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Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFN_e8_s24_50 : output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} inst mulAddRecFNToRaw_preMul of MulAddRecFNToRaw_preMul_e8_s24_50 inst mulAddRecFNToRaw_postMul of MulAddRecFNToRaw_postMul_e8_s24_50 connect mulAddRecFNToRaw_preMul.io.op, io.op connect mulAddRecFNToRaw_preMul.io.a, io.a connect mulAddRecFNToRaw_preMul.io.b, io.b connect mulAddRecFNToRaw_preMul.io.c, io.c node _mulAddResult_T = mul(mulAddRecFNToRaw_preMul.io.mulAddA, mulAddRecFNToRaw_preMul.io.mulAddB) node mulAddResult = add(_mulAddResult_T, mulAddRecFNToRaw_preMul.io.mulAddC) connect mulAddRecFNToRaw_postMul.io.fromPreMul.bit0AlignedSigC, mulAddRecFNToRaw_preMul.io.toPostMul.bit0AlignedSigC connect mulAddRecFNToRaw_postMul.io.fromPreMul.highAlignedSigC, mulAddRecFNToRaw_preMul.io.toPostMul.highAlignedSigC connect mulAddRecFNToRaw_postMul.io.fromPreMul.CDom_CAlignDist, mulAddRecFNToRaw_preMul.io.toPostMul.CDom_CAlignDist connect mulAddRecFNToRaw_postMul.io.fromPreMul.CIsDominant, mulAddRecFNToRaw_preMul.io.toPostMul.CIsDominant connect mulAddRecFNToRaw_postMul.io.fromPreMul.doSubMags, mulAddRecFNToRaw_preMul.io.toPostMul.doSubMags connect mulAddRecFNToRaw_postMul.io.fromPreMul.sExpSum, mulAddRecFNToRaw_preMul.io.toPostMul.sExpSum connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroC, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroC connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfC, mulAddRecFNToRaw_preMul.io.toPostMul.isInfC connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNC, mulAddRecFNToRaw_preMul.io.toPostMul.isNaNC connect mulAddRecFNToRaw_postMul.io.fromPreMul.signProd, mulAddRecFNToRaw_preMul.io.toPostMul.signProd connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroB, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfB, mulAddRecFNToRaw_preMul.io.toPostMul.isInfB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroA, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroA connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfA, mulAddRecFNToRaw_preMul.io.toPostMul.isInfA connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNAOrB, mulAddRecFNToRaw_preMul.io.toPostMul.isNaNAOrB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isSigNaNAny, mulAddRecFNToRaw_preMul.io.toPostMul.isSigNaNAny connect mulAddRecFNToRaw_postMul.io.mulAddResult, mulAddResult connect mulAddRecFNToRaw_postMul.io.roundingMode, io.roundingMode inst roundRawFNToRecFN of RoundRawFNToRecFN_e8_s24_70 connect roundRawFNToRecFN.io.invalidExc, mulAddRecFNToRaw_postMul.io.invalidExc connect roundRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect roundRawFNToRecFN.io.in.sig, mulAddRecFNToRaw_postMul.io.rawOut.sig connect roundRawFNToRecFN.io.in.sExp, mulAddRecFNToRaw_postMul.io.rawOut.sExp connect roundRawFNToRecFN.io.in.sign, mulAddRecFNToRaw_postMul.io.rawOut.sign connect roundRawFNToRecFN.io.in.isZero, mulAddRecFNToRaw_postMul.io.rawOut.isZero connect roundRawFNToRecFN.io.in.isInf, mulAddRecFNToRaw_postMul.io.rawOut.isInf connect roundRawFNToRecFN.io.in.isNaN, mulAddRecFNToRaw_postMul.io.rawOut.isNaN connect roundRawFNToRecFN.io.roundingMode, io.roundingMode connect roundRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundRawFNToRecFN.io.out connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags
module MulAddRecFN_e8_s24_50( // @[MulAddRecFN.scala:300:7] input [32:0] io_a, // @[MulAddRecFN.scala:303:16] input [32:0] io_c, // @[MulAddRecFN.scala:303:16] output [32:0] io_out // @[MulAddRecFN.scala:303:16] ); wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[MulAddRecFN.scala:319:15] wire [9:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[MulAddRecFN.scala:319:15] wire [26:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[MulAddRecFN.scala:319:15] wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddA; // @[MulAddRecFN.scala:317:15] wire [47:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[MulAddRecFN.scala:317:15] wire [9:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[MulAddRecFN.scala:317:15] wire [4:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[MulAddRecFN.scala:317:15] wire [25:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[MulAddRecFN.scala:317:15] wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:300:7] wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:300:7] wire io_detectTininess = 1'h1; // @[MulAddRecFN.scala:300:7, :303:16, :339:15] wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:300:7, :303:16, :319:15, :339:15] wire [32:0] io_b = 33'h80000000; // @[MulAddRecFN.scala:300:7, :303:16, :317:15] wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:300:7, :303:16, :317:15] wire [32:0] io_out_0; // @[MulAddRecFN.scala:300:7] wire [4:0] io_exceptionFlags; // @[MulAddRecFN.scala:300:7] wire [47:0] _mulAddResult_T = {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddA, 23'h0}; // @[MulAddRecFN.scala:317:15, :327:45] wire [48:0] mulAddResult = {1'h0, _mulAddResult_T} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[MulAddRecFN.scala:317:15, :327:45, :328:50] MulAddRecFNToRaw_preMul_e8_s24_50 mulAddRecFNToRaw_preMul ( // @[MulAddRecFN.scala:317:15] .io_a (io_a_0), // @[MulAddRecFN.scala:300:7] .io_c (io_c_0), // @[MulAddRecFN.scala:300:7] .io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA), .io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC), .io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), .io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), .io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), .io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), .io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), .io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), .io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), .io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), .io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), .io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), .io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), .io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), .io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), .io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC) ); // @[MulAddRecFN.scala:317:15] MulAddRecFNToRaw_postMul_e8_s24_50 mulAddRecFNToRaw_postMul ( // @[MulAddRecFN.scala:319:15] .io_fromPreMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC), // @[MulAddRecFN.scala:317:15] .io_mulAddResult (mulAddResult), // @[MulAddRecFN.scala:328:50] .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), .io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), .io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), .io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), .io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), .io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), .io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig) ); // @[MulAddRecFN.scala:319:15] RoundRawFNToRecFN_e8_s24_70 roundRawFNToRecFN ( // @[MulAddRecFN.scala:339:15] .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), // @[MulAddRecFN.scala:319:15] .io_in_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), // @[MulAddRecFN.scala:319:15] .io_in_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), // @[MulAddRecFN.scala:319:15] .io_in_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), // @[MulAddRecFN.scala:319:15] .io_in_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), // @[MulAddRecFN.scala:319:15] .io_in_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), // @[MulAddRecFN.scala:319:15] .io_in_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig), // @[MulAddRecFN.scala:319:15] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags) ); // @[MulAddRecFN.scala:339:15] assign io_out = io_out_0; // @[MulAddRecFN.scala:300:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_66 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T = shr(io.in.a.bits.source, 2) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<5>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 2, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 4, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<3>(0h5)) node mask_sub_sub_sub_sub_size = bits(mask_sizeOH, 4, 4) node mask_sub_sub_sub_sub_bit = bits(io.in.a.bits.address, 4, 4) node mask_sub_sub_sub_sub_nbit = eq(mask_sub_sub_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_sub_sub_nbit) node _mask_sub_sub_sub_sub_acc_T = and(mask_sub_sub_sub_sub_size, mask_sub_sub_sub_sub_0_2) node mask_sub_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_sub_acc_T) node mask_sub_sub_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_sub_sub_bit) node _mask_sub_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_sub_size, mask_sub_sub_sub_sub_1_2) node mask_sub_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_sub_acc_T_1) node mask_sub_sub_sub_size = bits(mask_sizeOH, 3, 3) node mask_sub_sub_sub_bit = bits(io.in.a.bits.address, 3, 3) node mask_sub_sub_sub_nbit = eq(mask_sub_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_sub_0_2 = and(mask_sub_sub_sub_sub_0_2, mask_sub_sub_sub_nbit) node _mask_sub_sub_sub_acc_T = and(mask_sub_sub_sub_size, mask_sub_sub_sub_0_2) node mask_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T) node mask_sub_sub_sub_1_2 = and(mask_sub_sub_sub_sub_0_2, mask_sub_sub_sub_bit) node _mask_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_1_2) node mask_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T_1) node mask_sub_sub_sub_2_2 = and(mask_sub_sub_sub_sub_1_2, mask_sub_sub_sub_nbit) node _mask_sub_sub_sub_acc_T_2 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_2_2) node mask_sub_sub_sub_2_1 = or(mask_sub_sub_sub_sub_1_1, _mask_sub_sub_sub_acc_T_2) node mask_sub_sub_sub_3_2 = and(mask_sub_sub_sub_sub_1_2, mask_sub_sub_sub_bit) node _mask_sub_sub_sub_acc_T_3 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_3_2) node mask_sub_sub_sub_3_1 = or(mask_sub_sub_sub_sub_1_1, _mask_sub_sub_sub_acc_T_3) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_sub_2_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size, mask_sub_sub_2_2) node mask_sub_sub_2_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_3_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size, mask_sub_sub_3_2) node mask_sub_sub_3_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_3) node mask_sub_sub_4_2 = and(mask_sub_sub_sub_2_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T_4 = and(mask_sub_sub_size, mask_sub_sub_4_2) node mask_sub_sub_4_1 = or(mask_sub_sub_sub_2_1, _mask_sub_sub_acc_T_4) node mask_sub_sub_5_2 = and(mask_sub_sub_sub_2_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_5 = and(mask_sub_sub_size, mask_sub_sub_5_2) node mask_sub_sub_5_1 = or(mask_sub_sub_sub_2_1, _mask_sub_sub_acc_T_5) node mask_sub_sub_6_2 = and(mask_sub_sub_sub_3_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T_6 = and(mask_sub_sub_size, mask_sub_sub_6_2) node mask_sub_sub_6_1 = or(mask_sub_sub_sub_3_1, _mask_sub_sub_acc_T_6) node mask_sub_sub_7_2 = and(mask_sub_sub_sub_3_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_7 = and(mask_sub_sub_size, mask_sub_sub_7_2) node mask_sub_sub_7_1 = or(mask_sub_sub_sub_3_1, _mask_sub_sub_acc_T_7) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_sub_4_2 = and(mask_sub_sub_2_2, mask_sub_nbit) node _mask_sub_acc_T_4 = and(mask_sub_size, mask_sub_4_2) node mask_sub_4_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_4) node mask_sub_5_2 = and(mask_sub_sub_2_2, mask_sub_bit) node _mask_sub_acc_T_5 = and(mask_sub_size, mask_sub_5_2) node mask_sub_5_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_5) node mask_sub_6_2 = and(mask_sub_sub_3_2, mask_sub_nbit) node _mask_sub_acc_T_6 = and(mask_sub_size, mask_sub_6_2) node mask_sub_6_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_6) node mask_sub_7_2 = and(mask_sub_sub_3_2, mask_sub_bit) node _mask_sub_acc_T_7 = and(mask_sub_size, mask_sub_7_2) node mask_sub_7_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_7) node mask_sub_8_2 = and(mask_sub_sub_4_2, mask_sub_nbit) node _mask_sub_acc_T_8 = and(mask_sub_size, mask_sub_8_2) node mask_sub_8_1 = or(mask_sub_sub_4_1, _mask_sub_acc_T_8) node mask_sub_9_2 = and(mask_sub_sub_4_2, mask_sub_bit) node _mask_sub_acc_T_9 = and(mask_sub_size, mask_sub_9_2) node mask_sub_9_1 = or(mask_sub_sub_4_1, _mask_sub_acc_T_9) node mask_sub_10_2 = and(mask_sub_sub_5_2, mask_sub_nbit) node _mask_sub_acc_T_10 = and(mask_sub_size, mask_sub_10_2) node mask_sub_10_1 = or(mask_sub_sub_5_1, _mask_sub_acc_T_10) node mask_sub_11_2 = and(mask_sub_sub_5_2, mask_sub_bit) node _mask_sub_acc_T_11 = and(mask_sub_size, mask_sub_11_2) node mask_sub_11_1 = or(mask_sub_sub_5_1, _mask_sub_acc_T_11) node mask_sub_12_2 = and(mask_sub_sub_6_2, mask_sub_nbit) node _mask_sub_acc_T_12 = and(mask_sub_size, mask_sub_12_2) node mask_sub_12_1 = or(mask_sub_sub_6_1, _mask_sub_acc_T_12) node mask_sub_13_2 = and(mask_sub_sub_6_2, mask_sub_bit) node _mask_sub_acc_T_13 = and(mask_sub_size, mask_sub_13_2) node mask_sub_13_1 = or(mask_sub_sub_6_1, _mask_sub_acc_T_13) node mask_sub_14_2 = and(mask_sub_sub_7_2, mask_sub_nbit) node _mask_sub_acc_T_14 = and(mask_sub_size, mask_sub_14_2) node mask_sub_14_1 = or(mask_sub_sub_7_1, _mask_sub_acc_T_14) node mask_sub_15_2 = and(mask_sub_sub_7_2, mask_sub_bit) node _mask_sub_acc_T_15 = and(mask_sub_size, mask_sub_15_2) node mask_sub_15_1 = or(mask_sub_sub_7_1, _mask_sub_acc_T_15) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_eq_8 = and(mask_sub_4_2, mask_nbit) node _mask_acc_T_8 = and(mask_size, mask_eq_8) node mask_acc_8 = or(mask_sub_4_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_4_2, mask_bit) node _mask_acc_T_9 = and(mask_size, mask_eq_9) node mask_acc_9 = or(mask_sub_4_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_5_2, mask_nbit) node _mask_acc_T_10 = and(mask_size, mask_eq_10) node mask_acc_10 = or(mask_sub_5_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_5_2, mask_bit) node _mask_acc_T_11 = and(mask_size, mask_eq_11) node mask_acc_11 = or(mask_sub_5_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_6_2, mask_nbit) node _mask_acc_T_12 = and(mask_size, mask_eq_12) node mask_acc_12 = or(mask_sub_6_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_6_2, mask_bit) node _mask_acc_T_13 = and(mask_size, mask_eq_13) node mask_acc_13 = or(mask_sub_6_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_7_2, mask_nbit) node _mask_acc_T_14 = and(mask_size, mask_eq_14) node mask_acc_14 = or(mask_sub_7_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_7_2, mask_bit) node _mask_acc_T_15 = and(mask_size, mask_eq_15) node mask_acc_15 = or(mask_sub_7_1, _mask_acc_T_15) node mask_eq_16 = and(mask_sub_8_2, mask_nbit) node _mask_acc_T_16 = and(mask_size, mask_eq_16) node mask_acc_16 = or(mask_sub_8_1, _mask_acc_T_16) node mask_eq_17 = and(mask_sub_8_2, mask_bit) node _mask_acc_T_17 = and(mask_size, mask_eq_17) node mask_acc_17 = or(mask_sub_8_1, _mask_acc_T_17) node mask_eq_18 = and(mask_sub_9_2, mask_nbit) node _mask_acc_T_18 = and(mask_size, mask_eq_18) node mask_acc_18 = or(mask_sub_9_1, _mask_acc_T_18) node mask_eq_19 = and(mask_sub_9_2, mask_bit) node _mask_acc_T_19 = and(mask_size, mask_eq_19) node mask_acc_19 = or(mask_sub_9_1, _mask_acc_T_19) node mask_eq_20 = and(mask_sub_10_2, mask_nbit) node _mask_acc_T_20 = and(mask_size, mask_eq_20) node mask_acc_20 = or(mask_sub_10_1, _mask_acc_T_20) node mask_eq_21 = and(mask_sub_10_2, mask_bit) node _mask_acc_T_21 = and(mask_size, mask_eq_21) node mask_acc_21 = or(mask_sub_10_1, _mask_acc_T_21) node mask_eq_22 = and(mask_sub_11_2, mask_nbit) node _mask_acc_T_22 = and(mask_size, mask_eq_22) node mask_acc_22 = or(mask_sub_11_1, _mask_acc_T_22) node mask_eq_23 = and(mask_sub_11_2, mask_bit) node _mask_acc_T_23 = and(mask_size, mask_eq_23) node mask_acc_23 = or(mask_sub_11_1, _mask_acc_T_23) node mask_eq_24 = and(mask_sub_12_2, mask_nbit) node _mask_acc_T_24 = and(mask_size, mask_eq_24) node mask_acc_24 = or(mask_sub_12_1, _mask_acc_T_24) node mask_eq_25 = and(mask_sub_12_2, mask_bit) node _mask_acc_T_25 = and(mask_size, mask_eq_25) node mask_acc_25 = or(mask_sub_12_1, _mask_acc_T_25) node mask_eq_26 = and(mask_sub_13_2, mask_nbit) node _mask_acc_T_26 = and(mask_size, mask_eq_26) node mask_acc_26 = or(mask_sub_13_1, _mask_acc_T_26) node mask_eq_27 = and(mask_sub_13_2, mask_bit) node _mask_acc_T_27 = and(mask_size, mask_eq_27) node mask_acc_27 = or(mask_sub_13_1, _mask_acc_T_27) node mask_eq_28 = and(mask_sub_14_2, mask_nbit) node _mask_acc_T_28 = and(mask_size, mask_eq_28) node mask_acc_28 = or(mask_sub_14_1, _mask_acc_T_28) node mask_eq_29 = and(mask_sub_14_2, mask_bit) node _mask_acc_T_29 = and(mask_size, mask_eq_29) node mask_acc_29 = or(mask_sub_14_1, _mask_acc_T_29) node mask_eq_30 = and(mask_sub_15_2, mask_nbit) node _mask_acc_T_30 = and(mask_size, mask_eq_30) node mask_acc_30 = or(mask_sub_15_1, _mask_acc_T_30) node mask_eq_31 = and(mask_sub_15_2, mask_bit) node _mask_acc_T_31 = and(mask_size, mask_eq_31) node mask_acc_31 = or(mask_sub_15_1, _mask_acc_T_31) node mask_lo_lo_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_lo_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo_lo_lo = cat(mask_lo_lo_lo_hi, mask_lo_lo_lo_lo) node mask_lo_lo_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_lo_lo_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_lo_lo_hi = cat(mask_lo_lo_hi_hi, mask_lo_lo_hi_lo) node mask_lo_lo = cat(mask_lo_lo_hi, mask_lo_lo_lo) node mask_lo_hi_lo_lo = cat(mask_acc_9, mask_acc_8) node mask_lo_hi_lo_hi = cat(mask_acc_11, mask_acc_10) node mask_lo_hi_lo = cat(mask_lo_hi_lo_hi, mask_lo_hi_lo_lo) node mask_lo_hi_hi_lo = cat(mask_acc_13, mask_acc_12) node mask_lo_hi_hi_hi = cat(mask_acc_15, mask_acc_14) node mask_lo_hi_hi = cat(mask_lo_hi_hi_hi, mask_lo_hi_hi_lo) node mask_lo_hi = cat(mask_lo_hi_hi, mask_lo_hi_lo) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo_lo_lo = cat(mask_acc_17, mask_acc_16) node mask_hi_lo_lo_hi = cat(mask_acc_19, mask_acc_18) node mask_hi_lo_lo = cat(mask_hi_lo_lo_hi, mask_hi_lo_lo_lo) node mask_hi_lo_hi_lo = cat(mask_acc_21, mask_acc_20) node mask_hi_lo_hi_hi = cat(mask_acc_23, mask_acc_22) node mask_hi_lo_hi = cat(mask_hi_lo_hi_hi, mask_hi_lo_hi_lo) node mask_hi_lo = cat(mask_hi_lo_hi, mask_hi_lo_lo) node mask_hi_hi_lo_lo = cat(mask_acc_25, mask_acc_24) node mask_hi_hi_lo_hi = cat(mask_acc_27, mask_acc_26) node mask_hi_hi_lo = cat(mask_hi_hi_lo_hi, mask_hi_hi_lo_lo) node mask_hi_hi_hi_lo = cat(mask_acc_29, mask_acc_28) node mask_hi_hi_hi_hi = cat(mask_acc_31, mask_acc_30) node mask_hi_hi_hi = cat(mask_hi_hi_hi_hi, mask_hi_hi_hi_lo) node mask_hi_hi = cat(mask_hi_hi_hi, mask_hi_hi_lo) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_4 = shr(io.in.a.bits.source, 2) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<2>(0h3)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_24 = shr(io.in.a.bits.source, 2) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<14>(0h2000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<13>(0h1000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<18>(0h2f000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<17>(0h10000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_64 = cvt(_T_63) node _T_65 = and(_T_64, asSInt(UInt<27>(0h4000000))) node _T_66 = asSInt(_T_65) node _T_67 = eq(_T_66, asSInt(UInt<1>(0h0))) node _T_68 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_69 = cvt(_T_68) node _T_70 = and(_T_69, asSInt(UInt<13>(0h1000))) node _T_71 = asSInt(_T_70) node _T_72 = eq(_T_71, asSInt(UInt<1>(0h0))) node _T_73 = or(_T_37, _T_42) node _T_74 = or(_T_73, _T_47) node _T_75 = or(_T_74, _T_52) node _T_76 = or(_T_75, _T_57) node _T_77 = or(_T_76, _T_62) node _T_78 = or(_T_77, _T_67) node _T_79 = or(_T_78, _T_72) node _T_80 = and(_T_32, _T_79) node _T_81 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_82 = or(UInt<1>(0h0), _T_81) node _T_83 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_84 = cvt(_T_83) node _T_85 = and(_T_84, asSInt(UInt<17>(0h10000))) node _T_86 = asSInt(_T_85) node _T_87 = eq(_T_86, asSInt(UInt<1>(0h0))) node _T_88 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_89 = cvt(_T_88) node _T_90 = and(_T_89, asSInt(UInt<29>(0h10000000))) node _T_91 = asSInt(_T_90) node _T_92 = eq(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = or(_T_87, _T_92) node _T_94 = and(_T_82, _T_93) node _T_95 = or(UInt<1>(0h0), _T_80) node _T_96 = or(_T_95, _T_94) node _T_97 = and(_T_31, _T_96) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_97, UInt<1>(0h1), "") : assert_2 node _T_101 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_102 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_103 = and(_T_101, _T_102) node _T_104 = or(UInt<1>(0h0), _T_103) node _T_105 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<14>(0h2000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_116 = cvt(_T_115) node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000))) node _T_118 = asSInt(_T_117) node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0))) node _T_120 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_121 = cvt(_T_120) node _T_122 = and(_T_121, asSInt(UInt<18>(0h2f000))) node _T_123 = asSInt(_T_122) node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_126 = cvt(_T_125) node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000))) node _T_128 = asSInt(_T_127) node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0))) node _T_130 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<13>(0h1000))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_136 = cvt(_T_135) node _T_137 = and(_T_136, asSInt(UInt<17>(0h10000))) node _T_138 = asSInt(_T_137) node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0))) node _T_140 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<27>(0h4000000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_146 = cvt(_T_145) node _T_147 = and(_T_146, asSInt(UInt<13>(0h1000))) node _T_148 = asSInt(_T_147) node _T_149 = eq(_T_148, asSInt(UInt<1>(0h0))) node _T_150 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_151 = cvt(_T_150) node _T_152 = and(_T_151, asSInt(UInt<29>(0h10000000))) node _T_153 = asSInt(_T_152) node _T_154 = eq(_T_153, asSInt(UInt<1>(0h0))) node _T_155 = or(_T_109, _T_114) node _T_156 = or(_T_155, _T_119) node _T_157 = or(_T_156, _T_124) node _T_158 = or(_T_157, _T_129) node _T_159 = or(_T_158, _T_134) node _T_160 = or(_T_159, _T_139) node _T_161 = or(_T_160, _T_144) node _T_162 = or(_T_161, _T_149) node _T_163 = or(_T_162, _T_154) node _T_164 = and(_T_104, _T_163) node _T_165 = or(UInt<1>(0h0), _T_164) node _T_166 = and(UInt<1>(0h0), _T_165) node _T_167 = asUInt(reset) node _T_168 = eq(_T_167, UInt<1>(0h0)) when _T_168 : node _T_169 = eq(_T_166, UInt<1>(0h0)) when _T_169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_166, UInt<1>(0h1), "") : assert_3 node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_173 = geq(io.in.a.bits.size, UInt<3>(0h5)) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_173, UInt<1>(0h1), "") : assert_5 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(is_aligned, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_180 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_181 = asUInt(reset) node _T_182 = eq(_T_181, UInt<1>(0h0)) when _T_182 : node _T_183 = eq(_T_180, UInt<1>(0h0)) when _T_183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_180, UInt<1>(0h1), "") : assert_7 node _T_184 = not(io.in.a.bits.mask) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = asUInt(reset) node _T_187 = eq(_T_186, UInt<1>(0h0)) when _T_187 : node _T_188 = eq(_T_185, UInt<1>(0h0)) when _T_188 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_185, UInt<1>(0h1), "") : assert_8 node _T_189 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_190 = asUInt(reset) node _T_191 = eq(_T_190, UInt<1>(0h0)) when _T_191 : node _T_192 = eq(_T_189, UInt<1>(0h0)) when _T_192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_189, UInt<1>(0h1), "") : assert_9 node _T_193 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_193 : node _T_194 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_195 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_196 = and(_T_194, _T_195) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_197 = shr(io.in.a.bits.source, 2) node _T_198 = eq(_T_197, UInt<1>(0h0)) node _T_199 = leq(UInt<1>(0h0), uncommonBits_2) node _T_200 = and(_T_198, _T_199) node _T_201 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_202 = and(_T_200, _T_201) node _T_203 = and(_T_196, _T_202) node _T_204 = or(UInt<1>(0h0), _T_203) node _T_205 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_206 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<14>(0h2000))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_217 = cvt(_T_216) node _T_218 = and(_T_217, asSInt(UInt<17>(0h10000))) node _T_219 = asSInt(_T_218) node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<18>(0h2f000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<17>(0h10000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_232 = cvt(_T_231) node _T_233 = and(_T_232, asSInt(UInt<13>(0h1000))) node _T_234 = asSInt(_T_233) node _T_235 = eq(_T_234, asSInt(UInt<1>(0h0))) node _T_236 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_237 = cvt(_T_236) node _T_238 = and(_T_237, asSInt(UInt<27>(0h4000000))) node _T_239 = asSInt(_T_238) node _T_240 = eq(_T_239, asSInt(UInt<1>(0h0))) node _T_241 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<13>(0h1000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = or(_T_210, _T_215) node _T_247 = or(_T_246, _T_220) node _T_248 = or(_T_247, _T_225) node _T_249 = or(_T_248, _T_230) node _T_250 = or(_T_249, _T_235) node _T_251 = or(_T_250, _T_240) node _T_252 = or(_T_251, _T_245) node _T_253 = and(_T_205, _T_252) node _T_254 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_255 = or(UInt<1>(0h0), _T_254) node _T_256 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_257 = cvt(_T_256) node _T_258 = and(_T_257, asSInt(UInt<17>(0h10000))) node _T_259 = asSInt(_T_258) node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_262 = cvt(_T_261) node _T_263 = and(_T_262, asSInt(UInt<29>(0h10000000))) node _T_264 = asSInt(_T_263) node _T_265 = eq(_T_264, asSInt(UInt<1>(0h0))) node _T_266 = or(_T_260, _T_265) node _T_267 = and(_T_255, _T_266) node _T_268 = or(UInt<1>(0h0), _T_253) node _T_269 = or(_T_268, _T_267) node _T_270 = and(_T_204, _T_269) node _T_271 = asUInt(reset) node _T_272 = eq(_T_271, UInt<1>(0h0)) when _T_272 : node _T_273 = eq(_T_270, UInt<1>(0h0)) when _T_273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_270, UInt<1>(0h1), "") : assert_10 node _T_274 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_275 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_276 = and(_T_274, _T_275) node _T_277 = or(UInt<1>(0h0), _T_276) node _T_278 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<14>(0h2000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<13>(0h1000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<17>(0h10000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<18>(0h2f000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<17>(0h10000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<17>(0h10000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_314 = cvt(_T_313) node _T_315 = and(_T_314, asSInt(UInt<27>(0h4000000))) node _T_316 = asSInt(_T_315) node _T_317 = eq(_T_316, asSInt(UInt<1>(0h0))) node _T_318 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_319 = cvt(_T_318) node _T_320 = and(_T_319, asSInt(UInt<13>(0h1000))) node _T_321 = asSInt(_T_320) node _T_322 = eq(_T_321, asSInt(UInt<1>(0h0))) node _T_323 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_324 = cvt(_T_323) node _T_325 = and(_T_324, asSInt(UInt<29>(0h10000000))) node _T_326 = asSInt(_T_325) node _T_327 = eq(_T_326, asSInt(UInt<1>(0h0))) node _T_328 = or(_T_282, _T_287) node _T_329 = or(_T_328, _T_292) node _T_330 = or(_T_329, _T_297) node _T_331 = or(_T_330, _T_302) node _T_332 = or(_T_331, _T_307) node _T_333 = or(_T_332, _T_312) node _T_334 = or(_T_333, _T_317) node _T_335 = or(_T_334, _T_322) node _T_336 = or(_T_335, _T_327) node _T_337 = and(_T_277, _T_336) node _T_338 = or(UInt<1>(0h0), _T_337) node _T_339 = and(UInt<1>(0h0), _T_338) node _T_340 = asUInt(reset) node _T_341 = eq(_T_340, UInt<1>(0h0)) when _T_341 : node _T_342 = eq(_T_339, UInt<1>(0h0)) when _T_342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_339, UInt<1>(0h1), "") : assert_11 node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_346 = geq(io.in.a.bits.size, UInt<3>(0h5)) node _T_347 = asUInt(reset) node _T_348 = eq(_T_347, UInt<1>(0h0)) when _T_348 : node _T_349 = eq(_T_346, UInt<1>(0h0)) when _T_349 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_346, UInt<1>(0h1), "") : assert_13 node _T_350 = asUInt(reset) node _T_351 = eq(_T_350, UInt<1>(0h0)) when _T_351 : node _T_352 = eq(is_aligned, UInt<1>(0h0)) when _T_352 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_353 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_354 = asUInt(reset) node _T_355 = eq(_T_354, UInt<1>(0h0)) when _T_355 : node _T_356 = eq(_T_353, UInt<1>(0h0)) when _T_356 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_353, UInt<1>(0h1), "") : assert_15 node _T_357 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_358 = asUInt(reset) node _T_359 = eq(_T_358, UInt<1>(0h0)) when _T_359 : node _T_360 = eq(_T_357, UInt<1>(0h0)) when _T_360 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_357, UInt<1>(0h1), "") : assert_16 node _T_361 = not(io.in.a.bits.mask) node _T_362 = eq(_T_361, UInt<1>(0h0)) node _T_363 = asUInt(reset) node _T_364 = eq(_T_363, UInt<1>(0h0)) when _T_364 : node _T_365 = eq(_T_362, UInt<1>(0h0)) when _T_365 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_362, UInt<1>(0h1), "") : assert_17 node _T_366 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_366, UInt<1>(0h1), "") : assert_18 node _T_370 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_370 : node _T_371 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_372 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_373 = and(_T_371, _T_372) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_374 = shr(io.in.a.bits.source, 2) node _T_375 = eq(_T_374, UInt<1>(0h0)) node _T_376 = leq(UInt<1>(0h0), uncommonBits_3) node _T_377 = and(_T_375, _T_376) node _T_378 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_379 = and(_T_377, _T_378) node _T_380 = and(_T_373, _T_379) node _T_381 = or(UInt<1>(0h0), _T_380) node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(_T_381, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_381, UInt<1>(0h1), "") : assert_19 node _T_385 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_386 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_387 = and(_T_385, _T_386) node _T_388 = or(UInt<1>(0h0), _T_387) node _T_389 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<13>(0h1000))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = and(_T_388, _T_393) node _T_395 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_396 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_397 = and(_T_395, _T_396) node _T_398 = or(UInt<1>(0h0), _T_397) node _T_399 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<14>(0h2000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<18>(0h2f000))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<17>(0h10000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<13>(0h1000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_425 = cvt(_T_424) node _T_426 = and(_T_425, asSInt(UInt<17>(0h10000))) node _T_427 = asSInt(_T_426) node _T_428 = eq(_T_427, asSInt(UInt<1>(0h0))) node _T_429 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_430 = cvt(_T_429) node _T_431 = and(_T_430, asSInt(UInt<27>(0h4000000))) node _T_432 = asSInt(_T_431) node _T_433 = eq(_T_432, asSInt(UInt<1>(0h0))) node _T_434 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_435 = cvt(_T_434) node _T_436 = and(_T_435, asSInt(UInt<13>(0h1000))) node _T_437 = asSInt(_T_436) node _T_438 = eq(_T_437, asSInt(UInt<1>(0h0))) node _T_439 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_440 = cvt(_T_439) node _T_441 = and(_T_440, asSInt(UInt<29>(0h10000000))) node _T_442 = asSInt(_T_441) node _T_443 = eq(_T_442, asSInt(UInt<1>(0h0))) node _T_444 = or(_T_403, _T_408) node _T_445 = or(_T_444, _T_413) node _T_446 = or(_T_445, _T_418) node _T_447 = or(_T_446, _T_423) node _T_448 = or(_T_447, _T_428) node _T_449 = or(_T_448, _T_433) node _T_450 = or(_T_449, _T_438) node _T_451 = or(_T_450, _T_443) node _T_452 = and(_T_398, _T_451) node _T_453 = or(UInt<1>(0h0), _T_394) node _T_454 = or(_T_453, _T_452) node _T_455 = asUInt(reset) node _T_456 = eq(_T_455, UInt<1>(0h0)) when _T_456 : node _T_457 = eq(_T_454, UInt<1>(0h0)) when _T_457 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_454, UInt<1>(0h1), "") : assert_20 node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(is_aligned, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_464 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_464, UInt<1>(0h1), "") : assert_23 node _T_468 = eq(io.in.a.bits.mask, mask) node _T_469 = asUInt(reset) node _T_470 = eq(_T_469, UInt<1>(0h0)) when _T_470 : node _T_471 = eq(_T_468, UInt<1>(0h0)) when _T_471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_468, UInt<1>(0h1), "") : assert_24 node _T_472 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_473 = asUInt(reset) node _T_474 = eq(_T_473, UInt<1>(0h0)) when _T_474 : node _T_475 = eq(_T_472, UInt<1>(0h0)) when _T_475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_472, UInt<1>(0h1), "") : assert_25 node _T_476 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_476 : node _T_477 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_478 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_479 = and(_T_477, _T_478) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_480 = shr(io.in.a.bits.source, 2) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = leq(UInt<1>(0h0), uncommonBits_4) node _T_483 = and(_T_481, _T_482) node _T_484 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_485 = and(_T_483, _T_484) node _T_486 = and(_T_479, _T_485) node _T_487 = or(UInt<1>(0h0), _T_486) node _T_488 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_489 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_490 = and(_T_488, _T_489) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = and(_T_491, _T_496) node _T_498 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_499 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_500 = and(_T_498, _T_499) node _T_501 = or(UInt<1>(0h0), _T_500) node _T_502 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_503 = cvt(_T_502) node _T_504 = and(_T_503, asSInt(UInt<14>(0h2000))) node _T_505 = asSInt(_T_504) node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0))) node _T_507 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<18>(0h2f000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<17>(0h10000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_518 = cvt(_T_517) node _T_519 = and(_T_518, asSInt(UInt<13>(0h1000))) node _T_520 = asSInt(_T_519) node _T_521 = eq(_T_520, asSInt(UInt<1>(0h0))) node _T_522 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_523 = cvt(_T_522) node _T_524 = and(_T_523, asSInt(UInt<17>(0h10000))) node _T_525 = asSInt(_T_524) node _T_526 = eq(_T_525, asSInt(UInt<1>(0h0))) node _T_527 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_528 = cvt(_T_527) node _T_529 = and(_T_528, asSInt(UInt<27>(0h4000000))) node _T_530 = asSInt(_T_529) node _T_531 = eq(_T_530, asSInt(UInt<1>(0h0))) node _T_532 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_533 = cvt(_T_532) node _T_534 = and(_T_533, asSInt(UInt<13>(0h1000))) node _T_535 = asSInt(_T_534) node _T_536 = eq(_T_535, asSInt(UInt<1>(0h0))) node _T_537 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_538 = cvt(_T_537) node _T_539 = and(_T_538, asSInt(UInt<29>(0h10000000))) node _T_540 = asSInt(_T_539) node _T_541 = eq(_T_540, asSInt(UInt<1>(0h0))) node _T_542 = or(_T_506, _T_511) node _T_543 = or(_T_542, _T_516) node _T_544 = or(_T_543, _T_521) node _T_545 = or(_T_544, _T_526) node _T_546 = or(_T_545, _T_531) node _T_547 = or(_T_546, _T_536) node _T_548 = or(_T_547, _T_541) node _T_549 = and(_T_501, _T_548) node _T_550 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_551 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_552 = cvt(_T_551) node _T_553 = and(_T_552, asSInt(UInt<17>(0h10000))) node _T_554 = asSInt(_T_553) node _T_555 = eq(_T_554, asSInt(UInt<1>(0h0))) node _T_556 = and(_T_550, _T_555) node _T_557 = or(UInt<1>(0h0), _T_497) node _T_558 = or(_T_557, _T_549) node _T_559 = or(_T_558, _T_556) node _T_560 = and(_T_487, _T_559) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_560, UInt<1>(0h1), "") : assert_26 node _T_564 = asUInt(reset) node _T_565 = eq(_T_564, UInt<1>(0h0)) when _T_565 : node _T_566 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_567 = asUInt(reset) node _T_568 = eq(_T_567, UInt<1>(0h0)) when _T_568 : node _T_569 = eq(is_aligned, UInt<1>(0h0)) when _T_569 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_570 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_571 = asUInt(reset) node _T_572 = eq(_T_571, UInt<1>(0h0)) when _T_572 : node _T_573 = eq(_T_570, UInt<1>(0h0)) when _T_573 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_570, UInt<1>(0h1), "") : assert_29 node _T_574 = eq(io.in.a.bits.mask, mask) node _T_575 = asUInt(reset) node _T_576 = eq(_T_575, UInt<1>(0h0)) when _T_576 : node _T_577 = eq(_T_574, UInt<1>(0h0)) when _T_577 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_574, UInt<1>(0h1), "") : assert_30 node _T_578 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_578 : node _T_579 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_580 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_581 = and(_T_579, _T_580) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_582 = shr(io.in.a.bits.source, 2) node _T_583 = eq(_T_582, UInt<1>(0h0)) node _T_584 = leq(UInt<1>(0h0), uncommonBits_5) node _T_585 = and(_T_583, _T_584) node _T_586 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_587 = and(_T_585, _T_586) node _T_588 = and(_T_581, _T_587) node _T_589 = or(UInt<1>(0h0), _T_588) node _T_590 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_591 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_592 = and(_T_590, _T_591) node _T_593 = or(UInt<1>(0h0), _T_592) node _T_594 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<13>(0h1000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = and(_T_593, _T_598) node _T_600 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_601 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_602 = and(_T_600, _T_601) node _T_603 = or(UInt<1>(0h0), _T_602) node _T_604 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_605 = cvt(_T_604) node _T_606 = and(_T_605, asSInt(UInt<14>(0h2000))) node _T_607 = asSInt(_T_606) node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0))) node _T_609 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<18>(0h2f000))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_615 = cvt(_T_614) node _T_616 = and(_T_615, asSInt(UInt<17>(0h10000))) node _T_617 = asSInt(_T_616) node _T_618 = eq(_T_617, asSInt(UInt<1>(0h0))) node _T_619 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_620 = cvt(_T_619) node _T_621 = and(_T_620, asSInt(UInt<13>(0h1000))) node _T_622 = asSInt(_T_621) node _T_623 = eq(_T_622, asSInt(UInt<1>(0h0))) node _T_624 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_625 = cvt(_T_624) node _T_626 = and(_T_625, asSInt(UInt<17>(0h10000))) node _T_627 = asSInt(_T_626) node _T_628 = eq(_T_627, asSInt(UInt<1>(0h0))) node _T_629 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_630 = cvt(_T_629) node _T_631 = and(_T_630, asSInt(UInt<27>(0h4000000))) node _T_632 = asSInt(_T_631) node _T_633 = eq(_T_632, asSInt(UInt<1>(0h0))) node _T_634 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_635 = cvt(_T_634) node _T_636 = and(_T_635, asSInt(UInt<13>(0h1000))) node _T_637 = asSInt(_T_636) node _T_638 = eq(_T_637, asSInt(UInt<1>(0h0))) node _T_639 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_640 = cvt(_T_639) node _T_641 = and(_T_640, asSInt(UInt<29>(0h10000000))) node _T_642 = asSInt(_T_641) node _T_643 = eq(_T_642, asSInt(UInt<1>(0h0))) node _T_644 = or(_T_608, _T_613) node _T_645 = or(_T_644, _T_618) node _T_646 = or(_T_645, _T_623) node _T_647 = or(_T_646, _T_628) node _T_648 = or(_T_647, _T_633) node _T_649 = or(_T_648, _T_638) node _T_650 = or(_T_649, _T_643) node _T_651 = and(_T_603, _T_650) node _T_652 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_653 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_654 = cvt(_T_653) node _T_655 = and(_T_654, asSInt(UInt<17>(0h10000))) node _T_656 = asSInt(_T_655) node _T_657 = eq(_T_656, asSInt(UInt<1>(0h0))) node _T_658 = and(_T_652, _T_657) node _T_659 = or(UInt<1>(0h0), _T_599) node _T_660 = or(_T_659, _T_651) node _T_661 = or(_T_660, _T_658) node _T_662 = and(_T_589, _T_661) node _T_663 = asUInt(reset) node _T_664 = eq(_T_663, UInt<1>(0h0)) when _T_664 : node _T_665 = eq(_T_662, UInt<1>(0h0)) when _T_665 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_662, UInt<1>(0h1), "") : assert_31 node _T_666 = asUInt(reset) node _T_667 = eq(_T_666, UInt<1>(0h0)) when _T_667 : node _T_668 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_668 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(is_aligned, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_672 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_673 = asUInt(reset) node _T_674 = eq(_T_673, UInt<1>(0h0)) when _T_674 : node _T_675 = eq(_T_672, UInt<1>(0h0)) when _T_675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_672, UInt<1>(0h1), "") : assert_34 node _T_676 = not(mask) node _T_677 = and(io.in.a.bits.mask, _T_676) node _T_678 = eq(_T_677, UInt<1>(0h0)) node _T_679 = asUInt(reset) node _T_680 = eq(_T_679, UInt<1>(0h0)) when _T_680 : node _T_681 = eq(_T_678, UInt<1>(0h0)) when _T_681 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_678, UInt<1>(0h1), "") : assert_35 node _T_682 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_682 : node _T_683 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_684 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_685 = and(_T_683, _T_684) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_686 = shr(io.in.a.bits.source, 2) node _T_687 = eq(_T_686, UInt<1>(0h0)) node _T_688 = leq(UInt<1>(0h0), uncommonBits_6) node _T_689 = and(_T_687, _T_688) node _T_690 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_691 = and(_T_689, _T_690) node _T_692 = and(_T_685, _T_691) node _T_693 = or(UInt<1>(0h0), _T_692) node _T_694 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_695 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_696 = and(_T_694, _T_695) node _T_697 = or(UInt<1>(0h0), _T_696) node _T_698 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_699 = cvt(_T_698) node _T_700 = and(_T_699, asSInt(UInt<14>(0h2000))) node _T_701 = asSInt(_T_700) node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0))) node _T_703 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_704 = cvt(_T_703) node _T_705 = and(_T_704, asSInt(UInt<13>(0h1000))) node _T_706 = asSInt(_T_705) node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0))) node _T_708 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_709 = cvt(_T_708) node _T_710 = and(_T_709, asSInt(UInt<18>(0h2f000))) node _T_711 = asSInt(_T_710) node _T_712 = eq(_T_711, asSInt(UInt<1>(0h0))) node _T_713 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_714 = cvt(_T_713) node _T_715 = and(_T_714, asSInt(UInt<17>(0h10000))) node _T_716 = asSInt(_T_715) node _T_717 = eq(_T_716, asSInt(UInt<1>(0h0))) node _T_718 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_719 = cvt(_T_718) node _T_720 = and(_T_719, asSInt(UInt<13>(0h1000))) node _T_721 = asSInt(_T_720) node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0))) node _T_723 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_724 = cvt(_T_723) node _T_725 = and(_T_724, asSInt(UInt<17>(0h10000))) node _T_726 = asSInt(_T_725) node _T_727 = eq(_T_726, asSInt(UInt<1>(0h0))) node _T_728 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_729 = cvt(_T_728) node _T_730 = and(_T_729, asSInt(UInt<27>(0h4000000))) node _T_731 = asSInt(_T_730) node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0))) node _T_733 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_734 = cvt(_T_733) node _T_735 = and(_T_734, asSInt(UInt<13>(0h1000))) node _T_736 = asSInt(_T_735) node _T_737 = eq(_T_736, asSInt(UInt<1>(0h0))) node _T_738 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_739 = cvt(_T_738) node _T_740 = and(_T_739, asSInt(UInt<29>(0h10000000))) node _T_741 = asSInt(_T_740) node _T_742 = eq(_T_741, asSInt(UInt<1>(0h0))) node _T_743 = or(_T_702, _T_707) node _T_744 = or(_T_743, _T_712) node _T_745 = or(_T_744, _T_717) node _T_746 = or(_T_745, _T_722) node _T_747 = or(_T_746, _T_727) node _T_748 = or(_T_747, _T_732) node _T_749 = or(_T_748, _T_737) node _T_750 = or(_T_749, _T_742) node _T_751 = and(_T_697, _T_750) node _T_752 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_753 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_754 = cvt(_T_753) node _T_755 = and(_T_754, asSInt(UInt<17>(0h10000))) node _T_756 = asSInt(_T_755) node _T_757 = eq(_T_756, asSInt(UInt<1>(0h0))) node _T_758 = and(_T_752, _T_757) node _T_759 = or(UInt<1>(0h0), _T_751) node _T_760 = or(_T_759, _T_758) node _T_761 = and(_T_693, _T_760) node _T_762 = asUInt(reset) node _T_763 = eq(_T_762, UInt<1>(0h0)) when _T_763 : node _T_764 = eq(_T_761, UInt<1>(0h0)) when _T_764 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_761, UInt<1>(0h1), "") : assert_36 node _T_765 = asUInt(reset) node _T_766 = eq(_T_765, UInt<1>(0h0)) when _T_766 : node _T_767 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_767 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_768 = asUInt(reset) node _T_769 = eq(_T_768, UInt<1>(0h0)) when _T_769 : node _T_770 = eq(is_aligned, UInt<1>(0h0)) when _T_770 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_771 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_772 = asUInt(reset) node _T_773 = eq(_T_772, UInt<1>(0h0)) when _T_773 : node _T_774 = eq(_T_771, UInt<1>(0h0)) when _T_774 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_771, UInt<1>(0h1), "") : assert_39 node _T_775 = eq(io.in.a.bits.mask, mask) node _T_776 = asUInt(reset) node _T_777 = eq(_T_776, UInt<1>(0h0)) when _T_777 : node _T_778 = eq(_T_775, UInt<1>(0h0)) when _T_778 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_775, UInt<1>(0h1), "") : assert_40 node _T_779 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_779 : node _T_780 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_781 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_782 = and(_T_780, _T_781) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_783 = shr(io.in.a.bits.source, 2) node _T_784 = eq(_T_783, UInt<1>(0h0)) node _T_785 = leq(UInt<1>(0h0), uncommonBits_7) node _T_786 = and(_T_784, _T_785) node _T_787 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_788 = and(_T_786, _T_787) node _T_789 = and(_T_782, _T_788) node _T_790 = or(UInt<1>(0h0), _T_789) node _T_791 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_792 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_793 = and(_T_791, _T_792) node _T_794 = or(UInt<1>(0h0), _T_793) node _T_795 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_796 = cvt(_T_795) node _T_797 = and(_T_796, asSInt(UInt<14>(0h2000))) node _T_798 = asSInt(_T_797) node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0))) node _T_800 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_801 = cvt(_T_800) node _T_802 = and(_T_801, asSInt(UInt<13>(0h1000))) node _T_803 = asSInt(_T_802) node _T_804 = eq(_T_803, asSInt(UInt<1>(0h0))) node _T_805 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_806 = cvt(_T_805) node _T_807 = and(_T_806, asSInt(UInt<18>(0h2f000))) node _T_808 = asSInt(_T_807) node _T_809 = eq(_T_808, asSInt(UInt<1>(0h0))) node _T_810 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_811 = cvt(_T_810) node _T_812 = and(_T_811, asSInt(UInt<17>(0h10000))) node _T_813 = asSInt(_T_812) node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0))) node _T_815 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_816 = cvt(_T_815) node _T_817 = and(_T_816, asSInt(UInt<13>(0h1000))) node _T_818 = asSInt(_T_817) node _T_819 = eq(_T_818, asSInt(UInt<1>(0h0))) node _T_820 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_821 = cvt(_T_820) node _T_822 = and(_T_821, asSInt(UInt<17>(0h10000))) node _T_823 = asSInt(_T_822) node _T_824 = eq(_T_823, asSInt(UInt<1>(0h0))) node _T_825 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_826 = cvt(_T_825) node _T_827 = and(_T_826, asSInt(UInt<27>(0h4000000))) node _T_828 = asSInt(_T_827) node _T_829 = eq(_T_828, asSInt(UInt<1>(0h0))) node _T_830 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_831 = cvt(_T_830) node _T_832 = and(_T_831, asSInt(UInt<13>(0h1000))) node _T_833 = asSInt(_T_832) node _T_834 = eq(_T_833, asSInt(UInt<1>(0h0))) node _T_835 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_836 = cvt(_T_835) node _T_837 = and(_T_836, asSInt(UInt<29>(0h10000000))) node _T_838 = asSInt(_T_837) node _T_839 = eq(_T_838, asSInt(UInt<1>(0h0))) node _T_840 = or(_T_799, _T_804) node _T_841 = or(_T_840, _T_809) node _T_842 = or(_T_841, _T_814) node _T_843 = or(_T_842, _T_819) node _T_844 = or(_T_843, _T_824) node _T_845 = or(_T_844, _T_829) node _T_846 = or(_T_845, _T_834) node _T_847 = or(_T_846, _T_839) node _T_848 = and(_T_794, _T_847) node _T_849 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_850 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_851 = cvt(_T_850) node _T_852 = and(_T_851, asSInt(UInt<17>(0h10000))) node _T_853 = asSInt(_T_852) node _T_854 = eq(_T_853, asSInt(UInt<1>(0h0))) node _T_855 = and(_T_849, _T_854) node _T_856 = or(UInt<1>(0h0), _T_848) node _T_857 = or(_T_856, _T_855) node _T_858 = and(_T_790, _T_857) node _T_859 = asUInt(reset) node _T_860 = eq(_T_859, UInt<1>(0h0)) when _T_860 : node _T_861 = eq(_T_858, UInt<1>(0h0)) when _T_861 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_858, UInt<1>(0h1), "") : assert_41 node _T_862 = asUInt(reset) node _T_863 = eq(_T_862, UInt<1>(0h0)) when _T_863 : node _T_864 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_865 = asUInt(reset) node _T_866 = eq(_T_865, UInt<1>(0h0)) when _T_866 : node _T_867 = eq(is_aligned, UInt<1>(0h0)) when _T_867 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_868 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_869 = asUInt(reset) node _T_870 = eq(_T_869, UInt<1>(0h0)) when _T_870 : node _T_871 = eq(_T_868, UInt<1>(0h0)) when _T_871 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_868, UInt<1>(0h1), "") : assert_44 node _T_872 = eq(io.in.a.bits.mask, mask) node _T_873 = asUInt(reset) node _T_874 = eq(_T_873, UInt<1>(0h0)) when _T_874 : node _T_875 = eq(_T_872, UInt<1>(0h0)) when _T_875 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_872, UInt<1>(0h1), "") : assert_45 node _T_876 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_876 : node _T_877 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_878 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_879 = and(_T_877, _T_878) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_880 = shr(io.in.a.bits.source, 2) node _T_881 = eq(_T_880, UInt<1>(0h0)) node _T_882 = leq(UInt<1>(0h0), uncommonBits_8) node _T_883 = and(_T_881, _T_882) node _T_884 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_885 = and(_T_883, _T_884) node _T_886 = and(_T_879, _T_885) node _T_887 = or(UInt<1>(0h0), _T_886) node _T_888 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_889 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_890 = and(_T_888, _T_889) node _T_891 = or(UInt<1>(0h0), _T_890) node _T_892 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_893 = cvt(_T_892) node _T_894 = and(_T_893, asSInt(UInt<13>(0h1000))) node _T_895 = asSInt(_T_894) node _T_896 = eq(_T_895, asSInt(UInt<1>(0h0))) node _T_897 = and(_T_891, _T_896) node _T_898 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_899 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_900 = cvt(_T_899) node _T_901 = and(_T_900, asSInt(UInt<14>(0h2000))) node _T_902 = asSInt(_T_901) node _T_903 = eq(_T_902, asSInt(UInt<1>(0h0))) node _T_904 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_905 = cvt(_T_904) node _T_906 = and(_T_905, asSInt(UInt<17>(0h10000))) node _T_907 = asSInt(_T_906) node _T_908 = eq(_T_907, asSInt(UInt<1>(0h0))) node _T_909 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_910 = cvt(_T_909) node _T_911 = and(_T_910, asSInt(UInt<18>(0h2f000))) node _T_912 = asSInt(_T_911) node _T_913 = eq(_T_912, asSInt(UInt<1>(0h0))) node _T_914 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_915 = cvt(_T_914) node _T_916 = and(_T_915, asSInt(UInt<17>(0h10000))) node _T_917 = asSInt(_T_916) node _T_918 = eq(_T_917, asSInt(UInt<1>(0h0))) node _T_919 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_920 = cvt(_T_919) node _T_921 = and(_T_920, asSInt(UInt<13>(0h1000))) node _T_922 = asSInt(_T_921) node _T_923 = eq(_T_922, asSInt(UInt<1>(0h0))) node _T_924 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_925 = cvt(_T_924) node _T_926 = and(_T_925, asSInt(UInt<27>(0h4000000))) node _T_927 = asSInt(_T_926) node _T_928 = eq(_T_927, asSInt(UInt<1>(0h0))) node _T_929 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_930 = cvt(_T_929) node _T_931 = and(_T_930, asSInt(UInt<13>(0h1000))) node _T_932 = asSInt(_T_931) node _T_933 = eq(_T_932, asSInt(UInt<1>(0h0))) node _T_934 = or(_T_903, _T_908) node _T_935 = or(_T_934, _T_913) node _T_936 = or(_T_935, _T_918) node _T_937 = or(_T_936, _T_923) node _T_938 = or(_T_937, _T_928) node _T_939 = or(_T_938, _T_933) node _T_940 = and(_T_898, _T_939) node _T_941 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_942 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_943 = and(_T_941, _T_942) node _T_944 = or(UInt<1>(0h0), _T_943) node _T_945 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_946 = cvt(_T_945) node _T_947 = and(_T_946, asSInt(UInt<17>(0h10000))) node _T_948 = asSInt(_T_947) node _T_949 = eq(_T_948, asSInt(UInt<1>(0h0))) node _T_950 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_951 = cvt(_T_950) node _T_952 = and(_T_951, asSInt(UInt<29>(0h10000000))) node _T_953 = asSInt(_T_952) node _T_954 = eq(_T_953, asSInt(UInt<1>(0h0))) node _T_955 = or(_T_949, _T_954) node _T_956 = and(_T_944, _T_955) node _T_957 = or(UInt<1>(0h0), _T_897) node _T_958 = or(_T_957, _T_940) node _T_959 = or(_T_958, _T_956) node _T_960 = and(_T_887, _T_959) node _T_961 = asUInt(reset) node _T_962 = eq(_T_961, UInt<1>(0h0)) when _T_962 : node _T_963 = eq(_T_960, UInt<1>(0h0)) when _T_963 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_960, UInt<1>(0h1), "") : assert_46 node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_967 = asUInt(reset) node _T_968 = eq(_T_967, UInt<1>(0h0)) when _T_968 : node _T_969 = eq(is_aligned, UInt<1>(0h0)) when _T_969 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_970 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_971 = asUInt(reset) node _T_972 = eq(_T_971, UInt<1>(0h0)) when _T_972 : node _T_973 = eq(_T_970, UInt<1>(0h0)) when _T_973 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_970, UInt<1>(0h1), "") : assert_49 node _T_974 = eq(io.in.a.bits.mask, mask) node _T_975 = asUInt(reset) node _T_976 = eq(_T_975, UInt<1>(0h0)) when _T_976 : node _T_977 = eq(_T_974, UInt<1>(0h0)) when _T_977 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_974, UInt<1>(0h1), "") : assert_50 node _T_978 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_979 = asUInt(reset) node _T_980 = eq(_T_979, UInt<1>(0h0)) when _T_980 : node _T_981 = eq(_T_978, UInt<1>(0h0)) when _T_981 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_978, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_982 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_983 = asUInt(reset) node _T_984 = eq(_T_983, UInt<1>(0h0)) when _T_984 : node _T_985 = eq(_T_982, UInt<1>(0h0)) when _T_985 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_982, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 2) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_986 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_986 : node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_990 = geq(io.in.d.bits.size, UInt<3>(0h5)) node _T_991 = asUInt(reset) node _T_992 = eq(_T_991, UInt<1>(0h0)) when _T_992 : node _T_993 = eq(_T_990, UInt<1>(0h0)) when _T_993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_990, UInt<1>(0h1), "") : assert_54 node _T_994 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_995 = asUInt(reset) node _T_996 = eq(_T_995, UInt<1>(0h0)) when _T_996 : node _T_997 = eq(_T_994, UInt<1>(0h0)) when _T_997 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_994, UInt<1>(0h1), "") : assert_55 node _T_998 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_999 = asUInt(reset) node _T_1000 = eq(_T_999, UInt<1>(0h0)) when _T_1000 : node _T_1001 = eq(_T_998, UInt<1>(0h0)) when _T_1001 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_998, UInt<1>(0h1), "") : assert_56 node _T_1002 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1003 = asUInt(reset) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) when _T_1004 : node _T_1005 = eq(_T_1002, UInt<1>(0h0)) when _T_1005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1002, UInt<1>(0h1), "") : assert_57 node _T_1006 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1006 : node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(sink_ok, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1013 = geq(io.in.d.bits.size, UInt<3>(0h5)) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_60 node _T_1017 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_61 node _T_1021 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1022 = asUInt(reset) node _T_1023 = eq(_T_1022, UInt<1>(0h0)) when _T_1023 : node _T_1024 = eq(_T_1021, UInt<1>(0h0)) when _T_1024 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1021, UInt<1>(0h1), "") : assert_62 node _T_1025 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1026 = asUInt(reset) node _T_1027 = eq(_T_1026, UInt<1>(0h0)) when _T_1027 : node _T_1028 = eq(_T_1025, UInt<1>(0h0)) when _T_1028 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1025, UInt<1>(0h1), "") : assert_63 node _T_1029 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1030 = or(UInt<1>(0h1), _T_1029) node _T_1031 = asUInt(reset) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) when _T_1032 : node _T_1033 = eq(_T_1030, UInt<1>(0h0)) when _T_1033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1030, UInt<1>(0h1), "") : assert_64 node _T_1034 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1034 : node _T_1035 = asUInt(reset) node _T_1036 = eq(_T_1035, UInt<1>(0h0)) when _T_1036 : node _T_1037 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1037 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_1038 = asUInt(reset) node _T_1039 = eq(_T_1038, UInt<1>(0h0)) when _T_1039 : node _T_1040 = eq(sink_ok, UInt<1>(0h0)) when _T_1040 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1041 = geq(io.in.d.bits.size, UInt<3>(0h5)) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_67 node _T_1045 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_T_1045, UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1045, UInt<1>(0h1), "") : assert_68 node _T_1049 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_69 node _T_1053 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1054 = or(_T_1053, io.in.d.bits.corrupt) node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(_T_1054, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1054, UInt<1>(0h1), "") : assert_70 node _T_1058 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1059 = or(UInt<1>(0h1), _T_1058) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_71 node _T_1063 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1063 : node _T_1064 = asUInt(reset) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) when _T_1065 : node _T_1066 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1067 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1068 = asUInt(reset) node _T_1069 = eq(_T_1068, UInt<1>(0h0)) when _T_1069 : node _T_1070 = eq(_T_1067, UInt<1>(0h0)) when _T_1070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1067, UInt<1>(0h1), "") : assert_73 node _T_1071 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1072 = asUInt(reset) node _T_1073 = eq(_T_1072, UInt<1>(0h0)) when _T_1073 : node _T_1074 = eq(_T_1071, UInt<1>(0h0)) when _T_1074 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1071, UInt<1>(0h1), "") : assert_74 node _T_1075 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1076 = or(UInt<1>(0h1), _T_1075) node _T_1077 = asUInt(reset) node _T_1078 = eq(_T_1077, UInt<1>(0h0)) when _T_1078 : node _T_1079 = eq(_T_1076, UInt<1>(0h0)) when _T_1079 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1076, UInt<1>(0h1), "") : assert_75 node _T_1080 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1080 : node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1084 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_77 node _T_1088 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1089 = or(_T_1088, io.in.d.bits.corrupt) node _T_1090 = asUInt(reset) node _T_1091 = eq(_T_1090, UInt<1>(0h0)) when _T_1091 : node _T_1092 = eq(_T_1089, UInt<1>(0h0)) when _T_1092 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1089, UInt<1>(0h1), "") : assert_78 node _T_1093 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1094 = or(UInt<1>(0h1), _T_1093) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_79 node _T_1098 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1098 : node _T_1099 = asUInt(reset) node _T_1100 = eq(_T_1099, UInt<1>(0h0)) when _T_1100 : node _T_1101 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1101 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1102 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1103 = asUInt(reset) node _T_1104 = eq(_T_1103, UInt<1>(0h0)) when _T_1104 : node _T_1105 = eq(_T_1102, UInt<1>(0h0)) when _T_1105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1102, UInt<1>(0h1), "") : assert_81 node _T_1106 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1107 = asUInt(reset) node _T_1108 = eq(_T_1107, UInt<1>(0h0)) when _T_1108 : node _T_1109 = eq(_T_1106, UInt<1>(0h0)) when _T_1109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1106, UInt<1>(0h1), "") : assert_82 node _T_1110 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1111 = or(UInt<1>(0h1), _T_1110) node _T_1112 = asUInt(reset) node _T_1113 = eq(_T_1112, UInt<1>(0h0)) when _T_1113 : node _T_1114 = eq(_T_1111, UInt<1>(0h0)) when _T_1114 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1111, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<256>(0h0) connect _WIRE.bits.mask, UInt<32>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<2>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1115 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1116 = asUInt(reset) node _T_1117 = eq(_T_1116, UInt<1>(0h0)) when _T_1117 : node _T_1118 = eq(_T_1115, UInt<1>(0h0)) when _T_1118 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1115, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<256>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<2>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1119 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1120 = asUInt(reset) node _T_1121 = eq(_T_1120, UInt<1>(0h0)) when _T_1121 : node _T_1122 = eq(_T_1119, UInt<1>(0h0)) when _T_1122 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1119, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1123 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1124 = asUInt(reset) node _T_1125 = eq(_T_1124, UInt<1>(0h0)) when _T_1125 : node _T_1126 = eq(_T_1123, UInt<1>(0h0)) when _T_1126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1123, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 5) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<7>, clock, reset, UInt<7>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1127 = eq(a_first, UInt<1>(0h0)) node _T_1128 = and(io.in.a.valid, _T_1127) when _T_1128 : node _T_1129 = eq(io.in.a.bits.opcode, opcode) node _T_1130 = asUInt(reset) node _T_1131 = eq(_T_1130, UInt<1>(0h0)) when _T_1131 : node _T_1132 = eq(_T_1129, UInt<1>(0h0)) when _T_1132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1129, UInt<1>(0h1), "") : assert_87 node _T_1133 = eq(io.in.a.bits.param, param) node _T_1134 = asUInt(reset) node _T_1135 = eq(_T_1134, UInt<1>(0h0)) when _T_1135 : node _T_1136 = eq(_T_1133, UInt<1>(0h0)) when _T_1136 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1133, UInt<1>(0h1), "") : assert_88 node _T_1137 = eq(io.in.a.bits.size, size) node _T_1138 = asUInt(reset) node _T_1139 = eq(_T_1138, UInt<1>(0h0)) when _T_1139 : node _T_1140 = eq(_T_1137, UInt<1>(0h0)) when _T_1140 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1137, UInt<1>(0h1), "") : assert_89 node _T_1141 = eq(io.in.a.bits.source, source) node _T_1142 = asUInt(reset) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) when _T_1143 : node _T_1144 = eq(_T_1141, UInt<1>(0h0)) when _T_1144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1141, UInt<1>(0h1), "") : assert_90 node _T_1145 = eq(io.in.a.bits.address, address) node _T_1146 = asUInt(reset) node _T_1147 = eq(_T_1146, UInt<1>(0h0)) when _T_1147 : node _T_1148 = eq(_T_1145, UInt<1>(0h0)) when _T_1148 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1145, UInt<1>(0h1), "") : assert_91 node _T_1149 = and(io.in.a.ready, io.in.a.valid) node _T_1150 = and(_T_1149, a_first) when _T_1150 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 5) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<7>, clock, reset, UInt<7>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1151 = eq(d_first, UInt<1>(0h0)) node _T_1152 = and(io.in.d.valid, _T_1151) when _T_1152 : node _T_1153 = eq(io.in.d.bits.opcode, opcode_1) node _T_1154 = asUInt(reset) node _T_1155 = eq(_T_1154, UInt<1>(0h0)) when _T_1155 : node _T_1156 = eq(_T_1153, UInt<1>(0h0)) when _T_1156 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1153, UInt<1>(0h1), "") : assert_92 node _T_1157 = eq(io.in.d.bits.param, param_1) node _T_1158 = asUInt(reset) node _T_1159 = eq(_T_1158, UInt<1>(0h0)) when _T_1159 : node _T_1160 = eq(_T_1157, UInt<1>(0h0)) when _T_1160 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1157, UInt<1>(0h1), "") : assert_93 node _T_1161 = eq(io.in.d.bits.size, size_1) node _T_1162 = asUInt(reset) node _T_1163 = eq(_T_1162, UInt<1>(0h0)) when _T_1163 : node _T_1164 = eq(_T_1161, UInt<1>(0h0)) when _T_1164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1161, UInt<1>(0h1), "") : assert_94 node _T_1165 = eq(io.in.d.bits.source, source_1) node _T_1166 = asUInt(reset) node _T_1167 = eq(_T_1166, UInt<1>(0h0)) when _T_1167 : node _T_1168 = eq(_T_1165, UInt<1>(0h0)) when _T_1168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1165, UInt<1>(0h1), "") : assert_95 node _T_1169 = eq(io.in.d.bits.sink, sink) node _T_1170 = asUInt(reset) node _T_1171 = eq(_T_1170, UInt<1>(0h0)) when _T_1171 : node _T_1172 = eq(_T_1169, UInt<1>(0h0)) when _T_1172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1169, UInt<1>(0h1), "") : assert_96 node _T_1173 = eq(io.in.d.bits.denied, denied) node _T_1174 = asUInt(reset) node _T_1175 = eq(_T_1174, UInt<1>(0h0)) when _T_1175 : node _T_1176 = eq(_T_1173, UInt<1>(0h0)) when _T_1176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1173, UInt<1>(0h1), "") : assert_97 node _T_1177 = and(io.in.d.ready, io.in.d.valid) node _T_1178 = and(_T_1177, d_first) when _T_1178 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_opcodes : UInt<16>, clock, reset, UInt<16>(0h0) regreset inflight_sizes : UInt<32>, clock, reset, UInt<32>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 5) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<7>, clock, reset, UInt<7>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 5) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<7>, clock, reset, UInt<7>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<4> connect a_set, UInt<4>(0h0) wire a_set_wo_ready : UInt<4> connect a_set_wo_ready, UInt<4>(0h0) wire a_opcodes_set : UInt<16> connect a_opcodes_set, UInt<16>(0h0) wire a_sizes_set : UInt<32> connect a_sizes_set, UInt<32>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1179 = and(io.in.a.valid, a_first_1) node _T_1180 = and(_T_1179, UInt<1>(0h1)) when _T_1180 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1181 = and(io.in.a.ready, io.in.a.valid) node _T_1182 = and(_T_1181, a_first_1) node _T_1183 = and(_T_1182, UInt<1>(0h1)) when _T_1183 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1184 = dshr(inflight, io.in.a.bits.source) node _T_1185 = bits(_T_1184, 0, 0) node _T_1186 = eq(_T_1185, UInt<1>(0h0)) node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(_T_1186, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1186, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<4> connect d_clr, UInt<4>(0h0) wire d_clr_wo_ready : UInt<4> connect d_clr_wo_ready, UInt<4>(0h0) wire d_opcodes_clr : UInt<16> connect d_opcodes_clr, UInt<16>(0h0) wire d_sizes_clr : UInt<32> connect d_sizes_clr, UInt<32>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1190 = and(io.in.d.valid, d_first_1) node _T_1191 = and(_T_1190, UInt<1>(0h1)) node _T_1192 = eq(d_release_ack, UInt<1>(0h0)) node _T_1193 = and(_T_1191, _T_1192) when _T_1193 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1194 = and(io.in.d.ready, io.in.d.valid) node _T_1195 = and(_T_1194, d_first_1) node _T_1196 = and(_T_1195, UInt<1>(0h1)) node _T_1197 = eq(d_release_ack, UInt<1>(0h0)) node _T_1198 = and(_T_1196, _T_1197) when _T_1198 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1199 = and(io.in.d.valid, d_first_1) node _T_1200 = and(_T_1199, UInt<1>(0h1)) node _T_1201 = eq(d_release_ack, UInt<1>(0h0)) node _T_1202 = and(_T_1200, _T_1201) when _T_1202 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1203 = dshr(inflight, io.in.d.bits.source) node _T_1204 = bits(_T_1203, 0, 0) node _T_1205 = or(_T_1204, same_cycle_resp) node _T_1206 = asUInt(reset) node _T_1207 = eq(_T_1206, UInt<1>(0h0)) when _T_1207 : node _T_1208 = eq(_T_1205, UInt<1>(0h0)) when _T_1208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1205, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1209 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1210 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1211 = or(_T_1209, _T_1210) node _T_1212 = asUInt(reset) node _T_1213 = eq(_T_1212, UInt<1>(0h0)) when _T_1213 : node _T_1214 = eq(_T_1211, UInt<1>(0h0)) when _T_1214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1211, UInt<1>(0h1), "") : assert_100 node _T_1215 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1216 = asUInt(reset) node _T_1217 = eq(_T_1216, UInt<1>(0h0)) when _T_1217 : node _T_1218 = eq(_T_1215, UInt<1>(0h0)) when _T_1218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1215, UInt<1>(0h1), "") : assert_101 else : node _T_1219 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1220 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1221 = or(_T_1219, _T_1220) node _T_1222 = asUInt(reset) node _T_1223 = eq(_T_1222, UInt<1>(0h0)) when _T_1223 : node _T_1224 = eq(_T_1221, UInt<1>(0h0)) when _T_1224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1221, UInt<1>(0h1), "") : assert_102 node _T_1225 = eq(io.in.d.bits.size, a_size_lookup) node _T_1226 = asUInt(reset) node _T_1227 = eq(_T_1226, UInt<1>(0h0)) when _T_1227 : node _T_1228 = eq(_T_1225, UInt<1>(0h0)) when _T_1228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1225, UInt<1>(0h1), "") : assert_103 node _T_1229 = and(io.in.d.valid, d_first_1) node _T_1230 = and(_T_1229, a_first_1) node _T_1231 = and(_T_1230, io.in.a.valid) node _T_1232 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1233 = and(_T_1231, _T_1232) node _T_1234 = eq(d_release_ack, UInt<1>(0h0)) node _T_1235 = and(_T_1233, _T_1234) when _T_1235 : node _T_1236 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1237 = or(_T_1236, io.in.a.ready) node _T_1238 = asUInt(reset) node _T_1239 = eq(_T_1238, UInt<1>(0h0)) when _T_1239 : node _T_1240 = eq(_T_1237, UInt<1>(0h0)) when _T_1240 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1237, UInt<1>(0h1), "") : assert_104 node _T_1241 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1242 = orr(a_set_wo_ready) node _T_1243 = eq(_T_1242, UInt<1>(0h0)) node _T_1244 = or(_T_1241, _T_1243) node _T_1245 = asUInt(reset) node _T_1246 = eq(_T_1245, UInt<1>(0h0)) when _T_1246 : node _T_1247 = eq(_T_1244, UInt<1>(0h0)) when _T_1247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1244, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_132 node _T_1248 = orr(inflight) node _T_1249 = eq(_T_1248, UInt<1>(0h0)) node _T_1250 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1251 = or(_T_1249, _T_1250) node _T_1252 = lt(watchdog, plusarg_reader.out) node _T_1253 = or(_T_1251, _T_1252) node _T_1254 = asUInt(reset) node _T_1255 = eq(_T_1254, UInt<1>(0h0)) when _T_1255 : node _T_1256 = eq(_T_1253, UInt<1>(0h0)) when _T_1256 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1253, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1257 = and(io.in.a.ready, io.in.a.valid) node _T_1258 = and(io.in.d.ready, io.in.d.valid) node _T_1259 = or(_T_1257, _T_1258) when _T_1259 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_opcodes_1 : UInt<16>, clock, reset, UInt<16>(0h0) regreset inflight_sizes_1 : UInt<32>, clock, reset, UInt<32>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<256>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<2>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<256>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<2>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 5) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<7>, clock, reset, UInt<7>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 5) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<7>, clock, reset, UInt<7>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<4> connect c_set, UInt<4>(0h0) wire c_set_wo_ready : UInt<4> connect c_set_wo_ready, UInt<4>(0h0) wire c_opcodes_set : UInt<16> connect c_opcodes_set, UInt<16>(0h0) wire c_sizes_set : UInt<32> connect c_sizes_set, UInt<32>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<256>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<2>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1260 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<256>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<2>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1261 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1262 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1263 = and(_T_1261, _T_1262) node _T_1264 = and(_T_1260, _T_1263) when _T_1264 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<256>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<256>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<2>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1265 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1266 = and(_T_1265, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<256>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<2>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1267 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1268 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1269 = and(_T_1267, _T_1268) node _T_1270 = and(_T_1266, _T_1269) when _T_1270 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<256>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<2>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<256>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<256>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<256>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<256>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<256>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<2>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1271 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1272 = bits(_T_1271, 0, 0) node _T_1273 = eq(_T_1272, UInt<1>(0h0)) node _T_1274 = asUInt(reset) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) when _T_1275 : node _T_1276 = eq(_T_1273, UInt<1>(0h0)) when _T_1276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1273, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<256>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<256>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<4> connect d_clr_1, UInt<4>(0h0) wire d_clr_wo_ready_1 : UInt<4> connect d_clr_wo_ready_1, UInt<4>(0h0) wire d_opcodes_clr_1 : UInt<16> connect d_opcodes_clr_1, UInt<16>(0h0) wire d_sizes_clr_1 : UInt<32> connect d_sizes_clr_1, UInt<32>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1277 = and(io.in.d.valid, d_first_2) node _T_1278 = and(_T_1277, UInt<1>(0h1)) node _T_1279 = and(_T_1278, d_release_ack_1) when _T_1279 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1280 = and(io.in.d.ready, io.in.d.valid) node _T_1281 = and(_T_1280, d_first_2) node _T_1282 = and(_T_1281, UInt<1>(0h1)) node _T_1283 = and(_T_1282, d_release_ack_1) when _T_1283 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1284 = and(io.in.d.valid, d_first_2) node _T_1285 = and(_T_1284, UInt<1>(0h1)) node _T_1286 = and(_T_1285, d_release_ack_1) when _T_1286 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<256>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<256>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<256>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1287 = dshr(inflight_1, io.in.d.bits.source) node _T_1288 = bits(_T_1287, 0, 0) node _T_1289 = or(_T_1288, same_cycle_resp_1) node _T_1290 = asUInt(reset) node _T_1291 = eq(_T_1290, UInt<1>(0h0)) when _T_1291 : node _T_1292 = eq(_T_1289, UInt<1>(0h0)) when _T_1292 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1289, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<256>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<2>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1293 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1294 = asUInt(reset) node _T_1295 = eq(_T_1294, UInt<1>(0h0)) when _T_1295 : node _T_1296 = eq(_T_1293, UInt<1>(0h0)) when _T_1296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1293, UInt<1>(0h1), "") : assert_109 else : node _T_1297 = eq(io.in.d.bits.size, c_size_lookup) node _T_1298 = asUInt(reset) node _T_1299 = eq(_T_1298, UInt<1>(0h0)) when _T_1299 : node _T_1300 = eq(_T_1297, UInt<1>(0h0)) when _T_1300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1297, UInt<1>(0h1), "") : assert_110 node _T_1301 = and(io.in.d.valid, d_first_2) node _T_1302 = and(_T_1301, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<256>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<2>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1303 = and(_T_1302, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<256>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<2>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1304 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1305 = and(_T_1303, _T_1304) node _T_1306 = and(_T_1305, d_release_ack_1) node _T_1307 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1308 = and(_T_1306, _T_1307) when _T_1308 : node _T_1309 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<256>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<2>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1310 = or(_T_1309, _WIRE_23.ready) node _T_1311 = asUInt(reset) node _T_1312 = eq(_T_1311, UInt<1>(0h0)) when _T_1312 : node _T_1313 = eq(_T_1310, UInt<1>(0h0)) when _T_1313 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1310, UInt<1>(0h1), "") : assert_111 node _T_1314 = orr(c_set_wo_ready) when _T_1314 : node _T_1315 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1316 = asUInt(reset) node _T_1317 = eq(_T_1316, UInt<1>(0h0)) when _T_1317 : node _T_1318 = eq(_T_1315, UInt<1>(0h0)) when _T_1318 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1315, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_133 node _T_1319 = orr(inflight_1) node _T_1320 = eq(_T_1319, UInt<1>(0h0)) node _T_1321 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1322 = or(_T_1320, _T_1321) node _T_1323 = lt(watchdog_1, plusarg_reader_1.out) node _T_1324 = or(_T_1322, _T_1323) node _T_1325 = asUInt(reset) node _T_1326 = eq(_T_1325, UInt<1>(0h0)) when _T_1326 : node _T_1327 = eq(_T_1324, UInt<1>(0h0)) when _T_1327 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:65:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1324, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<256>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<2>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1328 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1329 = and(io.in.d.ready, io.in.d.valid) node _T_1330 = or(_T_1328, _T_1329) when _T_1330 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_66( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [255:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [255:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [255:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [255:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [6:0] c_first_beats1_decode = 7'h0; // @[Edges.scala:220:59] wire [6:0] c_first_beats1 = 7'h0; // @[Edges.scala:221:14] wire [6:0] _c_first_count_T = 7'h0; // @[Edges.scala:234:27] wire [6:0] c_first_count = 7'h0; // @[Edges.scala:234:25] wire [6:0] _c_first_counter_T = 7'h0; // @[Edges.scala:236:21] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:56:48] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:56:48] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [6:0] c_first_counter1 = 7'h7F; // @[Edges.scala:230:28] wire [7:0] _c_first_counter1_T = 8'hFF; // @[Edges.scala:230:28] wire [255:0] _c_first_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_first_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_first_WIRE_2_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_first_WIRE_3_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_set_wo_ready_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_set_wo_ready_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_set_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_set_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_opcodes_set_interm_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_opcodes_set_interm_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_sizes_set_interm_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_sizes_set_interm_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_opcodes_set_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_opcodes_set_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_sizes_set_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_sizes_set_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_probe_ack_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_probe_ack_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_probe_ack_WIRE_2_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_probe_ack_WIRE_3_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _same_cycle_resp_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _same_cycle_resp_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _same_cycle_resp_WIRE_2_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _same_cycle_resp_WIRE_3_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _same_cycle_resp_WIRE_4_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _same_cycle_resp_WIRE_5_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] c_sizes_set = 32'h0; // @[Monitor.scala:741:34] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_set = 4'h0; // @[Monitor.scala:738:34] wire [3:0] c_set_wo_ready = 4'h0; // @[Monitor.scala:739:34] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [35:0] _c_sizes_set_T_1 = 36'h0; // @[Monitor.scala:768:52] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [4:0] _c_opcodes_set_T = 5'h0; // @[Monitor.scala:767:79] wire [4:0] _c_sizes_set_T = 5'h0; // @[Monitor.scala:768:77] wire [34:0] _c_opcodes_set_T_1 = 35'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [3:0] _c_set_wo_ready_T = 4'h1; // @[OneHot.scala:58:35] wire [3:0] _c_set_T = 4'h1; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [15:0] c_opcodes_set = 16'h0; // @[Monitor.scala:740:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [1:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [4:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [2:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[2:0]; // @[OneHot.scala:64:49] wire [7:0] _mask_sizeOH_T_1 = 8'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [4:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[4:0]; // @[OneHot.scala:65:{12,27}] wire [4:0] mask_sizeOH = {_mask_sizeOH_T_2[4:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h4; // @[Misc.scala:206:21] wire mask_sub_sub_sub_sub_size = mask_sizeOH[4]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_sub_bit = io_in_a_bits_address_0[4]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_sub_1_2 = mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_sub_nbit = ~mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_sub_0_2 = mask_sub_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_sub_acc_T = mask_sub_sub_sub_sub_size & mask_sub_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_sub_size & mask_sub_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_sub_0_2 & mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_sub_0_2 & mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_2_2 = mask_sub_sub_sub_sub_1_2 & mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T_2 = mask_sub_sub_sub_size & mask_sub_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_2_1 = mask_sub_sub_sub_sub_1_1 | _mask_sub_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_3_2 = mask_sub_sub_sub_sub_1_2 & mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_sub_acc_T_3 = mask_sub_sub_sub_size & mask_sub_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_3_1 = mask_sub_sub_sub_sub_1_1 | _mask_sub_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_4_2 = mask_sub_sub_sub_2_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_4 = mask_sub_sub_size & mask_sub_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_4_1 = mask_sub_sub_sub_2_1 | _mask_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_5_2 = mask_sub_sub_sub_2_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_5 = mask_sub_sub_size & mask_sub_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_5_1 = mask_sub_sub_sub_2_1 | _mask_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_6_2 = mask_sub_sub_sub_3_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_6 = mask_sub_sub_size & mask_sub_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_6_1 = mask_sub_sub_sub_3_1 | _mask_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_7_2 = mask_sub_sub_sub_3_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_7 = mask_sub_sub_size & mask_sub_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_7_1 = mask_sub_sub_sub_3_1 | _mask_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_sub_8_2 = mask_sub_sub_4_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_8 = mask_sub_size & mask_sub_8_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_8_1 = mask_sub_sub_4_1 | _mask_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_sub_9_2 = mask_sub_sub_4_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_9 = mask_sub_size & mask_sub_9_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_9_1 = mask_sub_sub_4_1 | _mask_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_sub_10_2 = mask_sub_sub_5_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_10 = mask_sub_size & mask_sub_10_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_10_1 = mask_sub_sub_5_1 | _mask_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_sub_11_2 = mask_sub_sub_5_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_11 = mask_sub_size & mask_sub_11_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_11_1 = mask_sub_sub_5_1 | _mask_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_sub_12_2 = mask_sub_sub_6_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_12 = mask_sub_size & mask_sub_12_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_12_1 = mask_sub_sub_6_1 | _mask_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_sub_13_2 = mask_sub_sub_6_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_13 = mask_sub_size & mask_sub_13_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_13_1 = mask_sub_sub_6_1 | _mask_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_sub_14_2 = mask_sub_sub_7_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_14 = mask_sub_size & mask_sub_14_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_14_1 = mask_sub_sub_7_1 | _mask_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_sub_15_2 = mask_sub_sub_7_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_15 = mask_sub_size & mask_sub_15_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_15_1 = mask_sub_sub_7_1 | _mask_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_4_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_4_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_5_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_5_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_6_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_6_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_7_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_7_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire mask_eq_16 = mask_sub_8_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_16 = mask_size & mask_eq_16; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_16 = mask_sub_8_1 | _mask_acc_T_16; // @[Misc.scala:215:{29,38}] wire mask_eq_17 = mask_sub_8_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_17 = mask_size & mask_eq_17; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_17 = mask_sub_8_1 | _mask_acc_T_17; // @[Misc.scala:215:{29,38}] wire mask_eq_18 = mask_sub_9_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_18 = mask_size & mask_eq_18; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_18 = mask_sub_9_1 | _mask_acc_T_18; // @[Misc.scala:215:{29,38}] wire mask_eq_19 = mask_sub_9_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_19 = mask_size & mask_eq_19; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_19 = mask_sub_9_1 | _mask_acc_T_19; // @[Misc.scala:215:{29,38}] wire mask_eq_20 = mask_sub_10_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_20 = mask_size & mask_eq_20; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_20 = mask_sub_10_1 | _mask_acc_T_20; // @[Misc.scala:215:{29,38}] wire mask_eq_21 = mask_sub_10_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_21 = mask_size & mask_eq_21; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_21 = mask_sub_10_1 | _mask_acc_T_21; // @[Misc.scala:215:{29,38}] wire mask_eq_22 = mask_sub_11_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_22 = mask_size & mask_eq_22; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_22 = mask_sub_11_1 | _mask_acc_T_22; // @[Misc.scala:215:{29,38}] wire mask_eq_23 = mask_sub_11_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_23 = mask_size & mask_eq_23; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_23 = mask_sub_11_1 | _mask_acc_T_23; // @[Misc.scala:215:{29,38}] wire mask_eq_24 = mask_sub_12_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_24 = mask_size & mask_eq_24; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_24 = mask_sub_12_1 | _mask_acc_T_24; // @[Misc.scala:215:{29,38}] wire mask_eq_25 = mask_sub_12_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_25 = mask_size & mask_eq_25; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_25 = mask_sub_12_1 | _mask_acc_T_25; // @[Misc.scala:215:{29,38}] wire mask_eq_26 = mask_sub_13_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_26 = mask_size & mask_eq_26; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_26 = mask_sub_13_1 | _mask_acc_T_26; // @[Misc.scala:215:{29,38}] wire mask_eq_27 = mask_sub_13_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_27 = mask_size & mask_eq_27; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_27 = mask_sub_13_1 | _mask_acc_T_27; // @[Misc.scala:215:{29,38}] wire mask_eq_28 = mask_sub_14_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_28 = mask_size & mask_eq_28; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_28 = mask_sub_14_1 | _mask_acc_T_28; // @[Misc.scala:215:{29,38}] wire mask_eq_29 = mask_sub_14_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_29 = mask_size & mask_eq_29; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_29 = mask_sub_14_1 | _mask_acc_T_29; // @[Misc.scala:215:{29,38}] wire mask_eq_30 = mask_sub_15_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_30 = mask_size & mask_eq_30; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_30 = mask_sub_15_1 | _mask_acc_T_30; // @[Misc.scala:215:{29,38}] wire mask_eq_31 = mask_sub_15_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_31 = mask_size & mask_eq_31; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_31 = mask_sub_15_1 | _mask_acc_T_31; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo_lo = {mask_lo_lo_lo_hi, mask_lo_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo_hi = {mask_lo_lo_hi_hi, mask_lo_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi_lo = {mask_lo_hi_lo_hi, mask_lo_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi_hi = {mask_lo_hi_hi_hi, mask_lo_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo_lo = {mask_acc_17, mask_acc_16}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_lo_hi = {mask_acc_19, mask_acc_18}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo_lo = {mask_hi_lo_lo_hi, mask_hi_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_hi_lo = {mask_acc_21, mask_acc_20}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi_hi = {mask_acc_23, mask_acc_22}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo_hi = {mask_hi_lo_hi_hi, mask_hi_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo_lo = {mask_acc_25, mask_acc_24}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_lo_hi = {mask_acc_27, mask_acc_26}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi_lo = {mask_hi_hi_lo_hi, mask_hi_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_hi_lo = {mask_acc_29, mask_acc_28}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi_hi = {mask_acc_31, mask_acc_30}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi_hi = {mask_hi_hi_hi_hi, mask_hi_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [31:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _T_1257 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1257; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1257; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [6:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:5]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [6:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 7'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [6:0] a_first_counter; // @[Edges.scala:229:27] wire [7:0] _a_first_counter1_T = {1'h0, a_first_counter} - 8'h1; // @[Edges.scala:229:27, :230:28] wire [6:0] a_first_counter1 = _a_first_counter1_T[6:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 7'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 7'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 7'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [6:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [6:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [6:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [1:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1330 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1330; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1330; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1330; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [6:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:5]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [6:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 7'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [6:0] d_first_counter; // @[Edges.scala:229:27] wire [7:0] _d_first_counter1_T = {1'h0, d_first_counter} - 8'h1; // @[Edges.scala:229:27, :230:28] wire [6:0] d_first_counter1 = _d_first_counter1_T[6:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 7'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 7'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 7'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [6:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [6:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [6:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [1:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [3:0] inflight; // @[Monitor.scala:614:27] reg [15:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [31:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [6:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:5]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [6:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 7'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [6:0] a_first_counter_1; // @[Edges.scala:229:27] wire [7:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 8'h1; // @[Edges.scala:229:27, :230:28] wire [6:0] a_first_counter1_1 = _a_first_counter1_T_1[6:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 7'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 7'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 7'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [6:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [6:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [6:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [6:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:5]; // @[package.scala:243:46] wire [6:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 7'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [6:0] d_first_counter_1; // @[Edges.scala:229:27] wire [7:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 8'h1; // @[Edges.scala:229:27, :230:28] wire [6:0] d_first_counter1_1 = _d_first_counter1_T_1[6:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 7'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 7'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 7'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [6:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [6:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [6:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] a_set; // @[Monitor.scala:626:34] wire [3:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [15:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [31:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [4:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [4:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [4:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [4:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [4:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [15:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & 16'hF; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [4:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [4:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [4:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [4:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [31:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [31:0] _a_size_lookup_T_6 = {24'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [31:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[31:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [3:0] _GEN_3 = {2'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [3:0] _GEN_4 = 4'h1 << _GEN_3; // @[OneHot.scala:58:35] wire [3:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [3:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 4'h0; // @[OneHot.scala:58:35] wire _T_1183 = _T_1257 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1183 ? _a_set_T : 4'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1183 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1183 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [4:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [34:0] _a_opcodes_set_T_1 = {31'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1183 ? _a_opcodes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [4:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [35:0] _a_sizes_set_T_1 = {31'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1183 ? _a_sizes_set_T_1[31:0] : 32'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [3:0] d_clr; // @[Monitor.scala:664:34] wire [3:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [15:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [31:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_1229 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [3:0] _GEN_6 = {2'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [3:0] _GEN_7 = 4'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [3:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [3:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [3:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [3:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1229 & ~d_release_ack ? _d_clr_wo_ready_T : 4'h0; // @[OneHot.scala:58:35] wire _T_1198 = _T_1330 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1198 ? _d_clr_T : 4'h0; // @[OneHot.scala:58:35] wire [46:0] _d_opcodes_clr_T_5 = 47'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1198 ? _d_opcodes_clr_T_5[15:0] : 16'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [46:0] _d_sizes_clr_T_5 = 47'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1198 ? _d_sizes_clr_T_5[31:0] : 32'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [3:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [3:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [3:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [15:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [15:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [15:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [31:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [31:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [31:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [3:0] inflight_1; // @[Monitor.scala:726:35] wire [3:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [15:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [15:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [31:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [31:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [6:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:5]; // @[package.scala:243:46] wire [6:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 7'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [6:0] d_first_counter_2; // @[Edges.scala:229:27] wire [7:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 8'h1; // @[Edges.scala:229:27, :230:28] wire [6:0] d_first_counter1_2 = _d_first_counter1_T_2[6:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 7'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 7'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 7'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [6:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [6:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [6:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = _c_opcode_lookup_T_1 & 16'hF; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [31:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [31:0] _c_size_lookup_T_6 = {24'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [31:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[31:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] d_clr_1; // @[Monitor.scala:774:34] wire [3:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [15:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [31:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1301 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1301 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 4'h0; // @[OneHot.scala:58:35] wire _T_1283 = _T_1330 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1283 ? _d_clr_T_1 : 4'h0; // @[OneHot.scala:58:35] wire [46:0] _d_opcodes_clr_T_11 = 47'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1283 ? _d_opcodes_clr_T_11[15:0] : 16'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [46:0] _d_sizes_clr_T_11 = 47'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1283 ? _d_sizes_clr_T_11[31:0] : 32'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 2'h0; // @[Monitor.scala:36:7, :795:113] wire [3:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [3:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [15:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [15:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [31:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [31:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module TLFragmenter : input clock : Clock input reset : Reset output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<15>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonIn.d.bits.corrupt invalidate anonIn.d.bits.data invalidate anonIn.d.bits.denied invalidate anonIn.d.bits.sink invalidate anonIn.d.bits.source invalidate anonIn.d.bits.size invalidate anonIn.d.bits.param invalidate anonIn.d.bits.opcode invalidate anonIn.d.valid invalidate anonIn.d.ready invalidate anonIn.a.bits.corrupt invalidate anonIn.a.bits.data invalidate anonIn.a.bits.mask invalidate anonIn.a.bits.address invalidate anonIn.a.bits.source invalidate anonIn.a.bits.size invalidate anonIn.a.bits.param invalidate anonIn.a.bits.opcode invalidate anonIn.a.valid invalidate anonIn.a.ready inst monitor of TLMonitor_8 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt connect monitor.io.in.d.bits.data, anonIn.d.bits.data connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink connect monitor.io.in.d.bits.source, anonIn.d.bits.source connect monitor.io.in.d.bits.size, anonIn.d.bits.size connect monitor.io.in.d.bits.param, anonIn.d.bits.param connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode connect monitor.io.in.d.valid, anonIn.d.valid connect monitor.io.in.d.ready, anonIn.d.ready connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt connect monitor.io.in.a.bits.data, anonIn.a.bits.data connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask connect monitor.io.in.a.bits.address, anonIn.a.bits.address connect monitor.io.in.a.bits.source, anonIn.a.bits.source connect monitor.io.in.a.bits.size, anonIn.a.bits.size connect monitor.io.in.a.bits.param, anonIn.a.bits.param connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode connect monitor.io.in.a.valid, anonIn.a.valid connect monitor.io.in.a.ready, anonIn.a.ready wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<15>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonOut.d.bits.corrupt invalidate anonOut.d.bits.data invalidate anonOut.d.bits.denied invalidate anonOut.d.bits.sink invalidate anonOut.d.bits.source invalidate anonOut.d.bits.size invalidate anonOut.d.bits.param invalidate anonOut.d.bits.opcode invalidate anonOut.d.valid invalidate anonOut.d.ready invalidate anonOut.a.bits.corrupt invalidate anonOut.a.bits.data invalidate anonOut.a.bits.mask invalidate anonOut.a.bits.address invalidate anonOut.a.bits.source invalidate anonOut.a.bits.size invalidate anonOut.a.bits.param invalidate anonOut.a.bits.opcode invalidate anonOut.a.valid invalidate anonOut.a.ready connect auto.anon_out, anonOut connect anonIn, auto.anon_in regreset acknum : UInt<3>, clock, reset, UInt<3>(0h0) reg dOrig : UInt, clock regreset dToggle : UInt<1>, clock, reset, UInt<1>(0h0) node dFragnum = bits(anonOut.d.bits.source, 2, 0) node dFirst = eq(acknum, UInt<1>(0h0)) node dLast = eq(dFragnum, UInt<1>(0h0)) node dsizeOH_shiftAmount = bits(anonOut.d.bits.size, 1, 0) node _dsizeOH_T = dshl(UInt<1>(0h1), dsizeOH_shiftAmount) node dsizeOH = bits(_dsizeOH_T, 3, 0) node _dsizeOH1_T = dshl(UInt<3>(0h7), anonOut.d.bits.size) node _dsizeOH1_T_1 = bits(_dsizeOH1_T, 2, 0) node dsizeOH1 = not(_dsizeOH1_T_1) node dHasData = bits(anonOut.d.bits.opcode, 0, 0) node acknum_fragment = shl(dFragnum, 0) node acknum_size = shr(dsizeOH1, 3) node _T = eq(anonOut.d.valid, UInt<1>(0h0)) node _T_1 = and(acknum_fragment, acknum_size) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = or(_T, _T_2) node _T_4 = asUInt(reset) node _T_5 = eq(_T_4, UInt<1>(0h0)) when _T_5 : node _T_6 = eq(_T_3, UInt<1>(0h0)) when _T_6 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:214 assert (!out.d.valid || (acknum_fragment & acknum_size) === 0.U)\n") : printf assert(clock, _T_3, UInt<1>(0h1), "") : assert node _dFirst_acknum_T = mux(dHasData, acknum_size, UInt<1>(0h0)) node dFirst_acknum = or(acknum_fragment, _dFirst_acknum_T) node _ack_decrement_T = shr(dsizeOH, 3) node ack_decrement = mux(dHasData, UInt<1>(0h1), _ack_decrement_T) node _dFirst_size_T = shl(dFragnum, 3) node _dFirst_size_T_1 = or(_dFirst_size_T, dsizeOH1) node _dFirst_size_T_2 = shl(_dFirst_size_T_1, 1) node _dFirst_size_T_3 = or(_dFirst_size_T_2, UInt<1>(0h1)) node _dFirst_size_T_4 = cat(UInt<1>(0h0), _dFirst_size_T_1) node _dFirst_size_T_5 = not(_dFirst_size_T_4) node _dFirst_size_T_6 = and(_dFirst_size_T_3, _dFirst_size_T_5) node dFirst_size_hi = bits(_dFirst_size_T_6, 6, 4) node dFirst_size_lo = bits(_dFirst_size_T_6, 3, 0) node _dFirst_size_T_7 = orr(dFirst_size_hi) node _dFirst_size_T_8 = or(dFirst_size_hi, dFirst_size_lo) node dFirst_size_hi_1 = bits(_dFirst_size_T_8, 3, 2) node dFirst_size_lo_1 = bits(_dFirst_size_T_8, 1, 0) node _dFirst_size_T_9 = orr(dFirst_size_hi_1) node _dFirst_size_T_10 = or(dFirst_size_hi_1, dFirst_size_lo_1) node _dFirst_size_T_11 = bits(_dFirst_size_T_10, 1, 1) node _dFirst_size_T_12 = cat(_dFirst_size_T_9, _dFirst_size_T_11) node dFirst_size = cat(_dFirst_size_T_7, _dFirst_size_T_12) node _T_7 = and(anonOut.d.ready, anonOut.d.valid) when _T_7 : node _acknum_T = sub(acknum, ack_decrement) node _acknum_T_1 = tail(_acknum_T, 1) node _acknum_T_2 = mux(dFirst, dFirst_acknum, _acknum_T_1) connect acknum, _acknum_T_2 when dFirst : connect dOrig, dFirst_size node _dToggle_T = bits(anonOut.d.bits.source, 3, 3) connect dToggle, _dToggle_T node _drop_T = eq(dHasData, UInt<1>(0h0)) node _drop_T_1 = mux(UInt<1>(0h0), dFirst, dLast) node _drop_T_2 = eq(_drop_T_1, UInt<1>(0h0)) node drop = and(_drop_T, _drop_T_2) node _anonOut_d_ready_T = or(anonIn.d.ready, drop) connect anonOut.d.ready, _anonOut_d_ready_T node _anonIn_d_valid_T = eq(drop, UInt<1>(0h0)) node _anonIn_d_valid_T_1 = and(anonOut.d.valid, _anonIn_d_valid_T) connect anonIn.d.valid, _anonIn_d_valid_T_1 connect anonIn.d.bits.corrupt, anonOut.d.bits.corrupt connect anonIn.d.bits.data, anonOut.d.bits.data connect anonIn.d.bits.denied, anonOut.d.bits.denied connect anonIn.d.bits.sink, anonOut.d.bits.sink connect anonIn.d.bits.source, anonOut.d.bits.source connect anonIn.d.bits.size, anonOut.d.bits.size connect anonIn.d.bits.param, anonOut.d.bits.param connect anonIn.d.bits.opcode, anonOut.d.bits.opcode node _anonIn_d_bits_source_T = shr(anonOut.d.bits.source, 4) connect anonIn.d.bits.source, _anonIn_d_bits_source_T node _anonIn_d_bits_size_T = mux(dFirst, dFirst_size, dOrig) connect anonIn.d.bits.size, _anonIn_d_bits_size_T inst repeater of Repeater_TLBundleA_a15d64s7k1z3u connect repeater.clock, clock connect repeater.reset, reset connect repeater.io.enq, anonIn.a node _find_T = xor(repeater.io.deq.bits.address, UInt<1>(0h0)) node _find_T_1 = cvt(_find_T) node _find_T_2 = and(_find_T_1, asSInt(UInt<1>(0h0))) node _find_T_3 = asSInt(_find_T_2) node _find_T_4 = eq(_find_T_3, asSInt(UInt<1>(0h0))) wire find : UInt<1>[1] connect find[0], _find_T_4 node _limit_T = eq(UInt<1>(0h0), repeater.io.deq.bits.opcode) node _limit_T_1 = mux(_limit_T, UInt<2>(0h3), UInt<2>(0h3)) node _limit_T_2 = eq(UInt<1>(0h1), repeater.io.deq.bits.opcode) node _limit_T_3 = mux(_limit_T_2, UInt<2>(0h3), _limit_T_1) node _limit_T_4 = eq(UInt<2>(0h2), repeater.io.deq.bits.opcode) node _limit_T_5 = mux(_limit_T_4, UInt<2>(0h3), _limit_T_3) node _limit_T_6 = eq(UInt<2>(0h3), repeater.io.deq.bits.opcode) node _limit_T_7 = mux(_limit_T_6, UInt<2>(0h3), _limit_T_5) node _limit_T_8 = eq(UInt<3>(0h4), repeater.io.deq.bits.opcode) node _limit_T_9 = mux(_limit_T_8, UInt<2>(0h3), _limit_T_7) node _limit_T_10 = eq(UInt<3>(0h5), repeater.io.deq.bits.opcode) node limit = mux(_limit_T_10, UInt<2>(0h3), _limit_T_9) node _aFrag_T = gt(repeater.io.deq.bits.size, limit) node aFrag = mux(_aFrag_T, limit, repeater.io.deq.bits.size) node _aOrigOH1_T = dshl(UInt<6>(0h3f), repeater.io.deq.bits.size) node _aOrigOH1_T_1 = bits(_aOrigOH1_T, 5, 0) node aOrigOH1 = not(_aOrigOH1_T_1) node _aFragOH1_T = dshl(UInt<3>(0h7), aFrag) node _aFragOH1_T_1 = bits(_aFragOH1_T, 2, 0) node aFragOH1 = not(_aFragOH1_T_1) node _aHasData_opdata_T = bits(repeater.io.deq.bits.opcode, 2, 2) node aHasData = eq(_aHasData_opdata_T, UInt<1>(0h0)) node aMask = mux(aHasData, UInt<1>(0h0), aFragOH1) regreset gennum : UInt<3>, clock, reset, UInt<3>(0h0) node aFirst = eq(gennum, UInt<1>(0h0)) node _old_gennum1_T = shr(aOrigOH1, 3) node _old_gennum1_T_1 = sub(gennum, UInt<1>(0h1)) node _old_gennum1_T_2 = tail(_old_gennum1_T_1, 1) node old_gennum1 = mux(aFirst, _old_gennum1_T, _old_gennum1_T_2) node _new_gennum_T = not(old_gennum1) node _new_gennum_T_1 = shr(aMask, 3) node _new_gennum_T_2 = or(_new_gennum_T, _new_gennum_T_1) node new_gennum = not(_new_gennum_T_2) node _aFragnum_T = shr(old_gennum1, 0) node _aFragnum_T_1 = not(_aFragnum_T) node _aFragnum_T_2 = shr(aFragOH1, 3) node _aFragnum_T_3 = or(_aFragnum_T_1, _aFragnum_T_2) node aFragnum = not(_aFragnum_T_3) node aLast = eq(aFragnum, UInt<1>(0h0)) reg aToggle_r : UInt<1>, clock when aFirst : connect aToggle_r, dToggle node _aToggle_T = mux(aFirst, dToggle, aToggle_r) node aToggle = eq(_aToggle_T, UInt<1>(0h0)) node _T_8 = and(anonOut.a.ready, anonOut.a.valid) when _T_8 : connect gennum, new_gennum node _repeater_io_repeat_T = eq(aHasData, UInt<1>(0h0)) node _repeater_io_repeat_T_1 = neq(aFragnum, UInt<1>(0h0)) node _repeater_io_repeat_T_2 = and(_repeater_io_repeat_T, _repeater_io_repeat_T_1) connect repeater.io.repeat, _repeater_io_repeat_T_2 connect anonOut.a.bits, repeater.io.deq.bits connect anonOut.a.valid, repeater.io.deq.valid connect repeater.io.deq.ready, anonOut.a.ready node _anonOut_a_bits_address_T = shl(old_gennum1, 3) node _anonOut_a_bits_address_T_1 = not(aOrigOH1) node _anonOut_a_bits_address_T_2 = or(_anonOut_a_bits_address_T, _anonOut_a_bits_address_T_1) node _anonOut_a_bits_address_T_3 = or(_anonOut_a_bits_address_T_2, aFragOH1) node _anonOut_a_bits_address_T_4 = or(_anonOut_a_bits_address_T_3, UInt<3>(0h7)) node _anonOut_a_bits_address_T_5 = not(_anonOut_a_bits_address_T_4) node _anonOut_a_bits_address_T_6 = or(repeater.io.deq.bits.address, _anonOut_a_bits_address_T_5) connect anonOut.a.bits.address, _anonOut_a_bits_address_T_6 node anonOut_a_bits_source_hi = cat(repeater.io.deq.bits.source, aToggle) node _anonOut_a_bits_source_T = cat(anonOut_a_bits_source_hi, aFragnum) connect anonOut.a.bits.source, _anonOut_a_bits_source_T connect anonOut.a.bits.size, aFrag node _T_9 = eq(repeater.io.full, UInt<1>(0h0)) node _T_10 = eq(aHasData, UInt<1>(0h0)) node _T_11 = or(_T_9, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:321 assert (!repeater.io.full || !aHasData)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 connect anonOut.a.bits.data, anonIn.a.bits.data node _T_15 = eq(repeater.io.full, UInt<1>(0h0)) node _T_16 = eq(repeater.io.deq.bits.mask, UInt<8>(0hff)) node _T_17 = or(_T_15, _T_16) node _T_18 = asUInt(reset) node _T_19 = eq(_T_18, UInt<1>(0h0)) when _T_19 : node _T_20 = eq(_T_17, UInt<1>(0h0)) when _T_20 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:324 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n") : printf_2 assert(clock, _T_17, UInt<1>(0h1), "") : assert_2 node _anonOut_a_bits_mask_T = mux(repeater.io.full, UInt<8>(0hff), anonIn.a.bits.mask) connect anonOut.a.bits.mask, _anonOut_a_bits_mask_T wire anonOut_a_bits_user_out : { } wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<15>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<15>(0h0) connect _WIRE.bits.source, UInt<7>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<15>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<15>(0h0) connect _WIRE_2.bits.source, UInt<7>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<15>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<15>(0h0) connect _WIRE_6.bits.source, UInt<11>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<15>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<15>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<15>(0h0) connect _WIRE_8.bits.source, UInt<11>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<15>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_10.bits.sink, UInt<1>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0)
module TLFragmenter( // @[Fragmenter.scala:92:9] input clock, // @[Fragmenter.scala:92:9] input reset, // @[Fragmenter.scala:92:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [14:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [14:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire _repeater_io_full; // @[Fragmenter.scala:274:30] wire _repeater_io_enq_ready; // @[Fragmenter.scala:274:30] wire _repeater_io_deq_valid; // @[Fragmenter.scala:274:30] wire [2:0] _repeater_io_deq_bits_opcode; // @[Fragmenter.scala:274:30] wire [2:0] _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30] wire [6:0] _repeater_io_deq_bits_source; // @[Fragmenter.scala:274:30] wire [14:0] _repeater_io_deq_bits_address; // @[Fragmenter.scala:274:30] wire [7:0] _repeater_io_deq_bits_mask; // @[Fragmenter.scala:274:30] reg [2:0] acknum; // @[Fragmenter.scala:201:29] reg [2:0] dOrig; // @[Fragmenter.scala:202:24] reg dToggle; // @[Fragmenter.scala:203:30] wire dFirst = acknum == 3'h0; // @[Fragmenter.scala:201:29, :205:29] wire [5:0] _dsizeOH1_T = 6'h7 << auto_anon_out_d_bits_size; // @[package.scala:243:71] wire [2:0] _GEN = ~(auto_anon_out_d_bits_source[2:0]); // @[package.scala:241:49] wire [2:0] dFirst_size_hi = auto_anon_out_d_bits_source[2:0] & {1'h1, _GEN[2:1]}; // @[OneHot.scala:30:18] wire [2:0] _dFirst_size_T_8 = {1'h0, dFirst_size_hi[2:1]} | ~(_dsizeOH1_T[2:0]) & {_GEN[0], _dsizeOH1_T[2:1]}; // @[OneHot.scala:30:18, :31:18, :32:28] wire [2:0] dFirst_size = {|dFirst_size_hi, |(_dFirst_size_T_8[2:1]), _dFirst_size_T_8[2] | _dFirst_size_T_8[0]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire drop = ~(auto_anon_out_d_bits_opcode[0]) & (|(auto_anon_out_d_bits_source[2:0])); // @[Fragmenter.scala:204:41, :206:30, :234:{20,30}] wire anonOut_d_ready = auto_anon_in_d_ready | drop; // @[Fragmenter.scala:234:30, :235:35] wire anonIn_d_valid = auto_anon_out_d_valid & ~drop; // @[Fragmenter.scala:234:30, :236:{36,39}] wire [2:0] anonIn_d_bits_size = dFirst ? dFirst_size : dOrig; // @[OneHot.scala:32:10] wire [12:0] _aOrigOH1_T = 13'h3F << _repeater_io_deq_bits_size; // @[package.scala:243:71] reg [2:0] gennum; // @[Fragmenter.scala:303:29] wire aFirst = gennum == 3'h0; // @[Fragmenter.scala:303:29, :304:29] wire [2:0] aFragnum = aFirst ? ~(_aOrigOH1_T[5:3]) : gennum - 3'h1; // @[package.scala:243:{46,71,76}] reg aToggle_r; // @[Fragmenter.scala:309:54]
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_73 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<7>, poisoned : UInt<1>}}[2], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<7>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}} wire next_state : UInt wire next_uopc : UInt wire next_lrs1_rtype : UInt wire next_lrs2_rtype : UInt regreset state : UInt<2>, clock, reset, UInt<2>(0h0) regreset p1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p3 : UInt<1>, clock, reset, UInt<1>(0h0) regreset ppred : UInt<1>, clock, reset, UInt<1>(0h0) regreset p1_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) connect p1_poisoned, UInt<1>(0h0) connect p2_poisoned, UInt<1>(0h0) node next_p1_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) node next_p2_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) wire slot_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} invalidate slot_uop_uop.debug_tsrc invalidate slot_uop_uop.debug_fsrc invalidate slot_uop_uop.bp_xcpt_if invalidate slot_uop_uop.bp_debug_if invalidate slot_uop_uop.xcpt_ma_if invalidate slot_uop_uop.xcpt_ae_if invalidate slot_uop_uop.xcpt_pf_if invalidate slot_uop_uop.fp_single invalidate slot_uop_uop.fp_val invalidate slot_uop_uop.frs3_en invalidate slot_uop_uop.lrs2_rtype invalidate slot_uop_uop.lrs1_rtype invalidate slot_uop_uop.dst_rtype invalidate slot_uop_uop.ldst_val invalidate slot_uop_uop.lrs3 invalidate slot_uop_uop.lrs2 invalidate slot_uop_uop.lrs1 invalidate slot_uop_uop.ldst invalidate slot_uop_uop.ldst_is_rs1 invalidate slot_uop_uop.flush_on_commit invalidate slot_uop_uop.is_unique invalidate slot_uop_uop.is_sys_pc2epc invalidate slot_uop_uop.uses_stq invalidate slot_uop_uop.uses_ldq invalidate slot_uop_uop.is_amo invalidate slot_uop_uop.is_fencei invalidate slot_uop_uop.is_fence invalidate slot_uop_uop.mem_signed invalidate slot_uop_uop.mem_size invalidate slot_uop_uop.mem_cmd invalidate slot_uop_uop.bypassable invalidate slot_uop_uop.exc_cause invalidate slot_uop_uop.exception invalidate slot_uop_uop.stale_pdst invalidate slot_uop_uop.ppred_busy invalidate slot_uop_uop.prs3_busy invalidate slot_uop_uop.prs2_busy invalidate slot_uop_uop.prs1_busy invalidate slot_uop_uop.ppred invalidate slot_uop_uop.prs3 invalidate slot_uop_uop.prs2 invalidate slot_uop_uop.prs1 invalidate slot_uop_uop.pdst invalidate slot_uop_uop.rxq_idx invalidate slot_uop_uop.stq_idx invalidate slot_uop_uop.ldq_idx invalidate slot_uop_uop.rob_idx invalidate slot_uop_uop.csr_addr invalidate slot_uop_uop.imm_packed invalidate slot_uop_uop.taken invalidate slot_uop_uop.pc_lob invalidate slot_uop_uop.edge_inst invalidate slot_uop_uop.ftq_idx invalidate slot_uop_uop.br_tag invalidate slot_uop_uop.br_mask invalidate slot_uop_uop.is_sfb invalidate slot_uop_uop.is_jal invalidate slot_uop_uop.is_jalr invalidate slot_uop_uop.is_br invalidate slot_uop_uop.iw_p2_poisoned invalidate slot_uop_uop.iw_p1_poisoned invalidate slot_uop_uop.iw_state invalidate slot_uop_uop.ctrl.is_std invalidate slot_uop_uop.ctrl.is_sta invalidate slot_uop_uop.ctrl.is_load invalidate slot_uop_uop.ctrl.csr_cmd invalidate slot_uop_uop.ctrl.fcn_dw invalidate slot_uop_uop.ctrl.op_fcn invalidate slot_uop_uop.ctrl.imm_sel invalidate slot_uop_uop.ctrl.op2_sel invalidate slot_uop_uop.ctrl.op1_sel invalidate slot_uop_uop.ctrl.br_type invalidate slot_uop_uop.fu_code invalidate slot_uop_uop.iq_type invalidate slot_uop_uop.debug_pc invalidate slot_uop_uop.is_rvc invalidate slot_uop_uop.debug_inst invalidate slot_uop_uop.inst invalidate slot_uop_uop.uopc connect slot_uop_uop.uopc, UInt<7>(0h0) connect slot_uop_uop.bypassable, UInt<1>(0h0) connect slot_uop_uop.fp_val, UInt<1>(0h0) connect slot_uop_uop.uses_stq, UInt<1>(0h0) connect slot_uop_uop.uses_ldq, UInt<1>(0h0) connect slot_uop_uop.pdst, UInt<1>(0h0) connect slot_uop_uop.dst_rtype, UInt<2>(0h2) wire slot_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>} invalidate slot_uop_cs.is_std invalidate slot_uop_cs.is_sta invalidate slot_uop_cs.is_load invalidate slot_uop_cs.csr_cmd invalidate slot_uop_cs.fcn_dw invalidate slot_uop_cs.op_fcn invalidate slot_uop_cs.imm_sel invalidate slot_uop_cs.op2_sel invalidate slot_uop_cs.op1_sel invalidate slot_uop_cs.br_type connect slot_uop_cs.br_type, UInt<4>(0h0) connect slot_uop_cs.csr_cmd, UInt<3>(0h0) connect slot_uop_cs.is_load, UInt<1>(0h0) connect slot_uop_cs.is_sta, UInt<1>(0h0) connect slot_uop_cs.is_std, UInt<1>(0h0) connect slot_uop_uop.ctrl, slot_uop_cs regreset slot_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock, reset, slot_uop_uop node next_uop = mux(io.in_uop.valid, io.in_uop.bits, slot_uop) when io.kill : connect state, UInt<2>(0h0) else : when io.in_uop.valid : connect state, io.in_uop.bits.iw_state else : when io.clear : connect state, UInt<2>(0h0) else : connect state, next_state connect next_state, state connect next_uopc, slot_uop.uopc connect next_lrs1_rtype, slot_uop.lrs1_rtype connect next_lrs2_rtype, slot_uop.lrs2_rtype when io.kill : connect next_state, UInt<2>(0h0) else : node _T = eq(state, UInt<2>(0h1)) node _T_1 = and(io.grant, _T) node _T_2 = eq(state, UInt<2>(0h2)) node _T_3 = and(io.grant, _T_2) node _T_4 = and(_T_3, p1) node _T_5 = and(_T_4, p2) node _T_6 = and(_T_5, ppred) node _T_7 = or(_T_1, _T_6) when _T_7 : node _T_8 = or(p1_poisoned, p2_poisoned) node _T_9 = and(io.ldspec_miss, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : connect next_state, UInt<2>(0h0) else : node _T_11 = eq(state, UInt<2>(0h2)) node _T_12 = and(io.grant, _T_11) when _T_12 : node _T_13 = or(p1_poisoned, p2_poisoned) node _T_14 = and(io.ldspec_miss, _T_13) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : connect next_state, UInt<2>(0h1) when p1 : connect slot_uop.uopc, UInt<7>(0h3) connect next_uopc, UInt<7>(0h3) connect slot_uop.lrs1_rtype, UInt<2>(0h2) connect next_lrs1_rtype, UInt<2>(0h2) else : connect slot_uop.lrs2_rtype, UInt<2>(0h2) connect next_lrs2_rtype, UInt<2>(0h2) when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T_16 = eq(state, UInt<2>(0h0)) node _T_17 = or(_T_16, io.clear) node _T_18 = or(_T_17, io.kill) node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : node _T_21 = eq(_T_18, UInt<1>(0h0)) when _T_21 : printf(clock, UInt<1>(0h1), "Assertion failed: trying to overwrite a valid issue slot.\n at issue-slot.scala:156 assert (is_invalid || io.clear || io.kill, \"trying to overwrite a valid issue slot.\")\n") : printf assert(clock, _T_18, UInt<1>(0h1), "") : assert wire next_p1 : UInt<1> connect next_p1, p1 wire next_p2 : UInt<1> connect next_p2, p2 wire next_p3 : UInt<1> connect next_p3, p3 wire next_ppred : UInt<1> connect next_ppred, ppred when io.in_uop.valid : node _p1_T = eq(io.in_uop.bits.prs1_busy, UInt<1>(0h0)) connect p1, _p1_T node _p2_T = eq(io.in_uop.bits.prs2_busy, UInt<1>(0h0)) connect p2, _p2_T node _p3_T = eq(io.in_uop.bits.prs3_busy, UInt<1>(0h0)) connect p3, _p3_T node _ppred_T = eq(io.in_uop.bits.ppred_busy, UInt<1>(0h0)) connect ppred, _ppred_T node _T_22 = and(io.ldspec_miss, next_p1_poisoned) when _T_22 : node _T_23 = neq(next_uop.prs1, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs1=x0!\n at issue-slot.scala:176 assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n") : printf_1 assert(clock, _T_23, UInt<1>(0h1), "") : assert_1 connect p1, UInt<1>(0h0) node _T_27 = and(io.ldspec_miss, next_p2_poisoned) when _T_27 : node _T_28 = neq(next_uop.prs2, UInt<1>(0h0)) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs2=x0!\n at issue-slot.scala:180 assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n") : printf_2 assert(clock, _T_28, UInt<1>(0h1), "") : assert_2 connect p2, UInt<1>(0h0) node _T_32 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs1) node _T_33 = and(io.wakeup_ports[0].valid, _T_32) when _T_33 : connect p1, UInt<1>(0h1) node _T_34 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs2) node _T_35 = and(io.wakeup_ports[0].valid, _T_34) when _T_35 : connect p2, UInt<1>(0h1) node _T_36 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs3) node _T_37 = and(io.wakeup_ports[0].valid, _T_36) when _T_37 : connect p3, UInt<1>(0h1) node _T_38 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs1) node _T_39 = and(io.wakeup_ports[1].valid, _T_38) when _T_39 : connect p1, UInt<1>(0h1) node _T_40 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs2) node _T_41 = and(io.wakeup_ports[1].valid, _T_40) when _T_41 : connect p2, UInt<1>(0h1) node _T_42 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs3) node _T_43 = and(io.wakeup_ports[1].valid, _T_42) when _T_43 : connect p3, UInt<1>(0h1) node _T_44 = eq(io.pred_wakeup_port.bits, next_uop.ppred) node _T_45 = and(io.pred_wakeup_port.valid, _T_44) when _T_45 : connect ppred, UInt<1>(0h1) node _T_46 = eq(io.spec_ld_wakeup[0].bits, UInt<1>(0h0)) node _T_47 = and(io.spec_ld_wakeup[0].valid, _T_46) node _T_48 = eq(_T_47, UInt<1>(0h0)) node _T_49 = asUInt(reset) node _T_50 = eq(_T_49, UInt<1>(0h0)) when _T_50 : node _T_51 = eq(_T_48, UInt<1>(0h0)) when _T_51 : printf(clock, UInt<1>(0h1), "Assertion failed: Loads to x0 should never speculatively wakeup other instructions\n at issue-slot.scala:203 assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n") : printf_3 assert(clock, _T_48, UInt<1>(0h1), "") : assert_3 node _T_52 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs1) node _T_53 = and(io.spec_ld_wakeup[0].valid, _T_52) node _T_54 = eq(next_uop.lrs1_rtype, UInt<2>(0h0)) node _T_55 = and(_T_53, _T_54) when _T_55 : connect p1, UInt<1>(0h1) connect p1_poisoned, UInt<1>(0h1) node _T_56 = eq(next_p1_poisoned, UInt<1>(0h0)) node _T_57 = asUInt(reset) node _T_58 = eq(_T_57, UInt<1>(0h0)) when _T_58 : node _T_59 = eq(_T_56, UInt<1>(0h0)) when _T_59 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:214 assert (!next_p1_poisoned)\n") : printf_4 assert(clock, _T_56, UInt<1>(0h1), "") : assert_4 node _T_60 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs2) node _T_61 = and(io.spec_ld_wakeup[0].valid, _T_60) node _T_62 = eq(next_uop.lrs2_rtype, UInt<2>(0h0)) node _T_63 = and(_T_61, _T_62) when _T_63 : connect p2, UInt<1>(0h1) connect p2_poisoned, UInt<1>(0h1) node _T_64 = eq(next_p2_poisoned, UInt<1>(0h0)) node _T_65 = asUInt(reset) node _T_66 = eq(_T_65, UInt<1>(0h0)) when _T_66 : node _T_67 = eq(_T_64, UInt<1>(0h0)) when _T_67 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:221 assert (!next_p2_poisoned)\n") : printf_5 assert(clock, _T_64, UInt<1>(0h1), "") : assert_5 node _next_br_mask_T = not(io.brupdate.b1.resolve_mask) node next_br_mask = and(slot_uop.br_mask, _next_br_mask_T) node _T_68 = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _T_69 = neq(_T_68, UInt<1>(0h0)) when _T_69 : connect next_state, UInt<2>(0h0) node _T_70 = eq(io.in_uop.valid, UInt<1>(0h0)) when _T_70 : connect slot_uop.br_mask, next_br_mask node _io_request_T = neq(state, UInt<2>(0h0)) node _io_request_T_1 = and(_io_request_T, p1) node _io_request_T_2 = and(_io_request_T_1, p2) node _io_request_T_3 = and(_io_request_T_2, p3) node _io_request_T_4 = and(_io_request_T_3, ppred) node _io_request_T_5 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_6 = and(_io_request_T_4, _io_request_T_5) connect io.request, _io_request_T_6 node _high_priority_T = or(slot_uop.is_br, slot_uop.is_jal) node high_priority = or(_high_priority_T, slot_uop.is_jalr) node _io_request_hp_T = and(io.request, high_priority) connect io.request_hp, _io_request_hp_T node _T_71 = eq(state, UInt<2>(0h1)) when _T_71 : node _io_request_T_7 = and(p1, p2) node _io_request_T_8 = and(_io_request_T_7, p3) node _io_request_T_9 = and(_io_request_T_8, ppred) node _io_request_T_10 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_11 = and(_io_request_T_9, _io_request_T_10) connect io.request, _io_request_T_11 else : node _T_72 = eq(state, UInt<2>(0h2)) when _T_72 : node _io_request_T_12 = or(p1, p2) node _io_request_T_13 = and(_io_request_T_12, ppred) node _io_request_T_14 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_15 = and(_io_request_T_13, _io_request_T_14) connect io.request, _io_request_T_15 else : connect io.request, UInt<1>(0h0) node _io_valid_T = neq(state, UInt<2>(0h0)) connect io.valid, _io_valid_T connect io.uop, slot_uop connect io.uop.iw_p1_poisoned, p1_poisoned connect io.uop.iw_p2_poisoned, p2_poisoned node _may_vacate_T = eq(state, UInt<2>(0h1)) node _may_vacate_T_1 = eq(state, UInt<2>(0h2)) node _may_vacate_T_2 = and(_may_vacate_T_1, p1) node _may_vacate_T_3 = and(_may_vacate_T_2, p2) node _may_vacate_T_4 = and(_may_vacate_T_3, ppred) node _may_vacate_T_5 = or(_may_vacate_T, _may_vacate_T_4) node may_vacate = and(io.grant, _may_vacate_T_5) node _squash_grant_T = or(p1_poisoned, p2_poisoned) node squash_grant = and(io.ldspec_miss, _squash_grant_T) node _io_will_be_valid_T = neq(state, UInt<2>(0h0)) node _io_will_be_valid_T_1 = eq(squash_grant, UInt<1>(0h0)) node _io_will_be_valid_T_2 = and(may_vacate, _io_will_be_valid_T_1) node _io_will_be_valid_T_3 = eq(_io_will_be_valid_T_2, UInt<1>(0h0)) node _io_will_be_valid_T_4 = and(_io_will_be_valid_T, _io_will_be_valid_T_3) connect io.will_be_valid, _io_will_be_valid_T_4 connect io.out_uop, slot_uop connect io.out_uop.iw_state, next_state connect io.out_uop.uopc, next_uopc connect io.out_uop.lrs1_rtype, next_lrs1_rtype connect io.out_uop.lrs2_rtype, next_lrs2_rtype connect io.out_uop.br_mask, next_br_mask node _io_out_uop_prs1_busy_T = eq(p1, UInt<1>(0h0)) connect io.out_uop.prs1_busy, _io_out_uop_prs1_busy_T node _io_out_uop_prs2_busy_T = eq(p2, UInt<1>(0h0)) connect io.out_uop.prs2_busy, _io_out_uop_prs2_busy_T node _io_out_uop_prs3_busy_T = eq(p3, UInt<1>(0h0)) connect io.out_uop.prs3_busy, _io_out_uop_prs3_busy_T node _io_out_uop_ppred_busy_T = eq(ppred, UInt<1>(0h0)) connect io.out_uop.ppred_busy, _io_out_uop_ppred_busy_T connect io.out_uop.iw_p1_poisoned, p1_poisoned connect io.out_uop.iw_p2_poisoned, p2_poisoned node _T_73 = eq(state, UInt<2>(0h2)) when _T_73 : node _T_74 = and(p1, p2) node _T_75 = and(_T_74, ppred) when _T_75 : skip else : node _T_76 = and(p1, ppred) when _T_76 : connect io.uop.uopc, slot_uop.uopc connect io.uop.lrs2_rtype, UInt<2>(0h2) else : node _T_77 = and(p2, ppred) when _T_77 : connect io.uop.uopc, UInt<7>(0h3) connect io.uop.lrs1_rtype, UInt<2>(0h2) connect io.debug.p1, p1 connect io.debug.p2, p2 connect io.debug.p3, p3 connect io.debug.ppred, ppred connect io.debug.state, state
module IssueSlot_73( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_ldspec_miss = 1'h0; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire next_p1_poisoned = 1'h0; // @[issue-slot.scala:99:29] wire next_p2_poisoned = 1'h0; // @[issue-slot.scala:100:29] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire _squash_grant_T = 1'h0; // @[issue-slot.scala:261:53] wire squash_grant = 1'h0; // @[issue-slot.scala:261:37] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [6:0] io_spec_ld_wakeup_0_bits = 7'h0; // @[issue-slot.scala:69:7] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire _io_will_be_valid_T_1 = 1'h1; // @[issue-slot.scala:262:51] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [15:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _GEN = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_0 = _GEN | ~(_T_12 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17, :143:23] assign next_uopc = _GEN_0 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_0 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_1 = _GEN | ~_T_12 | p1; // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17] assign next_lrs2_rtype = _GEN_1 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17]
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_176 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_197 connect io_out_source_valid_0.clock, clock connect io_out_source_valid_0.reset, reset connect io_out_source_valid_0.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid_0.io.q connect io.out, _io_out_WIRE
module AsyncValidSync_176( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_197 io_out_source_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_203 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_203( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module TLInterconnectCoupler_pbus_to_device_named_uart_0 : input clock : Clock input reset : Reset output auto : { control_xing_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} inst fragmenter of TLFragmenter_UART connect fragmenter.clock, clock connect fragmenter.reset, reset wire tlOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate tlOut.d.bits.corrupt invalidate tlOut.d.bits.data invalidate tlOut.d.bits.denied invalidate tlOut.d.bits.sink invalidate tlOut.d.bits.source invalidate tlOut.d.bits.size invalidate tlOut.d.bits.param invalidate tlOut.d.bits.opcode invalidate tlOut.d.valid invalidate tlOut.d.ready invalidate tlOut.a.bits.corrupt invalidate tlOut.a.bits.data invalidate tlOut.a.bits.mask invalidate tlOut.a.bits.address invalidate tlOut.a.bits.source invalidate tlOut.a.bits.size invalidate tlOut.a.bits.param invalidate tlOut.a.bits.opcode invalidate tlOut.a.valid invalidate tlOut.a.ready wire tlIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate tlIn.d.bits.corrupt invalidate tlIn.d.bits.data invalidate tlIn.d.bits.denied invalidate tlIn.d.bits.sink invalidate tlIn.d.bits.source invalidate tlIn.d.bits.size invalidate tlIn.d.bits.param invalidate tlIn.d.bits.opcode invalidate tlIn.d.valid invalidate tlIn.d.ready invalidate tlIn.a.bits.corrupt invalidate tlIn.a.bits.data invalidate tlIn.a.bits.mask invalidate tlIn.a.bits.address invalidate tlIn.a.bits.source invalidate tlIn.a.bits.size invalidate tlIn.a.bits.param invalidate tlIn.a.bits.opcode invalidate tlIn.a.valid invalidate tlIn.a.ready connect tlOut, tlIn wire controlXingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate controlXingOut.d.bits.corrupt invalidate controlXingOut.d.bits.data invalidate controlXingOut.d.bits.denied invalidate controlXingOut.d.bits.sink invalidate controlXingOut.d.bits.source invalidate controlXingOut.d.bits.size invalidate controlXingOut.d.bits.param invalidate controlXingOut.d.bits.opcode invalidate controlXingOut.d.valid invalidate controlXingOut.d.ready invalidate controlXingOut.a.bits.corrupt invalidate controlXingOut.a.bits.data invalidate controlXingOut.a.bits.mask invalidate controlXingOut.a.bits.address invalidate controlXingOut.a.bits.source invalidate controlXingOut.a.bits.size invalidate controlXingOut.a.bits.param invalidate controlXingOut.a.bits.opcode invalidate controlXingOut.a.valid invalidate controlXingOut.a.ready wire controlXingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate controlXingIn.d.bits.corrupt invalidate controlXingIn.d.bits.data invalidate controlXingIn.d.bits.denied invalidate controlXingIn.d.bits.sink invalidate controlXingIn.d.bits.source invalidate controlXingIn.d.bits.size invalidate controlXingIn.d.bits.param invalidate controlXingIn.d.bits.opcode invalidate controlXingIn.d.valid invalidate controlXingIn.d.ready invalidate controlXingIn.a.bits.corrupt invalidate controlXingIn.a.bits.data invalidate controlXingIn.a.bits.mask invalidate controlXingIn.a.bits.address invalidate controlXingIn.a.bits.source invalidate controlXingIn.a.bits.size invalidate controlXingIn.a.bits.param invalidate controlXingIn.a.bits.opcode invalidate controlXingIn.a.valid invalidate controlXingIn.a.ready connect controlXingOut, controlXingIn connect fragmenter.auto.anon_in, tlOut connect fragmenter.auto.anon_out.d, controlXingIn.d connect controlXingIn.a.bits, fragmenter.auto.anon_out.a.bits connect controlXingIn.a.valid, fragmenter.auto.anon_out.a.valid connect fragmenter.auto.anon_out.a.ready, controlXingIn.a.ready connect tlIn, auto.tl_in connect auto.control_xing_out, controlXingOut
module TLInterconnectCoupler_pbus_to_device_named_uart_0( // @[LazyModuleImp.scala:138:7] input clock, // @[LazyModuleImp.scala:138:7] input reset, // @[LazyModuleImp.scala:138:7] input auto_control_xing_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_control_xing_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_control_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_control_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_control_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_control_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_control_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_control_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_control_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_control_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_control_xing_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_control_xing_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_control_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_control_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_control_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_control_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_in_d_bits_data // @[LazyModuleImp.scala:107:25] ); TLFragmenter_UART fragmenter ( // @[Fragmenter.scala:345:34] .clock (clock), .reset (reset), .auto_anon_in_a_ready (auto_tl_in_a_ready), .auto_anon_in_a_valid (auto_tl_in_a_valid), .auto_anon_in_a_bits_opcode (auto_tl_in_a_bits_opcode), .auto_anon_in_a_bits_param (auto_tl_in_a_bits_param), .auto_anon_in_a_bits_size (auto_tl_in_a_bits_size), .auto_anon_in_a_bits_source (auto_tl_in_a_bits_source), .auto_anon_in_a_bits_address (auto_tl_in_a_bits_address), .auto_anon_in_a_bits_mask (auto_tl_in_a_bits_mask), .auto_anon_in_a_bits_data (auto_tl_in_a_bits_data), .auto_anon_in_a_bits_corrupt (auto_tl_in_a_bits_corrupt), .auto_anon_in_d_ready (auto_tl_in_d_ready), .auto_anon_in_d_valid (auto_tl_in_d_valid), .auto_anon_in_d_bits_opcode (auto_tl_in_d_bits_opcode), .auto_anon_in_d_bits_size (auto_tl_in_d_bits_size), .auto_anon_in_d_bits_source (auto_tl_in_d_bits_source), .auto_anon_in_d_bits_data (auto_tl_in_d_bits_data), .auto_anon_out_a_ready (auto_control_xing_out_a_ready), .auto_anon_out_a_valid (auto_control_xing_out_a_valid), .auto_anon_out_a_bits_opcode (auto_control_xing_out_a_bits_opcode), .auto_anon_out_a_bits_param (auto_control_xing_out_a_bits_param), .auto_anon_out_a_bits_size (auto_control_xing_out_a_bits_size), .auto_anon_out_a_bits_source (auto_control_xing_out_a_bits_source), .auto_anon_out_a_bits_address (auto_control_xing_out_a_bits_address), .auto_anon_out_a_bits_mask (auto_control_xing_out_a_bits_mask), .auto_anon_out_a_bits_data (auto_control_xing_out_a_bits_data), .auto_anon_out_a_bits_corrupt (auto_control_xing_out_a_bits_corrupt), .auto_anon_out_d_ready (auto_control_xing_out_d_ready), .auto_anon_out_d_valid (auto_control_xing_out_d_valid), .auto_anon_out_d_bits_opcode (auto_control_xing_out_d_bits_opcode), .auto_anon_out_d_bits_size (auto_control_xing_out_d_bits_size), .auto_anon_out_d_bits_source (auto_control_xing_out_d_bits_source), .auto_anon_out_d_bits_data (auto_control_xing_out_d_bits_data) ); // @[Fragmenter.scala:345:34] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLDebugModuleOuter : input clock : Clock input reset : Reset output auto : { flip dmi_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, int_out_7 : UInt<1>[1], int_out_6 : UInt<1>[1], int_out_5 : UInt<1>[1], int_out_4 : UInt<1>[1], int_out_3 : UInt<1>[1], int_out_2 : UInt<1>[1], int_out_1 : UInt<1>[1], int_out_0 : UInt<1>[1]} output io : { ctrl : { flip debugUnavail : UInt<1>[8], ndreset : UInt<1>, dmactive : UInt<1>, flip dmactiveAck : UInt<1>}, innerCtrl : { flip ready : UInt<1>, valid : UInt<1>, bits : { resumereq : UInt<1>, hartsel : UInt<10>, ackhavereset : UInt<1>, hasel : UInt<1>, hamask : UInt<1>[8], hrmask : UInt<1>[8]}}, flip hgDebugInt : UInt<1>[8]} wire intnodeOut : UInt<1>[1] invalidate intnodeOut[0] wire x1_intnodeOut : UInt<1>[1] invalidate x1_intnodeOut[0] wire x1_intnodeOut_1 : UInt<1>[1] invalidate x1_intnodeOut_1[0] wire x1_intnodeOut_2 : UInt<1>[1] invalidate x1_intnodeOut_2[0] wire x1_intnodeOut_3 : UInt<1>[1] invalidate x1_intnodeOut_3[0] wire x1_intnodeOut_4 : UInt<1>[1] invalidate x1_intnodeOut_4[0] wire x1_intnodeOut_5 : UInt<1>[1] invalidate x1_intnodeOut_5[0] wire x1_intnodeOut_6 : UInt<1>[1] invalidate x1_intnodeOut_6[0] wire dmiNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate dmiNodeIn.d.bits.corrupt invalidate dmiNodeIn.d.bits.data invalidate dmiNodeIn.d.bits.denied invalidate dmiNodeIn.d.bits.sink invalidate dmiNodeIn.d.bits.source invalidate dmiNodeIn.d.bits.size invalidate dmiNodeIn.d.bits.param invalidate dmiNodeIn.d.bits.opcode invalidate dmiNodeIn.d.valid invalidate dmiNodeIn.d.ready invalidate dmiNodeIn.a.bits.corrupt invalidate dmiNodeIn.a.bits.data invalidate dmiNodeIn.a.bits.mask invalidate dmiNodeIn.a.bits.address invalidate dmiNodeIn.a.bits.source invalidate dmiNodeIn.a.bits.size invalidate dmiNodeIn.a.bits.param invalidate dmiNodeIn.a.bits.opcode invalidate dmiNodeIn.a.valid invalidate dmiNodeIn.a.ready inst monitor of TLMonitor_87 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, dmiNodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, dmiNodeIn.d.bits.data connect monitor.io.in.d.bits.denied, dmiNodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, dmiNodeIn.d.bits.sink connect monitor.io.in.d.bits.source, dmiNodeIn.d.bits.source connect monitor.io.in.d.bits.size, dmiNodeIn.d.bits.size connect monitor.io.in.d.bits.param, dmiNodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, dmiNodeIn.d.bits.opcode connect monitor.io.in.d.valid, dmiNodeIn.d.valid connect monitor.io.in.d.ready, dmiNodeIn.d.ready connect monitor.io.in.a.bits.corrupt, dmiNodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, dmiNodeIn.a.bits.data connect monitor.io.in.a.bits.mask, dmiNodeIn.a.bits.mask connect monitor.io.in.a.bits.address, dmiNodeIn.a.bits.address connect monitor.io.in.a.bits.source, dmiNodeIn.a.bits.source connect monitor.io.in.a.bits.size, dmiNodeIn.a.bits.size connect monitor.io.in.a.bits.param, dmiNodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, dmiNodeIn.a.bits.opcode connect monitor.io.in.a.valid, dmiNodeIn.a.valid connect monitor.io.in.a.ready, dmiNodeIn.a.ready connect auto.int_out_0, intnodeOut connect auto.int_out_1, x1_intnodeOut connect auto.int_out_2, x1_intnodeOut_1 connect auto.int_out_3, x1_intnodeOut_2 connect auto.int_out_4, x1_intnodeOut_3 connect auto.int_out_5, x1_intnodeOut_4 connect auto.int_out_6, x1_intnodeOut_5 connect auto.int_out_7, x1_intnodeOut_6 connect dmiNodeIn, auto.dmi_in node _T = asAsyncReset(reset) wire _DMCONTROLReset_WIRE : { haltreq : UInt<1>, resumereq : UInt<1>, hartreset : UInt<1>, ackhavereset : UInt<1>, reserved0 : UInt<1>, hasel : UInt<1>, hartsello : UInt<10>, hartselhi : UInt<10>, reserved1 : UInt<2>, setresethaltreq : UInt<1>, clrresethaltreq : UInt<1>, ndmreset : UInt<1>, dmactive : UInt<1>} connect _DMCONTROLReset_WIRE.dmactive, UInt<1>(0h0) connect _DMCONTROLReset_WIRE.ndmreset, UInt<1>(0h0) connect _DMCONTROLReset_WIRE.clrresethaltreq, UInt<1>(0h0) connect _DMCONTROLReset_WIRE.setresethaltreq, UInt<1>(0h0) connect _DMCONTROLReset_WIRE.reserved1, UInt<2>(0h0) connect _DMCONTROLReset_WIRE.hartselhi, UInt<10>(0h0) connect _DMCONTROLReset_WIRE.hartsello, UInt<10>(0h0) connect _DMCONTROLReset_WIRE.hasel, UInt<1>(0h0) connect _DMCONTROLReset_WIRE.reserved0, UInt<1>(0h0) connect _DMCONTROLReset_WIRE.ackhavereset, UInt<1>(0h0) connect _DMCONTROLReset_WIRE.hartreset, UInt<1>(0h0) connect _DMCONTROLReset_WIRE.resumereq, UInt<1>(0h0) connect _DMCONTROLReset_WIRE.haltreq, UInt<1>(0h0) wire DMCONTROLReset : { haltreq : UInt<1>, resumereq : UInt<1>, hartreset : UInt<1>, ackhavereset : UInt<1>, reserved0 : UInt<1>, hasel : UInt<1>, hartsello : UInt<10>, hartselhi : UInt<10>, reserved1 : UInt<2>, setresethaltreq : UInt<1>, clrresethaltreq : UInt<1>, ndmreset : UInt<1>, dmactive : UInt<1>} connect DMCONTROLReset, _DMCONTROLReset_WIRE wire _DMCONTROLNxt_WIRE : { haltreq : UInt<1>, resumereq : UInt<1>, hartreset : UInt<1>, ackhavereset : UInt<1>, reserved0 : UInt<1>, hasel : UInt<1>, hartsello : UInt<10>, hartselhi : UInt<10>, reserved1 : UInt<2>, setresethaltreq : UInt<1>, clrresethaltreq : UInt<1>, ndmreset : UInt<1>, dmactive : UInt<1>} connect _DMCONTROLNxt_WIRE.dmactive, UInt<1>(0h0) connect _DMCONTROLNxt_WIRE.ndmreset, UInt<1>(0h0) connect _DMCONTROLNxt_WIRE.clrresethaltreq, UInt<1>(0h0) connect _DMCONTROLNxt_WIRE.setresethaltreq, UInt<1>(0h0) connect _DMCONTROLNxt_WIRE.reserved1, UInt<2>(0h0) connect _DMCONTROLNxt_WIRE.hartselhi, UInt<10>(0h0) connect _DMCONTROLNxt_WIRE.hartsello, UInt<10>(0h0) connect _DMCONTROLNxt_WIRE.hasel, UInt<1>(0h0) connect _DMCONTROLNxt_WIRE.reserved0, UInt<1>(0h0) connect _DMCONTROLNxt_WIRE.ackhavereset, UInt<1>(0h0) connect _DMCONTROLNxt_WIRE.hartreset, UInt<1>(0h0) connect _DMCONTROLNxt_WIRE.resumereq, UInt<1>(0h0) connect _DMCONTROLNxt_WIRE.haltreq, UInt<1>(0h0) wire DMCONTROLNxt : { haltreq : UInt<1>, resumereq : UInt<1>, hartreset : UInt<1>, ackhavereset : UInt<1>, reserved0 : UInt<1>, hasel : UInt<1>, hartsello : UInt<10>, hartselhi : UInt<10>, reserved1 : UInt<2>, setresethaltreq : UInt<1>, clrresethaltreq : UInt<1>, ndmreset : UInt<1>, dmactive : UInt<1>} connect DMCONTROLNxt, _DMCONTROLNxt_WIRE wire _DMCONTROLReg_WIRE : { haltreq : UInt<1>, resumereq : UInt<1>, hartreset : UInt<1>, ackhavereset : UInt<1>, reserved0 : UInt<1>, hasel : UInt<1>, hartsello : UInt<10>, hartselhi : UInt<10>, reserved1 : UInt<2>, setresethaltreq : UInt<1>, clrresethaltreq : UInt<1>, ndmreset : UInt<1>, dmactive : UInt<1>} connect _DMCONTROLReg_WIRE.dmactive, UInt<1>(0h0) connect _DMCONTROLReg_WIRE.ndmreset, UInt<1>(0h0) connect _DMCONTROLReg_WIRE.clrresethaltreq, UInt<1>(0h0) connect _DMCONTROLReg_WIRE.setresethaltreq, UInt<1>(0h0) connect _DMCONTROLReg_WIRE.reserved1, UInt<2>(0h0) connect _DMCONTROLReg_WIRE.hartselhi, UInt<10>(0h0) connect _DMCONTROLReg_WIRE.hartsello, UInt<10>(0h0) connect _DMCONTROLReg_WIRE.hasel, UInt<1>(0h0) connect _DMCONTROLReg_WIRE.reserved0, UInt<1>(0h0) connect _DMCONTROLReg_WIRE.ackhavereset, UInt<1>(0h0) connect _DMCONTROLReg_WIRE.hartreset, UInt<1>(0h0) connect _DMCONTROLReg_WIRE.resumereq, UInt<1>(0h0) connect _DMCONTROLReg_WIRE.haltreq, UInt<1>(0h0) regreset DMCONTROLReg : { haltreq : UInt<1>, resumereq : UInt<1>, hartreset : UInt<1>, ackhavereset : UInt<1>, reserved0 : UInt<1>, hasel : UInt<1>, hartsello : UInt<10>, hartselhi : UInt<10>, reserved1 : UInt<2>, setresethaltreq : UInt<1>, clrresethaltreq : UInt<1>, ndmreset : UInt<1>, dmactive : UInt<1>}, clock, _T, _DMCONTROLReg_WIRE connect DMCONTROLReg, DMCONTROLNxt wire _DMCONTROLWrData_WIRE : { haltreq : UInt<1>, resumereq : UInt<1>, hartreset : UInt<1>, ackhavereset : UInt<1>, reserved0 : UInt<1>, hasel : UInt<1>, hartsello : UInt<10>, hartselhi : UInt<10>, reserved1 : UInt<2>, setresethaltreq : UInt<1>, clrresethaltreq : UInt<1>, ndmreset : UInt<1>, dmactive : UInt<1>} connect _DMCONTROLWrData_WIRE.dmactive, UInt<1>(0h0) connect _DMCONTROLWrData_WIRE.ndmreset, UInt<1>(0h0) connect _DMCONTROLWrData_WIRE.clrresethaltreq, UInt<1>(0h0) connect _DMCONTROLWrData_WIRE.setresethaltreq, UInt<1>(0h0) connect _DMCONTROLWrData_WIRE.reserved1, UInt<2>(0h0) connect _DMCONTROLWrData_WIRE.hartselhi, UInt<10>(0h0) connect _DMCONTROLWrData_WIRE.hartsello, UInt<10>(0h0) connect _DMCONTROLWrData_WIRE.hasel, UInt<1>(0h0) connect _DMCONTROLWrData_WIRE.reserved0, UInt<1>(0h0) connect _DMCONTROLWrData_WIRE.ackhavereset, UInt<1>(0h0) connect _DMCONTROLWrData_WIRE.hartreset, UInt<1>(0h0) connect _DMCONTROLWrData_WIRE.resumereq, UInt<1>(0h0) connect _DMCONTROLWrData_WIRE.haltreq, UInt<1>(0h0) wire DMCONTROLWrData : { haltreq : UInt<1>, resumereq : UInt<1>, hartreset : UInt<1>, ackhavereset : UInt<1>, reserved0 : UInt<1>, hasel : UInt<1>, hartsello : UInt<10>, hartselhi : UInt<10>, reserved1 : UInt<2>, setresethaltreq : UInt<1>, clrresethaltreq : UInt<1>, ndmreset : UInt<1>, dmactive : UInt<1>} connect DMCONTROLWrData, _DMCONTROLWrData_WIRE wire dmactiveWrEn : UInt<1> connect dmactiveWrEn, UInt<1>(0h0) wire ndmresetWrEn : UInt<1> connect ndmresetWrEn, UInt<1>(0h0) wire clrresethaltreqWrEn : UInt<1> connect clrresethaltreqWrEn, UInt<1>(0h0) wire setresethaltreqWrEn : UInt<1> connect setresethaltreqWrEn, UInt<1>(0h0) wire hartselloWrEn : UInt<1> connect hartselloWrEn, UInt<1>(0h0) wire haselWrEn : UInt<1> connect haselWrEn, UInt<1>(0h0) wire ackhaveresetWrEn : UInt<1> connect ackhaveresetWrEn, UInt<1>(0h0) wire hartresetWrEn : UInt<1> connect hartresetWrEn, UInt<1>(0h0) wire resumereqWrEn : UInt<1> connect resumereqWrEn, UInt<1>(0h0) wire haltreqWrEn : UInt<1> connect haltreqWrEn, UInt<1>(0h0) connect DMCONTROLNxt, DMCONTROLReg node _T_1 = not(DMCONTROLReg.dmactive) when _T_1 : connect DMCONTROLNxt, DMCONTROLReset else : node _T_2 = and(UInt<1>(0h1), ndmresetWrEn) when _T_2 : connect DMCONTROLNxt.ndmreset, DMCONTROLWrData.ndmreset node _T_3 = and(UInt<1>(0h1), hartselloWrEn) when _T_3 : node _DMCONTROLNxt_hartsello_T = and(DMCONTROLWrData.hartsello, UInt<3>(0h7)) connect DMCONTROLNxt.hartsello, _DMCONTROLNxt_hartsello_T node _T_4 = and(UInt<1>(0h1), haselWrEn) when _T_4 : connect DMCONTROLNxt.hasel, DMCONTROLWrData.hasel node _T_5 = and(UInt<1>(0h1), hartresetWrEn) when _T_5 : connect DMCONTROLNxt.hartreset, DMCONTROLWrData.hartreset node _T_6 = and(UInt<1>(0h1), haltreqWrEn) when _T_6 : connect DMCONTROLNxt.haltreq, DMCONTROLWrData.haltreq when dmactiveWrEn : connect DMCONTROLNxt.dmactive, DMCONTROLWrData.dmactive wire _HARTINFORdData_WIRE : { reserved0 : UInt<8>, nscratch : UInt<4>, reserved1 : UInt<3>, dataaccess : UInt<1>, datasize : UInt<4>, dataaddr : UInt<12>} connect _HARTINFORdData_WIRE.dataaddr, UInt<12>(0h0) connect _HARTINFORdData_WIRE.datasize, UInt<4>(0h0) connect _HARTINFORdData_WIRE.dataaccess, UInt<1>(0h0) connect _HARTINFORdData_WIRE.reserved1, UInt<3>(0h0) connect _HARTINFORdData_WIRE.nscratch, UInt<4>(0h0) connect _HARTINFORdData_WIRE.reserved0, UInt<8>(0h0) wire HARTINFORdData : { reserved0 : UInt<8>, nscratch : UInt<4>, reserved1 : UInt<3>, dataaccess : UInt<1>, datasize : UInt<4>, dataaddr : UInt<12>} connect HARTINFORdData, _HARTINFORdData_WIRE when UInt<1>(0h1) : connect HARTINFORdData.dataaccess, UInt<1>(0h1) connect HARTINFORdData.datasize, UInt<4>(0h8) connect HARTINFORdData.dataaddr, UInt<10>(0h380) connect HARTINFORdData.nscratch, UInt<1>(0h1) wire _hamask_WIRE : UInt<1>[8] connect _hamask_WIRE[0], UInt<1>(0h0) connect _hamask_WIRE[1], UInt<1>(0h0) connect _hamask_WIRE[2], UInt<1>(0h0) connect _hamask_WIRE[3], UInt<1>(0h0) connect _hamask_WIRE[4], UInt<1>(0h0) connect _hamask_WIRE[5], UInt<1>(0h0) connect _hamask_WIRE[6], UInt<1>(0h0) connect _hamask_WIRE[7], UInt<1>(0h0) wire hamask : UInt<1>[8] connect hamask, _hamask_WIRE wire _HAWINDOWSELWrData_WIRE : { reserved0 : UInt<17>, hawindowsel : UInt<15>} connect _HAWINDOWSELWrData_WIRE.hawindowsel, UInt<15>(0h0) connect _HAWINDOWSELWrData_WIRE.reserved0, UInt<17>(0h0) wire HAWINDOWSELWrData : { reserved0 : UInt<17>, hawindowsel : UInt<15>} connect HAWINDOWSELWrData, _HAWINDOWSELWrData_WIRE wire HAWINDOWSELWrEn : UInt<1> connect HAWINDOWSELWrEn, UInt<1>(0h0) wire _HAWINDOWRdData_WIRE : { maskdata : UInt<32>} connect _HAWINDOWRdData_WIRE.maskdata, UInt<32>(0h0) wire HAWINDOWRdData : { maskdata : UInt<32>} connect HAWINDOWRdData, _HAWINDOWRdData_WIRE wire _HAWINDOWWrData_WIRE : { maskdata : UInt<32>} connect _HAWINDOWWrData_WIRE.maskdata, UInt<32>(0h0) wire HAWINDOWWrData : { maskdata : UInt<32>} connect HAWINDOWWrData, _HAWINDOWWrData_WIRE wire HAWINDOWWrEn : UInt<1> connect HAWINDOWWrEn, UInt<1>(0h0) wire _HAWINDOWSELNxt_WIRE : { reserved0 : UInt<17>, hawindowsel : UInt<15>} connect _HAWINDOWSELNxt_WIRE.hawindowsel, UInt<15>(0h0) connect _HAWINDOWSELNxt_WIRE.reserved0, UInt<17>(0h0) wire HAWINDOWSELNxt : { reserved0 : UInt<17>, hawindowsel : UInt<15>} connect HAWINDOWSELNxt, _HAWINDOWSELNxt_WIRE wire _HAWINDOWSELReg_WIRE : { reserved0 : UInt<17>, hawindowsel : UInt<15>} connect _HAWINDOWSELReg_WIRE.hawindowsel, UInt<15>(0h0) connect _HAWINDOWSELReg_WIRE.reserved0, UInt<17>(0h0) regreset HAWINDOWSELReg : { reserved0 : UInt<17>, hawindowsel : UInt<15>}, clock, _T, _HAWINDOWSELReg_WIRE connect HAWINDOWSELReg, HAWINDOWSELNxt wire _HAWINDOWSELReset_WIRE : { reserved0 : UInt<17>, hawindowsel : UInt<15>} connect _HAWINDOWSELReset_WIRE.hawindowsel, UInt<15>(0h0) connect _HAWINDOWSELReset_WIRE.reserved0, UInt<17>(0h0) wire HAWINDOWSELReset : { reserved0 : UInt<17>, hawindowsel : UInt<15>} connect HAWINDOWSELReset, _HAWINDOWSELReset_WIRE connect HAWINDOWSELNxt, HAWINDOWSELReg node _T_7 = not(DMCONTROLReg.dmactive) node _T_8 = not(UInt<1>(0h1)) node _T_9 = or(_T_7, _T_8) when _T_9 : connect HAWINDOWSELNxt, HAWINDOWSELReset else : when HAWINDOWSELWrEn : connect HAWINDOWSELNxt.hawindowsel, UInt<1>(0h0) connect HAWINDOWRdData.maskdata, UInt<1>(0h0) wire _HAMASKRst_WIRE : { maskdata : UInt<32>} connect _HAMASKRst_WIRE.maskdata, UInt<32>(0h0) wire HAMASKRst : { maskdata : UInt<32>} connect HAMASKRst, _HAMASKRst_WIRE wire _HAMASKNxt_WIRE : { maskdata : UInt<32>} connect _HAMASKNxt_WIRE.maskdata, UInt<32>(0h0) wire HAMASKNxt : { maskdata : UInt<32>} connect HAMASKNxt, _HAMASKNxt_WIRE wire _HAMASKReg_WIRE : { maskdata : UInt<32>} connect _HAMASKReg_WIRE.maskdata, UInt<32>(0h0) regreset HAMASKReg : { maskdata : UInt<32>}, clock, _T, _HAMASKReg_WIRE connect HAMASKReg, HAMASKNxt node _T_10 = eq(UInt<1>(0h0), HAWINDOWSELReg.hawindowsel) when _T_10 : node _HAWINDOWRdData_maskdata_T = and(HAMASKReg.maskdata, UInt<8>(0hff)) connect HAWINDOWRdData.maskdata, _HAWINDOWRdData_maskdata_T connect HAMASKNxt.maskdata, HAMASKReg.maskdata node _T_11 = not(DMCONTROLReg.dmactive) node _T_12 = not(UInt<1>(0h1)) node _T_13 = or(_T_11, _T_12) when _T_13 : connect HAMASKNxt, HAMASKRst else : node _T_14 = eq(UInt<1>(0h0), HAWINDOWSELReg.hawindowsel) node _T_15 = and(HAWINDOWWrEn, _T_14) when _T_15 : connect HAMASKNxt.maskdata, HAWINDOWWrData.maskdata node tempWrData_0 = bits(HAWINDOWWrData.maskdata, 0, 0) node tempWrData_1 = bits(HAWINDOWWrData.maskdata, 1, 1) node tempWrData_2 = bits(HAWINDOWWrData.maskdata, 2, 2) node tempWrData_3 = bits(HAWINDOWWrData.maskdata, 3, 3) node tempWrData_4 = bits(HAWINDOWWrData.maskdata, 4, 4) node tempWrData_5 = bits(HAWINDOWWrData.maskdata, 5, 5) node tempWrData_6 = bits(HAWINDOWWrData.maskdata, 6, 6) node tempWrData_7 = bits(HAWINDOWWrData.maskdata, 7, 7) node tempWrData_8 = bits(HAWINDOWWrData.maskdata, 8, 8) node tempWrData_9 = bits(HAWINDOWWrData.maskdata, 9, 9) node tempWrData_10 = bits(HAWINDOWWrData.maskdata, 10, 10) node tempWrData_11 = bits(HAWINDOWWrData.maskdata, 11, 11) node tempWrData_12 = bits(HAWINDOWWrData.maskdata, 12, 12) node tempWrData_13 = bits(HAWINDOWWrData.maskdata, 13, 13) node tempWrData_14 = bits(HAWINDOWWrData.maskdata, 14, 14) node tempWrData_15 = bits(HAWINDOWWrData.maskdata, 15, 15) node tempWrData_16 = bits(HAWINDOWWrData.maskdata, 16, 16) node tempWrData_17 = bits(HAWINDOWWrData.maskdata, 17, 17) node tempWrData_18 = bits(HAWINDOWWrData.maskdata, 18, 18) node tempWrData_19 = bits(HAWINDOWWrData.maskdata, 19, 19) node tempWrData_20 = bits(HAWINDOWWrData.maskdata, 20, 20) node tempWrData_21 = bits(HAWINDOWWrData.maskdata, 21, 21) node tempWrData_22 = bits(HAWINDOWWrData.maskdata, 22, 22) node tempWrData_23 = bits(HAWINDOWWrData.maskdata, 23, 23) node tempWrData_24 = bits(HAWINDOWWrData.maskdata, 24, 24) node tempWrData_25 = bits(HAWINDOWWrData.maskdata, 25, 25) node tempWrData_26 = bits(HAWINDOWWrData.maskdata, 26, 26) node tempWrData_27 = bits(HAWINDOWWrData.maskdata, 27, 27) node tempWrData_28 = bits(HAWINDOWWrData.maskdata, 28, 28) node tempWrData_29 = bits(HAWINDOWWrData.maskdata, 29, 29) node tempWrData_30 = bits(HAWINDOWWrData.maskdata, 30, 30) node tempWrData_31 = bits(HAWINDOWWrData.maskdata, 31, 31) node tempMaskReg_0 = bits(HAMASKReg.maskdata, 0, 0) node tempMaskReg_1 = bits(HAMASKReg.maskdata, 1, 1) node tempMaskReg_2 = bits(HAMASKReg.maskdata, 2, 2) node tempMaskReg_3 = bits(HAMASKReg.maskdata, 3, 3) node tempMaskReg_4 = bits(HAMASKReg.maskdata, 4, 4) node tempMaskReg_5 = bits(HAMASKReg.maskdata, 5, 5) node tempMaskReg_6 = bits(HAMASKReg.maskdata, 6, 6) node tempMaskReg_7 = bits(HAMASKReg.maskdata, 7, 7) node tempMaskReg_8 = bits(HAMASKReg.maskdata, 8, 8) node tempMaskReg_9 = bits(HAMASKReg.maskdata, 9, 9) node tempMaskReg_10 = bits(HAMASKReg.maskdata, 10, 10) node tempMaskReg_11 = bits(HAMASKReg.maskdata, 11, 11) node tempMaskReg_12 = bits(HAMASKReg.maskdata, 12, 12) node tempMaskReg_13 = bits(HAMASKReg.maskdata, 13, 13) node tempMaskReg_14 = bits(HAMASKReg.maskdata, 14, 14) node tempMaskReg_15 = bits(HAMASKReg.maskdata, 15, 15) node tempMaskReg_16 = bits(HAMASKReg.maskdata, 16, 16) node tempMaskReg_17 = bits(HAMASKReg.maskdata, 17, 17) node tempMaskReg_18 = bits(HAMASKReg.maskdata, 18, 18) node tempMaskReg_19 = bits(HAMASKReg.maskdata, 19, 19) node tempMaskReg_20 = bits(HAMASKReg.maskdata, 20, 20) node tempMaskReg_21 = bits(HAMASKReg.maskdata, 21, 21) node tempMaskReg_22 = bits(HAMASKReg.maskdata, 22, 22) node tempMaskReg_23 = bits(HAMASKReg.maskdata, 23, 23) node tempMaskReg_24 = bits(HAMASKReg.maskdata, 24, 24) node tempMaskReg_25 = bits(HAMASKReg.maskdata, 25, 25) node tempMaskReg_26 = bits(HAMASKReg.maskdata, 26, 26) node tempMaskReg_27 = bits(HAMASKReg.maskdata, 27, 27) node tempMaskReg_28 = bits(HAMASKReg.maskdata, 28, 28) node tempMaskReg_29 = bits(HAMASKReg.maskdata, 29, 29) node tempMaskReg_30 = bits(HAMASKReg.maskdata, 30, 30) node tempMaskReg_31 = bits(HAMASKReg.maskdata, 31, 31) node _T_16 = eq(UInt<1>(0h0), HAWINDOWSELReg.hawindowsel) node _T_17 = and(HAWINDOWWrEn, _T_16) when _T_17 : connect hamask[0], tempWrData_0 else : connect hamask[0], tempMaskReg_0 node tempWrData_0_1 = bits(HAWINDOWWrData.maskdata, 0, 0) node tempWrData_1_1 = bits(HAWINDOWWrData.maskdata, 1, 1) node tempWrData_2_1 = bits(HAWINDOWWrData.maskdata, 2, 2) node tempWrData_3_1 = bits(HAWINDOWWrData.maskdata, 3, 3) node tempWrData_4_1 = bits(HAWINDOWWrData.maskdata, 4, 4) node tempWrData_5_1 = bits(HAWINDOWWrData.maskdata, 5, 5) node tempWrData_6_1 = bits(HAWINDOWWrData.maskdata, 6, 6) node tempWrData_7_1 = bits(HAWINDOWWrData.maskdata, 7, 7) node tempWrData_8_1 = bits(HAWINDOWWrData.maskdata, 8, 8) node tempWrData_9_1 = bits(HAWINDOWWrData.maskdata, 9, 9) node tempWrData_10_1 = bits(HAWINDOWWrData.maskdata, 10, 10) node tempWrData_11_1 = bits(HAWINDOWWrData.maskdata, 11, 11) node tempWrData_12_1 = bits(HAWINDOWWrData.maskdata, 12, 12) node tempWrData_13_1 = bits(HAWINDOWWrData.maskdata, 13, 13) node tempWrData_14_1 = bits(HAWINDOWWrData.maskdata, 14, 14) node tempWrData_15_1 = bits(HAWINDOWWrData.maskdata, 15, 15) node tempWrData_16_1 = bits(HAWINDOWWrData.maskdata, 16, 16) node tempWrData_17_1 = bits(HAWINDOWWrData.maskdata, 17, 17) node tempWrData_18_1 = bits(HAWINDOWWrData.maskdata, 18, 18) node tempWrData_19_1 = bits(HAWINDOWWrData.maskdata, 19, 19) node tempWrData_20_1 = bits(HAWINDOWWrData.maskdata, 20, 20) node tempWrData_21_1 = bits(HAWINDOWWrData.maskdata, 21, 21) node tempWrData_22_1 = bits(HAWINDOWWrData.maskdata, 22, 22) node tempWrData_23_1 = bits(HAWINDOWWrData.maskdata, 23, 23) node tempWrData_24_1 = bits(HAWINDOWWrData.maskdata, 24, 24) node tempWrData_25_1 = bits(HAWINDOWWrData.maskdata, 25, 25) node tempWrData_26_1 = bits(HAWINDOWWrData.maskdata, 26, 26) node tempWrData_27_1 = bits(HAWINDOWWrData.maskdata, 27, 27) node tempWrData_28_1 = bits(HAWINDOWWrData.maskdata, 28, 28) node tempWrData_29_1 = bits(HAWINDOWWrData.maskdata, 29, 29) node tempWrData_30_1 = bits(HAWINDOWWrData.maskdata, 30, 30) node tempWrData_31_1 = bits(HAWINDOWWrData.maskdata, 31, 31) node tempMaskReg_0_1 = bits(HAMASKReg.maskdata, 0, 0) node tempMaskReg_1_1 = bits(HAMASKReg.maskdata, 1, 1) node tempMaskReg_2_1 = bits(HAMASKReg.maskdata, 2, 2) node tempMaskReg_3_1 = bits(HAMASKReg.maskdata, 3, 3) node tempMaskReg_4_1 = bits(HAMASKReg.maskdata, 4, 4) node tempMaskReg_5_1 = bits(HAMASKReg.maskdata, 5, 5) node tempMaskReg_6_1 = bits(HAMASKReg.maskdata, 6, 6) node tempMaskReg_7_1 = bits(HAMASKReg.maskdata, 7, 7) node tempMaskReg_8_1 = bits(HAMASKReg.maskdata, 8, 8) node tempMaskReg_9_1 = bits(HAMASKReg.maskdata, 9, 9) node tempMaskReg_10_1 = bits(HAMASKReg.maskdata, 10, 10) node tempMaskReg_11_1 = bits(HAMASKReg.maskdata, 11, 11) node tempMaskReg_12_1 = bits(HAMASKReg.maskdata, 12, 12) node tempMaskReg_13_1 = bits(HAMASKReg.maskdata, 13, 13) node tempMaskReg_14_1 = bits(HAMASKReg.maskdata, 14, 14) node tempMaskReg_15_1 = bits(HAMASKReg.maskdata, 15, 15) node tempMaskReg_16_1 = bits(HAMASKReg.maskdata, 16, 16) node tempMaskReg_17_1 = bits(HAMASKReg.maskdata, 17, 17) node tempMaskReg_18_1 = bits(HAMASKReg.maskdata, 18, 18) node tempMaskReg_19_1 = bits(HAMASKReg.maskdata, 19, 19) node tempMaskReg_20_1 = bits(HAMASKReg.maskdata, 20, 20) node tempMaskReg_21_1 = bits(HAMASKReg.maskdata, 21, 21) node tempMaskReg_22_1 = bits(HAMASKReg.maskdata, 22, 22) node tempMaskReg_23_1 = bits(HAMASKReg.maskdata, 23, 23) node tempMaskReg_24_1 = bits(HAMASKReg.maskdata, 24, 24) node tempMaskReg_25_1 = bits(HAMASKReg.maskdata, 25, 25) node tempMaskReg_26_1 = bits(HAMASKReg.maskdata, 26, 26) node tempMaskReg_27_1 = bits(HAMASKReg.maskdata, 27, 27) node tempMaskReg_28_1 = bits(HAMASKReg.maskdata, 28, 28) node tempMaskReg_29_1 = bits(HAMASKReg.maskdata, 29, 29) node tempMaskReg_30_1 = bits(HAMASKReg.maskdata, 30, 30) node tempMaskReg_31_1 = bits(HAMASKReg.maskdata, 31, 31) node _T_18 = eq(UInt<1>(0h0), HAWINDOWSELReg.hawindowsel) node _T_19 = and(HAWINDOWWrEn, _T_18) when _T_19 : connect hamask[1], tempWrData_1_1 else : connect hamask[1], tempMaskReg_1_1 node tempWrData_0_2 = bits(HAWINDOWWrData.maskdata, 0, 0) node tempWrData_1_2 = bits(HAWINDOWWrData.maskdata, 1, 1) node tempWrData_2_2 = bits(HAWINDOWWrData.maskdata, 2, 2) node tempWrData_3_2 = bits(HAWINDOWWrData.maskdata, 3, 3) node tempWrData_4_2 = bits(HAWINDOWWrData.maskdata, 4, 4) node tempWrData_5_2 = bits(HAWINDOWWrData.maskdata, 5, 5) node tempWrData_6_2 = bits(HAWINDOWWrData.maskdata, 6, 6) node tempWrData_7_2 = bits(HAWINDOWWrData.maskdata, 7, 7) node tempWrData_8_2 = bits(HAWINDOWWrData.maskdata, 8, 8) node tempWrData_9_2 = bits(HAWINDOWWrData.maskdata, 9, 9) node tempWrData_10_2 = bits(HAWINDOWWrData.maskdata, 10, 10) node tempWrData_11_2 = bits(HAWINDOWWrData.maskdata, 11, 11) node tempWrData_12_2 = bits(HAWINDOWWrData.maskdata, 12, 12) node tempWrData_13_2 = bits(HAWINDOWWrData.maskdata, 13, 13) node tempWrData_14_2 = bits(HAWINDOWWrData.maskdata, 14, 14) node tempWrData_15_2 = bits(HAWINDOWWrData.maskdata, 15, 15) node tempWrData_16_2 = bits(HAWINDOWWrData.maskdata, 16, 16) node tempWrData_17_2 = bits(HAWINDOWWrData.maskdata, 17, 17) node tempWrData_18_2 = bits(HAWINDOWWrData.maskdata, 18, 18) node tempWrData_19_2 = bits(HAWINDOWWrData.maskdata, 19, 19) node tempWrData_20_2 = bits(HAWINDOWWrData.maskdata, 20, 20) node tempWrData_21_2 = bits(HAWINDOWWrData.maskdata, 21, 21) node tempWrData_22_2 = bits(HAWINDOWWrData.maskdata, 22, 22) node tempWrData_23_2 = bits(HAWINDOWWrData.maskdata, 23, 23) node tempWrData_24_2 = bits(HAWINDOWWrData.maskdata, 24, 24) node tempWrData_25_2 = bits(HAWINDOWWrData.maskdata, 25, 25) node tempWrData_26_2 = bits(HAWINDOWWrData.maskdata, 26, 26) node tempWrData_27_2 = bits(HAWINDOWWrData.maskdata, 27, 27) node tempWrData_28_2 = bits(HAWINDOWWrData.maskdata, 28, 28) node tempWrData_29_2 = bits(HAWINDOWWrData.maskdata, 29, 29) node tempWrData_30_2 = bits(HAWINDOWWrData.maskdata, 30, 30) node tempWrData_31_2 = bits(HAWINDOWWrData.maskdata, 31, 31) node tempMaskReg_0_2 = bits(HAMASKReg.maskdata, 0, 0) node tempMaskReg_1_2 = bits(HAMASKReg.maskdata, 1, 1) node tempMaskReg_2_2 = bits(HAMASKReg.maskdata, 2, 2) node tempMaskReg_3_2 = bits(HAMASKReg.maskdata, 3, 3) node tempMaskReg_4_2 = bits(HAMASKReg.maskdata, 4, 4) node tempMaskReg_5_2 = bits(HAMASKReg.maskdata, 5, 5) node tempMaskReg_6_2 = bits(HAMASKReg.maskdata, 6, 6) node tempMaskReg_7_2 = bits(HAMASKReg.maskdata, 7, 7) node tempMaskReg_8_2 = bits(HAMASKReg.maskdata, 8, 8) node tempMaskReg_9_2 = bits(HAMASKReg.maskdata, 9, 9) node tempMaskReg_10_2 = bits(HAMASKReg.maskdata, 10, 10) node tempMaskReg_11_2 = bits(HAMASKReg.maskdata, 11, 11) node tempMaskReg_12_2 = bits(HAMASKReg.maskdata, 12, 12) node tempMaskReg_13_2 = bits(HAMASKReg.maskdata, 13, 13) node tempMaskReg_14_2 = bits(HAMASKReg.maskdata, 14, 14) node tempMaskReg_15_2 = bits(HAMASKReg.maskdata, 15, 15) node tempMaskReg_16_2 = bits(HAMASKReg.maskdata, 16, 16) node tempMaskReg_17_2 = bits(HAMASKReg.maskdata, 17, 17) node tempMaskReg_18_2 = bits(HAMASKReg.maskdata, 18, 18) node tempMaskReg_19_2 = bits(HAMASKReg.maskdata, 19, 19) node tempMaskReg_20_2 = bits(HAMASKReg.maskdata, 20, 20) node tempMaskReg_21_2 = bits(HAMASKReg.maskdata, 21, 21) node tempMaskReg_22_2 = bits(HAMASKReg.maskdata, 22, 22) node tempMaskReg_23_2 = bits(HAMASKReg.maskdata, 23, 23) node tempMaskReg_24_2 = bits(HAMASKReg.maskdata, 24, 24) node tempMaskReg_25_2 = bits(HAMASKReg.maskdata, 25, 25) node tempMaskReg_26_2 = bits(HAMASKReg.maskdata, 26, 26) node tempMaskReg_27_2 = bits(HAMASKReg.maskdata, 27, 27) node tempMaskReg_28_2 = bits(HAMASKReg.maskdata, 28, 28) node tempMaskReg_29_2 = bits(HAMASKReg.maskdata, 29, 29) node tempMaskReg_30_2 = bits(HAMASKReg.maskdata, 30, 30) node tempMaskReg_31_2 = bits(HAMASKReg.maskdata, 31, 31) node _T_20 = eq(UInt<1>(0h0), HAWINDOWSELReg.hawindowsel) node _T_21 = and(HAWINDOWWrEn, _T_20) when _T_21 : connect hamask[2], tempWrData_2_2 else : connect hamask[2], tempMaskReg_2_2 node tempWrData_0_3 = bits(HAWINDOWWrData.maskdata, 0, 0) node tempWrData_1_3 = bits(HAWINDOWWrData.maskdata, 1, 1) node tempWrData_2_3 = bits(HAWINDOWWrData.maskdata, 2, 2) node tempWrData_3_3 = bits(HAWINDOWWrData.maskdata, 3, 3) node tempWrData_4_3 = bits(HAWINDOWWrData.maskdata, 4, 4) node tempWrData_5_3 = bits(HAWINDOWWrData.maskdata, 5, 5) node tempWrData_6_3 = bits(HAWINDOWWrData.maskdata, 6, 6) node tempWrData_7_3 = bits(HAWINDOWWrData.maskdata, 7, 7) node tempWrData_8_3 = bits(HAWINDOWWrData.maskdata, 8, 8) node tempWrData_9_3 = bits(HAWINDOWWrData.maskdata, 9, 9) node tempWrData_10_3 = bits(HAWINDOWWrData.maskdata, 10, 10) node tempWrData_11_3 = bits(HAWINDOWWrData.maskdata, 11, 11) node tempWrData_12_3 = bits(HAWINDOWWrData.maskdata, 12, 12) node tempWrData_13_3 = bits(HAWINDOWWrData.maskdata, 13, 13) node tempWrData_14_3 = bits(HAWINDOWWrData.maskdata, 14, 14) node tempWrData_15_3 = bits(HAWINDOWWrData.maskdata, 15, 15) node tempWrData_16_3 = bits(HAWINDOWWrData.maskdata, 16, 16) node tempWrData_17_3 = bits(HAWINDOWWrData.maskdata, 17, 17) node tempWrData_18_3 = bits(HAWINDOWWrData.maskdata, 18, 18) node tempWrData_19_3 = bits(HAWINDOWWrData.maskdata, 19, 19) node tempWrData_20_3 = bits(HAWINDOWWrData.maskdata, 20, 20) node tempWrData_21_3 = bits(HAWINDOWWrData.maskdata, 21, 21) node tempWrData_22_3 = bits(HAWINDOWWrData.maskdata, 22, 22) node tempWrData_23_3 = bits(HAWINDOWWrData.maskdata, 23, 23) node tempWrData_24_3 = bits(HAWINDOWWrData.maskdata, 24, 24) node tempWrData_25_3 = bits(HAWINDOWWrData.maskdata, 25, 25) node tempWrData_26_3 = bits(HAWINDOWWrData.maskdata, 26, 26) node tempWrData_27_3 = bits(HAWINDOWWrData.maskdata, 27, 27) node tempWrData_28_3 = bits(HAWINDOWWrData.maskdata, 28, 28) node tempWrData_29_3 = bits(HAWINDOWWrData.maskdata, 29, 29) node tempWrData_30_3 = bits(HAWINDOWWrData.maskdata, 30, 30) node tempWrData_31_3 = bits(HAWINDOWWrData.maskdata, 31, 31) node tempMaskReg_0_3 = bits(HAMASKReg.maskdata, 0, 0) node tempMaskReg_1_3 = bits(HAMASKReg.maskdata, 1, 1) node tempMaskReg_2_3 = bits(HAMASKReg.maskdata, 2, 2) node tempMaskReg_3_3 = bits(HAMASKReg.maskdata, 3, 3) node tempMaskReg_4_3 = bits(HAMASKReg.maskdata, 4, 4) node tempMaskReg_5_3 = bits(HAMASKReg.maskdata, 5, 5) node tempMaskReg_6_3 = bits(HAMASKReg.maskdata, 6, 6) node tempMaskReg_7_3 = bits(HAMASKReg.maskdata, 7, 7) node tempMaskReg_8_3 = bits(HAMASKReg.maskdata, 8, 8) node tempMaskReg_9_3 = bits(HAMASKReg.maskdata, 9, 9) node tempMaskReg_10_3 = bits(HAMASKReg.maskdata, 10, 10) node tempMaskReg_11_3 = bits(HAMASKReg.maskdata, 11, 11) node tempMaskReg_12_3 = bits(HAMASKReg.maskdata, 12, 12) node tempMaskReg_13_3 = bits(HAMASKReg.maskdata, 13, 13) node tempMaskReg_14_3 = bits(HAMASKReg.maskdata, 14, 14) node tempMaskReg_15_3 = bits(HAMASKReg.maskdata, 15, 15) node tempMaskReg_16_3 = bits(HAMASKReg.maskdata, 16, 16) node tempMaskReg_17_3 = bits(HAMASKReg.maskdata, 17, 17) node tempMaskReg_18_3 = bits(HAMASKReg.maskdata, 18, 18) node tempMaskReg_19_3 = bits(HAMASKReg.maskdata, 19, 19) node tempMaskReg_20_3 = bits(HAMASKReg.maskdata, 20, 20) node tempMaskReg_21_3 = bits(HAMASKReg.maskdata, 21, 21) node tempMaskReg_22_3 = bits(HAMASKReg.maskdata, 22, 22) node tempMaskReg_23_3 = bits(HAMASKReg.maskdata, 23, 23) node tempMaskReg_24_3 = bits(HAMASKReg.maskdata, 24, 24) node tempMaskReg_25_3 = bits(HAMASKReg.maskdata, 25, 25) node tempMaskReg_26_3 = bits(HAMASKReg.maskdata, 26, 26) node tempMaskReg_27_3 = bits(HAMASKReg.maskdata, 27, 27) node tempMaskReg_28_3 = bits(HAMASKReg.maskdata, 28, 28) node tempMaskReg_29_3 = bits(HAMASKReg.maskdata, 29, 29) node tempMaskReg_30_3 = bits(HAMASKReg.maskdata, 30, 30) node tempMaskReg_31_3 = bits(HAMASKReg.maskdata, 31, 31) node _T_22 = eq(UInt<1>(0h0), HAWINDOWSELReg.hawindowsel) node _T_23 = and(HAWINDOWWrEn, _T_22) when _T_23 : connect hamask[3], tempWrData_3_3 else : connect hamask[3], tempMaskReg_3_3 node tempWrData_0_4 = bits(HAWINDOWWrData.maskdata, 0, 0) node tempWrData_1_4 = bits(HAWINDOWWrData.maskdata, 1, 1) node tempWrData_2_4 = bits(HAWINDOWWrData.maskdata, 2, 2) node tempWrData_3_4 = bits(HAWINDOWWrData.maskdata, 3, 3) node tempWrData_4_4 = bits(HAWINDOWWrData.maskdata, 4, 4) node tempWrData_5_4 = bits(HAWINDOWWrData.maskdata, 5, 5) node tempWrData_6_4 = bits(HAWINDOWWrData.maskdata, 6, 6) node tempWrData_7_4 = bits(HAWINDOWWrData.maskdata, 7, 7) node tempWrData_8_4 = bits(HAWINDOWWrData.maskdata, 8, 8) node tempWrData_9_4 = bits(HAWINDOWWrData.maskdata, 9, 9) node tempWrData_10_4 = bits(HAWINDOWWrData.maskdata, 10, 10) node tempWrData_11_4 = bits(HAWINDOWWrData.maskdata, 11, 11) node tempWrData_12_4 = bits(HAWINDOWWrData.maskdata, 12, 12) node tempWrData_13_4 = bits(HAWINDOWWrData.maskdata, 13, 13) node tempWrData_14_4 = bits(HAWINDOWWrData.maskdata, 14, 14) node tempWrData_15_4 = bits(HAWINDOWWrData.maskdata, 15, 15) node tempWrData_16_4 = bits(HAWINDOWWrData.maskdata, 16, 16) node tempWrData_17_4 = bits(HAWINDOWWrData.maskdata, 17, 17) node tempWrData_18_4 = bits(HAWINDOWWrData.maskdata, 18, 18) node tempWrData_19_4 = bits(HAWINDOWWrData.maskdata, 19, 19) node tempWrData_20_4 = bits(HAWINDOWWrData.maskdata, 20, 20) node tempWrData_21_4 = bits(HAWINDOWWrData.maskdata, 21, 21) node tempWrData_22_4 = bits(HAWINDOWWrData.maskdata, 22, 22) node tempWrData_23_4 = bits(HAWINDOWWrData.maskdata, 23, 23) node tempWrData_24_4 = bits(HAWINDOWWrData.maskdata, 24, 24) node tempWrData_25_4 = bits(HAWINDOWWrData.maskdata, 25, 25) node tempWrData_26_4 = bits(HAWINDOWWrData.maskdata, 26, 26) node tempWrData_27_4 = bits(HAWINDOWWrData.maskdata, 27, 27) node tempWrData_28_4 = bits(HAWINDOWWrData.maskdata, 28, 28) node tempWrData_29_4 = bits(HAWINDOWWrData.maskdata, 29, 29) node tempWrData_30_4 = bits(HAWINDOWWrData.maskdata, 30, 30) node tempWrData_31_4 = bits(HAWINDOWWrData.maskdata, 31, 31) node tempMaskReg_0_4 = bits(HAMASKReg.maskdata, 0, 0) node tempMaskReg_1_4 = bits(HAMASKReg.maskdata, 1, 1) node tempMaskReg_2_4 = bits(HAMASKReg.maskdata, 2, 2) node tempMaskReg_3_4 = bits(HAMASKReg.maskdata, 3, 3) node tempMaskReg_4_4 = bits(HAMASKReg.maskdata, 4, 4) node tempMaskReg_5_4 = bits(HAMASKReg.maskdata, 5, 5) node tempMaskReg_6_4 = bits(HAMASKReg.maskdata, 6, 6) node tempMaskReg_7_4 = bits(HAMASKReg.maskdata, 7, 7) node tempMaskReg_8_4 = bits(HAMASKReg.maskdata, 8, 8) node tempMaskReg_9_4 = bits(HAMASKReg.maskdata, 9, 9) node tempMaskReg_10_4 = bits(HAMASKReg.maskdata, 10, 10) node tempMaskReg_11_4 = bits(HAMASKReg.maskdata, 11, 11) node tempMaskReg_12_4 = bits(HAMASKReg.maskdata, 12, 12) node tempMaskReg_13_4 = bits(HAMASKReg.maskdata, 13, 13) node tempMaskReg_14_4 = bits(HAMASKReg.maskdata, 14, 14) node tempMaskReg_15_4 = bits(HAMASKReg.maskdata, 15, 15) node tempMaskReg_16_4 = bits(HAMASKReg.maskdata, 16, 16) node tempMaskReg_17_4 = bits(HAMASKReg.maskdata, 17, 17) node tempMaskReg_18_4 = bits(HAMASKReg.maskdata, 18, 18) node tempMaskReg_19_4 = bits(HAMASKReg.maskdata, 19, 19) node tempMaskReg_20_4 = bits(HAMASKReg.maskdata, 20, 20) node tempMaskReg_21_4 = bits(HAMASKReg.maskdata, 21, 21) node tempMaskReg_22_4 = bits(HAMASKReg.maskdata, 22, 22) node tempMaskReg_23_4 = bits(HAMASKReg.maskdata, 23, 23) node tempMaskReg_24_4 = bits(HAMASKReg.maskdata, 24, 24) node tempMaskReg_25_4 = bits(HAMASKReg.maskdata, 25, 25) node tempMaskReg_26_4 = bits(HAMASKReg.maskdata, 26, 26) node tempMaskReg_27_4 = bits(HAMASKReg.maskdata, 27, 27) node tempMaskReg_28_4 = bits(HAMASKReg.maskdata, 28, 28) node tempMaskReg_29_4 = bits(HAMASKReg.maskdata, 29, 29) node tempMaskReg_30_4 = bits(HAMASKReg.maskdata, 30, 30) node tempMaskReg_31_4 = bits(HAMASKReg.maskdata, 31, 31) node _T_24 = eq(UInt<1>(0h0), HAWINDOWSELReg.hawindowsel) node _T_25 = and(HAWINDOWWrEn, _T_24) when _T_25 : connect hamask[4], tempWrData_4_4 else : connect hamask[4], tempMaskReg_4_4 node tempWrData_0_5 = bits(HAWINDOWWrData.maskdata, 0, 0) node tempWrData_1_5 = bits(HAWINDOWWrData.maskdata, 1, 1) node tempWrData_2_5 = bits(HAWINDOWWrData.maskdata, 2, 2) node tempWrData_3_5 = bits(HAWINDOWWrData.maskdata, 3, 3) node tempWrData_4_5 = bits(HAWINDOWWrData.maskdata, 4, 4) node tempWrData_5_5 = bits(HAWINDOWWrData.maskdata, 5, 5) node tempWrData_6_5 = bits(HAWINDOWWrData.maskdata, 6, 6) node tempWrData_7_5 = bits(HAWINDOWWrData.maskdata, 7, 7) node tempWrData_8_5 = bits(HAWINDOWWrData.maskdata, 8, 8) node tempWrData_9_5 = bits(HAWINDOWWrData.maskdata, 9, 9) node tempWrData_10_5 = bits(HAWINDOWWrData.maskdata, 10, 10) node tempWrData_11_5 = bits(HAWINDOWWrData.maskdata, 11, 11) node tempWrData_12_5 = bits(HAWINDOWWrData.maskdata, 12, 12) node tempWrData_13_5 = bits(HAWINDOWWrData.maskdata, 13, 13) node tempWrData_14_5 = bits(HAWINDOWWrData.maskdata, 14, 14) node tempWrData_15_5 = bits(HAWINDOWWrData.maskdata, 15, 15) node tempWrData_16_5 = bits(HAWINDOWWrData.maskdata, 16, 16) node tempWrData_17_5 = bits(HAWINDOWWrData.maskdata, 17, 17) node tempWrData_18_5 = bits(HAWINDOWWrData.maskdata, 18, 18) node tempWrData_19_5 = bits(HAWINDOWWrData.maskdata, 19, 19) node tempWrData_20_5 = bits(HAWINDOWWrData.maskdata, 20, 20) node tempWrData_21_5 = bits(HAWINDOWWrData.maskdata, 21, 21) node tempWrData_22_5 = bits(HAWINDOWWrData.maskdata, 22, 22) node tempWrData_23_5 = bits(HAWINDOWWrData.maskdata, 23, 23) node tempWrData_24_5 = bits(HAWINDOWWrData.maskdata, 24, 24) node tempWrData_25_5 = bits(HAWINDOWWrData.maskdata, 25, 25) node tempWrData_26_5 = bits(HAWINDOWWrData.maskdata, 26, 26) node tempWrData_27_5 = bits(HAWINDOWWrData.maskdata, 27, 27) node tempWrData_28_5 = bits(HAWINDOWWrData.maskdata, 28, 28) node tempWrData_29_5 = bits(HAWINDOWWrData.maskdata, 29, 29) node tempWrData_30_5 = bits(HAWINDOWWrData.maskdata, 30, 30) node tempWrData_31_5 = bits(HAWINDOWWrData.maskdata, 31, 31) node tempMaskReg_0_5 = bits(HAMASKReg.maskdata, 0, 0) node tempMaskReg_1_5 = bits(HAMASKReg.maskdata, 1, 1) node tempMaskReg_2_5 = bits(HAMASKReg.maskdata, 2, 2) node tempMaskReg_3_5 = bits(HAMASKReg.maskdata, 3, 3) node tempMaskReg_4_5 = bits(HAMASKReg.maskdata, 4, 4) node tempMaskReg_5_5 = bits(HAMASKReg.maskdata, 5, 5) node tempMaskReg_6_5 = bits(HAMASKReg.maskdata, 6, 6) node tempMaskReg_7_5 = bits(HAMASKReg.maskdata, 7, 7) node tempMaskReg_8_5 = bits(HAMASKReg.maskdata, 8, 8) node tempMaskReg_9_5 = bits(HAMASKReg.maskdata, 9, 9) node tempMaskReg_10_5 = bits(HAMASKReg.maskdata, 10, 10) node tempMaskReg_11_5 = bits(HAMASKReg.maskdata, 11, 11) node tempMaskReg_12_5 = bits(HAMASKReg.maskdata, 12, 12) node tempMaskReg_13_5 = bits(HAMASKReg.maskdata, 13, 13) node tempMaskReg_14_5 = bits(HAMASKReg.maskdata, 14, 14) node tempMaskReg_15_5 = bits(HAMASKReg.maskdata, 15, 15) node tempMaskReg_16_5 = bits(HAMASKReg.maskdata, 16, 16) node tempMaskReg_17_5 = bits(HAMASKReg.maskdata, 17, 17) node tempMaskReg_18_5 = bits(HAMASKReg.maskdata, 18, 18) node tempMaskReg_19_5 = bits(HAMASKReg.maskdata, 19, 19) node tempMaskReg_20_5 = bits(HAMASKReg.maskdata, 20, 20) node tempMaskReg_21_5 = bits(HAMASKReg.maskdata, 21, 21) node tempMaskReg_22_5 = bits(HAMASKReg.maskdata, 22, 22) node tempMaskReg_23_5 = bits(HAMASKReg.maskdata, 23, 23) node tempMaskReg_24_5 = bits(HAMASKReg.maskdata, 24, 24) node tempMaskReg_25_5 = bits(HAMASKReg.maskdata, 25, 25) node tempMaskReg_26_5 = bits(HAMASKReg.maskdata, 26, 26) node tempMaskReg_27_5 = bits(HAMASKReg.maskdata, 27, 27) node tempMaskReg_28_5 = bits(HAMASKReg.maskdata, 28, 28) node tempMaskReg_29_5 = bits(HAMASKReg.maskdata, 29, 29) node tempMaskReg_30_5 = bits(HAMASKReg.maskdata, 30, 30) node tempMaskReg_31_5 = bits(HAMASKReg.maskdata, 31, 31) node _T_26 = eq(UInt<1>(0h0), HAWINDOWSELReg.hawindowsel) node _T_27 = and(HAWINDOWWrEn, _T_26) when _T_27 : connect hamask[5], tempWrData_5_5 else : connect hamask[5], tempMaskReg_5_5 node tempWrData_0_6 = bits(HAWINDOWWrData.maskdata, 0, 0) node tempWrData_1_6 = bits(HAWINDOWWrData.maskdata, 1, 1) node tempWrData_2_6 = bits(HAWINDOWWrData.maskdata, 2, 2) node tempWrData_3_6 = bits(HAWINDOWWrData.maskdata, 3, 3) node tempWrData_4_6 = bits(HAWINDOWWrData.maskdata, 4, 4) node tempWrData_5_6 = bits(HAWINDOWWrData.maskdata, 5, 5) node tempWrData_6_6 = bits(HAWINDOWWrData.maskdata, 6, 6) node tempWrData_7_6 = bits(HAWINDOWWrData.maskdata, 7, 7) node tempWrData_8_6 = bits(HAWINDOWWrData.maskdata, 8, 8) node tempWrData_9_6 = bits(HAWINDOWWrData.maskdata, 9, 9) node tempWrData_10_6 = bits(HAWINDOWWrData.maskdata, 10, 10) node tempWrData_11_6 = bits(HAWINDOWWrData.maskdata, 11, 11) node tempWrData_12_6 = bits(HAWINDOWWrData.maskdata, 12, 12) node tempWrData_13_6 = bits(HAWINDOWWrData.maskdata, 13, 13) node tempWrData_14_6 = bits(HAWINDOWWrData.maskdata, 14, 14) node tempWrData_15_6 = bits(HAWINDOWWrData.maskdata, 15, 15) node tempWrData_16_6 = bits(HAWINDOWWrData.maskdata, 16, 16) node tempWrData_17_6 = bits(HAWINDOWWrData.maskdata, 17, 17) node tempWrData_18_6 = bits(HAWINDOWWrData.maskdata, 18, 18) node tempWrData_19_6 = bits(HAWINDOWWrData.maskdata, 19, 19) node tempWrData_20_6 = bits(HAWINDOWWrData.maskdata, 20, 20) node tempWrData_21_6 = bits(HAWINDOWWrData.maskdata, 21, 21) node tempWrData_22_6 = bits(HAWINDOWWrData.maskdata, 22, 22) node tempWrData_23_6 = bits(HAWINDOWWrData.maskdata, 23, 23) node tempWrData_24_6 = bits(HAWINDOWWrData.maskdata, 24, 24) node tempWrData_25_6 = bits(HAWINDOWWrData.maskdata, 25, 25) node tempWrData_26_6 = bits(HAWINDOWWrData.maskdata, 26, 26) node tempWrData_27_6 = bits(HAWINDOWWrData.maskdata, 27, 27) node tempWrData_28_6 = bits(HAWINDOWWrData.maskdata, 28, 28) node tempWrData_29_6 = bits(HAWINDOWWrData.maskdata, 29, 29) node tempWrData_30_6 = bits(HAWINDOWWrData.maskdata, 30, 30) node tempWrData_31_6 = bits(HAWINDOWWrData.maskdata, 31, 31) node tempMaskReg_0_6 = bits(HAMASKReg.maskdata, 0, 0) node tempMaskReg_1_6 = bits(HAMASKReg.maskdata, 1, 1) node tempMaskReg_2_6 = bits(HAMASKReg.maskdata, 2, 2) node tempMaskReg_3_6 = bits(HAMASKReg.maskdata, 3, 3) node tempMaskReg_4_6 = bits(HAMASKReg.maskdata, 4, 4) node tempMaskReg_5_6 = bits(HAMASKReg.maskdata, 5, 5) node tempMaskReg_6_6 = bits(HAMASKReg.maskdata, 6, 6) node tempMaskReg_7_6 = bits(HAMASKReg.maskdata, 7, 7) node tempMaskReg_8_6 = bits(HAMASKReg.maskdata, 8, 8) node tempMaskReg_9_6 = bits(HAMASKReg.maskdata, 9, 9) node tempMaskReg_10_6 = bits(HAMASKReg.maskdata, 10, 10) node tempMaskReg_11_6 = bits(HAMASKReg.maskdata, 11, 11) node tempMaskReg_12_6 = bits(HAMASKReg.maskdata, 12, 12) node tempMaskReg_13_6 = bits(HAMASKReg.maskdata, 13, 13) node tempMaskReg_14_6 = bits(HAMASKReg.maskdata, 14, 14) node tempMaskReg_15_6 = bits(HAMASKReg.maskdata, 15, 15) node tempMaskReg_16_6 = bits(HAMASKReg.maskdata, 16, 16) node tempMaskReg_17_6 = bits(HAMASKReg.maskdata, 17, 17) node tempMaskReg_18_6 = bits(HAMASKReg.maskdata, 18, 18) node tempMaskReg_19_6 = bits(HAMASKReg.maskdata, 19, 19) node tempMaskReg_20_6 = bits(HAMASKReg.maskdata, 20, 20) node tempMaskReg_21_6 = bits(HAMASKReg.maskdata, 21, 21) node tempMaskReg_22_6 = bits(HAMASKReg.maskdata, 22, 22) node tempMaskReg_23_6 = bits(HAMASKReg.maskdata, 23, 23) node tempMaskReg_24_6 = bits(HAMASKReg.maskdata, 24, 24) node tempMaskReg_25_6 = bits(HAMASKReg.maskdata, 25, 25) node tempMaskReg_26_6 = bits(HAMASKReg.maskdata, 26, 26) node tempMaskReg_27_6 = bits(HAMASKReg.maskdata, 27, 27) node tempMaskReg_28_6 = bits(HAMASKReg.maskdata, 28, 28) node tempMaskReg_29_6 = bits(HAMASKReg.maskdata, 29, 29) node tempMaskReg_30_6 = bits(HAMASKReg.maskdata, 30, 30) node tempMaskReg_31_6 = bits(HAMASKReg.maskdata, 31, 31) node _T_28 = eq(UInt<1>(0h0), HAWINDOWSELReg.hawindowsel) node _T_29 = and(HAWINDOWWrEn, _T_28) when _T_29 : connect hamask[6], tempWrData_6_6 else : connect hamask[6], tempMaskReg_6_6 node tempWrData_0_7 = bits(HAWINDOWWrData.maskdata, 0, 0) node tempWrData_1_7 = bits(HAWINDOWWrData.maskdata, 1, 1) node tempWrData_2_7 = bits(HAWINDOWWrData.maskdata, 2, 2) node tempWrData_3_7 = bits(HAWINDOWWrData.maskdata, 3, 3) node tempWrData_4_7 = bits(HAWINDOWWrData.maskdata, 4, 4) node tempWrData_5_7 = bits(HAWINDOWWrData.maskdata, 5, 5) node tempWrData_6_7 = bits(HAWINDOWWrData.maskdata, 6, 6) node tempWrData_7_7 = bits(HAWINDOWWrData.maskdata, 7, 7) node tempWrData_8_7 = bits(HAWINDOWWrData.maskdata, 8, 8) node tempWrData_9_7 = bits(HAWINDOWWrData.maskdata, 9, 9) node tempWrData_10_7 = bits(HAWINDOWWrData.maskdata, 10, 10) node tempWrData_11_7 = bits(HAWINDOWWrData.maskdata, 11, 11) node tempWrData_12_7 = bits(HAWINDOWWrData.maskdata, 12, 12) node tempWrData_13_7 = bits(HAWINDOWWrData.maskdata, 13, 13) node tempWrData_14_7 = bits(HAWINDOWWrData.maskdata, 14, 14) node tempWrData_15_7 = bits(HAWINDOWWrData.maskdata, 15, 15) node tempWrData_16_7 = bits(HAWINDOWWrData.maskdata, 16, 16) node tempWrData_17_7 = bits(HAWINDOWWrData.maskdata, 17, 17) node tempWrData_18_7 = bits(HAWINDOWWrData.maskdata, 18, 18) node tempWrData_19_7 = bits(HAWINDOWWrData.maskdata, 19, 19) node tempWrData_20_7 = bits(HAWINDOWWrData.maskdata, 20, 20) node tempWrData_21_7 = bits(HAWINDOWWrData.maskdata, 21, 21) node tempWrData_22_7 = bits(HAWINDOWWrData.maskdata, 22, 22) node tempWrData_23_7 = bits(HAWINDOWWrData.maskdata, 23, 23) node tempWrData_24_7 = bits(HAWINDOWWrData.maskdata, 24, 24) node tempWrData_25_7 = bits(HAWINDOWWrData.maskdata, 25, 25) node tempWrData_26_7 = bits(HAWINDOWWrData.maskdata, 26, 26) node tempWrData_27_7 = bits(HAWINDOWWrData.maskdata, 27, 27) node tempWrData_28_7 = bits(HAWINDOWWrData.maskdata, 28, 28) node tempWrData_29_7 = bits(HAWINDOWWrData.maskdata, 29, 29) node tempWrData_30_7 = bits(HAWINDOWWrData.maskdata, 30, 30) node tempWrData_31_7 = bits(HAWINDOWWrData.maskdata, 31, 31) node tempMaskReg_0_7 = bits(HAMASKReg.maskdata, 0, 0) node tempMaskReg_1_7 = bits(HAMASKReg.maskdata, 1, 1) node tempMaskReg_2_7 = bits(HAMASKReg.maskdata, 2, 2) node tempMaskReg_3_7 = bits(HAMASKReg.maskdata, 3, 3) node tempMaskReg_4_7 = bits(HAMASKReg.maskdata, 4, 4) node tempMaskReg_5_7 = bits(HAMASKReg.maskdata, 5, 5) node tempMaskReg_6_7 = bits(HAMASKReg.maskdata, 6, 6) node tempMaskReg_7_7 = bits(HAMASKReg.maskdata, 7, 7) node tempMaskReg_8_7 = bits(HAMASKReg.maskdata, 8, 8) node tempMaskReg_9_7 = bits(HAMASKReg.maskdata, 9, 9) node tempMaskReg_10_7 = bits(HAMASKReg.maskdata, 10, 10) node tempMaskReg_11_7 = bits(HAMASKReg.maskdata, 11, 11) node tempMaskReg_12_7 = bits(HAMASKReg.maskdata, 12, 12) node tempMaskReg_13_7 = bits(HAMASKReg.maskdata, 13, 13) node tempMaskReg_14_7 = bits(HAMASKReg.maskdata, 14, 14) node tempMaskReg_15_7 = bits(HAMASKReg.maskdata, 15, 15) node tempMaskReg_16_7 = bits(HAMASKReg.maskdata, 16, 16) node tempMaskReg_17_7 = bits(HAMASKReg.maskdata, 17, 17) node tempMaskReg_18_7 = bits(HAMASKReg.maskdata, 18, 18) node tempMaskReg_19_7 = bits(HAMASKReg.maskdata, 19, 19) node tempMaskReg_20_7 = bits(HAMASKReg.maskdata, 20, 20) node tempMaskReg_21_7 = bits(HAMASKReg.maskdata, 21, 21) node tempMaskReg_22_7 = bits(HAMASKReg.maskdata, 22, 22) node tempMaskReg_23_7 = bits(HAMASKReg.maskdata, 23, 23) node tempMaskReg_24_7 = bits(HAMASKReg.maskdata, 24, 24) node tempMaskReg_25_7 = bits(HAMASKReg.maskdata, 25, 25) node tempMaskReg_26_7 = bits(HAMASKReg.maskdata, 26, 26) node tempMaskReg_27_7 = bits(HAMASKReg.maskdata, 27, 27) node tempMaskReg_28_7 = bits(HAMASKReg.maskdata, 28, 28) node tempMaskReg_29_7 = bits(HAMASKReg.maskdata, 29, 29) node tempMaskReg_30_7 = bits(HAMASKReg.maskdata, 30, 30) node tempMaskReg_31_7 = bits(HAMASKReg.maskdata, 31, 31) node _T_30 = eq(UInt<1>(0h0), HAWINDOWSELReg.hawindowsel) node _T_31 = and(HAWINDOWWrEn, _T_30) when _T_31 : connect hamask[7], tempWrData_7_7 else : connect hamask[7], tempMaskReg_7_7 wire hrmask : UInt<1>[8] wire hrmaskNxt : UInt<1>[8] wire _hrmaskReg_WIRE : UInt<1>[8] connect _hrmaskReg_WIRE[0], UInt<1>(0h0) connect _hrmaskReg_WIRE[1], UInt<1>(0h0) connect _hrmaskReg_WIRE[2], UInt<1>(0h0) connect _hrmaskReg_WIRE[3], UInt<1>(0h0) connect _hrmaskReg_WIRE[4], UInt<1>(0h0) connect _hrmaskReg_WIRE[5], UInt<1>(0h0) connect _hrmaskReg_WIRE[6], UInt<1>(0h0) connect _hrmaskReg_WIRE[7], UInt<1>(0h0) regreset hrmaskReg : UInt<1>[8], clock, _T, _hrmaskReg_WIRE connect hrmaskReg, hrmaskNxt connect hrmaskNxt, hrmaskReg node _T_32 = not(DMCONTROLReg.dmactive) node _T_33 = not(UInt<1>(0h1)) node _T_34 = or(_T_32, _T_33) when _T_34 : connect hrmaskNxt[0], UInt<1>(0h0) else : node _T_35 = and(clrresethaltreqWrEn, DMCONTROLWrData.clrresethaltreq) node _T_36 = eq(io.innerCtrl.bits.hartsel, UInt<1>(0h0)) node _T_37 = and(io.innerCtrl.bits.hasel, io.innerCtrl.bits.hamask[0]) node _T_38 = or(_T_36, _T_37) node _T_39 = and(_T_35, _T_38) when _T_39 : connect hrmaskNxt[0], UInt<1>(0h0) else : node _T_40 = and(setresethaltreqWrEn, DMCONTROLWrData.setresethaltreq) node _T_41 = eq(io.innerCtrl.bits.hartsel, UInt<1>(0h0)) node _T_42 = and(io.innerCtrl.bits.hasel, io.innerCtrl.bits.hamask[0]) node _T_43 = or(_T_41, _T_42) node _T_44 = and(_T_40, _T_43) when _T_44 : connect hrmaskNxt[0], UInt<1>(0h1) node _T_45 = not(DMCONTROLReg.dmactive) node _T_46 = not(UInt<1>(0h1)) node _T_47 = or(_T_45, _T_46) when _T_47 : connect hrmaskNxt[1], UInt<1>(0h0) else : node _T_48 = and(clrresethaltreqWrEn, DMCONTROLWrData.clrresethaltreq) node _T_49 = eq(io.innerCtrl.bits.hartsel, UInt<1>(0h1)) node _T_50 = and(io.innerCtrl.bits.hasel, io.innerCtrl.bits.hamask[1]) node _T_51 = or(_T_49, _T_50) node _T_52 = and(_T_48, _T_51) when _T_52 : connect hrmaskNxt[1], UInt<1>(0h0) else : node _T_53 = and(setresethaltreqWrEn, DMCONTROLWrData.setresethaltreq) node _T_54 = eq(io.innerCtrl.bits.hartsel, UInt<1>(0h1)) node _T_55 = and(io.innerCtrl.bits.hasel, io.innerCtrl.bits.hamask[1]) node _T_56 = or(_T_54, _T_55) node _T_57 = and(_T_53, _T_56) when _T_57 : connect hrmaskNxt[1], UInt<1>(0h1) node _T_58 = not(DMCONTROLReg.dmactive) node _T_59 = not(UInt<1>(0h1)) node _T_60 = or(_T_58, _T_59) when _T_60 : connect hrmaskNxt[2], UInt<1>(0h0) else : node _T_61 = and(clrresethaltreqWrEn, DMCONTROLWrData.clrresethaltreq) node _T_62 = eq(io.innerCtrl.bits.hartsel, UInt<2>(0h2)) node _T_63 = and(io.innerCtrl.bits.hasel, io.innerCtrl.bits.hamask[2]) node _T_64 = or(_T_62, _T_63) node _T_65 = and(_T_61, _T_64) when _T_65 : connect hrmaskNxt[2], UInt<1>(0h0) else : node _T_66 = and(setresethaltreqWrEn, DMCONTROLWrData.setresethaltreq) node _T_67 = eq(io.innerCtrl.bits.hartsel, UInt<2>(0h2)) node _T_68 = and(io.innerCtrl.bits.hasel, io.innerCtrl.bits.hamask[2]) node _T_69 = or(_T_67, _T_68) node _T_70 = and(_T_66, _T_69) when _T_70 : connect hrmaskNxt[2], UInt<1>(0h1) node _T_71 = not(DMCONTROLReg.dmactive) node _T_72 = not(UInt<1>(0h1)) node _T_73 = or(_T_71, _T_72) when _T_73 : connect hrmaskNxt[3], UInt<1>(0h0) else : node _T_74 = and(clrresethaltreqWrEn, DMCONTROLWrData.clrresethaltreq) node _T_75 = eq(io.innerCtrl.bits.hartsel, UInt<2>(0h3)) node _T_76 = and(io.innerCtrl.bits.hasel, io.innerCtrl.bits.hamask[3]) node _T_77 = or(_T_75, _T_76) node _T_78 = and(_T_74, _T_77) when _T_78 : connect hrmaskNxt[3], UInt<1>(0h0) else : node _T_79 = and(setresethaltreqWrEn, DMCONTROLWrData.setresethaltreq) node _T_80 = eq(io.innerCtrl.bits.hartsel, UInt<2>(0h3)) node _T_81 = and(io.innerCtrl.bits.hasel, io.innerCtrl.bits.hamask[3]) node _T_82 = or(_T_80, _T_81) node _T_83 = and(_T_79, _T_82) when _T_83 : connect hrmaskNxt[3], UInt<1>(0h1) node _T_84 = not(DMCONTROLReg.dmactive) node _T_85 = not(UInt<1>(0h1)) node _T_86 = or(_T_84, _T_85) when _T_86 : connect hrmaskNxt[4], UInt<1>(0h0) else : node _T_87 = and(clrresethaltreqWrEn, DMCONTROLWrData.clrresethaltreq) node _T_88 = eq(io.innerCtrl.bits.hartsel, UInt<3>(0h4)) node _T_89 = and(io.innerCtrl.bits.hasel, io.innerCtrl.bits.hamask[4]) node _T_90 = or(_T_88, _T_89) node _T_91 = and(_T_87, _T_90) when _T_91 : connect hrmaskNxt[4], UInt<1>(0h0) else : node _T_92 = and(setresethaltreqWrEn, DMCONTROLWrData.setresethaltreq) node _T_93 = eq(io.innerCtrl.bits.hartsel, UInt<3>(0h4)) node _T_94 = and(io.innerCtrl.bits.hasel, io.innerCtrl.bits.hamask[4]) node _T_95 = or(_T_93, _T_94) node _T_96 = and(_T_92, _T_95) when _T_96 : connect hrmaskNxt[4], UInt<1>(0h1) node _T_97 = not(DMCONTROLReg.dmactive) node _T_98 = not(UInt<1>(0h1)) node _T_99 = or(_T_97, _T_98) when _T_99 : connect hrmaskNxt[5], UInt<1>(0h0) else : node _T_100 = and(clrresethaltreqWrEn, DMCONTROLWrData.clrresethaltreq) node _T_101 = eq(io.innerCtrl.bits.hartsel, UInt<3>(0h5)) node _T_102 = and(io.innerCtrl.bits.hasel, io.innerCtrl.bits.hamask[5]) node _T_103 = or(_T_101, _T_102) node _T_104 = and(_T_100, _T_103) when _T_104 : connect hrmaskNxt[5], UInt<1>(0h0) else : node _T_105 = and(setresethaltreqWrEn, DMCONTROLWrData.setresethaltreq) node _T_106 = eq(io.innerCtrl.bits.hartsel, UInt<3>(0h5)) node _T_107 = and(io.innerCtrl.bits.hasel, io.innerCtrl.bits.hamask[5]) node _T_108 = or(_T_106, _T_107) node _T_109 = and(_T_105, _T_108) when _T_109 : connect hrmaskNxt[5], UInt<1>(0h1) node _T_110 = not(DMCONTROLReg.dmactive) node _T_111 = not(UInt<1>(0h1)) node _T_112 = or(_T_110, _T_111) when _T_112 : connect hrmaskNxt[6], UInt<1>(0h0) else : node _T_113 = and(clrresethaltreqWrEn, DMCONTROLWrData.clrresethaltreq) node _T_114 = eq(io.innerCtrl.bits.hartsel, UInt<3>(0h6)) node _T_115 = and(io.innerCtrl.bits.hasel, io.innerCtrl.bits.hamask[6]) node _T_116 = or(_T_114, _T_115) node _T_117 = and(_T_113, _T_116) when _T_117 : connect hrmaskNxt[6], UInt<1>(0h0) else : node _T_118 = and(setresethaltreqWrEn, DMCONTROLWrData.setresethaltreq) node _T_119 = eq(io.innerCtrl.bits.hartsel, UInt<3>(0h6)) node _T_120 = and(io.innerCtrl.bits.hasel, io.innerCtrl.bits.hamask[6]) node _T_121 = or(_T_119, _T_120) node _T_122 = and(_T_118, _T_121) when _T_122 : connect hrmaskNxt[6], UInt<1>(0h1) node _T_123 = not(DMCONTROLReg.dmactive) node _T_124 = not(UInt<1>(0h1)) node _T_125 = or(_T_123, _T_124) when _T_125 : connect hrmaskNxt[7], UInt<1>(0h0) else : node _T_126 = and(clrresethaltreqWrEn, DMCONTROLWrData.clrresethaltreq) node _T_127 = eq(io.innerCtrl.bits.hartsel, UInt<3>(0h7)) node _T_128 = and(io.innerCtrl.bits.hasel, io.innerCtrl.bits.hamask[7]) node _T_129 = or(_T_127, _T_128) node _T_130 = and(_T_126, _T_129) when _T_130 : connect hrmaskNxt[7], UInt<1>(0h0) else : node _T_131 = and(setresethaltreqWrEn, DMCONTROLWrData.setresethaltreq) node _T_132 = eq(io.innerCtrl.bits.hartsel, UInt<3>(0h7)) node _T_133 = and(io.innerCtrl.bits.hasel, io.innerCtrl.bits.hamask[7]) node _T_134 = or(_T_132, _T_133) node _T_135 = and(_T_131, _T_134) when _T_135 : connect hrmaskNxt[7], UInt<1>(0h1) connect hrmask, hrmaskNxt node _T_136 = and(DMCONTROLReg.dmactive, io.ctrl.dmactiveAck) wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<3>, data : UInt<32>, mask : UInt<4>, extra : { tlrr_extra : { source : UInt<1>, size : UInt<2>}}}} node _in_bits_read_T = eq(dmiNodeIn.a.bits.opcode, UInt<3>(0h4)) connect in.bits.read, _in_bits_read_T node _in_bits_index_T = shr(dmiNodeIn.a.bits.address, 2) connect in.bits.index, _in_bits_index_T connect in.bits.data, dmiNodeIn.a.bits.data connect in.bits.mask, dmiNodeIn.a.bits.mask connect in.bits.extra.tlrr_extra.source, dmiNodeIn.a.bits.source connect in.bits.extra.tlrr_extra.size, dmiNodeIn.a.bits.size wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<32>, extra : { tlrr_extra : { source : UInt<1>, size : UInt<2>}}}} wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<3>, data : UInt<32>, mask : UInt<4>, extra : { tlrr_extra : { source : UInt<1>, size : UInt<2>}}}} connect out_front.bits, in.bits node out_maskMatch = not(UInt<3>(0h6)) node out_findex = and(out_front.bits.index, out_maskMatch) node out_bindex = and(out_front.bits.index, out_maskMatch) node _out_T = eq(out_findex, UInt<3>(0h0)) node _out_T_1 = eq(out_bindex, UInt<3>(0h0)) node _out_T_2 = eq(out_findex, UInt<3>(0h1)) node _out_T_3 = eq(out_bindex, UInt<3>(0h1)) node _out_T_4 = eq(out_findex, UInt<3>(0h0)) node _out_T_5 = eq(out_bindex, UInt<3>(0h0)) wire out_rivalid : UInt<1>[19] wire out_wivalid : UInt<1>[19] wire out_roready : UInt<1>[19] wire out_woready : UInt<1>[19] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_frontMask_T_4 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_5 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_6 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_7 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node out_frontMask_lo = cat(_out_frontMask_T_5, _out_frontMask_T_4) node out_frontMask_hi = cat(_out_frontMask_T_7, _out_frontMask_T_6) node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) node _out_backMask_T = bits(out_front.bits.mask, 0, 0) node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_backMask_T_4 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_5 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_6 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_7 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node out_backMask_lo = cat(_out_backMask_T_5, _out_backMask_T_4) node out_backMask_hi = cat(_out_backMask_T_7, _out_backMask_T_6) node out_backMask = cat(out_backMask_hi, out_backMask_lo) node _out_rimask_T = bits(out_frontMask, 0, 0) node out_rimask = orr(_out_rimask_T) node _out_wimask_T = bits(out_frontMask, 0, 0) node out_wimask = andr(_out_wimask_T) node _out_romask_T = bits(out_backMask, 0, 0) node out_romask = orr(_out_romask_T) node _out_womask_T = bits(out_backMask, 0, 0) node out_womask = andr(_out_womask_T) node out_f_rivalid = and(out_rivalid[0], out_rimask) node out_f_roready = and(out_roready[0], out_romask) node out_f_wivalid = and(out_wivalid[0], out_wimask) node out_f_woready = and(out_woready[0], out_womask) node _out_T_6 = bits(out_front.bits.data, 0, 0) connect dmactiveWrEn, out_f_woready connect DMCONTROLWrData.dmactive, _out_T_6 node _out_T_7 = and(out_f_rivalid, UInt<1>(0h1)) node _out_T_8 = and(UInt<1>(0h1), out_f_roready) node _out_T_9 = and(out_f_wivalid, UInt<1>(0h1)) node _out_T_10 = and(UInt<1>(0h1), out_f_woready) node _out_T_11 = eq(out_rimask, UInt<1>(0h0)) node _out_T_12 = eq(out_wimask, UInt<1>(0h0)) node _out_T_13 = eq(out_romask, UInt<1>(0h0)) node _out_T_14 = eq(out_womask, UInt<1>(0h0)) node _out_T_15 = or(_T_136, UInt<1>(0h0)) node _out_T_16 = bits(_out_T_15, 0, 0) node _out_rimask_T_1 = bits(out_frontMask, 1, 1) node out_rimask_1 = orr(_out_rimask_T_1) node _out_wimask_T_1 = bits(out_frontMask, 1, 1) node out_wimask_1 = andr(_out_wimask_T_1) node _out_romask_T_1 = bits(out_backMask, 1, 1) node out_romask_1 = orr(_out_romask_T_1) node _out_womask_T_1 = bits(out_backMask, 1, 1) node out_womask_1 = andr(_out_womask_T_1) node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1) node out_f_roready_1 = and(out_roready[1], out_romask_1) node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1) node out_f_woready_1 = and(out_woready[1], out_womask_1) node _out_T_17 = bits(out_front.bits.data, 1, 1) connect ndmresetWrEn, out_f_woready_1 connect DMCONTROLWrData.ndmreset, _out_T_17 node _out_T_18 = and(out_f_rivalid_1, UInt<1>(0h1)) node _out_T_19 = and(UInt<1>(0h1), out_f_roready_1) node _out_T_20 = and(out_f_wivalid_1, UInt<1>(0h1)) node _out_T_21 = and(UInt<1>(0h1), out_f_woready_1) node _out_T_22 = eq(out_rimask_1, UInt<1>(0h0)) node _out_T_23 = eq(out_wimask_1, UInt<1>(0h0)) node _out_T_24 = eq(out_romask_1, UInt<1>(0h0)) node _out_T_25 = eq(out_womask_1, UInt<1>(0h0)) node _out_prepend_T = or(_out_T_16, UInt<1>(0h0)) node out_prepend = cat(DMCONTROLReg.ndmreset, _out_prepend_T) node _out_T_26 = or(out_prepend, UInt<2>(0h0)) node _out_T_27 = bits(_out_T_26, 1, 0) node _out_rimask_T_2 = bits(out_frontMask, 2, 2) node out_rimask_2 = orr(_out_rimask_T_2) node _out_wimask_T_2 = bits(out_frontMask, 2, 2) node out_wimask_2 = andr(_out_wimask_T_2) node _out_romask_T_2 = bits(out_backMask, 2, 2) node out_romask_2 = orr(_out_romask_T_2) node _out_womask_T_2 = bits(out_backMask, 2, 2) node out_womask_2 = andr(_out_womask_T_2) node out_f_rivalid_2 = and(out_rivalid[2], out_rimask_2) node out_f_roready_2 = and(out_roready[2], out_romask_2) node out_f_wivalid_2 = and(out_wivalid[2], out_wimask_2) node out_f_woready_2 = and(out_woready[2], out_womask_2) node _out_T_28 = bits(out_front.bits.data, 2, 2) connect clrresethaltreqWrEn, out_f_woready_2 connect DMCONTROLWrData.clrresethaltreq, _out_T_28 node _out_T_29 = and(out_f_wivalid_2, UInt<1>(0h1)) node _out_T_30 = and(UInt<1>(0h1), out_f_woready_2) node _out_T_31 = eq(out_rimask_2, UInt<1>(0h0)) node _out_T_32 = eq(out_wimask_2, UInt<1>(0h0)) node _out_T_33 = eq(out_romask_2, UInt<1>(0h0)) node _out_T_34 = eq(out_womask_2, UInt<1>(0h0)) node _out_prepend_T_1 = or(_out_T_27, UInt<2>(0h0)) node out_prepend_1 = cat(UInt<1>(0h0), _out_prepend_T_1) node _out_T_35 = or(out_prepend_1, UInt<3>(0h0)) node _out_T_36 = bits(_out_T_35, 2, 0) node _out_rimask_T_3 = bits(out_frontMask, 3, 3) node out_rimask_3 = orr(_out_rimask_T_3) node _out_wimask_T_3 = bits(out_frontMask, 3, 3) node out_wimask_3 = andr(_out_wimask_T_3) node _out_romask_T_3 = bits(out_backMask, 3, 3) node out_romask_3 = orr(_out_romask_T_3) node _out_womask_T_3 = bits(out_backMask, 3, 3) node out_womask_3 = andr(_out_womask_T_3) node out_f_rivalid_3 = and(out_rivalid[3], out_rimask_3) node out_f_roready_3 = and(out_roready[3], out_romask_3) node out_f_wivalid_3 = and(out_wivalid[3], out_wimask_3) node out_f_woready_3 = and(out_woready[3], out_womask_3) node _out_T_37 = bits(out_front.bits.data, 3, 3) connect setresethaltreqWrEn, out_f_woready_3 connect DMCONTROLWrData.setresethaltreq, _out_T_37 node _out_T_38 = and(out_f_wivalid_3, UInt<1>(0h1)) node _out_T_39 = and(UInt<1>(0h1), out_f_woready_3) node _out_T_40 = eq(out_rimask_3, UInt<1>(0h0)) node _out_T_41 = eq(out_wimask_3, UInt<1>(0h0)) node _out_T_42 = eq(out_romask_3, UInt<1>(0h0)) node _out_T_43 = eq(out_womask_3, UInt<1>(0h0)) node _out_prepend_T_2 = or(_out_T_36, UInt<3>(0h0)) node out_prepend_2 = cat(UInt<1>(0h0), _out_prepend_T_2) node _out_T_44 = or(out_prepend_2, UInt<4>(0h0)) node _out_T_45 = bits(_out_T_44, 3, 0) node _out_rimask_T_4 = bits(out_frontMask, 15, 4) node out_rimask_4 = orr(_out_rimask_T_4) node _out_wimask_T_4 = bits(out_frontMask, 15, 4) node out_wimask_4 = andr(_out_wimask_T_4) node _out_romask_T_4 = bits(out_backMask, 15, 4) node out_romask_4 = orr(_out_romask_T_4) node _out_womask_T_4 = bits(out_backMask, 15, 4) node out_womask_4 = andr(_out_womask_T_4) node out_f_rivalid_4 = and(out_rivalid[4], out_rimask_4) node out_f_roready_4 = and(out_roready[4], out_romask_4) node out_f_wivalid_4 = and(out_wivalid[4], out_wimask_4) node out_f_woready_4 = and(out_woready[4], out_womask_4) node _out_T_46 = bits(out_front.bits.data, 15, 4) node _out_T_47 = and(out_f_rivalid_4, UInt<1>(0h1)) node _out_T_48 = and(UInt<1>(0h1), out_f_roready_4) node _out_T_49 = eq(out_rimask_4, UInt<1>(0h0)) node _out_T_50 = eq(out_wimask_4, UInt<1>(0h0)) node _out_T_51 = eq(out_romask_4, UInt<1>(0h0)) node _out_T_52 = eq(out_womask_4, UInt<1>(0h0)) node _out_prepend_T_3 = or(_out_T_45, UInt<4>(0h0)) node out_prepend_3 = cat(UInt<1>(0h0), _out_prepend_T_3) node _out_T_53 = or(out_prepend_3, UInt<16>(0h0)) node _out_T_54 = bits(_out_T_53, 15, 0) node _out_rimask_T_5 = bits(out_frontMask, 18, 16) node out_rimask_5 = orr(_out_rimask_T_5) node _out_wimask_T_5 = bits(out_frontMask, 18, 16) node out_wimask_5 = andr(_out_wimask_T_5) node _out_romask_T_5 = bits(out_backMask, 18, 16) node out_romask_5 = orr(_out_romask_T_5) node _out_womask_T_5 = bits(out_backMask, 18, 16) node out_womask_5 = andr(_out_womask_T_5) node out_f_rivalid_5 = and(out_rivalid[5], out_rimask_5) node out_f_roready_5 = and(out_roready[5], out_romask_5) node out_f_wivalid_5 = and(out_wivalid[5], out_wimask_5) node out_f_woready_5 = and(out_woready[5], out_womask_5) node _out_T_55 = bits(out_front.bits.data, 18, 16) connect hartselloWrEn, out_f_woready_5 connect DMCONTROLWrData.hartsello, _out_T_55 node _out_T_56 = and(out_f_rivalid_5, UInt<1>(0h1)) node _out_T_57 = and(UInt<1>(0h1), out_f_roready_5) node _out_T_58 = and(out_f_wivalid_5, UInt<1>(0h1)) node _out_T_59 = and(UInt<1>(0h1), out_f_woready_5) node _out_T_60 = eq(out_rimask_5, UInt<1>(0h0)) node _out_T_61 = eq(out_wimask_5, UInt<1>(0h0)) node _out_T_62 = eq(out_romask_5, UInt<1>(0h0)) node _out_T_63 = eq(out_womask_5, UInt<1>(0h0)) node _out_prepend_T_4 = or(_out_T_54, UInt<16>(0h0)) node out_prepend_4 = cat(DMCONTROLReg.hartsello, _out_prepend_T_4) node _out_T_64 = or(out_prepend_4, UInt<19>(0h0)) node _out_T_65 = bits(_out_T_64, 18, 0) node _out_rimask_T_6 = bits(out_frontMask, 25, 19) node out_rimask_6 = orr(_out_rimask_T_6) node _out_wimask_T_6 = bits(out_frontMask, 25, 19) node out_wimask_6 = andr(_out_wimask_T_6) node _out_romask_T_6 = bits(out_backMask, 25, 19) node out_romask_6 = orr(_out_romask_T_6) node _out_womask_T_6 = bits(out_backMask, 25, 19) node out_womask_6 = andr(_out_womask_T_6) node out_f_rivalid_6 = and(out_rivalid[6], out_rimask_6) node out_f_roready_6 = and(out_roready[6], out_romask_6) node out_f_wivalid_6 = and(out_wivalid[6], out_wimask_6) node out_f_woready_6 = and(out_woready[6], out_womask_6) node _out_T_66 = bits(out_front.bits.data, 25, 19) node _out_T_67 = and(out_f_rivalid_6, UInt<1>(0h1)) node _out_T_68 = and(UInt<1>(0h1), out_f_roready_6) node _out_T_69 = eq(out_rimask_6, UInt<1>(0h0)) node _out_T_70 = eq(out_wimask_6, UInt<1>(0h0)) node _out_T_71 = eq(out_romask_6, UInt<1>(0h0)) node _out_T_72 = eq(out_womask_6, UInt<1>(0h0)) node _out_prepend_T_5 = or(_out_T_65, UInt<19>(0h0)) node out_prepend_5 = cat(UInt<1>(0h0), _out_prepend_T_5) node _out_T_73 = or(out_prepend_5, UInt<26>(0h0)) node _out_T_74 = bits(_out_T_73, 25, 0) node _out_rimask_T_7 = bits(out_frontMask, 26, 26) node out_rimask_7 = orr(_out_rimask_T_7) node _out_wimask_T_7 = bits(out_frontMask, 26, 26) node out_wimask_7 = andr(_out_wimask_T_7) node _out_romask_T_7 = bits(out_backMask, 26, 26) node out_romask_7 = orr(_out_romask_T_7) node _out_womask_T_7 = bits(out_backMask, 26, 26) node out_womask_7 = andr(_out_womask_T_7) node out_f_rivalid_7 = and(out_rivalid[7], out_rimask_7) node out_f_roready_7 = and(out_roready[7], out_romask_7) node out_f_wivalid_7 = and(out_wivalid[7], out_wimask_7) node out_f_woready_7 = and(out_woready[7], out_womask_7) node _out_T_75 = bits(out_front.bits.data, 26, 26) connect haselWrEn, out_f_woready_7 connect DMCONTROLWrData.hasel, _out_T_75 node _out_T_76 = and(out_f_rivalid_7, UInt<1>(0h1)) node _out_T_77 = and(UInt<1>(0h1), out_f_roready_7) node _out_T_78 = and(out_f_wivalid_7, UInt<1>(0h1)) node _out_T_79 = and(UInt<1>(0h1), out_f_woready_7) node _out_T_80 = eq(out_rimask_7, UInt<1>(0h0)) node _out_T_81 = eq(out_wimask_7, UInt<1>(0h0)) node _out_T_82 = eq(out_romask_7, UInt<1>(0h0)) node _out_T_83 = eq(out_womask_7, UInt<1>(0h0)) node _out_prepend_T_6 = or(_out_T_74, UInt<26>(0h0)) node out_prepend_6 = cat(DMCONTROLReg.hasel, _out_prepend_T_6) node _out_T_84 = or(out_prepend_6, UInt<27>(0h0)) node _out_T_85 = bits(_out_T_84, 26, 0) node _out_rimask_T_8 = bits(out_frontMask, 27, 27) node out_rimask_8 = orr(_out_rimask_T_8) node _out_wimask_T_8 = bits(out_frontMask, 27, 27) node out_wimask_8 = andr(_out_wimask_T_8) node _out_romask_T_8 = bits(out_backMask, 27, 27) node out_romask_8 = orr(_out_romask_T_8) node _out_womask_T_8 = bits(out_backMask, 27, 27) node out_womask_8 = andr(_out_womask_T_8) node out_f_rivalid_8 = and(out_rivalid[8], out_rimask_8) node out_f_roready_8 = and(out_roready[8], out_romask_8) node out_f_wivalid_8 = and(out_wivalid[8], out_wimask_8) node out_f_woready_8 = and(out_woready[8], out_womask_8) node _out_T_86 = bits(out_front.bits.data, 27, 27) node _out_T_87 = and(out_f_rivalid_8, UInt<1>(0h1)) node _out_T_88 = and(UInt<1>(0h1), out_f_roready_8) node _out_T_89 = eq(out_rimask_8, UInt<1>(0h0)) node _out_T_90 = eq(out_wimask_8, UInt<1>(0h0)) node _out_T_91 = eq(out_romask_8, UInt<1>(0h0)) node _out_T_92 = eq(out_womask_8, UInt<1>(0h0)) node _out_prepend_T_7 = or(_out_T_85, UInt<27>(0h0)) node out_prepend_7 = cat(UInt<1>(0h0), _out_prepend_T_7) node _out_T_93 = or(out_prepend_7, UInt<28>(0h0)) node _out_T_94 = bits(_out_T_93, 27, 0) node _out_rimask_T_9 = bits(out_frontMask, 28, 28) node out_rimask_9 = orr(_out_rimask_T_9) node _out_wimask_T_9 = bits(out_frontMask, 28, 28) node out_wimask_9 = andr(_out_wimask_T_9) node _out_romask_T_9 = bits(out_backMask, 28, 28) node out_romask_9 = orr(_out_romask_T_9) node _out_womask_T_9 = bits(out_backMask, 28, 28) node out_womask_9 = andr(_out_womask_T_9) node out_f_rivalid_9 = and(out_rivalid[9], out_rimask_9) node out_f_roready_9 = and(out_roready[9], out_romask_9) node out_f_wivalid_9 = and(out_wivalid[9], out_wimask_9) node out_f_woready_9 = and(out_woready[9], out_womask_9) node _out_T_95 = bits(out_front.bits.data, 28, 28) connect ackhaveresetWrEn, out_f_woready_9 connect DMCONTROLWrData.ackhavereset, _out_T_95 node _out_T_96 = and(out_f_wivalid_9, UInt<1>(0h1)) node _out_T_97 = and(UInt<1>(0h1), out_f_woready_9) node _out_T_98 = eq(out_rimask_9, UInt<1>(0h0)) node _out_T_99 = eq(out_wimask_9, UInt<1>(0h0)) node _out_T_100 = eq(out_romask_9, UInt<1>(0h0)) node _out_T_101 = eq(out_womask_9, UInt<1>(0h0)) node _out_prepend_T_8 = or(_out_T_94, UInt<28>(0h0)) node out_prepend_8 = cat(UInt<1>(0h0), _out_prepend_T_8) node _out_T_102 = or(out_prepend_8, UInt<29>(0h0)) node _out_T_103 = bits(_out_T_102, 28, 0) node _out_rimask_T_10 = bits(out_frontMask, 29, 29) node out_rimask_10 = orr(_out_rimask_T_10) node _out_wimask_T_10 = bits(out_frontMask, 29, 29) node out_wimask_10 = andr(_out_wimask_T_10) node _out_romask_T_10 = bits(out_backMask, 29, 29) node out_romask_10 = orr(_out_romask_T_10) node _out_womask_T_10 = bits(out_backMask, 29, 29) node out_womask_10 = andr(_out_womask_T_10) node out_f_rivalid_10 = and(out_rivalid[10], out_rimask_10) node out_f_roready_10 = and(out_roready[10], out_romask_10) node out_f_wivalid_10 = and(out_wivalid[10], out_wimask_10) node out_f_woready_10 = and(out_woready[10], out_womask_10) node _out_T_104 = bits(out_front.bits.data, 29, 29) node _out_T_105 = and(out_f_rivalid_10, UInt<1>(0h1)) node _out_T_106 = and(UInt<1>(0h1), out_f_roready_10) node _out_T_107 = eq(out_rimask_10, UInt<1>(0h0)) node _out_T_108 = eq(out_wimask_10, UInt<1>(0h0)) node _out_T_109 = eq(out_romask_10, UInt<1>(0h0)) node _out_T_110 = eq(out_womask_10, UInt<1>(0h0)) node _out_prepend_T_9 = or(_out_T_103, UInt<29>(0h0)) node out_prepend_9 = cat(UInt<1>(0h0), _out_prepend_T_9) node _out_T_111 = or(out_prepend_9, UInt<30>(0h0)) node _out_T_112 = bits(_out_T_111, 29, 0) node _out_rimask_T_11 = bits(out_frontMask, 30, 30) node out_rimask_11 = orr(_out_rimask_T_11) node _out_wimask_T_11 = bits(out_frontMask, 30, 30) node out_wimask_11 = andr(_out_wimask_T_11) node _out_romask_T_11 = bits(out_backMask, 30, 30) node out_romask_11 = orr(_out_romask_T_11) node _out_womask_T_11 = bits(out_backMask, 30, 30) node out_womask_11 = andr(_out_womask_T_11) node out_f_rivalid_11 = and(out_rivalid[11], out_rimask_11) node out_f_roready_11 = and(out_roready[11], out_romask_11) node out_f_wivalid_11 = and(out_wivalid[11], out_wimask_11) node out_f_woready_11 = and(out_woready[11], out_womask_11) node _out_T_113 = bits(out_front.bits.data, 30, 30) connect resumereqWrEn, out_f_woready_11 connect DMCONTROLWrData.resumereq, _out_T_113 node _out_T_114 = and(out_f_wivalid_11, UInt<1>(0h1)) node _out_T_115 = and(UInt<1>(0h1), out_f_woready_11) node _out_T_116 = eq(out_rimask_11, UInt<1>(0h0)) node _out_T_117 = eq(out_wimask_11, UInt<1>(0h0)) node _out_T_118 = eq(out_romask_11, UInt<1>(0h0)) node _out_T_119 = eq(out_womask_11, UInt<1>(0h0)) node _out_prepend_T_10 = or(_out_T_112, UInt<30>(0h0)) node out_prepend_10 = cat(UInt<1>(0h0), _out_prepend_T_10) node _out_T_120 = or(out_prepend_10, UInt<31>(0h0)) node _out_T_121 = bits(_out_T_120, 30, 0) node _out_rimask_T_12 = bits(out_frontMask, 31, 31) node out_rimask_12 = orr(_out_rimask_T_12) node _out_wimask_T_12 = bits(out_frontMask, 31, 31) node out_wimask_12 = andr(_out_wimask_T_12) node _out_romask_T_12 = bits(out_backMask, 31, 31) node out_romask_12 = orr(_out_romask_T_12) node _out_womask_T_12 = bits(out_backMask, 31, 31) node out_womask_12 = andr(_out_womask_T_12) node out_f_rivalid_12 = and(out_rivalid[12], out_rimask_12) node out_f_roready_12 = and(out_roready[12], out_romask_12) node out_f_wivalid_12 = and(out_wivalid[12], out_wimask_12) node out_f_woready_12 = and(out_woready[12], out_womask_12) node _out_T_122 = bits(out_front.bits.data, 31, 31) connect haltreqWrEn, out_f_woready_12 connect DMCONTROLWrData.haltreq, _out_T_122 node _out_T_123 = and(out_f_rivalid_12, UInt<1>(0h1)) node _out_T_124 = and(UInt<1>(0h1), out_f_roready_12) node _out_T_125 = and(out_f_wivalid_12, UInt<1>(0h1)) node _out_T_126 = and(UInt<1>(0h1), out_f_woready_12) node _out_T_127 = eq(out_rimask_12, UInt<1>(0h0)) node _out_T_128 = eq(out_wimask_12, UInt<1>(0h0)) node _out_T_129 = eq(out_romask_12, UInt<1>(0h0)) node _out_T_130 = eq(out_womask_12, UInt<1>(0h0)) node _out_prepend_T_11 = or(_out_T_121, UInt<31>(0h0)) node out_prepend_11 = cat(DMCONTROLReg.haltreq, _out_prepend_T_11) node _out_T_131 = or(out_prepend_11, UInt<32>(0h0)) node _out_T_132 = bits(_out_T_131, 31, 0) node _out_rimask_T_13 = bits(out_frontMask, 7, 0) node out_rimask_13 = orr(_out_rimask_T_13) node _out_wimask_T_13 = bits(out_frontMask, 7, 0) node out_wimask_13 = andr(_out_wimask_T_13) node _out_romask_T_13 = bits(out_backMask, 7, 0) node out_romask_13 = orr(_out_romask_T_13) node _out_womask_T_13 = bits(out_backMask, 7, 0) node out_womask_13 = andr(_out_womask_T_13) node out_f_rivalid_13 = and(out_rivalid[13], out_rimask_13) node out_f_roready_13 = and(out_roready[13], out_romask_13) node out_f_wivalid_13 = and(out_wivalid[13], out_wimask_13) node out_f_woready_13 = and(out_woready[13], out_womask_13) node _out_T_133 = bits(out_front.bits.data, 7, 0) connect HAWINDOWWrEn, out_f_woready_13 connect HAWINDOWWrData.maskdata, _out_T_133 node _out_T_134 = and(out_f_rivalid_13, UInt<1>(0h1)) node _out_T_135 = and(UInt<1>(0h1), out_f_roready_13) node _out_T_136 = and(out_f_wivalid_13, UInt<1>(0h1)) node _out_T_137 = and(UInt<1>(0h1), out_f_woready_13) node _out_T_138 = eq(out_rimask_13, UInt<1>(0h0)) node _out_T_139 = eq(out_wimask_13, UInt<1>(0h0)) node _out_T_140 = eq(out_romask_13, UInt<1>(0h0)) node _out_T_141 = eq(out_womask_13, UInt<1>(0h0)) node _out_T_142 = or(HAWINDOWRdData.maskdata, UInt<8>(0h0)) node _out_T_143 = bits(_out_T_142, 7, 0) node _out_rimask_T_14 = bits(out_frontMask, 11, 0) node out_rimask_14 = orr(_out_rimask_T_14) node _out_wimask_T_14 = bits(out_frontMask, 11, 0) node out_wimask_14 = andr(_out_wimask_T_14) node _out_romask_T_14 = bits(out_backMask, 11, 0) node out_romask_14 = orr(_out_romask_T_14) node _out_womask_T_14 = bits(out_backMask, 11, 0) node out_womask_14 = andr(_out_womask_T_14) node out_f_rivalid_14 = and(out_rivalid[14], out_rimask_14) node out_f_roready_14 = and(out_roready[14], out_romask_14) node out_f_wivalid_14 = and(out_wivalid[14], out_wimask_14) node out_f_woready_14 = and(out_woready[14], out_womask_14) node _out_T_144 = bits(out_front.bits.data, 11, 0) node _out_T_145 = and(out_f_rivalid_14, UInt<1>(0h1)) node _out_T_146 = and(UInt<1>(0h1), out_f_roready_14) node _out_T_147 = eq(out_rimask_14, UInt<1>(0h0)) node _out_T_148 = eq(out_wimask_14, UInt<1>(0h0)) node _out_T_149 = eq(out_romask_14, UInt<1>(0h0)) node _out_T_150 = eq(out_womask_14, UInt<1>(0h0)) node _out_T_151 = or(HARTINFORdData.dataaddr, UInt<12>(0h0)) node _out_T_152 = bits(_out_T_151, 11, 0) node _out_rimask_T_15 = bits(out_frontMask, 15, 12) node out_rimask_15 = orr(_out_rimask_T_15) node _out_wimask_T_15 = bits(out_frontMask, 15, 12) node out_wimask_15 = andr(_out_wimask_T_15) node _out_romask_T_15 = bits(out_backMask, 15, 12) node out_romask_15 = orr(_out_romask_T_15) node _out_womask_T_15 = bits(out_backMask, 15, 12) node out_womask_15 = andr(_out_womask_T_15) node out_f_rivalid_15 = and(out_rivalid[15], out_rimask_15) node out_f_roready_15 = and(out_roready[15], out_romask_15) node out_f_wivalid_15 = and(out_wivalid[15], out_wimask_15) node out_f_woready_15 = and(out_woready[15], out_womask_15) node _out_T_153 = bits(out_front.bits.data, 15, 12) node _out_T_154 = and(out_f_rivalid_15, UInt<1>(0h1)) node _out_T_155 = and(UInt<1>(0h1), out_f_roready_15) node _out_T_156 = eq(out_rimask_15, UInt<1>(0h0)) node _out_T_157 = eq(out_wimask_15, UInt<1>(0h0)) node _out_T_158 = eq(out_romask_15, UInt<1>(0h0)) node _out_T_159 = eq(out_womask_15, UInt<1>(0h0)) node _out_prepend_T_12 = or(_out_T_152, UInt<12>(0h0)) node out_prepend_12 = cat(HARTINFORdData.datasize, _out_prepend_T_12) node _out_T_160 = or(out_prepend_12, UInt<16>(0h0)) node _out_T_161 = bits(_out_T_160, 15, 0) node _out_rimask_T_16 = bits(out_frontMask, 16, 16) node out_rimask_16 = orr(_out_rimask_T_16) node _out_wimask_T_16 = bits(out_frontMask, 16, 16) node out_wimask_16 = andr(_out_wimask_T_16) node _out_romask_T_16 = bits(out_backMask, 16, 16) node out_romask_16 = orr(_out_romask_T_16) node _out_womask_T_16 = bits(out_backMask, 16, 16) node out_womask_16 = andr(_out_womask_T_16) node out_f_rivalid_16 = and(out_rivalid[16], out_rimask_16) node out_f_roready_16 = and(out_roready[16], out_romask_16) node out_f_wivalid_16 = and(out_wivalid[16], out_wimask_16) node out_f_woready_16 = and(out_woready[16], out_womask_16) node _out_T_162 = bits(out_front.bits.data, 16, 16) node _out_T_163 = and(out_f_rivalid_16, UInt<1>(0h1)) node _out_T_164 = and(UInt<1>(0h1), out_f_roready_16) node _out_T_165 = eq(out_rimask_16, UInt<1>(0h0)) node _out_T_166 = eq(out_wimask_16, UInt<1>(0h0)) node _out_T_167 = eq(out_romask_16, UInt<1>(0h0)) node _out_T_168 = eq(out_womask_16, UInt<1>(0h0)) node _out_prepend_T_13 = or(_out_T_161, UInt<16>(0h0)) node out_prepend_13 = cat(HARTINFORdData.dataaccess, _out_prepend_T_13) node _out_T_169 = or(out_prepend_13, UInt<17>(0h0)) node _out_T_170 = bits(_out_T_169, 16, 0) node _out_rimask_T_17 = bits(out_frontMask, 19, 17) node out_rimask_17 = orr(_out_rimask_T_17) node _out_wimask_T_17 = bits(out_frontMask, 19, 17) node out_wimask_17 = andr(_out_wimask_T_17) node _out_romask_T_17 = bits(out_backMask, 19, 17) node out_romask_17 = orr(_out_romask_T_17) node _out_womask_T_17 = bits(out_backMask, 19, 17) node out_womask_17 = andr(_out_womask_T_17) node out_f_rivalid_17 = and(out_rivalid[17], out_rimask_17) node out_f_roready_17 = and(out_roready[17], out_romask_17) node out_f_wivalid_17 = and(out_wivalid[17], out_wimask_17) node out_f_woready_17 = and(out_woready[17], out_womask_17) node _out_T_171 = bits(out_front.bits.data, 19, 17) node _out_T_172 = and(out_f_rivalid_17, UInt<1>(0h1)) node _out_T_173 = and(UInt<1>(0h1), out_f_roready_17) node _out_T_174 = eq(out_rimask_17, UInt<1>(0h0)) node _out_T_175 = eq(out_wimask_17, UInt<1>(0h0)) node _out_T_176 = eq(out_romask_17, UInt<1>(0h0)) node _out_T_177 = eq(out_womask_17, UInt<1>(0h0)) node _out_prepend_T_14 = or(_out_T_170, UInt<17>(0h0)) node out_prepend_14 = cat(UInt<1>(0h0), _out_prepend_T_14) node _out_T_178 = or(out_prepend_14, UInt<20>(0h0)) node _out_T_179 = bits(_out_T_178, 19, 0) node _out_rimask_T_18 = bits(out_frontMask, 23, 20) node out_rimask_18 = orr(_out_rimask_T_18) node _out_wimask_T_18 = bits(out_frontMask, 23, 20) node out_wimask_18 = andr(_out_wimask_T_18) node _out_romask_T_18 = bits(out_backMask, 23, 20) node out_romask_18 = orr(_out_romask_T_18) node _out_womask_T_18 = bits(out_backMask, 23, 20) node out_womask_18 = andr(_out_womask_T_18) node out_f_rivalid_18 = and(out_rivalid[18], out_rimask_18) node out_f_roready_18 = and(out_roready[18], out_romask_18) node out_f_wivalid_18 = and(out_wivalid[18], out_wimask_18) node out_f_woready_18 = and(out_woready[18], out_womask_18) node _out_T_180 = bits(out_front.bits.data, 23, 20) node _out_T_181 = and(out_f_rivalid_18, UInt<1>(0h1)) node _out_T_182 = and(UInt<1>(0h1), out_f_roready_18) node _out_T_183 = eq(out_rimask_18, UInt<1>(0h0)) node _out_T_184 = eq(out_wimask_18, UInt<1>(0h0)) node _out_T_185 = eq(out_romask_18, UInt<1>(0h0)) node _out_T_186 = eq(out_womask_18, UInt<1>(0h0)) node _out_prepend_T_15 = or(_out_T_179, UInt<20>(0h0)) node out_prepend_15 = cat(HARTINFORdData.nscratch, _out_prepend_T_15) node _out_T_187 = or(out_prepend_15, UInt<24>(0h0)) node _out_T_188 = bits(_out_T_187, 23, 0) node _out_iindex_T = bits(out_front.bits.index, 0, 0) node _out_iindex_T_1 = bits(out_front.bits.index, 1, 1) node _out_iindex_T_2 = bits(out_front.bits.index, 2, 2) node out_iindex = cat(_out_iindex_T_2, _out_iindex_T_1) node _out_oindex_T = bits(out_front.bits.index, 0, 0) node _out_oindex_T_1 = bits(out_front.bits.index, 1, 1) node _out_oindex_T_2 = bits(out_front.bits.index, 2, 2) node out_oindex = cat(_out_oindex_T_2, _out_oindex_T_1) node _out_frontSel_T = dshl(UInt<1>(0h1), out_iindex) node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) node out_frontSel_2 = bits(_out_frontSel_T, 2, 2) node out_frontSel_3 = bits(_out_frontSel_T, 3, 3) node _out_backSel_T = dshl(UInt<1>(0h1), out_oindex) node out_backSel_0 = bits(_out_backSel_T, 0, 0) node out_backSel_1 = bits(_out_backSel_T, 1, 1) node out_backSel_2 = bits(_out_backSel_T, 2, 2) node out_backSel_3 = bits(_out_backSel_T, 3, 3) node _out_rifireMux_T = and(in.valid, out_front.ready) node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) wire out_rifireMux_out : UInt<1> node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T) connect out_rifireMux_out, UInt<1>(0h1) connect out_rivalid[12], _out_rifireMux_T_3 connect out_rivalid[11], _out_rifireMux_T_3 connect out_rivalid[10], _out_rifireMux_T_3 connect out_rivalid[9], _out_rifireMux_T_3 connect out_rivalid[8], _out_rifireMux_T_3 connect out_rivalid[7], _out_rifireMux_T_3 connect out_rivalid[6], _out_rifireMux_T_3 connect out_rivalid[5], _out_rifireMux_T_3 connect out_rivalid[4], _out_rifireMux_T_3 connect out_rivalid[3], _out_rifireMux_T_3 connect out_rivalid[2], _out_rifireMux_T_3 connect out_rivalid[1], _out_rifireMux_T_3 connect out_rivalid[0], _out_rifireMux_T_3 node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0)) node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) wire out_rifireMux_out_1 : UInt<1> node _out_rifireMux_T_6 = and(_out_rifireMux_T_1, out_frontSel_1) node _out_rifireMux_T_7 = and(_out_rifireMux_T_6, _out_T_4) connect out_rifireMux_out_1, UInt<1>(0h1) connect out_rivalid[18], _out_rifireMux_T_7 connect out_rivalid[17], _out_rifireMux_T_7 connect out_rivalid[16], _out_rifireMux_T_7 connect out_rivalid[15], _out_rifireMux_T_7 connect out_rivalid[14], _out_rifireMux_T_7 node _out_rifireMux_T_8 = eq(_out_T_4, UInt<1>(0h0)) node _out_rifireMux_T_9 = or(out_rifireMux_out_1, _out_rifireMux_T_8) wire out_rifireMux_out_2 : UInt<1> node _out_rifireMux_T_10 = and(_out_rifireMux_T_1, out_frontSel_2) node _out_rifireMux_T_11 = and(_out_rifireMux_T_10, _out_T_2) connect out_rifireMux_out_2, UInt<1>(0h1) connect out_rivalid[13], _out_rifireMux_T_11 node _out_rifireMux_T_12 = eq(_out_T_2, UInt<1>(0h0)) node _out_rifireMux_T_13 = or(out_rifireMux_out_2, _out_rifireMux_T_12) wire out_rifireMux_out_3 : UInt<1> node _out_rifireMux_T_14 = and(_out_rifireMux_T_1, out_frontSel_3) node _out_rifireMux_T_15 = and(_out_rifireMux_T_14, UInt<1>(0h1)) connect out_rifireMux_out_3, UInt<1>(0h1) node _out_rifireMux_T_16 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_17 = or(out_rifireMux_out_3, _out_rifireMux_T_16) node _out_rifireMux_T_18 = geq(out_iindex, UInt<3>(0h4)) wire _out_rifireMux_WIRE : UInt<1>[4] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 connect _out_rifireMux_WIRE[1], _out_rifireMux_T_9 connect _out_rifireMux_WIRE[2], _out_rifireMux_T_13 connect _out_rifireMux_WIRE[3], _out_rifireMux_T_17 node out_rifireMux = mux(_out_rifireMux_T_18, UInt<1>(0h1), _out_rifireMux_WIRE[out_iindex]) node _out_wifireMux_T = and(in.valid, out_front.ready) node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) wire out_wifireMux_out : UInt<1> node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T) connect out_wifireMux_out, UInt<1>(0h1) connect out_wivalid[12], _out_wifireMux_T_4 connect out_wivalid[11], _out_wifireMux_T_4 connect out_wivalid[10], _out_wifireMux_T_4 connect out_wivalid[9], _out_wifireMux_T_4 connect out_wivalid[8], _out_wifireMux_T_4 connect out_wivalid[7], _out_wifireMux_T_4 connect out_wivalid[6], _out_wifireMux_T_4 connect out_wivalid[5], _out_wifireMux_T_4 connect out_wivalid[4], _out_wifireMux_T_4 connect out_wivalid[3], _out_wifireMux_T_4 connect out_wivalid[2], _out_wifireMux_T_4 connect out_wivalid[1], _out_wifireMux_T_4 connect out_wivalid[0], _out_wifireMux_T_4 node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0)) node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) wire out_wifireMux_out_1 : UInt<1> node _out_wifireMux_T_7 = and(_out_wifireMux_T_2, out_frontSel_1) node _out_wifireMux_T_8 = and(_out_wifireMux_T_7, _out_T_4) connect out_wifireMux_out_1, UInt<1>(0h1) connect out_wivalid[18], _out_wifireMux_T_8 connect out_wivalid[17], _out_wifireMux_T_8 connect out_wivalid[16], _out_wifireMux_T_8 connect out_wivalid[15], _out_wifireMux_T_8 connect out_wivalid[14], _out_wifireMux_T_8 node _out_wifireMux_T_9 = eq(_out_T_4, UInt<1>(0h0)) node _out_wifireMux_T_10 = or(out_wifireMux_out_1, _out_wifireMux_T_9) wire out_wifireMux_out_2 : UInt<1> node _out_wifireMux_T_11 = and(_out_wifireMux_T_2, out_frontSel_2) node _out_wifireMux_T_12 = and(_out_wifireMux_T_11, _out_T_2) connect out_wifireMux_out_2, UInt<1>(0h1) connect out_wivalid[13], _out_wifireMux_T_12 node _out_wifireMux_T_13 = eq(_out_T_2, UInt<1>(0h0)) node _out_wifireMux_T_14 = or(out_wifireMux_out_2, _out_wifireMux_T_13) wire out_wifireMux_out_3 : UInt<1> node _out_wifireMux_T_15 = and(_out_wifireMux_T_2, out_frontSel_3) node _out_wifireMux_T_16 = and(_out_wifireMux_T_15, UInt<1>(0h1)) connect out_wifireMux_out_3, UInt<1>(0h1) node _out_wifireMux_T_17 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_18 = or(out_wifireMux_out_3, _out_wifireMux_T_17) node _out_wifireMux_T_19 = geq(out_iindex, UInt<3>(0h4)) wire _out_wifireMux_WIRE : UInt<1>[4] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 connect _out_wifireMux_WIRE[1], _out_wifireMux_T_10 connect _out_wifireMux_WIRE[2], _out_wifireMux_T_14 connect _out_wifireMux_WIRE[3], _out_wifireMux_T_18 node out_wifireMux = mux(_out_wifireMux_T_19, UInt<1>(0h1), _out_wifireMux_WIRE[out_iindex]) node _out_rofireMux_T = and(out_front.valid, out.ready) node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read) wire out_rofireMux_out : UInt<1> node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1) connect out_rofireMux_out, UInt<1>(0h1) connect out_roready[12], _out_rofireMux_T_3 connect out_roready[11], _out_rofireMux_T_3 connect out_roready[10], _out_rofireMux_T_3 connect out_roready[9], _out_rofireMux_T_3 connect out_roready[8], _out_rofireMux_T_3 connect out_roready[7], _out_rofireMux_T_3 connect out_roready[6], _out_rofireMux_T_3 connect out_roready[5], _out_rofireMux_T_3 connect out_roready[4], _out_rofireMux_T_3 connect out_roready[3], _out_rofireMux_T_3 connect out_roready[2], _out_rofireMux_T_3 connect out_roready[1], _out_rofireMux_T_3 connect out_roready[0], _out_rofireMux_T_3 node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0)) node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) wire out_rofireMux_out_1 : UInt<1> node _out_rofireMux_T_6 = and(_out_rofireMux_T_1, out_backSel_1) node _out_rofireMux_T_7 = and(_out_rofireMux_T_6, _out_T_5) connect out_rofireMux_out_1, UInt<1>(0h1) connect out_roready[18], _out_rofireMux_T_7 connect out_roready[17], _out_rofireMux_T_7 connect out_roready[16], _out_rofireMux_T_7 connect out_roready[15], _out_rofireMux_T_7 connect out_roready[14], _out_rofireMux_T_7 node _out_rofireMux_T_8 = eq(_out_T_5, UInt<1>(0h0)) node _out_rofireMux_T_9 = or(out_rofireMux_out_1, _out_rofireMux_T_8) wire out_rofireMux_out_2 : UInt<1> node _out_rofireMux_T_10 = and(_out_rofireMux_T_1, out_backSel_2) node _out_rofireMux_T_11 = and(_out_rofireMux_T_10, _out_T_3) connect out_rofireMux_out_2, UInt<1>(0h1) connect out_roready[13], _out_rofireMux_T_11 node _out_rofireMux_T_12 = eq(_out_T_3, UInt<1>(0h0)) node _out_rofireMux_T_13 = or(out_rofireMux_out_2, _out_rofireMux_T_12) wire out_rofireMux_out_3 : UInt<1> node _out_rofireMux_T_14 = and(_out_rofireMux_T_1, out_backSel_3) node _out_rofireMux_T_15 = and(_out_rofireMux_T_14, UInt<1>(0h1)) connect out_rofireMux_out_3, UInt<1>(0h1) node _out_rofireMux_T_16 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_17 = or(out_rofireMux_out_3, _out_rofireMux_T_16) node _out_rofireMux_T_18 = geq(out_oindex, UInt<3>(0h4)) wire _out_rofireMux_WIRE : UInt<1>[4] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 connect _out_rofireMux_WIRE[1], _out_rofireMux_T_9 connect _out_rofireMux_WIRE[2], _out_rofireMux_T_13 connect _out_rofireMux_WIRE[3], _out_rofireMux_T_17 node out_rofireMux = mux(_out_rofireMux_T_18, UInt<1>(0h1), _out_rofireMux_WIRE[out_oindex]) node _out_wofireMux_T = and(out_front.valid, out.ready) node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) wire out_wofireMux_out : UInt<1> node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1) connect out_wofireMux_out, UInt<1>(0h1) connect out_woready[12], _out_wofireMux_T_4 connect out_woready[11], _out_wofireMux_T_4 connect out_woready[10], _out_wofireMux_T_4 connect out_woready[9], _out_wofireMux_T_4 connect out_woready[8], _out_wofireMux_T_4 connect out_woready[7], _out_wofireMux_T_4 connect out_woready[6], _out_wofireMux_T_4 connect out_woready[5], _out_wofireMux_T_4 connect out_woready[4], _out_wofireMux_T_4 connect out_woready[3], _out_wofireMux_T_4 connect out_woready[2], _out_wofireMux_T_4 connect out_woready[1], _out_wofireMux_T_4 connect out_woready[0], _out_wofireMux_T_4 node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0)) node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) wire out_wofireMux_out_1 : UInt<1> node _out_wofireMux_T_7 = and(_out_wofireMux_T_2, out_backSel_1) node _out_wofireMux_T_8 = and(_out_wofireMux_T_7, _out_T_5) connect out_wofireMux_out_1, UInt<1>(0h1) connect out_woready[18], _out_wofireMux_T_8 connect out_woready[17], _out_wofireMux_T_8 connect out_woready[16], _out_wofireMux_T_8 connect out_woready[15], _out_wofireMux_T_8 connect out_woready[14], _out_wofireMux_T_8 node _out_wofireMux_T_9 = eq(_out_T_5, UInt<1>(0h0)) node _out_wofireMux_T_10 = or(out_wofireMux_out_1, _out_wofireMux_T_9) wire out_wofireMux_out_2 : UInt<1> node _out_wofireMux_T_11 = and(_out_wofireMux_T_2, out_backSel_2) node _out_wofireMux_T_12 = and(_out_wofireMux_T_11, _out_T_3) connect out_wofireMux_out_2, UInt<1>(0h1) connect out_woready[13], _out_wofireMux_T_12 node _out_wofireMux_T_13 = eq(_out_T_3, UInt<1>(0h0)) node _out_wofireMux_T_14 = or(out_wofireMux_out_2, _out_wofireMux_T_13) wire out_wofireMux_out_3 : UInt<1> node _out_wofireMux_T_15 = and(_out_wofireMux_T_2, out_backSel_3) node _out_wofireMux_T_16 = and(_out_wofireMux_T_15, UInt<1>(0h1)) connect out_wofireMux_out_3, UInt<1>(0h1) node _out_wofireMux_T_17 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_18 = or(out_wofireMux_out_3, _out_wofireMux_T_17) node _out_wofireMux_T_19 = geq(out_oindex, UInt<3>(0h4)) wire _out_wofireMux_WIRE : UInt<1>[4] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 connect _out_wofireMux_WIRE[1], _out_wofireMux_T_10 connect _out_wofireMux_WIRE[2], _out_wofireMux_T_14 connect _out_wofireMux_WIRE[3], _out_wofireMux_T_18 node out_wofireMux = mux(_out_wofireMux_T_19, UInt<1>(0h1), _out_wofireMux_WIRE[out_oindex]) node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux) node _out_in_ready_T = and(out_front.ready, out_iready) connect in.ready, _out_in_ready_T node _out_front_valid_T = and(in.valid, out_iready) connect out_front.valid, _out_front_valid_T node _out_front_ready_T = and(out.ready, out_oready) connect out_front.ready, _out_front_ready_T node _out_out_valid_T = and(out_front.valid, out_oready) connect out.valid, _out_out_valid_T connect out.bits.read, out_front.bits.read node _out_out_bits_data_T = geq(out_oindex, UInt<3>(0h4)) wire _out_out_bits_data_WIRE : UInt<1>[4] connect _out_out_bits_data_WIRE[0], _out_T_1 connect _out_out_bits_data_WIRE[1], _out_T_5 connect _out_out_bits_data_WIRE[2], _out_T_3 connect _out_out_bits_data_WIRE[3], UInt<1>(0h1) node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[out_oindex]) node _out_out_bits_data_T_2 = geq(out_oindex, UInt<3>(0h4)) wire _out_out_bits_data_WIRE_1 : UInt<32>[4] connect _out_out_bits_data_WIRE_1[0], _out_T_132 connect _out_out_bits_data_WIRE_1[1], _out_T_188 connect _out_out_bits_data_WIRE_1[2], _out_T_143 connect _out_out_bits_data_WIRE_1[3], UInt<1>(0h0) node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[out_oindex]) node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0)) connect out.bits.data, _out_out_bits_data_T_4 connect out.bits.extra, out_front.bits.extra connect in.valid, dmiNodeIn.a.valid connect dmiNodeIn.a.ready, in.ready connect dmiNodeIn.d.valid, out.valid connect out.ready, dmiNodeIn.d.ready wire dmiNodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>} connect dmiNodeIn_d_bits_d.opcode, UInt<1>(0h0) connect dmiNodeIn_d_bits_d.param, UInt<1>(0h0) connect dmiNodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size connect dmiNodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source connect dmiNodeIn_d_bits_d.sink, UInt<1>(0h0) connect dmiNodeIn_d_bits_d.denied, UInt<1>(0h0) invalidate dmiNodeIn_d_bits_d.data connect dmiNodeIn_d_bits_d.corrupt, UInt<1>(0h0) connect dmiNodeIn.d.bits.corrupt, dmiNodeIn_d_bits_d.corrupt connect dmiNodeIn.d.bits.data, dmiNodeIn_d_bits_d.data connect dmiNodeIn.d.bits.denied, dmiNodeIn_d_bits_d.denied connect dmiNodeIn.d.bits.sink, dmiNodeIn_d_bits_d.sink connect dmiNodeIn.d.bits.source, dmiNodeIn_d_bits_d.source connect dmiNodeIn.d.bits.size, dmiNodeIn_d_bits_d.size connect dmiNodeIn.d.bits.param, dmiNodeIn_d_bits_d.param connect dmiNodeIn.d.bits.opcode, dmiNodeIn_d_bits_d.opcode connect dmiNodeIn.d.bits.data, out.bits.data node _dmiNodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) connect dmiNodeIn.d.bits.opcode, _dmiNodeIn_d_bits_opcode_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<7>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<7>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<7>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<7>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _debugIntNxt_WIRE : UInt<1>[8] connect _debugIntNxt_WIRE[0], UInt<1>(0h0) connect _debugIntNxt_WIRE[1], UInt<1>(0h0) connect _debugIntNxt_WIRE[2], UInt<1>(0h0) connect _debugIntNxt_WIRE[3], UInt<1>(0h0) connect _debugIntNxt_WIRE[4], UInt<1>(0h0) connect _debugIntNxt_WIRE[5], UInt<1>(0h0) connect _debugIntNxt_WIRE[6], UInt<1>(0h0) connect _debugIntNxt_WIRE[7], UInt<1>(0h0) wire debugIntNxt : UInt<1>[8] connect debugIntNxt, _debugIntNxt_WIRE wire _debugIntRegs_WIRE : UInt<1>[8] connect _debugIntRegs_WIRE[0], UInt<1>(0h0) connect _debugIntRegs_WIRE[1], UInt<1>(0h0) connect _debugIntRegs_WIRE[2], UInt<1>(0h0) connect _debugIntRegs_WIRE[3], UInt<1>(0h0) connect _debugIntRegs_WIRE[4], UInt<1>(0h0) connect _debugIntRegs_WIRE[5], UInt<1>(0h0) connect _debugIntRegs_WIRE[6], UInt<1>(0h0) connect _debugIntRegs_WIRE[7], UInt<1>(0h0) regreset debugIntRegs : UInt<1>[8], clock, _T, _debugIntRegs_WIRE connect debugIntRegs, debugIntNxt connect debugIntNxt, debugIntRegs node _intnodeOut_0_T = or(debugIntRegs[0], io.hgDebugInt[0]) connect intnodeOut[0], _intnodeOut_0_T node _intnodeOut_0_T_1 = or(debugIntRegs[1], io.hgDebugInt[1]) connect x1_intnodeOut[0], _intnodeOut_0_T_1 node _intnodeOut_0_T_2 = or(debugIntRegs[2], io.hgDebugInt[2]) connect x1_intnodeOut_1[0], _intnodeOut_0_T_2 node _intnodeOut_0_T_3 = or(debugIntRegs[3], io.hgDebugInt[3]) connect x1_intnodeOut_2[0], _intnodeOut_0_T_3 node _intnodeOut_0_T_4 = or(debugIntRegs[4], io.hgDebugInt[4]) connect x1_intnodeOut_3[0], _intnodeOut_0_T_4 node _intnodeOut_0_T_5 = or(debugIntRegs[5], io.hgDebugInt[5]) connect x1_intnodeOut_4[0], _intnodeOut_0_T_5 node _intnodeOut_0_T_6 = or(debugIntRegs[6], io.hgDebugInt[6]) connect x1_intnodeOut_5[0], _intnodeOut_0_T_6 node _intnodeOut_0_T_7 = or(debugIntRegs[7], io.hgDebugInt[7]) connect x1_intnodeOut_6[0], _intnodeOut_0_T_7 node _T_137 = not(DMCONTROLReg.dmactive) node _T_138 = not(UInt<1>(0h1)) node _T_139 = or(_T_137, _T_138) when _T_139 : connect debugIntNxt[0], UInt<1>(0h0) else : node _T_140 = eq(DMCONTROLWrData.hartsello, UInt<1>(0h0)) node _T_141 = and(DMCONTROLWrData.hasel, hamask[0]) node _T_142 = or(_T_140, _T_141) node _T_143 = and(haltreqWrEn, _T_142) when _T_143 : connect debugIntNxt[0], DMCONTROLWrData.haltreq node _T_144 = not(DMCONTROLReg.dmactive) node _T_145 = not(UInt<1>(0h1)) node _T_146 = or(_T_144, _T_145) when _T_146 : connect debugIntNxt[1], UInt<1>(0h0) else : node _T_147 = eq(DMCONTROLWrData.hartsello, UInt<1>(0h1)) node _T_148 = and(DMCONTROLWrData.hasel, hamask[1]) node _T_149 = or(_T_147, _T_148) node _T_150 = and(haltreqWrEn, _T_149) when _T_150 : connect debugIntNxt[1], DMCONTROLWrData.haltreq node _T_151 = not(DMCONTROLReg.dmactive) node _T_152 = not(UInt<1>(0h1)) node _T_153 = or(_T_151, _T_152) when _T_153 : connect debugIntNxt[2], UInt<1>(0h0) else : node _T_154 = eq(DMCONTROLWrData.hartsello, UInt<2>(0h2)) node _T_155 = and(DMCONTROLWrData.hasel, hamask[2]) node _T_156 = or(_T_154, _T_155) node _T_157 = and(haltreqWrEn, _T_156) when _T_157 : connect debugIntNxt[2], DMCONTROLWrData.haltreq node _T_158 = not(DMCONTROLReg.dmactive) node _T_159 = not(UInt<1>(0h1)) node _T_160 = or(_T_158, _T_159) when _T_160 : connect debugIntNxt[3], UInt<1>(0h0) else : node _T_161 = eq(DMCONTROLWrData.hartsello, UInt<2>(0h3)) node _T_162 = and(DMCONTROLWrData.hasel, hamask[3]) node _T_163 = or(_T_161, _T_162) node _T_164 = and(haltreqWrEn, _T_163) when _T_164 : connect debugIntNxt[3], DMCONTROLWrData.haltreq node _T_165 = not(DMCONTROLReg.dmactive) node _T_166 = not(UInt<1>(0h1)) node _T_167 = or(_T_165, _T_166) when _T_167 : connect debugIntNxt[4], UInt<1>(0h0) else : node _T_168 = eq(DMCONTROLWrData.hartsello, UInt<3>(0h4)) node _T_169 = and(DMCONTROLWrData.hasel, hamask[4]) node _T_170 = or(_T_168, _T_169) node _T_171 = and(haltreqWrEn, _T_170) when _T_171 : connect debugIntNxt[4], DMCONTROLWrData.haltreq node _T_172 = not(DMCONTROLReg.dmactive) node _T_173 = not(UInt<1>(0h1)) node _T_174 = or(_T_172, _T_173) when _T_174 : connect debugIntNxt[5], UInt<1>(0h0) else : node _T_175 = eq(DMCONTROLWrData.hartsello, UInt<3>(0h5)) node _T_176 = and(DMCONTROLWrData.hasel, hamask[5]) node _T_177 = or(_T_175, _T_176) node _T_178 = and(haltreqWrEn, _T_177) when _T_178 : connect debugIntNxt[5], DMCONTROLWrData.haltreq node _T_179 = not(DMCONTROLReg.dmactive) node _T_180 = not(UInt<1>(0h1)) node _T_181 = or(_T_179, _T_180) when _T_181 : connect debugIntNxt[6], UInt<1>(0h0) else : node _T_182 = eq(DMCONTROLWrData.hartsello, UInt<3>(0h6)) node _T_183 = and(DMCONTROLWrData.hasel, hamask[6]) node _T_184 = or(_T_182, _T_183) node _T_185 = and(haltreqWrEn, _T_184) when _T_185 : connect debugIntNxt[6], DMCONTROLWrData.haltreq node _T_186 = not(DMCONTROLReg.dmactive) node _T_187 = not(UInt<1>(0h1)) node _T_188 = or(_T_186, _T_187) when _T_188 : connect debugIntNxt[7], UInt<1>(0h0) else : node _T_189 = eq(DMCONTROLWrData.hartsello, UInt<3>(0h7)) node _T_190 = and(DMCONTROLWrData.hasel, hamask[7]) node _T_191 = or(_T_189, _T_190) node _T_192 = and(haltreqWrEn, _T_191) when _T_192 : connect debugIntNxt[7], DMCONTROLWrData.haltreq wire innerCtrlValid : UInt<1> regreset innerCtrlValidReg : UInt<1>, clock, _T, UInt<1>(0h0) regreset innerCtrlResumeReqReg : UInt<1>, clock, _T, UInt<1>(0h0) regreset innerCtrlAckHaveResetReg : UInt<1>, clock, _T, UInt<1>(0h0) node _innerCtrlValid_T = or(hartselloWrEn, resumereqWrEn) node _innerCtrlValid_T_1 = or(_innerCtrlValid_T, ackhaveresetWrEn) node _innerCtrlValid_T_2 = or(_innerCtrlValid_T_1, setresethaltreqWrEn) node _innerCtrlValid_T_3 = or(_innerCtrlValid_T_2, clrresethaltreqWrEn) node _innerCtrlValid_T_4 = or(_innerCtrlValid_T_3, haselWrEn) node _innerCtrlValid_T_5 = and(HAWINDOWWrEn, UInt<1>(0h1)) node _innerCtrlValid_T_6 = or(_innerCtrlValid_T_4, _innerCtrlValid_T_5) connect innerCtrlValid, _innerCtrlValid_T_6 node _innerCtrlValidReg_T = not(io.innerCtrl.ready) node _innerCtrlValidReg_T_1 = and(io.innerCtrl.valid, _innerCtrlValidReg_T) connect innerCtrlValidReg, _innerCtrlValidReg_T_1 node _innerCtrlResumeReqReg_T = not(io.innerCtrl.ready) node _innerCtrlResumeReqReg_T_1 = and(io.innerCtrl.bits.resumereq, _innerCtrlResumeReqReg_T) connect innerCtrlResumeReqReg, _innerCtrlResumeReqReg_T_1 node _innerCtrlAckHaveResetReg_T = not(io.innerCtrl.ready) node _innerCtrlAckHaveResetReg_T_1 = and(io.innerCtrl.bits.ackhavereset, _innerCtrlAckHaveResetReg_T) connect innerCtrlAckHaveResetReg, _innerCtrlAckHaveResetReg_T_1 node _io_innerCtrl_valid_T = or(innerCtrlValid, innerCtrlValidReg) connect io.innerCtrl.valid, _io_innerCtrl_valid_T node _io_innerCtrl_bits_hartsel_T = mux(hartselloWrEn, DMCONTROLWrData.hartsello, DMCONTROLReg.hartsello) connect io.innerCtrl.bits.hartsel, _io_innerCtrl_bits_hartsel_T node _io_innerCtrl_bits_resumereq_T = and(resumereqWrEn, DMCONTROLWrData.resumereq) node _io_innerCtrl_bits_resumereq_T_1 = or(_io_innerCtrl_bits_resumereq_T, innerCtrlResumeReqReg) connect io.innerCtrl.bits.resumereq, _io_innerCtrl_bits_resumereq_T_1 node _io_innerCtrl_bits_ackhavereset_T = and(ackhaveresetWrEn, DMCONTROLWrData.ackhavereset) node _io_innerCtrl_bits_ackhavereset_T_1 = or(_io_innerCtrl_bits_ackhavereset_T, innerCtrlAckHaveResetReg) connect io.innerCtrl.bits.ackhavereset, _io_innerCtrl_bits_ackhavereset_T_1 connect io.innerCtrl.bits.hrmask, hrmask node _io_innerCtrl_bits_hasel_T = mux(haselWrEn, DMCONTROLWrData.hasel, DMCONTROLReg.hasel) connect io.innerCtrl.bits.hasel, _io_innerCtrl_bits_hasel_T connect io.innerCtrl.bits.hamask, hamask connect io.ctrl.ndreset, DMCONTROLReg.ndmreset connect io.ctrl.dmactive, DMCONTROLReg.dmactive
module TLDebugModuleOuter( // @[Debug.scala:340:9] input clock, // @[Debug.scala:340:9] input reset, // @[Debug.scala:340:9] output auto_dmi_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_dmi_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dmi_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [6:0] auto_dmi_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [31:0] auto_dmi_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_dmi_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_dmi_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dmi_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [31:0] auto_dmi_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_int_out_7_0, // @[LazyModuleImp.scala:107:25] output auto_int_out_6_0, // @[LazyModuleImp.scala:107:25] output auto_int_out_5_0, // @[LazyModuleImp.scala:107:25] output auto_int_out_4_0, // @[LazyModuleImp.scala:107:25] output auto_int_out_3_0, // @[LazyModuleImp.scala:107:25] output auto_int_out_2_0, // @[LazyModuleImp.scala:107:25] output auto_int_out_1_0, // @[LazyModuleImp.scala:107:25] output auto_int_out_0_0, // @[LazyModuleImp.scala:107:25] output io_ctrl_dmactive, // @[Debug.scala:348:16] input io_ctrl_dmactiveAck, // @[Debug.scala:348:16] input io_innerCtrl_ready, // @[Debug.scala:348:16] output io_innerCtrl_valid, // @[Debug.scala:348:16] output io_innerCtrl_bits_resumereq, // @[Debug.scala:348:16] output [9:0] io_innerCtrl_bits_hartsel, // @[Debug.scala:348:16] output io_innerCtrl_bits_ackhavereset, // @[Debug.scala:348:16] output io_innerCtrl_bits_hasel, // @[Debug.scala:348:16] output io_innerCtrl_bits_hamask_0, // @[Debug.scala:348:16] output io_innerCtrl_bits_hamask_1, // @[Debug.scala:348:16] output io_innerCtrl_bits_hamask_2, // @[Debug.scala:348:16] output io_innerCtrl_bits_hamask_3, // @[Debug.scala:348:16] output io_innerCtrl_bits_hamask_4, // @[Debug.scala:348:16] output io_innerCtrl_bits_hamask_5, // @[Debug.scala:348:16] output io_innerCtrl_bits_hamask_6, // @[Debug.scala:348:16] output io_innerCtrl_bits_hamask_7, // @[Debug.scala:348:16] output io_innerCtrl_bits_hrmask_0, // @[Debug.scala:348:16] output io_innerCtrl_bits_hrmask_1, // @[Debug.scala:348:16] output io_innerCtrl_bits_hrmask_2, // @[Debug.scala:348:16] output io_innerCtrl_bits_hrmask_3, // @[Debug.scala:348:16] output io_innerCtrl_bits_hrmask_4, // @[Debug.scala:348:16] output io_innerCtrl_bits_hrmask_5, // @[Debug.scala:348:16] output io_innerCtrl_bits_hrmask_6, // @[Debug.scala:348:16] output io_innerCtrl_bits_hrmask_7, // @[Debug.scala:348:16] input io_hgDebugInt_0, // @[Debug.scala:348:16] input io_hgDebugInt_1, // @[Debug.scala:348:16] input io_hgDebugInt_2, // @[Debug.scala:348:16] input io_hgDebugInt_3, // @[Debug.scala:348:16] input io_hgDebugInt_4, // @[Debug.scala:348:16] input io_hgDebugInt_5, // @[Debug.scala:348:16] input io_hgDebugInt_6, // @[Debug.scala:348:16] input io_hgDebugInt_7 // @[Debug.scala:348:16] ); wire io_innerCtrl_bits_hasel_0; // @[Debug.scala:647:42] wire [9:0] io_innerCtrl_bits_hartsel_0; // @[Debug.scala:642:42] wire out_woready_13; // @[RegisterRouter.scala:87:24] wire out_woready_9; // @[RegisterRouter.scala:87:24] wire DMCONTROLWrData_setresethaltreq; // @[RegisterRouter.scala:87:24] wire DMCONTROLWrData_clrresethaltreq; // @[RegisterRouter.scala:87:24] reg DMCONTROLReg_haltreq; // @[Debug.scala:379:31] reg DMCONTROLReg_hasel; // @[Debug.scala:379:31] reg [9:0] DMCONTROLReg_hartsello; // @[Debug.scala:379:31] reg DMCONTROLReg_ndmreset; // @[Debug.scala:379:31] reg DMCONTROLReg_dmactive; // @[Debug.scala:379:31] reg [14:0] HAWINDOWSELReg_hawindowsel; // @[Debug.scala:451:33] reg [31:0] HAMASKReg_maskdata; // @[Debug.scala:477:32] wire _GEN = HAWINDOWSELReg_hawindowsel == 15'h0; // @[Debug.scala:451:33, :479:20] wire _GEN_0 = out_woready_13 & _GEN; // @[RegisterRouter.scala:87:24] wire hamask_0 = _GEN_0 ? auto_dmi_in_a_bits_data[0] : HAMASKReg_maskdata[0]; // @[Debug.scala:477:32, :487:30, :495:54, :496:48, :497:74, :498:44, :500:44] wire hamask_1 = _GEN_0 ? auto_dmi_in_a_bits_data[1] : HAMASKReg_maskdata[1]; // @[Debug.scala:477:32, :487:30, :495:54, :496:48, :497:74, :498:44, :500:44] wire hamask_2 = _GEN_0 ? auto_dmi_in_a_bits_data[2] : HAMASKReg_maskdata[2]; // @[Debug.scala:477:32, :487:30, :495:54, :496:48, :497:74, :498:44, :500:44] wire hamask_3 = _GEN_0 ? auto_dmi_in_a_bits_data[3] : HAMASKReg_maskdata[3]; // @[Debug.scala:477:32, :487:30, :495:54, :496:48, :497:74, :498:44, :500:44] wire hamask_4 = _GEN_0 ? auto_dmi_in_a_bits_data[4] : HAMASKReg_maskdata[4]; // @[Debug.scala:477:32, :487:30, :495:54, :496:48, :497:74, :498:44, :500:44] wire hamask_5 = _GEN_0 ? auto_dmi_in_a_bits_data[5] : HAMASKReg_maskdata[5]; // @[Debug.scala:477:32, :487:30, :495:54, :496:48, :497:74, :498:44, :500:44] wire hamask_6 = _GEN_0 ? auto_dmi_in_a_bits_data[6] : HAMASKReg_maskdata[6]; // @[Debug.scala:477:32, :487:30, :495:54, :496:48, :497:74, :498:44, :500:44] wire hamask_7 = _GEN_0 ? auto_dmi_in_a_bits_data[7] : HAMASKReg_maskdata[7]; // @[Debug.scala:477:32, :487:30, :495:54, :496:48, :497:74, :498:44, :500:44] reg hrmaskReg_0; // @[Debug.scala:519:28] reg hrmaskReg_1; // @[Debug.scala:519:28] reg hrmaskReg_2; // @[Debug.scala:519:28] reg hrmaskReg_3; // @[Debug.scala:519:28] reg hrmaskReg_4; // @[Debug.scala:519:28] reg hrmaskReg_5; // @[Debug.scala:519:28] reg hrmaskReg_6; // @[Debug.scala:519:28] reg hrmaskReg_7; // @[Debug.scala:519:28] wire _GEN_1 = out_woready_9 & DMCONTROLWrData_clrresethaltreq; // @[RegisterRouter.scala:87:24] wire _GEN_2 = io_innerCtrl_bits_hartsel_0 == 10'h0 | io_innerCtrl_bits_hasel_0 & hamask_0; // @[Debug.scala:446:{35,47}, :447:56, :497:74, :498:44, :500:44, :642:42, :647:42] wire _GEN_3 = out_woready_9 & DMCONTROLWrData_setresethaltreq; // @[RegisterRouter.scala:87:24] wire hrmaskNxt_0 = ~(~DMCONTROLReg_dmactive | _GEN_1 & _GEN_2) & (_GEN_3 & _GEN_2 | hrmaskReg_0); // @[Debug.scala:379:31, :398:11, :446:47, :519:28, :521:15, :523:44, :524:30, :525:{39,74,102}, :526:30, :527:{39,74,102}, :528:30] wire _GEN_4 = io_innerCtrl_bits_hartsel_0 == 10'h1 | io_innerCtrl_bits_hasel_0 & hamask_1; // @[Debug.scala:446:{35,47}, :447:56, :497:74, :498:44, :500:44, :642:42, :647:42] wire hrmaskNxt_1 = ~(~DMCONTROLReg_dmactive | _GEN_1 & _GEN_4) & (_GEN_3 & _GEN_4 | hrmaskReg_1); // @[Debug.scala:379:31, :398:11, :446:47, :519:28, :521:15, :523:44, :524:30, :525:{39,74,102}, :526:30, :527:{39,74,102}, :528:30] wire _GEN_5 = io_innerCtrl_bits_hartsel_0 == 10'h2 | io_innerCtrl_bits_hasel_0 & hamask_2; // @[Debug.scala:446:{35,47}, :447:56, :497:74, :498:44, :500:44, :642:42, :647:42] wire hrmaskNxt_2 = ~(~DMCONTROLReg_dmactive | _GEN_1 & _GEN_5) & (_GEN_3 & _GEN_5 | hrmaskReg_2); // @[Debug.scala:379:31, :398:11, :446:47, :519:28, :521:15, :523:44, :524:30, :525:{39,74,102}, :526:30, :527:{39,74,102}, :528:30] wire _GEN_6 = io_innerCtrl_bits_hartsel_0 == 10'h3 | io_innerCtrl_bits_hasel_0 & hamask_3; // @[Debug.scala:446:{35,47}, :447:56, :497:74, :498:44, :500:44, :642:42, :647:42] wire hrmaskNxt_3 = ~(~DMCONTROLReg_dmactive | _GEN_1 & _GEN_6) & (_GEN_3 & _GEN_6 | hrmaskReg_3); // @[Debug.scala:379:31, :398:11, :446:47, :519:28, :521:15, :523:44, :524:30, :525:{39,74,102}, :526:30, :527:{39,74,102}, :528:30] wire _GEN_7 = io_innerCtrl_bits_hartsel_0 == 10'h4 | io_innerCtrl_bits_hasel_0 & hamask_4; // @[Debug.scala:446:{35,47}, :447:56, :497:74, :498:44, :500:44, :642:42, :647:42] wire hrmaskNxt_4 = ~(~DMCONTROLReg_dmactive | _GEN_1 & _GEN_7) & (_GEN_3 & _GEN_7 | hrmaskReg_4); // @[Debug.scala:379:31, :398:11, :446:47, :519:28, :521:15, :523:44, :524:30, :525:{39,74,102}, :526:30, :527:{39,74,102}, :528:30] wire _GEN_8 = io_innerCtrl_bits_hartsel_0 == 10'h5 | io_innerCtrl_bits_hasel_0 & hamask_5; // @[Debug.scala:446:{35,47}, :447:56, :497:74, :498:44, :500:44, :642:42, :647:42] wire hrmaskNxt_5 = ~(~DMCONTROLReg_dmactive | _GEN_1 & _GEN_8) & (_GEN_3 & _GEN_8 | hrmaskReg_5); // @[Debug.scala:379:31, :398:11, :446:47, :519:28, :521:15, :523:44, :524:30, :525:{39,74,102}, :526:30, :527:{39,74,102}, :528:30] wire _GEN_9 = io_innerCtrl_bits_hartsel_0 == 10'h6 | io_innerCtrl_bits_hasel_0 & hamask_6; // @[Debug.scala:446:{35,47}, :447:56, :497:74, :498:44, :500:44, :642:42, :647:42] wire hrmaskNxt_6 = ~(~DMCONTROLReg_dmactive | _GEN_1 & _GEN_9) & (_GEN_3 & _GEN_9 | hrmaskReg_6); // @[Debug.scala:379:31, :398:11, :446:47, :519:28, :521:15, :523:44, :524:30, :525:{39,74,102}, :526:30, :527:{39,74,102}, :528:30] wire _GEN_10 = io_innerCtrl_bits_hartsel_0 == 10'h7 | io_innerCtrl_bits_hasel_0 & hamask_7; // @[Debug.scala:446:{35,47}, :447:56, :497:74, :498:44, :500:44, :642:42, :647:42] wire hrmaskNxt_7 = ~(~DMCONTROLReg_dmactive | _GEN_1 & _GEN_10) & (_GEN_3 & _GEN_10 | hrmaskReg_7); // @[Debug.scala:379:31, :398:11, :446:47, :519:28, :521:15, :523:44, :524:30, :525:{39,74,102}, :526:30, :527:{39,74,102}, :528:30] wire in_bits_read = auto_dmi_in_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign DMCONTROLWrData_clrresethaltreq = auto_dmi_in_a_bits_data[2]; // @[RegisterRouter.scala:87:24] assign DMCONTROLWrData_setresethaltreq = auto_dmi_in_a_bits_data[3]; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & ~in_bits_read; // @[RegisterRouter.scala:74:36, :87:24] assign out_woready_9 = _out_wofireMux_T_2 & auto_dmi_in_a_bits_address[4:3] == 2'h0 & ~(auto_dmi_in_a_bits_address[2]); // @[RegisterRouter.scala:75:19, :87:24] assign out_woready_13 = _out_wofireMux_T_2 & auto_dmi_in_a_bits_address[4:3] == 2'h2 & auto_dmi_in_a_bits_address[2]; // @[RegisterRouter.scala:75:19, :87:24] wire [3:0] _GEN_11 = {{1'h1}, {auto_dmi_in_a_bits_address[2]}, {~(auto_dmi_in_a_bits_address[2])}, {~(auto_dmi_in_a_bits_address[2])}}; // @[MuxLiteral.scala:49:10] wire [3:0][31:0] _GEN_12 = {{32'h0}, {{24'h0, _GEN ? HAMASKReg_maskdata[7:0] : 8'h0}}, {32'h118380}, {{DMCONTROLReg_haltreq, 4'h0, DMCONTROLReg_hasel, 7'h0, DMCONTROLReg_hartsello[2:0], 14'h0, DMCONTROLReg_ndmreset, DMCONTROLReg_dmactive & io_ctrl_dmactiveAck}}}; // @[MuxLiteral.scala:49:{10,48}] wire [2:0] dmiNodeIn_d_bits_opcode = {2'h0, in_bits_read}; // @[RegisterRouter.scala:74:36, :105:19] reg debugIntRegs_0; // @[Debug.scala:600:31] reg debugIntRegs_1; // @[Debug.scala:600:31] reg debugIntRegs_2; // @[Debug.scala:600:31] reg debugIntRegs_3; // @[Debug.scala:600:31] reg debugIntRegs_4; // @[Debug.scala:600:31] reg debugIntRegs_5; // @[Debug.scala:600:31] reg debugIntRegs_6; // @[Debug.scala:600:31] reg debugIntRegs_7; // @[Debug.scala:600:31] reg innerCtrlValidReg; // @[Debug.scala:630:36] reg innerCtrlResumeReqReg; // @[Debug.scala:631:40] reg innerCtrlAckHaveResetReg; // @[Debug.scala:632:43] wire io_innerCtrl_valid_0 = out_woready_9 | out_woready_13 | innerCtrlValidReg; // @[RegisterRouter.scala:87:24] assign io_innerCtrl_bits_hartsel_0 = out_woready_9 ? {7'h0, auto_dmi_in_a_bits_data[18:16]} : DMCONTROLReg_hartsello; // @[RegisterRouter.scala:87:24] wire io_innerCtrl_bits_resumereq_0 = out_woready_9 & auto_dmi_in_a_bits_data[30] | innerCtrlResumeReqReg; // @[RegisterRouter.scala:87:24] wire io_innerCtrl_bits_ackhavereset_0 = out_woready_9 & auto_dmi_in_a_bits_data[28] | innerCtrlAckHaveResetReg; // @[RegisterRouter.scala:87:24] assign io_innerCtrl_bits_hasel_0 = out_woready_9 ? auto_dmi_in_a_bits_data[26] : DMCONTROLReg_hasel; // @[RegisterRouter.scala:87:24] always @(posedge clock or posedge reset) begin // @[Debug.scala:340:9] if (reset) begin // @[Debug.scala:340:9] DMCONTROLReg_haltreq <= 1'h0; // @[Debug.scala:379:31] DMCONTROLReg_hasel <= 1'h0; // @[Debug.scala:379:31] DMCONTROLReg_hartsello <= 10'h0; // @[Debug.scala:379:31] DMCONTROLReg_ndmreset <= 1'h0; // @[Debug.scala:379:31] DMCONTROLReg_dmactive <= 1'h0; // @[Debug.scala:379:31] HAWINDOWSELReg_hawindowsel <= 15'h0; // @[Debug.scala:451:33] HAMASKReg_maskdata <= 32'h0; // @[Debug.scala:477:32] hrmaskReg_0 <= 1'h0; // @[Debug.scala:519:28] hrmaskReg_1 <= 1'h0; // @[Debug.scala:519:28] hrmaskReg_2 <= 1'h0; // @[Debug.scala:519:28] hrmaskReg_3 <= 1'h0; // @[Debug.scala:519:28] hrmaskReg_4 <= 1'h0; // @[Debug.scala:519:28] hrmaskReg_5 <= 1'h0; // @[Debug.scala:519:28] hrmaskReg_6 <= 1'h0; // @[Debug.scala:519:28] hrmaskReg_7 <= 1'h0; // @[Debug.scala:519:28] debugIntRegs_0 <= 1'h0; // @[Debug.scala:600:31] debugIntRegs_1 <= 1'h0; // @[Debug.scala:600:31] debugIntRegs_2 <= 1'h0; // @[Debug.scala:600:31] debugIntRegs_3 <= 1'h0; // @[Debug.scala:600:31] debugIntRegs_4 <= 1'h0; // @[Debug.scala:600:31] debugIntRegs_5 <= 1'h0; // @[Debug.scala:600:31] debugIntRegs_6 <= 1'h0; // @[Debug.scala:600:31] debugIntRegs_7 <= 1'h0; // @[Debug.scala:600:31] innerCtrlValidReg <= 1'h0; // @[Debug.scala:630:36] innerCtrlResumeReqReg <= 1'h0; // @[Debug.scala:631:40] innerCtrlAckHaveResetReg <= 1'h0; // @[Debug.scala:632:43] end else begin // @[Debug.scala:340:9] DMCONTROLReg_haltreq <= DMCONTROLReg_dmactive & (out_woready_9 ? auto_dmi_in_a_bits_data[31] : DMCONTROLReg_haltreq); // @[RegisterRouter.scala:87:24] DMCONTROLReg_hasel <= DMCONTROLReg_dmactive & (out_woready_9 ? auto_dmi_in_a_bits_data[26] : DMCONTROLReg_hasel); // @[RegisterRouter.scala:87:24] if (DMCONTROLReg_dmactive) begin // @[Debug.scala:379:31] if (out_woready_9) // @[RegisterRouter.scala:87:24] DMCONTROLReg_hartsello <= {7'h0, auto_dmi_in_a_bits_data[18:16]}; // @[RegisterRouter.scala:87:24] end else // @[Debug.scala:379:31] DMCONTROLReg_hartsello <= 10'h0; // @[Debug.scala:379:31] DMCONTROLReg_ndmreset <= DMCONTROLReg_dmactive & (out_woready_9 ? auto_dmi_in_a_bits_data[1] : DMCONTROLReg_ndmreset); // @[RegisterRouter.scala:87:24] if (out_woready_9) // @[RegisterRouter.scala:87:24] DMCONTROLReg_dmactive <= auto_dmi_in_a_bits_data[0]; // @[RegisterRouter.scala:87:24] if (DMCONTROLReg_dmactive) begin // @[Debug.scala:379:31] if (_GEN_0) // @[Debug.scala:487:30] HAMASKReg_maskdata <= {24'h0, auto_dmi_in_a_bits_data[7:0]}; // @[RegisterRouter.scala:87:24] end else begin // @[Debug.scala:379:31] HAWINDOWSELReg_hawindowsel <= 15'h0; // @[Debug.scala:451:33] HAMASKReg_maskdata <= 32'h0; // @[Debug.scala:477:32] end hrmaskReg_0 <= hrmaskNxt_0; // @[Debug.scala:519:28, :523:44, :524:30, :525:102, :526:30, :527:102] hrmaskReg_1 <= hrmaskNxt_1; // @[Debug.scala:519:28, :523:44, :524:30, :525:102, :526:30, :527:102] hrmaskReg_2 <= hrmaskNxt_2; // @[Debug.scala:519:28, :523:44, :524:30, :525:102, :526:30, :527:102] hrmaskReg_3 <= hrmaskNxt_3; // @[Debug.scala:519:28, :523:44, :524:30, :525:102, :526:30, :527:102] hrmaskReg_4 <= hrmaskNxt_4; // @[Debug.scala:519:28, :523:44, :524:30, :525:102, :526:30, :527:102] hrmaskReg_5 <= hrmaskNxt_5; // @[Debug.scala:519:28, :523:44, :524:30, :525:102, :526:30, :527:102] hrmaskReg_6 <= hrmaskNxt_6; // @[Debug.scala:519:28, :523:44, :524:30, :525:102, :526:30, :527:102] hrmaskReg_7 <= hrmaskNxt_7; // @[Debug.scala:519:28, :523:44, :524:30, :525:102, :526:30, :527:102] debugIntRegs_0 <= DMCONTROLReg_dmactive & (out_woready_9 & (auto_dmi_in_a_bits_data[18:16] == 3'h0 | auto_dmi_in_a_bits_data[26] & hamask_0) ? auto_dmi_in_a_bits_data[31] : debugIntRegs_0); // @[RegisterRouter.scala:87:24] debugIntRegs_1 <= DMCONTROLReg_dmactive & (out_woready_9 & (auto_dmi_in_a_bits_data[18:16] == 3'h1 | auto_dmi_in_a_bits_data[26] & hamask_1) ? auto_dmi_in_a_bits_data[31] : debugIntRegs_1); // @[RegisterRouter.scala:87:24] debugIntRegs_2 <= DMCONTROLReg_dmactive & (out_woready_9 & (auto_dmi_in_a_bits_data[18:16] == 3'h2 | auto_dmi_in_a_bits_data[26] & hamask_2) ? auto_dmi_in_a_bits_data[31] : debugIntRegs_2); // @[RegisterRouter.scala:87:24] debugIntRegs_3 <= DMCONTROLReg_dmactive & (out_woready_9 & (auto_dmi_in_a_bits_data[18:16] == 3'h3 | auto_dmi_in_a_bits_data[26] & hamask_3) ? auto_dmi_in_a_bits_data[31] : debugIntRegs_3); // @[RegisterRouter.scala:87:24] debugIntRegs_4 <= DMCONTROLReg_dmactive & (out_woready_9 & (auto_dmi_in_a_bits_data[18:16] == 3'h4 | auto_dmi_in_a_bits_data[26] & hamask_4) ? auto_dmi_in_a_bits_data[31] : debugIntRegs_4); // @[RegisterRouter.scala:87:24] debugIntRegs_5 <= DMCONTROLReg_dmactive & (out_woready_9 & (auto_dmi_in_a_bits_data[18:16] == 3'h5 | auto_dmi_in_a_bits_data[26] & hamask_5) ? auto_dmi_in_a_bits_data[31] : debugIntRegs_5); // @[RegisterRouter.scala:87:24] debugIntRegs_6 <= DMCONTROLReg_dmactive & (out_woready_9 & (auto_dmi_in_a_bits_data[18:16] == 3'h6 | auto_dmi_in_a_bits_data[26] & hamask_6) ? auto_dmi_in_a_bits_data[31] : debugIntRegs_6); // @[RegisterRouter.scala:87:24] debugIntRegs_7 <= DMCONTROLReg_dmactive & (out_woready_9 & ((&(auto_dmi_in_a_bits_data[18:16])) | auto_dmi_in_a_bits_data[26] & hamask_7) ? auto_dmi_in_a_bits_data[31] : debugIntRegs_7); // @[RegisterRouter.scala:87:24] innerCtrlValidReg <= io_innerCtrl_valid_0 & ~io_innerCtrl_ready; // @[Debug.scala:630:36, :634:128, :637:{52,54}, :641:54] innerCtrlResumeReqReg <= io_innerCtrl_bits_resumereq_0 & ~io_innerCtrl_ready; // @[Debug.scala:631:40, :637:54, :638:61, :643:83] innerCtrlAckHaveResetReg <= io_innerCtrl_bits_ackhavereset_0 & ~io_innerCtrl_ready; // @[Debug.scala:632:43, :637:54, :639:64, :644:89] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module MulFullRawFN_16 : output io : { flip a : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, flip b : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<48>}} node _notSigNaN_invalidExc_T = and(io.a.isInf, io.b.isZero) node _notSigNaN_invalidExc_T_1 = and(io.a.isZero, io.b.isInf) node notSigNaN_invalidExc = or(_notSigNaN_invalidExc_T, _notSigNaN_invalidExc_T_1) node notNaN_isInfOut = or(io.a.isInf, io.b.isInf) node notNaN_isZeroOut = or(io.a.isZero, io.b.isZero) node notNaN_signOut = xor(io.a.sign, io.b.sign) node _common_sExpOut_T = add(io.a.sExp, io.b.sExp) node _common_sExpOut_T_1 = tail(_common_sExpOut_T, 1) node _common_sExpOut_T_2 = asSInt(_common_sExpOut_T_1) node _common_sExpOut_T_3 = sub(_common_sExpOut_T_2, asSInt(UInt<10>(0h100))) node _common_sExpOut_T_4 = tail(_common_sExpOut_T_3, 1) node common_sExpOut = asSInt(_common_sExpOut_T_4) node _common_sigOut_T = mul(io.a.sig, io.b.sig) node common_sigOut = bits(_common_sigOut_T, 47, 0) node _io_invalidExc_T = bits(io.a.sig, 22, 22) node _io_invalidExc_T_1 = eq(_io_invalidExc_T, UInt<1>(0h0)) node _io_invalidExc_T_2 = and(io.a.isNaN, _io_invalidExc_T_1) node _io_invalidExc_T_3 = bits(io.b.sig, 22, 22) node _io_invalidExc_T_4 = eq(_io_invalidExc_T_3, UInt<1>(0h0)) node _io_invalidExc_T_5 = and(io.b.isNaN, _io_invalidExc_T_4) node _io_invalidExc_T_6 = or(_io_invalidExc_T_2, _io_invalidExc_T_5) node _io_invalidExc_T_7 = or(_io_invalidExc_T_6, notSigNaN_invalidExc) connect io.invalidExc, _io_invalidExc_T_7 connect io.rawOut.isInf, notNaN_isInfOut connect io.rawOut.isZero, notNaN_isZeroOut connect io.rawOut.sExp, common_sExpOut node _io_rawOut_isNaN_T = or(io.a.isNaN, io.b.isNaN) connect io.rawOut.isNaN, _io_rawOut_isNaN_T connect io.rawOut.sign, notNaN_signOut connect io.rawOut.sig, common_sigOut
module MulFullRawFN_16( // @[MulRecFN.scala:47:7] input io_a_isNaN, // @[MulRecFN.scala:49:16] input io_a_isInf, // @[MulRecFN.scala:49:16] input io_a_isZero, // @[MulRecFN.scala:49:16] input io_a_sign, // @[MulRecFN.scala:49:16] input [9:0] io_a_sExp, // @[MulRecFN.scala:49:16] input [24:0] io_a_sig, // @[MulRecFN.scala:49:16] input io_b_isNaN, // @[MulRecFN.scala:49:16] input io_b_isInf, // @[MulRecFN.scala:49:16] input io_b_isZero, // @[MulRecFN.scala:49:16] input io_b_sign, // @[MulRecFN.scala:49:16] input [9:0] io_b_sExp, // @[MulRecFN.scala:49:16] input [24:0] io_b_sig, // @[MulRecFN.scala:49:16] output io_invalidExc, // @[MulRecFN.scala:49:16] output io_rawOut_isNaN, // @[MulRecFN.scala:49:16] output io_rawOut_isInf, // @[MulRecFN.scala:49:16] output io_rawOut_isZero, // @[MulRecFN.scala:49:16] output io_rawOut_sign, // @[MulRecFN.scala:49:16] output [9:0] io_rawOut_sExp, // @[MulRecFN.scala:49:16] output [47:0] io_rawOut_sig // @[MulRecFN.scala:49:16] ); wire io_a_isNaN_0 = io_a_isNaN; // @[MulRecFN.scala:47:7] wire io_a_isInf_0 = io_a_isInf; // @[MulRecFN.scala:47:7] wire io_a_isZero_0 = io_a_isZero; // @[MulRecFN.scala:47:7] wire io_a_sign_0 = io_a_sign; // @[MulRecFN.scala:47:7] wire [9:0] io_a_sExp_0 = io_a_sExp; // @[MulRecFN.scala:47:7] wire [24:0] io_a_sig_0 = io_a_sig; // @[MulRecFN.scala:47:7] wire io_b_isNaN_0 = io_b_isNaN; // @[MulRecFN.scala:47:7] wire io_b_isInf_0 = io_b_isInf; // @[MulRecFN.scala:47:7] wire io_b_isZero_0 = io_b_isZero; // @[MulRecFN.scala:47:7] wire io_b_sign_0 = io_b_sign; // @[MulRecFN.scala:47:7] wire [9:0] io_b_sExp_0 = io_b_sExp; // @[MulRecFN.scala:47:7] wire [24:0] io_b_sig_0 = io_b_sig; // @[MulRecFN.scala:47:7] wire _io_invalidExc_T_7; // @[MulRecFN.scala:66:71] wire _io_rawOut_isNaN_T; // @[MulRecFN.scala:70:35] wire notNaN_isInfOut; // @[MulRecFN.scala:59:38] wire notNaN_isZeroOut; // @[MulRecFN.scala:60:40] wire notNaN_signOut; // @[MulRecFN.scala:61:36] wire [9:0] common_sExpOut; // @[MulRecFN.scala:62:48] wire [47:0] common_sigOut; // @[MulRecFN.scala:63:46] wire io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7] wire io_rawOut_isInf_0; // @[MulRecFN.scala:47:7] wire io_rawOut_isZero_0; // @[MulRecFN.scala:47:7] wire io_rawOut_sign_0; // @[MulRecFN.scala:47:7] wire [9:0] io_rawOut_sExp_0; // @[MulRecFN.scala:47:7] wire [47:0] io_rawOut_sig_0; // @[MulRecFN.scala:47:7] wire io_invalidExc_0; // @[MulRecFN.scala:47:7] wire _notSigNaN_invalidExc_T = io_a_isInf_0 & io_b_isZero_0; // @[MulRecFN.scala:47:7, :58:44] wire _notSigNaN_invalidExc_T_1 = io_a_isZero_0 & io_b_isInf_0; // @[MulRecFN.scala:47:7, :58:76] wire notSigNaN_invalidExc = _notSigNaN_invalidExc_T | _notSigNaN_invalidExc_T_1; // @[MulRecFN.scala:58:{44,60,76}] assign notNaN_isInfOut = io_a_isInf_0 | io_b_isInf_0; // @[MulRecFN.scala:47:7, :59:38] assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulRecFN.scala:47:7, :59:38] assign notNaN_isZeroOut = io_a_isZero_0 | io_b_isZero_0; // @[MulRecFN.scala:47:7, :60:40] assign io_rawOut_isZero_0 = notNaN_isZeroOut; // @[MulRecFN.scala:47:7, :60:40] assign notNaN_signOut = io_a_sign_0 ^ io_b_sign_0; // @[MulRecFN.scala:47:7, :61:36] assign io_rawOut_sign_0 = notNaN_signOut; // @[MulRecFN.scala:47:7, :61:36] wire [10:0] _common_sExpOut_T = {io_a_sExp_0[9], io_a_sExp_0} + {io_b_sExp_0[9], io_b_sExp_0}; // @[MulRecFN.scala:47:7, :62:36] wire [9:0] _common_sExpOut_T_1 = _common_sExpOut_T[9:0]; // @[MulRecFN.scala:62:36] wire [9:0] _common_sExpOut_T_2 = _common_sExpOut_T_1; // @[MulRecFN.scala:62:36] wire [10:0] _common_sExpOut_T_3 = {_common_sExpOut_T_2[9], _common_sExpOut_T_2} - 11'h100; // @[MulRecFN.scala:62:{36,48}] wire [9:0] _common_sExpOut_T_4 = _common_sExpOut_T_3[9:0]; // @[MulRecFN.scala:62:48] assign common_sExpOut = _common_sExpOut_T_4; // @[MulRecFN.scala:62:48] assign io_rawOut_sExp_0 = common_sExpOut; // @[MulRecFN.scala:47:7, :62:48] wire [49:0] _common_sigOut_T = {25'h0, io_a_sig_0} * {25'h0, io_b_sig_0}; // @[MulRecFN.scala:47:7, :63:35] assign common_sigOut = _common_sigOut_T[47:0]; // @[MulRecFN.scala:63:{35,46}] assign io_rawOut_sig_0 = common_sigOut; // @[MulRecFN.scala:47:7, :63:46] wire _io_invalidExc_T = io_a_sig_0[22]; // @[common.scala:82:56] wire _io_invalidExc_T_1 = ~_io_invalidExc_T; // @[common.scala:82:{49,56}] wire _io_invalidExc_T_2 = io_a_isNaN_0 & _io_invalidExc_T_1; // @[common.scala:82:{46,49}] wire _io_invalidExc_T_3 = io_b_sig_0[22]; // @[common.scala:82:56] wire _io_invalidExc_T_4 = ~_io_invalidExc_T_3; // @[common.scala:82:{49,56}] wire _io_invalidExc_T_5 = io_b_isNaN_0 & _io_invalidExc_T_4; // @[common.scala:82:{46,49}] wire _io_invalidExc_T_6 = _io_invalidExc_T_2 | _io_invalidExc_T_5; // @[common.scala:82:46] assign _io_invalidExc_T_7 = _io_invalidExc_T_6 | notSigNaN_invalidExc; // @[MulRecFN.scala:58:60, :66:{45,71}] assign io_invalidExc_0 = _io_invalidExc_T_7; // @[MulRecFN.scala:47:7, :66:71] assign _io_rawOut_isNaN_T = io_a_isNaN_0 | io_b_isNaN_0; // @[MulRecFN.scala:47:7, :70:35] assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulRecFN.scala:47:7, :70:35] assign io_invalidExc = io_invalidExc_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulRecFN.scala:47:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_281 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_25 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<32>, clock reg c2 : SInt<32>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node c1_sign = bits(io.in_d, 19, 19) node c1_lo_lo_hi = cat(c1_sign, c1_sign) node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign) node c1_lo_hi_hi = cat(c1_sign, c1_sign) node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign) node c1_lo = cat(c1_lo_hi, c1_lo_lo) node c1_hi_lo_hi = cat(c1_sign, c1_sign) node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign) node c1_hi_hi_hi = cat(c1_sign, c1_sign) node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign) node c1_hi = cat(c1_hi_hi, c1_hi_lo) node _c1_T = cat(c1_hi, c1_lo) node c1_lo_1 = asUInt(io.in_d) node _c1_T_1 = cat(_c1_T, c1_lo_1) wire _c1_WIRE : SInt<32> node _c1_T_2 = asSInt(_c1_T_1) connect _c1_WIRE, _c1_T_2 connect c1, _c1_WIRE else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node c2_sign = bits(io.in_d, 19, 19) node c2_lo_lo_hi = cat(c2_sign, c2_sign) node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign) node c2_lo_hi_hi = cat(c2_sign, c2_sign) node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign) node c2_lo = cat(c2_lo_hi, c2_lo_lo) node c2_hi_lo_hi = cat(c2_sign, c2_sign) node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign) node c2_hi_hi_hi = cat(c2_sign, c2_sign) node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign) node c2_hi = cat(c2_hi_hi, c2_hi_lo) node _c2_T = cat(c2_hi, c2_lo) node c2_lo_1 = asUInt(io.in_d) node _c2_T_1 = cat(_c2_T, c2_lo_1) wire _c2_WIRE : SInt<32> node _c2_T_2 = asSInt(_c2_T_1) connect _c2_WIRE, _c2_T_2 connect c2, _c2_WIRE else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h1), _T_4) node _T_6 = or(UInt<1>(0h0), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c
module PE_281( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_25 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module SourceB : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<11>, set : UInt<10>, clients : UInt<8>}}, b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}} regreset remain : UInt<8>, clock, reset, UInt<8>(0h0) wire remain_set : UInt<8> connect remain_set, UInt<8>(0h0) wire remain_clr : UInt<8> connect remain_clr, UInt<8>(0h0) node _remain_T = or(remain, remain_set) node _remain_T_1 = not(remain_clr) node _remain_T_2 = and(_remain_T, _remain_T_1) connect remain, _remain_T_2 node busy = orr(remain) node todo = mux(busy, remain, io.req.bits.clients) node _next_T = shl(todo, 1) node _next_T_1 = bits(_next_T, 7, 0) node _next_T_2 = or(todo, _next_T_1) node _next_T_3 = shl(_next_T_2, 2) node _next_T_4 = bits(_next_T_3, 7, 0) node _next_T_5 = or(_next_T_2, _next_T_4) node _next_T_6 = shl(_next_T_5, 4) node _next_T_7 = bits(_next_T_6, 7, 0) node _next_T_8 = or(_next_T_5, _next_T_7) node _next_T_9 = bits(_next_T_8, 7, 0) node _next_T_10 = shl(_next_T_9, 1) node _next_T_11 = not(_next_T_10) node next = and(_next_T_11, todo) node _T = bits(remain, 0, 0) node _T_1 = bits(remain, 1, 1) node _T_2 = bits(remain, 2, 2) node _T_3 = bits(remain, 3, 3) node _T_4 = bits(remain, 4, 4) node _T_5 = bits(remain, 5, 5) node _T_6 = bits(remain, 6, 6) node _T_7 = bits(remain, 7, 7) node _T_8 = add(_T, _T_1) node _T_9 = bits(_T_8, 1, 0) node _T_10 = add(_T_2, _T_3) node _T_11 = bits(_T_10, 1, 0) node _T_12 = add(_T_9, _T_11) node _T_13 = bits(_T_12, 2, 0) node _T_14 = add(_T_4, _T_5) node _T_15 = bits(_T_14, 1, 0) node _T_16 = add(_T_6, _T_7) node _T_17 = bits(_T_16, 1, 0) node _T_18 = add(_T_15, _T_17) node _T_19 = bits(_T_18, 2, 0) node _T_20 = add(_T_13, _T_19) node _T_21 = bits(_T_20, 3, 0) node _T_22 = gt(_T_21, UInt<1>(0h1)) node _T_23 = eq(io.req.valid, UInt<1>(0h0)) node _T_24 = neq(io.req.bits.clients, UInt<1>(0h0)) node _T_25 = or(_T_23, _T_24) node _T_26 = asUInt(reset) node _T_27 = eq(_T_26, UInt<1>(0h0)) when _T_27 : node _T_28 = eq(_T_25, UInt<1>(0h0)) when _T_28 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SourceB.scala:59 assert (!io.req.valid || io.req.bits.clients =/= 0.U)\n") : printf assert(clock, _T_25, UInt<1>(0h1), "") : assert node _io_req_ready_T = eq(busy, UInt<1>(0h0)) connect io.req.ready, _io_req_ready_T node _T_29 = and(io.req.ready, io.req.valid) when _T_29 : connect remain_set, io.req.bits.clients wire b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect io.b, b node _b_valid_T = or(busy, io.req.valid) connect b.valid, _b_valid_T node _T_30 = and(b.ready, b.valid) when _T_30 : connect remain_clr, next node _T_31 = eq(b.ready, UInt<1>(0h0)) node _T_32 = and(b.valid, _T_31) node _tag_T = eq(busy, UInt<1>(0h0)) node _tag_T_1 = and(io.req.ready, io.req.valid) reg tag_r : UInt<11>, clock when _tag_T_1 : connect tag_r, io.req.bits.tag node tag = mux(_tag_T, io.req.bits.tag, tag_r) node _set_T = eq(busy, UInt<1>(0h0)) node _set_T_1 = and(io.req.ready, io.req.valid) reg set_r : UInt<10>, clock when _set_T_1 : connect set_r, io.req.bits.set node set = mux(_set_T, io.req.bits.set, set_r) node _param_T = eq(busy, UInt<1>(0h0)) node _param_T_1 = and(io.req.ready, io.req.valid) reg param_r : UInt<3>, clock when _param_T_1 : connect param_r, io.req.bits.param node param = mux(_param_T, io.req.bits.param, param_r) connect b.bits.opcode, UInt<3>(0h6) connect b.bits.param, param connect b.bits.size, UInt<3>(0h6) node _b_bits_source_T = bits(next, 0, 0) node _b_bits_source_T_1 = bits(next, 1, 1) node _b_bits_source_T_2 = bits(next, 2, 2) node _b_bits_source_T_3 = bits(next, 3, 3) node _b_bits_source_T_4 = bits(next, 4, 4) node _b_bits_source_T_5 = bits(next, 5, 5) node _b_bits_source_T_6 = bits(next, 6, 6) node _b_bits_source_T_7 = bits(next, 7, 7) node _b_bits_source_T_8 = mux(_b_bits_source_T, UInt<6>(0h3c), UInt<1>(0h0)) node _b_bits_source_T_9 = mux(_b_bits_source_T_1, UInt<6>(0h38), UInt<1>(0h0)) node _b_bits_source_T_10 = mux(_b_bits_source_T_2, UInt<6>(0h34), UInt<1>(0h0)) node _b_bits_source_T_11 = mux(_b_bits_source_T_3, UInt<6>(0h30), UInt<1>(0h0)) node _b_bits_source_T_12 = mux(_b_bits_source_T_4, UInt<6>(0h2c), UInt<1>(0h0)) node _b_bits_source_T_13 = mux(_b_bits_source_T_5, UInt<6>(0h28), UInt<1>(0h0)) node _b_bits_source_T_14 = mux(_b_bits_source_T_6, UInt<6>(0h24), UInt<1>(0h0)) node _b_bits_source_T_15 = mux(_b_bits_source_T_7, UInt<6>(0h20), UInt<1>(0h0)) node _b_bits_source_T_16 = or(_b_bits_source_T_8, _b_bits_source_T_9) node _b_bits_source_T_17 = or(_b_bits_source_T_16, _b_bits_source_T_10) node _b_bits_source_T_18 = or(_b_bits_source_T_17, _b_bits_source_T_11) node _b_bits_source_T_19 = or(_b_bits_source_T_18, _b_bits_source_T_12) node _b_bits_source_T_20 = or(_b_bits_source_T_19, _b_bits_source_T_13) node _b_bits_source_T_21 = or(_b_bits_source_T_20, _b_bits_source_T_14) node _b_bits_source_T_22 = or(_b_bits_source_T_21, _b_bits_source_T_15) wire _b_bits_source_WIRE : UInt<6> connect _b_bits_source_WIRE, _b_bits_source_T_22 connect b.bits.source, _b_bits_source_WIRE node b_bits_address_base_y = or(tag, UInt<11>(0h0)) node _b_bits_address_base_T = shr(b_bits_address_base_y, 11) node _b_bits_address_base_T_1 = eq(_b_bits_address_base_T, UInt<1>(0h0)) node _b_bits_address_base_T_2 = asUInt(reset) node _b_bits_address_base_T_3 = eq(_b_bits_address_base_T_2, UInt<1>(0h0)) when _b_bits_address_base_T_3 : node _b_bits_address_base_T_4 = eq(_b_bits_address_base_T_1, UInt<1>(0h0)) when _b_bits_address_base_T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Parameters.scala:222 assert (y >> width === 0.U)\n") : b_bits_address_base_printf assert(clock, _b_bits_address_base_T_1, UInt<1>(0h1), "") : b_bits_address_base_assert node _b_bits_address_base_T_5 = bits(b_bits_address_base_y, 10, 0) node b_bits_address_base_y_1 = or(set, UInt<10>(0h0)) node _b_bits_address_base_T_6 = shr(b_bits_address_base_y_1, 10) node _b_bits_address_base_T_7 = eq(_b_bits_address_base_T_6, UInt<1>(0h0)) node _b_bits_address_base_T_8 = asUInt(reset) node _b_bits_address_base_T_9 = eq(_b_bits_address_base_T_8, UInt<1>(0h0)) when _b_bits_address_base_T_9 : node _b_bits_address_base_T_10 = eq(_b_bits_address_base_T_7, UInt<1>(0h0)) when _b_bits_address_base_T_10 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Parameters.scala:222 assert (y >> width === 0.U)\n") : b_bits_address_base_printf_1 assert(clock, _b_bits_address_base_T_7, UInt<1>(0h1), "") : b_bits_address_base_assert_1 node _b_bits_address_base_T_11 = bits(b_bits_address_base_y_1, 9, 0) node b_bits_address_base_y_2 = or(UInt<1>(0h0), UInt<6>(0h0)) node _b_bits_address_base_T_12 = shr(b_bits_address_base_y_2, 6) node _b_bits_address_base_T_13 = eq(_b_bits_address_base_T_12, UInt<1>(0h0)) node _b_bits_address_base_T_14 = asUInt(reset) node _b_bits_address_base_T_15 = eq(_b_bits_address_base_T_14, UInt<1>(0h0)) when _b_bits_address_base_T_15 : node _b_bits_address_base_T_16 = eq(_b_bits_address_base_T_13, UInt<1>(0h0)) when _b_bits_address_base_T_16 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Parameters.scala:222 assert (y >> width === 0.U)\n") : b_bits_address_base_printf_2 assert(clock, _b_bits_address_base_T_13, UInt<1>(0h1), "") : b_bits_address_base_assert_2 node _b_bits_address_base_T_17 = bits(b_bits_address_base_y_2, 5, 0) node b_bits_address_base_hi = cat(_b_bits_address_base_T_5, _b_bits_address_base_T_11) node b_bits_address_base = cat(b_bits_address_base_hi, _b_bits_address_base_T_17) node _b_bits_address_T = bits(b_bits_address_base, 0, 0) node _b_bits_address_T_1 = bits(b_bits_address_base, 1, 1) node _b_bits_address_T_2 = bits(b_bits_address_base, 2, 2) node _b_bits_address_T_3 = bits(b_bits_address_base, 3, 3) node _b_bits_address_T_4 = bits(b_bits_address_base, 4, 4) node _b_bits_address_T_5 = bits(b_bits_address_base, 5, 5) node _b_bits_address_T_6 = bits(b_bits_address_base, 6, 6) node _b_bits_address_T_7 = bits(b_bits_address_base, 7, 7) node _b_bits_address_T_8 = bits(b_bits_address_base, 8, 8) node _b_bits_address_T_9 = bits(b_bits_address_base, 9, 9) node _b_bits_address_T_10 = bits(b_bits_address_base, 10, 10) node _b_bits_address_T_11 = bits(b_bits_address_base, 11, 11) node _b_bits_address_T_12 = bits(b_bits_address_base, 12, 12) node _b_bits_address_T_13 = bits(b_bits_address_base, 13, 13) node _b_bits_address_T_14 = bits(b_bits_address_base, 14, 14) node _b_bits_address_T_15 = bits(b_bits_address_base, 15, 15) node _b_bits_address_T_16 = bits(b_bits_address_base, 16, 16) node _b_bits_address_T_17 = bits(b_bits_address_base, 17, 17) node _b_bits_address_T_18 = bits(b_bits_address_base, 18, 18) node _b_bits_address_T_19 = bits(b_bits_address_base, 19, 19) node _b_bits_address_T_20 = bits(b_bits_address_base, 20, 20) node _b_bits_address_T_21 = bits(b_bits_address_base, 21, 21) node _b_bits_address_T_22 = bits(b_bits_address_base, 22, 22) node _b_bits_address_T_23 = bits(b_bits_address_base, 23, 23) node _b_bits_address_T_24 = bits(b_bits_address_base, 24, 24) node _b_bits_address_T_25 = bits(b_bits_address_base, 25, 25) node _b_bits_address_T_26 = bits(b_bits_address_base, 26, 26) node b_bits_address_lo_lo_lo_lo = cat(_b_bits_address_T_1, _b_bits_address_T) node b_bits_address_lo_lo_lo_hi = cat(_b_bits_address_T_3, _b_bits_address_T_2) node b_bits_address_lo_lo_lo = cat(b_bits_address_lo_lo_lo_hi, b_bits_address_lo_lo_lo_lo) node b_bits_address_lo_lo_hi_lo = cat(_b_bits_address_T_5, _b_bits_address_T_4) node b_bits_address_lo_lo_hi_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node b_bits_address_lo_lo_hi = cat(b_bits_address_lo_lo_hi_hi, b_bits_address_lo_lo_hi_lo) node b_bits_address_lo_lo = cat(b_bits_address_lo_lo_hi, b_bits_address_lo_lo_lo) node b_bits_address_lo_hi_lo_lo = cat(_b_bits_address_T_7, _b_bits_address_T_6) node b_bits_address_lo_hi_lo_hi = cat(_b_bits_address_T_9, _b_bits_address_T_8) node b_bits_address_lo_hi_lo = cat(b_bits_address_lo_hi_lo_hi, b_bits_address_lo_hi_lo_lo) node b_bits_address_lo_hi_hi_lo = cat(_b_bits_address_T_11, _b_bits_address_T_10) node b_bits_address_lo_hi_hi_hi = cat(_b_bits_address_T_13, _b_bits_address_T_12) node b_bits_address_lo_hi_hi = cat(b_bits_address_lo_hi_hi_hi, b_bits_address_lo_hi_hi_lo) node b_bits_address_lo_hi = cat(b_bits_address_lo_hi_hi, b_bits_address_lo_hi_lo) node b_bits_address_lo = cat(b_bits_address_lo_hi, b_bits_address_lo_lo) node b_bits_address_hi_lo_lo_lo = cat(_b_bits_address_T_15, _b_bits_address_T_14) node b_bits_address_hi_lo_lo_hi = cat(_b_bits_address_T_17, _b_bits_address_T_16) node b_bits_address_hi_lo_lo = cat(b_bits_address_hi_lo_lo_hi, b_bits_address_hi_lo_lo_lo) node b_bits_address_hi_lo_hi_lo = cat(_b_bits_address_T_19, _b_bits_address_T_18) node b_bits_address_hi_lo_hi_hi = cat(_b_bits_address_T_21, _b_bits_address_T_20) node b_bits_address_hi_lo_hi = cat(b_bits_address_hi_lo_hi_hi, b_bits_address_hi_lo_hi_lo) node b_bits_address_hi_lo = cat(b_bits_address_hi_lo_hi, b_bits_address_hi_lo_lo) node b_bits_address_hi_hi_lo_lo = cat(_b_bits_address_T_23, _b_bits_address_T_22) node b_bits_address_hi_hi_lo_hi = cat(_b_bits_address_T_25, _b_bits_address_T_24) node b_bits_address_hi_hi_lo = cat(b_bits_address_hi_hi_lo_hi, b_bits_address_hi_hi_lo_lo) node b_bits_address_hi_hi_hi_lo = cat(UInt<1>(0h0), UInt<1>(0h0)) node b_bits_address_hi_hi_hi_hi = cat(_b_bits_address_T_26, UInt<1>(0h0)) node b_bits_address_hi_hi_hi = cat(b_bits_address_hi_hi_hi_hi, b_bits_address_hi_hi_hi_lo) node b_bits_address_hi_hi = cat(b_bits_address_hi_hi_hi, b_bits_address_hi_hi_lo) node b_bits_address_hi = cat(b_bits_address_hi_hi, b_bits_address_hi_lo) node _b_bits_address_T_27 = cat(b_bits_address_hi, b_bits_address_lo) connect b.bits.address, _b_bits_address_T_27 node _b_bits_mask_T = not(UInt<8>(0h0)) connect b.bits.mask, _b_bits_mask_T connect b.bits.data, UInt<1>(0h0) connect b.bits.corrupt, UInt<1>(0h0)
module SourceB( // @[SourceB.scala:33:7] input clock, // @[SourceB.scala:33:7] input reset, // @[SourceB.scala:33:7] output io_req_ready, // @[SourceB.scala:35:14] input io_req_valid, // @[SourceB.scala:35:14] input [2:0] io_req_bits_param, // @[SourceB.scala:35:14] input [10:0] io_req_bits_tag, // @[SourceB.scala:35:14] input [9:0] io_req_bits_set, // @[SourceB.scala:35:14] input [7:0] io_req_bits_clients, // @[SourceB.scala:35:14] input io_b_ready, // @[SourceB.scala:35:14] output io_b_valid, // @[SourceB.scala:35:14] output [1:0] io_b_bits_param, // @[SourceB.scala:35:14] output [5:0] io_b_bits_source, // @[SourceB.scala:35:14] output [31:0] io_b_bits_address // @[SourceB.scala:35:14] ); reg [7:0] remain; // @[SourceB.scala:46:25] wire [7:0] todo = (|remain) ? remain : io_req_bits_clients; // @[SourceB.scala:46:25, :51:23, :52:19] wire [6:0] _next_T_2 = todo[6:0] | {todo[5:0], 1'h0}; // @[package.scala:253:{43,53}] wire [6:0] _next_T_5 = _next_T_2 | {_next_T_2[4:0], 2'h0}; // @[package.scala:253:{43,53}] wire [7:0] _GEN = {~(_next_T_5 | {_next_T_5[2:0], 4'h0}), 1'h1} & todo; // @[package.scala:253:{43,53}]
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_246 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x
module OptimizationBarrier_TLBEntryData_246( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_25 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[9] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 node _source_ok_T_29 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[2]) node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[3]) node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[4]) node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[5]) node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[6]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[7]) node source_ok = or(_source_ok_T_35, _source_ok_WIRE[8]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = and(_T_11, _T_24) node _T_97 = and(_T_96, _T_37) node _T_98 = and(_T_97, _T_50) node _T_99 = and(_T_98, _T_63) node _T_100 = and(_T_99, _T_71) node _T_101 = and(_T_100, _T_79) node _T_102 = and(_T_101, _T_87) node _T_103 = and(_T_102, _T_95) node _T_104 = asUInt(reset) node _T_105 = eq(_T_104, UInt<1>(0h0)) when _T_105 : node _T_106 = eq(_T_103, UInt<1>(0h0)) when _T_106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_103, UInt<1>(0h1), "") : assert_1 node _T_107 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_107 : node _T_108 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_109 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_112 = shr(io.in.a.bits.source, 2) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = leq(UInt<1>(0h0), uncommonBits_4) node _T_115 = and(_T_113, _T_114) node _T_116 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_117 = and(_T_115, _T_116) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_118 = shr(io.in.a.bits.source, 2) node _T_119 = eq(_T_118, UInt<1>(0h1)) node _T_120 = leq(UInt<1>(0h0), uncommonBits_5) node _T_121 = and(_T_119, _T_120) node _T_122 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_123 = and(_T_121, _T_122) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_124 = shr(io.in.a.bits.source, 2) node _T_125 = eq(_T_124, UInt<2>(0h2)) node _T_126 = leq(UInt<1>(0h0), uncommonBits_6) node _T_127 = and(_T_125, _T_126) node _T_128 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_129 = and(_T_127, _T_128) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_130 = shr(io.in.a.bits.source, 2) node _T_131 = eq(_T_130, UInt<2>(0h3)) node _T_132 = leq(UInt<1>(0h0), uncommonBits_7) node _T_133 = and(_T_131, _T_132) node _T_134 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_135 = and(_T_133, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_137 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_138 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_139 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_140 = or(_T_111, _T_117) node _T_141 = or(_T_140, _T_123) node _T_142 = or(_T_141, _T_129) node _T_143 = or(_T_142, _T_135) node _T_144 = or(_T_143, _T_136) node _T_145 = or(_T_144, _T_137) node _T_146 = or(_T_145, _T_138) node _T_147 = or(_T_146, _T_139) node _T_148 = and(_T_110, _T_147) node _T_149 = or(UInt<1>(0h0), _T_148) node _T_150 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_151 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_152 = cvt(_T_151) node _T_153 = and(_T_152, asSInt(UInt<13>(0h1000))) node _T_154 = asSInt(_T_153) node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) node _T_156 = and(_T_150, _T_155) node _T_157 = or(UInt<1>(0h0), _T_156) node _T_158 = and(_T_149, _T_157) node _T_159 = asUInt(reset) node _T_160 = eq(_T_159, UInt<1>(0h0)) when _T_160 : node _T_161 = eq(_T_158, UInt<1>(0h0)) when _T_161 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_158, UInt<1>(0h1), "") : assert_2 node _T_162 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_163 = shr(io.in.a.bits.source, 2) node _T_164 = eq(_T_163, UInt<1>(0h0)) node _T_165 = leq(UInt<1>(0h0), uncommonBits_8) node _T_166 = and(_T_164, _T_165) node _T_167 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_168 = and(_T_166, _T_167) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_169 = shr(io.in.a.bits.source, 2) node _T_170 = eq(_T_169, UInt<1>(0h1)) node _T_171 = leq(UInt<1>(0h0), uncommonBits_9) node _T_172 = and(_T_170, _T_171) node _T_173 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_174 = and(_T_172, _T_173) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_175 = shr(io.in.a.bits.source, 2) node _T_176 = eq(_T_175, UInt<2>(0h2)) node _T_177 = leq(UInt<1>(0h0), uncommonBits_10) node _T_178 = and(_T_176, _T_177) node _T_179 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_180 = and(_T_178, _T_179) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_181 = shr(io.in.a.bits.source, 2) node _T_182 = eq(_T_181, UInt<2>(0h3)) node _T_183 = leq(UInt<1>(0h0), uncommonBits_11) node _T_184 = and(_T_182, _T_183) node _T_185 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_188 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_189 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_190 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[9] connect _WIRE[0], _T_162 connect _WIRE[1], _T_168 connect _WIRE[2], _T_174 connect _WIRE[3], _T_180 connect _WIRE[4], _T_186 connect _WIRE[5], _T_187 connect _WIRE[6], _T_188 connect _WIRE[7], _T_189 connect _WIRE[8], _T_190 node _T_191 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_192 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_193 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_194 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_195 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_196 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_197 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_198 = mux(_WIRE[6], _T_191, UInt<1>(0h0)) node _T_199 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_200 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_201 = or(_T_192, _T_193) node _T_202 = or(_T_201, _T_194) node _T_203 = or(_T_202, _T_195) node _T_204 = or(_T_203, _T_196) node _T_205 = or(_T_204, _T_197) node _T_206 = or(_T_205, _T_198) node _T_207 = or(_T_206, _T_199) node _T_208 = or(_T_207, _T_200) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_208 node _T_209 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_210 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_211 = and(_T_209, _T_210) node _T_212 = or(UInt<1>(0h0), _T_211) node _T_213 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_214 = cvt(_T_213) node _T_215 = and(_T_214, asSInt(UInt<13>(0h1000))) node _T_216 = asSInt(_T_215) node _T_217 = eq(_T_216, asSInt(UInt<1>(0h0))) node _T_218 = and(_T_212, _T_217) node _T_219 = or(UInt<1>(0h0), _T_218) node _T_220 = and(_WIRE_1, _T_219) node _T_221 = asUInt(reset) node _T_222 = eq(_T_221, UInt<1>(0h0)) when _T_222 : node _T_223 = eq(_T_220, UInt<1>(0h0)) when _T_223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_220, UInt<1>(0h1), "") : assert_3 node _T_224 = asUInt(reset) node _T_225 = eq(_T_224, UInt<1>(0h0)) when _T_225 : node _T_226 = eq(source_ok, UInt<1>(0h0)) when _T_226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_227 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_228 = asUInt(reset) node _T_229 = eq(_T_228, UInt<1>(0h0)) when _T_229 : node _T_230 = eq(_T_227, UInt<1>(0h0)) when _T_230 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_227, UInt<1>(0h1), "") : assert_5 node _T_231 = asUInt(reset) node _T_232 = eq(_T_231, UInt<1>(0h0)) when _T_232 : node _T_233 = eq(is_aligned, UInt<1>(0h0)) when _T_233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_234 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_235 = asUInt(reset) node _T_236 = eq(_T_235, UInt<1>(0h0)) when _T_236 : node _T_237 = eq(_T_234, UInt<1>(0h0)) when _T_237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_234, UInt<1>(0h1), "") : assert_7 node _T_238 = not(io.in.a.bits.mask) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_239, UInt<1>(0h1), "") : assert_8 node _T_243 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_244 = asUInt(reset) node _T_245 = eq(_T_244, UInt<1>(0h0)) when _T_245 : node _T_246 = eq(_T_243, UInt<1>(0h0)) when _T_246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_243, UInt<1>(0h1), "") : assert_9 node _T_247 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_247 : node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_250 = and(_T_248, _T_249) node _T_251 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_252 = shr(io.in.a.bits.source, 2) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = leq(UInt<1>(0h0), uncommonBits_12) node _T_255 = and(_T_253, _T_254) node _T_256 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_257 = and(_T_255, _T_256) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_258 = shr(io.in.a.bits.source, 2) node _T_259 = eq(_T_258, UInt<1>(0h1)) node _T_260 = leq(UInt<1>(0h0), uncommonBits_13) node _T_261 = and(_T_259, _T_260) node _T_262 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_263 = and(_T_261, _T_262) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_264 = shr(io.in.a.bits.source, 2) node _T_265 = eq(_T_264, UInt<2>(0h2)) node _T_266 = leq(UInt<1>(0h0), uncommonBits_14) node _T_267 = and(_T_265, _T_266) node _T_268 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_269 = and(_T_267, _T_268) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_270 = shr(io.in.a.bits.source, 2) node _T_271 = eq(_T_270, UInt<2>(0h3)) node _T_272 = leq(UInt<1>(0h0), uncommonBits_15) node _T_273 = and(_T_271, _T_272) node _T_274 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_275 = and(_T_273, _T_274) node _T_276 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_277 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_278 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_279 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_280 = or(_T_251, _T_257) node _T_281 = or(_T_280, _T_263) node _T_282 = or(_T_281, _T_269) node _T_283 = or(_T_282, _T_275) node _T_284 = or(_T_283, _T_276) node _T_285 = or(_T_284, _T_277) node _T_286 = or(_T_285, _T_278) node _T_287 = or(_T_286, _T_279) node _T_288 = and(_T_250, _T_287) node _T_289 = or(UInt<1>(0h0), _T_288) node _T_290 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_291 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_292 = cvt(_T_291) node _T_293 = and(_T_292, asSInt(UInt<13>(0h1000))) node _T_294 = asSInt(_T_293) node _T_295 = eq(_T_294, asSInt(UInt<1>(0h0))) node _T_296 = and(_T_290, _T_295) node _T_297 = or(UInt<1>(0h0), _T_296) node _T_298 = and(_T_289, _T_297) node _T_299 = asUInt(reset) node _T_300 = eq(_T_299, UInt<1>(0h0)) when _T_300 : node _T_301 = eq(_T_298, UInt<1>(0h0)) when _T_301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_298, UInt<1>(0h1), "") : assert_10 node _T_302 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_303 = shr(io.in.a.bits.source, 2) node _T_304 = eq(_T_303, UInt<1>(0h0)) node _T_305 = leq(UInt<1>(0h0), uncommonBits_16) node _T_306 = and(_T_304, _T_305) node _T_307 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_308 = and(_T_306, _T_307) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_309 = shr(io.in.a.bits.source, 2) node _T_310 = eq(_T_309, UInt<1>(0h1)) node _T_311 = leq(UInt<1>(0h0), uncommonBits_17) node _T_312 = and(_T_310, _T_311) node _T_313 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_314 = and(_T_312, _T_313) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_315 = shr(io.in.a.bits.source, 2) node _T_316 = eq(_T_315, UInt<2>(0h2)) node _T_317 = leq(UInt<1>(0h0), uncommonBits_18) node _T_318 = and(_T_316, _T_317) node _T_319 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_321 = shr(io.in.a.bits.source, 2) node _T_322 = eq(_T_321, UInt<2>(0h3)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_19) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_326 = and(_T_324, _T_325) node _T_327 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_329 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_330 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[9] connect _WIRE_2[0], _T_302 connect _WIRE_2[1], _T_308 connect _WIRE_2[2], _T_314 connect _WIRE_2[3], _T_320 connect _WIRE_2[4], _T_326 connect _WIRE_2[5], _T_327 connect _WIRE_2[6], _T_328 connect _WIRE_2[7], _T_329 connect _WIRE_2[8], _T_330 node _T_331 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_332 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_333 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_334 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_335 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_336 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_337 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_338 = mux(_WIRE_2[6], _T_331, UInt<1>(0h0)) node _T_339 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_340 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_341 = or(_T_332, _T_333) node _T_342 = or(_T_341, _T_334) node _T_343 = or(_T_342, _T_335) node _T_344 = or(_T_343, _T_336) node _T_345 = or(_T_344, _T_337) node _T_346 = or(_T_345, _T_338) node _T_347 = or(_T_346, _T_339) node _T_348 = or(_T_347, _T_340) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_348 node _T_349 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_350 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_351 = and(_T_349, _T_350) node _T_352 = or(UInt<1>(0h0), _T_351) node _T_353 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_354 = cvt(_T_353) node _T_355 = and(_T_354, asSInt(UInt<13>(0h1000))) node _T_356 = asSInt(_T_355) node _T_357 = eq(_T_356, asSInt(UInt<1>(0h0))) node _T_358 = and(_T_352, _T_357) node _T_359 = or(UInt<1>(0h0), _T_358) node _T_360 = and(_WIRE_3, _T_359) node _T_361 = asUInt(reset) node _T_362 = eq(_T_361, UInt<1>(0h0)) when _T_362 : node _T_363 = eq(_T_360, UInt<1>(0h0)) when _T_363 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_360, UInt<1>(0h1), "") : assert_11 node _T_364 = asUInt(reset) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : node _T_366 = eq(source_ok, UInt<1>(0h0)) when _T_366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_367 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_368 = asUInt(reset) node _T_369 = eq(_T_368, UInt<1>(0h0)) when _T_369 : node _T_370 = eq(_T_367, UInt<1>(0h0)) when _T_370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_367, UInt<1>(0h1), "") : assert_13 node _T_371 = asUInt(reset) node _T_372 = eq(_T_371, UInt<1>(0h0)) when _T_372 : node _T_373 = eq(is_aligned, UInt<1>(0h0)) when _T_373 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_374 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_375 = asUInt(reset) node _T_376 = eq(_T_375, UInt<1>(0h0)) when _T_376 : node _T_377 = eq(_T_374, UInt<1>(0h0)) when _T_377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_374, UInt<1>(0h1), "") : assert_15 node _T_378 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_T_378, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_378, UInt<1>(0h1), "") : assert_16 node _T_382 = not(io.in.a.bits.mask) node _T_383 = eq(_T_382, UInt<1>(0h0)) node _T_384 = asUInt(reset) node _T_385 = eq(_T_384, UInt<1>(0h0)) when _T_385 : node _T_386 = eq(_T_383, UInt<1>(0h0)) when _T_386 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_383, UInt<1>(0h1), "") : assert_17 node _T_387 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_387, UInt<1>(0h1), "") : assert_18 node _T_391 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_391 : node _T_392 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_393 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_394 = and(_T_392, _T_393) node _T_395 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_396 = shr(io.in.a.bits.source, 2) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = leq(UInt<1>(0h0), uncommonBits_20) node _T_399 = and(_T_397, _T_398) node _T_400 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_401 = and(_T_399, _T_400) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_402 = shr(io.in.a.bits.source, 2) node _T_403 = eq(_T_402, UInt<1>(0h1)) node _T_404 = leq(UInt<1>(0h0), uncommonBits_21) node _T_405 = and(_T_403, _T_404) node _T_406 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_407 = and(_T_405, _T_406) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_408 = shr(io.in.a.bits.source, 2) node _T_409 = eq(_T_408, UInt<2>(0h2)) node _T_410 = leq(UInt<1>(0h0), uncommonBits_22) node _T_411 = and(_T_409, _T_410) node _T_412 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_413 = and(_T_411, _T_412) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_414 = shr(io.in.a.bits.source, 2) node _T_415 = eq(_T_414, UInt<2>(0h3)) node _T_416 = leq(UInt<1>(0h0), uncommonBits_23) node _T_417 = and(_T_415, _T_416) node _T_418 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_419 = and(_T_417, _T_418) node _T_420 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_421 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_422 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_423 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_424 = or(_T_395, _T_401) node _T_425 = or(_T_424, _T_407) node _T_426 = or(_T_425, _T_413) node _T_427 = or(_T_426, _T_419) node _T_428 = or(_T_427, _T_420) node _T_429 = or(_T_428, _T_421) node _T_430 = or(_T_429, _T_422) node _T_431 = or(_T_430, _T_423) node _T_432 = and(_T_394, _T_431) node _T_433 = or(UInt<1>(0h0), _T_432) node _T_434 = asUInt(reset) node _T_435 = eq(_T_434, UInt<1>(0h0)) when _T_435 : node _T_436 = eq(_T_433, UInt<1>(0h0)) when _T_436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_433, UInt<1>(0h1), "") : assert_19 node _T_437 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_438 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_439 = and(_T_437, _T_438) node _T_440 = or(UInt<1>(0h0), _T_439) node _T_441 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_442 = cvt(_T_441) node _T_443 = and(_T_442, asSInt(UInt<13>(0h1000))) node _T_444 = asSInt(_T_443) node _T_445 = eq(_T_444, asSInt(UInt<1>(0h0))) node _T_446 = and(_T_440, _T_445) node _T_447 = or(UInt<1>(0h0), _T_446) node _T_448 = asUInt(reset) node _T_449 = eq(_T_448, UInt<1>(0h0)) when _T_449 : node _T_450 = eq(_T_447, UInt<1>(0h0)) when _T_450 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_447, UInt<1>(0h1), "") : assert_20 node _T_451 = asUInt(reset) node _T_452 = eq(_T_451, UInt<1>(0h0)) when _T_452 : node _T_453 = eq(source_ok, UInt<1>(0h0)) when _T_453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_454 = asUInt(reset) node _T_455 = eq(_T_454, UInt<1>(0h0)) when _T_455 : node _T_456 = eq(is_aligned, UInt<1>(0h0)) when _T_456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_457 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_T_457, UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_457, UInt<1>(0h1), "") : assert_23 node _T_461 = eq(io.in.a.bits.mask, mask) node _T_462 = asUInt(reset) node _T_463 = eq(_T_462, UInt<1>(0h0)) when _T_463 : node _T_464 = eq(_T_461, UInt<1>(0h0)) when _T_464 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_461, UInt<1>(0h1), "") : assert_24 node _T_465 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_466 = asUInt(reset) node _T_467 = eq(_T_466, UInt<1>(0h0)) when _T_467 : node _T_468 = eq(_T_465, UInt<1>(0h0)) when _T_468 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_465, UInt<1>(0h1), "") : assert_25 node _T_469 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_469 : node _T_470 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_471 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_472 = and(_T_470, _T_471) node _T_473 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_474 = shr(io.in.a.bits.source, 2) node _T_475 = eq(_T_474, UInt<1>(0h0)) node _T_476 = leq(UInt<1>(0h0), uncommonBits_24) node _T_477 = and(_T_475, _T_476) node _T_478 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_479 = and(_T_477, _T_478) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_480 = shr(io.in.a.bits.source, 2) node _T_481 = eq(_T_480, UInt<1>(0h1)) node _T_482 = leq(UInt<1>(0h0), uncommonBits_25) node _T_483 = and(_T_481, _T_482) node _T_484 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_485 = and(_T_483, _T_484) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_486 = shr(io.in.a.bits.source, 2) node _T_487 = eq(_T_486, UInt<2>(0h2)) node _T_488 = leq(UInt<1>(0h0), uncommonBits_26) node _T_489 = and(_T_487, _T_488) node _T_490 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_491 = and(_T_489, _T_490) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_492 = shr(io.in.a.bits.source, 2) node _T_493 = eq(_T_492, UInt<2>(0h3)) node _T_494 = leq(UInt<1>(0h0), uncommonBits_27) node _T_495 = and(_T_493, _T_494) node _T_496 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_497 = and(_T_495, _T_496) node _T_498 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_499 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_500 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_501 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_502 = or(_T_473, _T_479) node _T_503 = or(_T_502, _T_485) node _T_504 = or(_T_503, _T_491) node _T_505 = or(_T_504, _T_497) node _T_506 = or(_T_505, _T_498) node _T_507 = or(_T_506, _T_499) node _T_508 = or(_T_507, _T_500) node _T_509 = or(_T_508, _T_501) node _T_510 = and(_T_472, _T_509) node _T_511 = or(UInt<1>(0h0), _T_510) node _T_512 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_513 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_514 = and(_T_512, _T_513) node _T_515 = or(UInt<1>(0h0), _T_514) node _T_516 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_517 = cvt(_T_516) node _T_518 = and(_T_517, asSInt(UInt<13>(0h1000))) node _T_519 = asSInt(_T_518) node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0))) node _T_521 = and(_T_515, _T_520) node _T_522 = or(UInt<1>(0h0), _T_521) node _T_523 = and(_T_511, _T_522) node _T_524 = asUInt(reset) node _T_525 = eq(_T_524, UInt<1>(0h0)) when _T_525 : node _T_526 = eq(_T_523, UInt<1>(0h0)) when _T_526 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_523, UInt<1>(0h1), "") : assert_26 node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(source_ok, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_530 = asUInt(reset) node _T_531 = eq(_T_530, UInt<1>(0h0)) when _T_531 : node _T_532 = eq(is_aligned, UInt<1>(0h0)) when _T_532 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_533 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_534 = asUInt(reset) node _T_535 = eq(_T_534, UInt<1>(0h0)) when _T_535 : node _T_536 = eq(_T_533, UInt<1>(0h0)) when _T_536 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_533, UInt<1>(0h1), "") : assert_29 node _T_537 = eq(io.in.a.bits.mask, mask) node _T_538 = asUInt(reset) node _T_539 = eq(_T_538, UInt<1>(0h0)) when _T_539 : node _T_540 = eq(_T_537, UInt<1>(0h0)) when _T_540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_537, UInt<1>(0h1), "") : assert_30 node _T_541 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_541 : node _T_542 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_543 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_544 = and(_T_542, _T_543) node _T_545 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_546 = shr(io.in.a.bits.source, 2) node _T_547 = eq(_T_546, UInt<1>(0h0)) node _T_548 = leq(UInt<1>(0h0), uncommonBits_28) node _T_549 = and(_T_547, _T_548) node _T_550 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_551 = and(_T_549, _T_550) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_552 = shr(io.in.a.bits.source, 2) node _T_553 = eq(_T_552, UInt<1>(0h1)) node _T_554 = leq(UInt<1>(0h0), uncommonBits_29) node _T_555 = and(_T_553, _T_554) node _T_556 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_557 = and(_T_555, _T_556) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_558 = shr(io.in.a.bits.source, 2) node _T_559 = eq(_T_558, UInt<2>(0h2)) node _T_560 = leq(UInt<1>(0h0), uncommonBits_30) node _T_561 = and(_T_559, _T_560) node _T_562 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_563 = and(_T_561, _T_562) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_564 = shr(io.in.a.bits.source, 2) node _T_565 = eq(_T_564, UInt<2>(0h3)) node _T_566 = leq(UInt<1>(0h0), uncommonBits_31) node _T_567 = and(_T_565, _T_566) node _T_568 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_569 = and(_T_567, _T_568) node _T_570 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_571 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_572 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_573 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_574 = or(_T_545, _T_551) node _T_575 = or(_T_574, _T_557) node _T_576 = or(_T_575, _T_563) node _T_577 = or(_T_576, _T_569) node _T_578 = or(_T_577, _T_570) node _T_579 = or(_T_578, _T_571) node _T_580 = or(_T_579, _T_572) node _T_581 = or(_T_580, _T_573) node _T_582 = and(_T_544, _T_581) node _T_583 = or(UInt<1>(0h0), _T_582) node _T_584 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_585 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_586 = and(_T_584, _T_585) node _T_587 = or(UInt<1>(0h0), _T_586) node _T_588 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_589 = cvt(_T_588) node _T_590 = and(_T_589, asSInt(UInt<13>(0h1000))) node _T_591 = asSInt(_T_590) node _T_592 = eq(_T_591, asSInt(UInt<1>(0h0))) node _T_593 = and(_T_587, _T_592) node _T_594 = or(UInt<1>(0h0), _T_593) node _T_595 = and(_T_583, _T_594) node _T_596 = asUInt(reset) node _T_597 = eq(_T_596, UInt<1>(0h0)) when _T_597 : node _T_598 = eq(_T_595, UInt<1>(0h0)) when _T_598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_595, UInt<1>(0h1), "") : assert_31 node _T_599 = asUInt(reset) node _T_600 = eq(_T_599, UInt<1>(0h0)) when _T_600 : node _T_601 = eq(source_ok, UInt<1>(0h0)) when _T_601 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(is_aligned, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_605 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_606 = asUInt(reset) node _T_607 = eq(_T_606, UInt<1>(0h0)) when _T_607 : node _T_608 = eq(_T_605, UInt<1>(0h0)) when _T_608 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_605, UInt<1>(0h1), "") : assert_34 node _T_609 = not(mask) node _T_610 = and(io.in.a.bits.mask, _T_609) node _T_611 = eq(_T_610, UInt<1>(0h0)) node _T_612 = asUInt(reset) node _T_613 = eq(_T_612, UInt<1>(0h0)) when _T_613 : node _T_614 = eq(_T_611, UInt<1>(0h0)) when _T_614 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_611, UInt<1>(0h1), "") : assert_35 node _T_615 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_615 : node _T_616 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_617 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_618 = and(_T_616, _T_617) node _T_619 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_620 = shr(io.in.a.bits.source, 2) node _T_621 = eq(_T_620, UInt<1>(0h0)) node _T_622 = leq(UInt<1>(0h0), uncommonBits_32) node _T_623 = and(_T_621, _T_622) node _T_624 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_625 = and(_T_623, _T_624) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_626 = shr(io.in.a.bits.source, 2) node _T_627 = eq(_T_626, UInt<1>(0h1)) node _T_628 = leq(UInt<1>(0h0), uncommonBits_33) node _T_629 = and(_T_627, _T_628) node _T_630 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_631 = and(_T_629, _T_630) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_632 = shr(io.in.a.bits.source, 2) node _T_633 = eq(_T_632, UInt<2>(0h2)) node _T_634 = leq(UInt<1>(0h0), uncommonBits_34) node _T_635 = and(_T_633, _T_634) node _T_636 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_637 = and(_T_635, _T_636) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_638 = shr(io.in.a.bits.source, 2) node _T_639 = eq(_T_638, UInt<2>(0h3)) node _T_640 = leq(UInt<1>(0h0), uncommonBits_35) node _T_641 = and(_T_639, _T_640) node _T_642 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_643 = and(_T_641, _T_642) node _T_644 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_645 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_646 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_647 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_648 = or(_T_619, _T_625) node _T_649 = or(_T_648, _T_631) node _T_650 = or(_T_649, _T_637) node _T_651 = or(_T_650, _T_643) node _T_652 = or(_T_651, _T_644) node _T_653 = or(_T_652, _T_645) node _T_654 = or(_T_653, _T_646) node _T_655 = or(_T_654, _T_647) node _T_656 = and(_T_618, _T_655) node _T_657 = or(UInt<1>(0h0), _T_656) node _T_658 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_659 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_660 = cvt(_T_659) node _T_661 = and(_T_660, asSInt(UInt<13>(0h1000))) node _T_662 = asSInt(_T_661) node _T_663 = eq(_T_662, asSInt(UInt<1>(0h0))) node _T_664 = and(_T_658, _T_663) node _T_665 = or(UInt<1>(0h0), _T_664) node _T_666 = and(_T_657, _T_665) node _T_667 = asUInt(reset) node _T_668 = eq(_T_667, UInt<1>(0h0)) when _T_668 : node _T_669 = eq(_T_666, UInt<1>(0h0)) when _T_669 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_666, UInt<1>(0h1), "") : assert_36 node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(source_ok, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_673 = asUInt(reset) node _T_674 = eq(_T_673, UInt<1>(0h0)) when _T_674 : node _T_675 = eq(is_aligned, UInt<1>(0h0)) when _T_675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_676 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_677 = asUInt(reset) node _T_678 = eq(_T_677, UInt<1>(0h0)) when _T_678 : node _T_679 = eq(_T_676, UInt<1>(0h0)) when _T_679 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_676, UInt<1>(0h1), "") : assert_39 node _T_680 = eq(io.in.a.bits.mask, mask) node _T_681 = asUInt(reset) node _T_682 = eq(_T_681, UInt<1>(0h0)) when _T_682 : node _T_683 = eq(_T_680, UInt<1>(0h0)) when _T_683 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_680, UInt<1>(0h1), "") : assert_40 node _T_684 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_684 : node _T_685 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_686 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_687 = and(_T_685, _T_686) node _T_688 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_689 = shr(io.in.a.bits.source, 2) node _T_690 = eq(_T_689, UInt<1>(0h0)) node _T_691 = leq(UInt<1>(0h0), uncommonBits_36) node _T_692 = and(_T_690, _T_691) node _T_693 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_694 = and(_T_692, _T_693) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_695 = shr(io.in.a.bits.source, 2) node _T_696 = eq(_T_695, UInt<1>(0h1)) node _T_697 = leq(UInt<1>(0h0), uncommonBits_37) node _T_698 = and(_T_696, _T_697) node _T_699 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_700 = and(_T_698, _T_699) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_701 = shr(io.in.a.bits.source, 2) node _T_702 = eq(_T_701, UInt<2>(0h2)) node _T_703 = leq(UInt<1>(0h0), uncommonBits_38) node _T_704 = and(_T_702, _T_703) node _T_705 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_706 = and(_T_704, _T_705) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_707 = shr(io.in.a.bits.source, 2) node _T_708 = eq(_T_707, UInt<2>(0h3)) node _T_709 = leq(UInt<1>(0h0), uncommonBits_39) node _T_710 = and(_T_708, _T_709) node _T_711 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_712 = and(_T_710, _T_711) node _T_713 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_714 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_715 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_716 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_717 = or(_T_688, _T_694) node _T_718 = or(_T_717, _T_700) node _T_719 = or(_T_718, _T_706) node _T_720 = or(_T_719, _T_712) node _T_721 = or(_T_720, _T_713) node _T_722 = or(_T_721, _T_714) node _T_723 = or(_T_722, _T_715) node _T_724 = or(_T_723, _T_716) node _T_725 = and(_T_687, _T_724) node _T_726 = or(UInt<1>(0h0), _T_725) node _T_727 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_728 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_729 = cvt(_T_728) node _T_730 = and(_T_729, asSInt(UInt<13>(0h1000))) node _T_731 = asSInt(_T_730) node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0))) node _T_733 = and(_T_727, _T_732) node _T_734 = or(UInt<1>(0h0), _T_733) node _T_735 = and(_T_726, _T_734) node _T_736 = asUInt(reset) node _T_737 = eq(_T_736, UInt<1>(0h0)) when _T_737 : node _T_738 = eq(_T_735, UInt<1>(0h0)) when _T_738 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_735, UInt<1>(0h1), "") : assert_41 node _T_739 = asUInt(reset) node _T_740 = eq(_T_739, UInt<1>(0h0)) when _T_740 : node _T_741 = eq(source_ok, UInt<1>(0h0)) when _T_741 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_742 = asUInt(reset) node _T_743 = eq(_T_742, UInt<1>(0h0)) when _T_743 : node _T_744 = eq(is_aligned, UInt<1>(0h0)) when _T_744 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_745 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_746 = asUInt(reset) node _T_747 = eq(_T_746, UInt<1>(0h0)) when _T_747 : node _T_748 = eq(_T_745, UInt<1>(0h0)) when _T_748 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_745, UInt<1>(0h1), "") : assert_44 node _T_749 = eq(io.in.a.bits.mask, mask) node _T_750 = asUInt(reset) node _T_751 = eq(_T_750, UInt<1>(0h0)) when _T_751 : node _T_752 = eq(_T_749, UInt<1>(0h0)) when _T_752 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_749, UInt<1>(0h1), "") : assert_45 node _T_753 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_753 : node _T_754 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_755 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_756 = and(_T_754, _T_755) node _T_757 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_758 = shr(io.in.a.bits.source, 2) node _T_759 = eq(_T_758, UInt<1>(0h0)) node _T_760 = leq(UInt<1>(0h0), uncommonBits_40) node _T_761 = and(_T_759, _T_760) node _T_762 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_763 = and(_T_761, _T_762) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_764 = shr(io.in.a.bits.source, 2) node _T_765 = eq(_T_764, UInt<1>(0h1)) node _T_766 = leq(UInt<1>(0h0), uncommonBits_41) node _T_767 = and(_T_765, _T_766) node _T_768 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_769 = and(_T_767, _T_768) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_770 = shr(io.in.a.bits.source, 2) node _T_771 = eq(_T_770, UInt<2>(0h2)) node _T_772 = leq(UInt<1>(0h0), uncommonBits_42) node _T_773 = and(_T_771, _T_772) node _T_774 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_775 = and(_T_773, _T_774) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_776 = shr(io.in.a.bits.source, 2) node _T_777 = eq(_T_776, UInt<2>(0h3)) node _T_778 = leq(UInt<1>(0h0), uncommonBits_43) node _T_779 = and(_T_777, _T_778) node _T_780 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_781 = and(_T_779, _T_780) node _T_782 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_783 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_784 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_785 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_786 = or(_T_757, _T_763) node _T_787 = or(_T_786, _T_769) node _T_788 = or(_T_787, _T_775) node _T_789 = or(_T_788, _T_781) node _T_790 = or(_T_789, _T_782) node _T_791 = or(_T_790, _T_783) node _T_792 = or(_T_791, _T_784) node _T_793 = or(_T_792, _T_785) node _T_794 = and(_T_756, _T_793) node _T_795 = or(UInt<1>(0h0), _T_794) node _T_796 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_797 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_798 = cvt(_T_797) node _T_799 = and(_T_798, asSInt(UInt<13>(0h1000))) node _T_800 = asSInt(_T_799) node _T_801 = eq(_T_800, asSInt(UInt<1>(0h0))) node _T_802 = and(_T_796, _T_801) node _T_803 = or(UInt<1>(0h0), _T_802) node _T_804 = and(_T_795, _T_803) node _T_805 = asUInt(reset) node _T_806 = eq(_T_805, UInt<1>(0h0)) when _T_806 : node _T_807 = eq(_T_804, UInt<1>(0h0)) when _T_807 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_804, UInt<1>(0h1), "") : assert_46 node _T_808 = asUInt(reset) node _T_809 = eq(_T_808, UInt<1>(0h0)) when _T_809 : node _T_810 = eq(source_ok, UInt<1>(0h0)) when _T_810 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_811 = asUInt(reset) node _T_812 = eq(_T_811, UInt<1>(0h0)) when _T_812 : node _T_813 = eq(is_aligned, UInt<1>(0h0)) when _T_813 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_814 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_815 = asUInt(reset) node _T_816 = eq(_T_815, UInt<1>(0h0)) when _T_816 : node _T_817 = eq(_T_814, UInt<1>(0h0)) when _T_817 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_814, UInt<1>(0h1), "") : assert_49 node _T_818 = eq(io.in.a.bits.mask, mask) node _T_819 = asUInt(reset) node _T_820 = eq(_T_819, UInt<1>(0h0)) when _T_820 : node _T_821 = eq(_T_818, UInt<1>(0h0)) when _T_821 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_818, UInt<1>(0h1), "") : assert_50 node _T_822 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_823 = asUInt(reset) node _T_824 = eq(_T_823, UInt<1>(0h0)) when _T_824 : node _T_825 = eq(_T_822, UInt<1>(0h0)) when _T_825 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_822, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_826 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_827 = asUInt(reset) node _T_828 = eq(_T_827, UInt<1>(0h0)) when _T_828 : node _T_829 = eq(_T_826, UInt<1>(0h0)) when _T_829 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_826, UInt<1>(0h1), "") : assert_52 node _source_ok_T_36 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_37 = shr(io.in.d.bits.source, 2) node _source_ok_T_38 = eq(_source_ok_T_37, UInt<1>(0h0)) node _source_ok_T_39 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_T_41 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_43 = shr(io.in.d.bits.source, 2) node _source_ok_T_44 = eq(_source_ok_T_43, UInt<1>(0h1)) node _source_ok_T_45 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45) node _source_ok_T_47 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_49 = shr(io.in.d.bits.source, 2) node _source_ok_T_50 = eq(_source_ok_T_49, UInt<2>(0h2)) node _source_ok_T_51 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) node _source_ok_T_53 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_55 = shr(io.in.d.bits.source, 2) node _source_ok_T_56 = eq(_source_ok_T_55, UInt<2>(0h3)) node _source_ok_T_57 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57) node _source_ok_T_59 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_T_61 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_62 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_63 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_64 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[9] connect _source_ok_WIRE_1[0], _source_ok_T_36 connect _source_ok_WIRE_1[1], _source_ok_T_42 connect _source_ok_WIRE_1[2], _source_ok_T_48 connect _source_ok_WIRE_1[3], _source_ok_T_54 connect _source_ok_WIRE_1[4], _source_ok_T_60 connect _source_ok_WIRE_1[5], _source_ok_T_61 connect _source_ok_WIRE_1[6], _source_ok_T_62 connect _source_ok_WIRE_1[7], _source_ok_T_63 connect _source_ok_WIRE_1[8], _source_ok_T_64 node _source_ok_T_65 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE_1[2]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE_1[3]) node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE_1[4]) node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE_1[5]) node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE_1[6]) node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE_1[7]) node source_ok_1 = or(_source_ok_T_71, _source_ok_WIRE_1[8]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_830 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_830 : node _T_831 = asUInt(reset) node _T_832 = eq(_T_831, UInt<1>(0h0)) when _T_832 : node _T_833 = eq(source_ok_1, UInt<1>(0h0)) when _T_833 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_834 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(_T_834, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_834, UInt<1>(0h1), "") : assert_54 node _T_838 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_839 = asUInt(reset) node _T_840 = eq(_T_839, UInt<1>(0h0)) when _T_840 : node _T_841 = eq(_T_838, UInt<1>(0h0)) when _T_841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_838, UInt<1>(0h1), "") : assert_55 node _T_842 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_843 = asUInt(reset) node _T_844 = eq(_T_843, UInt<1>(0h0)) when _T_844 : node _T_845 = eq(_T_842, UInt<1>(0h0)) when _T_845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_842, UInt<1>(0h1), "") : assert_56 node _T_846 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_847 = asUInt(reset) node _T_848 = eq(_T_847, UInt<1>(0h0)) when _T_848 : node _T_849 = eq(_T_846, UInt<1>(0h0)) when _T_849 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_846, UInt<1>(0h1), "") : assert_57 node _T_850 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_850 : node _T_851 = asUInt(reset) node _T_852 = eq(_T_851, UInt<1>(0h0)) when _T_852 : node _T_853 = eq(source_ok_1, UInt<1>(0h0)) when _T_853 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_854 = asUInt(reset) node _T_855 = eq(_T_854, UInt<1>(0h0)) when _T_855 : node _T_856 = eq(sink_ok, UInt<1>(0h0)) when _T_856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_857 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_858 = asUInt(reset) node _T_859 = eq(_T_858, UInt<1>(0h0)) when _T_859 : node _T_860 = eq(_T_857, UInt<1>(0h0)) when _T_860 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_857, UInt<1>(0h1), "") : assert_60 node _T_861 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_862 = asUInt(reset) node _T_863 = eq(_T_862, UInt<1>(0h0)) when _T_863 : node _T_864 = eq(_T_861, UInt<1>(0h0)) when _T_864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_861, UInt<1>(0h1), "") : assert_61 node _T_865 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_866 = asUInt(reset) node _T_867 = eq(_T_866, UInt<1>(0h0)) when _T_867 : node _T_868 = eq(_T_865, UInt<1>(0h0)) when _T_868 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_865, UInt<1>(0h1), "") : assert_62 node _T_869 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_869, UInt<1>(0h1), "") : assert_63 node _T_873 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_874 = or(UInt<1>(0h0), _T_873) node _T_875 = asUInt(reset) node _T_876 = eq(_T_875, UInt<1>(0h0)) when _T_876 : node _T_877 = eq(_T_874, UInt<1>(0h0)) when _T_877 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_874, UInt<1>(0h1), "") : assert_64 node _T_878 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_878 : node _T_879 = asUInt(reset) node _T_880 = eq(_T_879, UInt<1>(0h0)) when _T_880 : node _T_881 = eq(source_ok_1, UInt<1>(0h0)) when _T_881 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_882 = asUInt(reset) node _T_883 = eq(_T_882, UInt<1>(0h0)) when _T_883 : node _T_884 = eq(sink_ok, UInt<1>(0h0)) when _T_884 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_885 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(_T_885, UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_885, UInt<1>(0h1), "") : assert_67 node _T_889 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_890 = asUInt(reset) node _T_891 = eq(_T_890, UInt<1>(0h0)) when _T_891 : node _T_892 = eq(_T_889, UInt<1>(0h0)) when _T_892 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_889, UInt<1>(0h1), "") : assert_68 node _T_893 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_894 = asUInt(reset) node _T_895 = eq(_T_894, UInt<1>(0h0)) when _T_895 : node _T_896 = eq(_T_893, UInt<1>(0h0)) when _T_896 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_893, UInt<1>(0h1), "") : assert_69 node _T_897 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_898 = or(_T_897, io.in.d.bits.corrupt) node _T_899 = asUInt(reset) node _T_900 = eq(_T_899, UInt<1>(0h0)) when _T_900 : node _T_901 = eq(_T_898, UInt<1>(0h0)) when _T_901 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_898, UInt<1>(0h1), "") : assert_70 node _T_902 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_903 = or(UInt<1>(0h0), _T_902) node _T_904 = asUInt(reset) node _T_905 = eq(_T_904, UInt<1>(0h0)) when _T_905 : node _T_906 = eq(_T_903, UInt<1>(0h0)) when _T_906 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_903, UInt<1>(0h1), "") : assert_71 node _T_907 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_907 : node _T_908 = asUInt(reset) node _T_909 = eq(_T_908, UInt<1>(0h0)) when _T_909 : node _T_910 = eq(source_ok_1, UInt<1>(0h0)) when _T_910 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_911 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_912 = asUInt(reset) node _T_913 = eq(_T_912, UInt<1>(0h0)) when _T_913 : node _T_914 = eq(_T_911, UInt<1>(0h0)) when _T_914 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_911, UInt<1>(0h1), "") : assert_73 node _T_915 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_916 = asUInt(reset) node _T_917 = eq(_T_916, UInt<1>(0h0)) when _T_917 : node _T_918 = eq(_T_915, UInt<1>(0h0)) when _T_918 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_915, UInt<1>(0h1), "") : assert_74 node _T_919 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_920 = or(UInt<1>(0h0), _T_919) node _T_921 = asUInt(reset) node _T_922 = eq(_T_921, UInt<1>(0h0)) when _T_922 : node _T_923 = eq(_T_920, UInt<1>(0h0)) when _T_923 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_920, UInt<1>(0h1), "") : assert_75 node _T_924 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_924 : node _T_925 = asUInt(reset) node _T_926 = eq(_T_925, UInt<1>(0h0)) when _T_926 : node _T_927 = eq(source_ok_1, UInt<1>(0h0)) when _T_927 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_928 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_929 = asUInt(reset) node _T_930 = eq(_T_929, UInt<1>(0h0)) when _T_930 : node _T_931 = eq(_T_928, UInt<1>(0h0)) when _T_931 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_928, UInt<1>(0h1), "") : assert_77 node _T_932 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_933 = or(_T_932, io.in.d.bits.corrupt) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_933, UInt<1>(0h1), "") : assert_78 node _T_937 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_938 = or(UInt<1>(0h0), _T_937) node _T_939 = asUInt(reset) node _T_940 = eq(_T_939, UInt<1>(0h0)) when _T_940 : node _T_941 = eq(_T_938, UInt<1>(0h0)) when _T_941 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_938, UInt<1>(0h1), "") : assert_79 node _T_942 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_942 : node _T_943 = asUInt(reset) node _T_944 = eq(_T_943, UInt<1>(0h0)) when _T_944 : node _T_945 = eq(source_ok_1, UInt<1>(0h0)) when _T_945 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_946 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_947 = asUInt(reset) node _T_948 = eq(_T_947, UInt<1>(0h0)) when _T_948 : node _T_949 = eq(_T_946, UInt<1>(0h0)) when _T_949 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_946, UInt<1>(0h1), "") : assert_81 node _T_950 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_951 = asUInt(reset) node _T_952 = eq(_T_951, UInt<1>(0h0)) when _T_952 : node _T_953 = eq(_T_950, UInt<1>(0h0)) when _T_953 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_950, UInt<1>(0h1), "") : assert_82 node _T_954 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_955 = or(UInt<1>(0h0), _T_954) node _T_956 = asUInt(reset) node _T_957 = eq(_T_956, UInt<1>(0h0)) when _T_957 : node _T_958 = eq(_T_955, UInt<1>(0h0)) when _T_958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_955, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<12>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_959 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_960 = asUInt(reset) node _T_961 = eq(_T_960, UInt<1>(0h0)) when _T_961 : node _T_962 = eq(_T_959, UInt<1>(0h0)) when _T_962 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_959, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<12>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_963 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_T_963, UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_963, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_967 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_968 = asUInt(reset) node _T_969 = eq(_T_968, UInt<1>(0h0)) when _T_969 : node _T_970 = eq(_T_967, UInt<1>(0h0)) when _T_970 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_967, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_971 = eq(a_first, UInt<1>(0h0)) node _T_972 = and(io.in.a.valid, _T_971) when _T_972 : node _T_973 = eq(io.in.a.bits.opcode, opcode) node _T_974 = asUInt(reset) node _T_975 = eq(_T_974, UInt<1>(0h0)) when _T_975 : node _T_976 = eq(_T_973, UInt<1>(0h0)) when _T_976 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_973, UInt<1>(0h1), "") : assert_87 node _T_977 = eq(io.in.a.bits.param, param) node _T_978 = asUInt(reset) node _T_979 = eq(_T_978, UInt<1>(0h0)) when _T_979 : node _T_980 = eq(_T_977, UInt<1>(0h0)) when _T_980 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_977, UInt<1>(0h1), "") : assert_88 node _T_981 = eq(io.in.a.bits.size, size) node _T_982 = asUInt(reset) node _T_983 = eq(_T_982, UInt<1>(0h0)) when _T_983 : node _T_984 = eq(_T_981, UInt<1>(0h0)) when _T_984 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_981, UInt<1>(0h1), "") : assert_89 node _T_985 = eq(io.in.a.bits.source, source) node _T_986 = asUInt(reset) node _T_987 = eq(_T_986, UInt<1>(0h0)) when _T_987 : node _T_988 = eq(_T_985, UInt<1>(0h0)) when _T_988 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_985, UInt<1>(0h1), "") : assert_90 node _T_989 = eq(io.in.a.bits.address, address) node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(_T_989, UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_989, UInt<1>(0h1), "") : assert_91 node _T_993 = and(io.in.a.ready, io.in.a.valid) node _T_994 = and(_T_993, a_first) when _T_994 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_995 = eq(d_first, UInt<1>(0h0)) node _T_996 = and(io.in.d.valid, _T_995) when _T_996 : node _T_997 = eq(io.in.d.bits.opcode, opcode_1) node _T_998 = asUInt(reset) node _T_999 = eq(_T_998, UInt<1>(0h0)) when _T_999 : node _T_1000 = eq(_T_997, UInt<1>(0h0)) when _T_1000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_997, UInt<1>(0h1), "") : assert_92 node _T_1001 = eq(io.in.d.bits.param, param_1) node _T_1002 = asUInt(reset) node _T_1003 = eq(_T_1002, UInt<1>(0h0)) when _T_1003 : node _T_1004 = eq(_T_1001, UInt<1>(0h0)) when _T_1004 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1001, UInt<1>(0h1), "") : assert_93 node _T_1005 = eq(io.in.d.bits.size, size_1) node _T_1006 = asUInt(reset) node _T_1007 = eq(_T_1006, UInt<1>(0h0)) when _T_1007 : node _T_1008 = eq(_T_1005, UInt<1>(0h0)) when _T_1008 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1005, UInt<1>(0h1), "") : assert_94 node _T_1009 = eq(io.in.d.bits.source, source_1) node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(_T_1009, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1009, UInt<1>(0h1), "") : assert_95 node _T_1013 = eq(io.in.d.bits.sink, sink) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_96 node _T_1017 = eq(io.in.d.bits.denied, denied) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_97 node _T_1021 = and(io.in.d.ready, io.in.d.valid) node _T_1022 = and(_T_1021, d_first) when _T_1022 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<260> connect a_sizes_set, UInt<260>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1023 = and(io.in.a.valid, a_first_1) node _T_1024 = and(_T_1023, UInt<1>(0h1)) when _T_1024 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1025 = and(io.in.a.ready, io.in.a.valid) node _T_1026 = and(_T_1025, a_first_1) node _T_1027 = and(_T_1026, UInt<1>(0h1)) when _T_1027 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1028 = dshr(inflight, io.in.a.bits.source) node _T_1029 = bits(_T_1028, 0, 0) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) node _T_1031 = asUInt(reset) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) when _T_1032 : node _T_1033 = eq(_T_1030, UInt<1>(0h0)) when _T_1033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1030, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<260> connect d_sizes_clr, UInt<260>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1034 = and(io.in.d.valid, d_first_1) node _T_1035 = and(_T_1034, UInt<1>(0h1)) node _T_1036 = eq(d_release_ack, UInt<1>(0h0)) node _T_1037 = and(_T_1035, _T_1036) when _T_1037 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1038 = and(io.in.d.ready, io.in.d.valid) node _T_1039 = and(_T_1038, d_first_1) node _T_1040 = and(_T_1039, UInt<1>(0h1)) node _T_1041 = eq(d_release_ack, UInt<1>(0h0)) node _T_1042 = and(_T_1040, _T_1041) when _T_1042 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1043 = and(io.in.d.valid, d_first_1) node _T_1044 = and(_T_1043, UInt<1>(0h1)) node _T_1045 = eq(d_release_ack, UInt<1>(0h0)) node _T_1046 = and(_T_1044, _T_1045) when _T_1046 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1047 = dshr(inflight, io.in.d.bits.source) node _T_1048 = bits(_T_1047, 0, 0) node _T_1049 = or(_T_1048, same_cycle_resp) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1053 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1054 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1055 = or(_T_1053, _T_1054) node _T_1056 = asUInt(reset) node _T_1057 = eq(_T_1056, UInt<1>(0h0)) when _T_1057 : node _T_1058 = eq(_T_1055, UInt<1>(0h0)) when _T_1058 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1055, UInt<1>(0h1), "") : assert_100 node _T_1059 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_101 else : node _T_1063 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1064 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1065 = or(_T_1063, _T_1064) node _T_1066 = asUInt(reset) node _T_1067 = eq(_T_1066, UInt<1>(0h0)) when _T_1067 : node _T_1068 = eq(_T_1065, UInt<1>(0h0)) when _T_1068 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1065, UInt<1>(0h1), "") : assert_102 node _T_1069 = eq(io.in.d.bits.size, a_size_lookup) node _T_1070 = asUInt(reset) node _T_1071 = eq(_T_1070, UInt<1>(0h0)) when _T_1071 : node _T_1072 = eq(_T_1069, UInt<1>(0h0)) when _T_1072 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1069, UInt<1>(0h1), "") : assert_103 node _T_1073 = and(io.in.d.valid, d_first_1) node _T_1074 = and(_T_1073, a_first_1) node _T_1075 = and(_T_1074, io.in.a.valid) node _T_1076 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1077 = and(_T_1075, _T_1076) node _T_1078 = eq(d_release_ack, UInt<1>(0h0)) node _T_1079 = and(_T_1077, _T_1078) when _T_1079 : node _T_1080 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1081 = or(_T_1080, io.in.a.ready) node _T_1082 = asUInt(reset) node _T_1083 = eq(_T_1082, UInt<1>(0h0)) when _T_1083 : node _T_1084 = eq(_T_1081, UInt<1>(0h0)) when _T_1084 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1081, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_50 node _T_1085 = orr(inflight) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) node _T_1087 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1088 = or(_T_1086, _T_1087) node _T_1089 = lt(watchdog, plusarg_reader.out) node _T_1090 = or(_T_1088, _T_1089) node _T_1091 = asUInt(reset) node _T_1092 = eq(_T_1091, UInt<1>(0h0)) when _T_1092 : node _T_1093 = eq(_T_1090, UInt<1>(0h0)) when _T_1093 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1090, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1094 = and(io.in.a.ready, io.in.a.valid) node _T_1095 = and(io.in.d.ready, io.in.d.valid) node _T_1096 = or(_T_1094, _T_1095) when _T_1096 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<12>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<12>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<260> connect c_sizes_set, UInt<260>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<12>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1097 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<12>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1098 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1099 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1100 = and(_T_1098, _T_1099) node _T_1101 = and(_T_1097, _T_1100) when _T_1101 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<12>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<12>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1102 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1103 = and(_T_1102, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<12>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1104 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1105 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1106 = and(_T_1104, _T_1105) node _T_1107 = and(_T_1103, _T_1106) when _T_1107 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<12>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<12>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<12>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<12>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<12>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<12>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1108 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1109 = bits(_T_1108, 0, 0) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(_T_1110, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1110, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<12>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<12>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<260> connect d_sizes_clr_1, UInt<260>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1114 = and(io.in.d.valid, d_first_2) node _T_1115 = and(_T_1114, UInt<1>(0h1)) node _T_1116 = and(_T_1115, d_release_ack_1) when _T_1116 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1117 = and(io.in.d.ready, io.in.d.valid) node _T_1118 = and(_T_1117, d_first_2) node _T_1119 = and(_T_1118, UInt<1>(0h1)) node _T_1120 = and(_T_1119, d_release_ack_1) when _T_1120 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1121 = and(io.in.d.valid, d_first_2) node _T_1122 = and(_T_1121, UInt<1>(0h1)) node _T_1123 = and(_T_1122, d_release_ack_1) when _T_1123 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1124 = dshr(inflight_1, io.in.d.bits.source) node _T_1125 = bits(_T_1124, 0, 0) node _T_1126 = or(_T_1125, same_cycle_resp_1) node _T_1127 = asUInt(reset) node _T_1128 = eq(_T_1127, UInt<1>(0h0)) when _T_1128 : node _T_1129 = eq(_T_1126, UInt<1>(0h0)) when _T_1129 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_1126, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<12>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1130 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1131 = asUInt(reset) node _T_1132 = eq(_T_1131, UInt<1>(0h0)) when _T_1132 : node _T_1133 = eq(_T_1130, UInt<1>(0h0)) when _T_1133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1130, UInt<1>(0h1), "") : assert_108 else : node _T_1134 = eq(io.in.d.bits.size, c_size_lookup) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_109 node _T_1138 = and(io.in.d.valid, d_first_2) node _T_1139 = and(_T_1138, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<12>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1140 = and(_T_1139, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<12>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1141 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1142 = and(_T_1140, _T_1141) node _T_1143 = and(_T_1142, d_release_ack_1) node _T_1144 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1145 = and(_T_1143, _T_1144) when _T_1145 : node _T_1146 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<12>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1147 = or(_T_1146, _WIRE_27.ready) node _T_1148 = asUInt(reset) node _T_1149 = eq(_T_1148, UInt<1>(0h0)) when _T_1149 : node _T_1150 = eq(_T_1147, UInt<1>(0h0)) when _T_1150 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1147, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_51 node _T_1151 = orr(inflight_1) node _T_1152 = eq(_T_1151, UInt<1>(0h0)) node _T_1153 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1154 = or(_T_1152, _T_1153) node _T_1155 = lt(watchdog_1, plusarg_reader_1.out) node _T_1156 = or(_T_1154, _T_1155) node _T_1157 = asUInt(reset) node _T_1158 = eq(_T_1157, UInt<1>(0h0)) when _T_1158 : node _T_1159 = eq(_T_1156, UInt<1>(0h0)) when _T_1159 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1156, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<12>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1160 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1161 = and(io.in.d.ready, io.in.d.valid) node _T_1162 = or(_T_1160, _T_1161) when _T_1162 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_25( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [11:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_wo_ready_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_wo_ready_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_4_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_5_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire _source_ok_T_29 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_30 = _source_ok_T_29 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_31 = _source_ok_T_30 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_32 = _source_ok_T_31 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_33 = _source_ok_T_32 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_34 = _source_ok_T_33 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_35 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [11:0] _is_aligned_T = {6'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 12'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_36 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_37 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_43 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_49 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_55 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_38 = _source_ok_T_37 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_44 = _source_ok_T_43 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_48; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_50 = _source_ok_T_49 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_54; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_56 = _source_ok_T_55 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire _source_ok_T_61 = io_in_d_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire _source_ok_T_62 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_62; // @[Parameters.scala:1138:31] wire _source_ok_T_63 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_63; // @[Parameters.scala:1138:31] wire _source_ok_T_64 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_64; // @[Parameters.scala:1138:31] wire _source_ok_T_65 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_66 = _source_ok_T_65 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_67 = _source_ok_T_66 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_68 = _source_ok_T_67 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_69 = _source_ok_T_68 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_70 = _source_ok_T_69 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_71 = _source_ok_T_70 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_71 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _T_1094 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1094; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1094; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [11:0] address; // @[Monitor.scala:391:22] wire _T_1162 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1162; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1162; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1162; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1027 = _T_1094 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1027 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1027 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1027 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1027 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1027 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1073 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1073 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1042 = _T_1162 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1042 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1042 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1042 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1138 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1138 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1120 = _T_1162 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1120 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1120 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1120 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_270 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_502 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0
module AsyncResetSynchronizerShiftReg_w1_d3_i0_270( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_502 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_266 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_10 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c
module PE_266( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_10 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_163 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_178 connect io_out_sink_valid.clock, clock connect io_out_sink_valid.reset, reset connect io_out_sink_valid.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid.io.q connect io.out, _io_out_WIRE
module AsyncValidSync_163( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_178 io_out_sink_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_39 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2)) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_lo = cat(mask_acc_1, mask_acc) node mask_hi = cat(mask_acc_3, mask_acc_2) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_17 = and(UInt<1>(0h0), _T_16) node _T_18 = or(UInt<1>(0h0), _T_17) node _T_19 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_20 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_21 = cvt(_T_20) node _T_22 = and(_T_21, asSInt(UInt<7>(0h40))) node _T_23 = asSInt(_T_22) node _T_24 = eq(_T_23, asSInt(UInt<1>(0h0))) node _T_25 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_26 = cvt(_T_25) node _T_27 = and(_T_26, asSInt(UInt<5>(0h14))) node _T_28 = asSInt(_T_27) node _T_29 = eq(_T_28, asSInt(UInt<1>(0h0))) node _T_30 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_31 = cvt(_T_30) node _T_32 = and(_T_31, asSInt(UInt<4>(0h8))) node _T_33 = asSInt(_T_32) node _T_34 = eq(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_36 = cvt(_T_35) node _T_37 = and(_T_36, asSInt(UInt<6>(0h20))) node _T_38 = asSInt(_T_37) node _T_39 = eq(_T_38, asSInt(UInt<1>(0h0))) node _T_40 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_41 = cvt(_T_40) node _T_42 = and(_T_41, asSInt(UInt<8>(0h80))) node _T_43 = asSInt(_T_42) node _T_44 = eq(_T_43, asSInt(UInt<1>(0h0))) node _T_45 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<9>(0h100))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_24, _T_29) node _T_51 = or(_T_50, _T_34) node _T_52 = or(_T_51, _T_39) node _T_53 = or(_T_52, _T_44) node _T_54 = or(_T_53, _T_49) node _T_55 = and(_T_19, _T_54) node _T_56 = or(UInt<1>(0h0), _T_55) node _T_57 = and(_T_18, _T_56) node _T_58 = asUInt(reset) node _T_59 = eq(_T_58, UInt<1>(0h0)) when _T_59 : node _T_60 = eq(_T_57, UInt<1>(0h0)) when _T_60 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_57, UInt<1>(0h1), "") : assert_2 node _T_61 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_62 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_63 = and(_T_61, _T_62) node _T_64 = or(UInt<1>(0h0), _T_63) node _T_65 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_66 = cvt(_T_65) node _T_67 = and(_T_66, asSInt(UInt<7>(0h40))) node _T_68 = asSInt(_T_67) node _T_69 = eq(_T_68, asSInt(UInt<1>(0h0))) node _T_70 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_71 = cvt(_T_70) node _T_72 = and(_T_71, asSInt(UInt<5>(0h14))) node _T_73 = asSInt(_T_72) node _T_74 = eq(_T_73, asSInt(UInt<1>(0h0))) node _T_75 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_76 = cvt(_T_75) node _T_77 = and(_T_76, asSInt(UInt<4>(0h8))) node _T_78 = asSInt(_T_77) node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0))) node _T_80 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_81 = cvt(_T_80) node _T_82 = and(_T_81, asSInt(UInt<6>(0h20))) node _T_83 = asSInt(_T_82) node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_86 = cvt(_T_85) node _T_87 = and(_T_86, asSInt(UInt<8>(0h80))) node _T_88 = asSInt(_T_87) node _T_89 = eq(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<9>(0h100))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_69, _T_74) node _T_96 = or(_T_95, _T_79) node _T_97 = or(_T_96, _T_84) node _T_98 = or(_T_97, _T_89) node _T_99 = or(_T_98, _T_94) node _T_100 = and(_T_64, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(UInt<1>(0h0), _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_102, UInt<1>(0h1), "") : assert_3 node _T_106 = asUInt(reset) node _T_107 = eq(_T_106, UInt<1>(0h0)) when _T_107 : node _T_108 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_108 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_109 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_110 = asUInt(reset) node _T_111 = eq(_T_110, UInt<1>(0h0)) when _T_111 : node _T_112 = eq(_T_109, UInt<1>(0h0)) when _T_112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_109, UInt<1>(0h1), "") : assert_5 node _T_113 = asUInt(reset) node _T_114 = eq(_T_113, UInt<1>(0h0)) when _T_114 : node _T_115 = eq(is_aligned, UInt<1>(0h0)) when _T_115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_116 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_117 = asUInt(reset) node _T_118 = eq(_T_117, UInt<1>(0h0)) when _T_118 : node _T_119 = eq(_T_116, UInt<1>(0h0)) when _T_119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_116, UInt<1>(0h1), "") : assert_7 node _T_120 = not(io.in.a.bits.mask) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(_T_121, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_121, UInt<1>(0h1), "") : assert_8 node _T_125 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_126 = asUInt(reset) node _T_127 = eq(_T_126, UInt<1>(0h0)) when _T_127 : node _T_128 = eq(_T_125, UInt<1>(0h0)) when _T_128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_125, UInt<1>(0h1), "") : assert_9 node _T_129 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_129 : node _T_130 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_131 = and(UInt<1>(0h0), _T_130) node _T_132 = or(UInt<1>(0h0), _T_131) node _T_133 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_134 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_135 = cvt(_T_134) node _T_136 = and(_T_135, asSInt(UInt<7>(0h40))) node _T_137 = asSInt(_T_136) node _T_138 = eq(_T_137, asSInt(UInt<1>(0h0))) node _T_139 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_140 = cvt(_T_139) node _T_141 = and(_T_140, asSInt(UInt<5>(0h14))) node _T_142 = asSInt(_T_141) node _T_143 = eq(_T_142, asSInt(UInt<1>(0h0))) node _T_144 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_145 = cvt(_T_144) node _T_146 = and(_T_145, asSInt(UInt<4>(0h8))) node _T_147 = asSInt(_T_146) node _T_148 = eq(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_150 = cvt(_T_149) node _T_151 = and(_T_150, asSInt(UInt<6>(0h20))) node _T_152 = asSInt(_T_151) node _T_153 = eq(_T_152, asSInt(UInt<1>(0h0))) node _T_154 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_155 = cvt(_T_154) node _T_156 = and(_T_155, asSInt(UInt<8>(0h80))) node _T_157 = asSInt(_T_156) node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_160 = cvt(_T_159) node _T_161 = and(_T_160, asSInt(UInt<9>(0h100))) node _T_162 = asSInt(_T_161) node _T_163 = eq(_T_162, asSInt(UInt<1>(0h0))) node _T_164 = or(_T_138, _T_143) node _T_165 = or(_T_164, _T_148) node _T_166 = or(_T_165, _T_153) node _T_167 = or(_T_166, _T_158) node _T_168 = or(_T_167, _T_163) node _T_169 = and(_T_133, _T_168) node _T_170 = or(UInt<1>(0h0), _T_169) node _T_171 = and(_T_132, _T_170) node _T_172 = asUInt(reset) node _T_173 = eq(_T_172, UInt<1>(0h0)) when _T_173 : node _T_174 = eq(_T_171, UInt<1>(0h0)) when _T_174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_171, UInt<1>(0h1), "") : assert_10 node _T_175 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_176 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_177 = and(_T_175, _T_176) node _T_178 = or(UInt<1>(0h0), _T_177) node _T_179 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_180 = cvt(_T_179) node _T_181 = and(_T_180, asSInt(UInt<7>(0h40))) node _T_182 = asSInt(_T_181) node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0))) node _T_184 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_185 = cvt(_T_184) node _T_186 = and(_T_185, asSInt(UInt<5>(0h14))) node _T_187 = asSInt(_T_186) node _T_188 = eq(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_190 = cvt(_T_189) node _T_191 = and(_T_190, asSInt(UInt<4>(0h8))) node _T_192 = asSInt(_T_191) node _T_193 = eq(_T_192, asSInt(UInt<1>(0h0))) node _T_194 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<6>(0h20))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_200 = cvt(_T_199) node _T_201 = and(_T_200, asSInt(UInt<8>(0h80))) node _T_202 = asSInt(_T_201) node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0))) node _T_204 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_205 = cvt(_T_204) node _T_206 = and(_T_205, asSInt(UInt<9>(0h100))) node _T_207 = asSInt(_T_206) node _T_208 = eq(_T_207, asSInt(UInt<1>(0h0))) node _T_209 = or(_T_183, _T_188) node _T_210 = or(_T_209, _T_193) node _T_211 = or(_T_210, _T_198) node _T_212 = or(_T_211, _T_203) node _T_213 = or(_T_212, _T_208) node _T_214 = and(_T_178, _T_213) node _T_215 = or(UInt<1>(0h0), _T_214) node _T_216 = and(UInt<1>(0h0), _T_215) node _T_217 = asUInt(reset) node _T_218 = eq(_T_217, UInt<1>(0h0)) when _T_218 : node _T_219 = eq(_T_216, UInt<1>(0h0)) when _T_219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_216, UInt<1>(0h1), "") : assert_11 node _T_220 = asUInt(reset) node _T_221 = eq(_T_220, UInt<1>(0h0)) when _T_221 : node _T_222 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_223 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_224 = asUInt(reset) node _T_225 = eq(_T_224, UInt<1>(0h0)) when _T_225 : node _T_226 = eq(_T_223, UInt<1>(0h0)) when _T_226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_223, UInt<1>(0h1), "") : assert_13 node _T_227 = asUInt(reset) node _T_228 = eq(_T_227, UInt<1>(0h0)) when _T_228 : node _T_229 = eq(is_aligned, UInt<1>(0h0)) when _T_229 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_230 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_231 = asUInt(reset) node _T_232 = eq(_T_231, UInt<1>(0h0)) when _T_232 : node _T_233 = eq(_T_230, UInt<1>(0h0)) when _T_233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_230, UInt<1>(0h1), "") : assert_15 node _T_234 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_235 = asUInt(reset) node _T_236 = eq(_T_235, UInt<1>(0h0)) when _T_236 : node _T_237 = eq(_T_234, UInt<1>(0h0)) when _T_237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_234, UInt<1>(0h1), "") : assert_16 node _T_238 = not(io.in.a.bits.mask) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_239, UInt<1>(0h1), "") : assert_17 node _T_243 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_244 = asUInt(reset) node _T_245 = eq(_T_244, UInt<1>(0h0)) when _T_245 : node _T_246 = eq(_T_243, UInt<1>(0h0)) when _T_246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_243, UInt<1>(0h1), "") : assert_18 node _T_247 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_247 : node _T_248 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_249 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = asUInt(reset) node _T_253 = eq(_T_252, UInt<1>(0h0)) when _T_253 : node _T_254 = eq(_T_251, UInt<1>(0h0)) when _T_254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_251, UInt<1>(0h1), "") : assert_19 node _T_255 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_256 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_257 = and(_T_255, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_260 = cvt(_T_259) node _T_261 = and(_T_260, asSInt(UInt<7>(0h40))) node _T_262 = asSInt(_T_261) node _T_263 = eq(_T_262, asSInt(UInt<1>(0h0))) node _T_264 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_265 = cvt(_T_264) node _T_266 = and(_T_265, asSInt(UInt<5>(0h14))) node _T_267 = asSInt(_T_266) node _T_268 = eq(_T_267, asSInt(UInt<1>(0h0))) node _T_269 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_270 = cvt(_T_269) node _T_271 = and(_T_270, asSInt(UInt<4>(0h8))) node _T_272 = asSInt(_T_271) node _T_273 = eq(_T_272, asSInt(UInt<1>(0h0))) node _T_274 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_275 = cvt(_T_274) node _T_276 = and(_T_275, asSInt(UInt<6>(0h20))) node _T_277 = asSInt(_T_276) node _T_278 = eq(_T_277, asSInt(UInt<1>(0h0))) node _T_279 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_280 = cvt(_T_279) node _T_281 = and(_T_280, asSInt(UInt<8>(0h80))) node _T_282 = asSInt(_T_281) node _T_283 = eq(_T_282, asSInt(UInt<1>(0h0))) node _T_284 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_285 = cvt(_T_284) node _T_286 = and(_T_285, asSInt(UInt<9>(0h100))) node _T_287 = asSInt(_T_286) node _T_288 = eq(_T_287, asSInt(UInt<1>(0h0))) node _T_289 = or(_T_263, _T_268) node _T_290 = or(_T_289, _T_273) node _T_291 = or(_T_290, _T_278) node _T_292 = or(_T_291, _T_283) node _T_293 = or(_T_292, _T_288) node _T_294 = and(_T_258, _T_293) node _T_295 = or(UInt<1>(0h0), _T_294) node _T_296 = asUInt(reset) node _T_297 = eq(_T_296, UInt<1>(0h0)) when _T_297 : node _T_298 = eq(_T_295, UInt<1>(0h0)) when _T_298 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_295, UInt<1>(0h1), "") : assert_20 node _T_299 = asUInt(reset) node _T_300 = eq(_T_299, UInt<1>(0h0)) when _T_300 : node _T_301 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(is_aligned, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_305 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(_T_305, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_305, UInt<1>(0h1), "") : assert_23 node _T_309 = eq(io.in.a.bits.mask, mask) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_309, UInt<1>(0h1), "") : assert_24 node _T_313 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_313, UInt<1>(0h1), "") : assert_25 node _T_317 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_319 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_320 = and(_T_318, _T_319) node _T_321 = or(UInt<1>(0h0), _T_320) node _T_322 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_323 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_324 = and(_T_322, _T_323) node _T_325 = or(UInt<1>(0h0), _T_324) node _T_326 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_327 = cvt(_T_326) node _T_328 = and(_T_327, asSInt(UInt<7>(0h40))) node _T_329 = asSInt(_T_328) node _T_330 = eq(_T_329, asSInt(UInt<1>(0h0))) node _T_331 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_332 = cvt(_T_331) node _T_333 = and(_T_332, asSInt(UInt<5>(0h14))) node _T_334 = asSInt(_T_333) node _T_335 = eq(_T_334, asSInt(UInt<1>(0h0))) node _T_336 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_337 = cvt(_T_336) node _T_338 = and(_T_337, asSInt(UInt<4>(0h8))) node _T_339 = asSInt(_T_338) node _T_340 = eq(_T_339, asSInt(UInt<1>(0h0))) node _T_341 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_342 = cvt(_T_341) node _T_343 = and(_T_342, asSInt(UInt<6>(0h20))) node _T_344 = asSInt(_T_343) node _T_345 = eq(_T_344, asSInt(UInt<1>(0h0))) node _T_346 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_347 = cvt(_T_346) node _T_348 = and(_T_347, asSInt(UInt<8>(0h80))) node _T_349 = asSInt(_T_348) node _T_350 = eq(_T_349, asSInt(UInt<1>(0h0))) node _T_351 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_352 = cvt(_T_351) node _T_353 = and(_T_352, asSInt(UInt<9>(0h100))) node _T_354 = asSInt(_T_353) node _T_355 = eq(_T_354, asSInt(UInt<1>(0h0))) node _T_356 = or(_T_330, _T_335) node _T_357 = or(_T_356, _T_340) node _T_358 = or(_T_357, _T_345) node _T_359 = or(_T_358, _T_350) node _T_360 = or(_T_359, _T_355) node _T_361 = and(_T_325, _T_360) node _T_362 = or(UInt<1>(0h0), _T_361) node _T_363 = and(_T_321, _T_362) node _T_364 = asUInt(reset) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : node _T_366 = eq(_T_363, UInt<1>(0h0)) when _T_366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_363, UInt<1>(0h1), "") : assert_26 node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_370 = asUInt(reset) node _T_371 = eq(_T_370, UInt<1>(0h0)) when _T_371 : node _T_372 = eq(is_aligned, UInt<1>(0h0)) when _T_372 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_373 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_373, UInt<1>(0h1), "") : assert_29 node _T_377 = eq(io.in.a.bits.mask, mask) node _T_378 = asUInt(reset) node _T_379 = eq(_T_378, UInt<1>(0h0)) when _T_379 : node _T_380 = eq(_T_377, UInt<1>(0h0)) when _T_380 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_377, UInt<1>(0h1), "") : assert_30 node _T_381 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_381 : node _T_382 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_383 = and(UInt<1>(0h0), _T_382) node _T_384 = or(UInt<1>(0h0), _T_383) node _T_385 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_386 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_387 = and(_T_385, _T_386) node _T_388 = or(UInt<1>(0h0), _T_387) node _T_389 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<7>(0h40))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_395 = cvt(_T_394) node _T_396 = and(_T_395, asSInt(UInt<5>(0h14))) node _T_397 = asSInt(_T_396) node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0))) node _T_399 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<4>(0h8))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<6>(0h20))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<8>(0h80))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<9>(0h100))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = or(_T_393, _T_398) node _T_420 = or(_T_419, _T_403) node _T_421 = or(_T_420, _T_408) node _T_422 = or(_T_421, _T_413) node _T_423 = or(_T_422, _T_418) node _T_424 = and(_T_388, _T_423) node _T_425 = or(UInt<1>(0h0), _T_424) node _T_426 = and(_T_384, _T_425) node _T_427 = asUInt(reset) node _T_428 = eq(_T_427, UInt<1>(0h0)) when _T_428 : node _T_429 = eq(_T_426, UInt<1>(0h0)) when _T_429 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_426, UInt<1>(0h1), "") : assert_31 node _T_430 = asUInt(reset) node _T_431 = eq(_T_430, UInt<1>(0h0)) when _T_431 : node _T_432 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(is_aligned, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_436 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_436, UInt<1>(0h1), "") : assert_34 node _T_440 = not(mask) node _T_441 = and(io.in.a.bits.mask, _T_440) node _T_442 = eq(_T_441, UInt<1>(0h0)) node _T_443 = asUInt(reset) node _T_444 = eq(_T_443, UInt<1>(0h0)) when _T_444 : node _T_445 = eq(_T_442, UInt<1>(0h0)) when _T_445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_442, UInt<1>(0h1), "") : assert_35 node _T_446 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_446 : node _T_447 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_448 = and(UInt<1>(0h0), _T_447) node _T_449 = or(UInt<1>(0h0), _T_448) node _T_450 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_451 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_452 = cvt(_T_451) node _T_453 = and(_T_452, asSInt(UInt<7>(0h40))) node _T_454 = asSInt(_T_453) node _T_455 = eq(_T_454, asSInt(UInt<1>(0h0))) node _T_456 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_457 = cvt(_T_456) node _T_458 = and(_T_457, asSInt(UInt<5>(0h14))) node _T_459 = asSInt(_T_458) node _T_460 = eq(_T_459, asSInt(UInt<1>(0h0))) node _T_461 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_462 = cvt(_T_461) node _T_463 = and(_T_462, asSInt(UInt<4>(0h8))) node _T_464 = asSInt(_T_463) node _T_465 = eq(_T_464, asSInt(UInt<1>(0h0))) node _T_466 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_467 = cvt(_T_466) node _T_468 = and(_T_467, asSInt(UInt<6>(0h20))) node _T_469 = asSInt(_T_468) node _T_470 = eq(_T_469, asSInt(UInt<1>(0h0))) node _T_471 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_472 = cvt(_T_471) node _T_473 = and(_T_472, asSInt(UInt<8>(0h80))) node _T_474 = asSInt(_T_473) node _T_475 = eq(_T_474, asSInt(UInt<1>(0h0))) node _T_476 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_477 = cvt(_T_476) node _T_478 = and(_T_477, asSInt(UInt<9>(0h100))) node _T_479 = asSInt(_T_478) node _T_480 = eq(_T_479, asSInt(UInt<1>(0h0))) node _T_481 = or(_T_455, _T_460) node _T_482 = or(_T_481, _T_465) node _T_483 = or(_T_482, _T_470) node _T_484 = or(_T_483, _T_475) node _T_485 = or(_T_484, _T_480) node _T_486 = and(_T_450, _T_485) node _T_487 = or(UInt<1>(0h0), _T_486) node _T_488 = and(_T_449, _T_487) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_488, UInt<1>(0h1), "") : assert_36 node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_495 = asUInt(reset) node _T_496 = eq(_T_495, UInt<1>(0h0)) when _T_496 : node _T_497 = eq(is_aligned, UInt<1>(0h0)) when _T_497 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_498 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_499 = asUInt(reset) node _T_500 = eq(_T_499, UInt<1>(0h0)) when _T_500 : node _T_501 = eq(_T_498, UInt<1>(0h0)) when _T_501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_498, UInt<1>(0h1), "") : assert_39 node _T_502 = eq(io.in.a.bits.mask, mask) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_502, UInt<1>(0h1), "") : assert_40 node _T_506 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_506 : node _T_507 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_508 = and(UInt<1>(0h0), _T_507) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_511 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_512 = cvt(_T_511) node _T_513 = and(_T_512, asSInt(UInt<7>(0h40))) node _T_514 = asSInt(_T_513) node _T_515 = eq(_T_514, asSInt(UInt<1>(0h0))) node _T_516 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_517 = cvt(_T_516) node _T_518 = and(_T_517, asSInt(UInt<5>(0h14))) node _T_519 = asSInt(_T_518) node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0))) node _T_521 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_522 = cvt(_T_521) node _T_523 = and(_T_522, asSInt(UInt<4>(0h8))) node _T_524 = asSInt(_T_523) node _T_525 = eq(_T_524, asSInt(UInt<1>(0h0))) node _T_526 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_527 = cvt(_T_526) node _T_528 = and(_T_527, asSInt(UInt<6>(0h20))) node _T_529 = asSInt(_T_528) node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0))) node _T_531 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_532 = cvt(_T_531) node _T_533 = and(_T_532, asSInt(UInt<8>(0h80))) node _T_534 = asSInt(_T_533) node _T_535 = eq(_T_534, asSInt(UInt<1>(0h0))) node _T_536 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_537 = cvt(_T_536) node _T_538 = and(_T_537, asSInt(UInt<9>(0h100))) node _T_539 = asSInt(_T_538) node _T_540 = eq(_T_539, asSInt(UInt<1>(0h0))) node _T_541 = or(_T_515, _T_520) node _T_542 = or(_T_541, _T_525) node _T_543 = or(_T_542, _T_530) node _T_544 = or(_T_543, _T_535) node _T_545 = or(_T_544, _T_540) node _T_546 = and(_T_510, _T_545) node _T_547 = or(UInt<1>(0h0), _T_546) node _T_548 = and(_T_509, _T_547) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_548, UInt<1>(0h1), "") : assert_41 node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_555 = asUInt(reset) node _T_556 = eq(_T_555, UInt<1>(0h0)) when _T_556 : node _T_557 = eq(is_aligned, UInt<1>(0h0)) when _T_557 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_558 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_559 = asUInt(reset) node _T_560 = eq(_T_559, UInt<1>(0h0)) when _T_560 : node _T_561 = eq(_T_558, UInt<1>(0h0)) when _T_561 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_558, UInt<1>(0h1), "") : assert_44 node _T_562 = eq(io.in.a.bits.mask, mask) node _T_563 = asUInt(reset) node _T_564 = eq(_T_563, UInt<1>(0h0)) when _T_564 : node _T_565 = eq(_T_562, UInt<1>(0h0)) when _T_565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_562, UInt<1>(0h1), "") : assert_45 node _T_566 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_566 : node _T_567 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_568 = and(UInt<1>(0h0), _T_567) node _T_569 = or(UInt<1>(0h0), _T_568) node _T_570 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_571 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_572 = cvt(_T_571) node _T_573 = and(_T_572, asSInt(UInt<7>(0h40))) node _T_574 = asSInt(_T_573) node _T_575 = eq(_T_574, asSInt(UInt<1>(0h0))) node _T_576 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_577 = cvt(_T_576) node _T_578 = and(_T_577, asSInt(UInt<5>(0h14))) node _T_579 = asSInt(_T_578) node _T_580 = eq(_T_579, asSInt(UInt<1>(0h0))) node _T_581 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_582 = cvt(_T_581) node _T_583 = and(_T_582, asSInt(UInt<4>(0h8))) node _T_584 = asSInt(_T_583) node _T_585 = eq(_T_584, asSInt(UInt<1>(0h0))) node _T_586 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_587 = cvt(_T_586) node _T_588 = and(_T_587, asSInt(UInt<6>(0h20))) node _T_589 = asSInt(_T_588) node _T_590 = eq(_T_589, asSInt(UInt<1>(0h0))) node _T_591 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_592 = cvt(_T_591) node _T_593 = and(_T_592, asSInt(UInt<8>(0h80))) node _T_594 = asSInt(_T_593) node _T_595 = eq(_T_594, asSInt(UInt<1>(0h0))) node _T_596 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_597 = cvt(_T_596) node _T_598 = and(_T_597, asSInt(UInt<9>(0h100))) node _T_599 = asSInt(_T_598) node _T_600 = eq(_T_599, asSInt(UInt<1>(0h0))) node _T_601 = or(_T_575, _T_580) node _T_602 = or(_T_601, _T_585) node _T_603 = or(_T_602, _T_590) node _T_604 = or(_T_603, _T_595) node _T_605 = or(_T_604, _T_600) node _T_606 = and(_T_570, _T_605) node _T_607 = or(UInt<1>(0h0), _T_606) node _T_608 = and(_T_569, _T_607) node _T_609 = asUInt(reset) node _T_610 = eq(_T_609, UInt<1>(0h0)) when _T_610 : node _T_611 = eq(_T_608, UInt<1>(0h0)) when _T_611 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_608, UInt<1>(0h1), "") : assert_46 node _T_612 = asUInt(reset) node _T_613 = eq(_T_612, UInt<1>(0h0)) when _T_613 : node _T_614 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_614 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_615 = asUInt(reset) node _T_616 = eq(_T_615, UInt<1>(0h0)) when _T_616 : node _T_617 = eq(is_aligned, UInt<1>(0h0)) when _T_617 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_618 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_619 = asUInt(reset) node _T_620 = eq(_T_619, UInt<1>(0h0)) when _T_620 : node _T_621 = eq(_T_618, UInt<1>(0h0)) when _T_621 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_618, UInt<1>(0h1), "") : assert_49 node _T_622 = eq(io.in.a.bits.mask, mask) node _T_623 = asUInt(reset) node _T_624 = eq(_T_623, UInt<1>(0h0)) when _T_624 : node _T_625 = eq(_T_622, UInt<1>(0h0)) when _T_625 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_622, UInt<1>(0h1), "") : assert_50 node _T_626 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_626, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_630 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_630, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_634 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_634 : node _T_635 = asUInt(reset) node _T_636 = eq(_T_635, UInt<1>(0h0)) when _T_636 : node _T_637 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_637 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_638 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(_T_638, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_638, UInt<1>(0h1), "") : assert_54 node _T_642 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(_T_642, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_642, UInt<1>(0h1), "") : assert_55 node _T_646 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_647 = asUInt(reset) node _T_648 = eq(_T_647, UInt<1>(0h0)) when _T_648 : node _T_649 = eq(_T_646, UInt<1>(0h0)) when _T_649 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_646, UInt<1>(0h1), "") : assert_56 node _T_650 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_651 = asUInt(reset) node _T_652 = eq(_T_651, UInt<1>(0h0)) when _T_652 : node _T_653 = eq(_T_650, UInt<1>(0h0)) when _T_653 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_650, UInt<1>(0h1), "") : assert_57 node _T_654 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_654 : node _T_655 = asUInt(reset) node _T_656 = eq(_T_655, UInt<1>(0h0)) when _T_656 : node _T_657 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_657 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_658 = asUInt(reset) node _T_659 = eq(_T_658, UInt<1>(0h0)) when _T_659 : node _T_660 = eq(sink_ok, UInt<1>(0h0)) when _T_660 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_661 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_661, UInt<1>(0h1), "") : assert_60 node _T_665 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_666 = asUInt(reset) node _T_667 = eq(_T_666, UInt<1>(0h0)) when _T_667 : node _T_668 = eq(_T_665, UInt<1>(0h0)) when _T_668 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_665, UInt<1>(0h1), "") : assert_61 node _T_669 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(_T_669, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_669, UInt<1>(0h1), "") : assert_62 node _T_673 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_674 = asUInt(reset) node _T_675 = eq(_T_674, UInt<1>(0h0)) when _T_675 : node _T_676 = eq(_T_673, UInt<1>(0h0)) when _T_676 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_673, UInt<1>(0h1), "") : assert_63 node _T_677 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_678 = or(UInt<1>(0h0), _T_677) node _T_679 = asUInt(reset) node _T_680 = eq(_T_679, UInt<1>(0h0)) when _T_680 : node _T_681 = eq(_T_678, UInt<1>(0h0)) when _T_681 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_678, UInt<1>(0h1), "") : assert_64 node _T_682 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_682 : node _T_683 = asUInt(reset) node _T_684 = eq(_T_683, UInt<1>(0h0)) when _T_684 : node _T_685 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_685 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_686 = asUInt(reset) node _T_687 = eq(_T_686, UInt<1>(0h0)) when _T_687 : node _T_688 = eq(sink_ok, UInt<1>(0h0)) when _T_688 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_689 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_690 = asUInt(reset) node _T_691 = eq(_T_690, UInt<1>(0h0)) when _T_691 : node _T_692 = eq(_T_689, UInt<1>(0h0)) when _T_692 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_689, UInt<1>(0h1), "") : assert_67 node _T_693 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_694 = asUInt(reset) node _T_695 = eq(_T_694, UInt<1>(0h0)) when _T_695 : node _T_696 = eq(_T_693, UInt<1>(0h0)) when _T_696 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_693, UInt<1>(0h1), "") : assert_68 node _T_697 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_697, UInt<1>(0h1), "") : assert_69 node _T_701 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_702 = or(_T_701, io.in.d.bits.corrupt) node _T_703 = asUInt(reset) node _T_704 = eq(_T_703, UInt<1>(0h0)) when _T_704 : node _T_705 = eq(_T_702, UInt<1>(0h0)) when _T_705 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_702, UInt<1>(0h1), "") : assert_70 node _T_706 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_707 = or(UInt<1>(0h0), _T_706) node _T_708 = asUInt(reset) node _T_709 = eq(_T_708, UInt<1>(0h0)) when _T_709 : node _T_710 = eq(_T_707, UInt<1>(0h0)) when _T_710 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_707, UInt<1>(0h1), "") : assert_71 node _T_711 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_711 : node _T_712 = asUInt(reset) node _T_713 = eq(_T_712, UInt<1>(0h0)) when _T_713 : node _T_714 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_714 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_715 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_716 = asUInt(reset) node _T_717 = eq(_T_716, UInt<1>(0h0)) when _T_717 : node _T_718 = eq(_T_715, UInt<1>(0h0)) when _T_718 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_715, UInt<1>(0h1), "") : assert_73 node _T_719 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_720 = asUInt(reset) node _T_721 = eq(_T_720, UInt<1>(0h0)) when _T_721 : node _T_722 = eq(_T_719, UInt<1>(0h0)) when _T_722 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_719, UInt<1>(0h1), "") : assert_74 node _T_723 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_724 = or(UInt<1>(0h0), _T_723) node _T_725 = asUInt(reset) node _T_726 = eq(_T_725, UInt<1>(0h0)) when _T_726 : node _T_727 = eq(_T_724, UInt<1>(0h0)) when _T_727 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_724, UInt<1>(0h1), "") : assert_75 node _T_728 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_728 : node _T_729 = asUInt(reset) node _T_730 = eq(_T_729, UInt<1>(0h0)) when _T_730 : node _T_731 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_731 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_732 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_733 = asUInt(reset) node _T_734 = eq(_T_733, UInt<1>(0h0)) when _T_734 : node _T_735 = eq(_T_732, UInt<1>(0h0)) when _T_735 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_732, UInt<1>(0h1), "") : assert_77 node _T_736 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_737 = or(_T_736, io.in.d.bits.corrupt) node _T_738 = asUInt(reset) node _T_739 = eq(_T_738, UInt<1>(0h0)) when _T_739 : node _T_740 = eq(_T_737, UInt<1>(0h0)) when _T_740 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_737, UInt<1>(0h1), "") : assert_78 node _T_741 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_742 = or(UInt<1>(0h0), _T_741) node _T_743 = asUInt(reset) node _T_744 = eq(_T_743, UInt<1>(0h0)) when _T_744 : node _T_745 = eq(_T_742, UInt<1>(0h0)) when _T_745 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_742, UInt<1>(0h1), "") : assert_79 node _T_746 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_746 : node _T_747 = asUInt(reset) node _T_748 = eq(_T_747, UInt<1>(0h0)) when _T_748 : node _T_749 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_749 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_750 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_751 = asUInt(reset) node _T_752 = eq(_T_751, UInt<1>(0h0)) when _T_752 : node _T_753 = eq(_T_750, UInt<1>(0h0)) when _T_753 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_750, UInt<1>(0h1), "") : assert_81 node _T_754 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_755 = asUInt(reset) node _T_756 = eq(_T_755, UInt<1>(0h0)) when _T_756 : node _T_757 = eq(_T_754, UInt<1>(0h0)) when _T_757 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_754, UInt<1>(0h1), "") : assert_82 node _T_758 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_759 = or(UInt<1>(0h0), _T_758) node _T_760 = asUInt(reset) node _T_761 = eq(_T_760, UInt<1>(0h0)) when _T_761 : node _T_762 = eq(_T_759, UInt<1>(0h0)) when _T_762 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_759, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<9>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_763 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_764 = asUInt(reset) node _T_765 = eq(_T_764, UInt<1>(0h0)) when _T_765 : node _T_766 = eq(_T_763, UInt<1>(0h0)) when _T_766 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_763, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<9>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_767 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_768 = asUInt(reset) node _T_769 = eq(_T_768, UInt<1>(0h0)) when _T_769 : node _T_770 = eq(_T_767, UInt<1>(0h0)) when _T_770 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_767, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_771 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_772 = asUInt(reset) node _T_773 = eq(_T_772, UInt<1>(0h0)) when _T_773 : node _T_774 = eq(_T_771, UInt<1>(0h0)) when _T_774 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_771, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_775 = eq(a_first, UInt<1>(0h0)) node _T_776 = and(io.in.a.valid, _T_775) when _T_776 : node _T_777 = eq(io.in.a.bits.opcode, opcode) node _T_778 = asUInt(reset) node _T_779 = eq(_T_778, UInt<1>(0h0)) when _T_779 : node _T_780 = eq(_T_777, UInt<1>(0h0)) when _T_780 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_777, UInt<1>(0h1), "") : assert_87 node _T_781 = eq(io.in.a.bits.param, param) node _T_782 = asUInt(reset) node _T_783 = eq(_T_782, UInt<1>(0h0)) when _T_783 : node _T_784 = eq(_T_781, UInt<1>(0h0)) when _T_784 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_781, UInt<1>(0h1), "") : assert_88 node _T_785 = eq(io.in.a.bits.size, size) node _T_786 = asUInt(reset) node _T_787 = eq(_T_786, UInt<1>(0h0)) when _T_787 : node _T_788 = eq(_T_785, UInt<1>(0h0)) when _T_788 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_785, UInt<1>(0h1), "") : assert_89 node _T_789 = eq(io.in.a.bits.source, source) node _T_790 = asUInt(reset) node _T_791 = eq(_T_790, UInt<1>(0h0)) when _T_791 : node _T_792 = eq(_T_789, UInt<1>(0h0)) when _T_792 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_789, UInt<1>(0h1), "") : assert_90 node _T_793 = eq(io.in.a.bits.address, address) node _T_794 = asUInt(reset) node _T_795 = eq(_T_794, UInt<1>(0h0)) when _T_795 : node _T_796 = eq(_T_793, UInt<1>(0h0)) when _T_796 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_793, UInt<1>(0h1), "") : assert_91 node _T_797 = and(io.in.a.ready, io.in.a.valid) node _T_798 = and(_T_797, a_first) when _T_798 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_799 = eq(d_first, UInt<1>(0h0)) node _T_800 = and(io.in.d.valid, _T_799) when _T_800 : node _T_801 = eq(io.in.d.bits.opcode, opcode_1) node _T_802 = asUInt(reset) node _T_803 = eq(_T_802, UInt<1>(0h0)) when _T_803 : node _T_804 = eq(_T_801, UInt<1>(0h0)) when _T_804 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_801, UInt<1>(0h1), "") : assert_92 node _T_805 = eq(io.in.d.bits.param, param_1) node _T_806 = asUInt(reset) node _T_807 = eq(_T_806, UInt<1>(0h0)) when _T_807 : node _T_808 = eq(_T_805, UInt<1>(0h0)) when _T_808 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_805, UInt<1>(0h1), "") : assert_93 node _T_809 = eq(io.in.d.bits.size, size_1) node _T_810 = asUInt(reset) node _T_811 = eq(_T_810, UInt<1>(0h0)) when _T_811 : node _T_812 = eq(_T_809, UInt<1>(0h0)) when _T_812 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_809, UInt<1>(0h1), "") : assert_94 node _T_813 = eq(io.in.d.bits.source, source_1) node _T_814 = asUInt(reset) node _T_815 = eq(_T_814, UInt<1>(0h0)) when _T_815 : node _T_816 = eq(_T_813, UInt<1>(0h0)) when _T_816 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_813, UInt<1>(0h1), "") : assert_95 node _T_817 = eq(io.in.d.bits.sink, sink) node _T_818 = asUInt(reset) node _T_819 = eq(_T_818, UInt<1>(0h0)) when _T_819 : node _T_820 = eq(_T_817, UInt<1>(0h0)) when _T_820 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_817, UInt<1>(0h1), "") : assert_96 node _T_821 = eq(io.in.d.bits.denied, denied) node _T_822 = asUInt(reset) node _T_823 = eq(_T_822, UInt<1>(0h0)) when _T_823 : node _T_824 = eq(_T_821, UInt<1>(0h0)) when _T_824 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_821, UInt<1>(0h1), "") : assert_97 node _T_825 = and(io.in.d.ready, io.in.d.valid) node _T_826 = and(_T_825, d_first) when _T_826 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<4> connect a_sizes_set, UInt<4>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_827 = and(io.in.a.valid, a_first_1) node _T_828 = and(_T_827, UInt<1>(0h1)) when _T_828 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_829 = and(io.in.a.ready, io.in.a.valid) node _T_830 = and(_T_829, a_first_1) node _T_831 = and(_T_830, UInt<1>(0h1)) when _T_831 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_832 = dshr(inflight, io.in.a.bits.source) node _T_833 = bits(_T_832, 0, 0) node _T_834 = eq(_T_833, UInt<1>(0h0)) node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(_T_834, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_834, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<4> connect d_sizes_clr, UInt<4>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_838 = and(io.in.d.valid, d_first_1) node _T_839 = and(_T_838, UInt<1>(0h1)) node _T_840 = eq(d_release_ack, UInt<1>(0h0)) node _T_841 = and(_T_839, _T_840) when _T_841 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_842 = and(io.in.d.ready, io.in.d.valid) node _T_843 = and(_T_842, d_first_1) node _T_844 = and(_T_843, UInt<1>(0h1)) node _T_845 = eq(d_release_ack, UInt<1>(0h0)) node _T_846 = and(_T_844, _T_845) when _T_846 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_847 = and(io.in.d.valid, d_first_1) node _T_848 = and(_T_847, UInt<1>(0h1)) node _T_849 = eq(d_release_ack, UInt<1>(0h0)) node _T_850 = and(_T_848, _T_849) when _T_850 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_851 = dshr(inflight, io.in.d.bits.source) node _T_852 = bits(_T_851, 0, 0) node _T_853 = or(_T_852, same_cycle_resp) node _T_854 = asUInt(reset) node _T_855 = eq(_T_854, UInt<1>(0h0)) when _T_855 : node _T_856 = eq(_T_853, UInt<1>(0h0)) when _T_856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_853, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_857 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_858 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_859 = or(_T_857, _T_858) node _T_860 = asUInt(reset) node _T_861 = eq(_T_860, UInt<1>(0h0)) when _T_861 : node _T_862 = eq(_T_859, UInt<1>(0h0)) when _T_862 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_859, UInt<1>(0h1), "") : assert_100 node _T_863 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_864 = asUInt(reset) node _T_865 = eq(_T_864, UInt<1>(0h0)) when _T_865 : node _T_866 = eq(_T_863, UInt<1>(0h0)) when _T_866 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_863, UInt<1>(0h1), "") : assert_101 else : node _T_867 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_868 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_869 = or(_T_867, _T_868) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_869, UInt<1>(0h1), "") : assert_102 node _T_873 = eq(io.in.d.bits.size, a_size_lookup) node _T_874 = asUInt(reset) node _T_875 = eq(_T_874, UInt<1>(0h0)) when _T_875 : node _T_876 = eq(_T_873, UInt<1>(0h0)) when _T_876 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_873, UInt<1>(0h1), "") : assert_103 node _T_877 = and(io.in.d.valid, d_first_1) node _T_878 = and(_T_877, a_first_1) node _T_879 = and(_T_878, io.in.a.valid) node _T_880 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_881 = and(_T_879, _T_880) node _T_882 = eq(d_release_ack, UInt<1>(0h0)) node _T_883 = and(_T_881, _T_882) when _T_883 : node _T_884 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_885 = or(_T_884, io.in.a.ready) node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(_T_885, UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_885, UInt<1>(0h1), "") : assert_104 node _T_889 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_890 = orr(a_set_wo_ready) node _T_891 = eq(_T_890, UInt<1>(0h0)) node _T_892 = or(_T_889, _T_891) node _T_893 = asUInt(reset) node _T_894 = eq(_T_893, UInt<1>(0h0)) when _T_894 : node _T_895 = eq(_T_892, UInt<1>(0h0)) when _T_895 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_892, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_78 node _T_896 = orr(inflight) node _T_897 = eq(_T_896, UInt<1>(0h0)) node _T_898 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_899 = or(_T_897, _T_898) node _T_900 = lt(watchdog, plusarg_reader.out) node _T_901 = or(_T_899, _T_900) node _T_902 = asUInt(reset) node _T_903 = eq(_T_902, UInt<1>(0h0)) when _T_903 : node _T_904 = eq(_T_901, UInt<1>(0h0)) when _T_904 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_901, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_905 = and(io.in.a.ready, io.in.a.valid) node _T_906 = and(io.in.d.ready, io.in.d.valid) node _T_907 = or(_T_905, _T_906) when _T_907 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<32>(0h0) connect _c_first_WIRE.bits.address, UInt<9>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<32>(0h0) connect _c_first_WIRE_2.bits.address, UInt<9>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<4> connect c_sizes_set, UInt<4>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.address, UInt<9>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_908 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.address, UInt<9>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_909 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_910 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_911 = and(_T_909, _T_910) node _T_912 = and(_T_908, _T_911) when _T_912 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<9>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<32>(0h0) connect _WIRE_10.bits.address, UInt<9>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_913 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_914 = and(_T_913, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<32>(0h0) connect _WIRE_12.bits.address, UInt<9>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_915 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_916 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_917 = and(_T_915, _T_916) node _T_918 = and(_T_914, _T_917) when _T_918 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<32>(0h0) connect _c_set_WIRE.bits.address, UInt<9>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<9>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<9>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<9>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<9>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<32>(0h0) connect _WIRE_14.bits.address, UInt<9>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_919 = dshr(inflight_1, _WIRE_15.bits.source) node _T_920 = bits(_T_919, 0, 0) node _T_921 = eq(_T_920, UInt<1>(0h0)) node _T_922 = asUInt(reset) node _T_923 = eq(_T_922, UInt<1>(0h0)) when _T_923 : node _T_924 = eq(_T_921, UInt<1>(0h0)) when _T_924 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_921, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<9>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<9>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<4> connect d_sizes_clr_1, UInt<4>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_925 = and(io.in.d.valid, d_first_2) node _T_926 = and(_T_925, UInt<1>(0h1)) node _T_927 = and(_T_926, d_release_ack_1) when _T_927 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_928 = and(io.in.d.ready, io.in.d.valid) node _T_929 = and(_T_928, d_first_2) node _T_930 = and(_T_929, UInt<1>(0h1)) node _T_931 = and(_T_930, d_release_ack_1) when _T_931 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_932 = and(io.in.d.valid, d_first_2) node _T_933 = and(_T_932, UInt<1>(0h1)) node _T_934 = and(_T_933, d_release_ack_1) when _T_934 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_935 = dshr(inflight_1, io.in.d.bits.source) node _T_936 = bits(_T_935, 0, 0) node _T_937 = or(_T_936, same_cycle_resp_1) node _T_938 = asUInt(reset) node _T_939 = eq(_T_938, UInt<1>(0h0)) when _T_939 : node _T_940 = eq(_T_937, UInt<1>(0h0)) when _T_940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_937, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<32>(0h0) connect _WIRE_16.bits.address, UInt<9>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_941 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_942 = asUInt(reset) node _T_943 = eq(_T_942, UInt<1>(0h0)) when _T_943 : node _T_944 = eq(_T_941, UInt<1>(0h0)) when _T_944 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_941, UInt<1>(0h1), "") : assert_109 else : node _T_945 = eq(io.in.d.bits.size, c_size_lookup) node _T_946 = asUInt(reset) node _T_947 = eq(_T_946, UInt<1>(0h0)) when _T_947 : node _T_948 = eq(_T_945, UInt<1>(0h0)) when _T_948 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_945, UInt<1>(0h1), "") : assert_110 node _T_949 = and(io.in.d.valid, d_first_2) node _T_950 = and(_T_949, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<32>(0h0) connect _WIRE_18.bits.address, UInt<9>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_951 = and(_T_950, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<32>(0h0) connect _WIRE_20.bits.address, UInt<9>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_952 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_953 = and(_T_951, _T_952) node _T_954 = and(_T_953, d_release_ack_1) node _T_955 = eq(c_probe_ack, UInt<1>(0h0)) node _T_956 = and(_T_954, _T_955) when _T_956 : node _T_957 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<32>(0h0) connect _WIRE_22.bits.address, UInt<9>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_958 = or(_T_957, _WIRE_23.ready) node _T_959 = asUInt(reset) node _T_960 = eq(_T_959, UInt<1>(0h0)) when _T_960 : node _T_961 = eq(_T_958, UInt<1>(0h0)) when _T_961 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_958, UInt<1>(0h1), "") : assert_111 node _T_962 = orr(c_set_wo_ready) when _T_962 : node _T_963 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_T_963, UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_963, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_79 node _T_967 = orr(inflight_1) node _T_968 = eq(_T_967, UInt<1>(0h0)) node _T_969 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_970 = or(_T_968, _T_969) node _T_971 = lt(watchdog_1, plusarg_reader_1.out) node _T_972 = or(_T_970, _T_971) node _T_973 = asUInt(reset) node _T_974 = eq(_T_973, UInt<1>(0h0)) when _T_974 : node _T_975 = eq(_T_972, UInt<1>(0h0)) when _T_975 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_972, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<32>(0h0) connect _WIRE_24.bits.address, UInt<9>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_976 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_977 = and(io.in.d.ready, io.in.d.valid) node _T_978 = or(_T_976, _T_977) when _T_978 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_39( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [8:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [31:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [8:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [31:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire mask_sizeOH_shiftAmount = 1'h0; // @[OneHot.scala:64:49] wire mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size = 1'h1; // @[Misc.scala:209:26] wire mask_acc = 1'h1; // @[Misc.scala:215:29] wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] is_aligned_mask = 2'h3; // @[package.scala:243:46] wire [1:0] mask_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] _a_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _a_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46] wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_a_bits_size = 2'h2; // @[Monitor.scala:36:7] wire [1:0] _mask_sizeOH_T = 2'h2; // @[Misc.scala:202:34] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [3:0] io_in_a_bits_mask = 4'hF; // @[Monitor.scala:36:7] wire [3:0] mask = 4'hF; // @[Misc.scala:222:10] wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [8:0] _c_first_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_first_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_set_wo_ready_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_wo_ready_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_4_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_5_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [1:0] _is_aligned_mask_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [1:0] _mask_sizeOH_T_1 = 2'h1; // @[OneHot.scala:65:12] wire [1:0] _mask_sizeOH_T_2 = 2'h1; // @[OneHot.scala:65:27] wire [1:0] mask_sizeOH = 2'h1; // @[Misc.scala:202:81] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T_1 = 3'h5; // @[Monitor.scala:658:59] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T = 3'h4; // @[Monitor.scala:658:51] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [4:0] _is_aligned_mask_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [8:0] _is_aligned_T = {7'h0, io_in_a_bits_address_0[1:0]}; // @[Monitor.scala:36:7] wire is_aligned = _is_aligned_T == 9'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38] wire _source_ok_T_1 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire _T_905 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_905; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_905; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [8:0] address; // @[Monitor.scala:391:22] wire _T_978 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_978; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_978; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_978; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [4:0] _GEN = 5'h3 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71] wire [1:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [3:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [3:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [3:0] _GEN_0 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_0; // @[Monitor.scala:637:69, :641:65] wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_0; // @[Monitor.scala:637:69, :680:101] wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_0; // @[Monitor.scala:637:69, :681:99] wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_0; // @[Monitor.scala:637:69, :749:69] wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_0; // @[Monitor.scala:637:69, :750:67] wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_0; // @[Monitor.scala:637:69, :790:101] wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_0; // @[Monitor.scala:637:69, :791:99] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [3:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_828 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_828; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_828; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_905 & a_first_1; // @[Decoupled.scala:51:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}] assign a_sizes_set_interm = a_set ? 3'h5 : 3'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :659:54, :660:52] assign a_sizes_set = a_set ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_1 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_1; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_1; // @[Monitor.scala:673:46, :783:46] wire _T_877 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [1:0] _GEN_2 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_3 = 2'h1 << _GEN_2; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_3; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_3; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_3; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_877 & ~d_release_ack & _d_clr_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_846 = _T_978 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_846 & _d_clr_T[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_846 ? _d_opcodes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [30:0] _d_sizes_clr_T_5 = 31'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_846 ? _d_sizes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_949 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_949 & d_release_ack_1 & _d_clr_wo_ready_T_1[0]; // @[OneHot.scala:58:35] wire _T_931 = _T_978 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_931 & _d_clr_T_1[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_931 ? _d_opcodes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [30:0] _d_sizes_clr_T_11 = 31'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_931 ? _d_sizes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module IntToFP : input clock : Clock input reset : Reset output io : { flip in : { valid : UInt<1>, bits : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<64>}}, out : { valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}}} regreset in_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect in_pipe_v, io.in.valid reg in_pipe_b : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<64>}, clock when io.in.valid : connect in_pipe_b, io.in.bits wire in : { valid : UInt<1>, bits : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<64>}} connect in.valid, in_pipe_v connect in.bits, in_pipe_b wire mux : { data : UInt<65>, exc : UInt<5>} connect mux.exc, UInt<1>(0h0) node _mux_data_T = eq(in.bits.typeTagIn, UInt<1>(0h1)) node _mux_data_T_1 = mux(_mux_data_T, UInt<64>(0hffffffff00000000), UInt<64>(0hffffffffffff0000)) node _mux_data_T_2 = eq(in.bits.typeTagIn, UInt<2>(0h2)) node _mux_data_T_3 = mux(_mux_data_T_2, UInt<1>(0h0), _mux_data_T_1) node _mux_data_T_4 = eq(in.bits.typeTagIn, UInt<2>(0h3)) node _mux_data_T_5 = mux(_mux_data_T_4, UInt<1>(0h0), _mux_data_T_3) node _mux_data_T_6 = or(_mux_data_T_5, in.bits.in1) node mux_data_rawIn_sign = bits(_mux_data_T_6, 63, 63) node mux_data_rawIn_expIn = bits(_mux_data_T_6, 62, 52) node mux_data_rawIn_fractIn = bits(_mux_data_T_6, 51, 0) node mux_data_rawIn_isZeroExpIn = eq(mux_data_rawIn_expIn, UInt<1>(0h0)) node mux_data_rawIn_isZeroFractIn = eq(mux_data_rawIn_fractIn, UInt<1>(0h0)) node _mux_data_rawIn_normDist_T = bits(mux_data_rawIn_fractIn, 0, 0) node _mux_data_rawIn_normDist_T_1 = bits(mux_data_rawIn_fractIn, 1, 1) node _mux_data_rawIn_normDist_T_2 = bits(mux_data_rawIn_fractIn, 2, 2) node _mux_data_rawIn_normDist_T_3 = bits(mux_data_rawIn_fractIn, 3, 3) node _mux_data_rawIn_normDist_T_4 = bits(mux_data_rawIn_fractIn, 4, 4) node _mux_data_rawIn_normDist_T_5 = bits(mux_data_rawIn_fractIn, 5, 5) node _mux_data_rawIn_normDist_T_6 = bits(mux_data_rawIn_fractIn, 6, 6) node _mux_data_rawIn_normDist_T_7 = bits(mux_data_rawIn_fractIn, 7, 7) node _mux_data_rawIn_normDist_T_8 = bits(mux_data_rawIn_fractIn, 8, 8) node _mux_data_rawIn_normDist_T_9 = bits(mux_data_rawIn_fractIn, 9, 9) node _mux_data_rawIn_normDist_T_10 = bits(mux_data_rawIn_fractIn, 10, 10) node _mux_data_rawIn_normDist_T_11 = bits(mux_data_rawIn_fractIn, 11, 11) node _mux_data_rawIn_normDist_T_12 = bits(mux_data_rawIn_fractIn, 12, 12) node _mux_data_rawIn_normDist_T_13 = bits(mux_data_rawIn_fractIn, 13, 13) node _mux_data_rawIn_normDist_T_14 = bits(mux_data_rawIn_fractIn, 14, 14) node _mux_data_rawIn_normDist_T_15 = bits(mux_data_rawIn_fractIn, 15, 15) node _mux_data_rawIn_normDist_T_16 = bits(mux_data_rawIn_fractIn, 16, 16) node _mux_data_rawIn_normDist_T_17 = bits(mux_data_rawIn_fractIn, 17, 17) node _mux_data_rawIn_normDist_T_18 = bits(mux_data_rawIn_fractIn, 18, 18) node _mux_data_rawIn_normDist_T_19 = bits(mux_data_rawIn_fractIn, 19, 19) node _mux_data_rawIn_normDist_T_20 = bits(mux_data_rawIn_fractIn, 20, 20) node _mux_data_rawIn_normDist_T_21 = bits(mux_data_rawIn_fractIn, 21, 21) node _mux_data_rawIn_normDist_T_22 = bits(mux_data_rawIn_fractIn, 22, 22) node _mux_data_rawIn_normDist_T_23 = bits(mux_data_rawIn_fractIn, 23, 23) node _mux_data_rawIn_normDist_T_24 = bits(mux_data_rawIn_fractIn, 24, 24) node _mux_data_rawIn_normDist_T_25 = bits(mux_data_rawIn_fractIn, 25, 25) node _mux_data_rawIn_normDist_T_26 = bits(mux_data_rawIn_fractIn, 26, 26) node _mux_data_rawIn_normDist_T_27 = bits(mux_data_rawIn_fractIn, 27, 27) node _mux_data_rawIn_normDist_T_28 = bits(mux_data_rawIn_fractIn, 28, 28) node _mux_data_rawIn_normDist_T_29 = bits(mux_data_rawIn_fractIn, 29, 29) node _mux_data_rawIn_normDist_T_30 = bits(mux_data_rawIn_fractIn, 30, 30) node _mux_data_rawIn_normDist_T_31 = bits(mux_data_rawIn_fractIn, 31, 31) node _mux_data_rawIn_normDist_T_32 = bits(mux_data_rawIn_fractIn, 32, 32) node _mux_data_rawIn_normDist_T_33 = bits(mux_data_rawIn_fractIn, 33, 33) node _mux_data_rawIn_normDist_T_34 = bits(mux_data_rawIn_fractIn, 34, 34) node _mux_data_rawIn_normDist_T_35 = bits(mux_data_rawIn_fractIn, 35, 35) node _mux_data_rawIn_normDist_T_36 = bits(mux_data_rawIn_fractIn, 36, 36) node _mux_data_rawIn_normDist_T_37 = bits(mux_data_rawIn_fractIn, 37, 37) node _mux_data_rawIn_normDist_T_38 = bits(mux_data_rawIn_fractIn, 38, 38) node _mux_data_rawIn_normDist_T_39 = bits(mux_data_rawIn_fractIn, 39, 39) node _mux_data_rawIn_normDist_T_40 = bits(mux_data_rawIn_fractIn, 40, 40) node _mux_data_rawIn_normDist_T_41 = bits(mux_data_rawIn_fractIn, 41, 41) node _mux_data_rawIn_normDist_T_42 = bits(mux_data_rawIn_fractIn, 42, 42) node _mux_data_rawIn_normDist_T_43 = bits(mux_data_rawIn_fractIn, 43, 43) node _mux_data_rawIn_normDist_T_44 = bits(mux_data_rawIn_fractIn, 44, 44) node _mux_data_rawIn_normDist_T_45 = bits(mux_data_rawIn_fractIn, 45, 45) node _mux_data_rawIn_normDist_T_46 = bits(mux_data_rawIn_fractIn, 46, 46) node _mux_data_rawIn_normDist_T_47 = bits(mux_data_rawIn_fractIn, 47, 47) node _mux_data_rawIn_normDist_T_48 = bits(mux_data_rawIn_fractIn, 48, 48) node _mux_data_rawIn_normDist_T_49 = bits(mux_data_rawIn_fractIn, 49, 49) node _mux_data_rawIn_normDist_T_50 = bits(mux_data_rawIn_fractIn, 50, 50) node _mux_data_rawIn_normDist_T_51 = bits(mux_data_rawIn_fractIn, 51, 51) node _mux_data_rawIn_normDist_T_52 = mux(_mux_data_rawIn_normDist_T_1, UInt<6>(0h32), UInt<6>(0h33)) node _mux_data_rawIn_normDist_T_53 = mux(_mux_data_rawIn_normDist_T_2, UInt<6>(0h31), _mux_data_rawIn_normDist_T_52) node _mux_data_rawIn_normDist_T_54 = mux(_mux_data_rawIn_normDist_T_3, UInt<6>(0h30), _mux_data_rawIn_normDist_T_53) node _mux_data_rawIn_normDist_T_55 = mux(_mux_data_rawIn_normDist_T_4, UInt<6>(0h2f), _mux_data_rawIn_normDist_T_54) node _mux_data_rawIn_normDist_T_56 = mux(_mux_data_rawIn_normDist_T_5, UInt<6>(0h2e), _mux_data_rawIn_normDist_T_55) node _mux_data_rawIn_normDist_T_57 = mux(_mux_data_rawIn_normDist_T_6, UInt<6>(0h2d), _mux_data_rawIn_normDist_T_56) node _mux_data_rawIn_normDist_T_58 = mux(_mux_data_rawIn_normDist_T_7, UInt<6>(0h2c), _mux_data_rawIn_normDist_T_57) node _mux_data_rawIn_normDist_T_59 = mux(_mux_data_rawIn_normDist_T_8, UInt<6>(0h2b), _mux_data_rawIn_normDist_T_58) node _mux_data_rawIn_normDist_T_60 = mux(_mux_data_rawIn_normDist_T_9, UInt<6>(0h2a), _mux_data_rawIn_normDist_T_59) node _mux_data_rawIn_normDist_T_61 = mux(_mux_data_rawIn_normDist_T_10, UInt<6>(0h29), _mux_data_rawIn_normDist_T_60) node _mux_data_rawIn_normDist_T_62 = mux(_mux_data_rawIn_normDist_T_11, UInt<6>(0h28), _mux_data_rawIn_normDist_T_61) node _mux_data_rawIn_normDist_T_63 = mux(_mux_data_rawIn_normDist_T_12, UInt<6>(0h27), _mux_data_rawIn_normDist_T_62) node _mux_data_rawIn_normDist_T_64 = mux(_mux_data_rawIn_normDist_T_13, UInt<6>(0h26), _mux_data_rawIn_normDist_T_63) node _mux_data_rawIn_normDist_T_65 = mux(_mux_data_rawIn_normDist_T_14, UInt<6>(0h25), _mux_data_rawIn_normDist_T_64) node _mux_data_rawIn_normDist_T_66 = mux(_mux_data_rawIn_normDist_T_15, UInt<6>(0h24), _mux_data_rawIn_normDist_T_65) node _mux_data_rawIn_normDist_T_67 = mux(_mux_data_rawIn_normDist_T_16, UInt<6>(0h23), _mux_data_rawIn_normDist_T_66) node _mux_data_rawIn_normDist_T_68 = mux(_mux_data_rawIn_normDist_T_17, UInt<6>(0h22), _mux_data_rawIn_normDist_T_67) node _mux_data_rawIn_normDist_T_69 = mux(_mux_data_rawIn_normDist_T_18, UInt<6>(0h21), _mux_data_rawIn_normDist_T_68) node _mux_data_rawIn_normDist_T_70 = mux(_mux_data_rawIn_normDist_T_19, UInt<6>(0h20), _mux_data_rawIn_normDist_T_69) node _mux_data_rawIn_normDist_T_71 = mux(_mux_data_rawIn_normDist_T_20, UInt<5>(0h1f), _mux_data_rawIn_normDist_T_70) node _mux_data_rawIn_normDist_T_72 = mux(_mux_data_rawIn_normDist_T_21, UInt<5>(0h1e), _mux_data_rawIn_normDist_T_71) node _mux_data_rawIn_normDist_T_73 = mux(_mux_data_rawIn_normDist_T_22, UInt<5>(0h1d), _mux_data_rawIn_normDist_T_72) node _mux_data_rawIn_normDist_T_74 = mux(_mux_data_rawIn_normDist_T_23, UInt<5>(0h1c), _mux_data_rawIn_normDist_T_73) node _mux_data_rawIn_normDist_T_75 = mux(_mux_data_rawIn_normDist_T_24, UInt<5>(0h1b), _mux_data_rawIn_normDist_T_74) node _mux_data_rawIn_normDist_T_76 = mux(_mux_data_rawIn_normDist_T_25, UInt<5>(0h1a), _mux_data_rawIn_normDist_T_75) node _mux_data_rawIn_normDist_T_77 = mux(_mux_data_rawIn_normDist_T_26, UInt<5>(0h19), _mux_data_rawIn_normDist_T_76) node _mux_data_rawIn_normDist_T_78 = mux(_mux_data_rawIn_normDist_T_27, UInt<5>(0h18), _mux_data_rawIn_normDist_T_77) node _mux_data_rawIn_normDist_T_79 = mux(_mux_data_rawIn_normDist_T_28, UInt<5>(0h17), _mux_data_rawIn_normDist_T_78) node _mux_data_rawIn_normDist_T_80 = mux(_mux_data_rawIn_normDist_T_29, UInt<5>(0h16), _mux_data_rawIn_normDist_T_79) node _mux_data_rawIn_normDist_T_81 = mux(_mux_data_rawIn_normDist_T_30, UInt<5>(0h15), _mux_data_rawIn_normDist_T_80) node _mux_data_rawIn_normDist_T_82 = mux(_mux_data_rawIn_normDist_T_31, UInt<5>(0h14), _mux_data_rawIn_normDist_T_81) node _mux_data_rawIn_normDist_T_83 = mux(_mux_data_rawIn_normDist_T_32, UInt<5>(0h13), _mux_data_rawIn_normDist_T_82) node _mux_data_rawIn_normDist_T_84 = mux(_mux_data_rawIn_normDist_T_33, UInt<5>(0h12), _mux_data_rawIn_normDist_T_83) node _mux_data_rawIn_normDist_T_85 = mux(_mux_data_rawIn_normDist_T_34, UInt<5>(0h11), _mux_data_rawIn_normDist_T_84) node _mux_data_rawIn_normDist_T_86 = mux(_mux_data_rawIn_normDist_T_35, UInt<5>(0h10), _mux_data_rawIn_normDist_T_85) node _mux_data_rawIn_normDist_T_87 = mux(_mux_data_rawIn_normDist_T_36, UInt<4>(0hf), _mux_data_rawIn_normDist_T_86) node _mux_data_rawIn_normDist_T_88 = mux(_mux_data_rawIn_normDist_T_37, UInt<4>(0he), _mux_data_rawIn_normDist_T_87) node _mux_data_rawIn_normDist_T_89 = mux(_mux_data_rawIn_normDist_T_38, UInt<4>(0hd), _mux_data_rawIn_normDist_T_88) node _mux_data_rawIn_normDist_T_90 = mux(_mux_data_rawIn_normDist_T_39, UInt<4>(0hc), _mux_data_rawIn_normDist_T_89) node _mux_data_rawIn_normDist_T_91 = mux(_mux_data_rawIn_normDist_T_40, UInt<4>(0hb), _mux_data_rawIn_normDist_T_90) node _mux_data_rawIn_normDist_T_92 = mux(_mux_data_rawIn_normDist_T_41, UInt<4>(0ha), _mux_data_rawIn_normDist_T_91) node _mux_data_rawIn_normDist_T_93 = mux(_mux_data_rawIn_normDist_T_42, UInt<4>(0h9), _mux_data_rawIn_normDist_T_92) node _mux_data_rawIn_normDist_T_94 = mux(_mux_data_rawIn_normDist_T_43, UInt<4>(0h8), _mux_data_rawIn_normDist_T_93) node _mux_data_rawIn_normDist_T_95 = mux(_mux_data_rawIn_normDist_T_44, UInt<3>(0h7), _mux_data_rawIn_normDist_T_94) node _mux_data_rawIn_normDist_T_96 = mux(_mux_data_rawIn_normDist_T_45, UInt<3>(0h6), _mux_data_rawIn_normDist_T_95) node _mux_data_rawIn_normDist_T_97 = mux(_mux_data_rawIn_normDist_T_46, UInt<3>(0h5), _mux_data_rawIn_normDist_T_96) node _mux_data_rawIn_normDist_T_98 = mux(_mux_data_rawIn_normDist_T_47, UInt<3>(0h4), _mux_data_rawIn_normDist_T_97) node _mux_data_rawIn_normDist_T_99 = mux(_mux_data_rawIn_normDist_T_48, UInt<2>(0h3), _mux_data_rawIn_normDist_T_98) node _mux_data_rawIn_normDist_T_100 = mux(_mux_data_rawIn_normDist_T_49, UInt<2>(0h2), _mux_data_rawIn_normDist_T_99) node _mux_data_rawIn_normDist_T_101 = mux(_mux_data_rawIn_normDist_T_50, UInt<1>(0h1), _mux_data_rawIn_normDist_T_100) node mux_data_rawIn_normDist = mux(_mux_data_rawIn_normDist_T_51, UInt<1>(0h0), _mux_data_rawIn_normDist_T_101) node _mux_data_rawIn_subnormFract_T = dshl(mux_data_rawIn_fractIn, mux_data_rawIn_normDist) node _mux_data_rawIn_subnormFract_T_1 = bits(_mux_data_rawIn_subnormFract_T, 50, 0) node mux_data_rawIn_subnormFract = shl(_mux_data_rawIn_subnormFract_T_1, 1) node _mux_data_rawIn_adjustedExp_T = xor(mux_data_rawIn_normDist, UInt<12>(0hfff)) node _mux_data_rawIn_adjustedExp_T_1 = mux(mux_data_rawIn_isZeroExpIn, _mux_data_rawIn_adjustedExp_T, mux_data_rawIn_expIn) node _mux_data_rawIn_adjustedExp_T_2 = mux(mux_data_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1)) node _mux_data_rawIn_adjustedExp_T_3 = or(UInt<11>(0h400), _mux_data_rawIn_adjustedExp_T_2) node _mux_data_rawIn_adjustedExp_T_4 = add(_mux_data_rawIn_adjustedExp_T_1, _mux_data_rawIn_adjustedExp_T_3) node mux_data_rawIn_adjustedExp = tail(_mux_data_rawIn_adjustedExp_T_4, 1) node mux_data_rawIn_isZero = and(mux_data_rawIn_isZeroExpIn, mux_data_rawIn_isZeroFractIn) node _mux_data_rawIn_isSpecial_T = bits(mux_data_rawIn_adjustedExp, 11, 10) node mux_data_rawIn_isSpecial = eq(_mux_data_rawIn_isSpecial_T, UInt<2>(0h3)) wire mux_data_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _mux_data_rawIn_out_isNaN_T = eq(mux_data_rawIn_isZeroFractIn, UInt<1>(0h0)) node _mux_data_rawIn_out_isNaN_T_1 = and(mux_data_rawIn_isSpecial, _mux_data_rawIn_out_isNaN_T) connect mux_data_rawIn.isNaN, _mux_data_rawIn_out_isNaN_T_1 node _mux_data_rawIn_out_isInf_T = and(mux_data_rawIn_isSpecial, mux_data_rawIn_isZeroFractIn) connect mux_data_rawIn.isInf, _mux_data_rawIn_out_isInf_T connect mux_data_rawIn.isZero, mux_data_rawIn_isZero connect mux_data_rawIn.sign, mux_data_rawIn_sign node _mux_data_rawIn_out_sExp_T = bits(mux_data_rawIn_adjustedExp, 11, 0) node _mux_data_rawIn_out_sExp_T_1 = cvt(_mux_data_rawIn_out_sExp_T) connect mux_data_rawIn.sExp, _mux_data_rawIn_out_sExp_T_1 node _mux_data_rawIn_out_sig_T = eq(mux_data_rawIn_isZero, UInt<1>(0h0)) node _mux_data_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _mux_data_rawIn_out_sig_T) node _mux_data_rawIn_out_sig_T_2 = mux(mux_data_rawIn_isZeroExpIn, mux_data_rawIn_subnormFract, mux_data_rawIn_fractIn) node _mux_data_rawIn_out_sig_T_3 = cat(_mux_data_rawIn_out_sig_T_1, _mux_data_rawIn_out_sig_T_2) connect mux_data_rawIn.sig, _mux_data_rawIn_out_sig_T_3 node _mux_data_T_7 = bits(mux_data_rawIn.sExp, 11, 9) node _mux_data_T_8 = mux(mux_data_rawIn.isZero, UInt<3>(0h0), _mux_data_T_7) node _mux_data_T_9 = mux(mux_data_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _mux_data_T_10 = or(_mux_data_T_8, _mux_data_T_9) node _mux_data_T_11 = cat(mux_data_rawIn.sign, _mux_data_T_10) node _mux_data_T_12 = bits(mux_data_rawIn.sExp, 8, 0) node _mux_data_T_13 = cat(_mux_data_T_11, _mux_data_T_12) node _mux_data_T_14 = bits(mux_data_rawIn.sig, 51, 0) node _mux_data_T_15 = cat(_mux_data_T_13, _mux_data_T_14) node mux_data_rawIn_sign_1 = bits(_mux_data_T_6, 31, 31) node mux_data_rawIn_expIn_1 = bits(_mux_data_T_6, 30, 23) node mux_data_rawIn_fractIn_1 = bits(_mux_data_T_6, 22, 0) node mux_data_rawIn_isZeroExpIn_1 = eq(mux_data_rawIn_expIn_1, UInt<1>(0h0)) node mux_data_rawIn_isZeroFractIn_1 = eq(mux_data_rawIn_fractIn_1, UInt<1>(0h0)) node _mux_data_rawIn_normDist_T_102 = bits(mux_data_rawIn_fractIn_1, 0, 0) node _mux_data_rawIn_normDist_T_103 = bits(mux_data_rawIn_fractIn_1, 1, 1) node _mux_data_rawIn_normDist_T_104 = bits(mux_data_rawIn_fractIn_1, 2, 2) node _mux_data_rawIn_normDist_T_105 = bits(mux_data_rawIn_fractIn_1, 3, 3) node _mux_data_rawIn_normDist_T_106 = bits(mux_data_rawIn_fractIn_1, 4, 4) node _mux_data_rawIn_normDist_T_107 = bits(mux_data_rawIn_fractIn_1, 5, 5) node _mux_data_rawIn_normDist_T_108 = bits(mux_data_rawIn_fractIn_1, 6, 6) node _mux_data_rawIn_normDist_T_109 = bits(mux_data_rawIn_fractIn_1, 7, 7) node _mux_data_rawIn_normDist_T_110 = bits(mux_data_rawIn_fractIn_1, 8, 8) node _mux_data_rawIn_normDist_T_111 = bits(mux_data_rawIn_fractIn_1, 9, 9) node _mux_data_rawIn_normDist_T_112 = bits(mux_data_rawIn_fractIn_1, 10, 10) node _mux_data_rawIn_normDist_T_113 = bits(mux_data_rawIn_fractIn_1, 11, 11) node _mux_data_rawIn_normDist_T_114 = bits(mux_data_rawIn_fractIn_1, 12, 12) node _mux_data_rawIn_normDist_T_115 = bits(mux_data_rawIn_fractIn_1, 13, 13) node _mux_data_rawIn_normDist_T_116 = bits(mux_data_rawIn_fractIn_1, 14, 14) node _mux_data_rawIn_normDist_T_117 = bits(mux_data_rawIn_fractIn_1, 15, 15) node _mux_data_rawIn_normDist_T_118 = bits(mux_data_rawIn_fractIn_1, 16, 16) node _mux_data_rawIn_normDist_T_119 = bits(mux_data_rawIn_fractIn_1, 17, 17) node _mux_data_rawIn_normDist_T_120 = bits(mux_data_rawIn_fractIn_1, 18, 18) node _mux_data_rawIn_normDist_T_121 = bits(mux_data_rawIn_fractIn_1, 19, 19) node _mux_data_rawIn_normDist_T_122 = bits(mux_data_rawIn_fractIn_1, 20, 20) node _mux_data_rawIn_normDist_T_123 = bits(mux_data_rawIn_fractIn_1, 21, 21) node _mux_data_rawIn_normDist_T_124 = bits(mux_data_rawIn_fractIn_1, 22, 22) node _mux_data_rawIn_normDist_T_125 = mux(_mux_data_rawIn_normDist_T_103, UInt<5>(0h15), UInt<5>(0h16)) node _mux_data_rawIn_normDist_T_126 = mux(_mux_data_rawIn_normDist_T_104, UInt<5>(0h14), _mux_data_rawIn_normDist_T_125) node _mux_data_rawIn_normDist_T_127 = mux(_mux_data_rawIn_normDist_T_105, UInt<5>(0h13), _mux_data_rawIn_normDist_T_126) node _mux_data_rawIn_normDist_T_128 = mux(_mux_data_rawIn_normDist_T_106, UInt<5>(0h12), _mux_data_rawIn_normDist_T_127) node _mux_data_rawIn_normDist_T_129 = mux(_mux_data_rawIn_normDist_T_107, UInt<5>(0h11), _mux_data_rawIn_normDist_T_128) node _mux_data_rawIn_normDist_T_130 = mux(_mux_data_rawIn_normDist_T_108, UInt<5>(0h10), _mux_data_rawIn_normDist_T_129) node _mux_data_rawIn_normDist_T_131 = mux(_mux_data_rawIn_normDist_T_109, UInt<4>(0hf), _mux_data_rawIn_normDist_T_130) node _mux_data_rawIn_normDist_T_132 = mux(_mux_data_rawIn_normDist_T_110, UInt<4>(0he), _mux_data_rawIn_normDist_T_131) node _mux_data_rawIn_normDist_T_133 = mux(_mux_data_rawIn_normDist_T_111, UInt<4>(0hd), _mux_data_rawIn_normDist_T_132) node _mux_data_rawIn_normDist_T_134 = mux(_mux_data_rawIn_normDist_T_112, UInt<4>(0hc), _mux_data_rawIn_normDist_T_133) node _mux_data_rawIn_normDist_T_135 = mux(_mux_data_rawIn_normDist_T_113, UInt<4>(0hb), _mux_data_rawIn_normDist_T_134) node _mux_data_rawIn_normDist_T_136 = mux(_mux_data_rawIn_normDist_T_114, UInt<4>(0ha), _mux_data_rawIn_normDist_T_135) node _mux_data_rawIn_normDist_T_137 = mux(_mux_data_rawIn_normDist_T_115, UInt<4>(0h9), _mux_data_rawIn_normDist_T_136) node _mux_data_rawIn_normDist_T_138 = mux(_mux_data_rawIn_normDist_T_116, UInt<4>(0h8), _mux_data_rawIn_normDist_T_137) node _mux_data_rawIn_normDist_T_139 = mux(_mux_data_rawIn_normDist_T_117, UInt<3>(0h7), _mux_data_rawIn_normDist_T_138) node _mux_data_rawIn_normDist_T_140 = mux(_mux_data_rawIn_normDist_T_118, UInt<3>(0h6), _mux_data_rawIn_normDist_T_139) node _mux_data_rawIn_normDist_T_141 = mux(_mux_data_rawIn_normDist_T_119, UInt<3>(0h5), _mux_data_rawIn_normDist_T_140) node _mux_data_rawIn_normDist_T_142 = mux(_mux_data_rawIn_normDist_T_120, UInt<3>(0h4), _mux_data_rawIn_normDist_T_141) node _mux_data_rawIn_normDist_T_143 = mux(_mux_data_rawIn_normDist_T_121, UInt<2>(0h3), _mux_data_rawIn_normDist_T_142) node _mux_data_rawIn_normDist_T_144 = mux(_mux_data_rawIn_normDist_T_122, UInt<2>(0h2), _mux_data_rawIn_normDist_T_143) node _mux_data_rawIn_normDist_T_145 = mux(_mux_data_rawIn_normDist_T_123, UInt<1>(0h1), _mux_data_rawIn_normDist_T_144) node mux_data_rawIn_normDist_1 = mux(_mux_data_rawIn_normDist_T_124, UInt<1>(0h0), _mux_data_rawIn_normDist_T_145) node _mux_data_rawIn_subnormFract_T_2 = dshl(mux_data_rawIn_fractIn_1, mux_data_rawIn_normDist_1) node _mux_data_rawIn_subnormFract_T_3 = bits(_mux_data_rawIn_subnormFract_T_2, 21, 0) node mux_data_rawIn_subnormFract_1 = shl(_mux_data_rawIn_subnormFract_T_3, 1) node _mux_data_rawIn_adjustedExp_T_5 = xor(mux_data_rawIn_normDist_1, UInt<9>(0h1ff)) node _mux_data_rawIn_adjustedExp_T_6 = mux(mux_data_rawIn_isZeroExpIn_1, _mux_data_rawIn_adjustedExp_T_5, mux_data_rawIn_expIn_1) node _mux_data_rawIn_adjustedExp_T_7 = mux(mux_data_rawIn_isZeroExpIn_1, UInt<2>(0h2), UInt<1>(0h1)) node _mux_data_rawIn_adjustedExp_T_8 = or(UInt<8>(0h80), _mux_data_rawIn_adjustedExp_T_7) node _mux_data_rawIn_adjustedExp_T_9 = add(_mux_data_rawIn_adjustedExp_T_6, _mux_data_rawIn_adjustedExp_T_8) node mux_data_rawIn_adjustedExp_1 = tail(_mux_data_rawIn_adjustedExp_T_9, 1) node mux_data_rawIn_isZero_1 = and(mux_data_rawIn_isZeroExpIn_1, mux_data_rawIn_isZeroFractIn_1) node _mux_data_rawIn_isSpecial_T_1 = bits(mux_data_rawIn_adjustedExp_1, 8, 7) node mux_data_rawIn_isSpecial_1 = eq(_mux_data_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire mux_data_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _mux_data_rawIn_out_isNaN_T_2 = eq(mux_data_rawIn_isZeroFractIn_1, UInt<1>(0h0)) node _mux_data_rawIn_out_isNaN_T_3 = and(mux_data_rawIn_isSpecial_1, _mux_data_rawIn_out_isNaN_T_2) connect mux_data_rawIn_1.isNaN, _mux_data_rawIn_out_isNaN_T_3 node _mux_data_rawIn_out_isInf_T_1 = and(mux_data_rawIn_isSpecial_1, mux_data_rawIn_isZeroFractIn_1) connect mux_data_rawIn_1.isInf, _mux_data_rawIn_out_isInf_T_1 connect mux_data_rawIn_1.isZero, mux_data_rawIn_isZero_1 connect mux_data_rawIn_1.sign, mux_data_rawIn_sign_1 node _mux_data_rawIn_out_sExp_T_2 = bits(mux_data_rawIn_adjustedExp_1, 8, 0) node _mux_data_rawIn_out_sExp_T_3 = cvt(_mux_data_rawIn_out_sExp_T_2) connect mux_data_rawIn_1.sExp, _mux_data_rawIn_out_sExp_T_3 node _mux_data_rawIn_out_sig_T_4 = eq(mux_data_rawIn_isZero_1, UInt<1>(0h0)) node _mux_data_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _mux_data_rawIn_out_sig_T_4) node _mux_data_rawIn_out_sig_T_6 = mux(mux_data_rawIn_isZeroExpIn_1, mux_data_rawIn_subnormFract_1, mux_data_rawIn_fractIn_1) node _mux_data_rawIn_out_sig_T_7 = cat(_mux_data_rawIn_out_sig_T_5, _mux_data_rawIn_out_sig_T_6) connect mux_data_rawIn_1.sig, _mux_data_rawIn_out_sig_T_7 node _mux_data_T_16 = bits(mux_data_rawIn_1.sExp, 8, 6) node _mux_data_T_17 = mux(mux_data_rawIn_1.isZero, UInt<3>(0h0), _mux_data_T_16) node _mux_data_T_18 = mux(mux_data_rawIn_1.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _mux_data_T_19 = or(_mux_data_T_17, _mux_data_T_18) node _mux_data_T_20 = cat(mux_data_rawIn_1.sign, _mux_data_T_19) node _mux_data_T_21 = bits(mux_data_rawIn_1.sExp, 5, 0) node _mux_data_T_22 = cat(_mux_data_T_20, _mux_data_T_21) node _mux_data_T_23 = bits(mux_data_rawIn_1.sig, 22, 0) node _mux_data_T_24 = cat(_mux_data_T_22, _mux_data_T_23) node mux_data_rawIn_sign_2 = bits(_mux_data_T_6, 15, 15) node mux_data_rawIn_expIn_2 = bits(_mux_data_T_6, 14, 10) node mux_data_rawIn_fractIn_2 = bits(_mux_data_T_6, 9, 0) node mux_data_rawIn_isZeroExpIn_2 = eq(mux_data_rawIn_expIn_2, UInt<1>(0h0)) node mux_data_rawIn_isZeroFractIn_2 = eq(mux_data_rawIn_fractIn_2, UInt<1>(0h0)) node _mux_data_rawIn_normDist_T_146 = bits(mux_data_rawIn_fractIn_2, 0, 0) node _mux_data_rawIn_normDist_T_147 = bits(mux_data_rawIn_fractIn_2, 1, 1) node _mux_data_rawIn_normDist_T_148 = bits(mux_data_rawIn_fractIn_2, 2, 2) node _mux_data_rawIn_normDist_T_149 = bits(mux_data_rawIn_fractIn_2, 3, 3) node _mux_data_rawIn_normDist_T_150 = bits(mux_data_rawIn_fractIn_2, 4, 4) node _mux_data_rawIn_normDist_T_151 = bits(mux_data_rawIn_fractIn_2, 5, 5) node _mux_data_rawIn_normDist_T_152 = bits(mux_data_rawIn_fractIn_2, 6, 6) node _mux_data_rawIn_normDist_T_153 = bits(mux_data_rawIn_fractIn_2, 7, 7) node _mux_data_rawIn_normDist_T_154 = bits(mux_data_rawIn_fractIn_2, 8, 8) node _mux_data_rawIn_normDist_T_155 = bits(mux_data_rawIn_fractIn_2, 9, 9) node _mux_data_rawIn_normDist_T_156 = mux(_mux_data_rawIn_normDist_T_147, UInt<4>(0h8), UInt<4>(0h9)) node _mux_data_rawIn_normDist_T_157 = mux(_mux_data_rawIn_normDist_T_148, UInt<3>(0h7), _mux_data_rawIn_normDist_T_156) node _mux_data_rawIn_normDist_T_158 = mux(_mux_data_rawIn_normDist_T_149, UInt<3>(0h6), _mux_data_rawIn_normDist_T_157) node _mux_data_rawIn_normDist_T_159 = mux(_mux_data_rawIn_normDist_T_150, UInt<3>(0h5), _mux_data_rawIn_normDist_T_158) node _mux_data_rawIn_normDist_T_160 = mux(_mux_data_rawIn_normDist_T_151, UInt<3>(0h4), _mux_data_rawIn_normDist_T_159) node _mux_data_rawIn_normDist_T_161 = mux(_mux_data_rawIn_normDist_T_152, UInt<2>(0h3), _mux_data_rawIn_normDist_T_160) node _mux_data_rawIn_normDist_T_162 = mux(_mux_data_rawIn_normDist_T_153, UInt<2>(0h2), _mux_data_rawIn_normDist_T_161) node _mux_data_rawIn_normDist_T_163 = mux(_mux_data_rawIn_normDist_T_154, UInt<1>(0h1), _mux_data_rawIn_normDist_T_162) node mux_data_rawIn_normDist_2 = mux(_mux_data_rawIn_normDist_T_155, UInt<1>(0h0), _mux_data_rawIn_normDist_T_163) node _mux_data_rawIn_subnormFract_T_4 = dshl(mux_data_rawIn_fractIn_2, mux_data_rawIn_normDist_2) node _mux_data_rawIn_subnormFract_T_5 = bits(_mux_data_rawIn_subnormFract_T_4, 8, 0) node mux_data_rawIn_subnormFract_2 = shl(_mux_data_rawIn_subnormFract_T_5, 1) node _mux_data_rawIn_adjustedExp_T_10 = xor(mux_data_rawIn_normDist_2, UInt<6>(0h3f)) node _mux_data_rawIn_adjustedExp_T_11 = mux(mux_data_rawIn_isZeroExpIn_2, _mux_data_rawIn_adjustedExp_T_10, mux_data_rawIn_expIn_2) node _mux_data_rawIn_adjustedExp_T_12 = mux(mux_data_rawIn_isZeroExpIn_2, UInt<2>(0h2), UInt<1>(0h1)) node _mux_data_rawIn_adjustedExp_T_13 = or(UInt<5>(0h10), _mux_data_rawIn_adjustedExp_T_12) node _mux_data_rawIn_adjustedExp_T_14 = add(_mux_data_rawIn_adjustedExp_T_11, _mux_data_rawIn_adjustedExp_T_13) node mux_data_rawIn_adjustedExp_2 = tail(_mux_data_rawIn_adjustedExp_T_14, 1) node mux_data_rawIn_isZero_2 = and(mux_data_rawIn_isZeroExpIn_2, mux_data_rawIn_isZeroFractIn_2) node _mux_data_rawIn_isSpecial_T_2 = bits(mux_data_rawIn_adjustedExp_2, 5, 4) node mux_data_rawIn_isSpecial_2 = eq(_mux_data_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire mux_data_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _mux_data_rawIn_out_isNaN_T_4 = eq(mux_data_rawIn_isZeroFractIn_2, UInt<1>(0h0)) node _mux_data_rawIn_out_isNaN_T_5 = and(mux_data_rawIn_isSpecial_2, _mux_data_rawIn_out_isNaN_T_4) connect mux_data_rawIn_2.isNaN, _mux_data_rawIn_out_isNaN_T_5 node _mux_data_rawIn_out_isInf_T_2 = and(mux_data_rawIn_isSpecial_2, mux_data_rawIn_isZeroFractIn_2) connect mux_data_rawIn_2.isInf, _mux_data_rawIn_out_isInf_T_2 connect mux_data_rawIn_2.isZero, mux_data_rawIn_isZero_2 connect mux_data_rawIn_2.sign, mux_data_rawIn_sign_2 node _mux_data_rawIn_out_sExp_T_4 = bits(mux_data_rawIn_adjustedExp_2, 5, 0) node _mux_data_rawIn_out_sExp_T_5 = cvt(_mux_data_rawIn_out_sExp_T_4) connect mux_data_rawIn_2.sExp, _mux_data_rawIn_out_sExp_T_5 node _mux_data_rawIn_out_sig_T_8 = eq(mux_data_rawIn_isZero_2, UInt<1>(0h0)) node _mux_data_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _mux_data_rawIn_out_sig_T_8) node _mux_data_rawIn_out_sig_T_10 = mux(mux_data_rawIn_isZeroExpIn_2, mux_data_rawIn_subnormFract_2, mux_data_rawIn_fractIn_2) node _mux_data_rawIn_out_sig_T_11 = cat(_mux_data_rawIn_out_sig_T_9, _mux_data_rawIn_out_sig_T_10) connect mux_data_rawIn_2.sig, _mux_data_rawIn_out_sig_T_11 node _mux_data_T_25 = bits(mux_data_rawIn_2.sExp, 5, 3) node _mux_data_T_26 = mux(mux_data_rawIn_2.isZero, UInt<3>(0h0), _mux_data_T_25) node _mux_data_T_27 = mux(mux_data_rawIn_2.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _mux_data_T_28 = or(_mux_data_T_26, _mux_data_T_27) node _mux_data_T_29 = cat(mux_data_rawIn_2.sign, _mux_data_T_28) node _mux_data_T_30 = bits(mux_data_rawIn_2.sExp, 2, 0) node _mux_data_T_31 = cat(_mux_data_T_29, _mux_data_T_30) node _mux_data_T_32 = bits(mux_data_rawIn_2.sig, 9, 0) node _mux_data_T_33 = cat(_mux_data_T_31, _mux_data_T_32) node _mux_data_swizzledNaN_T = bits(_mux_data_T_24, 32, 29) node _mux_data_swizzledNaN_T_1 = bits(_mux_data_T_24, 22, 16) node _mux_data_swizzledNaN_T_2 = andr(_mux_data_swizzledNaN_T_1) node _mux_data_swizzledNaN_T_3 = bits(_mux_data_T_24, 27, 24) node _mux_data_swizzledNaN_T_4 = bits(_mux_data_T_33, 15, 15) node _mux_data_swizzledNaN_T_5 = bits(_mux_data_T_24, 22, 16) node _mux_data_swizzledNaN_T_6 = bits(_mux_data_T_33, 16, 16) node _mux_data_swizzledNaN_T_7 = bits(_mux_data_T_33, 14, 0) node mux_data_swizzledNaN_lo_hi = cat(_mux_data_swizzledNaN_T_5, _mux_data_swizzledNaN_T_6) node mux_data_swizzledNaN_lo = cat(mux_data_swizzledNaN_lo_hi, _mux_data_swizzledNaN_T_7) node mux_data_swizzledNaN_hi_lo = cat(_mux_data_swizzledNaN_T_3, _mux_data_swizzledNaN_T_4) node mux_data_swizzledNaN_hi_hi = cat(_mux_data_swizzledNaN_T, _mux_data_swizzledNaN_T_2) node mux_data_swizzledNaN_hi = cat(mux_data_swizzledNaN_hi_hi, mux_data_swizzledNaN_hi_lo) node mux_data_swizzledNaN = cat(mux_data_swizzledNaN_hi, mux_data_swizzledNaN_lo) node _mux_data_T_34 = bits(_mux_data_T_24, 31, 29) node _mux_data_T_35 = andr(_mux_data_T_34) node _mux_data_T_36 = mux(_mux_data_T_35, mux_data_swizzledNaN, _mux_data_T_24) node _mux_data_swizzledNaN_T_8 = bits(_mux_data_T_15, 64, 61) node _mux_data_swizzledNaN_T_9 = bits(_mux_data_T_15, 51, 32) node _mux_data_swizzledNaN_T_10 = andr(_mux_data_swizzledNaN_T_9) node _mux_data_swizzledNaN_T_11 = bits(_mux_data_T_15, 59, 53) node _mux_data_swizzledNaN_T_12 = bits(_mux_data_T_36, 31, 31) node _mux_data_swizzledNaN_T_13 = bits(_mux_data_T_15, 51, 32) node _mux_data_swizzledNaN_T_14 = bits(_mux_data_T_36, 32, 32) node _mux_data_swizzledNaN_T_15 = bits(_mux_data_T_36, 30, 0) node mux_data_swizzledNaN_lo_hi_1 = cat(_mux_data_swizzledNaN_T_13, _mux_data_swizzledNaN_T_14) node mux_data_swizzledNaN_lo_1 = cat(mux_data_swizzledNaN_lo_hi_1, _mux_data_swizzledNaN_T_15) node mux_data_swizzledNaN_hi_lo_1 = cat(_mux_data_swizzledNaN_T_11, _mux_data_swizzledNaN_T_12) node mux_data_swizzledNaN_hi_hi_1 = cat(_mux_data_swizzledNaN_T_8, _mux_data_swizzledNaN_T_10) node mux_data_swizzledNaN_hi_1 = cat(mux_data_swizzledNaN_hi_hi_1, mux_data_swizzledNaN_hi_lo_1) node mux_data_swizzledNaN_1 = cat(mux_data_swizzledNaN_hi_1, mux_data_swizzledNaN_lo_1) node _mux_data_T_37 = bits(_mux_data_T_15, 63, 61) node _mux_data_T_38 = andr(_mux_data_T_37) node _mux_data_T_39 = mux(_mux_data_T_38, mux_data_swizzledNaN_1, _mux_data_T_15) connect mux.data, _mux_data_T_39 node _intValue_res_T = asSInt(in.bits.in1) wire intValue_res : SInt connect intValue_res, _intValue_res_T node intValue_smallInt = bits(in.bits.in1, 31, 0) node _intValue_T = bits(in.bits.typ, 1, 1) node _intValue_T_1 = eq(_intValue_T, UInt<1>(0h0)) when _intValue_T_1 : node _intValue_res_T_1 = bits(in.bits.typ, 0, 0) node _intValue_res_T_2 = cvt(intValue_smallInt) node _intValue_res_T_3 = asSInt(intValue_smallInt) node _intValue_res_T_4 = mux(_intValue_res_T_1, _intValue_res_T_2, _intValue_res_T_3) connect intValue_res, _intValue_res_T_4 node intValue = asUInt(intValue_res) when in.bits.wflags : inst i2fResults_i2f of INToRecFN_i64_e5_s11 node _i2fResults_i2f_io_signedIn_T = bits(in.bits.typ, 0, 0) node _i2fResults_i2f_io_signedIn_T_1 = not(_i2fResults_i2f_io_signedIn_T) connect i2fResults_i2f.io.signedIn, _i2fResults_i2f_io_signedIn_T_1 connect i2fResults_i2f.io.in, intValue connect i2fResults_i2f.io.roundingMode, in.bits.rm connect i2fResults_i2f.io.detectTininess, UInt<1>(0h1) inst i2fResults_i2f_1 of INToRecFN_i64_e8_s24 node _i2fResults_i2f_io_signedIn_T_2 = bits(in.bits.typ, 0, 0) node _i2fResults_i2f_io_signedIn_T_3 = not(_i2fResults_i2f_io_signedIn_T_2) connect i2fResults_i2f_1.io.signedIn, _i2fResults_i2f_io_signedIn_T_3 connect i2fResults_i2f_1.io.in, intValue connect i2fResults_i2f_1.io.roundingMode, in.bits.rm connect i2fResults_i2f_1.io.detectTininess, UInt<1>(0h1) node _i2fResults_maskedNaN_T = not(UInt<33>(0h10800000)) node i2fResults_maskedNaN = and(i2fResults_i2f_1.io.out, _i2fResults_maskedNaN_T) node _i2fResults_T = bits(i2fResults_i2f_1.io.out, 31, 29) node _i2fResults_T_1 = andr(_i2fResults_T) node i2fResults_1_1 = mux(_i2fResults_T_1, i2fResults_maskedNaN, i2fResults_i2f_1.io.out) inst i2fResults_i2f_2 of INToRecFN_i64_e11_s53 node _i2fResults_i2f_io_signedIn_T_4 = bits(in.bits.typ, 0, 0) node _i2fResults_i2f_io_signedIn_T_5 = not(_i2fResults_i2f_io_signedIn_T_4) connect i2fResults_i2f_2.io.signedIn, _i2fResults_i2f_io_signedIn_T_5 connect i2fResults_i2f_2.io.in, intValue connect i2fResults_i2f_2.io.roundingMode, in.bits.rm connect i2fResults_i2f_2.io.detectTininess, UInt<1>(0h1) node _i2fResults_maskedNaN_T_1 = not(UInt<65>(0h1010000000000000)) node i2fResults_maskedNaN_1 = and(i2fResults_i2f_2.io.out, _i2fResults_maskedNaN_T_1) node _i2fResults_T_2 = bits(i2fResults_i2f_2.io.out, 63, 61) node _i2fResults_T_3 = andr(_i2fResults_T_2) node i2fResults_2_1 = mux(_i2fResults_T_3, i2fResults_maskedNaN_1, i2fResults_i2f_2.io.out) node _dataPadded_T = shr(i2fResults_2_1, 17) node dataPadded_0 = cat(_dataPadded_T, i2fResults_i2f.io.out) node _dataPadded_T_1 = shr(i2fResults_2_1, 33) node dataPadded_1 = cat(_dataPadded_T_1, i2fResults_1_1) node _mux_data_T_40 = eq(in.bits.typeTagIn, UInt<1>(0h1)) node _mux_data_T_41 = mux(_mux_data_T_40, dataPadded_1, dataPadded_0) node _mux_data_T_42 = eq(in.bits.typeTagIn, UInt<2>(0h2)) node _mux_data_T_43 = mux(_mux_data_T_42, i2fResults_2_1, _mux_data_T_41) node _mux_data_T_44 = eq(in.bits.typeTagIn, UInt<2>(0h3)) node _mux_data_T_45 = mux(_mux_data_T_44, i2fResults_2_1, _mux_data_T_43) connect mux.data, _mux_data_T_45 node _mux_exc_T = eq(in.bits.typeTagIn, UInt<1>(0h1)) node _mux_exc_T_1 = mux(_mux_exc_T, i2fResults_i2f_1.io.exceptionFlags, i2fResults_i2f.io.exceptionFlags) node _mux_exc_T_2 = eq(in.bits.typeTagIn, UInt<2>(0h2)) node _mux_exc_T_3 = mux(_mux_exc_T_2, i2fResults_i2f_2.io.exceptionFlags, _mux_exc_T_1) node _mux_exc_T_4 = eq(in.bits.typeTagIn, UInt<2>(0h3)) node _mux_exc_T_5 = mux(_mux_exc_T_4, i2fResults_i2f_2.io.exceptionFlags, _mux_exc_T_3) connect mux.exc, _mux_exc_T_5 regreset io_out_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect io_out_pipe_v, in.valid reg io_out_pipe_b : { data : UInt<65>, exc : UInt<5>}, clock when in.valid : connect io_out_pipe_b, mux wire io_out_pipe_out : { valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}} connect io_out_pipe_out.valid, io_out_pipe_v connect io_out_pipe_out.bits, io_out_pipe_b connect io.out, io_out_pipe_out
module IntToFP( // @[FPU.scala:528:7] input clock, // @[FPU.scala:528:7] input reset, // @[FPU.scala:528:7] input io_in_valid, // @[FPU.scala:529:14] input [1:0] io_in_bits_typeTagIn, // @[FPU.scala:529:14] input io_in_bits_wflags, // @[FPU.scala:529:14] input [2:0] io_in_bits_rm, // @[FPU.scala:529:14] input [1:0] io_in_bits_typ, // @[FPU.scala:529:14] input [63:0] io_in_bits_in1, // @[FPU.scala:529:14] output [64:0] io_out_bits_data, // @[FPU.scala:529:14] output [4:0] io_out_bits_exc // @[FPU.scala:529:14] ); wire [64:0] _i2fResults_i2f_2_io_out; // @[FPU.scala:556:23] wire [4:0] _i2fResults_i2f_2_io_exceptionFlags; // @[FPU.scala:556:23] wire [32:0] _i2fResults_i2f_1_io_out; // @[FPU.scala:556:23] wire [4:0] _i2fResults_i2f_1_io_exceptionFlags; // @[FPU.scala:556:23] wire [16:0] _i2fResults_i2f_io_out; // @[FPU.scala:556:23] wire [4:0] _i2fResults_i2f_io_exceptionFlags; // @[FPU.scala:556:23] reg in_pipe_v; // @[Valid.scala:141:24] reg [1:0] in_pipe_b_typeTagIn; // @[Valid.scala:142:26] reg in_pipe_b_wflags; // @[Valid.scala:142:26] reg [2:0] in_pipe_b_rm; // @[Valid.scala:142:26] reg [1:0] in_pipe_b_typ; // @[Valid.scala:142:26] reg [63:0] in_pipe_b_in1; // @[Valid.scala:142:26] wire [63:0] intValue_res = in_pipe_b_typ[1] ? in_pipe_b_in1 : {{32{~(in_pipe_b_typ[0]) & in_pipe_b_in1[31]}}, in_pipe_b_in1[31:0]}; // @[Valid.scala:142:26] reg [64:0] io_out_pipe_b_data; // @[Valid.scala:142:26] reg [4:0] io_out_pipe_b_exc; // @[Valid.scala:142:26] wire _mux_exc_T = in_pipe_b_typeTagIn == 2'h1; // @[Valid.scala:142:26] wire _GEN = (&in_pipe_b_typeTagIn) | in_pipe_b_typeTagIn == 2'h2; // @[Valid.scala:142:26] wire [63:0] _mux_data_T_6 = (_GEN ? 64'h0 : _mux_exc_T ? 64'hFFFFFFFF00000000 : 64'hFFFFFFFFFFFF0000) | in_pipe_b_in1; // @[Valid.scala:142:26] wire mux_data_rawIn_isZeroExpIn = _mux_data_T_6[62:52] == 11'h0; // @[FPU.scala:431:23] wire [5:0] mux_data_rawIn_normDist = _mux_data_T_6[51] ? 6'h0 : _mux_data_T_6[50] ? 6'h1 : _mux_data_T_6[49] ? 6'h2 : _mux_data_T_6[48] ? 6'h3 : _mux_data_T_6[47] ? 6'h4 : _mux_data_T_6[46] ? 6'h5 : _mux_data_T_6[45] ? 6'h6 : _mux_data_T_6[44] ? 6'h7 : _mux_data_T_6[43] ? 6'h8 : _mux_data_T_6[42] ? 6'h9 : _mux_data_T_6[41] ? 6'hA : _mux_data_T_6[40] ? 6'hB : _mux_data_T_6[39] ? 6'hC : _mux_data_T_6[38] ? 6'hD : _mux_data_T_6[37] ? 6'hE : _mux_data_T_6[36] ? 6'hF : _mux_data_T_6[35] ? 6'h10 : _mux_data_T_6[34] ? 6'h11 : _mux_data_T_6[33] ? 6'h12 : _mux_data_T_6[32] ? 6'h13 : _mux_data_T_6[31] ? 6'h14 : _mux_data_T_6[30] ? 6'h15 : _mux_data_T_6[29] ? 6'h16 : _mux_data_T_6[28] ? 6'h17 : _mux_data_T_6[27] ? 6'h18 : _mux_data_T_6[26] ? 6'h19 : _mux_data_T_6[25] ? 6'h1A : _mux_data_T_6[24] ? 6'h1B : _mux_data_T_6[23] ? 6'h1C : _mux_data_T_6[22] ? 6'h1D : _mux_data_T_6[21] ? 6'h1E : _mux_data_T_6[20] ? 6'h1F : _mux_data_T_6[19] ? 6'h20 : _mux_data_T_6[18] ? 6'h21 : _mux_data_T_6[17] ? 6'h22 : _mux_data_T_6[16] ? 6'h23 : _mux_data_T_6[15] ? 6'h24 : _mux_data_T_6[14] ? 6'h25 : _mux_data_T_6[13] ? 6'h26 : _mux_data_T_6[12] ? 6'h27 : _mux_data_T_6[11] ? 6'h28 : _mux_data_T_6[10] ? 6'h29 : _mux_data_T_6[9] ? 6'h2A : _mux_data_T_6[8] ? 6'h2B : _mux_data_T_6[7] ? 6'h2C : _mux_data_T_6[6] ? 6'h2D : _mux_data_T_6[5] ? 6'h2E : _mux_data_T_6[4] ? 6'h2F : _mux_data_T_6[3] ? 6'h30 : _mux_data_T_6[2] ? 6'h31 : {5'h19, ~(_mux_data_T_6[1])}; // @[Mux.scala:50:70] wire [11:0] _mux_data_rawIn_adjustedExp_T_4 = (mux_data_rawIn_isZeroExpIn ? {6'h3F, ~mux_data_rawIn_normDist} : {1'h0, _mux_data_T_6[62:52]}) + {10'h100, mux_data_rawIn_isZeroExpIn ? 2'h2 : 2'h1}; // @[Mux.scala:50:70] wire [114:0] _mux_data_rawIn_subnormFract_T = {63'h0, _mux_data_T_6[51:0]} << mux_data_rawIn_normDist; // @[Mux.scala:50:70] wire [51:0] _mux_data_rawIn_out_sig_T_2 = mux_data_rawIn_isZeroExpIn ? {_mux_data_rawIn_subnormFract_T[50:0], 1'h0} : _mux_data_T_6[51:0]; // @[FPU.scala:431:23] wire [2:0] _mux_data_T_8 = mux_data_rawIn_isZeroExpIn & ~(|(_mux_data_T_6[51:0])) ? 3'h0 : _mux_data_rawIn_adjustedExp_T_4[11:9]; // @[FPU.scala:431:23, :528:7] wire _GEN_0 = _mux_data_T_8[0] | (&(_mux_data_rawIn_adjustedExp_T_4[11:10])) & (|(_mux_data_T_6[51:0])); // @[FPU.scala:431:23] wire mux_data_rawIn_isZeroExpIn_1 = _mux_data_T_6[30:23] == 8'h0; // @[FPU.scala:431:23] wire [4:0] mux_data_rawIn_normDist_1 = _mux_data_T_6[22] ? 5'h0 : _mux_data_T_6[21] ? 5'h1 : _mux_data_T_6[20] ? 5'h2 : _mux_data_T_6[19] ? 5'h3 : _mux_data_T_6[18] ? 5'h4 : _mux_data_T_6[17] ? 5'h5 : _mux_data_T_6[16] ? 5'h6 : _mux_data_T_6[15] ? 5'h7 : _mux_data_T_6[14] ? 5'h8 : _mux_data_T_6[13] ? 5'h9 : _mux_data_T_6[12] ? 5'hA : _mux_data_T_6[11] ? 5'hB : _mux_data_T_6[10] ? 5'hC : _mux_data_T_6[9] ? 5'hD : _mux_data_T_6[8] ? 5'hE : _mux_data_T_6[7] ? 5'hF : _mux_data_T_6[6] ? 5'h10 : _mux_data_T_6[5] ? 5'h11 : _mux_data_T_6[4] ? 5'h12 : _mux_data_T_6[3] ? 5'h13 : _mux_data_T_6[2] ? 5'h14 : _mux_data_T_6[1] ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [8:0] _mux_data_rawIn_adjustedExp_T_9 = (mux_data_rawIn_isZeroExpIn_1 ? {4'hF, ~mux_data_rawIn_normDist_1} : {1'h0, _mux_data_T_6[30:23]}) + {7'h20, mux_data_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1}; // @[Mux.scala:50:70] wire [53:0] _mux_data_rawIn_subnormFract_T_2 = {31'h0, _mux_data_T_6[22:0]} << mux_data_rawIn_normDist_1; // @[Mux.scala:50:70] wire [22:0] _mux_data_rawIn_out_sig_T_6 = mux_data_rawIn_isZeroExpIn_1 ? {_mux_data_rawIn_subnormFract_T_2[21:0], 1'h0} : _mux_data_T_6[22:0]; // @[FPU.scala:431:23] wire [2:0] _mux_data_T_17 = mux_data_rawIn_isZeroExpIn_1 & ~(|(_mux_data_T_6[22:0])) ? 3'h0 : _mux_data_rawIn_adjustedExp_T_9[8:6]; // @[FPU.scala:431:23, :528:7] wire _GEN_1 = _mux_data_T_17[0] | (&(_mux_data_rawIn_adjustedExp_T_9[8:7])) & (|(_mux_data_T_6[22:0])); // @[FPU.scala:431:23] wire mux_data_rawIn_isZeroExpIn_2 = _mux_data_T_6[14:10] == 5'h0; // @[FPU.scala:431:23] wire [3:0] mux_data_rawIn_normDist_2 = _mux_data_T_6[9] ? 4'h0 : _mux_data_T_6[8] ? 4'h1 : _mux_data_T_6[7] ? 4'h2 : _mux_data_T_6[6] ? 4'h3 : _mux_data_T_6[5] ? 4'h4 : _mux_data_T_6[4] ? 4'h5 : _mux_data_T_6[3] ? 4'h6 : _mux_data_T_6[2] ? 4'h7 : {3'h4, ~(_mux_data_T_6[1])}; // @[Mux.scala:50:70] wire [5:0] _mux_data_rawIn_adjustedExp_T_14 = (mux_data_rawIn_isZeroExpIn_2 ? {2'h3, ~mux_data_rawIn_normDist_2} : {1'h0, _mux_data_T_6[14:10]}) + {4'h4, mux_data_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1}; // @[Mux.scala:50:70] wire [2:0] _mux_data_T_26 = mux_data_rawIn_isZeroExpIn_2 & ~(|(_mux_data_T_6[9:0])) ? 3'h0 : _mux_data_rawIn_adjustedExp_T_14[5:3]; // @[FPU.scala:431:23, :528:7] wire [64:0] i2fResults_2_1 = ({65{_i2fResults_i2f_2_io_out[63:61] != 3'h7}} | 65'h1EFEFFFFFFFFFFFFF) & _i2fResults_i2f_2_io_out; // @[FPU.scala:249:{25,56}, :414:10, :556:23] wire [24:0] _mux_data_rawIn_subnormFract_T_4 = {15'h0, _mux_data_T_6[9:0]} << mux_data_rawIn_normDist_2; // @[Mux.scala:50:70] always @(posedge clock) begin // @[FPU.scala:528:7] if (reset) // @[FPU.scala:528:7] in_pipe_v <= 1'h0; // @[Valid.scala:141:24] else // @[FPU.scala:528:7] in_pipe_v <= io_in_valid; // @[Valid.scala:141:24] if (io_in_valid) begin // @[FPU.scala:529:14] in_pipe_b_typeTagIn <= io_in_bits_typeTagIn; // @[Valid.scala:142:26] in_pipe_b_wflags <= io_in_bits_wflags; // @[Valid.scala:142:26] in_pipe_b_rm <= io_in_bits_rm; // @[Valid.scala:142:26] in_pipe_b_typ <= io_in_bits_typ; // @[Valid.scala:142:26] in_pipe_b_in1 <= io_in_bits_in1; // @[Valid.scala:142:26] end if (in_pipe_v) begin // @[Valid.scala:141:24] io_out_pipe_b_data <= in_pipe_b_wflags ? (_GEN ? i2fResults_2_1 : _mux_exc_T ? {i2fResults_2_1[64:33], ({33{_i2fResults_i2f_1_io_out[31:29] != 3'h7}} | 33'h1EF7FFFFF) & _i2fResults_i2f_1_io_out} : {i2fResults_2_1[64:17], _i2fResults_i2f_io_out}) : {_mux_data_T_6[63], _mux_data_T_8[2:1], _GEN_0, (&{_mux_data_T_8[2:1], _GEN_0}) ? {&(_mux_data_rawIn_out_sig_T_2[51:32]), _mux_data_rawIn_adjustedExp_T_4[7:1], _mux_data_T_17[2], _mux_data_rawIn_out_sig_T_2[51:32], _mux_data_T_6[31], _mux_data_T_17[1], _GEN_1, (&{_mux_data_T_17[2:1], _GEN_1}) ? {&(_mux_data_rawIn_out_sig_T_6[22:16]), _mux_data_rawIn_adjustedExp_T_9[4:1], _mux_data_T_26[2], _mux_data_rawIn_out_sig_T_6[22:16], _mux_data_T_6[15], _mux_data_T_26[1], _mux_data_T_26[0] | (&(_mux_data_rawIn_adjustedExp_T_14[5:4])) & (|(_mux_data_T_6[9:0])), _mux_data_rawIn_adjustedExp_T_14[2:0], mux_data_rawIn_isZeroExpIn_2 ? {_mux_data_rawIn_subnormFract_T_4[8:0], 1'h0} : _mux_data_T_6[9:0]} : {_mux_data_rawIn_adjustedExp_T_9[5:0], _mux_data_rawIn_out_sig_T_6}} : {_mux_data_rawIn_adjustedExp_T_4[8:0], _mux_data_rawIn_out_sig_T_2}}; // @[Valid.scala:142:26] io_out_pipe_b_exc <= in_pipe_b_wflags ? (_GEN ? _i2fResults_i2f_2_io_exceptionFlags : _mux_exc_T ? _i2fResults_i2f_1_io_exceptionFlags : _i2fResults_i2f_io_exceptionFlags) : 5'h0; // @[Valid.scala:142:26] end always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module TLFragmenter_1 : input clock : Clock input reset : Reset output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonIn.d.bits.corrupt invalidate anonIn.d.bits.data invalidate anonIn.d.bits.denied invalidate anonIn.d.bits.sink invalidate anonIn.d.bits.source invalidate anonIn.d.bits.size invalidate anonIn.d.bits.param invalidate anonIn.d.bits.opcode invalidate anonIn.d.valid invalidate anonIn.d.ready invalidate anonIn.a.bits.corrupt invalidate anonIn.a.bits.data invalidate anonIn.a.bits.mask invalidate anonIn.a.bits.address invalidate anonIn.a.bits.source invalidate anonIn.a.bits.size invalidate anonIn.a.bits.param invalidate anonIn.a.bits.opcode invalidate anonIn.a.valid invalidate anonIn.a.ready inst monitor of TLMonitor_61 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt connect monitor.io.in.d.bits.data, anonIn.d.bits.data connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink connect monitor.io.in.d.bits.source, anonIn.d.bits.source connect monitor.io.in.d.bits.size, anonIn.d.bits.size connect monitor.io.in.d.bits.param, anonIn.d.bits.param connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode connect monitor.io.in.d.valid, anonIn.d.valid connect monitor.io.in.d.ready, anonIn.d.ready connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt connect monitor.io.in.a.bits.data, anonIn.a.bits.data connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask connect monitor.io.in.a.bits.address, anonIn.a.bits.address connect monitor.io.in.a.bits.source, anonIn.a.bits.source connect monitor.io.in.a.bits.size, anonIn.a.bits.size connect monitor.io.in.a.bits.param, anonIn.a.bits.param connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode connect monitor.io.in.a.valid, anonIn.a.valid connect monitor.io.in.a.ready, anonIn.a.ready wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonOut.d.bits.corrupt invalidate anonOut.d.bits.data invalidate anonOut.d.bits.denied invalidate anonOut.d.bits.sink invalidate anonOut.d.bits.source invalidate anonOut.d.bits.size invalidate anonOut.d.bits.param invalidate anonOut.d.bits.opcode invalidate anonOut.d.valid invalidate anonOut.d.ready invalidate anonOut.a.bits.corrupt invalidate anonOut.a.bits.data invalidate anonOut.a.bits.mask invalidate anonOut.a.bits.address invalidate anonOut.a.bits.source invalidate anonOut.a.bits.size invalidate anonOut.a.bits.param invalidate anonOut.a.bits.opcode invalidate anonOut.a.valid invalidate anonOut.a.ready connect auto.anon_out, anonOut connect anonIn, auto.anon_in regreset acknum : UInt<3>, clock, reset, UInt<3>(0h0) reg dOrig : UInt, clock regreset dToggle : UInt<1>, clock, reset, UInt<1>(0h0) node dFragnum = bits(anonOut.d.bits.source, 2, 0) node dFirst = eq(acknum, UInt<1>(0h0)) node dLast = eq(dFragnum, UInt<1>(0h0)) node dsizeOH_shiftAmount = bits(anonOut.d.bits.size, 1, 0) node _dsizeOH_T = dshl(UInt<1>(0h1), dsizeOH_shiftAmount) node dsizeOH = bits(_dsizeOH_T, 3, 0) node _dsizeOH1_T = dshl(UInt<3>(0h7), anonOut.d.bits.size) node _dsizeOH1_T_1 = bits(_dsizeOH1_T, 2, 0) node dsizeOH1 = not(_dsizeOH1_T_1) node dHasData = bits(anonOut.d.bits.opcode, 0, 0) node acknum_fragment = shl(dFragnum, 0) node acknum_size = shr(dsizeOH1, 3) node _T = eq(anonOut.d.valid, UInt<1>(0h0)) node _T_1 = and(acknum_fragment, acknum_size) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = or(_T, _T_2) node _T_4 = asUInt(reset) node _T_5 = eq(_T_4, UInt<1>(0h0)) when _T_5 : node _T_6 = eq(_T_3, UInt<1>(0h0)) when _T_6 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:214 assert (!out.d.valid || (acknum_fragment & acknum_size) === 0.U)\n") : printf assert(clock, _T_3, UInt<1>(0h1), "") : assert node _dFirst_acknum_T = mux(dHasData, acknum_size, UInt<1>(0h0)) node dFirst_acknum = or(acknum_fragment, _dFirst_acknum_T) node _ack_decrement_T = shr(dsizeOH, 3) node ack_decrement = mux(dHasData, UInt<1>(0h1), _ack_decrement_T) node _dFirst_size_T = shl(dFragnum, 3) node _dFirst_size_T_1 = or(_dFirst_size_T, dsizeOH1) node _dFirst_size_T_2 = shl(_dFirst_size_T_1, 1) node _dFirst_size_T_3 = or(_dFirst_size_T_2, UInt<1>(0h1)) node _dFirst_size_T_4 = cat(UInt<1>(0h0), _dFirst_size_T_1) node _dFirst_size_T_5 = not(_dFirst_size_T_4) node _dFirst_size_T_6 = and(_dFirst_size_T_3, _dFirst_size_T_5) node dFirst_size_hi = bits(_dFirst_size_T_6, 6, 4) node dFirst_size_lo = bits(_dFirst_size_T_6, 3, 0) node _dFirst_size_T_7 = orr(dFirst_size_hi) node _dFirst_size_T_8 = or(dFirst_size_hi, dFirst_size_lo) node dFirst_size_hi_1 = bits(_dFirst_size_T_8, 3, 2) node dFirst_size_lo_1 = bits(_dFirst_size_T_8, 1, 0) node _dFirst_size_T_9 = orr(dFirst_size_hi_1) node _dFirst_size_T_10 = or(dFirst_size_hi_1, dFirst_size_lo_1) node _dFirst_size_T_11 = bits(_dFirst_size_T_10, 1, 1) node _dFirst_size_T_12 = cat(_dFirst_size_T_9, _dFirst_size_T_11) node dFirst_size = cat(_dFirst_size_T_7, _dFirst_size_T_12) node _T_7 = and(anonOut.d.ready, anonOut.d.valid) when _T_7 : node _acknum_T = sub(acknum, ack_decrement) node _acknum_T_1 = tail(_acknum_T, 1) node _acknum_T_2 = mux(dFirst, dFirst_acknum, _acknum_T_1) connect acknum, _acknum_T_2 when dFirst : connect dOrig, dFirst_size node _dToggle_T = bits(anonOut.d.bits.source, 3, 3) connect dToggle, _dToggle_T node _drop_T = eq(dHasData, UInt<1>(0h0)) node _drop_T_1 = mux(UInt<1>(0h0), dFirst, dLast) node _drop_T_2 = eq(_drop_T_1, UInt<1>(0h0)) node drop = and(_drop_T, _drop_T_2) node _anonOut_d_ready_T = or(anonIn.d.ready, drop) connect anonOut.d.ready, _anonOut_d_ready_T node _anonIn_d_valid_T = eq(drop, UInt<1>(0h0)) node _anonIn_d_valid_T_1 = and(anonOut.d.valid, _anonIn_d_valid_T) connect anonIn.d.valid, _anonIn_d_valid_T_1 connect anonIn.d.bits.corrupt, anonOut.d.bits.corrupt connect anonIn.d.bits.data, anonOut.d.bits.data connect anonIn.d.bits.denied, anonOut.d.bits.denied connect anonIn.d.bits.sink, anonOut.d.bits.sink connect anonIn.d.bits.source, anonOut.d.bits.source connect anonIn.d.bits.size, anonOut.d.bits.size connect anonIn.d.bits.param, anonOut.d.bits.param connect anonIn.d.bits.opcode, anonOut.d.bits.opcode node _anonIn_d_bits_source_T = shr(anonOut.d.bits.source, 4) connect anonIn.d.bits.source, _anonIn_d_bits_source_T node _anonIn_d_bits_size_T = mux(dFirst, dFirst_size, dOrig) connect anonIn.d.bits.size, _anonIn_d_bits_size_T inst repeater of Repeater_TLBundleA_a14d64s7k1z3u connect repeater.clock, clock connect repeater.reset, reset connect repeater.io.enq, anonIn.a node _find_T = xor(repeater.io.deq.bits.address, UInt<1>(0h0)) node _find_T_1 = cvt(_find_T) node _find_T_2 = and(_find_T_1, asSInt(UInt<1>(0h0))) node _find_T_3 = asSInt(_find_T_2) node _find_T_4 = eq(_find_T_3, asSInt(UInt<1>(0h0))) wire find : UInt<1>[1] connect find[0], _find_T_4 node _limit_T = eq(UInt<1>(0h0), repeater.io.deq.bits.opcode) node _limit_T_1 = mux(_limit_T, UInt<2>(0h3), UInt<2>(0h3)) node _limit_T_2 = eq(UInt<1>(0h1), repeater.io.deq.bits.opcode) node _limit_T_3 = mux(_limit_T_2, UInt<2>(0h3), _limit_T_1) node _limit_T_4 = eq(UInt<2>(0h2), repeater.io.deq.bits.opcode) node _limit_T_5 = mux(_limit_T_4, UInt<2>(0h3), _limit_T_3) node _limit_T_6 = eq(UInt<2>(0h3), repeater.io.deq.bits.opcode) node _limit_T_7 = mux(_limit_T_6, UInt<2>(0h3), _limit_T_5) node _limit_T_8 = eq(UInt<3>(0h4), repeater.io.deq.bits.opcode) node _limit_T_9 = mux(_limit_T_8, UInt<2>(0h3), _limit_T_7) node _limit_T_10 = eq(UInt<3>(0h5), repeater.io.deq.bits.opcode) node limit = mux(_limit_T_10, UInt<2>(0h3), _limit_T_9) node _aFrag_T = gt(repeater.io.deq.bits.size, limit) node aFrag = mux(_aFrag_T, limit, repeater.io.deq.bits.size) node _aOrigOH1_T = dshl(UInt<6>(0h3f), repeater.io.deq.bits.size) node _aOrigOH1_T_1 = bits(_aOrigOH1_T, 5, 0) node aOrigOH1 = not(_aOrigOH1_T_1) node _aFragOH1_T = dshl(UInt<3>(0h7), aFrag) node _aFragOH1_T_1 = bits(_aFragOH1_T, 2, 0) node aFragOH1 = not(_aFragOH1_T_1) node _aHasData_opdata_T = bits(repeater.io.deq.bits.opcode, 2, 2) node aHasData = eq(_aHasData_opdata_T, UInt<1>(0h0)) node aMask = mux(aHasData, UInt<1>(0h0), aFragOH1) regreset gennum : UInt<3>, clock, reset, UInt<3>(0h0) node aFirst = eq(gennum, UInt<1>(0h0)) node _old_gennum1_T = shr(aOrigOH1, 3) node _old_gennum1_T_1 = sub(gennum, UInt<1>(0h1)) node _old_gennum1_T_2 = tail(_old_gennum1_T_1, 1) node old_gennum1 = mux(aFirst, _old_gennum1_T, _old_gennum1_T_2) node _new_gennum_T = not(old_gennum1) node _new_gennum_T_1 = shr(aMask, 3) node _new_gennum_T_2 = or(_new_gennum_T, _new_gennum_T_1) node new_gennum = not(_new_gennum_T_2) node _aFragnum_T = shr(old_gennum1, 0) node _aFragnum_T_1 = not(_aFragnum_T) node _aFragnum_T_2 = shr(aFragOH1, 3) node _aFragnum_T_3 = or(_aFragnum_T_1, _aFragnum_T_2) node aFragnum = not(_aFragnum_T_3) node aLast = eq(aFragnum, UInt<1>(0h0)) reg aToggle_r : UInt<1>, clock when aFirst : connect aToggle_r, dToggle node _aToggle_T = mux(aFirst, dToggle, aToggle_r) node aToggle = eq(_aToggle_T, UInt<1>(0h0)) node _T_8 = and(anonOut.a.ready, anonOut.a.valid) when _T_8 : connect gennum, new_gennum node _repeater_io_repeat_T = eq(aHasData, UInt<1>(0h0)) node _repeater_io_repeat_T_1 = neq(aFragnum, UInt<1>(0h0)) node _repeater_io_repeat_T_2 = and(_repeater_io_repeat_T, _repeater_io_repeat_T_1) connect repeater.io.repeat, _repeater_io_repeat_T_2 connect anonOut.a.bits, repeater.io.deq.bits connect anonOut.a.valid, repeater.io.deq.valid connect repeater.io.deq.ready, anonOut.a.ready node _anonOut_a_bits_address_T = shl(old_gennum1, 3) node _anonOut_a_bits_address_T_1 = not(aOrigOH1) node _anonOut_a_bits_address_T_2 = or(_anonOut_a_bits_address_T, _anonOut_a_bits_address_T_1) node _anonOut_a_bits_address_T_3 = or(_anonOut_a_bits_address_T_2, aFragOH1) node _anonOut_a_bits_address_T_4 = or(_anonOut_a_bits_address_T_3, UInt<3>(0h7)) node _anonOut_a_bits_address_T_5 = not(_anonOut_a_bits_address_T_4) node _anonOut_a_bits_address_T_6 = or(repeater.io.deq.bits.address, _anonOut_a_bits_address_T_5) connect anonOut.a.bits.address, _anonOut_a_bits_address_T_6 node anonOut_a_bits_source_hi = cat(repeater.io.deq.bits.source, aToggle) node _anonOut_a_bits_source_T = cat(anonOut_a_bits_source_hi, aFragnum) connect anonOut.a.bits.source, _anonOut_a_bits_source_T connect anonOut.a.bits.size, aFrag node _T_9 = eq(repeater.io.full, UInt<1>(0h0)) node _T_10 = eq(aHasData, UInt<1>(0h0)) node _T_11 = or(_T_9, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:321 assert (!repeater.io.full || !aHasData)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 connect anonOut.a.bits.data, anonIn.a.bits.data node _T_15 = eq(repeater.io.full, UInt<1>(0h0)) node _T_16 = eq(repeater.io.deq.bits.mask, UInt<8>(0hff)) node _T_17 = or(_T_15, _T_16) node _T_18 = asUInt(reset) node _T_19 = eq(_T_18, UInt<1>(0h0)) when _T_19 : node _T_20 = eq(_T_17, UInt<1>(0h0)) when _T_20 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:324 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n") : printf_2 assert(clock, _T_17, UInt<1>(0h1), "") : assert_2 node _anonOut_a_bits_mask_T = mux(repeater.io.full, UInt<8>(0hff), anonIn.a.bits.mask) connect anonOut.a.bits.mask, _anonOut_a_bits_mask_T wire anonOut_a_bits_user_out : { } wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<14>(0h0) connect _WIRE.bits.source, UInt<7>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<14>(0h0) connect _WIRE_2.bits.source, UInt<7>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<14>(0h0) connect _WIRE_6.bits.source, UInt<11>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<14>(0h0) connect _WIRE_8.bits.source, UInt<11>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_10.bits.sink, UInt<1>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0)
module TLFragmenter_1( // @[Fragmenter.scala:92:9] input clock, // @[Fragmenter.scala:92:9] input reset, // @[Fragmenter.scala:92:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [13:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [13:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire _repeater_io_full; // @[Fragmenter.scala:274:30] wire _repeater_io_enq_ready; // @[Fragmenter.scala:274:30] wire _repeater_io_deq_valid; // @[Fragmenter.scala:274:30] wire [2:0] _repeater_io_deq_bits_opcode; // @[Fragmenter.scala:274:30] wire [2:0] _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30] wire [6:0] _repeater_io_deq_bits_source; // @[Fragmenter.scala:274:30] wire [13:0] _repeater_io_deq_bits_address; // @[Fragmenter.scala:274:30] wire [7:0] _repeater_io_deq_bits_mask; // @[Fragmenter.scala:274:30] reg [2:0] acknum; // @[Fragmenter.scala:201:29] reg [2:0] dOrig; // @[Fragmenter.scala:202:24] reg dToggle; // @[Fragmenter.scala:203:30] wire dFirst = acknum == 3'h0; // @[Fragmenter.scala:201:29, :205:29] wire [5:0] _dsizeOH1_T = 6'h7 << auto_anon_out_d_bits_size; // @[package.scala:243:71] wire [2:0] _GEN = ~(auto_anon_out_d_bits_source[2:0]); // @[package.scala:241:49] wire [2:0] dFirst_size_hi = auto_anon_out_d_bits_source[2:0] & {1'h1, _GEN[2:1]}; // @[OneHot.scala:30:18] wire [2:0] _dFirst_size_T_8 = {1'h0, dFirst_size_hi[2:1]} | ~(_dsizeOH1_T[2:0]) & {_GEN[0], _dsizeOH1_T[2:1]}; // @[OneHot.scala:30:18, :31:18, :32:28] wire [2:0] dFirst_size = {|dFirst_size_hi, |(_dFirst_size_T_8[2:1]), _dFirst_size_T_8[2] | _dFirst_size_T_8[0]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire drop = ~(auto_anon_out_d_bits_opcode[0]) & (|(auto_anon_out_d_bits_source[2:0])); // @[Fragmenter.scala:204:41, :206:30, :234:{20,30}] wire anonOut_d_ready = auto_anon_in_d_ready | drop; // @[Fragmenter.scala:234:30, :235:35] wire anonIn_d_valid = auto_anon_out_d_valid & ~drop; // @[Fragmenter.scala:234:30, :236:{36,39}] wire [2:0] anonIn_d_bits_size = dFirst ? dFirst_size : dOrig; // @[OneHot.scala:32:10] wire [12:0] _aOrigOH1_T = 13'h3F << _repeater_io_deq_bits_size; // @[package.scala:243:71] reg [2:0] gennum; // @[Fragmenter.scala:303:29] wire aFirst = gennum == 3'h0; // @[Fragmenter.scala:303:29, :304:29] wire [2:0] aFragnum = aFirst ? ~(_aOrigOH1_T[5:3]) : gennum - 3'h1; // @[package.scala:243:{46,71,76}] reg aToggle_r; // @[Fragmenter.scala:309:54]
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_210 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_227 connect io_out_sink_extend.clock, clock connect io_out_sink_extend.reset, reset connect io_out_sink_extend.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_extend.io.q connect io.out, _io_out_WIRE
module AsyncValidSync_210( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_227 io_out_sink_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncQueueSink_Phit_9 : input clock : Clock input reset : Reset output io : { deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}, flip async : { mem : { phit : UInt<32>}[8], flip ridx : UInt<4>, widx : UInt<4>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}} wire source_ready : UInt<1> connect source_ready, UInt<1>(0h1) node _ridx_T = asAsyncReset(reset) node _ridx_T_1 = and(io.deq.ready, io.deq.valid) node _ridx_T_2 = eq(source_ready, UInt<1>(0h0)) wire ridx_incremented : UInt<4> regreset ridx_ridx_bin : UInt, clock, _ridx_T, UInt<1>(0h0) connect ridx_ridx_bin, ridx_incremented node _ridx_incremented_T = add(ridx_ridx_bin, _ridx_T_1) node _ridx_incremented_T_1 = tail(_ridx_incremented_T, 1) node _ridx_incremented_T_2 = mux(_ridx_T_2, UInt<1>(0h0), _ridx_incremented_T_1) connect ridx_incremented, _ridx_incremented_T_2 node _ridx_T_3 = shr(ridx_incremented, 1) node ridx = xor(ridx_incremented, _ridx_T_3) inst widx_widx_gray of AsyncResetSynchronizerShiftReg_w4_d3_i0_19 connect widx_widx_gray.clock, clock connect widx_widx_gray.reset, reset connect widx_widx_gray.io.d, io.async.widx wire widx : UInt<4> connect widx, widx_widx_gray.io.q node _valid_T = neq(ridx, widx) node valid = and(source_ready, _valid_T) node _index_T = bits(ridx, 2, 0) node _index_T_1 = bits(ridx, 3, 3) node _index_T_2 = shl(_index_T_1, 2) node index = xor(_index_T, _index_T_2) inst io_deq_bits_deq_bits_reg of ClockCrossingReg_w32_9 connect io_deq_bits_deq_bits_reg.clock, clock connect io_deq_bits_deq_bits_reg.reset, reset connect io_deq_bits_deq_bits_reg.io.d, io.async.mem[index].phit connect io_deq_bits_deq_bits_reg.io.en, valid wire _io_deq_bits_WIRE : { phit : UInt<32>} wire _io_deq_bits_WIRE_1 : UInt<32> connect _io_deq_bits_WIRE_1, io_deq_bits_deq_bits_reg.io.q node _io_deq_bits_T = bits(_io_deq_bits_WIRE_1, 31, 0) connect _io_deq_bits_WIRE.phit, _io_deq_bits_T connect io.deq.bits, _io_deq_bits_WIRE node _valid_reg_T = asAsyncReset(reset) regreset valid_reg : UInt<1>, clock, _valid_reg_T, UInt<1>(0h0) connect valid_reg, valid node _io_deq_valid_T = and(valid_reg, source_ready) connect io.deq.valid, _io_deq_valid_T node _ridx_reg_T = asAsyncReset(reset) regreset ridx_gray : UInt, clock, _ridx_reg_T, UInt<1>(0h0) connect ridx_gray, ridx connect io.async.ridx, ridx_gray inst sink_valid_0 of AsyncValidSync_100 inst sink_valid_1 of AsyncValidSync_101 inst source_extend of AsyncValidSync_102 inst source_valid of AsyncValidSync_103 node _sink_valid_0_reset_T = asUInt(reset) node _sink_valid_0_reset_T_1 = eq(io.async.safe.source_reset_n, UInt<1>(0h0)) node _sink_valid_0_reset_T_2 = or(_sink_valid_0_reset_T, _sink_valid_0_reset_T_1) node _sink_valid_0_reset_T_3 = asAsyncReset(_sink_valid_0_reset_T_2) connect sink_valid_0.reset, _sink_valid_0_reset_T_3 node _sink_valid_1_reset_T = asUInt(reset) node _sink_valid_1_reset_T_1 = eq(io.async.safe.source_reset_n, UInt<1>(0h0)) node _sink_valid_1_reset_T_2 = or(_sink_valid_1_reset_T, _sink_valid_1_reset_T_1) node _sink_valid_1_reset_T_3 = asAsyncReset(_sink_valid_1_reset_T_2) connect sink_valid_1.reset, _sink_valid_1_reset_T_3 node _source_extend_reset_T = asUInt(reset) node _source_extend_reset_T_1 = eq(io.async.safe.source_reset_n, UInt<1>(0h0)) node _source_extend_reset_T_2 = or(_source_extend_reset_T, _source_extend_reset_T_1) node _source_extend_reset_T_3 = asAsyncReset(_source_extend_reset_T_2) connect source_extend.reset, _source_extend_reset_T_3 node _source_valid_reset_T = asAsyncReset(reset) connect source_valid.reset, _source_valid_reset_T connect sink_valid_0.clock, clock connect sink_valid_1.clock, clock connect source_extend.clock, clock connect source_valid.clock, clock connect sink_valid_0.io.in, UInt<1>(0h1) connect sink_valid_1.io.in, sink_valid_0.io.out connect io.async.safe.ridx_valid, sink_valid_1.io.out connect source_extend.io.in, io.async.safe.widx_valid connect source_valid.io.in, source_extend.io.out connect source_ready, source_valid.io.out node _io_async_safe_sink_reset_n_T = asUInt(reset) node _io_async_safe_sink_reset_n_T_1 = eq(_io_async_safe_sink_reset_n_T, UInt<1>(0h0)) connect io.async.safe.sink_reset_n, _io_async_safe_sink_reset_n_T_1
module AsyncQueueSink_Phit_9( // @[AsyncQueue.scala:136:7] input clock, // @[AsyncQueue.scala:136:7] input reset, // @[AsyncQueue.scala:136:7] input io_deq_ready, // @[AsyncQueue.scala:139:14] output io_deq_valid, // @[AsyncQueue.scala:139:14] output [31:0] io_deq_bits_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_0_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_1_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_2_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_3_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_4_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_5_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_6_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_7_phit, // @[AsyncQueue.scala:139:14] output [3:0] io_async_ridx, // @[AsyncQueue.scala:139:14] input [3:0] io_async_widx, // @[AsyncQueue.scala:139:14] output io_async_safe_ridx_valid, // @[AsyncQueue.scala:139:14] input io_async_safe_widx_valid, // @[AsyncQueue.scala:139:14] input io_async_safe_source_reset_n, // @[AsyncQueue.scala:139:14] output io_async_safe_sink_reset_n // @[AsyncQueue.scala:139:14] ); wire _source_extend_io_out; // @[AsyncQueue.scala:175:31] wire _sink_valid_0_io_out; // @[AsyncQueue.scala:172:33] wire io_deq_ready_0 = io_deq_ready; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_0_phit_0 = io_async_mem_0_phit; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_1_phit_0 = io_async_mem_1_phit; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_2_phit_0 = io_async_mem_2_phit; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_3_phit_0 = io_async_mem_3_phit; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_4_phit_0 = io_async_mem_4_phit; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_5_phit_0 = io_async_mem_5_phit; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_6_phit_0 = io_async_mem_6_phit; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_7_phit_0 = io_async_mem_7_phit; // @[AsyncQueue.scala:136:7] wire [3:0] io_async_widx_0 = io_async_widx; // @[AsyncQueue.scala:136:7] wire io_async_safe_widx_valid_0 = io_async_safe_widx_valid; // @[AsyncQueue.scala:136:7] wire io_async_safe_source_reset_n_0 = io_async_safe_source_reset_n; // @[AsyncQueue.scala:136:7] wire _ridx_T = reset; // @[AsyncQueue.scala:148:30] wire _valid_reg_T = reset; // @[AsyncQueue.scala:165:35] wire _ridx_reg_T = reset; // @[AsyncQueue.scala:168:34] wire _sink_valid_0_reset_T = reset; // @[AsyncQueue.scala:177:35] wire _sink_valid_1_reset_T = reset; // @[AsyncQueue.scala:178:35] wire _source_extend_reset_T = reset; // @[AsyncQueue.scala:179:35] wire _source_valid_reset_T = reset; // @[AsyncQueue.scala:180:34] wire _io_async_safe_sink_reset_n_T = reset; // @[AsyncQueue.scala:193:32] wire _io_deq_valid_T; // @[AsyncQueue.scala:166:29] wire [31:0] _io_deq_bits_WIRE_phit; // @[SynchronizerReg.scala:211:26] wire _io_async_safe_sink_reset_n_T_1; // @[AsyncQueue.scala:193:25] wire [31:0] io_deq_bits_phit_0; // @[AsyncQueue.scala:136:7] wire io_deq_valid_0; // @[AsyncQueue.scala:136:7] wire io_async_safe_ridx_valid_0; // @[AsyncQueue.scala:136:7] wire io_async_safe_sink_reset_n_0; // @[AsyncQueue.scala:136:7] wire [3:0] io_async_ridx_0; // @[AsyncQueue.scala:136:7] wire source_ready; // @[AsyncQueue.scala:147:30] wire _ridx_T_1 = io_deq_ready_0 & io_deq_valid_0; // @[Decoupled.scala:51:35] wire _ridx_T_2 = ~source_ready; // @[AsyncQueue.scala:147:30, :148:77] wire [3:0] _ridx_incremented_T_2; // @[AsyncQueue.scala:53:23] wire [3:0] ridx_incremented; // @[AsyncQueue.scala:51:27] reg [3:0] ridx_ridx_bin; // @[AsyncQueue.scala:52:25] wire [4:0] _ridx_incremented_T = {1'h0, ridx_ridx_bin} + {4'h0, _ridx_T_1}; // @[Decoupled.scala:51:35] wire [3:0] _ridx_incremented_T_1 = _ridx_incremented_T[3:0]; // @[AsyncQueue.scala:53:43] assign _ridx_incremented_T_2 = _ridx_T_2 ? 4'h0 : _ridx_incremented_T_1; // @[AsyncQueue.scala:52:25, :53:{23,43}, :148:77] assign ridx_incremented = _ridx_incremented_T_2; // @[AsyncQueue.scala:51:27, :53:23] wire [2:0] _ridx_T_3 = ridx_incremented[3:1]; // @[AsyncQueue.scala:51:27, :54:32] wire [3:0] ridx = {ridx_incremented[3], ridx_incremented[2:0] ^ _ridx_T_3}; // @[AsyncQueue.scala:51:27, :54:{17,32}] wire [3:0] widx; // @[ShiftReg.scala:48:24] wire _valid_T = ridx != widx; // @[ShiftReg.scala:48:24] wire valid = source_ready & _valid_T; // @[AsyncQueue.scala:147:30, :150:{28,36}] wire [2:0] _index_T = ridx[2:0]; // @[AsyncQueue.scala:54:17, :156:43] wire _index_T_1 = ridx[3]; // @[AsyncQueue.scala:54:17, :156:62] wire [2:0] _index_T_2 = {_index_T_1, 2'h0}; // @[AsyncQueue.scala:156:{62,75}] wire [2:0] index = _index_T ^ _index_T_2; // @[AsyncQueue.scala:156:{43,55,75}] wire [7:0][31:0] _GEN = {{io_async_mem_7_phit_0}, {io_async_mem_6_phit_0}, {io_async_mem_5_phit_0}, {io_async_mem_4_phit_0}, {io_async_mem_3_phit_0}, {io_async_mem_2_phit_0}, {io_async_mem_1_phit_0}, {io_async_mem_0_phit_0}}; // @[SynchronizerReg.scala:209:18] wire [31:0] _io_deq_bits_T; // @[SynchronizerReg.scala:211:26] assign io_deq_bits_phit_0 = _io_deq_bits_WIRE_phit; // @[SynchronizerReg.scala:211:26] wire [31:0] _io_deq_bits_WIRE_1; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_T = _io_deq_bits_WIRE_1; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_WIRE_phit = _io_deq_bits_T; // @[SynchronizerReg.scala:211:26] reg valid_reg; // @[AsyncQueue.scala:165:56] assign _io_deq_valid_T = valid_reg & source_ready; // @[AsyncQueue.scala:147:30, :165:56, :166:29] assign io_deq_valid_0 = _io_deq_valid_T; // @[AsyncQueue.scala:136:7, :166:29] reg [3:0] ridx_gray; // @[AsyncQueue.scala:168:55] assign io_async_ridx_0 = ridx_gray; // @[AsyncQueue.scala:136:7, :168:55] wire _sink_valid_0_reset_T_1 = ~io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:136:7, :177:45] wire _sink_valid_0_reset_T_2 = _sink_valid_0_reset_T | _sink_valid_0_reset_T_1; // @[AsyncQueue.scala:177:{35,42,45}] wire _sink_valid_0_reset_T_3 = _sink_valid_0_reset_T_2; // @[AsyncQueue.scala:177:{42,66}] wire _sink_valid_1_reset_T_1 = ~io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:136:7, :177:45, :178:45] wire _sink_valid_1_reset_T_2 = _sink_valid_1_reset_T | _sink_valid_1_reset_T_1; // @[AsyncQueue.scala:178:{35,42,45}] wire _sink_valid_1_reset_T_3 = _sink_valid_1_reset_T_2; // @[AsyncQueue.scala:178:{42,66}] wire _source_extend_reset_T_1 = ~io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:136:7, :177:45, :179:45] wire _source_extend_reset_T_2 = _source_extend_reset_T | _source_extend_reset_T_1; // @[AsyncQueue.scala:179:{35,42,45}] wire _source_extend_reset_T_3 = _source_extend_reset_T_2; // @[AsyncQueue.scala:179:{42,66}] assign _io_async_safe_sink_reset_n_T_1 = ~_io_async_safe_sink_reset_n_T; // @[AsyncQueue.scala:193:{25,32}] assign io_async_safe_sink_reset_n_0 = _io_async_safe_sink_reset_n_T_1; // @[AsyncQueue.scala:136:7, :193:25] always @(posedge clock or posedge _ridx_T) begin // @[AsyncQueue.scala:136:7, :148:30] if (_ridx_T) // @[AsyncQueue.scala:136:7, :148:30] ridx_ridx_bin <= 4'h0; // @[AsyncQueue.scala:52:25] else // @[AsyncQueue.scala:136:7] ridx_ridx_bin <= ridx_incremented; // @[AsyncQueue.scala:51:27, :52:25] always @(posedge, posedge) always @(posedge clock or posedge _valid_reg_T) begin // @[AsyncQueue.scala:136:7, :165:35] if (_valid_reg_T) // @[AsyncQueue.scala:136:7, :165:35] valid_reg <= 1'h0; // @[AsyncQueue.scala:165:56] else // @[AsyncQueue.scala:136:7] valid_reg <= valid; // @[AsyncQueue.scala:150:28, :165:56] always @(posedge, posedge) always @(posedge clock or posedge _ridx_reg_T) begin // @[AsyncQueue.scala:136:7, :168:34] if (_ridx_reg_T) // @[AsyncQueue.scala:136:7, :168:34] ridx_gray <= 4'h0; // @[AsyncQueue.scala:52:25, :168:55] else // @[AsyncQueue.scala:136:7] ridx_gray <= ridx; // @[AsyncQueue.scala:54:17, :168:55] always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_76 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_76 connect io_out_sink_valid_0.clock, clock connect io_out_sink_valid_0.reset, reset connect io_out_sink_valid_0.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid_0.io.q connect io.out, _io_out_WIRE
module AsyncValidSync_76( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_76 io_out_sink_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_postMul_e8_s24_54 : output io : { flip fromPreMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}, flip mulAddResult : UInt<49>, flip roundingMode : UInt<3>, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}} node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node opSignC = xor(io.fromPreMul.signProd, io.fromPreMul.doSubMags) node _sigSum_T = bits(io.mulAddResult, 48, 48) node _sigSum_T_1 = add(io.fromPreMul.highAlignedSigC, UInt<1>(0h1)) node _sigSum_T_2 = tail(_sigSum_T_1, 1) node _sigSum_T_3 = mux(_sigSum_T, _sigSum_T_2, io.fromPreMul.highAlignedSigC) node _sigSum_T_4 = bits(io.mulAddResult, 47, 0) node sigSum_hi = cat(_sigSum_T_3, _sigSum_T_4) node sigSum = cat(sigSum_hi, io.fromPreMul.bit0AlignedSigC) node _CDom_sExp_T = cvt(io.fromPreMul.doSubMags) node _CDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _CDom_sExp_T) node _CDom_sExp_T_2 = tail(_CDom_sExp_T_1, 1) node CDom_sExp = asSInt(_CDom_sExp_T_2) node _CDom_absSigSum_T = bits(sigSum, 74, 25) node _CDom_absSigSum_T_1 = not(_CDom_absSigSum_T) node _CDom_absSigSum_T_2 = bits(io.fromPreMul.highAlignedSigC, 25, 24) node _CDom_absSigSum_T_3 = cat(UInt<1>(0h0), _CDom_absSigSum_T_2) node _CDom_absSigSum_T_4 = bits(sigSum, 72, 26) node _CDom_absSigSum_T_5 = cat(_CDom_absSigSum_T_3, _CDom_absSigSum_T_4) node CDom_absSigSum = mux(io.fromPreMul.doSubMags, _CDom_absSigSum_T_1, _CDom_absSigSum_T_5) node _CDom_absSigSumExtra_T = bits(sigSum, 24, 1) node _CDom_absSigSumExtra_T_1 = not(_CDom_absSigSumExtra_T) node _CDom_absSigSumExtra_T_2 = orr(_CDom_absSigSumExtra_T_1) node _CDom_absSigSumExtra_T_3 = bits(sigSum, 25, 1) node _CDom_absSigSumExtra_T_4 = orr(_CDom_absSigSumExtra_T_3) node CDom_absSigSumExtra = mux(io.fromPreMul.doSubMags, _CDom_absSigSumExtra_T_2, _CDom_absSigSumExtra_T_4) node _CDom_mainSig_T = dshl(CDom_absSigSum, io.fromPreMul.CDom_CAlignDist) node CDom_mainSig = bits(_CDom_mainSig_T, 49, 21) node _CDom_reduced4SigExtra_T = bits(CDom_absSigSum, 23, 0) node _CDom_reduced4SigExtra_T_1 = shl(_CDom_reduced4SigExtra_T, 3) wire CDom_reduced4SigExtra_reducedVec : UInt<1>[7] node _CDom_reduced4SigExtra_reducedVec_0_T = bits(_CDom_reduced4SigExtra_T_1, 3, 0) node _CDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_0_T) connect CDom_reduced4SigExtra_reducedVec[0], _CDom_reduced4SigExtra_reducedVec_0_T_1 node _CDom_reduced4SigExtra_reducedVec_1_T = bits(_CDom_reduced4SigExtra_T_1, 7, 4) node _CDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_1_T) connect CDom_reduced4SigExtra_reducedVec[1], _CDom_reduced4SigExtra_reducedVec_1_T_1 node _CDom_reduced4SigExtra_reducedVec_2_T = bits(_CDom_reduced4SigExtra_T_1, 11, 8) node _CDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_2_T) connect CDom_reduced4SigExtra_reducedVec[2], _CDom_reduced4SigExtra_reducedVec_2_T_1 node _CDom_reduced4SigExtra_reducedVec_3_T = bits(_CDom_reduced4SigExtra_T_1, 15, 12) node _CDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_3_T) connect CDom_reduced4SigExtra_reducedVec[3], _CDom_reduced4SigExtra_reducedVec_3_T_1 node _CDom_reduced4SigExtra_reducedVec_4_T = bits(_CDom_reduced4SigExtra_T_1, 19, 16) node _CDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_4_T) connect CDom_reduced4SigExtra_reducedVec[4], _CDom_reduced4SigExtra_reducedVec_4_T_1 node _CDom_reduced4SigExtra_reducedVec_5_T = bits(_CDom_reduced4SigExtra_T_1, 23, 20) node _CDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_5_T) connect CDom_reduced4SigExtra_reducedVec[5], _CDom_reduced4SigExtra_reducedVec_5_T_1 node _CDom_reduced4SigExtra_reducedVec_6_T = bits(_CDom_reduced4SigExtra_T_1, 26, 24) node _CDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_6_T) connect CDom_reduced4SigExtra_reducedVec[6], _CDom_reduced4SigExtra_reducedVec_6_T_1 node CDom_reduced4SigExtra_lo_hi = cat(CDom_reduced4SigExtra_reducedVec[2], CDom_reduced4SigExtra_reducedVec[1]) node CDom_reduced4SigExtra_lo = cat(CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec[0]) node CDom_reduced4SigExtra_hi_lo = cat(CDom_reduced4SigExtra_reducedVec[4], CDom_reduced4SigExtra_reducedVec[3]) node CDom_reduced4SigExtra_hi_hi = cat(CDom_reduced4SigExtra_reducedVec[6], CDom_reduced4SigExtra_reducedVec[5]) node CDom_reduced4SigExtra_hi = cat(CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo) node _CDom_reduced4SigExtra_T_2 = cat(CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo) node _CDom_reduced4SigExtra_T_3 = shr(io.fromPreMul.CDom_CAlignDist, 2) node _CDom_reduced4SigExtra_T_4 = not(_CDom_reduced4SigExtra_T_3) node CDom_reduced4SigExtra_shift = dshr(asSInt(UInt<9>(0h100)), _CDom_reduced4SigExtra_T_4) node _CDom_reduced4SigExtra_T_5 = bits(CDom_reduced4SigExtra_shift, 6, 1) node _CDom_reduced4SigExtra_T_6 = bits(_CDom_reduced4SigExtra_T_5, 3, 0) node _CDom_reduced4SigExtra_T_7 = bits(_CDom_reduced4SigExtra_T_6, 1, 0) node _CDom_reduced4SigExtra_T_8 = bits(_CDom_reduced4SigExtra_T_7, 0, 0) node _CDom_reduced4SigExtra_T_9 = bits(_CDom_reduced4SigExtra_T_7, 1, 1) node _CDom_reduced4SigExtra_T_10 = cat(_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9) node _CDom_reduced4SigExtra_T_11 = bits(_CDom_reduced4SigExtra_T_6, 3, 2) node _CDom_reduced4SigExtra_T_12 = bits(_CDom_reduced4SigExtra_T_11, 0, 0) node _CDom_reduced4SigExtra_T_13 = bits(_CDom_reduced4SigExtra_T_11, 1, 1) node _CDom_reduced4SigExtra_T_14 = cat(_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13) node _CDom_reduced4SigExtra_T_15 = cat(_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14) node _CDom_reduced4SigExtra_T_16 = bits(_CDom_reduced4SigExtra_T_5, 5, 4) node _CDom_reduced4SigExtra_T_17 = bits(_CDom_reduced4SigExtra_T_16, 0, 0) node _CDom_reduced4SigExtra_T_18 = bits(_CDom_reduced4SigExtra_T_16, 1, 1) node _CDom_reduced4SigExtra_T_19 = cat(_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18) node _CDom_reduced4SigExtra_T_20 = cat(_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19) node _CDom_reduced4SigExtra_T_21 = and(_CDom_reduced4SigExtra_T_2, _CDom_reduced4SigExtra_T_20) node CDom_reduced4SigExtra = orr(_CDom_reduced4SigExtra_T_21) node _CDom_sig_T = shr(CDom_mainSig, 3) node _CDom_sig_T_1 = bits(CDom_mainSig, 2, 0) node _CDom_sig_T_2 = orr(_CDom_sig_T_1) node _CDom_sig_T_3 = or(_CDom_sig_T_2, CDom_reduced4SigExtra) node _CDom_sig_T_4 = or(_CDom_sig_T_3, CDom_absSigSumExtra) node CDom_sig = cat(_CDom_sig_T, _CDom_sig_T_4) node notCDom_signSigSum = bits(sigSum, 51, 51) node _notCDom_absSigSum_T = bits(sigSum, 50, 0) node _notCDom_absSigSum_T_1 = not(_notCDom_absSigSum_T) node _notCDom_absSigSum_T_2 = bits(sigSum, 50, 0) node _notCDom_absSigSum_T_3 = add(_notCDom_absSigSum_T_2, io.fromPreMul.doSubMags) node _notCDom_absSigSum_T_4 = tail(_notCDom_absSigSum_T_3, 1) node notCDom_absSigSum = mux(notCDom_signSigSum, _notCDom_absSigSum_T_1, _notCDom_absSigSum_T_4) wire notCDom_reduced2AbsSigSum_reducedVec : UInt<1>[26] node _notCDom_reduced2AbsSigSum_reducedVec_0_T = bits(notCDom_absSigSum, 1, 0) node _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_0_T) connect notCDom_reduced2AbsSigSum_reducedVec[0], _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_1_T = bits(notCDom_absSigSum, 3, 2) node _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_1_T) connect notCDom_reduced2AbsSigSum_reducedVec[1], _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_2_T = bits(notCDom_absSigSum, 5, 4) node _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_2_T) connect notCDom_reduced2AbsSigSum_reducedVec[2], _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_3_T = bits(notCDom_absSigSum, 7, 6) node _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_3_T) connect notCDom_reduced2AbsSigSum_reducedVec[3], _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_4_T = bits(notCDom_absSigSum, 9, 8) node _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_4_T) connect notCDom_reduced2AbsSigSum_reducedVec[4], _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_5_T = bits(notCDom_absSigSum, 11, 10) node _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_5_T) connect notCDom_reduced2AbsSigSum_reducedVec[5], _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_6_T = bits(notCDom_absSigSum, 13, 12) node _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_6_T) connect notCDom_reduced2AbsSigSum_reducedVec[6], _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_7_T = bits(notCDom_absSigSum, 15, 14) node _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_7_T) connect notCDom_reduced2AbsSigSum_reducedVec[7], _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_8_T = bits(notCDom_absSigSum, 17, 16) node _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_8_T) connect notCDom_reduced2AbsSigSum_reducedVec[8], _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_9_T = bits(notCDom_absSigSum, 19, 18) node _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_9_T) connect notCDom_reduced2AbsSigSum_reducedVec[9], _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_10_T = bits(notCDom_absSigSum, 21, 20) node _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_10_T) connect notCDom_reduced2AbsSigSum_reducedVec[10], _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_11_T = bits(notCDom_absSigSum, 23, 22) node _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_11_T) connect notCDom_reduced2AbsSigSum_reducedVec[11], _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_12_T = bits(notCDom_absSigSum, 25, 24) node _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_12_T) connect notCDom_reduced2AbsSigSum_reducedVec[12], _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_13_T = bits(notCDom_absSigSum, 27, 26) node _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_13_T) connect notCDom_reduced2AbsSigSum_reducedVec[13], _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_14_T = bits(notCDom_absSigSum, 29, 28) node _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_14_T) connect notCDom_reduced2AbsSigSum_reducedVec[14], _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_15_T = bits(notCDom_absSigSum, 31, 30) node _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_15_T) connect notCDom_reduced2AbsSigSum_reducedVec[15], _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_16_T = bits(notCDom_absSigSum, 33, 32) node _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_16_T) connect notCDom_reduced2AbsSigSum_reducedVec[16], _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_17_T = bits(notCDom_absSigSum, 35, 34) node _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_17_T) connect notCDom_reduced2AbsSigSum_reducedVec[17], _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_18_T = bits(notCDom_absSigSum, 37, 36) node _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_18_T) connect notCDom_reduced2AbsSigSum_reducedVec[18], _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_19_T = bits(notCDom_absSigSum, 39, 38) node _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_19_T) connect notCDom_reduced2AbsSigSum_reducedVec[19], _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_20_T = bits(notCDom_absSigSum, 41, 40) node _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_20_T) connect notCDom_reduced2AbsSigSum_reducedVec[20], _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_21_T = bits(notCDom_absSigSum, 43, 42) node _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_21_T) connect notCDom_reduced2AbsSigSum_reducedVec[21], _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_22_T = bits(notCDom_absSigSum, 45, 44) node _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_22_T) connect notCDom_reduced2AbsSigSum_reducedVec[22], _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_23_T = bits(notCDom_absSigSum, 47, 46) node _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_23_T) connect notCDom_reduced2AbsSigSum_reducedVec[23], _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_24_T = bits(notCDom_absSigSum, 49, 48) node _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_24_T) connect notCDom_reduced2AbsSigSum_reducedVec[24], _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_25_T = bits(notCDom_absSigSum, 50, 50) node _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_25_T) connect notCDom_reduced2AbsSigSum_reducedVec[25], _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 node notCDom_reduced2AbsSigSum_lo_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[2], notCDom_reduced2AbsSigSum_reducedVec[1]) node notCDom_reduced2AbsSigSum_lo_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[0]) node notCDom_reduced2AbsSigSum_lo_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[5], notCDom_reduced2AbsSigSum_reducedVec[4]) node notCDom_reduced2AbsSigSum_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[3]) node notCDom_reduced2AbsSigSum_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo) node notCDom_reduced2AbsSigSum_lo_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[8], notCDom_reduced2AbsSigSum_reducedVec[7]) node notCDom_reduced2AbsSigSum_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[6]) node notCDom_reduced2AbsSigSum_lo_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[10], notCDom_reduced2AbsSigSum_reducedVec[9]) node notCDom_reduced2AbsSigSum_lo_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[12], notCDom_reduced2AbsSigSum_reducedVec[11]) node notCDom_reduced2AbsSigSum_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo) node notCDom_reduced2AbsSigSum_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo) node notCDom_reduced2AbsSigSum_lo = cat(notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo) node notCDom_reduced2AbsSigSum_hi_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[15], notCDom_reduced2AbsSigSum_reducedVec[14]) node notCDom_reduced2AbsSigSum_hi_lo_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[13]) node notCDom_reduced2AbsSigSum_hi_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[18], notCDom_reduced2AbsSigSum_reducedVec[17]) node notCDom_reduced2AbsSigSum_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[16]) node notCDom_reduced2AbsSigSum_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo) node notCDom_reduced2AbsSigSum_hi_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[21], notCDom_reduced2AbsSigSum_reducedVec[20]) node notCDom_reduced2AbsSigSum_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[19]) node notCDom_reduced2AbsSigSum_hi_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[23], notCDom_reduced2AbsSigSum_reducedVec[22]) node notCDom_reduced2AbsSigSum_hi_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[25], notCDom_reduced2AbsSigSum_reducedVec[24]) node notCDom_reduced2AbsSigSum_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo) node notCDom_reduced2AbsSigSum_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo) node notCDom_reduced2AbsSigSum_hi = cat(notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo) node notCDom_reduced2AbsSigSum = cat(notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo) node _notCDom_normDistReduced2_T = bits(notCDom_reduced2AbsSigSum, 0, 0) node _notCDom_normDistReduced2_T_1 = bits(notCDom_reduced2AbsSigSum, 1, 1) node _notCDom_normDistReduced2_T_2 = bits(notCDom_reduced2AbsSigSum, 2, 2) node _notCDom_normDistReduced2_T_3 = bits(notCDom_reduced2AbsSigSum, 3, 3) node _notCDom_normDistReduced2_T_4 = bits(notCDom_reduced2AbsSigSum, 4, 4) node _notCDom_normDistReduced2_T_5 = bits(notCDom_reduced2AbsSigSum, 5, 5) node _notCDom_normDistReduced2_T_6 = bits(notCDom_reduced2AbsSigSum, 6, 6) node _notCDom_normDistReduced2_T_7 = bits(notCDom_reduced2AbsSigSum, 7, 7) node _notCDom_normDistReduced2_T_8 = bits(notCDom_reduced2AbsSigSum, 8, 8) node _notCDom_normDistReduced2_T_9 = bits(notCDom_reduced2AbsSigSum, 9, 9) node _notCDom_normDistReduced2_T_10 = bits(notCDom_reduced2AbsSigSum, 10, 10) node _notCDom_normDistReduced2_T_11 = bits(notCDom_reduced2AbsSigSum, 11, 11) node _notCDom_normDistReduced2_T_12 = bits(notCDom_reduced2AbsSigSum, 12, 12) node _notCDom_normDistReduced2_T_13 = bits(notCDom_reduced2AbsSigSum, 13, 13) node _notCDom_normDistReduced2_T_14 = bits(notCDom_reduced2AbsSigSum, 14, 14) node _notCDom_normDistReduced2_T_15 = bits(notCDom_reduced2AbsSigSum, 15, 15) node _notCDom_normDistReduced2_T_16 = bits(notCDom_reduced2AbsSigSum, 16, 16) node _notCDom_normDistReduced2_T_17 = bits(notCDom_reduced2AbsSigSum, 17, 17) node _notCDom_normDistReduced2_T_18 = bits(notCDom_reduced2AbsSigSum, 18, 18) node _notCDom_normDistReduced2_T_19 = bits(notCDom_reduced2AbsSigSum, 19, 19) node _notCDom_normDistReduced2_T_20 = bits(notCDom_reduced2AbsSigSum, 20, 20) node _notCDom_normDistReduced2_T_21 = bits(notCDom_reduced2AbsSigSum, 21, 21) node _notCDom_normDistReduced2_T_22 = bits(notCDom_reduced2AbsSigSum, 22, 22) node _notCDom_normDistReduced2_T_23 = bits(notCDom_reduced2AbsSigSum, 23, 23) node _notCDom_normDistReduced2_T_24 = bits(notCDom_reduced2AbsSigSum, 24, 24) node _notCDom_normDistReduced2_T_25 = bits(notCDom_reduced2AbsSigSum, 25, 25) node _notCDom_normDistReduced2_T_26 = mux(_notCDom_normDistReduced2_T_1, UInt<5>(0h18), UInt<5>(0h19)) node _notCDom_normDistReduced2_T_27 = mux(_notCDom_normDistReduced2_T_2, UInt<5>(0h17), _notCDom_normDistReduced2_T_26) node _notCDom_normDistReduced2_T_28 = mux(_notCDom_normDistReduced2_T_3, UInt<5>(0h16), _notCDom_normDistReduced2_T_27) node _notCDom_normDistReduced2_T_29 = mux(_notCDom_normDistReduced2_T_4, UInt<5>(0h15), _notCDom_normDistReduced2_T_28) node _notCDom_normDistReduced2_T_30 = mux(_notCDom_normDistReduced2_T_5, UInt<5>(0h14), _notCDom_normDistReduced2_T_29) node _notCDom_normDistReduced2_T_31 = mux(_notCDom_normDistReduced2_T_6, UInt<5>(0h13), _notCDom_normDistReduced2_T_30) node _notCDom_normDistReduced2_T_32 = mux(_notCDom_normDistReduced2_T_7, UInt<5>(0h12), _notCDom_normDistReduced2_T_31) node _notCDom_normDistReduced2_T_33 = mux(_notCDom_normDistReduced2_T_8, UInt<5>(0h11), _notCDom_normDistReduced2_T_32) node _notCDom_normDistReduced2_T_34 = mux(_notCDom_normDistReduced2_T_9, UInt<5>(0h10), _notCDom_normDistReduced2_T_33) node _notCDom_normDistReduced2_T_35 = mux(_notCDom_normDistReduced2_T_10, UInt<4>(0hf), _notCDom_normDistReduced2_T_34) node _notCDom_normDistReduced2_T_36 = mux(_notCDom_normDistReduced2_T_11, UInt<4>(0he), _notCDom_normDistReduced2_T_35) node _notCDom_normDistReduced2_T_37 = mux(_notCDom_normDistReduced2_T_12, UInt<4>(0hd), _notCDom_normDistReduced2_T_36) node _notCDom_normDistReduced2_T_38 = mux(_notCDom_normDistReduced2_T_13, UInt<4>(0hc), _notCDom_normDistReduced2_T_37) node _notCDom_normDistReduced2_T_39 = mux(_notCDom_normDistReduced2_T_14, UInt<4>(0hb), _notCDom_normDistReduced2_T_38) node _notCDom_normDistReduced2_T_40 = mux(_notCDom_normDistReduced2_T_15, UInt<4>(0ha), _notCDom_normDistReduced2_T_39) node _notCDom_normDistReduced2_T_41 = mux(_notCDom_normDistReduced2_T_16, UInt<4>(0h9), _notCDom_normDistReduced2_T_40) node _notCDom_normDistReduced2_T_42 = mux(_notCDom_normDistReduced2_T_17, UInt<4>(0h8), _notCDom_normDistReduced2_T_41) node _notCDom_normDistReduced2_T_43 = mux(_notCDom_normDistReduced2_T_18, UInt<3>(0h7), _notCDom_normDistReduced2_T_42) node _notCDom_normDistReduced2_T_44 = mux(_notCDom_normDistReduced2_T_19, UInt<3>(0h6), _notCDom_normDistReduced2_T_43) node _notCDom_normDistReduced2_T_45 = mux(_notCDom_normDistReduced2_T_20, UInt<3>(0h5), _notCDom_normDistReduced2_T_44) node _notCDom_normDistReduced2_T_46 = mux(_notCDom_normDistReduced2_T_21, UInt<3>(0h4), _notCDom_normDistReduced2_T_45) node _notCDom_normDistReduced2_T_47 = mux(_notCDom_normDistReduced2_T_22, UInt<2>(0h3), _notCDom_normDistReduced2_T_46) node _notCDom_normDistReduced2_T_48 = mux(_notCDom_normDistReduced2_T_23, UInt<2>(0h2), _notCDom_normDistReduced2_T_47) node _notCDom_normDistReduced2_T_49 = mux(_notCDom_normDistReduced2_T_24, UInt<1>(0h1), _notCDom_normDistReduced2_T_48) node notCDom_normDistReduced2 = mux(_notCDom_normDistReduced2_T_25, UInt<1>(0h0), _notCDom_normDistReduced2_T_49) node notCDom_nearNormDist = shl(notCDom_normDistReduced2, 1) node _notCDom_sExp_T = cvt(notCDom_nearNormDist) node _notCDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _notCDom_sExp_T) node _notCDom_sExp_T_2 = tail(_notCDom_sExp_T_1, 1) node notCDom_sExp = asSInt(_notCDom_sExp_T_2) node _notCDom_mainSig_T = dshl(notCDom_absSigSum, notCDom_nearNormDist) node notCDom_mainSig = bits(_notCDom_mainSig_T, 51, 23) node _notCDom_reduced4SigExtra_T = bits(notCDom_reduced2AbsSigSum, 12, 0) node _notCDom_reduced4SigExtra_T_1 = shl(_notCDom_reduced4SigExtra_T, 0) wire notCDom_reduced4SigExtra_reducedVec : UInt<1>[7] node _notCDom_reduced4SigExtra_reducedVec_0_T = bits(_notCDom_reduced4SigExtra_T_1, 1, 0) node _notCDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_0_T) connect notCDom_reduced4SigExtra_reducedVec[0], _notCDom_reduced4SigExtra_reducedVec_0_T_1 node _notCDom_reduced4SigExtra_reducedVec_1_T = bits(_notCDom_reduced4SigExtra_T_1, 3, 2) node _notCDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_1_T) connect notCDom_reduced4SigExtra_reducedVec[1], _notCDom_reduced4SigExtra_reducedVec_1_T_1 node _notCDom_reduced4SigExtra_reducedVec_2_T = bits(_notCDom_reduced4SigExtra_T_1, 5, 4) node _notCDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_2_T) connect notCDom_reduced4SigExtra_reducedVec[2], _notCDom_reduced4SigExtra_reducedVec_2_T_1 node _notCDom_reduced4SigExtra_reducedVec_3_T = bits(_notCDom_reduced4SigExtra_T_1, 7, 6) node _notCDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_3_T) connect notCDom_reduced4SigExtra_reducedVec[3], _notCDom_reduced4SigExtra_reducedVec_3_T_1 node _notCDom_reduced4SigExtra_reducedVec_4_T = bits(_notCDom_reduced4SigExtra_T_1, 9, 8) node _notCDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_4_T) connect notCDom_reduced4SigExtra_reducedVec[4], _notCDom_reduced4SigExtra_reducedVec_4_T_1 node _notCDom_reduced4SigExtra_reducedVec_5_T = bits(_notCDom_reduced4SigExtra_T_1, 11, 10) node _notCDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_5_T) connect notCDom_reduced4SigExtra_reducedVec[5], _notCDom_reduced4SigExtra_reducedVec_5_T_1 node _notCDom_reduced4SigExtra_reducedVec_6_T = bits(_notCDom_reduced4SigExtra_T_1, 12, 12) node _notCDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_6_T) connect notCDom_reduced4SigExtra_reducedVec[6], _notCDom_reduced4SigExtra_reducedVec_6_T_1 node notCDom_reduced4SigExtra_lo_hi = cat(notCDom_reduced4SigExtra_reducedVec[2], notCDom_reduced4SigExtra_reducedVec[1]) node notCDom_reduced4SigExtra_lo = cat(notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec[0]) node notCDom_reduced4SigExtra_hi_lo = cat(notCDom_reduced4SigExtra_reducedVec[4], notCDom_reduced4SigExtra_reducedVec[3]) node notCDom_reduced4SigExtra_hi_hi = cat(notCDom_reduced4SigExtra_reducedVec[6], notCDom_reduced4SigExtra_reducedVec[5]) node notCDom_reduced4SigExtra_hi = cat(notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo) node _notCDom_reduced4SigExtra_T_2 = cat(notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo) node _notCDom_reduced4SigExtra_T_3 = shr(notCDom_normDistReduced2, 1) node _notCDom_reduced4SigExtra_T_4 = not(_notCDom_reduced4SigExtra_T_3) node notCDom_reduced4SigExtra_shift = dshr(asSInt(UInt<17>(0h10000)), _notCDom_reduced4SigExtra_T_4) node _notCDom_reduced4SigExtra_T_5 = bits(notCDom_reduced4SigExtra_shift, 6, 1) node _notCDom_reduced4SigExtra_T_6 = bits(_notCDom_reduced4SigExtra_T_5, 3, 0) node _notCDom_reduced4SigExtra_T_7 = bits(_notCDom_reduced4SigExtra_T_6, 1, 0) node _notCDom_reduced4SigExtra_T_8 = bits(_notCDom_reduced4SigExtra_T_7, 0, 0) node _notCDom_reduced4SigExtra_T_9 = bits(_notCDom_reduced4SigExtra_T_7, 1, 1) node _notCDom_reduced4SigExtra_T_10 = cat(_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9) node _notCDom_reduced4SigExtra_T_11 = bits(_notCDom_reduced4SigExtra_T_6, 3, 2) node _notCDom_reduced4SigExtra_T_12 = bits(_notCDom_reduced4SigExtra_T_11, 0, 0) node _notCDom_reduced4SigExtra_T_13 = bits(_notCDom_reduced4SigExtra_T_11, 1, 1) node _notCDom_reduced4SigExtra_T_14 = cat(_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13) node _notCDom_reduced4SigExtra_T_15 = cat(_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14) node _notCDom_reduced4SigExtra_T_16 = bits(_notCDom_reduced4SigExtra_T_5, 5, 4) node _notCDom_reduced4SigExtra_T_17 = bits(_notCDom_reduced4SigExtra_T_16, 0, 0) node _notCDom_reduced4SigExtra_T_18 = bits(_notCDom_reduced4SigExtra_T_16, 1, 1) node _notCDom_reduced4SigExtra_T_19 = cat(_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18) node _notCDom_reduced4SigExtra_T_20 = cat(_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19) node _notCDom_reduced4SigExtra_T_21 = and(_notCDom_reduced4SigExtra_T_2, _notCDom_reduced4SigExtra_T_20) node notCDom_reduced4SigExtra = orr(_notCDom_reduced4SigExtra_T_21) node _notCDom_sig_T = shr(notCDom_mainSig, 3) node _notCDom_sig_T_1 = bits(notCDom_mainSig, 2, 0) node _notCDom_sig_T_2 = orr(_notCDom_sig_T_1) node _notCDom_sig_T_3 = or(_notCDom_sig_T_2, notCDom_reduced4SigExtra) node notCDom_sig = cat(_notCDom_sig_T, _notCDom_sig_T_3) node _notCDom_completeCancellation_T = bits(notCDom_sig, 26, 25) node notCDom_completeCancellation = eq(_notCDom_completeCancellation_T, UInt<1>(0h0)) node _notCDom_sign_T = xor(io.fromPreMul.signProd, notCDom_signSigSum) node notCDom_sign = mux(notCDom_completeCancellation, roundingMode_min, _notCDom_sign_T) node notNaN_isInfProd = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB) node notNaN_isInfOut = or(notNaN_isInfProd, io.fromPreMul.isInfC) node _notNaN_addZeros_T = or(io.fromPreMul.isZeroA, io.fromPreMul.isZeroB) node notNaN_addZeros = and(_notNaN_addZeros_T, io.fromPreMul.isZeroC) node _io_invalidExc_T = and(io.fromPreMul.isInfA, io.fromPreMul.isZeroB) node _io_invalidExc_T_1 = or(io.fromPreMul.isSigNaNAny, _io_invalidExc_T) node _io_invalidExc_T_2 = and(io.fromPreMul.isZeroA, io.fromPreMul.isInfB) node _io_invalidExc_T_3 = or(_io_invalidExc_T_1, _io_invalidExc_T_2) node _io_invalidExc_T_4 = eq(io.fromPreMul.isNaNAOrB, UInt<1>(0h0)) node _io_invalidExc_T_5 = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB) node _io_invalidExc_T_6 = and(_io_invalidExc_T_4, _io_invalidExc_T_5) node _io_invalidExc_T_7 = and(_io_invalidExc_T_6, io.fromPreMul.isInfC) node _io_invalidExc_T_8 = and(_io_invalidExc_T_7, io.fromPreMul.doSubMags) node _io_invalidExc_T_9 = or(_io_invalidExc_T_3, _io_invalidExc_T_8) connect io.invalidExc, _io_invalidExc_T_9 node _io_rawOut_isNaN_T = or(io.fromPreMul.isNaNAOrB, io.fromPreMul.isNaNC) connect io.rawOut.isNaN, _io_rawOut_isNaN_T connect io.rawOut.isInf, notNaN_isInfOut node _io_rawOut_isZero_T = eq(io.fromPreMul.CIsDominant, UInt<1>(0h0)) node _io_rawOut_isZero_T_1 = and(_io_rawOut_isZero_T, notCDom_completeCancellation) node _io_rawOut_isZero_T_2 = or(notNaN_addZeros, _io_rawOut_isZero_T_1) connect io.rawOut.isZero, _io_rawOut_isZero_T_2 node _io_rawOut_sign_T = and(notNaN_isInfProd, io.fromPreMul.signProd) node _io_rawOut_sign_T_1 = and(io.fromPreMul.isInfC, opSignC) node _io_rawOut_sign_T_2 = or(_io_rawOut_sign_T, _io_rawOut_sign_T_1) node _io_rawOut_sign_T_3 = eq(roundingMode_min, UInt<1>(0h0)) node _io_rawOut_sign_T_4 = and(notNaN_addZeros, _io_rawOut_sign_T_3) node _io_rawOut_sign_T_5 = and(_io_rawOut_sign_T_4, io.fromPreMul.signProd) node _io_rawOut_sign_T_6 = and(_io_rawOut_sign_T_5, opSignC) node _io_rawOut_sign_T_7 = or(_io_rawOut_sign_T_2, _io_rawOut_sign_T_6) node _io_rawOut_sign_T_8 = and(notNaN_addZeros, roundingMode_min) node _io_rawOut_sign_T_9 = or(io.fromPreMul.signProd, opSignC) node _io_rawOut_sign_T_10 = and(_io_rawOut_sign_T_8, _io_rawOut_sign_T_9) node _io_rawOut_sign_T_11 = or(_io_rawOut_sign_T_7, _io_rawOut_sign_T_10) node _io_rawOut_sign_T_12 = eq(notNaN_isInfOut, UInt<1>(0h0)) node _io_rawOut_sign_T_13 = eq(notNaN_addZeros, UInt<1>(0h0)) node _io_rawOut_sign_T_14 = and(_io_rawOut_sign_T_12, _io_rawOut_sign_T_13) node _io_rawOut_sign_T_15 = mux(io.fromPreMul.CIsDominant, opSignC, notCDom_sign) node _io_rawOut_sign_T_16 = and(_io_rawOut_sign_T_14, _io_rawOut_sign_T_15) node _io_rawOut_sign_T_17 = or(_io_rawOut_sign_T_11, _io_rawOut_sign_T_16) connect io.rawOut.sign, _io_rawOut_sign_T_17 node _io_rawOut_sExp_T = mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) connect io.rawOut.sExp, _io_rawOut_sExp_T node _io_rawOut_sig_T = mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) connect io.rawOut.sig, _io_rawOut_sig_T
module MulAddRecFNToRaw_postMul_e8_s24_54( // @[MulAddRecFN.scala:169:7] input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroC, // @[MulAddRecFN.scala:172:16] input [9:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_CIsDominant, // @[MulAddRecFN.scala:172:16] input [25:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16] input [48:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16] output io_invalidExc, // @[MulAddRecFN.scala:172:16] output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16] output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16] output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16] output io_rawOut_sign, // @[MulAddRecFN.scala:172:16] output [9:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16] output [26:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16] ); wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNC_0 = io_fromPreMul_isNaNC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfC_0 = io_fromPreMul_isInfC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroC_0 = io_fromPreMul_isZeroC; // @[MulAddRecFN.scala:169:7] wire [9:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_CIsDominant_0 = io_fromPreMul_CIsDominant; // @[MulAddRecFN.scala:169:7] wire [25:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7] wire [48:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7] wire [2:0] _CDom_reduced4SigExtra_T_4 = 3'h7; // @[primitives.scala:52:21] wire [8:0] CDom_reduced4SigExtra_shift = 9'h1FE; // @[primitives.scala:76:56] wire [3:0] _CDom_reduced4SigExtra_T_6 = 4'hF; // @[primitives.scala:77:20] wire [3:0] _CDom_reduced4SigExtra_T_15 = 4'hF; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_7 = 2'h3; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_10 = 2'h3; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_11 = 2'h3; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_14 = 2'h3; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_16 = 2'h3; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_19 = 2'h3; // @[primitives.scala:77:20] wire [5:0] _CDom_reduced4SigExtra_T_5 = 6'h3F; // @[primitives.scala:77:20, :78:22] wire [5:0] _CDom_reduced4SigExtra_T_20 = 6'h3F; // @[primitives.scala:77:20, :78:22] wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:169:7, :172:16, :223:51] wire [2:0] _CDom_reduced4SigExtra_T_3 = 3'h0; // @[MulAddRecFN.scala:169:7, :172:16, :223:51] wire [4:0] io_fromPreMul_CDom_CAlignDist = 5'h0; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroA = 1'h1; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_signProd = 1'h1; // @[MulAddRecFN.scala:169:7] wire _CDom_reduced4SigExtra_T_8 = 1'h1; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_9 = 1'h1; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_12 = 1'h1; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_13 = 1'h1; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_17 = 1'h1; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_18 = 1'h1; // @[primitives.scala:77:20] wire _notNaN_addZeros_T = 1'h1; // @[MulAddRecFN.scala:267:32] wire _io_invalidExc_T_4 = 1'h1; // @[MulAddRecFN.scala:274:10] wire _io_rawOut_sign_T_3 = 1'h1; // @[MulAddRecFN.scala:287:29] wire _io_rawOut_sign_T_9 = 1'h1; // @[MulAddRecFN.scala:290:37] wire io_fromPreMul_isNaNAOrB = 1'h0; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfA = 1'h0; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfB = 1'h0; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroB = 1'h0; // @[MulAddRecFN.scala:169:7] wire roundingMode_min = 1'h0; // @[MulAddRecFN.scala:186:45] wire notNaN_isInfProd = 1'h0; // @[MulAddRecFN.scala:264:49] wire _io_invalidExc_T = 1'h0; // @[MulAddRecFN.scala:272:31] wire _io_invalidExc_T_2 = 1'h0; // @[MulAddRecFN.scala:273:32] wire _io_invalidExc_T_5 = 1'h0; // @[MulAddRecFN.scala:275:36] wire _io_invalidExc_T_6 = 1'h0; // @[MulAddRecFN.scala:274:36] wire _io_invalidExc_T_7 = 1'h0; // @[MulAddRecFN.scala:275:61] wire _io_invalidExc_T_8 = 1'h0; // @[MulAddRecFN.scala:276:35] wire _io_rawOut_sign_T = 1'h0; // @[MulAddRecFN.scala:285:27] wire _io_rawOut_sign_T_8 = 1'h0; // @[MulAddRecFN.scala:289:26] wire _io_rawOut_sign_T_10 = 1'h0; // @[MulAddRecFN.scala:289:46] wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0; // @[MulAddRecFN.scala:169:7, :271:35] wire _io_rawOut_isNaN_T = io_fromPreMul_isNaNC_0; // @[MulAddRecFN.scala:169:7, :278:48] wire notNaN_isInfOut = io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :265:44] wire notNaN_addZeros = io_fromPreMul_isZeroC_0; // @[MulAddRecFN.scala:169:7, :267:58] wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57] wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25] wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50] wire [9:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26] wire [26:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25] wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] wire [9:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] wire [26:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7] wire opSignC = ~io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42] wire _sigSum_T = io_mulAddResult_0[48]; // @[MulAddRecFN.scala:169:7, :192:32] wire [26:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 27'h1; // @[MulAddRecFN.scala:169:7, :193:47] wire [25:0] _sigSum_T_2 = _sigSum_T_1[25:0]; // @[MulAddRecFN.scala:193:47] wire [25:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47] wire [47:0] _sigSum_T_4 = io_mulAddResult_0[47:0]; // @[MulAddRecFN.scala:169:7, :196:28] wire [73:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28] wire [74:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12] wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69] wire [10:0] _GEN = {io_fromPreMul_sExpSum_0[9], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43] wire [10:0] _CDom_sExp_T_1 = _GEN - {{9{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}] wire [9:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:203:43] wire [9:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43] wire [49:0] _CDom_absSigSum_T = sigSum[74:25]; // @[MulAddRecFN.scala:192:12, :206:20] wire [49:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}] wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[25:24]; // @[MulAddRecFN.scala:169:7, :209:46] wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46] wire [46:0] _CDom_absSigSum_T_4 = sigSum[72:26]; // @[MulAddRecFN.scala:192:12, :210:23] wire [49:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23] wire [49:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71] wire [23:0] _CDom_absSigSumExtra_T = sigSum[24:1]; // @[MulAddRecFN.scala:192:12, :215:21] wire [23:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}] wire _CDom_absSigSumExtra_T_2 = |_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}] wire [24:0] _CDom_absSigSumExtra_T_3 = sigSum[25:1]; // @[MulAddRecFN.scala:192:12, :216:19] wire _CDom_absSigSumExtra_T_4 = |_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}] wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37] wire [80:0] _CDom_mainSig_T = {31'h0, CDom_absSigSum}; // @[MulAddRecFN.scala:205:12, :219:24] wire [28:0] CDom_mainSig = _CDom_mainSig_T[49:21]; // @[MulAddRecFN.scala:219:{24,56}] wire [23:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[23:0]; // @[MulAddRecFN.scala:205:12, :222:36] wire [26:0] _CDom_reduced4SigExtra_T_1 = {_CDom_reduced4SigExtra_T, 3'h0}; // @[MulAddRecFN.scala:169:7, :172:16, :222:{36,53}, :223:51] wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:123:57] wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:118:30] wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = |_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = |_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[11:8]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = |_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_3_T = _CDom_reduced4SigExtra_T_1[15:12]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_3_T_1 = |_CDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_3 = _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_4_T = _CDom_reduced4SigExtra_T_1[19:16]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_4_T_1 = |_CDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_4 = _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_5_T = _CDom_reduced4SigExtra_T_1[23:20]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_5_T_1 = |_CDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_5 = _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54] wire [2:0] _CDom_reduced4SigExtra_reducedVec_6_T = _CDom_reduced4SigExtra_T_1[26:24]; // @[primitives.scala:123:15] assign _CDom_reduced4SigExtra_reducedVec_6_T_1 = |_CDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}] assign CDom_reduced4SigExtra_reducedVec_6 = _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57] wire [1:0] CDom_reduced4SigExtra_lo_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20] wire [2:0] CDom_reduced4SigExtra_lo = {CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_lo = {CDom_reduced4SigExtra_reducedVec_4, CDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_hi = {CDom_reduced4SigExtra_reducedVec_6, CDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20] wire [3:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:124:20] wire [6:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo}; // @[primitives.scala:124:20] wire [6:0] _CDom_reduced4SigExtra_T_21 = {1'h0, _CDom_reduced4SigExtra_T_2[5:0]}; // @[primitives.scala:124:20] wire CDom_reduced4SigExtra = |_CDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:222:72, :223:73] wire [25:0] _CDom_sig_T = CDom_mainSig[28:3]; // @[MulAddRecFN.scala:219:56, :225:25] wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25] wire _CDom_sig_T_2 = |_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}] wire _CDom_sig_T_3 = _CDom_sig_T_2 | CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}] wire _CDom_sig_T_4 = _CDom_sig_T_3 | CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}] wire [26:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61] wire notCDom_signSigSum = sigSum[51]; // @[MulAddRecFN.scala:192:12, :232:36] wire [50:0] _notCDom_absSigSum_T = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20] wire [50:0] _notCDom_absSigSum_T_2 = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19] wire [50:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}] wire [51:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {51'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}] wire [50:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[50:0]; // @[MulAddRecFN.scala:236:41] wire [50:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41] wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:106:57] wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_13; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_14; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_15; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_16; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_17; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_18; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_19; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_20; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_21; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_22; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_23; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_24; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_25; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[25:24]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_13_T = notCDom_absSigSum[27:26]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_13_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_13 = _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_14_T = notCDom_absSigSum[29:28]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_14_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_14 = _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_15_T = notCDom_absSigSum[31:30]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_15_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_15 = _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_16_T = notCDom_absSigSum[33:32]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_16_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_16 = _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_17_T = notCDom_absSigSum[35:34]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_17_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_17 = _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_18_T = notCDom_absSigSum[37:36]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_18_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_18 = _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_19_T = notCDom_absSigSum[39:38]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_19_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_19 = _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_20_T = notCDom_absSigSum[41:40]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_20_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_20 = _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_21_T = notCDom_absSigSum[43:42]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_21_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_21 = _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_22_T = notCDom_absSigSum[45:44]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_22_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_22 = _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_23_T = notCDom_absSigSum[47:46]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_23_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_23 = _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_24_T = notCDom_absSigSum[49:48]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_24_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_24 = _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T = notCDom_absSigSum[50]; // @[primitives.scala:106:15] assign _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_25_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced2AbsSigSum_reducedVec_25 = _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_hi_lo = {notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_15, notCDom_reduced2AbsSigSum_reducedVec_14}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_lo = {notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_13}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_18, notCDom_reduced2AbsSigSum_reducedVec_17}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_16}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_21, notCDom_reduced2AbsSigSum_reducedVec_20}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_19}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_23, notCDom_reduced2AbsSigSum_reducedVec_22}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_25, notCDom_reduced2AbsSigSum_reducedVec_24}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20] wire [25:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20] wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_13 = notCDom_reduced2AbsSigSum[13]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_14 = notCDom_reduced2AbsSigSum[14]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_15 = notCDom_reduced2AbsSigSum[15]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_16 = notCDom_reduced2AbsSigSum[16]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_17 = notCDom_reduced2AbsSigSum[17]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_18 = notCDom_reduced2AbsSigSum[18]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_19 = notCDom_reduced2AbsSigSum[19]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_20 = notCDom_reduced2AbsSigSum[20]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_21 = notCDom_reduced2AbsSigSum[21]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_22 = notCDom_reduced2AbsSigSum[22]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_23 = notCDom_reduced2AbsSigSum[23]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_24 = notCDom_reduced2AbsSigSum[24]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_25 = notCDom_reduced2AbsSigSum[25]; // @[primitives.scala:91:52, :107:20] wire [4:0] _notCDom_normDistReduced2_T_26 = {4'hC, ~_notCDom_normDistReduced2_T_1}; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_27 = _notCDom_normDistReduced2_T_2 ? 5'h17 : _notCDom_normDistReduced2_T_26; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_28 = _notCDom_normDistReduced2_T_3 ? 5'h16 : _notCDom_normDistReduced2_T_27; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_29 = _notCDom_normDistReduced2_T_4 ? 5'h15 : _notCDom_normDistReduced2_T_28; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_30 = _notCDom_normDistReduced2_T_5 ? 5'h14 : _notCDom_normDistReduced2_T_29; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_31 = _notCDom_normDistReduced2_T_6 ? 5'h13 : _notCDom_normDistReduced2_T_30; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_32 = _notCDom_normDistReduced2_T_7 ? 5'h12 : _notCDom_normDistReduced2_T_31; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_33 = _notCDom_normDistReduced2_T_8 ? 5'h11 : _notCDom_normDistReduced2_T_32; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_34 = _notCDom_normDistReduced2_T_9 ? 5'h10 : _notCDom_normDistReduced2_T_33; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_35 = _notCDom_normDistReduced2_T_10 ? 5'hF : _notCDom_normDistReduced2_T_34; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_36 = _notCDom_normDistReduced2_T_11 ? 5'hE : _notCDom_normDistReduced2_T_35; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_37 = _notCDom_normDistReduced2_T_12 ? 5'hD : _notCDom_normDistReduced2_T_36; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_38 = _notCDom_normDistReduced2_T_13 ? 5'hC : _notCDom_normDistReduced2_T_37; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_39 = _notCDom_normDistReduced2_T_14 ? 5'hB : _notCDom_normDistReduced2_T_38; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_40 = _notCDom_normDistReduced2_T_15 ? 5'hA : _notCDom_normDistReduced2_T_39; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_41 = _notCDom_normDistReduced2_T_16 ? 5'h9 : _notCDom_normDistReduced2_T_40; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_42 = _notCDom_normDistReduced2_T_17 ? 5'h8 : _notCDom_normDistReduced2_T_41; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_43 = _notCDom_normDistReduced2_T_18 ? 5'h7 : _notCDom_normDistReduced2_T_42; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_44 = _notCDom_normDistReduced2_T_19 ? 5'h6 : _notCDom_normDistReduced2_T_43; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_45 = _notCDom_normDistReduced2_T_20 ? 5'h5 : _notCDom_normDistReduced2_T_44; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_46 = _notCDom_normDistReduced2_T_21 ? 5'h4 : _notCDom_normDistReduced2_T_45; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_47 = _notCDom_normDistReduced2_T_22 ? 5'h3 : _notCDom_normDistReduced2_T_46; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_48 = _notCDom_normDistReduced2_T_23 ? 5'h2 : _notCDom_normDistReduced2_T_47; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_49 = _notCDom_normDistReduced2_T_24 ? 5'h1 : _notCDom_normDistReduced2_T_48; // @[Mux.scala:50:70] wire [4:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_25 ? 5'h0 : _notCDom_normDistReduced2_T_49; // @[Mux.scala:50:70] wire [5:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70] wire [6:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76] wire [10:0] _notCDom_sExp_T_1 = _GEN - {{4{_notCDom_sExp_T[6]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}] wire [9:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:241:46] wire [9:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46] wire [113:0] _notCDom_mainSig_T = {63'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27] wire [28:0] notCDom_mainSig = _notCDom_mainSig_T[51:23]; // @[MulAddRecFN.scala:243:{27,50}] wire [12:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[12:0]; // @[primitives.scala:107:20] wire [12:0] _notCDom_reduced4SigExtra_T_1 = _notCDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:247:{39,55}] wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:106:57] wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = |_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = |_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = |_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = |_notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_4_T = _notCDom_reduced4SigExtra_T_1[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_4_T_1 = |_notCDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_4 = _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_5_T = _notCDom_reduced4SigExtra_T_1[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_5_T_1 = |_notCDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_5 = _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T = _notCDom_reduced4SigExtra_T_1[12]; // @[primitives.scala:106:15] assign _notCDom_reduced4SigExtra_reducedVec_6_T_1 = _notCDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced4SigExtra_reducedVec_6 = _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced4SigExtra_lo_hi = {notCDom_reduced4SigExtra_reducedVec_2, notCDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_lo = {notCDom_reduced4SigExtra_reducedVec_4, notCDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_hi = {notCDom_reduced4SigExtra_reducedVec_6, notCDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:107:20] wire [6:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20] wire [3:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[4:1]; // @[Mux.scala:50:70] wire [3:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [16:0] notCDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [5:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22] wire [3:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _notCDom_reduced4SigExtra_T_7 = _notCDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_8 = _notCDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_9 = _notCDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_10 = {_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_11 = _notCDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_12 = _notCDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_13 = _notCDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_14 = {_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20] wire [3:0] _notCDom_reduced4SigExtra_T_15 = {_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_16 = _notCDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22] wire _notCDom_reduced4SigExtra_T_17 = _notCDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_18 = _notCDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_19 = {_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20] wire [5:0] _notCDom_reduced4SigExtra_T_20 = {_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20] wire [6:0] _notCDom_reduced4SigExtra_T_21 = {1'h0, _notCDom_reduced4SigExtra_T_2[5:0] & _notCDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :107:20] wire notCDom_reduced4SigExtra = |_notCDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:247:78, :249:11] wire [25:0] _notCDom_sig_T = notCDom_mainSig[28:3]; // @[MulAddRecFN.scala:243:50, :251:28] wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28] wire _notCDom_sig_T_2 = |_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}] wire _notCDom_sig_T_3 = _notCDom_sig_T_2 | notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}] wire [26:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39] wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[26:25]; // @[MulAddRecFN.scala:251:12, :255:21] wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[primitives.scala:103:54] wire _notCDom_sign_T = ~notCDom_signSigSum; // @[MulAddRecFN.scala:232:36, :259:36] wire notCDom_sign = ~notCDom_completeCancellation & _notCDom_sign_T; // @[MulAddRecFN.scala:255:50, :257:12, :259:36] assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44] wire _io_rawOut_sign_T_4 = notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :287:26] wire _io_invalidExc_T_3 = _io_invalidExc_T_1; // @[MulAddRecFN.scala:271:35, :272:57] assign _io_invalidExc_T_9 = _io_invalidExc_T_3; // @[MulAddRecFN.scala:272:57, :273:57] assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57] assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48] wire _io_rawOut_isZero_T = ~io_fromPreMul_CIsDominant_0; // @[MulAddRecFN.scala:169:7, :283:14] wire _io_rawOut_isZero_T_1 = _io_rawOut_isZero_T & notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:{14,42}] assign _io_rawOut_isZero_T_2 = notNaN_addZeros | _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42] assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25] wire _io_rawOut_sign_T_1 = io_fromPreMul_isInfC_0 & opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :286:31] wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T_1; // @[MulAddRecFN.scala:285:54, :286:31] wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4; // @[MulAddRecFN.scala:287:{26,48}] wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36] wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 | _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36] wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7; // @[MulAddRecFN.scala:286:43, :288:48] wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10] wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31] wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}] wire _io_rawOut_sign_T_15 = io_fromPreMul_CIsDominant_0 ? opSignC : notCDom_sign; // @[MulAddRecFN.scala:169:7, :190:42, :257:12, :292:17] wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17] assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 | _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49] assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50] assign _io_rawOut_sExp_T = io_fromPreMul_CIsDominant_0 ? CDom_sExp : notCDom_sExp; // @[MulAddRecFN.scala:169:7, :203:43, :241:46, :293:26] assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26] assign _io_rawOut_sig_T = io_fromPreMul_CIsDominant_0 ? CDom_sig : notCDom_sig; // @[MulAddRecFN.scala:169:7, :225:12, :251:12, :294:25] assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25] assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_84 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, flip grant : UInt<1>, iss_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip in_uop : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}, out_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip kill : UInt<1>, flip clear : UInt<1>, flip squash_grant : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}}[5], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip child_rebusys : UInt<3>} regreset slot_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg slot_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock wire next_valid : UInt<1> connect next_valid, slot_valid wire next_uop_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect next_uop_out, slot_uop node _next_uop_out_br_mask_T = not(io.brupdate.b1.resolve_mask) node _next_uop_out_br_mask_T_1 = and(slot_uop.br_mask, _next_uop_out_br_mask_T) connect next_uop_out.br_mask, _next_uop_out_br_mask_T_1 wire next_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect next_uop, next_uop_out node _killed_T = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _killed_T_1 = neq(_killed_T, UInt<1>(0h0)) node killed = or(_killed_T_1, io.kill) connect io.valid, slot_valid connect io.out_uop, next_uop node _io_will_be_valid_T = eq(killed, UInt<1>(0h0)) node _io_will_be_valid_T_1 = and(next_valid, _io_will_be_valid_T) connect io.will_be_valid, _io_will_be_valid_T_1 when io.kill : connect slot_valid, UInt<1>(0h0) else : when io.in_uop.valid : connect slot_valid, UInt<1>(0h1) else : when io.clear : connect slot_valid, UInt<1>(0h0) else : node _slot_valid_T = eq(killed, UInt<1>(0h0)) node _slot_valid_T_1 = and(next_valid, _slot_valid_T) connect slot_valid, _slot_valid_T_1 when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T = eq(slot_valid, UInt<1>(0h0)) node _T_1 = or(_T, io.clear) node _T_2 = or(_T_1, io.kill) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:79 assert (!slot_valid || io.clear || io.kill)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert else : connect slot_uop, next_uop connect next_uop.iw_p1_bypass_hint, UInt<1>(0h0) connect next_uop.iw_p2_bypass_hint, UInt<1>(0h0) connect next_uop.iw_p3_bypass_hint, UInt<1>(0h0) connect next_uop.iw_p1_speculative_child, UInt<1>(0h0) connect next_uop.iw_p2_speculative_child, UInt<1>(0h0) wire rebusied_prs1 : UInt<1> connect rebusied_prs1, UInt<1>(0h0) wire rebusied_prs2 : UInt<1> connect rebusied_prs2, UInt<1>(0h0) node rebusied = or(rebusied_prs1, rebusied_prs2) node prs1_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs1) node prs1_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs1) node prs1_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs1) node prs1_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs1) node prs1_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, slot_uop.prs1) node prs2_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs2) node prs2_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs2) node prs2_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs2) node prs2_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs2) node prs2_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, slot_uop.prs2) node prs3_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs3) node prs3_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs3) node prs3_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs3) node prs3_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs3) node prs3_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, slot_uop.prs3) node prs1_wakeups_0 = and(io.wakeup_ports[0].valid, prs1_matches_0) node prs1_wakeups_1 = and(io.wakeup_ports[1].valid, prs1_matches_1) node prs1_wakeups_2 = and(io.wakeup_ports[2].valid, prs1_matches_2) node prs1_wakeups_3 = and(io.wakeup_ports[3].valid, prs1_matches_3) node prs1_wakeups_4 = and(io.wakeup_ports[4].valid, prs1_matches_4) node prs2_wakeups_0 = and(io.wakeup_ports[0].valid, prs2_matches_0) node prs2_wakeups_1 = and(io.wakeup_ports[1].valid, prs2_matches_1) node prs2_wakeups_2 = and(io.wakeup_ports[2].valid, prs2_matches_2) node prs2_wakeups_3 = and(io.wakeup_ports[3].valid, prs2_matches_3) node prs2_wakeups_4 = and(io.wakeup_ports[4].valid, prs2_matches_4) node prs3_wakeups_0 = and(io.wakeup_ports[0].valid, prs3_matches_0) node prs3_wakeups_1 = and(io.wakeup_ports[1].valid, prs3_matches_1) node prs3_wakeups_2 = and(io.wakeup_ports[2].valid, prs3_matches_2) node prs3_wakeups_3 = and(io.wakeup_ports[3].valid, prs3_matches_3) node prs3_wakeups_4 = and(io.wakeup_ports[4].valid, prs3_matches_4) node prs1_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs1_matches_0) node prs1_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs1_matches_1) node prs1_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs1_matches_2) node prs1_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs1_matches_3) node prs1_rebusys_4 = and(io.wakeup_ports[4].bits.rebusy, prs1_matches_4) node prs2_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs2_matches_0) node prs2_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs2_matches_1) node prs2_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs2_matches_2) node prs2_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs2_matches_3) node prs2_rebusys_4 = and(io.wakeup_ports[4].bits.rebusy, prs2_matches_4) node _T_6 = or(prs1_wakeups_0, prs1_wakeups_1) node _T_7 = or(_T_6, prs1_wakeups_2) node _T_8 = or(_T_7, prs1_wakeups_3) node _T_9 = or(_T_8, prs1_wakeups_4) when _T_9 : connect next_uop.prs1_busy, UInt<1>(0h0) node _next_uop_iw_p1_speculative_child_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_2 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_3 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_4 = mux(prs1_wakeups_4, io.wakeup_ports[4].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_5 = or(_next_uop_iw_p1_speculative_child_T, _next_uop_iw_p1_speculative_child_T_1) node _next_uop_iw_p1_speculative_child_T_6 = or(_next_uop_iw_p1_speculative_child_T_5, _next_uop_iw_p1_speculative_child_T_2) node _next_uop_iw_p1_speculative_child_T_7 = or(_next_uop_iw_p1_speculative_child_T_6, _next_uop_iw_p1_speculative_child_T_3) node _next_uop_iw_p1_speculative_child_T_8 = or(_next_uop_iw_p1_speculative_child_T_7, _next_uop_iw_p1_speculative_child_T_4) wire _next_uop_iw_p1_speculative_child_WIRE : UInt<3> connect _next_uop_iw_p1_speculative_child_WIRE, _next_uop_iw_p1_speculative_child_T_8 connect next_uop.iw_p1_speculative_child, _next_uop_iw_p1_speculative_child_WIRE node _next_uop_iw_p1_bypass_hint_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_2 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_3 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_4 = mux(prs1_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_5 = or(_next_uop_iw_p1_bypass_hint_T, _next_uop_iw_p1_bypass_hint_T_1) node _next_uop_iw_p1_bypass_hint_T_6 = or(_next_uop_iw_p1_bypass_hint_T_5, _next_uop_iw_p1_bypass_hint_T_2) node _next_uop_iw_p1_bypass_hint_T_7 = or(_next_uop_iw_p1_bypass_hint_T_6, _next_uop_iw_p1_bypass_hint_T_3) node _next_uop_iw_p1_bypass_hint_T_8 = or(_next_uop_iw_p1_bypass_hint_T_7, _next_uop_iw_p1_bypass_hint_T_4) wire _next_uop_iw_p1_bypass_hint_WIRE : UInt<1> connect _next_uop_iw_p1_bypass_hint_WIRE, _next_uop_iw_p1_bypass_hint_T_8 connect next_uop.iw_p1_bypass_hint, _next_uop_iw_p1_bypass_hint_WIRE node _T_10 = or(prs1_rebusys_0, prs1_rebusys_1) node _T_11 = or(_T_10, prs1_rebusys_2) node _T_12 = or(_T_11, prs1_rebusys_3) node _T_13 = or(_T_12, prs1_rebusys_4) node _T_14 = and(io.child_rebusys, slot_uop.iw_p1_speculative_child) node _T_15 = neq(_T_14, UInt<1>(0h0)) node _T_16 = or(_T_13, _T_15) node _T_17 = eq(slot_uop.lrs1_rtype, UInt<2>(0h0)) node _T_18 = and(_T_16, _T_17) when _T_18 : connect next_uop.prs1_busy, UInt<1>(0h1) connect rebusied_prs1, UInt<1>(0h1) node _T_19 = or(prs2_wakeups_0, prs2_wakeups_1) node _T_20 = or(_T_19, prs2_wakeups_2) node _T_21 = or(_T_20, prs2_wakeups_3) node _T_22 = or(_T_21, prs2_wakeups_4) when _T_22 : connect next_uop.prs2_busy, UInt<1>(0h0) node _next_uop_iw_p2_speculative_child_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_2 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_3 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_4 = mux(prs2_wakeups_4, io.wakeup_ports[4].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_5 = or(_next_uop_iw_p2_speculative_child_T, _next_uop_iw_p2_speculative_child_T_1) node _next_uop_iw_p2_speculative_child_T_6 = or(_next_uop_iw_p2_speculative_child_T_5, _next_uop_iw_p2_speculative_child_T_2) node _next_uop_iw_p2_speculative_child_T_7 = or(_next_uop_iw_p2_speculative_child_T_6, _next_uop_iw_p2_speculative_child_T_3) node _next_uop_iw_p2_speculative_child_T_8 = or(_next_uop_iw_p2_speculative_child_T_7, _next_uop_iw_p2_speculative_child_T_4) wire _next_uop_iw_p2_speculative_child_WIRE : UInt<3> connect _next_uop_iw_p2_speculative_child_WIRE, _next_uop_iw_p2_speculative_child_T_8 connect next_uop.iw_p2_speculative_child, _next_uop_iw_p2_speculative_child_WIRE node _next_uop_iw_p2_bypass_hint_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_2 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_3 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_4 = mux(prs2_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_5 = or(_next_uop_iw_p2_bypass_hint_T, _next_uop_iw_p2_bypass_hint_T_1) node _next_uop_iw_p2_bypass_hint_T_6 = or(_next_uop_iw_p2_bypass_hint_T_5, _next_uop_iw_p2_bypass_hint_T_2) node _next_uop_iw_p2_bypass_hint_T_7 = or(_next_uop_iw_p2_bypass_hint_T_6, _next_uop_iw_p2_bypass_hint_T_3) node _next_uop_iw_p2_bypass_hint_T_8 = or(_next_uop_iw_p2_bypass_hint_T_7, _next_uop_iw_p2_bypass_hint_T_4) wire _next_uop_iw_p2_bypass_hint_WIRE : UInt<1> connect _next_uop_iw_p2_bypass_hint_WIRE, _next_uop_iw_p2_bypass_hint_T_8 connect next_uop.iw_p2_bypass_hint, _next_uop_iw_p2_bypass_hint_WIRE node _T_23 = or(prs2_rebusys_0, prs2_rebusys_1) node _T_24 = or(_T_23, prs2_rebusys_2) node _T_25 = or(_T_24, prs2_rebusys_3) node _T_26 = or(_T_25, prs2_rebusys_4) node _T_27 = and(io.child_rebusys, slot_uop.iw_p2_speculative_child) node _T_28 = neq(_T_27, UInt<1>(0h0)) node _T_29 = or(_T_26, _T_28) node _T_30 = eq(slot_uop.lrs2_rtype, UInt<2>(0h0)) node _T_31 = and(_T_29, _T_30) when _T_31 : connect next_uop.prs2_busy, UInt<1>(0h1) connect rebusied_prs2, UInt<1>(0h1) node _T_32 = or(prs3_wakeups_0, prs3_wakeups_1) node _T_33 = or(_T_32, prs3_wakeups_2) node _T_34 = or(_T_33, prs3_wakeups_3) node _T_35 = or(_T_34, prs3_wakeups_4) when _T_35 : connect next_uop.prs3_busy, UInt<1>(0h0) node _next_uop_iw_p3_bypass_hint_T = mux(prs3_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_1 = mux(prs3_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_2 = mux(prs3_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_3 = mux(prs3_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_4 = mux(prs3_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_5 = or(_next_uop_iw_p3_bypass_hint_T, _next_uop_iw_p3_bypass_hint_T_1) node _next_uop_iw_p3_bypass_hint_T_6 = or(_next_uop_iw_p3_bypass_hint_T_5, _next_uop_iw_p3_bypass_hint_T_2) node _next_uop_iw_p3_bypass_hint_T_7 = or(_next_uop_iw_p3_bypass_hint_T_6, _next_uop_iw_p3_bypass_hint_T_3) node _next_uop_iw_p3_bypass_hint_T_8 = or(_next_uop_iw_p3_bypass_hint_T_7, _next_uop_iw_p3_bypass_hint_T_4) wire _next_uop_iw_p3_bypass_hint_WIRE : UInt<1> connect _next_uop_iw_p3_bypass_hint_WIRE, _next_uop_iw_p3_bypass_hint_T_8 connect next_uop.iw_p3_bypass_hint, _next_uop_iw_p3_bypass_hint_WIRE node _T_36 = eq(io.pred_wakeup_port.bits, slot_uop.ppred) node _T_37 = and(io.pred_wakeup_port.valid, _T_36) when _T_37 : connect next_uop.ppred_busy, UInt<1>(0h0) node _iss_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0)) node _iss_ready_T_1 = eq(slot_uop.prs2_busy, UInt<1>(0h0)) node _iss_ready_T_2 = and(_iss_ready_T, _iss_ready_T_1) node _iss_ready_T_3 = and(slot_uop.ppred_busy, UInt<1>(0h1)) node _iss_ready_T_4 = eq(_iss_ready_T_3, UInt<1>(0h0)) node _iss_ready_T_5 = and(_iss_ready_T_2, _iss_ready_T_4) node _iss_ready_T_6 = and(slot_uop.prs3_busy, UInt<1>(0h0)) node _iss_ready_T_7 = eq(_iss_ready_T_6, UInt<1>(0h0)) node iss_ready = and(_iss_ready_T_5, _iss_ready_T_7) node _agen_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0)) node _agen_ready_T_1 = and(slot_uop.fu_code[1], _agen_ready_T) node _agen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1)) node _agen_ready_T_3 = eq(_agen_ready_T_2, UInt<1>(0h0)) node _agen_ready_T_4 = and(_agen_ready_T_1, _agen_ready_T_3) node agen_ready = and(_agen_ready_T_4, UInt<1>(0h0)) node _dgen_ready_T = eq(slot_uop.prs2_busy, UInt<1>(0h0)) node _dgen_ready_T_1 = and(slot_uop.fu_code[2], _dgen_ready_T) node _dgen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1)) node _dgen_ready_T_3 = eq(_dgen_ready_T_2, UInt<1>(0h0)) node _dgen_ready_T_4 = and(_dgen_ready_T_1, _dgen_ready_T_3) node dgen_ready = and(_dgen_ready_T_4, UInt<1>(0h0)) node _io_request_T = eq(slot_uop.iw_issued, UInt<1>(0h0)) node _io_request_T_1 = and(slot_valid, _io_request_T) node _io_request_T_2 = or(iss_ready, agen_ready) node _io_request_T_3 = or(_io_request_T_2, dgen_ready) node _io_request_T_4 = and(_io_request_T_1, _io_request_T_3) connect io.request, _io_request_T_4 connect io.iss_uop, slot_uop connect next_uop.iw_issued, UInt<1>(0h0) connect next_uop.iw_issued_partial_agen, UInt<1>(0h0) connect next_uop.iw_issued_partial_dgen, UInt<1>(0h0) node _T_38 = eq(io.squash_grant, UInt<1>(0h0)) node _T_39 = and(io.grant, _T_38) when _T_39 : connect next_uop.iw_issued, UInt<1>(0h1) node _T_40 = and(slot_valid, slot_uop.iw_issued) when _T_40 : connect next_valid, rebusied
module IssueSlot_84( // @[issue-slot.scala:49:7] input clock, // @[issue-slot.scala:49:7] input reset, // @[issue-slot.scala:49:7] output io_valid, // @[issue-slot.scala:52:14] output io_will_be_valid, // @[issue-slot.scala:52:14] output io_request, // @[issue-slot.scala:52:14] input io_grant, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14] output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14] output io_iss_uop_is_fence, // @[issue-slot.scala:52:14] output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14] output io_iss_uop_is_amo, // @[issue-slot.scala:52:14] output io_iss_uop_is_eret, // @[issue-slot.scala:52:14] output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14] output io_iss_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14] output io_iss_uop_taken, // @[issue-slot.scala:52:14] output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14] output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_iss_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14] output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14] output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14] output io_iss_uop_is_unique, // @[issue-slot.scala:52:14] output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14] output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14] output io_iss_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_in_uop_valid, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14] input io_in_uop_bits_taken, // @[issue-slot.scala:52:14] input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14] input io_in_uop_bits_exception, // @[issue-slot.scala:52:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14] input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14] output io_out_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14] output io_out_uop_is_sfb, // @[issue-slot.scala:52:14] output io_out_uop_is_fence, // @[issue-slot.scala:52:14] output io_out_uop_is_fencei, // @[issue-slot.scala:52:14] output io_out_uop_is_sfence, // @[issue-slot.scala:52:14] output io_out_uop_is_amo, // @[issue-slot.scala:52:14] output io_out_uop_is_eret, // @[issue-slot.scala:52:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_out_uop_is_rocc, // @[issue-slot.scala:52:14] output io_out_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_out_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14] output io_out_uop_taken, // @[issue-slot.scala:52:14] output io_out_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_out_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14] output io_out_uop_mem_signed, // @[issue-slot.scala:52:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_out_uop_uses_stq, // @[issue-slot.scala:52:14] output io_out_uop_is_unique, // @[issue-slot.scala:52:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_out_uop_frs3_en, // @[issue-slot.scala:52:14] output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14] output io_out_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14] input io_brupdate_b2_taken, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14] input io_kill, // @[issue-slot.scala:52:14] input io_clear, // @[issue-slot.scala:52:14] input io_squash_grant, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_bypassable, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_rebusy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_4_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_4_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_4_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_4_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_4_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_4_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_4_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_4_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_pred_wakeup_port_valid, // @[issue-slot.scala:52:14] input [4:0] io_pred_wakeup_port_bits, // @[issue-slot.scala:52:14] input [2:0] io_child_rebusys // @[issue-slot.scala:52:14] ); wire [15:0] next_uop_out_br_mask; // @[util.scala:104:23] wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7] wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7] wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_4_bits_uop_inst_0 = io_wakeup_ports_4_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_4_bits_uop_debug_inst_0 = io_wakeup_ports_4_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_rvc_0 = io_wakeup_ports_4_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_4_bits_uop_debug_pc_0 = io_wakeup_ports_4_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_0_0 = io_wakeup_ports_4_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_1_0 = io_wakeup_ports_4_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_2_0 = io_wakeup_ports_4_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_3_0 = io_wakeup_ports_4_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_0_0 = io_wakeup_ports_4_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_1_0 = io_wakeup_ports_4_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_2_0 = io_wakeup_ports_4_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_3_0 = io_wakeup_ports_4_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_4_0 = io_wakeup_ports_4_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_5_0 = io_wakeup_ports_4_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_6_0 = io_wakeup_ports_4_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_7_0 = io_wakeup_ports_4_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_8_0 = io_wakeup_ports_4_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_9_0 = io_wakeup_ports_4_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_0 = io_wakeup_ports_4_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel_0 = io_wakeup_ports_4_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_4_bits_uop_br_mask_0 = io_wakeup_ports_4_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_4_bits_uop_br_tag_0 = io_wakeup_ports_4_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_4_bits_uop_br_type_0 = io_wakeup_ports_4_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sfb_0 = io_wakeup_ports_4_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_fence_0 = io_wakeup_ports_4_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_fencei_0 = io_wakeup_ports_4_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sfence_0 = io_wakeup_ports_4_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_amo_0 = io_wakeup_ports_4_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_eret_0 = io_wakeup_ports_4_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_4_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_rocc_0 = io_wakeup_ports_4_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_mov_0 = io_wakeup_ports_4_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ftq_idx_0 = io_wakeup_ports_4_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_edge_inst_0 = io_wakeup_ports_4_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_pc_lob_0 = io_wakeup_ports_4_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_taken_0 = io_wakeup_ports_4_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_imm_rename_0 = io_wakeup_ports_4_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_imm_sel_0 = io_wakeup_ports_4_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_pimm_0 = io_wakeup_ports_4_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_4_bits_uop_imm_packed_0 = io_wakeup_ports_4_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_op1_sel_0 = io_wakeup_ports_4_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_op2_sel_0 = io_wakeup_ports_4_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_rob_idx_0 = io_wakeup_ports_4_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ldq_idx_0 = io_wakeup_ports_4_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_stq_idx_0 = io_wakeup_ports_4_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_rxq_idx_0 = io_wakeup_ports_4_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_pdst_0 = io_wakeup_ports_4_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs1_0 = io_wakeup_ports_4_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs2_0 = io_wakeup_ports_4_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs3_0 = io_wakeup_ports_4_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ppred_0 = io_wakeup_ports_4_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs1_busy_0 = io_wakeup_ports_4_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs2_busy_0 = io_wakeup_ports_4_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs3_busy_0 = io_wakeup_ports_4_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_ppred_busy_0 = io_wakeup_ports_4_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_stale_pdst_0 = io_wakeup_ports_4_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_exception_0 = io_wakeup_ports_4_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_4_bits_uop_exc_cause_0 = io_wakeup_ports_4_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_mem_cmd_0 = io_wakeup_ports_4_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_mem_size_0 = io_wakeup_ports_4_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_mem_signed_0 = io_wakeup_ports_4_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_uses_ldq_0 = io_wakeup_ports_4_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_uses_stq_0 = io_wakeup_ports_4_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_unique_0 = io_wakeup_ports_4_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_flush_on_commit_0 = io_wakeup_ports_4_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_csr_cmd_0 = io_wakeup_ports_4_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_4_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_ldst_0 = io_wakeup_ports_4_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs1_0 = io_wakeup_ports_4_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs2_0 = io_wakeup_ports_4_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs3_0 = io_wakeup_ports_4_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_dst_rtype_0 = io_wakeup_ports_4_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype_0 = io_wakeup_ports_4_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype_0 = io_wakeup_ports_4_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_frs3_en_0 = io_wakeup_ports_4_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fcn_dw_0 = io_wakeup_ports_4_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_fcn_op_0 = io_wakeup_ports_4_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_val_0 = io_wakeup_ports_4_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_fp_rm_0 = io_wakeup_ports_4_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_typ_0 = io_wakeup_ports_4_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_4_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_bp_debug_if_0 = io_wakeup_ports_4_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_4_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc_0 = io_wakeup_ports_4_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc_0 = io_wakeup_ports_4_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_pred_wakeup_port_valid_0 = io_pred_wakeup_port_valid; // @[issue-slot.scala:49:7] wire [4:0] io_pred_wakeup_port_bits_0 = io_pred_wakeup_port_bits; // @[issue-slot.scala:49:7] wire [2:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23] wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23] wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28] wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28] wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_2 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_3 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_4 = 1'h0; // @[issue-slot.scala:102:91] wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_2 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_3 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_4 = 1'h0; // @[issue-slot.scala:103:91] wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _iss_ready_T_6 = 1'h0; // @[issue-slot.scala:136:131] wire agen_ready = 1'h0; // @[issue-slot.scala:137:114] wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114] wire [2:0] io_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] _next_uop_iw_p1_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p2_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire _iss_ready_T_7 = 1'h1; // @[issue-slot.scala:136:110] wire [2:0] io_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-slot.scala:49:7] wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34] wire _io_request_T_4; // @[issue-slot.scala:140:51] wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28] wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28] wire next_uop_is_rvc; // @[issue-slot.scala:59:28] wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28] wire next_uop_iq_type_0; // @[issue-slot.scala:59:28] wire next_uop_iq_type_1; // @[issue-slot.scala:59:28] wire next_uop_iq_type_2; // @[issue-slot.scala:59:28] wire next_uop_iq_type_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_0; // @[issue-slot.scala:59:28] wire next_uop_fu_code_1; // @[issue-slot.scala:59:28] wire next_uop_fu_code_2; // @[issue-slot.scala:59:28] wire next_uop_fu_code_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_4; // @[issue-slot.scala:59:28] wire next_uop_fu_code_5; // @[issue-slot.scala:59:28] wire next_uop_fu_code_6; // @[issue-slot.scala:59:28] wire next_uop_fu_code_7; // @[issue-slot.scala:59:28] wire next_uop_fu_code_8; // @[issue-slot.scala:59:28] wire next_uop_fu_code_9; // @[issue-slot.scala:59:28] wire next_uop_iw_issued; // @[issue-slot.scala:59:28] wire [2:0] next_uop_iw_p1_speculative_child; // @[issue-slot.scala:59:28] wire [2:0] next_uop_iw_p2_speculative_child; // @[issue-slot.scala:59:28] wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28] wire [2:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28] wire [15:0] next_uop_br_mask; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28] wire next_uop_is_sfb; // @[issue-slot.scala:59:28] wire next_uop_is_fence; // @[issue-slot.scala:59:28] wire next_uop_is_fencei; // @[issue-slot.scala:59:28] wire next_uop_is_sfence; // @[issue-slot.scala:59:28] wire next_uop_is_amo; // @[issue-slot.scala:59:28] wire next_uop_is_eret; // @[issue-slot.scala:59:28] wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28] wire next_uop_is_rocc; // @[issue-slot.scala:59:28] wire next_uop_is_mov; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28] wire next_uop_edge_inst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28] wire next_uop_taken; // @[issue-slot.scala:59:28] wire next_uop_imm_rename; // @[issue-slot.scala:59:28] wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28] wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28] wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28] wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28] wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28] wire [6:0] next_uop_rob_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_stq_idx; // @[issue-slot.scala:59:28] wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28] wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28] wire next_uop_prs1_busy; // @[issue-slot.scala:59:28] wire next_uop_prs2_busy; // @[issue-slot.scala:59:28] wire next_uop_prs3_busy; // @[issue-slot.scala:59:28] wire next_uop_ppred_busy; // @[issue-slot.scala:59:28] wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28] wire next_uop_exception; // @[issue-slot.scala:59:28] wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28] wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28] wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28] wire next_uop_mem_signed; // @[issue-slot.scala:59:28] wire next_uop_uses_ldq; // @[issue-slot.scala:59:28] wire next_uop_uses_stq; // @[issue-slot.scala:59:28] wire next_uop_is_unique; // @[issue-slot.scala:59:28] wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28] wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28] wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28] wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28] wire next_uop_frs3_en; // @[issue-slot.scala:59:28] wire next_uop_fcn_dw; // @[issue-slot.scala:59:28] wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28] wire next_uop_fp_val; // @[issue-slot.scala:59:28] wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28] wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28] wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28] wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28] wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7] wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_out_uop_taken_0; // @[issue-slot.scala:49:7] wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_out_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_valid_0; // @[issue-slot.scala:49:7] wire io_will_be_valid_0; // @[issue-slot.scala:49:7] wire io_request_0; // @[issue-slot.scala:49:7] reg slot_valid; // @[issue-slot.scala:55:27] assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27] reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23] reg slot_uop_is_rvc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21] wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23] reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23] reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23] reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23] reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23] reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23] reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23] reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23] reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23] reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23] reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23] reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23] reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23] reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23] reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23] reg slot_uop_iw_issued; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23] reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23] reg [2:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:56:21] assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21] assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23] reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21] assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23] reg slot_uop_is_sfb; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23] reg slot_uop_is_fence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23] reg slot_uop_is_fencei; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23] reg slot_uop_is_sfence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23] reg slot_uop_is_amo; // @[issue-slot.scala:56:21] assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23] reg slot_uop_is_eret; // @[issue-slot.scala:56:21] assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23] reg slot_uop_is_rocc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23] reg slot_uop_is_mov; // @[issue-slot.scala:56:21] assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23] reg slot_uop_edge_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21] assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23] reg slot_uop_taken; // @[issue-slot.scala:56:21] assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23] reg slot_uop_imm_rename; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23] reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23] reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21] assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21] wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23] reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23] reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23] reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23] reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23] reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23] reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23] reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23] reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23] reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23] wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88] wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95] wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23] reg slot_uop_exception; // @[issue-slot.scala:56:21] assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21] assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21] wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23] reg slot_uop_mem_signed; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23] reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23] reg slot_uop_uses_stq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23] reg slot_uop_is_unique; // @[issue-slot.scala:56:21] assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23] reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21] assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23] reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23] reg slot_uop_frs3_en; // @[issue-slot.scala:56:21] assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23] reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23] reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23] reg slot_uop_fp_val; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23] reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23] reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23] reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23] reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23] wire next_valid; // @[issue-slot.scala:58:28] assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23] assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23] assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23] assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23] assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23] assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23] assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23] assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23] assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23] assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23] assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23] assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23] assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23] assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23] assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23] assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23] assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23] assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25] assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23] assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23] assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23] assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23] assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23] assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23] assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23] assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23] assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23] assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23] assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23] assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23] assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23] assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23] assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23] assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23] assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23] assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23] assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23] assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23] assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23] assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23] assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23] assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23] assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23] assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23] assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23] assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23] assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23] assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23] assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23] assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23] assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23] assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23] assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23] assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23] assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23] assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23] assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23] assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23] assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23] assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23] assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23] assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23] assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23] assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23] assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23] assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23] assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23] assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23] assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23] assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23] assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23] assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23] assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23] assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23] assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23] assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23] assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23] assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23] assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23] assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23] assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23] assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23] assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23] assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23] assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23] assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23] assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23] assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23] assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23] assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23] assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23] assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28] wire [15:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51] wire _killed_T_1 = |_killed_T; // @[util.scala:126:{51,59}] wire killed = _killed_T_1 | io_kill_0; // @[util.scala:61:61, :126:59] wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61] assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}] assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34] wire _slot_valid_T = ~killed; // @[util.scala:61:61] wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_48 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_56 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0
module AsyncResetSynchronizerShiftReg_w1_d3_i0_48( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_56 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_297 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_297( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module Tile_74 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_330 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a
module Tile_74( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_330 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_105 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_105( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_25 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<4>, sig : UInt<2>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node _sAdjustedExp_T = add(io.in.sExp, asSInt(UInt<9>(0hfc))) node _sAdjustedExp_T_1 = bits(_sAdjustedExp_T, 8, 0) node sAdjustedExp = cvt(_sAdjustedExp_T_1) node adjustedSig = shl(io.in.sig, 25) wire common_expOut : UInt<9> wire common_fractOut : UInt<23> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _common_expOut_T = bits(sAdjustedExp, 8, 0) node _common_expOut_T_1 = add(_common_expOut_T, UInt<1>(0h0)) node _common_expOut_T_2 = tail(_common_expOut_T_1, 1) connect common_expOut, _common_expOut_T_2 node _common_fractOut_T = bits(adjustedSig, 25, 3) node _common_fractOut_T_1 = bits(adjustedSig, 24, 2) node _common_fractOut_T_2 = mux(UInt<1>(0h0), _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 connect common_overflow, UInt<1>(0h0) connect common_totalUnderflow, UInt<1>(0h0) connect common_underflow, UInt<1>(0h0) connect common_inexact, UInt<1>(0h0) node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<9>(0h6b)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3
module RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_25(); // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [26:0] adjustedSig = 27'h2000000; // @[RoundAnyRawFNToRecFN.scala:114:22] wire [22:0] _common_fractOut_T = 23'h400000; // @[RoundAnyRawFNToRecFN.scala:139:28] wire [8:0] _expOut_T_2 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_12 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_1 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_11 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_18 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_20 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _sAdjustedExp_T_1 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] common_expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _common_expOut_T = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _common_expOut_T_2 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_3 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_7 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_10 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_13 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_15 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_17 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_19 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [22:0] common_fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _common_fractOut_T_1 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _common_fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_3 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [9:0] _sAdjustedExp_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:104:25, :136:55, :286:23] wire [9:0] sAdjustedExp = 10'h100; // @[RoundAnyRawFNToRecFN.scala:106:31, :136:55, :286:23] wire [9:0] _common_expOut_T_1 = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23] wire [9:0] _io_out_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23] wire [1:0] _io_exceptionFlags_T = 2'h0; // @[RoundAnyRawFNToRecFN.scala:288:23] wire [3:0] _io_exceptionFlags_T_2 = 4'h0; // @[RoundAnyRawFNToRecFN.scala:288:53] wire [4:0] io_exceptionFlags = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66] wire [4:0] _io_exceptionFlags_T_3 = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66] wire [32:0] io_out = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33] wire [32:0] _io_out_T_1 = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _roundMagUp_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_2 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_3 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire commonCase = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41] wire [2:0] _io_exceptionFlags_T_1 = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41] wire [1:0] io_in_sig = 2'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16] wire [3:0] io_in_sExp = 4'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16] wire io_invalidExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire common_overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:124:37] wire common_totalUnderflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:125:37] wire common_underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:126:37] wire common_inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:127:37] wire isNaNOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:235:34] wire notNaN_isSpecialInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:236:49] wire overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:238:32] wire underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:239:32] wire _inexact_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:43] wire inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:28] wire _pegMinNonzeroMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:20] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire _notNaN_isInfOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:45] wire notNaN_isInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:32] wire signOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:250:22] wire _expOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:253:32] wire _fractOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:22] wire _fractOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:38] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_170 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip
module PriorityQueueStage_170( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IntXbar_i4_o1_2 : output auto : { flip anon_in_3 : UInt<1>[1], flip anon_in_2 : UInt<1>[1], flip anon_in_1 : UInt<1>[2], flip anon_in_0 : UInt<1>[1], anon_out : UInt<1>[5]} wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset wire anonIn : UInt<1>[1] invalidate anonIn[0] wire anonIn_1 : UInt<1>[2] invalidate anonIn_1[0] invalidate anonIn_1[1] wire anonIn_2 : UInt<1>[1] invalidate anonIn_2[0] wire anonIn_3 : UInt<1>[1] invalidate anonIn_3[0] wire anonOut : UInt<1>[5] invalidate anonOut[0] invalidate anonOut[1] invalidate anonOut[2] invalidate anonOut[3] invalidate anonOut[4] connect auto.anon_out, anonOut connect anonIn, auto.anon_in_0 connect anonIn_1, auto.anon_in_1 connect anonIn_2, auto.anon_in_2 connect anonIn_3, auto.anon_in_3 connect anonOut[0], anonIn[0] connect anonOut[1], anonIn_1[0] connect anonOut[2], anonIn_1[1] connect anonOut[3], anonIn_2[0] connect anonOut[4], anonIn_3[0]
module IntXbar_i4_o1_2( // @[Xbar.scala:22:9] input auto_anon_in_3_0, // @[LazyModuleImp.scala:107:25] input auto_anon_in_2_0, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_0, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_1, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_0, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1, // @[LazyModuleImp.scala:107:25] output auto_anon_out_2, // @[LazyModuleImp.scala:107:25] output auto_anon_out_3, // @[LazyModuleImp.scala:107:25] output auto_anon_out_4 // @[LazyModuleImp.scala:107:25] ); wire auto_anon_in_3_0_0 = auto_anon_in_3_0; // @[Xbar.scala:22:9] wire auto_anon_in_2_0_0 = auto_anon_in_2_0; // @[Xbar.scala:22:9] wire auto_anon_in_1_0_0 = auto_anon_in_1_0; // @[Xbar.scala:22:9] wire auto_anon_in_1_1_0 = auto_anon_in_1_1; // @[Xbar.scala:22:9] wire auto_anon_in_0_0_0 = auto_anon_in_0_0; // @[Xbar.scala:22:9] wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire anonIn_3_0 = auto_anon_in_3_0_0; // @[Xbar.scala:22:9] wire anonIn_2_0 = auto_anon_in_2_0_0; // @[Xbar.scala:22:9] wire anonIn_1_0 = auto_anon_in_1_0_0; // @[Xbar.scala:22:9] wire anonIn_1_1 = auto_anon_in_1_1_0; // @[Xbar.scala:22:9] wire anonIn_0 = auto_anon_in_0_0_0; // @[Xbar.scala:22:9] wire anonOut_0; // @[MixedNode.scala:542:17] wire anonOut_1; // @[MixedNode.scala:542:17] wire anonOut_2; // @[MixedNode.scala:542:17] wire anonOut_3; // @[MixedNode.scala:542:17] wire anonOut_4; // @[MixedNode.scala:542:17] wire auto_anon_out_0_0; // @[Xbar.scala:22:9] wire auto_anon_out_1_0; // @[Xbar.scala:22:9] wire auto_anon_out_2_0; // @[Xbar.scala:22:9] wire auto_anon_out_3_0; // @[Xbar.scala:22:9] wire auto_anon_out_4_0; // @[Xbar.scala:22:9] assign anonOut_0 = anonIn_0; // @[MixedNode.scala:542:17, :551:17] assign anonOut_1 = anonIn_1_0; // @[MixedNode.scala:542:17, :551:17] assign anonOut_2 = anonIn_1_1; // @[MixedNode.scala:542:17, :551:17] assign anonOut_3 = anonIn_2_0; // @[MixedNode.scala:542:17, :551:17] assign anonOut_4 = anonIn_3_0; // @[MixedNode.scala:542:17, :551:17] assign auto_anon_out_0_0 = anonOut_0; // @[Xbar.scala:22:9] assign auto_anon_out_1_0 = anonOut_1; // @[Xbar.scala:22:9] assign auto_anon_out_2_0 = anonOut_2; // @[Xbar.scala:22:9] assign auto_anon_out_3_0 = anonOut_3; // @[Xbar.scala:22:9] assign auto_anon_out_4_0 = anonOut_4; // @[Xbar.scala:22:9] assign auto_anon_out_0 = auto_anon_out_0_0; // @[Xbar.scala:22:9] assign auto_anon_out_1 = auto_anon_out_1_0; // @[Xbar.scala:22:9] assign auto_anon_out_2 = auto_anon_out_2_0; // @[Xbar.scala:22:9] assign auto_anon_out_3 = auto_anon_out_3_0; // @[Xbar.scala:22:9] assign auto_anon_out_4 = auto_anon_out_4_0; // @[Xbar.scala:22:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_195 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_355 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0
module AsyncResetSynchronizerShiftReg_w1_d3_i0_195( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_355 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module NonSyncResetSynchronizerPrimitiveShiftReg_d3_7 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} reg sync_0 : UInt<1>, clock reg sync_1 : UInt<1>, clock reg sync_2 : UInt<1>, clock node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0
module NonSyncResetSynchronizerPrimitiveShiftReg_d3_7( // @[SynchronizerReg.scala:37:15] input clock, // @[SynchronizerReg.scala:37:15] input reset, // @[SynchronizerReg.scala:37:15] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:37:15] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:37:15, :54:22] wire io_q_0; // @[SynchronizerReg.scala:37:15] reg sync_0; // @[SynchronizerReg.scala:51:66] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:37:15, :51:66] reg sync_1; // @[SynchronizerReg.scala:51:66] reg sync_2; // @[SynchronizerReg.scala:51:66] always @(posedge clock) begin // @[SynchronizerReg.scala:37:15] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:66] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:66] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:66, :54:22] always @(posedge) assign io_q = io_q_0; // @[SynchronizerReg.scala:37:15] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TileResetSetter : input clock : Clock input reset : Reset output auto : { flip clock_in : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}, clock_out : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}, flip tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire tlNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate tlNodeIn.d.bits.corrupt invalidate tlNodeIn.d.bits.data invalidate tlNodeIn.d.bits.denied invalidate tlNodeIn.d.bits.sink invalidate tlNodeIn.d.bits.source invalidate tlNodeIn.d.bits.size invalidate tlNodeIn.d.bits.param invalidate tlNodeIn.d.bits.opcode invalidate tlNodeIn.d.valid invalidate tlNodeIn.d.ready invalidate tlNodeIn.a.bits.corrupt invalidate tlNodeIn.a.bits.data invalidate tlNodeIn.a.bits.mask invalidate tlNodeIn.a.bits.address invalidate tlNodeIn.a.bits.source invalidate tlNodeIn.a.bits.size invalidate tlNodeIn.a.bits.param invalidate tlNodeIn.a.bits.opcode invalidate tlNodeIn.a.valid invalidate tlNodeIn.a.ready inst monitor of TLMonitor_90 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, tlNodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, tlNodeIn.d.bits.data connect monitor.io.in.d.bits.denied, tlNodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, tlNodeIn.d.bits.sink connect monitor.io.in.d.bits.source, tlNodeIn.d.bits.source connect monitor.io.in.d.bits.size, tlNodeIn.d.bits.size connect monitor.io.in.d.bits.param, tlNodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, tlNodeIn.d.bits.opcode connect monitor.io.in.d.valid, tlNodeIn.d.valid connect monitor.io.in.d.ready, tlNodeIn.d.ready connect monitor.io.in.a.bits.corrupt, tlNodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, tlNodeIn.a.bits.data connect monitor.io.in.a.bits.mask, tlNodeIn.a.bits.mask connect monitor.io.in.a.bits.address, tlNodeIn.a.bits.address connect monitor.io.in.a.bits.source, tlNodeIn.a.bits.source connect monitor.io.in.a.bits.size, tlNodeIn.a.bits.size connect monitor.io.in.a.bits.param, tlNodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, tlNodeIn.a.bits.opcode connect monitor.io.in.a.valid, tlNodeIn.a.valid connect monitor.io.in.a.ready, tlNodeIn.a.ready wire clockNodeOut : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}} invalidate clockNodeOut.member.allClocks_uncore.reset invalidate clockNodeOut.member.allClocks_uncore.clock wire clockNodeIn : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}} invalidate clockNodeIn.member.allClocks_uncore.reset invalidate clockNodeIn.member.allClocks_uncore.clock connect clockNodeOut, clockNodeIn connect tlNodeIn, auto.tl_in connect auto.clock_out, clockNodeOut connect clockNodeIn, auto.clock_in wire tile_async_resets : Reset[0] connect clockNodeOut.member.allClocks_uncore.clock, clockNodeIn.member.allClocks_uncore.clock connect clockNodeOut.member.allClocks_uncore.reset, clockNodeIn.member.allClocks_uncore.reset extmodule plusarg_reader_192 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_193 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32
module TileResetSetter( // @[TileResetSetter.scala:26:25] input clock, // @[TileResetSetter.scala:26:25] input reset, // @[TileResetSetter.scala:26:25] input auto_clock_in_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_clock_out_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] output auto_clock_out_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [20:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_in_d_ready // @[LazyModuleImp.scala:107:25] ); wire auto_clock_in_member_allClocks_uncore_clock_0 = auto_clock_in_member_allClocks_uncore_clock; // @[TileResetSetter.scala:26:25] wire auto_clock_in_member_allClocks_uncore_reset_0 = auto_clock_in_member_allClocks_uncore_reset; // @[TileResetSetter.scala:26:25] wire auto_tl_in_a_valid_0 = auto_tl_in_a_valid; // @[TileResetSetter.scala:26:25] wire [2:0] auto_tl_in_a_bits_opcode_0 = auto_tl_in_a_bits_opcode; // @[TileResetSetter.scala:26:25] wire [2:0] auto_tl_in_a_bits_param_0 = auto_tl_in_a_bits_param; // @[TileResetSetter.scala:26:25] wire [1:0] auto_tl_in_a_bits_size_0 = auto_tl_in_a_bits_size; // @[TileResetSetter.scala:26:25] wire [10:0] auto_tl_in_a_bits_source_0 = auto_tl_in_a_bits_source; // @[TileResetSetter.scala:26:25] wire [20:0] auto_tl_in_a_bits_address_0 = auto_tl_in_a_bits_address; // @[TileResetSetter.scala:26:25] wire [7:0] auto_tl_in_a_bits_mask_0 = auto_tl_in_a_bits_mask; // @[TileResetSetter.scala:26:25] wire [63:0] auto_tl_in_a_bits_data_0 = auto_tl_in_a_bits_data; // @[TileResetSetter.scala:26:25] wire auto_tl_in_a_bits_corrupt_0 = auto_tl_in_a_bits_corrupt; // @[TileResetSetter.scala:26:25] wire auto_tl_in_d_ready_0 = auto_tl_in_d_ready; // @[TileResetSetter.scala:26:25] wire [63:0] auto_tl_in_d_bits_data = 64'h0; // @[TileResetSetter.scala:26:25] wire [63:0] tlNodeIn_d_bits_data = 64'h0; // @[MixedNode.scala:551:17] wire [10:0] auto_tl_in_d_bits_source = 11'h0; // @[TileResetSetter.scala:26:25] wire [10:0] tlNodeIn_d_bits_source = 11'h0; // @[MixedNode.scala:551:17] wire [1:0] auto_tl_in_d_bits_param = 2'h0; // @[TileResetSetter.scala:26:25] wire [1:0] auto_tl_in_d_bits_size = 2'h0; // @[TileResetSetter.scala:26:25] wire [1:0] tlNodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] tlNodeIn_d_bits_size = 2'h0; // @[MixedNode.scala:551:17] wire [2:0] auto_tl_in_d_bits_opcode = 3'h0; // @[TileResetSetter.scala:26:25] wire [2:0] tlNodeIn_d_bits_opcode = 3'h0; // @[MixedNode.scala:551:17] wire auto_tl_in_a_ready = 1'h0; // @[TileResetSetter.scala:26:25] wire auto_tl_in_d_valid = 1'h0; // @[TileResetSetter.scala:26:25] wire auto_tl_in_d_bits_sink = 1'h0; // @[TileResetSetter.scala:26:25] wire auto_tl_in_d_bits_denied = 1'h0; // @[TileResetSetter.scala:26:25] wire auto_tl_in_d_bits_corrupt = 1'h0; // @[TileResetSetter.scala:26:25] wire tlNodeIn_a_ready = 1'h0; // @[MixedNode.scala:551:17] wire tlNodeIn_d_valid = 1'h0; // @[MixedNode.scala:551:17] wire tlNodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire tlNodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire tlNodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire clockNodeIn_member_allClocks_uncore_clock = auto_clock_in_member_allClocks_uncore_clock_0; // @[MixedNode.scala:551:17] wire clockNodeOut_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17] wire clockNodeIn_member_allClocks_uncore_reset = auto_clock_in_member_allClocks_uncore_reset_0; // @[MixedNode.scala:551:17] wire clockNodeOut_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17] wire tlNodeIn_a_valid = auto_tl_in_a_valid_0; // @[MixedNode.scala:551:17] wire [2:0] tlNodeIn_a_bits_opcode = auto_tl_in_a_bits_opcode_0; // @[MixedNode.scala:551:17] wire [2:0] tlNodeIn_a_bits_param = auto_tl_in_a_bits_param_0; // @[MixedNode.scala:551:17] wire [1:0] tlNodeIn_a_bits_size = auto_tl_in_a_bits_size_0; // @[MixedNode.scala:551:17] wire [10:0] tlNodeIn_a_bits_source = auto_tl_in_a_bits_source_0; // @[MixedNode.scala:551:17] wire [20:0] tlNodeIn_a_bits_address = auto_tl_in_a_bits_address_0; // @[MixedNode.scala:551:17] wire [7:0] tlNodeIn_a_bits_mask = auto_tl_in_a_bits_mask_0; // @[MixedNode.scala:551:17] wire [63:0] tlNodeIn_a_bits_data = auto_tl_in_a_bits_data_0; // @[MixedNode.scala:551:17] wire tlNodeIn_a_bits_corrupt = auto_tl_in_a_bits_corrupt_0; // @[MixedNode.scala:551:17] wire tlNodeIn_d_ready = auto_tl_in_d_ready_0; // @[MixedNode.scala:551:17] wire auto_clock_out_member_allClocks_uncore_clock_0; // @[TileResetSetter.scala:26:25] wire auto_clock_out_member_allClocks_uncore_reset_0; // @[TileResetSetter.scala:26:25] assign auto_clock_out_member_allClocks_uncore_clock_0 = clockNodeOut_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17] assign auto_clock_out_member_allClocks_uncore_reset_0 = clockNodeOut_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17] assign clockNodeOut_member_allClocks_uncore_clock = clockNodeIn_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNodeOut_member_allClocks_uncore_reset = clockNodeIn_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17, :551:17] TLMonitor_90 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_valid (tlNodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (tlNodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (tlNodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (tlNodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (tlNodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (tlNodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (tlNodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (tlNodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (tlNodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (tlNodeIn_d_ready) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] assign auto_clock_out_member_allClocks_uncore_clock = auto_clock_out_member_allClocks_uncore_clock_0; // @[TileResetSetter.scala:26:25] assign auto_clock_out_member_allClocks_uncore_reset = auto_clock_out_member_allClocks_uncore_reset_0; // @[TileResetSetter.scala:26:25] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_6 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _source_ok_T_34 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_35 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_36 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[18] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 connect _source_ok_WIRE[9], _source_ok_T_29 connect _source_ok_WIRE[10], _source_ok_T_30 connect _source_ok_WIRE[11], _source_ok_T_31 connect _source_ok_WIRE[12], _source_ok_T_32 connect _source_ok_WIRE[13], _source_ok_T_33 connect _source_ok_WIRE[14], _source_ok_T_34 connect _source_ok_WIRE[15], _source_ok_T_35 connect _source_ok_WIRE[16], _source_ok_T_36 connect _source_ok_WIRE[17], _source_ok_T_37 node _source_ok_T_38 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_39 = or(_source_ok_T_38, _source_ok_WIRE[2]) node _source_ok_T_40 = or(_source_ok_T_39, _source_ok_WIRE[3]) node _source_ok_T_41 = or(_source_ok_T_40, _source_ok_WIRE[4]) node _source_ok_T_42 = or(_source_ok_T_41, _source_ok_WIRE[5]) node _source_ok_T_43 = or(_source_ok_T_42, _source_ok_WIRE[6]) node _source_ok_T_44 = or(_source_ok_T_43, _source_ok_WIRE[7]) node _source_ok_T_45 = or(_source_ok_T_44, _source_ok_WIRE[8]) node _source_ok_T_46 = or(_source_ok_T_45, _source_ok_WIRE[9]) node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[10]) node _source_ok_T_48 = or(_source_ok_T_47, _source_ok_WIRE[11]) node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[12]) node _source_ok_T_50 = or(_source_ok_T_49, _source_ok_WIRE[13]) node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE[14]) node _source_ok_T_52 = or(_source_ok_T_51, _source_ok_WIRE[15]) node _source_ok_T_53 = or(_source_ok_T_52, _source_ok_WIRE[16]) node source_ok = or(_source_ok_T_53, _source_ok_WIRE[17]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_99 = cvt(_T_98) node _T_100 = and(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = asSInt(_T_100) node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = or(_T_97, _T_102) node _T_104 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_105 = eq(_T_104, UInt<1>(0h0)) node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<1>(0h0))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = or(_T_105, _T_110) node _T_112 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_115 = cvt(_T_114) node _T_116 = and(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = asSInt(_T_116) node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = or(_T_113, _T_118) node _T_120 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_123 = cvt(_T_122) node _T_124 = and(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = asSInt(_T_124) node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0))) node _T_127 = or(_T_121, _T_126) node _T_128 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_129 = eq(_T_128, UInt<1>(0h0)) node _T_130 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<1>(0h0))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = or(_T_129, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_137 = eq(_T_136, UInt<1>(0h0)) node _T_138 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_139 = cvt(_T_138) node _T_140 = and(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = asSInt(_T_140) node _T_142 = eq(_T_141, asSInt(UInt<1>(0h0))) node _T_143 = or(_T_137, _T_142) node _T_144 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_145 = eq(_T_144, UInt<1>(0h0)) node _T_146 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = or(_T_145, _T_150) node _T_152 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_155 = cvt(_T_154) node _T_156 = and(_T_155, asSInt(UInt<1>(0h0))) node _T_157 = asSInt(_T_156) node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = or(_T_153, _T_158) node _T_160 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_161 = eq(_T_160, UInt<1>(0h0)) node _T_162 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_163 = cvt(_T_162) node _T_164 = and(_T_163, asSInt(UInt<1>(0h0))) node _T_165 = asSInt(_T_164) node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = or(_T_161, _T_166) node _T_168 = and(_T_11, _T_24) node _T_169 = and(_T_168, _T_37) node _T_170 = and(_T_169, _T_50) node _T_171 = and(_T_170, _T_63) node _T_172 = and(_T_171, _T_71) node _T_173 = and(_T_172, _T_79) node _T_174 = and(_T_173, _T_87) node _T_175 = and(_T_174, _T_95) node _T_176 = and(_T_175, _T_103) node _T_177 = and(_T_176, _T_111) node _T_178 = and(_T_177, _T_119) node _T_179 = and(_T_178, _T_127) node _T_180 = and(_T_179, _T_135) node _T_181 = and(_T_180, _T_143) node _T_182 = and(_T_181, _T_151) node _T_183 = and(_T_182, _T_159) node _T_184 = and(_T_183, _T_167) node _T_185 = asUInt(reset) node _T_186 = eq(_T_185, UInt<1>(0h0)) when _T_186 : node _T_187 = eq(_T_184, UInt<1>(0h0)) when _T_187 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_184, UInt<1>(0h1), "") : assert_1 node _T_188 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_188 : node _T_189 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_190 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_191 = and(_T_189, _T_190) node _T_192 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_193 = shr(io.in.a.bits.source, 2) node _T_194 = eq(_T_193, UInt<1>(0h0)) node _T_195 = leq(UInt<1>(0h0), uncommonBits_4) node _T_196 = and(_T_194, _T_195) node _T_197 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_199 = shr(io.in.a.bits.source, 2) node _T_200 = eq(_T_199, UInt<1>(0h1)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_5) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_204 = and(_T_202, _T_203) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_205 = shr(io.in.a.bits.source, 2) node _T_206 = eq(_T_205, UInt<2>(0h2)) node _T_207 = leq(UInt<1>(0h0), uncommonBits_6) node _T_208 = and(_T_206, _T_207) node _T_209 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_210 = and(_T_208, _T_209) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_211 = shr(io.in.a.bits.source, 2) node _T_212 = eq(_T_211, UInt<2>(0h3)) node _T_213 = leq(UInt<1>(0h0), uncommonBits_7) node _T_214 = and(_T_212, _T_213) node _T_215 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_216 = and(_T_214, _T_215) node _T_217 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_218 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_219 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_220 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_221 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_222 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_223 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_224 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_225 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_226 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_227 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_228 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_229 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_230 = or(_T_192, _T_198) node _T_231 = or(_T_230, _T_204) node _T_232 = or(_T_231, _T_210) node _T_233 = or(_T_232, _T_216) node _T_234 = or(_T_233, _T_217) node _T_235 = or(_T_234, _T_218) node _T_236 = or(_T_235, _T_219) node _T_237 = or(_T_236, _T_220) node _T_238 = or(_T_237, _T_221) node _T_239 = or(_T_238, _T_222) node _T_240 = or(_T_239, _T_223) node _T_241 = or(_T_240, _T_224) node _T_242 = or(_T_241, _T_225) node _T_243 = or(_T_242, _T_226) node _T_244 = or(_T_243, _T_227) node _T_245 = or(_T_244, _T_228) node _T_246 = or(_T_245, _T_229) node _T_247 = and(_T_191, _T_246) node _T_248 = or(UInt<1>(0h0), _T_247) node _T_249 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_250 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_251 = cvt(_T_250) node _T_252 = and(_T_251, asSInt(UInt<13>(0h1000))) node _T_253 = asSInt(_T_252) node _T_254 = eq(_T_253, asSInt(UInt<1>(0h0))) node _T_255 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_256 = cvt(_T_255) node _T_257 = and(_T_256, asSInt(UInt<13>(0h1000))) node _T_258 = asSInt(_T_257) node _T_259 = eq(_T_258, asSInt(UInt<1>(0h0))) node _T_260 = or(_T_254, _T_259) node _T_261 = and(_T_249, _T_260) node _T_262 = or(UInt<1>(0h0), _T_261) node _T_263 = and(_T_248, _T_262) node _T_264 = asUInt(reset) node _T_265 = eq(_T_264, UInt<1>(0h0)) when _T_265 : node _T_266 = eq(_T_263, UInt<1>(0h0)) when _T_266 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_263, UInt<1>(0h1), "") : assert_2 node _T_267 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_268 = shr(io.in.a.bits.source, 2) node _T_269 = eq(_T_268, UInt<1>(0h0)) node _T_270 = leq(UInt<1>(0h0), uncommonBits_8) node _T_271 = and(_T_269, _T_270) node _T_272 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_273 = and(_T_271, _T_272) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_274 = shr(io.in.a.bits.source, 2) node _T_275 = eq(_T_274, UInt<1>(0h1)) node _T_276 = leq(UInt<1>(0h0), uncommonBits_9) node _T_277 = and(_T_275, _T_276) node _T_278 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_279 = and(_T_277, _T_278) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_280 = shr(io.in.a.bits.source, 2) node _T_281 = eq(_T_280, UInt<2>(0h2)) node _T_282 = leq(UInt<1>(0h0), uncommonBits_10) node _T_283 = and(_T_281, _T_282) node _T_284 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_285 = and(_T_283, _T_284) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_286 = shr(io.in.a.bits.source, 2) node _T_287 = eq(_T_286, UInt<2>(0h3)) node _T_288 = leq(UInt<1>(0h0), uncommonBits_11) node _T_289 = and(_T_287, _T_288) node _T_290 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_291 = and(_T_289, _T_290) node _T_292 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_293 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_294 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_295 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_296 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_297 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_298 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_299 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_300 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_301 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_302 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_303 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_304 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[18] connect _WIRE[0], _T_267 connect _WIRE[1], _T_273 connect _WIRE[2], _T_279 connect _WIRE[3], _T_285 connect _WIRE[4], _T_291 connect _WIRE[5], _T_292 connect _WIRE[6], _T_293 connect _WIRE[7], _T_294 connect _WIRE[8], _T_295 connect _WIRE[9], _T_296 connect _WIRE[10], _T_297 connect _WIRE[11], _T_298 connect _WIRE[12], _T_299 connect _WIRE[13], _T_300 connect _WIRE[14], _T_301 connect _WIRE[15], _T_302 connect _WIRE[16], _T_303 connect _WIRE[17], _T_304 node _T_305 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_306 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_307 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_308 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_309 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_310 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_311 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_312 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_313 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_314 = mux(_WIRE[5], _T_305, UInt<1>(0h0)) node _T_315 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_316 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_317 = mux(_WIRE[8], _T_306, UInt<1>(0h0)) node _T_318 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_319 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_320 = mux(_WIRE[11], _T_307, UInt<1>(0h0)) node _T_321 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_322 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_323 = mux(_WIRE[14], _T_308, UInt<1>(0h0)) node _T_324 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_325 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_326 = mux(_WIRE[17], UInt<1>(0h0), UInt<1>(0h0)) node _T_327 = or(_T_309, _T_310) node _T_328 = or(_T_327, _T_311) node _T_329 = or(_T_328, _T_312) node _T_330 = or(_T_329, _T_313) node _T_331 = or(_T_330, _T_314) node _T_332 = or(_T_331, _T_315) node _T_333 = or(_T_332, _T_316) node _T_334 = or(_T_333, _T_317) node _T_335 = or(_T_334, _T_318) node _T_336 = or(_T_335, _T_319) node _T_337 = or(_T_336, _T_320) node _T_338 = or(_T_337, _T_321) node _T_339 = or(_T_338, _T_322) node _T_340 = or(_T_339, _T_323) node _T_341 = or(_T_340, _T_324) node _T_342 = or(_T_341, _T_325) node _T_343 = or(_T_342, _T_326) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_343 node _T_344 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_345 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_346 = and(_T_344, _T_345) node _T_347 = or(UInt<1>(0h0), _T_346) node _T_348 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_349 = cvt(_T_348) node _T_350 = and(_T_349, asSInt(UInt<13>(0h1000))) node _T_351 = asSInt(_T_350) node _T_352 = eq(_T_351, asSInt(UInt<1>(0h0))) node _T_353 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_354 = cvt(_T_353) node _T_355 = and(_T_354, asSInt(UInt<13>(0h1000))) node _T_356 = asSInt(_T_355) node _T_357 = eq(_T_356, asSInt(UInt<1>(0h0))) node _T_358 = or(_T_352, _T_357) node _T_359 = and(_T_347, _T_358) node _T_360 = or(UInt<1>(0h0), _T_359) node _T_361 = and(_WIRE_1, _T_360) node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(_T_361, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_361, UInt<1>(0h1), "") : assert_3 node _T_365 = asUInt(reset) node _T_366 = eq(_T_365, UInt<1>(0h0)) when _T_366 : node _T_367 = eq(source_ok, UInt<1>(0h0)) when _T_367 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_368 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_369 = asUInt(reset) node _T_370 = eq(_T_369, UInt<1>(0h0)) when _T_370 : node _T_371 = eq(_T_368, UInt<1>(0h0)) when _T_371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_368, UInt<1>(0h1), "") : assert_5 node _T_372 = asUInt(reset) node _T_373 = eq(_T_372, UInt<1>(0h0)) when _T_373 : node _T_374 = eq(is_aligned, UInt<1>(0h0)) when _T_374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_375 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_375, UInt<1>(0h1), "") : assert_7 node _T_379 = not(io.in.a.bits.mask) node _T_380 = eq(_T_379, UInt<1>(0h0)) node _T_381 = asUInt(reset) node _T_382 = eq(_T_381, UInt<1>(0h0)) when _T_382 : node _T_383 = eq(_T_380, UInt<1>(0h0)) when _T_383 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_380, UInt<1>(0h1), "") : assert_8 node _T_384 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_385 = asUInt(reset) node _T_386 = eq(_T_385, UInt<1>(0h0)) when _T_386 : node _T_387 = eq(_T_384, UInt<1>(0h0)) when _T_387 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_384, UInt<1>(0h1), "") : assert_9 node _T_388 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_388 : node _T_389 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_390 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_391 = and(_T_389, _T_390) node _T_392 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_393 = shr(io.in.a.bits.source, 2) node _T_394 = eq(_T_393, UInt<1>(0h0)) node _T_395 = leq(UInt<1>(0h0), uncommonBits_12) node _T_396 = and(_T_394, _T_395) node _T_397 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_398 = and(_T_396, _T_397) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_399 = shr(io.in.a.bits.source, 2) node _T_400 = eq(_T_399, UInt<1>(0h1)) node _T_401 = leq(UInt<1>(0h0), uncommonBits_13) node _T_402 = and(_T_400, _T_401) node _T_403 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_404 = and(_T_402, _T_403) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_405 = shr(io.in.a.bits.source, 2) node _T_406 = eq(_T_405, UInt<2>(0h2)) node _T_407 = leq(UInt<1>(0h0), uncommonBits_14) node _T_408 = and(_T_406, _T_407) node _T_409 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_410 = and(_T_408, _T_409) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_411 = shr(io.in.a.bits.source, 2) node _T_412 = eq(_T_411, UInt<2>(0h3)) node _T_413 = leq(UInt<1>(0h0), uncommonBits_15) node _T_414 = and(_T_412, _T_413) node _T_415 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_416 = and(_T_414, _T_415) node _T_417 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_418 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_419 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_420 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_421 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_422 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_423 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_424 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_425 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_426 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_427 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_428 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_429 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_430 = or(_T_392, _T_398) node _T_431 = or(_T_430, _T_404) node _T_432 = or(_T_431, _T_410) node _T_433 = or(_T_432, _T_416) node _T_434 = or(_T_433, _T_417) node _T_435 = or(_T_434, _T_418) node _T_436 = or(_T_435, _T_419) node _T_437 = or(_T_436, _T_420) node _T_438 = or(_T_437, _T_421) node _T_439 = or(_T_438, _T_422) node _T_440 = or(_T_439, _T_423) node _T_441 = or(_T_440, _T_424) node _T_442 = or(_T_441, _T_425) node _T_443 = or(_T_442, _T_426) node _T_444 = or(_T_443, _T_427) node _T_445 = or(_T_444, _T_428) node _T_446 = or(_T_445, _T_429) node _T_447 = and(_T_391, _T_446) node _T_448 = or(UInt<1>(0h0), _T_447) node _T_449 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_450 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_451 = cvt(_T_450) node _T_452 = and(_T_451, asSInt(UInt<13>(0h1000))) node _T_453 = asSInt(_T_452) node _T_454 = eq(_T_453, asSInt(UInt<1>(0h0))) node _T_455 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_456 = cvt(_T_455) node _T_457 = and(_T_456, asSInt(UInt<13>(0h1000))) node _T_458 = asSInt(_T_457) node _T_459 = eq(_T_458, asSInt(UInt<1>(0h0))) node _T_460 = or(_T_454, _T_459) node _T_461 = and(_T_449, _T_460) node _T_462 = or(UInt<1>(0h0), _T_461) node _T_463 = and(_T_448, _T_462) node _T_464 = asUInt(reset) node _T_465 = eq(_T_464, UInt<1>(0h0)) when _T_465 : node _T_466 = eq(_T_463, UInt<1>(0h0)) when _T_466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_463, UInt<1>(0h1), "") : assert_10 node _T_467 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_468 = shr(io.in.a.bits.source, 2) node _T_469 = eq(_T_468, UInt<1>(0h0)) node _T_470 = leq(UInt<1>(0h0), uncommonBits_16) node _T_471 = and(_T_469, _T_470) node _T_472 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_473 = and(_T_471, _T_472) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_474 = shr(io.in.a.bits.source, 2) node _T_475 = eq(_T_474, UInt<1>(0h1)) node _T_476 = leq(UInt<1>(0h0), uncommonBits_17) node _T_477 = and(_T_475, _T_476) node _T_478 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_479 = and(_T_477, _T_478) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_480 = shr(io.in.a.bits.source, 2) node _T_481 = eq(_T_480, UInt<2>(0h2)) node _T_482 = leq(UInt<1>(0h0), uncommonBits_18) node _T_483 = and(_T_481, _T_482) node _T_484 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_485 = and(_T_483, _T_484) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_486 = shr(io.in.a.bits.source, 2) node _T_487 = eq(_T_486, UInt<2>(0h3)) node _T_488 = leq(UInt<1>(0h0), uncommonBits_19) node _T_489 = and(_T_487, _T_488) node _T_490 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_491 = and(_T_489, _T_490) node _T_492 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_493 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_494 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_495 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_496 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_497 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_498 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_499 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_500 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_501 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_502 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_503 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_504 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[18] connect _WIRE_2[0], _T_467 connect _WIRE_2[1], _T_473 connect _WIRE_2[2], _T_479 connect _WIRE_2[3], _T_485 connect _WIRE_2[4], _T_491 connect _WIRE_2[5], _T_492 connect _WIRE_2[6], _T_493 connect _WIRE_2[7], _T_494 connect _WIRE_2[8], _T_495 connect _WIRE_2[9], _T_496 connect _WIRE_2[10], _T_497 connect _WIRE_2[11], _T_498 connect _WIRE_2[12], _T_499 connect _WIRE_2[13], _T_500 connect _WIRE_2[14], _T_501 connect _WIRE_2[15], _T_502 connect _WIRE_2[16], _T_503 connect _WIRE_2[17], _T_504 node _T_505 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_506 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_507 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_508 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_509 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_510 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_511 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_512 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_513 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_514 = mux(_WIRE_2[5], _T_505, UInt<1>(0h0)) node _T_515 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_516 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_517 = mux(_WIRE_2[8], _T_506, UInt<1>(0h0)) node _T_518 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_519 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_520 = mux(_WIRE_2[11], _T_507, UInt<1>(0h0)) node _T_521 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_522 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_523 = mux(_WIRE_2[14], _T_508, UInt<1>(0h0)) node _T_524 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_525 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_526 = mux(_WIRE_2[17], UInt<1>(0h0), UInt<1>(0h0)) node _T_527 = or(_T_509, _T_510) node _T_528 = or(_T_527, _T_511) node _T_529 = or(_T_528, _T_512) node _T_530 = or(_T_529, _T_513) node _T_531 = or(_T_530, _T_514) node _T_532 = or(_T_531, _T_515) node _T_533 = or(_T_532, _T_516) node _T_534 = or(_T_533, _T_517) node _T_535 = or(_T_534, _T_518) node _T_536 = or(_T_535, _T_519) node _T_537 = or(_T_536, _T_520) node _T_538 = or(_T_537, _T_521) node _T_539 = or(_T_538, _T_522) node _T_540 = or(_T_539, _T_523) node _T_541 = or(_T_540, _T_524) node _T_542 = or(_T_541, _T_525) node _T_543 = or(_T_542, _T_526) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_543 node _T_544 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_545 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_546 = and(_T_544, _T_545) node _T_547 = or(UInt<1>(0h0), _T_546) node _T_548 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_549 = cvt(_T_548) node _T_550 = and(_T_549, asSInt(UInt<13>(0h1000))) node _T_551 = asSInt(_T_550) node _T_552 = eq(_T_551, asSInt(UInt<1>(0h0))) node _T_553 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_554 = cvt(_T_553) node _T_555 = and(_T_554, asSInt(UInt<13>(0h1000))) node _T_556 = asSInt(_T_555) node _T_557 = eq(_T_556, asSInt(UInt<1>(0h0))) node _T_558 = or(_T_552, _T_557) node _T_559 = and(_T_547, _T_558) node _T_560 = or(UInt<1>(0h0), _T_559) node _T_561 = and(_WIRE_3, _T_560) node _T_562 = asUInt(reset) node _T_563 = eq(_T_562, UInt<1>(0h0)) when _T_563 : node _T_564 = eq(_T_561, UInt<1>(0h0)) when _T_564 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_561, UInt<1>(0h1), "") : assert_11 node _T_565 = asUInt(reset) node _T_566 = eq(_T_565, UInt<1>(0h0)) when _T_566 : node _T_567 = eq(source_ok, UInt<1>(0h0)) when _T_567 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_568 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_568, UInt<1>(0h1), "") : assert_13 node _T_572 = asUInt(reset) node _T_573 = eq(_T_572, UInt<1>(0h0)) when _T_573 : node _T_574 = eq(is_aligned, UInt<1>(0h0)) when _T_574 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_575 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_576 = asUInt(reset) node _T_577 = eq(_T_576, UInt<1>(0h0)) when _T_577 : node _T_578 = eq(_T_575, UInt<1>(0h0)) when _T_578 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_575, UInt<1>(0h1), "") : assert_15 node _T_579 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_580 = asUInt(reset) node _T_581 = eq(_T_580, UInt<1>(0h0)) when _T_581 : node _T_582 = eq(_T_579, UInt<1>(0h0)) when _T_582 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_579, UInt<1>(0h1), "") : assert_16 node _T_583 = not(io.in.a.bits.mask) node _T_584 = eq(_T_583, UInt<1>(0h0)) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_584, UInt<1>(0h1), "") : assert_17 node _T_588 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_588, UInt<1>(0h1), "") : assert_18 node _T_592 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_592 : node _T_593 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_594 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_595 = and(_T_593, _T_594) node _T_596 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_597 = shr(io.in.a.bits.source, 2) node _T_598 = eq(_T_597, UInt<1>(0h0)) node _T_599 = leq(UInt<1>(0h0), uncommonBits_20) node _T_600 = and(_T_598, _T_599) node _T_601 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_602 = and(_T_600, _T_601) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_603 = shr(io.in.a.bits.source, 2) node _T_604 = eq(_T_603, UInt<1>(0h1)) node _T_605 = leq(UInt<1>(0h0), uncommonBits_21) node _T_606 = and(_T_604, _T_605) node _T_607 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_608 = and(_T_606, _T_607) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_609 = shr(io.in.a.bits.source, 2) node _T_610 = eq(_T_609, UInt<2>(0h2)) node _T_611 = leq(UInt<1>(0h0), uncommonBits_22) node _T_612 = and(_T_610, _T_611) node _T_613 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_614 = and(_T_612, _T_613) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_615 = shr(io.in.a.bits.source, 2) node _T_616 = eq(_T_615, UInt<2>(0h3)) node _T_617 = leq(UInt<1>(0h0), uncommonBits_23) node _T_618 = and(_T_616, _T_617) node _T_619 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_620 = and(_T_618, _T_619) node _T_621 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_622 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_623 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_624 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_625 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_626 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_627 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_628 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_629 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_630 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_631 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_632 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_633 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_634 = or(_T_596, _T_602) node _T_635 = or(_T_634, _T_608) node _T_636 = or(_T_635, _T_614) node _T_637 = or(_T_636, _T_620) node _T_638 = or(_T_637, _T_621) node _T_639 = or(_T_638, _T_622) node _T_640 = or(_T_639, _T_623) node _T_641 = or(_T_640, _T_624) node _T_642 = or(_T_641, _T_625) node _T_643 = or(_T_642, _T_626) node _T_644 = or(_T_643, _T_627) node _T_645 = or(_T_644, _T_628) node _T_646 = or(_T_645, _T_629) node _T_647 = or(_T_646, _T_630) node _T_648 = or(_T_647, _T_631) node _T_649 = or(_T_648, _T_632) node _T_650 = or(_T_649, _T_633) node _T_651 = and(_T_595, _T_650) node _T_652 = or(UInt<1>(0h0), _T_651) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_652, UInt<1>(0h1), "") : assert_19 node _T_656 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_657 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_658 = and(_T_656, _T_657) node _T_659 = or(UInt<1>(0h0), _T_658) node _T_660 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_661 = cvt(_T_660) node _T_662 = and(_T_661, asSInt(UInt<13>(0h1000))) node _T_663 = asSInt(_T_662) node _T_664 = eq(_T_663, asSInt(UInt<1>(0h0))) node _T_665 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_666 = cvt(_T_665) node _T_667 = and(_T_666, asSInt(UInt<13>(0h1000))) node _T_668 = asSInt(_T_667) node _T_669 = eq(_T_668, asSInt(UInt<1>(0h0))) node _T_670 = or(_T_664, _T_669) node _T_671 = and(_T_659, _T_670) node _T_672 = or(UInt<1>(0h0), _T_671) node _T_673 = asUInt(reset) node _T_674 = eq(_T_673, UInt<1>(0h0)) when _T_674 : node _T_675 = eq(_T_672, UInt<1>(0h0)) when _T_675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_672, UInt<1>(0h1), "") : assert_20 node _T_676 = asUInt(reset) node _T_677 = eq(_T_676, UInt<1>(0h0)) when _T_677 : node _T_678 = eq(source_ok, UInt<1>(0h0)) when _T_678 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_679 = asUInt(reset) node _T_680 = eq(_T_679, UInt<1>(0h0)) when _T_680 : node _T_681 = eq(is_aligned, UInt<1>(0h0)) when _T_681 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_682 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_683 = asUInt(reset) node _T_684 = eq(_T_683, UInt<1>(0h0)) when _T_684 : node _T_685 = eq(_T_682, UInt<1>(0h0)) when _T_685 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_682, UInt<1>(0h1), "") : assert_23 node _T_686 = eq(io.in.a.bits.mask, mask) node _T_687 = asUInt(reset) node _T_688 = eq(_T_687, UInt<1>(0h0)) when _T_688 : node _T_689 = eq(_T_686, UInt<1>(0h0)) when _T_689 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_686, UInt<1>(0h1), "") : assert_24 node _T_690 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_691 = asUInt(reset) node _T_692 = eq(_T_691, UInt<1>(0h0)) when _T_692 : node _T_693 = eq(_T_690, UInt<1>(0h0)) when _T_693 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_690, UInt<1>(0h1), "") : assert_25 node _T_694 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_694 : node _T_695 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_696 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_697 = and(_T_695, _T_696) node _T_698 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_699 = shr(io.in.a.bits.source, 2) node _T_700 = eq(_T_699, UInt<1>(0h0)) node _T_701 = leq(UInt<1>(0h0), uncommonBits_24) node _T_702 = and(_T_700, _T_701) node _T_703 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_704 = and(_T_702, _T_703) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_705 = shr(io.in.a.bits.source, 2) node _T_706 = eq(_T_705, UInt<1>(0h1)) node _T_707 = leq(UInt<1>(0h0), uncommonBits_25) node _T_708 = and(_T_706, _T_707) node _T_709 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_710 = and(_T_708, _T_709) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_711 = shr(io.in.a.bits.source, 2) node _T_712 = eq(_T_711, UInt<2>(0h2)) node _T_713 = leq(UInt<1>(0h0), uncommonBits_26) node _T_714 = and(_T_712, _T_713) node _T_715 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_716 = and(_T_714, _T_715) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_717 = shr(io.in.a.bits.source, 2) node _T_718 = eq(_T_717, UInt<2>(0h3)) node _T_719 = leq(UInt<1>(0h0), uncommonBits_27) node _T_720 = and(_T_718, _T_719) node _T_721 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_722 = and(_T_720, _T_721) node _T_723 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_724 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_725 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_726 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_727 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_728 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_729 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_730 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_731 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_732 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_733 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_734 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_735 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_736 = or(_T_698, _T_704) node _T_737 = or(_T_736, _T_710) node _T_738 = or(_T_737, _T_716) node _T_739 = or(_T_738, _T_722) node _T_740 = or(_T_739, _T_723) node _T_741 = or(_T_740, _T_724) node _T_742 = or(_T_741, _T_725) node _T_743 = or(_T_742, _T_726) node _T_744 = or(_T_743, _T_727) node _T_745 = or(_T_744, _T_728) node _T_746 = or(_T_745, _T_729) node _T_747 = or(_T_746, _T_730) node _T_748 = or(_T_747, _T_731) node _T_749 = or(_T_748, _T_732) node _T_750 = or(_T_749, _T_733) node _T_751 = or(_T_750, _T_734) node _T_752 = or(_T_751, _T_735) node _T_753 = and(_T_697, _T_752) node _T_754 = or(UInt<1>(0h0), _T_753) node _T_755 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_756 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_757 = and(_T_755, _T_756) node _T_758 = or(UInt<1>(0h0), _T_757) node _T_759 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_760 = cvt(_T_759) node _T_761 = and(_T_760, asSInt(UInt<13>(0h1000))) node _T_762 = asSInt(_T_761) node _T_763 = eq(_T_762, asSInt(UInt<1>(0h0))) node _T_764 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_765 = cvt(_T_764) node _T_766 = and(_T_765, asSInt(UInt<13>(0h1000))) node _T_767 = asSInt(_T_766) node _T_768 = eq(_T_767, asSInt(UInt<1>(0h0))) node _T_769 = or(_T_763, _T_768) node _T_770 = and(_T_758, _T_769) node _T_771 = or(UInt<1>(0h0), _T_770) node _T_772 = and(_T_754, _T_771) node _T_773 = asUInt(reset) node _T_774 = eq(_T_773, UInt<1>(0h0)) when _T_774 : node _T_775 = eq(_T_772, UInt<1>(0h0)) when _T_775 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_772, UInt<1>(0h1), "") : assert_26 node _T_776 = asUInt(reset) node _T_777 = eq(_T_776, UInt<1>(0h0)) when _T_777 : node _T_778 = eq(source_ok, UInt<1>(0h0)) when _T_778 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_779 = asUInt(reset) node _T_780 = eq(_T_779, UInt<1>(0h0)) when _T_780 : node _T_781 = eq(is_aligned, UInt<1>(0h0)) when _T_781 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_782 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_783 = asUInt(reset) node _T_784 = eq(_T_783, UInt<1>(0h0)) when _T_784 : node _T_785 = eq(_T_782, UInt<1>(0h0)) when _T_785 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_782, UInt<1>(0h1), "") : assert_29 node _T_786 = eq(io.in.a.bits.mask, mask) node _T_787 = asUInt(reset) node _T_788 = eq(_T_787, UInt<1>(0h0)) when _T_788 : node _T_789 = eq(_T_786, UInt<1>(0h0)) when _T_789 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_786, UInt<1>(0h1), "") : assert_30 node _T_790 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_790 : node _T_791 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_792 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_793 = and(_T_791, _T_792) node _T_794 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_795 = shr(io.in.a.bits.source, 2) node _T_796 = eq(_T_795, UInt<1>(0h0)) node _T_797 = leq(UInt<1>(0h0), uncommonBits_28) node _T_798 = and(_T_796, _T_797) node _T_799 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_800 = and(_T_798, _T_799) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_801 = shr(io.in.a.bits.source, 2) node _T_802 = eq(_T_801, UInt<1>(0h1)) node _T_803 = leq(UInt<1>(0h0), uncommonBits_29) node _T_804 = and(_T_802, _T_803) node _T_805 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_806 = and(_T_804, _T_805) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_807 = shr(io.in.a.bits.source, 2) node _T_808 = eq(_T_807, UInt<2>(0h2)) node _T_809 = leq(UInt<1>(0h0), uncommonBits_30) node _T_810 = and(_T_808, _T_809) node _T_811 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_812 = and(_T_810, _T_811) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_813 = shr(io.in.a.bits.source, 2) node _T_814 = eq(_T_813, UInt<2>(0h3)) node _T_815 = leq(UInt<1>(0h0), uncommonBits_31) node _T_816 = and(_T_814, _T_815) node _T_817 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_818 = and(_T_816, _T_817) node _T_819 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_820 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_821 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_822 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_823 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_824 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_825 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_826 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_827 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_828 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_829 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_830 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_831 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_832 = or(_T_794, _T_800) node _T_833 = or(_T_832, _T_806) node _T_834 = or(_T_833, _T_812) node _T_835 = or(_T_834, _T_818) node _T_836 = or(_T_835, _T_819) node _T_837 = or(_T_836, _T_820) node _T_838 = or(_T_837, _T_821) node _T_839 = or(_T_838, _T_822) node _T_840 = or(_T_839, _T_823) node _T_841 = or(_T_840, _T_824) node _T_842 = or(_T_841, _T_825) node _T_843 = or(_T_842, _T_826) node _T_844 = or(_T_843, _T_827) node _T_845 = or(_T_844, _T_828) node _T_846 = or(_T_845, _T_829) node _T_847 = or(_T_846, _T_830) node _T_848 = or(_T_847, _T_831) node _T_849 = and(_T_793, _T_848) node _T_850 = or(UInt<1>(0h0), _T_849) node _T_851 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_852 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_853 = and(_T_851, _T_852) node _T_854 = or(UInt<1>(0h0), _T_853) node _T_855 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_856 = cvt(_T_855) node _T_857 = and(_T_856, asSInt(UInt<13>(0h1000))) node _T_858 = asSInt(_T_857) node _T_859 = eq(_T_858, asSInt(UInt<1>(0h0))) node _T_860 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_861 = cvt(_T_860) node _T_862 = and(_T_861, asSInt(UInt<13>(0h1000))) node _T_863 = asSInt(_T_862) node _T_864 = eq(_T_863, asSInt(UInt<1>(0h0))) node _T_865 = or(_T_859, _T_864) node _T_866 = and(_T_854, _T_865) node _T_867 = or(UInt<1>(0h0), _T_866) node _T_868 = and(_T_850, _T_867) node _T_869 = asUInt(reset) node _T_870 = eq(_T_869, UInt<1>(0h0)) when _T_870 : node _T_871 = eq(_T_868, UInt<1>(0h0)) when _T_871 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_868, UInt<1>(0h1), "") : assert_31 node _T_872 = asUInt(reset) node _T_873 = eq(_T_872, UInt<1>(0h0)) when _T_873 : node _T_874 = eq(source_ok, UInt<1>(0h0)) when _T_874 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_875 = asUInt(reset) node _T_876 = eq(_T_875, UInt<1>(0h0)) when _T_876 : node _T_877 = eq(is_aligned, UInt<1>(0h0)) when _T_877 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_878 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_879 = asUInt(reset) node _T_880 = eq(_T_879, UInt<1>(0h0)) when _T_880 : node _T_881 = eq(_T_878, UInt<1>(0h0)) when _T_881 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_878, UInt<1>(0h1), "") : assert_34 node _T_882 = not(mask) node _T_883 = and(io.in.a.bits.mask, _T_882) node _T_884 = eq(_T_883, UInt<1>(0h0)) node _T_885 = asUInt(reset) node _T_886 = eq(_T_885, UInt<1>(0h0)) when _T_886 : node _T_887 = eq(_T_884, UInt<1>(0h0)) when _T_887 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_884, UInt<1>(0h1), "") : assert_35 node _T_888 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_888 : node _T_889 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_890 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_891 = and(_T_889, _T_890) node _T_892 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_893 = shr(io.in.a.bits.source, 2) node _T_894 = eq(_T_893, UInt<1>(0h0)) node _T_895 = leq(UInt<1>(0h0), uncommonBits_32) node _T_896 = and(_T_894, _T_895) node _T_897 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_898 = and(_T_896, _T_897) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_899 = shr(io.in.a.bits.source, 2) node _T_900 = eq(_T_899, UInt<1>(0h1)) node _T_901 = leq(UInt<1>(0h0), uncommonBits_33) node _T_902 = and(_T_900, _T_901) node _T_903 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_904 = and(_T_902, _T_903) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_905 = shr(io.in.a.bits.source, 2) node _T_906 = eq(_T_905, UInt<2>(0h2)) node _T_907 = leq(UInt<1>(0h0), uncommonBits_34) node _T_908 = and(_T_906, _T_907) node _T_909 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_910 = and(_T_908, _T_909) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_911 = shr(io.in.a.bits.source, 2) node _T_912 = eq(_T_911, UInt<2>(0h3)) node _T_913 = leq(UInt<1>(0h0), uncommonBits_35) node _T_914 = and(_T_912, _T_913) node _T_915 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_916 = and(_T_914, _T_915) node _T_917 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_918 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_919 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_920 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_921 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_922 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_923 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_924 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_925 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_926 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_927 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_928 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_929 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_930 = or(_T_892, _T_898) node _T_931 = or(_T_930, _T_904) node _T_932 = or(_T_931, _T_910) node _T_933 = or(_T_932, _T_916) node _T_934 = or(_T_933, _T_917) node _T_935 = or(_T_934, _T_918) node _T_936 = or(_T_935, _T_919) node _T_937 = or(_T_936, _T_920) node _T_938 = or(_T_937, _T_921) node _T_939 = or(_T_938, _T_922) node _T_940 = or(_T_939, _T_923) node _T_941 = or(_T_940, _T_924) node _T_942 = or(_T_941, _T_925) node _T_943 = or(_T_942, _T_926) node _T_944 = or(_T_943, _T_927) node _T_945 = or(_T_944, _T_928) node _T_946 = or(_T_945, _T_929) node _T_947 = and(_T_891, _T_946) node _T_948 = or(UInt<1>(0h0), _T_947) node _T_949 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_950 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_951 = cvt(_T_950) node _T_952 = and(_T_951, asSInt(UInt<13>(0h1000))) node _T_953 = asSInt(_T_952) node _T_954 = eq(_T_953, asSInt(UInt<1>(0h0))) node _T_955 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_956 = cvt(_T_955) node _T_957 = and(_T_956, asSInt(UInt<13>(0h1000))) node _T_958 = asSInt(_T_957) node _T_959 = eq(_T_958, asSInt(UInt<1>(0h0))) node _T_960 = or(_T_954, _T_959) node _T_961 = and(_T_949, _T_960) node _T_962 = or(UInt<1>(0h0), _T_961) node _T_963 = and(_T_948, _T_962) node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_T_963, UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_963, UInt<1>(0h1), "") : assert_36 node _T_967 = asUInt(reset) node _T_968 = eq(_T_967, UInt<1>(0h0)) when _T_968 : node _T_969 = eq(source_ok, UInt<1>(0h0)) when _T_969 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_970 = asUInt(reset) node _T_971 = eq(_T_970, UInt<1>(0h0)) when _T_971 : node _T_972 = eq(is_aligned, UInt<1>(0h0)) when _T_972 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_973 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_974 = asUInt(reset) node _T_975 = eq(_T_974, UInt<1>(0h0)) when _T_975 : node _T_976 = eq(_T_973, UInt<1>(0h0)) when _T_976 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_973, UInt<1>(0h1), "") : assert_39 node _T_977 = eq(io.in.a.bits.mask, mask) node _T_978 = asUInt(reset) node _T_979 = eq(_T_978, UInt<1>(0h0)) when _T_979 : node _T_980 = eq(_T_977, UInt<1>(0h0)) when _T_980 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_977, UInt<1>(0h1), "") : assert_40 node _T_981 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_981 : node _T_982 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_983 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_984 = and(_T_982, _T_983) node _T_985 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_986 = shr(io.in.a.bits.source, 2) node _T_987 = eq(_T_986, UInt<1>(0h0)) node _T_988 = leq(UInt<1>(0h0), uncommonBits_36) node _T_989 = and(_T_987, _T_988) node _T_990 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_991 = and(_T_989, _T_990) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_992 = shr(io.in.a.bits.source, 2) node _T_993 = eq(_T_992, UInt<1>(0h1)) node _T_994 = leq(UInt<1>(0h0), uncommonBits_37) node _T_995 = and(_T_993, _T_994) node _T_996 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_997 = and(_T_995, _T_996) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_998 = shr(io.in.a.bits.source, 2) node _T_999 = eq(_T_998, UInt<2>(0h2)) node _T_1000 = leq(UInt<1>(0h0), uncommonBits_38) node _T_1001 = and(_T_999, _T_1000) node _T_1002 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_1003 = and(_T_1001, _T_1002) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_1004 = shr(io.in.a.bits.source, 2) node _T_1005 = eq(_T_1004, UInt<2>(0h3)) node _T_1006 = leq(UInt<1>(0h0), uncommonBits_39) node _T_1007 = and(_T_1005, _T_1006) node _T_1008 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_1009 = and(_T_1007, _T_1008) node _T_1010 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1011 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1012 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1013 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1014 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1015 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1016 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1017 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1018 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1019 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1020 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1021 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1022 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1023 = or(_T_985, _T_991) node _T_1024 = or(_T_1023, _T_997) node _T_1025 = or(_T_1024, _T_1003) node _T_1026 = or(_T_1025, _T_1009) node _T_1027 = or(_T_1026, _T_1010) node _T_1028 = or(_T_1027, _T_1011) node _T_1029 = or(_T_1028, _T_1012) node _T_1030 = or(_T_1029, _T_1013) node _T_1031 = or(_T_1030, _T_1014) node _T_1032 = or(_T_1031, _T_1015) node _T_1033 = or(_T_1032, _T_1016) node _T_1034 = or(_T_1033, _T_1017) node _T_1035 = or(_T_1034, _T_1018) node _T_1036 = or(_T_1035, _T_1019) node _T_1037 = or(_T_1036, _T_1020) node _T_1038 = or(_T_1037, _T_1021) node _T_1039 = or(_T_1038, _T_1022) node _T_1040 = and(_T_984, _T_1039) node _T_1041 = or(UInt<1>(0h0), _T_1040) node _T_1042 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1043 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1044 = cvt(_T_1043) node _T_1045 = and(_T_1044, asSInt(UInt<13>(0h1000))) node _T_1046 = asSInt(_T_1045) node _T_1047 = eq(_T_1046, asSInt(UInt<1>(0h0))) node _T_1048 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1049 = cvt(_T_1048) node _T_1050 = and(_T_1049, asSInt(UInt<13>(0h1000))) node _T_1051 = asSInt(_T_1050) node _T_1052 = eq(_T_1051, asSInt(UInt<1>(0h0))) node _T_1053 = or(_T_1047, _T_1052) node _T_1054 = and(_T_1042, _T_1053) node _T_1055 = or(UInt<1>(0h0), _T_1054) node _T_1056 = and(_T_1041, _T_1055) node _T_1057 = asUInt(reset) node _T_1058 = eq(_T_1057, UInt<1>(0h0)) when _T_1058 : node _T_1059 = eq(_T_1056, UInt<1>(0h0)) when _T_1059 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1056, UInt<1>(0h1), "") : assert_41 node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(source_ok, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1063 = asUInt(reset) node _T_1064 = eq(_T_1063, UInt<1>(0h0)) when _T_1064 : node _T_1065 = eq(is_aligned, UInt<1>(0h0)) when _T_1065 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1066 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1067 = asUInt(reset) node _T_1068 = eq(_T_1067, UInt<1>(0h0)) when _T_1068 : node _T_1069 = eq(_T_1066, UInt<1>(0h0)) when _T_1069 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1066, UInt<1>(0h1), "") : assert_44 node _T_1070 = eq(io.in.a.bits.mask, mask) node _T_1071 = asUInt(reset) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) when _T_1072 : node _T_1073 = eq(_T_1070, UInt<1>(0h0)) when _T_1073 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1070, UInt<1>(0h1), "") : assert_45 node _T_1074 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1074 : node _T_1075 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1076 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1077 = and(_T_1075, _T_1076) node _T_1078 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_1079 = shr(io.in.a.bits.source, 2) node _T_1080 = eq(_T_1079, UInt<1>(0h0)) node _T_1081 = leq(UInt<1>(0h0), uncommonBits_40) node _T_1082 = and(_T_1080, _T_1081) node _T_1083 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_1084 = and(_T_1082, _T_1083) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_1085 = shr(io.in.a.bits.source, 2) node _T_1086 = eq(_T_1085, UInt<1>(0h1)) node _T_1087 = leq(UInt<1>(0h0), uncommonBits_41) node _T_1088 = and(_T_1086, _T_1087) node _T_1089 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_1090 = and(_T_1088, _T_1089) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_1091 = shr(io.in.a.bits.source, 2) node _T_1092 = eq(_T_1091, UInt<2>(0h2)) node _T_1093 = leq(UInt<1>(0h0), uncommonBits_42) node _T_1094 = and(_T_1092, _T_1093) node _T_1095 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_1096 = and(_T_1094, _T_1095) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_1097 = shr(io.in.a.bits.source, 2) node _T_1098 = eq(_T_1097, UInt<2>(0h3)) node _T_1099 = leq(UInt<1>(0h0), uncommonBits_43) node _T_1100 = and(_T_1098, _T_1099) node _T_1101 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_1102 = and(_T_1100, _T_1101) node _T_1103 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1104 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1105 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1106 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1107 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1108 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1109 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1110 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1111 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1112 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1113 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1114 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1115 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1116 = or(_T_1078, _T_1084) node _T_1117 = or(_T_1116, _T_1090) node _T_1118 = or(_T_1117, _T_1096) node _T_1119 = or(_T_1118, _T_1102) node _T_1120 = or(_T_1119, _T_1103) node _T_1121 = or(_T_1120, _T_1104) node _T_1122 = or(_T_1121, _T_1105) node _T_1123 = or(_T_1122, _T_1106) node _T_1124 = or(_T_1123, _T_1107) node _T_1125 = or(_T_1124, _T_1108) node _T_1126 = or(_T_1125, _T_1109) node _T_1127 = or(_T_1126, _T_1110) node _T_1128 = or(_T_1127, _T_1111) node _T_1129 = or(_T_1128, _T_1112) node _T_1130 = or(_T_1129, _T_1113) node _T_1131 = or(_T_1130, _T_1114) node _T_1132 = or(_T_1131, _T_1115) node _T_1133 = and(_T_1077, _T_1132) node _T_1134 = or(UInt<1>(0h0), _T_1133) node _T_1135 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1136 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1137 = cvt(_T_1136) node _T_1138 = and(_T_1137, asSInt(UInt<13>(0h1000))) node _T_1139 = asSInt(_T_1138) node _T_1140 = eq(_T_1139, asSInt(UInt<1>(0h0))) node _T_1141 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1142 = cvt(_T_1141) node _T_1143 = and(_T_1142, asSInt(UInt<13>(0h1000))) node _T_1144 = asSInt(_T_1143) node _T_1145 = eq(_T_1144, asSInt(UInt<1>(0h0))) node _T_1146 = or(_T_1140, _T_1145) node _T_1147 = and(_T_1135, _T_1146) node _T_1148 = or(UInt<1>(0h0), _T_1147) node _T_1149 = and(_T_1134, _T_1148) node _T_1150 = asUInt(reset) node _T_1151 = eq(_T_1150, UInt<1>(0h0)) when _T_1151 : node _T_1152 = eq(_T_1149, UInt<1>(0h0)) when _T_1152 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1149, UInt<1>(0h1), "") : assert_46 node _T_1153 = asUInt(reset) node _T_1154 = eq(_T_1153, UInt<1>(0h0)) when _T_1154 : node _T_1155 = eq(source_ok, UInt<1>(0h0)) when _T_1155 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1156 = asUInt(reset) node _T_1157 = eq(_T_1156, UInt<1>(0h0)) when _T_1157 : node _T_1158 = eq(is_aligned, UInt<1>(0h0)) when _T_1158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1159 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1160 = asUInt(reset) node _T_1161 = eq(_T_1160, UInt<1>(0h0)) when _T_1161 : node _T_1162 = eq(_T_1159, UInt<1>(0h0)) when _T_1162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1159, UInt<1>(0h1), "") : assert_49 node _T_1163 = eq(io.in.a.bits.mask, mask) node _T_1164 = asUInt(reset) node _T_1165 = eq(_T_1164, UInt<1>(0h0)) when _T_1165 : node _T_1166 = eq(_T_1163, UInt<1>(0h0)) when _T_1166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1163, UInt<1>(0h1), "") : assert_50 node _T_1167 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1168 = asUInt(reset) node _T_1169 = eq(_T_1168, UInt<1>(0h0)) when _T_1169 : node _T_1170 = eq(_T_1167, UInt<1>(0h0)) when _T_1170 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1167, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1171 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1172 = asUInt(reset) node _T_1173 = eq(_T_1172, UInt<1>(0h0)) when _T_1173 : node _T_1174 = eq(_T_1171, UInt<1>(0h0)) when _T_1174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1171, UInt<1>(0h1), "") : assert_52 node _source_ok_T_54 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_55 = shr(io.in.d.bits.source, 2) node _source_ok_T_56 = eq(_source_ok_T_55, UInt<1>(0h0)) node _source_ok_T_57 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57) node _source_ok_T_59 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_61 = shr(io.in.d.bits.source, 2) node _source_ok_T_62 = eq(_source_ok_T_61, UInt<1>(0h1)) node _source_ok_T_63 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_64 = and(_source_ok_T_62, _source_ok_T_63) node _source_ok_T_65 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_66 = and(_source_ok_T_64, _source_ok_T_65) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_67 = shr(io.in.d.bits.source, 2) node _source_ok_T_68 = eq(_source_ok_T_67, UInt<2>(0h2)) node _source_ok_T_69 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_70 = and(_source_ok_T_68, _source_ok_T_69) node _source_ok_T_71 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_72 = and(_source_ok_T_70, _source_ok_T_71) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_73 = shr(io.in.d.bits.source, 2) node _source_ok_T_74 = eq(_source_ok_T_73, UInt<2>(0h3)) node _source_ok_T_75 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_76 = and(_source_ok_T_74, _source_ok_T_75) node _source_ok_T_77 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_78 = and(_source_ok_T_76, _source_ok_T_77) node _source_ok_T_79 = eq(io.in.d.bits.source, UInt<6>(0h2c)) node _source_ok_T_80 = eq(io.in.d.bits.source, UInt<6>(0h2d)) node _source_ok_T_81 = eq(io.in.d.bits.source, UInt<6>(0h2e)) node _source_ok_T_82 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_83 = eq(io.in.d.bits.source, UInt<6>(0h29)) node _source_ok_T_84 = eq(io.in.d.bits.source, UInt<6>(0h2a)) node _source_ok_T_85 = eq(io.in.d.bits.source, UInt<6>(0h24)) node _source_ok_T_86 = eq(io.in.d.bits.source, UInt<6>(0h25)) node _source_ok_T_87 = eq(io.in.d.bits.source, UInt<6>(0h26)) node _source_ok_T_88 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_89 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_90 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_91 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[18] connect _source_ok_WIRE_1[0], _source_ok_T_54 connect _source_ok_WIRE_1[1], _source_ok_T_60 connect _source_ok_WIRE_1[2], _source_ok_T_66 connect _source_ok_WIRE_1[3], _source_ok_T_72 connect _source_ok_WIRE_1[4], _source_ok_T_78 connect _source_ok_WIRE_1[5], _source_ok_T_79 connect _source_ok_WIRE_1[6], _source_ok_T_80 connect _source_ok_WIRE_1[7], _source_ok_T_81 connect _source_ok_WIRE_1[8], _source_ok_T_82 connect _source_ok_WIRE_1[9], _source_ok_T_83 connect _source_ok_WIRE_1[10], _source_ok_T_84 connect _source_ok_WIRE_1[11], _source_ok_T_85 connect _source_ok_WIRE_1[12], _source_ok_T_86 connect _source_ok_WIRE_1[13], _source_ok_T_87 connect _source_ok_WIRE_1[14], _source_ok_T_88 connect _source_ok_WIRE_1[15], _source_ok_T_89 connect _source_ok_WIRE_1[16], _source_ok_T_90 connect _source_ok_WIRE_1[17], _source_ok_T_91 node _source_ok_T_92 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_93 = or(_source_ok_T_92, _source_ok_WIRE_1[2]) node _source_ok_T_94 = or(_source_ok_T_93, _source_ok_WIRE_1[3]) node _source_ok_T_95 = or(_source_ok_T_94, _source_ok_WIRE_1[4]) node _source_ok_T_96 = or(_source_ok_T_95, _source_ok_WIRE_1[5]) node _source_ok_T_97 = or(_source_ok_T_96, _source_ok_WIRE_1[6]) node _source_ok_T_98 = or(_source_ok_T_97, _source_ok_WIRE_1[7]) node _source_ok_T_99 = or(_source_ok_T_98, _source_ok_WIRE_1[8]) node _source_ok_T_100 = or(_source_ok_T_99, _source_ok_WIRE_1[9]) node _source_ok_T_101 = or(_source_ok_T_100, _source_ok_WIRE_1[10]) node _source_ok_T_102 = or(_source_ok_T_101, _source_ok_WIRE_1[11]) node _source_ok_T_103 = or(_source_ok_T_102, _source_ok_WIRE_1[12]) node _source_ok_T_104 = or(_source_ok_T_103, _source_ok_WIRE_1[13]) node _source_ok_T_105 = or(_source_ok_T_104, _source_ok_WIRE_1[14]) node _source_ok_T_106 = or(_source_ok_T_105, _source_ok_WIRE_1[15]) node _source_ok_T_107 = or(_source_ok_T_106, _source_ok_WIRE_1[16]) node source_ok_1 = or(_source_ok_T_107, _source_ok_WIRE_1[17]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1175 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1175 : node _T_1176 = asUInt(reset) node _T_1177 = eq(_T_1176, UInt<1>(0h0)) when _T_1177 : node _T_1178 = eq(source_ok_1, UInt<1>(0h0)) when _T_1178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1179 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1180 = asUInt(reset) node _T_1181 = eq(_T_1180, UInt<1>(0h0)) when _T_1181 : node _T_1182 = eq(_T_1179, UInt<1>(0h0)) when _T_1182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1179, UInt<1>(0h1), "") : assert_54 node _T_1183 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1184 = asUInt(reset) node _T_1185 = eq(_T_1184, UInt<1>(0h0)) when _T_1185 : node _T_1186 = eq(_T_1183, UInt<1>(0h0)) when _T_1186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1183, UInt<1>(0h1), "") : assert_55 node _T_1187 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1188 = asUInt(reset) node _T_1189 = eq(_T_1188, UInt<1>(0h0)) when _T_1189 : node _T_1190 = eq(_T_1187, UInt<1>(0h0)) when _T_1190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1187, UInt<1>(0h1), "") : assert_56 node _T_1191 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1192 = asUInt(reset) node _T_1193 = eq(_T_1192, UInt<1>(0h0)) when _T_1193 : node _T_1194 = eq(_T_1191, UInt<1>(0h0)) when _T_1194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1191, UInt<1>(0h1), "") : assert_57 node _T_1195 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1195 : node _T_1196 = asUInt(reset) node _T_1197 = eq(_T_1196, UInt<1>(0h0)) when _T_1197 : node _T_1198 = eq(source_ok_1, UInt<1>(0h0)) when _T_1198 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1199 = asUInt(reset) node _T_1200 = eq(_T_1199, UInt<1>(0h0)) when _T_1200 : node _T_1201 = eq(sink_ok, UInt<1>(0h0)) when _T_1201 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1202 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1203 = asUInt(reset) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) when _T_1204 : node _T_1205 = eq(_T_1202, UInt<1>(0h0)) when _T_1205 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1202, UInt<1>(0h1), "") : assert_60 node _T_1206 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1207 = asUInt(reset) node _T_1208 = eq(_T_1207, UInt<1>(0h0)) when _T_1208 : node _T_1209 = eq(_T_1206, UInt<1>(0h0)) when _T_1209 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1206, UInt<1>(0h1), "") : assert_61 node _T_1210 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1211 = asUInt(reset) node _T_1212 = eq(_T_1211, UInt<1>(0h0)) when _T_1212 : node _T_1213 = eq(_T_1210, UInt<1>(0h0)) when _T_1213 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1210, UInt<1>(0h1), "") : assert_62 node _T_1214 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1215 = asUInt(reset) node _T_1216 = eq(_T_1215, UInt<1>(0h0)) when _T_1216 : node _T_1217 = eq(_T_1214, UInt<1>(0h0)) when _T_1217 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1214, UInt<1>(0h1), "") : assert_63 node _T_1218 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1219 = or(UInt<1>(0h0), _T_1218) node _T_1220 = asUInt(reset) node _T_1221 = eq(_T_1220, UInt<1>(0h0)) when _T_1221 : node _T_1222 = eq(_T_1219, UInt<1>(0h0)) when _T_1222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1219, UInt<1>(0h1), "") : assert_64 node _T_1223 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1223 : node _T_1224 = asUInt(reset) node _T_1225 = eq(_T_1224, UInt<1>(0h0)) when _T_1225 : node _T_1226 = eq(source_ok_1, UInt<1>(0h0)) when _T_1226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1227 = asUInt(reset) node _T_1228 = eq(_T_1227, UInt<1>(0h0)) when _T_1228 : node _T_1229 = eq(sink_ok, UInt<1>(0h0)) when _T_1229 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1230 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1231 = asUInt(reset) node _T_1232 = eq(_T_1231, UInt<1>(0h0)) when _T_1232 : node _T_1233 = eq(_T_1230, UInt<1>(0h0)) when _T_1233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1230, UInt<1>(0h1), "") : assert_67 node _T_1234 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1235 = asUInt(reset) node _T_1236 = eq(_T_1235, UInt<1>(0h0)) when _T_1236 : node _T_1237 = eq(_T_1234, UInt<1>(0h0)) when _T_1237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1234, UInt<1>(0h1), "") : assert_68 node _T_1238 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1239 = asUInt(reset) node _T_1240 = eq(_T_1239, UInt<1>(0h0)) when _T_1240 : node _T_1241 = eq(_T_1238, UInt<1>(0h0)) when _T_1241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1238, UInt<1>(0h1), "") : assert_69 node _T_1242 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1243 = or(_T_1242, io.in.d.bits.corrupt) node _T_1244 = asUInt(reset) node _T_1245 = eq(_T_1244, UInt<1>(0h0)) when _T_1245 : node _T_1246 = eq(_T_1243, UInt<1>(0h0)) when _T_1246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1243, UInt<1>(0h1), "") : assert_70 node _T_1247 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1248 = or(UInt<1>(0h0), _T_1247) node _T_1249 = asUInt(reset) node _T_1250 = eq(_T_1249, UInt<1>(0h0)) when _T_1250 : node _T_1251 = eq(_T_1248, UInt<1>(0h0)) when _T_1251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1248, UInt<1>(0h1), "") : assert_71 node _T_1252 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1252 : node _T_1253 = asUInt(reset) node _T_1254 = eq(_T_1253, UInt<1>(0h0)) when _T_1254 : node _T_1255 = eq(source_ok_1, UInt<1>(0h0)) when _T_1255 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1256 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1257 = asUInt(reset) node _T_1258 = eq(_T_1257, UInt<1>(0h0)) when _T_1258 : node _T_1259 = eq(_T_1256, UInt<1>(0h0)) when _T_1259 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1256, UInt<1>(0h1), "") : assert_73 node _T_1260 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1261 = asUInt(reset) node _T_1262 = eq(_T_1261, UInt<1>(0h0)) when _T_1262 : node _T_1263 = eq(_T_1260, UInt<1>(0h0)) when _T_1263 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1260, UInt<1>(0h1), "") : assert_74 node _T_1264 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1265 = or(UInt<1>(0h0), _T_1264) node _T_1266 = asUInt(reset) node _T_1267 = eq(_T_1266, UInt<1>(0h0)) when _T_1267 : node _T_1268 = eq(_T_1265, UInt<1>(0h0)) when _T_1268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1265, UInt<1>(0h1), "") : assert_75 node _T_1269 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1269 : node _T_1270 = asUInt(reset) node _T_1271 = eq(_T_1270, UInt<1>(0h0)) when _T_1271 : node _T_1272 = eq(source_ok_1, UInt<1>(0h0)) when _T_1272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1273 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1274 = asUInt(reset) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) when _T_1275 : node _T_1276 = eq(_T_1273, UInt<1>(0h0)) when _T_1276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1273, UInt<1>(0h1), "") : assert_77 node _T_1277 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1278 = or(_T_1277, io.in.d.bits.corrupt) node _T_1279 = asUInt(reset) node _T_1280 = eq(_T_1279, UInt<1>(0h0)) when _T_1280 : node _T_1281 = eq(_T_1278, UInt<1>(0h0)) when _T_1281 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1278, UInt<1>(0h1), "") : assert_78 node _T_1282 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1283 = or(UInt<1>(0h0), _T_1282) node _T_1284 = asUInt(reset) node _T_1285 = eq(_T_1284, UInt<1>(0h0)) when _T_1285 : node _T_1286 = eq(_T_1283, UInt<1>(0h0)) when _T_1286 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1283, UInt<1>(0h1), "") : assert_79 node _T_1287 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1287 : node _T_1288 = asUInt(reset) node _T_1289 = eq(_T_1288, UInt<1>(0h0)) when _T_1289 : node _T_1290 = eq(source_ok_1, UInt<1>(0h0)) when _T_1290 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1291 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1292 = asUInt(reset) node _T_1293 = eq(_T_1292, UInt<1>(0h0)) when _T_1293 : node _T_1294 = eq(_T_1291, UInt<1>(0h0)) when _T_1294 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1291, UInt<1>(0h1), "") : assert_81 node _T_1295 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1296 = asUInt(reset) node _T_1297 = eq(_T_1296, UInt<1>(0h0)) when _T_1297 : node _T_1298 = eq(_T_1295, UInt<1>(0h0)) when _T_1298 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1295, UInt<1>(0h1), "") : assert_82 node _T_1299 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1300 = or(UInt<1>(0h0), _T_1299) node _T_1301 = asUInt(reset) node _T_1302 = eq(_T_1301, UInt<1>(0h0)) when _T_1302 : node _T_1303 = eq(_T_1300, UInt<1>(0h0)) when _T_1303 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1300, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<29>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1304 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1305 = asUInt(reset) node _T_1306 = eq(_T_1305, UInt<1>(0h0)) when _T_1306 : node _T_1307 = eq(_T_1304, UInt<1>(0h0)) when _T_1307 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1304, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1308 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1309 = asUInt(reset) node _T_1310 = eq(_T_1309, UInt<1>(0h0)) when _T_1310 : node _T_1311 = eq(_T_1308, UInt<1>(0h0)) when _T_1311 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1308, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1312 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1313 = asUInt(reset) node _T_1314 = eq(_T_1313, UInt<1>(0h0)) when _T_1314 : node _T_1315 = eq(_T_1312, UInt<1>(0h0)) when _T_1315 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1312, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1316 = eq(a_first, UInt<1>(0h0)) node _T_1317 = and(io.in.a.valid, _T_1316) when _T_1317 : node _T_1318 = eq(io.in.a.bits.opcode, opcode) node _T_1319 = asUInt(reset) node _T_1320 = eq(_T_1319, UInt<1>(0h0)) when _T_1320 : node _T_1321 = eq(_T_1318, UInt<1>(0h0)) when _T_1321 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1318, UInt<1>(0h1), "") : assert_87 node _T_1322 = eq(io.in.a.bits.param, param) node _T_1323 = asUInt(reset) node _T_1324 = eq(_T_1323, UInt<1>(0h0)) when _T_1324 : node _T_1325 = eq(_T_1322, UInt<1>(0h0)) when _T_1325 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1322, UInt<1>(0h1), "") : assert_88 node _T_1326 = eq(io.in.a.bits.size, size) node _T_1327 = asUInt(reset) node _T_1328 = eq(_T_1327, UInt<1>(0h0)) when _T_1328 : node _T_1329 = eq(_T_1326, UInt<1>(0h0)) when _T_1329 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1326, UInt<1>(0h1), "") : assert_89 node _T_1330 = eq(io.in.a.bits.source, source) node _T_1331 = asUInt(reset) node _T_1332 = eq(_T_1331, UInt<1>(0h0)) when _T_1332 : node _T_1333 = eq(_T_1330, UInt<1>(0h0)) when _T_1333 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1330, UInt<1>(0h1), "") : assert_90 node _T_1334 = eq(io.in.a.bits.address, address) node _T_1335 = asUInt(reset) node _T_1336 = eq(_T_1335, UInt<1>(0h0)) when _T_1336 : node _T_1337 = eq(_T_1334, UInt<1>(0h0)) when _T_1337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1334, UInt<1>(0h1), "") : assert_91 node _T_1338 = and(io.in.a.ready, io.in.a.valid) node _T_1339 = and(_T_1338, a_first) when _T_1339 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1340 = eq(d_first, UInt<1>(0h0)) node _T_1341 = and(io.in.d.valid, _T_1340) when _T_1341 : node _T_1342 = eq(io.in.d.bits.opcode, opcode_1) node _T_1343 = asUInt(reset) node _T_1344 = eq(_T_1343, UInt<1>(0h0)) when _T_1344 : node _T_1345 = eq(_T_1342, UInt<1>(0h0)) when _T_1345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1342, UInt<1>(0h1), "") : assert_92 node _T_1346 = eq(io.in.d.bits.param, param_1) node _T_1347 = asUInt(reset) node _T_1348 = eq(_T_1347, UInt<1>(0h0)) when _T_1348 : node _T_1349 = eq(_T_1346, UInt<1>(0h0)) when _T_1349 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1346, UInt<1>(0h1), "") : assert_93 node _T_1350 = eq(io.in.d.bits.size, size_1) node _T_1351 = asUInt(reset) node _T_1352 = eq(_T_1351, UInt<1>(0h0)) when _T_1352 : node _T_1353 = eq(_T_1350, UInt<1>(0h0)) when _T_1353 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1350, UInt<1>(0h1), "") : assert_94 node _T_1354 = eq(io.in.d.bits.source, source_1) node _T_1355 = asUInt(reset) node _T_1356 = eq(_T_1355, UInt<1>(0h0)) when _T_1356 : node _T_1357 = eq(_T_1354, UInt<1>(0h0)) when _T_1357 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1354, UInt<1>(0h1), "") : assert_95 node _T_1358 = eq(io.in.d.bits.sink, sink) node _T_1359 = asUInt(reset) node _T_1360 = eq(_T_1359, UInt<1>(0h0)) when _T_1360 : node _T_1361 = eq(_T_1358, UInt<1>(0h0)) when _T_1361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1358, UInt<1>(0h1), "") : assert_96 node _T_1362 = eq(io.in.d.bits.denied, denied) node _T_1363 = asUInt(reset) node _T_1364 = eq(_T_1363, UInt<1>(0h0)) when _T_1364 : node _T_1365 = eq(_T_1362, UInt<1>(0h0)) when _T_1365 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1362, UInt<1>(0h1), "") : assert_97 node _T_1366 = and(io.in.d.ready, io.in.d.valid) node _T_1367 = and(_T_1366, d_first) when _T_1367 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<260> connect a_sizes_set, UInt<260>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1368 = and(io.in.a.valid, a_first_1) node _T_1369 = and(_T_1368, UInt<1>(0h1)) when _T_1369 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1370 = and(io.in.a.ready, io.in.a.valid) node _T_1371 = and(_T_1370, a_first_1) node _T_1372 = and(_T_1371, UInt<1>(0h1)) when _T_1372 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1373 = dshr(inflight, io.in.a.bits.source) node _T_1374 = bits(_T_1373, 0, 0) node _T_1375 = eq(_T_1374, UInt<1>(0h0)) node _T_1376 = asUInt(reset) node _T_1377 = eq(_T_1376, UInt<1>(0h0)) when _T_1377 : node _T_1378 = eq(_T_1375, UInt<1>(0h0)) when _T_1378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1375, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<260> connect d_sizes_clr, UInt<260>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1379 = and(io.in.d.valid, d_first_1) node _T_1380 = and(_T_1379, UInt<1>(0h1)) node _T_1381 = eq(d_release_ack, UInt<1>(0h0)) node _T_1382 = and(_T_1380, _T_1381) when _T_1382 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1383 = and(io.in.d.ready, io.in.d.valid) node _T_1384 = and(_T_1383, d_first_1) node _T_1385 = and(_T_1384, UInt<1>(0h1)) node _T_1386 = eq(d_release_ack, UInt<1>(0h0)) node _T_1387 = and(_T_1385, _T_1386) when _T_1387 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1388 = and(io.in.d.valid, d_first_1) node _T_1389 = and(_T_1388, UInt<1>(0h1)) node _T_1390 = eq(d_release_ack, UInt<1>(0h0)) node _T_1391 = and(_T_1389, _T_1390) when _T_1391 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1392 = dshr(inflight, io.in.d.bits.source) node _T_1393 = bits(_T_1392, 0, 0) node _T_1394 = or(_T_1393, same_cycle_resp) node _T_1395 = asUInt(reset) node _T_1396 = eq(_T_1395, UInt<1>(0h0)) when _T_1396 : node _T_1397 = eq(_T_1394, UInt<1>(0h0)) when _T_1397 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1394, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1398 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1399 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1400 = or(_T_1398, _T_1399) node _T_1401 = asUInt(reset) node _T_1402 = eq(_T_1401, UInt<1>(0h0)) when _T_1402 : node _T_1403 = eq(_T_1400, UInt<1>(0h0)) when _T_1403 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1400, UInt<1>(0h1), "") : assert_100 node _T_1404 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1405 = asUInt(reset) node _T_1406 = eq(_T_1405, UInt<1>(0h0)) when _T_1406 : node _T_1407 = eq(_T_1404, UInt<1>(0h0)) when _T_1407 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1404, UInt<1>(0h1), "") : assert_101 else : node _T_1408 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1409 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1410 = or(_T_1408, _T_1409) node _T_1411 = asUInt(reset) node _T_1412 = eq(_T_1411, UInt<1>(0h0)) when _T_1412 : node _T_1413 = eq(_T_1410, UInt<1>(0h0)) when _T_1413 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1410, UInt<1>(0h1), "") : assert_102 node _T_1414 = eq(io.in.d.bits.size, a_size_lookup) node _T_1415 = asUInt(reset) node _T_1416 = eq(_T_1415, UInt<1>(0h0)) when _T_1416 : node _T_1417 = eq(_T_1414, UInt<1>(0h0)) when _T_1417 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1414, UInt<1>(0h1), "") : assert_103 node _T_1418 = and(io.in.d.valid, d_first_1) node _T_1419 = and(_T_1418, a_first_1) node _T_1420 = and(_T_1419, io.in.a.valid) node _T_1421 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1422 = and(_T_1420, _T_1421) node _T_1423 = eq(d_release_ack, UInt<1>(0h0)) node _T_1424 = and(_T_1422, _T_1423) when _T_1424 : node _T_1425 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1426 = or(_T_1425, io.in.a.ready) node _T_1427 = asUInt(reset) node _T_1428 = eq(_T_1427, UInt<1>(0h0)) when _T_1428 : node _T_1429 = eq(_T_1426, UInt<1>(0h0)) when _T_1429 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1426, UInt<1>(0h1), "") : assert_104 node _T_1430 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1431 = orr(a_set_wo_ready) node _T_1432 = eq(_T_1431, UInt<1>(0h0)) node _T_1433 = or(_T_1430, _T_1432) node _T_1434 = asUInt(reset) node _T_1435 = eq(_T_1434, UInt<1>(0h0)) when _T_1435 : node _T_1436 = eq(_T_1433, UInt<1>(0h0)) when _T_1436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1433, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_21 node _T_1437 = orr(inflight) node _T_1438 = eq(_T_1437, UInt<1>(0h0)) node _T_1439 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1440 = or(_T_1438, _T_1439) node _T_1441 = lt(watchdog, plusarg_reader.out) node _T_1442 = or(_T_1440, _T_1441) node _T_1443 = asUInt(reset) node _T_1444 = eq(_T_1443, UInt<1>(0h0)) when _T_1444 : node _T_1445 = eq(_T_1442, UInt<1>(0h0)) when _T_1445 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1442, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1446 = and(io.in.a.ready, io.in.a.valid) node _T_1447 = and(io.in.d.ready, io.in.d.valid) node _T_1448 = or(_T_1446, _T_1447) when _T_1448 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<260> connect c_sizes_set, UInt<260>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1449 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1450 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1451 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1452 = and(_T_1450, _T_1451) node _T_1453 = and(_T_1449, _T_1452) when _T_1453 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1454 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1455 = and(_T_1454, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1456 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1457 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1458 = and(_T_1456, _T_1457) node _T_1459 = and(_T_1455, _T_1458) when _T_1459 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1460 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1461 = bits(_T_1460, 0, 0) node _T_1462 = eq(_T_1461, UInt<1>(0h0)) node _T_1463 = asUInt(reset) node _T_1464 = eq(_T_1463, UInt<1>(0h0)) when _T_1464 : node _T_1465 = eq(_T_1462, UInt<1>(0h0)) when _T_1465 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1462, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<260> connect d_sizes_clr_1, UInt<260>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1466 = and(io.in.d.valid, d_first_2) node _T_1467 = and(_T_1466, UInt<1>(0h1)) node _T_1468 = and(_T_1467, d_release_ack_1) when _T_1468 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1469 = and(io.in.d.ready, io.in.d.valid) node _T_1470 = and(_T_1469, d_first_2) node _T_1471 = and(_T_1470, UInt<1>(0h1)) node _T_1472 = and(_T_1471, d_release_ack_1) when _T_1472 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1473 = and(io.in.d.valid, d_first_2) node _T_1474 = and(_T_1473, UInt<1>(0h1)) node _T_1475 = and(_T_1474, d_release_ack_1) when _T_1475 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1476 = dshr(inflight_1, io.in.d.bits.source) node _T_1477 = bits(_T_1476, 0, 0) node _T_1478 = or(_T_1477, same_cycle_resp_1) node _T_1479 = asUInt(reset) node _T_1480 = eq(_T_1479, UInt<1>(0h0)) when _T_1480 : node _T_1481 = eq(_T_1478, UInt<1>(0h0)) when _T_1481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1478, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1482 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1483 = asUInt(reset) node _T_1484 = eq(_T_1483, UInt<1>(0h0)) when _T_1484 : node _T_1485 = eq(_T_1482, UInt<1>(0h0)) when _T_1485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1482, UInt<1>(0h1), "") : assert_109 else : node _T_1486 = eq(io.in.d.bits.size, c_size_lookup) node _T_1487 = asUInt(reset) node _T_1488 = eq(_T_1487, UInt<1>(0h0)) when _T_1488 : node _T_1489 = eq(_T_1486, UInt<1>(0h0)) when _T_1489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1486, UInt<1>(0h1), "") : assert_110 node _T_1490 = and(io.in.d.valid, d_first_2) node _T_1491 = and(_T_1490, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1492 = and(_T_1491, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1493 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1494 = and(_T_1492, _T_1493) node _T_1495 = and(_T_1494, d_release_ack_1) node _T_1496 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1497 = and(_T_1495, _T_1496) when _T_1497 : node _T_1498 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<29>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1499 = or(_T_1498, _WIRE_27.ready) node _T_1500 = asUInt(reset) node _T_1501 = eq(_T_1500, UInt<1>(0h0)) when _T_1501 : node _T_1502 = eq(_T_1499, UInt<1>(0h0)) when _T_1502 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1499, UInt<1>(0h1), "") : assert_111 node _T_1503 = orr(c_set_wo_ready) when _T_1503 : node _T_1504 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1505 = asUInt(reset) node _T_1506 = eq(_T_1505, UInt<1>(0h0)) when _T_1506 : node _T_1507 = eq(_T_1504, UInt<1>(0h0)) when _T_1507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1504, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_22 node _T_1508 = orr(inflight_1) node _T_1509 = eq(_T_1508, UInt<1>(0h0)) node _T_1510 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1511 = or(_T_1509, _T_1510) node _T_1512 = lt(watchdog_1, plusarg_reader_1.out) node _T_1513 = or(_T_1511, _T_1512) node _T_1514 = asUInt(reset) node _T_1515 = eq(_T_1514, UInt<1>(0h0)) when _T_1515 : node _T_1516 = eq(_T_1513, UInt<1>(0h0)) when _T_1516 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1513, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<29>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1517 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1518 = and(io.in.d.ready, io.in.d.valid) node _T_1519 = or(_T_1517, _T_1518) when _T_1519 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_6( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire [127:0] _GEN_0 = {121'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [127:0] _GEN_3 = {121'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [64:0] inflight_1; // @[Monitor.scala:726:35] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module SinkC : input clock : Clock input reset : Reset output io : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, tag : UInt<12>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}}, resp : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<10>, tag : UInt<12>, source : UInt<5>, param : UInt<3>, data : UInt<1>}}, flip c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, set : UInt<10>, flip way : UInt<3>, bs_adr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<3>, set : UInt<10>, beat : UInt<3>, mask : UInt<1>}}, bs_dat : { data : UInt<64>}, flip rel_pop : { flip ready : UInt<1>, valid : UInt<1>, bits : { index : UInt<6>, last : UInt<1>}}, rel_beat : { data : UInt<64>, corrupt : UInt<1>}} inst c_q of Queue2_TLBundleC_a32d64s5k3z3c connect c_q.clock, clock connect c_q.reset, reset connect c_q.io.enq.valid, io.c.valid connect c_q.io.enq.bits.corrupt, io.c.bits.corrupt connect c_q.io.enq.bits.data, io.c.bits.data connect c_q.io.enq.bits.address, io.c.bits.address connect c_q.io.enq.bits.source, io.c.bits.source connect c_q.io.enq.bits.size, io.c.bits.size connect c_q.io.enq.bits.param, io.c.bits.param connect c_q.io.enq.bits.opcode, io.c.bits.opcode connect io.c.ready, c_q.io.enq.ready node _offset_T = bits(c_q.io.deq.bits.address, 0, 0) node _offset_T_1 = bits(c_q.io.deq.bits.address, 1, 1) node _offset_T_2 = bits(c_q.io.deq.bits.address, 2, 2) node _offset_T_3 = bits(c_q.io.deq.bits.address, 3, 3) node _offset_T_4 = bits(c_q.io.deq.bits.address, 4, 4) node _offset_T_5 = bits(c_q.io.deq.bits.address, 5, 5) node _offset_T_6 = bits(c_q.io.deq.bits.address, 6, 6) node _offset_T_7 = bits(c_q.io.deq.bits.address, 7, 7) node _offset_T_8 = bits(c_q.io.deq.bits.address, 8, 8) node _offset_T_9 = bits(c_q.io.deq.bits.address, 9, 9) node _offset_T_10 = bits(c_q.io.deq.bits.address, 10, 10) node _offset_T_11 = bits(c_q.io.deq.bits.address, 11, 11) node _offset_T_12 = bits(c_q.io.deq.bits.address, 12, 12) node _offset_T_13 = bits(c_q.io.deq.bits.address, 13, 13) node _offset_T_14 = bits(c_q.io.deq.bits.address, 14, 14) node _offset_T_15 = bits(c_q.io.deq.bits.address, 15, 15) node _offset_T_16 = bits(c_q.io.deq.bits.address, 16, 16) node _offset_T_17 = bits(c_q.io.deq.bits.address, 17, 17) node _offset_T_18 = bits(c_q.io.deq.bits.address, 18, 18) node _offset_T_19 = bits(c_q.io.deq.bits.address, 19, 19) node _offset_T_20 = bits(c_q.io.deq.bits.address, 20, 20) node _offset_T_21 = bits(c_q.io.deq.bits.address, 21, 21) node _offset_T_22 = bits(c_q.io.deq.bits.address, 22, 22) node _offset_T_23 = bits(c_q.io.deq.bits.address, 23, 23) node _offset_T_24 = bits(c_q.io.deq.bits.address, 24, 24) node _offset_T_25 = bits(c_q.io.deq.bits.address, 25, 25) node _offset_T_26 = bits(c_q.io.deq.bits.address, 26, 26) node _offset_T_27 = bits(c_q.io.deq.bits.address, 27, 27) node offset_lo_lo_lo_hi = cat(_offset_T_2, _offset_T_1) node offset_lo_lo_lo = cat(offset_lo_lo_lo_hi, _offset_T) node offset_lo_lo_hi_lo = cat(_offset_T_4, _offset_T_3) node offset_lo_lo_hi_hi = cat(_offset_T_6, _offset_T_5) node offset_lo_lo_hi = cat(offset_lo_lo_hi_hi, offset_lo_lo_hi_lo) node offset_lo_lo = cat(offset_lo_lo_hi, offset_lo_lo_lo) node offset_lo_hi_lo_hi = cat(_offset_T_9, _offset_T_8) node offset_lo_hi_lo = cat(offset_lo_hi_lo_hi, _offset_T_7) node offset_lo_hi_hi_lo = cat(_offset_T_11, _offset_T_10) node offset_lo_hi_hi_hi = cat(_offset_T_13, _offset_T_12) node offset_lo_hi_hi = cat(offset_lo_hi_hi_hi, offset_lo_hi_hi_lo) node offset_lo_hi = cat(offset_lo_hi_hi, offset_lo_hi_lo) node offset_lo = cat(offset_lo_hi, offset_lo_lo) node offset_hi_lo_lo_hi = cat(_offset_T_16, _offset_T_15) node offset_hi_lo_lo = cat(offset_hi_lo_lo_hi, _offset_T_14) node offset_hi_lo_hi_lo = cat(_offset_T_18, _offset_T_17) node offset_hi_lo_hi_hi = cat(_offset_T_20, _offset_T_19) node offset_hi_lo_hi = cat(offset_hi_lo_hi_hi, offset_hi_lo_hi_lo) node offset_hi_lo = cat(offset_hi_lo_hi, offset_hi_lo_lo) node offset_hi_hi_lo_hi = cat(_offset_T_23, _offset_T_22) node offset_hi_hi_lo = cat(offset_hi_hi_lo_hi, _offset_T_21) node offset_hi_hi_hi_lo = cat(_offset_T_25, _offset_T_24) node offset_hi_hi_hi_hi = cat(_offset_T_27, _offset_T_26) node offset_hi_hi_hi = cat(offset_hi_hi_hi_hi, offset_hi_hi_hi_lo) node offset_hi_hi = cat(offset_hi_hi_hi, offset_hi_hi_lo) node offset_hi = cat(offset_hi_hi, offset_hi_lo) node offset = cat(offset_hi, offset_lo) node set = shr(offset, 6) node tag = shr(set, 10) node tag_1 = bits(tag, 11, 0) node set_1 = bits(set, 9, 0) node offset_1 = bits(offset, 5, 0) node _T = and(c_q.io.deq.ready, c_q.io.deq.valid) node _r_beats1_decode_T = dshl(UInt<6>(0h3f), c_q.io.deq.bits.size) node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 5, 0) node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1) node r_beats1_decode = shr(_r_beats1_decode_T_2, 3) node r_beats1_opdata = bits(c_q.io.deq.bits.opcode, 0, 0) node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0)) regreset r_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _r_counter1_T = sub(r_counter, UInt<1>(0h1)) node r_counter1 = tail(_r_counter1_T, 1) node first = eq(r_counter, UInt<1>(0h0)) node _r_last_T = eq(r_counter, UInt<1>(0h1)) node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0)) node last = or(_r_last_T, _r_last_T_1) node r_3 = and(last, _T) node _r_count_T = not(r_counter1) node beat = and(r_beats1, _r_count_T) when _T : node _r_counter_T = mux(first, r_beats1, r_counter1) connect r_counter, _r_counter_T node hasData = bits(c_q.io.deq.bits.opcode, 0, 0) node _raw_resp_T = eq(c_q.io.deq.bits.opcode, UInt<3>(0h4)) node _raw_resp_T_1 = eq(c_q.io.deq.bits.opcode, UInt<3>(0h5)) node raw_resp = or(_raw_resp_T, _raw_resp_T_1) reg resp_r : UInt<1>, clock when c_q.io.deq.valid : connect resp_r, raw_resp node resp = mux(c_q.io.deq.valid, raw_resp, resp_r) node _T_1 = and(c_q.io.deq.valid, c_q.io.deq.bits.corrupt) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed: Data poisoning unavailable\n at SinkC.scala:90 assert (!(c.valid && c.bits.corrupt), \"Data poisoning unavailable\")\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert reg io_set_r : UInt<10>, clock when c_q.io.deq.valid : connect io_set_r, set_1 node _io_set_T = mux(c_q.io.deq.valid, set_1, io_set_r) connect io.set, _io_set_T wire bs_adr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<3>, set : UInt<10>, beat : UInt<3>, mask : UInt<1>}} inst io_bs_adr_q of Queue1_BankedStoreInnerAddress connect io_bs_adr_q.clock, clock connect io_bs_adr_q.reset, reset connect io_bs_adr_q.io.enq.valid, bs_adr.valid connect io_bs_adr_q.io.enq.bits.mask, bs_adr.bits.mask connect io_bs_adr_q.io.enq.bits.beat, bs_adr.bits.beat connect io_bs_adr_q.io.enq.bits.set, bs_adr.bits.set connect io_bs_adr_q.io.enq.bits.way, bs_adr.bits.way connect io_bs_adr_q.io.enq.bits.noop, bs_adr.bits.noop connect bs_adr.ready, io_bs_adr_q.io.enq.ready connect io.bs_adr.bits, io_bs_adr_q.io.deq.bits connect io.bs_adr.valid, io_bs_adr_q.io.deq.valid connect io_bs_adr_q.io.deq.ready, io.bs_adr.ready node _io_bs_dat_data_T = and(bs_adr.ready, bs_adr.valid) reg io_bs_dat_data_r : UInt<64>, clock when _io_bs_dat_data_T : connect io_bs_dat_data_r, c_q.io.deq.bits.data connect io.bs_dat.data, io_bs_dat_data_r node _bs_adr_valid_T = eq(first, UInt<1>(0h0)) node _bs_adr_valid_T_1 = and(c_q.io.deq.valid, hasData) node _bs_adr_valid_T_2 = or(_bs_adr_valid_T, _bs_adr_valid_T_1) node _bs_adr_valid_T_3 = and(resp, _bs_adr_valid_T_2) connect bs_adr.valid, _bs_adr_valid_T_3 node _bs_adr_bits_noop_T = eq(c_q.io.deq.valid, UInt<1>(0h0)) connect bs_adr.bits.noop, _bs_adr_bits_noop_T connect bs_adr.bits.way, io.way connect bs_adr.bits.set, io.set node _bs_adr_bits_beat_T = add(beat, bs_adr.ready) node _bs_adr_bits_beat_T_1 = tail(_bs_adr_bits_beat_T, 1) reg bs_adr_bits_beat_r : UInt<3>, clock when c_q.io.deq.valid : connect bs_adr_bits_beat_r, _bs_adr_bits_beat_T_1 node _bs_adr_bits_beat_T_2 = mux(c_q.io.deq.valid, beat, bs_adr_bits_beat_r) connect bs_adr.bits.beat, _bs_adr_bits_beat_T_2 node _bs_adr_bits_mask_T = not(UInt<1>(0h0)) connect bs_adr.bits.mask, _bs_adr_bits_mask_T node _T_6 = eq(bs_adr.ready, UInt<1>(0h0)) node _T_7 = and(bs_adr.valid, _T_6) node _io_resp_valid_T = and(resp, c_q.io.deq.valid) node _io_resp_valid_T_1 = or(first, last) node _io_resp_valid_T_2 = and(_io_resp_valid_T, _io_resp_valid_T_1) node _io_resp_valid_T_3 = eq(hasData, UInt<1>(0h0)) node _io_resp_valid_T_4 = or(_io_resp_valid_T_3, bs_adr.ready) node _io_resp_valid_T_5 = and(_io_resp_valid_T_2, _io_resp_valid_T_4) connect io.resp.valid, _io_resp_valid_T_5 connect io.resp.bits.last, last connect io.resp.bits.set, set_1 connect io.resp.bits.tag, tag_1 connect io.resp.bits.source, c_q.io.deq.bits.source connect io.resp.bits.param, c_q.io.deq.bits.param connect io.resp.bits.data, hasData inst putbuffer of ListBuffer_PutBufferCEntry_q2_e16 connect putbuffer.clock, clock connect putbuffer.reset, reset regreset lists : UInt<2>, clock, reset, UInt<2>(0h0) wire lists_set : UInt<2> connect lists_set, UInt<2>(0h0) wire lists_clr : UInt<2> connect lists_clr, UInt<2>(0h0) node _lists_T = or(lists, lists_set) node _lists_T_1 = not(lists_clr) node _lists_T_2 = and(_lists_T, _lists_T_1) connect lists, _lists_T_2 node _free_T = andr(lists) node free = eq(_free_T, UInt<1>(0h0)) node _freeOH_T = not(lists) node _freeOH_T_1 = shl(_freeOH_T, 1) node _freeOH_T_2 = bits(_freeOH_T_1, 1, 0) node _freeOH_T_3 = or(_freeOH_T, _freeOH_T_2) node _freeOH_T_4 = bits(_freeOH_T_3, 1, 0) node _freeOH_T_5 = shl(_freeOH_T_4, 1) node _freeOH_T_6 = not(_freeOH_T_5) node _freeOH_T_7 = not(lists) node freeOH = and(_freeOH_T_6, _freeOH_T_7) node freeIdx_hi = bits(freeOH, 2, 2) node freeIdx_lo = bits(freeOH, 1, 0) node _freeIdx_T = orr(freeIdx_hi) node _freeIdx_T_1 = or(freeIdx_hi, freeIdx_lo) node _freeIdx_T_2 = bits(_freeIdx_T_1, 1, 1) node freeIdx = cat(_freeIdx_T, _freeIdx_T_2) node _req_block_T = eq(io.req.ready, UInt<1>(0h0)) node req_block = and(first, _req_block_T) node _buf_block_T = eq(putbuffer.io.push.ready, UInt<1>(0h0)) node buf_block = and(hasData, _buf_block_T) node _set_block_T = and(hasData, first) node _set_block_T_1 = eq(free, UInt<1>(0h0)) node set_block = and(_set_block_T, _set_block_T_1) node _T_8 = eq(raw_resp, UInt<1>(0h0)) node _T_9 = and(c_q.io.deq.valid, _T_8) node _T_10 = and(_T_9, req_block) node _T_11 = eq(raw_resp, UInt<1>(0h0)) node _T_12 = and(c_q.io.deq.valid, _T_11) node _T_13 = and(_T_12, buf_block) node _T_14 = eq(raw_resp, UInt<1>(0h0)) node _T_15 = and(c_q.io.deq.valid, _T_14) node _T_16 = and(_T_15, set_block) node _q_io_deq_ready_T = eq(hasData, UInt<1>(0h0)) node _q_io_deq_ready_T_1 = or(_q_io_deq_ready_T, bs_adr.ready) node _q_io_deq_ready_T_2 = eq(req_block, UInt<1>(0h0)) node _q_io_deq_ready_T_3 = eq(buf_block, UInt<1>(0h0)) node _q_io_deq_ready_T_4 = and(_q_io_deq_ready_T_2, _q_io_deq_ready_T_3) node _q_io_deq_ready_T_5 = eq(set_block, UInt<1>(0h0)) node _q_io_deq_ready_T_6 = and(_q_io_deq_ready_T_4, _q_io_deq_ready_T_5) node _q_io_deq_ready_T_7 = mux(raw_resp, _q_io_deq_ready_T_1, _q_io_deq_ready_T_6) connect c_q.io.deq.ready, _q_io_deq_ready_T_7 node _io_req_valid_T = eq(resp, UInt<1>(0h0)) node _io_req_valid_T_1 = and(_io_req_valid_T, c_q.io.deq.valid) node _io_req_valid_T_2 = and(_io_req_valid_T_1, first) node _io_req_valid_T_3 = eq(buf_block, UInt<1>(0h0)) node _io_req_valid_T_4 = and(_io_req_valid_T_2, _io_req_valid_T_3) node _io_req_valid_T_5 = eq(set_block, UInt<1>(0h0)) node _io_req_valid_T_6 = and(_io_req_valid_T_4, _io_req_valid_T_5) connect io.req.valid, _io_req_valid_T_6 node _putbuffer_io_push_valid_T = eq(resp, UInt<1>(0h0)) node _putbuffer_io_push_valid_T_1 = and(_putbuffer_io_push_valid_T, c_q.io.deq.valid) node _putbuffer_io_push_valid_T_2 = and(_putbuffer_io_push_valid_T_1, hasData) node _putbuffer_io_push_valid_T_3 = eq(req_block, UInt<1>(0h0)) node _putbuffer_io_push_valid_T_4 = and(_putbuffer_io_push_valid_T_2, _putbuffer_io_push_valid_T_3) node _putbuffer_io_push_valid_T_5 = eq(set_block, UInt<1>(0h0)) node _putbuffer_io_push_valid_T_6 = and(_putbuffer_io_push_valid_T_4, _putbuffer_io_push_valid_T_5) connect putbuffer.io.push.valid, _putbuffer_io_push_valid_T_6 node _T_17 = eq(resp, UInt<1>(0h0)) node _T_18 = and(_T_17, c_q.io.deq.valid) node _T_19 = and(_T_18, first) node _T_20 = and(_T_19, hasData) node _T_21 = eq(req_block, UInt<1>(0h0)) node _T_22 = and(_T_20, _T_21) node _T_23 = eq(buf_block, UInt<1>(0h0)) node _T_24 = and(_T_22, _T_23) when _T_24 : connect lists_set, freeOH reg put_r : UInt<2>, clock when first : connect put_r, freeIdx node put = mux(first, freeIdx, put_r) wire _WIRE : UInt<1>[3] connect _WIRE[0], UInt<1>(0h0) connect _WIRE[1], UInt<1>(0h0) connect _WIRE[2], UInt<1>(0h1) connect io.req.bits.prio, _WIRE connect io.req.bits.control, UInt<1>(0h0) connect io.req.bits.opcode, c_q.io.deq.bits.opcode connect io.req.bits.param, c_q.io.deq.bits.param connect io.req.bits.size, c_q.io.deq.bits.size connect io.req.bits.source, c_q.io.deq.bits.source connect io.req.bits.offset, offset_1 connect io.req.bits.set, set_1 connect io.req.bits.tag, tag_1 connect io.req.bits.put, put connect putbuffer.io.push.bits.index, put connect putbuffer.io.push.bits.data.data, c_q.io.deq.bits.data connect putbuffer.io.push.bits.data.corrupt, c_q.io.deq.bits.corrupt connect putbuffer.io.pop.bits, io.rel_pop.bits.index node _putbuffer_io_pop_valid_T = and(io.rel_pop.ready, io.rel_pop.valid) connect putbuffer.io.pop.valid, _putbuffer_io_pop_valid_T node _io_rel_pop_ready_T = bits(io.rel_pop.bits.index, 0, 0) node _io_rel_pop_ready_T_1 = dshr(putbuffer.io.valid, _io_rel_pop_ready_T) node _io_rel_pop_ready_T_2 = bits(_io_rel_pop_ready_T_1, 0, 0) connect io.rel_pop.ready, _io_rel_pop_ready_T_2 connect io.rel_beat, putbuffer.io.data node _T_25 = and(io.rel_pop.ready, io.rel_pop.valid) node _T_26 = and(_T_25, io.rel_pop.bits.last) when _T_26 : node lists_clr_shiftAmount = bits(io.rel_pop.bits.index, 0, 0) node _lists_clr_T = dshl(UInt<1>(0h1), lists_clr_shiftAmount) node _lists_clr_T_1 = bits(_lists_clr_T, 1, 0) connect lists_clr, _lists_clr_T_1
module SinkC( // @[SinkC.scala:41:7] input clock, // @[SinkC.scala:41:7] input reset, // @[SinkC.scala:41:7] input io_req_ready, // @[SinkC.scala:43:14] output io_req_valid, // @[SinkC.scala:43:14] output [2:0] io_req_bits_opcode, // @[SinkC.scala:43:14] output [2:0] io_req_bits_param, // @[SinkC.scala:43:14] output [2:0] io_req_bits_size, // @[SinkC.scala:43:14] output [4:0] io_req_bits_source, // @[SinkC.scala:43:14] output [11:0] io_req_bits_tag, // @[SinkC.scala:43:14] output [5:0] io_req_bits_offset, // @[SinkC.scala:43:14] output [5:0] io_req_bits_put, // @[SinkC.scala:43:14] output [9:0] io_req_bits_set, // @[SinkC.scala:43:14] output io_resp_valid, // @[SinkC.scala:43:14] output io_resp_bits_last, // @[SinkC.scala:43:14] output [9:0] io_resp_bits_set, // @[SinkC.scala:43:14] output [11:0] io_resp_bits_tag, // @[SinkC.scala:43:14] output [4:0] io_resp_bits_source, // @[SinkC.scala:43:14] output [2:0] io_resp_bits_param, // @[SinkC.scala:43:14] output io_resp_bits_data, // @[SinkC.scala:43:14] output io_c_ready, // @[SinkC.scala:43:14] input io_c_valid, // @[SinkC.scala:43:14] input [2:0] io_c_bits_opcode, // @[SinkC.scala:43:14] input [2:0] io_c_bits_param, // @[SinkC.scala:43:14] input [2:0] io_c_bits_size, // @[SinkC.scala:43:14] input [4:0] io_c_bits_source, // @[SinkC.scala:43:14] input [31:0] io_c_bits_address, // @[SinkC.scala:43:14] input [63:0] io_c_bits_data, // @[SinkC.scala:43:14] input io_c_bits_corrupt, // @[SinkC.scala:43:14] output [9:0] io_set, // @[SinkC.scala:43:14] input [2:0] io_way, // @[SinkC.scala:43:14] input io_bs_adr_ready, // @[SinkC.scala:43:14] output io_bs_adr_valid, // @[SinkC.scala:43:14] output io_bs_adr_bits_noop, // @[SinkC.scala:43:14] output [2:0] io_bs_adr_bits_way, // @[SinkC.scala:43:14] output [9:0] io_bs_adr_bits_set, // @[SinkC.scala:43:14] output [2:0] io_bs_adr_bits_beat, // @[SinkC.scala:43:14] output io_bs_adr_bits_mask, // @[SinkC.scala:43:14] output [63:0] io_bs_dat_data, // @[SinkC.scala:43:14] output io_rel_pop_ready, // @[SinkC.scala:43:14] input io_rel_pop_valid, // @[SinkC.scala:43:14] input [5:0] io_rel_pop_bits_index, // @[SinkC.scala:43:14] input io_rel_pop_bits_last, // @[SinkC.scala:43:14] output [63:0] io_rel_beat_data, // @[SinkC.scala:43:14] output io_rel_beat_corrupt // @[SinkC.scala:43:14] ); wire [9:0] io_set_0; // @[SinkC.scala:41:7] wire _putbuffer_io_push_ready; // @[SinkC.scala:115:27] wire [1:0] _putbuffer_io_valid; // @[SinkC.scala:115:27] wire _c_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [2:0] _c_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] wire [2:0] _c_q_io_deq_bits_param; // @[Decoupled.scala:362:21] wire [2:0] _c_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [4:0] _c_q_io_deq_bits_source; // @[Decoupled.scala:362:21] wire [31:0] _c_q_io_deq_bits_address; // @[Decoupled.scala:362:21] wire [63:0] _c_q_io_deq_bits_data; // @[Decoupled.scala:362:21] wire _c_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] wire io_req_ready_0 = io_req_ready; // @[SinkC.scala:41:7] wire io_c_valid_0 = io_c_valid; // @[SinkC.scala:41:7] wire [2:0] io_c_bits_opcode_0 = io_c_bits_opcode; // @[SinkC.scala:41:7] wire [2:0] io_c_bits_param_0 = io_c_bits_param; // @[SinkC.scala:41:7] wire [2:0] io_c_bits_size_0 = io_c_bits_size; // @[SinkC.scala:41:7] wire [4:0] io_c_bits_source_0 = io_c_bits_source; // @[SinkC.scala:41:7] wire [31:0] io_c_bits_address_0 = io_c_bits_address; // @[SinkC.scala:41:7] wire [63:0] io_c_bits_data_0 = io_c_bits_data; // @[SinkC.scala:41:7] wire io_c_bits_corrupt_0 = io_c_bits_corrupt; // @[SinkC.scala:41:7] wire [2:0] io_way_0 = io_way; // @[SinkC.scala:41:7] wire io_bs_adr_ready_0 = io_bs_adr_ready; // @[SinkC.scala:41:7] wire io_rel_pop_valid_0 = io_rel_pop_valid; // @[SinkC.scala:41:7] wire [5:0] io_rel_pop_bits_index_0 = io_rel_pop_bits_index; // @[SinkC.scala:41:7] wire io_rel_pop_bits_last_0 = io_rel_pop_bits_last; // @[SinkC.scala:41:7] wire io_req_bits_prio_0 = 1'h0; // @[SinkC.scala:41:7] wire io_req_bits_prio_1 = 1'h0; // @[SinkC.scala:41:7] wire io_req_bits_control = 1'h0; // @[SinkC.scala:41:7] wire io_req_bits_prio_2 = 1'h1; // @[SinkC.scala:41:7] wire bs_adr_bits_mask = 1'h1; // @[SinkC.scala:96:22] wire _bs_adr_bits_mask_T = 1'h1; // @[SinkC.scala:104:25] wire _io_req_valid_T_6; // @[SinkC.scala:136:61] wire [11:0] tag_1; // @[Parameters.scala:217:9] wire [5:0] offset_1; // @[Parameters.scala:217:50] wire [9:0] set_1; // @[Parameters.scala:217:28] wire _io_resp_valid_T_5; // @[SinkC.scala:107:57] wire last; // @[Edges.scala:232:33] wire hasData; // @[Edges.scala:102:36] wire [9:0] _io_set_T; // @[SinkC.scala:92:18] wire [9:0] bs_adr_bits_set = io_set_0; // @[SinkC.scala:41:7, :96:22] wire [2:0] bs_adr_bits_way = io_way_0; // @[SinkC.scala:41:7, :96:22] wire _io_rel_pop_ready_T_2; // @[SinkC.scala:160:43] wire [2:0] io_req_bits_opcode_0; // @[SinkC.scala:41:7] wire [2:0] io_req_bits_param_0; // @[SinkC.scala:41:7] wire [2:0] io_req_bits_size_0; // @[SinkC.scala:41:7] wire [4:0] io_req_bits_source_0; // @[SinkC.scala:41:7] wire [11:0] io_req_bits_tag_0; // @[SinkC.scala:41:7] wire [5:0] io_req_bits_offset_0; // @[SinkC.scala:41:7] wire [5:0] io_req_bits_put_0; // @[SinkC.scala:41:7] wire [9:0] io_req_bits_set_0; // @[SinkC.scala:41:7] wire io_req_valid_0; // @[SinkC.scala:41:7] wire io_resp_bits_last_0; // @[SinkC.scala:41:7] wire [9:0] io_resp_bits_set_0; // @[SinkC.scala:41:7] wire [11:0] io_resp_bits_tag_0; // @[SinkC.scala:41:7] wire [4:0] io_resp_bits_source_0; // @[SinkC.scala:41:7] wire [2:0] io_resp_bits_param_0; // @[SinkC.scala:41:7] wire io_resp_bits_data_0; // @[SinkC.scala:41:7] wire io_resp_valid_0; // @[SinkC.scala:41:7] wire io_c_ready_0; // @[SinkC.scala:41:7] wire io_bs_adr_bits_noop_0; // @[SinkC.scala:41:7] wire [2:0] io_bs_adr_bits_way_0; // @[SinkC.scala:41:7] wire [9:0] io_bs_adr_bits_set_0; // @[SinkC.scala:41:7] wire [2:0] io_bs_adr_bits_beat_0; // @[SinkC.scala:41:7] wire io_bs_adr_bits_mask_0; // @[SinkC.scala:41:7] wire io_bs_adr_valid_0; // @[SinkC.scala:41:7] wire [63:0] io_bs_dat_data_0; // @[SinkC.scala:41:7] wire io_rel_pop_ready_0; // @[SinkC.scala:41:7] wire [63:0] io_rel_beat_data_0; // @[SinkC.scala:41:7] wire io_rel_beat_corrupt_0; // @[SinkC.scala:41:7] wire _offset_T = _c_q_io_deq_bits_address[0]; // @[Decoupled.scala:362:21] wire _offset_T_1 = _c_q_io_deq_bits_address[1]; // @[Decoupled.scala:362:21] wire _offset_T_2 = _c_q_io_deq_bits_address[2]; // @[Decoupled.scala:362:21] wire _offset_T_3 = _c_q_io_deq_bits_address[3]; // @[Decoupled.scala:362:21] wire _offset_T_4 = _c_q_io_deq_bits_address[4]; // @[Decoupled.scala:362:21] wire _offset_T_5 = _c_q_io_deq_bits_address[5]; // @[Decoupled.scala:362:21] wire _offset_T_6 = _c_q_io_deq_bits_address[6]; // @[Decoupled.scala:362:21] wire _offset_T_7 = _c_q_io_deq_bits_address[7]; // @[Decoupled.scala:362:21] wire _offset_T_8 = _c_q_io_deq_bits_address[8]; // @[Decoupled.scala:362:21] wire _offset_T_9 = _c_q_io_deq_bits_address[9]; // @[Decoupled.scala:362:21] wire _offset_T_10 = _c_q_io_deq_bits_address[10]; // @[Decoupled.scala:362:21] wire _offset_T_11 = _c_q_io_deq_bits_address[11]; // @[Decoupled.scala:362:21] wire _offset_T_12 = _c_q_io_deq_bits_address[12]; // @[Decoupled.scala:362:21] wire _offset_T_13 = _c_q_io_deq_bits_address[13]; // @[Decoupled.scala:362:21] wire _offset_T_14 = _c_q_io_deq_bits_address[14]; // @[Decoupled.scala:362:21] wire _offset_T_15 = _c_q_io_deq_bits_address[15]; // @[Decoupled.scala:362:21] wire _offset_T_16 = _c_q_io_deq_bits_address[16]; // @[Decoupled.scala:362:21] wire _offset_T_17 = _c_q_io_deq_bits_address[17]; // @[Decoupled.scala:362:21] wire _offset_T_18 = _c_q_io_deq_bits_address[18]; // @[Decoupled.scala:362:21] wire _offset_T_19 = _c_q_io_deq_bits_address[19]; // @[Decoupled.scala:362:21] wire _offset_T_20 = _c_q_io_deq_bits_address[20]; // @[Decoupled.scala:362:21] wire _offset_T_21 = _c_q_io_deq_bits_address[21]; // @[Decoupled.scala:362:21] wire _offset_T_22 = _c_q_io_deq_bits_address[22]; // @[Decoupled.scala:362:21] wire _offset_T_23 = _c_q_io_deq_bits_address[23]; // @[Decoupled.scala:362:21] wire _offset_T_24 = _c_q_io_deq_bits_address[24]; // @[Decoupled.scala:362:21] wire _offset_T_25 = _c_q_io_deq_bits_address[25]; // @[Decoupled.scala:362:21] wire _offset_T_26 = _c_q_io_deq_bits_address[26]; // @[Decoupled.scala:362:21] wire _offset_T_27 = _c_q_io_deq_bits_address[27]; // @[Decoupled.scala:362:21] wire [1:0] offset_lo_lo_lo_hi = {_offset_T_2, _offset_T_1}; // @[Parameters.scala:214:{21,47}] wire [2:0] offset_lo_lo_lo = {offset_lo_lo_lo_hi, _offset_T}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_lo_lo_hi_lo = {_offset_T_4, _offset_T_3}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_lo_lo_hi_hi = {_offset_T_6, _offset_T_5}; // @[Parameters.scala:214:{21,47}] wire [3:0] offset_lo_lo_hi = {offset_lo_lo_hi_hi, offset_lo_lo_hi_lo}; // @[Parameters.scala:214:21] wire [6:0] offset_lo_lo = {offset_lo_lo_hi, offset_lo_lo_lo}; // @[Parameters.scala:214:21] wire [1:0] offset_lo_hi_lo_hi = {_offset_T_9, _offset_T_8}; // @[Parameters.scala:214:{21,47}] wire [2:0] offset_lo_hi_lo = {offset_lo_hi_lo_hi, _offset_T_7}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_lo_hi_hi_lo = {_offset_T_11, _offset_T_10}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_lo_hi_hi_hi = {_offset_T_13, _offset_T_12}; // @[Parameters.scala:214:{21,47}] wire [3:0] offset_lo_hi_hi = {offset_lo_hi_hi_hi, offset_lo_hi_hi_lo}; // @[Parameters.scala:214:21] wire [6:0] offset_lo_hi = {offset_lo_hi_hi, offset_lo_hi_lo}; // @[Parameters.scala:214:21] wire [13:0] offset_lo = {offset_lo_hi, offset_lo_lo}; // @[Parameters.scala:214:21] wire [1:0] offset_hi_lo_lo_hi = {_offset_T_16, _offset_T_15}; // @[Parameters.scala:214:{21,47}] wire [2:0] offset_hi_lo_lo = {offset_hi_lo_lo_hi, _offset_T_14}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_hi_lo_hi_lo = {_offset_T_18, _offset_T_17}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_hi_lo_hi_hi = {_offset_T_20, _offset_T_19}; // @[Parameters.scala:214:{21,47}] wire [3:0] offset_hi_lo_hi = {offset_hi_lo_hi_hi, offset_hi_lo_hi_lo}; // @[Parameters.scala:214:21] wire [6:0] offset_hi_lo = {offset_hi_lo_hi, offset_hi_lo_lo}; // @[Parameters.scala:214:21] wire [1:0] offset_hi_hi_lo_hi = {_offset_T_23, _offset_T_22}; // @[Parameters.scala:214:{21,47}] wire [2:0] offset_hi_hi_lo = {offset_hi_hi_lo_hi, _offset_T_21}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_hi_hi_hi_lo = {_offset_T_25, _offset_T_24}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_hi_hi_hi_hi = {_offset_T_27, _offset_T_26}; // @[Parameters.scala:214:{21,47}] wire [3:0] offset_hi_hi_hi = {offset_hi_hi_hi_hi, offset_hi_hi_hi_lo}; // @[Parameters.scala:214:21] wire [6:0] offset_hi_hi = {offset_hi_hi_hi, offset_hi_hi_lo}; // @[Parameters.scala:214:21] wire [13:0] offset_hi = {offset_hi_hi, offset_hi_lo}; // @[Parameters.scala:214:21] wire [27:0] offset = {offset_hi, offset_lo}; // @[Parameters.scala:214:21] wire [21:0] set = offset[27:6]; // @[Parameters.scala:214:21, :215:22] wire [11:0] tag = set[21:10]; // @[Parameters.scala:215:22, :216:19] assign tag_1 = tag; // @[Parameters.scala:216:19, :217:9] assign io_req_bits_tag_0 = tag_1; // @[SinkC.scala:41:7] assign io_resp_bits_tag_0 = tag_1; // @[SinkC.scala:41:7] assign set_1 = set[9:0]; // @[Parameters.scala:215:22, :217:28] assign io_req_bits_set_0 = set_1; // @[SinkC.scala:41:7] assign io_resp_bits_set_0 = set_1; // @[SinkC.scala:41:7] assign offset_1 = offset[5:0]; // @[Parameters.scala:214:21, :217:50] assign io_req_bits_offset_0 = offset_1; // @[SinkC.scala:41:7] wire _q_io_deq_ready_T_7; // @[SinkC.scala:134:19] wire _T = _q_io_deq_ready_T_7 & _c_q_io_deq_valid; // @[Decoupled.scala:51:35, :362:21] wire [12:0] _r_beats1_decode_T = 13'h3F << _c_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [5:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] r_beats1_decode = _r_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire r_beats1_opdata = _c_q_io_deq_bits_opcode[0]; // @[Decoupled.scala:362:21] assign hasData = _c_q_io_deq_bits_opcode[0]; // @[Decoupled.scala:362:21] wire [2:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 3'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [2:0] r_counter; // @[Edges.scala:229:27] wire [3:0] _r_counter1_T = {1'h0, r_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] r_counter1 = _r_counter1_T[2:0]; // @[Edges.scala:230:28] wire first = r_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T = r_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_1 = r_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] assign last = _r_last_T | _r_last_T_1; // @[Edges.scala:232:{25,33,43}] assign io_resp_bits_last_0 = last; // @[Edges.scala:232:33] wire r_3 = last & _T; // @[Decoupled.scala:51:35] wire [2:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] beat = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _r_counter_T = first ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] assign io_resp_bits_data_0 = hasData; // @[Edges.scala:102:36] wire _raw_resp_T = _c_q_io_deq_bits_opcode == 3'h4; // @[Decoupled.scala:362:21] wire _raw_resp_T_1 = _c_q_io_deq_bits_opcode == 3'h5; // @[Decoupled.scala:362:21] wire raw_resp = _raw_resp_T | _raw_resp_T_1; // @[SinkC.scala:78:{34,58,75}] reg resp_r; // @[SinkC.scala:79:48] wire resp = _c_q_io_deq_valid ? raw_resp : resp_r; // @[Decoupled.scala:362:21]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_38 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<12>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 11, 0) node _source_ok_T = shr(io.in.a.bits.source, 12) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<12>(0h80f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits = bits(_uncommonBits_T, 11, 0) node _T_4 = shr(io.in.a.bits.source, 12) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<12>(0h80f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 11, 0) node _T_24 = shr(io.in.a.bits.source, 12) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<12>(0h80f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 11, 0) node _T_86 = shr(io.in.a.bits.source, 12) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<12>(0h80f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 11, 0) node _T_152 = shr(io.in.a.bits.source, 12) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<12>(0h80f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 11, 0) node _T_199 = shr(io.in.a.bits.source, 12) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<12>(0h80f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 11, 0) node _T_240 = shr(io.in.a.bits.source, 12) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<12>(0h80f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 11, 0) node _T_283 = shr(io.in.a.bits.source, 12) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<12>(0h80f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 11, 0) node _T_321 = shr(io.in.a.bits.source, 12) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<12>(0h80f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 11, 0) node _T_359 = shr(io.in.a.bits.source, 12) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<12>(0h80f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<12>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 11, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 12) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<12>(0h80f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<26>(0h0) connect _WIRE.bits.source, UInt<12>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<26>(0h0) connect _WIRE_2.bits.source, UInt<12>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2064>, clock, reset, UInt<2064>(0h0) regreset inflight_opcodes : UInt<8256>, clock, reset, UInt<8256>(0h0) regreset inflight_sizes : UInt<8256>, clock, reset, UInt<8256>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<2064> connect a_set, UInt<2064>(0h0) wire a_set_wo_ready : UInt<2064> connect a_set_wo_ready, UInt<2064>(0h0) wire a_opcodes_set : UInt<8256> connect a_opcodes_set, UInt<8256>(0h0) wire a_sizes_set : UInt<8256> connect a_sizes_set, UInt<8256>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<2064> connect d_clr, UInt<2064>(0h0) wire d_clr_wo_ready : UInt<2064> connect d_clr_wo_ready, UInt<2064>(0h0) wire d_opcodes_clr : UInt<8256> connect d_opcodes_clr, UInt<8256>(0h0) wire d_sizes_clr : UInt<8256> connect d_sizes_clr, UInt<8256>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_657 = orr(a_set_wo_ready) node _T_658 = eq(_T_657, UInt<1>(0h0)) node _T_659 = or(_T_656, _T_658) node _T_660 = asUInt(reset) node _T_661 = eq(_T_660, UInt<1>(0h0)) when _T_661 : node _T_662 = eq(_T_659, UInt<1>(0h0)) when _T_662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_659, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_76 node _T_663 = orr(inflight) node _T_664 = eq(_T_663, UInt<1>(0h0)) node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_666 = or(_T_664, _T_665) node _T_667 = lt(watchdog, plusarg_reader.out) node _T_668 = or(_T_666, _T_667) node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(_T_668, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_668, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_672 = and(io.in.a.ready, io.in.a.valid) node _T_673 = and(io.in.d.ready, io.in.d.valid) node _T_674 = or(_T_672, _T_673) when _T_674 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2064>, clock, reset, UInt<2064>(0h0) regreset inflight_opcodes_1 : UInt<8256>, clock, reset, UInt<8256>(0h0) regreset inflight_sizes_1 : UInt<8256>, clock, reset, UInt<8256>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<26>(0h0) connect _c_first_WIRE.bits.source, UInt<12>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<26>(0h0) connect _c_first_WIRE_2.bits.source, UInt<12>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<2064> connect c_set, UInt<2064>(0h0) wire c_set_wo_ready : UInt<2064> connect c_set_wo_ready, UInt<2064>(0h0) wire c_opcodes_set : UInt<8256> connect c_opcodes_set, UInt<8256>(0h0) wire c_sizes_set : UInt<8256> connect c_sizes_set, UInt<8256>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<26>(0h0) connect _WIRE_6.bits.source, UInt<12>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_675 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<26>(0h0) connect _WIRE_8.bits.source, UInt<12>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_678 = and(_T_676, _T_677) node _T_679 = and(_T_675, _T_678) when _T_679 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<26>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<12>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<26>(0h0) connect _WIRE_10.bits.source, UInt<12>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_681 = and(_T_680, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<26>(0h0) connect _WIRE_12.bits.source, UInt<12>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_684 = and(_T_682, _T_683) node _T_685 = and(_T_681, _T_684) when _T_685 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<26>(0h0) connect _c_set_WIRE.bits.source, UInt<12>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<26>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<12>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<26>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<12>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<26>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<12>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<26>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<12>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<26>(0h0) connect _WIRE_14.bits.source, UInt<12>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_686 = dshr(inflight_1, _WIRE_15.bits.source) node _T_687 = bits(_T_686, 0, 0) node _T_688 = eq(_T_687, UInt<1>(0h0)) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_688, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<26>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<12>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<26>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<12>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<2064> connect d_clr_1, UInt<2064>(0h0) wire d_clr_wo_ready_1 : UInt<2064> connect d_clr_wo_ready_1, UInt<2064>(0h0) wire d_opcodes_clr_1 : UInt<8256> connect d_opcodes_clr_1, UInt<8256>(0h0) wire d_sizes_clr_1 : UInt<8256> connect d_sizes_clr_1, UInt<8256>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_695 = and(io.in.d.ready, io.in.d.valid) node _T_696 = and(_T_695, d_first_2) node _T_697 = and(_T_696, UInt<1>(0h1)) node _T_698 = and(_T_697, d_release_ack_1) when _T_698 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_699 = and(io.in.d.valid, d_first_2) node _T_700 = and(_T_699, UInt<1>(0h1)) node _T_701 = and(_T_700, d_release_ack_1) when _T_701 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<12>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<12>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<12>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_702 = dshr(inflight_1, io.in.d.bits.source) node _T_703 = bits(_T_702, 0, 0) node _T_704 = or(_T_703, same_cycle_resp_1) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_704, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<26>(0h0) connect _WIRE_16.bits.source, UInt<12>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_709 = asUInt(reset) node _T_710 = eq(_T_709, UInt<1>(0h0)) when _T_710 : node _T_711 = eq(_T_708, UInt<1>(0h0)) when _T_711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_708, UInt<1>(0h1), "") : assert_109 else : node _T_712 = eq(io.in.d.bits.size, c_size_lookup) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_712, UInt<1>(0h1), "") : assert_110 node _T_716 = and(io.in.d.valid, d_first_2) node _T_717 = and(_T_716, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<26>(0h0) connect _WIRE_18.bits.source, UInt<12>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_718 = and(_T_717, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<26>(0h0) connect _WIRE_20.bits.source, UInt<12>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_720 = and(_T_718, _T_719) node _T_721 = and(_T_720, d_release_ack_1) node _T_722 = eq(c_probe_ack, UInt<1>(0h0)) node _T_723 = and(_T_721, _T_722) when _T_723 : node _T_724 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<26>(0h0) connect _WIRE_22.bits.source, UInt<12>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_725 = or(_T_724, _WIRE_23.ready) node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(_T_725, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_725, UInt<1>(0h1), "") : assert_111 node _T_729 = orr(c_set_wo_ready) when _T_729 : node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_731 = asUInt(reset) node _T_732 = eq(_T_731, UInt<1>(0h0)) when _T_732 : node _T_733 = eq(_T_730, UInt<1>(0h0)) when _T_733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_730, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_77 node _T_734 = orr(inflight_1) node _T_735 = eq(_T_734, UInt<1>(0h0)) node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_737 = or(_T_735, _T_736) node _T_738 = lt(watchdog_1, plusarg_reader_1.out) node _T_739 = or(_T_737, _T_738) node _T_740 = asUInt(reset) node _T_741 = eq(_T_740, UInt<1>(0h0)) when _T_741 : node _T_742 = eq(_T_739, UInt<1>(0h0)) when _T_742 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_739, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<26>(0h0) connect _WIRE_24.bits.source, UInt<12>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_744 = and(io.in.d.ready, io.in.d.valid) node _T_745 = or(_T_743, _T_744) when _T_745 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_38( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [25:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [11:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [11:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [25:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [11:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [25:0] _c_first_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_first_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_first_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_first_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_set_wo_ready_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_set_wo_ready_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_opcodes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_opcodes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_sizes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_sizes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_opcodes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_opcodes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_sizes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_sizes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_probe_ack_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_probe_ack_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_probe_ack_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_probe_ack_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_4_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_5_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_wo_ready_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_wo_ready_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_interm_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_interm_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_interm_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_interm_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_4_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_5_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [32769:0] _c_sizes_set_T_1 = 32770'h0; // @[Monitor.scala:768:52] wire [14:0] _c_opcodes_set_T = 15'h0; // @[Monitor.scala:767:79] wire [14:0] _c_sizes_set_T = 15'h0; // @[Monitor.scala:768:77] wire [32770:0] _c_opcodes_set_T_1 = 32771'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [4095:0] _c_set_wo_ready_T = 4096'h1; // @[OneHot.scala:58:35] wire [4095:0] _c_set_T = 4096'h1; // @[OneHot.scala:58:35] wire [8255:0] c_opcodes_set = 8256'h0; // @[Monitor.scala:740:34] wire [8255:0] c_sizes_set = 8256'h0; // @[Monitor.scala:741:34] wire [2063:0] c_set = 2064'h0; // @[Monitor.scala:738:34] wire [2063:0] c_set_wo_ready = 2064'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [11:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 12'h810; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [25:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 26'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [11:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [11:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 12'h810; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_672; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [11:0] source; // @[Monitor.scala:390:22] reg [25:0] address; // @[Monitor.scala:391:22] wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [11:0] source_1; // @[Monitor.scala:541:22] reg [2063:0] inflight; // @[Monitor.scala:614:27] reg [8255:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [8255:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [2063:0] a_set; // @[Monitor.scala:626:34] wire [2063:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [8255:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [8255:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [14:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [14:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [14:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [14:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [14:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [14:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [14:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [14:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [14:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [8255:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [8255:0] _a_opcode_lookup_T_6 = {8252'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [8255:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[8255:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [8255:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [8255:0] _a_size_lookup_T_6 = {8252'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [8255:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[8255:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [4095:0] _GEN_2 = 4096'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [4095:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [4095:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [14:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [14:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [14:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [32770:0] _a_opcodes_set_T_1 = {32767'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[8255:0] : 8256'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [32769:0] _a_sizes_set_T_1 = {32767'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[8255:0] : 8256'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [2063:0] d_clr; // @[Monitor.scala:664:34] wire [2063:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [8255:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [8255:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [4095:0] _GEN_5 = 4096'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire [32782:0] _d_opcodes_clr_T_5 = 32783'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[8255:0] : 8256'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [32782:0] _d_sizes_clr_T_5 = 32783'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[8255:0] : 8256'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [2063:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [2063:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [2063:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [8255:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [8255:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [8255:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [8255:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [8255:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [8255:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [2063:0] inflight_1; // @[Monitor.scala:726:35] wire [2063:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [8255:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [8255:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [8255:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [8255:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [8255:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [8255:0] _c_opcode_lookup_T_6 = {8252'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [8255:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[8255:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [8255:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [8255:0] _c_size_lookup_T_6 = {8252'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [8255:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[8255:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [2063:0] d_clr_1; // @[Monitor.scala:774:34] wire [2063:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [8255:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [8255:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_698 ? _d_clr_T_1[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire [32782:0] _d_opcodes_clr_T_11 = 32783'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[8255:0] : 8256'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [32782:0] _d_sizes_clr_T_11 = 32783'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[8255:0] : 8256'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 12'h0; // @[Monitor.scala:36:7, :795:113] wire [2063:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [2063:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [8255:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [8255:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [8255:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [8255:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_40 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) node _source_ok_T_1 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _source_ok_T_2 = eq(io.in.a.bits.source, UInt<2>(0h2)) wire _source_ok_WIRE : UInt<1>[3] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_1 connect _source_ok_WIRE[2], _source_ok_T_2 node _source_ok_T_3 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node source_ok = or(_source_ok_T_3, _source_ok_WIRE[2]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_15 = cvt(_T_14) node _T_16 = and(_T_15, asSInt(UInt<1>(0h0))) node _T_17 = asSInt(_T_16) node _T_18 = eq(_T_17, asSInt(UInt<1>(0h0))) node _T_19 = or(_T_13, _T_18) node _T_20 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_21 = eq(_T_20, UInt<1>(0h0)) node _T_22 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_23 = cvt(_T_22) node _T_24 = and(_T_23, asSInt(UInt<1>(0h0))) node _T_25 = asSInt(_T_24) node _T_26 = eq(_T_25, asSInt(UInt<1>(0h0))) node _T_27 = or(_T_21, _T_26) node _T_28 = and(_T_11, _T_19) node _T_29 = and(_T_28, _T_27) node _T_30 = asUInt(reset) node _T_31 = eq(_T_30, UInt<1>(0h0)) when _T_31 : node _T_32 = eq(_T_29, UInt<1>(0h0)) when _T_32 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_29, UInt<1>(0h1), "") : assert_1 node _T_33 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_33 : node _T_34 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_35 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_36 = and(_T_34, _T_35) node _T_37 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_38 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_39 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_40 = or(_T_37, _T_38) node _T_41 = or(_T_40, _T_39) node _T_42 = and(_T_36, _T_41) node _T_43 = or(UInt<1>(0h0), _T_42) node _T_44 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<14>(0h2000))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_51 = cvt(_T_50) node _T_52 = and(_T_51, asSInt(UInt<13>(0h1000))) node _T_53 = asSInt(_T_52) node _T_54 = eq(_T_53, asSInt(UInt<1>(0h0))) node _T_55 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_56 = cvt(_T_55) node _T_57 = and(_T_56, asSInt(UInt<17>(0h10000))) node _T_58 = asSInt(_T_57) node _T_59 = eq(_T_58, asSInt(UInt<1>(0h0))) node _T_60 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_61 = cvt(_T_60) node _T_62 = and(_T_61, asSInt(UInt<18>(0h2f000))) node _T_63 = asSInt(_T_62) node _T_64 = eq(_T_63, asSInt(UInt<1>(0h0))) node _T_65 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_66 = cvt(_T_65) node _T_67 = and(_T_66, asSInt(UInt<17>(0h10000))) node _T_68 = asSInt(_T_67) node _T_69 = eq(_T_68, asSInt(UInt<1>(0h0))) node _T_70 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_71 = cvt(_T_70) node _T_72 = and(_T_71, asSInt(UInt<13>(0h1000))) node _T_73 = asSInt(_T_72) node _T_74 = eq(_T_73, asSInt(UInt<1>(0h0))) node _T_75 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_76 = cvt(_T_75) node _T_77 = and(_T_76, asSInt(UInt<27>(0h4000000))) node _T_78 = asSInt(_T_77) node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0))) node _T_80 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_81 = cvt(_T_80) node _T_82 = and(_T_81, asSInt(UInt<13>(0h1000))) node _T_83 = asSInt(_T_82) node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = or(_T_49, _T_54) node _T_86 = or(_T_85, _T_59) node _T_87 = or(_T_86, _T_64) node _T_88 = or(_T_87, _T_69) node _T_89 = or(_T_88, _T_74) node _T_90 = or(_T_89, _T_79) node _T_91 = or(_T_90, _T_84) node _T_92 = and(_T_44, _T_91) node _T_93 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<29>(0h10000000))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = or(_T_99, _T_104) node _T_106 = and(_T_94, _T_105) node _T_107 = or(UInt<1>(0h0), _T_92) node _T_108 = or(_T_107, _T_106) node _T_109 = and(_T_43, _T_108) node _T_110 = asUInt(reset) node _T_111 = eq(_T_110, UInt<1>(0h0)) when _T_111 : node _T_112 = eq(_T_109, UInt<1>(0h0)) when _T_112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_109, UInt<1>(0h1), "") : assert_2 node _T_113 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_114 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_115 = eq(io.in.a.bits.source, UInt<2>(0h2)) wire _WIRE : UInt<1>[3] connect _WIRE[0], _T_113 connect _WIRE[1], _T_114 connect _WIRE[2], _T_115 node _T_116 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_117 = mux(_WIRE[0], _T_116, UInt<1>(0h0)) node _T_118 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_119 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_120 = or(_T_117, _T_118) node _T_121 = or(_T_120, _T_119) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_121 node _T_122 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_123 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_124 = and(_T_122, _T_123) node _T_125 = or(UInt<1>(0h0), _T_124) node _T_126 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_127 = cvt(_T_126) node _T_128 = and(_T_127, asSInt(UInt<14>(0h2000))) node _T_129 = asSInt(_T_128) node _T_130 = eq(_T_129, asSInt(UInt<1>(0h0))) node _T_131 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_132 = cvt(_T_131) node _T_133 = and(_T_132, asSInt(UInt<13>(0h1000))) node _T_134 = asSInt(_T_133) node _T_135 = eq(_T_134, asSInt(UInt<1>(0h0))) node _T_136 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_137 = cvt(_T_136) node _T_138 = and(_T_137, asSInt(UInt<17>(0h10000))) node _T_139 = asSInt(_T_138) node _T_140 = eq(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_142 = cvt(_T_141) node _T_143 = and(_T_142, asSInt(UInt<18>(0h2f000))) node _T_144 = asSInt(_T_143) node _T_145 = eq(_T_144, asSInt(UInt<1>(0h0))) node _T_146 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<17>(0h10000))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_152 = cvt(_T_151) node _T_153 = and(_T_152, asSInt(UInt<13>(0h1000))) node _T_154 = asSInt(_T_153) node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) node _T_156 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_157 = cvt(_T_156) node _T_158 = and(_T_157, asSInt(UInt<17>(0h10000))) node _T_159 = asSInt(_T_158) node _T_160 = eq(_T_159, asSInt(UInt<1>(0h0))) node _T_161 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_162 = cvt(_T_161) node _T_163 = and(_T_162, asSInt(UInt<27>(0h4000000))) node _T_164 = asSInt(_T_163) node _T_165 = eq(_T_164, asSInt(UInt<1>(0h0))) node _T_166 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_167 = cvt(_T_166) node _T_168 = and(_T_167, asSInt(UInt<13>(0h1000))) node _T_169 = asSInt(_T_168) node _T_170 = eq(_T_169, asSInt(UInt<1>(0h0))) node _T_171 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_172 = cvt(_T_171) node _T_173 = and(_T_172, asSInt(UInt<29>(0h10000000))) node _T_174 = asSInt(_T_173) node _T_175 = eq(_T_174, asSInt(UInt<1>(0h0))) node _T_176 = or(_T_130, _T_135) node _T_177 = or(_T_176, _T_140) node _T_178 = or(_T_177, _T_145) node _T_179 = or(_T_178, _T_150) node _T_180 = or(_T_179, _T_155) node _T_181 = or(_T_180, _T_160) node _T_182 = or(_T_181, _T_165) node _T_183 = or(_T_182, _T_170) node _T_184 = or(_T_183, _T_175) node _T_185 = and(_T_125, _T_184) node _T_186 = or(UInt<1>(0h0), _T_185) node _T_187 = and(_WIRE_1, _T_186) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_187, UInt<1>(0h1), "") : assert_3 node _T_191 = asUInt(reset) node _T_192 = eq(_T_191, UInt<1>(0h0)) when _T_192 : node _T_193 = eq(source_ok, UInt<1>(0h0)) when _T_193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_194 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_195 = asUInt(reset) node _T_196 = eq(_T_195, UInt<1>(0h0)) when _T_196 : node _T_197 = eq(_T_194, UInt<1>(0h0)) when _T_197 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_194, UInt<1>(0h1), "") : assert_5 node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(is_aligned, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_201 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_202 = asUInt(reset) node _T_203 = eq(_T_202, UInt<1>(0h0)) when _T_203 : node _T_204 = eq(_T_201, UInt<1>(0h0)) when _T_204 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_201, UInt<1>(0h1), "") : assert_7 node _T_205 = not(io.in.a.bits.mask) node _T_206 = eq(_T_205, UInt<1>(0h0)) node _T_207 = asUInt(reset) node _T_208 = eq(_T_207, UInt<1>(0h0)) when _T_208 : node _T_209 = eq(_T_206, UInt<1>(0h0)) when _T_209 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_206, UInt<1>(0h1), "") : assert_8 node _T_210 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_211 = asUInt(reset) node _T_212 = eq(_T_211, UInt<1>(0h0)) when _T_212 : node _T_213 = eq(_T_210, UInt<1>(0h0)) when _T_213 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_210, UInt<1>(0h1), "") : assert_9 node _T_214 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_214 : node _T_215 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_216 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_217 = and(_T_215, _T_216) node _T_218 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_219 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_220 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_221 = or(_T_218, _T_219) node _T_222 = or(_T_221, _T_220) node _T_223 = and(_T_217, _T_222) node _T_224 = or(UInt<1>(0h0), _T_223) node _T_225 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_226 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<14>(0h2000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_232 = cvt(_T_231) node _T_233 = and(_T_232, asSInt(UInt<13>(0h1000))) node _T_234 = asSInt(_T_233) node _T_235 = eq(_T_234, asSInt(UInt<1>(0h0))) node _T_236 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_237 = cvt(_T_236) node _T_238 = and(_T_237, asSInt(UInt<17>(0h10000))) node _T_239 = asSInt(_T_238) node _T_240 = eq(_T_239, asSInt(UInt<1>(0h0))) node _T_241 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<18>(0h2f000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<17>(0h10000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_252 = cvt(_T_251) node _T_253 = and(_T_252, asSInt(UInt<13>(0h1000))) node _T_254 = asSInt(_T_253) node _T_255 = eq(_T_254, asSInt(UInt<1>(0h0))) node _T_256 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_257 = cvt(_T_256) node _T_258 = and(_T_257, asSInt(UInt<27>(0h4000000))) node _T_259 = asSInt(_T_258) node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_262 = cvt(_T_261) node _T_263 = and(_T_262, asSInt(UInt<13>(0h1000))) node _T_264 = asSInt(_T_263) node _T_265 = eq(_T_264, asSInt(UInt<1>(0h0))) node _T_266 = or(_T_230, _T_235) node _T_267 = or(_T_266, _T_240) node _T_268 = or(_T_267, _T_245) node _T_269 = or(_T_268, _T_250) node _T_270 = or(_T_269, _T_255) node _T_271 = or(_T_270, _T_260) node _T_272 = or(_T_271, _T_265) node _T_273 = and(_T_225, _T_272) node _T_274 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_275 = or(UInt<1>(0h0), _T_274) node _T_276 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_277 = cvt(_T_276) node _T_278 = and(_T_277, asSInt(UInt<17>(0h10000))) node _T_279 = asSInt(_T_278) node _T_280 = eq(_T_279, asSInt(UInt<1>(0h0))) node _T_281 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_282 = cvt(_T_281) node _T_283 = and(_T_282, asSInt(UInt<29>(0h10000000))) node _T_284 = asSInt(_T_283) node _T_285 = eq(_T_284, asSInt(UInt<1>(0h0))) node _T_286 = or(_T_280, _T_285) node _T_287 = and(_T_275, _T_286) node _T_288 = or(UInt<1>(0h0), _T_273) node _T_289 = or(_T_288, _T_287) node _T_290 = and(_T_224, _T_289) node _T_291 = asUInt(reset) node _T_292 = eq(_T_291, UInt<1>(0h0)) when _T_292 : node _T_293 = eq(_T_290, UInt<1>(0h0)) when _T_293 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_290, UInt<1>(0h1), "") : assert_10 node _T_294 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_295 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_296 = eq(io.in.a.bits.source, UInt<2>(0h2)) wire _WIRE_2 : UInt<1>[3] connect _WIRE_2[0], _T_294 connect _WIRE_2[1], _T_295 connect _WIRE_2[2], _T_296 node _T_297 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_298 = mux(_WIRE_2[0], _T_297, UInt<1>(0h0)) node _T_299 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_300 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_301 = or(_T_298, _T_299) node _T_302 = or(_T_301, _T_300) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_302 node _T_303 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_304 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_305 = and(_T_303, _T_304) node _T_306 = or(UInt<1>(0h0), _T_305) node _T_307 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_308 = cvt(_T_307) node _T_309 = and(_T_308, asSInt(UInt<14>(0h2000))) node _T_310 = asSInt(_T_309) node _T_311 = eq(_T_310, asSInt(UInt<1>(0h0))) node _T_312 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_313 = cvt(_T_312) node _T_314 = and(_T_313, asSInt(UInt<13>(0h1000))) node _T_315 = asSInt(_T_314) node _T_316 = eq(_T_315, asSInt(UInt<1>(0h0))) node _T_317 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_318 = cvt(_T_317) node _T_319 = and(_T_318, asSInt(UInt<17>(0h10000))) node _T_320 = asSInt(_T_319) node _T_321 = eq(_T_320, asSInt(UInt<1>(0h0))) node _T_322 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_323 = cvt(_T_322) node _T_324 = and(_T_323, asSInt(UInt<18>(0h2f000))) node _T_325 = asSInt(_T_324) node _T_326 = eq(_T_325, asSInt(UInt<1>(0h0))) node _T_327 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_328 = cvt(_T_327) node _T_329 = and(_T_328, asSInt(UInt<17>(0h10000))) node _T_330 = asSInt(_T_329) node _T_331 = eq(_T_330, asSInt(UInt<1>(0h0))) node _T_332 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_333 = cvt(_T_332) node _T_334 = and(_T_333, asSInt(UInt<13>(0h1000))) node _T_335 = asSInt(_T_334) node _T_336 = eq(_T_335, asSInt(UInt<1>(0h0))) node _T_337 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_338 = cvt(_T_337) node _T_339 = and(_T_338, asSInt(UInt<17>(0h10000))) node _T_340 = asSInt(_T_339) node _T_341 = eq(_T_340, asSInt(UInt<1>(0h0))) node _T_342 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_343 = cvt(_T_342) node _T_344 = and(_T_343, asSInt(UInt<27>(0h4000000))) node _T_345 = asSInt(_T_344) node _T_346 = eq(_T_345, asSInt(UInt<1>(0h0))) node _T_347 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_348 = cvt(_T_347) node _T_349 = and(_T_348, asSInt(UInt<13>(0h1000))) node _T_350 = asSInt(_T_349) node _T_351 = eq(_T_350, asSInt(UInt<1>(0h0))) node _T_352 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_353 = cvt(_T_352) node _T_354 = and(_T_353, asSInt(UInt<29>(0h10000000))) node _T_355 = asSInt(_T_354) node _T_356 = eq(_T_355, asSInt(UInt<1>(0h0))) node _T_357 = or(_T_311, _T_316) node _T_358 = or(_T_357, _T_321) node _T_359 = or(_T_358, _T_326) node _T_360 = or(_T_359, _T_331) node _T_361 = or(_T_360, _T_336) node _T_362 = or(_T_361, _T_341) node _T_363 = or(_T_362, _T_346) node _T_364 = or(_T_363, _T_351) node _T_365 = or(_T_364, _T_356) node _T_366 = and(_T_306, _T_365) node _T_367 = or(UInt<1>(0h0), _T_366) node _T_368 = and(_WIRE_3, _T_367) node _T_369 = asUInt(reset) node _T_370 = eq(_T_369, UInt<1>(0h0)) when _T_370 : node _T_371 = eq(_T_368, UInt<1>(0h0)) when _T_371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_368, UInt<1>(0h1), "") : assert_11 node _T_372 = asUInt(reset) node _T_373 = eq(_T_372, UInt<1>(0h0)) when _T_373 : node _T_374 = eq(source_ok, UInt<1>(0h0)) when _T_374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_375 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_375, UInt<1>(0h1), "") : assert_13 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(is_aligned, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_382 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(_T_382, UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_382, UInt<1>(0h1), "") : assert_15 node _T_386 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_387 = asUInt(reset) node _T_388 = eq(_T_387, UInt<1>(0h0)) when _T_388 : node _T_389 = eq(_T_386, UInt<1>(0h0)) when _T_389 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_386, UInt<1>(0h1), "") : assert_16 node _T_390 = not(io.in.a.bits.mask) node _T_391 = eq(_T_390, UInt<1>(0h0)) node _T_392 = asUInt(reset) node _T_393 = eq(_T_392, UInt<1>(0h0)) when _T_393 : node _T_394 = eq(_T_391, UInt<1>(0h0)) when _T_394 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_391, UInt<1>(0h1), "") : assert_17 node _T_395 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_396 = asUInt(reset) node _T_397 = eq(_T_396, UInt<1>(0h0)) when _T_397 : node _T_398 = eq(_T_395, UInt<1>(0h0)) when _T_398 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_395, UInt<1>(0h1), "") : assert_18 node _T_399 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_399 : node _T_400 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_401 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_402 = and(_T_400, _T_401) node _T_403 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_404 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_405 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_406 = or(_T_403, _T_404) node _T_407 = or(_T_406, _T_405) node _T_408 = and(_T_402, _T_407) node _T_409 = or(UInt<1>(0h0), _T_408) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_409, UInt<1>(0h1), "") : assert_19 node _T_413 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_414 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_415 = and(_T_413, _T_414) node _T_416 = or(UInt<1>(0h0), _T_415) node _T_417 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_418 = cvt(_T_417) node _T_419 = and(_T_418, asSInt(UInt<13>(0h1000))) node _T_420 = asSInt(_T_419) node _T_421 = eq(_T_420, asSInt(UInt<1>(0h0))) node _T_422 = and(_T_416, _T_421) node _T_423 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_424 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_425 = and(_T_423, _T_424) node _T_426 = or(UInt<1>(0h0), _T_425) node _T_427 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_428 = cvt(_T_427) node _T_429 = and(_T_428, asSInt(UInt<14>(0h2000))) node _T_430 = asSInt(_T_429) node _T_431 = eq(_T_430, asSInt(UInt<1>(0h0))) node _T_432 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_433 = cvt(_T_432) node _T_434 = and(_T_433, asSInt(UInt<17>(0h10000))) node _T_435 = asSInt(_T_434) node _T_436 = eq(_T_435, asSInt(UInt<1>(0h0))) node _T_437 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_438 = cvt(_T_437) node _T_439 = and(_T_438, asSInt(UInt<18>(0h2f000))) node _T_440 = asSInt(_T_439) node _T_441 = eq(_T_440, asSInt(UInt<1>(0h0))) node _T_442 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_443 = cvt(_T_442) node _T_444 = and(_T_443, asSInt(UInt<17>(0h10000))) node _T_445 = asSInt(_T_444) node _T_446 = eq(_T_445, asSInt(UInt<1>(0h0))) node _T_447 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_448 = cvt(_T_447) node _T_449 = and(_T_448, asSInt(UInt<13>(0h1000))) node _T_450 = asSInt(_T_449) node _T_451 = eq(_T_450, asSInt(UInt<1>(0h0))) node _T_452 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_453 = cvt(_T_452) node _T_454 = and(_T_453, asSInt(UInt<17>(0h10000))) node _T_455 = asSInt(_T_454) node _T_456 = eq(_T_455, asSInt(UInt<1>(0h0))) node _T_457 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_458 = cvt(_T_457) node _T_459 = and(_T_458, asSInt(UInt<27>(0h4000000))) node _T_460 = asSInt(_T_459) node _T_461 = eq(_T_460, asSInt(UInt<1>(0h0))) node _T_462 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_463 = cvt(_T_462) node _T_464 = and(_T_463, asSInt(UInt<13>(0h1000))) node _T_465 = asSInt(_T_464) node _T_466 = eq(_T_465, asSInt(UInt<1>(0h0))) node _T_467 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<29>(0h10000000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = or(_T_431, _T_436) node _T_473 = or(_T_472, _T_441) node _T_474 = or(_T_473, _T_446) node _T_475 = or(_T_474, _T_451) node _T_476 = or(_T_475, _T_456) node _T_477 = or(_T_476, _T_461) node _T_478 = or(_T_477, _T_466) node _T_479 = or(_T_478, _T_471) node _T_480 = and(_T_426, _T_479) node _T_481 = or(UInt<1>(0h0), _T_422) node _T_482 = or(_T_481, _T_480) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_482, UInt<1>(0h1), "") : assert_20 node _T_486 = asUInt(reset) node _T_487 = eq(_T_486, UInt<1>(0h0)) when _T_487 : node _T_488 = eq(source_ok, UInt<1>(0h0)) when _T_488 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(is_aligned, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_492 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_493 = asUInt(reset) node _T_494 = eq(_T_493, UInt<1>(0h0)) when _T_494 : node _T_495 = eq(_T_492, UInt<1>(0h0)) when _T_495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_492, UInt<1>(0h1), "") : assert_23 node _T_496 = eq(io.in.a.bits.mask, mask) node _T_497 = asUInt(reset) node _T_498 = eq(_T_497, UInt<1>(0h0)) when _T_498 : node _T_499 = eq(_T_496, UInt<1>(0h0)) when _T_499 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_496, UInt<1>(0h1), "") : assert_24 node _T_500 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_501 = asUInt(reset) node _T_502 = eq(_T_501, UInt<1>(0h0)) when _T_502 : node _T_503 = eq(_T_500, UInt<1>(0h0)) when _T_503 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_500, UInt<1>(0h1), "") : assert_25 node _T_504 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_504 : node _T_505 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_506 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_507 = and(_T_505, _T_506) node _T_508 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_509 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_510 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_511 = or(_T_508, _T_509) node _T_512 = or(_T_511, _T_510) node _T_513 = and(_T_507, _T_512) node _T_514 = or(UInt<1>(0h0), _T_513) node _T_515 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_516 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_517 = and(_T_515, _T_516) node _T_518 = or(UInt<1>(0h0), _T_517) node _T_519 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_520 = cvt(_T_519) node _T_521 = and(_T_520, asSInt(UInt<13>(0h1000))) node _T_522 = asSInt(_T_521) node _T_523 = eq(_T_522, asSInt(UInt<1>(0h0))) node _T_524 = and(_T_518, _T_523) node _T_525 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_526 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_527 = and(_T_525, _T_526) node _T_528 = or(UInt<1>(0h0), _T_527) node _T_529 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_530 = cvt(_T_529) node _T_531 = and(_T_530, asSInt(UInt<14>(0h2000))) node _T_532 = asSInt(_T_531) node _T_533 = eq(_T_532, asSInt(UInt<1>(0h0))) node _T_534 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_535 = cvt(_T_534) node _T_536 = and(_T_535, asSInt(UInt<18>(0h2f000))) node _T_537 = asSInt(_T_536) node _T_538 = eq(_T_537, asSInt(UInt<1>(0h0))) node _T_539 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_540 = cvt(_T_539) node _T_541 = and(_T_540, asSInt(UInt<17>(0h10000))) node _T_542 = asSInt(_T_541) node _T_543 = eq(_T_542, asSInt(UInt<1>(0h0))) node _T_544 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_545 = cvt(_T_544) node _T_546 = and(_T_545, asSInt(UInt<13>(0h1000))) node _T_547 = asSInt(_T_546) node _T_548 = eq(_T_547, asSInt(UInt<1>(0h0))) node _T_549 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_550 = cvt(_T_549) node _T_551 = and(_T_550, asSInt(UInt<17>(0h10000))) node _T_552 = asSInt(_T_551) node _T_553 = eq(_T_552, asSInt(UInt<1>(0h0))) node _T_554 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_555 = cvt(_T_554) node _T_556 = and(_T_555, asSInt(UInt<27>(0h4000000))) node _T_557 = asSInt(_T_556) node _T_558 = eq(_T_557, asSInt(UInt<1>(0h0))) node _T_559 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_560 = cvt(_T_559) node _T_561 = and(_T_560, asSInt(UInt<13>(0h1000))) node _T_562 = asSInt(_T_561) node _T_563 = eq(_T_562, asSInt(UInt<1>(0h0))) node _T_564 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_565 = cvt(_T_564) node _T_566 = and(_T_565, asSInt(UInt<29>(0h10000000))) node _T_567 = asSInt(_T_566) node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0))) node _T_569 = or(_T_533, _T_538) node _T_570 = or(_T_569, _T_543) node _T_571 = or(_T_570, _T_548) node _T_572 = or(_T_571, _T_553) node _T_573 = or(_T_572, _T_558) node _T_574 = or(_T_573, _T_563) node _T_575 = or(_T_574, _T_568) node _T_576 = and(_T_528, _T_575) node _T_577 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_578 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_579 = cvt(_T_578) node _T_580 = and(_T_579, asSInt(UInt<17>(0h10000))) node _T_581 = asSInt(_T_580) node _T_582 = eq(_T_581, asSInt(UInt<1>(0h0))) node _T_583 = and(_T_577, _T_582) node _T_584 = or(UInt<1>(0h0), _T_524) node _T_585 = or(_T_584, _T_576) node _T_586 = or(_T_585, _T_583) node _T_587 = and(_T_514, _T_586) node _T_588 = asUInt(reset) node _T_589 = eq(_T_588, UInt<1>(0h0)) when _T_589 : node _T_590 = eq(_T_587, UInt<1>(0h0)) when _T_590 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_587, UInt<1>(0h1), "") : assert_26 node _T_591 = asUInt(reset) node _T_592 = eq(_T_591, UInt<1>(0h0)) when _T_592 : node _T_593 = eq(source_ok, UInt<1>(0h0)) when _T_593 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_594 = asUInt(reset) node _T_595 = eq(_T_594, UInt<1>(0h0)) when _T_595 : node _T_596 = eq(is_aligned, UInt<1>(0h0)) when _T_596 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_597 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_598 = asUInt(reset) node _T_599 = eq(_T_598, UInt<1>(0h0)) when _T_599 : node _T_600 = eq(_T_597, UInt<1>(0h0)) when _T_600 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_597, UInt<1>(0h1), "") : assert_29 node _T_601 = eq(io.in.a.bits.mask, mask) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_601, UInt<1>(0h1), "") : assert_30 node _T_605 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_605 : node _T_606 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_607 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_608 = and(_T_606, _T_607) node _T_609 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_610 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_611 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_612 = or(_T_609, _T_610) node _T_613 = or(_T_612, _T_611) node _T_614 = and(_T_608, _T_613) node _T_615 = or(UInt<1>(0h0), _T_614) node _T_616 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_617 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_618 = and(_T_616, _T_617) node _T_619 = or(UInt<1>(0h0), _T_618) node _T_620 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_621 = cvt(_T_620) node _T_622 = and(_T_621, asSInt(UInt<13>(0h1000))) node _T_623 = asSInt(_T_622) node _T_624 = eq(_T_623, asSInt(UInt<1>(0h0))) node _T_625 = and(_T_619, _T_624) node _T_626 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_627 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_628 = and(_T_626, _T_627) node _T_629 = or(UInt<1>(0h0), _T_628) node _T_630 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_631 = cvt(_T_630) node _T_632 = and(_T_631, asSInt(UInt<14>(0h2000))) node _T_633 = asSInt(_T_632) node _T_634 = eq(_T_633, asSInt(UInt<1>(0h0))) node _T_635 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_636 = cvt(_T_635) node _T_637 = and(_T_636, asSInt(UInt<18>(0h2f000))) node _T_638 = asSInt(_T_637) node _T_639 = eq(_T_638, asSInt(UInt<1>(0h0))) node _T_640 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_641 = cvt(_T_640) node _T_642 = and(_T_641, asSInt(UInt<17>(0h10000))) node _T_643 = asSInt(_T_642) node _T_644 = eq(_T_643, asSInt(UInt<1>(0h0))) node _T_645 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_646 = cvt(_T_645) node _T_647 = and(_T_646, asSInt(UInt<13>(0h1000))) node _T_648 = asSInt(_T_647) node _T_649 = eq(_T_648, asSInt(UInt<1>(0h0))) node _T_650 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_651 = cvt(_T_650) node _T_652 = and(_T_651, asSInt(UInt<17>(0h10000))) node _T_653 = asSInt(_T_652) node _T_654 = eq(_T_653, asSInt(UInt<1>(0h0))) node _T_655 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_656 = cvt(_T_655) node _T_657 = and(_T_656, asSInt(UInt<27>(0h4000000))) node _T_658 = asSInt(_T_657) node _T_659 = eq(_T_658, asSInt(UInt<1>(0h0))) node _T_660 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_661 = cvt(_T_660) node _T_662 = and(_T_661, asSInt(UInt<13>(0h1000))) node _T_663 = asSInt(_T_662) node _T_664 = eq(_T_663, asSInt(UInt<1>(0h0))) node _T_665 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_666 = cvt(_T_665) node _T_667 = and(_T_666, asSInt(UInt<29>(0h10000000))) node _T_668 = asSInt(_T_667) node _T_669 = eq(_T_668, asSInt(UInt<1>(0h0))) node _T_670 = or(_T_634, _T_639) node _T_671 = or(_T_670, _T_644) node _T_672 = or(_T_671, _T_649) node _T_673 = or(_T_672, _T_654) node _T_674 = or(_T_673, _T_659) node _T_675 = or(_T_674, _T_664) node _T_676 = or(_T_675, _T_669) node _T_677 = and(_T_629, _T_676) node _T_678 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_679 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_680 = cvt(_T_679) node _T_681 = and(_T_680, asSInt(UInt<17>(0h10000))) node _T_682 = asSInt(_T_681) node _T_683 = eq(_T_682, asSInt(UInt<1>(0h0))) node _T_684 = and(_T_678, _T_683) node _T_685 = or(UInt<1>(0h0), _T_625) node _T_686 = or(_T_685, _T_677) node _T_687 = or(_T_686, _T_684) node _T_688 = and(_T_615, _T_687) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_688, UInt<1>(0h1), "") : assert_31 node _T_692 = asUInt(reset) node _T_693 = eq(_T_692, UInt<1>(0h0)) when _T_693 : node _T_694 = eq(source_ok, UInt<1>(0h0)) when _T_694 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_695 = asUInt(reset) node _T_696 = eq(_T_695, UInt<1>(0h0)) when _T_696 : node _T_697 = eq(is_aligned, UInt<1>(0h0)) when _T_697 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_698 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_699 = asUInt(reset) node _T_700 = eq(_T_699, UInt<1>(0h0)) when _T_700 : node _T_701 = eq(_T_698, UInt<1>(0h0)) when _T_701 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_698, UInt<1>(0h1), "") : assert_34 node _T_702 = not(mask) node _T_703 = and(io.in.a.bits.mask, _T_702) node _T_704 = eq(_T_703, UInt<1>(0h0)) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_704, UInt<1>(0h1), "") : assert_35 node _T_708 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_708 : node _T_709 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_710 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_711 = and(_T_709, _T_710) node _T_712 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_713 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_714 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_715 = or(_T_712, _T_713) node _T_716 = or(_T_715, _T_714) node _T_717 = and(_T_711, _T_716) node _T_718 = or(UInt<1>(0h0), _T_717) node _T_719 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_720 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_721 = and(_T_719, _T_720) node _T_722 = or(UInt<1>(0h0), _T_721) node _T_723 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_724 = cvt(_T_723) node _T_725 = and(_T_724, asSInt(UInt<14>(0h2000))) node _T_726 = asSInt(_T_725) node _T_727 = eq(_T_726, asSInt(UInt<1>(0h0))) node _T_728 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_729 = cvt(_T_728) node _T_730 = and(_T_729, asSInt(UInt<13>(0h1000))) node _T_731 = asSInt(_T_730) node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0))) node _T_733 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_734 = cvt(_T_733) node _T_735 = and(_T_734, asSInt(UInt<18>(0h2f000))) node _T_736 = asSInt(_T_735) node _T_737 = eq(_T_736, asSInt(UInt<1>(0h0))) node _T_738 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_739 = cvt(_T_738) node _T_740 = and(_T_739, asSInt(UInt<17>(0h10000))) node _T_741 = asSInt(_T_740) node _T_742 = eq(_T_741, asSInt(UInt<1>(0h0))) node _T_743 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_744 = cvt(_T_743) node _T_745 = and(_T_744, asSInt(UInt<13>(0h1000))) node _T_746 = asSInt(_T_745) node _T_747 = eq(_T_746, asSInt(UInt<1>(0h0))) node _T_748 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_749 = cvt(_T_748) node _T_750 = and(_T_749, asSInt(UInt<17>(0h10000))) node _T_751 = asSInt(_T_750) node _T_752 = eq(_T_751, asSInt(UInt<1>(0h0))) node _T_753 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_754 = cvt(_T_753) node _T_755 = and(_T_754, asSInt(UInt<27>(0h4000000))) node _T_756 = asSInt(_T_755) node _T_757 = eq(_T_756, asSInt(UInt<1>(0h0))) node _T_758 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_759 = cvt(_T_758) node _T_760 = and(_T_759, asSInt(UInt<13>(0h1000))) node _T_761 = asSInt(_T_760) node _T_762 = eq(_T_761, asSInt(UInt<1>(0h0))) node _T_763 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_764 = cvt(_T_763) node _T_765 = and(_T_764, asSInt(UInt<29>(0h10000000))) node _T_766 = asSInt(_T_765) node _T_767 = eq(_T_766, asSInt(UInt<1>(0h0))) node _T_768 = or(_T_727, _T_732) node _T_769 = or(_T_768, _T_737) node _T_770 = or(_T_769, _T_742) node _T_771 = or(_T_770, _T_747) node _T_772 = or(_T_771, _T_752) node _T_773 = or(_T_772, _T_757) node _T_774 = or(_T_773, _T_762) node _T_775 = or(_T_774, _T_767) node _T_776 = and(_T_722, _T_775) node _T_777 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_778 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_779 = cvt(_T_778) node _T_780 = and(_T_779, asSInt(UInt<17>(0h10000))) node _T_781 = asSInt(_T_780) node _T_782 = eq(_T_781, asSInt(UInt<1>(0h0))) node _T_783 = and(_T_777, _T_782) node _T_784 = or(UInt<1>(0h0), _T_776) node _T_785 = or(_T_784, _T_783) node _T_786 = and(_T_718, _T_785) node _T_787 = asUInt(reset) node _T_788 = eq(_T_787, UInt<1>(0h0)) when _T_788 : node _T_789 = eq(_T_786, UInt<1>(0h0)) when _T_789 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_786, UInt<1>(0h1), "") : assert_36 node _T_790 = asUInt(reset) node _T_791 = eq(_T_790, UInt<1>(0h0)) when _T_791 : node _T_792 = eq(source_ok, UInt<1>(0h0)) when _T_792 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_793 = asUInt(reset) node _T_794 = eq(_T_793, UInt<1>(0h0)) when _T_794 : node _T_795 = eq(is_aligned, UInt<1>(0h0)) when _T_795 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_796 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_797 = asUInt(reset) node _T_798 = eq(_T_797, UInt<1>(0h0)) when _T_798 : node _T_799 = eq(_T_796, UInt<1>(0h0)) when _T_799 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_796, UInt<1>(0h1), "") : assert_39 node _T_800 = eq(io.in.a.bits.mask, mask) node _T_801 = asUInt(reset) node _T_802 = eq(_T_801, UInt<1>(0h0)) when _T_802 : node _T_803 = eq(_T_800, UInt<1>(0h0)) when _T_803 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_800, UInt<1>(0h1), "") : assert_40 node _T_804 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_804 : node _T_805 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_806 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_807 = and(_T_805, _T_806) node _T_808 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_809 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_810 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_811 = or(_T_808, _T_809) node _T_812 = or(_T_811, _T_810) node _T_813 = and(_T_807, _T_812) node _T_814 = or(UInt<1>(0h0), _T_813) node _T_815 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_816 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_817 = and(_T_815, _T_816) node _T_818 = or(UInt<1>(0h0), _T_817) node _T_819 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_820 = cvt(_T_819) node _T_821 = and(_T_820, asSInt(UInt<14>(0h2000))) node _T_822 = asSInt(_T_821) node _T_823 = eq(_T_822, asSInt(UInt<1>(0h0))) node _T_824 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_825 = cvt(_T_824) node _T_826 = and(_T_825, asSInt(UInt<13>(0h1000))) node _T_827 = asSInt(_T_826) node _T_828 = eq(_T_827, asSInt(UInt<1>(0h0))) node _T_829 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_830 = cvt(_T_829) node _T_831 = and(_T_830, asSInt(UInt<18>(0h2f000))) node _T_832 = asSInt(_T_831) node _T_833 = eq(_T_832, asSInt(UInt<1>(0h0))) node _T_834 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_835 = cvt(_T_834) node _T_836 = and(_T_835, asSInt(UInt<17>(0h10000))) node _T_837 = asSInt(_T_836) node _T_838 = eq(_T_837, asSInt(UInt<1>(0h0))) node _T_839 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_840 = cvt(_T_839) node _T_841 = and(_T_840, asSInt(UInt<13>(0h1000))) node _T_842 = asSInt(_T_841) node _T_843 = eq(_T_842, asSInt(UInt<1>(0h0))) node _T_844 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_845 = cvt(_T_844) node _T_846 = and(_T_845, asSInt(UInt<17>(0h10000))) node _T_847 = asSInt(_T_846) node _T_848 = eq(_T_847, asSInt(UInt<1>(0h0))) node _T_849 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_850 = cvt(_T_849) node _T_851 = and(_T_850, asSInt(UInt<27>(0h4000000))) node _T_852 = asSInt(_T_851) node _T_853 = eq(_T_852, asSInt(UInt<1>(0h0))) node _T_854 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_855 = cvt(_T_854) node _T_856 = and(_T_855, asSInt(UInt<13>(0h1000))) node _T_857 = asSInt(_T_856) node _T_858 = eq(_T_857, asSInt(UInt<1>(0h0))) node _T_859 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_860 = cvt(_T_859) node _T_861 = and(_T_860, asSInt(UInt<29>(0h10000000))) node _T_862 = asSInt(_T_861) node _T_863 = eq(_T_862, asSInt(UInt<1>(0h0))) node _T_864 = or(_T_823, _T_828) node _T_865 = or(_T_864, _T_833) node _T_866 = or(_T_865, _T_838) node _T_867 = or(_T_866, _T_843) node _T_868 = or(_T_867, _T_848) node _T_869 = or(_T_868, _T_853) node _T_870 = or(_T_869, _T_858) node _T_871 = or(_T_870, _T_863) node _T_872 = and(_T_818, _T_871) node _T_873 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_874 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<17>(0h10000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = and(_T_873, _T_878) node _T_880 = or(UInt<1>(0h0), _T_872) node _T_881 = or(_T_880, _T_879) node _T_882 = and(_T_814, _T_881) node _T_883 = asUInt(reset) node _T_884 = eq(_T_883, UInt<1>(0h0)) when _T_884 : node _T_885 = eq(_T_882, UInt<1>(0h0)) when _T_885 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_882, UInt<1>(0h1), "") : assert_41 node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(source_ok, UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_889 = asUInt(reset) node _T_890 = eq(_T_889, UInt<1>(0h0)) when _T_890 : node _T_891 = eq(is_aligned, UInt<1>(0h0)) when _T_891 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_892 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_893 = asUInt(reset) node _T_894 = eq(_T_893, UInt<1>(0h0)) when _T_894 : node _T_895 = eq(_T_892, UInt<1>(0h0)) when _T_895 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_892, UInt<1>(0h1), "") : assert_44 node _T_896 = eq(io.in.a.bits.mask, mask) node _T_897 = asUInt(reset) node _T_898 = eq(_T_897, UInt<1>(0h0)) when _T_898 : node _T_899 = eq(_T_896, UInt<1>(0h0)) when _T_899 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_896, UInt<1>(0h1), "") : assert_45 node _T_900 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_900 : node _T_901 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_902 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_903 = and(_T_901, _T_902) node _T_904 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_905 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_906 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_907 = or(_T_904, _T_905) node _T_908 = or(_T_907, _T_906) node _T_909 = and(_T_903, _T_908) node _T_910 = or(UInt<1>(0h0), _T_909) node _T_911 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_912 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_913 = and(_T_911, _T_912) node _T_914 = or(UInt<1>(0h0), _T_913) node _T_915 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_916 = cvt(_T_915) node _T_917 = and(_T_916, asSInt(UInt<13>(0h1000))) node _T_918 = asSInt(_T_917) node _T_919 = eq(_T_918, asSInt(UInt<1>(0h0))) node _T_920 = and(_T_914, _T_919) node _T_921 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_922 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_923 = cvt(_T_922) node _T_924 = and(_T_923, asSInt(UInt<14>(0h2000))) node _T_925 = asSInt(_T_924) node _T_926 = eq(_T_925, asSInt(UInt<1>(0h0))) node _T_927 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_928 = cvt(_T_927) node _T_929 = and(_T_928, asSInt(UInt<17>(0h10000))) node _T_930 = asSInt(_T_929) node _T_931 = eq(_T_930, asSInt(UInt<1>(0h0))) node _T_932 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_933 = cvt(_T_932) node _T_934 = and(_T_933, asSInt(UInt<18>(0h2f000))) node _T_935 = asSInt(_T_934) node _T_936 = eq(_T_935, asSInt(UInt<1>(0h0))) node _T_937 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_938 = cvt(_T_937) node _T_939 = and(_T_938, asSInt(UInt<17>(0h10000))) node _T_940 = asSInt(_T_939) node _T_941 = eq(_T_940, asSInt(UInt<1>(0h0))) node _T_942 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_943 = cvt(_T_942) node _T_944 = and(_T_943, asSInt(UInt<13>(0h1000))) node _T_945 = asSInt(_T_944) node _T_946 = eq(_T_945, asSInt(UInt<1>(0h0))) node _T_947 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_948 = cvt(_T_947) node _T_949 = and(_T_948, asSInt(UInt<27>(0h4000000))) node _T_950 = asSInt(_T_949) node _T_951 = eq(_T_950, asSInt(UInt<1>(0h0))) node _T_952 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_953 = cvt(_T_952) node _T_954 = and(_T_953, asSInt(UInt<13>(0h1000))) node _T_955 = asSInt(_T_954) node _T_956 = eq(_T_955, asSInt(UInt<1>(0h0))) node _T_957 = or(_T_926, _T_931) node _T_958 = or(_T_957, _T_936) node _T_959 = or(_T_958, _T_941) node _T_960 = or(_T_959, _T_946) node _T_961 = or(_T_960, _T_951) node _T_962 = or(_T_961, _T_956) node _T_963 = and(_T_921, _T_962) node _T_964 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_965 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_966 = and(_T_964, _T_965) node _T_967 = or(UInt<1>(0h0), _T_966) node _T_968 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_969 = cvt(_T_968) node _T_970 = and(_T_969, asSInt(UInt<17>(0h10000))) node _T_971 = asSInt(_T_970) node _T_972 = eq(_T_971, asSInt(UInt<1>(0h0))) node _T_973 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_974 = cvt(_T_973) node _T_975 = and(_T_974, asSInt(UInt<29>(0h10000000))) node _T_976 = asSInt(_T_975) node _T_977 = eq(_T_976, asSInt(UInt<1>(0h0))) node _T_978 = or(_T_972, _T_977) node _T_979 = and(_T_967, _T_978) node _T_980 = or(UInt<1>(0h0), _T_920) node _T_981 = or(_T_980, _T_963) node _T_982 = or(_T_981, _T_979) node _T_983 = and(_T_910, _T_982) node _T_984 = asUInt(reset) node _T_985 = eq(_T_984, UInt<1>(0h0)) when _T_985 : node _T_986 = eq(_T_983, UInt<1>(0h0)) when _T_986 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_983, UInt<1>(0h1), "") : assert_46 node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(source_ok, UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(is_aligned, UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_993 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_994 = asUInt(reset) node _T_995 = eq(_T_994, UInt<1>(0h0)) when _T_995 : node _T_996 = eq(_T_993, UInt<1>(0h0)) when _T_996 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_993, UInt<1>(0h1), "") : assert_49 node _T_997 = eq(io.in.a.bits.mask, mask) node _T_998 = asUInt(reset) node _T_999 = eq(_T_998, UInt<1>(0h0)) when _T_999 : node _T_1000 = eq(_T_997, UInt<1>(0h0)) when _T_1000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_997, UInt<1>(0h1), "") : assert_50 node _T_1001 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1002 = asUInt(reset) node _T_1003 = eq(_T_1002, UInt<1>(0h0)) when _T_1003 : node _T_1004 = eq(_T_1001, UInt<1>(0h0)) when _T_1004 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1001, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1005 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1006 = asUInt(reset) node _T_1007 = eq(_T_1006, UInt<1>(0h0)) when _T_1007 : node _T_1008 = eq(_T_1005, UInt<1>(0h0)) when _T_1008 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1005, UInt<1>(0h1), "") : assert_52 node _source_ok_T_4 = eq(io.in.d.bits.source, UInt<1>(0h0)) node _source_ok_T_5 = eq(io.in.d.bits.source, UInt<1>(0h1)) node _source_ok_T_6 = eq(io.in.d.bits.source, UInt<2>(0h2)) wire _source_ok_WIRE_1 : UInt<1>[3] connect _source_ok_WIRE_1[0], _source_ok_T_4 connect _source_ok_WIRE_1[1], _source_ok_T_5 connect _source_ok_WIRE_1[2], _source_ok_T_6 node _source_ok_T_7 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node source_ok_1 = or(_source_ok_T_7, _source_ok_WIRE_1[2]) node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_1009 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1009 : node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(source_ok_1, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1013 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_54 node _T_1017 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_55 node _T_1021 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1022 = asUInt(reset) node _T_1023 = eq(_T_1022, UInt<1>(0h0)) when _T_1023 : node _T_1024 = eq(_T_1021, UInt<1>(0h0)) when _T_1024 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1021, UInt<1>(0h1), "") : assert_56 node _T_1025 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1026 = asUInt(reset) node _T_1027 = eq(_T_1026, UInt<1>(0h0)) when _T_1027 : node _T_1028 = eq(_T_1025, UInt<1>(0h0)) when _T_1028 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1025, UInt<1>(0h1), "") : assert_57 node _T_1029 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1029 : node _T_1030 = asUInt(reset) node _T_1031 = eq(_T_1030, UInt<1>(0h0)) when _T_1031 : node _T_1032 = eq(source_ok_1, UInt<1>(0h0)) when _T_1032 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1033 = asUInt(reset) node _T_1034 = eq(_T_1033, UInt<1>(0h0)) when _T_1034 : node _T_1035 = eq(sink_ok, UInt<1>(0h0)) when _T_1035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1036 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1037 = asUInt(reset) node _T_1038 = eq(_T_1037, UInt<1>(0h0)) when _T_1038 : node _T_1039 = eq(_T_1036, UInt<1>(0h0)) when _T_1039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1036, UInt<1>(0h1), "") : assert_60 node _T_1040 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1041 = asUInt(reset) node _T_1042 = eq(_T_1041, UInt<1>(0h0)) when _T_1042 : node _T_1043 = eq(_T_1040, UInt<1>(0h0)) when _T_1043 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1040, UInt<1>(0h1), "") : assert_61 node _T_1044 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1045 = asUInt(reset) node _T_1046 = eq(_T_1045, UInt<1>(0h0)) when _T_1046 : node _T_1047 = eq(_T_1044, UInt<1>(0h0)) when _T_1047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1044, UInt<1>(0h1), "") : assert_62 node _T_1048 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1049 = asUInt(reset) node _T_1050 = eq(_T_1049, UInt<1>(0h0)) when _T_1050 : node _T_1051 = eq(_T_1048, UInt<1>(0h0)) when _T_1051 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1048, UInt<1>(0h1), "") : assert_63 node _T_1052 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1053 = or(UInt<1>(0h1), _T_1052) node _T_1054 = asUInt(reset) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) when _T_1055 : node _T_1056 = eq(_T_1053, UInt<1>(0h0)) when _T_1056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1053, UInt<1>(0h1), "") : assert_64 node _T_1057 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1057 : node _T_1058 = asUInt(reset) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) when _T_1059 : node _T_1060 = eq(source_ok_1, UInt<1>(0h0)) when _T_1060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1061 = asUInt(reset) node _T_1062 = eq(_T_1061, UInt<1>(0h0)) when _T_1062 : node _T_1063 = eq(sink_ok, UInt<1>(0h0)) when _T_1063 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1064 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1065 = asUInt(reset) node _T_1066 = eq(_T_1065, UInt<1>(0h0)) when _T_1066 : node _T_1067 = eq(_T_1064, UInt<1>(0h0)) when _T_1067 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1064, UInt<1>(0h1), "") : assert_67 node _T_1068 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1069 = asUInt(reset) node _T_1070 = eq(_T_1069, UInt<1>(0h0)) when _T_1070 : node _T_1071 = eq(_T_1068, UInt<1>(0h0)) when _T_1071 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1068, UInt<1>(0h1), "") : assert_68 node _T_1072 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1073 = asUInt(reset) node _T_1074 = eq(_T_1073, UInt<1>(0h0)) when _T_1074 : node _T_1075 = eq(_T_1072, UInt<1>(0h0)) when _T_1075 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1072, UInt<1>(0h1), "") : assert_69 node _T_1076 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1077 = or(_T_1076, io.in.d.bits.corrupt) node _T_1078 = asUInt(reset) node _T_1079 = eq(_T_1078, UInt<1>(0h0)) when _T_1079 : node _T_1080 = eq(_T_1077, UInt<1>(0h0)) when _T_1080 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1077, UInt<1>(0h1), "") : assert_70 node _T_1081 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1082 = or(UInt<1>(0h1), _T_1081) node _T_1083 = asUInt(reset) node _T_1084 = eq(_T_1083, UInt<1>(0h0)) when _T_1084 : node _T_1085 = eq(_T_1082, UInt<1>(0h0)) when _T_1085 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1082, UInt<1>(0h1), "") : assert_71 node _T_1086 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1086 : node _T_1087 = asUInt(reset) node _T_1088 = eq(_T_1087, UInt<1>(0h0)) when _T_1088 : node _T_1089 = eq(source_ok_1, UInt<1>(0h0)) when _T_1089 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1090 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1091 = asUInt(reset) node _T_1092 = eq(_T_1091, UInt<1>(0h0)) when _T_1092 : node _T_1093 = eq(_T_1090, UInt<1>(0h0)) when _T_1093 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1090, UInt<1>(0h1), "") : assert_73 node _T_1094 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_74 node _T_1098 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1099 = or(UInt<1>(0h1), _T_1098) node _T_1100 = asUInt(reset) node _T_1101 = eq(_T_1100, UInt<1>(0h0)) when _T_1101 : node _T_1102 = eq(_T_1099, UInt<1>(0h0)) when _T_1102 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1099, UInt<1>(0h1), "") : assert_75 node _T_1103 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1103 : node _T_1104 = asUInt(reset) node _T_1105 = eq(_T_1104, UInt<1>(0h0)) when _T_1105 : node _T_1106 = eq(source_ok_1, UInt<1>(0h0)) when _T_1106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1107 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1108 = asUInt(reset) node _T_1109 = eq(_T_1108, UInt<1>(0h0)) when _T_1109 : node _T_1110 = eq(_T_1107, UInt<1>(0h0)) when _T_1110 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1107, UInt<1>(0h1), "") : assert_77 node _T_1111 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1112 = or(_T_1111, io.in.d.bits.corrupt) node _T_1113 = asUInt(reset) node _T_1114 = eq(_T_1113, UInt<1>(0h0)) when _T_1114 : node _T_1115 = eq(_T_1112, UInt<1>(0h0)) when _T_1115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1112, UInt<1>(0h1), "") : assert_78 node _T_1116 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1117 = or(UInt<1>(0h1), _T_1116) node _T_1118 = asUInt(reset) node _T_1119 = eq(_T_1118, UInt<1>(0h0)) when _T_1119 : node _T_1120 = eq(_T_1117, UInt<1>(0h0)) when _T_1120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1117, UInt<1>(0h1), "") : assert_79 node _T_1121 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1121 : node _T_1122 = asUInt(reset) node _T_1123 = eq(_T_1122, UInt<1>(0h0)) when _T_1123 : node _T_1124 = eq(source_ok_1, UInt<1>(0h0)) when _T_1124 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1125 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1126 = asUInt(reset) node _T_1127 = eq(_T_1126, UInt<1>(0h0)) when _T_1127 : node _T_1128 = eq(_T_1125, UInt<1>(0h0)) when _T_1128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1125, UInt<1>(0h1), "") : assert_81 node _T_1129 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1130 = asUInt(reset) node _T_1131 = eq(_T_1130, UInt<1>(0h0)) when _T_1131 : node _T_1132 = eq(_T_1129, UInt<1>(0h0)) when _T_1132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1129, UInt<1>(0h1), "") : assert_82 node _T_1133 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1134 = or(UInt<1>(0h1), _T_1133) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_1138 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_1139 = asUInt(reset) node _T_1140 = eq(_T_1139, UInt<1>(0h0)) when _T_1140 : node _T_1141 = eq(_T_1138, UInt<1>(0h0)) when _T_1141 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1138, UInt<1>(0h1), "") : assert_84 node _T_1142 = eq(io.in.b.bits.source, UInt<1>(0h0)) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) node _T_1144 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1145 = cvt(_T_1144) node _T_1146 = and(_T_1145, asSInt(UInt<1>(0h0))) node _T_1147 = asSInt(_T_1146) node _T_1148 = eq(_T_1147, asSInt(UInt<1>(0h0))) node _T_1149 = or(_T_1143, _T_1148) node _T_1150 = eq(io.in.b.bits.source, UInt<1>(0h1)) node _T_1151 = eq(_T_1150, UInt<1>(0h0)) node _T_1152 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1153 = cvt(_T_1152) node _T_1154 = and(_T_1153, asSInt(UInt<1>(0h0))) node _T_1155 = asSInt(_T_1154) node _T_1156 = eq(_T_1155, asSInt(UInt<1>(0h0))) node _T_1157 = or(_T_1151, _T_1156) node _T_1158 = eq(io.in.b.bits.source, UInt<2>(0h2)) node _T_1159 = eq(_T_1158, UInt<1>(0h0)) node _T_1160 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1161 = cvt(_T_1160) node _T_1162 = and(_T_1161, asSInt(UInt<1>(0h0))) node _T_1163 = asSInt(_T_1162) node _T_1164 = eq(_T_1163, asSInt(UInt<1>(0h0))) node _T_1165 = or(_T_1159, _T_1164) node _T_1166 = and(_T_1149, _T_1157) node _T_1167 = and(_T_1166, _T_1165) node _T_1168 = asUInt(reset) node _T_1169 = eq(_T_1168, UInt<1>(0h0)) when _T_1169 : node _T_1170 = eq(_T_1167, UInt<1>(0h0)) when _T_1170 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1167, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<1>(0h0)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<13>(0h1000))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<13>(0h1000)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<13>(0h1000))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) node _address_ok_T_10 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<13>(0h1000))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<17>(0h10000))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) node _address_ok_T_20 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _address_ok_T_21 = cvt(_address_ok_T_20) node _address_ok_T_22 = and(_address_ok_T_21, asSInt(UInt<13>(0h1000))) node _address_ok_T_23 = asSInt(_address_ok_T_22) node _address_ok_T_24 = eq(_address_ok_T_23, asSInt(UInt<1>(0h0))) node _address_ok_T_25 = xor(io.in.b.bits.address, UInt<21>(0h110000)) node _address_ok_T_26 = cvt(_address_ok_T_25) node _address_ok_T_27 = and(_address_ok_T_26, asSInt(UInt<13>(0h1000))) node _address_ok_T_28 = asSInt(_address_ok_T_27) node _address_ok_T_29 = eq(_address_ok_T_28, asSInt(UInt<1>(0h0))) node _address_ok_T_30 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _address_ok_T_31 = cvt(_address_ok_T_30) node _address_ok_T_32 = and(_address_ok_T_31, asSInt(UInt<17>(0h10000))) node _address_ok_T_33 = asSInt(_address_ok_T_32) node _address_ok_T_34 = eq(_address_ok_T_33, asSInt(UInt<1>(0h0))) node _address_ok_T_35 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _address_ok_T_36 = cvt(_address_ok_T_35) node _address_ok_T_37 = and(_address_ok_T_36, asSInt(UInt<13>(0h1000))) node _address_ok_T_38 = asSInt(_address_ok_T_37) node _address_ok_T_39 = eq(_address_ok_T_38, asSInt(UInt<1>(0h0))) node _address_ok_T_40 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _address_ok_T_41 = cvt(_address_ok_T_40) node _address_ok_T_42 = and(_address_ok_T_41, asSInt(UInt<17>(0h10000))) node _address_ok_T_43 = asSInt(_address_ok_T_42) node _address_ok_T_44 = eq(_address_ok_T_43, asSInt(UInt<1>(0h0))) node _address_ok_T_45 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _address_ok_T_46 = cvt(_address_ok_T_45) node _address_ok_T_47 = and(_address_ok_T_46, asSInt(UInt<27>(0h4000000))) node _address_ok_T_48 = asSInt(_address_ok_T_47) node _address_ok_T_49 = eq(_address_ok_T_48, asSInt(UInt<1>(0h0))) node _address_ok_T_50 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _address_ok_T_51 = cvt(_address_ok_T_50) node _address_ok_T_52 = and(_address_ok_T_51, asSInt(UInt<13>(0h1000))) node _address_ok_T_53 = asSInt(_address_ok_T_52) node _address_ok_T_54 = eq(_address_ok_T_53, asSInt(UInt<1>(0h0))) node _address_ok_T_55 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _address_ok_T_56 = cvt(_address_ok_T_55) node _address_ok_T_57 = and(_address_ok_T_56, asSInt(UInt<29>(0h10000000))) node _address_ok_T_58 = asSInt(_address_ok_T_57) node _address_ok_T_59 = eq(_address_ok_T_58, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[12] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 connect _address_ok_WIRE[2], _address_ok_T_14 connect _address_ok_WIRE[3], _address_ok_T_19 connect _address_ok_WIRE[4], _address_ok_T_24 connect _address_ok_WIRE[5], _address_ok_T_29 connect _address_ok_WIRE[6], _address_ok_T_34 connect _address_ok_WIRE[7], _address_ok_T_39 connect _address_ok_WIRE[8], _address_ok_T_44 connect _address_ok_WIRE[9], _address_ok_T_49 connect _address_ok_WIRE[10], _address_ok_T_54 connect _address_ok_WIRE[11], _address_ok_T_59 node _address_ok_T_60 = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _address_ok_T_61 = or(_address_ok_T_60, _address_ok_WIRE[2]) node _address_ok_T_62 = or(_address_ok_T_61, _address_ok_WIRE[3]) node _address_ok_T_63 = or(_address_ok_T_62, _address_ok_WIRE[4]) node _address_ok_T_64 = or(_address_ok_T_63, _address_ok_WIRE[5]) node _address_ok_T_65 = or(_address_ok_T_64, _address_ok_WIRE[6]) node _address_ok_T_66 = or(_address_ok_T_65, _address_ok_WIRE[7]) node _address_ok_T_67 = or(_address_ok_T_66, _address_ok_WIRE[8]) node _address_ok_T_68 = or(_address_ok_T_67, _address_ok_WIRE[9]) node _address_ok_T_69 = or(_address_ok_T_68, _address_ok_WIRE[10]) node address_ok = or(_address_ok_T_69, _address_ok_WIRE[11]) node _is_aligned_mask_T_2 = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 11, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3)) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_8 = and(mask_size_1, mask_eq_8) node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_9 = and(mask_size_1, mask_eq_9) node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_10 = and(mask_size_1, mask_eq_10) node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_11 = and(mask_size_1, mask_eq_11) node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_12 = and(mask_size_1, mask_eq_12) node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_13 = and(mask_size_1, mask_eq_13) node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_14 = and(mask_size_1, mask_eq_14) node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_15 = and(mask_size_1, mask_eq_15) node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15) node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8) node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_T = eq(io.in.b.bits.source, UInt<1>(0h0)) node _legal_source_T_1 = eq(io.in.b.bits.source, UInt<1>(0h1)) node _legal_source_T_2 = eq(io.in.b.bits.source, UInt<2>(0h2)) wire _legal_source_WIRE : UInt<1>[3] connect _legal_source_WIRE[0], _legal_source_T connect _legal_source_WIRE[1], _legal_source_T_1 connect _legal_source_WIRE[2], _legal_source_T_2 node _legal_source_T_3 = mux(_legal_source_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _legal_source_T_4 = mux(_legal_source_WIRE[1], UInt<1>(0h1), UInt<1>(0h0)) node _legal_source_T_5 = mux(_legal_source_WIRE[2], UInt<2>(0h2), UInt<1>(0h0)) node _legal_source_T_6 = or(_legal_source_T_3, _legal_source_T_4) node _legal_source_T_7 = or(_legal_source_T_6, _legal_source_T_5) wire _legal_source_WIRE_1 : UInt<2> connect _legal_source_WIRE_1, _legal_source_T_7 node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source) node _T_1171 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_1171 : node _T_1172 = eq(io.in.b.bits.source, UInt<1>(0h0)) node _T_1173 = eq(io.in.b.bits.source, UInt<1>(0h1)) node _T_1174 = eq(io.in.b.bits.source, UInt<2>(0h2)) wire _WIRE_4 : UInt<1>[3] connect _WIRE_4[0], _T_1172 connect _WIRE_4[1], _T_1173 connect _WIRE_4[2], _T_1174 node _T_1175 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1176 = mux(_WIRE_4[0], _T_1175, UInt<1>(0h0)) node _T_1177 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1178 = mux(_WIRE_4[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1179 = or(_T_1176, _T_1177) node _T_1180 = or(_T_1179, _T_1178) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_1180 node _T_1181 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1182 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1183 = and(_T_1181, _T_1182) node _T_1184 = or(UInt<1>(0h0), _T_1183) node _T_1185 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1186 = cvt(_T_1185) node _T_1187 = and(_T_1186, asSInt(UInt<14>(0h2000))) node _T_1188 = asSInt(_T_1187) node _T_1189 = eq(_T_1188, asSInt(UInt<1>(0h0))) node _T_1190 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1191 = cvt(_T_1190) node _T_1192 = and(_T_1191, asSInt(UInt<13>(0h1000))) node _T_1193 = asSInt(_T_1192) node _T_1194 = eq(_T_1193, asSInt(UInt<1>(0h0))) node _T_1195 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1196 = cvt(_T_1195) node _T_1197 = and(_T_1196, asSInt(UInt<17>(0h10000))) node _T_1198 = asSInt(_T_1197) node _T_1199 = eq(_T_1198, asSInt(UInt<1>(0h0))) node _T_1200 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1201 = cvt(_T_1200) node _T_1202 = and(_T_1201, asSInt(UInt<18>(0h2f000))) node _T_1203 = asSInt(_T_1202) node _T_1204 = eq(_T_1203, asSInt(UInt<1>(0h0))) node _T_1205 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1206 = cvt(_T_1205) node _T_1207 = and(_T_1206, asSInt(UInt<17>(0h10000))) node _T_1208 = asSInt(_T_1207) node _T_1209 = eq(_T_1208, asSInt(UInt<1>(0h0))) node _T_1210 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1211 = cvt(_T_1210) node _T_1212 = and(_T_1211, asSInt(UInt<13>(0h1000))) node _T_1213 = asSInt(_T_1212) node _T_1214 = eq(_T_1213, asSInt(UInt<1>(0h0))) node _T_1215 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1216 = cvt(_T_1215) node _T_1217 = and(_T_1216, asSInt(UInt<17>(0h10000))) node _T_1218 = asSInt(_T_1217) node _T_1219 = eq(_T_1218, asSInt(UInt<1>(0h0))) node _T_1220 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1221 = cvt(_T_1220) node _T_1222 = and(_T_1221, asSInt(UInt<27>(0h4000000))) node _T_1223 = asSInt(_T_1222) node _T_1224 = eq(_T_1223, asSInt(UInt<1>(0h0))) node _T_1225 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1226 = cvt(_T_1225) node _T_1227 = and(_T_1226, asSInt(UInt<13>(0h1000))) node _T_1228 = asSInt(_T_1227) node _T_1229 = eq(_T_1228, asSInt(UInt<1>(0h0))) node _T_1230 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1231 = cvt(_T_1230) node _T_1232 = and(_T_1231, asSInt(UInt<29>(0h10000000))) node _T_1233 = asSInt(_T_1232) node _T_1234 = eq(_T_1233, asSInt(UInt<1>(0h0))) node _T_1235 = or(_T_1189, _T_1194) node _T_1236 = or(_T_1235, _T_1199) node _T_1237 = or(_T_1236, _T_1204) node _T_1238 = or(_T_1237, _T_1209) node _T_1239 = or(_T_1238, _T_1214) node _T_1240 = or(_T_1239, _T_1219) node _T_1241 = or(_T_1240, _T_1224) node _T_1242 = or(_T_1241, _T_1229) node _T_1243 = or(_T_1242, _T_1234) node _T_1244 = and(_T_1184, _T_1243) node _T_1245 = or(UInt<1>(0h0), _T_1244) node _T_1246 = and(_WIRE_5, _T_1245) node _T_1247 = asUInt(reset) node _T_1248 = eq(_T_1247, UInt<1>(0h0)) when _T_1248 : node _T_1249 = eq(_T_1246, UInt<1>(0h0)) when _T_1249 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_1246, UInt<1>(0h1), "") : assert_86 node _T_1250 = asUInt(reset) node _T_1251 = eq(_T_1250, UInt<1>(0h0)) when _T_1251 : node _T_1252 = eq(address_ok, UInt<1>(0h0)) when _T_1252 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_1253 = asUInt(reset) node _T_1254 = eq(_T_1253, UInt<1>(0h0)) when _T_1254 : node _T_1255 = eq(legal_source, UInt<1>(0h0)) when _T_1255 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_1256 = asUInt(reset) node _T_1257 = eq(_T_1256, UInt<1>(0h0)) when _T_1257 : node _T_1258 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_1259 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_1260 = asUInt(reset) node _T_1261 = eq(_T_1260, UInt<1>(0h0)) when _T_1261 : node _T_1262 = eq(_T_1259, UInt<1>(0h0)) when _T_1262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_1259, UInt<1>(0h1), "") : assert_90 node _T_1263 = eq(io.in.b.bits.mask, mask_1) node _T_1264 = asUInt(reset) node _T_1265 = eq(_T_1264, UInt<1>(0h0)) when _T_1265 : node _T_1266 = eq(_T_1263, UInt<1>(0h0)) when _T_1266 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_1263, UInt<1>(0h1), "") : assert_91 node _T_1267 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1268 = asUInt(reset) node _T_1269 = eq(_T_1268, UInt<1>(0h0)) when _T_1269 : node _T_1270 = eq(_T_1267, UInt<1>(0h0)) when _T_1270 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1267, UInt<1>(0h1), "") : assert_92 node _T_1271 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_1271 : node _T_1272 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1273 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1274 = and(_T_1272, _T_1273) node _T_1275 = or(UInt<1>(0h0), _T_1274) node _T_1276 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1277 = cvt(_T_1276) node _T_1278 = and(_T_1277, asSInt(UInt<14>(0h2000))) node _T_1279 = asSInt(_T_1278) node _T_1280 = eq(_T_1279, asSInt(UInt<1>(0h0))) node _T_1281 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1282 = cvt(_T_1281) node _T_1283 = and(_T_1282, asSInt(UInt<13>(0h1000))) node _T_1284 = asSInt(_T_1283) node _T_1285 = eq(_T_1284, asSInt(UInt<1>(0h0))) node _T_1286 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1287 = cvt(_T_1286) node _T_1288 = and(_T_1287, asSInt(UInt<17>(0h10000))) node _T_1289 = asSInt(_T_1288) node _T_1290 = eq(_T_1289, asSInt(UInt<1>(0h0))) node _T_1291 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1292 = cvt(_T_1291) node _T_1293 = and(_T_1292, asSInt(UInt<18>(0h2f000))) node _T_1294 = asSInt(_T_1293) node _T_1295 = eq(_T_1294, asSInt(UInt<1>(0h0))) node _T_1296 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1297 = cvt(_T_1296) node _T_1298 = and(_T_1297, asSInt(UInt<17>(0h10000))) node _T_1299 = asSInt(_T_1298) node _T_1300 = eq(_T_1299, asSInt(UInt<1>(0h0))) node _T_1301 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1302 = cvt(_T_1301) node _T_1303 = and(_T_1302, asSInt(UInt<13>(0h1000))) node _T_1304 = asSInt(_T_1303) node _T_1305 = eq(_T_1304, asSInt(UInt<1>(0h0))) node _T_1306 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1307 = cvt(_T_1306) node _T_1308 = and(_T_1307, asSInt(UInt<17>(0h10000))) node _T_1309 = asSInt(_T_1308) node _T_1310 = eq(_T_1309, asSInt(UInt<1>(0h0))) node _T_1311 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1312 = cvt(_T_1311) node _T_1313 = and(_T_1312, asSInt(UInt<27>(0h4000000))) node _T_1314 = asSInt(_T_1313) node _T_1315 = eq(_T_1314, asSInt(UInt<1>(0h0))) node _T_1316 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1317 = cvt(_T_1316) node _T_1318 = and(_T_1317, asSInt(UInt<13>(0h1000))) node _T_1319 = asSInt(_T_1318) node _T_1320 = eq(_T_1319, asSInt(UInt<1>(0h0))) node _T_1321 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1322 = cvt(_T_1321) node _T_1323 = and(_T_1322, asSInt(UInt<29>(0h10000000))) node _T_1324 = asSInt(_T_1323) node _T_1325 = eq(_T_1324, asSInt(UInt<1>(0h0))) node _T_1326 = or(_T_1280, _T_1285) node _T_1327 = or(_T_1326, _T_1290) node _T_1328 = or(_T_1327, _T_1295) node _T_1329 = or(_T_1328, _T_1300) node _T_1330 = or(_T_1329, _T_1305) node _T_1331 = or(_T_1330, _T_1310) node _T_1332 = or(_T_1331, _T_1315) node _T_1333 = or(_T_1332, _T_1320) node _T_1334 = or(_T_1333, _T_1325) node _T_1335 = and(_T_1275, _T_1334) node _T_1336 = or(UInt<1>(0h0), _T_1335) node _T_1337 = and(UInt<1>(0h0), _T_1336) node _T_1338 = asUInt(reset) node _T_1339 = eq(_T_1338, UInt<1>(0h0)) when _T_1339 : node _T_1340 = eq(_T_1337, UInt<1>(0h0)) when _T_1340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_1337, UInt<1>(0h1), "") : assert_93 node _T_1341 = asUInt(reset) node _T_1342 = eq(_T_1341, UInt<1>(0h0)) when _T_1342 : node _T_1343 = eq(address_ok, UInt<1>(0h0)) when _T_1343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_1344 = asUInt(reset) node _T_1345 = eq(_T_1344, UInt<1>(0h0)) when _T_1345 : node _T_1346 = eq(legal_source, UInt<1>(0h0)) when _T_1346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_1347 = asUInt(reset) node _T_1348 = eq(_T_1347, UInt<1>(0h0)) when _T_1348 : node _T_1349 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1349 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_1350 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1351 = asUInt(reset) node _T_1352 = eq(_T_1351, UInt<1>(0h0)) when _T_1352 : node _T_1353 = eq(_T_1350, UInt<1>(0h0)) when _T_1353 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_1350, UInt<1>(0h1), "") : assert_97 node _T_1354 = eq(io.in.b.bits.mask, mask_1) node _T_1355 = asUInt(reset) node _T_1356 = eq(_T_1355, UInt<1>(0h0)) when _T_1356 : node _T_1357 = eq(_T_1354, UInt<1>(0h0)) when _T_1357 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1354, UInt<1>(0h1), "") : assert_98 node _T_1358 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1359 = asUInt(reset) node _T_1360 = eq(_T_1359, UInt<1>(0h0)) when _T_1360 : node _T_1361 = eq(_T_1358, UInt<1>(0h0)) when _T_1361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_1358, UInt<1>(0h1), "") : assert_99 node _T_1362 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_1362 : node _T_1363 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1364 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1365 = and(_T_1363, _T_1364) node _T_1366 = or(UInt<1>(0h0), _T_1365) node _T_1367 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1368 = cvt(_T_1367) node _T_1369 = and(_T_1368, asSInt(UInt<14>(0h2000))) node _T_1370 = asSInt(_T_1369) node _T_1371 = eq(_T_1370, asSInt(UInt<1>(0h0))) node _T_1372 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1373 = cvt(_T_1372) node _T_1374 = and(_T_1373, asSInt(UInt<13>(0h1000))) node _T_1375 = asSInt(_T_1374) node _T_1376 = eq(_T_1375, asSInt(UInt<1>(0h0))) node _T_1377 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1378 = cvt(_T_1377) node _T_1379 = and(_T_1378, asSInt(UInt<17>(0h10000))) node _T_1380 = asSInt(_T_1379) node _T_1381 = eq(_T_1380, asSInt(UInt<1>(0h0))) node _T_1382 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1383 = cvt(_T_1382) node _T_1384 = and(_T_1383, asSInt(UInt<18>(0h2f000))) node _T_1385 = asSInt(_T_1384) node _T_1386 = eq(_T_1385, asSInt(UInt<1>(0h0))) node _T_1387 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1388 = cvt(_T_1387) node _T_1389 = and(_T_1388, asSInt(UInt<17>(0h10000))) node _T_1390 = asSInt(_T_1389) node _T_1391 = eq(_T_1390, asSInt(UInt<1>(0h0))) node _T_1392 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1393 = cvt(_T_1392) node _T_1394 = and(_T_1393, asSInt(UInt<13>(0h1000))) node _T_1395 = asSInt(_T_1394) node _T_1396 = eq(_T_1395, asSInt(UInt<1>(0h0))) node _T_1397 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1398 = cvt(_T_1397) node _T_1399 = and(_T_1398, asSInt(UInt<17>(0h10000))) node _T_1400 = asSInt(_T_1399) node _T_1401 = eq(_T_1400, asSInt(UInt<1>(0h0))) node _T_1402 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1403 = cvt(_T_1402) node _T_1404 = and(_T_1403, asSInt(UInt<27>(0h4000000))) node _T_1405 = asSInt(_T_1404) node _T_1406 = eq(_T_1405, asSInt(UInt<1>(0h0))) node _T_1407 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1408 = cvt(_T_1407) node _T_1409 = and(_T_1408, asSInt(UInt<13>(0h1000))) node _T_1410 = asSInt(_T_1409) node _T_1411 = eq(_T_1410, asSInt(UInt<1>(0h0))) node _T_1412 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1413 = cvt(_T_1412) node _T_1414 = and(_T_1413, asSInt(UInt<29>(0h10000000))) node _T_1415 = asSInt(_T_1414) node _T_1416 = eq(_T_1415, asSInt(UInt<1>(0h0))) node _T_1417 = or(_T_1371, _T_1376) node _T_1418 = or(_T_1417, _T_1381) node _T_1419 = or(_T_1418, _T_1386) node _T_1420 = or(_T_1419, _T_1391) node _T_1421 = or(_T_1420, _T_1396) node _T_1422 = or(_T_1421, _T_1401) node _T_1423 = or(_T_1422, _T_1406) node _T_1424 = or(_T_1423, _T_1411) node _T_1425 = or(_T_1424, _T_1416) node _T_1426 = and(_T_1366, _T_1425) node _T_1427 = or(UInt<1>(0h0), _T_1426) node _T_1428 = and(UInt<1>(0h0), _T_1427) node _T_1429 = asUInt(reset) node _T_1430 = eq(_T_1429, UInt<1>(0h0)) when _T_1430 : node _T_1431 = eq(_T_1428, UInt<1>(0h0)) when _T_1431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_1428, UInt<1>(0h1), "") : assert_100 node _T_1432 = asUInt(reset) node _T_1433 = eq(_T_1432, UInt<1>(0h0)) when _T_1433 : node _T_1434 = eq(address_ok, UInt<1>(0h0)) when _T_1434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_1435 = asUInt(reset) node _T_1436 = eq(_T_1435, UInt<1>(0h0)) when _T_1436 : node _T_1437 = eq(legal_source, UInt<1>(0h0)) when _T_1437 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_1438 = asUInt(reset) node _T_1439 = eq(_T_1438, UInt<1>(0h0)) when _T_1439 : node _T_1440 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_1441 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1442 = asUInt(reset) node _T_1443 = eq(_T_1442, UInt<1>(0h0)) when _T_1443 : node _T_1444 = eq(_T_1441, UInt<1>(0h0)) when _T_1444 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_1441, UInt<1>(0h1), "") : assert_104 node _T_1445 = eq(io.in.b.bits.mask, mask_1) node _T_1446 = asUInt(reset) node _T_1447 = eq(_T_1446, UInt<1>(0h0)) when _T_1447 : node _T_1448 = eq(_T_1445, UInt<1>(0h0)) when _T_1448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1445, UInt<1>(0h1), "") : assert_105 node _T_1449 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_1449 : node _T_1450 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1451 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1452 = and(_T_1450, _T_1451) node _T_1453 = or(UInt<1>(0h0), _T_1452) node _T_1454 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1455 = cvt(_T_1454) node _T_1456 = and(_T_1455, asSInt(UInt<14>(0h2000))) node _T_1457 = asSInt(_T_1456) node _T_1458 = eq(_T_1457, asSInt(UInt<1>(0h0))) node _T_1459 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1460 = cvt(_T_1459) node _T_1461 = and(_T_1460, asSInt(UInt<13>(0h1000))) node _T_1462 = asSInt(_T_1461) node _T_1463 = eq(_T_1462, asSInt(UInt<1>(0h0))) node _T_1464 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1465 = cvt(_T_1464) node _T_1466 = and(_T_1465, asSInt(UInt<17>(0h10000))) node _T_1467 = asSInt(_T_1466) node _T_1468 = eq(_T_1467, asSInt(UInt<1>(0h0))) node _T_1469 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1470 = cvt(_T_1469) node _T_1471 = and(_T_1470, asSInt(UInt<18>(0h2f000))) node _T_1472 = asSInt(_T_1471) node _T_1473 = eq(_T_1472, asSInt(UInt<1>(0h0))) node _T_1474 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1475 = cvt(_T_1474) node _T_1476 = and(_T_1475, asSInt(UInt<17>(0h10000))) node _T_1477 = asSInt(_T_1476) node _T_1478 = eq(_T_1477, asSInt(UInt<1>(0h0))) node _T_1479 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1480 = cvt(_T_1479) node _T_1481 = and(_T_1480, asSInt(UInt<13>(0h1000))) node _T_1482 = asSInt(_T_1481) node _T_1483 = eq(_T_1482, asSInt(UInt<1>(0h0))) node _T_1484 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1485 = cvt(_T_1484) node _T_1486 = and(_T_1485, asSInt(UInt<17>(0h10000))) node _T_1487 = asSInt(_T_1486) node _T_1488 = eq(_T_1487, asSInt(UInt<1>(0h0))) node _T_1489 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1490 = cvt(_T_1489) node _T_1491 = and(_T_1490, asSInt(UInt<27>(0h4000000))) node _T_1492 = asSInt(_T_1491) node _T_1493 = eq(_T_1492, asSInt(UInt<1>(0h0))) node _T_1494 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1495 = cvt(_T_1494) node _T_1496 = and(_T_1495, asSInt(UInt<13>(0h1000))) node _T_1497 = asSInt(_T_1496) node _T_1498 = eq(_T_1497, asSInt(UInt<1>(0h0))) node _T_1499 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1500 = cvt(_T_1499) node _T_1501 = and(_T_1500, asSInt(UInt<29>(0h10000000))) node _T_1502 = asSInt(_T_1501) node _T_1503 = eq(_T_1502, asSInt(UInt<1>(0h0))) node _T_1504 = or(_T_1458, _T_1463) node _T_1505 = or(_T_1504, _T_1468) node _T_1506 = or(_T_1505, _T_1473) node _T_1507 = or(_T_1506, _T_1478) node _T_1508 = or(_T_1507, _T_1483) node _T_1509 = or(_T_1508, _T_1488) node _T_1510 = or(_T_1509, _T_1493) node _T_1511 = or(_T_1510, _T_1498) node _T_1512 = or(_T_1511, _T_1503) node _T_1513 = and(_T_1453, _T_1512) node _T_1514 = or(UInt<1>(0h0), _T_1513) node _T_1515 = and(UInt<1>(0h0), _T_1514) node _T_1516 = asUInt(reset) node _T_1517 = eq(_T_1516, UInt<1>(0h0)) when _T_1517 : node _T_1518 = eq(_T_1515, UInt<1>(0h0)) when _T_1518 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1515, UInt<1>(0h1), "") : assert_106 node _T_1519 = asUInt(reset) node _T_1520 = eq(_T_1519, UInt<1>(0h0)) when _T_1520 : node _T_1521 = eq(address_ok, UInt<1>(0h0)) when _T_1521 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_1522 = asUInt(reset) node _T_1523 = eq(_T_1522, UInt<1>(0h0)) when _T_1523 : node _T_1524 = eq(legal_source, UInt<1>(0h0)) when _T_1524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_1525 = asUInt(reset) node _T_1526 = eq(_T_1525, UInt<1>(0h0)) when _T_1526 : node _T_1527 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_1528 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1529 = asUInt(reset) node _T_1530 = eq(_T_1529, UInt<1>(0h0)) when _T_1530 : node _T_1531 = eq(_T_1528, UInt<1>(0h0)) when _T_1531 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_1528, UInt<1>(0h1), "") : assert_110 node _T_1532 = not(mask_1) node _T_1533 = and(io.in.b.bits.mask, _T_1532) node _T_1534 = eq(_T_1533, UInt<1>(0h0)) node _T_1535 = asUInt(reset) node _T_1536 = eq(_T_1535, UInt<1>(0h0)) when _T_1536 : node _T_1537 = eq(_T_1534, UInt<1>(0h0)) when _T_1537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1534, UInt<1>(0h1), "") : assert_111 node _T_1538 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_1538 : node _T_1539 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1540 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1541 = and(_T_1539, _T_1540) node _T_1542 = or(UInt<1>(0h0), _T_1541) node _T_1543 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1544 = cvt(_T_1543) node _T_1545 = and(_T_1544, asSInt(UInt<14>(0h2000))) node _T_1546 = asSInt(_T_1545) node _T_1547 = eq(_T_1546, asSInt(UInt<1>(0h0))) node _T_1548 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1549 = cvt(_T_1548) node _T_1550 = and(_T_1549, asSInt(UInt<13>(0h1000))) node _T_1551 = asSInt(_T_1550) node _T_1552 = eq(_T_1551, asSInt(UInt<1>(0h0))) node _T_1553 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1554 = cvt(_T_1553) node _T_1555 = and(_T_1554, asSInt(UInt<17>(0h10000))) node _T_1556 = asSInt(_T_1555) node _T_1557 = eq(_T_1556, asSInt(UInt<1>(0h0))) node _T_1558 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1559 = cvt(_T_1558) node _T_1560 = and(_T_1559, asSInt(UInt<18>(0h2f000))) node _T_1561 = asSInt(_T_1560) node _T_1562 = eq(_T_1561, asSInt(UInt<1>(0h0))) node _T_1563 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1564 = cvt(_T_1563) node _T_1565 = and(_T_1564, asSInt(UInt<17>(0h10000))) node _T_1566 = asSInt(_T_1565) node _T_1567 = eq(_T_1566, asSInt(UInt<1>(0h0))) node _T_1568 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1569 = cvt(_T_1568) node _T_1570 = and(_T_1569, asSInt(UInt<13>(0h1000))) node _T_1571 = asSInt(_T_1570) node _T_1572 = eq(_T_1571, asSInt(UInt<1>(0h0))) node _T_1573 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1574 = cvt(_T_1573) node _T_1575 = and(_T_1574, asSInt(UInt<17>(0h10000))) node _T_1576 = asSInt(_T_1575) node _T_1577 = eq(_T_1576, asSInt(UInt<1>(0h0))) node _T_1578 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1579 = cvt(_T_1578) node _T_1580 = and(_T_1579, asSInt(UInt<27>(0h4000000))) node _T_1581 = asSInt(_T_1580) node _T_1582 = eq(_T_1581, asSInt(UInt<1>(0h0))) node _T_1583 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1584 = cvt(_T_1583) node _T_1585 = and(_T_1584, asSInt(UInt<13>(0h1000))) node _T_1586 = asSInt(_T_1585) node _T_1587 = eq(_T_1586, asSInt(UInt<1>(0h0))) node _T_1588 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1589 = cvt(_T_1588) node _T_1590 = and(_T_1589, asSInt(UInt<29>(0h10000000))) node _T_1591 = asSInt(_T_1590) node _T_1592 = eq(_T_1591, asSInt(UInt<1>(0h0))) node _T_1593 = or(_T_1547, _T_1552) node _T_1594 = or(_T_1593, _T_1557) node _T_1595 = or(_T_1594, _T_1562) node _T_1596 = or(_T_1595, _T_1567) node _T_1597 = or(_T_1596, _T_1572) node _T_1598 = or(_T_1597, _T_1577) node _T_1599 = or(_T_1598, _T_1582) node _T_1600 = or(_T_1599, _T_1587) node _T_1601 = or(_T_1600, _T_1592) node _T_1602 = and(_T_1542, _T_1601) node _T_1603 = or(UInt<1>(0h0), _T_1602) node _T_1604 = and(UInt<1>(0h0), _T_1603) node _T_1605 = asUInt(reset) node _T_1606 = eq(_T_1605, UInt<1>(0h0)) when _T_1606 : node _T_1607 = eq(_T_1604, UInt<1>(0h0)) when _T_1607 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_1604, UInt<1>(0h1), "") : assert_112 node _T_1608 = asUInt(reset) node _T_1609 = eq(_T_1608, UInt<1>(0h0)) when _T_1609 : node _T_1610 = eq(address_ok, UInt<1>(0h0)) when _T_1610 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_1611 = asUInt(reset) node _T_1612 = eq(_T_1611, UInt<1>(0h0)) when _T_1612 : node _T_1613 = eq(legal_source, UInt<1>(0h0)) when _T_1613 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_1614 = asUInt(reset) node _T_1615 = eq(_T_1614, UInt<1>(0h0)) when _T_1615 : node _T_1616 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1616 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_1617 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_1618 = asUInt(reset) node _T_1619 = eq(_T_1618, UInt<1>(0h0)) when _T_1619 : node _T_1620 = eq(_T_1617, UInt<1>(0h0)) when _T_1620 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_1617, UInt<1>(0h1), "") : assert_116 node _T_1621 = eq(io.in.b.bits.mask, mask_1) node _T_1622 = asUInt(reset) node _T_1623 = eq(_T_1622, UInt<1>(0h0)) when _T_1623 : node _T_1624 = eq(_T_1621, UInt<1>(0h0)) when _T_1624 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_1621, UInt<1>(0h1), "") : assert_117 node _T_1625 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_1625 : node _T_1626 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1627 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1628 = and(_T_1626, _T_1627) node _T_1629 = or(UInt<1>(0h0), _T_1628) node _T_1630 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1631 = cvt(_T_1630) node _T_1632 = and(_T_1631, asSInt(UInt<14>(0h2000))) node _T_1633 = asSInt(_T_1632) node _T_1634 = eq(_T_1633, asSInt(UInt<1>(0h0))) node _T_1635 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1636 = cvt(_T_1635) node _T_1637 = and(_T_1636, asSInt(UInt<13>(0h1000))) node _T_1638 = asSInt(_T_1637) node _T_1639 = eq(_T_1638, asSInt(UInt<1>(0h0))) node _T_1640 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1641 = cvt(_T_1640) node _T_1642 = and(_T_1641, asSInt(UInt<17>(0h10000))) node _T_1643 = asSInt(_T_1642) node _T_1644 = eq(_T_1643, asSInt(UInt<1>(0h0))) node _T_1645 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1646 = cvt(_T_1645) node _T_1647 = and(_T_1646, asSInt(UInt<18>(0h2f000))) node _T_1648 = asSInt(_T_1647) node _T_1649 = eq(_T_1648, asSInt(UInt<1>(0h0))) node _T_1650 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1651 = cvt(_T_1650) node _T_1652 = and(_T_1651, asSInt(UInt<17>(0h10000))) node _T_1653 = asSInt(_T_1652) node _T_1654 = eq(_T_1653, asSInt(UInt<1>(0h0))) node _T_1655 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1656 = cvt(_T_1655) node _T_1657 = and(_T_1656, asSInt(UInt<13>(0h1000))) node _T_1658 = asSInt(_T_1657) node _T_1659 = eq(_T_1658, asSInt(UInt<1>(0h0))) node _T_1660 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1661 = cvt(_T_1660) node _T_1662 = and(_T_1661, asSInt(UInt<17>(0h10000))) node _T_1663 = asSInt(_T_1662) node _T_1664 = eq(_T_1663, asSInt(UInt<1>(0h0))) node _T_1665 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1666 = cvt(_T_1665) node _T_1667 = and(_T_1666, asSInt(UInt<27>(0h4000000))) node _T_1668 = asSInt(_T_1667) node _T_1669 = eq(_T_1668, asSInt(UInt<1>(0h0))) node _T_1670 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1671 = cvt(_T_1670) node _T_1672 = and(_T_1671, asSInt(UInt<13>(0h1000))) node _T_1673 = asSInt(_T_1672) node _T_1674 = eq(_T_1673, asSInt(UInt<1>(0h0))) node _T_1675 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1676 = cvt(_T_1675) node _T_1677 = and(_T_1676, asSInt(UInt<29>(0h10000000))) node _T_1678 = asSInt(_T_1677) node _T_1679 = eq(_T_1678, asSInt(UInt<1>(0h0))) node _T_1680 = or(_T_1634, _T_1639) node _T_1681 = or(_T_1680, _T_1644) node _T_1682 = or(_T_1681, _T_1649) node _T_1683 = or(_T_1682, _T_1654) node _T_1684 = or(_T_1683, _T_1659) node _T_1685 = or(_T_1684, _T_1664) node _T_1686 = or(_T_1685, _T_1669) node _T_1687 = or(_T_1686, _T_1674) node _T_1688 = or(_T_1687, _T_1679) node _T_1689 = and(_T_1629, _T_1688) node _T_1690 = or(UInt<1>(0h0), _T_1689) node _T_1691 = and(UInt<1>(0h0), _T_1690) node _T_1692 = asUInt(reset) node _T_1693 = eq(_T_1692, UInt<1>(0h0)) when _T_1693 : node _T_1694 = eq(_T_1691, UInt<1>(0h0)) when _T_1694 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_1691, UInt<1>(0h1), "") : assert_118 node _T_1695 = asUInt(reset) node _T_1696 = eq(_T_1695, UInt<1>(0h0)) when _T_1696 : node _T_1697 = eq(address_ok, UInt<1>(0h0)) when _T_1697 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_1698 = asUInt(reset) node _T_1699 = eq(_T_1698, UInt<1>(0h0)) when _T_1699 : node _T_1700 = eq(legal_source, UInt<1>(0h0)) when _T_1700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_1701 = asUInt(reset) node _T_1702 = eq(_T_1701, UInt<1>(0h0)) when _T_1702 : node _T_1703 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1703 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_1704 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_1705 = asUInt(reset) node _T_1706 = eq(_T_1705, UInt<1>(0h0)) when _T_1706 : node _T_1707 = eq(_T_1704, UInt<1>(0h0)) when _T_1707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_1704, UInt<1>(0h1), "") : assert_122 node _T_1708 = eq(io.in.b.bits.mask, mask_1) node _T_1709 = asUInt(reset) node _T_1710 = eq(_T_1709, UInt<1>(0h0)) when _T_1710 : node _T_1711 = eq(_T_1708, UInt<1>(0h0)) when _T_1711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_1708, UInt<1>(0h1), "") : assert_123 node _T_1712 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_1712 : node _T_1713 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1714 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1715 = and(_T_1713, _T_1714) node _T_1716 = or(UInt<1>(0h0), _T_1715) node _T_1717 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1718 = cvt(_T_1717) node _T_1719 = and(_T_1718, asSInt(UInt<14>(0h2000))) node _T_1720 = asSInt(_T_1719) node _T_1721 = eq(_T_1720, asSInt(UInt<1>(0h0))) node _T_1722 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1723 = cvt(_T_1722) node _T_1724 = and(_T_1723, asSInt(UInt<13>(0h1000))) node _T_1725 = asSInt(_T_1724) node _T_1726 = eq(_T_1725, asSInt(UInt<1>(0h0))) node _T_1727 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1728 = cvt(_T_1727) node _T_1729 = and(_T_1728, asSInt(UInt<17>(0h10000))) node _T_1730 = asSInt(_T_1729) node _T_1731 = eq(_T_1730, asSInt(UInt<1>(0h0))) node _T_1732 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1733 = cvt(_T_1732) node _T_1734 = and(_T_1733, asSInt(UInt<18>(0h2f000))) node _T_1735 = asSInt(_T_1734) node _T_1736 = eq(_T_1735, asSInt(UInt<1>(0h0))) node _T_1737 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1738 = cvt(_T_1737) node _T_1739 = and(_T_1738, asSInt(UInt<17>(0h10000))) node _T_1740 = asSInt(_T_1739) node _T_1741 = eq(_T_1740, asSInt(UInt<1>(0h0))) node _T_1742 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1743 = cvt(_T_1742) node _T_1744 = and(_T_1743, asSInt(UInt<13>(0h1000))) node _T_1745 = asSInt(_T_1744) node _T_1746 = eq(_T_1745, asSInt(UInt<1>(0h0))) node _T_1747 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1748 = cvt(_T_1747) node _T_1749 = and(_T_1748, asSInt(UInt<17>(0h10000))) node _T_1750 = asSInt(_T_1749) node _T_1751 = eq(_T_1750, asSInt(UInt<1>(0h0))) node _T_1752 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1753 = cvt(_T_1752) node _T_1754 = and(_T_1753, asSInt(UInt<27>(0h4000000))) node _T_1755 = asSInt(_T_1754) node _T_1756 = eq(_T_1755, asSInt(UInt<1>(0h0))) node _T_1757 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1758 = cvt(_T_1757) node _T_1759 = and(_T_1758, asSInt(UInt<13>(0h1000))) node _T_1760 = asSInt(_T_1759) node _T_1761 = eq(_T_1760, asSInt(UInt<1>(0h0))) node _T_1762 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1763 = cvt(_T_1762) node _T_1764 = and(_T_1763, asSInt(UInt<29>(0h10000000))) node _T_1765 = asSInt(_T_1764) node _T_1766 = eq(_T_1765, asSInt(UInt<1>(0h0))) node _T_1767 = or(_T_1721, _T_1726) node _T_1768 = or(_T_1767, _T_1731) node _T_1769 = or(_T_1768, _T_1736) node _T_1770 = or(_T_1769, _T_1741) node _T_1771 = or(_T_1770, _T_1746) node _T_1772 = or(_T_1771, _T_1751) node _T_1773 = or(_T_1772, _T_1756) node _T_1774 = or(_T_1773, _T_1761) node _T_1775 = or(_T_1774, _T_1766) node _T_1776 = and(_T_1716, _T_1775) node _T_1777 = or(UInt<1>(0h0), _T_1776) node _T_1778 = and(UInt<1>(0h0), _T_1777) node _T_1779 = asUInt(reset) node _T_1780 = eq(_T_1779, UInt<1>(0h0)) when _T_1780 : node _T_1781 = eq(_T_1778, UInt<1>(0h0)) when _T_1781 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_1778, UInt<1>(0h1), "") : assert_124 node _T_1782 = asUInt(reset) node _T_1783 = eq(_T_1782, UInt<1>(0h0)) when _T_1783 : node _T_1784 = eq(address_ok, UInt<1>(0h0)) when _T_1784 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_1785 = asUInt(reset) node _T_1786 = eq(_T_1785, UInt<1>(0h0)) when _T_1786 : node _T_1787 = eq(legal_source, UInt<1>(0h0)) when _T_1787 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_1788 = asUInt(reset) node _T_1789 = eq(_T_1788, UInt<1>(0h0)) when _T_1789 : node _T_1790 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1790 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_1791 = eq(io.in.b.bits.mask, mask_1) node _T_1792 = asUInt(reset) node _T_1793 = eq(_T_1792, UInt<1>(0h0)) when _T_1793 : node _T_1794 = eq(_T_1791, UInt<1>(0h0)) when _T_1794 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_1791, UInt<1>(0h1), "") : assert_128 node _T_1795 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1796 = asUInt(reset) node _T_1797 = eq(_T_1796, UInt<1>(0h0)) when _T_1797 : node _T_1798 = eq(_T_1795, UInt<1>(0h0)) when _T_1798 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_1795, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_1799 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_1800 = asUInt(reset) node _T_1801 = eq(_T_1800, UInt<1>(0h0)) when _T_1801 : node _T_1802 = eq(_T_1799, UInt<1>(0h0)) when _T_1802 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_1799, UInt<1>(0h1), "") : assert_130 node _source_ok_T_8 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _source_ok_T_9 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _source_ok_T_10 = eq(io.in.c.bits.source, UInt<2>(0h2)) wire _source_ok_WIRE_2 : UInt<1>[3] connect _source_ok_WIRE_2[0], _source_ok_T_8 connect _source_ok_WIRE_2[1], _source_ok_T_9 connect _source_ok_WIRE_2[2], _source_ok_T_10 node _source_ok_T_11 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1]) node source_ok_2 = or(_source_ok_T_11, _source_ok_WIRE_2[2]) node _is_aligned_mask_T_4 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 11, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_70 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _address_ok_T_71 = cvt(_address_ok_T_70) node _address_ok_T_72 = and(_address_ok_T_71, asSInt(UInt<13>(0h1000))) node _address_ok_T_73 = asSInt(_address_ok_T_72) node _address_ok_T_74 = eq(_address_ok_T_73, asSInt(UInt<1>(0h0))) node _address_ok_T_75 = xor(io.in.c.bits.address, UInt<13>(0h1000)) node _address_ok_T_76 = cvt(_address_ok_T_75) node _address_ok_T_77 = and(_address_ok_T_76, asSInt(UInt<13>(0h1000))) node _address_ok_T_78 = asSInt(_address_ok_T_77) node _address_ok_T_79 = eq(_address_ok_T_78, asSInt(UInt<1>(0h0))) node _address_ok_T_80 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _address_ok_T_81 = cvt(_address_ok_T_80) node _address_ok_T_82 = and(_address_ok_T_81, asSInt(UInt<13>(0h1000))) node _address_ok_T_83 = asSInt(_address_ok_T_82) node _address_ok_T_84 = eq(_address_ok_T_83, asSInt(UInt<1>(0h0))) node _address_ok_T_85 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _address_ok_T_86 = cvt(_address_ok_T_85) node _address_ok_T_87 = and(_address_ok_T_86, asSInt(UInt<17>(0h10000))) node _address_ok_T_88 = asSInt(_address_ok_T_87) node _address_ok_T_89 = eq(_address_ok_T_88, asSInt(UInt<1>(0h0))) node _address_ok_T_90 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _address_ok_T_91 = cvt(_address_ok_T_90) node _address_ok_T_92 = and(_address_ok_T_91, asSInt(UInt<13>(0h1000))) node _address_ok_T_93 = asSInt(_address_ok_T_92) node _address_ok_T_94 = eq(_address_ok_T_93, asSInt(UInt<1>(0h0))) node _address_ok_T_95 = xor(io.in.c.bits.address, UInt<21>(0h110000)) node _address_ok_T_96 = cvt(_address_ok_T_95) node _address_ok_T_97 = and(_address_ok_T_96, asSInt(UInt<13>(0h1000))) node _address_ok_T_98 = asSInt(_address_ok_T_97) node _address_ok_T_99 = eq(_address_ok_T_98, asSInt(UInt<1>(0h0))) node _address_ok_T_100 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _address_ok_T_101 = cvt(_address_ok_T_100) node _address_ok_T_102 = and(_address_ok_T_101, asSInt(UInt<17>(0h10000))) node _address_ok_T_103 = asSInt(_address_ok_T_102) node _address_ok_T_104 = eq(_address_ok_T_103, asSInt(UInt<1>(0h0))) node _address_ok_T_105 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _address_ok_T_106 = cvt(_address_ok_T_105) node _address_ok_T_107 = and(_address_ok_T_106, asSInt(UInt<13>(0h1000))) node _address_ok_T_108 = asSInt(_address_ok_T_107) node _address_ok_T_109 = eq(_address_ok_T_108, asSInt(UInt<1>(0h0))) node _address_ok_T_110 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _address_ok_T_111 = cvt(_address_ok_T_110) node _address_ok_T_112 = and(_address_ok_T_111, asSInt(UInt<17>(0h10000))) node _address_ok_T_113 = asSInt(_address_ok_T_112) node _address_ok_T_114 = eq(_address_ok_T_113, asSInt(UInt<1>(0h0))) node _address_ok_T_115 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _address_ok_T_116 = cvt(_address_ok_T_115) node _address_ok_T_117 = and(_address_ok_T_116, asSInt(UInt<27>(0h4000000))) node _address_ok_T_118 = asSInt(_address_ok_T_117) node _address_ok_T_119 = eq(_address_ok_T_118, asSInt(UInt<1>(0h0))) node _address_ok_T_120 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _address_ok_T_121 = cvt(_address_ok_T_120) node _address_ok_T_122 = and(_address_ok_T_121, asSInt(UInt<13>(0h1000))) node _address_ok_T_123 = asSInt(_address_ok_T_122) node _address_ok_T_124 = eq(_address_ok_T_123, asSInt(UInt<1>(0h0))) node _address_ok_T_125 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _address_ok_T_126 = cvt(_address_ok_T_125) node _address_ok_T_127 = and(_address_ok_T_126, asSInt(UInt<29>(0h10000000))) node _address_ok_T_128 = asSInt(_address_ok_T_127) node _address_ok_T_129 = eq(_address_ok_T_128, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[12] connect _address_ok_WIRE_1[0], _address_ok_T_74 connect _address_ok_WIRE_1[1], _address_ok_T_79 connect _address_ok_WIRE_1[2], _address_ok_T_84 connect _address_ok_WIRE_1[3], _address_ok_T_89 connect _address_ok_WIRE_1[4], _address_ok_T_94 connect _address_ok_WIRE_1[5], _address_ok_T_99 connect _address_ok_WIRE_1[6], _address_ok_T_104 connect _address_ok_WIRE_1[7], _address_ok_T_109 connect _address_ok_WIRE_1[8], _address_ok_T_114 connect _address_ok_WIRE_1[9], _address_ok_T_119 connect _address_ok_WIRE_1[10], _address_ok_T_124 connect _address_ok_WIRE_1[11], _address_ok_T_129 node _address_ok_T_130 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _address_ok_T_131 = or(_address_ok_T_130, _address_ok_WIRE_1[2]) node _address_ok_T_132 = or(_address_ok_T_131, _address_ok_WIRE_1[3]) node _address_ok_T_133 = or(_address_ok_T_132, _address_ok_WIRE_1[4]) node _address_ok_T_134 = or(_address_ok_T_133, _address_ok_WIRE_1[5]) node _address_ok_T_135 = or(_address_ok_T_134, _address_ok_WIRE_1[6]) node _address_ok_T_136 = or(_address_ok_T_135, _address_ok_WIRE_1[7]) node _address_ok_T_137 = or(_address_ok_T_136, _address_ok_WIRE_1[8]) node _address_ok_T_138 = or(_address_ok_T_137, _address_ok_WIRE_1[9]) node _address_ok_T_139 = or(_address_ok_T_138, _address_ok_WIRE_1[10]) node address_ok_1 = or(_address_ok_T_139, _address_ok_WIRE_1[11]) node _T_1803 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_1804 = eq(_T_1803, UInt<1>(0h0)) node _T_1805 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1806 = cvt(_T_1805) node _T_1807 = and(_T_1806, asSInt(UInt<1>(0h0))) node _T_1808 = asSInt(_T_1807) node _T_1809 = eq(_T_1808, asSInt(UInt<1>(0h0))) node _T_1810 = or(_T_1804, _T_1809) node _T_1811 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_1812 = eq(_T_1811, UInt<1>(0h0)) node _T_1813 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1814 = cvt(_T_1813) node _T_1815 = and(_T_1814, asSInt(UInt<1>(0h0))) node _T_1816 = asSInt(_T_1815) node _T_1817 = eq(_T_1816, asSInt(UInt<1>(0h0))) node _T_1818 = or(_T_1812, _T_1817) node _T_1819 = eq(io.in.c.bits.source, UInt<2>(0h2)) node _T_1820 = eq(_T_1819, UInt<1>(0h0)) node _T_1821 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1822 = cvt(_T_1821) node _T_1823 = and(_T_1822, asSInt(UInt<1>(0h0))) node _T_1824 = asSInt(_T_1823) node _T_1825 = eq(_T_1824, asSInt(UInt<1>(0h0))) node _T_1826 = or(_T_1820, _T_1825) node _T_1827 = and(_T_1810, _T_1818) node _T_1828 = and(_T_1827, _T_1826) node _T_1829 = asUInt(reset) node _T_1830 = eq(_T_1829, UInt<1>(0h0)) when _T_1830 : node _T_1831 = eq(_T_1828, UInt<1>(0h0)) when _T_1831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_1828, UInt<1>(0h1), "") : assert_131 node _T_1832 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_1832 : node _T_1833 = asUInt(reset) node _T_1834 = eq(_T_1833, UInt<1>(0h0)) when _T_1834 : node _T_1835 = eq(address_ok_1, UInt<1>(0h0)) when _T_1835 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_1836 = asUInt(reset) node _T_1837 = eq(_T_1836, UInt<1>(0h0)) when _T_1837 : node _T_1838 = eq(source_ok_2, UInt<1>(0h0)) when _T_1838 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133 node _T_1839 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1840 = asUInt(reset) node _T_1841 = eq(_T_1840, UInt<1>(0h0)) when _T_1841 : node _T_1842 = eq(_T_1839, UInt<1>(0h0)) when _T_1842 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_1839, UInt<1>(0h1), "") : assert_134 node _T_1843 = asUInt(reset) node _T_1844 = eq(_T_1843, UInt<1>(0h0)) when _T_1844 : node _T_1845 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_1846 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1847 = asUInt(reset) node _T_1848 = eq(_T_1847, UInt<1>(0h0)) when _T_1848 : node _T_1849 = eq(_T_1846, UInt<1>(0h0)) when _T_1849 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_1846, UInt<1>(0h1), "") : assert_136 node _T_1850 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1851 = asUInt(reset) node _T_1852 = eq(_T_1851, UInt<1>(0h0)) when _T_1852 : node _T_1853 = eq(_T_1850, UInt<1>(0h0)) when _T_1853 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_1850, UInt<1>(0h1), "") : assert_137 node _T_1854 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_1854 : node _T_1855 = asUInt(reset) node _T_1856 = eq(_T_1855, UInt<1>(0h0)) when _T_1856 : node _T_1857 = eq(address_ok_1, UInt<1>(0h0)) when _T_1857 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_1858 = asUInt(reset) node _T_1859 = eq(_T_1858, UInt<1>(0h0)) when _T_1859 : node _T_1860 = eq(source_ok_2, UInt<1>(0h0)) when _T_1860 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139 node _T_1861 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1862 = asUInt(reset) node _T_1863 = eq(_T_1862, UInt<1>(0h0)) when _T_1863 : node _T_1864 = eq(_T_1861, UInt<1>(0h0)) when _T_1864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_1861, UInt<1>(0h1), "") : assert_140 node _T_1865 = asUInt(reset) node _T_1866 = eq(_T_1865, UInt<1>(0h0)) when _T_1866 : node _T_1867 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1867 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_1868 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1869 = asUInt(reset) node _T_1870 = eq(_T_1869, UInt<1>(0h0)) when _T_1870 : node _T_1871 = eq(_T_1868, UInt<1>(0h0)) when _T_1871 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_1868, UInt<1>(0h1), "") : assert_142 node _T_1872 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_1872 : node _T_1873 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1874 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1875 = and(_T_1873, _T_1874) node _T_1876 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_1877 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_1878 = eq(io.in.c.bits.source, UInt<2>(0h2)) node _T_1879 = or(_T_1876, _T_1877) node _T_1880 = or(_T_1879, _T_1878) node _T_1881 = and(_T_1875, _T_1880) node _T_1882 = or(UInt<1>(0h0), _T_1881) node _T_1883 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1884 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1885 = cvt(_T_1884) node _T_1886 = and(_T_1885, asSInt(UInt<14>(0h2000))) node _T_1887 = asSInt(_T_1886) node _T_1888 = eq(_T_1887, asSInt(UInt<1>(0h0))) node _T_1889 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_1890 = cvt(_T_1889) node _T_1891 = and(_T_1890, asSInt(UInt<13>(0h1000))) node _T_1892 = asSInt(_T_1891) node _T_1893 = eq(_T_1892, asSInt(UInt<1>(0h0))) node _T_1894 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_1895 = cvt(_T_1894) node _T_1896 = and(_T_1895, asSInt(UInt<17>(0h10000))) node _T_1897 = asSInt(_T_1896) node _T_1898 = eq(_T_1897, asSInt(UInt<1>(0h0))) node _T_1899 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_1900 = cvt(_T_1899) node _T_1901 = and(_T_1900, asSInt(UInt<18>(0h2f000))) node _T_1902 = asSInt(_T_1901) node _T_1903 = eq(_T_1902, asSInt(UInt<1>(0h0))) node _T_1904 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_1905 = cvt(_T_1904) node _T_1906 = and(_T_1905, asSInt(UInt<17>(0h10000))) node _T_1907 = asSInt(_T_1906) node _T_1908 = eq(_T_1907, asSInt(UInt<1>(0h0))) node _T_1909 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_1910 = cvt(_T_1909) node _T_1911 = and(_T_1910, asSInt(UInt<13>(0h1000))) node _T_1912 = asSInt(_T_1911) node _T_1913 = eq(_T_1912, asSInt(UInt<1>(0h0))) node _T_1914 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_1915 = cvt(_T_1914) node _T_1916 = and(_T_1915, asSInt(UInt<27>(0h4000000))) node _T_1917 = asSInt(_T_1916) node _T_1918 = eq(_T_1917, asSInt(UInt<1>(0h0))) node _T_1919 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_1920 = cvt(_T_1919) node _T_1921 = and(_T_1920, asSInt(UInt<13>(0h1000))) node _T_1922 = asSInt(_T_1921) node _T_1923 = eq(_T_1922, asSInt(UInt<1>(0h0))) node _T_1924 = or(_T_1888, _T_1893) node _T_1925 = or(_T_1924, _T_1898) node _T_1926 = or(_T_1925, _T_1903) node _T_1927 = or(_T_1926, _T_1908) node _T_1928 = or(_T_1927, _T_1913) node _T_1929 = or(_T_1928, _T_1918) node _T_1930 = or(_T_1929, _T_1923) node _T_1931 = and(_T_1883, _T_1930) node _T_1932 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1933 = or(UInt<1>(0h0), _T_1932) node _T_1934 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1935 = cvt(_T_1934) node _T_1936 = and(_T_1935, asSInt(UInt<17>(0h10000))) node _T_1937 = asSInt(_T_1936) node _T_1938 = eq(_T_1937, asSInt(UInt<1>(0h0))) node _T_1939 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1940 = cvt(_T_1939) node _T_1941 = and(_T_1940, asSInt(UInt<29>(0h10000000))) node _T_1942 = asSInt(_T_1941) node _T_1943 = eq(_T_1942, asSInt(UInt<1>(0h0))) node _T_1944 = or(_T_1938, _T_1943) node _T_1945 = and(_T_1933, _T_1944) node _T_1946 = or(UInt<1>(0h0), _T_1931) node _T_1947 = or(_T_1946, _T_1945) node _T_1948 = and(_T_1882, _T_1947) node _T_1949 = asUInt(reset) node _T_1950 = eq(_T_1949, UInt<1>(0h0)) when _T_1950 : node _T_1951 = eq(_T_1948, UInt<1>(0h0)) when _T_1951 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_1948, UInt<1>(0h1), "") : assert_143 node _T_1952 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_1953 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_1954 = eq(io.in.c.bits.source, UInt<2>(0h2)) wire _WIRE_6 : UInt<1>[3] connect _WIRE_6[0], _T_1952 connect _WIRE_6[1], _T_1953 connect _WIRE_6[2], _T_1954 node _T_1955 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1956 = mux(_WIRE_6[0], _T_1955, UInt<1>(0h0)) node _T_1957 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1958 = mux(_WIRE_6[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1959 = or(_T_1956, _T_1957) node _T_1960 = or(_T_1959, _T_1958) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_1960 node _T_1961 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1962 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1963 = and(_T_1961, _T_1962) node _T_1964 = or(UInt<1>(0h0), _T_1963) node _T_1965 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1966 = cvt(_T_1965) node _T_1967 = and(_T_1966, asSInt(UInt<14>(0h2000))) node _T_1968 = asSInt(_T_1967) node _T_1969 = eq(_T_1968, asSInt(UInt<1>(0h0))) node _T_1970 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_1971 = cvt(_T_1970) node _T_1972 = and(_T_1971, asSInt(UInt<13>(0h1000))) node _T_1973 = asSInt(_T_1972) node _T_1974 = eq(_T_1973, asSInt(UInt<1>(0h0))) node _T_1975 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_1976 = cvt(_T_1975) node _T_1977 = and(_T_1976, asSInt(UInt<17>(0h10000))) node _T_1978 = asSInt(_T_1977) node _T_1979 = eq(_T_1978, asSInt(UInt<1>(0h0))) node _T_1980 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_1981 = cvt(_T_1980) node _T_1982 = and(_T_1981, asSInt(UInt<18>(0h2f000))) node _T_1983 = asSInt(_T_1982) node _T_1984 = eq(_T_1983, asSInt(UInt<1>(0h0))) node _T_1985 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_1986 = cvt(_T_1985) node _T_1987 = and(_T_1986, asSInt(UInt<17>(0h10000))) node _T_1988 = asSInt(_T_1987) node _T_1989 = eq(_T_1988, asSInt(UInt<1>(0h0))) node _T_1990 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_1991 = cvt(_T_1990) node _T_1992 = and(_T_1991, asSInt(UInt<13>(0h1000))) node _T_1993 = asSInt(_T_1992) node _T_1994 = eq(_T_1993, asSInt(UInt<1>(0h0))) node _T_1995 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1996 = cvt(_T_1995) node _T_1997 = and(_T_1996, asSInt(UInt<17>(0h10000))) node _T_1998 = asSInt(_T_1997) node _T_1999 = eq(_T_1998, asSInt(UInt<1>(0h0))) node _T_2000 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2001 = cvt(_T_2000) node _T_2002 = and(_T_2001, asSInt(UInt<27>(0h4000000))) node _T_2003 = asSInt(_T_2002) node _T_2004 = eq(_T_2003, asSInt(UInt<1>(0h0))) node _T_2005 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2006 = cvt(_T_2005) node _T_2007 = and(_T_2006, asSInt(UInt<13>(0h1000))) node _T_2008 = asSInt(_T_2007) node _T_2009 = eq(_T_2008, asSInt(UInt<1>(0h0))) node _T_2010 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2011 = cvt(_T_2010) node _T_2012 = and(_T_2011, asSInt(UInt<29>(0h10000000))) node _T_2013 = asSInt(_T_2012) node _T_2014 = eq(_T_2013, asSInt(UInt<1>(0h0))) node _T_2015 = or(_T_1969, _T_1974) node _T_2016 = or(_T_2015, _T_1979) node _T_2017 = or(_T_2016, _T_1984) node _T_2018 = or(_T_2017, _T_1989) node _T_2019 = or(_T_2018, _T_1994) node _T_2020 = or(_T_2019, _T_1999) node _T_2021 = or(_T_2020, _T_2004) node _T_2022 = or(_T_2021, _T_2009) node _T_2023 = or(_T_2022, _T_2014) node _T_2024 = and(_T_1964, _T_2023) node _T_2025 = or(UInt<1>(0h0), _T_2024) node _T_2026 = and(_WIRE_7, _T_2025) node _T_2027 = asUInt(reset) node _T_2028 = eq(_T_2027, UInt<1>(0h0)) when _T_2028 : node _T_2029 = eq(_T_2026, UInt<1>(0h0)) when _T_2029 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_2026, UInt<1>(0h1), "") : assert_144 node _T_2030 = asUInt(reset) node _T_2031 = eq(_T_2030, UInt<1>(0h0)) when _T_2031 : node _T_2032 = eq(source_ok_2, UInt<1>(0h0)) when _T_2032 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145 node _T_2033 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2034 = asUInt(reset) node _T_2035 = eq(_T_2034, UInt<1>(0h0)) when _T_2035 : node _T_2036 = eq(_T_2033, UInt<1>(0h0)) when _T_2036 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_2033, UInt<1>(0h1), "") : assert_146 node _T_2037 = asUInt(reset) node _T_2038 = eq(_T_2037, UInt<1>(0h0)) when _T_2038 : node _T_2039 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_2040 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2041 = asUInt(reset) node _T_2042 = eq(_T_2041, UInt<1>(0h0)) when _T_2042 : node _T_2043 = eq(_T_2040, UInt<1>(0h0)) when _T_2043 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_2040, UInt<1>(0h1), "") : assert_148 node _T_2044 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2045 = asUInt(reset) node _T_2046 = eq(_T_2045, UInt<1>(0h0)) when _T_2046 : node _T_2047 = eq(_T_2044, UInt<1>(0h0)) when _T_2047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_2044, UInt<1>(0h1), "") : assert_149 node _T_2048 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_2048 : node _T_2049 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2050 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2051 = and(_T_2049, _T_2050) node _T_2052 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_2053 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_2054 = eq(io.in.c.bits.source, UInt<2>(0h2)) node _T_2055 = or(_T_2052, _T_2053) node _T_2056 = or(_T_2055, _T_2054) node _T_2057 = and(_T_2051, _T_2056) node _T_2058 = or(UInt<1>(0h0), _T_2057) node _T_2059 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_2060 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2061 = cvt(_T_2060) node _T_2062 = and(_T_2061, asSInt(UInt<14>(0h2000))) node _T_2063 = asSInt(_T_2062) node _T_2064 = eq(_T_2063, asSInt(UInt<1>(0h0))) node _T_2065 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2066 = cvt(_T_2065) node _T_2067 = and(_T_2066, asSInt(UInt<13>(0h1000))) node _T_2068 = asSInt(_T_2067) node _T_2069 = eq(_T_2068, asSInt(UInt<1>(0h0))) node _T_2070 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2071 = cvt(_T_2070) node _T_2072 = and(_T_2071, asSInt(UInt<17>(0h10000))) node _T_2073 = asSInt(_T_2072) node _T_2074 = eq(_T_2073, asSInt(UInt<1>(0h0))) node _T_2075 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2076 = cvt(_T_2075) node _T_2077 = and(_T_2076, asSInt(UInt<18>(0h2f000))) node _T_2078 = asSInt(_T_2077) node _T_2079 = eq(_T_2078, asSInt(UInt<1>(0h0))) node _T_2080 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2081 = cvt(_T_2080) node _T_2082 = and(_T_2081, asSInt(UInt<17>(0h10000))) node _T_2083 = asSInt(_T_2082) node _T_2084 = eq(_T_2083, asSInt(UInt<1>(0h0))) node _T_2085 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2086 = cvt(_T_2085) node _T_2087 = and(_T_2086, asSInt(UInt<13>(0h1000))) node _T_2088 = asSInt(_T_2087) node _T_2089 = eq(_T_2088, asSInt(UInt<1>(0h0))) node _T_2090 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2091 = cvt(_T_2090) node _T_2092 = and(_T_2091, asSInt(UInt<27>(0h4000000))) node _T_2093 = asSInt(_T_2092) node _T_2094 = eq(_T_2093, asSInt(UInt<1>(0h0))) node _T_2095 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2096 = cvt(_T_2095) node _T_2097 = and(_T_2096, asSInt(UInt<13>(0h1000))) node _T_2098 = asSInt(_T_2097) node _T_2099 = eq(_T_2098, asSInt(UInt<1>(0h0))) node _T_2100 = or(_T_2064, _T_2069) node _T_2101 = or(_T_2100, _T_2074) node _T_2102 = or(_T_2101, _T_2079) node _T_2103 = or(_T_2102, _T_2084) node _T_2104 = or(_T_2103, _T_2089) node _T_2105 = or(_T_2104, _T_2094) node _T_2106 = or(_T_2105, _T_2099) node _T_2107 = and(_T_2059, _T_2106) node _T_2108 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2109 = or(UInt<1>(0h0), _T_2108) node _T_2110 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2111 = cvt(_T_2110) node _T_2112 = and(_T_2111, asSInt(UInt<17>(0h10000))) node _T_2113 = asSInt(_T_2112) node _T_2114 = eq(_T_2113, asSInt(UInt<1>(0h0))) node _T_2115 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2116 = cvt(_T_2115) node _T_2117 = and(_T_2116, asSInt(UInt<29>(0h10000000))) node _T_2118 = asSInt(_T_2117) node _T_2119 = eq(_T_2118, asSInt(UInt<1>(0h0))) node _T_2120 = or(_T_2114, _T_2119) node _T_2121 = and(_T_2109, _T_2120) node _T_2122 = or(UInt<1>(0h0), _T_2107) node _T_2123 = or(_T_2122, _T_2121) node _T_2124 = and(_T_2058, _T_2123) node _T_2125 = asUInt(reset) node _T_2126 = eq(_T_2125, UInt<1>(0h0)) when _T_2126 : node _T_2127 = eq(_T_2124, UInt<1>(0h0)) when _T_2127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_2124, UInt<1>(0h1), "") : assert_150 node _T_2128 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_2129 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_2130 = eq(io.in.c.bits.source, UInt<2>(0h2)) wire _WIRE_8 : UInt<1>[3] connect _WIRE_8[0], _T_2128 connect _WIRE_8[1], _T_2129 connect _WIRE_8[2], _T_2130 node _T_2131 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2132 = mux(_WIRE_8[0], _T_2131, UInt<1>(0h0)) node _T_2133 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2134 = mux(_WIRE_8[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_2135 = or(_T_2132, _T_2133) node _T_2136 = or(_T_2135, _T_2134) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_2136 node _T_2137 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2138 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2139 = and(_T_2137, _T_2138) node _T_2140 = or(UInt<1>(0h0), _T_2139) node _T_2141 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2142 = cvt(_T_2141) node _T_2143 = and(_T_2142, asSInt(UInt<14>(0h2000))) node _T_2144 = asSInt(_T_2143) node _T_2145 = eq(_T_2144, asSInt(UInt<1>(0h0))) node _T_2146 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2147 = cvt(_T_2146) node _T_2148 = and(_T_2147, asSInt(UInt<13>(0h1000))) node _T_2149 = asSInt(_T_2148) node _T_2150 = eq(_T_2149, asSInt(UInt<1>(0h0))) node _T_2151 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2152 = cvt(_T_2151) node _T_2153 = and(_T_2152, asSInt(UInt<17>(0h10000))) node _T_2154 = asSInt(_T_2153) node _T_2155 = eq(_T_2154, asSInt(UInt<1>(0h0))) node _T_2156 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2157 = cvt(_T_2156) node _T_2158 = and(_T_2157, asSInt(UInt<18>(0h2f000))) node _T_2159 = asSInt(_T_2158) node _T_2160 = eq(_T_2159, asSInt(UInt<1>(0h0))) node _T_2161 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2162 = cvt(_T_2161) node _T_2163 = and(_T_2162, asSInt(UInt<17>(0h10000))) node _T_2164 = asSInt(_T_2163) node _T_2165 = eq(_T_2164, asSInt(UInt<1>(0h0))) node _T_2166 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2167 = cvt(_T_2166) node _T_2168 = and(_T_2167, asSInt(UInt<13>(0h1000))) node _T_2169 = asSInt(_T_2168) node _T_2170 = eq(_T_2169, asSInt(UInt<1>(0h0))) node _T_2171 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2172 = cvt(_T_2171) node _T_2173 = and(_T_2172, asSInt(UInt<17>(0h10000))) node _T_2174 = asSInt(_T_2173) node _T_2175 = eq(_T_2174, asSInt(UInt<1>(0h0))) node _T_2176 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2177 = cvt(_T_2176) node _T_2178 = and(_T_2177, asSInt(UInt<27>(0h4000000))) node _T_2179 = asSInt(_T_2178) node _T_2180 = eq(_T_2179, asSInt(UInt<1>(0h0))) node _T_2181 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2182 = cvt(_T_2181) node _T_2183 = and(_T_2182, asSInt(UInt<13>(0h1000))) node _T_2184 = asSInt(_T_2183) node _T_2185 = eq(_T_2184, asSInt(UInt<1>(0h0))) node _T_2186 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2187 = cvt(_T_2186) node _T_2188 = and(_T_2187, asSInt(UInt<29>(0h10000000))) node _T_2189 = asSInt(_T_2188) node _T_2190 = eq(_T_2189, asSInt(UInt<1>(0h0))) node _T_2191 = or(_T_2145, _T_2150) node _T_2192 = or(_T_2191, _T_2155) node _T_2193 = or(_T_2192, _T_2160) node _T_2194 = or(_T_2193, _T_2165) node _T_2195 = or(_T_2194, _T_2170) node _T_2196 = or(_T_2195, _T_2175) node _T_2197 = or(_T_2196, _T_2180) node _T_2198 = or(_T_2197, _T_2185) node _T_2199 = or(_T_2198, _T_2190) node _T_2200 = and(_T_2140, _T_2199) node _T_2201 = or(UInt<1>(0h0), _T_2200) node _T_2202 = and(_WIRE_9, _T_2201) node _T_2203 = asUInt(reset) node _T_2204 = eq(_T_2203, UInt<1>(0h0)) when _T_2204 : node _T_2205 = eq(_T_2202, UInt<1>(0h0)) when _T_2205 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_2202, UInt<1>(0h1), "") : assert_151 node _T_2206 = asUInt(reset) node _T_2207 = eq(_T_2206, UInt<1>(0h0)) when _T_2207 : node _T_2208 = eq(source_ok_2, UInt<1>(0h0)) when _T_2208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152 node _T_2209 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2210 = asUInt(reset) node _T_2211 = eq(_T_2210, UInt<1>(0h0)) when _T_2211 : node _T_2212 = eq(_T_2209, UInt<1>(0h0)) when _T_2212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_2209, UInt<1>(0h1), "") : assert_153 node _T_2213 = asUInt(reset) node _T_2214 = eq(_T_2213, UInt<1>(0h0)) when _T_2214 : node _T_2215 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2215 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_2216 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2217 = asUInt(reset) node _T_2218 = eq(_T_2217, UInt<1>(0h0)) when _T_2218 : node _T_2219 = eq(_T_2216, UInt<1>(0h0)) when _T_2219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_2216, UInt<1>(0h1), "") : assert_155 node _T_2220 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_2220 : node _T_2221 = asUInt(reset) node _T_2222 = eq(_T_2221, UInt<1>(0h0)) when _T_2222 : node _T_2223 = eq(address_ok_1, UInt<1>(0h0)) when _T_2223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_2224 = asUInt(reset) node _T_2225 = eq(_T_2224, UInt<1>(0h0)) when _T_2225 : node _T_2226 = eq(source_ok_2, UInt<1>(0h0)) when _T_2226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157 node _T_2227 = asUInt(reset) node _T_2228 = eq(_T_2227, UInt<1>(0h0)) when _T_2228 : node _T_2229 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2229 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_2230 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2231 = asUInt(reset) node _T_2232 = eq(_T_2231, UInt<1>(0h0)) when _T_2232 : node _T_2233 = eq(_T_2230, UInt<1>(0h0)) when _T_2233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_2230, UInt<1>(0h1), "") : assert_159 node _T_2234 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2235 = asUInt(reset) node _T_2236 = eq(_T_2235, UInt<1>(0h0)) when _T_2236 : node _T_2237 = eq(_T_2234, UInt<1>(0h0)) when _T_2237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_2234, UInt<1>(0h1), "") : assert_160 node _T_2238 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_2238 : node _T_2239 = asUInt(reset) node _T_2240 = eq(_T_2239, UInt<1>(0h0)) when _T_2240 : node _T_2241 = eq(address_ok_1, UInt<1>(0h0)) when _T_2241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_2242 = asUInt(reset) node _T_2243 = eq(_T_2242, UInt<1>(0h0)) when _T_2243 : node _T_2244 = eq(source_ok_2, UInt<1>(0h0)) when _T_2244 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162 node _T_2245 = asUInt(reset) node _T_2246 = eq(_T_2245, UInt<1>(0h0)) when _T_2246 : node _T_2247 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_2248 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2249 = asUInt(reset) node _T_2250 = eq(_T_2249, UInt<1>(0h0)) when _T_2250 : node _T_2251 = eq(_T_2248, UInt<1>(0h0)) when _T_2251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_2248, UInt<1>(0h1), "") : assert_164 node _T_2252 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_2252 : node _T_2253 = asUInt(reset) node _T_2254 = eq(_T_2253, UInt<1>(0h0)) when _T_2254 : node _T_2255 = eq(address_ok_1, UInt<1>(0h0)) when _T_2255 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_2256 = asUInt(reset) node _T_2257 = eq(_T_2256, UInt<1>(0h0)) when _T_2257 : node _T_2258 = eq(source_ok_2, UInt<1>(0h0)) when _T_2258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166 node _T_2259 = asUInt(reset) node _T_2260 = eq(_T_2259, UInt<1>(0h0)) when _T_2260 : node _T_2261 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_2262 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2263 = asUInt(reset) node _T_2264 = eq(_T_2263, UInt<1>(0h0)) when _T_2264 : node _T_2265 = eq(_T_2262, UInt<1>(0h0)) when _T_2265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_2262, UInt<1>(0h1), "") : assert_168 node _T_2266 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2267 = asUInt(reset) node _T_2268 = eq(_T_2267, UInt<1>(0h0)) when _T_2268 : node _T_2269 = eq(_T_2266, UInt<1>(0h0)) when _T_2269 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_2266, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0h8)) node _T_2270 = asUInt(reset) node _T_2271 = eq(_T_2270, UInt<1>(0h0)) when _T_2271 : node _T_2272 = eq(sink_ok_1, UInt<1>(0h0)) when _T_2272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2273 = eq(a_first, UInt<1>(0h0)) node _T_2274 = and(io.in.a.valid, _T_2273) when _T_2274 : node _T_2275 = eq(io.in.a.bits.opcode, opcode) node _T_2276 = asUInt(reset) node _T_2277 = eq(_T_2276, UInt<1>(0h0)) when _T_2277 : node _T_2278 = eq(_T_2275, UInt<1>(0h0)) when _T_2278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_2275, UInt<1>(0h1), "") : assert_171 node _T_2279 = eq(io.in.a.bits.param, param) node _T_2280 = asUInt(reset) node _T_2281 = eq(_T_2280, UInt<1>(0h0)) when _T_2281 : node _T_2282 = eq(_T_2279, UInt<1>(0h0)) when _T_2282 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_2279, UInt<1>(0h1), "") : assert_172 node _T_2283 = eq(io.in.a.bits.size, size) node _T_2284 = asUInt(reset) node _T_2285 = eq(_T_2284, UInt<1>(0h0)) when _T_2285 : node _T_2286 = eq(_T_2283, UInt<1>(0h0)) when _T_2286 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_2283, UInt<1>(0h1), "") : assert_173 node _T_2287 = eq(io.in.a.bits.source, source) node _T_2288 = asUInt(reset) node _T_2289 = eq(_T_2288, UInt<1>(0h0)) when _T_2289 : node _T_2290 = eq(_T_2287, UInt<1>(0h0)) when _T_2290 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_2287, UInt<1>(0h1), "") : assert_174 node _T_2291 = eq(io.in.a.bits.address, address) node _T_2292 = asUInt(reset) node _T_2293 = eq(_T_2292, UInt<1>(0h0)) when _T_2293 : node _T_2294 = eq(_T_2291, UInt<1>(0h0)) when _T_2294 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_2291, UInt<1>(0h1), "") : assert_175 node _T_2295 = and(io.in.a.ready, io.in.a.valid) node _T_2296 = and(_T_2295, a_first) when _T_2296 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2297 = eq(d_first, UInt<1>(0h0)) node _T_2298 = and(io.in.d.valid, _T_2297) when _T_2298 : node _T_2299 = eq(io.in.d.bits.opcode, opcode_1) node _T_2300 = asUInt(reset) node _T_2301 = eq(_T_2300, UInt<1>(0h0)) when _T_2301 : node _T_2302 = eq(_T_2299, UInt<1>(0h0)) when _T_2302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_2299, UInt<1>(0h1), "") : assert_176 node _T_2303 = eq(io.in.d.bits.param, param_1) node _T_2304 = asUInt(reset) node _T_2305 = eq(_T_2304, UInt<1>(0h0)) when _T_2305 : node _T_2306 = eq(_T_2303, UInt<1>(0h0)) when _T_2306 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_2303, UInt<1>(0h1), "") : assert_177 node _T_2307 = eq(io.in.d.bits.size, size_1) node _T_2308 = asUInt(reset) node _T_2309 = eq(_T_2308, UInt<1>(0h0)) when _T_2309 : node _T_2310 = eq(_T_2307, UInt<1>(0h0)) when _T_2310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_2307, UInt<1>(0h1), "") : assert_178 node _T_2311 = eq(io.in.d.bits.source, source_1) node _T_2312 = asUInt(reset) node _T_2313 = eq(_T_2312, UInt<1>(0h0)) when _T_2313 : node _T_2314 = eq(_T_2311, UInt<1>(0h0)) when _T_2314 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_2311, UInt<1>(0h1), "") : assert_179 node _T_2315 = eq(io.in.d.bits.sink, sink) node _T_2316 = asUInt(reset) node _T_2317 = eq(_T_2316, UInt<1>(0h0)) when _T_2317 : node _T_2318 = eq(_T_2315, UInt<1>(0h0)) when _T_2318 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_2315, UInt<1>(0h1), "") : assert_180 node _T_2319 = eq(io.in.d.bits.denied, denied) node _T_2320 = asUInt(reset) node _T_2321 = eq(_T_2320, UInt<1>(0h0)) when _T_2321 : node _T_2322 = eq(_T_2319, UInt<1>(0h0)) when _T_2322 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_2319, UInt<1>(0h1), "") : assert_181 node _T_2323 = and(io.in.d.ready, io.in.d.valid) node _T_2324 = and(_T_2323, d_first) when _T_2324 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 11, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_2325 = eq(b_first, UInt<1>(0h0)) node _T_2326 = and(io.in.b.valid, _T_2325) when _T_2326 : node _T_2327 = eq(io.in.b.bits.opcode, opcode_2) node _T_2328 = asUInt(reset) node _T_2329 = eq(_T_2328, UInt<1>(0h0)) when _T_2329 : node _T_2330 = eq(_T_2327, UInt<1>(0h0)) when _T_2330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_2327, UInt<1>(0h1), "") : assert_182 node _T_2331 = eq(io.in.b.bits.param, param_2) node _T_2332 = asUInt(reset) node _T_2333 = eq(_T_2332, UInt<1>(0h0)) when _T_2333 : node _T_2334 = eq(_T_2331, UInt<1>(0h0)) when _T_2334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_2331, UInt<1>(0h1), "") : assert_183 node _T_2335 = eq(io.in.b.bits.size, size_2) node _T_2336 = asUInt(reset) node _T_2337 = eq(_T_2336, UInt<1>(0h0)) when _T_2337 : node _T_2338 = eq(_T_2335, UInt<1>(0h0)) when _T_2338 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_2335, UInt<1>(0h1), "") : assert_184 node _T_2339 = eq(io.in.b.bits.source, source_2) node _T_2340 = asUInt(reset) node _T_2341 = eq(_T_2340, UInt<1>(0h0)) when _T_2341 : node _T_2342 = eq(_T_2339, UInt<1>(0h0)) when _T_2342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_2339, UInt<1>(0h1), "") : assert_185 node _T_2343 = eq(io.in.b.bits.address, address_1) node _T_2344 = asUInt(reset) node _T_2345 = eq(_T_2344, UInt<1>(0h0)) when _T_2345 : node _T_2346 = eq(_T_2343, UInt<1>(0h0)) when _T_2346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_2343, UInt<1>(0h1), "") : assert_186 node _T_2347 = and(io.in.b.ready, io.in.b.valid) node _T_2348 = and(_T_2347, b_first) when _T_2348 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_2349 = eq(c_first, UInt<1>(0h0)) node _T_2350 = and(io.in.c.valid, _T_2349) when _T_2350 : node _T_2351 = eq(io.in.c.bits.opcode, opcode_3) node _T_2352 = asUInt(reset) node _T_2353 = eq(_T_2352, UInt<1>(0h0)) when _T_2353 : node _T_2354 = eq(_T_2351, UInt<1>(0h0)) when _T_2354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_2351, UInt<1>(0h1), "") : assert_187 node _T_2355 = eq(io.in.c.bits.param, param_3) node _T_2356 = asUInt(reset) node _T_2357 = eq(_T_2356, UInt<1>(0h0)) when _T_2357 : node _T_2358 = eq(_T_2355, UInt<1>(0h0)) when _T_2358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_2355, UInt<1>(0h1), "") : assert_188 node _T_2359 = eq(io.in.c.bits.size, size_3) node _T_2360 = asUInt(reset) node _T_2361 = eq(_T_2360, UInt<1>(0h0)) when _T_2361 : node _T_2362 = eq(_T_2359, UInt<1>(0h0)) when _T_2362 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_2359, UInt<1>(0h1), "") : assert_189 node _T_2363 = eq(io.in.c.bits.source, source_3) node _T_2364 = asUInt(reset) node _T_2365 = eq(_T_2364, UInt<1>(0h0)) when _T_2365 : node _T_2366 = eq(_T_2363, UInt<1>(0h0)) when _T_2366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_2363, UInt<1>(0h1), "") : assert_190 node _T_2367 = eq(io.in.c.bits.address, address_2) node _T_2368 = asUInt(reset) node _T_2369 = eq(_T_2368, UInt<1>(0h0)) when _T_2369 : node _T_2370 = eq(_T_2367, UInt<1>(0h0)) when _T_2370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_2367, UInt<1>(0h1), "") : assert_191 node _T_2371 = and(io.in.c.ready, io.in.c.valid) node _T_2372 = and(_T_2371, c_first) when _T_2372 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<3>, clock, reset, UInt<3>(0h0) regreset inflight_opcodes : UInt<12>, clock, reset, UInt<12>(0h0) regreset inflight_sizes : UInt<24>, clock, reset, UInt<24>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<3> connect a_set, UInt<3>(0h0) wire a_set_wo_ready : UInt<3> connect a_set_wo_ready, UInt<3>(0h0) wire a_opcodes_set : UInt<12> connect a_opcodes_set, UInt<12>(0h0) wire a_sizes_set : UInt<24> connect a_sizes_set, UInt<24>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_2373 = and(io.in.a.valid, a_first_1) node _T_2374 = and(_T_2373, UInt<1>(0h1)) when _T_2374 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2375 = and(io.in.a.ready, io.in.a.valid) node _T_2376 = and(_T_2375, a_first_1) node _T_2377 = and(_T_2376, UInt<1>(0h1)) when _T_2377 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2378 = dshr(inflight, io.in.a.bits.source) node _T_2379 = bits(_T_2378, 0, 0) node _T_2380 = eq(_T_2379, UInt<1>(0h0)) node _T_2381 = asUInt(reset) node _T_2382 = eq(_T_2381, UInt<1>(0h0)) when _T_2382 : node _T_2383 = eq(_T_2380, UInt<1>(0h0)) when _T_2383 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_2380, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<3> connect d_clr, UInt<3>(0h0) wire d_clr_wo_ready : UInt<3> connect d_clr_wo_ready, UInt<3>(0h0) wire d_opcodes_clr : UInt<12> connect d_opcodes_clr, UInt<12>(0h0) wire d_sizes_clr : UInt<24> connect d_sizes_clr, UInt<24>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2384 = and(io.in.d.valid, d_first_1) node _T_2385 = and(_T_2384, UInt<1>(0h1)) node _T_2386 = eq(d_release_ack, UInt<1>(0h0)) node _T_2387 = and(_T_2385, _T_2386) when _T_2387 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2388 = and(io.in.d.ready, io.in.d.valid) node _T_2389 = and(_T_2388, d_first_1) node _T_2390 = and(_T_2389, UInt<1>(0h1)) node _T_2391 = eq(d_release_ack, UInt<1>(0h0)) node _T_2392 = and(_T_2390, _T_2391) when _T_2392 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2393 = and(io.in.d.valid, d_first_1) node _T_2394 = and(_T_2393, UInt<1>(0h1)) node _T_2395 = eq(d_release_ack, UInt<1>(0h0)) node _T_2396 = and(_T_2394, _T_2395) when _T_2396 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2397 = dshr(inflight, io.in.d.bits.source) node _T_2398 = bits(_T_2397, 0, 0) node _T_2399 = or(_T_2398, same_cycle_resp) node _T_2400 = asUInt(reset) node _T_2401 = eq(_T_2400, UInt<1>(0h0)) when _T_2401 : node _T_2402 = eq(_T_2399, UInt<1>(0h0)) when _T_2402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_2399, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_2403 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2404 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2405 = or(_T_2403, _T_2404) node _T_2406 = asUInt(reset) node _T_2407 = eq(_T_2406, UInt<1>(0h0)) when _T_2407 : node _T_2408 = eq(_T_2405, UInt<1>(0h0)) when _T_2408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_2405, UInt<1>(0h1), "") : assert_194 node _T_2409 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2410 = asUInt(reset) node _T_2411 = eq(_T_2410, UInt<1>(0h0)) when _T_2411 : node _T_2412 = eq(_T_2409, UInt<1>(0h0)) when _T_2412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_2409, UInt<1>(0h1), "") : assert_195 else : node _T_2413 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2414 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2415 = or(_T_2413, _T_2414) node _T_2416 = asUInt(reset) node _T_2417 = eq(_T_2416, UInt<1>(0h0)) when _T_2417 : node _T_2418 = eq(_T_2415, UInt<1>(0h0)) when _T_2418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_2415, UInt<1>(0h1), "") : assert_196 node _T_2419 = eq(io.in.d.bits.size, a_size_lookup) node _T_2420 = asUInt(reset) node _T_2421 = eq(_T_2420, UInt<1>(0h0)) when _T_2421 : node _T_2422 = eq(_T_2419, UInt<1>(0h0)) when _T_2422 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_2419, UInt<1>(0h1), "") : assert_197 node _T_2423 = and(io.in.d.valid, d_first_1) node _T_2424 = and(_T_2423, a_first_1) node _T_2425 = and(_T_2424, io.in.a.valid) node _T_2426 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2427 = and(_T_2425, _T_2426) node _T_2428 = eq(d_release_ack, UInt<1>(0h0)) node _T_2429 = and(_T_2427, _T_2428) when _T_2429 : node _T_2430 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2431 = or(_T_2430, io.in.a.ready) node _T_2432 = asUInt(reset) node _T_2433 = eq(_T_2432, UInt<1>(0h0)) when _T_2433 : node _T_2434 = eq(_T_2431, UInt<1>(0h0)) when _T_2434 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_2431, UInt<1>(0h1), "") : assert_198 node _T_2435 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_2436 = orr(a_set_wo_ready) node _T_2437 = eq(_T_2436, UInt<1>(0h0)) node _T_2438 = or(_T_2435, _T_2437) node _T_2439 = asUInt(reset) node _T_2440 = eq(_T_2439, UInt<1>(0h0)) when _T_2440 : node _T_2441 = eq(_T_2438, UInt<1>(0h0)) when _T_2441 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_2438, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_81 node _T_2442 = orr(inflight) node _T_2443 = eq(_T_2442, UInt<1>(0h0)) node _T_2444 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2445 = or(_T_2443, _T_2444) node _T_2446 = lt(watchdog, plusarg_reader.out) node _T_2447 = or(_T_2445, _T_2446) node _T_2448 = asUInt(reset) node _T_2449 = eq(_T_2448, UInt<1>(0h0)) when _T_2449 : node _T_2450 = eq(_T_2447, UInt<1>(0h0)) when _T_2450 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_2447, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2451 = and(io.in.a.ready, io.in.a.valid) node _T_2452 = and(io.in.d.ready, io.in.d.valid) node _T_2453 = or(_T_2451, _T_2452) when _T_2453 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<3>, clock, reset, UInt<3>(0h0) regreset inflight_opcodes_1 : UInt<12>, clock, reset, UInt<12>(0h0) regreset inflight_sizes_1 : UInt<24>, clock, reset, UInt<24>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 11, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<3> connect c_set, UInt<3>(0h0) wire c_set_wo_ready : UInt<3> connect c_set_wo_ready, UInt<3>(0h0) wire c_opcodes_set : UInt<12> connect c_opcodes_set, UInt<12>(0h0) wire c_sizes_set : UInt<24> connect c_sizes_set, UInt<24>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) node _T_2454 = and(io.in.c.valid, c_first_1) node _T_2455 = bits(io.in.c.bits.opcode, 2, 2) node _T_2456 = bits(io.in.c.bits.opcode, 1, 1) node _T_2457 = and(_T_2455, _T_2456) node _T_2458 = and(_T_2454, _T_2457) when _T_2458 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_2459 = and(io.in.c.ready, io.in.c.valid) node _T_2460 = and(_T_2459, c_first_1) node _T_2461 = bits(io.in.c.bits.opcode, 2, 2) node _T_2462 = bits(io.in.c.bits.opcode, 1, 1) node _T_2463 = and(_T_2461, _T_2462) node _T_2464 = and(_T_2460, _T_2463) when _T_2464 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_2465 = dshr(inflight_1, io.in.c.bits.source) node _T_2466 = bits(_T_2465, 0, 0) node _T_2467 = eq(_T_2466, UInt<1>(0h0)) node _T_2468 = asUInt(reset) node _T_2469 = eq(_T_2468, UInt<1>(0h0)) when _T_2469 : node _T_2470 = eq(_T_2467, UInt<1>(0h0)) when _T_2470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_2467, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<3> connect d_clr_1, UInt<3>(0h0) wire d_clr_wo_ready_1 : UInt<3> connect d_clr_wo_ready_1, UInt<3>(0h0) wire d_opcodes_clr_1 : UInt<12> connect d_opcodes_clr_1, UInt<12>(0h0) wire d_sizes_clr_1 : UInt<24> connect d_sizes_clr_1, UInt<24>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2471 = and(io.in.d.valid, d_first_2) node _T_2472 = and(_T_2471, UInt<1>(0h1)) node _T_2473 = and(_T_2472, d_release_ack_1) when _T_2473 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2474 = and(io.in.d.ready, io.in.d.valid) node _T_2475 = and(_T_2474, d_first_2) node _T_2476 = and(_T_2475, UInt<1>(0h1)) node _T_2477 = and(_T_2476, d_release_ack_1) when _T_2477 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2478 = and(io.in.d.valid, d_first_2) node _T_2479 = and(_T_2478, UInt<1>(0h1)) node _T_2480 = and(_T_2479, d_release_ack_1) when _T_2480 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2481 = dshr(inflight_1, io.in.d.bits.source) node _T_2482 = bits(_T_2481, 0, 0) node _T_2483 = or(_T_2482, same_cycle_resp_1) node _T_2484 = asUInt(reset) node _T_2485 = eq(_T_2484, UInt<1>(0h0)) when _T_2485 : node _T_2486 = eq(_T_2483, UInt<1>(0h0)) when _T_2486 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_2483, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_2487 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_2488 = asUInt(reset) node _T_2489 = eq(_T_2488, UInt<1>(0h0)) when _T_2489 : node _T_2490 = eq(_T_2487, UInt<1>(0h0)) when _T_2490 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_2487, UInt<1>(0h1), "") : assert_203 else : node _T_2491 = eq(io.in.d.bits.size, c_size_lookup) node _T_2492 = asUInt(reset) node _T_2493 = eq(_T_2492, UInt<1>(0h0)) when _T_2493 : node _T_2494 = eq(_T_2491, UInt<1>(0h0)) when _T_2494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_2491, UInt<1>(0h1), "") : assert_204 node _T_2495 = and(io.in.d.valid, d_first_2) node _T_2496 = and(_T_2495, c_first_1) node _T_2497 = and(_T_2496, io.in.c.valid) node _T_2498 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_2499 = and(_T_2497, _T_2498) node _T_2500 = and(_T_2499, d_release_ack_1) node _T_2501 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2502 = and(_T_2500, _T_2501) when _T_2502 : node _T_2503 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2504 = or(_T_2503, io.in.c.ready) node _T_2505 = asUInt(reset) node _T_2506 = eq(_T_2505, UInt<1>(0h0)) when _T_2506 : node _T_2507 = eq(_T_2504, UInt<1>(0h0)) when _T_2507 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_2504, UInt<1>(0h1), "") : assert_205 node _T_2508 = orr(c_set_wo_ready) when _T_2508 : node _T_2509 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_2510 = asUInt(reset) node _T_2511 = eq(_T_2510, UInt<1>(0h0)) when _T_2511 : node _T_2512 = eq(_T_2509, UInt<1>(0h0)) when _T_2512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_2509, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_82 node _T_2513 = orr(inflight_1) node _T_2514 = eq(_T_2513, UInt<1>(0h0)) node _T_2515 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2516 = or(_T_2514, _T_2515) node _T_2517 = lt(watchdog_1, plusarg_reader_1.out) node _T_2518 = or(_T_2516, _T_2517) node _T_2519 = asUInt(reset) node _T_2520 = eq(_T_2519, UInt<1>(0h0)) when _T_2520 : node _T_2521 = eq(_T_2518, UInt<1>(0h0)) when _T_2521 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_2518, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_2522 = and(io.in.c.ready, io.in.c.valid) node _T_2523 = and(io.in.d.ready, io.in.d.valid) node _T_2524 = or(_T_2522, _T_2523) when _T_2524 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 11, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<8> connect d_set, UInt<8>(0h0) node _T_2525 = and(io.in.d.ready, io.in.d.valid) node _T_2526 = and(_T_2525, d_first_3) node _T_2527 = bits(io.in.d.bits.opcode, 2, 2) node _T_2528 = bits(io.in.d.bits.opcode, 1, 1) node _T_2529 = eq(_T_2528, UInt<1>(0h0)) node _T_2530 = and(_T_2527, _T_2529) node _T_2531 = and(_T_2526, _T_2530) when _T_2531 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_2532 = dshr(inflight_2, io.in.d.bits.sink) node _T_2533 = bits(_T_2532, 0, 0) node _T_2534 = eq(_T_2533, UInt<1>(0h0)) node _T_2535 = asUInt(reset) node _T_2536 = eq(_T_2535, UInt<1>(0h0)) when _T_2536 : node _T_2537 = eq(_T_2534, UInt<1>(0h0)) when _T_2537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_2534, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<8> connect e_clr, UInt<8>(0h0) node _T_2538 = and(io.in.e.ready, io.in.e.valid) node _T_2539 = and(_T_2538, UInt<1>(0h1)) node _T_2540 = and(_T_2539, UInt<1>(0h1)) when _T_2540 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_2541 = or(d_set, inflight_2) node _T_2542 = dshr(_T_2541, io.in.e.bits.sink) node _T_2543 = bits(_T_2542, 0, 0) node _T_2544 = asUInt(reset) node _T_2545 = eq(_T_2544, UInt<1>(0h0)) when _T_2545 : node _T_2546 = eq(_T_2543, UInt<1>(0h0)) when _T_2546 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_2543, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8
module TLMonitor_40( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [2:0] io_in_b_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_b_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_b_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_b_bits_data, // @[Monitor.scala:20:14] input io_in_b_bits_corrupt, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_ready, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_opcode_0 = io_in_b_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_b_bits_size_0 = io_in_b_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_b_bits_mask_0 = io_in_b_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_b_bits_data_0 = io_in_b_bits_data; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt_0 = io_in_b_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_ready_0 = io_in_e_ready; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _legal_source_T_3 = 1'h0; // @[Mux.scala:30:73] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [8:0] b_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] b_first_count = 9'h0; // @[Edges.scala:234:25] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _mask_sizeOH_T_3 = io_in_b_bits_size_0; // @[Misc.scala:202:34] wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_70 = io_in_c_bits_address_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 2'h0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire _source_ok_T_1 = io_in_a_bits_source_0 == 2'h1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire _source_ok_T_2 = io_in_a_bits_source_0 == 2'h2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2 = _source_ok_T_2; // @[Parameters.scala:1138:31] wire _source_ok_T_3 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_3 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_T_4 = io_in_d_bits_source_0 == 2'h0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_4; // @[Parameters.scala:1138:31] wire _source_ok_T_5 = io_in_d_bits_source_0 == 2'h1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_1 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire _source_ok_T_6 = io_in_d_bits_source_0 == 2'h2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_2 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire _source_ok_T_7 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_7 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _legal_source_T = io_in_b_bits_source_0 == 2'h0; // @[Monitor.scala:36:7] wire _legal_source_T_1 = io_in_b_bits_source_0 == 2'h1; // @[Monitor.scala:36:7] wire _legal_source_T_2 = io_in_b_bits_source_0 == 2'h2; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40] wire [20:0] _GEN_2 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:21], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46] wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46] wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40] wire [25:0] _GEN_3 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:26], _GEN_3}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46] wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40] wire [25:0] _GEN_4 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:26], _GEN_4}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46] wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40] wire [27:0] _GEN_5 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:28], _GEN_5}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46] wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40] wire [27:0] _GEN_6 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:28], _GEN_6}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46] wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40] wire [28:0] _GEN_7 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:29], _GEN_7}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46] wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_55 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46] wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40] wire _address_ok_T_60 = _address_ok_WIRE_0 | _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_61 = _address_ok_T_60 | _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_62 = _address_ok_T_61 | _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_63 = _address_ok_T_62 | _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_64 = _address_ok_T_63 | _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_65 = _address_ok_T_64 | _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_66 = _address_ok_T_65 | _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_67 = _address_ok_T_66 | _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_68 = _address_ok_T_67 | _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_69 = _address_ok_T_68 | _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64] wire address_ok = _address_ok_T_69 | _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64] wire [26:0] _GEN_8 = 27'hFFF << io_in_b_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_2; // @[package.scala:243:71] assign _is_aligned_mask_T_2 = _GEN_8; // @[package.scala:243:71] wire [26:0] _b_first_beats1_decode_T; // @[package.scala:243:71] assign _b_first_beats1_decode_T = _GEN_8; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_3 = _is_aligned_mask_T_2[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_1 = ~_is_aligned_mask_T_3; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_1 = {20'h0, io_in_b_bits_address_0[11:0] & is_aligned_mask_1}; // @[package.scala:243:46] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount_1 = _mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_4 = 4'h1 << mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_5 = _mask_sizeOH_T_4[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH_1 = {_mask_sizeOH_T_5[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1_1 = io_in_b_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size_1 = mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size_1 & mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1_1 = mask_sub_sub_sub_0_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size_1 & mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1_1 = mask_sub_sub_sub_0_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size_1 = mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size_1 & mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1_1 = mask_sub_sub_0_1_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size_1 & mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1_1 = mask_sub_sub_0_1_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size_1 & mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1_1 = mask_sub_sub_1_1_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size_1 & mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1_1 = mask_sub_sub_1_1_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size_1 = mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size_1 & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_0_1_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size_1 & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_0_1_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size_1 & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_1_1_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size_1 & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_1_1_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size_1 & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_2_1_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size_1 & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_2_1_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size_1 & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_3_1_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size_1 & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_3_1_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_1 = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_1 = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_1 = {mask_lo_hi_1, mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_1 = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_1 = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_1 = {mask_hi_hi_1, mask_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] mask_1 = {mask_hi_1, mask_lo_1}; // @[Misc.scala:222:10] wire _legal_source_WIRE_0 = _legal_source_T; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_1 = _legal_source_T_1; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_2 = _legal_source_T_2; // @[Parameters.scala:1138:31] wire _legal_source_T_4 = _legal_source_WIRE_1; // @[Mux.scala:30:73] wire _legal_source_T_6 = _legal_source_T_4; // @[Mux.scala:30:73] wire [1:0] _legal_source_T_5 = {_legal_source_WIRE_2, 1'h0}; // @[Mux.scala:30:73] wire [1:0] _legal_source_T_7 = {1'h0, _legal_source_T_6} | _legal_source_T_5; // @[Mux.scala:30:73] wire [1:0] _legal_source_WIRE_1_0 = _legal_source_T_7; // @[Mux.scala:30:73] wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73] wire _source_ok_T_8 = io_in_c_bits_source_0 == 2'h0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_0 = _source_ok_T_8; // @[Parameters.scala:1138:31] wire _source_ok_T_9 = io_in_c_bits_source_0 == 2'h1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_1 = _source_ok_T_9; // @[Parameters.scala:1138:31] wire _source_ok_T_10 = io_in_c_bits_source_0 == 2'h2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_2 = _source_ok_T_10; // @[Parameters.scala:1138:31] wire _source_ok_T_11 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_2 = _source_ok_T_11 | _source_ok_WIRE_2_2; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN_9 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_9; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46] wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_74; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_75 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46] wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_79; // @[Parameters.scala:612:40] wire [13:0] _GEN_10 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_80 = {io_in_c_bits_address_0[31:14], _GEN_10}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46] wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_2 = _address_ok_T_84; // @[Parameters.scala:612:40] wire [16:0] _GEN_11 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_85 = {io_in_c_bits_address_0[31:17], _GEN_11}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_86 = {1'h0, _address_ok_T_85}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_87 = _address_ok_T_86 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_88 = _address_ok_T_87; // @[Parameters.scala:137:46] wire _address_ok_T_89 = _address_ok_T_88 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_3 = _address_ok_T_89; // @[Parameters.scala:612:40] wire [20:0] _GEN_12 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_90 = {io_in_c_bits_address_0[31:21], _GEN_12}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_91 = {1'h0, _address_ok_T_90}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_92 = _address_ok_T_91 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_93 = _address_ok_T_92; // @[Parameters.scala:137:46] wire _address_ok_T_94 = _address_ok_T_93 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_4 = _address_ok_T_94; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_95 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_96 = {1'h0, _address_ok_T_95}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_97 = _address_ok_T_96 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_98 = _address_ok_T_97; // @[Parameters.scala:137:46] wire _address_ok_T_99 = _address_ok_T_98 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_5 = _address_ok_T_99; // @[Parameters.scala:612:40] wire [25:0] _GEN_13 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_100 = {io_in_c_bits_address_0[31:26], _GEN_13}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46] wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_6 = _address_ok_T_104; // @[Parameters.scala:612:40] wire [25:0] _GEN_14 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:26], _GEN_14}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46] wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_7 = _address_ok_T_109; // @[Parameters.scala:612:40] wire [27:0] _GEN_15 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:28], _GEN_15}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46] wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_8 = _address_ok_T_114; // @[Parameters.scala:612:40] wire [27:0] _GEN_16 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:28], _GEN_16}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46] wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_9 = _address_ok_T_119; // @[Parameters.scala:612:40] wire [28:0] _GEN_17 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:29], _GEN_17}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46] wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_10 = _address_ok_T_124; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_125 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46] wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_11 = _address_ok_T_129; // @[Parameters.scala:612:40] wire _address_ok_T_130 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_131 = _address_ok_T_130 | _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_132 = _address_ok_T_131 | _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_133 = _address_ok_T_132 | _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_134 = _address_ok_T_133 | _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_135 = _address_ok_T_134 | _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_136 = _address_ok_T_135 | _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_137 = _address_ok_T_136 | _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_138 = _address_ok_T_137 | _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_139 = _address_ok_T_138 | _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64] wire address_ok_1 = _address_ok_T_139 | _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64] wire _T_2451 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2451; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2451; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [1:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2525 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2525; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2525; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2525; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2525; // @[Decoupled.scala:51:35] wire [26:0] _GEN_18 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_18; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [1:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] wire [11:0] _b_first_beats1_decode_T_1 = _b_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _b_first_beats1_decode_T_2 = ~_b_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] b_first_beats1_decode = _b_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _b_first_beats1_opdata_T = io_in_b_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire b_first_beats1_opdata = ~_b_first_beats1_opdata_T; // @[Edges.scala:97:{28,37}] reg [8:0] b_first_counter; // @[Edges.scala:229:27] wire [9:0] _b_first_counter1_T = {1'h0, b_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] b_first_counter1 = _b_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] _b_first_counter_T = b_first ? 9'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_2; // @[Monitor.scala:410:22] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [3:0] size_2; // @[Monitor.scala:412:22] reg [1:0] source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2522 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2522; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2522; // @[Decoupled.scala:51:35] wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T = {1'h0, c_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1 = _c_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg [1:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [2:0] inflight; // @[Monitor.scala:614:27] reg [11:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [23:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [2:0] a_set; // @[Monitor.scala:626:34] wire [2:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [11:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [23:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [4:0] _GEN_19 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [4:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69] wire [4:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_19; // @[Monitor.scala:637:69, :680:101] wire [4:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69, :749:69] wire [4:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_19; // @[Monitor.scala:637:69, :790:101] wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {4'h0, _a_opcode_lookup_T_1 & 12'hF}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4:0] _GEN_20 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [4:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65] wire [4:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_20; // @[Monitor.scala:641:65, :681:99] wire [4:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65, :750:67] wire [4:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_20; // @[Monitor.scala:641:65, :791:99] wire [23:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [23:0] _a_size_lookup_T_6 = {16'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [23:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[23:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [3:0] _GEN_21 = 4'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [3:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_21; // @[OneHot.scala:58:35] wire [3:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_21; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2377 = _T_2451 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2377 ? _a_set_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2377 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2377 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [4:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [34:0] _a_opcodes_set_T_1 = {31'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2377 ? _a_opcodes_set_T_1[11:0] : 12'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [4:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [35:0] _a_sizes_set_T_1 = {31'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_2377 ? _a_sizes_set_T_1[23:0] : 24'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [2:0] d_clr; // @[Monitor.scala:664:34] wire [2:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [11:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [23:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_22 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_22; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_22; // @[Monitor.scala:673:46, :783:46] wire _T_2423 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [3:0] _GEN_23 = 4'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [3:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_23; // @[OneHot.scala:58:35] wire [3:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_23; // @[OneHot.scala:58:35] wire [3:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_23; // @[OneHot.scala:58:35] wire [3:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_23; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2423 & ~d_release_ack ? _d_clr_wo_ready_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2392 = _T_2525 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2392 ? _d_clr_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [46:0] _d_opcodes_clr_T_5 = 47'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2392 ? _d_opcodes_clr_T_5[11:0] : 12'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [46:0] _d_sizes_clr_T_5 = 47'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2392 ? _d_sizes_clr_T_5[23:0] : 24'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [2:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [11:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [23:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [23:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [23:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [2:0] inflight_1; // @[Monitor.scala:726:35] reg [11:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [23:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1_1 = _c_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [2:0] c_set; // @[Monitor.scala:738:34] wire [2:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [11:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [23:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [11:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {4'h0, _c_opcode_lookup_T_1 & 12'hF}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [23:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [23:0] _c_size_lookup_T_6 = {16'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [23:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[23:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [3:0] _GEN_24 = 4'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35] wire [3:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_24; // @[OneHot.scala:58:35] wire [3:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_24; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2464 = _T_2522 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2464 ? _c_set_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2464 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2464 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [4:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [34:0] _c_opcodes_set_T_1 = {31'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_2464 ? _c_opcodes_set_T_1[11:0] : 12'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [4:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77] wire [35:0] _c_sizes_set_T_1 = {31'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_2464 ? _c_sizes_set_T_1[23:0] : 24'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [2:0] d_clr_1; // @[Monitor.scala:774:34] wire [2:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [11:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [23:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2495 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2495 & d_release_ack_1 ? _d_clr_wo_ready_T_1[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2477 = _T_2525 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2477 ? _d_clr_T_1[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [46:0] _d_opcodes_clr_T_11 = 47'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2477 ? _d_opcodes_clr_T_11[11:0] : 12'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [46:0] _d_sizes_clr_T_11 = 47'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2477 ? _d_sizes_clr_T_11[23:0] : 24'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [2:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [2:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [2:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [11:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [11:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [11:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [23:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [23:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [23:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [7:0] inflight_2; // @[Monitor.scala:828:27] wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_3; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_3 = _d_first_counter1_T_3[8:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [7:0] d_set; // @[Monitor.scala:833:25] wire _T_2531 = _T_2525 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [7:0] _GEN_25 = {5'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _d_set_T = 8'h1 << _GEN_25; // @[OneHot.scala:58:35] assign d_set = _T_2531 ? _d_set_T : 8'h0; // @[OneHot.scala:58:35] wire [7:0] e_clr; // @[Monitor.scala:839:25] wire _T_2540 = io_in_e_ready_0 & io_in_e_valid_0; // @[Decoupled.scala:51:35] wire [7:0] _GEN_26 = {5'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _e_clr_T = 8'h1 << _GEN_26; // @[OneHot.scala:58:35] assign e_clr = _T_2540 ? _e_clr_T : 8'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetRegVec_w2_i0_11 : input clock : Clock input reset : Reset output io : { flip d : UInt<2>, q : UInt<2>, flip en : UInt<1>} node _reg_T = asAsyncReset(reset) regreset reg : UInt<2>, clock, _reg_T, UInt<2>(0h0) when io.en : connect reg, io.d connect io.q, reg
module AsyncResetRegVec_w2_i0_11( // @[AsyncResetReg.scala:56:7] input clock, // @[AsyncResetReg.scala:56:7] input reset, // @[AsyncResetReg.scala:56:7] input [1:0] io_d, // @[AsyncResetReg.scala:59:14] output [1:0] io_q // @[AsyncResetReg.scala:59:14] ); wire [1:0] io_d_0 = io_d; // @[AsyncResetReg.scala:56:7] wire _reg_T = reset; // @[AsyncResetReg.scala:61:29] wire io_en = 1'h1; // @[AsyncResetReg.scala:56:7, :59:14] wire [1:0] io_q_0; // @[AsyncResetReg.scala:56:7] reg [1:0] reg_0; // @[AsyncResetReg.scala:61:50] assign io_q_0 = reg_0; // @[AsyncResetReg.scala:56:7, :61:50] always @(posedge clock or posedge _reg_T) begin // @[AsyncResetReg.scala:56:7, :61:29] if (_reg_T) // @[AsyncResetReg.scala:56:7, :61:29] reg_0 <= 2'h0; // @[AsyncResetReg.scala:61:50] else // @[AsyncResetReg.scala:56:7] reg_0 <= io_d_0; // @[AsyncResetReg.scala:56:7, :61:50] always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_7 : input clock : Clock input reset : Reset output io : { flip d : UInt<4>, q : UInt<4>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_90 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q node _output_T_2 = asAsyncReset(reset) node _output_T_3 = bits(io.d, 1, 1) inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_91 connect output_chain_1.clock, clock connect output_chain_1.reset, _output_T_2 connect output_chain_1.io.d, _output_T_3 wire output_1 : UInt<1> connect output_1, output_chain_1.io.q node _output_T_4 = asAsyncReset(reset) node _output_T_5 = bits(io.d, 2, 2) inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_92 connect output_chain_2.clock, clock connect output_chain_2.reset, _output_T_4 connect output_chain_2.io.d, _output_T_5 wire output_2 : UInt<1> connect output_2, output_chain_2.io.q node _output_T_6 = asAsyncReset(reset) node _output_T_7 = bits(io.d, 3, 3) inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_93 connect output_chain_3.clock, clock connect output_chain_3.reset, _output_T_6 connect output_chain_3.io.d, _output_T_7 wire output_3 : UInt<1> connect output_3, output_chain_3.io.q node io_q_lo = cat(output_1, output_0) node io_q_hi = cat(output_3, output_2) node _io_q_T = cat(io_q_hi, io_q_lo) connect io.q, _io_q_T
module AsyncResetSynchronizerShiftReg_w4_d3_i0_7( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_90 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_91 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_92 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_93 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_451 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_195 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<32>, clock reg c2 : SInt<32>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node c1_sign = bits(io.in_d, 19, 19) node c1_lo_lo_hi = cat(c1_sign, c1_sign) node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign) node c1_lo_hi_hi = cat(c1_sign, c1_sign) node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign) node c1_lo = cat(c1_lo_hi, c1_lo_lo) node c1_hi_lo_hi = cat(c1_sign, c1_sign) node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign) node c1_hi_hi_hi = cat(c1_sign, c1_sign) node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign) node c1_hi = cat(c1_hi_hi, c1_hi_lo) node _c1_T = cat(c1_hi, c1_lo) node c1_lo_1 = asUInt(io.in_d) node _c1_T_1 = cat(_c1_T, c1_lo_1) wire _c1_WIRE : SInt<32> node _c1_T_2 = asSInt(_c1_T_1) connect _c1_WIRE, _c1_T_2 connect c1, _c1_WIRE else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node c2_sign = bits(io.in_d, 19, 19) node c2_lo_lo_hi = cat(c2_sign, c2_sign) node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign) node c2_lo_hi_hi = cat(c2_sign, c2_sign) node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign) node c2_lo = cat(c2_lo_hi, c2_lo_lo) node c2_hi_lo_hi = cat(c2_sign, c2_sign) node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign) node c2_hi_hi_hi = cat(c2_sign, c2_sign) node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign) node c2_hi = cat(c2_hi_hi, c2_hi_lo) node _c2_T = cat(c2_hi, c2_lo) node c2_lo_1 = asUInt(io.in_d) node _c2_T_1 = cat(_c2_T, c2_lo_1) wire _c2_WIRE : SInt<32> node _c2_T_2 = asSInt(_c2_T_1) connect _c2_WIRE, _c2_T_2 connect c2, _c2_WIRE else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h1), _T_4) node _T_6 = or(UInt<1>(0h0), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c
module PE_451( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_195 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_460 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_204 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<32>, clock reg c2 : SInt<32>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node c1_sign = bits(io.in_d, 19, 19) node c1_lo_lo_hi = cat(c1_sign, c1_sign) node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign) node c1_lo_hi_hi = cat(c1_sign, c1_sign) node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign) node c1_lo = cat(c1_lo_hi, c1_lo_lo) node c1_hi_lo_hi = cat(c1_sign, c1_sign) node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign) node c1_hi_hi_hi = cat(c1_sign, c1_sign) node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign) node c1_hi = cat(c1_hi_hi, c1_hi_lo) node _c1_T = cat(c1_hi, c1_lo) node c1_lo_1 = asUInt(io.in_d) node _c1_T_1 = cat(_c1_T, c1_lo_1) wire _c1_WIRE : SInt<32> node _c1_T_2 = asSInt(_c1_T_1) connect _c1_WIRE, _c1_T_2 connect c1, _c1_WIRE else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node c2_sign = bits(io.in_d, 19, 19) node c2_lo_lo_hi = cat(c2_sign, c2_sign) node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign) node c2_lo_hi_hi = cat(c2_sign, c2_sign) node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign) node c2_lo = cat(c2_lo_hi, c2_lo_lo) node c2_hi_lo_hi = cat(c2_sign, c2_sign) node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign) node c2_hi_hi_hi = cat(c2_sign, c2_sign) node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign) node c2_hi = cat(c2_hi_hi, c2_hi_lo) node _c2_T = cat(c2_hi, c2_lo) node c2_lo_1 = asUInt(io.in_d) node _c2_T_1 = cat(_c2_T, c2_lo_1) wire _c2_WIRE : SInt<32> node _c2_T_2 = asSInt(_c2_T_1) connect _c2_WIRE, _c2_T_2 connect c2, _c2_WIRE else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h1), _T_4) node _T_6 = or(UInt<1>(0h0), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c
module PE_460( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_204 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_69 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}}, flip vcalloc_resp : { vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, flip out_credit_available : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<3>, sa_stall : UInt<3>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}} inst input_buffer of InputBuffer_69 connect input_buffer.clock, clock connect input_buffer.reset, reset connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head connect input_buffer.io.enq[0].valid, io.in.flit[0].valid connect input_buffer.io.deq[0].ready, UInt<1>(0h0) connect input_buffer.io.deq[1].ready, UInt<1>(0h0) connect input_buffer.io.deq[2].ready, UInt<1>(0h0) connect input_buffer.io.deq[3].ready, UInt<1>(0h0) connect input_buffer.io.deq[4].ready, UInt<1>(0h0) connect input_buffer.io.deq[5].ready, UInt<1>(0h0) connect input_buffer.io.deq[6].ready, UInt<1>(0h0) connect input_buffer.io.deq[7].ready, UInt<1>(0h0) inst route_arbiter of Arbiter8_RouteComputerReq_69 connect route_arbiter.clock, clock connect route_arbiter.reset, reset connect io.router_req.bits, route_arbiter.io.out.bits connect io.router_req.valid, route_arbiter.io.out.valid connect route_arbiter.io.out.ready, io.router_req.ready reg states : { g : UInt<3>, vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, fifo_deps : UInt<8>}[8], clock node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T : node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<4>(0h8)) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0)) node _T_6 = asUInt(reset) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(_T_5, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1 assert(clock, _T_5, UInt<1>(0h1), "") : assert_1 node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<5>(0h1e)) node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1)) connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow connect route_arbiter.io.in[0].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[0].bits.flow.egress_node_id invalidate route_arbiter.io.in[0].bits.flow.egress_node invalidate route_arbiter.io.in[0].bits.flow.ingress_node_id invalidate route_arbiter.io.in[0].bits.flow.ingress_node invalidate route_arbiter.io.in[0].bits.flow.vnet_id invalidate route_arbiter.io.in[0].bits.src_virt_id node _route_arbiter_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h1)) connect route_arbiter.io.in[1].valid, _route_arbiter_io_in_1_valid_T connect route_arbiter.io.in[1].bits.flow.egress_node_id, states[1].flow.egress_node_id connect route_arbiter.io.in[1].bits.flow.egress_node, states[1].flow.egress_node connect route_arbiter.io.in[1].bits.flow.ingress_node_id, states[1].flow.ingress_node_id connect route_arbiter.io.in[1].bits.flow.ingress_node, states[1].flow.ingress_node connect route_arbiter.io.in[1].bits.flow.vnet_id, states[1].flow.vnet_id connect route_arbiter.io.in[1].bits.src_virt_id, UInt<1>(0h1) node _T_9 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid) when _T_9 : connect states[1].g, UInt<3>(0h2) node _route_arbiter_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h1)) connect route_arbiter.io.in[2].valid, _route_arbiter_io_in_2_valid_T connect route_arbiter.io.in[2].bits.flow.egress_node_id, states[2].flow.egress_node_id connect route_arbiter.io.in[2].bits.flow.egress_node, states[2].flow.egress_node connect route_arbiter.io.in[2].bits.flow.ingress_node_id, states[2].flow.ingress_node_id connect route_arbiter.io.in[2].bits.flow.ingress_node, states[2].flow.ingress_node connect route_arbiter.io.in[2].bits.flow.vnet_id, states[2].flow.vnet_id connect route_arbiter.io.in[2].bits.src_virt_id, UInt<2>(0h2) node _T_10 = and(route_arbiter.io.in[2].ready, route_arbiter.io.in[2].valid) when _T_10 : connect states[2].g, UInt<3>(0h2) node _route_arbiter_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h1)) connect route_arbiter.io.in[3].valid, _route_arbiter_io_in_3_valid_T connect route_arbiter.io.in[3].bits.flow.egress_node_id, states[3].flow.egress_node_id connect route_arbiter.io.in[3].bits.flow.egress_node, states[3].flow.egress_node connect route_arbiter.io.in[3].bits.flow.ingress_node_id, states[3].flow.ingress_node_id connect route_arbiter.io.in[3].bits.flow.ingress_node, states[3].flow.ingress_node connect route_arbiter.io.in[3].bits.flow.vnet_id, states[3].flow.vnet_id connect route_arbiter.io.in[3].bits.src_virt_id, UInt<2>(0h3) node _T_11 = and(route_arbiter.io.in[3].ready, route_arbiter.io.in[3].valid) when _T_11 : connect states[3].g, UInt<3>(0h2) node _route_arbiter_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h1)) connect route_arbiter.io.in[4].valid, _route_arbiter_io_in_4_valid_T connect route_arbiter.io.in[4].bits.flow.egress_node_id, states[4].flow.egress_node_id connect route_arbiter.io.in[4].bits.flow.egress_node, states[4].flow.egress_node connect route_arbiter.io.in[4].bits.flow.ingress_node_id, states[4].flow.ingress_node_id connect route_arbiter.io.in[4].bits.flow.ingress_node, states[4].flow.ingress_node connect route_arbiter.io.in[4].bits.flow.vnet_id, states[4].flow.vnet_id connect route_arbiter.io.in[4].bits.src_virt_id, UInt<3>(0h4) node _T_12 = and(route_arbiter.io.in[4].ready, route_arbiter.io.in[4].valid) when _T_12 : connect states[4].g, UInt<3>(0h2) node _route_arbiter_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h1)) connect route_arbiter.io.in[5].valid, _route_arbiter_io_in_5_valid_T connect route_arbiter.io.in[5].bits.flow.egress_node_id, states[5].flow.egress_node_id connect route_arbiter.io.in[5].bits.flow.egress_node, states[5].flow.egress_node connect route_arbiter.io.in[5].bits.flow.ingress_node_id, states[5].flow.ingress_node_id connect route_arbiter.io.in[5].bits.flow.ingress_node, states[5].flow.ingress_node connect route_arbiter.io.in[5].bits.flow.vnet_id, states[5].flow.vnet_id connect route_arbiter.io.in[5].bits.src_virt_id, UInt<3>(0h5) node _T_13 = and(route_arbiter.io.in[5].ready, route_arbiter.io.in[5].valid) when _T_13 : connect states[5].g, UInt<3>(0h2) node _route_arbiter_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h1)) connect route_arbiter.io.in[6].valid, _route_arbiter_io_in_6_valid_T connect route_arbiter.io.in[6].bits.flow.egress_node_id, states[6].flow.egress_node_id connect route_arbiter.io.in[6].bits.flow.egress_node, states[6].flow.egress_node connect route_arbiter.io.in[6].bits.flow.ingress_node_id, states[6].flow.ingress_node_id connect route_arbiter.io.in[6].bits.flow.ingress_node, states[6].flow.ingress_node connect route_arbiter.io.in[6].bits.flow.vnet_id, states[6].flow.vnet_id connect route_arbiter.io.in[6].bits.src_virt_id, UInt<3>(0h6) node _T_14 = and(route_arbiter.io.in[6].ready, route_arbiter.io.in[6].valid) when _T_14 : connect states[6].g, UInt<3>(0h2) node _route_arbiter_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h1)) connect route_arbiter.io.in[7].valid, _route_arbiter_io_in_7_valid_T connect route_arbiter.io.in[7].bits.flow.egress_node_id, states[7].flow.egress_node_id connect route_arbiter.io.in[7].bits.flow.egress_node, states[7].flow.egress_node connect route_arbiter.io.in[7].bits.flow.ingress_node_id, states[7].flow.ingress_node_id connect route_arbiter.io.in[7].bits.flow.ingress_node, states[7].flow.ingress_node connect route_arbiter.io.in[7].bits.flow.vnet_id, states[7].flow.vnet_id connect route_arbiter.io.in[7].bits.src_virt_id, UInt<3>(0h7) node _T_15 = and(route_arbiter.io.in[7].ready, route_arbiter.io.in[7].valid) when _T_15 : connect states[7].g, UInt<3>(0h2) node _T_16 = and(io.router_req.ready, io.router_req.valid) when _T_16 : node _T_17 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1)) node _T_18 = asUInt(reset) node _T_19 = eq(_T_18, UInt<1>(0h0)) when _T_19 : node _T_20 = eq(_T_17, UInt<1>(0h0)) when _T_20 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2 assert(clock, _T_17, UInt<1>(0h1), "") : assert_2 connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2) node _T_21 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id) when _T_21 : connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_22 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id) when _T_22 : connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_23 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id) when _T_23 : connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[2].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_24 = eq(UInt<2>(0h3), io.router_req.bits.src_virt_id) when _T_24 : connect states[3].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[3].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[3].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_25 = eq(UInt<3>(0h4), io.router_req.bits.src_virt_id) when _T_25 : connect states[4].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[4].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[4].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_26 = eq(UInt<3>(0h5), io.router_req.bits.src_virt_id) when _T_26 : connect states[5].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[5].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[5].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[5].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_27 = eq(UInt<3>(0h6), io.router_req.bits.src_virt_id) when _T_27 : connect states[6].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[6].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[6].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[6].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_28 = eq(UInt<3>(0h7), io.router_req.bits.src_virt_id) when _T_28 : connect states[7].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[7].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[7].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[7].vc_sel.`3`, io.router_resp.vc_sel.`3` regreset mask : UInt<8>, clock, reset, UInt<8>(0h0) wire vcalloc_reqs : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}[8] wire vcalloc_vals : UInt<1>[8] node vcalloc_filter_lo_lo = cat(vcalloc_vals[1], vcalloc_vals[0]) node vcalloc_filter_lo_hi = cat(vcalloc_vals[3], vcalloc_vals[2]) node vcalloc_filter_lo = cat(vcalloc_filter_lo_hi, vcalloc_filter_lo_lo) node vcalloc_filter_hi_lo = cat(vcalloc_vals[5], vcalloc_vals[4]) node vcalloc_filter_hi_hi = cat(vcalloc_vals[7], vcalloc_vals[6]) node vcalloc_filter_hi = cat(vcalloc_filter_hi_hi, vcalloc_filter_hi_lo) node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_filter_lo) node vcalloc_filter_lo_lo_1 = cat(vcalloc_vals[1], vcalloc_vals[0]) node vcalloc_filter_lo_hi_1 = cat(vcalloc_vals[3], vcalloc_vals[2]) node vcalloc_filter_lo_1 = cat(vcalloc_filter_lo_hi_1, vcalloc_filter_lo_lo_1) node vcalloc_filter_hi_lo_1 = cat(vcalloc_vals[5], vcalloc_vals[4]) node vcalloc_filter_hi_hi_1 = cat(vcalloc_vals[7], vcalloc_vals[6]) node vcalloc_filter_hi_1 = cat(vcalloc_filter_hi_hi_1, vcalloc_filter_hi_lo_1) node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_filter_lo_1) node _vcalloc_filter_T_2 = not(mask) node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2) node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3) node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0) node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1) node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2) node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3) node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4) node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5) node _vcalloc_filter_T_11 = bits(_vcalloc_filter_T_4, 6, 6) node _vcalloc_filter_T_12 = bits(_vcalloc_filter_T_4, 7, 7) node _vcalloc_filter_T_13 = bits(_vcalloc_filter_T_4, 8, 8) node _vcalloc_filter_T_14 = bits(_vcalloc_filter_T_4, 9, 9) node _vcalloc_filter_T_15 = bits(_vcalloc_filter_T_4, 10, 10) node _vcalloc_filter_T_16 = bits(_vcalloc_filter_T_4, 11, 11) node _vcalloc_filter_T_17 = bits(_vcalloc_filter_T_4, 12, 12) node _vcalloc_filter_T_18 = bits(_vcalloc_filter_T_4, 13, 13) node _vcalloc_filter_T_19 = bits(_vcalloc_filter_T_4, 14, 14) node _vcalloc_filter_T_20 = bits(_vcalloc_filter_T_4, 15, 15) node _vcalloc_filter_T_21 = mux(_vcalloc_filter_T_20, UInt<16>(0h8000), UInt<16>(0h0)) node _vcalloc_filter_T_22 = mux(_vcalloc_filter_T_19, UInt<16>(0h4000), _vcalloc_filter_T_21) node _vcalloc_filter_T_23 = mux(_vcalloc_filter_T_18, UInt<16>(0h2000), _vcalloc_filter_T_22) node _vcalloc_filter_T_24 = mux(_vcalloc_filter_T_17, UInt<16>(0h1000), _vcalloc_filter_T_23) node _vcalloc_filter_T_25 = mux(_vcalloc_filter_T_16, UInt<16>(0h800), _vcalloc_filter_T_24) node _vcalloc_filter_T_26 = mux(_vcalloc_filter_T_15, UInt<16>(0h400), _vcalloc_filter_T_25) node _vcalloc_filter_T_27 = mux(_vcalloc_filter_T_14, UInt<16>(0h200), _vcalloc_filter_T_26) node _vcalloc_filter_T_28 = mux(_vcalloc_filter_T_13, UInt<16>(0h100), _vcalloc_filter_T_27) node _vcalloc_filter_T_29 = mux(_vcalloc_filter_T_12, UInt<16>(0h80), _vcalloc_filter_T_28) node _vcalloc_filter_T_30 = mux(_vcalloc_filter_T_11, UInt<16>(0h40), _vcalloc_filter_T_29) node _vcalloc_filter_T_31 = mux(_vcalloc_filter_T_10, UInt<16>(0h20), _vcalloc_filter_T_30) node _vcalloc_filter_T_32 = mux(_vcalloc_filter_T_9, UInt<16>(0h10), _vcalloc_filter_T_31) node _vcalloc_filter_T_33 = mux(_vcalloc_filter_T_8, UInt<16>(0h8), _vcalloc_filter_T_32) node _vcalloc_filter_T_34 = mux(_vcalloc_filter_T_7, UInt<16>(0h4), _vcalloc_filter_T_33) node _vcalloc_filter_T_35 = mux(_vcalloc_filter_T_6, UInt<16>(0h2), _vcalloc_filter_T_34) node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<16>(0h1), _vcalloc_filter_T_35) node _vcalloc_sel_T = bits(vcalloc_filter, 7, 0) node _vcalloc_sel_T_1 = shr(vcalloc_filter, 8) node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1) node _T_29 = and(io.router_req.ready, io.router_req.valid) when _T_29 : node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id) node _mask_T_1 = sub(_mask_T, UInt<1>(0h1)) node _mask_T_2 = tail(_mask_T_1, 1) connect mask, _mask_T_2 else : node _T_30 = or(vcalloc_vals[0], vcalloc_vals[1]) node _T_31 = or(_T_30, vcalloc_vals[2]) node _T_32 = or(_T_31, vcalloc_vals[3]) node _T_33 = or(_T_32, vcalloc_vals[4]) node _T_34 = or(_T_33, vcalloc_vals[5]) node _T_35 = or(_T_34, vcalloc_vals[6]) node _T_36 = or(_T_35, vcalloc_vals[7]) when _T_36 : node _mask_T_3 = not(UInt<1>(0h0)) node _mask_T_4 = not(UInt<2>(0h0)) node _mask_T_5 = not(UInt<3>(0h0)) node _mask_T_6 = not(UInt<4>(0h0)) node _mask_T_7 = not(UInt<5>(0h0)) node _mask_T_8 = not(UInt<6>(0h0)) node _mask_T_9 = not(UInt<7>(0h0)) node _mask_T_10 = not(UInt<8>(0h0)) node _mask_T_11 = bits(vcalloc_sel, 0, 0) node _mask_T_12 = bits(vcalloc_sel, 1, 1) node _mask_T_13 = bits(vcalloc_sel, 2, 2) node _mask_T_14 = bits(vcalloc_sel, 3, 3) node _mask_T_15 = bits(vcalloc_sel, 4, 4) node _mask_T_16 = bits(vcalloc_sel, 5, 5) node _mask_T_17 = bits(vcalloc_sel, 6, 6) node _mask_T_18 = bits(vcalloc_sel, 7, 7) node _mask_T_19 = mux(_mask_T_11, _mask_T_3, UInt<1>(0h0)) node _mask_T_20 = mux(_mask_T_12, _mask_T_4, UInt<1>(0h0)) node _mask_T_21 = mux(_mask_T_13, _mask_T_5, UInt<1>(0h0)) node _mask_T_22 = mux(_mask_T_14, _mask_T_6, UInt<1>(0h0)) node _mask_T_23 = mux(_mask_T_15, _mask_T_7, UInt<1>(0h0)) node _mask_T_24 = mux(_mask_T_16, _mask_T_8, UInt<1>(0h0)) node _mask_T_25 = mux(_mask_T_17, _mask_T_9, UInt<1>(0h0)) node _mask_T_26 = mux(_mask_T_18, _mask_T_10, UInt<1>(0h0)) node _mask_T_27 = or(_mask_T_19, _mask_T_20) node _mask_T_28 = or(_mask_T_27, _mask_T_21) node _mask_T_29 = or(_mask_T_28, _mask_T_22) node _mask_T_30 = or(_mask_T_29, _mask_T_23) node _mask_T_31 = or(_mask_T_30, _mask_T_24) node _mask_T_32 = or(_mask_T_31, _mask_T_25) node _mask_T_33 = or(_mask_T_32, _mask_T_26) wire _mask_WIRE : UInt<8> connect _mask_WIRE, _mask_T_33 connect mask, _mask_WIRE node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1]) node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2]) node _io_vcalloc_req_valid_T_2 = or(_io_vcalloc_req_valid_T_1, vcalloc_vals[3]) node _io_vcalloc_req_valid_T_3 = or(_io_vcalloc_req_valid_T_2, vcalloc_vals[4]) node _io_vcalloc_req_valid_T_4 = or(_io_vcalloc_req_valid_T_3, vcalloc_vals[5]) node _io_vcalloc_req_valid_T_5 = or(_io_vcalloc_req_valid_T_4, vcalloc_vals[6]) node _io_vcalloc_req_valid_T_6 = or(_io_vcalloc_req_valid_T_5, vcalloc_vals[7]) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_6 node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0) node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1) node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2) node _io_vcalloc_req_bits_T_3 = bits(vcalloc_sel, 3, 3) node _io_vcalloc_req_bits_T_4 = bits(vcalloc_sel, 4, 4) node _io_vcalloc_req_bits_T_5 = bits(vcalloc_sel, 5, 5) node _io_vcalloc_req_bits_T_6 = bits(vcalloc_sel, 6, 6) node _io_vcalloc_req_bits_T_7 = bits(vcalloc_sel, 7, 7) wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}} wire _io_vcalloc_req_bits_WIRE_1 : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]} wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[8] node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_11 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_12 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_13 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_8, _io_vcalloc_req_bits_T_9) node _io_vcalloc_req_bits_T_17 = or(_io_vcalloc_req_bits_T_16, _io_vcalloc_req_bits_T_10) node _io_vcalloc_req_bits_T_18 = or(_io_vcalloc_req_bits_T_17, _io_vcalloc_req_bits_T_11) node _io_vcalloc_req_bits_T_19 = or(_io_vcalloc_req_bits_T_18, _io_vcalloc_req_bits_T_12) node _io_vcalloc_req_bits_T_20 = or(_io_vcalloc_req_bits_T_19, _io_vcalloc_req_bits_T_13) node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_20, _io_vcalloc_req_bits_T_14) node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_15) wire _io_vcalloc_req_bits_WIRE_3 : UInt<1> connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_22 connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3 node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_25 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_26 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_27 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_28 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24) node _io_vcalloc_req_bits_T_32 = or(_io_vcalloc_req_bits_T_31, _io_vcalloc_req_bits_T_25) node _io_vcalloc_req_bits_T_33 = or(_io_vcalloc_req_bits_T_32, _io_vcalloc_req_bits_T_26) node _io_vcalloc_req_bits_T_34 = or(_io_vcalloc_req_bits_T_33, _io_vcalloc_req_bits_T_27) node _io_vcalloc_req_bits_T_35 = or(_io_vcalloc_req_bits_T_34, _io_vcalloc_req_bits_T_28) node _io_vcalloc_req_bits_T_36 = or(_io_vcalloc_req_bits_T_35, _io_vcalloc_req_bits_T_29) node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_36, _io_vcalloc_req_bits_T_30) wire _io_vcalloc_req_bits_WIRE_4 : UInt<1> connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_37 connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4 node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_40 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_41 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_42 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_43 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_45 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_39) node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_40) node _io_vcalloc_req_bits_T_48 = or(_io_vcalloc_req_bits_T_47, _io_vcalloc_req_bits_T_41) node _io_vcalloc_req_bits_T_49 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_42) node _io_vcalloc_req_bits_T_50 = or(_io_vcalloc_req_bits_T_49, _io_vcalloc_req_bits_T_43) node _io_vcalloc_req_bits_T_51 = or(_io_vcalloc_req_bits_T_50, _io_vcalloc_req_bits_T_44) node _io_vcalloc_req_bits_T_52 = or(_io_vcalloc_req_bits_T_51, _io_vcalloc_req_bits_T_45) wire _io_vcalloc_req_bits_WIRE_5 : UInt<1> connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_52 connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5 node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_56 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_57 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_58 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_59 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_60 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_61 = or(_io_vcalloc_req_bits_T_53, _io_vcalloc_req_bits_T_54) node _io_vcalloc_req_bits_T_62 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_55) node _io_vcalloc_req_bits_T_63 = or(_io_vcalloc_req_bits_T_62, _io_vcalloc_req_bits_T_56) node _io_vcalloc_req_bits_T_64 = or(_io_vcalloc_req_bits_T_63, _io_vcalloc_req_bits_T_57) node _io_vcalloc_req_bits_T_65 = or(_io_vcalloc_req_bits_T_64, _io_vcalloc_req_bits_T_58) node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_65, _io_vcalloc_req_bits_T_59) node _io_vcalloc_req_bits_T_67 = or(_io_vcalloc_req_bits_T_66, _io_vcalloc_req_bits_T_60) wire _io_vcalloc_req_bits_WIRE_6 : UInt<1> connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_67 connect _io_vcalloc_req_bits_WIRE_2[3], _io_vcalloc_req_bits_WIRE_6 node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_71 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_72 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_73 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_76 = or(_io_vcalloc_req_bits_T_68, _io_vcalloc_req_bits_T_69) node _io_vcalloc_req_bits_T_77 = or(_io_vcalloc_req_bits_T_76, _io_vcalloc_req_bits_T_70) node _io_vcalloc_req_bits_T_78 = or(_io_vcalloc_req_bits_T_77, _io_vcalloc_req_bits_T_71) node _io_vcalloc_req_bits_T_79 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_72) node _io_vcalloc_req_bits_T_80 = or(_io_vcalloc_req_bits_T_79, _io_vcalloc_req_bits_T_73) node _io_vcalloc_req_bits_T_81 = or(_io_vcalloc_req_bits_T_80, _io_vcalloc_req_bits_T_74) node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_81, _io_vcalloc_req_bits_T_75) wire _io_vcalloc_req_bits_WIRE_7 : UInt<1> connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_82 connect _io_vcalloc_req_bits_WIRE_2[4], _io_vcalloc_req_bits_WIRE_7 node _io_vcalloc_req_bits_T_83 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_84 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_85 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_86 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_87 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_88 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_89 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_90 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_91 = or(_io_vcalloc_req_bits_T_83, _io_vcalloc_req_bits_T_84) node _io_vcalloc_req_bits_T_92 = or(_io_vcalloc_req_bits_T_91, _io_vcalloc_req_bits_T_85) node _io_vcalloc_req_bits_T_93 = or(_io_vcalloc_req_bits_T_92, _io_vcalloc_req_bits_T_86) node _io_vcalloc_req_bits_T_94 = or(_io_vcalloc_req_bits_T_93, _io_vcalloc_req_bits_T_87) node _io_vcalloc_req_bits_T_95 = or(_io_vcalloc_req_bits_T_94, _io_vcalloc_req_bits_T_88) node _io_vcalloc_req_bits_T_96 = or(_io_vcalloc_req_bits_T_95, _io_vcalloc_req_bits_T_89) node _io_vcalloc_req_bits_T_97 = or(_io_vcalloc_req_bits_T_96, _io_vcalloc_req_bits_T_90) wire _io_vcalloc_req_bits_WIRE_8 : UInt<1> connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_97 connect _io_vcalloc_req_bits_WIRE_2[5], _io_vcalloc_req_bits_WIRE_8 node _io_vcalloc_req_bits_T_98 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_99 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_100 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_101 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_102 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_103 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_104 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_105 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_106 = or(_io_vcalloc_req_bits_T_98, _io_vcalloc_req_bits_T_99) node _io_vcalloc_req_bits_T_107 = or(_io_vcalloc_req_bits_T_106, _io_vcalloc_req_bits_T_100) node _io_vcalloc_req_bits_T_108 = or(_io_vcalloc_req_bits_T_107, _io_vcalloc_req_bits_T_101) node _io_vcalloc_req_bits_T_109 = or(_io_vcalloc_req_bits_T_108, _io_vcalloc_req_bits_T_102) node _io_vcalloc_req_bits_T_110 = or(_io_vcalloc_req_bits_T_109, _io_vcalloc_req_bits_T_103) node _io_vcalloc_req_bits_T_111 = or(_io_vcalloc_req_bits_T_110, _io_vcalloc_req_bits_T_104) node _io_vcalloc_req_bits_T_112 = or(_io_vcalloc_req_bits_T_111, _io_vcalloc_req_bits_T_105) wire _io_vcalloc_req_bits_WIRE_9 : UInt<1> connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_112 connect _io_vcalloc_req_bits_WIRE_2[6], _io_vcalloc_req_bits_WIRE_9 node _io_vcalloc_req_bits_T_113 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_114 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_115 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_116 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_117 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_118 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_119 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_120 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_121 = or(_io_vcalloc_req_bits_T_113, _io_vcalloc_req_bits_T_114) node _io_vcalloc_req_bits_T_122 = or(_io_vcalloc_req_bits_T_121, _io_vcalloc_req_bits_T_115) node _io_vcalloc_req_bits_T_123 = or(_io_vcalloc_req_bits_T_122, _io_vcalloc_req_bits_T_116) node _io_vcalloc_req_bits_T_124 = or(_io_vcalloc_req_bits_T_123, _io_vcalloc_req_bits_T_117) node _io_vcalloc_req_bits_T_125 = or(_io_vcalloc_req_bits_T_124, _io_vcalloc_req_bits_T_118) node _io_vcalloc_req_bits_T_126 = or(_io_vcalloc_req_bits_T_125, _io_vcalloc_req_bits_T_119) node _io_vcalloc_req_bits_T_127 = or(_io_vcalloc_req_bits_T_126, _io_vcalloc_req_bits_T_120) wire _io_vcalloc_req_bits_WIRE_10 : UInt<1> connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_127 connect _io_vcalloc_req_bits_WIRE_2[7], _io_vcalloc_req_bits_WIRE_10 connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2 wire _io_vcalloc_req_bits_WIRE_11 : UInt<1>[8] node _io_vcalloc_req_bits_T_128 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_129 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_130 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_131 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_132 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_133 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_134 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_135 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_136 = or(_io_vcalloc_req_bits_T_128, _io_vcalloc_req_bits_T_129) node _io_vcalloc_req_bits_T_137 = or(_io_vcalloc_req_bits_T_136, _io_vcalloc_req_bits_T_130) node _io_vcalloc_req_bits_T_138 = or(_io_vcalloc_req_bits_T_137, _io_vcalloc_req_bits_T_131) node _io_vcalloc_req_bits_T_139 = or(_io_vcalloc_req_bits_T_138, _io_vcalloc_req_bits_T_132) node _io_vcalloc_req_bits_T_140 = or(_io_vcalloc_req_bits_T_139, _io_vcalloc_req_bits_T_133) node _io_vcalloc_req_bits_T_141 = or(_io_vcalloc_req_bits_T_140, _io_vcalloc_req_bits_T_134) node _io_vcalloc_req_bits_T_142 = or(_io_vcalloc_req_bits_T_141, _io_vcalloc_req_bits_T_135) wire _io_vcalloc_req_bits_WIRE_12 : UInt<1> connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_142 connect _io_vcalloc_req_bits_WIRE_11[0], _io_vcalloc_req_bits_WIRE_12 node _io_vcalloc_req_bits_T_143 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_144 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_145 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_146 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_147 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_148 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_149 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_150 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_151 = or(_io_vcalloc_req_bits_T_143, _io_vcalloc_req_bits_T_144) node _io_vcalloc_req_bits_T_152 = or(_io_vcalloc_req_bits_T_151, _io_vcalloc_req_bits_T_145) node _io_vcalloc_req_bits_T_153 = or(_io_vcalloc_req_bits_T_152, _io_vcalloc_req_bits_T_146) node _io_vcalloc_req_bits_T_154 = or(_io_vcalloc_req_bits_T_153, _io_vcalloc_req_bits_T_147) node _io_vcalloc_req_bits_T_155 = or(_io_vcalloc_req_bits_T_154, _io_vcalloc_req_bits_T_148) node _io_vcalloc_req_bits_T_156 = or(_io_vcalloc_req_bits_T_155, _io_vcalloc_req_bits_T_149) node _io_vcalloc_req_bits_T_157 = or(_io_vcalloc_req_bits_T_156, _io_vcalloc_req_bits_T_150) wire _io_vcalloc_req_bits_WIRE_13 : UInt<1> connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_157 connect _io_vcalloc_req_bits_WIRE_11[1], _io_vcalloc_req_bits_WIRE_13 node _io_vcalloc_req_bits_T_158 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_159 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_160 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_161 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_162 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_163 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_164 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_165 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_166 = or(_io_vcalloc_req_bits_T_158, _io_vcalloc_req_bits_T_159) node _io_vcalloc_req_bits_T_167 = or(_io_vcalloc_req_bits_T_166, _io_vcalloc_req_bits_T_160) node _io_vcalloc_req_bits_T_168 = or(_io_vcalloc_req_bits_T_167, _io_vcalloc_req_bits_T_161) node _io_vcalloc_req_bits_T_169 = or(_io_vcalloc_req_bits_T_168, _io_vcalloc_req_bits_T_162) node _io_vcalloc_req_bits_T_170 = or(_io_vcalloc_req_bits_T_169, _io_vcalloc_req_bits_T_163) node _io_vcalloc_req_bits_T_171 = or(_io_vcalloc_req_bits_T_170, _io_vcalloc_req_bits_T_164) node _io_vcalloc_req_bits_T_172 = or(_io_vcalloc_req_bits_T_171, _io_vcalloc_req_bits_T_165) wire _io_vcalloc_req_bits_WIRE_14 : UInt<1> connect _io_vcalloc_req_bits_WIRE_14, _io_vcalloc_req_bits_T_172 connect _io_vcalloc_req_bits_WIRE_11[2], _io_vcalloc_req_bits_WIRE_14 node _io_vcalloc_req_bits_T_173 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_174 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_175 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_176 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_177 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_178 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_179 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_180 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_181 = or(_io_vcalloc_req_bits_T_173, _io_vcalloc_req_bits_T_174) node _io_vcalloc_req_bits_T_182 = or(_io_vcalloc_req_bits_T_181, _io_vcalloc_req_bits_T_175) node _io_vcalloc_req_bits_T_183 = or(_io_vcalloc_req_bits_T_182, _io_vcalloc_req_bits_T_176) node _io_vcalloc_req_bits_T_184 = or(_io_vcalloc_req_bits_T_183, _io_vcalloc_req_bits_T_177) node _io_vcalloc_req_bits_T_185 = or(_io_vcalloc_req_bits_T_184, _io_vcalloc_req_bits_T_178) node _io_vcalloc_req_bits_T_186 = or(_io_vcalloc_req_bits_T_185, _io_vcalloc_req_bits_T_179) node _io_vcalloc_req_bits_T_187 = or(_io_vcalloc_req_bits_T_186, _io_vcalloc_req_bits_T_180) wire _io_vcalloc_req_bits_WIRE_15 : UInt<1> connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_187 connect _io_vcalloc_req_bits_WIRE_11[3], _io_vcalloc_req_bits_WIRE_15 node _io_vcalloc_req_bits_T_188 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_189 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_190 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_191 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_192 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_193 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_194 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_195 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_196 = or(_io_vcalloc_req_bits_T_188, _io_vcalloc_req_bits_T_189) node _io_vcalloc_req_bits_T_197 = or(_io_vcalloc_req_bits_T_196, _io_vcalloc_req_bits_T_190) node _io_vcalloc_req_bits_T_198 = or(_io_vcalloc_req_bits_T_197, _io_vcalloc_req_bits_T_191) node _io_vcalloc_req_bits_T_199 = or(_io_vcalloc_req_bits_T_198, _io_vcalloc_req_bits_T_192) node _io_vcalloc_req_bits_T_200 = or(_io_vcalloc_req_bits_T_199, _io_vcalloc_req_bits_T_193) node _io_vcalloc_req_bits_T_201 = or(_io_vcalloc_req_bits_T_200, _io_vcalloc_req_bits_T_194) node _io_vcalloc_req_bits_T_202 = or(_io_vcalloc_req_bits_T_201, _io_vcalloc_req_bits_T_195) wire _io_vcalloc_req_bits_WIRE_16 : UInt<1> connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_202 connect _io_vcalloc_req_bits_WIRE_11[4], _io_vcalloc_req_bits_WIRE_16 node _io_vcalloc_req_bits_T_203 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_204 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_205 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_206 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_207 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_208 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_209 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_210 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_211 = or(_io_vcalloc_req_bits_T_203, _io_vcalloc_req_bits_T_204) node _io_vcalloc_req_bits_T_212 = or(_io_vcalloc_req_bits_T_211, _io_vcalloc_req_bits_T_205) node _io_vcalloc_req_bits_T_213 = or(_io_vcalloc_req_bits_T_212, _io_vcalloc_req_bits_T_206) node _io_vcalloc_req_bits_T_214 = or(_io_vcalloc_req_bits_T_213, _io_vcalloc_req_bits_T_207) node _io_vcalloc_req_bits_T_215 = or(_io_vcalloc_req_bits_T_214, _io_vcalloc_req_bits_T_208) node _io_vcalloc_req_bits_T_216 = or(_io_vcalloc_req_bits_T_215, _io_vcalloc_req_bits_T_209) node _io_vcalloc_req_bits_T_217 = or(_io_vcalloc_req_bits_T_216, _io_vcalloc_req_bits_T_210) wire _io_vcalloc_req_bits_WIRE_17 : UInt<1> connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_217 connect _io_vcalloc_req_bits_WIRE_11[5], _io_vcalloc_req_bits_WIRE_17 node _io_vcalloc_req_bits_T_218 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_219 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_220 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_221 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_222 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_223 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_224 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_225 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_226 = or(_io_vcalloc_req_bits_T_218, _io_vcalloc_req_bits_T_219) node _io_vcalloc_req_bits_T_227 = or(_io_vcalloc_req_bits_T_226, _io_vcalloc_req_bits_T_220) node _io_vcalloc_req_bits_T_228 = or(_io_vcalloc_req_bits_T_227, _io_vcalloc_req_bits_T_221) node _io_vcalloc_req_bits_T_229 = or(_io_vcalloc_req_bits_T_228, _io_vcalloc_req_bits_T_222) node _io_vcalloc_req_bits_T_230 = or(_io_vcalloc_req_bits_T_229, _io_vcalloc_req_bits_T_223) node _io_vcalloc_req_bits_T_231 = or(_io_vcalloc_req_bits_T_230, _io_vcalloc_req_bits_T_224) node _io_vcalloc_req_bits_T_232 = or(_io_vcalloc_req_bits_T_231, _io_vcalloc_req_bits_T_225) wire _io_vcalloc_req_bits_WIRE_18 : UInt<1> connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_232 connect _io_vcalloc_req_bits_WIRE_11[6], _io_vcalloc_req_bits_WIRE_18 node _io_vcalloc_req_bits_T_233 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_234 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_235 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_236 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_237 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_238 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_239 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_240 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_241 = or(_io_vcalloc_req_bits_T_233, _io_vcalloc_req_bits_T_234) node _io_vcalloc_req_bits_T_242 = or(_io_vcalloc_req_bits_T_241, _io_vcalloc_req_bits_T_235) node _io_vcalloc_req_bits_T_243 = or(_io_vcalloc_req_bits_T_242, _io_vcalloc_req_bits_T_236) node _io_vcalloc_req_bits_T_244 = or(_io_vcalloc_req_bits_T_243, _io_vcalloc_req_bits_T_237) node _io_vcalloc_req_bits_T_245 = or(_io_vcalloc_req_bits_T_244, _io_vcalloc_req_bits_T_238) node _io_vcalloc_req_bits_T_246 = or(_io_vcalloc_req_bits_T_245, _io_vcalloc_req_bits_T_239) node _io_vcalloc_req_bits_T_247 = or(_io_vcalloc_req_bits_T_246, _io_vcalloc_req_bits_T_240) wire _io_vcalloc_req_bits_WIRE_19 : UInt<1> connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_247 connect _io_vcalloc_req_bits_WIRE_11[7], _io_vcalloc_req_bits_WIRE_19 connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_11 wire _io_vcalloc_req_bits_WIRE_20 : UInt<1>[8] node _io_vcalloc_req_bits_T_248 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_249 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_250 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_251 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_252 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_253 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_254 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_255 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_256 = or(_io_vcalloc_req_bits_T_248, _io_vcalloc_req_bits_T_249) node _io_vcalloc_req_bits_T_257 = or(_io_vcalloc_req_bits_T_256, _io_vcalloc_req_bits_T_250) node _io_vcalloc_req_bits_T_258 = or(_io_vcalloc_req_bits_T_257, _io_vcalloc_req_bits_T_251) node _io_vcalloc_req_bits_T_259 = or(_io_vcalloc_req_bits_T_258, _io_vcalloc_req_bits_T_252) node _io_vcalloc_req_bits_T_260 = or(_io_vcalloc_req_bits_T_259, _io_vcalloc_req_bits_T_253) node _io_vcalloc_req_bits_T_261 = or(_io_vcalloc_req_bits_T_260, _io_vcalloc_req_bits_T_254) node _io_vcalloc_req_bits_T_262 = or(_io_vcalloc_req_bits_T_261, _io_vcalloc_req_bits_T_255) wire _io_vcalloc_req_bits_WIRE_21 : UInt<1> connect _io_vcalloc_req_bits_WIRE_21, _io_vcalloc_req_bits_T_262 connect _io_vcalloc_req_bits_WIRE_20[0], _io_vcalloc_req_bits_WIRE_21 node _io_vcalloc_req_bits_T_263 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_264 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_265 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_266 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_267 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_268 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_269 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_270 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_271 = or(_io_vcalloc_req_bits_T_263, _io_vcalloc_req_bits_T_264) node _io_vcalloc_req_bits_T_272 = or(_io_vcalloc_req_bits_T_271, _io_vcalloc_req_bits_T_265) node _io_vcalloc_req_bits_T_273 = or(_io_vcalloc_req_bits_T_272, _io_vcalloc_req_bits_T_266) node _io_vcalloc_req_bits_T_274 = or(_io_vcalloc_req_bits_T_273, _io_vcalloc_req_bits_T_267) node _io_vcalloc_req_bits_T_275 = or(_io_vcalloc_req_bits_T_274, _io_vcalloc_req_bits_T_268) node _io_vcalloc_req_bits_T_276 = or(_io_vcalloc_req_bits_T_275, _io_vcalloc_req_bits_T_269) node _io_vcalloc_req_bits_T_277 = or(_io_vcalloc_req_bits_T_276, _io_vcalloc_req_bits_T_270) wire _io_vcalloc_req_bits_WIRE_22 : UInt<1> connect _io_vcalloc_req_bits_WIRE_22, _io_vcalloc_req_bits_T_277 connect _io_vcalloc_req_bits_WIRE_20[1], _io_vcalloc_req_bits_WIRE_22 node _io_vcalloc_req_bits_T_278 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_279 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_280 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_281 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_282 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_283 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_284 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_285 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_286 = or(_io_vcalloc_req_bits_T_278, _io_vcalloc_req_bits_T_279) node _io_vcalloc_req_bits_T_287 = or(_io_vcalloc_req_bits_T_286, _io_vcalloc_req_bits_T_280) node _io_vcalloc_req_bits_T_288 = or(_io_vcalloc_req_bits_T_287, _io_vcalloc_req_bits_T_281) node _io_vcalloc_req_bits_T_289 = or(_io_vcalloc_req_bits_T_288, _io_vcalloc_req_bits_T_282) node _io_vcalloc_req_bits_T_290 = or(_io_vcalloc_req_bits_T_289, _io_vcalloc_req_bits_T_283) node _io_vcalloc_req_bits_T_291 = or(_io_vcalloc_req_bits_T_290, _io_vcalloc_req_bits_T_284) node _io_vcalloc_req_bits_T_292 = or(_io_vcalloc_req_bits_T_291, _io_vcalloc_req_bits_T_285) wire _io_vcalloc_req_bits_WIRE_23 : UInt<1> connect _io_vcalloc_req_bits_WIRE_23, _io_vcalloc_req_bits_T_292 connect _io_vcalloc_req_bits_WIRE_20[2], _io_vcalloc_req_bits_WIRE_23 node _io_vcalloc_req_bits_T_293 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_294 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_295 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_296 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_297 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_298 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_299 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_300 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_301 = or(_io_vcalloc_req_bits_T_293, _io_vcalloc_req_bits_T_294) node _io_vcalloc_req_bits_T_302 = or(_io_vcalloc_req_bits_T_301, _io_vcalloc_req_bits_T_295) node _io_vcalloc_req_bits_T_303 = or(_io_vcalloc_req_bits_T_302, _io_vcalloc_req_bits_T_296) node _io_vcalloc_req_bits_T_304 = or(_io_vcalloc_req_bits_T_303, _io_vcalloc_req_bits_T_297) node _io_vcalloc_req_bits_T_305 = or(_io_vcalloc_req_bits_T_304, _io_vcalloc_req_bits_T_298) node _io_vcalloc_req_bits_T_306 = or(_io_vcalloc_req_bits_T_305, _io_vcalloc_req_bits_T_299) node _io_vcalloc_req_bits_T_307 = or(_io_vcalloc_req_bits_T_306, _io_vcalloc_req_bits_T_300) wire _io_vcalloc_req_bits_WIRE_24 : UInt<1> connect _io_vcalloc_req_bits_WIRE_24, _io_vcalloc_req_bits_T_307 connect _io_vcalloc_req_bits_WIRE_20[3], _io_vcalloc_req_bits_WIRE_24 node _io_vcalloc_req_bits_T_308 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_309 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_310 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_311 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_312 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_313 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_314 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_315 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_316 = or(_io_vcalloc_req_bits_T_308, _io_vcalloc_req_bits_T_309) node _io_vcalloc_req_bits_T_317 = or(_io_vcalloc_req_bits_T_316, _io_vcalloc_req_bits_T_310) node _io_vcalloc_req_bits_T_318 = or(_io_vcalloc_req_bits_T_317, _io_vcalloc_req_bits_T_311) node _io_vcalloc_req_bits_T_319 = or(_io_vcalloc_req_bits_T_318, _io_vcalloc_req_bits_T_312) node _io_vcalloc_req_bits_T_320 = or(_io_vcalloc_req_bits_T_319, _io_vcalloc_req_bits_T_313) node _io_vcalloc_req_bits_T_321 = or(_io_vcalloc_req_bits_T_320, _io_vcalloc_req_bits_T_314) node _io_vcalloc_req_bits_T_322 = or(_io_vcalloc_req_bits_T_321, _io_vcalloc_req_bits_T_315) wire _io_vcalloc_req_bits_WIRE_25 : UInt<1> connect _io_vcalloc_req_bits_WIRE_25, _io_vcalloc_req_bits_T_322 connect _io_vcalloc_req_bits_WIRE_20[4], _io_vcalloc_req_bits_WIRE_25 node _io_vcalloc_req_bits_T_323 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_324 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_325 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_326 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_327 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_328 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_329 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_330 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_331 = or(_io_vcalloc_req_bits_T_323, _io_vcalloc_req_bits_T_324) node _io_vcalloc_req_bits_T_332 = or(_io_vcalloc_req_bits_T_331, _io_vcalloc_req_bits_T_325) node _io_vcalloc_req_bits_T_333 = or(_io_vcalloc_req_bits_T_332, _io_vcalloc_req_bits_T_326) node _io_vcalloc_req_bits_T_334 = or(_io_vcalloc_req_bits_T_333, _io_vcalloc_req_bits_T_327) node _io_vcalloc_req_bits_T_335 = or(_io_vcalloc_req_bits_T_334, _io_vcalloc_req_bits_T_328) node _io_vcalloc_req_bits_T_336 = or(_io_vcalloc_req_bits_T_335, _io_vcalloc_req_bits_T_329) node _io_vcalloc_req_bits_T_337 = or(_io_vcalloc_req_bits_T_336, _io_vcalloc_req_bits_T_330) wire _io_vcalloc_req_bits_WIRE_26 : UInt<1> connect _io_vcalloc_req_bits_WIRE_26, _io_vcalloc_req_bits_T_337 connect _io_vcalloc_req_bits_WIRE_20[5], _io_vcalloc_req_bits_WIRE_26 node _io_vcalloc_req_bits_T_338 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_339 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_340 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_341 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_342 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_343 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_344 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_345 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_346 = or(_io_vcalloc_req_bits_T_338, _io_vcalloc_req_bits_T_339) node _io_vcalloc_req_bits_T_347 = or(_io_vcalloc_req_bits_T_346, _io_vcalloc_req_bits_T_340) node _io_vcalloc_req_bits_T_348 = or(_io_vcalloc_req_bits_T_347, _io_vcalloc_req_bits_T_341) node _io_vcalloc_req_bits_T_349 = or(_io_vcalloc_req_bits_T_348, _io_vcalloc_req_bits_T_342) node _io_vcalloc_req_bits_T_350 = or(_io_vcalloc_req_bits_T_349, _io_vcalloc_req_bits_T_343) node _io_vcalloc_req_bits_T_351 = or(_io_vcalloc_req_bits_T_350, _io_vcalloc_req_bits_T_344) node _io_vcalloc_req_bits_T_352 = or(_io_vcalloc_req_bits_T_351, _io_vcalloc_req_bits_T_345) wire _io_vcalloc_req_bits_WIRE_27 : UInt<1> connect _io_vcalloc_req_bits_WIRE_27, _io_vcalloc_req_bits_T_352 connect _io_vcalloc_req_bits_WIRE_20[6], _io_vcalloc_req_bits_WIRE_27 node _io_vcalloc_req_bits_T_353 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_354 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_355 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_356 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_357 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_358 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_359 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_360 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_361 = or(_io_vcalloc_req_bits_T_353, _io_vcalloc_req_bits_T_354) node _io_vcalloc_req_bits_T_362 = or(_io_vcalloc_req_bits_T_361, _io_vcalloc_req_bits_T_355) node _io_vcalloc_req_bits_T_363 = or(_io_vcalloc_req_bits_T_362, _io_vcalloc_req_bits_T_356) node _io_vcalloc_req_bits_T_364 = or(_io_vcalloc_req_bits_T_363, _io_vcalloc_req_bits_T_357) node _io_vcalloc_req_bits_T_365 = or(_io_vcalloc_req_bits_T_364, _io_vcalloc_req_bits_T_358) node _io_vcalloc_req_bits_T_366 = or(_io_vcalloc_req_bits_T_365, _io_vcalloc_req_bits_T_359) node _io_vcalloc_req_bits_T_367 = or(_io_vcalloc_req_bits_T_366, _io_vcalloc_req_bits_T_360) wire _io_vcalloc_req_bits_WIRE_28 : UInt<1> connect _io_vcalloc_req_bits_WIRE_28, _io_vcalloc_req_bits_T_367 connect _io_vcalloc_req_bits_WIRE_20[7], _io_vcalloc_req_bits_WIRE_28 connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_20 wire _io_vcalloc_req_bits_WIRE_29 : UInt<1>[8] node _io_vcalloc_req_bits_T_368 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_369 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_370 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_371 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_372 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_373 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_374 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_375 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_376 = or(_io_vcalloc_req_bits_T_368, _io_vcalloc_req_bits_T_369) node _io_vcalloc_req_bits_T_377 = or(_io_vcalloc_req_bits_T_376, _io_vcalloc_req_bits_T_370) node _io_vcalloc_req_bits_T_378 = or(_io_vcalloc_req_bits_T_377, _io_vcalloc_req_bits_T_371) node _io_vcalloc_req_bits_T_379 = or(_io_vcalloc_req_bits_T_378, _io_vcalloc_req_bits_T_372) node _io_vcalloc_req_bits_T_380 = or(_io_vcalloc_req_bits_T_379, _io_vcalloc_req_bits_T_373) node _io_vcalloc_req_bits_T_381 = or(_io_vcalloc_req_bits_T_380, _io_vcalloc_req_bits_T_374) node _io_vcalloc_req_bits_T_382 = or(_io_vcalloc_req_bits_T_381, _io_vcalloc_req_bits_T_375) wire _io_vcalloc_req_bits_WIRE_30 : UInt<1> connect _io_vcalloc_req_bits_WIRE_30, _io_vcalloc_req_bits_T_382 connect _io_vcalloc_req_bits_WIRE_29[0], _io_vcalloc_req_bits_WIRE_30 node _io_vcalloc_req_bits_T_383 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_384 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_385 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_386 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_387 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_388 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_389 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_390 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_391 = or(_io_vcalloc_req_bits_T_383, _io_vcalloc_req_bits_T_384) node _io_vcalloc_req_bits_T_392 = or(_io_vcalloc_req_bits_T_391, _io_vcalloc_req_bits_T_385) node _io_vcalloc_req_bits_T_393 = or(_io_vcalloc_req_bits_T_392, _io_vcalloc_req_bits_T_386) node _io_vcalloc_req_bits_T_394 = or(_io_vcalloc_req_bits_T_393, _io_vcalloc_req_bits_T_387) node _io_vcalloc_req_bits_T_395 = or(_io_vcalloc_req_bits_T_394, _io_vcalloc_req_bits_T_388) node _io_vcalloc_req_bits_T_396 = or(_io_vcalloc_req_bits_T_395, _io_vcalloc_req_bits_T_389) node _io_vcalloc_req_bits_T_397 = or(_io_vcalloc_req_bits_T_396, _io_vcalloc_req_bits_T_390) wire _io_vcalloc_req_bits_WIRE_31 : UInt<1> connect _io_vcalloc_req_bits_WIRE_31, _io_vcalloc_req_bits_T_397 connect _io_vcalloc_req_bits_WIRE_29[1], _io_vcalloc_req_bits_WIRE_31 node _io_vcalloc_req_bits_T_398 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_399 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_400 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_401 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_402 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_403 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_404 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_405 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_406 = or(_io_vcalloc_req_bits_T_398, _io_vcalloc_req_bits_T_399) node _io_vcalloc_req_bits_T_407 = or(_io_vcalloc_req_bits_T_406, _io_vcalloc_req_bits_T_400) node _io_vcalloc_req_bits_T_408 = or(_io_vcalloc_req_bits_T_407, _io_vcalloc_req_bits_T_401) node _io_vcalloc_req_bits_T_409 = or(_io_vcalloc_req_bits_T_408, _io_vcalloc_req_bits_T_402) node _io_vcalloc_req_bits_T_410 = or(_io_vcalloc_req_bits_T_409, _io_vcalloc_req_bits_T_403) node _io_vcalloc_req_bits_T_411 = or(_io_vcalloc_req_bits_T_410, _io_vcalloc_req_bits_T_404) node _io_vcalloc_req_bits_T_412 = or(_io_vcalloc_req_bits_T_411, _io_vcalloc_req_bits_T_405) wire _io_vcalloc_req_bits_WIRE_32 : UInt<1> connect _io_vcalloc_req_bits_WIRE_32, _io_vcalloc_req_bits_T_412 connect _io_vcalloc_req_bits_WIRE_29[2], _io_vcalloc_req_bits_WIRE_32 node _io_vcalloc_req_bits_T_413 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_414 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_415 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_416 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_417 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_418 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_419 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_420 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_421 = or(_io_vcalloc_req_bits_T_413, _io_vcalloc_req_bits_T_414) node _io_vcalloc_req_bits_T_422 = or(_io_vcalloc_req_bits_T_421, _io_vcalloc_req_bits_T_415) node _io_vcalloc_req_bits_T_423 = or(_io_vcalloc_req_bits_T_422, _io_vcalloc_req_bits_T_416) node _io_vcalloc_req_bits_T_424 = or(_io_vcalloc_req_bits_T_423, _io_vcalloc_req_bits_T_417) node _io_vcalloc_req_bits_T_425 = or(_io_vcalloc_req_bits_T_424, _io_vcalloc_req_bits_T_418) node _io_vcalloc_req_bits_T_426 = or(_io_vcalloc_req_bits_T_425, _io_vcalloc_req_bits_T_419) node _io_vcalloc_req_bits_T_427 = or(_io_vcalloc_req_bits_T_426, _io_vcalloc_req_bits_T_420) wire _io_vcalloc_req_bits_WIRE_33 : UInt<1> connect _io_vcalloc_req_bits_WIRE_33, _io_vcalloc_req_bits_T_427 connect _io_vcalloc_req_bits_WIRE_29[3], _io_vcalloc_req_bits_WIRE_33 node _io_vcalloc_req_bits_T_428 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_429 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_430 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_431 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_432 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_433 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_434 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_435 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_436 = or(_io_vcalloc_req_bits_T_428, _io_vcalloc_req_bits_T_429) node _io_vcalloc_req_bits_T_437 = or(_io_vcalloc_req_bits_T_436, _io_vcalloc_req_bits_T_430) node _io_vcalloc_req_bits_T_438 = or(_io_vcalloc_req_bits_T_437, _io_vcalloc_req_bits_T_431) node _io_vcalloc_req_bits_T_439 = or(_io_vcalloc_req_bits_T_438, _io_vcalloc_req_bits_T_432) node _io_vcalloc_req_bits_T_440 = or(_io_vcalloc_req_bits_T_439, _io_vcalloc_req_bits_T_433) node _io_vcalloc_req_bits_T_441 = or(_io_vcalloc_req_bits_T_440, _io_vcalloc_req_bits_T_434) node _io_vcalloc_req_bits_T_442 = or(_io_vcalloc_req_bits_T_441, _io_vcalloc_req_bits_T_435) wire _io_vcalloc_req_bits_WIRE_34 : UInt<1> connect _io_vcalloc_req_bits_WIRE_34, _io_vcalloc_req_bits_T_442 connect _io_vcalloc_req_bits_WIRE_29[4], _io_vcalloc_req_bits_WIRE_34 node _io_vcalloc_req_bits_T_443 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_444 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_445 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_446 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_447 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_448 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_449 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_450 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_451 = or(_io_vcalloc_req_bits_T_443, _io_vcalloc_req_bits_T_444) node _io_vcalloc_req_bits_T_452 = or(_io_vcalloc_req_bits_T_451, _io_vcalloc_req_bits_T_445) node _io_vcalloc_req_bits_T_453 = or(_io_vcalloc_req_bits_T_452, _io_vcalloc_req_bits_T_446) node _io_vcalloc_req_bits_T_454 = or(_io_vcalloc_req_bits_T_453, _io_vcalloc_req_bits_T_447) node _io_vcalloc_req_bits_T_455 = or(_io_vcalloc_req_bits_T_454, _io_vcalloc_req_bits_T_448) node _io_vcalloc_req_bits_T_456 = or(_io_vcalloc_req_bits_T_455, _io_vcalloc_req_bits_T_449) node _io_vcalloc_req_bits_T_457 = or(_io_vcalloc_req_bits_T_456, _io_vcalloc_req_bits_T_450) wire _io_vcalloc_req_bits_WIRE_35 : UInt<1> connect _io_vcalloc_req_bits_WIRE_35, _io_vcalloc_req_bits_T_457 connect _io_vcalloc_req_bits_WIRE_29[5], _io_vcalloc_req_bits_WIRE_35 node _io_vcalloc_req_bits_T_458 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_459 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_460 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_461 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_462 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_463 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_464 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_465 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_466 = or(_io_vcalloc_req_bits_T_458, _io_vcalloc_req_bits_T_459) node _io_vcalloc_req_bits_T_467 = or(_io_vcalloc_req_bits_T_466, _io_vcalloc_req_bits_T_460) node _io_vcalloc_req_bits_T_468 = or(_io_vcalloc_req_bits_T_467, _io_vcalloc_req_bits_T_461) node _io_vcalloc_req_bits_T_469 = or(_io_vcalloc_req_bits_T_468, _io_vcalloc_req_bits_T_462) node _io_vcalloc_req_bits_T_470 = or(_io_vcalloc_req_bits_T_469, _io_vcalloc_req_bits_T_463) node _io_vcalloc_req_bits_T_471 = or(_io_vcalloc_req_bits_T_470, _io_vcalloc_req_bits_T_464) node _io_vcalloc_req_bits_T_472 = or(_io_vcalloc_req_bits_T_471, _io_vcalloc_req_bits_T_465) wire _io_vcalloc_req_bits_WIRE_36 : UInt<1> connect _io_vcalloc_req_bits_WIRE_36, _io_vcalloc_req_bits_T_472 connect _io_vcalloc_req_bits_WIRE_29[6], _io_vcalloc_req_bits_WIRE_36 node _io_vcalloc_req_bits_T_473 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_474 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_475 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_476 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_477 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_478 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_479 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_480 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_481 = or(_io_vcalloc_req_bits_T_473, _io_vcalloc_req_bits_T_474) node _io_vcalloc_req_bits_T_482 = or(_io_vcalloc_req_bits_T_481, _io_vcalloc_req_bits_T_475) node _io_vcalloc_req_bits_T_483 = or(_io_vcalloc_req_bits_T_482, _io_vcalloc_req_bits_T_476) node _io_vcalloc_req_bits_T_484 = or(_io_vcalloc_req_bits_T_483, _io_vcalloc_req_bits_T_477) node _io_vcalloc_req_bits_T_485 = or(_io_vcalloc_req_bits_T_484, _io_vcalloc_req_bits_T_478) node _io_vcalloc_req_bits_T_486 = or(_io_vcalloc_req_bits_T_485, _io_vcalloc_req_bits_T_479) node _io_vcalloc_req_bits_T_487 = or(_io_vcalloc_req_bits_T_486, _io_vcalloc_req_bits_T_480) wire _io_vcalloc_req_bits_WIRE_37 : UInt<1> connect _io_vcalloc_req_bits_WIRE_37, _io_vcalloc_req_bits_T_487 connect _io_vcalloc_req_bits_WIRE_29[7], _io_vcalloc_req_bits_WIRE_37 connect _io_vcalloc_req_bits_WIRE_1.`3`, _io_vcalloc_req_bits_WIRE_29 connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1 node _io_vcalloc_req_bits_T_488 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_489 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_490 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_491 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_492 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_493 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_494 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_495 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_496 = or(_io_vcalloc_req_bits_T_488, _io_vcalloc_req_bits_T_489) node _io_vcalloc_req_bits_T_497 = or(_io_vcalloc_req_bits_T_496, _io_vcalloc_req_bits_T_490) node _io_vcalloc_req_bits_T_498 = or(_io_vcalloc_req_bits_T_497, _io_vcalloc_req_bits_T_491) node _io_vcalloc_req_bits_T_499 = or(_io_vcalloc_req_bits_T_498, _io_vcalloc_req_bits_T_492) node _io_vcalloc_req_bits_T_500 = or(_io_vcalloc_req_bits_T_499, _io_vcalloc_req_bits_T_493) node _io_vcalloc_req_bits_T_501 = or(_io_vcalloc_req_bits_T_500, _io_vcalloc_req_bits_T_494) node _io_vcalloc_req_bits_T_502 = or(_io_vcalloc_req_bits_T_501, _io_vcalloc_req_bits_T_495) wire _io_vcalloc_req_bits_WIRE_38 : UInt<3> connect _io_vcalloc_req_bits_WIRE_38, _io_vcalloc_req_bits_T_502 connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_38 wire _io_vcalloc_req_bits_WIRE_39 : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>} node _io_vcalloc_req_bits_T_503 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_504 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_505 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_506 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_507 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_508 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_509 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_510 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_511 = or(_io_vcalloc_req_bits_T_503, _io_vcalloc_req_bits_T_504) node _io_vcalloc_req_bits_T_512 = or(_io_vcalloc_req_bits_T_511, _io_vcalloc_req_bits_T_505) node _io_vcalloc_req_bits_T_513 = or(_io_vcalloc_req_bits_T_512, _io_vcalloc_req_bits_T_506) node _io_vcalloc_req_bits_T_514 = or(_io_vcalloc_req_bits_T_513, _io_vcalloc_req_bits_T_507) node _io_vcalloc_req_bits_T_515 = or(_io_vcalloc_req_bits_T_514, _io_vcalloc_req_bits_T_508) node _io_vcalloc_req_bits_T_516 = or(_io_vcalloc_req_bits_T_515, _io_vcalloc_req_bits_T_509) node _io_vcalloc_req_bits_T_517 = or(_io_vcalloc_req_bits_T_516, _io_vcalloc_req_bits_T_510) wire _io_vcalloc_req_bits_WIRE_40 : UInt<2> connect _io_vcalloc_req_bits_WIRE_40, _io_vcalloc_req_bits_T_517 connect _io_vcalloc_req_bits_WIRE_39.egress_node_id, _io_vcalloc_req_bits_WIRE_40 node _io_vcalloc_req_bits_T_518 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_519 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_520 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_521 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_522 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_523 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_524 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_525 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_526 = or(_io_vcalloc_req_bits_T_518, _io_vcalloc_req_bits_T_519) node _io_vcalloc_req_bits_T_527 = or(_io_vcalloc_req_bits_T_526, _io_vcalloc_req_bits_T_520) node _io_vcalloc_req_bits_T_528 = or(_io_vcalloc_req_bits_T_527, _io_vcalloc_req_bits_T_521) node _io_vcalloc_req_bits_T_529 = or(_io_vcalloc_req_bits_T_528, _io_vcalloc_req_bits_T_522) node _io_vcalloc_req_bits_T_530 = or(_io_vcalloc_req_bits_T_529, _io_vcalloc_req_bits_T_523) node _io_vcalloc_req_bits_T_531 = or(_io_vcalloc_req_bits_T_530, _io_vcalloc_req_bits_T_524) node _io_vcalloc_req_bits_T_532 = or(_io_vcalloc_req_bits_T_531, _io_vcalloc_req_bits_T_525) wire _io_vcalloc_req_bits_WIRE_41 : UInt<5> connect _io_vcalloc_req_bits_WIRE_41, _io_vcalloc_req_bits_T_532 connect _io_vcalloc_req_bits_WIRE_39.egress_node, _io_vcalloc_req_bits_WIRE_41 node _io_vcalloc_req_bits_T_533 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_534 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_535 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_536 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_537 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_538 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_539 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_540 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_541 = or(_io_vcalloc_req_bits_T_533, _io_vcalloc_req_bits_T_534) node _io_vcalloc_req_bits_T_542 = or(_io_vcalloc_req_bits_T_541, _io_vcalloc_req_bits_T_535) node _io_vcalloc_req_bits_T_543 = or(_io_vcalloc_req_bits_T_542, _io_vcalloc_req_bits_T_536) node _io_vcalloc_req_bits_T_544 = or(_io_vcalloc_req_bits_T_543, _io_vcalloc_req_bits_T_537) node _io_vcalloc_req_bits_T_545 = or(_io_vcalloc_req_bits_T_544, _io_vcalloc_req_bits_T_538) node _io_vcalloc_req_bits_T_546 = or(_io_vcalloc_req_bits_T_545, _io_vcalloc_req_bits_T_539) node _io_vcalloc_req_bits_T_547 = or(_io_vcalloc_req_bits_T_546, _io_vcalloc_req_bits_T_540) wire _io_vcalloc_req_bits_WIRE_42 : UInt<2> connect _io_vcalloc_req_bits_WIRE_42, _io_vcalloc_req_bits_T_547 connect _io_vcalloc_req_bits_WIRE_39.ingress_node_id, _io_vcalloc_req_bits_WIRE_42 node _io_vcalloc_req_bits_T_548 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_549 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_550 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_551 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_552 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_553 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_554 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_555 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_556 = or(_io_vcalloc_req_bits_T_548, _io_vcalloc_req_bits_T_549) node _io_vcalloc_req_bits_T_557 = or(_io_vcalloc_req_bits_T_556, _io_vcalloc_req_bits_T_550) node _io_vcalloc_req_bits_T_558 = or(_io_vcalloc_req_bits_T_557, _io_vcalloc_req_bits_T_551) node _io_vcalloc_req_bits_T_559 = or(_io_vcalloc_req_bits_T_558, _io_vcalloc_req_bits_T_552) node _io_vcalloc_req_bits_T_560 = or(_io_vcalloc_req_bits_T_559, _io_vcalloc_req_bits_T_553) node _io_vcalloc_req_bits_T_561 = or(_io_vcalloc_req_bits_T_560, _io_vcalloc_req_bits_T_554) node _io_vcalloc_req_bits_T_562 = or(_io_vcalloc_req_bits_T_561, _io_vcalloc_req_bits_T_555) wire _io_vcalloc_req_bits_WIRE_43 : UInt<5> connect _io_vcalloc_req_bits_WIRE_43, _io_vcalloc_req_bits_T_562 connect _io_vcalloc_req_bits_WIRE_39.ingress_node, _io_vcalloc_req_bits_WIRE_43 node _io_vcalloc_req_bits_T_563 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_564 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_565 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_566 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_567 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_568 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_569 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_570 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_571 = or(_io_vcalloc_req_bits_T_563, _io_vcalloc_req_bits_T_564) node _io_vcalloc_req_bits_T_572 = or(_io_vcalloc_req_bits_T_571, _io_vcalloc_req_bits_T_565) node _io_vcalloc_req_bits_T_573 = or(_io_vcalloc_req_bits_T_572, _io_vcalloc_req_bits_T_566) node _io_vcalloc_req_bits_T_574 = or(_io_vcalloc_req_bits_T_573, _io_vcalloc_req_bits_T_567) node _io_vcalloc_req_bits_T_575 = or(_io_vcalloc_req_bits_T_574, _io_vcalloc_req_bits_T_568) node _io_vcalloc_req_bits_T_576 = or(_io_vcalloc_req_bits_T_575, _io_vcalloc_req_bits_T_569) node _io_vcalloc_req_bits_T_577 = or(_io_vcalloc_req_bits_T_576, _io_vcalloc_req_bits_T_570) wire _io_vcalloc_req_bits_WIRE_44 : UInt<3> connect _io_vcalloc_req_bits_WIRE_44, _io_vcalloc_req_bits_T_577 connect _io_vcalloc_req_bits_WIRE_39.vnet_id, _io_vcalloc_req_bits_WIRE_44 connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_39 connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE connect vcalloc_vals[0], UInt<1>(0h0) invalidate vcalloc_reqs[0].vc_sel.`0`[0] invalidate vcalloc_reqs[0].vc_sel.`0`[1] invalidate vcalloc_reqs[0].vc_sel.`0`[2] invalidate vcalloc_reqs[0].vc_sel.`0`[3] invalidate vcalloc_reqs[0].vc_sel.`0`[4] invalidate vcalloc_reqs[0].vc_sel.`0`[5] invalidate vcalloc_reqs[0].vc_sel.`0`[6] invalidate vcalloc_reqs[0].vc_sel.`0`[7] invalidate vcalloc_reqs[0].vc_sel.`1`[0] invalidate vcalloc_reqs[0].vc_sel.`1`[1] invalidate vcalloc_reqs[0].vc_sel.`1`[2] invalidate vcalloc_reqs[0].vc_sel.`1`[3] invalidate vcalloc_reqs[0].vc_sel.`1`[4] invalidate vcalloc_reqs[0].vc_sel.`1`[5] invalidate vcalloc_reqs[0].vc_sel.`1`[6] invalidate vcalloc_reqs[0].vc_sel.`1`[7] invalidate vcalloc_reqs[0].vc_sel.`2`[0] invalidate vcalloc_reqs[0].vc_sel.`2`[1] invalidate vcalloc_reqs[0].vc_sel.`2`[2] invalidate vcalloc_reqs[0].vc_sel.`2`[3] invalidate vcalloc_reqs[0].vc_sel.`2`[4] invalidate vcalloc_reqs[0].vc_sel.`2`[5] invalidate vcalloc_reqs[0].vc_sel.`2`[6] invalidate vcalloc_reqs[0].vc_sel.`2`[7] invalidate vcalloc_reqs[0].vc_sel.`3`[0] invalidate vcalloc_reqs[0].vc_sel.`3`[1] invalidate vcalloc_reqs[0].vc_sel.`3`[2] invalidate vcalloc_reqs[0].vc_sel.`3`[3] invalidate vcalloc_reqs[0].vc_sel.`3`[4] invalidate vcalloc_reqs[0].vc_sel.`3`[5] invalidate vcalloc_reqs[0].vc_sel.`3`[6] invalidate vcalloc_reqs[0].vc_sel.`3`[7] invalidate vcalloc_reqs[0].in_vc invalidate vcalloc_reqs[0].flow.egress_node_id invalidate vcalloc_reqs[0].flow.egress_node invalidate vcalloc_reqs[0].flow.ingress_node_id invalidate vcalloc_reqs[0].flow.ingress_node invalidate vcalloc_reqs[0].flow.vnet_id node _vcalloc_vals_1_T = eq(states[1].g, UInt<3>(0h2)) node _vcalloc_vals_1_T_1 = eq(states[1].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_1_T_2 = and(_vcalloc_vals_1_T, _vcalloc_vals_1_T_1) connect vcalloc_vals[1], _vcalloc_vals_1_T_2 connect vcalloc_reqs[1].in_vc, UInt<1>(0h1) connect vcalloc_reqs[1].vc_sel.`0`, states[1].vc_sel.`0` connect vcalloc_reqs[1].vc_sel.`1`, states[1].vc_sel.`1` connect vcalloc_reqs[1].vc_sel.`2`, states[1].vc_sel.`2` connect vcalloc_reqs[1].vc_sel.`3`, states[1].vc_sel.`3` connect vcalloc_reqs[1].flow, states[1].flow node _T_37 = bits(vcalloc_sel, 1, 1) node _T_38 = and(vcalloc_vals[1], _T_37) node _T_39 = and(_T_38, io.vcalloc_req.ready) when _T_39 : connect states[1].g, UInt<3>(0h3) node _vcalloc_vals_2_T = eq(states[2].g, UInt<3>(0h2)) node _vcalloc_vals_2_T_1 = eq(states[2].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_2_T_2 = and(_vcalloc_vals_2_T, _vcalloc_vals_2_T_1) connect vcalloc_vals[2], _vcalloc_vals_2_T_2 connect vcalloc_reqs[2].in_vc, UInt<2>(0h2) connect vcalloc_reqs[2].vc_sel.`0`, states[2].vc_sel.`0` connect vcalloc_reqs[2].vc_sel.`1`, states[2].vc_sel.`1` connect vcalloc_reqs[2].vc_sel.`2`, states[2].vc_sel.`2` connect vcalloc_reqs[2].vc_sel.`3`, states[2].vc_sel.`3` connect vcalloc_reqs[2].flow, states[2].flow node _T_40 = bits(vcalloc_sel, 2, 2) node _T_41 = and(vcalloc_vals[2], _T_40) node _T_42 = and(_T_41, io.vcalloc_req.ready) when _T_42 : connect states[2].g, UInt<3>(0h3) node _vcalloc_vals_3_T = eq(states[3].g, UInt<3>(0h2)) node _vcalloc_vals_3_T_1 = eq(states[3].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_3_T_2 = and(_vcalloc_vals_3_T, _vcalloc_vals_3_T_1) connect vcalloc_vals[3], _vcalloc_vals_3_T_2 connect vcalloc_reqs[3].in_vc, UInt<2>(0h3) connect vcalloc_reqs[3].vc_sel.`0`, states[3].vc_sel.`0` connect vcalloc_reqs[3].vc_sel.`1`, states[3].vc_sel.`1` connect vcalloc_reqs[3].vc_sel.`2`, states[3].vc_sel.`2` connect vcalloc_reqs[3].vc_sel.`3`, states[3].vc_sel.`3` connect vcalloc_reqs[3].flow, states[3].flow node _T_43 = bits(vcalloc_sel, 3, 3) node _T_44 = and(vcalloc_vals[3], _T_43) node _T_45 = and(_T_44, io.vcalloc_req.ready) when _T_45 : connect states[3].g, UInt<3>(0h3) node _vcalloc_vals_4_T = eq(states[4].g, UInt<3>(0h2)) node _vcalloc_vals_4_T_1 = eq(states[4].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_4_T_2 = and(_vcalloc_vals_4_T, _vcalloc_vals_4_T_1) connect vcalloc_vals[4], _vcalloc_vals_4_T_2 connect vcalloc_reqs[4].in_vc, UInt<3>(0h4) connect vcalloc_reqs[4].vc_sel.`0`, states[4].vc_sel.`0` connect vcalloc_reqs[4].vc_sel.`1`, states[4].vc_sel.`1` connect vcalloc_reqs[4].vc_sel.`2`, states[4].vc_sel.`2` connect vcalloc_reqs[4].vc_sel.`3`, states[4].vc_sel.`3` connect vcalloc_reqs[4].flow, states[4].flow node _T_46 = bits(vcalloc_sel, 4, 4) node _T_47 = and(vcalloc_vals[4], _T_46) node _T_48 = and(_T_47, io.vcalloc_req.ready) when _T_48 : connect states[4].g, UInt<3>(0h3) node _vcalloc_vals_5_T = eq(states[5].g, UInt<3>(0h2)) node _vcalloc_vals_5_T_1 = eq(states[5].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_5_T_2 = and(_vcalloc_vals_5_T, _vcalloc_vals_5_T_1) connect vcalloc_vals[5], _vcalloc_vals_5_T_2 connect vcalloc_reqs[5].in_vc, UInt<3>(0h5) connect vcalloc_reqs[5].vc_sel.`0`, states[5].vc_sel.`0` connect vcalloc_reqs[5].vc_sel.`1`, states[5].vc_sel.`1` connect vcalloc_reqs[5].vc_sel.`2`, states[5].vc_sel.`2` connect vcalloc_reqs[5].vc_sel.`3`, states[5].vc_sel.`3` connect vcalloc_reqs[5].flow, states[5].flow node _T_49 = bits(vcalloc_sel, 5, 5) node _T_50 = and(vcalloc_vals[5], _T_49) node _T_51 = and(_T_50, io.vcalloc_req.ready) when _T_51 : connect states[5].g, UInt<3>(0h3) node _vcalloc_vals_6_T = eq(states[6].g, UInt<3>(0h2)) node _vcalloc_vals_6_T_1 = eq(states[6].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_6_T_2 = and(_vcalloc_vals_6_T, _vcalloc_vals_6_T_1) connect vcalloc_vals[6], _vcalloc_vals_6_T_2 connect vcalloc_reqs[6].in_vc, UInt<3>(0h6) connect vcalloc_reqs[6].vc_sel.`0`, states[6].vc_sel.`0` connect vcalloc_reqs[6].vc_sel.`1`, states[6].vc_sel.`1` connect vcalloc_reqs[6].vc_sel.`2`, states[6].vc_sel.`2` connect vcalloc_reqs[6].vc_sel.`3`, states[6].vc_sel.`3` connect vcalloc_reqs[6].flow, states[6].flow node _T_52 = bits(vcalloc_sel, 6, 6) node _T_53 = and(vcalloc_vals[6], _T_52) node _T_54 = and(_T_53, io.vcalloc_req.ready) when _T_54 : connect states[6].g, UInt<3>(0h3) node _vcalloc_vals_7_T = eq(states[7].g, UInt<3>(0h2)) node _vcalloc_vals_7_T_1 = eq(states[7].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_7_T_2 = and(_vcalloc_vals_7_T, _vcalloc_vals_7_T_1) connect vcalloc_vals[7], _vcalloc_vals_7_T_2 connect vcalloc_reqs[7].in_vc, UInt<3>(0h7) connect vcalloc_reqs[7].vc_sel.`0`, states[7].vc_sel.`0` connect vcalloc_reqs[7].vc_sel.`1`, states[7].vc_sel.`1` connect vcalloc_reqs[7].vc_sel.`2`, states[7].vc_sel.`2` connect vcalloc_reqs[7].vc_sel.`3`, states[7].vc_sel.`3` connect vcalloc_reqs[7].flow, states[7].flow node _T_55 = bits(vcalloc_sel, 7, 7) node _T_56 = and(vcalloc_vals[7], _T_55) node _T_57 = and(_T_56, io.vcalloc_req.ready) when _T_57 : connect states[7].g, UInt<3>(0h3) node _io_debug_va_stall_T = add(vcalloc_vals[0], vcalloc_vals[1]) node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0) node _io_debug_va_stall_T_2 = add(vcalloc_vals[2], vcalloc_vals[3]) node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0) node _io_debug_va_stall_T_4 = add(_io_debug_va_stall_T_1, _io_debug_va_stall_T_3) node _io_debug_va_stall_T_5 = bits(_io_debug_va_stall_T_4, 2, 0) node _io_debug_va_stall_T_6 = add(vcalloc_vals[4], vcalloc_vals[5]) node _io_debug_va_stall_T_7 = bits(_io_debug_va_stall_T_6, 1, 0) node _io_debug_va_stall_T_8 = add(vcalloc_vals[6], vcalloc_vals[7]) node _io_debug_va_stall_T_9 = bits(_io_debug_va_stall_T_8, 1, 0) node _io_debug_va_stall_T_10 = add(_io_debug_va_stall_T_7, _io_debug_va_stall_T_9) node _io_debug_va_stall_T_11 = bits(_io_debug_va_stall_T_10, 2, 0) node _io_debug_va_stall_T_12 = add(_io_debug_va_stall_T_5, _io_debug_va_stall_T_11) node _io_debug_va_stall_T_13 = bits(_io_debug_va_stall_T_12, 3, 0) node _io_debug_va_stall_T_14 = sub(_io_debug_va_stall_T_13, io.vcalloc_req.ready) node _io_debug_va_stall_T_15 = tail(_io_debug_va_stall_T_14, 1) connect io.debug.va_stall, _io_debug_va_stall_T_15 node _T_58 = and(io.vcalloc_req.ready, io.vcalloc_req.valid) when _T_58 : node _T_59 = bits(vcalloc_sel, 0, 0) when _T_59 : connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[0].g, UInt<3>(0h3) node _T_60 = eq(states[0].g, UInt<3>(0h2)) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_3 assert(clock, _T_60, UInt<1>(0h1), "") : assert_3 node _T_64 = bits(vcalloc_sel, 1, 1) when _T_64 : connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[1].g, UInt<3>(0h3) node _T_65 = eq(states[1].g, UInt<3>(0h2)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_4 assert(clock, _T_65, UInt<1>(0h1), "") : assert_4 node _T_69 = bits(vcalloc_sel, 2, 2) when _T_69 : connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[2].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[2].g, UInt<3>(0h3) node _T_70 = eq(states[2].g, UInt<3>(0h2)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_5 assert(clock, _T_70, UInt<1>(0h1), "") : assert_5 node _T_74 = bits(vcalloc_sel, 3, 3) when _T_74 : connect states[3].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[3].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[3].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[3].g, UInt<3>(0h3) node _T_75 = eq(states[3].g, UInt<3>(0h2)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_6 assert(clock, _T_75, UInt<1>(0h1), "") : assert_6 node _T_79 = bits(vcalloc_sel, 4, 4) when _T_79 : connect states[4].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[4].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[4].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[4].g, UInt<3>(0h3) node _T_80 = eq(states[4].g, UInt<3>(0h2)) node _T_81 = asUInt(reset) node _T_82 = eq(_T_81, UInt<1>(0h0)) when _T_82 : node _T_83 = eq(_T_80, UInt<1>(0h0)) when _T_83 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_7 assert(clock, _T_80, UInt<1>(0h1), "") : assert_7 node _T_84 = bits(vcalloc_sel, 5, 5) when _T_84 : connect states[5].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[5].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[5].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[5].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[5].g, UInt<3>(0h3) node _T_85 = eq(states[5].g, UInt<3>(0h2)) node _T_86 = asUInt(reset) node _T_87 = eq(_T_86, UInt<1>(0h0)) when _T_87 : node _T_88 = eq(_T_85, UInt<1>(0h0)) when _T_88 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_8 assert(clock, _T_85, UInt<1>(0h1), "") : assert_8 node _T_89 = bits(vcalloc_sel, 6, 6) when _T_89 : connect states[6].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[6].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[6].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[6].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[6].g, UInt<3>(0h3) node _T_90 = eq(states[6].g, UInt<3>(0h2)) node _T_91 = asUInt(reset) node _T_92 = eq(_T_91, UInt<1>(0h0)) when _T_92 : node _T_93 = eq(_T_90, UInt<1>(0h0)) when _T_93 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_9 assert(clock, _T_90, UInt<1>(0h1), "") : assert_9 node _T_94 = bits(vcalloc_sel, 7, 7) when _T_94 : connect states[7].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[7].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[7].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[7].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[7].g, UInt<3>(0h3) node _T_95 = eq(states[7].g, UInt<3>(0h2)) node _T_96 = asUInt(reset) node _T_97 = eq(_T_96, UInt<1>(0h0)) when _T_97 : node _T_98 = eq(_T_95, UInt<1>(0h0)) when _T_98 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_10 assert(clock, _T_95, UInt<1>(0h1), "") : assert_10 inst salloc_arb of SwitchArbiter_168 connect salloc_arb.clock, clock connect salloc_arb.reset, reset connect salloc_arb.io.in[0].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[0].bits.tail invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[5] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[6] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[7] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[4] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[5] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[6] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[7] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[4] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[5] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[6] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[7] invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[4] invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[5] invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[6] invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[7] node credit_available_lo_lo = cat(states[1].vc_sel.`0`[1], states[1].vc_sel.`0`[0]) node credit_available_lo_hi = cat(states[1].vc_sel.`0`[3], states[1].vc_sel.`0`[2]) node credit_available_lo = cat(credit_available_lo_hi, credit_available_lo_lo) node credit_available_hi_lo = cat(states[1].vc_sel.`0`[5], states[1].vc_sel.`0`[4]) node credit_available_hi_hi = cat(states[1].vc_sel.`0`[7], states[1].vc_sel.`0`[6]) node credit_available_hi = cat(credit_available_hi_hi, credit_available_hi_lo) node _credit_available_T = cat(credit_available_hi, credit_available_lo) node credit_available_lo_lo_1 = cat(states[1].vc_sel.`1`[1], states[1].vc_sel.`1`[0]) node credit_available_lo_hi_1 = cat(states[1].vc_sel.`1`[3], states[1].vc_sel.`1`[2]) node credit_available_lo_1 = cat(credit_available_lo_hi_1, credit_available_lo_lo_1) node credit_available_hi_lo_1 = cat(states[1].vc_sel.`1`[5], states[1].vc_sel.`1`[4]) node credit_available_hi_hi_1 = cat(states[1].vc_sel.`1`[7], states[1].vc_sel.`1`[6]) node credit_available_hi_1 = cat(credit_available_hi_hi_1, credit_available_hi_lo_1) node _credit_available_T_1 = cat(credit_available_hi_1, credit_available_lo_1) node credit_available_lo_lo_2 = cat(states[1].vc_sel.`2`[1], states[1].vc_sel.`2`[0]) node credit_available_lo_hi_2 = cat(states[1].vc_sel.`2`[3], states[1].vc_sel.`2`[2]) node credit_available_lo_2 = cat(credit_available_lo_hi_2, credit_available_lo_lo_2) node credit_available_hi_lo_2 = cat(states[1].vc_sel.`2`[5], states[1].vc_sel.`2`[4]) node credit_available_hi_hi_2 = cat(states[1].vc_sel.`2`[7], states[1].vc_sel.`2`[6]) node credit_available_hi_2 = cat(credit_available_hi_hi_2, credit_available_hi_lo_2) node _credit_available_T_2 = cat(credit_available_hi_2, credit_available_lo_2) node credit_available_lo_lo_3 = cat(states[1].vc_sel.`3`[1], states[1].vc_sel.`3`[0]) node credit_available_lo_hi_3 = cat(states[1].vc_sel.`3`[3], states[1].vc_sel.`3`[2]) node credit_available_lo_3 = cat(credit_available_lo_hi_3, credit_available_lo_lo_3) node credit_available_hi_lo_3 = cat(states[1].vc_sel.`3`[5], states[1].vc_sel.`3`[4]) node credit_available_hi_hi_3 = cat(states[1].vc_sel.`3`[7], states[1].vc_sel.`3`[6]) node credit_available_hi_3 = cat(credit_available_hi_hi_3, credit_available_hi_lo_3) node _credit_available_T_3 = cat(credit_available_hi_3, credit_available_lo_3) node credit_available_lo_4 = cat(_credit_available_T_1, _credit_available_T) node credit_available_hi_4 = cat(_credit_available_T_3, _credit_available_T_2) node _credit_available_T_4 = cat(credit_available_hi_4, credit_available_lo_4) node credit_available_lo_lo_4 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_4 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_5 = cat(credit_available_lo_hi_4, credit_available_lo_lo_4) node credit_available_hi_lo_4 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_4 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_5 = cat(credit_available_hi_hi_4, credit_available_hi_lo_4) node _credit_available_T_5 = cat(credit_available_hi_5, credit_available_lo_5) node credit_available_lo_lo_5 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_5 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_6 = cat(credit_available_lo_hi_5, credit_available_lo_lo_5) node credit_available_hi_lo_5 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_5 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_6 = cat(credit_available_hi_hi_5, credit_available_hi_lo_5) node _credit_available_T_6 = cat(credit_available_hi_6, credit_available_lo_6) node credit_available_lo_lo_6 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_6 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_7 = cat(credit_available_lo_hi_6, credit_available_lo_lo_6) node credit_available_hi_lo_6 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_6 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_7 = cat(credit_available_hi_hi_6, credit_available_hi_lo_6) node _credit_available_T_7 = cat(credit_available_hi_7, credit_available_lo_7) node credit_available_lo_lo_7 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_7 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_8 = cat(credit_available_lo_hi_7, credit_available_lo_lo_7) node credit_available_hi_lo_7 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_7 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_8 = cat(credit_available_hi_hi_7, credit_available_hi_lo_7) node _credit_available_T_8 = cat(credit_available_hi_8, credit_available_lo_8) node credit_available_lo_9 = cat(_credit_available_T_6, _credit_available_T_5) node credit_available_hi_9 = cat(_credit_available_T_8, _credit_available_T_7) node _credit_available_T_9 = cat(credit_available_hi_9, credit_available_lo_9) node _credit_available_T_10 = and(_credit_available_T_4, _credit_available_T_9) node credit_available = neq(_credit_available_T_10, UInt<1>(0h0)) node _salloc_arb_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h3)) node _salloc_arb_io_in_1_valid_T_1 = and(_salloc_arb_io_in_1_valid_T, credit_available) node _salloc_arb_io_in_1_valid_T_2 = and(_salloc_arb_io_in_1_valid_T_1, input_buffer.io.deq[1].valid) connect salloc_arb.io.in[1].valid, _salloc_arb_io_in_1_valid_T_2 connect salloc_arb.io.in[1].bits.vc_sel.`0`[0], states[1].vc_sel.`0`[0] connect salloc_arb.io.in[1].bits.vc_sel.`0`[1], states[1].vc_sel.`0`[1] connect salloc_arb.io.in[1].bits.vc_sel.`0`[2], states[1].vc_sel.`0`[2] connect salloc_arb.io.in[1].bits.vc_sel.`0`[3], states[1].vc_sel.`0`[3] connect salloc_arb.io.in[1].bits.vc_sel.`0`[4], states[1].vc_sel.`0`[4] connect salloc_arb.io.in[1].bits.vc_sel.`0`[5], states[1].vc_sel.`0`[5] connect salloc_arb.io.in[1].bits.vc_sel.`0`[6], states[1].vc_sel.`0`[6] connect salloc_arb.io.in[1].bits.vc_sel.`0`[7], states[1].vc_sel.`0`[7] connect salloc_arb.io.in[1].bits.vc_sel.`1`[0], states[1].vc_sel.`1`[0] connect salloc_arb.io.in[1].bits.vc_sel.`1`[1], states[1].vc_sel.`1`[1] connect salloc_arb.io.in[1].bits.vc_sel.`1`[2], states[1].vc_sel.`1`[2] connect salloc_arb.io.in[1].bits.vc_sel.`1`[3], states[1].vc_sel.`1`[3] connect salloc_arb.io.in[1].bits.vc_sel.`1`[4], states[1].vc_sel.`1`[4] connect salloc_arb.io.in[1].bits.vc_sel.`1`[5], states[1].vc_sel.`1`[5] connect salloc_arb.io.in[1].bits.vc_sel.`1`[6], states[1].vc_sel.`1`[6] connect salloc_arb.io.in[1].bits.vc_sel.`1`[7], states[1].vc_sel.`1`[7] connect salloc_arb.io.in[1].bits.vc_sel.`2`[0], states[1].vc_sel.`2`[0] connect salloc_arb.io.in[1].bits.vc_sel.`2`[1], states[1].vc_sel.`2`[1] connect salloc_arb.io.in[1].bits.vc_sel.`2`[2], states[1].vc_sel.`2`[2] connect salloc_arb.io.in[1].bits.vc_sel.`2`[3], states[1].vc_sel.`2`[3] connect salloc_arb.io.in[1].bits.vc_sel.`2`[4], states[1].vc_sel.`2`[4] connect salloc_arb.io.in[1].bits.vc_sel.`2`[5], states[1].vc_sel.`2`[5] connect salloc_arb.io.in[1].bits.vc_sel.`2`[6], states[1].vc_sel.`2`[6] connect salloc_arb.io.in[1].bits.vc_sel.`2`[7], states[1].vc_sel.`2`[7] connect salloc_arb.io.in[1].bits.vc_sel.`3`[0], states[1].vc_sel.`3`[0] connect salloc_arb.io.in[1].bits.vc_sel.`3`[1], states[1].vc_sel.`3`[1] connect salloc_arb.io.in[1].bits.vc_sel.`3`[2], states[1].vc_sel.`3`[2] connect salloc_arb.io.in[1].bits.vc_sel.`3`[3], states[1].vc_sel.`3`[3] connect salloc_arb.io.in[1].bits.vc_sel.`3`[4], states[1].vc_sel.`3`[4] connect salloc_arb.io.in[1].bits.vc_sel.`3`[5], states[1].vc_sel.`3`[5] connect salloc_arb.io.in[1].bits.vc_sel.`3`[6], states[1].vc_sel.`3`[6] connect salloc_arb.io.in[1].bits.vc_sel.`3`[7], states[1].vc_sel.`3`[7] connect salloc_arb.io.in[1].bits.tail, input_buffer.io.deq[1].bits.tail node _T_99 = and(salloc_arb.io.in[1].ready, salloc_arb.io.in[1].valid) node _T_100 = and(_T_99, input_buffer.io.deq[1].bits.tail) when _T_100 : connect states[1].g, UInt<3>(0h0) connect input_buffer.io.deq[1].ready, salloc_arb.io.in[1].ready node credit_available_lo_lo_8 = cat(states[2].vc_sel.`0`[1], states[2].vc_sel.`0`[0]) node credit_available_lo_hi_8 = cat(states[2].vc_sel.`0`[3], states[2].vc_sel.`0`[2]) node credit_available_lo_10 = cat(credit_available_lo_hi_8, credit_available_lo_lo_8) node credit_available_hi_lo_8 = cat(states[2].vc_sel.`0`[5], states[2].vc_sel.`0`[4]) node credit_available_hi_hi_8 = cat(states[2].vc_sel.`0`[7], states[2].vc_sel.`0`[6]) node credit_available_hi_10 = cat(credit_available_hi_hi_8, credit_available_hi_lo_8) node _credit_available_T_11 = cat(credit_available_hi_10, credit_available_lo_10) node credit_available_lo_lo_9 = cat(states[2].vc_sel.`1`[1], states[2].vc_sel.`1`[0]) node credit_available_lo_hi_9 = cat(states[2].vc_sel.`1`[3], states[2].vc_sel.`1`[2]) node credit_available_lo_11 = cat(credit_available_lo_hi_9, credit_available_lo_lo_9) node credit_available_hi_lo_9 = cat(states[2].vc_sel.`1`[5], states[2].vc_sel.`1`[4]) node credit_available_hi_hi_9 = cat(states[2].vc_sel.`1`[7], states[2].vc_sel.`1`[6]) node credit_available_hi_11 = cat(credit_available_hi_hi_9, credit_available_hi_lo_9) node _credit_available_T_12 = cat(credit_available_hi_11, credit_available_lo_11) node credit_available_lo_lo_10 = cat(states[2].vc_sel.`2`[1], states[2].vc_sel.`2`[0]) node credit_available_lo_hi_10 = cat(states[2].vc_sel.`2`[3], states[2].vc_sel.`2`[2]) node credit_available_lo_12 = cat(credit_available_lo_hi_10, credit_available_lo_lo_10) node credit_available_hi_lo_10 = cat(states[2].vc_sel.`2`[5], states[2].vc_sel.`2`[4]) node credit_available_hi_hi_10 = cat(states[2].vc_sel.`2`[7], states[2].vc_sel.`2`[6]) node credit_available_hi_12 = cat(credit_available_hi_hi_10, credit_available_hi_lo_10) node _credit_available_T_13 = cat(credit_available_hi_12, credit_available_lo_12) node credit_available_lo_lo_11 = cat(states[2].vc_sel.`3`[1], states[2].vc_sel.`3`[0]) node credit_available_lo_hi_11 = cat(states[2].vc_sel.`3`[3], states[2].vc_sel.`3`[2]) node credit_available_lo_13 = cat(credit_available_lo_hi_11, credit_available_lo_lo_11) node credit_available_hi_lo_11 = cat(states[2].vc_sel.`3`[5], states[2].vc_sel.`3`[4]) node credit_available_hi_hi_11 = cat(states[2].vc_sel.`3`[7], states[2].vc_sel.`3`[6]) node credit_available_hi_13 = cat(credit_available_hi_hi_11, credit_available_hi_lo_11) node _credit_available_T_14 = cat(credit_available_hi_13, credit_available_lo_13) node credit_available_lo_14 = cat(_credit_available_T_12, _credit_available_T_11) node credit_available_hi_14 = cat(_credit_available_T_14, _credit_available_T_13) node _credit_available_T_15 = cat(credit_available_hi_14, credit_available_lo_14) node credit_available_lo_lo_12 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_12 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_15 = cat(credit_available_lo_hi_12, credit_available_lo_lo_12) node credit_available_hi_lo_12 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_12 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_15 = cat(credit_available_hi_hi_12, credit_available_hi_lo_12) node _credit_available_T_16 = cat(credit_available_hi_15, credit_available_lo_15) node credit_available_lo_lo_13 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_13 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_16 = cat(credit_available_lo_hi_13, credit_available_lo_lo_13) node credit_available_hi_lo_13 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_13 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_16 = cat(credit_available_hi_hi_13, credit_available_hi_lo_13) node _credit_available_T_17 = cat(credit_available_hi_16, credit_available_lo_16) node credit_available_lo_lo_14 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_14 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_17 = cat(credit_available_lo_hi_14, credit_available_lo_lo_14) node credit_available_hi_lo_14 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_14 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_17 = cat(credit_available_hi_hi_14, credit_available_hi_lo_14) node _credit_available_T_18 = cat(credit_available_hi_17, credit_available_lo_17) node credit_available_lo_lo_15 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_15 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_18 = cat(credit_available_lo_hi_15, credit_available_lo_lo_15) node credit_available_hi_lo_15 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_15 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_18 = cat(credit_available_hi_hi_15, credit_available_hi_lo_15) node _credit_available_T_19 = cat(credit_available_hi_18, credit_available_lo_18) node credit_available_lo_19 = cat(_credit_available_T_17, _credit_available_T_16) node credit_available_hi_19 = cat(_credit_available_T_19, _credit_available_T_18) node _credit_available_T_20 = cat(credit_available_hi_19, credit_available_lo_19) node _credit_available_T_21 = and(_credit_available_T_15, _credit_available_T_20) node credit_available_1 = neq(_credit_available_T_21, UInt<1>(0h0)) node _salloc_arb_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h3)) node _salloc_arb_io_in_2_valid_T_1 = and(_salloc_arb_io_in_2_valid_T, credit_available_1) node _salloc_arb_io_in_2_valid_T_2 = and(_salloc_arb_io_in_2_valid_T_1, input_buffer.io.deq[2].valid) connect salloc_arb.io.in[2].valid, _salloc_arb_io_in_2_valid_T_2 connect salloc_arb.io.in[2].bits.vc_sel.`0`[0], states[2].vc_sel.`0`[0] connect salloc_arb.io.in[2].bits.vc_sel.`0`[1], states[2].vc_sel.`0`[1] connect salloc_arb.io.in[2].bits.vc_sel.`0`[2], states[2].vc_sel.`0`[2] connect salloc_arb.io.in[2].bits.vc_sel.`0`[3], states[2].vc_sel.`0`[3] connect salloc_arb.io.in[2].bits.vc_sel.`0`[4], states[2].vc_sel.`0`[4] connect salloc_arb.io.in[2].bits.vc_sel.`0`[5], states[2].vc_sel.`0`[5] connect salloc_arb.io.in[2].bits.vc_sel.`0`[6], states[2].vc_sel.`0`[6] connect salloc_arb.io.in[2].bits.vc_sel.`0`[7], states[2].vc_sel.`0`[7] connect salloc_arb.io.in[2].bits.vc_sel.`1`[0], states[2].vc_sel.`1`[0] connect salloc_arb.io.in[2].bits.vc_sel.`1`[1], states[2].vc_sel.`1`[1] connect salloc_arb.io.in[2].bits.vc_sel.`1`[2], states[2].vc_sel.`1`[2] connect salloc_arb.io.in[2].bits.vc_sel.`1`[3], states[2].vc_sel.`1`[3] connect salloc_arb.io.in[2].bits.vc_sel.`1`[4], states[2].vc_sel.`1`[4] connect salloc_arb.io.in[2].bits.vc_sel.`1`[5], states[2].vc_sel.`1`[5] connect salloc_arb.io.in[2].bits.vc_sel.`1`[6], states[2].vc_sel.`1`[6] connect salloc_arb.io.in[2].bits.vc_sel.`1`[7], states[2].vc_sel.`1`[7] connect salloc_arb.io.in[2].bits.vc_sel.`2`[0], states[2].vc_sel.`2`[0] connect salloc_arb.io.in[2].bits.vc_sel.`2`[1], states[2].vc_sel.`2`[1] connect salloc_arb.io.in[2].bits.vc_sel.`2`[2], states[2].vc_sel.`2`[2] connect salloc_arb.io.in[2].bits.vc_sel.`2`[3], states[2].vc_sel.`2`[3] connect salloc_arb.io.in[2].bits.vc_sel.`2`[4], states[2].vc_sel.`2`[4] connect salloc_arb.io.in[2].bits.vc_sel.`2`[5], states[2].vc_sel.`2`[5] connect salloc_arb.io.in[2].bits.vc_sel.`2`[6], states[2].vc_sel.`2`[6] connect salloc_arb.io.in[2].bits.vc_sel.`2`[7], states[2].vc_sel.`2`[7] connect salloc_arb.io.in[2].bits.vc_sel.`3`[0], states[2].vc_sel.`3`[0] connect salloc_arb.io.in[2].bits.vc_sel.`3`[1], states[2].vc_sel.`3`[1] connect salloc_arb.io.in[2].bits.vc_sel.`3`[2], states[2].vc_sel.`3`[2] connect salloc_arb.io.in[2].bits.vc_sel.`3`[3], states[2].vc_sel.`3`[3] connect salloc_arb.io.in[2].bits.vc_sel.`3`[4], states[2].vc_sel.`3`[4] connect salloc_arb.io.in[2].bits.vc_sel.`3`[5], states[2].vc_sel.`3`[5] connect salloc_arb.io.in[2].bits.vc_sel.`3`[6], states[2].vc_sel.`3`[6] connect salloc_arb.io.in[2].bits.vc_sel.`3`[7], states[2].vc_sel.`3`[7] connect salloc_arb.io.in[2].bits.tail, input_buffer.io.deq[2].bits.tail node _T_101 = and(salloc_arb.io.in[2].ready, salloc_arb.io.in[2].valid) node _T_102 = and(_T_101, input_buffer.io.deq[2].bits.tail) when _T_102 : connect states[2].g, UInt<3>(0h0) connect input_buffer.io.deq[2].ready, salloc_arb.io.in[2].ready node credit_available_lo_lo_16 = cat(states[3].vc_sel.`0`[1], states[3].vc_sel.`0`[0]) node credit_available_lo_hi_16 = cat(states[3].vc_sel.`0`[3], states[3].vc_sel.`0`[2]) node credit_available_lo_20 = cat(credit_available_lo_hi_16, credit_available_lo_lo_16) node credit_available_hi_lo_16 = cat(states[3].vc_sel.`0`[5], states[3].vc_sel.`0`[4]) node credit_available_hi_hi_16 = cat(states[3].vc_sel.`0`[7], states[3].vc_sel.`0`[6]) node credit_available_hi_20 = cat(credit_available_hi_hi_16, credit_available_hi_lo_16) node _credit_available_T_22 = cat(credit_available_hi_20, credit_available_lo_20) node credit_available_lo_lo_17 = cat(states[3].vc_sel.`1`[1], states[3].vc_sel.`1`[0]) node credit_available_lo_hi_17 = cat(states[3].vc_sel.`1`[3], states[3].vc_sel.`1`[2]) node credit_available_lo_21 = cat(credit_available_lo_hi_17, credit_available_lo_lo_17) node credit_available_hi_lo_17 = cat(states[3].vc_sel.`1`[5], states[3].vc_sel.`1`[4]) node credit_available_hi_hi_17 = cat(states[3].vc_sel.`1`[7], states[3].vc_sel.`1`[6]) node credit_available_hi_21 = cat(credit_available_hi_hi_17, credit_available_hi_lo_17) node _credit_available_T_23 = cat(credit_available_hi_21, credit_available_lo_21) node credit_available_lo_lo_18 = cat(states[3].vc_sel.`2`[1], states[3].vc_sel.`2`[0]) node credit_available_lo_hi_18 = cat(states[3].vc_sel.`2`[3], states[3].vc_sel.`2`[2]) node credit_available_lo_22 = cat(credit_available_lo_hi_18, credit_available_lo_lo_18) node credit_available_hi_lo_18 = cat(states[3].vc_sel.`2`[5], states[3].vc_sel.`2`[4]) node credit_available_hi_hi_18 = cat(states[3].vc_sel.`2`[7], states[3].vc_sel.`2`[6]) node credit_available_hi_22 = cat(credit_available_hi_hi_18, credit_available_hi_lo_18) node _credit_available_T_24 = cat(credit_available_hi_22, credit_available_lo_22) node credit_available_lo_lo_19 = cat(states[3].vc_sel.`3`[1], states[3].vc_sel.`3`[0]) node credit_available_lo_hi_19 = cat(states[3].vc_sel.`3`[3], states[3].vc_sel.`3`[2]) node credit_available_lo_23 = cat(credit_available_lo_hi_19, credit_available_lo_lo_19) node credit_available_hi_lo_19 = cat(states[3].vc_sel.`3`[5], states[3].vc_sel.`3`[4]) node credit_available_hi_hi_19 = cat(states[3].vc_sel.`3`[7], states[3].vc_sel.`3`[6]) node credit_available_hi_23 = cat(credit_available_hi_hi_19, credit_available_hi_lo_19) node _credit_available_T_25 = cat(credit_available_hi_23, credit_available_lo_23) node credit_available_lo_24 = cat(_credit_available_T_23, _credit_available_T_22) node credit_available_hi_24 = cat(_credit_available_T_25, _credit_available_T_24) node _credit_available_T_26 = cat(credit_available_hi_24, credit_available_lo_24) node credit_available_lo_lo_20 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_20 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_25 = cat(credit_available_lo_hi_20, credit_available_lo_lo_20) node credit_available_hi_lo_20 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_20 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_25 = cat(credit_available_hi_hi_20, credit_available_hi_lo_20) node _credit_available_T_27 = cat(credit_available_hi_25, credit_available_lo_25) node credit_available_lo_lo_21 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_21 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_26 = cat(credit_available_lo_hi_21, credit_available_lo_lo_21) node credit_available_hi_lo_21 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_21 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_26 = cat(credit_available_hi_hi_21, credit_available_hi_lo_21) node _credit_available_T_28 = cat(credit_available_hi_26, credit_available_lo_26) node credit_available_lo_lo_22 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_22 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_27 = cat(credit_available_lo_hi_22, credit_available_lo_lo_22) node credit_available_hi_lo_22 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_22 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_27 = cat(credit_available_hi_hi_22, credit_available_hi_lo_22) node _credit_available_T_29 = cat(credit_available_hi_27, credit_available_lo_27) node credit_available_lo_lo_23 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_23 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_28 = cat(credit_available_lo_hi_23, credit_available_lo_lo_23) node credit_available_hi_lo_23 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_23 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_28 = cat(credit_available_hi_hi_23, credit_available_hi_lo_23) node _credit_available_T_30 = cat(credit_available_hi_28, credit_available_lo_28) node credit_available_lo_29 = cat(_credit_available_T_28, _credit_available_T_27) node credit_available_hi_29 = cat(_credit_available_T_30, _credit_available_T_29) node _credit_available_T_31 = cat(credit_available_hi_29, credit_available_lo_29) node _credit_available_T_32 = and(_credit_available_T_26, _credit_available_T_31) node credit_available_2 = neq(_credit_available_T_32, UInt<1>(0h0)) node _salloc_arb_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h3)) node _salloc_arb_io_in_3_valid_T_1 = and(_salloc_arb_io_in_3_valid_T, credit_available_2) node _salloc_arb_io_in_3_valid_T_2 = and(_salloc_arb_io_in_3_valid_T_1, input_buffer.io.deq[3].valid) connect salloc_arb.io.in[3].valid, _salloc_arb_io_in_3_valid_T_2 connect salloc_arb.io.in[3].bits.vc_sel.`0`[0], states[3].vc_sel.`0`[0] connect salloc_arb.io.in[3].bits.vc_sel.`0`[1], states[3].vc_sel.`0`[1] connect salloc_arb.io.in[3].bits.vc_sel.`0`[2], states[3].vc_sel.`0`[2] connect salloc_arb.io.in[3].bits.vc_sel.`0`[3], states[3].vc_sel.`0`[3] connect salloc_arb.io.in[3].bits.vc_sel.`0`[4], states[3].vc_sel.`0`[4] connect salloc_arb.io.in[3].bits.vc_sel.`0`[5], states[3].vc_sel.`0`[5] connect salloc_arb.io.in[3].bits.vc_sel.`0`[6], states[3].vc_sel.`0`[6] connect salloc_arb.io.in[3].bits.vc_sel.`0`[7], states[3].vc_sel.`0`[7] connect salloc_arb.io.in[3].bits.vc_sel.`1`[0], states[3].vc_sel.`1`[0] connect salloc_arb.io.in[3].bits.vc_sel.`1`[1], states[3].vc_sel.`1`[1] connect salloc_arb.io.in[3].bits.vc_sel.`1`[2], states[3].vc_sel.`1`[2] connect salloc_arb.io.in[3].bits.vc_sel.`1`[3], states[3].vc_sel.`1`[3] connect salloc_arb.io.in[3].bits.vc_sel.`1`[4], states[3].vc_sel.`1`[4] connect salloc_arb.io.in[3].bits.vc_sel.`1`[5], states[3].vc_sel.`1`[5] connect salloc_arb.io.in[3].bits.vc_sel.`1`[6], states[3].vc_sel.`1`[6] connect salloc_arb.io.in[3].bits.vc_sel.`1`[7], states[3].vc_sel.`1`[7] connect salloc_arb.io.in[3].bits.vc_sel.`2`[0], states[3].vc_sel.`2`[0] connect salloc_arb.io.in[3].bits.vc_sel.`2`[1], states[3].vc_sel.`2`[1] connect salloc_arb.io.in[3].bits.vc_sel.`2`[2], states[3].vc_sel.`2`[2] connect salloc_arb.io.in[3].bits.vc_sel.`2`[3], states[3].vc_sel.`2`[3] connect salloc_arb.io.in[3].bits.vc_sel.`2`[4], states[3].vc_sel.`2`[4] connect salloc_arb.io.in[3].bits.vc_sel.`2`[5], states[3].vc_sel.`2`[5] connect salloc_arb.io.in[3].bits.vc_sel.`2`[6], states[3].vc_sel.`2`[6] connect salloc_arb.io.in[3].bits.vc_sel.`2`[7], states[3].vc_sel.`2`[7] connect salloc_arb.io.in[3].bits.vc_sel.`3`[0], states[3].vc_sel.`3`[0] connect salloc_arb.io.in[3].bits.vc_sel.`3`[1], states[3].vc_sel.`3`[1] connect salloc_arb.io.in[3].bits.vc_sel.`3`[2], states[3].vc_sel.`3`[2] connect salloc_arb.io.in[3].bits.vc_sel.`3`[3], states[3].vc_sel.`3`[3] connect salloc_arb.io.in[3].bits.vc_sel.`3`[4], states[3].vc_sel.`3`[4] connect salloc_arb.io.in[3].bits.vc_sel.`3`[5], states[3].vc_sel.`3`[5] connect salloc_arb.io.in[3].bits.vc_sel.`3`[6], states[3].vc_sel.`3`[6] connect salloc_arb.io.in[3].bits.vc_sel.`3`[7], states[3].vc_sel.`3`[7] connect salloc_arb.io.in[3].bits.tail, input_buffer.io.deq[3].bits.tail node _T_103 = and(salloc_arb.io.in[3].ready, salloc_arb.io.in[3].valid) node _T_104 = and(_T_103, input_buffer.io.deq[3].bits.tail) when _T_104 : connect states[3].g, UInt<3>(0h0) connect input_buffer.io.deq[3].ready, salloc_arb.io.in[3].ready node credit_available_lo_lo_24 = cat(states[4].vc_sel.`0`[1], states[4].vc_sel.`0`[0]) node credit_available_lo_hi_24 = cat(states[4].vc_sel.`0`[3], states[4].vc_sel.`0`[2]) node credit_available_lo_30 = cat(credit_available_lo_hi_24, credit_available_lo_lo_24) node credit_available_hi_lo_24 = cat(states[4].vc_sel.`0`[5], states[4].vc_sel.`0`[4]) node credit_available_hi_hi_24 = cat(states[4].vc_sel.`0`[7], states[4].vc_sel.`0`[6]) node credit_available_hi_30 = cat(credit_available_hi_hi_24, credit_available_hi_lo_24) node _credit_available_T_33 = cat(credit_available_hi_30, credit_available_lo_30) node credit_available_lo_lo_25 = cat(states[4].vc_sel.`1`[1], states[4].vc_sel.`1`[0]) node credit_available_lo_hi_25 = cat(states[4].vc_sel.`1`[3], states[4].vc_sel.`1`[2]) node credit_available_lo_31 = cat(credit_available_lo_hi_25, credit_available_lo_lo_25) node credit_available_hi_lo_25 = cat(states[4].vc_sel.`1`[5], states[4].vc_sel.`1`[4]) node credit_available_hi_hi_25 = cat(states[4].vc_sel.`1`[7], states[4].vc_sel.`1`[6]) node credit_available_hi_31 = cat(credit_available_hi_hi_25, credit_available_hi_lo_25) node _credit_available_T_34 = cat(credit_available_hi_31, credit_available_lo_31) node credit_available_lo_lo_26 = cat(states[4].vc_sel.`2`[1], states[4].vc_sel.`2`[0]) node credit_available_lo_hi_26 = cat(states[4].vc_sel.`2`[3], states[4].vc_sel.`2`[2]) node credit_available_lo_32 = cat(credit_available_lo_hi_26, credit_available_lo_lo_26) node credit_available_hi_lo_26 = cat(states[4].vc_sel.`2`[5], states[4].vc_sel.`2`[4]) node credit_available_hi_hi_26 = cat(states[4].vc_sel.`2`[7], states[4].vc_sel.`2`[6]) node credit_available_hi_32 = cat(credit_available_hi_hi_26, credit_available_hi_lo_26) node _credit_available_T_35 = cat(credit_available_hi_32, credit_available_lo_32) node credit_available_lo_lo_27 = cat(states[4].vc_sel.`3`[1], states[4].vc_sel.`3`[0]) node credit_available_lo_hi_27 = cat(states[4].vc_sel.`3`[3], states[4].vc_sel.`3`[2]) node credit_available_lo_33 = cat(credit_available_lo_hi_27, credit_available_lo_lo_27) node credit_available_hi_lo_27 = cat(states[4].vc_sel.`3`[5], states[4].vc_sel.`3`[4]) node credit_available_hi_hi_27 = cat(states[4].vc_sel.`3`[7], states[4].vc_sel.`3`[6]) node credit_available_hi_33 = cat(credit_available_hi_hi_27, credit_available_hi_lo_27) node _credit_available_T_36 = cat(credit_available_hi_33, credit_available_lo_33) node credit_available_lo_34 = cat(_credit_available_T_34, _credit_available_T_33) node credit_available_hi_34 = cat(_credit_available_T_36, _credit_available_T_35) node _credit_available_T_37 = cat(credit_available_hi_34, credit_available_lo_34) node credit_available_lo_lo_28 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_28 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_35 = cat(credit_available_lo_hi_28, credit_available_lo_lo_28) node credit_available_hi_lo_28 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_28 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_35 = cat(credit_available_hi_hi_28, credit_available_hi_lo_28) node _credit_available_T_38 = cat(credit_available_hi_35, credit_available_lo_35) node credit_available_lo_lo_29 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_29 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_36 = cat(credit_available_lo_hi_29, credit_available_lo_lo_29) node credit_available_hi_lo_29 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_29 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_36 = cat(credit_available_hi_hi_29, credit_available_hi_lo_29) node _credit_available_T_39 = cat(credit_available_hi_36, credit_available_lo_36) node credit_available_lo_lo_30 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_30 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_37 = cat(credit_available_lo_hi_30, credit_available_lo_lo_30) node credit_available_hi_lo_30 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_30 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_37 = cat(credit_available_hi_hi_30, credit_available_hi_lo_30) node _credit_available_T_40 = cat(credit_available_hi_37, credit_available_lo_37) node credit_available_lo_lo_31 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_31 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_38 = cat(credit_available_lo_hi_31, credit_available_lo_lo_31) node credit_available_hi_lo_31 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_31 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_38 = cat(credit_available_hi_hi_31, credit_available_hi_lo_31) node _credit_available_T_41 = cat(credit_available_hi_38, credit_available_lo_38) node credit_available_lo_39 = cat(_credit_available_T_39, _credit_available_T_38) node credit_available_hi_39 = cat(_credit_available_T_41, _credit_available_T_40) node _credit_available_T_42 = cat(credit_available_hi_39, credit_available_lo_39) node _credit_available_T_43 = and(_credit_available_T_37, _credit_available_T_42) node credit_available_3 = neq(_credit_available_T_43, UInt<1>(0h0)) node _salloc_arb_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h3)) node _salloc_arb_io_in_4_valid_T_1 = and(_salloc_arb_io_in_4_valid_T, credit_available_3) node _salloc_arb_io_in_4_valid_T_2 = and(_salloc_arb_io_in_4_valid_T_1, input_buffer.io.deq[4].valid) connect salloc_arb.io.in[4].valid, _salloc_arb_io_in_4_valid_T_2 connect salloc_arb.io.in[4].bits.vc_sel.`0`[0], states[4].vc_sel.`0`[0] connect salloc_arb.io.in[4].bits.vc_sel.`0`[1], states[4].vc_sel.`0`[1] connect salloc_arb.io.in[4].bits.vc_sel.`0`[2], states[4].vc_sel.`0`[2] connect salloc_arb.io.in[4].bits.vc_sel.`0`[3], states[4].vc_sel.`0`[3] connect salloc_arb.io.in[4].bits.vc_sel.`0`[4], states[4].vc_sel.`0`[4] connect salloc_arb.io.in[4].bits.vc_sel.`0`[5], states[4].vc_sel.`0`[5] connect salloc_arb.io.in[4].bits.vc_sel.`0`[6], states[4].vc_sel.`0`[6] connect salloc_arb.io.in[4].bits.vc_sel.`0`[7], states[4].vc_sel.`0`[7] connect salloc_arb.io.in[4].bits.vc_sel.`1`[0], states[4].vc_sel.`1`[0] connect salloc_arb.io.in[4].bits.vc_sel.`1`[1], states[4].vc_sel.`1`[1] connect salloc_arb.io.in[4].bits.vc_sel.`1`[2], states[4].vc_sel.`1`[2] connect salloc_arb.io.in[4].bits.vc_sel.`1`[3], states[4].vc_sel.`1`[3] connect salloc_arb.io.in[4].bits.vc_sel.`1`[4], states[4].vc_sel.`1`[4] connect salloc_arb.io.in[4].bits.vc_sel.`1`[5], states[4].vc_sel.`1`[5] connect salloc_arb.io.in[4].bits.vc_sel.`1`[6], states[4].vc_sel.`1`[6] connect salloc_arb.io.in[4].bits.vc_sel.`1`[7], states[4].vc_sel.`1`[7] connect salloc_arb.io.in[4].bits.vc_sel.`2`[0], states[4].vc_sel.`2`[0] connect salloc_arb.io.in[4].bits.vc_sel.`2`[1], states[4].vc_sel.`2`[1] connect salloc_arb.io.in[4].bits.vc_sel.`2`[2], states[4].vc_sel.`2`[2] connect salloc_arb.io.in[4].bits.vc_sel.`2`[3], states[4].vc_sel.`2`[3] connect salloc_arb.io.in[4].bits.vc_sel.`2`[4], states[4].vc_sel.`2`[4] connect salloc_arb.io.in[4].bits.vc_sel.`2`[5], states[4].vc_sel.`2`[5] connect salloc_arb.io.in[4].bits.vc_sel.`2`[6], states[4].vc_sel.`2`[6] connect salloc_arb.io.in[4].bits.vc_sel.`2`[7], states[4].vc_sel.`2`[7] connect salloc_arb.io.in[4].bits.vc_sel.`3`[0], states[4].vc_sel.`3`[0] connect salloc_arb.io.in[4].bits.vc_sel.`3`[1], states[4].vc_sel.`3`[1] connect salloc_arb.io.in[4].bits.vc_sel.`3`[2], states[4].vc_sel.`3`[2] connect salloc_arb.io.in[4].bits.vc_sel.`3`[3], states[4].vc_sel.`3`[3] connect salloc_arb.io.in[4].bits.vc_sel.`3`[4], states[4].vc_sel.`3`[4] connect salloc_arb.io.in[4].bits.vc_sel.`3`[5], states[4].vc_sel.`3`[5] connect salloc_arb.io.in[4].bits.vc_sel.`3`[6], states[4].vc_sel.`3`[6] connect salloc_arb.io.in[4].bits.vc_sel.`3`[7], states[4].vc_sel.`3`[7] connect salloc_arb.io.in[4].bits.tail, input_buffer.io.deq[4].bits.tail node _T_105 = and(salloc_arb.io.in[4].ready, salloc_arb.io.in[4].valid) node _T_106 = and(_T_105, input_buffer.io.deq[4].bits.tail) when _T_106 : connect states[4].g, UInt<3>(0h0) connect input_buffer.io.deq[4].ready, salloc_arb.io.in[4].ready node credit_available_lo_lo_32 = cat(states[5].vc_sel.`0`[1], states[5].vc_sel.`0`[0]) node credit_available_lo_hi_32 = cat(states[5].vc_sel.`0`[3], states[5].vc_sel.`0`[2]) node credit_available_lo_40 = cat(credit_available_lo_hi_32, credit_available_lo_lo_32) node credit_available_hi_lo_32 = cat(states[5].vc_sel.`0`[5], states[5].vc_sel.`0`[4]) node credit_available_hi_hi_32 = cat(states[5].vc_sel.`0`[7], states[5].vc_sel.`0`[6]) node credit_available_hi_40 = cat(credit_available_hi_hi_32, credit_available_hi_lo_32) node _credit_available_T_44 = cat(credit_available_hi_40, credit_available_lo_40) node credit_available_lo_lo_33 = cat(states[5].vc_sel.`1`[1], states[5].vc_sel.`1`[0]) node credit_available_lo_hi_33 = cat(states[5].vc_sel.`1`[3], states[5].vc_sel.`1`[2]) node credit_available_lo_41 = cat(credit_available_lo_hi_33, credit_available_lo_lo_33) node credit_available_hi_lo_33 = cat(states[5].vc_sel.`1`[5], states[5].vc_sel.`1`[4]) node credit_available_hi_hi_33 = cat(states[5].vc_sel.`1`[7], states[5].vc_sel.`1`[6]) node credit_available_hi_41 = cat(credit_available_hi_hi_33, credit_available_hi_lo_33) node _credit_available_T_45 = cat(credit_available_hi_41, credit_available_lo_41) node credit_available_lo_lo_34 = cat(states[5].vc_sel.`2`[1], states[5].vc_sel.`2`[0]) node credit_available_lo_hi_34 = cat(states[5].vc_sel.`2`[3], states[5].vc_sel.`2`[2]) node credit_available_lo_42 = cat(credit_available_lo_hi_34, credit_available_lo_lo_34) node credit_available_hi_lo_34 = cat(states[5].vc_sel.`2`[5], states[5].vc_sel.`2`[4]) node credit_available_hi_hi_34 = cat(states[5].vc_sel.`2`[7], states[5].vc_sel.`2`[6]) node credit_available_hi_42 = cat(credit_available_hi_hi_34, credit_available_hi_lo_34) node _credit_available_T_46 = cat(credit_available_hi_42, credit_available_lo_42) node credit_available_lo_lo_35 = cat(states[5].vc_sel.`3`[1], states[5].vc_sel.`3`[0]) node credit_available_lo_hi_35 = cat(states[5].vc_sel.`3`[3], states[5].vc_sel.`3`[2]) node credit_available_lo_43 = cat(credit_available_lo_hi_35, credit_available_lo_lo_35) node credit_available_hi_lo_35 = cat(states[5].vc_sel.`3`[5], states[5].vc_sel.`3`[4]) node credit_available_hi_hi_35 = cat(states[5].vc_sel.`3`[7], states[5].vc_sel.`3`[6]) node credit_available_hi_43 = cat(credit_available_hi_hi_35, credit_available_hi_lo_35) node _credit_available_T_47 = cat(credit_available_hi_43, credit_available_lo_43) node credit_available_lo_44 = cat(_credit_available_T_45, _credit_available_T_44) node credit_available_hi_44 = cat(_credit_available_T_47, _credit_available_T_46) node _credit_available_T_48 = cat(credit_available_hi_44, credit_available_lo_44) node credit_available_lo_lo_36 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_36 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_45 = cat(credit_available_lo_hi_36, credit_available_lo_lo_36) node credit_available_hi_lo_36 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_36 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_45 = cat(credit_available_hi_hi_36, credit_available_hi_lo_36) node _credit_available_T_49 = cat(credit_available_hi_45, credit_available_lo_45) node credit_available_lo_lo_37 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_37 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_46 = cat(credit_available_lo_hi_37, credit_available_lo_lo_37) node credit_available_hi_lo_37 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_37 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_46 = cat(credit_available_hi_hi_37, credit_available_hi_lo_37) node _credit_available_T_50 = cat(credit_available_hi_46, credit_available_lo_46) node credit_available_lo_lo_38 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_38 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_47 = cat(credit_available_lo_hi_38, credit_available_lo_lo_38) node credit_available_hi_lo_38 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_38 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_47 = cat(credit_available_hi_hi_38, credit_available_hi_lo_38) node _credit_available_T_51 = cat(credit_available_hi_47, credit_available_lo_47) node credit_available_lo_lo_39 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_39 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_48 = cat(credit_available_lo_hi_39, credit_available_lo_lo_39) node credit_available_hi_lo_39 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_39 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_48 = cat(credit_available_hi_hi_39, credit_available_hi_lo_39) node _credit_available_T_52 = cat(credit_available_hi_48, credit_available_lo_48) node credit_available_lo_49 = cat(_credit_available_T_50, _credit_available_T_49) node credit_available_hi_49 = cat(_credit_available_T_52, _credit_available_T_51) node _credit_available_T_53 = cat(credit_available_hi_49, credit_available_lo_49) node _credit_available_T_54 = and(_credit_available_T_48, _credit_available_T_53) node credit_available_4 = neq(_credit_available_T_54, UInt<1>(0h0)) node _salloc_arb_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h3)) node _salloc_arb_io_in_5_valid_T_1 = and(_salloc_arb_io_in_5_valid_T, credit_available_4) node _salloc_arb_io_in_5_valid_T_2 = and(_salloc_arb_io_in_5_valid_T_1, input_buffer.io.deq[5].valid) connect salloc_arb.io.in[5].valid, _salloc_arb_io_in_5_valid_T_2 connect salloc_arb.io.in[5].bits.vc_sel.`0`[0], states[5].vc_sel.`0`[0] connect salloc_arb.io.in[5].bits.vc_sel.`0`[1], states[5].vc_sel.`0`[1] connect salloc_arb.io.in[5].bits.vc_sel.`0`[2], states[5].vc_sel.`0`[2] connect salloc_arb.io.in[5].bits.vc_sel.`0`[3], states[5].vc_sel.`0`[3] connect salloc_arb.io.in[5].bits.vc_sel.`0`[4], states[5].vc_sel.`0`[4] connect salloc_arb.io.in[5].bits.vc_sel.`0`[5], states[5].vc_sel.`0`[5] connect salloc_arb.io.in[5].bits.vc_sel.`0`[6], states[5].vc_sel.`0`[6] connect salloc_arb.io.in[5].bits.vc_sel.`0`[7], states[5].vc_sel.`0`[7] connect salloc_arb.io.in[5].bits.vc_sel.`1`[0], states[5].vc_sel.`1`[0] connect salloc_arb.io.in[5].bits.vc_sel.`1`[1], states[5].vc_sel.`1`[1] connect salloc_arb.io.in[5].bits.vc_sel.`1`[2], states[5].vc_sel.`1`[2] connect salloc_arb.io.in[5].bits.vc_sel.`1`[3], states[5].vc_sel.`1`[3] connect salloc_arb.io.in[5].bits.vc_sel.`1`[4], states[5].vc_sel.`1`[4] connect salloc_arb.io.in[5].bits.vc_sel.`1`[5], states[5].vc_sel.`1`[5] connect salloc_arb.io.in[5].bits.vc_sel.`1`[6], states[5].vc_sel.`1`[6] connect salloc_arb.io.in[5].bits.vc_sel.`1`[7], states[5].vc_sel.`1`[7] connect salloc_arb.io.in[5].bits.vc_sel.`2`[0], states[5].vc_sel.`2`[0] connect salloc_arb.io.in[5].bits.vc_sel.`2`[1], states[5].vc_sel.`2`[1] connect salloc_arb.io.in[5].bits.vc_sel.`2`[2], states[5].vc_sel.`2`[2] connect salloc_arb.io.in[5].bits.vc_sel.`2`[3], states[5].vc_sel.`2`[3] connect salloc_arb.io.in[5].bits.vc_sel.`2`[4], states[5].vc_sel.`2`[4] connect salloc_arb.io.in[5].bits.vc_sel.`2`[5], states[5].vc_sel.`2`[5] connect salloc_arb.io.in[5].bits.vc_sel.`2`[6], states[5].vc_sel.`2`[6] connect salloc_arb.io.in[5].bits.vc_sel.`2`[7], states[5].vc_sel.`2`[7] connect salloc_arb.io.in[5].bits.vc_sel.`3`[0], states[5].vc_sel.`3`[0] connect salloc_arb.io.in[5].bits.vc_sel.`3`[1], states[5].vc_sel.`3`[1] connect salloc_arb.io.in[5].bits.vc_sel.`3`[2], states[5].vc_sel.`3`[2] connect salloc_arb.io.in[5].bits.vc_sel.`3`[3], states[5].vc_sel.`3`[3] connect salloc_arb.io.in[5].bits.vc_sel.`3`[4], states[5].vc_sel.`3`[4] connect salloc_arb.io.in[5].bits.vc_sel.`3`[5], states[5].vc_sel.`3`[5] connect salloc_arb.io.in[5].bits.vc_sel.`3`[6], states[5].vc_sel.`3`[6] connect salloc_arb.io.in[5].bits.vc_sel.`3`[7], states[5].vc_sel.`3`[7] connect salloc_arb.io.in[5].bits.tail, input_buffer.io.deq[5].bits.tail node _T_107 = and(salloc_arb.io.in[5].ready, salloc_arb.io.in[5].valid) node _T_108 = and(_T_107, input_buffer.io.deq[5].bits.tail) when _T_108 : connect states[5].g, UInt<3>(0h0) connect input_buffer.io.deq[5].ready, salloc_arb.io.in[5].ready node credit_available_lo_lo_40 = cat(states[6].vc_sel.`0`[1], states[6].vc_sel.`0`[0]) node credit_available_lo_hi_40 = cat(states[6].vc_sel.`0`[3], states[6].vc_sel.`0`[2]) node credit_available_lo_50 = cat(credit_available_lo_hi_40, credit_available_lo_lo_40) node credit_available_hi_lo_40 = cat(states[6].vc_sel.`0`[5], states[6].vc_sel.`0`[4]) node credit_available_hi_hi_40 = cat(states[6].vc_sel.`0`[7], states[6].vc_sel.`0`[6]) node credit_available_hi_50 = cat(credit_available_hi_hi_40, credit_available_hi_lo_40) node _credit_available_T_55 = cat(credit_available_hi_50, credit_available_lo_50) node credit_available_lo_lo_41 = cat(states[6].vc_sel.`1`[1], states[6].vc_sel.`1`[0]) node credit_available_lo_hi_41 = cat(states[6].vc_sel.`1`[3], states[6].vc_sel.`1`[2]) node credit_available_lo_51 = cat(credit_available_lo_hi_41, credit_available_lo_lo_41) node credit_available_hi_lo_41 = cat(states[6].vc_sel.`1`[5], states[6].vc_sel.`1`[4]) node credit_available_hi_hi_41 = cat(states[6].vc_sel.`1`[7], states[6].vc_sel.`1`[6]) node credit_available_hi_51 = cat(credit_available_hi_hi_41, credit_available_hi_lo_41) node _credit_available_T_56 = cat(credit_available_hi_51, credit_available_lo_51) node credit_available_lo_lo_42 = cat(states[6].vc_sel.`2`[1], states[6].vc_sel.`2`[0]) node credit_available_lo_hi_42 = cat(states[6].vc_sel.`2`[3], states[6].vc_sel.`2`[2]) node credit_available_lo_52 = cat(credit_available_lo_hi_42, credit_available_lo_lo_42) node credit_available_hi_lo_42 = cat(states[6].vc_sel.`2`[5], states[6].vc_sel.`2`[4]) node credit_available_hi_hi_42 = cat(states[6].vc_sel.`2`[7], states[6].vc_sel.`2`[6]) node credit_available_hi_52 = cat(credit_available_hi_hi_42, credit_available_hi_lo_42) node _credit_available_T_57 = cat(credit_available_hi_52, credit_available_lo_52) node credit_available_lo_lo_43 = cat(states[6].vc_sel.`3`[1], states[6].vc_sel.`3`[0]) node credit_available_lo_hi_43 = cat(states[6].vc_sel.`3`[3], states[6].vc_sel.`3`[2]) node credit_available_lo_53 = cat(credit_available_lo_hi_43, credit_available_lo_lo_43) node credit_available_hi_lo_43 = cat(states[6].vc_sel.`3`[5], states[6].vc_sel.`3`[4]) node credit_available_hi_hi_43 = cat(states[6].vc_sel.`3`[7], states[6].vc_sel.`3`[6]) node credit_available_hi_53 = cat(credit_available_hi_hi_43, credit_available_hi_lo_43) node _credit_available_T_58 = cat(credit_available_hi_53, credit_available_lo_53) node credit_available_lo_54 = cat(_credit_available_T_56, _credit_available_T_55) node credit_available_hi_54 = cat(_credit_available_T_58, _credit_available_T_57) node _credit_available_T_59 = cat(credit_available_hi_54, credit_available_lo_54) node credit_available_lo_lo_44 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_44 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_55 = cat(credit_available_lo_hi_44, credit_available_lo_lo_44) node credit_available_hi_lo_44 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_44 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_55 = cat(credit_available_hi_hi_44, credit_available_hi_lo_44) node _credit_available_T_60 = cat(credit_available_hi_55, credit_available_lo_55) node credit_available_lo_lo_45 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_45 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_56 = cat(credit_available_lo_hi_45, credit_available_lo_lo_45) node credit_available_hi_lo_45 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_45 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_56 = cat(credit_available_hi_hi_45, credit_available_hi_lo_45) node _credit_available_T_61 = cat(credit_available_hi_56, credit_available_lo_56) node credit_available_lo_lo_46 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_46 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_57 = cat(credit_available_lo_hi_46, credit_available_lo_lo_46) node credit_available_hi_lo_46 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_46 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_57 = cat(credit_available_hi_hi_46, credit_available_hi_lo_46) node _credit_available_T_62 = cat(credit_available_hi_57, credit_available_lo_57) node credit_available_lo_lo_47 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_47 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_58 = cat(credit_available_lo_hi_47, credit_available_lo_lo_47) node credit_available_hi_lo_47 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_47 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_58 = cat(credit_available_hi_hi_47, credit_available_hi_lo_47) node _credit_available_T_63 = cat(credit_available_hi_58, credit_available_lo_58) node credit_available_lo_59 = cat(_credit_available_T_61, _credit_available_T_60) node credit_available_hi_59 = cat(_credit_available_T_63, _credit_available_T_62) node _credit_available_T_64 = cat(credit_available_hi_59, credit_available_lo_59) node _credit_available_T_65 = and(_credit_available_T_59, _credit_available_T_64) node credit_available_5 = neq(_credit_available_T_65, UInt<1>(0h0)) node _salloc_arb_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h3)) node _salloc_arb_io_in_6_valid_T_1 = and(_salloc_arb_io_in_6_valid_T, credit_available_5) node _salloc_arb_io_in_6_valid_T_2 = and(_salloc_arb_io_in_6_valid_T_1, input_buffer.io.deq[6].valid) connect salloc_arb.io.in[6].valid, _salloc_arb_io_in_6_valid_T_2 connect salloc_arb.io.in[6].bits.vc_sel.`0`[0], states[6].vc_sel.`0`[0] connect salloc_arb.io.in[6].bits.vc_sel.`0`[1], states[6].vc_sel.`0`[1] connect salloc_arb.io.in[6].bits.vc_sel.`0`[2], states[6].vc_sel.`0`[2] connect salloc_arb.io.in[6].bits.vc_sel.`0`[3], states[6].vc_sel.`0`[3] connect salloc_arb.io.in[6].bits.vc_sel.`0`[4], states[6].vc_sel.`0`[4] connect salloc_arb.io.in[6].bits.vc_sel.`0`[5], states[6].vc_sel.`0`[5] connect salloc_arb.io.in[6].bits.vc_sel.`0`[6], states[6].vc_sel.`0`[6] connect salloc_arb.io.in[6].bits.vc_sel.`0`[7], states[6].vc_sel.`0`[7] connect salloc_arb.io.in[6].bits.vc_sel.`1`[0], states[6].vc_sel.`1`[0] connect salloc_arb.io.in[6].bits.vc_sel.`1`[1], states[6].vc_sel.`1`[1] connect salloc_arb.io.in[6].bits.vc_sel.`1`[2], states[6].vc_sel.`1`[2] connect salloc_arb.io.in[6].bits.vc_sel.`1`[3], states[6].vc_sel.`1`[3] connect salloc_arb.io.in[6].bits.vc_sel.`1`[4], states[6].vc_sel.`1`[4] connect salloc_arb.io.in[6].bits.vc_sel.`1`[5], states[6].vc_sel.`1`[5] connect salloc_arb.io.in[6].bits.vc_sel.`1`[6], states[6].vc_sel.`1`[6] connect salloc_arb.io.in[6].bits.vc_sel.`1`[7], states[6].vc_sel.`1`[7] connect salloc_arb.io.in[6].bits.vc_sel.`2`[0], states[6].vc_sel.`2`[0] connect salloc_arb.io.in[6].bits.vc_sel.`2`[1], states[6].vc_sel.`2`[1] connect salloc_arb.io.in[6].bits.vc_sel.`2`[2], states[6].vc_sel.`2`[2] connect salloc_arb.io.in[6].bits.vc_sel.`2`[3], states[6].vc_sel.`2`[3] connect salloc_arb.io.in[6].bits.vc_sel.`2`[4], states[6].vc_sel.`2`[4] connect salloc_arb.io.in[6].bits.vc_sel.`2`[5], states[6].vc_sel.`2`[5] connect salloc_arb.io.in[6].bits.vc_sel.`2`[6], states[6].vc_sel.`2`[6] connect salloc_arb.io.in[6].bits.vc_sel.`2`[7], states[6].vc_sel.`2`[7] connect salloc_arb.io.in[6].bits.vc_sel.`3`[0], states[6].vc_sel.`3`[0] connect salloc_arb.io.in[6].bits.vc_sel.`3`[1], states[6].vc_sel.`3`[1] connect salloc_arb.io.in[6].bits.vc_sel.`3`[2], states[6].vc_sel.`3`[2] connect salloc_arb.io.in[6].bits.vc_sel.`3`[3], states[6].vc_sel.`3`[3] connect salloc_arb.io.in[6].bits.vc_sel.`3`[4], states[6].vc_sel.`3`[4] connect salloc_arb.io.in[6].bits.vc_sel.`3`[5], states[6].vc_sel.`3`[5] connect salloc_arb.io.in[6].bits.vc_sel.`3`[6], states[6].vc_sel.`3`[6] connect salloc_arb.io.in[6].bits.vc_sel.`3`[7], states[6].vc_sel.`3`[7] connect salloc_arb.io.in[6].bits.tail, input_buffer.io.deq[6].bits.tail node _T_109 = and(salloc_arb.io.in[6].ready, salloc_arb.io.in[6].valid) node _T_110 = and(_T_109, input_buffer.io.deq[6].bits.tail) when _T_110 : connect states[6].g, UInt<3>(0h0) connect input_buffer.io.deq[6].ready, salloc_arb.io.in[6].ready node credit_available_lo_lo_48 = cat(states[7].vc_sel.`0`[1], states[7].vc_sel.`0`[0]) node credit_available_lo_hi_48 = cat(states[7].vc_sel.`0`[3], states[7].vc_sel.`0`[2]) node credit_available_lo_60 = cat(credit_available_lo_hi_48, credit_available_lo_lo_48) node credit_available_hi_lo_48 = cat(states[7].vc_sel.`0`[5], states[7].vc_sel.`0`[4]) node credit_available_hi_hi_48 = cat(states[7].vc_sel.`0`[7], states[7].vc_sel.`0`[6]) node credit_available_hi_60 = cat(credit_available_hi_hi_48, credit_available_hi_lo_48) node _credit_available_T_66 = cat(credit_available_hi_60, credit_available_lo_60) node credit_available_lo_lo_49 = cat(states[7].vc_sel.`1`[1], states[7].vc_sel.`1`[0]) node credit_available_lo_hi_49 = cat(states[7].vc_sel.`1`[3], states[7].vc_sel.`1`[2]) node credit_available_lo_61 = cat(credit_available_lo_hi_49, credit_available_lo_lo_49) node credit_available_hi_lo_49 = cat(states[7].vc_sel.`1`[5], states[7].vc_sel.`1`[4]) node credit_available_hi_hi_49 = cat(states[7].vc_sel.`1`[7], states[7].vc_sel.`1`[6]) node credit_available_hi_61 = cat(credit_available_hi_hi_49, credit_available_hi_lo_49) node _credit_available_T_67 = cat(credit_available_hi_61, credit_available_lo_61) node credit_available_lo_lo_50 = cat(states[7].vc_sel.`2`[1], states[7].vc_sel.`2`[0]) node credit_available_lo_hi_50 = cat(states[7].vc_sel.`2`[3], states[7].vc_sel.`2`[2]) node credit_available_lo_62 = cat(credit_available_lo_hi_50, credit_available_lo_lo_50) node credit_available_hi_lo_50 = cat(states[7].vc_sel.`2`[5], states[7].vc_sel.`2`[4]) node credit_available_hi_hi_50 = cat(states[7].vc_sel.`2`[7], states[7].vc_sel.`2`[6]) node credit_available_hi_62 = cat(credit_available_hi_hi_50, credit_available_hi_lo_50) node _credit_available_T_68 = cat(credit_available_hi_62, credit_available_lo_62) node credit_available_lo_lo_51 = cat(states[7].vc_sel.`3`[1], states[7].vc_sel.`3`[0]) node credit_available_lo_hi_51 = cat(states[7].vc_sel.`3`[3], states[7].vc_sel.`3`[2]) node credit_available_lo_63 = cat(credit_available_lo_hi_51, credit_available_lo_lo_51) node credit_available_hi_lo_51 = cat(states[7].vc_sel.`3`[5], states[7].vc_sel.`3`[4]) node credit_available_hi_hi_51 = cat(states[7].vc_sel.`3`[7], states[7].vc_sel.`3`[6]) node credit_available_hi_63 = cat(credit_available_hi_hi_51, credit_available_hi_lo_51) node _credit_available_T_69 = cat(credit_available_hi_63, credit_available_lo_63) node credit_available_lo_64 = cat(_credit_available_T_67, _credit_available_T_66) node credit_available_hi_64 = cat(_credit_available_T_69, _credit_available_T_68) node _credit_available_T_70 = cat(credit_available_hi_64, credit_available_lo_64) node credit_available_lo_lo_52 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_52 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_65 = cat(credit_available_lo_hi_52, credit_available_lo_lo_52) node credit_available_hi_lo_52 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_52 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_65 = cat(credit_available_hi_hi_52, credit_available_hi_lo_52) node _credit_available_T_71 = cat(credit_available_hi_65, credit_available_lo_65) node credit_available_lo_lo_53 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_53 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_66 = cat(credit_available_lo_hi_53, credit_available_lo_lo_53) node credit_available_hi_lo_53 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_53 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_66 = cat(credit_available_hi_hi_53, credit_available_hi_lo_53) node _credit_available_T_72 = cat(credit_available_hi_66, credit_available_lo_66) node credit_available_lo_lo_54 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_54 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_67 = cat(credit_available_lo_hi_54, credit_available_lo_lo_54) node credit_available_hi_lo_54 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_54 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_67 = cat(credit_available_hi_hi_54, credit_available_hi_lo_54) node _credit_available_T_73 = cat(credit_available_hi_67, credit_available_lo_67) node credit_available_lo_lo_55 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_55 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_68 = cat(credit_available_lo_hi_55, credit_available_lo_lo_55) node credit_available_hi_lo_55 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_55 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_68 = cat(credit_available_hi_hi_55, credit_available_hi_lo_55) node _credit_available_T_74 = cat(credit_available_hi_68, credit_available_lo_68) node credit_available_lo_69 = cat(_credit_available_T_72, _credit_available_T_71) node credit_available_hi_69 = cat(_credit_available_T_74, _credit_available_T_73) node _credit_available_T_75 = cat(credit_available_hi_69, credit_available_lo_69) node _credit_available_T_76 = and(_credit_available_T_70, _credit_available_T_75) node credit_available_6 = neq(_credit_available_T_76, UInt<1>(0h0)) node _salloc_arb_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h3)) node _salloc_arb_io_in_7_valid_T_1 = and(_salloc_arb_io_in_7_valid_T, credit_available_6) node _salloc_arb_io_in_7_valid_T_2 = and(_salloc_arb_io_in_7_valid_T_1, input_buffer.io.deq[7].valid) connect salloc_arb.io.in[7].valid, _salloc_arb_io_in_7_valid_T_2 connect salloc_arb.io.in[7].bits.vc_sel.`0`[0], states[7].vc_sel.`0`[0] connect salloc_arb.io.in[7].bits.vc_sel.`0`[1], states[7].vc_sel.`0`[1] connect salloc_arb.io.in[7].bits.vc_sel.`0`[2], states[7].vc_sel.`0`[2] connect salloc_arb.io.in[7].bits.vc_sel.`0`[3], states[7].vc_sel.`0`[3] connect salloc_arb.io.in[7].bits.vc_sel.`0`[4], states[7].vc_sel.`0`[4] connect salloc_arb.io.in[7].bits.vc_sel.`0`[5], states[7].vc_sel.`0`[5] connect salloc_arb.io.in[7].bits.vc_sel.`0`[6], states[7].vc_sel.`0`[6] connect salloc_arb.io.in[7].bits.vc_sel.`0`[7], states[7].vc_sel.`0`[7] connect salloc_arb.io.in[7].bits.vc_sel.`1`[0], states[7].vc_sel.`1`[0] connect salloc_arb.io.in[7].bits.vc_sel.`1`[1], states[7].vc_sel.`1`[1] connect salloc_arb.io.in[7].bits.vc_sel.`1`[2], states[7].vc_sel.`1`[2] connect salloc_arb.io.in[7].bits.vc_sel.`1`[3], states[7].vc_sel.`1`[3] connect salloc_arb.io.in[7].bits.vc_sel.`1`[4], states[7].vc_sel.`1`[4] connect salloc_arb.io.in[7].bits.vc_sel.`1`[5], states[7].vc_sel.`1`[5] connect salloc_arb.io.in[7].bits.vc_sel.`1`[6], states[7].vc_sel.`1`[6] connect salloc_arb.io.in[7].bits.vc_sel.`1`[7], states[7].vc_sel.`1`[7] connect salloc_arb.io.in[7].bits.vc_sel.`2`[0], states[7].vc_sel.`2`[0] connect salloc_arb.io.in[7].bits.vc_sel.`2`[1], states[7].vc_sel.`2`[1] connect salloc_arb.io.in[7].bits.vc_sel.`2`[2], states[7].vc_sel.`2`[2] connect salloc_arb.io.in[7].bits.vc_sel.`2`[3], states[7].vc_sel.`2`[3] connect salloc_arb.io.in[7].bits.vc_sel.`2`[4], states[7].vc_sel.`2`[4] connect salloc_arb.io.in[7].bits.vc_sel.`2`[5], states[7].vc_sel.`2`[5] connect salloc_arb.io.in[7].bits.vc_sel.`2`[6], states[7].vc_sel.`2`[6] connect salloc_arb.io.in[7].bits.vc_sel.`2`[7], states[7].vc_sel.`2`[7] connect salloc_arb.io.in[7].bits.vc_sel.`3`[0], states[7].vc_sel.`3`[0] connect salloc_arb.io.in[7].bits.vc_sel.`3`[1], states[7].vc_sel.`3`[1] connect salloc_arb.io.in[7].bits.vc_sel.`3`[2], states[7].vc_sel.`3`[2] connect salloc_arb.io.in[7].bits.vc_sel.`3`[3], states[7].vc_sel.`3`[3] connect salloc_arb.io.in[7].bits.vc_sel.`3`[4], states[7].vc_sel.`3`[4] connect salloc_arb.io.in[7].bits.vc_sel.`3`[5], states[7].vc_sel.`3`[5] connect salloc_arb.io.in[7].bits.vc_sel.`3`[6], states[7].vc_sel.`3`[6] connect salloc_arb.io.in[7].bits.vc_sel.`3`[7], states[7].vc_sel.`3`[7] connect salloc_arb.io.in[7].bits.tail, input_buffer.io.deq[7].bits.tail node _T_111 = and(salloc_arb.io.in[7].ready, salloc_arb.io.in[7].valid) node _T_112 = and(_T_111, input_buffer.io.deq[7].bits.tail) when _T_112 : connect states[7].g, UInt<3>(0h0) connect input_buffer.io.deq[7].ready, salloc_arb.io.in[7].ready node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T) node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2) node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4) node _io_debug_sa_stall_T_6 = eq(salloc_arb.io.in[3].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_7 = and(salloc_arb.io.in[3].valid, _io_debug_sa_stall_T_6) node _io_debug_sa_stall_T_8 = eq(salloc_arb.io.in[4].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_9 = and(salloc_arb.io.in[4].valid, _io_debug_sa_stall_T_8) node _io_debug_sa_stall_T_10 = eq(salloc_arb.io.in[5].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_11 = and(salloc_arb.io.in[5].valid, _io_debug_sa_stall_T_10) node _io_debug_sa_stall_T_12 = eq(salloc_arb.io.in[6].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_13 = and(salloc_arb.io.in[6].valid, _io_debug_sa_stall_T_12) node _io_debug_sa_stall_T_14 = eq(salloc_arb.io.in[7].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_15 = and(salloc_arb.io.in[7].valid, _io_debug_sa_stall_T_14) node _io_debug_sa_stall_T_16 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_3) node _io_debug_sa_stall_T_17 = bits(_io_debug_sa_stall_T_16, 1, 0) node _io_debug_sa_stall_T_18 = add(_io_debug_sa_stall_T_5, _io_debug_sa_stall_T_7) node _io_debug_sa_stall_T_19 = bits(_io_debug_sa_stall_T_18, 1, 0) node _io_debug_sa_stall_T_20 = add(_io_debug_sa_stall_T_17, _io_debug_sa_stall_T_19) node _io_debug_sa_stall_T_21 = bits(_io_debug_sa_stall_T_20, 2, 0) node _io_debug_sa_stall_T_22 = add(_io_debug_sa_stall_T_9, _io_debug_sa_stall_T_11) node _io_debug_sa_stall_T_23 = bits(_io_debug_sa_stall_T_22, 1, 0) node _io_debug_sa_stall_T_24 = add(_io_debug_sa_stall_T_13, _io_debug_sa_stall_T_15) node _io_debug_sa_stall_T_25 = bits(_io_debug_sa_stall_T_24, 1, 0) node _io_debug_sa_stall_T_26 = add(_io_debug_sa_stall_T_23, _io_debug_sa_stall_T_25) node _io_debug_sa_stall_T_27 = bits(_io_debug_sa_stall_T_26, 2, 0) node _io_debug_sa_stall_T_28 = add(_io_debug_sa_stall_T_21, _io_debug_sa_stall_T_27) node _io_debug_sa_stall_T_29 = bits(_io_debug_sa_stall_T_28, 3, 0) connect io.debug.sa_stall, _io_debug_sa_stall_T_29 connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready when io.block : connect salloc_arb.io.out[0].ready, UInt<1>(0h0) connect io.salloc_req[0].valid, UInt<1>(0h0) reg salloc_outs : { valid : UInt<1>, vid : UInt<3>, out_vid : UInt<3>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], clock node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.credit_return, _io_in_credit_return_T_1 node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _io_in_vc_free_T_4 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _io_in_vc_free_T_5 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _io_in_vc_free_T_6 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _io_in_vc_free_T_7 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _io_in_vc_free_T_8 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _io_in_vc_free_T_9 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_10 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_11 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_12 = mux(_io_in_vc_free_T_4, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_13 = mux(_io_in_vc_free_T_5, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_14 = mux(_io_in_vc_free_T_6, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_15 = mux(_io_in_vc_free_T_7, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_16 = mux(_io_in_vc_free_T_8, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_17 = or(_io_in_vc_free_T_9, _io_in_vc_free_T_10) node _io_in_vc_free_T_18 = or(_io_in_vc_free_T_17, _io_in_vc_free_T_11) node _io_in_vc_free_T_19 = or(_io_in_vc_free_T_18, _io_in_vc_free_T_12) node _io_in_vc_free_T_20 = or(_io_in_vc_free_T_19, _io_in_vc_free_T_13) node _io_in_vc_free_T_21 = or(_io_in_vc_free_T_20, _io_in_vc_free_T_14) node _io_in_vc_free_T_22 = or(_io_in_vc_free_T_21, _io_in_vc_free_T_15) node _io_in_vc_free_T_23 = or(_io_in_vc_free_T_22, _io_in_vc_free_T_16) wire _io_in_vc_free_WIRE : UInt<1> connect _io_in_vc_free_WIRE, _io_in_vc_free_T_23 node _io_in_vc_free_T_24 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE) node _io_in_vc_free_T_25 = mux(_io_in_vc_free_T_24, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.vc_free, _io_in_vc_free_T_25 node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) connect salloc_outs[0].valid, _salloc_outs_0_valid_T node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 7, 4) node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 3, 0) node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi) node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo) node salloc_outs_0_vid_hi_1 = bits(_salloc_outs_0_vid_T_1, 3, 2) node salloc_outs_0_vid_lo_1 = bits(_salloc_outs_0_vid_T_1, 1, 0) node _salloc_outs_0_vid_T_2 = orr(salloc_outs_0_vid_hi_1) node _salloc_outs_0_vid_T_3 = or(salloc_outs_0_vid_hi_1, salloc_outs_0_vid_lo_1) node _salloc_outs_0_vid_T_4 = bits(_salloc_outs_0_vid_T_3, 1, 1) node _salloc_outs_0_vid_T_5 = cat(_salloc_outs_0_vid_T_2, _salloc_outs_0_vid_T_4) node _salloc_outs_0_vid_T_6 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_5) connect salloc_outs[0].vid, _salloc_outs_0_vid_T_6 node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _vc_sel_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _vc_sel_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _vc_sel_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _vc_sel_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _vc_sel_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) wire vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]} wire _vc_sel_WIRE : UInt<1>[8] node _vc_sel_T_8 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_9 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_10 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_11 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_12 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_13 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_14 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_15 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_16 = or(_vc_sel_T_8, _vc_sel_T_9) node _vc_sel_T_17 = or(_vc_sel_T_16, _vc_sel_T_10) node _vc_sel_T_18 = or(_vc_sel_T_17, _vc_sel_T_11) node _vc_sel_T_19 = or(_vc_sel_T_18, _vc_sel_T_12) node _vc_sel_T_20 = or(_vc_sel_T_19, _vc_sel_T_13) node _vc_sel_T_21 = or(_vc_sel_T_20, _vc_sel_T_14) node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_15) wire _vc_sel_WIRE_1 : UInt<1> connect _vc_sel_WIRE_1, _vc_sel_T_22 connect _vc_sel_WIRE[0], _vc_sel_WIRE_1 node _vc_sel_T_23 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_24 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_25 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_26 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_27 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_28 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_29 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_30 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_31 = or(_vc_sel_T_23, _vc_sel_T_24) node _vc_sel_T_32 = or(_vc_sel_T_31, _vc_sel_T_25) node _vc_sel_T_33 = or(_vc_sel_T_32, _vc_sel_T_26) node _vc_sel_T_34 = or(_vc_sel_T_33, _vc_sel_T_27) node _vc_sel_T_35 = or(_vc_sel_T_34, _vc_sel_T_28) node _vc_sel_T_36 = or(_vc_sel_T_35, _vc_sel_T_29) node _vc_sel_T_37 = or(_vc_sel_T_36, _vc_sel_T_30) wire _vc_sel_WIRE_2 : UInt<1> connect _vc_sel_WIRE_2, _vc_sel_T_37 connect _vc_sel_WIRE[1], _vc_sel_WIRE_2 node _vc_sel_T_38 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_39 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_40 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_41 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_42 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_43 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_44 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_45 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_46 = or(_vc_sel_T_38, _vc_sel_T_39) node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_40) node _vc_sel_T_48 = or(_vc_sel_T_47, _vc_sel_T_41) node _vc_sel_T_49 = or(_vc_sel_T_48, _vc_sel_T_42) node _vc_sel_T_50 = or(_vc_sel_T_49, _vc_sel_T_43) node _vc_sel_T_51 = or(_vc_sel_T_50, _vc_sel_T_44) node _vc_sel_T_52 = or(_vc_sel_T_51, _vc_sel_T_45) wire _vc_sel_WIRE_3 : UInt<1> connect _vc_sel_WIRE_3, _vc_sel_T_52 connect _vc_sel_WIRE[2], _vc_sel_WIRE_3 node _vc_sel_T_53 = mux(_vc_sel_T, states[0].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_54 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_55 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_56 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_57 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_58 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_59 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_60 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_61 = or(_vc_sel_T_53, _vc_sel_T_54) node _vc_sel_T_62 = or(_vc_sel_T_61, _vc_sel_T_55) node _vc_sel_T_63 = or(_vc_sel_T_62, _vc_sel_T_56) node _vc_sel_T_64 = or(_vc_sel_T_63, _vc_sel_T_57) node _vc_sel_T_65 = or(_vc_sel_T_64, _vc_sel_T_58) node _vc_sel_T_66 = or(_vc_sel_T_65, _vc_sel_T_59) node _vc_sel_T_67 = or(_vc_sel_T_66, _vc_sel_T_60) wire _vc_sel_WIRE_4 : UInt<1> connect _vc_sel_WIRE_4, _vc_sel_T_67 connect _vc_sel_WIRE[3], _vc_sel_WIRE_4 node _vc_sel_T_68 = mux(_vc_sel_T, states[0].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_69 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_70 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_71 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_72 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_73 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_74 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_75 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_76 = or(_vc_sel_T_68, _vc_sel_T_69) node _vc_sel_T_77 = or(_vc_sel_T_76, _vc_sel_T_70) node _vc_sel_T_78 = or(_vc_sel_T_77, _vc_sel_T_71) node _vc_sel_T_79 = or(_vc_sel_T_78, _vc_sel_T_72) node _vc_sel_T_80 = or(_vc_sel_T_79, _vc_sel_T_73) node _vc_sel_T_81 = or(_vc_sel_T_80, _vc_sel_T_74) node _vc_sel_T_82 = or(_vc_sel_T_81, _vc_sel_T_75) wire _vc_sel_WIRE_5 : UInt<1> connect _vc_sel_WIRE_5, _vc_sel_T_82 connect _vc_sel_WIRE[4], _vc_sel_WIRE_5 node _vc_sel_T_83 = mux(_vc_sel_T, states[0].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_84 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_85 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_86 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_87 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_88 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_89 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_90 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_91 = or(_vc_sel_T_83, _vc_sel_T_84) node _vc_sel_T_92 = or(_vc_sel_T_91, _vc_sel_T_85) node _vc_sel_T_93 = or(_vc_sel_T_92, _vc_sel_T_86) node _vc_sel_T_94 = or(_vc_sel_T_93, _vc_sel_T_87) node _vc_sel_T_95 = or(_vc_sel_T_94, _vc_sel_T_88) node _vc_sel_T_96 = or(_vc_sel_T_95, _vc_sel_T_89) node _vc_sel_T_97 = or(_vc_sel_T_96, _vc_sel_T_90) wire _vc_sel_WIRE_6 : UInt<1> connect _vc_sel_WIRE_6, _vc_sel_T_97 connect _vc_sel_WIRE[5], _vc_sel_WIRE_6 node _vc_sel_T_98 = mux(_vc_sel_T, states[0].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_99 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_100 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_101 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_102 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_103 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_104 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_105 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_106 = or(_vc_sel_T_98, _vc_sel_T_99) node _vc_sel_T_107 = or(_vc_sel_T_106, _vc_sel_T_100) node _vc_sel_T_108 = or(_vc_sel_T_107, _vc_sel_T_101) node _vc_sel_T_109 = or(_vc_sel_T_108, _vc_sel_T_102) node _vc_sel_T_110 = or(_vc_sel_T_109, _vc_sel_T_103) node _vc_sel_T_111 = or(_vc_sel_T_110, _vc_sel_T_104) node _vc_sel_T_112 = or(_vc_sel_T_111, _vc_sel_T_105) wire _vc_sel_WIRE_7 : UInt<1> connect _vc_sel_WIRE_7, _vc_sel_T_112 connect _vc_sel_WIRE[6], _vc_sel_WIRE_7 node _vc_sel_T_113 = mux(_vc_sel_T, states[0].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_114 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_115 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_116 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_117 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_118 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_119 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_120 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_121 = or(_vc_sel_T_113, _vc_sel_T_114) node _vc_sel_T_122 = or(_vc_sel_T_121, _vc_sel_T_115) node _vc_sel_T_123 = or(_vc_sel_T_122, _vc_sel_T_116) node _vc_sel_T_124 = or(_vc_sel_T_123, _vc_sel_T_117) node _vc_sel_T_125 = or(_vc_sel_T_124, _vc_sel_T_118) node _vc_sel_T_126 = or(_vc_sel_T_125, _vc_sel_T_119) node _vc_sel_T_127 = or(_vc_sel_T_126, _vc_sel_T_120) wire _vc_sel_WIRE_8 : UInt<1> connect _vc_sel_WIRE_8, _vc_sel_T_127 connect _vc_sel_WIRE[7], _vc_sel_WIRE_8 connect vc_sel.`0`, _vc_sel_WIRE wire _vc_sel_WIRE_9 : UInt<1>[8] node _vc_sel_T_128 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_129 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_130 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_131 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_132 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_133 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_134 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_135 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_136 = or(_vc_sel_T_128, _vc_sel_T_129) node _vc_sel_T_137 = or(_vc_sel_T_136, _vc_sel_T_130) node _vc_sel_T_138 = or(_vc_sel_T_137, _vc_sel_T_131) node _vc_sel_T_139 = or(_vc_sel_T_138, _vc_sel_T_132) node _vc_sel_T_140 = or(_vc_sel_T_139, _vc_sel_T_133) node _vc_sel_T_141 = or(_vc_sel_T_140, _vc_sel_T_134) node _vc_sel_T_142 = or(_vc_sel_T_141, _vc_sel_T_135) wire _vc_sel_WIRE_10 : UInt<1> connect _vc_sel_WIRE_10, _vc_sel_T_142 connect _vc_sel_WIRE_9[0], _vc_sel_WIRE_10 node _vc_sel_T_143 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_144 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_145 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_146 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_147 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_148 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_149 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_150 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_151 = or(_vc_sel_T_143, _vc_sel_T_144) node _vc_sel_T_152 = or(_vc_sel_T_151, _vc_sel_T_145) node _vc_sel_T_153 = or(_vc_sel_T_152, _vc_sel_T_146) node _vc_sel_T_154 = or(_vc_sel_T_153, _vc_sel_T_147) node _vc_sel_T_155 = or(_vc_sel_T_154, _vc_sel_T_148) node _vc_sel_T_156 = or(_vc_sel_T_155, _vc_sel_T_149) node _vc_sel_T_157 = or(_vc_sel_T_156, _vc_sel_T_150) wire _vc_sel_WIRE_11 : UInt<1> connect _vc_sel_WIRE_11, _vc_sel_T_157 connect _vc_sel_WIRE_9[1], _vc_sel_WIRE_11 node _vc_sel_T_158 = mux(_vc_sel_T, states[0].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_159 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_160 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_161 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_162 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_163 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_164 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_165 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_166 = or(_vc_sel_T_158, _vc_sel_T_159) node _vc_sel_T_167 = or(_vc_sel_T_166, _vc_sel_T_160) node _vc_sel_T_168 = or(_vc_sel_T_167, _vc_sel_T_161) node _vc_sel_T_169 = or(_vc_sel_T_168, _vc_sel_T_162) node _vc_sel_T_170 = or(_vc_sel_T_169, _vc_sel_T_163) node _vc_sel_T_171 = or(_vc_sel_T_170, _vc_sel_T_164) node _vc_sel_T_172 = or(_vc_sel_T_171, _vc_sel_T_165) wire _vc_sel_WIRE_12 : UInt<1> connect _vc_sel_WIRE_12, _vc_sel_T_172 connect _vc_sel_WIRE_9[2], _vc_sel_WIRE_12 node _vc_sel_T_173 = mux(_vc_sel_T, states[0].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_174 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_175 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_176 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_177 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_178 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_179 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_180 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_181 = or(_vc_sel_T_173, _vc_sel_T_174) node _vc_sel_T_182 = or(_vc_sel_T_181, _vc_sel_T_175) node _vc_sel_T_183 = or(_vc_sel_T_182, _vc_sel_T_176) node _vc_sel_T_184 = or(_vc_sel_T_183, _vc_sel_T_177) node _vc_sel_T_185 = or(_vc_sel_T_184, _vc_sel_T_178) node _vc_sel_T_186 = or(_vc_sel_T_185, _vc_sel_T_179) node _vc_sel_T_187 = or(_vc_sel_T_186, _vc_sel_T_180) wire _vc_sel_WIRE_13 : UInt<1> connect _vc_sel_WIRE_13, _vc_sel_T_187 connect _vc_sel_WIRE_9[3], _vc_sel_WIRE_13 node _vc_sel_T_188 = mux(_vc_sel_T, states[0].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_189 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_190 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_191 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_192 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_193 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_194 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_195 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_196 = or(_vc_sel_T_188, _vc_sel_T_189) node _vc_sel_T_197 = or(_vc_sel_T_196, _vc_sel_T_190) node _vc_sel_T_198 = or(_vc_sel_T_197, _vc_sel_T_191) node _vc_sel_T_199 = or(_vc_sel_T_198, _vc_sel_T_192) node _vc_sel_T_200 = or(_vc_sel_T_199, _vc_sel_T_193) node _vc_sel_T_201 = or(_vc_sel_T_200, _vc_sel_T_194) node _vc_sel_T_202 = or(_vc_sel_T_201, _vc_sel_T_195) wire _vc_sel_WIRE_14 : UInt<1> connect _vc_sel_WIRE_14, _vc_sel_T_202 connect _vc_sel_WIRE_9[4], _vc_sel_WIRE_14 node _vc_sel_T_203 = mux(_vc_sel_T, states[0].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_204 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_205 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_206 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_207 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_208 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_209 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_210 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_211 = or(_vc_sel_T_203, _vc_sel_T_204) node _vc_sel_T_212 = or(_vc_sel_T_211, _vc_sel_T_205) node _vc_sel_T_213 = or(_vc_sel_T_212, _vc_sel_T_206) node _vc_sel_T_214 = or(_vc_sel_T_213, _vc_sel_T_207) node _vc_sel_T_215 = or(_vc_sel_T_214, _vc_sel_T_208) node _vc_sel_T_216 = or(_vc_sel_T_215, _vc_sel_T_209) node _vc_sel_T_217 = or(_vc_sel_T_216, _vc_sel_T_210) wire _vc_sel_WIRE_15 : UInt<1> connect _vc_sel_WIRE_15, _vc_sel_T_217 connect _vc_sel_WIRE_9[5], _vc_sel_WIRE_15 node _vc_sel_T_218 = mux(_vc_sel_T, states[0].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_219 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_220 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_221 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_222 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_223 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_224 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_225 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_226 = or(_vc_sel_T_218, _vc_sel_T_219) node _vc_sel_T_227 = or(_vc_sel_T_226, _vc_sel_T_220) node _vc_sel_T_228 = or(_vc_sel_T_227, _vc_sel_T_221) node _vc_sel_T_229 = or(_vc_sel_T_228, _vc_sel_T_222) node _vc_sel_T_230 = or(_vc_sel_T_229, _vc_sel_T_223) node _vc_sel_T_231 = or(_vc_sel_T_230, _vc_sel_T_224) node _vc_sel_T_232 = or(_vc_sel_T_231, _vc_sel_T_225) wire _vc_sel_WIRE_16 : UInt<1> connect _vc_sel_WIRE_16, _vc_sel_T_232 connect _vc_sel_WIRE_9[6], _vc_sel_WIRE_16 node _vc_sel_T_233 = mux(_vc_sel_T, states[0].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_234 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_235 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_236 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_237 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_238 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_239 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_240 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_241 = or(_vc_sel_T_233, _vc_sel_T_234) node _vc_sel_T_242 = or(_vc_sel_T_241, _vc_sel_T_235) node _vc_sel_T_243 = or(_vc_sel_T_242, _vc_sel_T_236) node _vc_sel_T_244 = or(_vc_sel_T_243, _vc_sel_T_237) node _vc_sel_T_245 = or(_vc_sel_T_244, _vc_sel_T_238) node _vc_sel_T_246 = or(_vc_sel_T_245, _vc_sel_T_239) node _vc_sel_T_247 = or(_vc_sel_T_246, _vc_sel_T_240) wire _vc_sel_WIRE_17 : UInt<1> connect _vc_sel_WIRE_17, _vc_sel_T_247 connect _vc_sel_WIRE_9[7], _vc_sel_WIRE_17 connect vc_sel.`1`, _vc_sel_WIRE_9 wire _vc_sel_WIRE_18 : UInt<1>[8] node _vc_sel_T_248 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_249 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_250 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_251 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_252 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_253 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_254 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_255 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_256 = or(_vc_sel_T_248, _vc_sel_T_249) node _vc_sel_T_257 = or(_vc_sel_T_256, _vc_sel_T_250) node _vc_sel_T_258 = or(_vc_sel_T_257, _vc_sel_T_251) node _vc_sel_T_259 = or(_vc_sel_T_258, _vc_sel_T_252) node _vc_sel_T_260 = or(_vc_sel_T_259, _vc_sel_T_253) node _vc_sel_T_261 = or(_vc_sel_T_260, _vc_sel_T_254) node _vc_sel_T_262 = or(_vc_sel_T_261, _vc_sel_T_255) wire _vc_sel_WIRE_19 : UInt<1> connect _vc_sel_WIRE_19, _vc_sel_T_262 connect _vc_sel_WIRE_18[0], _vc_sel_WIRE_19 node _vc_sel_T_263 = mux(_vc_sel_T, states[0].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_264 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_265 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_266 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_267 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_268 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_269 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_270 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_271 = or(_vc_sel_T_263, _vc_sel_T_264) node _vc_sel_T_272 = or(_vc_sel_T_271, _vc_sel_T_265) node _vc_sel_T_273 = or(_vc_sel_T_272, _vc_sel_T_266) node _vc_sel_T_274 = or(_vc_sel_T_273, _vc_sel_T_267) node _vc_sel_T_275 = or(_vc_sel_T_274, _vc_sel_T_268) node _vc_sel_T_276 = or(_vc_sel_T_275, _vc_sel_T_269) node _vc_sel_T_277 = or(_vc_sel_T_276, _vc_sel_T_270) wire _vc_sel_WIRE_20 : UInt<1> connect _vc_sel_WIRE_20, _vc_sel_T_277 connect _vc_sel_WIRE_18[1], _vc_sel_WIRE_20 node _vc_sel_T_278 = mux(_vc_sel_T, states[0].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_279 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_280 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_281 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_282 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_283 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_284 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_285 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_286 = or(_vc_sel_T_278, _vc_sel_T_279) node _vc_sel_T_287 = or(_vc_sel_T_286, _vc_sel_T_280) node _vc_sel_T_288 = or(_vc_sel_T_287, _vc_sel_T_281) node _vc_sel_T_289 = or(_vc_sel_T_288, _vc_sel_T_282) node _vc_sel_T_290 = or(_vc_sel_T_289, _vc_sel_T_283) node _vc_sel_T_291 = or(_vc_sel_T_290, _vc_sel_T_284) node _vc_sel_T_292 = or(_vc_sel_T_291, _vc_sel_T_285) wire _vc_sel_WIRE_21 : UInt<1> connect _vc_sel_WIRE_21, _vc_sel_T_292 connect _vc_sel_WIRE_18[2], _vc_sel_WIRE_21 node _vc_sel_T_293 = mux(_vc_sel_T, states[0].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_294 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_295 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_296 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_297 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_298 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_299 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_300 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_301 = or(_vc_sel_T_293, _vc_sel_T_294) node _vc_sel_T_302 = or(_vc_sel_T_301, _vc_sel_T_295) node _vc_sel_T_303 = or(_vc_sel_T_302, _vc_sel_T_296) node _vc_sel_T_304 = or(_vc_sel_T_303, _vc_sel_T_297) node _vc_sel_T_305 = or(_vc_sel_T_304, _vc_sel_T_298) node _vc_sel_T_306 = or(_vc_sel_T_305, _vc_sel_T_299) node _vc_sel_T_307 = or(_vc_sel_T_306, _vc_sel_T_300) wire _vc_sel_WIRE_22 : UInt<1> connect _vc_sel_WIRE_22, _vc_sel_T_307 connect _vc_sel_WIRE_18[3], _vc_sel_WIRE_22 node _vc_sel_T_308 = mux(_vc_sel_T, states[0].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_309 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_310 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_311 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_312 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_313 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_314 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_315 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_316 = or(_vc_sel_T_308, _vc_sel_T_309) node _vc_sel_T_317 = or(_vc_sel_T_316, _vc_sel_T_310) node _vc_sel_T_318 = or(_vc_sel_T_317, _vc_sel_T_311) node _vc_sel_T_319 = or(_vc_sel_T_318, _vc_sel_T_312) node _vc_sel_T_320 = or(_vc_sel_T_319, _vc_sel_T_313) node _vc_sel_T_321 = or(_vc_sel_T_320, _vc_sel_T_314) node _vc_sel_T_322 = or(_vc_sel_T_321, _vc_sel_T_315) wire _vc_sel_WIRE_23 : UInt<1> connect _vc_sel_WIRE_23, _vc_sel_T_322 connect _vc_sel_WIRE_18[4], _vc_sel_WIRE_23 node _vc_sel_T_323 = mux(_vc_sel_T, states[0].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_324 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_325 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_326 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_327 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_328 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_329 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_330 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_331 = or(_vc_sel_T_323, _vc_sel_T_324) node _vc_sel_T_332 = or(_vc_sel_T_331, _vc_sel_T_325) node _vc_sel_T_333 = or(_vc_sel_T_332, _vc_sel_T_326) node _vc_sel_T_334 = or(_vc_sel_T_333, _vc_sel_T_327) node _vc_sel_T_335 = or(_vc_sel_T_334, _vc_sel_T_328) node _vc_sel_T_336 = or(_vc_sel_T_335, _vc_sel_T_329) node _vc_sel_T_337 = or(_vc_sel_T_336, _vc_sel_T_330) wire _vc_sel_WIRE_24 : UInt<1> connect _vc_sel_WIRE_24, _vc_sel_T_337 connect _vc_sel_WIRE_18[5], _vc_sel_WIRE_24 node _vc_sel_T_338 = mux(_vc_sel_T, states[0].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_339 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_340 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_341 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_342 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_343 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_344 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_345 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_346 = or(_vc_sel_T_338, _vc_sel_T_339) node _vc_sel_T_347 = or(_vc_sel_T_346, _vc_sel_T_340) node _vc_sel_T_348 = or(_vc_sel_T_347, _vc_sel_T_341) node _vc_sel_T_349 = or(_vc_sel_T_348, _vc_sel_T_342) node _vc_sel_T_350 = or(_vc_sel_T_349, _vc_sel_T_343) node _vc_sel_T_351 = or(_vc_sel_T_350, _vc_sel_T_344) node _vc_sel_T_352 = or(_vc_sel_T_351, _vc_sel_T_345) wire _vc_sel_WIRE_25 : UInt<1> connect _vc_sel_WIRE_25, _vc_sel_T_352 connect _vc_sel_WIRE_18[6], _vc_sel_WIRE_25 node _vc_sel_T_353 = mux(_vc_sel_T, states[0].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_354 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_355 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_356 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_357 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_358 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_359 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_360 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_361 = or(_vc_sel_T_353, _vc_sel_T_354) node _vc_sel_T_362 = or(_vc_sel_T_361, _vc_sel_T_355) node _vc_sel_T_363 = or(_vc_sel_T_362, _vc_sel_T_356) node _vc_sel_T_364 = or(_vc_sel_T_363, _vc_sel_T_357) node _vc_sel_T_365 = or(_vc_sel_T_364, _vc_sel_T_358) node _vc_sel_T_366 = or(_vc_sel_T_365, _vc_sel_T_359) node _vc_sel_T_367 = or(_vc_sel_T_366, _vc_sel_T_360) wire _vc_sel_WIRE_26 : UInt<1> connect _vc_sel_WIRE_26, _vc_sel_T_367 connect _vc_sel_WIRE_18[7], _vc_sel_WIRE_26 connect vc_sel.`2`, _vc_sel_WIRE_18 wire _vc_sel_WIRE_27 : UInt<1>[8] node _vc_sel_T_368 = mux(_vc_sel_T, states[0].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_369 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_370 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_371 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_372 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_373 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_374 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_375 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_376 = or(_vc_sel_T_368, _vc_sel_T_369) node _vc_sel_T_377 = or(_vc_sel_T_376, _vc_sel_T_370) node _vc_sel_T_378 = or(_vc_sel_T_377, _vc_sel_T_371) node _vc_sel_T_379 = or(_vc_sel_T_378, _vc_sel_T_372) node _vc_sel_T_380 = or(_vc_sel_T_379, _vc_sel_T_373) node _vc_sel_T_381 = or(_vc_sel_T_380, _vc_sel_T_374) node _vc_sel_T_382 = or(_vc_sel_T_381, _vc_sel_T_375) wire _vc_sel_WIRE_28 : UInt<1> connect _vc_sel_WIRE_28, _vc_sel_T_382 connect _vc_sel_WIRE_27[0], _vc_sel_WIRE_28 node _vc_sel_T_383 = mux(_vc_sel_T, states[0].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_384 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_385 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_386 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_387 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_388 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_389 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_390 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_391 = or(_vc_sel_T_383, _vc_sel_T_384) node _vc_sel_T_392 = or(_vc_sel_T_391, _vc_sel_T_385) node _vc_sel_T_393 = or(_vc_sel_T_392, _vc_sel_T_386) node _vc_sel_T_394 = or(_vc_sel_T_393, _vc_sel_T_387) node _vc_sel_T_395 = or(_vc_sel_T_394, _vc_sel_T_388) node _vc_sel_T_396 = or(_vc_sel_T_395, _vc_sel_T_389) node _vc_sel_T_397 = or(_vc_sel_T_396, _vc_sel_T_390) wire _vc_sel_WIRE_29 : UInt<1> connect _vc_sel_WIRE_29, _vc_sel_T_397 connect _vc_sel_WIRE_27[1], _vc_sel_WIRE_29 node _vc_sel_T_398 = mux(_vc_sel_T, states[0].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_399 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_400 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_401 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_402 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_403 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_404 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_405 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_406 = or(_vc_sel_T_398, _vc_sel_T_399) node _vc_sel_T_407 = or(_vc_sel_T_406, _vc_sel_T_400) node _vc_sel_T_408 = or(_vc_sel_T_407, _vc_sel_T_401) node _vc_sel_T_409 = or(_vc_sel_T_408, _vc_sel_T_402) node _vc_sel_T_410 = or(_vc_sel_T_409, _vc_sel_T_403) node _vc_sel_T_411 = or(_vc_sel_T_410, _vc_sel_T_404) node _vc_sel_T_412 = or(_vc_sel_T_411, _vc_sel_T_405) wire _vc_sel_WIRE_30 : UInt<1> connect _vc_sel_WIRE_30, _vc_sel_T_412 connect _vc_sel_WIRE_27[2], _vc_sel_WIRE_30 node _vc_sel_T_413 = mux(_vc_sel_T, states[0].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_414 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_415 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_416 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_417 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_418 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_419 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_420 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_421 = or(_vc_sel_T_413, _vc_sel_T_414) node _vc_sel_T_422 = or(_vc_sel_T_421, _vc_sel_T_415) node _vc_sel_T_423 = or(_vc_sel_T_422, _vc_sel_T_416) node _vc_sel_T_424 = or(_vc_sel_T_423, _vc_sel_T_417) node _vc_sel_T_425 = or(_vc_sel_T_424, _vc_sel_T_418) node _vc_sel_T_426 = or(_vc_sel_T_425, _vc_sel_T_419) node _vc_sel_T_427 = or(_vc_sel_T_426, _vc_sel_T_420) wire _vc_sel_WIRE_31 : UInt<1> connect _vc_sel_WIRE_31, _vc_sel_T_427 connect _vc_sel_WIRE_27[3], _vc_sel_WIRE_31 node _vc_sel_T_428 = mux(_vc_sel_T, states[0].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_429 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_430 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_431 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_432 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_433 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_434 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_435 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_436 = or(_vc_sel_T_428, _vc_sel_T_429) node _vc_sel_T_437 = or(_vc_sel_T_436, _vc_sel_T_430) node _vc_sel_T_438 = or(_vc_sel_T_437, _vc_sel_T_431) node _vc_sel_T_439 = or(_vc_sel_T_438, _vc_sel_T_432) node _vc_sel_T_440 = or(_vc_sel_T_439, _vc_sel_T_433) node _vc_sel_T_441 = or(_vc_sel_T_440, _vc_sel_T_434) node _vc_sel_T_442 = or(_vc_sel_T_441, _vc_sel_T_435) wire _vc_sel_WIRE_32 : UInt<1> connect _vc_sel_WIRE_32, _vc_sel_T_442 connect _vc_sel_WIRE_27[4], _vc_sel_WIRE_32 node _vc_sel_T_443 = mux(_vc_sel_T, states[0].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_444 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_445 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_446 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_447 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_448 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_449 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_450 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_451 = or(_vc_sel_T_443, _vc_sel_T_444) node _vc_sel_T_452 = or(_vc_sel_T_451, _vc_sel_T_445) node _vc_sel_T_453 = or(_vc_sel_T_452, _vc_sel_T_446) node _vc_sel_T_454 = or(_vc_sel_T_453, _vc_sel_T_447) node _vc_sel_T_455 = or(_vc_sel_T_454, _vc_sel_T_448) node _vc_sel_T_456 = or(_vc_sel_T_455, _vc_sel_T_449) node _vc_sel_T_457 = or(_vc_sel_T_456, _vc_sel_T_450) wire _vc_sel_WIRE_33 : UInt<1> connect _vc_sel_WIRE_33, _vc_sel_T_457 connect _vc_sel_WIRE_27[5], _vc_sel_WIRE_33 node _vc_sel_T_458 = mux(_vc_sel_T, states[0].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_459 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_460 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_461 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_462 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_463 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_464 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_465 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_466 = or(_vc_sel_T_458, _vc_sel_T_459) node _vc_sel_T_467 = or(_vc_sel_T_466, _vc_sel_T_460) node _vc_sel_T_468 = or(_vc_sel_T_467, _vc_sel_T_461) node _vc_sel_T_469 = or(_vc_sel_T_468, _vc_sel_T_462) node _vc_sel_T_470 = or(_vc_sel_T_469, _vc_sel_T_463) node _vc_sel_T_471 = or(_vc_sel_T_470, _vc_sel_T_464) node _vc_sel_T_472 = or(_vc_sel_T_471, _vc_sel_T_465) wire _vc_sel_WIRE_34 : UInt<1> connect _vc_sel_WIRE_34, _vc_sel_T_472 connect _vc_sel_WIRE_27[6], _vc_sel_WIRE_34 node _vc_sel_T_473 = mux(_vc_sel_T, states[0].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_474 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_475 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_476 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_477 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_478 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_479 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_480 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_481 = or(_vc_sel_T_473, _vc_sel_T_474) node _vc_sel_T_482 = or(_vc_sel_T_481, _vc_sel_T_475) node _vc_sel_T_483 = or(_vc_sel_T_482, _vc_sel_T_476) node _vc_sel_T_484 = or(_vc_sel_T_483, _vc_sel_T_477) node _vc_sel_T_485 = or(_vc_sel_T_484, _vc_sel_T_478) node _vc_sel_T_486 = or(_vc_sel_T_485, _vc_sel_T_479) node _vc_sel_T_487 = or(_vc_sel_T_486, _vc_sel_T_480) wire _vc_sel_WIRE_35 : UInt<1> connect _vc_sel_WIRE_35, _vc_sel_T_487 connect _vc_sel_WIRE_27[7], _vc_sel_WIRE_35 connect vc_sel.`3`, _vc_sel_WIRE_27 node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1]) node _channel_oh_T_1 = or(_channel_oh_T, vc_sel.`0`[2]) node _channel_oh_T_2 = or(_channel_oh_T_1, vc_sel.`0`[3]) node _channel_oh_T_3 = or(_channel_oh_T_2, vc_sel.`0`[4]) node _channel_oh_T_4 = or(_channel_oh_T_3, vc_sel.`0`[5]) node _channel_oh_T_5 = or(_channel_oh_T_4, vc_sel.`0`[6]) node channel_oh_0 = or(_channel_oh_T_5, vc_sel.`0`[7]) node _channel_oh_T_6 = or(vc_sel.`1`[0], vc_sel.`1`[1]) node _channel_oh_T_7 = or(_channel_oh_T_6, vc_sel.`1`[2]) node _channel_oh_T_8 = or(_channel_oh_T_7, vc_sel.`1`[3]) node _channel_oh_T_9 = or(_channel_oh_T_8, vc_sel.`1`[4]) node _channel_oh_T_10 = or(_channel_oh_T_9, vc_sel.`1`[5]) node _channel_oh_T_11 = or(_channel_oh_T_10, vc_sel.`1`[6]) node channel_oh_1 = or(_channel_oh_T_11, vc_sel.`1`[7]) node _channel_oh_T_12 = or(vc_sel.`2`[0], vc_sel.`2`[1]) node _channel_oh_T_13 = or(_channel_oh_T_12, vc_sel.`2`[2]) node _channel_oh_T_14 = or(_channel_oh_T_13, vc_sel.`2`[3]) node _channel_oh_T_15 = or(_channel_oh_T_14, vc_sel.`2`[4]) node _channel_oh_T_16 = or(_channel_oh_T_15, vc_sel.`2`[5]) node _channel_oh_T_17 = or(_channel_oh_T_16, vc_sel.`2`[6]) node channel_oh_2 = or(_channel_oh_T_17, vc_sel.`2`[7]) node _channel_oh_T_18 = or(vc_sel.`3`[0], vc_sel.`3`[1]) node _channel_oh_T_19 = or(_channel_oh_T_18, vc_sel.`3`[2]) node _channel_oh_T_20 = or(_channel_oh_T_19, vc_sel.`3`[3]) node _channel_oh_T_21 = or(_channel_oh_T_20, vc_sel.`3`[4]) node _channel_oh_T_22 = or(_channel_oh_T_21, vc_sel.`3`[5]) node _channel_oh_T_23 = or(_channel_oh_T_22, vc_sel.`3`[6]) node channel_oh_3 = or(_channel_oh_T_23, vc_sel.`3`[7]) node virt_channel_lo_lo = cat(vc_sel.`0`[1], vc_sel.`0`[0]) node virt_channel_lo_hi = cat(vc_sel.`0`[3], vc_sel.`0`[2]) node virt_channel_lo = cat(virt_channel_lo_hi, virt_channel_lo_lo) node virt_channel_hi_lo = cat(vc_sel.`0`[5], vc_sel.`0`[4]) node virt_channel_hi_hi = cat(vc_sel.`0`[7], vc_sel.`0`[6]) node virt_channel_hi = cat(virt_channel_hi_hi, virt_channel_hi_lo) node _virt_channel_T = cat(virt_channel_hi, virt_channel_lo) node virt_channel_hi_1 = bits(_virt_channel_T, 7, 4) node virt_channel_lo_1 = bits(_virt_channel_T, 3, 0) node _virt_channel_T_1 = orr(virt_channel_hi_1) node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo_1) node virt_channel_hi_2 = bits(_virt_channel_T_2, 3, 2) node virt_channel_lo_2 = bits(_virt_channel_T_2, 1, 0) node _virt_channel_T_3 = orr(virt_channel_hi_2) node _virt_channel_T_4 = or(virt_channel_hi_2, virt_channel_lo_2) node _virt_channel_T_5 = bits(_virt_channel_T_4, 1, 1) node _virt_channel_T_6 = cat(_virt_channel_T_3, _virt_channel_T_5) node _virt_channel_T_7 = cat(_virt_channel_T_1, _virt_channel_T_6) node virt_channel_lo_lo_1 = cat(vc_sel.`1`[1], vc_sel.`1`[0]) node virt_channel_lo_hi_1 = cat(vc_sel.`1`[3], vc_sel.`1`[2]) node virt_channel_lo_3 = cat(virt_channel_lo_hi_1, virt_channel_lo_lo_1) node virt_channel_hi_lo_1 = cat(vc_sel.`1`[5], vc_sel.`1`[4]) node virt_channel_hi_hi_1 = cat(vc_sel.`1`[7], vc_sel.`1`[6]) node virt_channel_hi_3 = cat(virt_channel_hi_hi_1, virt_channel_hi_lo_1) node _virt_channel_T_8 = cat(virt_channel_hi_3, virt_channel_lo_3) node virt_channel_hi_4 = bits(_virt_channel_T_8, 7, 4) node virt_channel_lo_4 = bits(_virt_channel_T_8, 3, 0) node _virt_channel_T_9 = orr(virt_channel_hi_4) node _virt_channel_T_10 = or(virt_channel_hi_4, virt_channel_lo_4) node virt_channel_hi_5 = bits(_virt_channel_T_10, 3, 2) node virt_channel_lo_5 = bits(_virt_channel_T_10, 1, 0) node _virt_channel_T_11 = orr(virt_channel_hi_5) node _virt_channel_T_12 = or(virt_channel_hi_5, virt_channel_lo_5) node _virt_channel_T_13 = bits(_virt_channel_T_12, 1, 1) node _virt_channel_T_14 = cat(_virt_channel_T_11, _virt_channel_T_13) node _virt_channel_T_15 = cat(_virt_channel_T_9, _virt_channel_T_14) node virt_channel_lo_lo_2 = cat(vc_sel.`2`[1], vc_sel.`2`[0]) node virt_channel_lo_hi_2 = cat(vc_sel.`2`[3], vc_sel.`2`[2]) node virt_channel_lo_6 = cat(virt_channel_lo_hi_2, virt_channel_lo_lo_2) node virt_channel_hi_lo_2 = cat(vc_sel.`2`[5], vc_sel.`2`[4]) node virt_channel_hi_hi_2 = cat(vc_sel.`2`[7], vc_sel.`2`[6]) node virt_channel_hi_6 = cat(virt_channel_hi_hi_2, virt_channel_hi_lo_2) node _virt_channel_T_16 = cat(virt_channel_hi_6, virt_channel_lo_6) node virt_channel_hi_7 = bits(_virt_channel_T_16, 7, 4) node virt_channel_lo_7 = bits(_virt_channel_T_16, 3, 0) node _virt_channel_T_17 = orr(virt_channel_hi_7) node _virt_channel_T_18 = or(virt_channel_hi_7, virt_channel_lo_7) node virt_channel_hi_8 = bits(_virt_channel_T_18, 3, 2) node virt_channel_lo_8 = bits(_virt_channel_T_18, 1, 0) node _virt_channel_T_19 = orr(virt_channel_hi_8) node _virt_channel_T_20 = or(virt_channel_hi_8, virt_channel_lo_8) node _virt_channel_T_21 = bits(_virt_channel_T_20, 1, 1) node _virt_channel_T_22 = cat(_virt_channel_T_19, _virt_channel_T_21) node _virt_channel_T_23 = cat(_virt_channel_T_17, _virt_channel_T_22) node virt_channel_lo_lo_3 = cat(vc_sel.`3`[1], vc_sel.`3`[0]) node virt_channel_lo_hi_3 = cat(vc_sel.`3`[3], vc_sel.`3`[2]) node virt_channel_lo_9 = cat(virt_channel_lo_hi_3, virt_channel_lo_lo_3) node virt_channel_hi_lo_3 = cat(vc_sel.`3`[5], vc_sel.`3`[4]) node virt_channel_hi_hi_3 = cat(vc_sel.`3`[7], vc_sel.`3`[6]) node virt_channel_hi_9 = cat(virt_channel_hi_hi_3, virt_channel_hi_lo_3) node _virt_channel_T_24 = cat(virt_channel_hi_9, virt_channel_lo_9) node virt_channel_hi_10 = bits(_virt_channel_T_24, 7, 4) node virt_channel_lo_10 = bits(_virt_channel_T_24, 3, 0) node _virt_channel_T_25 = orr(virt_channel_hi_10) node _virt_channel_T_26 = or(virt_channel_hi_10, virt_channel_lo_10) node virt_channel_hi_11 = bits(_virt_channel_T_26, 3, 2) node virt_channel_lo_11 = bits(_virt_channel_T_26, 1, 0) node _virt_channel_T_27 = orr(virt_channel_hi_11) node _virt_channel_T_28 = or(virt_channel_hi_11, virt_channel_lo_11) node _virt_channel_T_29 = bits(_virt_channel_T_28, 1, 1) node _virt_channel_T_30 = cat(_virt_channel_T_27, _virt_channel_T_29) node _virt_channel_T_31 = cat(_virt_channel_T_25, _virt_channel_T_30) node _virt_channel_T_32 = mux(channel_oh_0, _virt_channel_T_7, UInt<1>(0h0)) node _virt_channel_T_33 = mux(channel_oh_1, _virt_channel_T_15, UInt<1>(0h0)) node _virt_channel_T_34 = mux(channel_oh_2, _virt_channel_T_23, UInt<1>(0h0)) node _virt_channel_T_35 = mux(channel_oh_3, _virt_channel_T_31, UInt<1>(0h0)) node _virt_channel_T_36 = or(_virt_channel_T_32, _virt_channel_T_33) node _virt_channel_T_37 = or(_virt_channel_T_36, _virt_channel_T_34) node _virt_channel_T_38 = or(_virt_channel_T_37, _virt_channel_T_35) wire virt_channel : UInt<3> connect virt_channel, _virt_channel_T_38 node _T_113 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) when _T_113 : connect salloc_outs[0].out_vid, virt_channel node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_payload_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_payload_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_payload_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_payload_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_payload_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_payload_T_8 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_9 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_10 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_11 = mux(_salloc_outs_0_flit_payload_T_3, input_buffer.io.deq[3].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_12 = mux(_salloc_outs_0_flit_payload_T_4, input_buffer.io.deq[4].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_13 = mux(_salloc_outs_0_flit_payload_T_5, input_buffer.io.deq[5].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_14 = mux(_salloc_outs_0_flit_payload_T_6, input_buffer.io.deq[6].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_15 = mux(_salloc_outs_0_flit_payload_T_7, input_buffer.io.deq[7].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_16 = or(_salloc_outs_0_flit_payload_T_8, _salloc_outs_0_flit_payload_T_9) node _salloc_outs_0_flit_payload_T_17 = or(_salloc_outs_0_flit_payload_T_16, _salloc_outs_0_flit_payload_T_10) node _salloc_outs_0_flit_payload_T_18 = or(_salloc_outs_0_flit_payload_T_17, _salloc_outs_0_flit_payload_T_11) node _salloc_outs_0_flit_payload_T_19 = or(_salloc_outs_0_flit_payload_T_18, _salloc_outs_0_flit_payload_T_12) node _salloc_outs_0_flit_payload_T_20 = or(_salloc_outs_0_flit_payload_T_19, _salloc_outs_0_flit_payload_T_13) node _salloc_outs_0_flit_payload_T_21 = or(_salloc_outs_0_flit_payload_T_20, _salloc_outs_0_flit_payload_T_14) node _salloc_outs_0_flit_payload_T_22 = or(_salloc_outs_0_flit_payload_T_21, _salloc_outs_0_flit_payload_T_15) wire _salloc_outs_0_flit_payload_WIRE : UInt<73> connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_22 connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_head_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_head_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_head_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_head_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_head_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_head_T_8 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_9 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_10 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_11 = mux(_salloc_outs_0_flit_head_T_3, input_buffer.io.deq[3].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_12 = mux(_salloc_outs_0_flit_head_T_4, input_buffer.io.deq[4].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_13 = mux(_salloc_outs_0_flit_head_T_5, input_buffer.io.deq[5].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_14 = mux(_salloc_outs_0_flit_head_T_6, input_buffer.io.deq[6].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_15 = mux(_salloc_outs_0_flit_head_T_7, input_buffer.io.deq[7].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_16 = or(_salloc_outs_0_flit_head_T_8, _salloc_outs_0_flit_head_T_9) node _salloc_outs_0_flit_head_T_17 = or(_salloc_outs_0_flit_head_T_16, _salloc_outs_0_flit_head_T_10) node _salloc_outs_0_flit_head_T_18 = or(_salloc_outs_0_flit_head_T_17, _salloc_outs_0_flit_head_T_11) node _salloc_outs_0_flit_head_T_19 = or(_salloc_outs_0_flit_head_T_18, _salloc_outs_0_flit_head_T_12) node _salloc_outs_0_flit_head_T_20 = or(_salloc_outs_0_flit_head_T_19, _salloc_outs_0_flit_head_T_13) node _salloc_outs_0_flit_head_T_21 = or(_salloc_outs_0_flit_head_T_20, _salloc_outs_0_flit_head_T_14) node _salloc_outs_0_flit_head_T_22 = or(_salloc_outs_0_flit_head_T_21, _salloc_outs_0_flit_head_T_15) wire _salloc_outs_0_flit_head_WIRE : UInt<1> connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_22 connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_tail_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_tail_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_tail_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_tail_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_tail_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_tail_T_8 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_9 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_10 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_11 = mux(_salloc_outs_0_flit_tail_T_3, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_12 = mux(_salloc_outs_0_flit_tail_T_4, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_13 = mux(_salloc_outs_0_flit_tail_T_5, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_14 = mux(_salloc_outs_0_flit_tail_T_6, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_15 = mux(_salloc_outs_0_flit_tail_T_7, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_16 = or(_salloc_outs_0_flit_tail_T_8, _salloc_outs_0_flit_tail_T_9) node _salloc_outs_0_flit_tail_T_17 = or(_salloc_outs_0_flit_tail_T_16, _salloc_outs_0_flit_tail_T_10) node _salloc_outs_0_flit_tail_T_18 = or(_salloc_outs_0_flit_tail_T_17, _salloc_outs_0_flit_tail_T_11) node _salloc_outs_0_flit_tail_T_19 = or(_salloc_outs_0_flit_tail_T_18, _salloc_outs_0_flit_tail_T_12) node _salloc_outs_0_flit_tail_T_20 = or(_salloc_outs_0_flit_tail_T_19, _salloc_outs_0_flit_tail_T_13) node _salloc_outs_0_flit_tail_T_21 = or(_salloc_outs_0_flit_tail_T_20, _salloc_outs_0_flit_tail_T_14) node _salloc_outs_0_flit_tail_T_22 = or(_salloc_outs_0_flit_tail_T_21, _salloc_outs_0_flit_tail_T_15) wire _salloc_outs_0_flit_tail_WIRE : UInt<1> connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_22 connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_flow_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_flow_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_flow_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_flow_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_flow_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>} node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_11 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_12 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_13 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_8, _salloc_outs_0_flit_flow_T_9) node _salloc_outs_0_flit_flow_T_17 = or(_salloc_outs_0_flit_flow_T_16, _salloc_outs_0_flit_flow_T_10) node _salloc_outs_0_flit_flow_T_18 = or(_salloc_outs_0_flit_flow_T_17, _salloc_outs_0_flit_flow_T_11) node _salloc_outs_0_flit_flow_T_19 = or(_salloc_outs_0_flit_flow_T_18, _salloc_outs_0_flit_flow_T_12) node _salloc_outs_0_flit_flow_T_20 = or(_salloc_outs_0_flit_flow_T_19, _salloc_outs_0_flit_flow_T_13) node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_20, _salloc_outs_0_flit_flow_T_14) node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_15) wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_22 connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1 node _salloc_outs_0_flit_flow_T_23 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_24 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_25 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_26 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_27 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_28 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_29 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_30 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_31 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_24) node _salloc_outs_0_flit_flow_T_32 = or(_salloc_outs_0_flit_flow_T_31, _salloc_outs_0_flit_flow_T_25) node _salloc_outs_0_flit_flow_T_33 = or(_salloc_outs_0_flit_flow_T_32, _salloc_outs_0_flit_flow_T_26) node _salloc_outs_0_flit_flow_T_34 = or(_salloc_outs_0_flit_flow_T_33, _salloc_outs_0_flit_flow_T_27) node _salloc_outs_0_flit_flow_T_35 = or(_salloc_outs_0_flit_flow_T_34, _salloc_outs_0_flit_flow_T_28) node _salloc_outs_0_flit_flow_T_36 = or(_salloc_outs_0_flit_flow_T_35, _salloc_outs_0_flit_flow_T_29) node _salloc_outs_0_flit_flow_T_37 = or(_salloc_outs_0_flit_flow_T_36, _salloc_outs_0_flit_flow_T_30) wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<5> connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_37 connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2 node _salloc_outs_0_flit_flow_T_38 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_39 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_40 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_41 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_42 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_43 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_44 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_45 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_46 = or(_salloc_outs_0_flit_flow_T_38, _salloc_outs_0_flit_flow_T_39) node _salloc_outs_0_flit_flow_T_47 = or(_salloc_outs_0_flit_flow_T_46, _salloc_outs_0_flit_flow_T_40) node _salloc_outs_0_flit_flow_T_48 = or(_salloc_outs_0_flit_flow_T_47, _salloc_outs_0_flit_flow_T_41) node _salloc_outs_0_flit_flow_T_49 = or(_salloc_outs_0_flit_flow_T_48, _salloc_outs_0_flit_flow_T_42) node _salloc_outs_0_flit_flow_T_50 = or(_salloc_outs_0_flit_flow_T_49, _salloc_outs_0_flit_flow_T_43) node _salloc_outs_0_flit_flow_T_51 = or(_salloc_outs_0_flit_flow_T_50, _salloc_outs_0_flit_flow_T_44) node _salloc_outs_0_flit_flow_T_52 = or(_salloc_outs_0_flit_flow_T_51, _salloc_outs_0_flit_flow_T_45) wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_52 connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3 node _salloc_outs_0_flit_flow_T_53 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_54 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_55 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_56 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_57 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_58 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_59 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_60 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_61 = or(_salloc_outs_0_flit_flow_T_53, _salloc_outs_0_flit_flow_T_54) node _salloc_outs_0_flit_flow_T_62 = or(_salloc_outs_0_flit_flow_T_61, _salloc_outs_0_flit_flow_T_55) node _salloc_outs_0_flit_flow_T_63 = or(_salloc_outs_0_flit_flow_T_62, _salloc_outs_0_flit_flow_T_56) node _salloc_outs_0_flit_flow_T_64 = or(_salloc_outs_0_flit_flow_T_63, _salloc_outs_0_flit_flow_T_57) node _salloc_outs_0_flit_flow_T_65 = or(_salloc_outs_0_flit_flow_T_64, _salloc_outs_0_flit_flow_T_58) node _salloc_outs_0_flit_flow_T_66 = or(_salloc_outs_0_flit_flow_T_65, _salloc_outs_0_flit_flow_T_59) node _salloc_outs_0_flit_flow_T_67 = or(_salloc_outs_0_flit_flow_T_66, _salloc_outs_0_flit_flow_T_60) wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<5> connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_67 connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4 node _salloc_outs_0_flit_flow_T_68 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_69 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_70 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_71 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_72 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_73 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_74 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_75 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_76 = or(_salloc_outs_0_flit_flow_T_68, _salloc_outs_0_flit_flow_T_69) node _salloc_outs_0_flit_flow_T_77 = or(_salloc_outs_0_flit_flow_T_76, _salloc_outs_0_flit_flow_T_70) node _salloc_outs_0_flit_flow_T_78 = or(_salloc_outs_0_flit_flow_T_77, _salloc_outs_0_flit_flow_T_71) node _salloc_outs_0_flit_flow_T_79 = or(_salloc_outs_0_flit_flow_T_78, _salloc_outs_0_flit_flow_T_72) node _salloc_outs_0_flit_flow_T_80 = or(_salloc_outs_0_flit_flow_T_79, _salloc_outs_0_flit_flow_T_73) node _salloc_outs_0_flit_flow_T_81 = or(_salloc_outs_0_flit_flow_T_80, _salloc_outs_0_flit_flow_T_74) node _salloc_outs_0_flit_flow_T_82 = or(_salloc_outs_0_flit_flow_T_81, _salloc_outs_0_flit_flow_T_75) wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<3> connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_82 connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5 connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE else : invalidate salloc_outs[0].out_vid invalidate salloc_outs[0].flit.virt_channel_id invalidate salloc_outs[0].flit.flow.egress_node_id invalidate salloc_outs[0].flit.flow.egress_node invalidate salloc_outs[0].flit.flow.ingress_node_id invalidate salloc_outs[0].flit.flow.ingress_node invalidate salloc_outs[0].flit.flow.vnet_id invalidate salloc_outs[0].flit.payload invalidate salloc_outs[0].flit.tail invalidate salloc_outs[0].flit.head invalidate salloc_outs[0].flit.virt_channel_id connect io.out[0].valid, salloc_outs[0].valid connect io.out[0].bits.flit, salloc_outs[0].flit connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid invalidate states[0].fifo_deps invalidate states[0].flow.egress_node_id invalidate states[0].flow.egress_node invalidate states[0].flow.ingress_node_id invalidate states[0].flow.ingress_node invalidate states[0].flow.vnet_id invalidate states[0].vc_sel.`0`[0] invalidate states[0].vc_sel.`0`[1] invalidate states[0].vc_sel.`0`[2] invalidate states[0].vc_sel.`0`[3] invalidate states[0].vc_sel.`0`[4] invalidate states[0].vc_sel.`0`[5] invalidate states[0].vc_sel.`0`[6] invalidate states[0].vc_sel.`0`[7] invalidate states[0].vc_sel.`1`[0] invalidate states[0].vc_sel.`1`[1] invalidate states[0].vc_sel.`1`[2] invalidate states[0].vc_sel.`1`[3] invalidate states[0].vc_sel.`1`[4] invalidate states[0].vc_sel.`1`[5] invalidate states[0].vc_sel.`1`[6] invalidate states[0].vc_sel.`1`[7] invalidate states[0].vc_sel.`2`[0] invalidate states[0].vc_sel.`2`[1] invalidate states[0].vc_sel.`2`[2] invalidate states[0].vc_sel.`2`[3] invalidate states[0].vc_sel.`2`[4] invalidate states[0].vc_sel.`2`[5] invalidate states[0].vc_sel.`2`[6] invalidate states[0].vc_sel.`2`[7] invalidate states[0].vc_sel.`3`[0] invalidate states[0].vc_sel.`3`[1] invalidate states[0].vc_sel.`3`[2] invalidate states[0].vc_sel.`3`[3] invalidate states[0].vc_sel.`3`[4] invalidate states[0].vc_sel.`3`[5] invalidate states[0].vc_sel.`3`[6] invalidate states[0].vc_sel.`3`[7] invalidate states[0].g connect states[1].vc_sel.`0`[0], UInt<1>(0h0) connect states[1].vc_sel.`1`[0], UInt<1>(0h0) connect states[1].vc_sel.`1`[1], UInt<1>(0h0) connect states[1].vc_sel.`1`[2], UInt<1>(0h0) connect states[1].vc_sel.`1`[3], UInt<1>(0h0) connect states[1].vc_sel.`1`[4], UInt<1>(0h0) connect states[1].vc_sel.`1`[5], UInt<1>(0h0) connect states[1].vc_sel.`1`[6], UInt<1>(0h0) connect states[1].vc_sel.`1`[7], UInt<1>(0h0) connect states[1].vc_sel.`2`[0], UInt<1>(0h0) connect states[1].vc_sel.`2`[2], UInt<1>(0h0) connect states[1].vc_sel.`2`[3], UInt<1>(0h0) connect states[1].vc_sel.`2`[4], UInt<1>(0h0) connect states[1].vc_sel.`2`[5], UInt<1>(0h0) connect states[1].vc_sel.`2`[6], UInt<1>(0h0) connect states[1].vc_sel.`2`[7], UInt<1>(0h0) connect states[1].vc_sel.`3`[0], UInt<1>(0h0) connect states[1].vc_sel.`3`[1], UInt<1>(0h0) connect states[1].vc_sel.`3`[2], UInt<1>(0h0) connect states[1].vc_sel.`3`[3], UInt<1>(0h0) connect states[1].vc_sel.`3`[4], UInt<1>(0h0) connect states[1].vc_sel.`3`[5], UInt<1>(0h0) connect states[1].vc_sel.`3`[6], UInt<1>(0h0) connect states[1].vc_sel.`3`[7], UInt<1>(0h0) connect states[2].vc_sel.`0`[0], UInt<1>(0h0) connect states[2].vc_sel.`1`[0], UInt<1>(0h0) connect states[2].vc_sel.`1`[1], UInt<1>(0h0) connect states[2].vc_sel.`1`[2], UInt<1>(0h0) connect states[2].vc_sel.`1`[3], UInt<1>(0h0) connect states[2].vc_sel.`1`[4], UInt<1>(0h0) connect states[2].vc_sel.`1`[5], UInt<1>(0h0) connect states[2].vc_sel.`1`[6], UInt<1>(0h0) connect states[2].vc_sel.`1`[7], UInt<1>(0h0) connect states[2].vc_sel.`2`[0], UInt<1>(0h0) connect states[2].vc_sel.`3`[0], UInt<1>(0h0) connect states[2].vc_sel.`3`[1], UInt<1>(0h0) connect states[2].vc_sel.`3`[2], UInt<1>(0h0) connect states[2].vc_sel.`3`[3], UInt<1>(0h0) connect states[2].vc_sel.`3`[4], UInt<1>(0h0) connect states[2].vc_sel.`3`[5], UInt<1>(0h0) connect states[2].vc_sel.`3`[6], UInt<1>(0h0) connect states[2].vc_sel.`3`[7], UInt<1>(0h0) connect states[3].vc_sel.`0`[0], UInt<1>(0h0) connect states[3].vc_sel.`1`[0], UInt<1>(0h0) connect states[3].vc_sel.`1`[1], UInt<1>(0h0) connect states[3].vc_sel.`1`[2], UInt<1>(0h0) connect states[3].vc_sel.`1`[3], UInt<1>(0h0) connect states[3].vc_sel.`1`[4], UInt<1>(0h0) connect states[3].vc_sel.`1`[5], UInt<1>(0h0) connect states[3].vc_sel.`1`[6], UInt<1>(0h0) connect states[3].vc_sel.`1`[7], UInt<1>(0h0) connect states[3].vc_sel.`2`[0], UInt<1>(0h0) connect states[3].vc_sel.`3`[0], UInt<1>(0h0) connect states[3].vc_sel.`3`[1], UInt<1>(0h0) connect states[3].vc_sel.`3`[2], UInt<1>(0h0) connect states[3].vc_sel.`3`[3], UInt<1>(0h0) connect states[3].vc_sel.`3`[4], UInt<1>(0h0) connect states[3].vc_sel.`3`[5], UInt<1>(0h0) connect states[3].vc_sel.`3`[6], UInt<1>(0h0) connect states[3].vc_sel.`3`[7], UInt<1>(0h0) connect states[4].vc_sel.`0`[0], UInt<1>(0h0) connect states[4].vc_sel.`1`[0], UInt<1>(0h0) connect states[4].vc_sel.`1`[1], UInt<1>(0h0) connect states[4].vc_sel.`1`[2], UInt<1>(0h0) connect states[4].vc_sel.`1`[3], UInt<1>(0h0) connect states[4].vc_sel.`1`[4], UInt<1>(0h0) connect states[4].vc_sel.`1`[5], UInt<1>(0h0) connect states[4].vc_sel.`1`[6], UInt<1>(0h0) connect states[4].vc_sel.`1`[7], UInt<1>(0h0) connect states[4].vc_sel.`2`[0], UInt<1>(0h0) connect states[4].vc_sel.`3`[0], UInt<1>(0h0) connect states[4].vc_sel.`3`[1], UInt<1>(0h0) connect states[4].vc_sel.`3`[2], UInt<1>(0h0) connect states[4].vc_sel.`3`[3], UInt<1>(0h0) connect states[4].vc_sel.`3`[4], UInt<1>(0h0) connect states[4].vc_sel.`3`[5], UInt<1>(0h0) connect states[4].vc_sel.`3`[6], UInt<1>(0h0) connect states[4].vc_sel.`3`[7], UInt<1>(0h0) connect states[5].vc_sel.`0`[0], UInt<1>(0h0) connect states[5].vc_sel.`1`[0], UInt<1>(0h0) connect states[5].vc_sel.`1`[1], UInt<1>(0h0) connect states[5].vc_sel.`1`[2], UInt<1>(0h0) connect states[5].vc_sel.`1`[3], UInt<1>(0h0) connect states[5].vc_sel.`1`[4], UInt<1>(0h0) connect states[5].vc_sel.`1`[5], UInt<1>(0h0) connect states[5].vc_sel.`1`[6], UInt<1>(0h0) connect states[5].vc_sel.`1`[7], UInt<1>(0h0) connect states[5].vc_sel.`2`[0], UInt<1>(0h0) connect states[5].vc_sel.`3`[0], UInt<1>(0h0) connect states[5].vc_sel.`3`[1], UInt<1>(0h0) connect states[5].vc_sel.`3`[2], UInt<1>(0h0) connect states[5].vc_sel.`3`[3], UInt<1>(0h0) connect states[5].vc_sel.`3`[4], UInt<1>(0h0) connect states[5].vc_sel.`3`[5], UInt<1>(0h0) connect states[5].vc_sel.`3`[6], UInt<1>(0h0) connect states[5].vc_sel.`3`[7], UInt<1>(0h0) connect states[6].vc_sel.`0`[0], UInt<1>(0h0) connect states[6].vc_sel.`1`[0], UInt<1>(0h0) connect states[6].vc_sel.`1`[1], UInt<1>(0h0) connect states[6].vc_sel.`1`[2], UInt<1>(0h0) connect states[6].vc_sel.`1`[3], UInt<1>(0h0) connect states[6].vc_sel.`1`[4], UInt<1>(0h0) connect states[6].vc_sel.`1`[5], UInt<1>(0h0) connect states[6].vc_sel.`1`[6], UInt<1>(0h0) connect states[6].vc_sel.`1`[7], UInt<1>(0h0) connect states[6].vc_sel.`2`[0], UInt<1>(0h0) connect states[6].vc_sel.`3`[0], UInt<1>(0h0) connect states[6].vc_sel.`3`[1], UInt<1>(0h0) connect states[6].vc_sel.`3`[2], UInt<1>(0h0) connect states[6].vc_sel.`3`[3], UInt<1>(0h0) connect states[6].vc_sel.`3`[4], UInt<1>(0h0) connect states[6].vc_sel.`3`[5], UInt<1>(0h0) connect states[6].vc_sel.`3`[6], UInt<1>(0h0) connect states[6].vc_sel.`3`[7], UInt<1>(0h0) connect states[7].vc_sel.`0`[0], UInt<1>(0h0) connect states[7].vc_sel.`1`[0], UInt<1>(0h0) connect states[7].vc_sel.`1`[1], UInt<1>(0h0) connect states[7].vc_sel.`1`[2], UInt<1>(0h0) connect states[7].vc_sel.`1`[3], UInt<1>(0h0) connect states[7].vc_sel.`1`[4], UInt<1>(0h0) connect states[7].vc_sel.`1`[5], UInt<1>(0h0) connect states[7].vc_sel.`1`[6], UInt<1>(0h0) connect states[7].vc_sel.`1`[7], UInt<1>(0h0) connect states[7].vc_sel.`2`[0], UInt<1>(0h0) connect states[7].vc_sel.`3`[0], UInt<1>(0h0) connect states[7].vc_sel.`3`[1], UInt<1>(0h0) connect states[7].vc_sel.`3`[2], UInt<1>(0h0) connect states[7].vc_sel.`3`[3], UInt<1>(0h0) connect states[7].vc_sel.`3`[4], UInt<1>(0h0) connect states[7].vc_sel.`3`[5], UInt<1>(0h0) connect states[7].vc_sel.`3`[6], UInt<1>(0h0) connect states[7].vc_sel.`3`[7], UInt<1>(0h0) node _T_114 = asUInt(reset) when _T_114 : connect states[0].g, UInt<3>(0h0) connect states[1].g, UInt<3>(0h0) connect states[2].g, UInt<3>(0h0) connect states[3].g, UInt<3>(0h0) connect states[4].g, UInt<3>(0h0) connect states[5].g, UInt<3>(0h0) connect states[6].g, UInt<3>(0h0) connect states[7].g, UInt<3>(0h0)
module InputUnit_69( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output [2:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [4:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [4:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_3, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_4, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_5, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_6, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_7, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_3, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_4, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_5, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_6, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_7, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_3, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_4, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_5, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_6, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_7, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_5, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_6, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_7, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_3, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_5, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_6, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_7, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_3, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_5, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_6, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_7, // @[InputUnit.scala:170:14] input io_out_credit_available_3_4, // @[InputUnit.scala:170:14] input io_out_credit_available_3_5, // @[InputUnit.scala:170:14] input io_out_credit_available_3_6, // @[InputUnit.scala:170:14] input io_out_credit_available_3_7, // @[InputUnit.scala:170:14] input io_out_credit_available_2_0, // @[InputUnit.scala:170:14] input io_out_credit_available_2_1, // @[InputUnit.scala:170:14] input io_out_credit_available_2_2, // @[InputUnit.scala:170:14] input io_out_credit_available_2_3, // @[InputUnit.scala:170:14] input io_out_credit_available_2_4, // @[InputUnit.scala:170:14] input io_out_credit_available_2_5, // @[InputUnit.scala:170:14] input io_out_credit_available_2_6, // @[InputUnit.scala:170:14] input io_out_credit_available_2_7, // @[InputUnit.scala:170:14] input io_out_credit_available_1_0, // @[InputUnit.scala:170:14] input io_out_credit_available_1_1, // @[InputUnit.scala:170:14] input io_out_credit_available_1_2, // @[InputUnit.scala:170:14] input io_out_credit_available_1_3, // @[InputUnit.scala:170:14] input io_out_credit_available_1_4, // @[InputUnit.scala:170:14] input io_out_credit_available_1_5, // @[InputUnit.scala:170:14] input io_out_credit_available_1_6, // @[InputUnit.scala:170:14] input io_out_credit_available_1_7, // @[InputUnit.scala:170:14] input io_out_credit_available_0_1, // @[InputUnit.scala:170:14] input io_out_credit_available_0_2, // @[InputUnit.scala:170:14] input io_out_credit_available_0_3, // @[InputUnit.scala:170:14] input io_out_credit_available_0_4, // @[InputUnit.scala:170:14] input io_out_credit_available_0_5, // @[InputUnit.scala:170:14] input io_out_credit_available_0_6, // @[InputUnit.scala:170:14] input io_out_credit_available_0_7, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [4:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output [2:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [2:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [4:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [7:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [7:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire vcalloc_vals_7; // @[InputUnit.scala:266:32] wire vcalloc_vals_6; // @[InputUnit.scala:266:32] wire vcalloc_vals_5; // @[InputUnit.scala:266:32] wire vcalloc_vals_4; // @[InputUnit.scala:266:32] wire vcalloc_vals_3; // @[InputUnit.scala:266:32] wire vcalloc_vals_2; // @[InputUnit.scala:266:32] wire vcalloc_vals_1; // @[InputUnit.scala:266:32] wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_2_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_3_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_5_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_6_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_7_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [7:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_2_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_3_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_5_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_6_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_7_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [2:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_6_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_7_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_1_g; // @[InputUnit.scala:192:19] reg states_1_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_1_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_2_g; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_2_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_2_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_2_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_3_g; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_3_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_3_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_3_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_3_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_3_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_4_g; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_5_g; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_5_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_5_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_5_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_5_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_5_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_6_g; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_6_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_6_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_6_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_6_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_6_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_7_g; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_7_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_7_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_7_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_7_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_7_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_2_valid = states_2_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_3_valid = states_3_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_5_valid = states_5_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_6_valid = states_6_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_7_valid = states_7_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] reg [7:0] mask; // @[InputUnit.scala:250:21] wire [7:0] _vcalloc_filter_T_3 = {vcalloc_vals_7, vcalloc_vals_6, vcalloc_vals_5, vcalloc_vals_4, vcalloc_vals_3, vcalloc_vals_2, vcalloc_vals_1, 1'h0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32] wire [15:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 16'h1 : _vcalloc_filter_T_3[1] ? 16'h2 : _vcalloc_filter_T_3[2] ? 16'h4 : _vcalloc_filter_T_3[3] ? 16'h8 : _vcalloc_filter_T_3[4] ? 16'h10 : _vcalloc_filter_T_3[5] ? 16'h20 : _vcalloc_filter_T_3[6] ? 16'h40 : _vcalloc_filter_T_3[7] ? 16'h80 : vcalloc_vals_1 ? 16'h200 : vcalloc_vals_2 ? 16'h400 : vcalloc_vals_3 ? 16'h800 : vcalloc_vals_4 ? 16'h1000 : vcalloc_vals_5 ? 16'h2000 : vcalloc_vals_6 ? 16'h4000 : {vcalloc_vals_7, 15'h0}; // @[OneHot.scala:85:71] wire [7:0] vcalloc_sel = vcalloc_filter[7:0] | vcalloc_filter[15:8]; // @[Mux.scala:50:70] wire io_vcalloc_req_valid_0 = vcalloc_vals_1 | vcalloc_vals_2 | vcalloc_vals_3 | vcalloc_vals_4 | vcalloc_vals_5 | vcalloc_vals_6 | vcalloc_vals_7; // @[package.scala:81:59] assign vcalloc_vals_1 = states_1_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_2 = states_2_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_3 = states_3_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_5 = states_5_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_6 = states_6_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_7 = states_7_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] wire _GEN_1 = _GEN_0 & vcalloc_sel[1]; // @[Mux.scala:32:36] wire _GEN_2 = _GEN_0 & vcalloc_sel[2]; // @[Mux.scala:32:36] wire _GEN_3 = _GEN_0 & vcalloc_sel[3]; // @[Mux.scala:32:36] wire _GEN_4 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36] wire _GEN_5 = _GEN_0 & vcalloc_sel[5]; // @[Mux.scala:32:36] wire _GEN_6 = _GEN_0 & vcalloc_sel[6]; // @[Mux.scala:32:36] wire _GEN_7 = _GEN_0 & vcalloc_sel[7]; // @[Mux.scala:32:36]
Generate the Verilog code corresponding to this FIRRTL code module TLXbar_prcibus_i1_o2_a21d64s7k1z3u : input clock : Clock input reset : Reset output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonIn.d.bits.corrupt invalidate anonIn.d.bits.data invalidate anonIn.d.bits.denied invalidate anonIn.d.bits.sink invalidate anonIn.d.bits.source invalidate anonIn.d.bits.size invalidate anonIn.d.bits.param invalidate anonIn.d.bits.opcode invalidate anonIn.d.valid invalidate anonIn.d.ready invalidate anonIn.a.bits.corrupt invalidate anonIn.a.bits.data invalidate anonIn.a.bits.mask invalidate anonIn.a.bits.address invalidate anonIn.a.bits.source invalidate anonIn.a.bits.size invalidate anonIn.a.bits.param invalidate anonIn.a.bits.opcode invalidate anonIn.a.valid invalidate anonIn.a.ready inst monitor of TLMonitor_87 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt connect monitor.io.in.d.bits.data, anonIn.d.bits.data connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink connect monitor.io.in.d.bits.source, anonIn.d.bits.source connect monitor.io.in.d.bits.size, anonIn.d.bits.size connect monitor.io.in.d.bits.param, anonIn.d.bits.param connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode connect monitor.io.in.d.valid, anonIn.d.valid connect monitor.io.in.d.ready, anonIn.d.ready connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt connect monitor.io.in.a.bits.data, anonIn.a.bits.data connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask connect monitor.io.in.a.bits.address, anonIn.a.bits.address connect monitor.io.in.a.bits.source, anonIn.a.bits.source connect monitor.io.in.a.bits.size, anonIn.a.bits.size connect monitor.io.in.a.bits.param, anonIn.a.bits.param connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode connect monitor.io.in.a.valid, anonIn.a.valid connect monitor.io.in.a.ready, anonIn.a.ready wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonOut.d.bits.corrupt invalidate anonOut.d.bits.data invalidate anonOut.d.bits.denied invalidate anonOut.d.bits.sink invalidate anonOut.d.bits.source invalidate anonOut.d.bits.size invalidate anonOut.d.bits.param invalidate anonOut.d.bits.opcode invalidate anonOut.d.valid invalidate anonOut.d.ready invalidate anonOut.a.bits.corrupt invalidate anonOut.a.bits.data invalidate anonOut.a.bits.mask invalidate anonOut.a.bits.address invalidate anonOut.a.bits.source invalidate anonOut.a.bits.size invalidate anonOut.a.bits.param invalidate anonOut.a.bits.opcode invalidate anonOut.a.valid invalidate anonOut.a.ready wire x1_anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_anonOut.d.bits.corrupt invalidate x1_anonOut.d.bits.data invalidate x1_anonOut.d.bits.denied invalidate x1_anonOut.d.bits.sink invalidate x1_anonOut.d.bits.source invalidate x1_anonOut.d.bits.size invalidate x1_anonOut.d.bits.param invalidate x1_anonOut.d.bits.opcode invalidate x1_anonOut.d.valid invalidate x1_anonOut.d.ready invalidate x1_anonOut.a.bits.corrupt invalidate x1_anonOut.a.bits.data invalidate x1_anonOut.a.bits.mask invalidate x1_anonOut.a.bits.address invalidate x1_anonOut.a.bits.source invalidate x1_anonOut.a.bits.size invalidate x1_anonOut.a.bits.param invalidate x1_anonOut.a.bits.opcode invalidate x1_anonOut.a.valid invalidate x1_anonOut.a.ready connect auto.anon_out_0, anonOut connect auto.anon_out_1, x1_anonOut connect anonIn, auto.anon_in wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[1] connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt connect in[0].a.bits.data, anonIn.a.bits.data connect in[0].a.bits.mask, anonIn.a.bits.mask connect in[0].a.bits.address, anonIn.a.bits.address connect in[0].a.bits.source, anonIn.a.bits.source connect in[0].a.bits.size, anonIn.a.bits.size connect in[0].a.bits.param, anonIn.a.bits.param connect in[0].a.bits.opcode, anonIn.a.bits.opcode connect in[0].a.valid, anonIn.a.valid connect anonIn.a.ready, in[0].a.ready node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<1>(0h0)) connect in[0].a.bits.source, _in_0_a_bits_source_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<21>(0h0) connect _WIRE.bits.source, UInt<7>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready invalidate _WIRE_1.bits.corrupt invalidate _WIRE_1.bits.data invalidate _WIRE_1.bits.mask invalidate _WIRE_1.bits.address invalidate _WIRE_1.bits.source invalidate _WIRE_1.bits.size invalidate _WIRE_1.bits.param invalidate _WIRE_1.bits.opcode invalidate _WIRE_1.valid invalidate _WIRE_1.ready wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.mask, UInt<8>(0h0) connect _WIRE_2.bits.address, UInt<21>(0h0) connect _WIRE_2.bits.source, UInt<7>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<2>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready invalidate _WIRE_3.bits.corrupt invalidate _WIRE_3.bits.data invalidate _WIRE_3.bits.mask invalidate _WIRE_3.bits.address invalidate _WIRE_3.bits.source invalidate _WIRE_3.bits.size invalidate _WIRE_3.bits.param invalidate _WIRE_3.bits.opcode invalidate _WIRE_3.valid invalidate _WIRE_3.ready wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<21>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<21>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.valid, UInt<1>(0h0) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<21>(0h0) connect _WIRE_8.bits.source, UInt<7>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready invalidate _WIRE_9.bits.corrupt invalidate _WIRE_9.bits.data invalidate _WIRE_9.bits.address invalidate _WIRE_9.bits.source invalidate _WIRE_9.bits.size invalidate _WIRE_9.bits.param invalidate _WIRE_9.bits.opcode invalidate _WIRE_9.valid invalidate _WIRE_9.ready wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<21>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready invalidate _WIRE_11.bits.corrupt invalidate _WIRE_11.bits.data invalidate _WIRE_11.bits.address invalidate _WIRE_11.bits.source invalidate _WIRE_11.bits.size invalidate _WIRE_11.bits.param invalidate _WIRE_11.bits.opcode invalidate _WIRE_11.valid invalidate _WIRE_11.ready wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<21>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready connect _WIRE_13.valid, UInt<1>(0h0) wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<21>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready connect _WIRE_15.ready, UInt<1>(0h1) connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt connect anonIn.d.bits.data, in[0].d.bits.data connect anonIn.d.bits.denied, in[0].d.bits.denied connect anonIn.d.bits.sink, in[0].d.bits.sink connect anonIn.d.bits.source, in[0].d.bits.source connect anonIn.d.bits.size, in[0].d.bits.size connect anonIn.d.bits.param, in[0].d.bits.param connect anonIn.d.bits.opcode, in[0].d.bits.opcode connect anonIn.d.valid, in[0].d.valid connect in[0].d.ready, anonIn.d.ready node _anonIn_d_bits_source_T = bits(in[0].d.bits.source, 6, 0) connect anonIn.d.bits.source, _anonIn_d_bits_source_T wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_16.bits.sink, UInt<1>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready invalidate _WIRE_17.bits.sink invalidate _WIRE_17.valid invalidate _WIRE_17.ready wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_18.bits.sink, UInt<1>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready invalidate _WIRE_19.bits.sink invalidate _WIRE_19.valid invalidate _WIRE_19.ready wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_20.bits.sink, UInt<1>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready connect _WIRE_21.valid, UInt<1>(0h0) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_22.bits.sink, UInt<1>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready connect _WIRE_23.ready, UInt<1>(0h1) wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[2] connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt connect anonOut.a.bits.data, out[0].a.bits.data connect anonOut.a.bits.mask, out[0].a.bits.mask connect anonOut.a.bits.address, out[0].a.bits.address connect anonOut.a.bits.source, out[0].a.bits.source connect anonOut.a.bits.size, out[0].a.bits.size connect anonOut.a.bits.param, out[0].a.bits.param connect anonOut.a.bits.opcode, out[0].a.bits.opcode connect anonOut.a.valid, out[0].a.valid connect out[0].a.ready, anonOut.a.ready wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.mask, UInt<8>(0h0) connect _WIRE_24.bits.address, UInt<21>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<2>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready invalidate _WIRE_25.bits.corrupt invalidate _WIRE_25.bits.data invalidate _WIRE_25.bits.mask invalidate _WIRE_25.bits.address invalidate _WIRE_25.bits.source invalidate _WIRE_25.bits.size invalidate _WIRE_25.bits.param invalidate _WIRE_25.bits.opcode invalidate _WIRE_25.valid invalidate _WIRE_25.ready wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.mask, UInt<8>(0h0) connect _WIRE_26.bits.address, UInt<21>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<2>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready invalidate _WIRE_27.bits.corrupt invalidate _WIRE_27.bits.data invalidate _WIRE_27.bits.mask invalidate _WIRE_27.bits.address invalidate _WIRE_27.bits.source invalidate _WIRE_27.bits.size invalidate _WIRE_27.bits.param invalidate _WIRE_27.bits.opcode invalidate _WIRE_27.valid invalidate _WIRE_27.ready wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.mask, UInt<8>(0h0) connect _WIRE_28.bits.address, UInt<21>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<2>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready connect _WIRE_29.valid, UInt<1>(0h0) wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_30.bits.corrupt, UInt<1>(0h0) connect _WIRE_30.bits.data, UInt<64>(0h0) connect _WIRE_30.bits.mask, UInt<8>(0h0) connect _WIRE_30.bits.address, UInt<21>(0h0) connect _WIRE_30.bits.source, UInt<7>(0h0) connect _WIRE_30.bits.size, UInt<3>(0h0) connect _WIRE_30.bits.param, UInt<2>(0h0) connect _WIRE_30.bits.opcode, UInt<3>(0h0) connect _WIRE_30.valid, UInt<1>(0h0) connect _WIRE_30.ready, UInt<1>(0h0) wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_31.bits, _WIRE_30.bits connect _WIRE_31.valid, _WIRE_30.valid connect _WIRE_31.ready, _WIRE_30.ready connect _WIRE_31.ready, UInt<1>(0h1) wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_32.bits.corrupt, UInt<1>(0h0) connect _WIRE_32.bits.data, UInt<64>(0h0) connect _WIRE_32.bits.address, UInt<21>(0h0) connect _WIRE_32.bits.source, UInt<7>(0h0) connect _WIRE_32.bits.size, UInt<3>(0h0) connect _WIRE_32.bits.param, UInt<3>(0h0) connect _WIRE_32.bits.opcode, UInt<3>(0h0) connect _WIRE_32.valid, UInt<1>(0h0) connect _WIRE_32.ready, UInt<1>(0h0) wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_33.bits, _WIRE_32.bits connect _WIRE_33.valid, _WIRE_32.valid connect _WIRE_33.ready, _WIRE_32.ready invalidate _WIRE_33.bits.corrupt invalidate _WIRE_33.bits.data invalidate _WIRE_33.bits.address invalidate _WIRE_33.bits.source invalidate _WIRE_33.bits.size invalidate _WIRE_33.bits.param invalidate _WIRE_33.bits.opcode invalidate _WIRE_33.valid invalidate _WIRE_33.ready wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_34.bits.corrupt, UInt<1>(0h0) connect _WIRE_34.bits.data, UInt<64>(0h0) connect _WIRE_34.bits.address, UInt<21>(0h0) connect _WIRE_34.bits.source, UInt<7>(0h0) connect _WIRE_34.bits.size, UInt<3>(0h0) connect _WIRE_34.bits.param, UInt<3>(0h0) connect _WIRE_34.bits.opcode, UInt<3>(0h0) connect _WIRE_34.valid, UInt<1>(0h0) connect _WIRE_34.ready, UInt<1>(0h0) wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_35.bits, _WIRE_34.bits connect _WIRE_35.valid, _WIRE_34.valid connect _WIRE_35.ready, _WIRE_34.ready invalidate _WIRE_35.bits.corrupt invalidate _WIRE_35.bits.data invalidate _WIRE_35.bits.address invalidate _WIRE_35.bits.source invalidate _WIRE_35.bits.size invalidate _WIRE_35.bits.param invalidate _WIRE_35.bits.opcode invalidate _WIRE_35.valid invalidate _WIRE_35.ready wire _WIRE_36 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_36.bits.corrupt, UInt<1>(0h0) connect _WIRE_36.bits.data, UInt<64>(0h0) connect _WIRE_36.bits.address, UInt<21>(0h0) connect _WIRE_36.bits.source, UInt<7>(0h0) connect _WIRE_36.bits.size, UInt<3>(0h0) connect _WIRE_36.bits.param, UInt<3>(0h0) connect _WIRE_36.bits.opcode, UInt<3>(0h0) connect _WIRE_36.valid, UInt<1>(0h0) connect _WIRE_36.ready, UInt<1>(0h0) wire _WIRE_37 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_37.bits, _WIRE_36.bits connect _WIRE_37.valid, _WIRE_36.valid connect _WIRE_37.ready, _WIRE_36.ready connect _WIRE_37.ready, UInt<1>(0h1) wire _WIRE_38 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_38.bits.corrupt, UInt<1>(0h0) connect _WIRE_38.bits.data, UInt<64>(0h0) connect _WIRE_38.bits.address, UInt<21>(0h0) connect _WIRE_38.bits.source, UInt<7>(0h0) connect _WIRE_38.bits.size, UInt<3>(0h0) connect _WIRE_38.bits.param, UInt<3>(0h0) connect _WIRE_38.bits.opcode, UInt<3>(0h0) connect _WIRE_38.valid, UInt<1>(0h0) connect _WIRE_38.ready, UInt<1>(0h0) wire _WIRE_39 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_39.bits, _WIRE_38.bits connect _WIRE_39.valid, _WIRE_38.valid connect _WIRE_39.ready, _WIRE_38.ready connect _WIRE_39.valid, UInt<1>(0h0) connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt connect out[0].d.bits.data, anonOut.d.bits.data connect out[0].d.bits.denied, anonOut.d.bits.denied connect out[0].d.bits.sink, anonOut.d.bits.sink connect out[0].d.bits.source, anonOut.d.bits.source connect out[0].d.bits.size, anonOut.d.bits.size connect out[0].d.bits.param, anonOut.d.bits.param connect out[0].d.bits.opcode, anonOut.d.bits.opcode connect out[0].d.valid, anonOut.d.valid connect anonOut.d.ready, out[0].d.ready node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0)) connect out[0].d.bits.sink, _out_0_d_bits_sink_T wire _WIRE_40 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_40.bits.sink, UInt<1>(0h0) connect _WIRE_40.valid, UInt<1>(0h0) connect _WIRE_40.ready, UInt<1>(0h0) wire _WIRE_41 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_41.bits, _WIRE_40.bits connect _WIRE_41.valid, _WIRE_40.valid connect _WIRE_41.ready, _WIRE_40.ready invalidate _WIRE_41.bits.sink invalidate _WIRE_41.valid invalidate _WIRE_41.ready wire _WIRE_42 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_42.bits.sink, UInt<1>(0h0) connect _WIRE_42.valid, UInt<1>(0h0) connect _WIRE_42.ready, UInt<1>(0h0) wire _WIRE_43 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_43.bits, _WIRE_42.bits connect _WIRE_43.valid, _WIRE_42.valid connect _WIRE_43.ready, _WIRE_42.ready invalidate _WIRE_43.bits.sink invalidate _WIRE_43.valid invalidate _WIRE_43.ready wire _WIRE_44 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_44.bits.sink, UInt<1>(0h0) connect _WIRE_44.valid, UInt<1>(0h0) connect _WIRE_44.ready, UInt<1>(0h0) wire _WIRE_45 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_45.bits, _WIRE_44.bits connect _WIRE_45.valid, _WIRE_44.valid connect _WIRE_45.ready, _WIRE_44.ready connect _WIRE_45.ready, UInt<1>(0h1) wire _WIRE_46 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_46.bits.sink, UInt<1>(0h0) connect _WIRE_46.valid, UInt<1>(0h0) connect _WIRE_46.ready, UInt<1>(0h0) wire _WIRE_47 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_47.bits, _WIRE_46.bits connect _WIRE_47.valid, _WIRE_46.valid connect _WIRE_47.ready, _WIRE_46.ready connect _WIRE_47.valid, UInt<1>(0h0) connect x1_anonOut.a.bits.corrupt, out[1].a.bits.corrupt connect x1_anonOut.a.bits.data, out[1].a.bits.data connect x1_anonOut.a.bits.mask, out[1].a.bits.mask connect x1_anonOut.a.bits.address, out[1].a.bits.address connect x1_anonOut.a.bits.source, out[1].a.bits.source connect x1_anonOut.a.bits.size, out[1].a.bits.size connect x1_anonOut.a.bits.param, out[1].a.bits.param connect x1_anonOut.a.bits.opcode, out[1].a.bits.opcode connect x1_anonOut.a.valid, out[1].a.valid connect out[1].a.ready, x1_anonOut.a.ready wire _WIRE_48 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_48.bits.corrupt, UInt<1>(0h0) connect _WIRE_48.bits.data, UInt<64>(0h0) connect _WIRE_48.bits.mask, UInt<8>(0h0) connect _WIRE_48.bits.address, UInt<21>(0h0) connect _WIRE_48.bits.source, UInt<7>(0h0) connect _WIRE_48.bits.size, UInt<3>(0h0) connect _WIRE_48.bits.param, UInt<2>(0h0) connect _WIRE_48.bits.opcode, UInt<3>(0h0) connect _WIRE_48.valid, UInt<1>(0h0) connect _WIRE_48.ready, UInt<1>(0h0) wire _WIRE_49 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_49.bits, _WIRE_48.bits connect _WIRE_49.valid, _WIRE_48.valid connect _WIRE_49.ready, _WIRE_48.ready invalidate _WIRE_49.bits.corrupt invalidate _WIRE_49.bits.data invalidate _WIRE_49.bits.mask invalidate _WIRE_49.bits.address invalidate _WIRE_49.bits.source invalidate _WIRE_49.bits.size invalidate _WIRE_49.bits.param invalidate _WIRE_49.bits.opcode invalidate _WIRE_49.valid invalidate _WIRE_49.ready wire _WIRE_50 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_50.bits.corrupt, UInt<1>(0h0) connect _WIRE_50.bits.data, UInt<64>(0h0) connect _WIRE_50.bits.mask, UInt<8>(0h0) connect _WIRE_50.bits.address, UInt<21>(0h0) connect _WIRE_50.bits.source, UInt<7>(0h0) connect _WIRE_50.bits.size, UInt<3>(0h0) connect _WIRE_50.bits.param, UInt<2>(0h0) connect _WIRE_50.bits.opcode, UInt<3>(0h0) connect _WIRE_50.valid, UInt<1>(0h0) connect _WIRE_50.ready, UInt<1>(0h0) wire _WIRE_51 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_51.bits, _WIRE_50.bits connect _WIRE_51.valid, _WIRE_50.valid connect _WIRE_51.ready, _WIRE_50.ready invalidate _WIRE_51.bits.corrupt invalidate _WIRE_51.bits.data invalidate _WIRE_51.bits.mask invalidate _WIRE_51.bits.address invalidate _WIRE_51.bits.source invalidate _WIRE_51.bits.size invalidate _WIRE_51.bits.param invalidate _WIRE_51.bits.opcode invalidate _WIRE_51.valid invalidate _WIRE_51.ready wire _WIRE_52 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_52.bits.corrupt, UInt<1>(0h0) connect _WIRE_52.bits.data, UInt<64>(0h0) connect _WIRE_52.bits.mask, UInt<8>(0h0) connect _WIRE_52.bits.address, UInt<21>(0h0) connect _WIRE_52.bits.source, UInt<7>(0h0) connect _WIRE_52.bits.size, UInt<3>(0h0) connect _WIRE_52.bits.param, UInt<2>(0h0) connect _WIRE_52.bits.opcode, UInt<3>(0h0) connect _WIRE_52.valid, UInt<1>(0h0) connect _WIRE_52.ready, UInt<1>(0h0) wire _WIRE_53 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_53.bits, _WIRE_52.bits connect _WIRE_53.valid, _WIRE_52.valid connect _WIRE_53.ready, _WIRE_52.ready connect _WIRE_53.valid, UInt<1>(0h0) wire _WIRE_54 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_54.bits.corrupt, UInt<1>(0h0) connect _WIRE_54.bits.data, UInt<64>(0h0) connect _WIRE_54.bits.mask, UInt<8>(0h0) connect _WIRE_54.bits.address, UInt<21>(0h0) connect _WIRE_54.bits.source, UInt<7>(0h0) connect _WIRE_54.bits.size, UInt<3>(0h0) connect _WIRE_54.bits.param, UInt<2>(0h0) connect _WIRE_54.bits.opcode, UInt<3>(0h0) connect _WIRE_54.valid, UInt<1>(0h0) connect _WIRE_54.ready, UInt<1>(0h0) wire _WIRE_55 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_55.bits, _WIRE_54.bits connect _WIRE_55.valid, _WIRE_54.valid connect _WIRE_55.ready, _WIRE_54.ready connect _WIRE_55.ready, UInt<1>(0h1) wire _WIRE_56 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_56.bits.corrupt, UInt<1>(0h0) connect _WIRE_56.bits.data, UInt<64>(0h0) connect _WIRE_56.bits.address, UInt<21>(0h0) connect _WIRE_56.bits.source, UInt<7>(0h0) connect _WIRE_56.bits.size, UInt<3>(0h0) connect _WIRE_56.bits.param, UInt<3>(0h0) connect _WIRE_56.bits.opcode, UInt<3>(0h0) connect _WIRE_56.valid, UInt<1>(0h0) connect _WIRE_56.ready, UInt<1>(0h0) wire _WIRE_57 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_57.bits, _WIRE_56.bits connect _WIRE_57.valid, _WIRE_56.valid connect _WIRE_57.ready, _WIRE_56.ready invalidate _WIRE_57.bits.corrupt invalidate _WIRE_57.bits.data invalidate _WIRE_57.bits.address invalidate _WIRE_57.bits.source invalidate _WIRE_57.bits.size invalidate _WIRE_57.bits.param invalidate _WIRE_57.bits.opcode invalidate _WIRE_57.valid invalidate _WIRE_57.ready wire _WIRE_58 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_58.bits.corrupt, UInt<1>(0h0) connect _WIRE_58.bits.data, UInt<64>(0h0) connect _WIRE_58.bits.address, UInt<21>(0h0) connect _WIRE_58.bits.source, UInt<7>(0h0) connect _WIRE_58.bits.size, UInt<3>(0h0) connect _WIRE_58.bits.param, UInt<3>(0h0) connect _WIRE_58.bits.opcode, UInt<3>(0h0) connect _WIRE_58.valid, UInt<1>(0h0) connect _WIRE_58.ready, UInt<1>(0h0) wire _WIRE_59 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_59.bits, _WIRE_58.bits connect _WIRE_59.valid, _WIRE_58.valid connect _WIRE_59.ready, _WIRE_58.ready invalidate _WIRE_59.bits.corrupt invalidate _WIRE_59.bits.data invalidate _WIRE_59.bits.address invalidate _WIRE_59.bits.source invalidate _WIRE_59.bits.size invalidate _WIRE_59.bits.param invalidate _WIRE_59.bits.opcode invalidate _WIRE_59.valid invalidate _WIRE_59.ready wire _WIRE_60 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_60.bits.corrupt, UInt<1>(0h0) connect _WIRE_60.bits.data, UInt<64>(0h0) connect _WIRE_60.bits.address, UInt<21>(0h0) connect _WIRE_60.bits.source, UInt<7>(0h0) connect _WIRE_60.bits.size, UInt<3>(0h0) connect _WIRE_60.bits.param, UInt<3>(0h0) connect _WIRE_60.bits.opcode, UInt<3>(0h0) connect _WIRE_60.valid, UInt<1>(0h0) connect _WIRE_60.ready, UInt<1>(0h0) wire _WIRE_61 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_61.bits, _WIRE_60.bits connect _WIRE_61.valid, _WIRE_60.valid connect _WIRE_61.ready, _WIRE_60.ready connect _WIRE_61.ready, UInt<1>(0h1) wire _WIRE_62 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_62.bits.corrupt, UInt<1>(0h0) connect _WIRE_62.bits.data, UInt<64>(0h0) connect _WIRE_62.bits.address, UInt<21>(0h0) connect _WIRE_62.bits.source, UInt<7>(0h0) connect _WIRE_62.bits.size, UInt<3>(0h0) connect _WIRE_62.bits.param, UInt<3>(0h0) connect _WIRE_62.bits.opcode, UInt<3>(0h0) connect _WIRE_62.valid, UInt<1>(0h0) connect _WIRE_62.ready, UInt<1>(0h0) wire _WIRE_63 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_63.bits, _WIRE_62.bits connect _WIRE_63.valid, _WIRE_62.valid connect _WIRE_63.ready, _WIRE_62.ready connect _WIRE_63.valid, UInt<1>(0h0) connect out[1].d.bits.corrupt, x1_anonOut.d.bits.corrupt connect out[1].d.bits.data, x1_anonOut.d.bits.data connect out[1].d.bits.denied, x1_anonOut.d.bits.denied connect out[1].d.bits.sink, x1_anonOut.d.bits.sink connect out[1].d.bits.source, x1_anonOut.d.bits.source connect out[1].d.bits.size, x1_anonOut.d.bits.size connect out[1].d.bits.param, x1_anonOut.d.bits.param connect out[1].d.bits.opcode, x1_anonOut.d.bits.opcode connect out[1].d.valid, x1_anonOut.d.valid connect x1_anonOut.d.ready, out[1].d.ready node _out_1_d_bits_sink_T = or(x1_anonOut.d.bits.sink, UInt<1>(0h0)) connect out[1].d.bits.sink, _out_1_d_bits_sink_T wire _WIRE_64 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_64.bits.sink, UInt<1>(0h0) connect _WIRE_64.valid, UInt<1>(0h0) connect _WIRE_64.ready, UInt<1>(0h0) wire _WIRE_65 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_65.bits, _WIRE_64.bits connect _WIRE_65.valid, _WIRE_64.valid connect _WIRE_65.ready, _WIRE_64.ready invalidate _WIRE_65.bits.sink invalidate _WIRE_65.valid invalidate _WIRE_65.ready wire _WIRE_66 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_66.bits.sink, UInt<1>(0h0) connect _WIRE_66.valid, UInt<1>(0h0) connect _WIRE_66.ready, UInt<1>(0h0) wire _WIRE_67 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_67.bits, _WIRE_66.bits connect _WIRE_67.valid, _WIRE_66.valid connect _WIRE_67.ready, _WIRE_66.ready invalidate _WIRE_67.bits.sink invalidate _WIRE_67.valid invalidate _WIRE_67.ready wire _WIRE_68 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_68.bits.sink, UInt<1>(0h0) connect _WIRE_68.valid, UInt<1>(0h0) connect _WIRE_68.ready, UInt<1>(0h0) wire _WIRE_69 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_69.bits, _WIRE_68.bits connect _WIRE_69.valid, _WIRE_68.valid connect _WIRE_69.ready, _WIRE_68.ready connect _WIRE_69.ready, UInt<1>(0h1) wire _WIRE_70 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_70.bits.sink, UInt<1>(0h0) connect _WIRE_70.valid, UInt<1>(0h0) connect _WIRE_70.ready, UInt<1>(0h0) wire _WIRE_71 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_71.bits, _WIRE_70.bits connect _WIRE_71.valid, _WIRE_70.valid connect _WIRE_71.ready, _WIRE_70.ready connect _WIRE_71.valid, UInt<1>(0h0) wire _addressC_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _addressC_WIRE.bits.corrupt, UInt<1>(0h0) connect _addressC_WIRE.bits.data, UInt<64>(0h0) connect _addressC_WIRE.bits.address, UInt<21>(0h0) connect _addressC_WIRE.bits.source, UInt<7>(0h0) connect _addressC_WIRE.bits.size, UInt<3>(0h0) connect _addressC_WIRE.bits.param, UInt<3>(0h0) connect _addressC_WIRE.bits.opcode, UInt<3>(0h0) connect _addressC_WIRE.valid, UInt<1>(0h0) connect _addressC_WIRE.ready, UInt<1>(0h0) wire _addressC_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _addressC_WIRE_1.bits, _addressC_WIRE.bits connect _addressC_WIRE_1.valid, _addressC_WIRE.valid connect _addressC_WIRE_1.ready, _addressC_WIRE.ready node _requestAIO_T = xor(in[0].a.bits.address, UInt<1>(0h0)) node _requestAIO_T_1 = cvt(_requestAIO_T) node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<18>(0h10000))) node _requestAIO_T_3 = asSInt(_requestAIO_T_2) node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0))) node requestAIO_0_0 = or(UInt<1>(0h0), _requestAIO_T_4) node _requestAIO_T_5 = xor(in[0].a.bits.address, UInt<17>(0h10000)) node _requestAIO_T_6 = cvt(_requestAIO_T_5) node _requestAIO_T_7 = and(_requestAIO_T_6, asSInt(UInt<18>(0h10000))) node _requestAIO_T_8 = asSInt(_requestAIO_T_7) node _requestAIO_T_9 = eq(_requestAIO_T_8, asSInt(UInt<1>(0h0))) node requestAIO_0_1 = or(UInt<1>(0h0), _requestAIO_T_9) node _requestCIO_T = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) node _requestCIO_T_1 = cvt(_requestCIO_T) node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0))) node _requestCIO_T_3 = asSInt(_requestCIO_T_2) node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0))) node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4) node _requestCIO_T_5 = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) node _requestCIO_T_6 = cvt(_requestCIO_T_5) node _requestCIO_T_7 = and(_requestCIO_T_6, asSInt(UInt<1>(0h0))) node _requestCIO_T_8 = asSInt(_requestCIO_T_7) node _requestCIO_T_9 = eq(_requestCIO_T_8, asSInt(UInt<1>(0h0))) node requestCIO_0_1 = or(UInt<1>(0h1), _requestCIO_T_9) wire _requestBOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE.bits.corrupt, UInt<1>(0h0) connect _requestBOI_WIRE.bits.data, UInt<64>(0h0) connect _requestBOI_WIRE.bits.mask, UInt<8>(0h0) connect _requestBOI_WIRE.bits.address, UInt<21>(0h0) connect _requestBOI_WIRE.bits.source, UInt<7>(0h0) connect _requestBOI_WIRE.bits.size, UInt<3>(0h0) connect _requestBOI_WIRE.bits.param, UInt<2>(0h0) connect _requestBOI_WIRE.bits.opcode, UInt<3>(0h0) connect _requestBOI_WIRE.valid, UInt<1>(0h0) connect _requestBOI_WIRE.ready, UInt<1>(0h0) wire _requestBOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_1.bits, _requestBOI_WIRE.bits connect _requestBOI_WIRE_1.valid, _requestBOI_WIRE.valid connect _requestBOI_WIRE_1.ready, _requestBOI_WIRE.ready node _requestBOI_uncommonBits_T = or(_requestBOI_WIRE_1.bits.source, UInt<7>(0h0)) node requestBOI_uncommonBits = bits(_requestBOI_uncommonBits_T, 6, 0) node _requestBOI_T = shr(_requestBOI_WIRE_1.bits.source, 7) node _requestBOI_T_1 = eq(_requestBOI_T, UInt<1>(0h0)) node _requestBOI_T_2 = leq(UInt<1>(0h0), requestBOI_uncommonBits) node _requestBOI_T_3 = and(_requestBOI_T_1, _requestBOI_T_2) node _requestBOI_T_4 = leq(requestBOI_uncommonBits, UInt<7>(0h7f)) node requestBOI_0_0 = and(_requestBOI_T_3, _requestBOI_T_4) wire _requestBOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _requestBOI_WIRE_2.bits.data, UInt<64>(0h0) connect _requestBOI_WIRE_2.bits.mask, UInt<8>(0h0) connect _requestBOI_WIRE_2.bits.address, UInt<21>(0h0) connect _requestBOI_WIRE_2.bits.source, UInt<7>(0h0) connect _requestBOI_WIRE_2.bits.size, UInt<3>(0h0) connect _requestBOI_WIRE_2.bits.param, UInt<2>(0h0) connect _requestBOI_WIRE_2.bits.opcode, UInt<3>(0h0) connect _requestBOI_WIRE_2.valid, UInt<1>(0h0) connect _requestBOI_WIRE_2.ready, UInt<1>(0h0) wire _requestBOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_3.bits, _requestBOI_WIRE_2.bits connect _requestBOI_WIRE_3.valid, _requestBOI_WIRE_2.valid connect _requestBOI_WIRE_3.ready, _requestBOI_WIRE_2.ready node _requestBOI_uncommonBits_T_1 = or(_requestBOI_WIRE_3.bits.source, UInt<7>(0h0)) node requestBOI_uncommonBits_1 = bits(_requestBOI_uncommonBits_T_1, 6, 0) node _requestBOI_T_5 = shr(_requestBOI_WIRE_3.bits.source, 7) node _requestBOI_T_6 = eq(_requestBOI_T_5, UInt<1>(0h0)) node _requestBOI_T_7 = leq(UInt<1>(0h0), requestBOI_uncommonBits_1) node _requestBOI_T_8 = and(_requestBOI_T_6, _requestBOI_T_7) node _requestBOI_T_9 = leq(requestBOI_uncommonBits_1, UInt<7>(0h7f)) node requestBOI_1_0 = and(_requestBOI_T_8, _requestBOI_T_9) node _requestDOI_uncommonBits_T = or(out[0].d.bits.source, UInt<7>(0h0)) node requestDOI_uncommonBits = bits(_requestDOI_uncommonBits_T, 6, 0) node _requestDOI_T = shr(out[0].d.bits.source, 7) node _requestDOI_T_1 = eq(_requestDOI_T, UInt<1>(0h0)) node _requestDOI_T_2 = leq(UInt<1>(0h0), requestDOI_uncommonBits) node _requestDOI_T_3 = and(_requestDOI_T_1, _requestDOI_T_2) node _requestDOI_T_4 = leq(requestDOI_uncommonBits, UInt<7>(0h7f)) node requestDOI_0_0 = and(_requestDOI_T_3, _requestDOI_T_4) node _requestDOI_uncommonBits_T_1 = or(out[1].d.bits.source, UInt<7>(0h0)) node requestDOI_uncommonBits_1 = bits(_requestDOI_uncommonBits_T_1, 6, 0) node _requestDOI_T_5 = shr(out[1].d.bits.source, 7) node _requestDOI_T_6 = eq(_requestDOI_T_5, UInt<1>(0h0)) node _requestDOI_T_7 = leq(UInt<1>(0h0), requestDOI_uncommonBits_1) node _requestDOI_T_8 = and(_requestDOI_T_6, _requestDOI_T_7) node _requestDOI_T_9 = leq(requestDOI_uncommonBits_1, UInt<7>(0h7f)) node requestDOI_1_0 = and(_requestDOI_T_8, _requestDOI_T_9) wire _requestEIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE.bits.sink, UInt<1>(0h0) connect _requestEIO_WIRE.valid, UInt<1>(0h0) connect _requestEIO_WIRE.ready, UInt<1>(0h0) wire _requestEIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE_1.bits, _requestEIO_WIRE.bits connect _requestEIO_WIRE_1.valid, _requestEIO_WIRE.valid connect _requestEIO_WIRE_1.ready, _requestEIO_WIRE.ready wire _requestEIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE_2.bits.sink, UInt<1>(0h0) connect _requestEIO_WIRE_2.valid, UInt<1>(0h0) connect _requestEIO_WIRE_2.ready, UInt<1>(0h0) wire _requestEIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE_3.bits, _requestEIO_WIRE_2.bits connect _requestEIO_WIRE_3.valid, _requestEIO_WIRE_2.valid connect _requestEIO_WIRE_3.ready, _requestEIO_WIRE_2.ready node _beatsAI_decode_T = dshl(UInt<6>(0h3f), in[0].a.bits.size) node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 5, 0) node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1) node beatsAI_decode = shr(_beatsAI_decode_T_2, 3) node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2) node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0)) node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0)) wire _beatsBO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE.bits.corrupt, UInt<1>(0h0) connect _beatsBO_WIRE.bits.data, UInt<64>(0h0) connect _beatsBO_WIRE.bits.mask, UInt<8>(0h0) connect _beatsBO_WIRE.bits.address, UInt<21>(0h0) connect _beatsBO_WIRE.bits.source, UInt<7>(0h0) connect _beatsBO_WIRE.bits.size, UInt<3>(0h0) connect _beatsBO_WIRE.bits.param, UInt<2>(0h0) connect _beatsBO_WIRE.bits.opcode, UInt<3>(0h0) connect _beatsBO_WIRE.valid, UInt<1>(0h0) connect _beatsBO_WIRE.ready, UInt<1>(0h0) wire _beatsBO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE_1.bits, _beatsBO_WIRE.bits connect _beatsBO_WIRE_1.valid, _beatsBO_WIRE.valid connect _beatsBO_WIRE_1.ready, _beatsBO_WIRE.ready node _beatsBO_decode_T = dshl(UInt<6>(0h3f), _beatsBO_WIRE_1.bits.size) node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 5, 0) node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1) node beatsBO_decode = shr(_beatsBO_decode_T_2, 3) node _beatsBO_opdata_T = bits(_beatsBO_WIRE_1.bits.opcode, 2, 2) node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0)) node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0)) wire _beatsBO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _beatsBO_WIRE_2.bits.data, UInt<64>(0h0) connect _beatsBO_WIRE_2.bits.mask, UInt<8>(0h0) connect _beatsBO_WIRE_2.bits.address, UInt<21>(0h0) connect _beatsBO_WIRE_2.bits.source, UInt<7>(0h0) connect _beatsBO_WIRE_2.bits.size, UInt<3>(0h0) connect _beatsBO_WIRE_2.bits.param, UInt<2>(0h0) connect _beatsBO_WIRE_2.bits.opcode, UInt<3>(0h0) connect _beatsBO_WIRE_2.valid, UInt<1>(0h0) connect _beatsBO_WIRE_2.ready, UInt<1>(0h0) wire _beatsBO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE_3.bits, _beatsBO_WIRE_2.bits connect _beatsBO_WIRE_3.valid, _beatsBO_WIRE_2.valid connect _beatsBO_WIRE_3.ready, _beatsBO_WIRE_2.ready node _beatsBO_decode_T_3 = dshl(UInt<6>(0h3f), _beatsBO_WIRE_3.bits.size) node _beatsBO_decode_T_4 = bits(_beatsBO_decode_T_3, 5, 0) node _beatsBO_decode_T_5 = not(_beatsBO_decode_T_4) node beatsBO_decode_1 = shr(_beatsBO_decode_T_5, 3) node _beatsBO_opdata_T_1 = bits(_beatsBO_WIRE_3.bits.opcode, 2, 2) node beatsBO_opdata_1 = eq(_beatsBO_opdata_T_1, UInt<1>(0h0)) node beatsBO_1 = mux(UInt<1>(0h0), beatsBO_decode_1, UInt<1>(0h0)) wire _beatsCI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _beatsCI_WIRE.bits.corrupt, UInt<1>(0h0) connect _beatsCI_WIRE.bits.data, UInt<64>(0h0) connect _beatsCI_WIRE.bits.address, UInt<21>(0h0) connect _beatsCI_WIRE.bits.source, UInt<7>(0h0) connect _beatsCI_WIRE.bits.size, UInt<3>(0h0) connect _beatsCI_WIRE.bits.param, UInt<3>(0h0) connect _beatsCI_WIRE.bits.opcode, UInt<3>(0h0) connect _beatsCI_WIRE.valid, UInt<1>(0h0) connect _beatsCI_WIRE.ready, UInt<1>(0h0) wire _beatsCI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _beatsCI_WIRE_1.bits, _beatsCI_WIRE.bits connect _beatsCI_WIRE_1.valid, _beatsCI_WIRE.valid connect _beatsCI_WIRE_1.ready, _beatsCI_WIRE.ready node _beatsCI_decode_T = dshl(UInt<6>(0h3f), _beatsCI_WIRE_1.bits.size) node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 5, 0) node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1) node beatsCI_decode = shr(_beatsCI_decode_T_2, 3) node beatsCI_opdata = bits(_beatsCI_WIRE_1.bits.opcode, 0, 0) node beatsCI_0 = mux(beatsCI_opdata, beatsCI_decode, UInt<1>(0h0)) node _beatsDO_decode_T = dshl(UInt<6>(0h3f), out[0].d.bits.size) node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 5, 0) node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1) node beatsDO_decode = shr(_beatsDO_decode_T_2, 3) node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0) node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0)) node _beatsDO_decode_T_3 = dshl(UInt<6>(0h3f), out[1].d.bits.size) node _beatsDO_decode_T_4 = bits(_beatsDO_decode_T_3, 5, 0) node _beatsDO_decode_T_5 = not(_beatsDO_decode_T_4) node beatsDO_decode_1 = shr(_beatsDO_decode_T_5, 3) node beatsDO_opdata_1 = bits(out[1].d.bits.opcode, 0, 0) node beatsDO_1 = mux(beatsDO_opdata_1, beatsDO_decode_1, UInt<1>(0h0)) wire _beatsEI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _beatsEI_WIRE.bits.sink, UInt<1>(0h0) connect _beatsEI_WIRE.valid, UInt<1>(0h0) connect _beatsEI_WIRE.ready, UInt<1>(0h0) wire _beatsEI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _beatsEI_WIRE_1.bits, _beatsEI_WIRE.bits connect _beatsEI_WIRE_1.valid, _beatsEI_WIRE.valid connect _beatsEI_WIRE_1.ready, _beatsEI_WIRE.ready wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2] connect portsAOI_filtered[0].bits, in[0].a.bits node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h0)) node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T) connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1 connect portsAOI_filtered[1].bits, in[0].a.bits node _portsAOI_filtered_1_valid_T = or(requestAIO_0_1, UInt<1>(0h0)) node _portsAOI_filtered_1_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_1_valid_T) connect portsAOI_filtered[1].valid, _portsAOI_filtered_1_valid_T_1 node _portsAOI_in_0_a_ready_T = mux(requestAIO_0_0, portsAOI_filtered[0].ready, UInt<1>(0h0)) node _portsAOI_in_0_a_ready_T_1 = mux(requestAIO_0_1, portsAOI_filtered[1].ready, UInt<1>(0h0)) node _portsAOI_in_0_a_ready_T_2 = or(_portsAOI_in_0_a_ready_T, _portsAOI_in_0_a_ready_T_1) wire _portsAOI_in_0_a_ready_WIRE : UInt<1> connect _portsAOI_in_0_a_ready_WIRE, _portsAOI_in_0_a_ready_T_2 connect in[0].a.ready, _portsAOI_in_0_a_ready_WIRE wire _portsBIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE.bits.corrupt, UInt<1>(0h0) connect _portsBIO_WIRE.bits.data, UInt<64>(0h0) connect _portsBIO_WIRE.bits.mask, UInt<8>(0h0) connect _portsBIO_WIRE.bits.address, UInt<21>(0h0) connect _portsBIO_WIRE.bits.source, UInt<7>(0h0) connect _portsBIO_WIRE.bits.size, UInt<3>(0h0) connect _portsBIO_WIRE.bits.param, UInt<2>(0h0) connect _portsBIO_WIRE.bits.opcode, UInt<3>(0h0) connect _portsBIO_WIRE.valid, UInt<1>(0h0) connect _portsBIO_WIRE.ready, UInt<1>(0h0) wire _portsBIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE_1.bits, _portsBIO_WIRE.bits connect _portsBIO_WIRE_1.valid, _portsBIO_WIRE.valid connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE.ready wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsBIO_filtered[0].bits, _portsBIO_WIRE_1.bits node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h1)) node _portsBIO_filtered_0_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_0_valid_T) connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1 connect _portsBIO_WIRE_1.ready, portsBIO_filtered[0].ready wire _portsBIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _portsBIO_WIRE_2.bits.data, UInt<64>(0h0) connect _portsBIO_WIRE_2.bits.mask, UInt<8>(0h0) connect _portsBIO_WIRE_2.bits.address, UInt<21>(0h0) connect _portsBIO_WIRE_2.bits.source, UInt<7>(0h0) connect _portsBIO_WIRE_2.bits.size, UInt<3>(0h0) connect _portsBIO_WIRE_2.bits.param, UInt<2>(0h0) connect _portsBIO_WIRE_2.bits.opcode, UInt<3>(0h0) connect _portsBIO_WIRE_2.valid, UInt<1>(0h0) connect _portsBIO_WIRE_2.ready, UInt<1>(0h0) wire _portsBIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE_3.bits, _portsBIO_WIRE_2.bits connect _portsBIO_WIRE_3.valid, _portsBIO_WIRE_2.valid connect _portsBIO_WIRE_3.ready, _portsBIO_WIRE_2.ready wire portsBIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsBIO_filtered_1[0].bits, _portsBIO_WIRE_3.bits node _portsBIO_filtered_0_valid_T_2 = or(requestBOI_1_0, UInt<1>(0h1)) node _portsBIO_filtered_0_valid_T_3 = and(_portsBIO_WIRE_3.valid, _portsBIO_filtered_0_valid_T_2) connect portsBIO_filtered_1[0].valid, _portsBIO_filtered_0_valid_T_3 connect _portsBIO_WIRE_3.ready, portsBIO_filtered_1[0].ready wire _portsCOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _portsCOI_WIRE.bits.corrupt, UInt<1>(0h0) connect _portsCOI_WIRE.bits.data, UInt<64>(0h0) connect _portsCOI_WIRE.bits.address, UInt<21>(0h0) connect _portsCOI_WIRE.bits.source, UInt<7>(0h0) connect _portsCOI_WIRE.bits.size, UInt<3>(0h0) connect _portsCOI_WIRE.bits.param, UInt<3>(0h0) connect _portsCOI_WIRE.bits.opcode, UInt<3>(0h0) connect _portsCOI_WIRE.valid, UInt<1>(0h0) connect _portsCOI_WIRE.ready, UInt<1>(0h0) wire _portsCOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _portsCOI_WIRE_1.bits, _portsCOI_WIRE.bits connect _portsCOI_WIRE_1.valid, _portsCOI_WIRE.valid connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE.ready wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2] connect portsCOI_filtered[0].bits, _portsCOI_WIRE_1.bits node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h0)) node _portsCOI_filtered_0_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_0_valid_T) connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1 connect portsCOI_filtered[1].bits, _portsCOI_WIRE_1.bits node _portsCOI_filtered_1_valid_T = or(requestCIO_0_1, UInt<1>(0h0)) node _portsCOI_filtered_1_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_1_valid_T) connect portsCOI_filtered[1].valid, _portsCOI_filtered_1_valid_T_1 node _portsCOI_T = mux(requestCIO_0_0, portsCOI_filtered[0].ready, UInt<1>(0h0)) node _portsCOI_T_1 = mux(requestCIO_0_1, portsCOI_filtered[1].ready, UInt<1>(0h0)) node _portsCOI_T_2 = or(_portsCOI_T, _portsCOI_T_1) wire _portsCOI_WIRE_2 : UInt<1> connect _portsCOI_WIRE_2, _portsCOI_T_2 connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE_2 wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt connect portsDIO_filtered[0].bits.data, out[0].d.bits.data connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink connect portsDIO_filtered[0].bits.source, out[0].d.bits.source connect portsDIO_filtered[0].bits.size, out[0].d.bits.size connect portsDIO_filtered[0].bits.param, out[0].d.bits.param connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h1)) node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T) connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1 connect out[0].d.ready, portsDIO_filtered[0].ready wire portsDIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsDIO_filtered_1[0].bits.corrupt, out[1].d.bits.corrupt connect portsDIO_filtered_1[0].bits.data, out[1].d.bits.data connect portsDIO_filtered_1[0].bits.denied, out[1].d.bits.denied connect portsDIO_filtered_1[0].bits.sink, out[1].d.bits.sink connect portsDIO_filtered_1[0].bits.source, out[1].d.bits.source connect portsDIO_filtered_1[0].bits.size, out[1].d.bits.size connect portsDIO_filtered_1[0].bits.param, out[1].d.bits.param connect portsDIO_filtered_1[0].bits.opcode, out[1].d.bits.opcode node _portsDIO_filtered_0_valid_T_2 = or(requestDOI_1_0, UInt<1>(0h1)) node _portsDIO_filtered_0_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_0_valid_T_2) connect portsDIO_filtered_1[0].valid, _portsDIO_filtered_0_valid_T_3 connect out[1].d.ready, portsDIO_filtered_1[0].ready wire _portsEOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _portsEOI_WIRE.bits.sink, UInt<1>(0h0) connect _portsEOI_WIRE.valid, UInt<1>(0h0) connect _portsEOI_WIRE.ready, UInt<1>(0h0) wire _portsEOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _portsEOI_WIRE_1.bits, _portsEOI_WIRE.bits connect _portsEOI_WIRE_1.valid, _portsEOI_WIRE.valid connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE.ready wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}[2] connect portsEOI_filtered[0].bits, _portsEOI_WIRE_1.bits node _portsEOI_filtered_0_valid_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _portsEOI_filtered_0_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_0_valid_T) connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1 connect portsEOI_filtered[1].bits, _portsEOI_WIRE_1.bits node _portsEOI_filtered_1_valid_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _portsEOI_filtered_1_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_1_valid_T) connect portsEOI_filtered[1].valid, _portsEOI_filtered_1_valid_T_1 node _portsEOI_T = mux(UInt<1>(0h0), portsEOI_filtered[0].ready, UInt<1>(0h0)) node _portsEOI_T_1 = mux(UInt<1>(0h0), portsEOI_filtered[1].ready, UInt<1>(0h0)) node _portsEOI_T_2 = or(_portsEOI_T, _portsEOI_T_1) wire _portsEOI_WIRE_2 : UInt<1> connect _portsEOI_WIRE_2, _portsEOI_T_2 connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE_2 connect out[0].a, portsAOI_filtered[0] wire _WIRE_72 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_72.bits.corrupt, UInt<1>(0h0) connect _WIRE_72.bits.data, UInt<64>(0h0) connect _WIRE_72.bits.address, UInt<21>(0h0) connect _WIRE_72.bits.source, UInt<7>(0h0) connect _WIRE_72.bits.size, UInt<3>(0h0) connect _WIRE_72.bits.param, UInt<3>(0h0) connect _WIRE_72.bits.opcode, UInt<3>(0h0) connect _WIRE_72.valid, UInt<1>(0h0) connect _WIRE_72.ready, UInt<1>(0h0) wire _WIRE_73 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_73.bits, _WIRE_72.bits connect _WIRE_73.valid, _WIRE_72.valid connect _WIRE_73.ready, _WIRE_72.ready invalidate _WIRE_73.bits.corrupt invalidate _WIRE_73.bits.data invalidate _WIRE_73.bits.address invalidate _WIRE_73.bits.source invalidate _WIRE_73.bits.size invalidate _WIRE_73.bits.param invalidate _WIRE_73.bits.opcode wire _WIRE_74 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_74.bits.sink, UInt<1>(0h0) connect _WIRE_74.valid, UInt<1>(0h0) connect _WIRE_74.ready, UInt<1>(0h0) wire _WIRE_75 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_75.bits, _WIRE_74.bits connect _WIRE_75.valid, _WIRE_74.valid connect _WIRE_75.ready, _WIRE_74.ready invalidate _WIRE_75.bits.sink connect portsCOI_filtered[0].ready, UInt<1>(0h0) connect portsEOI_filtered[0].ready, UInt<1>(0h0) connect out[1].a, portsAOI_filtered[1] wire _WIRE_76 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_76.bits.corrupt, UInt<1>(0h0) connect _WIRE_76.bits.data, UInt<64>(0h0) connect _WIRE_76.bits.address, UInt<21>(0h0) connect _WIRE_76.bits.source, UInt<7>(0h0) connect _WIRE_76.bits.size, UInt<3>(0h0) connect _WIRE_76.bits.param, UInt<3>(0h0) connect _WIRE_76.bits.opcode, UInt<3>(0h0) connect _WIRE_76.valid, UInt<1>(0h0) connect _WIRE_76.ready, UInt<1>(0h0) wire _WIRE_77 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_77.bits, _WIRE_76.bits connect _WIRE_77.valid, _WIRE_76.valid connect _WIRE_77.ready, _WIRE_76.ready invalidate _WIRE_77.bits.corrupt invalidate _WIRE_77.bits.data invalidate _WIRE_77.bits.address invalidate _WIRE_77.bits.source invalidate _WIRE_77.bits.size invalidate _WIRE_77.bits.param invalidate _WIRE_77.bits.opcode wire _WIRE_78 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_78.bits.sink, UInt<1>(0h0) connect _WIRE_78.valid, UInt<1>(0h0) connect _WIRE_78.ready, UInt<1>(0h0) wire _WIRE_79 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_79.bits, _WIRE_78.bits connect _WIRE_79.valid, _WIRE_78.valid connect _WIRE_79.ready, _WIRE_78.ready invalidate _WIRE_79.bits.sink connect portsCOI_filtered[1].ready, UInt<1>(0h0) connect portsEOI_filtered[1].ready, UInt<1>(0h0) wire _WIRE_80 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_80.bits.corrupt, UInt<1>(0h0) connect _WIRE_80.bits.data, UInt<64>(0h0) connect _WIRE_80.bits.mask, UInt<8>(0h0) connect _WIRE_80.bits.address, UInt<21>(0h0) connect _WIRE_80.bits.source, UInt<7>(0h0) connect _WIRE_80.bits.size, UInt<3>(0h0) connect _WIRE_80.bits.param, UInt<2>(0h0) connect _WIRE_80.bits.opcode, UInt<3>(0h0) connect _WIRE_80.valid, UInt<1>(0h0) connect _WIRE_80.ready, UInt<1>(0h0) wire _WIRE_81 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_81.bits, _WIRE_80.bits connect _WIRE_81.valid, _WIRE_80.valid connect _WIRE_81.ready, _WIRE_80.ready invalidate _WIRE_81.bits.corrupt invalidate _WIRE_81.bits.data invalidate _WIRE_81.bits.mask invalidate _WIRE_81.bits.address invalidate _WIRE_81.bits.source invalidate _WIRE_81.bits.size invalidate _WIRE_81.bits.param invalidate _WIRE_81.bits.opcode regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0) node idle = eq(beatsLeft, UInt<1>(0h0)) node latch = and(idle, in[0].d.ready) node _readys_T = cat(portsDIO_filtered_1[0].valid, portsDIO_filtered[0].valid) node readys_valid = bits(_readys_T, 1, 0) node _readys_T_1 = eq(readys_valid, _readys_T) node _readys_T_2 = asUInt(reset) node _readys_T_3 = eq(_readys_T_2, UInt<1>(0h0)) when _readys_T_3 : node _readys_T_4 = eq(_readys_T_1, UInt<1>(0h0)) when _readys_T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf assert(clock, _readys_T_1, UInt<1>(0h1), "") : readys_assert regreset readys_mask : UInt<2>, clock, reset, UInt<2>(0h3) node _readys_filter_T = not(readys_mask) node _readys_filter_T_1 = and(readys_valid, _readys_filter_T) node readys_filter = cat(_readys_filter_T_1, readys_valid) node _readys_unready_T = shr(readys_filter, 1) node _readys_unready_T_1 = or(readys_filter, _readys_unready_T) node _readys_unready_T_2 = bits(_readys_unready_T_1, 3, 0) node _readys_unready_T_3 = shr(_readys_unready_T_2, 1) node _readys_unready_T_4 = shl(readys_mask, 2) node readys_unready = or(_readys_unready_T_3, _readys_unready_T_4) node _readys_readys_T = shr(readys_unready, 2) node _readys_readys_T_1 = bits(readys_unready, 1, 0) node _readys_readys_T_2 = and(_readys_readys_T, _readys_readys_T_1) node readys_readys = not(_readys_readys_T_2) node _readys_T_5 = orr(readys_valid) node _readys_T_6 = and(latch, _readys_T_5) when _readys_T_6 : node _readys_mask_T = and(readys_readys, readys_valid) node _readys_mask_T_1 = shl(_readys_mask_T, 1) node _readys_mask_T_2 = bits(_readys_mask_T_1, 1, 0) node _readys_mask_T_3 = or(_readys_mask_T, _readys_mask_T_2) node _readys_mask_T_4 = bits(_readys_mask_T_3, 1, 0) connect readys_mask, _readys_mask_T_4 node _readys_T_7 = bits(readys_readys, 1, 0) node _readys_T_8 = bits(_readys_T_7, 0, 0) node _readys_T_9 = bits(_readys_T_7, 1, 1) wire readys : UInt<1>[2] connect readys[0], _readys_T_8 connect readys[1], _readys_T_9 node _winner_T = and(readys[0], portsDIO_filtered[0].valid) node _winner_T_1 = and(readys[1], portsDIO_filtered_1[0].valid) wire winner : UInt<1>[2] connect winner[0], _winner_T connect winner[1], _winner_T_1 node prefixOR_1 = or(UInt<1>(0h0), winner[0]) node _prefixOR_T = or(prefixOR_1, winner[1]) node _T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1 = eq(winner[0], UInt<1>(0h0)) node _T_2 = or(_T, _T_1) node _T_3 = eq(prefixOR_1, UInt<1>(0h0)) node _T_4 = eq(winner[1], UInt<1>(0h0)) node _T_5 = or(_T_3, _T_4) node _T_6 = and(_T_2, _T_5) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf assert(clock, _T_6, UInt<1>(0h1), "") : assert node _T_10 = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid) node _T_11 = eq(_T_10, UInt<1>(0h0)) node _T_12 = or(winner[0], winner[1]) node _T_13 = or(_T_11, _T_12) node _T_14 = asUInt(reset) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : node _T_16 = eq(_T_13, UInt<1>(0h0)) when _T_16 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_1 assert(clock, _T_13, UInt<1>(0h1), "") : assert_1 node maskedBeats_0 = mux(winner[0], beatsDO_0, UInt<1>(0h0)) node maskedBeats_1 = mux(winner[1], beatsDO_1, UInt<1>(0h0)) node initBeats = or(maskedBeats_0, maskedBeats_1) node _beatsLeft_T = and(in[0].d.ready, in[0].d.valid) node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T) node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1) node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2) connect beatsLeft, _beatsLeft_T_3 wire _state_WIRE : UInt<1>[2] connect _state_WIRE[0], UInt<1>(0h0) connect _state_WIRE[1], UInt<1>(0h0) regreset state : UInt<1>[2], clock, reset, _state_WIRE node muxState = mux(idle, winner, state) connect state, muxState node allowed = mux(idle, readys, state) node _filtered_0_ready_T = and(in[0].d.ready, allowed[0]) connect portsDIO_filtered[0].ready, _filtered_0_ready_T node _filtered_0_ready_T_1 = and(in[0].d.ready, allowed[1]) connect portsDIO_filtered_1[0].ready, _filtered_0_ready_T_1 node _in_0_d_valid_T = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid) node _in_0_d_valid_T_1 = mux(state[0], portsDIO_filtered[0].valid, UInt<1>(0h0)) node _in_0_d_valid_T_2 = mux(state[1], portsDIO_filtered_1[0].valid, UInt<1>(0h0)) node _in_0_d_valid_T_3 = or(_in_0_d_valid_T_1, _in_0_d_valid_T_2) wire _in_0_d_valid_WIRE : UInt<1> connect _in_0_d_valid_WIRE, _in_0_d_valid_T_3 node _in_0_d_valid_T_4 = mux(idle, _in_0_d_valid_T, _in_0_d_valid_WIRE) connect in[0].d.valid, _in_0_d_valid_T_4 wire _in_0_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} node _in_0_d_bits_T = mux(muxState[0], portsDIO_filtered[0].bits.corrupt, UInt<1>(0h0)) node _in_0_d_bits_T_1 = mux(muxState[1], portsDIO_filtered_1[0].bits.corrupt, UInt<1>(0h0)) node _in_0_d_bits_T_2 = or(_in_0_d_bits_T, _in_0_d_bits_T_1) wire _in_0_d_bits_WIRE_1 : UInt<1> connect _in_0_d_bits_WIRE_1, _in_0_d_bits_T_2 connect _in_0_d_bits_WIRE.corrupt, _in_0_d_bits_WIRE_1 node _in_0_d_bits_T_3 = mux(muxState[0], portsDIO_filtered[0].bits.data, UInt<1>(0h0)) node _in_0_d_bits_T_4 = mux(muxState[1], portsDIO_filtered_1[0].bits.data, UInt<1>(0h0)) node _in_0_d_bits_T_5 = or(_in_0_d_bits_T_3, _in_0_d_bits_T_4) wire _in_0_d_bits_WIRE_2 : UInt<64> connect _in_0_d_bits_WIRE_2, _in_0_d_bits_T_5 connect _in_0_d_bits_WIRE.data, _in_0_d_bits_WIRE_2 wire _in_0_d_bits_WIRE_3 : { } connect _in_0_d_bits_WIRE.echo, _in_0_d_bits_WIRE_3 wire _in_0_d_bits_WIRE_4 : { } connect _in_0_d_bits_WIRE.user, _in_0_d_bits_WIRE_4 node _in_0_d_bits_T_6 = mux(muxState[0], portsDIO_filtered[0].bits.denied, UInt<1>(0h0)) node _in_0_d_bits_T_7 = mux(muxState[1], portsDIO_filtered_1[0].bits.denied, UInt<1>(0h0)) node _in_0_d_bits_T_8 = or(_in_0_d_bits_T_6, _in_0_d_bits_T_7) wire _in_0_d_bits_WIRE_5 : UInt<1> connect _in_0_d_bits_WIRE_5, _in_0_d_bits_T_8 connect _in_0_d_bits_WIRE.denied, _in_0_d_bits_WIRE_5 node _in_0_d_bits_T_9 = mux(muxState[0], portsDIO_filtered[0].bits.sink, UInt<1>(0h0)) node _in_0_d_bits_T_10 = mux(muxState[1], portsDIO_filtered_1[0].bits.sink, UInt<1>(0h0)) node _in_0_d_bits_T_11 = or(_in_0_d_bits_T_9, _in_0_d_bits_T_10) wire _in_0_d_bits_WIRE_6 : UInt<1> connect _in_0_d_bits_WIRE_6, _in_0_d_bits_T_11 connect _in_0_d_bits_WIRE.sink, _in_0_d_bits_WIRE_6 node _in_0_d_bits_T_12 = mux(muxState[0], portsDIO_filtered[0].bits.source, UInt<1>(0h0)) node _in_0_d_bits_T_13 = mux(muxState[1], portsDIO_filtered_1[0].bits.source, UInt<1>(0h0)) node _in_0_d_bits_T_14 = or(_in_0_d_bits_T_12, _in_0_d_bits_T_13) wire _in_0_d_bits_WIRE_7 : UInt<7> connect _in_0_d_bits_WIRE_7, _in_0_d_bits_T_14 connect _in_0_d_bits_WIRE.source, _in_0_d_bits_WIRE_7 node _in_0_d_bits_T_15 = mux(muxState[0], portsDIO_filtered[0].bits.size, UInt<1>(0h0)) node _in_0_d_bits_T_16 = mux(muxState[1], portsDIO_filtered_1[0].bits.size, UInt<1>(0h0)) node _in_0_d_bits_T_17 = or(_in_0_d_bits_T_15, _in_0_d_bits_T_16) wire _in_0_d_bits_WIRE_8 : UInt<3> connect _in_0_d_bits_WIRE_8, _in_0_d_bits_T_17 connect _in_0_d_bits_WIRE.size, _in_0_d_bits_WIRE_8 node _in_0_d_bits_T_18 = mux(muxState[0], portsDIO_filtered[0].bits.param, UInt<1>(0h0)) node _in_0_d_bits_T_19 = mux(muxState[1], portsDIO_filtered_1[0].bits.param, UInt<1>(0h0)) node _in_0_d_bits_T_20 = or(_in_0_d_bits_T_18, _in_0_d_bits_T_19) wire _in_0_d_bits_WIRE_9 : UInt<2> connect _in_0_d_bits_WIRE_9, _in_0_d_bits_T_20 connect _in_0_d_bits_WIRE.param, _in_0_d_bits_WIRE_9 node _in_0_d_bits_T_21 = mux(muxState[0], portsDIO_filtered[0].bits.opcode, UInt<1>(0h0)) node _in_0_d_bits_T_22 = mux(muxState[1], portsDIO_filtered_1[0].bits.opcode, UInt<1>(0h0)) node _in_0_d_bits_T_23 = or(_in_0_d_bits_T_21, _in_0_d_bits_T_22) wire _in_0_d_bits_WIRE_10 : UInt<3> connect _in_0_d_bits_WIRE_10, _in_0_d_bits_T_23 connect _in_0_d_bits_WIRE.opcode, _in_0_d_bits_WIRE_10 connect in[0].d.bits.corrupt, _in_0_d_bits_WIRE.corrupt connect in[0].d.bits.data, _in_0_d_bits_WIRE.data connect in[0].d.bits.denied, _in_0_d_bits_WIRE.denied connect in[0].d.bits.sink, _in_0_d_bits_WIRE.sink connect in[0].d.bits.source, _in_0_d_bits_WIRE.source connect in[0].d.bits.size, _in_0_d_bits_WIRE.size connect in[0].d.bits.param, _in_0_d_bits_WIRE.param connect in[0].d.bits.opcode, _in_0_d_bits_WIRE.opcode connect portsBIO_filtered[0].ready, UInt<1>(0h0) connect portsBIO_filtered_1[0].ready, UInt<1>(0h0)
module TLXbar_prcibus_i1_o2_a21d64s7k1z3u( // @[Xbar.scala:74:9] input clock, // @[Xbar.scala:74:9] input reset, // @[Xbar.scala:74:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [20:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_anon_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25] output [20:0] auto_anon_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_anon_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25] output [20:0] auto_anon_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_anon_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_0_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] wire [6:0] in_0_d_bits_source; // @[Xbar.scala:159:18] wire [6:0] in_0_a_bits_source; // @[Xbar.scala:159:18] wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[Xbar.scala:74:9] wire [6:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[Xbar.scala:74:9] wire [20:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_ready_0 = auto_anon_out_0_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_valid_0 = auto_anon_out_0_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_d_bits_opcode_0 = auto_anon_out_0_d_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_d_bits_size_0 = auto_anon_out_0_d_bits_size; // @[Xbar.scala:74:9] wire [6:0] auto_anon_out_0_d_bits_source_0 = auto_anon_out_0_d_bits_source; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_0_d_bits_data_0 = auto_anon_out_0_d_bits_data; // @[Xbar.scala:74:9] wire _readys_T_2 = reset; // @[Arbiter.scala:22:12] wire [2:0] auto_anon_out_1_d_bits_opcode = 3'h0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_d_bits_size = 3'h0; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_d_bits_opcode = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_d_bits_size = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] out_1_d_bits_opcode = 3'h0; // @[Xbar.scala:216:19] wire [2:0] out_1_d_bits_size = 3'h0; // @[Xbar.scala:216:19] wire [2:0] _addressC_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _requestBOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsBO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsBO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] beatsBO_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] beatsBO_0 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _beatsBO_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsBO_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] beatsBO_decode_1 = 3'h0; // @[Edges.scala:220:59] wire [2:0] beatsBO_1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _beatsCI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] beatsCI_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] beatsCI_0 = 3'h0; // @[Edges.scala:221:14] wire [2:0] beatsDO_decode_1 = 3'h0; // @[Edges.scala:220:59] wire [2:0] beatsDO_1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _portsBIO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _portsBIO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] portsBIO_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsBIO_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _portsBIO_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] portsBIO_filtered_1_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_1_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsCOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _portsCOI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _portsCOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] portsCOI_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsDIO_filtered_1_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsDIO_filtered_1_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] maskedBeats_1 = 3'h0; // @[Arbiter.scala:82:69] wire [2:0] _in_0_d_bits_T_16 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _in_0_d_bits_T_22 = 3'h0; // @[Mux.scala:30:73] wire [5:0] _beatsBO_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _beatsBO_decode_T_5 = 6'h0; // @[package.scala:243:46] wire [5:0] _beatsCI_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _beatsDO_decode_T_5 = 6'h0; // @[package.scala:243:46] wire [5:0] _beatsBO_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [5:0] _beatsBO_decode_T_4 = 6'h3F; // @[package.scala:243:76] wire [5:0] _beatsCI_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [5:0] _beatsDO_decode_T_4 = 6'h3F; // @[package.scala:243:76] wire [12:0] _beatsBO_decode_T = 13'h3F; // @[package.scala:243:71] wire [12:0] _beatsBO_decode_T_3 = 13'h3F; // @[package.scala:243:71] wire [12:0] _beatsCI_decode_T = 13'h3F; // @[package.scala:243:71] wire [12:0] _beatsDO_decode_T_3 = 13'h3F; // @[package.scala:243:71] wire [1:0] auto_anon_in_d_bits_param = 2'h0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_1_d_bits_param = 2'h0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_0_d_bits_param = 2'h0; // @[Xbar.scala:74:9] wire [1:0] anonIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] x1_anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] in_0_d_bits_param = 2'h0; // @[Xbar.scala:159:18] wire [1:0] out_0_d_bits_param = 2'h0; // @[Xbar.scala:216:19] wire [1:0] out_1_d_bits_param = 2'h0; // @[Xbar.scala:216:19] wire [1:0] _requestBOI_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _requestBOI_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _beatsBO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _beatsBO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _beatsBO_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _beatsBO_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _portsBIO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _portsBIO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] portsBIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] _portsBIO_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _portsBIO_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] portsBIO_filtered_1_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] portsDIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] portsDIO_filtered_1_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] _in_0_d_bits_WIRE_param = 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_0_d_bits_T_18 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_0_d_bits_T_19 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_0_d_bits_T_20 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_0_d_bits_WIRE_9 = 2'h0; // @[Mux.scala:30:73] wire auto_anon_in_d_bits_sink = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_d_bits_denied = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_d_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_ready = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_valid = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_bits_sink = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_bits_denied = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_bits_sink = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_bits_denied = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire anonIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire anonOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire anonOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire x1_anonOut_a_ready = 1'h0; // @[MixedNode.scala:542:17] wire x1_anonOut_d_valid = 1'h0; // @[MixedNode.scala:542:17] wire x1_anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire x1_anonOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire x1_anonOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire in_0_d_bits_sink = 1'h0; // @[Xbar.scala:159:18] wire in_0_d_bits_denied = 1'h0; // @[Xbar.scala:159:18] wire in_0_d_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire out_0_d_bits_sink = 1'h0; // @[Xbar.scala:216:19] wire out_0_d_bits_denied = 1'h0; // @[Xbar.scala:216:19] wire out_0_d_bits_corrupt = 1'h0; // @[Xbar.scala:216:19] wire out_1_a_ready = 1'h0; // @[Xbar.scala:216:19] wire out_1_d_valid = 1'h0; // @[Xbar.scala:216:19] wire out_1_d_bits_sink = 1'h0; // @[Xbar.scala:216:19] wire out_1_d_bits_denied = 1'h0; // @[Xbar.scala:216:19] wire out_1_d_bits_corrupt = 1'h0; // @[Xbar.scala:216:19] wire _out_0_d_bits_sink_T = 1'h0; // @[Xbar.scala:251:53] wire _out_1_d_bits_sink_T = 1'h0; // @[Xbar.scala:251:53] wire _addressC_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _requestBOI_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_T = 1'h0; // @[Parameters.scala:54:10] wire _requestBOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_T_5 = 1'h0; // @[Parameters.scala:54:10] wire _requestDOI_T = 1'h0; // @[Parameters.scala:54:10] wire _requestDOI_T_5 = 1'h0; // @[Parameters.scala:54:10] wire _requestEIO_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_2_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_3_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _beatsBO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_opdata_T = 1'h0; // @[Edges.scala:97:37] wire _beatsBO_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_opdata_T_1 = 1'h0; // @[Edges.scala:97:37] wire _beatsCI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire beatsCI_opdata = 1'h0; // @[Edges.scala:102:36] wire beatsDO_opdata_1 = 1'h0; // @[Edges.scala:106:36] wire _beatsEI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire portsAOI_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire _portsAOI_in_0_a_ready_T_1 = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire portsBIO_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire portsBIO_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire portsCOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsCOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_T = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_T_1 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_T_2 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_WIRE_2 = 1'h0; // @[Mux.scala:30:73] wire portsDIO_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire portsDIO_filtered_0_bits_denied = 1'h0; // @[Xbar.scala:352:24] wire portsDIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_0_bits_denied = 1'h0; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsDIO_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire portsEOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsEOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_filtered_1_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsEOI_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_T = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_T_1 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_T_2 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_WIRE_2 = 1'h0; // @[Mux.scala:30:73] wire _winner_T_1 = 1'h0; // @[Arbiter.scala:71:69] wire winner_1 = 1'h0; // @[Arbiter.scala:71:27] wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34] wire _in_0_d_valid_T_2 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_WIRE_sink = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_WIRE_denied = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_WIRE_corrupt = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_1 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_2 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_WIRE_1 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_6 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_7 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_8 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_WIRE_5 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_9 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_10 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_T_11 = 1'h0; // @[Mux.scala:30:73] wire _in_0_d_bits_WIRE_6 = 1'h0; // @[Mux.scala:30:73] wire [6:0] auto_anon_out_1_d_bits_source = 7'h0; // @[Xbar.scala:74:9] wire [6:0] x1_anonOut_d_bits_source = 7'h0; // @[MixedNode.scala:542:17] wire [6:0] out_1_d_bits_source = 7'h0; // @[Xbar.scala:216:19] wire [6:0] _addressC_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _addressC_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _requestBOI_WIRE_bits_source = 7'h0; // @[Bundles.scala:264:74] wire [6:0] _requestBOI_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:264:61] wire [6:0] _requestBOI_uncommonBits_T = 7'h0; // @[Parameters.scala:52:29] wire [6:0] requestBOI_uncommonBits = 7'h0; // @[Parameters.scala:52:56] wire [6:0] _requestBOI_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:264:74] wire [6:0] _requestBOI_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:264:61] wire [6:0] _requestBOI_uncommonBits_T_1 = 7'h0; // @[Parameters.scala:52:29] wire [6:0] requestBOI_uncommonBits_1 = 7'h0; // @[Parameters.scala:52:56] wire [6:0] _requestDOI_uncommonBits_T_1 = 7'h0; // @[Parameters.scala:52:29] wire [6:0] requestDOI_uncommonBits_1 = 7'h0; // @[Parameters.scala:52:56] wire [6:0] _beatsBO_WIRE_bits_source = 7'h0; // @[Bundles.scala:264:74] wire [6:0] _beatsBO_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:264:61] wire [6:0] _beatsBO_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:264:74] wire [6:0] _beatsBO_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:264:61] wire [6:0] _beatsCI_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _beatsCI_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _portsBIO_WIRE_bits_source = 7'h0; // @[Bundles.scala:264:74] wire [6:0] _portsBIO_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:264:61] wire [6:0] portsBIO_filtered_0_bits_source = 7'h0; // @[Xbar.scala:352:24] wire [6:0] _portsBIO_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:264:74] wire [6:0] _portsBIO_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:264:61] wire [6:0] portsBIO_filtered_1_0_bits_source = 7'h0; // @[Xbar.scala:352:24] wire [6:0] _portsCOI_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _portsCOI_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] portsCOI_filtered_0_bits_source = 7'h0; // @[Xbar.scala:352:24] wire [6:0] portsCOI_filtered_1_bits_source = 7'h0; // @[Xbar.scala:352:24] wire [6:0] portsDIO_filtered_1_0_bits_source = 7'h0; // @[Xbar.scala:352:24] wire [6:0] _in_0_d_bits_T_13 = 7'h0; // @[Mux.scala:30:73] wire [63:0] auto_anon_out_1_d_bits_data = 64'h0; // @[Xbar.scala:74:9] wire [63:0] x1_anonOut_d_bits_data = 64'h0; // @[MixedNode.scala:542:17] wire [63:0] out_1_d_bits_data = 64'h0; // @[Xbar.scala:216:19] wire [63:0] _addressC_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _addressC_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _requestBOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _requestBOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _requestBOI_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _requestBOI_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsBO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _beatsBO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsBO_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _beatsBO_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsCI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _beatsCI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _portsBIO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _portsBIO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] portsBIO_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _portsBIO_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _portsBIO_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] portsBIO_filtered_1_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _portsCOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _portsCOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] portsCOI_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] portsCOI_filtered_1_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] portsDIO_filtered_1_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _in_0_d_bits_T_4 = 64'h0; // @[Mux.scala:30:73] wire _requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_9 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_1 = 1'h1; // @[Xbar.scala:308:107] wire _requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestBOI_T_6 = 1'h1; // @[Parameters.scala:54:32] wire _requestBOI_T_7 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_8 = 1'h1; // @[Parameters.scala:54:67] wire _requestBOI_T_9 = 1'h1; // @[Parameters.scala:57:20] wire requestBOI_1_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestDOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire requestDOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestDOI_T_6 = 1'h1; // @[Parameters.scala:54:32] wire _requestDOI_T_7 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_8 = 1'h1; // @[Parameters.scala:54:67] wire _requestDOI_T_9 = 1'h1; // @[Parameters.scala:57:20] wire requestDOI_1_0 = 1'h1; // @[Parameters.scala:56:48] wire beatsBO_opdata = 1'h1; // @[Edges.scala:97:28] wire beatsBO_opdata_1 = 1'h1; // @[Edges.scala:97:28] wire _portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsBIO_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_1_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsDIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsDIO_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire [20:0] _addressC_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _addressC_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _requestCIO_T = 21'h0; // @[Parameters.scala:137:31] wire [20:0] _requestCIO_T_5 = 21'h0; // @[Parameters.scala:137:31] wire [20:0] _requestBOI_WIRE_bits_address = 21'h0; // @[Bundles.scala:264:74] wire [20:0] _requestBOI_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:264:61] wire [20:0] _requestBOI_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:264:74] wire [20:0] _requestBOI_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:264:61] wire [20:0] _beatsBO_WIRE_bits_address = 21'h0; // @[Bundles.scala:264:74] wire [20:0] _beatsBO_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:264:61] wire [20:0] _beatsBO_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:264:74] wire [20:0] _beatsBO_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:264:61] wire [20:0] _beatsCI_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _beatsCI_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _portsBIO_WIRE_bits_address = 21'h0; // @[Bundles.scala:264:74] wire [20:0] _portsBIO_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:264:61] wire [20:0] portsBIO_filtered_0_bits_address = 21'h0; // @[Xbar.scala:352:24] wire [20:0] _portsBIO_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:264:74] wire [20:0] _portsBIO_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:264:61] wire [20:0] portsBIO_filtered_1_0_bits_address = 21'h0; // @[Xbar.scala:352:24] wire [20:0] _portsCOI_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _portsCOI_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] portsCOI_filtered_0_bits_address = 21'h0; // @[Xbar.scala:352:24] wire [20:0] portsCOI_filtered_1_bits_address = 21'h0; // @[Xbar.scala:352:24] wire [7:0] _requestBOI_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _requestBOI_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _requestBOI_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _requestBOI_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _beatsBO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _beatsBO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _beatsBO_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _beatsBO_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _portsBIO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _portsBIO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] portsBIO_filtered_0_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [7:0] _portsBIO_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _portsBIO_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] portsBIO_filtered_1_0_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [21:0] _requestCIO_T_1 = 22'h0; // @[Parameters.scala:137:41] wire [21:0] _requestCIO_T_2 = 22'h0; // @[Parameters.scala:137:46] wire [21:0] _requestCIO_T_3 = 22'h0; // @[Parameters.scala:137:46] wire [21:0] _requestCIO_T_6 = 22'h0; // @[Parameters.scala:137:41] wire [21:0] _requestCIO_T_7 = 22'h0; // @[Parameters.scala:137:46] wire [21:0] _requestCIO_T_8 = 22'h0; // @[Parameters.scala:137:46] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[Xbar.scala:74:9] wire [6:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[Xbar.scala:74:9] wire [20:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[Xbar.scala:74:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [6:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire x1_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [6:0] x1_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [20:0] x1_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire x1_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_a_ready = auto_anon_out_0_a_ready_0; // @[Xbar.scala:74:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [6:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [20:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_0_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_0_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_size = auto_anon_out_0_d_bits_size_0; // @[Xbar.scala:74:9] wire [6:0] anonOut_d_bits_source = auto_anon_out_0_d_bits_source_0; // @[Xbar.scala:74:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_0_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_a_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_d_bits_size_0; // @[Xbar.scala:74:9] wire [6:0] auto_anon_in_d_bits_source_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_size_0; // @[Xbar.scala:74:9] wire [6:0] auto_anon_out_1_a_bits_source_0; // @[Xbar.scala:74:9] wire [20:0] auto_anon_out_1_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_1_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_1_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_a_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_a_bits_size_0; // @[Xbar.scala:74:9] wire [6:0] auto_anon_out_0_a_bits_source_0; // @[Xbar.scala:74:9] wire [20:0] auto_anon_out_0_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_0_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_0_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_ready_0; // @[Xbar.scala:74:9] wire in_0_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[Xbar.scala:74:9] wire in_0_a_valid = anonIn_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_opcode = anonIn_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_param = anonIn_a_bits_param; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_size = anonIn_a_bits_size; // @[Xbar.scala:159:18] wire [6:0] _in_0_a_bits_source_T = anonIn_a_bits_source; // @[Xbar.scala:166:55] wire [20:0] in_0_a_bits_address = anonIn_a_bits_address; // @[Xbar.scala:159:18] wire [7:0] in_0_a_bits_mask = anonIn_a_bits_mask; // @[Xbar.scala:159:18] wire [63:0] in_0_a_bits_data = anonIn_a_bits_data; // @[Xbar.scala:159:18] wire in_0_a_bits_corrupt = anonIn_a_bits_corrupt; // @[Xbar.scala:159:18] wire in_0_d_ready = anonIn_d_ready; // @[Xbar.scala:159:18] wire in_0_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_0_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] in_0_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[Xbar.scala:74:9] wire [6:0] _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[Xbar.scala:74:9] wire [63:0] in_0_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[Xbar.scala:74:9] wire out_0_a_ready = anonOut_a_ready; // @[Xbar.scala:216:19] wire out_0_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_valid_0 = anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_param_0 = anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_size; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_size_0 = anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [6:0] out_0_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_source_0 = anonOut_a_bits_source; // @[Xbar.scala:74:9] wire [20:0] out_0_a_bits_address; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_address_0 = anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] out_0_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_mask_0 = anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] out_0_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_data_0 = anonOut_a_bits_data; // @[Xbar.scala:74:9] wire out_0_a_bits_corrupt; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Xbar.scala:74:9] wire out_0_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_0_d_ready_0 = anonOut_d_ready; // @[Xbar.scala:74:9] wire out_0_d_valid = anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_opcode = anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_size = anonOut_d_bits_size; // @[Xbar.scala:216:19] wire [6:0] out_0_d_bits_source = anonOut_d_bits_source; // @[Xbar.scala:216:19] wire [63:0] out_0_d_bits_data = anonOut_d_bits_data; // @[Xbar.scala:216:19] wire out_1_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_valid_0 = x1_anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_1_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_opcode_0 = x1_anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_1_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_param_0 = x1_anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] out_1_a_bits_size; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_size_0 = x1_anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [6:0] out_1_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_source_0 = x1_anonOut_a_bits_source; // @[Xbar.scala:74:9] wire [20:0] out_1_a_bits_address; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_address_0 = x1_anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] out_1_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_mask_0 = x1_anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] out_1_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_data_0 = x1_anonOut_a_bits_data; // @[Xbar.scala:74:9] wire out_1_a_bits_corrupt; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_corrupt_0 = x1_anonOut_a_bits_corrupt; // @[Xbar.scala:74:9] wire out_1_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_1_d_ready_0 = x1_anonOut_d_ready; // @[Xbar.scala:74:9] wire _portsAOI_in_0_a_ready_WIRE; // @[Mux.scala:30:73] assign anonIn_a_ready = in_0_a_ready; // @[Xbar.scala:159:18] wire [2:0] portsAOI_filtered_0_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_0_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_0_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [6:0] portsAOI_filtered_0_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [6:0] portsAOI_filtered_1_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [20:0] _requestAIO_T = in_0_a_bits_address; // @[Xbar.scala:159:18] wire [20:0] portsAOI_filtered_0_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [20:0] portsAOI_filtered_1_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_0_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_1_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsAOI_filtered_0_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsAOI_filtered_1_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_0_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_1_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire _in_0_d_valid_T_4; // @[Arbiter.scala:96:24] assign anonIn_d_valid = in_0_d_valid; // @[Xbar.scala:159:18] wire [2:0] _in_0_d_bits_WIRE_opcode; // @[Mux.scala:30:73] assign anonIn_d_bits_opcode = in_0_d_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] _in_0_d_bits_WIRE_size; // @[Mux.scala:30:73] assign anonIn_d_bits_size = in_0_d_bits_size; // @[Xbar.scala:159:18] wire [6:0] _in_0_d_bits_WIRE_source; // @[Mux.scala:30:73] assign _anonIn_d_bits_source_T = in_0_d_bits_source; // @[Xbar.scala:156:69, :159:18] wire [63:0] _in_0_d_bits_WIRE_data; // @[Mux.scala:30:73] assign anonIn_d_bits_data = in_0_d_bits_data; // @[Xbar.scala:159:18] assign in_0_a_bits_source = _in_0_a_bits_source_T; // @[Xbar.scala:159:18, :166:55] assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] wire portsAOI_filtered_0_ready = out_0_a_ready; // @[Xbar.scala:216:19, :352:24] wire portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] assign anonOut_a_valid = out_0_a_valid; // @[Xbar.scala:216:19] assign anonOut_a_bits_opcode = out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign anonOut_a_bits_param = out_0_a_bits_param; // @[Xbar.scala:216:19] assign anonOut_a_bits_size = out_0_a_bits_size; // @[Xbar.scala:216:19] assign anonOut_a_bits_source = out_0_a_bits_source; // @[Xbar.scala:216:19] assign anonOut_a_bits_address = out_0_a_bits_address; // @[Xbar.scala:216:19] assign anonOut_a_bits_mask = out_0_a_bits_mask; // @[Xbar.scala:216:19] assign anonOut_a_bits_data = out_0_a_bits_data; // @[Xbar.scala:216:19] assign anonOut_a_bits_corrupt = out_0_a_bits_corrupt; // @[Xbar.scala:216:19] wire portsDIO_filtered_0_ready; // @[Xbar.scala:352:24] assign anonOut_d_ready = out_0_d_ready; // @[Xbar.scala:216:19] wire _portsDIO_filtered_0_valid_T_1 = out_0_d_valid; // @[Xbar.scala:216:19, :355:40] wire [2:0] portsDIO_filtered_0_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_0_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [6:0] _requestDOI_uncommonBits_T = out_0_d_bits_source; // @[Xbar.scala:216:19] wire [6:0] portsDIO_filtered_0_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire [63:0] portsDIO_filtered_0_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire portsAOI_filtered_1_valid; // @[Xbar.scala:352:24] assign x1_anonOut_a_valid = out_1_a_valid; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_opcode = out_1_a_bits_opcode; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_param = out_1_a_bits_param; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_size = out_1_a_bits_size; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_source = out_1_a_bits_source; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_address = out_1_a_bits_address; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_mask = out_1_a_bits_mask; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_data = out_1_a_bits_data; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_corrupt = out_1_a_bits_corrupt; // @[Xbar.scala:216:19] wire portsDIO_filtered_1_0_ready; // @[Xbar.scala:352:24] assign x1_anonOut_d_ready = out_1_d_ready; // @[Xbar.scala:216:19] wire [21:0] _requestAIO_T_1 = {1'h0, _requestAIO_T}; // @[Parameters.scala:137:{31,41}] wire [21:0] _requestAIO_T_2 = _requestAIO_T_1 & 22'h10000; // @[Parameters.scala:137:{41,46}] wire [21:0] _requestAIO_T_3 = _requestAIO_T_2; // @[Parameters.scala:137:46] wire _requestAIO_T_4 = _requestAIO_T_3 == 22'h0; // @[Parameters.scala:137:{46,59}] wire requestAIO_0_0 = _requestAIO_T_4; // @[Xbar.scala:307:107] wire _portsAOI_filtered_0_valid_T = requestAIO_0_0; // @[Xbar.scala:307:107, :355:54] wire [20:0] _requestAIO_T_5 = {in_0_a_bits_address[20:17], in_0_a_bits_address[16:0] ^ 17'h10000}; // @[Xbar.scala:159:18] wire [21:0] _requestAIO_T_6 = {1'h0, _requestAIO_T_5}; // @[Parameters.scala:137:{31,41}] wire [21:0] _requestAIO_T_7 = _requestAIO_T_6 & 22'h10000; // @[Parameters.scala:137:{41,46}] wire [21:0] _requestAIO_T_8 = _requestAIO_T_7; // @[Parameters.scala:137:46] wire _requestAIO_T_9 = _requestAIO_T_8 == 22'h0; // @[Parameters.scala:137:{46,59}] wire requestAIO_0_1 = _requestAIO_T_9; // @[Xbar.scala:307:107] wire _portsAOI_filtered_1_valid_T = requestAIO_0_1; // @[Xbar.scala:307:107, :355:54] wire [6:0] requestDOI_uncommonBits = _requestDOI_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [12:0] _beatsAI_decode_T = 13'h3F << in_0_a_bits_size; // @[package.scala:243:71] wire [5:0] _beatsAI_decode_T_1 = _beatsAI_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _beatsAI_decode_T_2 = ~_beatsAI_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] beatsAI_decode = _beatsAI_decode_T_2[5:3]; // @[package.scala:243:46] wire _beatsAI_opdata_T = in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire beatsAI_opdata = ~_beatsAI_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] beatsAI_0 = beatsAI_opdata ? beatsAI_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [12:0] _beatsDO_decode_T = 13'h3F << out_0_d_bits_size; // @[package.scala:243:71] wire [5:0] _beatsDO_decode_T_1 = _beatsDO_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _beatsDO_decode_T_2 = ~_beatsDO_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] beatsDO_decode = _beatsDO_decode_T_2[5:3]; // @[package.scala:243:46] wire beatsDO_opdata = out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [2:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:355:40] assign out_0_a_valid = portsAOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_opcode = portsAOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_param = portsAOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_size = portsAOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_source = portsAOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_address = portsAOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_mask = portsAOI_filtered_0_bits_mask; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_data = portsAOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_corrupt = portsAOI_filtered_0_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire _portsAOI_filtered_1_valid_T_1; // @[Xbar.scala:355:40] assign out_1_a_valid = portsAOI_filtered_1_valid; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_opcode = portsAOI_filtered_1_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_param = portsAOI_filtered_1_bits_param; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_size = portsAOI_filtered_1_bits_size; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_source = portsAOI_filtered_1_bits_source; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_address = portsAOI_filtered_1_bits_address; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_mask = portsAOI_filtered_1_bits_mask; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_data = portsAOI_filtered_1_bits_data; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_corrupt = portsAOI_filtered_1_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign _portsAOI_filtered_0_valid_T_1 = in_0_a_valid & _portsAOI_filtered_0_valid_T; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_0_valid = _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsAOI_filtered_1_valid_T_1 = in_0_a_valid & _portsAOI_filtered_1_valid_T; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_1_valid = _portsAOI_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _portsAOI_in_0_a_ready_T = requestAIO_0_0 & portsAOI_filtered_0_ready; // @[Mux.scala:30:73] wire _portsAOI_in_0_a_ready_T_2 = _portsAOI_in_0_a_ready_T; // @[Mux.scala:30:73] assign _portsAOI_in_0_a_ready_WIRE = _portsAOI_in_0_a_ready_T_2; // @[Mux.scala:30:73] assign in_0_a_ready = _portsAOI_in_0_a_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_0_ready_T; // @[Arbiter.scala:94:31] assign out_0_d_ready = portsDIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24] wire _in_0_d_valid_T = portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] assign portsDIO_filtered_0_valid = _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _filtered_0_ready_T_1; // @[Arbiter.scala:94:31] assign out_1_d_ready = portsDIO_filtered_1_0_ready; // @[Xbar.scala:216:19, :352:24] reg [2:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 3'h0; // @[Arbiter.scala:60:30, :61:28] wire latch = idle & in_0_d_ready; // @[Xbar.scala:159:18] wire [1:0] _readys_T = {1'h0, portsDIO_filtered_0_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_valid = _readys_T; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_1 = readys_valid == _readys_T; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_3 = ~_readys_T_2; // @[Arbiter.scala:22:12] wire _readys_T_4 = ~_readys_T_1; // @[Arbiter.scala:22:{12,19}] reg [1:0] readys_mask; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala:23:23, :24:30] wire [1:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala:21:23, :24:{28,30}] wire [3:0] readys_filter = {_readys_filter_T_1, readys_valid}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [2:0] _readys_unready_T = readys_filter[3:1]; // @[package.scala:262:48] wire [3:0] _readys_unready_T_1 = {readys_filter[3], readys_filter[2:0] | _readys_unready_T}; // @[package.scala:262:{43,48}] wire [3:0] _readys_unready_T_2 = _readys_unready_T_1; // @[package.scala:262:43, :263:17] wire [2:0] _readys_unready_T_3 = _readys_unready_T_2[3:1]; // @[package.scala:263:17] wire [3:0] _readys_unready_T_4 = {readys_mask, 2'h0}; // @[Arbiter.scala:23:23, :25:66] wire [3:0] readys_unready = {1'h0, _readys_unready_T_3} | _readys_unready_T_4; // @[Arbiter.scala:25:{52,58,66}] wire [1:0] _readys_readys_T = readys_unready[3:2]; // @[Arbiter.scala:25:58, :26:29] wire [1:0] _readys_readys_T_1 = readys_unready[1:0]; // @[Arbiter.scala:25:58, :26:48] wire [1:0] _readys_readys_T_2 = _readys_readys_T & _readys_readys_T_1; // @[Arbiter.scala:26:{29,39,48}] wire [1:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala:26:{18,39}] wire [1:0] _readys_T_7 = readys_readys; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_5 = |readys_valid; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_6 = latch & _readys_T_5; // @[Arbiter.scala:27:{18,27}, :62:24] wire [1:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [2:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_mask_T_2 = _readys_mask_T_1[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_mask_T_3 = _readys_mask_T | _readys_mask_T_2; // @[package.scala:253:{43,53}] wire [1:0] _readys_mask_T_4 = _readys_mask_T_3; // @[package.scala:253:43, :254:17] wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}] wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}] wire _winner_T = readys_0 & portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T = prefixOR_1; // @[Arbiter.scala:76:48]
Generate the Verilog code corresponding to this FIRRTL code module PE_252 : input clock : Clock input reset : Reset output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>} node _reg_T = eq(io.dir, UInt<1>(0h0)) node _reg_T_1 = mux(_reg_T, io.inR, io.inD) reg reg : SInt<8>, clock when io.en : connect reg, _reg_T_1 connect io.outU, reg connect io.outL, reg
module PE_252( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module ReservationStation : input clock : Clock input reset : Reset output io : { flip alloc : { flip ready : UInt<1>, valid : UInt<1>, bits : { cmd : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, rob_id : { valid : UInt<1>, bits : UInt<6>}, from_matmul_fsm : UInt<1>, from_conv_fsm : UInt<1>}}, flip completed : { valid : UInt<1>, bits : UInt<6>}, issue : { ld : { valid : UInt<1>, flip ready : UInt<1>, cmd : { cmd : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, rob_id : { valid : UInt<1>, bits : UInt<6>}, from_matmul_fsm : UInt<1>, from_conv_fsm : UInt<1>}, rob_id : UInt<6>}, st : { valid : UInt<1>, flip ready : UInt<1>, cmd : { cmd : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, rob_id : { valid : UInt<1>, bits : UInt<6>}, from_matmul_fsm : UInt<1>, from_conv_fsm : UInt<1>}, rob_id : UInt<6>}, ex : { valid : UInt<1>, flip ready : UInt<1>, cmd : { cmd : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, rob_id : { valid : UInt<1>, bits : UInt<6>}, from_matmul_fsm : UInt<1>, from_conv_fsm : UInt<1>}, rob_id : UInt<6>}}, conv_ld_completed : UInt<2>, conv_ex_completed : UInt<2>, conv_st_completed : UInt<2>, matmul_ld_completed : UInt<2>, matmul_ex_completed : UInt<2>, matmul_st_completed : UInt<2>, busy : UInt<1>, counter : { event_signal : UInt<1>[45], external_values : UInt<32>[8], flip external_reset : UInt<1>}} regreset instructions_allocated : UInt<32>, clock, reset, UInt<32>(0h0) node _T = and(io.alloc.ready, io.alloc.valid) when _T : node _instructions_allocated_T = add(instructions_allocated, UInt<1>(0h1)) node _instructions_allocated_T_1 = tail(_instructions_allocated_T, 1) connect instructions_allocated, _instructions_allocated_T_1 reg entries_ld : { valid : UInt<1>, bits : { q : UInt<2>, is_config : UInt<1>, opa : { valid : UInt<1>, bits : { start : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, end : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, wraps_around : UInt<1>}}, opa_is_dst : UInt<1>, opb : { valid : UInt<1>, bits : { start : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, end : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, wraps_around : UInt<1>}}, issued : UInt<1>, complete_on_issue : UInt<1>, cmd : { cmd : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, rob_id : { valid : UInt<1>, bits : UInt<6>}, from_matmul_fsm : UInt<1>, from_conv_fsm : UInt<1>}, deps_ld : UInt<1>[8], deps_ex : UInt<1>[16], deps_st : UInt<1>[4], allocated_at : UInt<32>}}[8], clock reg entries_ex : { valid : UInt<1>, bits : { q : UInt<2>, is_config : UInt<1>, opa : { valid : UInt<1>, bits : { start : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, end : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, wraps_around : UInt<1>}}, opa_is_dst : UInt<1>, opb : { valid : UInt<1>, bits : { start : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, end : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, wraps_around : UInt<1>}}, issued : UInt<1>, complete_on_issue : UInt<1>, cmd : { cmd : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, rob_id : { valid : UInt<1>, bits : UInt<6>}, from_matmul_fsm : UInt<1>, from_conv_fsm : UInt<1>}, deps_ld : UInt<1>[8], deps_ex : UInt<1>[16], deps_st : UInt<1>[4], allocated_at : UInt<32>}}[16], clock reg entries_st : { valid : UInt<1>, bits : { q : UInt<2>, is_config : UInt<1>, opa : { valid : UInt<1>, bits : { start : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, end : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, wraps_around : UInt<1>}}, opa_is_dst : UInt<1>, opb : { valid : UInt<1>, bits : { start : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, end : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, wraps_around : UInt<1>}}, issued : UInt<1>, complete_on_issue : UInt<1>, cmd : { cmd : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, rob_id : { valid : UInt<1>, bits : UInt<6>}, from_matmul_fsm : UInt<1>, from_conv_fsm : UInt<1>}, deps_ld : UInt<1>[8], deps_ex : UInt<1>[16], deps_st : UInt<1>[4], allocated_at : UInt<32>}}[4], clock node _empty_ld_T = or(entries_ld[0].valid, entries_ld[1].valid) node _empty_ld_T_1 = or(_empty_ld_T, entries_ld[2].valid) node _empty_ld_T_2 = or(_empty_ld_T_1, entries_ld[3].valid) node _empty_ld_T_3 = or(_empty_ld_T_2, entries_ld[4].valid) node _empty_ld_T_4 = or(_empty_ld_T_3, entries_ld[5].valid) node _empty_ld_T_5 = or(_empty_ld_T_4, entries_ld[6].valid) node _empty_ld_T_6 = or(_empty_ld_T_5, entries_ld[7].valid) node empty_ld = eq(_empty_ld_T_6, UInt<1>(0h0)) node _empty_ex_T = or(entries_ex[0].valid, entries_ex[1].valid) node _empty_ex_T_1 = or(_empty_ex_T, entries_ex[2].valid) node _empty_ex_T_2 = or(_empty_ex_T_1, entries_ex[3].valid) node _empty_ex_T_3 = or(_empty_ex_T_2, entries_ex[4].valid) node _empty_ex_T_4 = or(_empty_ex_T_3, entries_ex[5].valid) node _empty_ex_T_5 = or(_empty_ex_T_4, entries_ex[6].valid) node _empty_ex_T_6 = or(_empty_ex_T_5, entries_ex[7].valid) node _empty_ex_T_7 = or(_empty_ex_T_6, entries_ex[8].valid) node _empty_ex_T_8 = or(_empty_ex_T_7, entries_ex[9].valid) node _empty_ex_T_9 = or(_empty_ex_T_8, entries_ex[10].valid) node _empty_ex_T_10 = or(_empty_ex_T_9, entries_ex[11].valid) node _empty_ex_T_11 = or(_empty_ex_T_10, entries_ex[12].valid) node _empty_ex_T_12 = or(_empty_ex_T_11, entries_ex[13].valid) node _empty_ex_T_13 = or(_empty_ex_T_12, entries_ex[14].valid) node _empty_ex_T_14 = or(_empty_ex_T_13, entries_ex[15].valid) node empty_ex = eq(_empty_ex_T_14, UInt<1>(0h0)) node _empty_st_T = or(entries_st[0].valid, entries_st[1].valid) node _empty_st_T_1 = or(_empty_st_T, entries_st[2].valid) node _empty_st_T_2 = or(_empty_st_T_1, entries_st[3].valid) node empty_st = eq(_empty_st_T_2, UInt<1>(0h0)) node _full_ld_T = and(entries_ld[0].valid, entries_ld[1].valid) node _full_ld_T_1 = and(_full_ld_T, entries_ld[2].valid) node _full_ld_T_2 = and(_full_ld_T_1, entries_ld[3].valid) node _full_ld_T_3 = and(_full_ld_T_2, entries_ld[4].valid) node _full_ld_T_4 = and(_full_ld_T_3, entries_ld[5].valid) node _full_ld_T_5 = and(_full_ld_T_4, entries_ld[6].valid) node full_ld = and(_full_ld_T_5, entries_ld[7].valid) node _full_ex_T = and(entries_ex[0].valid, entries_ex[1].valid) node _full_ex_T_1 = and(_full_ex_T, entries_ex[2].valid) node _full_ex_T_2 = and(_full_ex_T_1, entries_ex[3].valid) node _full_ex_T_3 = and(_full_ex_T_2, entries_ex[4].valid) node _full_ex_T_4 = and(_full_ex_T_3, entries_ex[5].valid) node _full_ex_T_5 = and(_full_ex_T_4, entries_ex[6].valid) node _full_ex_T_6 = and(_full_ex_T_5, entries_ex[7].valid) node _full_ex_T_7 = and(_full_ex_T_6, entries_ex[8].valid) node _full_ex_T_8 = and(_full_ex_T_7, entries_ex[9].valid) node _full_ex_T_9 = and(_full_ex_T_8, entries_ex[10].valid) node _full_ex_T_10 = and(_full_ex_T_9, entries_ex[11].valid) node _full_ex_T_11 = and(_full_ex_T_10, entries_ex[12].valid) node _full_ex_T_12 = and(_full_ex_T_11, entries_ex[13].valid) node _full_ex_T_13 = and(_full_ex_T_12, entries_ex[14].valid) node full_ex = and(_full_ex_T_13, entries_ex[15].valid) node _full_st_T = and(entries_st[0].valid, entries_st[1].valid) node _full_st_T_1 = and(_full_st_T, entries_st[2].valid) node full_st = and(_full_st_T_1, entries_st[3].valid) node _empty_T = or(entries_ld[0].valid, entries_ld[1].valid) node _empty_T_1 = or(_empty_T, entries_ld[2].valid) node _empty_T_2 = or(_empty_T_1, entries_ld[3].valid) node _empty_T_3 = or(_empty_T_2, entries_ld[4].valid) node _empty_T_4 = or(_empty_T_3, entries_ld[5].valid) node _empty_T_5 = or(_empty_T_4, entries_ld[6].valid) node _empty_T_6 = or(_empty_T_5, entries_ld[7].valid) node _empty_T_7 = or(_empty_T_6, entries_ex[0].valid) node _empty_T_8 = or(_empty_T_7, entries_ex[1].valid) node _empty_T_9 = or(_empty_T_8, entries_ex[2].valid) node _empty_T_10 = or(_empty_T_9, entries_ex[3].valid) node _empty_T_11 = or(_empty_T_10, entries_ex[4].valid) node _empty_T_12 = or(_empty_T_11, entries_ex[5].valid) node _empty_T_13 = or(_empty_T_12, entries_ex[6].valid) node _empty_T_14 = or(_empty_T_13, entries_ex[7].valid) node _empty_T_15 = or(_empty_T_14, entries_ex[8].valid) node _empty_T_16 = or(_empty_T_15, entries_ex[9].valid) node _empty_T_17 = or(_empty_T_16, entries_ex[10].valid) node _empty_T_18 = or(_empty_T_17, entries_ex[11].valid) node _empty_T_19 = or(_empty_T_18, entries_ex[12].valid) node _empty_T_20 = or(_empty_T_19, entries_ex[13].valid) node _empty_T_21 = or(_empty_T_20, entries_ex[14].valid) node _empty_T_22 = or(_empty_T_21, entries_ex[15].valid) node _empty_T_23 = or(_empty_T_22, entries_st[0].valid) node _empty_T_24 = or(_empty_T_23, entries_st[1].valid) node _empty_T_25 = or(_empty_T_24, entries_st[2].valid) node _empty_T_26 = or(_empty_T_25, entries_st[3].valid) node empty = eq(_empty_T_26, UInt<1>(0h0)) node _full_T = and(entries_ld[0].valid, entries_ld[1].valid) node _full_T_1 = and(_full_T, entries_ld[2].valid) node _full_T_2 = and(_full_T_1, entries_ld[3].valid) node _full_T_3 = and(_full_T_2, entries_ld[4].valid) node _full_T_4 = and(_full_T_3, entries_ld[5].valid) node _full_T_5 = and(_full_T_4, entries_ld[6].valid) node _full_T_6 = and(_full_T_5, entries_ld[7].valid) node _full_T_7 = and(_full_T_6, entries_ex[0].valid) node _full_T_8 = and(_full_T_7, entries_ex[1].valid) node _full_T_9 = and(_full_T_8, entries_ex[2].valid) node _full_T_10 = and(_full_T_9, entries_ex[3].valid) node _full_T_11 = and(_full_T_10, entries_ex[4].valid) node _full_T_12 = and(_full_T_11, entries_ex[5].valid) node _full_T_13 = and(_full_T_12, entries_ex[6].valid) node _full_T_14 = and(_full_T_13, entries_ex[7].valid) node _full_T_15 = and(_full_T_14, entries_ex[8].valid) node _full_T_16 = and(_full_T_15, entries_ex[9].valid) node _full_T_17 = and(_full_T_16, entries_ex[10].valid) node _full_T_18 = and(_full_T_17, entries_ex[11].valid) node _full_T_19 = and(_full_T_18, entries_ex[12].valid) node _full_T_20 = and(_full_T_19, entries_ex[13].valid) node _full_T_21 = and(_full_T_20, entries_ex[14].valid) node _full_T_22 = and(_full_T_21, entries_ex[15].valid) node _full_T_23 = and(_full_T_22, entries_st[0].valid) node _full_T_24 = and(_full_T_23, entries_st[1].valid) node _full_T_25 = and(_full_T_24, entries_st[2].valid) node full = and(_full_T_25, entries_st[3].valid) node _utilization_T = add(entries_ld[1].valid, entries_ld[2].valid) node _utilization_T_1 = bits(_utilization_T, 1, 0) node _utilization_T_2 = add(entries_ld[0].valid, _utilization_T_1) node _utilization_T_3 = bits(_utilization_T_2, 1, 0) node _utilization_T_4 = add(entries_ld[3].valid, entries_ld[4].valid) node _utilization_T_5 = bits(_utilization_T_4, 1, 0) node _utilization_T_6 = add(entries_ld[5].valid, entries_ld[6].valid) node _utilization_T_7 = bits(_utilization_T_6, 1, 0) node _utilization_T_8 = add(_utilization_T_5, _utilization_T_7) node _utilization_T_9 = bits(_utilization_T_8, 2, 0) node _utilization_T_10 = add(_utilization_T_3, _utilization_T_9) node _utilization_T_11 = bits(_utilization_T_10, 2, 0) node _utilization_T_12 = add(entries_ex[0].valid, entries_ex[1].valid) node _utilization_T_13 = bits(_utilization_T_12, 1, 0) node _utilization_T_14 = add(entries_ld[7].valid, _utilization_T_13) node _utilization_T_15 = bits(_utilization_T_14, 1, 0) node _utilization_T_16 = add(entries_ex[2].valid, entries_ex[3].valid) node _utilization_T_17 = bits(_utilization_T_16, 1, 0) node _utilization_T_18 = add(entries_ex[4].valid, entries_ex[5].valid) node _utilization_T_19 = bits(_utilization_T_18, 1, 0) node _utilization_T_20 = add(_utilization_T_17, _utilization_T_19) node _utilization_T_21 = bits(_utilization_T_20, 2, 0) node _utilization_T_22 = add(_utilization_T_15, _utilization_T_21) node _utilization_T_23 = bits(_utilization_T_22, 2, 0) node _utilization_T_24 = add(_utilization_T_11, _utilization_T_23) node _utilization_T_25 = bits(_utilization_T_24, 3, 0) node _utilization_T_26 = add(entries_ex[7].valid, entries_ex[8].valid) node _utilization_T_27 = bits(_utilization_T_26, 1, 0) node _utilization_T_28 = add(entries_ex[6].valid, _utilization_T_27) node _utilization_T_29 = bits(_utilization_T_28, 1, 0) node _utilization_T_30 = add(entries_ex[9].valid, entries_ex[10].valid) node _utilization_T_31 = bits(_utilization_T_30, 1, 0) node _utilization_T_32 = add(entries_ex[11].valid, entries_ex[12].valid) node _utilization_T_33 = bits(_utilization_T_32, 1, 0) node _utilization_T_34 = add(_utilization_T_31, _utilization_T_33) node _utilization_T_35 = bits(_utilization_T_34, 2, 0) node _utilization_T_36 = add(_utilization_T_29, _utilization_T_35) node _utilization_T_37 = bits(_utilization_T_36, 2, 0) node _utilization_T_38 = add(entries_ex[14].valid, entries_ex[15].valid) node _utilization_T_39 = bits(_utilization_T_38, 1, 0) node _utilization_T_40 = add(entries_ex[13].valid, _utilization_T_39) node _utilization_T_41 = bits(_utilization_T_40, 1, 0) node _utilization_T_42 = add(entries_st[0].valid, entries_st[1].valid) node _utilization_T_43 = bits(_utilization_T_42, 1, 0) node _utilization_T_44 = add(entries_st[2].valid, entries_st[3].valid) node _utilization_T_45 = bits(_utilization_T_44, 1, 0) node _utilization_T_46 = add(_utilization_T_43, _utilization_T_45) node _utilization_T_47 = bits(_utilization_T_46, 2, 0) node _utilization_T_48 = add(_utilization_T_41, _utilization_T_47) node _utilization_T_49 = bits(_utilization_T_48, 2, 0) node _utilization_T_50 = add(_utilization_T_37, _utilization_T_49) node _utilization_T_51 = bits(_utilization_T_50, 3, 0) node _utilization_T_52 = add(_utilization_T_25, _utilization_T_51) node utilization = bits(_utilization_T_52, 4, 0) regreset solitary_preload : UInt<1>, clock, reset, UInt<1>(0h0) node _io_busy_T = eq(empty, UInt<1>(0h0)) node _io_busy_T_1 = eq(utilization, UInt<1>(0h1)) node _io_busy_T_2 = and(_io_busy_T_1, solitary_preload) node _io_busy_T_3 = eq(_io_busy_T_2, UInt<1>(0h0)) node _io_busy_T_4 = and(_io_busy_T, _io_busy_T_3) connect io.busy, _io_busy_T_4 wire conv_ld_issue_completed : UInt<1> connect conv_ld_issue_completed, UInt<1>(0h0) wire conv_st_issue_completed : UInt<1> connect conv_st_issue_completed, UInt<1>(0h0) wire conv_ex_issue_completed : UInt<1> connect conv_ex_issue_completed, UInt<1>(0h0) wire conv_ld_completed : UInt<1> connect conv_ld_completed, UInt<1>(0h0) wire conv_st_completed : UInt<1> connect conv_st_completed, UInt<1>(0h0) wire conv_ex_completed : UInt<1> connect conv_ex_completed, UInt<1>(0h0) wire matmul_ld_issue_completed : UInt<1> connect matmul_ld_issue_completed, UInt<1>(0h0) wire matmul_st_issue_completed : UInt<1> connect matmul_st_issue_completed, UInt<1>(0h0) wire matmul_ex_issue_completed : UInt<1> connect matmul_ex_issue_completed, UInt<1>(0h0) wire matmul_ld_completed : UInt<1> connect matmul_ld_completed, UInt<1>(0h0) wire matmul_st_completed : UInt<1> connect matmul_st_completed, UInt<1>(0h0) wire matmul_ex_completed : UInt<1> connect matmul_ex_completed, UInt<1>(0h0) node _io_conv_ld_completed_T = add(conv_ld_issue_completed, conv_ld_completed) connect io.conv_ld_completed, _io_conv_ld_completed_T node _io_conv_st_completed_T = add(conv_st_issue_completed, conv_st_completed) connect io.conv_st_completed, _io_conv_st_completed_T node _io_conv_ex_completed_T = add(conv_ex_issue_completed, conv_ex_completed) connect io.conv_ex_completed, _io_conv_ex_completed_T node _io_matmul_ld_completed_T = add(matmul_ld_issue_completed, matmul_ld_completed) connect io.matmul_ld_completed, _io_matmul_ld_completed_T node _io_matmul_st_completed_T = add(matmul_st_issue_completed, matmul_st_completed) connect io.matmul_st_completed, _io_matmul_st_completed_T node _io_matmul_ex_completed_T = add(matmul_ex_issue_completed, matmul_ex_completed) connect io.matmul_ex_completed, _io_matmul_ex_completed_T reg a_stride : UInt<14>, clock reg c_stride : UInt<14>, clock reg a_transpose : UInt<1>, clock reg ld_block_strides : UInt<14>[3], clock reg pooling_is_enabled : UInt<1>, clock reg ld_pixel_repeats : UInt<3>[3], clock wire new_entry : { q : UInt<2>, is_config : UInt<1>, opa : { valid : UInt<1>, bits : { start : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, end : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, wraps_around : UInt<1>}}, opa_is_dst : UInt<1>, opb : { valid : UInt<1>, bits : { start : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, end : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, wraps_around : UInt<1>}}, issued : UInt<1>, complete_on_issue : UInt<1>, cmd : { cmd : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, rob_id : { valid : UInt<1>, bits : UInt<6>}, from_matmul_fsm : UInt<1>, from_conv_fsm : UInt<1>}, deps_ld : UInt<1>[8], deps_ex : UInt<1>[16], deps_st : UInt<1>[4], allocated_at : UInt<32>} invalidate new_entry.allocated_at invalidate new_entry.deps_st[0] invalidate new_entry.deps_st[1] invalidate new_entry.deps_st[2] invalidate new_entry.deps_st[3] invalidate new_entry.deps_ex[0] invalidate new_entry.deps_ex[1] invalidate new_entry.deps_ex[2] invalidate new_entry.deps_ex[3] invalidate new_entry.deps_ex[4] invalidate new_entry.deps_ex[5] invalidate new_entry.deps_ex[6] invalidate new_entry.deps_ex[7] invalidate new_entry.deps_ex[8] invalidate new_entry.deps_ex[9] invalidate new_entry.deps_ex[10] invalidate new_entry.deps_ex[11] invalidate new_entry.deps_ex[12] invalidate new_entry.deps_ex[13] invalidate new_entry.deps_ex[14] invalidate new_entry.deps_ex[15] invalidate new_entry.deps_ld[0] invalidate new_entry.deps_ld[1] invalidate new_entry.deps_ld[2] invalidate new_entry.deps_ld[3] invalidate new_entry.deps_ld[4] invalidate new_entry.deps_ld[5] invalidate new_entry.deps_ld[6] invalidate new_entry.deps_ld[7] invalidate new_entry.cmd.from_conv_fsm invalidate new_entry.cmd.from_matmul_fsm invalidate new_entry.cmd.rob_id.bits invalidate new_entry.cmd.rob_id.valid invalidate new_entry.cmd.cmd.status.uie invalidate new_entry.cmd.cmd.status.sie invalidate new_entry.cmd.cmd.status.hie invalidate new_entry.cmd.cmd.status.mie invalidate new_entry.cmd.cmd.status.upie invalidate new_entry.cmd.cmd.status.spie invalidate new_entry.cmd.cmd.status.ube invalidate new_entry.cmd.cmd.status.mpie invalidate new_entry.cmd.cmd.status.spp invalidate new_entry.cmd.cmd.status.vs invalidate new_entry.cmd.cmd.status.mpp invalidate new_entry.cmd.cmd.status.fs invalidate new_entry.cmd.cmd.status.xs invalidate new_entry.cmd.cmd.status.mprv invalidate new_entry.cmd.cmd.status.sum invalidate new_entry.cmd.cmd.status.mxr invalidate new_entry.cmd.cmd.status.tvm invalidate new_entry.cmd.cmd.status.tw invalidate new_entry.cmd.cmd.status.tsr invalidate new_entry.cmd.cmd.status.zero1 invalidate new_entry.cmd.cmd.status.sd_rv32 invalidate new_entry.cmd.cmd.status.uxl invalidate new_entry.cmd.cmd.status.sxl invalidate new_entry.cmd.cmd.status.sbe invalidate new_entry.cmd.cmd.status.mbe invalidate new_entry.cmd.cmd.status.gva invalidate new_entry.cmd.cmd.status.mpv invalidate new_entry.cmd.cmd.status.zero2 invalidate new_entry.cmd.cmd.status.sd invalidate new_entry.cmd.cmd.status.v invalidate new_entry.cmd.cmd.status.prv invalidate new_entry.cmd.cmd.status.dv invalidate new_entry.cmd.cmd.status.dprv invalidate new_entry.cmd.cmd.status.isa invalidate new_entry.cmd.cmd.status.wfi invalidate new_entry.cmd.cmd.status.cease invalidate new_entry.cmd.cmd.status.debug invalidate new_entry.cmd.cmd.rs2 invalidate new_entry.cmd.cmd.rs1 invalidate new_entry.cmd.cmd.inst.opcode invalidate new_entry.cmd.cmd.inst.rd invalidate new_entry.cmd.cmd.inst.xs2 invalidate new_entry.cmd.cmd.inst.xs1 invalidate new_entry.cmd.cmd.inst.xd invalidate new_entry.cmd.cmd.inst.rs1 invalidate new_entry.cmd.cmd.inst.rs2 invalidate new_entry.cmd.cmd.inst.funct invalidate new_entry.complete_on_issue invalidate new_entry.issued invalidate new_entry.opb.bits.wraps_around invalidate new_entry.opb.bits.end.data invalidate new_entry.opb.bits.end.garbage_bit invalidate new_entry.opb.bits.end.garbage invalidate new_entry.opb.bits.end.norm_cmd invalidate new_entry.opb.bits.end.read_full_acc_row invalidate new_entry.opb.bits.end.accumulate invalidate new_entry.opb.bits.end.is_acc_addr invalidate new_entry.opb.bits.start.data invalidate new_entry.opb.bits.start.garbage_bit invalidate new_entry.opb.bits.start.garbage invalidate new_entry.opb.bits.start.norm_cmd invalidate new_entry.opb.bits.start.read_full_acc_row invalidate new_entry.opb.bits.start.accumulate invalidate new_entry.opb.bits.start.is_acc_addr invalidate new_entry.opb.valid invalidate new_entry.opa_is_dst invalidate new_entry.opa.bits.wraps_around invalidate new_entry.opa.bits.end.data invalidate new_entry.opa.bits.end.garbage_bit invalidate new_entry.opa.bits.end.garbage invalidate new_entry.opa.bits.end.norm_cmd invalidate new_entry.opa.bits.end.read_full_acc_row invalidate new_entry.opa.bits.end.accumulate invalidate new_entry.opa.bits.end.is_acc_addr invalidate new_entry.opa.bits.start.data invalidate new_entry.opa.bits.start.garbage_bit invalidate new_entry.opa.bits.start.garbage invalidate new_entry.opa.bits.start.norm_cmd invalidate new_entry.opa.bits.start.read_full_acc_row invalidate new_entry.opa.bits.start.accumulate invalidate new_entry.opa.bits.start.is_acc_addr invalidate new_entry.opa.valid invalidate new_entry.is_config invalidate new_entry.q wire new_allocs_oh_ld : UInt<1>[8] wire new_allocs_oh_ex : UInt<1>[16] wire new_allocs_oh_st : UInt<1>[4] connect new_allocs_oh_ld[0], UInt<1>(0h0) connect new_allocs_oh_ld[1], UInt<1>(0h0) connect new_allocs_oh_ld[2], UInt<1>(0h0) connect new_allocs_oh_ld[3], UInt<1>(0h0) connect new_allocs_oh_ld[4], UInt<1>(0h0) connect new_allocs_oh_ld[5], UInt<1>(0h0) connect new_allocs_oh_ld[6], UInt<1>(0h0) connect new_allocs_oh_ld[7], UInt<1>(0h0) connect new_allocs_oh_ex[0], UInt<1>(0h0) connect new_allocs_oh_ex[1], UInt<1>(0h0) connect new_allocs_oh_ex[2], UInt<1>(0h0) connect new_allocs_oh_ex[3], UInt<1>(0h0) connect new_allocs_oh_ex[4], UInt<1>(0h0) connect new_allocs_oh_ex[5], UInt<1>(0h0) connect new_allocs_oh_ex[6], UInt<1>(0h0) connect new_allocs_oh_ex[7], UInt<1>(0h0) connect new_allocs_oh_ex[8], UInt<1>(0h0) connect new_allocs_oh_ex[9], UInt<1>(0h0) connect new_allocs_oh_ex[10], UInt<1>(0h0) connect new_allocs_oh_ex[11], UInt<1>(0h0) connect new_allocs_oh_ex[12], UInt<1>(0h0) connect new_allocs_oh_ex[13], UInt<1>(0h0) connect new_allocs_oh_ex[14], UInt<1>(0h0) connect new_allocs_oh_ex[15], UInt<1>(0h0) connect new_allocs_oh_st[0], UInt<1>(0h0) connect new_allocs_oh_st[1], UInt<1>(0h0) connect new_allocs_oh_st[2], UInt<1>(0h0) connect new_allocs_oh_st[3], UInt<1>(0h0) node alloc_fire = and(io.alloc.ready, io.alloc.valid) connect io.alloc.ready, UInt<1>(0h0) when io.alloc.valid : node _funct_is_compute_T = eq(io.alloc.bits.cmd.inst.funct, UInt<3>(0h5)) node _funct_is_compute_T_1 = eq(io.alloc.bits.cmd.inst.funct, UInt<3>(0h4)) node funct_is_compute = or(_funct_is_compute_T, _funct_is_compute_T_1) node config_cmd_type = bits(io.alloc.bits.cmd.rs1, 1, 0) connect new_entry.issued, UInt<1>(0h0) connect new_entry.cmd, io.alloc.bits node _new_entry_is_config_T = eq(io.alloc.bits.cmd.inst.funct, UInt<1>(0h0)) connect new_entry.is_config, _new_entry_is_config_T wire op1 : { valid : UInt<1>, bits : { start : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, end : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, wraps_around : UInt<1>}} connect op1.valid, UInt<1>(0h0) invalidate op1.bits.wraps_around invalidate op1.bits.end.data invalidate op1.bits.end.garbage_bit invalidate op1.bits.end.garbage invalidate op1.bits.end.norm_cmd invalidate op1.bits.end.read_full_acc_row invalidate op1.bits.end.accumulate invalidate op1.bits.end.is_acc_addr invalidate op1.bits.start.data invalidate op1.bits.start.garbage_bit invalidate op1.bits.start.garbage invalidate op1.bits.start.norm_cmd invalidate op1.bits.start.read_full_acc_row invalidate op1.bits.start.accumulate invalidate op1.bits.start.is_acc_addr wire op2 : { valid : UInt<1>, bits : { start : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, end : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, wraps_around : UInt<1>}} connect op2.valid, UInt<1>(0h0) invalidate op2.bits.wraps_around invalidate op2.bits.end.data invalidate op2.bits.end.garbage_bit invalidate op2.bits.end.garbage invalidate op2.bits.end.norm_cmd invalidate op2.bits.end.read_full_acc_row invalidate op2.bits.end.accumulate invalidate op2.bits.end.is_acc_addr invalidate op2.bits.start.data invalidate op2.bits.start.garbage_bit invalidate op2.bits.start.garbage invalidate op2.bits.start.norm_cmd invalidate op2.bits.start.read_full_acc_row invalidate op2.bits.start.accumulate invalidate op2.bits.start.is_acc_addr wire dst : { valid : UInt<1>, bits : { start : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, end : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, wraps_around : UInt<1>}} connect dst.valid, UInt<1>(0h0) invalidate dst.bits.wraps_around invalidate dst.bits.end.data invalidate dst.bits.end.garbage_bit invalidate dst.bits.end.garbage invalidate dst.bits.end.norm_cmd invalidate dst.bits.end.read_full_acc_row invalidate dst.bits.end.accumulate invalidate dst.bits.end.is_acc_addr invalidate dst.bits.start.data invalidate dst.bits.start.garbage_bit invalidate dst.bits.start.garbage invalidate dst.bits.start.norm_cmd invalidate dst.bits.start.read_full_acc_row invalidate dst.bits.start.accumulate invalidate dst.bits.start.is_acc_addr node _T_1 = and(op1.valid, op2.valid) node _T_2 = and(_T_1, dst.valid) node _T_3 = eq(_T_2, UInt<1>(0h0)) node _T_4 = asUInt(reset) node _T_5 = eq(_T_4, UInt<1>(0h0)) when _T_5 : node _T_6 = eq(_T_3, UInt<1>(0h0)) when _T_6 : printf(clock, UInt<1>(0h1), "Assertion failed\n at ReservationStation.scala:205 assert(!(op1.valid && op2.valid && dst.valid))\n") : printf assert(clock, _T_3, UInt<1>(0h1), "") : assert connect new_entry.opa_is_dst, dst.valid when dst.valid : connect new_entry.opa, dst node _new_entry_opb_T = mux(op1.valid, op1, op2) connect new_entry.opb, _new_entry_opb_T else : node _new_entry_opa_T = mux(op1.valid, op1, op2) connect new_entry.opa, _new_entry_opa_T connect new_entry.opb, op2 node _op1_valid_T = eq(io.alloc.bits.cmd.inst.funct, UInt<3>(0h6)) node _op1_valid_T_1 = or(_op1_valid_T, funct_is_compute) connect op1.valid, _op1_valid_T_1 wire _op1_bits_start_WIRE : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} wire _op1_bits_start_WIRE_1 : UInt<32> connect _op1_bits_start_WIRE_1, io.alloc.bits.cmd.rs1 node _op1_bits_start_T = bits(_op1_bits_start_WIRE_1, 13, 0) connect _op1_bits_start_WIRE.data, _op1_bits_start_T node _op1_bits_start_T_1 = bits(_op1_bits_start_WIRE_1, 14, 14) connect _op1_bits_start_WIRE.garbage_bit, _op1_bits_start_T_1 node _op1_bits_start_T_2 = bits(_op1_bits_start_WIRE_1, 25, 15) connect _op1_bits_start_WIRE.garbage, _op1_bits_start_T_2 node _op1_bits_start_T_3 = bits(_op1_bits_start_WIRE_1, 28, 26) wire _op1_bits_start_WIRE_2 : UInt<3> connect _op1_bits_start_WIRE_2, _op1_bits_start_T_3 wire _op1_bits_start_WIRE_3 : UInt<3> connect _op1_bits_start_WIRE_3, _op1_bits_start_WIRE_2 connect _op1_bits_start_WIRE.norm_cmd, _op1_bits_start_WIRE_3 node _op1_bits_start_T_4 = bits(_op1_bits_start_WIRE_1, 29, 29) connect _op1_bits_start_WIRE.read_full_acc_row, _op1_bits_start_T_4 node _op1_bits_start_T_5 = bits(_op1_bits_start_WIRE_1, 30, 30) connect _op1_bits_start_WIRE.accumulate, _op1_bits_start_T_5 node _op1_bits_start_T_6 = bits(_op1_bits_start_WIRE_1, 31, 31) connect _op1_bits_start_WIRE.is_acc_addr, _op1_bits_start_T_6 connect op1.bits.start, _op1_bits_start_WIRE node _T_7 = eq(io.alloc.bits.cmd.inst.funct, UInt<3>(0h6)) when _T_7 : node preload_rows = bits(io.alloc.bits.cmd.rs1, 50, 48) wire op1_bits_end_result : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} connect op1_bits_end_result, op1.bits.start node _op1_bits_end_result_data_T = add(op1.bits.start.data, preload_rows) node _op1_bits_end_result_data_T_1 = tail(_op1_bits_end_result_data_T, 1) connect op1_bits_end_result.data, _op1_bits_end_result_data_T_1 connect op1.bits.end, op1_bits_end_result node op1_bits_wraps_around_sum = add(op1.bits.start.data, preload_rows) node _op1_bits_wraps_around_overflow_T = bits(op1_bits_wraps_around_sum, 12, 12) node _op1_bits_wraps_around_overflow_T_1 = bits(op1_bits_wraps_around_sum, 14, 14) node op1_bits_wraps_around_overflow = mux(op1.bits.start.is_acc_addr, _op1_bits_wraps_around_overflow_T, _op1_bits_wraps_around_overflow_T_1) wire op1_bits_wraps_around_result : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} connect op1_bits_wraps_around_result, op1.bits.start node _op1_bits_wraps_around_result_data_T = bits(op1_bits_wraps_around_sum, 13, 0) connect op1_bits_wraps_around_result.data, _op1_bits_wraps_around_result_data_T connect op1.bits.wraps_around, op1_bits_wraps_around_overflow else : node rows = bits(io.alloc.bits.cmd.rs1, 50, 48) node cols = bits(io.alloc.bits.cmd.rs1, 34, 32) node _compute_rows_T = mux(a_transpose, cols, rows) node compute_rows = mul(_compute_rows_T, a_stride) wire op1_bits_end_result_1 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} connect op1_bits_end_result_1, op1.bits.start node _op1_bits_end_result_data_T_2 = add(op1.bits.start.data, compute_rows) node _op1_bits_end_result_data_T_3 = tail(_op1_bits_end_result_data_T_2, 1) connect op1_bits_end_result_1.data, _op1_bits_end_result_data_T_3 connect op1.bits.end, op1_bits_end_result_1 node op1_bits_wraps_around_sum_1 = add(op1.bits.start.data, compute_rows) node _op1_bits_wraps_around_overflow_T_2 = bits(op1_bits_wraps_around_sum_1, 12, 12) node _op1_bits_wraps_around_overflow_T_3 = bits(op1_bits_wraps_around_sum_1, 14, 14) node op1_bits_wraps_around_overflow_1 = mux(op1.bits.start.is_acc_addr, _op1_bits_wraps_around_overflow_T_2, _op1_bits_wraps_around_overflow_T_3) wire op1_bits_wraps_around_result_1 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} connect op1_bits_wraps_around_result_1, op1.bits.start node _op1_bits_wraps_around_result_data_T_1 = bits(op1_bits_wraps_around_sum_1, 13, 0) connect op1_bits_wraps_around_result_1.data, _op1_bits_wraps_around_result_data_T_1 connect op1.bits.wraps_around, op1_bits_wraps_around_overflow_1 node _op2_valid_T = eq(io.alloc.bits.cmd.inst.funct, UInt<2>(0h3)) node _op2_valid_T_1 = or(funct_is_compute, _op2_valid_T) connect op2.valid, _op2_valid_T_1 wire _op2_bits_start_WIRE : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} wire _op2_bits_start_WIRE_1 : UInt<32> connect _op2_bits_start_WIRE_1, io.alloc.bits.cmd.rs2 node _op2_bits_start_T = bits(_op2_bits_start_WIRE_1, 13, 0) connect _op2_bits_start_WIRE.data, _op2_bits_start_T node _op2_bits_start_T_1 = bits(_op2_bits_start_WIRE_1, 14, 14) connect _op2_bits_start_WIRE.garbage_bit, _op2_bits_start_T_1 node _op2_bits_start_T_2 = bits(_op2_bits_start_WIRE_1, 25, 15) connect _op2_bits_start_WIRE.garbage, _op2_bits_start_T_2 node _op2_bits_start_T_3 = bits(_op2_bits_start_WIRE_1, 28, 26) wire _op2_bits_start_WIRE_2 : UInt<3> connect _op2_bits_start_WIRE_2, _op2_bits_start_T_3 wire _op2_bits_start_WIRE_3 : UInt<3> connect _op2_bits_start_WIRE_3, _op2_bits_start_WIRE_2 connect _op2_bits_start_WIRE.norm_cmd, _op2_bits_start_WIRE_3 node _op2_bits_start_T_4 = bits(_op2_bits_start_WIRE_1, 29, 29) connect _op2_bits_start_WIRE.read_full_acc_row, _op2_bits_start_T_4 node _op2_bits_start_T_5 = bits(_op2_bits_start_WIRE_1, 30, 30) connect _op2_bits_start_WIRE.accumulate, _op2_bits_start_T_5 node _op2_bits_start_T_6 = bits(_op2_bits_start_WIRE_1, 31, 31) connect _op2_bits_start_WIRE.is_acc_addr, _op2_bits_start_T_6 connect op2.bits.start, _op2_bits_start_WIRE when funct_is_compute : node compute_rows_1 = bits(io.alloc.bits.cmd.rs2, 50, 48) wire op2_bits_end_result : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} connect op2_bits_end_result, op2.bits.start node _op2_bits_end_result_data_T = add(op2.bits.start.data, compute_rows_1) node _op2_bits_end_result_data_T_1 = tail(_op2_bits_end_result_data_T, 1) connect op2_bits_end_result.data, _op2_bits_end_result_data_T_1 connect op2.bits.end, op2_bits_end_result node op2_bits_wraps_around_sum = add(op2.bits.start.data, compute_rows_1) node _op2_bits_wraps_around_overflow_T = bits(op2_bits_wraps_around_sum, 12, 12) node _op2_bits_wraps_around_overflow_T_1 = bits(op2_bits_wraps_around_sum, 14, 14) node op2_bits_wraps_around_overflow = mux(op2.bits.start.is_acc_addr, _op2_bits_wraps_around_overflow_T, _op2_bits_wraps_around_overflow_T_1) wire op2_bits_wraps_around_result : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} connect op2_bits_wraps_around_result, op2.bits.start node _op2_bits_wraps_around_result_data_T = bits(op2_bits_wraps_around_sum, 13, 0) connect op2_bits_wraps_around_result.data, _op2_bits_wraps_around_result_data_T connect op2.bits.wraps_around, op2_bits_wraps_around_overflow else : when pooling_is_enabled : wire _next_bank_addr_WIRE : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} connect _next_bank_addr_WIRE.data, UInt<14>(0h0) connect _next_bank_addr_WIRE.garbage_bit, UInt<1>(0h0) connect _next_bank_addr_WIRE.garbage, UInt<11>(0h0) connect _next_bank_addr_WIRE.norm_cmd, UInt<1>(0h0) connect _next_bank_addr_WIRE.read_full_acc_row, UInt<1>(0h0) connect _next_bank_addr_WIRE.accumulate, UInt<1>(0h0) connect _next_bank_addr_WIRE.is_acc_addr, UInt<1>(0h0) wire next_bank_addr : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} connect next_bank_addr, _next_bank_addr_WIRE connect next_bank_addr.is_acc_addr, UInt<1>(0h1) node _next_bank_addr_data_T = add(UInt<1>(0h0), UInt<1>(0h1)) node _next_bank_addr_data_T_1 = tail(_next_bank_addr_data_T, 1) node _next_bank_addr_data_T_2 = shl(_next_bank_addr_data_T_1, 12) connect next_bank_addr.data, _next_bank_addr_data_T_2 connect op2.bits.end, next_bank_addr node _op2_bits_wraps_around_T = eq(UInt<1>(0h0), UInt<1>(0h0)) connect op2.bits.wraps_around, _op2_bits_wraps_around_T else : node mvout_cols = bits(io.alloc.bits.cmd.rs2, 36, 32) node mvout_rows = bits(io.alloc.bits.cmd.rs2, 50, 48) node _mvout_mats_T = div(mvout_cols, UInt<5>(0h4)) node _mvout_mats_T_1 = rem(mvout_cols, UInt<3>(0h4)) node _mvout_mats_T_2 = neq(_mvout_mats_T_1, UInt<1>(0h0)) node _mvout_mats_T_3 = add(_mvout_mats_T, _mvout_mats_T_2) node mvout_mats = tail(_mvout_mats_T_3, 1) node _total_mvout_rows_T = sub(mvout_mats, UInt<1>(0h1)) node _total_mvout_rows_T_1 = tail(_total_mvout_rows_T, 1) node _total_mvout_rows_T_2 = mul(_total_mvout_rows_T_1, UInt<3>(0h4)) node _total_mvout_rows_T_3 = add(_total_mvout_rows_T_2, mvout_rows) node total_mvout_rows = tail(_total_mvout_rows_T_3, 1) wire op2_bits_end_result_1 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} connect op2_bits_end_result_1, op2.bits.start node _op2_bits_end_result_data_T_2 = add(op2.bits.start.data, total_mvout_rows) node _op2_bits_end_result_data_T_3 = tail(_op2_bits_end_result_data_T_2, 1) connect op2_bits_end_result_1.data, _op2_bits_end_result_data_T_3 connect op2.bits.end, op2_bits_end_result_1 node op2_bits_wraps_around_sum_1 = add(op2.bits.start.data, total_mvout_rows) node _op2_bits_wraps_around_overflow_T_2 = bits(op2_bits_wraps_around_sum_1, 12, 12) node _op2_bits_wraps_around_overflow_T_3 = bits(op2_bits_wraps_around_sum_1, 14, 14) node op2_bits_wraps_around_overflow_1 = mux(op2.bits.start.is_acc_addr, _op2_bits_wraps_around_overflow_T_2, _op2_bits_wraps_around_overflow_T_3) wire op2_bits_wraps_around_result_1 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} connect op2_bits_wraps_around_result_1, op2.bits.start node _op2_bits_wraps_around_result_data_T_1 = bits(op2_bits_wraps_around_sum_1, 13, 0) connect op2_bits_wraps_around_result_1.data, _op2_bits_wraps_around_result_data_T_1 node _op2_bits_wraps_around_T_1 = or(pooling_is_enabled, op2_bits_wraps_around_overflow_1) connect op2.bits.wraps_around, _op2_bits_wraps_around_T_1 node _dst_valid_T = eq(io.alloc.bits.cmd.inst.funct, UInt<3>(0h6)) node _dst_valid_T_1 = eq(io.alloc.bits.cmd.inst.funct, UInt<2>(0h2)) node _dst_valid_T_2 = or(_dst_valid_T, _dst_valid_T_1) node _dst_valid_T_3 = eq(io.alloc.bits.cmd.inst.funct, UInt<1>(0h1)) node _dst_valid_T_4 = or(_dst_valid_T_2, _dst_valid_T_3) node _dst_valid_T_5 = eq(io.alloc.bits.cmd.inst.funct, UInt<4>(0he)) node _dst_valid_T_6 = or(_dst_valid_T_4, _dst_valid_T_5) connect dst.valid, _dst_valid_T_6 node _dst_bits_start_T = bits(io.alloc.bits.cmd.rs2, 31, 0) wire _dst_bits_start_WIRE : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} wire _dst_bits_start_WIRE_1 : UInt<32> connect _dst_bits_start_WIRE_1, _dst_bits_start_T node _dst_bits_start_T_1 = bits(_dst_bits_start_WIRE_1, 13, 0) connect _dst_bits_start_WIRE.data, _dst_bits_start_T_1 node _dst_bits_start_T_2 = bits(_dst_bits_start_WIRE_1, 14, 14) connect _dst_bits_start_WIRE.garbage_bit, _dst_bits_start_T_2 node _dst_bits_start_T_3 = bits(_dst_bits_start_WIRE_1, 25, 15) connect _dst_bits_start_WIRE.garbage, _dst_bits_start_T_3 node _dst_bits_start_T_4 = bits(_dst_bits_start_WIRE_1, 28, 26) wire _dst_bits_start_WIRE_2 : UInt<3> connect _dst_bits_start_WIRE_2, _dst_bits_start_T_4 wire _dst_bits_start_WIRE_3 : UInt<3> connect _dst_bits_start_WIRE_3, _dst_bits_start_WIRE_2 connect _dst_bits_start_WIRE.norm_cmd, _dst_bits_start_WIRE_3 node _dst_bits_start_T_5 = bits(_dst_bits_start_WIRE_1, 29, 29) connect _dst_bits_start_WIRE.read_full_acc_row, _dst_bits_start_T_5 node _dst_bits_start_T_6 = bits(_dst_bits_start_WIRE_1, 30, 30) connect _dst_bits_start_WIRE.accumulate, _dst_bits_start_T_6 node _dst_bits_start_T_7 = bits(_dst_bits_start_WIRE_1, 31, 31) connect _dst_bits_start_WIRE.is_acc_addr, _dst_bits_start_T_7 connect dst.bits.start, _dst_bits_start_WIRE node _T_8 = eq(io.alloc.bits.cmd.inst.funct, UInt<3>(0h6)) when _T_8 : node _preload_rows_T = bits(io.alloc.bits.cmd.rs2, 50, 48) node preload_rows_1 = mul(_preload_rows_T, c_stride) wire dst_bits_end_result : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} connect dst_bits_end_result, dst.bits.start node _dst_bits_end_result_data_T = add(dst.bits.start.data, preload_rows_1) node _dst_bits_end_result_data_T_1 = tail(_dst_bits_end_result_data_T, 1) connect dst_bits_end_result.data, _dst_bits_end_result_data_T_1 connect dst.bits.end, dst_bits_end_result node dst_bits_wraps_around_sum = add(dst.bits.start.data, preload_rows_1) node _dst_bits_wraps_around_overflow_T = bits(dst_bits_wraps_around_sum, 12, 12) node _dst_bits_wraps_around_overflow_T_1 = bits(dst_bits_wraps_around_sum, 14, 14) node dst_bits_wraps_around_overflow = mux(dst.bits.start.is_acc_addr, _dst_bits_wraps_around_overflow_T, _dst_bits_wraps_around_overflow_T_1) wire dst_bits_wraps_around_result : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} connect dst_bits_wraps_around_result, dst.bits.start node _dst_bits_wraps_around_result_data_T = bits(dst_bits_wraps_around_sum, 13, 0) connect dst_bits_wraps_around_result.data, _dst_bits_wraps_around_result_data_T connect dst.bits.wraps_around, dst_bits_wraps_around_overflow else : node _id_T = eq(new_entry.cmd.cmd.inst.funct, UInt<1>(0h1)) node _id_T_1 = eq(new_entry.cmd.cmd.inst.funct, UInt<4>(0he)) node _id_T_2 = mux(_id_T_1, UInt<2>(0h2), UInt<1>(0h0)) node id = mux(_id_T, UInt<1>(0h1), _id_T_2) node mvin_cols = bits(io.alloc.bits.cmd.rs2, 36, 32) node mvin_rows = bits(io.alloc.bits.cmd.rs2, 50, 48) node _mvin_mats_T = div(mvin_cols, UInt<5>(0h4)) node _mvin_mats_T_1 = rem(mvin_cols, UInt<3>(0h4)) node _mvin_mats_T_2 = neq(_mvin_mats_T_1, UInt<1>(0h0)) node _mvin_mats_T_3 = add(_mvin_mats_T, _mvin_mats_T_2) node mvin_mats = tail(_mvin_mats_T_3, 1) node _total_mvin_rows_T = sub(mvin_mats, UInt<1>(0h1)) node _total_mvin_rows_T_1 = tail(_total_mvin_rows_T, 1) node _total_mvin_rows_T_2 = mul(_total_mvin_rows_T_1, ld_block_strides[id]) node _total_mvin_rows_T_3 = add(_total_mvin_rows_T_2, mvin_rows) node total_mvin_rows = tail(_total_mvin_rows_T_3, 1) node _start_T = bits(io.alloc.bits.cmd.rs2, 31, 0) wire start : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} wire _start_WIRE : UInt<32> connect _start_WIRE, _start_T node _start_T_1 = bits(_start_WIRE, 13, 0) connect start.data, _start_T_1 node _start_T_2 = bits(_start_WIRE, 14, 14) connect start.garbage_bit, _start_T_2 node _start_T_3 = bits(_start_WIRE, 25, 15) connect start.garbage, _start_T_3 node _start_T_4 = bits(_start_WIRE, 28, 26) wire _start_WIRE_1 : UInt<3> connect _start_WIRE_1, _start_T_4 wire _start_WIRE_2 : UInt<3> connect _start_WIRE_2, _start_WIRE_1 connect start.norm_cmd, _start_WIRE_2 node _start_T_5 = bits(_start_WIRE, 29, 29) connect start.read_full_acc_row, _start_T_5 node _start_T_6 = bits(_start_WIRE, 30, 30) connect start.accumulate, _start_T_6 node _start_T_7 = bits(_start_WIRE, 31, 31) connect start.is_acc_addr, _start_T_7 node _dst_bits_start_T_8 = bits(start.data, 13, 0) node _dst_bits_start_T_9 = gt(_dst_bits_start_T_8, UInt<14>(0h2000)) node _dst_bits_start_underflow_T = add(UInt<14>(0h2000), ld_pixel_repeats[id]) node dst_bits_start_underflow = lt(start.data, _dst_bits_start_underflow_T) wire dst_bits_start_result : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} connect dst_bits_start_result, start node _dst_bits_start_result_data_T = sub(start.data, ld_pixel_repeats[id]) node _dst_bits_start_result_data_T_1 = tail(_dst_bits_start_result_data_T, 1) node _dst_bits_start_result_data_T_2 = mux(dst_bits_start_underflow, UInt<14>(0h2000), _dst_bits_start_result_data_T_1) connect dst_bits_start_result.data, _dst_bits_start_result_data_T_2 node _dst_bits_start_underflow_T_1 = add(UInt<1>(0h0), ld_pixel_repeats[id]) node dst_bits_start_underflow_1 = lt(start.data, _dst_bits_start_underflow_T_1) wire dst_bits_start_result_1 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} connect dst_bits_start_result_1, start node _dst_bits_start_result_data_T_3 = sub(start.data, ld_pixel_repeats[id]) node _dst_bits_start_result_data_T_4 = tail(_dst_bits_start_result_data_T_3, 1) node _dst_bits_start_result_data_T_5 = mux(dst_bits_start_underflow_1, UInt<1>(0h0), _dst_bits_start_result_data_T_4) connect dst_bits_start_result_1.data, _dst_bits_start_result_data_T_5 node _dst_bits_start_T_10 = mux(_dst_bits_start_T_9, dst_bits_start_result, dst_bits_start_result_1) node _dst_bits_start_T_11 = mux(start.is_acc_addr, start, _dst_bits_start_T_10) connect dst.bits.start, _dst_bits_start_T_11 wire dst_bits_end_result_1 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} connect dst_bits_end_result_1, dst.bits.start node _dst_bits_end_result_data_T_2 = add(dst.bits.start.data, total_mvin_rows) node _dst_bits_end_result_data_T_3 = tail(_dst_bits_end_result_data_T_2, 1) connect dst_bits_end_result_1.data, _dst_bits_end_result_data_T_3 connect dst.bits.end, dst_bits_end_result_1 node dst_bits_wraps_around_sum_1 = add(dst.bits.start.data, total_mvin_rows) node _dst_bits_wraps_around_overflow_T_2 = bits(dst_bits_wraps_around_sum_1, 12, 12) node _dst_bits_wraps_around_overflow_T_3 = bits(dst_bits_wraps_around_sum_1, 14, 14) node dst_bits_wraps_around_overflow_1 = mux(dst.bits.start.is_acc_addr, _dst_bits_wraps_around_overflow_T_2, _dst_bits_wraps_around_overflow_T_3) wire dst_bits_wraps_around_result_1 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} connect dst_bits_wraps_around_result_1, dst.bits.start node _dst_bits_wraps_around_result_data_T_1 = bits(dst_bits_wraps_around_sum_1, 13, 0) connect dst_bits_wraps_around_result_1.data, _dst_bits_wraps_around_result_data_T_1 connect dst.bits.wraps_around, dst_bits_wraps_around_overflow_1 node _is_load_T = eq(io.alloc.bits.cmd.inst.funct, UInt<2>(0h2)) node _is_load_T_1 = eq(io.alloc.bits.cmd.inst.funct, UInt<1>(0h1)) node _is_load_T_2 = or(_is_load_T, _is_load_T_1) node _is_load_T_3 = eq(io.alloc.bits.cmd.inst.funct, UInt<4>(0he)) node _is_load_T_4 = or(_is_load_T_2, _is_load_T_3) node _is_load_T_5 = eq(io.alloc.bits.cmd.inst.funct, UInt<1>(0h0)) node _is_load_T_6 = eq(config_cmd_type, UInt<1>(0h1)) node _is_load_T_7 = and(_is_load_T_5, _is_load_T_6) node is_load = or(_is_load_T_4, _is_load_T_7) node _is_ex_T = eq(io.alloc.bits.cmd.inst.funct, UInt<3>(0h6)) node _is_ex_T_1 = or(_is_ex_T, funct_is_compute) node _is_ex_T_2 = eq(io.alloc.bits.cmd.inst.funct, UInt<1>(0h0)) node _is_ex_T_3 = eq(config_cmd_type, UInt<1>(0h0)) node _is_ex_T_4 = and(_is_ex_T_2, _is_ex_T_3) node is_ex = or(_is_ex_T_1, _is_ex_T_4) node _is_store_T = eq(io.alloc.bits.cmd.inst.funct, UInt<2>(0h3)) node _is_store_T_1 = eq(io.alloc.bits.cmd.inst.funct, UInt<1>(0h0)) node _is_store_T_2 = eq(config_cmd_type, UInt<2>(0h2)) node _is_store_T_3 = eq(config_cmd_type, UInt<2>(0h3)) node _is_store_T_4 = or(_is_store_T_2, _is_store_T_3) node _is_store_T_5 = and(_is_store_T_1, _is_store_T_4) node is_store = or(_is_store_T, _is_store_T_5) node _is_norm_T = eq(io.alloc.bits.cmd.inst.funct, UInt<1>(0h0)) node _is_norm_T_1 = eq(config_cmd_type, UInt<2>(0h3)) node is_norm = and(_is_norm_T, _is_norm_T_1) node _new_entry_q_T = mux(is_load, UInt<2>(0h0), UInt<1>(0h0)) node _new_entry_q_T_1 = mux(is_store, UInt<2>(0h2), UInt<1>(0h0)) node _new_entry_q_T_2 = mux(is_ex, UInt<2>(0h1), UInt<1>(0h0)) node _new_entry_q_T_3 = or(_new_entry_q_T, _new_entry_q_T_1) node _new_entry_q_T_4 = or(_new_entry_q_T_3, _new_entry_q_T_2) wire _new_entry_q_WIRE : UInt<2> connect _new_entry_q_WIRE, _new_entry_q_T_4 connect new_entry.q, _new_entry_q_WIRE node _T_9 = or(is_load, is_store) node _T_10 = or(_T_9, is_ex) node _T_11 = asUInt(reset) node _T_12 = eq(_T_11, UInt<1>(0h0)) when _T_12 : node _T_13 = eq(_T_10, UInt<1>(0h0)) when _T_13 : printf(clock, UInt<1>(0h1), "Assertion failed\n at ReservationStation.scala:306 assert(is_load || is_store || is_ex)\n") : printf_1 assert(clock, _T_10, UInt<1>(0h1), "") : assert_1 node _T_14 = lt(UInt<2>(0h0), UInt<2>(0h1)) node _T_15 = lt(UInt<2>(0h1), UInt<2>(0h2)) node _T_16 = and(_T_14, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at ReservationStation.scala:307 assert(ldq < exq && exq < stq)\n") : printf_2 assert(clock, _T_16, UInt<1>(0h1), "") : assert_2 node not_config = eq(new_entry.is_config, UInt<1>(0h0)) when is_load : node _T_20 = eq(entries_ld[0].bits.issued, UInt<1>(0h0)) node _T_21 = and(entries_ld[0].valid, _T_20) node _T_22 = eq(entries_ld[1].bits.issued, UInt<1>(0h0)) node _T_23 = and(entries_ld[1].valid, _T_22) node _T_24 = eq(entries_ld[2].bits.issued, UInt<1>(0h0)) node _T_25 = and(entries_ld[2].valid, _T_24) node _T_26 = eq(entries_ld[3].bits.issued, UInt<1>(0h0)) node _T_27 = and(entries_ld[3].valid, _T_26) node _T_28 = eq(entries_ld[4].bits.issued, UInt<1>(0h0)) node _T_29 = and(entries_ld[4].valid, _T_28) node _T_30 = eq(entries_ld[5].bits.issued, UInt<1>(0h0)) node _T_31 = and(entries_ld[5].valid, _T_30) node _T_32 = eq(entries_ld[6].bits.issued, UInt<1>(0h0)) node _T_33 = and(entries_ld[6].valid, _T_32) node _T_34 = eq(entries_ld[7].bits.issued, UInt<1>(0h0)) node _T_35 = and(entries_ld[7].valid, _T_34) wire _WIRE : UInt<1>[8] connect _WIRE[0], _T_21 connect _WIRE[1], _T_23 connect _WIRE[2], _T_25 connect _WIRE[3], _T_27 connect _WIRE[4], _T_29 connect _WIRE[5], _T_31 connect _WIRE[6], _T_33 connect _WIRE[7], _T_35 connect new_entry.deps_ld, _WIRE node _T_36 = eq(new_entry.is_config, UInt<1>(0h0)) node _T_37 = and(entries_ex[0].valid, _T_36) node _T_38 = eq(entries_ex[0].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_39 = bits(entries_ex[0].bits.opa.bits.start.data, 11, 0) node _T_40 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_41 = leq(_T_39, _T_40) node _T_42 = bits(entries_ex[0].bits.opa.bits.start.data, 13, 0) node _T_43 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_44 = leq(_T_42, _T_43) node _T_45 = mux(entries_ex[0].bits.opa.bits.start.is_acc_addr, _T_41, _T_44) node _T_46 = and(_T_38, _T_45) node _T_47 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[0].bits.opa.bits.end.is_acc_addr) node _T_48 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_49 = bits(entries_ex[0].bits.opa.bits.end.data, 11, 0) node _T_50 = lt(_T_48, _T_49) node _T_51 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_52 = bits(entries_ex[0].bits.opa.bits.end.data, 13, 0) node _T_53 = lt(_T_51, _T_52) node _T_54 = mux(new_entry.opa.bits.start.is_acc_addr, _T_50, _T_53) node _T_55 = and(_T_47, _T_54) node _T_56 = or(_T_55, entries_ex[0].bits.opa.bits.wraps_around) node _T_57 = and(_T_46, _T_56) node _T_58 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[0].bits.opa.bits.start.is_acc_addr) node _T_59 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_60 = bits(entries_ex[0].bits.opa.bits.start.data, 11, 0) node _T_61 = leq(_T_59, _T_60) node _T_62 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_63 = bits(entries_ex[0].bits.opa.bits.start.data, 13, 0) node _T_64 = leq(_T_62, _T_63) node _T_65 = mux(new_entry.opa.bits.start.is_acc_addr, _T_61, _T_64) node _T_66 = and(_T_58, _T_65) node _T_67 = eq(entries_ex[0].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_68 = bits(entries_ex[0].bits.opa.bits.start.data, 11, 0) node _T_69 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_70 = lt(_T_68, _T_69) node _T_71 = bits(entries_ex[0].bits.opa.bits.start.data, 13, 0) node _T_72 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_73 = lt(_T_71, _T_72) node _T_74 = mux(entries_ex[0].bits.opa.bits.start.is_acc_addr, _T_70, _T_73) node _T_75 = and(_T_67, _T_74) node _T_76 = or(_T_75, new_entry.opa.bits.wraps_around) node _T_77 = and(_T_66, _T_76) node _T_78 = or(_T_57, _T_77) node _T_79 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_80 = and(_T_79, new_entry.opa.bits.start.read_full_acc_row) node _T_81 = andr(new_entry.opa.bits.start.data) node _T_82 = and(_T_80, _T_81) node _T_83 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_84 = and(_T_82, _T_83) node _T_85 = and(entries_ex[0].bits.opa.bits.start.is_acc_addr, entries_ex[0].bits.opa.bits.start.accumulate) node _T_86 = and(_T_85, entries_ex[0].bits.opa.bits.start.read_full_acc_row) node _T_87 = andr(entries_ex[0].bits.opa.bits.start.data) node _T_88 = and(_T_86, _T_87) node _T_89 = bits(entries_ex[0].bits.opa.bits.start.garbage_bit, 0, 0) node _T_90 = and(_T_88, _T_89) node _T_91 = or(_T_84, _T_90) node _T_92 = eq(_T_91, UInt<1>(0h0)) node _T_93 = and(_T_78, _T_92) node _T_94 = and(_T_93, entries_ex[0].bits.opa.valid) node _T_95 = eq(entries_ex[0].bits.opb.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_96 = bits(entries_ex[0].bits.opb.bits.start.data, 11, 0) node _T_97 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_98 = leq(_T_96, _T_97) node _T_99 = bits(entries_ex[0].bits.opb.bits.start.data, 13, 0) node _T_100 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_101 = leq(_T_99, _T_100) node _T_102 = mux(entries_ex[0].bits.opb.bits.start.is_acc_addr, _T_98, _T_101) node _T_103 = and(_T_95, _T_102) node _T_104 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[0].bits.opb.bits.end.is_acc_addr) node _T_105 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_106 = bits(entries_ex[0].bits.opb.bits.end.data, 11, 0) node _T_107 = lt(_T_105, _T_106) node _T_108 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_109 = bits(entries_ex[0].bits.opb.bits.end.data, 13, 0) node _T_110 = lt(_T_108, _T_109) node _T_111 = mux(new_entry.opa.bits.start.is_acc_addr, _T_107, _T_110) node _T_112 = and(_T_104, _T_111) node _T_113 = or(_T_112, entries_ex[0].bits.opb.bits.wraps_around) node _T_114 = and(_T_103, _T_113) node _T_115 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[0].bits.opb.bits.start.is_acc_addr) node _T_116 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_117 = bits(entries_ex[0].bits.opb.bits.start.data, 11, 0) node _T_118 = leq(_T_116, _T_117) node _T_119 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_120 = bits(entries_ex[0].bits.opb.bits.start.data, 13, 0) node _T_121 = leq(_T_119, _T_120) node _T_122 = mux(new_entry.opa.bits.start.is_acc_addr, _T_118, _T_121) node _T_123 = and(_T_115, _T_122) node _T_124 = eq(entries_ex[0].bits.opb.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_125 = bits(entries_ex[0].bits.opb.bits.start.data, 11, 0) node _T_126 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_127 = lt(_T_125, _T_126) node _T_128 = bits(entries_ex[0].bits.opb.bits.start.data, 13, 0) node _T_129 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_130 = lt(_T_128, _T_129) node _T_131 = mux(entries_ex[0].bits.opb.bits.start.is_acc_addr, _T_127, _T_130) node _T_132 = and(_T_124, _T_131) node _T_133 = or(_T_132, new_entry.opa.bits.wraps_around) node _T_134 = and(_T_123, _T_133) node _T_135 = or(_T_114, _T_134) node _T_136 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_137 = and(_T_136, new_entry.opa.bits.start.read_full_acc_row) node _T_138 = andr(new_entry.opa.bits.start.data) node _T_139 = and(_T_137, _T_138) node _T_140 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_141 = and(_T_139, _T_140) node _T_142 = and(entries_ex[0].bits.opb.bits.start.is_acc_addr, entries_ex[0].bits.opb.bits.start.accumulate) node _T_143 = and(_T_142, entries_ex[0].bits.opb.bits.start.read_full_acc_row) node _T_144 = andr(entries_ex[0].bits.opb.bits.start.data) node _T_145 = and(_T_143, _T_144) node _T_146 = bits(entries_ex[0].bits.opb.bits.start.garbage_bit, 0, 0) node _T_147 = and(_T_145, _T_146) node _T_148 = or(_T_141, _T_147) node _T_149 = eq(_T_148, UInt<1>(0h0)) node _T_150 = and(_T_135, _T_149) node _T_151 = and(_T_150, entries_ex[0].bits.opb.valid) node _T_152 = or(_T_94, _T_151) node _T_153 = and(_T_37, _T_152) node _T_154 = eq(new_entry.is_config, UInt<1>(0h0)) node _T_155 = and(entries_ex[1].valid, _T_154) node _T_156 = eq(entries_ex[1].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_157 = bits(entries_ex[1].bits.opa.bits.start.data, 11, 0) node _T_158 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_159 = leq(_T_157, _T_158) node _T_160 = bits(entries_ex[1].bits.opa.bits.start.data, 13, 0) node _T_161 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_162 = leq(_T_160, _T_161) node _T_163 = mux(entries_ex[1].bits.opa.bits.start.is_acc_addr, _T_159, _T_162) node _T_164 = and(_T_156, _T_163) node _T_165 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[1].bits.opa.bits.end.is_acc_addr) node _T_166 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_167 = bits(entries_ex[1].bits.opa.bits.end.data, 11, 0) node _T_168 = lt(_T_166, _T_167) node _T_169 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_170 = bits(entries_ex[1].bits.opa.bits.end.data, 13, 0) node _T_171 = lt(_T_169, _T_170) node _T_172 = mux(new_entry.opa.bits.start.is_acc_addr, _T_168, _T_171) node _T_173 = and(_T_165, _T_172) node _T_174 = or(_T_173, entries_ex[1].bits.opa.bits.wraps_around) node _T_175 = and(_T_164, _T_174) node _T_176 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[1].bits.opa.bits.start.is_acc_addr) node _T_177 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_178 = bits(entries_ex[1].bits.opa.bits.start.data, 11, 0) node _T_179 = leq(_T_177, _T_178) node _T_180 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_181 = bits(entries_ex[1].bits.opa.bits.start.data, 13, 0) node _T_182 = leq(_T_180, _T_181) node _T_183 = mux(new_entry.opa.bits.start.is_acc_addr, _T_179, _T_182) node _T_184 = and(_T_176, _T_183) node _T_185 = eq(entries_ex[1].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_186 = bits(entries_ex[1].bits.opa.bits.start.data, 11, 0) node _T_187 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_188 = lt(_T_186, _T_187) node _T_189 = bits(entries_ex[1].bits.opa.bits.start.data, 13, 0) node _T_190 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_191 = lt(_T_189, _T_190) node _T_192 = mux(entries_ex[1].bits.opa.bits.start.is_acc_addr, _T_188, _T_191) node _T_193 = and(_T_185, _T_192) node _T_194 = or(_T_193, new_entry.opa.bits.wraps_around) node _T_195 = and(_T_184, _T_194) node _T_196 = or(_T_175, _T_195) node _T_197 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_198 = and(_T_197, new_entry.opa.bits.start.read_full_acc_row) node _T_199 = andr(new_entry.opa.bits.start.data) node _T_200 = and(_T_198, _T_199) node _T_201 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_202 = and(_T_200, _T_201) node _T_203 = and(entries_ex[1].bits.opa.bits.start.is_acc_addr, entries_ex[1].bits.opa.bits.start.accumulate) node _T_204 = and(_T_203, entries_ex[1].bits.opa.bits.start.read_full_acc_row) node _T_205 = andr(entries_ex[1].bits.opa.bits.start.data) node _T_206 = and(_T_204, _T_205) node _T_207 = bits(entries_ex[1].bits.opa.bits.start.garbage_bit, 0, 0) node _T_208 = and(_T_206, _T_207) node _T_209 = or(_T_202, _T_208) node _T_210 = eq(_T_209, UInt<1>(0h0)) node _T_211 = and(_T_196, _T_210) node _T_212 = and(_T_211, entries_ex[1].bits.opa.valid) node _T_213 = eq(entries_ex[1].bits.opb.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_214 = bits(entries_ex[1].bits.opb.bits.start.data, 11, 0) node _T_215 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_216 = leq(_T_214, _T_215) node _T_217 = bits(entries_ex[1].bits.opb.bits.start.data, 13, 0) node _T_218 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_219 = leq(_T_217, _T_218) node _T_220 = mux(entries_ex[1].bits.opb.bits.start.is_acc_addr, _T_216, _T_219) node _T_221 = and(_T_213, _T_220) node _T_222 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[1].bits.opb.bits.end.is_acc_addr) node _T_223 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_224 = bits(entries_ex[1].bits.opb.bits.end.data, 11, 0) node _T_225 = lt(_T_223, _T_224) node _T_226 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_227 = bits(entries_ex[1].bits.opb.bits.end.data, 13, 0) node _T_228 = lt(_T_226, _T_227) node _T_229 = mux(new_entry.opa.bits.start.is_acc_addr, _T_225, _T_228) node _T_230 = and(_T_222, _T_229) node _T_231 = or(_T_230, entries_ex[1].bits.opb.bits.wraps_around) node _T_232 = and(_T_221, _T_231) node _T_233 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[1].bits.opb.bits.start.is_acc_addr) node _T_234 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_235 = bits(entries_ex[1].bits.opb.bits.start.data, 11, 0) node _T_236 = leq(_T_234, _T_235) node _T_237 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_238 = bits(entries_ex[1].bits.opb.bits.start.data, 13, 0) node _T_239 = leq(_T_237, _T_238) node _T_240 = mux(new_entry.opa.bits.start.is_acc_addr, _T_236, _T_239) node _T_241 = and(_T_233, _T_240) node _T_242 = eq(entries_ex[1].bits.opb.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_243 = bits(entries_ex[1].bits.opb.bits.start.data, 11, 0) node _T_244 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_245 = lt(_T_243, _T_244) node _T_246 = bits(entries_ex[1].bits.opb.bits.start.data, 13, 0) node _T_247 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_248 = lt(_T_246, _T_247) node _T_249 = mux(entries_ex[1].bits.opb.bits.start.is_acc_addr, _T_245, _T_248) node _T_250 = and(_T_242, _T_249) node _T_251 = or(_T_250, new_entry.opa.bits.wraps_around) node _T_252 = and(_T_241, _T_251) node _T_253 = or(_T_232, _T_252) node _T_254 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_255 = and(_T_254, new_entry.opa.bits.start.read_full_acc_row) node _T_256 = andr(new_entry.opa.bits.start.data) node _T_257 = and(_T_255, _T_256) node _T_258 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_259 = and(_T_257, _T_258) node _T_260 = and(entries_ex[1].bits.opb.bits.start.is_acc_addr, entries_ex[1].bits.opb.bits.start.accumulate) node _T_261 = and(_T_260, entries_ex[1].bits.opb.bits.start.read_full_acc_row) node _T_262 = andr(entries_ex[1].bits.opb.bits.start.data) node _T_263 = and(_T_261, _T_262) node _T_264 = bits(entries_ex[1].bits.opb.bits.start.garbage_bit, 0, 0) node _T_265 = and(_T_263, _T_264) node _T_266 = or(_T_259, _T_265) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = and(_T_253, _T_267) node _T_269 = and(_T_268, entries_ex[1].bits.opb.valid) node _T_270 = or(_T_212, _T_269) node _T_271 = and(_T_155, _T_270) node _T_272 = eq(new_entry.is_config, UInt<1>(0h0)) node _T_273 = and(entries_ex[2].valid, _T_272) node _T_274 = eq(entries_ex[2].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_275 = bits(entries_ex[2].bits.opa.bits.start.data, 11, 0) node _T_276 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_277 = leq(_T_275, _T_276) node _T_278 = bits(entries_ex[2].bits.opa.bits.start.data, 13, 0) node _T_279 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_280 = leq(_T_278, _T_279) node _T_281 = mux(entries_ex[2].bits.opa.bits.start.is_acc_addr, _T_277, _T_280) node _T_282 = and(_T_274, _T_281) node _T_283 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[2].bits.opa.bits.end.is_acc_addr) node _T_284 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_285 = bits(entries_ex[2].bits.opa.bits.end.data, 11, 0) node _T_286 = lt(_T_284, _T_285) node _T_287 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_288 = bits(entries_ex[2].bits.opa.bits.end.data, 13, 0) node _T_289 = lt(_T_287, _T_288) node _T_290 = mux(new_entry.opa.bits.start.is_acc_addr, _T_286, _T_289) node _T_291 = and(_T_283, _T_290) node _T_292 = or(_T_291, entries_ex[2].bits.opa.bits.wraps_around) node _T_293 = and(_T_282, _T_292) node _T_294 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[2].bits.opa.bits.start.is_acc_addr) node _T_295 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_296 = bits(entries_ex[2].bits.opa.bits.start.data, 11, 0) node _T_297 = leq(_T_295, _T_296) node _T_298 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_299 = bits(entries_ex[2].bits.opa.bits.start.data, 13, 0) node _T_300 = leq(_T_298, _T_299) node _T_301 = mux(new_entry.opa.bits.start.is_acc_addr, _T_297, _T_300) node _T_302 = and(_T_294, _T_301) node _T_303 = eq(entries_ex[2].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_304 = bits(entries_ex[2].bits.opa.bits.start.data, 11, 0) node _T_305 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_306 = lt(_T_304, _T_305) node _T_307 = bits(entries_ex[2].bits.opa.bits.start.data, 13, 0) node _T_308 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_309 = lt(_T_307, _T_308) node _T_310 = mux(entries_ex[2].bits.opa.bits.start.is_acc_addr, _T_306, _T_309) node _T_311 = and(_T_303, _T_310) node _T_312 = or(_T_311, new_entry.opa.bits.wraps_around) node _T_313 = and(_T_302, _T_312) node _T_314 = or(_T_293, _T_313) node _T_315 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_316 = and(_T_315, new_entry.opa.bits.start.read_full_acc_row) node _T_317 = andr(new_entry.opa.bits.start.data) node _T_318 = and(_T_316, _T_317) node _T_319 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_320 = and(_T_318, _T_319) node _T_321 = and(entries_ex[2].bits.opa.bits.start.is_acc_addr, entries_ex[2].bits.opa.bits.start.accumulate) node _T_322 = and(_T_321, entries_ex[2].bits.opa.bits.start.read_full_acc_row) node _T_323 = andr(entries_ex[2].bits.opa.bits.start.data) node _T_324 = and(_T_322, _T_323) node _T_325 = bits(entries_ex[2].bits.opa.bits.start.garbage_bit, 0, 0) node _T_326 = and(_T_324, _T_325) node _T_327 = or(_T_320, _T_326) node _T_328 = eq(_T_327, UInt<1>(0h0)) node _T_329 = and(_T_314, _T_328) node _T_330 = and(_T_329, entries_ex[2].bits.opa.valid) node _T_331 = eq(entries_ex[2].bits.opb.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_332 = bits(entries_ex[2].bits.opb.bits.start.data, 11, 0) node _T_333 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_334 = leq(_T_332, _T_333) node _T_335 = bits(entries_ex[2].bits.opb.bits.start.data, 13, 0) node _T_336 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_337 = leq(_T_335, _T_336) node _T_338 = mux(entries_ex[2].bits.opb.bits.start.is_acc_addr, _T_334, _T_337) node _T_339 = and(_T_331, _T_338) node _T_340 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[2].bits.opb.bits.end.is_acc_addr) node _T_341 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_342 = bits(entries_ex[2].bits.opb.bits.end.data, 11, 0) node _T_343 = lt(_T_341, _T_342) node _T_344 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_345 = bits(entries_ex[2].bits.opb.bits.end.data, 13, 0) node _T_346 = lt(_T_344, _T_345) node _T_347 = mux(new_entry.opa.bits.start.is_acc_addr, _T_343, _T_346) node _T_348 = and(_T_340, _T_347) node _T_349 = or(_T_348, entries_ex[2].bits.opb.bits.wraps_around) node _T_350 = and(_T_339, _T_349) node _T_351 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[2].bits.opb.bits.start.is_acc_addr) node _T_352 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_353 = bits(entries_ex[2].bits.opb.bits.start.data, 11, 0) node _T_354 = leq(_T_352, _T_353) node _T_355 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_356 = bits(entries_ex[2].bits.opb.bits.start.data, 13, 0) node _T_357 = leq(_T_355, _T_356) node _T_358 = mux(new_entry.opa.bits.start.is_acc_addr, _T_354, _T_357) node _T_359 = and(_T_351, _T_358) node _T_360 = eq(entries_ex[2].bits.opb.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_361 = bits(entries_ex[2].bits.opb.bits.start.data, 11, 0) node _T_362 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_363 = lt(_T_361, _T_362) node _T_364 = bits(entries_ex[2].bits.opb.bits.start.data, 13, 0) node _T_365 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_366 = lt(_T_364, _T_365) node _T_367 = mux(entries_ex[2].bits.opb.bits.start.is_acc_addr, _T_363, _T_366) node _T_368 = and(_T_360, _T_367) node _T_369 = or(_T_368, new_entry.opa.bits.wraps_around) node _T_370 = and(_T_359, _T_369) node _T_371 = or(_T_350, _T_370) node _T_372 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_373 = and(_T_372, new_entry.opa.bits.start.read_full_acc_row) node _T_374 = andr(new_entry.opa.bits.start.data) node _T_375 = and(_T_373, _T_374) node _T_376 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_377 = and(_T_375, _T_376) node _T_378 = and(entries_ex[2].bits.opb.bits.start.is_acc_addr, entries_ex[2].bits.opb.bits.start.accumulate) node _T_379 = and(_T_378, entries_ex[2].bits.opb.bits.start.read_full_acc_row) node _T_380 = andr(entries_ex[2].bits.opb.bits.start.data) node _T_381 = and(_T_379, _T_380) node _T_382 = bits(entries_ex[2].bits.opb.bits.start.garbage_bit, 0, 0) node _T_383 = and(_T_381, _T_382) node _T_384 = or(_T_377, _T_383) node _T_385 = eq(_T_384, UInt<1>(0h0)) node _T_386 = and(_T_371, _T_385) node _T_387 = and(_T_386, entries_ex[2].bits.opb.valid) node _T_388 = or(_T_330, _T_387) node _T_389 = and(_T_273, _T_388) node _T_390 = eq(new_entry.is_config, UInt<1>(0h0)) node _T_391 = and(entries_ex[3].valid, _T_390) node _T_392 = eq(entries_ex[3].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_393 = bits(entries_ex[3].bits.opa.bits.start.data, 11, 0) node _T_394 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_395 = leq(_T_393, _T_394) node _T_396 = bits(entries_ex[3].bits.opa.bits.start.data, 13, 0) node _T_397 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_398 = leq(_T_396, _T_397) node _T_399 = mux(entries_ex[3].bits.opa.bits.start.is_acc_addr, _T_395, _T_398) node _T_400 = and(_T_392, _T_399) node _T_401 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[3].bits.opa.bits.end.is_acc_addr) node _T_402 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_403 = bits(entries_ex[3].bits.opa.bits.end.data, 11, 0) node _T_404 = lt(_T_402, _T_403) node _T_405 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_406 = bits(entries_ex[3].bits.opa.bits.end.data, 13, 0) node _T_407 = lt(_T_405, _T_406) node _T_408 = mux(new_entry.opa.bits.start.is_acc_addr, _T_404, _T_407) node _T_409 = and(_T_401, _T_408) node _T_410 = or(_T_409, entries_ex[3].bits.opa.bits.wraps_around) node _T_411 = and(_T_400, _T_410) node _T_412 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[3].bits.opa.bits.start.is_acc_addr) node _T_413 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_414 = bits(entries_ex[3].bits.opa.bits.start.data, 11, 0) node _T_415 = leq(_T_413, _T_414) node _T_416 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_417 = bits(entries_ex[3].bits.opa.bits.start.data, 13, 0) node _T_418 = leq(_T_416, _T_417) node _T_419 = mux(new_entry.opa.bits.start.is_acc_addr, _T_415, _T_418) node _T_420 = and(_T_412, _T_419) node _T_421 = eq(entries_ex[3].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_422 = bits(entries_ex[3].bits.opa.bits.start.data, 11, 0) node _T_423 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_424 = lt(_T_422, _T_423) node _T_425 = bits(entries_ex[3].bits.opa.bits.start.data, 13, 0) node _T_426 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_427 = lt(_T_425, _T_426) node _T_428 = mux(entries_ex[3].bits.opa.bits.start.is_acc_addr, _T_424, _T_427) node _T_429 = and(_T_421, _T_428) node _T_430 = or(_T_429, new_entry.opa.bits.wraps_around) node _T_431 = and(_T_420, _T_430) node _T_432 = or(_T_411, _T_431) node _T_433 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_434 = and(_T_433, new_entry.opa.bits.start.read_full_acc_row) node _T_435 = andr(new_entry.opa.bits.start.data) node _T_436 = and(_T_434, _T_435) node _T_437 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_438 = and(_T_436, _T_437) node _T_439 = and(entries_ex[3].bits.opa.bits.start.is_acc_addr, entries_ex[3].bits.opa.bits.start.accumulate) node _T_440 = and(_T_439, entries_ex[3].bits.opa.bits.start.read_full_acc_row) node _T_441 = andr(entries_ex[3].bits.opa.bits.start.data) node _T_442 = and(_T_440, _T_441) node _T_443 = bits(entries_ex[3].bits.opa.bits.start.garbage_bit, 0, 0) node _T_444 = and(_T_442, _T_443) node _T_445 = or(_T_438, _T_444) node _T_446 = eq(_T_445, UInt<1>(0h0)) node _T_447 = and(_T_432, _T_446) node _T_448 = and(_T_447, entries_ex[3].bits.opa.valid) node _T_449 = eq(entries_ex[3].bits.opb.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_450 = bits(entries_ex[3].bits.opb.bits.start.data, 11, 0) node _T_451 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_452 = leq(_T_450, _T_451) node _T_453 = bits(entries_ex[3].bits.opb.bits.start.data, 13, 0) node _T_454 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_455 = leq(_T_453, _T_454) node _T_456 = mux(entries_ex[3].bits.opb.bits.start.is_acc_addr, _T_452, _T_455) node _T_457 = and(_T_449, _T_456) node _T_458 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[3].bits.opb.bits.end.is_acc_addr) node _T_459 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_460 = bits(entries_ex[3].bits.opb.bits.end.data, 11, 0) node _T_461 = lt(_T_459, _T_460) node _T_462 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_463 = bits(entries_ex[3].bits.opb.bits.end.data, 13, 0) node _T_464 = lt(_T_462, _T_463) node _T_465 = mux(new_entry.opa.bits.start.is_acc_addr, _T_461, _T_464) node _T_466 = and(_T_458, _T_465) node _T_467 = or(_T_466, entries_ex[3].bits.opb.bits.wraps_around) node _T_468 = and(_T_457, _T_467) node _T_469 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[3].bits.opb.bits.start.is_acc_addr) node _T_470 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_471 = bits(entries_ex[3].bits.opb.bits.start.data, 11, 0) node _T_472 = leq(_T_470, _T_471) node _T_473 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_474 = bits(entries_ex[3].bits.opb.bits.start.data, 13, 0) node _T_475 = leq(_T_473, _T_474) node _T_476 = mux(new_entry.opa.bits.start.is_acc_addr, _T_472, _T_475) node _T_477 = and(_T_469, _T_476) node _T_478 = eq(entries_ex[3].bits.opb.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_479 = bits(entries_ex[3].bits.opb.bits.start.data, 11, 0) node _T_480 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_481 = lt(_T_479, _T_480) node _T_482 = bits(entries_ex[3].bits.opb.bits.start.data, 13, 0) node _T_483 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_484 = lt(_T_482, _T_483) node _T_485 = mux(entries_ex[3].bits.opb.bits.start.is_acc_addr, _T_481, _T_484) node _T_486 = and(_T_478, _T_485) node _T_487 = or(_T_486, new_entry.opa.bits.wraps_around) node _T_488 = and(_T_477, _T_487) node _T_489 = or(_T_468, _T_488) node _T_490 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_491 = and(_T_490, new_entry.opa.bits.start.read_full_acc_row) node _T_492 = andr(new_entry.opa.bits.start.data) node _T_493 = and(_T_491, _T_492) node _T_494 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_495 = and(_T_493, _T_494) node _T_496 = and(entries_ex[3].bits.opb.bits.start.is_acc_addr, entries_ex[3].bits.opb.bits.start.accumulate) node _T_497 = and(_T_496, entries_ex[3].bits.opb.bits.start.read_full_acc_row) node _T_498 = andr(entries_ex[3].bits.opb.bits.start.data) node _T_499 = and(_T_497, _T_498) node _T_500 = bits(entries_ex[3].bits.opb.bits.start.garbage_bit, 0, 0) node _T_501 = and(_T_499, _T_500) node _T_502 = or(_T_495, _T_501) node _T_503 = eq(_T_502, UInt<1>(0h0)) node _T_504 = and(_T_489, _T_503) node _T_505 = and(_T_504, entries_ex[3].bits.opb.valid) node _T_506 = or(_T_448, _T_505) node _T_507 = and(_T_391, _T_506) node _T_508 = eq(new_entry.is_config, UInt<1>(0h0)) node _T_509 = and(entries_ex[4].valid, _T_508) node _T_510 = eq(entries_ex[4].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_511 = bits(entries_ex[4].bits.opa.bits.start.data, 11, 0) node _T_512 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_513 = leq(_T_511, _T_512) node _T_514 = bits(entries_ex[4].bits.opa.bits.start.data, 13, 0) node _T_515 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_516 = leq(_T_514, _T_515) node _T_517 = mux(entries_ex[4].bits.opa.bits.start.is_acc_addr, _T_513, _T_516) node _T_518 = and(_T_510, _T_517) node _T_519 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[4].bits.opa.bits.end.is_acc_addr) node _T_520 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_521 = bits(entries_ex[4].bits.opa.bits.end.data, 11, 0) node _T_522 = lt(_T_520, _T_521) node _T_523 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_524 = bits(entries_ex[4].bits.opa.bits.end.data, 13, 0) node _T_525 = lt(_T_523, _T_524) node _T_526 = mux(new_entry.opa.bits.start.is_acc_addr, _T_522, _T_525) node _T_527 = and(_T_519, _T_526) node _T_528 = or(_T_527, entries_ex[4].bits.opa.bits.wraps_around) node _T_529 = and(_T_518, _T_528) node _T_530 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[4].bits.opa.bits.start.is_acc_addr) node _T_531 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_532 = bits(entries_ex[4].bits.opa.bits.start.data, 11, 0) node _T_533 = leq(_T_531, _T_532) node _T_534 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_535 = bits(entries_ex[4].bits.opa.bits.start.data, 13, 0) node _T_536 = leq(_T_534, _T_535) node _T_537 = mux(new_entry.opa.bits.start.is_acc_addr, _T_533, _T_536) node _T_538 = and(_T_530, _T_537) node _T_539 = eq(entries_ex[4].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_540 = bits(entries_ex[4].bits.opa.bits.start.data, 11, 0) node _T_541 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_542 = lt(_T_540, _T_541) node _T_543 = bits(entries_ex[4].bits.opa.bits.start.data, 13, 0) node _T_544 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_545 = lt(_T_543, _T_544) node _T_546 = mux(entries_ex[4].bits.opa.bits.start.is_acc_addr, _T_542, _T_545) node _T_547 = and(_T_539, _T_546) node _T_548 = or(_T_547, new_entry.opa.bits.wraps_around) node _T_549 = and(_T_538, _T_548) node _T_550 = or(_T_529, _T_549) node _T_551 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_552 = and(_T_551, new_entry.opa.bits.start.read_full_acc_row) node _T_553 = andr(new_entry.opa.bits.start.data) node _T_554 = and(_T_552, _T_553) node _T_555 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_556 = and(_T_554, _T_555) node _T_557 = and(entries_ex[4].bits.opa.bits.start.is_acc_addr, entries_ex[4].bits.opa.bits.start.accumulate) node _T_558 = and(_T_557, entries_ex[4].bits.opa.bits.start.read_full_acc_row) node _T_559 = andr(entries_ex[4].bits.opa.bits.start.data) node _T_560 = and(_T_558, _T_559) node _T_561 = bits(entries_ex[4].bits.opa.bits.start.garbage_bit, 0, 0) node _T_562 = and(_T_560, _T_561) node _T_563 = or(_T_556, _T_562) node _T_564 = eq(_T_563, UInt<1>(0h0)) node _T_565 = and(_T_550, _T_564) node _T_566 = and(_T_565, entries_ex[4].bits.opa.valid) node _T_567 = eq(entries_ex[4].bits.opb.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_568 = bits(entries_ex[4].bits.opb.bits.start.data, 11, 0) node _T_569 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_570 = leq(_T_568, _T_569) node _T_571 = bits(entries_ex[4].bits.opb.bits.start.data, 13, 0) node _T_572 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_573 = leq(_T_571, _T_572) node _T_574 = mux(entries_ex[4].bits.opb.bits.start.is_acc_addr, _T_570, _T_573) node _T_575 = and(_T_567, _T_574) node _T_576 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[4].bits.opb.bits.end.is_acc_addr) node _T_577 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_578 = bits(entries_ex[4].bits.opb.bits.end.data, 11, 0) node _T_579 = lt(_T_577, _T_578) node _T_580 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_581 = bits(entries_ex[4].bits.opb.bits.end.data, 13, 0) node _T_582 = lt(_T_580, _T_581) node _T_583 = mux(new_entry.opa.bits.start.is_acc_addr, _T_579, _T_582) node _T_584 = and(_T_576, _T_583) node _T_585 = or(_T_584, entries_ex[4].bits.opb.bits.wraps_around) node _T_586 = and(_T_575, _T_585) node _T_587 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[4].bits.opb.bits.start.is_acc_addr) node _T_588 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_589 = bits(entries_ex[4].bits.opb.bits.start.data, 11, 0) node _T_590 = leq(_T_588, _T_589) node _T_591 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_592 = bits(entries_ex[4].bits.opb.bits.start.data, 13, 0) node _T_593 = leq(_T_591, _T_592) node _T_594 = mux(new_entry.opa.bits.start.is_acc_addr, _T_590, _T_593) node _T_595 = and(_T_587, _T_594) node _T_596 = eq(entries_ex[4].bits.opb.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_597 = bits(entries_ex[4].bits.opb.bits.start.data, 11, 0) node _T_598 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_599 = lt(_T_597, _T_598) node _T_600 = bits(entries_ex[4].bits.opb.bits.start.data, 13, 0) node _T_601 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_602 = lt(_T_600, _T_601) node _T_603 = mux(entries_ex[4].bits.opb.bits.start.is_acc_addr, _T_599, _T_602) node _T_604 = and(_T_596, _T_603) node _T_605 = or(_T_604, new_entry.opa.bits.wraps_around) node _T_606 = and(_T_595, _T_605) node _T_607 = or(_T_586, _T_606) node _T_608 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_609 = and(_T_608, new_entry.opa.bits.start.read_full_acc_row) node _T_610 = andr(new_entry.opa.bits.start.data) node _T_611 = and(_T_609, _T_610) node _T_612 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_613 = and(_T_611, _T_612) node _T_614 = and(entries_ex[4].bits.opb.bits.start.is_acc_addr, entries_ex[4].bits.opb.bits.start.accumulate) node _T_615 = and(_T_614, entries_ex[4].bits.opb.bits.start.read_full_acc_row) node _T_616 = andr(entries_ex[4].bits.opb.bits.start.data) node _T_617 = and(_T_615, _T_616) node _T_618 = bits(entries_ex[4].bits.opb.bits.start.garbage_bit, 0, 0) node _T_619 = and(_T_617, _T_618) node _T_620 = or(_T_613, _T_619) node _T_621 = eq(_T_620, UInt<1>(0h0)) node _T_622 = and(_T_607, _T_621) node _T_623 = and(_T_622, entries_ex[4].bits.opb.valid) node _T_624 = or(_T_566, _T_623) node _T_625 = and(_T_509, _T_624) node _T_626 = eq(new_entry.is_config, UInt<1>(0h0)) node _T_627 = and(entries_ex[5].valid, _T_626) node _T_628 = eq(entries_ex[5].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_629 = bits(entries_ex[5].bits.opa.bits.start.data, 11, 0) node _T_630 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_631 = leq(_T_629, _T_630) node _T_632 = bits(entries_ex[5].bits.opa.bits.start.data, 13, 0) node _T_633 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_634 = leq(_T_632, _T_633) node _T_635 = mux(entries_ex[5].bits.opa.bits.start.is_acc_addr, _T_631, _T_634) node _T_636 = and(_T_628, _T_635) node _T_637 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[5].bits.opa.bits.end.is_acc_addr) node _T_638 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_639 = bits(entries_ex[5].bits.opa.bits.end.data, 11, 0) node _T_640 = lt(_T_638, _T_639) node _T_641 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_642 = bits(entries_ex[5].bits.opa.bits.end.data, 13, 0) node _T_643 = lt(_T_641, _T_642) node _T_644 = mux(new_entry.opa.bits.start.is_acc_addr, _T_640, _T_643) node _T_645 = and(_T_637, _T_644) node _T_646 = or(_T_645, entries_ex[5].bits.opa.bits.wraps_around) node _T_647 = and(_T_636, _T_646) node _T_648 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[5].bits.opa.bits.start.is_acc_addr) node _T_649 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_650 = bits(entries_ex[5].bits.opa.bits.start.data, 11, 0) node _T_651 = leq(_T_649, _T_650) node _T_652 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_653 = bits(entries_ex[5].bits.opa.bits.start.data, 13, 0) node _T_654 = leq(_T_652, _T_653) node _T_655 = mux(new_entry.opa.bits.start.is_acc_addr, _T_651, _T_654) node _T_656 = and(_T_648, _T_655) node _T_657 = eq(entries_ex[5].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_658 = bits(entries_ex[5].bits.opa.bits.start.data, 11, 0) node _T_659 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_660 = lt(_T_658, _T_659) node _T_661 = bits(entries_ex[5].bits.opa.bits.start.data, 13, 0) node _T_662 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_663 = lt(_T_661, _T_662) node _T_664 = mux(entries_ex[5].bits.opa.bits.start.is_acc_addr, _T_660, _T_663) node _T_665 = and(_T_657, _T_664) node _T_666 = or(_T_665, new_entry.opa.bits.wraps_around) node _T_667 = and(_T_656, _T_666) node _T_668 = or(_T_647, _T_667) node _T_669 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_670 = and(_T_669, new_entry.opa.bits.start.read_full_acc_row) node _T_671 = andr(new_entry.opa.bits.start.data) node _T_672 = and(_T_670, _T_671) node _T_673 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_674 = and(_T_672, _T_673) node _T_675 = and(entries_ex[5].bits.opa.bits.start.is_acc_addr, entries_ex[5].bits.opa.bits.start.accumulate) node _T_676 = and(_T_675, entries_ex[5].bits.opa.bits.start.read_full_acc_row) node _T_677 = andr(entries_ex[5].bits.opa.bits.start.data) node _T_678 = and(_T_676, _T_677) node _T_679 = bits(entries_ex[5].bits.opa.bits.start.garbage_bit, 0, 0) node _T_680 = and(_T_678, _T_679) node _T_681 = or(_T_674, _T_680) node _T_682 = eq(_T_681, UInt<1>(0h0)) node _T_683 = and(_T_668, _T_682) node _T_684 = and(_T_683, entries_ex[5].bits.opa.valid) node _T_685 = eq(entries_ex[5].bits.opb.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_686 = bits(entries_ex[5].bits.opb.bits.start.data, 11, 0) node _T_687 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_688 = leq(_T_686, _T_687) node _T_689 = bits(entries_ex[5].bits.opb.bits.start.data, 13, 0) node _T_690 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_691 = leq(_T_689, _T_690) node _T_692 = mux(entries_ex[5].bits.opb.bits.start.is_acc_addr, _T_688, _T_691) node _T_693 = and(_T_685, _T_692) node _T_694 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[5].bits.opb.bits.end.is_acc_addr) node _T_695 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_696 = bits(entries_ex[5].bits.opb.bits.end.data, 11, 0) node _T_697 = lt(_T_695, _T_696) node _T_698 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_699 = bits(entries_ex[5].bits.opb.bits.end.data, 13, 0) node _T_700 = lt(_T_698, _T_699) node _T_701 = mux(new_entry.opa.bits.start.is_acc_addr, _T_697, _T_700) node _T_702 = and(_T_694, _T_701) node _T_703 = or(_T_702, entries_ex[5].bits.opb.bits.wraps_around) node _T_704 = and(_T_693, _T_703) node _T_705 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[5].bits.opb.bits.start.is_acc_addr) node _T_706 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_707 = bits(entries_ex[5].bits.opb.bits.start.data, 11, 0) node _T_708 = leq(_T_706, _T_707) node _T_709 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_710 = bits(entries_ex[5].bits.opb.bits.start.data, 13, 0) node _T_711 = leq(_T_709, _T_710) node _T_712 = mux(new_entry.opa.bits.start.is_acc_addr, _T_708, _T_711) node _T_713 = and(_T_705, _T_712) node _T_714 = eq(entries_ex[5].bits.opb.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_715 = bits(entries_ex[5].bits.opb.bits.start.data, 11, 0) node _T_716 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_717 = lt(_T_715, _T_716) node _T_718 = bits(entries_ex[5].bits.opb.bits.start.data, 13, 0) node _T_719 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_720 = lt(_T_718, _T_719) node _T_721 = mux(entries_ex[5].bits.opb.bits.start.is_acc_addr, _T_717, _T_720) node _T_722 = and(_T_714, _T_721) node _T_723 = or(_T_722, new_entry.opa.bits.wraps_around) node _T_724 = and(_T_713, _T_723) node _T_725 = or(_T_704, _T_724) node _T_726 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_727 = and(_T_726, new_entry.opa.bits.start.read_full_acc_row) node _T_728 = andr(new_entry.opa.bits.start.data) node _T_729 = and(_T_727, _T_728) node _T_730 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_731 = and(_T_729, _T_730) node _T_732 = and(entries_ex[5].bits.opb.bits.start.is_acc_addr, entries_ex[5].bits.opb.bits.start.accumulate) node _T_733 = and(_T_732, entries_ex[5].bits.opb.bits.start.read_full_acc_row) node _T_734 = andr(entries_ex[5].bits.opb.bits.start.data) node _T_735 = and(_T_733, _T_734) node _T_736 = bits(entries_ex[5].bits.opb.bits.start.garbage_bit, 0, 0) node _T_737 = and(_T_735, _T_736) node _T_738 = or(_T_731, _T_737) node _T_739 = eq(_T_738, UInt<1>(0h0)) node _T_740 = and(_T_725, _T_739) node _T_741 = and(_T_740, entries_ex[5].bits.opb.valid) node _T_742 = or(_T_684, _T_741) node _T_743 = and(_T_627, _T_742) node _T_744 = eq(new_entry.is_config, UInt<1>(0h0)) node _T_745 = and(entries_ex[6].valid, _T_744) node _T_746 = eq(entries_ex[6].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_747 = bits(entries_ex[6].bits.opa.bits.start.data, 11, 0) node _T_748 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_749 = leq(_T_747, _T_748) node _T_750 = bits(entries_ex[6].bits.opa.bits.start.data, 13, 0) node _T_751 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_752 = leq(_T_750, _T_751) node _T_753 = mux(entries_ex[6].bits.opa.bits.start.is_acc_addr, _T_749, _T_752) node _T_754 = and(_T_746, _T_753) node _T_755 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[6].bits.opa.bits.end.is_acc_addr) node _T_756 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_757 = bits(entries_ex[6].bits.opa.bits.end.data, 11, 0) node _T_758 = lt(_T_756, _T_757) node _T_759 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_760 = bits(entries_ex[6].bits.opa.bits.end.data, 13, 0) node _T_761 = lt(_T_759, _T_760) node _T_762 = mux(new_entry.opa.bits.start.is_acc_addr, _T_758, _T_761) node _T_763 = and(_T_755, _T_762) node _T_764 = or(_T_763, entries_ex[6].bits.opa.bits.wraps_around) node _T_765 = and(_T_754, _T_764) node _T_766 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[6].bits.opa.bits.start.is_acc_addr) node _T_767 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_768 = bits(entries_ex[6].bits.opa.bits.start.data, 11, 0) node _T_769 = leq(_T_767, _T_768) node _T_770 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_771 = bits(entries_ex[6].bits.opa.bits.start.data, 13, 0) node _T_772 = leq(_T_770, _T_771) node _T_773 = mux(new_entry.opa.bits.start.is_acc_addr, _T_769, _T_772) node _T_774 = and(_T_766, _T_773) node _T_775 = eq(entries_ex[6].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_776 = bits(entries_ex[6].bits.opa.bits.start.data, 11, 0) node _T_777 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_778 = lt(_T_776, _T_777) node _T_779 = bits(entries_ex[6].bits.opa.bits.start.data, 13, 0) node _T_780 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_781 = lt(_T_779, _T_780) node _T_782 = mux(entries_ex[6].bits.opa.bits.start.is_acc_addr, _T_778, _T_781) node _T_783 = and(_T_775, _T_782) node _T_784 = or(_T_783, new_entry.opa.bits.wraps_around) node _T_785 = and(_T_774, _T_784) node _T_786 = or(_T_765, _T_785) node _T_787 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_788 = and(_T_787, new_entry.opa.bits.start.read_full_acc_row) node _T_789 = andr(new_entry.opa.bits.start.data) node _T_790 = and(_T_788, _T_789) node _T_791 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_792 = and(_T_790, _T_791) node _T_793 = and(entries_ex[6].bits.opa.bits.start.is_acc_addr, entries_ex[6].bits.opa.bits.start.accumulate) node _T_794 = and(_T_793, entries_ex[6].bits.opa.bits.start.read_full_acc_row) node _T_795 = andr(entries_ex[6].bits.opa.bits.start.data) node _T_796 = and(_T_794, _T_795) node _T_797 = bits(entries_ex[6].bits.opa.bits.start.garbage_bit, 0, 0) node _T_798 = and(_T_796, _T_797) node _T_799 = or(_T_792, _T_798) node _T_800 = eq(_T_799, UInt<1>(0h0)) node _T_801 = and(_T_786, _T_800) node _T_802 = and(_T_801, entries_ex[6].bits.opa.valid) node _T_803 = eq(entries_ex[6].bits.opb.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_804 = bits(entries_ex[6].bits.opb.bits.start.data, 11, 0) node _T_805 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_806 = leq(_T_804, _T_805) node _T_807 = bits(entries_ex[6].bits.opb.bits.start.data, 13, 0) node _T_808 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_809 = leq(_T_807, _T_808) node _T_810 = mux(entries_ex[6].bits.opb.bits.start.is_acc_addr, _T_806, _T_809) node _T_811 = and(_T_803, _T_810) node _T_812 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[6].bits.opb.bits.end.is_acc_addr) node _T_813 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_814 = bits(entries_ex[6].bits.opb.bits.end.data, 11, 0) node _T_815 = lt(_T_813, _T_814) node _T_816 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_817 = bits(entries_ex[6].bits.opb.bits.end.data, 13, 0) node _T_818 = lt(_T_816, _T_817) node _T_819 = mux(new_entry.opa.bits.start.is_acc_addr, _T_815, _T_818) node _T_820 = and(_T_812, _T_819) node _T_821 = or(_T_820, entries_ex[6].bits.opb.bits.wraps_around) node _T_822 = and(_T_811, _T_821) node _T_823 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[6].bits.opb.bits.start.is_acc_addr) node _T_824 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_825 = bits(entries_ex[6].bits.opb.bits.start.data, 11, 0) node _T_826 = leq(_T_824, _T_825) node _T_827 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_828 = bits(entries_ex[6].bits.opb.bits.start.data, 13, 0) node _T_829 = leq(_T_827, _T_828) node _T_830 = mux(new_entry.opa.bits.start.is_acc_addr, _T_826, _T_829) node _T_831 = and(_T_823, _T_830) node _T_832 = eq(entries_ex[6].bits.opb.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_833 = bits(entries_ex[6].bits.opb.bits.start.data, 11, 0) node _T_834 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_835 = lt(_T_833, _T_834) node _T_836 = bits(entries_ex[6].bits.opb.bits.start.data, 13, 0) node _T_837 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_838 = lt(_T_836, _T_837) node _T_839 = mux(entries_ex[6].bits.opb.bits.start.is_acc_addr, _T_835, _T_838) node _T_840 = and(_T_832, _T_839) node _T_841 = or(_T_840, new_entry.opa.bits.wraps_around) node _T_842 = and(_T_831, _T_841) node _T_843 = or(_T_822, _T_842) node _T_844 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_845 = and(_T_844, new_entry.opa.bits.start.read_full_acc_row) node _T_846 = andr(new_entry.opa.bits.start.data) node _T_847 = and(_T_845, _T_846) node _T_848 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_849 = and(_T_847, _T_848) node _T_850 = and(entries_ex[6].bits.opb.bits.start.is_acc_addr, entries_ex[6].bits.opb.bits.start.accumulate) node _T_851 = and(_T_850, entries_ex[6].bits.opb.bits.start.read_full_acc_row) node _T_852 = andr(entries_ex[6].bits.opb.bits.start.data) node _T_853 = and(_T_851, _T_852) node _T_854 = bits(entries_ex[6].bits.opb.bits.start.garbage_bit, 0, 0) node _T_855 = and(_T_853, _T_854) node _T_856 = or(_T_849, _T_855) node _T_857 = eq(_T_856, UInt<1>(0h0)) node _T_858 = and(_T_843, _T_857) node _T_859 = and(_T_858, entries_ex[6].bits.opb.valid) node _T_860 = or(_T_802, _T_859) node _T_861 = and(_T_745, _T_860) node _T_862 = eq(new_entry.is_config, UInt<1>(0h0)) node _T_863 = and(entries_ex[7].valid, _T_862) node _T_864 = eq(entries_ex[7].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_865 = bits(entries_ex[7].bits.opa.bits.start.data, 11, 0) node _T_866 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_867 = leq(_T_865, _T_866) node _T_868 = bits(entries_ex[7].bits.opa.bits.start.data, 13, 0) node _T_869 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_870 = leq(_T_868, _T_869) node _T_871 = mux(entries_ex[7].bits.opa.bits.start.is_acc_addr, _T_867, _T_870) node _T_872 = and(_T_864, _T_871) node _T_873 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[7].bits.opa.bits.end.is_acc_addr) node _T_874 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_875 = bits(entries_ex[7].bits.opa.bits.end.data, 11, 0) node _T_876 = lt(_T_874, _T_875) node _T_877 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_878 = bits(entries_ex[7].bits.opa.bits.end.data, 13, 0) node _T_879 = lt(_T_877, _T_878) node _T_880 = mux(new_entry.opa.bits.start.is_acc_addr, _T_876, _T_879) node _T_881 = and(_T_873, _T_880) node _T_882 = or(_T_881, entries_ex[7].bits.opa.bits.wraps_around) node _T_883 = and(_T_872, _T_882) node _T_884 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[7].bits.opa.bits.start.is_acc_addr) node _T_885 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_886 = bits(entries_ex[7].bits.opa.bits.start.data, 11, 0) node _T_887 = leq(_T_885, _T_886) node _T_888 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_889 = bits(entries_ex[7].bits.opa.bits.start.data, 13, 0) node _T_890 = leq(_T_888, _T_889) node _T_891 = mux(new_entry.opa.bits.start.is_acc_addr, _T_887, _T_890) node _T_892 = and(_T_884, _T_891) node _T_893 = eq(entries_ex[7].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_894 = bits(entries_ex[7].bits.opa.bits.start.data, 11, 0) node _T_895 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_896 = lt(_T_894, _T_895) node _T_897 = bits(entries_ex[7].bits.opa.bits.start.data, 13, 0) node _T_898 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_899 = lt(_T_897, _T_898) node _T_900 = mux(entries_ex[7].bits.opa.bits.start.is_acc_addr, _T_896, _T_899) node _T_901 = and(_T_893, _T_900) node _T_902 = or(_T_901, new_entry.opa.bits.wraps_around) node _T_903 = and(_T_892, _T_902) node _T_904 = or(_T_883, _T_903) node _T_905 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_906 = and(_T_905, new_entry.opa.bits.start.read_full_acc_row) node _T_907 = andr(new_entry.opa.bits.start.data) node _T_908 = and(_T_906, _T_907) node _T_909 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_910 = and(_T_908, _T_909) node _T_911 = and(entries_ex[7].bits.opa.bits.start.is_acc_addr, entries_ex[7].bits.opa.bits.start.accumulate) node _T_912 = and(_T_911, entries_ex[7].bits.opa.bits.start.read_full_acc_row) node _T_913 = andr(entries_ex[7].bits.opa.bits.start.data) node _T_914 = and(_T_912, _T_913) node _T_915 = bits(entries_ex[7].bits.opa.bits.start.garbage_bit, 0, 0) node _T_916 = and(_T_914, _T_915) node _T_917 = or(_T_910, _T_916) node _T_918 = eq(_T_917, UInt<1>(0h0)) node _T_919 = and(_T_904, _T_918) node _T_920 = and(_T_919, entries_ex[7].bits.opa.valid) node _T_921 = eq(entries_ex[7].bits.opb.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_922 = bits(entries_ex[7].bits.opb.bits.start.data, 11, 0) node _T_923 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_924 = leq(_T_922, _T_923) node _T_925 = bits(entries_ex[7].bits.opb.bits.start.data, 13, 0) node _T_926 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_927 = leq(_T_925, _T_926) node _T_928 = mux(entries_ex[7].bits.opb.bits.start.is_acc_addr, _T_924, _T_927) node _T_929 = and(_T_921, _T_928) node _T_930 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[7].bits.opb.bits.end.is_acc_addr) node _T_931 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_932 = bits(entries_ex[7].bits.opb.bits.end.data, 11, 0) node _T_933 = lt(_T_931, _T_932) node _T_934 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_935 = bits(entries_ex[7].bits.opb.bits.end.data, 13, 0) node _T_936 = lt(_T_934, _T_935) node _T_937 = mux(new_entry.opa.bits.start.is_acc_addr, _T_933, _T_936) node _T_938 = and(_T_930, _T_937) node _T_939 = or(_T_938, entries_ex[7].bits.opb.bits.wraps_around) node _T_940 = and(_T_929, _T_939) node _T_941 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[7].bits.opb.bits.start.is_acc_addr) node _T_942 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_943 = bits(entries_ex[7].bits.opb.bits.start.data, 11, 0) node _T_944 = leq(_T_942, _T_943) node _T_945 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_946 = bits(entries_ex[7].bits.opb.bits.start.data, 13, 0) node _T_947 = leq(_T_945, _T_946) node _T_948 = mux(new_entry.opa.bits.start.is_acc_addr, _T_944, _T_947) node _T_949 = and(_T_941, _T_948) node _T_950 = eq(entries_ex[7].bits.opb.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_951 = bits(entries_ex[7].bits.opb.bits.start.data, 11, 0) node _T_952 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_953 = lt(_T_951, _T_952) node _T_954 = bits(entries_ex[7].bits.opb.bits.start.data, 13, 0) node _T_955 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_956 = lt(_T_954, _T_955) node _T_957 = mux(entries_ex[7].bits.opb.bits.start.is_acc_addr, _T_953, _T_956) node _T_958 = and(_T_950, _T_957) node _T_959 = or(_T_958, new_entry.opa.bits.wraps_around) node _T_960 = and(_T_949, _T_959) node _T_961 = or(_T_940, _T_960) node _T_962 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_963 = and(_T_962, new_entry.opa.bits.start.read_full_acc_row) node _T_964 = andr(new_entry.opa.bits.start.data) node _T_965 = and(_T_963, _T_964) node _T_966 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_967 = and(_T_965, _T_966) node _T_968 = and(entries_ex[7].bits.opb.bits.start.is_acc_addr, entries_ex[7].bits.opb.bits.start.accumulate) node _T_969 = and(_T_968, entries_ex[7].bits.opb.bits.start.read_full_acc_row) node _T_970 = andr(entries_ex[7].bits.opb.bits.start.data) node _T_971 = and(_T_969, _T_970) node _T_972 = bits(entries_ex[7].bits.opb.bits.start.garbage_bit, 0, 0) node _T_973 = and(_T_971, _T_972) node _T_974 = or(_T_967, _T_973) node _T_975 = eq(_T_974, UInt<1>(0h0)) node _T_976 = and(_T_961, _T_975) node _T_977 = and(_T_976, entries_ex[7].bits.opb.valid) node _T_978 = or(_T_920, _T_977) node _T_979 = and(_T_863, _T_978) node _T_980 = eq(new_entry.is_config, UInt<1>(0h0)) node _T_981 = and(entries_ex[8].valid, _T_980) node _T_982 = eq(entries_ex[8].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_983 = bits(entries_ex[8].bits.opa.bits.start.data, 11, 0) node _T_984 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_985 = leq(_T_983, _T_984) node _T_986 = bits(entries_ex[8].bits.opa.bits.start.data, 13, 0) node _T_987 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_988 = leq(_T_986, _T_987) node _T_989 = mux(entries_ex[8].bits.opa.bits.start.is_acc_addr, _T_985, _T_988) node _T_990 = and(_T_982, _T_989) node _T_991 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[8].bits.opa.bits.end.is_acc_addr) node _T_992 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_993 = bits(entries_ex[8].bits.opa.bits.end.data, 11, 0) node _T_994 = lt(_T_992, _T_993) node _T_995 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_996 = bits(entries_ex[8].bits.opa.bits.end.data, 13, 0) node _T_997 = lt(_T_995, _T_996) node _T_998 = mux(new_entry.opa.bits.start.is_acc_addr, _T_994, _T_997) node _T_999 = and(_T_991, _T_998) node _T_1000 = or(_T_999, entries_ex[8].bits.opa.bits.wraps_around) node _T_1001 = and(_T_990, _T_1000) node _T_1002 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[8].bits.opa.bits.start.is_acc_addr) node _T_1003 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_1004 = bits(entries_ex[8].bits.opa.bits.start.data, 11, 0) node _T_1005 = leq(_T_1003, _T_1004) node _T_1006 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_1007 = bits(entries_ex[8].bits.opa.bits.start.data, 13, 0) node _T_1008 = leq(_T_1006, _T_1007) node _T_1009 = mux(new_entry.opa.bits.start.is_acc_addr, _T_1005, _T_1008) node _T_1010 = and(_T_1002, _T_1009) node _T_1011 = eq(entries_ex[8].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_1012 = bits(entries_ex[8].bits.opa.bits.start.data, 11, 0) node _T_1013 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_1014 = lt(_T_1012, _T_1013) node _T_1015 = bits(entries_ex[8].bits.opa.bits.start.data, 13, 0) node _T_1016 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_1017 = lt(_T_1015, _T_1016) node _T_1018 = mux(entries_ex[8].bits.opa.bits.start.is_acc_addr, _T_1014, _T_1017) node _T_1019 = and(_T_1011, _T_1018) node _T_1020 = or(_T_1019, new_entry.opa.bits.wraps_around) node _T_1021 = and(_T_1010, _T_1020) node _T_1022 = or(_T_1001, _T_1021) node _T_1023 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_1024 = and(_T_1023, new_entry.opa.bits.start.read_full_acc_row) node _T_1025 = andr(new_entry.opa.bits.start.data) node _T_1026 = and(_T_1024, _T_1025) node _T_1027 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_1028 = and(_T_1026, _T_1027) node _T_1029 = and(entries_ex[8].bits.opa.bits.start.is_acc_addr, entries_ex[8].bits.opa.bits.start.accumulate) node _T_1030 = and(_T_1029, entries_ex[8].bits.opa.bits.start.read_full_acc_row) node _T_1031 = andr(entries_ex[8].bits.opa.bits.start.data) node _T_1032 = and(_T_1030, _T_1031) node _T_1033 = bits(entries_ex[8].bits.opa.bits.start.garbage_bit, 0, 0) node _T_1034 = and(_T_1032, _T_1033) node _T_1035 = or(_T_1028, _T_1034) node _T_1036 = eq(_T_1035, UInt<1>(0h0)) node _T_1037 = and(_T_1022, _T_1036) node _T_1038 = and(_T_1037, entries_ex[8].bits.opa.valid) node _T_1039 = eq(entries_ex[8].bits.opb.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_1040 = bits(entries_ex[8].bits.opb.bits.start.data, 11, 0) node _T_1041 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_1042 = leq(_T_1040, _T_1041) node _T_1043 = bits(entries_ex[8].bits.opb.bits.start.data, 13, 0) node _T_1044 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_1045 = leq(_T_1043, _T_1044) node _T_1046 = mux(entries_ex[8].bits.opb.bits.start.is_acc_addr, _T_1042, _T_1045) node _T_1047 = and(_T_1039, _T_1046) node _T_1048 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[8].bits.opb.bits.end.is_acc_addr) node _T_1049 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_1050 = bits(entries_ex[8].bits.opb.bits.end.data, 11, 0) node _T_1051 = lt(_T_1049, _T_1050) node _T_1052 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_1053 = bits(entries_ex[8].bits.opb.bits.end.data, 13, 0) node _T_1054 = lt(_T_1052, _T_1053) node _T_1055 = mux(new_entry.opa.bits.start.is_acc_addr, _T_1051, _T_1054) node _T_1056 = and(_T_1048, _T_1055) node _T_1057 = or(_T_1056, entries_ex[8].bits.opb.bits.wraps_around) node _T_1058 = and(_T_1047, _T_1057) node _T_1059 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[8].bits.opb.bits.start.is_acc_addr) node _T_1060 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_1061 = bits(entries_ex[8].bits.opb.bits.start.data, 11, 0) node _T_1062 = leq(_T_1060, _T_1061) node _T_1063 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_1064 = bits(entries_ex[8].bits.opb.bits.start.data, 13, 0) node _T_1065 = leq(_T_1063, _T_1064) node _T_1066 = mux(new_entry.opa.bits.start.is_acc_addr, _T_1062, _T_1065) node _T_1067 = and(_T_1059, _T_1066) node _T_1068 = eq(entries_ex[8].bits.opb.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_1069 = bits(entries_ex[8].bits.opb.bits.start.data, 11, 0) node _T_1070 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_1071 = lt(_T_1069, _T_1070) node _T_1072 = bits(entries_ex[8].bits.opb.bits.start.data, 13, 0) node _T_1073 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_1074 = lt(_T_1072, _T_1073) node _T_1075 = mux(entries_ex[8].bits.opb.bits.start.is_acc_addr, _T_1071, _T_1074) node _T_1076 = and(_T_1068, _T_1075) node _T_1077 = or(_T_1076, new_entry.opa.bits.wraps_around) node _T_1078 = and(_T_1067, _T_1077) node _T_1079 = or(_T_1058, _T_1078) node _T_1080 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_1081 = and(_T_1080, new_entry.opa.bits.start.read_full_acc_row) node _T_1082 = andr(new_entry.opa.bits.start.data) node _T_1083 = and(_T_1081, _T_1082) node _T_1084 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_1085 = and(_T_1083, _T_1084) node _T_1086 = and(entries_ex[8].bits.opb.bits.start.is_acc_addr, entries_ex[8].bits.opb.bits.start.accumulate) node _T_1087 = and(_T_1086, entries_ex[8].bits.opb.bits.start.read_full_acc_row) node _T_1088 = andr(entries_ex[8].bits.opb.bits.start.data) node _T_1089 = and(_T_1087, _T_1088) node _T_1090 = bits(entries_ex[8].bits.opb.bits.start.garbage_bit, 0, 0) node _T_1091 = and(_T_1089, _T_1090) node _T_1092 = or(_T_1085, _T_1091) node _T_1093 = eq(_T_1092, UInt<1>(0h0)) node _T_1094 = and(_T_1079, _T_1093) node _T_1095 = and(_T_1094, entries_ex[8].bits.opb.valid) node _T_1096 = or(_T_1038, _T_1095) node _T_1097 = and(_T_981, _T_1096) node _T_1098 = eq(new_entry.is_config, UInt<1>(0h0)) node _T_1099 = and(entries_ex[9].valid, _T_1098) node _T_1100 = eq(entries_ex[9].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_1101 = bits(entries_ex[9].bits.opa.bits.start.data, 11, 0) node _T_1102 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_1103 = leq(_T_1101, _T_1102) node _T_1104 = bits(entries_ex[9].bits.opa.bits.start.data, 13, 0) node _T_1105 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_1106 = leq(_T_1104, _T_1105) node _T_1107 = mux(entries_ex[9].bits.opa.bits.start.is_acc_addr, _T_1103, _T_1106) node _T_1108 = and(_T_1100, _T_1107) node _T_1109 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[9].bits.opa.bits.end.is_acc_addr) node _T_1110 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_1111 = bits(entries_ex[9].bits.opa.bits.end.data, 11, 0) node _T_1112 = lt(_T_1110, _T_1111) node _T_1113 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_1114 = bits(entries_ex[9].bits.opa.bits.end.data, 13, 0) node _T_1115 = lt(_T_1113, _T_1114) node _T_1116 = mux(new_entry.opa.bits.start.is_acc_addr, _T_1112, _T_1115) node _T_1117 = and(_T_1109, _T_1116) node _T_1118 = or(_T_1117, entries_ex[9].bits.opa.bits.wraps_around) node _T_1119 = and(_T_1108, _T_1118) node _T_1120 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[9].bits.opa.bits.start.is_acc_addr) node _T_1121 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_1122 = bits(entries_ex[9].bits.opa.bits.start.data, 11, 0) node _T_1123 = leq(_T_1121, _T_1122) node _T_1124 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_1125 = bits(entries_ex[9].bits.opa.bits.start.data, 13, 0) node _T_1126 = leq(_T_1124, _T_1125) node _T_1127 = mux(new_entry.opa.bits.start.is_acc_addr, _T_1123, _T_1126) node _T_1128 = and(_T_1120, _T_1127) node _T_1129 = eq(entries_ex[9].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_1130 = bits(entries_ex[9].bits.opa.bits.start.data, 11, 0) node _T_1131 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_1132 = lt(_T_1130, _T_1131) node _T_1133 = bits(entries_ex[9].bits.opa.bits.start.data, 13, 0) node _T_1134 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_1135 = lt(_T_1133, _T_1134) node _T_1136 = mux(entries_ex[9].bits.opa.bits.start.is_acc_addr, _T_1132, _T_1135) node _T_1137 = and(_T_1129, _T_1136) node _T_1138 = or(_T_1137, new_entry.opa.bits.wraps_around) node _T_1139 = and(_T_1128, _T_1138) node _T_1140 = or(_T_1119, _T_1139) node _T_1141 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_1142 = and(_T_1141, new_entry.opa.bits.start.read_full_acc_row) node _T_1143 = andr(new_entry.opa.bits.start.data) node _T_1144 = and(_T_1142, _T_1143) node _T_1145 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_1146 = and(_T_1144, _T_1145) node _T_1147 = and(entries_ex[9].bits.opa.bits.start.is_acc_addr, entries_ex[9].bits.opa.bits.start.accumulate) node _T_1148 = and(_T_1147, entries_ex[9].bits.opa.bits.start.read_full_acc_row) node _T_1149 = andr(entries_ex[9].bits.opa.bits.start.data) node _T_1150 = and(_T_1148, _T_1149) node _T_1151 = bits(entries_ex[9].bits.opa.bits.start.garbage_bit, 0, 0) node _T_1152 = and(_T_1150, _T_1151) node _T_1153 = or(_T_1146, _T_1152) node _T_1154 = eq(_T_1153, UInt<1>(0h0)) node _T_1155 = and(_T_1140, _T_1154) node _T_1156 = and(_T_1155, entries_ex[9].bits.opa.valid) node _T_1157 = eq(entries_ex[9].bits.opb.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_1158 = bits(entries_ex[9].bits.opb.bits.start.data, 11, 0) node _T_1159 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_1160 = leq(_T_1158, _T_1159) node _T_1161 = bits(entries_ex[9].bits.opb.bits.start.data, 13, 0) node _T_1162 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_1163 = leq(_T_1161, _T_1162) node _T_1164 = mux(entries_ex[9].bits.opb.bits.start.is_acc_addr, _T_1160, _T_1163) node _T_1165 = and(_T_1157, _T_1164) node _T_1166 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[9].bits.opb.bits.end.is_acc_addr) node _T_1167 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_1168 = bits(entries_ex[9].bits.opb.bits.end.data, 11, 0) node _T_1169 = lt(_T_1167, _T_1168) node _T_1170 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_1171 = bits(entries_ex[9].bits.opb.bits.end.data, 13, 0) node _T_1172 = lt(_T_1170, _T_1171) node _T_1173 = mux(new_entry.opa.bits.start.is_acc_addr, _T_1169, _T_1172) node _T_1174 = and(_T_1166, _T_1173) node _T_1175 = or(_T_1174, entries_ex[9].bits.opb.bits.wraps_around) node _T_1176 = and(_T_1165, _T_1175) node _T_1177 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[9].bits.opb.bits.start.is_acc_addr) node _T_1178 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_1179 = bits(entries_ex[9].bits.opb.bits.start.data, 11, 0) node _T_1180 = leq(_T_1178, _T_1179) node _T_1181 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_1182 = bits(entries_ex[9].bits.opb.bits.start.data, 13, 0) node _T_1183 = leq(_T_1181, _T_1182) node _T_1184 = mux(new_entry.opa.bits.start.is_acc_addr, _T_1180, _T_1183) node _T_1185 = and(_T_1177, _T_1184) node _T_1186 = eq(entries_ex[9].bits.opb.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_1187 = bits(entries_ex[9].bits.opb.bits.start.data, 11, 0) node _T_1188 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_1189 = lt(_T_1187, _T_1188) node _T_1190 = bits(entries_ex[9].bits.opb.bits.start.data, 13, 0) node _T_1191 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_1192 = lt(_T_1190, _T_1191) node _T_1193 = mux(entries_ex[9].bits.opb.bits.start.is_acc_addr, _T_1189, _T_1192) node _T_1194 = and(_T_1186, _T_1193) node _T_1195 = or(_T_1194, new_entry.opa.bits.wraps_around) node _T_1196 = and(_T_1185, _T_1195) node _T_1197 = or(_T_1176, _T_1196) node _T_1198 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_1199 = and(_T_1198, new_entry.opa.bits.start.read_full_acc_row) node _T_1200 = andr(new_entry.opa.bits.start.data) node _T_1201 = and(_T_1199, _T_1200) node _T_1202 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_1203 = and(_T_1201, _T_1202) node _T_1204 = and(entries_ex[9].bits.opb.bits.start.is_acc_addr, entries_ex[9].bits.opb.bits.start.accumulate) node _T_1205 = and(_T_1204, entries_ex[9].bits.opb.bits.start.read_full_acc_row) node _T_1206 = andr(entries_ex[9].bits.opb.bits.start.data) node _T_1207 = and(_T_1205, _T_1206) node _T_1208 = bits(entries_ex[9].bits.opb.bits.start.garbage_bit, 0, 0) node _T_1209 = and(_T_1207, _T_1208) node _T_1210 = or(_T_1203, _T_1209) node _T_1211 = eq(_T_1210, UInt<1>(0h0)) node _T_1212 = and(_T_1197, _T_1211) node _T_1213 = and(_T_1212, entries_ex[9].bits.opb.valid) node _T_1214 = or(_T_1156, _T_1213) node _T_1215 = and(_T_1099, _T_1214) node _T_1216 = eq(new_entry.is_config, UInt<1>(0h0)) node _T_1217 = and(entries_ex[10].valid, _T_1216) node _T_1218 = eq(entries_ex[10].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_1219 = bits(entries_ex[10].bits.opa.bits.start.data, 11, 0) node _T_1220 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_1221 = leq(_T_1219, _T_1220) node _T_1222 = bits(entries_ex[10].bits.opa.bits.start.data, 13, 0) node _T_1223 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_1224 = leq(_T_1222, _T_1223) node _T_1225 = mux(entries_ex[10].bits.opa.bits.start.is_acc_addr, _T_1221, _T_1224) node _T_1226 = and(_T_1218, _T_1225) node _T_1227 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[10].bits.opa.bits.end.is_acc_addr) node _T_1228 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_1229 = bits(entries_ex[10].bits.opa.bits.end.data, 11, 0) node _T_1230 = lt(_T_1228, _T_1229) node _T_1231 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_1232 = bits(entries_ex[10].bits.opa.bits.end.data, 13, 0) node _T_1233 = lt(_T_1231, _T_1232) node _T_1234 = mux(new_entry.opa.bits.start.is_acc_addr, _T_1230, _T_1233) node _T_1235 = and(_T_1227, _T_1234) node _T_1236 = or(_T_1235, entries_ex[10].bits.opa.bits.wraps_around) node _T_1237 = and(_T_1226, _T_1236) node _T_1238 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[10].bits.opa.bits.start.is_acc_addr) node _T_1239 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_1240 = bits(entries_ex[10].bits.opa.bits.start.data, 11, 0) node _T_1241 = leq(_T_1239, _T_1240) node _T_1242 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_1243 = bits(entries_ex[10].bits.opa.bits.start.data, 13, 0) node _T_1244 = leq(_T_1242, _T_1243) node _T_1245 = mux(new_entry.opa.bits.start.is_acc_addr, _T_1241, _T_1244) node _T_1246 = and(_T_1238, _T_1245) node _T_1247 = eq(entries_ex[10].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_1248 = bits(entries_ex[10].bits.opa.bits.start.data, 11, 0) node _T_1249 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_1250 = lt(_T_1248, _T_1249) node _T_1251 = bits(entries_ex[10].bits.opa.bits.start.data, 13, 0) node _T_1252 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_1253 = lt(_T_1251, _T_1252) node _T_1254 = mux(entries_ex[10].bits.opa.bits.start.is_acc_addr, _T_1250, _T_1253) node _T_1255 = and(_T_1247, _T_1254) node _T_1256 = or(_T_1255, new_entry.opa.bits.wraps_around) node _T_1257 = and(_T_1246, _T_1256) node _T_1258 = or(_T_1237, _T_1257) node _T_1259 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_1260 = and(_T_1259, new_entry.opa.bits.start.read_full_acc_row) node _T_1261 = andr(new_entry.opa.bits.start.data) node _T_1262 = and(_T_1260, _T_1261) node _T_1263 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_1264 = and(_T_1262, _T_1263) node _T_1265 = and(entries_ex[10].bits.opa.bits.start.is_acc_addr, entries_ex[10].bits.opa.bits.start.accumulate) node _T_1266 = and(_T_1265, entries_ex[10].bits.opa.bits.start.read_full_acc_row) node _T_1267 = andr(entries_ex[10].bits.opa.bits.start.data) node _T_1268 = and(_T_1266, _T_1267) node _T_1269 = bits(entries_ex[10].bits.opa.bits.start.garbage_bit, 0, 0) node _T_1270 = and(_T_1268, _T_1269) node _T_1271 = or(_T_1264, _T_1270) node _T_1272 = eq(_T_1271, UInt<1>(0h0)) node _T_1273 = and(_T_1258, _T_1272) node _T_1274 = and(_T_1273, entries_ex[10].bits.opa.valid) node _T_1275 = eq(entries_ex[10].bits.opb.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_1276 = bits(entries_ex[10].bits.opb.bits.start.data, 11, 0) node _T_1277 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_1278 = leq(_T_1276, _T_1277) node _T_1279 = bits(entries_ex[10].bits.opb.bits.start.data, 13, 0) node _T_1280 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_1281 = leq(_T_1279, _T_1280) node _T_1282 = mux(entries_ex[10].bits.opb.bits.start.is_acc_addr, _T_1278, _T_1281) node _T_1283 = and(_T_1275, _T_1282) node _T_1284 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[10].bits.opb.bits.end.is_acc_addr) node _T_1285 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_1286 = bits(entries_ex[10].bits.opb.bits.end.data, 11, 0) node _T_1287 = lt(_T_1285, _T_1286) node _T_1288 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_1289 = bits(entries_ex[10].bits.opb.bits.end.data, 13, 0) node _T_1290 = lt(_T_1288, _T_1289) node _T_1291 = mux(new_entry.opa.bits.start.is_acc_addr, _T_1287, _T_1290) node _T_1292 = and(_T_1284, _T_1291) node _T_1293 = or(_T_1292, entries_ex[10].bits.opb.bits.wraps_around) node _T_1294 = and(_T_1283, _T_1293) node _T_1295 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[10].bits.opb.bits.start.is_acc_addr) node _T_1296 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_1297 = bits(entries_ex[10].bits.opb.bits.start.data, 11, 0) node _T_1298 = leq(_T_1296, _T_1297) node _T_1299 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_1300 = bits(entries_ex[10].bits.opb.bits.start.data, 13, 0) node _T_1301 = leq(_T_1299, _T_1300) node _T_1302 = mux(new_entry.opa.bits.start.is_acc_addr, _T_1298, _T_1301) node _T_1303 = and(_T_1295, _T_1302) node _T_1304 = eq(entries_ex[10].bits.opb.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_1305 = bits(entries_ex[10].bits.opb.bits.start.data, 11, 0) node _T_1306 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_1307 = lt(_T_1305, _T_1306) node _T_1308 = bits(entries_ex[10].bits.opb.bits.start.data, 13, 0) node _T_1309 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_1310 = lt(_T_1308, _T_1309) node _T_1311 = mux(entries_ex[10].bits.opb.bits.start.is_acc_addr, _T_1307, _T_1310) node _T_1312 = and(_T_1304, _T_1311) node _T_1313 = or(_T_1312, new_entry.opa.bits.wraps_around) node _T_1314 = and(_T_1303, _T_1313) node _T_1315 = or(_T_1294, _T_1314) node _T_1316 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_1317 = and(_T_1316, new_entry.opa.bits.start.read_full_acc_row) node _T_1318 = andr(new_entry.opa.bits.start.data) node _T_1319 = and(_T_1317, _T_1318) node _T_1320 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_1321 = and(_T_1319, _T_1320) node _T_1322 = and(entries_ex[10].bits.opb.bits.start.is_acc_addr, entries_ex[10].bits.opb.bits.start.accumulate) node _T_1323 = and(_T_1322, entries_ex[10].bits.opb.bits.start.read_full_acc_row) node _T_1324 = andr(entries_ex[10].bits.opb.bits.start.data) node _T_1325 = and(_T_1323, _T_1324) node _T_1326 = bits(entries_ex[10].bits.opb.bits.start.garbage_bit, 0, 0) node _T_1327 = and(_T_1325, _T_1326) node _T_1328 = or(_T_1321, _T_1327) node _T_1329 = eq(_T_1328, UInt<1>(0h0)) node _T_1330 = and(_T_1315, _T_1329) node _T_1331 = and(_T_1330, entries_ex[10].bits.opb.valid) node _T_1332 = or(_T_1274, _T_1331) node _T_1333 = and(_T_1217, _T_1332) node _T_1334 = eq(new_entry.is_config, UInt<1>(0h0)) node _T_1335 = and(entries_ex[11].valid, _T_1334) node _T_1336 = eq(entries_ex[11].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_1337 = bits(entries_ex[11].bits.opa.bits.start.data, 11, 0) node _T_1338 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_1339 = leq(_T_1337, _T_1338) node _T_1340 = bits(entries_ex[11].bits.opa.bits.start.data, 13, 0) node _T_1341 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_1342 = leq(_T_1340, _T_1341) node _T_1343 = mux(entries_ex[11].bits.opa.bits.start.is_acc_addr, _T_1339, _T_1342) node _T_1344 = and(_T_1336, _T_1343) node _T_1345 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[11].bits.opa.bits.end.is_acc_addr) node _T_1346 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_1347 = bits(entries_ex[11].bits.opa.bits.end.data, 11, 0) node _T_1348 = lt(_T_1346, _T_1347) node _T_1349 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_1350 = bits(entries_ex[11].bits.opa.bits.end.data, 13, 0) node _T_1351 = lt(_T_1349, _T_1350) node _T_1352 = mux(new_entry.opa.bits.start.is_acc_addr, _T_1348, _T_1351) node _T_1353 = and(_T_1345, _T_1352) node _T_1354 = or(_T_1353, entries_ex[11].bits.opa.bits.wraps_around) node _T_1355 = and(_T_1344, _T_1354) node _T_1356 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[11].bits.opa.bits.start.is_acc_addr) node _T_1357 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_1358 = bits(entries_ex[11].bits.opa.bits.start.data, 11, 0) node _T_1359 = leq(_T_1357, _T_1358) node _T_1360 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_1361 = bits(entries_ex[11].bits.opa.bits.start.data, 13, 0) node _T_1362 = leq(_T_1360, _T_1361) node _T_1363 = mux(new_entry.opa.bits.start.is_acc_addr, _T_1359, _T_1362) node _T_1364 = and(_T_1356, _T_1363) node _T_1365 = eq(entries_ex[11].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_1366 = bits(entries_ex[11].bits.opa.bits.start.data, 11, 0) node _T_1367 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_1368 = lt(_T_1366, _T_1367) node _T_1369 = bits(entries_ex[11].bits.opa.bits.start.data, 13, 0) node _T_1370 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_1371 = lt(_T_1369, _T_1370) node _T_1372 = mux(entries_ex[11].bits.opa.bits.start.is_acc_addr, _T_1368, _T_1371) node _T_1373 = and(_T_1365, _T_1372) node _T_1374 = or(_T_1373, new_entry.opa.bits.wraps_around) node _T_1375 = and(_T_1364, _T_1374) node _T_1376 = or(_T_1355, _T_1375) node _T_1377 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_1378 = and(_T_1377, new_entry.opa.bits.start.read_full_acc_row) node _T_1379 = andr(new_entry.opa.bits.start.data) node _T_1380 = and(_T_1378, _T_1379) node _T_1381 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_1382 = and(_T_1380, _T_1381) node _T_1383 = and(entries_ex[11].bits.opa.bits.start.is_acc_addr, entries_ex[11].bits.opa.bits.start.accumulate) node _T_1384 = and(_T_1383, entries_ex[11].bits.opa.bits.start.read_full_acc_row) node _T_1385 = andr(entries_ex[11].bits.opa.bits.start.data) node _T_1386 = and(_T_1384, _T_1385) node _T_1387 = bits(entries_ex[11].bits.opa.bits.start.garbage_bit, 0, 0) node _T_1388 = and(_T_1386, _T_1387) node _T_1389 = or(_T_1382, _T_1388) node _T_1390 = eq(_T_1389, UInt<1>(0h0)) node _T_1391 = and(_T_1376, _T_1390) node _T_1392 = and(_T_1391, entries_ex[11].bits.opa.valid) node _T_1393 = eq(entries_ex[11].bits.opb.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_1394 = bits(entries_ex[11].bits.opb.bits.start.data, 11, 0) node _T_1395 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_1396 = leq(_T_1394, _T_1395) node _T_1397 = bits(entries_ex[11].bits.opb.bits.start.data, 13, 0) node _T_1398 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_1399 = leq(_T_1397, _T_1398) node _T_1400 = mux(entries_ex[11].bits.opb.bits.start.is_acc_addr, _T_1396, _T_1399) node _T_1401 = and(_T_1393, _T_1400) node _T_1402 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[11].bits.opb.bits.end.is_acc_addr) node _T_1403 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_1404 = bits(entries_ex[11].bits.opb.bits.end.data, 11, 0) node _T_1405 = lt(_T_1403, _T_1404) node _T_1406 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_1407 = bits(entries_ex[11].bits.opb.bits.end.data, 13, 0) node _T_1408 = lt(_T_1406, _T_1407) node _T_1409 = mux(new_entry.opa.bits.start.is_acc_addr, _T_1405, _T_1408) node _T_1410 = and(_T_1402, _T_1409) node _T_1411 = or(_T_1410, entries_ex[11].bits.opb.bits.wraps_around) node _T_1412 = and(_T_1401, _T_1411) node _T_1413 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[11].bits.opb.bits.start.is_acc_addr) node _T_1414 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_1415 = bits(entries_ex[11].bits.opb.bits.start.data, 11, 0) node _T_1416 = leq(_T_1414, _T_1415) node _T_1417 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_1418 = bits(entries_ex[11].bits.opb.bits.start.data, 13, 0) node _T_1419 = leq(_T_1417, _T_1418) node _T_1420 = mux(new_entry.opa.bits.start.is_acc_addr, _T_1416, _T_1419) node _T_1421 = and(_T_1413, _T_1420) node _T_1422 = eq(entries_ex[11].bits.opb.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_1423 = bits(entries_ex[11].bits.opb.bits.start.data, 11, 0) node _T_1424 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_1425 = lt(_T_1423, _T_1424) node _T_1426 = bits(entries_ex[11].bits.opb.bits.start.data, 13, 0) node _T_1427 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_1428 = lt(_T_1426, _T_1427) node _T_1429 = mux(entries_ex[11].bits.opb.bits.start.is_acc_addr, _T_1425, _T_1428) node _T_1430 = and(_T_1422, _T_1429) node _T_1431 = or(_T_1430, new_entry.opa.bits.wraps_around) node _T_1432 = and(_T_1421, _T_1431) node _T_1433 = or(_T_1412, _T_1432) node _T_1434 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_1435 = and(_T_1434, new_entry.opa.bits.start.read_full_acc_row) node _T_1436 = andr(new_entry.opa.bits.start.data) node _T_1437 = and(_T_1435, _T_1436) node _T_1438 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_1439 = and(_T_1437, _T_1438) node _T_1440 = and(entries_ex[11].bits.opb.bits.start.is_acc_addr, entries_ex[11].bits.opb.bits.start.accumulate) node _T_1441 = and(_T_1440, entries_ex[11].bits.opb.bits.start.read_full_acc_row) node _T_1442 = andr(entries_ex[11].bits.opb.bits.start.data) node _T_1443 = and(_T_1441, _T_1442) node _T_1444 = bits(entries_ex[11].bits.opb.bits.start.garbage_bit, 0, 0) node _T_1445 = and(_T_1443, _T_1444) node _T_1446 = or(_T_1439, _T_1445) node _T_1447 = eq(_T_1446, UInt<1>(0h0)) node _T_1448 = and(_T_1433, _T_1447) node _T_1449 = and(_T_1448, entries_ex[11].bits.opb.valid) node _T_1450 = or(_T_1392, _T_1449) node _T_1451 = and(_T_1335, _T_1450) node _T_1452 = eq(new_entry.is_config, UInt<1>(0h0)) node _T_1453 = and(entries_ex[12].valid, _T_1452) node _T_1454 = eq(entries_ex[12].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_1455 = bits(entries_ex[12].bits.opa.bits.start.data, 11, 0) node _T_1456 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_1457 = leq(_T_1455, _T_1456) node _T_1458 = bits(entries_ex[12].bits.opa.bits.start.data, 13, 0) node _T_1459 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_1460 = leq(_T_1458, _T_1459) node _T_1461 = mux(entries_ex[12].bits.opa.bits.start.is_acc_addr, _T_1457, _T_1460) node _T_1462 = and(_T_1454, _T_1461) node _T_1463 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[12].bits.opa.bits.end.is_acc_addr) node _T_1464 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_1465 = bits(entries_ex[12].bits.opa.bits.end.data, 11, 0) node _T_1466 = lt(_T_1464, _T_1465) node _T_1467 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_1468 = bits(entries_ex[12].bits.opa.bits.end.data, 13, 0) node _T_1469 = lt(_T_1467, _T_1468) node _T_1470 = mux(new_entry.opa.bits.start.is_acc_addr, _T_1466, _T_1469) node _T_1471 = and(_T_1463, _T_1470) node _T_1472 = or(_T_1471, entries_ex[12].bits.opa.bits.wraps_around) node _T_1473 = and(_T_1462, _T_1472) node _T_1474 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[12].bits.opa.bits.start.is_acc_addr) node _T_1475 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_1476 = bits(entries_ex[12].bits.opa.bits.start.data, 11, 0) node _T_1477 = leq(_T_1475, _T_1476) node _T_1478 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_1479 = bits(entries_ex[12].bits.opa.bits.start.data, 13, 0) node _T_1480 = leq(_T_1478, _T_1479) node _T_1481 = mux(new_entry.opa.bits.start.is_acc_addr, _T_1477, _T_1480) node _T_1482 = and(_T_1474, _T_1481) node _T_1483 = eq(entries_ex[12].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_1484 = bits(entries_ex[12].bits.opa.bits.start.data, 11, 0) node _T_1485 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_1486 = lt(_T_1484, _T_1485) node _T_1487 = bits(entries_ex[12].bits.opa.bits.start.data, 13, 0) node _T_1488 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_1489 = lt(_T_1487, _T_1488) node _T_1490 = mux(entries_ex[12].bits.opa.bits.start.is_acc_addr, _T_1486, _T_1489) node _T_1491 = and(_T_1483, _T_1490) node _T_1492 = or(_T_1491, new_entry.opa.bits.wraps_around) node _T_1493 = and(_T_1482, _T_1492) node _T_1494 = or(_T_1473, _T_1493) node _T_1495 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_1496 = and(_T_1495, new_entry.opa.bits.start.read_full_acc_row) node _T_1497 = andr(new_entry.opa.bits.start.data) node _T_1498 = and(_T_1496, _T_1497) node _T_1499 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_1500 = and(_T_1498, _T_1499) node _T_1501 = and(entries_ex[12].bits.opa.bits.start.is_acc_addr, entries_ex[12].bits.opa.bits.start.accumulate) node _T_1502 = and(_T_1501, entries_ex[12].bits.opa.bits.start.read_full_acc_row) node _T_1503 = andr(entries_ex[12].bits.opa.bits.start.data) node _T_1504 = and(_T_1502, _T_1503) node _T_1505 = bits(entries_ex[12].bits.opa.bits.start.garbage_bit, 0, 0) node _T_1506 = and(_T_1504, _T_1505) node _T_1507 = or(_T_1500, _T_1506) node _T_1508 = eq(_T_1507, UInt<1>(0h0)) node _T_1509 = and(_T_1494, _T_1508) node _T_1510 = and(_T_1509, entries_ex[12].bits.opa.valid) node _T_1511 = eq(entries_ex[12].bits.opb.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_1512 = bits(entries_ex[12].bits.opb.bits.start.data, 11, 0) node _T_1513 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_1514 = leq(_T_1512, _T_1513) node _T_1515 = bits(entries_ex[12].bits.opb.bits.start.data, 13, 0) node _T_1516 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_1517 = leq(_T_1515, _T_1516) node _T_1518 = mux(entries_ex[12].bits.opb.bits.start.is_acc_addr, _T_1514, _T_1517) node _T_1519 = and(_T_1511, _T_1518) node _T_1520 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[12].bits.opb.bits.end.is_acc_addr) node _T_1521 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_1522 = bits(entries_ex[12].bits.opb.bits.end.data, 11, 0) node _T_1523 = lt(_T_1521, _T_1522) node _T_1524 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_1525 = bits(entries_ex[12].bits.opb.bits.end.data, 13, 0) node _T_1526 = lt(_T_1524, _T_1525) node _T_1527 = mux(new_entry.opa.bits.start.is_acc_addr, _T_1523, _T_1526) node _T_1528 = and(_T_1520, _T_1527) node _T_1529 = or(_T_1528, entries_ex[12].bits.opb.bits.wraps_around) node _T_1530 = and(_T_1519, _T_1529) node _T_1531 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[12].bits.opb.bits.start.is_acc_addr) node _T_1532 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_1533 = bits(entries_ex[12].bits.opb.bits.start.data, 11, 0) node _T_1534 = leq(_T_1532, _T_1533) node _T_1535 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_1536 = bits(entries_ex[12].bits.opb.bits.start.data, 13, 0) node _T_1537 = leq(_T_1535, _T_1536) node _T_1538 = mux(new_entry.opa.bits.start.is_acc_addr, _T_1534, _T_1537) node _T_1539 = and(_T_1531, _T_1538) node _T_1540 = eq(entries_ex[12].bits.opb.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_1541 = bits(entries_ex[12].bits.opb.bits.start.data, 11, 0) node _T_1542 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_1543 = lt(_T_1541, _T_1542) node _T_1544 = bits(entries_ex[12].bits.opb.bits.start.data, 13, 0) node _T_1545 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_1546 = lt(_T_1544, _T_1545) node _T_1547 = mux(entries_ex[12].bits.opb.bits.start.is_acc_addr, _T_1543, _T_1546) node _T_1548 = and(_T_1540, _T_1547) node _T_1549 = or(_T_1548, new_entry.opa.bits.wraps_around) node _T_1550 = and(_T_1539, _T_1549) node _T_1551 = or(_T_1530, _T_1550) node _T_1552 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_1553 = and(_T_1552, new_entry.opa.bits.start.read_full_acc_row) node _T_1554 = andr(new_entry.opa.bits.start.data) node _T_1555 = and(_T_1553, _T_1554) node _T_1556 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_1557 = and(_T_1555, _T_1556) node _T_1558 = and(entries_ex[12].bits.opb.bits.start.is_acc_addr, entries_ex[12].bits.opb.bits.start.accumulate) node _T_1559 = and(_T_1558, entries_ex[12].bits.opb.bits.start.read_full_acc_row) node _T_1560 = andr(entries_ex[12].bits.opb.bits.start.data) node _T_1561 = and(_T_1559, _T_1560) node _T_1562 = bits(entries_ex[12].bits.opb.bits.start.garbage_bit, 0, 0) node _T_1563 = and(_T_1561, _T_1562) node _T_1564 = or(_T_1557, _T_1563) node _T_1565 = eq(_T_1564, UInt<1>(0h0)) node _T_1566 = and(_T_1551, _T_1565) node _T_1567 = and(_T_1566, entries_ex[12].bits.opb.valid) node _T_1568 = or(_T_1510, _T_1567) node _T_1569 = and(_T_1453, _T_1568) node _T_1570 = eq(new_entry.is_config, UInt<1>(0h0)) node _T_1571 = and(entries_ex[13].valid, _T_1570) node _T_1572 = eq(entries_ex[13].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_1573 = bits(entries_ex[13].bits.opa.bits.start.data, 11, 0) node _T_1574 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_1575 = leq(_T_1573, _T_1574) node _T_1576 = bits(entries_ex[13].bits.opa.bits.start.data, 13, 0) node _T_1577 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_1578 = leq(_T_1576, _T_1577) node _T_1579 = mux(entries_ex[13].bits.opa.bits.start.is_acc_addr, _T_1575, _T_1578) node _T_1580 = and(_T_1572, _T_1579) node _T_1581 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[13].bits.opa.bits.end.is_acc_addr) node _T_1582 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_1583 = bits(entries_ex[13].bits.opa.bits.end.data, 11, 0) node _T_1584 = lt(_T_1582, _T_1583) node _T_1585 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_1586 = bits(entries_ex[13].bits.opa.bits.end.data, 13, 0) node _T_1587 = lt(_T_1585, _T_1586) node _T_1588 = mux(new_entry.opa.bits.start.is_acc_addr, _T_1584, _T_1587) node _T_1589 = and(_T_1581, _T_1588) node _T_1590 = or(_T_1589, entries_ex[13].bits.opa.bits.wraps_around) node _T_1591 = and(_T_1580, _T_1590) node _T_1592 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[13].bits.opa.bits.start.is_acc_addr) node _T_1593 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_1594 = bits(entries_ex[13].bits.opa.bits.start.data, 11, 0) node _T_1595 = leq(_T_1593, _T_1594) node _T_1596 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_1597 = bits(entries_ex[13].bits.opa.bits.start.data, 13, 0) node _T_1598 = leq(_T_1596, _T_1597) node _T_1599 = mux(new_entry.opa.bits.start.is_acc_addr, _T_1595, _T_1598) node _T_1600 = and(_T_1592, _T_1599) node _T_1601 = eq(entries_ex[13].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_1602 = bits(entries_ex[13].bits.opa.bits.start.data, 11, 0) node _T_1603 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_1604 = lt(_T_1602, _T_1603) node _T_1605 = bits(entries_ex[13].bits.opa.bits.start.data, 13, 0) node _T_1606 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_1607 = lt(_T_1605, _T_1606) node _T_1608 = mux(entries_ex[13].bits.opa.bits.start.is_acc_addr, _T_1604, _T_1607) node _T_1609 = and(_T_1601, _T_1608) node _T_1610 = or(_T_1609, new_entry.opa.bits.wraps_around) node _T_1611 = and(_T_1600, _T_1610) node _T_1612 = or(_T_1591, _T_1611) node _T_1613 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_1614 = and(_T_1613, new_entry.opa.bits.start.read_full_acc_row) node _T_1615 = andr(new_entry.opa.bits.start.data) node _T_1616 = and(_T_1614, _T_1615) node _T_1617 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_1618 = and(_T_1616, _T_1617) node _T_1619 = and(entries_ex[13].bits.opa.bits.start.is_acc_addr, entries_ex[13].bits.opa.bits.start.accumulate) node _T_1620 = and(_T_1619, entries_ex[13].bits.opa.bits.start.read_full_acc_row) node _T_1621 = andr(entries_ex[13].bits.opa.bits.start.data) node _T_1622 = and(_T_1620, _T_1621) node _T_1623 = bits(entries_ex[13].bits.opa.bits.start.garbage_bit, 0, 0) node _T_1624 = and(_T_1622, _T_1623) node _T_1625 = or(_T_1618, _T_1624) node _T_1626 = eq(_T_1625, UInt<1>(0h0)) node _T_1627 = and(_T_1612, _T_1626) node _T_1628 = and(_T_1627, entries_ex[13].bits.opa.valid) node _T_1629 = eq(entries_ex[13].bits.opb.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_1630 = bits(entries_ex[13].bits.opb.bits.start.data, 11, 0) node _T_1631 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_1632 = leq(_T_1630, _T_1631) node _T_1633 = bits(entries_ex[13].bits.opb.bits.start.data, 13, 0) node _T_1634 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_1635 = leq(_T_1633, _T_1634) node _T_1636 = mux(entries_ex[13].bits.opb.bits.start.is_acc_addr, _T_1632, _T_1635) node _T_1637 = and(_T_1629, _T_1636) node _T_1638 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[13].bits.opb.bits.end.is_acc_addr) node _T_1639 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_1640 = bits(entries_ex[13].bits.opb.bits.end.data, 11, 0) node _T_1641 = lt(_T_1639, _T_1640) node _T_1642 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_1643 = bits(entries_ex[13].bits.opb.bits.end.data, 13, 0) node _T_1644 = lt(_T_1642, _T_1643) node _T_1645 = mux(new_entry.opa.bits.start.is_acc_addr, _T_1641, _T_1644) node _T_1646 = and(_T_1638, _T_1645) node _T_1647 = or(_T_1646, entries_ex[13].bits.opb.bits.wraps_around) node _T_1648 = and(_T_1637, _T_1647) node _T_1649 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[13].bits.opb.bits.start.is_acc_addr) node _T_1650 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_1651 = bits(entries_ex[13].bits.opb.bits.start.data, 11, 0) node _T_1652 = leq(_T_1650, _T_1651) node _T_1653 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_1654 = bits(entries_ex[13].bits.opb.bits.start.data, 13, 0) node _T_1655 = leq(_T_1653, _T_1654) node _T_1656 = mux(new_entry.opa.bits.start.is_acc_addr, _T_1652, _T_1655) node _T_1657 = and(_T_1649, _T_1656) node _T_1658 = eq(entries_ex[13].bits.opb.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_1659 = bits(entries_ex[13].bits.opb.bits.start.data, 11, 0) node _T_1660 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_1661 = lt(_T_1659, _T_1660) node _T_1662 = bits(entries_ex[13].bits.opb.bits.start.data, 13, 0) node _T_1663 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_1664 = lt(_T_1662, _T_1663) node _T_1665 = mux(entries_ex[13].bits.opb.bits.start.is_acc_addr, _T_1661, _T_1664) node _T_1666 = and(_T_1658, _T_1665) node _T_1667 = or(_T_1666, new_entry.opa.bits.wraps_around) node _T_1668 = and(_T_1657, _T_1667) node _T_1669 = or(_T_1648, _T_1668) node _T_1670 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_1671 = and(_T_1670, new_entry.opa.bits.start.read_full_acc_row) node _T_1672 = andr(new_entry.opa.bits.start.data) node _T_1673 = and(_T_1671, _T_1672) node _T_1674 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_1675 = and(_T_1673, _T_1674) node _T_1676 = and(entries_ex[13].bits.opb.bits.start.is_acc_addr, entries_ex[13].bits.opb.bits.start.accumulate) node _T_1677 = and(_T_1676, entries_ex[13].bits.opb.bits.start.read_full_acc_row) node _T_1678 = andr(entries_ex[13].bits.opb.bits.start.data) node _T_1679 = and(_T_1677, _T_1678) node _T_1680 = bits(entries_ex[13].bits.opb.bits.start.garbage_bit, 0, 0) node _T_1681 = and(_T_1679, _T_1680) node _T_1682 = or(_T_1675, _T_1681) node _T_1683 = eq(_T_1682, UInt<1>(0h0)) node _T_1684 = and(_T_1669, _T_1683) node _T_1685 = and(_T_1684, entries_ex[13].bits.opb.valid) node _T_1686 = or(_T_1628, _T_1685) node _T_1687 = and(_T_1571, _T_1686) node _T_1688 = eq(new_entry.is_config, UInt<1>(0h0)) node _T_1689 = and(entries_ex[14].valid, _T_1688) node _T_1690 = eq(entries_ex[14].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_1691 = bits(entries_ex[14].bits.opa.bits.start.data, 11, 0) node _T_1692 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_1693 = leq(_T_1691, _T_1692) node _T_1694 = bits(entries_ex[14].bits.opa.bits.start.data, 13, 0) node _T_1695 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_1696 = leq(_T_1694, _T_1695) node _T_1697 = mux(entries_ex[14].bits.opa.bits.start.is_acc_addr, _T_1693, _T_1696) node _T_1698 = and(_T_1690, _T_1697) node _T_1699 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[14].bits.opa.bits.end.is_acc_addr) node _T_1700 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_1701 = bits(entries_ex[14].bits.opa.bits.end.data, 11, 0) node _T_1702 = lt(_T_1700, _T_1701) node _T_1703 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_1704 = bits(entries_ex[14].bits.opa.bits.end.data, 13, 0) node _T_1705 = lt(_T_1703, _T_1704) node _T_1706 = mux(new_entry.opa.bits.start.is_acc_addr, _T_1702, _T_1705) node _T_1707 = and(_T_1699, _T_1706) node _T_1708 = or(_T_1707, entries_ex[14].bits.opa.bits.wraps_around) node _T_1709 = and(_T_1698, _T_1708) node _T_1710 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[14].bits.opa.bits.start.is_acc_addr) node _T_1711 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_1712 = bits(entries_ex[14].bits.opa.bits.start.data, 11, 0) node _T_1713 = leq(_T_1711, _T_1712) node _T_1714 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_1715 = bits(entries_ex[14].bits.opa.bits.start.data, 13, 0) node _T_1716 = leq(_T_1714, _T_1715) node _T_1717 = mux(new_entry.opa.bits.start.is_acc_addr, _T_1713, _T_1716) node _T_1718 = and(_T_1710, _T_1717) node _T_1719 = eq(entries_ex[14].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_1720 = bits(entries_ex[14].bits.opa.bits.start.data, 11, 0) node _T_1721 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_1722 = lt(_T_1720, _T_1721) node _T_1723 = bits(entries_ex[14].bits.opa.bits.start.data, 13, 0) node _T_1724 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_1725 = lt(_T_1723, _T_1724) node _T_1726 = mux(entries_ex[14].bits.opa.bits.start.is_acc_addr, _T_1722, _T_1725) node _T_1727 = and(_T_1719, _T_1726) node _T_1728 = or(_T_1727, new_entry.opa.bits.wraps_around) node _T_1729 = and(_T_1718, _T_1728) node _T_1730 = or(_T_1709, _T_1729) node _T_1731 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_1732 = and(_T_1731, new_entry.opa.bits.start.read_full_acc_row) node _T_1733 = andr(new_entry.opa.bits.start.data) node _T_1734 = and(_T_1732, _T_1733) node _T_1735 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_1736 = and(_T_1734, _T_1735) node _T_1737 = and(entries_ex[14].bits.opa.bits.start.is_acc_addr, entries_ex[14].bits.opa.bits.start.accumulate) node _T_1738 = and(_T_1737, entries_ex[14].bits.opa.bits.start.read_full_acc_row) node _T_1739 = andr(entries_ex[14].bits.opa.bits.start.data) node _T_1740 = and(_T_1738, _T_1739) node _T_1741 = bits(entries_ex[14].bits.opa.bits.start.garbage_bit, 0, 0) node _T_1742 = and(_T_1740, _T_1741) node _T_1743 = or(_T_1736, _T_1742) node _T_1744 = eq(_T_1743, UInt<1>(0h0)) node _T_1745 = and(_T_1730, _T_1744) node _T_1746 = and(_T_1745, entries_ex[14].bits.opa.valid) node _T_1747 = eq(entries_ex[14].bits.opb.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_1748 = bits(entries_ex[14].bits.opb.bits.start.data, 11, 0) node _T_1749 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_1750 = leq(_T_1748, _T_1749) node _T_1751 = bits(entries_ex[14].bits.opb.bits.start.data, 13, 0) node _T_1752 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_1753 = leq(_T_1751, _T_1752) node _T_1754 = mux(entries_ex[14].bits.opb.bits.start.is_acc_addr, _T_1750, _T_1753) node _T_1755 = and(_T_1747, _T_1754) node _T_1756 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[14].bits.opb.bits.end.is_acc_addr) node _T_1757 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_1758 = bits(entries_ex[14].bits.opb.bits.end.data, 11, 0) node _T_1759 = lt(_T_1757, _T_1758) node _T_1760 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_1761 = bits(entries_ex[14].bits.opb.bits.end.data, 13, 0) node _T_1762 = lt(_T_1760, _T_1761) node _T_1763 = mux(new_entry.opa.bits.start.is_acc_addr, _T_1759, _T_1762) node _T_1764 = and(_T_1756, _T_1763) node _T_1765 = or(_T_1764, entries_ex[14].bits.opb.bits.wraps_around) node _T_1766 = and(_T_1755, _T_1765) node _T_1767 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[14].bits.opb.bits.start.is_acc_addr) node _T_1768 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_1769 = bits(entries_ex[14].bits.opb.bits.start.data, 11, 0) node _T_1770 = leq(_T_1768, _T_1769) node _T_1771 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_1772 = bits(entries_ex[14].bits.opb.bits.start.data, 13, 0) node _T_1773 = leq(_T_1771, _T_1772) node _T_1774 = mux(new_entry.opa.bits.start.is_acc_addr, _T_1770, _T_1773) node _T_1775 = and(_T_1767, _T_1774) node _T_1776 = eq(entries_ex[14].bits.opb.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_1777 = bits(entries_ex[14].bits.opb.bits.start.data, 11, 0) node _T_1778 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_1779 = lt(_T_1777, _T_1778) node _T_1780 = bits(entries_ex[14].bits.opb.bits.start.data, 13, 0) node _T_1781 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_1782 = lt(_T_1780, _T_1781) node _T_1783 = mux(entries_ex[14].bits.opb.bits.start.is_acc_addr, _T_1779, _T_1782) node _T_1784 = and(_T_1776, _T_1783) node _T_1785 = or(_T_1784, new_entry.opa.bits.wraps_around) node _T_1786 = and(_T_1775, _T_1785) node _T_1787 = or(_T_1766, _T_1786) node _T_1788 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_1789 = and(_T_1788, new_entry.opa.bits.start.read_full_acc_row) node _T_1790 = andr(new_entry.opa.bits.start.data) node _T_1791 = and(_T_1789, _T_1790) node _T_1792 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_1793 = and(_T_1791, _T_1792) node _T_1794 = and(entries_ex[14].bits.opb.bits.start.is_acc_addr, entries_ex[14].bits.opb.bits.start.accumulate) node _T_1795 = and(_T_1794, entries_ex[14].bits.opb.bits.start.read_full_acc_row) node _T_1796 = andr(entries_ex[14].bits.opb.bits.start.data) node _T_1797 = and(_T_1795, _T_1796) node _T_1798 = bits(entries_ex[14].bits.opb.bits.start.garbage_bit, 0, 0) node _T_1799 = and(_T_1797, _T_1798) node _T_1800 = or(_T_1793, _T_1799) node _T_1801 = eq(_T_1800, UInt<1>(0h0)) node _T_1802 = and(_T_1787, _T_1801) node _T_1803 = and(_T_1802, entries_ex[14].bits.opb.valid) node _T_1804 = or(_T_1746, _T_1803) node _T_1805 = and(_T_1689, _T_1804) node _T_1806 = eq(new_entry.is_config, UInt<1>(0h0)) node _T_1807 = and(entries_ex[15].valid, _T_1806) node _T_1808 = eq(entries_ex[15].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_1809 = bits(entries_ex[15].bits.opa.bits.start.data, 11, 0) node _T_1810 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_1811 = leq(_T_1809, _T_1810) node _T_1812 = bits(entries_ex[15].bits.opa.bits.start.data, 13, 0) node _T_1813 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_1814 = leq(_T_1812, _T_1813) node _T_1815 = mux(entries_ex[15].bits.opa.bits.start.is_acc_addr, _T_1811, _T_1814) node _T_1816 = and(_T_1808, _T_1815) node _T_1817 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[15].bits.opa.bits.end.is_acc_addr) node _T_1818 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_1819 = bits(entries_ex[15].bits.opa.bits.end.data, 11, 0) node _T_1820 = lt(_T_1818, _T_1819) node _T_1821 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_1822 = bits(entries_ex[15].bits.opa.bits.end.data, 13, 0) node _T_1823 = lt(_T_1821, _T_1822) node _T_1824 = mux(new_entry.opa.bits.start.is_acc_addr, _T_1820, _T_1823) node _T_1825 = and(_T_1817, _T_1824) node _T_1826 = or(_T_1825, entries_ex[15].bits.opa.bits.wraps_around) node _T_1827 = and(_T_1816, _T_1826) node _T_1828 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[15].bits.opa.bits.start.is_acc_addr) node _T_1829 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_1830 = bits(entries_ex[15].bits.opa.bits.start.data, 11, 0) node _T_1831 = leq(_T_1829, _T_1830) node _T_1832 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_1833 = bits(entries_ex[15].bits.opa.bits.start.data, 13, 0) node _T_1834 = leq(_T_1832, _T_1833) node _T_1835 = mux(new_entry.opa.bits.start.is_acc_addr, _T_1831, _T_1834) node _T_1836 = and(_T_1828, _T_1835) node _T_1837 = eq(entries_ex[15].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_1838 = bits(entries_ex[15].bits.opa.bits.start.data, 11, 0) node _T_1839 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_1840 = lt(_T_1838, _T_1839) node _T_1841 = bits(entries_ex[15].bits.opa.bits.start.data, 13, 0) node _T_1842 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_1843 = lt(_T_1841, _T_1842) node _T_1844 = mux(entries_ex[15].bits.opa.bits.start.is_acc_addr, _T_1840, _T_1843) node _T_1845 = and(_T_1837, _T_1844) node _T_1846 = or(_T_1845, new_entry.opa.bits.wraps_around) node _T_1847 = and(_T_1836, _T_1846) node _T_1848 = or(_T_1827, _T_1847) node _T_1849 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_1850 = and(_T_1849, new_entry.opa.bits.start.read_full_acc_row) node _T_1851 = andr(new_entry.opa.bits.start.data) node _T_1852 = and(_T_1850, _T_1851) node _T_1853 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_1854 = and(_T_1852, _T_1853) node _T_1855 = and(entries_ex[15].bits.opa.bits.start.is_acc_addr, entries_ex[15].bits.opa.bits.start.accumulate) node _T_1856 = and(_T_1855, entries_ex[15].bits.opa.bits.start.read_full_acc_row) node _T_1857 = andr(entries_ex[15].bits.opa.bits.start.data) node _T_1858 = and(_T_1856, _T_1857) node _T_1859 = bits(entries_ex[15].bits.opa.bits.start.garbage_bit, 0, 0) node _T_1860 = and(_T_1858, _T_1859) node _T_1861 = or(_T_1854, _T_1860) node _T_1862 = eq(_T_1861, UInt<1>(0h0)) node _T_1863 = and(_T_1848, _T_1862) node _T_1864 = and(_T_1863, entries_ex[15].bits.opa.valid) node _T_1865 = eq(entries_ex[15].bits.opb.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_1866 = bits(entries_ex[15].bits.opb.bits.start.data, 11, 0) node _T_1867 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_1868 = leq(_T_1866, _T_1867) node _T_1869 = bits(entries_ex[15].bits.opb.bits.start.data, 13, 0) node _T_1870 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_1871 = leq(_T_1869, _T_1870) node _T_1872 = mux(entries_ex[15].bits.opb.bits.start.is_acc_addr, _T_1868, _T_1871) node _T_1873 = and(_T_1865, _T_1872) node _T_1874 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[15].bits.opb.bits.end.is_acc_addr) node _T_1875 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_1876 = bits(entries_ex[15].bits.opb.bits.end.data, 11, 0) node _T_1877 = lt(_T_1875, _T_1876) node _T_1878 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_1879 = bits(entries_ex[15].bits.opb.bits.end.data, 13, 0) node _T_1880 = lt(_T_1878, _T_1879) node _T_1881 = mux(new_entry.opa.bits.start.is_acc_addr, _T_1877, _T_1880) node _T_1882 = and(_T_1874, _T_1881) node _T_1883 = or(_T_1882, entries_ex[15].bits.opb.bits.wraps_around) node _T_1884 = and(_T_1873, _T_1883) node _T_1885 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[15].bits.opb.bits.start.is_acc_addr) node _T_1886 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_1887 = bits(entries_ex[15].bits.opb.bits.start.data, 11, 0) node _T_1888 = leq(_T_1886, _T_1887) node _T_1889 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_1890 = bits(entries_ex[15].bits.opb.bits.start.data, 13, 0) node _T_1891 = leq(_T_1889, _T_1890) node _T_1892 = mux(new_entry.opa.bits.start.is_acc_addr, _T_1888, _T_1891) node _T_1893 = and(_T_1885, _T_1892) node _T_1894 = eq(entries_ex[15].bits.opb.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_1895 = bits(entries_ex[15].bits.opb.bits.start.data, 11, 0) node _T_1896 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_1897 = lt(_T_1895, _T_1896) node _T_1898 = bits(entries_ex[15].bits.opb.bits.start.data, 13, 0) node _T_1899 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_1900 = lt(_T_1898, _T_1899) node _T_1901 = mux(entries_ex[15].bits.opb.bits.start.is_acc_addr, _T_1897, _T_1900) node _T_1902 = and(_T_1894, _T_1901) node _T_1903 = or(_T_1902, new_entry.opa.bits.wraps_around) node _T_1904 = and(_T_1893, _T_1903) node _T_1905 = or(_T_1884, _T_1904) node _T_1906 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_1907 = and(_T_1906, new_entry.opa.bits.start.read_full_acc_row) node _T_1908 = andr(new_entry.opa.bits.start.data) node _T_1909 = and(_T_1907, _T_1908) node _T_1910 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_1911 = and(_T_1909, _T_1910) node _T_1912 = and(entries_ex[15].bits.opb.bits.start.is_acc_addr, entries_ex[15].bits.opb.bits.start.accumulate) node _T_1913 = and(_T_1912, entries_ex[15].bits.opb.bits.start.read_full_acc_row) node _T_1914 = andr(entries_ex[15].bits.opb.bits.start.data) node _T_1915 = and(_T_1913, _T_1914) node _T_1916 = bits(entries_ex[15].bits.opb.bits.start.garbage_bit, 0, 0) node _T_1917 = and(_T_1915, _T_1916) node _T_1918 = or(_T_1911, _T_1917) node _T_1919 = eq(_T_1918, UInt<1>(0h0)) node _T_1920 = and(_T_1905, _T_1919) node _T_1921 = and(_T_1920, entries_ex[15].bits.opb.valid) node _T_1922 = or(_T_1864, _T_1921) node _T_1923 = and(_T_1807, _T_1922) wire _WIRE_1 : UInt<1>[16] connect _WIRE_1[0], _T_153 connect _WIRE_1[1], _T_271 connect _WIRE_1[2], _T_389 connect _WIRE_1[3], _T_507 connect _WIRE_1[4], _T_625 connect _WIRE_1[5], _T_743 connect _WIRE_1[6], _T_861 connect _WIRE_1[7], _T_979 connect _WIRE_1[8], _T_1097 connect _WIRE_1[9], _T_1215 connect _WIRE_1[10], _T_1333 connect _WIRE_1[11], _T_1451 connect _WIRE_1[12], _T_1569 connect _WIRE_1[13], _T_1687 connect _WIRE_1[14], _T_1805 connect _WIRE_1[15], _T_1923 connect new_entry.deps_ex, _WIRE_1 node _T_1924 = and(entries_st[0].valid, entries_st[0].bits.opa.valid) node _T_1925 = and(_T_1924, not_config) node _T_1926 = eq(entries_st[0].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_1927 = bits(entries_st[0].bits.opa.bits.start.data, 11, 0) node _T_1928 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_1929 = leq(_T_1927, _T_1928) node _T_1930 = bits(entries_st[0].bits.opa.bits.start.data, 13, 0) node _T_1931 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_1932 = leq(_T_1930, _T_1931) node _T_1933 = mux(entries_st[0].bits.opa.bits.start.is_acc_addr, _T_1929, _T_1932) node _T_1934 = and(_T_1926, _T_1933) node _T_1935 = eq(new_entry.opa.bits.start.is_acc_addr, entries_st[0].bits.opa.bits.end.is_acc_addr) node _T_1936 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_1937 = bits(entries_st[0].bits.opa.bits.end.data, 11, 0) node _T_1938 = lt(_T_1936, _T_1937) node _T_1939 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_1940 = bits(entries_st[0].bits.opa.bits.end.data, 13, 0) node _T_1941 = lt(_T_1939, _T_1940) node _T_1942 = mux(new_entry.opa.bits.start.is_acc_addr, _T_1938, _T_1941) node _T_1943 = and(_T_1935, _T_1942) node _T_1944 = or(_T_1943, entries_st[0].bits.opa.bits.wraps_around) node _T_1945 = and(_T_1934, _T_1944) node _T_1946 = eq(new_entry.opa.bits.start.is_acc_addr, entries_st[0].bits.opa.bits.start.is_acc_addr) node _T_1947 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_1948 = bits(entries_st[0].bits.opa.bits.start.data, 11, 0) node _T_1949 = leq(_T_1947, _T_1948) node _T_1950 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_1951 = bits(entries_st[0].bits.opa.bits.start.data, 13, 0) node _T_1952 = leq(_T_1950, _T_1951) node _T_1953 = mux(new_entry.opa.bits.start.is_acc_addr, _T_1949, _T_1952) node _T_1954 = and(_T_1946, _T_1953) node _T_1955 = eq(entries_st[0].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_1956 = bits(entries_st[0].bits.opa.bits.start.data, 11, 0) node _T_1957 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_1958 = lt(_T_1956, _T_1957) node _T_1959 = bits(entries_st[0].bits.opa.bits.start.data, 13, 0) node _T_1960 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_1961 = lt(_T_1959, _T_1960) node _T_1962 = mux(entries_st[0].bits.opa.bits.start.is_acc_addr, _T_1958, _T_1961) node _T_1963 = and(_T_1955, _T_1962) node _T_1964 = or(_T_1963, new_entry.opa.bits.wraps_around) node _T_1965 = and(_T_1954, _T_1964) node _T_1966 = or(_T_1945, _T_1965) node _T_1967 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_1968 = and(_T_1967, new_entry.opa.bits.start.read_full_acc_row) node _T_1969 = andr(new_entry.opa.bits.start.data) node _T_1970 = and(_T_1968, _T_1969) node _T_1971 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_1972 = and(_T_1970, _T_1971) node _T_1973 = and(entries_st[0].bits.opa.bits.start.is_acc_addr, entries_st[0].bits.opa.bits.start.accumulate) node _T_1974 = and(_T_1973, entries_st[0].bits.opa.bits.start.read_full_acc_row) node _T_1975 = andr(entries_st[0].bits.opa.bits.start.data) node _T_1976 = and(_T_1974, _T_1975) node _T_1977 = bits(entries_st[0].bits.opa.bits.start.garbage_bit, 0, 0) node _T_1978 = and(_T_1976, _T_1977) node _T_1979 = or(_T_1972, _T_1978) node _T_1980 = eq(_T_1979, UInt<1>(0h0)) node _T_1981 = and(_T_1966, _T_1980) node _T_1982 = and(_T_1925, _T_1981) node _T_1983 = and(entries_st[1].valid, entries_st[1].bits.opa.valid) node _T_1984 = and(_T_1983, not_config) node _T_1985 = eq(entries_st[1].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_1986 = bits(entries_st[1].bits.opa.bits.start.data, 11, 0) node _T_1987 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_1988 = leq(_T_1986, _T_1987) node _T_1989 = bits(entries_st[1].bits.opa.bits.start.data, 13, 0) node _T_1990 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_1991 = leq(_T_1989, _T_1990) node _T_1992 = mux(entries_st[1].bits.opa.bits.start.is_acc_addr, _T_1988, _T_1991) node _T_1993 = and(_T_1985, _T_1992) node _T_1994 = eq(new_entry.opa.bits.start.is_acc_addr, entries_st[1].bits.opa.bits.end.is_acc_addr) node _T_1995 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_1996 = bits(entries_st[1].bits.opa.bits.end.data, 11, 0) node _T_1997 = lt(_T_1995, _T_1996) node _T_1998 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_1999 = bits(entries_st[1].bits.opa.bits.end.data, 13, 0) node _T_2000 = lt(_T_1998, _T_1999) node _T_2001 = mux(new_entry.opa.bits.start.is_acc_addr, _T_1997, _T_2000) node _T_2002 = and(_T_1994, _T_2001) node _T_2003 = or(_T_2002, entries_st[1].bits.opa.bits.wraps_around) node _T_2004 = and(_T_1993, _T_2003) node _T_2005 = eq(new_entry.opa.bits.start.is_acc_addr, entries_st[1].bits.opa.bits.start.is_acc_addr) node _T_2006 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_2007 = bits(entries_st[1].bits.opa.bits.start.data, 11, 0) node _T_2008 = leq(_T_2006, _T_2007) node _T_2009 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_2010 = bits(entries_st[1].bits.opa.bits.start.data, 13, 0) node _T_2011 = leq(_T_2009, _T_2010) node _T_2012 = mux(new_entry.opa.bits.start.is_acc_addr, _T_2008, _T_2011) node _T_2013 = and(_T_2005, _T_2012) node _T_2014 = eq(entries_st[1].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_2015 = bits(entries_st[1].bits.opa.bits.start.data, 11, 0) node _T_2016 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_2017 = lt(_T_2015, _T_2016) node _T_2018 = bits(entries_st[1].bits.opa.bits.start.data, 13, 0) node _T_2019 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_2020 = lt(_T_2018, _T_2019) node _T_2021 = mux(entries_st[1].bits.opa.bits.start.is_acc_addr, _T_2017, _T_2020) node _T_2022 = and(_T_2014, _T_2021) node _T_2023 = or(_T_2022, new_entry.opa.bits.wraps_around) node _T_2024 = and(_T_2013, _T_2023) node _T_2025 = or(_T_2004, _T_2024) node _T_2026 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_2027 = and(_T_2026, new_entry.opa.bits.start.read_full_acc_row) node _T_2028 = andr(new_entry.opa.bits.start.data) node _T_2029 = and(_T_2027, _T_2028) node _T_2030 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_2031 = and(_T_2029, _T_2030) node _T_2032 = and(entries_st[1].bits.opa.bits.start.is_acc_addr, entries_st[1].bits.opa.bits.start.accumulate) node _T_2033 = and(_T_2032, entries_st[1].bits.opa.bits.start.read_full_acc_row) node _T_2034 = andr(entries_st[1].bits.opa.bits.start.data) node _T_2035 = and(_T_2033, _T_2034) node _T_2036 = bits(entries_st[1].bits.opa.bits.start.garbage_bit, 0, 0) node _T_2037 = and(_T_2035, _T_2036) node _T_2038 = or(_T_2031, _T_2037) node _T_2039 = eq(_T_2038, UInt<1>(0h0)) node _T_2040 = and(_T_2025, _T_2039) node _T_2041 = and(_T_1984, _T_2040) node _T_2042 = and(entries_st[2].valid, entries_st[2].bits.opa.valid) node _T_2043 = and(_T_2042, not_config) node _T_2044 = eq(entries_st[2].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_2045 = bits(entries_st[2].bits.opa.bits.start.data, 11, 0) node _T_2046 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_2047 = leq(_T_2045, _T_2046) node _T_2048 = bits(entries_st[2].bits.opa.bits.start.data, 13, 0) node _T_2049 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_2050 = leq(_T_2048, _T_2049) node _T_2051 = mux(entries_st[2].bits.opa.bits.start.is_acc_addr, _T_2047, _T_2050) node _T_2052 = and(_T_2044, _T_2051) node _T_2053 = eq(new_entry.opa.bits.start.is_acc_addr, entries_st[2].bits.opa.bits.end.is_acc_addr) node _T_2054 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_2055 = bits(entries_st[2].bits.opa.bits.end.data, 11, 0) node _T_2056 = lt(_T_2054, _T_2055) node _T_2057 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_2058 = bits(entries_st[2].bits.opa.bits.end.data, 13, 0) node _T_2059 = lt(_T_2057, _T_2058) node _T_2060 = mux(new_entry.opa.bits.start.is_acc_addr, _T_2056, _T_2059) node _T_2061 = and(_T_2053, _T_2060) node _T_2062 = or(_T_2061, entries_st[2].bits.opa.bits.wraps_around) node _T_2063 = and(_T_2052, _T_2062) node _T_2064 = eq(new_entry.opa.bits.start.is_acc_addr, entries_st[2].bits.opa.bits.start.is_acc_addr) node _T_2065 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_2066 = bits(entries_st[2].bits.opa.bits.start.data, 11, 0) node _T_2067 = leq(_T_2065, _T_2066) node _T_2068 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_2069 = bits(entries_st[2].bits.opa.bits.start.data, 13, 0) node _T_2070 = leq(_T_2068, _T_2069) node _T_2071 = mux(new_entry.opa.bits.start.is_acc_addr, _T_2067, _T_2070) node _T_2072 = and(_T_2064, _T_2071) node _T_2073 = eq(entries_st[2].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_2074 = bits(entries_st[2].bits.opa.bits.start.data, 11, 0) node _T_2075 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_2076 = lt(_T_2074, _T_2075) node _T_2077 = bits(entries_st[2].bits.opa.bits.start.data, 13, 0) node _T_2078 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_2079 = lt(_T_2077, _T_2078) node _T_2080 = mux(entries_st[2].bits.opa.bits.start.is_acc_addr, _T_2076, _T_2079) node _T_2081 = and(_T_2073, _T_2080) node _T_2082 = or(_T_2081, new_entry.opa.bits.wraps_around) node _T_2083 = and(_T_2072, _T_2082) node _T_2084 = or(_T_2063, _T_2083) node _T_2085 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_2086 = and(_T_2085, new_entry.opa.bits.start.read_full_acc_row) node _T_2087 = andr(new_entry.opa.bits.start.data) node _T_2088 = and(_T_2086, _T_2087) node _T_2089 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_2090 = and(_T_2088, _T_2089) node _T_2091 = and(entries_st[2].bits.opa.bits.start.is_acc_addr, entries_st[2].bits.opa.bits.start.accumulate) node _T_2092 = and(_T_2091, entries_st[2].bits.opa.bits.start.read_full_acc_row) node _T_2093 = andr(entries_st[2].bits.opa.bits.start.data) node _T_2094 = and(_T_2092, _T_2093) node _T_2095 = bits(entries_st[2].bits.opa.bits.start.garbage_bit, 0, 0) node _T_2096 = and(_T_2094, _T_2095) node _T_2097 = or(_T_2090, _T_2096) node _T_2098 = eq(_T_2097, UInt<1>(0h0)) node _T_2099 = and(_T_2084, _T_2098) node _T_2100 = and(_T_2043, _T_2099) node _T_2101 = and(entries_st[3].valid, entries_st[3].bits.opa.valid) node _T_2102 = and(_T_2101, not_config) node _T_2103 = eq(entries_st[3].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_2104 = bits(entries_st[3].bits.opa.bits.start.data, 11, 0) node _T_2105 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_2106 = leq(_T_2104, _T_2105) node _T_2107 = bits(entries_st[3].bits.opa.bits.start.data, 13, 0) node _T_2108 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_2109 = leq(_T_2107, _T_2108) node _T_2110 = mux(entries_st[3].bits.opa.bits.start.is_acc_addr, _T_2106, _T_2109) node _T_2111 = and(_T_2103, _T_2110) node _T_2112 = eq(new_entry.opa.bits.start.is_acc_addr, entries_st[3].bits.opa.bits.end.is_acc_addr) node _T_2113 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_2114 = bits(entries_st[3].bits.opa.bits.end.data, 11, 0) node _T_2115 = lt(_T_2113, _T_2114) node _T_2116 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_2117 = bits(entries_st[3].bits.opa.bits.end.data, 13, 0) node _T_2118 = lt(_T_2116, _T_2117) node _T_2119 = mux(new_entry.opa.bits.start.is_acc_addr, _T_2115, _T_2118) node _T_2120 = and(_T_2112, _T_2119) node _T_2121 = or(_T_2120, entries_st[3].bits.opa.bits.wraps_around) node _T_2122 = and(_T_2111, _T_2121) node _T_2123 = eq(new_entry.opa.bits.start.is_acc_addr, entries_st[3].bits.opa.bits.start.is_acc_addr) node _T_2124 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_2125 = bits(entries_st[3].bits.opa.bits.start.data, 11, 0) node _T_2126 = leq(_T_2124, _T_2125) node _T_2127 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_2128 = bits(entries_st[3].bits.opa.bits.start.data, 13, 0) node _T_2129 = leq(_T_2127, _T_2128) node _T_2130 = mux(new_entry.opa.bits.start.is_acc_addr, _T_2126, _T_2129) node _T_2131 = and(_T_2123, _T_2130) node _T_2132 = eq(entries_st[3].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_2133 = bits(entries_st[3].bits.opa.bits.start.data, 11, 0) node _T_2134 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_2135 = lt(_T_2133, _T_2134) node _T_2136 = bits(entries_st[3].bits.opa.bits.start.data, 13, 0) node _T_2137 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_2138 = lt(_T_2136, _T_2137) node _T_2139 = mux(entries_st[3].bits.opa.bits.start.is_acc_addr, _T_2135, _T_2138) node _T_2140 = and(_T_2132, _T_2139) node _T_2141 = or(_T_2140, new_entry.opa.bits.wraps_around) node _T_2142 = and(_T_2131, _T_2141) node _T_2143 = or(_T_2122, _T_2142) node _T_2144 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_2145 = and(_T_2144, new_entry.opa.bits.start.read_full_acc_row) node _T_2146 = andr(new_entry.opa.bits.start.data) node _T_2147 = and(_T_2145, _T_2146) node _T_2148 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_2149 = and(_T_2147, _T_2148) node _T_2150 = and(entries_st[3].bits.opa.bits.start.is_acc_addr, entries_st[3].bits.opa.bits.start.accumulate) node _T_2151 = and(_T_2150, entries_st[3].bits.opa.bits.start.read_full_acc_row) node _T_2152 = andr(entries_st[3].bits.opa.bits.start.data) node _T_2153 = and(_T_2151, _T_2152) node _T_2154 = bits(entries_st[3].bits.opa.bits.start.garbage_bit, 0, 0) node _T_2155 = and(_T_2153, _T_2154) node _T_2156 = or(_T_2149, _T_2155) node _T_2157 = eq(_T_2156, UInt<1>(0h0)) node _T_2158 = and(_T_2143, _T_2157) node _T_2159 = and(_T_2102, _T_2158) wire _WIRE_2 : UInt<1>[4] connect _WIRE_2[0], _T_1982 connect _WIRE_2[1], _T_2041 connect _WIRE_2[2], _T_2100 connect _WIRE_2[3], _T_2159 connect new_entry.deps_st, _WIRE_2 else : when is_ex : node _T_2160 = and(entries_ld[0].valid, entries_ld[0].bits.opa.valid) node _T_2161 = and(_T_2160, not_config) node _T_2162 = eq(entries_ld[0].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_2163 = bits(entries_ld[0].bits.opa.bits.start.data, 11, 0) node _T_2164 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_2165 = leq(_T_2163, _T_2164) node _T_2166 = bits(entries_ld[0].bits.opa.bits.start.data, 13, 0) node _T_2167 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_2168 = leq(_T_2166, _T_2167) node _T_2169 = mux(entries_ld[0].bits.opa.bits.start.is_acc_addr, _T_2165, _T_2168) node _T_2170 = and(_T_2162, _T_2169) node _T_2171 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ld[0].bits.opa.bits.end.is_acc_addr) node _T_2172 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_2173 = bits(entries_ld[0].bits.opa.bits.end.data, 11, 0) node _T_2174 = lt(_T_2172, _T_2173) node _T_2175 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_2176 = bits(entries_ld[0].bits.opa.bits.end.data, 13, 0) node _T_2177 = lt(_T_2175, _T_2176) node _T_2178 = mux(new_entry.opa.bits.start.is_acc_addr, _T_2174, _T_2177) node _T_2179 = and(_T_2171, _T_2178) node _T_2180 = or(_T_2179, entries_ld[0].bits.opa.bits.wraps_around) node _T_2181 = and(_T_2170, _T_2180) node _T_2182 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ld[0].bits.opa.bits.start.is_acc_addr) node _T_2183 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_2184 = bits(entries_ld[0].bits.opa.bits.start.data, 11, 0) node _T_2185 = leq(_T_2183, _T_2184) node _T_2186 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_2187 = bits(entries_ld[0].bits.opa.bits.start.data, 13, 0) node _T_2188 = leq(_T_2186, _T_2187) node _T_2189 = mux(new_entry.opa.bits.start.is_acc_addr, _T_2185, _T_2188) node _T_2190 = and(_T_2182, _T_2189) node _T_2191 = eq(entries_ld[0].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_2192 = bits(entries_ld[0].bits.opa.bits.start.data, 11, 0) node _T_2193 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_2194 = lt(_T_2192, _T_2193) node _T_2195 = bits(entries_ld[0].bits.opa.bits.start.data, 13, 0) node _T_2196 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_2197 = lt(_T_2195, _T_2196) node _T_2198 = mux(entries_ld[0].bits.opa.bits.start.is_acc_addr, _T_2194, _T_2197) node _T_2199 = and(_T_2191, _T_2198) node _T_2200 = or(_T_2199, new_entry.opa.bits.wraps_around) node _T_2201 = and(_T_2190, _T_2200) node _T_2202 = or(_T_2181, _T_2201) node _T_2203 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_2204 = and(_T_2203, new_entry.opa.bits.start.read_full_acc_row) node _T_2205 = andr(new_entry.opa.bits.start.data) node _T_2206 = and(_T_2204, _T_2205) node _T_2207 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_2208 = and(_T_2206, _T_2207) node _T_2209 = and(entries_ld[0].bits.opa.bits.start.is_acc_addr, entries_ld[0].bits.opa.bits.start.accumulate) node _T_2210 = and(_T_2209, entries_ld[0].bits.opa.bits.start.read_full_acc_row) node _T_2211 = andr(entries_ld[0].bits.opa.bits.start.data) node _T_2212 = and(_T_2210, _T_2211) node _T_2213 = bits(entries_ld[0].bits.opa.bits.start.garbage_bit, 0, 0) node _T_2214 = and(_T_2212, _T_2213) node _T_2215 = or(_T_2208, _T_2214) node _T_2216 = eq(_T_2215, UInt<1>(0h0)) node _T_2217 = and(_T_2202, _T_2216) node _T_2218 = eq(entries_ld[0].bits.opa.bits.start.is_acc_addr, new_entry.opb.bits.start.is_acc_addr) node _T_2219 = bits(entries_ld[0].bits.opa.bits.start.data, 11, 0) node _T_2220 = bits(new_entry.opb.bits.start.data, 11, 0) node _T_2221 = leq(_T_2219, _T_2220) node _T_2222 = bits(entries_ld[0].bits.opa.bits.start.data, 13, 0) node _T_2223 = bits(new_entry.opb.bits.start.data, 13, 0) node _T_2224 = leq(_T_2222, _T_2223) node _T_2225 = mux(entries_ld[0].bits.opa.bits.start.is_acc_addr, _T_2221, _T_2224) node _T_2226 = and(_T_2218, _T_2225) node _T_2227 = eq(new_entry.opb.bits.start.is_acc_addr, entries_ld[0].bits.opa.bits.end.is_acc_addr) node _T_2228 = bits(new_entry.opb.bits.start.data, 11, 0) node _T_2229 = bits(entries_ld[0].bits.opa.bits.end.data, 11, 0) node _T_2230 = lt(_T_2228, _T_2229) node _T_2231 = bits(new_entry.opb.bits.start.data, 13, 0) node _T_2232 = bits(entries_ld[0].bits.opa.bits.end.data, 13, 0) node _T_2233 = lt(_T_2231, _T_2232) node _T_2234 = mux(new_entry.opb.bits.start.is_acc_addr, _T_2230, _T_2233) node _T_2235 = and(_T_2227, _T_2234) node _T_2236 = or(_T_2235, entries_ld[0].bits.opa.bits.wraps_around) node _T_2237 = and(_T_2226, _T_2236) node _T_2238 = eq(new_entry.opb.bits.start.is_acc_addr, entries_ld[0].bits.opa.bits.start.is_acc_addr) node _T_2239 = bits(new_entry.opb.bits.start.data, 11, 0) node _T_2240 = bits(entries_ld[0].bits.opa.bits.start.data, 11, 0) node _T_2241 = leq(_T_2239, _T_2240) node _T_2242 = bits(new_entry.opb.bits.start.data, 13, 0) node _T_2243 = bits(entries_ld[0].bits.opa.bits.start.data, 13, 0) node _T_2244 = leq(_T_2242, _T_2243) node _T_2245 = mux(new_entry.opb.bits.start.is_acc_addr, _T_2241, _T_2244) node _T_2246 = and(_T_2238, _T_2245) node _T_2247 = eq(entries_ld[0].bits.opa.bits.start.is_acc_addr, new_entry.opb.bits.end.is_acc_addr) node _T_2248 = bits(entries_ld[0].bits.opa.bits.start.data, 11, 0) node _T_2249 = bits(new_entry.opb.bits.end.data, 11, 0) node _T_2250 = lt(_T_2248, _T_2249) node _T_2251 = bits(entries_ld[0].bits.opa.bits.start.data, 13, 0) node _T_2252 = bits(new_entry.opb.bits.end.data, 13, 0) node _T_2253 = lt(_T_2251, _T_2252) node _T_2254 = mux(entries_ld[0].bits.opa.bits.start.is_acc_addr, _T_2250, _T_2253) node _T_2255 = and(_T_2247, _T_2254) node _T_2256 = or(_T_2255, new_entry.opb.bits.wraps_around) node _T_2257 = and(_T_2246, _T_2256) node _T_2258 = or(_T_2237, _T_2257) node _T_2259 = and(new_entry.opb.bits.start.is_acc_addr, new_entry.opb.bits.start.accumulate) node _T_2260 = and(_T_2259, new_entry.opb.bits.start.read_full_acc_row) node _T_2261 = andr(new_entry.opb.bits.start.data) node _T_2262 = and(_T_2260, _T_2261) node _T_2263 = bits(new_entry.opb.bits.start.garbage_bit, 0, 0) node _T_2264 = and(_T_2262, _T_2263) node _T_2265 = and(entries_ld[0].bits.opa.bits.start.is_acc_addr, entries_ld[0].bits.opa.bits.start.accumulate) node _T_2266 = and(_T_2265, entries_ld[0].bits.opa.bits.start.read_full_acc_row) node _T_2267 = andr(entries_ld[0].bits.opa.bits.start.data) node _T_2268 = and(_T_2266, _T_2267) node _T_2269 = bits(entries_ld[0].bits.opa.bits.start.garbage_bit, 0, 0) node _T_2270 = and(_T_2268, _T_2269) node _T_2271 = or(_T_2264, _T_2270) node _T_2272 = eq(_T_2271, UInt<1>(0h0)) node _T_2273 = and(_T_2258, _T_2272) node _T_2274 = or(_T_2217, _T_2273) node _T_2275 = and(_T_2161, _T_2274) node _T_2276 = and(entries_ld[1].valid, entries_ld[1].bits.opa.valid) node _T_2277 = and(_T_2276, not_config) node _T_2278 = eq(entries_ld[1].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_2279 = bits(entries_ld[1].bits.opa.bits.start.data, 11, 0) node _T_2280 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_2281 = leq(_T_2279, _T_2280) node _T_2282 = bits(entries_ld[1].bits.opa.bits.start.data, 13, 0) node _T_2283 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_2284 = leq(_T_2282, _T_2283) node _T_2285 = mux(entries_ld[1].bits.opa.bits.start.is_acc_addr, _T_2281, _T_2284) node _T_2286 = and(_T_2278, _T_2285) node _T_2287 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ld[1].bits.opa.bits.end.is_acc_addr) node _T_2288 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_2289 = bits(entries_ld[1].bits.opa.bits.end.data, 11, 0) node _T_2290 = lt(_T_2288, _T_2289) node _T_2291 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_2292 = bits(entries_ld[1].bits.opa.bits.end.data, 13, 0) node _T_2293 = lt(_T_2291, _T_2292) node _T_2294 = mux(new_entry.opa.bits.start.is_acc_addr, _T_2290, _T_2293) node _T_2295 = and(_T_2287, _T_2294) node _T_2296 = or(_T_2295, entries_ld[1].bits.opa.bits.wraps_around) node _T_2297 = and(_T_2286, _T_2296) node _T_2298 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ld[1].bits.opa.bits.start.is_acc_addr) node _T_2299 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_2300 = bits(entries_ld[1].bits.opa.bits.start.data, 11, 0) node _T_2301 = leq(_T_2299, _T_2300) node _T_2302 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_2303 = bits(entries_ld[1].bits.opa.bits.start.data, 13, 0) node _T_2304 = leq(_T_2302, _T_2303) node _T_2305 = mux(new_entry.opa.bits.start.is_acc_addr, _T_2301, _T_2304) node _T_2306 = and(_T_2298, _T_2305) node _T_2307 = eq(entries_ld[1].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_2308 = bits(entries_ld[1].bits.opa.bits.start.data, 11, 0) node _T_2309 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_2310 = lt(_T_2308, _T_2309) node _T_2311 = bits(entries_ld[1].bits.opa.bits.start.data, 13, 0) node _T_2312 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_2313 = lt(_T_2311, _T_2312) node _T_2314 = mux(entries_ld[1].bits.opa.bits.start.is_acc_addr, _T_2310, _T_2313) node _T_2315 = and(_T_2307, _T_2314) node _T_2316 = or(_T_2315, new_entry.opa.bits.wraps_around) node _T_2317 = and(_T_2306, _T_2316) node _T_2318 = or(_T_2297, _T_2317) node _T_2319 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_2320 = and(_T_2319, new_entry.opa.bits.start.read_full_acc_row) node _T_2321 = andr(new_entry.opa.bits.start.data) node _T_2322 = and(_T_2320, _T_2321) node _T_2323 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_2324 = and(_T_2322, _T_2323) node _T_2325 = and(entries_ld[1].bits.opa.bits.start.is_acc_addr, entries_ld[1].bits.opa.bits.start.accumulate) node _T_2326 = and(_T_2325, entries_ld[1].bits.opa.bits.start.read_full_acc_row) node _T_2327 = andr(entries_ld[1].bits.opa.bits.start.data) node _T_2328 = and(_T_2326, _T_2327) node _T_2329 = bits(entries_ld[1].bits.opa.bits.start.garbage_bit, 0, 0) node _T_2330 = and(_T_2328, _T_2329) node _T_2331 = or(_T_2324, _T_2330) node _T_2332 = eq(_T_2331, UInt<1>(0h0)) node _T_2333 = and(_T_2318, _T_2332) node _T_2334 = eq(entries_ld[1].bits.opa.bits.start.is_acc_addr, new_entry.opb.bits.start.is_acc_addr) node _T_2335 = bits(entries_ld[1].bits.opa.bits.start.data, 11, 0) node _T_2336 = bits(new_entry.opb.bits.start.data, 11, 0) node _T_2337 = leq(_T_2335, _T_2336) node _T_2338 = bits(entries_ld[1].bits.opa.bits.start.data, 13, 0) node _T_2339 = bits(new_entry.opb.bits.start.data, 13, 0) node _T_2340 = leq(_T_2338, _T_2339) node _T_2341 = mux(entries_ld[1].bits.opa.bits.start.is_acc_addr, _T_2337, _T_2340) node _T_2342 = and(_T_2334, _T_2341) node _T_2343 = eq(new_entry.opb.bits.start.is_acc_addr, entries_ld[1].bits.opa.bits.end.is_acc_addr) node _T_2344 = bits(new_entry.opb.bits.start.data, 11, 0) node _T_2345 = bits(entries_ld[1].bits.opa.bits.end.data, 11, 0) node _T_2346 = lt(_T_2344, _T_2345) node _T_2347 = bits(new_entry.opb.bits.start.data, 13, 0) node _T_2348 = bits(entries_ld[1].bits.opa.bits.end.data, 13, 0) node _T_2349 = lt(_T_2347, _T_2348) node _T_2350 = mux(new_entry.opb.bits.start.is_acc_addr, _T_2346, _T_2349) node _T_2351 = and(_T_2343, _T_2350) node _T_2352 = or(_T_2351, entries_ld[1].bits.opa.bits.wraps_around) node _T_2353 = and(_T_2342, _T_2352) node _T_2354 = eq(new_entry.opb.bits.start.is_acc_addr, entries_ld[1].bits.opa.bits.start.is_acc_addr) node _T_2355 = bits(new_entry.opb.bits.start.data, 11, 0) node _T_2356 = bits(entries_ld[1].bits.opa.bits.start.data, 11, 0) node _T_2357 = leq(_T_2355, _T_2356) node _T_2358 = bits(new_entry.opb.bits.start.data, 13, 0) node _T_2359 = bits(entries_ld[1].bits.opa.bits.start.data, 13, 0) node _T_2360 = leq(_T_2358, _T_2359) node _T_2361 = mux(new_entry.opb.bits.start.is_acc_addr, _T_2357, _T_2360) node _T_2362 = and(_T_2354, _T_2361) node _T_2363 = eq(entries_ld[1].bits.opa.bits.start.is_acc_addr, new_entry.opb.bits.end.is_acc_addr) node _T_2364 = bits(entries_ld[1].bits.opa.bits.start.data, 11, 0) node _T_2365 = bits(new_entry.opb.bits.end.data, 11, 0) node _T_2366 = lt(_T_2364, _T_2365) node _T_2367 = bits(entries_ld[1].bits.opa.bits.start.data, 13, 0) node _T_2368 = bits(new_entry.opb.bits.end.data, 13, 0) node _T_2369 = lt(_T_2367, _T_2368) node _T_2370 = mux(entries_ld[1].bits.opa.bits.start.is_acc_addr, _T_2366, _T_2369) node _T_2371 = and(_T_2363, _T_2370) node _T_2372 = or(_T_2371, new_entry.opb.bits.wraps_around) node _T_2373 = and(_T_2362, _T_2372) node _T_2374 = or(_T_2353, _T_2373) node _T_2375 = and(new_entry.opb.bits.start.is_acc_addr, new_entry.opb.bits.start.accumulate) node _T_2376 = and(_T_2375, new_entry.opb.bits.start.read_full_acc_row) node _T_2377 = andr(new_entry.opb.bits.start.data) node _T_2378 = and(_T_2376, _T_2377) node _T_2379 = bits(new_entry.opb.bits.start.garbage_bit, 0, 0) node _T_2380 = and(_T_2378, _T_2379) node _T_2381 = and(entries_ld[1].bits.opa.bits.start.is_acc_addr, entries_ld[1].bits.opa.bits.start.accumulate) node _T_2382 = and(_T_2381, entries_ld[1].bits.opa.bits.start.read_full_acc_row) node _T_2383 = andr(entries_ld[1].bits.opa.bits.start.data) node _T_2384 = and(_T_2382, _T_2383) node _T_2385 = bits(entries_ld[1].bits.opa.bits.start.garbage_bit, 0, 0) node _T_2386 = and(_T_2384, _T_2385) node _T_2387 = or(_T_2380, _T_2386) node _T_2388 = eq(_T_2387, UInt<1>(0h0)) node _T_2389 = and(_T_2374, _T_2388) node _T_2390 = or(_T_2333, _T_2389) node _T_2391 = and(_T_2277, _T_2390) node _T_2392 = and(entries_ld[2].valid, entries_ld[2].bits.opa.valid) node _T_2393 = and(_T_2392, not_config) node _T_2394 = eq(entries_ld[2].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_2395 = bits(entries_ld[2].bits.opa.bits.start.data, 11, 0) node _T_2396 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_2397 = leq(_T_2395, _T_2396) node _T_2398 = bits(entries_ld[2].bits.opa.bits.start.data, 13, 0) node _T_2399 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_2400 = leq(_T_2398, _T_2399) node _T_2401 = mux(entries_ld[2].bits.opa.bits.start.is_acc_addr, _T_2397, _T_2400) node _T_2402 = and(_T_2394, _T_2401) node _T_2403 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ld[2].bits.opa.bits.end.is_acc_addr) node _T_2404 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_2405 = bits(entries_ld[2].bits.opa.bits.end.data, 11, 0) node _T_2406 = lt(_T_2404, _T_2405) node _T_2407 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_2408 = bits(entries_ld[2].bits.opa.bits.end.data, 13, 0) node _T_2409 = lt(_T_2407, _T_2408) node _T_2410 = mux(new_entry.opa.bits.start.is_acc_addr, _T_2406, _T_2409) node _T_2411 = and(_T_2403, _T_2410) node _T_2412 = or(_T_2411, entries_ld[2].bits.opa.bits.wraps_around) node _T_2413 = and(_T_2402, _T_2412) node _T_2414 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ld[2].bits.opa.bits.start.is_acc_addr) node _T_2415 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_2416 = bits(entries_ld[2].bits.opa.bits.start.data, 11, 0) node _T_2417 = leq(_T_2415, _T_2416) node _T_2418 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_2419 = bits(entries_ld[2].bits.opa.bits.start.data, 13, 0) node _T_2420 = leq(_T_2418, _T_2419) node _T_2421 = mux(new_entry.opa.bits.start.is_acc_addr, _T_2417, _T_2420) node _T_2422 = and(_T_2414, _T_2421) node _T_2423 = eq(entries_ld[2].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_2424 = bits(entries_ld[2].bits.opa.bits.start.data, 11, 0) node _T_2425 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_2426 = lt(_T_2424, _T_2425) node _T_2427 = bits(entries_ld[2].bits.opa.bits.start.data, 13, 0) node _T_2428 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_2429 = lt(_T_2427, _T_2428) node _T_2430 = mux(entries_ld[2].bits.opa.bits.start.is_acc_addr, _T_2426, _T_2429) node _T_2431 = and(_T_2423, _T_2430) node _T_2432 = or(_T_2431, new_entry.opa.bits.wraps_around) node _T_2433 = and(_T_2422, _T_2432) node _T_2434 = or(_T_2413, _T_2433) node _T_2435 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_2436 = and(_T_2435, new_entry.opa.bits.start.read_full_acc_row) node _T_2437 = andr(new_entry.opa.bits.start.data) node _T_2438 = and(_T_2436, _T_2437) node _T_2439 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_2440 = and(_T_2438, _T_2439) node _T_2441 = and(entries_ld[2].bits.opa.bits.start.is_acc_addr, entries_ld[2].bits.opa.bits.start.accumulate) node _T_2442 = and(_T_2441, entries_ld[2].bits.opa.bits.start.read_full_acc_row) node _T_2443 = andr(entries_ld[2].bits.opa.bits.start.data) node _T_2444 = and(_T_2442, _T_2443) node _T_2445 = bits(entries_ld[2].bits.opa.bits.start.garbage_bit, 0, 0) node _T_2446 = and(_T_2444, _T_2445) node _T_2447 = or(_T_2440, _T_2446) node _T_2448 = eq(_T_2447, UInt<1>(0h0)) node _T_2449 = and(_T_2434, _T_2448) node _T_2450 = eq(entries_ld[2].bits.opa.bits.start.is_acc_addr, new_entry.opb.bits.start.is_acc_addr) node _T_2451 = bits(entries_ld[2].bits.opa.bits.start.data, 11, 0) node _T_2452 = bits(new_entry.opb.bits.start.data, 11, 0) node _T_2453 = leq(_T_2451, _T_2452) node _T_2454 = bits(entries_ld[2].bits.opa.bits.start.data, 13, 0) node _T_2455 = bits(new_entry.opb.bits.start.data, 13, 0) node _T_2456 = leq(_T_2454, _T_2455) node _T_2457 = mux(entries_ld[2].bits.opa.bits.start.is_acc_addr, _T_2453, _T_2456) node _T_2458 = and(_T_2450, _T_2457) node _T_2459 = eq(new_entry.opb.bits.start.is_acc_addr, entries_ld[2].bits.opa.bits.end.is_acc_addr) node _T_2460 = bits(new_entry.opb.bits.start.data, 11, 0) node _T_2461 = bits(entries_ld[2].bits.opa.bits.end.data, 11, 0) node _T_2462 = lt(_T_2460, _T_2461) node _T_2463 = bits(new_entry.opb.bits.start.data, 13, 0) node _T_2464 = bits(entries_ld[2].bits.opa.bits.end.data, 13, 0) node _T_2465 = lt(_T_2463, _T_2464) node _T_2466 = mux(new_entry.opb.bits.start.is_acc_addr, _T_2462, _T_2465) node _T_2467 = and(_T_2459, _T_2466) node _T_2468 = or(_T_2467, entries_ld[2].bits.opa.bits.wraps_around) node _T_2469 = and(_T_2458, _T_2468) node _T_2470 = eq(new_entry.opb.bits.start.is_acc_addr, entries_ld[2].bits.opa.bits.start.is_acc_addr) node _T_2471 = bits(new_entry.opb.bits.start.data, 11, 0) node _T_2472 = bits(entries_ld[2].bits.opa.bits.start.data, 11, 0) node _T_2473 = leq(_T_2471, _T_2472) node _T_2474 = bits(new_entry.opb.bits.start.data, 13, 0) node _T_2475 = bits(entries_ld[2].bits.opa.bits.start.data, 13, 0) node _T_2476 = leq(_T_2474, _T_2475) node _T_2477 = mux(new_entry.opb.bits.start.is_acc_addr, _T_2473, _T_2476) node _T_2478 = and(_T_2470, _T_2477) node _T_2479 = eq(entries_ld[2].bits.opa.bits.start.is_acc_addr, new_entry.opb.bits.end.is_acc_addr) node _T_2480 = bits(entries_ld[2].bits.opa.bits.start.data, 11, 0) node _T_2481 = bits(new_entry.opb.bits.end.data, 11, 0) node _T_2482 = lt(_T_2480, _T_2481) node _T_2483 = bits(entries_ld[2].bits.opa.bits.start.data, 13, 0) node _T_2484 = bits(new_entry.opb.bits.end.data, 13, 0) node _T_2485 = lt(_T_2483, _T_2484) node _T_2486 = mux(entries_ld[2].bits.opa.bits.start.is_acc_addr, _T_2482, _T_2485) node _T_2487 = and(_T_2479, _T_2486) node _T_2488 = or(_T_2487, new_entry.opb.bits.wraps_around) node _T_2489 = and(_T_2478, _T_2488) node _T_2490 = or(_T_2469, _T_2489) node _T_2491 = and(new_entry.opb.bits.start.is_acc_addr, new_entry.opb.bits.start.accumulate) node _T_2492 = and(_T_2491, new_entry.opb.bits.start.read_full_acc_row) node _T_2493 = andr(new_entry.opb.bits.start.data) node _T_2494 = and(_T_2492, _T_2493) node _T_2495 = bits(new_entry.opb.bits.start.garbage_bit, 0, 0) node _T_2496 = and(_T_2494, _T_2495) node _T_2497 = and(entries_ld[2].bits.opa.bits.start.is_acc_addr, entries_ld[2].bits.opa.bits.start.accumulate) node _T_2498 = and(_T_2497, entries_ld[2].bits.opa.bits.start.read_full_acc_row) node _T_2499 = andr(entries_ld[2].bits.opa.bits.start.data) node _T_2500 = and(_T_2498, _T_2499) node _T_2501 = bits(entries_ld[2].bits.opa.bits.start.garbage_bit, 0, 0) node _T_2502 = and(_T_2500, _T_2501) node _T_2503 = or(_T_2496, _T_2502) node _T_2504 = eq(_T_2503, UInt<1>(0h0)) node _T_2505 = and(_T_2490, _T_2504) node _T_2506 = or(_T_2449, _T_2505) node _T_2507 = and(_T_2393, _T_2506) node _T_2508 = and(entries_ld[3].valid, entries_ld[3].bits.opa.valid) node _T_2509 = and(_T_2508, not_config) node _T_2510 = eq(entries_ld[3].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_2511 = bits(entries_ld[3].bits.opa.bits.start.data, 11, 0) node _T_2512 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_2513 = leq(_T_2511, _T_2512) node _T_2514 = bits(entries_ld[3].bits.opa.bits.start.data, 13, 0) node _T_2515 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_2516 = leq(_T_2514, _T_2515) node _T_2517 = mux(entries_ld[3].bits.opa.bits.start.is_acc_addr, _T_2513, _T_2516) node _T_2518 = and(_T_2510, _T_2517) node _T_2519 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ld[3].bits.opa.bits.end.is_acc_addr) node _T_2520 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_2521 = bits(entries_ld[3].bits.opa.bits.end.data, 11, 0) node _T_2522 = lt(_T_2520, _T_2521) node _T_2523 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_2524 = bits(entries_ld[3].bits.opa.bits.end.data, 13, 0) node _T_2525 = lt(_T_2523, _T_2524) node _T_2526 = mux(new_entry.opa.bits.start.is_acc_addr, _T_2522, _T_2525) node _T_2527 = and(_T_2519, _T_2526) node _T_2528 = or(_T_2527, entries_ld[3].bits.opa.bits.wraps_around) node _T_2529 = and(_T_2518, _T_2528) node _T_2530 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ld[3].bits.opa.bits.start.is_acc_addr) node _T_2531 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_2532 = bits(entries_ld[3].bits.opa.bits.start.data, 11, 0) node _T_2533 = leq(_T_2531, _T_2532) node _T_2534 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_2535 = bits(entries_ld[3].bits.opa.bits.start.data, 13, 0) node _T_2536 = leq(_T_2534, _T_2535) node _T_2537 = mux(new_entry.opa.bits.start.is_acc_addr, _T_2533, _T_2536) node _T_2538 = and(_T_2530, _T_2537) node _T_2539 = eq(entries_ld[3].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_2540 = bits(entries_ld[3].bits.opa.bits.start.data, 11, 0) node _T_2541 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_2542 = lt(_T_2540, _T_2541) node _T_2543 = bits(entries_ld[3].bits.opa.bits.start.data, 13, 0) node _T_2544 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_2545 = lt(_T_2543, _T_2544) node _T_2546 = mux(entries_ld[3].bits.opa.bits.start.is_acc_addr, _T_2542, _T_2545) node _T_2547 = and(_T_2539, _T_2546) node _T_2548 = or(_T_2547, new_entry.opa.bits.wraps_around) node _T_2549 = and(_T_2538, _T_2548) node _T_2550 = or(_T_2529, _T_2549) node _T_2551 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_2552 = and(_T_2551, new_entry.opa.bits.start.read_full_acc_row) node _T_2553 = andr(new_entry.opa.bits.start.data) node _T_2554 = and(_T_2552, _T_2553) node _T_2555 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_2556 = and(_T_2554, _T_2555) node _T_2557 = and(entries_ld[3].bits.opa.bits.start.is_acc_addr, entries_ld[3].bits.opa.bits.start.accumulate) node _T_2558 = and(_T_2557, entries_ld[3].bits.opa.bits.start.read_full_acc_row) node _T_2559 = andr(entries_ld[3].bits.opa.bits.start.data) node _T_2560 = and(_T_2558, _T_2559) node _T_2561 = bits(entries_ld[3].bits.opa.bits.start.garbage_bit, 0, 0) node _T_2562 = and(_T_2560, _T_2561) node _T_2563 = or(_T_2556, _T_2562) node _T_2564 = eq(_T_2563, UInt<1>(0h0)) node _T_2565 = and(_T_2550, _T_2564) node _T_2566 = eq(entries_ld[3].bits.opa.bits.start.is_acc_addr, new_entry.opb.bits.start.is_acc_addr) node _T_2567 = bits(entries_ld[3].bits.opa.bits.start.data, 11, 0) node _T_2568 = bits(new_entry.opb.bits.start.data, 11, 0) node _T_2569 = leq(_T_2567, _T_2568) node _T_2570 = bits(entries_ld[3].bits.opa.bits.start.data, 13, 0) node _T_2571 = bits(new_entry.opb.bits.start.data, 13, 0) node _T_2572 = leq(_T_2570, _T_2571) node _T_2573 = mux(entries_ld[3].bits.opa.bits.start.is_acc_addr, _T_2569, _T_2572) node _T_2574 = and(_T_2566, _T_2573) node _T_2575 = eq(new_entry.opb.bits.start.is_acc_addr, entries_ld[3].bits.opa.bits.end.is_acc_addr) node _T_2576 = bits(new_entry.opb.bits.start.data, 11, 0) node _T_2577 = bits(entries_ld[3].bits.opa.bits.end.data, 11, 0) node _T_2578 = lt(_T_2576, _T_2577) node _T_2579 = bits(new_entry.opb.bits.start.data, 13, 0) node _T_2580 = bits(entries_ld[3].bits.opa.bits.end.data, 13, 0) node _T_2581 = lt(_T_2579, _T_2580) node _T_2582 = mux(new_entry.opb.bits.start.is_acc_addr, _T_2578, _T_2581) node _T_2583 = and(_T_2575, _T_2582) node _T_2584 = or(_T_2583, entries_ld[3].bits.opa.bits.wraps_around) node _T_2585 = and(_T_2574, _T_2584) node _T_2586 = eq(new_entry.opb.bits.start.is_acc_addr, entries_ld[3].bits.opa.bits.start.is_acc_addr) node _T_2587 = bits(new_entry.opb.bits.start.data, 11, 0) node _T_2588 = bits(entries_ld[3].bits.opa.bits.start.data, 11, 0) node _T_2589 = leq(_T_2587, _T_2588) node _T_2590 = bits(new_entry.opb.bits.start.data, 13, 0) node _T_2591 = bits(entries_ld[3].bits.opa.bits.start.data, 13, 0) node _T_2592 = leq(_T_2590, _T_2591) node _T_2593 = mux(new_entry.opb.bits.start.is_acc_addr, _T_2589, _T_2592) node _T_2594 = and(_T_2586, _T_2593) node _T_2595 = eq(entries_ld[3].bits.opa.bits.start.is_acc_addr, new_entry.opb.bits.end.is_acc_addr) node _T_2596 = bits(entries_ld[3].bits.opa.bits.start.data, 11, 0) node _T_2597 = bits(new_entry.opb.bits.end.data, 11, 0) node _T_2598 = lt(_T_2596, _T_2597) node _T_2599 = bits(entries_ld[3].bits.opa.bits.start.data, 13, 0) node _T_2600 = bits(new_entry.opb.bits.end.data, 13, 0) node _T_2601 = lt(_T_2599, _T_2600) node _T_2602 = mux(entries_ld[3].bits.opa.bits.start.is_acc_addr, _T_2598, _T_2601) node _T_2603 = and(_T_2595, _T_2602) node _T_2604 = or(_T_2603, new_entry.opb.bits.wraps_around) node _T_2605 = and(_T_2594, _T_2604) node _T_2606 = or(_T_2585, _T_2605) node _T_2607 = and(new_entry.opb.bits.start.is_acc_addr, new_entry.opb.bits.start.accumulate) node _T_2608 = and(_T_2607, new_entry.opb.bits.start.read_full_acc_row) node _T_2609 = andr(new_entry.opb.bits.start.data) node _T_2610 = and(_T_2608, _T_2609) node _T_2611 = bits(new_entry.opb.bits.start.garbage_bit, 0, 0) node _T_2612 = and(_T_2610, _T_2611) node _T_2613 = and(entries_ld[3].bits.opa.bits.start.is_acc_addr, entries_ld[3].bits.opa.bits.start.accumulate) node _T_2614 = and(_T_2613, entries_ld[3].bits.opa.bits.start.read_full_acc_row) node _T_2615 = andr(entries_ld[3].bits.opa.bits.start.data) node _T_2616 = and(_T_2614, _T_2615) node _T_2617 = bits(entries_ld[3].bits.opa.bits.start.garbage_bit, 0, 0) node _T_2618 = and(_T_2616, _T_2617) node _T_2619 = or(_T_2612, _T_2618) node _T_2620 = eq(_T_2619, UInt<1>(0h0)) node _T_2621 = and(_T_2606, _T_2620) node _T_2622 = or(_T_2565, _T_2621) node _T_2623 = and(_T_2509, _T_2622) node _T_2624 = and(entries_ld[4].valid, entries_ld[4].bits.opa.valid) node _T_2625 = and(_T_2624, not_config) node _T_2626 = eq(entries_ld[4].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_2627 = bits(entries_ld[4].bits.opa.bits.start.data, 11, 0) node _T_2628 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_2629 = leq(_T_2627, _T_2628) node _T_2630 = bits(entries_ld[4].bits.opa.bits.start.data, 13, 0) node _T_2631 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_2632 = leq(_T_2630, _T_2631) node _T_2633 = mux(entries_ld[4].bits.opa.bits.start.is_acc_addr, _T_2629, _T_2632) node _T_2634 = and(_T_2626, _T_2633) node _T_2635 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ld[4].bits.opa.bits.end.is_acc_addr) node _T_2636 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_2637 = bits(entries_ld[4].bits.opa.bits.end.data, 11, 0) node _T_2638 = lt(_T_2636, _T_2637) node _T_2639 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_2640 = bits(entries_ld[4].bits.opa.bits.end.data, 13, 0) node _T_2641 = lt(_T_2639, _T_2640) node _T_2642 = mux(new_entry.opa.bits.start.is_acc_addr, _T_2638, _T_2641) node _T_2643 = and(_T_2635, _T_2642) node _T_2644 = or(_T_2643, entries_ld[4].bits.opa.bits.wraps_around) node _T_2645 = and(_T_2634, _T_2644) node _T_2646 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ld[4].bits.opa.bits.start.is_acc_addr) node _T_2647 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_2648 = bits(entries_ld[4].bits.opa.bits.start.data, 11, 0) node _T_2649 = leq(_T_2647, _T_2648) node _T_2650 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_2651 = bits(entries_ld[4].bits.opa.bits.start.data, 13, 0) node _T_2652 = leq(_T_2650, _T_2651) node _T_2653 = mux(new_entry.opa.bits.start.is_acc_addr, _T_2649, _T_2652) node _T_2654 = and(_T_2646, _T_2653) node _T_2655 = eq(entries_ld[4].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_2656 = bits(entries_ld[4].bits.opa.bits.start.data, 11, 0) node _T_2657 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_2658 = lt(_T_2656, _T_2657) node _T_2659 = bits(entries_ld[4].bits.opa.bits.start.data, 13, 0) node _T_2660 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_2661 = lt(_T_2659, _T_2660) node _T_2662 = mux(entries_ld[4].bits.opa.bits.start.is_acc_addr, _T_2658, _T_2661) node _T_2663 = and(_T_2655, _T_2662) node _T_2664 = or(_T_2663, new_entry.opa.bits.wraps_around) node _T_2665 = and(_T_2654, _T_2664) node _T_2666 = or(_T_2645, _T_2665) node _T_2667 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_2668 = and(_T_2667, new_entry.opa.bits.start.read_full_acc_row) node _T_2669 = andr(new_entry.opa.bits.start.data) node _T_2670 = and(_T_2668, _T_2669) node _T_2671 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_2672 = and(_T_2670, _T_2671) node _T_2673 = and(entries_ld[4].bits.opa.bits.start.is_acc_addr, entries_ld[4].bits.opa.bits.start.accumulate) node _T_2674 = and(_T_2673, entries_ld[4].bits.opa.bits.start.read_full_acc_row) node _T_2675 = andr(entries_ld[4].bits.opa.bits.start.data) node _T_2676 = and(_T_2674, _T_2675) node _T_2677 = bits(entries_ld[4].bits.opa.bits.start.garbage_bit, 0, 0) node _T_2678 = and(_T_2676, _T_2677) node _T_2679 = or(_T_2672, _T_2678) node _T_2680 = eq(_T_2679, UInt<1>(0h0)) node _T_2681 = and(_T_2666, _T_2680) node _T_2682 = eq(entries_ld[4].bits.opa.bits.start.is_acc_addr, new_entry.opb.bits.start.is_acc_addr) node _T_2683 = bits(entries_ld[4].bits.opa.bits.start.data, 11, 0) node _T_2684 = bits(new_entry.opb.bits.start.data, 11, 0) node _T_2685 = leq(_T_2683, _T_2684) node _T_2686 = bits(entries_ld[4].bits.opa.bits.start.data, 13, 0) node _T_2687 = bits(new_entry.opb.bits.start.data, 13, 0) node _T_2688 = leq(_T_2686, _T_2687) node _T_2689 = mux(entries_ld[4].bits.opa.bits.start.is_acc_addr, _T_2685, _T_2688) node _T_2690 = and(_T_2682, _T_2689) node _T_2691 = eq(new_entry.opb.bits.start.is_acc_addr, entries_ld[4].bits.opa.bits.end.is_acc_addr) node _T_2692 = bits(new_entry.opb.bits.start.data, 11, 0) node _T_2693 = bits(entries_ld[4].bits.opa.bits.end.data, 11, 0) node _T_2694 = lt(_T_2692, _T_2693) node _T_2695 = bits(new_entry.opb.bits.start.data, 13, 0) node _T_2696 = bits(entries_ld[4].bits.opa.bits.end.data, 13, 0) node _T_2697 = lt(_T_2695, _T_2696) node _T_2698 = mux(new_entry.opb.bits.start.is_acc_addr, _T_2694, _T_2697) node _T_2699 = and(_T_2691, _T_2698) node _T_2700 = or(_T_2699, entries_ld[4].bits.opa.bits.wraps_around) node _T_2701 = and(_T_2690, _T_2700) node _T_2702 = eq(new_entry.opb.bits.start.is_acc_addr, entries_ld[4].bits.opa.bits.start.is_acc_addr) node _T_2703 = bits(new_entry.opb.bits.start.data, 11, 0) node _T_2704 = bits(entries_ld[4].bits.opa.bits.start.data, 11, 0) node _T_2705 = leq(_T_2703, _T_2704) node _T_2706 = bits(new_entry.opb.bits.start.data, 13, 0) node _T_2707 = bits(entries_ld[4].bits.opa.bits.start.data, 13, 0) node _T_2708 = leq(_T_2706, _T_2707) node _T_2709 = mux(new_entry.opb.bits.start.is_acc_addr, _T_2705, _T_2708) node _T_2710 = and(_T_2702, _T_2709) node _T_2711 = eq(entries_ld[4].bits.opa.bits.start.is_acc_addr, new_entry.opb.bits.end.is_acc_addr) node _T_2712 = bits(entries_ld[4].bits.opa.bits.start.data, 11, 0) node _T_2713 = bits(new_entry.opb.bits.end.data, 11, 0) node _T_2714 = lt(_T_2712, _T_2713) node _T_2715 = bits(entries_ld[4].bits.opa.bits.start.data, 13, 0) node _T_2716 = bits(new_entry.opb.bits.end.data, 13, 0) node _T_2717 = lt(_T_2715, _T_2716) node _T_2718 = mux(entries_ld[4].bits.opa.bits.start.is_acc_addr, _T_2714, _T_2717) node _T_2719 = and(_T_2711, _T_2718) node _T_2720 = or(_T_2719, new_entry.opb.bits.wraps_around) node _T_2721 = and(_T_2710, _T_2720) node _T_2722 = or(_T_2701, _T_2721) node _T_2723 = and(new_entry.opb.bits.start.is_acc_addr, new_entry.opb.bits.start.accumulate) node _T_2724 = and(_T_2723, new_entry.opb.bits.start.read_full_acc_row) node _T_2725 = andr(new_entry.opb.bits.start.data) node _T_2726 = and(_T_2724, _T_2725) node _T_2727 = bits(new_entry.opb.bits.start.garbage_bit, 0, 0) node _T_2728 = and(_T_2726, _T_2727) node _T_2729 = and(entries_ld[4].bits.opa.bits.start.is_acc_addr, entries_ld[4].bits.opa.bits.start.accumulate) node _T_2730 = and(_T_2729, entries_ld[4].bits.opa.bits.start.read_full_acc_row) node _T_2731 = andr(entries_ld[4].bits.opa.bits.start.data) node _T_2732 = and(_T_2730, _T_2731) node _T_2733 = bits(entries_ld[4].bits.opa.bits.start.garbage_bit, 0, 0) node _T_2734 = and(_T_2732, _T_2733) node _T_2735 = or(_T_2728, _T_2734) node _T_2736 = eq(_T_2735, UInt<1>(0h0)) node _T_2737 = and(_T_2722, _T_2736) node _T_2738 = or(_T_2681, _T_2737) node _T_2739 = and(_T_2625, _T_2738) node _T_2740 = and(entries_ld[5].valid, entries_ld[5].bits.opa.valid) node _T_2741 = and(_T_2740, not_config) node _T_2742 = eq(entries_ld[5].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_2743 = bits(entries_ld[5].bits.opa.bits.start.data, 11, 0) node _T_2744 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_2745 = leq(_T_2743, _T_2744) node _T_2746 = bits(entries_ld[5].bits.opa.bits.start.data, 13, 0) node _T_2747 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_2748 = leq(_T_2746, _T_2747) node _T_2749 = mux(entries_ld[5].bits.opa.bits.start.is_acc_addr, _T_2745, _T_2748) node _T_2750 = and(_T_2742, _T_2749) node _T_2751 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ld[5].bits.opa.bits.end.is_acc_addr) node _T_2752 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_2753 = bits(entries_ld[5].bits.opa.bits.end.data, 11, 0) node _T_2754 = lt(_T_2752, _T_2753) node _T_2755 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_2756 = bits(entries_ld[5].bits.opa.bits.end.data, 13, 0) node _T_2757 = lt(_T_2755, _T_2756) node _T_2758 = mux(new_entry.opa.bits.start.is_acc_addr, _T_2754, _T_2757) node _T_2759 = and(_T_2751, _T_2758) node _T_2760 = or(_T_2759, entries_ld[5].bits.opa.bits.wraps_around) node _T_2761 = and(_T_2750, _T_2760) node _T_2762 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ld[5].bits.opa.bits.start.is_acc_addr) node _T_2763 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_2764 = bits(entries_ld[5].bits.opa.bits.start.data, 11, 0) node _T_2765 = leq(_T_2763, _T_2764) node _T_2766 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_2767 = bits(entries_ld[5].bits.opa.bits.start.data, 13, 0) node _T_2768 = leq(_T_2766, _T_2767) node _T_2769 = mux(new_entry.opa.bits.start.is_acc_addr, _T_2765, _T_2768) node _T_2770 = and(_T_2762, _T_2769) node _T_2771 = eq(entries_ld[5].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_2772 = bits(entries_ld[5].bits.opa.bits.start.data, 11, 0) node _T_2773 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_2774 = lt(_T_2772, _T_2773) node _T_2775 = bits(entries_ld[5].bits.opa.bits.start.data, 13, 0) node _T_2776 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_2777 = lt(_T_2775, _T_2776) node _T_2778 = mux(entries_ld[5].bits.opa.bits.start.is_acc_addr, _T_2774, _T_2777) node _T_2779 = and(_T_2771, _T_2778) node _T_2780 = or(_T_2779, new_entry.opa.bits.wraps_around) node _T_2781 = and(_T_2770, _T_2780) node _T_2782 = or(_T_2761, _T_2781) node _T_2783 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_2784 = and(_T_2783, new_entry.opa.bits.start.read_full_acc_row) node _T_2785 = andr(new_entry.opa.bits.start.data) node _T_2786 = and(_T_2784, _T_2785) node _T_2787 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_2788 = and(_T_2786, _T_2787) node _T_2789 = and(entries_ld[5].bits.opa.bits.start.is_acc_addr, entries_ld[5].bits.opa.bits.start.accumulate) node _T_2790 = and(_T_2789, entries_ld[5].bits.opa.bits.start.read_full_acc_row) node _T_2791 = andr(entries_ld[5].bits.opa.bits.start.data) node _T_2792 = and(_T_2790, _T_2791) node _T_2793 = bits(entries_ld[5].bits.opa.bits.start.garbage_bit, 0, 0) node _T_2794 = and(_T_2792, _T_2793) node _T_2795 = or(_T_2788, _T_2794) node _T_2796 = eq(_T_2795, UInt<1>(0h0)) node _T_2797 = and(_T_2782, _T_2796) node _T_2798 = eq(entries_ld[5].bits.opa.bits.start.is_acc_addr, new_entry.opb.bits.start.is_acc_addr) node _T_2799 = bits(entries_ld[5].bits.opa.bits.start.data, 11, 0) node _T_2800 = bits(new_entry.opb.bits.start.data, 11, 0) node _T_2801 = leq(_T_2799, _T_2800) node _T_2802 = bits(entries_ld[5].bits.opa.bits.start.data, 13, 0) node _T_2803 = bits(new_entry.opb.bits.start.data, 13, 0) node _T_2804 = leq(_T_2802, _T_2803) node _T_2805 = mux(entries_ld[5].bits.opa.bits.start.is_acc_addr, _T_2801, _T_2804) node _T_2806 = and(_T_2798, _T_2805) node _T_2807 = eq(new_entry.opb.bits.start.is_acc_addr, entries_ld[5].bits.opa.bits.end.is_acc_addr) node _T_2808 = bits(new_entry.opb.bits.start.data, 11, 0) node _T_2809 = bits(entries_ld[5].bits.opa.bits.end.data, 11, 0) node _T_2810 = lt(_T_2808, _T_2809) node _T_2811 = bits(new_entry.opb.bits.start.data, 13, 0) node _T_2812 = bits(entries_ld[5].bits.opa.bits.end.data, 13, 0) node _T_2813 = lt(_T_2811, _T_2812) node _T_2814 = mux(new_entry.opb.bits.start.is_acc_addr, _T_2810, _T_2813) node _T_2815 = and(_T_2807, _T_2814) node _T_2816 = or(_T_2815, entries_ld[5].bits.opa.bits.wraps_around) node _T_2817 = and(_T_2806, _T_2816) node _T_2818 = eq(new_entry.opb.bits.start.is_acc_addr, entries_ld[5].bits.opa.bits.start.is_acc_addr) node _T_2819 = bits(new_entry.opb.bits.start.data, 11, 0) node _T_2820 = bits(entries_ld[5].bits.opa.bits.start.data, 11, 0) node _T_2821 = leq(_T_2819, _T_2820) node _T_2822 = bits(new_entry.opb.bits.start.data, 13, 0) node _T_2823 = bits(entries_ld[5].bits.opa.bits.start.data, 13, 0) node _T_2824 = leq(_T_2822, _T_2823) node _T_2825 = mux(new_entry.opb.bits.start.is_acc_addr, _T_2821, _T_2824) node _T_2826 = and(_T_2818, _T_2825) node _T_2827 = eq(entries_ld[5].bits.opa.bits.start.is_acc_addr, new_entry.opb.bits.end.is_acc_addr) node _T_2828 = bits(entries_ld[5].bits.opa.bits.start.data, 11, 0) node _T_2829 = bits(new_entry.opb.bits.end.data, 11, 0) node _T_2830 = lt(_T_2828, _T_2829) node _T_2831 = bits(entries_ld[5].bits.opa.bits.start.data, 13, 0) node _T_2832 = bits(new_entry.opb.bits.end.data, 13, 0) node _T_2833 = lt(_T_2831, _T_2832) node _T_2834 = mux(entries_ld[5].bits.opa.bits.start.is_acc_addr, _T_2830, _T_2833) node _T_2835 = and(_T_2827, _T_2834) node _T_2836 = or(_T_2835, new_entry.opb.bits.wraps_around) node _T_2837 = and(_T_2826, _T_2836) node _T_2838 = or(_T_2817, _T_2837) node _T_2839 = and(new_entry.opb.bits.start.is_acc_addr, new_entry.opb.bits.start.accumulate) node _T_2840 = and(_T_2839, new_entry.opb.bits.start.read_full_acc_row) node _T_2841 = andr(new_entry.opb.bits.start.data) node _T_2842 = and(_T_2840, _T_2841) node _T_2843 = bits(new_entry.opb.bits.start.garbage_bit, 0, 0) node _T_2844 = and(_T_2842, _T_2843) node _T_2845 = and(entries_ld[5].bits.opa.bits.start.is_acc_addr, entries_ld[5].bits.opa.bits.start.accumulate) node _T_2846 = and(_T_2845, entries_ld[5].bits.opa.bits.start.read_full_acc_row) node _T_2847 = andr(entries_ld[5].bits.opa.bits.start.data) node _T_2848 = and(_T_2846, _T_2847) node _T_2849 = bits(entries_ld[5].bits.opa.bits.start.garbage_bit, 0, 0) node _T_2850 = and(_T_2848, _T_2849) node _T_2851 = or(_T_2844, _T_2850) node _T_2852 = eq(_T_2851, UInt<1>(0h0)) node _T_2853 = and(_T_2838, _T_2852) node _T_2854 = or(_T_2797, _T_2853) node _T_2855 = and(_T_2741, _T_2854) node _T_2856 = and(entries_ld[6].valid, entries_ld[6].bits.opa.valid) node _T_2857 = and(_T_2856, not_config) node _T_2858 = eq(entries_ld[6].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_2859 = bits(entries_ld[6].bits.opa.bits.start.data, 11, 0) node _T_2860 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_2861 = leq(_T_2859, _T_2860) node _T_2862 = bits(entries_ld[6].bits.opa.bits.start.data, 13, 0) node _T_2863 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_2864 = leq(_T_2862, _T_2863) node _T_2865 = mux(entries_ld[6].bits.opa.bits.start.is_acc_addr, _T_2861, _T_2864) node _T_2866 = and(_T_2858, _T_2865) node _T_2867 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ld[6].bits.opa.bits.end.is_acc_addr) node _T_2868 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_2869 = bits(entries_ld[6].bits.opa.bits.end.data, 11, 0) node _T_2870 = lt(_T_2868, _T_2869) node _T_2871 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_2872 = bits(entries_ld[6].bits.opa.bits.end.data, 13, 0) node _T_2873 = lt(_T_2871, _T_2872) node _T_2874 = mux(new_entry.opa.bits.start.is_acc_addr, _T_2870, _T_2873) node _T_2875 = and(_T_2867, _T_2874) node _T_2876 = or(_T_2875, entries_ld[6].bits.opa.bits.wraps_around) node _T_2877 = and(_T_2866, _T_2876) node _T_2878 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ld[6].bits.opa.bits.start.is_acc_addr) node _T_2879 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_2880 = bits(entries_ld[6].bits.opa.bits.start.data, 11, 0) node _T_2881 = leq(_T_2879, _T_2880) node _T_2882 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_2883 = bits(entries_ld[6].bits.opa.bits.start.data, 13, 0) node _T_2884 = leq(_T_2882, _T_2883) node _T_2885 = mux(new_entry.opa.bits.start.is_acc_addr, _T_2881, _T_2884) node _T_2886 = and(_T_2878, _T_2885) node _T_2887 = eq(entries_ld[6].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_2888 = bits(entries_ld[6].bits.opa.bits.start.data, 11, 0) node _T_2889 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_2890 = lt(_T_2888, _T_2889) node _T_2891 = bits(entries_ld[6].bits.opa.bits.start.data, 13, 0) node _T_2892 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_2893 = lt(_T_2891, _T_2892) node _T_2894 = mux(entries_ld[6].bits.opa.bits.start.is_acc_addr, _T_2890, _T_2893) node _T_2895 = and(_T_2887, _T_2894) node _T_2896 = or(_T_2895, new_entry.opa.bits.wraps_around) node _T_2897 = and(_T_2886, _T_2896) node _T_2898 = or(_T_2877, _T_2897) node _T_2899 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_2900 = and(_T_2899, new_entry.opa.bits.start.read_full_acc_row) node _T_2901 = andr(new_entry.opa.bits.start.data) node _T_2902 = and(_T_2900, _T_2901) node _T_2903 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_2904 = and(_T_2902, _T_2903) node _T_2905 = and(entries_ld[6].bits.opa.bits.start.is_acc_addr, entries_ld[6].bits.opa.bits.start.accumulate) node _T_2906 = and(_T_2905, entries_ld[6].bits.opa.bits.start.read_full_acc_row) node _T_2907 = andr(entries_ld[6].bits.opa.bits.start.data) node _T_2908 = and(_T_2906, _T_2907) node _T_2909 = bits(entries_ld[6].bits.opa.bits.start.garbage_bit, 0, 0) node _T_2910 = and(_T_2908, _T_2909) node _T_2911 = or(_T_2904, _T_2910) node _T_2912 = eq(_T_2911, UInt<1>(0h0)) node _T_2913 = and(_T_2898, _T_2912) node _T_2914 = eq(entries_ld[6].bits.opa.bits.start.is_acc_addr, new_entry.opb.bits.start.is_acc_addr) node _T_2915 = bits(entries_ld[6].bits.opa.bits.start.data, 11, 0) node _T_2916 = bits(new_entry.opb.bits.start.data, 11, 0) node _T_2917 = leq(_T_2915, _T_2916) node _T_2918 = bits(entries_ld[6].bits.opa.bits.start.data, 13, 0) node _T_2919 = bits(new_entry.opb.bits.start.data, 13, 0) node _T_2920 = leq(_T_2918, _T_2919) node _T_2921 = mux(entries_ld[6].bits.opa.bits.start.is_acc_addr, _T_2917, _T_2920) node _T_2922 = and(_T_2914, _T_2921) node _T_2923 = eq(new_entry.opb.bits.start.is_acc_addr, entries_ld[6].bits.opa.bits.end.is_acc_addr) node _T_2924 = bits(new_entry.opb.bits.start.data, 11, 0) node _T_2925 = bits(entries_ld[6].bits.opa.bits.end.data, 11, 0) node _T_2926 = lt(_T_2924, _T_2925) node _T_2927 = bits(new_entry.opb.bits.start.data, 13, 0) node _T_2928 = bits(entries_ld[6].bits.opa.bits.end.data, 13, 0) node _T_2929 = lt(_T_2927, _T_2928) node _T_2930 = mux(new_entry.opb.bits.start.is_acc_addr, _T_2926, _T_2929) node _T_2931 = and(_T_2923, _T_2930) node _T_2932 = or(_T_2931, entries_ld[6].bits.opa.bits.wraps_around) node _T_2933 = and(_T_2922, _T_2932) node _T_2934 = eq(new_entry.opb.bits.start.is_acc_addr, entries_ld[6].bits.opa.bits.start.is_acc_addr) node _T_2935 = bits(new_entry.opb.bits.start.data, 11, 0) node _T_2936 = bits(entries_ld[6].bits.opa.bits.start.data, 11, 0) node _T_2937 = leq(_T_2935, _T_2936) node _T_2938 = bits(new_entry.opb.bits.start.data, 13, 0) node _T_2939 = bits(entries_ld[6].bits.opa.bits.start.data, 13, 0) node _T_2940 = leq(_T_2938, _T_2939) node _T_2941 = mux(new_entry.opb.bits.start.is_acc_addr, _T_2937, _T_2940) node _T_2942 = and(_T_2934, _T_2941) node _T_2943 = eq(entries_ld[6].bits.opa.bits.start.is_acc_addr, new_entry.opb.bits.end.is_acc_addr) node _T_2944 = bits(entries_ld[6].bits.opa.bits.start.data, 11, 0) node _T_2945 = bits(new_entry.opb.bits.end.data, 11, 0) node _T_2946 = lt(_T_2944, _T_2945) node _T_2947 = bits(entries_ld[6].bits.opa.bits.start.data, 13, 0) node _T_2948 = bits(new_entry.opb.bits.end.data, 13, 0) node _T_2949 = lt(_T_2947, _T_2948) node _T_2950 = mux(entries_ld[6].bits.opa.bits.start.is_acc_addr, _T_2946, _T_2949) node _T_2951 = and(_T_2943, _T_2950) node _T_2952 = or(_T_2951, new_entry.opb.bits.wraps_around) node _T_2953 = and(_T_2942, _T_2952) node _T_2954 = or(_T_2933, _T_2953) node _T_2955 = and(new_entry.opb.bits.start.is_acc_addr, new_entry.opb.bits.start.accumulate) node _T_2956 = and(_T_2955, new_entry.opb.bits.start.read_full_acc_row) node _T_2957 = andr(new_entry.opb.bits.start.data) node _T_2958 = and(_T_2956, _T_2957) node _T_2959 = bits(new_entry.opb.bits.start.garbage_bit, 0, 0) node _T_2960 = and(_T_2958, _T_2959) node _T_2961 = and(entries_ld[6].bits.opa.bits.start.is_acc_addr, entries_ld[6].bits.opa.bits.start.accumulate) node _T_2962 = and(_T_2961, entries_ld[6].bits.opa.bits.start.read_full_acc_row) node _T_2963 = andr(entries_ld[6].bits.opa.bits.start.data) node _T_2964 = and(_T_2962, _T_2963) node _T_2965 = bits(entries_ld[6].bits.opa.bits.start.garbage_bit, 0, 0) node _T_2966 = and(_T_2964, _T_2965) node _T_2967 = or(_T_2960, _T_2966) node _T_2968 = eq(_T_2967, UInt<1>(0h0)) node _T_2969 = and(_T_2954, _T_2968) node _T_2970 = or(_T_2913, _T_2969) node _T_2971 = and(_T_2857, _T_2970) node _T_2972 = and(entries_ld[7].valid, entries_ld[7].bits.opa.valid) node _T_2973 = and(_T_2972, not_config) node _T_2974 = eq(entries_ld[7].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_2975 = bits(entries_ld[7].bits.opa.bits.start.data, 11, 0) node _T_2976 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_2977 = leq(_T_2975, _T_2976) node _T_2978 = bits(entries_ld[7].bits.opa.bits.start.data, 13, 0) node _T_2979 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_2980 = leq(_T_2978, _T_2979) node _T_2981 = mux(entries_ld[7].bits.opa.bits.start.is_acc_addr, _T_2977, _T_2980) node _T_2982 = and(_T_2974, _T_2981) node _T_2983 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ld[7].bits.opa.bits.end.is_acc_addr) node _T_2984 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_2985 = bits(entries_ld[7].bits.opa.bits.end.data, 11, 0) node _T_2986 = lt(_T_2984, _T_2985) node _T_2987 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_2988 = bits(entries_ld[7].bits.opa.bits.end.data, 13, 0) node _T_2989 = lt(_T_2987, _T_2988) node _T_2990 = mux(new_entry.opa.bits.start.is_acc_addr, _T_2986, _T_2989) node _T_2991 = and(_T_2983, _T_2990) node _T_2992 = or(_T_2991, entries_ld[7].bits.opa.bits.wraps_around) node _T_2993 = and(_T_2982, _T_2992) node _T_2994 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ld[7].bits.opa.bits.start.is_acc_addr) node _T_2995 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_2996 = bits(entries_ld[7].bits.opa.bits.start.data, 11, 0) node _T_2997 = leq(_T_2995, _T_2996) node _T_2998 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_2999 = bits(entries_ld[7].bits.opa.bits.start.data, 13, 0) node _T_3000 = leq(_T_2998, _T_2999) node _T_3001 = mux(new_entry.opa.bits.start.is_acc_addr, _T_2997, _T_3000) node _T_3002 = and(_T_2994, _T_3001) node _T_3003 = eq(entries_ld[7].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_3004 = bits(entries_ld[7].bits.opa.bits.start.data, 11, 0) node _T_3005 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_3006 = lt(_T_3004, _T_3005) node _T_3007 = bits(entries_ld[7].bits.opa.bits.start.data, 13, 0) node _T_3008 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_3009 = lt(_T_3007, _T_3008) node _T_3010 = mux(entries_ld[7].bits.opa.bits.start.is_acc_addr, _T_3006, _T_3009) node _T_3011 = and(_T_3003, _T_3010) node _T_3012 = or(_T_3011, new_entry.opa.bits.wraps_around) node _T_3013 = and(_T_3002, _T_3012) node _T_3014 = or(_T_2993, _T_3013) node _T_3015 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_3016 = and(_T_3015, new_entry.opa.bits.start.read_full_acc_row) node _T_3017 = andr(new_entry.opa.bits.start.data) node _T_3018 = and(_T_3016, _T_3017) node _T_3019 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_3020 = and(_T_3018, _T_3019) node _T_3021 = and(entries_ld[7].bits.opa.bits.start.is_acc_addr, entries_ld[7].bits.opa.bits.start.accumulate) node _T_3022 = and(_T_3021, entries_ld[7].bits.opa.bits.start.read_full_acc_row) node _T_3023 = andr(entries_ld[7].bits.opa.bits.start.data) node _T_3024 = and(_T_3022, _T_3023) node _T_3025 = bits(entries_ld[7].bits.opa.bits.start.garbage_bit, 0, 0) node _T_3026 = and(_T_3024, _T_3025) node _T_3027 = or(_T_3020, _T_3026) node _T_3028 = eq(_T_3027, UInt<1>(0h0)) node _T_3029 = and(_T_3014, _T_3028) node _T_3030 = eq(entries_ld[7].bits.opa.bits.start.is_acc_addr, new_entry.opb.bits.start.is_acc_addr) node _T_3031 = bits(entries_ld[7].bits.opa.bits.start.data, 11, 0) node _T_3032 = bits(new_entry.opb.bits.start.data, 11, 0) node _T_3033 = leq(_T_3031, _T_3032) node _T_3034 = bits(entries_ld[7].bits.opa.bits.start.data, 13, 0) node _T_3035 = bits(new_entry.opb.bits.start.data, 13, 0) node _T_3036 = leq(_T_3034, _T_3035) node _T_3037 = mux(entries_ld[7].bits.opa.bits.start.is_acc_addr, _T_3033, _T_3036) node _T_3038 = and(_T_3030, _T_3037) node _T_3039 = eq(new_entry.opb.bits.start.is_acc_addr, entries_ld[7].bits.opa.bits.end.is_acc_addr) node _T_3040 = bits(new_entry.opb.bits.start.data, 11, 0) node _T_3041 = bits(entries_ld[7].bits.opa.bits.end.data, 11, 0) node _T_3042 = lt(_T_3040, _T_3041) node _T_3043 = bits(new_entry.opb.bits.start.data, 13, 0) node _T_3044 = bits(entries_ld[7].bits.opa.bits.end.data, 13, 0) node _T_3045 = lt(_T_3043, _T_3044) node _T_3046 = mux(new_entry.opb.bits.start.is_acc_addr, _T_3042, _T_3045) node _T_3047 = and(_T_3039, _T_3046) node _T_3048 = or(_T_3047, entries_ld[7].bits.opa.bits.wraps_around) node _T_3049 = and(_T_3038, _T_3048) node _T_3050 = eq(new_entry.opb.bits.start.is_acc_addr, entries_ld[7].bits.opa.bits.start.is_acc_addr) node _T_3051 = bits(new_entry.opb.bits.start.data, 11, 0) node _T_3052 = bits(entries_ld[7].bits.opa.bits.start.data, 11, 0) node _T_3053 = leq(_T_3051, _T_3052) node _T_3054 = bits(new_entry.opb.bits.start.data, 13, 0) node _T_3055 = bits(entries_ld[7].bits.opa.bits.start.data, 13, 0) node _T_3056 = leq(_T_3054, _T_3055) node _T_3057 = mux(new_entry.opb.bits.start.is_acc_addr, _T_3053, _T_3056) node _T_3058 = and(_T_3050, _T_3057) node _T_3059 = eq(entries_ld[7].bits.opa.bits.start.is_acc_addr, new_entry.opb.bits.end.is_acc_addr) node _T_3060 = bits(entries_ld[7].bits.opa.bits.start.data, 11, 0) node _T_3061 = bits(new_entry.opb.bits.end.data, 11, 0) node _T_3062 = lt(_T_3060, _T_3061) node _T_3063 = bits(entries_ld[7].bits.opa.bits.start.data, 13, 0) node _T_3064 = bits(new_entry.opb.bits.end.data, 13, 0) node _T_3065 = lt(_T_3063, _T_3064) node _T_3066 = mux(entries_ld[7].bits.opa.bits.start.is_acc_addr, _T_3062, _T_3065) node _T_3067 = and(_T_3059, _T_3066) node _T_3068 = or(_T_3067, new_entry.opb.bits.wraps_around) node _T_3069 = and(_T_3058, _T_3068) node _T_3070 = or(_T_3049, _T_3069) node _T_3071 = and(new_entry.opb.bits.start.is_acc_addr, new_entry.opb.bits.start.accumulate) node _T_3072 = and(_T_3071, new_entry.opb.bits.start.read_full_acc_row) node _T_3073 = andr(new_entry.opb.bits.start.data) node _T_3074 = and(_T_3072, _T_3073) node _T_3075 = bits(new_entry.opb.bits.start.garbage_bit, 0, 0) node _T_3076 = and(_T_3074, _T_3075) node _T_3077 = and(entries_ld[7].bits.opa.bits.start.is_acc_addr, entries_ld[7].bits.opa.bits.start.accumulate) node _T_3078 = and(_T_3077, entries_ld[7].bits.opa.bits.start.read_full_acc_row) node _T_3079 = andr(entries_ld[7].bits.opa.bits.start.data) node _T_3080 = and(_T_3078, _T_3079) node _T_3081 = bits(entries_ld[7].bits.opa.bits.start.garbage_bit, 0, 0) node _T_3082 = and(_T_3080, _T_3081) node _T_3083 = or(_T_3076, _T_3082) node _T_3084 = eq(_T_3083, UInt<1>(0h0)) node _T_3085 = and(_T_3070, _T_3084) node _T_3086 = or(_T_3029, _T_3085) node _T_3087 = and(_T_2973, _T_3086) wire _WIRE_3 : UInt<1>[8] connect _WIRE_3[0], _T_2275 connect _WIRE_3[1], _T_2391 connect _WIRE_3[2], _T_2507 connect _WIRE_3[3], _T_2623 connect _WIRE_3[4], _T_2739 connect _WIRE_3[5], _T_2855 connect _WIRE_3[6], _T_2971 connect _WIRE_3[7], _T_3087 connect new_entry.deps_ld, _WIRE_3 node _T_3088 = eq(entries_ex[0].bits.issued, UInt<1>(0h0)) node _T_3089 = and(entries_ex[0].valid, _T_3088) node _T_3090 = eq(entries_ex[1].bits.issued, UInt<1>(0h0)) node _T_3091 = and(entries_ex[1].valid, _T_3090) node _T_3092 = eq(entries_ex[2].bits.issued, UInt<1>(0h0)) node _T_3093 = and(entries_ex[2].valid, _T_3092) node _T_3094 = eq(entries_ex[3].bits.issued, UInt<1>(0h0)) node _T_3095 = and(entries_ex[3].valid, _T_3094) node _T_3096 = eq(entries_ex[4].bits.issued, UInt<1>(0h0)) node _T_3097 = and(entries_ex[4].valid, _T_3096) node _T_3098 = eq(entries_ex[5].bits.issued, UInt<1>(0h0)) node _T_3099 = and(entries_ex[5].valid, _T_3098) node _T_3100 = eq(entries_ex[6].bits.issued, UInt<1>(0h0)) node _T_3101 = and(entries_ex[6].valid, _T_3100) node _T_3102 = eq(entries_ex[7].bits.issued, UInt<1>(0h0)) node _T_3103 = and(entries_ex[7].valid, _T_3102) node _T_3104 = eq(entries_ex[8].bits.issued, UInt<1>(0h0)) node _T_3105 = and(entries_ex[8].valid, _T_3104) node _T_3106 = eq(entries_ex[9].bits.issued, UInt<1>(0h0)) node _T_3107 = and(entries_ex[9].valid, _T_3106) node _T_3108 = eq(entries_ex[10].bits.issued, UInt<1>(0h0)) node _T_3109 = and(entries_ex[10].valid, _T_3108) node _T_3110 = eq(entries_ex[11].bits.issued, UInt<1>(0h0)) node _T_3111 = and(entries_ex[11].valid, _T_3110) node _T_3112 = eq(entries_ex[12].bits.issued, UInt<1>(0h0)) node _T_3113 = and(entries_ex[12].valid, _T_3112) node _T_3114 = eq(entries_ex[13].bits.issued, UInt<1>(0h0)) node _T_3115 = and(entries_ex[13].valid, _T_3114) node _T_3116 = eq(entries_ex[14].bits.issued, UInt<1>(0h0)) node _T_3117 = and(entries_ex[14].valid, _T_3116) node _T_3118 = eq(entries_ex[15].bits.issued, UInt<1>(0h0)) node _T_3119 = and(entries_ex[15].valid, _T_3118) wire _WIRE_4 : UInt<1>[16] connect _WIRE_4[0], _T_3089 connect _WIRE_4[1], _T_3091 connect _WIRE_4[2], _T_3093 connect _WIRE_4[3], _T_3095 connect _WIRE_4[4], _T_3097 connect _WIRE_4[5], _T_3099 connect _WIRE_4[6], _T_3101 connect _WIRE_4[7], _T_3103 connect _WIRE_4[8], _T_3105 connect _WIRE_4[9], _T_3107 connect _WIRE_4[10], _T_3109 connect _WIRE_4[11], _T_3111 connect _WIRE_4[12], _T_3113 connect _WIRE_4[13], _T_3115 connect _WIRE_4[14], _T_3117 connect _WIRE_4[15], _T_3119 connect new_entry.deps_ex, _WIRE_4 node _T_3120 = and(entries_st[0].valid, entries_st[0].bits.opa.valid) node _T_3121 = and(_T_3120, not_config) node _T_3122 = and(_T_3121, new_entry.opa_is_dst) node _T_3123 = eq(entries_st[0].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_3124 = bits(entries_st[0].bits.opa.bits.start.data, 11, 0) node _T_3125 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_3126 = leq(_T_3124, _T_3125) node _T_3127 = bits(entries_st[0].bits.opa.bits.start.data, 13, 0) node _T_3128 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_3129 = leq(_T_3127, _T_3128) node _T_3130 = mux(entries_st[0].bits.opa.bits.start.is_acc_addr, _T_3126, _T_3129) node _T_3131 = and(_T_3123, _T_3130) node _T_3132 = eq(new_entry.opa.bits.start.is_acc_addr, entries_st[0].bits.opa.bits.end.is_acc_addr) node _T_3133 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_3134 = bits(entries_st[0].bits.opa.bits.end.data, 11, 0) node _T_3135 = lt(_T_3133, _T_3134) node _T_3136 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_3137 = bits(entries_st[0].bits.opa.bits.end.data, 13, 0) node _T_3138 = lt(_T_3136, _T_3137) node _T_3139 = mux(new_entry.opa.bits.start.is_acc_addr, _T_3135, _T_3138) node _T_3140 = and(_T_3132, _T_3139) node _T_3141 = or(_T_3140, entries_st[0].bits.opa.bits.wraps_around) node _T_3142 = and(_T_3131, _T_3141) node _T_3143 = eq(new_entry.opa.bits.start.is_acc_addr, entries_st[0].bits.opa.bits.start.is_acc_addr) node _T_3144 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_3145 = bits(entries_st[0].bits.opa.bits.start.data, 11, 0) node _T_3146 = leq(_T_3144, _T_3145) node _T_3147 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_3148 = bits(entries_st[0].bits.opa.bits.start.data, 13, 0) node _T_3149 = leq(_T_3147, _T_3148) node _T_3150 = mux(new_entry.opa.bits.start.is_acc_addr, _T_3146, _T_3149) node _T_3151 = and(_T_3143, _T_3150) node _T_3152 = eq(entries_st[0].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_3153 = bits(entries_st[0].bits.opa.bits.start.data, 11, 0) node _T_3154 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_3155 = lt(_T_3153, _T_3154) node _T_3156 = bits(entries_st[0].bits.opa.bits.start.data, 13, 0) node _T_3157 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_3158 = lt(_T_3156, _T_3157) node _T_3159 = mux(entries_st[0].bits.opa.bits.start.is_acc_addr, _T_3155, _T_3158) node _T_3160 = and(_T_3152, _T_3159) node _T_3161 = or(_T_3160, new_entry.opa.bits.wraps_around) node _T_3162 = and(_T_3151, _T_3161) node _T_3163 = or(_T_3142, _T_3162) node _T_3164 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_3165 = and(_T_3164, new_entry.opa.bits.start.read_full_acc_row) node _T_3166 = andr(new_entry.opa.bits.start.data) node _T_3167 = and(_T_3165, _T_3166) node _T_3168 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_3169 = and(_T_3167, _T_3168) node _T_3170 = and(entries_st[0].bits.opa.bits.start.is_acc_addr, entries_st[0].bits.opa.bits.start.accumulate) node _T_3171 = and(_T_3170, entries_st[0].bits.opa.bits.start.read_full_acc_row) node _T_3172 = andr(entries_st[0].bits.opa.bits.start.data) node _T_3173 = and(_T_3171, _T_3172) node _T_3174 = bits(entries_st[0].bits.opa.bits.start.garbage_bit, 0, 0) node _T_3175 = and(_T_3173, _T_3174) node _T_3176 = or(_T_3169, _T_3175) node _T_3177 = eq(_T_3176, UInt<1>(0h0)) node _T_3178 = and(_T_3163, _T_3177) node _T_3179 = and(_T_3122, _T_3178) node _T_3180 = and(entries_st[1].valid, entries_st[1].bits.opa.valid) node _T_3181 = and(_T_3180, not_config) node _T_3182 = and(_T_3181, new_entry.opa_is_dst) node _T_3183 = eq(entries_st[1].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_3184 = bits(entries_st[1].bits.opa.bits.start.data, 11, 0) node _T_3185 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_3186 = leq(_T_3184, _T_3185) node _T_3187 = bits(entries_st[1].bits.opa.bits.start.data, 13, 0) node _T_3188 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_3189 = leq(_T_3187, _T_3188) node _T_3190 = mux(entries_st[1].bits.opa.bits.start.is_acc_addr, _T_3186, _T_3189) node _T_3191 = and(_T_3183, _T_3190) node _T_3192 = eq(new_entry.opa.bits.start.is_acc_addr, entries_st[1].bits.opa.bits.end.is_acc_addr) node _T_3193 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_3194 = bits(entries_st[1].bits.opa.bits.end.data, 11, 0) node _T_3195 = lt(_T_3193, _T_3194) node _T_3196 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_3197 = bits(entries_st[1].bits.opa.bits.end.data, 13, 0) node _T_3198 = lt(_T_3196, _T_3197) node _T_3199 = mux(new_entry.opa.bits.start.is_acc_addr, _T_3195, _T_3198) node _T_3200 = and(_T_3192, _T_3199) node _T_3201 = or(_T_3200, entries_st[1].bits.opa.bits.wraps_around) node _T_3202 = and(_T_3191, _T_3201) node _T_3203 = eq(new_entry.opa.bits.start.is_acc_addr, entries_st[1].bits.opa.bits.start.is_acc_addr) node _T_3204 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_3205 = bits(entries_st[1].bits.opa.bits.start.data, 11, 0) node _T_3206 = leq(_T_3204, _T_3205) node _T_3207 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_3208 = bits(entries_st[1].bits.opa.bits.start.data, 13, 0) node _T_3209 = leq(_T_3207, _T_3208) node _T_3210 = mux(new_entry.opa.bits.start.is_acc_addr, _T_3206, _T_3209) node _T_3211 = and(_T_3203, _T_3210) node _T_3212 = eq(entries_st[1].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_3213 = bits(entries_st[1].bits.opa.bits.start.data, 11, 0) node _T_3214 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_3215 = lt(_T_3213, _T_3214) node _T_3216 = bits(entries_st[1].bits.opa.bits.start.data, 13, 0) node _T_3217 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_3218 = lt(_T_3216, _T_3217) node _T_3219 = mux(entries_st[1].bits.opa.bits.start.is_acc_addr, _T_3215, _T_3218) node _T_3220 = and(_T_3212, _T_3219) node _T_3221 = or(_T_3220, new_entry.opa.bits.wraps_around) node _T_3222 = and(_T_3211, _T_3221) node _T_3223 = or(_T_3202, _T_3222) node _T_3224 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_3225 = and(_T_3224, new_entry.opa.bits.start.read_full_acc_row) node _T_3226 = andr(new_entry.opa.bits.start.data) node _T_3227 = and(_T_3225, _T_3226) node _T_3228 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_3229 = and(_T_3227, _T_3228) node _T_3230 = and(entries_st[1].bits.opa.bits.start.is_acc_addr, entries_st[1].bits.opa.bits.start.accumulate) node _T_3231 = and(_T_3230, entries_st[1].bits.opa.bits.start.read_full_acc_row) node _T_3232 = andr(entries_st[1].bits.opa.bits.start.data) node _T_3233 = and(_T_3231, _T_3232) node _T_3234 = bits(entries_st[1].bits.opa.bits.start.garbage_bit, 0, 0) node _T_3235 = and(_T_3233, _T_3234) node _T_3236 = or(_T_3229, _T_3235) node _T_3237 = eq(_T_3236, UInt<1>(0h0)) node _T_3238 = and(_T_3223, _T_3237) node _T_3239 = and(_T_3182, _T_3238) node _T_3240 = and(entries_st[2].valid, entries_st[2].bits.opa.valid) node _T_3241 = and(_T_3240, not_config) node _T_3242 = and(_T_3241, new_entry.opa_is_dst) node _T_3243 = eq(entries_st[2].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_3244 = bits(entries_st[2].bits.opa.bits.start.data, 11, 0) node _T_3245 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_3246 = leq(_T_3244, _T_3245) node _T_3247 = bits(entries_st[2].bits.opa.bits.start.data, 13, 0) node _T_3248 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_3249 = leq(_T_3247, _T_3248) node _T_3250 = mux(entries_st[2].bits.opa.bits.start.is_acc_addr, _T_3246, _T_3249) node _T_3251 = and(_T_3243, _T_3250) node _T_3252 = eq(new_entry.opa.bits.start.is_acc_addr, entries_st[2].bits.opa.bits.end.is_acc_addr) node _T_3253 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_3254 = bits(entries_st[2].bits.opa.bits.end.data, 11, 0) node _T_3255 = lt(_T_3253, _T_3254) node _T_3256 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_3257 = bits(entries_st[2].bits.opa.bits.end.data, 13, 0) node _T_3258 = lt(_T_3256, _T_3257) node _T_3259 = mux(new_entry.opa.bits.start.is_acc_addr, _T_3255, _T_3258) node _T_3260 = and(_T_3252, _T_3259) node _T_3261 = or(_T_3260, entries_st[2].bits.opa.bits.wraps_around) node _T_3262 = and(_T_3251, _T_3261) node _T_3263 = eq(new_entry.opa.bits.start.is_acc_addr, entries_st[2].bits.opa.bits.start.is_acc_addr) node _T_3264 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_3265 = bits(entries_st[2].bits.opa.bits.start.data, 11, 0) node _T_3266 = leq(_T_3264, _T_3265) node _T_3267 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_3268 = bits(entries_st[2].bits.opa.bits.start.data, 13, 0) node _T_3269 = leq(_T_3267, _T_3268) node _T_3270 = mux(new_entry.opa.bits.start.is_acc_addr, _T_3266, _T_3269) node _T_3271 = and(_T_3263, _T_3270) node _T_3272 = eq(entries_st[2].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_3273 = bits(entries_st[2].bits.opa.bits.start.data, 11, 0) node _T_3274 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_3275 = lt(_T_3273, _T_3274) node _T_3276 = bits(entries_st[2].bits.opa.bits.start.data, 13, 0) node _T_3277 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_3278 = lt(_T_3276, _T_3277) node _T_3279 = mux(entries_st[2].bits.opa.bits.start.is_acc_addr, _T_3275, _T_3278) node _T_3280 = and(_T_3272, _T_3279) node _T_3281 = or(_T_3280, new_entry.opa.bits.wraps_around) node _T_3282 = and(_T_3271, _T_3281) node _T_3283 = or(_T_3262, _T_3282) node _T_3284 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_3285 = and(_T_3284, new_entry.opa.bits.start.read_full_acc_row) node _T_3286 = andr(new_entry.opa.bits.start.data) node _T_3287 = and(_T_3285, _T_3286) node _T_3288 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_3289 = and(_T_3287, _T_3288) node _T_3290 = and(entries_st[2].bits.opa.bits.start.is_acc_addr, entries_st[2].bits.opa.bits.start.accumulate) node _T_3291 = and(_T_3290, entries_st[2].bits.opa.bits.start.read_full_acc_row) node _T_3292 = andr(entries_st[2].bits.opa.bits.start.data) node _T_3293 = and(_T_3291, _T_3292) node _T_3294 = bits(entries_st[2].bits.opa.bits.start.garbage_bit, 0, 0) node _T_3295 = and(_T_3293, _T_3294) node _T_3296 = or(_T_3289, _T_3295) node _T_3297 = eq(_T_3296, UInt<1>(0h0)) node _T_3298 = and(_T_3283, _T_3297) node _T_3299 = and(_T_3242, _T_3298) node _T_3300 = and(entries_st[3].valid, entries_st[3].bits.opa.valid) node _T_3301 = and(_T_3300, not_config) node _T_3302 = and(_T_3301, new_entry.opa_is_dst) node _T_3303 = eq(entries_st[3].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_3304 = bits(entries_st[3].bits.opa.bits.start.data, 11, 0) node _T_3305 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_3306 = leq(_T_3304, _T_3305) node _T_3307 = bits(entries_st[3].bits.opa.bits.start.data, 13, 0) node _T_3308 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_3309 = leq(_T_3307, _T_3308) node _T_3310 = mux(entries_st[3].bits.opa.bits.start.is_acc_addr, _T_3306, _T_3309) node _T_3311 = and(_T_3303, _T_3310) node _T_3312 = eq(new_entry.opa.bits.start.is_acc_addr, entries_st[3].bits.opa.bits.end.is_acc_addr) node _T_3313 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_3314 = bits(entries_st[3].bits.opa.bits.end.data, 11, 0) node _T_3315 = lt(_T_3313, _T_3314) node _T_3316 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_3317 = bits(entries_st[3].bits.opa.bits.end.data, 13, 0) node _T_3318 = lt(_T_3316, _T_3317) node _T_3319 = mux(new_entry.opa.bits.start.is_acc_addr, _T_3315, _T_3318) node _T_3320 = and(_T_3312, _T_3319) node _T_3321 = or(_T_3320, entries_st[3].bits.opa.bits.wraps_around) node _T_3322 = and(_T_3311, _T_3321) node _T_3323 = eq(new_entry.opa.bits.start.is_acc_addr, entries_st[3].bits.opa.bits.start.is_acc_addr) node _T_3324 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_3325 = bits(entries_st[3].bits.opa.bits.start.data, 11, 0) node _T_3326 = leq(_T_3324, _T_3325) node _T_3327 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_3328 = bits(entries_st[3].bits.opa.bits.start.data, 13, 0) node _T_3329 = leq(_T_3327, _T_3328) node _T_3330 = mux(new_entry.opa.bits.start.is_acc_addr, _T_3326, _T_3329) node _T_3331 = and(_T_3323, _T_3330) node _T_3332 = eq(entries_st[3].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_3333 = bits(entries_st[3].bits.opa.bits.start.data, 11, 0) node _T_3334 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_3335 = lt(_T_3333, _T_3334) node _T_3336 = bits(entries_st[3].bits.opa.bits.start.data, 13, 0) node _T_3337 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_3338 = lt(_T_3336, _T_3337) node _T_3339 = mux(entries_st[3].bits.opa.bits.start.is_acc_addr, _T_3335, _T_3338) node _T_3340 = and(_T_3332, _T_3339) node _T_3341 = or(_T_3340, new_entry.opa.bits.wraps_around) node _T_3342 = and(_T_3331, _T_3341) node _T_3343 = or(_T_3322, _T_3342) node _T_3344 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_3345 = and(_T_3344, new_entry.opa.bits.start.read_full_acc_row) node _T_3346 = andr(new_entry.opa.bits.start.data) node _T_3347 = and(_T_3345, _T_3346) node _T_3348 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_3349 = and(_T_3347, _T_3348) node _T_3350 = and(entries_st[3].bits.opa.bits.start.is_acc_addr, entries_st[3].bits.opa.bits.start.accumulate) node _T_3351 = and(_T_3350, entries_st[3].bits.opa.bits.start.read_full_acc_row) node _T_3352 = andr(entries_st[3].bits.opa.bits.start.data) node _T_3353 = and(_T_3351, _T_3352) node _T_3354 = bits(entries_st[3].bits.opa.bits.start.garbage_bit, 0, 0) node _T_3355 = and(_T_3353, _T_3354) node _T_3356 = or(_T_3349, _T_3355) node _T_3357 = eq(_T_3356, UInt<1>(0h0)) node _T_3358 = and(_T_3343, _T_3357) node _T_3359 = and(_T_3302, _T_3358) wire _WIRE_5 : UInt<1>[4] connect _WIRE_5[0], _T_3179 connect _WIRE_5[1], _T_3239 connect _WIRE_5[2], _T_3299 connect _WIRE_5[3], _T_3359 connect new_entry.deps_st, _WIRE_5 else : node _T_3360 = and(entries_ld[0].valid, entries_ld[0].bits.opa.valid) node _T_3361 = and(_T_3360, not_config) node _T_3362 = eq(entries_ld[0].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_3363 = bits(entries_ld[0].bits.opa.bits.start.data, 11, 0) node _T_3364 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_3365 = leq(_T_3363, _T_3364) node _T_3366 = bits(entries_ld[0].bits.opa.bits.start.data, 13, 0) node _T_3367 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_3368 = leq(_T_3366, _T_3367) node _T_3369 = mux(entries_ld[0].bits.opa.bits.start.is_acc_addr, _T_3365, _T_3368) node _T_3370 = and(_T_3362, _T_3369) node _T_3371 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ld[0].bits.opa.bits.end.is_acc_addr) node _T_3372 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_3373 = bits(entries_ld[0].bits.opa.bits.end.data, 11, 0) node _T_3374 = lt(_T_3372, _T_3373) node _T_3375 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_3376 = bits(entries_ld[0].bits.opa.bits.end.data, 13, 0) node _T_3377 = lt(_T_3375, _T_3376) node _T_3378 = mux(new_entry.opa.bits.start.is_acc_addr, _T_3374, _T_3377) node _T_3379 = and(_T_3371, _T_3378) node _T_3380 = or(_T_3379, entries_ld[0].bits.opa.bits.wraps_around) node _T_3381 = and(_T_3370, _T_3380) node _T_3382 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ld[0].bits.opa.bits.start.is_acc_addr) node _T_3383 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_3384 = bits(entries_ld[0].bits.opa.bits.start.data, 11, 0) node _T_3385 = leq(_T_3383, _T_3384) node _T_3386 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_3387 = bits(entries_ld[0].bits.opa.bits.start.data, 13, 0) node _T_3388 = leq(_T_3386, _T_3387) node _T_3389 = mux(new_entry.opa.bits.start.is_acc_addr, _T_3385, _T_3388) node _T_3390 = and(_T_3382, _T_3389) node _T_3391 = eq(entries_ld[0].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_3392 = bits(entries_ld[0].bits.opa.bits.start.data, 11, 0) node _T_3393 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_3394 = lt(_T_3392, _T_3393) node _T_3395 = bits(entries_ld[0].bits.opa.bits.start.data, 13, 0) node _T_3396 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_3397 = lt(_T_3395, _T_3396) node _T_3398 = mux(entries_ld[0].bits.opa.bits.start.is_acc_addr, _T_3394, _T_3397) node _T_3399 = and(_T_3391, _T_3398) node _T_3400 = or(_T_3399, new_entry.opa.bits.wraps_around) node _T_3401 = and(_T_3390, _T_3400) node _T_3402 = or(_T_3381, _T_3401) node _T_3403 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_3404 = and(_T_3403, new_entry.opa.bits.start.read_full_acc_row) node _T_3405 = andr(new_entry.opa.bits.start.data) node _T_3406 = and(_T_3404, _T_3405) node _T_3407 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_3408 = and(_T_3406, _T_3407) node _T_3409 = and(entries_ld[0].bits.opa.bits.start.is_acc_addr, entries_ld[0].bits.opa.bits.start.accumulate) node _T_3410 = and(_T_3409, entries_ld[0].bits.opa.bits.start.read_full_acc_row) node _T_3411 = andr(entries_ld[0].bits.opa.bits.start.data) node _T_3412 = and(_T_3410, _T_3411) node _T_3413 = bits(entries_ld[0].bits.opa.bits.start.garbage_bit, 0, 0) node _T_3414 = and(_T_3412, _T_3413) node _T_3415 = or(_T_3408, _T_3414) node _T_3416 = eq(_T_3415, UInt<1>(0h0)) node _T_3417 = and(_T_3402, _T_3416) node _T_3418 = and(_T_3361, _T_3417) node _T_3419 = and(entries_ld[1].valid, entries_ld[1].bits.opa.valid) node _T_3420 = and(_T_3419, not_config) node _T_3421 = eq(entries_ld[1].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_3422 = bits(entries_ld[1].bits.opa.bits.start.data, 11, 0) node _T_3423 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_3424 = leq(_T_3422, _T_3423) node _T_3425 = bits(entries_ld[1].bits.opa.bits.start.data, 13, 0) node _T_3426 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_3427 = leq(_T_3425, _T_3426) node _T_3428 = mux(entries_ld[1].bits.opa.bits.start.is_acc_addr, _T_3424, _T_3427) node _T_3429 = and(_T_3421, _T_3428) node _T_3430 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ld[1].bits.opa.bits.end.is_acc_addr) node _T_3431 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_3432 = bits(entries_ld[1].bits.opa.bits.end.data, 11, 0) node _T_3433 = lt(_T_3431, _T_3432) node _T_3434 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_3435 = bits(entries_ld[1].bits.opa.bits.end.data, 13, 0) node _T_3436 = lt(_T_3434, _T_3435) node _T_3437 = mux(new_entry.opa.bits.start.is_acc_addr, _T_3433, _T_3436) node _T_3438 = and(_T_3430, _T_3437) node _T_3439 = or(_T_3438, entries_ld[1].bits.opa.bits.wraps_around) node _T_3440 = and(_T_3429, _T_3439) node _T_3441 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ld[1].bits.opa.bits.start.is_acc_addr) node _T_3442 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_3443 = bits(entries_ld[1].bits.opa.bits.start.data, 11, 0) node _T_3444 = leq(_T_3442, _T_3443) node _T_3445 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_3446 = bits(entries_ld[1].bits.opa.bits.start.data, 13, 0) node _T_3447 = leq(_T_3445, _T_3446) node _T_3448 = mux(new_entry.opa.bits.start.is_acc_addr, _T_3444, _T_3447) node _T_3449 = and(_T_3441, _T_3448) node _T_3450 = eq(entries_ld[1].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_3451 = bits(entries_ld[1].bits.opa.bits.start.data, 11, 0) node _T_3452 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_3453 = lt(_T_3451, _T_3452) node _T_3454 = bits(entries_ld[1].bits.opa.bits.start.data, 13, 0) node _T_3455 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_3456 = lt(_T_3454, _T_3455) node _T_3457 = mux(entries_ld[1].bits.opa.bits.start.is_acc_addr, _T_3453, _T_3456) node _T_3458 = and(_T_3450, _T_3457) node _T_3459 = or(_T_3458, new_entry.opa.bits.wraps_around) node _T_3460 = and(_T_3449, _T_3459) node _T_3461 = or(_T_3440, _T_3460) node _T_3462 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_3463 = and(_T_3462, new_entry.opa.bits.start.read_full_acc_row) node _T_3464 = andr(new_entry.opa.bits.start.data) node _T_3465 = and(_T_3463, _T_3464) node _T_3466 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_3467 = and(_T_3465, _T_3466) node _T_3468 = and(entries_ld[1].bits.opa.bits.start.is_acc_addr, entries_ld[1].bits.opa.bits.start.accumulate) node _T_3469 = and(_T_3468, entries_ld[1].bits.opa.bits.start.read_full_acc_row) node _T_3470 = andr(entries_ld[1].bits.opa.bits.start.data) node _T_3471 = and(_T_3469, _T_3470) node _T_3472 = bits(entries_ld[1].bits.opa.bits.start.garbage_bit, 0, 0) node _T_3473 = and(_T_3471, _T_3472) node _T_3474 = or(_T_3467, _T_3473) node _T_3475 = eq(_T_3474, UInt<1>(0h0)) node _T_3476 = and(_T_3461, _T_3475) node _T_3477 = and(_T_3420, _T_3476) node _T_3478 = and(entries_ld[2].valid, entries_ld[2].bits.opa.valid) node _T_3479 = and(_T_3478, not_config) node _T_3480 = eq(entries_ld[2].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_3481 = bits(entries_ld[2].bits.opa.bits.start.data, 11, 0) node _T_3482 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_3483 = leq(_T_3481, _T_3482) node _T_3484 = bits(entries_ld[2].bits.opa.bits.start.data, 13, 0) node _T_3485 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_3486 = leq(_T_3484, _T_3485) node _T_3487 = mux(entries_ld[2].bits.opa.bits.start.is_acc_addr, _T_3483, _T_3486) node _T_3488 = and(_T_3480, _T_3487) node _T_3489 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ld[2].bits.opa.bits.end.is_acc_addr) node _T_3490 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_3491 = bits(entries_ld[2].bits.opa.bits.end.data, 11, 0) node _T_3492 = lt(_T_3490, _T_3491) node _T_3493 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_3494 = bits(entries_ld[2].bits.opa.bits.end.data, 13, 0) node _T_3495 = lt(_T_3493, _T_3494) node _T_3496 = mux(new_entry.opa.bits.start.is_acc_addr, _T_3492, _T_3495) node _T_3497 = and(_T_3489, _T_3496) node _T_3498 = or(_T_3497, entries_ld[2].bits.opa.bits.wraps_around) node _T_3499 = and(_T_3488, _T_3498) node _T_3500 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ld[2].bits.opa.bits.start.is_acc_addr) node _T_3501 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_3502 = bits(entries_ld[2].bits.opa.bits.start.data, 11, 0) node _T_3503 = leq(_T_3501, _T_3502) node _T_3504 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_3505 = bits(entries_ld[2].bits.opa.bits.start.data, 13, 0) node _T_3506 = leq(_T_3504, _T_3505) node _T_3507 = mux(new_entry.opa.bits.start.is_acc_addr, _T_3503, _T_3506) node _T_3508 = and(_T_3500, _T_3507) node _T_3509 = eq(entries_ld[2].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_3510 = bits(entries_ld[2].bits.opa.bits.start.data, 11, 0) node _T_3511 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_3512 = lt(_T_3510, _T_3511) node _T_3513 = bits(entries_ld[2].bits.opa.bits.start.data, 13, 0) node _T_3514 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_3515 = lt(_T_3513, _T_3514) node _T_3516 = mux(entries_ld[2].bits.opa.bits.start.is_acc_addr, _T_3512, _T_3515) node _T_3517 = and(_T_3509, _T_3516) node _T_3518 = or(_T_3517, new_entry.opa.bits.wraps_around) node _T_3519 = and(_T_3508, _T_3518) node _T_3520 = or(_T_3499, _T_3519) node _T_3521 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_3522 = and(_T_3521, new_entry.opa.bits.start.read_full_acc_row) node _T_3523 = andr(new_entry.opa.bits.start.data) node _T_3524 = and(_T_3522, _T_3523) node _T_3525 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_3526 = and(_T_3524, _T_3525) node _T_3527 = and(entries_ld[2].bits.opa.bits.start.is_acc_addr, entries_ld[2].bits.opa.bits.start.accumulate) node _T_3528 = and(_T_3527, entries_ld[2].bits.opa.bits.start.read_full_acc_row) node _T_3529 = andr(entries_ld[2].bits.opa.bits.start.data) node _T_3530 = and(_T_3528, _T_3529) node _T_3531 = bits(entries_ld[2].bits.opa.bits.start.garbage_bit, 0, 0) node _T_3532 = and(_T_3530, _T_3531) node _T_3533 = or(_T_3526, _T_3532) node _T_3534 = eq(_T_3533, UInt<1>(0h0)) node _T_3535 = and(_T_3520, _T_3534) node _T_3536 = and(_T_3479, _T_3535) node _T_3537 = and(entries_ld[3].valid, entries_ld[3].bits.opa.valid) node _T_3538 = and(_T_3537, not_config) node _T_3539 = eq(entries_ld[3].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_3540 = bits(entries_ld[3].bits.opa.bits.start.data, 11, 0) node _T_3541 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_3542 = leq(_T_3540, _T_3541) node _T_3543 = bits(entries_ld[3].bits.opa.bits.start.data, 13, 0) node _T_3544 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_3545 = leq(_T_3543, _T_3544) node _T_3546 = mux(entries_ld[3].bits.opa.bits.start.is_acc_addr, _T_3542, _T_3545) node _T_3547 = and(_T_3539, _T_3546) node _T_3548 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ld[3].bits.opa.bits.end.is_acc_addr) node _T_3549 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_3550 = bits(entries_ld[3].bits.opa.bits.end.data, 11, 0) node _T_3551 = lt(_T_3549, _T_3550) node _T_3552 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_3553 = bits(entries_ld[3].bits.opa.bits.end.data, 13, 0) node _T_3554 = lt(_T_3552, _T_3553) node _T_3555 = mux(new_entry.opa.bits.start.is_acc_addr, _T_3551, _T_3554) node _T_3556 = and(_T_3548, _T_3555) node _T_3557 = or(_T_3556, entries_ld[3].bits.opa.bits.wraps_around) node _T_3558 = and(_T_3547, _T_3557) node _T_3559 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ld[3].bits.opa.bits.start.is_acc_addr) node _T_3560 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_3561 = bits(entries_ld[3].bits.opa.bits.start.data, 11, 0) node _T_3562 = leq(_T_3560, _T_3561) node _T_3563 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_3564 = bits(entries_ld[3].bits.opa.bits.start.data, 13, 0) node _T_3565 = leq(_T_3563, _T_3564) node _T_3566 = mux(new_entry.opa.bits.start.is_acc_addr, _T_3562, _T_3565) node _T_3567 = and(_T_3559, _T_3566) node _T_3568 = eq(entries_ld[3].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_3569 = bits(entries_ld[3].bits.opa.bits.start.data, 11, 0) node _T_3570 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_3571 = lt(_T_3569, _T_3570) node _T_3572 = bits(entries_ld[3].bits.opa.bits.start.data, 13, 0) node _T_3573 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_3574 = lt(_T_3572, _T_3573) node _T_3575 = mux(entries_ld[3].bits.opa.bits.start.is_acc_addr, _T_3571, _T_3574) node _T_3576 = and(_T_3568, _T_3575) node _T_3577 = or(_T_3576, new_entry.opa.bits.wraps_around) node _T_3578 = and(_T_3567, _T_3577) node _T_3579 = or(_T_3558, _T_3578) node _T_3580 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_3581 = and(_T_3580, new_entry.opa.bits.start.read_full_acc_row) node _T_3582 = andr(new_entry.opa.bits.start.data) node _T_3583 = and(_T_3581, _T_3582) node _T_3584 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_3585 = and(_T_3583, _T_3584) node _T_3586 = and(entries_ld[3].bits.opa.bits.start.is_acc_addr, entries_ld[3].bits.opa.bits.start.accumulate) node _T_3587 = and(_T_3586, entries_ld[3].bits.opa.bits.start.read_full_acc_row) node _T_3588 = andr(entries_ld[3].bits.opa.bits.start.data) node _T_3589 = and(_T_3587, _T_3588) node _T_3590 = bits(entries_ld[3].bits.opa.bits.start.garbage_bit, 0, 0) node _T_3591 = and(_T_3589, _T_3590) node _T_3592 = or(_T_3585, _T_3591) node _T_3593 = eq(_T_3592, UInt<1>(0h0)) node _T_3594 = and(_T_3579, _T_3593) node _T_3595 = and(_T_3538, _T_3594) node _T_3596 = and(entries_ld[4].valid, entries_ld[4].bits.opa.valid) node _T_3597 = and(_T_3596, not_config) node _T_3598 = eq(entries_ld[4].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_3599 = bits(entries_ld[4].bits.opa.bits.start.data, 11, 0) node _T_3600 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_3601 = leq(_T_3599, _T_3600) node _T_3602 = bits(entries_ld[4].bits.opa.bits.start.data, 13, 0) node _T_3603 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_3604 = leq(_T_3602, _T_3603) node _T_3605 = mux(entries_ld[4].bits.opa.bits.start.is_acc_addr, _T_3601, _T_3604) node _T_3606 = and(_T_3598, _T_3605) node _T_3607 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ld[4].bits.opa.bits.end.is_acc_addr) node _T_3608 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_3609 = bits(entries_ld[4].bits.opa.bits.end.data, 11, 0) node _T_3610 = lt(_T_3608, _T_3609) node _T_3611 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_3612 = bits(entries_ld[4].bits.opa.bits.end.data, 13, 0) node _T_3613 = lt(_T_3611, _T_3612) node _T_3614 = mux(new_entry.opa.bits.start.is_acc_addr, _T_3610, _T_3613) node _T_3615 = and(_T_3607, _T_3614) node _T_3616 = or(_T_3615, entries_ld[4].bits.opa.bits.wraps_around) node _T_3617 = and(_T_3606, _T_3616) node _T_3618 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ld[4].bits.opa.bits.start.is_acc_addr) node _T_3619 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_3620 = bits(entries_ld[4].bits.opa.bits.start.data, 11, 0) node _T_3621 = leq(_T_3619, _T_3620) node _T_3622 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_3623 = bits(entries_ld[4].bits.opa.bits.start.data, 13, 0) node _T_3624 = leq(_T_3622, _T_3623) node _T_3625 = mux(new_entry.opa.bits.start.is_acc_addr, _T_3621, _T_3624) node _T_3626 = and(_T_3618, _T_3625) node _T_3627 = eq(entries_ld[4].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_3628 = bits(entries_ld[4].bits.opa.bits.start.data, 11, 0) node _T_3629 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_3630 = lt(_T_3628, _T_3629) node _T_3631 = bits(entries_ld[4].bits.opa.bits.start.data, 13, 0) node _T_3632 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_3633 = lt(_T_3631, _T_3632) node _T_3634 = mux(entries_ld[4].bits.opa.bits.start.is_acc_addr, _T_3630, _T_3633) node _T_3635 = and(_T_3627, _T_3634) node _T_3636 = or(_T_3635, new_entry.opa.bits.wraps_around) node _T_3637 = and(_T_3626, _T_3636) node _T_3638 = or(_T_3617, _T_3637) node _T_3639 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_3640 = and(_T_3639, new_entry.opa.bits.start.read_full_acc_row) node _T_3641 = andr(new_entry.opa.bits.start.data) node _T_3642 = and(_T_3640, _T_3641) node _T_3643 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_3644 = and(_T_3642, _T_3643) node _T_3645 = and(entries_ld[4].bits.opa.bits.start.is_acc_addr, entries_ld[4].bits.opa.bits.start.accumulate) node _T_3646 = and(_T_3645, entries_ld[4].bits.opa.bits.start.read_full_acc_row) node _T_3647 = andr(entries_ld[4].bits.opa.bits.start.data) node _T_3648 = and(_T_3646, _T_3647) node _T_3649 = bits(entries_ld[4].bits.opa.bits.start.garbage_bit, 0, 0) node _T_3650 = and(_T_3648, _T_3649) node _T_3651 = or(_T_3644, _T_3650) node _T_3652 = eq(_T_3651, UInt<1>(0h0)) node _T_3653 = and(_T_3638, _T_3652) node _T_3654 = and(_T_3597, _T_3653) node _T_3655 = and(entries_ld[5].valid, entries_ld[5].bits.opa.valid) node _T_3656 = and(_T_3655, not_config) node _T_3657 = eq(entries_ld[5].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_3658 = bits(entries_ld[5].bits.opa.bits.start.data, 11, 0) node _T_3659 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_3660 = leq(_T_3658, _T_3659) node _T_3661 = bits(entries_ld[5].bits.opa.bits.start.data, 13, 0) node _T_3662 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_3663 = leq(_T_3661, _T_3662) node _T_3664 = mux(entries_ld[5].bits.opa.bits.start.is_acc_addr, _T_3660, _T_3663) node _T_3665 = and(_T_3657, _T_3664) node _T_3666 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ld[5].bits.opa.bits.end.is_acc_addr) node _T_3667 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_3668 = bits(entries_ld[5].bits.opa.bits.end.data, 11, 0) node _T_3669 = lt(_T_3667, _T_3668) node _T_3670 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_3671 = bits(entries_ld[5].bits.opa.bits.end.data, 13, 0) node _T_3672 = lt(_T_3670, _T_3671) node _T_3673 = mux(new_entry.opa.bits.start.is_acc_addr, _T_3669, _T_3672) node _T_3674 = and(_T_3666, _T_3673) node _T_3675 = or(_T_3674, entries_ld[5].bits.opa.bits.wraps_around) node _T_3676 = and(_T_3665, _T_3675) node _T_3677 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ld[5].bits.opa.bits.start.is_acc_addr) node _T_3678 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_3679 = bits(entries_ld[5].bits.opa.bits.start.data, 11, 0) node _T_3680 = leq(_T_3678, _T_3679) node _T_3681 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_3682 = bits(entries_ld[5].bits.opa.bits.start.data, 13, 0) node _T_3683 = leq(_T_3681, _T_3682) node _T_3684 = mux(new_entry.opa.bits.start.is_acc_addr, _T_3680, _T_3683) node _T_3685 = and(_T_3677, _T_3684) node _T_3686 = eq(entries_ld[5].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_3687 = bits(entries_ld[5].bits.opa.bits.start.data, 11, 0) node _T_3688 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_3689 = lt(_T_3687, _T_3688) node _T_3690 = bits(entries_ld[5].bits.opa.bits.start.data, 13, 0) node _T_3691 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_3692 = lt(_T_3690, _T_3691) node _T_3693 = mux(entries_ld[5].bits.opa.bits.start.is_acc_addr, _T_3689, _T_3692) node _T_3694 = and(_T_3686, _T_3693) node _T_3695 = or(_T_3694, new_entry.opa.bits.wraps_around) node _T_3696 = and(_T_3685, _T_3695) node _T_3697 = or(_T_3676, _T_3696) node _T_3698 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_3699 = and(_T_3698, new_entry.opa.bits.start.read_full_acc_row) node _T_3700 = andr(new_entry.opa.bits.start.data) node _T_3701 = and(_T_3699, _T_3700) node _T_3702 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_3703 = and(_T_3701, _T_3702) node _T_3704 = and(entries_ld[5].bits.opa.bits.start.is_acc_addr, entries_ld[5].bits.opa.bits.start.accumulate) node _T_3705 = and(_T_3704, entries_ld[5].bits.opa.bits.start.read_full_acc_row) node _T_3706 = andr(entries_ld[5].bits.opa.bits.start.data) node _T_3707 = and(_T_3705, _T_3706) node _T_3708 = bits(entries_ld[5].bits.opa.bits.start.garbage_bit, 0, 0) node _T_3709 = and(_T_3707, _T_3708) node _T_3710 = or(_T_3703, _T_3709) node _T_3711 = eq(_T_3710, UInt<1>(0h0)) node _T_3712 = and(_T_3697, _T_3711) node _T_3713 = and(_T_3656, _T_3712) node _T_3714 = and(entries_ld[6].valid, entries_ld[6].bits.opa.valid) node _T_3715 = and(_T_3714, not_config) node _T_3716 = eq(entries_ld[6].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_3717 = bits(entries_ld[6].bits.opa.bits.start.data, 11, 0) node _T_3718 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_3719 = leq(_T_3717, _T_3718) node _T_3720 = bits(entries_ld[6].bits.opa.bits.start.data, 13, 0) node _T_3721 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_3722 = leq(_T_3720, _T_3721) node _T_3723 = mux(entries_ld[6].bits.opa.bits.start.is_acc_addr, _T_3719, _T_3722) node _T_3724 = and(_T_3716, _T_3723) node _T_3725 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ld[6].bits.opa.bits.end.is_acc_addr) node _T_3726 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_3727 = bits(entries_ld[6].bits.opa.bits.end.data, 11, 0) node _T_3728 = lt(_T_3726, _T_3727) node _T_3729 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_3730 = bits(entries_ld[6].bits.opa.bits.end.data, 13, 0) node _T_3731 = lt(_T_3729, _T_3730) node _T_3732 = mux(new_entry.opa.bits.start.is_acc_addr, _T_3728, _T_3731) node _T_3733 = and(_T_3725, _T_3732) node _T_3734 = or(_T_3733, entries_ld[6].bits.opa.bits.wraps_around) node _T_3735 = and(_T_3724, _T_3734) node _T_3736 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ld[6].bits.opa.bits.start.is_acc_addr) node _T_3737 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_3738 = bits(entries_ld[6].bits.opa.bits.start.data, 11, 0) node _T_3739 = leq(_T_3737, _T_3738) node _T_3740 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_3741 = bits(entries_ld[6].bits.opa.bits.start.data, 13, 0) node _T_3742 = leq(_T_3740, _T_3741) node _T_3743 = mux(new_entry.opa.bits.start.is_acc_addr, _T_3739, _T_3742) node _T_3744 = and(_T_3736, _T_3743) node _T_3745 = eq(entries_ld[6].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_3746 = bits(entries_ld[6].bits.opa.bits.start.data, 11, 0) node _T_3747 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_3748 = lt(_T_3746, _T_3747) node _T_3749 = bits(entries_ld[6].bits.opa.bits.start.data, 13, 0) node _T_3750 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_3751 = lt(_T_3749, _T_3750) node _T_3752 = mux(entries_ld[6].bits.opa.bits.start.is_acc_addr, _T_3748, _T_3751) node _T_3753 = and(_T_3745, _T_3752) node _T_3754 = or(_T_3753, new_entry.opa.bits.wraps_around) node _T_3755 = and(_T_3744, _T_3754) node _T_3756 = or(_T_3735, _T_3755) node _T_3757 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_3758 = and(_T_3757, new_entry.opa.bits.start.read_full_acc_row) node _T_3759 = andr(new_entry.opa.bits.start.data) node _T_3760 = and(_T_3758, _T_3759) node _T_3761 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_3762 = and(_T_3760, _T_3761) node _T_3763 = and(entries_ld[6].bits.opa.bits.start.is_acc_addr, entries_ld[6].bits.opa.bits.start.accumulate) node _T_3764 = and(_T_3763, entries_ld[6].bits.opa.bits.start.read_full_acc_row) node _T_3765 = andr(entries_ld[6].bits.opa.bits.start.data) node _T_3766 = and(_T_3764, _T_3765) node _T_3767 = bits(entries_ld[6].bits.opa.bits.start.garbage_bit, 0, 0) node _T_3768 = and(_T_3766, _T_3767) node _T_3769 = or(_T_3762, _T_3768) node _T_3770 = eq(_T_3769, UInt<1>(0h0)) node _T_3771 = and(_T_3756, _T_3770) node _T_3772 = and(_T_3715, _T_3771) node _T_3773 = and(entries_ld[7].valid, entries_ld[7].bits.opa.valid) node _T_3774 = and(_T_3773, not_config) node _T_3775 = eq(entries_ld[7].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_3776 = bits(entries_ld[7].bits.opa.bits.start.data, 11, 0) node _T_3777 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_3778 = leq(_T_3776, _T_3777) node _T_3779 = bits(entries_ld[7].bits.opa.bits.start.data, 13, 0) node _T_3780 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_3781 = leq(_T_3779, _T_3780) node _T_3782 = mux(entries_ld[7].bits.opa.bits.start.is_acc_addr, _T_3778, _T_3781) node _T_3783 = and(_T_3775, _T_3782) node _T_3784 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ld[7].bits.opa.bits.end.is_acc_addr) node _T_3785 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_3786 = bits(entries_ld[7].bits.opa.bits.end.data, 11, 0) node _T_3787 = lt(_T_3785, _T_3786) node _T_3788 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_3789 = bits(entries_ld[7].bits.opa.bits.end.data, 13, 0) node _T_3790 = lt(_T_3788, _T_3789) node _T_3791 = mux(new_entry.opa.bits.start.is_acc_addr, _T_3787, _T_3790) node _T_3792 = and(_T_3784, _T_3791) node _T_3793 = or(_T_3792, entries_ld[7].bits.opa.bits.wraps_around) node _T_3794 = and(_T_3783, _T_3793) node _T_3795 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ld[7].bits.opa.bits.start.is_acc_addr) node _T_3796 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_3797 = bits(entries_ld[7].bits.opa.bits.start.data, 11, 0) node _T_3798 = leq(_T_3796, _T_3797) node _T_3799 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_3800 = bits(entries_ld[7].bits.opa.bits.start.data, 13, 0) node _T_3801 = leq(_T_3799, _T_3800) node _T_3802 = mux(new_entry.opa.bits.start.is_acc_addr, _T_3798, _T_3801) node _T_3803 = and(_T_3795, _T_3802) node _T_3804 = eq(entries_ld[7].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_3805 = bits(entries_ld[7].bits.opa.bits.start.data, 11, 0) node _T_3806 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_3807 = lt(_T_3805, _T_3806) node _T_3808 = bits(entries_ld[7].bits.opa.bits.start.data, 13, 0) node _T_3809 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_3810 = lt(_T_3808, _T_3809) node _T_3811 = mux(entries_ld[7].bits.opa.bits.start.is_acc_addr, _T_3807, _T_3810) node _T_3812 = and(_T_3804, _T_3811) node _T_3813 = or(_T_3812, new_entry.opa.bits.wraps_around) node _T_3814 = and(_T_3803, _T_3813) node _T_3815 = or(_T_3794, _T_3814) node _T_3816 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_3817 = and(_T_3816, new_entry.opa.bits.start.read_full_acc_row) node _T_3818 = andr(new_entry.opa.bits.start.data) node _T_3819 = and(_T_3817, _T_3818) node _T_3820 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_3821 = and(_T_3819, _T_3820) node _T_3822 = and(entries_ld[7].bits.opa.bits.start.is_acc_addr, entries_ld[7].bits.opa.bits.start.accumulate) node _T_3823 = and(_T_3822, entries_ld[7].bits.opa.bits.start.read_full_acc_row) node _T_3824 = andr(entries_ld[7].bits.opa.bits.start.data) node _T_3825 = and(_T_3823, _T_3824) node _T_3826 = bits(entries_ld[7].bits.opa.bits.start.garbage_bit, 0, 0) node _T_3827 = and(_T_3825, _T_3826) node _T_3828 = or(_T_3821, _T_3827) node _T_3829 = eq(_T_3828, UInt<1>(0h0)) node _T_3830 = and(_T_3815, _T_3829) node _T_3831 = and(_T_3774, _T_3830) wire _WIRE_6 : UInt<1>[8] connect _WIRE_6[0], _T_3418 connect _WIRE_6[1], _T_3477 connect _WIRE_6[2], _T_3536 connect _WIRE_6[3], _T_3595 connect _WIRE_6[4], _T_3654 connect _WIRE_6[5], _T_3713 connect _WIRE_6[6], _T_3772 connect _WIRE_6[7], _T_3831 connect new_entry.deps_ld, _WIRE_6 node _T_3832 = and(entries_ex[0].valid, entries_ex[0].bits.opa.valid) node _T_3833 = and(_T_3832, not_config) node _T_3834 = and(_T_3833, entries_ex[0].bits.opa_is_dst) node _T_3835 = eq(entries_ex[0].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_3836 = bits(entries_ex[0].bits.opa.bits.start.data, 11, 0) node _T_3837 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_3838 = leq(_T_3836, _T_3837) node _T_3839 = bits(entries_ex[0].bits.opa.bits.start.data, 13, 0) node _T_3840 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_3841 = leq(_T_3839, _T_3840) node _T_3842 = mux(entries_ex[0].bits.opa.bits.start.is_acc_addr, _T_3838, _T_3841) node _T_3843 = and(_T_3835, _T_3842) node _T_3844 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[0].bits.opa.bits.end.is_acc_addr) node _T_3845 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_3846 = bits(entries_ex[0].bits.opa.bits.end.data, 11, 0) node _T_3847 = lt(_T_3845, _T_3846) node _T_3848 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_3849 = bits(entries_ex[0].bits.opa.bits.end.data, 13, 0) node _T_3850 = lt(_T_3848, _T_3849) node _T_3851 = mux(new_entry.opa.bits.start.is_acc_addr, _T_3847, _T_3850) node _T_3852 = and(_T_3844, _T_3851) node _T_3853 = or(_T_3852, entries_ex[0].bits.opa.bits.wraps_around) node _T_3854 = and(_T_3843, _T_3853) node _T_3855 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[0].bits.opa.bits.start.is_acc_addr) node _T_3856 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_3857 = bits(entries_ex[0].bits.opa.bits.start.data, 11, 0) node _T_3858 = leq(_T_3856, _T_3857) node _T_3859 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_3860 = bits(entries_ex[0].bits.opa.bits.start.data, 13, 0) node _T_3861 = leq(_T_3859, _T_3860) node _T_3862 = mux(new_entry.opa.bits.start.is_acc_addr, _T_3858, _T_3861) node _T_3863 = and(_T_3855, _T_3862) node _T_3864 = eq(entries_ex[0].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_3865 = bits(entries_ex[0].bits.opa.bits.start.data, 11, 0) node _T_3866 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_3867 = lt(_T_3865, _T_3866) node _T_3868 = bits(entries_ex[0].bits.opa.bits.start.data, 13, 0) node _T_3869 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_3870 = lt(_T_3868, _T_3869) node _T_3871 = mux(entries_ex[0].bits.opa.bits.start.is_acc_addr, _T_3867, _T_3870) node _T_3872 = and(_T_3864, _T_3871) node _T_3873 = or(_T_3872, new_entry.opa.bits.wraps_around) node _T_3874 = and(_T_3863, _T_3873) node _T_3875 = or(_T_3854, _T_3874) node _T_3876 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_3877 = and(_T_3876, new_entry.opa.bits.start.read_full_acc_row) node _T_3878 = andr(new_entry.opa.bits.start.data) node _T_3879 = and(_T_3877, _T_3878) node _T_3880 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_3881 = and(_T_3879, _T_3880) node _T_3882 = and(entries_ex[0].bits.opa.bits.start.is_acc_addr, entries_ex[0].bits.opa.bits.start.accumulate) node _T_3883 = and(_T_3882, entries_ex[0].bits.opa.bits.start.read_full_acc_row) node _T_3884 = andr(entries_ex[0].bits.opa.bits.start.data) node _T_3885 = and(_T_3883, _T_3884) node _T_3886 = bits(entries_ex[0].bits.opa.bits.start.garbage_bit, 0, 0) node _T_3887 = and(_T_3885, _T_3886) node _T_3888 = or(_T_3881, _T_3887) node _T_3889 = eq(_T_3888, UInt<1>(0h0)) node _T_3890 = and(_T_3875, _T_3889) node _T_3891 = and(_T_3834, _T_3890) node _T_3892 = and(entries_ex[1].valid, entries_ex[1].bits.opa.valid) node _T_3893 = and(_T_3892, not_config) node _T_3894 = and(_T_3893, entries_ex[1].bits.opa_is_dst) node _T_3895 = eq(entries_ex[1].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_3896 = bits(entries_ex[1].bits.opa.bits.start.data, 11, 0) node _T_3897 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_3898 = leq(_T_3896, _T_3897) node _T_3899 = bits(entries_ex[1].bits.opa.bits.start.data, 13, 0) node _T_3900 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_3901 = leq(_T_3899, _T_3900) node _T_3902 = mux(entries_ex[1].bits.opa.bits.start.is_acc_addr, _T_3898, _T_3901) node _T_3903 = and(_T_3895, _T_3902) node _T_3904 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[1].bits.opa.bits.end.is_acc_addr) node _T_3905 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_3906 = bits(entries_ex[1].bits.opa.bits.end.data, 11, 0) node _T_3907 = lt(_T_3905, _T_3906) node _T_3908 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_3909 = bits(entries_ex[1].bits.opa.bits.end.data, 13, 0) node _T_3910 = lt(_T_3908, _T_3909) node _T_3911 = mux(new_entry.opa.bits.start.is_acc_addr, _T_3907, _T_3910) node _T_3912 = and(_T_3904, _T_3911) node _T_3913 = or(_T_3912, entries_ex[1].bits.opa.bits.wraps_around) node _T_3914 = and(_T_3903, _T_3913) node _T_3915 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[1].bits.opa.bits.start.is_acc_addr) node _T_3916 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_3917 = bits(entries_ex[1].bits.opa.bits.start.data, 11, 0) node _T_3918 = leq(_T_3916, _T_3917) node _T_3919 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_3920 = bits(entries_ex[1].bits.opa.bits.start.data, 13, 0) node _T_3921 = leq(_T_3919, _T_3920) node _T_3922 = mux(new_entry.opa.bits.start.is_acc_addr, _T_3918, _T_3921) node _T_3923 = and(_T_3915, _T_3922) node _T_3924 = eq(entries_ex[1].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_3925 = bits(entries_ex[1].bits.opa.bits.start.data, 11, 0) node _T_3926 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_3927 = lt(_T_3925, _T_3926) node _T_3928 = bits(entries_ex[1].bits.opa.bits.start.data, 13, 0) node _T_3929 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_3930 = lt(_T_3928, _T_3929) node _T_3931 = mux(entries_ex[1].bits.opa.bits.start.is_acc_addr, _T_3927, _T_3930) node _T_3932 = and(_T_3924, _T_3931) node _T_3933 = or(_T_3932, new_entry.opa.bits.wraps_around) node _T_3934 = and(_T_3923, _T_3933) node _T_3935 = or(_T_3914, _T_3934) node _T_3936 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_3937 = and(_T_3936, new_entry.opa.bits.start.read_full_acc_row) node _T_3938 = andr(new_entry.opa.bits.start.data) node _T_3939 = and(_T_3937, _T_3938) node _T_3940 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_3941 = and(_T_3939, _T_3940) node _T_3942 = and(entries_ex[1].bits.opa.bits.start.is_acc_addr, entries_ex[1].bits.opa.bits.start.accumulate) node _T_3943 = and(_T_3942, entries_ex[1].bits.opa.bits.start.read_full_acc_row) node _T_3944 = andr(entries_ex[1].bits.opa.bits.start.data) node _T_3945 = and(_T_3943, _T_3944) node _T_3946 = bits(entries_ex[1].bits.opa.bits.start.garbage_bit, 0, 0) node _T_3947 = and(_T_3945, _T_3946) node _T_3948 = or(_T_3941, _T_3947) node _T_3949 = eq(_T_3948, UInt<1>(0h0)) node _T_3950 = and(_T_3935, _T_3949) node _T_3951 = and(_T_3894, _T_3950) node _T_3952 = and(entries_ex[2].valid, entries_ex[2].bits.opa.valid) node _T_3953 = and(_T_3952, not_config) node _T_3954 = and(_T_3953, entries_ex[2].bits.opa_is_dst) node _T_3955 = eq(entries_ex[2].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_3956 = bits(entries_ex[2].bits.opa.bits.start.data, 11, 0) node _T_3957 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_3958 = leq(_T_3956, _T_3957) node _T_3959 = bits(entries_ex[2].bits.opa.bits.start.data, 13, 0) node _T_3960 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_3961 = leq(_T_3959, _T_3960) node _T_3962 = mux(entries_ex[2].bits.opa.bits.start.is_acc_addr, _T_3958, _T_3961) node _T_3963 = and(_T_3955, _T_3962) node _T_3964 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[2].bits.opa.bits.end.is_acc_addr) node _T_3965 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_3966 = bits(entries_ex[2].bits.opa.bits.end.data, 11, 0) node _T_3967 = lt(_T_3965, _T_3966) node _T_3968 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_3969 = bits(entries_ex[2].bits.opa.bits.end.data, 13, 0) node _T_3970 = lt(_T_3968, _T_3969) node _T_3971 = mux(new_entry.opa.bits.start.is_acc_addr, _T_3967, _T_3970) node _T_3972 = and(_T_3964, _T_3971) node _T_3973 = or(_T_3972, entries_ex[2].bits.opa.bits.wraps_around) node _T_3974 = and(_T_3963, _T_3973) node _T_3975 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[2].bits.opa.bits.start.is_acc_addr) node _T_3976 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_3977 = bits(entries_ex[2].bits.opa.bits.start.data, 11, 0) node _T_3978 = leq(_T_3976, _T_3977) node _T_3979 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_3980 = bits(entries_ex[2].bits.opa.bits.start.data, 13, 0) node _T_3981 = leq(_T_3979, _T_3980) node _T_3982 = mux(new_entry.opa.bits.start.is_acc_addr, _T_3978, _T_3981) node _T_3983 = and(_T_3975, _T_3982) node _T_3984 = eq(entries_ex[2].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_3985 = bits(entries_ex[2].bits.opa.bits.start.data, 11, 0) node _T_3986 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_3987 = lt(_T_3985, _T_3986) node _T_3988 = bits(entries_ex[2].bits.opa.bits.start.data, 13, 0) node _T_3989 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_3990 = lt(_T_3988, _T_3989) node _T_3991 = mux(entries_ex[2].bits.opa.bits.start.is_acc_addr, _T_3987, _T_3990) node _T_3992 = and(_T_3984, _T_3991) node _T_3993 = or(_T_3992, new_entry.opa.bits.wraps_around) node _T_3994 = and(_T_3983, _T_3993) node _T_3995 = or(_T_3974, _T_3994) node _T_3996 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_3997 = and(_T_3996, new_entry.opa.bits.start.read_full_acc_row) node _T_3998 = andr(new_entry.opa.bits.start.data) node _T_3999 = and(_T_3997, _T_3998) node _T_4000 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_4001 = and(_T_3999, _T_4000) node _T_4002 = and(entries_ex[2].bits.opa.bits.start.is_acc_addr, entries_ex[2].bits.opa.bits.start.accumulate) node _T_4003 = and(_T_4002, entries_ex[2].bits.opa.bits.start.read_full_acc_row) node _T_4004 = andr(entries_ex[2].bits.opa.bits.start.data) node _T_4005 = and(_T_4003, _T_4004) node _T_4006 = bits(entries_ex[2].bits.opa.bits.start.garbage_bit, 0, 0) node _T_4007 = and(_T_4005, _T_4006) node _T_4008 = or(_T_4001, _T_4007) node _T_4009 = eq(_T_4008, UInt<1>(0h0)) node _T_4010 = and(_T_3995, _T_4009) node _T_4011 = and(_T_3954, _T_4010) node _T_4012 = and(entries_ex[3].valid, entries_ex[3].bits.opa.valid) node _T_4013 = and(_T_4012, not_config) node _T_4014 = and(_T_4013, entries_ex[3].bits.opa_is_dst) node _T_4015 = eq(entries_ex[3].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_4016 = bits(entries_ex[3].bits.opa.bits.start.data, 11, 0) node _T_4017 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_4018 = leq(_T_4016, _T_4017) node _T_4019 = bits(entries_ex[3].bits.opa.bits.start.data, 13, 0) node _T_4020 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_4021 = leq(_T_4019, _T_4020) node _T_4022 = mux(entries_ex[3].bits.opa.bits.start.is_acc_addr, _T_4018, _T_4021) node _T_4023 = and(_T_4015, _T_4022) node _T_4024 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[3].bits.opa.bits.end.is_acc_addr) node _T_4025 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_4026 = bits(entries_ex[3].bits.opa.bits.end.data, 11, 0) node _T_4027 = lt(_T_4025, _T_4026) node _T_4028 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_4029 = bits(entries_ex[3].bits.opa.bits.end.data, 13, 0) node _T_4030 = lt(_T_4028, _T_4029) node _T_4031 = mux(new_entry.opa.bits.start.is_acc_addr, _T_4027, _T_4030) node _T_4032 = and(_T_4024, _T_4031) node _T_4033 = or(_T_4032, entries_ex[3].bits.opa.bits.wraps_around) node _T_4034 = and(_T_4023, _T_4033) node _T_4035 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[3].bits.opa.bits.start.is_acc_addr) node _T_4036 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_4037 = bits(entries_ex[3].bits.opa.bits.start.data, 11, 0) node _T_4038 = leq(_T_4036, _T_4037) node _T_4039 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_4040 = bits(entries_ex[3].bits.opa.bits.start.data, 13, 0) node _T_4041 = leq(_T_4039, _T_4040) node _T_4042 = mux(new_entry.opa.bits.start.is_acc_addr, _T_4038, _T_4041) node _T_4043 = and(_T_4035, _T_4042) node _T_4044 = eq(entries_ex[3].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_4045 = bits(entries_ex[3].bits.opa.bits.start.data, 11, 0) node _T_4046 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_4047 = lt(_T_4045, _T_4046) node _T_4048 = bits(entries_ex[3].bits.opa.bits.start.data, 13, 0) node _T_4049 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_4050 = lt(_T_4048, _T_4049) node _T_4051 = mux(entries_ex[3].bits.opa.bits.start.is_acc_addr, _T_4047, _T_4050) node _T_4052 = and(_T_4044, _T_4051) node _T_4053 = or(_T_4052, new_entry.opa.bits.wraps_around) node _T_4054 = and(_T_4043, _T_4053) node _T_4055 = or(_T_4034, _T_4054) node _T_4056 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_4057 = and(_T_4056, new_entry.opa.bits.start.read_full_acc_row) node _T_4058 = andr(new_entry.opa.bits.start.data) node _T_4059 = and(_T_4057, _T_4058) node _T_4060 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_4061 = and(_T_4059, _T_4060) node _T_4062 = and(entries_ex[3].bits.opa.bits.start.is_acc_addr, entries_ex[3].bits.opa.bits.start.accumulate) node _T_4063 = and(_T_4062, entries_ex[3].bits.opa.bits.start.read_full_acc_row) node _T_4064 = andr(entries_ex[3].bits.opa.bits.start.data) node _T_4065 = and(_T_4063, _T_4064) node _T_4066 = bits(entries_ex[3].bits.opa.bits.start.garbage_bit, 0, 0) node _T_4067 = and(_T_4065, _T_4066) node _T_4068 = or(_T_4061, _T_4067) node _T_4069 = eq(_T_4068, UInt<1>(0h0)) node _T_4070 = and(_T_4055, _T_4069) node _T_4071 = and(_T_4014, _T_4070) node _T_4072 = and(entries_ex[4].valid, entries_ex[4].bits.opa.valid) node _T_4073 = and(_T_4072, not_config) node _T_4074 = and(_T_4073, entries_ex[4].bits.opa_is_dst) node _T_4075 = eq(entries_ex[4].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_4076 = bits(entries_ex[4].bits.opa.bits.start.data, 11, 0) node _T_4077 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_4078 = leq(_T_4076, _T_4077) node _T_4079 = bits(entries_ex[4].bits.opa.bits.start.data, 13, 0) node _T_4080 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_4081 = leq(_T_4079, _T_4080) node _T_4082 = mux(entries_ex[4].bits.opa.bits.start.is_acc_addr, _T_4078, _T_4081) node _T_4083 = and(_T_4075, _T_4082) node _T_4084 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[4].bits.opa.bits.end.is_acc_addr) node _T_4085 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_4086 = bits(entries_ex[4].bits.opa.bits.end.data, 11, 0) node _T_4087 = lt(_T_4085, _T_4086) node _T_4088 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_4089 = bits(entries_ex[4].bits.opa.bits.end.data, 13, 0) node _T_4090 = lt(_T_4088, _T_4089) node _T_4091 = mux(new_entry.opa.bits.start.is_acc_addr, _T_4087, _T_4090) node _T_4092 = and(_T_4084, _T_4091) node _T_4093 = or(_T_4092, entries_ex[4].bits.opa.bits.wraps_around) node _T_4094 = and(_T_4083, _T_4093) node _T_4095 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[4].bits.opa.bits.start.is_acc_addr) node _T_4096 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_4097 = bits(entries_ex[4].bits.opa.bits.start.data, 11, 0) node _T_4098 = leq(_T_4096, _T_4097) node _T_4099 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_4100 = bits(entries_ex[4].bits.opa.bits.start.data, 13, 0) node _T_4101 = leq(_T_4099, _T_4100) node _T_4102 = mux(new_entry.opa.bits.start.is_acc_addr, _T_4098, _T_4101) node _T_4103 = and(_T_4095, _T_4102) node _T_4104 = eq(entries_ex[4].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_4105 = bits(entries_ex[4].bits.opa.bits.start.data, 11, 0) node _T_4106 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_4107 = lt(_T_4105, _T_4106) node _T_4108 = bits(entries_ex[4].bits.opa.bits.start.data, 13, 0) node _T_4109 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_4110 = lt(_T_4108, _T_4109) node _T_4111 = mux(entries_ex[4].bits.opa.bits.start.is_acc_addr, _T_4107, _T_4110) node _T_4112 = and(_T_4104, _T_4111) node _T_4113 = or(_T_4112, new_entry.opa.bits.wraps_around) node _T_4114 = and(_T_4103, _T_4113) node _T_4115 = or(_T_4094, _T_4114) node _T_4116 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_4117 = and(_T_4116, new_entry.opa.bits.start.read_full_acc_row) node _T_4118 = andr(new_entry.opa.bits.start.data) node _T_4119 = and(_T_4117, _T_4118) node _T_4120 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_4121 = and(_T_4119, _T_4120) node _T_4122 = and(entries_ex[4].bits.opa.bits.start.is_acc_addr, entries_ex[4].bits.opa.bits.start.accumulate) node _T_4123 = and(_T_4122, entries_ex[4].bits.opa.bits.start.read_full_acc_row) node _T_4124 = andr(entries_ex[4].bits.opa.bits.start.data) node _T_4125 = and(_T_4123, _T_4124) node _T_4126 = bits(entries_ex[4].bits.opa.bits.start.garbage_bit, 0, 0) node _T_4127 = and(_T_4125, _T_4126) node _T_4128 = or(_T_4121, _T_4127) node _T_4129 = eq(_T_4128, UInt<1>(0h0)) node _T_4130 = and(_T_4115, _T_4129) node _T_4131 = and(_T_4074, _T_4130) node _T_4132 = and(entries_ex[5].valid, entries_ex[5].bits.opa.valid) node _T_4133 = and(_T_4132, not_config) node _T_4134 = and(_T_4133, entries_ex[5].bits.opa_is_dst) node _T_4135 = eq(entries_ex[5].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_4136 = bits(entries_ex[5].bits.opa.bits.start.data, 11, 0) node _T_4137 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_4138 = leq(_T_4136, _T_4137) node _T_4139 = bits(entries_ex[5].bits.opa.bits.start.data, 13, 0) node _T_4140 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_4141 = leq(_T_4139, _T_4140) node _T_4142 = mux(entries_ex[5].bits.opa.bits.start.is_acc_addr, _T_4138, _T_4141) node _T_4143 = and(_T_4135, _T_4142) node _T_4144 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[5].bits.opa.bits.end.is_acc_addr) node _T_4145 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_4146 = bits(entries_ex[5].bits.opa.bits.end.data, 11, 0) node _T_4147 = lt(_T_4145, _T_4146) node _T_4148 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_4149 = bits(entries_ex[5].bits.opa.bits.end.data, 13, 0) node _T_4150 = lt(_T_4148, _T_4149) node _T_4151 = mux(new_entry.opa.bits.start.is_acc_addr, _T_4147, _T_4150) node _T_4152 = and(_T_4144, _T_4151) node _T_4153 = or(_T_4152, entries_ex[5].bits.opa.bits.wraps_around) node _T_4154 = and(_T_4143, _T_4153) node _T_4155 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[5].bits.opa.bits.start.is_acc_addr) node _T_4156 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_4157 = bits(entries_ex[5].bits.opa.bits.start.data, 11, 0) node _T_4158 = leq(_T_4156, _T_4157) node _T_4159 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_4160 = bits(entries_ex[5].bits.opa.bits.start.data, 13, 0) node _T_4161 = leq(_T_4159, _T_4160) node _T_4162 = mux(new_entry.opa.bits.start.is_acc_addr, _T_4158, _T_4161) node _T_4163 = and(_T_4155, _T_4162) node _T_4164 = eq(entries_ex[5].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_4165 = bits(entries_ex[5].bits.opa.bits.start.data, 11, 0) node _T_4166 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_4167 = lt(_T_4165, _T_4166) node _T_4168 = bits(entries_ex[5].bits.opa.bits.start.data, 13, 0) node _T_4169 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_4170 = lt(_T_4168, _T_4169) node _T_4171 = mux(entries_ex[5].bits.opa.bits.start.is_acc_addr, _T_4167, _T_4170) node _T_4172 = and(_T_4164, _T_4171) node _T_4173 = or(_T_4172, new_entry.opa.bits.wraps_around) node _T_4174 = and(_T_4163, _T_4173) node _T_4175 = or(_T_4154, _T_4174) node _T_4176 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_4177 = and(_T_4176, new_entry.opa.bits.start.read_full_acc_row) node _T_4178 = andr(new_entry.opa.bits.start.data) node _T_4179 = and(_T_4177, _T_4178) node _T_4180 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_4181 = and(_T_4179, _T_4180) node _T_4182 = and(entries_ex[5].bits.opa.bits.start.is_acc_addr, entries_ex[5].bits.opa.bits.start.accumulate) node _T_4183 = and(_T_4182, entries_ex[5].bits.opa.bits.start.read_full_acc_row) node _T_4184 = andr(entries_ex[5].bits.opa.bits.start.data) node _T_4185 = and(_T_4183, _T_4184) node _T_4186 = bits(entries_ex[5].bits.opa.bits.start.garbage_bit, 0, 0) node _T_4187 = and(_T_4185, _T_4186) node _T_4188 = or(_T_4181, _T_4187) node _T_4189 = eq(_T_4188, UInt<1>(0h0)) node _T_4190 = and(_T_4175, _T_4189) node _T_4191 = and(_T_4134, _T_4190) node _T_4192 = and(entries_ex[6].valid, entries_ex[6].bits.opa.valid) node _T_4193 = and(_T_4192, not_config) node _T_4194 = and(_T_4193, entries_ex[6].bits.opa_is_dst) node _T_4195 = eq(entries_ex[6].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_4196 = bits(entries_ex[6].bits.opa.bits.start.data, 11, 0) node _T_4197 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_4198 = leq(_T_4196, _T_4197) node _T_4199 = bits(entries_ex[6].bits.opa.bits.start.data, 13, 0) node _T_4200 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_4201 = leq(_T_4199, _T_4200) node _T_4202 = mux(entries_ex[6].bits.opa.bits.start.is_acc_addr, _T_4198, _T_4201) node _T_4203 = and(_T_4195, _T_4202) node _T_4204 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[6].bits.opa.bits.end.is_acc_addr) node _T_4205 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_4206 = bits(entries_ex[6].bits.opa.bits.end.data, 11, 0) node _T_4207 = lt(_T_4205, _T_4206) node _T_4208 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_4209 = bits(entries_ex[6].bits.opa.bits.end.data, 13, 0) node _T_4210 = lt(_T_4208, _T_4209) node _T_4211 = mux(new_entry.opa.bits.start.is_acc_addr, _T_4207, _T_4210) node _T_4212 = and(_T_4204, _T_4211) node _T_4213 = or(_T_4212, entries_ex[6].bits.opa.bits.wraps_around) node _T_4214 = and(_T_4203, _T_4213) node _T_4215 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[6].bits.opa.bits.start.is_acc_addr) node _T_4216 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_4217 = bits(entries_ex[6].bits.opa.bits.start.data, 11, 0) node _T_4218 = leq(_T_4216, _T_4217) node _T_4219 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_4220 = bits(entries_ex[6].bits.opa.bits.start.data, 13, 0) node _T_4221 = leq(_T_4219, _T_4220) node _T_4222 = mux(new_entry.opa.bits.start.is_acc_addr, _T_4218, _T_4221) node _T_4223 = and(_T_4215, _T_4222) node _T_4224 = eq(entries_ex[6].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_4225 = bits(entries_ex[6].bits.opa.bits.start.data, 11, 0) node _T_4226 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_4227 = lt(_T_4225, _T_4226) node _T_4228 = bits(entries_ex[6].bits.opa.bits.start.data, 13, 0) node _T_4229 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_4230 = lt(_T_4228, _T_4229) node _T_4231 = mux(entries_ex[6].bits.opa.bits.start.is_acc_addr, _T_4227, _T_4230) node _T_4232 = and(_T_4224, _T_4231) node _T_4233 = or(_T_4232, new_entry.opa.bits.wraps_around) node _T_4234 = and(_T_4223, _T_4233) node _T_4235 = or(_T_4214, _T_4234) node _T_4236 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_4237 = and(_T_4236, new_entry.opa.bits.start.read_full_acc_row) node _T_4238 = andr(new_entry.opa.bits.start.data) node _T_4239 = and(_T_4237, _T_4238) node _T_4240 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_4241 = and(_T_4239, _T_4240) node _T_4242 = and(entries_ex[6].bits.opa.bits.start.is_acc_addr, entries_ex[6].bits.opa.bits.start.accumulate) node _T_4243 = and(_T_4242, entries_ex[6].bits.opa.bits.start.read_full_acc_row) node _T_4244 = andr(entries_ex[6].bits.opa.bits.start.data) node _T_4245 = and(_T_4243, _T_4244) node _T_4246 = bits(entries_ex[6].bits.opa.bits.start.garbage_bit, 0, 0) node _T_4247 = and(_T_4245, _T_4246) node _T_4248 = or(_T_4241, _T_4247) node _T_4249 = eq(_T_4248, UInt<1>(0h0)) node _T_4250 = and(_T_4235, _T_4249) node _T_4251 = and(_T_4194, _T_4250) node _T_4252 = and(entries_ex[7].valid, entries_ex[7].bits.opa.valid) node _T_4253 = and(_T_4252, not_config) node _T_4254 = and(_T_4253, entries_ex[7].bits.opa_is_dst) node _T_4255 = eq(entries_ex[7].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_4256 = bits(entries_ex[7].bits.opa.bits.start.data, 11, 0) node _T_4257 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_4258 = leq(_T_4256, _T_4257) node _T_4259 = bits(entries_ex[7].bits.opa.bits.start.data, 13, 0) node _T_4260 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_4261 = leq(_T_4259, _T_4260) node _T_4262 = mux(entries_ex[7].bits.opa.bits.start.is_acc_addr, _T_4258, _T_4261) node _T_4263 = and(_T_4255, _T_4262) node _T_4264 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[7].bits.opa.bits.end.is_acc_addr) node _T_4265 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_4266 = bits(entries_ex[7].bits.opa.bits.end.data, 11, 0) node _T_4267 = lt(_T_4265, _T_4266) node _T_4268 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_4269 = bits(entries_ex[7].bits.opa.bits.end.data, 13, 0) node _T_4270 = lt(_T_4268, _T_4269) node _T_4271 = mux(new_entry.opa.bits.start.is_acc_addr, _T_4267, _T_4270) node _T_4272 = and(_T_4264, _T_4271) node _T_4273 = or(_T_4272, entries_ex[7].bits.opa.bits.wraps_around) node _T_4274 = and(_T_4263, _T_4273) node _T_4275 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[7].bits.opa.bits.start.is_acc_addr) node _T_4276 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_4277 = bits(entries_ex[7].bits.opa.bits.start.data, 11, 0) node _T_4278 = leq(_T_4276, _T_4277) node _T_4279 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_4280 = bits(entries_ex[7].bits.opa.bits.start.data, 13, 0) node _T_4281 = leq(_T_4279, _T_4280) node _T_4282 = mux(new_entry.opa.bits.start.is_acc_addr, _T_4278, _T_4281) node _T_4283 = and(_T_4275, _T_4282) node _T_4284 = eq(entries_ex[7].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_4285 = bits(entries_ex[7].bits.opa.bits.start.data, 11, 0) node _T_4286 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_4287 = lt(_T_4285, _T_4286) node _T_4288 = bits(entries_ex[7].bits.opa.bits.start.data, 13, 0) node _T_4289 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_4290 = lt(_T_4288, _T_4289) node _T_4291 = mux(entries_ex[7].bits.opa.bits.start.is_acc_addr, _T_4287, _T_4290) node _T_4292 = and(_T_4284, _T_4291) node _T_4293 = or(_T_4292, new_entry.opa.bits.wraps_around) node _T_4294 = and(_T_4283, _T_4293) node _T_4295 = or(_T_4274, _T_4294) node _T_4296 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_4297 = and(_T_4296, new_entry.opa.bits.start.read_full_acc_row) node _T_4298 = andr(new_entry.opa.bits.start.data) node _T_4299 = and(_T_4297, _T_4298) node _T_4300 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_4301 = and(_T_4299, _T_4300) node _T_4302 = and(entries_ex[7].bits.opa.bits.start.is_acc_addr, entries_ex[7].bits.opa.bits.start.accumulate) node _T_4303 = and(_T_4302, entries_ex[7].bits.opa.bits.start.read_full_acc_row) node _T_4304 = andr(entries_ex[7].bits.opa.bits.start.data) node _T_4305 = and(_T_4303, _T_4304) node _T_4306 = bits(entries_ex[7].bits.opa.bits.start.garbage_bit, 0, 0) node _T_4307 = and(_T_4305, _T_4306) node _T_4308 = or(_T_4301, _T_4307) node _T_4309 = eq(_T_4308, UInt<1>(0h0)) node _T_4310 = and(_T_4295, _T_4309) node _T_4311 = and(_T_4254, _T_4310) node _T_4312 = and(entries_ex[8].valid, entries_ex[8].bits.opa.valid) node _T_4313 = and(_T_4312, not_config) node _T_4314 = and(_T_4313, entries_ex[8].bits.opa_is_dst) node _T_4315 = eq(entries_ex[8].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_4316 = bits(entries_ex[8].bits.opa.bits.start.data, 11, 0) node _T_4317 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_4318 = leq(_T_4316, _T_4317) node _T_4319 = bits(entries_ex[8].bits.opa.bits.start.data, 13, 0) node _T_4320 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_4321 = leq(_T_4319, _T_4320) node _T_4322 = mux(entries_ex[8].bits.opa.bits.start.is_acc_addr, _T_4318, _T_4321) node _T_4323 = and(_T_4315, _T_4322) node _T_4324 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[8].bits.opa.bits.end.is_acc_addr) node _T_4325 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_4326 = bits(entries_ex[8].bits.opa.bits.end.data, 11, 0) node _T_4327 = lt(_T_4325, _T_4326) node _T_4328 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_4329 = bits(entries_ex[8].bits.opa.bits.end.data, 13, 0) node _T_4330 = lt(_T_4328, _T_4329) node _T_4331 = mux(new_entry.opa.bits.start.is_acc_addr, _T_4327, _T_4330) node _T_4332 = and(_T_4324, _T_4331) node _T_4333 = or(_T_4332, entries_ex[8].bits.opa.bits.wraps_around) node _T_4334 = and(_T_4323, _T_4333) node _T_4335 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[8].bits.opa.bits.start.is_acc_addr) node _T_4336 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_4337 = bits(entries_ex[8].bits.opa.bits.start.data, 11, 0) node _T_4338 = leq(_T_4336, _T_4337) node _T_4339 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_4340 = bits(entries_ex[8].bits.opa.bits.start.data, 13, 0) node _T_4341 = leq(_T_4339, _T_4340) node _T_4342 = mux(new_entry.opa.bits.start.is_acc_addr, _T_4338, _T_4341) node _T_4343 = and(_T_4335, _T_4342) node _T_4344 = eq(entries_ex[8].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_4345 = bits(entries_ex[8].bits.opa.bits.start.data, 11, 0) node _T_4346 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_4347 = lt(_T_4345, _T_4346) node _T_4348 = bits(entries_ex[8].bits.opa.bits.start.data, 13, 0) node _T_4349 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_4350 = lt(_T_4348, _T_4349) node _T_4351 = mux(entries_ex[8].bits.opa.bits.start.is_acc_addr, _T_4347, _T_4350) node _T_4352 = and(_T_4344, _T_4351) node _T_4353 = or(_T_4352, new_entry.opa.bits.wraps_around) node _T_4354 = and(_T_4343, _T_4353) node _T_4355 = or(_T_4334, _T_4354) node _T_4356 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_4357 = and(_T_4356, new_entry.opa.bits.start.read_full_acc_row) node _T_4358 = andr(new_entry.opa.bits.start.data) node _T_4359 = and(_T_4357, _T_4358) node _T_4360 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_4361 = and(_T_4359, _T_4360) node _T_4362 = and(entries_ex[8].bits.opa.bits.start.is_acc_addr, entries_ex[8].bits.opa.bits.start.accumulate) node _T_4363 = and(_T_4362, entries_ex[8].bits.opa.bits.start.read_full_acc_row) node _T_4364 = andr(entries_ex[8].bits.opa.bits.start.data) node _T_4365 = and(_T_4363, _T_4364) node _T_4366 = bits(entries_ex[8].bits.opa.bits.start.garbage_bit, 0, 0) node _T_4367 = and(_T_4365, _T_4366) node _T_4368 = or(_T_4361, _T_4367) node _T_4369 = eq(_T_4368, UInt<1>(0h0)) node _T_4370 = and(_T_4355, _T_4369) node _T_4371 = and(_T_4314, _T_4370) node _T_4372 = and(entries_ex[9].valid, entries_ex[9].bits.opa.valid) node _T_4373 = and(_T_4372, not_config) node _T_4374 = and(_T_4373, entries_ex[9].bits.opa_is_dst) node _T_4375 = eq(entries_ex[9].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_4376 = bits(entries_ex[9].bits.opa.bits.start.data, 11, 0) node _T_4377 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_4378 = leq(_T_4376, _T_4377) node _T_4379 = bits(entries_ex[9].bits.opa.bits.start.data, 13, 0) node _T_4380 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_4381 = leq(_T_4379, _T_4380) node _T_4382 = mux(entries_ex[9].bits.opa.bits.start.is_acc_addr, _T_4378, _T_4381) node _T_4383 = and(_T_4375, _T_4382) node _T_4384 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[9].bits.opa.bits.end.is_acc_addr) node _T_4385 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_4386 = bits(entries_ex[9].bits.opa.bits.end.data, 11, 0) node _T_4387 = lt(_T_4385, _T_4386) node _T_4388 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_4389 = bits(entries_ex[9].bits.opa.bits.end.data, 13, 0) node _T_4390 = lt(_T_4388, _T_4389) node _T_4391 = mux(new_entry.opa.bits.start.is_acc_addr, _T_4387, _T_4390) node _T_4392 = and(_T_4384, _T_4391) node _T_4393 = or(_T_4392, entries_ex[9].bits.opa.bits.wraps_around) node _T_4394 = and(_T_4383, _T_4393) node _T_4395 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[9].bits.opa.bits.start.is_acc_addr) node _T_4396 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_4397 = bits(entries_ex[9].bits.opa.bits.start.data, 11, 0) node _T_4398 = leq(_T_4396, _T_4397) node _T_4399 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_4400 = bits(entries_ex[9].bits.opa.bits.start.data, 13, 0) node _T_4401 = leq(_T_4399, _T_4400) node _T_4402 = mux(new_entry.opa.bits.start.is_acc_addr, _T_4398, _T_4401) node _T_4403 = and(_T_4395, _T_4402) node _T_4404 = eq(entries_ex[9].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_4405 = bits(entries_ex[9].bits.opa.bits.start.data, 11, 0) node _T_4406 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_4407 = lt(_T_4405, _T_4406) node _T_4408 = bits(entries_ex[9].bits.opa.bits.start.data, 13, 0) node _T_4409 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_4410 = lt(_T_4408, _T_4409) node _T_4411 = mux(entries_ex[9].bits.opa.bits.start.is_acc_addr, _T_4407, _T_4410) node _T_4412 = and(_T_4404, _T_4411) node _T_4413 = or(_T_4412, new_entry.opa.bits.wraps_around) node _T_4414 = and(_T_4403, _T_4413) node _T_4415 = or(_T_4394, _T_4414) node _T_4416 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_4417 = and(_T_4416, new_entry.opa.bits.start.read_full_acc_row) node _T_4418 = andr(new_entry.opa.bits.start.data) node _T_4419 = and(_T_4417, _T_4418) node _T_4420 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_4421 = and(_T_4419, _T_4420) node _T_4422 = and(entries_ex[9].bits.opa.bits.start.is_acc_addr, entries_ex[9].bits.opa.bits.start.accumulate) node _T_4423 = and(_T_4422, entries_ex[9].bits.opa.bits.start.read_full_acc_row) node _T_4424 = andr(entries_ex[9].bits.opa.bits.start.data) node _T_4425 = and(_T_4423, _T_4424) node _T_4426 = bits(entries_ex[9].bits.opa.bits.start.garbage_bit, 0, 0) node _T_4427 = and(_T_4425, _T_4426) node _T_4428 = or(_T_4421, _T_4427) node _T_4429 = eq(_T_4428, UInt<1>(0h0)) node _T_4430 = and(_T_4415, _T_4429) node _T_4431 = and(_T_4374, _T_4430) node _T_4432 = and(entries_ex[10].valid, entries_ex[10].bits.opa.valid) node _T_4433 = and(_T_4432, not_config) node _T_4434 = and(_T_4433, entries_ex[10].bits.opa_is_dst) node _T_4435 = eq(entries_ex[10].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_4436 = bits(entries_ex[10].bits.opa.bits.start.data, 11, 0) node _T_4437 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_4438 = leq(_T_4436, _T_4437) node _T_4439 = bits(entries_ex[10].bits.opa.bits.start.data, 13, 0) node _T_4440 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_4441 = leq(_T_4439, _T_4440) node _T_4442 = mux(entries_ex[10].bits.opa.bits.start.is_acc_addr, _T_4438, _T_4441) node _T_4443 = and(_T_4435, _T_4442) node _T_4444 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[10].bits.opa.bits.end.is_acc_addr) node _T_4445 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_4446 = bits(entries_ex[10].bits.opa.bits.end.data, 11, 0) node _T_4447 = lt(_T_4445, _T_4446) node _T_4448 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_4449 = bits(entries_ex[10].bits.opa.bits.end.data, 13, 0) node _T_4450 = lt(_T_4448, _T_4449) node _T_4451 = mux(new_entry.opa.bits.start.is_acc_addr, _T_4447, _T_4450) node _T_4452 = and(_T_4444, _T_4451) node _T_4453 = or(_T_4452, entries_ex[10].bits.opa.bits.wraps_around) node _T_4454 = and(_T_4443, _T_4453) node _T_4455 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[10].bits.opa.bits.start.is_acc_addr) node _T_4456 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_4457 = bits(entries_ex[10].bits.opa.bits.start.data, 11, 0) node _T_4458 = leq(_T_4456, _T_4457) node _T_4459 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_4460 = bits(entries_ex[10].bits.opa.bits.start.data, 13, 0) node _T_4461 = leq(_T_4459, _T_4460) node _T_4462 = mux(new_entry.opa.bits.start.is_acc_addr, _T_4458, _T_4461) node _T_4463 = and(_T_4455, _T_4462) node _T_4464 = eq(entries_ex[10].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_4465 = bits(entries_ex[10].bits.opa.bits.start.data, 11, 0) node _T_4466 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_4467 = lt(_T_4465, _T_4466) node _T_4468 = bits(entries_ex[10].bits.opa.bits.start.data, 13, 0) node _T_4469 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_4470 = lt(_T_4468, _T_4469) node _T_4471 = mux(entries_ex[10].bits.opa.bits.start.is_acc_addr, _T_4467, _T_4470) node _T_4472 = and(_T_4464, _T_4471) node _T_4473 = or(_T_4472, new_entry.opa.bits.wraps_around) node _T_4474 = and(_T_4463, _T_4473) node _T_4475 = or(_T_4454, _T_4474) node _T_4476 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_4477 = and(_T_4476, new_entry.opa.bits.start.read_full_acc_row) node _T_4478 = andr(new_entry.opa.bits.start.data) node _T_4479 = and(_T_4477, _T_4478) node _T_4480 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_4481 = and(_T_4479, _T_4480) node _T_4482 = and(entries_ex[10].bits.opa.bits.start.is_acc_addr, entries_ex[10].bits.opa.bits.start.accumulate) node _T_4483 = and(_T_4482, entries_ex[10].bits.opa.bits.start.read_full_acc_row) node _T_4484 = andr(entries_ex[10].bits.opa.bits.start.data) node _T_4485 = and(_T_4483, _T_4484) node _T_4486 = bits(entries_ex[10].bits.opa.bits.start.garbage_bit, 0, 0) node _T_4487 = and(_T_4485, _T_4486) node _T_4488 = or(_T_4481, _T_4487) node _T_4489 = eq(_T_4488, UInt<1>(0h0)) node _T_4490 = and(_T_4475, _T_4489) node _T_4491 = and(_T_4434, _T_4490) node _T_4492 = and(entries_ex[11].valid, entries_ex[11].bits.opa.valid) node _T_4493 = and(_T_4492, not_config) node _T_4494 = and(_T_4493, entries_ex[11].bits.opa_is_dst) node _T_4495 = eq(entries_ex[11].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_4496 = bits(entries_ex[11].bits.opa.bits.start.data, 11, 0) node _T_4497 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_4498 = leq(_T_4496, _T_4497) node _T_4499 = bits(entries_ex[11].bits.opa.bits.start.data, 13, 0) node _T_4500 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_4501 = leq(_T_4499, _T_4500) node _T_4502 = mux(entries_ex[11].bits.opa.bits.start.is_acc_addr, _T_4498, _T_4501) node _T_4503 = and(_T_4495, _T_4502) node _T_4504 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[11].bits.opa.bits.end.is_acc_addr) node _T_4505 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_4506 = bits(entries_ex[11].bits.opa.bits.end.data, 11, 0) node _T_4507 = lt(_T_4505, _T_4506) node _T_4508 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_4509 = bits(entries_ex[11].bits.opa.bits.end.data, 13, 0) node _T_4510 = lt(_T_4508, _T_4509) node _T_4511 = mux(new_entry.opa.bits.start.is_acc_addr, _T_4507, _T_4510) node _T_4512 = and(_T_4504, _T_4511) node _T_4513 = or(_T_4512, entries_ex[11].bits.opa.bits.wraps_around) node _T_4514 = and(_T_4503, _T_4513) node _T_4515 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[11].bits.opa.bits.start.is_acc_addr) node _T_4516 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_4517 = bits(entries_ex[11].bits.opa.bits.start.data, 11, 0) node _T_4518 = leq(_T_4516, _T_4517) node _T_4519 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_4520 = bits(entries_ex[11].bits.opa.bits.start.data, 13, 0) node _T_4521 = leq(_T_4519, _T_4520) node _T_4522 = mux(new_entry.opa.bits.start.is_acc_addr, _T_4518, _T_4521) node _T_4523 = and(_T_4515, _T_4522) node _T_4524 = eq(entries_ex[11].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_4525 = bits(entries_ex[11].bits.opa.bits.start.data, 11, 0) node _T_4526 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_4527 = lt(_T_4525, _T_4526) node _T_4528 = bits(entries_ex[11].bits.opa.bits.start.data, 13, 0) node _T_4529 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_4530 = lt(_T_4528, _T_4529) node _T_4531 = mux(entries_ex[11].bits.opa.bits.start.is_acc_addr, _T_4527, _T_4530) node _T_4532 = and(_T_4524, _T_4531) node _T_4533 = or(_T_4532, new_entry.opa.bits.wraps_around) node _T_4534 = and(_T_4523, _T_4533) node _T_4535 = or(_T_4514, _T_4534) node _T_4536 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_4537 = and(_T_4536, new_entry.opa.bits.start.read_full_acc_row) node _T_4538 = andr(new_entry.opa.bits.start.data) node _T_4539 = and(_T_4537, _T_4538) node _T_4540 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_4541 = and(_T_4539, _T_4540) node _T_4542 = and(entries_ex[11].bits.opa.bits.start.is_acc_addr, entries_ex[11].bits.opa.bits.start.accumulate) node _T_4543 = and(_T_4542, entries_ex[11].bits.opa.bits.start.read_full_acc_row) node _T_4544 = andr(entries_ex[11].bits.opa.bits.start.data) node _T_4545 = and(_T_4543, _T_4544) node _T_4546 = bits(entries_ex[11].bits.opa.bits.start.garbage_bit, 0, 0) node _T_4547 = and(_T_4545, _T_4546) node _T_4548 = or(_T_4541, _T_4547) node _T_4549 = eq(_T_4548, UInt<1>(0h0)) node _T_4550 = and(_T_4535, _T_4549) node _T_4551 = and(_T_4494, _T_4550) node _T_4552 = and(entries_ex[12].valid, entries_ex[12].bits.opa.valid) node _T_4553 = and(_T_4552, not_config) node _T_4554 = and(_T_4553, entries_ex[12].bits.opa_is_dst) node _T_4555 = eq(entries_ex[12].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_4556 = bits(entries_ex[12].bits.opa.bits.start.data, 11, 0) node _T_4557 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_4558 = leq(_T_4556, _T_4557) node _T_4559 = bits(entries_ex[12].bits.opa.bits.start.data, 13, 0) node _T_4560 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_4561 = leq(_T_4559, _T_4560) node _T_4562 = mux(entries_ex[12].bits.opa.bits.start.is_acc_addr, _T_4558, _T_4561) node _T_4563 = and(_T_4555, _T_4562) node _T_4564 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[12].bits.opa.bits.end.is_acc_addr) node _T_4565 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_4566 = bits(entries_ex[12].bits.opa.bits.end.data, 11, 0) node _T_4567 = lt(_T_4565, _T_4566) node _T_4568 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_4569 = bits(entries_ex[12].bits.opa.bits.end.data, 13, 0) node _T_4570 = lt(_T_4568, _T_4569) node _T_4571 = mux(new_entry.opa.bits.start.is_acc_addr, _T_4567, _T_4570) node _T_4572 = and(_T_4564, _T_4571) node _T_4573 = or(_T_4572, entries_ex[12].bits.opa.bits.wraps_around) node _T_4574 = and(_T_4563, _T_4573) node _T_4575 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[12].bits.opa.bits.start.is_acc_addr) node _T_4576 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_4577 = bits(entries_ex[12].bits.opa.bits.start.data, 11, 0) node _T_4578 = leq(_T_4576, _T_4577) node _T_4579 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_4580 = bits(entries_ex[12].bits.opa.bits.start.data, 13, 0) node _T_4581 = leq(_T_4579, _T_4580) node _T_4582 = mux(new_entry.opa.bits.start.is_acc_addr, _T_4578, _T_4581) node _T_4583 = and(_T_4575, _T_4582) node _T_4584 = eq(entries_ex[12].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_4585 = bits(entries_ex[12].bits.opa.bits.start.data, 11, 0) node _T_4586 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_4587 = lt(_T_4585, _T_4586) node _T_4588 = bits(entries_ex[12].bits.opa.bits.start.data, 13, 0) node _T_4589 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_4590 = lt(_T_4588, _T_4589) node _T_4591 = mux(entries_ex[12].bits.opa.bits.start.is_acc_addr, _T_4587, _T_4590) node _T_4592 = and(_T_4584, _T_4591) node _T_4593 = or(_T_4592, new_entry.opa.bits.wraps_around) node _T_4594 = and(_T_4583, _T_4593) node _T_4595 = or(_T_4574, _T_4594) node _T_4596 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_4597 = and(_T_4596, new_entry.opa.bits.start.read_full_acc_row) node _T_4598 = andr(new_entry.opa.bits.start.data) node _T_4599 = and(_T_4597, _T_4598) node _T_4600 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_4601 = and(_T_4599, _T_4600) node _T_4602 = and(entries_ex[12].bits.opa.bits.start.is_acc_addr, entries_ex[12].bits.opa.bits.start.accumulate) node _T_4603 = and(_T_4602, entries_ex[12].bits.opa.bits.start.read_full_acc_row) node _T_4604 = andr(entries_ex[12].bits.opa.bits.start.data) node _T_4605 = and(_T_4603, _T_4604) node _T_4606 = bits(entries_ex[12].bits.opa.bits.start.garbage_bit, 0, 0) node _T_4607 = and(_T_4605, _T_4606) node _T_4608 = or(_T_4601, _T_4607) node _T_4609 = eq(_T_4608, UInt<1>(0h0)) node _T_4610 = and(_T_4595, _T_4609) node _T_4611 = and(_T_4554, _T_4610) node _T_4612 = and(entries_ex[13].valid, entries_ex[13].bits.opa.valid) node _T_4613 = and(_T_4612, not_config) node _T_4614 = and(_T_4613, entries_ex[13].bits.opa_is_dst) node _T_4615 = eq(entries_ex[13].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_4616 = bits(entries_ex[13].bits.opa.bits.start.data, 11, 0) node _T_4617 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_4618 = leq(_T_4616, _T_4617) node _T_4619 = bits(entries_ex[13].bits.opa.bits.start.data, 13, 0) node _T_4620 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_4621 = leq(_T_4619, _T_4620) node _T_4622 = mux(entries_ex[13].bits.opa.bits.start.is_acc_addr, _T_4618, _T_4621) node _T_4623 = and(_T_4615, _T_4622) node _T_4624 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[13].bits.opa.bits.end.is_acc_addr) node _T_4625 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_4626 = bits(entries_ex[13].bits.opa.bits.end.data, 11, 0) node _T_4627 = lt(_T_4625, _T_4626) node _T_4628 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_4629 = bits(entries_ex[13].bits.opa.bits.end.data, 13, 0) node _T_4630 = lt(_T_4628, _T_4629) node _T_4631 = mux(new_entry.opa.bits.start.is_acc_addr, _T_4627, _T_4630) node _T_4632 = and(_T_4624, _T_4631) node _T_4633 = or(_T_4632, entries_ex[13].bits.opa.bits.wraps_around) node _T_4634 = and(_T_4623, _T_4633) node _T_4635 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[13].bits.opa.bits.start.is_acc_addr) node _T_4636 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_4637 = bits(entries_ex[13].bits.opa.bits.start.data, 11, 0) node _T_4638 = leq(_T_4636, _T_4637) node _T_4639 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_4640 = bits(entries_ex[13].bits.opa.bits.start.data, 13, 0) node _T_4641 = leq(_T_4639, _T_4640) node _T_4642 = mux(new_entry.opa.bits.start.is_acc_addr, _T_4638, _T_4641) node _T_4643 = and(_T_4635, _T_4642) node _T_4644 = eq(entries_ex[13].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_4645 = bits(entries_ex[13].bits.opa.bits.start.data, 11, 0) node _T_4646 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_4647 = lt(_T_4645, _T_4646) node _T_4648 = bits(entries_ex[13].bits.opa.bits.start.data, 13, 0) node _T_4649 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_4650 = lt(_T_4648, _T_4649) node _T_4651 = mux(entries_ex[13].bits.opa.bits.start.is_acc_addr, _T_4647, _T_4650) node _T_4652 = and(_T_4644, _T_4651) node _T_4653 = or(_T_4652, new_entry.opa.bits.wraps_around) node _T_4654 = and(_T_4643, _T_4653) node _T_4655 = or(_T_4634, _T_4654) node _T_4656 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_4657 = and(_T_4656, new_entry.opa.bits.start.read_full_acc_row) node _T_4658 = andr(new_entry.opa.bits.start.data) node _T_4659 = and(_T_4657, _T_4658) node _T_4660 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_4661 = and(_T_4659, _T_4660) node _T_4662 = and(entries_ex[13].bits.opa.bits.start.is_acc_addr, entries_ex[13].bits.opa.bits.start.accumulate) node _T_4663 = and(_T_4662, entries_ex[13].bits.opa.bits.start.read_full_acc_row) node _T_4664 = andr(entries_ex[13].bits.opa.bits.start.data) node _T_4665 = and(_T_4663, _T_4664) node _T_4666 = bits(entries_ex[13].bits.opa.bits.start.garbage_bit, 0, 0) node _T_4667 = and(_T_4665, _T_4666) node _T_4668 = or(_T_4661, _T_4667) node _T_4669 = eq(_T_4668, UInt<1>(0h0)) node _T_4670 = and(_T_4655, _T_4669) node _T_4671 = and(_T_4614, _T_4670) node _T_4672 = and(entries_ex[14].valid, entries_ex[14].bits.opa.valid) node _T_4673 = and(_T_4672, not_config) node _T_4674 = and(_T_4673, entries_ex[14].bits.opa_is_dst) node _T_4675 = eq(entries_ex[14].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_4676 = bits(entries_ex[14].bits.opa.bits.start.data, 11, 0) node _T_4677 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_4678 = leq(_T_4676, _T_4677) node _T_4679 = bits(entries_ex[14].bits.opa.bits.start.data, 13, 0) node _T_4680 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_4681 = leq(_T_4679, _T_4680) node _T_4682 = mux(entries_ex[14].bits.opa.bits.start.is_acc_addr, _T_4678, _T_4681) node _T_4683 = and(_T_4675, _T_4682) node _T_4684 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[14].bits.opa.bits.end.is_acc_addr) node _T_4685 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_4686 = bits(entries_ex[14].bits.opa.bits.end.data, 11, 0) node _T_4687 = lt(_T_4685, _T_4686) node _T_4688 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_4689 = bits(entries_ex[14].bits.opa.bits.end.data, 13, 0) node _T_4690 = lt(_T_4688, _T_4689) node _T_4691 = mux(new_entry.opa.bits.start.is_acc_addr, _T_4687, _T_4690) node _T_4692 = and(_T_4684, _T_4691) node _T_4693 = or(_T_4692, entries_ex[14].bits.opa.bits.wraps_around) node _T_4694 = and(_T_4683, _T_4693) node _T_4695 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[14].bits.opa.bits.start.is_acc_addr) node _T_4696 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_4697 = bits(entries_ex[14].bits.opa.bits.start.data, 11, 0) node _T_4698 = leq(_T_4696, _T_4697) node _T_4699 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_4700 = bits(entries_ex[14].bits.opa.bits.start.data, 13, 0) node _T_4701 = leq(_T_4699, _T_4700) node _T_4702 = mux(new_entry.opa.bits.start.is_acc_addr, _T_4698, _T_4701) node _T_4703 = and(_T_4695, _T_4702) node _T_4704 = eq(entries_ex[14].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_4705 = bits(entries_ex[14].bits.opa.bits.start.data, 11, 0) node _T_4706 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_4707 = lt(_T_4705, _T_4706) node _T_4708 = bits(entries_ex[14].bits.opa.bits.start.data, 13, 0) node _T_4709 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_4710 = lt(_T_4708, _T_4709) node _T_4711 = mux(entries_ex[14].bits.opa.bits.start.is_acc_addr, _T_4707, _T_4710) node _T_4712 = and(_T_4704, _T_4711) node _T_4713 = or(_T_4712, new_entry.opa.bits.wraps_around) node _T_4714 = and(_T_4703, _T_4713) node _T_4715 = or(_T_4694, _T_4714) node _T_4716 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_4717 = and(_T_4716, new_entry.opa.bits.start.read_full_acc_row) node _T_4718 = andr(new_entry.opa.bits.start.data) node _T_4719 = and(_T_4717, _T_4718) node _T_4720 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_4721 = and(_T_4719, _T_4720) node _T_4722 = and(entries_ex[14].bits.opa.bits.start.is_acc_addr, entries_ex[14].bits.opa.bits.start.accumulate) node _T_4723 = and(_T_4722, entries_ex[14].bits.opa.bits.start.read_full_acc_row) node _T_4724 = andr(entries_ex[14].bits.opa.bits.start.data) node _T_4725 = and(_T_4723, _T_4724) node _T_4726 = bits(entries_ex[14].bits.opa.bits.start.garbage_bit, 0, 0) node _T_4727 = and(_T_4725, _T_4726) node _T_4728 = or(_T_4721, _T_4727) node _T_4729 = eq(_T_4728, UInt<1>(0h0)) node _T_4730 = and(_T_4715, _T_4729) node _T_4731 = and(_T_4674, _T_4730) node _T_4732 = and(entries_ex[15].valid, entries_ex[15].bits.opa.valid) node _T_4733 = and(_T_4732, not_config) node _T_4734 = and(_T_4733, entries_ex[15].bits.opa_is_dst) node _T_4735 = eq(entries_ex[15].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.is_acc_addr) node _T_4736 = bits(entries_ex[15].bits.opa.bits.start.data, 11, 0) node _T_4737 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_4738 = leq(_T_4736, _T_4737) node _T_4739 = bits(entries_ex[15].bits.opa.bits.start.data, 13, 0) node _T_4740 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_4741 = leq(_T_4739, _T_4740) node _T_4742 = mux(entries_ex[15].bits.opa.bits.start.is_acc_addr, _T_4738, _T_4741) node _T_4743 = and(_T_4735, _T_4742) node _T_4744 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[15].bits.opa.bits.end.is_acc_addr) node _T_4745 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_4746 = bits(entries_ex[15].bits.opa.bits.end.data, 11, 0) node _T_4747 = lt(_T_4745, _T_4746) node _T_4748 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_4749 = bits(entries_ex[15].bits.opa.bits.end.data, 13, 0) node _T_4750 = lt(_T_4748, _T_4749) node _T_4751 = mux(new_entry.opa.bits.start.is_acc_addr, _T_4747, _T_4750) node _T_4752 = and(_T_4744, _T_4751) node _T_4753 = or(_T_4752, entries_ex[15].bits.opa.bits.wraps_around) node _T_4754 = and(_T_4743, _T_4753) node _T_4755 = eq(new_entry.opa.bits.start.is_acc_addr, entries_ex[15].bits.opa.bits.start.is_acc_addr) node _T_4756 = bits(new_entry.opa.bits.start.data, 11, 0) node _T_4757 = bits(entries_ex[15].bits.opa.bits.start.data, 11, 0) node _T_4758 = leq(_T_4756, _T_4757) node _T_4759 = bits(new_entry.opa.bits.start.data, 13, 0) node _T_4760 = bits(entries_ex[15].bits.opa.bits.start.data, 13, 0) node _T_4761 = leq(_T_4759, _T_4760) node _T_4762 = mux(new_entry.opa.bits.start.is_acc_addr, _T_4758, _T_4761) node _T_4763 = and(_T_4755, _T_4762) node _T_4764 = eq(entries_ex[15].bits.opa.bits.start.is_acc_addr, new_entry.opa.bits.end.is_acc_addr) node _T_4765 = bits(entries_ex[15].bits.opa.bits.start.data, 11, 0) node _T_4766 = bits(new_entry.opa.bits.end.data, 11, 0) node _T_4767 = lt(_T_4765, _T_4766) node _T_4768 = bits(entries_ex[15].bits.opa.bits.start.data, 13, 0) node _T_4769 = bits(new_entry.opa.bits.end.data, 13, 0) node _T_4770 = lt(_T_4768, _T_4769) node _T_4771 = mux(entries_ex[15].bits.opa.bits.start.is_acc_addr, _T_4767, _T_4770) node _T_4772 = and(_T_4764, _T_4771) node _T_4773 = or(_T_4772, new_entry.opa.bits.wraps_around) node _T_4774 = and(_T_4763, _T_4773) node _T_4775 = or(_T_4754, _T_4774) node _T_4776 = and(new_entry.opa.bits.start.is_acc_addr, new_entry.opa.bits.start.accumulate) node _T_4777 = and(_T_4776, new_entry.opa.bits.start.read_full_acc_row) node _T_4778 = andr(new_entry.opa.bits.start.data) node _T_4779 = and(_T_4777, _T_4778) node _T_4780 = bits(new_entry.opa.bits.start.garbage_bit, 0, 0) node _T_4781 = and(_T_4779, _T_4780) node _T_4782 = and(entries_ex[15].bits.opa.bits.start.is_acc_addr, entries_ex[15].bits.opa.bits.start.accumulate) node _T_4783 = and(_T_4782, entries_ex[15].bits.opa.bits.start.read_full_acc_row) node _T_4784 = andr(entries_ex[15].bits.opa.bits.start.data) node _T_4785 = and(_T_4783, _T_4784) node _T_4786 = bits(entries_ex[15].bits.opa.bits.start.garbage_bit, 0, 0) node _T_4787 = and(_T_4785, _T_4786) node _T_4788 = or(_T_4781, _T_4787) node _T_4789 = eq(_T_4788, UInt<1>(0h0)) node _T_4790 = and(_T_4775, _T_4789) node _T_4791 = and(_T_4734, _T_4790) wire _WIRE_7 : UInt<1>[16] connect _WIRE_7[0], _T_3891 connect _WIRE_7[1], _T_3951 connect _WIRE_7[2], _T_4011 connect _WIRE_7[3], _T_4071 connect _WIRE_7[4], _T_4131 connect _WIRE_7[5], _T_4191 connect _WIRE_7[6], _T_4251 connect _WIRE_7[7], _T_4311 connect _WIRE_7[8], _T_4371 connect _WIRE_7[9], _T_4431 connect _WIRE_7[10], _T_4491 connect _WIRE_7[11], _T_4551 connect _WIRE_7[12], _T_4611 connect _WIRE_7[13], _T_4671 connect _WIRE_7[14], _T_4731 connect _WIRE_7[15], _T_4791 connect new_entry.deps_ex, _WIRE_7 node _T_4792 = eq(entries_st[0].bits.issued, UInt<1>(0h0)) node _T_4793 = and(entries_st[0].valid, _T_4792) node _T_4794 = eq(entries_st[1].bits.issued, UInt<1>(0h0)) node _T_4795 = and(entries_st[1].valid, _T_4794) node _T_4796 = eq(entries_st[2].bits.issued, UInt<1>(0h0)) node _T_4797 = and(entries_st[2].valid, _T_4796) node _T_4798 = eq(entries_st[3].bits.issued, UInt<1>(0h0)) node _T_4799 = and(entries_st[3].valid, _T_4798) wire _WIRE_8 : UInt<1>[4] connect _WIRE_8[0], _T_4793 connect _WIRE_8[1], _T_4795 connect _WIRE_8[2], _T_4797 connect _WIRE_8[3], _T_4799 connect new_entry.deps_st, _WIRE_8 connect new_entry.allocated_at, instructions_allocated node _new_entry_complete_on_issue_T = neq(new_entry.q, UInt<2>(0h1)) node _new_entry_complete_on_issue_T_1 = and(new_entry.is_config, _new_entry_complete_on_issue_T) connect new_entry.complete_on_issue, _new_entry_complete_on_issue_T_1 node _T_4800 = eq(new_entry.q, UInt<2>(0h0)) when _T_4800 : node _is_full_T = add(op1.valid, op2.valid) node _is_full_T_1 = bits(_is_full_T, 1, 0) node _is_full_T_2 = add(dst.valid, _is_full_T_1) node _is_full_T_3 = bits(_is_full_T_2, 1, 0) node is_full = gt(_is_full_T_3, UInt<1>(0h1)) node _T_4801 = neq(UInt<2>(0h0), UInt<2>(0h1)) when _T_4801 : node _T_4802 = eq(is_full, UInt<1>(0h0)) node _T_4803 = asUInt(reset) node _T_4804 = eq(_T_4803, UInt<1>(0h0)) when _T_4804 : node _T_4805 = eq(_T_4802, UInt<1>(0h0)) when _T_4805 : printf(clock, UInt<1>(0h1), "Assertion failed\n at ReservationStation.scala:352 when (q =/= exq) { assert(!is_full) }\n") : printf_3 assert(clock, _T_4802, UInt<1>(0h1), "") : assert_3 node _alloc_id_T = eq(entries_ld[0].valid, UInt<1>(0h0)) node _alloc_id_T_1 = eq(entries_ld[1].valid, UInt<1>(0h0)) node _alloc_id_T_2 = eq(entries_ld[2].valid, UInt<1>(0h0)) node _alloc_id_T_3 = eq(entries_ld[3].valid, UInt<1>(0h0)) node _alloc_id_T_4 = eq(entries_ld[4].valid, UInt<1>(0h0)) node _alloc_id_T_5 = eq(entries_ld[5].valid, UInt<1>(0h0)) node _alloc_id_T_6 = eq(entries_ld[6].valid, UInt<1>(0h0)) node _alloc_id_T_7 = eq(entries_ld[7].valid, UInt<1>(0h0)) node _alloc_id_T_8 = mux(_alloc_id_T_7, UInt<3>(0h7), UInt<3>(0h7)) node _alloc_id_T_9 = mux(_alloc_id_T_6, UInt<3>(0h6), _alloc_id_T_8) node _alloc_id_T_10 = mux(_alloc_id_T_5, UInt<3>(0h5), _alloc_id_T_9) node _alloc_id_T_11 = mux(_alloc_id_T_4, UInt<3>(0h4), _alloc_id_T_10) node _alloc_id_T_12 = mux(_alloc_id_T_3, UInt<2>(0h3), _alloc_id_T_11) node _alloc_id_T_13 = mux(_alloc_id_T_2, UInt<2>(0h2), _alloc_id_T_12) node _alloc_id_T_14 = mux(_alloc_id_T_1, UInt<1>(0h1), _alloc_id_T_13) node alloc_id = mux(_alloc_id_T, UInt<1>(0h0), _alloc_id_T_14) node _T_4806 = eq(entries_ld[alloc_id].valid, UInt<1>(0h0)) when _T_4806 : connect io.alloc.ready, UInt<1>(0h1) connect entries_ld[alloc_id].valid, UInt<1>(0h1) connect entries_ld[alloc_id].bits, new_entry connect new_allocs_oh_ld[alloc_id], UInt<1>(0h1) node _T_4807 = eq(new_entry.q, UInt<2>(0h1)) when _T_4807 : node _is_full_T_4 = add(op1.valid, op2.valid) node _is_full_T_5 = bits(_is_full_T_4, 1, 0) node _is_full_T_6 = add(dst.valid, _is_full_T_5) node _is_full_T_7 = bits(_is_full_T_6, 1, 0) node is_full_1 = gt(_is_full_T_7, UInt<1>(0h1)) node _T_4808 = neq(UInt<2>(0h1), UInt<2>(0h1)) when _T_4808 : node _T_4809 = eq(is_full_1, UInt<1>(0h0)) node _T_4810 = asUInt(reset) node _T_4811 = eq(_T_4810, UInt<1>(0h0)) when _T_4811 : node _T_4812 = eq(_T_4809, UInt<1>(0h0)) when _T_4812 : printf(clock, UInt<1>(0h1), "Assertion failed\n at ReservationStation.scala:352 when (q =/= exq) { assert(!is_full) }\n") : printf_4 assert(clock, _T_4809, UInt<1>(0h1), "") : assert_4 node _alloc_id_T_15 = eq(entries_ex[0].valid, UInt<1>(0h0)) node _alloc_id_T_16 = eq(entries_ex[1].valid, UInt<1>(0h0)) node _alloc_id_T_17 = eq(entries_ex[2].valid, UInt<1>(0h0)) node _alloc_id_T_18 = eq(entries_ex[3].valid, UInt<1>(0h0)) node _alloc_id_T_19 = eq(entries_ex[4].valid, UInt<1>(0h0)) node _alloc_id_T_20 = eq(entries_ex[5].valid, UInt<1>(0h0)) node _alloc_id_T_21 = eq(entries_ex[6].valid, UInt<1>(0h0)) node _alloc_id_T_22 = eq(entries_ex[7].valid, UInt<1>(0h0)) node _alloc_id_T_23 = eq(entries_ex[8].valid, UInt<1>(0h0)) node _alloc_id_T_24 = eq(entries_ex[9].valid, UInt<1>(0h0)) node _alloc_id_T_25 = eq(entries_ex[10].valid, UInt<1>(0h0)) node _alloc_id_T_26 = eq(entries_ex[11].valid, UInt<1>(0h0)) node _alloc_id_T_27 = eq(entries_ex[12].valid, UInt<1>(0h0)) node _alloc_id_T_28 = eq(entries_ex[13].valid, UInt<1>(0h0)) node _alloc_id_T_29 = eq(entries_ex[14].valid, UInt<1>(0h0)) node _alloc_id_T_30 = eq(entries_ex[15].valid, UInt<1>(0h0)) node _alloc_id_T_31 = mux(_alloc_id_T_30, UInt<4>(0hf), UInt<4>(0hf)) node _alloc_id_T_32 = mux(_alloc_id_T_29, UInt<4>(0he), _alloc_id_T_31) node _alloc_id_T_33 = mux(_alloc_id_T_28, UInt<4>(0hd), _alloc_id_T_32) node _alloc_id_T_34 = mux(_alloc_id_T_27, UInt<4>(0hc), _alloc_id_T_33) node _alloc_id_T_35 = mux(_alloc_id_T_26, UInt<4>(0hb), _alloc_id_T_34) node _alloc_id_T_36 = mux(_alloc_id_T_25, UInt<4>(0ha), _alloc_id_T_35) node _alloc_id_T_37 = mux(_alloc_id_T_24, UInt<4>(0h9), _alloc_id_T_36) node _alloc_id_T_38 = mux(_alloc_id_T_23, UInt<4>(0h8), _alloc_id_T_37) node _alloc_id_T_39 = mux(_alloc_id_T_22, UInt<3>(0h7), _alloc_id_T_38) node _alloc_id_T_40 = mux(_alloc_id_T_21, UInt<3>(0h6), _alloc_id_T_39) node _alloc_id_T_41 = mux(_alloc_id_T_20, UInt<3>(0h5), _alloc_id_T_40) node _alloc_id_T_42 = mux(_alloc_id_T_19, UInt<3>(0h4), _alloc_id_T_41) node _alloc_id_T_43 = mux(_alloc_id_T_18, UInt<2>(0h3), _alloc_id_T_42) node _alloc_id_T_44 = mux(_alloc_id_T_17, UInt<2>(0h2), _alloc_id_T_43) node _alloc_id_T_45 = mux(_alloc_id_T_16, UInt<1>(0h1), _alloc_id_T_44) node alloc_id_1 = mux(_alloc_id_T_15, UInt<1>(0h0), _alloc_id_T_45) node _T_4813 = eq(entries_ex[alloc_id_1].valid, UInt<1>(0h0)) when _T_4813 : connect io.alloc.ready, UInt<1>(0h1) connect entries_ex[alloc_id_1].valid, UInt<1>(0h1) connect entries_ex[alloc_id_1].bits, new_entry connect new_allocs_oh_ex[alloc_id_1], UInt<1>(0h1) node _T_4814 = eq(new_entry.q, UInt<2>(0h2)) when _T_4814 : node _is_full_T_8 = add(op1.valid, op2.valid) node _is_full_T_9 = bits(_is_full_T_8, 1, 0) node _is_full_T_10 = add(dst.valid, _is_full_T_9) node _is_full_T_11 = bits(_is_full_T_10, 1, 0) node is_full_2 = gt(_is_full_T_11, UInt<1>(0h1)) node _T_4815 = neq(UInt<2>(0h2), UInt<2>(0h1)) when _T_4815 : node _T_4816 = eq(is_full_2, UInt<1>(0h0)) node _T_4817 = asUInt(reset) node _T_4818 = eq(_T_4817, UInt<1>(0h0)) when _T_4818 : node _T_4819 = eq(_T_4816, UInt<1>(0h0)) when _T_4819 : printf(clock, UInt<1>(0h1), "Assertion failed\n at ReservationStation.scala:352 when (q =/= exq) { assert(!is_full) }\n") : printf_5 assert(clock, _T_4816, UInt<1>(0h1), "") : assert_5 node _alloc_id_T_46 = eq(entries_st[0].valid, UInt<1>(0h0)) node _alloc_id_T_47 = eq(entries_st[1].valid, UInt<1>(0h0)) node _alloc_id_T_48 = eq(entries_st[2].valid, UInt<1>(0h0)) node _alloc_id_T_49 = eq(entries_st[3].valid, UInt<1>(0h0)) node _alloc_id_T_50 = mux(_alloc_id_T_49, UInt<2>(0h3), UInt<2>(0h3)) node _alloc_id_T_51 = mux(_alloc_id_T_48, UInt<2>(0h2), _alloc_id_T_50) node _alloc_id_T_52 = mux(_alloc_id_T_47, UInt<1>(0h1), _alloc_id_T_51) node alloc_id_2 = mux(_alloc_id_T_46, UInt<1>(0h0), _alloc_id_T_52) node _T_4820 = eq(entries_st[alloc_id_2].valid, UInt<1>(0h0)) when _T_4820 : connect io.alloc.ready, UInt<1>(0h1) connect entries_st[alloc_id_2].valid, UInt<1>(0h1) connect entries_st[alloc_id_2].bits, new_entry connect new_allocs_oh_st[alloc_id_2], UInt<1>(0h1) node _T_4821 = and(io.alloc.ready, io.alloc.valid) when _T_4821 : node _T_4822 = eq(new_entry.q, UInt<2>(0h1)) node _T_4823 = and(new_entry.is_config, _T_4822) when _T_4823 : node _a_stride_T = bits(new_entry.cmd.cmd.rs1, 31, 16) connect a_stride, _a_stride_T node _c_stride_T = bits(new_entry.cmd.cmd.rs2, 63, 48) connect c_stride, _c_stride_T node set_only_strides = bits(new_entry.cmd.cmd.rs1, 7, 7) node _T_4824 = eq(set_only_strides, UInt<1>(0h0)) when _T_4824 : node _a_transpose_T = bits(new_entry.cmd.cmd.rs1, 8, 8) connect a_transpose, _a_transpose_T else : node _T_4825 = eq(new_entry.q, UInt<2>(0h0)) node _T_4826 = and(new_entry.is_config, _T_4825) when _T_4826 : node id_1 = bits(new_entry.cmd.cmd.rs1, 4, 3) node block_stride = bits(new_entry.cmd.cmd.rs1, 31, 16) node _repeat_pixels_T = bits(new_entry.cmd.cmd.rs1, 10, 8) node _repeat_pixels_T_1 = gt(_repeat_pixels_T, UInt<1>(0h1)) node repeat_pixels = mux(_repeat_pixels_T_1, _repeat_pixels_T, UInt<1>(0h1)) connect ld_block_strides[id_1], block_stride node _ld_pixel_repeats_T = sub(repeat_pixels, UInt<1>(0h1)) node _ld_pixel_repeats_T_1 = tail(_ld_pixel_repeats_T, 1) connect ld_pixel_repeats[id_1], _ld_pixel_repeats_T_1 else : node _T_4827 = eq(new_entry.q, UInt<2>(0h2)) node _T_4828 = and(new_entry.is_config, _T_4827) node _T_4829 = eq(is_norm, UInt<1>(0h0)) node _T_4830 = and(_T_4828, _T_4829) when _T_4830 : node pool_stride = bits(new_entry.cmd.cmd.rs1, 5, 4) node _pooling_is_enabled_T = neq(pool_stride, UInt<1>(0h0)) connect pooling_is_enabled, _pooling_is_enabled_T else : node _T_4831 = eq(io.alloc.bits.cmd.inst.funct, UInt<3>(0h6)) when _T_4831 : connect solitary_preload, UInt<1>(0h1) else : when funct_is_compute : connect solitary_preload, UInt<1>(0h0) node _issue_valids_T = or(entries_ld[0].bits.deps_ld[0], entries_ld[0].bits.deps_ld[1]) node _issue_valids_T_1 = or(_issue_valids_T, entries_ld[0].bits.deps_ld[2]) node _issue_valids_T_2 = or(_issue_valids_T_1, entries_ld[0].bits.deps_ld[3]) node _issue_valids_T_3 = or(_issue_valids_T_2, entries_ld[0].bits.deps_ld[4]) node _issue_valids_T_4 = or(_issue_valids_T_3, entries_ld[0].bits.deps_ld[5]) node _issue_valids_T_5 = or(_issue_valids_T_4, entries_ld[0].bits.deps_ld[6]) node _issue_valids_T_6 = or(_issue_valids_T_5, entries_ld[0].bits.deps_ld[7]) node _issue_valids_T_7 = or(entries_ld[0].bits.deps_ex[0], entries_ld[0].bits.deps_ex[1]) node _issue_valids_T_8 = or(_issue_valids_T_7, entries_ld[0].bits.deps_ex[2]) node _issue_valids_T_9 = or(_issue_valids_T_8, entries_ld[0].bits.deps_ex[3]) node _issue_valids_T_10 = or(_issue_valids_T_9, entries_ld[0].bits.deps_ex[4]) node _issue_valids_T_11 = or(_issue_valids_T_10, entries_ld[0].bits.deps_ex[5]) node _issue_valids_T_12 = or(_issue_valids_T_11, entries_ld[0].bits.deps_ex[6]) node _issue_valids_T_13 = or(_issue_valids_T_12, entries_ld[0].bits.deps_ex[7]) node _issue_valids_T_14 = or(_issue_valids_T_13, entries_ld[0].bits.deps_ex[8]) node _issue_valids_T_15 = or(_issue_valids_T_14, entries_ld[0].bits.deps_ex[9]) node _issue_valids_T_16 = or(_issue_valids_T_15, entries_ld[0].bits.deps_ex[10]) node _issue_valids_T_17 = or(_issue_valids_T_16, entries_ld[0].bits.deps_ex[11]) node _issue_valids_T_18 = or(_issue_valids_T_17, entries_ld[0].bits.deps_ex[12]) node _issue_valids_T_19 = or(_issue_valids_T_18, entries_ld[0].bits.deps_ex[13]) node _issue_valids_T_20 = or(_issue_valids_T_19, entries_ld[0].bits.deps_ex[14]) node _issue_valids_T_21 = or(_issue_valids_T_20, entries_ld[0].bits.deps_ex[15]) node _issue_valids_T_22 = or(_issue_valids_T_6, _issue_valids_T_21) node _issue_valids_T_23 = or(entries_ld[0].bits.deps_st[0], entries_ld[0].bits.deps_st[1]) node _issue_valids_T_24 = or(_issue_valids_T_23, entries_ld[0].bits.deps_st[2]) node _issue_valids_T_25 = or(_issue_valids_T_24, entries_ld[0].bits.deps_st[3]) node _issue_valids_T_26 = or(_issue_valids_T_22, _issue_valids_T_25) node _issue_valids_T_27 = eq(_issue_valids_T_26, UInt<1>(0h0)) node _issue_valids_T_28 = and(entries_ld[0].valid, _issue_valids_T_27) node _issue_valids_T_29 = eq(entries_ld[0].bits.issued, UInt<1>(0h0)) node issue_valids_0 = and(_issue_valids_T_28, _issue_valids_T_29) node _issue_valids_T_30 = or(entries_ld[1].bits.deps_ld[0], entries_ld[1].bits.deps_ld[1]) node _issue_valids_T_31 = or(_issue_valids_T_30, entries_ld[1].bits.deps_ld[2]) node _issue_valids_T_32 = or(_issue_valids_T_31, entries_ld[1].bits.deps_ld[3]) node _issue_valids_T_33 = or(_issue_valids_T_32, entries_ld[1].bits.deps_ld[4]) node _issue_valids_T_34 = or(_issue_valids_T_33, entries_ld[1].bits.deps_ld[5]) node _issue_valids_T_35 = or(_issue_valids_T_34, entries_ld[1].bits.deps_ld[6]) node _issue_valids_T_36 = or(_issue_valids_T_35, entries_ld[1].bits.deps_ld[7]) node _issue_valids_T_37 = or(entries_ld[1].bits.deps_ex[0], entries_ld[1].bits.deps_ex[1]) node _issue_valids_T_38 = or(_issue_valids_T_37, entries_ld[1].bits.deps_ex[2]) node _issue_valids_T_39 = or(_issue_valids_T_38, entries_ld[1].bits.deps_ex[3]) node _issue_valids_T_40 = or(_issue_valids_T_39, entries_ld[1].bits.deps_ex[4]) node _issue_valids_T_41 = or(_issue_valids_T_40, entries_ld[1].bits.deps_ex[5]) node _issue_valids_T_42 = or(_issue_valids_T_41, entries_ld[1].bits.deps_ex[6]) node _issue_valids_T_43 = or(_issue_valids_T_42, entries_ld[1].bits.deps_ex[7]) node _issue_valids_T_44 = or(_issue_valids_T_43, entries_ld[1].bits.deps_ex[8]) node _issue_valids_T_45 = or(_issue_valids_T_44, entries_ld[1].bits.deps_ex[9]) node _issue_valids_T_46 = or(_issue_valids_T_45, entries_ld[1].bits.deps_ex[10]) node _issue_valids_T_47 = or(_issue_valids_T_46, entries_ld[1].bits.deps_ex[11]) node _issue_valids_T_48 = or(_issue_valids_T_47, entries_ld[1].bits.deps_ex[12]) node _issue_valids_T_49 = or(_issue_valids_T_48, entries_ld[1].bits.deps_ex[13]) node _issue_valids_T_50 = or(_issue_valids_T_49, entries_ld[1].bits.deps_ex[14]) node _issue_valids_T_51 = or(_issue_valids_T_50, entries_ld[1].bits.deps_ex[15]) node _issue_valids_T_52 = or(_issue_valids_T_36, _issue_valids_T_51) node _issue_valids_T_53 = or(entries_ld[1].bits.deps_st[0], entries_ld[1].bits.deps_st[1]) node _issue_valids_T_54 = or(_issue_valids_T_53, entries_ld[1].bits.deps_st[2]) node _issue_valids_T_55 = or(_issue_valids_T_54, entries_ld[1].bits.deps_st[3]) node _issue_valids_T_56 = or(_issue_valids_T_52, _issue_valids_T_55) node _issue_valids_T_57 = eq(_issue_valids_T_56, UInt<1>(0h0)) node _issue_valids_T_58 = and(entries_ld[1].valid, _issue_valids_T_57) node _issue_valids_T_59 = eq(entries_ld[1].bits.issued, UInt<1>(0h0)) node issue_valids_1 = and(_issue_valids_T_58, _issue_valids_T_59) node _issue_valids_T_60 = or(entries_ld[2].bits.deps_ld[0], entries_ld[2].bits.deps_ld[1]) node _issue_valids_T_61 = or(_issue_valids_T_60, entries_ld[2].bits.deps_ld[2]) node _issue_valids_T_62 = or(_issue_valids_T_61, entries_ld[2].bits.deps_ld[3]) node _issue_valids_T_63 = or(_issue_valids_T_62, entries_ld[2].bits.deps_ld[4]) node _issue_valids_T_64 = or(_issue_valids_T_63, entries_ld[2].bits.deps_ld[5]) node _issue_valids_T_65 = or(_issue_valids_T_64, entries_ld[2].bits.deps_ld[6]) node _issue_valids_T_66 = or(_issue_valids_T_65, entries_ld[2].bits.deps_ld[7]) node _issue_valids_T_67 = or(entries_ld[2].bits.deps_ex[0], entries_ld[2].bits.deps_ex[1]) node _issue_valids_T_68 = or(_issue_valids_T_67, entries_ld[2].bits.deps_ex[2]) node _issue_valids_T_69 = or(_issue_valids_T_68, entries_ld[2].bits.deps_ex[3]) node _issue_valids_T_70 = or(_issue_valids_T_69, entries_ld[2].bits.deps_ex[4]) node _issue_valids_T_71 = or(_issue_valids_T_70, entries_ld[2].bits.deps_ex[5]) node _issue_valids_T_72 = or(_issue_valids_T_71, entries_ld[2].bits.deps_ex[6]) node _issue_valids_T_73 = or(_issue_valids_T_72, entries_ld[2].bits.deps_ex[7]) node _issue_valids_T_74 = or(_issue_valids_T_73, entries_ld[2].bits.deps_ex[8]) node _issue_valids_T_75 = or(_issue_valids_T_74, entries_ld[2].bits.deps_ex[9]) node _issue_valids_T_76 = or(_issue_valids_T_75, entries_ld[2].bits.deps_ex[10]) node _issue_valids_T_77 = or(_issue_valids_T_76, entries_ld[2].bits.deps_ex[11]) node _issue_valids_T_78 = or(_issue_valids_T_77, entries_ld[2].bits.deps_ex[12]) node _issue_valids_T_79 = or(_issue_valids_T_78, entries_ld[2].bits.deps_ex[13]) node _issue_valids_T_80 = or(_issue_valids_T_79, entries_ld[2].bits.deps_ex[14]) node _issue_valids_T_81 = or(_issue_valids_T_80, entries_ld[2].bits.deps_ex[15]) node _issue_valids_T_82 = or(_issue_valids_T_66, _issue_valids_T_81) node _issue_valids_T_83 = or(entries_ld[2].bits.deps_st[0], entries_ld[2].bits.deps_st[1]) node _issue_valids_T_84 = or(_issue_valids_T_83, entries_ld[2].bits.deps_st[2]) node _issue_valids_T_85 = or(_issue_valids_T_84, entries_ld[2].bits.deps_st[3]) node _issue_valids_T_86 = or(_issue_valids_T_82, _issue_valids_T_85) node _issue_valids_T_87 = eq(_issue_valids_T_86, UInt<1>(0h0)) node _issue_valids_T_88 = and(entries_ld[2].valid, _issue_valids_T_87) node _issue_valids_T_89 = eq(entries_ld[2].bits.issued, UInt<1>(0h0)) node issue_valids_2 = and(_issue_valids_T_88, _issue_valids_T_89) node _issue_valids_T_90 = or(entries_ld[3].bits.deps_ld[0], entries_ld[3].bits.deps_ld[1]) node _issue_valids_T_91 = or(_issue_valids_T_90, entries_ld[3].bits.deps_ld[2]) node _issue_valids_T_92 = or(_issue_valids_T_91, entries_ld[3].bits.deps_ld[3]) node _issue_valids_T_93 = or(_issue_valids_T_92, entries_ld[3].bits.deps_ld[4]) node _issue_valids_T_94 = or(_issue_valids_T_93, entries_ld[3].bits.deps_ld[5]) node _issue_valids_T_95 = or(_issue_valids_T_94, entries_ld[3].bits.deps_ld[6]) node _issue_valids_T_96 = or(_issue_valids_T_95, entries_ld[3].bits.deps_ld[7]) node _issue_valids_T_97 = or(entries_ld[3].bits.deps_ex[0], entries_ld[3].bits.deps_ex[1]) node _issue_valids_T_98 = or(_issue_valids_T_97, entries_ld[3].bits.deps_ex[2]) node _issue_valids_T_99 = or(_issue_valids_T_98, entries_ld[3].bits.deps_ex[3]) node _issue_valids_T_100 = or(_issue_valids_T_99, entries_ld[3].bits.deps_ex[4]) node _issue_valids_T_101 = or(_issue_valids_T_100, entries_ld[3].bits.deps_ex[5]) node _issue_valids_T_102 = or(_issue_valids_T_101, entries_ld[3].bits.deps_ex[6]) node _issue_valids_T_103 = or(_issue_valids_T_102, entries_ld[3].bits.deps_ex[7]) node _issue_valids_T_104 = or(_issue_valids_T_103, entries_ld[3].bits.deps_ex[8]) node _issue_valids_T_105 = or(_issue_valids_T_104, entries_ld[3].bits.deps_ex[9]) node _issue_valids_T_106 = or(_issue_valids_T_105, entries_ld[3].bits.deps_ex[10]) node _issue_valids_T_107 = or(_issue_valids_T_106, entries_ld[3].bits.deps_ex[11]) node _issue_valids_T_108 = or(_issue_valids_T_107, entries_ld[3].bits.deps_ex[12]) node _issue_valids_T_109 = or(_issue_valids_T_108, entries_ld[3].bits.deps_ex[13]) node _issue_valids_T_110 = or(_issue_valids_T_109, entries_ld[3].bits.deps_ex[14]) node _issue_valids_T_111 = or(_issue_valids_T_110, entries_ld[3].bits.deps_ex[15]) node _issue_valids_T_112 = or(_issue_valids_T_96, _issue_valids_T_111) node _issue_valids_T_113 = or(entries_ld[3].bits.deps_st[0], entries_ld[3].bits.deps_st[1]) node _issue_valids_T_114 = or(_issue_valids_T_113, entries_ld[3].bits.deps_st[2]) node _issue_valids_T_115 = or(_issue_valids_T_114, entries_ld[3].bits.deps_st[3]) node _issue_valids_T_116 = or(_issue_valids_T_112, _issue_valids_T_115) node _issue_valids_T_117 = eq(_issue_valids_T_116, UInt<1>(0h0)) node _issue_valids_T_118 = and(entries_ld[3].valid, _issue_valids_T_117) node _issue_valids_T_119 = eq(entries_ld[3].bits.issued, UInt<1>(0h0)) node issue_valids_3 = and(_issue_valids_T_118, _issue_valids_T_119) node _issue_valids_T_120 = or(entries_ld[4].bits.deps_ld[0], entries_ld[4].bits.deps_ld[1]) node _issue_valids_T_121 = or(_issue_valids_T_120, entries_ld[4].bits.deps_ld[2]) node _issue_valids_T_122 = or(_issue_valids_T_121, entries_ld[4].bits.deps_ld[3]) node _issue_valids_T_123 = or(_issue_valids_T_122, entries_ld[4].bits.deps_ld[4]) node _issue_valids_T_124 = or(_issue_valids_T_123, entries_ld[4].bits.deps_ld[5]) node _issue_valids_T_125 = or(_issue_valids_T_124, entries_ld[4].bits.deps_ld[6]) node _issue_valids_T_126 = or(_issue_valids_T_125, entries_ld[4].bits.deps_ld[7]) node _issue_valids_T_127 = or(entries_ld[4].bits.deps_ex[0], entries_ld[4].bits.deps_ex[1]) node _issue_valids_T_128 = or(_issue_valids_T_127, entries_ld[4].bits.deps_ex[2]) node _issue_valids_T_129 = or(_issue_valids_T_128, entries_ld[4].bits.deps_ex[3]) node _issue_valids_T_130 = or(_issue_valids_T_129, entries_ld[4].bits.deps_ex[4]) node _issue_valids_T_131 = or(_issue_valids_T_130, entries_ld[4].bits.deps_ex[5]) node _issue_valids_T_132 = or(_issue_valids_T_131, entries_ld[4].bits.deps_ex[6]) node _issue_valids_T_133 = or(_issue_valids_T_132, entries_ld[4].bits.deps_ex[7]) node _issue_valids_T_134 = or(_issue_valids_T_133, entries_ld[4].bits.deps_ex[8]) node _issue_valids_T_135 = or(_issue_valids_T_134, entries_ld[4].bits.deps_ex[9]) node _issue_valids_T_136 = or(_issue_valids_T_135, entries_ld[4].bits.deps_ex[10]) node _issue_valids_T_137 = or(_issue_valids_T_136, entries_ld[4].bits.deps_ex[11]) node _issue_valids_T_138 = or(_issue_valids_T_137, entries_ld[4].bits.deps_ex[12]) node _issue_valids_T_139 = or(_issue_valids_T_138, entries_ld[4].bits.deps_ex[13]) node _issue_valids_T_140 = or(_issue_valids_T_139, entries_ld[4].bits.deps_ex[14]) node _issue_valids_T_141 = or(_issue_valids_T_140, entries_ld[4].bits.deps_ex[15]) node _issue_valids_T_142 = or(_issue_valids_T_126, _issue_valids_T_141) node _issue_valids_T_143 = or(entries_ld[4].bits.deps_st[0], entries_ld[4].bits.deps_st[1]) node _issue_valids_T_144 = or(_issue_valids_T_143, entries_ld[4].bits.deps_st[2]) node _issue_valids_T_145 = or(_issue_valids_T_144, entries_ld[4].bits.deps_st[3]) node _issue_valids_T_146 = or(_issue_valids_T_142, _issue_valids_T_145) node _issue_valids_T_147 = eq(_issue_valids_T_146, UInt<1>(0h0)) node _issue_valids_T_148 = and(entries_ld[4].valid, _issue_valids_T_147) node _issue_valids_T_149 = eq(entries_ld[4].bits.issued, UInt<1>(0h0)) node issue_valids_4 = and(_issue_valids_T_148, _issue_valids_T_149) node _issue_valids_T_150 = or(entries_ld[5].bits.deps_ld[0], entries_ld[5].bits.deps_ld[1]) node _issue_valids_T_151 = or(_issue_valids_T_150, entries_ld[5].bits.deps_ld[2]) node _issue_valids_T_152 = or(_issue_valids_T_151, entries_ld[5].bits.deps_ld[3]) node _issue_valids_T_153 = or(_issue_valids_T_152, entries_ld[5].bits.deps_ld[4]) node _issue_valids_T_154 = or(_issue_valids_T_153, entries_ld[5].bits.deps_ld[5]) node _issue_valids_T_155 = or(_issue_valids_T_154, entries_ld[5].bits.deps_ld[6]) node _issue_valids_T_156 = or(_issue_valids_T_155, entries_ld[5].bits.deps_ld[7]) node _issue_valids_T_157 = or(entries_ld[5].bits.deps_ex[0], entries_ld[5].bits.deps_ex[1]) node _issue_valids_T_158 = or(_issue_valids_T_157, entries_ld[5].bits.deps_ex[2]) node _issue_valids_T_159 = or(_issue_valids_T_158, entries_ld[5].bits.deps_ex[3]) node _issue_valids_T_160 = or(_issue_valids_T_159, entries_ld[5].bits.deps_ex[4]) node _issue_valids_T_161 = or(_issue_valids_T_160, entries_ld[5].bits.deps_ex[5]) node _issue_valids_T_162 = or(_issue_valids_T_161, entries_ld[5].bits.deps_ex[6]) node _issue_valids_T_163 = or(_issue_valids_T_162, entries_ld[5].bits.deps_ex[7]) node _issue_valids_T_164 = or(_issue_valids_T_163, entries_ld[5].bits.deps_ex[8]) node _issue_valids_T_165 = or(_issue_valids_T_164, entries_ld[5].bits.deps_ex[9]) node _issue_valids_T_166 = or(_issue_valids_T_165, entries_ld[5].bits.deps_ex[10]) node _issue_valids_T_167 = or(_issue_valids_T_166, entries_ld[5].bits.deps_ex[11]) node _issue_valids_T_168 = or(_issue_valids_T_167, entries_ld[5].bits.deps_ex[12]) node _issue_valids_T_169 = or(_issue_valids_T_168, entries_ld[5].bits.deps_ex[13]) node _issue_valids_T_170 = or(_issue_valids_T_169, entries_ld[5].bits.deps_ex[14]) node _issue_valids_T_171 = or(_issue_valids_T_170, entries_ld[5].bits.deps_ex[15]) node _issue_valids_T_172 = or(_issue_valids_T_156, _issue_valids_T_171) node _issue_valids_T_173 = or(entries_ld[5].bits.deps_st[0], entries_ld[5].bits.deps_st[1]) node _issue_valids_T_174 = or(_issue_valids_T_173, entries_ld[5].bits.deps_st[2]) node _issue_valids_T_175 = or(_issue_valids_T_174, entries_ld[5].bits.deps_st[3]) node _issue_valids_T_176 = or(_issue_valids_T_172, _issue_valids_T_175) node _issue_valids_T_177 = eq(_issue_valids_T_176, UInt<1>(0h0)) node _issue_valids_T_178 = and(entries_ld[5].valid, _issue_valids_T_177) node _issue_valids_T_179 = eq(entries_ld[5].bits.issued, UInt<1>(0h0)) node issue_valids_5 = and(_issue_valids_T_178, _issue_valids_T_179) node _issue_valids_T_180 = or(entries_ld[6].bits.deps_ld[0], entries_ld[6].bits.deps_ld[1]) node _issue_valids_T_181 = or(_issue_valids_T_180, entries_ld[6].bits.deps_ld[2]) node _issue_valids_T_182 = or(_issue_valids_T_181, entries_ld[6].bits.deps_ld[3]) node _issue_valids_T_183 = or(_issue_valids_T_182, entries_ld[6].bits.deps_ld[4]) node _issue_valids_T_184 = or(_issue_valids_T_183, entries_ld[6].bits.deps_ld[5]) node _issue_valids_T_185 = or(_issue_valids_T_184, entries_ld[6].bits.deps_ld[6]) node _issue_valids_T_186 = or(_issue_valids_T_185, entries_ld[6].bits.deps_ld[7]) node _issue_valids_T_187 = or(entries_ld[6].bits.deps_ex[0], entries_ld[6].bits.deps_ex[1]) node _issue_valids_T_188 = or(_issue_valids_T_187, entries_ld[6].bits.deps_ex[2]) node _issue_valids_T_189 = or(_issue_valids_T_188, entries_ld[6].bits.deps_ex[3]) node _issue_valids_T_190 = or(_issue_valids_T_189, entries_ld[6].bits.deps_ex[4]) node _issue_valids_T_191 = or(_issue_valids_T_190, entries_ld[6].bits.deps_ex[5]) node _issue_valids_T_192 = or(_issue_valids_T_191, entries_ld[6].bits.deps_ex[6]) node _issue_valids_T_193 = or(_issue_valids_T_192, entries_ld[6].bits.deps_ex[7]) node _issue_valids_T_194 = or(_issue_valids_T_193, entries_ld[6].bits.deps_ex[8]) node _issue_valids_T_195 = or(_issue_valids_T_194, entries_ld[6].bits.deps_ex[9]) node _issue_valids_T_196 = or(_issue_valids_T_195, entries_ld[6].bits.deps_ex[10]) node _issue_valids_T_197 = or(_issue_valids_T_196, entries_ld[6].bits.deps_ex[11]) node _issue_valids_T_198 = or(_issue_valids_T_197, entries_ld[6].bits.deps_ex[12]) node _issue_valids_T_199 = or(_issue_valids_T_198, entries_ld[6].bits.deps_ex[13]) node _issue_valids_T_200 = or(_issue_valids_T_199, entries_ld[6].bits.deps_ex[14]) node _issue_valids_T_201 = or(_issue_valids_T_200, entries_ld[6].bits.deps_ex[15]) node _issue_valids_T_202 = or(_issue_valids_T_186, _issue_valids_T_201) node _issue_valids_T_203 = or(entries_ld[6].bits.deps_st[0], entries_ld[6].bits.deps_st[1]) node _issue_valids_T_204 = or(_issue_valids_T_203, entries_ld[6].bits.deps_st[2]) node _issue_valids_T_205 = or(_issue_valids_T_204, entries_ld[6].bits.deps_st[3]) node _issue_valids_T_206 = or(_issue_valids_T_202, _issue_valids_T_205) node _issue_valids_T_207 = eq(_issue_valids_T_206, UInt<1>(0h0)) node _issue_valids_T_208 = and(entries_ld[6].valid, _issue_valids_T_207) node _issue_valids_T_209 = eq(entries_ld[6].bits.issued, UInt<1>(0h0)) node issue_valids_6 = and(_issue_valids_T_208, _issue_valids_T_209) node _issue_valids_T_210 = or(entries_ld[7].bits.deps_ld[0], entries_ld[7].bits.deps_ld[1]) node _issue_valids_T_211 = or(_issue_valids_T_210, entries_ld[7].bits.deps_ld[2]) node _issue_valids_T_212 = or(_issue_valids_T_211, entries_ld[7].bits.deps_ld[3]) node _issue_valids_T_213 = or(_issue_valids_T_212, entries_ld[7].bits.deps_ld[4]) node _issue_valids_T_214 = or(_issue_valids_T_213, entries_ld[7].bits.deps_ld[5]) node _issue_valids_T_215 = or(_issue_valids_T_214, entries_ld[7].bits.deps_ld[6]) node _issue_valids_T_216 = or(_issue_valids_T_215, entries_ld[7].bits.deps_ld[7]) node _issue_valids_T_217 = or(entries_ld[7].bits.deps_ex[0], entries_ld[7].bits.deps_ex[1]) node _issue_valids_T_218 = or(_issue_valids_T_217, entries_ld[7].bits.deps_ex[2]) node _issue_valids_T_219 = or(_issue_valids_T_218, entries_ld[7].bits.deps_ex[3]) node _issue_valids_T_220 = or(_issue_valids_T_219, entries_ld[7].bits.deps_ex[4]) node _issue_valids_T_221 = or(_issue_valids_T_220, entries_ld[7].bits.deps_ex[5]) node _issue_valids_T_222 = or(_issue_valids_T_221, entries_ld[7].bits.deps_ex[6]) node _issue_valids_T_223 = or(_issue_valids_T_222, entries_ld[7].bits.deps_ex[7]) node _issue_valids_T_224 = or(_issue_valids_T_223, entries_ld[7].bits.deps_ex[8]) node _issue_valids_T_225 = or(_issue_valids_T_224, entries_ld[7].bits.deps_ex[9]) node _issue_valids_T_226 = or(_issue_valids_T_225, entries_ld[7].bits.deps_ex[10]) node _issue_valids_T_227 = or(_issue_valids_T_226, entries_ld[7].bits.deps_ex[11]) node _issue_valids_T_228 = or(_issue_valids_T_227, entries_ld[7].bits.deps_ex[12]) node _issue_valids_T_229 = or(_issue_valids_T_228, entries_ld[7].bits.deps_ex[13]) node _issue_valids_T_230 = or(_issue_valids_T_229, entries_ld[7].bits.deps_ex[14]) node _issue_valids_T_231 = or(_issue_valids_T_230, entries_ld[7].bits.deps_ex[15]) node _issue_valids_T_232 = or(_issue_valids_T_216, _issue_valids_T_231) node _issue_valids_T_233 = or(entries_ld[7].bits.deps_st[0], entries_ld[7].bits.deps_st[1]) node _issue_valids_T_234 = or(_issue_valids_T_233, entries_ld[7].bits.deps_st[2]) node _issue_valids_T_235 = or(_issue_valids_T_234, entries_ld[7].bits.deps_st[3]) node _issue_valids_T_236 = or(_issue_valids_T_232, _issue_valids_T_235) node _issue_valids_T_237 = eq(_issue_valids_T_236, UInt<1>(0h0)) node _issue_valids_T_238 = and(entries_ld[7].valid, _issue_valids_T_237) node _issue_valids_T_239 = eq(entries_ld[7].bits.issued, UInt<1>(0h0)) node issue_valids_7 = and(_issue_valids_T_238, _issue_valids_T_239) node _issue_sel_enc_T = mux(issue_valids_7, UInt<8>(0h80), UInt<8>(0h0)) node _issue_sel_enc_T_1 = mux(issue_valids_6, UInt<8>(0h40), _issue_sel_enc_T) node _issue_sel_enc_T_2 = mux(issue_valids_5, UInt<8>(0h20), _issue_sel_enc_T_1) node _issue_sel_enc_T_3 = mux(issue_valids_4, UInt<8>(0h10), _issue_sel_enc_T_2) node _issue_sel_enc_T_4 = mux(issue_valids_3, UInt<8>(0h8), _issue_sel_enc_T_3) node _issue_sel_enc_T_5 = mux(issue_valids_2, UInt<8>(0h4), _issue_sel_enc_T_4) node _issue_sel_enc_T_6 = mux(issue_valids_1, UInt<8>(0h2), _issue_sel_enc_T_5) node issue_sel_enc = mux(issue_valids_0, UInt<8>(0h1), _issue_sel_enc_T_6) node issue_sel_0 = bits(issue_sel_enc, 0, 0) node issue_sel_1 = bits(issue_sel_enc, 1, 1) node issue_sel_2 = bits(issue_sel_enc, 2, 2) node issue_sel_3 = bits(issue_sel_enc, 3, 3) node issue_sel_4 = bits(issue_sel_enc, 4, 4) node issue_sel_5 = bits(issue_sel_enc, 5, 5) node issue_sel_6 = bits(issue_sel_enc, 6, 6) node issue_sel_7 = bits(issue_sel_enc, 7, 7) node issue_id_lo_lo = cat(issue_sel_1, issue_sel_0) node issue_id_lo_hi = cat(issue_sel_3, issue_sel_2) node issue_id_lo = cat(issue_id_lo_hi, issue_id_lo_lo) node issue_id_hi_lo = cat(issue_sel_5, issue_sel_4) node issue_id_hi_hi = cat(issue_sel_7, issue_sel_6) node issue_id_hi = cat(issue_id_hi_hi, issue_id_hi_lo) node _issue_id_T = cat(issue_id_hi, issue_id_lo) node issue_id_hi_1 = bits(_issue_id_T, 7, 4) node issue_id_lo_1 = bits(_issue_id_T, 3, 0) node _issue_id_T_1 = orr(issue_id_hi_1) node _issue_id_T_2 = or(issue_id_hi_1, issue_id_lo_1) node issue_id_hi_2 = bits(_issue_id_T_2, 3, 2) node issue_id_lo_2 = bits(_issue_id_T_2, 1, 0) node _issue_id_T_3 = orr(issue_id_hi_2) node _issue_id_T_4 = or(issue_id_hi_2, issue_id_lo_2) node _issue_id_T_5 = bits(_issue_id_T_4, 1, 1) node _issue_id_T_6 = cat(_issue_id_T_3, _issue_id_T_5) node issue_id = cat(_issue_id_T_1, _issue_id_T_6) node _global_issue_id_T = pad(issue_id, 4) node global_issue_id = cat(UInt<2>(0h0), _global_issue_id_T) wire issue_entry : { valid : UInt<1>, bits : { q : UInt<2>, is_config : UInt<1>, opa : { valid : UInt<1>, bits : { start : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, end : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, wraps_around : UInt<1>}}, opa_is_dst : UInt<1>, opb : { valid : UInt<1>, bits : { start : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, end : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, wraps_around : UInt<1>}}, issued : UInt<1>, complete_on_issue : UInt<1>, cmd : { cmd : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, rob_id : { valid : UInt<1>, bits : UInt<6>}, from_matmul_fsm : UInt<1>, from_conv_fsm : UInt<1>}, deps_ld : UInt<1>[8], deps_ex : UInt<1>[16], deps_st : UInt<1>[4], allocated_at : UInt<32>}} wire _issue_entry_WIRE : { q : UInt<2>, is_config : UInt<1>, opa : { valid : UInt<1>, bits : { start : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, end : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, wraps_around : UInt<1>}}, opa_is_dst : UInt<1>, opb : { valid : UInt<1>, bits : { start : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, end : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, wraps_around : UInt<1>}}, issued : UInt<1>, complete_on_issue : UInt<1>, cmd : { cmd : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, rob_id : { valid : UInt<1>, bits : UInt<6>}, from_matmul_fsm : UInt<1>, from_conv_fsm : UInt<1>}, deps_ld : UInt<1>[8], deps_ex : UInt<1>[16], deps_st : UInt<1>[4], allocated_at : UInt<32>} node _issue_entry_T = mux(issue_sel_0, entries_ld[0].bits.allocated_at, UInt<1>(0h0)) node _issue_entry_T_1 = mux(issue_sel_1, entries_ld[1].bits.allocated_at, UInt<1>(0h0)) node _issue_entry_T_2 = mux(issue_sel_2, entries_ld[2].bits.allocated_at, UInt<1>(0h0)) node _issue_entry_T_3 = mux(issue_sel_3, entries_ld[3].bits.allocated_at, UInt<1>(0h0)) node _issue_entry_T_4 = mux(issue_sel_4, entries_ld[4].bits.allocated_at, UInt<1>(0h0)) node _issue_entry_T_5 = mux(issue_sel_5, entries_ld[5].bits.allocated_at, UInt<1>(0h0)) node _issue_entry_T_6 = mux(issue_sel_6, entries_ld[6].bits.allocated_at, UInt<1>(0h0)) node _issue_entry_T_7 = mux(issue_sel_7, entries_ld[7].bits.allocated_at, UInt<1>(0h0)) node _issue_entry_T_8 = or(_issue_entry_T, _issue_entry_T_1) node _issue_entry_T_9 = or(_issue_entry_T_8, _issue_entry_T_2) node _issue_entry_T_10 = or(_issue_entry_T_9, _issue_entry_T_3) node _issue_entry_T_11 = or(_issue_entry_T_10, _issue_entry_T_4) node _issue_entry_T_12 = or(_issue_entry_T_11, _issue_entry_T_5) node _issue_entry_T_13 = or(_issue_entry_T_12, _issue_entry_T_6) node _issue_entry_T_14 = or(_issue_entry_T_13, _issue_entry_T_7) wire _issue_entry_WIRE_1 : UInt<32> connect _issue_entry_WIRE_1, _issue_entry_T_14 connect _issue_entry_WIRE.allocated_at, _issue_entry_WIRE_1 wire _issue_entry_WIRE_2 : UInt<1>[4] node _issue_entry_T_15 = mux(issue_sel_0, entries_ld[0].bits.deps_st[0], UInt<1>(0h0)) node _issue_entry_T_16 = mux(issue_sel_1, entries_ld[1].bits.deps_st[0], UInt<1>(0h0)) node _issue_entry_T_17 = mux(issue_sel_2, entries_ld[2].bits.deps_st[0], UInt<1>(0h0)) node _issue_entry_T_18 = mux(issue_sel_3, entries_ld[3].bits.deps_st[0], UInt<1>(0h0)) node _issue_entry_T_19 = mux(issue_sel_4, entries_ld[4].bits.deps_st[0], UInt<1>(0h0)) node _issue_entry_T_20 = mux(issue_sel_5, entries_ld[5].bits.deps_st[0], UInt<1>(0h0)) node _issue_entry_T_21 = mux(issue_sel_6, entries_ld[6].bits.deps_st[0], UInt<1>(0h0)) node _issue_entry_T_22 = mux(issue_sel_7, entries_ld[7].bits.deps_st[0], UInt<1>(0h0)) node _issue_entry_T_23 = or(_issue_entry_T_15, _issue_entry_T_16) node _issue_entry_T_24 = or(_issue_entry_T_23, _issue_entry_T_17) node _issue_entry_T_25 = or(_issue_entry_T_24, _issue_entry_T_18) node _issue_entry_T_26 = or(_issue_entry_T_25, _issue_entry_T_19) node _issue_entry_T_27 = or(_issue_entry_T_26, _issue_entry_T_20) node _issue_entry_T_28 = or(_issue_entry_T_27, _issue_entry_T_21) node _issue_entry_T_29 = or(_issue_entry_T_28, _issue_entry_T_22) wire _issue_entry_WIRE_3 : UInt<1> connect _issue_entry_WIRE_3, _issue_entry_T_29 connect _issue_entry_WIRE_2[0], _issue_entry_WIRE_3 node _issue_entry_T_30 = mux(issue_sel_0, entries_ld[0].bits.deps_st[1], UInt<1>(0h0)) node _issue_entry_T_31 = mux(issue_sel_1, entries_ld[1].bits.deps_st[1], UInt<1>(0h0)) node _issue_entry_T_32 = mux(issue_sel_2, entries_ld[2].bits.deps_st[1], UInt<1>(0h0)) node _issue_entry_T_33 = mux(issue_sel_3, entries_ld[3].bits.deps_st[1], UInt<1>(0h0)) node _issue_entry_T_34 = mux(issue_sel_4, entries_ld[4].bits.deps_st[1], UInt<1>(0h0)) node _issue_entry_T_35 = mux(issue_sel_5, entries_ld[5].bits.deps_st[1], UInt<1>(0h0)) node _issue_entry_T_36 = mux(issue_sel_6, entries_ld[6].bits.deps_st[1], UInt<1>(0h0)) node _issue_entry_T_37 = mux(issue_sel_7, entries_ld[7].bits.deps_st[1], UInt<1>(0h0)) node _issue_entry_T_38 = or(_issue_entry_T_30, _issue_entry_T_31) node _issue_entry_T_39 = or(_issue_entry_T_38, _issue_entry_T_32) node _issue_entry_T_40 = or(_issue_entry_T_39, _issue_entry_T_33) node _issue_entry_T_41 = or(_issue_entry_T_40, _issue_entry_T_34) node _issue_entry_T_42 = or(_issue_entry_T_41, _issue_entry_T_35) node _issue_entry_T_43 = or(_issue_entry_T_42, _issue_entry_T_36) node _issue_entry_T_44 = or(_issue_entry_T_43, _issue_entry_T_37) wire _issue_entry_WIRE_4 : UInt<1> connect _issue_entry_WIRE_4, _issue_entry_T_44 connect _issue_entry_WIRE_2[1], _issue_entry_WIRE_4 node _issue_entry_T_45 = mux(issue_sel_0, entries_ld[0].bits.deps_st[2], UInt<1>(0h0)) node _issue_entry_T_46 = mux(issue_sel_1, entries_ld[1].bits.deps_st[2], UInt<1>(0h0)) node _issue_entry_T_47 = mux(issue_sel_2, entries_ld[2].bits.deps_st[2], UInt<1>(0h0)) node _issue_entry_T_48 = mux(issue_sel_3, entries_ld[3].bits.deps_st[2], UInt<1>(0h0)) node _issue_entry_T_49 = mux(issue_sel_4, entries_ld[4].bits.deps_st[2], UInt<1>(0h0)) node _issue_entry_T_50 = mux(issue_sel_5, entries_ld[5].bits.deps_st[2], UInt<1>(0h0)) node _issue_entry_T_51 = mux(issue_sel_6, entries_ld[6].bits.deps_st[2], UInt<1>(0h0)) node _issue_entry_T_52 = mux(issue_sel_7, entries_ld[7].bits.deps_st[2], UInt<1>(0h0)) node _issue_entry_T_53 = or(_issue_entry_T_45, _issue_entry_T_46) node _issue_entry_T_54 = or(_issue_entry_T_53, _issue_entry_T_47) node _issue_entry_T_55 = or(_issue_entry_T_54, _issue_entry_T_48) node _issue_entry_T_56 = or(_issue_entry_T_55, _issue_entry_T_49) node _issue_entry_T_57 = or(_issue_entry_T_56, _issue_entry_T_50) node _issue_entry_T_58 = or(_issue_entry_T_57, _issue_entry_T_51) node _issue_entry_T_59 = or(_issue_entry_T_58, _issue_entry_T_52) wire _issue_entry_WIRE_5 : UInt<1> connect _issue_entry_WIRE_5, _issue_entry_T_59 connect _issue_entry_WIRE_2[2], _issue_entry_WIRE_5 node _issue_entry_T_60 = mux(issue_sel_0, entries_ld[0].bits.deps_st[3], UInt<1>(0h0)) node _issue_entry_T_61 = mux(issue_sel_1, entries_ld[1].bits.deps_st[3], UInt<1>(0h0)) node _issue_entry_T_62 = mux(issue_sel_2, entries_ld[2].bits.deps_st[3], UInt<1>(0h0)) node _issue_entry_T_63 = mux(issue_sel_3, entries_ld[3].bits.deps_st[3], UInt<1>(0h0)) node _issue_entry_T_64 = mux(issue_sel_4, entries_ld[4].bits.deps_st[3], UInt<1>(0h0)) node _issue_entry_T_65 = mux(issue_sel_5, entries_ld[5].bits.deps_st[3], UInt<1>(0h0)) node _issue_entry_T_66 = mux(issue_sel_6, entries_ld[6].bits.deps_st[3], UInt<1>(0h0)) node _issue_entry_T_67 = mux(issue_sel_7, entries_ld[7].bits.deps_st[3], UInt<1>(0h0)) node _issue_entry_T_68 = or(_issue_entry_T_60, _issue_entry_T_61) node _issue_entry_T_69 = or(_issue_entry_T_68, _issue_entry_T_62) node _issue_entry_T_70 = or(_issue_entry_T_69, _issue_entry_T_63) node _issue_entry_T_71 = or(_issue_entry_T_70, _issue_entry_T_64) node _issue_entry_T_72 = or(_issue_entry_T_71, _issue_entry_T_65) node _issue_entry_T_73 = or(_issue_entry_T_72, _issue_entry_T_66) node _issue_entry_T_74 = or(_issue_entry_T_73, _issue_entry_T_67) wire _issue_entry_WIRE_6 : UInt<1> connect _issue_entry_WIRE_6, _issue_entry_T_74 connect _issue_entry_WIRE_2[3], _issue_entry_WIRE_6 connect _issue_entry_WIRE.deps_st, _issue_entry_WIRE_2 wire _issue_entry_WIRE_7 : UInt<1>[16] node _issue_entry_T_75 = mux(issue_sel_0, entries_ld[0].bits.deps_ex[0], UInt<1>(0h0)) node _issue_entry_T_76 = mux(issue_sel_1, entries_ld[1].bits.deps_ex[0], UInt<1>(0h0)) node _issue_entry_T_77 = mux(issue_sel_2, entries_ld[2].bits.deps_ex[0], UInt<1>(0h0)) node _issue_entry_T_78 = mux(issue_sel_3, entries_ld[3].bits.deps_ex[0], UInt<1>(0h0)) node _issue_entry_T_79 = mux(issue_sel_4, entries_ld[4].bits.deps_ex[0], UInt<1>(0h0)) node _issue_entry_T_80 = mux(issue_sel_5, entries_ld[5].bits.deps_ex[0], UInt<1>(0h0)) node _issue_entry_T_81 = mux(issue_sel_6, entries_ld[6].bits.deps_ex[0], UInt<1>(0h0)) node _issue_entry_T_82 = mux(issue_sel_7, entries_ld[7].bits.deps_ex[0], UInt<1>(0h0)) node _issue_entry_T_83 = or(_issue_entry_T_75, _issue_entry_T_76) node _issue_entry_T_84 = or(_issue_entry_T_83, _issue_entry_T_77) node _issue_entry_T_85 = or(_issue_entry_T_84, _issue_entry_T_78) node _issue_entry_T_86 = or(_issue_entry_T_85, _issue_entry_T_79) node _issue_entry_T_87 = or(_issue_entry_T_86, _issue_entry_T_80) node _issue_entry_T_88 = or(_issue_entry_T_87, _issue_entry_T_81) node _issue_entry_T_89 = or(_issue_entry_T_88, _issue_entry_T_82) wire _issue_entry_WIRE_8 : UInt<1> connect _issue_entry_WIRE_8, _issue_entry_T_89 connect _issue_entry_WIRE_7[0], _issue_entry_WIRE_8 node _issue_entry_T_90 = mux(issue_sel_0, entries_ld[0].bits.deps_ex[1], UInt<1>(0h0)) node _issue_entry_T_91 = mux(issue_sel_1, entries_ld[1].bits.deps_ex[1], UInt<1>(0h0)) node _issue_entry_T_92 = mux(issue_sel_2, entries_ld[2].bits.deps_ex[1], UInt<1>(0h0)) node _issue_entry_T_93 = mux(issue_sel_3, entries_ld[3].bits.deps_ex[1], UInt<1>(0h0)) node _issue_entry_T_94 = mux(issue_sel_4, entries_ld[4].bits.deps_ex[1], UInt<1>(0h0)) node _issue_entry_T_95 = mux(issue_sel_5, entries_ld[5].bits.deps_ex[1], UInt<1>(0h0)) node _issue_entry_T_96 = mux(issue_sel_6, entries_ld[6].bits.deps_ex[1], UInt<1>(0h0)) node _issue_entry_T_97 = mux(issue_sel_7, entries_ld[7].bits.deps_ex[1], UInt<1>(0h0)) node _issue_entry_T_98 = or(_issue_entry_T_90, _issue_entry_T_91) node _issue_entry_T_99 = or(_issue_entry_T_98, _issue_entry_T_92) node _issue_entry_T_100 = or(_issue_entry_T_99, _issue_entry_T_93) node _issue_entry_T_101 = or(_issue_entry_T_100, _issue_entry_T_94) node _issue_entry_T_102 = or(_issue_entry_T_101, _issue_entry_T_95) node _issue_entry_T_103 = or(_issue_entry_T_102, _issue_entry_T_96) node _issue_entry_T_104 = or(_issue_entry_T_103, _issue_entry_T_97) wire _issue_entry_WIRE_9 : UInt<1> connect _issue_entry_WIRE_9, _issue_entry_T_104 connect _issue_entry_WIRE_7[1], _issue_entry_WIRE_9 node _issue_entry_T_105 = mux(issue_sel_0, entries_ld[0].bits.deps_ex[2], UInt<1>(0h0)) node _issue_entry_T_106 = mux(issue_sel_1, entries_ld[1].bits.deps_ex[2], UInt<1>(0h0)) node _issue_entry_T_107 = mux(issue_sel_2, entries_ld[2].bits.deps_ex[2], UInt<1>(0h0)) node _issue_entry_T_108 = mux(issue_sel_3, entries_ld[3].bits.deps_ex[2], UInt<1>(0h0)) node _issue_entry_T_109 = mux(issue_sel_4, entries_ld[4].bits.deps_ex[2], UInt<1>(0h0)) node _issue_entry_T_110 = mux(issue_sel_5, entries_ld[5].bits.deps_ex[2], UInt<1>(0h0)) node _issue_entry_T_111 = mux(issue_sel_6, entries_ld[6].bits.deps_ex[2], UInt<1>(0h0)) node _issue_entry_T_112 = mux(issue_sel_7, entries_ld[7].bits.deps_ex[2], UInt<1>(0h0)) node _issue_entry_T_113 = or(_issue_entry_T_105, _issue_entry_T_106) node _issue_entry_T_114 = or(_issue_entry_T_113, _issue_entry_T_107) node _issue_entry_T_115 = or(_issue_entry_T_114, _issue_entry_T_108) node _issue_entry_T_116 = or(_issue_entry_T_115, _issue_entry_T_109) node _issue_entry_T_117 = or(_issue_entry_T_116, _issue_entry_T_110) node _issue_entry_T_118 = or(_issue_entry_T_117, _issue_entry_T_111) node _issue_entry_T_119 = or(_issue_entry_T_118, _issue_entry_T_112) wire _issue_entry_WIRE_10 : UInt<1> connect _issue_entry_WIRE_10, _issue_entry_T_119 connect _issue_entry_WIRE_7[2], _issue_entry_WIRE_10 node _issue_entry_T_120 = mux(issue_sel_0, entries_ld[0].bits.deps_ex[3], UInt<1>(0h0)) node _issue_entry_T_121 = mux(issue_sel_1, entries_ld[1].bits.deps_ex[3], UInt<1>(0h0)) node _issue_entry_T_122 = mux(issue_sel_2, entries_ld[2].bits.deps_ex[3], UInt<1>(0h0)) node _issue_entry_T_123 = mux(issue_sel_3, entries_ld[3].bits.deps_ex[3], UInt<1>(0h0)) node _issue_entry_T_124 = mux(issue_sel_4, entries_ld[4].bits.deps_ex[3], UInt<1>(0h0)) node _issue_entry_T_125 = mux(issue_sel_5, entries_ld[5].bits.deps_ex[3], UInt<1>(0h0)) node _issue_entry_T_126 = mux(issue_sel_6, entries_ld[6].bits.deps_ex[3], UInt<1>(0h0)) node _issue_entry_T_127 = mux(issue_sel_7, entries_ld[7].bits.deps_ex[3], UInt<1>(0h0)) node _issue_entry_T_128 = or(_issue_entry_T_120, _issue_entry_T_121) node _issue_entry_T_129 = or(_issue_entry_T_128, _issue_entry_T_122) node _issue_entry_T_130 = or(_issue_entry_T_129, _issue_entry_T_123) node _issue_entry_T_131 = or(_issue_entry_T_130, _issue_entry_T_124) node _issue_entry_T_132 = or(_issue_entry_T_131, _issue_entry_T_125) node _issue_entry_T_133 = or(_issue_entry_T_132, _issue_entry_T_126) node _issue_entry_T_134 = or(_issue_entry_T_133, _issue_entry_T_127) wire _issue_entry_WIRE_11 : UInt<1> connect _issue_entry_WIRE_11, _issue_entry_T_134 connect _issue_entry_WIRE_7[3], _issue_entry_WIRE_11 node _issue_entry_T_135 = mux(issue_sel_0, entries_ld[0].bits.deps_ex[4], UInt<1>(0h0)) node _issue_entry_T_136 = mux(issue_sel_1, entries_ld[1].bits.deps_ex[4], UInt<1>(0h0)) node _issue_entry_T_137 = mux(issue_sel_2, entries_ld[2].bits.deps_ex[4], UInt<1>(0h0)) node _issue_entry_T_138 = mux(issue_sel_3, entries_ld[3].bits.deps_ex[4], UInt<1>(0h0)) node _issue_entry_T_139 = mux(issue_sel_4, entries_ld[4].bits.deps_ex[4], UInt<1>(0h0)) node _issue_entry_T_140 = mux(issue_sel_5, entries_ld[5].bits.deps_ex[4], UInt<1>(0h0)) node _issue_entry_T_141 = mux(issue_sel_6, entries_ld[6].bits.deps_ex[4], UInt<1>(0h0)) node _issue_entry_T_142 = mux(issue_sel_7, entries_ld[7].bits.deps_ex[4], UInt<1>(0h0)) node _issue_entry_T_143 = or(_issue_entry_T_135, _issue_entry_T_136) node _issue_entry_T_144 = or(_issue_entry_T_143, _issue_entry_T_137) node _issue_entry_T_145 = or(_issue_entry_T_144, _issue_entry_T_138) node _issue_entry_T_146 = or(_issue_entry_T_145, _issue_entry_T_139) node _issue_entry_T_147 = or(_issue_entry_T_146, _issue_entry_T_140) node _issue_entry_T_148 = or(_issue_entry_T_147, _issue_entry_T_141) node _issue_entry_T_149 = or(_issue_entry_T_148, _issue_entry_T_142) wire _issue_entry_WIRE_12 : UInt<1> connect _issue_entry_WIRE_12, _issue_entry_T_149 connect _issue_entry_WIRE_7[4], _issue_entry_WIRE_12 node _issue_entry_T_150 = mux(issue_sel_0, entries_ld[0].bits.deps_ex[5], UInt<1>(0h0)) node _issue_entry_T_151 = mux(issue_sel_1, entries_ld[1].bits.deps_ex[5], UInt<1>(0h0)) node _issue_entry_T_152 = mux(issue_sel_2, entries_ld[2].bits.deps_ex[5], UInt<1>(0h0)) node _issue_entry_T_153 = mux(issue_sel_3, entries_ld[3].bits.deps_ex[5], UInt<1>(0h0)) node _issue_entry_T_154 = mux(issue_sel_4, entries_ld[4].bits.deps_ex[5], UInt<1>(0h0)) node _issue_entry_T_155 = mux(issue_sel_5, entries_ld[5].bits.deps_ex[5], UInt<1>(0h0)) node _issue_entry_T_156 = mux(issue_sel_6, entries_ld[6].bits.deps_ex[5], UInt<1>(0h0)) node _issue_entry_T_157 = mux(issue_sel_7, entries_ld[7].bits.deps_ex[5], UInt<1>(0h0)) node _issue_entry_T_158 = or(_issue_entry_T_150, _issue_entry_T_151) node _issue_entry_T_159 = or(_issue_entry_T_158, _issue_entry_T_152) node _issue_entry_T_160 = or(_issue_entry_T_159, _issue_entry_T_153) node _issue_entry_T_161 = or(_issue_entry_T_160, _issue_entry_T_154) node _issue_entry_T_162 = or(_issue_entry_T_161, _issue_entry_T_155) node _issue_entry_T_163 = or(_issue_entry_T_162, _issue_entry_T_156) node _issue_entry_T_164 = or(_issue_entry_T_163, _issue_entry_T_157) wire _issue_entry_WIRE_13 : UInt<1> connect _issue_entry_WIRE_13, _issue_entry_T_164 connect _issue_entry_WIRE_7[5], _issue_entry_WIRE_13 node _issue_entry_T_165 = mux(issue_sel_0, entries_ld[0].bits.deps_ex[6], UInt<1>(0h0)) node _issue_entry_T_166 = mux(issue_sel_1, entries_ld[1].bits.deps_ex[6], UInt<1>(0h0)) node _issue_entry_T_167 = mux(issue_sel_2, entries_ld[2].bits.deps_ex[6], UInt<1>(0h0)) node _issue_entry_T_168 = mux(issue_sel_3, entries_ld[3].bits.deps_ex[6], UInt<1>(0h0)) node _issue_entry_T_169 = mux(issue_sel_4, entries_ld[4].bits.deps_ex[6], UInt<1>(0h0)) node _issue_entry_T_170 = mux(issue_sel_5, entries_ld[5].bits.deps_ex[6], UInt<1>(0h0)) node _issue_entry_T_171 = mux(issue_sel_6, entries_ld[6].bits.deps_ex[6], UInt<1>(0h0)) node _issue_entry_T_172 = mux(issue_sel_7, entries_ld[7].bits.deps_ex[6], UInt<1>(0h0)) node _issue_entry_T_173 = or(_issue_entry_T_165, _issue_entry_T_166) node _issue_entry_T_174 = or(_issue_entry_T_173, _issue_entry_T_167) node _issue_entry_T_175 = or(_issue_entry_T_174, _issue_entry_T_168) node _issue_entry_T_176 = or(_issue_entry_T_175, _issue_entry_T_169) node _issue_entry_T_177 = or(_issue_entry_T_176, _issue_entry_T_170) node _issue_entry_T_178 = or(_issue_entry_T_177, _issue_entry_T_171) node _issue_entry_T_179 = or(_issue_entry_T_178, _issue_entry_T_172) wire _issue_entry_WIRE_14 : UInt<1> connect _issue_entry_WIRE_14, _issue_entry_T_179 connect _issue_entry_WIRE_7[6], _issue_entry_WIRE_14 node _issue_entry_T_180 = mux(issue_sel_0, entries_ld[0].bits.deps_ex[7], UInt<1>(0h0)) node _issue_entry_T_181 = mux(issue_sel_1, entries_ld[1].bits.deps_ex[7], UInt<1>(0h0)) node _issue_entry_T_182 = mux(issue_sel_2, entries_ld[2].bits.deps_ex[7], UInt<1>(0h0)) node _issue_entry_T_183 = mux(issue_sel_3, entries_ld[3].bits.deps_ex[7], UInt<1>(0h0)) node _issue_entry_T_184 = mux(issue_sel_4, entries_ld[4].bits.deps_ex[7], UInt<1>(0h0)) node _issue_entry_T_185 = mux(issue_sel_5, entries_ld[5].bits.deps_ex[7], UInt<1>(0h0)) node _issue_entry_T_186 = mux(issue_sel_6, entries_ld[6].bits.deps_ex[7], UInt<1>(0h0)) node _issue_entry_T_187 = mux(issue_sel_7, entries_ld[7].bits.deps_ex[7], UInt<1>(0h0)) node _issue_entry_T_188 = or(_issue_entry_T_180, _issue_entry_T_181) node _issue_entry_T_189 = or(_issue_entry_T_188, _issue_entry_T_182) node _issue_entry_T_190 = or(_issue_entry_T_189, _issue_entry_T_183) node _issue_entry_T_191 = or(_issue_entry_T_190, _issue_entry_T_184) node _issue_entry_T_192 = or(_issue_entry_T_191, _issue_entry_T_185) node _issue_entry_T_193 = or(_issue_entry_T_192, _issue_entry_T_186) node _issue_entry_T_194 = or(_issue_entry_T_193, _issue_entry_T_187) wire _issue_entry_WIRE_15 : UInt<1> connect _issue_entry_WIRE_15, _issue_entry_T_194 connect _issue_entry_WIRE_7[7], _issue_entry_WIRE_15 node _issue_entry_T_195 = mux(issue_sel_0, entries_ld[0].bits.deps_ex[8], UInt<1>(0h0)) node _issue_entry_T_196 = mux(issue_sel_1, entries_ld[1].bits.deps_ex[8], UInt<1>(0h0)) node _issue_entry_T_197 = mux(issue_sel_2, entries_ld[2].bits.deps_ex[8], UInt<1>(0h0)) node _issue_entry_T_198 = mux(issue_sel_3, entries_ld[3].bits.deps_ex[8], UInt<1>(0h0)) node _issue_entry_T_199 = mux(issue_sel_4, entries_ld[4].bits.deps_ex[8], UInt<1>(0h0)) node _issue_entry_T_200 = mux(issue_sel_5, entries_ld[5].bits.deps_ex[8], UInt<1>(0h0)) node _issue_entry_T_201 = mux(issue_sel_6, entries_ld[6].bits.deps_ex[8], UInt<1>(0h0)) node _issue_entry_T_202 = mux(issue_sel_7, entries_ld[7].bits.deps_ex[8], UInt<1>(0h0)) node _issue_entry_T_203 = or(_issue_entry_T_195, _issue_entry_T_196) node _issue_entry_T_204 = or(_issue_entry_T_203, _issue_entry_T_197) node _issue_entry_T_205 = or(_issue_entry_T_204, _issue_entry_T_198) node _issue_entry_T_206 = or(_issue_entry_T_205, _issue_entry_T_199) node _issue_entry_T_207 = or(_issue_entry_T_206, _issue_entry_T_200) node _issue_entry_T_208 = or(_issue_entry_T_207, _issue_entry_T_201) node _issue_entry_T_209 = or(_issue_entry_T_208, _issue_entry_T_202) wire _issue_entry_WIRE_16 : UInt<1> connect _issue_entry_WIRE_16, _issue_entry_T_209 connect _issue_entry_WIRE_7[8], _issue_entry_WIRE_16 node _issue_entry_T_210 = mux(issue_sel_0, entries_ld[0].bits.deps_ex[9], UInt<1>(0h0)) node _issue_entry_T_211 = mux(issue_sel_1, entries_ld[1].bits.deps_ex[9], UInt<1>(0h0)) node _issue_entry_T_212 = mux(issue_sel_2, entries_ld[2].bits.deps_ex[9], UInt<1>(0h0)) node _issue_entry_T_213 = mux(issue_sel_3, entries_ld[3].bits.deps_ex[9], UInt<1>(0h0)) node _issue_entry_T_214 = mux(issue_sel_4, entries_ld[4].bits.deps_ex[9], UInt<1>(0h0)) node _issue_entry_T_215 = mux(issue_sel_5, entries_ld[5].bits.deps_ex[9], UInt<1>(0h0)) node _issue_entry_T_216 = mux(issue_sel_6, entries_ld[6].bits.deps_ex[9], UInt<1>(0h0)) node _issue_entry_T_217 = mux(issue_sel_7, entries_ld[7].bits.deps_ex[9], UInt<1>(0h0)) node _issue_entry_T_218 = or(_issue_entry_T_210, _issue_entry_T_211) node _issue_entry_T_219 = or(_issue_entry_T_218, _issue_entry_T_212) node _issue_entry_T_220 = or(_issue_entry_T_219, _issue_entry_T_213) node _issue_entry_T_221 = or(_issue_entry_T_220, _issue_entry_T_214) node _issue_entry_T_222 = or(_issue_entry_T_221, _issue_entry_T_215) node _issue_entry_T_223 = or(_issue_entry_T_222, _issue_entry_T_216) node _issue_entry_T_224 = or(_issue_entry_T_223, _issue_entry_T_217) wire _issue_entry_WIRE_17 : UInt<1> connect _issue_entry_WIRE_17, _issue_entry_T_224 connect _issue_entry_WIRE_7[9], _issue_entry_WIRE_17 node _issue_entry_T_225 = mux(issue_sel_0, entries_ld[0].bits.deps_ex[10], UInt<1>(0h0)) node _issue_entry_T_226 = mux(issue_sel_1, entries_ld[1].bits.deps_ex[10], UInt<1>(0h0)) node _issue_entry_T_227 = mux(issue_sel_2, entries_ld[2].bits.deps_ex[10], UInt<1>(0h0)) node _issue_entry_T_228 = mux(issue_sel_3, entries_ld[3].bits.deps_ex[10], UInt<1>(0h0)) node _issue_entry_T_229 = mux(issue_sel_4, entries_ld[4].bits.deps_ex[10], UInt<1>(0h0)) node _issue_entry_T_230 = mux(issue_sel_5, entries_ld[5].bits.deps_ex[10], UInt<1>(0h0)) node _issue_entry_T_231 = mux(issue_sel_6, entries_ld[6].bits.deps_ex[10], UInt<1>(0h0)) node _issue_entry_T_232 = mux(issue_sel_7, entries_ld[7].bits.deps_ex[10], UInt<1>(0h0)) node _issue_entry_T_233 = or(_issue_entry_T_225, _issue_entry_T_226) node _issue_entry_T_234 = or(_issue_entry_T_233, _issue_entry_T_227) node _issue_entry_T_235 = or(_issue_entry_T_234, _issue_entry_T_228) node _issue_entry_T_236 = or(_issue_entry_T_235, _issue_entry_T_229) node _issue_entry_T_237 = or(_issue_entry_T_236, _issue_entry_T_230) node _issue_entry_T_238 = or(_issue_entry_T_237, _issue_entry_T_231) node _issue_entry_T_239 = or(_issue_entry_T_238, _issue_entry_T_232) wire _issue_entry_WIRE_18 : UInt<1> connect _issue_entry_WIRE_18, _issue_entry_T_239 connect _issue_entry_WIRE_7[10], _issue_entry_WIRE_18 node _issue_entry_T_240 = mux(issue_sel_0, entries_ld[0].bits.deps_ex[11], UInt<1>(0h0)) node _issue_entry_T_241 = mux(issue_sel_1, entries_ld[1].bits.deps_ex[11], UInt<1>(0h0)) node _issue_entry_T_242 = mux(issue_sel_2, entries_ld[2].bits.deps_ex[11], UInt<1>(0h0)) node _issue_entry_T_243 = mux(issue_sel_3, entries_ld[3].bits.deps_ex[11], UInt<1>(0h0)) node _issue_entry_T_244 = mux(issue_sel_4, entries_ld[4].bits.deps_ex[11], UInt<1>(0h0)) node _issue_entry_T_245 = mux(issue_sel_5, entries_ld[5].bits.deps_ex[11], UInt<1>(0h0)) node _issue_entry_T_246 = mux(issue_sel_6, entries_ld[6].bits.deps_ex[11], UInt<1>(0h0)) node _issue_entry_T_247 = mux(issue_sel_7, entries_ld[7].bits.deps_ex[11], UInt<1>(0h0)) node _issue_entry_T_248 = or(_issue_entry_T_240, _issue_entry_T_241) node _issue_entry_T_249 = or(_issue_entry_T_248, _issue_entry_T_242) node _issue_entry_T_250 = or(_issue_entry_T_249, _issue_entry_T_243) node _issue_entry_T_251 = or(_issue_entry_T_250, _issue_entry_T_244) node _issue_entry_T_252 = or(_issue_entry_T_251, _issue_entry_T_245) node _issue_entry_T_253 = or(_issue_entry_T_252, _issue_entry_T_246) node _issue_entry_T_254 = or(_issue_entry_T_253, _issue_entry_T_247) wire _issue_entry_WIRE_19 : UInt<1> connect _issue_entry_WIRE_19, _issue_entry_T_254 connect _issue_entry_WIRE_7[11], _issue_entry_WIRE_19 node _issue_entry_T_255 = mux(issue_sel_0, entries_ld[0].bits.deps_ex[12], UInt<1>(0h0)) node _issue_entry_T_256 = mux(issue_sel_1, entries_ld[1].bits.deps_ex[12], UInt<1>(0h0)) node _issue_entry_T_257 = mux(issue_sel_2, entries_ld[2].bits.deps_ex[12], UInt<1>(0h0)) node _issue_entry_T_258 = mux(issue_sel_3, entries_ld[3].bits.deps_ex[12], UInt<1>(0h0)) node _issue_entry_T_259 = mux(issue_sel_4, entries_ld[4].bits.deps_ex[12], UInt<1>(0h0)) node _issue_entry_T_260 = mux(issue_sel_5, entries_ld[5].bits.deps_ex[12], UInt<1>(0h0)) node _issue_entry_T_261 = mux(issue_sel_6, entries_ld[6].bits.deps_ex[12], UInt<1>(0h0)) node _issue_entry_T_262 = mux(issue_sel_7, entries_ld[7].bits.deps_ex[12], UInt<1>(0h0)) node _issue_entry_T_263 = or(_issue_entry_T_255, _issue_entry_T_256) node _issue_entry_T_264 = or(_issue_entry_T_263, _issue_entry_T_257) node _issue_entry_T_265 = or(_issue_entry_T_264, _issue_entry_T_258) node _issue_entry_T_266 = or(_issue_entry_T_265, _issue_entry_T_259) node _issue_entry_T_267 = or(_issue_entry_T_266, _issue_entry_T_260) node _issue_entry_T_268 = or(_issue_entry_T_267, _issue_entry_T_261) node _issue_entry_T_269 = or(_issue_entry_T_268, _issue_entry_T_262) wire _issue_entry_WIRE_20 : UInt<1> connect _issue_entry_WIRE_20, _issue_entry_T_269 connect _issue_entry_WIRE_7[12], _issue_entry_WIRE_20 node _issue_entry_T_270 = mux(issue_sel_0, entries_ld[0].bits.deps_ex[13], UInt<1>(0h0)) node _issue_entry_T_271 = mux(issue_sel_1, entries_ld[1].bits.deps_ex[13], UInt<1>(0h0)) node _issue_entry_T_272 = mux(issue_sel_2, entries_ld[2].bits.deps_ex[13], UInt<1>(0h0)) node _issue_entry_T_273 = mux(issue_sel_3, entries_ld[3].bits.deps_ex[13], UInt<1>(0h0)) node _issue_entry_T_274 = mux(issue_sel_4, entries_ld[4].bits.deps_ex[13], UInt<1>(0h0)) node _issue_entry_T_275 = mux(issue_sel_5, entries_ld[5].bits.deps_ex[13], UInt<1>(0h0)) node _issue_entry_T_276 = mux(issue_sel_6, entries_ld[6].bits.deps_ex[13], UInt<1>(0h0)) node _issue_entry_T_277 = mux(issue_sel_7, entries_ld[7].bits.deps_ex[13], UInt<1>(0h0)) node _issue_entry_T_278 = or(_issue_entry_T_270, _issue_entry_T_271) node _issue_entry_T_279 = or(_issue_entry_T_278, _issue_entry_T_272) node _issue_entry_T_280 = or(_issue_entry_T_279, _issue_entry_T_273) node _issue_entry_T_281 = or(_issue_entry_T_280, _issue_entry_T_274) node _issue_entry_T_282 = or(_issue_entry_T_281, _issue_entry_T_275) node _issue_entry_T_283 = or(_issue_entry_T_282, _issue_entry_T_276) node _issue_entry_T_284 = or(_issue_entry_T_283, _issue_entry_T_277) wire _issue_entry_WIRE_21 : UInt<1> connect _issue_entry_WIRE_21, _issue_entry_T_284 connect _issue_entry_WIRE_7[13], _issue_entry_WIRE_21 node _issue_entry_T_285 = mux(issue_sel_0, entries_ld[0].bits.deps_ex[14], UInt<1>(0h0)) node _issue_entry_T_286 = mux(issue_sel_1, entries_ld[1].bits.deps_ex[14], UInt<1>(0h0)) node _issue_entry_T_287 = mux(issue_sel_2, entries_ld[2].bits.deps_ex[14], UInt<1>(0h0)) node _issue_entry_T_288 = mux(issue_sel_3, entries_ld[3].bits.deps_ex[14], UInt<1>(0h0)) node _issue_entry_T_289 = mux(issue_sel_4, entries_ld[4].bits.deps_ex[14], UInt<1>(0h0)) node _issue_entry_T_290 = mux(issue_sel_5, entries_ld[5].bits.deps_ex[14], UInt<1>(0h0)) node _issue_entry_T_291 = mux(issue_sel_6, entries_ld[6].bits.deps_ex[14], UInt<1>(0h0)) node _issue_entry_T_292 = mux(issue_sel_7, entries_ld[7].bits.deps_ex[14], UInt<1>(0h0)) node _issue_entry_T_293 = or(_issue_entry_T_285, _issue_entry_T_286) node _issue_entry_T_294 = or(_issue_entry_T_293, _issue_entry_T_287) node _issue_entry_T_295 = or(_issue_entry_T_294, _issue_entry_T_288) node _issue_entry_T_296 = or(_issue_entry_T_295, _issue_entry_T_289) node _issue_entry_T_297 = or(_issue_entry_T_296, _issue_entry_T_290) node _issue_entry_T_298 = or(_issue_entry_T_297, _issue_entry_T_291) node _issue_entry_T_299 = or(_issue_entry_T_298, _issue_entry_T_292) wire _issue_entry_WIRE_22 : UInt<1> connect _issue_entry_WIRE_22, _issue_entry_T_299 connect _issue_entry_WIRE_7[14], _issue_entry_WIRE_22 node _issue_entry_T_300 = mux(issue_sel_0, entries_ld[0].bits.deps_ex[15], UInt<1>(0h0)) node _issue_entry_T_301 = mux(issue_sel_1, entries_ld[1].bits.deps_ex[15], UInt<1>(0h0)) node _issue_entry_T_302 = mux(issue_sel_2, entries_ld[2].bits.deps_ex[15], UInt<1>(0h0)) node _issue_entry_T_303 = mux(issue_sel_3, entries_ld[3].bits.deps_ex[15], UInt<1>(0h0)) node _issue_entry_T_304 = mux(issue_sel_4, entries_ld[4].bits.deps_ex[15], UInt<1>(0h0)) node _issue_entry_T_305 = mux(issue_sel_5, entries_ld[5].bits.deps_ex[15], UInt<1>(0h0)) node _issue_entry_T_306 = mux(issue_sel_6, entries_ld[6].bits.deps_ex[15], UInt<1>(0h0)) node _issue_entry_T_307 = mux(issue_sel_7, entries_ld[7].bits.deps_ex[15], UInt<1>(0h0)) node _issue_entry_T_308 = or(_issue_entry_T_300, _issue_entry_T_301) node _issue_entry_T_309 = or(_issue_entry_T_308, _issue_entry_T_302) node _issue_entry_T_310 = or(_issue_entry_T_309, _issue_entry_T_303) node _issue_entry_T_311 = or(_issue_entry_T_310, _issue_entry_T_304) node _issue_entry_T_312 = or(_issue_entry_T_311, _issue_entry_T_305) node _issue_entry_T_313 = or(_issue_entry_T_312, _issue_entry_T_306) node _issue_entry_T_314 = or(_issue_entry_T_313, _issue_entry_T_307) wire _issue_entry_WIRE_23 : UInt<1> connect _issue_entry_WIRE_23, _issue_entry_T_314 connect _issue_entry_WIRE_7[15], _issue_entry_WIRE_23 connect _issue_entry_WIRE.deps_ex, _issue_entry_WIRE_7 wire _issue_entry_WIRE_24 : UInt<1>[8] node _issue_entry_T_315 = mux(issue_sel_0, entries_ld[0].bits.deps_ld[0], UInt<1>(0h0)) node _issue_entry_T_316 = mux(issue_sel_1, entries_ld[1].bits.deps_ld[0], UInt<1>(0h0)) node _issue_entry_T_317 = mux(issue_sel_2, entries_ld[2].bits.deps_ld[0], UInt<1>(0h0)) node _issue_entry_T_318 = mux(issue_sel_3, entries_ld[3].bits.deps_ld[0], UInt<1>(0h0)) node _issue_entry_T_319 = mux(issue_sel_4, entries_ld[4].bits.deps_ld[0], UInt<1>(0h0)) node _issue_entry_T_320 = mux(issue_sel_5, entries_ld[5].bits.deps_ld[0], UInt<1>(0h0)) node _issue_entry_T_321 = mux(issue_sel_6, entries_ld[6].bits.deps_ld[0], UInt<1>(0h0)) node _issue_entry_T_322 = mux(issue_sel_7, entries_ld[7].bits.deps_ld[0], UInt<1>(0h0)) node _issue_entry_T_323 = or(_issue_entry_T_315, _issue_entry_T_316) node _issue_entry_T_324 = or(_issue_entry_T_323, _issue_entry_T_317) node _issue_entry_T_325 = or(_issue_entry_T_324, _issue_entry_T_318) node _issue_entry_T_326 = or(_issue_entry_T_325, _issue_entry_T_319) node _issue_entry_T_327 = or(_issue_entry_T_326, _issue_entry_T_320) node _issue_entry_T_328 = or(_issue_entry_T_327, _issue_entry_T_321) node _issue_entry_T_329 = or(_issue_entry_T_328, _issue_entry_T_322) wire _issue_entry_WIRE_25 : UInt<1> connect _issue_entry_WIRE_25, _issue_entry_T_329 connect _issue_entry_WIRE_24[0], _issue_entry_WIRE_25 node _issue_entry_T_330 = mux(issue_sel_0, entries_ld[0].bits.deps_ld[1], UInt<1>(0h0)) node _issue_entry_T_331 = mux(issue_sel_1, entries_ld[1].bits.deps_ld[1], UInt<1>(0h0)) node _issue_entry_T_332 = mux(issue_sel_2, entries_ld[2].bits.deps_ld[1], UInt<1>(0h0)) node _issue_entry_T_333 = mux(issue_sel_3, entries_ld[3].bits.deps_ld[1], UInt<1>(0h0)) node _issue_entry_T_334 = mux(issue_sel_4, entries_ld[4].bits.deps_ld[1], UInt<1>(0h0)) node _issue_entry_T_335 = mux(issue_sel_5, entries_ld[5].bits.deps_ld[1], UInt<1>(0h0)) node _issue_entry_T_336 = mux(issue_sel_6, entries_ld[6].bits.deps_ld[1], UInt<1>(0h0)) node _issue_entry_T_337 = mux(issue_sel_7, entries_ld[7].bits.deps_ld[1], UInt<1>(0h0)) node _issue_entry_T_338 = or(_issue_entry_T_330, _issue_entry_T_331) node _issue_entry_T_339 = or(_issue_entry_T_338, _issue_entry_T_332) node _issue_entry_T_340 = or(_issue_entry_T_339, _issue_entry_T_333) node _issue_entry_T_341 = or(_issue_entry_T_340, _issue_entry_T_334) node _issue_entry_T_342 = or(_issue_entry_T_341, _issue_entry_T_335) node _issue_entry_T_343 = or(_issue_entry_T_342, _issue_entry_T_336) node _issue_entry_T_344 = or(_issue_entry_T_343, _issue_entry_T_337) wire _issue_entry_WIRE_26 : UInt<1> connect _issue_entry_WIRE_26, _issue_entry_T_344 connect _issue_entry_WIRE_24[1], _issue_entry_WIRE_26 node _issue_entry_T_345 = mux(issue_sel_0, entries_ld[0].bits.deps_ld[2], UInt<1>(0h0)) node _issue_entry_T_346 = mux(issue_sel_1, entries_ld[1].bits.deps_ld[2], UInt<1>(0h0)) node _issue_entry_T_347 = mux(issue_sel_2, entries_ld[2].bits.deps_ld[2], UInt<1>(0h0)) node _issue_entry_T_348 = mux(issue_sel_3, entries_ld[3].bits.deps_ld[2], UInt<1>(0h0)) node _issue_entry_T_349 = mux(issue_sel_4, entries_ld[4].bits.deps_ld[2], UInt<1>(0h0)) node _issue_entry_T_350 = mux(issue_sel_5, entries_ld[5].bits.deps_ld[2], UInt<1>(0h0)) node _issue_entry_T_351 = mux(issue_sel_6, entries_ld[6].bits.deps_ld[2], UInt<1>(0h0)) node _issue_entry_T_352 = mux(issue_sel_7, entries_ld[7].bits.deps_ld[2], UInt<1>(0h0)) node _issue_entry_T_353 = or(_issue_entry_T_345, _issue_entry_T_346) node _issue_entry_T_354 = or(_issue_entry_T_353, _issue_entry_T_347) node _issue_entry_T_355 = or(_issue_entry_T_354, _issue_entry_T_348) node _issue_entry_T_356 = or(_issue_entry_T_355, _issue_entry_T_349) node _issue_entry_T_357 = or(_issue_entry_T_356, _issue_entry_T_350) node _issue_entry_T_358 = or(_issue_entry_T_357, _issue_entry_T_351) node _issue_entry_T_359 = or(_issue_entry_T_358, _issue_entry_T_352) wire _issue_entry_WIRE_27 : UInt<1> connect _issue_entry_WIRE_27, _issue_entry_T_359 connect _issue_entry_WIRE_24[2], _issue_entry_WIRE_27 node _issue_entry_T_360 = mux(issue_sel_0, entries_ld[0].bits.deps_ld[3], UInt<1>(0h0)) node _issue_entry_T_361 = mux(issue_sel_1, entries_ld[1].bits.deps_ld[3], UInt<1>(0h0)) node _issue_entry_T_362 = mux(issue_sel_2, entries_ld[2].bits.deps_ld[3], UInt<1>(0h0)) node _issue_entry_T_363 = mux(issue_sel_3, entries_ld[3].bits.deps_ld[3], UInt<1>(0h0)) node _issue_entry_T_364 = mux(issue_sel_4, entries_ld[4].bits.deps_ld[3], UInt<1>(0h0)) node _issue_entry_T_365 = mux(issue_sel_5, entries_ld[5].bits.deps_ld[3], UInt<1>(0h0)) node _issue_entry_T_366 = mux(issue_sel_6, entries_ld[6].bits.deps_ld[3], UInt<1>(0h0)) node _issue_entry_T_367 = mux(issue_sel_7, entries_ld[7].bits.deps_ld[3], UInt<1>(0h0)) node _issue_entry_T_368 = or(_issue_entry_T_360, _issue_entry_T_361) node _issue_entry_T_369 = or(_issue_entry_T_368, _issue_entry_T_362) node _issue_entry_T_370 = or(_issue_entry_T_369, _issue_entry_T_363) node _issue_entry_T_371 = or(_issue_entry_T_370, _issue_entry_T_364) node _issue_entry_T_372 = or(_issue_entry_T_371, _issue_entry_T_365) node _issue_entry_T_373 = or(_issue_entry_T_372, _issue_entry_T_366) node _issue_entry_T_374 = or(_issue_entry_T_373, _issue_entry_T_367) wire _issue_entry_WIRE_28 : UInt<1> connect _issue_entry_WIRE_28, _issue_entry_T_374 connect _issue_entry_WIRE_24[3], _issue_entry_WIRE_28 node _issue_entry_T_375 = mux(issue_sel_0, entries_ld[0].bits.deps_ld[4], UInt<1>(0h0)) node _issue_entry_T_376 = mux(issue_sel_1, entries_ld[1].bits.deps_ld[4], UInt<1>(0h0)) node _issue_entry_T_377 = mux(issue_sel_2, entries_ld[2].bits.deps_ld[4], UInt<1>(0h0)) node _issue_entry_T_378 = mux(issue_sel_3, entries_ld[3].bits.deps_ld[4], UInt<1>(0h0)) node _issue_entry_T_379 = mux(issue_sel_4, entries_ld[4].bits.deps_ld[4], UInt<1>(0h0)) node _issue_entry_T_380 = mux(issue_sel_5, entries_ld[5].bits.deps_ld[4], UInt<1>(0h0)) node _issue_entry_T_381 = mux(issue_sel_6, entries_ld[6].bits.deps_ld[4], UInt<1>(0h0)) node _issue_entry_T_382 = mux(issue_sel_7, entries_ld[7].bits.deps_ld[4], UInt<1>(0h0)) node _issue_entry_T_383 = or(_issue_entry_T_375, _issue_entry_T_376) node _issue_entry_T_384 = or(_issue_entry_T_383, _issue_entry_T_377) node _issue_entry_T_385 = or(_issue_entry_T_384, _issue_entry_T_378) node _issue_entry_T_386 = or(_issue_entry_T_385, _issue_entry_T_379) node _issue_entry_T_387 = or(_issue_entry_T_386, _issue_entry_T_380) node _issue_entry_T_388 = or(_issue_entry_T_387, _issue_entry_T_381) node _issue_entry_T_389 = or(_issue_entry_T_388, _issue_entry_T_382) wire _issue_entry_WIRE_29 : UInt<1> connect _issue_entry_WIRE_29, _issue_entry_T_389 connect _issue_entry_WIRE_24[4], _issue_entry_WIRE_29 node _issue_entry_T_390 = mux(issue_sel_0, entries_ld[0].bits.deps_ld[5], UInt<1>(0h0)) node _issue_entry_T_391 = mux(issue_sel_1, entries_ld[1].bits.deps_ld[5], UInt<1>(0h0)) node _issue_entry_T_392 = mux(issue_sel_2, entries_ld[2].bits.deps_ld[5], UInt<1>(0h0)) node _issue_entry_T_393 = mux(issue_sel_3, entries_ld[3].bits.deps_ld[5], UInt<1>(0h0)) node _issue_entry_T_394 = mux(issue_sel_4, entries_ld[4].bits.deps_ld[5], UInt<1>(0h0)) node _issue_entry_T_395 = mux(issue_sel_5, entries_ld[5].bits.deps_ld[5], UInt<1>(0h0)) node _issue_entry_T_396 = mux(issue_sel_6, entries_ld[6].bits.deps_ld[5], UInt<1>(0h0)) node _issue_entry_T_397 = mux(issue_sel_7, entries_ld[7].bits.deps_ld[5], UInt<1>(0h0)) node _issue_entry_T_398 = or(_issue_entry_T_390, _issue_entry_T_391) node _issue_entry_T_399 = or(_issue_entry_T_398, _issue_entry_T_392) node _issue_entry_T_400 = or(_issue_entry_T_399, _issue_entry_T_393) node _issue_entry_T_401 = or(_issue_entry_T_400, _issue_entry_T_394) node _issue_entry_T_402 = or(_issue_entry_T_401, _issue_entry_T_395) node _issue_entry_T_403 = or(_issue_entry_T_402, _issue_entry_T_396) node _issue_entry_T_404 = or(_issue_entry_T_403, _issue_entry_T_397) wire _issue_entry_WIRE_30 : UInt<1> connect _issue_entry_WIRE_30, _issue_entry_T_404 connect _issue_entry_WIRE_24[5], _issue_entry_WIRE_30 node _issue_entry_T_405 = mux(issue_sel_0, entries_ld[0].bits.deps_ld[6], UInt<1>(0h0)) node _issue_entry_T_406 = mux(issue_sel_1, entries_ld[1].bits.deps_ld[6], UInt<1>(0h0)) node _issue_entry_T_407 = mux(issue_sel_2, entries_ld[2].bits.deps_ld[6], UInt<1>(0h0)) node _issue_entry_T_408 = mux(issue_sel_3, entries_ld[3].bits.deps_ld[6], UInt<1>(0h0)) node _issue_entry_T_409 = mux(issue_sel_4, entries_ld[4].bits.deps_ld[6], UInt<1>(0h0)) node _issue_entry_T_410 = mux(issue_sel_5, entries_ld[5].bits.deps_ld[6], UInt<1>(0h0)) node _issue_entry_T_411 = mux(issue_sel_6, entries_ld[6].bits.deps_ld[6], UInt<1>(0h0)) node _issue_entry_T_412 = mux(issue_sel_7, entries_ld[7].bits.deps_ld[6], UInt<1>(0h0)) node _issue_entry_T_413 = or(_issue_entry_T_405, _issue_entry_T_406) node _issue_entry_T_414 = or(_issue_entry_T_413, _issue_entry_T_407) node _issue_entry_T_415 = or(_issue_entry_T_414, _issue_entry_T_408) node _issue_entry_T_416 = or(_issue_entry_T_415, _issue_entry_T_409) node _issue_entry_T_417 = or(_issue_entry_T_416, _issue_entry_T_410) node _issue_entry_T_418 = or(_issue_entry_T_417, _issue_entry_T_411) node _issue_entry_T_419 = or(_issue_entry_T_418, _issue_entry_T_412) wire _issue_entry_WIRE_31 : UInt<1> connect _issue_entry_WIRE_31, _issue_entry_T_419 connect _issue_entry_WIRE_24[6], _issue_entry_WIRE_31 node _issue_entry_T_420 = mux(issue_sel_0, entries_ld[0].bits.deps_ld[7], UInt<1>(0h0)) node _issue_entry_T_421 = mux(issue_sel_1, entries_ld[1].bits.deps_ld[7], UInt<1>(0h0)) node _issue_entry_T_422 = mux(issue_sel_2, entries_ld[2].bits.deps_ld[7], UInt<1>(0h0)) node _issue_entry_T_423 = mux(issue_sel_3, entries_ld[3].bits.deps_ld[7], UInt<1>(0h0)) node _issue_entry_T_424 = mux(issue_sel_4, entries_ld[4].bits.deps_ld[7], UInt<1>(0h0)) node _issue_entry_T_425 = mux(issue_sel_5, entries_ld[5].bits.deps_ld[7], UInt<1>(0h0)) node _issue_entry_T_426 = mux(issue_sel_6, entries_ld[6].bits.deps_ld[7], UInt<1>(0h0)) node _issue_entry_T_427 = mux(issue_sel_7, entries_ld[7].bits.deps_ld[7], UInt<1>(0h0)) node _issue_entry_T_428 = or(_issue_entry_T_420, _issue_entry_T_421) node _issue_entry_T_429 = or(_issue_entry_T_428, _issue_entry_T_422) node _issue_entry_T_430 = or(_issue_entry_T_429, _issue_entry_T_423) node _issue_entry_T_431 = or(_issue_entry_T_430, _issue_entry_T_424) node _issue_entry_T_432 = or(_issue_entry_T_431, _issue_entry_T_425) node _issue_entry_T_433 = or(_issue_entry_T_432, _issue_entry_T_426) node _issue_entry_T_434 = or(_issue_entry_T_433, _issue_entry_T_427) wire _issue_entry_WIRE_32 : UInt<1> connect _issue_entry_WIRE_32, _issue_entry_T_434 connect _issue_entry_WIRE_24[7], _issue_entry_WIRE_32 connect _issue_entry_WIRE.deps_ld, _issue_entry_WIRE_24 wire _issue_entry_WIRE_33 : { cmd : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, rob_id : { valid : UInt<1>, bits : UInt<6>}, from_matmul_fsm : UInt<1>, from_conv_fsm : UInt<1>} node _issue_entry_T_435 = mux(issue_sel_0, entries_ld[0].bits.cmd.from_conv_fsm, UInt<1>(0h0)) node _issue_entry_T_436 = mux(issue_sel_1, entries_ld[1].bits.cmd.from_conv_fsm, UInt<1>(0h0)) node _issue_entry_T_437 = mux(issue_sel_2, entries_ld[2].bits.cmd.from_conv_fsm, UInt<1>(0h0)) node _issue_entry_T_438 = mux(issue_sel_3, entries_ld[3].bits.cmd.from_conv_fsm, UInt<1>(0h0)) node _issue_entry_T_439 = mux(issue_sel_4, entries_ld[4].bits.cmd.from_conv_fsm, UInt<1>(0h0)) node _issue_entry_T_440 = mux(issue_sel_5, entries_ld[5].bits.cmd.from_conv_fsm, UInt<1>(0h0)) node _issue_entry_T_441 = mux(issue_sel_6, entries_ld[6].bits.cmd.from_conv_fsm, UInt<1>(0h0)) node _issue_entry_T_442 = mux(issue_sel_7, entries_ld[7].bits.cmd.from_conv_fsm, UInt<1>(0h0)) node _issue_entry_T_443 = or(_issue_entry_T_435, _issue_entry_T_436) node _issue_entry_T_444 = or(_issue_entry_T_443, _issue_entry_T_437) node _issue_entry_T_445 = or(_issue_entry_T_444, _issue_entry_T_438) node _issue_entry_T_446 = or(_issue_entry_T_445, _issue_entry_T_439) node _issue_entry_T_447 = or(_issue_entry_T_446, _issue_entry_T_440) node _issue_entry_T_448 = or(_issue_entry_T_447, _issue_entry_T_441) node _issue_entry_T_449 = or(_issue_entry_T_448, _issue_entry_T_442) wire _issue_entry_WIRE_34 : UInt<1> connect _issue_entry_WIRE_34, _issue_entry_T_449 connect _issue_entry_WIRE_33.from_conv_fsm, _issue_entry_WIRE_34 node _issue_entry_T_450 = mux(issue_sel_0, entries_ld[0].bits.cmd.from_matmul_fsm, UInt<1>(0h0)) node _issue_entry_T_451 = mux(issue_sel_1, entries_ld[1].bits.cmd.from_matmul_fsm, UInt<1>(0h0)) node _issue_entry_T_452 = mux(issue_sel_2, entries_ld[2].bits.cmd.from_matmul_fsm, UInt<1>(0h0)) node _issue_entry_T_453 = mux(issue_sel_3, entries_ld[3].bits.cmd.from_matmul_fsm, UInt<1>(0h0)) node _issue_entry_T_454 = mux(issue_sel_4, entries_ld[4].bits.cmd.from_matmul_fsm, UInt<1>(0h0)) node _issue_entry_T_455 = mux(issue_sel_5, entries_ld[5].bits.cmd.from_matmul_fsm, UInt<1>(0h0)) node _issue_entry_T_456 = mux(issue_sel_6, entries_ld[6].bits.cmd.from_matmul_fsm, UInt<1>(0h0)) node _issue_entry_T_457 = mux(issue_sel_7, entries_ld[7].bits.cmd.from_matmul_fsm, UInt<1>(0h0)) node _issue_entry_T_458 = or(_issue_entry_T_450, _issue_entry_T_451) node _issue_entry_T_459 = or(_issue_entry_T_458, _issue_entry_T_452) node _issue_entry_T_460 = or(_issue_entry_T_459, _issue_entry_T_453) node _issue_entry_T_461 = or(_issue_entry_T_460, _issue_entry_T_454) node _issue_entry_T_462 = or(_issue_entry_T_461, _issue_entry_T_455) node _issue_entry_T_463 = or(_issue_entry_T_462, _issue_entry_T_456) node _issue_entry_T_464 = or(_issue_entry_T_463, _issue_entry_T_457) wire _issue_entry_WIRE_35 : UInt<1> connect _issue_entry_WIRE_35, _issue_entry_T_464 connect _issue_entry_WIRE_33.from_matmul_fsm, _issue_entry_WIRE_35 wire _issue_entry_WIRE_36 : { valid : UInt<1>, bits : UInt<6>} node _issue_entry_T_465 = mux(issue_sel_0, entries_ld[0].bits.cmd.rob_id.bits, UInt<1>(0h0)) node _issue_entry_T_466 = mux(issue_sel_1, entries_ld[1].bits.cmd.rob_id.bits, UInt<1>(0h0)) node _issue_entry_T_467 = mux(issue_sel_2, entries_ld[2].bits.cmd.rob_id.bits, UInt<1>(0h0)) node _issue_entry_T_468 = mux(issue_sel_3, entries_ld[3].bits.cmd.rob_id.bits, UInt<1>(0h0)) node _issue_entry_T_469 = mux(issue_sel_4, entries_ld[4].bits.cmd.rob_id.bits, UInt<1>(0h0)) node _issue_entry_T_470 = mux(issue_sel_5, entries_ld[5].bits.cmd.rob_id.bits, UInt<1>(0h0)) node _issue_entry_T_471 = mux(issue_sel_6, entries_ld[6].bits.cmd.rob_id.bits, UInt<1>(0h0)) node _issue_entry_T_472 = mux(issue_sel_7, entries_ld[7].bits.cmd.rob_id.bits, UInt<1>(0h0)) node _issue_entry_T_473 = or(_issue_entry_T_465, _issue_entry_T_466) node _issue_entry_T_474 = or(_issue_entry_T_473, _issue_entry_T_467) node _issue_entry_T_475 = or(_issue_entry_T_474, _issue_entry_T_468) node _issue_entry_T_476 = or(_issue_entry_T_475, _issue_entry_T_469) node _issue_entry_T_477 = or(_issue_entry_T_476, _issue_entry_T_470) node _issue_entry_T_478 = or(_issue_entry_T_477, _issue_entry_T_471) node _issue_entry_T_479 = or(_issue_entry_T_478, _issue_entry_T_472) wire _issue_entry_WIRE_37 : UInt<6> connect _issue_entry_WIRE_37, _issue_entry_T_479 connect _issue_entry_WIRE_36.bits, _issue_entry_WIRE_37 node _issue_entry_T_480 = mux(issue_sel_0, entries_ld[0].bits.cmd.rob_id.valid, UInt<1>(0h0)) node _issue_entry_T_481 = mux(issue_sel_1, entries_ld[1].bits.cmd.rob_id.valid, UInt<1>(0h0)) node _issue_entry_T_482 = mux(issue_sel_2, entries_ld[2].bits.cmd.rob_id.valid, UInt<1>(0h0)) node _issue_entry_T_483 = mux(issue_sel_3, entries_ld[3].bits.cmd.rob_id.valid, UInt<1>(0h0)) node _issue_entry_T_484 = mux(issue_sel_4, entries_ld[4].bits.cmd.rob_id.valid, UInt<1>(0h0)) node _issue_entry_T_485 = mux(issue_sel_5, entries_ld[5].bits.cmd.rob_id.valid, UInt<1>(0h0)) node _issue_entry_T_486 = mux(issue_sel_6, entries_ld[6].bits.cmd.rob_id.valid, UInt<1>(0h0)) node _issue_entry_T_487 = mux(issue_sel_7, entries_ld[7].bits.cmd.rob_id.valid, UInt<1>(0h0)) node _issue_entry_T_488 = or(_issue_entry_T_480, _issue_entry_T_481) node _issue_entry_T_489 = or(_issue_entry_T_488, _issue_entry_T_482) node _issue_entry_T_490 = or(_issue_entry_T_489, _issue_entry_T_483) node _issue_entry_T_491 = or(_issue_entry_T_490, _issue_entry_T_484) node _issue_entry_T_492 = or(_issue_entry_T_491, _issue_entry_T_485) node _issue_entry_T_493 = or(_issue_entry_T_492, _issue_entry_T_486) node _issue_entry_T_494 = or(_issue_entry_T_493, _issue_entry_T_487) wire _issue_entry_WIRE_38 : UInt<1> connect _issue_entry_WIRE_38, _issue_entry_T_494 connect _issue_entry_WIRE_36.valid, _issue_entry_WIRE_38 connect _issue_entry_WIRE_33.rob_id, _issue_entry_WIRE_36 wire _issue_entry_WIRE_39 : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}} wire _issue_entry_WIRE_40 : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} node _issue_entry_T_495 = mux(issue_sel_0, entries_ld[0].bits.cmd.cmd.status.uie, UInt<1>(0h0)) node _issue_entry_T_496 = mux(issue_sel_1, entries_ld[1].bits.cmd.cmd.status.uie, UInt<1>(0h0)) node _issue_entry_T_497 = mux(issue_sel_2, entries_ld[2].bits.cmd.cmd.status.uie, UInt<1>(0h0)) node _issue_entry_T_498 = mux(issue_sel_3, entries_ld[3].bits.cmd.cmd.status.uie, UInt<1>(0h0)) node _issue_entry_T_499 = mux(issue_sel_4, entries_ld[4].bits.cmd.cmd.status.uie, UInt<1>(0h0)) node _issue_entry_T_500 = mux(issue_sel_5, entries_ld[5].bits.cmd.cmd.status.uie, UInt<1>(0h0)) node _issue_entry_T_501 = mux(issue_sel_6, entries_ld[6].bits.cmd.cmd.status.uie, UInt<1>(0h0)) node _issue_entry_T_502 = mux(issue_sel_7, entries_ld[7].bits.cmd.cmd.status.uie, UInt<1>(0h0)) node _issue_entry_T_503 = or(_issue_entry_T_495, _issue_entry_T_496) node _issue_entry_T_504 = or(_issue_entry_T_503, _issue_entry_T_497) node _issue_entry_T_505 = or(_issue_entry_T_504, _issue_entry_T_498) node _issue_entry_T_506 = or(_issue_entry_T_505, _issue_entry_T_499) node _issue_entry_T_507 = or(_issue_entry_T_506, _issue_entry_T_500) node _issue_entry_T_508 = or(_issue_entry_T_507, _issue_entry_T_501) node _issue_entry_T_509 = or(_issue_entry_T_508, _issue_entry_T_502) wire _issue_entry_WIRE_41 : UInt<1> connect _issue_entry_WIRE_41, _issue_entry_T_509 connect _issue_entry_WIRE_40.uie, _issue_entry_WIRE_41 node _issue_entry_T_510 = mux(issue_sel_0, entries_ld[0].bits.cmd.cmd.status.sie, UInt<1>(0h0)) node _issue_entry_T_511 = mux(issue_sel_1, entries_ld[1].bits.cmd.cmd.status.sie, UInt<1>(0h0)) node _issue_entry_T_512 = mux(issue_sel_2, entries_ld[2].bits.cmd.cmd.status.sie, UInt<1>(0h0)) node _issue_entry_T_513 = mux(issue_sel_3, entries_ld[3].bits.cmd.cmd.status.sie, UInt<1>(0h0)) node _issue_entry_T_514 = mux(issue_sel_4, entries_ld[4].bits.cmd.cmd.status.sie, UInt<1>(0h0)) node _issue_entry_T_515 = mux(issue_sel_5, entries_ld[5].bits.cmd.cmd.status.sie, UInt<1>(0h0)) node _issue_entry_T_516 = mux(issue_sel_6, entries_ld[6].bits.cmd.cmd.status.sie, UInt<1>(0h0)) node _issue_entry_T_517 = mux(issue_sel_7, entries_ld[7].bits.cmd.cmd.status.sie, UInt<1>(0h0)) node _issue_entry_T_518 = or(_issue_entry_T_510, _issue_entry_T_511) node _issue_entry_T_519 = or(_issue_entry_T_518, _issue_entry_T_512) node _issue_entry_T_520 = or(_issue_entry_T_519, _issue_entry_T_513) node _issue_entry_T_521 = or(_issue_entry_T_520, _issue_entry_T_514) node _issue_entry_T_522 = or(_issue_entry_T_521, _issue_entry_T_515) node _issue_entry_T_523 = or(_issue_entry_T_522, _issue_entry_T_516) node _issue_entry_T_524 = or(_issue_entry_T_523, _issue_entry_T_517) wire _issue_entry_WIRE_42 : UInt<1> connect _issue_entry_WIRE_42, _issue_entry_T_524 connect _issue_entry_WIRE_40.sie, _issue_entry_WIRE_42 node _issue_entry_T_525 = mux(issue_sel_0, entries_ld[0].bits.cmd.cmd.status.hie, UInt<1>(0h0)) node _issue_entry_T_526 = mux(issue_sel_1, entries_ld[1].bits.cmd.cmd.status.hie, UInt<1>(0h0)) node _issue_entry_T_527 = mux(issue_sel_2, entries_ld[2].bits.cmd.cmd.status.hie, UInt<1>(0h0)) node _issue_entry_T_528 = mux(issue_sel_3, entries_ld[3].bits.cmd.cmd.status.hie, UInt<1>(0h0)) node _issue_entry_T_529 = mux(issue_sel_4, entries_ld[4].bits.cmd.cmd.status.hie, UInt<1>(0h0)) node _issue_entry_T_530 = mux(issue_sel_5, entries_ld[5].bits.cmd.cmd.status.hie, UInt<1>(0h0)) node _issue_entry_T_531 = mux(issue_sel_6, entries_ld[6].bits.cmd.cmd.status.hie, UInt<1>(0h0)) node _issue_entry_T_532 = mux(issue_sel_7, entries_ld[7].bits.cmd.cmd.status.hie, UInt<1>(0h0)) node _issue_entry_T_533 = or(_issue_entry_T_525, _issue_entry_T_526) node _issue_entry_T_534 = or(_issue_entry_T_533, _issue_entry_T_527) node _issue_entry_T_535 = or(_issue_entry_T_534, _issue_entry_T_528) node _issue_entry_T_536 = or(_issue_entry_T_535, _issue_entry_T_529) node _issue_entry_T_537 = or(_issue_entry_T_536, _issue_entry_T_530) node _issue_entry_T_538 = or(_issue_entry_T_537, _issue_entry_T_531) node _issue_entry_T_539 = or(_issue_entry_T_538, _issue_entry_T_532) wire _issue_entry_WIRE_43 : UInt<1> connect _issue_entry_WIRE_43, _issue_entry_T_539 connect _issue_entry_WIRE_40.hie, _issue_entry_WIRE_43 node _issue_entry_T_540 = mux(issue_sel_0, entries_ld[0].bits.cmd.cmd.status.mie, UInt<1>(0h0)) node _issue_entry_T_541 = mux(issue_sel_1, entries_ld[1].bits.cmd.cmd.status.mie, UInt<1>(0h0)) node _issue_entry_T_542 = mux(issue_sel_2, entries_ld[2].bits.cmd.cmd.status.mie, UInt<1>(0h0)) node _issue_entry_T_543 = mux(issue_sel_3, entries_ld[3].bits.cmd.cmd.status.mie, UInt<1>(0h0)) node _issue_entry_T_544 = mux(issue_sel_4, entries_ld[4].bits.cmd.cmd.status.mie, UInt<1>(0h0)) node _issue_entry_T_545 = mux(issue_sel_5, entries_ld[5].bits.cmd.cmd.status.mie, UInt<1>(0h0)) node _issue_entry_T_546 = mux(issue_sel_6, entries_ld[6].bits.cmd.cmd.status.mie, UInt<1>(0h0)) node _issue_entry_T_547 = mux(issue_sel_7, entries_ld[7].bits.cmd.cmd.status.mie, UInt<1>(0h0)) node _issue_entry_T_548 = or(_issue_entry_T_540, _issue_entry_T_541) node _issue_entry_T_549 = or(_issue_entry_T_548, _issue_entry_T_542) node _issue_entry_T_550 = or(_issue_entry_T_549, _issue_entry_T_543) node _issue_entry_T_551 = or(_issue_entry_T_550, _issue_entry_T_544) node _issue_entry_T_552 = or(_issue_entry_T_551, _issue_entry_T_545) node _issue_entry_T_553 = or(_issue_entry_T_552, _issue_entry_T_546) node _issue_entry_T_554 = or(_issue_entry_T_553, _issue_entry_T_547) wire _issue_entry_WIRE_44 : UInt<1> connect _issue_entry_WIRE_44, _issue_entry_T_554 connect _issue_entry_WIRE_40.mie, _issue_entry_WIRE_44 node _issue_entry_T_555 = mux(issue_sel_0, entries_ld[0].bits.cmd.cmd.status.upie, UInt<1>(0h0)) node _issue_entry_T_556 = mux(issue_sel_1, entries_ld[1].bits.cmd.cmd.status.upie, UInt<1>(0h0)) node _issue_entry_T_557 = mux(issue_sel_2, entries_ld[2].bits.cmd.cmd.status.upie, UInt<1>(0h0)) node _issue_entry_T_558 = mux(issue_sel_3, entries_ld[3].bits.cmd.cmd.status.upie, UInt<1>(0h0)) node _issue_entry_T_559 = mux(issue_sel_4, entries_ld[4].bits.cmd.cmd.status.upie, UInt<1>(0h0)) node _issue_entry_T_560 = mux(issue_sel_5, entries_ld[5].bits.cmd.cmd.status.upie, UInt<1>(0h0)) node _issue_entry_T_561 = mux(issue_sel_6, entries_ld[6].bits.cmd.cmd.status.upie, UInt<1>(0h0)) node _issue_entry_T_562 = mux(issue_sel_7, entries_ld[7].bits.cmd.cmd.status.upie, UInt<1>(0h0)) node _issue_entry_T_563 = or(_issue_entry_T_555, _issue_entry_T_556) node _issue_entry_T_564 = or(_issue_entry_T_563, _issue_entry_T_557) node _issue_entry_T_565 = or(_issue_entry_T_564, _issue_entry_T_558) node _issue_entry_T_566 = or(_issue_entry_T_565, _issue_entry_T_559) node _issue_entry_T_567 = or(_issue_entry_T_566, _issue_entry_T_560) node _issue_entry_T_568 = or(_issue_entry_T_567, _issue_entry_T_561) node _issue_entry_T_569 = or(_issue_entry_T_568, _issue_entry_T_562) wire _issue_entry_WIRE_45 : UInt<1> connect _issue_entry_WIRE_45, _issue_entry_T_569 connect _issue_entry_WIRE_40.upie, _issue_entry_WIRE_45 node _issue_entry_T_570 = mux(issue_sel_0, entries_ld[0].bits.cmd.cmd.status.spie, UInt<1>(0h0)) node _issue_entry_T_571 = mux(issue_sel_1, entries_ld[1].bits.cmd.cmd.status.spie, UInt<1>(0h0)) node _issue_entry_T_572 = mux(issue_sel_2, entries_ld[2].bits.cmd.cmd.status.spie, UInt<1>(0h0)) node _issue_entry_T_573 = mux(issue_sel_3, entries_ld[3].bits.cmd.cmd.status.spie, UInt<1>(0h0)) node _issue_entry_T_574 = mux(issue_sel_4, entries_ld[4].bits.cmd.cmd.status.spie, UInt<1>(0h0)) node _issue_entry_T_575 = mux(issue_sel_5, entries_ld[5].bits.cmd.cmd.status.spie, UInt<1>(0h0)) node _issue_entry_T_576 = mux(issue_sel_6, entries_ld[6].bits.cmd.cmd.status.spie, UInt<1>(0h0)) node _issue_entry_T_577 = mux(issue_sel_7, entries_ld[7].bits.cmd.cmd.status.spie, UInt<1>(0h0)) node _issue_entry_T_578 = or(_issue_entry_T_570, _issue_entry_T_571) node _issue_entry_T_579 = or(_issue_entry_T_578, _issue_entry_T_572) node _issue_entry_T_580 = or(_issue_entry_T_579, _issue_entry_T_573) node _issue_entry_T_581 = or(_issue_entry_T_580, _issue_entry_T_574) node _issue_entry_T_582 = or(_issue_entry_T_581, _issue_entry_T_575) node _issue_entry_T_583 = or(_issue_entry_T_582, _issue_entry_T_576) node _issue_entry_T_584 = or(_issue_entry_T_583, _issue_entry_T_577) wire _issue_entry_WIRE_46 : UInt<1> connect _issue_entry_WIRE_46, _issue_entry_T_584 connect _issue_entry_WIRE_40.spie, _issue_entry_WIRE_46 node _issue_entry_T_585 = mux(issue_sel_0, entries_ld[0].bits.cmd.cmd.status.ube, UInt<1>(0h0)) node _issue_entry_T_586 = mux(issue_sel_1, entries_ld[1].bits.cmd.cmd.status.ube, UInt<1>(0h0)) node _issue_entry_T_587 = mux(issue_sel_2, entries_ld[2].bits.cmd.cmd.status.ube, UInt<1>(0h0)) node _issue_entry_T_588 = mux(issue_sel_3, entries_ld[3].bits.cmd.cmd.status.ube, UInt<1>(0h0)) node _issue_entry_T_589 = mux(issue_sel_4, entries_ld[4].bits.cmd.cmd.status.ube, UInt<1>(0h0)) node _issue_entry_T_590 = mux(issue_sel_5, entries_ld[5].bits.cmd.cmd.status.ube, UInt<1>(0h0)) node _issue_entry_T_591 = mux(issue_sel_6, entries_ld[6].bits.cmd.cmd.status.ube, UInt<1>(0h0)) node _issue_entry_T_592 = mux(issue_sel_7, entries_ld[7].bits.cmd.cmd.status.ube, UInt<1>(0h0)) node _issue_entry_T_593 = or(_issue_entry_T_585, _issue_entry_T_586) node _issue_entry_T_594 = or(_issue_entry_T_593, _issue_entry_T_587) node _issue_entry_T_595 = or(_issue_entry_T_594, _issue_entry_T_588) node _issue_entry_T_596 = or(_issue_entry_T_595, _issue_entry_T_589) node _issue_entry_T_597 = or(_issue_entry_T_596, _issue_entry_T_590) node _issue_entry_T_598 = or(_issue_entry_T_597, _issue_entry_T_591) node _issue_entry_T_599 = or(_issue_entry_T_598, _issue_entry_T_592) wire _issue_entry_WIRE_47 : UInt<1> connect _issue_entry_WIRE_47, _issue_entry_T_599 connect _issue_entry_WIRE_40.ube, _issue_entry_WIRE_47 node _issue_entry_T_600 = mux(issue_sel_0, entries_ld[0].bits.cmd.cmd.status.mpie, UInt<1>(0h0)) node _issue_entry_T_601 = mux(issue_sel_1, entries_ld[1].bits.cmd.cmd.status.mpie, UInt<1>(0h0)) node _issue_entry_T_602 = mux(issue_sel_2, entries_ld[2].bits.cmd.cmd.status.mpie, UInt<1>(0h0)) node _issue_entry_T_603 = mux(issue_sel_3, entries_ld[3].bits.cmd.cmd.status.mpie, UInt<1>(0h0)) node _issue_entry_T_604 = mux(issue_sel_4, entries_ld[4].bits.cmd.cmd.status.mpie, UInt<1>(0h0)) node _issue_entry_T_605 = mux(issue_sel_5, entries_ld[5].bits.cmd.cmd.status.mpie, UInt<1>(0h0)) node _issue_entry_T_606 = mux(issue_sel_6, entries_ld[6].bits.cmd.cmd.status.mpie, UInt<1>(0h0)) node _issue_entry_T_607 = mux(issue_sel_7, entries_ld[7].bits.cmd.cmd.status.mpie, UInt<1>(0h0)) node _issue_entry_T_608 = or(_issue_entry_T_600, _issue_entry_T_601) node _issue_entry_T_609 = or(_issue_entry_T_608, _issue_entry_T_602) node _issue_entry_T_610 = or(_issue_entry_T_609, _issue_entry_T_603) node _issue_entry_T_611 = or(_issue_entry_T_610, _issue_entry_T_604) node _issue_entry_T_612 = or(_issue_entry_T_611, _issue_entry_T_605) node _issue_entry_T_613 = or(_issue_entry_T_612, _issue_entry_T_606) node _issue_entry_T_614 = or(_issue_entry_T_613, _issue_entry_T_607) wire _issue_entry_WIRE_48 : UInt<1> connect _issue_entry_WIRE_48, _issue_entry_T_614 connect _issue_entry_WIRE_40.mpie, _issue_entry_WIRE_48 node _issue_entry_T_615 = mux(issue_sel_0, entries_ld[0].bits.cmd.cmd.status.spp, UInt<1>(0h0)) node _issue_entry_T_616 = mux(issue_sel_1, entries_ld[1].bits.cmd.cmd.status.spp, UInt<1>(0h0)) node _issue_entry_T_617 = mux(issue_sel_2, entries_ld[2].bits.cmd.cmd.status.spp, UInt<1>(0h0)) node _issue_entry_T_618 = mux(issue_sel_3, entries_ld[3].bits.cmd.cmd.status.spp, UInt<1>(0h0)) node _issue_entry_T_619 = mux(issue_sel_4, entries_ld[4].bits.cmd.cmd.status.spp, UInt<1>(0h0)) node _issue_entry_T_620 = mux(issue_sel_5, entries_ld[5].bits.cmd.cmd.status.spp, UInt<1>(0h0)) node _issue_entry_T_621 = mux(issue_sel_6, entries_ld[6].bits.cmd.cmd.status.spp, UInt<1>(0h0)) node _issue_entry_T_622 = mux(issue_sel_7, entries_ld[7].bits.cmd.cmd.status.spp, UInt<1>(0h0)) node _issue_entry_T_623 = or(_issue_entry_T_615, _issue_entry_T_616) node _issue_entry_T_624 = or(_issue_entry_T_623, _issue_entry_T_617) node _issue_entry_T_625 = or(_issue_entry_T_624, _issue_entry_T_618) node _issue_entry_T_626 = or(_issue_entry_T_625, _issue_entry_T_619) node _issue_entry_T_627 = or(_issue_entry_T_626, _issue_entry_T_620) node _issue_entry_T_628 = or(_issue_entry_T_627, _issue_entry_T_621) node _issue_entry_T_629 = or(_issue_entry_T_628, _issue_entry_T_622) wire _issue_entry_WIRE_49 : UInt<1> connect _issue_entry_WIRE_49, _issue_entry_T_629 connect _issue_entry_WIRE_40.spp, _issue_entry_WIRE_49 node _issue_entry_T_630 = mux(issue_sel_0, entries_ld[0].bits.cmd.cmd.status.vs, UInt<1>(0h0)) node _issue_entry_T_631 = mux(issue_sel_1, entries_ld[1].bits.cmd.cmd.status.vs, UInt<1>(0h0)) node _issue_entry_T_632 = mux(issue_sel_2, entries_ld[2].bits.cmd.cmd.status.vs, UInt<1>(0h0)) node _issue_entry_T_633 = mux(issue_sel_3, entries_ld[3].bits.cmd.cmd.status.vs, UInt<1>(0h0)) node _issue_entry_T_634 = mux(issue_sel_4, entries_ld[4].bits.cmd.cmd.status.vs, UInt<1>(0h0)) node _issue_entry_T_635 = mux(issue_sel_5, entries_ld[5].bits.cmd.cmd.status.vs, UInt<1>(0h0)) node _issue_entry_T_636 = mux(issue_sel_6, entries_ld[6].bits.cmd.cmd.status.vs, UInt<1>(0h0)) node _issue_entry_T_637 = mux(issue_sel_7, entries_ld[7].bits.cmd.cmd.status.vs, UInt<1>(0h0)) node _issue_entry_T_638 = or(_issue_entry_T_630, _issue_entry_T_631) node _issue_entry_T_639 = or(_issue_entry_T_638, _issue_entry_T_632) node _issue_entry_T_640 = or(_issue_entry_T_639, _issue_entry_T_633) node _issue_entry_T_641 = or(_issue_entry_T_640, _issue_entry_T_634) node _issue_entry_T_642 = or(_issue_entry_T_641, _issue_entry_T_635) node _issue_entry_T_643 = or(_issue_entry_T_642, _issue_entry_T_636) node _issue_entry_T_644 = or(_issue_entry_T_643, _issue_entry_T_637) wire _issue_entry_WIRE_50 : UInt<2> connect _issue_entry_WIRE_50, _issue_entry_T_644 connect _issue_entry_WIRE_40.vs, _issue_entry_WIRE_50 node _issue_entry_T_645 = mux(issue_sel_0, entries_ld[0].bits.cmd.cmd.status.mpp, UInt<1>(0h0)) node _issue_entry_T_646 = mux(issue_sel_1, entries_ld[1].bits.cmd.cmd.status.mpp, UInt<1>(0h0)) node _issue_entry_T_647 = mux(issue_sel_2, entries_ld[2].bits.cmd.cmd.status.mpp, UInt<1>(0h0)) node _issue_entry_T_648 = mux(issue_sel_3, entries_ld[3].bits.cmd.cmd.status.mpp, UInt<1>(0h0)) node _issue_entry_T_649 = mux(issue_sel_4, entries_ld[4].bits.cmd.cmd.status.mpp, UInt<1>(0h0)) node _issue_entry_T_650 = mux(issue_sel_5, entries_ld[5].bits.cmd.cmd.status.mpp, UInt<1>(0h0)) node _issue_entry_T_651 = mux(issue_sel_6, entries_ld[6].bits.cmd.cmd.status.mpp, UInt<1>(0h0)) node _issue_entry_T_652 = mux(issue_sel_7, entries_ld[7].bits.cmd.cmd.status.mpp, UInt<1>(0h0)) node _issue_entry_T_653 = or(_issue_entry_T_645, _issue_entry_T_646) node _issue_entry_T_654 = or(_issue_entry_T_653, _issue_entry_T_647) node _issue_entry_T_655 = or(_issue_entry_T_654, _issue_entry_T_648) node _issue_entry_T_656 = or(_issue_entry_T_655, _issue_entry_T_649) node _issue_entry_T_657 = or(_issue_entry_T_656, _issue_entry_T_650) node _issue_entry_T_658 = or(_issue_entry_T_657, _issue_entry_T_651) node _issue_entry_T_659 = or(_issue_entry_T_658, _issue_entry_T_652) wire _issue_entry_WIRE_51 : UInt<2> connect _issue_entry_WIRE_51, _issue_entry_T_659 connect _issue_entry_WIRE_40.mpp, _issue_entry_WIRE_51 node _issue_entry_T_660 = mux(issue_sel_0, entries_ld[0].bits.cmd.cmd.status.fs, UInt<1>(0h0)) node _issue_entry_T_661 = mux(issue_sel_1, entries_ld[1].bits.cmd.cmd.status.fs, UInt<1>(0h0)) node _issue_entry_T_662 = mux(issue_sel_2, entries_ld[2].bits.cmd.cmd.status.fs, UInt<1>(0h0)) node _issue_entry_T_663 = mux(issue_sel_3, entries_ld[3].bits.cmd.cmd.status.fs, UInt<1>(0h0)) node _issue_entry_T_664 = mux(issue_sel_4, entries_ld[4].bits.cmd.cmd.status.fs, UInt<1>(0h0)) node _issue_entry_T_665 = mux(issue_sel_5, entries_ld[5].bits.cmd.cmd.status.fs, UInt<1>(0h0)) node _issue_entry_T_666 = mux(issue_sel_6, entries_ld[6].bits.cmd.cmd.status.fs, UInt<1>(0h0)) node _issue_entry_T_667 = mux(issue_sel_7, entries_ld[7].bits.cmd.cmd.status.fs, UInt<1>(0h0)) node _issue_entry_T_668 = or(_issue_entry_T_660, _issue_entry_T_661) node _issue_entry_T_669 = or(_issue_entry_T_668, _issue_entry_T_662) node _issue_entry_T_670 = or(_issue_entry_T_669, _issue_entry_T_663) node _issue_entry_T_671 = or(_issue_entry_T_670, _issue_entry_T_664) node _issue_entry_T_672 = or(_issue_entry_T_671, _issue_entry_T_665) node _issue_entry_T_673 = or(_issue_entry_T_672, _issue_entry_T_666) node _issue_entry_T_674 = or(_issue_entry_T_673, _issue_entry_T_667) wire _issue_entry_WIRE_52 : UInt<2> connect _issue_entry_WIRE_52, _issue_entry_T_674 connect _issue_entry_WIRE_40.fs, _issue_entry_WIRE_52 node _issue_entry_T_675 = mux(issue_sel_0, entries_ld[0].bits.cmd.cmd.status.xs, UInt<1>(0h0)) node _issue_entry_T_676 = mux(issue_sel_1, entries_ld[1].bits.cmd.cmd.status.xs, UInt<1>(0h0)) node _issue_entry_T_677 = mux(issue_sel_2, entries_ld[2].bits.cmd.cmd.status.xs, UInt<1>(0h0)) node _issue_entry_T_678 = mux(issue_sel_3, entries_ld[3].bits.cmd.cmd.status.xs, UInt<1>(0h0)) node _issue_entry_T_679 = mux(issue_sel_4, entries_ld[4].bits.cmd.cmd.status.xs, UInt<1>(0h0)) node _issue_entry_T_680 = mux(issue_sel_5, entries_ld[5].bits.cmd.cmd.status.xs, UInt<1>(0h0)) node _issue_entry_T_681 = mux(issue_sel_6, entries_ld[6].bits.cmd.cmd.status.xs, UInt<1>(0h0)) node _issue_entry_T_682 = mux(issue_sel_7, entries_ld[7].bits.cmd.cmd.status.xs, UInt<1>(0h0)) node _issue_entry_T_683 = or(_issue_entry_T_675, _issue_entry_T_676) node _issue_entry_T_684 = or(_issue_entry_T_683, _issue_entry_T_677) node _issue_entry_T_685 = or(_issue_entry_T_684, _issue_entry_T_678) node _issue_entry_T_686 = or(_issue_entry_T_685, _issue_entry_T_679) node _issue_entry_T_687 = or(_issue_entry_T_686, _issue_entry_T_680) node _issue_entry_T_688 = or(_issue_entry_T_687, _issue_entry_T_681) node _issue_entry_T_689 = or(_issue_entry_T_688, _issue_entry_T_682) wire _issue_entry_WIRE_53 : UInt<2> connect _issue_entry_WIRE_53, _issue_entry_T_689 connect _issue_entry_WIRE_40.xs, _issue_entry_WIRE_53 node _issue_entry_T_690 = mux(issue_sel_0, entries_ld[0].bits.cmd.cmd.status.mprv, UInt<1>(0h0)) node _issue_entry_T_691 = mux(issue_sel_1, entries_ld[1].bits.cmd.cmd.status.mprv, UInt<1>(0h0)) node _issue_entry_T_692 = mux(issue_sel_2, entries_ld[2].bits.cmd.cmd.status.mprv, UInt<1>(0h0)) node _issue_entry_T_693 = mux(issue_sel_3, entries_ld[3].bits.cmd.cmd.status.mprv, UInt<1>(0h0)) node _issue_entry_T_694 = mux(issue_sel_4, entries_ld[4].bits.cmd.cmd.status.mprv, UInt<1>(0h0)) node _issue_entry_T_695 = mux(issue_sel_5, entries_ld[5].bits.cmd.cmd.status.mprv, UInt<1>(0h0)) node _issue_entry_T_696 = mux(issue_sel_6, entries_ld[6].bits.cmd.cmd.status.mprv, UInt<1>(0h0)) node _issue_entry_T_697 = mux(issue_sel_7, entries_ld[7].bits.cmd.cmd.status.mprv, UInt<1>(0h0)) node _issue_entry_T_698 = or(_issue_entry_T_690, _issue_entry_T_691) node _issue_entry_T_699 = or(_issue_entry_T_698, _issue_entry_T_692) node _issue_entry_T_700 = or(_issue_entry_T_699, _issue_entry_T_693) node _issue_entry_T_701 = or(_issue_entry_T_700, _issue_entry_T_694) node _issue_entry_T_702 = or(_issue_entry_T_701, _issue_entry_T_695) node _issue_entry_T_703 = or(_issue_entry_T_702, _issue_entry_T_696) node _issue_entry_T_704 = or(_issue_entry_T_703, _issue_entry_T_697) wire _issue_entry_WIRE_54 : UInt<1> connect _issue_entry_WIRE_54, _issue_entry_T_704 connect _issue_entry_WIRE_40.mprv, _issue_entry_WIRE_54 node _issue_entry_T_705 = mux(issue_sel_0, entries_ld[0].bits.cmd.cmd.status.sum, UInt<1>(0h0)) node _issue_entry_T_706 = mux(issue_sel_1, entries_ld[1].bits.cmd.cmd.status.sum, UInt<1>(0h0)) node _issue_entry_T_707 = mux(issue_sel_2, entries_ld[2].bits.cmd.cmd.status.sum, UInt<1>(0h0)) node _issue_entry_T_708 = mux(issue_sel_3, entries_ld[3].bits.cmd.cmd.status.sum, UInt<1>(0h0)) node _issue_entry_T_709 = mux(issue_sel_4, entries_ld[4].bits.cmd.cmd.status.sum, UInt<1>(0h0)) node _issue_entry_T_710 = mux(issue_sel_5, entries_ld[5].bits.cmd.cmd.status.sum, UInt<1>(0h0)) node _issue_entry_T_711 = mux(issue_sel_6, entries_ld[6].bits.cmd.cmd.status.sum, UInt<1>(0h0)) node _issue_entry_T_712 = mux(issue_sel_7, entries_ld[7].bits.cmd.cmd.status.sum, UInt<1>(0h0)) node _issue_entry_T_713 = or(_issue_entry_T_705, _issue_entry_T_706) node _issue_entry_T_714 = or(_issue_entry_T_713, _issue_entry_T_707) node _issue_entry_T_715 = or(_issue_entry_T_714, _issue_entry_T_708) node _issue_entry_T_716 = or(_issue_entry_T_715, _issue_entry_T_709) node _issue_entry_T_717 = or(_issue_entry_T_716, _issue_entry_T_710) node _issue_entry_T_718 = or(_issue_entry_T_717, _issue_entry_T_711) node _issue_entry_T_719 = or(_issue_entry_T_718, _issue_entry_T_712) wire _issue_entry_WIRE_55 : UInt<1> connect _issue_entry_WIRE_55, _issue_entry_T_719 connect _issue_entry_WIRE_40.sum, _issue_entry_WIRE_55 node _issue_entry_T_720 = mux(issue_sel_0, entries_ld[0].bits.cmd.cmd.status.mxr, UInt<1>(0h0)) node _issue_entry_T_721 = mux(issue_sel_1, entries_ld[1].bits.cmd.cmd.status.mxr, UInt<1>(0h0)) node _issue_entry_T_722 = mux(issue_sel_2, entries_ld[2].bits.cmd.cmd.status.mxr, UInt<1>(0h0)) node _issue_entry_T_723 = mux(issue_sel_3, entries_ld[3].bits.cmd.cmd.status.mxr, UInt<1>(0h0)) node _issue_entry_T_724 = mux(issue_sel_4, entries_ld[4].bits.cmd.cmd.status.mxr, UInt<1>(0h0)) node _issue_entry_T_725 = mux(issue_sel_5, entries_ld[5].bits.cmd.cmd.status.mxr, UInt<1>(0h0)) node _issue_entry_T_726 = mux(issue_sel_6, entries_ld[6].bits.cmd.cmd.status.mxr, UInt<1>(0h0)) node _issue_entry_T_727 = mux(issue_sel_7, entries_ld[7].bits.cmd.cmd.status.mxr, UInt<1>(0h0)) node _issue_entry_T_728 = or(_issue_entry_T_720, _issue_entry_T_721) node _issue_entry_T_729 = or(_issue_entry_T_728, _issue_entry_T_722) node _issue_entry_T_730 = or(_issue_entry_T_729, _issue_entry_T_723) node _issue_entry_T_731 = or(_issue_entry_T_730, _issue_entry_T_724) node _issue_entry_T_732 = or(_issue_entry_T_731, _issue_entry_T_725) node _issue_entry_T_733 = or(_issue_entry_T_732, _issue_entry_T_726) node _issue_entry_T_734 = or(_issue_entry_T_733, _issue_entry_T_727) wire _issue_entry_WIRE_56 : UInt<1> connect _issue_entry_WIRE_56, _issue_entry_T_734 connect _issue_entry_WIRE_40.mxr, _issue_entry_WIRE_56 node _issue_entry_T_735 = mux(issue_sel_0, entries_ld[0].bits.cmd.cmd.status.tvm, UInt<1>(0h0)) node _issue_entry_T_736 = mux(issue_sel_1, entries_ld[1].bits.cmd.cmd.status.tvm, UInt<1>(0h0)) node _issue_entry_T_737 = mux(issue_sel_2, entries_ld[2].bits.cmd.cmd.status.tvm, UInt<1>(0h0)) node _issue_entry_T_738 = mux(issue_sel_3, entries_ld[3].bits.cmd.cmd.status.tvm, UInt<1>(0h0)) node _issue_entry_T_739 = mux(issue_sel_4, entries_ld[4].bits.cmd.cmd.status.tvm, UInt<1>(0h0)) node _issue_entry_T_740 = mux(issue_sel_5, entries_ld[5].bits.cmd.cmd.status.tvm, UInt<1>(0h0)) node _issue_entry_T_741 = mux(issue_sel_6, entries_ld[6].bits.cmd.cmd.status.tvm, UInt<1>(0h0)) node _issue_entry_T_742 = mux(issue_sel_7, entries_ld[7].bits.cmd.cmd.status.tvm, UInt<1>(0h0)) node _issue_entry_T_743 = or(_issue_entry_T_735, _issue_entry_T_736) node _issue_entry_T_744 = or(_issue_entry_T_743, _issue_entry_T_737) node _issue_entry_T_745 = or(_issue_entry_T_744, _issue_entry_T_738) node _issue_entry_T_746 = or(_issue_entry_T_745, _issue_entry_T_739) node _issue_entry_T_747 = or(_issue_entry_T_746, _issue_entry_T_740) node _issue_entry_T_748 = or(_issue_entry_T_747, _issue_entry_T_741) node _issue_entry_T_749 = or(_issue_entry_T_748, _issue_entry_T_742) wire _issue_entry_WIRE_57 : UInt<1> connect _issue_entry_WIRE_57, _issue_entry_T_749 connect _issue_entry_WIRE_40.tvm, _issue_entry_WIRE_57 node _issue_entry_T_750 = mux(issue_sel_0, entries_ld[0].bits.cmd.cmd.status.tw, UInt<1>(0h0)) node _issue_entry_T_751 = mux(issue_sel_1, entries_ld[1].bits.cmd.cmd.status.tw, UInt<1>(0h0)) node _issue_entry_T_752 = mux(issue_sel_2, entries_ld[2].bits.cmd.cmd.status.tw, UInt<1>(0h0)) node _issue_entry_T_753 = mux(issue_sel_3, entries_ld[3].bits.cmd.cmd.status.tw, UInt<1>(0h0)) node _issue_entry_T_754 = mux(issue_sel_4, entries_ld[4].bits.cmd.cmd.status.tw, UInt<1>(0h0)) node _issue_entry_T_755 = mux(issue_sel_5, entries_ld[5].bits.cmd.cmd.status.tw, UInt<1>(0h0)) node _issue_entry_T_756 = mux(issue_sel_6, entries_ld[6].bits.cmd.cmd.status.tw, UInt<1>(0h0)) node _issue_entry_T_757 = mux(issue_sel_7, entries_ld[7].bits.cmd.cmd.status.tw, UInt<1>(0h0)) node _issue_entry_T_758 = or(_issue_entry_T_750, _issue_entry_T_751) node _issue_entry_T_759 = or(_issue_entry_T_758, _issue_entry_T_752) node _issue_entry_T_760 = or(_issue_entry_T_759, _issue_entry_T_753) node _issue_entry_T_761 = or(_issue_entry_T_760, _issue_entry_T_754) node _issue_entry_T_762 = or(_issue_entry_T_761, _issue_entry_T_755) node _issue_entry_T_763 = or(_issue_entry_T_762, _issue_entry_T_756) node _issue_entry_T_764 = or(_issue_entry_T_763, _issue_entry_T_757) wire _issue_entry_WIRE_58 : UInt<1> connect _issue_entry_WIRE_58, _issue_entry_T_764 connect _issue_entry_WIRE_40.tw, _issue_entry_WIRE_58 node _issue_entry_T_765 = mux(issue_sel_0, entries_ld[0].bits.cmd.cmd.status.tsr, UInt<1>(0h0)) node _issue_entry_T_766 = mux(issue_sel_1, entries_ld[1].bits.cmd.cmd.status.tsr, UInt<1>(0h0)) node _issue_entry_T_767 = mux(issue_sel_2, entries_ld[2].bits.cmd.cmd.status.tsr, UInt<1>(0h0)) node _issue_entry_T_768 = mux(issue_sel_3, entries_ld[3].bits.cmd.cmd.status.tsr, UInt<1>(0h0)) node _issue_entry_T_769 = mux(issue_sel_4, entries_ld[4].bits.cmd.cmd.status.tsr, UInt<1>(0h0)) node _issue_entry_T_770 = mux(issue_sel_5, entries_ld[5].bits.cmd.cmd.status.tsr, UInt<1>(0h0)) node _issue_entry_T_771 = mux(issue_sel_6, entries_ld[6].bits.cmd.cmd.status.tsr, UInt<1>(0h0)) node _issue_entry_T_772 = mux(issue_sel_7, entries_ld[7].bits.cmd.cmd.status.tsr, UInt<1>(0h0)) node _issue_entry_T_773 = or(_issue_entry_T_765, _issue_entry_T_766) node _issue_entry_T_774 = or(_issue_entry_T_773, _issue_entry_T_767) node _issue_entry_T_775 = or(_issue_entry_T_774, _issue_entry_T_768) node _issue_entry_T_776 = or(_issue_entry_T_775, _issue_entry_T_769) node _issue_entry_T_777 = or(_issue_entry_T_776, _issue_entry_T_770) node _issue_entry_T_778 = or(_issue_entry_T_777, _issue_entry_T_771) node _issue_entry_T_779 = or(_issue_entry_T_778, _issue_entry_T_772) wire _issue_entry_WIRE_59 : UInt<1> connect _issue_entry_WIRE_59, _issue_entry_T_779 connect _issue_entry_WIRE_40.tsr, _issue_entry_WIRE_59 node _issue_entry_T_780 = mux(issue_sel_0, entries_ld[0].bits.cmd.cmd.status.zero1, UInt<1>(0h0)) node _issue_entry_T_781 = mux(issue_sel_1, entries_ld[1].bits.cmd.cmd.status.zero1, UInt<1>(0h0)) node _issue_entry_T_782 = mux(issue_sel_2, entries_ld[2].bits.cmd.cmd.status.zero1, UInt<1>(0h0)) node _issue_entry_T_783 = mux(issue_sel_3, entries_ld[3].bits.cmd.cmd.status.zero1, UInt<1>(0h0)) node _issue_entry_T_784 = mux(issue_sel_4, entries_ld[4].bits.cmd.cmd.status.zero1, UInt<1>(0h0)) node _issue_entry_T_785 = mux(issue_sel_5, entries_ld[5].bits.cmd.cmd.status.zero1, UInt<1>(0h0)) node _issue_entry_T_786 = mux(issue_sel_6, entries_ld[6].bits.cmd.cmd.status.zero1, UInt<1>(0h0)) node _issue_entry_T_787 = mux(issue_sel_7, entries_ld[7].bits.cmd.cmd.status.zero1, UInt<1>(0h0)) node _issue_entry_T_788 = or(_issue_entry_T_780, _issue_entry_T_781) node _issue_entry_T_789 = or(_issue_entry_T_788, _issue_entry_T_782) node _issue_entry_T_790 = or(_issue_entry_T_789, _issue_entry_T_783) node _issue_entry_T_791 = or(_issue_entry_T_790, _issue_entry_T_784) node _issue_entry_T_792 = or(_issue_entry_T_791, _issue_entry_T_785) node _issue_entry_T_793 = or(_issue_entry_T_792, _issue_entry_T_786) node _issue_entry_T_794 = or(_issue_entry_T_793, _issue_entry_T_787) wire _issue_entry_WIRE_60 : UInt<8> connect _issue_entry_WIRE_60, _issue_entry_T_794 connect _issue_entry_WIRE_40.zero1, _issue_entry_WIRE_60 node _issue_entry_T_795 = mux(issue_sel_0, entries_ld[0].bits.cmd.cmd.status.sd_rv32, UInt<1>(0h0)) node _issue_entry_T_796 = mux(issue_sel_1, entries_ld[1].bits.cmd.cmd.status.sd_rv32, UInt<1>(0h0)) node _issue_entry_T_797 = mux(issue_sel_2, entries_ld[2].bits.cmd.cmd.status.sd_rv32, UInt<1>(0h0)) node _issue_entry_T_798 = mux(issue_sel_3, entries_ld[3].bits.cmd.cmd.status.sd_rv32, UInt<1>(0h0)) node _issue_entry_T_799 = mux(issue_sel_4, entries_ld[4].bits.cmd.cmd.status.sd_rv32, UInt<1>(0h0)) node _issue_entry_T_800 = mux(issue_sel_5, entries_ld[5].bits.cmd.cmd.status.sd_rv32, UInt<1>(0h0)) node _issue_entry_T_801 = mux(issue_sel_6, entries_ld[6].bits.cmd.cmd.status.sd_rv32, UInt<1>(0h0)) node _issue_entry_T_802 = mux(issue_sel_7, entries_ld[7].bits.cmd.cmd.status.sd_rv32, UInt<1>(0h0)) node _issue_entry_T_803 = or(_issue_entry_T_795, _issue_entry_T_796) node _issue_entry_T_804 = or(_issue_entry_T_803, _issue_entry_T_797) node _issue_entry_T_805 = or(_issue_entry_T_804, _issue_entry_T_798) node _issue_entry_T_806 = or(_issue_entry_T_805, _issue_entry_T_799) node _issue_entry_T_807 = or(_issue_entry_T_806, _issue_entry_T_800) node _issue_entry_T_808 = or(_issue_entry_T_807, _issue_entry_T_801) node _issue_entry_T_809 = or(_issue_entry_T_808, _issue_entry_T_802) wire _issue_entry_WIRE_61 : UInt<1> connect _issue_entry_WIRE_61, _issue_entry_T_809 connect _issue_entry_WIRE_40.sd_rv32, _issue_entry_WIRE_61 node _issue_entry_T_810 = mux(issue_sel_0, entries_ld[0].bits.cmd.cmd.status.uxl, UInt<1>(0h0)) node _issue_entry_T_811 = mux(issue_sel_1, entries_ld[1].bits.cmd.cmd.status.uxl, UInt<1>(0h0)) node _issue_entry_T_812 = mux(issue_sel_2, entries_ld[2].bits.cmd.cmd.status.uxl, UInt<1>(0h0)) node _issue_entry_T_813 = mux(issue_sel_3, entries_ld[3].bits.cmd.cmd.status.uxl, UInt<1>(0h0)) node _issue_entry_T_814 = mux(issue_sel_4, entries_ld[4].bits.cmd.cmd.status.uxl, UInt<1>(0h0)) node _issue_entry_T_815 = mux(issue_sel_5, entries_ld[5].bits.cmd.cmd.status.uxl, UInt<1>(0h0)) node _issue_entry_T_816 = mux(issue_sel_6, entries_ld[6].bits.cmd.cmd.status.uxl, UInt<1>(0h0)) node _issue_entry_T_817 = mux(issue_sel_7, entries_ld[7].bits.cmd.cmd.status.uxl, UInt<1>(0h0)) node _issue_entry_T_818 = or(_issue_entry_T_810, _issue_entry_T_811) node _issue_entry_T_819 = or(_issue_entry_T_818, _issue_entry_T_812) node _issue_entry_T_820 = or(_issue_entry_T_819, _issue_entry_T_813) node _issue_entry_T_821 = or(_issue_entry_T_820, _issue_entry_T_814) node _issue_entry_T_822 = or(_issue_entry_T_821, _issue_entry_T_815) node _issue_entry_T_823 = or(_issue_entry_T_822, _issue_entry_T_816) node _issue_entry_T_824 = or(_issue_entry_T_823, _issue_entry_T_817) wire _issue_entry_WIRE_62 : UInt<2> connect _issue_entry_WIRE_62, _issue_entry_T_824 connect _issue_entry_WIRE_40.uxl, _issue_entry_WIRE_62 node _issue_entry_T_825 = mux(issue_sel_0, entries_ld[0].bits.cmd.cmd.status.sxl, UInt<1>(0h0)) node _issue_entry_T_826 = mux(issue_sel_1, entries_ld[1].bits.cmd.cmd.status.sxl, UInt<1>(0h0)) node _issue_entry_T_827 = mux(issue_sel_2, entries_ld[2].bits.cmd.cmd.status.sxl, UInt<1>(0h0)) node _issue_entry_T_828 = mux(issue_sel_3, entries_ld[3].bits.cmd.cmd.status.sxl, UInt<1>(0h0)) node _issue_entry_T_829 = mux(issue_sel_4, entries_ld[4].bits.cmd.cmd.status.sxl, UInt<1>(0h0)) node _issue_entry_T_830 = mux(issue_sel_5, entries_ld[5].bits.cmd.cmd.status.sxl, UInt<1>(0h0)) node _issue_entry_T_831 = mux(issue_sel_6, entries_ld[6].bits.cmd.cmd.status.sxl, UInt<1>(0h0)) node _issue_entry_T_832 = mux(issue_sel_7, entries_ld[7].bits.cmd.cmd.status.sxl, UInt<1>(0h0)) node _issue_entry_T_833 = or(_issue_entry_T_825, _issue_entry_T_826) node _issue_entry_T_834 = or(_issue_entry_T_833, _issue_entry_T_827) node _issue_entry_T_835 = or(_issue_entry_T_834, _issue_entry_T_828) node _issue_entry_T_836 = or(_issue_entry_T_835, _issue_entry_T_829) node _issue_entry_T_837 = or(_issue_entry_T_836, _issue_entry_T_830) node _issue_entry_T_838 = or(_issue_entry_T_837, _issue_entry_T_831) node _issue_entry_T_839 = or(_issue_entry_T_838, _issue_entry_T_832) wire _issue_entry_WIRE_63 : UInt<2> connect _issue_entry_WIRE_63, _issue_entry_T_839 connect _issue_entry_WIRE_40.sxl, _issue_entry_WIRE_63 node _issue_entry_T_840 = mux(issue_sel_0, entries_ld[0].bits.cmd.cmd.status.sbe, UInt<1>(0h0)) node _issue_entry_T_841 = mux(issue_sel_1, entries_ld[1].bits.cmd.cmd.status.sbe, UInt<1>(0h0)) node _issue_entry_T_842 = mux(issue_sel_2, entries_ld[2].bits.cmd.cmd.status.sbe, UInt<1>(0h0)) node _issue_entry_T_843 = mux(issue_sel_3, entries_ld[3].bits.cmd.cmd.status.sbe, UInt<1>(0h0)) node _issue_entry_T_844 = mux(issue_sel_4, entries_ld[4].bits.cmd.cmd.status.sbe, UInt<1>(0h0)) node _issue_entry_T_845 = mux(issue_sel_5, entries_ld[5].bits.cmd.cmd.status.sbe, UInt<1>(0h0)) node _issue_entry_T_846 = mux(issue_sel_6, entries_ld[6].bits.cmd.cmd.status.sbe, UInt<1>(0h0)) node _issue_entry_T_847 = mux(issue_sel_7, entries_ld[7].bits.cmd.cmd.status.sbe, UInt<1>(0h0)) node _issue_entry_T_848 = or(_issue_entry_T_840, _issue_entry_T_841) node _issue_entry_T_849 = or(_issue_entry_T_848, _issue_entry_T_842) node _issue_entry_T_850 = or(_issue_entry_T_849, _issue_entry_T_843) node _issue_entry_T_851 = or(_issue_entry_T_850, _issue_entry_T_844) node _issue_entry_T_852 = or(_issue_entry_T_851, _issue_entry_T_845) node _issue_entry_T_853 = or(_issue_entry_T_852, _issue_entry_T_846) node _issue_entry_T_854 = or(_issue_entry_T_853, _issue_entry_T_847) wire _issue_entry_WIRE_64 : UInt<1> connect _issue_entry_WIRE_64, _issue_entry_T_854 connect _issue_entry_WIRE_40.sbe, _issue_entry_WIRE_64 node _issue_entry_T_855 = mux(issue_sel_0, entries_ld[0].bits.cmd.cmd.status.mbe, UInt<1>(0h0)) node _issue_entry_T_856 = mux(issue_sel_1, entries_ld[1].bits.cmd.cmd.status.mbe, UInt<1>(0h0)) node _issue_entry_T_857 = mux(issue_sel_2, entries_ld[2].bits.cmd.cmd.status.mbe, UInt<1>(0h0)) node _issue_entry_T_858 = mux(issue_sel_3, entries_ld[3].bits.cmd.cmd.status.mbe, UInt<1>(0h0)) node _issue_entry_T_859 = mux(issue_sel_4, entries_ld[4].bits.cmd.cmd.status.mbe, UInt<1>(0h0)) node _issue_entry_T_860 = mux(issue_sel_5, entries_ld[5].bits.cmd.cmd.status.mbe, UInt<1>(0h0)) node _issue_entry_T_861 = mux(issue_sel_6, entries_ld[6].bits.cmd.cmd.status.mbe, UInt<1>(0h0)) node _issue_entry_T_862 = mux(issue_sel_7, entries_ld[7].bits.cmd.cmd.status.mbe, UInt<1>(0h0)) node _issue_entry_T_863 = or(_issue_entry_T_855, _issue_entry_T_856) node _issue_entry_T_864 = or(_issue_entry_T_863, _issue_entry_T_857) node _issue_entry_T_865 = or(_issue_entry_T_864, _issue_entry_T_858) node _issue_entry_T_866 = or(_issue_entry_T_865, _issue_entry_T_859) node _issue_entry_T_867 = or(_issue_entry_T_866, _issue_entry_T_860) node _issue_entry_T_868 = or(_issue_entry_T_867, _issue_entry_T_861) node _issue_entry_T_869 = or(_issue_entry_T_868, _issue_entry_T_862) wire _issue_entry_WIRE_65 : UInt<1> connect _issue_entry_WIRE_65, _issue_entry_T_869 connect _issue_entry_WIRE_40.mbe, _issue_entry_WIRE_65 node _issue_entry_T_870 = mux(issue_sel_0, entries_ld[0].bits.cmd.cmd.status.gva, UInt<1>(0h0)) node _issue_entry_T_871 = mux(issue_sel_1, entries_ld[1].bits.cmd.cmd.status.gva, UInt<1>(0h0)) node _issue_entry_T_872 = mux(issue_sel_2, entries_ld[2].bits.cmd.cmd.status.gva, UInt<1>(0h0)) node _issue_entry_T_873 = mux(issue_sel_3, entries_ld[3].bits.cmd.cmd.status.gva, UInt<1>(0h0)) node _issue_entry_T_874 = mux(issue_sel_4, entries_ld[4].bits.cmd.cmd.status.gva, UInt<1>(0h0)) node _issue_entry_T_875 = mux(issue_sel_5, entries_ld[5].bits.cmd.cmd.status.gva, UInt<1>(0h0)) node _issue_entry_T_876 = mux(issue_sel_6, entries_ld[6].bits.cmd.cmd.status.gva, UInt<1>(0h0)) node _issue_entry_T_877 = mux(issue_sel_7, entries_ld[7].bits.cmd.cmd.status.gva, UInt<1>(0h0)) node _issue_entry_T_878 = or(_issue_entry_T_870, _issue_entry_T_871) node _issue_entry_T_879 = or(_issue_entry_T_878, _issue_entry_T_872) node _issue_entry_T_880 = or(_issue_entry_T_879, _issue_entry_T_873) node _issue_entry_T_881 = or(_issue_entry_T_880, _issue_entry_T_874) node _issue_entry_T_882 = or(_issue_entry_T_881, _issue_entry_T_875) node _issue_entry_T_883 = or(_issue_entry_T_882, _issue_entry_T_876) node _issue_entry_T_884 = or(_issue_entry_T_883, _issue_entry_T_877) wire _issue_entry_WIRE_66 : UInt<1> connect _issue_entry_WIRE_66, _issue_entry_T_884 connect _issue_entry_WIRE_40.gva, _issue_entry_WIRE_66 node _issue_entry_T_885 = mux(issue_sel_0, entries_ld[0].bits.cmd.cmd.status.mpv, UInt<1>(0h0)) node _issue_entry_T_886 = mux(issue_sel_1, entries_ld[1].bits.cmd.cmd.status.mpv, UInt<1>(0h0)) node _issue_entry_T_887 = mux(issue_sel_2, entries_ld[2].bits.cmd.cmd.status.mpv, UInt<1>(0h0)) node _issue_entry_T_888 = mux(issue_sel_3, entries_ld[3].bits.cmd.cmd.status.mpv, UInt<1>(0h0)) node _issue_entry_T_889 = mux(issue_sel_4, entries_ld[4].bits.cmd.cmd.status.mpv, UInt<1>(0h0)) node _issue_entry_T_890 = mux(issue_sel_5, entries_ld[5].bits.cmd.cmd.status.mpv, UInt<1>(0h0)) node _issue_entry_T_891 = mux(issue_sel_6, entries_ld[6].bits.cmd.cmd.status.mpv, UInt<1>(0h0)) node _issue_entry_T_892 = mux(issue_sel_7, entries_ld[7].bits.cmd.cmd.status.mpv, UInt<1>(0h0)) node _issue_entry_T_893 = or(_issue_entry_T_885, _issue_entry_T_886) node _issue_entry_T_894 = or(_issue_entry_T_893, _issue_entry_T_887) node _issue_entry_T_895 = or(_issue_entry_T_894, _issue_entry_T_888) node _issue_entry_T_896 = or(_issue_entry_T_895, _issue_entry_T_889) node _issue_entry_T_897 = or(_issue_entry_T_896, _issue_entry_T_890) node _issue_entry_T_898 = or(_issue_entry_T_897, _issue_entry_T_891) node _issue_entry_T_899 = or(_issue_entry_T_898, _issue_entry_T_892) wire _issue_entry_WIRE_67 : UInt<1> connect _issue_entry_WIRE_67, _issue_entry_T_899 connect _issue_entry_WIRE_40.mpv, _issue_entry_WIRE_67 node _issue_entry_T_900 = mux(issue_sel_0, entries_ld[0].bits.cmd.cmd.status.zero2, UInt<1>(0h0)) node _issue_entry_T_901 = mux(issue_sel_1, entries_ld[1].bits.cmd.cmd.status.zero2, UInt<1>(0h0)) node _issue_entry_T_902 = mux(issue_sel_2, entries_ld[2].bits.cmd.cmd.status.zero2, UInt<1>(0h0)) node _issue_entry_T_903 = mux(issue_sel_3, entries_ld[3].bits.cmd.cmd.status.zero2, UInt<1>(0h0)) node _issue_entry_T_904 = mux(issue_sel_4, entries_ld[4].bits.cmd.cmd.status.zero2, UInt<1>(0h0)) node _issue_entry_T_905 = mux(issue_sel_5, entries_ld[5].bits.cmd.cmd.status.zero2, UInt<1>(0h0)) node _issue_entry_T_906 = mux(issue_sel_6, entries_ld[6].bits.cmd.cmd.status.zero2, UInt<1>(0h0)) node _issue_entry_T_907 = mux(issue_sel_7, entries_ld[7].bits.cmd.cmd.status.zero2, UInt<1>(0h0)) node _issue_entry_T_908 = or(_issue_entry_T_900, _issue_entry_T_901) node _issue_entry_T_909 = or(_issue_entry_T_908, _issue_entry_T_902) node _issue_entry_T_910 = or(_issue_entry_T_909, _issue_entry_T_903) node _issue_entry_T_911 = or(_issue_entry_T_910, _issue_entry_T_904) node _issue_entry_T_912 = or(_issue_entry_T_911, _issue_entry_T_905) node _issue_entry_T_913 = or(_issue_entry_T_912, _issue_entry_T_906) node _issue_entry_T_914 = or(_issue_entry_T_913, _issue_entry_T_907) wire _issue_entry_WIRE_68 : UInt<23> connect _issue_entry_WIRE_68, _issue_entry_T_914 connect _issue_entry_WIRE_40.zero2, _issue_entry_WIRE_68 node _issue_entry_T_915 = mux(issue_sel_0, entries_ld[0].bits.cmd.cmd.status.sd, UInt<1>(0h0)) node _issue_entry_T_916 = mux(issue_sel_1, entries_ld[1].bits.cmd.cmd.status.sd, UInt<1>(0h0)) node _issue_entry_T_917 = mux(issue_sel_2, entries_ld[2].bits.cmd.cmd.status.sd, UInt<1>(0h0)) node _issue_entry_T_918 = mux(issue_sel_3, entries_ld[3].bits.cmd.cmd.status.sd, UInt<1>(0h0)) node _issue_entry_T_919 = mux(issue_sel_4, entries_ld[4].bits.cmd.cmd.status.sd, UInt<1>(0h0)) node _issue_entry_T_920 = mux(issue_sel_5, entries_ld[5].bits.cmd.cmd.status.sd, UInt<1>(0h0)) node _issue_entry_T_921 = mux(issue_sel_6, entries_ld[6].bits.cmd.cmd.status.sd, UInt<1>(0h0)) node _issue_entry_T_922 = mux(issue_sel_7, entries_ld[7].bits.cmd.cmd.status.sd, UInt<1>(0h0)) node _issue_entry_T_923 = or(_issue_entry_T_915, _issue_entry_T_916) node _issue_entry_T_924 = or(_issue_entry_T_923, _issue_entry_T_917) node _issue_entry_T_925 = or(_issue_entry_T_924, _issue_entry_T_918) node _issue_entry_T_926 = or(_issue_entry_T_925, _issue_entry_T_919) node _issue_entry_T_927 = or(_issue_entry_T_926, _issue_entry_T_920) node _issue_entry_T_928 = or(_issue_entry_T_927, _issue_entry_T_921) node _issue_entry_T_929 = or(_issue_entry_T_928, _issue_entry_T_922) wire _issue_entry_WIRE_69 : UInt<1> connect _issue_entry_WIRE_69, _issue_entry_T_929 connect _issue_entry_WIRE_40.sd, _issue_entry_WIRE_69 node _issue_entry_T_930 = mux(issue_sel_0, entries_ld[0].bits.cmd.cmd.status.v, UInt<1>(0h0)) node _issue_entry_T_931 = mux(issue_sel_1, entries_ld[1].bits.cmd.cmd.status.v, UInt<1>(0h0)) node _issue_entry_T_932 = mux(issue_sel_2, entries_ld[2].bits.cmd.cmd.status.v, UInt<1>(0h0)) node _issue_entry_T_933 = mux(issue_sel_3, entries_ld[3].bits.cmd.cmd.status.v, UInt<1>(0h0)) node _issue_entry_T_934 = mux(issue_sel_4, entries_ld[4].bits.cmd.cmd.status.v, UInt<1>(0h0)) node _issue_entry_T_935 = mux(issue_sel_5, entries_ld[5].bits.cmd.cmd.status.v, UInt<1>(0h0)) node _issue_entry_T_936 = mux(issue_sel_6, entries_ld[6].bits.cmd.cmd.status.v, UInt<1>(0h0)) node _issue_entry_T_937 = mux(issue_sel_7, entries_ld[7].bits.cmd.cmd.status.v, UInt<1>(0h0)) node _issue_entry_T_938 = or(_issue_entry_T_930, _issue_entry_T_931) node _issue_entry_T_939 = or(_issue_entry_T_938, _issue_entry_T_932) node _issue_entry_T_940 = or(_issue_entry_T_939, _issue_entry_T_933) node _issue_entry_T_941 = or(_issue_entry_T_940, _issue_entry_T_934) node _issue_entry_T_942 = or(_issue_entry_T_941, _issue_entry_T_935) node _issue_entry_T_943 = or(_issue_entry_T_942, _issue_entry_T_936) node _issue_entry_T_944 = or(_issue_entry_T_943, _issue_entry_T_937) wire _issue_entry_WIRE_70 : UInt<1> connect _issue_entry_WIRE_70, _issue_entry_T_944 connect _issue_entry_WIRE_40.v, _issue_entry_WIRE_70 node _issue_entry_T_945 = mux(issue_sel_0, entries_ld[0].bits.cmd.cmd.status.prv, UInt<1>(0h0)) node _issue_entry_T_946 = mux(issue_sel_1, entries_ld[1].bits.cmd.cmd.status.prv, UInt<1>(0h0)) node _issue_entry_T_947 = mux(issue_sel_2, entries_ld[2].bits.cmd.cmd.status.prv, UInt<1>(0h0)) node _issue_entry_T_948 = mux(issue_sel_3, entries_ld[3].bits.cmd.cmd.status.prv, UInt<1>(0h0)) node _issue_entry_T_949 = mux(issue_sel_4, entries_ld[4].bits.cmd.cmd.status.prv, UInt<1>(0h0)) node _issue_entry_T_950 = mux(issue_sel_5, entries_ld[5].bits.cmd.cmd.status.prv, UInt<1>(0h0)) node _issue_entry_T_951 = mux(issue_sel_6, entries_ld[6].bits.cmd.cmd.status.prv, UInt<1>(0h0)) node _issue_entry_T_952 = mux(issue_sel_7, entries_ld[7].bits.cmd.cmd.status.prv, UInt<1>(0h0)) node _issue_entry_T_953 = or(_issue_entry_T_945, _issue_entry_T_946) node _issue_entry_T_954 = or(_issue_entry_T_953, _issue_entry_T_947) node _issue_entry_T_955 = or(_issue_entry_T_954, _issue_entry_T_948) node _issue_entry_T_956 = or(_issue_entry_T_955, _issue_entry_T_949) node _issue_entry_T_957 = or(_issue_entry_T_956, _issue_entry_T_950) node _issue_entry_T_958 = or(_issue_entry_T_957, _issue_entry_T_951) node _issue_entry_T_959 = or(_issue_entry_T_958, _issue_entry_T_952) wire _issue_entry_WIRE_71 : UInt<2> connect _issue_entry_WIRE_71, _issue_entry_T_959 connect _issue_entry_WIRE_40.prv, _issue_entry_WIRE_71 node _issue_entry_T_960 = mux(issue_sel_0, entries_ld[0].bits.cmd.cmd.status.dv, UInt<1>(0h0)) node _issue_entry_T_961 = mux(issue_sel_1, entries_ld[1].bits.cmd.cmd.status.dv, UInt<1>(0h0)) node _issue_entry_T_962 = mux(issue_sel_2, entries_ld[2].bits.cmd.cmd.status.dv, UInt<1>(0h0)) node _issue_entry_T_963 = mux(issue_sel_3, entries_ld[3].bits.cmd.cmd.status.dv, UInt<1>(0h0)) node _issue_entry_T_964 = mux(issue_sel_4, entries_ld[4].bits.cmd.cmd.status.dv, UInt<1>(0h0)) node _issue_entry_T_965 = mux(issue_sel_5, entries_ld[5].bits.cmd.cmd.status.dv, UInt<1>(0h0)) node _issue_entry_T_966 = mux(issue_sel_6, entries_ld[6].bits.cmd.cmd.status.dv, UInt<1>(0h0)) node _issue_entry_T_967 = mux(issue_sel_7, entries_ld[7].bits.cmd.cmd.status.dv, UInt<1>(0h0)) node _issue_entry_T_968 = or(_issue_entry_T_960, _issue_entry_T_961) node _issue_entry_T_969 = or(_issue_entry_T_968, _issue_entry_T_962) node _issue_entry_T_970 = or(_issue_entry_T_969, _issue_entry_T_963) node _issue_entry_T_971 = or(_issue_entry_T_970, _issue_entry_T_964) node _issue_entry_T_972 = or(_issue_entry_T_971, _issue_entry_T_965) node _issue_entry_T_973 = or(_issue_entry_T_972, _issue_entry_T_966) node _issue_entry_T_974 = or(_issue_entry_T_973, _issue_entry_T_967) wire _issue_entry_WIRE_72 : UInt<1> connect _issue_entry_WIRE_72, _issue_entry_T_974 connect _issue_entry_WIRE_40.dv, _issue_entry_WIRE_72 node _issue_entry_T_975 = mux(issue_sel_0, entries_ld[0].bits.cmd.cmd.status.dprv, UInt<1>(0h0)) node _issue_entry_T_976 = mux(issue_sel_1, entries_ld[1].bits.cmd.cmd.status.dprv, UInt<1>(0h0)) node _issue_entry_T_977 = mux(issue_sel_2, entries_ld[2].bits.cmd.cmd.status.dprv, UInt<1>(0h0)) node _issue_entry_T_978 = mux(issue_sel_3, entries_ld[3].bits.cmd.cmd.status.dprv, UInt<1>(0h0)) node _issue_entry_T_979 = mux(issue_sel_4, entries_ld[4].bits.cmd.cmd.status.dprv, UInt<1>(0h0)) node _issue_entry_T_980 = mux(issue_sel_5, entries_ld[5].bits.cmd.cmd.status.dprv, UInt<1>(0h0)) node _issue_entry_T_981 = mux(issue_sel_6, entries_ld[6].bits.cmd.cmd.status.dprv, UInt<1>(0h0)) node _issue_entry_T_982 = mux(issue_sel_7, entries_ld[7].bits.cmd.cmd.status.dprv, UInt<1>(0h0)) node _issue_entry_T_983 = or(_issue_entry_T_975, _issue_entry_T_976) node _issue_entry_T_984 = or(_issue_entry_T_983, _issue_entry_T_977) node _issue_entry_T_985 = or(_issue_entry_T_984, _issue_entry_T_978) node _issue_entry_T_986 = or(_issue_entry_T_985, _issue_entry_T_979) node _issue_entry_T_987 = or(_issue_entry_T_986, _issue_entry_T_980) node _issue_entry_T_988 = or(_issue_entry_T_987, _issue_entry_T_981) node _issue_entry_T_989 = or(_issue_entry_T_988, _issue_entry_T_982) wire _issue_entry_WIRE_73 : UInt<2> connect _issue_entry_WIRE_73, _issue_entry_T_989 connect _issue_entry_WIRE_40.dprv, _issue_entry_WIRE_73 node _issue_entry_T_990 = mux(issue_sel_0, entries_ld[0].bits.cmd.cmd.status.isa, UInt<1>(0h0)) node _issue_entry_T_991 = mux(issue_sel_1, entries_ld[1].bits.cmd.cmd.status.isa, UInt<1>(0h0)) node _issue_entry_T_992 = mux(issue_sel_2, entries_ld[2].bits.cmd.cmd.status.isa, UInt<1>(0h0)) node _issue_entry_T_993 = mux(issue_sel_3, entries_ld[3].bits.cmd.cmd.status.isa, UInt<1>(0h0)) node _issue_entry_T_994 = mux(issue_sel_4, entries_ld[4].bits.cmd.cmd.status.isa, UInt<1>(0h0)) node _issue_entry_T_995 = mux(issue_sel_5, entries_ld[5].bits.cmd.cmd.status.isa, UInt<1>(0h0)) node _issue_entry_T_996 = mux(issue_sel_6, entries_ld[6].bits.cmd.cmd.status.isa, UInt<1>(0h0)) node _issue_entry_T_997 = mux(issue_sel_7, entries_ld[7].bits.cmd.cmd.status.isa, UInt<1>(0h0)) node _issue_entry_T_998 = or(_issue_entry_T_990, _issue_entry_T_991) node _issue_entry_T_999 = or(_issue_entry_T_998, _issue_entry_T_992) node _issue_entry_T_1000 = or(_issue_entry_T_999, _issue_entry_T_993) node _issue_entry_T_1001 = or(_issue_entry_T_1000, _issue_entry_T_994) node _issue_entry_T_1002 = or(_issue_entry_T_1001, _issue_entry_T_995) node _issue_entry_T_1003 = or(_issue_entry_T_1002, _issue_entry_T_996) node _issue_entry_T_1004 = or(_issue_entry_T_1003, _issue_entry_T_997) wire _issue_entry_WIRE_74 : UInt<32> connect _issue_entry_WIRE_74, _issue_entry_T_1004 connect _issue_entry_WIRE_40.isa, _issue_entry_WIRE_74 node _issue_entry_T_1005 = mux(issue_sel_0, entries_ld[0].bits.cmd.cmd.status.wfi, UInt<1>(0h0)) node _issue_entry_T_1006 = mux(issue_sel_1, entries_ld[1].bits.cmd.cmd.status.wfi, UInt<1>(0h0)) node _issue_entry_T_1007 = mux(issue_sel_2, entries_ld[2].bits.cmd.cmd.status.wfi, UInt<1>(0h0)) node _issue_entry_T_1008 = mux(issue_sel_3, entries_ld[3].bits.cmd.cmd.status.wfi, UInt<1>(0h0)) node _issue_entry_T_1009 = mux(issue_sel_4, entries_ld[4].bits.cmd.cmd.status.wfi, UInt<1>(0h0)) node _issue_entry_T_1010 = mux(issue_sel_5, entries_ld[5].bits.cmd.cmd.status.wfi, UInt<1>(0h0)) node _issue_entry_T_1011 = mux(issue_sel_6, entries_ld[6].bits.cmd.cmd.status.wfi, UInt<1>(0h0)) node _issue_entry_T_1012 = mux(issue_sel_7, entries_ld[7].bits.cmd.cmd.status.wfi, UInt<1>(0h0)) node _issue_entry_T_1013 = or(_issue_entry_T_1005, _issue_entry_T_1006) node _issue_entry_T_1014 = or(_issue_entry_T_1013, _issue_entry_T_1007) node _issue_entry_T_1015 = or(_issue_entry_T_1014, _issue_entry_T_1008) node _issue_entry_T_1016 = or(_issue_entry_T_1015, _issue_entry_T_1009) node _issue_entry_T_1017 = or(_issue_entry_T_1016, _issue_entry_T_1010) node _issue_entry_T_1018 = or(_issue_entry_T_1017, _issue_entry_T_1011) node _issue_entry_T_1019 = or(_issue_entry_T_1018, _issue_entry_T_1012) wire _issue_entry_WIRE_75 : UInt<1> connect _issue_entry_WIRE_75, _issue_entry_T_1019 connect _issue_entry_WIRE_40.wfi, _issue_entry_WIRE_75 node _issue_entry_T_1020 = mux(issue_sel_0, entries_ld[0].bits.cmd.cmd.status.cease, UInt<1>(0h0)) node _issue_entry_T_1021 = mux(issue_sel_1, entries_ld[1].bits.cmd.cmd.status.cease, UInt<1>(0h0)) node _issue_entry_T_1022 = mux(issue_sel_2, entries_ld[2].bits.cmd.cmd.status.cease, UInt<1>(0h0)) node _issue_entry_T_1023 = mux(issue_sel_3, entries_ld[3].bits.cmd.cmd.status.cease, UInt<1>(0h0)) node _issue_entry_T_1024 = mux(issue_sel_4, entries_ld[4].bits.cmd.cmd.status.cease, UInt<1>(0h0)) node _issue_entry_T_1025 = mux(issue_sel_5, entries_ld[5].bits.cmd.cmd.status.cease, UInt<1>(0h0)) node _issue_entry_T_1026 = mux(issue_sel_6, entries_ld[6].bits.cmd.cmd.status.cease, UInt<1>(0h0)) node _issue_entry_T_1027 = mux(issue_sel_7, entries_ld[7].bits.cmd.cmd.status.cease, UInt<1>(0h0)) node _issue_entry_T_1028 = or(_issue_entry_T_1020, _issue_entry_T_1021) node _issue_entry_T_1029 = or(_issue_entry_T_1028, _issue_entry_T_1022) node _issue_entry_T_1030 = or(_issue_entry_T_1029, _issue_entry_T_1023) node _issue_entry_T_1031 = or(_issue_entry_T_1030, _issue_entry_T_1024) node _issue_entry_T_1032 = or(_issue_entry_T_1031, _issue_entry_T_1025) node _issue_entry_T_1033 = or(_issue_entry_T_1032, _issue_entry_T_1026) node _issue_entry_T_1034 = or(_issue_entry_T_1033, _issue_entry_T_1027) wire _issue_entry_WIRE_76 : UInt<1> connect _issue_entry_WIRE_76, _issue_entry_T_1034 connect _issue_entry_WIRE_40.cease, _issue_entry_WIRE_76 node _issue_entry_T_1035 = mux(issue_sel_0, entries_ld[0].bits.cmd.cmd.status.debug, UInt<1>(0h0)) node _issue_entry_T_1036 = mux(issue_sel_1, entries_ld[1].bits.cmd.cmd.status.debug, UInt<1>(0h0)) node _issue_entry_T_1037 = mux(issue_sel_2, entries_ld[2].bits.cmd.cmd.status.debug, UInt<1>(0h0)) node _issue_entry_T_1038 = mux(issue_sel_3, entries_ld[3].bits.cmd.cmd.status.debug, UInt<1>(0h0)) node _issue_entry_T_1039 = mux(issue_sel_4, entries_ld[4].bits.cmd.cmd.status.debug, UInt<1>(0h0)) node _issue_entry_T_1040 = mux(issue_sel_5, entries_ld[5].bits.cmd.cmd.status.debug, UInt<1>(0h0)) node _issue_entry_T_1041 = mux(issue_sel_6, entries_ld[6].bits.cmd.cmd.status.debug, UInt<1>(0h0)) node _issue_entry_T_1042 = mux(issue_sel_7, entries_ld[7].bits.cmd.cmd.status.debug, UInt<1>(0h0)) node _issue_entry_T_1043 = or(_issue_entry_T_1035, _issue_entry_T_1036) node _issue_entry_T_1044 = or(_issue_entry_T_1043, _issue_entry_T_1037) node _issue_entry_T_1045 = or(_issue_entry_T_1044, _issue_entry_T_1038) node _issue_entry_T_1046 = or(_issue_entry_T_1045, _issue_entry_T_1039) node _issue_entry_T_1047 = or(_issue_entry_T_1046, _issue_entry_T_1040) node _issue_entry_T_1048 = or(_issue_entry_T_1047, _issue_entry_T_1041) node _issue_entry_T_1049 = or(_issue_entry_T_1048, _issue_entry_T_1042) wire _issue_entry_WIRE_77 : UInt<1> connect _issue_entry_WIRE_77, _issue_entry_T_1049 connect _issue_entry_WIRE_40.debug, _issue_entry_WIRE_77 connect _issue_entry_WIRE_39.status, _issue_entry_WIRE_40 node _issue_entry_T_1050 = mux(issue_sel_0, entries_ld[0].bits.cmd.cmd.rs2, UInt<1>(0h0)) node _issue_entry_T_1051 = mux(issue_sel_1, entries_ld[1].bits.cmd.cmd.rs2, UInt<1>(0h0)) node _issue_entry_T_1052 = mux(issue_sel_2, entries_ld[2].bits.cmd.cmd.rs2, UInt<1>(0h0)) node _issue_entry_T_1053 = mux(issue_sel_3, entries_ld[3].bits.cmd.cmd.rs2, UInt<1>(0h0)) node _issue_entry_T_1054 = mux(issue_sel_4, entries_ld[4].bits.cmd.cmd.rs2, UInt<1>(0h0)) node _issue_entry_T_1055 = mux(issue_sel_5, entries_ld[5].bits.cmd.cmd.rs2, UInt<1>(0h0)) node _issue_entry_T_1056 = mux(issue_sel_6, entries_ld[6].bits.cmd.cmd.rs2, UInt<1>(0h0)) node _issue_entry_T_1057 = mux(issue_sel_7, entries_ld[7].bits.cmd.cmd.rs2, UInt<1>(0h0)) node _issue_entry_T_1058 = or(_issue_entry_T_1050, _issue_entry_T_1051) node _issue_entry_T_1059 = or(_issue_entry_T_1058, _issue_entry_T_1052) node _issue_entry_T_1060 = or(_issue_entry_T_1059, _issue_entry_T_1053) node _issue_entry_T_1061 = or(_issue_entry_T_1060, _issue_entry_T_1054) node _issue_entry_T_1062 = or(_issue_entry_T_1061, _issue_entry_T_1055) node _issue_entry_T_1063 = or(_issue_entry_T_1062, _issue_entry_T_1056) node _issue_entry_T_1064 = or(_issue_entry_T_1063, _issue_entry_T_1057) wire _issue_entry_WIRE_78 : UInt<64> connect _issue_entry_WIRE_78, _issue_entry_T_1064 connect _issue_entry_WIRE_39.rs2, _issue_entry_WIRE_78 node _issue_entry_T_1065 = mux(issue_sel_0, entries_ld[0].bits.cmd.cmd.rs1, UInt<1>(0h0)) node _issue_entry_T_1066 = mux(issue_sel_1, entries_ld[1].bits.cmd.cmd.rs1, UInt<1>(0h0)) node _issue_entry_T_1067 = mux(issue_sel_2, entries_ld[2].bits.cmd.cmd.rs1, UInt<1>(0h0)) node _issue_entry_T_1068 = mux(issue_sel_3, entries_ld[3].bits.cmd.cmd.rs1, UInt<1>(0h0)) node _issue_entry_T_1069 = mux(issue_sel_4, entries_ld[4].bits.cmd.cmd.rs1, UInt<1>(0h0)) node _issue_entry_T_1070 = mux(issue_sel_5, entries_ld[5].bits.cmd.cmd.rs1, UInt<1>(0h0)) node _issue_entry_T_1071 = mux(issue_sel_6, entries_ld[6].bits.cmd.cmd.rs1, UInt<1>(0h0)) node _issue_entry_T_1072 = mux(issue_sel_7, entries_ld[7].bits.cmd.cmd.rs1, UInt<1>(0h0)) node _issue_entry_T_1073 = or(_issue_entry_T_1065, _issue_entry_T_1066) node _issue_entry_T_1074 = or(_issue_entry_T_1073, _issue_entry_T_1067) node _issue_entry_T_1075 = or(_issue_entry_T_1074, _issue_entry_T_1068) node _issue_entry_T_1076 = or(_issue_entry_T_1075, _issue_entry_T_1069) node _issue_entry_T_1077 = or(_issue_entry_T_1076, _issue_entry_T_1070) node _issue_entry_T_1078 = or(_issue_entry_T_1077, _issue_entry_T_1071) node _issue_entry_T_1079 = or(_issue_entry_T_1078, _issue_entry_T_1072) wire _issue_entry_WIRE_79 : UInt<64> connect _issue_entry_WIRE_79, _issue_entry_T_1079 connect _issue_entry_WIRE_39.rs1, _issue_entry_WIRE_79 wire _issue_entry_WIRE_80 : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>} node _issue_entry_T_1080 = mux(issue_sel_0, entries_ld[0].bits.cmd.cmd.inst.opcode, UInt<1>(0h0)) node _issue_entry_T_1081 = mux(issue_sel_1, entries_ld[1].bits.cmd.cmd.inst.opcode, UInt<1>(0h0)) node _issue_entry_T_1082 = mux(issue_sel_2, entries_ld[2].bits.cmd.cmd.inst.opcode, UInt<1>(0h0)) node _issue_entry_T_1083 = mux(issue_sel_3, entries_ld[3].bits.cmd.cmd.inst.opcode, UInt<1>(0h0)) node _issue_entry_T_1084 = mux(issue_sel_4, entries_ld[4].bits.cmd.cmd.inst.opcode, UInt<1>(0h0)) node _issue_entry_T_1085 = mux(issue_sel_5, entries_ld[5].bits.cmd.cmd.inst.opcode, UInt<1>(0h0)) node _issue_entry_T_1086 = mux(issue_sel_6, entries_ld[6].bits.cmd.cmd.inst.opcode, UInt<1>(0h0)) node _issue_entry_T_1087 = mux(issue_sel_7, entries_ld[7].bits.cmd.cmd.inst.opcode, UInt<1>(0h0)) node _issue_entry_T_1088 = or(_issue_entry_T_1080, _issue_entry_T_1081) node _issue_entry_T_1089 = or(_issue_entry_T_1088, _issue_entry_T_1082) node _issue_entry_T_1090 = or(_issue_entry_T_1089, _issue_entry_T_1083) node _issue_entry_T_1091 = or(_issue_entry_T_1090, _issue_entry_T_1084) node _issue_entry_T_1092 = or(_issue_entry_T_1091, _issue_entry_T_1085) node _issue_entry_T_1093 = or(_issue_entry_T_1092, _issue_entry_T_1086) node _issue_entry_T_1094 = or(_issue_entry_T_1093, _issue_entry_T_1087) wire _issue_entry_WIRE_81 : UInt<7> connect _issue_entry_WIRE_81, _issue_entry_T_1094 connect _issue_entry_WIRE_80.opcode, _issue_entry_WIRE_81 node _issue_entry_T_1095 = mux(issue_sel_0, entries_ld[0].bits.cmd.cmd.inst.rd, UInt<1>(0h0)) node _issue_entry_T_1096 = mux(issue_sel_1, entries_ld[1].bits.cmd.cmd.inst.rd, UInt<1>(0h0)) node _issue_entry_T_1097 = mux(issue_sel_2, entries_ld[2].bits.cmd.cmd.inst.rd, UInt<1>(0h0)) node _issue_entry_T_1098 = mux(issue_sel_3, entries_ld[3].bits.cmd.cmd.inst.rd, UInt<1>(0h0)) node _issue_entry_T_1099 = mux(issue_sel_4, entries_ld[4].bits.cmd.cmd.inst.rd, UInt<1>(0h0)) node _issue_entry_T_1100 = mux(issue_sel_5, entries_ld[5].bits.cmd.cmd.inst.rd, UInt<1>(0h0)) node _issue_entry_T_1101 = mux(issue_sel_6, entries_ld[6].bits.cmd.cmd.inst.rd, UInt<1>(0h0)) node _issue_entry_T_1102 = mux(issue_sel_7, entries_ld[7].bits.cmd.cmd.inst.rd, UInt<1>(0h0)) node _issue_entry_T_1103 = or(_issue_entry_T_1095, _issue_entry_T_1096) node _issue_entry_T_1104 = or(_issue_entry_T_1103, _issue_entry_T_1097) node _issue_entry_T_1105 = or(_issue_entry_T_1104, _issue_entry_T_1098) node _issue_entry_T_1106 = or(_issue_entry_T_1105, _issue_entry_T_1099) node _issue_entry_T_1107 = or(_issue_entry_T_1106, _issue_entry_T_1100) node _issue_entry_T_1108 = or(_issue_entry_T_1107, _issue_entry_T_1101) node _issue_entry_T_1109 = or(_issue_entry_T_1108, _issue_entry_T_1102) wire _issue_entry_WIRE_82 : UInt<5> connect _issue_entry_WIRE_82, _issue_entry_T_1109 connect _issue_entry_WIRE_80.rd, _issue_entry_WIRE_82 node _issue_entry_T_1110 = mux(issue_sel_0, entries_ld[0].bits.cmd.cmd.inst.xs2, UInt<1>(0h0)) node _issue_entry_T_1111 = mux(issue_sel_1, entries_ld[1].bits.cmd.cmd.inst.xs2, UInt<1>(0h0)) node _issue_entry_T_1112 = mux(issue_sel_2, entries_ld[2].bits.cmd.cmd.inst.xs2, UInt<1>(0h0)) node _issue_entry_T_1113 = mux(issue_sel_3, entries_ld[3].bits.cmd.cmd.inst.xs2, UInt<1>(0h0)) node _issue_entry_T_1114 = mux(issue_sel_4, entries_ld[4].bits.cmd.cmd.inst.xs2, UInt<1>(0h0)) node _issue_entry_T_1115 = mux(issue_sel_5, entries_ld[5].bits.cmd.cmd.inst.xs2, UInt<1>(0h0)) node _issue_entry_T_1116 = mux(issue_sel_6, entries_ld[6].bits.cmd.cmd.inst.xs2, UInt<1>(0h0)) node _issue_entry_T_1117 = mux(issue_sel_7, entries_ld[7].bits.cmd.cmd.inst.xs2, UInt<1>(0h0)) node _issue_entry_T_1118 = or(_issue_entry_T_1110, _issue_entry_T_1111) node _issue_entry_T_1119 = or(_issue_entry_T_1118, _issue_entry_T_1112) node _issue_entry_T_1120 = or(_issue_entry_T_1119, _issue_entry_T_1113) node _issue_entry_T_1121 = or(_issue_entry_T_1120, _issue_entry_T_1114) node _issue_entry_T_1122 = or(_issue_entry_T_1121, _issue_entry_T_1115) node _issue_entry_T_1123 = or(_issue_entry_T_1122, _issue_entry_T_1116) node _issue_entry_T_1124 = or(_issue_entry_T_1123, _issue_entry_T_1117) wire _issue_entry_WIRE_83 : UInt<1> connect _issue_entry_WIRE_83, _issue_entry_T_1124 connect _issue_entry_WIRE_80.xs2, _issue_entry_WIRE_83 node _issue_entry_T_1125 = mux(issue_sel_0, entries_ld[0].bits.cmd.cmd.inst.xs1, UInt<1>(0h0)) node _issue_entry_T_1126 = mux(issue_sel_1, entries_ld[1].bits.cmd.cmd.inst.xs1, UInt<1>(0h0)) node _issue_entry_T_1127 = mux(issue_sel_2, entries_ld[2].bits.cmd.cmd.inst.xs1, UInt<1>(0h0)) node _issue_entry_T_1128 = mux(issue_sel_3, entries_ld[3].bits.cmd.cmd.inst.xs1, UInt<1>(0h0)) node _issue_entry_T_1129 = mux(issue_sel_4, entries_ld[4].bits.cmd.cmd.inst.xs1, UInt<1>(0h0)) node _issue_entry_T_1130 = mux(issue_sel_5, entries_ld[5].bits.cmd.cmd.inst.xs1, UInt<1>(0h0)) node _issue_entry_T_1131 = mux(issue_sel_6, entries_ld[6].bits.cmd.cmd.inst.xs1, UInt<1>(0h0)) node _issue_entry_T_1132 = mux(issue_sel_7, entries_ld[7].bits.cmd.cmd.inst.xs1, UInt<1>(0h0)) node _issue_entry_T_1133 = or(_issue_entry_T_1125, _issue_entry_T_1126) node _issue_entry_T_1134 = or(_issue_entry_T_1133, _issue_entry_T_1127) node _issue_entry_T_1135 = or(_issue_entry_T_1134, _issue_entry_T_1128) node _issue_entry_T_1136 = or(_issue_entry_T_1135, _issue_entry_T_1129) node _issue_entry_T_1137 = or(_issue_entry_T_1136, _issue_entry_T_1130) node _issue_entry_T_1138 = or(_issue_entry_T_1137, _issue_entry_T_1131) node _issue_entry_T_1139 = or(_issue_entry_T_1138, _issue_entry_T_1132) wire _issue_entry_WIRE_84 : UInt<1> connect _issue_entry_WIRE_84, _issue_entry_T_1139 connect _issue_entry_WIRE_80.xs1, _issue_entry_WIRE_84 node _issue_entry_T_1140 = mux(issue_sel_0, entries_ld[0].bits.cmd.cmd.inst.xd, UInt<1>(0h0)) node _issue_entry_T_1141 = mux(issue_sel_1, entries_ld[1].bits.cmd.cmd.inst.xd, UInt<1>(0h0)) node _issue_entry_T_1142 = mux(issue_sel_2, entries_ld[2].bits.cmd.cmd.inst.xd, UInt<1>(0h0)) node _issue_entry_T_1143 = mux(issue_sel_3, entries_ld[3].bits.cmd.cmd.inst.xd, UInt<1>(0h0)) node _issue_entry_T_1144 = mux(issue_sel_4, entries_ld[4].bits.cmd.cmd.inst.xd, UInt<1>(0h0)) node _issue_entry_T_1145 = mux(issue_sel_5, entries_ld[5].bits.cmd.cmd.inst.xd, UInt<1>(0h0)) node _issue_entry_T_1146 = mux(issue_sel_6, entries_ld[6].bits.cmd.cmd.inst.xd, UInt<1>(0h0)) node _issue_entry_T_1147 = mux(issue_sel_7, entries_ld[7].bits.cmd.cmd.inst.xd, UInt<1>(0h0)) node _issue_entry_T_1148 = or(_issue_entry_T_1140, _issue_entry_T_1141) node _issue_entry_T_1149 = or(_issue_entry_T_1148, _issue_entry_T_1142) node _issue_entry_T_1150 = or(_issue_entry_T_1149, _issue_entry_T_1143) node _issue_entry_T_1151 = or(_issue_entry_T_1150, _issue_entry_T_1144) node _issue_entry_T_1152 = or(_issue_entry_T_1151, _issue_entry_T_1145) node _issue_entry_T_1153 = or(_issue_entry_T_1152, _issue_entry_T_1146) node _issue_entry_T_1154 = or(_issue_entry_T_1153, _issue_entry_T_1147) wire _issue_entry_WIRE_85 : UInt<1> connect _issue_entry_WIRE_85, _issue_entry_T_1154 connect _issue_entry_WIRE_80.xd, _issue_entry_WIRE_85 node _issue_entry_T_1155 = mux(issue_sel_0, entries_ld[0].bits.cmd.cmd.inst.rs1, UInt<1>(0h0)) node _issue_entry_T_1156 = mux(issue_sel_1, entries_ld[1].bits.cmd.cmd.inst.rs1, UInt<1>(0h0)) node _issue_entry_T_1157 = mux(issue_sel_2, entries_ld[2].bits.cmd.cmd.inst.rs1, UInt<1>(0h0)) node _issue_entry_T_1158 = mux(issue_sel_3, entries_ld[3].bits.cmd.cmd.inst.rs1, UInt<1>(0h0)) node _issue_entry_T_1159 = mux(issue_sel_4, entries_ld[4].bits.cmd.cmd.inst.rs1, UInt<1>(0h0)) node _issue_entry_T_1160 = mux(issue_sel_5, entries_ld[5].bits.cmd.cmd.inst.rs1, UInt<1>(0h0)) node _issue_entry_T_1161 = mux(issue_sel_6, entries_ld[6].bits.cmd.cmd.inst.rs1, UInt<1>(0h0)) node _issue_entry_T_1162 = mux(issue_sel_7, entries_ld[7].bits.cmd.cmd.inst.rs1, UInt<1>(0h0)) node _issue_entry_T_1163 = or(_issue_entry_T_1155, _issue_entry_T_1156) node _issue_entry_T_1164 = or(_issue_entry_T_1163, _issue_entry_T_1157) node _issue_entry_T_1165 = or(_issue_entry_T_1164, _issue_entry_T_1158) node _issue_entry_T_1166 = or(_issue_entry_T_1165, _issue_entry_T_1159) node _issue_entry_T_1167 = or(_issue_entry_T_1166, _issue_entry_T_1160) node _issue_entry_T_1168 = or(_issue_entry_T_1167, _issue_entry_T_1161) node _issue_entry_T_1169 = or(_issue_entry_T_1168, _issue_entry_T_1162) wire _issue_entry_WIRE_86 : UInt<5> connect _issue_entry_WIRE_86, _issue_entry_T_1169 connect _issue_entry_WIRE_80.rs1, _issue_entry_WIRE_86 node _issue_entry_T_1170 = mux(issue_sel_0, entries_ld[0].bits.cmd.cmd.inst.rs2, UInt<1>(0h0)) node _issue_entry_T_1171 = mux(issue_sel_1, entries_ld[1].bits.cmd.cmd.inst.rs2, UInt<1>(0h0)) node _issue_entry_T_1172 = mux(issue_sel_2, entries_ld[2].bits.cmd.cmd.inst.rs2, UInt<1>(0h0)) node _issue_entry_T_1173 = mux(issue_sel_3, entries_ld[3].bits.cmd.cmd.inst.rs2, UInt<1>(0h0)) node _issue_entry_T_1174 = mux(issue_sel_4, entries_ld[4].bits.cmd.cmd.inst.rs2, UInt<1>(0h0)) node _issue_entry_T_1175 = mux(issue_sel_5, entries_ld[5].bits.cmd.cmd.inst.rs2, UInt<1>(0h0)) node _issue_entry_T_1176 = mux(issue_sel_6, entries_ld[6].bits.cmd.cmd.inst.rs2, UInt<1>(0h0)) node _issue_entry_T_1177 = mux(issue_sel_7, entries_ld[7].bits.cmd.cmd.inst.rs2, UInt<1>(0h0)) node _issue_entry_T_1178 = or(_issue_entry_T_1170, _issue_entry_T_1171) node _issue_entry_T_1179 = or(_issue_entry_T_1178, _issue_entry_T_1172) node _issue_entry_T_1180 = or(_issue_entry_T_1179, _issue_entry_T_1173) node _issue_entry_T_1181 = or(_issue_entry_T_1180, _issue_entry_T_1174) node _issue_entry_T_1182 = or(_issue_entry_T_1181, _issue_entry_T_1175) node _issue_entry_T_1183 = or(_issue_entry_T_1182, _issue_entry_T_1176) node _issue_entry_T_1184 = or(_issue_entry_T_1183, _issue_entry_T_1177) wire _issue_entry_WIRE_87 : UInt<5> connect _issue_entry_WIRE_87, _issue_entry_T_1184 connect _issue_entry_WIRE_80.rs2, _issue_entry_WIRE_87 node _issue_entry_T_1185 = mux(issue_sel_0, entries_ld[0].bits.cmd.cmd.inst.funct, UInt<1>(0h0)) node _issue_entry_T_1186 = mux(issue_sel_1, entries_ld[1].bits.cmd.cmd.inst.funct, UInt<1>(0h0)) node _issue_entry_T_1187 = mux(issue_sel_2, entries_ld[2].bits.cmd.cmd.inst.funct, UInt<1>(0h0)) node _issue_entry_T_1188 = mux(issue_sel_3, entries_ld[3].bits.cmd.cmd.inst.funct, UInt<1>(0h0)) node _issue_entry_T_1189 = mux(issue_sel_4, entries_ld[4].bits.cmd.cmd.inst.funct, UInt<1>(0h0)) node _issue_entry_T_1190 = mux(issue_sel_5, entries_ld[5].bits.cmd.cmd.inst.funct, UInt<1>(0h0)) node _issue_entry_T_1191 = mux(issue_sel_6, entries_ld[6].bits.cmd.cmd.inst.funct, UInt<1>(0h0)) node _issue_entry_T_1192 = mux(issue_sel_7, entries_ld[7].bits.cmd.cmd.inst.funct, UInt<1>(0h0)) node _issue_entry_T_1193 = or(_issue_entry_T_1185, _issue_entry_T_1186) node _issue_entry_T_1194 = or(_issue_entry_T_1193, _issue_entry_T_1187) node _issue_entry_T_1195 = or(_issue_entry_T_1194, _issue_entry_T_1188) node _issue_entry_T_1196 = or(_issue_entry_T_1195, _issue_entry_T_1189) node _issue_entry_T_1197 = or(_issue_entry_T_1196, _issue_entry_T_1190) node _issue_entry_T_1198 = or(_issue_entry_T_1197, _issue_entry_T_1191) node _issue_entry_T_1199 = or(_issue_entry_T_1198, _issue_entry_T_1192) wire _issue_entry_WIRE_88 : UInt<7> connect _issue_entry_WIRE_88, _issue_entry_T_1199 connect _issue_entry_WIRE_80.funct, _issue_entry_WIRE_88 connect _issue_entry_WIRE_39.inst, _issue_entry_WIRE_80 connect _issue_entry_WIRE_33.cmd, _issue_entry_WIRE_39 connect _issue_entry_WIRE.cmd, _issue_entry_WIRE_33 node _issue_entry_T_1200 = mux(issue_sel_0, entries_ld[0].bits.complete_on_issue, UInt<1>(0h0)) node _issue_entry_T_1201 = mux(issue_sel_1, entries_ld[1].bits.complete_on_issue, UInt<1>(0h0)) node _issue_entry_T_1202 = mux(issue_sel_2, entries_ld[2].bits.complete_on_issue, UInt<1>(0h0)) node _issue_entry_T_1203 = mux(issue_sel_3, entries_ld[3].bits.complete_on_issue, UInt<1>(0h0)) node _issue_entry_T_1204 = mux(issue_sel_4, entries_ld[4].bits.complete_on_issue, UInt<1>(0h0)) node _issue_entry_T_1205 = mux(issue_sel_5, entries_ld[5].bits.complete_on_issue, UInt<1>(0h0)) node _issue_entry_T_1206 = mux(issue_sel_6, entries_ld[6].bits.complete_on_issue, UInt<1>(0h0)) node _issue_entry_T_1207 = mux(issue_sel_7, entries_ld[7].bits.complete_on_issue, UInt<1>(0h0)) node _issue_entry_T_1208 = or(_issue_entry_T_1200, _issue_entry_T_1201) node _issue_entry_T_1209 = or(_issue_entry_T_1208, _issue_entry_T_1202) node _issue_entry_T_1210 = or(_issue_entry_T_1209, _issue_entry_T_1203) node _issue_entry_T_1211 = or(_issue_entry_T_1210, _issue_entry_T_1204) node _issue_entry_T_1212 = or(_issue_entry_T_1211, _issue_entry_T_1205) node _issue_entry_T_1213 = or(_issue_entry_T_1212, _issue_entry_T_1206) node _issue_entry_T_1214 = or(_issue_entry_T_1213, _issue_entry_T_1207) wire _issue_entry_WIRE_89 : UInt<1> connect _issue_entry_WIRE_89, _issue_entry_T_1214 connect _issue_entry_WIRE.complete_on_issue, _issue_entry_WIRE_89 node _issue_entry_T_1215 = mux(issue_sel_0, entries_ld[0].bits.issued, UInt<1>(0h0)) node _issue_entry_T_1216 = mux(issue_sel_1, entries_ld[1].bits.issued, UInt<1>(0h0)) node _issue_entry_T_1217 = mux(issue_sel_2, entries_ld[2].bits.issued, UInt<1>(0h0)) node _issue_entry_T_1218 = mux(issue_sel_3, entries_ld[3].bits.issued, UInt<1>(0h0)) node _issue_entry_T_1219 = mux(issue_sel_4, entries_ld[4].bits.issued, UInt<1>(0h0)) node _issue_entry_T_1220 = mux(issue_sel_5, entries_ld[5].bits.issued, UInt<1>(0h0)) node _issue_entry_T_1221 = mux(issue_sel_6, entries_ld[6].bits.issued, UInt<1>(0h0)) node _issue_entry_T_1222 = mux(issue_sel_7, entries_ld[7].bits.issued, UInt<1>(0h0)) node _issue_entry_T_1223 = or(_issue_entry_T_1215, _issue_entry_T_1216) node _issue_entry_T_1224 = or(_issue_entry_T_1223, _issue_entry_T_1217) node _issue_entry_T_1225 = or(_issue_entry_T_1224, _issue_entry_T_1218) node _issue_entry_T_1226 = or(_issue_entry_T_1225, _issue_entry_T_1219) node _issue_entry_T_1227 = or(_issue_entry_T_1226, _issue_entry_T_1220) node _issue_entry_T_1228 = or(_issue_entry_T_1227, _issue_entry_T_1221) node _issue_entry_T_1229 = or(_issue_entry_T_1228, _issue_entry_T_1222) wire _issue_entry_WIRE_90 : UInt<1> connect _issue_entry_WIRE_90, _issue_entry_T_1229 connect _issue_entry_WIRE.issued, _issue_entry_WIRE_90 wire _issue_entry_WIRE_91 : { valid : UInt<1>, bits : { start : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, end : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, wraps_around : UInt<1>}} wire _issue_entry_WIRE_92 : { start : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, end : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, wraps_around : UInt<1>} node _issue_entry_T_1230 = mux(issue_sel_0, entries_ld[0].bits.opb.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_1231 = mux(issue_sel_1, entries_ld[1].bits.opb.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_1232 = mux(issue_sel_2, entries_ld[2].bits.opb.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_1233 = mux(issue_sel_3, entries_ld[3].bits.opb.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_1234 = mux(issue_sel_4, entries_ld[4].bits.opb.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_1235 = mux(issue_sel_5, entries_ld[5].bits.opb.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_1236 = mux(issue_sel_6, entries_ld[6].bits.opb.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_1237 = mux(issue_sel_7, entries_ld[7].bits.opb.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_1238 = or(_issue_entry_T_1230, _issue_entry_T_1231) node _issue_entry_T_1239 = or(_issue_entry_T_1238, _issue_entry_T_1232) node _issue_entry_T_1240 = or(_issue_entry_T_1239, _issue_entry_T_1233) node _issue_entry_T_1241 = or(_issue_entry_T_1240, _issue_entry_T_1234) node _issue_entry_T_1242 = or(_issue_entry_T_1241, _issue_entry_T_1235) node _issue_entry_T_1243 = or(_issue_entry_T_1242, _issue_entry_T_1236) node _issue_entry_T_1244 = or(_issue_entry_T_1243, _issue_entry_T_1237) wire _issue_entry_WIRE_93 : UInt<1> connect _issue_entry_WIRE_93, _issue_entry_T_1244 connect _issue_entry_WIRE_92.wraps_around, _issue_entry_WIRE_93 wire _issue_entry_WIRE_94 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} node _issue_entry_T_1245 = mux(issue_sel_0, entries_ld[0].bits.opb.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_1246 = mux(issue_sel_1, entries_ld[1].bits.opb.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_1247 = mux(issue_sel_2, entries_ld[2].bits.opb.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_1248 = mux(issue_sel_3, entries_ld[3].bits.opb.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_1249 = mux(issue_sel_4, entries_ld[4].bits.opb.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_1250 = mux(issue_sel_5, entries_ld[5].bits.opb.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_1251 = mux(issue_sel_6, entries_ld[6].bits.opb.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_1252 = mux(issue_sel_7, entries_ld[7].bits.opb.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_1253 = or(_issue_entry_T_1245, _issue_entry_T_1246) node _issue_entry_T_1254 = or(_issue_entry_T_1253, _issue_entry_T_1247) node _issue_entry_T_1255 = or(_issue_entry_T_1254, _issue_entry_T_1248) node _issue_entry_T_1256 = or(_issue_entry_T_1255, _issue_entry_T_1249) node _issue_entry_T_1257 = or(_issue_entry_T_1256, _issue_entry_T_1250) node _issue_entry_T_1258 = or(_issue_entry_T_1257, _issue_entry_T_1251) node _issue_entry_T_1259 = or(_issue_entry_T_1258, _issue_entry_T_1252) wire _issue_entry_WIRE_95 : UInt<14> connect _issue_entry_WIRE_95, _issue_entry_T_1259 connect _issue_entry_WIRE_94.data, _issue_entry_WIRE_95 node _issue_entry_T_1260 = mux(issue_sel_0, entries_ld[0].bits.opb.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_1261 = mux(issue_sel_1, entries_ld[1].bits.opb.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_1262 = mux(issue_sel_2, entries_ld[2].bits.opb.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_1263 = mux(issue_sel_3, entries_ld[3].bits.opb.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_1264 = mux(issue_sel_4, entries_ld[4].bits.opb.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_1265 = mux(issue_sel_5, entries_ld[5].bits.opb.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_1266 = mux(issue_sel_6, entries_ld[6].bits.opb.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_1267 = mux(issue_sel_7, entries_ld[7].bits.opb.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_1268 = or(_issue_entry_T_1260, _issue_entry_T_1261) node _issue_entry_T_1269 = or(_issue_entry_T_1268, _issue_entry_T_1262) node _issue_entry_T_1270 = or(_issue_entry_T_1269, _issue_entry_T_1263) node _issue_entry_T_1271 = or(_issue_entry_T_1270, _issue_entry_T_1264) node _issue_entry_T_1272 = or(_issue_entry_T_1271, _issue_entry_T_1265) node _issue_entry_T_1273 = or(_issue_entry_T_1272, _issue_entry_T_1266) node _issue_entry_T_1274 = or(_issue_entry_T_1273, _issue_entry_T_1267) wire _issue_entry_WIRE_96 : UInt<1> connect _issue_entry_WIRE_96, _issue_entry_T_1274 connect _issue_entry_WIRE_94.garbage_bit, _issue_entry_WIRE_96 node _issue_entry_T_1275 = mux(issue_sel_0, entries_ld[0].bits.opb.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_1276 = mux(issue_sel_1, entries_ld[1].bits.opb.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_1277 = mux(issue_sel_2, entries_ld[2].bits.opb.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_1278 = mux(issue_sel_3, entries_ld[3].bits.opb.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_1279 = mux(issue_sel_4, entries_ld[4].bits.opb.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_1280 = mux(issue_sel_5, entries_ld[5].bits.opb.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_1281 = mux(issue_sel_6, entries_ld[6].bits.opb.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_1282 = mux(issue_sel_7, entries_ld[7].bits.opb.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_1283 = or(_issue_entry_T_1275, _issue_entry_T_1276) node _issue_entry_T_1284 = or(_issue_entry_T_1283, _issue_entry_T_1277) node _issue_entry_T_1285 = or(_issue_entry_T_1284, _issue_entry_T_1278) node _issue_entry_T_1286 = or(_issue_entry_T_1285, _issue_entry_T_1279) node _issue_entry_T_1287 = or(_issue_entry_T_1286, _issue_entry_T_1280) node _issue_entry_T_1288 = or(_issue_entry_T_1287, _issue_entry_T_1281) node _issue_entry_T_1289 = or(_issue_entry_T_1288, _issue_entry_T_1282) wire _issue_entry_WIRE_97 : UInt<11> connect _issue_entry_WIRE_97, _issue_entry_T_1289 connect _issue_entry_WIRE_94.garbage, _issue_entry_WIRE_97 node _issue_entry_T_1290 = asUInt(entries_ld[0].bits.opb.bits.end.norm_cmd) node _issue_entry_T_1291 = mux(issue_sel_0, _issue_entry_T_1290, UInt<1>(0h0)) node _issue_entry_T_1292 = asUInt(entries_ld[1].bits.opb.bits.end.norm_cmd) node _issue_entry_T_1293 = mux(issue_sel_1, _issue_entry_T_1292, UInt<1>(0h0)) node _issue_entry_T_1294 = asUInt(entries_ld[2].bits.opb.bits.end.norm_cmd) node _issue_entry_T_1295 = mux(issue_sel_2, _issue_entry_T_1294, UInt<1>(0h0)) node _issue_entry_T_1296 = asUInt(entries_ld[3].bits.opb.bits.end.norm_cmd) node _issue_entry_T_1297 = mux(issue_sel_3, _issue_entry_T_1296, UInt<1>(0h0)) node _issue_entry_T_1298 = asUInt(entries_ld[4].bits.opb.bits.end.norm_cmd) node _issue_entry_T_1299 = mux(issue_sel_4, _issue_entry_T_1298, UInt<1>(0h0)) node _issue_entry_T_1300 = asUInt(entries_ld[5].bits.opb.bits.end.norm_cmd) node _issue_entry_T_1301 = mux(issue_sel_5, _issue_entry_T_1300, UInt<1>(0h0)) node _issue_entry_T_1302 = asUInt(entries_ld[6].bits.opb.bits.end.norm_cmd) node _issue_entry_T_1303 = mux(issue_sel_6, _issue_entry_T_1302, UInt<1>(0h0)) node _issue_entry_T_1304 = asUInt(entries_ld[7].bits.opb.bits.end.norm_cmd) node _issue_entry_T_1305 = mux(issue_sel_7, _issue_entry_T_1304, UInt<1>(0h0)) node _issue_entry_T_1306 = or(_issue_entry_T_1291, _issue_entry_T_1293) node _issue_entry_T_1307 = or(_issue_entry_T_1306, _issue_entry_T_1295) node _issue_entry_T_1308 = or(_issue_entry_T_1307, _issue_entry_T_1297) node _issue_entry_T_1309 = or(_issue_entry_T_1308, _issue_entry_T_1299) node _issue_entry_T_1310 = or(_issue_entry_T_1309, _issue_entry_T_1301) node _issue_entry_T_1311 = or(_issue_entry_T_1310, _issue_entry_T_1303) node _issue_entry_T_1312 = or(_issue_entry_T_1311, _issue_entry_T_1305) wire _issue_entry_WIRE_98 : UInt<3> wire _issue_entry_WIRE_99 : UInt<3> connect _issue_entry_WIRE_99, _issue_entry_T_1312 wire _issue_entry_WIRE_100 : UInt<3> connect _issue_entry_WIRE_100, _issue_entry_WIRE_99 connect _issue_entry_WIRE_98, _issue_entry_WIRE_100 connect _issue_entry_WIRE_94.norm_cmd, _issue_entry_WIRE_98 node _issue_entry_T_1313 = mux(issue_sel_0, entries_ld[0].bits.opb.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_1314 = mux(issue_sel_1, entries_ld[1].bits.opb.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_1315 = mux(issue_sel_2, entries_ld[2].bits.opb.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_1316 = mux(issue_sel_3, entries_ld[3].bits.opb.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_1317 = mux(issue_sel_4, entries_ld[4].bits.opb.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_1318 = mux(issue_sel_5, entries_ld[5].bits.opb.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_1319 = mux(issue_sel_6, entries_ld[6].bits.opb.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_1320 = mux(issue_sel_7, entries_ld[7].bits.opb.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_1321 = or(_issue_entry_T_1313, _issue_entry_T_1314) node _issue_entry_T_1322 = or(_issue_entry_T_1321, _issue_entry_T_1315) node _issue_entry_T_1323 = or(_issue_entry_T_1322, _issue_entry_T_1316) node _issue_entry_T_1324 = or(_issue_entry_T_1323, _issue_entry_T_1317) node _issue_entry_T_1325 = or(_issue_entry_T_1324, _issue_entry_T_1318) node _issue_entry_T_1326 = or(_issue_entry_T_1325, _issue_entry_T_1319) node _issue_entry_T_1327 = or(_issue_entry_T_1326, _issue_entry_T_1320) wire _issue_entry_WIRE_101 : UInt<1> connect _issue_entry_WIRE_101, _issue_entry_T_1327 connect _issue_entry_WIRE_94.read_full_acc_row, _issue_entry_WIRE_101 node _issue_entry_T_1328 = mux(issue_sel_0, entries_ld[0].bits.opb.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_1329 = mux(issue_sel_1, entries_ld[1].bits.opb.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_1330 = mux(issue_sel_2, entries_ld[2].bits.opb.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_1331 = mux(issue_sel_3, entries_ld[3].bits.opb.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_1332 = mux(issue_sel_4, entries_ld[4].bits.opb.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_1333 = mux(issue_sel_5, entries_ld[5].bits.opb.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_1334 = mux(issue_sel_6, entries_ld[6].bits.opb.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_1335 = mux(issue_sel_7, entries_ld[7].bits.opb.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_1336 = or(_issue_entry_T_1328, _issue_entry_T_1329) node _issue_entry_T_1337 = or(_issue_entry_T_1336, _issue_entry_T_1330) node _issue_entry_T_1338 = or(_issue_entry_T_1337, _issue_entry_T_1331) node _issue_entry_T_1339 = or(_issue_entry_T_1338, _issue_entry_T_1332) node _issue_entry_T_1340 = or(_issue_entry_T_1339, _issue_entry_T_1333) node _issue_entry_T_1341 = or(_issue_entry_T_1340, _issue_entry_T_1334) node _issue_entry_T_1342 = or(_issue_entry_T_1341, _issue_entry_T_1335) wire _issue_entry_WIRE_102 : UInt<1> connect _issue_entry_WIRE_102, _issue_entry_T_1342 connect _issue_entry_WIRE_94.accumulate, _issue_entry_WIRE_102 node _issue_entry_T_1343 = mux(issue_sel_0, entries_ld[0].bits.opb.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_1344 = mux(issue_sel_1, entries_ld[1].bits.opb.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_1345 = mux(issue_sel_2, entries_ld[2].bits.opb.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_1346 = mux(issue_sel_3, entries_ld[3].bits.opb.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_1347 = mux(issue_sel_4, entries_ld[4].bits.opb.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_1348 = mux(issue_sel_5, entries_ld[5].bits.opb.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_1349 = mux(issue_sel_6, entries_ld[6].bits.opb.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_1350 = mux(issue_sel_7, entries_ld[7].bits.opb.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_1351 = or(_issue_entry_T_1343, _issue_entry_T_1344) node _issue_entry_T_1352 = or(_issue_entry_T_1351, _issue_entry_T_1345) node _issue_entry_T_1353 = or(_issue_entry_T_1352, _issue_entry_T_1346) node _issue_entry_T_1354 = or(_issue_entry_T_1353, _issue_entry_T_1347) node _issue_entry_T_1355 = or(_issue_entry_T_1354, _issue_entry_T_1348) node _issue_entry_T_1356 = or(_issue_entry_T_1355, _issue_entry_T_1349) node _issue_entry_T_1357 = or(_issue_entry_T_1356, _issue_entry_T_1350) wire _issue_entry_WIRE_103 : UInt<1> connect _issue_entry_WIRE_103, _issue_entry_T_1357 connect _issue_entry_WIRE_94.is_acc_addr, _issue_entry_WIRE_103 connect _issue_entry_WIRE_92.end, _issue_entry_WIRE_94 wire _issue_entry_WIRE_104 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} node _issue_entry_T_1358 = mux(issue_sel_0, entries_ld[0].bits.opb.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_1359 = mux(issue_sel_1, entries_ld[1].bits.opb.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_1360 = mux(issue_sel_2, entries_ld[2].bits.opb.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_1361 = mux(issue_sel_3, entries_ld[3].bits.opb.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_1362 = mux(issue_sel_4, entries_ld[4].bits.opb.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_1363 = mux(issue_sel_5, entries_ld[5].bits.opb.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_1364 = mux(issue_sel_6, entries_ld[6].bits.opb.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_1365 = mux(issue_sel_7, entries_ld[7].bits.opb.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_1366 = or(_issue_entry_T_1358, _issue_entry_T_1359) node _issue_entry_T_1367 = or(_issue_entry_T_1366, _issue_entry_T_1360) node _issue_entry_T_1368 = or(_issue_entry_T_1367, _issue_entry_T_1361) node _issue_entry_T_1369 = or(_issue_entry_T_1368, _issue_entry_T_1362) node _issue_entry_T_1370 = or(_issue_entry_T_1369, _issue_entry_T_1363) node _issue_entry_T_1371 = or(_issue_entry_T_1370, _issue_entry_T_1364) node _issue_entry_T_1372 = or(_issue_entry_T_1371, _issue_entry_T_1365) wire _issue_entry_WIRE_105 : UInt<14> connect _issue_entry_WIRE_105, _issue_entry_T_1372 connect _issue_entry_WIRE_104.data, _issue_entry_WIRE_105 node _issue_entry_T_1373 = mux(issue_sel_0, entries_ld[0].bits.opb.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_1374 = mux(issue_sel_1, entries_ld[1].bits.opb.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_1375 = mux(issue_sel_2, entries_ld[2].bits.opb.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_1376 = mux(issue_sel_3, entries_ld[3].bits.opb.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_1377 = mux(issue_sel_4, entries_ld[4].bits.opb.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_1378 = mux(issue_sel_5, entries_ld[5].bits.opb.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_1379 = mux(issue_sel_6, entries_ld[6].bits.opb.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_1380 = mux(issue_sel_7, entries_ld[7].bits.opb.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_1381 = or(_issue_entry_T_1373, _issue_entry_T_1374) node _issue_entry_T_1382 = or(_issue_entry_T_1381, _issue_entry_T_1375) node _issue_entry_T_1383 = or(_issue_entry_T_1382, _issue_entry_T_1376) node _issue_entry_T_1384 = or(_issue_entry_T_1383, _issue_entry_T_1377) node _issue_entry_T_1385 = or(_issue_entry_T_1384, _issue_entry_T_1378) node _issue_entry_T_1386 = or(_issue_entry_T_1385, _issue_entry_T_1379) node _issue_entry_T_1387 = or(_issue_entry_T_1386, _issue_entry_T_1380) wire _issue_entry_WIRE_106 : UInt<1> connect _issue_entry_WIRE_106, _issue_entry_T_1387 connect _issue_entry_WIRE_104.garbage_bit, _issue_entry_WIRE_106 node _issue_entry_T_1388 = mux(issue_sel_0, entries_ld[0].bits.opb.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_1389 = mux(issue_sel_1, entries_ld[1].bits.opb.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_1390 = mux(issue_sel_2, entries_ld[2].bits.opb.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_1391 = mux(issue_sel_3, entries_ld[3].bits.opb.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_1392 = mux(issue_sel_4, entries_ld[4].bits.opb.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_1393 = mux(issue_sel_5, entries_ld[5].bits.opb.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_1394 = mux(issue_sel_6, entries_ld[6].bits.opb.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_1395 = mux(issue_sel_7, entries_ld[7].bits.opb.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_1396 = or(_issue_entry_T_1388, _issue_entry_T_1389) node _issue_entry_T_1397 = or(_issue_entry_T_1396, _issue_entry_T_1390) node _issue_entry_T_1398 = or(_issue_entry_T_1397, _issue_entry_T_1391) node _issue_entry_T_1399 = or(_issue_entry_T_1398, _issue_entry_T_1392) node _issue_entry_T_1400 = or(_issue_entry_T_1399, _issue_entry_T_1393) node _issue_entry_T_1401 = or(_issue_entry_T_1400, _issue_entry_T_1394) node _issue_entry_T_1402 = or(_issue_entry_T_1401, _issue_entry_T_1395) wire _issue_entry_WIRE_107 : UInt<11> connect _issue_entry_WIRE_107, _issue_entry_T_1402 connect _issue_entry_WIRE_104.garbage, _issue_entry_WIRE_107 node _issue_entry_T_1403 = asUInt(entries_ld[0].bits.opb.bits.start.norm_cmd) node _issue_entry_T_1404 = mux(issue_sel_0, _issue_entry_T_1403, UInt<1>(0h0)) node _issue_entry_T_1405 = asUInt(entries_ld[1].bits.opb.bits.start.norm_cmd) node _issue_entry_T_1406 = mux(issue_sel_1, _issue_entry_T_1405, UInt<1>(0h0)) node _issue_entry_T_1407 = asUInt(entries_ld[2].bits.opb.bits.start.norm_cmd) node _issue_entry_T_1408 = mux(issue_sel_2, _issue_entry_T_1407, UInt<1>(0h0)) node _issue_entry_T_1409 = asUInt(entries_ld[3].bits.opb.bits.start.norm_cmd) node _issue_entry_T_1410 = mux(issue_sel_3, _issue_entry_T_1409, UInt<1>(0h0)) node _issue_entry_T_1411 = asUInt(entries_ld[4].bits.opb.bits.start.norm_cmd) node _issue_entry_T_1412 = mux(issue_sel_4, _issue_entry_T_1411, UInt<1>(0h0)) node _issue_entry_T_1413 = asUInt(entries_ld[5].bits.opb.bits.start.norm_cmd) node _issue_entry_T_1414 = mux(issue_sel_5, _issue_entry_T_1413, UInt<1>(0h0)) node _issue_entry_T_1415 = asUInt(entries_ld[6].bits.opb.bits.start.norm_cmd) node _issue_entry_T_1416 = mux(issue_sel_6, _issue_entry_T_1415, UInt<1>(0h0)) node _issue_entry_T_1417 = asUInt(entries_ld[7].bits.opb.bits.start.norm_cmd) node _issue_entry_T_1418 = mux(issue_sel_7, _issue_entry_T_1417, UInt<1>(0h0)) node _issue_entry_T_1419 = or(_issue_entry_T_1404, _issue_entry_T_1406) node _issue_entry_T_1420 = or(_issue_entry_T_1419, _issue_entry_T_1408) node _issue_entry_T_1421 = or(_issue_entry_T_1420, _issue_entry_T_1410) node _issue_entry_T_1422 = or(_issue_entry_T_1421, _issue_entry_T_1412) node _issue_entry_T_1423 = or(_issue_entry_T_1422, _issue_entry_T_1414) node _issue_entry_T_1424 = or(_issue_entry_T_1423, _issue_entry_T_1416) node _issue_entry_T_1425 = or(_issue_entry_T_1424, _issue_entry_T_1418) wire _issue_entry_WIRE_108 : UInt<3> wire _issue_entry_WIRE_109 : UInt<3> connect _issue_entry_WIRE_109, _issue_entry_T_1425 wire _issue_entry_WIRE_110 : UInt<3> connect _issue_entry_WIRE_110, _issue_entry_WIRE_109 connect _issue_entry_WIRE_108, _issue_entry_WIRE_110 connect _issue_entry_WIRE_104.norm_cmd, _issue_entry_WIRE_108 node _issue_entry_T_1426 = mux(issue_sel_0, entries_ld[0].bits.opb.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_1427 = mux(issue_sel_1, entries_ld[1].bits.opb.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_1428 = mux(issue_sel_2, entries_ld[2].bits.opb.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_1429 = mux(issue_sel_3, entries_ld[3].bits.opb.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_1430 = mux(issue_sel_4, entries_ld[4].bits.opb.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_1431 = mux(issue_sel_5, entries_ld[5].bits.opb.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_1432 = mux(issue_sel_6, entries_ld[6].bits.opb.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_1433 = mux(issue_sel_7, entries_ld[7].bits.opb.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_1434 = or(_issue_entry_T_1426, _issue_entry_T_1427) node _issue_entry_T_1435 = or(_issue_entry_T_1434, _issue_entry_T_1428) node _issue_entry_T_1436 = or(_issue_entry_T_1435, _issue_entry_T_1429) node _issue_entry_T_1437 = or(_issue_entry_T_1436, _issue_entry_T_1430) node _issue_entry_T_1438 = or(_issue_entry_T_1437, _issue_entry_T_1431) node _issue_entry_T_1439 = or(_issue_entry_T_1438, _issue_entry_T_1432) node _issue_entry_T_1440 = or(_issue_entry_T_1439, _issue_entry_T_1433) wire _issue_entry_WIRE_111 : UInt<1> connect _issue_entry_WIRE_111, _issue_entry_T_1440 connect _issue_entry_WIRE_104.read_full_acc_row, _issue_entry_WIRE_111 node _issue_entry_T_1441 = mux(issue_sel_0, entries_ld[0].bits.opb.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_1442 = mux(issue_sel_1, entries_ld[1].bits.opb.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_1443 = mux(issue_sel_2, entries_ld[2].bits.opb.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_1444 = mux(issue_sel_3, entries_ld[3].bits.opb.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_1445 = mux(issue_sel_4, entries_ld[4].bits.opb.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_1446 = mux(issue_sel_5, entries_ld[5].bits.opb.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_1447 = mux(issue_sel_6, entries_ld[6].bits.opb.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_1448 = mux(issue_sel_7, entries_ld[7].bits.opb.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_1449 = or(_issue_entry_T_1441, _issue_entry_T_1442) node _issue_entry_T_1450 = or(_issue_entry_T_1449, _issue_entry_T_1443) node _issue_entry_T_1451 = or(_issue_entry_T_1450, _issue_entry_T_1444) node _issue_entry_T_1452 = or(_issue_entry_T_1451, _issue_entry_T_1445) node _issue_entry_T_1453 = or(_issue_entry_T_1452, _issue_entry_T_1446) node _issue_entry_T_1454 = or(_issue_entry_T_1453, _issue_entry_T_1447) node _issue_entry_T_1455 = or(_issue_entry_T_1454, _issue_entry_T_1448) wire _issue_entry_WIRE_112 : UInt<1> connect _issue_entry_WIRE_112, _issue_entry_T_1455 connect _issue_entry_WIRE_104.accumulate, _issue_entry_WIRE_112 node _issue_entry_T_1456 = mux(issue_sel_0, entries_ld[0].bits.opb.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_1457 = mux(issue_sel_1, entries_ld[1].bits.opb.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_1458 = mux(issue_sel_2, entries_ld[2].bits.opb.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_1459 = mux(issue_sel_3, entries_ld[3].bits.opb.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_1460 = mux(issue_sel_4, entries_ld[4].bits.opb.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_1461 = mux(issue_sel_5, entries_ld[5].bits.opb.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_1462 = mux(issue_sel_6, entries_ld[6].bits.opb.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_1463 = mux(issue_sel_7, entries_ld[7].bits.opb.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_1464 = or(_issue_entry_T_1456, _issue_entry_T_1457) node _issue_entry_T_1465 = or(_issue_entry_T_1464, _issue_entry_T_1458) node _issue_entry_T_1466 = or(_issue_entry_T_1465, _issue_entry_T_1459) node _issue_entry_T_1467 = or(_issue_entry_T_1466, _issue_entry_T_1460) node _issue_entry_T_1468 = or(_issue_entry_T_1467, _issue_entry_T_1461) node _issue_entry_T_1469 = or(_issue_entry_T_1468, _issue_entry_T_1462) node _issue_entry_T_1470 = or(_issue_entry_T_1469, _issue_entry_T_1463) wire _issue_entry_WIRE_113 : UInt<1> connect _issue_entry_WIRE_113, _issue_entry_T_1470 connect _issue_entry_WIRE_104.is_acc_addr, _issue_entry_WIRE_113 connect _issue_entry_WIRE_92.start, _issue_entry_WIRE_104 connect _issue_entry_WIRE_91.bits, _issue_entry_WIRE_92 node _issue_entry_T_1471 = mux(issue_sel_0, entries_ld[0].bits.opb.valid, UInt<1>(0h0)) node _issue_entry_T_1472 = mux(issue_sel_1, entries_ld[1].bits.opb.valid, UInt<1>(0h0)) node _issue_entry_T_1473 = mux(issue_sel_2, entries_ld[2].bits.opb.valid, UInt<1>(0h0)) node _issue_entry_T_1474 = mux(issue_sel_3, entries_ld[3].bits.opb.valid, UInt<1>(0h0)) node _issue_entry_T_1475 = mux(issue_sel_4, entries_ld[4].bits.opb.valid, UInt<1>(0h0)) node _issue_entry_T_1476 = mux(issue_sel_5, entries_ld[5].bits.opb.valid, UInt<1>(0h0)) node _issue_entry_T_1477 = mux(issue_sel_6, entries_ld[6].bits.opb.valid, UInt<1>(0h0)) node _issue_entry_T_1478 = mux(issue_sel_7, entries_ld[7].bits.opb.valid, UInt<1>(0h0)) node _issue_entry_T_1479 = or(_issue_entry_T_1471, _issue_entry_T_1472) node _issue_entry_T_1480 = or(_issue_entry_T_1479, _issue_entry_T_1473) node _issue_entry_T_1481 = or(_issue_entry_T_1480, _issue_entry_T_1474) node _issue_entry_T_1482 = or(_issue_entry_T_1481, _issue_entry_T_1475) node _issue_entry_T_1483 = or(_issue_entry_T_1482, _issue_entry_T_1476) node _issue_entry_T_1484 = or(_issue_entry_T_1483, _issue_entry_T_1477) node _issue_entry_T_1485 = or(_issue_entry_T_1484, _issue_entry_T_1478) wire _issue_entry_WIRE_114 : UInt<1> connect _issue_entry_WIRE_114, _issue_entry_T_1485 connect _issue_entry_WIRE_91.valid, _issue_entry_WIRE_114 connect _issue_entry_WIRE.opb, _issue_entry_WIRE_91 node _issue_entry_T_1486 = mux(issue_sel_0, entries_ld[0].bits.opa_is_dst, UInt<1>(0h0)) node _issue_entry_T_1487 = mux(issue_sel_1, entries_ld[1].bits.opa_is_dst, UInt<1>(0h0)) node _issue_entry_T_1488 = mux(issue_sel_2, entries_ld[2].bits.opa_is_dst, UInt<1>(0h0)) node _issue_entry_T_1489 = mux(issue_sel_3, entries_ld[3].bits.opa_is_dst, UInt<1>(0h0)) node _issue_entry_T_1490 = mux(issue_sel_4, entries_ld[4].bits.opa_is_dst, UInt<1>(0h0)) node _issue_entry_T_1491 = mux(issue_sel_5, entries_ld[5].bits.opa_is_dst, UInt<1>(0h0)) node _issue_entry_T_1492 = mux(issue_sel_6, entries_ld[6].bits.opa_is_dst, UInt<1>(0h0)) node _issue_entry_T_1493 = mux(issue_sel_7, entries_ld[7].bits.opa_is_dst, UInt<1>(0h0)) node _issue_entry_T_1494 = or(_issue_entry_T_1486, _issue_entry_T_1487) node _issue_entry_T_1495 = or(_issue_entry_T_1494, _issue_entry_T_1488) node _issue_entry_T_1496 = or(_issue_entry_T_1495, _issue_entry_T_1489) node _issue_entry_T_1497 = or(_issue_entry_T_1496, _issue_entry_T_1490) node _issue_entry_T_1498 = or(_issue_entry_T_1497, _issue_entry_T_1491) node _issue_entry_T_1499 = or(_issue_entry_T_1498, _issue_entry_T_1492) node _issue_entry_T_1500 = or(_issue_entry_T_1499, _issue_entry_T_1493) wire _issue_entry_WIRE_115 : UInt<1> connect _issue_entry_WIRE_115, _issue_entry_T_1500 connect _issue_entry_WIRE.opa_is_dst, _issue_entry_WIRE_115 wire _issue_entry_WIRE_116 : { valid : UInt<1>, bits : { start : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, end : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, wraps_around : UInt<1>}} wire _issue_entry_WIRE_117 : { start : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, end : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, wraps_around : UInt<1>} node _issue_entry_T_1501 = mux(issue_sel_0, entries_ld[0].bits.opa.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_1502 = mux(issue_sel_1, entries_ld[1].bits.opa.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_1503 = mux(issue_sel_2, entries_ld[2].bits.opa.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_1504 = mux(issue_sel_3, entries_ld[3].bits.opa.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_1505 = mux(issue_sel_4, entries_ld[4].bits.opa.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_1506 = mux(issue_sel_5, entries_ld[5].bits.opa.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_1507 = mux(issue_sel_6, entries_ld[6].bits.opa.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_1508 = mux(issue_sel_7, entries_ld[7].bits.opa.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_1509 = or(_issue_entry_T_1501, _issue_entry_T_1502) node _issue_entry_T_1510 = or(_issue_entry_T_1509, _issue_entry_T_1503) node _issue_entry_T_1511 = or(_issue_entry_T_1510, _issue_entry_T_1504) node _issue_entry_T_1512 = or(_issue_entry_T_1511, _issue_entry_T_1505) node _issue_entry_T_1513 = or(_issue_entry_T_1512, _issue_entry_T_1506) node _issue_entry_T_1514 = or(_issue_entry_T_1513, _issue_entry_T_1507) node _issue_entry_T_1515 = or(_issue_entry_T_1514, _issue_entry_T_1508) wire _issue_entry_WIRE_118 : UInt<1> connect _issue_entry_WIRE_118, _issue_entry_T_1515 connect _issue_entry_WIRE_117.wraps_around, _issue_entry_WIRE_118 wire _issue_entry_WIRE_119 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} node _issue_entry_T_1516 = mux(issue_sel_0, entries_ld[0].bits.opa.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_1517 = mux(issue_sel_1, entries_ld[1].bits.opa.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_1518 = mux(issue_sel_2, entries_ld[2].bits.opa.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_1519 = mux(issue_sel_3, entries_ld[3].bits.opa.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_1520 = mux(issue_sel_4, entries_ld[4].bits.opa.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_1521 = mux(issue_sel_5, entries_ld[5].bits.opa.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_1522 = mux(issue_sel_6, entries_ld[6].bits.opa.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_1523 = mux(issue_sel_7, entries_ld[7].bits.opa.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_1524 = or(_issue_entry_T_1516, _issue_entry_T_1517) node _issue_entry_T_1525 = or(_issue_entry_T_1524, _issue_entry_T_1518) node _issue_entry_T_1526 = or(_issue_entry_T_1525, _issue_entry_T_1519) node _issue_entry_T_1527 = or(_issue_entry_T_1526, _issue_entry_T_1520) node _issue_entry_T_1528 = or(_issue_entry_T_1527, _issue_entry_T_1521) node _issue_entry_T_1529 = or(_issue_entry_T_1528, _issue_entry_T_1522) node _issue_entry_T_1530 = or(_issue_entry_T_1529, _issue_entry_T_1523) wire _issue_entry_WIRE_120 : UInt<14> connect _issue_entry_WIRE_120, _issue_entry_T_1530 connect _issue_entry_WIRE_119.data, _issue_entry_WIRE_120 node _issue_entry_T_1531 = mux(issue_sel_0, entries_ld[0].bits.opa.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_1532 = mux(issue_sel_1, entries_ld[1].bits.opa.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_1533 = mux(issue_sel_2, entries_ld[2].bits.opa.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_1534 = mux(issue_sel_3, entries_ld[3].bits.opa.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_1535 = mux(issue_sel_4, entries_ld[4].bits.opa.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_1536 = mux(issue_sel_5, entries_ld[5].bits.opa.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_1537 = mux(issue_sel_6, entries_ld[6].bits.opa.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_1538 = mux(issue_sel_7, entries_ld[7].bits.opa.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_1539 = or(_issue_entry_T_1531, _issue_entry_T_1532) node _issue_entry_T_1540 = or(_issue_entry_T_1539, _issue_entry_T_1533) node _issue_entry_T_1541 = or(_issue_entry_T_1540, _issue_entry_T_1534) node _issue_entry_T_1542 = or(_issue_entry_T_1541, _issue_entry_T_1535) node _issue_entry_T_1543 = or(_issue_entry_T_1542, _issue_entry_T_1536) node _issue_entry_T_1544 = or(_issue_entry_T_1543, _issue_entry_T_1537) node _issue_entry_T_1545 = or(_issue_entry_T_1544, _issue_entry_T_1538) wire _issue_entry_WIRE_121 : UInt<1> connect _issue_entry_WIRE_121, _issue_entry_T_1545 connect _issue_entry_WIRE_119.garbage_bit, _issue_entry_WIRE_121 node _issue_entry_T_1546 = mux(issue_sel_0, entries_ld[0].bits.opa.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_1547 = mux(issue_sel_1, entries_ld[1].bits.opa.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_1548 = mux(issue_sel_2, entries_ld[2].bits.opa.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_1549 = mux(issue_sel_3, entries_ld[3].bits.opa.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_1550 = mux(issue_sel_4, entries_ld[4].bits.opa.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_1551 = mux(issue_sel_5, entries_ld[5].bits.opa.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_1552 = mux(issue_sel_6, entries_ld[6].bits.opa.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_1553 = mux(issue_sel_7, entries_ld[7].bits.opa.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_1554 = or(_issue_entry_T_1546, _issue_entry_T_1547) node _issue_entry_T_1555 = or(_issue_entry_T_1554, _issue_entry_T_1548) node _issue_entry_T_1556 = or(_issue_entry_T_1555, _issue_entry_T_1549) node _issue_entry_T_1557 = or(_issue_entry_T_1556, _issue_entry_T_1550) node _issue_entry_T_1558 = or(_issue_entry_T_1557, _issue_entry_T_1551) node _issue_entry_T_1559 = or(_issue_entry_T_1558, _issue_entry_T_1552) node _issue_entry_T_1560 = or(_issue_entry_T_1559, _issue_entry_T_1553) wire _issue_entry_WIRE_122 : UInt<11> connect _issue_entry_WIRE_122, _issue_entry_T_1560 connect _issue_entry_WIRE_119.garbage, _issue_entry_WIRE_122 node _issue_entry_T_1561 = asUInt(entries_ld[0].bits.opa.bits.end.norm_cmd) node _issue_entry_T_1562 = mux(issue_sel_0, _issue_entry_T_1561, UInt<1>(0h0)) node _issue_entry_T_1563 = asUInt(entries_ld[1].bits.opa.bits.end.norm_cmd) node _issue_entry_T_1564 = mux(issue_sel_1, _issue_entry_T_1563, UInt<1>(0h0)) node _issue_entry_T_1565 = asUInt(entries_ld[2].bits.opa.bits.end.norm_cmd) node _issue_entry_T_1566 = mux(issue_sel_2, _issue_entry_T_1565, UInt<1>(0h0)) node _issue_entry_T_1567 = asUInt(entries_ld[3].bits.opa.bits.end.norm_cmd) node _issue_entry_T_1568 = mux(issue_sel_3, _issue_entry_T_1567, UInt<1>(0h0)) node _issue_entry_T_1569 = asUInt(entries_ld[4].bits.opa.bits.end.norm_cmd) node _issue_entry_T_1570 = mux(issue_sel_4, _issue_entry_T_1569, UInt<1>(0h0)) node _issue_entry_T_1571 = asUInt(entries_ld[5].bits.opa.bits.end.norm_cmd) node _issue_entry_T_1572 = mux(issue_sel_5, _issue_entry_T_1571, UInt<1>(0h0)) node _issue_entry_T_1573 = asUInt(entries_ld[6].bits.opa.bits.end.norm_cmd) node _issue_entry_T_1574 = mux(issue_sel_6, _issue_entry_T_1573, UInt<1>(0h0)) node _issue_entry_T_1575 = asUInt(entries_ld[7].bits.opa.bits.end.norm_cmd) node _issue_entry_T_1576 = mux(issue_sel_7, _issue_entry_T_1575, UInt<1>(0h0)) node _issue_entry_T_1577 = or(_issue_entry_T_1562, _issue_entry_T_1564) node _issue_entry_T_1578 = or(_issue_entry_T_1577, _issue_entry_T_1566) node _issue_entry_T_1579 = or(_issue_entry_T_1578, _issue_entry_T_1568) node _issue_entry_T_1580 = or(_issue_entry_T_1579, _issue_entry_T_1570) node _issue_entry_T_1581 = or(_issue_entry_T_1580, _issue_entry_T_1572) node _issue_entry_T_1582 = or(_issue_entry_T_1581, _issue_entry_T_1574) node _issue_entry_T_1583 = or(_issue_entry_T_1582, _issue_entry_T_1576) wire _issue_entry_WIRE_123 : UInt<3> wire _issue_entry_WIRE_124 : UInt<3> connect _issue_entry_WIRE_124, _issue_entry_T_1583 wire _issue_entry_WIRE_125 : UInt<3> connect _issue_entry_WIRE_125, _issue_entry_WIRE_124 connect _issue_entry_WIRE_123, _issue_entry_WIRE_125 connect _issue_entry_WIRE_119.norm_cmd, _issue_entry_WIRE_123 node _issue_entry_T_1584 = mux(issue_sel_0, entries_ld[0].bits.opa.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_1585 = mux(issue_sel_1, entries_ld[1].bits.opa.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_1586 = mux(issue_sel_2, entries_ld[2].bits.opa.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_1587 = mux(issue_sel_3, entries_ld[3].bits.opa.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_1588 = mux(issue_sel_4, entries_ld[4].bits.opa.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_1589 = mux(issue_sel_5, entries_ld[5].bits.opa.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_1590 = mux(issue_sel_6, entries_ld[6].bits.opa.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_1591 = mux(issue_sel_7, entries_ld[7].bits.opa.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_1592 = or(_issue_entry_T_1584, _issue_entry_T_1585) node _issue_entry_T_1593 = or(_issue_entry_T_1592, _issue_entry_T_1586) node _issue_entry_T_1594 = or(_issue_entry_T_1593, _issue_entry_T_1587) node _issue_entry_T_1595 = or(_issue_entry_T_1594, _issue_entry_T_1588) node _issue_entry_T_1596 = or(_issue_entry_T_1595, _issue_entry_T_1589) node _issue_entry_T_1597 = or(_issue_entry_T_1596, _issue_entry_T_1590) node _issue_entry_T_1598 = or(_issue_entry_T_1597, _issue_entry_T_1591) wire _issue_entry_WIRE_126 : UInt<1> connect _issue_entry_WIRE_126, _issue_entry_T_1598 connect _issue_entry_WIRE_119.read_full_acc_row, _issue_entry_WIRE_126 node _issue_entry_T_1599 = mux(issue_sel_0, entries_ld[0].bits.opa.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_1600 = mux(issue_sel_1, entries_ld[1].bits.opa.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_1601 = mux(issue_sel_2, entries_ld[2].bits.opa.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_1602 = mux(issue_sel_3, entries_ld[3].bits.opa.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_1603 = mux(issue_sel_4, entries_ld[4].bits.opa.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_1604 = mux(issue_sel_5, entries_ld[5].bits.opa.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_1605 = mux(issue_sel_6, entries_ld[6].bits.opa.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_1606 = mux(issue_sel_7, entries_ld[7].bits.opa.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_1607 = or(_issue_entry_T_1599, _issue_entry_T_1600) node _issue_entry_T_1608 = or(_issue_entry_T_1607, _issue_entry_T_1601) node _issue_entry_T_1609 = or(_issue_entry_T_1608, _issue_entry_T_1602) node _issue_entry_T_1610 = or(_issue_entry_T_1609, _issue_entry_T_1603) node _issue_entry_T_1611 = or(_issue_entry_T_1610, _issue_entry_T_1604) node _issue_entry_T_1612 = or(_issue_entry_T_1611, _issue_entry_T_1605) node _issue_entry_T_1613 = or(_issue_entry_T_1612, _issue_entry_T_1606) wire _issue_entry_WIRE_127 : UInt<1> connect _issue_entry_WIRE_127, _issue_entry_T_1613 connect _issue_entry_WIRE_119.accumulate, _issue_entry_WIRE_127 node _issue_entry_T_1614 = mux(issue_sel_0, entries_ld[0].bits.opa.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_1615 = mux(issue_sel_1, entries_ld[1].bits.opa.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_1616 = mux(issue_sel_2, entries_ld[2].bits.opa.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_1617 = mux(issue_sel_3, entries_ld[3].bits.opa.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_1618 = mux(issue_sel_4, entries_ld[4].bits.opa.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_1619 = mux(issue_sel_5, entries_ld[5].bits.opa.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_1620 = mux(issue_sel_6, entries_ld[6].bits.opa.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_1621 = mux(issue_sel_7, entries_ld[7].bits.opa.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_1622 = or(_issue_entry_T_1614, _issue_entry_T_1615) node _issue_entry_T_1623 = or(_issue_entry_T_1622, _issue_entry_T_1616) node _issue_entry_T_1624 = or(_issue_entry_T_1623, _issue_entry_T_1617) node _issue_entry_T_1625 = or(_issue_entry_T_1624, _issue_entry_T_1618) node _issue_entry_T_1626 = or(_issue_entry_T_1625, _issue_entry_T_1619) node _issue_entry_T_1627 = or(_issue_entry_T_1626, _issue_entry_T_1620) node _issue_entry_T_1628 = or(_issue_entry_T_1627, _issue_entry_T_1621) wire _issue_entry_WIRE_128 : UInt<1> connect _issue_entry_WIRE_128, _issue_entry_T_1628 connect _issue_entry_WIRE_119.is_acc_addr, _issue_entry_WIRE_128 connect _issue_entry_WIRE_117.end, _issue_entry_WIRE_119 wire _issue_entry_WIRE_129 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} node _issue_entry_T_1629 = mux(issue_sel_0, entries_ld[0].bits.opa.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_1630 = mux(issue_sel_1, entries_ld[1].bits.opa.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_1631 = mux(issue_sel_2, entries_ld[2].bits.opa.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_1632 = mux(issue_sel_3, entries_ld[3].bits.opa.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_1633 = mux(issue_sel_4, entries_ld[4].bits.opa.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_1634 = mux(issue_sel_5, entries_ld[5].bits.opa.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_1635 = mux(issue_sel_6, entries_ld[6].bits.opa.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_1636 = mux(issue_sel_7, entries_ld[7].bits.opa.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_1637 = or(_issue_entry_T_1629, _issue_entry_T_1630) node _issue_entry_T_1638 = or(_issue_entry_T_1637, _issue_entry_T_1631) node _issue_entry_T_1639 = or(_issue_entry_T_1638, _issue_entry_T_1632) node _issue_entry_T_1640 = or(_issue_entry_T_1639, _issue_entry_T_1633) node _issue_entry_T_1641 = or(_issue_entry_T_1640, _issue_entry_T_1634) node _issue_entry_T_1642 = or(_issue_entry_T_1641, _issue_entry_T_1635) node _issue_entry_T_1643 = or(_issue_entry_T_1642, _issue_entry_T_1636) wire _issue_entry_WIRE_130 : UInt<14> connect _issue_entry_WIRE_130, _issue_entry_T_1643 connect _issue_entry_WIRE_129.data, _issue_entry_WIRE_130 node _issue_entry_T_1644 = mux(issue_sel_0, entries_ld[0].bits.opa.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_1645 = mux(issue_sel_1, entries_ld[1].bits.opa.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_1646 = mux(issue_sel_2, entries_ld[2].bits.opa.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_1647 = mux(issue_sel_3, entries_ld[3].bits.opa.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_1648 = mux(issue_sel_4, entries_ld[4].bits.opa.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_1649 = mux(issue_sel_5, entries_ld[5].bits.opa.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_1650 = mux(issue_sel_6, entries_ld[6].bits.opa.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_1651 = mux(issue_sel_7, entries_ld[7].bits.opa.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_1652 = or(_issue_entry_T_1644, _issue_entry_T_1645) node _issue_entry_T_1653 = or(_issue_entry_T_1652, _issue_entry_T_1646) node _issue_entry_T_1654 = or(_issue_entry_T_1653, _issue_entry_T_1647) node _issue_entry_T_1655 = or(_issue_entry_T_1654, _issue_entry_T_1648) node _issue_entry_T_1656 = or(_issue_entry_T_1655, _issue_entry_T_1649) node _issue_entry_T_1657 = or(_issue_entry_T_1656, _issue_entry_T_1650) node _issue_entry_T_1658 = or(_issue_entry_T_1657, _issue_entry_T_1651) wire _issue_entry_WIRE_131 : UInt<1> connect _issue_entry_WIRE_131, _issue_entry_T_1658 connect _issue_entry_WIRE_129.garbage_bit, _issue_entry_WIRE_131 node _issue_entry_T_1659 = mux(issue_sel_0, entries_ld[0].bits.opa.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_1660 = mux(issue_sel_1, entries_ld[1].bits.opa.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_1661 = mux(issue_sel_2, entries_ld[2].bits.opa.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_1662 = mux(issue_sel_3, entries_ld[3].bits.opa.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_1663 = mux(issue_sel_4, entries_ld[4].bits.opa.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_1664 = mux(issue_sel_5, entries_ld[5].bits.opa.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_1665 = mux(issue_sel_6, entries_ld[6].bits.opa.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_1666 = mux(issue_sel_7, entries_ld[7].bits.opa.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_1667 = or(_issue_entry_T_1659, _issue_entry_T_1660) node _issue_entry_T_1668 = or(_issue_entry_T_1667, _issue_entry_T_1661) node _issue_entry_T_1669 = or(_issue_entry_T_1668, _issue_entry_T_1662) node _issue_entry_T_1670 = or(_issue_entry_T_1669, _issue_entry_T_1663) node _issue_entry_T_1671 = or(_issue_entry_T_1670, _issue_entry_T_1664) node _issue_entry_T_1672 = or(_issue_entry_T_1671, _issue_entry_T_1665) node _issue_entry_T_1673 = or(_issue_entry_T_1672, _issue_entry_T_1666) wire _issue_entry_WIRE_132 : UInt<11> connect _issue_entry_WIRE_132, _issue_entry_T_1673 connect _issue_entry_WIRE_129.garbage, _issue_entry_WIRE_132 node _issue_entry_T_1674 = asUInt(entries_ld[0].bits.opa.bits.start.norm_cmd) node _issue_entry_T_1675 = mux(issue_sel_0, _issue_entry_T_1674, UInt<1>(0h0)) node _issue_entry_T_1676 = asUInt(entries_ld[1].bits.opa.bits.start.norm_cmd) node _issue_entry_T_1677 = mux(issue_sel_1, _issue_entry_T_1676, UInt<1>(0h0)) node _issue_entry_T_1678 = asUInt(entries_ld[2].bits.opa.bits.start.norm_cmd) node _issue_entry_T_1679 = mux(issue_sel_2, _issue_entry_T_1678, UInt<1>(0h0)) node _issue_entry_T_1680 = asUInt(entries_ld[3].bits.opa.bits.start.norm_cmd) node _issue_entry_T_1681 = mux(issue_sel_3, _issue_entry_T_1680, UInt<1>(0h0)) node _issue_entry_T_1682 = asUInt(entries_ld[4].bits.opa.bits.start.norm_cmd) node _issue_entry_T_1683 = mux(issue_sel_4, _issue_entry_T_1682, UInt<1>(0h0)) node _issue_entry_T_1684 = asUInt(entries_ld[5].bits.opa.bits.start.norm_cmd) node _issue_entry_T_1685 = mux(issue_sel_5, _issue_entry_T_1684, UInt<1>(0h0)) node _issue_entry_T_1686 = asUInt(entries_ld[6].bits.opa.bits.start.norm_cmd) node _issue_entry_T_1687 = mux(issue_sel_6, _issue_entry_T_1686, UInt<1>(0h0)) node _issue_entry_T_1688 = asUInt(entries_ld[7].bits.opa.bits.start.norm_cmd) node _issue_entry_T_1689 = mux(issue_sel_7, _issue_entry_T_1688, UInt<1>(0h0)) node _issue_entry_T_1690 = or(_issue_entry_T_1675, _issue_entry_T_1677) node _issue_entry_T_1691 = or(_issue_entry_T_1690, _issue_entry_T_1679) node _issue_entry_T_1692 = or(_issue_entry_T_1691, _issue_entry_T_1681) node _issue_entry_T_1693 = or(_issue_entry_T_1692, _issue_entry_T_1683) node _issue_entry_T_1694 = or(_issue_entry_T_1693, _issue_entry_T_1685) node _issue_entry_T_1695 = or(_issue_entry_T_1694, _issue_entry_T_1687) node _issue_entry_T_1696 = or(_issue_entry_T_1695, _issue_entry_T_1689) wire _issue_entry_WIRE_133 : UInt<3> wire _issue_entry_WIRE_134 : UInt<3> connect _issue_entry_WIRE_134, _issue_entry_T_1696 wire _issue_entry_WIRE_135 : UInt<3> connect _issue_entry_WIRE_135, _issue_entry_WIRE_134 connect _issue_entry_WIRE_133, _issue_entry_WIRE_135 connect _issue_entry_WIRE_129.norm_cmd, _issue_entry_WIRE_133 node _issue_entry_T_1697 = mux(issue_sel_0, entries_ld[0].bits.opa.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_1698 = mux(issue_sel_1, entries_ld[1].bits.opa.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_1699 = mux(issue_sel_2, entries_ld[2].bits.opa.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_1700 = mux(issue_sel_3, entries_ld[3].bits.opa.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_1701 = mux(issue_sel_4, entries_ld[4].bits.opa.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_1702 = mux(issue_sel_5, entries_ld[5].bits.opa.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_1703 = mux(issue_sel_6, entries_ld[6].bits.opa.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_1704 = mux(issue_sel_7, entries_ld[7].bits.opa.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_1705 = or(_issue_entry_T_1697, _issue_entry_T_1698) node _issue_entry_T_1706 = or(_issue_entry_T_1705, _issue_entry_T_1699) node _issue_entry_T_1707 = or(_issue_entry_T_1706, _issue_entry_T_1700) node _issue_entry_T_1708 = or(_issue_entry_T_1707, _issue_entry_T_1701) node _issue_entry_T_1709 = or(_issue_entry_T_1708, _issue_entry_T_1702) node _issue_entry_T_1710 = or(_issue_entry_T_1709, _issue_entry_T_1703) node _issue_entry_T_1711 = or(_issue_entry_T_1710, _issue_entry_T_1704) wire _issue_entry_WIRE_136 : UInt<1> connect _issue_entry_WIRE_136, _issue_entry_T_1711 connect _issue_entry_WIRE_129.read_full_acc_row, _issue_entry_WIRE_136 node _issue_entry_T_1712 = mux(issue_sel_0, entries_ld[0].bits.opa.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_1713 = mux(issue_sel_1, entries_ld[1].bits.opa.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_1714 = mux(issue_sel_2, entries_ld[2].bits.opa.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_1715 = mux(issue_sel_3, entries_ld[3].bits.opa.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_1716 = mux(issue_sel_4, entries_ld[4].bits.opa.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_1717 = mux(issue_sel_5, entries_ld[5].bits.opa.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_1718 = mux(issue_sel_6, entries_ld[6].bits.opa.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_1719 = mux(issue_sel_7, entries_ld[7].bits.opa.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_1720 = or(_issue_entry_T_1712, _issue_entry_T_1713) node _issue_entry_T_1721 = or(_issue_entry_T_1720, _issue_entry_T_1714) node _issue_entry_T_1722 = or(_issue_entry_T_1721, _issue_entry_T_1715) node _issue_entry_T_1723 = or(_issue_entry_T_1722, _issue_entry_T_1716) node _issue_entry_T_1724 = or(_issue_entry_T_1723, _issue_entry_T_1717) node _issue_entry_T_1725 = or(_issue_entry_T_1724, _issue_entry_T_1718) node _issue_entry_T_1726 = or(_issue_entry_T_1725, _issue_entry_T_1719) wire _issue_entry_WIRE_137 : UInt<1> connect _issue_entry_WIRE_137, _issue_entry_T_1726 connect _issue_entry_WIRE_129.accumulate, _issue_entry_WIRE_137 node _issue_entry_T_1727 = mux(issue_sel_0, entries_ld[0].bits.opa.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_1728 = mux(issue_sel_1, entries_ld[1].bits.opa.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_1729 = mux(issue_sel_2, entries_ld[2].bits.opa.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_1730 = mux(issue_sel_3, entries_ld[3].bits.opa.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_1731 = mux(issue_sel_4, entries_ld[4].bits.opa.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_1732 = mux(issue_sel_5, entries_ld[5].bits.opa.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_1733 = mux(issue_sel_6, entries_ld[6].bits.opa.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_1734 = mux(issue_sel_7, entries_ld[7].bits.opa.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_1735 = or(_issue_entry_T_1727, _issue_entry_T_1728) node _issue_entry_T_1736 = or(_issue_entry_T_1735, _issue_entry_T_1729) node _issue_entry_T_1737 = or(_issue_entry_T_1736, _issue_entry_T_1730) node _issue_entry_T_1738 = or(_issue_entry_T_1737, _issue_entry_T_1731) node _issue_entry_T_1739 = or(_issue_entry_T_1738, _issue_entry_T_1732) node _issue_entry_T_1740 = or(_issue_entry_T_1739, _issue_entry_T_1733) node _issue_entry_T_1741 = or(_issue_entry_T_1740, _issue_entry_T_1734) wire _issue_entry_WIRE_138 : UInt<1> connect _issue_entry_WIRE_138, _issue_entry_T_1741 connect _issue_entry_WIRE_129.is_acc_addr, _issue_entry_WIRE_138 connect _issue_entry_WIRE_117.start, _issue_entry_WIRE_129 connect _issue_entry_WIRE_116.bits, _issue_entry_WIRE_117 node _issue_entry_T_1742 = mux(issue_sel_0, entries_ld[0].bits.opa.valid, UInt<1>(0h0)) node _issue_entry_T_1743 = mux(issue_sel_1, entries_ld[1].bits.opa.valid, UInt<1>(0h0)) node _issue_entry_T_1744 = mux(issue_sel_2, entries_ld[2].bits.opa.valid, UInt<1>(0h0)) node _issue_entry_T_1745 = mux(issue_sel_3, entries_ld[3].bits.opa.valid, UInt<1>(0h0)) node _issue_entry_T_1746 = mux(issue_sel_4, entries_ld[4].bits.opa.valid, UInt<1>(0h0)) node _issue_entry_T_1747 = mux(issue_sel_5, entries_ld[5].bits.opa.valid, UInt<1>(0h0)) node _issue_entry_T_1748 = mux(issue_sel_6, entries_ld[6].bits.opa.valid, UInt<1>(0h0)) node _issue_entry_T_1749 = mux(issue_sel_7, entries_ld[7].bits.opa.valid, UInt<1>(0h0)) node _issue_entry_T_1750 = or(_issue_entry_T_1742, _issue_entry_T_1743) node _issue_entry_T_1751 = or(_issue_entry_T_1750, _issue_entry_T_1744) node _issue_entry_T_1752 = or(_issue_entry_T_1751, _issue_entry_T_1745) node _issue_entry_T_1753 = or(_issue_entry_T_1752, _issue_entry_T_1746) node _issue_entry_T_1754 = or(_issue_entry_T_1753, _issue_entry_T_1747) node _issue_entry_T_1755 = or(_issue_entry_T_1754, _issue_entry_T_1748) node _issue_entry_T_1756 = or(_issue_entry_T_1755, _issue_entry_T_1749) wire _issue_entry_WIRE_139 : UInt<1> connect _issue_entry_WIRE_139, _issue_entry_T_1756 connect _issue_entry_WIRE_116.valid, _issue_entry_WIRE_139 connect _issue_entry_WIRE.opa, _issue_entry_WIRE_116 node _issue_entry_T_1757 = mux(issue_sel_0, entries_ld[0].bits.is_config, UInt<1>(0h0)) node _issue_entry_T_1758 = mux(issue_sel_1, entries_ld[1].bits.is_config, UInt<1>(0h0)) node _issue_entry_T_1759 = mux(issue_sel_2, entries_ld[2].bits.is_config, UInt<1>(0h0)) node _issue_entry_T_1760 = mux(issue_sel_3, entries_ld[3].bits.is_config, UInt<1>(0h0)) node _issue_entry_T_1761 = mux(issue_sel_4, entries_ld[4].bits.is_config, UInt<1>(0h0)) node _issue_entry_T_1762 = mux(issue_sel_5, entries_ld[5].bits.is_config, UInt<1>(0h0)) node _issue_entry_T_1763 = mux(issue_sel_6, entries_ld[6].bits.is_config, UInt<1>(0h0)) node _issue_entry_T_1764 = mux(issue_sel_7, entries_ld[7].bits.is_config, UInt<1>(0h0)) node _issue_entry_T_1765 = or(_issue_entry_T_1757, _issue_entry_T_1758) node _issue_entry_T_1766 = or(_issue_entry_T_1765, _issue_entry_T_1759) node _issue_entry_T_1767 = or(_issue_entry_T_1766, _issue_entry_T_1760) node _issue_entry_T_1768 = or(_issue_entry_T_1767, _issue_entry_T_1761) node _issue_entry_T_1769 = or(_issue_entry_T_1768, _issue_entry_T_1762) node _issue_entry_T_1770 = or(_issue_entry_T_1769, _issue_entry_T_1763) node _issue_entry_T_1771 = or(_issue_entry_T_1770, _issue_entry_T_1764) wire _issue_entry_WIRE_140 : UInt<1> connect _issue_entry_WIRE_140, _issue_entry_T_1771 connect _issue_entry_WIRE.is_config, _issue_entry_WIRE_140 node _issue_entry_T_1772 = mux(issue_sel_0, entries_ld[0].bits.q, UInt<1>(0h0)) node _issue_entry_T_1773 = mux(issue_sel_1, entries_ld[1].bits.q, UInt<1>(0h0)) node _issue_entry_T_1774 = mux(issue_sel_2, entries_ld[2].bits.q, UInt<1>(0h0)) node _issue_entry_T_1775 = mux(issue_sel_3, entries_ld[3].bits.q, UInt<1>(0h0)) node _issue_entry_T_1776 = mux(issue_sel_4, entries_ld[4].bits.q, UInt<1>(0h0)) node _issue_entry_T_1777 = mux(issue_sel_5, entries_ld[5].bits.q, UInt<1>(0h0)) node _issue_entry_T_1778 = mux(issue_sel_6, entries_ld[6].bits.q, UInt<1>(0h0)) node _issue_entry_T_1779 = mux(issue_sel_7, entries_ld[7].bits.q, UInt<1>(0h0)) node _issue_entry_T_1780 = or(_issue_entry_T_1772, _issue_entry_T_1773) node _issue_entry_T_1781 = or(_issue_entry_T_1780, _issue_entry_T_1774) node _issue_entry_T_1782 = or(_issue_entry_T_1781, _issue_entry_T_1775) node _issue_entry_T_1783 = or(_issue_entry_T_1782, _issue_entry_T_1776) node _issue_entry_T_1784 = or(_issue_entry_T_1783, _issue_entry_T_1777) node _issue_entry_T_1785 = or(_issue_entry_T_1784, _issue_entry_T_1778) node _issue_entry_T_1786 = or(_issue_entry_T_1785, _issue_entry_T_1779) wire _issue_entry_WIRE_141 : UInt<2> connect _issue_entry_WIRE_141, _issue_entry_T_1786 connect _issue_entry_WIRE.q, _issue_entry_WIRE_141 connect issue_entry.bits, _issue_entry_WIRE node _issue_entry_T_1787 = mux(issue_sel_0, entries_ld[0].valid, UInt<1>(0h0)) node _issue_entry_T_1788 = mux(issue_sel_1, entries_ld[1].valid, UInt<1>(0h0)) node _issue_entry_T_1789 = mux(issue_sel_2, entries_ld[2].valid, UInt<1>(0h0)) node _issue_entry_T_1790 = mux(issue_sel_3, entries_ld[3].valid, UInt<1>(0h0)) node _issue_entry_T_1791 = mux(issue_sel_4, entries_ld[4].valid, UInt<1>(0h0)) node _issue_entry_T_1792 = mux(issue_sel_5, entries_ld[5].valid, UInt<1>(0h0)) node _issue_entry_T_1793 = mux(issue_sel_6, entries_ld[6].valid, UInt<1>(0h0)) node _issue_entry_T_1794 = mux(issue_sel_7, entries_ld[7].valid, UInt<1>(0h0)) node _issue_entry_T_1795 = or(_issue_entry_T_1787, _issue_entry_T_1788) node _issue_entry_T_1796 = or(_issue_entry_T_1795, _issue_entry_T_1789) node _issue_entry_T_1797 = or(_issue_entry_T_1796, _issue_entry_T_1790) node _issue_entry_T_1798 = or(_issue_entry_T_1797, _issue_entry_T_1791) node _issue_entry_T_1799 = or(_issue_entry_T_1798, _issue_entry_T_1792) node _issue_entry_T_1800 = or(_issue_entry_T_1799, _issue_entry_T_1793) node _issue_entry_T_1801 = or(_issue_entry_T_1800, _issue_entry_T_1794) wire _issue_entry_WIRE_142 : UInt<1> connect _issue_entry_WIRE_142, _issue_entry_T_1801 connect issue_entry.valid, _issue_entry_WIRE_142 node _io_issue_ld_valid_T = or(issue_valids_0, issue_valids_1) node _io_issue_ld_valid_T_1 = or(_io_issue_ld_valid_T, issue_valids_2) node _io_issue_ld_valid_T_2 = or(_io_issue_ld_valid_T_1, issue_valids_3) node _io_issue_ld_valid_T_3 = or(_io_issue_ld_valid_T_2, issue_valids_4) node _io_issue_ld_valid_T_4 = or(_io_issue_ld_valid_T_3, issue_valids_5) node _io_issue_ld_valid_T_5 = or(_io_issue_ld_valid_T_4, issue_valids_6) node _io_issue_ld_valid_T_6 = or(_io_issue_ld_valid_T_5, issue_valids_7) connect io.issue.ld.valid, _io_issue_ld_valid_T_6 connect io.issue.ld.cmd, issue_entry.bits.cmd connect io.issue.ld.rob_id, global_issue_id node _T_4832 = and(io.issue.ld.valid, io.issue.ld.ready) when _T_4832 : when issue_sel_0 : connect entries_ld[0].bits.issued, UInt<1>(0h1) node _entries_ld_0_valid_T = eq(entries_ld[0].bits.complete_on_issue, UInt<1>(0h0)) connect entries_ld[0].valid, _entries_ld_0_valid_T when issue_sel_1 : connect entries_ld[1].bits.issued, UInt<1>(0h1) node _entries_ld_1_valid_T = eq(entries_ld[1].bits.complete_on_issue, UInt<1>(0h0)) connect entries_ld[1].valid, _entries_ld_1_valid_T when issue_sel_2 : connect entries_ld[2].bits.issued, UInt<1>(0h1) node _entries_ld_2_valid_T = eq(entries_ld[2].bits.complete_on_issue, UInt<1>(0h0)) connect entries_ld[2].valid, _entries_ld_2_valid_T when issue_sel_3 : connect entries_ld[3].bits.issued, UInt<1>(0h1) node _entries_ld_3_valid_T = eq(entries_ld[3].bits.complete_on_issue, UInt<1>(0h0)) connect entries_ld[3].valid, _entries_ld_3_valid_T when issue_sel_4 : connect entries_ld[4].bits.issued, UInt<1>(0h1) node _entries_ld_4_valid_T = eq(entries_ld[4].bits.complete_on_issue, UInt<1>(0h0)) connect entries_ld[4].valid, _entries_ld_4_valid_T when issue_sel_5 : connect entries_ld[5].bits.issued, UInt<1>(0h1) node _entries_ld_5_valid_T = eq(entries_ld[5].bits.complete_on_issue, UInt<1>(0h0)) connect entries_ld[5].valid, _entries_ld_5_valid_T when issue_sel_6 : connect entries_ld[6].bits.issued, UInt<1>(0h1) node _entries_ld_6_valid_T = eq(entries_ld[6].bits.complete_on_issue, UInt<1>(0h0)) connect entries_ld[6].valid, _entries_ld_6_valid_T when issue_sel_7 : connect entries_ld[7].bits.issued, UInt<1>(0h1) node _entries_ld_7_valid_T = eq(entries_ld[7].bits.complete_on_issue, UInt<1>(0h0)) connect entries_ld[7].valid, _entries_ld_7_valid_T node _T_4833 = eq(UInt<2>(0h0), UInt<2>(0h0)) when _T_4833 : connect entries_ld[0].bits.deps_ld[issue_id], UInt<1>(0h0) else : when issue_entry.bits.complete_on_issue : connect entries_ld[0].bits.deps_ld[issue_id], UInt<1>(0h0) node _T_4834 = eq(UInt<2>(0h0), UInt<2>(0h0)) when _T_4834 : connect entries_ld[1].bits.deps_ld[issue_id], UInt<1>(0h0) else : when issue_entry.bits.complete_on_issue : connect entries_ld[1].bits.deps_ld[issue_id], UInt<1>(0h0) node _T_4835 = eq(UInt<2>(0h0), UInt<2>(0h0)) when _T_4835 : connect entries_ld[2].bits.deps_ld[issue_id], UInt<1>(0h0) else : when issue_entry.bits.complete_on_issue : connect entries_ld[2].bits.deps_ld[issue_id], UInt<1>(0h0) node _T_4836 = eq(UInt<2>(0h0), UInt<2>(0h0)) when _T_4836 : connect entries_ld[3].bits.deps_ld[issue_id], UInt<1>(0h0) else : when issue_entry.bits.complete_on_issue : connect entries_ld[3].bits.deps_ld[issue_id], UInt<1>(0h0) node _T_4837 = eq(UInt<2>(0h0), UInt<2>(0h0)) when _T_4837 : connect entries_ld[4].bits.deps_ld[issue_id], UInt<1>(0h0) else : when issue_entry.bits.complete_on_issue : connect entries_ld[4].bits.deps_ld[issue_id], UInt<1>(0h0) node _T_4838 = eq(UInt<2>(0h0), UInt<2>(0h0)) when _T_4838 : connect entries_ld[5].bits.deps_ld[issue_id], UInt<1>(0h0) else : when issue_entry.bits.complete_on_issue : connect entries_ld[5].bits.deps_ld[issue_id], UInt<1>(0h0) node _T_4839 = eq(UInt<2>(0h0), UInt<2>(0h0)) when _T_4839 : connect entries_ld[6].bits.deps_ld[issue_id], UInt<1>(0h0) else : when issue_entry.bits.complete_on_issue : connect entries_ld[6].bits.deps_ld[issue_id], UInt<1>(0h0) node _T_4840 = eq(UInt<2>(0h0), UInt<2>(0h0)) when _T_4840 : connect entries_ld[7].bits.deps_ld[issue_id], UInt<1>(0h0) else : when issue_entry.bits.complete_on_issue : connect entries_ld[7].bits.deps_ld[issue_id], UInt<1>(0h0) node _T_4841 = eq(UInt<2>(0h0), UInt<2>(0h1)) when _T_4841 : connect entries_ex[0].bits.deps_ld[issue_id], UInt<1>(0h0) else : when issue_entry.bits.complete_on_issue : connect entries_ex[0].bits.deps_ld[issue_id], UInt<1>(0h0) node _T_4842 = eq(UInt<2>(0h0), UInt<2>(0h1)) when _T_4842 : connect entries_ex[1].bits.deps_ld[issue_id], UInt<1>(0h0) else : when issue_entry.bits.complete_on_issue : connect entries_ex[1].bits.deps_ld[issue_id], UInt<1>(0h0) node _T_4843 = eq(UInt<2>(0h0), UInt<2>(0h1)) when _T_4843 : connect entries_ex[2].bits.deps_ld[issue_id], UInt<1>(0h0) else : when issue_entry.bits.complete_on_issue : connect entries_ex[2].bits.deps_ld[issue_id], UInt<1>(0h0) node _T_4844 = eq(UInt<2>(0h0), UInt<2>(0h1)) when _T_4844 : connect entries_ex[3].bits.deps_ld[issue_id], UInt<1>(0h0) else : when issue_entry.bits.complete_on_issue : connect entries_ex[3].bits.deps_ld[issue_id], UInt<1>(0h0) node _T_4845 = eq(UInt<2>(0h0), UInt<2>(0h1)) when _T_4845 : connect entries_ex[4].bits.deps_ld[issue_id], UInt<1>(0h0) else : when issue_entry.bits.complete_on_issue : connect entries_ex[4].bits.deps_ld[issue_id], UInt<1>(0h0) node _T_4846 = eq(UInt<2>(0h0), UInt<2>(0h1)) when _T_4846 : connect entries_ex[5].bits.deps_ld[issue_id], UInt<1>(0h0) else : when issue_entry.bits.complete_on_issue : connect entries_ex[5].bits.deps_ld[issue_id], UInt<1>(0h0) node _T_4847 = eq(UInt<2>(0h0), UInt<2>(0h1)) when _T_4847 : connect entries_ex[6].bits.deps_ld[issue_id], UInt<1>(0h0) else : when issue_entry.bits.complete_on_issue : connect entries_ex[6].bits.deps_ld[issue_id], UInt<1>(0h0) node _T_4848 = eq(UInt<2>(0h0), UInt<2>(0h1)) when _T_4848 : connect entries_ex[7].bits.deps_ld[issue_id], UInt<1>(0h0) else : when issue_entry.bits.complete_on_issue : connect entries_ex[7].bits.deps_ld[issue_id], UInt<1>(0h0) node _T_4849 = eq(UInt<2>(0h0), UInt<2>(0h1)) when _T_4849 : connect entries_ex[8].bits.deps_ld[issue_id], UInt<1>(0h0) else : when issue_entry.bits.complete_on_issue : connect entries_ex[8].bits.deps_ld[issue_id], UInt<1>(0h0) node _T_4850 = eq(UInt<2>(0h0), UInt<2>(0h1)) when _T_4850 : connect entries_ex[9].bits.deps_ld[issue_id], UInt<1>(0h0) else : when issue_entry.bits.complete_on_issue : connect entries_ex[9].bits.deps_ld[issue_id], UInt<1>(0h0) node _T_4851 = eq(UInt<2>(0h0), UInt<2>(0h1)) when _T_4851 : connect entries_ex[10].bits.deps_ld[issue_id], UInt<1>(0h0) else : when issue_entry.bits.complete_on_issue : connect entries_ex[10].bits.deps_ld[issue_id], UInt<1>(0h0) node _T_4852 = eq(UInt<2>(0h0), UInt<2>(0h1)) when _T_4852 : connect entries_ex[11].bits.deps_ld[issue_id], UInt<1>(0h0) else : when issue_entry.bits.complete_on_issue : connect entries_ex[11].bits.deps_ld[issue_id], UInt<1>(0h0) node _T_4853 = eq(UInt<2>(0h0), UInt<2>(0h1)) when _T_4853 : connect entries_ex[12].bits.deps_ld[issue_id], UInt<1>(0h0) else : when issue_entry.bits.complete_on_issue : connect entries_ex[12].bits.deps_ld[issue_id], UInt<1>(0h0) node _T_4854 = eq(UInt<2>(0h0), UInt<2>(0h1)) when _T_4854 : connect entries_ex[13].bits.deps_ld[issue_id], UInt<1>(0h0) else : when issue_entry.bits.complete_on_issue : connect entries_ex[13].bits.deps_ld[issue_id], UInt<1>(0h0) node _T_4855 = eq(UInt<2>(0h0), UInt<2>(0h1)) when _T_4855 : connect entries_ex[14].bits.deps_ld[issue_id], UInt<1>(0h0) else : when issue_entry.bits.complete_on_issue : connect entries_ex[14].bits.deps_ld[issue_id], UInt<1>(0h0) node _T_4856 = eq(UInt<2>(0h0), UInt<2>(0h1)) when _T_4856 : connect entries_ex[15].bits.deps_ld[issue_id], UInt<1>(0h0) else : when issue_entry.bits.complete_on_issue : connect entries_ex[15].bits.deps_ld[issue_id], UInt<1>(0h0) node _T_4857 = eq(UInt<2>(0h0), UInt<2>(0h2)) when _T_4857 : connect entries_st[0].bits.deps_ld[issue_id], UInt<1>(0h0) else : when issue_entry.bits.complete_on_issue : connect entries_st[0].bits.deps_ld[issue_id], UInt<1>(0h0) node _T_4858 = eq(UInt<2>(0h0), UInt<2>(0h2)) when _T_4858 : connect entries_st[1].bits.deps_ld[issue_id], UInt<1>(0h0) else : when issue_entry.bits.complete_on_issue : connect entries_st[1].bits.deps_ld[issue_id], UInt<1>(0h0) node _T_4859 = eq(UInt<2>(0h0), UInt<2>(0h2)) when _T_4859 : connect entries_st[2].bits.deps_ld[issue_id], UInt<1>(0h0) else : when issue_entry.bits.complete_on_issue : connect entries_st[2].bits.deps_ld[issue_id], UInt<1>(0h0) node _T_4860 = eq(UInt<2>(0h0), UInt<2>(0h2)) when _T_4860 : connect entries_st[3].bits.deps_ld[issue_id], UInt<1>(0h0) else : when issue_entry.bits.complete_on_issue : connect entries_st[3].bits.deps_ld[issue_id], UInt<1>(0h0) node _T_4861 = eq(UInt<2>(0h0), UInt<2>(0h0)) when _T_4861 : node _conv_ld_issue_completed_T = and(entries_ld[issue_id].bits.complete_on_issue, entries_ld[issue_id].bits.cmd.from_conv_fsm) connect conv_ld_issue_completed, _conv_ld_issue_completed_T node _T_4862 = eq(UInt<2>(0h0), UInt<2>(0h2)) when _T_4862 : node _conv_st_issue_completed_T = and(entries_ld[issue_id].bits.complete_on_issue, entries_ld[issue_id].bits.cmd.from_conv_fsm) connect conv_st_issue_completed, _conv_st_issue_completed_T node _T_4863 = eq(UInt<2>(0h0), UInt<2>(0h1)) when _T_4863 : node _conv_ex_issue_completed_T = and(entries_ld[issue_id].bits.complete_on_issue, entries_ld[issue_id].bits.cmd.from_conv_fsm) connect conv_ex_issue_completed, _conv_ex_issue_completed_T node _T_4864 = eq(UInt<2>(0h0), UInt<2>(0h0)) when _T_4864 : node _matmul_ld_issue_completed_T = and(entries_ld[issue_id].bits.complete_on_issue, entries_ld[issue_id].bits.cmd.from_matmul_fsm) connect matmul_ld_issue_completed, _matmul_ld_issue_completed_T node _T_4865 = eq(UInt<2>(0h0), UInt<2>(0h2)) when _T_4865 : node _matmul_st_issue_completed_T = and(entries_ld[issue_id].bits.complete_on_issue, entries_ld[issue_id].bits.cmd.from_matmul_fsm) connect matmul_st_issue_completed, _matmul_st_issue_completed_T node _T_4866 = eq(UInt<2>(0h0), UInt<2>(0h1)) when _T_4866 : node _matmul_ex_issue_completed_T = and(entries_ld[issue_id].bits.complete_on_issue, entries_ld[issue_id].bits.cmd.from_matmul_fsm) connect matmul_ex_issue_completed, _matmul_ex_issue_completed_T node _issue_valids_T_240 = or(entries_ex[0].bits.deps_ld[0], entries_ex[0].bits.deps_ld[1]) node _issue_valids_T_241 = or(_issue_valids_T_240, entries_ex[0].bits.deps_ld[2]) node _issue_valids_T_242 = or(_issue_valids_T_241, entries_ex[0].bits.deps_ld[3]) node _issue_valids_T_243 = or(_issue_valids_T_242, entries_ex[0].bits.deps_ld[4]) node _issue_valids_T_244 = or(_issue_valids_T_243, entries_ex[0].bits.deps_ld[5]) node _issue_valids_T_245 = or(_issue_valids_T_244, entries_ex[0].bits.deps_ld[6]) node _issue_valids_T_246 = or(_issue_valids_T_245, entries_ex[0].bits.deps_ld[7]) node _issue_valids_T_247 = or(entries_ex[0].bits.deps_ex[0], entries_ex[0].bits.deps_ex[1]) node _issue_valids_T_248 = or(_issue_valids_T_247, entries_ex[0].bits.deps_ex[2]) node _issue_valids_T_249 = or(_issue_valids_T_248, entries_ex[0].bits.deps_ex[3]) node _issue_valids_T_250 = or(_issue_valids_T_249, entries_ex[0].bits.deps_ex[4]) node _issue_valids_T_251 = or(_issue_valids_T_250, entries_ex[0].bits.deps_ex[5]) node _issue_valids_T_252 = or(_issue_valids_T_251, entries_ex[0].bits.deps_ex[6]) node _issue_valids_T_253 = or(_issue_valids_T_252, entries_ex[0].bits.deps_ex[7]) node _issue_valids_T_254 = or(_issue_valids_T_253, entries_ex[0].bits.deps_ex[8]) node _issue_valids_T_255 = or(_issue_valids_T_254, entries_ex[0].bits.deps_ex[9]) node _issue_valids_T_256 = or(_issue_valids_T_255, entries_ex[0].bits.deps_ex[10]) node _issue_valids_T_257 = or(_issue_valids_T_256, entries_ex[0].bits.deps_ex[11]) node _issue_valids_T_258 = or(_issue_valids_T_257, entries_ex[0].bits.deps_ex[12]) node _issue_valids_T_259 = or(_issue_valids_T_258, entries_ex[0].bits.deps_ex[13]) node _issue_valids_T_260 = or(_issue_valids_T_259, entries_ex[0].bits.deps_ex[14]) node _issue_valids_T_261 = or(_issue_valids_T_260, entries_ex[0].bits.deps_ex[15]) node _issue_valids_T_262 = or(_issue_valids_T_246, _issue_valids_T_261) node _issue_valids_T_263 = or(entries_ex[0].bits.deps_st[0], entries_ex[0].bits.deps_st[1]) node _issue_valids_T_264 = or(_issue_valids_T_263, entries_ex[0].bits.deps_st[2]) node _issue_valids_T_265 = or(_issue_valids_T_264, entries_ex[0].bits.deps_st[3]) node _issue_valids_T_266 = or(_issue_valids_T_262, _issue_valids_T_265) node _issue_valids_T_267 = eq(_issue_valids_T_266, UInt<1>(0h0)) node _issue_valids_T_268 = and(entries_ex[0].valid, _issue_valids_T_267) node _issue_valids_T_269 = eq(entries_ex[0].bits.issued, UInt<1>(0h0)) node issue_valids_0_1 = and(_issue_valids_T_268, _issue_valids_T_269) node _issue_valids_T_270 = or(entries_ex[1].bits.deps_ld[0], entries_ex[1].bits.deps_ld[1]) node _issue_valids_T_271 = or(_issue_valids_T_270, entries_ex[1].bits.deps_ld[2]) node _issue_valids_T_272 = or(_issue_valids_T_271, entries_ex[1].bits.deps_ld[3]) node _issue_valids_T_273 = or(_issue_valids_T_272, entries_ex[1].bits.deps_ld[4]) node _issue_valids_T_274 = or(_issue_valids_T_273, entries_ex[1].bits.deps_ld[5]) node _issue_valids_T_275 = or(_issue_valids_T_274, entries_ex[1].bits.deps_ld[6]) node _issue_valids_T_276 = or(_issue_valids_T_275, entries_ex[1].bits.deps_ld[7]) node _issue_valids_T_277 = or(entries_ex[1].bits.deps_ex[0], entries_ex[1].bits.deps_ex[1]) node _issue_valids_T_278 = or(_issue_valids_T_277, entries_ex[1].bits.deps_ex[2]) node _issue_valids_T_279 = or(_issue_valids_T_278, entries_ex[1].bits.deps_ex[3]) node _issue_valids_T_280 = or(_issue_valids_T_279, entries_ex[1].bits.deps_ex[4]) node _issue_valids_T_281 = or(_issue_valids_T_280, entries_ex[1].bits.deps_ex[5]) node _issue_valids_T_282 = or(_issue_valids_T_281, entries_ex[1].bits.deps_ex[6]) node _issue_valids_T_283 = or(_issue_valids_T_282, entries_ex[1].bits.deps_ex[7]) node _issue_valids_T_284 = or(_issue_valids_T_283, entries_ex[1].bits.deps_ex[8]) node _issue_valids_T_285 = or(_issue_valids_T_284, entries_ex[1].bits.deps_ex[9]) node _issue_valids_T_286 = or(_issue_valids_T_285, entries_ex[1].bits.deps_ex[10]) node _issue_valids_T_287 = or(_issue_valids_T_286, entries_ex[1].bits.deps_ex[11]) node _issue_valids_T_288 = or(_issue_valids_T_287, entries_ex[1].bits.deps_ex[12]) node _issue_valids_T_289 = or(_issue_valids_T_288, entries_ex[1].bits.deps_ex[13]) node _issue_valids_T_290 = or(_issue_valids_T_289, entries_ex[1].bits.deps_ex[14]) node _issue_valids_T_291 = or(_issue_valids_T_290, entries_ex[1].bits.deps_ex[15]) node _issue_valids_T_292 = or(_issue_valids_T_276, _issue_valids_T_291) node _issue_valids_T_293 = or(entries_ex[1].bits.deps_st[0], entries_ex[1].bits.deps_st[1]) node _issue_valids_T_294 = or(_issue_valids_T_293, entries_ex[1].bits.deps_st[2]) node _issue_valids_T_295 = or(_issue_valids_T_294, entries_ex[1].bits.deps_st[3]) node _issue_valids_T_296 = or(_issue_valids_T_292, _issue_valids_T_295) node _issue_valids_T_297 = eq(_issue_valids_T_296, UInt<1>(0h0)) node _issue_valids_T_298 = and(entries_ex[1].valid, _issue_valids_T_297) node _issue_valids_T_299 = eq(entries_ex[1].bits.issued, UInt<1>(0h0)) node issue_valids_1_1 = and(_issue_valids_T_298, _issue_valids_T_299) node _issue_valids_T_300 = or(entries_ex[2].bits.deps_ld[0], entries_ex[2].bits.deps_ld[1]) node _issue_valids_T_301 = or(_issue_valids_T_300, entries_ex[2].bits.deps_ld[2]) node _issue_valids_T_302 = or(_issue_valids_T_301, entries_ex[2].bits.deps_ld[3]) node _issue_valids_T_303 = or(_issue_valids_T_302, entries_ex[2].bits.deps_ld[4]) node _issue_valids_T_304 = or(_issue_valids_T_303, entries_ex[2].bits.deps_ld[5]) node _issue_valids_T_305 = or(_issue_valids_T_304, entries_ex[2].bits.deps_ld[6]) node _issue_valids_T_306 = or(_issue_valids_T_305, entries_ex[2].bits.deps_ld[7]) node _issue_valids_T_307 = or(entries_ex[2].bits.deps_ex[0], entries_ex[2].bits.deps_ex[1]) node _issue_valids_T_308 = or(_issue_valids_T_307, entries_ex[2].bits.deps_ex[2]) node _issue_valids_T_309 = or(_issue_valids_T_308, entries_ex[2].bits.deps_ex[3]) node _issue_valids_T_310 = or(_issue_valids_T_309, entries_ex[2].bits.deps_ex[4]) node _issue_valids_T_311 = or(_issue_valids_T_310, entries_ex[2].bits.deps_ex[5]) node _issue_valids_T_312 = or(_issue_valids_T_311, entries_ex[2].bits.deps_ex[6]) node _issue_valids_T_313 = or(_issue_valids_T_312, entries_ex[2].bits.deps_ex[7]) node _issue_valids_T_314 = or(_issue_valids_T_313, entries_ex[2].bits.deps_ex[8]) node _issue_valids_T_315 = or(_issue_valids_T_314, entries_ex[2].bits.deps_ex[9]) node _issue_valids_T_316 = or(_issue_valids_T_315, entries_ex[2].bits.deps_ex[10]) node _issue_valids_T_317 = or(_issue_valids_T_316, entries_ex[2].bits.deps_ex[11]) node _issue_valids_T_318 = or(_issue_valids_T_317, entries_ex[2].bits.deps_ex[12]) node _issue_valids_T_319 = or(_issue_valids_T_318, entries_ex[2].bits.deps_ex[13]) node _issue_valids_T_320 = or(_issue_valids_T_319, entries_ex[2].bits.deps_ex[14]) node _issue_valids_T_321 = or(_issue_valids_T_320, entries_ex[2].bits.deps_ex[15]) node _issue_valids_T_322 = or(_issue_valids_T_306, _issue_valids_T_321) node _issue_valids_T_323 = or(entries_ex[2].bits.deps_st[0], entries_ex[2].bits.deps_st[1]) node _issue_valids_T_324 = or(_issue_valids_T_323, entries_ex[2].bits.deps_st[2]) node _issue_valids_T_325 = or(_issue_valids_T_324, entries_ex[2].bits.deps_st[3]) node _issue_valids_T_326 = or(_issue_valids_T_322, _issue_valids_T_325) node _issue_valids_T_327 = eq(_issue_valids_T_326, UInt<1>(0h0)) node _issue_valids_T_328 = and(entries_ex[2].valid, _issue_valids_T_327) node _issue_valids_T_329 = eq(entries_ex[2].bits.issued, UInt<1>(0h0)) node issue_valids_2_1 = and(_issue_valids_T_328, _issue_valids_T_329) node _issue_valids_T_330 = or(entries_ex[3].bits.deps_ld[0], entries_ex[3].bits.deps_ld[1]) node _issue_valids_T_331 = or(_issue_valids_T_330, entries_ex[3].bits.deps_ld[2]) node _issue_valids_T_332 = or(_issue_valids_T_331, entries_ex[3].bits.deps_ld[3]) node _issue_valids_T_333 = or(_issue_valids_T_332, entries_ex[3].bits.deps_ld[4]) node _issue_valids_T_334 = or(_issue_valids_T_333, entries_ex[3].bits.deps_ld[5]) node _issue_valids_T_335 = or(_issue_valids_T_334, entries_ex[3].bits.deps_ld[6]) node _issue_valids_T_336 = or(_issue_valids_T_335, entries_ex[3].bits.deps_ld[7]) node _issue_valids_T_337 = or(entries_ex[3].bits.deps_ex[0], entries_ex[3].bits.deps_ex[1]) node _issue_valids_T_338 = or(_issue_valids_T_337, entries_ex[3].bits.deps_ex[2]) node _issue_valids_T_339 = or(_issue_valids_T_338, entries_ex[3].bits.deps_ex[3]) node _issue_valids_T_340 = or(_issue_valids_T_339, entries_ex[3].bits.deps_ex[4]) node _issue_valids_T_341 = or(_issue_valids_T_340, entries_ex[3].bits.deps_ex[5]) node _issue_valids_T_342 = or(_issue_valids_T_341, entries_ex[3].bits.deps_ex[6]) node _issue_valids_T_343 = or(_issue_valids_T_342, entries_ex[3].bits.deps_ex[7]) node _issue_valids_T_344 = or(_issue_valids_T_343, entries_ex[3].bits.deps_ex[8]) node _issue_valids_T_345 = or(_issue_valids_T_344, entries_ex[3].bits.deps_ex[9]) node _issue_valids_T_346 = or(_issue_valids_T_345, entries_ex[3].bits.deps_ex[10]) node _issue_valids_T_347 = or(_issue_valids_T_346, entries_ex[3].bits.deps_ex[11]) node _issue_valids_T_348 = or(_issue_valids_T_347, entries_ex[3].bits.deps_ex[12]) node _issue_valids_T_349 = or(_issue_valids_T_348, entries_ex[3].bits.deps_ex[13]) node _issue_valids_T_350 = or(_issue_valids_T_349, entries_ex[3].bits.deps_ex[14]) node _issue_valids_T_351 = or(_issue_valids_T_350, entries_ex[3].bits.deps_ex[15]) node _issue_valids_T_352 = or(_issue_valids_T_336, _issue_valids_T_351) node _issue_valids_T_353 = or(entries_ex[3].bits.deps_st[0], entries_ex[3].bits.deps_st[1]) node _issue_valids_T_354 = or(_issue_valids_T_353, entries_ex[3].bits.deps_st[2]) node _issue_valids_T_355 = or(_issue_valids_T_354, entries_ex[3].bits.deps_st[3]) node _issue_valids_T_356 = or(_issue_valids_T_352, _issue_valids_T_355) node _issue_valids_T_357 = eq(_issue_valids_T_356, UInt<1>(0h0)) node _issue_valids_T_358 = and(entries_ex[3].valid, _issue_valids_T_357) node _issue_valids_T_359 = eq(entries_ex[3].bits.issued, UInt<1>(0h0)) node issue_valids_3_1 = and(_issue_valids_T_358, _issue_valids_T_359) node _issue_valids_T_360 = or(entries_ex[4].bits.deps_ld[0], entries_ex[4].bits.deps_ld[1]) node _issue_valids_T_361 = or(_issue_valids_T_360, entries_ex[4].bits.deps_ld[2]) node _issue_valids_T_362 = or(_issue_valids_T_361, entries_ex[4].bits.deps_ld[3]) node _issue_valids_T_363 = or(_issue_valids_T_362, entries_ex[4].bits.deps_ld[4]) node _issue_valids_T_364 = or(_issue_valids_T_363, entries_ex[4].bits.deps_ld[5]) node _issue_valids_T_365 = or(_issue_valids_T_364, entries_ex[4].bits.deps_ld[6]) node _issue_valids_T_366 = or(_issue_valids_T_365, entries_ex[4].bits.deps_ld[7]) node _issue_valids_T_367 = or(entries_ex[4].bits.deps_ex[0], entries_ex[4].bits.deps_ex[1]) node _issue_valids_T_368 = or(_issue_valids_T_367, entries_ex[4].bits.deps_ex[2]) node _issue_valids_T_369 = or(_issue_valids_T_368, entries_ex[4].bits.deps_ex[3]) node _issue_valids_T_370 = or(_issue_valids_T_369, entries_ex[4].bits.deps_ex[4]) node _issue_valids_T_371 = or(_issue_valids_T_370, entries_ex[4].bits.deps_ex[5]) node _issue_valids_T_372 = or(_issue_valids_T_371, entries_ex[4].bits.deps_ex[6]) node _issue_valids_T_373 = or(_issue_valids_T_372, entries_ex[4].bits.deps_ex[7]) node _issue_valids_T_374 = or(_issue_valids_T_373, entries_ex[4].bits.deps_ex[8]) node _issue_valids_T_375 = or(_issue_valids_T_374, entries_ex[4].bits.deps_ex[9]) node _issue_valids_T_376 = or(_issue_valids_T_375, entries_ex[4].bits.deps_ex[10]) node _issue_valids_T_377 = or(_issue_valids_T_376, entries_ex[4].bits.deps_ex[11]) node _issue_valids_T_378 = or(_issue_valids_T_377, entries_ex[4].bits.deps_ex[12]) node _issue_valids_T_379 = or(_issue_valids_T_378, entries_ex[4].bits.deps_ex[13]) node _issue_valids_T_380 = or(_issue_valids_T_379, entries_ex[4].bits.deps_ex[14]) node _issue_valids_T_381 = or(_issue_valids_T_380, entries_ex[4].bits.deps_ex[15]) node _issue_valids_T_382 = or(_issue_valids_T_366, _issue_valids_T_381) node _issue_valids_T_383 = or(entries_ex[4].bits.deps_st[0], entries_ex[4].bits.deps_st[1]) node _issue_valids_T_384 = or(_issue_valids_T_383, entries_ex[4].bits.deps_st[2]) node _issue_valids_T_385 = or(_issue_valids_T_384, entries_ex[4].bits.deps_st[3]) node _issue_valids_T_386 = or(_issue_valids_T_382, _issue_valids_T_385) node _issue_valids_T_387 = eq(_issue_valids_T_386, UInt<1>(0h0)) node _issue_valids_T_388 = and(entries_ex[4].valid, _issue_valids_T_387) node _issue_valids_T_389 = eq(entries_ex[4].bits.issued, UInt<1>(0h0)) node issue_valids_4_1 = and(_issue_valids_T_388, _issue_valids_T_389) node _issue_valids_T_390 = or(entries_ex[5].bits.deps_ld[0], entries_ex[5].bits.deps_ld[1]) node _issue_valids_T_391 = or(_issue_valids_T_390, entries_ex[5].bits.deps_ld[2]) node _issue_valids_T_392 = or(_issue_valids_T_391, entries_ex[5].bits.deps_ld[3]) node _issue_valids_T_393 = or(_issue_valids_T_392, entries_ex[5].bits.deps_ld[4]) node _issue_valids_T_394 = or(_issue_valids_T_393, entries_ex[5].bits.deps_ld[5]) node _issue_valids_T_395 = or(_issue_valids_T_394, entries_ex[5].bits.deps_ld[6]) node _issue_valids_T_396 = or(_issue_valids_T_395, entries_ex[5].bits.deps_ld[7]) node _issue_valids_T_397 = or(entries_ex[5].bits.deps_ex[0], entries_ex[5].bits.deps_ex[1]) node _issue_valids_T_398 = or(_issue_valids_T_397, entries_ex[5].bits.deps_ex[2]) node _issue_valids_T_399 = or(_issue_valids_T_398, entries_ex[5].bits.deps_ex[3]) node _issue_valids_T_400 = or(_issue_valids_T_399, entries_ex[5].bits.deps_ex[4]) node _issue_valids_T_401 = or(_issue_valids_T_400, entries_ex[5].bits.deps_ex[5]) node _issue_valids_T_402 = or(_issue_valids_T_401, entries_ex[5].bits.deps_ex[6]) node _issue_valids_T_403 = or(_issue_valids_T_402, entries_ex[5].bits.deps_ex[7]) node _issue_valids_T_404 = or(_issue_valids_T_403, entries_ex[5].bits.deps_ex[8]) node _issue_valids_T_405 = or(_issue_valids_T_404, entries_ex[5].bits.deps_ex[9]) node _issue_valids_T_406 = or(_issue_valids_T_405, entries_ex[5].bits.deps_ex[10]) node _issue_valids_T_407 = or(_issue_valids_T_406, entries_ex[5].bits.deps_ex[11]) node _issue_valids_T_408 = or(_issue_valids_T_407, entries_ex[5].bits.deps_ex[12]) node _issue_valids_T_409 = or(_issue_valids_T_408, entries_ex[5].bits.deps_ex[13]) node _issue_valids_T_410 = or(_issue_valids_T_409, entries_ex[5].bits.deps_ex[14]) node _issue_valids_T_411 = or(_issue_valids_T_410, entries_ex[5].bits.deps_ex[15]) node _issue_valids_T_412 = or(_issue_valids_T_396, _issue_valids_T_411) node _issue_valids_T_413 = or(entries_ex[5].bits.deps_st[0], entries_ex[5].bits.deps_st[1]) node _issue_valids_T_414 = or(_issue_valids_T_413, entries_ex[5].bits.deps_st[2]) node _issue_valids_T_415 = or(_issue_valids_T_414, entries_ex[5].bits.deps_st[3]) node _issue_valids_T_416 = or(_issue_valids_T_412, _issue_valids_T_415) node _issue_valids_T_417 = eq(_issue_valids_T_416, UInt<1>(0h0)) node _issue_valids_T_418 = and(entries_ex[5].valid, _issue_valids_T_417) node _issue_valids_T_419 = eq(entries_ex[5].bits.issued, UInt<1>(0h0)) node issue_valids_5_1 = and(_issue_valids_T_418, _issue_valids_T_419) node _issue_valids_T_420 = or(entries_ex[6].bits.deps_ld[0], entries_ex[6].bits.deps_ld[1]) node _issue_valids_T_421 = or(_issue_valids_T_420, entries_ex[6].bits.deps_ld[2]) node _issue_valids_T_422 = or(_issue_valids_T_421, entries_ex[6].bits.deps_ld[3]) node _issue_valids_T_423 = or(_issue_valids_T_422, entries_ex[6].bits.deps_ld[4]) node _issue_valids_T_424 = or(_issue_valids_T_423, entries_ex[6].bits.deps_ld[5]) node _issue_valids_T_425 = or(_issue_valids_T_424, entries_ex[6].bits.deps_ld[6]) node _issue_valids_T_426 = or(_issue_valids_T_425, entries_ex[6].bits.deps_ld[7]) node _issue_valids_T_427 = or(entries_ex[6].bits.deps_ex[0], entries_ex[6].bits.deps_ex[1]) node _issue_valids_T_428 = or(_issue_valids_T_427, entries_ex[6].bits.deps_ex[2]) node _issue_valids_T_429 = or(_issue_valids_T_428, entries_ex[6].bits.deps_ex[3]) node _issue_valids_T_430 = or(_issue_valids_T_429, entries_ex[6].bits.deps_ex[4]) node _issue_valids_T_431 = or(_issue_valids_T_430, entries_ex[6].bits.deps_ex[5]) node _issue_valids_T_432 = or(_issue_valids_T_431, entries_ex[6].bits.deps_ex[6]) node _issue_valids_T_433 = or(_issue_valids_T_432, entries_ex[6].bits.deps_ex[7]) node _issue_valids_T_434 = or(_issue_valids_T_433, entries_ex[6].bits.deps_ex[8]) node _issue_valids_T_435 = or(_issue_valids_T_434, entries_ex[6].bits.deps_ex[9]) node _issue_valids_T_436 = or(_issue_valids_T_435, entries_ex[6].bits.deps_ex[10]) node _issue_valids_T_437 = or(_issue_valids_T_436, entries_ex[6].bits.deps_ex[11]) node _issue_valids_T_438 = or(_issue_valids_T_437, entries_ex[6].bits.deps_ex[12]) node _issue_valids_T_439 = or(_issue_valids_T_438, entries_ex[6].bits.deps_ex[13]) node _issue_valids_T_440 = or(_issue_valids_T_439, entries_ex[6].bits.deps_ex[14]) node _issue_valids_T_441 = or(_issue_valids_T_440, entries_ex[6].bits.deps_ex[15]) node _issue_valids_T_442 = or(_issue_valids_T_426, _issue_valids_T_441) node _issue_valids_T_443 = or(entries_ex[6].bits.deps_st[0], entries_ex[6].bits.deps_st[1]) node _issue_valids_T_444 = or(_issue_valids_T_443, entries_ex[6].bits.deps_st[2]) node _issue_valids_T_445 = or(_issue_valids_T_444, entries_ex[6].bits.deps_st[3]) node _issue_valids_T_446 = or(_issue_valids_T_442, _issue_valids_T_445) node _issue_valids_T_447 = eq(_issue_valids_T_446, UInt<1>(0h0)) node _issue_valids_T_448 = and(entries_ex[6].valid, _issue_valids_T_447) node _issue_valids_T_449 = eq(entries_ex[6].bits.issued, UInt<1>(0h0)) node issue_valids_6_1 = and(_issue_valids_T_448, _issue_valids_T_449) node _issue_valids_T_450 = or(entries_ex[7].bits.deps_ld[0], entries_ex[7].bits.deps_ld[1]) node _issue_valids_T_451 = or(_issue_valids_T_450, entries_ex[7].bits.deps_ld[2]) node _issue_valids_T_452 = or(_issue_valids_T_451, entries_ex[7].bits.deps_ld[3]) node _issue_valids_T_453 = or(_issue_valids_T_452, entries_ex[7].bits.deps_ld[4]) node _issue_valids_T_454 = or(_issue_valids_T_453, entries_ex[7].bits.deps_ld[5]) node _issue_valids_T_455 = or(_issue_valids_T_454, entries_ex[7].bits.deps_ld[6]) node _issue_valids_T_456 = or(_issue_valids_T_455, entries_ex[7].bits.deps_ld[7]) node _issue_valids_T_457 = or(entries_ex[7].bits.deps_ex[0], entries_ex[7].bits.deps_ex[1]) node _issue_valids_T_458 = or(_issue_valids_T_457, entries_ex[7].bits.deps_ex[2]) node _issue_valids_T_459 = or(_issue_valids_T_458, entries_ex[7].bits.deps_ex[3]) node _issue_valids_T_460 = or(_issue_valids_T_459, entries_ex[7].bits.deps_ex[4]) node _issue_valids_T_461 = or(_issue_valids_T_460, entries_ex[7].bits.deps_ex[5]) node _issue_valids_T_462 = or(_issue_valids_T_461, entries_ex[7].bits.deps_ex[6]) node _issue_valids_T_463 = or(_issue_valids_T_462, entries_ex[7].bits.deps_ex[7]) node _issue_valids_T_464 = or(_issue_valids_T_463, entries_ex[7].bits.deps_ex[8]) node _issue_valids_T_465 = or(_issue_valids_T_464, entries_ex[7].bits.deps_ex[9]) node _issue_valids_T_466 = or(_issue_valids_T_465, entries_ex[7].bits.deps_ex[10]) node _issue_valids_T_467 = or(_issue_valids_T_466, entries_ex[7].bits.deps_ex[11]) node _issue_valids_T_468 = or(_issue_valids_T_467, entries_ex[7].bits.deps_ex[12]) node _issue_valids_T_469 = or(_issue_valids_T_468, entries_ex[7].bits.deps_ex[13]) node _issue_valids_T_470 = or(_issue_valids_T_469, entries_ex[7].bits.deps_ex[14]) node _issue_valids_T_471 = or(_issue_valids_T_470, entries_ex[7].bits.deps_ex[15]) node _issue_valids_T_472 = or(_issue_valids_T_456, _issue_valids_T_471) node _issue_valids_T_473 = or(entries_ex[7].bits.deps_st[0], entries_ex[7].bits.deps_st[1]) node _issue_valids_T_474 = or(_issue_valids_T_473, entries_ex[7].bits.deps_st[2]) node _issue_valids_T_475 = or(_issue_valids_T_474, entries_ex[7].bits.deps_st[3]) node _issue_valids_T_476 = or(_issue_valids_T_472, _issue_valids_T_475) node _issue_valids_T_477 = eq(_issue_valids_T_476, UInt<1>(0h0)) node _issue_valids_T_478 = and(entries_ex[7].valid, _issue_valids_T_477) node _issue_valids_T_479 = eq(entries_ex[7].bits.issued, UInt<1>(0h0)) node issue_valids_7_1 = and(_issue_valids_T_478, _issue_valids_T_479) node _issue_valids_T_480 = or(entries_ex[8].bits.deps_ld[0], entries_ex[8].bits.deps_ld[1]) node _issue_valids_T_481 = or(_issue_valids_T_480, entries_ex[8].bits.deps_ld[2]) node _issue_valids_T_482 = or(_issue_valids_T_481, entries_ex[8].bits.deps_ld[3]) node _issue_valids_T_483 = or(_issue_valids_T_482, entries_ex[8].bits.deps_ld[4]) node _issue_valids_T_484 = or(_issue_valids_T_483, entries_ex[8].bits.deps_ld[5]) node _issue_valids_T_485 = or(_issue_valids_T_484, entries_ex[8].bits.deps_ld[6]) node _issue_valids_T_486 = or(_issue_valids_T_485, entries_ex[8].bits.deps_ld[7]) node _issue_valids_T_487 = or(entries_ex[8].bits.deps_ex[0], entries_ex[8].bits.deps_ex[1]) node _issue_valids_T_488 = or(_issue_valids_T_487, entries_ex[8].bits.deps_ex[2]) node _issue_valids_T_489 = or(_issue_valids_T_488, entries_ex[8].bits.deps_ex[3]) node _issue_valids_T_490 = or(_issue_valids_T_489, entries_ex[8].bits.deps_ex[4]) node _issue_valids_T_491 = or(_issue_valids_T_490, entries_ex[8].bits.deps_ex[5]) node _issue_valids_T_492 = or(_issue_valids_T_491, entries_ex[8].bits.deps_ex[6]) node _issue_valids_T_493 = or(_issue_valids_T_492, entries_ex[8].bits.deps_ex[7]) node _issue_valids_T_494 = or(_issue_valids_T_493, entries_ex[8].bits.deps_ex[8]) node _issue_valids_T_495 = or(_issue_valids_T_494, entries_ex[8].bits.deps_ex[9]) node _issue_valids_T_496 = or(_issue_valids_T_495, entries_ex[8].bits.deps_ex[10]) node _issue_valids_T_497 = or(_issue_valids_T_496, entries_ex[8].bits.deps_ex[11]) node _issue_valids_T_498 = or(_issue_valids_T_497, entries_ex[8].bits.deps_ex[12]) node _issue_valids_T_499 = or(_issue_valids_T_498, entries_ex[8].bits.deps_ex[13]) node _issue_valids_T_500 = or(_issue_valids_T_499, entries_ex[8].bits.deps_ex[14]) node _issue_valids_T_501 = or(_issue_valids_T_500, entries_ex[8].bits.deps_ex[15]) node _issue_valids_T_502 = or(_issue_valids_T_486, _issue_valids_T_501) node _issue_valids_T_503 = or(entries_ex[8].bits.deps_st[0], entries_ex[8].bits.deps_st[1]) node _issue_valids_T_504 = or(_issue_valids_T_503, entries_ex[8].bits.deps_st[2]) node _issue_valids_T_505 = or(_issue_valids_T_504, entries_ex[8].bits.deps_st[3]) node _issue_valids_T_506 = or(_issue_valids_T_502, _issue_valids_T_505) node _issue_valids_T_507 = eq(_issue_valids_T_506, UInt<1>(0h0)) node _issue_valids_T_508 = and(entries_ex[8].valid, _issue_valids_T_507) node _issue_valids_T_509 = eq(entries_ex[8].bits.issued, UInt<1>(0h0)) node issue_valids_8 = and(_issue_valids_T_508, _issue_valids_T_509) node _issue_valids_T_510 = or(entries_ex[9].bits.deps_ld[0], entries_ex[9].bits.deps_ld[1]) node _issue_valids_T_511 = or(_issue_valids_T_510, entries_ex[9].bits.deps_ld[2]) node _issue_valids_T_512 = or(_issue_valids_T_511, entries_ex[9].bits.deps_ld[3]) node _issue_valids_T_513 = or(_issue_valids_T_512, entries_ex[9].bits.deps_ld[4]) node _issue_valids_T_514 = or(_issue_valids_T_513, entries_ex[9].bits.deps_ld[5]) node _issue_valids_T_515 = or(_issue_valids_T_514, entries_ex[9].bits.deps_ld[6]) node _issue_valids_T_516 = or(_issue_valids_T_515, entries_ex[9].bits.deps_ld[7]) node _issue_valids_T_517 = or(entries_ex[9].bits.deps_ex[0], entries_ex[9].bits.deps_ex[1]) node _issue_valids_T_518 = or(_issue_valids_T_517, entries_ex[9].bits.deps_ex[2]) node _issue_valids_T_519 = or(_issue_valids_T_518, entries_ex[9].bits.deps_ex[3]) node _issue_valids_T_520 = or(_issue_valids_T_519, entries_ex[9].bits.deps_ex[4]) node _issue_valids_T_521 = or(_issue_valids_T_520, entries_ex[9].bits.deps_ex[5]) node _issue_valids_T_522 = or(_issue_valids_T_521, entries_ex[9].bits.deps_ex[6]) node _issue_valids_T_523 = or(_issue_valids_T_522, entries_ex[9].bits.deps_ex[7]) node _issue_valids_T_524 = or(_issue_valids_T_523, entries_ex[9].bits.deps_ex[8]) node _issue_valids_T_525 = or(_issue_valids_T_524, entries_ex[9].bits.deps_ex[9]) node _issue_valids_T_526 = or(_issue_valids_T_525, entries_ex[9].bits.deps_ex[10]) node _issue_valids_T_527 = or(_issue_valids_T_526, entries_ex[9].bits.deps_ex[11]) node _issue_valids_T_528 = or(_issue_valids_T_527, entries_ex[9].bits.deps_ex[12]) node _issue_valids_T_529 = or(_issue_valids_T_528, entries_ex[9].bits.deps_ex[13]) node _issue_valids_T_530 = or(_issue_valids_T_529, entries_ex[9].bits.deps_ex[14]) node _issue_valids_T_531 = or(_issue_valids_T_530, entries_ex[9].bits.deps_ex[15]) node _issue_valids_T_532 = or(_issue_valids_T_516, _issue_valids_T_531) node _issue_valids_T_533 = or(entries_ex[9].bits.deps_st[0], entries_ex[9].bits.deps_st[1]) node _issue_valids_T_534 = or(_issue_valids_T_533, entries_ex[9].bits.deps_st[2]) node _issue_valids_T_535 = or(_issue_valids_T_534, entries_ex[9].bits.deps_st[3]) node _issue_valids_T_536 = or(_issue_valids_T_532, _issue_valids_T_535) node _issue_valids_T_537 = eq(_issue_valids_T_536, UInt<1>(0h0)) node _issue_valids_T_538 = and(entries_ex[9].valid, _issue_valids_T_537) node _issue_valids_T_539 = eq(entries_ex[9].bits.issued, UInt<1>(0h0)) node issue_valids_9 = and(_issue_valids_T_538, _issue_valids_T_539) node _issue_valids_T_540 = or(entries_ex[10].bits.deps_ld[0], entries_ex[10].bits.deps_ld[1]) node _issue_valids_T_541 = or(_issue_valids_T_540, entries_ex[10].bits.deps_ld[2]) node _issue_valids_T_542 = or(_issue_valids_T_541, entries_ex[10].bits.deps_ld[3]) node _issue_valids_T_543 = or(_issue_valids_T_542, entries_ex[10].bits.deps_ld[4]) node _issue_valids_T_544 = or(_issue_valids_T_543, entries_ex[10].bits.deps_ld[5]) node _issue_valids_T_545 = or(_issue_valids_T_544, entries_ex[10].bits.deps_ld[6]) node _issue_valids_T_546 = or(_issue_valids_T_545, entries_ex[10].bits.deps_ld[7]) node _issue_valids_T_547 = or(entries_ex[10].bits.deps_ex[0], entries_ex[10].bits.deps_ex[1]) node _issue_valids_T_548 = or(_issue_valids_T_547, entries_ex[10].bits.deps_ex[2]) node _issue_valids_T_549 = or(_issue_valids_T_548, entries_ex[10].bits.deps_ex[3]) node _issue_valids_T_550 = or(_issue_valids_T_549, entries_ex[10].bits.deps_ex[4]) node _issue_valids_T_551 = or(_issue_valids_T_550, entries_ex[10].bits.deps_ex[5]) node _issue_valids_T_552 = or(_issue_valids_T_551, entries_ex[10].bits.deps_ex[6]) node _issue_valids_T_553 = or(_issue_valids_T_552, entries_ex[10].bits.deps_ex[7]) node _issue_valids_T_554 = or(_issue_valids_T_553, entries_ex[10].bits.deps_ex[8]) node _issue_valids_T_555 = or(_issue_valids_T_554, entries_ex[10].bits.deps_ex[9]) node _issue_valids_T_556 = or(_issue_valids_T_555, entries_ex[10].bits.deps_ex[10]) node _issue_valids_T_557 = or(_issue_valids_T_556, entries_ex[10].bits.deps_ex[11]) node _issue_valids_T_558 = or(_issue_valids_T_557, entries_ex[10].bits.deps_ex[12]) node _issue_valids_T_559 = or(_issue_valids_T_558, entries_ex[10].bits.deps_ex[13]) node _issue_valids_T_560 = or(_issue_valids_T_559, entries_ex[10].bits.deps_ex[14]) node _issue_valids_T_561 = or(_issue_valids_T_560, entries_ex[10].bits.deps_ex[15]) node _issue_valids_T_562 = or(_issue_valids_T_546, _issue_valids_T_561) node _issue_valids_T_563 = or(entries_ex[10].bits.deps_st[0], entries_ex[10].bits.deps_st[1]) node _issue_valids_T_564 = or(_issue_valids_T_563, entries_ex[10].bits.deps_st[2]) node _issue_valids_T_565 = or(_issue_valids_T_564, entries_ex[10].bits.deps_st[3]) node _issue_valids_T_566 = or(_issue_valids_T_562, _issue_valids_T_565) node _issue_valids_T_567 = eq(_issue_valids_T_566, UInt<1>(0h0)) node _issue_valids_T_568 = and(entries_ex[10].valid, _issue_valids_T_567) node _issue_valids_T_569 = eq(entries_ex[10].bits.issued, UInt<1>(0h0)) node issue_valids_10 = and(_issue_valids_T_568, _issue_valids_T_569) node _issue_valids_T_570 = or(entries_ex[11].bits.deps_ld[0], entries_ex[11].bits.deps_ld[1]) node _issue_valids_T_571 = or(_issue_valids_T_570, entries_ex[11].bits.deps_ld[2]) node _issue_valids_T_572 = or(_issue_valids_T_571, entries_ex[11].bits.deps_ld[3]) node _issue_valids_T_573 = or(_issue_valids_T_572, entries_ex[11].bits.deps_ld[4]) node _issue_valids_T_574 = or(_issue_valids_T_573, entries_ex[11].bits.deps_ld[5]) node _issue_valids_T_575 = or(_issue_valids_T_574, entries_ex[11].bits.deps_ld[6]) node _issue_valids_T_576 = or(_issue_valids_T_575, entries_ex[11].bits.deps_ld[7]) node _issue_valids_T_577 = or(entries_ex[11].bits.deps_ex[0], entries_ex[11].bits.deps_ex[1]) node _issue_valids_T_578 = or(_issue_valids_T_577, entries_ex[11].bits.deps_ex[2]) node _issue_valids_T_579 = or(_issue_valids_T_578, entries_ex[11].bits.deps_ex[3]) node _issue_valids_T_580 = or(_issue_valids_T_579, entries_ex[11].bits.deps_ex[4]) node _issue_valids_T_581 = or(_issue_valids_T_580, entries_ex[11].bits.deps_ex[5]) node _issue_valids_T_582 = or(_issue_valids_T_581, entries_ex[11].bits.deps_ex[6]) node _issue_valids_T_583 = or(_issue_valids_T_582, entries_ex[11].bits.deps_ex[7]) node _issue_valids_T_584 = or(_issue_valids_T_583, entries_ex[11].bits.deps_ex[8]) node _issue_valids_T_585 = or(_issue_valids_T_584, entries_ex[11].bits.deps_ex[9]) node _issue_valids_T_586 = or(_issue_valids_T_585, entries_ex[11].bits.deps_ex[10]) node _issue_valids_T_587 = or(_issue_valids_T_586, entries_ex[11].bits.deps_ex[11]) node _issue_valids_T_588 = or(_issue_valids_T_587, entries_ex[11].bits.deps_ex[12]) node _issue_valids_T_589 = or(_issue_valids_T_588, entries_ex[11].bits.deps_ex[13]) node _issue_valids_T_590 = or(_issue_valids_T_589, entries_ex[11].bits.deps_ex[14]) node _issue_valids_T_591 = or(_issue_valids_T_590, entries_ex[11].bits.deps_ex[15]) node _issue_valids_T_592 = or(_issue_valids_T_576, _issue_valids_T_591) node _issue_valids_T_593 = or(entries_ex[11].bits.deps_st[0], entries_ex[11].bits.deps_st[1]) node _issue_valids_T_594 = or(_issue_valids_T_593, entries_ex[11].bits.deps_st[2]) node _issue_valids_T_595 = or(_issue_valids_T_594, entries_ex[11].bits.deps_st[3]) node _issue_valids_T_596 = or(_issue_valids_T_592, _issue_valids_T_595) node _issue_valids_T_597 = eq(_issue_valids_T_596, UInt<1>(0h0)) node _issue_valids_T_598 = and(entries_ex[11].valid, _issue_valids_T_597) node _issue_valids_T_599 = eq(entries_ex[11].bits.issued, UInt<1>(0h0)) node issue_valids_11 = and(_issue_valids_T_598, _issue_valids_T_599) node _issue_valids_T_600 = or(entries_ex[12].bits.deps_ld[0], entries_ex[12].bits.deps_ld[1]) node _issue_valids_T_601 = or(_issue_valids_T_600, entries_ex[12].bits.deps_ld[2]) node _issue_valids_T_602 = or(_issue_valids_T_601, entries_ex[12].bits.deps_ld[3]) node _issue_valids_T_603 = or(_issue_valids_T_602, entries_ex[12].bits.deps_ld[4]) node _issue_valids_T_604 = or(_issue_valids_T_603, entries_ex[12].bits.deps_ld[5]) node _issue_valids_T_605 = or(_issue_valids_T_604, entries_ex[12].bits.deps_ld[6]) node _issue_valids_T_606 = or(_issue_valids_T_605, entries_ex[12].bits.deps_ld[7]) node _issue_valids_T_607 = or(entries_ex[12].bits.deps_ex[0], entries_ex[12].bits.deps_ex[1]) node _issue_valids_T_608 = or(_issue_valids_T_607, entries_ex[12].bits.deps_ex[2]) node _issue_valids_T_609 = or(_issue_valids_T_608, entries_ex[12].bits.deps_ex[3]) node _issue_valids_T_610 = or(_issue_valids_T_609, entries_ex[12].bits.deps_ex[4]) node _issue_valids_T_611 = or(_issue_valids_T_610, entries_ex[12].bits.deps_ex[5]) node _issue_valids_T_612 = or(_issue_valids_T_611, entries_ex[12].bits.deps_ex[6]) node _issue_valids_T_613 = or(_issue_valids_T_612, entries_ex[12].bits.deps_ex[7]) node _issue_valids_T_614 = or(_issue_valids_T_613, entries_ex[12].bits.deps_ex[8]) node _issue_valids_T_615 = or(_issue_valids_T_614, entries_ex[12].bits.deps_ex[9]) node _issue_valids_T_616 = or(_issue_valids_T_615, entries_ex[12].bits.deps_ex[10]) node _issue_valids_T_617 = or(_issue_valids_T_616, entries_ex[12].bits.deps_ex[11]) node _issue_valids_T_618 = or(_issue_valids_T_617, entries_ex[12].bits.deps_ex[12]) node _issue_valids_T_619 = or(_issue_valids_T_618, entries_ex[12].bits.deps_ex[13]) node _issue_valids_T_620 = or(_issue_valids_T_619, entries_ex[12].bits.deps_ex[14]) node _issue_valids_T_621 = or(_issue_valids_T_620, entries_ex[12].bits.deps_ex[15]) node _issue_valids_T_622 = or(_issue_valids_T_606, _issue_valids_T_621) node _issue_valids_T_623 = or(entries_ex[12].bits.deps_st[0], entries_ex[12].bits.deps_st[1]) node _issue_valids_T_624 = or(_issue_valids_T_623, entries_ex[12].bits.deps_st[2]) node _issue_valids_T_625 = or(_issue_valids_T_624, entries_ex[12].bits.deps_st[3]) node _issue_valids_T_626 = or(_issue_valids_T_622, _issue_valids_T_625) node _issue_valids_T_627 = eq(_issue_valids_T_626, UInt<1>(0h0)) node _issue_valids_T_628 = and(entries_ex[12].valid, _issue_valids_T_627) node _issue_valids_T_629 = eq(entries_ex[12].bits.issued, UInt<1>(0h0)) node issue_valids_12 = and(_issue_valids_T_628, _issue_valids_T_629) node _issue_valids_T_630 = or(entries_ex[13].bits.deps_ld[0], entries_ex[13].bits.deps_ld[1]) node _issue_valids_T_631 = or(_issue_valids_T_630, entries_ex[13].bits.deps_ld[2]) node _issue_valids_T_632 = or(_issue_valids_T_631, entries_ex[13].bits.deps_ld[3]) node _issue_valids_T_633 = or(_issue_valids_T_632, entries_ex[13].bits.deps_ld[4]) node _issue_valids_T_634 = or(_issue_valids_T_633, entries_ex[13].bits.deps_ld[5]) node _issue_valids_T_635 = or(_issue_valids_T_634, entries_ex[13].bits.deps_ld[6]) node _issue_valids_T_636 = or(_issue_valids_T_635, entries_ex[13].bits.deps_ld[7]) node _issue_valids_T_637 = or(entries_ex[13].bits.deps_ex[0], entries_ex[13].bits.deps_ex[1]) node _issue_valids_T_638 = or(_issue_valids_T_637, entries_ex[13].bits.deps_ex[2]) node _issue_valids_T_639 = or(_issue_valids_T_638, entries_ex[13].bits.deps_ex[3]) node _issue_valids_T_640 = or(_issue_valids_T_639, entries_ex[13].bits.deps_ex[4]) node _issue_valids_T_641 = or(_issue_valids_T_640, entries_ex[13].bits.deps_ex[5]) node _issue_valids_T_642 = or(_issue_valids_T_641, entries_ex[13].bits.deps_ex[6]) node _issue_valids_T_643 = or(_issue_valids_T_642, entries_ex[13].bits.deps_ex[7]) node _issue_valids_T_644 = or(_issue_valids_T_643, entries_ex[13].bits.deps_ex[8]) node _issue_valids_T_645 = or(_issue_valids_T_644, entries_ex[13].bits.deps_ex[9]) node _issue_valids_T_646 = or(_issue_valids_T_645, entries_ex[13].bits.deps_ex[10]) node _issue_valids_T_647 = or(_issue_valids_T_646, entries_ex[13].bits.deps_ex[11]) node _issue_valids_T_648 = or(_issue_valids_T_647, entries_ex[13].bits.deps_ex[12]) node _issue_valids_T_649 = or(_issue_valids_T_648, entries_ex[13].bits.deps_ex[13]) node _issue_valids_T_650 = or(_issue_valids_T_649, entries_ex[13].bits.deps_ex[14]) node _issue_valids_T_651 = or(_issue_valids_T_650, entries_ex[13].bits.deps_ex[15]) node _issue_valids_T_652 = or(_issue_valids_T_636, _issue_valids_T_651) node _issue_valids_T_653 = or(entries_ex[13].bits.deps_st[0], entries_ex[13].bits.deps_st[1]) node _issue_valids_T_654 = or(_issue_valids_T_653, entries_ex[13].bits.deps_st[2]) node _issue_valids_T_655 = or(_issue_valids_T_654, entries_ex[13].bits.deps_st[3]) node _issue_valids_T_656 = or(_issue_valids_T_652, _issue_valids_T_655) node _issue_valids_T_657 = eq(_issue_valids_T_656, UInt<1>(0h0)) node _issue_valids_T_658 = and(entries_ex[13].valid, _issue_valids_T_657) node _issue_valids_T_659 = eq(entries_ex[13].bits.issued, UInt<1>(0h0)) node issue_valids_13 = and(_issue_valids_T_658, _issue_valids_T_659) node _issue_valids_T_660 = or(entries_ex[14].bits.deps_ld[0], entries_ex[14].bits.deps_ld[1]) node _issue_valids_T_661 = or(_issue_valids_T_660, entries_ex[14].bits.deps_ld[2]) node _issue_valids_T_662 = or(_issue_valids_T_661, entries_ex[14].bits.deps_ld[3]) node _issue_valids_T_663 = or(_issue_valids_T_662, entries_ex[14].bits.deps_ld[4]) node _issue_valids_T_664 = or(_issue_valids_T_663, entries_ex[14].bits.deps_ld[5]) node _issue_valids_T_665 = or(_issue_valids_T_664, entries_ex[14].bits.deps_ld[6]) node _issue_valids_T_666 = or(_issue_valids_T_665, entries_ex[14].bits.deps_ld[7]) node _issue_valids_T_667 = or(entries_ex[14].bits.deps_ex[0], entries_ex[14].bits.deps_ex[1]) node _issue_valids_T_668 = or(_issue_valids_T_667, entries_ex[14].bits.deps_ex[2]) node _issue_valids_T_669 = or(_issue_valids_T_668, entries_ex[14].bits.deps_ex[3]) node _issue_valids_T_670 = or(_issue_valids_T_669, entries_ex[14].bits.deps_ex[4]) node _issue_valids_T_671 = or(_issue_valids_T_670, entries_ex[14].bits.deps_ex[5]) node _issue_valids_T_672 = or(_issue_valids_T_671, entries_ex[14].bits.deps_ex[6]) node _issue_valids_T_673 = or(_issue_valids_T_672, entries_ex[14].bits.deps_ex[7]) node _issue_valids_T_674 = or(_issue_valids_T_673, entries_ex[14].bits.deps_ex[8]) node _issue_valids_T_675 = or(_issue_valids_T_674, entries_ex[14].bits.deps_ex[9]) node _issue_valids_T_676 = or(_issue_valids_T_675, entries_ex[14].bits.deps_ex[10]) node _issue_valids_T_677 = or(_issue_valids_T_676, entries_ex[14].bits.deps_ex[11]) node _issue_valids_T_678 = or(_issue_valids_T_677, entries_ex[14].bits.deps_ex[12]) node _issue_valids_T_679 = or(_issue_valids_T_678, entries_ex[14].bits.deps_ex[13]) node _issue_valids_T_680 = or(_issue_valids_T_679, entries_ex[14].bits.deps_ex[14]) node _issue_valids_T_681 = or(_issue_valids_T_680, entries_ex[14].bits.deps_ex[15]) node _issue_valids_T_682 = or(_issue_valids_T_666, _issue_valids_T_681) node _issue_valids_T_683 = or(entries_ex[14].bits.deps_st[0], entries_ex[14].bits.deps_st[1]) node _issue_valids_T_684 = or(_issue_valids_T_683, entries_ex[14].bits.deps_st[2]) node _issue_valids_T_685 = or(_issue_valids_T_684, entries_ex[14].bits.deps_st[3]) node _issue_valids_T_686 = or(_issue_valids_T_682, _issue_valids_T_685) node _issue_valids_T_687 = eq(_issue_valids_T_686, UInt<1>(0h0)) node _issue_valids_T_688 = and(entries_ex[14].valid, _issue_valids_T_687) node _issue_valids_T_689 = eq(entries_ex[14].bits.issued, UInt<1>(0h0)) node issue_valids_14 = and(_issue_valids_T_688, _issue_valids_T_689) node _issue_valids_T_690 = or(entries_ex[15].bits.deps_ld[0], entries_ex[15].bits.deps_ld[1]) node _issue_valids_T_691 = or(_issue_valids_T_690, entries_ex[15].bits.deps_ld[2]) node _issue_valids_T_692 = or(_issue_valids_T_691, entries_ex[15].bits.deps_ld[3]) node _issue_valids_T_693 = or(_issue_valids_T_692, entries_ex[15].bits.deps_ld[4]) node _issue_valids_T_694 = or(_issue_valids_T_693, entries_ex[15].bits.deps_ld[5]) node _issue_valids_T_695 = or(_issue_valids_T_694, entries_ex[15].bits.deps_ld[6]) node _issue_valids_T_696 = or(_issue_valids_T_695, entries_ex[15].bits.deps_ld[7]) node _issue_valids_T_697 = or(entries_ex[15].bits.deps_ex[0], entries_ex[15].bits.deps_ex[1]) node _issue_valids_T_698 = or(_issue_valids_T_697, entries_ex[15].bits.deps_ex[2]) node _issue_valids_T_699 = or(_issue_valids_T_698, entries_ex[15].bits.deps_ex[3]) node _issue_valids_T_700 = or(_issue_valids_T_699, entries_ex[15].bits.deps_ex[4]) node _issue_valids_T_701 = or(_issue_valids_T_700, entries_ex[15].bits.deps_ex[5]) node _issue_valids_T_702 = or(_issue_valids_T_701, entries_ex[15].bits.deps_ex[6]) node _issue_valids_T_703 = or(_issue_valids_T_702, entries_ex[15].bits.deps_ex[7]) node _issue_valids_T_704 = or(_issue_valids_T_703, entries_ex[15].bits.deps_ex[8]) node _issue_valids_T_705 = or(_issue_valids_T_704, entries_ex[15].bits.deps_ex[9]) node _issue_valids_T_706 = or(_issue_valids_T_705, entries_ex[15].bits.deps_ex[10]) node _issue_valids_T_707 = or(_issue_valids_T_706, entries_ex[15].bits.deps_ex[11]) node _issue_valids_T_708 = or(_issue_valids_T_707, entries_ex[15].bits.deps_ex[12]) node _issue_valids_T_709 = or(_issue_valids_T_708, entries_ex[15].bits.deps_ex[13]) node _issue_valids_T_710 = or(_issue_valids_T_709, entries_ex[15].bits.deps_ex[14]) node _issue_valids_T_711 = or(_issue_valids_T_710, entries_ex[15].bits.deps_ex[15]) node _issue_valids_T_712 = or(_issue_valids_T_696, _issue_valids_T_711) node _issue_valids_T_713 = or(entries_ex[15].bits.deps_st[0], entries_ex[15].bits.deps_st[1]) node _issue_valids_T_714 = or(_issue_valids_T_713, entries_ex[15].bits.deps_st[2]) node _issue_valids_T_715 = or(_issue_valids_T_714, entries_ex[15].bits.deps_st[3]) node _issue_valids_T_716 = or(_issue_valids_T_712, _issue_valids_T_715) node _issue_valids_T_717 = eq(_issue_valids_T_716, UInt<1>(0h0)) node _issue_valids_T_718 = and(entries_ex[15].valid, _issue_valids_T_717) node _issue_valids_T_719 = eq(entries_ex[15].bits.issued, UInt<1>(0h0)) node issue_valids_15 = and(_issue_valids_T_718, _issue_valids_T_719) node _issue_sel_enc_T_7 = mux(issue_valids_15, UInt<16>(0h8000), UInt<16>(0h0)) node _issue_sel_enc_T_8 = mux(issue_valids_14, UInt<16>(0h4000), _issue_sel_enc_T_7) node _issue_sel_enc_T_9 = mux(issue_valids_13, UInt<16>(0h2000), _issue_sel_enc_T_8) node _issue_sel_enc_T_10 = mux(issue_valids_12, UInt<16>(0h1000), _issue_sel_enc_T_9) node _issue_sel_enc_T_11 = mux(issue_valids_11, UInt<16>(0h800), _issue_sel_enc_T_10) node _issue_sel_enc_T_12 = mux(issue_valids_10, UInt<16>(0h400), _issue_sel_enc_T_11) node _issue_sel_enc_T_13 = mux(issue_valids_9, UInt<16>(0h200), _issue_sel_enc_T_12) node _issue_sel_enc_T_14 = mux(issue_valids_8, UInt<16>(0h100), _issue_sel_enc_T_13) node _issue_sel_enc_T_15 = mux(issue_valids_7_1, UInt<16>(0h80), _issue_sel_enc_T_14) node _issue_sel_enc_T_16 = mux(issue_valids_6_1, UInt<16>(0h40), _issue_sel_enc_T_15) node _issue_sel_enc_T_17 = mux(issue_valids_5_1, UInt<16>(0h20), _issue_sel_enc_T_16) node _issue_sel_enc_T_18 = mux(issue_valids_4_1, UInt<16>(0h10), _issue_sel_enc_T_17) node _issue_sel_enc_T_19 = mux(issue_valids_3_1, UInt<16>(0h8), _issue_sel_enc_T_18) node _issue_sel_enc_T_20 = mux(issue_valids_2_1, UInt<16>(0h4), _issue_sel_enc_T_19) node _issue_sel_enc_T_21 = mux(issue_valids_1_1, UInt<16>(0h2), _issue_sel_enc_T_20) node issue_sel_enc_1 = mux(issue_valids_0_1, UInt<16>(0h1), _issue_sel_enc_T_21) node issue_sel_0_1 = bits(issue_sel_enc_1, 0, 0) node issue_sel_1_1 = bits(issue_sel_enc_1, 1, 1) node issue_sel_2_1 = bits(issue_sel_enc_1, 2, 2) node issue_sel_3_1 = bits(issue_sel_enc_1, 3, 3) node issue_sel_4_1 = bits(issue_sel_enc_1, 4, 4) node issue_sel_5_1 = bits(issue_sel_enc_1, 5, 5) node issue_sel_6_1 = bits(issue_sel_enc_1, 6, 6) node issue_sel_7_1 = bits(issue_sel_enc_1, 7, 7) node issue_sel_8 = bits(issue_sel_enc_1, 8, 8) node issue_sel_9 = bits(issue_sel_enc_1, 9, 9) node issue_sel_10 = bits(issue_sel_enc_1, 10, 10) node issue_sel_11 = bits(issue_sel_enc_1, 11, 11) node issue_sel_12 = bits(issue_sel_enc_1, 12, 12) node issue_sel_13 = bits(issue_sel_enc_1, 13, 13) node issue_sel_14 = bits(issue_sel_enc_1, 14, 14) node issue_sel_15 = bits(issue_sel_enc_1, 15, 15) node issue_id_lo_lo_lo = cat(issue_sel_1_1, issue_sel_0_1) node issue_id_lo_lo_hi = cat(issue_sel_3_1, issue_sel_2_1) node issue_id_lo_lo_1 = cat(issue_id_lo_lo_hi, issue_id_lo_lo_lo) node issue_id_lo_hi_lo = cat(issue_sel_5_1, issue_sel_4_1) node issue_id_lo_hi_hi = cat(issue_sel_7_1, issue_sel_6_1) node issue_id_lo_hi_1 = cat(issue_id_lo_hi_hi, issue_id_lo_hi_lo) node issue_id_lo_3 = cat(issue_id_lo_hi_1, issue_id_lo_lo_1) node issue_id_hi_lo_lo = cat(issue_sel_9, issue_sel_8) node issue_id_hi_lo_hi = cat(issue_sel_11, issue_sel_10) node issue_id_hi_lo_1 = cat(issue_id_hi_lo_hi, issue_id_hi_lo_lo) node issue_id_hi_hi_lo = cat(issue_sel_13, issue_sel_12) node issue_id_hi_hi_hi = cat(issue_sel_15, issue_sel_14) node issue_id_hi_hi_1 = cat(issue_id_hi_hi_hi, issue_id_hi_hi_lo) node issue_id_hi_3 = cat(issue_id_hi_hi_1, issue_id_hi_lo_1) node _issue_id_T_7 = cat(issue_id_hi_3, issue_id_lo_3) node issue_id_hi_4 = bits(_issue_id_T_7, 15, 8) node issue_id_lo_4 = bits(_issue_id_T_7, 7, 0) node _issue_id_T_8 = orr(issue_id_hi_4) node _issue_id_T_9 = or(issue_id_hi_4, issue_id_lo_4) node issue_id_hi_5 = bits(_issue_id_T_9, 7, 4) node issue_id_lo_5 = bits(_issue_id_T_9, 3, 0) node _issue_id_T_10 = orr(issue_id_hi_5) node _issue_id_T_11 = or(issue_id_hi_5, issue_id_lo_5) node issue_id_hi_6 = bits(_issue_id_T_11, 3, 2) node issue_id_lo_6 = bits(_issue_id_T_11, 1, 0) node _issue_id_T_12 = orr(issue_id_hi_6) node _issue_id_T_13 = or(issue_id_hi_6, issue_id_lo_6) node _issue_id_T_14 = bits(_issue_id_T_13, 1, 1) node _issue_id_T_15 = cat(_issue_id_T_12, _issue_id_T_14) node _issue_id_T_16 = cat(_issue_id_T_10, _issue_id_T_15) node issue_id_1 = cat(_issue_id_T_8, _issue_id_T_16) node global_issue_id_1 = cat(UInt<2>(0h1), issue_id_1) wire issue_entry_1 : { valid : UInt<1>, bits : { q : UInt<2>, is_config : UInt<1>, opa : { valid : UInt<1>, bits : { start : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, end : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, wraps_around : UInt<1>}}, opa_is_dst : UInt<1>, opb : { valid : UInt<1>, bits : { start : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, end : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, wraps_around : UInt<1>}}, issued : UInt<1>, complete_on_issue : UInt<1>, cmd : { cmd : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, rob_id : { valid : UInt<1>, bits : UInt<6>}, from_matmul_fsm : UInt<1>, from_conv_fsm : UInt<1>}, deps_ld : UInt<1>[8], deps_ex : UInt<1>[16], deps_st : UInt<1>[4], allocated_at : UInt<32>}} wire _issue_entry_WIRE_143 : { q : UInt<2>, is_config : UInt<1>, opa : { valid : UInt<1>, bits : { start : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, end : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, wraps_around : UInt<1>}}, opa_is_dst : UInt<1>, opb : { valid : UInt<1>, bits : { start : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, end : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, wraps_around : UInt<1>}}, issued : UInt<1>, complete_on_issue : UInt<1>, cmd : { cmd : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, rob_id : { valid : UInt<1>, bits : UInt<6>}, from_matmul_fsm : UInt<1>, from_conv_fsm : UInt<1>}, deps_ld : UInt<1>[8], deps_ex : UInt<1>[16], deps_st : UInt<1>[4], allocated_at : UInt<32>} node _issue_entry_T_1802 = mux(issue_sel_0_1, entries_ex[0].bits.allocated_at, UInt<1>(0h0)) node _issue_entry_T_1803 = mux(issue_sel_1_1, entries_ex[1].bits.allocated_at, UInt<1>(0h0)) node _issue_entry_T_1804 = mux(issue_sel_2_1, entries_ex[2].bits.allocated_at, UInt<1>(0h0)) node _issue_entry_T_1805 = mux(issue_sel_3_1, entries_ex[3].bits.allocated_at, UInt<1>(0h0)) node _issue_entry_T_1806 = mux(issue_sel_4_1, entries_ex[4].bits.allocated_at, UInt<1>(0h0)) node _issue_entry_T_1807 = mux(issue_sel_5_1, entries_ex[5].bits.allocated_at, UInt<1>(0h0)) node _issue_entry_T_1808 = mux(issue_sel_6_1, entries_ex[6].bits.allocated_at, UInt<1>(0h0)) node _issue_entry_T_1809 = mux(issue_sel_7_1, entries_ex[7].bits.allocated_at, UInt<1>(0h0)) node _issue_entry_T_1810 = mux(issue_sel_8, entries_ex[8].bits.allocated_at, UInt<1>(0h0)) node _issue_entry_T_1811 = mux(issue_sel_9, entries_ex[9].bits.allocated_at, UInt<1>(0h0)) node _issue_entry_T_1812 = mux(issue_sel_10, entries_ex[10].bits.allocated_at, UInt<1>(0h0)) node _issue_entry_T_1813 = mux(issue_sel_11, entries_ex[11].bits.allocated_at, UInt<1>(0h0)) node _issue_entry_T_1814 = mux(issue_sel_12, entries_ex[12].bits.allocated_at, UInt<1>(0h0)) node _issue_entry_T_1815 = mux(issue_sel_13, entries_ex[13].bits.allocated_at, UInt<1>(0h0)) node _issue_entry_T_1816 = mux(issue_sel_14, entries_ex[14].bits.allocated_at, UInt<1>(0h0)) node _issue_entry_T_1817 = mux(issue_sel_15, entries_ex[15].bits.allocated_at, UInt<1>(0h0)) node _issue_entry_T_1818 = or(_issue_entry_T_1802, _issue_entry_T_1803) node _issue_entry_T_1819 = or(_issue_entry_T_1818, _issue_entry_T_1804) node _issue_entry_T_1820 = or(_issue_entry_T_1819, _issue_entry_T_1805) node _issue_entry_T_1821 = or(_issue_entry_T_1820, _issue_entry_T_1806) node _issue_entry_T_1822 = or(_issue_entry_T_1821, _issue_entry_T_1807) node _issue_entry_T_1823 = or(_issue_entry_T_1822, _issue_entry_T_1808) node _issue_entry_T_1824 = or(_issue_entry_T_1823, _issue_entry_T_1809) node _issue_entry_T_1825 = or(_issue_entry_T_1824, _issue_entry_T_1810) node _issue_entry_T_1826 = or(_issue_entry_T_1825, _issue_entry_T_1811) node _issue_entry_T_1827 = or(_issue_entry_T_1826, _issue_entry_T_1812) node _issue_entry_T_1828 = or(_issue_entry_T_1827, _issue_entry_T_1813) node _issue_entry_T_1829 = or(_issue_entry_T_1828, _issue_entry_T_1814) node _issue_entry_T_1830 = or(_issue_entry_T_1829, _issue_entry_T_1815) node _issue_entry_T_1831 = or(_issue_entry_T_1830, _issue_entry_T_1816) node _issue_entry_T_1832 = or(_issue_entry_T_1831, _issue_entry_T_1817) wire _issue_entry_WIRE_144 : UInt<32> connect _issue_entry_WIRE_144, _issue_entry_T_1832 connect _issue_entry_WIRE_143.allocated_at, _issue_entry_WIRE_144 wire _issue_entry_WIRE_145 : UInt<1>[4] node _issue_entry_T_1833 = mux(issue_sel_0_1, entries_ex[0].bits.deps_st[0], UInt<1>(0h0)) node _issue_entry_T_1834 = mux(issue_sel_1_1, entries_ex[1].bits.deps_st[0], UInt<1>(0h0)) node _issue_entry_T_1835 = mux(issue_sel_2_1, entries_ex[2].bits.deps_st[0], UInt<1>(0h0)) node _issue_entry_T_1836 = mux(issue_sel_3_1, entries_ex[3].bits.deps_st[0], UInt<1>(0h0)) node _issue_entry_T_1837 = mux(issue_sel_4_1, entries_ex[4].bits.deps_st[0], UInt<1>(0h0)) node _issue_entry_T_1838 = mux(issue_sel_5_1, entries_ex[5].bits.deps_st[0], UInt<1>(0h0)) node _issue_entry_T_1839 = mux(issue_sel_6_1, entries_ex[6].bits.deps_st[0], UInt<1>(0h0)) node _issue_entry_T_1840 = mux(issue_sel_7_1, entries_ex[7].bits.deps_st[0], UInt<1>(0h0)) node _issue_entry_T_1841 = mux(issue_sel_8, entries_ex[8].bits.deps_st[0], UInt<1>(0h0)) node _issue_entry_T_1842 = mux(issue_sel_9, entries_ex[9].bits.deps_st[0], UInt<1>(0h0)) node _issue_entry_T_1843 = mux(issue_sel_10, entries_ex[10].bits.deps_st[0], UInt<1>(0h0)) node _issue_entry_T_1844 = mux(issue_sel_11, entries_ex[11].bits.deps_st[0], UInt<1>(0h0)) node _issue_entry_T_1845 = mux(issue_sel_12, entries_ex[12].bits.deps_st[0], UInt<1>(0h0)) node _issue_entry_T_1846 = mux(issue_sel_13, entries_ex[13].bits.deps_st[0], UInt<1>(0h0)) node _issue_entry_T_1847 = mux(issue_sel_14, entries_ex[14].bits.deps_st[0], UInt<1>(0h0)) node _issue_entry_T_1848 = mux(issue_sel_15, entries_ex[15].bits.deps_st[0], UInt<1>(0h0)) node _issue_entry_T_1849 = or(_issue_entry_T_1833, _issue_entry_T_1834) node _issue_entry_T_1850 = or(_issue_entry_T_1849, _issue_entry_T_1835) node _issue_entry_T_1851 = or(_issue_entry_T_1850, _issue_entry_T_1836) node _issue_entry_T_1852 = or(_issue_entry_T_1851, _issue_entry_T_1837) node _issue_entry_T_1853 = or(_issue_entry_T_1852, _issue_entry_T_1838) node _issue_entry_T_1854 = or(_issue_entry_T_1853, _issue_entry_T_1839) node _issue_entry_T_1855 = or(_issue_entry_T_1854, _issue_entry_T_1840) node _issue_entry_T_1856 = or(_issue_entry_T_1855, _issue_entry_T_1841) node _issue_entry_T_1857 = or(_issue_entry_T_1856, _issue_entry_T_1842) node _issue_entry_T_1858 = or(_issue_entry_T_1857, _issue_entry_T_1843) node _issue_entry_T_1859 = or(_issue_entry_T_1858, _issue_entry_T_1844) node _issue_entry_T_1860 = or(_issue_entry_T_1859, _issue_entry_T_1845) node _issue_entry_T_1861 = or(_issue_entry_T_1860, _issue_entry_T_1846) node _issue_entry_T_1862 = or(_issue_entry_T_1861, _issue_entry_T_1847) node _issue_entry_T_1863 = or(_issue_entry_T_1862, _issue_entry_T_1848) wire _issue_entry_WIRE_146 : UInt<1> connect _issue_entry_WIRE_146, _issue_entry_T_1863 connect _issue_entry_WIRE_145[0], _issue_entry_WIRE_146 node _issue_entry_T_1864 = mux(issue_sel_0_1, entries_ex[0].bits.deps_st[1], UInt<1>(0h0)) node _issue_entry_T_1865 = mux(issue_sel_1_1, entries_ex[1].bits.deps_st[1], UInt<1>(0h0)) node _issue_entry_T_1866 = mux(issue_sel_2_1, entries_ex[2].bits.deps_st[1], UInt<1>(0h0)) node _issue_entry_T_1867 = mux(issue_sel_3_1, entries_ex[3].bits.deps_st[1], UInt<1>(0h0)) node _issue_entry_T_1868 = mux(issue_sel_4_1, entries_ex[4].bits.deps_st[1], UInt<1>(0h0)) node _issue_entry_T_1869 = mux(issue_sel_5_1, entries_ex[5].bits.deps_st[1], UInt<1>(0h0)) node _issue_entry_T_1870 = mux(issue_sel_6_1, entries_ex[6].bits.deps_st[1], UInt<1>(0h0)) node _issue_entry_T_1871 = mux(issue_sel_7_1, entries_ex[7].bits.deps_st[1], UInt<1>(0h0)) node _issue_entry_T_1872 = mux(issue_sel_8, entries_ex[8].bits.deps_st[1], UInt<1>(0h0)) node _issue_entry_T_1873 = mux(issue_sel_9, entries_ex[9].bits.deps_st[1], UInt<1>(0h0)) node _issue_entry_T_1874 = mux(issue_sel_10, entries_ex[10].bits.deps_st[1], UInt<1>(0h0)) node _issue_entry_T_1875 = mux(issue_sel_11, entries_ex[11].bits.deps_st[1], UInt<1>(0h0)) node _issue_entry_T_1876 = mux(issue_sel_12, entries_ex[12].bits.deps_st[1], UInt<1>(0h0)) node _issue_entry_T_1877 = mux(issue_sel_13, entries_ex[13].bits.deps_st[1], UInt<1>(0h0)) node _issue_entry_T_1878 = mux(issue_sel_14, entries_ex[14].bits.deps_st[1], UInt<1>(0h0)) node _issue_entry_T_1879 = mux(issue_sel_15, entries_ex[15].bits.deps_st[1], UInt<1>(0h0)) node _issue_entry_T_1880 = or(_issue_entry_T_1864, _issue_entry_T_1865) node _issue_entry_T_1881 = or(_issue_entry_T_1880, _issue_entry_T_1866) node _issue_entry_T_1882 = or(_issue_entry_T_1881, _issue_entry_T_1867) node _issue_entry_T_1883 = or(_issue_entry_T_1882, _issue_entry_T_1868) node _issue_entry_T_1884 = or(_issue_entry_T_1883, _issue_entry_T_1869) node _issue_entry_T_1885 = or(_issue_entry_T_1884, _issue_entry_T_1870) node _issue_entry_T_1886 = or(_issue_entry_T_1885, _issue_entry_T_1871) node _issue_entry_T_1887 = or(_issue_entry_T_1886, _issue_entry_T_1872) node _issue_entry_T_1888 = or(_issue_entry_T_1887, _issue_entry_T_1873) node _issue_entry_T_1889 = or(_issue_entry_T_1888, _issue_entry_T_1874) node _issue_entry_T_1890 = or(_issue_entry_T_1889, _issue_entry_T_1875) node _issue_entry_T_1891 = or(_issue_entry_T_1890, _issue_entry_T_1876) node _issue_entry_T_1892 = or(_issue_entry_T_1891, _issue_entry_T_1877) node _issue_entry_T_1893 = or(_issue_entry_T_1892, _issue_entry_T_1878) node _issue_entry_T_1894 = or(_issue_entry_T_1893, _issue_entry_T_1879) wire _issue_entry_WIRE_147 : UInt<1> connect _issue_entry_WIRE_147, _issue_entry_T_1894 connect _issue_entry_WIRE_145[1], _issue_entry_WIRE_147 node _issue_entry_T_1895 = mux(issue_sel_0_1, entries_ex[0].bits.deps_st[2], UInt<1>(0h0)) node _issue_entry_T_1896 = mux(issue_sel_1_1, entries_ex[1].bits.deps_st[2], UInt<1>(0h0)) node _issue_entry_T_1897 = mux(issue_sel_2_1, entries_ex[2].bits.deps_st[2], UInt<1>(0h0)) node _issue_entry_T_1898 = mux(issue_sel_3_1, entries_ex[3].bits.deps_st[2], UInt<1>(0h0)) node _issue_entry_T_1899 = mux(issue_sel_4_1, entries_ex[4].bits.deps_st[2], UInt<1>(0h0)) node _issue_entry_T_1900 = mux(issue_sel_5_1, entries_ex[5].bits.deps_st[2], UInt<1>(0h0)) node _issue_entry_T_1901 = mux(issue_sel_6_1, entries_ex[6].bits.deps_st[2], UInt<1>(0h0)) node _issue_entry_T_1902 = mux(issue_sel_7_1, entries_ex[7].bits.deps_st[2], UInt<1>(0h0)) node _issue_entry_T_1903 = mux(issue_sel_8, entries_ex[8].bits.deps_st[2], UInt<1>(0h0)) node _issue_entry_T_1904 = mux(issue_sel_9, entries_ex[9].bits.deps_st[2], UInt<1>(0h0)) node _issue_entry_T_1905 = mux(issue_sel_10, entries_ex[10].bits.deps_st[2], UInt<1>(0h0)) node _issue_entry_T_1906 = mux(issue_sel_11, entries_ex[11].bits.deps_st[2], UInt<1>(0h0)) node _issue_entry_T_1907 = mux(issue_sel_12, entries_ex[12].bits.deps_st[2], UInt<1>(0h0)) node _issue_entry_T_1908 = mux(issue_sel_13, entries_ex[13].bits.deps_st[2], UInt<1>(0h0)) node _issue_entry_T_1909 = mux(issue_sel_14, entries_ex[14].bits.deps_st[2], UInt<1>(0h0)) node _issue_entry_T_1910 = mux(issue_sel_15, entries_ex[15].bits.deps_st[2], UInt<1>(0h0)) node _issue_entry_T_1911 = or(_issue_entry_T_1895, _issue_entry_T_1896) node _issue_entry_T_1912 = or(_issue_entry_T_1911, _issue_entry_T_1897) node _issue_entry_T_1913 = or(_issue_entry_T_1912, _issue_entry_T_1898) node _issue_entry_T_1914 = or(_issue_entry_T_1913, _issue_entry_T_1899) node _issue_entry_T_1915 = or(_issue_entry_T_1914, _issue_entry_T_1900) node _issue_entry_T_1916 = or(_issue_entry_T_1915, _issue_entry_T_1901) node _issue_entry_T_1917 = or(_issue_entry_T_1916, _issue_entry_T_1902) node _issue_entry_T_1918 = or(_issue_entry_T_1917, _issue_entry_T_1903) node _issue_entry_T_1919 = or(_issue_entry_T_1918, _issue_entry_T_1904) node _issue_entry_T_1920 = or(_issue_entry_T_1919, _issue_entry_T_1905) node _issue_entry_T_1921 = or(_issue_entry_T_1920, _issue_entry_T_1906) node _issue_entry_T_1922 = or(_issue_entry_T_1921, _issue_entry_T_1907) node _issue_entry_T_1923 = or(_issue_entry_T_1922, _issue_entry_T_1908) node _issue_entry_T_1924 = or(_issue_entry_T_1923, _issue_entry_T_1909) node _issue_entry_T_1925 = or(_issue_entry_T_1924, _issue_entry_T_1910) wire _issue_entry_WIRE_148 : UInt<1> connect _issue_entry_WIRE_148, _issue_entry_T_1925 connect _issue_entry_WIRE_145[2], _issue_entry_WIRE_148 node _issue_entry_T_1926 = mux(issue_sel_0_1, entries_ex[0].bits.deps_st[3], UInt<1>(0h0)) node _issue_entry_T_1927 = mux(issue_sel_1_1, entries_ex[1].bits.deps_st[3], UInt<1>(0h0)) node _issue_entry_T_1928 = mux(issue_sel_2_1, entries_ex[2].bits.deps_st[3], UInt<1>(0h0)) node _issue_entry_T_1929 = mux(issue_sel_3_1, entries_ex[3].bits.deps_st[3], UInt<1>(0h0)) node _issue_entry_T_1930 = mux(issue_sel_4_1, entries_ex[4].bits.deps_st[3], UInt<1>(0h0)) node _issue_entry_T_1931 = mux(issue_sel_5_1, entries_ex[5].bits.deps_st[3], UInt<1>(0h0)) node _issue_entry_T_1932 = mux(issue_sel_6_1, entries_ex[6].bits.deps_st[3], UInt<1>(0h0)) node _issue_entry_T_1933 = mux(issue_sel_7_1, entries_ex[7].bits.deps_st[3], UInt<1>(0h0)) node _issue_entry_T_1934 = mux(issue_sel_8, entries_ex[8].bits.deps_st[3], UInt<1>(0h0)) node _issue_entry_T_1935 = mux(issue_sel_9, entries_ex[9].bits.deps_st[3], UInt<1>(0h0)) node _issue_entry_T_1936 = mux(issue_sel_10, entries_ex[10].bits.deps_st[3], UInt<1>(0h0)) node _issue_entry_T_1937 = mux(issue_sel_11, entries_ex[11].bits.deps_st[3], UInt<1>(0h0)) node _issue_entry_T_1938 = mux(issue_sel_12, entries_ex[12].bits.deps_st[3], UInt<1>(0h0)) node _issue_entry_T_1939 = mux(issue_sel_13, entries_ex[13].bits.deps_st[3], UInt<1>(0h0)) node _issue_entry_T_1940 = mux(issue_sel_14, entries_ex[14].bits.deps_st[3], UInt<1>(0h0)) node _issue_entry_T_1941 = mux(issue_sel_15, entries_ex[15].bits.deps_st[3], UInt<1>(0h0)) node _issue_entry_T_1942 = or(_issue_entry_T_1926, _issue_entry_T_1927) node _issue_entry_T_1943 = or(_issue_entry_T_1942, _issue_entry_T_1928) node _issue_entry_T_1944 = or(_issue_entry_T_1943, _issue_entry_T_1929) node _issue_entry_T_1945 = or(_issue_entry_T_1944, _issue_entry_T_1930) node _issue_entry_T_1946 = or(_issue_entry_T_1945, _issue_entry_T_1931) node _issue_entry_T_1947 = or(_issue_entry_T_1946, _issue_entry_T_1932) node _issue_entry_T_1948 = or(_issue_entry_T_1947, _issue_entry_T_1933) node _issue_entry_T_1949 = or(_issue_entry_T_1948, _issue_entry_T_1934) node _issue_entry_T_1950 = or(_issue_entry_T_1949, _issue_entry_T_1935) node _issue_entry_T_1951 = or(_issue_entry_T_1950, _issue_entry_T_1936) node _issue_entry_T_1952 = or(_issue_entry_T_1951, _issue_entry_T_1937) node _issue_entry_T_1953 = or(_issue_entry_T_1952, _issue_entry_T_1938) node _issue_entry_T_1954 = or(_issue_entry_T_1953, _issue_entry_T_1939) node _issue_entry_T_1955 = or(_issue_entry_T_1954, _issue_entry_T_1940) node _issue_entry_T_1956 = or(_issue_entry_T_1955, _issue_entry_T_1941) wire _issue_entry_WIRE_149 : UInt<1> connect _issue_entry_WIRE_149, _issue_entry_T_1956 connect _issue_entry_WIRE_145[3], _issue_entry_WIRE_149 connect _issue_entry_WIRE_143.deps_st, _issue_entry_WIRE_145 wire _issue_entry_WIRE_150 : UInt<1>[16] node _issue_entry_T_1957 = mux(issue_sel_0_1, entries_ex[0].bits.deps_ex[0], UInt<1>(0h0)) node _issue_entry_T_1958 = mux(issue_sel_1_1, entries_ex[1].bits.deps_ex[0], UInt<1>(0h0)) node _issue_entry_T_1959 = mux(issue_sel_2_1, entries_ex[2].bits.deps_ex[0], UInt<1>(0h0)) node _issue_entry_T_1960 = mux(issue_sel_3_1, entries_ex[3].bits.deps_ex[0], UInt<1>(0h0)) node _issue_entry_T_1961 = mux(issue_sel_4_1, entries_ex[4].bits.deps_ex[0], UInt<1>(0h0)) node _issue_entry_T_1962 = mux(issue_sel_5_1, entries_ex[5].bits.deps_ex[0], UInt<1>(0h0)) node _issue_entry_T_1963 = mux(issue_sel_6_1, entries_ex[6].bits.deps_ex[0], UInt<1>(0h0)) node _issue_entry_T_1964 = mux(issue_sel_7_1, entries_ex[7].bits.deps_ex[0], UInt<1>(0h0)) node _issue_entry_T_1965 = mux(issue_sel_8, entries_ex[8].bits.deps_ex[0], UInt<1>(0h0)) node _issue_entry_T_1966 = mux(issue_sel_9, entries_ex[9].bits.deps_ex[0], UInt<1>(0h0)) node _issue_entry_T_1967 = mux(issue_sel_10, entries_ex[10].bits.deps_ex[0], UInt<1>(0h0)) node _issue_entry_T_1968 = mux(issue_sel_11, entries_ex[11].bits.deps_ex[0], UInt<1>(0h0)) node _issue_entry_T_1969 = mux(issue_sel_12, entries_ex[12].bits.deps_ex[0], UInt<1>(0h0)) node _issue_entry_T_1970 = mux(issue_sel_13, entries_ex[13].bits.deps_ex[0], UInt<1>(0h0)) node _issue_entry_T_1971 = mux(issue_sel_14, entries_ex[14].bits.deps_ex[0], UInt<1>(0h0)) node _issue_entry_T_1972 = mux(issue_sel_15, entries_ex[15].bits.deps_ex[0], UInt<1>(0h0)) node _issue_entry_T_1973 = or(_issue_entry_T_1957, _issue_entry_T_1958) node _issue_entry_T_1974 = or(_issue_entry_T_1973, _issue_entry_T_1959) node _issue_entry_T_1975 = or(_issue_entry_T_1974, _issue_entry_T_1960) node _issue_entry_T_1976 = or(_issue_entry_T_1975, _issue_entry_T_1961) node _issue_entry_T_1977 = or(_issue_entry_T_1976, _issue_entry_T_1962) node _issue_entry_T_1978 = or(_issue_entry_T_1977, _issue_entry_T_1963) node _issue_entry_T_1979 = or(_issue_entry_T_1978, _issue_entry_T_1964) node _issue_entry_T_1980 = or(_issue_entry_T_1979, _issue_entry_T_1965) node _issue_entry_T_1981 = or(_issue_entry_T_1980, _issue_entry_T_1966) node _issue_entry_T_1982 = or(_issue_entry_T_1981, _issue_entry_T_1967) node _issue_entry_T_1983 = or(_issue_entry_T_1982, _issue_entry_T_1968) node _issue_entry_T_1984 = or(_issue_entry_T_1983, _issue_entry_T_1969) node _issue_entry_T_1985 = or(_issue_entry_T_1984, _issue_entry_T_1970) node _issue_entry_T_1986 = or(_issue_entry_T_1985, _issue_entry_T_1971) node _issue_entry_T_1987 = or(_issue_entry_T_1986, _issue_entry_T_1972) wire _issue_entry_WIRE_151 : UInt<1> connect _issue_entry_WIRE_151, _issue_entry_T_1987 connect _issue_entry_WIRE_150[0], _issue_entry_WIRE_151 node _issue_entry_T_1988 = mux(issue_sel_0_1, entries_ex[0].bits.deps_ex[1], UInt<1>(0h0)) node _issue_entry_T_1989 = mux(issue_sel_1_1, entries_ex[1].bits.deps_ex[1], UInt<1>(0h0)) node _issue_entry_T_1990 = mux(issue_sel_2_1, entries_ex[2].bits.deps_ex[1], UInt<1>(0h0)) node _issue_entry_T_1991 = mux(issue_sel_3_1, entries_ex[3].bits.deps_ex[1], UInt<1>(0h0)) node _issue_entry_T_1992 = mux(issue_sel_4_1, entries_ex[4].bits.deps_ex[1], UInt<1>(0h0)) node _issue_entry_T_1993 = mux(issue_sel_5_1, entries_ex[5].bits.deps_ex[1], UInt<1>(0h0)) node _issue_entry_T_1994 = mux(issue_sel_6_1, entries_ex[6].bits.deps_ex[1], UInt<1>(0h0)) node _issue_entry_T_1995 = mux(issue_sel_7_1, entries_ex[7].bits.deps_ex[1], UInt<1>(0h0)) node _issue_entry_T_1996 = mux(issue_sel_8, entries_ex[8].bits.deps_ex[1], UInt<1>(0h0)) node _issue_entry_T_1997 = mux(issue_sel_9, entries_ex[9].bits.deps_ex[1], UInt<1>(0h0)) node _issue_entry_T_1998 = mux(issue_sel_10, entries_ex[10].bits.deps_ex[1], UInt<1>(0h0)) node _issue_entry_T_1999 = mux(issue_sel_11, entries_ex[11].bits.deps_ex[1], UInt<1>(0h0)) node _issue_entry_T_2000 = mux(issue_sel_12, entries_ex[12].bits.deps_ex[1], UInt<1>(0h0)) node _issue_entry_T_2001 = mux(issue_sel_13, entries_ex[13].bits.deps_ex[1], UInt<1>(0h0)) node _issue_entry_T_2002 = mux(issue_sel_14, entries_ex[14].bits.deps_ex[1], UInt<1>(0h0)) node _issue_entry_T_2003 = mux(issue_sel_15, entries_ex[15].bits.deps_ex[1], UInt<1>(0h0)) node _issue_entry_T_2004 = or(_issue_entry_T_1988, _issue_entry_T_1989) node _issue_entry_T_2005 = or(_issue_entry_T_2004, _issue_entry_T_1990) node _issue_entry_T_2006 = or(_issue_entry_T_2005, _issue_entry_T_1991) node _issue_entry_T_2007 = or(_issue_entry_T_2006, _issue_entry_T_1992) node _issue_entry_T_2008 = or(_issue_entry_T_2007, _issue_entry_T_1993) node _issue_entry_T_2009 = or(_issue_entry_T_2008, _issue_entry_T_1994) node _issue_entry_T_2010 = or(_issue_entry_T_2009, _issue_entry_T_1995) node _issue_entry_T_2011 = or(_issue_entry_T_2010, _issue_entry_T_1996) node _issue_entry_T_2012 = or(_issue_entry_T_2011, _issue_entry_T_1997) node _issue_entry_T_2013 = or(_issue_entry_T_2012, _issue_entry_T_1998) node _issue_entry_T_2014 = or(_issue_entry_T_2013, _issue_entry_T_1999) node _issue_entry_T_2015 = or(_issue_entry_T_2014, _issue_entry_T_2000) node _issue_entry_T_2016 = or(_issue_entry_T_2015, _issue_entry_T_2001) node _issue_entry_T_2017 = or(_issue_entry_T_2016, _issue_entry_T_2002) node _issue_entry_T_2018 = or(_issue_entry_T_2017, _issue_entry_T_2003) wire _issue_entry_WIRE_152 : UInt<1> connect _issue_entry_WIRE_152, _issue_entry_T_2018 connect _issue_entry_WIRE_150[1], _issue_entry_WIRE_152 node _issue_entry_T_2019 = mux(issue_sel_0_1, entries_ex[0].bits.deps_ex[2], UInt<1>(0h0)) node _issue_entry_T_2020 = mux(issue_sel_1_1, entries_ex[1].bits.deps_ex[2], UInt<1>(0h0)) node _issue_entry_T_2021 = mux(issue_sel_2_1, entries_ex[2].bits.deps_ex[2], UInt<1>(0h0)) node _issue_entry_T_2022 = mux(issue_sel_3_1, entries_ex[3].bits.deps_ex[2], UInt<1>(0h0)) node _issue_entry_T_2023 = mux(issue_sel_4_1, entries_ex[4].bits.deps_ex[2], UInt<1>(0h0)) node _issue_entry_T_2024 = mux(issue_sel_5_1, entries_ex[5].bits.deps_ex[2], UInt<1>(0h0)) node _issue_entry_T_2025 = mux(issue_sel_6_1, entries_ex[6].bits.deps_ex[2], UInt<1>(0h0)) node _issue_entry_T_2026 = mux(issue_sel_7_1, entries_ex[7].bits.deps_ex[2], UInt<1>(0h0)) node _issue_entry_T_2027 = mux(issue_sel_8, entries_ex[8].bits.deps_ex[2], UInt<1>(0h0)) node _issue_entry_T_2028 = mux(issue_sel_9, entries_ex[9].bits.deps_ex[2], UInt<1>(0h0)) node _issue_entry_T_2029 = mux(issue_sel_10, entries_ex[10].bits.deps_ex[2], UInt<1>(0h0)) node _issue_entry_T_2030 = mux(issue_sel_11, entries_ex[11].bits.deps_ex[2], UInt<1>(0h0)) node _issue_entry_T_2031 = mux(issue_sel_12, entries_ex[12].bits.deps_ex[2], UInt<1>(0h0)) node _issue_entry_T_2032 = mux(issue_sel_13, entries_ex[13].bits.deps_ex[2], UInt<1>(0h0)) node _issue_entry_T_2033 = mux(issue_sel_14, entries_ex[14].bits.deps_ex[2], UInt<1>(0h0)) node _issue_entry_T_2034 = mux(issue_sel_15, entries_ex[15].bits.deps_ex[2], UInt<1>(0h0)) node _issue_entry_T_2035 = or(_issue_entry_T_2019, _issue_entry_T_2020) node _issue_entry_T_2036 = or(_issue_entry_T_2035, _issue_entry_T_2021) node _issue_entry_T_2037 = or(_issue_entry_T_2036, _issue_entry_T_2022) node _issue_entry_T_2038 = or(_issue_entry_T_2037, _issue_entry_T_2023) node _issue_entry_T_2039 = or(_issue_entry_T_2038, _issue_entry_T_2024) node _issue_entry_T_2040 = or(_issue_entry_T_2039, _issue_entry_T_2025) node _issue_entry_T_2041 = or(_issue_entry_T_2040, _issue_entry_T_2026) node _issue_entry_T_2042 = or(_issue_entry_T_2041, _issue_entry_T_2027) node _issue_entry_T_2043 = or(_issue_entry_T_2042, _issue_entry_T_2028) node _issue_entry_T_2044 = or(_issue_entry_T_2043, _issue_entry_T_2029) node _issue_entry_T_2045 = or(_issue_entry_T_2044, _issue_entry_T_2030) node _issue_entry_T_2046 = or(_issue_entry_T_2045, _issue_entry_T_2031) node _issue_entry_T_2047 = or(_issue_entry_T_2046, _issue_entry_T_2032) node _issue_entry_T_2048 = or(_issue_entry_T_2047, _issue_entry_T_2033) node _issue_entry_T_2049 = or(_issue_entry_T_2048, _issue_entry_T_2034) wire _issue_entry_WIRE_153 : UInt<1> connect _issue_entry_WIRE_153, _issue_entry_T_2049 connect _issue_entry_WIRE_150[2], _issue_entry_WIRE_153 node _issue_entry_T_2050 = mux(issue_sel_0_1, entries_ex[0].bits.deps_ex[3], UInt<1>(0h0)) node _issue_entry_T_2051 = mux(issue_sel_1_1, entries_ex[1].bits.deps_ex[3], UInt<1>(0h0)) node _issue_entry_T_2052 = mux(issue_sel_2_1, entries_ex[2].bits.deps_ex[3], UInt<1>(0h0)) node _issue_entry_T_2053 = mux(issue_sel_3_1, entries_ex[3].bits.deps_ex[3], UInt<1>(0h0)) node _issue_entry_T_2054 = mux(issue_sel_4_1, entries_ex[4].bits.deps_ex[3], UInt<1>(0h0)) node _issue_entry_T_2055 = mux(issue_sel_5_1, entries_ex[5].bits.deps_ex[3], UInt<1>(0h0)) node _issue_entry_T_2056 = mux(issue_sel_6_1, entries_ex[6].bits.deps_ex[3], UInt<1>(0h0)) node _issue_entry_T_2057 = mux(issue_sel_7_1, entries_ex[7].bits.deps_ex[3], UInt<1>(0h0)) node _issue_entry_T_2058 = mux(issue_sel_8, entries_ex[8].bits.deps_ex[3], UInt<1>(0h0)) node _issue_entry_T_2059 = mux(issue_sel_9, entries_ex[9].bits.deps_ex[3], UInt<1>(0h0)) node _issue_entry_T_2060 = mux(issue_sel_10, entries_ex[10].bits.deps_ex[3], UInt<1>(0h0)) node _issue_entry_T_2061 = mux(issue_sel_11, entries_ex[11].bits.deps_ex[3], UInt<1>(0h0)) node _issue_entry_T_2062 = mux(issue_sel_12, entries_ex[12].bits.deps_ex[3], UInt<1>(0h0)) node _issue_entry_T_2063 = mux(issue_sel_13, entries_ex[13].bits.deps_ex[3], UInt<1>(0h0)) node _issue_entry_T_2064 = mux(issue_sel_14, entries_ex[14].bits.deps_ex[3], UInt<1>(0h0)) node _issue_entry_T_2065 = mux(issue_sel_15, entries_ex[15].bits.deps_ex[3], UInt<1>(0h0)) node _issue_entry_T_2066 = or(_issue_entry_T_2050, _issue_entry_T_2051) node _issue_entry_T_2067 = or(_issue_entry_T_2066, _issue_entry_T_2052) node _issue_entry_T_2068 = or(_issue_entry_T_2067, _issue_entry_T_2053) node _issue_entry_T_2069 = or(_issue_entry_T_2068, _issue_entry_T_2054) node _issue_entry_T_2070 = or(_issue_entry_T_2069, _issue_entry_T_2055) node _issue_entry_T_2071 = or(_issue_entry_T_2070, _issue_entry_T_2056) node _issue_entry_T_2072 = or(_issue_entry_T_2071, _issue_entry_T_2057) node _issue_entry_T_2073 = or(_issue_entry_T_2072, _issue_entry_T_2058) node _issue_entry_T_2074 = or(_issue_entry_T_2073, _issue_entry_T_2059) node _issue_entry_T_2075 = or(_issue_entry_T_2074, _issue_entry_T_2060) node _issue_entry_T_2076 = or(_issue_entry_T_2075, _issue_entry_T_2061) node _issue_entry_T_2077 = or(_issue_entry_T_2076, _issue_entry_T_2062) node _issue_entry_T_2078 = or(_issue_entry_T_2077, _issue_entry_T_2063) node _issue_entry_T_2079 = or(_issue_entry_T_2078, _issue_entry_T_2064) node _issue_entry_T_2080 = or(_issue_entry_T_2079, _issue_entry_T_2065) wire _issue_entry_WIRE_154 : UInt<1> connect _issue_entry_WIRE_154, _issue_entry_T_2080 connect _issue_entry_WIRE_150[3], _issue_entry_WIRE_154 node _issue_entry_T_2081 = mux(issue_sel_0_1, entries_ex[0].bits.deps_ex[4], UInt<1>(0h0)) node _issue_entry_T_2082 = mux(issue_sel_1_1, entries_ex[1].bits.deps_ex[4], UInt<1>(0h0)) node _issue_entry_T_2083 = mux(issue_sel_2_1, entries_ex[2].bits.deps_ex[4], UInt<1>(0h0)) node _issue_entry_T_2084 = mux(issue_sel_3_1, entries_ex[3].bits.deps_ex[4], UInt<1>(0h0)) node _issue_entry_T_2085 = mux(issue_sel_4_1, entries_ex[4].bits.deps_ex[4], UInt<1>(0h0)) node _issue_entry_T_2086 = mux(issue_sel_5_1, entries_ex[5].bits.deps_ex[4], UInt<1>(0h0)) node _issue_entry_T_2087 = mux(issue_sel_6_1, entries_ex[6].bits.deps_ex[4], UInt<1>(0h0)) node _issue_entry_T_2088 = mux(issue_sel_7_1, entries_ex[7].bits.deps_ex[4], UInt<1>(0h0)) node _issue_entry_T_2089 = mux(issue_sel_8, entries_ex[8].bits.deps_ex[4], UInt<1>(0h0)) node _issue_entry_T_2090 = mux(issue_sel_9, entries_ex[9].bits.deps_ex[4], UInt<1>(0h0)) node _issue_entry_T_2091 = mux(issue_sel_10, entries_ex[10].bits.deps_ex[4], UInt<1>(0h0)) node _issue_entry_T_2092 = mux(issue_sel_11, entries_ex[11].bits.deps_ex[4], UInt<1>(0h0)) node _issue_entry_T_2093 = mux(issue_sel_12, entries_ex[12].bits.deps_ex[4], UInt<1>(0h0)) node _issue_entry_T_2094 = mux(issue_sel_13, entries_ex[13].bits.deps_ex[4], UInt<1>(0h0)) node _issue_entry_T_2095 = mux(issue_sel_14, entries_ex[14].bits.deps_ex[4], UInt<1>(0h0)) node _issue_entry_T_2096 = mux(issue_sel_15, entries_ex[15].bits.deps_ex[4], UInt<1>(0h0)) node _issue_entry_T_2097 = or(_issue_entry_T_2081, _issue_entry_T_2082) node _issue_entry_T_2098 = or(_issue_entry_T_2097, _issue_entry_T_2083) node _issue_entry_T_2099 = or(_issue_entry_T_2098, _issue_entry_T_2084) node _issue_entry_T_2100 = or(_issue_entry_T_2099, _issue_entry_T_2085) node _issue_entry_T_2101 = or(_issue_entry_T_2100, _issue_entry_T_2086) node _issue_entry_T_2102 = or(_issue_entry_T_2101, _issue_entry_T_2087) node _issue_entry_T_2103 = or(_issue_entry_T_2102, _issue_entry_T_2088) node _issue_entry_T_2104 = or(_issue_entry_T_2103, _issue_entry_T_2089) node _issue_entry_T_2105 = or(_issue_entry_T_2104, _issue_entry_T_2090) node _issue_entry_T_2106 = or(_issue_entry_T_2105, _issue_entry_T_2091) node _issue_entry_T_2107 = or(_issue_entry_T_2106, _issue_entry_T_2092) node _issue_entry_T_2108 = or(_issue_entry_T_2107, _issue_entry_T_2093) node _issue_entry_T_2109 = or(_issue_entry_T_2108, _issue_entry_T_2094) node _issue_entry_T_2110 = or(_issue_entry_T_2109, _issue_entry_T_2095) node _issue_entry_T_2111 = or(_issue_entry_T_2110, _issue_entry_T_2096) wire _issue_entry_WIRE_155 : UInt<1> connect _issue_entry_WIRE_155, _issue_entry_T_2111 connect _issue_entry_WIRE_150[4], _issue_entry_WIRE_155 node _issue_entry_T_2112 = mux(issue_sel_0_1, entries_ex[0].bits.deps_ex[5], UInt<1>(0h0)) node _issue_entry_T_2113 = mux(issue_sel_1_1, entries_ex[1].bits.deps_ex[5], UInt<1>(0h0)) node _issue_entry_T_2114 = mux(issue_sel_2_1, entries_ex[2].bits.deps_ex[5], UInt<1>(0h0)) node _issue_entry_T_2115 = mux(issue_sel_3_1, entries_ex[3].bits.deps_ex[5], UInt<1>(0h0)) node _issue_entry_T_2116 = mux(issue_sel_4_1, entries_ex[4].bits.deps_ex[5], UInt<1>(0h0)) node _issue_entry_T_2117 = mux(issue_sel_5_1, entries_ex[5].bits.deps_ex[5], UInt<1>(0h0)) node _issue_entry_T_2118 = mux(issue_sel_6_1, entries_ex[6].bits.deps_ex[5], UInt<1>(0h0)) node _issue_entry_T_2119 = mux(issue_sel_7_1, entries_ex[7].bits.deps_ex[5], UInt<1>(0h0)) node _issue_entry_T_2120 = mux(issue_sel_8, entries_ex[8].bits.deps_ex[5], UInt<1>(0h0)) node _issue_entry_T_2121 = mux(issue_sel_9, entries_ex[9].bits.deps_ex[5], UInt<1>(0h0)) node _issue_entry_T_2122 = mux(issue_sel_10, entries_ex[10].bits.deps_ex[5], UInt<1>(0h0)) node _issue_entry_T_2123 = mux(issue_sel_11, entries_ex[11].bits.deps_ex[5], UInt<1>(0h0)) node _issue_entry_T_2124 = mux(issue_sel_12, entries_ex[12].bits.deps_ex[5], UInt<1>(0h0)) node _issue_entry_T_2125 = mux(issue_sel_13, entries_ex[13].bits.deps_ex[5], UInt<1>(0h0)) node _issue_entry_T_2126 = mux(issue_sel_14, entries_ex[14].bits.deps_ex[5], UInt<1>(0h0)) node _issue_entry_T_2127 = mux(issue_sel_15, entries_ex[15].bits.deps_ex[5], UInt<1>(0h0)) node _issue_entry_T_2128 = or(_issue_entry_T_2112, _issue_entry_T_2113) node _issue_entry_T_2129 = or(_issue_entry_T_2128, _issue_entry_T_2114) node _issue_entry_T_2130 = or(_issue_entry_T_2129, _issue_entry_T_2115) node _issue_entry_T_2131 = or(_issue_entry_T_2130, _issue_entry_T_2116) node _issue_entry_T_2132 = or(_issue_entry_T_2131, _issue_entry_T_2117) node _issue_entry_T_2133 = or(_issue_entry_T_2132, _issue_entry_T_2118) node _issue_entry_T_2134 = or(_issue_entry_T_2133, _issue_entry_T_2119) node _issue_entry_T_2135 = or(_issue_entry_T_2134, _issue_entry_T_2120) node _issue_entry_T_2136 = or(_issue_entry_T_2135, _issue_entry_T_2121) node _issue_entry_T_2137 = or(_issue_entry_T_2136, _issue_entry_T_2122) node _issue_entry_T_2138 = or(_issue_entry_T_2137, _issue_entry_T_2123) node _issue_entry_T_2139 = or(_issue_entry_T_2138, _issue_entry_T_2124) node _issue_entry_T_2140 = or(_issue_entry_T_2139, _issue_entry_T_2125) node _issue_entry_T_2141 = or(_issue_entry_T_2140, _issue_entry_T_2126) node _issue_entry_T_2142 = or(_issue_entry_T_2141, _issue_entry_T_2127) wire _issue_entry_WIRE_156 : UInt<1> connect _issue_entry_WIRE_156, _issue_entry_T_2142 connect _issue_entry_WIRE_150[5], _issue_entry_WIRE_156 node _issue_entry_T_2143 = mux(issue_sel_0_1, entries_ex[0].bits.deps_ex[6], UInt<1>(0h0)) node _issue_entry_T_2144 = mux(issue_sel_1_1, entries_ex[1].bits.deps_ex[6], UInt<1>(0h0)) node _issue_entry_T_2145 = mux(issue_sel_2_1, entries_ex[2].bits.deps_ex[6], UInt<1>(0h0)) node _issue_entry_T_2146 = mux(issue_sel_3_1, entries_ex[3].bits.deps_ex[6], UInt<1>(0h0)) node _issue_entry_T_2147 = mux(issue_sel_4_1, entries_ex[4].bits.deps_ex[6], UInt<1>(0h0)) node _issue_entry_T_2148 = mux(issue_sel_5_1, entries_ex[5].bits.deps_ex[6], UInt<1>(0h0)) node _issue_entry_T_2149 = mux(issue_sel_6_1, entries_ex[6].bits.deps_ex[6], UInt<1>(0h0)) node _issue_entry_T_2150 = mux(issue_sel_7_1, entries_ex[7].bits.deps_ex[6], UInt<1>(0h0)) node _issue_entry_T_2151 = mux(issue_sel_8, entries_ex[8].bits.deps_ex[6], UInt<1>(0h0)) node _issue_entry_T_2152 = mux(issue_sel_9, entries_ex[9].bits.deps_ex[6], UInt<1>(0h0)) node _issue_entry_T_2153 = mux(issue_sel_10, entries_ex[10].bits.deps_ex[6], UInt<1>(0h0)) node _issue_entry_T_2154 = mux(issue_sel_11, entries_ex[11].bits.deps_ex[6], UInt<1>(0h0)) node _issue_entry_T_2155 = mux(issue_sel_12, entries_ex[12].bits.deps_ex[6], UInt<1>(0h0)) node _issue_entry_T_2156 = mux(issue_sel_13, entries_ex[13].bits.deps_ex[6], UInt<1>(0h0)) node _issue_entry_T_2157 = mux(issue_sel_14, entries_ex[14].bits.deps_ex[6], UInt<1>(0h0)) node _issue_entry_T_2158 = mux(issue_sel_15, entries_ex[15].bits.deps_ex[6], UInt<1>(0h0)) node _issue_entry_T_2159 = or(_issue_entry_T_2143, _issue_entry_T_2144) node _issue_entry_T_2160 = or(_issue_entry_T_2159, _issue_entry_T_2145) node _issue_entry_T_2161 = or(_issue_entry_T_2160, _issue_entry_T_2146) node _issue_entry_T_2162 = or(_issue_entry_T_2161, _issue_entry_T_2147) node _issue_entry_T_2163 = or(_issue_entry_T_2162, _issue_entry_T_2148) node _issue_entry_T_2164 = or(_issue_entry_T_2163, _issue_entry_T_2149) node _issue_entry_T_2165 = or(_issue_entry_T_2164, _issue_entry_T_2150) node _issue_entry_T_2166 = or(_issue_entry_T_2165, _issue_entry_T_2151) node _issue_entry_T_2167 = or(_issue_entry_T_2166, _issue_entry_T_2152) node _issue_entry_T_2168 = or(_issue_entry_T_2167, _issue_entry_T_2153) node _issue_entry_T_2169 = or(_issue_entry_T_2168, _issue_entry_T_2154) node _issue_entry_T_2170 = or(_issue_entry_T_2169, _issue_entry_T_2155) node _issue_entry_T_2171 = or(_issue_entry_T_2170, _issue_entry_T_2156) node _issue_entry_T_2172 = or(_issue_entry_T_2171, _issue_entry_T_2157) node _issue_entry_T_2173 = or(_issue_entry_T_2172, _issue_entry_T_2158) wire _issue_entry_WIRE_157 : UInt<1> connect _issue_entry_WIRE_157, _issue_entry_T_2173 connect _issue_entry_WIRE_150[6], _issue_entry_WIRE_157 node _issue_entry_T_2174 = mux(issue_sel_0_1, entries_ex[0].bits.deps_ex[7], UInt<1>(0h0)) node _issue_entry_T_2175 = mux(issue_sel_1_1, entries_ex[1].bits.deps_ex[7], UInt<1>(0h0)) node _issue_entry_T_2176 = mux(issue_sel_2_1, entries_ex[2].bits.deps_ex[7], UInt<1>(0h0)) node _issue_entry_T_2177 = mux(issue_sel_3_1, entries_ex[3].bits.deps_ex[7], UInt<1>(0h0)) node _issue_entry_T_2178 = mux(issue_sel_4_1, entries_ex[4].bits.deps_ex[7], UInt<1>(0h0)) node _issue_entry_T_2179 = mux(issue_sel_5_1, entries_ex[5].bits.deps_ex[7], UInt<1>(0h0)) node _issue_entry_T_2180 = mux(issue_sel_6_1, entries_ex[6].bits.deps_ex[7], UInt<1>(0h0)) node _issue_entry_T_2181 = mux(issue_sel_7_1, entries_ex[7].bits.deps_ex[7], UInt<1>(0h0)) node _issue_entry_T_2182 = mux(issue_sel_8, entries_ex[8].bits.deps_ex[7], UInt<1>(0h0)) node _issue_entry_T_2183 = mux(issue_sel_9, entries_ex[9].bits.deps_ex[7], UInt<1>(0h0)) node _issue_entry_T_2184 = mux(issue_sel_10, entries_ex[10].bits.deps_ex[7], UInt<1>(0h0)) node _issue_entry_T_2185 = mux(issue_sel_11, entries_ex[11].bits.deps_ex[7], UInt<1>(0h0)) node _issue_entry_T_2186 = mux(issue_sel_12, entries_ex[12].bits.deps_ex[7], UInt<1>(0h0)) node _issue_entry_T_2187 = mux(issue_sel_13, entries_ex[13].bits.deps_ex[7], UInt<1>(0h0)) node _issue_entry_T_2188 = mux(issue_sel_14, entries_ex[14].bits.deps_ex[7], UInt<1>(0h0)) node _issue_entry_T_2189 = mux(issue_sel_15, entries_ex[15].bits.deps_ex[7], UInt<1>(0h0)) node _issue_entry_T_2190 = or(_issue_entry_T_2174, _issue_entry_T_2175) node _issue_entry_T_2191 = or(_issue_entry_T_2190, _issue_entry_T_2176) node _issue_entry_T_2192 = or(_issue_entry_T_2191, _issue_entry_T_2177) node _issue_entry_T_2193 = or(_issue_entry_T_2192, _issue_entry_T_2178) node _issue_entry_T_2194 = or(_issue_entry_T_2193, _issue_entry_T_2179) node _issue_entry_T_2195 = or(_issue_entry_T_2194, _issue_entry_T_2180) node _issue_entry_T_2196 = or(_issue_entry_T_2195, _issue_entry_T_2181) node _issue_entry_T_2197 = or(_issue_entry_T_2196, _issue_entry_T_2182) node _issue_entry_T_2198 = or(_issue_entry_T_2197, _issue_entry_T_2183) node _issue_entry_T_2199 = or(_issue_entry_T_2198, _issue_entry_T_2184) node _issue_entry_T_2200 = or(_issue_entry_T_2199, _issue_entry_T_2185) node _issue_entry_T_2201 = or(_issue_entry_T_2200, _issue_entry_T_2186) node _issue_entry_T_2202 = or(_issue_entry_T_2201, _issue_entry_T_2187) node _issue_entry_T_2203 = or(_issue_entry_T_2202, _issue_entry_T_2188) node _issue_entry_T_2204 = or(_issue_entry_T_2203, _issue_entry_T_2189) wire _issue_entry_WIRE_158 : UInt<1> connect _issue_entry_WIRE_158, _issue_entry_T_2204 connect _issue_entry_WIRE_150[7], _issue_entry_WIRE_158 node _issue_entry_T_2205 = mux(issue_sel_0_1, entries_ex[0].bits.deps_ex[8], UInt<1>(0h0)) node _issue_entry_T_2206 = mux(issue_sel_1_1, entries_ex[1].bits.deps_ex[8], UInt<1>(0h0)) node _issue_entry_T_2207 = mux(issue_sel_2_1, entries_ex[2].bits.deps_ex[8], UInt<1>(0h0)) node _issue_entry_T_2208 = mux(issue_sel_3_1, entries_ex[3].bits.deps_ex[8], UInt<1>(0h0)) node _issue_entry_T_2209 = mux(issue_sel_4_1, entries_ex[4].bits.deps_ex[8], UInt<1>(0h0)) node _issue_entry_T_2210 = mux(issue_sel_5_1, entries_ex[5].bits.deps_ex[8], UInt<1>(0h0)) node _issue_entry_T_2211 = mux(issue_sel_6_1, entries_ex[6].bits.deps_ex[8], UInt<1>(0h0)) node _issue_entry_T_2212 = mux(issue_sel_7_1, entries_ex[7].bits.deps_ex[8], UInt<1>(0h0)) node _issue_entry_T_2213 = mux(issue_sel_8, entries_ex[8].bits.deps_ex[8], UInt<1>(0h0)) node _issue_entry_T_2214 = mux(issue_sel_9, entries_ex[9].bits.deps_ex[8], UInt<1>(0h0)) node _issue_entry_T_2215 = mux(issue_sel_10, entries_ex[10].bits.deps_ex[8], UInt<1>(0h0)) node _issue_entry_T_2216 = mux(issue_sel_11, entries_ex[11].bits.deps_ex[8], UInt<1>(0h0)) node _issue_entry_T_2217 = mux(issue_sel_12, entries_ex[12].bits.deps_ex[8], UInt<1>(0h0)) node _issue_entry_T_2218 = mux(issue_sel_13, entries_ex[13].bits.deps_ex[8], UInt<1>(0h0)) node _issue_entry_T_2219 = mux(issue_sel_14, entries_ex[14].bits.deps_ex[8], UInt<1>(0h0)) node _issue_entry_T_2220 = mux(issue_sel_15, entries_ex[15].bits.deps_ex[8], UInt<1>(0h0)) node _issue_entry_T_2221 = or(_issue_entry_T_2205, _issue_entry_T_2206) node _issue_entry_T_2222 = or(_issue_entry_T_2221, _issue_entry_T_2207) node _issue_entry_T_2223 = or(_issue_entry_T_2222, _issue_entry_T_2208) node _issue_entry_T_2224 = or(_issue_entry_T_2223, _issue_entry_T_2209) node _issue_entry_T_2225 = or(_issue_entry_T_2224, _issue_entry_T_2210) node _issue_entry_T_2226 = or(_issue_entry_T_2225, _issue_entry_T_2211) node _issue_entry_T_2227 = or(_issue_entry_T_2226, _issue_entry_T_2212) node _issue_entry_T_2228 = or(_issue_entry_T_2227, _issue_entry_T_2213) node _issue_entry_T_2229 = or(_issue_entry_T_2228, _issue_entry_T_2214) node _issue_entry_T_2230 = or(_issue_entry_T_2229, _issue_entry_T_2215) node _issue_entry_T_2231 = or(_issue_entry_T_2230, _issue_entry_T_2216) node _issue_entry_T_2232 = or(_issue_entry_T_2231, _issue_entry_T_2217) node _issue_entry_T_2233 = or(_issue_entry_T_2232, _issue_entry_T_2218) node _issue_entry_T_2234 = or(_issue_entry_T_2233, _issue_entry_T_2219) node _issue_entry_T_2235 = or(_issue_entry_T_2234, _issue_entry_T_2220) wire _issue_entry_WIRE_159 : UInt<1> connect _issue_entry_WIRE_159, _issue_entry_T_2235 connect _issue_entry_WIRE_150[8], _issue_entry_WIRE_159 node _issue_entry_T_2236 = mux(issue_sel_0_1, entries_ex[0].bits.deps_ex[9], UInt<1>(0h0)) node _issue_entry_T_2237 = mux(issue_sel_1_1, entries_ex[1].bits.deps_ex[9], UInt<1>(0h0)) node _issue_entry_T_2238 = mux(issue_sel_2_1, entries_ex[2].bits.deps_ex[9], UInt<1>(0h0)) node _issue_entry_T_2239 = mux(issue_sel_3_1, entries_ex[3].bits.deps_ex[9], UInt<1>(0h0)) node _issue_entry_T_2240 = mux(issue_sel_4_1, entries_ex[4].bits.deps_ex[9], UInt<1>(0h0)) node _issue_entry_T_2241 = mux(issue_sel_5_1, entries_ex[5].bits.deps_ex[9], UInt<1>(0h0)) node _issue_entry_T_2242 = mux(issue_sel_6_1, entries_ex[6].bits.deps_ex[9], UInt<1>(0h0)) node _issue_entry_T_2243 = mux(issue_sel_7_1, entries_ex[7].bits.deps_ex[9], UInt<1>(0h0)) node _issue_entry_T_2244 = mux(issue_sel_8, entries_ex[8].bits.deps_ex[9], UInt<1>(0h0)) node _issue_entry_T_2245 = mux(issue_sel_9, entries_ex[9].bits.deps_ex[9], UInt<1>(0h0)) node _issue_entry_T_2246 = mux(issue_sel_10, entries_ex[10].bits.deps_ex[9], UInt<1>(0h0)) node _issue_entry_T_2247 = mux(issue_sel_11, entries_ex[11].bits.deps_ex[9], UInt<1>(0h0)) node _issue_entry_T_2248 = mux(issue_sel_12, entries_ex[12].bits.deps_ex[9], UInt<1>(0h0)) node _issue_entry_T_2249 = mux(issue_sel_13, entries_ex[13].bits.deps_ex[9], UInt<1>(0h0)) node _issue_entry_T_2250 = mux(issue_sel_14, entries_ex[14].bits.deps_ex[9], UInt<1>(0h0)) node _issue_entry_T_2251 = mux(issue_sel_15, entries_ex[15].bits.deps_ex[9], UInt<1>(0h0)) node _issue_entry_T_2252 = or(_issue_entry_T_2236, _issue_entry_T_2237) node _issue_entry_T_2253 = or(_issue_entry_T_2252, _issue_entry_T_2238) node _issue_entry_T_2254 = or(_issue_entry_T_2253, _issue_entry_T_2239) node _issue_entry_T_2255 = or(_issue_entry_T_2254, _issue_entry_T_2240) node _issue_entry_T_2256 = or(_issue_entry_T_2255, _issue_entry_T_2241) node _issue_entry_T_2257 = or(_issue_entry_T_2256, _issue_entry_T_2242) node _issue_entry_T_2258 = or(_issue_entry_T_2257, _issue_entry_T_2243) node _issue_entry_T_2259 = or(_issue_entry_T_2258, _issue_entry_T_2244) node _issue_entry_T_2260 = or(_issue_entry_T_2259, _issue_entry_T_2245) node _issue_entry_T_2261 = or(_issue_entry_T_2260, _issue_entry_T_2246) node _issue_entry_T_2262 = or(_issue_entry_T_2261, _issue_entry_T_2247) node _issue_entry_T_2263 = or(_issue_entry_T_2262, _issue_entry_T_2248) node _issue_entry_T_2264 = or(_issue_entry_T_2263, _issue_entry_T_2249) node _issue_entry_T_2265 = or(_issue_entry_T_2264, _issue_entry_T_2250) node _issue_entry_T_2266 = or(_issue_entry_T_2265, _issue_entry_T_2251) wire _issue_entry_WIRE_160 : UInt<1> connect _issue_entry_WIRE_160, _issue_entry_T_2266 connect _issue_entry_WIRE_150[9], _issue_entry_WIRE_160 node _issue_entry_T_2267 = mux(issue_sel_0_1, entries_ex[0].bits.deps_ex[10], UInt<1>(0h0)) node _issue_entry_T_2268 = mux(issue_sel_1_1, entries_ex[1].bits.deps_ex[10], UInt<1>(0h0)) node _issue_entry_T_2269 = mux(issue_sel_2_1, entries_ex[2].bits.deps_ex[10], UInt<1>(0h0)) node _issue_entry_T_2270 = mux(issue_sel_3_1, entries_ex[3].bits.deps_ex[10], UInt<1>(0h0)) node _issue_entry_T_2271 = mux(issue_sel_4_1, entries_ex[4].bits.deps_ex[10], UInt<1>(0h0)) node _issue_entry_T_2272 = mux(issue_sel_5_1, entries_ex[5].bits.deps_ex[10], UInt<1>(0h0)) node _issue_entry_T_2273 = mux(issue_sel_6_1, entries_ex[6].bits.deps_ex[10], UInt<1>(0h0)) node _issue_entry_T_2274 = mux(issue_sel_7_1, entries_ex[7].bits.deps_ex[10], UInt<1>(0h0)) node _issue_entry_T_2275 = mux(issue_sel_8, entries_ex[8].bits.deps_ex[10], UInt<1>(0h0)) node _issue_entry_T_2276 = mux(issue_sel_9, entries_ex[9].bits.deps_ex[10], UInt<1>(0h0)) node _issue_entry_T_2277 = mux(issue_sel_10, entries_ex[10].bits.deps_ex[10], UInt<1>(0h0)) node _issue_entry_T_2278 = mux(issue_sel_11, entries_ex[11].bits.deps_ex[10], UInt<1>(0h0)) node _issue_entry_T_2279 = mux(issue_sel_12, entries_ex[12].bits.deps_ex[10], UInt<1>(0h0)) node _issue_entry_T_2280 = mux(issue_sel_13, entries_ex[13].bits.deps_ex[10], UInt<1>(0h0)) node _issue_entry_T_2281 = mux(issue_sel_14, entries_ex[14].bits.deps_ex[10], UInt<1>(0h0)) node _issue_entry_T_2282 = mux(issue_sel_15, entries_ex[15].bits.deps_ex[10], UInt<1>(0h0)) node _issue_entry_T_2283 = or(_issue_entry_T_2267, _issue_entry_T_2268) node _issue_entry_T_2284 = or(_issue_entry_T_2283, _issue_entry_T_2269) node _issue_entry_T_2285 = or(_issue_entry_T_2284, _issue_entry_T_2270) node _issue_entry_T_2286 = or(_issue_entry_T_2285, _issue_entry_T_2271) node _issue_entry_T_2287 = or(_issue_entry_T_2286, _issue_entry_T_2272) node _issue_entry_T_2288 = or(_issue_entry_T_2287, _issue_entry_T_2273) node _issue_entry_T_2289 = or(_issue_entry_T_2288, _issue_entry_T_2274) node _issue_entry_T_2290 = or(_issue_entry_T_2289, _issue_entry_T_2275) node _issue_entry_T_2291 = or(_issue_entry_T_2290, _issue_entry_T_2276) node _issue_entry_T_2292 = or(_issue_entry_T_2291, _issue_entry_T_2277) node _issue_entry_T_2293 = or(_issue_entry_T_2292, _issue_entry_T_2278) node _issue_entry_T_2294 = or(_issue_entry_T_2293, _issue_entry_T_2279) node _issue_entry_T_2295 = or(_issue_entry_T_2294, _issue_entry_T_2280) node _issue_entry_T_2296 = or(_issue_entry_T_2295, _issue_entry_T_2281) node _issue_entry_T_2297 = or(_issue_entry_T_2296, _issue_entry_T_2282) wire _issue_entry_WIRE_161 : UInt<1> connect _issue_entry_WIRE_161, _issue_entry_T_2297 connect _issue_entry_WIRE_150[10], _issue_entry_WIRE_161 node _issue_entry_T_2298 = mux(issue_sel_0_1, entries_ex[0].bits.deps_ex[11], UInt<1>(0h0)) node _issue_entry_T_2299 = mux(issue_sel_1_1, entries_ex[1].bits.deps_ex[11], UInt<1>(0h0)) node _issue_entry_T_2300 = mux(issue_sel_2_1, entries_ex[2].bits.deps_ex[11], UInt<1>(0h0)) node _issue_entry_T_2301 = mux(issue_sel_3_1, entries_ex[3].bits.deps_ex[11], UInt<1>(0h0)) node _issue_entry_T_2302 = mux(issue_sel_4_1, entries_ex[4].bits.deps_ex[11], UInt<1>(0h0)) node _issue_entry_T_2303 = mux(issue_sel_5_1, entries_ex[5].bits.deps_ex[11], UInt<1>(0h0)) node _issue_entry_T_2304 = mux(issue_sel_6_1, entries_ex[6].bits.deps_ex[11], UInt<1>(0h0)) node _issue_entry_T_2305 = mux(issue_sel_7_1, entries_ex[7].bits.deps_ex[11], UInt<1>(0h0)) node _issue_entry_T_2306 = mux(issue_sel_8, entries_ex[8].bits.deps_ex[11], UInt<1>(0h0)) node _issue_entry_T_2307 = mux(issue_sel_9, entries_ex[9].bits.deps_ex[11], UInt<1>(0h0)) node _issue_entry_T_2308 = mux(issue_sel_10, entries_ex[10].bits.deps_ex[11], UInt<1>(0h0)) node _issue_entry_T_2309 = mux(issue_sel_11, entries_ex[11].bits.deps_ex[11], UInt<1>(0h0)) node _issue_entry_T_2310 = mux(issue_sel_12, entries_ex[12].bits.deps_ex[11], UInt<1>(0h0)) node _issue_entry_T_2311 = mux(issue_sel_13, entries_ex[13].bits.deps_ex[11], UInt<1>(0h0)) node _issue_entry_T_2312 = mux(issue_sel_14, entries_ex[14].bits.deps_ex[11], UInt<1>(0h0)) node _issue_entry_T_2313 = mux(issue_sel_15, entries_ex[15].bits.deps_ex[11], UInt<1>(0h0)) node _issue_entry_T_2314 = or(_issue_entry_T_2298, _issue_entry_T_2299) node _issue_entry_T_2315 = or(_issue_entry_T_2314, _issue_entry_T_2300) node _issue_entry_T_2316 = or(_issue_entry_T_2315, _issue_entry_T_2301) node _issue_entry_T_2317 = or(_issue_entry_T_2316, _issue_entry_T_2302) node _issue_entry_T_2318 = or(_issue_entry_T_2317, _issue_entry_T_2303) node _issue_entry_T_2319 = or(_issue_entry_T_2318, _issue_entry_T_2304) node _issue_entry_T_2320 = or(_issue_entry_T_2319, _issue_entry_T_2305) node _issue_entry_T_2321 = or(_issue_entry_T_2320, _issue_entry_T_2306) node _issue_entry_T_2322 = or(_issue_entry_T_2321, _issue_entry_T_2307) node _issue_entry_T_2323 = or(_issue_entry_T_2322, _issue_entry_T_2308) node _issue_entry_T_2324 = or(_issue_entry_T_2323, _issue_entry_T_2309) node _issue_entry_T_2325 = or(_issue_entry_T_2324, _issue_entry_T_2310) node _issue_entry_T_2326 = or(_issue_entry_T_2325, _issue_entry_T_2311) node _issue_entry_T_2327 = or(_issue_entry_T_2326, _issue_entry_T_2312) node _issue_entry_T_2328 = or(_issue_entry_T_2327, _issue_entry_T_2313) wire _issue_entry_WIRE_162 : UInt<1> connect _issue_entry_WIRE_162, _issue_entry_T_2328 connect _issue_entry_WIRE_150[11], _issue_entry_WIRE_162 node _issue_entry_T_2329 = mux(issue_sel_0_1, entries_ex[0].bits.deps_ex[12], UInt<1>(0h0)) node _issue_entry_T_2330 = mux(issue_sel_1_1, entries_ex[1].bits.deps_ex[12], UInt<1>(0h0)) node _issue_entry_T_2331 = mux(issue_sel_2_1, entries_ex[2].bits.deps_ex[12], UInt<1>(0h0)) node _issue_entry_T_2332 = mux(issue_sel_3_1, entries_ex[3].bits.deps_ex[12], UInt<1>(0h0)) node _issue_entry_T_2333 = mux(issue_sel_4_1, entries_ex[4].bits.deps_ex[12], UInt<1>(0h0)) node _issue_entry_T_2334 = mux(issue_sel_5_1, entries_ex[5].bits.deps_ex[12], UInt<1>(0h0)) node _issue_entry_T_2335 = mux(issue_sel_6_1, entries_ex[6].bits.deps_ex[12], UInt<1>(0h0)) node _issue_entry_T_2336 = mux(issue_sel_7_1, entries_ex[7].bits.deps_ex[12], UInt<1>(0h0)) node _issue_entry_T_2337 = mux(issue_sel_8, entries_ex[8].bits.deps_ex[12], UInt<1>(0h0)) node _issue_entry_T_2338 = mux(issue_sel_9, entries_ex[9].bits.deps_ex[12], UInt<1>(0h0)) node _issue_entry_T_2339 = mux(issue_sel_10, entries_ex[10].bits.deps_ex[12], UInt<1>(0h0)) node _issue_entry_T_2340 = mux(issue_sel_11, entries_ex[11].bits.deps_ex[12], UInt<1>(0h0)) node _issue_entry_T_2341 = mux(issue_sel_12, entries_ex[12].bits.deps_ex[12], UInt<1>(0h0)) node _issue_entry_T_2342 = mux(issue_sel_13, entries_ex[13].bits.deps_ex[12], UInt<1>(0h0)) node _issue_entry_T_2343 = mux(issue_sel_14, entries_ex[14].bits.deps_ex[12], UInt<1>(0h0)) node _issue_entry_T_2344 = mux(issue_sel_15, entries_ex[15].bits.deps_ex[12], UInt<1>(0h0)) node _issue_entry_T_2345 = or(_issue_entry_T_2329, _issue_entry_T_2330) node _issue_entry_T_2346 = or(_issue_entry_T_2345, _issue_entry_T_2331) node _issue_entry_T_2347 = or(_issue_entry_T_2346, _issue_entry_T_2332) node _issue_entry_T_2348 = or(_issue_entry_T_2347, _issue_entry_T_2333) node _issue_entry_T_2349 = or(_issue_entry_T_2348, _issue_entry_T_2334) node _issue_entry_T_2350 = or(_issue_entry_T_2349, _issue_entry_T_2335) node _issue_entry_T_2351 = or(_issue_entry_T_2350, _issue_entry_T_2336) node _issue_entry_T_2352 = or(_issue_entry_T_2351, _issue_entry_T_2337) node _issue_entry_T_2353 = or(_issue_entry_T_2352, _issue_entry_T_2338) node _issue_entry_T_2354 = or(_issue_entry_T_2353, _issue_entry_T_2339) node _issue_entry_T_2355 = or(_issue_entry_T_2354, _issue_entry_T_2340) node _issue_entry_T_2356 = or(_issue_entry_T_2355, _issue_entry_T_2341) node _issue_entry_T_2357 = or(_issue_entry_T_2356, _issue_entry_T_2342) node _issue_entry_T_2358 = or(_issue_entry_T_2357, _issue_entry_T_2343) node _issue_entry_T_2359 = or(_issue_entry_T_2358, _issue_entry_T_2344) wire _issue_entry_WIRE_163 : UInt<1> connect _issue_entry_WIRE_163, _issue_entry_T_2359 connect _issue_entry_WIRE_150[12], _issue_entry_WIRE_163 node _issue_entry_T_2360 = mux(issue_sel_0_1, entries_ex[0].bits.deps_ex[13], UInt<1>(0h0)) node _issue_entry_T_2361 = mux(issue_sel_1_1, entries_ex[1].bits.deps_ex[13], UInt<1>(0h0)) node _issue_entry_T_2362 = mux(issue_sel_2_1, entries_ex[2].bits.deps_ex[13], UInt<1>(0h0)) node _issue_entry_T_2363 = mux(issue_sel_3_1, entries_ex[3].bits.deps_ex[13], UInt<1>(0h0)) node _issue_entry_T_2364 = mux(issue_sel_4_1, entries_ex[4].bits.deps_ex[13], UInt<1>(0h0)) node _issue_entry_T_2365 = mux(issue_sel_5_1, entries_ex[5].bits.deps_ex[13], UInt<1>(0h0)) node _issue_entry_T_2366 = mux(issue_sel_6_1, entries_ex[6].bits.deps_ex[13], UInt<1>(0h0)) node _issue_entry_T_2367 = mux(issue_sel_7_1, entries_ex[7].bits.deps_ex[13], UInt<1>(0h0)) node _issue_entry_T_2368 = mux(issue_sel_8, entries_ex[8].bits.deps_ex[13], UInt<1>(0h0)) node _issue_entry_T_2369 = mux(issue_sel_9, entries_ex[9].bits.deps_ex[13], UInt<1>(0h0)) node _issue_entry_T_2370 = mux(issue_sel_10, entries_ex[10].bits.deps_ex[13], UInt<1>(0h0)) node _issue_entry_T_2371 = mux(issue_sel_11, entries_ex[11].bits.deps_ex[13], UInt<1>(0h0)) node _issue_entry_T_2372 = mux(issue_sel_12, entries_ex[12].bits.deps_ex[13], UInt<1>(0h0)) node _issue_entry_T_2373 = mux(issue_sel_13, entries_ex[13].bits.deps_ex[13], UInt<1>(0h0)) node _issue_entry_T_2374 = mux(issue_sel_14, entries_ex[14].bits.deps_ex[13], UInt<1>(0h0)) node _issue_entry_T_2375 = mux(issue_sel_15, entries_ex[15].bits.deps_ex[13], UInt<1>(0h0)) node _issue_entry_T_2376 = or(_issue_entry_T_2360, _issue_entry_T_2361) node _issue_entry_T_2377 = or(_issue_entry_T_2376, _issue_entry_T_2362) node _issue_entry_T_2378 = or(_issue_entry_T_2377, _issue_entry_T_2363) node _issue_entry_T_2379 = or(_issue_entry_T_2378, _issue_entry_T_2364) node _issue_entry_T_2380 = or(_issue_entry_T_2379, _issue_entry_T_2365) node _issue_entry_T_2381 = or(_issue_entry_T_2380, _issue_entry_T_2366) node _issue_entry_T_2382 = or(_issue_entry_T_2381, _issue_entry_T_2367) node _issue_entry_T_2383 = or(_issue_entry_T_2382, _issue_entry_T_2368) node _issue_entry_T_2384 = or(_issue_entry_T_2383, _issue_entry_T_2369) node _issue_entry_T_2385 = or(_issue_entry_T_2384, _issue_entry_T_2370) node _issue_entry_T_2386 = or(_issue_entry_T_2385, _issue_entry_T_2371) node _issue_entry_T_2387 = or(_issue_entry_T_2386, _issue_entry_T_2372) node _issue_entry_T_2388 = or(_issue_entry_T_2387, _issue_entry_T_2373) node _issue_entry_T_2389 = or(_issue_entry_T_2388, _issue_entry_T_2374) node _issue_entry_T_2390 = or(_issue_entry_T_2389, _issue_entry_T_2375) wire _issue_entry_WIRE_164 : UInt<1> connect _issue_entry_WIRE_164, _issue_entry_T_2390 connect _issue_entry_WIRE_150[13], _issue_entry_WIRE_164 node _issue_entry_T_2391 = mux(issue_sel_0_1, entries_ex[0].bits.deps_ex[14], UInt<1>(0h0)) node _issue_entry_T_2392 = mux(issue_sel_1_1, entries_ex[1].bits.deps_ex[14], UInt<1>(0h0)) node _issue_entry_T_2393 = mux(issue_sel_2_1, entries_ex[2].bits.deps_ex[14], UInt<1>(0h0)) node _issue_entry_T_2394 = mux(issue_sel_3_1, entries_ex[3].bits.deps_ex[14], UInt<1>(0h0)) node _issue_entry_T_2395 = mux(issue_sel_4_1, entries_ex[4].bits.deps_ex[14], UInt<1>(0h0)) node _issue_entry_T_2396 = mux(issue_sel_5_1, entries_ex[5].bits.deps_ex[14], UInt<1>(0h0)) node _issue_entry_T_2397 = mux(issue_sel_6_1, entries_ex[6].bits.deps_ex[14], UInt<1>(0h0)) node _issue_entry_T_2398 = mux(issue_sel_7_1, entries_ex[7].bits.deps_ex[14], UInt<1>(0h0)) node _issue_entry_T_2399 = mux(issue_sel_8, entries_ex[8].bits.deps_ex[14], UInt<1>(0h0)) node _issue_entry_T_2400 = mux(issue_sel_9, entries_ex[9].bits.deps_ex[14], UInt<1>(0h0)) node _issue_entry_T_2401 = mux(issue_sel_10, entries_ex[10].bits.deps_ex[14], UInt<1>(0h0)) node _issue_entry_T_2402 = mux(issue_sel_11, entries_ex[11].bits.deps_ex[14], UInt<1>(0h0)) node _issue_entry_T_2403 = mux(issue_sel_12, entries_ex[12].bits.deps_ex[14], UInt<1>(0h0)) node _issue_entry_T_2404 = mux(issue_sel_13, entries_ex[13].bits.deps_ex[14], UInt<1>(0h0)) node _issue_entry_T_2405 = mux(issue_sel_14, entries_ex[14].bits.deps_ex[14], UInt<1>(0h0)) node _issue_entry_T_2406 = mux(issue_sel_15, entries_ex[15].bits.deps_ex[14], UInt<1>(0h0)) node _issue_entry_T_2407 = or(_issue_entry_T_2391, _issue_entry_T_2392) node _issue_entry_T_2408 = or(_issue_entry_T_2407, _issue_entry_T_2393) node _issue_entry_T_2409 = or(_issue_entry_T_2408, _issue_entry_T_2394) node _issue_entry_T_2410 = or(_issue_entry_T_2409, _issue_entry_T_2395) node _issue_entry_T_2411 = or(_issue_entry_T_2410, _issue_entry_T_2396) node _issue_entry_T_2412 = or(_issue_entry_T_2411, _issue_entry_T_2397) node _issue_entry_T_2413 = or(_issue_entry_T_2412, _issue_entry_T_2398) node _issue_entry_T_2414 = or(_issue_entry_T_2413, _issue_entry_T_2399) node _issue_entry_T_2415 = or(_issue_entry_T_2414, _issue_entry_T_2400) node _issue_entry_T_2416 = or(_issue_entry_T_2415, _issue_entry_T_2401) node _issue_entry_T_2417 = or(_issue_entry_T_2416, _issue_entry_T_2402) node _issue_entry_T_2418 = or(_issue_entry_T_2417, _issue_entry_T_2403) node _issue_entry_T_2419 = or(_issue_entry_T_2418, _issue_entry_T_2404) node _issue_entry_T_2420 = or(_issue_entry_T_2419, _issue_entry_T_2405) node _issue_entry_T_2421 = or(_issue_entry_T_2420, _issue_entry_T_2406) wire _issue_entry_WIRE_165 : UInt<1> connect _issue_entry_WIRE_165, _issue_entry_T_2421 connect _issue_entry_WIRE_150[14], _issue_entry_WIRE_165 node _issue_entry_T_2422 = mux(issue_sel_0_1, entries_ex[0].bits.deps_ex[15], UInt<1>(0h0)) node _issue_entry_T_2423 = mux(issue_sel_1_1, entries_ex[1].bits.deps_ex[15], UInt<1>(0h0)) node _issue_entry_T_2424 = mux(issue_sel_2_1, entries_ex[2].bits.deps_ex[15], UInt<1>(0h0)) node _issue_entry_T_2425 = mux(issue_sel_3_1, entries_ex[3].bits.deps_ex[15], UInt<1>(0h0)) node _issue_entry_T_2426 = mux(issue_sel_4_1, entries_ex[4].bits.deps_ex[15], UInt<1>(0h0)) node _issue_entry_T_2427 = mux(issue_sel_5_1, entries_ex[5].bits.deps_ex[15], UInt<1>(0h0)) node _issue_entry_T_2428 = mux(issue_sel_6_1, entries_ex[6].bits.deps_ex[15], UInt<1>(0h0)) node _issue_entry_T_2429 = mux(issue_sel_7_1, entries_ex[7].bits.deps_ex[15], UInt<1>(0h0)) node _issue_entry_T_2430 = mux(issue_sel_8, entries_ex[8].bits.deps_ex[15], UInt<1>(0h0)) node _issue_entry_T_2431 = mux(issue_sel_9, entries_ex[9].bits.deps_ex[15], UInt<1>(0h0)) node _issue_entry_T_2432 = mux(issue_sel_10, entries_ex[10].bits.deps_ex[15], UInt<1>(0h0)) node _issue_entry_T_2433 = mux(issue_sel_11, entries_ex[11].bits.deps_ex[15], UInt<1>(0h0)) node _issue_entry_T_2434 = mux(issue_sel_12, entries_ex[12].bits.deps_ex[15], UInt<1>(0h0)) node _issue_entry_T_2435 = mux(issue_sel_13, entries_ex[13].bits.deps_ex[15], UInt<1>(0h0)) node _issue_entry_T_2436 = mux(issue_sel_14, entries_ex[14].bits.deps_ex[15], UInt<1>(0h0)) node _issue_entry_T_2437 = mux(issue_sel_15, entries_ex[15].bits.deps_ex[15], UInt<1>(0h0)) node _issue_entry_T_2438 = or(_issue_entry_T_2422, _issue_entry_T_2423) node _issue_entry_T_2439 = or(_issue_entry_T_2438, _issue_entry_T_2424) node _issue_entry_T_2440 = or(_issue_entry_T_2439, _issue_entry_T_2425) node _issue_entry_T_2441 = or(_issue_entry_T_2440, _issue_entry_T_2426) node _issue_entry_T_2442 = or(_issue_entry_T_2441, _issue_entry_T_2427) node _issue_entry_T_2443 = or(_issue_entry_T_2442, _issue_entry_T_2428) node _issue_entry_T_2444 = or(_issue_entry_T_2443, _issue_entry_T_2429) node _issue_entry_T_2445 = or(_issue_entry_T_2444, _issue_entry_T_2430) node _issue_entry_T_2446 = or(_issue_entry_T_2445, _issue_entry_T_2431) node _issue_entry_T_2447 = or(_issue_entry_T_2446, _issue_entry_T_2432) node _issue_entry_T_2448 = or(_issue_entry_T_2447, _issue_entry_T_2433) node _issue_entry_T_2449 = or(_issue_entry_T_2448, _issue_entry_T_2434) node _issue_entry_T_2450 = or(_issue_entry_T_2449, _issue_entry_T_2435) node _issue_entry_T_2451 = or(_issue_entry_T_2450, _issue_entry_T_2436) node _issue_entry_T_2452 = or(_issue_entry_T_2451, _issue_entry_T_2437) wire _issue_entry_WIRE_166 : UInt<1> connect _issue_entry_WIRE_166, _issue_entry_T_2452 connect _issue_entry_WIRE_150[15], _issue_entry_WIRE_166 connect _issue_entry_WIRE_143.deps_ex, _issue_entry_WIRE_150 wire _issue_entry_WIRE_167 : UInt<1>[8] node _issue_entry_T_2453 = mux(issue_sel_0_1, entries_ex[0].bits.deps_ld[0], UInt<1>(0h0)) node _issue_entry_T_2454 = mux(issue_sel_1_1, entries_ex[1].bits.deps_ld[0], UInt<1>(0h0)) node _issue_entry_T_2455 = mux(issue_sel_2_1, entries_ex[2].bits.deps_ld[0], UInt<1>(0h0)) node _issue_entry_T_2456 = mux(issue_sel_3_1, entries_ex[3].bits.deps_ld[0], UInt<1>(0h0)) node _issue_entry_T_2457 = mux(issue_sel_4_1, entries_ex[4].bits.deps_ld[0], UInt<1>(0h0)) node _issue_entry_T_2458 = mux(issue_sel_5_1, entries_ex[5].bits.deps_ld[0], UInt<1>(0h0)) node _issue_entry_T_2459 = mux(issue_sel_6_1, entries_ex[6].bits.deps_ld[0], UInt<1>(0h0)) node _issue_entry_T_2460 = mux(issue_sel_7_1, entries_ex[7].bits.deps_ld[0], UInt<1>(0h0)) node _issue_entry_T_2461 = mux(issue_sel_8, entries_ex[8].bits.deps_ld[0], UInt<1>(0h0)) node _issue_entry_T_2462 = mux(issue_sel_9, entries_ex[9].bits.deps_ld[0], UInt<1>(0h0)) node _issue_entry_T_2463 = mux(issue_sel_10, entries_ex[10].bits.deps_ld[0], UInt<1>(0h0)) node _issue_entry_T_2464 = mux(issue_sel_11, entries_ex[11].bits.deps_ld[0], UInt<1>(0h0)) node _issue_entry_T_2465 = mux(issue_sel_12, entries_ex[12].bits.deps_ld[0], UInt<1>(0h0)) node _issue_entry_T_2466 = mux(issue_sel_13, entries_ex[13].bits.deps_ld[0], UInt<1>(0h0)) node _issue_entry_T_2467 = mux(issue_sel_14, entries_ex[14].bits.deps_ld[0], UInt<1>(0h0)) node _issue_entry_T_2468 = mux(issue_sel_15, entries_ex[15].bits.deps_ld[0], UInt<1>(0h0)) node _issue_entry_T_2469 = or(_issue_entry_T_2453, _issue_entry_T_2454) node _issue_entry_T_2470 = or(_issue_entry_T_2469, _issue_entry_T_2455) node _issue_entry_T_2471 = or(_issue_entry_T_2470, _issue_entry_T_2456) node _issue_entry_T_2472 = or(_issue_entry_T_2471, _issue_entry_T_2457) node _issue_entry_T_2473 = or(_issue_entry_T_2472, _issue_entry_T_2458) node _issue_entry_T_2474 = or(_issue_entry_T_2473, _issue_entry_T_2459) node _issue_entry_T_2475 = or(_issue_entry_T_2474, _issue_entry_T_2460) node _issue_entry_T_2476 = or(_issue_entry_T_2475, _issue_entry_T_2461) node _issue_entry_T_2477 = or(_issue_entry_T_2476, _issue_entry_T_2462) node _issue_entry_T_2478 = or(_issue_entry_T_2477, _issue_entry_T_2463) node _issue_entry_T_2479 = or(_issue_entry_T_2478, _issue_entry_T_2464) node _issue_entry_T_2480 = or(_issue_entry_T_2479, _issue_entry_T_2465) node _issue_entry_T_2481 = or(_issue_entry_T_2480, _issue_entry_T_2466) node _issue_entry_T_2482 = or(_issue_entry_T_2481, _issue_entry_T_2467) node _issue_entry_T_2483 = or(_issue_entry_T_2482, _issue_entry_T_2468) wire _issue_entry_WIRE_168 : UInt<1> connect _issue_entry_WIRE_168, _issue_entry_T_2483 connect _issue_entry_WIRE_167[0], _issue_entry_WIRE_168 node _issue_entry_T_2484 = mux(issue_sel_0_1, entries_ex[0].bits.deps_ld[1], UInt<1>(0h0)) node _issue_entry_T_2485 = mux(issue_sel_1_1, entries_ex[1].bits.deps_ld[1], UInt<1>(0h0)) node _issue_entry_T_2486 = mux(issue_sel_2_1, entries_ex[2].bits.deps_ld[1], UInt<1>(0h0)) node _issue_entry_T_2487 = mux(issue_sel_3_1, entries_ex[3].bits.deps_ld[1], UInt<1>(0h0)) node _issue_entry_T_2488 = mux(issue_sel_4_1, entries_ex[4].bits.deps_ld[1], UInt<1>(0h0)) node _issue_entry_T_2489 = mux(issue_sel_5_1, entries_ex[5].bits.deps_ld[1], UInt<1>(0h0)) node _issue_entry_T_2490 = mux(issue_sel_6_1, entries_ex[6].bits.deps_ld[1], UInt<1>(0h0)) node _issue_entry_T_2491 = mux(issue_sel_7_1, entries_ex[7].bits.deps_ld[1], UInt<1>(0h0)) node _issue_entry_T_2492 = mux(issue_sel_8, entries_ex[8].bits.deps_ld[1], UInt<1>(0h0)) node _issue_entry_T_2493 = mux(issue_sel_9, entries_ex[9].bits.deps_ld[1], UInt<1>(0h0)) node _issue_entry_T_2494 = mux(issue_sel_10, entries_ex[10].bits.deps_ld[1], UInt<1>(0h0)) node _issue_entry_T_2495 = mux(issue_sel_11, entries_ex[11].bits.deps_ld[1], UInt<1>(0h0)) node _issue_entry_T_2496 = mux(issue_sel_12, entries_ex[12].bits.deps_ld[1], UInt<1>(0h0)) node _issue_entry_T_2497 = mux(issue_sel_13, entries_ex[13].bits.deps_ld[1], UInt<1>(0h0)) node _issue_entry_T_2498 = mux(issue_sel_14, entries_ex[14].bits.deps_ld[1], UInt<1>(0h0)) node _issue_entry_T_2499 = mux(issue_sel_15, entries_ex[15].bits.deps_ld[1], UInt<1>(0h0)) node _issue_entry_T_2500 = or(_issue_entry_T_2484, _issue_entry_T_2485) node _issue_entry_T_2501 = or(_issue_entry_T_2500, _issue_entry_T_2486) node _issue_entry_T_2502 = or(_issue_entry_T_2501, _issue_entry_T_2487) node _issue_entry_T_2503 = or(_issue_entry_T_2502, _issue_entry_T_2488) node _issue_entry_T_2504 = or(_issue_entry_T_2503, _issue_entry_T_2489) node _issue_entry_T_2505 = or(_issue_entry_T_2504, _issue_entry_T_2490) node _issue_entry_T_2506 = or(_issue_entry_T_2505, _issue_entry_T_2491) node _issue_entry_T_2507 = or(_issue_entry_T_2506, _issue_entry_T_2492) node _issue_entry_T_2508 = or(_issue_entry_T_2507, _issue_entry_T_2493) node _issue_entry_T_2509 = or(_issue_entry_T_2508, _issue_entry_T_2494) node _issue_entry_T_2510 = or(_issue_entry_T_2509, _issue_entry_T_2495) node _issue_entry_T_2511 = or(_issue_entry_T_2510, _issue_entry_T_2496) node _issue_entry_T_2512 = or(_issue_entry_T_2511, _issue_entry_T_2497) node _issue_entry_T_2513 = or(_issue_entry_T_2512, _issue_entry_T_2498) node _issue_entry_T_2514 = or(_issue_entry_T_2513, _issue_entry_T_2499) wire _issue_entry_WIRE_169 : UInt<1> connect _issue_entry_WIRE_169, _issue_entry_T_2514 connect _issue_entry_WIRE_167[1], _issue_entry_WIRE_169 node _issue_entry_T_2515 = mux(issue_sel_0_1, entries_ex[0].bits.deps_ld[2], UInt<1>(0h0)) node _issue_entry_T_2516 = mux(issue_sel_1_1, entries_ex[1].bits.deps_ld[2], UInt<1>(0h0)) node _issue_entry_T_2517 = mux(issue_sel_2_1, entries_ex[2].bits.deps_ld[2], UInt<1>(0h0)) node _issue_entry_T_2518 = mux(issue_sel_3_1, entries_ex[3].bits.deps_ld[2], UInt<1>(0h0)) node _issue_entry_T_2519 = mux(issue_sel_4_1, entries_ex[4].bits.deps_ld[2], UInt<1>(0h0)) node _issue_entry_T_2520 = mux(issue_sel_5_1, entries_ex[5].bits.deps_ld[2], UInt<1>(0h0)) node _issue_entry_T_2521 = mux(issue_sel_6_1, entries_ex[6].bits.deps_ld[2], UInt<1>(0h0)) node _issue_entry_T_2522 = mux(issue_sel_7_1, entries_ex[7].bits.deps_ld[2], UInt<1>(0h0)) node _issue_entry_T_2523 = mux(issue_sel_8, entries_ex[8].bits.deps_ld[2], UInt<1>(0h0)) node _issue_entry_T_2524 = mux(issue_sel_9, entries_ex[9].bits.deps_ld[2], UInt<1>(0h0)) node _issue_entry_T_2525 = mux(issue_sel_10, entries_ex[10].bits.deps_ld[2], UInt<1>(0h0)) node _issue_entry_T_2526 = mux(issue_sel_11, entries_ex[11].bits.deps_ld[2], UInt<1>(0h0)) node _issue_entry_T_2527 = mux(issue_sel_12, entries_ex[12].bits.deps_ld[2], UInt<1>(0h0)) node _issue_entry_T_2528 = mux(issue_sel_13, entries_ex[13].bits.deps_ld[2], UInt<1>(0h0)) node _issue_entry_T_2529 = mux(issue_sel_14, entries_ex[14].bits.deps_ld[2], UInt<1>(0h0)) node _issue_entry_T_2530 = mux(issue_sel_15, entries_ex[15].bits.deps_ld[2], UInt<1>(0h0)) node _issue_entry_T_2531 = or(_issue_entry_T_2515, _issue_entry_T_2516) node _issue_entry_T_2532 = or(_issue_entry_T_2531, _issue_entry_T_2517) node _issue_entry_T_2533 = or(_issue_entry_T_2532, _issue_entry_T_2518) node _issue_entry_T_2534 = or(_issue_entry_T_2533, _issue_entry_T_2519) node _issue_entry_T_2535 = or(_issue_entry_T_2534, _issue_entry_T_2520) node _issue_entry_T_2536 = or(_issue_entry_T_2535, _issue_entry_T_2521) node _issue_entry_T_2537 = or(_issue_entry_T_2536, _issue_entry_T_2522) node _issue_entry_T_2538 = or(_issue_entry_T_2537, _issue_entry_T_2523) node _issue_entry_T_2539 = or(_issue_entry_T_2538, _issue_entry_T_2524) node _issue_entry_T_2540 = or(_issue_entry_T_2539, _issue_entry_T_2525) node _issue_entry_T_2541 = or(_issue_entry_T_2540, _issue_entry_T_2526) node _issue_entry_T_2542 = or(_issue_entry_T_2541, _issue_entry_T_2527) node _issue_entry_T_2543 = or(_issue_entry_T_2542, _issue_entry_T_2528) node _issue_entry_T_2544 = or(_issue_entry_T_2543, _issue_entry_T_2529) node _issue_entry_T_2545 = or(_issue_entry_T_2544, _issue_entry_T_2530) wire _issue_entry_WIRE_170 : UInt<1> connect _issue_entry_WIRE_170, _issue_entry_T_2545 connect _issue_entry_WIRE_167[2], _issue_entry_WIRE_170 node _issue_entry_T_2546 = mux(issue_sel_0_1, entries_ex[0].bits.deps_ld[3], UInt<1>(0h0)) node _issue_entry_T_2547 = mux(issue_sel_1_1, entries_ex[1].bits.deps_ld[3], UInt<1>(0h0)) node _issue_entry_T_2548 = mux(issue_sel_2_1, entries_ex[2].bits.deps_ld[3], UInt<1>(0h0)) node _issue_entry_T_2549 = mux(issue_sel_3_1, entries_ex[3].bits.deps_ld[3], UInt<1>(0h0)) node _issue_entry_T_2550 = mux(issue_sel_4_1, entries_ex[4].bits.deps_ld[3], UInt<1>(0h0)) node _issue_entry_T_2551 = mux(issue_sel_5_1, entries_ex[5].bits.deps_ld[3], UInt<1>(0h0)) node _issue_entry_T_2552 = mux(issue_sel_6_1, entries_ex[6].bits.deps_ld[3], UInt<1>(0h0)) node _issue_entry_T_2553 = mux(issue_sel_7_1, entries_ex[7].bits.deps_ld[3], UInt<1>(0h0)) node _issue_entry_T_2554 = mux(issue_sel_8, entries_ex[8].bits.deps_ld[3], UInt<1>(0h0)) node _issue_entry_T_2555 = mux(issue_sel_9, entries_ex[9].bits.deps_ld[3], UInt<1>(0h0)) node _issue_entry_T_2556 = mux(issue_sel_10, entries_ex[10].bits.deps_ld[3], UInt<1>(0h0)) node _issue_entry_T_2557 = mux(issue_sel_11, entries_ex[11].bits.deps_ld[3], UInt<1>(0h0)) node _issue_entry_T_2558 = mux(issue_sel_12, entries_ex[12].bits.deps_ld[3], UInt<1>(0h0)) node _issue_entry_T_2559 = mux(issue_sel_13, entries_ex[13].bits.deps_ld[3], UInt<1>(0h0)) node _issue_entry_T_2560 = mux(issue_sel_14, entries_ex[14].bits.deps_ld[3], UInt<1>(0h0)) node _issue_entry_T_2561 = mux(issue_sel_15, entries_ex[15].bits.deps_ld[3], UInt<1>(0h0)) node _issue_entry_T_2562 = or(_issue_entry_T_2546, _issue_entry_T_2547) node _issue_entry_T_2563 = or(_issue_entry_T_2562, _issue_entry_T_2548) node _issue_entry_T_2564 = or(_issue_entry_T_2563, _issue_entry_T_2549) node _issue_entry_T_2565 = or(_issue_entry_T_2564, _issue_entry_T_2550) node _issue_entry_T_2566 = or(_issue_entry_T_2565, _issue_entry_T_2551) node _issue_entry_T_2567 = or(_issue_entry_T_2566, _issue_entry_T_2552) node _issue_entry_T_2568 = or(_issue_entry_T_2567, _issue_entry_T_2553) node _issue_entry_T_2569 = or(_issue_entry_T_2568, _issue_entry_T_2554) node _issue_entry_T_2570 = or(_issue_entry_T_2569, _issue_entry_T_2555) node _issue_entry_T_2571 = or(_issue_entry_T_2570, _issue_entry_T_2556) node _issue_entry_T_2572 = or(_issue_entry_T_2571, _issue_entry_T_2557) node _issue_entry_T_2573 = or(_issue_entry_T_2572, _issue_entry_T_2558) node _issue_entry_T_2574 = or(_issue_entry_T_2573, _issue_entry_T_2559) node _issue_entry_T_2575 = or(_issue_entry_T_2574, _issue_entry_T_2560) node _issue_entry_T_2576 = or(_issue_entry_T_2575, _issue_entry_T_2561) wire _issue_entry_WIRE_171 : UInt<1> connect _issue_entry_WIRE_171, _issue_entry_T_2576 connect _issue_entry_WIRE_167[3], _issue_entry_WIRE_171 node _issue_entry_T_2577 = mux(issue_sel_0_1, entries_ex[0].bits.deps_ld[4], UInt<1>(0h0)) node _issue_entry_T_2578 = mux(issue_sel_1_1, entries_ex[1].bits.deps_ld[4], UInt<1>(0h0)) node _issue_entry_T_2579 = mux(issue_sel_2_1, entries_ex[2].bits.deps_ld[4], UInt<1>(0h0)) node _issue_entry_T_2580 = mux(issue_sel_3_1, entries_ex[3].bits.deps_ld[4], UInt<1>(0h0)) node _issue_entry_T_2581 = mux(issue_sel_4_1, entries_ex[4].bits.deps_ld[4], UInt<1>(0h0)) node _issue_entry_T_2582 = mux(issue_sel_5_1, entries_ex[5].bits.deps_ld[4], UInt<1>(0h0)) node _issue_entry_T_2583 = mux(issue_sel_6_1, entries_ex[6].bits.deps_ld[4], UInt<1>(0h0)) node _issue_entry_T_2584 = mux(issue_sel_7_1, entries_ex[7].bits.deps_ld[4], UInt<1>(0h0)) node _issue_entry_T_2585 = mux(issue_sel_8, entries_ex[8].bits.deps_ld[4], UInt<1>(0h0)) node _issue_entry_T_2586 = mux(issue_sel_9, entries_ex[9].bits.deps_ld[4], UInt<1>(0h0)) node _issue_entry_T_2587 = mux(issue_sel_10, entries_ex[10].bits.deps_ld[4], UInt<1>(0h0)) node _issue_entry_T_2588 = mux(issue_sel_11, entries_ex[11].bits.deps_ld[4], UInt<1>(0h0)) node _issue_entry_T_2589 = mux(issue_sel_12, entries_ex[12].bits.deps_ld[4], UInt<1>(0h0)) node _issue_entry_T_2590 = mux(issue_sel_13, entries_ex[13].bits.deps_ld[4], UInt<1>(0h0)) node _issue_entry_T_2591 = mux(issue_sel_14, entries_ex[14].bits.deps_ld[4], UInt<1>(0h0)) node _issue_entry_T_2592 = mux(issue_sel_15, entries_ex[15].bits.deps_ld[4], UInt<1>(0h0)) node _issue_entry_T_2593 = or(_issue_entry_T_2577, _issue_entry_T_2578) node _issue_entry_T_2594 = or(_issue_entry_T_2593, _issue_entry_T_2579) node _issue_entry_T_2595 = or(_issue_entry_T_2594, _issue_entry_T_2580) node _issue_entry_T_2596 = or(_issue_entry_T_2595, _issue_entry_T_2581) node _issue_entry_T_2597 = or(_issue_entry_T_2596, _issue_entry_T_2582) node _issue_entry_T_2598 = or(_issue_entry_T_2597, _issue_entry_T_2583) node _issue_entry_T_2599 = or(_issue_entry_T_2598, _issue_entry_T_2584) node _issue_entry_T_2600 = or(_issue_entry_T_2599, _issue_entry_T_2585) node _issue_entry_T_2601 = or(_issue_entry_T_2600, _issue_entry_T_2586) node _issue_entry_T_2602 = or(_issue_entry_T_2601, _issue_entry_T_2587) node _issue_entry_T_2603 = or(_issue_entry_T_2602, _issue_entry_T_2588) node _issue_entry_T_2604 = or(_issue_entry_T_2603, _issue_entry_T_2589) node _issue_entry_T_2605 = or(_issue_entry_T_2604, _issue_entry_T_2590) node _issue_entry_T_2606 = or(_issue_entry_T_2605, _issue_entry_T_2591) node _issue_entry_T_2607 = or(_issue_entry_T_2606, _issue_entry_T_2592) wire _issue_entry_WIRE_172 : UInt<1> connect _issue_entry_WIRE_172, _issue_entry_T_2607 connect _issue_entry_WIRE_167[4], _issue_entry_WIRE_172 node _issue_entry_T_2608 = mux(issue_sel_0_1, entries_ex[0].bits.deps_ld[5], UInt<1>(0h0)) node _issue_entry_T_2609 = mux(issue_sel_1_1, entries_ex[1].bits.deps_ld[5], UInt<1>(0h0)) node _issue_entry_T_2610 = mux(issue_sel_2_1, entries_ex[2].bits.deps_ld[5], UInt<1>(0h0)) node _issue_entry_T_2611 = mux(issue_sel_3_1, entries_ex[3].bits.deps_ld[5], UInt<1>(0h0)) node _issue_entry_T_2612 = mux(issue_sel_4_1, entries_ex[4].bits.deps_ld[5], UInt<1>(0h0)) node _issue_entry_T_2613 = mux(issue_sel_5_1, entries_ex[5].bits.deps_ld[5], UInt<1>(0h0)) node _issue_entry_T_2614 = mux(issue_sel_6_1, entries_ex[6].bits.deps_ld[5], UInt<1>(0h0)) node _issue_entry_T_2615 = mux(issue_sel_7_1, entries_ex[7].bits.deps_ld[5], UInt<1>(0h0)) node _issue_entry_T_2616 = mux(issue_sel_8, entries_ex[8].bits.deps_ld[5], UInt<1>(0h0)) node _issue_entry_T_2617 = mux(issue_sel_9, entries_ex[9].bits.deps_ld[5], UInt<1>(0h0)) node _issue_entry_T_2618 = mux(issue_sel_10, entries_ex[10].bits.deps_ld[5], UInt<1>(0h0)) node _issue_entry_T_2619 = mux(issue_sel_11, entries_ex[11].bits.deps_ld[5], UInt<1>(0h0)) node _issue_entry_T_2620 = mux(issue_sel_12, entries_ex[12].bits.deps_ld[5], UInt<1>(0h0)) node _issue_entry_T_2621 = mux(issue_sel_13, entries_ex[13].bits.deps_ld[5], UInt<1>(0h0)) node _issue_entry_T_2622 = mux(issue_sel_14, entries_ex[14].bits.deps_ld[5], UInt<1>(0h0)) node _issue_entry_T_2623 = mux(issue_sel_15, entries_ex[15].bits.deps_ld[5], UInt<1>(0h0)) node _issue_entry_T_2624 = or(_issue_entry_T_2608, _issue_entry_T_2609) node _issue_entry_T_2625 = or(_issue_entry_T_2624, _issue_entry_T_2610) node _issue_entry_T_2626 = or(_issue_entry_T_2625, _issue_entry_T_2611) node _issue_entry_T_2627 = or(_issue_entry_T_2626, _issue_entry_T_2612) node _issue_entry_T_2628 = or(_issue_entry_T_2627, _issue_entry_T_2613) node _issue_entry_T_2629 = or(_issue_entry_T_2628, _issue_entry_T_2614) node _issue_entry_T_2630 = or(_issue_entry_T_2629, _issue_entry_T_2615) node _issue_entry_T_2631 = or(_issue_entry_T_2630, _issue_entry_T_2616) node _issue_entry_T_2632 = or(_issue_entry_T_2631, _issue_entry_T_2617) node _issue_entry_T_2633 = or(_issue_entry_T_2632, _issue_entry_T_2618) node _issue_entry_T_2634 = or(_issue_entry_T_2633, _issue_entry_T_2619) node _issue_entry_T_2635 = or(_issue_entry_T_2634, _issue_entry_T_2620) node _issue_entry_T_2636 = or(_issue_entry_T_2635, _issue_entry_T_2621) node _issue_entry_T_2637 = or(_issue_entry_T_2636, _issue_entry_T_2622) node _issue_entry_T_2638 = or(_issue_entry_T_2637, _issue_entry_T_2623) wire _issue_entry_WIRE_173 : UInt<1> connect _issue_entry_WIRE_173, _issue_entry_T_2638 connect _issue_entry_WIRE_167[5], _issue_entry_WIRE_173 node _issue_entry_T_2639 = mux(issue_sel_0_1, entries_ex[0].bits.deps_ld[6], UInt<1>(0h0)) node _issue_entry_T_2640 = mux(issue_sel_1_1, entries_ex[1].bits.deps_ld[6], UInt<1>(0h0)) node _issue_entry_T_2641 = mux(issue_sel_2_1, entries_ex[2].bits.deps_ld[6], UInt<1>(0h0)) node _issue_entry_T_2642 = mux(issue_sel_3_1, entries_ex[3].bits.deps_ld[6], UInt<1>(0h0)) node _issue_entry_T_2643 = mux(issue_sel_4_1, entries_ex[4].bits.deps_ld[6], UInt<1>(0h0)) node _issue_entry_T_2644 = mux(issue_sel_5_1, entries_ex[5].bits.deps_ld[6], UInt<1>(0h0)) node _issue_entry_T_2645 = mux(issue_sel_6_1, entries_ex[6].bits.deps_ld[6], UInt<1>(0h0)) node _issue_entry_T_2646 = mux(issue_sel_7_1, entries_ex[7].bits.deps_ld[6], UInt<1>(0h0)) node _issue_entry_T_2647 = mux(issue_sel_8, entries_ex[8].bits.deps_ld[6], UInt<1>(0h0)) node _issue_entry_T_2648 = mux(issue_sel_9, entries_ex[9].bits.deps_ld[6], UInt<1>(0h0)) node _issue_entry_T_2649 = mux(issue_sel_10, entries_ex[10].bits.deps_ld[6], UInt<1>(0h0)) node _issue_entry_T_2650 = mux(issue_sel_11, entries_ex[11].bits.deps_ld[6], UInt<1>(0h0)) node _issue_entry_T_2651 = mux(issue_sel_12, entries_ex[12].bits.deps_ld[6], UInt<1>(0h0)) node _issue_entry_T_2652 = mux(issue_sel_13, entries_ex[13].bits.deps_ld[6], UInt<1>(0h0)) node _issue_entry_T_2653 = mux(issue_sel_14, entries_ex[14].bits.deps_ld[6], UInt<1>(0h0)) node _issue_entry_T_2654 = mux(issue_sel_15, entries_ex[15].bits.deps_ld[6], UInt<1>(0h0)) node _issue_entry_T_2655 = or(_issue_entry_T_2639, _issue_entry_T_2640) node _issue_entry_T_2656 = or(_issue_entry_T_2655, _issue_entry_T_2641) node _issue_entry_T_2657 = or(_issue_entry_T_2656, _issue_entry_T_2642) node _issue_entry_T_2658 = or(_issue_entry_T_2657, _issue_entry_T_2643) node _issue_entry_T_2659 = or(_issue_entry_T_2658, _issue_entry_T_2644) node _issue_entry_T_2660 = or(_issue_entry_T_2659, _issue_entry_T_2645) node _issue_entry_T_2661 = or(_issue_entry_T_2660, _issue_entry_T_2646) node _issue_entry_T_2662 = or(_issue_entry_T_2661, _issue_entry_T_2647) node _issue_entry_T_2663 = or(_issue_entry_T_2662, _issue_entry_T_2648) node _issue_entry_T_2664 = or(_issue_entry_T_2663, _issue_entry_T_2649) node _issue_entry_T_2665 = or(_issue_entry_T_2664, _issue_entry_T_2650) node _issue_entry_T_2666 = or(_issue_entry_T_2665, _issue_entry_T_2651) node _issue_entry_T_2667 = or(_issue_entry_T_2666, _issue_entry_T_2652) node _issue_entry_T_2668 = or(_issue_entry_T_2667, _issue_entry_T_2653) node _issue_entry_T_2669 = or(_issue_entry_T_2668, _issue_entry_T_2654) wire _issue_entry_WIRE_174 : UInt<1> connect _issue_entry_WIRE_174, _issue_entry_T_2669 connect _issue_entry_WIRE_167[6], _issue_entry_WIRE_174 node _issue_entry_T_2670 = mux(issue_sel_0_1, entries_ex[0].bits.deps_ld[7], UInt<1>(0h0)) node _issue_entry_T_2671 = mux(issue_sel_1_1, entries_ex[1].bits.deps_ld[7], UInt<1>(0h0)) node _issue_entry_T_2672 = mux(issue_sel_2_1, entries_ex[2].bits.deps_ld[7], UInt<1>(0h0)) node _issue_entry_T_2673 = mux(issue_sel_3_1, entries_ex[3].bits.deps_ld[7], UInt<1>(0h0)) node _issue_entry_T_2674 = mux(issue_sel_4_1, entries_ex[4].bits.deps_ld[7], UInt<1>(0h0)) node _issue_entry_T_2675 = mux(issue_sel_5_1, entries_ex[5].bits.deps_ld[7], UInt<1>(0h0)) node _issue_entry_T_2676 = mux(issue_sel_6_1, entries_ex[6].bits.deps_ld[7], UInt<1>(0h0)) node _issue_entry_T_2677 = mux(issue_sel_7_1, entries_ex[7].bits.deps_ld[7], UInt<1>(0h0)) node _issue_entry_T_2678 = mux(issue_sel_8, entries_ex[8].bits.deps_ld[7], UInt<1>(0h0)) node _issue_entry_T_2679 = mux(issue_sel_9, entries_ex[9].bits.deps_ld[7], UInt<1>(0h0)) node _issue_entry_T_2680 = mux(issue_sel_10, entries_ex[10].bits.deps_ld[7], UInt<1>(0h0)) node _issue_entry_T_2681 = mux(issue_sel_11, entries_ex[11].bits.deps_ld[7], UInt<1>(0h0)) node _issue_entry_T_2682 = mux(issue_sel_12, entries_ex[12].bits.deps_ld[7], UInt<1>(0h0)) node _issue_entry_T_2683 = mux(issue_sel_13, entries_ex[13].bits.deps_ld[7], UInt<1>(0h0)) node _issue_entry_T_2684 = mux(issue_sel_14, entries_ex[14].bits.deps_ld[7], UInt<1>(0h0)) node _issue_entry_T_2685 = mux(issue_sel_15, entries_ex[15].bits.deps_ld[7], UInt<1>(0h0)) node _issue_entry_T_2686 = or(_issue_entry_T_2670, _issue_entry_T_2671) node _issue_entry_T_2687 = or(_issue_entry_T_2686, _issue_entry_T_2672) node _issue_entry_T_2688 = or(_issue_entry_T_2687, _issue_entry_T_2673) node _issue_entry_T_2689 = or(_issue_entry_T_2688, _issue_entry_T_2674) node _issue_entry_T_2690 = or(_issue_entry_T_2689, _issue_entry_T_2675) node _issue_entry_T_2691 = or(_issue_entry_T_2690, _issue_entry_T_2676) node _issue_entry_T_2692 = or(_issue_entry_T_2691, _issue_entry_T_2677) node _issue_entry_T_2693 = or(_issue_entry_T_2692, _issue_entry_T_2678) node _issue_entry_T_2694 = or(_issue_entry_T_2693, _issue_entry_T_2679) node _issue_entry_T_2695 = or(_issue_entry_T_2694, _issue_entry_T_2680) node _issue_entry_T_2696 = or(_issue_entry_T_2695, _issue_entry_T_2681) node _issue_entry_T_2697 = or(_issue_entry_T_2696, _issue_entry_T_2682) node _issue_entry_T_2698 = or(_issue_entry_T_2697, _issue_entry_T_2683) node _issue_entry_T_2699 = or(_issue_entry_T_2698, _issue_entry_T_2684) node _issue_entry_T_2700 = or(_issue_entry_T_2699, _issue_entry_T_2685) wire _issue_entry_WIRE_175 : UInt<1> connect _issue_entry_WIRE_175, _issue_entry_T_2700 connect _issue_entry_WIRE_167[7], _issue_entry_WIRE_175 connect _issue_entry_WIRE_143.deps_ld, _issue_entry_WIRE_167 wire _issue_entry_WIRE_176 : { cmd : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, rob_id : { valid : UInt<1>, bits : UInt<6>}, from_matmul_fsm : UInt<1>, from_conv_fsm : UInt<1>} node _issue_entry_T_2701 = mux(issue_sel_0_1, entries_ex[0].bits.cmd.from_conv_fsm, UInt<1>(0h0)) node _issue_entry_T_2702 = mux(issue_sel_1_1, entries_ex[1].bits.cmd.from_conv_fsm, UInt<1>(0h0)) node _issue_entry_T_2703 = mux(issue_sel_2_1, entries_ex[2].bits.cmd.from_conv_fsm, UInt<1>(0h0)) node _issue_entry_T_2704 = mux(issue_sel_3_1, entries_ex[3].bits.cmd.from_conv_fsm, UInt<1>(0h0)) node _issue_entry_T_2705 = mux(issue_sel_4_1, entries_ex[4].bits.cmd.from_conv_fsm, UInt<1>(0h0)) node _issue_entry_T_2706 = mux(issue_sel_5_1, entries_ex[5].bits.cmd.from_conv_fsm, UInt<1>(0h0)) node _issue_entry_T_2707 = mux(issue_sel_6_1, entries_ex[6].bits.cmd.from_conv_fsm, UInt<1>(0h0)) node _issue_entry_T_2708 = mux(issue_sel_7_1, entries_ex[7].bits.cmd.from_conv_fsm, UInt<1>(0h0)) node _issue_entry_T_2709 = mux(issue_sel_8, entries_ex[8].bits.cmd.from_conv_fsm, UInt<1>(0h0)) node _issue_entry_T_2710 = mux(issue_sel_9, entries_ex[9].bits.cmd.from_conv_fsm, UInt<1>(0h0)) node _issue_entry_T_2711 = mux(issue_sel_10, entries_ex[10].bits.cmd.from_conv_fsm, UInt<1>(0h0)) node _issue_entry_T_2712 = mux(issue_sel_11, entries_ex[11].bits.cmd.from_conv_fsm, UInt<1>(0h0)) node _issue_entry_T_2713 = mux(issue_sel_12, entries_ex[12].bits.cmd.from_conv_fsm, UInt<1>(0h0)) node _issue_entry_T_2714 = mux(issue_sel_13, entries_ex[13].bits.cmd.from_conv_fsm, UInt<1>(0h0)) node _issue_entry_T_2715 = mux(issue_sel_14, entries_ex[14].bits.cmd.from_conv_fsm, UInt<1>(0h0)) node _issue_entry_T_2716 = mux(issue_sel_15, entries_ex[15].bits.cmd.from_conv_fsm, UInt<1>(0h0)) node _issue_entry_T_2717 = or(_issue_entry_T_2701, _issue_entry_T_2702) node _issue_entry_T_2718 = or(_issue_entry_T_2717, _issue_entry_T_2703) node _issue_entry_T_2719 = or(_issue_entry_T_2718, _issue_entry_T_2704) node _issue_entry_T_2720 = or(_issue_entry_T_2719, _issue_entry_T_2705) node _issue_entry_T_2721 = or(_issue_entry_T_2720, _issue_entry_T_2706) node _issue_entry_T_2722 = or(_issue_entry_T_2721, _issue_entry_T_2707) node _issue_entry_T_2723 = or(_issue_entry_T_2722, _issue_entry_T_2708) node _issue_entry_T_2724 = or(_issue_entry_T_2723, _issue_entry_T_2709) node _issue_entry_T_2725 = or(_issue_entry_T_2724, _issue_entry_T_2710) node _issue_entry_T_2726 = or(_issue_entry_T_2725, _issue_entry_T_2711) node _issue_entry_T_2727 = or(_issue_entry_T_2726, _issue_entry_T_2712) node _issue_entry_T_2728 = or(_issue_entry_T_2727, _issue_entry_T_2713) node _issue_entry_T_2729 = or(_issue_entry_T_2728, _issue_entry_T_2714) node _issue_entry_T_2730 = or(_issue_entry_T_2729, _issue_entry_T_2715) node _issue_entry_T_2731 = or(_issue_entry_T_2730, _issue_entry_T_2716) wire _issue_entry_WIRE_177 : UInt<1> connect _issue_entry_WIRE_177, _issue_entry_T_2731 connect _issue_entry_WIRE_176.from_conv_fsm, _issue_entry_WIRE_177 node _issue_entry_T_2732 = mux(issue_sel_0_1, entries_ex[0].bits.cmd.from_matmul_fsm, UInt<1>(0h0)) node _issue_entry_T_2733 = mux(issue_sel_1_1, entries_ex[1].bits.cmd.from_matmul_fsm, UInt<1>(0h0)) node _issue_entry_T_2734 = mux(issue_sel_2_1, entries_ex[2].bits.cmd.from_matmul_fsm, UInt<1>(0h0)) node _issue_entry_T_2735 = mux(issue_sel_3_1, entries_ex[3].bits.cmd.from_matmul_fsm, UInt<1>(0h0)) node _issue_entry_T_2736 = mux(issue_sel_4_1, entries_ex[4].bits.cmd.from_matmul_fsm, UInt<1>(0h0)) node _issue_entry_T_2737 = mux(issue_sel_5_1, entries_ex[5].bits.cmd.from_matmul_fsm, UInt<1>(0h0)) node _issue_entry_T_2738 = mux(issue_sel_6_1, entries_ex[6].bits.cmd.from_matmul_fsm, UInt<1>(0h0)) node _issue_entry_T_2739 = mux(issue_sel_7_1, entries_ex[7].bits.cmd.from_matmul_fsm, UInt<1>(0h0)) node _issue_entry_T_2740 = mux(issue_sel_8, entries_ex[8].bits.cmd.from_matmul_fsm, UInt<1>(0h0)) node _issue_entry_T_2741 = mux(issue_sel_9, entries_ex[9].bits.cmd.from_matmul_fsm, UInt<1>(0h0)) node _issue_entry_T_2742 = mux(issue_sel_10, entries_ex[10].bits.cmd.from_matmul_fsm, UInt<1>(0h0)) node _issue_entry_T_2743 = mux(issue_sel_11, entries_ex[11].bits.cmd.from_matmul_fsm, UInt<1>(0h0)) node _issue_entry_T_2744 = mux(issue_sel_12, entries_ex[12].bits.cmd.from_matmul_fsm, UInt<1>(0h0)) node _issue_entry_T_2745 = mux(issue_sel_13, entries_ex[13].bits.cmd.from_matmul_fsm, UInt<1>(0h0)) node _issue_entry_T_2746 = mux(issue_sel_14, entries_ex[14].bits.cmd.from_matmul_fsm, UInt<1>(0h0)) node _issue_entry_T_2747 = mux(issue_sel_15, entries_ex[15].bits.cmd.from_matmul_fsm, UInt<1>(0h0)) node _issue_entry_T_2748 = or(_issue_entry_T_2732, _issue_entry_T_2733) node _issue_entry_T_2749 = or(_issue_entry_T_2748, _issue_entry_T_2734) node _issue_entry_T_2750 = or(_issue_entry_T_2749, _issue_entry_T_2735) node _issue_entry_T_2751 = or(_issue_entry_T_2750, _issue_entry_T_2736) node _issue_entry_T_2752 = or(_issue_entry_T_2751, _issue_entry_T_2737) node _issue_entry_T_2753 = or(_issue_entry_T_2752, _issue_entry_T_2738) node _issue_entry_T_2754 = or(_issue_entry_T_2753, _issue_entry_T_2739) node _issue_entry_T_2755 = or(_issue_entry_T_2754, _issue_entry_T_2740) node _issue_entry_T_2756 = or(_issue_entry_T_2755, _issue_entry_T_2741) node _issue_entry_T_2757 = or(_issue_entry_T_2756, _issue_entry_T_2742) node _issue_entry_T_2758 = or(_issue_entry_T_2757, _issue_entry_T_2743) node _issue_entry_T_2759 = or(_issue_entry_T_2758, _issue_entry_T_2744) node _issue_entry_T_2760 = or(_issue_entry_T_2759, _issue_entry_T_2745) node _issue_entry_T_2761 = or(_issue_entry_T_2760, _issue_entry_T_2746) node _issue_entry_T_2762 = or(_issue_entry_T_2761, _issue_entry_T_2747) wire _issue_entry_WIRE_178 : UInt<1> connect _issue_entry_WIRE_178, _issue_entry_T_2762 connect _issue_entry_WIRE_176.from_matmul_fsm, _issue_entry_WIRE_178 wire _issue_entry_WIRE_179 : { valid : UInt<1>, bits : UInt<6>} node _issue_entry_T_2763 = mux(issue_sel_0_1, entries_ex[0].bits.cmd.rob_id.bits, UInt<1>(0h0)) node _issue_entry_T_2764 = mux(issue_sel_1_1, entries_ex[1].bits.cmd.rob_id.bits, UInt<1>(0h0)) node _issue_entry_T_2765 = mux(issue_sel_2_1, entries_ex[2].bits.cmd.rob_id.bits, UInt<1>(0h0)) node _issue_entry_T_2766 = mux(issue_sel_3_1, entries_ex[3].bits.cmd.rob_id.bits, UInt<1>(0h0)) node _issue_entry_T_2767 = mux(issue_sel_4_1, entries_ex[4].bits.cmd.rob_id.bits, UInt<1>(0h0)) node _issue_entry_T_2768 = mux(issue_sel_5_1, entries_ex[5].bits.cmd.rob_id.bits, UInt<1>(0h0)) node _issue_entry_T_2769 = mux(issue_sel_6_1, entries_ex[6].bits.cmd.rob_id.bits, UInt<1>(0h0)) node _issue_entry_T_2770 = mux(issue_sel_7_1, entries_ex[7].bits.cmd.rob_id.bits, UInt<1>(0h0)) node _issue_entry_T_2771 = mux(issue_sel_8, entries_ex[8].bits.cmd.rob_id.bits, UInt<1>(0h0)) node _issue_entry_T_2772 = mux(issue_sel_9, entries_ex[9].bits.cmd.rob_id.bits, UInt<1>(0h0)) node _issue_entry_T_2773 = mux(issue_sel_10, entries_ex[10].bits.cmd.rob_id.bits, UInt<1>(0h0)) node _issue_entry_T_2774 = mux(issue_sel_11, entries_ex[11].bits.cmd.rob_id.bits, UInt<1>(0h0)) node _issue_entry_T_2775 = mux(issue_sel_12, entries_ex[12].bits.cmd.rob_id.bits, UInt<1>(0h0)) node _issue_entry_T_2776 = mux(issue_sel_13, entries_ex[13].bits.cmd.rob_id.bits, UInt<1>(0h0)) node _issue_entry_T_2777 = mux(issue_sel_14, entries_ex[14].bits.cmd.rob_id.bits, UInt<1>(0h0)) node _issue_entry_T_2778 = mux(issue_sel_15, entries_ex[15].bits.cmd.rob_id.bits, UInt<1>(0h0)) node _issue_entry_T_2779 = or(_issue_entry_T_2763, _issue_entry_T_2764) node _issue_entry_T_2780 = or(_issue_entry_T_2779, _issue_entry_T_2765) node _issue_entry_T_2781 = or(_issue_entry_T_2780, _issue_entry_T_2766) node _issue_entry_T_2782 = or(_issue_entry_T_2781, _issue_entry_T_2767) node _issue_entry_T_2783 = or(_issue_entry_T_2782, _issue_entry_T_2768) node _issue_entry_T_2784 = or(_issue_entry_T_2783, _issue_entry_T_2769) node _issue_entry_T_2785 = or(_issue_entry_T_2784, _issue_entry_T_2770) node _issue_entry_T_2786 = or(_issue_entry_T_2785, _issue_entry_T_2771) node _issue_entry_T_2787 = or(_issue_entry_T_2786, _issue_entry_T_2772) node _issue_entry_T_2788 = or(_issue_entry_T_2787, _issue_entry_T_2773) node _issue_entry_T_2789 = or(_issue_entry_T_2788, _issue_entry_T_2774) node _issue_entry_T_2790 = or(_issue_entry_T_2789, _issue_entry_T_2775) node _issue_entry_T_2791 = or(_issue_entry_T_2790, _issue_entry_T_2776) node _issue_entry_T_2792 = or(_issue_entry_T_2791, _issue_entry_T_2777) node _issue_entry_T_2793 = or(_issue_entry_T_2792, _issue_entry_T_2778) wire _issue_entry_WIRE_180 : UInt<6> connect _issue_entry_WIRE_180, _issue_entry_T_2793 connect _issue_entry_WIRE_179.bits, _issue_entry_WIRE_180 node _issue_entry_T_2794 = mux(issue_sel_0_1, entries_ex[0].bits.cmd.rob_id.valid, UInt<1>(0h0)) node _issue_entry_T_2795 = mux(issue_sel_1_1, entries_ex[1].bits.cmd.rob_id.valid, UInt<1>(0h0)) node _issue_entry_T_2796 = mux(issue_sel_2_1, entries_ex[2].bits.cmd.rob_id.valid, UInt<1>(0h0)) node _issue_entry_T_2797 = mux(issue_sel_3_1, entries_ex[3].bits.cmd.rob_id.valid, UInt<1>(0h0)) node _issue_entry_T_2798 = mux(issue_sel_4_1, entries_ex[4].bits.cmd.rob_id.valid, UInt<1>(0h0)) node _issue_entry_T_2799 = mux(issue_sel_5_1, entries_ex[5].bits.cmd.rob_id.valid, UInt<1>(0h0)) node _issue_entry_T_2800 = mux(issue_sel_6_1, entries_ex[6].bits.cmd.rob_id.valid, UInt<1>(0h0)) node _issue_entry_T_2801 = mux(issue_sel_7_1, entries_ex[7].bits.cmd.rob_id.valid, UInt<1>(0h0)) node _issue_entry_T_2802 = mux(issue_sel_8, entries_ex[8].bits.cmd.rob_id.valid, UInt<1>(0h0)) node _issue_entry_T_2803 = mux(issue_sel_9, entries_ex[9].bits.cmd.rob_id.valid, UInt<1>(0h0)) node _issue_entry_T_2804 = mux(issue_sel_10, entries_ex[10].bits.cmd.rob_id.valid, UInt<1>(0h0)) node _issue_entry_T_2805 = mux(issue_sel_11, entries_ex[11].bits.cmd.rob_id.valid, UInt<1>(0h0)) node _issue_entry_T_2806 = mux(issue_sel_12, entries_ex[12].bits.cmd.rob_id.valid, UInt<1>(0h0)) node _issue_entry_T_2807 = mux(issue_sel_13, entries_ex[13].bits.cmd.rob_id.valid, UInt<1>(0h0)) node _issue_entry_T_2808 = mux(issue_sel_14, entries_ex[14].bits.cmd.rob_id.valid, UInt<1>(0h0)) node _issue_entry_T_2809 = mux(issue_sel_15, entries_ex[15].bits.cmd.rob_id.valid, UInt<1>(0h0)) node _issue_entry_T_2810 = or(_issue_entry_T_2794, _issue_entry_T_2795) node _issue_entry_T_2811 = or(_issue_entry_T_2810, _issue_entry_T_2796) node _issue_entry_T_2812 = or(_issue_entry_T_2811, _issue_entry_T_2797) node _issue_entry_T_2813 = or(_issue_entry_T_2812, _issue_entry_T_2798) node _issue_entry_T_2814 = or(_issue_entry_T_2813, _issue_entry_T_2799) node _issue_entry_T_2815 = or(_issue_entry_T_2814, _issue_entry_T_2800) node _issue_entry_T_2816 = or(_issue_entry_T_2815, _issue_entry_T_2801) node _issue_entry_T_2817 = or(_issue_entry_T_2816, _issue_entry_T_2802) node _issue_entry_T_2818 = or(_issue_entry_T_2817, _issue_entry_T_2803) node _issue_entry_T_2819 = or(_issue_entry_T_2818, _issue_entry_T_2804) node _issue_entry_T_2820 = or(_issue_entry_T_2819, _issue_entry_T_2805) node _issue_entry_T_2821 = or(_issue_entry_T_2820, _issue_entry_T_2806) node _issue_entry_T_2822 = or(_issue_entry_T_2821, _issue_entry_T_2807) node _issue_entry_T_2823 = or(_issue_entry_T_2822, _issue_entry_T_2808) node _issue_entry_T_2824 = or(_issue_entry_T_2823, _issue_entry_T_2809) wire _issue_entry_WIRE_181 : UInt<1> connect _issue_entry_WIRE_181, _issue_entry_T_2824 connect _issue_entry_WIRE_179.valid, _issue_entry_WIRE_181 connect _issue_entry_WIRE_176.rob_id, _issue_entry_WIRE_179 wire _issue_entry_WIRE_182 : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}} wire _issue_entry_WIRE_183 : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} node _issue_entry_T_2825 = mux(issue_sel_0_1, entries_ex[0].bits.cmd.cmd.status.uie, UInt<1>(0h0)) node _issue_entry_T_2826 = mux(issue_sel_1_1, entries_ex[1].bits.cmd.cmd.status.uie, UInt<1>(0h0)) node _issue_entry_T_2827 = mux(issue_sel_2_1, entries_ex[2].bits.cmd.cmd.status.uie, UInt<1>(0h0)) node _issue_entry_T_2828 = mux(issue_sel_3_1, entries_ex[3].bits.cmd.cmd.status.uie, UInt<1>(0h0)) node _issue_entry_T_2829 = mux(issue_sel_4_1, entries_ex[4].bits.cmd.cmd.status.uie, UInt<1>(0h0)) node _issue_entry_T_2830 = mux(issue_sel_5_1, entries_ex[5].bits.cmd.cmd.status.uie, UInt<1>(0h0)) node _issue_entry_T_2831 = mux(issue_sel_6_1, entries_ex[6].bits.cmd.cmd.status.uie, UInt<1>(0h0)) node _issue_entry_T_2832 = mux(issue_sel_7_1, entries_ex[7].bits.cmd.cmd.status.uie, UInt<1>(0h0)) node _issue_entry_T_2833 = mux(issue_sel_8, entries_ex[8].bits.cmd.cmd.status.uie, UInt<1>(0h0)) node _issue_entry_T_2834 = mux(issue_sel_9, entries_ex[9].bits.cmd.cmd.status.uie, UInt<1>(0h0)) node _issue_entry_T_2835 = mux(issue_sel_10, entries_ex[10].bits.cmd.cmd.status.uie, UInt<1>(0h0)) node _issue_entry_T_2836 = mux(issue_sel_11, entries_ex[11].bits.cmd.cmd.status.uie, UInt<1>(0h0)) node _issue_entry_T_2837 = mux(issue_sel_12, entries_ex[12].bits.cmd.cmd.status.uie, UInt<1>(0h0)) node _issue_entry_T_2838 = mux(issue_sel_13, entries_ex[13].bits.cmd.cmd.status.uie, UInt<1>(0h0)) node _issue_entry_T_2839 = mux(issue_sel_14, entries_ex[14].bits.cmd.cmd.status.uie, UInt<1>(0h0)) node _issue_entry_T_2840 = mux(issue_sel_15, entries_ex[15].bits.cmd.cmd.status.uie, UInt<1>(0h0)) node _issue_entry_T_2841 = or(_issue_entry_T_2825, _issue_entry_T_2826) node _issue_entry_T_2842 = or(_issue_entry_T_2841, _issue_entry_T_2827) node _issue_entry_T_2843 = or(_issue_entry_T_2842, _issue_entry_T_2828) node _issue_entry_T_2844 = or(_issue_entry_T_2843, _issue_entry_T_2829) node _issue_entry_T_2845 = or(_issue_entry_T_2844, _issue_entry_T_2830) node _issue_entry_T_2846 = or(_issue_entry_T_2845, _issue_entry_T_2831) node _issue_entry_T_2847 = or(_issue_entry_T_2846, _issue_entry_T_2832) node _issue_entry_T_2848 = or(_issue_entry_T_2847, _issue_entry_T_2833) node _issue_entry_T_2849 = or(_issue_entry_T_2848, _issue_entry_T_2834) node _issue_entry_T_2850 = or(_issue_entry_T_2849, _issue_entry_T_2835) node _issue_entry_T_2851 = or(_issue_entry_T_2850, _issue_entry_T_2836) node _issue_entry_T_2852 = or(_issue_entry_T_2851, _issue_entry_T_2837) node _issue_entry_T_2853 = or(_issue_entry_T_2852, _issue_entry_T_2838) node _issue_entry_T_2854 = or(_issue_entry_T_2853, _issue_entry_T_2839) node _issue_entry_T_2855 = or(_issue_entry_T_2854, _issue_entry_T_2840) wire _issue_entry_WIRE_184 : UInt<1> connect _issue_entry_WIRE_184, _issue_entry_T_2855 connect _issue_entry_WIRE_183.uie, _issue_entry_WIRE_184 node _issue_entry_T_2856 = mux(issue_sel_0_1, entries_ex[0].bits.cmd.cmd.status.sie, UInt<1>(0h0)) node _issue_entry_T_2857 = mux(issue_sel_1_1, entries_ex[1].bits.cmd.cmd.status.sie, UInt<1>(0h0)) node _issue_entry_T_2858 = mux(issue_sel_2_1, entries_ex[2].bits.cmd.cmd.status.sie, UInt<1>(0h0)) node _issue_entry_T_2859 = mux(issue_sel_3_1, entries_ex[3].bits.cmd.cmd.status.sie, UInt<1>(0h0)) node _issue_entry_T_2860 = mux(issue_sel_4_1, entries_ex[4].bits.cmd.cmd.status.sie, UInt<1>(0h0)) node _issue_entry_T_2861 = mux(issue_sel_5_1, entries_ex[5].bits.cmd.cmd.status.sie, UInt<1>(0h0)) node _issue_entry_T_2862 = mux(issue_sel_6_1, entries_ex[6].bits.cmd.cmd.status.sie, UInt<1>(0h0)) node _issue_entry_T_2863 = mux(issue_sel_7_1, entries_ex[7].bits.cmd.cmd.status.sie, UInt<1>(0h0)) node _issue_entry_T_2864 = mux(issue_sel_8, entries_ex[8].bits.cmd.cmd.status.sie, UInt<1>(0h0)) node _issue_entry_T_2865 = mux(issue_sel_9, entries_ex[9].bits.cmd.cmd.status.sie, UInt<1>(0h0)) node _issue_entry_T_2866 = mux(issue_sel_10, entries_ex[10].bits.cmd.cmd.status.sie, UInt<1>(0h0)) node _issue_entry_T_2867 = mux(issue_sel_11, entries_ex[11].bits.cmd.cmd.status.sie, UInt<1>(0h0)) node _issue_entry_T_2868 = mux(issue_sel_12, entries_ex[12].bits.cmd.cmd.status.sie, UInt<1>(0h0)) node _issue_entry_T_2869 = mux(issue_sel_13, entries_ex[13].bits.cmd.cmd.status.sie, UInt<1>(0h0)) node _issue_entry_T_2870 = mux(issue_sel_14, entries_ex[14].bits.cmd.cmd.status.sie, UInt<1>(0h0)) node _issue_entry_T_2871 = mux(issue_sel_15, entries_ex[15].bits.cmd.cmd.status.sie, UInt<1>(0h0)) node _issue_entry_T_2872 = or(_issue_entry_T_2856, _issue_entry_T_2857) node _issue_entry_T_2873 = or(_issue_entry_T_2872, _issue_entry_T_2858) node _issue_entry_T_2874 = or(_issue_entry_T_2873, _issue_entry_T_2859) node _issue_entry_T_2875 = or(_issue_entry_T_2874, _issue_entry_T_2860) node _issue_entry_T_2876 = or(_issue_entry_T_2875, _issue_entry_T_2861) node _issue_entry_T_2877 = or(_issue_entry_T_2876, _issue_entry_T_2862) node _issue_entry_T_2878 = or(_issue_entry_T_2877, _issue_entry_T_2863) node _issue_entry_T_2879 = or(_issue_entry_T_2878, _issue_entry_T_2864) node _issue_entry_T_2880 = or(_issue_entry_T_2879, _issue_entry_T_2865) node _issue_entry_T_2881 = or(_issue_entry_T_2880, _issue_entry_T_2866) node _issue_entry_T_2882 = or(_issue_entry_T_2881, _issue_entry_T_2867) node _issue_entry_T_2883 = or(_issue_entry_T_2882, _issue_entry_T_2868) node _issue_entry_T_2884 = or(_issue_entry_T_2883, _issue_entry_T_2869) node _issue_entry_T_2885 = or(_issue_entry_T_2884, _issue_entry_T_2870) node _issue_entry_T_2886 = or(_issue_entry_T_2885, _issue_entry_T_2871) wire _issue_entry_WIRE_185 : UInt<1> connect _issue_entry_WIRE_185, _issue_entry_T_2886 connect _issue_entry_WIRE_183.sie, _issue_entry_WIRE_185 node _issue_entry_T_2887 = mux(issue_sel_0_1, entries_ex[0].bits.cmd.cmd.status.hie, UInt<1>(0h0)) node _issue_entry_T_2888 = mux(issue_sel_1_1, entries_ex[1].bits.cmd.cmd.status.hie, UInt<1>(0h0)) node _issue_entry_T_2889 = mux(issue_sel_2_1, entries_ex[2].bits.cmd.cmd.status.hie, UInt<1>(0h0)) node _issue_entry_T_2890 = mux(issue_sel_3_1, entries_ex[3].bits.cmd.cmd.status.hie, UInt<1>(0h0)) node _issue_entry_T_2891 = mux(issue_sel_4_1, entries_ex[4].bits.cmd.cmd.status.hie, UInt<1>(0h0)) node _issue_entry_T_2892 = mux(issue_sel_5_1, entries_ex[5].bits.cmd.cmd.status.hie, UInt<1>(0h0)) node _issue_entry_T_2893 = mux(issue_sel_6_1, entries_ex[6].bits.cmd.cmd.status.hie, UInt<1>(0h0)) node _issue_entry_T_2894 = mux(issue_sel_7_1, entries_ex[7].bits.cmd.cmd.status.hie, UInt<1>(0h0)) node _issue_entry_T_2895 = mux(issue_sel_8, entries_ex[8].bits.cmd.cmd.status.hie, UInt<1>(0h0)) node _issue_entry_T_2896 = mux(issue_sel_9, entries_ex[9].bits.cmd.cmd.status.hie, UInt<1>(0h0)) node _issue_entry_T_2897 = mux(issue_sel_10, entries_ex[10].bits.cmd.cmd.status.hie, UInt<1>(0h0)) node _issue_entry_T_2898 = mux(issue_sel_11, entries_ex[11].bits.cmd.cmd.status.hie, UInt<1>(0h0)) node _issue_entry_T_2899 = mux(issue_sel_12, entries_ex[12].bits.cmd.cmd.status.hie, UInt<1>(0h0)) node _issue_entry_T_2900 = mux(issue_sel_13, entries_ex[13].bits.cmd.cmd.status.hie, UInt<1>(0h0)) node _issue_entry_T_2901 = mux(issue_sel_14, entries_ex[14].bits.cmd.cmd.status.hie, UInt<1>(0h0)) node _issue_entry_T_2902 = mux(issue_sel_15, entries_ex[15].bits.cmd.cmd.status.hie, UInt<1>(0h0)) node _issue_entry_T_2903 = or(_issue_entry_T_2887, _issue_entry_T_2888) node _issue_entry_T_2904 = or(_issue_entry_T_2903, _issue_entry_T_2889) node _issue_entry_T_2905 = or(_issue_entry_T_2904, _issue_entry_T_2890) node _issue_entry_T_2906 = or(_issue_entry_T_2905, _issue_entry_T_2891) node _issue_entry_T_2907 = or(_issue_entry_T_2906, _issue_entry_T_2892) node _issue_entry_T_2908 = or(_issue_entry_T_2907, _issue_entry_T_2893) node _issue_entry_T_2909 = or(_issue_entry_T_2908, _issue_entry_T_2894) node _issue_entry_T_2910 = or(_issue_entry_T_2909, _issue_entry_T_2895) node _issue_entry_T_2911 = or(_issue_entry_T_2910, _issue_entry_T_2896) node _issue_entry_T_2912 = or(_issue_entry_T_2911, _issue_entry_T_2897) node _issue_entry_T_2913 = or(_issue_entry_T_2912, _issue_entry_T_2898) node _issue_entry_T_2914 = or(_issue_entry_T_2913, _issue_entry_T_2899) node _issue_entry_T_2915 = or(_issue_entry_T_2914, _issue_entry_T_2900) node _issue_entry_T_2916 = or(_issue_entry_T_2915, _issue_entry_T_2901) node _issue_entry_T_2917 = or(_issue_entry_T_2916, _issue_entry_T_2902) wire _issue_entry_WIRE_186 : UInt<1> connect _issue_entry_WIRE_186, _issue_entry_T_2917 connect _issue_entry_WIRE_183.hie, _issue_entry_WIRE_186 node _issue_entry_T_2918 = mux(issue_sel_0_1, entries_ex[0].bits.cmd.cmd.status.mie, UInt<1>(0h0)) node _issue_entry_T_2919 = mux(issue_sel_1_1, entries_ex[1].bits.cmd.cmd.status.mie, UInt<1>(0h0)) node _issue_entry_T_2920 = mux(issue_sel_2_1, entries_ex[2].bits.cmd.cmd.status.mie, UInt<1>(0h0)) node _issue_entry_T_2921 = mux(issue_sel_3_1, entries_ex[3].bits.cmd.cmd.status.mie, UInt<1>(0h0)) node _issue_entry_T_2922 = mux(issue_sel_4_1, entries_ex[4].bits.cmd.cmd.status.mie, UInt<1>(0h0)) node _issue_entry_T_2923 = mux(issue_sel_5_1, entries_ex[5].bits.cmd.cmd.status.mie, UInt<1>(0h0)) node _issue_entry_T_2924 = mux(issue_sel_6_1, entries_ex[6].bits.cmd.cmd.status.mie, UInt<1>(0h0)) node _issue_entry_T_2925 = mux(issue_sel_7_1, entries_ex[7].bits.cmd.cmd.status.mie, UInt<1>(0h0)) node _issue_entry_T_2926 = mux(issue_sel_8, entries_ex[8].bits.cmd.cmd.status.mie, UInt<1>(0h0)) node _issue_entry_T_2927 = mux(issue_sel_9, entries_ex[9].bits.cmd.cmd.status.mie, UInt<1>(0h0)) node _issue_entry_T_2928 = mux(issue_sel_10, entries_ex[10].bits.cmd.cmd.status.mie, UInt<1>(0h0)) node _issue_entry_T_2929 = mux(issue_sel_11, entries_ex[11].bits.cmd.cmd.status.mie, UInt<1>(0h0)) node _issue_entry_T_2930 = mux(issue_sel_12, entries_ex[12].bits.cmd.cmd.status.mie, UInt<1>(0h0)) node _issue_entry_T_2931 = mux(issue_sel_13, entries_ex[13].bits.cmd.cmd.status.mie, UInt<1>(0h0)) node _issue_entry_T_2932 = mux(issue_sel_14, entries_ex[14].bits.cmd.cmd.status.mie, UInt<1>(0h0)) node _issue_entry_T_2933 = mux(issue_sel_15, entries_ex[15].bits.cmd.cmd.status.mie, UInt<1>(0h0)) node _issue_entry_T_2934 = or(_issue_entry_T_2918, _issue_entry_T_2919) node _issue_entry_T_2935 = or(_issue_entry_T_2934, _issue_entry_T_2920) node _issue_entry_T_2936 = or(_issue_entry_T_2935, _issue_entry_T_2921) node _issue_entry_T_2937 = or(_issue_entry_T_2936, _issue_entry_T_2922) node _issue_entry_T_2938 = or(_issue_entry_T_2937, _issue_entry_T_2923) node _issue_entry_T_2939 = or(_issue_entry_T_2938, _issue_entry_T_2924) node _issue_entry_T_2940 = or(_issue_entry_T_2939, _issue_entry_T_2925) node _issue_entry_T_2941 = or(_issue_entry_T_2940, _issue_entry_T_2926) node _issue_entry_T_2942 = or(_issue_entry_T_2941, _issue_entry_T_2927) node _issue_entry_T_2943 = or(_issue_entry_T_2942, _issue_entry_T_2928) node _issue_entry_T_2944 = or(_issue_entry_T_2943, _issue_entry_T_2929) node _issue_entry_T_2945 = or(_issue_entry_T_2944, _issue_entry_T_2930) node _issue_entry_T_2946 = or(_issue_entry_T_2945, _issue_entry_T_2931) node _issue_entry_T_2947 = or(_issue_entry_T_2946, _issue_entry_T_2932) node _issue_entry_T_2948 = or(_issue_entry_T_2947, _issue_entry_T_2933) wire _issue_entry_WIRE_187 : UInt<1> connect _issue_entry_WIRE_187, _issue_entry_T_2948 connect _issue_entry_WIRE_183.mie, _issue_entry_WIRE_187 node _issue_entry_T_2949 = mux(issue_sel_0_1, entries_ex[0].bits.cmd.cmd.status.upie, UInt<1>(0h0)) node _issue_entry_T_2950 = mux(issue_sel_1_1, entries_ex[1].bits.cmd.cmd.status.upie, UInt<1>(0h0)) node _issue_entry_T_2951 = mux(issue_sel_2_1, entries_ex[2].bits.cmd.cmd.status.upie, UInt<1>(0h0)) node _issue_entry_T_2952 = mux(issue_sel_3_1, entries_ex[3].bits.cmd.cmd.status.upie, UInt<1>(0h0)) node _issue_entry_T_2953 = mux(issue_sel_4_1, entries_ex[4].bits.cmd.cmd.status.upie, UInt<1>(0h0)) node _issue_entry_T_2954 = mux(issue_sel_5_1, entries_ex[5].bits.cmd.cmd.status.upie, UInt<1>(0h0)) node _issue_entry_T_2955 = mux(issue_sel_6_1, entries_ex[6].bits.cmd.cmd.status.upie, UInt<1>(0h0)) node _issue_entry_T_2956 = mux(issue_sel_7_1, entries_ex[7].bits.cmd.cmd.status.upie, UInt<1>(0h0)) node _issue_entry_T_2957 = mux(issue_sel_8, entries_ex[8].bits.cmd.cmd.status.upie, UInt<1>(0h0)) node _issue_entry_T_2958 = mux(issue_sel_9, entries_ex[9].bits.cmd.cmd.status.upie, UInt<1>(0h0)) node _issue_entry_T_2959 = mux(issue_sel_10, entries_ex[10].bits.cmd.cmd.status.upie, UInt<1>(0h0)) node _issue_entry_T_2960 = mux(issue_sel_11, entries_ex[11].bits.cmd.cmd.status.upie, UInt<1>(0h0)) node _issue_entry_T_2961 = mux(issue_sel_12, entries_ex[12].bits.cmd.cmd.status.upie, UInt<1>(0h0)) node _issue_entry_T_2962 = mux(issue_sel_13, entries_ex[13].bits.cmd.cmd.status.upie, UInt<1>(0h0)) node _issue_entry_T_2963 = mux(issue_sel_14, entries_ex[14].bits.cmd.cmd.status.upie, UInt<1>(0h0)) node _issue_entry_T_2964 = mux(issue_sel_15, entries_ex[15].bits.cmd.cmd.status.upie, UInt<1>(0h0)) node _issue_entry_T_2965 = or(_issue_entry_T_2949, _issue_entry_T_2950) node _issue_entry_T_2966 = or(_issue_entry_T_2965, _issue_entry_T_2951) node _issue_entry_T_2967 = or(_issue_entry_T_2966, _issue_entry_T_2952) node _issue_entry_T_2968 = or(_issue_entry_T_2967, _issue_entry_T_2953) node _issue_entry_T_2969 = or(_issue_entry_T_2968, _issue_entry_T_2954) node _issue_entry_T_2970 = or(_issue_entry_T_2969, _issue_entry_T_2955) node _issue_entry_T_2971 = or(_issue_entry_T_2970, _issue_entry_T_2956) node _issue_entry_T_2972 = or(_issue_entry_T_2971, _issue_entry_T_2957) node _issue_entry_T_2973 = or(_issue_entry_T_2972, _issue_entry_T_2958) node _issue_entry_T_2974 = or(_issue_entry_T_2973, _issue_entry_T_2959) node _issue_entry_T_2975 = or(_issue_entry_T_2974, _issue_entry_T_2960) node _issue_entry_T_2976 = or(_issue_entry_T_2975, _issue_entry_T_2961) node _issue_entry_T_2977 = or(_issue_entry_T_2976, _issue_entry_T_2962) node _issue_entry_T_2978 = or(_issue_entry_T_2977, _issue_entry_T_2963) node _issue_entry_T_2979 = or(_issue_entry_T_2978, _issue_entry_T_2964) wire _issue_entry_WIRE_188 : UInt<1> connect _issue_entry_WIRE_188, _issue_entry_T_2979 connect _issue_entry_WIRE_183.upie, _issue_entry_WIRE_188 node _issue_entry_T_2980 = mux(issue_sel_0_1, entries_ex[0].bits.cmd.cmd.status.spie, UInt<1>(0h0)) node _issue_entry_T_2981 = mux(issue_sel_1_1, entries_ex[1].bits.cmd.cmd.status.spie, UInt<1>(0h0)) node _issue_entry_T_2982 = mux(issue_sel_2_1, entries_ex[2].bits.cmd.cmd.status.spie, UInt<1>(0h0)) node _issue_entry_T_2983 = mux(issue_sel_3_1, entries_ex[3].bits.cmd.cmd.status.spie, UInt<1>(0h0)) node _issue_entry_T_2984 = mux(issue_sel_4_1, entries_ex[4].bits.cmd.cmd.status.spie, UInt<1>(0h0)) node _issue_entry_T_2985 = mux(issue_sel_5_1, entries_ex[5].bits.cmd.cmd.status.spie, UInt<1>(0h0)) node _issue_entry_T_2986 = mux(issue_sel_6_1, entries_ex[6].bits.cmd.cmd.status.spie, UInt<1>(0h0)) node _issue_entry_T_2987 = mux(issue_sel_7_1, entries_ex[7].bits.cmd.cmd.status.spie, UInt<1>(0h0)) node _issue_entry_T_2988 = mux(issue_sel_8, entries_ex[8].bits.cmd.cmd.status.spie, UInt<1>(0h0)) node _issue_entry_T_2989 = mux(issue_sel_9, entries_ex[9].bits.cmd.cmd.status.spie, UInt<1>(0h0)) node _issue_entry_T_2990 = mux(issue_sel_10, entries_ex[10].bits.cmd.cmd.status.spie, UInt<1>(0h0)) node _issue_entry_T_2991 = mux(issue_sel_11, entries_ex[11].bits.cmd.cmd.status.spie, UInt<1>(0h0)) node _issue_entry_T_2992 = mux(issue_sel_12, entries_ex[12].bits.cmd.cmd.status.spie, UInt<1>(0h0)) node _issue_entry_T_2993 = mux(issue_sel_13, entries_ex[13].bits.cmd.cmd.status.spie, UInt<1>(0h0)) node _issue_entry_T_2994 = mux(issue_sel_14, entries_ex[14].bits.cmd.cmd.status.spie, UInt<1>(0h0)) node _issue_entry_T_2995 = mux(issue_sel_15, entries_ex[15].bits.cmd.cmd.status.spie, UInt<1>(0h0)) node _issue_entry_T_2996 = or(_issue_entry_T_2980, _issue_entry_T_2981) node _issue_entry_T_2997 = or(_issue_entry_T_2996, _issue_entry_T_2982) node _issue_entry_T_2998 = or(_issue_entry_T_2997, _issue_entry_T_2983) node _issue_entry_T_2999 = or(_issue_entry_T_2998, _issue_entry_T_2984) node _issue_entry_T_3000 = or(_issue_entry_T_2999, _issue_entry_T_2985) node _issue_entry_T_3001 = or(_issue_entry_T_3000, _issue_entry_T_2986) node _issue_entry_T_3002 = or(_issue_entry_T_3001, _issue_entry_T_2987) node _issue_entry_T_3003 = or(_issue_entry_T_3002, _issue_entry_T_2988) node _issue_entry_T_3004 = or(_issue_entry_T_3003, _issue_entry_T_2989) node _issue_entry_T_3005 = or(_issue_entry_T_3004, _issue_entry_T_2990) node _issue_entry_T_3006 = or(_issue_entry_T_3005, _issue_entry_T_2991) node _issue_entry_T_3007 = or(_issue_entry_T_3006, _issue_entry_T_2992) node _issue_entry_T_3008 = or(_issue_entry_T_3007, _issue_entry_T_2993) node _issue_entry_T_3009 = or(_issue_entry_T_3008, _issue_entry_T_2994) node _issue_entry_T_3010 = or(_issue_entry_T_3009, _issue_entry_T_2995) wire _issue_entry_WIRE_189 : UInt<1> connect _issue_entry_WIRE_189, _issue_entry_T_3010 connect _issue_entry_WIRE_183.spie, _issue_entry_WIRE_189 node _issue_entry_T_3011 = mux(issue_sel_0_1, entries_ex[0].bits.cmd.cmd.status.ube, UInt<1>(0h0)) node _issue_entry_T_3012 = mux(issue_sel_1_1, entries_ex[1].bits.cmd.cmd.status.ube, UInt<1>(0h0)) node _issue_entry_T_3013 = mux(issue_sel_2_1, entries_ex[2].bits.cmd.cmd.status.ube, UInt<1>(0h0)) node _issue_entry_T_3014 = mux(issue_sel_3_1, entries_ex[3].bits.cmd.cmd.status.ube, UInt<1>(0h0)) node _issue_entry_T_3015 = mux(issue_sel_4_1, entries_ex[4].bits.cmd.cmd.status.ube, UInt<1>(0h0)) node _issue_entry_T_3016 = mux(issue_sel_5_1, entries_ex[5].bits.cmd.cmd.status.ube, UInt<1>(0h0)) node _issue_entry_T_3017 = mux(issue_sel_6_1, entries_ex[6].bits.cmd.cmd.status.ube, UInt<1>(0h0)) node _issue_entry_T_3018 = mux(issue_sel_7_1, entries_ex[7].bits.cmd.cmd.status.ube, UInt<1>(0h0)) node _issue_entry_T_3019 = mux(issue_sel_8, entries_ex[8].bits.cmd.cmd.status.ube, UInt<1>(0h0)) node _issue_entry_T_3020 = mux(issue_sel_9, entries_ex[9].bits.cmd.cmd.status.ube, UInt<1>(0h0)) node _issue_entry_T_3021 = mux(issue_sel_10, entries_ex[10].bits.cmd.cmd.status.ube, UInt<1>(0h0)) node _issue_entry_T_3022 = mux(issue_sel_11, entries_ex[11].bits.cmd.cmd.status.ube, UInt<1>(0h0)) node _issue_entry_T_3023 = mux(issue_sel_12, entries_ex[12].bits.cmd.cmd.status.ube, UInt<1>(0h0)) node _issue_entry_T_3024 = mux(issue_sel_13, entries_ex[13].bits.cmd.cmd.status.ube, UInt<1>(0h0)) node _issue_entry_T_3025 = mux(issue_sel_14, entries_ex[14].bits.cmd.cmd.status.ube, UInt<1>(0h0)) node _issue_entry_T_3026 = mux(issue_sel_15, entries_ex[15].bits.cmd.cmd.status.ube, UInt<1>(0h0)) node _issue_entry_T_3027 = or(_issue_entry_T_3011, _issue_entry_T_3012) node _issue_entry_T_3028 = or(_issue_entry_T_3027, _issue_entry_T_3013) node _issue_entry_T_3029 = or(_issue_entry_T_3028, _issue_entry_T_3014) node _issue_entry_T_3030 = or(_issue_entry_T_3029, _issue_entry_T_3015) node _issue_entry_T_3031 = or(_issue_entry_T_3030, _issue_entry_T_3016) node _issue_entry_T_3032 = or(_issue_entry_T_3031, _issue_entry_T_3017) node _issue_entry_T_3033 = or(_issue_entry_T_3032, _issue_entry_T_3018) node _issue_entry_T_3034 = or(_issue_entry_T_3033, _issue_entry_T_3019) node _issue_entry_T_3035 = or(_issue_entry_T_3034, _issue_entry_T_3020) node _issue_entry_T_3036 = or(_issue_entry_T_3035, _issue_entry_T_3021) node _issue_entry_T_3037 = or(_issue_entry_T_3036, _issue_entry_T_3022) node _issue_entry_T_3038 = or(_issue_entry_T_3037, _issue_entry_T_3023) node _issue_entry_T_3039 = or(_issue_entry_T_3038, _issue_entry_T_3024) node _issue_entry_T_3040 = or(_issue_entry_T_3039, _issue_entry_T_3025) node _issue_entry_T_3041 = or(_issue_entry_T_3040, _issue_entry_T_3026) wire _issue_entry_WIRE_190 : UInt<1> connect _issue_entry_WIRE_190, _issue_entry_T_3041 connect _issue_entry_WIRE_183.ube, _issue_entry_WIRE_190 node _issue_entry_T_3042 = mux(issue_sel_0_1, entries_ex[0].bits.cmd.cmd.status.mpie, UInt<1>(0h0)) node _issue_entry_T_3043 = mux(issue_sel_1_1, entries_ex[1].bits.cmd.cmd.status.mpie, UInt<1>(0h0)) node _issue_entry_T_3044 = mux(issue_sel_2_1, entries_ex[2].bits.cmd.cmd.status.mpie, UInt<1>(0h0)) node _issue_entry_T_3045 = mux(issue_sel_3_1, entries_ex[3].bits.cmd.cmd.status.mpie, UInt<1>(0h0)) node _issue_entry_T_3046 = mux(issue_sel_4_1, entries_ex[4].bits.cmd.cmd.status.mpie, UInt<1>(0h0)) node _issue_entry_T_3047 = mux(issue_sel_5_1, entries_ex[5].bits.cmd.cmd.status.mpie, UInt<1>(0h0)) node _issue_entry_T_3048 = mux(issue_sel_6_1, entries_ex[6].bits.cmd.cmd.status.mpie, UInt<1>(0h0)) node _issue_entry_T_3049 = mux(issue_sel_7_1, entries_ex[7].bits.cmd.cmd.status.mpie, UInt<1>(0h0)) node _issue_entry_T_3050 = mux(issue_sel_8, entries_ex[8].bits.cmd.cmd.status.mpie, UInt<1>(0h0)) node _issue_entry_T_3051 = mux(issue_sel_9, entries_ex[9].bits.cmd.cmd.status.mpie, UInt<1>(0h0)) node _issue_entry_T_3052 = mux(issue_sel_10, entries_ex[10].bits.cmd.cmd.status.mpie, UInt<1>(0h0)) node _issue_entry_T_3053 = mux(issue_sel_11, entries_ex[11].bits.cmd.cmd.status.mpie, UInt<1>(0h0)) node _issue_entry_T_3054 = mux(issue_sel_12, entries_ex[12].bits.cmd.cmd.status.mpie, UInt<1>(0h0)) node _issue_entry_T_3055 = mux(issue_sel_13, entries_ex[13].bits.cmd.cmd.status.mpie, UInt<1>(0h0)) node _issue_entry_T_3056 = mux(issue_sel_14, entries_ex[14].bits.cmd.cmd.status.mpie, UInt<1>(0h0)) node _issue_entry_T_3057 = mux(issue_sel_15, entries_ex[15].bits.cmd.cmd.status.mpie, UInt<1>(0h0)) node _issue_entry_T_3058 = or(_issue_entry_T_3042, _issue_entry_T_3043) node _issue_entry_T_3059 = or(_issue_entry_T_3058, _issue_entry_T_3044) node _issue_entry_T_3060 = or(_issue_entry_T_3059, _issue_entry_T_3045) node _issue_entry_T_3061 = or(_issue_entry_T_3060, _issue_entry_T_3046) node _issue_entry_T_3062 = or(_issue_entry_T_3061, _issue_entry_T_3047) node _issue_entry_T_3063 = or(_issue_entry_T_3062, _issue_entry_T_3048) node _issue_entry_T_3064 = or(_issue_entry_T_3063, _issue_entry_T_3049) node _issue_entry_T_3065 = or(_issue_entry_T_3064, _issue_entry_T_3050) node _issue_entry_T_3066 = or(_issue_entry_T_3065, _issue_entry_T_3051) node _issue_entry_T_3067 = or(_issue_entry_T_3066, _issue_entry_T_3052) node _issue_entry_T_3068 = or(_issue_entry_T_3067, _issue_entry_T_3053) node _issue_entry_T_3069 = or(_issue_entry_T_3068, _issue_entry_T_3054) node _issue_entry_T_3070 = or(_issue_entry_T_3069, _issue_entry_T_3055) node _issue_entry_T_3071 = or(_issue_entry_T_3070, _issue_entry_T_3056) node _issue_entry_T_3072 = or(_issue_entry_T_3071, _issue_entry_T_3057) wire _issue_entry_WIRE_191 : UInt<1> connect _issue_entry_WIRE_191, _issue_entry_T_3072 connect _issue_entry_WIRE_183.mpie, _issue_entry_WIRE_191 node _issue_entry_T_3073 = mux(issue_sel_0_1, entries_ex[0].bits.cmd.cmd.status.spp, UInt<1>(0h0)) node _issue_entry_T_3074 = mux(issue_sel_1_1, entries_ex[1].bits.cmd.cmd.status.spp, UInt<1>(0h0)) node _issue_entry_T_3075 = mux(issue_sel_2_1, entries_ex[2].bits.cmd.cmd.status.spp, UInt<1>(0h0)) node _issue_entry_T_3076 = mux(issue_sel_3_1, entries_ex[3].bits.cmd.cmd.status.spp, UInt<1>(0h0)) node _issue_entry_T_3077 = mux(issue_sel_4_1, entries_ex[4].bits.cmd.cmd.status.spp, UInt<1>(0h0)) node _issue_entry_T_3078 = mux(issue_sel_5_1, entries_ex[5].bits.cmd.cmd.status.spp, UInt<1>(0h0)) node _issue_entry_T_3079 = mux(issue_sel_6_1, entries_ex[6].bits.cmd.cmd.status.spp, UInt<1>(0h0)) node _issue_entry_T_3080 = mux(issue_sel_7_1, entries_ex[7].bits.cmd.cmd.status.spp, UInt<1>(0h0)) node _issue_entry_T_3081 = mux(issue_sel_8, entries_ex[8].bits.cmd.cmd.status.spp, UInt<1>(0h0)) node _issue_entry_T_3082 = mux(issue_sel_9, entries_ex[9].bits.cmd.cmd.status.spp, UInt<1>(0h0)) node _issue_entry_T_3083 = mux(issue_sel_10, entries_ex[10].bits.cmd.cmd.status.spp, UInt<1>(0h0)) node _issue_entry_T_3084 = mux(issue_sel_11, entries_ex[11].bits.cmd.cmd.status.spp, UInt<1>(0h0)) node _issue_entry_T_3085 = mux(issue_sel_12, entries_ex[12].bits.cmd.cmd.status.spp, UInt<1>(0h0)) node _issue_entry_T_3086 = mux(issue_sel_13, entries_ex[13].bits.cmd.cmd.status.spp, UInt<1>(0h0)) node _issue_entry_T_3087 = mux(issue_sel_14, entries_ex[14].bits.cmd.cmd.status.spp, UInt<1>(0h0)) node _issue_entry_T_3088 = mux(issue_sel_15, entries_ex[15].bits.cmd.cmd.status.spp, UInt<1>(0h0)) node _issue_entry_T_3089 = or(_issue_entry_T_3073, _issue_entry_T_3074) node _issue_entry_T_3090 = or(_issue_entry_T_3089, _issue_entry_T_3075) node _issue_entry_T_3091 = or(_issue_entry_T_3090, _issue_entry_T_3076) node _issue_entry_T_3092 = or(_issue_entry_T_3091, _issue_entry_T_3077) node _issue_entry_T_3093 = or(_issue_entry_T_3092, _issue_entry_T_3078) node _issue_entry_T_3094 = or(_issue_entry_T_3093, _issue_entry_T_3079) node _issue_entry_T_3095 = or(_issue_entry_T_3094, _issue_entry_T_3080) node _issue_entry_T_3096 = or(_issue_entry_T_3095, _issue_entry_T_3081) node _issue_entry_T_3097 = or(_issue_entry_T_3096, _issue_entry_T_3082) node _issue_entry_T_3098 = or(_issue_entry_T_3097, _issue_entry_T_3083) node _issue_entry_T_3099 = or(_issue_entry_T_3098, _issue_entry_T_3084) node _issue_entry_T_3100 = or(_issue_entry_T_3099, _issue_entry_T_3085) node _issue_entry_T_3101 = or(_issue_entry_T_3100, _issue_entry_T_3086) node _issue_entry_T_3102 = or(_issue_entry_T_3101, _issue_entry_T_3087) node _issue_entry_T_3103 = or(_issue_entry_T_3102, _issue_entry_T_3088) wire _issue_entry_WIRE_192 : UInt<1> connect _issue_entry_WIRE_192, _issue_entry_T_3103 connect _issue_entry_WIRE_183.spp, _issue_entry_WIRE_192 node _issue_entry_T_3104 = mux(issue_sel_0_1, entries_ex[0].bits.cmd.cmd.status.vs, UInt<1>(0h0)) node _issue_entry_T_3105 = mux(issue_sel_1_1, entries_ex[1].bits.cmd.cmd.status.vs, UInt<1>(0h0)) node _issue_entry_T_3106 = mux(issue_sel_2_1, entries_ex[2].bits.cmd.cmd.status.vs, UInt<1>(0h0)) node _issue_entry_T_3107 = mux(issue_sel_3_1, entries_ex[3].bits.cmd.cmd.status.vs, UInt<1>(0h0)) node _issue_entry_T_3108 = mux(issue_sel_4_1, entries_ex[4].bits.cmd.cmd.status.vs, UInt<1>(0h0)) node _issue_entry_T_3109 = mux(issue_sel_5_1, entries_ex[5].bits.cmd.cmd.status.vs, UInt<1>(0h0)) node _issue_entry_T_3110 = mux(issue_sel_6_1, entries_ex[6].bits.cmd.cmd.status.vs, UInt<1>(0h0)) node _issue_entry_T_3111 = mux(issue_sel_7_1, entries_ex[7].bits.cmd.cmd.status.vs, UInt<1>(0h0)) node _issue_entry_T_3112 = mux(issue_sel_8, entries_ex[8].bits.cmd.cmd.status.vs, UInt<1>(0h0)) node _issue_entry_T_3113 = mux(issue_sel_9, entries_ex[9].bits.cmd.cmd.status.vs, UInt<1>(0h0)) node _issue_entry_T_3114 = mux(issue_sel_10, entries_ex[10].bits.cmd.cmd.status.vs, UInt<1>(0h0)) node _issue_entry_T_3115 = mux(issue_sel_11, entries_ex[11].bits.cmd.cmd.status.vs, UInt<1>(0h0)) node _issue_entry_T_3116 = mux(issue_sel_12, entries_ex[12].bits.cmd.cmd.status.vs, UInt<1>(0h0)) node _issue_entry_T_3117 = mux(issue_sel_13, entries_ex[13].bits.cmd.cmd.status.vs, UInt<1>(0h0)) node _issue_entry_T_3118 = mux(issue_sel_14, entries_ex[14].bits.cmd.cmd.status.vs, UInt<1>(0h0)) node _issue_entry_T_3119 = mux(issue_sel_15, entries_ex[15].bits.cmd.cmd.status.vs, UInt<1>(0h0)) node _issue_entry_T_3120 = or(_issue_entry_T_3104, _issue_entry_T_3105) node _issue_entry_T_3121 = or(_issue_entry_T_3120, _issue_entry_T_3106) node _issue_entry_T_3122 = or(_issue_entry_T_3121, _issue_entry_T_3107) node _issue_entry_T_3123 = or(_issue_entry_T_3122, _issue_entry_T_3108) node _issue_entry_T_3124 = or(_issue_entry_T_3123, _issue_entry_T_3109) node _issue_entry_T_3125 = or(_issue_entry_T_3124, _issue_entry_T_3110) node _issue_entry_T_3126 = or(_issue_entry_T_3125, _issue_entry_T_3111) node _issue_entry_T_3127 = or(_issue_entry_T_3126, _issue_entry_T_3112) node _issue_entry_T_3128 = or(_issue_entry_T_3127, _issue_entry_T_3113) node _issue_entry_T_3129 = or(_issue_entry_T_3128, _issue_entry_T_3114) node _issue_entry_T_3130 = or(_issue_entry_T_3129, _issue_entry_T_3115) node _issue_entry_T_3131 = or(_issue_entry_T_3130, _issue_entry_T_3116) node _issue_entry_T_3132 = or(_issue_entry_T_3131, _issue_entry_T_3117) node _issue_entry_T_3133 = or(_issue_entry_T_3132, _issue_entry_T_3118) node _issue_entry_T_3134 = or(_issue_entry_T_3133, _issue_entry_T_3119) wire _issue_entry_WIRE_193 : UInt<2> connect _issue_entry_WIRE_193, _issue_entry_T_3134 connect _issue_entry_WIRE_183.vs, _issue_entry_WIRE_193 node _issue_entry_T_3135 = mux(issue_sel_0_1, entries_ex[0].bits.cmd.cmd.status.mpp, UInt<1>(0h0)) node _issue_entry_T_3136 = mux(issue_sel_1_1, entries_ex[1].bits.cmd.cmd.status.mpp, UInt<1>(0h0)) node _issue_entry_T_3137 = mux(issue_sel_2_1, entries_ex[2].bits.cmd.cmd.status.mpp, UInt<1>(0h0)) node _issue_entry_T_3138 = mux(issue_sel_3_1, entries_ex[3].bits.cmd.cmd.status.mpp, UInt<1>(0h0)) node _issue_entry_T_3139 = mux(issue_sel_4_1, entries_ex[4].bits.cmd.cmd.status.mpp, UInt<1>(0h0)) node _issue_entry_T_3140 = mux(issue_sel_5_1, entries_ex[5].bits.cmd.cmd.status.mpp, UInt<1>(0h0)) node _issue_entry_T_3141 = mux(issue_sel_6_1, entries_ex[6].bits.cmd.cmd.status.mpp, UInt<1>(0h0)) node _issue_entry_T_3142 = mux(issue_sel_7_1, entries_ex[7].bits.cmd.cmd.status.mpp, UInt<1>(0h0)) node _issue_entry_T_3143 = mux(issue_sel_8, entries_ex[8].bits.cmd.cmd.status.mpp, UInt<1>(0h0)) node _issue_entry_T_3144 = mux(issue_sel_9, entries_ex[9].bits.cmd.cmd.status.mpp, UInt<1>(0h0)) node _issue_entry_T_3145 = mux(issue_sel_10, entries_ex[10].bits.cmd.cmd.status.mpp, UInt<1>(0h0)) node _issue_entry_T_3146 = mux(issue_sel_11, entries_ex[11].bits.cmd.cmd.status.mpp, UInt<1>(0h0)) node _issue_entry_T_3147 = mux(issue_sel_12, entries_ex[12].bits.cmd.cmd.status.mpp, UInt<1>(0h0)) node _issue_entry_T_3148 = mux(issue_sel_13, entries_ex[13].bits.cmd.cmd.status.mpp, UInt<1>(0h0)) node _issue_entry_T_3149 = mux(issue_sel_14, entries_ex[14].bits.cmd.cmd.status.mpp, UInt<1>(0h0)) node _issue_entry_T_3150 = mux(issue_sel_15, entries_ex[15].bits.cmd.cmd.status.mpp, UInt<1>(0h0)) node _issue_entry_T_3151 = or(_issue_entry_T_3135, _issue_entry_T_3136) node _issue_entry_T_3152 = or(_issue_entry_T_3151, _issue_entry_T_3137) node _issue_entry_T_3153 = or(_issue_entry_T_3152, _issue_entry_T_3138) node _issue_entry_T_3154 = or(_issue_entry_T_3153, _issue_entry_T_3139) node _issue_entry_T_3155 = or(_issue_entry_T_3154, _issue_entry_T_3140) node _issue_entry_T_3156 = or(_issue_entry_T_3155, _issue_entry_T_3141) node _issue_entry_T_3157 = or(_issue_entry_T_3156, _issue_entry_T_3142) node _issue_entry_T_3158 = or(_issue_entry_T_3157, _issue_entry_T_3143) node _issue_entry_T_3159 = or(_issue_entry_T_3158, _issue_entry_T_3144) node _issue_entry_T_3160 = or(_issue_entry_T_3159, _issue_entry_T_3145) node _issue_entry_T_3161 = or(_issue_entry_T_3160, _issue_entry_T_3146) node _issue_entry_T_3162 = or(_issue_entry_T_3161, _issue_entry_T_3147) node _issue_entry_T_3163 = or(_issue_entry_T_3162, _issue_entry_T_3148) node _issue_entry_T_3164 = or(_issue_entry_T_3163, _issue_entry_T_3149) node _issue_entry_T_3165 = or(_issue_entry_T_3164, _issue_entry_T_3150) wire _issue_entry_WIRE_194 : UInt<2> connect _issue_entry_WIRE_194, _issue_entry_T_3165 connect _issue_entry_WIRE_183.mpp, _issue_entry_WIRE_194 node _issue_entry_T_3166 = mux(issue_sel_0_1, entries_ex[0].bits.cmd.cmd.status.fs, UInt<1>(0h0)) node _issue_entry_T_3167 = mux(issue_sel_1_1, entries_ex[1].bits.cmd.cmd.status.fs, UInt<1>(0h0)) node _issue_entry_T_3168 = mux(issue_sel_2_1, entries_ex[2].bits.cmd.cmd.status.fs, UInt<1>(0h0)) node _issue_entry_T_3169 = mux(issue_sel_3_1, entries_ex[3].bits.cmd.cmd.status.fs, UInt<1>(0h0)) node _issue_entry_T_3170 = mux(issue_sel_4_1, entries_ex[4].bits.cmd.cmd.status.fs, UInt<1>(0h0)) node _issue_entry_T_3171 = mux(issue_sel_5_1, entries_ex[5].bits.cmd.cmd.status.fs, UInt<1>(0h0)) node _issue_entry_T_3172 = mux(issue_sel_6_1, entries_ex[6].bits.cmd.cmd.status.fs, UInt<1>(0h0)) node _issue_entry_T_3173 = mux(issue_sel_7_1, entries_ex[7].bits.cmd.cmd.status.fs, UInt<1>(0h0)) node _issue_entry_T_3174 = mux(issue_sel_8, entries_ex[8].bits.cmd.cmd.status.fs, UInt<1>(0h0)) node _issue_entry_T_3175 = mux(issue_sel_9, entries_ex[9].bits.cmd.cmd.status.fs, UInt<1>(0h0)) node _issue_entry_T_3176 = mux(issue_sel_10, entries_ex[10].bits.cmd.cmd.status.fs, UInt<1>(0h0)) node _issue_entry_T_3177 = mux(issue_sel_11, entries_ex[11].bits.cmd.cmd.status.fs, UInt<1>(0h0)) node _issue_entry_T_3178 = mux(issue_sel_12, entries_ex[12].bits.cmd.cmd.status.fs, UInt<1>(0h0)) node _issue_entry_T_3179 = mux(issue_sel_13, entries_ex[13].bits.cmd.cmd.status.fs, UInt<1>(0h0)) node _issue_entry_T_3180 = mux(issue_sel_14, entries_ex[14].bits.cmd.cmd.status.fs, UInt<1>(0h0)) node _issue_entry_T_3181 = mux(issue_sel_15, entries_ex[15].bits.cmd.cmd.status.fs, UInt<1>(0h0)) node _issue_entry_T_3182 = or(_issue_entry_T_3166, _issue_entry_T_3167) node _issue_entry_T_3183 = or(_issue_entry_T_3182, _issue_entry_T_3168) node _issue_entry_T_3184 = or(_issue_entry_T_3183, _issue_entry_T_3169) node _issue_entry_T_3185 = or(_issue_entry_T_3184, _issue_entry_T_3170) node _issue_entry_T_3186 = or(_issue_entry_T_3185, _issue_entry_T_3171) node _issue_entry_T_3187 = or(_issue_entry_T_3186, _issue_entry_T_3172) node _issue_entry_T_3188 = or(_issue_entry_T_3187, _issue_entry_T_3173) node _issue_entry_T_3189 = or(_issue_entry_T_3188, _issue_entry_T_3174) node _issue_entry_T_3190 = or(_issue_entry_T_3189, _issue_entry_T_3175) node _issue_entry_T_3191 = or(_issue_entry_T_3190, _issue_entry_T_3176) node _issue_entry_T_3192 = or(_issue_entry_T_3191, _issue_entry_T_3177) node _issue_entry_T_3193 = or(_issue_entry_T_3192, _issue_entry_T_3178) node _issue_entry_T_3194 = or(_issue_entry_T_3193, _issue_entry_T_3179) node _issue_entry_T_3195 = or(_issue_entry_T_3194, _issue_entry_T_3180) node _issue_entry_T_3196 = or(_issue_entry_T_3195, _issue_entry_T_3181) wire _issue_entry_WIRE_195 : UInt<2> connect _issue_entry_WIRE_195, _issue_entry_T_3196 connect _issue_entry_WIRE_183.fs, _issue_entry_WIRE_195 node _issue_entry_T_3197 = mux(issue_sel_0_1, entries_ex[0].bits.cmd.cmd.status.xs, UInt<1>(0h0)) node _issue_entry_T_3198 = mux(issue_sel_1_1, entries_ex[1].bits.cmd.cmd.status.xs, UInt<1>(0h0)) node _issue_entry_T_3199 = mux(issue_sel_2_1, entries_ex[2].bits.cmd.cmd.status.xs, UInt<1>(0h0)) node _issue_entry_T_3200 = mux(issue_sel_3_1, entries_ex[3].bits.cmd.cmd.status.xs, UInt<1>(0h0)) node _issue_entry_T_3201 = mux(issue_sel_4_1, entries_ex[4].bits.cmd.cmd.status.xs, UInt<1>(0h0)) node _issue_entry_T_3202 = mux(issue_sel_5_1, entries_ex[5].bits.cmd.cmd.status.xs, UInt<1>(0h0)) node _issue_entry_T_3203 = mux(issue_sel_6_1, entries_ex[6].bits.cmd.cmd.status.xs, UInt<1>(0h0)) node _issue_entry_T_3204 = mux(issue_sel_7_1, entries_ex[7].bits.cmd.cmd.status.xs, UInt<1>(0h0)) node _issue_entry_T_3205 = mux(issue_sel_8, entries_ex[8].bits.cmd.cmd.status.xs, UInt<1>(0h0)) node _issue_entry_T_3206 = mux(issue_sel_9, entries_ex[9].bits.cmd.cmd.status.xs, UInt<1>(0h0)) node _issue_entry_T_3207 = mux(issue_sel_10, entries_ex[10].bits.cmd.cmd.status.xs, UInt<1>(0h0)) node _issue_entry_T_3208 = mux(issue_sel_11, entries_ex[11].bits.cmd.cmd.status.xs, UInt<1>(0h0)) node _issue_entry_T_3209 = mux(issue_sel_12, entries_ex[12].bits.cmd.cmd.status.xs, UInt<1>(0h0)) node _issue_entry_T_3210 = mux(issue_sel_13, entries_ex[13].bits.cmd.cmd.status.xs, UInt<1>(0h0)) node _issue_entry_T_3211 = mux(issue_sel_14, entries_ex[14].bits.cmd.cmd.status.xs, UInt<1>(0h0)) node _issue_entry_T_3212 = mux(issue_sel_15, entries_ex[15].bits.cmd.cmd.status.xs, UInt<1>(0h0)) node _issue_entry_T_3213 = or(_issue_entry_T_3197, _issue_entry_T_3198) node _issue_entry_T_3214 = or(_issue_entry_T_3213, _issue_entry_T_3199) node _issue_entry_T_3215 = or(_issue_entry_T_3214, _issue_entry_T_3200) node _issue_entry_T_3216 = or(_issue_entry_T_3215, _issue_entry_T_3201) node _issue_entry_T_3217 = or(_issue_entry_T_3216, _issue_entry_T_3202) node _issue_entry_T_3218 = or(_issue_entry_T_3217, _issue_entry_T_3203) node _issue_entry_T_3219 = or(_issue_entry_T_3218, _issue_entry_T_3204) node _issue_entry_T_3220 = or(_issue_entry_T_3219, _issue_entry_T_3205) node _issue_entry_T_3221 = or(_issue_entry_T_3220, _issue_entry_T_3206) node _issue_entry_T_3222 = or(_issue_entry_T_3221, _issue_entry_T_3207) node _issue_entry_T_3223 = or(_issue_entry_T_3222, _issue_entry_T_3208) node _issue_entry_T_3224 = or(_issue_entry_T_3223, _issue_entry_T_3209) node _issue_entry_T_3225 = or(_issue_entry_T_3224, _issue_entry_T_3210) node _issue_entry_T_3226 = or(_issue_entry_T_3225, _issue_entry_T_3211) node _issue_entry_T_3227 = or(_issue_entry_T_3226, _issue_entry_T_3212) wire _issue_entry_WIRE_196 : UInt<2> connect _issue_entry_WIRE_196, _issue_entry_T_3227 connect _issue_entry_WIRE_183.xs, _issue_entry_WIRE_196 node _issue_entry_T_3228 = mux(issue_sel_0_1, entries_ex[0].bits.cmd.cmd.status.mprv, UInt<1>(0h0)) node _issue_entry_T_3229 = mux(issue_sel_1_1, entries_ex[1].bits.cmd.cmd.status.mprv, UInt<1>(0h0)) node _issue_entry_T_3230 = mux(issue_sel_2_1, entries_ex[2].bits.cmd.cmd.status.mprv, UInt<1>(0h0)) node _issue_entry_T_3231 = mux(issue_sel_3_1, entries_ex[3].bits.cmd.cmd.status.mprv, UInt<1>(0h0)) node _issue_entry_T_3232 = mux(issue_sel_4_1, entries_ex[4].bits.cmd.cmd.status.mprv, UInt<1>(0h0)) node _issue_entry_T_3233 = mux(issue_sel_5_1, entries_ex[5].bits.cmd.cmd.status.mprv, UInt<1>(0h0)) node _issue_entry_T_3234 = mux(issue_sel_6_1, entries_ex[6].bits.cmd.cmd.status.mprv, UInt<1>(0h0)) node _issue_entry_T_3235 = mux(issue_sel_7_1, entries_ex[7].bits.cmd.cmd.status.mprv, UInt<1>(0h0)) node _issue_entry_T_3236 = mux(issue_sel_8, entries_ex[8].bits.cmd.cmd.status.mprv, UInt<1>(0h0)) node _issue_entry_T_3237 = mux(issue_sel_9, entries_ex[9].bits.cmd.cmd.status.mprv, UInt<1>(0h0)) node _issue_entry_T_3238 = mux(issue_sel_10, entries_ex[10].bits.cmd.cmd.status.mprv, UInt<1>(0h0)) node _issue_entry_T_3239 = mux(issue_sel_11, entries_ex[11].bits.cmd.cmd.status.mprv, UInt<1>(0h0)) node _issue_entry_T_3240 = mux(issue_sel_12, entries_ex[12].bits.cmd.cmd.status.mprv, UInt<1>(0h0)) node _issue_entry_T_3241 = mux(issue_sel_13, entries_ex[13].bits.cmd.cmd.status.mprv, UInt<1>(0h0)) node _issue_entry_T_3242 = mux(issue_sel_14, entries_ex[14].bits.cmd.cmd.status.mprv, UInt<1>(0h0)) node _issue_entry_T_3243 = mux(issue_sel_15, entries_ex[15].bits.cmd.cmd.status.mprv, UInt<1>(0h0)) node _issue_entry_T_3244 = or(_issue_entry_T_3228, _issue_entry_T_3229) node _issue_entry_T_3245 = or(_issue_entry_T_3244, _issue_entry_T_3230) node _issue_entry_T_3246 = or(_issue_entry_T_3245, _issue_entry_T_3231) node _issue_entry_T_3247 = or(_issue_entry_T_3246, _issue_entry_T_3232) node _issue_entry_T_3248 = or(_issue_entry_T_3247, _issue_entry_T_3233) node _issue_entry_T_3249 = or(_issue_entry_T_3248, _issue_entry_T_3234) node _issue_entry_T_3250 = or(_issue_entry_T_3249, _issue_entry_T_3235) node _issue_entry_T_3251 = or(_issue_entry_T_3250, _issue_entry_T_3236) node _issue_entry_T_3252 = or(_issue_entry_T_3251, _issue_entry_T_3237) node _issue_entry_T_3253 = or(_issue_entry_T_3252, _issue_entry_T_3238) node _issue_entry_T_3254 = or(_issue_entry_T_3253, _issue_entry_T_3239) node _issue_entry_T_3255 = or(_issue_entry_T_3254, _issue_entry_T_3240) node _issue_entry_T_3256 = or(_issue_entry_T_3255, _issue_entry_T_3241) node _issue_entry_T_3257 = or(_issue_entry_T_3256, _issue_entry_T_3242) node _issue_entry_T_3258 = or(_issue_entry_T_3257, _issue_entry_T_3243) wire _issue_entry_WIRE_197 : UInt<1> connect _issue_entry_WIRE_197, _issue_entry_T_3258 connect _issue_entry_WIRE_183.mprv, _issue_entry_WIRE_197 node _issue_entry_T_3259 = mux(issue_sel_0_1, entries_ex[0].bits.cmd.cmd.status.sum, UInt<1>(0h0)) node _issue_entry_T_3260 = mux(issue_sel_1_1, entries_ex[1].bits.cmd.cmd.status.sum, UInt<1>(0h0)) node _issue_entry_T_3261 = mux(issue_sel_2_1, entries_ex[2].bits.cmd.cmd.status.sum, UInt<1>(0h0)) node _issue_entry_T_3262 = mux(issue_sel_3_1, entries_ex[3].bits.cmd.cmd.status.sum, UInt<1>(0h0)) node _issue_entry_T_3263 = mux(issue_sel_4_1, entries_ex[4].bits.cmd.cmd.status.sum, UInt<1>(0h0)) node _issue_entry_T_3264 = mux(issue_sel_5_1, entries_ex[5].bits.cmd.cmd.status.sum, UInt<1>(0h0)) node _issue_entry_T_3265 = mux(issue_sel_6_1, entries_ex[6].bits.cmd.cmd.status.sum, UInt<1>(0h0)) node _issue_entry_T_3266 = mux(issue_sel_7_1, entries_ex[7].bits.cmd.cmd.status.sum, UInt<1>(0h0)) node _issue_entry_T_3267 = mux(issue_sel_8, entries_ex[8].bits.cmd.cmd.status.sum, UInt<1>(0h0)) node _issue_entry_T_3268 = mux(issue_sel_9, entries_ex[9].bits.cmd.cmd.status.sum, UInt<1>(0h0)) node _issue_entry_T_3269 = mux(issue_sel_10, entries_ex[10].bits.cmd.cmd.status.sum, UInt<1>(0h0)) node _issue_entry_T_3270 = mux(issue_sel_11, entries_ex[11].bits.cmd.cmd.status.sum, UInt<1>(0h0)) node _issue_entry_T_3271 = mux(issue_sel_12, entries_ex[12].bits.cmd.cmd.status.sum, UInt<1>(0h0)) node _issue_entry_T_3272 = mux(issue_sel_13, entries_ex[13].bits.cmd.cmd.status.sum, UInt<1>(0h0)) node _issue_entry_T_3273 = mux(issue_sel_14, entries_ex[14].bits.cmd.cmd.status.sum, UInt<1>(0h0)) node _issue_entry_T_3274 = mux(issue_sel_15, entries_ex[15].bits.cmd.cmd.status.sum, UInt<1>(0h0)) node _issue_entry_T_3275 = or(_issue_entry_T_3259, _issue_entry_T_3260) node _issue_entry_T_3276 = or(_issue_entry_T_3275, _issue_entry_T_3261) node _issue_entry_T_3277 = or(_issue_entry_T_3276, _issue_entry_T_3262) node _issue_entry_T_3278 = or(_issue_entry_T_3277, _issue_entry_T_3263) node _issue_entry_T_3279 = or(_issue_entry_T_3278, _issue_entry_T_3264) node _issue_entry_T_3280 = or(_issue_entry_T_3279, _issue_entry_T_3265) node _issue_entry_T_3281 = or(_issue_entry_T_3280, _issue_entry_T_3266) node _issue_entry_T_3282 = or(_issue_entry_T_3281, _issue_entry_T_3267) node _issue_entry_T_3283 = or(_issue_entry_T_3282, _issue_entry_T_3268) node _issue_entry_T_3284 = or(_issue_entry_T_3283, _issue_entry_T_3269) node _issue_entry_T_3285 = or(_issue_entry_T_3284, _issue_entry_T_3270) node _issue_entry_T_3286 = or(_issue_entry_T_3285, _issue_entry_T_3271) node _issue_entry_T_3287 = or(_issue_entry_T_3286, _issue_entry_T_3272) node _issue_entry_T_3288 = or(_issue_entry_T_3287, _issue_entry_T_3273) node _issue_entry_T_3289 = or(_issue_entry_T_3288, _issue_entry_T_3274) wire _issue_entry_WIRE_198 : UInt<1> connect _issue_entry_WIRE_198, _issue_entry_T_3289 connect _issue_entry_WIRE_183.sum, _issue_entry_WIRE_198 node _issue_entry_T_3290 = mux(issue_sel_0_1, entries_ex[0].bits.cmd.cmd.status.mxr, UInt<1>(0h0)) node _issue_entry_T_3291 = mux(issue_sel_1_1, entries_ex[1].bits.cmd.cmd.status.mxr, UInt<1>(0h0)) node _issue_entry_T_3292 = mux(issue_sel_2_1, entries_ex[2].bits.cmd.cmd.status.mxr, UInt<1>(0h0)) node _issue_entry_T_3293 = mux(issue_sel_3_1, entries_ex[3].bits.cmd.cmd.status.mxr, UInt<1>(0h0)) node _issue_entry_T_3294 = mux(issue_sel_4_1, entries_ex[4].bits.cmd.cmd.status.mxr, UInt<1>(0h0)) node _issue_entry_T_3295 = mux(issue_sel_5_1, entries_ex[5].bits.cmd.cmd.status.mxr, UInt<1>(0h0)) node _issue_entry_T_3296 = mux(issue_sel_6_1, entries_ex[6].bits.cmd.cmd.status.mxr, UInt<1>(0h0)) node _issue_entry_T_3297 = mux(issue_sel_7_1, entries_ex[7].bits.cmd.cmd.status.mxr, UInt<1>(0h0)) node _issue_entry_T_3298 = mux(issue_sel_8, entries_ex[8].bits.cmd.cmd.status.mxr, UInt<1>(0h0)) node _issue_entry_T_3299 = mux(issue_sel_9, entries_ex[9].bits.cmd.cmd.status.mxr, UInt<1>(0h0)) node _issue_entry_T_3300 = mux(issue_sel_10, entries_ex[10].bits.cmd.cmd.status.mxr, UInt<1>(0h0)) node _issue_entry_T_3301 = mux(issue_sel_11, entries_ex[11].bits.cmd.cmd.status.mxr, UInt<1>(0h0)) node _issue_entry_T_3302 = mux(issue_sel_12, entries_ex[12].bits.cmd.cmd.status.mxr, UInt<1>(0h0)) node _issue_entry_T_3303 = mux(issue_sel_13, entries_ex[13].bits.cmd.cmd.status.mxr, UInt<1>(0h0)) node _issue_entry_T_3304 = mux(issue_sel_14, entries_ex[14].bits.cmd.cmd.status.mxr, UInt<1>(0h0)) node _issue_entry_T_3305 = mux(issue_sel_15, entries_ex[15].bits.cmd.cmd.status.mxr, UInt<1>(0h0)) node _issue_entry_T_3306 = or(_issue_entry_T_3290, _issue_entry_T_3291) node _issue_entry_T_3307 = or(_issue_entry_T_3306, _issue_entry_T_3292) node _issue_entry_T_3308 = or(_issue_entry_T_3307, _issue_entry_T_3293) node _issue_entry_T_3309 = or(_issue_entry_T_3308, _issue_entry_T_3294) node _issue_entry_T_3310 = or(_issue_entry_T_3309, _issue_entry_T_3295) node _issue_entry_T_3311 = or(_issue_entry_T_3310, _issue_entry_T_3296) node _issue_entry_T_3312 = or(_issue_entry_T_3311, _issue_entry_T_3297) node _issue_entry_T_3313 = or(_issue_entry_T_3312, _issue_entry_T_3298) node _issue_entry_T_3314 = or(_issue_entry_T_3313, _issue_entry_T_3299) node _issue_entry_T_3315 = or(_issue_entry_T_3314, _issue_entry_T_3300) node _issue_entry_T_3316 = or(_issue_entry_T_3315, _issue_entry_T_3301) node _issue_entry_T_3317 = or(_issue_entry_T_3316, _issue_entry_T_3302) node _issue_entry_T_3318 = or(_issue_entry_T_3317, _issue_entry_T_3303) node _issue_entry_T_3319 = or(_issue_entry_T_3318, _issue_entry_T_3304) node _issue_entry_T_3320 = or(_issue_entry_T_3319, _issue_entry_T_3305) wire _issue_entry_WIRE_199 : UInt<1> connect _issue_entry_WIRE_199, _issue_entry_T_3320 connect _issue_entry_WIRE_183.mxr, _issue_entry_WIRE_199 node _issue_entry_T_3321 = mux(issue_sel_0_1, entries_ex[0].bits.cmd.cmd.status.tvm, UInt<1>(0h0)) node _issue_entry_T_3322 = mux(issue_sel_1_1, entries_ex[1].bits.cmd.cmd.status.tvm, UInt<1>(0h0)) node _issue_entry_T_3323 = mux(issue_sel_2_1, entries_ex[2].bits.cmd.cmd.status.tvm, UInt<1>(0h0)) node _issue_entry_T_3324 = mux(issue_sel_3_1, entries_ex[3].bits.cmd.cmd.status.tvm, UInt<1>(0h0)) node _issue_entry_T_3325 = mux(issue_sel_4_1, entries_ex[4].bits.cmd.cmd.status.tvm, UInt<1>(0h0)) node _issue_entry_T_3326 = mux(issue_sel_5_1, entries_ex[5].bits.cmd.cmd.status.tvm, UInt<1>(0h0)) node _issue_entry_T_3327 = mux(issue_sel_6_1, entries_ex[6].bits.cmd.cmd.status.tvm, UInt<1>(0h0)) node _issue_entry_T_3328 = mux(issue_sel_7_1, entries_ex[7].bits.cmd.cmd.status.tvm, UInt<1>(0h0)) node _issue_entry_T_3329 = mux(issue_sel_8, entries_ex[8].bits.cmd.cmd.status.tvm, UInt<1>(0h0)) node _issue_entry_T_3330 = mux(issue_sel_9, entries_ex[9].bits.cmd.cmd.status.tvm, UInt<1>(0h0)) node _issue_entry_T_3331 = mux(issue_sel_10, entries_ex[10].bits.cmd.cmd.status.tvm, UInt<1>(0h0)) node _issue_entry_T_3332 = mux(issue_sel_11, entries_ex[11].bits.cmd.cmd.status.tvm, UInt<1>(0h0)) node _issue_entry_T_3333 = mux(issue_sel_12, entries_ex[12].bits.cmd.cmd.status.tvm, UInt<1>(0h0)) node _issue_entry_T_3334 = mux(issue_sel_13, entries_ex[13].bits.cmd.cmd.status.tvm, UInt<1>(0h0)) node _issue_entry_T_3335 = mux(issue_sel_14, entries_ex[14].bits.cmd.cmd.status.tvm, UInt<1>(0h0)) node _issue_entry_T_3336 = mux(issue_sel_15, entries_ex[15].bits.cmd.cmd.status.tvm, UInt<1>(0h0)) node _issue_entry_T_3337 = or(_issue_entry_T_3321, _issue_entry_T_3322) node _issue_entry_T_3338 = or(_issue_entry_T_3337, _issue_entry_T_3323) node _issue_entry_T_3339 = or(_issue_entry_T_3338, _issue_entry_T_3324) node _issue_entry_T_3340 = or(_issue_entry_T_3339, _issue_entry_T_3325) node _issue_entry_T_3341 = or(_issue_entry_T_3340, _issue_entry_T_3326) node _issue_entry_T_3342 = or(_issue_entry_T_3341, _issue_entry_T_3327) node _issue_entry_T_3343 = or(_issue_entry_T_3342, _issue_entry_T_3328) node _issue_entry_T_3344 = or(_issue_entry_T_3343, _issue_entry_T_3329) node _issue_entry_T_3345 = or(_issue_entry_T_3344, _issue_entry_T_3330) node _issue_entry_T_3346 = or(_issue_entry_T_3345, _issue_entry_T_3331) node _issue_entry_T_3347 = or(_issue_entry_T_3346, _issue_entry_T_3332) node _issue_entry_T_3348 = or(_issue_entry_T_3347, _issue_entry_T_3333) node _issue_entry_T_3349 = or(_issue_entry_T_3348, _issue_entry_T_3334) node _issue_entry_T_3350 = or(_issue_entry_T_3349, _issue_entry_T_3335) node _issue_entry_T_3351 = or(_issue_entry_T_3350, _issue_entry_T_3336) wire _issue_entry_WIRE_200 : UInt<1> connect _issue_entry_WIRE_200, _issue_entry_T_3351 connect _issue_entry_WIRE_183.tvm, _issue_entry_WIRE_200 node _issue_entry_T_3352 = mux(issue_sel_0_1, entries_ex[0].bits.cmd.cmd.status.tw, UInt<1>(0h0)) node _issue_entry_T_3353 = mux(issue_sel_1_1, entries_ex[1].bits.cmd.cmd.status.tw, UInt<1>(0h0)) node _issue_entry_T_3354 = mux(issue_sel_2_1, entries_ex[2].bits.cmd.cmd.status.tw, UInt<1>(0h0)) node _issue_entry_T_3355 = mux(issue_sel_3_1, entries_ex[3].bits.cmd.cmd.status.tw, UInt<1>(0h0)) node _issue_entry_T_3356 = mux(issue_sel_4_1, entries_ex[4].bits.cmd.cmd.status.tw, UInt<1>(0h0)) node _issue_entry_T_3357 = mux(issue_sel_5_1, entries_ex[5].bits.cmd.cmd.status.tw, UInt<1>(0h0)) node _issue_entry_T_3358 = mux(issue_sel_6_1, entries_ex[6].bits.cmd.cmd.status.tw, UInt<1>(0h0)) node _issue_entry_T_3359 = mux(issue_sel_7_1, entries_ex[7].bits.cmd.cmd.status.tw, UInt<1>(0h0)) node _issue_entry_T_3360 = mux(issue_sel_8, entries_ex[8].bits.cmd.cmd.status.tw, UInt<1>(0h0)) node _issue_entry_T_3361 = mux(issue_sel_9, entries_ex[9].bits.cmd.cmd.status.tw, UInt<1>(0h0)) node _issue_entry_T_3362 = mux(issue_sel_10, entries_ex[10].bits.cmd.cmd.status.tw, UInt<1>(0h0)) node _issue_entry_T_3363 = mux(issue_sel_11, entries_ex[11].bits.cmd.cmd.status.tw, UInt<1>(0h0)) node _issue_entry_T_3364 = mux(issue_sel_12, entries_ex[12].bits.cmd.cmd.status.tw, UInt<1>(0h0)) node _issue_entry_T_3365 = mux(issue_sel_13, entries_ex[13].bits.cmd.cmd.status.tw, UInt<1>(0h0)) node _issue_entry_T_3366 = mux(issue_sel_14, entries_ex[14].bits.cmd.cmd.status.tw, UInt<1>(0h0)) node _issue_entry_T_3367 = mux(issue_sel_15, entries_ex[15].bits.cmd.cmd.status.tw, UInt<1>(0h0)) node _issue_entry_T_3368 = or(_issue_entry_T_3352, _issue_entry_T_3353) node _issue_entry_T_3369 = or(_issue_entry_T_3368, _issue_entry_T_3354) node _issue_entry_T_3370 = or(_issue_entry_T_3369, _issue_entry_T_3355) node _issue_entry_T_3371 = or(_issue_entry_T_3370, _issue_entry_T_3356) node _issue_entry_T_3372 = or(_issue_entry_T_3371, _issue_entry_T_3357) node _issue_entry_T_3373 = or(_issue_entry_T_3372, _issue_entry_T_3358) node _issue_entry_T_3374 = or(_issue_entry_T_3373, _issue_entry_T_3359) node _issue_entry_T_3375 = or(_issue_entry_T_3374, _issue_entry_T_3360) node _issue_entry_T_3376 = or(_issue_entry_T_3375, _issue_entry_T_3361) node _issue_entry_T_3377 = or(_issue_entry_T_3376, _issue_entry_T_3362) node _issue_entry_T_3378 = or(_issue_entry_T_3377, _issue_entry_T_3363) node _issue_entry_T_3379 = or(_issue_entry_T_3378, _issue_entry_T_3364) node _issue_entry_T_3380 = or(_issue_entry_T_3379, _issue_entry_T_3365) node _issue_entry_T_3381 = or(_issue_entry_T_3380, _issue_entry_T_3366) node _issue_entry_T_3382 = or(_issue_entry_T_3381, _issue_entry_T_3367) wire _issue_entry_WIRE_201 : UInt<1> connect _issue_entry_WIRE_201, _issue_entry_T_3382 connect _issue_entry_WIRE_183.tw, _issue_entry_WIRE_201 node _issue_entry_T_3383 = mux(issue_sel_0_1, entries_ex[0].bits.cmd.cmd.status.tsr, UInt<1>(0h0)) node _issue_entry_T_3384 = mux(issue_sel_1_1, entries_ex[1].bits.cmd.cmd.status.tsr, UInt<1>(0h0)) node _issue_entry_T_3385 = mux(issue_sel_2_1, entries_ex[2].bits.cmd.cmd.status.tsr, UInt<1>(0h0)) node _issue_entry_T_3386 = mux(issue_sel_3_1, entries_ex[3].bits.cmd.cmd.status.tsr, UInt<1>(0h0)) node _issue_entry_T_3387 = mux(issue_sel_4_1, entries_ex[4].bits.cmd.cmd.status.tsr, UInt<1>(0h0)) node _issue_entry_T_3388 = mux(issue_sel_5_1, entries_ex[5].bits.cmd.cmd.status.tsr, UInt<1>(0h0)) node _issue_entry_T_3389 = mux(issue_sel_6_1, entries_ex[6].bits.cmd.cmd.status.tsr, UInt<1>(0h0)) node _issue_entry_T_3390 = mux(issue_sel_7_1, entries_ex[7].bits.cmd.cmd.status.tsr, UInt<1>(0h0)) node _issue_entry_T_3391 = mux(issue_sel_8, entries_ex[8].bits.cmd.cmd.status.tsr, UInt<1>(0h0)) node _issue_entry_T_3392 = mux(issue_sel_9, entries_ex[9].bits.cmd.cmd.status.tsr, UInt<1>(0h0)) node _issue_entry_T_3393 = mux(issue_sel_10, entries_ex[10].bits.cmd.cmd.status.tsr, UInt<1>(0h0)) node _issue_entry_T_3394 = mux(issue_sel_11, entries_ex[11].bits.cmd.cmd.status.tsr, UInt<1>(0h0)) node _issue_entry_T_3395 = mux(issue_sel_12, entries_ex[12].bits.cmd.cmd.status.tsr, UInt<1>(0h0)) node _issue_entry_T_3396 = mux(issue_sel_13, entries_ex[13].bits.cmd.cmd.status.tsr, UInt<1>(0h0)) node _issue_entry_T_3397 = mux(issue_sel_14, entries_ex[14].bits.cmd.cmd.status.tsr, UInt<1>(0h0)) node _issue_entry_T_3398 = mux(issue_sel_15, entries_ex[15].bits.cmd.cmd.status.tsr, UInt<1>(0h0)) node _issue_entry_T_3399 = or(_issue_entry_T_3383, _issue_entry_T_3384) node _issue_entry_T_3400 = or(_issue_entry_T_3399, _issue_entry_T_3385) node _issue_entry_T_3401 = or(_issue_entry_T_3400, _issue_entry_T_3386) node _issue_entry_T_3402 = or(_issue_entry_T_3401, _issue_entry_T_3387) node _issue_entry_T_3403 = or(_issue_entry_T_3402, _issue_entry_T_3388) node _issue_entry_T_3404 = or(_issue_entry_T_3403, _issue_entry_T_3389) node _issue_entry_T_3405 = or(_issue_entry_T_3404, _issue_entry_T_3390) node _issue_entry_T_3406 = or(_issue_entry_T_3405, _issue_entry_T_3391) node _issue_entry_T_3407 = or(_issue_entry_T_3406, _issue_entry_T_3392) node _issue_entry_T_3408 = or(_issue_entry_T_3407, _issue_entry_T_3393) node _issue_entry_T_3409 = or(_issue_entry_T_3408, _issue_entry_T_3394) node _issue_entry_T_3410 = or(_issue_entry_T_3409, _issue_entry_T_3395) node _issue_entry_T_3411 = or(_issue_entry_T_3410, _issue_entry_T_3396) node _issue_entry_T_3412 = or(_issue_entry_T_3411, _issue_entry_T_3397) node _issue_entry_T_3413 = or(_issue_entry_T_3412, _issue_entry_T_3398) wire _issue_entry_WIRE_202 : UInt<1> connect _issue_entry_WIRE_202, _issue_entry_T_3413 connect _issue_entry_WIRE_183.tsr, _issue_entry_WIRE_202 node _issue_entry_T_3414 = mux(issue_sel_0_1, entries_ex[0].bits.cmd.cmd.status.zero1, UInt<1>(0h0)) node _issue_entry_T_3415 = mux(issue_sel_1_1, entries_ex[1].bits.cmd.cmd.status.zero1, UInt<1>(0h0)) node _issue_entry_T_3416 = mux(issue_sel_2_1, entries_ex[2].bits.cmd.cmd.status.zero1, UInt<1>(0h0)) node _issue_entry_T_3417 = mux(issue_sel_3_1, entries_ex[3].bits.cmd.cmd.status.zero1, UInt<1>(0h0)) node _issue_entry_T_3418 = mux(issue_sel_4_1, entries_ex[4].bits.cmd.cmd.status.zero1, UInt<1>(0h0)) node _issue_entry_T_3419 = mux(issue_sel_5_1, entries_ex[5].bits.cmd.cmd.status.zero1, UInt<1>(0h0)) node _issue_entry_T_3420 = mux(issue_sel_6_1, entries_ex[6].bits.cmd.cmd.status.zero1, UInt<1>(0h0)) node _issue_entry_T_3421 = mux(issue_sel_7_1, entries_ex[7].bits.cmd.cmd.status.zero1, UInt<1>(0h0)) node _issue_entry_T_3422 = mux(issue_sel_8, entries_ex[8].bits.cmd.cmd.status.zero1, UInt<1>(0h0)) node _issue_entry_T_3423 = mux(issue_sel_9, entries_ex[9].bits.cmd.cmd.status.zero1, UInt<1>(0h0)) node _issue_entry_T_3424 = mux(issue_sel_10, entries_ex[10].bits.cmd.cmd.status.zero1, UInt<1>(0h0)) node _issue_entry_T_3425 = mux(issue_sel_11, entries_ex[11].bits.cmd.cmd.status.zero1, UInt<1>(0h0)) node _issue_entry_T_3426 = mux(issue_sel_12, entries_ex[12].bits.cmd.cmd.status.zero1, UInt<1>(0h0)) node _issue_entry_T_3427 = mux(issue_sel_13, entries_ex[13].bits.cmd.cmd.status.zero1, UInt<1>(0h0)) node _issue_entry_T_3428 = mux(issue_sel_14, entries_ex[14].bits.cmd.cmd.status.zero1, UInt<1>(0h0)) node _issue_entry_T_3429 = mux(issue_sel_15, entries_ex[15].bits.cmd.cmd.status.zero1, UInt<1>(0h0)) node _issue_entry_T_3430 = or(_issue_entry_T_3414, _issue_entry_T_3415) node _issue_entry_T_3431 = or(_issue_entry_T_3430, _issue_entry_T_3416) node _issue_entry_T_3432 = or(_issue_entry_T_3431, _issue_entry_T_3417) node _issue_entry_T_3433 = or(_issue_entry_T_3432, _issue_entry_T_3418) node _issue_entry_T_3434 = or(_issue_entry_T_3433, _issue_entry_T_3419) node _issue_entry_T_3435 = or(_issue_entry_T_3434, _issue_entry_T_3420) node _issue_entry_T_3436 = or(_issue_entry_T_3435, _issue_entry_T_3421) node _issue_entry_T_3437 = or(_issue_entry_T_3436, _issue_entry_T_3422) node _issue_entry_T_3438 = or(_issue_entry_T_3437, _issue_entry_T_3423) node _issue_entry_T_3439 = or(_issue_entry_T_3438, _issue_entry_T_3424) node _issue_entry_T_3440 = or(_issue_entry_T_3439, _issue_entry_T_3425) node _issue_entry_T_3441 = or(_issue_entry_T_3440, _issue_entry_T_3426) node _issue_entry_T_3442 = or(_issue_entry_T_3441, _issue_entry_T_3427) node _issue_entry_T_3443 = or(_issue_entry_T_3442, _issue_entry_T_3428) node _issue_entry_T_3444 = or(_issue_entry_T_3443, _issue_entry_T_3429) wire _issue_entry_WIRE_203 : UInt<8> connect _issue_entry_WIRE_203, _issue_entry_T_3444 connect _issue_entry_WIRE_183.zero1, _issue_entry_WIRE_203 node _issue_entry_T_3445 = mux(issue_sel_0_1, entries_ex[0].bits.cmd.cmd.status.sd_rv32, UInt<1>(0h0)) node _issue_entry_T_3446 = mux(issue_sel_1_1, entries_ex[1].bits.cmd.cmd.status.sd_rv32, UInt<1>(0h0)) node _issue_entry_T_3447 = mux(issue_sel_2_1, entries_ex[2].bits.cmd.cmd.status.sd_rv32, UInt<1>(0h0)) node _issue_entry_T_3448 = mux(issue_sel_3_1, entries_ex[3].bits.cmd.cmd.status.sd_rv32, UInt<1>(0h0)) node _issue_entry_T_3449 = mux(issue_sel_4_1, entries_ex[4].bits.cmd.cmd.status.sd_rv32, UInt<1>(0h0)) node _issue_entry_T_3450 = mux(issue_sel_5_1, entries_ex[5].bits.cmd.cmd.status.sd_rv32, UInt<1>(0h0)) node _issue_entry_T_3451 = mux(issue_sel_6_1, entries_ex[6].bits.cmd.cmd.status.sd_rv32, UInt<1>(0h0)) node _issue_entry_T_3452 = mux(issue_sel_7_1, entries_ex[7].bits.cmd.cmd.status.sd_rv32, UInt<1>(0h0)) node _issue_entry_T_3453 = mux(issue_sel_8, entries_ex[8].bits.cmd.cmd.status.sd_rv32, UInt<1>(0h0)) node _issue_entry_T_3454 = mux(issue_sel_9, entries_ex[9].bits.cmd.cmd.status.sd_rv32, UInt<1>(0h0)) node _issue_entry_T_3455 = mux(issue_sel_10, entries_ex[10].bits.cmd.cmd.status.sd_rv32, UInt<1>(0h0)) node _issue_entry_T_3456 = mux(issue_sel_11, entries_ex[11].bits.cmd.cmd.status.sd_rv32, UInt<1>(0h0)) node _issue_entry_T_3457 = mux(issue_sel_12, entries_ex[12].bits.cmd.cmd.status.sd_rv32, UInt<1>(0h0)) node _issue_entry_T_3458 = mux(issue_sel_13, entries_ex[13].bits.cmd.cmd.status.sd_rv32, UInt<1>(0h0)) node _issue_entry_T_3459 = mux(issue_sel_14, entries_ex[14].bits.cmd.cmd.status.sd_rv32, UInt<1>(0h0)) node _issue_entry_T_3460 = mux(issue_sel_15, entries_ex[15].bits.cmd.cmd.status.sd_rv32, UInt<1>(0h0)) node _issue_entry_T_3461 = or(_issue_entry_T_3445, _issue_entry_T_3446) node _issue_entry_T_3462 = or(_issue_entry_T_3461, _issue_entry_T_3447) node _issue_entry_T_3463 = or(_issue_entry_T_3462, _issue_entry_T_3448) node _issue_entry_T_3464 = or(_issue_entry_T_3463, _issue_entry_T_3449) node _issue_entry_T_3465 = or(_issue_entry_T_3464, _issue_entry_T_3450) node _issue_entry_T_3466 = or(_issue_entry_T_3465, _issue_entry_T_3451) node _issue_entry_T_3467 = or(_issue_entry_T_3466, _issue_entry_T_3452) node _issue_entry_T_3468 = or(_issue_entry_T_3467, _issue_entry_T_3453) node _issue_entry_T_3469 = or(_issue_entry_T_3468, _issue_entry_T_3454) node _issue_entry_T_3470 = or(_issue_entry_T_3469, _issue_entry_T_3455) node _issue_entry_T_3471 = or(_issue_entry_T_3470, _issue_entry_T_3456) node _issue_entry_T_3472 = or(_issue_entry_T_3471, _issue_entry_T_3457) node _issue_entry_T_3473 = or(_issue_entry_T_3472, _issue_entry_T_3458) node _issue_entry_T_3474 = or(_issue_entry_T_3473, _issue_entry_T_3459) node _issue_entry_T_3475 = or(_issue_entry_T_3474, _issue_entry_T_3460) wire _issue_entry_WIRE_204 : UInt<1> connect _issue_entry_WIRE_204, _issue_entry_T_3475 connect _issue_entry_WIRE_183.sd_rv32, _issue_entry_WIRE_204 node _issue_entry_T_3476 = mux(issue_sel_0_1, entries_ex[0].bits.cmd.cmd.status.uxl, UInt<1>(0h0)) node _issue_entry_T_3477 = mux(issue_sel_1_1, entries_ex[1].bits.cmd.cmd.status.uxl, UInt<1>(0h0)) node _issue_entry_T_3478 = mux(issue_sel_2_1, entries_ex[2].bits.cmd.cmd.status.uxl, UInt<1>(0h0)) node _issue_entry_T_3479 = mux(issue_sel_3_1, entries_ex[3].bits.cmd.cmd.status.uxl, UInt<1>(0h0)) node _issue_entry_T_3480 = mux(issue_sel_4_1, entries_ex[4].bits.cmd.cmd.status.uxl, UInt<1>(0h0)) node _issue_entry_T_3481 = mux(issue_sel_5_1, entries_ex[5].bits.cmd.cmd.status.uxl, UInt<1>(0h0)) node _issue_entry_T_3482 = mux(issue_sel_6_1, entries_ex[6].bits.cmd.cmd.status.uxl, UInt<1>(0h0)) node _issue_entry_T_3483 = mux(issue_sel_7_1, entries_ex[7].bits.cmd.cmd.status.uxl, UInt<1>(0h0)) node _issue_entry_T_3484 = mux(issue_sel_8, entries_ex[8].bits.cmd.cmd.status.uxl, UInt<1>(0h0)) node _issue_entry_T_3485 = mux(issue_sel_9, entries_ex[9].bits.cmd.cmd.status.uxl, UInt<1>(0h0)) node _issue_entry_T_3486 = mux(issue_sel_10, entries_ex[10].bits.cmd.cmd.status.uxl, UInt<1>(0h0)) node _issue_entry_T_3487 = mux(issue_sel_11, entries_ex[11].bits.cmd.cmd.status.uxl, UInt<1>(0h0)) node _issue_entry_T_3488 = mux(issue_sel_12, entries_ex[12].bits.cmd.cmd.status.uxl, UInt<1>(0h0)) node _issue_entry_T_3489 = mux(issue_sel_13, entries_ex[13].bits.cmd.cmd.status.uxl, UInt<1>(0h0)) node _issue_entry_T_3490 = mux(issue_sel_14, entries_ex[14].bits.cmd.cmd.status.uxl, UInt<1>(0h0)) node _issue_entry_T_3491 = mux(issue_sel_15, entries_ex[15].bits.cmd.cmd.status.uxl, UInt<1>(0h0)) node _issue_entry_T_3492 = or(_issue_entry_T_3476, _issue_entry_T_3477) node _issue_entry_T_3493 = or(_issue_entry_T_3492, _issue_entry_T_3478) node _issue_entry_T_3494 = or(_issue_entry_T_3493, _issue_entry_T_3479) node _issue_entry_T_3495 = or(_issue_entry_T_3494, _issue_entry_T_3480) node _issue_entry_T_3496 = or(_issue_entry_T_3495, _issue_entry_T_3481) node _issue_entry_T_3497 = or(_issue_entry_T_3496, _issue_entry_T_3482) node _issue_entry_T_3498 = or(_issue_entry_T_3497, _issue_entry_T_3483) node _issue_entry_T_3499 = or(_issue_entry_T_3498, _issue_entry_T_3484) node _issue_entry_T_3500 = or(_issue_entry_T_3499, _issue_entry_T_3485) node _issue_entry_T_3501 = or(_issue_entry_T_3500, _issue_entry_T_3486) node _issue_entry_T_3502 = or(_issue_entry_T_3501, _issue_entry_T_3487) node _issue_entry_T_3503 = or(_issue_entry_T_3502, _issue_entry_T_3488) node _issue_entry_T_3504 = or(_issue_entry_T_3503, _issue_entry_T_3489) node _issue_entry_T_3505 = or(_issue_entry_T_3504, _issue_entry_T_3490) node _issue_entry_T_3506 = or(_issue_entry_T_3505, _issue_entry_T_3491) wire _issue_entry_WIRE_205 : UInt<2> connect _issue_entry_WIRE_205, _issue_entry_T_3506 connect _issue_entry_WIRE_183.uxl, _issue_entry_WIRE_205 node _issue_entry_T_3507 = mux(issue_sel_0_1, entries_ex[0].bits.cmd.cmd.status.sxl, UInt<1>(0h0)) node _issue_entry_T_3508 = mux(issue_sel_1_1, entries_ex[1].bits.cmd.cmd.status.sxl, UInt<1>(0h0)) node _issue_entry_T_3509 = mux(issue_sel_2_1, entries_ex[2].bits.cmd.cmd.status.sxl, UInt<1>(0h0)) node _issue_entry_T_3510 = mux(issue_sel_3_1, entries_ex[3].bits.cmd.cmd.status.sxl, UInt<1>(0h0)) node _issue_entry_T_3511 = mux(issue_sel_4_1, entries_ex[4].bits.cmd.cmd.status.sxl, UInt<1>(0h0)) node _issue_entry_T_3512 = mux(issue_sel_5_1, entries_ex[5].bits.cmd.cmd.status.sxl, UInt<1>(0h0)) node _issue_entry_T_3513 = mux(issue_sel_6_1, entries_ex[6].bits.cmd.cmd.status.sxl, UInt<1>(0h0)) node _issue_entry_T_3514 = mux(issue_sel_7_1, entries_ex[7].bits.cmd.cmd.status.sxl, UInt<1>(0h0)) node _issue_entry_T_3515 = mux(issue_sel_8, entries_ex[8].bits.cmd.cmd.status.sxl, UInt<1>(0h0)) node _issue_entry_T_3516 = mux(issue_sel_9, entries_ex[9].bits.cmd.cmd.status.sxl, UInt<1>(0h0)) node _issue_entry_T_3517 = mux(issue_sel_10, entries_ex[10].bits.cmd.cmd.status.sxl, UInt<1>(0h0)) node _issue_entry_T_3518 = mux(issue_sel_11, entries_ex[11].bits.cmd.cmd.status.sxl, UInt<1>(0h0)) node _issue_entry_T_3519 = mux(issue_sel_12, entries_ex[12].bits.cmd.cmd.status.sxl, UInt<1>(0h0)) node _issue_entry_T_3520 = mux(issue_sel_13, entries_ex[13].bits.cmd.cmd.status.sxl, UInt<1>(0h0)) node _issue_entry_T_3521 = mux(issue_sel_14, entries_ex[14].bits.cmd.cmd.status.sxl, UInt<1>(0h0)) node _issue_entry_T_3522 = mux(issue_sel_15, entries_ex[15].bits.cmd.cmd.status.sxl, UInt<1>(0h0)) node _issue_entry_T_3523 = or(_issue_entry_T_3507, _issue_entry_T_3508) node _issue_entry_T_3524 = or(_issue_entry_T_3523, _issue_entry_T_3509) node _issue_entry_T_3525 = or(_issue_entry_T_3524, _issue_entry_T_3510) node _issue_entry_T_3526 = or(_issue_entry_T_3525, _issue_entry_T_3511) node _issue_entry_T_3527 = or(_issue_entry_T_3526, _issue_entry_T_3512) node _issue_entry_T_3528 = or(_issue_entry_T_3527, _issue_entry_T_3513) node _issue_entry_T_3529 = or(_issue_entry_T_3528, _issue_entry_T_3514) node _issue_entry_T_3530 = or(_issue_entry_T_3529, _issue_entry_T_3515) node _issue_entry_T_3531 = or(_issue_entry_T_3530, _issue_entry_T_3516) node _issue_entry_T_3532 = or(_issue_entry_T_3531, _issue_entry_T_3517) node _issue_entry_T_3533 = or(_issue_entry_T_3532, _issue_entry_T_3518) node _issue_entry_T_3534 = or(_issue_entry_T_3533, _issue_entry_T_3519) node _issue_entry_T_3535 = or(_issue_entry_T_3534, _issue_entry_T_3520) node _issue_entry_T_3536 = or(_issue_entry_T_3535, _issue_entry_T_3521) node _issue_entry_T_3537 = or(_issue_entry_T_3536, _issue_entry_T_3522) wire _issue_entry_WIRE_206 : UInt<2> connect _issue_entry_WIRE_206, _issue_entry_T_3537 connect _issue_entry_WIRE_183.sxl, _issue_entry_WIRE_206 node _issue_entry_T_3538 = mux(issue_sel_0_1, entries_ex[0].bits.cmd.cmd.status.sbe, UInt<1>(0h0)) node _issue_entry_T_3539 = mux(issue_sel_1_1, entries_ex[1].bits.cmd.cmd.status.sbe, UInt<1>(0h0)) node _issue_entry_T_3540 = mux(issue_sel_2_1, entries_ex[2].bits.cmd.cmd.status.sbe, UInt<1>(0h0)) node _issue_entry_T_3541 = mux(issue_sel_3_1, entries_ex[3].bits.cmd.cmd.status.sbe, UInt<1>(0h0)) node _issue_entry_T_3542 = mux(issue_sel_4_1, entries_ex[4].bits.cmd.cmd.status.sbe, UInt<1>(0h0)) node _issue_entry_T_3543 = mux(issue_sel_5_1, entries_ex[5].bits.cmd.cmd.status.sbe, UInt<1>(0h0)) node _issue_entry_T_3544 = mux(issue_sel_6_1, entries_ex[6].bits.cmd.cmd.status.sbe, UInt<1>(0h0)) node _issue_entry_T_3545 = mux(issue_sel_7_1, entries_ex[7].bits.cmd.cmd.status.sbe, UInt<1>(0h0)) node _issue_entry_T_3546 = mux(issue_sel_8, entries_ex[8].bits.cmd.cmd.status.sbe, UInt<1>(0h0)) node _issue_entry_T_3547 = mux(issue_sel_9, entries_ex[9].bits.cmd.cmd.status.sbe, UInt<1>(0h0)) node _issue_entry_T_3548 = mux(issue_sel_10, entries_ex[10].bits.cmd.cmd.status.sbe, UInt<1>(0h0)) node _issue_entry_T_3549 = mux(issue_sel_11, entries_ex[11].bits.cmd.cmd.status.sbe, UInt<1>(0h0)) node _issue_entry_T_3550 = mux(issue_sel_12, entries_ex[12].bits.cmd.cmd.status.sbe, UInt<1>(0h0)) node _issue_entry_T_3551 = mux(issue_sel_13, entries_ex[13].bits.cmd.cmd.status.sbe, UInt<1>(0h0)) node _issue_entry_T_3552 = mux(issue_sel_14, entries_ex[14].bits.cmd.cmd.status.sbe, UInt<1>(0h0)) node _issue_entry_T_3553 = mux(issue_sel_15, entries_ex[15].bits.cmd.cmd.status.sbe, UInt<1>(0h0)) node _issue_entry_T_3554 = or(_issue_entry_T_3538, _issue_entry_T_3539) node _issue_entry_T_3555 = or(_issue_entry_T_3554, _issue_entry_T_3540) node _issue_entry_T_3556 = or(_issue_entry_T_3555, _issue_entry_T_3541) node _issue_entry_T_3557 = or(_issue_entry_T_3556, _issue_entry_T_3542) node _issue_entry_T_3558 = or(_issue_entry_T_3557, _issue_entry_T_3543) node _issue_entry_T_3559 = or(_issue_entry_T_3558, _issue_entry_T_3544) node _issue_entry_T_3560 = or(_issue_entry_T_3559, _issue_entry_T_3545) node _issue_entry_T_3561 = or(_issue_entry_T_3560, _issue_entry_T_3546) node _issue_entry_T_3562 = or(_issue_entry_T_3561, _issue_entry_T_3547) node _issue_entry_T_3563 = or(_issue_entry_T_3562, _issue_entry_T_3548) node _issue_entry_T_3564 = or(_issue_entry_T_3563, _issue_entry_T_3549) node _issue_entry_T_3565 = or(_issue_entry_T_3564, _issue_entry_T_3550) node _issue_entry_T_3566 = or(_issue_entry_T_3565, _issue_entry_T_3551) node _issue_entry_T_3567 = or(_issue_entry_T_3566, _issue_entry_T_3552) node _issue_entry_T_3568 = or(_issue_entry_T_3567, _issue_entry_T_3553) wire _issue_entry_WIRE_207 : UInt<1> connect _issue_entry_WIRE_207, _issue_entry_T_3568 connect _issue_entry_WIRE_183.sbe, _issue_entry_WIRE_207 node _issue_entry_T_3569 = mux(issue_sel_0_1, entries_ex[0].bits.cmd.cmd.status.mbe, UInt<1>(0h0)) node _issue_entry_T_3570 = mux(issue_sel_1_1, entries_ex[1].bits.cmd.cmd.status.mbe, UInt<1>(0h0)) node _issue_entry_T_3571 = mux(issue_sel_2_1, entries_ex[2].bits.cmd.cmd.status.mbe, UInt<1>(0h0)) node _issue_entry_T_3572 = mux(issue_sel_3_1, entries_ex[3].bits.cmd.cmd.status.mbe, UInt<1>(0h0)) node _issue_entry_T_3573 = mux(issue_sel_4_1, entries_ex[4].bits.cmd.cmd.status.mbe, UInt<1>(0h0)) node _issue_entry_T_3574 = mux(issue_sel_5_1, entries_ex[5].bits.cmd.cmd.status.mbe, UInt<1>(0h0)) node _issue_entry_T_3575 = mux(issue_sel_6_1, entries_ex[6].bits.cmd.cmd.status.mbe, UInt<1>(0h0)) node _issue_entry_T_3576 = mux(issue_sel_7_1, entries_ex[7].bits.cmd.cmd.status.mbe, UInt<1>(0h0)) node _issue_entry_T_3577 = mux(issue_sel_8, entries_ex[8].bits.cmd.cmd.status.mbe, UInt<1>(0h0)) node _issue_entry_T_3578 = mux(issue_sel_9, entries_ex[9].bits.cmd.cmd.status.mbe, UInt<1>(0h0)) node _issue_entry_T_3579 = mux(issue_sel_10, entries_ex[10].bits.cmd.cmd.status.mbe, UInt<1>(0h0)) node _issue_entry_T_3580 = mux(issue_sel_11, entries_ex[11].bits.cmd.cmd.status.mbe, UInt<1>(0h0)) node _issue_entry_T_3581 = mux(issue_sel_12, entries_ex[12].bits.cmd.cmd.status.mbe, UInt<1>(0h0)) node _issue_entry_T_3582 = mux(issue_sel_13, entries_ex[13].bits.cmd.cmd.status.mbe, UInt<1>(0h0)) node _issue_entry_T_3583 = mux(issue_sel_14, entries_ex[14].bits.cmd.cmd.status.mbe, UInt<1>(0h0)) node _issue_entry_T_3584 = mux(issue_sel_15, entries_ex[15].bits.cmd.cmd.status.mbe, UInt<1>(0h0)) node _issue_entry_T_3585 = or(_issue_entry_T_3569, _issue_entry_T_3570) node _issue_entry_T_3586 = or(_issue_entry_T_3585, _issue_entry_T_3571) node _issue_entry_T_3587 = or(_issue_entry_T_3586, _issue_entry_T_3572) node _issue_entry_T_3588 = or(_issue_entry_T_3587, _issue_entry_T_3573) node _issue_entry_T_3589 = or(_issue_entry_T_3588, _issue_entry_T_3574) node _issue_entry_T_3590 = or(_issue_entry_T_3589, _issue_entry_T_3575) node _issue_entry_T_3591 = or(_issue_entry_T_3590, _issue_entry_T_3576) node _issue_entry_T_3592 = or(_issue_entry_T_3591, _issue_entry_T_3577) node _issue_entry_T_3593 = or(_issue_entry_T_3592, _issue_entry_T_3578) node _issue_entry_T_3594 = or(_issue_entry_T_3593, _issue_entry_T_3579) node _issue_entry_T_3595 = or(_issue_entry_T_3594, _issue_entry_T_3580) node _issue_entry_T_3596 = or(_issue_entry_T_3595, _issue_entry_T_3581) node _issue_entry_T_3597 = or(_issue_entry_T_3596, _issue_entry_T_3582) node _issue_entry_T_3598 = or(_issue_entry_T_3597, _issue_entry_T_3583) node _issue_entry_T_3599 = or(_issue_entry_T_3598, _issue_entry_T_3584) wire _issue_entry_WIRE_208 : UInt<1> connect _issue_entry_WIRE_208, _issue_entry_T_3599 connect _issue_entry_WIRE_183.mbe, _issue_entry_WIRE_208 node _issue_entry_T_3600 = mux(issue_sel_0_1, entries_ex[0].bits.cmd.cmd.status.gva, UInt<1>(0h0)) node _issue_entry_T_3601 = mux(issue_sel_1_1, entries_ex[1].bits.cmd.cmd.status.gva, UInt<1>(0h0)) node _issue_entry_T_3602 = mux(issue_sel_2_1, entries_ex[2].bits.cmd.cmd.status.gva, UInt<1>(0h0)) node _issue_entry_T_3603 = mux(issue_sel_3_1, entries_ex[3].bits.cmd.cmd.status.gva, UInt<1>(0h0)) node _issue_entry_T_3604 = mux(issue_sel_4_1, entries_ex[4].bits.cmd.cmd.status.gva, UInt<1>(0h0)) node _issue_entry_T_3605 = mux(issue_sel_5_1, entries_ex[5].bits.cmd.cmd.status.gva, UInt<1>(0h0)) node _issue_entry_T_3606 = mux(issue_sel_6_1, entries_ex[6].bits.cmd.cmd.status.gva, UInt<1>(0h0)) node _issue_entry_T_3607 = mux(issue_sel_7_1, entries_ex[7].bits.cmd.cmd.status.gva, UInt<1>(0h0)) node _issue_entry_T_3608 = mux(issue_sel_8, entries_ex[8].bits.cmd.cmd.status.gva, UInt<1>(0h0)) node _issue_entry_T_3609 = mux(issue_sel_9, entries_ex[9].bits.cmd.cmd.status.gva, UInt<1>(0h0)) node _issue_entry_T_3610 = mux(issue_sel_10, entries_ex[10].bits.cmd.cmd.status.gva, UInt<1>(0h0)) node _issue_entry_T_3611 = mux(issue_sel_11, entries_ex[11].bits.cmd.cmd.status.gva, UInt<1>(0h0)) node _issue_entry_T_3612 = mux(issue_sel_12, entries_ex[12].bits.cmd.cmd.status.gva, UInt<1>(0h0)) node _issue_entry_T_3613 = mux(issue_sel_13, entries_ex[13].bits.cmd.cmd.status.gva, UInt<1>(0h0)) node _issue_entry_T_3614 = mux(issue_sel_14, entries_ex[14].bits.cmd.cmd.status.gva, UInt<1>(0h0)) node _issue_entry_T_3615 = mux(issue_sel_15, entries_ex[15].bits.cmd.cmd.status.gva, UInt<1>(0h0)) node _issue_entry_T_3616 = or(_issue_entry_T_3600, _issue_entry_T_3601) node _issue_entry_T_3617 = or(_issue_entry_T_3616, _issue_entry_T_3602) node _issue_entry_T_3618 = or(_issue_entry_T_3617, _issue_entry_T_3603) node _issue_entry_T_3619 = or(_issue_entry_T_3618, _issue_entry_T_3604) node _issue_entry_T_3620 = or(_issue_entry_T_3619, _issue_entry_T_3605) node _issue_entry_T_3621 = or(_issue_entry_T_3620, _issue_entry_T_3606) node _issue_entry_T_3622 = or(_issue_entry_T_3621, _issue_entry_T_3607) node _issue_entry_T_3623 = or(_issue_entry_T_3622, _issue_entry_T_3608) node _issue_entry_T_3624 = or(_issue_entry_T_3623, _issue_entry_T_3609) node _issue_entry_T_3625 = or(_issue_entry_T_3624, _issue_entry_T_3610) node _issue_entry_T_3626 = or(_issue_entry_T_3625, _issue_entry_T_3611) node _issue_entry_T_3627 = or(_issue_entry_T_3626, _issue_entry_T_3612) node _issue_entry_T_3628 = or(_issue_entry_T_3627, _issue_entry_T_3613) node _issue_entry_T_3629 = or(_issue_entry_T_3628, _issue_entry_T_3614) node _issue_entry_T_3630 = or(_issue_entry_T_3629, _issue_entry_T_3615) wire _issue_entry_WIRE_209 : UInt<1> connect _issue_entry_WIRE_209, _issue_entry_T_3630 connect _issue_entry_WIRE_183.gva, _issue_entry_WIRE_209 node _issue_entry_T_3631 = mux(issue_sel_0_1, entries_ex[0].bits.cmd.cmd.status.mpv, UInt<1>(0h0)) node _issue_entry_T_3632 = mux(issue_sel_1_1, entries_ex[1].bits.cmd.cmd.status.mpv, UInt<1>(0h0)) node _issue_entry_T_3633 = mux(issue_sel_2_1, entries_ex[2].bits.cmd.cmd.status.mpv, UInt<1>(0h0)) node _issue_entry_T_3634 = mux(issue_sel_3_1, entries_ex[3].bits.cmd.cmd.status.mpv, UInt<1>(0h0)) node _issue_entry_T_3635 = mux(issue_sel_4_1, entries_ex[4].bits.cmd.cmd.status.mpv, UInt<1>(0h0)) node _issue_entry_T_3636 = mux(issue_sel_5_1, entries_ex[5].bits.cmd.cmd.status.mpv, UInt<1>(0h0)) node _issue_entry_T_3637 = mux(issue_sel_6_1, entries_ex[6].bits.cmd.cmd.status.mpv, UInt<1>(0h0)) node _issue_entry_T_3638 = mux(issue_sel_7_1, entries_ex[7].bits.cmd.cmd.status.mpv, UInt<1>(0h0)) node _issue_entry_T_3639 = mux(issue_sel_8, entries_ex[8].bits.cmd.cmd.status.mpv, UInt<1>(0h0)) node _issue_entry_T_3640 = mux(issue_sel_9, entries_ex[9].bits.cmd.cmd.status.mpv, UInt<1>(0h0)) node _issue_entry_T_3641 = mux(issue_sel_10, entries_ex[10].bits.cmd.cmd.status.mpv, UInt<1>(0h0)) node _issue_entry_T_3642 = mux(issue_sel_11, entries_ex[11].bits.cmd.cmd.status.mpv, UInt<1>(0h0)) node _issue_entry_T_3643 = mux(issue_sel_12, entries_ex[12].bits.cmd.cmd.status.mpv, UInt<1>(0h0)) node _issue_entry_T_3644 = mux(issue_sel_13, entries_ex[13].bits.cmd.cmd.status.mpv, UInt<1>(0h0)) node _issue_entry_T_3645 = mux(issue_sel_14, entries_ex[14].bits.cmd.cmd.status.mpv, UInt<1>(0h0)) node _issue_entry_T_3646 = mux(issue_sel_15, entries_ex[15].bits.cmd.cmd.status.mpv, UInt<1>(0h0)) node _issue_entry_T_3647 = or(_issue_entry_T_3631, _issue_entry_T_3632) node _issue_entry_T_3648 = or(_issue_entry_T_3647, _issue_entry_T_3633) node _issue_entry_T_3649 = or(_issue_entry_T_3648, _issue_entry_T_3634) node _issue_entry_T_3650 = or(_issue_entry_T_3649, _issue_entry_T_3635) node _issue_entry_T_3651 = or(_issue_entry_T_3650, _issue_entry_T_3636) node _issue_entry_T_3652 = or(_issue_entry_T_3651, _issue_entry_T_3637) node _issue_entry_T_3653 = or(_issue_entry_T_3652, _issue_entry_T_3638) node _issue_entry_T_3654 = or(_issue_entry_T_3653, _issue_entry_T_3639) node _issue_entry_T_3655 = or(_issue_entry_T_3654, _issue_entry_T_3640) node _issue_entry_T_3656 = or(_issue_entry_T_3655, _issue_entry_T_3641) node _issue_entry_T_3657 = or(_issue_entry_T_3656, _issue_entry_T_3642) node _issue_entry_T_3658 = or(_issue_entry_T_3657, _issue_entry_T_3643) node _issue_entry_T_3659 = or(_issue_entry_T_3658, _issue_entry_T_3644) node _issue_entry_T_3660 = or(_issue_entry_T_3659, _issue_entry_T_3645) node _issue_entry_T_3661 = or(_issue_entry_T_3660, _issue_entry_T_3646) wire _issue_entry_WIRE_210 : UInt<1> connect _issue_entry_WIRE_210, _issue_entry_T_3661 connect _issue_entry_WIRE_183.mpv, _issue_entry_WIRE_210 node _issue_entry_T_3662 = mux(issue_sel_0_1, entries_ex[0].bits.cmd.cmd.status.zero2, UInt<1>(0h0)) node _issue_entry_T_3663 = mux(issue_sel_1_1, entries_ex[1].bits.cmd.cmd.status.zero2, UInt<1>(0h0)) node _issue_entry_T_3664 = mux(issue_sel_2_1, entries_ex[2].bits.cmd.cmd.status.zero2, UInt<1>(0h0)) node _issue_entry_T_3665 = mux(issue_sel_3_1, entries_ex[3].bits.cmd.cmd.status.zero2, UInt<1>(0h0)) node _issue_entry_T_3666 = mux(issue_sel_4_1, entries_ex[4].bits.cmd.cmd.status.zero2, UInt<1>(0h0)) node _issue_entry_T_3667 = mux(issue_sel_5_1, entries_ex[5].bits.cmd.cmd.status.zero2, UInt<1>(0h0)) node _issue_entry_T_3668 = mux(issue_sel_6_1, entries_ex[6].bits.cmd.cmd.status.zero2, UInt<1>(0h0)) node _issue_entry_T_3669 = mux(issue_sel_7_1, entries_ex[7].bits.cmd.cmd.status.zero2, UInt<1>(0h0)) node _issue_entry_T_3670 = mux(issue_sel_8, entries_ex[8].bits.cmd.cmd.status.zero2, UInt<1>(0h0)) node _issue_entry_T_3671 = mux(issue_sel_9, entries_ex[9].bits.cmd.cmd.status.zero2, UInt<1>(0h0)) node _issue_entry_T_3672 = mux(issue_sel_10, entries_ex[10].bits.cmd.cmd.status.zero2, UInt<1>(0h0)) node _issue_entry_T_3673 = mux(issue_sel_11, entries_ex[11].bits.cmd.cmd.status.zero2, UInt<1>(0h0)) node _issue_entry_T_3674 = mux(issue_sel_12, entries_ex[12].bits.cmd.cmd.status.zero2, UInt<1>(0h0)) node _issue_entry_T_3675 = mux(issue_sel_13, entries_ex[13].bits.cmd.cmd.status.zero2, UInt<1>(0h0)) node _issue_entry_T_3676 = mux(issue_sel_14, entries_ex[14].bits.cmd.cmd.status.zero2, UInt<1>(0h0)) node _issue_entry_T_3677 = mux(issue_sel_15, entries_ex[15].bits.cmd.cmd.status.zero2, UInt<1>(0h0)) node _issue_entry_T_3678 = or(_issue_entry_T_3662, _issue_entry_T_3663) node _issue_entry_T_3679 = or(_issue_entry_T_3678, _issue_entry_T_3664) node _issue_entry_T_3680 = or(_issue_entry_T_3679, _issue_entry_T_3665) node _issue_entry_T_3681 = or(_issue_entry_T_3680, _issue_entry_T_3666) node _issue_entry_T_3682 = or(_issue_entry_T_3681, _issue_entry_T_3667) node _issue_entry_T_3683 = or(_issue_entry_T_3682, _issue_entry_T_3668) node _issue_entry_T_3684 = or(_issue_entry_T_3683, _issue_entry_T_3669) node _issue_entry_T_3685 = or(_issue_entry_T_3684, _issue_entry_T_3670) node _issue_entry_T_3686 = or(_issue_entry_T_3685, _issue_entry_T_3671) node _issue_entry_T_3687 = or(_issue_entry_T_3686, _issue_entry_T_3672) node _issue_entry_T_3688 = or(_issue_entry_T_3687, _issue_entry_T_3673) node _issue_entry_T_3689 = or(_issue_entry_T_3688, _issue_entry_T_3674) node _issue_entry_T_3690 = or(_issue_entry_T_3689, _issue_entry_T_3675) node _issue_entry_T_3691 = or(_issue_entry_T_3690, _issue_entry_T_3676) node _issue_entry_T_3692 = or(_issue_entry_T_3691, _issue_entry_T_3677) wire _issue_entry_WIRE_211 : UInt<23> connect _issue_entry_WIRE_211, _issue_entry_T_3692 connect _issue_entry_WIRE_183.zero2, _issue_entry_WIRE_211 node _issue_entry_T_3693 = mux(issue_sel_0_1, entries_ex[0].bits.cmd.cmd.status.sd, UInt<1>(0h0)) node _issue_entry_T_3694 = mux(issue_sel_1_1, entries_ex[1].bits.cmd.cmd.status.sd, UInt<1>(0h0)) node _issue_entry_T_3695 = mux(issue_sel_2_1, entries_ex[2].bits.cmd.cmd.status.sd, UInt<1>(0h0)) node _issue_entry_T_3696 = mux(issue_sel_3_1, entries_ex[3].bits.cmd.cmd.status.sd, UInt<1>(0h0)) node _issue_entry_T_3697 = mux(issue_sel_4_1, entries_ex[4].bits.cmd.cmd.status.sd, UInt<1>(0h0)) node _issue_entry_T_3698 = mux(issue_sel_5_1, entries_ex[5].bits.cmd.cmd.status.sd, UInt<1>(0h0)) node _issue_entry_T_3699 = mux(issue_sel_6_1, entries_ex[6].bits.cmd.cmd.status.sd, UInt<1>(0h0)) node _issue_entry_T_3700 = mux(issue_sel_7_1, entries_ex[7].bits.cmd.cmd.status.sd, UInt<1>(0h0)) node _issue_entry_T_3701 = mux(issue_sel_8, entries_ex[8].bits.cmd.cmd.status.sd, UInt<1>(0h0)) node _issue_entry_T_3702 = mux(issue_sel_9, entries_ex[9].bits.cmd.cmd.status.sd, UInt<1>(0h0)) node _issue_entry_T_3703 = mux(issue_sel_10, entries_ex[10].bits.cmd.cmd.status.sd, UInt<1>(0h0)) node _issue_entry_T_3704 = mux(issue_sel_11, entries_ex[11].bits.cmd.cmd.status.sd, UInt<1>(0h0)) node _issue_entry_T_3705 = mux(issue_sel_12, entries_ex[12].bits.cmd.cmd.status.sd, UInt<1>(0h0)) node _issue_entry_T_3706 = mux(issue_sel_13, entries_ex[13].bits.cmd.cmd.status.sd, UInt<1>(0h0)) node _issue_entry_T_3707 = mux(issue_sel_14, entries_ex[14].bits.cmd.cmd.status.sd, UInt<1>(0h0)) node _issue_entry_T_3708 = mux(issue_sel_15, entries_ex[15].bits.cmd.cmd.status.sd, UInt<1>(0h0)) node _issue_entry_T_3709 = or(_issue_entry_T_3693, _issue_entry_T_3694) node _issue_entry_T_3710 = or(_issue_entry_T_3709, _issue_entry_T_3695) node _issue_entry_T_3711 = or(_issue_entry_T_3710, _issue_entry_T_3696) node _issue_entry_T_3712 = or(_issue_entry_T_3711, _issue_entry_T_3697) node _issue_entry_T_3713 = or(_issue_entry_T_3712, _issue_entry_T_3698) node _issue_entry_T_3714 = or(_issue_entry_T_3713, _issue_entry_T_3699) node _issue_entry_T_3715 = or(_issue_entry_T_3714, _issue_entry_T_3700) node _issue_entry_T_3716 = or(_issue_entry_T_3715, _issue_entry_T_3701) node _issue_entry_T_3717 = or(_issue_entry_T_3716, _issue_entry_T_3702) node _issue_entry_T_3718 = or(_issue_entry_T_3717, _issue_entry_T_3703) node _issue_entry_T_3719 = or(_issue_entry_T_3718, _issue_entry_T_3704) node _issue_entry_T_3720 = or(_issue_entry_T_3719, _issue_entry_T_3705) node _issue_entry_T_3721 = or(_issue_entry_T_3720, _issue_entry_T_3706) node _issue_entry_T_3722 = or(_issue_entry_T_3721, _issue_entry_T_3707) node _issue_entry_T_3723 = or(_issue_entry_T_3722, _issue_entry_T_3708) wire _issue_entry_WIRE_212 : UInt<1> connect _issue_entry_WIRE_212, _issue_entry_T_3723 connect _issue_entry_WIRE_183.sd, _issue_entry_WIRE_212 node _issue_entry_T_3724 = mux(issue_sel_0_1, entries_ex[0].bits.cmd.cmd.status.v, UInt<1>(0h0)) node _issue_entry_T_3725 = mux(issue_sel_1_1, entries_ex[1].bits.cmd.cmd.status.v, UInt<1>(0h0)) node _issue_entry_T_3726 = mux(issue_sel_2_1, entries_ex[2].bits.cmd.cmd.status.v, UInt<1>(0h0)) node _issue_entry_T_3727 = mux(issue_sel_3_1, entries_ex[3].bits.cmd.cmd.status.v, UInt<1>(0h0)) node _issue_entry_T_3728 = mux(issue_sel_4_1, entries_ex[4].bits.cmd.cmd.status.v, UInt<1>(0h0)) node _issue_entry_T_3729 = mux(issue_sel_5_1, entries_ex[5].bits.cmd.cmd.status.v, UInt<1>(0h0)) node _issue_entry_T_3730 = mux(issue_sel_6_1, entries_ex[6].bits.cmd.cmd.status.v, UInt<1>(0h0)) node _issue_entry_T_3731 = mux(issue_sel_7_1, entries_ex[7].bits.cmd.cmd.status.v, UInt<1>(0h0)) node _issue_entry_T_3732 = mux(issue_sel_8, entries_ex[8].bits.cmd.cmd.status.v, UInt<1>(0h0)) node _issue_entry_T_3733 = mux(issue_sel_9, entries_ex[9].bits.cmd.cmd.status.v, UInt<1>(0h0)) node _issue_entry_T_3734 = mux(issue_sel_10, entries_ex[10].bits.cmd.cmd.status.v, UInt<1>(0h0)) node _issue_entry_T_3735 = mux(issue_sel_11, entries_ex[11].bits.cmd.cmd.status.v, UInt<1>(0h0)) node _issue_entry_T_3736 = mux(issue_sel_12, entries_ex[12].bits.cmd.cmd.status.v, UInt<1>(0h0)) node _issue_entry_T_3737 = mux(issue_sel_13, entries_ex[13].bits.cmd.cmd.status.v, UInt<1>(0h0)) node _issue_entry_T_3738 = mux(issue_sel_14, entries_ex[14].bits.cmd.cmd.status.v, UInt<1>(0h0)) node _issue_entry_T_3739 = mux(issue_sel_15, entries_ex[15].bits.cmd.cmd.status.v, UInt<1>(0h0)) node _issue_entry_T_3740 = or(_issue_entry_T_3724, _issue_entry_T_3725) node _issue_entry_T_3741 = or(_issue_entry_T_3740, _issue_entry_T_3726) node _issue_entry_T_3742 = or(_issue_entry_T_3741, _issue_entry_T_3727) node _issue_entry_T_3743 = or(_issue_entry_T_3742, _issue_entry_T_3728) node _issue_entry_T_3744 = or(_issue_entry_T_3743, _issue_entry_T_3729) node _issue_entry_T_3745 = or(_issue_entry_T_3744, _issue_entry_T_3730) node _issue_entry_T_3746 = or(_issue_entry_T_3745, _issue_entry_T_3731) node _issue_entry_T_3747 = or(_issue_entry_T_3746, _issue_entry_T_3732) node _issue_entry_T_3748 = or(_issue_entry_T_3747, _issue_entry_T_3733) node _issue_entry_T_3749 = or(_issue_entry_T_3748, _issue_entry_T_3734) node _issue_entry_T_3750 = or(_issue_entry_T_3749, _issue_entry_T_3735) node _issue_entry_T_3751 = or(_issue_entry_T_3750, _issue_entry_T_3736) node _issue_entry_T_3752 = or(_issue_entry_T_3751, _issue_entry_T_3737) node _issue_entry_T_3753 = or(_issue_entry_T_3752, _issue_entry_T_3738) node _issue_entry_T_3754 = or(_issue_entry_T_3753, _issue_entry_T_3739) wire _issue_entry_WIRE_213 : UInt<1> connect _issue_entry_WIRE_213, _issue_entry_T_3754 connect _issue_entry_WIRE_183.v, _issue_entry_WIRE_213 node _issue_entry_T_3755 = mux(issue_sel_0_1, entries_ex[0].bits.cmd.cmd.status.prv, UInt<1>(0h0)) node _issue_entry_T_3756 = mux(issue_sel_1_1, entries_ex[1].bits.cmd.cmd.status.prv, UInt<1>(0h0)) node _issue_entry_T_3757 = mux(issue_sel_2_1, entries_ex[2].bits.cmd.cmd.status.prv, UInt<1>(0h0)) node _issue_entry_T_3758 = mux(issue_sel_3_1, entries_ex[3].bits.cmd.cmd.status.prv, UInt<1>(0h0)) node _issue_entry_T_3759 = mux(issue_sel_4_1, entries_ex[4].bits.cmd.cmd.status.prv, UInt<1>(0h0)) node _issue_entry_T_3760 = mux(issue_sel_5_1, entries_ex[5].bits.cmd.cmd.status.prv, UInt<1>(0h0)) node _issue_entry_T_3761 = mux(issue_sel_6_1, entries_ex[6].bits.cmd.cmd.status.prv, UInt<1>(0h0)) node _issue_entry_T_3762 = mux(issue_sel_7_1, entries_ex[7].bits.cmd.cmd.status.prv, UInt<1>(0h0)) node _issue_entry_T_3763 = mux(issue_sel_8, entries_ex[8].bits.cmd.cmd.status.prv, UInt<1>(0h0)) node _issue_entry_T_3764 = mux(issue_sel_9, entries_ex[9].bits.cmd.cmd.status.prv, UInt<1>(0h0)) node _issue_entry_T_3765 = mux(issue_sel_10, entries_ex[10].bits.cmd.cmd.status.prv, UInt<1>(0h0)) node _issue_entry_T_3766 = mux(issue_sel_11, entries_ex[11].bits.cmd.cmd.status.prv, UInt<1>(0h0)) node _issue_entry_T_3767 = mux(issue_sel_12, entries_ex[12].bits.cmd.cmd.status.prv, UInt<1>(0h0)) node _issue_entry_T_3768 = mux(issue_sel_13, entries_ex[13].bits.cmd.cmd.status.prv, UInt<1>(0h0)) node _issue_entry_T_3769 = mux(issue_sel_14, entries_ex[14].bits.cmd.cmd.status.prv, UInt<1>(0h0)) node _issue_entry_T_3770 = mux(issue_sel_15, entries_ex[15].bits.cmd.cmd.status.prv, UInt<1>(0h0)) node _issue_entry_T_3771 = or(_issue_entry_T_3755, _issue_entry_T_3756) node _issue_entry_T_3772 = or(_issue_entry_T_3771, _issue_entry_T_3757) node _issue_entry_T_3773 = or(_issue_entry_T_3772, _issue_entry_T_3758) node _issue_entry_T_3774 = or(_issue_entry_T_3773, _issue_entry_T_3759) node _issue_entry_T_3775 = or(_issue_entry_T_3774, _issue_entry_T_3760) node _issue_entry_T_3776 = or(_issue_entry_T_3775, _issue_entry_T_3761) node _issue_entry_T_3777 = or(_issue_entry_T_3776, _issue_entry_T_3762) node _issue_entry_T_3778 = or(_issue_entry_T_3777, _issue_entry_T_3763) node _issue_entry_T_3779 = or(_issue_entry_T_3778, _issue_entry_T_3764) node _issue_entry_T_3780 = or(_issue_entry_T_3779, _issue_entry_T_3765) node _issue_entry_T_3781 = or(_issue_entry_T_3780, _issue_entry_T_3766) node _issue_entry_T_3782 = or(_issue_entry_T_3781, _issue_entry_T_3767) node _issue_entry_T_3783 = or(_issue_entry_T_3782, _issue_entry_T_3768) node _issue_entry_T_3784 = or(_issue_entry_T_3783, _issue_entry_T_3769) node _issue_entry_T_3785 = or(_issue_entry_T_3784, _issue_entry_T_3770) wire _issue_entry_WIRE_214 : UInt<2> connect _issue_entry_WIRE_214, _issue_entry_T_3785 connect _issue_entry_WIRE_183.prv, _issue_entry_WIRE_214 node _issue_entry_T_3786 = mux(issue_sel_0_1, entries_ex[0].bits.cmd.cmd.status.dv, UInt<1>(0h0)) node _issue_entry_T_3787 = mux(issue_sel_1_1, entries_ex[1].bits.cmd.cmd.status.dv, UInt<1>(0h0)) node _issue_entry_T_3788 = mux(issue_sel_2_1, entries_ex[2].bits.cmd.cmd.status.dv, UInt<1>(0h0)) node _issue_entry_T_3789 = mux(issue_sel_3_1, entries_ex[3].bits.cmd.cmd.status.dv, UInt<1>(0h0)) node _issue_entry_T_3790 = mux(issue_sel_4_1, entries_ex[4].bits.cmd.cmd.status.dv, UInt<1>(0h0)) node _issue_entry_T_3791 = mux(issue_sel_5_1, entries_ex[5].bits.cmd.cmd.status.dv, UInt<1>(0h0)) node _issue_entry_T_3792 = mux(issue_sel_6_1, entries_ex[6].bits.cmd.cmd.status.dv, UInt<1>(0h0)) node _issue_entry_T_3793 = mux(issue_sel_7_1, entries_ex[7].bits.cmd.cmd.status.dv, UInt<1>(0h0)) node _issue_entry_T_3794 = mux(issue_sel_8, entries_ex[8].bits.cmd.cmd.status.dv, UInt<1>(0h0)) node _issue_entry_T_3795 = mux(issue_sel_9, entries_ex[9].bits.cmd.cmd.status.dv, UInt<1>(0h0)) node _issue_entry_T_3796 = mux(issue_sel_10, entries_ex[10].bits.cmd.cmd.status.dv, UInt<1>(0h0)) node _issue_entry_T_3797 = mux(issue_sel_11, entries_ex[11].bits.cmd.cmd.status.dv, UInt<1>(0h0)) node _issue_entry_T_3798 = mux(issue_sel_12, entries_ex[12].bits.cmd.cmd.status.dv, UInt<1>(0h0)) node _issue_entry_T_3799 = mux(issue_sel_13, entries_ex[13].bits.cmd.cmd.status.dv, UInt<1>(0h0)) node _issue_entry_T_3800 = mux(issue_sel_14, entries_ex[14].bits.cmd.cmd.status.dv, UInt<1>(0h0)) node _issue_entry_T_3801 = mux(issue_sel_15, entries_ex[15].bits.cmd.cmd.status.dv, UInt<1>(0h0)) node _issue_entry_T_3802 = or(_issue_entry_T_3786, _issue_entry_T_3787) node _issue_entry_T_3803 = or(_issue_entry_T_3802, _issue_entry_T_3788) node _issue_entry_T_3804 = or(_issue_entry_T_3803, _issue_entry_T_3789) node _issue_entry_T_3805 = or(_issue_entry_T_3804, _issue_entry_T_3790) node _issue_entry_T_3806 = or(_issue_entry_T_3805, _issue_entry_T_3791) node _issue_entry_T_3807 = or(_issue_entry_T_3806, _issue_entry_T_3792) node _issue_entry_T_3808 = or(_issue_entry_T_3807, _issue_entry_T_3793) node _issue_entry_T_3809 = or(_issue_entry_T_3808, _issue_entry_T_3794) node _issue_entry_T_3810 = or(_issue_entry_T_3809, _issue_entry_T_3795) node _issue_entry_T_3811 = or(_issue_entry_T_3810, _issue_entry_T_3796) node _issue_entry_T_3812 = or(_issue_entry_T_3811, _issue_entry_T_3797) node _issue_entry_T_3813 = or(_issue_entry_T_3812, _issue_entry_T_3798) node _issue_entry_T_3814 = or(_issue_entry_T_3813, _issue_entry_T_3799) node _issue_entry_T_3815 = or(_issue_entry_T_3814, _issue_entry_T_3800) node _issue_entry_T_3816 = or(_issue_entry_T_3815, _issue_entry_T_3801) wire _issue_entry_WIRE_215 : UInt<1> connect _issue_entry_WIRE_215, _issue_entry_T_3816 connect _issue_entry_WIRE_183.dv, _issue_entry_WIRE_215 node _issue_entry_T_3817 = mux(issue_sel_0_1, entries_ex[0].bits.cmd.cmd.status.dprv, UInt<1>(0h0)) node _issue_entry_T_3818 = mux(issue_sel_1_1, entries_ex[1].bits.cmd.cmd.status.dprv, UInt<1>(0h0)) node _issue_entry_T_3819 = mux(issue_sel_2_1, entries_ex[2].bits.cmd.cmd.status.dprv, UInt<1>(0h0)) node _issue_entry_T_3820 = mux(issue_sel_3_1, entries_ex[3].bits.cmd.cmd.status.dprv, UInt<1>(0h0)) node _issue_entry_T_3821 = mux(issue_sel_4_1, entries_ex[4].bits.cmd.cmd.status.dprv, UInt<1>(0h0)) node _issue_entry_T_3822 = mux(issue_sel_5_1, entries_ex[5].bits.cmd.cmd.status.dprv, UInt<1>(0h0)) node _issue_entry_T_3823 = mux(issue_sel_6_1, entries_ex[6].bits.cmd.cmd.status.dprv, UInt<1>(0h0)) node _issue_entry_T_3824 = mux(issue_sel_7_1, entries_ex[7].bits.cmd.cmd.status.dprv, UInt<1>(0h0)) node _issue_entry_T_3825 = mux(issue_sel_8, entries_ex[8].bits.cmd.cmd.status.dprv, UInt<1>(0h0)) node _issue_entry_T_3826 = mux(issue_sel_9, entries_ex[9].bits.cmd.cmd.status.dprv, UInt<1>(0h0)) node _issue_entry_T_3827 = mux(issue_sel_10, entries_ex[10].bits.cmd.cmd.status.dprv, UInt<1>(0h0)) node _issue_entry_T_3828 = mux(issue_sel_11, entries_ex[11].bits.cmd.cmd.status.dprv, UInt<1>(0h0)) node _issue_entry_T_3829 = mux(issue_sel_12, entries_ex[12].bits.cmd.cmd.status.dprv, UInt<1>(0h0)) node _issue_entry_T_3830 = mux(issue_sel_13, entries_ex[13].bits.cmd.cmd.status.dprv, UInt<1>(0h0)) node _issue_entry_T_3831 = mux(issue_sel_14, entries_ex[14].bits.cmd.cmd.status.dprv, UInt<1>(0h0)) node _issue_entry_T_3832 = mux(issue_sel_15, entries_ex[15].bits.cmd.cmd.status.dprv, UInt<1>(0h0)) node _issue_entry_T_3833 = or(_issue_entry_T_3817, _issue_entry_T_3818) node _issue_entry_T_3834 = or(_issue_entry_T_3833, _issue_entry_T_3819) node _issue_entry_T_3835 = or(_issue_entry_T_3834, _issue_entry_T_3820) node _issue_entry_T_3836 = or(_issue_entry_T_3835, _issue_entry_T_3821) node _issue_entry_T_3837 = or(_issue_entry_T_3836, _issue_entry_T_3822) node _issue_entry_T_3838 = or(_issue_entry_T_3837, _issue_entry_T_3823) node _issue_entry_T_3839 = or(_issue_entry_T_3838, _issue_entry_T_3824) node _issue_entry_T_3840 = or(_issue_entry_T_3839, _issue_entry_T_3825) node _issue_entry_T_3841 = or(_issue_entry_T_3840, _issue_entry_T_3826) node _issue_entry_T_3842 = or(_issue_entry_T_3841, _issue_entry_T_3827) node _issue_entry_T_3843 = or(_issue_entry_T_3842, _issue_entry_T_3828) node _issue_entry_T_3844 = or(_issue_entry_T_3843, _issue_entry_T_3829) node _issue_entry_T_3845 = or(_issue_entry_T_3844, _issue_entry_T_3830) node _issue_entry_T_3846 = or(_issue_entry_T_3845, _issue_entry_T_3831) node _issue_entry_T_3847 = or(_issue_entry_T_3846, _issue_entry_T_3832) wire _issue_entry_WIRE_216 : UInt<2> connect _issue_entry_WIRE_216, _issue_entry_T_3847 connect _issue_entry_WIRE_183.dprv, _issue_entry_WIRE_216 node _issue_entry_T_3848 = mux(issue_sel_0_1, entries_ex[0].bits.cmd.cmd.status.isa, UInt<1>(0h0)) node _issue_entry_T_3849 = mux(issue_sel_1_1, entries_ex[1].bits.cmd.cmd.status.isa, UInt<1>(0h0)) node _issue_entry_T_3850 = mux(issue_sel_2_1, entries_ex[2].bits.cmd.cmd.status.isa, UInt<1>(0h0)) node _issue_entry_T_3851 = mux(issue_sel_3_1, entries_ex[3].bits.cmd.cmd.status.isa, UInt<1>(0h0)) node _issue_entry_T_3852 = mux(issue_sel_4_1, entries_ex[4].bits.cmd.cmd.status.isa, UInt<1>(0h0)) node _issue_entry_T_3853 = mux(issue_sel_5_1, entries_ex[5].bits.cmd.cmd.status.isa, UInt<1>(0h0)) node _issue_entry_T_3854 = mux(issue_sel_6_1, entries_ex[6].bits.cmd.cmd.status.isa, UInt<1>(0h0)) node _issue_entry_T_3855 = mux(issue_sel_7_1, entries_ex[7].bits.cmd.cmd.status.isa, UInt<1>(0h0)) node _issue_entry_T_3856 = mux(issue_sel_8, entries_ex[8].bits.cmd.cmd.status.isa, UInt<1>(0h0)) node _issue_entry_T_3857 = mux(issue_sel_9, entries_ex[9].bits.cmd.cmd.status.isa, UInt<1>(0h0)) node _issue_entry_T_3858 = mux(issue_sel_10, entries_ex[10].bits.cmd.cmd.status.isa, UInt<1>(0h0)) node _issue_entry_T_3859 = mux(issue_sel_11, entries_ex[11].bits.cmd.cmd.status.isa, UInt<1>(0h0)) node _issue_entry_T_3860 = mux(issue_sel_12, entries_ex[12].bits.cmd.cmd.status.isa, UInt<1>(0h0)) node _issue_entry_T_3861 = mux(issue_sel_13, entries_ex[13].bits.cmd.cmd.status.isa, UInt<1>(0h0)) node _issue_entry_T_3862 = mux(issue_sel_14, entries_ex[14].bits.cmd.cmd.status.isa, UInt<1>(0h0)) node _issue_entry_T_3863 = mux(issue_sel_15, entries_ex[15].bits.cmd.cmd.status.isa, UInt<1>(0h0)) node _issue_entry_T_3864 = or(_issue_entry_T_3848, _issue_entry_T_3849) node _issue_entry_T_3865 = or(_issue_entry_T_3864, _issue_entry_T_3850) node _issue_entry_T_3866 = or(_issue_entry_T_3865, _issue_entry_T_3851) node _issue_entry_T_3867 = or(_issue_entry_T_3866, _issue_entry_T_3852) node _issue_entry_T_3868 = or(_issue_entry_T_3867, _issue_entry_T_3853) node _issue_entry_T_3869 = or(_issue_entry_T_3868, _issue_entry_T_3854) node _issue_entry_T_3870 = or(_issue_entry_T_3869, _issue_entry_T_3855) node _issue_entry_T_3871 = or(_issue_entry_T_3870, _issue_entry_T_3856) node _issue_entry_T_3872 = or(_issue_entry_T_3871, _issue_entry_T_3857) node _issue_entry_T_3873 = or(_issue_entry_T_3872, _issue_entry_T_3858) node _issue_entry_T_3874 = or(_issue_entry_T_3873, _issue_entry_T_3859) node _issue_entry_T_3875 = or(_issue_entry_T_3874, _issue_entry_T_3860) node _issue_entry_T_3876 = or(_issue_entry_T_3875, _issue_entry_T_3861) node _issue_entry_T_3877 = or(_issue_entry_T_3876, _issue_entry_T_3862) node _issue_entry_T_3878 = or(_issue_entry_T_3877, _issue_entry_T_3863) wire _issue_entry_WIRE_217 : UInt<32> connect _issue_entry_WIRE_217, _issue_entry_T_3878 connect _issue_entry_WIRE_183.isa, _issue_entry_WIRE_217 node _issue_entry_T_3879 = mux(issue_sel_0_1, entries_ex[0].bits.cmd.cmd.status.wfi, UInt<1>(0h0)) node _issue_entry_T_3880 = mux(issue_sel_1_1, entries_ex[1].bits.cmd.cmd.status.wfi, UInt<1>(0h0)) node _issue_entry_T_3881 = mux(issue_sel_2_1, entries_ex[2].bits.cmd.cmd.status.wfi, UInt<1>(0h0)) node _issue_entry_T_3882 = mux(issue_sel_3_1, entries_ex[3].bits.cmd.cmd.status.wfi, UInt<1>(0h0)) node _issue_entry_T_3883 = mux(issue_sel_4_1, entries_ex[4].bits.cmd.cmd.status.wfi, UInt<1>(0h0)) node _issue_entry_T_3884 = mux(issue_sel_5_1, entries_ex[5].bits.cmd.cmd.status.wfi, UInt<1>(0h0)) node _issue_entry_T_3885 = mux(issue_sel_6_1, entries_ex[6].bits.cmd.cmd.status.wfi, UInt<1>(0h0)) node _issue_entry_T_3886 = mux(issue_sel_7_1, entries_ex[7].bits.cmd.cmd.status.wfi, UInt<1>(0h0)) node _issue_entry_T_3887 = mux(issue_sel_8, entries_ex[8].bits.cmd.cmd.status.wfi, UInt<1>(0h0)) node _issue_entry_T_3888 = mux(issue_sel_9, entries_ex[9].bits.cmd.cmd.status.wfi, UInt<1>(0h0)) node _issue_entry_T_3889 = mux(issue_sel_10, entries_ex[10].bits.cmd.cmd.status.wfi, UInt<1>(0h0)) node _issue_entry_T_3890 = mux(issue_sel_11, entries_ex[11].bits.cmd.cmd.status.wfi, UInt<1>(0h0)) node _issue_entry_T_3891 = mux(issue_sel_12, entries_ex[12].bits.cmd.cmd.status.wfi, UInt<1>(0h0)) node _issue_entry_T_3892 = mux(issue_sel_13, entries_ex[13].bits.cmd.cmd.status.wfi, UInt<1>(0h0)) node _issue_entry_T_3893 = mux(issue_sel_14, entries_ex[14].bits.cmd.cmd.status.wfi, UInt<1>(0h0)) node _issue_entry_T_3894 = mux(issue_sel_15, entries_ex[15].bits.cmd.cmd.status.wfi, UInt<1>(0h0)) node _issue_entry_T_3895 = or(_issue_entry_T_3879, _issue_entry_T_3880) node _issue_entry_T_3896 = or(_issue_entry_T_3895, _issue_entry_T_3881) node _issue_entry_T_3897 = or(_issue_entry_T_3896, _issue_entry_T_3882) node _issue_entry_T_3898 = or(_issue_entry_T_3897, _issue_entry_T_3883) node _issue_entry_T_3899 = or(_issue_entry_T_3898, _issue_entry_T_3884) node _issue_entry_T_3900 = or(_issue_entry_T_3899, _issue_entry_T_3885) node _issue_entry_T_3901 = or(_issue_entry_T_3900, _issue_entry_T_3886) node _issue_entry_T_3902 = or(_issue_entry_T_3901, _issue_entry_T_3887) node _issue_entry_T_3903 = or(_issue_entry_T_3902, _issue_entry_T_3888) node _issue_entry_T_3904 = or(_issue_entry_T_3903, _issue_entry_T_3889) node _issue_entry_T_3905 = or(_issue_entry_T_3904, _issue_entry_T_3890) node _issue_entry_T_3906 = or(_issue_entry_T_3905, _issue_entry_T_3891) node _issue_entry_T_3907 = or(_issue_entry_T_3906, _issue_entry_T_3892) node _issue_entry_T_3908 = or(_issue_entry_T_3907, _issue_entry_T_3893) node _issue_entry_T_3909 = or(_issue_entry_T_3908, _issue_entry_T_3894) wire _issue_entry_WIRE_218 : UInt<1> connect _issue_entry_WIRE_218, _issue_entry_T_3909 connect _issue_entry_WIRE_183.wfi, _issue_entry_WIRE_218 node _issue_entry_T_3910 = mux(issue_sel_0_1, entries_ex[0].bits.cmd.cmd.status.cease, UInt<1>(0h0)) node _issue_entry_T_3911 = mux(issue_sel_1_1, entries_ex[1].bits.cmd.cmd.status.cease, UInt<1>(0h0)) node _issue_entry_T_3912 = mux(issue_sel_2_1, entries_ex[2].bits.cmd.cmd.status.cease, UInt<1>(0h0)) node _issue_entry_T_3913 = mux(issue_sel_3_1, entries_ex[3].bits.cmd.cmd.status.cease, UInt<1>(0h0)) node _issue_entry_T_3914 = mux(issue_sel_4_1, entries_ex[4].bits.cmd.cmd.status.cease, UInt<1>(0h0)) node _issue_entry_T_3915 = mux(issue_sel_5_1, entries_ex[5].bits.cmd.cmd.status.cease, UInt<1>(0h0)) node _issue_entry_T_3916 = mux(issue_sel_6_1, entries_ex[6].bits.cmd.cmd.status.cease, UInt<1>(0h0)) node _issue_entry_T_3917 = mux(issue_sel_7_1, entries_ex[7].bits.cmd.cmd.status.cease, UInt<1>(0h0)) node _issue_entry_T_3918 = mux(issue_sel_8, entries_ex[8].bits.cmd.cmd.status.cease, UInt<1>(0h0)) node _issue_entry_T_3919 = mux(issue_sel_9, entries_ex[9].bits.cmd.cmd.status.cease, UInt<1>(0h0)) node _issue_entry_T_3920 = mux(issue_sel_10, entries_ex[10].bits.cmd.cmd.status.cease, UInt<1>(0h0)) node _issue_entry_T_3921 = mux(issue_sel_11, entries_ex[11].bits.cmd.cmd.status.cease, UInt<1>(0h0)) node _issue_entry_T_3922 = mux(issue_sel_12, entries_ex[12].bits.cmd.cmd.status.cease, UInt<1>(0h0)) node _issue_entry_T_3923 = mux(issue_sel_13, entries_ex[13].bits.cmd.cmd.status.cease, UInt<1>(0h0)) node _issue_entry_T_3924 = mux(issue_sel_14, entries_ex[14].bits.cmd.cmd.status.cease, UInt<1>(0h0)) node _issue_entry_T_3925 = mux(issue_sel_15, entries_ex[15].bits.cmd.cmd.status.cease, UInt<1>(0h0)) node _issue_entry_T_3926 = or(_issue_entry_T_3910, _issue_entry_T_3911) node _issue_entry_T_3927 = or(_issue_entry_T_3926, _issue_entry_T_3912) node _issue_entry_T_3928 = or(_issue_entry_T_3927, _issue_entry_T_3913) node _issue_entry_T_3929 = or(_issue_entry_T_3928, _issue_entry_T_3914) node _issue_entry_T_3930 = or(_issue_entry_T_3929, _issue_entry_T_3915) node _issue_entry_T_3931 = or(_issue_entry_T_3930, _issue_entry_T_3916) node _issue_entry_T_3932 = or(_issue_entry_T_3931, _issue_entry_T_3917) node _issue_entry_T_3933 = or(_issue_entry_T_3932, _issue_entry_T_3918) node _issue_entry_T_3934 = or(_issue_entry_T_3933, _issue_entry_T_3919) node _issue_entry_T_3935 = or(_issue_entry_T_3934, _issue_entry_T_3920) node _issue_entry_T_3936 = or(_issue_entry_T_3935, _issue_entry_T_3921) node _issue_entry_T_3937 = or(_issue_entry_T_3936, _issue_entry_T_3922) node _issue_entry_T_3938 = or(_issue_entry_T_3937, _issue_entry_T_3923) node _issue_entry_T_3939 = or(_issue_entry_T_3938, _issue_entry_T_3924) node _issue_entry_T_3940 = or(_issue_entry_T_3939, _issue_entry_T_3925) wire _issue_entry_WIRE_219 : UInt<1> connect _issue_entry_WIRE_219, _issue_entry_T_3940 connect _issue_entry_WIRE_183.cease, _issue_entry_WIRE_219 node _issue_entry_T_3941 = mux(issue_sel_0_1, entries_ex[0].bits.cmd.cmd.status.debug, UInt<1>(0h0)) node _issue_entry_T_3942 = mux(issue_sel_1_1, entries_ex[1].bits.cmd.cmd.status.debug, UInt<1>(0h0)) node _issue_entry_T_3943 = mux(issue_sel_2_1, entries_ex[2].bits.cmd.cmd.status.debug, UInt<1>(0h0)) node _issue_entry_T_3944 = mux(issue_sel_3_1, entries_ex[3].bits.cmd.cmd.status.debug, UInt<1>(0h0)) node _issue_entry_T_3945 = mux(issue_sel_4_1, entries_ex[4].bits.cmd.cmd.status.debug, UInt<1>(0h0)) node _issue_entry_T_3946 = mux(issue_sel_5_1, entries_ex[5].bits.cmd.cmd.status.debug, UInt<1>(0h0)) node _issue_entry_T_3947 = mux(issue_sel_6_1, entries_ex[6].bits.cmd.cmd.status.debug, UInt<1>(0h0)) node _issue_entry_T_3948 = mux(issue_sel_7_1, entries_ex[7].bits.cmd.cmd.status.debug, UInt<1>(0h0)) node _issue_entry_T_3949 = mux(issue_sel_8, entries_ex[8].bits.cmd.cmd.status.debug, UInt<1>(0h0)) node _issue_entry_T_3950 = mux(issue_sel_9, entries_ex[9].bits.cmd.cmd.status.debug, UInt<1>(0h0)) node _issue_entry_T_3951 = mux(issue_sel_10, entries_ex[10].bits.cmd.cmd.status.debug, UInt<1>(0h0)) node _issue_entry_T_3952 = mux(issue_sel_11, entries_ex[11].bits.cmd.cmd.status.debug, UInt<1>(0h0)) node _issue_entry_T_3953 = mux(issue_sel_12, entries_ex[12].bits.cmd.cmd.status.debug, UInt<1>(0h0)) node _issue_entry_T_3954 = mux(issue_sel_13, entries_ex[13].bits.cmd.cmd.status.debug, UInt<1>(0h0)) node _issue_entry_T_3955 = mux(issue_sel_14, entries_ex[14].bits.cmd.cmd.status.debug, UInt<1>(0h0)) node _issue_entry_T_3956 = mux(issue_sel_15, entries_ex[15].bits.cmd.cmd.status.debug, UInt<1>(0h0)) node _issue_entry_T_3957 = or(_issue_entry_T_3941, _issue_entry_T_3942) node _issue_entry_T_3958 = or(_issue_entry_T_3957, _issue_entry_T_3943) node _issue_entry_T_3959 = or(_issue_entry_T_3958, _issue_entry_T_3944) node _issue_entry_T_3960 = or(_issue_entry_T_3959, _issue_entry_T_3945) node _issue_entry_T_3961 = or(_issue_entry_T_3960, _issue_entry_T_3946) node _issue_entry_T_3962 = or(_issue_entry_T_3961, _issue_entry_T_3947) node _issue_entry_T_3963 = or(_issue_entry_T_3962, _issue_entry_T_3948) node _issue_entry_T_3964 = or(_issue_entry_T_3963, _issue_entry_T_3949) node _issue_entry_T_3965 = or(_issue_entry_T_3964, _issue_entry_T_3950) node _issue_entry_T_3966 = or(_issue_entry_T_3965, _issue_entry_T_3951) node _issue_entry_T_3967 = or(_issue_entry_T_3966, _issue_entry_T_3952) node _issue_entry_T_3968 = or(_issue_entry_T_3967, _issue_entry_T_3953) node _issue_entry_T_3969 = or(_issue_entry_T_3968, _issue_entry_T_3954) node _issue_entry_T_3970 = or(_issue_entry_T_3969, _issue_entry_T_3955) node _issue_entry_T_3971 = or(_issue_entry_T_3970, _issue_entry_T_3956) wire _issue_entry_WIRE_220 : UInt<1> connect _issue_entry_WIRE_220, _issue_entry_T_3971 connect _issue_entry_WIRE_183.debug, _issue_entry_WIRE_220 connect _issue_entry_WIRE_182.status, _issue_entry_WIRE_183 node _issue_entry_T_3972 = mux(issue_sel_0_1, entries_ex[0].bits.cmd.cmd.rs2, UInt<1>(0h0)) node _issue_entry_T_3973 = mux(issue_sel_1_1, entries_ex[1].bits.cmd.cmd.rs2, UInt<1>(0h0)) node _issue_entry_T_3974 = mux(issue_sel_2_1, entries_ex[2].bits.cmd.cmd.rs2, UInt<1>(0h0)) node _issue_entry_T_3975 = mux(issue_sel_3_1, entries_ex[3].bits.cmd.cmd.rs2, UInt<1>(0h0)) node _issue_entry_T_3976 = mux(issue_sel_4_1, entries_ex[4].bits.cmd.cmd.rs2, UInt<1>(0h0)) node _issue_entry_T_3977 = mux(issue_sel_5_1, entries_ex[5].bits.cmd.cmd.rs2, UInt<1>(0h0)) node _issue_entry_T_3978 = mux(issue_sel_6_1, entries_ex[6].bits.cmd.cmd.rs2, UInt<1>(0h0)) node _issue_entry_T_3979 = mux(issue_sel_7_1, entries_ex[7].bits.cmd.cmd.rs2, UInt<1>(0h0)) node _issue_entry_T_3980 = mux(issue_sel_8, entries_ex[8].bits.cmd.cmd.rs2, UInt<1>(0h0)) node _issue_entry_T_3981 = mux(issue_sel_9, entries_ex[9].bits.cmd.cmd.rs2, UInt<1>(0h0)) node _issue_entry_T_3982 = mux(issue_sel_10, entries_ex[10].bits.cmd.cmd.rs2, UInt<1>(0h0)) node _issue_entry_T_3983 = mux(issue_sel_11, entries_ex[11].bits.cmd.cmd.rs2, UInt<1>(0h0)) node _issue_entry_T_3984 = mux(issue_sel_12, entries_ex[12].bits.cmd.cmd.rs2, UInt<1>(0h0)) node _issue_entry_T_3985 = mux(issue_sel_13, entries_ex[13].bits.cmd.cmd.rs2, UInt<1>(0h0)) node _issue_entry_T_3986 = mux(issue_sel_14, entries_ex[14].bits.cmd.cmd.rs2, UInt<1>(0h0)) node _issue_entry_T_3987 = mux(issue_sel_15, entries_ex[15].bits.cmd.cmd.rs2, UInt<1>(0h0)) node _issue_entry_T_3988 = or(_issue_entry_T_3972, _issue_entry_T_3973) node _issue_entry_T_3989 = or(_issue_entry_T_3988, _issue_entry_T_3974) node _issue_entry_T_3990 = or(_issue_entry_T_3989, _issue_entry_T_3975) node _issue_entry_T_3991 = or(_issue_entry_T_3990, _issue_entry_T_3976) node _issue_entry_T_3992 = or(_issue_entry_T_3991, _issue_entry_T_3977) node _issue_entry_T_3993 = or(_issue_entry_T_3992, _issue_entry_T_3978) node _issue_entry_T_3994 = or(_issue_entry_T_3993, _issue_entry_T_3979) node _issue_entry_T_3995 = or(_issue_entry_T_3994, _issue_entry_T_3980) node _issue_entry_T_3996 = or(_issue_entry_T_3995, _issue_entry_T_3981) node _issue_entry_T_3997 = or(_issue_entry_T_3996, _issue_entry_T_3982) node _issue_entry_T_3998 = or(_issue_entry_T_3997, _issue_entry_T_3983) node _issue_entry_T_3999 = or(_issue_entry_T_3998, _issue_entry_T_3984) node _issue_entry_T_4000 = or(_issue_entry_T_3999, _issue_entry_T_3985) node _issue_entry_T_4001 = or(_issue_entry_T_4000, _issue_entry_T_3986) node _issue_entry_T_4002 = or(_issue_entry_T_4001, _issue_entry_T_3987) wire _issue_entry_WIRE_221 : UInt<64> connect _issue_entry_WIRE_221, _issue_entry_T_4002 connect _issue_entry_WIRE_182.rs2, _issue_entry_WIRE_221 node _issue_entry_T_4003 = mux(issue_sel_0_1, entries_ex[0].bits.cmd.cmd.rs1, UInt<1>(0h0)) node _issue_entry_T_4004 = mux(issue_sel_1_1, entries_ex[1].bits.cmd.cmd.rs1, UInt<1>(0h0)) node _issue_entry_T_4005 = mux(issue_sel_2_1, entries_ex[2].bits.cmd.cmd.rs1, UInt<1>(0h0)) node _issue_entry_T_4006 = mux(issue_sel_3_1, entries_ex[3].bits.cmd.cmd.rs1, UInt<1>(0h0)) node _issue_entry_T_4007 = mux(issue_sel_4_1, entries_ex[4].bits.cmd.cmd.rs1, UInt<1>(0h0)) node _issue_entry_T_4008 = mux(issue_sel_5_1, entries_ex[5].bits.cmd.cmd.rs1, UInt<1>(0h0)) node _issue_entry_T_4009 = mux(issue_sel_6_1, entries_ex[6].bits.cmd.cmd.rs1, UInt<1>(0h0)) node _issue_entry_T_4010 = mux(issue_sel_7_1, entries_ex[7].bits.cmd.cmd.rs1, UInt<1>(0h0)) node _issue_entry_T_4011 = mux(issue_sel_8, entries_ex[8].bits.cmd.cmd.rs1, UInt<1>(0h0)) node _issue_entry_T_4012 = mux(issue_sel_9, entries_ex[9].bits.cmd.cmd.rs1, UInt<1>(0h0)) node _issue_entry_T_4013 = mux(issue_sel_10, entries_ex[10].bits.cmd.cmd.rs1, UInt<1>(0h0)) node _issue_entry_T_4014 = mux(issue_sel_11, entries_ex[11].bits.cmd.cmd.rs1, UInt<1>(0h0)) node _issue_entry_T_4015 = mux(issue_sel_12, entries_ex[12].bits.cmd.cmd.rs1, UInt<1>(0h0)) node _issue_entry_T_4016 = mux(issue_sel_13, entries_ex[13].bits.cmd.cmd.rs1, UInt<1>(0h0)) node _issue_entry_T_4017 = mux(issue_sel_14, entries_ex[14].bits.cmd.cmd.rs1, UInt<1>(0h0)) node _issue_entry_T_4018 = mux(issue_sel_15, entries_ex[15].bits.cmd.cmd.rs1, UInt<1>(0h0)) node _issue_entry_T_4019 = or(_issue_entry_T_4003, _issue_entry_T_4004) node _issue_entry_T_4020 = or(_issue_entry_T_4019, _issue_entry_T_4005) node _issue_entry_T_4021 = or(_issue_entry_T_4020, _issue_entry_T_4006) node _issue_entry_T_4022 = or(_issue_entry_T_4021, _issue_entry_T_4007) node _issue_entry_T_4023 = or(_issue_entry_T_4022, _issue_entry_T_4008) node _issue_entry_T_4024 = or(_issue_entry_T_4023, _issue_entry_T_4009) node _issue_entry_T_4025 = or(_issue_entry_T_4024, _issue_entry_T_4010) node _issue_entry_T_4026 = or(_issue_entry_T_4025, _issue_entry_T_4011) node _issue_entry_T_4027 = or(_issue_entry_T_4026, _issue_entry_T_4012) node _issue_entry_T_4028 = or(_issue_entry_T_4027, _issue_entry_T_4013) node _issue_entry_T_4029 = or(_issue_entry_T_4028, _issue_entry_T_4014) node _issue_entry_T_4030 = or(_issue_entry_T_4029, _issue_entry_T_4015) node _issue_entry_T_4031 = or(_issue_entry_T_4030, _issue_entry_T_4016) node _issue_entry_T_4032 = or(_issue_entry_T_4031, _issue_entry_T_4017) node _issue_entry_T_4033 = or(_issue_entry_T_4032, _issue_entry_T_4018) wire _issue_entry_WIRE_222 : UInt<64> connect _issue_entry_WIRE_222, _issue_entry_T_4033 connect _issue_entry_WIRE_182.rs1, _issue_entry_WIRE_222 wire _issue_entry_WIRE_223 : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>} node _issue_entry_T_4034 = mux(issue_sel_0_1, entries_ex[0].bits.cmd.cmd.inst.opcode, UInt<1>(0h0)) node _issue_entry_T_4035 = mux(issue_sel_1_1, entries_ex[1].bits.cmd.cmd.inst.opcode, UInt<1>(0h0)) node _issue_entry_T_4036 = mux(issue_sel_2_1, entries_ex[2].bits.cmd.cmd.inst.opcode, UInt<1>(0h0)) node _issue_entry_T_4037 = mux(issue_sel_3_1, entries_ex[3].bits.cmd.cmd.inst.opcode, UInt<1>(0h0)) node _issue_entry_T_4038 = mux(issue_sel_4_1, entries_ex[4].bits.cmd.cmd.inst.opcode, UInt<1>(0h0)) node _issue_entry_T_4039 = mux(issue_sel_5_1, entries_ex[5].bits.cmd.cmd.inst.opcode, UInt<1>(0h0)) node _issue_entry_T_4040 = mux(issue_sel_6_1, entries_ex[6].bits.cmd.cmd.inst.opcode, UInt<1>(0h0)) node _issue_entry_T_4041 = mux(issue_sel_7_1, entries_ex[7].bits.cmd.cmd.inst.opcode, UInt<1>(0h0)) node _issue_entry_T_4042 = mux(issue_sel_8, entries_ex[8].bits.cmd.cmd.inst.opcode, UInt<1>(0h0)) node _issue_entry_T_4043 = mux(issue_sel_9, entries_ex[9].bits.cmd.cmd.inst.opcode, UInt<1>(0h0)) node _issue_entry_T_4044 = mux(issue_sel_10, entries_ex[10].bits.cmd.cmd.inst.opcode, UInt<1>(0h0)) node _issue_entry_T_4045 = mux(issue_sel_11, entries_ex[11].bits.cmd.cmd.inst.opcode, UInt<1>(0h0)) node _issue_entry_T_4046 = mux(issue_sel_12, entries_ex[12].bits.cmd.cmd.inst.opcode, UInt<1>(0h0)) node _issue_entry_T_4047 = mux(issue_sel_13, entries_ex[13].bits.cmd.cmd.inst.opcode, UInt<1>(0h0)) node _issue_entry_T_4048 = mux(issue_sel_14, entries_ex[14].bits.cmd.cmd.inst.opcode, UInt<1>(0h0)) node _issue_entry_T_4049 = mux(issue_sel_15, entries_ex[15].bits.cmd.cmd.inst.opcode, UInt<1>(0h0)) node _issue_entry_T_4050 = or(_issue_entry_T_4034, _issue_entry_T_4035) node _issue_entry_T_4051 = or(_issue_entry_T_4050, _issue_entry_T_4036) node _issue_entry_T_4052 = or(_issue_entry_T_4051, _issue_entry_T_4037) node _issue_entry_T_4053 = or(_issue_entry_T_4052, _issue_entry_T_4038) node _issue_entry_T_4054 = or(_issue_entry_T_4053, _issue_entry_T_4039) node _issue_entry_T_4055 = or(_issue_entry_T_4054, _issue_entry_T_4040) node _issue_entry_T_4056 = or(_issue_entry_T_4055, _issue_entry_T_4041) node _issue_entry_T_4057 = or(_issue_entry_T_4056, _issue_entry_T_4042) node _issue_entry_T_4058 = or(_issue_entry_T_4057, _issue_entry_T_4043) node _issue_entry_T_4059 = or(_issue_entry_T_4058, _issue_entry_T_4044) node _issue_entry_T_4060 = or(_issue_entry_T_4059, _issue_entry_T_4045) node _issue_entry_T_4061 = or(_issue_entry_T_4060, _issue_entry_T_4046) node _issue_entry_T_4062 = or(_issue_entry_T_4061, _issue_entry_T_4047) node _issue_entry_T_4063 = or(_issue_entry_T_4062, _issue_entry_T_4048) node _issue_entry_T_4064 = or(_issue_entry_T_4063, _issue_entry_T_4049) wire _issue_entry_WIRE_224 : UInt<7> connect _issue_entry_WIRE_224, _issue_entry_T_4064 connect _issue_entry_WIRE_223.opcode, _issue_entry_WIRE_224 node _issue_entry_T_4065 = mux(issue_sel_0_1, entries_ex[0].bits.cmd.cmd.inst.rd, UInt<1>(0h0)) node _issue_entry_T_4066 = mux(issue_sel_1_1, entries_ex[1].bits.cmd.cmd.inst.rd, UInt<1>(0h0)) node _issue_entry_T_4067 = mux(issue_sel_2_1, entries_ex[2].bits.cmd.cmd.inst.rd, UInt<1>(0h0)) node _issue_entry_T_4068 = mux(issue_sel_3_1, entries_ex[3].bits.cmd.cmd.inst.rd, UInt<1>(0h0)) node _issue_entry_T_4069 = mux(issue_sel_4_1, entries_ex[4].bits.cmd.cmd.inst.rd, UInt<1>(0h0)) node _issue_entry_T_4070 = mux(issue_sel_5_1, entries_ex[5].bits.cmd.cmd.inst.rd, UInt<1>(0h0)) node _issue_entry_T_4071 = mux(issue_sel_6_1, entries_ex[6].bits.cmd.cmd.inst.rd, UInt<1>(0h0)) node _issue_entry_T_4072 = mux(issue_sel_7_1, entries_ex[7].bits.cmd.cmd.inst.rd, UInt<1>(0h0)) node _issue_entry_T_4073 = mux(issue_sel_8, entries_ex[8].bits.cmd.cmd.inst.rd, UInt<1>(0h0)) node _issue_entry_T_4074 = mux(issue_sel_9, entries_ex[9].bits.cmd.cmd.inst.rd, UInt<1>(0h0)) node _issue_entry_T_4075 = mux(issue_sel_10, entries_ex[10].bits.cmd.cmd.inst.rd, UInt<1>(0h0)) node _issue_entry_T_4076 = mux(issue_sel_11, entries_ex[11].bits.cmd.cmd.inst.rd, UInt<1>(0h0)) node _issue_entry_T_4077 = mux(issue_sel_12, entries_ex[12].bits.cmd.cmd.inst.rd, UInt<1>(0h0)) node _issue_entry_T_4078 = mux(issue_sel_13, entries_ex[13].bits.cmd.cmd.inst.rd, UInt<1>(0h0)) node _issue_entry_T_4079 = mux(issue_sel_14, entries_ex[14].bits.cmd.cmd.inst.rd, UInt<1>(0h0)) node _issue_entry_T_4080 = mux(issue_sel_15, entries_ex[15].bits.cmd.cmd.inst.rd, UInt<1>(0h0)) node _issue_entry_T_4081 = or(_issue_entry_T_4065, _issue_entry_T_4066) node _issue_entry_T_4082 = or(_issue_entry_T_4081, _issue_entry_T_4067) node _issue_entry_T_4083 = or(_issue_entry_T_4082, _issue_entry_T_4068) node _issue_entry_T_4084 = or(_issue_entry_T_4083, _issue_entry_T_4069) node _issue_entry_T_4085 = or(_issue_entry_T_4084, _issue_entry_T_4070) node _issue_entry_T_4086 = or(_issue_entry_T_4085, _issue_entry_T_4071) node _issue_entry_T_4087 = or(_issue_entry_T_4086, _issue_entry_T_4072) node _issue_entry_T_4088 = or(_issue_entry_T_4087, _issue_entry_T_4073) node _issue_entry_T_4089 = or(_issue_entry_T_4088, _issue_entry_T_4074) node _issue_entry_T_4090 = or(_issue_entry_T_4089, _issue_entry_T_4075) node _issue_entry_T_4091 = or(_issue_entry_T_4090, _issue_entry_T_4076) node _issue_entry_T_4092 = or(_issue_entry_T_4091, _issue_entry_T_4077) node _issue_entry_T_4093 = or(_issue_entry_T_4092, _issue_entry_T_4078) node _issue_entry_T_4094 = or(_issue_entry_T_4093, _issue_entry_T_4079) node _issue_entry_T_4095 = or(_issue_entry_T_4094, _issue_entry_T_4080) wire _issue_entry_WIRE_225 : UInt<5> connect _issue_entry_WIRE_225, _issue_entry_T_4095 connect _issue_entry_WIRE_223.rd, _issue_entry_WIRE_225 node _issue_entry_T_4096 = mux(issue_sel_0_1, entries_ex[0].bits.cmd.cmd.inst.xs2, UInt<1>(0h0)) node _issue_entry_T_4097 = mux(issue_sel_1_1, entries_ex[1].bits.cmd.cmd.inst.xs2, UInt<1>(0h0)) node _issue_entry_T_4098 = mux(issue_sel_2_1, entries_ex[2].bits.cmd.cmd.inst.xs2, UInt<1>(0h0)) node _issue_entry_T_4099 = mux(issue_sel_3_1, entries_ex[3].bits.cmd.cmd.inst.xs2, UInt<1>(0h0)) node _issue_entry_T_4100 = mux(issue_sel_4_1, entries_ex[4].bits.cmd.cmd.inst.xs2, UInt<1>(0h0)) node _issue_entry_T_4101 = mux(issue_sel_5_1, entries_ex[5].bits.cmd.cmd.inst.xs2, UInt<1>(0h0)) node _issue_entry_T_4102 = mux(issue_sel_6_1, entries_ex[6].bits.cmd.cmd.inst.xs2, UInt<1>(0h0)) node _issue_entry_T_4103 = mux(issue_sel_7_1, entries_ex[7].bits.cmd.cmd.inst.xs2, UInt<1>(0h0)) node _issue_entry_T_4104 = mux(issue_sel_8, entries_ex[8].bits.cmd.cmd.inst.xs2, UInt<1>(0h0)) node _issue_entry_T_4105 = mux(issue_sel_9, entries_ex[9].bits.cmd.cmd.inst.xs2, UInt<1>(0h0)) node _issue_entry_T_4106 = mux(issue_sel_10, entries_ex[10].bits.cmd.cmd.inst.xs2, UInt<1>(0h0)) node _issue_entry_T_4107 = mux(issue_sel_11, entries_ex[11].bits.cmd.cmd.inst.xs2, UInt<1>(0h0)) node _issue_entry_T_4108 = mux(issue_sel_12, entries_ex[12].bits.cmd.cmd.inst.xs2, UInt<1>(0h0)) node _issue_entry_T_4109 = mux(issue_sel_13, entries_ex[13].bits.cmd.cmd.inst.xs2, UInt<1>(0h0)) node _issue_entry_T_4110 = mux(issue_sel_14, entries_ex[14].bits.cmd.cmd.inst.xs2, UInt<1>(0h0)) node _issue_entry_T_4111 = mux(issue_sel_15, entries_ex[15].bits.cmd.cmd.inst.xs2, UInt<1>(0h0)) node _issue_entry_T_4112 = or(_issue_entry_T_4096, _issue_entry_T_4097) node _issue_entry_T_4113 = or(_issue_entry_T_4112, _issue_entry_T_4098) node _issue_entry_T_4114 = or(_issue_entry_T_4113, _issue_entry_T_4099) node _issue_entry_T_4115 = or(_issue_entry_T_4114, _issue_entry_T_4100) node _issue_entry_T_4116 = or(_issue_entry_T_4115, _issue_entry_T_4101) node _issue_entry_T_4117 = or(_issue_entry_T_4116, _issue_entry_T_4102) node _issue_entry_T_4118 = or(_issue_entry_T_4117, _issue_entry_T_4103) node _issue_entry_T_4119 = or(_issue_entry_T_4118, _issue_entry_T_4104) node _issue_entry_T_4120 = or(_issue_entry_T_4119, _issue_entry_T_4105) node _issue_entry_T_4121 = or(_issue_entry_T_4120, _issue_entry_T_4106) node _issue_entry_T_4122 = or(_issue_entry_T_4121, _issue_entry_T_4107) node _issue_entry_T_4123 = or(_issue_entry_T_4122, _issue_entry_T_4108) node _issue_entry_T_4124 = or(_issue_entry_T_4123, _issue_entry_T_4109) node _issue_entry_T_4125 = or(_issue_entry_T_4124, _issue_entry_T_4110) node _issue_entry_T_4126 = or(_issue_entry_T_4125, _issue_entry_T_4111) wire _issue_entry_WIRE_226 : UInt<1> connect _issue_entry_WIRE_226, _issue_entry_T_4126 connect _issue_entry_WIRE_223.xs2, _issue_entry_WIRE_226 node _issue_entry_T_4127 = mux(issue_sel_0_1, entries_ex[0].bits.cmd.cmd.inst.xs1, UInt<1>(0h0)) node _issue_entry_T_4128 = mux(issue_sel_1_1, entries_ex[1].bits.cmd.cmd.inst.xs1, UInt<1>(0h0)) node _issue_entry_T_4129 = mux(issue_sel_2_1, entries_ex[2].bits.cmd.cmd.inst.xs1, UInt<1>(0h0)) node _issue_entry_T_4130 = mux(issue_sel_3_1, entries_ex[3].bits.cmd.cmd.inst.xs1, UInt<1>(0h0)) node _issue_entry_T_4131 = mux(issue_sel_4_1, entries_ex[4].bits.cmd.cmd.inst.xs1, UInt<1>(0h0)) node _issue_entry_T_4132 = mux(issue_sel_5_1, entries_ex[5].bits.cmd.cmd.inst.xs1, UInt<1>(0h0)) node _issue_entry_T_4133 = mux(issue_sel_6_1, entries_ex[6].bits.cmd.cmd.inst.xs1, UInt<1>(0h0)) node _issue_entry_T_4134 = mux(issue_sel_7_1, entries_ex[7].bits.cmd.cmd.inst.xs1, UInt<1>(0h0)) node _issue_entry_T_4135 = mux(issue_sel_8, entries_ex[8].bits.cmd.cmd.inst.xs1, UInt<1>(0h0)) node _issue_entry_T_4136 = mux(issue_sel_9, entries_ex[9].bits.cmd.cmd.inst.xs1, UInt<1>(0h0)) node _issue_entry_T_4137 = mux(issue_sel_10, entries_ex[10].bits.cmd.cmd.inst.xs1, UInt<1>(0h0)) node _issue_entry_T_4138 = mux(issue_sel_11, entries_ex[11].bits.cmd.cmd.inst.xs1, UInt<1>(0h0)) node _issue_entry_T_4139 = mux(issue_sel_12, entries_ex[12].bits.cmd.cmd.inst.xs1, UInt<1>(0h0)) node _issue_entry_T_4140 = mux(issue_sel_13, entries_ex[13].bits.cmd.cmd.inst.xs1, UInt<1>(0h0)) node _issue_entry_T_4141 = mux(issue_sel_14, entries_ex[14].bits.cmd.cmd.inst.xs1, UInt<1>(0h0)) node _issue_entry_T_4142 = mux(issue_sel_15, entries_ex[15].bits.cmd.cmd.inst.xs1, UInt<1>(0h0)) node _issue_entry_T_4143 = or(_issue_entry_T_4127, _issue_entry_T_4128) node _issue_entry_T_4144 = or(_issue_entry_T_4143, _issue_entry_T_4129) node _issue_entry_T_4145 = or(_issue_entry_T_4144, _issue_entry_T_4130) node _issue_entry_T_4146 = or(_issue_entry_T_4145, _issue_entry_T_4131) node _issue_entry_T_4147 = or(_issue_entry_T_4146, _issue_entry_T_4132) node _issue_entry_T_4148 = or(_issue_entry_T_4147, _issue_entry_T_4133) node _issue_entry_T_4149 = or(_issue_entry_T_4148, _issue_entry_T_4134) node _issue_entry_T_4150 = or(_issue_entry_T_4149, _issue_entry_T_4135) node _issue_entry_T_4151 = or(_issue_entry_T_4150, _issue_entry_T_4136) node _issue_entry_T_4152 = or(_issue_entry_T_4151, _issue_entry_T_4137) node _issue_entry_T_4153 = or(_issue_entry_T_4152, _issue_entry_T_4138) node _issue_entry_T_4154 = or(_issue_entry_T_4153, _issue_entry_T_4139) node _issue_entry_T_4155 = or(_issue_entry_T_4154, _issue_entry_T_4140) node _issue_entry_T_4156 = or(_issue_entry_T_4155, _issue_entry_T_4141) node _issue_entry_T_4157 = or(_issue_entry_T_4156, _issue_entry_T_4142) wire _issue_entry_WIRE_227 : UInt<1> connect _issue_entry_WIRE_227, _issue_entry_T_4157 connect _issue_entry_WIRE_223.xs1, _issue_entry_WIRE_227 node _issue_entry_T_4158 = mux(issue_sel_0_1, entries_ex[0].bits.cmd.cmd.inst.xd, UInt<1>(0h0)) node _issue_entry_T_4159 = mux(issue_sel_1_1, entries_ex[1].bits.cmd.cmd.inst.xd, UInt<1>(0h0)) node _issue_entry_T_4160 = mux(issue_sel_2_1, entries_ex[2].bits.cmd.cmd.inst.xd, UInt<1>(0h0)) node _issue_entry_T_4161 = mux(issue_sel_3_1, entries_ex[3].bits.cmd.cmd.inst.xd, UInt<1>(0h0)) node _issue_entry_T_4162 = mux(issue_sel_4_1, entries_ex[4].bits.cmd.cmd.inst.xd, UInt<1>(0h0)) node _issue_entry_T_4163 = mux(issue_sel_5_1, entries_ex[5].bits.cmd.cmd.inst.xd, UInt<1>(0h0)) node _issue_entry_T_4164 = mux(issue_sel_6_1, entries_ex[6].bits.cmd.cmd.inst.xd, UInt<1>(0h0)) node _issue_entry_T_4165 = mux(issue_sel_7_1, entries_ex[7].bits.cmd.cmd.inst.xd, UInt<1>(0h0)) node _issue_entry_T_4166 = mux(issue_sel_8, entries_ex[8].bits.cmd.cmd.inst.xd, UInt<1>(0h0)) node _issue_entry_T_4167 = mux(issue_sel_9, entries_ex[9].bits.cmd.cmd.inst.xd, UInt<1>(0h0)) node _issue_entry_T_4168 = mux(issue_sel_10, entries_ex[10].bits.cmd.cmd.inst.xd, UInt<1>(0h0)) node _issue_entry_T_4169 = mux(issue_sel_11, entries_ex[11].bits.cmd.cmd.inst.xd, UInt<1>(0h0)) node _issue_entry_T_4170 = mux(issue_sel_12, entries_ex[12].bits.cmd.cmd.inst.xd, UInt<1>(0h0)) node _issue_entry_T_4171 = mux(issue_sel_13, entries_ex[13].bits.cmd.cmd.inst.xd, UInt<1>(0h0)) node _issue_entry_T_4172 = mux(issue_sel_14, entries_ex[14].bits.cmd.cmd.inst.xd, UInt<1>(0h0)) node _issue_entry_T_4173 = mux(issue_sel_15, entries_ex[15].bits.cmd.cmd.inst.xd, UInt<1>(0h0)) node _issue_entry_T_4174 = or(_issue_entry_T_4158, _issue_entry_T_4159) node _issue_entry_T_4175 = or(_issue_entry_T_4174, _issue_entry_T_4160) node _issue_entry_T_4176 = or(_issue_entry_T_4175, _issue_entry_T_4161) node _issue_entry_T_4177 = or(_issue_entry_T_4176, _issue_entry_T_4162) node _issue_entry_T_4178 = or(_issue_entry_T_4177, _issue_entry_T_4163) node _issue_entry_T_4179 = or(_issue_entry_T_4178, _issue_entry_T_4164) node _issue_entry_T_4180 = or(_issue_entry_T_4179, _issue_entry_T_4165) node _issue_entry_T_4181 = or(_issue_entry_T_4180, _issue_entry_T_4166) node _issue_entry_T_4182 = or(_issue_entry_T_4181, _issue_entry_T_4167) node _issue_entry_T_4183 = or(_issue_entry_T_4182, _issue_entry_T_4168) node _issue_entry_T_4184 = or(_issue_entry_T_4183, _issue_entry_T_4169) node _issue_entry_T_4185 = or(_issue_entry_T_4184, _issue_entry_T_4170) node _issue_entry_T_4186 = or(_issue_entry_T_4185, _issue_entry_T_4171) node _issue_entry_T_4187 = or(_issue_entry_T_4186, _issue_entry_T_4172) node _issue_entry_T_4188 = or(_issue_entry_T_4187, _issue_entry_T_4173) wire _issue_entry_WIRE_228 : UInt<1> connect _issue_entry_WIRE_228, _issue_entry_T_4188 connect _issue_entry_WIRE_223.xd, _issue_entry_WIRE_228 node _issue_entry_T_4189 = mux(issue_sel_0_1, entries_ex[0].bits.cmd.cmd.inst.rs1, UInt<1>(0h0)) node _issue_entry_T_4190 = mux(issue_sel_1_1, entries_ex[1].bits.cmd.cmd.inst.rs1, UInt<1>(0h0)) node _issue_entry_T_4191 = mux(issue_sel_2_1, entries_ex[2].bits.cmd.cmd.inst.rs1, UInt<1>(0h0)) node _issue_entry_T_4192 = mux(issue_sel_3_1, entries_ex[3].bits.cmd.cmd.inst.rs1, UInt<1>(0h0)) node _issue_entry_T_4193 = mux(issue_sel_4_1, entries_ex[4].bits.cmd.cmd.inst.rs1, UInt<1>(0h0)) node _issue_entry_T_4194 = mux(issue_sel_5_1, entries_ex[5].bits.cmd.cmd.inst.rs1, UInt<1>(0h0)) node _issue_entry_T_4195 = mux(issue_sel_6_1, entries_ex[6].bits.cmd.cmd.inst.rs1, UInt<1>(0h0)) node _issue_entry_T_4196 = mux(issue_sel_7_1, entries_ex[7].bits.cmd.cmd.inst.rs1, UInt<1>(0h0)) node _issue_entry_T_4197 = mux(issue_sel_8, entries_ex[8].bits.cmd.cmd.inst.rs1, UInt<1>(0h0)) node _issue_entry_T_4198 = mux(issue_sel_9, entries_ex[9].bits.cmd.cmd.inst.rs1, UInt<1>(0h0)) node _issue_entry_T_4199 = mux(issue_sel_10, entries_ex[10].bits.cmd.cmd.inst.rs1, UInt<1>(0h0)) node _issue_entry_T_4200 = mux(issue_sel_11, entries_ex[11].bits.cmd.cmd.inst.rs1, UInt<1>(0h0)) node _issue_entry_T_4201 = mux(issue_sel_12, entries_ex[12].bits.cmd.cmd.inst.rs1, UInt<1>(0h0)) node _issue_entry_T_4202 = mux(issue_sel_13, entries_ex[13].bits.cmd.cmd.inst.rs1, UInt<1>(0h0)) node _issue_entry_T_4203 = mux(issue_sel_14, entries_ex[14].bits.cmd.cmd.inst.rs1, UInt<1>(0h0)) node _issue_entry_T_4204 = mux(issue_sel_15, entries_ex[15].bits.cmd.cmd.inst.rs1, UInt<1>(0h0)) node _issue_entry_T_4205 = or(_issue_entry_T_4189, _issue_entry_T_4190) node _issue_entry_T_4206 = or(_issue_entry_T_4205, _issue_entry_T_4191) node _issue_entry_T_4207 = or(_issue_entry_T_4206, _issue_entry_T_4192) node _issue_entry_T_4208 = or(_issue_entry_T_4207, _issue_entry_T_4193) node _issue_entry_T_4209 = or(_issue_entry_T_4208, _issue_entry_T_4194) node _issue_entry_T_4210 = or(_issue_entry_T_4209, _issue_entry_T_4195) node _issue_entry_T_4211 = or(_issue_entry_T_4210, _issue_entry_T_4196) node _issue_entry_T_4212 = or(_issue_entry_T_4211, _issue_entry_T_4197) node _issue_entry_T_4213 = or(_issue_entry_T_4212, _issue_entry_T_4198) node _issue_entry_T_4214 = or(_issue_entry_T_4213, _issue_entry_T_4199) node _issue_entry_T_4215 = or(_issue_entry_T_4214, _issue_entry_T_4200) node _issue_entry_T_4216 = or(_issue_entry_T_4215, _issue_entry_T_4201) node _issue_entry_T_4217 = or(_issue_entry_T_4216, _issue_entry_T_4202) node _issue_entry_T_4218 = or(_issue_entry_T_4217, _issue_entry_T_4203) node _issue_entry_T_4219 = or(_issue_entry_T_4218, _issue_entry_T_4204) wire _issue_entry_WIRE_229 : UInt<5> connect _issue_entry_WIRE_229, _issue_entry_T_4219 connect _issue_entry_WIRE_223.rs1, _issue_entry_WIRE_229 node _issue_entry_T_4220 = mux(issue_sel_0_1, entries_ex[0].bits.cmd.cmd.inst.rs2, UInt<1>(0h0)) node _issue_entry_T_4221 = mux(issue_sel_1_1, entries_ex[1].bits.cmd.cmd.inst.rs2, UInt<1>(0h0)) node _issue_entry_T_4222 = mux(issue_sel_2_1, entries_ex[2].bits.cmd.cmd.inst.rs2, UInt<1>(0h0)) node _issue_entry_T_4223 = mux(issue_sel_3_1, entries_ex[3].bits.cmd.cmd.inst.rs2, UInt<1>(0h0)) node _issue_entry_T_4224 = mux(issue_sel_4_1, entries_ex[4].bits.cmd.cmd.inst.rs2, UInt<1>(0h0)) node _issue_entry_T_4225 = mux(issue_sel_5_1, entries_ex[5].bits.cmd.cmd.inst.rs2, UInt<1>(0h0)) node _issue_entry_T_4226 = mux(issue_sel_6_1, entries_ex[6].bits.cmd.cmd.inst.rs2, UInt<1>(0h0)) node _issue_entry_T_4227 = mux(issue_sel_7_1, entries_ex[7].bits.cmd.cmd.inst.rs2, UInt<1>(0h0)) node _issue_entry_T_4228 = mux(issue_sel_8, entries_ex[8].bits.cmd.cmd.inst.rs2, UInt<1>(0h0)) node _issue_entry_T_4229 = mux(issue_sel_9, entries_ex[9].bits.cmd.cmd.inst.rs2, UInt<1>(0h0)) node _issue_entry_T_4230 = mux(issue_sel_10, entries_ex[10].bits.cmd.cmd.inst.rs2, UInt<1>(0h0)) node _issue_entry_T_4231 = mux(issue_sel_11, entries_ex[11].bits.cmd.cmd.inst.rs2, UInt<1>(0h0)) node _issue_entry_T_4232 = mux(issue_sel_12, entries_ex[12].bits.cmd.cmd.inst.rs2, UInt<1>(0h0)) node _issue_entry_T_4233 = mux(issue_sel_13, entries_ex[13].bits.cmd.cmd.inst.rs2, UInt<1>(0h0)) node _issue_entry_T_4234 = mux(issue_sel_14, entries_ex[14].bits.cmd.cmd.inst.rs2, UInt<1>(0h0)) node _issue_entry_T_4235 = mux(issue_sel_15, entries_ex[15].bits.cmd.cmd.inst.rs2, UInt<1>(0h0)) node _issue_entry_T_4236 = or(_issue_entry_T_4220, _issue_entry_T_4221) node _issue_entry_T_4237 = or(_issue_entry_T_4236, _issue_entry_T_4222) node _issue_entry_T_4238 = or(_issue_entry_T_4237, _issue_entry_T_4223) node _issue_entry_T_4239 = or(_issue_entry_T_4238, _issue_entry_T_4224) node _issue_entry_T_4240 = or(_issue_entry_T_4239, _issue_entry_T_4225) node _issue_entry_T_4241 = or(_issue_entry_T_4240, _issue_entry_T_4226) node _issue_entry_T_4242 = or(_issue_entry_T_4241, _issue_entry_T_4227) node _issue_entry_T_4243 = or(_issue_entry_T_4242, _issue_entry_T_4228) node _issue_entry_T_4244 = or(_issue_entry_T_4243, _issue_entry_T_4229) node _issue_entry_T_4245 = or(_issue_entry_T_4244, _issue_entry_T_4230) node _issue_entry_T_4246 = or(_issue_entry_T_4245, _issue_entry_T_4231) node _issue_entry_T_4247 = or(_issue_entry_T_4246, _issue_entry_T_4232) node _issue_entry_T_4248 = or(_issue_entry_T_4247, _issue_entry_T_4233) node _issue_entry_T_4249 = or(_issue_entry_T_4248, _issue_entry_T_4234) node _issue_entry_T_4250 = or(_issue_entry_T_4249, _issue_entry_T_4235) wire _issue_entry_WIRE_230 : UInt<5> connect _issue_entry_WIRE_230, _issue_entry_T_4250 connect _issue_entry_WIRE_223.rs2, _issue_entry_WIRE_230 node _issue_entry_T_4251 = mux(issue_sel_0_1, entries_ex[0].bits.cmd.cmd.inst.funct, UInt<1>(0h0)) node _issue_entry_T_4252 = mux(issue_sel_1_1, entries_ex[1].bits.cmd.cmd.inst.funct, UInt<1>(0h0)) node _issue_entry_T_4253 = mux(issue_sel_2_1, entries_ex[2].bits.cmd.cmd.inst.funct, UInt<1>(0h0)) node _issue_entry_T_4254 = mux(issue_sel_3_1, entries_ex[3].bits.cmd.cmd.inst.funct, UInt<1>(0h0)) node _issue_entry_T_4255 = mux(issue_sel_4_1, entries_ex[4].bits.cmd.cmd.inst.funct, UInt<1>(0h0)) node _issue_entry_T_4256 = mux(issue_sel_5_1, entries_ex[5].bits.cmd.cmd.inst.funct, UInt<1>(0h0)) node _issue_entry_T_4257 = mux(issue_sel_6_1, entries_ex[6].bits.cmd.cmd.inst.funct, UInt<1>(0h0)) node _issue_entry_T_4258 = mux(issue_sel_7_1, entries_ex[7].bits.cmd.cmd.inst.funct, UInt<1>(0h0)) node _issue_entry_T_4259 = mux(issue_sel_8, entries_ex[8].bits.cmd.cmd.inst.funct, UInt<1>(0h0)) node _issue_entry_T_4260 = mux(issue_sel_9, entries_ex[9].bits.cmd.cmd.inst.funct, UInt<1>(0h0)) node _issue_entry_T_4261 = mux(issue_sel_10, entries_ex[10].bits.cmd.cmd.inst.funct, UInt<1>(0h0)) node _issue_entry_T_4262 = mux(issue_sel_11, entries_ex[11].bits.cmd.cmd.inst.funct, UInt<1>(0h0)) node _issue_entry_T_4263 = mux(issue_sel_12, entries_ex[12].bits.cmd.cmd.inst.funct, UInt<1>(0h0)) node _issue_entry_T_4264 = mux(issue_sel_13, entries_ex[13].bits.cmd.cmd.inst.funct, UInt<1>(0h0)) node _issue_entry_T_4265 = mux(issue_sel_14, entries_ex[14].bits.cmd.cmd.inst.funct, UInt<1>(0h0)) node _issue_entry_T_4266 = mux(issue_sel_15, entries_ex[15].bits.cmd.cmd.inst.funct, UInt<1>(0h0)) node _issue_entry_T_4267 = or(_issue_entry_T_4251, _issue_entry_T_4252) node _issue_entry_T_4268 = or(_issue_entry_T_4267, _issue_entry_T_4253) node _issue_entry_T_4269 = or(_issue_entry_T_4268, _issue_entry_T_4254) node _issue_entry_T_4270 = or(_issue_entry_T_4269, _issue_entry_T_4255) node _issue_entry_T_4271 = or(_issue_entry_T_4270, _issue_entry_T_4256) node _issue_entry_T_4272 = or(_issue_entry_T_4271, _issue_entry_T_4257) node _issue_entry_T_4273 = or(_issue_entry_T_4272, _issue_entry_T_4258) node _issue_entry_T_4274 = or(_issue_entry_T_4273, _issue_entry_T_4259) node _issue_entry_T_4275 = or(_issue_entry_T_4274, _issue_entry_T_4260) node _issue_entry_T_4276 = or(_issue_entry_T_4275, _issue_entry_T_4261) node _issue_entry_T_4277 = or(_issue_entry_T_4276, _issue_entry_T_4262) node _issue_entry_T_4278 = or(_issue_entry_T_4277, _issue_entry_T_4263) node _issue_entry_T_4279 = or(_issue_entry_T_4278, _issue_entry_T_4264) node _issue_entry_T_4280 = or(_issue_entry_T_4279, _issue_entry_T_4265) node _issue_entry_T_4281 = or(_issue_entry_T_4280, _issue_entry_T_4266) wire _issue_entry_WIRE_231 : UInt<7> connect _issue_entry_WIRE_231, _issue_entry_T_4281 connect _issue_entry_WIRE_223.funct, _issue_entry_WIRE_231 connect _issue_entry_WIRE_182.inst, _issue_entry_WIRE_223 connect _issue_entry_WIRE_176.cmd, _issue_entry_WIRE_182 connect _issue_entry_WIRE_143.cmd, _issue_entry_WIRE_176 node _issue_entry_T_4282 = mux(issue_sel_0_1, entries_ex[0].bits.complete_on_issue, UInt<1>(0h0)) node _issue_entry_T_4283 = mux(issue_sel_1_1, entries_ex[1].bits.complete_on_issue, UInt<1>(0h0)) node _issue_entry_T_4284 = mux(issue_sel_2_1, entries_ex[2].bits.complete_on_issue, UInt<1>(0h0)) node _issue_entry_T_4285 = mux(issue_sel_3_1, entries_ex[3].bits.complete_on_issue, UInt<1>(0h0)) node _issue_entry_T_4286 = mux(issue_sel_4_1, entries_ex[4].bits.complete_on_issue, UInt<1>(0h0)) node _issue_entry_T_4287 = mux(issue_sel_5_1, entries_ex[5].bits.complete_on_issue, UInt<1>(0h0)) node _issue_entry_T_4288 = mux(issue_sel_6_1, entries_ex[6].bits.complete_on_issue, UInt<1>(0h0)) node _issue_entry_T_4289 = mux(issue_sel_7_1, entries_ex[7].bits.complete_on_issue, UInt<1>(0h0)) node _issue_entry_T_4290 = mux(issue_sel_8, entries_ex[8].bits.complete_on_issue, UInt<1>(0h0)) node _issue_entry_T_4291 = mux(issue_sel_9, entries_ex[9].bits.complete_on_issue, UInt<1>(0h0)) node _issue_entry_T_4292 = mux(issue_sel_10, entries_ex[10].bits.complete_on_issue, UInt<1>(0h0)) node _issue_entry_T_4293 = mux(issue_sel_11, entries_ex[11].bits.complete_on_issue, UInt<1>(0h0)) node _issue_entry_T_4294 = mux(issue_sel_12, entries_ex[12].bits.complete_on_issue, UInt<1>(0h0)) node _issue_entry_T_4295 = mux(issue_sel_13, entries_ex[13].bits.complete_on_issue, UInt<1>(0h0)) node _issue_entry_T_4296 = mux(issue_sel_14, entries_ex[14].bits.complete_on_issue, UInt<1>(0h0)) node _issue_entry_T_4297 = mux(issue_sel_15, entries_ex[15].bits.complete_on_issue, UInt<1>(0h0)) node _issue_entry_T_4298 = or(_issue_entry_T_4282, _issue_entry_T_4283) node _issue_entry_T_4299 = or(_issue_entry_T_4298, _issue_entry_T_4284) node _issue_entry_T_4300 = or(_issue_entry_T_4299, _issue_entry_T_4285) node _issue_entry_T_4301 = or(_issue_entry_T_4300, _issue_entry_T_4286) node _issue_entry_T_4302 = or(_issue_entry_T_4301, _issue_entry_T_4287) node _issue_entry_T_4303 = or(_issue_entry_T_4302, _issue_entry_T_4288) node _issue_entry_T_4304 = or(_issue_entry_T_4303, _issue_entry_T_4289) node _issue_entry_T_4305 = or(_issue_entry_T_4304, _issue_entry_T_4290) node _issue_entry_T_4306 = or(_issue_entry_T_4305, _issue_entry_T_4291) node _issue_entry_T_4307 = or(_issue_entry_T_4306, _issue_entry_T_4292) node _issue_entry_T_4308 = or(_issue_entry_T_4307, _issue_entry_T_4293) node _issue_entry_T_4309 = or(_issue_entry_T_4308, _issue_entry_T_4294) node _issue_entry_T_4310 = or(_issue_entry_T_4309, _issue_entry_T_4295) node _issue_entry_T_4311 = or(_issue_entry_T_4310, _issue_entry_T_4296) node _issue_entry_T_4312 = or(_issue_entry_T_4311, _issue_entry_T_4297) wire _issue_entry_WIRE_232 : UInt<1> connect _issue_entry_WIRE_232, _issue_entry_T_4312 connect _issue_entry_WIRE_143.complete_on_issue, _issue_entry_WIRE_232 node _issue_entry_T_4313 = mux(issue_sel_0_1, entries_ex[0].bits.issued, UInt<1>(0h0)) node _issue_entry_T_4314 = mux(issue_sel_1_1, entries_ex[1].bits.issued, UInt<1>(0h0)) node _issue_entry_T_4315 = mux(issue_sel_2_1, entries_ex[2].bits.issued, UInt<1>(0h0)) node _issue_entry_T_4316 = mux(issue_sel_3_1, entries_ex[3].bits.issued, UInt<1>(0h0)) node _issue_entry_T_4317 = mux(issue_sel_4_1, entries_ex[4].bits.issued, UInt<1>(0h0)) node _issue_entry_T_4318 = mux(issue_sel_5_1, entries_ex[5].bits.issued, UInt<1>(0h0)) node _issue_entry_T_4319 = mux(issue_sel_6_1, entries_ex[6].bits.issued, UInt<1>(0h0)) node _issue_entry_T_4320 = mux(issue_sel_7_1, entries_ex[7].bits.issued, UInt<1>(0h0)) node _issue_entry_T_4321 = mux(issue_sel_8, entries_ex[8].bits.issued, UInt<1>(0h0)) node _issue_entry_T_4322 = mux(issue_sel_9, entries_ex[9].bits.issued, UInt<1>(0h0)) node _issue_entry_T_4323 = mux(issue_sel_10, entries_ex[10].bits.issued, UInt<1>(0h0)) node _issue_entry_T_4324 = mux(issue_sel_11, entries_ex[11].bits.issued, UInt<1>(0h0)) node _issue_entry_T_4325 = mux(issue_sel_12, entries_ex[12].bits.issued, UInt<1>(0h0)) node _issue_entry_T_4326 = mux(issue_sel_13, entries_ex[13].bits.issued, UInt<1>(0h0)) node _issue_entry_T_4327 = mux(issue_sel_14, entries_ex[14].bits.issued, UInt<1>(0h0)) node _issue_entry_T_4328 = mux(issue_sel_15, entries_ex[15].bits.issued, UInt<1>(0h0)) node _issue_entry_T_4329 = or(_issue_entry_T_4313, _issue_entry_T_4314) node _issue_entry_T_4330 = or(_issue_entry_T_4329, _issue_entry_T_4315) node _issue_entry_T_4331 = or(_issue_entry_T_4330, _issue_entry_T_4316) node _issue_entry_T_4332 = or(_issue_entry_T_4331, _issue_entry_T_4317) node _issue_entry_T_4333 = or(_issue_entry_T_4332, _issue_entry_T_4318) node _issue_entry_T_4334 = or(_issue_entry_T_4333, _issue_entry_T_4319) node _issue_entry_T_4335 = or(_issue_entry_T_4334, _issue_entry_T_4320) node _issue_entry_T_4336 = or(_issue_entry_T_4335, _issue_entry_T_4321) node _issue_entry_T_4337 = or(_issue_entry_T_4336, _issue_entry_T_4322) node _issue_entry_T_4338 = or(_issue_entry_T_4337, _issue_entry_T_4323) node _issue_entry_T_4339 = or(_issue_entry_T_4338, _issue_entry_T_4324) node _issue_entry_T_4340 = or(_issue_entry_T_4339, _issue_entry_T_4325) node _issue_entry_T_4341 = or(_issue_entry_T_4340, _issue_entry_T_4326) node _issue_entry_T_4342 = or(_issue_entry_T_4341, _issue_entry_T_4327) node _issue_entry_T_4343 = or(_issue_entry_T_4342, _issue_entry_T_4328) wire _issue_entry_WIRE_233 : UInt<1> connect _issue_entry_WIRE_233, _issue_entry_T_4343 connect _issue_entry_WIRE_143.issued, _issue_entry_WIRE_233 wire _issue_entry_WIRE_234 : { valid : UInt<1>, bits : { start : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, end : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, wraps_around : UInt<1>}} wire _issue_entry_WIRE_235 : { start : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, end : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, wraps_around : UInt<1>} node _issue_entry_T_4344 = mux(issue_sel_0_1, entries_ex[0].bits.opb.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_4345 = mux(issue_sel_1_1, entries_ex[1].bits.opb.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_4346 = mux(issue_sel_2_1, entries_ex[2].bits.opb.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_4347 = mux(issue_sel_3_1, entries_ex[3].bits.opb.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_4348 = mux(issue_sel_4_1, entries_ex[4].bits.opb.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_4349 = mux(issue_sel_5_1, entries_ex[5].bits.opb.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_4350 = mux(issue_sel_6_1, entries_ex[6].bits.opb.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_4351 = mux(issue_sel_7_1, entries_ex[7].bits.opb.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_4352 = mux(issue_sel_8, entries_ex[8].bits.opb.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_4353 = mux(issue_sel_9, entries_ex[9].bits.opb.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_4354 = mux(issue_sel_10, entries_ex[10].bits.opb.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_4355 = mux(issue_sel_11, entries_ex[11].bits.opb.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_4356 = mux(issue_sel_12, entries_ex[12].bits.opb.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_4357 = mux(issue_sel_13, entries_ex[13].bits.opb.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_4358 = mux(issue_sel_14, entries_ex[14].bits.opb.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_4359 = mux(issue_sel_15, entries_ex[15].bits.opb.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_4360 = or(_issue_entry_T_4344, _issue_entry_T_4345) node _issue_entry_T_4361 = or(_issue_entry_T_4360, _issue_entry_T_4346) node _issue_entry_T_4362 = or(_issue_entry_T_4361, _issue_entry_T_4347) node _issue_entry_T_4363 = or(_issue_entry_T_4362, _issue_entry_T_4348) node _issue_entry_T_4364 = or(_issue_entry_T_4363, _issue_entry_T_4349) node _issue_entry_T_4365 = or(_issue_entry_T_4364, _issue_entry_T_4350) node _issue_entry_T_4366 = or(_issue_entry_T_4365, _issue_entry_T_4351) node _issue_entry_T_4367 = or(_issue_entry_T_4366, _issue_entry_T_4352) node _issue_entry_T_4368 = or(_issue_entry_T_4367, _issue_entry_T_4353) node _issue_entry_T_4369 = or(_issue_entry_T_4368, _issue_entry_T_4354) node _issue_entry_T_4370 = or(_issue_entry_T_4369, _issue_entry_T_4355) node _issue_entry_T_4371 = or(_issue_entry_T_4370, _issue_entry_T_4356) node _issue_entry_T_4372 = or(_issue_entry_T_4371, _issue_entry_T_4357) node _issue_entry_T_4373 = or(_issue_entry_T_4372, _issue_entry_T_4358) node _issue_entry_T_4374 = or(_issue_entry_T_4373, _issue_entry_T_4359) wire _issue_entry_WIRE_236 : UInt<1> connect _issue_entry_WIRE_236, _issue_entry_T_4374 connect _issue_entry_WIRE_235.wraps_around, _issue_entry_WIRE_236 wire _issue_entry_WIRE_237 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} node _issue_entry_T_4375 = mux(issue_sel_0_1, entries_ex[0].bits.opb.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_4376 = mux(issue_sel_1_1, entries_ex[1].bits.opb.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_4377 = mux(issue_sel_2_1, entries_ex[2].bits.opb.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_4378 = mux(issue_sel_3_1, entries_ex[3].bits.opb.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_4379 = mux(issue_sel_4_1, entries_ex[4].bits.opb.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_4380 = mux(issue_sel_5_1, entries_ex[5].bits.opb.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_4381 = mux(issue_sel_6_1, entries_ex[6].bits.opb.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_4382 = mux(issue_sel_7_1, entries_ex[7].bits.opb.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_4383 = mux(issue_sel_8, entries_ex[8].bits.opb.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_4384 = mux(issue_sel_9, entries_ex[9].bits.opb.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_4385 = mux(issue_sel_10, entries_ex[10].bits.opb.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_4386 = mux(issue_sel_11, entries_ex[11].bits.opb.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_4387 = mux(issue_sel_12, entries_ex[12].bits.opb.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_4388 = mux(issue_sel_13, entries_ex[13].bits.opb.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_4389 = mux(issue_sel_14, entries_ex[14].bits.opb.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_4390 = mux(issue_sel_15, entries_ex[15].bits.opb.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_4391 = or(_issue_entry_T_4375, _issue_entry_T_4376) node _issue_entry_T_4392 = or(_issue_entry_T_4391, _issue_entry_T_4377) node _issue_entry_T_4393 = or(_issue_entry_T_4392, _issue_entry_T_4378) node _issue_entry_T_4394 = or(_issue_entry_T_4393, _issue_entry_T_4379) node _issue_entry_T_4395 = or(_issue_entry_T_4394, _issue_entry_T_4380) node _issue_entry_T_4396 = or(_issue_entry_T_4395, _issue_entry_T_4381) node _issue_entry_T_4397 = or(_issue_entry_T_4396, _issue_entry_T_4382) node _issue_entry_T_4398 = or(_issue_entry_T_4397, _issue_entry_T_4383) node _issue_entry_T_4399 = or(_issue_entry_T_4398, _issue_entry_T_4384) node _issue_entry_T_4400 = or(_issue_entry_T_4399, _issue_entry_T_4385) node _issue_entry_T_4401 = or(_issue_entry_T_4400, _issue_entry_T_4386) node _issue_entry_T_4402 = or(_issue_entry_T_4401, _issue_entry_T_4387) node _issue_entry_T_4403 = or(_issue_entry_T_4402, _issue_entry_T_4388) node _issue_entry_T_4404 = or(_issue_entry_T_4403, _issue_entry_T_4389) node _issue_entry_T_4405 = or(_issue_entry_T_4404, _issue_entry_T_4390) wire _issue_entry_WIRE_238 : UInt<14> connect _issue_entry_WIRE_238, _issue_entry_T_4405 connect _issue_entry_WIRE_237.data, _issue_entry_WIRE_238 node _issue_entry_T_4406 = mux(issue_sel_0_1, entries_ex[0].bits.opb.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_4407 = mux(issue_sel_1_1, entries_ex[1].bits.opb.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_4408 = mux(issue_sel_2_1, entries_ex[2].bits.opb.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_4409 = mux(issue_sel_3_1, entries_ex[3].bits.opb.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_4410 = mux(issue_sel_4_1, entries_ex[4].bits.opb.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_4411 = mux(issue_sel_5_1, entries_ex[5].bits.opb.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_4412 = mux(issue_sel_6_1, entries_ex[6].bits.opb.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_4413 = mux(issue_sel_7_1, entries_ex[7].bits.opb.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_4414 = mux(issue_sel_8, entries_ex[8].bits.opb.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_4415 = mux(issue_sel_9, entries_ex[9].bits.opb.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_4416 = mux(issue_sel_10, entries_ex[10].bits.opb.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_4417 = mux(issue_sel_11, entries_ex[11].bits.opb.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_4418 = mux(issue_sel_12, entries_ex[12].bits.opb.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_4419 = mux(issue_sel_13, entries_ex[13].bits.opb.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_4420 = mux(issue_sel_14, entries_ex[14].bits.opb.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_4421 = mux(issue_sel_15, entries_ex[15].bits.opb.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_4422 = or(_issue_entry_T_4406, _issue_entry_T_4407) node _issue_entry_T_4423 = or(_issue_entry_T_4422, _issue_entry_T_4408) node _issue_entry_T_4424 = or(_issue_entry_T_4423, _issue_entry_T_4409) node _issue_entry_T_4425 = or(_issue_entry_T_4424, _issue_entry_T_4410) node _issue_entry_T_4426 = or(_issue_entry_T_4425, _issue_entry_T_4411) node _issue_entry_T_4427 = or(_issue_entry_T_4426, _issue_entry_T_4412) node _issue_entry_T_4428 = or(_issue_entry_T_4427, _issue_entry_T_4413) node _issue_entry_T_4429 = or(_issue_entry_T_4428, _issue_entry_T_4414) node _issue_entry_T_4430 = or(_issue_entry_T_4429, _issue_entry_T_4415) node _issue_entry_T_4431 = or(_issue_entry_T_4430, _issue_entry_T_4416) node _issue_entry_T_4432 = or(_issue_entry_T_4431, _issue_entry_T_4417) node _issue_entry_T_4433 = or(_issue_entry_T_4432, _issue_entry_T_4418) node _issue_entry_T_4434 = or(_issue_entry_T_4433, _issue_entry_T_4419) node _issue_entry_T_4435 = or(_issue_entry_T_4434, _issue_entry_T_4420) node _issue_entry_T_4436 = or(_issue_entry_T_4435, _issue_entry_T_4421) wire _issue_entry_WIRE_239 : UInt<1> connect _issue_entry_WIRE_239, _issue_entry_T_4436 connect _issue_entry_WIRE_237.garbage_bit, _issue_entry_WIRE_239 node _issue_entry_T_4437 = mux(issue_sel_0_1, entries_ex[0].bits.opb.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_4438 = mux(issue_sel_1_1, entries_ex[1].bits.opb.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_4439 = mux(issue_sel_2_1, entries_ex[2].bits.opb.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_4440 = mux(issue_sel_3_1, entries_ex[3].bits.opb.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_4441 = mux(issue_sel_4_1, entries_ex[4].bits.opb.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_4442 = mux(issue_sel_5_1, entries_ex[5].bits.opb.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_4443 = mux(issue_sel_6_1, entries_ex[6].bits.opb.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_4444 = mux(issue_sel_7_1, entries_ex[7].bits.opb.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_4445 = mux(issue_sel_8, entries_ex[8].bits.opb.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_4446 = mux(issue_sel_9, entries_ex[9].bits.opb.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_4447 = mux(issue_sel_10, entries_ex[10].bits.opb.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_4448 = mux(issue_sel_11, entries_ex[11].bits.opb.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_4449 = mux(issue_sel_12, entries_ex[12].bits.opb.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_4450 = mux(issue_sel_13, entries_ex[13].bits.opb.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_4451 = mux(issue_sel_14, entries_ex[14].bits.opb.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_4452 = mux(issue_sel_15, entries_ex[15].bits.opb.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_4453 = or(_issue_entry_T_4437, _issue_entry_T_4438) node _issue_entry_T_4454 = or(_issue_entry_T_4453, _issue_entry_T_4439) node _issue_entry_T_4455 = or(_issue_entry_T_4454, _issue_entry_T_4440) node _issue_entry_T_4456 = or(_issue_entry_T_4455, _issue_entry_T_4441) node _issue_entry_T_4457 = or(_issue_entry_T_4456, _issue_entry_T_4442) node _issue_entry_T_4458 = or(_issue_entry_T_4457, _issue_entry_T_4443) node _issue_entry_T_4459 = or(_issue_entry_T_4458, _issue_entry_T_4444) node _issue_entry_T_4460 = or(_issue_entry_T_4459, _issue_entry_T_4445) node _issue_entry_T_4461 = or(_issue_entry_T_4460, _issue_entry_T_4446) node _issue_entry_T_4462 = or(_issue_entry_T_4461, _issue_entry_T_4447) node _issue_entry_T_4463 = or(_issue_entry_T_4462, _issue_entry_T_4448) node _issue_entry_T_4464 = or(_issue_entry_T_4463, _issue_entry_T_4449) node _issue_entry_T_4465 = or(_issue_entry_T_4464, _issue_entry_T_4450) node _issue_entry_T_4466 = or(_issue_entry_T_4465, _issue_entry_T_4451) node _issue_entry_T_4467 = or(_issue_entry_T_4466, _issue_entry_T_4452) wire _issue_entry_WIRE_240 : UInt<11> connect _issue_entry_WIRE_240, _issue_entry_T_4467 connect _issue_entry_WIRE_237.garbage, _issue_entry_WIRE_240 node _issue_entry_T_4468 = asUInt(entries_ex[0].bits.opb.bits.end.norm_cmd) node _issue_entry_T_4469 = mux(issue_sel_0_1, _issue_entry_T_4468, UInt<1>(0h0)) node _issue_entry_T_4470 = asUInt(entries_ex[1].bits.opb.bits.end.norm_cmd) node _issue_entry_T_4471 = mux(issue_sel_1_1, _issue_entry_T_4470, UInt<1>(0h0)) node _issue_entry_T_4472 = asUInt(entries_ex[2].bits.opb.bits.end.norm_cmd) node _issue_entry_T_4473 = mux(issue_sel_2_1, _issue_entry_T_4472, UInt<1>(0h0)) node _issue_entry_T_4474 = asUInt(entries_ex[3].bits.opb.bits.end.norm_cmd) node _issue_entry_T_4475 = mux(issue_sel_3_1, _issue_entry_T_4474, UInt<1>(0h0)) node _issue_entry_T_4476 = asUInt(entries_ex[4].bits.opb.bits.end.norm_cmd) node _issue_entry_T_4477 = mux(issue_sel_4_1, _issue_entry_T_4476, UInt<1>(0h0)) node _issue_entry_T_4478 = asUInt(entries_ex[5].bits.opb.bits.end.norm_cmd) node _issue_entry_T_4479 = mux(issue_sel_5_1, _issue_entry_T_4478, UInt<1>(0h0)) node _issue_entry_T_4480 = asUInt(entries_ex[6].bits.opb.bits.end.norm_cmd) node _issue_entry_T_4481 = mux(issue_sel_6_1, _issue_entry_T_4480, UInt<1>(0h0)) node _issue_entry_T_4482 = asUInt(entries_ex[7].bits.opb.bits.end.norm_cmd) node _issue_entry_T_4483 = mux(issue_sel_7_1, _issue_entry_T_4482, UInt<1>(0h0)) node _issue_entry_T_4484 = asUInt(entries_ex[8].bits.opb.bits.end.norm_cmd) node _issue_entry_T_4485 = mux(issue_sel_8, _issue_entry_T_4484, UInt<1>(0h0)) node _issue_entry_T_4486 = asUInt(entries_ex[9].bits.opb.bits.end.norm_cmd) node _issue_entry_T_4487 = mux(issue_sel_9, _issue_entry_T_4486, UInt<1>(0h0)) node _issue_entry_T_4488 = asUInt(entries_ex[10].bits.opb.bits.end.norm_cmd) node _issue_entry_T_4489 = mux(issue_sel_10, _issue_entry_T_4488, UInt<1>(0h0)) node _issue_entry_T_4490 = asUInt(entries_ex[11].bits.opb.bits.end.norm_cmd) node _issue_entry_T_4491 = mux(issue_sel_11, _issue_entry_T_4490, UInt<1>(0h0)) node _issue_entry_T_4492 = asUInt(entries_ex[12].bits.opb.bits.end.norm_cmd) node _issue_entry_T_4493 = mux(issue_sel_12, _issue_entry_T_4492, UInt<1>(0h0)) node _issue_entry_T_4494 = asUInt(entries_ex[13].bits.opb.bits.end.norm_cmd) node _issue_entry_T_4495 = mux(issue_sel_13, _issue_entry_T_4494, UInt<1>(0h0)) node _issue_entry_T_4496 = asUInt(entries_ex[14].bits.opb.bits.end.norm_cmd) node _issue_entry_T_4497 = mux(issue_sel_14, _issue_entry_T_4496, UInt<1>(0h0)) node _issue_entry_T_4498 = asUInt(entries_ex[15].bits.opb.bits.end.norm_cmd) node _issue_entry_T_4499 = mux(issue_sel_15, _issue_entry_T_4498, UInt<1>(0h0)) node _issue_entry_T_4500 = or(_issue_entry_T_4469, _issue_entry_T_4471) node _issue_entry_T_4501 = or(_issue_entry_T_4500, _issue_entry_T_4473) node _issue_entry_T_4502 = or(_issue_entry_T_4501, _issue_entry_T_4475) node _issue_entry_T_4503 = or(_issue_entry_T_4502, _issue_entry_T_4477) node _issue_entry_T_4504 = or(_issue_entry_T_4503, _issue_entry_T_4479) node _issue_entry_T_4505 = or(_issue_entry_T_4504, _issue_entry_T_4481) node _issue_entry_T_4506 = or(_issue_entry_T_4505, _issue_entry_T_4483) node _issue_entry_T_4507 = or(_issue_entry_T_4506, _issue_entry_T_4485) node _issue_entry_T_4508 = or(_issue_entry_T_4507, _issue_entry_T_4487) node _issue_entry_T_4509 = or(_issue_entry_T_4508, _issue_entry_T_4489) node _issue_entry_T_4510 = or(_issue_entry_T_4509, _issue_entry_T_4491) node _issue_entry_T_4511 = or(_issue_entry_T_4510, _issue_entry_T_4493) node _issue_entry_T_4512 = or(_issue_entry_T_4511, _issue_entry_T_4495) node _issue_entry_T_4513 = or(_issue_entry_T_4512, _issue_entry_T_4497) node _issue_entry_T_4514 = or(_issue_entry_T_4513, _issue_entry_T_4499) wire _issue_entry_WIRE_241 : UInt<3> wire _issue_entry_WIRE_242 : UInt<3> connect _issue_entry_WIRE_242, _issue_entry_T_4514 wire _issue_entry_WIRE_243 : UInt<3> connect _issue_entry_WIRE_243, _issue_entry_WIRE_242 connect _issue_entry_WIRE_241, _issue_entry_WIRE_243 connect _issue_entry_WIRE_237.norm_cmd, _issue_entry_WIRE_241 node _issue_entry_T_4515 = mux(issue_sel_0_1, entries_ex[0].bits.opb.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_4516 = mux(issue_sel_1_1, entries_ex[1].bits.opb.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_4517 = mux(issue_sel_2_1, entries_ex[2].bits.opb.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_4518 = mux(issue_sel_3_1, entries_ex[3].bits.opb.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_4519 = mux(issue_sel_4_1, entries_ex[4].bits.opb.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_4520 = mux(issue_sel_5_1, entries_ex[5].bits.opb.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_4521 = mux(issue_sel_6_1, entries_ex[6].bits.opb.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_4522 = mux(issue_sel_7_1, entries_ex[7].bits.opb.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_4523 = mux(issue_sel_8, entries_ex[8].bits.opb.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_4524 = mux(issue_sel_9, entries_ex[9].bits.opb.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_4525 = mux(issue_sel_10, entries_ex[10].bits.opb.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_4526 = mux(issue_sel_11, entries_ex[11].bits.opb.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_4527 = mux(issue_sel_12, entries_ex[12].bits.opb.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_4528 = mux(issue_sel_13, entries_ex[13].bits.opb.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_4529 = mux(issue_sel_14, entries_ex[14].bits.opb.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_4530 = mux(issue_sel_15, entries_ex[15].bits.opb.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_4531 = or(_issue_entry_T_4515, _issue_entry_T_4516) node _issue_entry_T_4532 = or(_issue_entry_T_4531, _issue_entry_T_4517) node _issue_entry_T_4533 = or(_issue_entry_T_4532, _issue_entry_T_4518) node _issue_entry_T_4534 = or(_issue_entry_T_4533, _issue_entry_T_4519) node _issue_entry_T_4535 = or(_issue_entry_T_4534, _issue_entry_T_4520) node _issue_entry_T_4536 = or(_issue_entry_T_4535, _issue_entry_T_4521) node _issue_entry_T_4537 = or(_issue_entry_T_4536, _issue_entry_T_4522) node _issue_entry_T_4538 = or(_issue_entry_T_4537, _issue_entry_T_4523) node _issue_entry_T_4539 = or(_issue_entry_T_4538, _issue_entry_T_4524) node _issue_entry_T_4540 = or(_issue_entry_T_4539, _issue_entry_T_4525) node _issue_entry_T_4541 = or(_issue_entry_T_4540, _issue_entry_T_4526) node _issue_entry_T_4542 = or(_issue_entry_T_4541, _issue_entry_T_4527) node _issue_entry_T_4543 = or(_issue_entry_T_4542, _issue_entry_T_4528) node _issue_entry_T_4544 = or(_issue_entry_T_4543, _issue_entry_T_4529) node _issue_entry_T_4545 = or(_issue_entry_T_4544, _issue_entry_T_4530) wire _issue_entry_WIRE_244 : UInt<1> connect _issue_entry_WIRE_244, _issue_entry_T_4545 connect _issue_entry_WIRE_237.read_full_acc_row, _issue_entry_WIRE_244 node _issue_entry_T_4546 = mux(issue_sel_0_1, entries_ex[0].bits.opb.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_4547 = mux(issue_sel_1_1, entries_ex[1].bits.opb.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_4548 = mux(issue_sel_2_1, entries_ex[2].bits.opb.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_4549 = mux(issue_sel_3_1, entries_ex[3].bits.opb.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_4550 = mux(issue_sel_4_1, entries_ex[4].bits.opb.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_4551 = mux(issue_sel_5_1, entries_ex[5].bits.opb.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_4552 = mux(issue_sel_6_1, entries_ex[6].bits.opb.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_4553 = mux(issue_sel_7_1, entries_ex[7].bits.opb.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_4554 = mux(issue_sel_8, entries_ex[8].bits.opb.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_4555 = mux(issue_sel_9, entries_ex[9].bits.opb.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_4556 = mux(issue_sel_10, entries_ex[10].bits.opb.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_4557 = mux(issue_sel_11, entries_ex[11].bits.opb.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_4558 = mux(issue_sel_12, entries_ex[12].bits.opb.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_4559 = mux(issue_sel_13, entries_ex[13].bits.opb.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_4560 = mux(issue_sel_14, entries_ex[14].bits.opb.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_4561 = mux(issue_sel_15, entries_ex[15].bits.opb.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_4562 = or(_issue_entry_T_4546, _issue_entry_T_4547) node _issue_entry_T_4563 = or(_issue_entry_T_4562, _issue_entry_T_4548) node _issue_entry_T_4564 = or(_issue_entry_T_4563, _issue_entry_T_4549) node _issue_entry_T_4565 = or(_issue_entry_T_4564, _issue_entry_T_4550) node _issue_entry_T_4566 = or(_issue_entry_T_4565, _issue_entry_T_4551) node _issue_entry_T_4567 = or(_issue_entry_T_4566, _issue_entry_T_4552) node _issue_entry_T_4568 = or(_issue_entry_T_4567, _issue_entry_T_4553) node _issue_entry_T_4569 = or(_issue_entry_T_4568, _issue_entry_T_4554) node _issue_entry_T_4570 = or(_issue_entry_T_4569, _issue_entry_T_4555) node _issue_entry_T_4571 = or(_issue_entry_T_4570, _issue_entry_T_4556) node _issue_entry_T_4572 = or(_issue_entry_T_4571, _issue_entry_T_4557) node _issue_entry_T_4573 = or(_issue_entry_T_4572, _issue_entry_T_4558) node _issue_entry_T_4574 = or(_issue_entry_T_4573, _issue_entry_T_4559) node _issue_entry_T_4575 = or(_issue_entry_T_4574, _issue_entry_T_4560) node _issue_entry_T_4576 = or(_issue_entry_T_4575, _issue_entry_T_4561) wire _issue_entry_WIRE_245 : UInt<1> connect _issue_entry_WIRE_245, _issue_entry_T_4576 connect _issue_entry_WIRE_237.accumulate, _issue_entry_WIRE_245 node _issue_entry_T_4577 = mux(issue_sel_0_1, entries_ex[0].bits.opb.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_4578 = mux(issue_sel_1_1, entries_ex[1].bits.opb.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_4579 = mux(issue_sel_2_1, entries_ex[2].bits.opb.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_4580 = mux(issue_sel_3_1, entries_ex[3].bits.opb.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_4581 = mux(issue_sel_4_1, entries_ex[4].bits.opb.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_4582 = mux(issue_sel_5_1, entries_ex[5].bits.opb.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_4583 = mux(issue_sel_6_1, entries_ex[6].bits.opb.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_4584 = mux(issue_sel_7_1, entries_ex[7].bits.opb.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_4585 = mux(issue_sel_8, entries_ex[8].bits.opb.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_4586 = mux(issue_sel_9, entries_ex[9].bits.opb.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_4587 = mux(issue_sel_10, entries_ex[10].bits.opb.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_4588 = mux(issue_sel_11, entries_ex[11].bits.opb.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_4589 = mux(issue_sel_12, entries_ex[12].bits.opb.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_4590 = mux(issue_sel_13, entries_ex[13].bits.opb.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_4591 = mux(issue_sel_14, entries_ex[14].bits.opb.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_4592 = mux(issue_sel_15, entries_ex[15].bits.opb.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_4593 = or(_issue_entry_T_4577, _issue_entry_T_4578) node _issue_entry_T_4594 = or(_issue_entry_T_4593, _issue_entry_T_4579) node _issue_entry_T_4595 = or(_issue_entry_T_4594, _issue_entry_T_4580) node _issue_entry_T_4596 = or(_issue_entry_T_4595, _issue_entry_T_4581) node _issue_entry_T_4597 = or(_issue_entry_T_4596, _issue_entry_T_4582) node _issue_entry_T_4598 = or(_issue_entry_T_4597, _issue_entry_T_4583) node _issue_entry_T_4599 = or(_issue_entry_T_4598, _issue_entry_T_4584) node _issue_entry_T_4600 = or(_issue_entry_T_4599, _issue_entry_T_4585) node _issue_entry_T_4601 = or(_issue_entry_T_4600, _issue_entry_T_4586) node _issue_entry_T_4602 = or(_issue_entry_T_4601, _issue_entry_T_4587) node _issue_entry_T_4603 = or(_issue_entry_T_4602, _issue_entry_T_4588) node _issue_entry_T_4604 = or(_issue_entry_T_4603, _issue_entry_T_4589) node _issue_entry_T_4605 = or(_issue_entry_T_4604, _issue_entry_T_4590) node _issue_entry_T_4606 = or(_issue_entry_T_4605, _issue_entry_T_4591) node _issue_entry_T_4607 = or(_issue_entry_T_4606, _issue_entry_T_4592) wire _issue_entry_WIRE_246 : UInt<1> connect _issue_entry_WIRE_246, _issue_entry_T_4607 connect _issue_entry_WIRE_237.is_acc_addr, _issue_entry_WIRE_246 connect _issue_entry_WIRE_235.end, _issue_entry_WIRE_237 wire _issue_entry_WIRE_247 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} node _issue_entry_T_4608 = mux(issue_sel_0_1, entries_ex[0].bits.opb.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_4609 = mux(issue_sel_1_1, entries_ex[1].bits.opb.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_4610 = mux(issue_sel_2_1, entries_ex[2].bits.opb.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_4611 = mux(issue_sel_3_1, entries_ex[3].bits.opb.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_4612 = mux(issue_sel_4_1, entries_ex[4].bits.opb.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_4613 = mux(issue_sel_5_1, entries_ex[5].bits.opb.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_4614 = mux(issue_sel_6_1, entries_ex[6].bits.opb.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_4615 = mux(issue_sel_7_1, entries_ex[7].bits.opb.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_4616 = mux(issue_sel_8, entries_ex[8].bits.opb.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_4617 = mux(issue_sel_9, entries_ex[9].bits.opb.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_4618 = mux(issue_sel_10, entries_ex[10].bits.opb.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_4619 = mux(issue_sel_11, entries_ex[11].bits.opb.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_4620 = mux(issue_sel_12, entries_ex[12].bits.opb.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_4621 = mux(issue_sel_13, entries_ex[13].bits.opb.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_4622 = mux(issue_sel_14, entries_ex[14].bits.opb.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_4623 = mux(issue_sel_15, entries_ex[15].bits.opb.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_4624 = or(_issue_entry_T_4608, _issue_entry_T_4609) node _issue_entry_T_4625 = or(_issue_entry_T_4624, _issue_entry_T_4610) node _issue_entry_T_4626 = or(_issue_entry_T_4625, _issue_entry_T_4611) node _issue_entry_T_4627 = or(_issue_entry_T_4626, _issue_entry_T_4612) node _issue_entry_T_4628 = or(_issue_entry_T_4627, _issue_entry_T_4613) node _issue_entry_T_4629 = or(_issue_entry_T_4628, _issue_entry_T_4614) node _issue_entry_T_4630 = or(_issue_entry_T_4629, _issue_entry_T_4615) node _issue_entry_T_4631 = or(_issue_entry_T_4630, _issue_entry_T_4616) node _issue_entry_T_4632 = or(_issue_entry_T_4631, _issue_entry_T_4617) node _issue_entry_T_4633 = or(_issue_entry_T_4632, _issue_entry_T_4618) node _issue_entry_T_4634 = or(_issue_entry_T_4633, _issue_entry_T_4619) node _issue_entry_T_4635 = or(_issue_entry_T_4634, _issue_entry_T_4620) node _issue_entry_T_4636 = or(_issue_entry_T_4635, _issue_entry_T_4621) node _issue_entry_T_4637 = or(_issue_entry_T_4636, _issue_entry_T_4622) node _issue_entry_T_4638 = or(_issue_entry_T_4637, _issue_entry_T_4623) wire _issue_entry_WIRE_248 : UInt<14> connect _issue_entry_WIRE_248, _issue_entry_T_4638 connect _issue_entry_WIRE_247.data, _issue_entry_WIRE_248 node _issue_entry_T_4639 = mux(issue_sel_0_1, entries_ex[0].bits.opb.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_4640 = mux(issue_sel_1_1, entries_ex[1].bits.opb.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_4641 = mux(issue_sel_2_1, entries_ex[2].bits.opb.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_4642 = mux(issue_sel_3_1, entries_ex[3].bits.opb.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_4643 = mux(issue_sel_4_1, entries_ex[4].bits.opb.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_4644 = mux(issue_sel_5_1, entries_ex[5].bits.opb.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_4645 = mux(issue_sel_6_1, entries_ex[6].bits.opb.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_4646 = mux(issue_sel_7_1, entries_ex[7].bits.opb.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_4647 = mux(issue_sel_8, entries_ex[8].bits.opb.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_4648 = mux(issue_sel_9, entries_ex[9].bits.opb.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_4649 = mux(issue_sel_10, entries_ex[10].bits.opb.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_4650 = mux(issue_sel_11, entries_ex[11].bits.opb.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_4651 = mux(issue_sel_12, entries_ex[12].bits.opb.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_4652 = mux(issue_sel_13, entries_ex[13].bits.opb.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_4653 = mux(issue_sel_14, entries_ex[14].bits.opb.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_4654 = mux(issue_sel_15, entries_ex[15].bits.opb.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_4655 = or(_issue_entry_T_4639, _issue_entry_T_4640) node _issue_entry_T_4656 = or(_issue_entry_T_4655, _issue_entry_T_4641) node _issue_entry_T_4657 = or(_issue_entry_T_4656, _issue_entry_T_4642) node _issue_entry_T_4658 = or(_issue_entry_T_4657, _issue_entry_T_4643) node _issue_entry_T_4659 = or(_issue_entry_T_4658, _issue_entry_T_4644) node _issue_entry_T_4660 = or(_issue_entry_T_4659, _issue_entry_T_4645) node _issue_entry_T_4661 = or(_issue_entry_T_4660, _issue_entry_T_4646) node _issue_entry_T_4662 = or(_issue_entry_T_4661, _issue_entry_T_4647) node _issue_entry_T_4663 = or(_issue_entry_T_4662, _issue_entry_T_4648) node _issue_entry_T_4664 = or(_issue_entry_T_4663, _issue_entry_T_4649) node _issue_entry_T_4665 = or(_issue_entry_T_4664, _issue_entry_T_4650) node _issue_entry_T_4666 = or(_issue_entry_T_4665, _issue_entry_T_4651) node _issue_entry_T_4667 = or(_issue_entry_T_4666, _issue_entry_T_4652) node _issue_entry_T_4668 = or(_issue_entry_T_4667, _issue_entry_T_4653) node _issue_entry_T_4669 = or(_issue_entry_T_4668, _issue_entry_T_4654) wire _issue_entry_WIRE_249 : UInt<1> connect _issue_entry_WIRE_249, _issue_entry_T_4669 connect _issue_entry_WIRE_247.garbage_bit, _issue_entry_WIRE_249 node _issue_entry_T_4670 = mux(issue_sel_0_1, entries_ex[0].bits.opb.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_4671 = mux(issue_sel_1_1, entries_ex[1].bits.opb.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_4672 = mux(issue_sel_2_1, entries_ex[2].bits.opb.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_4673 = mux(issue_sel_3_1, entries_ex[3].bits.opb.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_4674 = mux(issue_sel_4_1, entries_ex[4].bits.opb.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_4675 = mux(issue_sel_5_1, entries_ex[5].bits.opb.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_4676 = mux(issue_sel_6_1, entries_ex[6].bits.opb.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_4677 = mux(issue_sel_7_1, entries_ex[7].bits.opb.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_4678 = mux(issue_sel_8, entries_ex[8].bits.opb.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_4679 = mux(issue_sel_9, entries_ex[9].bits.opb.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_4680 = mux(issue_sel_10, entries_ex[10].bits.opb.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_4681 = mux(issue_sel_11, entries_ex[11].bits.opb.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_4682 = mux(issue_sel_12, entries_ex[12].bits.opb.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_4683 = mux(issue_sel_13, entries_ex[13].bits.opb.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_4684 = mux(issue_sel_14, entries_ex[14].bits.opb.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_4685 = mux(issue_sel_15, entries_ex[15].bits.opb.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_4686 = or(_issue_entry_T_4670, _issue_entry_T_4671) node _issue_entry_T_4687 = or(_issue_entry_T_4686, _issue_entry_T_4672) node _issue_entry_T_4688 = or(_issue_entry_T_4687, _issue_entry_T_4673) node _issue_entry_T_4689 = or(_issue_entry_T_4688, _issue_entry_T_4674) node _issue_entry_T_4690 = or(_issue_entry_T_4689, _issue_entry_T_4675) node _issue_entry_T_4691 = or(_issue_entry_T_4690, _issue_entry_T_4676) node _issue_entry_T_4692 = or(_issue_entry_T_4691, _issue_entry_T_4677) node _issue_entry_T_4693 = or(_issue_entry_T_4692, _issue_entry_T_4678) node _issue_entry_T_4694 = or(_issue_entry_T_4693, _issue_entry_T_4679) node _issue_entry_T_4695 = or(_issue_entry_T_4694, _issue_entry_T_4680) node _issue_entry_T_4696 = or(_issue_entry_T_4695, _issue_entry_T_4681) node _issue_entry_T_4697 = or(_issue_entry_T_4696, _issue_entry_T_4682) node _issue_entry_T_4698 = or(_issue_entry_T_4697, _issue_entry_T_4683) node _issue_entry_T_4699 = or(_issue_entry_T_4698, _issue_entry_T_4684) node _issue_entry_T_4700 = or(_issue_entry_T_4699, _issue_entry_T_4685) wire _issue_entry_WIRE_250 : UInt<11> connect _issue_entry_WIRE_250, _issue_entry_T_4700 connect _issue_entry_WIRE_247.garbage, _issue_entry_WIRE_250 node _issue_entry_T_4701 = asUInt(entries_ex[0].bits.opb.bits.start.norm_cmd) node _issue_entry_T_4702 = mux(issue_sel_0_1, _issue_entry_T_4701, UInt<1>(0h0)) node _issue_entry_T_4703 = asUInt(entries_ex[1].bits.opb.bits.start.norm_cmd) node _issue_entry_T_4704 = mux(issue_sel_1_1, _issue_entry_T_4703, UInt<1>(0h0)) node _issue_entry_T_4705 = asUInt(entries_ex[2].bits.opb.bits.start.norm_cmd) node _issue_entry_T_4706 = mux(issue_sel_2_1, _issue_entry_T_4705, UInt<1>(0h0)) node _issue_entry_T_4707 = asUInt(entries_ex[3].bits.opb.bits.start.norm_cmd) node _issue_entry_T_4708 = mux(issue_sel_3_1, _issue_entry_T_4707, UInt<1>(0h0)) node _issue_entry_T_4709 = asUInt(entries_ex[4].bits.opb.bits.start.norm_cmd) node _issue_entry_T_4710 = mux(issue_sel_4_1, _issue_entry_T_4709, UInt<1>(0h0)) node _issue_entry_T_4711 = asUInt(entries_ex[5].bits.opb.bits.start.norm_cmd) node _issue_entry_T_4712 = mux(issue_sel_5_1, _issue_entry_T_4711, UInt<1>(0h0)) node _issue_entry_T_4713 = asUInt(entries_ex[6].bits.opb.bits.start.norm_cmd) node _issue_entry_T_4714 = mux(issue_sel_6_1, _issue_entry_T_4713, UInt<1>(0h0)) node _issue_entry_T_4715 = asUInt(entries_ex[7].bits.opb.bits.start.norm_cmd) node _issue_entry_T_4716 = mux(issue_sel_7_1, _issue_entry_T_4715, UInt<1>(0h0)) node _issue_entry_T_4717 = asUInt(entries_ex[8].bits.opb.bits.start.norm_cmd) node _issue_entry_T_4718 = mux(issue_sel_8, _issue_entry_T_4717, UInt<1>(0h0)) node _issue_entry_T_4719 = asUInt(entries_ex[9].bits.opb.bits.start.norm_cmd) node _issue_entry_T_4720 = mux(issue_sel_9, _issue_entry_T_4719, UInt<1>(0h0)) node _issue_entry_T_4721 = asUInt(entries_ex[10].bits.opb.bits.start.norm_cmd) node _issue_entry_T_4722 = mux(issue_sel_10, _issue_entry_T_4721, UInt<1>(0h0)) node _issue_entry_T_4723 = asUInt(entries_ex[11].bits.opb.bits.start.norm_cmd) node _issue_entry_T_4724 = mux(issue_sel_11, _issue_entry_T_4723, UInt<1>(0h0)) node _issue_entry_T_4725 = asUInt(entries_ex[12].bits.opb.bits.start.norm_cmd) node _issue_entry_T_4726 = mux(issue_sel_12, _issue_entry_T_4725, UInt<1>(0h0)) node _issue_entry_T_4727 = asUInt(entries_ex[13].bits.opb.bits.start.norm_cmd) node _issue_entry_T_4728 = mux(issue_sel_13, _issue_entry_T_4727, UInt<1>(0h0)) node _issue_entry_T_4729 = asUInt(entries_ex[14].bits.opb.bits.start.norm_cmd) node _issue_entry_T_4730 = mux(issue_sel_14, _issue_entry_T_4729, UInt<1>(0h0)) node _issue_entry_T_4731 = asUInt(entries_ex[15].bits.opb.bits.start.norm_cmd) node _issue_entry_T_4732 = mux(issue_sel_15, _issue_entry_T_4731, UInt<1>(0h0)) node _issue_entry_T_4733 = or(_issue_entry_T_4702, _issue_entry_T_4704) node _issue_entry_T_4734 = or(_issue_entry_T_4733, _issue_entry_T_4706) node _issue_entry_T_4735 = or(_issue_entry_T_4734, _issue_entry_T_4708) node _issue_entry_T_4736 = or(_issue_entry_T_4735, _issue_entry_T_4710) node _issue_entry_T_4737 = or(_issue_entry_T_4736, _issue_entry_T_4712) node _issue_entry_T_4738 = or(_issue_entry_T_4737, _issue_entry_T_4714) node _issue_entry_T_4739 = or(_issue_entry_T_4738, _issue_entry_T_4716) node _issue_entry_T_4740 = or(_issue_entry_T_4739, _issue_entry_T_4718) node _issue_entry_T_4741 = or(_issue_entry_T_4740, _issue_entry_T_4720) node _issue_entry_T_4742 = or(_issue_entry_T_4741, _issue_entry_T_4722) node _issue_entry_T_4743 = or(_issue_entry_T_4742, _issue_entry_T_4724) node _issue_entry_T_4744 = or(_issue_entry_T_4743, _issue_entry_T_4726) node _issue_entry_T_4745 = or(_issue_entry_T_4744, _issue_entry_T_4728) node _issue_entry_T_4746 = or(_issue_entry_T_4745, _issue_entry_T_4730) node _issue_entry_T_4747 = or(_issue_entry_T_4746, _issue_entry_T_4732) wire _issue_entry_WIRE_251 : UInt<3> wire _issue_entry_WIRE_252 : UInt<3> connect _issue_entry_WIRE_252, _issue_entry_T_4747 wire _issue_entry_WIRE_253 : UInt<3> connect _issue_entry_WIRE_253, _issue_entry_WIRE_252 connect _issue_entry_WIRE_251, _issue_entry_WIRE_253 connect _issue_entry_WIRE_247.norm_cmd, _issue_entry_WIRE_251 node _issue_entry_T_4748 = mux(issue_sel_0_1, entries_ex[0].bits.opb.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_4749 = mux(issue_sel_1_1, entries_ex[1].bits.opb.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_4750 = mux(issue_sel_2_1, entries_ex[2].bits.opb.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_4751 = mux(issue_sel_3_1, entries_ex[3].bits.opb.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_4752 = mux(issue_sel_4_1, entries_ex[4].bits.opb.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_4753 = mux(issue_sel_5_1, entries_ex[5].bits.opb.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_4754 = mux(issue_sel_6_1, entries_ex[6].bits.opb.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_4755 = mux(issue_sel_7_1, entries_ex[7].bits.opb.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_4756 = mux(issue_sel_8, entries_ex[8].bits.opb.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_4757 = mux(issue_sel_9, entries_ex[9].bits.opb.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_4758 = mux(issue_sel_10, entries_ex[10].bits.opb.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_4759 = mux(issue_sel_11, entries_ex[11].bits.opb.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_4760 = mux(issue_sel_12, entries_ex[12].bits.opb.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_4761 = mux(issue_sel_13, entries_ex[13].bits.opb.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_4762 = mux(issue_sel_14, entries_ex[14].bits.opb.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_4763 = mux(issue_sel_15, entries_ex[15].bits.opb.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_4764 = or(_issue_entry_T_4748, _issue_entry_T_4749) node _issue_entry_T_4765 = or(_issue_entry_T_4764, _issue_entry_T_4750) node _issue_entry_T_4766 = or(_issue_entry_T_4765, _issue_entry_T_4751) node _issue_entry_T_4767 = or(_issue_entry_T_4766, _issue_entry_T_4752) node _issue_entry_T_4768 = or(_issue_entry_T_4767, _issue_entry_T_4753) node _issue_entry_T_4769 = or(_issue_entry_T_4768, _issue_entry_T_4754) node _issue_entry_T_4770 = or(_issue_entry_T_4769, _issue_entry_T_4755) node _issue_entry_T_4771 = or(_issue_entry_T_4770, _issue_entry_T_4756) node _issue_entry_T_4772 = or(_issue_entry_T_4771, _issue_entry_T_4757) node _issue_entry_T_4773 = or(_issue_entry_T_4772, _issue_entry_T_4758) node _issue_entry_T_4774 = or(_issue_entry_T_4773, _issue_entry_T_4759) node _issue_entry_T_4775 = or(_issue_entry_T_4774, _issue_entry_T_4760) node _issue_entry_T_4776 = or(_issue_entry_T_4775, _issue_entry_T_4761) node _issue_entry_T_4777 = or(_issue_entry_T_4776, _issue_entry_T_4762) node _issue_entry_T_4778 = or(_issue_entry_T_4777, _issue_entry_T_4763) wire _issue_entry_WIRE_254 : UInt<1> connect _issue_entry_WIRE_254, _issue_entry_T_4778 connect _issue_entry_WIRE_247.read_full_acc_row, _issue_entry_WIRE_254 node _issue_entry_T_4779 = mux(issue_sel_0_1, entries_ex[0].bits.opb.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_4780 = mux(issue_sel_1_1, entries_ex[1].bits.opb.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_4781 = mux(issue_sel_2_1, entries_ex[2].bits.opb.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_4782 = mux(issue_sel_3_1, entries_ex[3].bits.opb.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_4783 = mux(issue_sel_4_1, entries_ex[4].bits.opb.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_4784 = mux(issue_sel_5_1, entries_ex[5].bits.opb.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_4785 = mux(issue_sel_6_1, entries_ex[6].bits.opb.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_4786 = mux(issue_sel_7_1, entries_ex[7].bits.opb.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_4787 = mux(issue_sel_8, entries_ex[8].bits.opb.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_4788 = mux(issue_sel_9, entries_ex[9].bits.opb.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_4789 = mux(issue_sel_10, entries_ex[10].bits.opb.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_4790 = mux(issue_sel_11, entries_ex[11].bits.opb.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_4791 = mux(issue_sel_12, entries_ex[12].bits.opb.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_4792 = mux(issue_sel_13, entries_ex[13].bits.opb.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_4793 = mux(issue_sel_14, entries_ex[14].bits.opb.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_4794 = mux(issue_sel_15, entries_ex[15].bits.opb.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_4795 = or(_issue_entry_T_4779, _issue_entry_T_4780) node _issue_entry_T_4796 = or(_issue_entry_T_4795, _issue_entry_T_4781) node _issue_entry_T_4797 = or(_issue_entry_T_4796, _issue_entry_T_4782) node _issue_entry_T_4798 = or(_issue_entry_T_4797, _issue_entry_T_4783) node _issue_entry_T_4799 = or(_issue_entry_T_4798, _issue_entry_T_4784) node _issue_entry_T_4800 = or(_issue_entry_T_4799, _issue_entry_T_4785) node _issue_entry_T_4801 = or(_issue_entry_T_4800, _issue_entry_T_4786) node _issue_entry_T_4802 = or(_issue_entry_T_4801, _issue_entry_T_4787) node _issue_entry_T_4803 = or(_issue_entry_T_4802, _issue_entry_T_4788) node _issue_entry_T_4804 = or(_issue_entry_T_4803, _issue_entry_T_4789) node _issue_entry_T_4805 = or(_issue_entry_T_4804, _issue_entry_T_4790) node _issue_entry_T_4806 = or(_issue_entry_T_4805, _issue_entry_T_4791) node _issue_entry_T_4807 = or(_issue_entry_T_4806, _issue_entry_T_4792) node _issue_entry_T_4808 = or(_issue_entry_T_4807, _issue_entry_T_4793) node _issue_entry_T_4809 = or(_issue_entry_T_4808, _issue_entry_T_4794) wire _issue_entry_WIRE_255 : UInt<1> connect _issue_entry_WIRE_255, _issue_entry_T_4809 connect _issue_entry_WIRE_247.accumulate, _issue_entry_WIRE_255 node _issue_entry_T_4810 = mux(issue_sel_0_1, entries_ex[0].bits.opb.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_4811 = mux(issue_sel_1_1, entries_ex[1].bits.opb.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_4812 = mux(issue_sel_2_1, entries_ex[2].bits.opb.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_4813 = mux(issue_sel_3_1, entries_ex[3].bits.opb.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_4814 = mux(issue_sel_4_1, entries_ex[4].bits.opb.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_4815 = mux(issue_sel_5_1, entries_ex[5].bits.opb.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_4816 = mux(issue_sel_6_1, entries_ex[6].bits.opb.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_4817 = mux(issue_sel_7_1, entries_ex[7].bits.opb.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_4818 = mux(issue_sel_8, entries_ex[8].bits.opb.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_4819 = mux(issue_sel_9, entries_ex[9].bits.opb.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_4820 = mux(issue_sel_10, entries_ex[10].bits.opb.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_4821 = mux(issue_sel_11, entries_ex[11].bits.opb.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_4822 = mux(issue_sel_12, entries_ex[12].bits.opb.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_4823 = mux(issue_sel_13, entries_ex[13].bits.opb.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_4824 = mux(issue_sel_14, entries_ex[14].bits.opb.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_4825 = mux(issue_sel_15, entries_ex[15].bits.opb.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_4826 = or(_issue_entry_T_4810, _issue_entry_T_4811) node _issue_entry_T_4827 = or(_issue_entry_T_4826, _issue_entry_T_4812) node _issue_entry_T_4828 = or(_issue_entry_T_4827, _issue_entry_T_4813) node _issue_entry_T_4829 = or(_issue_entry_T_4828, _issue_entry_T_4814) node _issue_entry_T_4830 = or(_issue_entry_T_4829, _issue_entry_T_4815) node _issue_entry_T_4831 = or(_issue_entry_T_4830, _issue_entry_T_4816) node _issue_entry_T_4832 = or(_issue_entry_T_4831, _issue_entry_T_4817) node _issue_entry_T_4833 = or(_issue_entry_T_4832, _issue_entry_T_4818) node _issue_entry_T_4834 = or(_issue_entry_T_4833, _issue_entry_T_4819) node _issue_entry_T_4835 = or(_issue_entry_T_4834, _issue_entry_T_4820) node _issue_entry_T_4836 = or(_issue_entry_T_4835, _issue_entry_T_4821) node _issue_entry_T_4837 = or(_issue_entry_T_4836, _issue_entry_T_4822) node _issue_entry_T_4838 = or(_issue_entry_T_4837, _issue_entry_T_4823) node _issue_entry_T_4839 = or(_issue_entry_T_4838, _issue_entry_T_4824) node _issue_entry_T_4840 = or(_issue_entry_T_4839, _issue_entry_T_4825) wire _issue_entry_WIRE_256 : UInt<1> connect _issue_entry_WIRE_256, _issue_entry_T_4840 connect _issue_entry_WIRE_247.is_acc_addr, _issue_entry_WIRE_256 connect _issue_entry_WIRE_235.start, _issue_entry_WIRE_247 connect _issue_entry_WIRE_234.bits, _issue_entry_WIRE_235 node _issue_entry_T_4841 = mux(issue_sel_0_1, entries_ex[0].bits.opb.valid, UInt<1>(0h0)) node _issue_entry_T_4842 = mux(issue_sel_1_1, entries_ex[1].bits.opb.valid, UInt<1>(0h0)) node _issue_entry_T_4843 = mux(issue_sel_2_1, entries_ex[2].bits.opb.valid, UInt<1>(0h0)) node _issue_entry_T_4844 = mux(issue_sel_3_1, entries_ex[3].bits.opb.valid, UInt<1>(0h0)) node _issue_entry_T_4845 = mux(issue_sel_4_1, entries_ex[4].bits.opb.valid, UInt<1>(0h0)) node _issue_entry_T_4846 = mux(issue_sel_5_1, entries_ex[5].bits.opb.valid, UInt<1>(0h0)) node _issue_entry_T_4847 = mux(issue_sel_6_1, entries_ex[6].bits.opb.valid, UInt<1>(0h0)) node _issue_entry_T_4848 = mux(issue_sel_7_1, entries_ex[7].bits.opb.valid, UInt<1>(0h0)) node _issue_entry_T_4849 = mux(issue_sel_8, entries_ex[8].bits.opb.valid, UInt<1>(0h0)) node _issue_entry_T_4850 = mux(issue_sel_9, entries_ex[9].bits.opb.valid, UInt<1>(0h0)) node _issue_entry_T_4851 = mux(issue_sel_10, entries_ex[10].bits.opb.valid, UInt<1>(0h0)) node _issue_entry_T_4852 = mux(issue_sel_11, entries_ex[11].bits.opb.valid, UInt<1>(0h0)) node _issue_entry_T_4853 = mux(issue_sel_12, entries_ex[12].bits.opb.valid, UInt<1>(0h0)) node _issue_entry_T_4854 = mux(issue_sel_13, entries_ex[13].bits.opb.valid, UInt<1>(0h0)) node _issue_entry_T_4855 = mux(issue_sel_14, entries_ex[14].bits.opb.valid, UInt<1>(0h0)) node _issue_entry_T_4856 = mux(issue_sel_15, entries_ex[15].bits.opb.valid, UInt<1>(0h0)) node _issue_entry_T_4857 = or(_issue_entry_T_4841, _issue_entry_T_4842) node _issue_entry_T_4858 = or(_issue_entry_T_4857, _issue_entry_T_4843) node _issue_entry_T_4859 = or(_issue_entry_T_4858, _issue_entry_T_4844) node _issue_entry_T_4860 = or(_issue_entry_T_4859, _issue_entry_T_4845) node _issue_entry_T_4861 = or(_issue_entry_T_4860, _issue_entry_T_4846) node _issue_entry_T_4862 = or(_issue_entry_T_4861, _issue_entry_T_4847) node _issue_entry_T_4863 = or(_issue_entry_T_4862, _issue_entry_T_4848) node _issue_entry_T_4864 = or(_issue_entry_T_4863, _issue_entry_T_4849) node _issue_entry_T_4865 = or(_issue_entry_T_4864, _issue_entry_T_4850) node _issue_entry_T_4866 = or(_issue_entry_T_4865, _issue_entry_T_4851) node _issue_entry_T_4867 = or(_issue_entry_T_4866, _issue_entry_T_4852) node _issue_entry_T_4868 = or(_issue_entry_T_4867, _issue_entry_T_4853) node _issue_entry_T_4869 = or(_issue_entry_T_4868, _issue_entry_T_4854) node _issue_entry_T_4870 = or(_issue_entry_T_4869, _issue_entry_T_4855) node _issue_entry_T_4871 = or(_issue_entry_T_4870, _issue_entry_T_4856) wire _issue_entry_WIRE_257 : UInt<1> connect _issue_entry_WIRE_257, _issue_entry_T_4871 connect _issue_entry_WIRE_234.valid, _issue_entry_WIRE_257 connect _issue_entry_WIRE_143.opb, _issue_entry_WIRE_234 node _issue_entry_T_4872 = mux(issue_sel_0_1, entries_ex[0].bits.opa_is_dst, UInt<1>(0h0)) node _issue_entry_T_4873 = mux(issue_sel_1_1, entries_ex[1].bits.opa_is_dst, UInt<1>(0h0)) node _issue_entry_T_4874 = mux(issue_sel_2_1, entries_ex[2].bits.opa_is_dst, UInt<1>(0h0)) node _issue_entry_T_4875 = mux(issue_sel_3_1, entries_ex[3].bits.opa_is_dst, UInt<1>(0h0)) node _issue_entry_T_4876 = mux(issue_sel_4_1, entries_ex[4].bits.opa_is_dst, UInt<1>(0h0)) node _issue_entry_T_4877 = mux(issue_sel_5_1, entries_ex[5].bits.opa_is_dst, UInt<1>(0h0)) node _issue_entry_T_4878 = mux(issue_sel_6_1, entries_ex[6].bits.opa_is_dst, UInt<1>(0h0)) node _issue_entry_T_4879 = mux(issue_sel_7_1, entries_ex[7].bits.opa_is_dst, UInt<1>(0h0)) node _issue_entry_T_4880 = mux(issue_sel_8, entries_ex[8].bits.opa_is_dst, UInt<1>(0h0)) node _issue_entry_T_4881 = mux(issue_sel_9, entries_ex[9].bits.opa_is_dst, UInt<1>(0h0)) node _issue_entry_T_4882 = mux(issue_sel_10, entries_ex[10].bits.opa_is_dst, UInt<1>(0h0)) node _issue_entry_T_4883 = mux(issue_sel_11, entries_ex[11].bits.opa_is_dst, UInt<1>(0h0)) node _issue_entry_T_4884 = mux(issue_sel_12, entries_ex[12].bits.opa_is_dst, UInt<1>(0h0)) node _issue_entry_T_4885 = mux(issue_sel_13, entries_ex[13].bits.opa_is_dst, UInt<1>(0h0)) node _issue_entry_T_4886 = mux(issue_sel_14, entries_ex[14].bits.opa_is_dst, UInt<1>(0h0)) node _issue_entry_T_4887 = mux(issue_sel_15, entries_ex[15].bits.opa_is_dst, UInt<1>(0h0)) node _issue_entry_T_4888 = or(_issue_entry_T_4872, _issue_entry_T_4873) node _issue_entry_T_4889 = or(_issue_entry_T_4888, _issue_entry_T_4874) node _issue_entry_T_4890 = or(_issue_entry_T_4889, _issue_entry_T_4875) node _issue_entry_T_4891 = or(_issue_entry_T_4890, _issue_entry_T_4876) node _issue_entry_T_4892 = or(_issue_entry_T_4891, _issue_entry_T_4877) node _issue_entry_T_4893 = or(_issue_entry_T_4892, _issue_entry_T_4878) node _issue_entry_T_4894 = or(_issue_entry_T_4893, _issue_entry_T_4879) node _issue_entry_T_4895 = or(_issue_entry_T_4894, _issue_entry_T_4880) node _issue_entry_T_4896 = or(_issue_entry_T_4895, _issue_entry_T_4881) node _issue_entry_T_4897 = or(_issue_entry_T_4896, _issue_entry_T_4882) node _issue_entry_T_4898 = or(_issue_entry_T_4897, _issue_entry_T_4883) node _issue_entry_T_4899 = or(_issue_entry_T_4898, _issue_entry_T_4884) node _issue_entry_T_4900 = or(_issue_entry_T_4899, _issue_entry_T_4885) node _issue_entry_T_4901 = or(_issue_entry_T_4900, _issue_entry_T_4886) node _issue_entry_T_4902 = or(_issue_entry_T_4901, _issue_entry_T_4887) wire _issue_entry_WIRE_258 : UInt<1> connect _issue_entry_WIRE_258, _issue_entry_T_4902 connect _issue_entry_WIRE_143.opa_is_dst, _issue_entry_WIRE_258 wire _issue_entry_WIRE_259 : { valid : UInt<1>, bits : { start : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, end : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, wraps_around : UInt<1>}} wire _issue_entry_WIRE_260 : { start : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, end : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, wraps_around : UInt<1>} node _issue_entry_T_4903 = mux(issue_sel_0_1, entries_ex[0].bits.opa.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_4904 = mux(issue_sel_1_1, entries_ex[1].bits.opa.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_4905 = mux(issue_sel_2_1, entries_ex[2].bits.opa.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_4906 = mux(issue_sel_3_1, entries_ex[3].bits.opa.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_4907 = mux(issue_sel_4_1, entries_ex[4].bits.opa.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_4908 = mux(issue_sel_5_1, entries_ex[5].bits.opa.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_4909 = mux(issue_sel_6_1, entries_ex[6].bits.opa.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_4910 = mux(issue_sel_7_1, entries_ex[7].bits.opa.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_4911 = mux(issue_sel_8, entries_ex[8].bits.opa.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_4912 = mux(issue_sel_9, entries_ex[9].bits.opa.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_4913 = mux(issue_sel_10, entries_ex[10].bits.opa.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_4914 = mux(issue_sel_11, entries_ex[11].bits.opa.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_4915 = mux(issue_sel_12, entries_ex[12].bits.opa.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_4916 = mux(issue_sel_13, entries_ex[13].bits.opa.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_4917 = mux(issue_sel_14, entries_ex[14].bits.opa.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_4918 = mux(issue_sel_15, entries_ex[15].bits.opa.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_4919 = or(_issue_entry_T_4903, _issue_entry_T_4904) node _issue_entry_T_4920 = or(_issue_entry_T_4919, _issue_entry_T_4905) node _issue_entry_T_4921 = or(_issue_entry_T_4920, _issue_entry_T_4906) node _issue_entry_T_4922 = or(_issue_entry_T_4921, _issue_entry_T_4907) node _issue_entry_T_4923 = or(_issue_entry_T_4922, _issue_entry_T_4908) node _issue_entry_T_4924 = or(_issue_entry_T_4923, _issue_entry_T_4909) node _issue_entry_T_4925 = or(_issue_entry_T_4924, _issue_entry_T_4910) node _issue_entry_T_4926 = or(_issue_entry_T_4925, _issue_entry_T_4911) node _issue_entry_T_4927 = or(_issue_entry_T_4926, _issue_entry_T_4912) node _issue_entry_T_4928 = or(_issue_entry_T_4927, _issue_entry_T_4913) node _issue_entry_T_4929 = or(_issue_entry_T_4928, _issue_entry_T_4914) node _issue_entry_T_4930 = or(_issue_entry_T_4929, _issue_entry_T_4915) node _issue_entry_T_4931 = or(_issue_entry_T_4930, _issue_entry_T_4916) node _issue_entry_T_4932 = or(_issue_entry_T_4931, _issue_entry_T_4917) node _issue_entry_T_4933 = or(_issue_entry_T_4932, _issue_entry_T_4918) wire _issue_entry_WIRE_261 : UInt<1> connect _issue_entry_WIRE_261, _issue_entry_T_4933 connect _issue_entry_WIRE_260.wraps_around, _issue_entry_WIRE_261 wire _issue_entry_WIRE_262 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} node _issue_entry_T_4934 = mux(issue_sel_0_1, entries_ex[0].bits.opa.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_4935 = mux(issue_sel_1_1, entries_ex[1].bits.opa.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_4936 = mux(issue_sel_2_1, entries_ex[2].bits.opa.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_4937 = mux(issue_sel_3_1, entries_ex[3].bits.opa.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_4938 = mux(issue_sel_4_1, entries_ex[4].bits.opa.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_4939 = mux(issue_sel_5_1, entries_ex[5].bits.opa.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_4940 = mux(issue_sel_6_1, entries_ex[6].bits.opa.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_4941 = mux(issue_sel_7_1, entries_ex[7].bits.opa.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_4942 = mux(issue_sel_8, entries_ex[8].bits.opa.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_4943 = mux(issue_sel_9, entries_ex[9].bits.opa.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_4944 = mux(issue_sel_10, entries_ex[10].bits.opa.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_4945 = mux(issue_sel_11, entries_ex[11].bits.opa.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_4946 = mux(issue_sel_12, entries_ex[12].bits.opa.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_4947 = mux(issue_sel_13, entries_ex[13].bits.opa.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_4948 = mux(issue_sel_14, entries_ex[14].bits.opa.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_4949 = mux(issue_sel_15, entries_ex[15].bits.opa.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_4950 = or(_issue_entry_T_4934, _issue_entry_T_4935) node _issue_entry_T_4951 = or(_issue_entry_T_4950, _issue_entry_T_4936) node _issue_entry_T_4952 = or(_issue_entry_T_4951, _issue_entry_T_4937) node _issue_entry_T_4953 = or(_issue_entry_T_4952, _issue_entry_T_4938) node _issue_entry_T_4954 = or(_issue_entry_T_4953, _issue_entry_T_4939) node _issue_entry_T_4955 = or(_issue_entry_T_4954, _issue_entry_T_4940) node _issue_entry_T_4956 = or(_issue_entry_T_4955, _issue_entry_T_4941) node _issue_entry_T_4957 = or(_issue_entry_T_4956, _issue_entry_T_4942) node _issue_entry_T_4958 = or(_issue_entry_T_4957, _issue_entry_T_4943) node _issue_entry_T_4959 = or(_issue_entry_T_4958, _issue_entry_T_4944) node _issue_entry_T_4960 = or(_issue_entry_T_4959, _issue_entry_T_4945) node _issue_entry_T_4961 = or(_issue_entry_T_4960, _issue_entry_T_4946) node _issue_entry_T_4962 = or(_issue_entry_T_4961, _issue_entry_T_4947) node _issue_entry_T_4963 = or(_issue_entry_T_4962, _issue_entry_T_4948) node _issue_entry_T_4964 = or(_issue_entry_T_4963, _issue_entry_T_4949) wire _issue_entry_WIRE_263 : UInt<14> connect _issue_entry_WIRE_263, _issue_entry_T_4964 connect _issue_entry_WIRE_262.data, _issue_entry_WIRE_263 node _issue_entry_T_4965 = mux(issue_sel_0_1, entries_ex[0].bits.opa.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_4966 = mux(issue_sel_1_1, entries_ex[1].bits.opa.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_4967 = mux(issue_sel_2_1, entries_ex[2].bits.opa.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_4968 = mux(issue_sel_3_1, entries_ex[3].bits.opa.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_4969 = mux(issue_sel_4_1, entries_ex[4].bits.opa.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_4970 = mux(issue_sel_5_1, entries_ex[5].bits.opa.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_4971 = mux(issue_sel_6_1, entries_ex[6].bits.opa.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_4972 = mux(issue_sel_7_1, entries_ex[7].bits.opa.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_4973 = mux(issue_sel_8, entries_ex[8].bits.opa.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_4974 = mux(issue_sel_9, entries_ex[9].bits.opa.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_4975 = mux(issue_sel_10, entries_ex[10].bits.opa.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_4976 = mux(issue_sel_11, entries_ex[11].bits.opa.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_4977 = mux(issue_sel_12, entries_ex[12].bits.opa.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_4978 = mux(issue_sel_13, entries_ex[13].bits.opa.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_4979 = mux(issue_sel_14, entries_ex[14].bits.opa.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_4980 = mux(issue_sel_15, entries_ex[15].bits.opa.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_4981 = or(_issue_entry_T_4965, _issue_entry_T_4966) node _issue_entry_T_4982 = or(_issue_entry_T_4981, _issue_entry_T_4967) node _issue_entry_T_4983 = or(_issue_entry_T_4982, _issue_entry_T_4968) node _issue_entry_T_4984 = or(_issue_entry_T_4983, _issue_entry_T_4969) node _issue_entry_T_4985 = or(_issue_entry_T_4984, _issue_entry_T_4970) node _issue_entry_T_4986 = or(_issue_entry_T_4985, _issue_entry_T_4971) node _issue_entry_T_4987 = or(_issue_entry_T_4986, _issue_entry_T_4972) node _issue_entry_T_4988 = or(_issue_entry_T_4987, _issue_entry_T_4973) node _issue_entry_T_4989 = or(_issue_entry_T_4988, _issue_entry_T_4974) node _issue_entry_T_4990 = or(_issue_entry_T_4989, _issue_entry_T_4975) node _issue_entry_T_4991 = or(_issue_entry_T_4990, _issue_entry_T_4976) node _issue_entry_T_4992 = or(_issue_entry_T_4991, _issue_entry_T_4977) node _issue_entry_T_4993 = or(_issue_entry_T_4992, _issue_entry_T_4978) node _issue_entry_T_4994 = or(_issue_entry_T_4993, _issue_entry_T_4979) node _issue_entry_T_4995 = or(_issue_entry_T_4994, _issue_entry_T_4980) wire _issue_entry_WIRE_264 : UInt<1> connect _issue_entry_WIRE_264, _issue_entry_T_4995 connect _issue_entry_WIRE_262.garbage_bit, _issue_entry_WIRE_264 node _issue_entry_T_4996 = mux(issue_sel_0_1, entries_ex[0].bits.opa.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_4997 = mux(issue_sel_1_1, entries_ex[1].bits.opa.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_4998 = mux(issue_sel_2_1, entries_ex[2].bits.opa.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_4999 = mux(issue_sel_3_1, entries_ex[3].bits.opa.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_5000 = mux(issue_sel_4_1, entries_ex[4].bits.opa.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_5001 = mux(issue_sel_5_1, entries_ex[5].bits.opa.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_5002 = mux(issue_sel_6_1, entries_ex[6].bits.opa.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_5003 = mux(issue_sel_7_1, entries_ex[7].bits.opa.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_5004 = mux(issue_sel_8, entries_ex[8].bits.opa.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_5005 = mux(issue_sel_9, entries_ex[9].bits.opa.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_5006 = mux(issue_sel_10, entries_ex[10].bits.opa.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_5007 = mux(issue_sel_11, entries_ex[11].bits.opa.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_5008 = mux(issue_sel_12, entries_ex[12].bits.opa.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_5009 = mux(issue_sel_13, entries_ex[13].bits.opa.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_5010 = mux(issue_sel_14, entries_ex[14].bits.opa.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_5011 = mux(issue_sel_15, entries_ex[15].bits.opa.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_5012 = or(_issue_entry_T_4996, _issue_entry_T_4997) node _issue_entry_T_5013 = or(_issue_entry_T_5012, _issue_entry_T_4998) node _issue_entry_T_5014 = or(_issue_entry_T_5013, _issue_entry_T_4999) node _issue_entry_T_5015 = or(_issue_entry_T_5014, _issue_entry_T_5000) node _issue_entry_T_5016 = or(_issue_entry_T_5015, _issue_entry_T_5001) node _issue_entry_T_5017 = or(_issue_entry_T_5016, _issue_entry_T_5002) node _issue_entry_T_5018 = or(_issue_entry_T_5017, _issue_entry_T_5003) node _issue_entry_T_5019 = or(_issue_entry_T_5018, _issue_entry_T_5004) node _issue_entry_T_5020 = or(_issue_entry_T_5019, _issue_entry_T_5005) node _issue_entry_T_5021 = or(_issue_entry_T_5020, _issue_entry_T_5006) node _issue_entry_T_5022 = or(_issue_entry_T_5021, _issue_entry_T_5007) node _issue_entry_T_5023 = or(_issue_entry_T_5022, _issue_entry_T_5008) node _issue_entry_T_5024 = or(_issue_entry_T_5023, _issue_entry_T_5009) node _issue_entry_T_5025 = or(_issue_entry_T_5024, _issue_entry_T_5010) node _issue_entry_T_5026 = or(_issue_entry_T_5025, _issue_entry_T_5011) wire _issue_entry_WIRE_265 : UInt<11> connect _issue_entry_WIRE_265, _issue_entry_T_5026 connect _issue_entry_WIRE_262.garbage, _issue_entry_WIRE_265 node _issue_entry_T_5027 = asUInt(entries_ex[0].bits.opa.bits.end.norm_cmd) node _issue_entry_T_5028 = mux(issue_sel_0_1, _issue_entry_T_5027, UInt<1>(0h0)) node _issue_entry_T_5029 = asUInt(entries_ex[1].bits.opa.bits.end.norm_cmd) node _issue_entry_T_5030 = mux(issue_sel_1_1, _issue_entry_T_5029, UInt<1>(0h0)) node _issue_entry_T_5031 = asUInt(entries_ex[2].bits.opa.bits.end.norm_cmd) node _issue_entry_T_5032 = mux(issue_sel_2_1, _issue_entry_T_5031, UInt<1>(0h0)) node _issue_entry_T_5033 = asUInt(entries_ex[3].bits.opa.bits.end.norm_cmd) node _issue_entry_T_5034 = mux(issue_sel_3_1, _issue_entry_T_5033, UInt<1>(0h0)) node _issue_entry_T_5035 = asUInt(entries_ex[4].bits.opa.bits.end.norm_cmd) node _issue_entry_T_5036 = mux(issue_sel_4_1, _issue_entry_T_5035, UInt<1>(0h0)) node _issue_entry_T_5037 = asUInt(entries_ex[5].bits.opa.bits.end.norm_cmd) node _issue_entry_T_5038 = mux(issue_sel_5_1, _issue_entry_T_5037, UInt<1>(0h0)) node _issue_entry_T_5039 = asUInt(entries_ex[6].bits.opa.bits.end.norm_cmd) node _issue_entry_T_5040 = mux(issue_sel_6_1, _issue_entry_T_5039, UInt<1>(0h0)) node _issue_entry_T_5041 = asUInt(entries_ex[7].bits.opa.bits.end.norm_cmd) node _issue_entry_T_5042 = mux(issue_sel_7_1, _issue_entry_T_5041, UInt<1>(0h0)) node _issue_entry_T_5043 = asUInt(entries_ex[8].bits.opa.bits.end.norm_cmd) node _issue_entry_T_5044 = mux(issue_sel_8, _issue_entry_T_5043, UInt<1>(0h0)) node _issue_entry_T_5045 = asUInt(entries_ex[9].bits.opa.bits.end.norm_cmd) node _issue_entry_T_5046 = mux(issue_sel_9, _issue_entry_T_5045, UInt<1>(0h0)) node _issue_entry_T_5047 = asUInt(entries_ex[10].bits.opa.bits.end.norm_cmd) node _issue_entry_T_5048 = mux(issue_sel_10, _issue_entry_T_5047, UInt<1>(0h0)) node _issue_entry_T_5049 = asUInt(entries_ex[11].bits.opa.bits.end.norm_cmd) node _issue_entry_T_5050 = mux(issue_sel_11, _issue_entry_T_5049, UInt<1>(0h0)) node _issue_entry_T_5051 = asUInt(entries_ex[12].bits.opa.bits.end.norm_cmd) node _issue_entry_T_5052 = mux(issue_sel_12, _issue_entry_T_5051, UInt<1>(0h0)) node _issue_entry_T_5053 = asUInt(entries_ex[13].bits.opa.bits.end.norm_cmd) node _issue_entry_T_5054 = mux(issue_sel_13, _issue_entry_T_5053, UInt<1>(0h0)) node _issue_entry_T_5055 = asUInt(entries_ex[14].bits.opa.bits.end.norm_cmd) node _issue_entry_T_5056 = mux(issue_sel_14, _issue_entry_T_5055, UInt<1>(0h0)) node _issue_entry_T_5057 = asUInt(entries_ex[15].bits.opa.bits.end.norm_cmd) node _issue_entry_T_5058 = mux(issue_sel_15, _issue_entry_T_5057, UInt<1>(0h0)) node _issue_entry_T_5059 = or(_issue_entry_T_5028, _issue_entry_T_5030) node _issue_entry_T_5060 = or(_issue_entry_T_5059, _issue_entry_T_5032) node _issue_entry_T_5061 = or(_issue_entry_T_5060, _issue_entry_T_5034) node _issue_entry_T_5062 = or(_issue_entry_T_5061, _issue_entry_T_5036) node _issue_entry_T_5063 = or(_issue_entry_T_5062, _issue_entry_T_5038) node _issue_entry_T_5064 = or(_issue_entry_T_5063, _issue_entry_T_5040) node _issue_entry_T_5065 = or(_issue_entry_T_5064, _issue_entry_T_5042) node _issue_entry_T_5066 = or(_issue_entry_T_5065, _issue_entry_T_5044) node _issue_entry_T_5067 = or(_issue_entry_T_5066, _issue_entry_T_5046) node _issue_entry_T_5068 = or(_issue_entry_T_5067, _issue_entry_T_5048) node _issue_entry_T_5069 = or(_issue_entry_T_5068, _issue_entry_T_5050) node _issue_entry_T_5070 = or(_issue_entry_T_5069, _issue_entry_T_5052) node _issue_entry_T_5071 = or(_issue_entry_T_5070, _issue_entry_T_5054) node _issue_entry_T_5072 = or(_issue_entry_T_5071, _issue_entry_T_5056) node _issue_entry_T_5073 = or(_issue_entry_T_5072, _issue_entry_T_5058) wire _issue_entry_WIRE_266 : UInt<3> wire _issue_entry_WIRE_267 : UInt<3> connect _issue_entry_WIRE_267, _issue_entry_T_5073 wire _issue_entry_WIRE_268 : UInt<3> connect _issue_entry_WIRE_268, _issue_entry_WIRE_267 connect _issue_entry_WIRE_266, _issue_entry_WIRE_268 connect _issue_entry_WIRE_262.norm_cmd, _issue_entry_WIRE_266 node _issue_entry_T_5074 = mux(issue_sel_0_1, entries_ex[0].bits.opa.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_5075 = mux(issue_sel_1_1, entries_ex[1].bits.opa.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_5076 = mux(issue_sel_2_1, entries_ex[2].bits.opa.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_5077 = mux(issue_sel_3_1, entries_ex[3].bits.opa.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_5078 = mux(issue_sel_4_1, entries_ex[4].bits.opa.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_5079 = mux(issue_sel_5_1, entries_ex[5].bits.opa.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_5080 = mux(issue_sel_6_1, entries_ex[6].bits.opa.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_5081 = mux(issue_sel_7_1, entries_ex[7].bits.opa.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_5082 = mux(issue_sel_8, entries_ex[8].bits.opa.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_5083 = mux(issue_sel_9, entries_ex[9].bits.opa.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_5084 = mux(issue_sel_10, entries_ex[10].bits.opa.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_5085 = mux(issue_sel_11, entries_ex[11].bits.opa.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_5086 = mux(issue_sel_12, entries_ex[12].bits.opa.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_5087 = mux(issue_sel_13, entries_ex[13].bits.opa.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_5088 = mux(issue_sel_14, entries_ex[14].bits.opa.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_5089 = mux(issue_sel_15, entries_ex[15].bits.opa.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_5090 = or(_issue_entry_T_5074, _issue_entry_T_5075) node _issue_entry_T_5091 = or(_issue_entry_T_5090, _issue_entry_T_5076) node _issue_entry_T_5092 = or(_issue_entry_T_5091, _issue_entry_T_5077) node _issue_entry_T_5093 = or(_issue_entry_T_5092, _issue_entry_T_5078) node _issue_entry_T_5094 = or(_issue_entry_T_5093, _issue_entry_T_5079) node _issue_entry_T_5095 = or(_issue_entry_T_5094, _issue_entry_T_5080) node _issue_entry_T_5096 = or(_issue_entry_T_5095, _issue_entry_T_5081) node _issue_entry_T_5097 = or(_issue_entry_T_5096, _issue_entry_T_5082) node _issue_entry_T_5098 = or(_issue_entry_T_5097, _issue_entry_T_5083) node _issue_entry_T_5099 = or(_issue_entry_T_5098, _issue_entry_T_5084) node _issue_entry_T_5100 = or(_issue_entry_T_5099, _issue_entry_T_5085) node _issue_entry_T_5101 = or(_issue_entry_T_5100, _issue_entry_T_5086) node _issue_entry_T_5102 = or(_issue_entry_T_5101, _issue_entry_T_5087) node _issue_entry_T_5103 = or(_issue_entry_T_5102, _issue_entry_T_5088) node _issue_entry_T_5104 = or(_issue_entry_T_5103, _issue_entry_T_5089) wire _issue_entry_WIRE_269 : UInt<1> connect _issue_entry_WIRE_269, _issue_entry_T_5104 connect _issue_entry_WIRE_262.read_full_acc_row, _issue_entry_WIRE_269 node _issue_entry_T_5105 = mux(issue_sel_0_1, entries_ex[0].bits.opa.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_5106 = mux(issue_sel_1_1, entries_ex[1].bits.opa.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_5107 = mux(issue_sel_2_1, entries_ex[2].bits.opa.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_5108 = mux(issue_sel_3_1, entries_ex[3].bits.opa.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_5109 = mux(issue_sel_4_1, entries_ex[4].bits.opa.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_5110 = mux(issue_sel_5_1, entries_ex[5].bits.opa.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_5111 = mux(issue_sel_6_1, entries_ex[6].bits.opa.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_5112 = mux(issue_sel_7_1, entries_ex[7].bits.opa.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_5113 = mux(issue_sel_8, entries_ex[8].bits.opa.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_5114 = mux(issue_sel_9, entries_ex[9].bits.opa.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_5115 = mux(issue_sel_10, entries_ex[10].bits.opa.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_5116 = mux(issue_sel_11, entries_ex[11].bits.opa.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_5117 = mux(issue_sel_12, entries_ex[12].bits.opa.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_5118 = mux(issue_sel_13, entries_ex[13].bits.opa.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_5119 = mux(issue_sel_14, entries_ex[14].bits.opa.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_5120 = mux(issue_sel_15, entries_ex[15].bits.opa.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_5121 = or(_issue_entry_T_5105, _issue_entry_T_5106) node _issue_entry_T_5122 = or(_issue_entry_T_5121, _issue_entry_T_5107) node _issue_entry_T_5123 = or(_issue_entry_T_5122, _issue_entry_T_5108) node _issue_entry_T_5124 = or(_issue_entry_T_5123, _issue_entry_T_5109) node _issue_entry_T_5125 = or(_issue_entry_T_5124, _issue_entry_T_5110) node _issue_entry_T_5126 = or(_issue_entry_T_5125, _issue_entry_T_5111) node _issue_entry_T_5127 = or(_issue_entry_T_5126, _issue_entry_T_5112) node _issue_entry_T_5128 = or(_issue_entry_T_5127, _issue_entry_T_5113) node _issue_entry_T_5129 = or(_issue_entry_T_5128, _issue_entry_T_5114) node _issue_entry_T_5130 = or(_issue_entry_T_5129, _issue_entry_T_5115) node _issue_entry_T_5131 = or(_issue_entry_T_5130, _issue_entry_T_5116) node _issue_entry_T_5132 = or(_issue_entry_T_5131, _issue_entry_T_5117) node _issue_entry_T_5133 = or(_issue_entry_T_5132, _issue_entry_T_5118) node _issue_entry_T_5134 = or(_issue_entry_T_5133, _issue_entry_T_5119) node _issue_entry_T_5135 = or(_issue_entry_T_5134, _issue_entry_T_5120) wire _issue_entry_WIRE_270 : UInt<1> connect _issue_entry_WIRE_270, _issue_entry_T_5135 connect _issue_entry_WIRE_262.accumulate, _issue_entry_WIRE_270 node _issue_entry_T_5136 = mux(issue_sel_0_1, entries_ex[0].bits.opa.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_5137 = mux(issue_sel_1_1, entries_ex[1].bits.opa.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_5138 = mux(issue_sel_2_1, entries_ex[2].bits.opa.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_5139 = mux(issue_sel_3_1, entries_ex[3].bits.opa.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_5140 = mux(issue_sel_4_1, entries_ex[4].bits.opa.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_5141 = mux(issue_sel_5_1, entries_ex[5].bits.opa.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_5142 = mux(issue_sel_6_1, entries_ex[6].bits.opa.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_5143 = mux(issue_sel_7_1, entries_ex[7].bits.opa.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_5144 = mux(issue_sel_8, entries_ex[8].bits.opa.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_5145 = mux(issue_sel_9, entries_ex[9].bits.opa.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_5146 = mux(issue_sel_10, entries_ex[10].bits.opa.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_5147 = mux(issue_sel_11, entries_ex[11].bits.opa.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_5148 = mux(issue_sel_12, entries_ex[12].bits.opa.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_5149 = mux(issue_sel_13, entries_ex[13].bits.opa.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_5150 = mux(issue_sel_14, entries_ex[14].bits.opa.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_5151 = mux(issue_sel_15, entries_ex[15].bits.opa.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_5152 = or(_issue_entry_T_5136, _issue_entry_T_5137) node _issue_entry_T_5153 = or(_issue_entry_T_5152, _issue_entry_T_5138) node _issue_entry_T_5154 = or(_issue_entry_T_5153, _issue_entry_T_5139) node _issue_entry_T_5155 = or(_issue_entry_T_5154, _issue_entry_T_5140) node _issue_entry_T_5156 = or(_issue_entry_T_5155, _issue_entry_T_5141) node _issue_entry_T_5157 = or(_issue_entry_T_5156, _issue_entry_T_5142) node _issue_entry_T_5158 = or(_issue_entry_T_5157, _issue_entry_T_5143) node _issue_entry_T_5159 = or(_issue_entry_T_5158, _issue_entry_T_5144) node _issue_entry_T_5160 = or(_issue_entry_T_5159, _issue_entry_T_5145) node _issue_entry_T_5161 = or(_issue_entry_T_5160, _issue_entry_T_5146) node _issue_entry_T_5162 = or(_issue_entry_T_5161, _issue_entry_T_5147) node _issue_entry_T_5163 = or(_issue_entry_T_5162, _issue_entry_T_5148) node _issue_entry_T_5164 = or(_issue_entry_T_5163, _issue_entry_T_5149) node _issue_entry_T_5165 = or(_issue_entry_T_5164, _issue_entry_T_5150) node _issue_entry_T_5166 = or(_issue_entry_T_5165, _issue_entry_T_5151) wire _issue_entry_WIRE_271 : UInt<1> connect _issue_entry_WIRE_271, _issue_entry_T_5166 connect _issue_entry_WIRE_262.is_acc_addr, _issue_entry_WIRE_271 connect _issue_entry_WIRE_260.end, _issue_entry_WIRE_262 wire _issue_entry_WIRE_272 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} node _issue_entry_T_5167 = mux(issue_sel_0_1, entries_ex[0].bits.opa.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_5168 = mux(issue_sel_1_1, entries_ex[1].bits.opa.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_5169 = mux(issue_sel_2_1, entries_ex[2].bits.opa.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_5170 = mux(issue_sel_3_1, entries_ex[3].bits.opa.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_5171 = mux(issue_sel_4_1, entries_ex[4].bits.opa.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_5172 = mux(issue_sel_5_1, entries_ex[5].bits.opa.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_5173 = mux(issue_sel_6_1, entries_ex[6].bits.opa.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_5174 = mux(issue_sel_7_1, entries_ex[7].bits.opa.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_5175 = mux(issue_sel_8, entries_ex[8].bits.opa.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_5176 = mux(issue_sel_9, entries_ex[9].bits.opa.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_5177 = mux(issue_sel_10, entries_ex[10].bits.opa.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_5178 = mux(issue_sel_11, entries_ex[11].bits.opa.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_5179 = mux(issue_sel_12, entries_ex[12].bits.opa.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_5180 = mux(issue_sel_13, entries_ex[13].bits.opa.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_5181 = mux(issue_sel_14, entries_ex[14].bits.opa.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_5182 = mux(issue_sel_15, entries_ex[15].bits.opa.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_5183 = or(_issue_entry_T_5167, _issue_entry_T_5168) node _issue_entry_T_5184 = or(_issue_entry_T_5183, _issue_entry_T_5169) node _issue_entry_T_5185 = or(_issue_entry_T_5184, _issue_entry_T_5170) node _issue_entry_T_5186 = or(_issue_entry_T_5185, _issue_entry_T_5171) node _issue_entry_T_5187 = or(_issue_entry_T_5186, _issue_entry_T_5172) node _issue_entry_T_5188 = or(_issue_entry_T_5187, _issue_entry_T_5173) node _issue_entry_T_5189 = or(_issue_entry_T_5188, _issue_entry_T_5174) node _issue_entry_T_5190 = or(_issue_entry_T_5189, _issue_entry_T_5175) node _issue_entry_T_5191 = or(_issue_entry_T_5190, _issue_entry_T_5176) node _issue_entry_T_5192 = or(_issue_entry_T_5191, _issue_entry_T_5177) node _issue_entry_T_5193 = or(_issue_entry_T_5192, _issue_entry_T_5178) node _issue_entry_T_5194 = or(_issue_entry_T_5193, _issue_entry_T_5179) node _issue_entry_T_5195 = or(_issue_entry_T_5194, _issue_entry_T_5180) node _issue_entry_T_5196 = or(_issue_entry_T_5195, _issue_entry_T_5181) node _issue_entry_T_5197 = or(_issue_entry_T_5196, _issue_entry_T_5182) wire _issue_entry_WIRE_273 : UInt<14> connect _issue_entry_WIRE_273, _issue_entry_T_5197 connect _issue_entry_WIRE_272.data, _issue_entry_WIRE_273 node _issue_entry_T_5198 = mux(issue_sel_0_1, entries_ex[0].bits.opa.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_5199 = mux(issue_sel_1_1, entries_ex[1].bits.opa.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_5200 = mux(issue_sel_2_1, entries_ex[2].bits.opa.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_5201 = mux(issue_sel_3_1, entries_ex[3].bits.opa.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_5202 = mux(issue_sel_4_1, entries_ex[4].bits.opa.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_5203 = mux(issue_sel_5_1, entries_ex[5].bits.opa.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_5204 = mux(issue_sel_6_1, entries_ex[6].bits.opa.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_5205 = mux(issue_sel_7_1, entries_ex[7].bits.opa.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_5206 = mux(issue_sel_8, entries_ex[8].bits.opa.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_5207 = mux(issue_sel_9, entries_ex[9].bits.opa.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_5208 = mux(issue_sel_10, entries_ex[10].bits.opa.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_5209 = mux(issue_sel_11, entries_ex[11].bits.opa.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_5210 = mux(issue_sel_12, entries_ex[12].bits.opa.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_5211 = mux(issue_sel_13, entries_ex[13].bits.opa.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_5212 = mux(issue_sel_14, entries_ex[14].bits.opa.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_5213 = mux(issue_sel_15, entries_ex[15].bits.opa.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_5214 = or(_issue_entry_T_5198, _issue_entry_T_5199) node _issue_entry_T_5215 = or(_issue_entry_T_5214, _issue_entry_T_5200) node _issue_entry_T_5216 = or(_issue_entry_T_5215, _issue_entry_T_5201) node _issue_entry_T_5217 = or(_issue_entry_T_5216, _issue_entry_T_5202) node _issue_entry_T_5218 = or(_issue_entry_T_5217, _issue_entry_T_5203) node _issue_entry_T_5219 = or(_issue_entry_T_5218, _issue_entry_T_5204) node _issue_entry_T_5220 = or(_issue_entry_T_5219, _issue_entry_T_5205) node _issue_entry_T_5221 = or(_issue_entry_T_5220, _issue_entry_T_5206) node _issue_entry_T_5222 = or(_issue_entry_T_5221, _issue_entry_T_5207) node _issue_entry_T_5223 = or(_issue_entry_T_5222, _issue_entry_T_5208) node _issue_entry_T_5224 = or(_issue_entry_T_5223, _issue_entry_T_5209) node _issue_entry_T_5225 = or(_issue_entry_T_5224, _issue_entry_T_5210) node _issue_entry_T_5226 = or(_issue_entry_T_5225, _issue_entry_T_5211) node _issue_entry_T_5227 = or(_issue_entry_T_5226, _issue_entry_T_5212) node _issue_entry_T_5228 = or(_issue_entry_T_5227, _issue_entry_T_5213) wire _issue_entry_WIRE_274 : UInt<1> connect _issue_entry_WIRE_274, _issue_entry_T_5228 connect _issue_entry_WIRE_272.garbage_bit, _issue_entry_WIRE_274 node _issue_entry_T_5229 = mux(issue_sel_0_1, entries_ex[0].bits.opa.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_5230 = mux(issue_sel_1_1, entries_ex[1].bits.opa.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_5231 = mux(issue_sel_2_1, entries_ex[2].bits.opa.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_5232 = mux(issue_sel_3_1, entries_ex[3].bits.opa.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_5233 = mux(issue_sel_4_1, entries_ex[4].bits.opa.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_5234 = mux(issue_sel_5_1, entries_ex[5].bits.opa.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_5235 = mux(issue_sel_6_1, entries_ex[6].bits.opa.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_5236 = mux(issue_sel_7_1, entries_ex[7].bits.opa.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_5237 = mux(issue_sel_8, entries_ex[8].bits.opa.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_5238 = mux(issue_sel_9, entries_ex[9].bits.opa.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_5239 = mux(issue_sel_10, entries_ex[10].bits.opa.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_5240 = mux(issue_sel_11, entries_ex[11].bits.opa.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_5241 = mux(issue_sel_12, entries_ex[12].bits.opa.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_5242 = mux(issue_sel_13, entries_ex[13].bits.opa.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_5243 = mux(issue_sel_14, entries_ex[14].bits.opa.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_5244 = mux(issue_sel_15, entries_ex[15].bits.opa.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_5245 = or(_issue_entry_T_5229, _issue_entry_T_5230) node _issue_entry_T_5246 = or(_issue_entry_T_5245, _issue_entry_T_5231) node _issue_entry_T_5247 = or(_issue_entry_T_5246, _issue_entry_T_5232) node _issue_entry_T_5248 = or(_issue_entry_T_5247, _issue_entry_T_5233) node _issue_entry_T_5249 = or(_issue_entry_T_5248, _issue_entry_T_5234) node _issue_entry_T_5250 = or(_issue_entry_T_5249, _issue_entry_T_5235) node _issue_entry_T_5251 = or(_issue_entry_T_5250, _issue_entry_T_5236) node _issue_entry_T_5252 = or(_issue_entry_T_5251, _issue_entry_T_5237) node _issue_entry_T_5253 = or(_issue_entry_T_5252, _issue_entry_T_5238) node _issue_entry_T_5254 = or(_issue_entry_T_5253, _issue_entry_T_5239) node _issue_entry_T_5255 = or(_issue_entry_T_5254, _issue_entry_T_5240) node _issue_entry_T_5256 = or(_issue_entry_T_5255, _issue_entry_T_5241) node _issue_entry_T_5257 = or(_issue_entry_T_5256, _issue_entry_T_5242) node _issue_entry_T_5258 = or(_issue_entry_T_5257, _issue_entry_T_5243) node _issue_entry_T_5259 = or(_issue_entry_T_5258, _issue_entry_T_5244) wire _issue_entry_WIRE_275 : UInt<11> connect _issue_entry_WIRE_275, _issue_entry_T_5259 connect _issue_entry_WIRE_272.garbage, _issue_entry_WIRE_275 node _issue_entry_T_5260 = asUInt(entries_ex[0].bits.opa.bits.start.norm_cmd) node _issue_entry_T_5261 = mux(issue_sel_0_1, _issue_entry_T_5260, UInt<1>(0h0)) node _issue_entry_T_5262 = asUInt(entries_ex[1].bits.opa.bits.start.norm_cmd) node _issue_entry_T_5263 = mux(issue_sel_1_1, _issue_entry_T_5262, UInt<1>(0h0)) node _issue_entry_T_5264 = asUInt(entries_ex[2].bits.opa.bits.start.norm_cmd) node _issue_entry_T_5265 = mux(issue_sel_2_1, _issue_entry_T_5264, UInt<1>(0h0)) node _issue_entry_T_5266 = asUInt(entries_ex[3].bits.opa.bits.start.norm_cmd) node _issue_entry_T_5267 = mux(issue_sel_3_1, _issue_entry_T_5266, UInt<1>(0h0)) node _issue_entry_T_5268 = asUInt(entries_ex[4].bits.opa.bits.start.norm_cmd) node _issue_entry_T_5269 = mux(issue_sel_4_1, _issue_entry_T_5268, UInt<1>(0h0)) node _issue_entry_T_5270 = asUInt(entries_ex[5].bits.opa.bits.start.norm_cmd) node _issue_entry_T_5271 = mux(issue_sel_5_1, _issue_entry_T_5270, UInt<1>(0h0)) node _issue_entry_T_5272 = asUInt(entries_ex[6].bits.opa.bits.start.norm_cmd) node _issue_entry_T_5273 = mux(issue_sel_6_1, _issue_entry_T_5272, UInt<1>(0h0)) node _issue_entry_T_5274 = asUInt(entries_ex[7].bits.opa.bits.start.norm_cmd) node _issue_entry_T_5275 = mux(issue_sel_7_1, _issue_entry_T_5274, UInt<1>(0h0)) node _issue_entry_T_5276 = asUInt(entries_ex[8].bits.opa.bits.start.norm_cmd) node _issue_entry_T_5277 = mux(issue_sel_8, _issue_entry_T_5276, UInt<1>(0h0)) node _issue_entry_T_5278 = asUInt(entries_ex[9].bits.opa.bits.start.norm_cmd) node _issue_entry_T_5279 = mux(issue_sel_9, _issue_entry_T_5278, UInt<1>(0h0)) node _issue_entry_T_5280 = asUInt(entries_ex[10].bits.opa.bits.start.norm_cmd) node _issue_entry_T_5281 = mux(issue_sel_10, _issue_entry_T_5280, UInt<1>(0h0)) node _issue_entry_T_5282 = asUInt(entries_ex[11].bits.opa.bits.start.norm_cmd) node _issue_entry_T_5283 = mux(issue_sel_11, _issue_entry_T_5282, UInt<1>(0h0)) node _issue_entry_T_5284 = asUInt(entries_ex[12].bits.opa.bits.start.norm_cmd) node _issue_entry_T_5285 = mux(issue_sel_12, _issue_entry_T_5284, UInt<1>(0h0)) node _issue_entry_T_5286 = asUInt(entries_ex[13].bits.opa.bits.start.norm_cmd) node _issue_entry_T_5287 = mux(issue_sel_13, _issue_entry_T_5286, UInt<1>(0h0)) node _issue_entry_T_5288 = asUInt(entries_ex[14].bits.opa.bits.start.norm_cmd) node _issue_entry_T_5289 = mux(issue_sel_14, _issue_entry_T_5288, UInt<1>(0h0)) node _issue_entry_T_5290 = asUInt(entries_ex[15].bits.opa.bits.start.norm_cmd) node _issue_entry_T_5291 = mux(issue_sel_15, _issue_entry_T_5290, UInt<1>(0h0)) node _issue_entry_T_5292 = or(_issue_entry_T_5261, _issue_entry_T_5263) node _issue_entry_T_5293 = or(_issue_entry_T_5292, _issue_entry_T_5265) node _issue_entry_T_5294 = or(_issue_entry_T_5293, _issue_entry_T_5267) node _issue_entry_T_5295 = or(_issue_entry_T_5294, _issue_entry_T_5269) node _issue_entry_T_5296 = or(_issue_entry_T_5295, _issue_entry_T_5271) node _issue_entry_T_5297 = or(_issue_entry_T_5296, _issue_entry_T_5273) node _issue_entry_T_5298 = or(_issue_entry_T_5297, _issue_entry_T_5275) node _issue_entry_T_5299 = or(_issue_entry_T_5298, _issue_entry_T_5277) node _issue_entry_T_5300 = or(_issue_entry_T_5299, _issue_entry_T_5279) node _issue_entry_T_5301 = or(_issue_entry_T_5300, _issue_entry_T_5281) node _issue_entry_T_5302 = or(_issue_entry_T_5301, _issue_entry_T_5283) node _issue_entry_T_5303 = or(_issue_entry_T_5302, _issue_entry_T_5285) node _issue_entry_T_5304 = or(_issue_entry_T_5303, _issue_entry_T_5287) node _issue_entry_T_5305 = or(_issue_entry_T_5304, _issue_entry_T_5289) node _issue_entry_T_5306 = or(_issue_entry_T_5305, _issue_entry_T_5291) wire _issue_entry_WIRE_276 : UInt<3> wire _issue_entry_WIRE_277 : UInt<3> connect _issue_entry_WIRE_277, _issue_entry_T_5306 wire _issue_entry_WIRE_278 : UInt<3> connect _issue_entry_WIRE_278, _issue_entry_WIRE_277 connect _issue_entry_WIRE_276, _issue_entry_WIRE_278 connect _issue_entry_WIRE_272.norm_cmd, _issue_entry_WIRE_276 node _issue_entry_T_5307 = mux(issue_sel_0_1, entries_ex[0].bits.opa.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_5308 = mux(issue_sel_1_1, entries_ex[1].bits.opa.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_5309 = mux(issue_sel_2_1, entries_ex[2].bits.opa.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_5310 = mux(issue_sel_3_1, entries_ex[3].bits.opa.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_5311 = mux(issue_sel_4_1, entries_ex[4].bits.opa.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_5312 = mux(issue_sel_5_1, entries_ex[5].bits.opa.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_5313 = mux(issue_sel_6_1, entries_ex[6].bits.opa.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_5314 = mux(issue_sel_7_1, entries_ex[7].bits.opa.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_5315 = mux(issue_sel_8, entries_ex[8].bits.opa.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_5316 = mux(issue_sel_9, entries_ex[9].bits.opa.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_5317 = mux(issue_sel_10, entries_ex[10].bits.opa.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_5318 = mux(issue_sel_11, entries_ex[11].bits.opa.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_5319 = mux(issue_sel_12, entries_ex[12].bits.opa.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_5320 = mux(issue_sel_13, entries_ex[13].bits.opa.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_5321 = mux(issue_sel_14, entries_ex[14].bits.opa.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_5322 = mux(issue_sel_15, entries_ex[15].bits.opa.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_5323 = or(_issue_entry_T_5307, _issue_entry_T_5308) node _issue_entry_T_5324 = or(_issue_entry_T_5323, _issue_entry_T_5309) node _issue_entry_T_5325 = or(_issue_entry_T_5324, _issue_entry_T_5310) node _issue_entry_T_5326 = or(_issue_entry_T_5325, _issue_entry_T_5311) node _issue_entry_T_5327 = or(_issue_entry_T_5326, _issue_entry_T_5312) node _issue_entry_T_5328 = or(_issue_entry_T_5327, _issue_entry_T_5313) node _issue_entry_T_5329 = or(_issue_entry_T_5328, _issue_entry_T_5314) node _issue_entry_T_5330 = or(_issue_entry_T_5329, _issue_entry_T_5315) node _issue_entry_T_5331 = or(_issue_entry_T_5330, _issue_entry_T_5316) node _issue_entry_T_5332 = or(_issue_entry_T_5331, _issue_entry_T_5317) node _issue_entry_T_5333 = or(_issue_entry_T_5332, _issue_entry_T_5318) node _issue_entry_T_5334 = or(_issue_entry_T_5333, _issue_entry_T_5319) node _issue_entry_T_5335 = or(_issue_entry_T_5334, _issue_entry_T_5320) node _issue_entry_T_5336 = or(_issue_entry_T_5335, _issue_entry_T_5321) node _issue_entry_T_5337 = or(_issue_entry_T_5336, _issue_entry_T_5322) wire _issue_entry_WIRE_279 : UInt<1> connect _issue_entry_WIRE_279, _issue_entry_T_5337 connect _issue_entry_WIRE_272.read_full_acc_row, _issue_entry_WIRE_279 node _issue_entry_T_5338 = mux(issue_sel_0_1, entries_ex[0].bits.opa.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_5339 = mux(issue_sel_1_1, entries_ex[1].bits.opa.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_5340 = mux(issue_sel_2_1, entries_ex[2].bits.opa.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_5341 = mux(issue_sel_3_1, entries_ex[3].bits.opa.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_5342 = mux(issue_sel_4_1, entries_ex[4].bits.opa.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_5343 = mux(issue_sel_5_1, entries_ex[5].bits.opa.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_5344 = mux(issue_sel_6_1, entries_ex[6].bits.opa.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_5345 = mux(issue_sel_7_1, entries_ex[7].bits.opa.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_5346 = mux(issue_sel_8, entries_ex[8].bits.opa.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_5347 = mux(issue_sel_9, entries_ex[9].bits.opa.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_5348 = mux(issue_sel_10, entries_ex[10].bits.opa.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_5349 = mux(issue_sel_11, entries_ex[11].bits.opa.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_5350 = mux(issue_sel_12, entries_ex[12].bits.opa.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_5351 = mux(issue_sel_13, entries_ex[13].bits.opa.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_5352 = mux(issue_sel_14, entries_ex[14].bits.opa.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_5353 = mux(issue_sel_15, entries_ex[15].bits.opa.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_5354 = or(_issue_entry_T_5338, _issue_entry_T_5339) node _issue_entry_T_5355 = or(_issue_entry_T_5354, _issue_entry_T_5340) node _issue_entry_T_5356 = or(_issue_entry_T_5355, _issue_entry_T_5341) node _issue_entry_T_5357 = or(_issue_entry_T_5356, _issue_entry_T_5342) node _issue_entry_T_5358 = or(_issue_entry_T_5357, _issue_entry_T_5343) node _issue_entry_T_5359 = or(_issue_entry_T_5358, _issue_entry_T_5344) node _issue_entry_T_5360 = or(_issue_entry_T_5359, _issue_entry_T_5345) node _issue_entry_T_5361 = or(_issue_entry_T_5360, _issue_entry_T_5346) node _issue_entry_T_5362 = or(_issue_entry_T_5361, _issue_entry_T_5347) node _issue_entry_T_5363 = or(_issue_entry_T_5362, _issue_entry_T_5348) node _issue_entry_T_5364 = or(_issue_entry_T_5363, _issue_entry_T_5349) node _issue_entry_T_5365 = or(_issue_entry_T_5364, _issue_entry_T_5350) node _issue_entry_T_5366 = or(_issue_entry_T_5365, _issue_entry_T_5351) node _issue_entry_T_5367 = or(_issue_entry_T_5366, _issue_entry_T_5352) node _issue_entry_T_5368 = or(_issue_entry_T_5367, _issue_entry_T_5353) wire _issue_entry_WIRE_280 : UInt<1> connect _issue_entry_WIRE_280, _issue_entry_T_5368 connect _issue_entry_WIRE_272.accumulate, _issue_entry_WIRE_280 node _issue_entry_T_5369 = mux(issue_sel_0_1, entries_ex[0].bits.opa.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_5370 = mux(issue_sel_1_1, entries_ex[1].bits.opa.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_5371 = mux(issue_sel_2_1, entries_ex[2].bits.opa.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_5372 = mux(issue_sel_3_1, entries_ex[3].bits.opa.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_5373 = mux(issue_sel_4_1, entries_ex[4].bits.opa.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_5374 = mux(issue_sel_5_1, entries_ex[5].bits.opa.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_5375 = mux(issue_sel_6_1, entries_ex[6].bits.opa.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_5376 = mux(issue_sel_7_1, entries_ex[7].bits.opa.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_5377 = mux(issue_sel_8, entries_ex[8].bits.opa.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_5378 = mux(issue_sel_9, entries_ex[9].bits.opa.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_5379 = mux(issue_sel_10, entries_ex[10].bits.opa.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_5380 = mux(issue_sel_11, entries_ex[11].bits.opa.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_5381 = mux(issue_sel_12, entries_ex[12].bits.opa.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_5382 = mux(issue_sel_13, entries_ex[13].bits.opa.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_5383 = mux(issue_sel_14, entries_ex[14].bits.opa.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_5384 = mux(issue_sel_15, entries_ex[15].bits.opa.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_5385 = or(_issue_entry_T_5369, _issue_entry_T_5370) node _issue_entry_T_5386 = or(_issue_entry_T_5385, _issue_entry_T_5371) node _issue_entry_T_5387 = or(_issue_entry_T_5386, _issue_entry_T_5372) node _issue_entry_T_5388 = or(_issue_entry_T_5387, _issue_entry_T_5373) node _issue_entry_T_5389 = or(_issue_entry_T_5388, _issue_entry_T_5374) node _issue_entry_T_5390 = or(_issue_entry_T_5389, _issue_entry_T_5375) node _issue_entry_T_5391 = or(_issue_entry_T_5390, _issue_entry_T_5376) node _issue_entry_T_5392 = or(_issue_entry_T_5391, _issue_entry_T_5377) node _issue_entry_T_5393 = or(_issue_entry_T_5392, _issue_entry_T_5378) node _issue_entry_T_5394 = or(_issue_entry_T_5393, _issue_entry_T_5379) node _issue_entry_T_5395 = or(_issue_entry_T_5394, _issue_entry_T_5380) node _issue_entry_T_5396 = or(_issue_entry_T_5395, _issue_entry_T_5381) node _issue_entry_T_5397 = or(_issue_entry_T_5396, _issue_entry_T_5382) node _issue_entry_T_5398 = or(_issue_entry_T_5397, _issue_entry_T_5383) node _issue_entry_T_5399 = or(_issue_entry_T_5398, _issue_entry_T_5384) wire _issue_entry_WIRE_281 : UInt<1> connect _issue_entry_WIRE_281, _issue_entry_T_5399 connect _issue_entry_WIRE_272.is_acc_addr, _issue_entry_WIRE_281 connect _issue_entry_WIRE_260.start, _issue_entry_WIRE_272 connect _issue_entry_WIRE_259.bits, _issue_entry_WIRE_260 node _issue_entry_T_5400 = mux(issue_sel_0_1, entries_ex[0].bits.opa.valid, UInt<1>(0h0)) node _issue_entry_T_5401 = mux(issue_sel_1_1, entries_ex[1].bits.opa.valid, UInt<1>(0h0)) node _issue_entry_T_5402 = mux(issue_sel_2_1, entries_ex[2].bits.opa.valid, UInt<1>(0h0)) node _issue_entry_T_5403 = mux(issue_sel_3_1, entries_ex[3].bits.opa.valid, UInt<1>(0h0)) node _issue_entry_T_5404 = mux(issue_sel_4_1, entries_ex[4].bits.opa.valid, UInt<1>(0h0)) node _issue_entry_T_5405 = mux(issue_sel_5_1, entries_ex[5].bits.opa.valid, UInt<1>(0h0)) node _issue_entry_T_5406 = mux(issue_sel_6_1, entries_ex[6].bits.opa.valid, UInt<1>(0h0)) node _issue_entry_T_5407 = mux(issue_sel_7_1, entries_ex[7].bits.opa.valid, UInt<1>(0h0)) node _issue_entry_T_5408 = mux(issue_sel_8, entries_ex[8].bits.opa.valid, UInt<1>(0h0)) node _issue_entry_T_5409 = mux(issue_sel_9, entries_ex[9].bits.opa.valid, UInt<1>(0h0)) node _issue_entry_T_5410 = mux(issue_sel_10, entries_ex[10].bits.opa.valid, UInt<1>(0h0)) node _issue_entry_T_5411 = mux(issue_sel_11, entries_ex[11].bits.opa.valid, UInt<1>(0h0)) node _issue_entry_T_5412 = mux(issue_sel_12, entries_ex[12].bits.opa.valid, UInt<1>(0h0)) node _issue_entry_T_5413 = mux(issue_sel_13, entries_ex[13].bits.opa.valid, UInt<1>(0h0)) node _issue_entry_T_5414 = mux(issue_sel_14, entries_ex[14].bits.opa.valid, UInt<1>(0h0)) node _issue_entry_T_5415 = mux(issue_sel_15, entries_ex[15].bits.opa.valid, UInt<1>(0h0)) node _issue_entry_T_5416 = or(_issue_entry_T_5400, _issue_entry_T_5401) node _issue_entry_T_5417 = or(_issue_entry_T_5416, _issue_entry_T_5402) node _issue_entry_T_5418 = or(_issue_entry_T_5417, _issue_entry_T_5403) node _issue_entry_T_5419 = or(_issue_entry_T_5418, _issue_entry_T_5404) node _issue_entry_T_5420 = or(_issue_entry_T_5419, _issue_entry_T_5405) node _issue_entry_T_5421 = or(_issue_entry_T_5420, _issue_entry_T_5406) node _issue_entry_T_5422 = or(_issue_entry_T_5421, _issue_entry_T_5407) node _issue_entry_T_5423 = or(_issue_entry_T_5422, _issue_entry_T_5408) node _issue_entry_T_5424 = or(_issue_entry_T_5423, _issue_entry_T_5409) node _issue_entry_T_5425 = or(_issue_entry_T_5424, _issue_entry_T_5410) node _issue_entry_T_5426 = or(_issue_entry_T_5425, _issue_entry_T_5411) node _issue_entry_T_5427 = or(_issue_entry_T_5426, _issue_entry_T_5412) node _issue_entry_T_5428 = or(_issue_entry_T_5427, _issue_entry_T_5413) node _issue_entry_T_5429 = or(_issue_entry_T_5428, _issue_entry_T_5414) node _issue_entry_T_5430 = or(_issue_entry_T_5429, _issue_entry_T_5415) wire _issue_entry_WIRE_282 : UInt<1> connect _issue_entry_WIRE_282, _issue_entry_T_5430 connect _issue_entry_WIRE_259.valid, _issue_entry_WIRE_282 connect _issue_entry_WIRE_143.opa, _issue_entry_WIRE_259 node _issue_entry_T_5431 = mux(issue_sel_0_1, entries_ex[0].bits.is_config, UInt<1>(0h0)) node _issue_entry_T_5432 = mux(issue_sel_1_1, entries_ex[1].bits.is_config, UInt<1>(0h0)) node _issue_entry_T_5433 = mux(issue_sel_2_1, entries_ex[2].bits.is_config, UInt<1>(0h0)) node _issue_entry_T_5434 = mux(issue_sel_3_1, entries_ex[3].bits.is_config, UInt<1>(0h0)) node _issue_entry_T_5435 = mux(issue_sel_4_1, entries_ex[4].bits.is_config, UInt<1>(0h0)) node _issue_entry_T_5436 = mux(issue_sel_5_1, entries_ex[5].bits.is_config, UInt<1>(0h0)) node _issue_entry_T_5437 = mux(issue_sel_6_1, entries_ex[6].bits.is_config, UInt<1>(0h0)) node _issue_entry_T_5438 = mux(issue_sel_7_1, entries_ex[7].bits.is_config, UInt<1>(0h0)) node _issue_entry_T_5439 = mux(issue_sel_8, entries_ex[8].bits.is_config, UInt<1>(0h0)) node _issue_entry_T_5440 = mux(issue_sel_9, entries_ex[9].bits.is_config, UInt<1>(0h0)) node _issue_entry_T_5441 = mux(issue_sel_10, entries_ex[10].bits.is_config, UInt<1>(0h0)) node _issue_entry_T_5442 = mux(issue_sel_11, entries_ex[11].bits.is_config, UInt<1>(0h0)) node _issue_entry_T_5443 = mux(issue_sel_12, entries_ex[12].bits.is_config, UInt<1>(0h0)) node _issue_entry_T_5444 = mux(issue_sel_13, entries_ex[13].bits.is_config, UInt<1>(0h0)) node _issue_entry_T_5445 = mux(issue_sel_14, entries_ex[14].bits.is_config, UInt<1>(0h0)) node _issue_entry_T_5446 = mux(issue_sel_15, entries_ex[15].bits.is_config, UInt<1>(0h0)) node _issue_entry_T_5447 = or(_issue_entry_T_5431, _issue_entry_T_5432) node _issue_entry_T_5448 = or(_issue_entry_T_5447, _issue_entry_T_5433) node _issue_entry_T_5449 = or(_issue_entry_T_5448, _issue_entry_T_5434) node _issue_entry_T_5450 = or(_issue_entry_T_5449, _issue_entry_T_5435) node _issue_entry_T_5451 = or(_issue_entry_T_5450, _issue_entry_T_5436) node _issue_entry_T_5452 = or(_issue_entry_T_5451, _issue_entry_T_5437) node _issue_entry_T_5453 = or(_issue_entry_T_5452, _issue_entry_T_5438) node _issue_entry_T_5454 = or(_issue_entry_T_5453, _issue_entry_T_5439) node _issue_entry_T_5455 = or(_issue_entry_T_5454, _issue_entry_T_5440) node _issue_entry_T_5456 = or(_issue_entry_T_5455, _issue_entry_T_5441) node _issue_entry_T_5457 = or(_issue_entry_T_5456, _issue_entry_T_5442) node _issue_entry_T_5458 = or(_issue_entry_T_5457, _issue_entry_T_5443) node _issue_entry_T_5459 = or(_issue_entry_T_5458, _issue_entry_T_5444) node _issue_entry_T_5460 = or(_issue_entry_T_5459, _issue_entry_T_5445) node _issue_entry_T_5461 = or(_issue_entry_T_5460, _issue_entry_T_5446) wire _issue_entry_WIRE_283 : UInt<1> connect _issue_entry_WIRE_283, _issue_entry_T_5461 connect _issue_entry_WIRE_143.is_config, _issue_entry_WIRE_283 node _issue_entry_T_5462 = mux(issue_sel_0_1, entries_ex[0].bits.q, UInt<1>(0h0)) node _issue_entry_T_5463 = mux(issue_sel_1_1, entries_ex[1].bits.q, UInt<1>(0h0)) node _issue_entry_T_5464 = mux(issue_sel_2_1, entries_ex[2].bits.q, UInt<1>(0h0)) node _issue_entry_T_5465 = mux(issue_sel_3_1, entries_ex[3].bits.q, UInt<1>(0h0)) node _issue_entry_T_5466 = mux(issue_sel_4_1, entries_ex[4].bits.q, UInt<1>(0h0)) node _issue_entry_T_5467 = mux(issue_sel_5_1, entries_ex[5].bits.q, UInt<1>(0h0)) node _issue_entry_T_5468 = mux(issue_sel_6_1, entries_ex[6].bits.q, UInt<1>(0h0)) node _issue_entry_T_5469 = mux(issue_sel_7_1, entries_ex[7].bits.q, UInt<1>(0h0)) node _issue_entry_T_5470 = mux(issue_sel_8, entries_ex[8].bits.q, UInt<1>(0h0)) node _issue_entry_T_5471 = mux(issue_sel_9, entries_ex[9].bits.q, UInt<1>(0h0)) node _issue_entry_T_5472 = mux(issue_sel_10, entries_ex[10].bits.q, UInt<1>(0h0)) node _issue_entry_T_5473 = mux(issue_sel_11, entries_ex[11].bits.q, UInt<1>(0h0)) node _issue_entry_T_5474 = mux(issue_sel_12, entries_ex[12].bits.q, UInt<1>(0h0)) node _issue_entry_T_5475 = mux(issue_sel_13, entries_ex[13].bits.q, UInt<1>(0h0)) node _issue_entry_T_5476 = mux(issue_sel_14, entries_ex[14].bits.q, UInt<1>(0h0)) node _issue_entry_T_5477 = mux(issue_sel_15, entries_ex[15].bits.q, UInt<1>(0h0)) node _issue_entry_T_5478 = or(_issue_entry_T_5462, _issue_entry_T_5463) node _issue_entry_T_5479 = or(_issue_entry_T_5478, _issue_entry_T_5464) node _issue_entry_T_5480 = or(_issue_entry_T_5479, _issue_entry_T_5465) node _issue_entry_T_5481 = or(_issue_entry_T_5480, _issue_entry_T_5466) node _issue_entry_T_5482 = or(_issue_entry_T_5481, _issue_entry_T_5467) node _issue_entry_T_5483 = or(_issue_entry_T_5482, _issue_entry_T_5468) node _issue_entry_T_5484 = or(_issue_entry_T_5483, _issue_entry_T_5469) node _issue_entry_T_5485 = or(_issue_entry_T_5484, _issue_entry_T_5470) node _issue_entry_T_5486 = or(_issue_entry_T_5485, _issue_entry_T_5471) node _issue_entry_T_5487 = or(_issue_entry_T_5486, _issue_entry_T_5472) node _issue_entry_T_5488 = or(_issue_entry_T_5487, _issue_entry_T_5473) node _issue_entry_T_5489 = or(_issue_entry_T_5488, _issue_entry_T_5474) node _issue_entry_T_5490 = or(_issue_entry_T_5489, _issue_entry_T_5475) node _issue_entry_T_5491 = or(_issue_entry_T_5490, _issue_entry_T_5476) node _issue_entry_T_5492 = or(_issue_entry_T_5491, _issue_entry_T_5477) wire _issue_entry_WIRE_284 : UInt<2> connect _issue_entry_WIRE_284, _issue_entry_T_5492 connect _issue_entry_WIRE_143.q, _issue_entry_WIRE_284 connect issue_entry_1.bits, _issue_entry_WIRE_143 node _issue_entry_T_5493 = mux(issue_sel_0_1, entries_ex[0].valid, UInt<1>(0h0)) node _issue_entry_T_5494 = mux(issue_sel_1_1, entries_ex[1].valid, UInt<1>(0h0)) node _issue_entry_T_5495 = mux(issue_sel_2_1, entries_ex[2].valid, UInt<1>(0h0)) node _issue_entry_T_5496 = mux(issue_sel_3_1, entries_ex[3].valid, UInt<1>(0h0)) node _issue_entry_T_5497 = mux(issue_sel_4_1, entries_ex[4].valid, UInt<1>(0h0)) node _issue_entry_T_5498 = mux(issue_sel_5_1, entries_ex[5].valid, UInt<1>(0h0)) node _issue_entry_T_5499 = mux(issue_sel_6_1, entries_ex[6].valid, UInt<1>(0h0)) node _issue_entry_T_5500 = mux(issue_sel_7_1, entries_ex[7].valid, UInt<1>(0h0)) node _issue_entry_T_5501 = mux(issue_sel_8, entries_ex[8].valid, UInt<1>(0h0)) node _issue_entry_T_5502 = mux(issue_sel_9, entries_ex[9].valid, UInt<1>(0h0)) node _issue_entry_T_5503 = mux(issue_sel_10, entries_ex[10].valid, UInt<1>(0h0)) node _issue_entry_T_5504 = mux(issue_sel_11, entries_ex[11].valid, UInt<1>(0h0)) node _issue_entry_T_5505 = mux(issue_sel_12, entries_ex[12].valid, UInt<1>(0h0)) node _issue_entry_T_5506 = mux(issue_sel_13, entries_ex[13].valid, UInt<1>(0h0)) node _issue_entry_T_5507 = mux(issue_sel_14, entries_ex[14].valid, UInt<1>(0h0)) node _issue_entry_T_5508 = mux(issue_sel_15, entries_ex[15].valid, UInt<1>(0h0)) node _issue_entry_T_5509 = or(_issue_entry_T_5493, _issue_entry_T_5494) node _issue_entry_T_5510 = or(_issue_entry_T_5509, _issue_entry_T_5495) node _issue_entry_T_5511 = or(_issue_entry_T_5510, _issue_entry_T_5496) node _issue_entry_T_5512 = or(_issue_entry_T_5511, _issue_entry_T_5497) node _issue_entry_T_5513 = or(_issue_entry_T_5512, _issue_entry_T_5498) node _issue_entry_T_5514 = or(_issue_entry_T_5513, _issue_entry_T_5499) node _issue_entry_T_5515 = or(_issue_entry_T_5514, _issue_entry_T_5500) node _issue_entry_T_5516 = or(_issue_entry_T_5515, _issue_entry_T_5501) node _issue_entry_T_5517 = or(_issue_entry_T_5516, _issue_entry_T_5502) node _issue_entry_T_5518 = or(_issue_entry_T_5517, _issue_entry_T_5503) node _issue_entry_T_5519 = or(_issue_entry_T_5518, _issue_entry_T_5504) node _issue_entry_T_5520 = or(_issue_entry_T_5519, _issue_entry_T_5505) node _issue_entry_T_5521 = or(_issue_entry_T_5520, _issue_entry_T_5506) node _issue_entry_T_5522 = or(_issue_entry_T_5521, _issue_entry_T_5507) node _issue_entry_T_5523 = or(_issue_entry_T_5522, _issue_entry_T_5508) wire _issue_entry_WIRE_285 : UInt<1> connect _issue_entry_WIRE_285, _issue_entry_T_5523 connect issue_entry_1.valid, _issue_entry_WIRE_285 node _io_issue_ex_valid_T = or(issue_valids_0_1, issue_valids_1_1) node _io_issue_ex_valid_T_1 = or(_io_issue_ex_valid_T, issue_valids_2_1) node _io_issue_ex_valid_T_2 = or(_io_issue_ex_valid_T_1, issue_valids_3_1) node _io_issue_ex_valid_T_3 = or(_io_issue_ex_valid_T_2, issue_valids_4_1) node _io_issue_ex_valid_T_4 = or(_io_issue_ex_valid_T_3, issue_valids_5_1) node _io_issue_ex_valid_T_5 = or(_io_issue_ex_valid_T_4, issue_valids_6_1) node _io_issue_ex_valid_T_6 = or(_io_issue_ex_valid_T_5, issue_valids_7_1) node _io_issue_ex_valid_T_7 = or(_io_issue_ex_valid_T_6, issue_valids_8) node _io_issue_ex_valid_T_8 = or(_io_issue_ex_valid_T_7, issue_valids_9) node _io_issue_ex_valid_T_9 = or(_io_issue_ex_valid_T_8, issue_valids_10) node _io_issue_ex_valid_T_10 = or(_io_issue_ex_valid_T_9, issue_valids_11) node _io_issue_ex_valid_T_11 = or(_io_issue_ex_valid_T_10, issue_valids_12) node _io_issue_ex_valid_T_12 = or(_io_issue_ex_valid_T_11, issue_valids_13) node _io_issue_ex_valid_T_13 = or(_io_issue_ex_valid_T_12, issue_valids_14) node _io_issue_ex_valid_T_14 = or(_io_issue_ex_valid_T_13, issue_valids_15) connect io.issue.ex.valid, _io_issue_ex_valid_T_14 connect io.issue.ex.cmd, issue_entry_1.bits.cmd connect io.issue.ex.rob_id, global_issue_id_1 node _T_4867 = and(io.issue.ex.valid, io.issue.ex.ready) when _T_4867 : when issue_sel_0_1 : connect entries_ex[0].bits.issued, UInt<1>(0h1) node _entries_ex_0_valid_T = eq(entries_ex[0].bits.complete_on_issue, UInt<1>(0h0)) connect entries_ex[0].valid, _entries_ex_0_valid_T when issue_sel_1_1 : connect entries_ex[1].bits.issued, UInt<1>(0h1) node _entries_ex_1_valid_T = eq(entries_ex[1].bits.complete_on_issue, UInt<1>(0h0)) connect entries_ex[1].valid, _entries_ex_1_valid_T when issue_sel_2_1 : connect entries_ex[2].bits.issued, UInt<1>(0h1) node _entries_ex_2_valid_T = eq(entries_ex[2].bits.complete_on_issue, UInt<1>(0h0)) connect entries_ex[2].valid, _entries_ex_2_valid_T when issue_sel_3_1 : connect entries_ex[3].bits.issued, UInt<1>(0h1) node _entries_ex_3_valid_T = eq(entries_ex[3].bits.complete_on_issue, UInt<1>(0h0)) connect entries_ex[3].valid, _entries_ex_3_valid_T when issue_sel_4_1 : connect entries_ex[4].bits.issued, UInt<1>(0h1) node _entries_ex_4_valid_T = eq(entries_ex[4].bits.complete_on_issue, UInt<1>(0h0)) connect entries_ex[4].valid, _entries_ex_4_valid_T when issue_sel_5_1 : connect entries_ex[5].bits.issued, UInt<1>(0h1) node _entries_ex_5_valid_T = eq(entries_ex[5].bits.complete_on_issue, UInt<1>(0h0)) connect entries_ex[5].valid, _entries_ex_5_valid_T when issue_sel_6_1 : connect entries_ex[6].bits.issued, UInt<1>(0h1) node _entries_ex_6_valid_T = eq(entries_ex[6].bits.complete_on_issue, UInt<1>(0h0)) connect entries_ex[6].valid, _entries_ex_6_valid_T when issue_sel_7_1 : connect entries_ex[7].bits.issued, UInt<1>(0h1) node _entries_ex_7_valid_T = eq(entries_ex[7].bits.complete_on_issue, UInt<1>(0h0)) connect entries_ex[7].valid, _entries_ex_7_valid_T when issue_sel_8 : connect entries_ex[8].bits.issued, UInt<1>(0h1) node _entries_ex_8_valid_T = eq(entries_ex[8].bits.complete_on_issue, UInt<1>(0h0)) connect entries_ex[8].valid, _entries_ex_8_valid_T when issue_sel_9 : connect entries_ex[9].bits.issued, UInt<1>(0h1) node _entries_ex_9_valid_T = eq(entries_ex[9].bits.complete_on_issue, UInt<1>(0h0)) connect entries_ex[9].valid, _entries_ex_9_valid_T when issue_sel_10 : connect entries_ex[10].bits.issued, UInt<1>(0h1) node _entries_ex_10_valid_T = eq(entries_ex[10].bits.complete_on_issue, UInt<1>(0h0)) connect entries_ex[10].valid, _entries_ex_10_valid_T when issue_sel_11 : connect entries_ex[11].bits.issued, UInt<1>(0h1) node _entries_ex_11_valid_T = eq(entries_ex[11].bits.complete_on_issue, UInt<1>(0h0)) connect entries_ex[11].valid, _entries_ex_11_valid_T when issue_sel_12 : connect entries_ex[12].bits.issued, UInt<1>(0h1) node _entries_ex_12_valid_T = eq(entries_ex[12].bits.complete_on_issue, UInt<1>(0h0)) connect entries_ex[12].valid, _entries_ex_12_valid_T when issue_sel_13 : connect entries_ex[13].bits.issued, UInt<1>(0h1) node _entries_ex_13_valid_T = eq(entries_ex[13].bits.complete_on_issue, UInt<1>(0h0)) connect entries_ex[13].valid, _entries_ex_13_valid_T when issue_sel_14 : connect entries_ex[14].bits.issued, UInt<1>(0h1) node _entries_ex_14_valid_T = eq(entries_ex[14].bits.complete_on_issue, UInt<1>(0h0)) connect entries_ex[14].valid, _entries_ex_14_valid_T when issue_sel_15 : connect entries_ex[15].bits.issued, UInt<1>(0h1) node _entries_ex_15_valid_T = eq(entries_ex[15].bits.complete_on_issue, UInt<1>(0h0)) connect entries_ex[15].valid, _entries_ex_15_valid_T node _T_4868 = eq(UInt<2>(0h1), UInt<2>(0h0)) when _T_4868 : connect entries_ld[0].bits.deps_ex[issue_id_1], UInt<1>(0h0) else : when issue_entry_1.bits.complete_on_issue : connect entries_ld[0].bits.deps_ex[issue_id_1], UInt<1>(0h0) node _T_4869 = eq(UInt<2>(0h1), UInt<2>(0h0)) when _T_4869 : connect entries_ld[1].bits.deps_ex[issue_id_1], UInt<1>(0h0) else : when issue_entry_1.bits.complete_on_issue : connect entries_ld[1].bits.deps_ex[issue_id_1], UInt<1>(0h0) node _T_4870 = eq(UInt<2>(0h1), UInt<2>(0h0)) when _T_4870 : connect entries_ld[2].bits.deps_ex[issue_id_1], UInt<1>(0h0) else : when issue_entry_1.bits.complete_on_issue : connect entries_ld[2].bits.deps_ex[issue_id_1], UInt<1>(0h0) node _T_4871 = eq(UInt<2>(0h1), UInt<2>(0h0)) when _T_4871 : connect entries_ld[3].bits.deps_ex[issue_id_1], UInt<1>(0h0) else : when issue_entry_1.bits.complete_on_issue : connect entries_ld[3].bits.deps_ex[issue_id_1], UInt<1>(0h0) node _T_4872 = eq(UInt<2>(0h1), UInt<2>(0h0)) when _T_4872 : connect entries_ld[4].bits.deps_ex[issue_id_1], UInt<1>(0h0) else : when issue_entry_1.bits.complete_on_issue : connect entries_ld[4].bits.deps_ex[issue_id_1], UInt<1>(0h0) node _T_4873 = eq(UInt<2>(0h1), UInt<2>(0h0)) when _T_4873 : connect entries_ld[5].bits.deps_ex[issue_id_1], UInt<1>(0h0) else : when issue_entry_1.bits.complete_on_issue : connect entries_ld[5].bits.deps_ex[issue_id_1], UInt<1>(0h0) node _T_4874 = eq(UInt<2>(0h1), UInt<2>(0h0)) when _T_4874 : connect entries_ld[6].bits.deps_ex[issue_id_1], UInt<1>(0h0) else : when issue_entry_1.bits.complete_on_issue : connect entries_ld[6].bits.deps_ex[issue_id_1], UInt<1>(0h0) node _T_4875 = eq(UInt<2>(0h1), UInt<2>(0h0)) when _T_4875 : connect entries_ld[7].bits.deps_ex[issue_id_1], UInt<1>(0h0) else : when issue_entry_1.bits.complete_on_issue : connect entries_ld[7].bits.deps_ex[issue_id_1], UInt<1>(0h0) node _T_4876 = eq(UInt<2>(0h1), UInt<2>(0h1)) when _T_4876 : connect entries_ex[0].bits.deps_ex[issue_id_1], UInt<1>(0h0) else : when issue_entry_1.bits.complete_on_issue : connect entries_ex[0].bits.deps_ex[issue_id_1], UInt<1>(0h0) node _T_4877 = eq(UInt<2>(0h1), UInt<2>(0h1)) when _T_4877 : connect entries_ex[1].bits.deps_ex[issue_id_1], UInt<1>(0h0) else : when issue_entry_1.bits.complete_on_issue : connect entries_ex[1].bits.deps_ex[issue_id_1], UInt<1>(0h0) node _T_4878 = eq(UInt<2>(0h1), UInt<2>(0h1)) when _T_4878 : connect entries_ex[2].bits.deps_ex[issue_id_1], UInt<1>(0h0) else : when issue_entry_1.bits.complete_on_issue : connect entries_ex[2].bits.deps_ex[issue_id_1], UInt<1>(0h0) node _T_4879 = eq(UInt<2>(0h1), UInt<2>(0h1)) when _T_4879 : connect entries_ex[3].bits.deps_ex[issue_id_1], UInt<1>(0h0) else : when issue_entry_1.bits.complete_on_issue : connect entries_ex[3].bits.deps_ex[issue_id_1], UInt<1>(0h0) node _T_4880 = eq(UInt<2>(0h1), UInt<2>(0h1)) when _T_4880 : connect entries_ex[4].bits.deps_ex[issue_id_1], UInt<1>(0h0) else : when issue_entry_1.bits.complete_on_issue : connect entries_ex[4].bits.deps_ex[issue_id_1], UInt<1>(0h0) node _T_4881 = eq(UInt<2>(0h1), UInt<2>(0h1)) when _T_4881 : connect entries_ex[5].bits.deps_ex[issue_id_1], UInt<1>(0h0) else : when issue_entry_1.bits.complete_on_issue : connect entries_ex[5].bits.deps_ex[issue_id_1], UInt<1>(0h0) node _T_4882 = eq(UInt<2>(0h1), UInt<2>(0h1)) when _T_4882 : connect entries_ex[6].bits.deps_ex[issue_id_1], UInt<1>(0h0) else : when issue_entry_1.bits.complete_on_issue : connect entries_ex[6].bits.deps_ex[issue_id_1], UInt<1>(0h0) node _T_4883 = eq(UInt<2>(0h1), UInt<2>(0h1)) when _T_4883 : connect entries_ex[7].bits.deps_ex[issue_id_1], UInt<1>(0h0) else : when issue_entry_1.bits.complete_on_issue : connect entries_ex[7].bits.deps_ex[issue_id_1], UInt<1>(0h0) node _T_4884 = eq(UInt<2>(0h1), UInt<2>(0h1)) when _T_4884 : connect entries_ex[8].bits.deps_ex[issue_id_1], UInt<1>(0h0) else : when issue_entry_1.bits.complete_on_issue : connect entries_ex[8].bits.deps_ex[issue_id_1], UInt<1>(0h0) node _T_4885 = eq(UInt<2>(0h1), UInt<2>(0h1)) when _T_4885 : connect entries_ex[9].bits.deps_ex[issue_id_1], UInt<1>(0h0) else : when issue_entry_1.bits.complete_on_issue : connect entries_ex[9].bits.deps_ex[issue_id_1], UInt<1>(0h0) node _T_4886 = eq(UInt<2>(0h1), UInt<2>(0h1)) when _T_4886 : connect entries_ex[10].bits.deps_ex[issue_id_1], UInt<1>(0h0) else : when issue_entry_1.bits.complete_on_issue : connect entries_ex[10].bits.deps_ex[issue_id_1], UInt<1>(0h0) node _T_4887 = eq(UInt<2>(0h1), UInt<2>(0h1)) when _T_4887 : connect entries_ex[11].bits.deps_ex[issue_id_1], UInt<1>(0h0) else : when issue_entry_1.bits.complete_on_issue : connect entries_ex[11].bits.deps_ex[issue_id_1], UInt<1>(0h0) node _T_4888 = eq(UInt<2>(0h1), UInt<2>(0h1)) when _T_4888 : connect entries_ex[12].bits.deps_ex[issue_id_1], UInt<1>(0h0) else : when issue_entry_1.bits.complete_on_issue : connect entries_ex[12].bits.deps_ex[issue_id_1], UInt<1>(0h0) node _T_4889 = eq(UInt<2>(0h1), UInt<2>(0h1)) when _T_4889 : connect entries_ex[13].bits.deps_ex[issue_id_1], UInt<1>(0h0) else : when issue_entry_1.bits.complete_on_issue : connect entries_ex[13].bits.deps_ex[issue_id_1], UInt<1>(0h0) node _T_4890 = eq(UInt<2>(0h1), UInt<2>(0h1)) when _T_4890 : connect entries_ex[14].bits.deps_ex[issue_id_1], UInt<1>(0h0) else : when issue_entry_1.bits.complete_on_issue : connect entries_ex[14].bits.deps_ex[issue_id_1], UInt<1>(0h0) node _T_4891 = eq(UInt<2>(0h1), UInt<2>(0h1)) when _T_4891 : connect entries_ex[15].bits.deps_ex[issue_id_1], UInt<1>(0h0) else : when issue_entry_1.bits.complete_on_issue : connect entries_ex[15].bits.deps_ex[issue_id_1], UInt<1>(0h0) node _T_4892 = eq(UInt<2>(0h1), UInt<2>(0h2)) when _T_4892 : connect entries_st[0].bits.deps_ex[issue_id_1], UInt<1>(0h0) else : when issue_entry_1.bits.complete_on_issue : connect entries_st[0].bits.deps_ex[issue_id_1], UInt<1>(0h0) node _T_4893 = eq(UInt<2>(0h1), UInt<2>(0h2)) when _T_4893 : connect entries_st[1].bits.deps_ex[issue_id_1], UInt<1>(0h0) else : when issue_entry_1.bits.complete_on_issue : connect entries_st[1].bits.deps_ex[issue_id_1], UInt<1>(0h0) node _T_4894 = eq(UInt<2>(0h1), UInt<2>(0h2)) when _T_4894 : connect entries_st[2].bits.deps_ex[issue_id_1], UInt<1>(0h0) else : when issue_entry_1.bits.complete_on_issue : connect entries_st[2].bits.deps_ex[issue_id_1], UInt<1>(0h0) node _T_4895 = eq(UInt<2>(0h1), UInt<2>(0h2)) when _T_4895 : connect entries_st[3].bits.deps_ex[issue_id_1], UInt<1>(0h0) else : when issue_entry_1.bits.complete_on_issue : connect entries_st[3].bits.deps_ex[issue_id_1], UInt<1>(0h0) node _T_4896 = eq(UInt<2>(0h1), UInt<2>(0h0)) when _T_4896 : node _conv_ld_issue_completed_T_1 = and(entries_ex[issue_id_1].bits.complete_on_issue, entries_ex[issue_id_1].bits.cmd.from_conv_fsm) connect conv_ld_issue_completed, _conv_ld_issue_completed_T_1 node _T_4897 = eq(UInt<2>(0h1), UInt<2>(0h2)) when _T_4897 : node _conv_st_issue_completed_T_1 = and(entries_ex[issue_id_1].bits.complete_on_issue, entries_ex[issue_id_1].bits.cmd.from_conv_fsm) connect conv_st_issue_completed, _conv_st_issue_completed_T_1 node _T_4898 = eq(UInt<2>(0h1), UInt<2>(0h1)) when _T_4898 : node _conv_ex_issue_completed_T_1 = and(entries_ex[issue_id_1].bits.complete_on_issue, entries_ex[issue_id_1].bits.cmd.from_conv_fsm) connect conv_ex_issue_completed, _conv_ex_issue_completed_T_1 node _T_4899 = eq(UInt<2>(0h1), UInt<2>(0h0)) when _T_4899 : node _matmul_ld_issue_completed_T_1 = and(entries_ex[issue_id_1].bits.complete_on_issue, entries_ex[issue_id_1].bits.cmd.from_matmul_fsm) connect matmul_ld_issue_completed, _matmul_ld_issue_completed_T_1 node _T_4900 = eq(UInt<2>(0h1), UInt<2>(0h2)) when _T_4900 : node _matmul_st_issue_completed_T_1 = and(entries_ex[issue_id_1].bits.complete_on_issue, entries_ex[issue_id_1].bits.cmd.from_matmul_fsm) connect matmul_st_issue_completed, _matmul_st_issue_completed_T_1 node _T_4901 = eq(UInt<2>(0h1), UInt<2>(0h1)) when _T_4901 : node _matmul_ex_issue_completed_T_1 = and(entries_ex[issue_id_1].bits.complete_on_issue, entries_ex[issue_id_1].bits.cmd.from_matmul_fsm) connect matmul_ex_issue_completed, _matmul_ex_issue_completed_T_1 node _issue_valids_T_720 = or(entries_st[0].bits.deps_ld[0], entries_st[0].bits.deps_ld[1]) node _issue_valids_T_721 = or(_issue_valids_T_720, entries_st[0].bits.deps_ld[2]) node _issue_valids_T_722 = or(_issue_valids_T_721, entries_st[0].bits.deps_ld[3]) node _issue_valids_T_723 = or(_issue_valids_T_722, entries_st[0].bits.deps_ld[4]) node _issue_valids_T_724 = or(_issue_valids_T_723, entries_st[0].bits.deps_ld[5]) node _issue_valids_T_725 = or(_issue_valids_T_724, entries_st[0].bits.deps_ld[6]) node _issue_valids_T_726 = or(_issue_valids_T_725, entries_st[0].bits.deps_ld[7]) node _issue_valids_T_727 = or(entries_st[0].bits.deps_ex[0], entries_st[0].bits.deps_ex[1]) node _issue_valids_T_728 = or(_issue_valids_T_727, entries_st[0].bits.deps_ex[2]) node _issue_valids_T_729 = or(_issue_valids_T_728, entries_st[0].bits.deps_ex[3]) node _issue_valids_T_730 = or(_issue_valids_T_729, entries_st[0].bits.deps_ex[4]) node _issue_valids_T_731 = or(_issue_valids_T_730, entries_st[0].bits.deps_ex[5]) node _issue_valids_T_732 = or(_issue_valids_T_731, entries_st[0].bits.deps_ex[6]) node _issue_valids_T_733 = or(_issue_valids_T_732, entries_st[0].bits.deps_ex[7]) node _issue_valids_T_734 = or(_issue_valids_T_733, entries_st[0].bits.deps_ex[8]) node _issue_valids_T_735 = or(_issue_valids_T_734, entries_st[0].bits.deps_ex[9]) node _issue_valids_T_736 = or(_issue_valids_T_735, entries_st[0].bits.deps_ex[10]) node _issue_valids_T_737 = or(_issue_valids_T_736, entries_st[0].bits.deps_ex[11]) node _issue_valids_T_738 = or(_issue_valids_T_737, entries_st[0].bits.deps_ex[12]) node _issue_valids_T_739 = or(_issue_valids_T_738, entries_st[0].bits.deps_ex[13]) node _issue_valids_T_740 = or(_issue_valids_T_739, entries_st[0].bits.deps_ex[14]) node _issue_valids_T_741 = or(_issue_valids_T_740, entries_st[0].bits.deps_ex[15]) node _issue_valids_T_742 = or(_issue_valids_T_726, _issue_valids_T_741) node _issue_valids_T_743 = or(entries_st[0].bits.deps_st[0], entries_st[0].bits.deps_st[1]) node _issue_valids_T_744 = or(_issue_valids_T_743, entries_st[0].bits.deps_st[2]) node _issue_valids_T_745 = or(_issue_valids_T_744, entries_st[0].bits.deps_st[3]) node _issue_valids_T_746 = or(_issue_valids_T_742, _issue_valids_T_745) node _issue_valids_T_747 = eq(_issue_valids_T_746, UInt<1>(0h0)) node _issue_valids_T_748 = and(entries_st[0].valid, _issue_valids_T_747) node _issue_valids_T_749 = eq(entries_st[0].bits.issued, UInt<1>(0h0)) node issue_valids_0_2 = and(_issue_valids_T_748, _issue_valids_T_749) node _issue_valids_T_750 = or(entries_st[1].bits.deps_ld[0], entries_st[1].bits.deps_ld[1]) node _issue_valids_T_751 = or(_issue_valids_T_750, entries_st[1].bits.deps_ld[2]) node _issue_valids_T_752 = or(_issue_valids_T_751, entries_st[1].bits.deps_ld[3]) node _issue_valids_T_753 = or(_issue_valids_T_752, entries_st[1].bits.deps_ld[4]) node _issue_valids_T_754 = or(_issue_valids_T_753, entries_st[1].bits.deps_ld[5]) node _issue_valids_T_755 = or(_issue_valids_T_754, entries_st[1].bits.deps_ld[6]) node _issue_valids_T_756 = or(_issue_valids_T_755, entries_st[1].bits.deps_ld[7]) node _issue_valids_T_757 = or(entries_st[1].bits.deps_ex[0], entries_st[1].bits.deps_ex[1]) node _issue_valids_T_758 = or(_issue_valids_T_757, entries_st[1].bits.deps_ex[2]) node _issue_valids_T_759 = or(_issue_valids_T_758, entries_st[1].bits.deps_ex[3]) node _issue_valids_T_760 = or(_issue_valids_T_759, entries_st[1].bits.deps_ex[4]) node _issue_valids_T_761 = or(_issue_valids_T_760, entries_st[1].bits.deps_ex[5]) node _issue_valids_T_762 = or(_issue_valids_T_761, entries_st[1].bits.deps_ex[6]) node _issue_valids_T_763 = or(_issue_valids_T_762, entries_st[1].bits.deps_ex[7]) node _issue_valids_T_764 = or(_issue_valids_T_763, entries_st[1].bits.deps_ex[8]) node _issue_valids_T_765 = or(_issue_valids_T_764, entries_st[1].bits.deps_ex[9]) node _issue_valids_T_766 = or(_issue_valids_T_765, entries_st[1].bits.deps_ex[10]) node _issue_valids_T_767 = or(_issue_valids_T_766, entries_st[1].bits.deps_ex[11]) node _issue_valids_T_768 = or(_issue_valids_T_767, entries_st[1].bits.deps_ex[12]) node _issue_valids_T_769 = or(_issue_valids_T_768, entries_st[1].bits.deps_ex[13]) node _issue_valids_T_770 = or(_issue_valids_T_769, entries_st[1].bits.deps_ex[14]) node _issue_valids_T_771 = or(_issue_valids_T_770, entries_st[1].bits.deps_ex[15]) node _issue_valids_T_772 = or(_issue_valids_T_756, _issue_valids_T_771) node _issue_valids_T_773 = or(entries_st[1].bits.deps_st[0], entries_st[1].bits.deps_st[1]) node _issue_valids_T_774 = or(_issue_valids_T_773, entries_st[1].bits.deps_st[2]) node _issue_valids_T_775 = or(_issue_valids_T_774, entries_st[1].bits.deps_st[3]) node _issue_valids_T_776 = or(_issue_valids_T_772, _issue_valids_T_775) node _issue_valids_T_777 = eq(_issue_valids_T_776, UInt<1>(0h0)) node _issue_valids_T_778 = and(entries_st[1].valid, _issue_valids_T_777) node _issue_valids_T_779 = eq(entries_st[1].bits.issued, UInt<1>(0h0)) node issue_valids_1_2 = and(_issue_valids_T_778, _issue_valids_T_779) node _issue_valids_T_780 = or(entries_st[2].bits.deps_ld[0], entries_st[2].bits.deps_ld[1]) node _issue_valids_T_781 = or(_issue_valids_T_780, entries_st[2].bits.deps_ld[2]) node _issue_valids_T_782 = or(_issue_valids_T_781, entries_st[2].bits.deps_ld[3]) node _issue_valids_T_783 = or(_issue_valids_T_782, entries_st[2].bits.deps_ld[4]) node _issue_valids_T_784 = or(_issue_valids_T_783, entries_st[2].bits.deps_ld[5]) node _issue_valids_T_785 = or(_issue_valids_T_784, entries_st[2].bits.deps_ld[6]) node _issue_valids_T_786 = or(_issue_valids_T_785, entries_st[2].bits.deps_ld[7]) node _issue_valids_T_787 = or(entries_st[2].bits.deps_ex[0], entries_st[2].bits.deps_ex[1]) node _issue_valids_T_788 = or(_issue_valids_T_787, entries_st[2].bits.deps_ex[2]) node _issue_valids_T_789 = or(_issue_valids_T_788, entries_st[2].bits.deps_ex[3]) node _issue_valids_T_790 = or(_issue_valids_T_789, entries_st[2].bits.deps_ex[4]) node _issue_valids_T_791 = or(_issue_valids_T_790, entries_st[2].bits.deps_ex[5]) node _issue_valids_T_792 = or(_issue_valids_T_791, entries_st[2].bits.deps_ex[6]) node _issue_valids_T_793 = or(_issue_valids_T_792, entries_st[2].bits.deps_ex[7]) node _issue_valids_T_794 = or(_issue_valids_T_793, entries_st[2].bits.deps_ex[8]) node _issue_valids_T_795 = or(_issue_valids_T_794, entries_st[2].bits.deps_ex[9]) node _issue_valids_T_796 = or(_issue_valids_T_795, entries_st[2].bits.deps_ex[10]) node _issue_valids_T_797 = or(_issue_valids_T_796, entries_st[2].bits.deps_ex[11]) node _issue_valids_T_798 = or(_issue_valids_T_797, entries_st[2].bits.deps_ex[12]) node _issue_valids_T_799 = or(_issue_valids_T_798, entries_st[2].bits.deps_ex[13]) node _issue_valids_T_800 = or(_issue_valids_T_799, entries_st[2].bits.deps_ex[14]) node _issue_valids_T_801 = or(_issue_valids_T_800, entries_st[2].bits.deps_ex[15]) node _issue_valids_T_802 = or(_issue_valids_T_786, _issue_valids_T_801) node _issue_valids_T_803 = or(entries_st[2].bits.deps_st[0], entries_st[2].bits.deps_st[1]) node _issue_valids_T_804 = or(_issue_valids_T_803, entries_st[2].bits.deps_st[2]) node _issue_valids_T_805 = or(_issue_valids_T_804, entries_st[2].bits.deps_st[3]) node _issue_valids_T_806 = or(_issue_valids_T_802, _issue_valids_T_805) node _issue_valids_T_807 = eq(_issue_valids_T_806, UInt<1>(0h0)) node _issue_valids_T_808 = and(entries_st[2].valid, _issue_valids_T_807) node _issue_valids_T_809 = eq(entries_st[2].bits.issued, UInt<1>(0h0)) node issue_valids_2_2 = and(_issue_valids_T_808, _issue_valids_T_809) node _issue_valids_T_810 = or(entries_st[3].bits.deps_ld[0], entries_st[3].bits.deps_ld[1]) node _issue_valids_T_811 = or(_issue_valids_T_810, entries_st[3].bits.deps_ld[2]) node _issue_valids_T_812 = or(_issue_valids_T_811, entries_st[3].bits.deps_ld[3]) node _issue_valids_T_813 = or(_issue_valids_T_812, entries_st[3].bits.deps_ld[4]) node _issue_valids_T_814 = or(_issue_valids_T_813, entries_st[3].bits.deps_ld[5]) node _issue_valids_T_815 = or(_issue_valids_T_814, entries_st[3].bits.deps_ld[6]) node _issue_valids_T_816 = or(_issue_valids_T_815, entries_st[3].bits.deps_ld[7]) node _issue_valids_T_817 = or(entries_st[3].bits.deps_ex[0], entries_st[3].bits.deps_ex[1]) node _issue_valids_T_818 = or(_issue_valids_T_817, entries_st[3].bits.deps_ex[2]) node _issue_valids_T_819 = or(_issue_valids_T_818, entries_st[3].bits.deps_ex[3]) node _issue_valids_T_820 = or(_issue_valids_T_819, entries_st[3].bits.deps_ex[4]) node _issue_valids_T_821 = or(_issue_valids_T_820, entries_st[3].bits.deps_ex[5]) node _issue_valids_T_822 = or(_issue_valids_T_821, entries_st[3].bits.deps_ex[6]) node _issue_valids_T_823 = or(_issue_valids_T_822, entries_st[3].bits.deps_ex[7]) node _issue_valids_T_824 = or(_issue_valids_T_823, entries_st[3].bits.deps_ex[8]) node _issue_valids_T_825 = or(_issue_valids_T_824, entries_st[3].bits.deps_ex[9]) node _issue_valids_T_826 = or(_issue_valids_T_825, entries_st[3].bits.deps_ex[10]) node _issue_valids_T_827 = or(_issue_valids_T_826, entries_st[3].bits.deps_ex[11]) node _issue_valids_T_828 = or(_issue_valids_T_827, entries_st[3].bits.deps_ex[12]) node _issue_valids_T_829 = or(_issue_valids_T_828, entries_st[3].bits.deps_ex[13]) node _issue_valids_T_830 = or(_issue_valids_T_829, entries_st[3].bits.deps_ex[14]) node _issue_valids_T_831 = or(_issue_valids_T_830, entries_st[3].bits.deps_ex[15]) node _issue_valids_T_832 = or(_issue_valids_T_816, _issue_valids_T_831) node _issue_valids_T_833 = or(entries_st[3].bits.deps_st[0], entries_st[3].bits.deps_st[1]) node _issue_valids_T_834 = or(_issue_valids_T_833, entries_st[3].bits.deps_st[2]) node _issue_valids_T_835 = or(_issue_valids_T_834, entries_st[3].bits.deps_st[3]) node _issue_valids_T_836 = or(_issue_valids_T_832, _issue_valids_T_835) node _issue_valids_T_837 = eq(_issue_valids_T_836, UInt<1>(0h0)) node _issue_valids_T_838 = and(entries_st[3].valid, _issue_valids_T_837) node _issue_valids_T_839 = eq(entries_st[3].bits.issued, UInt<1>(0h0)) node issue_valids_3_2 = and(_issue_valids_T_838, _issue_valids_T_839) node _issue_sel_enc_T_22 = mux(issue_valids_3_2, UInt<4>(0h8), UInt<4>(0h0)) node _issue_sel_enc_T_23 = mux(issue_valids_2_2, UInt<4>(0h4), _issue_sel_enc_T_22) node _issue_sel_enc_T_24 = mux(issue_valids_1_2, UInt<4>(0h2), _issue_sel_enc_T_23) node issue_sel_enc_2 = mux(issue_valids_0_2, UInt<4>(0h1), _issue_sel_enc_T_24) node issue_sel_0_2 = bits(issue_sel_enc_2, 0, 0) node issue_sel_1_2 = bits(issue_sel_enc_2, 1, 1) node issue_sel_2_2 = bits(issue_sel_enc_2, 2, 2) node issue_sel_3_2 = bits(issue_sel_enc_2, 3, 3) node issue_id_lo_7 = cat(issue_sel_1_2, issue_sel_0_2) node issue_id_hi_7 = cat(issue_sel_3_2, issue_sel_2_2) node _issue_id_T_17 = cat(issue_id_hi_7, issue_id_lo_7) node issue_id_hi_8 = bits(_issue_id_T_17, 3, 2) node issue_id_lo_8 = bits(_issue_id_T_17, 1, 0) node _issue_id_T_18 = orr(issue_id_hi_8) node _issue_id_T_19 = or(issue_id_hi_8, issue_id_lo_8) node _issue_id_T_20 = bits(_issue_id_T_19, 1, 1) node issue_id_2 = cat(_issue_id_T_18, _issue_id_T_20) node _global_issue_id_T_1 = pad(issue_id_2, 4) node global_issue_id_2 = cat(UInt<2>(0h2), _global_issue_id_T_1) wire issue_entry_2 : { valid : UInt<1>, bits : { q : UInt<2>, is_config : UInt<1>, opa : { valid : UInt<1>, bits : { start : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, end : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, wraps_around : UInt<1>}}, opa_is_dst : UInt<1>, opb : { valid : UInt<1>, bits : { start : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, end : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, wraps_around : UInt<1>}}, issued : UInt<1>, complete_on_issue : UInt<1>, cmd : { cmd : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, rob_id : { valid : UInt<1>, bits : UInt<6>}, from_matmul_fsm : UInt<1>, from_conv_fsm : UInt<1>}, deps_ld : UInt<1>[8], deps_ex : UInt<1>[16], deps_st : UInt<1>[4], allocated_at : UInt<32>}} wire _issue_entry_WIRE_286 : { q : UInt<2>, is_config : UInt<1>, opa : { valid : UInt<1>, bits : { start : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, end : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, wraps_around : UInt<1>}}, opa_is_dst : UInt<1>, opb : { valid : UInt<1>, bits : { start : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, end : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, wraps_around : UInt<1>}}, issued : UInt<1>, complete_on_issue : UInt<1>, cmd : { cmd : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, rob_id : { valid : UInt<1>, bits : UInt<6>}, from_matmul_fsm : UInt<1>, from_conv_fsm : UInt<1>}, deps_ld : UInt<1>[8], deps_ex : UInt<1>[16], deps_st : UInt<1>[4], allocated_at : UInt<32>} node _issue_entry_T_5524 = mux(issue_sel_0_2, entries_st[0].bits.allocated_at, UInt<1>(0h0)) node _issue_entry_T_5525 = mux(issue_sel_1_2, entries_st[1].bits.allocated_at, UInt<1>(0h0)) node _issue_entry_T_5526 = mux(issue_sel_2_2, entries_st[2].bits.allocated_at, UInt<1>(0h0)) node _issue_entry_T_5527 = mux(issue_sel_3_2, entries_st[3].bits.allocated_at, UInt<1>(0h0)) node _issue_entry_T_5528 = or(_issue_entry_T_5524, _issue_entry_T_5525) node _issue_entry_T_5529 = or(_issue_entry_T_5528, _issue_entry_T_5526) node _issue_entry_T_5530 = or(_issue_entry_T_5529, _issue_entry_T_5527) wire _issue_entry_WIRE_287 : UInt<32> connect _issue_entry_WIRE_287, _issue_entry_T_5530 connect _issue_entry_WIRE_286.allocated_at, _issue_entry_WIRE_287 wire _issue_entry_WIRE_288 : UInt<1>[4] node _issue_entry_T_5531 = mux(issue_sel_0_2, entries_st[0].bits.deps_st[0], UInt<1>(0h0)) node _issue_entry_T_5532 = mux(issue_sel_1_2, entries_st[1].bits.deps_st[0], UInt<1>(0h0)) node _issue_entry_T_5533 = mux(issue_sel_2_2, entries_st[2].bits.deps_st[0], UInt<1>(0h0)) node _issue_entry_T_5534 = mux(issue_sel_3_2, entries_st[3].bits.deps_st[0], UInt<1>(0h0)) node _issue_entry_T_5535 = or(_issue_entry_T_5531, _issue_entry_T_5532) node _issue_entry_T_5536 = or(_issue_entry_T_5535, _issue_entry_T_5533) node _issue_entry_T_5537 = or(_issue_entry_T_5536, _issue_entry_T_5534) wire _issue_entry_WIRE_289 : UInt<1> connect _issue_entry_WIRE_289, _issue_entry_T_5537 connect _issue_entry_WIRE_288[0], _issue_entry_WIRE_289 node _issue_entry_T_5538 = mux(issue_sel_0_2, entries_st[0].bits.deps_st[1], UInt<1>(0h0)) node _issue_entry_T_5539 = mux(issue_sel_1_2, entries_st[1].bits.deps_st[1], UInt<1>(0h0)) node _issue_entry_T_5540 = mux(issue_sel_2_2, entries_st[2].bits.deps_st[1], UInt<1>(0h0)) node _issue_entry_T_5541 = mux(issue_sel_3_2, entries_st[3].bits.deps_st[1], UInt<1>(0h0)) node _issue_entry_T_5542 = or(_issue_entry_T_5538, _issue_entry_T_5539) node _issue_entry_T_5543 = or(_issue_entry_T_5542, _issue_entry_T_5540) node _issue_entry_T_5544 = or(_issue_entry_T_5543, _issue_entry_T_5541) wire _issue_entry_WIRE_290 : UInt<1> connect _issue_entry_WIRE_290, _issue_entry_T_5544 connect _issue_entry_WIRE_288[1], _issue_entry_WIRE_290 node _issue_entry_T_5545 = mux(issue_sel_0_2, entries_st[0].bits.deps_st[2], UInt<1>(0h0)) node _issue_entry_T_5546 = mux(issue_sel_1_2, entries_st[1].bits.deps_st[2], UInt<1>(0h0)) node _issue_entry_T_5547 = mux(issue_sel_2_2, entries_st[2].bits.deps_st[2], UInt<1>(0h0)) node _issue_entry_T_5548 = mux(issue_sel_3_2, entries_st[3].bits.deps_st[2], UInt<1>(0h0)) node _issue_entry_T_5549 = or(_issue_entry_T_5545, _issue_entry_T_5546) node _issue_entry_T_5550 = or(_issue_entry_T_5549, _issue_entry_T_5547) node _issue_entry_T_5551 = or(_issue_entry_T_5550, _issue_entry_T_5548) wire _issue_entry_WIRE_291 : UInt<1> connect _issue_entry_WIRE_291, _issue_entry_T_5551 connect _issue_entry_WIRE_288[2], _issue_entry_WIRE_291 node _issue_entry_T_5552 = mux(issue_sel_0_2, entries_st[0].bits.deps_st[3], UInt<1>(0h0)) node _issue_entry_T_5553 = mux(issue_sel_1_2, entries_st[1].bits.deps_st[3], UInt<1>(0h0)) node _issue_entry_T_5554 = mux(issue_sel_2_2, entries_st[2].bits.deps_st[3], UInt<1>(0h0)) node _issue_entry_T_5555 = mux(issue_sel_3_2, entries_st[3].bits.deps_st[3], UInt<1>(0h0)) node _issue_entry_T_5556 = or(_issue_entry_T_5552, _issue_entry_T_5553) node _issue_entry_T_5557 = or(_issue_entry_T_5556, _issue_entry_T_5554) node _issue_entry_T_5558 = or(_issue_entry_T_5557, _issue_entry_T_5555) wire _issue_entry_WIRE_292 : UInt<1> connect _issue_entry_WIRE_292, _issue_entry_T_5558 connect _issue_entry_WIRE_288[3], _issue_entry_WIRE_292 connect _issue_entry_WIRE_286.deps_st, _issue_entry_WIRE_288 wire _issue_entry_WIRE_293 : UInt<1>[16] node _issue_entry_T_5559 = mux(issue_sel_0_2, entries_st[0].bits.deps_ex[0], UInt<1>(0h0)) node _issue_entry_T_5560 = mux(issue_sel_1_2, entries_st[1].bits.deps_ex[0], UInt<1>(0h0)) node _issue_entry_T_5561 = mux(issue_sel_2_2, entries_st[2].bits.deps_ex[0], UInt<1>(0h0)) node _issue_entry_T_5562 = mux(issue_sel_3_2, entries_st[3].bits.deps_ex[0], UInt<1>(0h0)) node _issue_entry_T_5563 = or(_issue_entry_T_5559, _issue_entry_T_5560) node _issue_entry_T_5564 = or(_issue_entry_T_5563, _issue_entry_T_5561) node _issue_entry_T_5565 = or(_issue_entry_T_5564, _issue_entry_T_5562) wire _issue_entry_WIRE_294 : UInt<1> connect _issue_entry_WIRE_294, _issue_entry_T_5565 connect _issue_entry_WIRE_293[0], _issue_entry_WIRE_294 node _issue_entry_T_5566 = mux(issue_sel_0_2, entries_st[0].bits.deps_ex[1], UInt<1>(0h0)) node _issue_entry_T_5567 = mux(issue_sel_1_2, entries_st[1].bits.deps_ex[1], UInt<1>(0h0)) node _issue_entry_T_5568 = mux(issue_sel_2_2, entries_st[2].bits.deps_ex[1], UInt<1>(0h0)) node _issue_entry_T_5569 = mux(issue_sel_3_2, entries_st[3].bits.deps_ex[1], UInt<1>(0h0)) node _issue_entry_T_5570 = or(_issue_entry_T_5566, _issue_entry_T_5567) node _issue_entry_T_5571 = or(_issue_entry_T_5570, _issue_entry_T_5568) node _issue_entry_T_5572 = or(_issue_entry_T_5571, _issue_entry_T_5569) wire _issue_entry_WIRE_295 : UInt<1> connect _issue_entry_WIRE_295, _issue_entry_T_5572 connect _issue_entry_WIRE_293[1], _issue_entry_WIRE_295 node _issue_entry_T_5573 = mux(issue_sel_0_2, entries_st[0].bits.deps_ex[2], UInt<1>(0h0)) node _issue_entry_T_5574 = mux(issue_sel_1_2, entries_st[1].bits.deps_ex[2], UInt<1>(0h0)) node _issue_entry_T_5575 = mux(issue_sel_2_2, entries_st[2].bits.deps_ex[2], UInt<1>(0h0)) node _issue_entry_T_5576 = mux(issue_sel_3_2, entries_st[3].bits.deps_ex[2], UInt<1>(0h0)) node _issue_entry_T_5577 = or(_issue_entry_T_5573, _issue_entry_T_5574) node _issue_entry_T_5578 = or(_issue_entry_T_5577, _issue_entry_T_5575) node _issue_entry_T_5579 = or(_issue_entry_T_5578, _issue_entry_T_5576) wire _issue_entry_WIRE_296 : UInt<1> connect _issue_entry_WIRE_296, _issue_entry_T_5579 connect _issue_entry_WIRE_293[2], _issue_entry_WIRE_296 node _issue_entry_T_5580 = mux(issue_sel_0_2, entries_st[0].bits.deps_ex[3], UInt<1>(0h0)) node _issue_entry_T_5581 = mux(issue_sel_1_2, entries_st[1].bits.deps_ex[3], UInt<1>(0h0)) node _issue_entry_T_5582 = mux(issue_sel_2_2, entries_st[2].bits.deps_ex[3], UInt<1>(0h0)) node _issue_entry_T_5583 = mux(issue_sel_3_2, entries_st[3].bits.deps_ex[3], UInt<1>(0h0)) node _issue_entry_T_5584 = or(_issue_entry_T_5580, _issue_entry_T_5581) node _issue_entry_T_5585 = or(_issue_entry_T_5584, _issue_entry_T_5582) node _issue_entry_T_5586 = or(_issue_entry_T_5585, _issue_entry_T_5583) wire _issue_entry_WIRE_297 : UInt<1> connect _issue_entry_WIRE_297, _issue_entry_T_5586 connect _issue_entry_WIRE_293[3], _issue_entry_WIRE_297 node _issue_entry_T_5587 = mux(issue_sel_0_2, entries_st[0].bits.deps_ex[4], UInt<1>(0h0)) node _issue_entry_T_5588 = mux(issue_sel_1_2, entries_st[1].bits.deps_ex[4], UInt<1>(0h0)) node _issue_entry_T_5589 = mux(issue_sel_2_2, entries_st[2].bits.deps_ex[4], UInt<1>(0h0)) node _issue_entry_T_5590 = mux(issue_sel_3_2, entries_st[3].bits.deps_ex[4], UInt<1>(0h0)) node _issue_entry_T_5591 = or(_issue_entry_T_5587, _issue_entry_T_5588) node _issue_entry_T_5592 = or(_issue_entry_T_5591, _issue_entry_T_5589) node _issue_entry_T_5593 = or(_issue_entry_T_5592, _issue_entry_T_5590) wire _issue_entry_WIRE_298 : UInt<1> connect _issue_entry_WIRE_298, _issue_entry_T_5593 connect _issue_entry_WIRE_293[4], _issue_entry_WIRE_298 node _issue_entry_T_5594 = mux(issue_sel_0_2, entries_st[0].bits.deps_ex[5], UInt<1>(0h0)) node _issue_entry_T_5595 = mux(issue_sel_1_2, entries_st[1].bits.deps_ex[5], UInt<1>(0h0)) node _issue_entry_T_5596 = mux(issue_sel_2_2, entries_st[2].bits.deps_ex[5], UInt<1>(0h0)) node _issue_entry_T_5597 = mux(issue_sel_3_2, entries_st[3].bits.deps_ex[5], UInt<1>(0h0)) node _issue_entry_T_5598 = or(_issue_entry_T_5594, _issue_entry_T_5595) node _issue_entry_T_5599 = or(_issue_entry_T_5598, _issue_entry_T_5596) node _issue_entry_T_5600 = or(_issue_entry_T_5599, _issue_entry_T_5597) wire _issue_entry_WIRE_299 : UInt<1> connect _issue_entry_WIRE_299, _issue_entry_T_5600 connect _issue_entry_WIRE_293[5], _issue_entry_WIRE_299 node _issue_entry_T_5601 = mux(issue_sel_0_2, entries_st[0].bits.deps_ex[6], UInt<1>(0h0)) node _issue_entry_T_5602 = mux(issue_sel_1_2, entries_st[1].bits.deps_ex[6], UInt<1>(0h0)) node _issue_entry_T_5603 = mux(issue_sel_2_2, entries_st[2].bits.deps_ex[6], UInt<1>(0h0)) node _issue_entry_T_5604 = mux(issue_sel_3_2, entries_st[3].bits.deps_ex[6], UInt<1>(0h0)) node _issue_entry_T_5605 = or(_issue_entry_T_5601, _issue_entry_T_5602) node _issue_entry_T_5606 = or(_issue_entry_T_5605, _issue_entry_T_5603) node _issue_entry_T_5607 = or(_issue_entry_T_5606, _issue_entry_T_5604) wire _issue_entry_WIRE_300 : UInt<1> connect _issue_entry_WIRE_300, _issue_entry_T_5607 connect _issue_entry_WIRE_293[6], _issue_entry_WIRE_300 node _issue_entry_T_5608 = mux(issue_sel_0_2, entries_st[0].bits.deps_ex[7], UInt<1>(0h0)) node _issue_entry_T_5609 = mux(issue_sel_1_2, entries_st[1].bits.deps_ex[7], UInt<1>(0h0)) node _issue_entry_T_5610 = mux(issue_sel_2_2, entries_st[2].bits.deps_ex[7], UInt<1>(0h0)) node _issue_entry_T_5611 = mux(issue_sel_3_2, entries_st[3].bits.deps_ex[7], UInt<1>(0h0)) node _issue_entry_T_5612 = or(_issue_entry_T_5608, _issue_entry_T_5609) node _issue_entry_T_5613 = or(_issue_entry_T_5612, _issue_entry_T_5610) node _issue_entry_T_5614 = or(_issue_entry_T_5613, _issue_entry_T_5611) wire _issue_entry_WIRE_301 : UInt<1> connect _issue_entry_WIRE_301, _issue_entry_T_5614 connect _issue_entry_WIRE_293[7], _issue_entry_WIRE_301 node _issue_entry_T_5615 = mux(issue_sel_0_2, entries_st[0].bits.deps_ex[8], UInt<1>(0h0)) node _issue_entry_T_5616 = mux(issue_sel_1_2, entries_st[1].bits.deps_ex[8], UInt<1>(0h0)) node _issue_entry_T_5617 = mux(issue_sel_2_2, entries_st[2].bits.deps_ex[8], UInt<1>(0h0)) node _issue_entry_T_5618 = mux(issue_sel_3_2, entries_st[3].bits.deps_ex[8], UInt<1>(0h0)) node _issue_entry_T_5619 = or(_issue_entry_T_5615, _issue_entry_T_5616) node _issue_entry_T_5620 = or(_issue_entry_T_5619, _issue_entry_T_5617) node _issue_entry_T_5621 = or(_issue_entry_T_5620, _issue_entry_T_5618) wire _issue_entry_WIRE_302 : UInt<1> connect _issue_entry_WIRE_302, _issue_entry_T_5621 connect _issue_entry_WIRE_293[8], _issue_entry_WIRE_302 node _issue_entry_T_5622 = mux(issue_sel_0_2, entries_st[0].bits.deps_ex[9], UInt<1>(0h0)) node _issue_entry_T_5623 = mux(issue_sel_1_2, entries_st[1].bits.deps_ex[9], UInt<1>(0h0)) node _issue_entry_T_5624 = mux(issue_sel_2_2, entries_st[2].bits.deps_ex[9], UInt<1>(0h0)) node _issue_entry_T_5625 = mux(issue_sel_3_2, entries_st[3].bits.deps_ex[9], UInt<1>(0h0)) node _issue_entry_T_5626 = or(_issue_entry_T_5622, _issue_entry_T_5623) node _issue_entry_T_5627 = or(_issue_entry_T_5626, _issue_entry_T_5624) node _issue_entry_T_5628 = or(_issue_entry_T_5627, _issue_entry_T_5625) wire _issue_entry_WIRE_303 : UInt<1> connect _issue_entry_WIRE_303, _issue_entry_T_5628 connect _issue_entry_WIRE_293[9], _issue_entry_WIRE_303 node _issue_entry_T_5629 = mux(issue_sel_0_2, entries_st[0].bits.deps_ex[10], UInt<1>(0h0)) node _issue_entry_T_5630 = mux(issue_sel_1_2, entries_st[1].bits.deps_ex[10], UInt<1>(0h0)) node _issue_entry_T_5631 = mux(issue_sel_2_2, entries_st[2].bits.deps_ex[10], UInt<1>(0h0)) node _issue_entry_T_5632 = mux(issue_sel_3_2, entries_st[3].bits.deps_ex[10], UInt<1>(0h0)) node _issue_entry_T_5633 = or(_issue_entry_T_5629, _issue_entry_T_5630) node _issue_entry_T_5634 = or(_issue_entry_T_5633, _issue_entry_T_5631) node _issue_entry_T_5635 = or(_issue_entry_T_5634, _issue_entry_T_5632) wire _issue_entry_WIRE_304 : UInt<1> connect _issue_entry_WIRE_304, _issue_entry_T_5635 connect _issue_entry_WIRE_293[10], _issue_entry_WIRE_304 node _issue_entry_T_5636 = mux(issue_sel_0_2, entries_st[0].bits.deps_ex[11], UInt<1>(0h0)) node _issue_entry_T_5637 = mux(issue_sel_1_2, entries_st[1].bits.deps_ex[11], UInt<1>(0h0)) node _issue_entry_T_5638 = mux(issue_sel_2_2, entries_st[2].bits.deps_ex[11], UInt<1>(0h0)) node _issue_entry_T_5639 = mux(issue_sel_3_2, entries_st[3].bits.deps_ex[11], UInt<1>(0h0)) node _issue_entry_T_5640 = or(_issue_entry_T_5636, _issue_entry_T_5637) node _issue_entry_T_5641 = or(_issue_entry_T_5640, _issue_entry_T_5638) node _issue_entry_T_5642 = or(_issue_entry_T_5641, _issue_entry_T_5639) wire _issue_entry_WIRE_305 : UInt<1> connect _issue_entry_WIRE_305, _issue_entry_T_5642 connect _issue_entry_WIRE_293[11], _issue_entry_WIRE_305 node _issue_entry_T_5643 = mux(issue_sel_0_2, entries_st[0].bits.deps_ex[12], UInt<1>(0h0)) node _issue_entry_T_5644 = mux(issue_sel_1_2, entries_st[1].bits.deps_ex[12], UInt<1>(0h0)) node _issue_entry_T_5645 = mux(issue_sel_2_2, entries_st[2].bits.deps_ex[12], UInt<1>(0h0)) node _issue_entry_T_5646 = mux(issue_sel_3_2, entries_st[3].bits.deps_ex[12], UInt<1>(0h0)) node _issue_entry_T_5647 = or(_issue_entry_T_5643, _issue_entry_T_5644) node _issue_entry_T_5648 = or(_issue_entry_T_5647, _issue_entry_T_5645) node _issue_entry_T_5649 = or(_issue_entry_T_5648, _issue_entry_T_5646) wire _issue_entry_WIRE_306 : UInt<1> connect _issue_entry_WIRE_306, _issue_entry_T_5649 connect _issue_entry_WIRE_293[12], _issue_entry_WIRE_306 node _issue_entry_T_5650 = mux(issue_sel_0_2, entries_st[0].bits.deps_ex[13], UInt<1>(0h0)) node _issue_entry_T_5651 = mux(issue_sel_1_2, entries_st[1].bits.deps_ex[13], UInt<1>(0h0)) node _issue_entry_T_5652 = mux(issue_sel_2_2, entries_st[2].bits.deps_ex[13], UInt<1>(0h0)) node _issue_entry_T_5653 = mux(issue_sel_3_2, entries_st[3].bits.deps_ex[13], UInt<1>(0h0)) node _issue_entry_T_5654 = or(_issue_entry_T_5650, _issue_entry_T_5651) node _issue_entry_T_5655 = or(_issue_entry_T_5654, _issue_entry_T_5652) node _issue_entry_T_5656 = or(_issue_entry_T_5655, _issue_entry_T_5653) wire _issue_entry_WIRE_307 : UInt<1> connect _issue_entry_WIRE_307, _issue_entry_T_5656 connect _issue_entry_WIRE_293[13], _issue_entry_WIRE_307 node _issue_entry_T_5657 = mux(issue_sel_0_2, entries_st[0].bits.deps_ex[14], UInt<1>(0h0)) node _issue_entry_T_5658 = mux(issue_sel_1_2, entries_st[1].bits.deps_ex[14], UInt<1>(0h0)) node _issue_entry_T_5659 = mux(issue_sel_2_2, entries_st[2].bits.deps_ex[14], UInt<1>(0h0)) node _issue_entry_T_5660 = mux(issue_sel_3_2, entries_st[3].bits.deps_ex[14], UInt<1>(0h0)) node _issue_entry_T_5661 = or(_issue_entry_T_5657, _issue_entry_T_5658) node _issue_entry_T_5662 = or(_issue_entry_T_5661, _issue_entry_T_5659) node _issue_entry_T_5663 = or(_issue_entry_T_5662, _issue_entry_T_5660) wire _issue_entry_WIRE_308 : UInt<1> connect _issue_entry_WIRE_308, _issue_entry_T_5663 connect _issue_entry_WIRE_293[14], _issue_entry_WIRE_308 node _issue_entry_T_5664 = mux(issue_sel_0_2, entries_st[0].bits.deps_ex[15], UInt<1>(0h0)) node _issue_entry_T_5665 = mux(issue_sel_1_2, entries_st[1].bits.deps_ex[15], UInt<1>(0h0)) node _issue_entry_T_5666 = mux(issue_sel_2_2, entries_st[2].bits.deps_ex[15], UInt<1>(0h0)) node _issue_entry_T_5667 = mux(issue_sel_3_2, entries_st[3].bits.deps_ex[15], UInt<1>(0h0)) node _issue_entry_T_5668 = or(_issue_entry_T_5664, _issue_entry_T_5665) node _issue_entry_T_5669 = or(_issue_entry_T_5668, _issue_entry_T_5666) node _issue_entry_T_5670 = or(_issue_entry_T_5669, _issue_entry_T_5667) wire _issue_entry_WIRE_309 : UInt<1> connect _issue_entry_WIRE_309, _issue_entry_T_5670 connect _issue_entry_WIRE_293[15], _issue_entry_WIRE_309 connect _issue_entry_WIRE_286.deps_ex, _issue_entry_WIRE_293 wire _issue_entry_WIRE_310 : UInt<1>[8] node _issue_entry_T_5671 = mux(issue_sel_0_2, entries_st[0].bits.deps_ld[0], UInt<1>(0h0)) node _issue_entry_T_5672 = mux(issue_sel_1_2, entries_st[1].bits.deps_ld[0], UInt<1>(0h0)) node _issue_entry_T_5673 = mux(issue_sel_2_2, entries_st[2].bits.deps_ld[0], UInt<1>(0h0)) node _issue_entry_T_5674 = mux(issue_sel_3_2, entries_st[3].bits.deps_ld[0], UInt<1>(0h0)) node _issue_entry_T_5675 = or(_issue_entry_T_5671, _issue_entry_T_5672) node _issue_entry_T_5676 = or(_issue_entry_T_5675, _issue_entry_T_5673) node _issue_entry_T_5677 = or(_issue_entry_T_5676, _issue_entry_T_5674) wire _issue_entry_WIRE_311 : UInt<1> connect _issue_entry_WIRE_311, _issue_entry_T_5677 connect _issue_entry_WIRE_310[0], _issue_entry_WIRE_311 node _issue_entry_T_5678 = mux(issue_sel_0_2, entries_st[0].bits.deps_ld[1], UInt<1>(0h0)) node _issue_entry_T_5679 = mux(issue_sel_1_2, entries_st[1].bits.deps_ld[1], UInt<1>(0h0)) node _issue_entry_T_5680 = mux(issue_sel_2_2, entries_st[2].bits.deps_ld[1], UInt<1>(0h0)) node _issue_entry_T_5681 = mux(issue_sel_3_2, entries_st[3].bits.deps_ld[1], UInt<1>(0h0)) node _issue_entry_T_5682 = or(_issue_entry_T_5678, _issue_entry_T_5679) node _issue_entry_T_5683 = or(_issue_entry_T_5682, _issue_entry_T_5680) node _issue_entry_T_5684 = or(_issue_entry_T_5683, _issue_entry_T_5681) wire _issue_entry_WIRE_312 : UInt<1> connect _issue_entry_WIRE_312, _issue_entry_T_5684 connect _issue_entry_WIRE_310[1], _issue_entry_WIRE_312 node _issue_entry_T_5685 = mux(issue_sel_0_2, entries_st[0].bits.deps_ld[2], UInt<1>(0h0)) node _issue_entry_T_5686 = mux(issue_sel_1_2, entries_st[1].bits.deps_ld[2], UInt<1>(0h0)) node _issue_entry_T_5687 = mux(issue_sel_2_2, entries_st[2].bits.deps_ld[2], UInt<1>(0h0)) node _issue_entry_T_5688 = mux(issue_sel_3_2, entries_st[3].bits.deps_ld[2], UInt<1>(0h0)) node _issue_entry_T_5689 = or(_issue_entry_T_5685, _issue_entry_T_5686) node _issue_entry_T_5690 = or(_issue_entry_T_5689, _issue_entry_T_5687) node _issue_entry_T_5691 = or(_issue_entry_T_5690, _issue_entry_T_5688) wire _issue_entry_WIRE_313 : UInt<1> connect _issue_entry_WIRE_313, _issue_entry_T_5691 connect _issue_entry_WIRE_310[2], _issue_entry_WIRE_313 node _issue_entry_T_5692 = mux(issue_sel_0_2, entries_st[0].bits.deps_ld[3], UInt<1>(0h0)) node _issue_entry_T_5693 = mux(issue_sel_1_2, entries_st[1].bits.deps_ld[3], UInt<1>(0h0)) node _issue_entry_T_5694 = mux(issue_sel_2_2, entries_st[2].bits.deps_ld[3], UInt<1>(0h0)) node _issue_entry_T_5695 = mux(issue_sel_3_2, entries_st[3].bits.deps_ld[3], UInt<1>(0h0)) node _issue_entry_T_5696 = or(_issue_entry_T_5692, _issue_entry_T_5693) node _issue_entry_T_5697 = or(_issue_entry_T_5696, _issue_entry_T_5694) node _issue_entry_T_5698 = or(_issue_entry_T_5697, _issue_entry_T_5695) wire _issue_entry_WIRE_314 : UInt<1> connect _issue_entry_WIRE_314, _issue_entry_T_5698 connect _issue_entry_WIRE_310[3], _issue_entry_WIRE_314 node _issue_entry_T_5699 = mux(issue_sel_0_2, entries_st[0].bits.deps_ld[4], UInt<1>(0h0)) node _issue_entry_T_5700 = mux(issue_sel_1_2, entries_st[1].bits.deps_ld[4], UInt<1>(0h0)) node _issue_entry_T_5701 = mux(issue_sel_2_2, entries_st[2].bits.deps_ld[4], UInt<1>(0h0)) node _issue_entry_T_5702 = mux(issue_sel_3_2, entries_st[3].bits.deps_ld[4], UInt<1>(0h0)) node _issue_entry_T_5703 = or(_issue_entry_T_5699, _issue_entry_T_5700) node _issue_entry_T_5704 = or(_issue_entry_T_5703, _issue_entry_T_5701) node _issue_entry_T_5705 = or(_issue_entry_T_5704, _issue_entry_T_5702) wire _issue_entry_WIRE_315 : UInt<1> connect _issue_entry_WIRE_315, _issue_entry_T_5705 connect _issue_entry_WIRE_310[4], _issue_entry_WIRE_315 node _issue_entry_T_5706 = mux(issue_sel_0_2, entries_st[0].bits.deps_ld[5], UInt<1>(0h0)) node _issue_entry_T_5707 = mux(issue_sel_1_2, entries_st[1].bits.deps_ld[5], UInt<1>(0h0)) node _issue_entry_T_5708 = mux(issue_sel_2_2, entries_st[2].bits.deps_ld[5], UInt<1>(0h0)) node _issue_entry_T_5709 = mux(issue_sel_3_2, entries_st[3].bits.deps_ld[5], UInt<1>(0h0)) node _issue_entry_T_5710 = or(_issue_entry_T_5706, _issue_entry_T_5707) node _issue_entry_T_5711 = or(_issue_entry_T_5710, _issue_entry_T_5708) node _issue_entry_T_5712 = or(_issue_entry_T_5711, _issue_entry_T_5709) wire _issue_entry_WIRE_316 : UInt<1> connect _issue_entry_WIRE_316, _issue_entry_T_5712 connect _issue_entry_WIRE_310[5], _issue_entry_WIRE_316 node _issue_entry_T_5713 = mux(issue_sel_0_2, entries_st[0].bits.deps_ld[6], UInt<1>(0h0)) node _issue_entry_T_5714 = mux(issue_sel_1_2, entries_st[1].bits.deps_ld[6], UInt<1>(0h0)) node _issue_entry_T_5715 = mux(issue_sel_2_2, entries_st[2].bits.deps_ld[6], UInt<1>(0h0)) node _issue_entry_T_5716 = mux(issue_sel_3_2, entries_st[3].bits.deps_ld[6], UInt<1>(0h0)) node _issue_entry_T_5717 = or(_issue_entry_T_5713, _issue_entry_T_5714) node _issue_entry_T_5718 = or(_issue_entry_T_5717, _issue_entry_T_5715) node _issue_entry_T_5719 = or(_issue_entry_T_5718, _issue_entry_T_5716) wire _issue_entry_WIRE_317 : UInt<1> connect _issue_entry_WIRE_317, _issue_entry_T_5719 connect _issue_entry_WIRE_310[6], _issue_entry_WIRE_317 node _issue_entry_T_5720 = mux(issue_sel_0_2, entries_st[0].bits.deps_ld[7], UInt<1>(0h0)) node _issue_entry_T_5721 = mux(issue_sel_1_2, entries_st[1].bits.deps_ld[7], UInt<1>(0h0)) node _issue_entry_T_5722 = mux(issue_sel_2_2, entries_st[2].bits.deps_ld[7], UInt<1>(0h0)) node _issue_entry_T_5723 = mux(issue_sel_3_2, entries_st[3].bits.deps_ld[7], UInt<1>(0h0)) node _issue_entry_T_5724 = or(_issue_entry_T_5720, _issue_entry_T_5721) node _issue_entry_T_5725 = or(_issue_entry_T_5724, _issue_entry_T_5722) node _issue_entry_T_5726 = or(_issue_entry_T_5725, _issue_entry_T_5723) wire _issue_entry_WIRE_318 : UInt<1> connect _issue_entry_WIRE_318, _issue_entry_T_5726 connect _issue_entry_WIRE_310[7], _issue_entry_WIRE_318 connect _issue_entry_WIRE_286.deps_ld, _issue_entry_WIRE_310 wire _issue_entry_WIRE_319 : { cmd : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, rob_id : { valid : UInt<1>, bits : UInt<6>}, from_matmul_fsm : UInt<1>, from_conv_fsm : UInt<1>} node _issue_entry_T_5727 = mux(issue_sel_0_2, entries_st[0].bits.cmd.from_conv_fsm, UInt<1>(0h0)) node _issue_entry_T_5728 = mux(issue_sel_1_2, entries_st[1].bits.cmd.from_conv_fsm, UInt<1>(0h0)) node _issue_entry_T_5729 = mux(issue_sel_2_2, entries_st[2].bits.cmd.from_conv_fsm, UInt<1>(0h0)) node _issue_entry_T_5730 = mux(issue_sel_3_2, entries_st[3].bits.cmd.from_conv_fsm, UInt<1>(0h0)) node _issue_entry_T_5731 = or(_issue_entry_T_5727, _issue_entry_T_5728) node _issue_entry_T_5732 = or(_issue_entry_T_5731, _issue_entry_T_5729) node _issue_entry_T_5733 = or(_issue_entry_T_5732, _issue_entry_T_5730) wire _issue_entry_WIRE_320 : UInt<1> connect _issue_entry_WIRE_320, _issue_entry_T_5733 connect _issue_entry_WIRE_319.from_conv_fsm, _issue_entry_WIRE_320 node _issue_entry_T_5734 = mux(issue_sel_0_2, entries_st[0].bits.cmd.from_matmul_fsm, UInt<1>(0h0)) node _issue_entry_T_5735 = mux(issue_sel_1_2, entries_st[1].bits.cmd.from_matmul_fsm, UInt<1>(0h0)) node _issue_entry_T_5736 = mux(issue_sel_2_2, entries_st[2].bits.cmd.from_matmul_fsm, UInt<1>(0h0)) node _issue_entry_T_5737 = mux(issue_sel_3_2, entries_st[3].bits.cmd.from_matmul_fsm, UInt<1>(0h0)) node _issue_entry_T_5738 = or(_issue_entry_T_5734, _issue_entry_T_5735) node _issue_entry_T_5739 = or(_issue_entry_T_5738, _issue_entry_T_5736) node _issue_entry_T_5740 = or(_issue_entry_T_5739, _issue_entry_T_5737) wire _issue_entry_WIRE_321 : UInt<1> connect _issue_entry_WIRE_321, _issue_entry_T_5740 connect _issue_entry_WIRE_319.from_matmul_fsm, _issue_entry_WIRE_321 wire _issue_entry_WIRE_322 : { valid : UInt<1>, bits : UInt<6>} node _issue_entry_T_5741 = mux(issue_sel_0_2, entries_st[0].bits.cmd.rob_id.bits, UInt<1>(0h0)) node _issue_entry_T_5742 = mux(issue_sel_1_2, entries_st[1].bits.cmd.rob_id.bits, UInt<1>(0h0)) node _issue_entry_T_5743 = mux(issue_sel_2_2, entries_st[2].bits.cmd.rob_id.bits, UInt<1>(0h0)) node _issue_entry_T_5744 = mux(issue_sel_3_2, entries_st[3].bits.cmd.rob_id.bits, UInt<1>(0h0)) node _issue_entry_T_5745 = or(_issue_entry_T_5741, _issue_entry_T_5742) node _issue_entry_T_5746 = or(_issue_entry_T_5745, _issue_entry_T_5743) node _issue_entry_T_5747 = or(_issue_entry_T_5746, _issue_entry_T_5744) wire _issue_entry_WIRE_323 : UInt<6> connect _issue_entry_WIRE_323, _issue_entry_T_5747 connect _issue_entry_WIRE_322.bits, _issue_entry_WIRE_323 node _issue_entry_T_5748 = mux(issue_sel_0_2, entries_st[0].bits.cmd.rob_id.valid, UInt<1>(0h0)) node _issue_entry_T_5749 = mux(issue_sel_1_2, entries_st[1].bits.cmd.rob_id.valid, UInt<1>(0h0)) node _issue_entry_T_5750 = mux(issue_sel_2_2, entries_st[2].bits.cmd.rob_id.valid, UInt<1>(0h0)) node _issue_entry_T_5751 = mux(issue_sel_3_2, entries_st[3].bits.cmd.rob_id.valid, UInt<1>(0h0)) node _issue_entry_T_5752 = or(_issue_entry_T_5748, _issue_entry_T_5749) node _issue_entry_T_5753 = or(_issue_entry_T_5752, _issue_entry_T_5750) node _issue_entry_T_5754 = or(_issue_entry_T_5753, _issue_entry_T_5751) wire _issue_entry_WIRE_324 : UInt<1> connect _issue_entry_WIRE_324, _issue_entry_T_5754 connect _issue_entry_WIRE_322.valid, _issue_entry_WIRE_324 connect _issue_entry_WIRE_319.rob_id, _issue_entry_WIRE_322 wire _issue_entry_WIRE_325 : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}} wire _issue_entry_WIRE_326 : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} node _issue_entry_T_5755 = mux(issue_sel_0_2, entries_st[0].bits.cmd.cmd.status.uie, UInt<1>(0h0)) node _issue_entry_T_5756 = mux(issue_sel_1_2, entries_st[1].bits.cmd.cmd.status.uie, UInt<1>(0h0)) node _issue_entry_T_5757 = mux(issue_sel_2_2, entries_st[2].bits.cmd.cmd.status.uie, UInt<1>(0h0)) node _issue_entry_T_5758 = mux(issue_sel_3_2, entries_st[3].bits.cmd.cmd.status.uie, UInt<1>(0h0)) node _issue_entry_T_5759 = or(_issue_entry_T_5755, _issue_entry_T_5756) node _issue_entry_T_5760 = or(_issue_entry_T_5759, _issue_entry_T_5757) node _issue_entry_T_5761 = or(_issue_entry_T_5760, _issue_entry_T_5758) wire _issue_entry_WIRE_327 : UInt<1> connect _issue_entry_WIRE_327, _issue_entry_T_5761 connect _issue_entry_WIRE_326.uie, _issue_entry_WIRE_327 node _issue_entry_T_5762 = mux(issue_sel_0_2, entries_st[0].bits.cmd.cmd.status.sie, UInt<1>(0h0)) node _issue_entry_T_5763 = mux(issue_sel_1_2, entries_st[1].bits.cmd.cmd.status.sie, UInt<1>(0h0)) node _issue_entry_T_5764 = mux(issue_sel_2_2, entries_st[2].bits.cmd.cmd.status.sie, UInt<1>(0h0)) node _issue_entry_T_5765 = mux(issue_sel_3_2, entries_st[3].bits.cmd.cmd.status.sie, UInt<1>(0h0)) node _issue_entry_T_5766 = or(_issue_entry_T_5762, _issue_entry_T_5763) node _issue_entry_T_5767 = or(_issue_entry_T_5766, _issue_entry_T_5764) node _issue_entry_T_5768 = or(_issue_entry_T_5767, _issue_entry_T_5765) wire _issue_entry_WIRE_328 : UInt<1> connect _issue_entry_WIRE_328, _issue_entry_T_5768 connect _issue_entry_WIRE_326.sie, _issue_entry_WIRE_328 node _issue_entry_T_5769 = mux(issue_sel_0_2, entries_st[0].bits.cmd.cmd.status.hie, UInt<1>(0h0)) node _issue_entry_T_5770 = mux(issue_sel_1_2, entries_st[1].bits.cmd.cmd.status.hie, UInt<1>(0h0)) node _issue_entry_T_5771 = mux(issue_sel_2_2, entries_st[2].bits.cmd.cmd.status.hie, UInt<1>(0h0)) node _issue_entry_T_5772 = mux(issue_sel_3_2, entries_st[3].bits.cmd.cmd.status.hie, UInt<1>(0h0)) node _issue_entry_T_5773 = or(_issue_entry_T_5769, _issue_entry_T_5770) node _issue_entry_T_5774 = or(_issue_entry_T_5773, _issue_entry_T_5771) node _issue_entry_T_5775 = or(_issue_entry_T_5774, _issue_entry_T_5772) wire _issue_entry_WIRE_329 : UInt<1> connect _issue_entry_WIRE_329, _issue_entry_T_5775 connect _issue_entry_WIRE_326.hie, _issue_entry_WIRE_329 node _issue_entry_T_5776 = mux(issue_sel_0_2, entries_st[0].bits.cmd.cmd.status.mie, UInt<1>(0h0)) node _issue_entry_T_5777 = mux(issue_sel_1_2, entries_st[1].bits.cmd.cmd.status.mie, UInt<1>(0h0)) node _issue_entry_T_5778 = mux(issue_sel_2_2, entries_st[2].bits.cmd.cmd.status.mie, UInt<1>(0h0)) node _issue_entry_T_5779 = mux(issue_sel_3_2, entries_st[3].bits.cmd.cmd.status.mie, UInt<1>(0h0)) node _issue_entry_T_5780 = or(_issue_entry_T_5776, _issue_entry_T_5777) node _issue_entry_T_5781 = or(_issue_entry_T_5780, _issue_entry_T_5778) node _issue_entry_T_5782 = or(_issue_entry_T_5781, _issue_entry_T_5779) wire _issue_entry_WIRE_330 : UInt<1> connect _issue_entry_WIRE_330, _issue_entry_T_5782 connect _issue_entry_WIRE_326.mie, _issue_entry_WIRE_330 node _issue_entry_T_5783 = mux(issue_sel_0_2, entries_st[0].bits.cmd.cmd.status.upie, UInt<1>(0h0)) node _issue_entry_T_5784 = mux(issue_sel_1_2, entries_st[1].bits.cmd.cmd.status.upie, UInt<1>(0h0)) node _issue_entry_T_5785 = mux(issue_sel_2_2, entries_st[2].bits.cmd.cmd.status.upie, UInt<1>(0h0)) node _issue_entry_T_5786 = mux(issue_sel_3_2, entries_st[3].bits.cmd.cmd.status.upie, UInt<1>(0h0)) node _issue_entry_T_5787 = or(_issue_entry_T_5783, _issue_entry_T_5784) node _issue_entry_T_5788 = or(_issue_entry_T_5787, _issue_entry_T_5785) node _issue_entry_T_5789 = or(_issue_entry_T_5788, _issue_entry_T_5786) wire _issue_entry_WIRE_331 : UInt<1> connect _issue_entry_WIRE_331, _issue_entry_T_5789 connect _issue_entry_WIRE_326.upie, _issue_entry_WIRE_331 node _issue_entry_T_5790 = mux(issue_sel_0_2, entries_st[0].bits.cmd.cmd.status.spie, UInt<1>(0h0)) node _issue_entry_T_5791 = mux(issue_sel_1_2, entries_st[1].bits.cmd.cmd.status.spie, UInt<1>(0h0)) node _issue_entry_T_5792 = mux(issue_sel_2_2, entries_st[2].bits.cmd.cmd.status.spie, UInt<1>(0h0)) node _issue_entry_T_5793 = mux(issue_sel_3_2, entries_st[3].bits.cmd.cmd.status.spie, UInt<1>(0h0)) node _issue_entry_T_5794 = or(_issue_entry_T_5790, _issue_entry_T_5791) node _issue_entry_T_5795 = or(_issue_entry_T_5794, _issue_entry_T_5792) node _issue_entry_T_5796 = or(_issue_entry_T_5795, _issue_entry_T_5793) wire _issue_entry_WIRE_332 : UInt<1> connect _issue_entry_WIRE_332, _issue_entry_T_5796 connect _issue_entry_WIRE_326.spie, _issue_entry_WIRE_332 node _issue_entry_T_5797 = mux(issue_sel_0_2, entries_st[0].bits.cmd.cmd.status.ube, UInt<1>(0h0)) node _issue_entry_T_5798 = mux(issue_sel_1_2, entries_st[1].bits.cmd.cmd.status.ube, UInt<1>(0h0)) node _issue_entry_T_5799 = mux(issue_sel_2_2, entries_st[2].bits.cmd.cmd.status.ube, UInt<1>(0h0)) node _issue_entry_T_5800 = mux(issue_sel_3_2, entries_st[3].bits.cmd.cmd.status.ube, UInt<1>(0h0)) node _issue_entry_T_5801 = or(_issue_entry_T_5797, _issue_entry_T_5798) node _issue_entry_T_5802 = or(_issue_entry_T_5801, _issue_entry_T_5799) node _issue_entry_T_5803 = or(_issue_entry_T_5802, _issue_entry_T_5800) wire _issue_entry_WIRE_333 : UInt<1> connect _issue_entry_WIRE_333, _issue_entry_T_5803 connect _issue_entry_WIRE_326.ube, _issue_entry_WIRE_333 node _issue_entry_T_5804 = mux(issue_sel_0_2, entries_st[0].bits.cmd.cmd.status.mpie, UInt<1>(0h0)) node _issue_entry_T_5805 = mux(issue_sel_1_2, entries_st[1].bits.cmd.cmd.status.mpie, UInt<1>(0h0)) node _issue_entry_T_5806 = mux(issue_sel_2_2, entries_st[2].bits.cmd.cmd.status.mpie, UInt<1>(0h0)) node _issue_entry_T_5807 = mux(issue_sel_3_2, entries_st[3].bits.cmd.cmd.status.mpie, UInt<1>(0h0)) node _issue_entry_T_5808 = or(_issue_entry_T_5804, _issue_entry_T_5805) node _issue_entry_T_5809 = or(_issue_entry_T_5808, _issue_entry_T_5806) node _issue_entry_T_5810 = or(_issue_entry_T_5809, _issue_entry_T_5807) wire _issue_entry_WIRE_334 : UInt<1> connect _issue_entry_WIRE_334, _issue_entry_T_5810 connect _issue_entry_WIRE_326.mpie, _issue_entry_WIRE_334 node _issue_entry_T_5811 = mux(issue_sel_0_2, entries_st[0].bits.cmd.cmd.status.spp, UInt<1>(0h0)) node _issue_entry_T_5812 = mux(issue_sel_1_2, entries_st[1].bits.cmd.cmd.status.spp, UInt<1>(0h0)) node _issue_entry_T_5813 = mux(issue_sel_2_2, entries_st[2].bits.cmd.cmd.status.spp, UInt<1>(0h0)) node _issue_entry_T_5814 = mux(issue_sel_3_2, entries_st[3].bits.cmd.cmd.status.spp, UInt<1>(0h0)) node _issue_entry_T_5815 = or(_issue_entry_T_5811, _issue_entry_T_5812) node _issue_entry_T_5816 = or(_issue_entry_T_5815, _issue_entry_T_5813) node _issue_entry_T_5817 = or(_issue_entry_T_5816, _issue_entry_T_5814) wire _issue_entry_WIRE_335 : UInt<1> connect _issue_entry_WIRE_335, _issue_entry_T_5817 connect _issue_entry_WIRE_326.spp, _issue_entry_WIRE_335 node _issue_entry_T_5818 = mux(issue_sel_0_2, entries_st[0].bits.cmd.cmd.status.vs, UInt<1>(0h0)) node _issue_entry_T_5819 = mux(issue_sel_1_2, entries_st[1].bits.cmd.cmd.status.vs, UInt<1>(0h0)) node _issue_entry_T_5820 = mux(issue_sel_2_2, entries_st[2].bits.cmd.cmd.status.vs, UInt<1>(0h0)) node _issue_entry_T_5821 = mux(issue_sel_3_2, entries_st[3].bits.cmd.cmd.status.vs, UInt<1>(0h0)) node _issue_entry_T_5822 = or(_issue_entry_T_5818, _issue_entry_T_5819) node _issue_entry_T_5823 = or(_issue_entry_T_5822, _issue_entry_T_5820) node _issue_entry_T_5824 = or(_issue_entry_T_5823, _issue_entry_T_5821) wire _issue_entry_WIRE_336 : UInt<2> connect _issue_entry_WIRE_336, _issue_entry_T_5824 connect _issue_entry_WIRE_326.vs, _issue_entry_WIRE_336 node _issue_entry_T_5825 = mux(issue_sel_0_2, entries_st[0].bits.cmd.cmd.status.mpp, UInt<1>(0h0)) node _issue_entry_T_5826 = mux(issue_sel_1_2, entries_st[1].bits.cmd.cmd.status.mpp, UInt<1>(0h0)) node _issue_entry_T_5827 = mux(issue_sel_2_2, entries_st[2].bits.cmd.cmd.status.mpp, UInt<1>(0h0)) node _issue_entry_T_5828 = mux(issue_sel_3_2, entries_st[3].bits.cmd.cmd.status.mpp, UInt<1>(0h0)) node _issue_entry_T_5829 = or(_issue_entry_T_5825, _issue_entry_T_5826) node _issue_entry_T_5830 = or(_issue_entry_T_5829, _issue_entry_T_5827) node _issue_entry_T_5831 = or(_issue_entry_T_5830, _issue_entry_T_5828) wire _issue_entry_WIRE_337 : UInt<2> connect _issue_entry_WIRE_337, _issue_entry_T_5831 connect _issue_entry_WIRE_326.mpp, _issue_entry_WIRE_337 node _issue_entry_T_5832 = mux(issue_sel_0_2, entries_st[0].bits.cmd.cmd.status.fs, UInt<1>(0h0)) node _issue_entry_T_5833 = mux(issue_sel_1_2, entries_st[1].bits.cmd.cmd.status.fs, UInt<1>(0h0)) node _issue_entry_T_5834 = mux(issue_sel_2_2, entries_st[2].bits.cmd.cmd.status.fs, UInt<1>(0h0)) node _issue_entry_T_5835 = mux(issue_sel_3_2, entries_st[3].bits.cmd.cmd.status.fs, UInt<1>(0h0)) node _issue_entry_T_5836 = or(_issue_entry_T_5832, _issue_entry_T_5833) node _issue_entry_T_5837 = or(_issue_entry_T_5836, _issue_entry_T_5834) node _issue_entry_T_5838 = or(_issue_entry_T_5837, _issue_entry_T_5835) wire _issue_entry_WIRE_338 : UInt<2> connect _issue_entry_WIRE_338, _issue_entry_T_5838 connect _issue_entry_WIRE_326.fs, _issue_entry_WIRE_338 node _issue_entry_T_5839 = mux(issue_sel_0_2, entries_st[0].bits.cmd.cmd.status.xs, UInt<1>(0h0)) node _issue_entry_T_5840 = mux(issue_sel_1_2, entries_st[1].bits.cmd.cmd.status.xs, UInt<1>(0h0)) node _issue_entry_T_5841 = mux(issue_sel_2_2, entries_st[2].bits.cmd.cmd.status.xs, UInt<1>(0h0)) node _issue_entry_T_5842 = mux(issue_sel_3_2, entries_st[3].bits.cmd.cmd.status.xs, UInt<1>(0h0)) node _issue_entry_T_5843 = or(_issue_entry_T_5839, _issue_entry_T_5840) node _issue_entry_T_5844 = or(_issue_entry_T_5843, _issue_entry_T_5841) node _issue_entry_T_5845 = or(_issue_entry_T_5844, _issue_entry_T_5842) wire _issue_entry_WIRE_339 : UInt<2> connect _issue_entry_WIRE_339, _issue_entry_T_5845 connect _issue_entry_WIRE_326.xs, _issue_entry_WIRE_339 node _issue_entry_T_5846 = mux(issue_sel_0_2, entries_st[0].bits.cmd.cmd.status.mprv, UInt<1>(0h0)) node _issue_entry_T_5847 = mux(issue_sel_1_2, entries_st[1].bits.cmd.cmd.status.mprv, UInt<1>(0h0)) node _issue_entry_T_5848 = mux(issue_sel_2_2, entries_st[2].bits.cmd.cmd.status.mprv, UInt<1>(0h0)) node _issue_entry_T_5849 = mux(issue_sel_3_2, entries_st[3].bits.cmd.cmd.status.mprv, UInt<1>(0h0)) node _issue_entry_T_5850 = or(_issue_entry_T_5846, _issue_entry_T_5847) node _issue_entry_T_5851 = or(_issue_entry_T_5850, _issue_entry_T_5848) node _issue_entry_T_5852 = or(_issue_entry_T_5851, _issue_entry_T_5849) wire _issue_entry_WIRE_340 : UInt<1> connect _issue_entry_WIRE_340, _issue_entry_T_5852 connect _issue_entry_WIRE_326.mprv, _issue_entry_WIRE_340 node _issue_entry_T_5853 = mux(issue_sel_0_2, entries_st[0].bits.cmd.cmd.status.sum, UInt<1>(0h0)) node _issue_entry_T_5854 = mux(issue_sel_1_2, entries_st[1].bits.cmd.cmd.status.sum, UInt<1>(0h0)) node _issue_entry_T_5855 = mux(issue_sel_2_2, entries_st[2].bits.cmd.cmd.status.sum, UInt<1>(0h0)) node _issue_entry_T_5856 = mux(issue_sel_3_2, entries_st[3].bits.cmd.cmd.status.sum, UInt<1>(0h0)) node _issue_entry_T_5857 = or(_issue_entry_T_5853, _issue_entry_T_5854) node _issue_entry_T_5858 = or(_issue_entry_T_5857, _issue_entry_T_5855) node _issue_entry_T_5859 = or(_issue_entry_T_5858, _issue_entry_T_5856) wire _issue_entry_WIRE_341 : UInt<1> connect _issue_entry_WIRE_341, _issue_entry_T_5859 connect _issue_entry_WIRE_326.sum, _issue_entry_WIRE_341 node _issue_entry_T_5860 = mux(issue_sel_0_2, entries_st[0].bits.cmd.cmd.status.mxr, UInt<1>(0h0)) node _issue_entry_T_5861 = mux(issue_sel_1_2, entries_st[1].bits.cmd.cmd.status.mxr, UInt<1>(0h0)) node _issue_entry_T_5862 = mux(issue_sel_2_2, entries_st[2].bits.cmd.cmd.status.mxr, UInt<1>(0h0)) node _issue_entry_T_5863 = mux(issue_sel_3_2, entries_st[3].bits.cmd.cmd.status.mxr, UInt<1>(0h0)) node _issue_entry_T_5864 = or(_issue_entry_T_5860, _issue_entry_T_5861) node _issue_entry_T_5865 = or(_issue_entry_T_5864, _issue_entry_T_5862) node _issue_entry_T_5866 = or(_issue_entry_T_5865, _issue_entry_T_5863) wire _issue_entry_WIRE_342 : UInt<1> connect _issue_entry_WIRE_342, _issue_entry_T_5866 connect _issue_entry_WIRE_326.mxr, _issue_entry_WIRE_342 node _issue_entry_T_5867 = mux(issue_sel_0_2, entries_st[0].bits.cmd.cmd.status.tvm, UInt<1>(0h0)) node _issue_entry_T_5868 = mux(issue_sel_1_2, entries_st[1].bits.cmd.cmd.status.tvm, UInt<1>(0h0)) node _issue_entry_T_5869 = mux(issue_sel_2_2, entries_st[2].bits.cmd.cmd.status.tvm, UInt<1>(0h0)) node _issue_entry_T_5870 = mux(issue_sel_3_2, entries_st[3].bits.cmd.cmd.status.tvm, UInt<1>(0h0)) node _issue_entry_T_5871 = or(_issue_entry_T_5867, _issue_entry_T_5868) node _issue_entry_T_5872 = or(_issue_entry_T_5871, _issue_entry_T_5869) node _issue_entry_T_5873 = or(_issue_entry_T_5872, _issue_entry_T_5870) wire _issue_entry_WIRE_343 : UInt<1> connect _issue_entry_WIRE_343, _issue_entry_T_5873 connect _issue_entry_WIRE_326.tvm, _issue_entry_WIRE_343 node _issue_entry_T_5874 = mux(issue_sel_0_2, entries_st[0].bits.cmd.cmd.status.tw, UInt<1>(0h0)) node _issue_entry_T_5875 = mux(issue_sel_1_2, entries_st[1].bits.cmd.cmd.status.tw, UInt<1>(0h0)) node _issue_entry_T_5876 = mux(issue_sel_2_2, entries_st[2].bits.cmd.cmd.status.tw, UInt<1>(0h0)) node _issue_entry_T_5877 = mux(issue_sel_3_2, entries_st[3].bits.cmd.cmd.status.tw, UInt<1>(0h0)) node _issue_entry_T_5878 = or(_issue_entry_T_5874, _issue_entry_T_5875) node _issue_entry_T_5879 = or(_issue_entry_T_5878, _issue_entry_T_5876) node _issue_entry_T_5880 = or(_issue_entry_T_5879, _issue_entry_T_5877) wire _issue_entry_WIRE_344 : UInt<1> connect _issue_entry_WIRE_344, _issue_entry_T_5880 connect _issue_entry_WIRE_326.tw, _issue_entry_WIRE_344 node _issue_entry_T_5881 = mux(issue_sel_0_2, entries_st[0].bits.cmd.cmd.status.tsr, UInt<1>(0h0)) node _issue_entry_T_5882 = mux(issue_sel_1_2, entries_st[1].bits.cmd.cmd.status.tsr, UInt<1>(0h0)) node _issue_entry_T_5883 = mux(issue_sel_2_2, entries_st[2].bits.cmd.cmd.status.tsr, UInt<1>(0h0)) node _issue_entry_T_5884 = mux(issue_sel_3_2, entries_st[3].bits.cmd.cmd.status.tsr, UInt<1>(0h0)) node _issue_entry_T_5885 = or(_issue_entry_T_5881, _issue_entry_T_5882) node _issue_entry_T_5886 = or(_issue_entry_T_5885, _issue_entry_T_5883) node _issue_entry_T_5887 = or(_issue_entry_T_5886, _issue_entry_T_5884) wire _issue_entry_WIRE_345 : UInt<1> connect _issue_entry_WIRE_345, _issue_entry_T_5887 connect _issue_entry_WIRE_326.tsr, _issue_entry_WIRE_345 node _issue_entry_T_5888 = mux(issue_sel_0_2, entries_st[0].bits.cmd.cmd.status.zero1, UInt<1>(0h0)) node _issue_entry_T_5889 = mux(issue_sel_1_2, entries_st[1].bits.cmd.cmd.status.zero1, UInt<1>(0h0)) node _issue_entry_T_5890 = mux(issue_sel_2_2, entries_st[2].bits.cmd.cmd.status.zero1, UInt<1>(0h0)) node _issue_entry_T_5891 = mux(issue_sel_3_2, entries_st[3].bits.cmd.cmd.status.zero1, UInt<1>(0h0)) node _issue_entry_T_5892 = or(_issue_entry_T_5888, _issue_entry_T_5889) node _issue_entry_T_5893 = or(_issue_entry_T_5892, _issue_entry_T_5890) node _issue_entry_T_5894 = or(_issue_entry_T_5893, _issue_entry_T_5891) wire _issue_entry_WIRE_346 : UInt<8> connect _issue_entry_WIRE_346, _issue_entry_T_5894 connect _issue_entry_WIRE_326.zero1, _issue_entry_WIRE_346 node _issue_entry_T_5895 = mux(issue_sel_0_2, entries_st[0].bits.cmd.cmd.status.sd_rv32, UInt<1>(0h0)) node _issue_entry_T_5896 = mux(issue_sel_1_2, entries_st[1].bits.cmd.cmd.status.sd_rv32, UInt<1>(0h0)) node _issue_entry_T_5897 = mux(issue_sel_2_2, entries_st[2].bits.cmd.cmd.status.sd_rv32, UInt<1>(0h0)) node _issue_entry_T_5898 = mux(issue_sel_3_2, entries_st[3].bits.cmd.cmd.status.sd_rv32, UInt<1>(0h0)) node _issue_entry_T_5899 = or(_issue_entry_T_5895, _issue_entry_T_5896) node _issue_entry_T_5900 = or(_issue_entry_T_5899, _issue_entry_T_5897) node _issue_entry_T_5901 = or(_issue_entry_T_5900, _issue_entry_T_5898) wire _issue_entry_WIRE_347 : UInt<1> connect _issue_entry_WIRE_347, _issue_entry_T_5901 connect _issue_entry_WIRE_326.sd_rv32, _issue_entry_WIRE_347 node _issue_entry_T_5902 = mux(issue_sel_0_2, entries_st[0].bits.cmd.cmd.status.uxl, UInt<1>(0h0)) node _issue_entry_T_5903 = mux(issue_sel_1_2, entries_st[1].bits.cmd.cmd.status.uxl, UInt<1>(0h0)) node _issue_entry_T_5904 = mux(issue_sel_2_2, entries_st[2].bits.cmd.cmd.status.uxl, UInt<1>(0h0)) node _issue_entry_T_5905 = mux(issue_sel_3_2, entries_st[3].bits.cmd.cmd.status.uxl, UInt<1>(0h0)) node _issue_entry_T_5906 = or(_issue_entry_T_5902, _issue_entry_T_5903) node _issue_entry_T_5907 = or(_issue_entry_T_5906, _issue_entry_T_5904) node _issue_entry_T_5908 = or(_issue_entry_T_5907, _issue_entry_T_5905) wire _issue_entry_WIRE_348 : UInt<2> connect _issue_entry_WIRE_348, _issue_entry_T_5908 connect _issue_entry_WIRE_326.uxl, _issue_entry_WIRE_348 node _issue_entry_T_5909 = mux(issue_sel_0_2, entries_st[0].bits.cmd.cmd.status.sxl, UInt<1>(0h0)) node _issue_entry_T_5910 = mux(issue_sel_1_2, entries_st[1].bits.cmd.cmd.status.sxl, UInt<1>(0h0)) node _issue_entry_T_5911 = mux(issue_sel_2_2, entries_st[2].bits.cmd.cmd.status.sxl, UInt<1>(0h0)) node _issue_entry_T_5912 = mux(issue_sel_3_2, entries_st[3].bits.cmd.cmd.status.sxl, UInt<1>(0h0)) node _issue_entry_T_5913 = or(_issue_entry_T_5909, _issue_entry_T_5910) node _issue_entry_T_5914 = or(_issue_entry_T_5913, _issue_entry_T_5911) node _issue_entry_T_5915 = or(_issue_entry_T_5914, _issue_entry_T_5912) wire _issue_entry_WIRE_349 : UInt<2> connect _issue_entry_WIRE_349, _issue_entry_T_5915 connect _issue_entry_WIRE_326.sxl, _issue_entry_WIRE_349 node _issue_entry_T_5916 = mux(issue_sel_0_2, entries_st[0].bits.cmd.cmd.status.sbe, UInt<1>(0h0)) node _issue_entry_T_5917 = mux(issue_sel_1_2, entries_st[1].bits.cmd.cmd.status.sbe, UInt<1>(0h0)) node _issue_entry_T_5918 = mux(issue_sel_2_2, entries_st[2].bits.cmd.cmd.status.sbe, UInt<1>(0h0)) node _issue_entry_T_5919 = mux(issue_sel_3_2, entries_st[3].bits.cmd.cmd.status.sbe, UInt<1>(0h0)) node _issue_entry_T_5920 = or(_issue_entry_T_5916, _issue_entry_T_5917) node _issue_entry_T_5921 = or(_issue_entry_T_5920, _issue_entry_T_5918) node _issue_entry_T_5922 = or(_issue_entry_T_5921, _issue_entry_T_5919) wire _issue_entry_WIRE_350 : UInt<1> connect _issue_entry_WIRE_350, _issue_entry_T_5922 connect _issue_entry_WIRE_326.sbe, _issue_entry_WIRE_350 node _issue_entry_T_5923 = mux(issue_sel_0_2, entries_st[0].bits.cmd.cmd.status.mbe, UInt<1>(0h0)) node _issue_entry_T_5924 = mux(issue_sel_1_2, entries_st[1].bits.cmd.cmd.status.mbe, UInt<1>(0h0)) node _issue_entry_T_5925 = mux(issue_sel_2_2, entries_st[2].bits.cmd.cmd.status.mbe, UInt<1>(0h0)) node _issue_entry_T_5926 = mux(issue_sel_3_2, entries_st[3].bits.cmd.cmd.status.mbe, UInt<1>(0h0)) node _issue_entry_T_5927 = or(_issue_entry_T_5923, _issue_entry_T_5924) node _issue_entry_T_5928 = or(_issue_entry_T_5927, _issue_entry_T_5925) node _issue_entry_T_5929 = or(_issue_entry_T_5928, _issue_entry_T_5926) wire _issue_entry_WIRE_351 : UInt<1> connect _issue_entry_WIRE_351, _issue_entry_T_5929 connect _issue_entry_WIRE_326.mbe, _issue_entry_WIRE_351 node _issue_entry_T_5930 = mux(issue_sel_0_2, entries_st[0].bits.cmd.cmd.status.gva, UInt<1>(0h0)) node _issue_entry_T_5931 = mux(issue_sel_1_2, entries_st[1].bits.cmd.cmd.status.gva, UInt<1>(0h0)) node _issue_entry_T_5932 = mux(issue_sel_2_2, entries_st[2].bits.cmd.cmd.status.gva, UInt<1>(0h0)) node _issue_entry_T_5933 = mux(issue_sel_3_2, entries_st[3].bits.cmd.cmd.status.gva, UInt<1>(0h0)) node _issue_entry_T_5934 = or(_issue_entry_T_5930, _issue_entry_T_5931) node _issue_entry_T_5935 = or(_issue_entry_T_5934, _issue_entry_T_5932) node _issue_entry_T_5936 = or(_issue_entry_T_5935, _issue_entry_T_5933) wire _issue_entry_WIRE_352 : UInt<1> connect _issue_entry_WIRE_352, _issue_entry_T_5936 connect _issue_entry_WIRE_326.gva, _issue_entry_WIRE_352 node _issue_entry_T_5937 = mux(issue_sel_0_2, entries_st[0].bits.cmd.cmd.status.mpv, UInt<1>(0h0)) node _issue_entry_T_5938 = mux(issue_sel_1_2, entries_st[1].bits.cmd.cmd.status.mpv, UInt<1>(0h0)) node _issue_entry_T_5939 = mux(issue_sel_2_2, entries_st[2].bits.cmd.cmd.status.mpv, UInt<1>(0h0)) node _issue_entry_T_5940 = mux(issue_sel_3_2, entries_st[3].bits.cmd.cmd.status.mpv, UInt<1>(0h0)) node _issue_entry_T_5941 = or(_issue_entry_T_5937, _issue_entry_T_5938) node _issue_entry_T_5942 = or(_issue_entry_T_5941, _issue_entry_T_5939) node _issue_entry_T_5943 = or(_issue_entry_T_5942, _issue_entry_T_5940) wire _issue_entry_WIRE_353 : UInt<1> connect _issue_entry_WIRE_353, _issue_entry_T_5943 connect _issue_entry_WIRE_326.mpv, _issue_entry_WIRE_353 node _issue_entry_T_5944 = mux(issue_sel_0_2, entries_st[0].bits.cmd.cmd.status.zero2, UInt<1>(0h0)) node _issue_entry_T_5945 = mux(issue_sel_1_2, entries_st[1].bits.cmd.cmd.status.zero2, UInt<1>(0h0)) node _issue_entry_T_5946 = mux(issue_sel_2_2, entries_st[2].bits.cmd.cmd.status.zero2, UInt<1>(0h0)) node _issue_entry_T_5947 = mux(issue_sel_3_2, entries_st[3].bits.cmd.cmd.status.zero2, UInt<1>(0h0)) node _issue_entry_T_5948 = or(_issue_entry_T_5944, _issue_entry_T_5945) node _issue_entry_T_5949 = or(_issue_entry_T_5948, _issue_entry_T_5946) node _issue_entry_T_5950 = or(_issue_entry_T_5949, _issue_entry_T_5947) wire _issue_entry_WIRE_354 : UInt<23> connect _issue_entry_WIRE_354, _issue_entry_T_5950 connect _issue_entry_WIRE_326.zero2, _issue_entry_WIRE_354 node _issue_entry_T_5951 = mux(issue_sel_0_2, entries_st[0].bits.cmd.cmd.status.sd, UInt<1>(0h0)) node _issue_entry_T_5952 = mux(issue_sel_1_2, entries_st[1].bits.cmd.cmd.status.sd, UInt<1>(0h0)) node _issue_entry_T_5953 = mux(issue_sel_2_2, entries_st[2].bits.cmd.cmd.status.sd, UInt<1>(0h0)) node _issue_entry_T_5954 = mux(issue_sel_3_2, entries_st[3].bits.cmd.cmd.status.sd, UInt<1>(0h0)) node _issue_entry_T_5955 = or(_issue_entry_T_5951, _issue_entry_T_5952) node _issue_entry_T_5956 = or(_issue_entry_T_5955, _issue_entry_T_5953) node _issue_entry_T_5957 = or(_issue_entry_T_5956, _issue_entry_T_5954) wire _issue_entry_WIRE_355 : UInt<1> connect _issue_entry_WIRE_355, _issue_entry_T_5957 connect _issue_entry_WIRE_326.sd, _issue_entry_WIRE_355 node _issue_entry_T_5958 = mux(issue_sel_0_2, entries_st[0].bits.cmd.cmd.status.v, UInt<1>(0h0)) node _issue_entry_T_5959 = mux(issue_sel_1_2, entries_st[1].bits.cmd.cmd.status.v, UInt<1>(0h0)) node _issue_entry_T_5960 = mux(issue_sel_2_2, entries_st[2].bits.cmd.cmd.status.v, UInt<1>(0h0)) node _issue_entry_T_5961 = mux(issue_sel_3_2, entries_st[3].bits.cmd.cmd.status.v, UInt<1>(0h0)) node _issue_entry_T_5962 = or(_issue_entry_T_5958, _issue_entry_T_5959) node _issue_entry_T_5963 = or(_issue_entry_T_5962, _issue_entry_T_5960) node _issue_entry_T_5964 = or(_issue_entry_T_5963, _issue_entry_T_5961) wire _issue_entry_WIRE_356 : UInt<1> connect _issue_entry_WIRE_356, _issue_entry_T_5964 connect _issue_entry_WIRE_326.v, _issue_entry_WIRE_356 node _issue_entry_T_5965 = mux(issue_sel_0_2, entries_st[0].bits.cmd.cmd.status.prv, UInt<1>(0h0)) node _issue_entry_T_5966 = mux(issue_sel_1_2, entries_st[1].bits.cmd.cmd.status.prv, UInt<1>(0h0)) node _issue_entry_T_5967 = mux(issue_sel_2_2, entries_st[2].bits.cmd.cmd.status.prv, UInt<1>(0h0)) node _issue_entry_T_5968 = mux(issue_sel_3_2, entries_st[3].bits.cmd.cmd.status.prv, UInt<1>(0h0)) node _issue_entry_T_5969 = or(_issue_entry_T_5965, _issue_entry_T_5966) node _issue_entry_T_5970 = or(_issue_entry_T_5969, _issue_entry_T_5967) node _issue_entry_T_5971 = or(_issue_entry_T_5970, _issue_entry_T_5968) wire _issue_entry_WIRE_357 : UInt<2> connect _issue_entry_WIRE_357, _issue_entry_T_5971 connect _issue_entry_WIRE_326.prv, _issue_entry_WIRE_357 node _issue_entry_T_5972 = mux(issue_sel_0_2, entries_st[0].bits.cmd.cmd.status.dv, UInt<1>(0h0)) node _issue_entry_T_5973 = mux(issue_sel_1_2, entries_st[1].bits.cmd.cmd.status.dv, UInt<1>(0h0)) node _issue_entry_T_5974 = mux(issue_sel_2_2, entries_st[2].bits.cmd.cmd.status.dv, UInt<1>(0h0)) node _issue_entry_T_5975 = mux(issue_sel_3_2, entries_st[3].bits.cmd.cmd.status.dv, UInt<1>(0h0)) node _issue_entry_T_5976 = or(_issue_entry_T_5972, _issue_entry_T_5973) node _issue_entry_T_5977 = or(_issue_entry_T_5976, _issue_entry_T_5974) node _issue_entry_T_5978 = or(_issue_entry_T_5977, _issue_entry_T_5975) wire _issue_entry_WIRE_358 : UInt<1> connect _issue_entry_WIRE_358, _issue_entry_T_5978 connect _issue_entry_WIRE_326.dv, _issue_entry_WIRE_358 node _issue_entry_T_5979 = mux(issue_sel_0_2, entries_st[0].bits.cmd.cmd.status.dprv, UInt<1>(0h0)) node _issue_entry_T_5980 = mux(issue_sel_1_2, entries_st[1].bits.cmd.cmd.status.dprv, UInt<1>(0h0)) node _issue_entry_T_5981 = mux(issue_sel_2_2, entries_st[2].bits.cmd.cmd.status.dprv, UInt<1>(0h0)) node _issue_entry_T_5982 = mux(issue_sel_3_2, entries_st[3].bits.cmd.cmd.status.dprv, UInt<1>(0h0)) node _issue_entry_T_5983 = or(_issue_entry_T_5979, _issue_entry_T_5980) node _issue_entry_T_5984 = or(_issue_entry_T_5983, _issue_entry_T_5981) node _issue_entry_T_5985 = or(_issue_entry_T_5984, _issue_entry_T_5982) wire _issue_entry_WIRE_359 : UInt<2> connect _issue_entry_WIRE_359, _issue_entry_T_5985 connect _issue_entry_WIRE_326.dprv, _issue_entry_WIRE_359 node _issue_entry_T_5986 = mux(issue_sel_0_2, entries_st[0].bits.cmd.cmd.status.isa, UInt<1>(0h0)) node _issue_entry_T_5987 = mux(issue_sel_1_2, entries_st[1].bits.cmd.cmd.status.isa, UInt<1>(0h0)) node _issue_entry_T_5988 = mux(issue_sel_2_2, entries_st[2].bits.cmd.cmd.status.isa, UInt<1>(0h0)) node _issue_entry_T_5989 = mux(issue_sel_3_2, entries_st[3].bits.cmd.cmd.status.isa, UInt<1>(0h0)) node _issue_entry_T_5990 = or(_issue_entry_T_5986, _issue_entry_T_5987) node _issue_entry_T_5991 = or(_issue_entry_T_5990, _issue_entry_T_5988) node _issue_entry_T_5992 = or(_issue_entry_T_5991, _issue_entry_T_5989) wire _issue_entry_WIRE_360 : UInt<32> connect _issue_entry_WIRE_360, _issue_entry_T_5992 connect _issue_entry_WIRE_326.isa, _issue_entry_WIRE_360 node _issue_entry_T_5993 = mux(issue_sel_0_2, entries_st[0].bits.cmd.cmd.status.wfi, UInt<1>(0h0)) node _issue_entry_T_5994 = mux(issue_sel_1_2, entries_st[1].bits.cmd.cmd.status.wfi, UInt<1>(0h0)) node _issue_entry_T_5995 = mux(issue_sel_2_2, entries_st[2].bits.cmd.cmd.status.wfi, UInt<1>(0h0)) node _issue_entry_T_5996 = mux(issue_sel_3_2, entries_st[3].bits.cmd.cmd.status.wfi, UInt<1>(0h0)) node _issue_entry_T_5997 = or(_issue_entry_T_5993, _issue_entry_T_5994) node _issue_entry_T_5998 = or(_issue_entry_T_5997, _issue_entry_T_5995) node _issue_entry_T_5999 = or(_issue_entry_T_5998, _issue_entry_T_5996) wire _issue_entry_WIRE_361 : UInt<1> connect _issue_entry_WIRE_361, _issue_entry_T_5999 connect _issue_entry_WIRE_326.wfi, _issue_entry_WIRE_361 node _issue_entry_T_6000 = mux(issue_sel_0_2, entries_st[0].bits.cmd.cmd.status.cease, UInt<1>(0h0)) node _issue_entry_T_6001 = mux(issue_sel_1_2, entries_st[1].bits.cmd.cmd.status.cease, UInt<1>(0h0)) node _issue_entry_T_6002 = mux(issue_sel_2_2, entries_st[2].bits.cmd.cmd.status.cease, UInt<1>(0h0)) node _issue_entry_T_6003 = mux(issue_sel_3_2, entries_st[3].bits.cmd.cmd.status.cease, UInt<1>(0h0)) node _issue_entry_T_6004 = or(_issue_entry_T_6000, _issue_entry_T_6001) node _issue_entry_T_6005 = or(_issue_entry_T_6004, _issue_entry_T_6002) node _issue_entry_T_6006 = or(_issue_entry_T_6005, _issue_entry_T_6003) wire _issue_entry_WIRE_362 : UInt<1> connect _issue_entry_WIRE_362, _issue_entry_T_6006 connect _issue_entry_WIRE_326.cease, _issue_entry_WIRE_362 node _issue_entry_T_6007 = mux(issue_sel_0_2, entries_st[0].bits.cmd.cmd.status.debug, UInt<1>(0h0)) node _issue_entry_T_6008 = mux(issue_sel_1_2, entries_st[1].bits.cmd.cmd.status.debug, UInt<1>(0h0)) node _issue_entry_T_6009 = mux(issue_sel_2_2, entries_st[2].bits.cmd.cmd.status.debug, UInt<1>(0h0)) node _issue_entry_T_6010 = mux(issue_sel_3_2, entries_st[3].bits.cmd.cmd.status.debug, UInt<1>(0h0)) node _issue_entry_T_6011 = or(_issue_entry_T_6007, _issue_entry_T_6008) node _issue_entry_T_6012 = or(_issue_entry_T_6011, _issue_entry_T_6009) node _issue_entry_T_6013 = or(_issue_entry_T_6012, _issue_entry_T_6010) wire _issue_entry_WIRE_363 : UInt<1> connect _issue_entry_WIRE_363, _issue_entry_T_6013 connect _issue_entry_WIRE_326.debug, _issue_entry_WIRE_363 connect _issue_entry_WIRE_325.status, _issue_entry_WIRE_326 node _issue_entry_T_6014 = mux(issue_sel_0_2, entries_st[0].bits.cmd.cmd.rs2, UInt<1>(0h0)) node _issue_entry_T_6015 = mux(issue_sel_1_2, entries_st[1].bits.cmd.cmd.rs2, UInt<1>(0h0)) node _issue_entry_T_6016 = mux(issue_sel_2_2, entries_st[2].bits.cmd.cmd.rs2, UInt<1>(0h0)) node _issue_entry_T_6017 = mux(issue_sel_3_2, entries_st[3].bits.cmd.cmd.rs2, UInt<1>(0h0)) node _issue_entry_T_6018 = or(_issue_entry_T_6014, _issue_entry_T_6015) node _issue_entry_T_6019 = or(_issue_entry_T_6018, _issue_entry_T_6016) node _issue_entry_T_6020 = or(_issue_entry_T_6019, _issue_entry_T_6017) wire _issue_entry_WIRE_364 : UInt<64> connect _issue_entry_WIRE_364, _issue_entry_T_6020 connect _issue_entry_WIRE_325.rs2, _issue_entry_WIRE_364 node _issue_entry_T_6021 = mux(issue_sel_0_2, entries_st[0].bits.cmd.cmd.rs1, UInt<1>(0h0)) node _issue_entry_T_6022 = mux(issue_sel_1_2, entries_st[1].bits.cmd.cmd.rs1, UInt<1>(0h0)) node _issue_entry_T_6023 = mux(issue_sel_2_2, entries_st[2].bits.cmd.cmd.rs1, UInt<1>(0h0)) node _issue_entry_T_6024 = mux(issue_sel_3_2, entries_st[3].bits.cmd.cmd.rs1, UInt<1>(0h0)) node _issue_entry_T_6025 = or(_issue_entry_T_6021, _issue_entry_T_6022) node _issue_entry_T_6026 = or(_issue_entry_T_6025, _issue_entry_T_6023) node _issue_entry_T_6027 = or(_issue_entry_T_6026, _issue_entry_T_6024) wire _issue_entry_WIRE_365 : UInt<64> connect _issue_entry_WIRE_365, _issue_entry_T_6027 connect _issue_entry_WIRE_325.rs1, _issue_entry_WIRE_365 wire _issue_entry_WIRE_366 : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>} node _issue_entry_T_6028 = mux(issue_sel_0_2, entries_st[0].bits.cmd.cmd.inst.opcode, UInt<1>(0h0)) node _issue_entry_T_6029 = mux(issue_sel_1_2, entries_st[1].bits.cmd.cmd.inst.opcode, UInt<1>(0h0)) node _issue_entry_T_6030 = mux(issue_sel_2_2, entries_st[2].bits.cmd.cmd.inst.opcode, UInt<1>(0h0)) node _issue_entry_T_6031 = mux(issue_sel_3_2, entries_st[3].bits.cmd.cmd.inst.opcode, UInt<1>(0h0)) node _issue_entry_T_6032 = or(_issue_entry_T_6028, _issue_entry_T_6029) node _issue_entry_T_6033 = or(_issue_entry_T_6032, _issue_entry_T_6030) node _issue_entry_T_6034 = or(_issue_entry_T_6033, _issue_entry_T_6031) wire _issue_entry_WIRE_367 : UInt<7> connect _issue_entry_WIRE_367, _issue_entry_T_6034 connect _issue_entry_WIRE_366.opcode, _issue_entry_WIRE_367 node _issue_entry_T_6035 = mux(issue_sel_0_2, entries_st[0].bits.cmd.cmd.inst.rd, UInt<1>(0h0)) node _issue_entry_T_6036 = mux(issue_sel_1_2, entries_st[1].bits.cmd.cmd.inst.rd, UInt<1>(0h0)) node _issue_entry_T_6037 = mux(issue_sel_2_2, entries_st[2].bits.cmd.cmd.inst.rd, UInt<1>(0h0)) node _issue_entry_T_6038 = mux(issue_sel_3_2, entries_st[3].bits.cmd.cmd.inst.rd, UInt<1>(0h0)) node _issue_entry_T_6039 = or(_issue_entry_T_6035, _issue_entry_T_6036) node _issue_entry_T_6040 = or(_issue_entry_T_6039, _issue_entry_T_6037) node _issue_entry_T_6041 = or(_issue_entry_T_6040, _issue_entry_T_6038) wire _issue_entry_WIRE_368 : UInt<5> connect _issue_entry_WIRE_368, _issue_entry_T_6041 connect _issue_entry_WIRE_366.rd, _issue_entry_WIRE_368 node _issue_entry_T_6042 = mux(issue_sel_0_2, entries_st[0].bits.cmd.cmd.inst.xs2, UInt<1>(0h0)) node _issue_entry_T_6043 = mux(issue_sel_1_2, entries_st[1].bits.cmd.cmd.inst.xs2, UInt<1>(0h0)) node _issue_entry_T_6044 = mux(issue_sel_2_2, entries_st[2].bits.cmd.cmd.inst.xs2, UInt<1>(0h0)) node _issue_entry_T_6045 = mux(issue_sel_3_2, entries_st[3].bits.cmd.cmd.inst.xs2, UInt<1>(0h0)) node _issue_entry_T_6046 = or(_issue_entry_T_6042, _issue_entry_T_6043) node _issue_entry_T_6047 = or(_issue_entry_T_6046, _issue_entry_T_6044) node _issue_entry_T_6048 = or(_issue_entry_T_6047, _issue_entry_T_6045) wire _issue_entry_WIRE_369 : UInt<1> connect _issue_entry_WIRE_369, _issue_entry_T_6048 connect _issue_entry_WIRE_366.xs2, _issue_entry_WIRE_369 node _issue_entry_T_6049 = mux(issue_sel_0_2, entries_st[0].bits.cmd.cmd.inst.xs1, UInt<1>(0h0)) node _issue_entry_T_6050 = mux(issue_sel_1_2, entries_st[1].bits.cmd.cmd.inst.xs1, UInt<1>(0h0)) node _issue_entry_T_6051 = mux(issue_sel_2_2, entries_st[2].bits.cmd.cmd.inst.xs1, UInt<1>(0h0)) node _issue_entry_T_6052 = mux(issue_sel_3_2, entries_st[3].bits.cmd.cmd.inst.xs1, UInt<1>(0h0)) node _issue_entry_T_6053 = or(_issue_entry_T_6049, _issue_entry_T_6050) node _issue_entry_T_6054 = or(_issue_entry_T_6053, _issue_entry_T_6051) node _issue_entry_T_6055 = or(_issue_entry_T_6054, _issue_entry_T_6052) wire _issue_entry_WIRE_370 : UInt<1> connect _issue_entry_WIRE_370, _issue_entry_T_6055 connect _issue_entry_WIRE_366.xs1, _issue_entry_WIRE_370 node _issue_entry_T_6056 = mux(issue_sel_0_2, entries_st[0].bits.cmd.cmd.inst.xd, UInt<1>(0h0)) node _issue_entry_T_6057 = mux(issue_sel_1_2, entries_st[1].bits.cmd.cmd.inst.xd, UInt<1>(0h0)) node _issue_entry_T_6058 = mux(issue_sel_2_2, entries_st[2].bits.cmd.cmd.inst.xd, UInt<1>(0h0)) node _issue_entry_T_6059 = mux(issue_sel_3_2, entries_st[3].bits.cmd.cmd.inst.xd, UInt<1>(0h0)) node _issue_entry_T_6060 = or(_issue_entry_T_6056, _issue_entry_T_6057) node _issue_entry_T_6061 = or(_issue_entry_T_6060, _issue_entry_T_6058) node _issue_entry_T_6062 = or(_issue_entry_T_6061, _issue_entry_T_6059) wire _issue_entry_WIRE_371 : UInt<1> connect _issue_entry_WIRE_371, _issue_entry_T_6062 connect _issue_entry_WIRE_366.xd, _issue_entry_WIRE_371 node _issue_entry_T_6063 = mux(issue_sel_0_2, entries_st[0].bits.cmd.cmd.inst.rs1, UInt<1>(0h0)) node _issue_entry_T_6064 = mux(issue_sel_1_2, entries_st[1].bits.cmd.cmd.inst.rs1, UInt<1>(0h0)) node _issue_entry_T_6065 = mux(issue_sel_2_2, entries_st[2].bits.cmd.cmd.inst.rs1, UInt<1>(0h0)) node _issue_entry_T_6066 = mux(issue_sel_3_2, entries_st[3].bits.cmd.cmd.inst.rs1, UInt<1>(0h0)) node _issue_entry_T_6067 = or(_issue_entry_T_6063, _issue_entry_T_6064) node _issue_entry_T_6068 = or(_issue_entry_T_6067, _issue_entry_T_6065) node _issue_entry_T_6069 = or(_issue_entry_T_6068, _issue_entry_T_6066) wire _issue_entry_WIRE_372 : UInt<5> connect _issue_entry_WIRE_372, _issue_entry_T_6069 connect _issue_entry_WIRE_366.rs1, _issue_entry_WIRE_372 node _issue_entry_T_6070 = mux(issue_sel_0_2, entries_st[0].bits.cmd.cmd.inst.rs2, UInt<1>(0h0)) node _issue_entry_T_6071 = mux(issue_sel_1_2, entries_st[1].bits.cmd.cmd.inst.rs2, UInt<1>(0h0)) node _issue_entry_T_6072 = mux(issue_sel_2_2, entries_st[2].bits.cmd.cmd.inst.rs2, UInt<1>(0h0)) node _issue_entry_T_6073 = mux(issue_sel_3_2, entries_st[3].bits.cmd.cmd.inst.rs2, UInt<1>(0h0)) node _issue_entry_T_6074 = or(_issue_entry_T_6070, _issue_entry_T_6071) node _issue_entry_T_6075 = or(_issue_entry_T_6074, _issue_entry_T_6072) node _issue_entry_T_6076 = or(_issue_entry_T_6075, _issue_entry_T_6073) wire _issue_entry_WIRE_373 : UInt<5> connect _issue_entry_WIRE_373, _issue_entry_T_6076 connect _issue_entry_WIRE_366.rs2, _issue_entry_WIRE_373 node _issue_entry_T_6077 = mux(issue_sel_0_2, entries_st[0].bits.cmd.cmd.inst.funct, UInt<1>(0h0)) node _issue_entry_T_6078 = mux(issue_sel_1_2, entries_st[1].bits.cmd.cmd.inst.funct, UInt<1>(0h0)) node _issue_entry_T_6079 = mux(issue_sel_2_2, entries_st[2].bits.cmd.cmd.inst.funct, UInt<1>(0h0)) node _issue_entry_T_6080 = mux(issue_sel_3_2, entries_st[3].bits.cmd.cmd.inst.funct, UInt<1>(0h0)) node _issue_entry_T_6081 = or(_issue_entry_T_6077, _issue_entry_T_6078) node _issue_entry_T_6082 = or(_issue_entry_T_6081, _issue_entry_T_6079) node _issue_entry_T_6083 = or(_issue_entry_T_6082, _issue_entry_T_6080) wire _issue_entry_WIRE_374 : UInt<7> connect _issue_entry_WIRE_374, _issue_entry_T_6083 connect _issue_entry_WIRE_366.funct, _issue_entry_WIRE_374 connect _issue_entry_WIRE_325.inst, _issue_entry_WIRE_366 connect _issue_entry_WIRE_319.cmd, _issue_entry_WIRE_325 connect _issue_entry_WIRE_286.cmd, _issue_entry_WIRE_319 node _issue_entry_T_6084 = mux(issue_sel_0_2, entries_st[0].bits.complete_on_issue, UInt<1>(0h0)) node _issue_entry_T_6085 = mux(issue_sel_1_2, entries_st[1].bits.complete_on_issue, UInt<1>(0h0)) node _issue_entry_T_6086 = mux(issue_sel_2_2, entries_st[2].bits.complete_on_issue, UInt<1>(0h0)) node _issue_entry_T_6087 = mux(issue_sel_3_2, entries_st[3].bits.complete_on_issue, UInt<1>(0h0)) node _issue_entry_T_6088 = or(_issue_entry_T_6084, _issue_entry_T_6085) node _issue_entry_T_6089 = or(_issue_entry_T_6088, _issue_entry_T_6086) node _issue_entry_T_6090 = or(_issue_entry_T_6089, _issue_entry_T_6087) wire _issue_entry_WIRE_375 : UInt<1> connect _issue_entry_WIRE_375, _issue_entry_T_6090 connect _issue_entry_WIRE_286.complete_on_issue, _issue_entry_WIRE_375 node _issue_entry_T_6091 = mux(issue_sel_0_2, entries_st[0].bits.issued, UInt<1>(0h0)) node _issue_entry_T_6092 = mux(issue_sel_1_2, entries_st[1].bits.issued, UInt<1>(0h0)) node _issue_entry_T_6093 = mux(issue_sel_2_2, entries_st[2].bits.issued, UInt<1>(0h0)) node _issue_entry_T_6094 = mux(issue_sel_3_2, entries_st[3].bits.issued, UInt<1>(0h0)) node _issue_entry_T_6095 = or(_issue_entry_T_6091, _issue_entry_T_6092) node _issue_entry_T_6096 = or(_issue_entry_T_6095, _issue_entry_T_6093) node _issue_entry_T_6097 = or(_issue_entry_T_6096, _issue_entry_T_6094) wire _issue_entry_WIRE_376 : UInt<1> connect _issue_entry_WIRE_376, _issue_entry_T_6097 connect _issue_entry_WIRE_286.issued, _issue_entry_WIRE_376 wire _issue_entry_WIRE_377 : { valid : UInt<1>, bits : { start : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, end : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, wraps_around : UInt<1>}} wire _issue_entry_WIRE_378 : { start : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, end : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, wraps_around : UInt<1>} node _issue_entry_T_6098 = mux(issue_sel_0_2, entries_st[0].bits.opb.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_6099 = mux(issue_sel_1_2, entries_st[1].bits.opb.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_6100 = mux(issue_sel_2_2, entries_st[2].bits.opb.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_6101 = mux(issue_sel_3_2, entries_st[3].bits.opb.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_6102 = or(_issue_entry_T_6098, _issue_entry_T_6099) node _issue_entry_T_6103 = or(_issue_entry_T_6102, _issue_entry_T_6100) node _issue_entry_T_6104 = or(_issue_entry_T_6103, _issue_entry_T_6101) wire _issue_entry_WIRE_379 : UInt<1> connect _issue_entry_WIRE_379, _issue_entry_T_6104 connect _issue_entry_WIRE_378.wraps_around, _issue_entry_WIRE_379 wire _issue_entry_WIRE_380 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} node _issue_entry_T_6105 = mux(issue_sel_0_2, entries_st[0].bits.opb.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_6106 = mux(issue_sel_1_2, entries_st[1].bits.opb.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_6107 = mux(issue_sel_2_2, entries_st[2].bits.opb.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_6108 = mux(issue_sel_3_2, entries_st[3].bits.opb.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_6109 = or(_issue_entry_T_6105, _issue_entry_T_6106) node _issue_entry_T_6110 = or(_issue_entry_T_6109, _issue_entry_T_6107) node _issue_entry_T_6111 = or(_issue_entry_T_6110, _issue_entry_T_6108) wire _issue_entry_WIRE_381 : UInt<14> connect _issue_entry_WIRE_381, _issue_entry_T_6111 connect _issue_entry_WIRE_380.data, _issue_entry_WIRE_381 node _issue_entry_T_6112 = mux(issue_sel_0_2, entries_st[0].bits.opb.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_6113 = mux(issue_sel_1_2, entries_st[1].bits.opb.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_6114 = mux(issue_sel_2_2, entries_st[2].bits.opb.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_6115 = mux(issue_sel_3_2, entries_st[3].bits.opb.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_6116 = or(_issue_entry_T_6112, _issue_entry_T_6113) node _issue_entry_T_6117 = or(_issue_entry_T_6116, _issue_entry_T_6114) node _issue_entry_T_6118 = or(_issue_entry_T_6117, _issue_entry_T_6115) wire _issue_entry_WIRE_382 : UInt<1> connect _issue_entry_WIRE_382, _issue_entry_T_6118 connect _issue_entry_WIRE_380.garbage_bit, _issue_entry_WIRE_382 node _issue_entry_T_6119 = mux(issue_sel_0_2, entries_st[0].bits.opb.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_6120 = mux(issue_sel_1_2, entries_st[1].bits.opb.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_6121 = mux(issue_sel_2_2, entries_st[2].bits.opb.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_6122 = mux(issue_sel_3_2, entries_st[3].bits.opb.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_6123 = or(_issue_entry_T_6119, _issue_entry_T_6120) node _issue_entry_T_6124 = or(_issue_entry_T_6123, _issue_entry_T_6121) node _issue_entry_T_6125 = or(_issue_entry_T_6124, _issue_entry_T_6122) wire _issue_entry_WIRE_383 : UInt<11> connect _issue_entry_WIRE_383, _issue_entry_T_6125 connect _issue_entry_WIRE_380.garbage, _issue_entry_WIRE_383 node _issue_entry_T_6126 = asUInt(entries_st[0].bits.opb.bits.end.norm_cmd) node _issue_entry_T_6127 = mux(issue_sel_0_2, _issue_entry_T_6126, UInt<1>(0h0)) node _issue_entry_T_6128 = asUInt(entries_st[1].bits.opb.bits.end.norm_cmd) node _issue_entry_T_6129 = mux(issue_sel_1_2, _issue_entry_T_6128, UInt<1>(0h0)) node _issue_entry_T_6130 = asUInt(entries_st[2].bits.opb.bits.end.norm_cmd) node _issue_entry_T_6131 = mux(issue_sel_2_2, _issue_entry_T_6130, UInt<1>(0h0)) node _issue_entry_T_6132 = asUInt(entries_st[3].bits.opb.bits.end.norm_cmd) node _issue_entry_T_6133 = mux(issue_sel_3_2, _issue_entry_T_6132, UInt<1>(0h0)) node _issue_entry_T_6134 = or(_issue_entry_T_6127, _issue_entry_T_6129) node _issue_entry_T_6135 = or(_issue_entry_T_6134, _issue_entry_T_6131) node _issue_entry_T_6136 = or(_issue_entry_T_6135, _issue_entry_T_6133) wire _issue_entry_WIRE_384 : UInt<3> wire _issue_entry_WIRE_385 : UInt<3> connect _issue_entry_WIRE_385, _issue_entry_T_6136 wire _issue_entry_WIRE_386 : UInt<3> connect _issue_entry_WIRE_386, _issue_entry_WIRE_385 connect _issue_entry_WIRE_384, _issue_entry_WIRE_386 connect _issue_entry_WIRE_380.norm_cmd, _issue_entry_WIRE_384 node _issue_entry_T_6137 = mux(issue_sel_0_2, entries_st[0].bits.opb.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_6138 = mux(issue_sel_1_2, entries_st[1].bits.opb.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_6139 = mux(issue_sel_2_2, entries_st[2].bits.opb.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_6140 = mux(issue_sel_3_2, entries_st[3].bits.opb.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_6141 = or(_issue_entry_T_6137, _issue_entry_T_6138) node _issue_entry_T_6142 = or(_issue_entry_T_6141, _issue_entry_T_6139) node _issue_entry_T_6143 = or(_issue_entry_T_6142, _issue_entry_T_6140) wire _issue_entry_WIRE_387 : UInt<1> connect _issue_entry_WIRE_387, _issue_entry_T_6143 connect _issue_entry_WIRE_380.read_full_acc_row, _issue_entry_WIRE_387 node _issue_entry_T_6144 = mux(issue_sel_0_2, entries_st[0].bits.opb.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_6145 = mux(issue_sel_1_2, entries_st[1].bits.opb.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_6146 = mux(issue_sel_2_2, entries_st[2].bits.opb.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_6147 = mux(issue_sel_3_2, entries_st[3].bits.opb.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_6148 = or(_issue_entry_T_6144, _issue_entry_T_6145) node _issue_entry_T_6149 = or(_issue_entry_T_6148, _issue_entry_T_6146) node _issue_entry_T_6150 = or(_issue_entry_T_6149, _issue_entry_T_6147) wire _issue_entry_WIRE_388 : UInt<1> connect _issue_entry_WIRE_388, _issue_entry_T_6150 connect _issue_entry_WIRE_380.accumulate, _issue_entry_WIRE_388 node _issue_entry_T_6151 = mux(issue_sel_0_2, entries_st[0].bits.opb.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_6152 = mux(issue_sel_1_2, entries_st[1].bits.opb.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_6153 = mux(issue_sel_2_2, entries_st[2].bits.opb.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_6154 = mux(issue_sel_3_2, entries_st[3].bits.opb.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_6155 = or(_issue_entry_T_6151, _issue_entry_T_6152) node _issue_entry_T_6156 = or(_issue_entry_T_6155, _issue_entry_T_6153) node _issue_entry_T_6157 = or(_issue_entry_T_6156, _issue_entry_T_6154) wire _issue_entry_WIRE_389 : UInt<1> connect _issue_entry_WIRE_389, _issue_entry_T_6157 connect _issue_entry_WIRE_380.is_acc_addr, _issue_entry_WIRE_389 connect _issue_entry_WIRE_378.end, _issue_entry_WIRE_380 wire _issue_entry_WIRE_390 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} node _issue_entry_T_6158 = mux(issue_sel_0_2, entries_st[0].bits.opb.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_6159 = mux(issue_sel_1_2, entries_st[1].bits.opb.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_6160 = mux(issue_sel_2_2, entries_st[2].bits.opb.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_6161 = mux(issue_sel_3_2, entries_st[3].bits.opb.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_6162 = or(_issue_entry_T_6158, _issue_entry_T_6159) node _issue_entry_T_6163 = or(_issue_entry_T_6162, _issue_entry_T_6160) node _issue_entry_T_6164 = or(_issue_entry_T_6163, _issue_entry_T_6161) wire _issue_entry_WIRE_391 : UInt<14> connect _issue_entry_WIRE_391, _issue_entry_T_6164 connect _issue_entry_WIRE_390.data, _issue_entry_WIRE_391 node _issue_entry_T_6165 = mux(issue_sel_0_2, entries_st[0].bits.opb.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_6166 = mux(issue_sel_1_2, entries_st[1].bits.opb.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_6167 = mux(issue_sel_2_2, entries_st[2].bits.opb.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_6168 = mux(issue_sel_3_2, entries_st[3].bits.opb.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_6169 = or(_issue_entry_T_6165, _issue_entry_T_6166) node _issue_entry_T_6170 = or(_issue_entry_T_6169, _issue_entry_T_6167) node _issue_entry_T_6171 = or(_issue_entry_T_6170, _issue_entry_T_6168) wire _issue_entry_WIRE_392 : UInt<1> connect _issue_entry_WIRE_392, _issue_entry_T_6171 connect _issue_entry_WIRE_390.garbage_bit, _issue_entry_WIRE_392 node _issue_entry_T_6172 = mux(issue_sel_0_2, entries_st[0].bits.opb.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_6173 = mux(issue_sel_1_2, entries_st[1].bits.opb.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_6174 = mux(issue_sel_2_2, entries_st[2].bits.opb.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_6175 = mux(issue_sel_3_2, entries_st[3].bits.opb.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_6176 = or(_issue_entry_T_6172, _issue_entry_T_6173) node _issue_entry_T_6177 = or(_issue_entry_T_6176, _issue_entry_T_6174) node _issue_entry_T_6178 = or(_issue_entry_T_6177, _issue_entry_T_6175) wire _issue_entry_WIRE_393 : UInt<11> connect _issue_entry_WIRE_393, _issue_entry_T_6178 connect _issue_entry_WIRE_390.garbage, _issue_entry_WIRE_393 node _issue_entry_T_6179 = asUInt(entries_st[0].bits.opb.bits.start.norm_cmd) node _issue_entry_T_6180 = mux(issue_sel_0_2, _issue_entry_T_6179, UInt<1>(0h0)) node _issue_entry_T_6181 = asUInt(entries_st[1].bits.opb.bits.start.norm_cmd) node _issue_entry_T_6182 = mux(issue_sel_1_2, _issue_entry_T_6181, UInt<1>(0h0)) node _issue_entry_T_6183 = asUInt(entries_st[2].bits.opb.bits.start.norm_cmd) node _issue_entry_T_6184 = mux(issue_sel_2_2, _issue_entry_T_6183, UInt<1>(0h0)) node _issue_entry_T_6185 = asUInt(entries_st[3].bits.opb.bits.start.norm_cmd) node _issue_entry_T_6186 = mux(issue_sel_3_2, _issue_entry_T_6185, UInt<1>(0h0)) node _issue_entry_T_6187 = or(_issue_entry_T_6180, _issue_entry_T_6182) node _issue_entry_T_6188 = or(_issue_entry_T_6187, _issue_entry_T_6184) node _issue_entry_T_6189 = or(_issue_entry_T_6188, _issue_entry_T_6186) wire _issue_entry_WIRE_394 : UInt<3> wire _issue_entry_WIRE_395 : UInt<3> connect _issue_entry_WIRE_395, _issue_entry_T_6189 wire _issue_entry_WIRE_396 : UInt<3> connect _issue_entry_WIRE_396, _issue_entry_WIRE_395 connect _issue_entry_WIRE_394, _issue_entry_WIRE_396 connect _issue_entry_WIRE_390.norm_cmd, _issue_entry_WIRE_394 node _issue_entry_T_6190 = mux(issue_sel_0_2, entries_st[0].bits.opb.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_6191 = mux(issue_sel_1_2, entries_st[1].bits.opb.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_6192 = mux(issue_sel_2_2, entries_st[2].bits.opb.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_6193 = mux(issue_sel_3_2, entries_st[3].bits.opb.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_6194 = or(_issue_entry_T_6190, _issue_entry_T_6191) node _issue_entry_T_6195 = or(_issue_entry_T_6194, _issue_entry_T_6192) node _issue_entry_T_6196 = or(_issue_entry_T_6195, _issue_entry_T_6193) wire _issue_entry_WIRE_397 : UInt<1> connect _issue_entry_WIRE_397, _issue_entry_T_6196 connect _issue_entry_WIRE_390.read_full_acc_row, _issue_entry_WIRE_397 node _issue_entry_T_6197 = mux(issue_sel_0_2, entries_st[0].bits.opb.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_6198 = mux(issue_sel_1_2, entries_st[1].bits.opb.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_6199 = mux(issue_sel_2_2, entries_st[2].bits.opb.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_6200 = mux(issue_sel_3_2, entries_st[3].bits.opb.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_6201 = or(_issue_entry_T_6197, _issue_entry_T_6198) node _issue_entry_T_6202 = or(_issue_entry_T_6201, _issue_entry_T_6199) node _issue_entry_T_6203 = or(_issue_entry_T_6202, _issue_entry_T_6200) wire _issue_entry_WIRE_398 : UInt<1> connect _issue_entry_WIRE_398, _issue_entry_T_6203 connect _issue_entry_WIRE_390.accumulate, _issue_entry_WIRE_398 node _issue_entry_T_6204 = mux(issue_sel_0_2, entries_st[0].bits.opb.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_6205 = mux(issue_sel_1_2, entries_st[1].bits.opb.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_6206 = mux(issue_sel_2_2, entries_st[2].bits.opb.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_6207 = mux(issue_sel_3_2, entries_st[3].bits.opb.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_6208 = or(_issue_entry_T_6204, _issue_entry_T_6205) node _issue_entry_T_6209 = or(_issue_entry_T_6208, _issue_entry_T_6206) node _issue_entry_T_6210 = or(_issue_entry_T_6209, _issue_entry_T_6207) wire _issue_entry_WIRE_399 : UInt<1> connect _issue_entry_WIRE_399, _issue_entry_T_6210 connect _issue_entry_WIRE_390.is_acc_addr, _issue_entry_WIRE_399 connect _issue_entry_WIRE_378.start, _issue_entry_WIRE_390 connect _issue_entry_WIRE_377.bits, _issue_entry_WIRE_378 node _issue_entry_T_6211 = mux(issue_sel_0_2, entries_st[0].bits.opb.valid, UInt<1>(0h0)) node _issue_entry_T_6212 = mux(issue_sel_1_2, entries_st[1].bits.opb.valid, UInt<1>(0h0)) node _issue_entry_T_6213 = mux(issue_sel_2_2, entries_st[2].bits.opb.valid, UInt<1>(0h0)) node _issue_entry_T_6214 = mux(issue_sel_3_2, entries_st[3].bits.opb.valid, UInt<1>(0h0)) node _issue_entry_T_6215 = or(_issue_entry_T_6211, _issue_entry_T_6212) node _issue_entry_T_6216 = or(_issue_entry_T_6215, _issue_entry_T_6213) node _issue_entry_T_6217 = or(_issue_entry_T_6216, _issue_entry_T_6214) wire _issue_entry_WIRE_400 : UInt<1> connect _issue_entry_WIRE_400, _issue_entry_T_6217 connect _issue_entry_WIRE_377.valid, _issue_entry_WIRE_400 connect _issue_entry_WIRE_286.opb, _issue_entry_WIRE_377 node _issue_entry_T_6218 = mux(issue_sel_0_2, entries_st[0].bits.opa_is_dst, UInt<1>(0h0)) node _issue_entry_T_6219 = mux(issue_sel_1_2, entries_st[1].bits.opa_is_dst, UInt<1>(0h0)) node _issue_entry_T_6220 = mux(issue_sel_2_2, entries_st[2].bits.opa_is_dst, UInt<1>(0h0)) node _issue_entry_T_6221 = mux(issue_sel_3_2, entries_st[3].bits.opa_is_dst, UInt<1>(0h0)) node _issue_entry_T_6222 = or(_issue_entry_T_6218, _issue_entry_T_6219) node _issue_entry_T_6223 = or(_issue_entry_T_6222, _issue_entry_T_6220) node _issue_entry_T_6224 = or(_issue_entry_T_6223, _issue_entry_T_6221) wire _issue_entry_WIRE_401 : UInt<1> connect _issue_entry_WIRE_401, _issue_entry_T_6224 connect _issue_entry_WIRE_286.opa_is_dst, _issue_entry_WIRE_401 wire _issue_entry_WIRE_402 : { valid : UInt<1>, bits : { start : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, end : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, wraps_around : UInt<1>}} wire _issue_entry_WIRE_403 : { start : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, end : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, wraps_around : UInt<1>} node _issue_entry_T_6225 = mux(issue_sel_0_2, entries_st[0].bits.opa.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_6226 = mux(issue_sel_1_2, entries_st[1].bits.opa.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_6227 = mux(issue_sel_2_2, entries_st[2].bits.opa.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_6228 = mux(issue_sel_3_2, entries_st[3].bits.opa.bits.wraps_around, UInt<1>(0h0)) node _issue_entry_T_6229 = or(_issue_entry_T_6225, _issue_entry_T_6226) node _issue_entry_T_6230 = or(_issue_entry_T_6229, _issue_entry_T_6227) node _issue_entry_T_6231 = or(_issue_entry_T_6230, _issue_entry_T_6228) wire _issue_entry_WIRE_404 : UInt<1> connect _issue_entry_WIRE_404, _issue_entry_T_6231 connect _issue_entry_WIRE_403.wraps_around, _issue_entry_WIRE_404 wire _issue_entry_WIRE_405 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} node _issue_entry_T_6232 = mux(issue_sel_0_2, entries_st[0].bits.opa.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_6233 = mux(issue_sel_1_2, entries_st[1].bits.opa.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_6234 = mux(issue_sel_2_2, entries_st[2].bits.opa.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_6235 = mux(issue_sel_3_2, entries_st[3].bits.opa.bits.end.data, UInt<1>(0h0)) node _issue_entry_T_6236 = or(_issue_entry_T_6232, _issue_entry_T_6233) node _issue_entry_T_6237 = or(_issue_entry_T_6236, _issue_entry_T_6234) node _issue_entry_T_6238 = or(_issue_entry_T_6237, _issue_entry_T_6235) wire _issue_entry_WIRE_406 : UInt<14> connect _issue_entry_WIRE_406, _issue_entry_T_6238 connect _issue_entry_WIRE_405.data, _issue_entry_WIRE_406 node _issue_entry_T_6239 = mux(issue_sel_0_2, entries_st[0].bits.opa.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_6240 = mux(issue_sel_1_2, entries_st[1].bits.opa.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_6241 = mux(issue_sel_2_2, entries_st[2].bits.opa.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_6242 = mux(issue_sel_3_2, entries_st[3].bits.opa.bits.end.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_6243 = or(_issue_entry_T_6239, _issue_entry_T_6240) node _issue_entry_T_6244 = or(_issue_entry_T_6243, _issue_entry_T_6241) node _issue_entry_T_6245 = or(_issue_entry_T_6244, _issue_entry_T_6242) wire _issue_entry_WIRE_407 : UInt<1> connect _issue_entry_WIRE_407, _issue_entry_T_6245 connect _issue_entry_WIRE_405.garbage_bit, _issue_entry_WIRE_407 node _issue_entry_T_6246 = mux(issue_sel_0_2, entries_st[0].bits.opa.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_6247 = mux(issue_sel_1_2, entries_st[1].bits.opa.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_6248 = mux(issue_sel_2_2, entries_st[2].bits.opa.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_6249 = mux(issue_sel_3_2, entries_st[3].bits.opa.bits.end.garbage, UInt<1>(0h0)) node _issue_entry_T_6250 = or(_issue_entry_T_6246, _issue_entry_T_6247) node _issue_entry_T_6251 = or(_issue_entry_T_6250, _issue_entry_T_6248) node _issue_entry_T_6252 = or(_issue_entry_T_6251, _issue_entry_T_6249) wire _issue_entry_WIRE_408 : UInt<11> connect _issue_entry_WIRE_408, _issue_entry_T_6252 connect _issue_entry_WIRE_405.garbage, _issue_entry_WIRE_408 node _issue_entry_T_6253 = asUInt(entries_st[0].bits.opa.bits.end.norm_cmd) node _issue_entry_T_6254 = mux(issue_sel_0_2, _issue_entry_T_6253, UInt<1>(0h0)) node _issue_entry_T_6255 = asUInt(entries_st[1].bits.opa.bits.end.norm_cmd) node _issue_entry_T_6256 = mux(issue_sel_1_2, _issue_entry_T_6255, UInt<1>(0h0)) node _issue_entry_T_6257 = asUInt(entries_st[2].bits.opa.bits.end.norm_cmd) node _issue_entry_T_6258 = mux(issue_sel_2_2, _issue_entry_T_6257, UInt<1>(0h0)) node _issue_entry_T_6259 = asUInt(entries_st[3].bits.opa.bits.end.norm_cmd) node _issue_entry_T_6260 = mux(issue_sel_3_2, _issue_entry_T_6259, UInt<1>(0h0)) node _issue_entry_T_6261 = or(_issue_entry_T_6254, _issue_entry_T_6256) node _issue_entry_T_6262 = or(_issue_entry_T_6261, _issue_entry_T_6258) node _issue_entry_T_6263 = or(_issue_entry_T_6262, _issue_entry_T_6260) wire _issue_entry_WIRE_409 : UInt<3> wire _issue_entry_WIRE_410 : UInt<3> connect _issue_entry_WIRE_410, _issue_entry_T_6263 wire _issue_entry_WIRE_411 : UInt<3> connect _issue_entry_WIRE_411, _issue_entry_WIRE_410 connect _issue_entry_WIRE_409, _issue_entry_WIRE_411 connect _issue_entry_WIRE_405.norm_cmd, _issue_entry_WIRE_409 node _issue_entry_T_6264 = mux(issue_sel_0_2, entries_st[0].bits.opa.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_6265 = mux(issue_sel_1_2, entries_st[1].bits.opa.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_6266 = mux(issue_sel_2_2, entries_st[2].bits.opa.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_6267 = mux(issue_sel_3_2, entries_st[3].bits.opa.bits.end.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_6268 = or(_issue_entry_T_6264, _issue_entry_T_6265) node _issue_entry_T_6269 = or(_issue_entry_T_6268, _issue_entry_T_6266) node _issue_entry_T_6270 = or(_issue_entry_T_6269, _issue_entry_T_6267) wire _issue_entry_WIRE_412 : UInt<1> connect _issue_entry_WIRE_412, _issue_entry_T_6270 connect _issue_entry_WIRE_405.read_full_acc_row, _issue_entry_WIRE_412 node _issue_entry_T_6271 = mux(issue_sel_0_2, entries_st[0].bits.opa.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_6272 = mux(issue_sel_1_2, entries_st[1].bits.opa.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_6273 = mux(issue_sel_2_2, entries_st[2].bits.opa.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_6274 = mux(issue_sel_3_2, entries_st[3].bits.opa.bits.end.accumulate, UInt<1>(0h0)) node _issue_entry_T_6275 = or(_issue_entry_T_6271, _issue_entry_T_6272) node _issue_entry_T_6276 = or(_issue_entry_T_6275, _issue_entry_T_6273) node _issue_entry_T_6277 = or(_issue_entry_T_6276, _issue_entry_T_6274) wire _issue_entry_WIRE_413 : UInt<1> connect _issue_entry_WIRE_413, _issue_entry_T_6277 connect _issue_entry_WIRE_405.accumulate, _issue_entry_WIRE_413 node _issue_entry_T_6278 = mux(issue_sel_0_2, entries_st[0].bits.opa.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_6279 = mux(issue_sel_1_2, entries_st[1].bits.opa.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_6280 = mux(issue_sel_2_2, entries_st[2].bits.opa.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_6281 = mux(issue_sel_3_2, entries_st[3].bits.opa.bits.end.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_6282 = or(_issue_entry_T_6278, _issue_entry_T_6279) node _issue_entry_T_6283 = or(_issue_entry_T_6282, _issue_entry_T_6280) node _issue_entry_T_6284 = or(_issue_entry_T_6283, _issue_entry_T_6281) wire _issue_entry_WIRE_414 : UInt<1> connect _issue_entry_WIRE_414, _issue_entry_T_6284 connect _issue_entry_WIRE_405.is_acc_addr, _issue_entry_WIRE_414 connect _issue_entry_WIRE_403.end, _issue_entry_WIRE_405 wire _issue_entry_WIRE_415 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} node _issue_entry_T_6285 = mux(issue_sel_0_2, entries_st[0].bits.opa.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_6286 = mux(issue_sel_1_2, entries_st[1].bits.opa.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_6287 = mux(issue_sel_2_2, entries_st[2].bits.opa.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_6288 = mux(issue_sel_3_2, entries_st[3].bits.opa.bits.start.data, UInt<1>(0h0)) node _issue_entry_T_6289 = or(_issue_entry_T_6285, _issue_entry_T_6286) node _issue_entry_T_6290 = or(_issue_entry_T_6289, _issue_entry_T_6287) node _issue_entry_T_6291 = or(_issue_entry_T_6290, _issue_entry_T_6288) wire _issue_entry_WIRE_416 : UInt<14> connect _issue_entry_WIRE_416, _issue_entry_T_6291 connect _issue_entry_WIRE_415.data, _issue_entry_WIRE_416 node _issue_entry_T_6292 = mux(issue_sel_0_2, entries_st[0].bits.opa.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_6293 = mux(issue_sel_1_2, entries_st[1].bits.opa.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_6294 = mux(issue_sel_2_2, entries_st[2].bits.opa.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_6295 = mux(issue_sel_3_2, entries_st[3].bits.opa.bits.start.garbage_bit, UInt<1>(0h0)) node _issue_entry_T_6296 = or(_issue_entry_T_6292, _issue_entry_T_6293) node _issue_entry_T_6297 = or(_issue_entry_T_6296, _issue_entry_T_6294) node _issue_entry_T_6298 = or(_issue_entry_T_6297, _issue_entry_T_6295) wire _issue_entry_WIRE_417 : UInt<1> connect _issue_entry_WIRE_417, _issue_entry_T_6298 connect _issue_entry_WIRE_415.garbage_bit, _issue_entry_WIRE_417 node _issue_entry_T_6299 = mux(issue_sel_0_2, entries_st[0].bits.opa.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_6300 = mux(issue_sel_1_2, entries_st[1].bits.opa.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_6301 = mux(issue_sel_2_2, entries_st[2].bits.opa.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_6302 = mux(issue_sel_3_2, entries_st[3].bits.opa.bits.start.garbage, UInt<1>(0h0)) node _issue_entry_T_6303 = or(_issue_entry_T_6299, _issue_entry_T_6300) node _issue_entry_T_6304 = or(_issue_entry_T_6303, _issue_entry_T_6301) node _issue_entry_T_6305 = or(_issue_entry_T_6304, _issue_entry_T_6302) wire _issue_entry_WIRE_418 : UInt<11> connect _issue_entry_WIRE_418, _issue_entry_T_6305 connect _issue_entry_WIRE_415.garbage, _issue_entry_WIRE_418 node _issue_entry_T_6306 = asUInt(entries_st[0].bits.opa.bits.start.norm_cmd) node _issue_entry_T_6307 = mux(issue_sel_0_2, _issue_entry_T_6306, UInt<1>(0h0)) node _issue_entry_T_6308 = asUInt(entries_st[1].bits.opa.bits.start.norm_cmd) node _issue_entry_T_6309 = mux(issue_sel_1_2, _issue_entry_T_6308, UInt<1>(0h0)) node _issue_entry_T_6310 = asUInt(entries_st[2].bits.opa.bits.start.norm_cmd) node _issue_entry_T_6311 = mux(issue_sel_2_2, _issue_entry_T_6310, UInt<1>(0h0)) node _issue_entry_T_6312 = asUInt(entries_st[3].bits.opa.bits.start.norm_cmd) node _issue_entry_T_6313 = mux(issue_sel_3_2, _issue_entry_T_6312, UInt<1>(0h0)) node _issue_entry_T_6314 = or(_issue_entry_T_6307, _issue_entry_T_6309) node _issue_entry_T_6315 = or(_issue_entry_T_6314, _issue_entry_T_6311) node _issue_entry_T_6316 = or(_issue_entry_T_6315, _issue_entry_T_6313) wire _issue_entry_WIRE_419 : UInt<3> wire _issue_entry_WIRE_420 : UInt<3> connect _issue_entry_WIRE_420, _issue_entry_T_6316 wire _issue_entry_WIRE_421 : UInt<3> connect _issue_entry_WIRE_421, _issue_entry_WIRE_420 connect _issue_entry_WIRE_419, _issue_entry_WIRE_421 connect _issue_entry_WIRE_415.norm_cmd, _issue_entry_WIRE_419 node _issue_entry_T_6317 = mux(issue_sel_0_2, entries_st[0].bits.opa.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_6318 = mux(issue_sel_1_2, entries_st[1].bits.opa.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_6319 = mux(issue_sel_2_2, entries_st[2].bits.opa.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_6320 = mux(issue_sel_3_2, entries_st[3].bits.opa.bits.start.read_full_acc_row, UInt<1>(0h0)) node _issue_entry_T_6321 = or(_issue_entry_T_6317, _issue_entry_T_6318) node _issue_entry_T_6322 = or(_issue_entry_T_6321, _issue_entry_T_6319) node _issue_entry_T_6323 = or(_issue_entry_T_6322, _issue_entry_T_6320) wire _issue_entry_WIRE_422 : UInt<1> connect _issue_entry_WIRE_422, _issue_entry_T_6323 connect _issue_entry_WIRE_415.read_full_acc_row, _issue_entry_WIRE_422 node _issue_entry_T_6324 = mux(issue_sel_0_2, entries_st[0].bits.opa.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_6325 = mux(issue_sel_1_2, entries_st[1].bits.opa.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_6326 = mux(issue_sel_2_2, entries_st[2].bits.opa.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_6327 = mux(issue_sel_3_2, entries_st[3].bits.opa.bits.start.accumulate, UInt<1>(0h0)) node _issue_entry_T_6328 = or(_issue_entry_T_6324, _issue_entry_T_6325) node _issue_entry_T_6329 = or(_issue_entry_T_6328, _issue_entry_T_6326) node _issue_entry_T_6330 = or(_issue_entry_T_6329, _issue_entry_T_6327) wire _issue_entry_WIRE_423 : UInt<1> connect _issue_entry_WIRE_423, _issue_entry_T_6330 connect _issue_entry_WIRE_415.accumulate, _issue_entry_WIRE_423 node _issue_entry_T_6331 = mux(issue_sel_0_2, entries_st[0].bits.opa.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_6332 = mux(issue_sel_1_2, entries_st[1].bits.opa.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_6333 = mux(issue_sel_2_2, entries_st[2].bits.opa.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_6334 = mux(issue_sel_3_2, entries_st[3].bits.opa.bits.start.is_acc_addr, UInt<1>(0h0)) node _issue_entry_T_6335 = or(_issue_entry_T_6331, _issue_entry_T_6332) node _issue_entry_T_6336 = or(_issue_entry_T_6335, _issue_entry_T_6333) node _issue_entry_T_6337 = or(_issue_entry_T_6336, _issue_entry_T_6334) wire _issue_entry_WIRE_424 : UInt<1> connect _issue_entry_WIRE_424, _issue_entry_T_6337 connect _issue_entry_WIRE_415.is_acc_addr, _issue_entry_WIRE_424 connect _issue_entry_WIRE_403.start, _issue_entry_WIRE_415 connect _issue_entry_WIRE_402.bits, _issue_entry_WIRE_403 node _issue_entry_T_6338 = mux(issue_sel_0_2, entries_st[0].bits.opa.valid, UInt<1>(0h0)) node _issue_entry_T_6339 = mux(issue_sel_1_2, entries_st[1].bits.opa.valid, UInt<1>(0h0)) node _issue_entry_T_6340 = mux(issue_sel_2_2, entries_st[2].bits.opa.valid, UInt<1>(0h0)) node _issue_entry_T_6341 = mux(issue_sel_3_2, entries_st[3].bits.opa.valid, UInt<1>(0h0)) node _issue_entry_T_6342 = or(_issue_entry_T_6338, _issue_entry_T_6339) node _issue_entry_T_6343 = or(_issue_entry_T_6342, _issue_entry_T_6340) node _issue_entry_T_6344 = or(_issue_entry_T_6343, _issue_entry_T_6341) wire _issue_entry_WIRE_425 : UInt<1> connect _issue_entry_WIRE_425, _issue_entry_T_6344 connect _issue_entry_WIRE_402.valid, _issue_entry_WIRE_425 connect _issue_entry_WIRE_286.opa, _issue_entry_WIRE_402 node _issue_entry_T_6345 = mux(issue_sel_0_2, entries_st[0].bits.is_config, UInt<1>(0h0)) node _issue_entry_T_6346 = mux(issue_sel_1_2, entries_st[1].bits.is_config, UInt<1>(0h0)) node _issue_entry_T_6347 = mux(issue_sel_2_2, entries_st[2].bits.is_config, UInt<1>(0h0)) node _issue_entry_T_6348 = mux(issue_sel_3_2, entries_st[3].bits.is_config, UInt<1>(0h0)) node _issue_entry_T_6349 = or(_issue_entry_T_6345, _issue_entry_T_6346) node _issue_entry_T_6350 = or(_issue_entry_T_6349, _issue_entry_T_6347) node _issue_entry_T_6351 = or(_issue_entry_T_6350, _issue_entry_T_6348) wire _issue_entry_WIRE_426 : UInt<1> connect _issue_entry_WIRE_426, _issue_entry_T_6351 connect _issue_entry_WIRE_286.is_config, _issue_entry_WIRE_426 node _issue_entry_T_6352 = mux(issue_sel_0_2, entries_st[0].bits.q, UInt<1>(0h0)) node _issue_entry_T_6353 = mux(issue_sel_1_2, entries_st[1].bits.q, UInt<1>(0h0)) node _issue_entry_T_6354 = mux(issue_sel_2_2, entries_st[2].bits.q, UInt<1>(0h0)) node _issue_entry_T_6355 = mux(issue_sel_3_2, entries_st[3].bits.q, UInt<1>(0h0)) node _issue_entry_T_6356 = or(_issue_entry_T_6352, _issue_entry_T_6353) node _issue_entry_T_6357 = or(_issue_entry_T_6356, _issue_entry_T_6354) node _issue_entry_T_6358 = or(_issue_entry_T_6357, _issue_entry_T_6355) wire _issue_entry_WIRE_427 : UInt<2> connect _issue_entry_WIRE_427, _issue_entry_T_6358 connect _issue_entry_WIRE_286.q, _issue_entry_WIRE_427 connect issue_entry_2.bits, _issue_entry_WIRE_286 node _issue_entry_T_6359 = mux(issue_sel_0_2, entries_st[0].valid, UInt<1>(0h0)) node _issue_entry_T_6360 = mux(issue_sel_1_2, entries_st[1].valid, UInt<1>(0h0)) node _issue_entry_T_6361 = mux(issue_sel_2_2, entries_st[2].valid, UInt<1>(0h0)) node _issue_entry_T_6362 = mux(issue_sel_3_2, entries_st[3].valid, UInt<1>(0h0)) node _issue_entry_T_6363 = or(_issue_entry_T_6359, _issue_entry_T_6360) node _issue_entry_T_6364 = or(_issue_entry_T_6363, _issue_entry_T_6361) node _issue_entry_T_6365 = or(_issue_entry_T_6364, _issue_entry_T_6362) wire _issue_entry_WIRE_428 : UInt<1> connect _issue_entry_WIRE_428, _issue_entry_T_6365 connect issue_entry_2.valid, _issue_entry_WIRE_428 node _io_issue_st_valid_T = or(issue_valids_0_2, issue_valids_1_2) node _io_issue_st_valid_T_1 = or(_io_issue_st_valid_T, issue_valids_2_2) node _io_issue_st_valid_T_2 = or(_io_issue_st_valid_T_1, issue_valids_3_2) connect io.issue.st.valid, _io_issue_st_valid_T_2 connect io.issue.st.cmd, issue_entry_2.bits.cmd connect io.issue.st.rob_id, global_issue_id_2 node _T_4902 = and(io.issue.st.valid, io.issue.st.ready) when _T_4902 : when issue_sel_0_2 : connect entries_st[0].bits.issued, UInt<1>(0h1) node _entries_st_0_valid_T = eq(entries_st[0].bits.complete_on_issue, UInt<1>(0h0)) connect entries_st[0].valid, _entries_st_0_valid_T when issue_sel_1_2 : connect entries_st[1].bits.issued, UInt<1>(0h1) node _entries_st_1_valid_T = eq(entries_st[1].bits.complete_on_issue, UInt<1>(0h0)) connect entries_st[1].valid, _entries_st_1_valid_T when issue_sel_2_2 : connect entries_st[2].bits.issued, UInt<1>(0h1) node _entries_st_2_valid_T = eq(entries_st[2].bits.complete_on_issue, UInt<1>(0h0)) connect entries_st[2].valid, _entries_st_2_valid_T when issue_sel_3_2 : connect entries_st[3].bits.issued, UInt<1>(0h1) node _entries_st_3_valid_T = eq(entries_st[3].bits.complete_on_issue, UInt<1>(0h0)) connect entries_st[3].valid, _entries_st_3_valid_T node _T_4903 = eq(UInt<2>(0h2), UInt<2>(0h0)) when _T_4903 : connect entries_ld[0].bits.deps_st[issue_id_2], UInt<1>(0h0) else : when issue_entry_2.bits.complete_on_issue : connect entries_ld[0].bits.deps_st[issue_id_2], UInt<1>(0h0) node _T_4904 = eq(UInt<2>(0h2), UInt<2>(0h0)) when _T_4904 : connect entries_ld[1].bits.deps_st[issue_id_2], UInt<1>(0h0) else : when issue_entry_2.bits.complete_on_issue : connect entries_ld[1].bits.deps_st[issue_id_2], UInt<1>(0h0) node _T_4905 = eq(UInt<2>(0h2), UInt<2>(0h0)) when _T_4905 : connect entries_ld[2].bits.deps_st[issue_id_2], UInt<1>(0h0) else : when issue_entry_2.bits.complete_on_issue : connect entries_ld[2].bits.deps_st[issue_id_2], UInt<1>(0h0) node _T_4906 = eq(UInt<2>(0h2), UInt<2>(0h0)) when _T_4906 : connect entries_ld[3].bits.deps_st[issue_id_2], UInt<1>(0h0) else : when issue_entry_2.bits.complete_on_issue : connect entries_ld[3].bits.deps_st[issue_id_2], UInt<1>(0h0) node _T_4907 = eq(UInt<2>(0h2), UInt<2>(0h0)) when _T_4907 : connect entries_ld[4].bits.deps_st[issue_id_2], UInt<1>(0h0) else : when issue_entry_2.bits.complete_on_issue : connect entries_ld[4].bits.deps_st[issue_id_2], UInt<1>(0h0) node _T_4908 = eq(UInt<2>(0h2), UInt<2>(0h0)) when _T_4908 : connect entries_ld[5].bits.deps_st[issue_id_2], UInt<1>(0h0) else : when issue_entry_2.bits.complete_on_issue : connect entries_ld[5].bits.deps_st[issue_id_2], UInt<1>(0h0) node _T_4909 = eq(UInt<2>(0h2), UInt<2>(0h0)) when _T_4909 : connect entries_ld[6].bits.deps_st[issue_id_2], UInt<1>(0h0) else : when issue_entry_2.bits.complete_on_issue : connect entries_ld[6].bits.deps_st[issue_id_2], UInt<1>(0h0) node _T_4910 = eq(UInt<2>(0h2), UInt<2>(0h0)) when _T_4910 : connect entries_ld[7].bits.deps_st[issue_id_2], UInt<1>(0h0) else : when issue_entry_2.bits.complete_on_issue : connect entries_ld[7].bits.deps_st[issue_id_2], UInt<1>(0h0) node _T_4911 = eq(UInt<2>(0h2), UInt<2>(0h1)) when _T_4911 : connect entries_ex[0].bits.deps_st[issue_id_2], UInt<1>(0h0) else : when issue_entry_2.bits.complete_on_issue : connect entries_ex[0].bits.deps_st[issue_id_2], UInt<1>(0h0) node _T_4912 = eq(UInt<2>(0h2), UInt<2>(0h1)) when _T_4912 : connect entries_ex[1].bits.deps_st[issue_id_2], UInt<1>(0h0) else : when issue_entry_2.bits.complete_on_issue : connect entries_ex[1].bits.deps_st[issue_id_2], UInt<1>(0h0) node _T_4913 = eq(UInt<2>(0h2), UInt<2>(0h1)) when _T_4913 : connect entries_ex[2].bits.deps_st[issue_id_2], UInt<1>(0h0) else : when issue_entry_2.bits.complete_on_issue : connect entries_ex[2].bits.deps_st[issue_id_2], UInt<1>(0h0) node _T_4914 = eq(UInt<2>(0h2), UInt<2>(0h1)) when _T_4914 : connect entries_ex[3].bits.deps_st[issue_id_2], UInt<1>(0h0) else : when issue_entry_2.bits.complete_on_issue : connect entries_ex[3].bits.deps_st[issue_id_2], UInt<1>(0h0) node _T_4915 = eq(UInt<2>(0h2), UInt<2>(0h1)) when _T_4915 : connect entries_ex[4].bits.deps_st[issue_id_2], UInt<1>(0h0) else : when issue_entry_2.bits.complete_on_issue : connect entries_ex[4].bits.deps_st[issue_id_2], UInt<1>(0h0) node _T_4916 = eq(UInt<2>(0h2), UInt<2>(0h1)) when _T_4916 : connect entries_ex[5].bits.deps_st[issue_id_2], UInt<1>(0h0) else : when issue_entry_2.bits.complete_on_issue : connect entries_ex[5].bits.deps_st[issue_id_2], UInt<1>(0h0) node _T_4917 = eq(UInt<2>(0h2), UInt<2>(0h1)) when _T_4917 : connect entries_ex[6].bits.deps_st[issue_id_2], UInt<1>(0h0) else : when issue_entry_2.bits.complete_on_issue : connect entries_ex[6].bits.deps_st[issue_id_2], UInt<1>(0h0) node _T_4918 = eq(UInt<2>(0h2), UInt<2>(0h1)) when _T_4918 : connect entries_ex[7].bits.deps_st[issue_id_2], UInt<1>(0h0) else : when issue_entry_2.bits.complete_on_issue : connect entries_ex[7].bits.deps_st[issue_id_2], UInt<1>(0h0) node _T_4919 = eq(UInt<2>(0h2), UInt<2>(0h1)) when _T_4919 : connect entries_ex[8].bits.deps_st[issue_id_2], UInt<1>(0h0) else : when issue_entry_2.bits.complete_on_issue : connect entries_ex[8].bits.deps_st[issue_id_2], UInt<1>(0h0) node _T_4920 = eq(UInt<2>(0h2), UInt<2>(0h1)) when _T_4920 : connect entries_ex[9].bits.deps_st[issue_id_2], UInt<1>(0h0) else : when issue_entry_2.bits.complete_on_issue : connect entries_ex[9].bits.deps_st[issue_id_2], UInt<1>(0h0) node _T_4921 = eq(UInt<2>(0h2), UInt<2>(0h1)) when _T_4921 : connect entries_ex[10].bits.deps_st[issue_id_2], UInt<1>(0h0) else : when issue_entry_2.bits.complete_on_issue : connect entries_ex[10].bits.deps_st[issue_id_2], UInt<1>(0h0) node _T_4922 = eq(UInt<2>(0h2), UInt<2>(0h1)) when _T_4922 : connect entries_ex[11].bits.deps_st[issue_id_2], UInt<1>(0h0) else : when issue_entry_2.bits.complete_on_issue : connect entries_ex[11].bits.deps_st[issue_id_2], UInt<1>(0h0) node _T_4923 = eq(UInt<2>(0h2), UInt<2>(0h1)) when _T_4923 : connect entries_ex[12].bits.deps_st[issue_id_2], UInt<1>(0h0) else : when issue_entry_2.bits.complete_on_issue : connect entries_ex[12].bits.deps_st[issue_id_2], UInt<1>(0h0) node _T_4924 = eq(UInt<2>(0h2), UInt<2>(0h1)) when _T_4924 : connect entries_ex[13].bits.deps_st[issue_id_2], UInt<1>(0h0) else : when issue_entry_2.bits.complete_on_issue : connect entries_ex[13].bits.deps_st[issue_id_2], UInt<1>(0h0) node _T_4925 = eq(UInt<2>(0h2), UInt<2>(0h1)) when _T_4925 : connect entries_ex[14].bits.deps_st[issue_id_2], UInt<1>(0h0) else : when issue_entry_2.bits.complete_on_issue : connect entries_ex[14].bits.deps_st[issue_id_2], UInt<1>(0h0) node _T_4926 = eq(UInt<2>(0h2), UInt<2>(0h1)) when _T_4926 : connect entries_ex[15].bits.deps_st[issue_id_2], UInt<1>(0h0) else : when issue_entry_2.bits.complete_on_issue : connect entries_ex[15].bits.deps_st[issue_id_2], UInt<1>(0h0) node _T_4927 = eq(UInt<2>(0h2), UInt<2>(0h2)) when _T_4927 : connect entries_st[0].bits.deps_st[issue_id_2], UInt<1>(0h0) else : when issue_entry_2.bits.complete_on_issue : connect entries_st[0].bits.deps_st[issue_id_2], UInt<1>(0h0) node _T_4928 = eq(UInt<2>(0h2), UInt<2>(0h2)) when _T_4928 : connect entries_st[1].bits.deps_st[issue_id_2], UInt<1>(0h0) else : when issue_entry_2.bits.complete_on_issue : connect entries_st[1].bits.deps_st[issue_id_2], UInt<1>(0h0) node _T_4929 = eq(UInt<2>(0h2), UInt<2>(0h2)) when _T_4929 : connect entries_st[2].bits.deps_st[issue_id_2], UInt<1>(0h0) else : when issue_entry_2.bits.complete_on_issue : connect entries_st[2].bits.deps_st[issue_id_2], UInt<1>(0h0) node _T_4930 = eq(UInt<2>(0h2), UInt<2>(0h2)) when _T_4930 : connect entries_st[3].bits.deps_st[issue_id_2], UInt<1>(0h0) else : when issue_entry_2.bits.complete_on_issue : connect entries_st[3].bits.deps_st[issue_id_2], UInt<1>(0h0) node _T_4931 = eq(UInt<2>(0h2), UInt<2>(0h0)) when _T_4931 : node _conv_ld_issue_completed_T_2 = and(entries_st[issue_id_2].bits.complete_on_issue, entries_st[issue_id_2].bits.cmd.from_conv_fsm) connect conv_ld_issue_completed, _conv_ld_issue_completed_T_2 node _T_4932 = eq(UInt<2>(0h2), UInt<2>(0h2)) when _T_4932 : node _conv_st_issue_completed_T_2 = and(entries_st[issue_id_2].bits.complete_on_issue, entries_st[issue_id_2].bits.cmd.from_conv_fsm) connect conv_st_issue_completed, _conv_st_issue_completed_T_2 node _T_4933 = eq(UInt<2>(0h2), UInt<2>(0h1)) when _T_4933 : node _conv_ex_issue_completed_T_2 = and(entries_st[issue_id_2].bits.complete_on_issue, entries_st[issue_id_2].bits.cmd.from_conv_fsm) connect conv_ex_issue_completed, _conv_ex_issue_completed_T_2 node _T_4934 = eq(UInt<2>(0h2), UInt<2>(0h0)) when _T_4934 : node _matmul_ld_issue_completed_T_2 = and(entries_st[issue_id_2].bits.complete_on_issue, entries_st[issue_id_2].bits.cmd.from_matmul_fsm) connect matmul_ld_issue_completed, _matmul_ld_issue_completed_T_2 node _T_4935 = eq(UInt<2>(0h2), UInt<2>(0h2)) when _T_4935 : node _matmul_st_issue_completed_T_2 = and(entries_st[issue_id_2].bits.complete_on_issue, entries_st[issue_id_2].bits.cmd.from_matmul_fsm) connect matmul_st_issue_completed, _matmul_st_issue_completed_T_2 node _T_4936 = eq(UInt<2>(0h2), UInt<2>(0h1)) when _T_4936 : node _matmul_ex_issue_completed_T_2 = and(entries_st[issue_id_2].bits.complete_on_issue, entries_st[issue_id_2].bits.cmd.from_matmul_fsm) connect matmul_ex_issue_completed, _matmul_ex_issue_completed_T_2 when io.completed.valid : node queue_type = bits(io.completed.bits, 5, 4) node issue_id_3 = bits(io.completed.bits, 3, 0) node _T_4937 = eq(queue_type, UInt<2>(0h0)) when _T_4937 : node _T_4938 = bits(issue_id_3, 2, 0) connect entries_ld[0].bits.deps_ld[_T_4938], UInt<1>(0h0) node _T_4939 = bits(issue_id_3, 2, 0) connect entries_ld[1].bits.deps_ld[_T_4939], UInt<1>(0h0) node _T_4940 = bits(issue_id_3, 2, 0) connect entries_ld[2].bits.deps_ld[_T_4940], UInt<1>(0h0) node _T_4941 = bits(issue_id_3, 2, 0) connect entries_ld[3].bits.deps_ld[_T_4941], UInt<1>(0h0) node _T_4942 = bits(issue_id_3, 2, 0) connect entries_ld[4].bits.deps_ld[_T_4942], UInt<1>(0h0) node _T_4943 = bits(issue_id_3, 2, 0) connect entries_ld[5].bits.deps_ld[_T_4943], UInt<1>(0h0) node _T_4944 = bits(issue_id_3, 2, 0) connect entries_ld[6].bits.deps_ld[_T_4944], UInt<1>(0h0) node _T_4945 = bits(issue_id_3, 2, 0) connect entries_ld[7].bits.deps_ld[_T_4945], UInt<1>(0h0) node _T_4946 = bits(issue_id_3, 2, 0) connect entries_ex[0].bits.deps_ld[_T_4946], UInt<1>(0h0) node _T_4947 = bits(issue_id_3, 2, 0) connect entries_ex[1].bits.deps_ld[_T_4947], UInt<1>(0h0) node _T_4948 = bits(issue_id_3, 2, 0) connect entries_ex[2].bits.deps_ld[_T_4948], UInt<1>(0h0) node _T_4949 = bits(issue_id_3, 2, 0) connect entries_ex[3].bits.deps_ld[_T_4949], UInt<1>(0h0) node _T_4950 = bits(issue_id_3, 2, 0) connect entries_ex[4].bits.deps_ld[_T_4950], UInt<1>(0h0) node _T_4951 = bits(issue_id_3, 2, 0) connect entries_ex[5].bits.deps_ld[_T_4951], UInt<1>(0h0) node _T_4952 = bits(issue_id_3, 2, 0) connect entries_ex[6].bits.deps_ld[_T_4952], UInt<1>(0h0) node _T_4953 = bits(issue_id_3, 2, 0) connect entries_ex[7].bits.deps_ld[_T_4953], UInt<1>(0h0) node _T_4954 = bits(issue_id_3, 2, 0) connect entries_ex[8].bits.deps_ld[_T_4954], UInt<1>(0h0) node _T_4955 = bits(issue_id_3, 2, 0) connect entries_ex[9].bits.deps_ld[_T_4955], UInt<1>(0h0) node _T_4956 = bits(issue_id_3, 2, 0) connect entries_ex[10].bits.deps_ld[_T_4956], UInt<1>(0h0) node _T_4957 = bits(issue_id_3, 2, 0) connect entries_ex[11].bits.deps_ld[_T_4957], UInt<1>(0h0) node _T_4958 = bits(issue_id_3, 2, 0) connect entries_ex[12].bits.deps_ld[_T_4958], UInt<1>(0h0) node _T_4959 = bits(issue_id_3, 2, 0) connect entries_ex[13].bits.deps_ld[_T_4959], UInt<1>(0h0) node _T_4960 = bits(issue_id_3, 2, 0) connect entries_ex[14].bits.deps_ld[_T_4960], UInt<1>(0h0) node _T_4961 = bits(issue_id_3, 2, 0) connect entries_ex[15].bits.deps_ld[_T_4961], UInt<1>(0h0) node _T_4962 = bits(issue_id_3, 2, 0) connect entries_st[0].bits.deps_ld[_T_4962], UInt<1>(0h0) node _T_4963 = bits(issue_id_3, 2, 0) connect entries_st[1].bits.deps_ld[_T_4963], UInt<1>(0h0) node _T_4964 = bits(issue_id_3, 2, 0) connect entries_st[2].bits.deps_ld[_T_4964], UInt<1>(0h0) node _T_4965 = bits(issue_id_3, 2, 0) connect entries_st[3].bits.deps_ld[_T_4965], UInt<1>(0h0) node _T_4966 = bits(issue_id_3, 2, 0) connect entries_ld[_T_4966].valid, UInt<1>(0h0) node _conv_ld_completed_T = bits(issue_id_3, 2, 0) connect conv_ld_completed, entries_ld[_conv_ld_completed_T].bits.cmd.from_conv_fsm node _matmul_ld_completed_T = bits(issue_id_3, 2, 0) connect matmul_ld_completed, entries_ld[_matmul_ld_completed_T].bits.cmd.from_matmul_fsm node _T_4967 = bits(issue_id_3, 2, 0) node _T_4968 = asUInt(reset) node _T_4969 = eq(_T_4968, UInt<1>(0h0)) when _T_4969 : node _T_4970 = eq(entries_ld[_T_4967].valid, UInt<1>(0h0)) when _T_4970 : printf(clock, UInt<1>(0h1), "Assertion failed\n at ReservationStation.scala:463 assert(entries_ld(issue_id).valid)\n") : printf_6 assert(clock, entries_ld[_T_4967].valid, UInt<1>(0h1), "") : assert_6 else : node _T_4971 = eq(queue_type, UInt<2>(0h1)) when _T_4971 : connect entries_ld[0].bits.deps_ex[issue_id_3], UInt<1>(0h0) connect entries_ld[1].bits.deps_ex[issue_id_3], UInt<1>(0h0) connect entries_ld[2].bits.deps_ex[issue_id_3], UInt<1>(0h0) connect entries_ld[3].bits.deps_ex[issue_id_3], UInt<1>(0h0) connect entries_ld[4].bits.deps_ex[issue_id_3], UInt<1>(0h0) connect entries_ld[5].bits.deps_ex[issue_id_3], UInt<1>(0h0) connect entries_ld[6].bits.deps_ex[issue_id_3], UInt<1>(0h0) connect entries_ld[7].bits.deps_ex[issue_id_3], UInt<1>(0h0) connect entries_ex[0].bits.deps_ex[issue_id_3], UInt<1>(0h0) connect entries_ex[1].bits.deps_ex[issue_id_3], UInt<1>(0h0) connect entries_ex[2].bits.deps_ex[issue_id_3], UInt<1>(0h0) connect entries_ex[3].bits.deps_ex[issue_id_3], UInt<1>(0h0) connect entries_ex[4].bits.deps_ex[issue_id_3], UInt<1>(0h0) connect entries_ex[5].bits.deps_ex[issue_id_3], UInt<1>(0h0) connect entries_ex[6].bits.deps_ex[issue_id_3], UInt<1>(0h0) connect entries_ex[7].bits.deps_ex[issue_id_3], UInt<1>(0h0) connect entries_ex[8].bits.deps_ex[issue_id_3], UInt<1>(0h0) connect entries_ex[9].bits.deps_ex[issue_id_3], UInt<1>(0h0) connect entries_ex[10].bits.deps_ex[issue_id_3], UInt<1>(0h0) connect entries_ex[11].bits.deps_ex[issue_id_3], UInt<1>(0h0) connect entries_ex[12].bits.deps_ex[issue_id_3], UInt<1>(0h0) connect entries_ex[13].bits.deps_ex[issue_id_3], UInt<1>(0h0) connect entries_ex[14].bits.deps_ex[issue_id_3], UInt<1>(0h0) connect entries_ex[15].bits.deps_ex[issue_id_3], UInt<1>(0h0) connect entries_st[0].bits.deps_ex[issue_id_3], UInt<1>(0h0) connect entries_st[1].bits.deps_ex[issue_id_3], UInt<1>(0h0) connect entries_st[2].bits.deps_ex[issue_id_3], UInt<1>(0h0) connect entries_st[3].bits.deps_ex[issue_id_3], UInt<1>(0h0) connect entries_ex[issue_id_3].valid, UInt<1>(0h0) connect conv_ex_completed, entries_ex[issue_id_3].bits.cmd.from_conv_fsm connect matmul_ex_completed, entries_ex[issue_id_3].bits.cmd.from_matmul_fsm node _T_4972 = asUInt(reset) node _T_4973 = eq(_T_4972, UInt<1>(0h0)) when _T_4973 : node _T_4974 = eq(entries_ex[issue_id_3].valid, UInt<1>(0h0)) when _T_4974 : printf(clock, UInt<1>(0h1), "Assertion failed\n at ReservationStation.scala:471 assert(entries_ex(issue_id).valid)\n") : printf_7 assert(clock, entries_ex[issue_id_3].valid, UInt<1>(0h1), "") : assert_7 else : node _T_4975 = eq(queue_type, UInt<2>(0h2)) when _T_4975 : node _T_4976 = bits(issue_id_3, 1, 0) connect entries_ld[0].bits.deps_st[_T_4976], UInt<1>(0h0) node _T_4977 = bits(issue_id_3, 1, 0) connect entries_ld[1].bits.deps_st[_T_4977], UInt<1>(0h0) node _T_4978 = bits(issue_id_3, 1, 0) connect entries_ld[2].bits.deps_st[_T_4978], UInt<1>(0h0) node _T_4979 = bits(issue_id_3, 1, 0) connect entries_ld[3].bits.deps_st[_T_4979], UInt<1>(0h0) node _T_4980 = bits(issue_id_3, 1, 0) connect entries_ld[4].bits.deps_st[_T_4980], UInt<1>(0h0) node _T_4981 = bits(issue_id_3, 1, 0) connect entries_ld[5].bits.deps_st[_T_4981], UInt<1>(0h0) node _T_4982 = bits(issue_id_3, 1, 0) connect entries_ld[6].bits.deps_st[_T_4982], UInt<1>(0h0) node _T_4983 = bits(issue_id_3, 1, 0) connect entries_ld[7].bits.deps_st[_T_4983], UInt<1>(0h0) node _T_4984 = bits(issue_id_3, 1, 0) connect entries_ex[0].bits.deps_st[_T_4984], UInt<1>(0h0) node _T_4985 = bits(issue_id_3, 1, 0) connect entries_ex[1].bits.deps_st[_T_4985], UInt<1>(0h0) node _T_4986 = bits(issue_id_3, 1, 0) connect entries_ex[2].bits.deps_st[_T_4986], UInt<1>(0h0) node _T_4987 = bits(issue_id_3, 1, 0) connect entries_ex[3].bits.deps_st[_T_4987], UInt<1>(0h0) node _T_4988 = bits(issue_id_3, 1, 0) connect entries_ex[4].bits.deps_st[_T_4988], UInt<1>(0h0) node _T_4989 = bits(issue_id_3, 1, 0) connect entries_ex[5].bits.deps_st[_T_4989], UInt<1>(0h0) node _T_4990 = bits(issue_id_3, 1, 0) connect entries_ex[6].bits.deps_st[_T_4990], UInt<1>(0h0) node _T_4991 = bits(issue_id_3, 1, 0) connect entries_ex[7].bits.deps_st[_T_4991], UInt<1>(0h0) node _T_4992 = bits(issue_id_3, 1, 0) connect entries_ex[8].bits.deps_st[_T_4992], UInt<1>(0h0) node _T_4993 = bits(issue_id_3, 1, 0) connect entries_ex[9].bits.deps_st[_T_4993], UInt<1>(0h0) node _T_4994 = bits(issue_id_3, 1, 0) connect entries_ex[10].bits.deps_st[_T_4994], UInt<1>(0h0) node _T_4995 = bits(issue_id_3, 1, 0) connect entries_ex[11].bits.deps_st[_T_4995], UInt<1>(0h0) node _T_4996 = bits(issue_id_3, 1, 0) connect entries_ex[12].bits.deps_st[_T_4996], UInt<1>(0h0) node _T_4997 = bits(issue_id_3, 1, 0) connect entries_ex[13].bits.deps_st[_T_4997], UInt<1>(0h0) node _T_4998 = bits(issue_id_3, 1, 0) connect entries_ex[14].bits.deps_st[_T_4998], UInt<1>(0h0) node _T_4999 = bits(issue_id_3, 1, 0) connect entries_ex[15].bits.deps_st[_T_4999], UInt<1>(0h0) node _T_5000 = bits(issue_id_3, 1, 0) connect entries_st[0].bits.deps_st[_T_5000], UInt<1>(0h0) node _T_5001 = bits(issue_id_3, 1, 0) connect entries_st[1].bits.deps_st[_T_5001], UInt<1>(0h0) node _T_5002 = bits(issue_id_3, 1, 0) connect entries_st[2].bits.deps_st[_T_5002], UInt<1>(0h0) node _T_5003 = bits(issue_id_3, 1, 0) connect entries_st[3].bits.deps_st[_T_5003], UInt<1>(0h0) node _T_5004 = bits(issue_id_3, 1, 0) connect entries_st[_T_5004].valid, UInt<1>(0h0) node _conv_st_completed_T = bits(issue_id_3, 1, 0) connect conv_st_completed, entries_st[_conv_st_completed_T].bits.cmd.from_conv_fsm node _matmul_st_completed_T = bits(issue_id_3, 1, 0) connect matmul_st_completed, entries_st[_matmul_st_completed_T].bits.cmd.from_matmul_fsm node _T_5005 = bits(issue_id_3, 1, 0) node _T_5006 = asUInt(reset) node _T_5007 = eq(_T_5006, UInt<1>(0h0)) when _T_5007 : node _T_5008 = eq(entries_st[_T_5005].valid, UInt<1>(0h0)) when _T_5008 : printf(clock, UInt<1>(0h1), "Assertion failed\n at ReservationStation.scala:479 assert(entries_st(issue_id).valid)\n") : printf_8 assert(clock, entries_st[_T_5005].valid, UInt<1>(0h1), "") : assert_8 else : node _T_5009 = neq(queue_type, UInt<2>(0h3)) node _T_5010 = asUInt(reset) node _T_5011 = eq(_T_5010, UInt<1>(0h0)) when _T_5011 : node _T_5012 = eq(_T_5009, UInt<1>(0h0)) when _T_5012 : printf(clock, UInt<1>(0h1), "Assertion failed\n at ReservationStation.scala:481 assert(queue_type =/= 3.U)\n") : printf_9 assert(clock, _T_5009, UInt<1>(0h1), "") : assert_9 connect entries_ld[0].bits.opb.valid, UInt<1>(0h0) invalidate entries_ld[0].bits.opb.bits.wraps_around invalidate entries_ld[0].bits.opb.bits.end.data invalidate entries_ld[0].bits.opb.bits.end.garbage_bit invalidate entries_ld[0].bits.opb.bits.end.garbage invalidate entries_ld[0].bits.opb.bits.end.norm_cmd invalidate entries_ld[0].bits.opb.bits.end.read_full_acc_row invalidate entries_ld[0].bits.opb.bits.end.accumulate invalidate entries_ld[0].bits.opb.bits.end.is_acc_addr invalidate entries_ld[0].bits.opb.bits.start.data invalidate entries_ld[0].bits.opb.bits.start.garbage_bit invalidate entries_ld[0].bits.opb.bits.start.garbage invalidate entries_ld[0].bits.opb.bits.start.norm_cmd invalidate entries_ld[0].bits.opb.bits.start.read_full_acc_row invalidate entries_ld[0].bits.opb.bits.start.accumulate invalidate entries_ld[0].bits.opb.bits.start.is_acc_addr connect entries_ld[1].bits.opb.valid, UInt<1>(0h0) invalidate entries_ld[1].bits.opb.bits.wraps_around invalidate entries_ld[1].bits.opb.bits.end.data invalidate entries_ld[1].bits.opb.bits.end.garbage_bit invalidate entries_ld[1].bits.opb.bits.end.garbage invalidate entries_ld[1].bits.opb.bits.end.norm_cmd invalidate entries_ld[1].bits.opb.bits.end.read_full_acc_row invalidate entries_ld[1].bits.opb.bits.end.accumulate invalidate entries_ld[1].bits.opb.bits.end.is_acc_addr invalidate entries_ld[1].bits.opb.bits.start.data invalidate entries_ld[1].bits.opb.bits.start.garbage_bit invalidate entries_ld[1].bits.opb.bits.start.garbage invalidate entries_ld[1].bits.opb.bits.start.norm_cmd invalidate entries_ld[1].bits.opb.bits.start.read_full_acc_row invalidate entries_ld[1].bits.opb.bits.start.accumulate invalidate entries_ld[1].bits.opb.bits.start.is_acc_addr connect entries_ld[2].bits.opb.valid, UInt<1>(0h0) invalidate entries_ld[2].bits.opb.bits.wraps_around invalidate entries_ld[2].bits.opb.bits.end.data invalidate entries_ld[2].bits.opb.bits.end.garbage_bit invalidate entries_ld[2].bits.opb.bits.end.garbage invalidate entries_ld[2].bits.opb.bits.end.norm_cmd invalidate entries_ld[2].bits.opb.bits.end.read_full_acc_row invalidate entries_ld[2].bits.opb.bits.end.accumulate invalidate entries_ld[2].bits.opb.bits.end.is_acc_addr invalidate entries_ld[2].bits.opb.bits.start.data invalidate entries_ld[2].bits.opb.bits.start.garbage_bit invalidate entries_ld[2].bits.opb.bits.start.garbage invalidate entries_ld[2].bits.opb.bits.start.norm_cmd invalidate entries_ld[2].bits.opb.bits.start.read_full_acc_row invalidate entries_ld[2].bits.opb.bits.start.accumulate invalidate entries_ld[2].bits.opb.bits.start.is_acc_addr connect entries_ld[3].bits.opb.valid, UInt<1>(0h0) invalidate entries_ld[3].bits.opb.bits.wraps_around invalidate entries_ld[3].bits.opb.bits.end.data invalidate entries_ld[3].bits.opb.bits.end.garbage_bit invalidate entries_ld[3].bits.opb.bits.end.garbage invalidate entries_ld[3].bits.opb.bits.end.norm_cmd invalidate entries_ld[3].bits.opb.bits.end.read_full_acc_row invalidate entries_ld[3].bits.opb.bits.end.accumulate invalidate entries_ld[3].bits.opb.bits.end.is_acc_addr invalidate entries_ld[3].bits.opb.bits.start.data invalidate entries_ld[3].bits.opb.bits.start.garbage_bit invalidate entries_ld[3].bits.opb.bits.start.garbage invalidate entries_ld[3].bits.opb.bits.start.norm_cmd invalidate entries_ld[3].bits.opb.bits.start.read_full_acc_row invalidate entries_ld[3].bits.opb.bits.start.accumulate invalidate entries_ld[3].bits.opb.bits.start.is_acc_addr connect entries_ld[4].bits.opb.valid, UInt<1>(0h0) invalidate entries_ld[4].bits.opb.bits.wraps_around invalidate entries_ld[4].bits.opb.bits.end.data invalidate entries_ld[4].bits.opb.bits.end.garbage_bit invalidate entries_ld[4].bits.opb.bits.end.garbage invalidate entries_ld[4].bits.opb.bits.end.norm_cmd invalidate entries_ld[4].bits.opb.bits.end.read_full_acc_row invalidate entries_ld[4].bits.opb.bits.end.accumulate invalidate entries_ld[4].bits.opb.bits.end.is_acc_addr invalidate entries_ld[4].bits.opb.bits.start.data invalidate entries_ld[4].bits.opb.bits.start.garbage_bit invalidate entries_ld[4].bits.opb.bits.start.garbage invalidate entries_ld[4].bits.opb.bits.start.norm_cmd invalidate entries_ld[4].bits.opb.bits.start.read_full_acc_row invalidate entries_ld[4].bits.opb.bits.start.accumulate invalidate entries_ld[4].bits.opb.bits.start.is_acc_addr connect entries_ld[5].bits.opb.valid, UInt<1>(0h0) invalidate entries_ld[5].bits.opb.bits.wraps_around invalidate entries_ld[5].bits.opb.bits.end.data invalidate entries_ld[5].bits.opb.bits.end.garbage_bit invalidate entries_ld[5].bits.opb.bits.end.garbage invalidate entries_ld[5].bits.opb.bits.end.norm_cmd invalidate entries_ld[5].bits.opb.bits.end.read_full_acc_row invalidate entries_ld[5].bits.opb.bits.end.accumulate invalidate entries_ld[5].bits.opb.bits.end.is_acc_addr invalidate entries_ld[5].bits.opb.bits.start.data invalidate entries_ld[5].bits.opb.bits.start.garbage_bit invalidate entries_ld[5].bits.opb.bits.start.garbage invalidate entries_ld[5].bits.opb.bits.start.norm_cmd invalidate entries_ld[5].bits.opb.bits.start.read_full_acc_row invalidate entries_ld[5].bits.opb.bits.start.accumulate invalidate entries_ld[5].bits.opb.bits.start.is_acc_addr connect entries_ld[6].bits.opb.valid, UInt<1>(0h0) invalidate entries_ld[6].bits.opb.bits.wraps_around invalidate entries_ld[6].bits.opb.bits.end.data invalidate entries_ld[6].bits.opb.bits.end.garbage_bit invalidate entries_ld[6].bits.opb.bits.end.garbage invalidate entries_ld[6].bits.opb.bits.end.norm_cmd invalidate entries_ld[6].bits.opb.bits.end.read_full_acc_row invalidate entries_ld[6].bits.opb.bits.end.accumulate invalidate entries_ld[6].bits.opb.bits.end.is_acc_addr invalidate entries_ld[6].bits.opb.bits.start.data invalidate entries_ld[6].bits.opb.bits.start.garbage_bit invalidate entries_ld[6].bits.opb.bits.start.garbage invalidate entries_ld[6].bits.opb.bits.start.norm_cmd invalidate entries_ld[6].bits.opb.bits.start.read_full_acc_row invalidate entries_ld[6].bits.opb.bits.start.accumulate invalidate entries_ld[6].bits.opb.bits.start.is_acc_addr connect entries_ld[7].bits.opb.valid, UInt<1>(0h0) invalidate entries_ld[7].bits.opb.bits.wraps_around invalidate entries_ld[7].bits.opb.bits.end.data invalidate entries_ld[7].bits.opb.bits.end.garbage_bit invalidate entries_ld[7].bits.opb.bits.end.garbage invalidate entries_ld[7].bits.opb.bits.end.norm_cmd invalidate entries_ld[7].bits.opb.bits.end.read_full_acc_row invalidate entries_ld[7].bits.opb.bits.end.accumulate invalidate entries_ld[7].bits.opb.bits.end.is_acc_addr invalidate entries_ld[7].bits.opb.bits.start.data invalidate entries_ld[7].bits.opb.bits.start.garbage_bit invalidate entries_ld[7].bits.opb.bits.start.garbage invalidate entries_ld[7].bits.opb.bits.start.norm_cmd invalidate entries_ld[7].bits.opb.bits.start.read_full_acc_row invalidate entries_ld[7].bits.opb.bits.start.accumulate invalidate entries_ld[7].bits.opb.bits.start.is_acc_addr connect entries_st[0].bits.opb.valid, UInt<1>(0h0) invalidate entries_st[0].bits.opb.bits.wraps_around invalidate entries_st[0].bits.opb.bits.end.data invalidate entries_st[0].bits.opb.bits.end.garbage_bit invalidate entries_st[0].bits.opb.bits.end.garbage invalidate entries_st[0].bits.opb.bits.end.norm_cmd invalidate entries_st[0].bits.opb.bits.end.read_full_acc_row invalidate entries_st[0].bits.opb.bits.end.accumulate invalidate entries_st[0].bits.opb.bits.end.is_acc_addr invalidate entries_st[0].bits.opb.bits.start.data invalidate entries_st[0].bits.opb.bits.start.garbage_bit invalidate entries_st[0].bits.opb.bits.start.garbage invalidate entries_st[0].bits.opb.bits.start.norm_cmd invalidate entries_st[0].bits.opb.bits.start.read_full_acc_row invalidate entries_st[0].bits.opb.bits.start.accumulate invalidate entries_st[0].bits.opb.bits.start.is_acc_addr connect entries_st[1].bits.opb.valid, UInt<1>(0h0) invalidate entries_st[1].bits.opb.bits.wraps_around invalidate entries_st[1].bits.opb.bits.end.data invalidate entries_st[1].bits.opb.bits.end.garbage_bit invalidate entries_st[1].bits.opb.bits.end.garbage invalidate entries_st[1].bits.opb.bits.end.norm_cmd invalidate entries_st[1].bits.opb.bits.end.read_full_acc_row invalidate entries_st[1].bits.opb.bits.end.accumulate invalidate entries_st[1].bits.opb.bits.end.is_acc_addr invalidate entries_st[1].bits.opb.bits.start.data invalidate entries_st[1].bits.opb.bits.start.garbage_bit invalidate entries_st[1].bits.opb.bits.start.garbage invalidate entries_st[1].bits.opb.bits.start.norm_cmd invalidate entries_st[1].bits.opb.bits.start.read_full_acc_row invalidate entries_st[1].bits.opb.bits.start.accumulate invalidate entries_st[1].bits.opb.bits.start.is_acc_addr connect entries_st[2].bits.opb.valid, UInt<1>(0h0) invalidate entries_st[2].bits.opb.bits.wraps_around invalidate entries_st[2].bits.opb.bits.end.data invalidate entries_st[2].bits.opb.bits.end.garbage_bit invalidate entries_st[2].bits.opb.bits.end.garbage invalidate entries_st[2].bits.opb.bits.end.norm_cmd invalidate entries_st[2].bits.opb.bits.end.read_full_acc_row invalidate entries_st[2].bits.opb.bits.end.accumulate invalidate entries_st[2].bits.opb.bits.end.is_acc_addr invalidate entries_st[2].bits.opb.bits.start.data invalidate entries_st[2].bits.opb.bits.start.garbage_bit invalidate entries_st[2].bits.opb.bits.start.garbage invalidate entries_st[2].bits.opb.bits.start.norm_cmd invalidate entries_st[2].bits.opb.bits.start.read_full_acc_row invalidate entries_st[2].bits.opb.bits.start.accumulate invalidate entries_st[2].bits.opb.bits.start.is_acc_addr connect entries_st[3].bits.opb.valid, UInt<1>(0h0) invalidate entries_st[3].bits.opb.bits.wraps_around invalidate entries_st[3].bits.opb.bits.end.data invalidate entries_st[3].bits.opb.bits.end.garbage_bit invalidate entries_st[3].bits.opb.bits.end.garbage invalidate entries_st[3].bits.opb.bits.end.norm_cmd invalidate entries_st[3].bits.opb.bits.end.read_full_acc_row invalidate entries_st[3].bits.opb.bits.end.accumulate invalidate entries_st[3].bits.opb.bits.end.is_acc_addr invalidate entries_st[3].bits.opb.bits.start.data invalidate entries_st[3].bits.opb.bits.start.garbage_bit invalidate entries_st[3].bits.opb.bits.start.garbage invalidate entries_st[3].bits.opb.bits.start.norm_cmd invalidate entries_st[3].bits.opb.bits.start.read_full_acc_row invalidate entries_st[3].bits.opb.bits.start.accumulate invalidate entries_st[3].bits.opb.bits.start.is_acc_addr node _utilization_ld_q_unissued_T = eq(entries_ld[0].bits.issued, UInt<1>(0h0)) node _utilization_ld_q_unissued_T_1 = and(entries_ld[0].valid, _utilization_ld_q_unissued_T) node _utilization_ld_q_unissued_T_2 = eq(entries_ld[0].bits.q, UInt<2>(0h0)) node _utilization_ld_q_unissued_T_3 = and(_utilization_ld_q_unissued_T_1, _utilization_ld_q_unissued_T_2) node _utilization_ld_q_unissued_T_4 = eq(entries_ld[1].bits.issued, UInt<1>(0h0)) node _utilization_ld_q_unissued_T_5 = and(entries_ld[1].valid, _utilization_ld_q_unissued_T_4) node _utilization_ld_q_unissued_T_6 = eq(entries_ld[1].bits.q, UInt<2>(0h0)) node _utilization_ld_q_unissued_T_7 = and(_utilization_ld_q_unissued_T_5, _utilization_ld_q_unissued_T_6) node _utilization_ld_q_unissued_T_8 = eq(entries_ld[2].bits.issued, UInt<1>(0h0)) node _utilization_ld_q_unissued_T_9 = and(entries_ld[2].valid, _utilization_ld_q_unissued_T_8) node _utilization_ld_q_unissued_T_10 = eq(entries_ld[2].bits.q, UInt<2>(0h0)) node _utilization_ld_q_unissued_T_11 = and(_utilization_ld_q_unissued_T_9, _utilization_ld_q_unissued_T_10) node _utilization_ld_q_unissued_T_12 = eq(entries_ld[3].bits.issued, UInt<1>(0h0)) node _utilization_ld_q_unissued_T_13 = and(entries_ld[3].valid, _utilization_ld_q_unissued_T_12) node _utilization_ld_q_unissued_T_14 = eq(entries_ld[3].bits.q, UInt<2>(0h0)) node _utilization_ld_q_unissued_T_15 = and(_utilization_ld_q_unissued_T_13, _utilization_ld_q_unissued_T_14) node _utilization_ld_q_unissued_T_16 = eq(entries_ld[4].bits.issued, UInt<1>(0h0)) node _utilization_ld_q_unissued_T_17 = and(entries_ld[4].valid, _utilization_ld_q_unissued_T_16) node _utilization_ld_q_unissued_T_18 = eq(entries_ld[4].bits.q, UInt<2>(0h0)) node _utilization_ld_q_unissued_T_19 = and(_utilization_ld_q_unissued_T_17, _utilization_ld_q_unissued_T_18) node _utilization_ld_q_unissued_T_20 = eq(entries_ld[5].bits.issued, UInt<1>(0h0)) node _utilization_ld_q_unissued_T_21 = and(entries_ld[5].valid, _utilization_ld_q_unissued_T_20) node _utilization_ld_q_unissued_T_22 = eq(entries_ld[5].bits.q, UInt<2>(0h0)) node _utilization_ld_q_unissued_T_23 = and(_utilization_ld_q_unissued_T_21, _utilization_ld_q_unissued_T_22) node _utilization_ld_q_unissued_T_24 = eq(entries_ld[6].bits.issued, UInt<1>(0h0)) node _utilization_ld_q_unissued_T_25 = and(entries_ld[6].valid, _utilization_ld_q_unissued_T_24) node _utilization_ld_q_unissued_T_26 = eq(entries_ld[6].bits.q, UInt<2>(0h0)) node _utilization_ld_q_unissued_T_27 = and(_utilization_ld_q_unissued_T_25, _utilization_ld_q_unissued_T_26) node _utilization_ld_q_unissued_T_28 = eq(entries_ld[7].bits.issued, UInt<1>(0h0)) node _utilization_ld_q_unissued_T_29 = and(entries_ld[7].valid, _utilization_ld_q_unissued_T_28) node _utilization_ld_q_unissued_T_30 = eq(entries_ld[7].bits.q, UInt<2>(0h0)) node _utilization_ld_q_unissued_T_31 = and(_utilization_ld_q_unissued_T_29, _utilization_ld_q_unissued_T_30) node _utilization_ld_q_unissued_T_32 = eq(entries_ex[0].bits.issued, UInt<1>(0h0)) node _utilization_ld_q_unissued_T_33 = and(entries_ex[0].valid, _utilization_ld_q_unissued_T_32) node _utilization_ld_q_unissued_T_34 = eq(entries_ex[0].bits.q, UInt<2>(0h0)) node _utilization_ld_q_unissued_T_35 = and(_utilization_ld_q_unissued_T_33, _utilization_ld_q_unissued_T_34) node _utilization_ld_q_unissued_T_36 = eq(entries_ex[1].bits.issued, UInt<1>(0h0)) node _utilization_ld_q_unissued_T_37 = and(entries_ex[1].valid, _utilization_ld_q_unissued_T_36) node _utilization_ld_q_unissued_T_38 = eq(entries_ex[1].bits.q, UInt<2>(0h0)) node _utilization_ld_q_unissued_T_39 = and(_utilization_ld_q_unissued_T_37, _utilization_ld_q_unissued_T_38) node _utilization_ld_q_unissued_T_40 = eq(entries_ex[2].bits.issued, UInt<1>(0h0)) node _utilization_ld_q_unissued_T_41 = and(entries_ex[2].valid, _utilization_ld_q_unissued_T_40) node _utilization_ld_q_unissued_T_42 = eq(entries_ex[2].bits.q, UInt<2>(0h0)) node _utilization_ld_q_unissued_T_43 = and(_utilization_ld_q_unissued_T_41, _utilization_ld_q_unissued_T_42) node _utilization_ld_q_unissued_T_44 = eq(entries_ex[3].bits.issued, UInt<1>(0h0)) node _utilization_ld_q_unissued_T_45 = and(entries_ex[3].valid, _utilization_ld_q_unissued_T_44) node _utilization_ld_q_unissued_T_46 = eq(entries_ex[3].bits.q, UInt<2>(0h0)) node _utilization_ld_q_unissued_T_47 = and(_utilization_ld_q_unissued_T_45, _utilization_ld_q_unissued_T_46) node _utilization_ld_q_unissued_T_48 = eq(entries_ex[4].bits.issued, UInt<1>(0h0)) node _utilization_ld_q_unissued_T_49 = and(entries_ex[4].valid, _utilization_ld_q_unissued_T_48) node _utilization_ld_q_unissued_T_50 = eq(entries_ex[4].bits.q, UInt<2>(0h0)) node _utilization_ld_q_unissued_T_51 = and(_utilization_ld_q_unissued_T_49, _utilization_ld_q_unissued_T_50) node _utilization_ld_q_unissued_T_52 = eq(entries_ex[5].bits.issued, UInt<1>(0h0)) node _utilization_ld_q_unissued_T_53 = and(entries_ex[5].valid, _utilization_ld_q_unissued_T_52) node _utilization_ld_q_unissued_T_54 = eq(entries_ex[5].bits.q, UInt<2>(0h0)) node _utilization_ld_q_unissued_T_55 = and(_utilization_ld_q_unissued_T_53, _utilization_ld_q_unissued_T_54) node _utilization_ld_q_unissued_T_56 = eq(entries_ex[6].bits.issued, UInt<1>(0h0)) node _utilization_ld_q_unissued_T_57 = and(entries_ex[6].valid, _utilization_ld_q_unissued_T_56) node _utilization_ld_q_unissued_T_58 = eq(entries_ex[6].bits.q, UInt<2>(0h0)) node _utilization_ld_q_unissued_T_59 = and(_utilization_ld_q_unissued_T_57, _utilization_ld_q_unissued_T_58) node _utilization_ld_q_unissued_T_60 = eq(entries_ex[7].bits.issued, UInt<1>(0h0)) node _utilization_ld_q_unissued_T_61 = and(entries_ex[7].valid, _utilization_ld_q_unissued_T_60) node _utilization_ld_q_unissued_T_62 = eq(entries_ex[7].bits.q, UInt<2>(0h0)) node _utilization_ld_q_unissued_T_63 = and(_utilization_ld_q_unissued_T_61, _utilization_ld_q_unissued_T_62) node _utilization_ld_q_unissued_T_64 = eq(entries_ex[8].bits.issued, UInt<1>(0h0)) node _utilization_ld_q_unissued_T_65 = and(entries_ex[8].valid, _utilization_ld_q_unissued_T_64) node _utilization_ld_q_unissued_T_66 = eq(entries_ex[8].bits.q, UInt<2>(0h0)) node _utilization_ld_q_unissued_T_67 = and(_utilization_ld_q_unissued_T_65, _utilization_ld_q_unissued_T_66) node _utilization_ld_q_unissued_T_68 = eq(entries_ex[9].bits.issued, UInt<1>(0h0)) node _utilization_ld_q_unissued_T_69 = and(entries_ex[9].valid, _utilization_ld_q_unissued_T_68) node _utilization_ld_q_unissued_T_70 = eq(entries_ex[9].bits.q, UInt<2>(0h0)) node _utilization_ld_q_unissued_T_71 = and(_utilization_ld_q_unissued_T_69, _utilization_ld_q_unissued_T_70) node _utilization_ld_q_unissued_T_72 = eq(entries_ex[10].bits.issued, UInt<1>(0h0)) node _utilization_ld_q_unissued_T_73 = and(entries_ex[10].valid, _utilization_ld_q_unissued_T_72) node _utilization_ld_q_unissued_T_74 = eq(entries_ex[10].bits.q, UInt<2>(0h0)) node _utilization_ld_q_unissued_T_75 = and(_utilization_ld_q_unissued_T_73, _utilization_ld_q_unissued_T_74) node _utilization_ld_q_unissued_T_76 = eq(entries_ex[11].bits.issued, UInt<1>(0h0)) node _utilization_ld_q_unissued_T_77 = and(entries_ex[11].valid, _utilization_ld_q_unissued_T_76) node _utilization_ld_q_unissued_T_78 = eq(entries_ex[11].bits.q, UInt<2>(0h0)) node _utilization_ld_q_unissued_T_79 = and(_utilization_ld_q_unissued_T_77, _utilization_ld_q_unissued_T_78) node _utilization_ld_q_unissued_T_80 = eq(entries_ex[12].bits.issued, UInt<1>(0h0)) node _utilization_ld_q_unissued_T_81 = and(entries_ex[12].valid, _utilization_ld_q_unissued_T_80) node _utilization_ld_q_unissued_T_82 = eq(entries_ex[12].bits.q, UInt<2>(0h0)) node _utilization_ld_q_unissued_T_83 = and(_utilization_ld_q_unissued_T_81, _utilization_ld_q_unissued_T_82) node _utilization_ld_q_unissued_T_84 = eq(entries_ex[13].bits.issued, UInt<1>(0h0)) node _utilization_ld_q_unissued_T_85 = and(entries_ex[13].valid, _utilization_ld_q_unissued_T_84) node _utilization_ld_q_unissued_T_86 = eq(entries_ex[13].bits.q, UInt<2>(0h0)) node _utilization_ld_q_unissued_T_87 = and(_utilization_ld_q_unissued_T_85, _utilization_ld_q_unissued_T_86) node _utilization_ld_q_unissued_T_88 = eq(entries_ex[14].bits.issued, UInt<1>(0h0)) node _utilization_ld_q_unissued_T_89 = and(entries_ex[14].valid, _utilization_ld_q_unissued_T_88) node _utilization_ld_q_unissued_T_90 = eq(entries_ex[14].bits.q, UInt<2>(0h0)) node _utilization_ld_q_unissued_T_91 = and(_utilization_ld_q_unissued_T_89, _utilization_ld_q_unissued_T_90) node _utilization_ld_q_unissued_T_92 = eq(entries_ex[15].bits.issued, UInt<1>(0h0)) node _utilization_ld_q_unissued_T_93 = and(entries_ex[15].valid, _utilization_ld_q_unissued_T_92) node _utilization_ld_q_unissued_T_94 = eq(entries_ex[15].bits.q, UInt<2>(0h0)) node _utilization_ld_q_unissued_T_95 = and(_utilization_ld_q_unissued_T_93, _utilization_ld_q_unissued_T_94) node _utilization_ld_q_unissued_T_96 = eq(entries_st[0].bits.issued, UInt<1>(0h0)) node _utilization_ld_q_unissued_T_97 = and(entries_st[0].valid, _utilization_ld_q_unissued_T_96) node _utilization_ld_q_unissued_T_98 = eq(entries_st[0].bits.q, UInt<2>(0h0)) node _utilization_ld_q_unissued_T_99 = and(_utilization_ld_q_unissued_T_97, _utilization_ld_q_unissued_T_98) node _utilization_ld_q_unissued_T_100 = eq(entries_st[1].bits.issued, UInt<1>(0h0)) node _utilization_ld_q_unissued_T_101 = and(entries_st[1].valid, _utilization_ld_q_unissued_T_100) node _utilization_ld_q_unissued_T_102 = eq(entries_st[1].bits.q, UInt<2>(0h0)) node _utilization_ld_q_unissued_T_103 = and(_utilization_ld_q_unissued_T_101, _utilization_ld_q_unissued_T_102) node _utilization_ld_q_unissued_T_104 = eq(entries_st[2].bits.issued, UInt<1>(0h0)) node _utilization_ld_q_unissued_T_105 = and(entries_st[2].valid, _utilization_ld_q_unissued_T_104) node _utilization_ld_q_unissued_T_106 = eq(entries_st[2].bits.q, UInt<2>(0h0)) node _utilization_ld_q_unissued_T_107 = and(_utilization_ld_q_unissued_T_105, _utilization_ld_q_unissued_T_106) node _utilization_ld_q_unissued_T_108 = eq(entries_st[3].bits.issued, UInt<1>(0h0)) node _utilization_ld_q_unissued_T_109 = and(entries_st[3].valid, _utilization_ld_q_unissued_T_108) node _utilization_ld_q_unissued_T_110 = eq(entries_st[3].bits.q, UInt<2>(0h0)) node _utilization_ld_q_unissued_T_111 = and(_utilization_ld_q_unissued_T_109, _utilization_ld_q_unissued_T_110) node _utilization_ld_q_unissued_T_112 = add(_utilization_ld_q_unissued_T_7, _utilization_ld_q_unissued_T_11) node _utilization_ld_q_unissued_T_113 = bits(_utilization_ld_q_unissued_T_112, 1, 0) node _utilization_ld_q_unissued_T_114 = add(_utilization_ld_q_unissued_T_3, _utilization_ld_q_unissued_T_113) node _utilization_ld_q_unissued_T_115 = bits(_utilization_ld_q_unissued_T_114, 1, 0) node _utilization_ld_q_unissued_T_116 = add(_utilization_ld_q_unissued_T_15, _utilization_ld_q_unissued_T_19) node _utilization_ld_q_unissued_T_117 = bits(_utilization_ld_q_unissued_T_116, 1, 0) node _utilization_ld_q_unissued_T_118 = add(_utilization_ld_q_unissued_T_23, _utilization_ld_q_unissued_T_27) node _utilization_ld_q_unissued_T_119 = bits(_utilization_ld_q_unissued_T_118, 1, 0) node _utilization_ld_q_unissued_T_120 = add(_utilization_ld_q_unissued_T_117, _utilization_ld_q_unissued_T_119) node _utilization_ld_q_unissued_T_121 = bits(_utilization_ld_q_unissued_T_120, 2, 0) node _utilization_ld_q_unissued_T_122 = add(_utilization_ld_q_unissued_T_115, _utilization_ld_q_unissued_T_121) node _utilization_ld_q_unissued_T_123 = bits(_utilization_ld_q_unissued_T_122, 2, 0) node _utilization_ld_q_unissued_T_124 = add(_utilization_ld_q_unissued_T_35, _utilization_ld_q_unissued_T_39) node _utilization_ld_q_unissued_T_125 = bits(_utilization_ld_q_unissued_T_124, 1, 0) node _utilization_ld_q_unissued_T_126 = add(_utilization_ld_q_unissued_T_31, _utilization_ld_q_unissued_T_125) node _utilization_ld_q_unissued_T_127 = bits(_utilization_ld_q_unissued_T_126, 1, 0) node _utilization_ld_q_unissued_T_128 = add(_utilization_ld_q_unissued_T_43, _utilization_ld_q_unissued_T_47) node _utilization_ld_q_unissued_T_129 = bits(_utilization_ld_q_unissued_T_128, 1, 0) node _utilization_ld_q_unissued_T_130 = add(_utilization_ld_q_unissued_T_51, _utilization_ld_q_unissued_T_55) node _utilization_ld_q_unissued_T_131 = bits(_utilization_ld_q_unissued_T_130, 1, 0) node _utilization_ld_q_unissued_T_132 = add(_utilization_ld_q_unissued_T_129, _utilization_ld_q_unissued_T_131) node _utilization_ld_q_unissued_T_133 = bits(_utilization_ld_q_unissued_T_132, 2, 0) node _utilization_ld_q_unissued_T_134 = add(_utilization_ld_q_unissued_T_127, _utilization_ld_q_unissued_T_133) node _utilization_ld_q_unissued_T_135 = bits(_utilization_ld_q_unissued_T_134, 2, 0) node _utilization_ld_q_unissued_T_136 = add(_utilization_ld_q_unissued_T_123, _utilization_ld_q_unissued_T_135) node _utilization_ld_q_unissued_T_137 = bits(_utilization_ld_q_unissued_T_136, 3, 0) node _utilization_ld_q_unissued_T_138 = add(_utilization_ld_q_unissued_T_63, _utilization_ld_q_unissued_T_67) node _utilization_ld_q_unissued_T_139 = bits(_utilization_ld_q_unissued_T_138, 1, 0) node _utilization_ld_q_unissued_T_140 = add(_utilization_ld_q_unissued_T_59, _utilization_ld_q_unissued_T_139) node _utilization_ld_q_unissued_T_141 = bits(_utilization_ld_q_unissued_T_140, 1, 0) node _utilization_ld_q_unissued_T_142 = add(_utilization_ld_q_unissued_T_71, _utilization_ld_q_unissued_T_75) node _utilization_ld_q_unissued_T_143 = bits(_utilization_ld_q_unissued_T_142, 1, 0) node _utilization_ld_q_unissued_T_144 = add(_utilization_ld_q_unissued_T_79, _utilization_ld_q_unissued_T_83) node _utilization_ld_q_unissued_T_145 = bits(_utilization_ld_q_unissued_T_144, 1, 0) node _utilization_ld_q_unissued_T_146 = add(_utilization_ld_q_unissued_T_143, _utilization_ld_q_unissued_T_145) node _utilization_ld_q_unissued_T_147 = bits(_utilization_ld_q_unissued_T_146, 2, 0) node _utilization_ld_q_unissued_T_148 = add(_utilization_ld_q_unissued_T_141, _utilization_ld_q_unissued_T_147) node _utilization_ld_q_unissued_T_149 = bits(_utilization_ld_q_unissued_T_148, 2, 0) node _utilization_ld_q_unissued_T_150 = add(_utilization_ld_q_unissued_T_91, _utilization_ld_q_unissued_T_95) node _utilization_ld_q_unissued_T_151 = bits(_utilization_ld_q_unissued_T_150, 1, 0) node _utilization_ld_q_unissued_T_152 = add(_utilization_ld_q_unissued_T_87, _utilization_ld_q_unissued_T_151) node _utilization_ld_q_unissued_T_153 = bits(_utilization_ld_q_unissued_T_152, 1, 0) node _utilization_ld_q_unissued_T_154 = add(_utilization_ld_q_unissued_T_99, _utilization_ld_q_unissued_T_103) node _utilization_ld_q_unissued_T_155 = bits(_utilization_ld_q_unissued_T_154, 1, 0) node _utilization_ld_q_unissued_T_156 = add(_utilization_ld_q_unissued_T_107, _utilization_ld_q_unissued_T_111) node _utilization_ld_q_unissued_T_157 = bits(_utilization_ld_q_unissued_T_156, 1, 0) node _utilization_ld_q_unissued_T_158 = add(_utilization_ld_q_unissued_T_155, _utilization_ld_q_unissued_T_157) node _utilization_ld_q_unissued_T_159 = bits(_utilization_ld_q_unissued_T_158, 2, 0) node _utilization_ld_q_unissued_T_160 = add(_utilization_ld_q_unissued_T_153, _utilization_ld_q_unissued_T_159) node _utilization_ld_q_unissued_T_161 = bits(_utilization_ld_q_unissued_T_160, 2, 0) node _utilization_ld_q_unissued_T_162 = add(_utilization_ld_q_unissued_T_149, _utilization_ld_q_unissued_T_161) node _utilization_ld_q_unissued_T_163 = bits(_utilization_ld_q_unissued_T_162, 3, 0) node _utilization_ld_q_unissued_T_164 = add(_utilization_ld_q_unissued_T_137, _utilization_ld_q_unissued_T_163) node utilization_ld_q_unissued = bits(_utilization_ld_q_unissued_T_164, 4, 0) node _utilization_st_q_unissued_T = eq(entries_ld[0].bits.issued, UInt<1>(0h0)) node _utilization_st_q_unissued_T_1 = and(entries_ld[0].valid, _utilization_st_q_unissued_T) node _utilization_st_q_unissued_T_2 = eq(entries_ld[0].bits.q, UInt<2>(0h2)) node _utilization_st_q_unissued_T_3 = and(_utilization_st_q_unissued_T_1, _utilization_st_q_unissued_T_2) node _utilization_st_q_unissued_T_4 = eq(entries_ld[1].bits.issued, UInt<1>(0h0)) node _utilization_st_q_unissued_T_5 = and(entries_ld[1].valid, _utilization_st_q_unissued_T_4) node _utilization_st_q_unissued_T_6 = eq(entries_ld[1].bits.q, UInt<2>(0h2)) node _utilization_st_q_unissued_T_7 = and(_utilization_st_q_unissued_T_5, _utilization_st_q_unissued_T_6) node _utilization_st_q_unissued_T_8 = eq(entries_ld[2].bits.issued, UInt<1>(0h0)) node _utilization_st_q_unissued_T_9 = and(entries_ld[2].valid, _utilization_st_q_unissued_T_8) node _utilization_st_q_unissued_T_10 = eq(entries_ld[2].bits.q, UInt<2>(0h2)) node _utilization_st_q_unissued_T_11 = and(_utilization_st_q_unissued_T_9, _utilization_st_q_unissued_T_10) node _utilization_st_q_unissued_T_12 = eq(entries_ld[3].bits.issued, UInt<1>(0h0)) node _utilization_st_q_unissued_T_13 = and(entries_ld[3].valid, _utilization_st_q_unissued_T_12) node _utilization_st_q_unissued_T_14 = eq(entries_ld[3].bits.q, UInt<2>(0h2)) node _utilization_st_q_unissued_T_15 = and(_utilization_st_q_unissued_T_13, _utilization_st_q_unissued_T_14) node _utilization_st_q_unissued_T_16 = eq(entries_ld[4].bits.issued, UInt<1>(0h0)) node _utilization_st_q_unissued_T_17 = and(entries_ld[4].valid, _utilization_st_q_unissued_T_16) node _utilization_st_q_unissued_T_18 = eq(entries_ld[4].bits.q, UInt<2>(0h2)) node _utilization_st_q_unissued_T_19 = and(_utilization_st_q_unissued_T_17, _utilization_st_q_unissued_T_18) node _utilization_st_q_unissued_T_20 = eq(entries_ld[5].bits.issued, UInt<1>(0h0)) node _utilization_st_q_unissued_T_21 = and(entries_ld[5].valid, _utilization_st_q_unissued_T_20) node _utilization_st_q_unissued_T_22 = eq(entries_ld[5].bits.q, UInt<2>(0h2)) node _utilization_st_q_unissued_T_23 = and(_utilization_st_q_unissued_T_21, _utilization_st_q_unissued_T_22) node _utilization_st_q_unissued_T_24 = eq(entries_ld[6].bits.issued, UInt<1>(0h0)) node _utilization_st_q_unissued_T_25 = and(entries_ld[6].valid, _utilization_st_q_unissued_T_24) node _utilization_st_q_unissued_T_26 = eq(entries_ld[6].bits.q, UInt<2>(0h2)) node _utilization_st_q_unissued_T_27 = and(_utilization_st_q_unissued_T_25, _utilization_st_q_unissued_T_26) node _utilization_st_q_unissued_T_28 = eq(entries_ld[7].bits.issued, UInt<1>(0h0)) node _utilization_st_q_unissued_T_29 = and(entries_ld[7].valid, _utilization_st_q_unissued_T_28) node _utilization_st_q_unissued_T_30 = eq(entries_ld[7].bits.q, UInt<2>(0h2)) node _utilization_st_q_unissued_T_31 = and(_utilization_st_q_unissued_T_29, _utilization_st_q_unissued_T_30) node _utilization_st_q_unissued_T_32 = eq(entries_ex[0].bits.issued, UInt<1>(0h0)) node _utilization_st_q_unissued_T_33 = and(entries_ex[0].valid, _utilization_st_q_unissued_T_32) node _utilization_st_q_unissued_T_34 = eq(entries_ex[0].bits.q, UInt<2>(0h2)) node _utilization_st_q_unissued_T_35 = and(_utilization_st_q_unissued_T_33, _utilization_st_q_unissued_T_34) node _utilization_st_q_unissued_T_36 = eq(entries_ex[1].bits.issued, UInt<1>(0h0)) node _utilization_st_q_unissued_T_37 = and(entries_ex[1].valid, _utilization_st_q_unissued_T_36) node _utilization_st_q_unissued_T_38 = eq(entries_ex[1].bits.q, UInt<2>(0h2)) node _utilization_st_q_unissued_T_39 = and(_utilization_st_q_unissued_T_37, _utilization_st_q_unissued_T_38) node _utilization_st_q_unissued_T_40 = eq(entries_ex[2].bits.issued, UInt<1>(0h0)) node _utilization_st_q_unissued_T_41 = and(entries_ex[2].valid, _utilization_st_q_unissued_T_40) node _utilization_st_q_unissued_T_42 = eq(entries_ex[2].bits.q, UInt<2>(0h2)) node _utilization_st_q_unissued_T_43 = and(_utilization_st_q_unissued_T_41, _utilization_st_q_unissued_T_42) node _utilization_st_q_unissued_T_44 = eq(entries_ex[3].bits.issued, UInt<1>(0h0)) node _utilization_st_q_unissued_T_45 = and(entries_ex[3].valid, _utilization_st_q_unissued_T_44) node _utilization_st_q_unissued_T_46 = eq(entries_ex[3].bits.q, UInt<2>(0h2)) node _utilization_st_q_unissued_T_47 = and(_utilization_st_q_unissued_T_45, _utilization_st_q_unissued_T_46) node _utilization_st_q_unissued_T_48 = eq(entries_ex[4].bits.issued, UInt<1>(0h0)) node _utilization_st_q_unissued_T_49 = and(entries_ex[4].valid, _utilization_st_q_unissued_T_48) node _utilization_st_q_unissued_T_50 = eq(entries_ex[4].bits.q, UInt<2>(0h2)) node _utilization_st_q_unissued_T_51 = and(_utilization_st_q_unissued_T_49, _utilization_st_q_unissued_T_50) node _utilization_st_q_unissued_T_52 = eq(entries_ex[5].bits.issued, UInt<1>(0h0)) node _utilization_st_q_unissued_T_53 = and(entries_ex[5].valid, _utilization_st_q_unissued_T_52) node _utilization_st_q_unissued_T_54 = eq(entries_ex[5].bits.q, UInt<2>(0h2)) node _utilization_st_q_unissued_T_55 = and(_utilization_st_q_unissued_T_53, _utilization_st_q_unissued_T_54) node _utilization_st_q_unissued_T_56 = eq(entries_ex[6].bits.issued, UInt<1>(0h0)) node _utilization_st_q_unissued_T_57 = and(entries_ex[6].valid, _utilization_st_q_unissued_T_56) node _utilization_st_q_unissued_T_58 = eq(entries_ex[6].bits.q, UInt<2>(0h2)) node _utilization_st_q_unissued_T_59 = and(_utilization_st_q_unissued_T_57, _utilization_st_q_unissued_T_58) node _utilization_st_q_unissued_T_60 = eq(entries_ex[7].bits.issued, UInt<1>(0h0)) node _utilization_st_q_unissued_T_61 = and(entries_ex[7].valid, _utilization_st_q_unissued_T_60) node _utilization_st_q_unissued_T_62 = eq(entries_ex[7].bits.q, UInt<2>(0h2)) node _utilization_st_q_unissued_T_63 = and(_utilization_st_q_unissued_T_61, _utilization_st_q_unissued_T_62) node _utilization_st_q_unissued_T_64 = eq(entries_ex[8].bits.issued, UInt<1>(0h0)) node _utilization_st_q_unissued_T_65 = and(entries_ex[8].valid, _utilization_st_q_unissued_T_64) node _utilization_st_q_unissued_T_66 = eq(entries_ex[8].bits.q, UInt<2>(0h2)) node _utilization_st_q_unissued_T_67 = and(_utilization_st_q_unissued_T_65, _utilization_st_q_unissued_T_66) node _utilization_st_q_unissued_T_68 = eq(entries_ex[9].bits.issued, UInt<1>(0h0)) node _utilization_st_q_unissued_T_69 = and(entries_ex[9].valid, _utilization_st_q_unissued_T_68) node _utilization_st_q_unissued_T_70 = eq(entries_ex[9].bits.q, UInt<2>(0h2)) node _utilization_st_q_unissued_T_71 = and(_utilization_st_q_unissued_T_69, _utilization_st_q_unissued_T_70) node _utilization_st_q_unissued_T_72 = eq(entries_ex[10].bits.issued, UInt<1>(0h0)) node _utilization_st_q_unissued_T_73 = and(entries_ex[10].valid, _utilization_st_q_unissued_T_72) node _utilization_st_q_unissued_T_74 = eq(entries_ex[10].bits.q, UInt<2>(0h2)) node _utilization_st_q_unissued_T_75 = and(_utilization_st_q_unissued_T_73, _utilization_st_q_unissued_T_74) node _utilization_st_q_unissued_T_76 = eq(entries_ex[11].bits.issued, UInt<1>(0h0)) node _utilization_st_q_unissued_T_77 = and(entries_ex[11].valid, _utilization_st_q_unissued_T_76) node _utilization_st_q_unissued_T_78 = eq(entries_ex[11].bits.q, UInt<2>(0h2)) node _utilization_st_q_unissued_T_79 = and(_utilization_st_q_unissued_T_77, _utilization_st_q_unissued_T_78) node _utilization_st_q_unissued_T_80 = eq(entries_ex[12].bits.issued, UInt<1>(0h0)) node _utilization_st_q_unissued_T_81 = and(entries_ex[12].valid, _utilization_st_q_unissued_T_80) node _utilization_st_q_unissued_T_82 = eq(entries_ex[12].bits.q, UInt<2>(0h2)) node _utilization_st_q_unissued_T_83 = and(_utilization_st_q_unissued_T_81, _utilization_st_q_unissued_T_82) node _utilization_st_q_unissued_T_84 = eq(entries_ex[13].bits.issued, UInt<1>(0h0)) node _utilization_st_q_unissued_T_85 = and(entries_ex[13].valid, _utilization_st_q_unissued_T_84) node _utilization_st_q_unissued_T_86 = eq(entries_ex[13].bits.q, UInt<2>(0h2)) node _utilization_st_q_unissued_T_87 = and(_utilization_st_q_unissued_T_85, _utilization_st_q_unissued_T_86) node _utilization_st_q_unissued_T_88 = eq(entries_ex[14].bits.issued, UInt<1>(0h0)) node _utilization_st_q_unissued_T_89 = and(entries_ex[14].valid, _utilization_st_q_unissued_T_88) node _utilization_st_q_unissued_T_90 = eq(entries_ex[14].bits.q, UInt<2>(0h2)) node _utilization_st_q_unissued_T_91 = and(_utilization_st_q_unissued_T_89, _utilization_st_q_unissued_T_90) node _utilization_st_q_unissued_T_92 = eq(entries_ex[15].bits.issued, UInt<1>(0h0)) node _utilization_st_q_unissued_T_93 = and(entries_ex[15].valid, _utilization_st_q_unissued_T_92) node _utilization_st_q_unissued_T_94 = eq(entries_ex[15].bits.q, UInt<2>(0h2)) node _utilization_st_q_unissued_T_95 = and(_utilization_st_q_unissued_T_93, _utilization_st_q_unissued_T_94) node _utilization_st_q_unissued_T_96 = eq(entries_st[0].bits.issued, UInt<1>(0h0)) node _utilization_st_q_unissued_T_97 = and(entries_st[0].valid, _utilization_st_q_unissued_T_96) node _utilization_st_q_unissued_T_98 = eq(entries_st[0].bits.q, UInt<2>(0h2)) node _utilization_st_q_unissued_T_99 = and(_utilization_st_q_unissued_T_97, _utilization_st_q_unissued_T_98) node _utilization_st_q_unissued_T_100 = eq(entries_st[1].bits.issued, UInt<1>(0h0)) node _utilization_st_q_unissued_T_101 = and(entries_st[1].valid, _utilization_st_q_unissued_T_100) node _utilization_st_q_unissued_T_102 = eq(entries_st[1].bits.q, UInt<2>(0h2)) node _utilization_st_q_unissued_T_103 = and(_utilization_st_q_unissued_T_101, _utilization_st_q_unissued_T_102) node _utilization_st_q_unissued_T_104 = eq(entries_st[2].bits.issued, UInt<1>(0h0)) node _utilization_st_q_unissued_T_105 = and(entries_st[2].valid, _utilization_st_q_unissued_T_104) node _utilization_st_q_unissued_T_106 = eq(entries_st[2].bits.q, UInt<2>(0h2)) node _utilization_st_q_unissued_T_107 = and(_utilization_st_q_unissued_T_105, _utilization_st_q_unissued_T_106) node _utilization_st_q_unissued_T_108 = eq(entries_st[3].bits.issued, UInt<1>(0h0)) node _utilization_st_q_unissued_T_109 = and(entries_st[3].valid, _utilization_st_q_unissued_T_108) node _utilization_st_q_unissued_T_110 = eq(entries_st[3].bits.q, UInt<2>(0h2)) node _utilization_st_q_unissued_T_111 = and(_utilization_st_q_unissued_T_109, _utilization_st_q_unissued_T_110) node _utilization_st_q_unissued_T_112 = add(_utilization_st_q_unissued_T_7, _utilization_st_q_unissued_T_11) node _utilization_st_q_unissued_T_113 = bits(_utilization_st_q_unissued_T_112, 1, 0) node _utilization_st_q_unissued_T_114 = add(_utilization_st_q_unissued_T_3, _utilization_st_q_unissued_T_113) node _utilization_st_q_unissued_T_115 = bits(_utilization_st_q_unissued_T_114, 1, 0) node _utilization_st_q_unissued_T_116 = add(_utilization_st_q_unissued_T_15, _utilization_st_q_unissued_T_19) node _utilization_st_q_unissued_T_117 = bits(_utilization_st_q_unissued_T_116, 1, 0) node _utilization_st_q_unissued_T_118 = add(_utilization_st_q_unissued_T_23, _utilization_st_q_unissued_T_27) node _utilization_st_q_unissued_T_119 = bits(_utilization_st_q_unissued_T_118, 1, 0) node _utilization_st_q_unissued_T_120 = add(_utilization_st_q_unissued_T_117, _utilization_st_q_unissued_T_119) node _utilization_st_q_unissued_T_121 = bits(_utilization_st_q_unissued_T_120, 2, 0) node _utilization_st_q_unissued_T_122 = add(_utilization_st_q_unissued_T_115, _utilization_st_q_unissued_T_121) node _utilization_st_q_unissued_T_123 = bits(_utilization_st_q_unissued_T_122, 2, 0) node _utilization_st_q_unissued_T_124 = add(_utilization_st_q_unissued_T_35, _utilization_st_q_unissued_T_39) node _utilization_st_q_unissued_T_125 = bits(_utilization_st_q_unissued_T_124, 1, 0) node _utilization_st_q_unissued_T_126 = add(_utilization_st_q_unissued_T_31, _utilization_st_q_unissued_T_125) node _utilization_st_q_unissued_T_127 = bits(_utilization_st_q_unissued_T_126, 1, 0) node _utilization_st_q_unissued_T_128 = add(_utilization_st_q_unissued_T_43, _utilization_st_q_unissued_T_47) node _utilization_st_q_unissued_T_129 = bits(_utilization_st_q_unissued_T_128, 1, 0) node _utilization_st_q_unissued_T_130 = add(_utilization_st_q_unissued_T_51, _utilization_st_q_unissued_T_55) node _utilization_st_q_unissued_T_131 = bits(_utilization_st_q_unissued_T_130, 1, 0) node _utilization_st_q_unissued_T_132 = add(_utilization_st_q_unissued_T_129, _utilization_st_q_unissued_T_131) node _utilization_st_q_unissued_T_133 = bits(_utilization_st_q_unissued_T_132, 2, 0) node _utilization_st_q_unissued_T_134 = add(_utilization_st_q_unissued_T_127, _utilization_st_q_unissued_T_133) node _utilization_st_q_unissued_T_135 = bits(_utilization_st_q_unissued_T_134, 2, 0) node _utilization_st_q_unissued_T_136 = add(_utilization_st_q_unissued_T_123, _utilization_st_q_unissued_T_135) node _utilization_st_q_unissued_T_137 = bits(_utilization_st_q_unissued_T_136, 3, 0) node _utilization_st_q_unissued_T_138 = add(_utilization_st_q_unissued_T_63, _utilization_st_q_unissued_T_67) node _utilization_st_q_unissued_T_139 = bits(_utilization_st_q_unissued_T_138, 1, 0) node _utilization_st_q_unissued_T_140 = add(_utilization_st_q_unissued_T_59, _utilization_st_q_unissued_T_139) node _utilization_st_q_unissued_T_141 = bits(_utilization_st_q_unissued_T_140, 1, 0) node _utilization_st_q_unissued_T_142 = add(_utilization_st_q_unissued_T_71, _utilization_st_q_unissued_T_75) node _utilization_st_q_unissued_T_143 = bits(_utilization_st_q_unissued_T_142, 1, 0) node _utilization_st_q_unissued_T_144 = add(_utilization_st_q_unissued_T_79, _utilization_st_q_unissued_T_83) node _utilization_st_q_unissued_T_145 = bits(_utilization_st_q_unissued_T_144, 1, 0) node _utilization_st_q_unissued_T_146 = add(_utilization_st_q_unissued_T_143, _utilization_st_q_unissued_T_145) node _utilization_st_q_unissued_T_147 = bits(_utilization_st_q_unissued_T_146, 2, 0) node _utilization_st_q_unissued_T_148 = add(_utilization_st_q_unissued_T_141, _utilization_st_q_unissued_T_147) node _utilization_st_q_unissued_T_149 = bits(_utilization_st_q_unissued_T_148, 2, 0) node _utilization_st_q_unissued_T_150 = add(_utilization_st_q_unissued_T_91, _utilization_st_q_unissued_T_95) node _utilization_st_q_unissued_T_151 = bits(_utilization_st_q_unissued_T_150, 1, 0) node _utilization_st_q_unissued_T_152 = add(_utilization_st_q_unissued_T_87, _utilization_st_q_unissued_T_151) node _utilization_st_q_unissued_T_153 = bits(_utilization_st_q_unissued_T_152, 1, 0) node _utilization_st_q_unissued_T_154 = add(_utilization_st_q_unissued_T_99, _utilization_st_q_unissued_T_103) node _utilization_st_q_unissued_T_155 = bits(_utilization_st_q_unissued_T_154, 1, 0) node _utilization_st_q_unissued_T_156 = add(_utilization_st_q_unissued_T_107, _utilization_st_q_unissued_T_111) node _utilization_st_q_unissued_T_157 = bits(_utilization_st_q_unissued_T_156, 1, 0) node _utilization_st_q_unissued_T_158 = add(_utilization_st_q_unissued_T_155, _utilization_st_q_unissued_T_157) node _utilization_st_q_unissued_T_159 = bits(_utilization_st_q_unissued_T_158, 2, 0) node _utilization_st_q_unissued_T_160 = add(_utilization_st_q_unissued_T_153, _utilization_st_q_unissued_T_159) node _utilization_st_q_unissued_T_161 = bits(_utilization_st_q_unissued_T_160, 2, 0) node _utilization_st_q_unissued_T_162 = add(_utilization_st_q_unissued_T_149, _utilization_st_q_unissued_T_161) node _utilization_st_q_unissued_T_163 = bits(_utilization_st_q_unissued_T_162, 3, 0) node _utilization_st_q_unissued_T_164 = add(_utilization_st_q_unissued_T_137, _utilization_st_q_unissued_T_163) node utilization_st_q_unissued = bits(_utilization_st_q_unissued_T_164, 4, 0) node _utilization_ex_q_unissued_T = eq(entries_ld[0].bits.issued, UInt<1>(0h0)) node _utilization_ex_q_unissued_T_1 = and(entries_ld[0].valid, _utilization_ex_q_unissued_T) node _utilization_ex_q_unissued_T_2 = eq(entries_ld[0].bits.q, UInt<2>(0h1)) node _utilization_ex_q_unissued_T_3 = and(_utilization_ex_q_unissued_T_1, _utilization_ex_q_unissued_T_2) node _utilization_ex_q_unissued_T_4 = eq(entries_ld[1].bits.issued, UInt<1>(0h0)) node _utilization_ex_q_unissued_T_5 = and(entries_ld[1].valid, _utilization_ex_q_unissued_T_4) node _utilization_ex_q_unissued_T_6 = eq(entries_ld[1].bits.q, UInt<2>(0h1)) node _utilization_ex_q_unissued_T_7 = and(_utilization_ex_q_unissued_T_5, _utilization_ex_q_unissued_T_6) node _utilization_ex_q_unissued_T_8 = eq(entries_ld[2].bits.issued, UInt<1>(0h0)) node _utilization_ex_q_unissued_T_9 = and(entries_ld[2].valid, _utilization_ex_q_unissued_T_8) node _utilization_ex_q_unissued_T_10 = eq(entries_ld[2].bits.q, UInt<2>(0h1)) node _utilization_ex_q_unissued_T_11 = and(_utilization_ex_q_unissued_T_9, _utilization_ex_q_unissued_T_10) node _utilization_ex_q_unissued_T_12 = eq(entries_ld[3].bits.issued, UInt<1>(0h0)) node _utilization_ex_q_unissued_T_13 = and(entries_ld[3].valid, _utilization_ex_q_unissued_T_12) node _utilization_ex_q_unissued_T_14 = eq(entries_ld[3].bits.q, UInt<2>(0h1)) node _utilization_ex_q_unissued_T_15 = and(_utilization_ex_q_unissued_T_13, _utilization_ex_q_unissued_T_14) node _utilization_ex_q_unissued_T_16 = eq(entries_ld[4].bits.issued, UInt<1>(0h0)) node _utilization_ex_q_unissued_T_17 = and(entries_ld[4].valid, _utilization_ex_q_unissued_T_16) node _utilization_ex_q_unissued_T_18 = eq(entries_ld[4].bits.q, UInt<2>(0h1)) node _utilization_ex_q_unissued_T_19 = and(_utilization_ex_q_unissued_T_17, _utilization_ex_q_unissued_T_18) node _utilization_ex_q_unissued_T_20 = eq(entries_ld[5].bits.issued, UInt<1>(0h0)) node _utilization_ex_q_unissued_T_21 = and(entries_ld[5].valid, _utilization_ex_q_unissued_T_20) node _utilization_ex_q_unissued_T_22 = eq(entries_ld[5].bits.q, UInt<2>(0h1)) node _utilization_ex_q_unissued_T_23 = and(_utilization_ex_q_unissued_T_21, _utilization_ex_q_unissued_T_22) node _utilization_ex_q_unissued_T_24 = eq(entries_ld[6].bits.issued, UInt<1>(0h0)) node _utilization_ex_q_unissued_T_25 = and(entries_ld[6].valid, _utilization_ex_q_unissued_T_24) node _utilization_ex_q_unissued_T_26 = eq(entries_ld[6].bits.q, UInt<2>(0h1)) node _utilization_ex_q_unissued_T_27 = and(_utilization_ex_q_unissued_T_25, _utilization_ex_q_unissued_T_26) node _utilization_ex_q_unissued_T_28 = eq(entries_ld[7].bits.issued, UInt<1>(0h0)) node _utilization_ex_q_unissued_T_29 = and(entries_ld[7].valid, _utilization_ex_q_unissued_T_28) node _utilization_ex_q_unissued_T_30 = eq(entries_ld[7].bits.q, UInt<2>(0h1)) node _utilization_ex_q_unissued_T_31 = and(_utilization_ex_q_unissued_T_29, _utilization_ex_q_unissued_T_30) node _utilization_ex_q_unissued_T_32 = eq(entries_ex[0].bits.issued, UInt<1>(0h0)) node _utilization_ex_q_unissued_T_33 = and(entries_ex[0].valid, _utilization_ex_q_unissued_T_32) node _utilization_ex_q_unissued_T_34 = eq(entries_ex[0].bits.q, UInt<2>(0h1)) node _utilization_ex_q_unissued_T_35 = and(_utilization_ex_q_unissued_T_33, _utilization_ex_q_unissued_T_34) node _utilization_ex_q_unissued_T_36 = eq(entries_ex[1].bits.issued, UInt<1>(0h0)) node _utilization_ex_q_unissued_T_37 = and(entries_ex[1].valid, _utilization_ex_q_unissued_T_36) node _utilization_ex_q_unissued_T_38 = eq(entries_ex[1].bits.q, UInt<2>(0h1)) node _utilization_ex_q_unissued_T_39 = and(_utilization_ex_q_unissued_T_37, _utilization_ex_q_unissued_T_38) node _utilization_ex_q_unissued_T_40 = eq(entries_ex[2].bits.issued, UInt<1>(0h0)) node _utilization_ex_q_unissued_T_41 = and(entries_ex[2].valid, _utilization_ex_q_unissued_T_40) node _utilization_ex_q_unissued_T_42 = eq(entries_ex[2].bits.q, UInt<2>(0h1)) node _utilization_ex_q_unissued_T_43 = and(_utilization_ex_q_unissued_T_41, _utilization_ex_q_unissued_T_42) node _utilization_ex_q_unissued_T_44 = eq(entries_ex[3].bits.issued, UInt<1>(0h0)) node _utilization_ex_q_unissued_T_45 = and(entries_ex[3].valid, _utilization_ex_q_unissued_T_44) node _utilization_ex_q_unissued_T_46 = eq(entries_ex[3].bits.q, UInt<2>(0h1)) node _utilization_ex_q_unissued_T_47 = and(_utilization_ex_q_unissued_T_45, _utilization_ex_q_unissued_T_46) node _utilization_ex_q_unissued_T_48 = eq(entries_ex[4].bits.issued, UInt<1>(0h0)) node _utilization_ex_q_unissued_T_49 = and(entries_ex[4].valid, _utilization_ex_q_unissued_T_48) node _utilization_ex_q_unissued_T_50 = eq(entries_ex[4].bits.q, UInt<2>(0h1)) node _utilization_ex_q_unissued_T_51 = and(_utilization_ex_q_unissued_T_49, _utilization_ex_q_unissued_T_50) node _utilization_ex_q_unissued_T_52 = eq(entries_ex[5].bits.issued, UInt<1>(0h0)) node _utilization_ex_q_unissued_T_53 = and(entries_ex[5].valid, _utilization_ex_q_unissued_T_52) node _utilization_ex_q_unissued_T_54 = eq(entries_ex[5].bits.q, UInt<2>(0h1)) node _utilization_ex_q_unissued_T_55 = and(_utilization_ex_q_unissued_T_53, _utilization_ex_q_unissued_T_54) node _utilization_ex_q_unissued_T_56 = eq(entries_ex[6].bits.issued, UInt<1>(0h0)) node _utilization_ex_q_unissued_T_57 = and(entries_ex[6].valid, _utilization_ex_q_unissued_T_56) node _utilization_ex_q_unissued_T_58 = eq(entries_ex[6].bits.q, UInt<2>(0h1)) node _utilization_ex_q_unissued_T_59 = and(_utilization_ex_q_unissued_T_57, _utilization_ex_q_unissued_T_58) node _utilization_ex_q_unissued_T_60 = eq(entries_ex[7].bits.issued, UInt<1>(0h0)) node _utilization_ex_q_unissued_T_61 = and(entries_ex[7].valid, _utilization_ex_q_unissued_T_60) node _utilization_ex_q_unissued_T_62 = eq(entries_ex[7].bits.q, UInt<2>(0h1)) node _utilization_ex_q_unissued_T_63 = and(_utilization_ex_q_unissued_T_61, _utilization_ex_q_unissued_T_62) node _utilization_ex_q_unissued_T_64 = eq(entries_ex[8].bits.issued, UInt<1>(0h0)) node _utilization_ex_q_unissued_T_65 = and(entries_ex[8].valid, _utilization_ex_q_unissued_T_64) node _utilization_ex_q_unissued_T_66 = eq(entries_ex[8].bits.q, UInt<2>(0h1)) node _utilization_ex_q_unissued_T_67 = and(_utilization_ex_q_unissued_T_65, _utilization_ex_q_unissued_T_66) node _utilization_ex_q_unissued_T_68 = eq(entries_ex[9].bits.issued, UInt<1>(0h0)) node _utilization_ex_q_unissued_T_69 = and(entries_ex[9].valid, _utilization_ex_q_unissued_T_68) node _utilization_ex_q_unissued_T_70 = eq(entries_ex[9].bits.q, UInt<2>(0h1)) node _utilization_ex_q_unissued_T_71 = and(_utilization_ex_q_unissued_T_69, _utilization_ex_q_unissued_T_70) node _utilization_ex_q_unissued_T_72 = eq(entries_ex[10].bits.issued, UInt<1>(0h0)) node _utilization_ex_q_unissued_T_73 = and(entries_ex[10].valid, _utilization_ex_q_unissued_T_72) node _utilization_ex_q_unissued_T_74 = eq(entries_ex[10].bits.q, UInt<2>(0h1)) node _utilization_ex_q_unissued_T_75 = and(_utilization_ex_q_unissued_T_73, _utilization_ex_q_unissued_T_74) node _utilization_ex_q_unissued_T_76 = eq(entries_ex[11].bits.issued, UInt<1>(0h0)) node _utilization_ex_q_unissued_T_77 = and(entries_ex[11].valid, _utilization_ex_q_unissued_T_76) node _utilization_ex_q_unissued_T_78 = eq(entries_ex[11].bits.q, UInt<2>(0h1)) node _utilization_ex_q_unissued_T_79 = and(_utilization_ex_q_unissued_T_77, _utilization_ex_q_unissued_T_78) node _utilization_ex_q_unissued_T_80 = eq(entries_ex[12].bits.issued, UInt<1>(0h0)) node _utilization_ex_q_unissued_T_81 = and(entries_ex[12].valid, _utilization_ex_q_unissued_T_80) node _utilization_ex_q_unissued_T_82 = eq(entries_ex[12].bits.q, UInt<2>(0h1)) node _utilization_ex_q_unissued_T_83 = and(_utilization_ex_q_unissued_T_81, _utilization_ex_q_unissued_T_82) node _utilization_ex_q_unissued_T_84 = eq(entries_ex[13].bits.issued, UInt<1>(0h0)) node _utilization_ex_q_unissued_T_85 = and(entries_ex[13].valid, _utilization_ex_q_unissued_T_84) node _utilization_ex_q_unissued_T_86 = eq(entries_ex[13].bits.q, UInt<2>(0h1)) node _utilization_ex_q_unissued_T_87 = and(_utilization_ex_q_unissued_T_85, _utilization_ex_q_unissued_T_86) node _utilization_ex_q_unissued_T_88 = eq(entries_ex[14].bits.issued, UInt<1>(0h0)) node _utilization_ex_q_unissued_T_89 = and(entries_ex[14].valid, _utilization_ex_q_unissued_T_88) node _utilization_ex_q_unissued_T_90 = eq(entries_ex[14].bits.q, UInt<2>(0h1)) node _utilization_ex_q_unissued_T_91 = and(_utilization_ex_q_unissued_T_89, _utilization_ex_q_unissued_T_90) node _utilization_ex_q_unissued_T_92 = eq(entries_ex[15].bits.issued, UInt<1>(0h0)) node _utilization_ex_q_unissued_T_93 = and(entries_ex[15].valid, _utilization_ex_q_unissued_T_92) node _utilization_ex_q_unissued_T_94 = eq(entries_ex[15].bits.q, UInt<2>(0h1)) node _utilization_ex_q_unissued_T_95 = and(_utilization_ex_q_unissued_T_93, _utilization_ex_q_unissued_T_94) node _utilization_ex_q_unissued_T_96 = eq(entries_st[0].bits.issued, UInt<1>(0h0)) node _utilization_ex_q_unissued_T_97 = and(entries_st[0].valid, _utilization_ex_q_unissued_T_96) node _utilization_ex_q_unissued_T_98 = eq(entries_st[0].bits.q, UInt<2>(0h1)) node _utilization_ex_q_unissued_T_99 = and(_utilization_ex_q_unissued_T_97, _utilization_ex_q_unissued_T_98) node _utilization_ex_q_unissued_T_100 = eq(entries_st[1].bits.issued, UInt<1>(0h0)) node _utilization_ex_q_unissued_T_101 = and(entries_st[1].valid, _utilization_ex_q_unissued_T_100) node _utilization_ex_q_unissued_T_102 = eq(entries_st[1].bits.q, UInt<2>(0h1)) node _utilization_ex_q_unissued_T_103 = and(_utilization_ex_q_unissued_T_101, _utilization_ex_q_unissued_T_102) node _utilization_ex_q_unissued_T_104 = eq(entries_st[2].bits.issued, UInt<1>(0h0)) node _utilization_ex_q_unissued_T_105 = and(entries_st[2].valid, _utilization_ex_q_unissued_T_104) node _utilization_ex_q_unissued_T_106 = eq(entries_st[2].bits.q, UInt<2>(0h1)) node _utilization_ex_q_unissued_T_107 = and(_utilization_ex_q_unissued_T_105, _utilization_ex_q_unissued_T_106) node _utilization_ex_q_unissued_T_108 = eq(entries_st[3].bits.issued, UInt<1>(0h0)) node _utilization_ex_q_unissued_T_109 = and(entries_st[3].valid, _utilization_ex_q_unissued_T_108) node _utilization_ex_q_unissued_T_110 = eq(entries_st[3].bits.q, UInt<2>(0h1)) node _utilization_ex_q_unissued_T_111 = and(_utilization_ex_q_unissued_T_109, _utilization_ex_q_unissued_T_110) node _utilization_ex_q_unissued_T_112 = add(_utilization_ex_q_unissued_T_7, _utilization_ex_q_unissued_T_11) node _utilization_ex_q_unissued_T_113 = bits(_utilization_ex_q_unissued_T_112, 1, 0) node _utilization_ex_q_unissued_T_114 = add(_utilization_ex_q_unissued_T_3, _utilization_ex_q_unissued_T_113) node _utilization_ex_q_unissued_T_115 = bits(_utilization_ex_q_unissued_T_114, 1, 0) node _utilization_ex_q_unissued_T_116 = add(_utilization_ex_q_unissued_T_15, _utilization_ex_q_unissued_T_19) node _utilization_ex_q_unissued_T_117 = bits(_utilization_ex_q_unissued_T_116, 1, 0) node _utilization_ex_q_unissued_T_118 = add(_utilization_ex_q_unissued_T_23, _utilization_ex_q_unissued_T_27) node _utilization_ex_q_unissued_T_119 = bits(_utilization_ex_q_unissued_T_118, 1, 0) node _utilization_ex_q_unissued_T_120 = add(_utilization_ex_q_unissued_T_117, _utilization_ex_q_unissued_T_119) node _utilization_ex_q_unissued_T_121 = bits(_utilization_ex_q_unissued_T_120, 2, 0) node _utilization_ex_q_unissued_T_122 = add(_utilization_ex_q_unissued_T_115, _utilization_ex_q_unissued_T_121) node _utilization_ex_q_unissued_T_123 = bits(_utilization_ex_q_unissued_T_122, 2, 0) node _utilization_ex_q_unissued_T_124 = add(_utilization_ex_q_unissued_T_35, _utilization_ex_q_unissued_T_39) node _utilization_ex_q_unissued_T_125 = bits(_utilization_ex_q_unissued_T_124, 1, 0) node _utilization_ex_q_unissued_T_126 = add(_utilization_ex_q_unissued_T_31, _utilization_ex_q_unissued_T_125) node _utilization_ex_q_unissued_T_127 = bits(_utilization_ex_q_unissued_T_126, 1, 0) node _utilization_ex_q_unissued_T_128 = add(_utilization_ex_q_unissued_T_43, _utilization_ex_q_unissued_T_47) node _utilization_ex_q_unissued_T_129 = bits(_utilization_ex_q_unissued_T_128, 1, 0) node _utilization_ex_q_unissued_T_130 = add(_utilization_ex_q_unissued_T_51, _utilization_ex_q_unissued_T_55) node _utilization_ex_q_unissued_T_131 = bits(_utilization_ex_q_unissued_T_130, 1, 0) node _utilization_ex_q_unissued_T_132 = add(_utilization_ex_q_unissued_T_129, _utilization_ex_q_unissued_T_131) node _utilization_ex_q_unissued_T_133 = bits(_utilization_ex_q_unissued_T_132, 2, 0) node _utilization_ex_q_unissued_T_134 = add(_utilization_ex_q_unissued_T_127, _utilization_ex_q_unissued_T_133) node _utilization_ex_q_unissued_T_135 = bits(_utilization_ex_q_unissued_T_134, 2, 0) node _utilization_ex_q_unissued_T_136 = add(_utilization_ex_q_unissued_T_123, _utilization_ex_q_unissued_T_135) node _utilization_ex_q_unissued_T_137 = bits(_utilization_ex_q_unissued_T_136, 3, 0) node _utilization_ex_q_unissued_T_138 = add(_utilization_ex_q_unissued_T_63, _utilization_ex_q_unissued_T_67) node _utilization_ex_q_unissued_T_139 = bits(_utilization_ex_q_unissued_T_138, 1, 0) node _utilization_ex_q_unissued_T_140 = add(_utilization_ex_q_unissued_T_59, _utilization_ex_q_unissued_T_139) node _utilization_ex_q_unissued_T_141 = bits(_utilization_ex_q_unissued_T_140, 1, 0) node _utilization_ex_q_unissued_T_142 = add(_utilization_ex_q_unissued_T_71, _utilization_ex_q_unissued_T_75) node _utilization_ex_q_unissued_T_143 = bits(_utilization_ex_q_unissued_T_142, 1, 0) node _utilization_ex_q_unissued_T_144 = add(_utilization_ex_q_unissued_T_79, _utilization_ex_q_unissued_T_83) node _utilization_ex_q_unissued_T_145 = bits(_utilization_ex_q_unissued_T_144, 1, 0) node _utilization_ex_q_unissued_T_146 = add(_utilization_ex_q_unissued_T_143, _utilization_ex_q_unissued_T_145) node _utilization_ex_q_unissued_T_147 = bits(_utilization_ex_q_unissued_T_146, 2, 0) node _utilization_ex_q_unissued_T_148 = add(_utilization_ex_q_unissued_T_141, _utilization_ex_q_unissued_T_147) node _utilization_ex_q_unissued_T_149 = bits(_utilization_ex_q_unissued_T_148, 2, 0) node _utilization_ex_q_unissued_T_150 = add(_utilization_ex_q_unissued_T_91, _utilization_ex_q_unissued_T_95) node _utilization_ex_q_unissued_T_151 = bits(_utilization_ex_q_unissued_T_150, 1, 0) node _utilization_ex_q_unissued_T_152 = add(_utilization_ex_q_unissued_T_87, _utilization_ex_q_unissued_T_151) node _utilization_ex_q_unissued_T_153 = bits(_utilization_ex_q_unissued_T_152, 1, 0) node _utilization_ex_q_unissued_T_154 = add(_utilization_ex_q_unissued_T_99, _utilization_ex_q_unissued_T_103) node _utilization_ex_q_unissued_T_155 = bits(_utilization_ex_q_unissued_T_154, 1, 0) node _utilization_ex_q_unissued_T_156 = add(_utilization_ex_q_unissued_T_107, _utilization_ex_q_unissued_T_111) node _utilization_ex_q_unissued_T_157 = bits(_utilization_ex_q_unissued_T_156, 1, 0) node _utilization_ex_q_unissued_T_158 = add(_utilization_ex_q_unissued_T_155, _utilization_ex_q_unissued_T_157) node _utilization_ex_q_unissued_T_159 = bits(_utilization_ex_q_unissued_T_158, 2, 0) node _utilization_ex_q_unissued_T_160 = add(_utilization_ex_q_unissued_T_153, _utilization_ex_q_unissued_T_159) node _utilization_ex_q_unissued_T_161 = bits(_utilization_ex_q_unissued_T_160, 2, 0) node _utilization_ex_q_unissued_T_162 = add(_utilization_ex_q_unissued_T_149, _utilization_ex_q_unissued_T_161) node _utilization_ex_q_unissued_T_163 = bits(_utilization_ex_q_unissued_T_162, 3, 0) node _utilization_ex_q_unissued_T_164 = add(_utilization_ex_q_unissued_T_137, _utilization_ex_q_unissued_T_163) node utilization_ex_q_unissued = bits(_utilization_ex_q_unissued_T_164, 4, 0) node _utilization_ld_q_T = add(entries_ld[0].valid, entries_ld[1].valid) node _utilization_ld_q_T_1 = bits(_utilization_ld_q_T, 1, 0) node _utilization_ld_q_T_2 = add(entries_ld[2].valid, entries_ld[3].valid) node _utilization_ld_q_T_3 = bits(_utilization_ld_q_T_2, 1, 0) node _utilization_ld_q_T_4 = add(_utilization_ld_q_T_1, _utilization_ld_q_T_3) node _utilization_ld_q_T_5 = bits(_utilization_ld_q_T_4, 2, 0) node _utilization_ld_q_T_6 = add(entries_ld[4].valid, entries_ld[5].valid) node _utilization_ld_q_T_7 = bits(_utilization_ld_q_T_6, 1, 0) node _utilization_ld_q_T_8 = add(entries_ld[6].valid, entries_ld[7].valid) node _utilization_ld_q_T_9 = bits(_utilization_ld_q_T_8, 1, 0) node _utilization_ld_q_T_10 = add(_utilization_ld_q_T_7, _utilization_ld_q_T_9) node _utilization_ld_q_T_11 = bits(_utilization_ld_q_T_10, 2, 0) node _utilization_ld_q_T_12 = add(_utilization_ld_q_T_5, _utilization_ld_q_T_11) node utilization_ld_q = bits(_utilization_ld_q_T_12, 3, 0) node _utilization_st_q_T = add(entries_st[0].valid, entries_st[1].valid) node _utilization_st_q_T_1 = bits(_utilization_st_q_T, 1, 0) node _utilization_st_q_T_2 = add(entries_st[2].valid, entries_st[3].valid) node _utilization_st_q_T_3 = bits(_utilization_st_q_T_2, 1, 0) node _utilization_st_q_T_4 = add(_utilization_st_q_T_1, _utilization_st_q_T_3) node utilization_st_q = bits(_utilization_st_q_T_4, 2, 0) node _utilization_ex_q_T = add(entries_ex[0].valid, entries_ex[1].valid) node _utilization_ex_q_T_1 = bits(_utilization_ex_q_T, 1, 0) node _utilization_ex_q_T_2 = add(entries_ex[2].valid, entries_ex[3].valid) node _utilization_ex_q_T_3 = bits(_utilization_ex_q_T_2, 1, 0) node _utilization_ex_q_T_4 = add(_utilization_ex_q_T_1, _utilization_ex_q_T_3) node _utilization_ex_q_T_5 = bits(_utilization_ex_q_T_4, 2, 0) node _utilization_ex_q_T_6 = add(entries_ex[4].valid, entries_ex[5].valid) node _utilization_ex_q_T_7 = bits(_utilization_ex_q_T_6, 1, 0) node _utilization_ex_q_T_8 = add(entries_ex[6].valid, entries_ex[7].valid) node _utilization_ex_q_T_9 = bits(_utilization_ex_q_T_8, 1, 0) node _utilization_ex_q_T_10 = add(_utilization_ex_q_T_7, _utilization_ex_q_T_9) node _utilization_ex_q_T_11 = bits(_utilization_ex_q_T_10, 2, 0) node _utilization_ex_q_T_12 = add(_utilization_ex_q_T_5, _utilization_ex_q_T_11) node _utilization_ex_q_T_13 = bits(_utilization_ex_q_T_12, 3, 0) node _utilization_ex_q_T_14 = add(entries_ex[8].valid, entries_ex[9].valid) node _utilization_ex_q_T_15 = bits(_utilization_ex_q_T_14, 1, 0) node _utilization_ex_q_T_16 = add(entries_ex[10].valid, entries_ex[11].valid) node _utilization_ex_q_T_17 = bits(_utilization_ex_q_T_16, 1, 0) node _utilization_ex_q_T_18 = add(_utilization_ex_q_T_15, _utilization_ex_q_T_17) node _utilization_ex_q_T_19 = bits(_utilization_ex_q_T_18, 2, 0) node _utilization_ex_q_T_20 = add(entries_ex[12].valid, entries_ex[13].valid) node _utilization_ex_q_T_21 = bits(_utilization_ex_q_T_20, 1, 0) node _utilization_ex_q_T_22 = add(entries_ex[14].valid, entries_ex[15].valid) node _utilization_ex_q_T_23 = bits(_utilization_ex_q_T_22, 1, 0) node _utilization_ex_q_T_24 = add(_utilization_ex_q_T_21, _utilization_ex_q_T_23) node _utilization_ex_q_T_25 = bits(_utilization_ex_q_T_24, 2, 0) node _utilization_ex_q_T_26 = add(_utilization_ex_q_T_19, _utilization_ex_q_T_25) node _utilization_ex_q_T_27 = bits(_utilization_ex_q_T_26, 3, 0) node _utilization_ex_q_T_28 = add(_utilization_ex_q_T_13, _utilization_ex_q_T_27) node utilization_ex_q = bits(_utilization_ex_q_T_28, 4, 0) wire valids : UInt<1>[28] connect valids[0], entries_ld[0].valid connect valids[1], entries_ld[1].valid connect valids[2], entries_ld[2].valid connect valids[3], entries_ld[3].valid connect valids[4], entries_ld[4].valid connect valids[5], entries_ld[5].valid connect valids[6], entries_ld[6].valid connect valids[7], entries_ld[7].valid connect valids[8], entries_ex[0].valid connect valids[9], entries_ex[1].valid connect valids[10], entries_ex[2].valid connect valids[11], entries_ex[3].valid connect valids[12], entries_ex[4].valid connect valids[13], entries_ex[5].valid connect valids[14], entries_ex[6].valid connect valids[15], entries_ex[7].valid connect valids[16], entries_ex[8].valid connect valids[17], entries_ex[9].valid connect valids[18], entries_ex[10].valid connect valids[19], entries_ex[11].valid connect valids[20], entries_ex[12].valid connect valids[21], entries_ex[13].valid connect valids[22], entries_ex[14].valid connect valids[23], entries_ex[15].valid connect valids[24], entries_st[0].valid connect valids[25], entries_st[1].valid connect valids[26], entries_st[2].valid connect valids[27], entries_st[3].valid wire functs : UInt<7>[28] connect functs[0], entries_ld[0].bits.cmd.cmd.inst.funct connect functs[1], entries_ld[1].bits.cmd.cmd.inst.funct connect functs[2], entries_ld[2].bits.cmd.cmd.inst.funct connect functs[3], entries_ld[3].bits.cmd.cmd.inst.funct connect functs[4], entries_ld[4].bits.cmd.cmd.inst.funct connect functs[5], entries_ld[5].bits.cmd.cmd.inst.funct connect functs[6], entries_ld[6].bits.cmd.cmd.inst.funct connect functs[7], entries_ld[7].bits.cmd.cmd.inst.funct connect functs[8], entries_ex[0].bits.cmd.cmd.inst.funct connect functs[9], entries_ex[1].bits.cmd.cmd.inst.funct connect functs[10], entries_ex[2].bits.cmd.cmd.inst.funct connect functs[11], entries_ex[3].bits.cmd.cmd.inst.funct connect functs[12], entries_ex[4].bits.cmd.cmd.inst.funct connect functs[13], entries_ex[5].bits.cmd.cmd.inst.funct connect functs[14], entries_ex[6].bits.cmd.cmd.inst.funct connect functs[15], entries_ex[7].bits.cmd.cmd.inst.funct connect functs[16], entries_ex[8].bits.cmd.cmd.inst.funct connect functs[17], entries_ex[9].bits.cmd.cmd.inst.funct connect functs[18], entries_ex[10].bits.cmd.cmd.inst.funct connect functs[19], entries_ex[11].bits.cmd.cmd.inst.funct connect functs[20], entries_ex[12].bits.cmd.cmd.inst.funct connect functs[21], entries_ex[13].bits.cmd.cmd.inst.funct connect functs[22], entries_ex[14].bits.cmd.cmd.inst.funct connect functs[23], entries_ex[15].bits.cmd.cmd.inst.funct connect functs[24], entries_st[0].bits.cmd.cmd.inst.funct connect functs[25], entries_st[1].bits.cmd.cmd.inst.funct connect functs[26], entries_st[2].bits.cmd.cmd.inst.funct connect functs[27], entries_st[3].bits.cmd.cmd.inst.funct wire issueds : UInt<1>[28] connect issueds[0], entries_ld[0].bits.issued connect issueds[1], entries_ld[1].bits.issued connect issueds[2], entries_ld[2].bits.issued connect issueds[3], entries_ld[3].bits.issued connect issueds[4], entries_ld[4].bits.issued connect issueds[5], entries_ld[5].bits.issued connect issueds[6], entries_ld[6].bits.issued connect issueds[7], entries_ld[7].bits.issued connect issueds[8], entries_ex[0].bits.issued connect issueds[9], entries_ex[1].bits.issued connect issueds[10], entries_ex[2].bits.issued connect issueds[11], entries_ex[3].bits.issued connect issueds[12], entries_ex[4].bits.issued connect issueds[13], entries_ex[5].bits.issued connect issueds[14], entries_ex[6].bits.issued connect issueds[15], entries_ex[7].bits.issued connect issueds[16], entries_ex[8].bits.issued connect issueds[17], entries_ex[9].bits.issued connect issueds[18], entries_ex[10].bits.issued connect issueds[19], entries_ex[11].bits.issued connect issueds[20], entries_ex[12].bits.issued connect issueds[21], entries_ex[13].bits.issued connect issueds[22], entries_ex[14].bits.issued connect issueds[23], entries_ex[15].bits.issued connect issueds[24], entries_st[0].bits.issued connect issueds[25], entries_st[1].bits.issued connect issueds[26], entries_st[2].bits.issued connect issueds[27], entries_st[3].bits.issued node packed_deps_lo_lo = cat(entries_ld[0].bits.deps_ld[1], entries_ld[0].bits.deps_ld[0]) node packed_deps_lo_hi = cat(entries_ld[0].bits.deps_ld[3], entries_ld[0].bits.deps_ld[2]) node packed_deps_lo = cat(packed_deps_lo_hi, packed_deps_lo_lo) node packed_deps_hi_lo = cat(entries_ld[0].bits.deps_ld[5], entries_ld[0].bits.deps_ld[4]) node packed_deps_hi_hi = cat(entries_ld[0].bits.deps_ld[7], entries_ld[0].bits.deps_ld[6]) node packed_deps_hi = cat(packed_deps_hi_hi, packed_deps_hi_lo) node _packed_deps_T = cat(packed_deps_hi, packed_deps_lo) node packed_deps_lo_lo_lo = cat(entries_ld[0].bits.deps_ex[1], entries_ld[0].bits.deps_ex[0]) node packed_deps_lo_lo_hi = cat(entries_ld[0].bits.deps_ex[3], entries_ld[0].bits.deps_ex[2]) node packed_deps_lo_lo_1 = cat(packed_deps_lo_lo_hi, packed_deps_lo_lo_lo) node packed_deps_lo_hi_lo = cat(entries_ld[0].bits.deps_ex[5], entries_ld[0].bits.deps_ex[4]) node packed_deps_lo_hi_hi = cat(entries_ld[0].bits.deps_ex[7], entries_ld[0].bits.deps_ex[6]) node packed_deps_lo_hi_1 = cat(packed_deps_lo_hi_hi, packed_deps_lo_hi_lo) node packed_deps_lo_1 = cat(packed_deps_lo_hi_1, packed_deps_lo_lo_1) node packed_deps_hi_lo_lo = cat(entries_ld[0].bits.deps_ex[9], entries_ld[0].bits.deps_ex[8]) node packed_deps_hi_lo_hi = cat(entries_ld[0].bits.deps_ex[11], entries_ld[0].bits.deps_ex[10]) node packed_deps_hi_lo_1 = cat(packed_deps_hi_lo_hi, packed_deps_hi_lo_lo) node packed_deps_hi_hi_lo = cat(entries_ld[0].bits.deps_ex[13], entries_ld[0].bits.deps_ex[12]) node packed_deps_hi_hi_hi = cat(entries_ld[0].bits.deps_ex[15], entries_ld[0].bits.deps_ex[14]) node packed_deps_hi_hi_1 = cat(packed_deps_hi_hi_hi, packed_deps_hi_hi_lo) node packed_deps_hi_1 = cat(packed_deps_hi_hi_1, packed_deps_hi_lo_1) node _packed_deps_T_1 = cat(packed_deps_hi_1, packed_deps_lo_1) node packed_deps_lo_2 = cat(entries_ld[0].bits.deps_st[1], entries_ld[0].bits.deps_st[0]) node packed_deps_hi_2 = cat(entries_ld[0].bits.deps_st[3], entries_ld[0].bits.deps_st[2]) node _packed_deps_T_2 = cat(packed_deps_hi_2, packed_deps_lo_2) node packed_deps_hi_3 = cat(_packed_deps_T, _packed_deps_T_1) node _packed_deps_T_3 = cat(packed_deps_hi_3, _packed_deps_T_2) node packed_deps_lo_lo_2 = cat(entries_ld[1].bits.deps_ld[1], entries_ld[1].bits.deps_ld[0]) node packed_deps_lo_hi_2 = cat(entries_ld[1].bits.deps_ld[3], entries_ld[1].bits.deps_ld[2]) node packed_deps_lo_3 = cat(packed_deps_lo_hi_2, packed_deps_lo_lo_2) node packed_deps_hi_lo_2 = cat(entries_ld[1].bits.deps_ld[5], entries_ld[1].bits.deps_ld[4]) node packed_deps_hi_hi_2 = cat(entries_ld[1].bits.deps_ld[7], entries_ld[1].bits.deps_ld[6]) node packed_deps_hi_4 = cat(packed_deps_hi_hi_2, packed_deps_hi_lo_2) node _packed_deps_T_4 = cat(packed_deps_hi_4, packed_deps_lo_3) node packed_deps_lo_lo_lo_1 = cat(entries_ld[1].bits.deps_ex[1], entries_ld[1].bits.deps_ex[0]) node packed_deps_lo_lo_hi_1 = cat(entries_ld[1].bits.deps_ex[3], entries_ld[1].bits.deps_ex[2]) node packed_deps_lo_lo_3 = cat(packed_deps_lo_lo_hi_1, packed_deps_lo_lo_lo_1) node packed_deps_lo_hi_lo_1 = cat(entries_ld[1].bits.deps_ex[5], entries_ld[1].bits.deps_ex[4]) node packed_deps_lo_hi_hi_1 = cat(entries_ld[1].bits.deps_ex[7], entries_ld[1].bits.deps_ex[6]) node packed_deps_lo_hi_3 = cat(packed_deps_lo_hi_hi_1, packed_deps_lo_hi_lo_1) node packed_deps_lo_4 = cat(packed_deps_lo_hi_3, packed_deps_lo_lo_3) node packed_deps_hi_lo_lo_1 = cat(entries_ld[1].bits.deps_ex[9], entries_ld[1].bits.deps_ex[8]) node packed_deps_hi_lo_hi_1 = cat(entries_ld[1].bits.deps_ex[11], entries_ld[1].bits.deps_ex[10]) node packed_deps_hi_lo_3 = cat(packed_deps_hi_lo_hi_1, packed_deps_hi_lo_lo_1) node packed_deps_hi_hi_lo_1 = cat(entries_ld[1].bits.deps_ex[13], entries_ld[1].bits.deps_ex[12]) node packed_deps_hi_hi_hi_1 = cat(entries_ld[1].bits.deps_ex[15], entries_ld[1].bits.deps_ex[14]) node packed_deps_hi_hi_3 = cat(packed_deps_hi_hi_hi_1, packed_deps_hi_hi_lo_1) node packed_deps_hi_5 = cat(packed_deps_hi_hi_3, packed_deps_hi_lo_3) node _packed_deps_T_5 = cat(packed_deps_hi_5, packed_deps_lo_4) node packed_deps_lo_5 = cat(entries_ld[1].bits.deps_st[1], entries_ld[1].bits.deps_st[0]) node packed_deps_hi_6 = cat(entries_ld[1].bits.deps_st[3], entries_ld[1].bits.deps_st[2]) node _packed_deps_T_6 = cat(packed_deps_hi_6, packed_deps_lo_5) node packed_deps_hi_7 = cat(_packed_deps_T_4, _packed_deps_T_5) node _packed_deps_T_7 = cat(packed_deps_hi_7, _packed_deps_T_6) node packed_deps_lo_lo_4 = cat(entries_ld[2].bits.deps_ld[1], entries_ld[2].bits.deps_ld[0]) node packed_deps_lo_hi_4 = cat(entries_ld[2].bits.deps_ld[3], entries_ld[2].bits.deps_ld[2]) node packed_deps_lo_6 = cat(packed_deps_lo_hi_4, packed_deps_lo_lo_4) node packed_deps_hi_lo_4 = cat(entries_ld[2].bits.deps_ld[5], entries_ld[2].bits.deps_ld[4]) node packed_deps_hi_hi_4 = cat(entries_ld[2].bits.deps_ld[7], entries_ld[2].bits.deps_ld[6]) node packed_deps_hi_8 = cat(packed_deps_hi_hi_4, packed_deps_hi_lo_4) node _packed_deps_T_8 = cat(packed_deps_hi_8, packed_deps_lo_6) node packed_deps_lo_lo_lo_2 = cat(entries_ld[2].bits.deps_ex[1], entries_ld[2].bits.deps_ex[0]) node packed_deps_lo_lo_hi_2 = cat(entries_ld[2].bits.deps_ex[3], entries_ld[2].bits.deps_ex[2]) node packed_deps_lo_lo_5 = cat(packed_deps_lo_lo_hi_2, packed_deps_lo_lo_lo_2) node packed_deps_lo_hi_lo_2 = cat(entries_ld[2].bits.deps_ex[5], entries_ld[2].bits.deps_ex[4]) node packed_deps_lo_hi_hi_2 = cat(entries_ld[2].bits.deps_ex[7], entries_ld[2].bits.deps_ex[6]) node packed_deps_lo_hi_5 = cat(packed_deps_lo_hi_hi_2, packed_deps_lo_hi_lo_2) node packed_deps_lo_7 = cat(packed_deps_lo_hi_5, packed_deps_lo_lo_5) node packed_deps_hi_lo_lo_2 = cat(entries_ld[2].bits.deps_ex[9], entries_ld[2].bits.deps_ex[8]) node packed_deps_hi_lo_hi_2 = cat(entries_ld[2].bits.deps_ex[11], entries_ld[2].bits.deps_ex[10]) node packed_deps_hi_lo_5 = cat(packed_deps_hi_lo_hi_2, packed_deps_hi_lo_lo_2) node packed_deps_hi_hi_lo_2 = cat(entries_ld[2].bits.deps_ex[13], entries_ld[2].bits.deps_ex[12]) node packed_deps_hi_hi_hi_2 = cat(entries_ld[2].bits.deps_ex[15], entries_ld[2].bits.deps_ex[14]) node packed_deps_hi_hi_5 = cat(packed_deps_hi_hi_hi_2, packed_deps_hi_hi_lo_2) node packed_deps_hi_9 = cat(packed_deps_hi_hi_5, packed_deps_hi_lo_5) node _packed_deps_T_9 = cat(packed_deps_hi_9, packed_deps_lo_7) node packed_deps_lo_8 = cat(entries_ld[2].bits.deps_st[1], entries_ld[2].bits.deps_st[0]) node packed_deps_hi_10 = cat(entries_ld[2].bits.deps_st[3], entries_ld[2].bits.deps_st[2]) node _packed_deps_T_10 = cat(packed_deps_hi_10, packed_deps_lo_8) node packed_deps_hi_11 = cat(_packed_deps_T_8, _packed_deps_T_9) node _packed_deps_T_11 = cat(packed_deps_hi_11, _packed_deps_T_10) node packed_deps_lo_lo_6 = cat(entries_ld[3].bits.deps_ld[1], entries_ld[3].bits.deps_ld[0]) node packed_deps_lo_hi_6 = cat(entries_ld[3].bits.deps_ld[3], entries_ld[3].bits.deps_ld[2]) node packed_deps_lo_9 = cat(packed_deps_lo_hi_6, packed_deps_lo_lo_6) node packed_deps_hi_lo_6 = cat(entries_ld[3].bits.deps_ld[5], entries_ld[3].bits.deps_ld[4]) node packed_deps_hi_hi_6 = cat(entries_ld[3].bits.deps_ld[7], entries_ld[3].bits.deps_ld[6]) node packed_deps_hi_12 = cat(packed_deps_hi_hi_6, packed_deps_hi_lo_6) node _packed_deps_T_12 = cat(packed_deps_hi_12, packed_deps_lo_9) node packed_deps_lo_lo_lo_3 = cat(entries_ld[3].bits.deps_ex[1], entries_ld[3].bits.deps_ex[0]) node packed_deps_lo_lo_hi_3 = cat(entries_ld[3].bits.deps_ex[3], entries_ld[3].bits.deps_ex[2]) node packed_deps_lo_lo_7 = cat(packed_deps_lo_lo_hi_3, packed_deps_lo_lo_lo_3) node packed_deps_lo_hi_lo_3 = cat(entries_ld[3].bits.deps_ex[5], entries_ld[3].bits.deps_ex[4]) node packed_deps_lo_hi_hi_3 = cat(entries_ld[3].bits.deps_ex[7], entries_ld[3].bits.deps_ex[6]) node packed_deps_lo_hi_7 = cat(packed_deps_lo_hi_hi_3, packed_deps_lo_hi_lo_3) node packed_deps_lo_10 = cat(packed_deps_lo_hi_7, packed_deps_lo_lo_7) node packed_deps_hi_lo_lo_3 = cat(entries_ld[3].bits.deps_ex[9], entries_ld[3].bits.deps_ex[8]) node packed_deps_hi_lo_hi_3 = cat(entries_ld[3].bits.deps_ex[11], entries_ld[3].bits.deps_ex[10]) node packed_deps_hi_lo_7 = cat(packed_deps_hi_lo_hi_3, packed_deps_hi_lo_lo_3) node packed_deps_hi_hi_lo_3 = cat(entries_ld[3].bits.deps_ex[13], entries_ld[3].bits.deps_ex[12]) node packed_deps_hi_hi_hi_3 = cat(entries_ld[3].bits.deps_ex[15], entries_ld[3].bits.deps_ex[14]) node packed_deps_hi_hi_7 = cat(packed_deps_hi_hi_hi_3, packed_deps_hi_hi_lo_3) node packed_deps_hi_13 = cat(packed_deps_hi_hi_7, packed_deps_hi_lo_7) node _packed_deps_T_13 = cat(packed_deps_hi_13, packed_deps_lo_10) node packed_deps_lo_11 = cat(entries_ld[3].bits.deps_st[1], entries_ld[3].bits.deps_st[0]) node packed_deps_hi_14 = cat(entries_ld[3].bits.deps_st[3], entries_ld[3].bits.deps_st[2]) node _packed_deps_T_14 = cat(packed_deps_hi_14, packed_deps_lo_11) node packed_deps_hi_15 = cat(_packed_deps_T_12, _packed_deps_T_13) node _packed_deps_T_15 = cat(packed_deps_hi_15, _packed_deps_T_14) node packed_deps_lo_lo_8 = cat(entries_ld[4].bits.deps_ld[1], entries_ld[4].bits.deps_ld[0]) node packed_deps_lo_hi_8 = cat(entries_ld[4].bits.deps_ld[3], entries_ld[4].bits.deps_ld[2]) node packed_deps_lo_12 = cat(packed_deps_lo_hi_8, packed_deps_lo_lo_8) node packed_deps_hi_lo_8 = cat(entries_ld[4].bits.deps_ld[5], entries_ld[4].bits.deps_ld[4]) node packed_deps_hi_hi_8 = cat(entries_ld[4].bits.deps_ld[7], entries_ld[4].bits.deps_ld[6]) node packed_deps_hi_16 = cat(packed_deps_hi_hi_8, packed_deps_hi_lo_8) node _packed_deps_T_16 = cat(packed_deps_hi_16, packed_deps_lo_12) node packed_deps_lo_lo_lo_4 = cat(entries_ld[4].bits.deps_ex[1], entries_ld[4].bits.deps_ex[0]) node packed_deps_lo_lo_hi_4 = cat(entries_ld[4].bits.deps_ex[3], entries_ld[4].bits.deps_ex[2]) node packed_deps_lo_lo_9 = cat(packed_deps_lo_lo_hi_4, packed_deps_lo_lo_lo_4) node packed_deps_lo_hi_lo_4 = cat(entries_ld[4].bits.deps_ex[5], entries_ld[4].bits.deps_ex[4]) node packed_deps_lo_hi_hi_4 = cat(entries_ld[4].bits.deps_ex[7], entries_ld[4].bits.deps_ex[6]) node packed_deps_lo_hi_9 = cat(packed_deps_lo_hi_hi_4, packed_deps_lo_hi_lo_4) node packed_deps_lo_13 = cat(packed_deps_lo_hi_9, packed_deps_lo_lo_9) node packed_deps_hi_lo_lo_4 = cat(entries_ld[4].bits.deps_ex[9], entries_ld[4].bits.deps_ex[8]) node packed_deps_hi_lo_hi_4 = cat(entries_ld[4].bits.deps_ex[11], entries_ld[4].bits.deps_ex[10]) node packed_deps_hi_lo_9 = cat(packed_deps_hi_lo_hi_4, packed_deps_hi_lo_lo_4) node packed_deps_hi_hi_lo_4 = cat(entries_ld[4].bits.deps_ex[13], entries_ld[4].bits.deps_ex[12]) node packed_deps_hi_hi_hi_4 = cat(entries_ld[4].bits.deps_ex[15], entries_ld[4].bits.deps_ex[14]) node packed_deps_hi_hi_9 = cat(packed_deps_hi_hi_hi_4, packed_deps_hi_hi_lo_4) node packed_deps_hi_17 = cat(packed_deps_hi_hi_9, packed_deps_hi_lo_9) node _packed_deps_T_17 = cat(packed_deps_hi_17, packed_deps_lo_13) node packed_deps_lo_14 = cat(entries_ld[4].bits.deps_st[1], entries_ld[4].bits.deps_st[0]) node packed_deps_hi_18 = cat(entries_ld[4].bits.deps_st[3], entries_ld[4].bits.deps_st[2]) node _packed_deps_T_18 = cat(packed_deps_hi_18, packed_deps_lo_14) node packed_deps_hi_19 = cat(_packed_deps_T_16, _packed_deps_T_17) node _packed_deps_T_19 = cat(packed_deps_hi_19, _packed_deps_T_18) node packed_deps_lo_lo_10 = cat(entries_ld[5].bits.deps_ld[1], entries_ld[5].bits.deps_ld[0]) node packed_deps_lo_hi_10 = cat(entries_ld[5].bits.deps_ld[3], entries_ld[5].bits.deps_ld[2]) node packed_deps_lo_15 = cat(packed_deps_lo_hi_10, packed_deps_lo_lo_10) node packed_deps_hi_lo_10 = cat(entries_ld[5].bits.deps_ld[5], entries_ld[5].bits.deps_ld[4]) node packed_deps_hi_hi_10 = cat(entries_ld[5].bits.deps_ld[7], entries_ld[5].bits.deps_ld[6]) node packed_deps_hi_20 = cat(packed_deps_hi_hi_10, packed_deps_hi_lo_10) node _packed_deps_T_20 = cat(packed_deps_hi_20, packed_deps_lo_15) node packed_deps_lo_lo_lo_5 = cat(entries_ld[5].bits.deps_ex[1], entries_ld[5].bits.deps_ex[0]) node packed_deps_lo_lo_hi_5 = cat(entries_ld[5].bits.deps_ex[3], entries_ld[5].bits.deps_ex[2]) node packed_deps_lo_lo_11 = cat(packed_deps_lo_lo_hi_5, packed_deps_lo_lo_lo_5) node packed_deps_lo_hi_lo_5 = cat(entries_ld[5].bits.deps_ex[5], entries_ld[5].bits.deps_ex[4]) node packed_deps_lo_hi_hi_5 = cat(entries_ld[5].bits.deps_ex[7], entries_ld[5].bits.deps_ex[6]) node packed_deps_lo_hi_11 = cat(packed_deps_lo_hi_hi_5, packed_deps_lo_hi_lo_5) node packed_deps_lo_16 = cat(packed_deps_lo_hi_11, packed_deps_lo_lo_11) node packed_deps_hi_lo_lo_5 = cat(entries_ld[5].bits.deps_ex[9], entries_ld[5].bits.deps_ex[8]) node packed_deps_hi_lo_hi_5 = cat(entries_ld[5].bits.deps_ex[11], entries_ld[5].bits.deps_ex[10]) node packed_deps_hi_lo_11 = cat(packed_deps_hi_lo_hi_5, packed_deps_hi_lo_lo_5) node packed_deps_hi_hi_lo_5 = cat(entries_ld[5].bits.deps_ex[13], entries_ld[5].bits.deps_ex[12]) node packed_deps_hi_hi_hi_5 = cat(entries_ld[5].bits.deps_ex[15], entries_ld[5].bits.deps_ex[14]) node packed_deps_hi_hi_11 = cat(packed_deps_hi_hi_hi_5, packed_deps_hi_hi_lo_5) node packed_deps_hi_21 = cat(packed_deps_hi_hi_11, packed_deps_hi_lo_11) node _packed_deps_T_21 = cat(packed_deps_hi_21, packed_deps_lo_16) node packed_deps_lo_17 = cat(entries_ld[5].bits.deps_st[1], entries_ld[5].bits.deps_st[0]) node packed_deps_hi_22 = cat(entries_ld[5].bits.deps_st[3], entries_ld[5].bits.deps_st[2]) node _packed_deps_T_22 = cat(packed_deps_hi_22, packed_deps_lo_17) node packed_deps_hi_23 = cat(_packed_deps_T_20, _packed_deps_T_21) node _packed_deps_T_23 = cat(packed_deps_hi_23, _packed_deps_T_22) node packed_deps_lo_lo_12 = cat(entries_ld[6].bits.deps_ld[1], entries_ld[6].bits.deps_ld[0]) node packed_deps_lo_hi_12 = cat(entries_ld[6].bits.deps_ld[3], entries_ld[6].bits.deps_ld[2]) node packed_deps_lo_18 = cat(packed_deps_lo_hi_12, packed_deps_lo_lo_12) node packed_deps_hi_lo_12 = cat(entries_ld[6].bits.deps_ld[5], entries_ld[6].bits.deps_ld[4]) node packed_deps_hi_hi_12 = cat(entries_ld[6].bits.deps_ld[7], entries_ld[6].bits.deps_ld[6]) node packed_deps_hi_24 = cat(packed_deps_hi_hi_12, packed_deps_hi_lo_12) node _packed_deps_T_24 = cat(packed_deps_hi_24, packed_deps_lo_18) node packed_deps_lo_lo_lo_6 = cat(entries_ld[6].bits.deps_ex[1], entries_ld[6].bits.deps_ex[0]) node packed_deps_lo_lo_hi_6 = cat(entries_ld[6].bits.deps_ex[3], entries_ld[6].bits.deps_ex[2]) node packed_deps_lo_lo_13 = cat(packed_deps_lo_lo_hi_6, packed_deps_lo_lo_lo_6) node packed_deps_lo_hi_lo_6 = cat(entries_ld[6].bits.deps_ex[5], entries_ld[6].bits.deps_ex[4]) node packed_deps_lo_hi_hi_6 = cat(entries_ld[6].bits.deps_ex[7], entries_ld[6].bits.deps_ex[6]) node packed_deps_lo_hi_13 = cat(packed_deps_lo_hi_hi_6, packed_deps_lo_hi_lo_6) node packed_deps_lo_19 = cat(packed_deps_lo_hi_13, packed_deps_lo_lo_13) node packed_deps_hi_lo_lo_6 = cat(entries_ld[6].bits.deps_ex[9], entries_ld[6].bits.deps_ex[8]) node packed_deps_hi_lo_hi_6 = cat(entries_ld[6].bits.deps_ex[11], entries_ld[6].bits.deps_ex[10]) node packed_deps_hi_lo_13 = cat(packed_deps_hi_lo_hi_6, packed_deps_hi_lo_lo_6) node packed_deps_hi_hi_lo_6 = cat(entries_ld[6].bits.deps_ex[13], entries_ld[6].bits.deps_ex[12]) node packed_deps_hi_hi_hi_6 = cat(entries_ld[6].bits.deps_ex[15], entries_ld[6].bits.deps_ex[14]) node packed_deps_hi_hi_13 = cat(packed_deps_hi_hi_hi_6, packed_deps_hi_hi_lo_6) node packed_deps_hi_25 = cat(packed_deps_hi_hi_13, packed_deps_hi_lo_13) node _packed_deps_T_25 = cat(packed_deps_hi_25, packed_deps_lo_19) node packed_deps_lo_20 = cat(entries_ld[6].bits.deps_st[1], entries_ld[6].bits.deps_st[0]) node packed_deps_hi_26 = cat(entries_ld[6].bits.deps_st[3], entries_ld[6].bits.deps_st[2]) node _packed_deps_T_26 = cat(packed_deps_hi_26, packed_deps_lo_20) node packed_deps_hi_27 = cat(_packed_deps_T_24, _packed_deps_T_25) node _packed_deps_T_27 = cat(packed_deps_hi_27, _packed_deps_T_26) node packed_deps_lo_lo_14 = cat(entries_ld[7].bits.deps_ld[1], entries_ld[7].bits.deps_ld[0]) node packed_deps_lo_hi_14 = cat(entries_ld[7].bits.deps_ld[3], entries_ld[7].bits.deps_ld[2]) node packed_deps_lo_21 = cat(packed_deps_lo_hi_14, packed_deps_lo_lo_14) node packed_deps_hi_lo_14 = cat(entries_ld[7].bits.deps_ld[5], entries_ld[7].bits.deps_ld[4]) node packed_deps_hi_hi_14 = cat(entries_ld[7].bits.deps_ld[7], entries_ld[7].bits.deps_ld[6]) node packed_deps_hi_28 = cat(packed_deps_hi_hi_14, packed_deps_hi_lo_14) node _packed_deps_T_28 = cat(packed_deps_hi_28, packed_deps_lo_21) node packed_deps_lo_lo_lo_7 = cat(entries_ld[7].bits.deps_ex[1], entries_ld[7].bits.deps_ex[0]) node packed_deps_lo_lo_hi_7 = cat(entries_ld[7].bits.deps_ex[3], entries_ld[7].bits.deps_ex[2]) node packed_deps_lo_lo_15 = cat(packed_deps_lo_lo_hi_7, packed_deps_lo_lo_lo_7) node packed_deps_lo_hi_lo_7 = cat(entries_ld[7].bits.deps_ex[5], entries_ld[7].bits.deps_ex[4]) node packed_deps_lo_hi_hi_7 = cat(entries_ld[7].bits.deps_ex[7], entries_ld[7].bits.deps_ex[6]) node packed_deps_lo_hi_15 = cat(packed_deps_lo_hi_hi_7, packed_deps_lo_hi_lo_7) node packed_deps_lo_22 = cat(packed_deps_lo_hi_15, packed_deps_lo_lo_15) node packed_deps_hi_lo_lo_7 = cat(entries_ld[7].bits.deps_ex[9], entries_ld[7].bits.deps_ex[8]) node packed_deps_hi_lo_hi_7 = cat(entries_ld[7].bits.deps_ex[11], entries_ld[7].bits.deps_ex[10]) node packed_deps_hi_lo_15 = cat(packed_deps_hi_lo_hi_7, packed_deps_hi_lo_lo_7) node packed_deps_hi_hi_lo_7 = cat(entries_ld[7].bits.deps_ex[13], entries_ld[7].bits.deps_ex[12]) node packed_deps_hi_hi_hi_7 = cat(entries_ld[7].bits.deps_ex[15], entries_ld[7].bits.deps_ex[14]) node packed_deps_hi_hi_15 = cat(packed_deps_hi_hi_hi_7, packed_deps_hi_hi_lo_7) node packed_deps_hi_29 = cat(packed_deps_hi_hi_15, packed_deps_hi_lo_15) node _packed_deps_T_29 = cat(packed_deps_hi_29, packed_deps_lo_22) node packed_deps_lo_23 = cat(entries_ld[7].bits.deps_st[1], entries_ld[7].bits.deps_st[0]) node packed_deps_hi_30 = cat(entries_ld[7].bits.deps_st[3], entries_ld[7].bits.deps_st[2]) node _packed_deps_T_30 = cat(packed_deps_hi_30, packed_deps_lo_23) node packed_deps_hi_31 = cat(_packed_deps_T_28, _packed_deps_T_29) node _packed_deps_T_31 = cat(packed_deps_hi_31, _packed_deps_T_30) node packed_deps_lo_lo_16 = cat(entries_ex[0].bits.deps_ld[1], entries_ex[0].bits.deps_ld[0]) node packed_deps_lo_hi_16 = cat(entries_ex[0].bits.deps_ld[3], entries_ex[0].bits.deps_ld[2]) node packed_deps_lo_24 = cat(packed_deps_lo_hi_16, packed_deps_lo_lo_16) node packed_deps_hi_lo_16 = cat(entries_ex[0].bits.deps_ld[5], entries_ex[0].bits.deps_ld[4]) node packed_deps_hi_hi_16 = cat(entries_ex[0].bits.deps_ld[7], entries_ex[0].bits.deps_ld[6]) node packed_deps_hi_32 = cat(packed_deps_hi_hi_16, packed_deps_hi_lo_16) node _packed_deps_T_32 = cat(packed_deps_hi_32, packed_deps_lo_24) node packed_deps_lo_lo_lo_8 = cat(entries_ex[0].bits.deps_ex[1], entries_ex[0].bits.deps_ex[0]) node packed_deps_lo_lo_hi_8 = cat(entries_ex[0].bits.deps_ex[3], entries_ex[0].bits.deps_ex[2]) node packed_deps_lo_lo_17 = cat(packed_deps_lo_lo_hi_8, packed_deps_lo_lo_lo_8) node packed_deps_lo_hi_lo_8 = cat(entries_ex[0].bits.deps_ex[5], entries_ex[0].bits.deps_ex[4]) node packed_deps_lo_hi_hi_8 = cat(entries_ex[0].bits.deps_ex[7], entries_ex[0].bits.deps_ex[6]) node packed_deps_lo_hi_17 = cat(packed_deps_lo_hi_hi_8, packed_deps_lo_hi_lo_8) node packed_deps_lo_25 = cat(packed_deps_lo_hi_17, packed_deps_lo_lo_17) node packed_deps_hi_lo_lo_8 = cat(entries_ex[0].bits.deps_ex[9], entries_ex[0].bits.deps_ex[8]) node packed_deps_hi_lo_hi_8 = cat(entries_ex[0].bits.deps_ex[11], entries_ex[0].bits.deps_ex[10]) node packed_deps_hi_lo_17 = cat(packed_deps_hi_lo_hi_8, packed_deps_hi_lo_lo_8) node packed_deps_hi_hi_lo_8 = cat(entries_ex[0].bits.deps_ex[13], entries_ex[0].bits.deps_ex[12]) node packed_deps_hi_hi_hi_8 = cat(entries_ex[0].bits.deps_ex[15], entries_ex[0].bits.deps_ex[14]) node packed_deps_hi_hi_17 = cat(packed_deps_hi_hi_hi_8, packed_deps_hi_hi_lo_8) node packed_deps_hi_33 = cat(packed_deps_hi_hi_17, packed_deps_hi_lo_17) node _packed_deps_T_33 = cat(packed_deps_hi_33, packed_deps_lo_25) node packed_deps_lo_26 = cat(entries_ex[0].bits.deps_st[1], entries_ex[0].bits.deps_st[0]) node packed_deps_hi_34 = cat(entries_ex[0].bits.deps_st[3], entries_ex[0].bits.deps_st[2]) node _packed_deps_T_34 = cat(packed_deps_hi_34, packed_deps_lo_26) node packed_deps_hi_35 = cat(_packed_deps_T_32, _packed_deps_T_33) node _packed_deps_T_35 = cat(packed_deps_hi_35, _packed_deps_T_34) node packed_deps_lo_lo_18 = cat(entries_ex[1].bits.deps_ld[1], entries_ex[1].bits.deps_ld[0]) node packed_deps_lo_hi_18 = cat(entries_ex[1].bits.deps_ld[3], entries_ex[1].bits.deps_ld[2]) node packed_deps_lo_27 = cat(packed_deps_lo_hi_18, packed_deps_lo_lo_18) node packed_deps_hi_lo_18 = cat(entries_ex[1].bits.deps_ld[5], entries_ex[1].bits.deps_ld[4]) node packed_deps_hi_hi_18 = cat(entries_ex[1].bits.deps_ld[7], entries_ex[1].bits.deps_ld[6]) node packed_deps_hi_36 = cat(packed_deps_hi_hi_18, packed_deps_hi_lo_18) node _packed_deps_T_36 = cat(packed_deps_hi_36, packed_deps_lo_27) node packed_deps_lo_lo_lo_9 = cat(entries_ex[1].bits.deps_ex[1], entries_ex[1].bits.deps_ex[0]) node packed_deps_lo_lo_hi_9 = cat(entries_ex[1].bits.deps_ex[3], entries_ex[1].bits.deps_ex[2]) node packed_deps_lo_lo_19 = cat(packed_deps_lo_lo_hi_9, packed_deps_lo_lo_lo_9) node packed_deps_lo_hi_lo_9 = cat(entries_ex[1].bits.deps_ex[5], entries_ex[1].bits.deps_ex[4]) node packed_deps_lo_hi_hi_9 = cat(entries_ex[1].bits.deps_ex[7], entries_ex[1].bits.deps_ex[6]) node packed_deps_lo_hi_19 = cat(packed_deps_lo_hi_hi_9, packed_deps_lo_hi_lo_9) node packed_deps_lo_28 = cat(packed_deps_lo_hi_19, packed_deps_lo_lo_19) node packed_deps_hi_lo_lo_9 = cat(entries_ex[1].bits.deps_ex[9], entries_ex[1].bits.deps_ex[8]) node packed_deps_hi_lo_hi_9 = cat(entries_ex[1].bits.deps_ex[11], entries_ex[1].bits.deps_ex[10]) node packed_deps_hi_lo_19 = cat(packed_deps_hi_lo_hi_9, packed_deps_hi_lo_lo_9) node packed_deps_hi_hi_lo_9 = cat(entries_ex[1].bits.deps_ex[13], entries_ex[1].bits.deps_ex[12]) node packed_deps_hi_hi_hi_9 = cat(entries_ex[1].bits.deps_ex[15], entries_ex[1].bits.deps_ex[14]) node packed_deps_hi_hi_19 = cat(packed_deps_hi_hi_hi_9, packed_deps_hi_hi_lo_9) node packed_deps_hi_37 = cat(packed_deps_hi_hi_19, packed_deps_hi_lo_19) node _packed_deps_T_37 = cat(packed_deps_hi_37, packed_deps_lo_28) node packed_deps_lo_29 = cat(entries_ex[1].bits.deps_st[1], entries_ex[1].bits.deps_st[0]) node packed_deps_hi_38 = cat(entries_ex[1].bits.deps_st[3], entries_ex[1].bits.deps_st[2]) node _packed_deps_T_38 = cat(packed_deps_hi_38, packed_deps_lo_29) node packed_deps_hi_39 = cat(_packed_deps_T_36, _packed_deps_T_37) node _packed_deps_T_39 = cat(packed_deps_hi_39, _packed_deps_T_38) node packed_deps_lo_lo_20 = cat(entries_ex[2].bits.deps_ld[1], entries_ex[2].bits.deps_ld[0]) node packed_deps_lo_hi_20 = cat(entries_ex[2].bits.deps_ld[3], entries_ex[2].bits.deps_ld[2]) node packed_deps_lo_30 = cat(packed_deps_lo_hi_20, packed_deps_lo_lo_20) node packed_deps_hi_lo_20 = cat(entries_ex[2].bits.deps_ld[5], entries_ex[2].bits.deps_ld[4]) node packed_deps_hi_hi_20 = cat(entries_ex[2].bits.deps_ld[7], entries_ex[2].bits.deps_ld[6]) node packed_deps_hi_40 = cat(packed_deps_hi_hi_20, packed_deps_hi_lo_20) node _packed_deps_T_40 = cat(packed_deps_hi_40, packed_deps_lo_30) node packed_deps_lo_lo_lo_10 = cat(entries_ex[2].bits.deps_ex[1], entries_ex[2].bits.deps_ex[0]) node packed_deps_lo_lo_hi_10 = cat(entries_ex[2].bits.deps_ex[3], entries_ex[2].bits.deps_ex[2]) node packed_deps_lo_lo_21 = cat(packed_deps_lo_lo_hi_10, packed_deps_lo_lo_lo_10) node packed_deps_lo_hi_lo_10 = cat(entries_ex[2].bits.deps_ex[5], entries_ex[2].bits.deps_ex[4]) node packed_deps_lo_hi_hi_10 = cat(entries_ex[2].bits.deps_ex[7], entries_ex[2].bits.deps_ex[6]) node packed_deps_lo_hi_21 = cat(packed_deps_lo_hi_hi_10, packed_deps_lo_hi_lo_10) node packed_deps_lo_31 = cat(packed_deps_lo_hi_21, packed_deps_lo_lo_21) node packed_deps_hi_lo_lo_10 = cat(entries_ex[2].bits.deps_ex[9], entries_ex[2].bits.deps_ex[8]) node packed_deps_hi_lo_hi_10 = cat(entries_ex[2].bits.deps_ex[11], entries_ex[2].bits.deps_ex[10]) node packed_deps_hi_lo_21 = cat(packed_deps_hi_lo_hi_10, packed_deps_hi_lo_lo_10) node packed_deps_hi_hi_lo_10 = cat(entries_ex[2].bits.deps_ex[13], entries_ex[2].bits.deps_ex[12]) node packed_deps_hi_hi_hi_10 = cat(entries_ex[2].bits.deps_ex[15], entries_ex[2].bits.deps_ex[14]) node packed_deps_hi_hi_21 = cat(packed_deps_hi_hi_hi_10, packed_deps_hi_hi_lo_10) node packed_deps_hi_41 = cat(packed_deps_hi_hi_21, packed_deps_hi_lo_21) node _packed_deps_T_41 = cat(packed_deps_hi_41, packed_deps_lo_31) node packed_deps_lo_32 = cat(entries_ex[2].bits.deps_st[1], entries_ex[2].bits.deps_st[0]) node packed_deps_hi_42 = cat(entries_ex[2].bits.deps_st[3], entries_ex[2].bits.deps_st[2]) node _packed_deps_T_42 = cat(packed_deps_hi_42, packed_deps_lo_32) node packed_deps_hi_43 = cat(_packed_deps_T_40, _packed_deps_T_41) node _packed_deps_T_43 = cat(packed_deps_hi_43, _packed_deps_T_42) node packed_deps_lo_lo_22 = cat(entries_ex[3].bits.deps_ld[1], entries_ex[3].bits.deps_ld[0]) node packed_deps_lo_hi_22 = cat(entries_ex[3].bits.deps_ld[3], entries_ex[3].bits.deps_ld[2]) node packed_deps_lo_33 = cat(packed_deps_lo_hi_22, packed_deps_lo_lo_22) node packed_deps_hi_lo_22 = cat(entries_ex[3].bits.deps_ld[5], entries_ex[3].bits.deps_ld[4]) node packed_deps_hi_hi_22 = cat(entries_ex[3].bits.deps_ld[7], entries_ex[3].bits.deps_ld[6]) node packed_deps_hi_44 = cat(packed_deps_hi_hi_22, packed_deps_hi_lo_22) node _packed_deps_T_44 = cat(packed_deps_hi_44, packed_deps_lo_33) node packed_deps_lo_lo_lo_11 = cat(entries_ex[3].bits.deps_ex[1], entries_ex[3].bits.deps_ex[0]) node packed_deps_lo_lo_hi_11 = cat(entries_ex[3].bits.deps_ex[3], entries_ex[3].bits.deps_ex[2]) node packed_deps_lo_lo_23 = cat(packed_deps_lo_lo_hi_11, packed_deps_lo_lo_lo_11) node packed_deps_lo_hi_lo_11 = cat(entries_ex[3].bits.deps_ex[5], entries_ex[3].bits.deps_ex[4]) node packed_deps_lo_hi_hi_11 = cat(entries_ex[3].bits.deps_ex[7], entries_ex[3].bits.deps_ex[6]) node packed_deps_lo_hi_23 = cat(packed_deps_lo_hi_hi_11, packed_deps_lo_hi_lo_11) node packed_deps_lo_34 = cat(packed_deps_lo_hi_23, packed_deps_lo_lo_23) node packed_deps_hi_lo_lo_11 = cat(entries_ex[3].bits.deps_ex[9], entries_ex[3].bits.deps_ex[8]) node packed_deps_hi_lo_hi_11 = cat(entries_ex[3].bits.deps_ex[11], entries_ex[3].bits.deps_ex[10]) node packed_deps_hi_lo_23 = cat(packed_deps_hi_lo_hi_11, packed_deps_hi_lo_lo_11) node packed_deps_hi_hi_lo_11 = cat(entries_ex[3].bits.deps_ex[13], entries_ex[3].bits.deps_ex[12]) node packed_deps_hi_hi_hi_11 = cat(entries_ex[3].bits.deps_ex[15], entries_ex[3].bits.deps_ex[14]) node packed_deps_hi_hi_23 = cat(packed_deps_hi_hi_hi_11, packed_deps_hi_hi_lo_11) node packed_deps_hi_45 = cat(packed_deps_hi_hi_23, packed_deps_hi_lo_23) node _packed_deps_T_45 = cat(packed_deps_hi_45, packed_deps_lo_34) node packed_deps_lo_35 = cat(entries_ex[3].bits.deps_st[1], entries_ex[3].bits.deps_st[0]) node packed_deps_hi_46 = cat(entries_ex[3].bits.deps_st[3], entries_ex[3].bits.deps_st[2]) node _packed_deps_T_46 = cat(packed_deps_hi_46, packed_deps_lo_35) node packed_deps_hi_47 = cat(_packed_deps_T_44, _packed_deps_T_45) node _packed_deps_T_47 = cat(packed_deps_hi_47, _packed_deps_T_46) node packed_deps_lo_lo_24 = cat(entries_ex[4].bits.deps_ld[1], entries_ex[4].bits.deps_ld[0]) node packed_deps_lo_hi_24 = cat(entries_ex[4].bits.deps_ld[3], entries_ex[4].bits.deps_ld[2]) node packed_deps_lo_36 = cat(packed_deps_lo_hi_24, packed_deps_lo_lo_24) node packed_deps_hi_lo_24 = cat(entries_ex[4].bits.deps_ld[5], entries_ex[4].bits.deps_ld[4]) node packed_deps_hi_hi_24 = cat(entries_ex[4].bits.deps_ld[7], entries_ex[4].bits.deps_ld[6]) node packed_deps_hi_48 = cat(packed_deps_hi_hi_24, packed_deps_hi_lo_24) node _packed_deps_T_48 = cat(packed_deps_hi_48, packed_deps_lo_36) node packed_deps_lo_lo_lo_12 = cat(entries_ex[4].bits.deps_ex[1], entries_ex[4].bits.deps_ex[0]) node packed_deps_lo_lo_hi_12 = cat(entries_ex[4].bits.deps_ex[3], entries_ex[4].bits.deps_ex[2]) node packed_deps_lo_lo_25 = cat(packed_deps_lo_lo_hi_12, packed_deps_lo_lo_lo_12) node packed_deps_lo_hi_lo_12 = cat(entries_ex[4].bits.deps_ex[5], entries_ex[4].bits.deps_ex[4]) node packed_deps_lo_hi_hi_12 = cat(entries_ex[4].bits.deps_ex[7], entries_ex[4].bits.deps_ex[6]) node packed_deps_lo_hi_25 = cat(packed_deps_lo_hi_hi_12, packed_deps_lo_hi_lo_12) node packed_deps_lo_37 = cat(packed_deps_lo_hi_25, packed_deps_lo_lo_25) node packed_deps_hi_lo_lo_12 = cat(entries_ex[4].bits.deps_ex[9], entries_ex[4].bits.deps_ex[8]) node packed_deps_hi_lo_hi_12 = cat(entries_ex[4].bits.deps_ex[11], entries_ex[4].bits.deps_ex[10]) node packed_deps_hi_lo_25 = cat(packed_deps_hi_lo_hi_12, packed_deps_hi_lo_lo_12) node packed_deps_hi_hi_lo_12 = cat(entries_ex[4].bits.deps_ex[13], entries_ex[4].bits.deps_ex[12]) node packed_deps_hi_hi_hi_12 = cat(entries_ex[4].bits.deps_ex[15], entries_ex[4].bits.deps_ex[14]) node packed_deps_hi_hi_25 = cat(packed_deps_hi_hi_hi_12, packed_deps_hi_hi_lo_12) node packed_deps_hi_49 = cat(packed_deps_hi_hi_25, packed_deps_hi_lo_25) node _packed_deps_T_49 = cat(packed_deps_hi_49, packed_deps_lo_37) node packed_deps_lo_38 = cat(entries_ex[4].bits.deps_st[1], entries_ex[4].bits.deps_st[0]) node packed_deps_hi_50 = cat(entries_ex[4].bits.deps_st[3], entries_ex[4].bits.deps_st[2]) node _packed_deps_T_50 = cat(packed_deps_hi_50, packed_deps_lo_38) node packed_deps_hi_51 = cat(_packed_deps_T_48, _packed_deps_T_49) node _packed_deps_T_51 = cat(packed_deps_hi_51, _packed_deps_T_50) node packed_deps_lo_lo_26 = cat(entries_ex[5].bits.deps_ld[1], entries_ex[5].bits.deps_ld[0]) node packed_deps_lo_hi_26 = cat(entries_ex[5].bits.deps_ld[3], entries_ex[5].bits.deps_ld[2]) node packed_deps_lo_39 = cat(packed_deps_lo_hi_26, packed_deps_lo_lo_26) node packed_deps_hi_lo_26 = cat(entries_ex[5].bits.deps_ld[5], entries_ex[5].bits.deps_ld[4]) node packed_deps_hi_hi_26 = cat(entries_ex[5].bits.deps_ld[7], entries_ex[5].bits.deps_ld[6]) node packed_deps_hi_52 = cat(packed_deps_hi_hi_26, packed_deps_hi_lo_26) node _packed_deps_T_52 = cat(packed_deps_hi_52, packed_deps_lo_39) node packed_deps_lo_lo_lo_13 = cat(entries_ex[5].bits.deps_ex[1], entries_ex[5].bits.deps_ex[0]) node packed_deps_lo_lo_hi_13 = cat(entries_ex[5].bits.deps_ex[3], entries_ex[5].bits.deps_ex[2]) node packed_deps_lo_lo_27 = cat(packed_deps_lo_lo_hi_13, packed_deps_lo_lo_lo_13) node packed_deps_lo_hi_lo_13 = cat(entries_ex[5].bits.deps_ex[5], entries_ex[5].bits.deps_ex[4]) node packed_deps_lo_hi_hi_13 = cat(entries_ex[5].bits.deps_ex[7], entries_ex[5].bits.deps_ex[6]) node packed_deps_lo_hi_27 = cat(packed_deps_lo_hi_hi_13, packed_deps_lo_hi_lo_13) node packed_deps_lo_40 = cat(packed_deps_lo_hi_27, packed_deps_lo_lo_27) node packed_deps_hi_lo_lo_13 = cat(entries_ex[5].bits.deps_ex[9], entries_ex[5].bits.deps_ex[8]) node packed_deps_hi_lo_hi_13 = cat(entries_ex[5].bits.deps_ex[11], entries_ex[5].bits.deps_ex[10]) node packed_deps_hi_lo_27 = cat(packed_deps_hi_lo_hi_13, packed_deps_hi_lo_lo_13) node packed_deps_hi_hi_lo_13 = cat(entries_ex[5].bits.deps_ex[13], entries_ex[5].bits.deps_ex[12]) node packed_deps_hi_hi_hi_13 = cat(entries_ex[5].bits.deps_ex[15], entries_ex[5].bits.deps_ex[14]) node packed_deps_hi_hi_27 = cat(packed_deps_hi_hi_hi_13, packed_deps_hi_hi_lo_13) node packed_deps_hi_53 = cat(packed_deps_hi_hi_27, packed_deps_hi_lo_27) node _packed_deps_T_53 = cat(packed_deps_hi_53, packed_deps_lo_40) node packed_deps_lo_41 = cat(entries_ex[5].bits.deps_st[1], entries_ex[5].bits.deps_st[0]) node packed_deps_hi_54 = cat(entries_ex[5].bits.deps_st[3], entries_ex[5].bits.deps_st[2]) node _packed_deps_T_54 = cat(packed_deps_hi_54, packed_deps_lo_41) node packed_deps_hi_55 = cat(_packed_deps_T_52, _packed_deps_T_53) node _packed_deps_T_55 = cat(packed_deps_hi_55, _packed_deps_T_54) node packed_deps_lo_lo_28 = cat(entries_ex[6].bits.deps_ld[1], entries_ex[6].bits.deps_ld[0]) node packed_deps_lo_hi_28 = cat(entries_ex[6].bits.deps_ld[3], entries_ex[6].bits.deps_ld[2]) node packed_deps_lo_42 = cat(packed_deps_lo_hi_28, packed_deps_lo_lo_28) node packed_deps_hi_lo_28 = cat(entries_ex[6].bits.deps_ld[5], entries_ex[6].bits.deps_ld[4]) node packed_deps_hi_hi_28 = cat(entries_ex[6].bits.deps_ld[7], entries_ex[6].bits.deps_ld[6]) node packed_deps_hi_56 = cat(packed_deps_hi_hi_28, packed_deps_hi_lo_28) node _packed_deps_T_56 = cat(packed_deps_hi_56, packed_deps_lo_42) node packed_deps_lo_lo_lo_14 = cat(entries_ex[6].bits.deps_ex[1], entries_ex[6].bits.deps_ex[0]) node packed_deps_lo_lo_hi_14 = cat(entries_ex[6].bits.deps_ex[3], entries_ex[6].bits.deps_ex[2]) node packed_deps_lo_lo_29 = cat(packed_deps_lo_lo_hi_14, packed_deps_lo_lo_lo_14) node packed_deps_lo_hi_lo_14 = cat(entries_ex[6].bits.deps_ex[5], entries_ex[6].bits.deps_ex[4]) node packed_deps_lo_hi_hi_14 = cat(entries_ex[6].bits.deps_ex[7], entries_ex[6].bits.deps_ex[6]) node packed_deps_lo_hi_29 = cat(packed_deps_lo_hi_hi_14, packed_deps_lo_hi_lo_14) node packed_deps_lo_43 = cat(packed_deps_lo_hi_29, packed_deps_lo_lo_29) node packed_deps_hi_lo_lo_14 = cat(entries_ex[6].bits.deps_ex[9], entries_ex[6].bits.deps_ex[8]) node packed_deps_hi_lo_hi_14 = cat(entries_ex[6].bits.deps_ex[11], entries_ex[6].bits.deps_ex[10]) node packed_deps_hi_lo_29 = cat(packed_deps_hi_lo_hi_14, packed_deps_hi_lo_lo_14) node packed_deps_hi_hi_lo_14 = cat(entries_ex[6].bits.deps_ex[13], entries_ex[6].bits.deps_ex[12]) node packed_deps_hi_hi_hi_14 = cat(entries_ex[6].bits.deps_ex[15], entries_ex[6].bits.deps_ex[14]) node packed_deps_hi_hi_29 = cat(packed_deps_hi_hi_hi_14, packed_deps_hi_hi_lo_14) node packed_deps_hi_57 = cat(packed_deps_hi_hi_29, packed_deps_hi_lo_29) node _packed_deps_T_57 = cat(packed_deps_hi_57, packed_deps_lo_43) node packed_deps_lo_44 = cat(entries_ex[6].bits.deps_st[1], entries_ex[6].bits.deps_st[0]) node packed_deps_hi_58 = cat(entries_ex[6].bits.deps_st[3], entries_ex[6].bits.deps_st[2]) node _packed_deps_T_58 = cat(packed_deps_hi_58, packed_deps_lo_44) node packed_deps_hi_59 = cat(_packed_deps_T_56, _packed_deps_T_57) node _packed_deps_T_59 = cat(packed_deps_hi_59, _packed_deps_T_58) node packed_deps_lo_lo_30 = cat(entries_ex[7].bits.deps_ld[1], entries_ex[7].bits.deps_ld[0]) node packed_deps_lo_hi_30 = cat(entries_ex[7].bits.deps_ld[3], entries_ex[7].bits.deps_ld[2]) node packed_deps_lo_45 = cat(packed_deps_lo_hi_30, packed_deps_lo_lo_30) node packed_deps_hi_lo_30 = cat(entries_ex[7].bits.deps_ld[5], entries_ex[7].bits.deps_ld[4]) node packed_deps_hi_hi_30 = cat(entries_ex[7].bits.deps_ld[7], entries_ex[7].bits.deps_ld[6]) node packed_deps_hi_60 = cat(packed_deps_hi_hi_30, packed_deps_hi_lo_30) node _packed_deps_T_60 = cat(packed_deps_hi_60, packed_deps_lo_45) node packed_deps_lo_lo_lo_15 = cat(entries_ex[7].bits.deps_ex[1], entries_ex[7].bits.deps_ex[0]) node packed_deps_lo_lo_hi_15 = cat(entries_ex[7].bits.deps_ex[3], entries_ex[7].bits.deps_ex[2]) node packed_deps_lo_lo_31 = cat(packed_deps_lo_lo_hi_15, packed_deps_lo_lo_lo_15) node packed_deps_lo_hi_lo_15 = cat(entries_ex[7].bits.deps_ex[5], entries_ex[7].bits.deps_ex[4]) node packed_deps_lo_hi_hi_15 = cat(entries_ex[7].bits.deps_ex[7], entries_ex[7].bits.deps_ex[6]) node packed_deps_lo_hi_31 = cat(packed_deps_lo_hi_hi_15, packed_deps_lo_hi_lo_15) node packed_deps_lo_46 = cat(packed_deps_lo_hi_31, packed_deps_lo_lo_31) node packed_deps_hi_lo_lo_15 = cat(entries_ex[7].bits.deps_ex[9], entries_ex[7].bits.deps_ex[8]) node packed_deps_hi_lo_hi_15 = cat(entries_ex[7].bits.deps_ex[11], entries_ex[7].bits.deps_ex[10]) node packed_deps_hi_lo_31 = cat(packed_deps_hi_lo_hi_15, packed_deps_hi_lo_lo_15) node packed_deps_hi_hi_lo_15 = cat(entries_ex[7].bits.deps_ex[13], entries_ex[7].bits.deps_ex[12]) node packed_deps_hi_hi_hi_15 = cat(entries_ex[7].bits.deps_ex[15], entries_ex[7].bits.deps_ex[14]) node packed_deps_hi_hi_31 = cat(packed_deps_hi_hi_hi_15, packed_deps_hi_hi_lo_15) node packed_deps_hi_61 = cat(packed_deps_hi_hi_31, packed_deps_hi_lo_31) node _packed_deps_T_61 = cat(packed_deps_hi_61, packed_deps_lo_46) node packed_deps_lo_47 = cat(entries_ex[7].bits.deps_st[1], entries_ex[7].bits.deps_st[0]) node packed_deps_hi_62 = cat(entries_ex[7].bits.deps_st[3], entries_ex[7].bits.deps_st[2]) node _packed_deps_T_62 = cat(packed_deps_hi_62, packed_deps_lo_47) node packed_deps_hi_63 = cat(_packed_deps_T_60, _packed_deps_T_61) node _packed_deps_T_63 = cat(packed_deps_hi_63, _packed_deps_T_62) node packed_deps_lo_lo_32 = cat(entries_ex[8].bits.deps_ld[1], entries_ex[8].bits.deps_ld[0]) node packed_deps_lo_hi_32 = cat(entries_ex[8].bits.deps_ld[3], entries_ex[8].bits.deps_ld[2]) node packed_deps_lo_48 = cat(packed_deps_lo_hi_32, packed_deps_lo_lo_32) node packed_deps_hi_lo_32 = cat(entries_ex[8].bits.deps_ld[5], entries_ex[8].bits.deps_ld[4]) node packed_deps_hi_hi_32 = cat(entries_ex[8].bits.deps_ld[7], entries_ex[8].bits.deps_ld[6]) node packed_deps_hi_64 = cat(packed_deps_hi_hi_32, packed_deps_hi_lo_32) node _packed_deps_T_64 = cat(packed_deps_hi_64, packed_deps_lo_48) node packed_deps_lo_lo_lo_16 = cat(entries_ex[8].bits.deps_ex[1], entries_ex[8].bits.deps_ex[0]) node packed_deps_lo_lo_hi_16 = cat(entries_ex[8].bits.deps_ex[3], entries_ex[8].bits.deps_ex[2]) node packed_deps_lo_lo_33 = cat(packed_deps_lo_lo_hi_16, packed_deps_lo_lo_lo_16) node packed_deps_lo_hi_lo_16 = cat(entries_ex[8].bits.deps_ex[5], entries_ex[8].bits.deps_ex[4]) node packed_deps_lo_hi_hi_16 = cat(entries_ex[8].bits.deps_ex[7], entries_ex[8].bits.deps_ex[6]) node packed_deps_lo_hi_33 = cat(packed_deps_lo_hi_hi_16, packed_deps_lo_hi_lo_16) node packed_deps_lo_49 = cat(packed_deps_lo_hi_33, packed_deps_lo_lo_33) node packed_deps_hi_lo_lo_16 = cat(entries_ex[8].bits.deps_ex[9], entries_ex[8].bits.deps_ex[8]) node packed_deps_hi_lo_hi_16 = cat(entries_ex[8].bits.deps_ex[11], entries_ex[8].bits.deps_ex[10]) node packed_deps_hi_lo_33 = cat(packed_deps_hi_lo_hi_16, packed_deps_hi_lo_lo_16) node packed_deps_hi_hi_lo_16 = cat(entries_ex[8].bits.deps_ex[13], entries_ex[8].bits.deps_ex[12]) node packed_deps_hi_hi_hi_16 = cat(entries_ex[8].bits.deps_ex[15], entries_ex[8].bits.deps_ex[14]) node packed_deps_hi_hi_33 = cat(packed_deps_hi_hi_hi_16, packed_deps_hi_hi_lo_16) node packed_deps_hi_65 = cat(packed_deps_hi_hi_33, packed_deps_hi_lo_33) node _packed_deps_T_65 = cat(packed_deps_hi_65, packed_deps_lo_49) node packed_deps_lo_50 = cat(entries_ex[8].bits.deps_st[1], entries_ex[8].bits.deps_st[0]) node packed_deps_hi_66 = cat(entries_ex[8].bits.deps_st[3], entries_ex[8].bits.deps_st[2]) node _packed_deps_T_66 = cat(packed_deps_hi_66, packed_deps_lo_50) node packed_deps_hi_67 = cat(_packed_deps_T_64, _packed_deps_T_65) node _packed_deps_T_67 = cat(packed_deps_hi_67, _packed_deps_T_66) node packed_deps_lo_lo_34 = cat(entries_ex[9].bits.deps_ld[1], entries_ex[9].bits.deps_ld[0]) node packed_deps_lo_hi_34 = cat(entries_ex[9].bits.deps_ld[3], entries_ex[9].bits.deps_ld[2]) node packed_deps_lo_51 = cat(packed_deps_lo_hi_34, packed_deps_lo_lo_34) node packed_deps_hi_lo_34 = cat(entries_ex[9].bits.deps_ld[5], entries_ex[9].bits.deps_ld[4]) node packed_deps_hi_hi_34 = cat(entries_ex[9].bits.deps_ld[7], entries_ex[9].bits.deps_ld[6]) node packed_deps_hi_68 = cat(packed_deps_hi_hi_34, packed_deps_hi_lo_34) node _packed_deps_T_68 = cat(packed_deps_hi_68, packed_deps_lo_51) node packed_deps_lo_lo_lo_17 = cat(entries_ex[9].bits.deps_ex[1], entries_ex[9].bits.deps_ex[0]) node packed_deps_lo_lo_hi_17 = cat(entries_ex[9].bits.deps_ex[3], entries_ex[9].bits.deps_ex[2]) node packed_deps_lo_lo_35 = cat(packed_deps_lo_lo_hi_17, packed_deps_lo_lo_lo_17) node packed_deps_lo_hi_lo_17 = cat(entries_ex[9].bits.deps_ex[5], entries_ex[9].bits.deps_ex[4]) node packed_deps_lo_hi_hi_17 = cat(entries_ex[9].bits.deps_ex[7], entries_ex[9].bits.deps_ex[6]) node packed_deps_lo_hi_35 = cat(packed_deps_lo_hi_hi_17, packed_deps_lo_hi_lo_17) node packed_deps_lo_52 = cat(packed_deps_lo_hi_35, packed_deps_lo_lo_35) node packed_deps_hi_lo_lo_17 = cat(entries_ex[9].bits.deps_ex[9], entries_ex[9].bits.deps_ex[8]) node packed_deps_hi_lo_hi_17 = cat(entries_ex[9].bits.deps_ex[11], entries_ex[9].bits.deps_ex[10]) node packed_deps_hi_lo_35 = cat(packed_deps_hi_lo_hi_17, packed_deps_hi_lo_lo_17) node packed_deps_hi_hi_lo_17 = cat(entries_ex[9].bits.deps_ex[13], entries_ex[9].bits.deps_ex[12]) node packed_deps_hi_hi_hi_17 = cat(entries_ex[9].bits.deps_ex[15], entries_ex[9].bits.deps_ex[14]) node packed_deps_hi_hi_35 = cat(packed_deps_hi_hi_hi_17, packed_deps_hi_hi_lo_17) node packed_deps_hi_69 = cat(packed_deps_hi_hi_35, packed_deps_hi_lo_35) node _packed_deps_T_69 = cat(packed_deps_hi_69, packed_deps_lo_52) node packed_deps_lo_53 = cat(entries_ex[9].bits.deps_st[1], entries_ex[9].bits.deps_st[0]) node packed_deps_hi_70 = cat(entries_ex[9].bits.deps_st[3], entries_ex[9].bits.deps_st[2]) node _packed_deps_T_70 = cat(packed_deps_hi_70, packed_deps_lo_53) node packed_deps_hi_71 = cat(_packed_deps_T_68, _packed_deps_T_69) node _packed_deps_T_71 = cat(packed_deps_hi_71, _packed_deps_T_70) node packed_deps_lo_lo_36 = cat(entries_ex[10].bits.deps_ld[1], entries_ex[10].bits.deps_ld[0]) node packed_deps_lo_hi_36 = cat(entries_ex[10].bits.deps_ld[3], entries_ex[10].bits.deps_ld[2]) node packed_deps_lo_54 = cat(packed_deps_lo_hi_36, packed_deps_lo_lo_36) node packed_deps_hi_lo_36 = cat(entries_ex[10].bits.deps_ld[5], entries_ex[10].bits.deps_ld[4]) node packed_deps_hi_hi_36 = cat(entries_ex[10].bits.deps_ld[7], entries_ex[10].bits.deps_ld[6]) node packed_deps_hi_72 = cat(packed_deps_hi_hi_36, packed_deps_hi_lo_36) node _packed_deps_T_72 = cat(packed_deps_hi_72, packed_deps_lo_54) node packed_deps_lo_lo_lo_18 = cat(entries_ex[10].bits.deps_ex[1], entries_ex[10].bits.deps_ex[0]) node packed_deps_lo_lo_hi_18 = cat(entries_ex[10].bits.deps_ex[3], entries_ex[10].bits.deps_ex[2]) node packed_deps_lo_lo_37 = cat(packed_deps_lo_lo_hi_18, packed_deps_lo_lo_lo_18) node packed_deps_lo_hi_lo_18 = cat(entries_ex[10].bits.deps_ex[5], entries_ex[10].bits.deps_ex[4]) node packed_deps_lo_hi_hi_18 = cat(entries_ex[10].bits.deps_ex[7], entries_ex[10].bits.deps_ex[6]) node packed_deps_lo_hi_37 = cat(packed_deps_lo_hi_hi_18, packed_deps_lo_hi_lo_18) node packed_deps_lo_55 = cat(packed_deps_lo_hi_37, packed_deps_lo_lo_37) node packed_deps_hi_lo_lo_18 = cat(entries_ex[10].bits.deps_ex[9], entries_ex[10].bits.deps_ex[8]) node packed_deps_hi_lo_hi_18 = cat(entries_ex[10].bits.deps_ex[11], entries_ex[10].bits.deps_ex[10]) node packed_deps_hi_lo_37 = cat(packed_deps_hi_lo_hi_18, packed_deps_hi_lo_lo_18) node packed_deps_hi_hi_lo_18 = cat(entries_ex[10].bits.deps_ex[13], entries_ex[10].bits.deps_ex[12]) node packed_deps_hi_hi_hi_18 = cat(entries_ex[10].bits.deps_ex[15], entries_ex[10].bits.deps_ex[14]) node packed_deps_hi_hi_37 = cat(packed_deps_hi_hi_hi_18, packed_deps_hi_hi_lo_18) node packed_deps_hi_73 = cat(packed_deps_hi_hi_37, packed_deps_hi_lo_37) node _packed_deps_T_73 = cat(packed_deps_hi_73, packed_deps_lo_55) node packed_deps_lo_56 = cat(entries_ex[10].bits.deps_st[1], entries_ex[10].bits.deps_st[0]) node packed_deps_hi_74 = cat(entries_ex[10].bits.deps_st[3], entries_ex[10].bits.deps_st[2]) node _packed_deps_T_74 = cat(packed_deps_hi_74, packed_deps_lo_56) node packed_deps_hi_75 = cat(_packed_deps_T_72, _packed_deps_T_73) node _packed_deps_T_75 = cat(packed_deps_hi_75, _packed_deps_T_74) node packed_deps_lo_lo_38 = cat(entries_ex[11].bits.deps_ld[1], entries_ex[11].bits.deps_ld[0]) node packed_deps_lo_hi_38 = cat(entries_ex[11].bits.deps_ld[3], entries_ex[11].bits.deps_ld[2]) node packed_deps_lo_57 = cat(packed_deps_lo_hi_38, packed_deps_lo_lo_38) node packed_deps_hi_lo_38 = cat(entries_ex[11].bits.deps_ld[5], entries_ex[11].bits.deps_ld[4]) node packed_deps_hi_hi_38 = cat(entries_ex[11].bits.deps_ld[7], entries_ex[11].bits.deps_ld[6]) node packed_deps_hi_76 = cat(packed_deps_hi_hi_38, packed_deps_hi_lo_38) node _packed_deps_T_76 = cat(packed_deps_hi_76, packed_deps_lo_57) node packed_deps_lo_lo_lo_19 = cat(entries_ex[11].bits.deps_ex[1], entries_ex[11].bits.deps_ex[0]) node packed_deps_lo_lo_hi_19 = cat(entries_ex[11].bits.deps_ex[3], entries_ex[11].bits.deps_ex[2]) node packed_deps_lo_lo_39 = cat(packed_deps_lo_lo_hi_19, packed_deps_lo_lo_lo_19) node packed_deps_lo_hi_lo_19 = cat(entries_ex[11].bits.deps_ex[5], entries_ex[11].bits.deps_ex[4]) node packed_deps_lo_hi_hi_19 = cat(entries_ex[11].bits.deps_ex[7], entries_ex[11].bits.deps_ex[6]) node packed_deps_lo_hi_39 = cat(packed_deps_lo_hi_hi_19, packed_deps_lo_hi_lo_19) node packed_deps_lo_58 = cat(packed_deps_lo_hi_39, packed_deps_lo_lo_39) node packed_deps_hi_lo_lo_19 = cat(entries_ex[11].bits.deps_ex[9], entries_ex[11].bits.deps_ex[8]) node packed_deps_hi_lo_hi_19 = cat(entries_ex[11].bits.deps_ex[11], entries_ex[11].bits.deps_ex[10]) node packed_deps_hi_lo_39 = cat(packed_deps_hi_lo_hi_19, packed_deps_hi_lo_lo_19) node packed_deps_hi_hi_lo_19 = cat(entries_ex[11].bits.deps_ex[13], entries_ex[11].bits.deps_ex[12]) node packed_deps_hi_hi_hi_19 = cat(entries_ex[11].bits.deps_ex[15], entries_ex[11].bits.deps_ex[14]) node packed_deps_hi_hi_39 = cat(packed_deps_hi_hi_hi_19, packed_deps_hi_hi_lo_19) node packed_deps_hi_77 = cat(packed_deps_hi_hi_39, packed_deps_hi_lo_39) node _packed_deps_T_77 = cat(packed_deps_hi_77, packed_deps_lo_58) node packed_deps_lo_59 = cat(entries_ex[11].bits.deps_st[1], entries_ex[11].bits.deps_st[0]) node packed_deps_hi_78 = cat(entries_ex[11].bits.deps_st[3], entries_ex[11].bits.deps_st[2]) node _packed_deps_T_78 = cat(packed_deps_hi_78, packed_deps_lo_59) node packed_deps_hi_79 = cat(_packed_deps_T_76, _packed_deps_T_77) node _packed_deps_T_79 = cat(packed_deps_hi_79, _packed_deps_T_78) node packed_deps_lo_lo_40 = cat(entries_ex[12].bits.deps_ld[1], entries_ex[12].bits.deps_ld[0]) node packed_deps_lo_hi_40 = cat(entries_ex[12].bits.deps_ld[3], entries_ex[12].bits.deps_ld[2]) node packed_deps_lo_60 = cat(packed_deps_lo_hi_40, packed_deps_lo_lo_40) node packed_deps_hi_lo_40 = cat(entries_ex[12].bits.deps_ld[5], entries_ex[12].bits.deps_ld[4]) node packed_deps_hi_hi_40 = cat(entries_ex[12].bits.deps_ld[7], entries_ex[12].bits.deps_ld[6]) node packed_deps_hi_80 = cat(packed_deps_hi_hi_40, packed_deps_hi_lo_40) node _packed_deps_T_80 = cat(packed_deps_hi_80, packed_deps_lo_60) node packed_deps_lo_lo_lo_20 = cat(entries_ex[12].bits.deps_ex[1], entries_ex[12].bits.deps_ex[0]) node packed_deps_lo_lo_hi_20 = cat(entries_ex[12].bits.deps_ex[3], entries_ex[12].bits.deps_ex[2]) node packed_deps_lo_lo_41 = cat(packed_deps_lo_lo_hi_20, packed_deps_lo_lo_lo_20) node packed_deps_lo_hi_lo_20 = cat(entries_ex[12].bits.deps_ex[5], entries_ex[12].bits.deps_ex[4]) node packed_deps_lo_hi_hi_20 = cat(entries_ex[12].bits.deps_ex[7], entries_ex[12].bits.deps_ex[6]) node packed_deps_lo_hi_41 = cat(packed_deps_lo_hi_hi_20, packed_deps_lo_hi_lo_20) node packed_deps_lo_61 = cat(packed_deps_lo_hi_41, packed_deps_lo_lo_41) node packed_deps_hi_lo_lo_20 = cat(entries_ex[12].bits.deps_ex[9], entries_ex[12].bits.deps_ex[8]) node packed_deps_hi_lo_hi_20 = cat(entries_ex[12].bits.deps_ex[11], entries_ex[12].bits.deps_ex[10]) node packed_deps_hi_lo_41 = cat(packed_deps_hi_lo_hi_20, packed_deps_hi_lo_lo_20) node packed_deps_hi_hi_lo_20 = cat(entries_ex[12].bits.deps_ex[13], entries_ex[12].bits.deps_ex[12]) node packed_deps_hi_hi_hi_20 = cat(entries_ex[12].bits.deps_ex[15], entries_ex[12].bits.deps_ex[14]) node packed_deps_hi_hi_41 = cat(packed_deps_hi_hi_hi_20, packed_deps_hi_hi_lo_20) node packed_deps_hi_81 = cat(packed_deps_hi_hi_41, packed_deps_hi_lo_41) node _packed_deps_T_81 = cat(packed_deps_hi_81, packed_deps_lo_61) node packed_deps_lo_62 = cat(entries_ex[12].bits.deps_st[1], entries_ex[12].bits.deps_st[0]) node packed_deps_hi_82 = cat(entries_ex[12].bits.deps_st[3], entries_ex[12].bits.deps_st[2]) node _packed_deps_T_82 = cat(packed_deps_hi_82, packed_deps_lo_62) node packed_deps_hi_83 = cat(_packed_deps_T_80, _packed_deps_T_81) node _packed_deps_T_83 = cat(packed_deps_hi_83, _packed_deps_T_82) node packed_deps_lo_lo_42 = cat(entries_ex[13].bits.deps_ld[1], entries_ex[13].bits.deps_ld[0]) node packed_deps_lo_hi_42 = cat(entries_ex[13].bits.deps_ld[3], entries_ex[13].bits.deps_ld[2]) node packed_deps_lo_63 = cat(packed_deps_lo_hi_42, packed_deps_lo_lo_42) node packed_deps_hi_lo_42 = cat(entries_ex[13].bits.deps_ld[5], entries_ex[13].bits.deps_ld[4]) node packed_deps_hi_hi_42 = cat(entries_ex[13].bits.deps_ld[7], entries_ex[13].bits.deps_ld[6]) node packed_deps_hi_84 = cat(packed_deps_hi_hi_42, packed_deps_hi_lo_42) node _packed_deps_T_84 = cat(packed_deps_hi_84, packed_deps_lo_63) node packed_deps_lo_lo_lo_21 = cat(entries_ex[13].bits.deps_ex[1], entries_ex[13].bits.deps_ex[0]) node packed_deps_lo_lo_hi_21 = cat(entries_ex[13].bits.deps_ex[3], entries_ex[13].bits.deps_ex[2]) node packed_deps_lo_lo_43 = cat(packed_deps_lo_lo_hi_21, packed_deps_lo_lo_lo_21) node packed_deps_lo_hi_lo_21 = cat(entries_ex[13].bits.deps_ex[5], entries_ex[13].bits.deps_ex[4]) node packed_deps_lo_hi_hi_21 = cat(entries_ex[13].bits.deps_ex[7], entries_ex[13].bits.deps_ex[6]) node packed_deps_lo_hi_43 = cat(packed_deps_lo_hi_hi_21, packed_deps_lo_hi_lo_21) node packed_deps_lo_64 = cat(packed_deps_lo_hi_43, packed_deps_lo_lo_43) node packed_deps_hi_lo_lo_21 = cat(entries_ex[13].bits.deps_ex[9], entries_ex[13].bits.deps_ex[8]) node packed_deps_hi_lo_hi_21 = cat(entries_ex[13].bits.deps_ex[11], entries_ex[13].bits.deps_ex[10]) node packed_deps_hi_lo_43 = cat(packed_deps_hi_lo_hi_21, packed_deps_hi_lo_lo_21) node packed_deps_hi_hi_lo_21 = cat(entries_ex[13].bits.deps_ex[13], entries_ex[13].bits.deps_ex[12]) node packed_deps_hi_hi_hi_21 = cat(entries_ex[13].bits.deps_ex[15], entries_ex[13].bits.deps_ex[14]) node packed_deps_hi_hi_43 = cat(packed_deps_hi_hi_hi_21, packed_deps_hi_hi_lo_21) node packed_deps_hi_85 = cat(packed_deps_hi_hi_43, packed_deps_hi_lo_43) node _packed_deps_T_85 = cat(packed_deps_hi_85, packed_deps_lo_64) node packed_deps_lo_65 = cat(entries_ex[13].bits.deps_st[1], entries_ex[13].bits.deps_st[0]) node packed_deps_hi_86 = cat(entries_ex[13].bits.deps_st[3], entries_ex[13].bits.deps_st[2]) node _packed_deps_T_86 = cat(packed_deps_hi_86, packed_deps_lo_65) node packed_deps_hi_87 = cat(_packed_deps_T_84, _packed_deps_T_85) node _packed_deps_T_87 = cat(packed_deps_hi_87, _packed_deps_T_86) node packed_deps_lo_lo_44 = cat(entries_ex[14].bits.deps_ld[1], entries_ex[14].bits.deps_ld[0]) node packed_deps_lo_hi_44 = cat(entries_ex[14].bits.deps_ld[3], entries_ex[14].bits.deps_ld[2]) node packed_deps_lo_66 = cat(packed_deps_lo_hi_44, packed_deps_lo_lo_44) node packed_deps_hi_lo_44 = cat(entries_ex[14].bits.deps_ld[5], entries_ex[14].bits.deps_ld[4]) node packed_deps_hi_hi_44 = cat(entries_ex[14].bits.deps_ld[7], entries_ex[14].bits.deps_ld[6]) node packed_deps_hi_88 = cat(packed_deps_hi_hi_44, packed_deps_hi_lo_44) node _packed_deps_T_88 = cat(packed_deps_hi_88, packed_deps_lo_66) node packed_deps_lo_lo_lo_22 = cat(entries_ex[14].bits.deps_ex[1], entries_ex[14].bits.deps_ex[0]) node packed_deps_lo_lo_hi_22 = cat(entries_ex[14].bits.deps_ex[3], entries_ex[14].bits.deps_ex[2]) node packed_deps_lo_lo_45 = cat(packed_deps_lo_lo_hi_22, packed_deps_lo_lo_lo_22) node packed_deps_lo_hi_lo_22 = cat(entries_ex[14].bits.deps_ex[5], entries_ex[14].bits.deps_ex[4]) node packed_deps_lo_hi_hi_22 = cat(entries_ex[14].bits.deps_ex[7], entries_ex[14].bits.deps_ex[6]) node packed_deps_lo_hi_45 = cat(packed_deps_lo_hi_hi_22, packed_deps_lo_hi_lo_22) node packed_deps_lo_67 = cat(packed_deps_lo_hi_45, packed_deps_lo_lo_45) node packed_deps_hi_lo_lo_22 = cat(entries_ex[14].bits.deps_ex[9], entries_ex[14].bits.deps_ex[8]) node packed_deps_hi_lo_hi_22 = cat(entries_ex[14].bits.deps_ex[11], entries_ex[14].bits.deps_ex[10]) node packed_deps_hi_lo_45 = cat(packed_deps_hi_lo_hi_22, packed_deps_hi_lo_lo_22) node packed_deps_hi_hi_lo_22 = cat(entries_ex[14].bits.deps_ex[13], entries_ex[14].bits.deps_ex[12]) node packed_deps_hi_hi_hi_22 = cat(entries_ex[14].bits.deps_ex[15], entries_ex[14].bits.deps_ex[14]) node packed_deps_hi_hi_45 = cat(packed_deps_hi_hi_hi_22, packed_deps_hi_hi_lo_22) node packed_deps_hi_89 = cat(packed_deps_hi_hi_45, packed_deps_hi_lo_45) node _packed_deps_T_89 = cat(packed_deps_hi_89, packed_deps_lo_67) node packed_deps_lo_68 = cat(entries_ex[14].bits.deps_st[1], entries_ex[14].bits.deps_st[0]) node packed_deps_hi_90 = cat(entries_ex[14].bits.deps_st[3], entries_ex[14].bits.deps_st[2]) node _packed_deps_T_90 = cat(packed_deps_hi_90, packed_deps_lo_68) node packed_deps_hi_91 = cat(_packed_deps_T_88, _packed_deps_T_89) node _packed_deps_T_91 = cat(packed_deps_hi_91, _packed_deps_T_90) node packed_deps_lo_lo_46 = cat(entries_ex[15].bits.deps_ld[1], entries_ex[15].bits.deps_ld[0]) node packed_deps_lo_hi_46 = cat(entries_ex[15].bits.deps_ld[3], entries_ex[15].bits.deps_ld[2]) node packed_deps_lo_69 = cat(packed_deps_lo_hi_46, packed_deps_lo_lo_46) node packed_deps_hi_lo_46 = cat(entries_ex[15].bits.deps_ld[5], entries_ex[15].bits.deps_ld[4]) node packed_deps_hi_hi_46 = cat(entries_ex[15].bits.deps_ld[7], entries_ex[15].bits.deps_ld[6]) node packed_deps_hi_92 = cat(packed_deps_hi_hi_46, packed_deps_hi_lo_46) node _packed_deps_T_92 = cat(packed_deps_hi_92, packed_deps_lo_69) node packed_deps_lo_lo_lo_23 = cat(entries_ex[15].bits.deps_ex[1], entries_ex[15].bits.deps_ex[0]) node packed_deps_lo_lo_hi_23 = cat(entries_ex[15].bits.deps_ex[3], entries_ex[15].bits.deps_ex[2]) node packed_deps_lo_lo_47 = cat(packed_deps_lo_lo_hi_23, packed_deps_lo_lo_lo_23) node packed_deps_lo_hi_lo_23 = cat(entries_ex[15].bits.deps_ex[5], entries_ex[15].bits.deps_ex[4]) node packed_deps_lo_hi_hi_23 = cat(entries_ex[15].bits.deps_ex[7], entries_ex[15].bits.deps_ex[6]) node packed_deps_lo_hi_47 = cat(packed_deps_lo_hi_hi_23, packed_deps_lo_hi_lo_23) node packed_deps_lo_70 = cat(packed_deps_lo_hi_47, packed_deps_lo_lo_47) node packed_deps_hi_lo_lo_23 = cat(entries_ex[15].bits.deps_ex[9], entries_ex[15].bits.deps_ex[8]) node packed_deps_hi_lo_hi_23 = cat(entries_ex[15].bits.deps_ex[11], entries_ex[15].bits.deps_ex[10]) node packed_deps_hi_lo_47 = cat(packed_deps_hi_lo_hi_23, packed_deps_hi_lo_lo_23) node packed_deps_hi_hi_lo_23 = cat(entries_ex[15].bits.deps_ex[13], entries_ex[15].bits.deps_ex[12]) node packed_deps_hi_hi_hi_23 = cat(entries_ex[15].bits.deps_ex[15], entries_ex[15].bits.deps_ex[14]) node packed_deps_hi_hi_47 = cat(packed_deps_hi_hi_hi_23, packed_deps_hi_hi_lo_23) node packed_deps_hi_93 = cat(packed_deps_hi_hi_47, packed_deps_hi_lo_47) node _packed_deps_T_93 = cat(packed_deps_hi_93, packed_deps_lo_70) node packed_deps_lo_71 = cat(entries_ex[15].bits.deps_st[1], entries_ex[15].bits.deps_st[0]) node packed_deps_hi_94 = cat(entries_ex[15].bits.deps_st[3], entries_ex[15].bits.deps_st[2]) node _packed_deps_T_94 = cat(packed_deps_hi_94, packed_deps_lo_71) node packed_deps_hi_95 = cat(_packed_deps_T_92, _packed_deps_T_93) node _packed_deps_T_95 = cat(packed_deps_hi_95, _packed_deps_T_94) node packed_deps_lo_lo_48 = cat(entries_st[0].bits.deps_ld[1], entries_st[0].bits.deps_ld[0]) node packed_deps_lo_hi_48 = cat(entries_st[0].bits.deps_ld[3], entries_st[0].bits.deps_ld[2]) node packed_deps_lo_72 = cat(packed_deps_lo_hi_48, packed_deps_lo_lo_48) node packed_deps_hi_lo_48 = cat(entries_st[0].bits.deps_ld[5], entries_st[0].bits.deps_ld[4]) node packed_deps_hi_hi_48 = cat(entries_st[0].bits.deps_ld[7], entries_st[0].bits.deps_ld[6]) node packed_deps_hi_96 = cat(packed_deps_hi_hi_48, packed_deps_hi_lo_48) node _packed_deps_T_96 = cat(packed_deps_hi_96, packed_deps_lo_72) node packed_deps_lo_lo_lo_24 = cat(entries_st[0].bits.deps_ex[1], entries_st[0].bits.deps_ex[0]) node packed_deps_lo_lo_hi_24 = cat(entries_st[0].bits.deps_ex[3], entries_st[0].bits.deps_ex[2]) node packed_deps_lo_lo_49 = cat(packed_deps_lo_lo_hi_24, packed_deps_lo_lo_lo_24) node packed_deps_lo_hi_lo_24 = cat(entries_st[0].bits.deps_ex[5], entries_st[0].bits.deps_ex[4]) node packed_deps_lo_hi_hi_24 = cat(entries_st[0].bits.deps_ex[7], entries_st[0].bits.deps_ex[6]) node packed_deps_lo_hi_49 = cat(packed_deps_lo_hi_hi_24, packed_deps_lo_hi_lo_24) node packed_deps_lo_73 = cat(packed_deps_lo_hi_49, packed_deps_lo_lo_49) node packed_deps_hi_lo_lo_24 = cat(entries_st[0].bits.deps_ex[9], entries_st[0].bits.deps_ex[8]) node packed_deps_hi_lo_hi_24 = cat(entries_st[0].bits.deps_ex[11], entries_st[0].bits.deps_ex[10]) node packed_deps_hi_lo_49 = cat(packed_deps_hi_lo_hi_24, packed_deps_hi_lo_lo_24) node packed_deps_hi_hi_lo_24 = cat(entries_st[0].bits.deps_ex[13], entries_st[0].bits.deps_ex[12]) node packed_deps_hi_hi_hi_24 = cat(entries_st[0].bits.deps_ex[15], entries_st[0].bits.deps_ex[14]) node packed_deps_hi_hi_49 = cat(packed_deps_hi_hi_hi_24, packed_deps_hi_hi_lo_24) node packed_deps_hi_97 = cat(packed_deps_hi_hi_49, packed_deps_hi_lo_49) node _packed_deps_T_97 = cat(packed_deps_hi_97, packed_deps_lo_73) node packed_deps_lo_74 = cat(entries_st[0].bits.deps_st[1], entries_st[0].bits.deps_st[0]) node packed_deps_hi_98 = cat(entries_st[0].bits.deps_st[3], entries_st[0].bits.deps_st[2]) node _packed_deps_T_98 = cat(packed_deps_hi_98, packed_deps_lo_74) node packed_deps_hi_99 = cat(_packed_deps_T_96, _packed_deps_T_97) node _packed_deps_T_99 = cat(packed_deps_hi_99, _packed_deps_T_98) node packed_deps_lo_lo_50 = cat(entries_st[1].bits.deps_ld[1], entries_st[1].bits.deps_ld[0]) node packed_deps_lo_hi_50 = cat(entries_st[1].bits.deps_ld[3], entries_st[1].bits.deps_ld[2]) node packed_deps_lo_75 = cat(packed_deps_lo_hi_50, packed_deps_lo_lo_50) node packed_deps_hi_lo_50 = cat(entries_st[1].bits.deps_ld[5], entries_st[1].bits.deps_ld[4]) node packed_deps_hi_hi_50 = cat(entries_st[1].bits.deps_ld[7], entries_st[1].bits.deps_ld[6]) node packed_deps_hi_100 = cat(packed_deps_hi_hi_50, packed_deps_hi_lo_50) node _packed_deps_T_100 = cat(packed_deps_hi_100, packed_deps_lo_75) node packed_deps_lo_lo_lo_25 = cat(entries_st[1].bits.deps_ex[1], entries_st[1].bits.deps_ex[0]) node packed_deps_lo_lo_hi_25 = cat(entries_st[1].bits.deps_ex[3], entries_st[1].bits.deps_ex[2]) node packed_deps_lo_lo_51 = cat(packed_deps_lo_lo_hi_25, packed_deps_lo_lo_lo_25) node packed_deps_lo_hi_lo_25 = cat(entries_st[1].bits.deps_ex[5], entries_st[1].bits.deps_ex[4]) node packed_deps_lo_hi_hi_25 = cat(entries_st[1].bits.deps_ex[7], entries_st[1].bits.deps_ex[6]) node packed_deps_lo_hi_51 = cat(packed_deps_lo_hi_hi_25, packed_deps_lo_hi_lo_25) node packed_deps_lo_76 = cat(packed_deps_lo_hi_51, packed_deps_lo_lo_51) node packed_deps_hi_lo_lo_25 = cat(entries_st[1].bits.deps_ex[9], entries_st[1].bits.deps_ex[8]) node packed_deps_hi_lo_hi_25 = cat(entries_st[1].bits.deps_ex[11], entries_st[1].bits.deps_ex[10]) node packed_deps_hi_lo_51 = cat(packed_deps_hi_lo_hi_25, packed_deps_hi_lo_lo_25) node packed_deps_hi_hi_lo_25 = cat(entries_st[1].bits.deps_ex[13], entries_st[1].bits.deps_ex[12]) node packed_deps_hi_hi_hi_25 = cat(entries_st[1].bits.deps_ex[15], entries_st[1].bits.deps_ex[14]) node packed_deps_hi_hi_51 = cat(packed_deps_hi_hi_hi_25, packed_deps_hi_hi_lo_25) node packed_deps_hi_101 = cat(packed_deps_hi_hi_51, packed_deps_hi_lo_51) node _packed_deps_T_101 = cat(packed_deps_hi_101, packed_deps_lo_76) node packed_deps_lo_77 = cat(entries_st[1].bits.deps_st[1], entries_st[1].bits.deps_st[0]) node packed_deps_hi_102 = cat(entries_st[1].bits.deps_st[3], entries_st[1].bits.deps_st[2]) node _packed_deps_T_102 = cat(packed_deps_hi_102, packed_deps_lo_77) node packed_deps_hi_103 = cat(_packed_deps_T_100, _packed_deps_T_101) node _packed_deps_T_103 = cat(packed_deps_hi_103, _packed_deps_T_102) node packed_deps_lo_lo_52 = cat(entries_st[2].bits.deps_ld[1], entries_st[2].bits.deps_ld[0]) node packed_deps_lo_hi_52 = cat(entries_st[2].bits.deps_ld[3], entries_st[2].bits.deps_ld[2]) node packed_deps_lo_78 = cat(packed_deps_lo_hi_52, packed_deps_lo_lo_52) node packed_deps_hi_lo_52 = cat(entries_st[2].bits.deps_ld[5], entries_st[2].bits.deps_ld[4]) node packed_deps_hi_hi_52 = cat(entries_st[2].bits.deps_ld[7], entries_st[2].bits.deps_ld[6]) node packed_deps_hi_104 = cat(packed_deps_hi_hi_52, packed_deps_hi_lo_52) node _packed_deps_T_104 = cat(packed_deps_hi_104, packed_deps_lo_78) node packed_deps_lo_lo_lo_26 = cat(entries_st[2].bits.deps_ex[1], entries_st[2].bits.deps_ex[0]) node packed_deps_lo_lo_hi_26 = cat(entries_st[2].bits.deps_ex[3], entries_st[2].bits.deps_ex[2]) node packed_deps_lo_lo_53 = cat(packed_deps_lo_lo_hi_26, packed_deps_lo_lo_lo_26) node packed_deps_lo_hi_lo_26 = cat(entries_st[2].bits.deps_ex[5], entries_st[2].bits.deps_ex[4]) node packed_deps_lo_hi_hi_26 = cat(entries_st[2].bits.deps_ex[7], entries_st[2].bits.deps_ex[6]) node packed_deps_lo_hi_53 = cat(packed_deps_lo_hi_hi_26, packed_deps_lo_hi_lo_26) node packed_deps_lo_79 = cat(packed_deps_lo_hi_53, packed_deps_lo_lo_53) node packed_deps_hi_lo_lo_26 = cat(entries_st[2].bits.deps_ex[9], entries_st[2].bits.deps_ex[8]) node packed_deps_hi_lo_hi_26 = cat(entries_st[2].bits.deps_ex[11], entries_st[2].bits.deps_ex[10]) node packed_deps_hi_lo_53 = cat(packed_deps_hi_lo_hi_26, packed_deps_hi_lo_lo_26) node packed_deps_hi_hi_lo_26 = cat(entries_st[2].bits.deps_ex[13], entries_st[2].bits.deps_ex[12]) node packed_deps_hi_hi_hi_26 = cat(entries_st[2].bits.deps_ex[15], entries_st[2].bits.deps_ex[14]) node packed_deps_hi_hi_53 = cat(packed_deps_hi_hi_hi_26, packed_deps_hi_hi_lo_26) node packed_deps_hi_105 = cat(packed_deps_hi_hi_53, packed_deps_hi_lo_53) node _packed_deps_T_105 = cat(packed_deps_hi_105, packed_deps_lo_79) node packed_deps_lo_80 = cat(entries_st[2].bits.deps_st[1], entries_st[2].bits.deps_st[0]) node packed_deps_hi_106 = cat(entries_st[2].bits.deps_st[3], entries_st[2].bits.deps_st[2]) node _packed_deps_T_106 = cat(packed_deps_hi_106, packed_deps_lo_80) node packed_deps_hi_107 = cat(_packed_deps_T_104, _packed_deps_T_105) node _packed_deps_T_107 = cat(packed_deps_hi_107, _packed_deps_T_106) node packed_deps_lo_lo_54 = cat(entries_st[3].bits.deps_ld[1], entries_st[3].bits.deps_ld[0]) node packed_deps_lo_hi_54 = cat(entries_st[3].bits.deps_ld[3], entries_st[3].bits.deps_ld[2]) node packed_deps_lo_81 = cat(packed_deps_lo_hi_54, packed_deps_lo_lo_54) node packed_deps_hi_lo_54 = cat(entries_st[3].bits.deps_ld[5], entries_st[3].bits.deps_ld[4]) node packed_deps_hi_hi_54 = cat(entries_st[3].bits.deps_ld[7], entries_st[3].bits.deps_ld[6]) node packed_deps_hi_108 = cat(packed_deps_hi_hi_54, packed_deps_hi_lo_54) node _packed_deps_T_108 = cat(packed_deps_hi_108, packed_deps_lo_81) node packed_deps_lo_lo_lo_27 = cat(entries_st[3].bits.deps_ex[1], entries_st[3].bits.deps_ex[0]) node packed_deps_lo_lo_hi_27 = cat(entries_st[3].bits.deps_ex[3], entries_st[3].bits.deps_ex[2]) node packed_deps_lo_lo_55 = cat(packed_deps_lo_lo_hi_27, packed_deps_lo_lo_lo_27) node packed_deps_lo_hi_lo_27 = cat(entries_st[3].bits.deps_ex[5], entries_st[3].bits.deps_ex[4]) node packed_deps_lo_hi_hi_27 = cat(entries_st[3].bits.deps_ex[7], entries_st[3].bits.deps_ex[6]) node packed_deps_lo_hi_55 = cat(packed_deps_lo_hi_hi_27, packed_deps_lo_hi_lo_27) node packed_deps_lo_82 = cat(packed_deps_lo_hi_55, packed_deps_lo_lo_55) node packed_deps_hi_lo_lo_27 = cat(entries_st[3].bits.deps_ex[9], entries_st[3].bits.deps_ex[8]) node packed_deps_hi_lo_hi_27 = cat(entries_st[3].bits.deps_ex[11], entries_st[3].bits.deps_ex[10]) node packed_deps_hi_lo_55 = cat(packed_deps_hi_lo_hi_27, packed_deps_hi_lo_lo_27) node packed_deps_hi_hi_lo_27 = cat(entries_st[3].bits.deps_ex[13], entries_st[3].bits.deps_ex[12]) node packed_deps_hi_hi_hi_27 = cat(entries_st[3].bits.deps_ex[15], entries_st[3].bits.deps_ex[14]) node packed_deps_hi_hi_55 = cat(packed_deps_hi_hi_hi_27, packed_deps_hi_hi_lo_27) node packed_deps_hi_109 = cat(packed_deps_hi_hi_55, packed_deps_hi_lo_55) node _packed_deps_T_109 = cat(packed_deps_hi_109, packed_deps_lo_82) node packed_deps_lo_83 = cat(entries_st[3].bits.deps_st[1], entries_st[3].bits.deps_st[0]) node packed_deps_hi_110 = cat(entries_st[3].bits.deps_st[3], entries_st[3].bits.deps_st[2]) node _packed_deps_T_110 = cat(packed_deps_hi_110, packed_deps_lo_83) node packed_deps_hi_111 = cat(_packed_deps_T_108, _packed_deps_T_109) node _packed_deps_T_111 = cat(packed_deps_hi_111, _packed_deps_T_110) wire packed_deps : UInt<28>[28] connect packed_deps[0], _packed_deps_T_3 connect packed_deps[1], _packed_deps_T_7 connect packed_deps[2], _packed_deps_T_11 connect packed_deps[3], _packed_deps_T_15 connect packed_deps[4], _packed_deps_T_19 connect packed_deps[5], _packed_deps_T_23 connect packed_deps[6], _packed_deps_T_27 connect packed_deps[7], _packed_deps_T_31 connect packed_deps[8], _packed_deps_T_35 connect packed_deps[9], _packed_deps_T_39 connect packed_deps[10], _packed_deps_T_43 connect packed_deps[11], _packed_deps_T_47 connect packed_deps[12], _packed_deps_T_51 connect packed_deps[13], _packed_deps_T_55 connect packed_deps[14], _packed_deps_T_59 connect packed_deps[15], _packed_deps_T_63 connect packed_deps[16], _packed_deps_T_67 connect packed_deps[17], _packed_deps_T_71 connect packed_deps[18], _packed_deps_T_75 connect packed_deps[19], _packed_deps_T_79 connect packed_deps[20], _packed_deps_T_83 connect packed_deps[21], _packed_deps_T_87 connect packed_deps[22], _packed_deps_T_91 connect packed_deps[23], _packed_deps_T_95 connect packed_deps[24], _packed_deps_T_99 connect packed_deps[25], _packed_deps_T_103 connect packed_deps[26], _packed_deps_T_107 connect packed_deps[27], _packed_deps_T_111 node _pop_count_packed_deps_T = add(entries_ld[0].bits.deps_ld[0], entries_ld[0].bits.deps_ld[1]) node _pop_count_packed_deps_T_1 = bits(_pop_count_packed_deps_T, 1, 0) node _pop_count_packed_deps_T_2 = add(entries_ld[0].bits.deps_ld[2], entries_ld[0].bits.deps_ld[3]) node _pop_count_packed_deps_T_3 = bits(_pop_count_packed_deps_T_2, 1, 0) node _pop_count_packed_deps_T_4 = add(_pop_count_packed_deps_T_1, _pop_count_packed_deps_T_3) node _pop_count_packed_deps_T_5 = bits(_pop_count_packed_deps_T_4, 2, 0) node _pop_count_packed_deps_T_6 = add(entries_ld[0].bits.deps_ld[4], entries_ld[0].bits.deps_ld[5]) node _pop_count_packed_deps_T_7 = bits(_pop_count_packed_deps_T_6, 1, 0) node _pop_count_packed_deps_T_8 = add(entries_ld[0].bits.deps_ld[6], entries_ld[0].bits.deps_ld[7]) node _pop_count_packed_deps_T_9 = bits(_pop_count_packed_deps_T_8, 1, 0) node _pop_count_packed_deps_T_10 = add(_pop_count_packed_deps_T_7, _pop_count_packed_deps_T_9) node _pop_count_packed_deps_T_11 = bits(_pop_count_packed_deps_T_10, 2, 0) node _pop_count_packed_deps_T_12 = add(_pop_count_packed_deps_T_5, _pop_count_packed_deps_T_11) node _pop_count_packed_deps_T_13 = bits(_pop_count_packed_deps_T_12, 3, 0) node _pop_count_packed_deps_T_14 = add(entries_ld[0].bits.deps_ex[0], entries_ld[0].bits.deps_ex[1]) node _pop_count_packed_deps_T_15 = bits(_pop_count_packed_deps_T_14, 1, 0) node _pop_count_packed_deps_T_16 = add(entries_ld[0].bits.deps_ex[2], entries_ld[0].bits.deps_ex[3]) node _pop_count_packed_deps_T_17 = bits(_pop_count_packed_deps_T_16, 1, 0) node _pop_count_packed_deps_T_18 = add(_pop_count_packed_deps_T_15, _pop_count_packed_deps_T_17) node _pop_count_packed_deps_T_19 = bits(_pop_count_packed_deps_T_18, 2, 0) node _pop_count_packed_deps_T_20 = add(entries_ld[0].bits.deps_ex[4], entries_ld[0].bits.deps_ex[5]) node _pop_count_packed_deps_T_21 = bits(_pop_count_packed_deps_T_20, 1, 0) node _pop_count_packed_deps_T_22 = add(entries_ld[0].bits.deps_ex[6], entries_ld[0].bits.deps_ex[7]) node _pop_count_packed_deps_T_23 = bits(_pop_count_packed_deps_T_22, 1, 0) node _pop_count_packed_deps_T_24 = add(_pop_count_packed_deps_T_21, _pop_count_packed_deps_T_23) node _pop_count_packed_deps_T_25 = bits(_pop_count_packed_deps_T_24, 2, 0) node _pop_count_packed_deps_T_26 = add(_pop_count_packed_deps_T_19, _pop_count_packed_deps_T_25) node _pop_count_packed_deps_T_27 = bits(_pop_count_packed_deps_T_26, 3, 0) node _pop_count_packed_deps_T_28 = add(entries_ld[0].bits.deps_ex[8], entries_ld[0].bits.deps_ex[9]) node _pop_count_packed_deps_T_29 = bits(_pop_count_packed_deps_T_28, 1, 0) node _pop_count_packed_deps_T_30 = add(entries_ld[0].bits.deps_ex[10], entries_ld[0].bits.deps_ex[11]) node _pop_count_packed_deps_T_31 = bits(_pop_count_packed_deps_T_30, 1, 0) node _pop_count_packed_deps_T_32 = add(_pop_count_packed_deps_T_29, _pop_count_packed_deps_T_31) node _pop_count_packed_deps_T_33 = bits(_pop_count_packed_deps_T_32, 2, 0) node _pop_count_packed_deps_T_34 = add(entries_ld[0].bits.deps_ex[12], entries_ld[0].bits.deps_ex[13]) node _pop_count_packed_deps_T_35 = bits(_pop_count_packed_deps_T_34, 1, 0) node _pop_count_packed_deps_T_36 = add(entries_ld[0].bits.deps_ex[14], entries_ld[0].bits.deps_ex[15]) node _pop_count_packed_deps_T_37 = bits(_pop_count_packed_deps_T_36, 1, 0) node _pop_count_packed_deps_T_38 = add(_pop_count_packed_deps_T_35, _pop_count_packed_deps_T_37) node _pop_count_packed_deps_T_39 = bits(_pop_count_packed_deps_T_38, 2, 0) node _pop_count_packed_deps_T_40 = add(_pop_count_packed_deps_T_33, _pop_count_packed_deps_T_39) node _pop_count_packed_deps_T_41 = bits(_pop_count_packed_deps_T_40, 3, 0) node _pop_count_packed_deps_T_42 = add(_pop_count_packed_deps_T_27, _pop_count_packed_deps_T_41) node _pop_count_packed_deps_T_43 = bits(_pop_count_packed_deps_T_42, 4, 0) node _pop_count_packed_deps_T_44 = add(_pop_count_packed_deps_T_13, _pop_count_packed_deps_T_43) node _pop_count_packed_deps_T_45 = tail(_pop_count_packed_deps_T_44, 1) node _pop_count_packed_deps_T_46 = add(entries_ld[0].bits.deps_st[0], entries_ld[0].bits.deps_st[1]) node _pop_count_packed_deps_T_47 = bits(_pop_count_packed_deps_T_46, 1, 0) node _pop_count_packed_deps_T_48 = add(entries_ld[0].bits.deps_st[2], entries_ld[0].bits.deps_st[3]) node _pop_count_packed_deps_T_49 = bits(_pop_count_packed_deps_T_48, 1, 0) node _pop_count_packed_deps_T_50 = add(_pop_count_packed_deps_T_47, _pop_count_packed_deps_T_49) node _pop_count_packed_deps_T_51 = bits(_pop_count_packed_deps_T_50, 2, 0) node _pop_count_packed_deps_T_52 = add(_pop_count_packed_deps_T_45, _pop_count_packed_deps_T_51) node _pop_count_packed_deps_T_53 = tail(_pop_count_packed_deps_T_52, 1) node _pop_count_packed_deps_T_54 = mux(entries_ld[0].valid, _pop_count_packed_deps_T_53, UInt<1>(0h0)) node _pop_count_packed_deps_T_55 = add(entries_ld[1].bits.deps_ld[0], entries_ld[1].bits.deps_ld[1]) node _pop_count_packed_deps_T_56 = bits(_pop_count_packed_deps_T_55, 1, 0) node _pop_count_packed_deps_T_57 = add(entries_ld[1].bits.deps_ld[2], entries_ld[1].bits.deps_ld[3]) node _pop_count_packed_deps_T_58 = bits(_pop_count_packed_deps_T_57, 1, 0) node _pop_count_packed_deps_T_59 = add(_pop_count_packed_deps_T_56, _pop_count_packed_deps_T_58) node _pop_count_packed_deps_T_60 = bits(_pop_count_packed_deps_T_59, 2, 0) node _pop_count_packed_deps_T_61 = add(entries_ld[1].bits.deps_ld[4], entries_ld[1].bits.deps_ld[5]) node _pop_count_packed_deps_T_62 = bits(_pop_count_packed_deps_T_61, 1, 0) node _pop_count_packed_deps_T_63 = add(entries_ld[1].bits.deps_ld[6], entries_ld[1].bits.deps_ld[7]) node _pop_count_packed_deps_T_64 = bits(_pop_count_packed_deps_T_63, 1, 0) node _pop_count_packed_deps_T_65 = add(_pop_count_packed_deps_T_62, _pop_count_packed_deps_T_64) node _pop_count_packed_deps_T_66 = bits(_pop_count_packed_deps_T_65, 2, 0) node _pop_count_packed_deps_T_67 = add(_pop_count_packed_deps_T_60, _pop_count_packed_deps_T_66) node _pop_count_packed_deps_T_68 = bits(_pop_count_packed_deps_T_67, 3, 0) node _pop_count_packed_deps_T_69 = add(entries_ld[1].bits.deps_ex[0], entries_ld[1].bits.deps_ex[1]) node _pop_count_packed_deps_T_70 = bits(_pop_count_packed_deps_T_69, 1, 0) node _pop_count_packed_deps_T_71 = add(entries_ld[1].bits.deps_ex[2], entries_ld[1].bits.deps_ex[3]) node _pop_count_packed_deps_T_72 = bits(_pop_count_packed_deps_T_71, 1, 0) node _pop_count_packed_deps_T_73 = add(_pop_count_packed_deps_T_70, _pop_count_packed_deps_T_72) node _pop_count_packed_deps_T_74 = bits(_pop_count_packed_deps_T_73, 2, 0) node _pop_count_packed_deps_T_75 = add(entries_ld[1].bits.deps_ex[4], entries_ld[1].bits.deps_ex[5]) node _pop_count_packed_deps_T_76 = bits(_pop_count_packed_deps_T_75, 1, 0) node _pop_count_packed_deps_T_77 = add(entries_ld[1].bits.deps_ex[6], entries_ld[1].bits.deps_ex[7]) node _pop_count_packed_deps_T_78 = bits(_pop_count_packed_deps_T_77, 1, 0) node _pop_count_packed_deps_T_79 = add(_pop_count_packed_deps_T_76, _pop_count_packed_deps_T_78) node _pop_count_packed_deps_T_80 = bits(_pop_count_packed_deps_T_79, 2, 0) node _pop_count_packed_deps_T_81 = add(_pop_count_packed_deps_T_74, _pop_count_packed_deps_T_80) node _pop_count_packed_deps_T_82 = bits(_pop_count_packed_deps_T_81, 3, 0) node _pop_count_packed_deps_T_83 = add(entries_ld[1].bits.deps_ex[8], entries_ld[1].bits.deps_ex[9]) node _pop_count_packed_deps_T_84 = bits(_pop_count_packed_deps_T_83, 1, 0) node _pop_count_packed_deps_T_85 = add(entries_ld[1].bits.deps_ex[10], entries_ld[1].bits.deps_ex[11]) node _pop_count_packed_deps_T_86 = bits(_pop_count_packed_deps_T_85, 1, 0) node _pop_count_packed_deps_T_87 = add(_pop_count_packed_deps_T_84, _pop_count_packed_deps_T_86) node _pop_count_packed_deps_T_88 = bits(_pop_count_packed_deps_T_87, 2, 0) node _pop_count_packed_deps_T_89 = add(entries_ld[1].bits.deps_ex[12], entries_ld[1].bits.deps_ex[13]) node _pop_count_packed_deps_T_90 = bits(_pop_count_packed_deps_T_89, 1, 0) node _pop_count_packed_deps_T_91 = add(entries_ld[1].bits.deps_ex[14], entries_ld[1].bits.deps_ex[15]) node _pop_count_packed_deps_T_92 = bits(_pop_count_packed_deps_T_91, 1, 0) node _pop_count_packed_deps_T_93 = add(_pop_count_packed_deps_T_90, _pop_count_packed_deps_T_92) node _pop_count_packed_deps_T_94 = bits(_pop_count_packed_deps_T_93, 2, 0) node _pop_count_packed_deps_T_95 = add(_pop_count_packed_deps_T_88, _pop_count_packed_deps_T_94) node _pop_count_packed_deps_T_96 = bits(_pop_count_packed_deps_T_95, 3, 0) node _pop_count_packed_deps_T_97 = add(_pop_count_packed_deps_T_82, _pop_count_packed_deps_T_96) node _pop_count_packed_deps_T_98 = bits(_pop_count_packed_deps_T_97, 4, 0) node _pop_count_packed_deps_T_99 = add(_pop_count_packed_deps_T_68, _pop_count_packed_deps_T_98) node _pop_count_packed_deps_T_100 = tail(_pop_count_packed_deps_T_99, 1) node _pop_count_packed_deps_T_101 = add(entries_ld[1].bits.deps_st[0], entries_ld[1].bits.deps_st[1]) node _pop_count_packed_deps_T_102 = bits(_pop_count_packed_deps_T_101, 1, 0) node _pop_count_packed_deps_T_103 = add(entries_ld[1].bits.deps_st[2], entries_ld[1].bits.deps_st[3]) node _pop_count_packed_deps_T_104 = bits(_pop_count_packed_deps_T_103, 1, 0) node _pop_count_packed_deps_T_105 = add(_pop_count_packed_deps_T_102, _pop_count_packed_deps_T_104) node _pop_count_packed_deps_T_106 = bits(_pop_count_packed_deps_T_105, 2, 0) node _pop_count_packed_deps_T_107 = add(_pop_count_packed_deps_T_100, _pop_count_packed_deps_T_106) node _pop_count_packed_deps_T_108 = tail(_pop_count_packed_deps_T_107, 1) node _pop_count_packed_deps_T_109 = mux(entries_ld[1].valid, _pop_count_packed_deps_T_108, UInt<1>(0h0)) node _pop_count_packed_deps_T_110 = add(entries_ld[2].bits.deps_ld[0], entries_ld[2].bits.deps_ld[1]) node _pop_count_packed_deps_T_111 = bits(_pop_count_packed_deps_T_110, 1, 0) node _pop_count_packed_deps_T_112 = add(entries_ld[2].bits.deps_ld[2], entries_ld[2].bits.deps_ld[3]) node _pop_count_packed_deps_T_113 = bits(_pop_count_packed_deps_T_112, 1, 0) node _pop_count_packed_deps_T_114 = add(_pop_count_packed_deps_T_111, _pop_count_packed_deps_T_113) node _pop_count_packed_deps_T_115 = bits(_pop_count_packed_deps_T_114, 2, 0) node _pop_count_packed_deps_T_116 = add(entries_ld[2].bits.deps_ld[4], entries_ld[2].bits.deps_ld[5]) node _pop_count_packed_deps_T_117 = bits(_pop_count_packed_deps_T_116, 1, 0) node _pop_count_packed_deps_T_118 = add(entries_ld[2].bits.deps_ld[6], entries_ld[2].bits.deps_ld[7]) node _pop_count_packed_deps_T_119 = bits(_pop_count_packed_deps_T_118, 1, 0) node _pop_count_packed_deps_T_120 = add(_pop_count_packed_deps_T_117, _pop_count_packed_deps_T_119) node _pop_count_packed_deps_T_121 = bits(_pop_count_packed_deps_T_120, 2, 0) node _pop_count_packed_deps_T_122 = add(_pop_count_packed_deps_T_115, _pop_count_packed_deps_T_121) node _pop_count_packed_deps_T_123 = bits(_pop_count_packed_deps_T_122, 3, 0) node _pop_count_packed_deps_T_124 = add(entries_ld[2].bits.deps_ex[0], entries_ld[2].bits.deps_ex[1]) node _pop_count_packed_deps_T_125 = bits(_pop_count_packed_deps_T_124, 1, 0) node _pop_count_packed_deps_T_126 = add(entries_ld[2].bits.deps_ex[2], entries_ld[2].bits.deps_ex[3]) node _pop_count_packed_deps_T_127 = bits(_pop_count_packed_deps_T_126, 1, 0) node _pop_count_packed_deps_T_128 = add(_pop_count_packed_deps_T_125, _pop_count_packed_deps_T_127) node _pop_count_packed_deps_T_129 = bits(_pop_count_packed_deps_T_128, 2, 0) node _pop_count_packed_deps_T_130 = add(entries_ld[2].bits.deps_ex[4], entries_ld[2].bits.deps_ex[5]) node _pop_count_packed_deps_T_131 = bits(_pop_count_packed_deps_T_130, 1, 0) node _pop_count_packed_deps_T_132 = add(entries_ld[2].bits.deps_ex[6], entries_ld[2].bits.deps_ex[7]) node _pop_count_packed_deps_T_133 = bits(_pop_count_packed_deps_T_132, 1, 0) node _pop_count_packed_deps_T_134 = add(_pop_count_packed_deps_T_131, _pop_count_packed_deps_T_133) node _pop_count_packed_deps_T_135 = bits(_pop_count_packed_deps_T_134, 2, 0) node _pop_count_packed_deps_T_136 = add(_pop_count_packed_deps_T_129, _pop_count_packed_deps_T_135) node _pop_count_packed_deps_T_137 = bits(_pop_count_packed_deps_T_136, 3, 0) node _pop_count_packed_deps_T_138 = add(entries_ld[2].bits.deps_ex[8], entries_ld[2].bits.deps_ex[9]) node _pop_count_packed_deps_T_139 = bits(_pop_count_packed_deps_T_138, 1, 0) node _pop_count_packed_deps_T_140 = add(entries_ld[2].bits.deps_ex[10], entries_ld[2].bits.deps_ex[11]) node _pop_count_packed_deps_T_141 = bits(_pop_count_packed_deps_T_140, 1, 0) node _pop_count_packed_deps_T_142 = add(_pop_count_packed_deps_T_139, _pop_count_packed_deps_T_141) node _pop_count_packed_deps_T_143 = bits(_pop_count_packed_deps_T_142, 2, 0) node _pop_count_packed_deps_T_144 = add(entries_ld[2].bits.deps_ex[12], entries_ld[2].bits.deps_ex[13]) node _pop_count_packed_deps_T_145 = bits(_pop_count_packed_deps_T_144, 1, 0) node _pop_count_packed_deps_T_146 = add(entries_ld[2].bits.deps_ex[14], entries_ld[2].bits.deps_ex[15]) node _pop_count_packed_deps_T_147 = bits(_pop_count_packed_deps_T_146, 1, 0) node _pop_count_packed_deps_T_148 = add(_pop_count_packed_deps_T_145, _pop_count_packed_deps_T_147) node _pop_count_packed_deps_T_149 = bits(_pop_count_packed_deps_T_148, 2, 0) node _pop_count_packed_deps_T_150 = add(_pop_count_packed_deps_T_143, _pop_count_packed_deps_T_149) node _pop_count_packed_deps_T_151 = bits(_pop_count_packed_deps_T_150, 3, 0) node _pop_count_packed_deps_T_152 = add(_pop_count_packed_deps_T_137, _pop_count_packed_deps_T_151) node _pop_count_packed_deps_T_153 = bits(_pop_count_packed_deps_T_152, 4, 0) node _pop_count_packed_deps_T_154 = add(_pop_count_packed_deps_T_123, _pop_count_packed_deps_T_153) node _pop_count_packed_deps_T_155 = tail(_pop_count_packed_deps_T_154, 1) node _pop_count_packed_deps_T_156 = add(entries_ld[2].bits.deps_st[0], entries_ld[2].bits.deps_st[1]) node _pop_count_packed_deps_T_157 = bits(_pop_count_packed_deps_T_156, 1, 0) node _pop_count_packed_deps_T_158 = add(entries_ld[2].bits.deps_st[2], entries_ld[2].bits.deps_st[3]) node _pop_count_packed_deps_T_159 = bits(_pop_count_packed_deps_T_158, 1, 0) node _pop_count_packed_deps_T_160 = add(_pop_count_packed_deps_T_157, _pop_count_packed_deps_T_159) node _pop_count_packed_deps_T_161 = bits(_pop_count_packed_deps_T_160, 2, 0) node _pop_count_packed_deps_T_162 = add(_pop_count_packed_deps_T_155, _pop_count_packed_deps_T_161) node _pop_count_packed_deps_T_163 = tail(_pop_count_packed_deps_T_162, 1) node _pop_count_packed_deps_T_164 = mux(entries_ld[2].valid, _pop_count_packed_deps_T_163, UInt<1>(0h0)) node _pop_count_packed_deps_T_165 = add(entries_ld[3].bits.deps_ld[0], entries_ld[3].bits.deps_ld[1]) node _pop_count_packed_deps_T_166 = bits(_pop_count_packed_deps_T_165, 1, 0) node _pop_count_packed_deps_T_167 = add(entries_ld[3].bits.deps_ld[2], entries_ld[3].bits.deps_ld[3]) node _pop_count_packed_deps_T_168 = bits(_pop_count_packed_deps_T_167, 1, 0) node _pop_count_packed_deps_T_169 = add(_pop_count_packed_deps_T_166, _pop_count_packed_deps_T_168) node _pop_count_packed_deps_T_170 = bits(_pop_count_packed_deps_T_169, 2, 0) node _pop_count_packed_deps_T_171 = add(entries_ld[3].bits.deps_ld[4], entries_ld[3].bits.deps_ld[5]) node _pop_count_packed_deps_T_172 = bits(_pop_count_packed_deps_T_171, 1, 0) node _pop_count_packed_deps_T_173 = add(entries_ld[3].bits.deps_ld[6], entries_ld[3].bits.deps_ld[7]) node _pop_count_packed_deps_T_174 = bits(_pop_count_packed_deps_T_173, 1, 0) node _pop_count_packed_deps_T_175 = add(_pop_count_packed_deps_T_172, _pop_count_packed_deps_T_174) node _pop_count_packed_deps_T_176 = bits(_pop_count_packed_deps_T_175, 2, 0) node _pop_count_packed_deps_T_177 = add(_pop_count_packed_deps_T_170, _pop_count_packed_deps_T_176) node _pop_count_packed_deps_T_178 = bits(_pop_count_packed_deps_T_177, 3, 0) node _pop_count_packed_deps_T_179 = add(entries_ld[3].bits.deps_ex[0], entries_ld[3].bits.deps_ex[1]) node _pop_count_packed_deps_T_180 = bits(_pop_count_packed_deps_T_179, 1, 0) node _pop_count_packed_deps_T_181 = add(entries_ld[3].bits.deps_ex[2], entries_ld[3].bits.deps_ex[3]) node _pop_count_packed_deps_T_182 = bits(_pop_count_packed_deps_T_181, 1, 0) node _pop_count_packed_deps_T_183 = add(_pop_count_packed_deps_T_180, _pop_count_packed_deps_T_182) node _pop_count_packed_deps_T_184 = bits(_pop_count_packed_deps_T_183, 2, 0) node _pop_count_packed_deps_T_185 = add(entries_ld[3].bits.deps_ex[4], entries_ld[3].bits.deps_ex[5]) node _pop_count_packed_deps_T_186 = bits(_pop_count_packed_deps_T_185, 1, 0) node _pop_count_packed_deps_T_187 = add(entries_ld[3].bits.deps_ex[6], entries_ld[3].bits.deps_ex[7]) node _pop_count_packed_deps_T_188 = bits(_pop_count_packed_deps_T_187, 1, 0) node _pop_count_packed_deps_T_189 = add(_pop_count_packed_deps_T_186, _pop_count_packed_deps_T_188) node _pop_count_packed_deps_T_190 = bits(_pop_count_packed_deps_T_189, 2, 0) node _pop_count_packed_deps_T_191 = add(_pop_count_packed_deps_T_184, _pop_count_packed_deps_T_190) node _pop_count_packed_deps_T_192 = bits(_pop_count_packed_deps_T_191, 3, 0) node _pop_count_packed_deps_T_193 = add(entries_ld[3].bits.deps_ex[8], entries_ld[3].bits.deps_ex[9]) node _pop_count_packed_deps_T_194 = bits(_pop_count_packed_deps_T_193, 1, 0) node _pop_count_packed_deps_T_195 = add(entries_ld[3].bits.deps_ex[10], entries_ld[3].bits.deps_ex[11]) node _pop_count_packed_deps_T_196 = bits(_pop_count_packed_deps_T_195, 1, 0) node _pop_count_packed_deps_T_197 = add(_pop_count_packed_deps_T_194, _pop_count_packed_deps_T_196) node _pop_count_packed_deps_T_198 = bits(_pop_count_packed_deps_T_197, 2, 0) node _pop_count_packed_deps_T_199 = add(entries_ld[3].bits.deps_ex[12], entries_ld[3].bits.deps_ex[13]) node _pop_count_packed_deps_T_200 = bits(_pop_count_packed_deps_T_199, 1, 0) node _pop_count_packed_deps_T_201 = add(entries_ld[3].bits.deps_ex[14], entries_ld[3].bits.deps_ex[15]) node _pop_count_packed_deps_T_202 = bits(_pop_count_packed_deps_T_201, 1, 0) node _pop_count_packed_deps_T_203 = add(_pop_count_packed_deps_T_200, _pop_count_packed_deps_T_202) node _pop_count_packed_deps_T_204 = bits(_pop_count_packed_deps_T_203, 2, 0) node _pop_count_packed_deps_T_205 = add(_pop_count_packed_deps_T_198, _pop_count_packed_deps_T_204) node _pop_count_packed_deps_T_206 = bits(_pop_count_packed_deps_T_205, 3, 0) node _pop_count_packed_deps_T_207 = add(_pop_count_packed_deps_T_192, _pop_count_packed_deps_T_206) node _pop_count_packed_deps_T_208 = bits(_pop_count_packed_deps_T_207, 4, 0) node _pop_count_packed_deps_T_209 = add(_pop_count_packed_deps_T_178, _pop_count_packed_deps_T_208) node _pop_count_packed_deps_T_210 = tail(_pop_count_packed_deps_T_209, 1) node _pop_count_packed_deps_T_211 = add(entries_ld[3].bits.deps_st[0], entries_ld[3].bits.deps_st[1]) node _pop_count_packed_deps_T_212 = bits(_pop_count_packed_deps_T_211, 1, 0) node _pop_count_packed_deps_T_213 = add(entries_ld[3].bits.deps_st[2], entries_ld[3].bits.deps_st[3]) node _pop_count_packed_deps_T_214 = bits(_pop_count_packed_deps_T_213, 1, 0) node _pop_count_packed_deps_T_215 = add(_pop_count_packed_deps_T_212, _pop_count_packed_deps_T_214) node _pop_count_packed_deps_T_216 = bits(_pop_count_packed_deps_T_215, 2, 0) node _pop_count_packed_deps_T_217 = add(_pop_count_packed_deps_T_210, _pop_count_packed_deps_T_216) node _pop_count_packed_deps_T_218 = tail(_pop_count_packed_deps_T_217, 1) node _pop_count_packed_deps_T_219 = mux(entries_ld[3].valid, _pop_count_packed_deps_T_218, UInt<1>(0h0)) node _pop_count_packed_deps_T_220 = add(entries_ld[4].bits.deps_ld[0], entries_ld[4].bits.deps_ld[1]) node _pop_count_packed_deps_T_221 = bits(_pop_count_packed_deps_T_220, 1, 0) node _pop_count_packed_deps_T_222 = add(entries_ld[4].bits.deps_ld[2], entries_ld[4].bits.deps_ld[3]) node _pop_count_packed_deps_T_223 = bits(_pop_count_packed_deps_T_222, 1, 0) node _pop_count_packed_deps_T_224 = add(_pop_count_packed_deps_T_221, _pop_count_packed_deps_T_223) node _pop_count_packed_deps_T_225 = bits(_pop_count_packed_deps_T_224, 2, 0) node _pop_count_packed_deps_T_226 = add(entries_ld[4].bits.deps_ld[4], entries_ld[4].bits.deps_ld[5]) node _pop_count_packed_deps_T_227 = bits(_pop_count_packed_deps_T_226, 1, 0) node _pop_count_packed_deps_T_228 = add(entries_ld[4].bits.deps_ld[6], entries_ld[4].bits.deps_ld[7]) node _pop_count_packed_deps_T_229 = bits(_pop_count_packed_deps_T_228, 1, 0) node _pop_count_packed_deps_T_230 = add(_pop_count_packed_deps_T_227, _pop_count_packed_deps_T_229) node _pop_count_packed_deps_T_231 = bits(_pop_count_packed_deps_T_230, 2, 0) node _pop_count_packed_deps_T_232 = add(_pop_count_packed_deps_T_225, _pop_count_packed_deps_T_231) node _pop_count_packed_deps_T_233 = bits(_pop_count_packed_deps_T_232, 3, 0) node _pop_count_packed_deps_T_234 = add(entries_ld[4].bits.deps_ex[0], entries_ld[4].bits.deps_ex[1]) node _pop_count_packed_deps_T_235 = bits(_pop_count_packed_deps_T_234, 1, 0) node _pop_count_packed_deps_T_236 = add(entries_ld[4].bits.deps_ex[2], entries_ld[4].bits.deps_ex[3]) node _pop_count_packed_deps_T_237 = bits(_pop_count_packed_deps_T_236, 1, 0) node _pop_count_packed_deps_T_238 = add(_pop_count_packed_deps_T_235, _pop_count_packed_deps_T_237) node _pop_count_packed_deps_T_239 = bits(_pop_count_packed_deps_T_238, 2, 0) node _pop_count_packed_deps_T_240 = add(entries_ld[4].bits.deps_ex[4], entries_ld[4].bits.deps_ex[5]) node _pop_count_packed_deps_T_241 = bits(_pop_count_packed_deps_T_240, 1, 0) node _pop_count_packed_deps_T_242 = add(entries_ld[4].bits.deps_ex[6], entries_ld[4].bits.deps_ex[7]) node _pop_count_packed_deps_T_243 = bits(_pop_count_packed_deps_T_242, 1, 0) node _pop_count_packed_deps_T_244 = add(_pop_count_packed_deps_T_241, _pop_count_packed_deps_T_243) node _pop_count_packed_deps_T_245 = bits(_pop_count_packed_deps_T_244, 2, 0) node _pop_count_packed_deps_T_246 = add(_pop_count_packed_deps_T_239, _pop_count_packed_deps_T_245) node _pop_count_packed_deps_T_247 = bits(_pop_count_packed_deps_T_246, 3, 0) node _pop_count_packed_deps_T_248 = add(entries_ld[4].bits.deps_ex[8], entries_ld[4].bits.deps_ex[9]) node _pop_count_packed_deps_T_249 = bits(_pop_count_packed_deps_T_248, 1, 0) node _pop_count_packed_deps_T_250 = add(entries_ld[4].bits.deps_ex[10], entries_ld[4].bits.deps_ex[11]) node _pop_count_packed_deps_T_251 = bits(_pop_count_packed_deps_T_250, 1, 0) node _pop_count_packed_deps_T_252 = add(_pop_count_packed_deps_T_249, _pop_count_packed_deps_T_251) node _pop_count_packed_deps_T_253 = bits(_pop_count_packed_deps_T_252, 2, 0) node _pop_count_packed_deps_T_254 = add(entries_ld[4].bits.deps_ex[12], entries_ld[4].bits.deps_ex[13]) node _pop_count_packed_deps_T_255 = bits(_pop_count_packed_deps_T_254, 1, 0) node _pop_count_packed_deps_T_256 = add(entries_ld[4].bits.deps_ex[14], entries_ld[4].bits.deps_ex[15]) node _pop_count_packed_deps_T_257 = bits(_pop_count_packed_deps_T_256, 1, 0) node _pop_count_packed_deps_T_258 = add(_pop_count_packed_deps_T_255, _pop_count_packed_deps_T_257) node _pop_count_packed_deps_T_259 = bits(_pop_count_packed_deps_T_258, 2, 0) node _pop_count_packed_deps_T_260 = add(_pop_count_packed_deps_T_253, _pop_count_packed_deps_T_259) node _pop_count_packed_deps_T_261 = bits(_pop_count_packed_deps_T_260, 3, 0) node _pop_count_packed_deps_T_262 = add(_pop_count_packed_deps_T_247, _pop_count_packed_deps_T_261) node _pop_count_packed_deps_T_263 = bits(_pop_count_packed_deps_T_262, 4, 0) node _pop_count_packed_deps_T_264 = add(_pop_count_packed_deps_T_233, _pop_count_packed_deps_T_263) node _pop_count_packed_deps_T_265 = tail(_pop_count_packed_deps_T_264, 1) node _pop_count_packed_deps_T_266 = add(entries_ld[4].bits.deps_st[0], entries_ld[4].bits.deps_st[1]) node _pop_count_packed_deps_T_267 = bits(_pop_count_packed_deps_T_266, 1, 0) node _pop_count_packed_deps_T_268 = add(entries_ld[4].bits.deps_st[2], entries_ld[4].bits.deps_st[3]) node _pop_count_packed_deps_T_269 = bits(_pop_count_packed_deps_T_268, 1, 0) node _pop_count_packed_deps_T_270 = add(_pop_count_packed_deps_T_267, _pop_count_packed_deps_T_269) node _pop_count_packed_deps_T_271 = bits(_pop_count_packed_deps_T_270, 2, 0) node _pop_count_packed_deps_T_272 = add(_pop_count_packed_deps_T_265, _pop_count_packed_deps_T_271) node _pop_count_packed_deps_T_273 = tail(_pop_count_packed_deps_T_272, 1) node _pop_count_packed_deps_T_274 = mux(entries_ld[4].valid, _pop_count_packed_deps_T_273, UInt<1>(0h0)) node _pop_count_packed_deps_T_275 = add(entries_ld[5].bits.deps_ld[0], entries_ld[5].bits.deps_ld[1]) node _pop_count_packed_deps_T_276 = bits(_pop_count_packed_deps_T_275, 1, 0) node _pop_count_packed_deps_T_277 = add(entries_ld[5].bits.deps_ld[2], entries_ld[5].bits.deps_ld[3]) node _pop_count_packed_deps_T_278 = bits(_pop_count_packed_deps_T_277, 1, 0) node _pop_count_packed_deps_T_279 = add(_pop_count_packed_deps_T_276, _pop_count_packed_deps_T_278) node _pop_count_packed_deps_T_280 = bits(_pop_count_packed_deps_T_279, 2, 0) node _pop_count_packed_deps_T_281 = add(entries_ld[5].bits.deps_ld[4], entries_ld[5].bits.deps_ld[5]) node _pop_count_packed_deps_T_282 = bits(_pop_count_packed_deps_T_281, 1, 0) node _pop_count_packed_deps_T_283 = add(entries_ld[5].bits.deps_ld[6], entries_ld[5].bits.deps_ld[7]) node _pop_count_packed_deps_T_284 = bits(_pop_count_packed_deps_T_283, 1, 0) node _pop_count_packed_deps_T_285 = add(_pop_count_packed_deps_T_282, _pop_count_packed_deps_T_284) node _pop_count_packed_deps_T_286 = bits(_pop_count_packed_deps_T_285, 2, 0) node _pop_count_packed_deps_T_287 = add(_pop_count_packed_deps_T_280, _pop_count_packed_deps_T_286) node _pop_count_packed_deps_T_288 = bits(_pop_count_packed_deps_T_287, 3, 0) node _pop_count_packed_deps_T_289 = add(entries_ld[5].bits.deps_ex[0], entries_ld[5].bits.deps_ex[1]) node _pop_count_packed_deps_T_290 = bits(_pop_count_packed_deps_T_289, 1, 0) node _pop_count_packed_deps_T_291 = add(entries_ld[5].bits.deps_ex[2], entries_ld[5].bits.deps_ex[3]) node _pop_count_packed_deps_T_292 = bits(_pop_count_packed_deps_T_291, 1, 0) node _pop_count_packed_deps_T_293 = add(_pop_count_packed_deps_T_290, _pop_count_packed_deps_T_292) node _pop_count_packed_deps_T_294 = bits(_pop_count_packed_deps_T_293, 2, 0) node _pop_count_packed_deps_T_295 = add(entries_ld[5].bits.deps_ex[4], entries_ld[5].bits.deps_ex[5]) node _pop_count_packed_deps_T_296 = bits(_pop_count_packed_deps_T_295, 1, 0) node _pop_count_packed_deps_T_297 = add(entries_ld[5].bits.deps_ex[6], entries_ld[5].bits.deps_ex[7]) node _pop_count_packed_deps_T_298 = bits(_pop_count_packed_deps_T_297, 1, 0) node _pop_count_packed_deps_T_299 = add(_pop_count_packed_deps_T_296, _pop_count_packed_deps_T_298) node _pop_count_packed_deps_T_300 = bits(_pop_count_packed_deps_T_299, 2, 0) node _pop_count_packed_deps_T_301 = add(_pop_count_packed_deps_T_294, _pop_count_packed_deps_T_300) node _pop_count_packed_deps_T_302 = bits(_pop_count_packed_deps_T_301, 3, 0) node _pop_count_packed_deps_T_303 = add(entries_ld[5].bits.deps_ex[8], entries_ld[5].bits.deps_ex[9]) node _pop_count_packed_deps_T_304 = bits(_pop_count_packed_deps_T_303, 1, 0) node _pop_count_packed_deps_T_305 = add(entries_ld[5].bits.deps_ex[10], entries_ld[5].bits.deps_ex[11]) node _pop_count_packed_deps_T_306 = bits(_pop_count_packed_deps_T_305, 1, 0) node _pop_count_packed_deps_T_307 = add(_pop_count_packed_deps_T_304, _pop_count_packed_deps_T_306) node _pop_count_packed_deps_T_308 = bits(_pop_count_packed_deps_T_307, 2, 0) node _pop_count_packed_deps_T_309 = add(entries_ld[5].bits.deps_ex[12], entries_ld[5].bits.deps_ex[13]) node _pop_count_packed_deps_T_310 = bits(_pop_count_packed_deps_T_309, 1, 0) node _pop_count_packed_deps_T_311 = add(entries_ld[5].bits.deps_ex[14], entries_ld[5].bits.deps_ex[15]) node _pop_count_packed_deps_T_312 = bits(_pop_count_packed_deps_T_311, 1, 0) node _pop_count_packed_deps_T_313 = add(_pop_count_packed_deps_T_310, _pop_count_packed_deps_T_312) node _pop_count_packed_deps_T_314 = bits(_pop_count_packed_deps_T_313, 2, 0) node _pop_count_packed_deps_T_315 = add(_pop_count_packed_deps_T_308, _pop_count_packed_deps_T_314) node _pop_count_packed_deps_T_316 = bits(_pop_count_packed_deps_T_315, 3, 0) node _pop_count_packed_deps_T_317 = add(_pop_count_packed_deps_T_302, _pop_count_packed_deps_T_316) node _pop_count_packed_deps_T_318 = bits(_pop_count_packed_deps_T_317, 4, 0) node _pop_count_packed_deps_T_319 = add(_pop_count_packed_deps_T_288, _pop_count_packed_deps_T_318) node _pop_count_packed_deps_T_320 = tail(_pop_count_packed_deps_T_319, 1) node _pop_count_packed_deps_T_321 = add(entries_ld[5].bits.deps_st[0], entries_ld[5].bits.deps_st[1]) node _pop_count_packed_deps_T_322 = bits(_pop_count_packed_deps_T_321, 1, 0) node _pop_count_packed_deps_T_323 = add(entries_ld[5].bits.deps_st[2], entries_ld[5].bits.deps_st[3]) node _pop_count_packed_deps_T_324 = bits(_pop_count_packed_deps_T_323, 1, 0) node _pop_count_packed_deps_T_325 = add(_pop_count_packed_deps_T_322, _pop_count_packed_deps_T_324) node _pop_count_packed_deps_T_326 = bits(_pop_count_packed_deps_T_325, 2, 0) node _pop_count_packed_deps_T_327 = add(_pop_count_packed_deps_T_320, _pop_count_packed_deps_T_326) node _pop_count_packed_deps_T_328 = tail(_pop_count_packed_deps_T_327, 1) node _pop_count_packed_deps_T_329 = mux(entries_ld[5].valid, _pop_count_packed_deps_T_328, UInt<1>(0h0)) node _pop_count_packed_deps_T_330 = add(entries_ld[6].bits.deps_ld[0], entries_ld[6].bits.deps_ld[1]) node _pop_count_packed_deps_T_331 = bits(_pop_count_packed_deps_T_330, 1, 0) node _pop_count_packed_deps_T_332 = add(entries_ld[6].bits.deps_ld[2], entries_ld[6].bits.deps_ld[3]) node _pop_count_packed_deps_T_333 = bits(_pop_count_packed_deps_T_332, 1, 0) node _pop_count_packed_deps_T_334 = add(_pop_count_packed_deps_T_331, _pop_count_packed_deps_T_333) node _pop_count_packed_deps_T_335 = bits(_pop_count_packed_deps_T_334, 2, 0) node _pop_count_packed_deps_T_336 = add(entries_ld[6].bits.deps_ld[4], entries_ld[6].bits.deps_ld[5]) node _pop_count_packed_deps_T_337 = bits(_pop_count_packed_deps_T_336, 1, 0) node _pop_count_packed_deps_T_338 = add(entries_ld[6].bits.deps_ld[6], entries_ld[6].bits.deps_ld[7]) node _pop_count_packed_deps_T_339 = bits(_pop_count_packed_deps_T_338, 1, 0) node _pop_count_packed_deps_T_340 = add(_pop_count_packed_deps_T_337, _pop_count_packed_deps_T_339) node _pop_count_packed_deps_T_341 = bits(_pop_count_packed_deps_T_340, 2, 0) node _pop_count_packed_deps_T_342 = add(_pop_count_packed_deps_T_335, _pop_count_packed_deps_T_341) node _pop_count_packed_deps_T_343 = bits(_pop_count_packed_deps_T_342, 3, 0) node _pop_count_packed_deps_T_344 = add(entries_ld[6].bits.deps_ex[0], entries_ld[6].bits.deps_ex[1]) node _pop_count_packed_deps_T_345 = bits(_pop_count_packed_deps_T_344, 1, 0) node _pop_count_packed_deps_T_346 = add(entries_ld[6].bits.deps_ex[2], entries_ld[6].bits.deps_ex[3]) node _pop_count_packed_deps_T_347 = bits(_pop_count_packed_deps_T_346, 1, 0) node _pop_count_packed_deps_T_348 = add(_pop_count_packed_deps_T_345, _pop_count_packed_deps_T_347) node _pop_count_packed_deps_T_349 = bits(_pop_count_packed_deps_T_348, 2, 0) node _pop_count_packed_deps_T_350 = add(entries_ld[6].bits.deps_ex[4], entries_ld[6].bits.deps_ex[5]) node _pop_count_packed_deps_T_351 = bits(_pop_count_packed_deps_T_350, 1, 0) node _pop_count_packed_deps_T_352 = add(entries_ld[6].bits.deps_ex[6], entries_ld[6].bits.deps_ex[7]) node _pop_count_packed_deps_T_353 = bits(_pop_count_packed_deps_T_352, 1, 0) node _pop_count_packed_deps_T_354 = add(_pop_count_packed_deps_T_351, _pop_count_packed_deps_T_353) node _pop_count_packed_deps_T_355 = bits(_pop_count_packed_deps_T_354, 2, 0) node _pop_count_packed_deps_T_356 = add(_pop_count_packed_deps_T_349, _pop_count_packed_deps_T_355) node _pop_count_packed_deps_T_357 = bits(_pop_count_packed_deps_T_356, 3, 0) node _pop_count_packed_deps_T_358 = add(entries_ld[6].bits.deps_ex[8], entries_ld[6].bits.deps_ex[9]) node _pop_count_packed_deps_T_359 = bits(_pop_count_packed_deps_T_358, 1, 0) node _pop_count_packed_deps_T_360 = add(entries_ld[6].bits.deps_ex[10], entries_ld[6].bits.deps_ex[11]) node _pop_count_packed_deps_T_361 = bits(_pop_count_packed_deps_T_360, 1, 0) node _pop_count_packed_deps_T_362 = add(_pop_count_packed_deps_T_359, _pop_count_packed_deps_T_361) node _pop_count_packed_deps_T_363 = bits(_pop_count_packed_deps_T_362, 2, 0) node _pop_count_packed_deps_T_364 = add(entries_ld[6].bits.deps_ex[12], entries_ld[6].bits.deps_ex[13]) node _pop_count_packed_deps_T_365 = bits(_pop_count_packed_deps_T_364, 1, 0) node _pop_count_packed_deps_T_366 = add(entries_ld[6].bits.deps_ex[14], entries_ld[6].bits.deps_ex[15]) node _pop_count_packed_deps_T_367 = bits(_pop_count_packed_deps_T_366, 1, 0) node _pop_count_packed_deps_T_368 = add(_pop_count_packed_deps_T_365, _pop_count_packed_deps_T_367) node _pop_count_packed_deps_T_369 = bits(_pop_count_packed_deps_T_368, 2, 0) node _pop_count_packed_deps_T_370 = add(_pop_count_packed_deps_T_363, _pop_count_packed_deps_T_369) node _pop_count_packed_deps_T_371 = bits(_pop_count_packed_deps_T_370, 3, 0) node _pop_count_packed_deps_T_372 = add(_pop_count_packed_deps_T_357, _pop_count_packed_deps_T_371) node _pop_count_packed_deps_T_373 = bits(_pop_count_packed_deps_T_372, 4, 0) node _pop_count_packed_deps_T_374 = add(_pop_count_packed_deps_T_343, _pop_count_packed_deps_T_373) node _pop_count_packed_deps_T_375 = tail(_pop_count_packed_deps_T_374, 1) node _pop_count_packed_deps_T_376 = add(entries_ld[6].bits.deps_st[0], entries_ld[6].bits.deps_st[1]) node _pop_count_packed_deps_T_377 = bits(_pop_count_packed_deps_T_376, 1, 0) node _pop_count_packed_deps_T_378 = add(entries_ld[6].bits.deps_st[2], entries_ld[6].bits.deps_st[3]) node _pop_count_packed_deps_T_379 = bits(_pop_count_packed_deps_T_378, 1, 0) node _pop_count_packed_deps_T_380 = add(_pop_count_packed_deps_T_377, _pop_count_packed_deps_T_379) node _pop_count_packed_deps_T_381 = bits(_pop_count_packed_deps_T_380, 2, 0) node _pop_count_packed_deps_T_382 = add(_pop_count_packed_deps_T_375, _pop_count_packed_deps_T_381) node _pop_count_packed_deps_T_383 = tail(_pop_count_packed_deps_T_382, 1) node _pop_count_packed_deps_T_384 = mux(entries_ld[6].valid, _pop_count_packed_deps_T_383, UInt<1>(0h0)) node _pop_count_packed_deps_T_385 = add(entries_ld[7].bits.deps_ld[0], entries_ld[7].bits.deps_ld[1]) node _pop_count_packed_deps_T_386 = bits(_pop_count_packed_deps_T_385, 1, 0) node _pop_count_packed_deps_T_387 = add(entries_ld[7].bits.deps_ld[2], entries_ld[7].bits.deps_ld[3]) node _pop_count_packed_deps_T_388 = bits(_pop_count_packed_deps_T_387, 1, 0) node _pop_count_packed_deps_T_389 = add(_pop_count_packed_deps_T_386, _pop_count_packed_deps_T_388) node _pop_count_packed_deps_T_390 = bits(_pop_count_packed_deps_T_389, 2, 0) node _pop_count_packed_deps_T_391 = add(entries_ld[7].bits.deps_ld[4], entries_ld[7].bits.deps_ld[5]) node _pop_count_packed_deps_T_392 = bits(_pop_count_packed_deps_T_391, 1, 0) node _pop_count_packed_deps_T_393 = add(entries_ld[7].bits.deps_ld[6], entries_ld[7].bits.deps_ld[7]) node _pop_count_packed_deps_T_394 = bits(_pop_count_packed_deps_T_393, 1, 0) node _pop_count_packed_deps_T_395 = add(_pop_count_packed_deps_T_392, _pop_count_packed_deps_T_394) node _pop_count_packed_deps_T_396 = bits(_pop_count_packed_deps_T_395, 2, 0) node _pop_count_packed_deps_T_397 = add(_pop_count_packed_deps_T_390, _pop_count_packed_deps_T_396) node _pop_count_packed_deps_T_398 = bits(_pop_count_packed_deps_T_397, 3, 0) node _pop_count_packed_deps_T_399 = add(entries_ld[7].bits.deps_ex[0], entries_ld[7].bits.deps_ex[1]) node _pop_count_packed_deps_T_400 = bits(_pop_count_packed_deps_T_399, 1, 0) node _pop_count_packed_deps_T_401 = add(entries_ld[7].bits.deps_ex[2], entries_ld[7].bits.deps_ex[3]) node _pop_count_packed_deps_T_402 = bits(_pop_count_packed_deps_T_401, 1, 0) node _pop_count_packed_deps_T_403 = add(_pop_count_packed_deps_T_400, _pop_count_packed_deps_T_402) node _pop_count_packed_deps_T_404 = bits(_pop_count_packed_deps_T_403, 2, 0) node _pop_count_packed_deps_T_405 = add(entries_ld[7].bits.deps_ex[4], entries_ld[7].bits.deps_ex[5]) node _pop_count_packed_deps_T_406 = bits(_pop_count_packed_deps_T_405, 1, 0) node _pop_count_packed_deps_T_407 = add(entries_ld[7].bits.deps_ex[6], entries_ld[7].bits.deps_ex[7]) node _pop_count_packed_deps_T_408 = bits(_pop_count_packed_deps_T_407, 1, 0) node _pop_count_packed_deps_T_409 = add(_pop_count_packed_deps_T_406, _pop_count_packed_deps_T_408) node _pop_count_packed_deps_T_410 = bits(_pop_count_packed_deps_T_409, 2, 0) node _pop_count_packed_deps_T_411 = add(_pop_count_packed_deps_T_404, _pop_count_packed_deps_T_410) node _pop_count_packed_deps_T_412 = bits(_pop_count_packed_deps_T_411, 3, 0) node _pop_count_packed_deps_T_413 = add(entries_ld[7].bits.deps_ex[8], entries_ld[7].bits.deps_ex[9]) node _pop_count_packed_deps_T_414 = bits(_pop_count_packed_deps_T_413, 1, 0) node _pop_count_packed_deps_T_415 = add(entries_ld[7].bits.deps_ex[10], entries_ld[7].bits.deps_ex[11]) node _pop_count_packed_deps_T_416 = bits(_pop_count_packed_deps_T_415, 1, 0) node _pop_count_packed_deps_T_417 = add(_pop_count_packed_deps_T_414, _pop_count_packed_deps_T_416) node _pop_count_packed_deps_T_418 = bits(_pop_count_packed_deps_T_417, 2, 0) node _pop_count_packed_deps_T_419 = add(entries_ld[7].bits.deps_ex[12], entries_ld[7].bits.deps_ex[13]) node _pop_count_packed_deps_T_420 = bits(_pop_count_packed_deps_T_419, 1, 0) node _pop_count_packed_deps_T_421 = add(entries_ld[7].bits.deps_ex[14], entries_ld[7].bits.deps_ex[15]) node _pop_count_packed_deps_T_422 = bits(_pop_count_packed_deps_T_421, 1, 0) node _pop_count_packed_deps_T_423 = add(_pop_count_packed_deps_T_420, _pop_count_packed_deps_T_422) node _pop_count_packed_deps_T_424 = bits(_pop_count_packed_deps_T_423, 2, 0) node _pop_count_packed_deps_T_425 = add(_pop_count_packed_deps_T_418, _pop_count_packed_deps_T_424) node _pop_count_packed_deps_T_426 = bits(_pop_count_packed_deps_T_425, 3, 0) node _pop_count_packed_deps_T_427 = add(_pop_count_packed_deps_T_412, _pop_count_packed_deps_T_426) node _pop_count_packed_deps_T_428 = bits(_pop_count_packed_deps_T_427, 4, 0) node _pop_count_packed_deps_T_429 = add(_pop_count_packed_deps_T_398, _pop_count_packed_deps_T_428) node _pop_count_packed_deps_T_430 = tail(_pop_count_packed_deps_T_429, 1) node _pop_count_packed_deps_T_431 = add(entries_ld[7].bits.deps_st[0], entries_ld[7].bits.deps_st[1]) node _pop_count_packed_deps_T_432 = bits(_pop_count_packed_deps_T_431, 1, 0) node _pop_count_packed_deps_T_433 = add(entries_ld[7].bits.deps_st[2], entries_ld[7].bits.deps_st[3]) node _pop_count_packed_deps_T_434 = bits(_pop_count_packed_deps_T_433, 1, 0) node _pop_count_packed_deps_T_435 = add(_pop_count_packed_deps_T_432, _pop_count_packed_deps_T_434) node _pop_count_packed_deps_T_436 = bits(_pop_count_packed_deps_T_435, 2, 0) node _pop_count_packed_deps_T_437 = add(_pop_count_packed_deps_T_430, _pop_count_packed_deps_T_436) node _pop_count_packed_deps_T_438 = tail(_pop_count_packed_deps_T_437, 1) node _pop_count_packed_deps_T_439 = mux(entries_ld[7].valid, _pop_count_packed_deps_T_438, UInt<1>(0h0)) node _pop_count_packed_deps_T_440 = add(entries_ex[0].bits.deps_ld[0], entries_ex[0].bits.deps_ld[1]) node _pop_count_packed_deps_T_441 = bits(_pop_count_packed_deps_T_440, 1, 0) node _pop_count_packed_deps_T_442 = add(entries_ex[0].bits.deps_ld[2], entries_ex[0].bits.deps_ld[3]) node _pop_count_packed_deps_T_443 = bits(_pop_count_packed_deps_T_442, 1, 0) node _pop_count_packed_deps_T_444 = add(_pop_count_packed_deps_T_441, _pop_count_packed_deps_T_443) node _pop_count_packed_deps_T_445 = bits(_pop_count_packed_deps_T_444, 2, 0) node _pop_count_packed_deps_T_446 = add(entries_ex[0].bits.deps_ld[4], entries_ex[0].bits.deps_ld[5]) node _pop_count_packed_deps_T_447 = bits(_pop_count_packed_deps_T_446, 1, 0) node _pop_count_packed_deps_T_448 = add(entries_ex[0].bits.deps_ld[6], entries_ex[0].bits.deps_ld[7]) node _pop_count_packed_deps_T_449 = bits(_pop_count_packed_deps_T_448, 1, 0) node _pop_count_packed_deps_T_450 = add(_pop_count_packed_deps_T_447, _pop_count_packed_deps_T_449) node _pop_count_packed_deps_T_451 = bits(_pop_count_packed_deps_T_450, 2, 0) node _pop_count_packed_deps_T_452 = add(_pop_count_packed_deps_T_445, _pop_count_packed_deps_T_451) node _pop_count_packed_deps_T_453 = bits(_pop_count_packed_deps_T_452, 3, 0) node _pop_count_packed_deps_T_454 = add(entries_ex[0].bits.deps_ex[0], entries_ex[0].bits.deps_ex[1]) node _pop_count_packed_deps_T_455 = bits(_pop_count_packed_deps_T_454, 1, 0) node _pop_count_packed_deps_T_456 = add(entries_ex[0].bits.deps_ex[2], entries_ex[0].bits.deps_ex[3]) node _pop_count_packed_deps_T_457 = bits(_pop_count_packed_deps_T_456, 1, 0) node _pop_count_packed_deps_T_458 = add(_pop_count_packed_deps_T_455, _pop_count_packed_deps_T_457) node _pop_count_packed_deps_T_459 = bits(_pop_count_packed_deps_T_458, 2, 0) node _pop_count_packed_deps_T_460 = add(entries_ex[0].bits.deps_ex[4], entries_ex[0].bits.deps_ex[5]) node _pop_count_packed_deps_T_461 = bits(_pop_count_packed_deps_T_460, 1, 0) node _pop_count_packed_deps_T_462 = add(entries_ex[0].bits.deps_ex[6], entries_ex[0].bits.deps_ex[7]) node _pop_count_packed_deps_T_463 = bits(_pop_count_packed_deps_T_462, 1, 0) node _pop_count_packed_deps_T_464 = add(_pop_count_packed_deps_T_461, _pop_count_packed_deps_T_463) node _pop_count_packed_deps_T_465 = bits(_pop_count_packed_deps_T_464, 2, 0) node _pop_count_packed_deps_T_466 = add(_pop_count_packed_deps_T_459, _pop_count_packed_deps_T_465) node _pop_count_packed_deps_T_467 = bits(_pop_count_packed_deps_T_466, 3, 0) node _pop_count_packed_deps_T_468 = add(entries_ex[0].bits.deps_ex[8], entries_ex[0].bits.deps_ex[9]) node _pop_count_packed_deps_T_469 = bits(_pop_count_packed_deps_T_468, 1, 0) node _pop_count_packed_deps_T_470 = add(entries_ex[0].bits.deps_ex[10], entries_ex[0].bits.deps_ex[11]) node _pop_count_packed_deps_T_471 = bits(_pop_count_packed_deps_T_470, 1, 0) node _pop_count_packed_deps_T_472 = add(_pop_count_packed_deps_T_469, _pop_count_packed_deps_T_471) node _pop_count_packed_deps_T_473 = bits(_pop_count_packed_deps_T_472, 2, 0) node _pop_count_packed_deps_T_474 = add(entries_ex[0].bits.deps_ex[12], entries_ex[0].bits.deps_ex[13]) node _pop_count_packed_deps_T_475 = bits(_pop_count_packed_deps_T_474, 1, 0) node _pop_count_packed_deps_T_476 = add(entries_ex[0].bits.deps_ex[14], entries_ex[0].bits.deps_ex[15]) node _pop_count_packed_deps_T_477 = bits(_pop_count_packed_deps_T_476, 1, 0) node _pop_count_packed_deps_T_478 = add(_pop_count_packed_deps_T_475, _pop_count_packed_deps_T_477) node _pop_count_packed_deps_T_479 = bits(_pop_count_packed_deps_T_478, 2, 0) node _pop_count_packed_deps_T_480 = add(_pop_count_packed_deps_T_473, _pop_count_packed_deps_T_479) node _pop_count_packed_deps_T_481 = bits(_pop_count_packed_deps_T_480, 3, 0) node _pop_count_packed_deps_T_482 = add(_pop_count_packed_deps_T_467, _pop_count_packed_deps_T_481) node _pop_count_packed_deps_T_483 = bits(_pop_count_packed_deps_T_482, 4, 0) node _pop_count_packed_deps_T_484 = add(_pop_count_packed_deps_T_453, _pop_count_packed_deps_T_483) node _pop_count_packed_deps_T_485 = tail(_pop_count_packed_deps_T_484, 1) node _pop_count_packed_deps_T_486 = add(entries_ex[0].bits.deps_st[0], entries_ex[0].bits.deps_st[1]) node _pop_count_packed_deps_T_487 = bits(_pop_count_packed_deps_T_486, 1, 0) node _pop_count_packed_deps_T_488 = add(entries_ex[0].bits.deps_st[2], entries_ex[0].bits.deps_st[3]) node _pop_count_packed_deps_T_489 = bits(_pop_count_packed_deps_T_488, 1, 0) node _pop_count_packed_deps_T_490 = add(_pop_count_packed_deps_T_487, _pop_count_packed_deps_T_489) node _pop_count_packed_deps_T_491 = bits(_pop_count_packed_deps_T_490, 2, 0) node _pop_count_packed_deps_T_492 = add(_pop_count_packed_deps_T_485, _pop_count_packed_deps_T_491) node _pop_count_packed_deps_T_493 = tail(_pop_count_packed_deps_T_492, 1) node _pop_count_packed_deps_T_494 = mux(entries_ex[0].valid, _pop_count_packed_deps_T_493, UInt<1>(0h0)) node _pop_count_packed_deps_T_495 = add(entries_ex[1].bits.deps_ld[0], entries_ex[1].bits.deps_ld[1]) node _pop_count_packed_deps_T_496 = bits(_pop_count_packed_deps_T_495, 1, 0) node _pop_count_packed_deps_T_497 = add(entries_ex[1].bits.deps_ld[2], entries_ex[1].bits.deps_ld[3]) node _pop_count_packed_deps_T_498 = bits(_pop_count_packed_deps_T_497, 1, 0) node _pop_count_packed_deps_T_499 = add(_pop_count_packed_deps_T_496, _pop_count_packed_deps_T_498) node _pop_count_packed_deps_T_500 = bits(_pop_count_packed_deps_T_499, 2, 0) node _pop_count_packed_deps_T_501 = add(entries_ex[1].bits.deps_ld[4], entries_ex[1].bits.deps_ld[5]) node _pop_count_packed_deps_T_502 = bits(_pop_count_packed_deps_T_501, 1, 0) node _pop_count_packed_deps_T_503 = add(entries_ex[1].bits.deps_ld[6], entries_ex[1].bits.deps_ld[7]) node _pop_count_packed_deps_T_504 = bits(_pop_count_packed_deps_T_503, 1, 0) node _pop_count_packed_deps_T_505 = add(_pop_count_packed_deps_T_502, _pop_count_packed_deps_T_504) node _pop_count_packed_deps_T_506 = bits(_pop_count_packed_deps_T_505, 2, 0) node _pop_count_packed_deps_T_507 = add(_pop_count_packed_deps_T_500, _pop_count_packed_deps_T_506) node _pop_count_packed_deps_T_508 = bits(_pop_count_packed_deps_T_507, 3, 0) node _pop_count_packed_deps_T_509 = add(entries_ex[1].bits.deps_ex[0], entries_ex[1].bits.deps_ex[1]) node _pop_count_packed_deps_T_510 = bits(_pop_count_packed_deps_T_509, 1, 0) node _pop_count_packed_deps_T_511 = add(entries_ex[1].bits.deps_ex[2], entries_ex[1].bits.deps_ex[3]) node _pop_count_packed_deps_T_512 = bits(_pop_count_packed_deps_T_511, 1, 0) node _pop_count_packed_deps_T_513 = add(_pop_count_packed_deps_T_510, _pop_count_packed_deps_T_512) node _pop_count_packed_deps_T_514 = bits(_pop_count_packed_deps_T_513, 2, 0) node _pop_count_packed_deps_T_515 = add(entries_ex[1].bits.deps_ex[4], entries_ex[1].bits.deps_ex[5]) node _pop_count_packed_deps_T_516 = bits(_pop_count_packed_deps_T_515, 1, 0) node _pop_count_packed_deps_T_517 = add(entries_ex[1].bits.deps_ex[6], entries_ex[1].bits.deps_ex[7]) node _pop_count_packed_deps_T_518 = bits(_pop_count_packed_deps_T_517, 1, 0) node _pop_count_packed_deps_T_519 = add(_pop_count_packed_deps_T_516, _pop_count_packed_deps_T_518) node _pop_count_packed_deps_T_520 = bits(_pop_count_packed_deps_T_519, 2, 0) node _pop_count_packed_deps_T_521 = add(_pop_count_packed_deps_T_514, _pop_count_packed_deps_T_520) node _pop_count_packed_deps_T_522 = bits(_pop_count_packed_deps_T_521, 3, 0) node _pop_count_packed_deps_T_523 = add(entries_ex[1].bits.deps_ex[8], entries_ex[1].bits.deps_ex[9]) node _pop_count_packed_deps_T_524 = bits(_pop_count_packed_deps_T_523, 1, 0) node _pop_count_packed_deps_T_525 = add(entries_ex[1].bits.deps_ex[10], entries_ex[1].bits.deps_ex[11]) node _pop_count_packed_deps_T_526 = bits(_pop_count_packed_deps_T_525, 1, 0) node _pop_count_packed_deps_T_527 = add(_pop_count_packed_deps_T_524, _pop_count_packed_deps_T_526) node _pop_count_packed_deps_T_528 = bits(_pop_count_packed_deps_T_527, 2, 0) node _pop_count_packed_deps_T_529 = add(entries_ex[1].bits.deps_ex[12], entries_ex[1].bits.deps_ex[13]) node _pop_count_packed_deps_T_530 = bits(_pop_count_packed_deps_T_529, 1, 0) node _pop_count_packed_deps_T_531 = add(entries_ex[1].bits.deps_ex[14], entries_ex[1].bits.deps_ex[15]) node _pop_count_packed_deps_T_532 = bits(_pop_count_packed_deps_T_531, 1, 0) node _pop_count_packed_deps_T_533 = add(_pop_count_packed_deps_T_530, _pop_count_packed_deps_T_532) node _pop_count_packed_deps_T_534 = bits(_pop_count_packed_deps_T_533, 2, 0) node _pop_count_packed_deps_T_535 = add(_pop_count_packed_deps_T_528, _pop_count_packed_deps_T_534) node _pop_count_packed_deps_T_536 = bits(_pop_count_packed_deps_T_535, 3, 0) node _pop_count_packed_deps_T_537 = add(_pop_count_packed_deps_T_522, _pop_count_packed_deps_T_536) node _pop_count_packed_deps_T_538 = bits(_pop_count_packed_deps_T_537, 4, 0) node _pop_count_packed_deps_T_539 = add(_pop_count_packed_deps_T_508, _pop_count_packed_deps_T_538) node _pop_count_packed_deps_T_540 = tail(_pop_count_packed_deps_T_539, 1) node _pop_count_packed_deps_T_541 = add(entries_ex[1].bits.deps_st[0], entries_ex[1].bits.deps_st[1]) node _pop_count_packed_deps_T_542 = bits(_pop_count_packed_deps_T_541, 1, 0) node _pop_count_packed_deps_T_543 = add(entries_ex[1].bits.deps_st[2], entries_ex[1].bits.deps_st[3]) node _pop_count_packed_deps_T_544 = bits(_pop_count_packed_deps_T_543, 1, 0) node _pop_count_packed_deps_T_545 = add(_pop_count_packed_deps_T_542, _pop_count_packed_deps_T_544) node _pop_count_packed_deps_T_546 = bits(_pop_count_packed_deps_T_545, 2, 0) node _pop_count_packed_deps_T_547 = add(_pop_count_packed_deps_T_540, _pop_count_packed_deps_T_546) node _pop_count_packed_deps_T_548 = tail(_pop_count_packed_deps_T_547, 1) node _pop_count_packed_deps_T_549 = mux(entries_ex[1].valid, _pop_count_packed_deps_T_548, UInt<1>(0h0)) node _pop_count_packed_deps_T_550 = add(entries_ex[2].bits.deps_ld[0], entries_ex[2].bits.deps_ld[1]) node _pop_count_packed_deps_T_551 = bits(_pop_count_packed_deps_T_550, 1, 0) node _pop_count_packed_deps_T_552 = add(entries_ex[2].bits.deps_ld[2], entries_ex[2].bits.deps_ld[3]) node _pop_count_packed_deps_T_553 = bits(_pop_count_packed_deps_T_552, 1, 0) node _pop_count_packed_deps_T_554 = add(_pop_count_packed_deps_T_551, _pop_count_packed_deps_T_553) node _pop_count_packed_deps_T_555 = bits(_pop_count_packed_deps_T_554, 2, 0) node _pop_count_packed_deps_T_556 = add(entries_ex[2].bits.deps_ld[4], entries_ex[2].bits.deps_ld[5]) node _pop_count_packed_deps_T_557 = bits(_pop_count_packed_deps_T_556, 1, 0) node _pop_count_packed_deps_T_558 = add(entries_ex[2].bits.deps_ld[6], entries_ex[2].bits.deps_ld[7]) node _pop_count_packed_deps_T_559 = bits(_pop_count_packed_deps_T_558, 1, 0) node _pop_count_packed_deps_T_560 = add(_pop_count_packed_deps_T_557, _pop_count_packed_deps_T_559) node _pop_count_packed_deps_T_561 = bits(_pop_count_packed_deps_T_560, 2, 0) node _pop_count_packed_deps_T_562 = add(_pop_count_packed_deps_T_555, _pop_count_packed_deps_T_561) node _pop_count_packed_deps_T_563 = bits(_pop_count_packed_deps_T_562, 3, 0) node _pop_count_packed_deps_T_564 = add(entries_ex[2].bits.deps_ex[0], entries_ex[2].bits.deps_ex[1]) node _pop_count_packed_deps_T_565 = bits(_pop_count_packed_deps_T_564, 1, 0) node _pop_count_packed_deps_T_566 = add(entries_ex[2].bits.deps_ex[2], entries_ex[2].bits.deps_ex[3]) node _pop_count_packed_deps_T_567 = bits(_pop_count_packed_deps_T_566, 1, 0) node _pop_count_packed_deps_T_568 = add(_pop_count_packed_deps_T_565, _pop_count_packed_deps_T_567) node _pop_count_packed_deps_T_569 = bits(_pop_count_packed_deps_T_568, 2, 0) node _pop_count_packed_deps_T_570 = add(entries_ex[2].bits.deps_ex[4], entries_ex[2].bits.deps_ex[5]) node _pop_count_packed_deps_T_571 = bits(_pop_count_packed_deps_T_570, 1, 0) node _pop_count_packed_deps_T_572 = add(entries_ex[2].bits.deps_ex[6], entries_ex[2].bits.deps_ex[7]) node _pop_count_packed_deps_T_573 = bits(_pop_count_packed_deps_T_572, 1, 0) node _pop_count_packed_deps_T_574 = add(_pop_count_packed_deps_T_571, _pop_count_packed_deps_T_573) node _pop_count_packed_deps_T_575 = bits(_pop_count_packed_deps_T_574, 2, 0) node _pop_count_packed_deps_T_576 = add(_pop_count_packed_deps_T_569, _pop_count_packed_deps_T_575) node _pop_count_packed_deps_T_577 = bits(_pop_count_packed_deps_T_576, 3, 0) node _pop_count_packed_deps_T_578 = add(entries_ex[2].bits.deps_ex[8], entries_ex[2].bits.deps_ex[9]) node _pop_count_packed_deps_T_579 = bits(_pop_count_packed_deps_T_578, 1, 0) node _pop_count_packed_deps_T_580 = add(entries_ex[2].bits.deps_ex[10], entries_ex[2].bits.deps_ex[11]) node _pop_count_packed_deps_T_581 = bits(_pop_count_packed_deps_T_580, 1, 0) node _pop_count_packed_deps_T_582 = add(_pop_count_packed_deps_T_579, _pop_count_packed_deps_T_581) node _pop_count_packed_deps_T_583 = bits(_pop_count_packed_deps_T_582, 2, 0) node _pop_count_packed_deps_T_584 = add(entries_ex[2].bits.deps_ex[12], entries_ex[2].bits.deps_ex[13]) node _pop_count_packed_deps_T_585 = bits(_pop_count_packed_deps_T_584, 1, 0) node _pop_count_packed_deps_T_586 = add(entries_ex[2].bits.deps_ex[14], entries_ex[2].bits.deps_ex[15]) node _pop_count_packed_deps_T_587 = bits(_pop_count_packed_deps_T_586, 1, 0) node _pop_count_packed_deps_T_588 = add(_pop_count_packed_deps_T_585, _pop_count_packed_deps_T_587) node _pop_count_packed_deps_T_589 = bits(_pop_count_packed_deps_T_588, 2, 0) node _pop_count_packed_deps_T_590 = add(_pop_count_packed_deps_T_583, _pop_count_packed_deps_T_589) node _pop_count_packed_deps_T_591 = bits(_pop_count_packed_deps_T_590, 3, 0) node _pop_count_packed_deps_T_592 = add(_pop_count_packed_deps_T_577, _pop_count_packed_deps_T_591) node _pop_count_packed_deps_T_593 = bits(_pop_count_packed_deps_T_592, 4, 0) node _pop_count_packed_deps_T_594 = add(_pop_count_packed_deps_T_563, _pop_count_packed_deps_T_593) node _pop_count_packed_deps_T_595 = tail(_pop_count_packed_deps_T_594, 1) node _pop_count_packed_deps_T_596 = add(entries_ex[2].bits.deps_st[0], entries_ex[2].bits.deps_st[1]) node _pop_count_packed_deps_T_597 = bits(_pop_count_packed_deps_T_596, 1, 0) node _pop_count_packed_deps_T_598 = add(entries_ex[2].bits.deps_st[2], entries_ex[2].bits.deps_st[3]) node _pop_count_packed_deps_T_599 = bits(_pop_count_packed_deps_T_598, 1, 0) node _pop_count_packed_deps_T_600 = add(_pop_count_packed_deps_T_597, _pop_count_packed_deps_T_599) node _pop_count_packed_deps_T_601 = bits(_pop_count_packed_deps_T_600, 2, 0) node _pop_count_packed_deps_T_602 = add(_pop_count_packed_deps_T_595, _pop_count_packed_deps_T_601) node _pop_count_packed_deps_T_603 = tail(_pop_count_packed_deps_T_602, 1) node _pop_count_packed_deps_T_604 = mux(entries_ex[2].valid, _pop_count_packed_deps_T_603, UInt<1>(0h0)) node _pop_count_packed_deps_T_605 = add(entries_ex[3].bits.deps_ld[0], entries_ex[3].bits.deps_ld[1]) node _pop_count_packed_deps_T_606 = bits(_pop_count_packed_deps_T_605, 1, 0) node _pop_count_packed_deps_T_607 = add(entries_ex[3].bits.deps_ld[2], entries_ex[3].bits.deps_ld[3]) node _pop_count_packed_deps_T_608 = bits(_pop_count_packed_deps_T_607, 1, 0) node _pop_count_packed_deps_T_609 = add(_pop_count_packed_deps_T_606, _pop_count_packed_deps_T_608) node _pop_count_packed_deps_T_610 = bits(_pop_count_packed_deps_T_609, 2, 0) node _pop_count_packed_deps_T_611 = add(entries_ex[3].bits.deps_ld[4], entries_ex[3].bits.deps_ld[5]) node _pop_count_packed_deps_T_612 = bits(_pop_count_packed_deps_T_611, 1, 0) node _pop_count_packed_deps_T_613 = add(entries_ex[3].bits.deps_ld[6], entries_ex[3].bits.deps_ld[7]) node _pop_count_packed_deps_T_614 = bits(_pop_count_packed_deps_T_613, 1, 0) node _pop_count_packed_deps_T_615 = add(_pop_count_packed_deps_T_612, _pop_count_packed_deps_T_614) node _pop_count_packed_deps_T_616 = bits(_pop_count_packed_deps_T_615, 2, 0) node _pop_count_packed_deps_T_617 = add(_pop_count_packed_deps_T_610, _pop_count_packed_deps_T_616) node _pop_count_packed_deps_T_618 = bits(_pop_count_packed_deps_T_617, 3, 0) node _pop_count_packed_deps_T_619 = add(entries_ex[3].bits.deps_ex[0], entries_ex[3].bits.deps_ex[1]) node _pop_count_packed_deps_T_620 = bits(_pop_count_packed_deps_T_619, 1, 0) node _pop_count_packed_deps_T_621 = add(entries_ex[3].bits.deps_ex[2], entries_ex[3].bits.deps_ex[3]) node _pop_count_packed_deps_T_622 = bits(_pop_count_packed_deps_T_621, 1, 0) node _pop_count_packed_deps_T_623 = add(_pop_count_packed_deps_T_620, _pop_count_packed_deps_T_622) node _pop_count_packed_deps_T_624 = bits(_pop_count_packed_deps_T_623, 2, 0) node _pop_count_packed_deps_T_625 = add(entries_ex[3].bits.deps_ex[4], entries_ex[3].bits.deps_ex[5]) node _pop_count_packed_deps_T_626 = bits(_pop_count_packed_deps_T_625, 1, 0) node _pop_count_packed_deps_T_627 = add(entries_ex[3].bits.deps_ex[6], entries_ex[3].bits.deps_ex[7]) node _pop_count_packed_deps_T_628 = bits(_pop_count_packed_deps_T_627, 1, 0) node _pop_count_packed_deps_T_629 = add(_pop_count_packed_deps_T_626, _pop_count_packed_deps_T_628) node _pop_count_packed_deps_T_630 = bits(_pop_count_packed_deps_T_629, 2, 0) node _pop_count_packed_deps_T_631 = add(_pop_count_packed_deps_T_624, _pop_count_packed_deps_T_630) node _pop_count_packed_deps_T_632 = bits(_pop_count_packed_deps_T_631, 3, 0) node _pop_count_packed_deps_T_633 = add(entries_ex[3].bits.deps_ex[8], entries_ex[3].bits.deps_ex[9]) node _pop_count_packed_deps_T_634 = bits(_pop_count_packed_deps_T_633, 1, 0) node _pop_count_packed_deps_T_635 = add(entries_ex[3].bits.deps_ex[10], entries_ex[3].bits.deps_ex[11]) node _pop_count_packed_deps_T_636 = bits(_pop_count_packed_deps_T_635, 1, 0) node _pop_count_packed_deps_T_637 = add(_pop_count_packed_deps_T_634, _pop_count_packed_deps_T_636) node _pop_count_packed_deps_T_638 = bits(_pop_count_packed_deps_T_637, 2, 0) node _pop_count_packed_deps_T_639 = add(entries_ex[3].bits.deps_ex[12], entries_ex[3].bits.deps_ex[13]) node _pop_count_packed_deps_T_640 = bits(_pop_count_packed_deps_T_639, 1, 0) node _pop_count_packed_deps_T_641 = add(entries_ex[3].bits.deps_ex[14], entries_ex[3].bits.deps_ex[15]) node _pop_count_packed_deps_T_642 = bits(_pop_count_packed_deps_T_641, 1, 0) node _pop_count_packed_deps_T_643 = add(_pop_count_packed_deps_T_640, _pop_count_packed_deps_T_642) node _pop_count_packed_deps_T_644 = bits(_pop_count_packed_deps_T_643, 2, 0) node _pop_count_packed_deps_T_645 = add(_pop_count_packed_deps_T_638, _pop_count_packed_deps_T_644) node _pop_count_packed_deps_T_646 = bits(_pop_count_packed_deps_T_645, 3, 0) node _pop_count_packed_deps_T_647 = add(_pop_count_packed_deps_T_632, _pop_count_packed_deps_T_646) node _pop_count_packed_deps_T_648 = bits(_pop_count_packed_deps_T_647, 4, 0) node _pop_count_packed_deps_T_649 = add(_pop_count_packed_deps_T_618, _pop_count_packed_deps_T_648) node _pop_count_packed_deps_T_650 = tail(_pop_count_packed_deps_T_649, 1) node _pop_count_packed_deps_T_651 = add(entries_ex[3].bits.deps_st[0], entries_ex[3].bits.deps_st[1]) node _pop_count_packed_deps_T_652 = bits(_pop_count_packed_deps_T_651, 1, 0) node _pop_count_packed_deps_T_653 = add(entries_ex[3].bits.deps_st[2], entries_ex[3].bits.deps_st[3]) node _pop_count_packed_deps_T_654 = bits(_pop_count_packed_deps_T_653, 1, 0) node _pop_count_packed_deps_T_655 = add(_pop_count_packed_deps_T_652, _pop_count_packed_deps_T_654) node _pop_count_packed_deps_T_656 = bits(_pop_count_packed_deps_T_655, 2, 0) node _pop_count_packed_deps_T_657 = add(_pop_count_packed_deps_T_650, _pop_count_packed_deps_T_656) node _pop_count_packed_deps_T_658 = tail(_pop_count_packed_deps_T_657, 1) node _pop_count_packed_deps_T_659 = mux(entries_ex[3].valid, _pop_count_packed_deps_T_658, UInt<1>(0h0)) node _pop_count_packed_deps_T_660 = add(entries_ex[4].bits.deps_ld[0], entries_ex[4].bits.deps_ld[1]) node _pop_count_packed_deps_T_661 = bits(_pop_count_packed_deps_T_660, 1, 0) node _pop_count_packed_deps_T_662 = add(entries_ex[4].bits.deps_ld[2], entries_ex[4].bits.deps_ld[3]) node _pop_count_packed_deps_T_663 = bits(_pop_count_packed_deps_T_662, 1, 0) node _pop_count_packed_deps_T_664 = add(_pop_count_packed_deps_T_661, _pop_count_packed_deps_T_663) node _pop_count_packed_deps_T_665 = bits(_pop_count_packed_deps_T_664, 2, 0) node _pop_count_packed_deps_T_666 = add(entries_ex[4].bits.deps_ld[4], entries_ex[4].bits.deps_ld[5]) node _pop_count_packed_deps_T_667 = bits(_pop_count_packed_deps_T_666, 1, 0) node _pop_count_packed_deps_T_668 = add(entries_ex[4].bits.deps_ld[6], entries_ex[4].bits.deps_ld[7]) node _pop_count_packed_deps_T_669 = bits(_pop_count_packed_deps_T_668, 1, 0) node _pop_count_packed_deps_T_670 = add(_pop_count_packed_deps_T_667, _pop_count_packed_deps_T_669) node _pop_count_packed_deps_T_671 = bits(_pop_count_packed_deps_T_670, 2, 0) node _pop_count_packed_deps_T_672 = add(_pop_count_packed_deps_T_665, _pop_count_packed_deps_T_671) node _pop_count_packed_deps_T_673 = bits(_pop_count_packed_deps_T_672, 3, 0) node _pop_count_packed_deps_T_674 = add(entries_ex[4].bits.deps_ex[0], entries_ex[4].bits.deps_ex[1]) node _pop_count_packed_deps_T_675 = bits(_pop_count_packed_deps_T_674, 1, 0) node _pop_count_packed_deps_T_676 = add(entries_ex[4].bits.deps_ex[2], entries_ex[4].bits.deps_ex[3]) node _pop_count_packed_deps_T_677 = bits(_pop_count_packed_deps_T_676, 1, 0) node _pop_count_packed_deps_T_678 = add(_pop_count_packed_deps_T_675, _pop_count_packed_deps_T_677) node _pop_count_packed_deps_T_679 = bits(_pop_count_packed_deps_T_678, 2, 0) node _pop_count_packed_deps_T_680 = add(entries_ex[4].bits.deps_ex[4], entries_ex[4].bits.deps_ex[5]) node _pop_count_packed_deps_T_681 = bits(_pop_count_packed_deps_T_680, 1, 0) node _pop_count_packed_deps_T_682 = add(entries_ex[4].bits.deps_ex[6], entries_ex[4].bits.deps_ex[7]) node _pop_count_packed_deps_T_683 = bits(_pop_count_packed_deps_T_682, 1, 0) node _pop_count_packed_deps_T_684 = add(_pop_count_packed_deps_T_681, _pop_count_packed_deps_T_683) node _pop_count_packed_deps_T_685 = bits(_pop_count_packed_deps_T_684, 2, 0) node _pop_count_packed_deps_T_686 = add(_pop_count_packed_deps_T_679, _pop_count_packed_deps_T_685) node _pop_count_packed_deps_T_687 = bits(_pop_count_packed_deps_T_686, 3, 0) node _pop_count_packed_deps_T_688 = add(entries_ex[4].bits.deps_ex[8], entries_ex[4].bits.deps_ex[9]) node _pop_count_packed_deps_T_689 = bits(_pop_count_packed_deps_T_688, 1, 0) node _pop_count_packed_deps_T_690 = add(entries_ex[4].bits.deps_ex[10], entries_ex[4].bits.deps_ex[11]) node _pop_count_packed_deps_T_691 = bits(_pop_count_packed_deps_T_690, 1, 0) node _pop_count_packed_deps_T_692 = add(_pop_count_packed_deps_T_689, _pop_count_packed_deps_T_691) node _pop_count_packed_deps_T_693 = bits(_pop_count_packed_deps_T_692, 2, 0) node _pop_count_packed_deps_T_694 = add(entries_ex[4].bits.deps_ex[12], entries_ex[4].bits.deps_ex[13]) node _pop_count_packed_deps_T_695 = bits(_pop_count_packed_deps_T_694, 1, 0) node _pop_count_packed_deps_T_696 = add(entries_ex[4].bits.deps_ex[14], entries_ex[4].bits.deps_ex[15]) node _pop_count_packed_deps_T_697 = bits(_pop_count_packed_deps_T_696, 1, 0) node _pop_count_packed_deps_T_698 = add(_pop_count_packed_deps_T_695, _pop_count_packed_deps_T_697) node _pop_count_packed_deps_T_699 = bits(_pop_count_packed_deps_T_698, 2, 0) node _pop_count_packed_deps_T_700 = add(_pop_count_packed_deps_T_693, _pop_count_packed_deps_T_699) node _pop_count_packed_deps_T_701 = bits(_pop_count_packed_deps_T_700, 3, 0) node _pop_count_packed_deps_T_702 = add(_pop_count_packed_deps_T_687, _pop_count_packed_deps_T_701) node _pop_count_packed_deps_T_703 = bits(_pop_count_packed_deps_T_702, 4, 0) node _pop_count_packed_deps_T_704 = add(_pop_count_packed_deps_T_673, _pop_count_packed_deps_T_703) node _pop_count_packed_deps_T_705 = tail(_pop_count_packed_deps_T_704, 1) node _pop_count_packed_deps_T_706 = add(entries_ex[4].bits.deps_st[0], entries_ex[4].bits.deps_st[1]) node _pop_count_packed_deps_T_707 = bits(_pop_count_packed_deps_T_706, 1, 0) node _pop_count_packed_deps_T_708 = add(entries_ex[4].bits.deps_st[2], entries_ex[4].bits.deps_st[3]) node _pop_count_packed_deps_T_709 = bits(_pop_count_packed_deps_T_708, 1, 0) node _pop_count_packed_deps_T_710 = add(_pop_count_packed_deps_T_707, _pop_count_packed_deps_T_709) node _pop_count_packed_deps_T_711 = bits(_pop_count_packed_deps_T_710, 2, 0) node _pop_count_packed_deps_T_712 = add(_pop_count_packed_deps_T_705, _pop_count_packed_deps_T_711) node _pop_count_packed_deps_T_713 = tail(_pop_count_packed_deps_T_712, 1) node _pop_count_packed_deps_T_714 = mux(entries_ex[4].valid, _pop_count_packed_deps_T_713, UInt<1>(0h0)) node _pop_count_packed_deps_T_715 = add(entries_ex[5].bits.deps_ld[0], entries_ex[5].bits.deps_ld[1]) node _pop_count_packed_deps_T_716 = bits(_pop_count_packed_deps_T_715, 1, 0) node _pop_count_packed_deps_T_717 = add(entries_ex[5].bits.deps_ld[2], entries_ex[5].bits.deps_ld[3]) node _pop_count_packed_deps_T_718 = bits(_pop_count_packed_deps_T_717, 1, 0) node _pop_count_packed_deps_T_719 = add(_pop_count_packed_deps_T_716, _pop_count_packed_deps_T_718) node _pop_count_packed_deps_T_720 = bits(_pop_count_packed_deps_T_719, 2, 0) node _pop_count_packed_deps_T_721 = add(entries_ex[5].bits.deps_ld[4], entries_ex[5].bits.deps_ld[5]) node _pop_count_packed_deps_T_722 = bits(_pop_count_packed_deps_T_721, 1, 0) node _pop_count_packed_deps_T_723 = add(entries_ex[5].bits.deps_ld[6], entries_ex[5].bits.deps_ld[7]) node _pop_count_packed_deps_T_724 = bits(_pop_count_packed_deps_T_723, 1, 0) node _pop_count_packed_deps_T_725 = add(_pop_count_packed_deps_T_722, _pop_count_packed_deps_T_724) node _pop_count_packed_deps_T_726 = bits(_pop_count_packed_deps_T_725, 2, 0) node _pop_count_packed_deps_T_727 = add(_pop_count_packed_deps_T_720, _pop_count_packed_deps_T_726) node _pop_count_packed_deps_T_728 = bits(_pop_count_packed_deps_T_727, 3, 0) node _pop_count_packed_deps_T_729 = add(entries_ex[5].bits.deps_ex[0], entries_ex[5].bits.deps_ex[1]) node _pop_count_packed_deps_T_730 = bits(_pop_count_packed_deps_T_729, 1, 0) node _pop_count_packed_deps_T_731 = add(entries_ex[5].bits.deps_ex[2], entries_ex[5].bits.deps_ex[3]) node _pop_count_packed_deps_T_732 = bits(_pop_count_packed_deps_T_731, 1, 0) node _pop_count_packed_deps_T_733 = add(_pop_count_packed_deps_T_730, _pop_count_packed_deps_T_732) node _pop_count_packed_deps_T_734 = bits(_pop_count_packed_deps_T_733, 2, 0) node _pop_count_packed_deps_T_735 = add(entries_ex[5].bits.deps_ex[4], entries_ex[5].bits.deps_ex[5]) node _pop_count_packed_deps_T_736 = bits(_pop_count_packed_deps_T_735, 1, 0) node _pop_count_packed_deps_T_737 = add(entries_ex[5].bits.deps_ex[6], entries_ex[5].bits.deps_ex[7]) node _pop_count_packed_deps_T_738 = bits(_pop_count_packed_deps_T_737, 1, 0) node _pop_count_packed_deps_T_739 = add(_pop_count_packed_deps_T_736, _pop_count_packed_deps_T_738) node _pop_count_packed_deps_T_740 = bits(_pop_count_packed_deps_T_739, 2, 0) node _pop_count_packed_deps_T_741 = add(_pop_count_packed_deps_T_734, _pop_count_packed_deps_T_740) node _pop_count_packed_deps_T_742 = bits(_pop_count_packed_deps_T_741, 3, 0) node _pop_count_packed_deps_T_743 = add(entries_ex[5].bits.deps_ex[8], entries_ex[5].bits.deps_ex[9]) node _pop_count_packed_deps_T_744 = bits(_pop_count_packed_deps_T_743, 1, 0) node _pop_count_packed_deps_T_745 = add(entries_ex[5].bits.deps_ex[10], entries_ex[5].bits.deps_ex[11]) node _pop_count_packed_deps_T_746 = bits(_pop_count_packed_deps_T_745, 1, 0) node _pop_count_packed_deps_T_747 = add(_pop_count_packed_deps_T_744, _pop_count_packed_deps_T_746) node _pop_count_packed_deps_T_748 = bits(_pop_count_packed_deps_T_747, 2, 0) node _pop_count_packed_deps_T_749 = add(entries_ex[5].bits.deps_ex[12], entries_ex[5].bits.deps_ex[13]) node _pop_count_packed_deps_T_750 = bits(_pop_count_packed_deps_T_749, 1, 0) node _pop_count_packed_deps_T_751 = add(entries_ex[5].bits.deps_ex[14], entries_ex[5].bits.deps_ex[15]) node _pop_count_packed_deps_T_752 = bits(_pop_count_packed_deps_T_751, 1, 0) node _pop_count_packed_deps_T_753 = add(_pop_count_packed_deps_T_750, _pop_count_packed_deps_T_752) node _pop_count_packed_deps_T_754 = bits(_pop_count_packed_deps_T_753, 2, 0) node _pop_count_packed_deps_T_755 = add(_pop_count_packed_deps_T_748, _pop_count_packed_deps_T_754) node _pop_count_packed_deps_T_756 = bits(_pop_count_packed_deps_T_755, 3, 0) node _pop_count_packed_deps_T_757 = add(_pop_count_packed_deps_T_742, _pop_count_packed_deps_T_756) node _pop_count_packed_deps_T_758 = bits(_pop_count_packed_deps_T_757, 4, 0) node _pop_count_packed_deps_T_759 = add(_pop_count_packed_deps_T_728, _pop_count_packed_deps_T_758) node _pop_count_packed_deps_T_760 = tail(_pop_count_packed_deps_T_759, 1) node _pop_count_packed_deps_T_761 = add(entries_ex[5].bits.deps_st[0], entries_ex[5].bits.deps_st[1]) node _pop_count_packed_deps_T_762 = bits(_pop_count_packed_deps_T_761, 1, 0) node _pop_count_packed_deps_T_763 = add(entries_ex[5].bits.deps_st[2], entries_ex[5].bits.deps_st[3]) node _pop_count_packed_deps_T_764 = bits(_pop_count_packed_deps_T_763, 1, 0) node _pop_count_packed_deps_T_765 = add(_pop_count_packed_deps_T_762, _pop_count_packed_deps_T_764) node _pop_count_packed_deps_T_766 = bits(_pop_count_packed_deps_T_765, 2, 0) node _pop_count_packed_deps_T_767 = add(_pop_count_packed_deps_T_760, _pop_count_packed_deps_T_766) node _pop_count_packed_deps_T_768 = tail(_pop_count_packed_deps_T_767, 1) node _pop_count_packed_deps_T_769 = mux(entries_ex[5].valid, _pop_count_packed_deps_T_768, UInt<1>(0h0)) node _pop_count_packed_deps_T_770 = add(entries_ex[6].bits.deps_ld[0], entries_ex[6].bits.deps_ld[1]) node _pop_count_packed_deps_T_771 = bits(_pop_count_packed_deps_T_770, 1, 0) node _pop_count_packed_deps_T_772 = add(entries_ex[6].bits.deps_ld[2], entries_ex[6].bits.deps_ld[3]) node _pop_count_packed_deps_T_773 = bits(_pop_count_packed_deps_T_772, 1, 0) node _pop_count_packed_deps_T_774 = add(_pop_count_packed_deps_T_771, _pop_count_packed_deps_T_773) node _pop_count_packed_deps_T_775 = bits(_pop_count_packed_deps_T_774, 2, 0) node _pop_count_packed_deps_T_776 = add(entries_ex[6].bits.deps_ld[4], entries_ex[6].bits.deps_ld[5]) node _pop_count_packed_deps_T_777 = bits(_pop_count_packed_deps_T_776, 1, 0) node _pop_count_packed_deps_T_778 = add(entries_ex[6].bits.deps_ld[6], entries_ex[6].bits.deps_ld[7]) node _pop_count_packed_deps_T_779 = bits(_pop_count_packed_deps_T_778, 1, 0) node _pop_count_packed_deps_T_780 = add(_pop_count_packed_deps_T_777, _pop_count_packed_deps_T_779) node _pop_count_packed_deps_T_781 = bits(_pop_count_packed_deps_T_780, 2, 0) node _pop_count_packed_deps_T_782 = add(_pop_count_packed_deps_T_775, _pop_count_packed_deps_T_781) node _pop_count_packed_deps_T_783 = bits(_pop_count_packed_deps_T_782, 3, 0) node _pop_count_packed_deps_T_784 = add(entries_ex[6].bits.deps_ex[0], entries_ex[6].bits.deps_ex[1]) node _pop_count_packed_deps_T_785 = bits(_pop_count_packed_deps_T_784, 1, 0) node _pop_count_packed_deps_T_786 = add(entries_ex[6].bits.deps_ex[2], entries_ex[6].bits.deps_ex[3]) node _pop_count_packed_deps_T_787 = bits(_pop_count_packed_deps_T_786, 1, 0) node _pop_count_packed_deps_T_788 = add(_pop_count_packed_deps_T_785, _pop_count_packed_deps_T_787) node _pop_count_packed_deps_T_789 = bits(_pop_count_packed_deps_T_788, 2, 0) node _pop_count_packed_deps_T_790 = add(entries_ex[6].bits.deps_ex[4], entries_ex[6].bits.deps_ex[5]) node _pop_count_packed_deps_T_791 = bits(_pop_count_packed_deps_T_790, 1, 0) node _pop_count_packed_deps_T_792 = add(entries_ex[6].bits.deps_ex[6], entries_ex[6].bits.deps_ex[7]) node _pop_count_packed_deps_T_793 = bits(_pop_count_packed_deps_T_792, 1, 0) node _pop_count_packed_deps_T_794 = add(_pop_count_packed_deps_T_791, _pop_count_packed_deps_T_793) node _pop_count_packed_deps_T_795 = bits(_pop_count_packed_deps_T_794, 2, 0) node _pop_count_packed_deps_T_796 = add(_pop_count_packed_deps_T_789, _pop_count_packed_deps_T_795) node _pop_count_packed_deps_T_797 = bits(_pop_count_packed_deps_T_796, 3, 0) node _pop_count_packed_deps_T_798 = add(entries_ex[6].bits.deps_ex[8], entries_ex[6].bits.deps_ex[9]) node _pop_count_packed_deps_T_799 = bits(_pop_count_packed_deps_T_798, 1, 0) node _pop_count_packed_deps_T_800 = add(entries_ex[6].bits.deps_ex[10], entries_ex[6].bits.deps_ex[11]) node _pop_count_packed_deps_T_801 = bits(_pop_count_packed_deps_T_800, 1, 0) node _pop_count_packed_deps_T_802 = add(_pop_count_packed_deps_T_799, _pop_count_packed_deps_T_801) node _pop_count_packed_deps_T_803 = bits(_pop_count_packed_deps_T_802, 2, 0) node _pop_count_packed_deps_T_804 = add(entries_ex[6].bits.deps_ex[12], entries_ex[6].bits.deps_ex[13]) node _pop_count_packed_deps_T_805 = bits(_pop_count_packed_deps_T_804, 1, 0) node _pop_count_packed_deps_T_806 = add(entries_ex[6].bits.deps_ex[14], entries_ex[6].bits.deps_ex[15]) node _pop_count_packed_deps_T_807 = bits(_pop_count_packed_deps_T_806, 1, 0) node _pop_count_packed_deps_T_808 = add(_pop_count_packed_deps_T_805, _pop_count_packed_deps_T_807) node _pop_count_packed_deps_T_809 = bits(_pop_count_packed_deps_T_808, 2, 0) node _pop_count_packed_deps_T_810 = add(_pop_count_packed_deps_T_803, _pop_count_packed_deps_T_809) node _pop_count_packed_deps_T_811 = bits(_pop_count_packed_deps_T_810, 3, 0) node _pop_count_packed_deps_T_812 = add(_pop_count_packed_deps_T_797, _pop_count_packed_deps_T_811) node _pop_count_packed_deps_T_813 = bits(_pop_count_packed_deps_T_812, 4, 0) node _pop_count_packed_deps_T_814 = add(_pop_count_packed_deps_T_783, _pop_count_packed_deps_T_813) node _pop_count_packed_deps_T_815 = tail(_pop_count_packed_deps_T_814, 1) node _pop_count_packed_deps_T_816 = add(entries_ex[6].bits.deps_st[0], entries_ex[6].bits.deps_st[1]) node _pop_count_packed_deps_T_817 = bits(_pop_count_packed_deps_T_816, 1, 0) node _pop_count_packed_deps_T_818 = add(entries_ex[6].bits.deps_st[2], entries_ex[6].bits.deps_st[3]) node _pop_count_packed_deps_T_819 = bits(_pop_count_packed_deps_T_818, 1, 0) node _pop_count_packed_deps_T_820 = add(_pop_count_packed_deps_T_817, _pop_count_packed_deps_T_819) node _pop_count_packed_deps_T_821 = bits(_pop_count_packed_deps_T_820, 2, 0) node _pop_count_packed_deps_T_822 = add(_pop_count_packed_deps_T_815, _pop_count_packed_deps_T_821) node _pop_count_packed_deps_T_823 = tail(_pop_count_packed_deps_T_822, 1) node _pop_count_packed_deps_T_824 = mux(entries_ex[6].valid, _pop_count_packed_deps_T_823, UInt<1>(0h0)) node _pop_count_packed_deps_T_825 = add(entries_ex[7].bits.deps_ld[0], entries_ex[7].bits.deps_ld[1]) node _pop_count_packed_deps_T_826 = bits(_pop_count_packed_deps_T_825, 1, 0) node _pop_count_packed_deps_T_827 = add(entries_ex[7].bits.deps_ld[2], entries_ex[7].bits.deps_ld[3]) node _pop_count_packed_deps_T_828 = bits(_pop_count_packed_deps_T_827, 1, 0) node _pop_count_packed_deps_T_829 = add(_pop_count_packed_deps_T_826, _pop_count_packed_deps_T_828) node _pop_count_packed_deps_T_830 = bits(_pop_count_packed_deps_T_829, 2, 0) node _pop_count_packed_deps_T_831 = add(entries_ex[7].bits.deps_ld[4], entries_ex[7].bits.deps_ld[5]) node _pop_count_packed_deps_T_832 = bits(_pop_count_packed_deps_T_831, 1, 0) node _pop_count_packed_deps_T_833 = add(entries_ex[7].bits.deps_ld[6], entries_ex[7].bits.deps_ld[7]) node _pop_count_packed_deps_T_834 = bits(_pop_count_packed_deps_T_833, 1, 0) node _pop_count_packed_deps_T_835 = add(_pop_count_packed_deps_T_832, _pop_count_packed_deps_T_834) node _pop_count_packed_deps_T_836 = bits(_pop_count_packed_deps_T_835, 2, 0) node _pop_count_packed_deps_T_837 = add(_pop_count_packed_deps_T_830, _pop_count_packed_deps_T_836) node _pop_count_packed_deps_T_838 = bits(_pop_count_packed_deps_T_837, 3, 0) node _pop_count_packed_deps_T_839 = add(entries_ex[7].bits.deps_ex[0], entries_ex[7].bits.deps_ex[1]) node _pop_count_packed_deps_T_840 = bits(_pop_count_packed_deps_T_839, 1, 0) node _pop_count_packed_deps_T_841 = add(entries_ex[7].bits.deps_ex[2], entries_ex[7].bits.deps_ex[3]) node _pop_count_packed_deps_T_842 = bits(_pop_count_packed_deps_T_841, 1, 0) node _pop_count_packed_deps_T_843 = add(_pop_count_packed_deps_T_840, _pop_count_packed_deps_T_842) node _pop_count_packed_deps_T_844 = bits(_pop_count_packed_deps_T_843, 2, 0) node _pop_count_packed_deps_T_845 = add(entries_ex[7].bits.deps_ex[4], entries_ex[7].bits.deps_ex[5]) node _pop_count_packed_deps_T_846 = bits(_pop_count_packed_deps_T_845, 1, 0) node _pop_count_packed_deps_T_847 = add(entries_ex[7].bits.deps_ex[6], entries_ex[7].bits.deps_ex[7]) node _pop_count_packed_deps_T_848 = bits(_pop_count_packed_deps_T_847, 1, 0) node _pop_count_packed_deps_T_849 = add(_pop_count_packed_deps_T_846, _pop_count_packed_deps_T_848) node _pop_count_packed_deps_T_850 = bits(_pop_count_packed_deps_T_849, 2, 0) node _pop_count_packed_deps_T_851 = add(_pop_count_packed_deps_T_844, _pop_count_packed_deps_T_850) node _pop_count_packed_deps_T_852 = bits(_pop_count_packed_deps_T_851, 3, 0) node _pop_count_packed_deps_T_853 = add(entries_ex[7].bits.deps_ex[8], entries_ex[7].bits.deps_ex[9]) node _pop_count_packed_deps_T_854 = bits(_pop_count_packed_deps_T_853, 1, 0) node _pop_count_packed_deps_T_855 = add(entries_ex[7].bits.deps_ex[10], entries_ex[7].bits.deps_ex[11]) node _pop_count_packed_deps_T_856 = bits(_pop_count_packed_deps_T_855, 1, 0) node _pop_count_packed_deps_T_857 = add(_pop_count_packed_deps_T_854, _pop_count_packed_deps_T_856) node _pop_count_packed_deps_T_858 = bits(_pop_count_packed_deps_T_857, 2, 0) node _pop_count_packed_deps_T_859 = add(entries_ex[7].bits.deps_ex[12], entries_ex[7].bits.deps_ex[13]) node _pop_count_packed_deps_T_860 = bits(_pop_count_packed_deps_T_859, 1, 0) node _pop_count_packed_deps_T_861 = add(entries_ex[7].bits.deps_ex[14], entries_ex[7].bits.deps_ex[15]) node _pop_count_packed_deps_T_862 = bits(_pop_count_packed_deps_T_861, 1, 0) node _pop_count_packed_deps_T_863 = add(_pop_count_packed_deps_T_860, _pop_count_packed_deps_T_862) node _pop_count_packed_deps_T_864 = bits(_pop_count_packed_deps_T_863, 2, 0) node _pop_count_packed_deps_T_865 = add(_pop_count_packed_deps_T_858, _pop_count_packed_deps_T_864) node _pop_count_packed_deps_T_866 = bits(_pop_count_packed_deps_T_865, 3, 0) node _pop_count_packed_deps_T_867 = add(_pop_count_packed_deps_T_852, _pop_count_packed_deps_T_866) node _pop_count_packed_deps_T_868 = bits(_pop_count_packed_deps_T_867, 4, 0) node _pop_count_packed_deps_T_869 = add(_pop_count_packed_deps_T_838, _pop_count_packed_deps_T_868) node _pop_count_packed_deps_T_870 = tail(_pop_count_packed_deps_T_869, 1) node _pop_count_packed_deps_T_871 = add(entries_ex[7].bits.deps_st[0], entries_ex[7].bits.deps_st[1]) node _pop_count_packed_deps_T_872 = bits(_pop_count_packed_deps_T_871, 1, 0) node _pop_count_packed_deps_T_873 = add(entries_ex[7].bits.deps_st[2], entries_ex[7].bits.deps_st[3]) node _pop_count_packed_deps_T_874 = bits(_pop_count_packed_deps_T_873, 1, 0) node _pop_count_packed_deps_T_875 = add(_pop_count_packed_deps_T_872, _pop_count_packed_deps_T_874) node _pop_count_packed_deps_T_876 = bits(_pop_count_packed_deps_T_875, 2, 0) node _pop_count_packed_deps_T_877 = add(_pop_count_packed_deps_T_870, _pop_count_packed_deps_T_876) node _pop_count_packed_deps_T_878 = tail(_pop_count_packed_deps_T_877, 1) node _pop_count_packed_deps_T_879 = mux(entries_ex[7].valid, _pop_count_packed_deps_T_878, UInt<1>(0h0)) node _pop_count_packed_deps_T_880 = add(entries_ex[8].bits.deps_ld[0], entries_ex[8].bits.deps_ld[1]) node _pop_count_packed_deps_T_881 = bits(_pop_count_packed_deps_T_880, 1, 0) node _pop_count_packed_deps_T_882 = add(entries_ex[8].bits.deps_ld[2], entries_ex[8].bits.deps_ld[3]) node _pop_count_packed_deps_T_883 = bits(_pop_count_packed_deps_T_882, 1, 0) node _pop_count_packed_deps_T_884 = add(_pop_count_packed_deps_T_881, _pop_count_packed_deps_T_883) node _pop_count_packed_deps_T_885 = bits(_pop_count_packed_deps_T_884, 2, 0) node _pop_count_packed_deps_T_886 = add(entries_ex[8].bits.deps_ld[4], entries_ex[8].bits.deps_ld[5]) node _pop_count_packed_deps_T_887 = bits(_pop_count_packed_deps_T_886, 1, 0) node _pop_count_packed_deps_T_888 = add(entries_ex[8].bits.deps_ld[6], entries_ex[8].bits.deps_ld[7]) node _pop_count_packed_deps_T_889 = bits(_pop_count_packed_deps_T_888, 1, 0) node _pop_count_packed_deps_T_890 = add(_pop_count_packed_deps_T_887, _pop_count_packed_deps_T_889) node _pop_count_packed_deps_T_891 = bits(_pop_count_packed_deps_T_890, 2, 0) node _pop_count_packed_deps_T_892 = add(_pop_count_packed_deps_T_885, _pop_count_packed_deps_T_891) node _pop_count_packed_deps_T_893 = bits(_pop_count_packed_deps_T_892, 3, 0) node _pop_count_packed_deps_T_894 = add(entries_ex[8].bits.deps_ex[0], entries_ex[8].bits.deps_ex[1]) node _pop_count_packed_deps_T_895 = bits(_pop_count_packed_deps_T_894, 1, 0) node _pop_count_packed_deps_T_896 = add(entries_ex[8].bits.deps_ex[2], entries_ex[8].bits.deps_ex[3]) node _pop_count_packed_deps_T_897 = bits(_pop_count_packed_deps_T_896, 1, 0) node _pop_count_packed_deps_T_898 = add(_pop_count_packed_deps_T_895, _pop_count_packed_deps_T_897) node _pop_count_packed_deps_T_899 = bits(_pop_count_packed_deps_T_898, 2, 0) node _pop_count_packed_deps_T_900 = add(entries_ex[8].bits.deps_ex[4], entries_ex[8].bits.deps_ex[5]) node _pop_count_packed_deps_T_901 = bits(_pop_count_packed_deps_T_900, 1, 0) node _pop_count_packed_deps_T_902 = add(entries_ex[8].bits.deps_ex[6], entries_ex[8].bits.deps_ex[7]) node _pop_count_packed_deps_T_903 = bits(_pop_count_packed_deps_T_902, 1, 0) node _pop_count_packed_deps_T_904 = add(_pop_count_packed_deps_T_901, _pop_count_packed_deps_T_903) node _pop_count_packed_deps_T_905 = bits(_pop_count_packed_deps_T_904, 2, 0) node _pop_count_packed_deps_T_906 = add(_pop_count_packed_deps_T_899, _pop_count_packed_deps_T_905) node _pop_count_packed_deps_T_907 = bits(_pop_count_packed_deps_T_906, 3, 0) node _pop_count_packed_deps_T_908 = add(entries_ex[8].bits.deps_ex[8], entries_ex[8].bits.deps_ex[9]) node _pop_count_packed_deps_T_909 = bits(_pop_count_packed_deps_T_908, 1, 0) node _pop_count_packed_deps_T_910 = add(entries_ex[8].bits.deps_ex[10], entries_ex[8].bits.deps_ex[11]) node _pop_count_packed_deps_T_911 = bits(_pop_count_packed_deps_T_910, 1, 0) node _pop_count_packed_deps_T_912 = add(_pop_count_packed_deps_T_909, _pop_count_packed_deps_T_911) node _pop_count_packed_deps_T_913 = bits(_pop_count_packed_deps_T_912, 2, 0) node _pop_count_packed_deps_T_914 = add(entries_ex[8].bits.deps_ex[12], entries_ex[8].bits.deps_ex[13]) node _pop_count_packed_deps_T_915 = bits(_pop_count_packed_deps_T_914, 1, 0) node _pop_count_packed_deps_T_916 = add(entries_ex[8].bits.deps_ex[14], entries_ex[8].bits.deps_ex[15]) node _pop_count_packed_deps_T_917 = bits(_pop_count_packed_deps_T_916, 1, 0) node _pop_count_packed_deps_T_918 = add(_pop_count_packed_deps_T_915, _pop_count_packed_deps_T_917) node _pop_count_packed_deps_T_919 = bits(_pop_count_packed_deps_T_918, 2, 0) node _pop_count_packed_deps_T_920 = add(_pop_count_packed_deps_T_913, _pop_count_packed_deps_T_919) node _pop_count_packed_deps_T_921 = bits(_pop_count_packed_deps_T_920, 3, 0) node _pop_count_packed_deps_T_922 = add(_pop_count_packed_deps_T_907, _pop_count_packed_deps_T_921) node _pop_count_packed_deps_T_923 = bits(_pop_count_packed_deps_T_922, 4, 0) node _pop_count_packed_deps_T_924 = add(_pop_count_packed_deps_T_893, _pop_count_packed_deps_T_923) node _pop_count_packed_deps_T_925 = tail(_pop_count_packed_deps_T_924, 1) node _pop_count_packed_deps_T_926 = add(entries_ex[8].bits.deps_st[0], entries_ex[8].bits.deps_st[1]) node _pop_count_packed_deps_T_927 = bits(_pop_count_packed_deps_T_926, 1, 0) node _pop_count_packed_deps_T_928 = add(entries_ex[8].bits.deps_st[2], entries_ex[8].bits.deps_st[3]) node _pop_count_packed_deps_T_929 = bits(_pop_count_packed_deps_T_928, 1, 0) node _pop_count_packed_deps_T_930 = add(_pop_count_packed_deps_T_927, _pop_count_packed_deps_T_929) node _pop_count_packed_deps_T_931 = bits(_pop_count_packed_deps_T_930, 2, 0) node _pop_count_packed_deps_T_932 = add(_pop_count_packed_deps_T_925, _pop_count_packed_deps_T_931) node _pop_count_packed_deps_T_933 = tail(_pop_count_packed_deps_T_932, 1) node _pop_count_packed_deps_T_934 = mux(entries_ex[8].valid, _pop_count_packed_deps_T_933, UInt<1>(0h0)) node _pop_count_packed_deps_T_935 = add(entries_ex[9].bits.deps_ld[0], entries_ex[9].bits.deps_ld[1]) node _pop_count_packed_deps_T_936 = bits(_pop_count_packed_deps_T_935, 1, 0) node _pop_count_packed_deps_T_937 = add(entries_ex[9].bits.deps_ld[2], entries_ex[9].bits.deps_ld[3]) node _pop_count_packed_deps_T_938 = bits(_pop_count_packed_deps_T_937, 1, 0) node _pop_count_packed_deps_T_939 = add(_pop_count_packed_deps_T_936, _pop_count_packed_deps_T_938) node _pop_count_packed_deps_T_940 = bits(_pop_count_packed_deps_T_939, 2, 0) node _pop_count_packed_deps_T_941 = add(entries_ex[9].bits.deps_ld[4], entries_ex[9].bits.deps_ld[5]) node _pop_count_packed_deps_T_942 = bits(_pop_count_packed_deps_T_941, 1, 0) node _pop_count_packed_deps_T_943 = add(entries_ex[9].bits.deps_ld[6], entries_ex[9].bits.deps_ld[7]) node _pop_count_packed_deps_T_944 = bits(_pop_count_packed_deps_T_943, 1, 0) node _pop_count_packed_deps_T_945 = add(_pop_count_packed_deps_T_942, _pop_count_packed_deps_T_944) node _pop_count_packed_deps_T_946 = bits(_pop_count_packed_deps_T_945, 2, 0) node _pop_count_packed_deps_T_947 = add(_pop_count_packed_deps_T_940, _pop_count_packed_deps_T_946) node _pop_count_packed_deps_T_948 = bits(_pop_count_packed_deps_T_947, 3, 0) node _pop_count_packed_deps_T_949 = add(entries_ex[9].bits.deps_ex[0], entries_ex[9].bits.deps_ex[1]) node _pop_count_packed_deps_T_950 = bits(_pop_count_packed_deps_T_949, 1, 0) node _pop_count_packed_deps_T_951 = add(entries_ex[9].bits.deps_ex[2], entries_ex[9].bits.deps_ex[3]) node _pop_count_packed_deps_T_952 = bits(_pop_count_packed_deps_T_951, 1, 0) node _pop_count_packed_deps_T_953 = add(_pop_count_packed_deps_T_950, _pop_count_packed_deps_T_952) node _pop_count_packed_deps_T_954 = bits(_pop_count_packed_deps_T_953, 2, 0) node _pop_count_packed_deps_T_955 = add(entries_ex[9].bits.deps_ex[4], entries_ex[9].bits.deps_ex[5]) node _pop_count_packed_deps_T_956 = bits(_pop_count_packed_deps_T_955, 1, 0) node _pop_count_packed_deps_T_957 = add(entries_ex[9].bits.deps_ex[6], entries_ex[9].bits.deps_ex[7]) node _pop_count_packed_deps_T_958 = bits(_pop_count_packed_deps_T_957, 1, 0) node _pop_count_packed_deps_T_959 = add(_pop_count_packed_deps_T_956, _pop_count_packed_deps_T_958) node _pop_count_packed_deps_T_960 = bits(_pop_count_packed_deps_T_959, 2, 0) node _pop_count_packed_deps_T_961 = add(_pop_count_packed_deps_T_954, _pop_count_packed_deps_T_960) node _pop_count_packed_deps_T_962 = bits(_pop_count_packed_deps_T_961, 3, 0) node _pop_count_packed_deps_T_963 = add(entries_ex[9].bits.deps_ex[8], entries_ex[9].bits.deps_ex[9]) node _pop_count_packed_deps_T_964 = bits(_pop_count_packed_deps_T_963, 1, 0) node _pop_count_packed_deps_T_965 = add(entries_ex[9].bits.deps_ex[10], entries_ex[9].bits.deps_ex[11]) node _pop_count_packed_deps_T_966 = bits(_pop_count_packed_deps_T_965, 1, 0) node _pop_count_packed_deps_T_967 = add(_pop_count_packed_deps_T_964, _pop_count_packed_deps_T_966) node _pop_count_packed_deps_T_968 = bits(_pop_count_packed_deps_T_967, 2, 0) node _pop_count_packed_deps_T_969 = add(entries_ex[9].bits.deps_ex[12], entries_ex[9].bits.deps_ex[13]) node _pop_count_packed_deps_T_970 = bits(_pop_count_packed_deps_T_969, 1, 0) node _pop_count_packed_deps_T_971 = add(entries_ex[9].bits.deps_ex[14], entries_ex[9].bits.deps_ex[15]) node _pop_count_packed_deps_T_972 = bits(_pop_count_packed_deps_T_971, 1, 0) node _pop_count_packed_deps_T_973 = add(_pop_count_packed_deps_T_970, _pop_count_packed_deps_T_972) node _pop_count_packed_deps_T_974 = bits(_pop_count_packed_deps_T_973, 2, 0) node _pop_count_packed_deps_T_975 = add(_pop_count_packed_deps_T_968, _pop_count_packed_deps_T_974) node _pop_count_packed_deps_T_976 = bits(_pop_count_packed_deps_T_975, 3, 0) node _pop_count_packed_deps_T_977 = add(_pop_count_packed_deps_T_962, _pop_count_packed_deps_T_976) node _pop_count_packed_deps_T_978 = bits(_pop_count_packed_deps_T_977, 4, 0) node _pop_count_packed_deps_T_979 = add(_pop_count_packed_deps_T_948, _pop_count_packed_deps_T_978) node _pop_count_packed_deps_T_980 = tail(_pop_count_packed_deps_T_979, 1) node _pop_count_packed_deps_T_981 = add(entries_ex[9].bits.deps_st[0], entries_ex[9].bits.deps_st[1]) node _pop_count_packed_deps_T_982 = bits(_pop_count_packed_deps_T_981, 1, 0) node _pop_count_packed_deps_T_983 = add(entries_ex[9].bits.deps_st[2], entries_ex[9].bits.deps_st[3]) node _pop_count_packed_deps_T_984 = bits(_pop_count_packed_deps_T_983, 1, 0) node _pop_count_packed_deps_T_985 = add(_pop_count_packed_deps_T_982, _pop_count_packed_deps_T_984) node _pop_count_packed_deps_T_986 = bits(_pop_count_packed_deps_T_985, 2, 0) node _pop_count_packed_deps_T_987 = add(_pop_count_packed_deps_T_980, _pop_count_packed_deps_T_986) node _pop_count_packed_deps_T_988 = tail(_pop_count_packed_deps_T_987, 1) node _pop_count_packed_deps_T_989 = mux(entries_ex[9].valid, _pop_count_packed_deps_T_988, UInt<1>(0h0)) node _pop_count_packed_deps_T_990 = add(entries_ex[10].bits.deps_ld[0], entries_ex[10].bits.deps_ld[1]) node _pop_count_packed_deps_T_991 = bits(_pop_count_packed_deps_T_990, 1, 0) node _pop_count_packed_deps_T_992 = add(entries_ex[10].bits.deps_ld[2], entries_ex[10].bits.deps_ld[3]) node _pop_count_packed_deps_T_993 = bits(_pop_count_packed_deps_T_992, 1, 0) node _pop_count_packed_deps_T_994 = add(_pop_count_packed_deps_T_991, _pop_count_packed_deps_T_993) node _pop_count_packed_deps_T_995 = bits(_pop_count_packed_deps_T_994, 2, 0) node _pop_count_packed_deps_T_996 = add(entries_ex[10].bits.deps_ld[4], entries_ex[10].bits.deps_ld[5]) node _pop_count_packed_deps_T_997 = bits(_pop_count_packed_deps_T_996, 1, 0) node _pop_count_packed_deps_T_998 = add(entries_ex[10].bits.deps_ld[6], entries_ex[10].bits.deps_ld[7]) node _pop_count_packed_deps_T_999 = bits(_pop_count_packed_deps_T_998, 1, 0) node _pop_count_packed_deps_T_1000 = add(_pop_count_packed_deps_T_997, _pop_count_packed_deps_T_999) node _pop_count_packed_deps_T_1001 = bits(_pop_count_packed_deps_T_1000, 2, 0) node _pop_count_packed_deps_T_1002 = add(_pop_count_packed_deps_T_995, _pop_count_packed_deps_T_1001) node _pop_count_packed_deps_T_1003 = bits(_pop_count_packed_deps_T_1002, 3, 0) node _pop_count_packed_deps_T_1004 = add(entries_ex[10].bits.deps_ex[0], entries_ex[10].bits.deps_ex[1]) node _pop_count_packed_deps_T_1005 = bits(_pop_count_packed_deps_T_1004, 1, 0) node _pop_count_packed_deps_T_1006 = add(entries_ex[10].bits.deps_ex[2], entries_ex[10].bits.deps_ex[3]) node _pop_count_packed_deps_T_1007 = bits(_pop_count_packed_deps_T_1006, 1, 0) node _pop_count_packed_deps_T_1008 = add(_pop_count_packed_deps_T_1005, _pop_count_packed_deps_T_1007) node _pop_count_packed_deps_T_1009 = bits(_pop_count_packed_deps_T_1008, 2, 0) node _pop_count_packed_deps_T_1010 = add(entries_ex[10].bits.deps_ex[4], entries_ex[10].bits.deps_ex[5]) node _pop_count_packed_deps_T_1011 = bits(_pop_count_packed_deps_T_1010, 1, 0) node _pop_count_packed_deps_T_1012 = add(entries_ex[10].bits.deps_ex[6], entries_ex[10].bits.deps_ex[7]) node _pop_count_packed_deps_T_1013 = bits(_pop_count_packed_deps_T_1012, 1, 0) node _pop_count_packed_deps_T_1014 = add(_pop_count_packed_deps_T_1011, _pop_count_packed_deps_T_1013) node _pop_count_packed_deps_T_1015 = bits(_pop_count_packed_deps_T_1014, 2, 0) node _pop_count_packed_deps_T_1016 = add(_pop_count_packed_deps_T_1009, _pop_count_packed_deps_T_1015) node _pop_count_packed_deps_T_1017 = bits(_pop_count_packed_deps_T_1016, 3, 0) node _pop_count_packed_deps_T_1018 = add(entries_ex[10].bits.deps_ex[8], entries_ex[10].bits.deps_ex[9]) node _pop_count_packed_deps_T_1019 = bits(_pop_count_packed_deps_T_1018, 1, 0) node _pop_count_packed_deps_T_1020 = add(entries_ex[10].bits.deps_ex[10], entries_ex[10].bits.deps_ex[11]) node _pop_count_packed_deps_T_1021 = bits(_pop_count_packed_deps_T_1020, 1, 0) node _pop_count_packed_deps_T_1022 = add(_pop_count_packed_deps_T_1019, _pop_count_packed_deps_T_1021) node _pop_count_packed_deps_T_1023 = bits(_pop_count_packed_deps_T_1022, 2, 0) node _pop_count_packed_deps_T_1024 = add(entries_ex[10].bits.deps_ex[12], entries_ex[10].bits.deps_ex[13]) node _pop_count_packed_deps_T_1025 = bits(_pop_count_packed_deps_T_1024, 1, 0) node _pop_count_packed_deps_T_1026 = add(entries_ex[10].bits.deps_ex[14], entries_ex[10].bits.deps_ex[15]) node _pop_count_packed_deps_T_1027 = bits(_pop_count_packed_deps_T_1026, 1, 0) node _pop_count_packed_deps_T_1028 = add(_pop_count_packed_deps_T_1025, _pop_count_packed_deps_T_1027) node _pop_count_packed_deps_T_1029 = bits(_pop_count_packed_deps_T_1028, 2, 0) node _pop_count_packed_deps_T_1030 = add(_pop_count_packed_deps_T_1023, _pop_count_packed_deps_T_1029) node _pop_count_packed_deps_T_1031 = bits(_pop_count_packed_deps_T_1030, 3, 0) node _pop_count_packed_deps_T_1032 = add(_pop_count_packed_deps_T_1017, _pop_count_packed_deps_T_1031) node _pop_count_packed_deps_T_1033 = bits(_pop_count_packed_deps_T_1032, 4, 0) node _pop_count_packed_deps_T_1034 = add(_pop_count_packed_deps_T_1003, _pop_count_packed_deps_T_1033) node _pop_count_packed_deps_T_1035 = tail(_pop_count_packed_deps_T_1034, 1) node _pop_count_packed_deps_T_1036 = add(entries_ex[10].bits.deps_st[0], entries_ex[10].bits.deps_st[1]) node _pop_count_packed_deps_T_1037 = bits(_pop_count_packed_deps_T_1036, 1, 0) node _pop_count_packed_deps_T_1038 = add(entries_ex[10].bits.deps_st[2], entries_ex[10].bits.deps_st[3]) node _pop_count_packed_deps_T_1039 = bits(_pop_count_packed_deps_T_1038, 1, 0) node _pop_count_packed_deps_T_1040 = add(_pop_count_packed_deps_T_1037, _pop_count_packed_deps_T_1039) node _pop_count_packed_deps_T_1041 = bits(_pop_count_packed_deps_T_1040, 2, 0) node _pop_count_packed_deps_T_1042 = add(_pop_count_packed_deps_T_1035, _pop_count_packed_deps_T_1041) node _pop_count_packed_deps_T_1043 = tail(_pop_count_packed_deps_T_1042, 1) node _pop_count_packed_deps_T_1044 = mux(entries_ex[10].valid, _pop_count_packed_deps_T_1043, UInt<1>(0h0)) node _pop_count_packed_deps_T_1045 = add(entries_ex[11].bits.deps_ld[0], entries_ex[11].bits.deps_ld[1]) node _pop_count_packed_deps_T_1046 = bits(_pop_count_packed_deps_T_1045, 1, 0) node _pop_count_packed_deps_T_1047 = add(entries_ex[11].bits.deps_ld[2], entries_ex[11].bits.deps_ld[3]) node _pop_count_packed_deps_T_1048 = bits(_pop_count_packed_deps_T_1047, 1, 0) node _pop_count_packed_deps_T_1049 = add(_pop_count_packed_deps_T_1046, _pop_count_packed_deps_T_1048) node _pop_count_packed_deps_T_1050 = bits(_pop_count_packed_deps_T_1049, 2, 0) node _pop_count_packed_deps_T_1051 = add(entries_ex[11].bits.deps_ld[4], entries_ex[11].bits.deps_ld[5]) node _pop_count_packed_deps_T_1052 = bits(_pop_count_packed_deps_T_1051, 1, 0) node _pop_count_packed_deps_T_1053 = add(entries_ex[11].bits.deps_ld[6], entries_ex[11].bits.deps_ld[7]) node _pop_count_packed_deps_T_1054 = bits(_pop_count_packed_deps_T_1053, 1, 0) node _pop_count_packed_deps_T_1055 = add(_pop_count_packed_deps_T_1052, _pop_count_packed_deps_T_1054) node _pop_count_packed_deps_T_1056 = bits(_pop_count_packed_deps_T_1055, 2, 0) node _pop_count_packed_deps_T_1057 = add(_pop_count_packed_deps_T_1050, _pop_count_packed_deps_T_1056) node _pop_count_packed_deps_T_1058 = bits(_pop_count_packed_deps_T_1057, 3, 0) node _pop_count_packed_deps_T_1059 = add(entries_ex[11].bits.deps_ex[0], entries_ex[11].bits.deps_ex[1]) node _pop_count_packed_deps_T_1060 = bits(_pop_count_packed_deps_T_1059, 1, 0) node _pop_count_packed_deps_T_1061 = add(entries_ex[11].bits.deps_ex[2], entries_ex[11].bits.deps_ex[3]) node _pop_count_packed_deps_T_1062 = bits(_pop_count_packed_deps_T_1061, 1, 0) node _pop_count_packed_deps_T_1063 = add(_pop_count_packed_deps_T_1060, _pop_count_packed_deps_T_1062) node _pop_count_packed_deps_T_1064 = bits(_pop_count_packed_deps_T_1063, 2, 0) node _pop_count_packed_deps_T_1065 = add(entries_ex[11].bits.deps_ex[4], entries_ex[11].bits.deps_ex[5]) node _pop_count_packed_deps_T_1066 = bits(_pop_count_packed_deps_T_1065, 1, 0) node _pop_count_packed_deps_T_1067 = add(entries_ex[11].bits.deps_ex[6], entries_ex[11].bits.deps_ex[7]) node _pop_count_packed_deps_T_1068 = bits(_pop_count_packed_deps_T_1067, 1, 0) node _pop_count_packed_deps_T_1069 = add(_pop_count_packed_deps_T_1066, _pop_count_packed_deps_T_1068) node _pop_count_packed_deps_T_1070 = bits(_pop_count_packed_deps_T_1069, 2, 0) node _pop_count_packed_deps_T_1071 = add(_pop_count_packed_deps_T_1064, _pop_count_packed_deps_T_1070) node _pop_count_packed_deps_T_1072 = bits(_pop_count_packed_deps_T_1071, 3, 0) node _pop_count_packed_deps_T_1073 = add(entries_ex[11].bits.deps_ex[8], entries_ex[11].bits.deps_ex[9]) node _pop_count_packed_deps_T_1074 = bits(_pop_count_packed_deps_T_1073, 1, 0) node _pop_count_packed_deps_T_1075 = add(entries_ex[11].bits.deps_ex[10], entries_ex[11].bits.deps_ex[11]) node _pop_count_packed_deps_T_1076 = bits(_pop_count_packed_deps_T_1075, 1, 0) node _pop_count_packed_deps_T_1077 = add(_pop_count_packed_deps_T_1074, _pop_count_packed_deps_T_1076) node _pop_count_packed_deps_T_1078 = bits(_pop_count_packed_deps_T_1077, 2, 0) node _pop_count_packed_deps_T_1079 = add(entries_ex[11].bits.deps_ex[12], entries_ex[11].bits.deps_ex[13]) node _pop_count_packed_deps_T_1080 = bits(_pop_count_packed_deps_T_1079, 1, 0) node _pop_count_packed_deps_T_1081 = add(entries_ex[11].bits.deps_ex[14], entries_ex[11].bits.deps_ex[15]) node _pop_count_packed_deps_T_1082 = bits(_pop_count_packed_deps_T_1081, 1, 0) node _pop_count_packed_deps_T_1083 = add(_pop_count_packed_deps_T_1080, _pop_count_packed_deps_T_1082) node _pop_count_packed_deps_T_1084 = bits(_pop_count_packed_deps_T_1083, 2, 0) node _pop_count_packed_deps_T_1085 = add(_pop_count_packed_deps_T_1078, _pop_count_packed_deps_T_1084) node _pop_count_packed_deps_T_1086 = bits(_pop_count_packed_deps_T_1085, 3, 0) node _pop_count_packed_deps_T_1087 = add(_pop_count_packed_deps_T_1072, _pop_count_packed_deps_T_1086) node _pop_count_packed_deps_T_1088 = bits(_pop_count_packed_deps_T_1087, 4, 0) node _pop_count_packed_deps_T_1089 = add(_pop_count_packed_deps_T_1058, _pop_count_packed_deps_T_1088) node _pop_count_packed_deps_T_1090 = tail(_pop_count_packed_deps_T_1089, 1) node _pop_count_packed_deps_T_1091 = add(entries_ex[11].bits.deps_st[0], entries_ex[11].bits.deps_st[1]) node _pop_count_packed_deps_T_1092 = bits(_pop_count_packed_deps_T_1091, 1, 0) node _pop_count_packed_deps_T_1093 = add(entries_ex[11].bits.deps_st[2], entries_ex[11].bits.deps_st[3]) node _pop_count_packed_deps_T_1094 = bits(_pop_count_packed_deps_T_1093, 1, 0) node _pop_count_packed_deps_T_1095 = add(_pop_count_packed_deps_T_1092, _pop_count_packed_deps_T_1094) node _pop_count_packed_deps_T_1096 = bits(_pop_count_packed_deps_T_1095, 2, 0) node _pop_count_packed_deps_T_1097 = add(_pop_count_packed_deps_T_1090, _pop_count_packed_deps_T_1096) node _pop_count_packed_deps_T_1098 = tail(_pop_count_packed_deps_T_1097, 1) node _pop_count_packed_deps_T_1099 = mux(entries_ex[11].valid, _pop_count_packed_deps_T_1098, UInt<1>(0h0)) node _pop_count_packed_deps_T_1100 = add(entries_ex[12].bits.deps_ld[0], entries_ex[12].bits.deps_ld[1]) node _pop_count_packed_deps_T_1101 = bits(_pop_count_packed_deps_T_1100, 1, 0) node _pop_count_packed_deps_T_1102 = add(entries_ex[12].bits.deps_ld[2], entries_ex[12].bits.deps_ld[3]) node _pop_count_packed_deps_T_1103 = bits(_pop_count_packed_deps_T_1102, 1, 0) node _pop_count_packed_deps_T_1104 = add(_pop_count_packed_deps_T_1101, _pop_count_packed_deps_T_1103) node _pop_count_packed_deps_T_1105 = bits(_pop_count_packed_deps_T_1104, 2, 0) node _pop_count_packed_deps_T_1106 = add(entries_ex[12].bits.deps_ld[4], entries_ex[12].bits.deps_ld[5]) node _pop_count_packed_deps_T_1107 = bits(_pop_count_packed_deps_T_1106, 1, 0) node _pop_count_packed_deps_T_1108 = add(entries_ex[12].bits.deps_ld[6], entries_ex[12].bits.deps_ld[7]) node _pop_count_packed_deps_T_1109 = bits(_pop_count_packed_deps_T_1108, 1, 0) node _pop_count_packed_deps_T_1110 = add(_pop_count_packed_deps_T_1107, _pop_count_packed_deps_T_1109) node _pop_count_packed_deps_T_1111 = bits(_pop_count_packed_deps_T_1110, 2, 0) node _pop_count_packed_deps_T_1112 = add(_pop_count_packed_deps_T_1105, _pop_count_packed_deps_T_1111) node _pop_count_packed_deps_T_1113 = bits(_pop_count_packed_deps_T_1112, 3, 0) node _pop_count_packed_deps_T_1114 = add(entries_ex[12].bits.deps_ex[0], entries_ex[12].bits.deps_ex[1]) node _pop_count_packed_deps_T_1115 = bits(_pop_count_packed_deps_T_1114, 1, 0) node _pop_count_packed_deps_T_1116 = add(entries_ex[12].bits.deps_ex[2], entries_ex[12].bits.deps_ex[3]) node _pop_count_packed_deps_T_1117 = bits(_pop_count_packed_deps_T_1116, 1, 0) node _pop_count_packed_deps_T_1118 = add(_pop_count_packed_deps_T_1115, _pop_count_packed_deps_T_1117) node _pop_count_packed_deps_T_1119 = bits(_pop_count_packed_deps_T_1118, 2, 0) node _pop_count_packed_deps_T_1120 = add(entries_ex[12].bits.deps_ex[4], entries_ex[12].bits.deps_ex[5]) node _pop_count_packed_deps_T_1121 = bits(_pop_count_packed_deps_T_1120, 1, 0) node _pop_count_packed_deps_T_1122 = add(entries_ex[12].bits.deps_ex[6], entries_ex[12].bits.deps_ex[7]) node _pop_count_packed_deps_T_1123 = bits(_pop_count_packed_deps_T_1122, 1, 0) node _pop_count_packed_deps_T_1124 = add(_pop_count_packed_deps_T_1121, _pop_count_packed_deps_T_1123) node _pop_count_packed_deps_T_1125 = bits(_pop_count_packed_deps_T_1124, 2, 0) node _pop_count_packed_deps_T_1126 = add(_pop_count_packed_deps_T_1119, _pop_count_packed_deps_T_1125) node _pop_count_packed_deps_T_1127 = bits(_pop_count_packed_deps_T_1126, 3, 0) node _pop_count_packed_deps_T_1128 = add(entries_ex[12].bits.deps_ex[8], entries_ex[12].bits.deps_ex[9]) node _pop_count_packed_deps_T_1129 = bits(_pop_count_packed_deps_T_1128, 1, 0) node _pop_count_packed_deps_T_1130 = add(entries_ex[12].bits.deps_ex[10], entries_ex[12].bits.deps_ex[11]) node _pop_count_packed_deps_T_1131 = bits(_pop_count_packed_deps_T_1130, 1, 0) node _pop_count_packed_deps_T_1132 = add(_pop_count_packed_deps_T_1129, _pop_count_packed_deps_T_1131) node _pop_count_packed_deps_T_1133 = bits(_pop_count_packed_deps_T_1132, 2, 0) node _pop_count_packed_deps_T_1134 = add(entries_ex[12].bits.deps_ex[12], entries_ex[12].bits.deps_ex[13]) node _pop_count_packed_deps_T_1135 = bits(_pop_count_packed_deps_T_1134, 1, 0) node _pop_count_packed_deps_T_1136 = add(entries_ex[12].bits.deps_ex[14], entries_ex[12].bits.deps_ex[15]) node _pop_count_packed_deps_T_1137 = bits(_pop_count_packed_deps_T_1136, 1, 0) node _pop_count_packed_deps_T_1138 = add(_pop_count_packed_deps_T_1135, _pop_count_packed_deps_T_1137) node _pop_count_packed_deps_T_1139 = bits(_pop_count_packed_deps_T_1138, 2, 0) node _pop_count_packed_deps_T_1140 = add(_pop_count_packed_deps_T_1133, _pop_count_packed_deps_T_1139) node _pop_count_packed_deps_T_1141 = bits(_pop_count_packed_deps_T_1140, 3, 0) node _pop_count_packed_deps_T_1142 = add(_pop_count_packed_deps_T_1127, _pop_count_packed_deps_T_1141) node _pop_count_packed_deps_T_1143 = bits(_pop_count_packed_deps_T_1142, 4, 0) node _pop_count_packed_deps_T_1144 = add(_pop_count_packed_deps_T_1113, _pop_count_packed_deps_T_1143) node _pop_count_packed_deps_T_1145 = tail(_pop_count_packed_deps_T_1144, 1) node _pop_count_packed_deps_T_1146 = add(entries_ex[12].bits.deps_st[0], entries_ex[12].bits.deps_st[1]) node _pop_count_packed_deps_T_1147 = bits(_pop_count_packed_deps_T_1146, 1, 0) node _pop_count_packed_deps_T_1148 = add(entries_ex[12].bits.deps_st[2], entries_ex[12].bits.deps_st[3]) node _pop_count_packed_deps_T_1149 = bits(_pop_count_packed_deps_T_1148, 1, 0) node _pop_count_packed_deps_T_1150 = add(_pop_count_packed_deps_T_1147, _pop_count_packed_deps_T_1149) node _pop_count_packed_deps_T_1151 = bits(_pop_count_packed_deps_T_1150, 2, 0) node _pop_count_packed_deps_T_1152 = add(_pop_count_packed_deps_T_1145, _pop_count_packed_deps_T_1151) node _pop_count_packed_deps_T_1153 = tail(_pop_count_packed_deps_T_1152, 1) node _pop_count_packed_deps_T_1154 = mux(entries_ex[12].valid, _pop_count_packed_deps_T_1153, UInt<1>(0h0)) node _pop_count_packed_deps_T_1155 = add(entries_ex[13].bits.deps_ld[0], entries_ex[13].bits.deps_ld[1]) node _pop_count_packed_deps_T_1156 = bits(_pop_count_packed_deps_T_1155, 1, 0) node _pop_count_packed_deps_T_1157 = add(entries_ex[13].bits.deps_ld[2], entries_ex[13].bits.deps_ld[3]) node _pop_count_packed_deps_T_1158 = bits(_pop_count_packed_deps_T_1157, 1, 0) node _pop_count_packed_deps_T_1159 = add(_pop_count_packed_deps_T_1156, _pop_count_packed_deps_T_1158) node _pop_count_packed_deps_T_1160 = bits(_pop_count_packed_deps_T_1159, 2, 0) node _pop_count_packed_deps_T_1161 = add(entries_ex[13].bits.deps_ld[4], entries_ex[13].bits.deps_ld[5]) node _pop_count_packed_deps_T_1162 = bits(_pop_count_packed_deps_T_1161, 1, 0) node _pop_count_packed_deps_T_1163 = add(entries_ex[13].bits.deps_ld[6], entries_ex[13].bits.deps_ld[7]) node _pop_count_packed_deps_T_1164 = bits(_pop_count_packed_deps_T_1163, 1, 0) node _pop_count_packed_deps_T_1165 = add(_pop_count_packed_deps_T_1162, _pop_count_packed_deps_T_1164) node _pop_count_packed_deps_T_1166 = bits(_pop_count_packed_deps_T_1165, 2, 0) node _pop_count_packed_deps_T_1167 = add(_pop_count_packed_deps_T_1160, _pop_count_packed_deps_T_1166) node _pop_count_packed_deps_T_1168 = bits(_pop_count_packed_deps_T_1167, 3, 0) node _pop_count_packed_deps_T_1169 = add(entries_ex[13].bits.deps_ex[0], entries_ex[13].bits.deps_ex[1]) node _pop_count_packed_deps_T_1170 = bits(_pop_count_packed_deps_T_1169, 1, 0) node _pop_count_packed_deps_T_1171 = add(entries_ex[13].bits.deps_ex[2], entries_ex[13].bits.deps_ex[3]) node _pop_count_packed_deps_T_1172 = bits(_pop_count_packed_deps_T_1171, 1, 0) node _pop_count_packed_deps_T_1173 = add(_pop_count_packed_deps_T_1170, _pop_count_packed_deps_T_1172) node _pop_count_packed_deps_T_1174 = bits(_pop_count_packed_deps_T_1173, 2, 0) node _pop_count_packed_deps_T_1175 = add(entries_ex[13].bits.deps_ex[4], entries_ex[13].bits.deps_ex[5]) node _pop_count_packed_deps_T_1176 = bits(_pop_count_packed_deps_T_1175, 1, 0) node _pop_count_packed_deps_T_1177 = add(entries_ex[13].bits.deps_ex[6], entries_ex[13].bits.deps_ex[7]) node _pop_count_packed_deps_T_1178 = bits(_pop_count_packed_deps_T_1177, 1, 0) node _pop_count_packed_deps_T_1179 = add(_pop_count_packed_deps_T_1176, _pop_count_packed_deps_T_1178) node _pop_count_packed_deps_T_1180 = bits(_pop_count_packed_deps_T_1179, 2, 0) node _pop_count_packed_deps_T_1181 = add(_pop_count_packed_deps_T_1174, _pop_count_packed_deps_T_1180) node _pop_count_packed_deps_T_1182 = bits(_pop_count_packed_deps_T_1181, 3, 0) node _pop_count_packed_deps_T_1183 = add(entries_ex[13].bits.deps_ex[8], entries_ex[13].bits.deps_ex[9]) node _pop_count_packed_deps_T_1184 = bits(_pop_count_packed_deps_T_1183, 1, 0) node _pop_count_packed_deps_T_1185 = add(entries_ex[13].bits.deps_ex[10], entries_ex[13].bits.deps_ex[11]) node _pop_count_packed_deps_T_1186 = bits(_pop_count_packed_deps_T_1185, 1, 0) node _pop_count_packed_deps_T_1187 = add(_pop_count_packed_deps_T_1184, _pop_count_packed_deps_T_1186) node _pop_count_packed_deps_T_1188 = bits(_pop_count_packed_deps_T_1187, 2, 0) node _pop_count_packed_deps_T_1189 = add(entries_ex[13].bits.deps_ex[12], entries_ex[13].bits.deps_ex[13]) node _pop_count_packed_deps_T_1190 = bits(_pop_count_packed_deps_T_1189, 1, 0) node _pop_count_packed_deps_T_1191 = add(entries_ex[13].bits.deps_ex[14], entries_ex[13].bits.deps_ex[15]) node _pop_count_packed_deps_T_1192 = bits(_pop_count_packed_deps_T_1191, 1, 0) node _pop_count_packed_deps_T_1193 = add(_pop_count_packed_deps_T_1190, _pop_count_packed_deps_T_1192) node _pop_count_packed_deps_T_1194 = bits(_pop_count_packed_deps_T_1193, 2, 0) node _pop_count_packed_deps_T_1195 = add(_pop_count_packed_deps_T_1188, _pop_count_packed_deps_T_1194) node _pop_count_packed_deps_T_1196 = bits(_pop_count_packed_deps_T_1195, 3, 0) node _pop_count_packed_deps_T_1197 = add(_pop_count_packed_deps_T_1182, _pop_count_packed_deps_T_1196) node _pop_count_packed_deps_T_1198 = bits(_pop_count_packed_deps_T_1197, 4, 0) node _pop_count_packed_deps_T_1199 = add(_pop_count_packed_deps_T_1168, _pop_count_packed_deps_T_1198) node _pop_count_packed_deps_T_1200 = tail(_pop_count_packed_deps_T_1199, 1) node _pop_count_packed_deps_T_1201 = add(entries_ex[13].bits.deps_st[0], entries_ex[13].bits.deps_st[1]) node _pop_count_packed_deps_T_1202 = bits(_pop_count_packed_deps_T_1201, 1, 0) node _pop_count_packed_deps_T_1203 = add(entries_ex[13].bits.deps_st[2], entries_ex[13].bits.deps_st[3]) node _pop_count_packed_deps_T_1204 = bits(_pop_count_packed_deps_T_1203, 1, 0) node _pop_count_packed_deps_T_1205 = add(_pop_count_packed_deps_T_1202, _pop_count_packed_deps_T_1204) node _pop_count_packed_deps_T_1206 = bits(_pop_count_packed_deps_T_1205, 2, 0) node _pop_count_packed_deps_T_1207 = add(_pop_count_packed_deps_T_1200, _pop_count_packed_deps_T_1206) node _pop_count_packed_deps_T_1208 = tail(_pop_count_packed_deps_T_1207, 1) node _pop_count_packed_deps_T_1209 = mux(entries_ex[13].valid, _pop_count_packed_deps_T_1208, UInt<1>(0h0)) node _pop_count_packed_deps_T_1210 = add(entries_ex[14].bits.deps_ld[0], entries_ex[14].bits.deps_ld[1]) node _pop_count_packed_deps_T_1211 = bits(_pop_count_packed_deps_T_1210, 1, 0) node _pop_count_packed_deps_T_1212 = add(entries_ex[14].bits.deps_ld[2], entries_ex[14].bits.deps_ld[3]) node _pop_count_packed_deps_T_1213 = bits(_pop_count_packed_deps_T_1212, 1, 0) node _pop_count_packed_deps_T_1214 = add(_pop_count_packed_deps_T_1211, _pop_count_packed_deps_T_1213) node _pop_count_packed_deps_T_1215 = bits(_pop_count_packed_deps_T_1214, 2, 0) node _pop_count_packed_deps_T_1216 = add(entries_ex[14].bits.deps_ld[4], entries_ex[14].bits.deps_ld[5]) node _pop_count_packed_deps_T_1217 = bits(_pop_count_packed_deps_T_1216, 1, 0) node _pop_count_packed_deps_T_1218 = add(entries_ex[14].bits.deps_ld[6], entries_ex[14].bits.deps_ld[7]) node _pop_count_packed_deps_T_1219 = bits(_pop_count_packed_deps_T_1218, 1, 0) node _pop_count_packed_deps_T_1220 = add(_pop_count_packed_deps_T_1217, _pop_count_packed_deps_T_1219) node _pop_count_packed_deps_T_1221 = bits(_pop_count_packed_deps_T_1220, 2, 0) node _pop_count_packed_deps_T_1222 = add(_pop_count_packed_deps_T_1215, _pop_count_packed_deps_T_1221) node _pop_count_packed_deps_T_1223 = bits(_pop_count_packed_deps_T_1222, 3, 0) node _pop_count_packed_deps_T_1224 = add(entries_ex[14].bits.deps_ex[0], entries_ex[14].bits.deps_ex[1]) node _pop_count_packed_deps_T_1225 = bits(_pop_count_packed_deps_T_1224, 1, 0) node _pop_count_packed_deps_T_1226 = add(entries_ex[14].bits.deps_ex[2], entries_ex[14].bits.deps_ex[3]) node _pop_count_packed_deps_T_1227 = bits(_pop_count_packed_deps_T_1226, 1, 0) node _pop_count_packed_deps_T_1228 = add(_pop_count_packed_deps_T_1225, _pop_count_packed_deps_T_1227) node _pop_count_packed_deps_T_1229 = bits(_pop_count_packed_deps_T_1228, 2, 0) node _pop_count_packed_deps_T_1230 = add(entries_ex[14].bits.deps_ex[4], entries_ex[14].bits.deps_ex[5]) node _pop_count_packed_deps_T_1231 = bits(_pop_count_packed_deps_T_1230, 1, 0) node _pop_count_packed_deps_T_1232 = add(entries_ex[14].bits.deps_ex[6], entries_ex[14].bits.deps_ex[7]) node _pop_count_packed_deps_T_1233 = bits(_pop_count_packed_deps_T_1232, 1, 0) node _pop_count_packed_deps_T_1234 = add(_pop_count_packed_deps_T_1231, _pop_count_packed_deps_T_1233) node _pop_count_packed_deps_T_1235 = bits(_pop_count_packed_deps_T_1234, 2, 0) node _pop_count_packed_deps_T_1236 = add(_pop_count_packed_deps_T_1229, _pop_count_packed_deps_T_1235) node _pop_count_packed_deps_T_1237 = bits(_pop_count_packed_deps_T_1236, 3, 0) node _pop_count_packed_deps_T_1238 = add(entries_ex[14].bits.deps_ex[8], entries_ex[14].bits.deps_ex[9]) node _pop_count_packed_deps_T_1239 = bits(_pop_count_packed_deps_T_1238, 1, 0) node _pop_count_packed_deps_T_1240 = add(entries_ex[14].bits.deps_ex[10], entries_ex[14].bits.deps_ex[11]) node _pop_count_packed_deps_T_1241 = bits(_pop_count_packed_deps_T_1240, 1, 0) node _pop_count_packed_deps_T_1242 = add(_pop_count_packed_deps_T_1239, _pop_count_packed_deps_T_1241) node _pop_count_packed_deps_T_1243 = bits(_pop_count_packed_deps_T_1242, 2, 0) node _pop_count_packed_deps_T_1244 = add(entries_ex[14].bits.deps_ex[12], entries_ex[14].bits.deps_ex[13]) node _pop_count_packed_deps_T_1245 = bits(_pop_count_packed_deps_T_1244, 1, 0) node _pop_count_packed_deps_T_1246 = add(entries_ex[14].bits.deps_ex[14], entries_ex[14].bits.deps_ex[15]) node _pop_count_packed_deps_T_1247 = bits(_pop_count_packed_deps_T_1246, 1, 0) node _pop_count_packed_deps_T_1248 = add(_pop_count_packed_deps_T_1245, _pop_count_packed_deps_T_1247) node _pop_count_packed_deps_T_1249 = bits(_pop_count_packed_deps_T_1248, 2, 0) node _pop_count_packed_deps_T_1250 = add(_pop_count_packed_deps_T_1243, _pop_count_packed_deps_T_1249) node _pop_count_packed_deps_T_1251 = bits(_pop_count_packed_deps_T_1250, 3, 0) node _pop_count_packed_deps_T_1252 = add(_pop_count_packed_deps_T_1237, _pop_count_packed_deps_T_1251) node _pop_count_packed_deps_T_1253 = bits(_pop_count_packed_deps_T_1252, 4, 0) node _pop_count_packed_deps_T_1254 = add(_pop_count_packed_deps_T_1223, _pop_count_packed_deps_T_1253) node _pop_count_packed_deps_T_1255 = tail(_pop_count_packed_deps_T_1254, 1) node _pop_count_packed_deps_T_1256 = add(entries_ex[14].bits.deps_st[0], entries_ex[14].bits.deps_st[1]) node _pop_count_packed_deps_T_1257 = bits(_pop_count_packed_deps_T_1256, 1, 0) node _pop_count_packed_deps_T_1258 = add(entries_ex[14].bits.deps_st[2], entries_ex[14].bits.deps_st[3]) node _pop_count_packed_deps_T_1259 = bits(_pop_count_packed_deps_T_1258, 1, 0) node _pop_count_packed_deps_T_1260 = add(_pop_count_packed_deps_T_1257, _pop_count_packed_deps_T_1259) node _pop_count_packed_deps_T_1261 = bits(_pop_count_packed_deps_T_1260, 2, 0) node _pop_count_packed_deps_T_1262 = add(_pop_count_packed_deps_T_1255, _pop_count_packed_deps_T_1261) node _pop_count_packed_deps_T_1263 = tail(_pop_count_packed_deps_T_1262, 1) node _pop_count_packed_deps_T_1264 = mux(entries_ex[14].valid, _pop_count_packed_deps_T_1263, UInt<1>(0h0)) node _pop_count_packed_deps_T_1265 = add(entries_ex[15].bits.deps_ld[0], entries_ex[15].bits.deps_ld[1]) node _pop_count_packed_deps_T_1266 = bits(_pop_count_packed_deps_T_1265, 1, 0) node _pop_count_packed_deps_T_1267 = add(entries_ex[15].bits.deps_ld[2], entries_ex[15].bits.deps_ld[3]) node _pop_count_packed_deps_T_1268 = bits(_pop_count_packed_deps_T_1267, 1, 0) node _pop_count_packed_deps_T_1269 = add(_pop_count_packed_deps_T_1266, _pop_count_packed_deps_T_1268) node _pop_count_packed_deps_T_1270 = bits(_pop_count_packed_deps_T_1269, 2, 0) node _pop_count_packed_deps_T_1271 = add(entries_ex[15].bits.deps_ld[4], entries_ex[15].bits.deps_ld[5]) node _pop_count_packed_deps_T_1272 = bits(_pop_count_packed_deps_T_1271, 1, 0) node _pop_count_packed_deps_T_1273 = add(entries_ex[15].bits.deps_ld[6], entries_ex[15].bits.deps_ld[7]) node _pop_count_packed_deps_T_1274 = bits(_pop_count_packed_deps_T_1273, 1, 0) node _pop_count_packed_deps_T_1275 = add(_pop_count_packed_deps_T_1272, _pop_count_packed_deps_T_1274) node _pop_count_packed_deps_T_1276 = bits(_pop_count_packed_deps_T_1275, 2, 0) node _pop_count_packed_deps_T_1277 = add(_pop_count_packed_deps_T_1270, _pop_count_packed_deps_T_1276) node _pop_count_packed_deps_T_1278 = bits(_pop_count_packed_deps_T_1277, 3, 0) node _pop_count_packed_deps_T_1279 = add(entries_ex[15].bits.deps_ex[0], entries_ex[15].bits.deps_ex[1]) node _pop_count_packed_deps_T_1280 = bits(_pop_count_packed_deps_T_1279, 1, 0) node _pop_count_packed_deps_T_1281 = add(entries_ex[15].bits.deps_ex[2], entries_ex[15].bits.deps_ex[3]) node _pop_count_packed_deps_T_1282 = bits(_pop_count_packed_deps_T_1281, 1, 0) node _pop_count_packed_deps_T_1283 = add(_pop_count_packed_deps_T_1280, _pop_count_packed_deps_T_1282) node _pop_count_packed_deps_T_1284 = bits(_pop_count_packed_deps_T_1283, 2, 0) node _pop_count_packed_deps_T_1285 = add(entries_ex[15].bits.deps_ex[4], entries_ex[15].bits.deps_ex[5]) node _pop_count_packed_deps_T_1286 = bits(_pop_count_packed_deps_T_1285, 1, 0) node _pop_count_packed_deps_T_1287 = add(entries_ex[15].bits.deps_ex[6], entries_ex[15].bits.deps_ex[7]) node _pop_count_packed_deps_T_1288 = bits(_pop_count_packed_deps_T_1287, 1, 0) node _pop_count_packed_deps_T_1289 = add(_pop_count_packed_deps_T_1286, _pop_count_packed_deps_T_1288) node _pop_count_packed_deps_T_1290 = bits(_pop_count_packed_deps_T_1289, 2, 0) node _pop_count_packed_deps_T_1291 = add(_pop_count_packed_deps_T_1284, _pop_count_packed_deps_T_1290) node _pop_count_packed_deps_T_1292 = bits(_pop_count_packed_deps_T_1291, 3, 0) node _pop_count_packed_deps_T_1293 = add(entries_ex[15].bits.deps_ex[8], entries_ex[15].bits.deps_ex[9]) node _pop_count_packed_deps_T_1294 = bits(_pop_count_packed_deps_T_1293, 1, 0) node _pop_count_packed_deps_T_1295 = add(entries_ex[15].bits.deps_ex[10], entries_ex[15].bits.deps_ex[11]) node _pop_count_packed_deps_T_1296 = bits(_pop_count_packed_deps_T_1295, 1, 0) node _pop_count_packed_deps_T_1297 = add(_pop_count_packed_deps_T_1294, _pop_count_packed_deps_T_1296) node _pop_count_packed_deps_T_1298 = bits(_pop_count_packed_deps_T_1297, 2, 0) node _pop_count_packed_deps_T_1299 = add(entries_ex[15].bits.deps_ex[12], entries_ex[15].bits.deps_ex[13]) node _pop_count_packed_deps_T_1300 = bits(_pop_count_packed_deps_T_1299, 1, 0) node _pop_count_packed_deps_T_1301 = add(entries_ex[15].bits.deps_ex[14], entries_ex[15].bits.deps_ex[15]) node _pop_count_packed_deps_T_1302 = bits(_pop_count_packed_deps_T_1301, 1, 0) node _pop_count_packed_deps_T_1303 = add(_pop_count_packed_deps_T_1300, _pop_count_packed_deps_T_1302) node _pop_count_packed_deps_T_1304 = bits(_pop_count_packed_deps_T_1303, 2, 0) node _pop_count_packed_deps_T_1305 = add(_pop_count_packed_deps_T_1298, _pop_count_packed_deps_T_1304) node _pop_count_packed_deps_T_1306 = bits(_pop_count_packed_deps_T_1305, 3, 0) node _pop_count_packed_deps_T_1307 = add(_pop_count_packed_deps_T_1292, _pop_count_packed_deps_T_1306) node _pop_count_packed_deps_T_1308 = bits(_pop_count_packed_deps_T_1307, 4, 0) node _pop_count_packed_deps_T_1309 = add(_pop_count_packed_deps_T_1278, _pop_count_packed_deps_T_1308) node _pop_count_packed_deps_T_1310 = tail(_pop_count_packed_deps_T_1309, 1) node _pop_count_packed_deps_T_1311 = add(entries_ex[15].bits.deps_st[0], entries_ex[15].bits.deps_st[1]) node _pop_count_packed_deps_T_1312 = bits(_pop_count_packed_deps_T_1311, 1, 0) node _pop_count_packed_deps_T_1313 = add(entries_ex[15].bits.deps_st[2], entries_ex[15].bits.deps_st[3]) node _pop_count_packed_deps_T_1314 = bits(_pop_count_packed_deps_T_1313, 1, 0) node _pop_count_packed_deps_T_1315 = add(_pop_count_packed_deps_T_1312, _pop_count_packed_deps_T_1314) node _pop_count_packed_deps_T_1316 = bits(_pop_count_packed_deps_T_1315, 2, 0) node _pop_count_packed_deps_T_1317 = add(_pop_count_packed_deps_T_1310, _pop_count_packed_deps_T_1316) node _pop_count_packed_deps_T_1318 = tail(_pop_count_packed_deps_T_1317, 1) node _pop_count_packed_deps_T_1319 = mux(entries_ex[15].valid, _pop_count_packed_deps_T_1318, UInt<1>(0h0)) node _pop_count_packed_deps_T_1320 = add(entries_st[0].bits.deps_ld[0], entries_st[0].bits.deps_ld[1]) node _pop_count_packed_deps_T_1321 = bits(_pop_count_packed_deps_T_1320, 1, 0) node _pop_count_packed_deps_T_1322 = add(entries_st[0].bits.deps_ld[2], entries_st[0].bits.deps_ld[3]) node _pop_count_packed_deps_T_1323 = bits(_pop_count_packed_deps_T_1322, 1, 0) node _pop_count_packed_deps_T_1324 = add(_pop_count_packed_deps_T_1321, _pop_count_packed_deps_T_1323) node _pop_count_packed_deps_T_1325 = bits(_pop_count_packed_deps_T_1324, 2, 0) node _pop_count_packed_deps_T_1326 = add(entries_st[0].bits.deps_ld[4], entries_st[0].bits.deps_ld[5]) node _pop_count_packed_deps_T_1327 = bits(_pop_count_packed_deps_T_1326, 1, 0) node _pop_count_packed_deps_T_1328 = add(entries_st[0].bits.deps_ld[6], entries_st[0].bits.deps_ld[7]) node _pop_count_packed_deps_T_1329 = bits(_pop_count_packed_deps_T_1328, 1, 0) node _pop_count_packed_deps_T_1330 = add(_pop_count_packed_deps_T_1327, _pop_count_packed_deps_T_1329) node _pop_count_packed_deps_T_1331 = bits(_pop_count_packed_deps_T_1330, 2, 0) node _pop_count_packed_deps_T_1332 = add(_pop_count_packed_deps_T_1325, _pop_count_packed_deps_T_1331) node _pop_count_packed_deps_T_1333 = bits(_pop_count_packed_deps_T_1332, 3, 0) node _pop_count_packed_deps_T_1334 = add(entries_st[0].bits.deps_ex[0], entries_st[0].bits.deps_ex[1]) node _pop_count_packed_deps_T_1335 = bits(_pop_count_packed_deps_T_1334, 1, 0) node _pop_count_packed_deps_T_1336 = add(entries_st[0].bits.deps_ex[2], entries_st[0].bits.deps_ex[3]) node _pop_count_packed_deps_T_1337 = bits(_pop_count_packed_deps_T_1336, 1, 0) node _pop_count_packed_deps_T_1338 = add(_pop_count_packed_deps_T_1335, _pop_count_packed_deps_T_1337) node _pop_count_packed_deps_T_1339 = bits(_pop_count_packed_deps_T_1338, 2, 0) node _pop_count_packed_deps_T_1340 = add(entries_st[0].bits.deps_ex[4], entries_st[0].bits.deps_ex[5]) node _pop_count_packed_deps_T_1341 = bits(_pop_count_packed_deps_T_1340, 1, 0) node _pop_count_packed_deps_T_1342 = add(entries_st[0].bits.deps_ex[6], entries_st[0].bits.deps_ex[7]) node _pop_count_packed_deps_T_1343 = bits(_pop_count_packed_deps_T_1342, 1, 0) node _pop_count_packed_deps_T_1344 = add(_pop_count_packed_deps_T_1341, _pop_count_packed_deps_T_1343) node _pop_count_packed_deps_T_1345 = bits(_pop_count_packed_deps_T_1344, 2, 0) node _pop_count_packed_deps_T_1346 = add(_pop_count_packed_deps_T_1339, _pop_count_packed_deps_T_1345) node _pop_count_packed_deps_T_1347 = bits(_pop_count_packed_deps_T_1346, 3, 0) node _pop_count_packed_deps_T_1348 = add(entries_st[0].bits.deps_ex[8], entries_st[0].bits.deps_ex[9]) node _pop_count_packed_deps_T_1349 = bits(_pop_count_packed_deps_T_1348, 1, 0) node _pop_count_packed_deps_T_1350 = add(entries_st[0].bits.deps_ex[10], entries_st[0].bits.deps_ex[11]) node _pop_count_packed_deps_T_1351 = bits(_pop_count_packed_deps_T_1350, 1, 0) node _pop_count_packed_deps_T_1352 = add(_pop_count_packed_deps_T_1349, _pop_count_packed_deps_T_1351) node _pop_count_packed_deps_T_1353 = bits(_pop_count_packed_deps_T_1352, 2, 0) node _pop_count_packed_deps_T_1354 = add(entries_st[0].bits.deps_ex[12], entries_st[0].bits.deps_ex[13]) node _pop_count_packed_deps_T_1355 = bits(_pop_count_packed_deps_T_1354, 1, 0) node _pop_count_packed_deps_T_1356 = add(entries_st[0].bits.deps_ex[14], entries_st[0].bits.deps_ex[15]) node _pop_count_packed_deps_T_1357 = bits(_pop_count_packed_deps_T_1356, 1, 0) node _pop_count_packed_deps_T_1358 = add(_pop_count_packed_deps_T_1355, _pop_count_packed_deps_T_1357) node _pop_count_packed_deps_T_1359 = bits(_pop_count_packed_deps_T_1358, 2, 0) node _pop_count_packed_deps_T_1360 = add(_pop_count_packed_deps_T_1353, _pop_count_packed_deps_T_1359) node _pop_count_packed_deps_T_1361 = bits(_pop_count_packed_deps_T_1360, 3, 0) node _pop_count_packed_deps_T_1362 = add(_pop_count_packed_deps_T_1347, _pop_count_packed_deps_T_1361) node _pop_count_packed_deps_T_1363 = bits(_pop_count_packed_deps_T_1362, 4, 0) node _pop_count_packed_deps_T_1364 = add(_pop_count_packed_deps_T_1333, _pop_count_packed_deps_T_1363) node _pop_count_packed_deps_T_1365 = tail(_pop_count_packed_deps_T_1364, 1) node _pop_count_packed_deps_T_1366 = add(entries_st[0].bits.deps_st[0], entries_st[0].bits.deps_st[1]) node _pop_count_packed_deps_T_1367 = bits(_pop_count_packed_deps_T_1366, 1, 0) node _pop_count_packed_deps_T_1368 = add(entries_st[0].bits.deps_st[2], entries_st[0].bits.deps_st[3]) node _pop_count_packed_deps_T_1369 = bits(_pop_count_packed_deps_T_1368, 1, 0) node _pop_count_packed_deps_T_1370 = add(_pop_count_packed_deps_T_1367, _pop_count_packed_deps_T_1369) node _pop_count_packed_deps_T_1371 = bits(_pop_count_packed_deps_T_1370, 2, 0) node _pop_count_packed_deps_T_1372 = add(_pop_count_packed_deps_T_1365, _pop_count_packed_deps_T_1371) node _pop_count_packed_deps_T_1373 = tail(_pop_count_packed_deps_T_1372, 1) node _pop_count_packed_deps_T_1374 = mux(entries_st[0].valid, _pop_count_packed_deps_T_1373, UInt<1>(0h0)) node _pop_count_packed_deps_T_1375 = add(entries_st[1].bits.deps_ld[0], entries_st[1].bits.deps_ld[1]) node _pop_count_packed_deps_T_1376 = bits(_pop_count_packed_deps_T_1375, 1, 0) node _pop_count_packed_deps_T_1377 = add(entries_st[1].bits.deps_ld[2], entries_st[1].bits.deps_ld[3]) node _pop_count_packed_deps_T_1378 = bits(_pop_count_packed_deps_T_1377, 1, 0) node _pop_count_packed_deps_T_1379 = add(_pop_count_packed_deps_T_1376, _pop_count_packed_deps_T_1378) node _pop_count_packed_deps_T_1380 = bits(_pop_count_packed_deps_T_1379, 2, 0) node _pop_count_packed_deps_T_1381 = add(entries_st[1].bits.deps_ld[4], entries_st[1].bits.deps_ld[5]) node _pop_count_packed_deps_T_1382 = bits(_pop_count_packed_deps_T_1381, 1, 0) node _pop_count_packed_deps_T_1383 = add(entries_st[1].bits.deps_ld[6], entries_st[1].bits.deps_ld[7]) node _pop_count_packed_deps_T_1384 = bits(_pop_count_packed_deps_T_1383, 1, 0) node _pop_count_packed_deps_T_1385 = add(_pop_count_packed_deps_T_1382, _pop_count_packed_deps_T_1384) node _pop_count_packed_deps_T_1386 = bits(_pop_count_packed_deps_T_1385, 2, 0) node _pop_count_packed_deps_T_1387 = add(_pop_count_packed_deps_T_1380, _pop_count_packed_deps_T_1386) node _pop_count_packed_deps_T_1388 = bits(_pop_count_packed_deps_T_1387, 3, 0) node _pop_count_packed_deps_T_1389 = add(entries_st[1].bits.deps_ex[0], entries_st[1].bits.deps_ex[1]) node _pop_count_packed_deps_T_1390 = bits(_pop_count_packed_deps_T_1389, 1, 0) node _pop_count_packed_deps_T_1391 = add(entries_st[1].bits.deps_ex[2], entries_st[1].bits.deps_ex[3]) node _pop_count_packed_deps_T_1392 = bits(_pop_count_packed_deps_T_1391, 1, 0) node _pop_count_packed_deps_T_1393 = add(_pop_count_packed_deps_T_1390, _pop_count_packed_deps_T_1392) node _pop_count_packed_deps_T_1394 = bits(_pop_count_packed_deps_T_1393, 2, 0) node _pop_count_packed_deps_T_1395 = add(entries_st[1].bits.deps_ex[4], entries_st[1].bits.deps_ex[5]) node _pop_count_packed_deps_T_1396 = bits(_pop_count_packed_deps_T_1395, 1, 0) node _pop_count_packed_deps_T_1397 = add(entries_st[1].bits.deps_ex[6], entries_st[1].bits.deps_ex[7]) node _pop_count_packed_deps_T_1398 = bits(_pop_count_packed_deps_T_1397, 1, 0) node _pop_count_packed_deps_T_1399 = add(_pop_count_packed_deps_T_1396, _pop_count_packed_deps_T_1398) node _pop_count_packed_deps_T_1400 = bits(_pop_count_packed_deps_T_1399, 2, 0) node _pop_count_packed_deps_T_1401 = add(_pop_count_packed_deps_T_1394, _pop_count_packed_deps_T_1400) node _pop_count_packed_deps_T_1402 = bits(_pop_count_packed_deps_T_1401, 3, 0) node _pop_count_packed_deps_T_1403 = add(entries_st[1].bits.deps_ex[8], entries_st[1].bits.deps_ex[9]) node _pop_count_packed_deps_T_1404 = bits(_pop_count_packed_deps_T_1403, 1, 0) node _pop_count_packed_deps_T_1405 = add(entries_st[1].bits.deps_ex[10], entries_st[1].bits.deps_ex[11]) node _pop_count_packed_deps_T_1406 = bits(_pop_count_packed_deps_T_1405, 1, 0) node _pop_count_packed_deps_T_1407 = add(_pop_count_packed_deps_T_1404, _pop_count_packed_deps_T_1406) node _pop_count_packed_deps_T_1408 = bits(_pop_count_packed_deps_T_1407, 2, 0) node _pop_count_packed_deps_T_1409 = add(entries_st[1].bits.deps_ex[12], entries_st[1].bits.deps_ex[13]) node _pop_count_packed_deps_T_1410 = bits(_pop_count_packed_deps_T_1409, 1, 0) node _pop_count_packed_deps_T_1411 = add(entries_st[1].bits.deps_ex[14], entries_st[1].bits.deps_ex[15]) node _pop_count_packed_deps_T_1412 = bits(_pop_count_packed_deps_T_1411, 1, 0) node _pop_count_packed_deps_T_1413 = add(_pop_count_packed_deps_T_1410, _pop_count_packed_deps_T_1412) node _pop_count_packed_deps_T_1414 = bits(_pop_count_packed_deps_T_1413, 2, 0) node _pop_count_packed_deps_T_1415 = add(_pop_count_packed_deps_T_1408, _pop_count_packed_deps_T_1414) node _pop_count_packed_deps_T_1416 = bits(_pop_count_packed_deps_T_1415, 3, 0) node _pop_count_packed_deps_T_1417 = add(_pop_count_packed_deps_T_1402, _pop_count_packed_deps_T_1416) node _pop_count_packed_deps_T_1418 = bits(_pop_count_packed_deps_T_1417, 4, 0) node _pop_count_packed_deps_T_1419 = add(_pop_count_packed_deps_T_1388, _pop_count_packed_deps_T_1418) node _pop_count_packed_deps_T_1420 = tail(_pop_count_packed_deps_T_1419, 1) node _pop_count_packed_deps_T_1421 = add(entries_st[1].bits.deps_st[0], entries_st[1].bits.deps_st[1]) node _pop_count_packed_deps_T_1422 = bits(_pop_count_packed_deps_T_1421, 1, 0) node _pop_count_packed_deps_T_1423 = add(entries_st[1].bits.deps_st[2], entries_st[1].bits.deps_st[3]) node _pop_count_packed_deps_T_1424 = bits(_pop_count_packed_deps_T_1423, 1, 0) node _pop_count_packed_deps_T_1425 = add(_pop_count_packed_deps_T_1422, _pop_count_packed_deps_T_1424) node _pop_count_packed_deps_T_1426 = bits(_pop_count_packed_deps_T_1425, 2, 0) node _pop_count_packed_deps_T_1427 = add(_pop_count_packed_deps_T_1420, _pop_count_packed_deps_T_1426) node _pop_count_packed_deps_T_1428 = tail(_pop_count_packed_deps_T_1427, 1) node _pop_count_packed_deps_T_1429 = mux(entries_st[1].valid, _pop_count_packed_deps_T_1428, UInt<1>(0h0)) node _pop_count_packed_deps_T_1430 = add(entries_st[2].bits.deps_ld[0], entries_st[2].bits.deps_ld[1]) node _pop_count_packed_deps_T_1431 = bits(_pop_count_packed_deps_T_1430, 1, 0) node _pop_count_packed_deps_T_1432 = add(entries_st[2].bits.deps_ld[2], entries_st[2].bits.deps_ld[3]) node _pop_count_packed_deps_T_1433 = bits(_pop_count_packed_deps_T_1432, 1, 0) node _pop_count_packed_deps_T_1434 = add(_pop_count_packed_deps_T_1431, _pop_count_packed_deps_T_1433) node _pop_count_packed_deps_T_1435 = bits(_pop_count_packed_deps_T_1434, 2, 0) node _pop_count_packed_deps_T_1436 = add(entries_st[2].bits.deps_ld[4], entries_st[2].bits.deps_ld[5]) node _pop_count_packed_deps_T_1437 = bits(_pop_count_packed_deps_T_1436, 1, 0) node _pop_count_packed_deps_T_1438 = add(entries_st[2].bits.deps_ld[6], entries_st[2].bits.deps_ld[7]) node _pop_count_packed_deps_T_1439 = bits(_pop_count_packed_deps_T_1438, 1, 0) node _pop_count_packed_deps_T_1440 = add(_pop_count_packed_deps_T_1437, _pop_count_packed_deps_T_1439) node _pop_count_packed_deps_T_1441 = bits(_pop_count_packed_deps_T_1440, 2, 0) node _pop_count_packed_deps_T_1442 = add(_pop_count_packed_deps_T_1435, _pop_count_packed_deps_T_1441) node _pop_count_packed_deps_T_1443 = bits(_pop_count_packed_deps_T_1442, 3, 0) node _pop_count_packed_deps_T_1444 = add(entries_st[2].bits.deps_ex[0], entries_st[2].bits.deps_ex[1]) node _pop_count_packed_deps_T_1445 = bits(_pop_count_packed_deps_T_1444, 1, 0) node _pop_count_packed_deps_T_1446 = add(entries_st[2].bits.deps_ex[2], entries_st[2].bits.deps_ex[3]) node _pop_count_packed_deps_T_1447 = bits(_pop_count_packed_deps_T_1446, 1, 0) node _pop_count_packed_deps_T_1448 = add(_pop_count_packed_deps_T_1445, _pop_count_packed_deps_T_1447) node _pop_count_packed_deps_T_1449 = bits(_pop_count_packed_deps_T_1448, 2, 0) node _pop_count_packed_deps_T_1450 = add(entries_st[2].bits.deps_ex[4], entries_st[2].bits.deps_ex[5]) node _pop_count_packed_deps_T_1451 = bits(_pop_count_packed_deps_T_1450, 1, 0) node _pop_count_packed_deps_T_1452 = add(entries_st[2].bits.deps_ex[6], entries_st[2].bits.deps_ex[7]) node _pop_count_packed_deps_T_1453 = bits(_pop_count_packed_deps_T_1452, 1, 0) node _pop_count_packed_deps_T_1454 = add(_pop_count_packed_deps_T_1451, _pop_count_packed_deps_T_1453) node _pop_count_packed_deps_T_1455 = bits(_pop_count_packed_deps_T_1454, 2, 0) node _pop_count_packed_deps_T_1456 = add(_pop_count_packed_deps_T_1449, _pop_count_packed_deps_T_1455) node _pop_count_packed_deps_T_1457 = bits(_pop_count_packed_deps_T_1456, 3, 0) node _pop_count_packed_deps_T_1458 = add(entries_st[2].bits.deps_ex[8], entries_st[2].bits.deps_ex[9]) node _pop_count_packed_deps_T_1459 = bits(_pop_count_packed_deps_T_1458, 1, 0) node _pop_count_packed_deps_T_1460 = add(entries_st[2].bits.deps_ex[10], entries_st[2].bits.deps_ex[11]) node _pop_count_packed_deps_T_1461 = bits(_pop_count_packed_deps_T_1460, 1, 0) node _pop_count_packed_deps_T_1462 = add(_pop_count_packed_deps_T_1459, _pop_count_packed_deps_T_1461) node _pop_count_packed_deps_T_1463 = bits(_pop_count_packed_deps_T_1462, 2, 0) node _pop_count_packed_deps_T_1464 = add(entries_st[2].bits.deps_ex[12], entries_st[2].bits.deps_ex[13]) node _pop_count_packed_deps_T_1465 = bits(_pop_count_packed_deps_T_1464, 1, 0) node _pop_count_packed_deps_T_1466 = add(entries_st[2].bits.deps_ex[14], entries_st[2].bits.deps_ex[15]) node _pop_count_packed_deps_T_1467 = bits(_pop_count_packed_deps_T_1466, 1, 0) node _pop_count_packed_deps_T_1468 = add(_pop_count_packed_deps_T_1465, _pop_count_packed_deps_T_1467) node _pop_count_packed_deps_T_1469 = bits(_pop_count_packed_deps_T_1468, 2, 0) node _pop_count_packed_deps_T_1470 = add(_pop_count_packed_deps_T_1463, _pop_count_packed_deps_T_1469) node _pop_count_packed_deps_T_1471 = bits(_pop_count_packed_deps_T_1470, 3, 0) node _pop_count_packed_deps_T_1472 = add(_pop_count_packed_deps_T_1457, _pop_count_packed_deps_T_1471) node _pop_count_packed_deps_T_1473 = bits(_pop_count_packed_deps_T_1472, 4, 0) node _pop_count_packed_deps_T_1474 = add(_pop_count_packed_deps_T_1443, _pop_count_packed_deps_T_1473) node _pop_count_packed_deps_T_1475 = tail(_pop_count_packed_deps_T_1474, 1) node _pop_count_packed_deps_T_1476 = add(entries_st[2].bits.deps_st[0], entries_st[2].bits.deps_st[1]) node _pop_count_packed_deps_T_1477 = bits(_pop_count_packed_deps_T_1476, 1, 0) node _pop_count_packed_deps_T_1478 = add(entries_st[2].bits.deps_st[2], entries_st[2].bits.deps_st[3]) node _pop_count_packed_deps_T_1479 = bits(_pop_count_packed_deps_T_1478, 1, 0) node _pop_count_packed_deps_T_1480 = add(_pop_count_packed_deps_T_1477, _pop_count_packed_deps_T_1479) node _pop_count_packed_deps_T_1481 = bits(_pop_count_packed_deps_T_1480, 2, 0) node _pop_count_packed_deps_T_1482 = add(_pop_count_packed_deps_T_1475, _pop_count_packed_deps_T_1481) node _pop_count_packed_deps_T_1483 = tail(_pop_count_packed_deps_T_1482, 1) node _pop_count_packed_deps_T_1484 = mux(entries_st[2].valid, _pop_count_packed_deps_T_1483, UInt<1>(0h0)) node _pop_count_packed_deps_T_1485 = add(entries_st[3].bits.deps_ld[0], entries_st[3].bits.deps_ld[1]) node _pop_count_packed_deps_T_1486 = bits(_pop_count_packed_deps_T_1485, 1, 0) node _pop_count_packed_deps_T_1487 = add(entries_st[3].bits.deps_ld[2], entries_st[3].bits.deps_ld[3]) node _pop_count_packed_deps_T_1488 = bits(_pop_count_packed_deps_T_1487, 1, 0) node _pop_count_packed_deps_T_1489 = add(_pop_count_packed_deps_T_1486, _pop_count_packed_deps_T_1488) node _pop_count_packed_deps_T_1490 = bits(_pop_count_packed_deps_T_1489, 2, 0) node _pop_count_packed_deps_T_1491 = add(entries_st[3].bits.deps_ld[4], entries_st[3].bits.deps_ld[5]) node _pop_count_packed_deps_T_1492 = bits(_pop_count_packed_deps_T_1491, 1, 0) node _pop_count_packed_deps_T_1493 = add(entries_st[3].bits.deps_ld[6], entries_st[3].bits.deps_ld[7]) node _pop_count_packed_deps_T_1494 = bits(_pop_count_packed_deps_T_1493, 1, 0) node _pop_count_packed_deps_T_1495 = add(_pop_count_packed_deps_T_1492, _pop_count_packed_deps_T_1494) node _pop_count_packed_deps_T_1496 = bits(_pop_count_packed_deps_T_1495, 2, 0) node _pop_count_packed_deps_T_1497 = add(_pop_count_packed_deps_T_1490, _pop_count_packed_deps_T_1496) node _pop_count_packed_deps_T_1498 = bits(_pop_count_packed_deps_T_1497, 3, 0) node _pop_count_packed_deps_T_1499 = add(entries_st[3].bits.deps_ex[0], entries_st[3].bits.deps_ex[1]) node _pop_count_packed_deps_T_1500 = bits(_pop_count_packed_deps_T_1499, 1, 0) node _pop_count_packed_deps_T_1501 = add(entries_st[3].bits.deps_ex[2], entries_st[3].bits.deps_ex[3]) node _pop_count_packed_deps_T_1502 = bits(_pop_count_packed_deps_T_1501, 1, 0) node _pop_count_packed_deps_T_1503 = add(_pop_count_packed_deps_T_1500, _pop_count_packed_deps_T_1502) node _pop_count_packed_deps_T_1504 = bits(_pop_count_packed_deps_T_1503, 2, 0) node _pop_count_packed_deps_T_1505 = add(entries_st[3].bits.deps_ex[4], entries_st[3].bits.deps_ex[5]) node _pop_count_packed_deps_T_1506 = bits(_pop_count_packed_deps_T_1505, 1, 0) node _pop_count_packed_deps_T_1507 = add(entries_st[3].bits.deps_ex[6], entries_st[3].bits.deps_ex[7]) node _pop_count_packed_deps_T_1508 = bits(_pop_count_packed_deps_T_1507, 1, 0) node _pop_count_packed_deps_T_1509 = add(_pop_count_packed_deps_T_1506, _pop_count_packed_deps_T_1508) node _pop_count_packed_deps_T_1510 = bits(_pop_count_packed_deps_T_1509, 2, 0) node _pop_count_packed_deps_T_1511 = add(_pop_count_packed_deps_T_1504, _pop_count_packed_deps_T_1510) node _pop_count_packed_deps_T_1512 = bits(_pop_count_packed_deps_T_1511, 3, 0) node _pop_count_packed_deps_T_1513 = add(entries_st[3].bits.deps_ex[8], entries_st[3].bits.deps_ex[9]) node _pop_count_packed_deps_T_1514 = bits(_pop_count_packed_deps_T_1513, 1, 0) node _pop_count_packed_deps_T_1515 = add(entries_st[3].bits.deps_ex[10], entries_st[3].bits.deps_ex[11]) node _pop_count_packed_deps_T_1516 = bits(_pop_count_packed_deps_T_1515, 1, 0) node _pop_count_packed_deps_T_1517 = add(_pop_count_packed_deps_T_1514, _pop_count_packed_deps_T_1516) node _pop_count_packed_deps_T_1518 = bits(_pop_count_packed_deps_T_1517, 2, 0) node _pop_count_packed_deps_T_1519 = add(entries_st[3].bits.deps_ex[12], entries_st[3].bits.deps_ex[13]) node _pop_count_packed_deps_T_1520 = bits(_pop_count_packed_deps_T_1519, 1, 0) node _pop_count_packed_deps_T_1521 = add(entries_st[3].bits.deps_ex[14], entries_st[3].bits.deps_ex[15]) node _pop_count_packed_deps_T_1522 = bits(_pop_count_packed_deps_T_1521, 1, 0) node _pop_count_packed_deps_T_1523 = add(_pop_count_packed_deps_T_1520, _pop_count_packed_deps_T_1522) node _pop_count_packed_deps_T_1524 = bits(_pop_count_packed_deps_T_1523, 2, 0) node _pop_count_packed_deps_T_1525 = add(_pop_count_packed_deps_T_1518, _pop_count_packed_deps_T_1524) node _pop_count_packed_deps_T_1526 = bits(_pop_count_packed_deps_T_1525, 3, 0) node _pop_count_packed_deps_T_1527 = add(_pop_count_packed_deps_T_1512, _pop_count_packed_deps_T_1526) node _pop_count_packed_deps_T_1528 = bits(_pop_count_packed_deps_T_1527, 4, 0) node _pop_count_packed_deps_T_1529 = add(_pop_count_packed_deps_T_1498, _pop_count_packed_deps_T_1528) node _pop_count_packed_deps_T_1530 = tail(_pop_count_packed_deps_T_1529, 1) node _pop_count_packed_deps_T_1531 = add(entries_st[3].bits.deps_st[0], entries_st[3].bits.deps_st[1]) node _pop_count_packed_deps_T_1532 = bits(_pop_count_packed_deps_T_1531, 1, 0) node _pop_count_packed_deps_T_1533 = add(entries_st[3].bits.deps_st[2], entries_st[3].bits.deps_st[3]) node _pop_count_packed_deps_T_1534 = bits(_pop_count_packed_deps_T_1533, 1, 0) node _pop_count_packed_deps_T_1535 = add(_pop_count_packed_deps_T_1532, _pop_count_packed_deps_T_1534) node _pop_count_packed_deps_T_1536 = bits(_pop_count_packed_deps_T_1535, 2, 0) node _pop_count_packed_deps_T_1537 = add(_pop_count_packed_deps_T_1530, _pop_count_packed_deps_T_1536) node _pop_count_packed_deps_T_1538 = tail(_pop_count_packed_deps_T_1537, 1) node _pop_count_packed_deps_T_1539 = mux(entries_st[3].valid, _pop_count_packed_deps_T_1538, UInt<1>(0h0)) wire pop_count_packed_deps : UInt<5>[28] connect pop_count_packed_deps[0], _pop_count_packed_deps_T_54 connect pop_count_packed_deps[1], _pop_count_packed_deps_T_109 connect pop_count_packed_deps[2], _pop_count_packed_deps_T_164 connect pop_count_packed_deps[3], _pop_count_packed_deps_T_219 connect pop_count_packed_deps[4], _pop_count_packed_deps_T_274 connect pop_count_packed_deps[5], _pop_count_packed_deps_T_329 connect pop_count_packed_deps[6], _pop_count_packed_deps_T_384 connect pop_count_packed_deps[7], _pop_count_packed_deps_T_439 connect pop_count_packed_deps[8], _pop_count_packed_deps_T_494 connect pop_count_packed_deps[9], _pop_count_packed_deps_T_549 connect pop_count_packed_deps[10], _pop_count_packed_deps_T_604 connect pop_count_packed_deps[11], _pop_count_packed_deps_T_659 connect pop_count_packed_deps[12], _pop_count_packed_deps_T_714 connect pop_count_packed_deps[13], _pop_count_packed_deps_T_769 connect pop_count_packed_deps[14], _pop_count_packed_deps_T_824 connect pop_count_packed_deps[15], _pop_count_packed_deps_T_879 connect pop_count_packed_deps[16], _pop_count_packed_deps_T_934 connect pop_count_packed_deps[17], _pop_count_packed_deps_T_989 connect pop_count_packed_deps[18], _pop_count_packed_deps_T_1044 connect pop_count_packed_deps[19], _pop_count_packed_deps_T_1099 connect pop_count_packed_deps[20], _pop_count_packed_deps_T_1154 connect pop_count_packed_deps[21], _pop_count_packed_deps_T_1209 connect pop_count_packed_deps[22], _pop_count_packed_deps_T_1264 connect pop_count_packed_deps[23], _pop_count_packed_deps_T_1319 connect pop_count_packed_deps[24], _pop_count_packed_deps_T_1374 connect pop_count_packed_deps[25], _pop_count_packed_deps_T_1429 connect pop_count_packed_deps[26], _pop_count_packed_deps_T_1484 connect pop_count_packed_deps[27], _pop_count_packed_deps_T_1539 node _min_pop_count_T = lt(pop_count_packed_deps[0], pop_count_packed_deps[1]) node _min_pop_count_T_1 = mux(_min_pop_count_T, pop_count_packed_deps[0], pop_count_packed_deps[1]) node _min_pop_count_T_2 = lt(_min_pop_count_T_1, pop_count_packed_deps[2]) node _min_pop_count_T_3 = mux(_min_pop_count_T_2, _min_pop_count_T_1, pop_count_packed_deps[2]) node _min_pop_count_T_4 = lt(_min_pop_count_T_3, pop_count_packed_deps[3]) node _min_pop_count_T_5 = mux(_min_pop_count_T_4, _min_pop_count_T_3, pop_count_packed_deps[3]) node _min_pop_count_T_6 = lt(_min_pop_count_T_5, pop_count_packed_deps[4]) node _min_pop_count_T_7 = mux(_min_pop_count_T_6, _min_pop_count_T_5, pop_count_packed_deps[4]) node _min_pop_count_T_8 = lt(_min_pop_count_T_7, pop_count_packed_deps[5]) node _min_pop_count_T_9 = mux(_min_pop_count_T_8, _min_pop_count_T_7, pop_count_packed_deps[5]) node _min_pop_count_T_10 = lt(_min_pop_count_T_9, pop_count_packed_deps[6]) node _min_pop_count_T_11 = mux(_min_pop_count_T_10, _min_pop_count_T_9, pop_count_packed_deps[6]) node _min_pop_count_T_12 = lt(_min_pop_count_T_11, pop_count_packed_deps[7]) node _min_pop_count_T_13 = mux(_min_pop_count_T_12, _min_pop_count_T_11, pop_count_packed_deps[7]) node _min_pop_count_T_14 = lt(_min_pop_count_T_13, pop_count_packed_deps[8]) node _min_pop_count_T_15 = mux(_min_pop_count_T_14, _min_pop_count_T_13, pop_count_packed_deps[8]) node _min_pop_count_T_16 = lt(_min_pop_count_T_15, pop_count_packed_deps[9]) node _min_pop_count_T_17 = mux(_min_pop_count_T_16, _min_pop_count_T_15, pop_count_packed_deps[9]) node _min_pop_count_T_18 = lt(_min_pop_count_T_17, pop_count_packed_deps[10]) node _min_pop_count_T_19 = mux(_min_pop_count_T_18, _min_pop_count_T_17, pop_count_packed_deps[10]) node _min_pop_count_T_20 = lt(_min_pop_count_T_19, pop_count_packed_deps[11]) node _min_pop_count_T_21 = mux(_min_pop_count_T_20, _min_pop_count_T_19, pop_count_packed_deps[11]) node _min_pop_count_T_22 = lt(_min_pop_count_T_21, pop_count_packed_deps[12]) node _min_pop_count_T_23 = mux(_min_pop_count_T_22, _min_pop_count_T_21, pop_count_packed_deps[12]) node _min_pop_count_T_24 = lt(_min_pop_count_T_23, pop_count_packed_deps[13]) node _min_pop_count_T_25 = mux(_min_pop_count_T_24, _min_pop_count_T_23, pop_count_packed_deps[13]) node _min_pop_count_T_26 = lt(_min_pop_count_T_25, pop_count_packed_deps[14]) node _min_pop_count_T_27 = mux(_min_pop_count_T_26, _min_pop_count_T_25, pop_count_packed_deps[14]) node _min_pop_count_T_28 = lt(_min_pop_count_T_27, pop_count_packed_deps[15]) node _min_pop_count_T_29 = mux(_min_pop_count_T_28, _min_pop_count_T_27, pop_count_packed_deps[15]) node _min_pop_count_T_30 = lt(_min_pop_count_T_29, pop_count_packed_deps[16]) node _min_pop_count_T_31 = mux(_min_pop_count_T_30, _min_pop_count_T_29, pop_count_packed_deps[16]) node _min_pop_count_T_32 = lt(_min_pop_count_T_31, pop_count_packed_deps[17]) node _min_pop_count_T_33 = mux(_min_pop_count_T_32, _min_pop_count_T_31, pop_count_packed_deps[17]) node _min_pop_count_T_34 = lt(_min_pop_count_T_33, pop_count_packed_deps[18]) node _min_pop_count_T_35 = mux(_min_pop_count_T_34, _min_pop_count_T_33, pop_count_packed_deps[18]) node _min_pop_count_T_36 = lt(_min_pop_count_T_35, pop_count_packed_deps[19]) node _min_pop_count_T_37 = mux(_min_pop_count_T_36, _min_pop_count_T_35, pop_count_packed_deps[19]) node _min_pop_count_T_38 = lt(_min_pop_count_T_37, pop_count_packed_deps[20]) node _min_pop_count_T_39 = mux(_min_pop_count_T_38, _min_pop_count_T_37, pop_count_packed_deps[20]) node _min_pop_count_T_40 = lt(_min_pop_count_T_39, pop_count_packed_deps[21]) node _min_pop_count_T_41 = mux(_min_pop_count_T_40, _min_pop_count_T_39, pop_count_packed_deps[21]) node _min_pop_count_T_42 = lt(_min_pop_count_T_41, pop_count_packed_deps[22]) node _min_pop_count_T_43 = mux(_min_pop_count_T_42, _min_pop_count_T_41, pop_count_packed_deps[22]) node _min_pop_count_T_44 = lt(_min_pop_count_T_43, pop_count_packed_deps[23]) node _min_pop_count_T_45 = mux(_min_pop_count_T_44, _min_pop_count_T_43, pop_count_packed_deps[23]) node _min_pop_count_T_46 = lt(_min_pop_count_T_45, pop_count_packed_deps[24]) node _min_pop_count_T_47 = mux(_min_pop_count_T_46, _min_pop_count_T_45, pop_count_packed_deps[24]) node _min_pop_count_T_48 = lt(_min_pop_count_T_47, pop_count_packed_deps[25]) node _min_pop_count_T_49 = mux(_min_pop_count_T_48, _min_pop_count_T_47, pop_count_packed_deps[25]) node _min_pop_count_T_50 = lt(_min_pop_count_T_49, pop_count_packed_deps[26]) node _min_pop_count_T_51 = mux(_min_pop_count_T_50, _min_pop_count_T_49, pop_count_packed_deps[26]) node _min_pop_count_T_52 = lt(_min_pop_count_T_51, pop_count_packed_deps[27]) node min_pop_count = mux(_min_pop_count_T_52, _min_pop_count_T_51, pop_count_packed_deps[27]) regreset cycles_since_issue : UInt<16>, clock, reset, UInt<16>(0h0) node _T_5013 = and(io.issue.ld.valid, io.issue.ld.ready) node _T_5014 = and(io.issue.st.valid, io.issue.st.ready) node _T_5015 = or(_T_5013, _T_5014) node _T_5016 = and(io.issue.ex.valid, io.issue.ex.ready) node _T_5017 = or(_T_5015, _T_5016) node _T_5018 = eq(io.busy, UInt<1>(0h0)) node _T_5019 = or(_T_5017, _T_5018) node _T_5020 = or(_T_5019, io.completed.valid) when _T_5020 : connect cycles_since_issue, UInt<1>(0h0) else : when io.busy : node _cycles_since_issue_T = add(cycles_since_issue, UInt<1>(0h1)) node _cycles_since_issue_T_1 = tail(_cycles_since_issue_T, 1) connect cycles_since_issue, _cycles_since_issue_T_1 inst plusarg_reader of plusarg_reader_96 node _T_5021 = lt(cycles_since_issue, plusarg_reader.out) node _T_5022 = asUInt(reset) node _T_5023 = eq(_T_5022, UInt<1>(0h0)) when _T_5023 : node _T_5024 = eq(_T_5021, UInt<1>(0h0)) when _T_5024 : printf(clock, UInt<1>(0h1), "Assertion failed: pipeline stall\n at ReservationStation.scala:527 assert(cycles_since_issue < PlusArg(\"gemmini_timeout\", 10000), \"pipeline stall\")\n") : printf_10 assert(clock, _T_5021, UInt<1>(0h1), "") : assert_10 regreset cntr_value : UInt<21>, clock, reset, UInt<21>(0h0) node wrap = eq(cntr_value, UInt<21>(0h1e847f)) node _value_T = add(cntr_value, UInt<1>(0h1)) node _value_T_1 = tail(_value_T, 1) connect cntr_value, _value_T_1 when wrap : connect cntr_value, UInt<1>(0h0) when wrap : node _T_5025 = asUInt(reset) node _T_5026 = eq(_T_5025, UInt<1>(0h0)) when _T_5026 : printf(clock, UInt<1>(0h1), "Utilization: %d\n", utilization) : printf_11 node _T_5027 = asUInt(reset) node _T_5028 = eq(_T_5027, UInt<1>(0h0)) when _T_5028 : printf(clock, UInt<1>(0h1), "Utilization ld q (incomplete): %d\n", utilization_ld_q_unissued) : printf_12 node _T_5029 = asUInt(reset) node _T_5030 = eq(_T_5029, UInt<1>(0h0)) when _T_5030 : printf(clock, UInt<1>(0h1), "Utilization st q (incomplete): %d\n", utilization_st_q_unissued) : printf_13 node _T_5031 = asUInt(reset) node _T_5032 = eq(_T_5031, UInt<1>(0h0)) when _T_5032 : printf(clock, UInt<1>(0h1), "Utilization ex q (incomplete): %d\n", utilization_ex_q_unissued) : printf_14 node _T_5033 = asUInt(reset) node _T_5034 = eq(_T_5033, UInt<1>(0h0)) when _T_5034 : printf(clock, UInt<1>(0h1), "Utilization ld q: %d\n", utilization_ld_q) : printf_15 node _T_5035 = asUInt(reset) node _T_5036 = eq(_T_5035, UInt<1>(0h0)) when _T_5036 : printf(clock, UInt<1>(0h1), "Utilization st q: %d\n", utilization_st_q) : printf_16 node _T_5037 = asUInt(reset) node _T_5038 = eq(_T_5037, UInt<1>(0h0)) when _T_5038 : printf(clock, UInt<1>(0h1), "Utilization ex q: %d\n", utilization_ex_q) : printf_17 node _T_5039 = asUInt(reset) node _T_5040 = eq(_T_5039, UInt<1>(0h0)) when _T_5040 : printf(clock, UInt<1>(0h1), "Packed deps: Vec(%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d)\n", packed_deps[0], packed_deps[1], packed_deps[2], packed_deps[3], packed_deps[4], packed_deps[5], packed_deps[6], packed_deps[7], packed_deps[8], packed_deps[9], packed_deps[10], packed_deps[11], packed_deps[12], packed_deps[13], packed_deps[14], packed_deps[15], packed_deps[16], packed_deps[17], packed_deps[18], packed_deps[19], packed_deps[20], packed_deps[21], packed_deps[22], packed_deps[23], packed_deps[24], packed_deps[25], packed_deps[26], packed_deps[27]) : printf_18 node _T_5041 = asUInt(reset) when _T_5041 : connect entries_ld[0].valid, UInt<1>(0h0) connect entries_ld[1].valid, UInt<1>(0h0) connect entries_ld[2].valid, UInt<1>(0h0) connect entries_ld[3].valid, UInt<1>(0h0) connect entries_ld[4].valid, UInt<1>(0h0) connect entries_ld[5].valid, UInt<1>(0h0) connect entries_ld[6].valid, UInt<1>(0h0) connect entries_ld[7].valid, UInt<1>(0h0) connect entries_ex[0].valid, UInt<1>(0h0) connect entries_ex[1].valid, UInt<1>(0h0) connect entries_ex[2].valid, UInt<1>(0h0) connect entries_ex[3].valid, UInt<1>(0h0) connect entries_ex[4].valid, UInt<1>(0h0) connect entries_ex[5].valid, UInt<1>(0h0) connect entries_ex[6].valid, UInt<1>(0h0) connect entries_ex[7].valid, UInt<1>(0h0) connect entries_ex[8].valid, UInt<1>(0h0) connect entries_ex[9].valid, UInt<1>(0h0) connect entries_ex[10].valid, UInt<1>(0h0) connect entries_ex[11].valid, UInt<1>(0h0) connect entries_ex[12].valid, UInt<1>(0h0) connect entries_ex[13].valid, UInt<1>(0h0) connect entries_ex[14].valid, UInt<1>(0h0) connect entries_ex[15].valid, UInt<1>(0h0) connect entries_st[0].valid, UInt<1>(0h0) connect entries_st[1].valid, UInt<1>(0h0) connect entries_st[2].valid, UInt<1>(0h0) connect entries_st[3].valid, UInt<1>(0h0) wire _WIRE_9 : UInt<1>[45] connect _WIRE_9[0], UInt<1>(0h0) connect _WIRE_9[1], UInt<1>(0h0) connect _WIRE_9[2], UInt<1>(0h0) connect _WIRE_9[3], UInt<1>(0h0) connect _WIRE_9[4], UInt<1>(0h0) connect _WIRE_9[5], UInt<1>(0h0) connect _WIRE_9[6], UInt<1>(0h0) connect _WIRE_9[7], UInt<1>(0h0) connect _WIRE_9[8], UInt<1>(0h0) connect _WIRE_9[9], UInt<1>(0h0) connect _WIRE_9[10], UInt<1>(0h0) connect _WIRE_9[11], UInt<1>(0h0) connect _WIRE_9[12], UInt<1>(0h0) connect _WIRE_9[13], UInt<1>(0h0) connect _WIRE_9[14], UInt<1>(0h0) connect _WIRE_9[15], UInt<1>(0h0) connect _WIRE_9[16], UInt<1>(0h0) connect _WIRE_9[17], UInt<1>(0h0) connect _WIRE_9[18], UInt<1>(0h0) connect _WIRE_9[19], UInt<1>(0h0) connect _WIRE_9[20], UInt<1>(0h0) connect _WIRE_9[21], UInt<1>(0h0) connect _WIRE_9[22], UInt<1>(0h0) connect _WIRE_9[23], UInt<1>(0h0) connect _WIRE_9[24], UInt<1>(0h0) connect _WIRE_9[25], UInt<1>(0h0) connect _WIRE_9[26], UInt<1>(0h0) connect _WIRE_9[27], UInt<1>(0h0) connect _WIRE_9[28], UInt<1>(0h0) connect _WIRE_9[29], UInt<1>(0h0) connect _WIRE_9[30], UInt<1>(0h0) connect _WIRE_9[31], UInt<1>(0h0) connect _WIRE_9[32], UInt<1>(0h0) connect _WIRE_9[33], UInt<1>(0h0) connect _WIRE_9[34], UInt<1>(0h0) connect _WIRE_9[35], UInt<1>(0h0) connect _WIRE_9[36], UInt<1>(0h0) connect _WIRE_9[37], UInt<1>(0h0) connect _WIRE_9[38], UInt<1>(0h0) connect _WIRE_9[39], UInt<1>(0h0) connect _WIRE_9[40], UInt<1>(0h0) connect _WIRE_9[41], UInt<1>(0h0) connect _WIRE_9[42], UInt<1>(0h0) connect _WIRE_9[43], UInt<1>(0h0) connect _WIRE_9[44], UInt<1>(0h0) connect io.counter.event_signal, _WIRE_9 wire _WIRE_10 : UInt<32>[8] connect _WIRE_10[0], UInt<32>(0h0) connect _WIRE_10[1], UInt<32>(0h0) connect _WIRE_10[2], UInt<32>(0h0) connect _WIRE_10[3], UInt<32>(0h0) connect _WIRE_10[4], UInt<32>(0h0) connect _WIRE_10[5], UInt<32>(0h0) connect _WIRE_10[6], UInt<32>(0h0) connect _WIRE_10[7], UInt<32>(0h0) connect io.counter.external_values, _WIRE_10 connect io.counter.external_values[1], utilization_ld_q connect io.counter.external_values[2], utilization_st_q connect io.counter.external_values[3], utilization_ex_q connect io.counter.event_signal[42], io.busy node _T_5042 = eq(io.alloc.ready, UInt<1>(0h0)) connect io.counter.event_signal[41], _T_5042
module ReservationStation( // @[ReservationStation.scala:26:7] input clock, // @[ReservationStation.scala:26:7] input reset, // @[ReservationStation.scala:26:7] output io_alloc_ready, // @[ReservationStation.scala:35:14] input io_alloc_valid, // @[ReservationStation.scala:35:14] input [6:0] io_alloc_bits_cmd_inst_funct, // @[ReservationStation.scala:35:14] input [4:0] io_alloc_bits_cmd_inst_rs2, // @[ReservationStation.scala:35:14] input [4:0] io_alloc_bits_cmd_inst_rs1, // @[ReservationStation.scala:35:14] input io_alloc_bits_cmd_inst_xd, // @[ReservationStation.scala:35:14] input io_alloc_bits_cmd_inst_xs1, // @[ReservationStation.scala:35:14] input io_alloc_bits_cmd_inst_xs2, // @[ReservationStation.scala:35:14] input [4:0] io_alloc_bits_cmd_inst_rd, // @[ReservationStation.scala:35:14] input [6:0] io_alloc_bits_cmd_inst_opcode, // @[ReservationStation.scala:35:14] input [63:0] io_alloc_bits_cmd_rs1, // @[ReservationStation.scala:35:14] input [63:0] io_alloc_bits_cmd_rs2, // @[ReservationStation.scala:35:14] input io_alloc_bits_cmd_status_debug, // @[ReservationStation.scala:35:14] input io_alloc_bits_cmd_status_cease, // @[ReservationStation.scala:35:14] input io_alloc_bits_cmd_status_wfi, // @[ReservationStation.scala:35:14] input [31:0] io_alloc_bits_cmd_status_isa, // @[ReservationStation.scala:35:14] input [1:0] io_alloc_bits_cmd_status_dprv, // @[ReservationStation.scala:35:14] input io_alloc_bits_cmd_status_dv, // @[ReservationStation.scala:35:14] input [1:0] io_alloc_bits_cmd_status_prv, // @[ReservationStation.scala:35:14] input io_alloc_bits_cmd_status_v, // @[ReservationStation.scala:35:14] input io_alloc_bits_cmd_status_sd, // @[ReservationStation.scala:35:14] input [22:0] io_alloc_bits_cmd_status_zero2, // @[ReservationStation.scala:35:14] input io_alloc_bits_cmd_status_mpv, // @[ReservationStation.scala:35:14] input io_alloc_bits_cmd_status_gva, // @[ReservationStation.scala:35:14] input io_alloc_bits_cmd_status_mbe, // @[ReservationStation.scala:35:14] input io_alloc_bits_cmd_status_sbe, // @[ReservationStation.scala:35:14] input [1:0] io_alloc_bits_cmd_status_sxl, // @[ReservationStation.scala:35:14] input [1:0] io_alloc_bits_cmd_status_uxl, // @[ReservationStation.scala:35:14] input io_alloc_bits_cmd_status_sd_rv32, // @[ReservationStation.scala:35:14] input [7:0] io_alloc_bits_cmd_status_zero1, // @[ReservationStation.scala:35:14] input io_alloc_bits_cmd_status_tsr, // @[ReservationStation.scala:35:14] input io_alloc_bits_cmd_status_tw, // @[ReservationStation.scala:35:14] input io_alloc_bits_cmd_status_tvm, // @[ReservationStation.scala:35:14] input io_alloc_bits_cmd_status_mxr, // @[ReservationStation.scala:35:14] input io_alloc_bits_cmd_status_sum, // @[ReservationStation.scala:35:14] input io_alloc_bits_cmd_status_mprv, // @[ReservationStation.scala:35:14] input [1:0] io_alloc_bits_cmd_status_xs, // @[ReservationStation.scala:35:14] input [1:0] io_alloc_bits_cmd_status_fs, // @[ReservationStation.scala:35:14] input [1:0] io_alloc_bits_cmd_status_mpp, // @[ReservationStation.scala:35:14] input [1:0] io_alloc_bits_cmd_status_vs, // @[ReservationStation.scala:35:14] input io_alloc_bits_cmd_status_spp, // @[ReservationStation.scala:35:14] input io_alloc_bits_cmd_status_mpie, // @[ReservationStation.scala:35:14] input io_alloc_bits_cmd_status_ube, // @[ReservationStation.scala:35:14] input io_alloc_bits_cmd_status_spie, // @[ReservationStation.scala:35:14] input io_alloc_bits_cmd_status_upie, // @[ReservationStation.scala:35:14] input io_alloc_bits_cmd_status_mie, // @[ReservationStation.scala:35:14] input io_alloc_bits_cmd_status_hie, // @[ReservationStation.scala:35:14] input io_alloc_bits_cmd_status_sie, // @[ReservationStation.scala:35:14] input io_alloc_bits_cmd_status_uie, // @[ReservationStation.scala:35:14] input io_alloc_bits_rob_id_valid, // @[ReservationStation.scala:35:14] input [5:0] io_alloc_bits_rob_id_bits, // @[ReservationStation.scala:35:14] input io_alloc_bits_from_matmul_fsm, // @[ReservationStation.scala:35:14] input io_alloc_bits_from_conv_fsm, // @[ReservationStation.scala:35:14] input io_completed_valid, // @[ReservationStation.scala:35:14] input [5:0] io_completed_bits, // @[ReservationStation.scala:35:14] output io_issue_ld_valid, // @[ReservationStation.scala:35:14] input io_issue_ld_ready, // @[ReservationStation.scala:35:14] output [6:0] io_issue_ld_cmd_cmd_inst_funct, // @[ReservationStation.scala:35:14] output [4:0] io_issue_ld_cmd_cmd_inst_rs2, // @[ReservationStation.scala:35:14] output [4:0] io_issue_ld_cmd_cmd_inst_rs1, // @[ReservationStation.scala:35:14] output io_issue_ld_cmd_cmd_inst_xd, // @[ReservationStation.scala:35:14] output io_issue_ld_cmd_cmd_inst_xs1, // @[ReservationStation.scala:35:14] output io_issue_ld_cmd_cmd_inst_xs2, // @[ReservationStation.scala:35:14] output [4:0] io_issue_ld_cmd_cmd_inst_rd, // @[ReservationStation.scala:35:14] output [6:0] io_issue_ld_cmd_cmd_inst_opcode, // @[ReservationStation.scala:35:14] output [63:0] io_issue_ld_cmd_cmd_rs1, // @[ReservationStation.scala:35:14] output [63:0] io_issue_ld_cmd_cmd_rs2, // @[ReservationStation.scala:35:14] output io_issue_ld_cmd_cmd_status_debug, // @[ReservationStation.scala:35:14] output io_issue_ld_cmd_cmd_status_cease, // @[ReservationStation.scala:35:14] output io_issue_ld_cmd_cmd_status_wfi, // @[ReservationStation.scala:35:14] output [31:0] io_issue_ld_cmd_cmd_status_isa, // @[ReservationStation.scala:35:14] output [1:0] io_issue_ld_cmd_cmd_status_dprv, // @[ReservationStation.scala:35:14] output io_issue_ld_cmd_cmd_status_dv, // @[ReservationStation.scala:35:14] output [1:0] io_issue_ld_cmd_cmd_status_prv, // @[ReservationStation.scala:35:14] output io_issue_ld_cmd_cmd_status_v, // @[ReservationStation.scala:35:14] output io_issue_ld_cmd_cmd_status_sd, // @[ReservationStation.scala:35:14] output [22:0] io_issue_ld_cmd_cmd_status_zero2, // @[ReservationStation.scala:35:14] output io_issue_ld_cmd_cmd_status_mpv, // @[ReservationStation.scala:35:14] output io_issue_ld_cmd_cmd_status_gva, // @[ReservationStation.scala:35:14] output io_issue_ld_cmd_cmd_status_mbe, // @[ReservationStation.scala:35:14] output io_issue_ld_cmd_cmd_status_sbe, // @[ReservationStation.scala:35:14] output [1:0] io_issue_ld_cmd_cmd_status_sxl, // @[ReservationStation.scala:35:14] output [1:0] io_issue_ld_cmd_cmd_status_uxl, // @[ReservationStation.scala:35:14] output io_issue_ld_cmd_cmd_status_sd_rv32, // @[ReservationStation.scala:35:14] output [7:0] io_issue_ld_cmd_cmd_status_zero1, // @[ReservationStation.scala:35:14] output io_issue_ld_cmd_cmd_status_tsr, // @[ReservationStation.scala:35:14] output io_issue_ld_cmd_cmd_status_tw, // @[ReservationStation.scala:35:14] output io_issue_ld_cmd_cmd_status_tvm, // @[ReservationStation.scala:35:14] output io_issue_ld_cmd_cmd_status_mxr, // @[ReservationStation.scala:35:14] output io_issue_ld_cmd_cmd_status_sum, // @[ReservationStation.scala:35:14] output io_issue_ld_cmd_cmd_status_mprv, // @[ReservationStation.scala:35:14] output [1:0] io_issue_ld_cmd_cmd_status_xs, // @[ReservationStation.scala:35:14] output [1:0] io_issue_ld_cmd_cmd_status_fs, // @[ReservationStation.scala:35:14] output [1:0] io_issue_ld_cmd_cmd_status_mpp, // @[ReservationStation.scala:35:14] output [1:0] io_issue_ld_cmd_cmd_status_vs, // @[ReservationStation.scala:35:14] output io_issue_ld_cmd_cmd_status_spp, // @[ReservationStation.scala:35:14] output io_issue_ld_cmd_cmd_status_mpie, // @[ReservationStation.scala:35:14] output io_issue_ld_cmd_cmd_status_ube, // @[ReservationStation.scala:35:14] output io_issue_ld_cmd_cmd_status_spie, // @[ReservationStation.scala:35:14] output io_issue_ld_cmd_cmd_status_upie, // @[ReservationStation.scala:35:14] output io_issue_ld_cmd_cmd_status_mie, // @[ReservationStation.scala:35:14] output io_issue_ld_cmd_cmd_status_hie, // @[ReservationStation.scala:35:14] output io_issue_ld_cmd_cmd_status_sie, // @[ReservationStation.scala:35:14] output io_issue_ld_cmd_cmd_status_uie, // @[ReservationStation.scala:35:14] output io_issue_ld_cmd_from_matmul_fsm, // @[ReservationStation.scala:35:14] output io_issue_ld_cmd_from_conv_fsm, // @[ReservationStation.scala:35:14] output [5:0] io_issue_ld_rob_id, // @[ReservationStation.scala:35:14] output io_issue_st_valid, // @[ReservationStation.scala:35:14] input io_issue_st_ready, // @[ReservationStation.scala:35:14] output [6:0] io_issue_st_cmd_cmd_inst_funct, // @[ReservationStation.scala:35:14] output [4:0] io_issue_st_cmd_cmd_inst_rs2, // @[ReservationStation.scala:35:14] output [4:0] io_issue_st_cmd_cmd_inst_rs1, // @[ReservationStation.scala:35:14] output io_issue_st_cmd_cmd_inst_xd, // @[ReservationStation.scala:35:14] output io_issue_st_cmd_cmd_inst_xs1, // @[ReservationStation.scala:35:14] output io_issue_st_cmd_cmd_inst_xs2, // @[ReservationStation.scala:35:14] output [4:0] io_issue_st_cmd_cmd_inst_rd, // @[ReservationStation.scala:35:14] output [6:0] io_issue_st_cmd_cmd_inst_opcode, // @[ReservationStation.scala:35:14] output [63:0] io_issue_st_cmd_cmd_rs1, // @[ReservationStation.scala:35:14] output [63:0] io_issue_st_cmd_cmd_rs2, // @[ReservationStation.scala:35:14] output io_issue_st_cmd_cmd_status_debug, // @[ReservationStation.scala:35:14] output io_issue_st_cmd_cmd_status_cease, // @[ReservationStation.scala:35:14] output io_issue_st_cmd_cmd_status_wfi, // @[ReservationStation.scala:35:14] output [31:0] io_issue_st_cmd_cmd_status_isa, // @[ReservationStation.scala:35:14] output [1:0] io_issue_st_cmd_cmd_status_dprv, // @[ReservationStation.scala:35:14] output io_issue_st_cmd_cmd_status_dv, // @[ReservationStation.scala:35:14] output [1:0] io_issue_st_cmd_cmd_status_prv, // @[ReservationStation.scala:35:14] output io_issue_st_cmd_cmd_status_v, // @[ReservationStation.scala:35:14] output io_issue_st_cmd_cmd_status_sd, // @[ReservationStation.scala:35:14] output [22:0] io_issue_st_cmd_cmd_status_zero2, // @[ReservationStation.scala:35:14] output io_issue_st_cmd_cmd_status_mpv, // @[ReservationStation.scala:35:14] output io_issue_st_cmd_cmd_status_gva, // @[ReservationStation.scala:35:14] output io_issue_st_cmd_cmd_status_mbe, // @[ReservationStation.scala:35:14] output io_issue_st_cmd_cmd_status_sbe, // @[ReservationStation.scala:35:14] output [1:0] io_issue_st_cmd_cmd_status_sxl, // @[ReservationStation.scala:35:14] output [1:0] io_issue_st_cmd_cmd_status_uxl, // @[ReservationStation.scala:35:14] output io_issue_st_cmd_cmd_status_sd_rv32, // @[ReservationStation.scala:35:14] output [7:0] io_issue_st_cmd_cmd_status_zero1, // @[ReservationStation.scala:35:14] output io_issue_st_cmd_cmd_status_tsr, // @[ReservationStation.scala:35:14] output io_issue_st_cmd_cmd_status_tw, // @[ReservationStation.scala:35:14] output io_issue_st_cmd_cmd_status_tvm, // @[ReservationStation.scala:35:14] output io_issue_st_cmd_cmd_status_mxr, // @[ReservationStation.scala:35:14] output io_issue_st_cmd_cmd_status_sum, // @[ReservationStation.scala:35:14] output io_issue_st_cmd_cmd_status_mprv, // @[ReservationStation.scala:35:14] output [1:0] io_issue_st_cmd_cmd_status_xs, // @[ReservationStation.scala:35:14] output [1:0] io_issue_st_cmd_cmd_status_fs, // @[ReservationStation.scala:35:14] output [1:0] io_issue_st_cmd_cmd_status_mpp, // @[ReservationStation.scala:35:14] output [1:0] io_issue_st_cmd_cmd_status_vs, // @[ReservationStation.scala:35:14] output io_issue_st_cmd_cmd_status_spp, // @[ReservationStation.scala:35:14] output io_issue_st_cmd_cmd_status_mpie, // @[ReservationStation.scala:35:14] output io_issue_st_cmd_cmd_status_ube, // @[ReservationStation.scala:35:14] output io_issue_st_cmd_cmd_status_spie, // @[ReservationStation.scala:35:14] output io_issue_st_cmd_cmd_status_upie, // @[ReservationStation.scala:35:14] output io_issue_st_cmd_cmd_status_mie, // @[ReservationStation.scala:35:14] output io_issue_st_cmd_cmd_status_hie, // @[ReservationStation.scala:35:14] output io_issue_st_cmd_cmd_status_sie, // @[ReservationStation.scala:35:14] output io_issue_st_cmd_cmd_status_uie, // @[ReservationStation.scala:35:14] output io_issue_st_cmd_from_matmul_fsm, // @[ReservationStation.scala:35:14] output io_issue_st_cmd_from_conv_fsm, // @[ReservationStation.scala:35:14] output [5:0] io_issue_st_rob_id, // @[ReservationStation.scala:35:14] output io_issue_ex_valid, // @[ReservationStation.scala:35:14] input io_issue_ex_ready, // @[ReservationStation.scala:35:14] output [6:0] io_issue_ex_cmd_cmd_inst_funct, // @[ReservationStation.scala:35:14] output [4:0] io_issue_ex_cmd_cmd_inst_rs2, // @[ReservationStation.scala:35:14] output [4:0] io_issue_ex_cmd_cmd_inst_rs1, // @[ReservationStation.scala:35:14] output io_issue_ex_cmd_cmd_inst_xd, // @[ReservationStation.scala:35:14] output io_issue_ex_cmd_cmd_inst_xs1, // @[ReservationStation.scala:35:14] output io_issue_ex_cmd_cmd_inst_xs2, // @[ReservationStation.scala:35:14] output [4:0] io_issue_ex_cmd_cmd_inst_rd, // @[ReservationStation.scala:35:14] output [6:0] io_issue_ex_cmd_cmd_inst_opcode, // @[ReservationStation.scala:35:14] output [63:0] io_issue_ex_cmd_cmd_rs1, // @[ReservationStation.scala:35:14] output [63:0] io_issue_ex_cmd_cmd_rs2, // @[ReservationStation.scala:35:14] output io_issue_ex_cmd_cmd_status_debug, // @[ReservationStation.scala:35:14] output io_issue_ex_cmd_cmd_status_cease, // @[ReservationStation.scala:35:14] output io_issue_ex_cmd_cmd_status_wfi, // @[ReservationStation.scala:35:14] output [31:0] io_issue_ex_cmd_cmd_status_isa, // @[ReservationStation.scala:35:14] output [1:0] io_issue_ex_cmd_cmd_status_dprv, // @[ReservationStation.scala:35:14] output io_issue_ex_cmd_cmd_status_dv, // @[ReservationStation.scala:35:14] output [1:0] io_issue_ex_cmd_cmd_status_prv, // @[ReservationStation.scala:35:14] output io_issue_ex_cmd_cmd_status_v, // @[ReservationStation.scala:35:14] output io_issue_ex_cmd_cmd_status_sd, // @[ReservationStation.scala:35:14] output [22:0] io_issue_ex_cmd_cmd_status_zero2, // @[ReservationStation.scala:35:14] output io_issue_ex_cmd_cmd_status_mpv, // @[ReservationStation.scala:35:14] output io_issue_ex_cmd_cmd_status_gva, // @[ReservationStation.scala:35:14] output io_issue_ex_cmd_cmd_status_mbe, // @[ReservationStation.scala:35:14] output io_issue_ex_cmd_cmd_status_sbe, // @[ReservationStation.scala:35:14] output [1:0] io_issue_ex_cmd_cmd_status_sxl, // @[ReservationStation.scala:35:14] output [1:0] io_issue_ex_cmd_cmd_status_uxl, // @[ReservationStation.scala:35:14] output io_issue_ex_cmd_cmd_status_sd_rv32, // @[ReservationStation.scala:35:14] output [7:0] io_issue_ex_cmd_cmd_status_zero1, // @[ReservationStation.scala:35:14] output io_issue_ex_cmd_cmd_status_tsr, // @[ReservationStation.scala:35:14] output io_issue_ex_cmd_cmd_status_tw, // @[ReservationStation.scala:35:14] output io_issue_ex_cmd_cmd_status_tvm, // @[ReservationStation.scala:35:14] output io_issue_ex_cmd_cmd_status_mxr, // @[ReservationStation.scala:35:14] output io_issue_ex_cmd_cmd_status_sum, // @[ReservationStation.scala:35:14] output io_issue_ex_cmd_cmd_status_mprv, // @[ReservationStation.scala:35:14] output [1:0] io_issue_ex_cmd_cmd_status_xs, // @[ReservationStation.scala:35:14] output [1:0] io_issue_ex_cmd_cmd_status_fs, // @[ReservationStation.scala:35:14] output [1:0] io_issue_ex_cmd_cmd_status_mpp, // @[ReservationStation.scala:35:14] output [1:0] io_issue_ex_cmd_cmd_status_vs, // @[ReservationStation.scala:35:14] output io_issue_ex_cmd_cmd_status_spp, // @[ReservationStation.scala:35:14] output io_issue_ex_cmd_cmd_status_mpie, // @[ReservationStation.scala:35:14] output io_issue_ex_cmd_cmd_status_ube, // @[ReservationStation.scala:35:14] output io_issue_ex_cmd_cmd_status_spie, // @[ReservationStation.scala:35:14] output io_issue_ex_cmd_cmd_status_upie, // @[ReservationStation.scala:35:14] output io_issue_ex_cmd_cmd_status_mie, // @[ReservationStation.scala:35:14] output io_issue_ex_cmd_cmd_status_hie, // @[ReservationStation.scala:35:14] output io_issue_ex_cmd_cmd_status_sie, // @[ReservationStation.scala:35:14] output io_issue_ex_cmd_cmd_status_uie, // @[ReservationStation.scala:35:14] output io_issue_ex_cmd_from_matmul_fsm, // @[ReservationStation.scala:35:14] output io_issue_ex_cmd_from_conv_fsm, // @[ReservationStation.scala:35:14] output [5:0] io_issue_ex_rob_id, // @[ReservationStation.scala:35:14] output [1:0] io_conv_ld_completed, // @[ReservationStation.scala:35:14] output [1:0] io_conv_ex_completed, // @[ReservationStation.scala:35:14] output [1:0] io_conv_st_completed, // @[ReservationStation.scala:35:14] output [1:0] io_matmul_ld_completed, // @[ReservationStation.scala:35:14] output [1:0] io_matmul_ex_completed, // @[ReservationStation.scala:35:14] output [1:0] io_matmul_st_completed, // @[ReservationStation.scala:35:14] output io_busy, // @[ReservationStation.scala:35:14] output io_counter_event_signal_41, // @[ReservationStation.scala:35:14] output io_counter_event_signal_42, // @[ReservationStation.scala:35:14] output [31:0] io_counter_external_values_1, // @[ReservationStation.scala:35:14] output [31:0] io_counter_external_values_2, // @[ReservationStation.scala:35:14] output [31:0] io_counter_external_values_3, // @[ReservationStation.scala:35:14] input io_counter_external_reset // @[ReservationStation.scala:35:14] ); wire start_garbage_bit; // @[ReservationStation.scala:281:44] wire [10:0] start_garbage; // @[ReservationStation.scala:281:44] wire [2:0] start_norm_cmd; // @[ReservationStation.scala:281:44] wire start_read_full_acc_row; // @[ReservationStation.scala:281:44] wire start_accumulate; // @[ReservationStation.scala:281:44] wire start_is_acc_addr; // @[ReservationStation.scala:281:44] wire dst_bits_start_garbage_bit; // @[ReservationStation.scala:202:19] wire [10:0] dst_bits_start_garbage; // @[ReservationStation.scala:202:19] wire [2:0] dst_bits_start_norm_cmd; // @[ReservationStation.scala:202:19] wire dst_bits_start_read_full_acc_row; // @[ReservationStation.scala:202:19] wire dst_bits_start_accumulate; // @[ReservationStation.scala:202:19] wire dst_bits_start_is_acc_addr; // @[ReservationStation.scala:202:19] wire op2_bits_start_garbage_bit; // @[ReservationStation.scala:199:19] wire [10:0] op2_bits_start_garbage; // @[ReservationStation.scala:199:19] wire [2:0] op2_bits_start_norm_cmd; // @[ReservationStation.scala:199:19] wire op2_bits_start_read_full_acc_row; // @[ReservationStation.scala:199:19] wire op2_bits_start_accumulate; // @[ReservationStation.scala:199:19] wire op2_bits_start_is_acc_addr; // @[ReservationStation.scala:199:19] wire op1_bits_start_garbage_bit; // @[ReservationStation.scala:196:19] wire [10:0] op1_bits_start_garbage; // @[ReservationStation.scala:196:19] wire [2:0] op1_bits_start_norm_cmd; // @[ReservationStation.scala:196:19] wire op1_bits_start_read_full_acc_row; // @[ReservationStation.scala:196:19] wire op1_bits_start_accumulate; // @[ReservationStation.scala:196:19] wire op1_bits_start_is_acc_addr; // @[ReservationStation.scala:196:19] wire io_busy_0; // @[ReservationStation.scala:26:7] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_alloc_valid_0 = io_alloc_valid; // @[ReservationStation.scala:26:7] wire [6:0] io_alloc_bits_cmd_inst_funct_0 = io_alloc_bits_cmd_inst_funct; // @[ReservationStation.scala:26:7] wire [4:0] io_alloc_bits_cmd_inst_rs2_0 = io_alloc_bits_cmd_inst_rs2; // @[ReservationStation.scala:26:7] wire [4:0] io_alloc_bits_cmd_inst_rs1_0 = io_alloc_bits_cmd_inst_rs1; // @[ReservationStation.scala:26:7] wire io_alloc_bits_cmd_inst_xd_0 = io_alloc_bits_cmd_inst_xd; // @[ReservationStation.scala:26:7] wire io_alloc_bits_cmd_inst_xs1_0 = io_alloc_bits_cmd_inst_xs1; // @[ReservationStation.scala:26:7] wire io_alloc_bits_cmd_inst_xs2_0 = io_alloc_bits_cmd_inst_xs2; // @[ReservationStation.scala:26:7] wire [4:0] io_alloc_bits_cmd_inst_rd_0 = io_alloc_bits_cmd_inst_rd; // @[ReservationStation.scala:26:7] wire [6:0] io_alloc_bits_cmd_inst_opcode_0 = io_alloc_bits_cmd_inst_opcode; // @[ReservationStation.scala:26:7] wire [63:0] io_alloc_bits_cmd_rs1_0 = io_alloc_bits_cmd_rs1; // @[ReservationStation.scala:26:7] wire [63:0] io_alloc_bits_cmd_rs2_0 = io_alloc_bits_cmd_rs2; // @[ReservationStation.scala:26:7] wire io_alloc_bits_cmd_status_debug_0 = io_alloc_bits_cmd_status_debug; // @[ReservationStation.scala:26:7] wire io_alloc_bits_cmd_status_cease_0 = io_alloc_bits_cmd_status_cease; // @[ReservationStation.scala:26:7] wire io_alloc_bits_cmd_status_wfi_0 = io_alloc_bits_cmd_status_wfi; // @[ReservationStation.scala:26:7] wire [31:0] io_alloc_bits_cmd_status_isa_0 = io_alloc_bits_cmd_status_isa; // @[ReservationStation.scala:26:7] wire [1:0] io_alloc_bits_cmd_status_dprv_0 = io_alloc_bits_cmd_status_dprv; // @[ReservationStation.scala:26:7] wire io_alloc_bits_cmd_status_dv_0 = io_alloc_bits_cmd_status_dv; // @[ReservationStation.scala:26:7] wire [1:0] io_alloc_bits_cmd_status_prv_0 = io_alloc_bits_cmd_status_prv; // @[ReservationStation.scala:26:7] wire io_alloc_bits_cmd_status_v_0 = io_alloc_bits_cmd_status_v; // @[ReservationStation.scala:26:7] wire io_alloc_bits_cmd_status_sd_0 = io_alloc_bits_cmd_status_sd; // @[ReservationStation.scala:26:7] wire [22:0] io_alloc_bits_cmd_status_zero2_0 = io_alloc_bits_cmd_status_zero2; // @[ReservationStation.scala:26:7] wire io_alloc_bits_cmd_status_mpv_0 = io_alloc_bits_cmd_status_mpv; // @[ReservationStation.scala:26:7] wire io_alloc_bits_cmd_status_gva_0 = io_alloc_bits_cmd_status_gva; // @[ReservationStation.scala:26:7] wire io_alloc_bits_cmd_status_mbe_0 = io_alloc_bits_cmd_status_mbe; // @[ReservationStation.scala:26:7] wire io_alloc_bits_cmd_status_sbe_0 = io_alloc_bits_cmd_status_sbe; // @[ReservationStation.scala:26:7] wire [1:0] io_alloc_bits_cmd_status_sxl_0 = io_alloc_bits_cmd_status_sxl; // @[ReservationStation.scala:26:7] wire [1:0] io_alloc_bits_cmd_status_uxl_0 = io_alloc_bits_cmd_status_uxl; // @[ReservationStation.scala:26:7] wire io_alloc_bits_cmd_status_sd_rv32_0 = io_alloc_bits_cmd_status_sd_rv32; // @[ReservationStation.scala:26:7] wire [7:0] io_alloc_bits_cmd_status_zero1_0 = io_alloc_bits_cmd_status_zero1; // @[ReservationStation.scala:26:7] wire io_alloc_bits_cmd_status_tsr_0 = io_alloc_bits_cmd_status_tsr; // @[ReservationStation.scala:26:7] wire io_alloc_bits_cmd_status_tw_0 = io_alloc_bits_cmd_status_tw; // @[ReservationStation.scala:26:7] wire io_alloc_bits_cmd_status_tvm_0 = io_alloc_bits_cmd_status_tvm; // @[ReservationStation.scala:26:7] wire io_alloc_bits_cmd_status_mxr_0 = io_alloc_bits_cmd_status_mxr; // @[ReservationStation.scala:26:7] wire io_alloc_bits_cmd_status_sum_0 = io_alloc_bits_cmd_status_sum; // @[ReservationStation.scala:26:7] wire io_alloc_bits_cmd_status_mprv_0 = io_alloc_bits_cmd_status_mprv; // @[ReservationStation.scala:26:7] wire [1:0] io_alloc_bits_cmd_status_xs_0 = io_alloc_bits_cmd_status_xs; // @[ReservationStation.scala:26:7] wire [1:0] io_alloc_bits_cmd_status_fs_0 = io_alloc_bits_cmd_status_fs; // @[ReservationStation.scala:26:7] wire [1:0] io_alloc_bits_cmd_status_mpp_0 = io_alloc_bits_cmd_status_mpp; // @[ReservationStation.scala:26:7] wire [1:0] io_alloc_bits_cmd_status_vs_0 = io_alloc_bits_cmd_status_vs; // @[ReservationStation.scala:26:7] wire io_alloc_bits_cmd_status_spp_0 = io_alloc_bits_cmd_status_spp; // @[ReservationStation.scala:26:7] wire io_alloc_bits_cmd_status_mpie_0 = io_alloc_bits_cmd_status_mpie; // @[ReservationStation.scala:26:7] wire io_alloc_bits_cmd_status_ube_0 = io_alloc_bits_cmd_status_ube; // @[ReservationStation.scala:26:7] wire io_alloc_bits_cmd_status_spie_0 = io_alloc_bits_cmd_status_spie; // @[ReservationStation.scala:26:7] wire io_alloc_bits_cmd_status_upie_0 = io_alloc_bits_cmd_status_upie; // @[ReservationStation.scala:26:7] wire io_alloc_bits_cmd_status_mie_0 = io_alloc_bits_cmd_status_mie; // @[ReservationStation.scala:26:7] wire io_alloc_bits_cmd_status_hie_0 = io_alloc_bits_cmd_status_hie; // @[ReservationStation.scala:26:7] wire io_alloc_bits_cmd_status_sie_0 = io_alloc_bits_cmd_status_sie; // @[ReservationStation.scala:26:7] wire io_alloc_bits_cmd_status_uie_0 = io_alloc_bits_cmd_status_uie; // @[ReservationStation.scala:26:7] wire io_alloc_bits_rob_id_valid_0 = io_alloc_bits_rob_id_valid; // @[ReservationStation.scala:26:7] wire [5:0] io_alloc_bits_rob_id_bits_0 = io_alloc_bits_rob_id_bits; // @[ReservationStation.scala:26:7] wire io_alloc_bits_from_matmul_fsm_0 = io_alloc_bits_from_matmul_fsm; // @[ReservationStation.scala:26:7] wire io_alloc_bits_from_conv_fsm_0 = io_alloc_bits_from_conv_fsm; // @[ReservationStation.scala:26:7] wire io_completed_valid_0 = io_completed_valid; // @[ReservationStation.scala:26:7] wire [5:0] io_completed_bits_0 = io_completed_bits; // @[ReservationStation.scala:26:7] wire io_issue_ld_ready_0 = io_issue_ld_ready; // @[ReservationStation.scala:26:7] wire io_issue_st_ready_0 = io_issue_st_ready; // @[ReservationStation.scala:26:7] wire io_issue_ex_ready_0 = io_issue_ex_ready; // @[ReservationStation.scala:26:7] wire io_counter_external_reset_0 = io_counter_external_reset; // @[ReservationStation.scala:26:7] wire io_counter_event_signal_0 = 1'h0; // @[ReservationStation.scala:26:7] wire io_counter_event_signal_1 = 1'h0; // @[ReservationStation.scala:26:7] wire io_counter_event_signal_2 = 1'h0; // @[ReservationStation.scala:26:7] wire io_counter_event_signal_3 = 1'h0; // @[ReservationStation.scala:26:7] wire io_counter_event_signal_4 = 1'h0; // @[ReservationStation.scala:26:7] wire io_counter_event_signal_5 = 1'h0; // @[ReservationStation.scala:26:7] wire io_counter_event_signal_6 = 1'h0; // @[ReservationStation.scala:26:7] wire io_counter_event_signal_7 = 1'h0; // @[ReservationStation.scala:26:7] wire io_counter_event_signal_8 = 1'h0; // @[ReservationStation.scala:26:7] wire io_counter_event_signal_9 = 1'h0; // @[ReservationStation.scala:26:7] wire io_counter_event_signal_10 = 1'h0; // @[ReservationStation.scala:26:7] wire io_counter_event_signal_11 = 1'h0; // @[ReservationStation.scala:26:7] wire io_counter_event_signal_12 = 1'h0; // @[ReservationStation.scala:26:7] wire io_counter_event_signal_13 = 1'h0; // @[ReservationStation.scala:26:7] wire io_counter_event_signal_14 = 1'h0; // @[ReservationStation.scala:26:7] wire io_counter_event_signal_15 = 1'h0; // @[ReservationStation.scala:26:7] wire io_counter_event_signal_16 = 1'h0; // @[ReservationStation.scala:26:7] wire io_counter_event_signal_17 = 1'h0; // @[ReservationStation.scala:26:7] wire io_counter_event_signal_18 = 1'h0; // @[ReservationStation.scala:26:7] wire io_counter_event_signal_19 = 1'h0; // @[ReservationStation.scala:26:7] wire io_counter_event_signal_20 = 1'h0; // @[ReservationStation.scala:26:7] wire io_counter_event_signal_21 = 1'h0; // @[ReservationStation.scala:26:7] wire io_counter_event_signal_22 = 1'h0; // @[ReservationStation.scala:26:7] wire io_counter_event_signal_23 = 1'h0; // @[ReservationStation.scala:26:7] wire io_counter_event_signal_24 = 1'h0; // @[ReservationStation.scala:26:7] wire io_counter_event_signal_25 = 1'h0; // @[ReservationStation.scala:26:7] wire io_counter_event_signal_26 = 1'h0; // @[ReservationStation.scala:26:7] wire io_counter_event_signal_27 = 1'h0; // @[ReservationStation.scala:26:7] wire io_counter_event_signal_28 = 1'h0; // @[ReservationStation.scala:26:7] wire io_counter_event_signal_29 = 1'h0; // @[ReservationStation.scala:26:7] wire io_counter_event_signal_30 = 1'h0; // @[ReservationStation.scala:26:7] wire io_counter_event_signal_31 = 1'h0; // @[ReservationStation.scala:26:7] wire io_counter_event_signal_32 = 1'h0; // @[ReservationStation.scala:26:7] wire io_counter_event_signal_33 = 1'h0; // @[ReservationStation.scala:26:7] wire io_counter_event_signal_34 = 1'h0; // @[ReservationStation.scala:26:7] wire io_counter_event_signal_35 = 1'h0; // @[ReservationStation.scala:26:7] wire io_counter_event_signal_36 = 1'h0; // @[ReservationStation.scala:26:7] wire io_counter_event_signal_37 = 1'h0; // @[ReservationStation.scala:26:7] wire io_counter_event_signal_38 = 1'h0; // @[ReservationStation.scala:26:7] wire io_counter_event_signal_39 = 1'h0; // @[ReservationStation.scala:26:7] wire io_counter_event_signal_40 = 1'h0; // @[ReservationStation.scala:26:7] wire io_counter_event_signal_43 = 1'h0; // @[ReservationStation.scala:26:7] wire io_counter_event_signal_44 = 1'h0; // @[ReservationStation.scala:26:7] wire new_entry_issued = 1'h0; // @[ReservationStation.scala:171:23] wire _next_bank_addr_WIRE_is_acc_addr = 1'h0; // @[ReservationStation.scala:242:49] wire _next_bank_addr_WIRE_accumulate = 1'h0; // @[ReservationStation.scala:242:49] wire _next_bank_addr_WIRE_read_full_acc_row = 1'h0; // @[ReservationStation.scala:242:49] wire _next_bank_addr_WIRE_garbage_bit = 1'h0; // @[ReservationStation.scala:242:49] wire next_bank_addr_accumulate = 1'h0; // @[ReservationStation.scala:242:36] wire next_bank_addr_read_full_acc_row = 1'h0; // @[ReservationStation.scala:242:36] wire next_bank_addr_garbage_bit = 1'h0; // @[ReservationStation.scala:242:36] wire issue_entry_bits_opb_valid = 1'h0; // @[Mux.scala:30:73] wire issue_entry_bits_opb_bits_start_is_acc_addr = 1'h0; // @[Mux.scala:30:73] wire issue_entry_bits_opb_bits_start_accumulate = 1'h0; // @[Mux.scala:30:73] wire issue_entry_bits_opb_bits_start_read_full_acc_row = 1'h0; // @[Mux.scala:30:73] wire issue_entry_bits_opb_bits_start_garbage_bit = 1'h0; // @[Mux.scala:30:73] wire issue_entry_bits_opb_bits_end_is_acc_addr = 1'h0; // @[Mux.scala:30:73] wire issue_entry_bits_opb_bits_end_accumulate = 1'h0; // @[Mux.scala:30:73] wire issue_entry_bits_opb_bits_end_read_full_acc_row = 1'h0; // @[Mux.scala:30:73] wire issue_entry_bits_opb_bits_end_garbage_bit = 1'h0; // @[Mux.scala:30:73] wire issue_entry_bits_opb_bits_wraps_around = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_opb_valid = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_opb_bits_start_is_acc_addr = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_opb_bits_start_accumulate = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_opb_bits_start_read_full_acc_row = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_opb_bits_start_garbage_bit = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_opb_bits_end_is_acc_addr = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_opb_bits_end_accumulate = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_opb_bits_end_read_full_acc_row = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_opb_bits_end_garbage_bit = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_opb_bits_wraps_around = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_91_valid = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_91_bits_start_is_acc_addr = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_91_bits_start_accumulate = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_91_bits_start_read_full_acc_row = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_91_bits_start_garbage_bit = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_91_bits_end_is_acc_addr = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_91_bits_end_accumulate = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_91_bits_end_read_full_acc_row = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_91_bits_end_garbage_bit = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_91_bits_wraps_around = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_92_start_is_acc_addr = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_92_start_accumulate = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_92_start_read_full_acc_row = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_92_start_garbage_bit = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_92_end_is_acc_addr = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_92_end_accumulate = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_92_end_read_full_acc_row = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_92_end_garbage_bit = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_92_wraps_around = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1230 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1231 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1232 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1233 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1234 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1235 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1236 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1237 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1238 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1239 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1240 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1241 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1242 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1243 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1244 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_93 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_94_is_acc_addr = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_94_accumulate = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_94_read_full_acc_row = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_94_garbage_bit = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1260 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1261 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1262 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1263 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1264 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1265 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1266 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1267 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1268 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1269 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1270 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1271 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1272 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1273 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1274 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_96 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1313 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1314 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1315 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1316 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1317 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1318 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1319 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1320 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1321 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1322 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1323 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1324 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1325 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1326 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1327 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_101 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1328 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1329 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1330 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1331 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1332 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1333 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1334 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1335 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1336 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1337 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1338 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1339 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1340 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1341 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1342 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_102 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1343 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1344 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1345 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1346 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1347 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1348 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1349 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1350 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1351 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1352 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1353 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1354 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1355 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1356 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1357 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_103 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_104_is_acc_addr = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_104_accumulate = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_104_read_full_acc_row = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_104_garbage_bit = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1373 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1374 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1375 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1376 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1377 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1378 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1379 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1380 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1381 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1382 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1383 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1384 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1385 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1386 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1387 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_106 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1426 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1427 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1428 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1429 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1430 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1431 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1432 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1433 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1434 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1435 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1436 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1437 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1438 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1439 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1440 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_111 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1441 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1442 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1443 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1444 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1445 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1446 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1447 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1448 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1449 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1450 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1451 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1452 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1453 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1454 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1455 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_112 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1456 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1457 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1458 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1459 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1460 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1461 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1462 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1463 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1464 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1465 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1466 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1467 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1468 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1469 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1470 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_113 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1471 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1472 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1473 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1474 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1475 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1476 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1477 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1478 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1479 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1480 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1481 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1482 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1483 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1484 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_1485 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_114 = 1'h0; // @[Mux.scala:30:73] wire issue_entry_2_bits_opb_valid = 1'h0; // @[Mux.scala:30:73] wire issue_entry_2_bits_opb_bits_start_is_acc_addr = 1'h0; // @[Mux.scala:30:73] wire issue_entry_2_bits_opb_bits_start_accumulate = 1'h0; // @[Mux.scala:30:73] wire issue_entry_2_bits_opb_bits_start_read_full_acc_row = 1'h0; // @[Mux.scala:30:73] wire issue_entry_2_bits_opb_bits_start_garbage_bit = 1'h0; // @[Mux.scala:30:73] wire issue_entry_2_bits_opb_bits_end_is_acc_addr = 1'h0; // @[Mux.scala:30:73] wire issue_entry_2_bits_opb_bits_end_accumulate = 1'h0; // @[Mux.scala:30:73] wire issue_entry_2_bits_opb_bits_end_read_full_acc_row = 1'h0; // @[Mux.scala:30:73] wire issue_entry_2_bits_opb_bits_end_garbage_bit = 1'h0; // @[Mux.scala:30:73] wire issue_entry_2_bits_opb_bits_wraps_around = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_opb_valid = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_opb_bits_start_is_acc_addr = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_opb_bits_start_accumulate = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_opb_bits_start_read_full_acc_row = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_opb_bits_start_garbage_bit = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_opb_bits_end_is_acc_addr = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_opb_bits_end_accumulate = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_opb_bits_end_read_full_acc_row = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_opb_bits_end_garbage_bit = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_opb_bits_wraps_around = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_377_valid = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_377_bits_start_is_acc_addr = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_377_bits_start_accumulate = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_377_bits_start_read_full_acc_row = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_377_bits_start_garbage_bit = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_377_bits_end_is_acc_addr = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_377_bits_end_accumulate = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_377_bits_end_read_full_acc_row = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_377_bits_end_garbage_bit = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_377_bits_wraps_around = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_378_start_is_acc_addr = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_378_start_accumulate = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_378_start_read_full_acc_row = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_378_start_garbage_bit = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_378_end_is_acc_addr = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_378_end_accumulate = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_378_end_read_full_acc_row = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_378_end_garbage_bit = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_378_wraps_around = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6098 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6099 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6100 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6101 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6102 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6103 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6104 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_379 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_380_is_acc_addr = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_380_accumulate = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_380_read_full_acc_row = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_380_garbage_bit = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6112 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6113 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6114 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6115 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6116 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6117 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6118 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_382 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6137 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6138 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6139 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6140 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6141 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6142 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6143 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_387 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6144 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6145 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6146 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6147 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6148 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6149 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6150 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_388 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6151 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6152 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6153 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6154 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6155 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6156 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6157 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_389 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_390_is_acc_addr = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_390_accumulate = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_390_read_full_acc_row = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_390_garbage_bit = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6165 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6166 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6167 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6168 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6169 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6170 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6171 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_392 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6190 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6191 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6192 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6193 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6194 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6195 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6196 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_397 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6197 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6198 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6199 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6200 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6201 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6202 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6203 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_398 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6204 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6205 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6206 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6207 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6208 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6209 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6210 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_399 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6211 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6212 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6213 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6214 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6215 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6216 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_T_6217 = 1'h0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_400 = 1'h0; // @[Mux.scala:30:73] wire [2:0] _next_bank_addr_WIRE_norm_cmd = 3'h0; // @[ReservationStation.scala:242:49] wire [2:0] next_bank_addr_norm_cmd = 3'h0; // @[ReservationStation.scala:242:36] wire [2:0] issue_entry_bits_opb_bits_start_norm_cmd = 3'h0; // @[Mux.scala:30:73] wire [2:0] issue_entry_bits_opb_bits_end_norm_cmd = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_opb_bits_start_norm_cmd = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_opb_bits_end_norm_cmd = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_91_bits_start_norm_cmd = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_91_bits_end_norm_cmd = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_92_start_norm_cmd = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_92_end_norm_cmd = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_94_norm_cmd = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1290 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1291 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1292 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1293 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1294 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1295 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1296 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1297 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1298 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1299 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1300 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1301 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1302 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1303 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1304 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1305 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1306 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1307 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1308 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1309 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1310 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1311 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1312 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_98 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_99 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_100 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_104_norm_cmd = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1403 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1404 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1405 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1406 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1407 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1408 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1409 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1410 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1411 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1412 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1413 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1414 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1415 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1416 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1417 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1418 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1419 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1420 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1421 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1422 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1423 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1424 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1425 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_108 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_109 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_110 = 3'h0; // @[Mux.scala:30:73] wire [2:0] issue_entry_2_bits_opb_bits_start_norm_cmd = 3'h0; // @[Mux.scala:30:73] wire [2:0] issue_entry_2_bits_opb_bits_end_norm_cmd = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_286_opb_bits_start_norm_cmd = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_286_opb_bits_end_norm_cmd = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_377_bits_start_norm_cmd = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_377_bits_end_norm_cmd = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_378_start_norm_cmd = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_378_end_norm_cmd = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_380_norm_cmd = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_6126 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_6127 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_6128 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_6129 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_6130 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_6131 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_6132 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_6133 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_6134 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_6135 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_6136 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_384 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_385 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_386 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_390_norm_cmd = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_6179 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_6180 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_6181 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_6182 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_6183 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_6184 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_6185 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_6186 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_6187 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_6188 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_6189 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_394 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_395 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_396 = 3'h0; // @[Mux.scala:30:73] wire [10:0] _next_bank_addr_WIRE_garbage = 11'h0; // @[ReservationStation.scala:242:49] wire [10:0] next_bank_addr_garbage = 11'h0; // @[ReservationStation.scala:242:36] wire [10:0] issue_entry_bits_opb_bits_start_garbage = 11'h0; // @[Mux.scala:30:73] wire [10:0] issue_entry_bits_opb_bits_end_garbage = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_opb_bits_start_garbage = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_opb_bits_end_garbage = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_91_bits_start_garbage = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_91_bits_end_garbage = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_92_start_garbage = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_92_end_garbage = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_94_garbage = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_1275 = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_1276 = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_1277 = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_1278 = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_1279 = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_1280 = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_1281 = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_1282 = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_1283 = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_1284 = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_1285 = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_1286 = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_1287 = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_1288 = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_1289 = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_97 = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_104_garbage = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_1388 = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_1389 = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_1390 = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_1391 = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_1392 = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_1393 = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_1394 = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_1395 = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_1396 = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_1397 = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_1398 = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_1399 = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_1400 = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_1401 = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_1402 = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_107 = 11'h0; // @[Mux.scala:30:73] wire [10:0] issue_entry_2_bits_opb_bits_start_garbage = 11'h0; // @[Mux.scala:30:73] wire [10:0] issue_entry_2_bits_opb_bits_end_garbage = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_286_opb_bits_start_garbage = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_286_opb_bits_end_garbage = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_377_bits_start_garbage = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_377_bits_end_garbage = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_378_start_garbage = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_378_end_garbage = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_380_garbage = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_6119 = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_6120 = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_6121 = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_6122 = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_6123 = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_6124 = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_6125 = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_383 = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_390_garbage = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_6172 = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_6173 = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_6174 = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_6175 = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_6176 = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_6177 = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_6178 = 11'h0; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_393 = 11'h0; // @[Mux.scala:30:73] wire [13:0] _next_bank_addr_WIRE_data = 14'h0; // @[ReservationStation.scala:242:49] wire [13:0] issue_entry_bits_opb_bits_start_data = 14'h0; // @[Mux.scala:30:73] wire [13:0] issue_entry_bits_opb_bits_end_data = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_opb_bits_start_data = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_opb_bits_end_data = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_91_bits_start_data = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_91_bits_end_data = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_92_start_data = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_92_end_data = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_94_data = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_1245 = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_1246 = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_1247 = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_1248 = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_1249 = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_1250 = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_1251 = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_1252 = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_1253 = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_1254 = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_1255 = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_1256 = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_1257 = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_1258 = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_1259 = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_95 = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_104_data = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_1358 = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_1359 = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_1360 = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_1361 = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_1362 = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_1363 = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_1364 = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_1365 = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_1366 = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_1367 = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_1368 = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_1369 = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_1370 = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_1371 = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_1372 = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_105 = 14'h0; // @[Mux.scala:30:73] wire [13:0] issue_entry_2_bits_opb_bits_start_data = 14'h0; // @[Mux.scala:30:73] wire [13:0] issue_entry_2_bits_opb_bits_end_data = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_286_opb_bits_start_data = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_286_opb_bits_end_data = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_377_bits_start_data = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_377_bits_end_data = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_378_start_data = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_378_end_data = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_380_data = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_6105 = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_6106 = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_6107 = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_6108 = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_6109 = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_6110 = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_6111 = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_381 = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_390_data = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_6158 = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_6159 = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_6160 = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_6161 = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_6162 = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_6163 = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_6164 = 14'h0; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_391 = 14'h0; // @[Mux.scala:30:73] wire [31:0] io_counter_external_values_0 = 32'h0; // @[ReservationStation.scala:26:7] wire [31:0] io_counter_external_values_4 = 32'h0; // @[ReservationStation.scala:26:7] wire [31:0] io_counter_external_values_5 = 32'h0; // @[ReservationStation.scala:26:7] wire [31:0] io_counter_external_values_6 = 32'h0; // @[ReservationStation.scala:26:7] wire [31:0] io_counter_external_values_7 = 32'h0; // @[ReservationStation.scala:26:7] wire [1:0] _alloc_id_T_50 = 2'h3; // @[Mux.scala:126:16] wire [3:0] _alloc_id_T_31 = 4'hF; // @[Mux.scala:126:16] wire [2:0] _alloc_id_T_8 = 3'h7; // @[Mux.scala:126:16] wire [1:0] _new_entry_q_T = 2'h0; // @[Mux.scala:30:73] wire next_bank_addr_is_acc_addr = 1'h1; // @[ReservationStation.scala:242:36] wire _next_bank_addr_data_T_1 = 1'h1; // @[ReservationStation.scala:244:40] wire _op2_bits_wraps_around_T = 1'h1; // @[ReservationStation.scala:247:58] wire [13:0] next_bank_addr_data = 14'h1000; // @[ReservationStation.scala:242:36] wire [12:0] _next_bank_addr_data_T_2 = 13'h1000; // @[ReservationStation.scala:244:47] wire [1:0] _next_bank_addr_data_T = 2'h1; // @[ReservationStation.scala:244:40] wire [6:0] new_entry_cmd_cmd_inst_funct = io_alloc_bits_cmd_inst_funct_0; // @[ReservationStation.scala:26:7, :171:23] wire [4:0] new_entry_cmd_cmd_inst_rs2 = io_alloc_bits_cmd_inst_rs2_0; // @[ReservationStation.scala:26:7, :171:23] wire [4:0] new_entry_cmd_cmd_inst_rs1 = io_alloc_bits_cmd_inst_rs1_0; // @[ReservationStation.scala:26:7, :171:23] wire new_entry_cmd_cmd_inst_xd = io_alloc_bits_cmd_inst_xd_0; // @[ReservationStation.scala:26:7, :171:23] wire new_entry_cmd_cmd_inst_xs1 = io_alloc_bits_cmd_inst_xs1_0; // @[ReservationStation.scala:26:7, :171:23] wire new_entry_cmd_cmd_inst_xs2 = io_alloc_bits_cmd_inst_xs2_0; // @[ReservationStation.scala:26:7, :171:23] wire [4:0] new_entry_cmd_cmd_inst_rd = io_alloc_bits_cmd_inst_rd_0; // @[ReservationStation.scala:26:7, :171:23] wire [6:0] new_entry_cmd_cmd_inst_opcode = io_alloc_bits_cmd_inst_opcode_0; // @[ReservationStation.scala:26:7, :171:23] wire [63:0] new_entry_cmd_cmd_rs1 = io_alloc_bits_cmd_rs1_0; // @[ReservationStation.scala:26:7, :171:23] wire [63:0] new_entry_cmd_cmd_rs2 = io_alloc_bits_cmd_rs2_0; // @[ReservationStation.scala:26:7, :171:23] wire new_entry_cmd_cmd_status_debug = io_alloc_bits_cmd_status_debug_0; // @[ReservationStation.scala:26:7, :171:23] wire new_entry_cmd_cmd_status_cease = io_alloc_bits_cmd_status_cease_0; // @[ReservationStation.scala:26:7, :171:23] wire new_entry_cmd_cmd_status_wfi = io_alloc_bits_cmd_status_wfi_0; // @[ReservationStation.scala:26:7, :171:23] wire [31:0] new_entry_cmd_cmd_status_isa = io_alloc_bits_cmd_status_isa_0; // @[ReservationStation.scala:26:7, :171:23] wire [1:0] new_entry_cmd_cmd_status_dprv = io_alloc_bits_cmd_status_dprv_0; // @[ReservationStation.scala:26:7, :171:23] wire new_entry_cmd_cmd_status_dv = io_alloc_bits_cmd_status_dv_0; // @[ReservationStation.scala:26:7, :171:23] wire [1:0] new_entry_cmd_cmd_status_prv = io_alloc_bits_cmd_status_prv_0; // @[ReservationStation.scala:26:7, :171:23] wire new_entry_cmd_cmd_status_v = io_alloc_bits_cmd_status_v_0; // @[ReservationStation.scala:26:7, :171:23] wire new_entry_cmd_cmd_status_sd = io_alloc_bits_cmd_status_sd_0; // @[ReservationStation.scala:26:7, :171:23] wire [22:0] new_entry_cmd_cmd_status_zero2 = io_alloc_bits_cmd_status_zero2_0; // @[ReservationStation.scala:26:7, :171:23] wire new_entry_cmd_cmd_status_mpv = io_alloc_bits_cmd_status_mpv_0; // @[ReservationStation.scala:26:7, :171:23] wire new_entry_cmd_cmd_status_gva = io_alloc_bits_cmd_status_gva_0; // @[ReservationStation.scala:26:7, :171:23] wire new_entry_cmd_cmd_status_mbe = io_alloc_bits_cmd_status_mbe_0; // @[ReservationStation.scala:26:7, :171:23] wire new_entry_cmd_cmd_status_sbe = io_alloc_bits_cmd_status_sbe_0; // @[ReservationStation.scala:26:7, :171:23] wire [1:0] new_entry_cmd_cmd_status_sxl = io_alloc_bits_cmd_status_sxl_0; // @[ReservationStation.scala:26:7, :171:23] wire [1:0] new_entry_cmd_cmd_status_uxl = io_alloc_bits_cmd_status_uxl_0; // @[ReservationStation.scala:26:7, :171:23] wire new_entry_cmd_cmd_status_sd_rv32 = io_alloc_bits_cmd_status_sd_rv32_0; // @[ReservationStation.scala:26:7, :171:23] wire [7:0] new_entry_cmd_cmd_status_zero1 = io_alloc_bits_cmd_status_zero1_0; // @[ReservationStation.scala:26:7, :171:23] wire new_entry_cmd_cmd_status_tsr = io_alloc_bits_cmd_status_tsr_0; // @[ReservationStation.scala:26:7, :171:23] wire new_entry_cmd_cmd_status_tw = io_alloc_bits_cmd_status_tw_0; // @[ReservationStation.scala:26:7, :171:23] wire new_entry_cmd_cmd_status_tvm = io_alloc_bits_cmd_status_tvm_0; // @[ReservationStation.scala:26:7, :171:23] wire new_entry_cmd_cmd_status_mxr = io_alloc_bits_cmd_status_mxr_0; // @[ReservationStation.scala:26:7, :171:23] wire new_entry_cmd_cmd_status_sum = io_alloc_bits_cmd_status_sum_0; // @[ReservationStation.scala:26:7, :171:23] wire new_entry_cmd_cmd_status_mprv = io_alloc_bits_cmd_status_mprv_0; // @[ReservationStation.scala:26:7, :171:23] wire [1:0] new_entry_cmd_cmd_status_xs = io_alloc_bits_cmd_status_xs_0; // @[ReservationStation.scala:26:7, :171:23] wire [1:0] new_entry_cmd_cmd_status_fs = io_alloc_bits_cmd_status_fs_0; // @[ReservationStation.scala:26:7, :171:23] wire [1:0] new_entry_cmd_cmd_status_mpp = io_alloc_bits_cmd_status_mpp_0; // @[ReservationStation.scala:26:7, :171:23] wire [1:0] new_entry_cmd_cmd_status_vs = io_alloc_bits_cmd_status_vs_0; // @[ReservationStation.scala:26:7, :171:23] wire new_entry_cmd_cmd_status_spp = io_alloc_bits_cmd_status_spp_0; // @[ReservationStation.scala:26:7, :171:23] wire new_entry_cmd_cmd_status_mpie = io_alloc_bits_cmd_status_mpie_0; // @[ReservationStation.scala:26:7, :171:23] wire new_entry_cmd_cmd_status_ube = io_alloc_bits_cmd_status_ube_0; // @[ReservationStation.scala:26:7, :171:23] wire new_entry_cmd_cmd_status_spie = io_alloc_bits_cmd_status_spie_0; // @[ReservationStation.scala:26:7, :171:23] wire new_entry_cmd_cmd_status_upie = io_alloc_bits_cmd_status_upie_0; // @[ReservationStation.scala:26:7, :171:23] wire new_entry_cmd_cmd_status_mie = io_alloc_bits_cmd_status_mie_0; // @[ReservationStation.scala:26:7, :171:23] wire new_entry_cmd_cmd_status_hie = io_alloc_bits_cmd_status_hie_0; // @[ReservationStation.scala:26:7, :171:23] wire new_entry_cmd_cmd_status_sie = io_alloc_bits_cmd_status_sie_0; // @[ReservationStation.scala:26:7, :171:23] wire new_entry_cmd_cmd_status_uie = io_alloc_bits_cmd_status_uie_0; // @[ReservationStation.scala:26:7, :171:23] wire new_entry_cmd_rob_id_valid = io_alloc_bits_rob_id_valid_0; // @[ReservationStation.scala:26:7, :171:23] wire [5:0] new_entry_cmd_rob_id_bits = io_alloc_bits_rob_id_bits_0; // @[ReservationStation.scala:26:7, :171:23] wire new_entry_cmd_from_matmul_fsm = io_alloc_bits_from_matmul_fsm_0; // @[ReservationStation.scala:26:7, :171:23] wire new_entry_cmd_from_conv_fsm = io_alloc_bits_from_conv_fsm_0; // @[ReservationStation.scala:26:7, :171:23] wire _io_issue_ld_valid_T_6; // @[ReservationStation.scala:404:38] wire [6:0] issue_entry_bits_cmd_cmd_inst_funct; // @[Mux.scala:30:73] wire [4:0] issue_entry_bits_cmd_cmd_inst_rs2; // @[Mux.scala:30:73] wire [4:0] issue_entry_bits_cmd_cmd_inst_rs1; // @[Mux.scala:30:73] wire issue_entry_bits_cmd_cmd_inst_xd; // @[Mux.scala:30:73] wire issue_entry_bits_cmd_cmd_inst_xs1; // @[Mux.scala:30:73] wire issue_entry_bits_cmd_cmd_inst_xs2; // @[Mux.scala:30:73] wire [4:0] issue_entry_bits_cmd_cmd_inst_rd; // @[Mux.scala:30:73] wire [6:0] issue_entry_bits_cmd_cmd_inst_opcode; // @[Mux.scala:30:73] wire [63:0] issue_entry_bits_cmd_cmd_rs1; // @[Mux.scala:30:73] wire [63:0] issue_entry_bits_cmd_cmd_rs2; // @[Mux.scala:30:73] wire issue_entry_bits_cmd_cmd_status_debug; // @[Mux.scala:30:73] wire issue_entry_bits_cmd_cmd_status_cease; // @[Mux.scala:30:73] wire issue_entry_bits_cmd_cmd_status_wfi; // @[Mux.scala:30:73] wire [31:0] issue_entry_bits_cmd_cmd_status_isa; // @[Mux.scala:30:73] wire [1:0] issue_entry_bits_cmd_cmd_status_dprv; // @[Mux.scala:30:73] wire issue_entry_bits_cmd_cmd_status_dv; // @[Mux.scala:30:73] wire [1:0] issue_entry_bits_cmd_cmd_status_prv; // @[Mux.scala:30:73] wire issue_entry_bits_cmd_cmd_status_v; // @[Mux.scala:30:73] wire issue_entry_bits_cmd_cmd_status_sd; // @[Mux.scala:30:73] wire [22:0] issue_entry_bits_cmd_cmd_status_zero2; // @[Mux.scala:30:73] wire issue_entry_bits_cmd_cmd_status_mpv; // @[Mux.scala:30:73] wire issue_entry_bits_cmd_cmd_status_gva; // @[Mux.scala:30:73] wire issue_entry_bits_cmd_cmd_status_mbe; // @[Mux.scala:30:73] wire issue_entry_bits_cmd_cmd_status_sbe; // @[Mux.scala:30:73] wire [1:0] issue_entry_bits_cmd_cmd_status_sxl; // @[Mux.scala:30:73] wire [1:0] issue_entry_bits_cmd_cmd_status_uxl; // @[Mux.scala:30:73] wire issue_entry_bits_cmd_cmd_status_sd_rv32; // @[Mux.scala:30:73] wire [7:0] issue_entry_bits_cmd_cmd_status_zero1; // @[Mux.scala:30:73] wire issue_entry_bits_cmd_cmd_status_tsr; // @[Mux.scala:30:73] wire issue_entry_bits_cmd_cmd_status_tw; // @[Mux.scala:30:73] wire issue_entry_bits_cmd_cmd_status_tvm; // @[Mux.scala:30:73] wire issue_entry_bits_cmd_cmd_status_mxr; // @[Mux.scala:30:73] wire issue_entry_bits_cmd_cmd_status_sum; // @[Mux.scala:30:73] wire issue_entry_bits_cmd_cmd_status_mprv; // @[Mux.scala:30:73] wire [1:0] issue_entry_bits_cmd_cmd_status_xs; // @[Mux.scala:30:73] wire [1:0] issue_entry_bits_cmd_cmd_status_fs; // @[Mux.scala:30:73] wire [1:0] issue_entry_bits_cmd_cmd_status_mpp; // @[Mux.scala:30:73] wire [1:0] issue_entry_bits_cmd_cmd_status_vs; // @[Mux.scala:30:73] wire issue_entry_bits_cmd_cmd_status_spp; // @[Mux.scala:30:73] wire issue_entry_bits_cmd_cmd_status_mpie; // @[Mux.scala:30:73] wire issue_entry_bits_cmd_cmd_status_ube; // @[Mux.scala:30:73] wire issue_entry_bits_cmd_cmd_status_spie; // @[Mux.scala:30:73] wire issue_entry_bits_cmd_cmd_status_upie; // @[Mux.scala:30:73] wire issue_entry_bits_cmd_cmd_status_mie; // @[Mux.scala:30:73] wire issue_entry_bits_cmd_cmd_status_hie; // @[Mux.scala:30:73] wire issue_entry_bits_cmd_cmd_status_sie; // @[Mux.scala:30:73] wire issue_entry_bits_cmd_cmd_status_uie; // @[Mux.scala:30:73] wire issue_entry_bits_cmd_rob_id_valid; // @[Mux.scala:30:73] wire [5:0] issue_entry_bits_cmd_rob_id_bits; // @[Mux.scala:30:73] wire issue_entry_bits_cmd_from_matmul_fsm; // @[Mux.scala:30:73] wire issue_entry_bits_cmd_from_conv_fsm; // @[Mux.scala:30:73] wire [5:0] global_issue_id; // @[ReservationStation.scala:398:30] wire _io_issue_st_valid_T_2; // @[ReservationStation.scala:404:38] wire [6:0] issue_entry_2_bits_cmd_cmd_inst_funct; // @[Mux.scala:30:73] wire [4:0] issue_entry_2_bits_cmd_cmd_inst_rs2; // @[Mux.scala:30:73] wire [4:0] issue_entry_2_bits_cmd_cmd_inst_rs1; // @[Mux.scala:30:73] wire issue_entry_2_bits_cmd_cmd_inst_xd; // @[Mux.scala:30:73] wire issue_entry_2_bits_cmd_cmd_inst_xs1; // @[Mux.scala:30:73] wire issue_entry_2_bits_cmd_cmd_inst_xs2; // @[Mux.scala:30:73] wire [4:0] issue_entry_2_bits_cmd_cmd_inst_rd; // @[Mux.scala:30:73] wire [6:0] issue_entry_2_bits_cmd_cmd_inst_opcode; // @[Mux.scala:30:73] wire [63:0] issue_entry_2_bits_cmd_cmd_rs1; // @[Mux.scala:30:73] wire [63:0] issue_entry_2_bits_cmd_cmd_rs2; // @[Mux.scala:30:73] wire issue_entry_2_bits_cmd_cmd_status_debug; // @[Mux.scala:30:73] wire issue_entry_2_bits_cmd_cmd_status_cease; // @[Mux.scala:30:73] wire issue_entry_2_bits_cmd_cmd_status_wfi; // @[Mux.scala:30:73] wire [31:0] issue_entry_2_bits_cmd_cmd_status_isa; // @[Mux.scala:30:73] wire [1:0] issue_entry_2_bits_cmd_cmd_status_dprv; // @[Mux.scala:30:73] wire issue_entry_2_bits_cmd_cmd_status_dv; // @[Mux.scala:30:73] wire [1:0] issue_entry_2_bits_cmd_cmd_status_prv; // @[Mux.scala:30:73] wire issue_entry_2_bits_cmd_cmd_status_v; // @[Mux.scala:30:73] wire issue_entry_2_bits_cmd_cmd_status_sd; // @[Mux.scala:30:73] wire [22:0] issue_entry_2_bits_cmd_cmd_status_zero2; // @[Mux.scala:30:73] wire issue_entry_2_bits_cmd_cmd_status_mpv; // @[Mux.scala:30:73] wire issue_entry_2_bits_cmd_cmd_status_gva; // @[Mux.scala:30:73] wire issue_entry_2_bits_cmd_cmd_status_mbe; // @[Mux.scala:30:73] wire issue_entry_2_bits_cmd_cmd_status_sbe; // @[Mux.scala:30:73] wire [1:0] issue_entry_2_bits_cmd_cmd_status_sxl; // @[Mux.scala:30:73] wire [1:0] issue_entry_2_bits_cmd_cmd_status_uxl; // @[Mux.scala:30:73] wire issue_entry_2_bits_cmd_cmd_status_sd_rv32; // @[Mux.scala:30:73] wire [7:0] issue_entry_2_bits_cmd_cmd_status_zero1; // @[Mux.scala:30:73] wire issue_entry_2_bits_cmd_cmd_status_tsr; // @[Mux.scala:30:73] wire issue_entry_2_bits_cmd_cmd_status_tw; // @[Mux.scala:30:73] wire issue_entry_2_bits_cmd_cmd_status_tvm; // @[Mux.scala:30:73] wire issue_entry_2_bits_cmd_cmd_status_mxr; // @[Mux.scala:30:73] wire issue_entry_2_bits_cmd_cmd_status_sum; // @[Mux.scala:30:73] wire issue_entry_2_bits_cmd_cmd_status_mprv; // @[Mux.scala:30:73] wire [1:0] issue_entry_2_bits_cmd_cmd_status_xs; // @[Mux.scala:30:73] wire [1:0] issue_entry_2_bits_cmd_cmd_status_fs; // @[Mux.scala:30:73] wire [1:0] issue_entry_2_bits_cmd_cmd_status_mpp; // @[Mux.scala:30:73] wire [1:0] issue_entry_2_bits_cmd_cmd_status_vs; // @[Mux.scala:30:73] wire issue_entry_2_bits_cmd_cmd_status_spp; // @[Mux.scala:30:73] wire issue_entry_2_bits_cmd_cmd_status_mpie; // @[Mux.scala:30:73] wire issue_entry_2_bits_cmd_cmd_status_ube; // @[Mux.scala:30:73] wire issue_entry_2_bits_cmd_cmd_status_spie; // @[Mux.scala:30:73] wire issue_entry_2_bits_cmd_cmd_status_upie; // @[Mux.scala:30:73] wire issue_entry_2_bits_cmd_cmd_status_mie; // @[Mux.scala:30:73] wire issue_entry_2_bits_cmd_cmd_status_hie; // @[Mux.scala:30:73] wire issue_entry_2_bits_cmd_cmd_status_sie; // @[Mux.scala:30:73] wire issue_entry_2_bits_cmd_cmd_status_uie; // @[Mux.scala:30:73] wire issue_entry_2_bits_cmd_rob_id_valid; // @[Mux.scala:30:73] wire [5:0] issue_entry_2_bits_cmd_rob_id_bits; // @[Mux.scala:30:73] wire issue_entry_2_bits_cmd_from_matmul_fsm; // @[Mux.scala:30:73] wire issue_entry_2_bits_cmd_from_conv_fsm; // @[Mux.scala:30:73] wire [5:0] global_issue_id_2; // @[ReservationStation.scala:398:30] wire _io_issue_ex_valid_T_14; // @[ReservationStation.scala:404:38] wire [6:0] issue_entry_1_bits_cmd_cmd_inst_funct; // @[Mux.scala:30:73] wire [4:0] issue_entry_1_bits_cmd_cmd_inst_rs2; // @[Mux.scala:30:73] wire [4:0] issue_entry_1_bits_cmd_cmd_inst_rs1; // @[Mux.scala:30:73] wire issue_entry_1_bits_cmd_cmd_inst_xd; // @[Mux.scala:30:73] wire issue_entry_1_bits_cmd_cmd_inst_xs1; // @[Mux.scala:30:73] wire issue_entry_1_bits_cmd_cmd_inst_xs2; // @[Mux.scala:30:73] wire [4:0] issue_entry_1_bits_cmd_cmd_inst_rd; // @[Mux.scala:30:73] wire [6:0] issue_entry_1_bits_cmd_cmd_inst_opcode; // @[Mux.scala:30:73] wire [63:0] issue_entry_1_bits_cmd_cmd_rs1; // @[Mux.scala:30:73] wire [63:0] issue_entry_1_bits_cmd_cmd_rs2; // @[Mux.scala:30:73] wire issue_entry_1_bits_cmd_cmd_status_debug; // @[Mux.scala:30:73] wire issue_entry_1_bits_cmd_cmd_status_cease; // @[Mux.scala:30:73] wire issue_entry_1_bits_cmd_cmd_status_wfi; // @[Mux.scala:30:73] wire [31:0] issue_entry_1_bits_cmd_cmd_status_isa; // @[Mux.scala:30:73] wire [1:0] issue_entry_1_bits_cmd_cmd_status_dprv; // @[Mux.scala:30:73] wire issue_entry_1_bits_cmd_cmd_status_dv; // @[Mux.scala:30:73] wire [1:0] issue_entry_1_bits_cmd_cmd_status_prv; // @[Mux.scala:30:73] wire issue_entry_1_bits_cmd_cmd_status_v; // @[Mux.scala:30:73] wire issue_entry_1_bits_cmd_cmd_status_sd; // @[Mux.scala:30:73] wire [22:0] issue_entry_1_bits_cmd_cmd_status_zero2; // @[Mux.scala:30:73] wire issue_entry_1_bits_cmd_cmd_status_mpv; // @[Mux.scala:30:73] wire issue_entry_1_bits_cmd_cmd_status_gva; // @[Mux.scala:30:73] wire issue_entry_1_bits_cmd_cmd_status_mbe; // @[Mux.scala:30:73] wire issue_entry_1_bits_cmd_cmd_status_sbe; // @[Mux.scala:30:73] wire [1:0] issue_entry_1_bits_cmd_cmd_status_sxl; // @[Mux.scala:30:73] wire [1:0] issue_entry_1_bits_cmd_cmd_status_uxl; // @[Mux.scala:30:73] wire issue_entry_1_bits_cmd_cmd_status_sd_rv32; // @[Mux.scala:30:73] wire [7:0] issue_entry_1_bits_cmd_cmd_status_zero1; // @[Mux.scala:30:73] wire issue_entry_1_bits_cmd_cmd_status_tsr; // @[Mux.scala:30:73] wire issue_entry_1_bits_cmd_cmd_status_tw; // @[Mux.scala:30:73] wire issue_entry_1_bits_cmd_cmd_status_tvm; // @[Mux.scala:30:73] wire issue_entry_1_bits_cmd_cmd_status_mxr; // @[Mux.scala:30:73] wire issue_entry_1_bits_cmd_cmd_status_sum; // @[Mux.scala:30:73] wire issue_entry_1_bits_cmd_cmd_status_mprv; // @[Mux.scala:30:73] wire [1:0] issue_entry_1_bits_cmd_cmd_status_xs; // @[Mux.scala:30:73] wire [1:0] issue_entry_1_bits_cmd_cmd_status_fs; // @[Mux.scala:30:73] wire [1:0] issue_entry_1_bits_cmd_cmd_status_mpp; // @[Mux.scala:30:73] wire [1:0] issue_entry_1_bits_cmd_cmd_status_vs; // @[Mux.scala:30:73] wire issue_entry_1_bits_cmd_cmd_status_spp; // @[Mux.scala:30:73] wire issue_entry_1_bits_cmd_cmd_status_mpie; // @[Mux.scala:30:73] wire issue_entry_1_bits_cmd_cmd_status_ube; // @[Mux.scala:30:73] wire issue_entry_1_bits_cmd_cmd_status_spie; // @[Mux.scala:30:73] wire issue_entry_1_bits_cmd_cmd_status_upie; // @[Mux.scala:30:73] wire issue_entry_1_bits_cmd_cmd_status_mie; // @[Mux.scala:30:73] wire issue_entry_1_bits_cmd_cmd_status_hie; // @[Mux.scala:30:73] wire issue_entry_1_bits_cmd_cmd_status_sie; // @[Mux.scala:30:73] wire issue_entry_1_bits_cmd_cmd_status_uie; // @[Mux.scala:30:73] wire issue_entry_1_bits_cmd_rob_id_valid; // @[Mux.scala:30:73] wire [5:0] issue_entry_1_bits_cmd_rob_id_bits; // @[Mux.scala:30:73] wire issue_entry_1_bits_cmd_from_matmul_fsm; // @[Mux.scala:30:73] wire issue_entry_1_bits_cmd_from_conv_fsm; // @[Mux.scala:30:73] wire [5:0] global_issue_id_1; // @[ReservationStation.scala:398:30] wire [1:0] _io_conv_ld_completed_T; // @[ReservationStation.scala:154:51] wire [1:0] _io_conv_ex_completed_T; // @[ReservationStation.scala:156:51] wire [1:0] _io_conv_st_completed_T; // @[ReservationStation.scala:155:51] wire [1:0] _io_matmul_ld_completed_T; // @[ReservationStation.scala:158:55] wire [1:0] _io_matmul_ex_completed_T; // @[ReservationStation.scala:160:55] wire [1:0] _io_matmul_st_completed_T; // @[ReservationStation.scala:159:55] wire _io_busy_T_4; // @[ReservationStation.scala:135:21] wire io_counter_event_signal_42_0 = io_busy_0; // @[ReservationStation.scala:26:7] wire io_alloc_ready_0; // @[ReservationStation.scala:26:7] wire [6:0] io_issue_ld_cmd_cmd_inst_funct_0; // @[ReservationStation.scala:26:7] wire [4:0] io_issue_ld_cmd_cmd_inst_rs2_0; // @[ReservationStation.scala:26:7] wire [4:0] io_issue_ld_cmd_cmd_inst_rs1_0; // @[ReservationStation.scala:26:7] wire io_issue_ld_cmd_cmd_inst_xd_0; // @[ReservationStation.scala:26:7] wire io_issue_ld_cmd_cmd_inst_xs1_0; // @[ReservationStation.scala:26:7] wire io_issue_ld_cmd_cmd_inst_xs2_0; // @[ReservationStation.scala:26:7] wire [4:0] io_issue_ld_cmd_cmd_inst_rd_0; // @[ReservationStation.scala:26:7] wire [6:0] io_issue_ld_cmd_cmd_inst_opcode_0; // @[ReservationStation.scala:26:7] wire io_issue_ld_cmd_cmd_status_debug_0; // @[ReservationStation.scala:26:7] wire io_issue_ld_cmd_cmd_status_cease_0; // @[ReservationStation.scala:26:7] wire io_issue_ld_cmd_cmd_status_wfi_0; // @[ReservationStation.scala:26:7] wire [31:0] io_issue_ld_cmd_cmd_status_isa_0; // @[ReservationStation.scala:26:7] wire [1:0] io_issue_ld_cmd_cmd_status_dprv_0; // @[ReservationStation.scala:26:7] wire io_issue_ld_cmd_cmd_status_dv_0; // @[ReservationStation.scala:26:7] wire [1:0] io_issue_ld_cmd_cmd_status_prv_0; // @[ReservationStation.scala:26:7] wire io_issue_ld_cmd_cmd_status_v_0; // @[ReservationStation.scala:26:7] wire io_issue_ld_cmd_cmd_status_sd_0; // @[ReservationStation.scala:26:7] wire [22:0] io_issue_ld_cmd_cmd_status_zero2_0; // @[ReservationStation.scala:26:7] wire io_issue_ld_cmd_cmd_status_mpv_0; // @[ReservationStation.scala:26:7] wire io_issue_ld_cmd_cmd_status_gva_0; // @[ReservationStation.scala:26:7] wire io_issue_ld_cmd_cmd_status_mbe_0; // @[ReservationStation.scala:26:7] wire io_issue_ld_cmd_cmd_status_sbe_0; // @[ReservationStation.scala:26:7] wire [1:0] io_issue_ld_cmd_cmd_status_sxl_0; // @[ReservationStation.scala:26:7] wire [1:0] io_issue_ld_cmd_cmd_status_uxl_0; // @[ReservationStation.scala:26:7] wire io_issue_ld_cmd_cmd_status_sd_rv32_0; // @[ReservationStation.scala:26:7] wire [7:0] io_issue_ld_cmd_cmd_status_zero1_0; // @[ReservationStation.scala:26:7] wire io_issue_ld_cmd_cmd_status_tsr_0; // @[ReservationStation.scala:26:7] wire io_issue_ld_cmd_cmd_status_tw_0; // @[ReservationStation.scala:26:7] wire io_issue_ld_cmd_cmd_status_tvm_0; // @[ReservationStation.scala:26:7] wire io_issue_ld_cmd_cmd_status_mxr_0; // @[ReservationStation.scala:26:7] wire io_issue_ld_cmd_cmd_status_sum_0; // @[ReservationStation.scala:26:7] wire io_issue_ld_cmd_cmd_status_mprv_0; // @[ReservationStation.scala:26:7] wire [1:0] io_issue_ld_cmd_cmd_status_xs_0; // @[ReservationStation.scala:26:7] wire [1:0] io_issue_ld_cmd_cmd_status_fs_0; // @[ReservationStation.scala:26:7] wire [1:0] io_issue_ld_cmd_cmd_status_mpp_0; // @[ReservationStation.scala:26:7] wire [1:0] io_issue_ld_cmd_cmd_status_vs_0; // @[ReservationStation.scala:26:7] wire io_issue_ld_cmd_cmd_status_spp_0; // @[ReservationStation.scala:26:7] wire io_issue_ld_cmd_cmd_status_mpie_0; // @[ReservationStation.scala:26:7] wire io_issue_ld_cmd_cmd_status_ube_0; // @[ReservationStation.scala:26:7] wire io_issue_ld_cmd_cmd_status_spie_0; // @[ReservationStation.scala:26:7] wire io_issue_ld_cmd_cmd_status_upie_0; // @[ReservationStation.scala:26:7] wire io_issue_ld_cmd_cmd_status_mie_0; // @[ReservationStation.scala:26:7] wire io_issue_ld_cmd_cmd_status_hie_0; // @[ReservationStation.scala:26:7] wire io_issue_ld_cmd_cmd_status_sie_0; // @[ReservationStation.scala:26:7] wire io_issue_ld_cmd_cmd_status_uie_0; // @[ReservationStation.scala:26:7] wire [63:0] io_issue_ld_cmd_cmd_rs1_0; // @[ReservationStation.scala:26:7] wire [63:0] io_issue_ld_cmd_cmd_rs2_0; // @[ReservationStation.scala:26:7] wire io_issue_ld_cmd_rob_id_valid; // @[ReservationStation.scala:26:7] wire [5:0] io_issue_ld_cmd_rob_id_bits; // @[ReservationStation.scala:26:7] wire io_issue_ld_cmd_from_matmul_fsm_0; // @[ReservationStation.scala:26:7] wire io_issue_ld_cmd_from_conv_fsm_0; // @[ReservationStation.scala:26:7] wire io_issue_ld_valid_0; // @[ReservationStation.scala:26:7] wire [5:0] io_issue_ld_rob_id_0; // @[ReservationStation.scala:26:7] wire [6:0] io_issue_st_cmd_cmd_inst_funct_0; // @[ReservationStation.scala:26:7] wire [4:0] io_issue_st_cmd_cmd_inst_rs2_0; // @[ReservationStation.scala:26:7] wire [4:0] io_issue_st_cmd_cmd_inst_rs1_0; // @[ReservationStation.scala:26:7] wire io_issue_st_cmd_cmd_inst_xd_0; // @[ReservationStation.scala:26:7] wire io_issue_st_cmd_cmd_inst_xs1_0; // @[ReservationStation.scala:26:7] wire io_issue_st_cmd_cmd_inst_xs2_0; // @[ReservationStation.scala:26:7] wire [4:0] io_issue_st_cmd_cmd_inst_rd_0; // @[ReservationStation.scala:26:7] wire [6:0] io_issue_st_cmd_cmd_inst_opcode_0; // @[ReservationStation.scala:26:7] wire io_issue_st_cmd_cmd_status_debug_0; // @[ReservationStation.scala:26:7] wire io_issue_st_cmd_cmd_status_cease_0; // @[ReservationStation.scala:26:7] wire io_issue_st_cmd_cmd_status_wfi_0; // @[ReservationStation.scala:26:7] wire [31:0] io_issue_st_cmd_cmd_status_isa_0; // @[ReservationStation.scala:26:7] wire [1:0] io_issue_st_cmd_cmd_status_dprv_0; // @[ReservationStation.scala:26:7] wire io_issue_st_cmd_cmd_status_dv_0; // @[ReservationStation.scala:26:7] wire [1:0] io_issue_st_cmd_cmd_status_prv_0; // @[ReservationStation.scala:26:7] wire io_issue_st_cmd_cmd_status_v_0; // @[ReservationStation.scala:26:7] wire io_issue_st_cmd_cmd_status_sd_0; // @[ReservationStation.scala:26:7] wire [22:0] io_issue_st_cmd_cmd_status_zero2_0; // @[ReservationStation.scala:26:7] wire io_issue_st_cmd_cmd_status_mpv_0; // @[ReservationStation.scala:26:7] wire io_issue_st_cmd_cmd_status_gva_0; // @[ReservationStation.scala:26:7] wire io_issue_st_cmd_cmd_status_mbe_0; // @[ReservationStation.scala:26:7] wire io_issue_st_cmd_cmd_status_sbe_0; // @[ReservationStation.scala:26:7] wire [1:0] io_issue_st_cmd_cmd_status_sxl_0; // @[ReservationStation.scala:26:7] wire [1:0] io_issue_st_cmd_cmd_status_uxl_0; // @[ReservationStation.scala:26:7] wire io_issue_st_cmd_cmd_status_sd_rv32_0; // @[ReservationStation.scala:26:7] wire [7:0] io_issue_st_cmd_cmd_status_zero1_0; // @[ReservationStation.scala:26:7] wire io_issue_st_cmd_cmd_status_tsr_0; // @[ReservationStation.scala:26:7] wire io_issue_st_cmd_cmd_status_tw_0; // @[ReservationStation.scala:26:7] wire io_issue_st_cmd_cmd_status_tvm_0; // @[ReservationStation.scala:26:7] wire io_issue_st_cmd_cmd_status_mxr_0; // @[ReservationStation.scala:26:7] wire io_issue_st_cmd_cmd_status_sum_0; // @[ReservationStation.scala:26:7] wire io_issue_st_cmd_cmd_status_mprv_0; // @[ReservationStation.scala:26:7] wire [1:0] io_issue_st_cmd_cmd_status_xs_0; // @[ReservationStation.scala:26:7] wire [1:0] io_issue_st_cmd_cmd_status_fs_0; // @[ReservationStation.scala:26:7] wire [1:0] io_issue_st_cmd_cmd_status_mpp_0; // @[ReservationStation.scala:26:7] wire [1:0] io_issue_st_cmd_cmd_status_vs_0; // @[ReservationStation.scala:26:7] wire io_issue_st_cmd_cmd_status_spp_0; // @[ReservationStation.scala:26:7] wire io_issue_st_cmd_cmd_status_mpie_0; // @[ReservationStation.scala:26:7] wire io_issue_st_cmd_cmd_status_ube_0; // @[ReservationStation.scala:26:7] wire io_issue_st_cmd_cmd_status_spie_0; // @[ReservationStation.scala:26:7] wire io_issue_st_cmd_cmd_status_upie_0; // @[ReservationStation.scala:26:7] wire io_issue_st_cmd_cmd_status_mie_0; // @[ReservationStation.scala:26:7] wire io_issue_st_cmd_cmd_status_hie_0; // @[ReservationStation.scala:26:7] wire io_issue_st_cmd_cmd_status_sie_0; // @[ReservationStation.scala:26:7] wire io_issue_st_cmd_cmd_status_uie_0; // @[ReservationStation.scala:26:7] wire [63:0] io_issue_st_cmd_cmd_rs1_0; // @[ReservationStation.scala:26:7] wire [63:0] io_issue_st_cmd_cmd_rs2_0; // @[ReservationStation.scala:26:7] wire io_issue_st_cmd_rob_id_valid; // @[ReservationStation.scala:26:7] wire [5:0] io_issue_st_cmd_rob_id_bits; // @[ReservationStation.scala:26:7] wire io_issue_st_cmd_from_matmul_fsm_0; // @[ReservationStation.scala:26:7] wire io_issue_st_cmd_from_conv_fsm_0; // @[ReservationStation.scala:26:7] wire io_issue_st_valid_0; // @[ReservationStation.scala:26:7] wire [5:0] io_issue_st_rob_id_0; // @[ReservationStation.scala:26:7] wire [6:0] io_issue_ex_cmd_cmd_inst_funct_0; // @[ReservationStation.scala:26:7] wire [4:0] io_issue_ex_cmd_cmd_inst_rs2_0; // @[ReservationStation.scala:26:7] wire [4:0] io_issue_ex_cmd_cmd_inst_rs1_0; // @[ReservationStation.scala:26:7] wire io_issue_ex_cmd_cmd_inst_xd_0; // @[ReservationStation.scala:26:7] wire io_issue_ex_cmd_cmd_inst_xs1_0; // @[ReservationStation.scala:26:7] wire io_issue_ex_cmd_cmd_inst_xs2_0; // @[ReservationStation.scala:26:7] wire [4:0] io_issue_ex_cmd_cmd_inst_rd_0; // @[ReservationStation.scala:26:7] wire [6:0] io_issue_ex_cmd_cmd_inst_opcode_0; // @[ReservationStation.scala:26:7] wire io_issue_ex_cmd_cmd_status_debug_0; // @[ReservationStation.scala:26:7] wire io_issue_ex_cmd_cmd_status_cease_0; // @[ReservationStation.scala:26:7] wire io_issue_ex_cmd_cmd_status_wfi_0; // @[ReservationStation.scala:26:7] wire [31:0] io_issue_ex_cmd_cmd_status_isa_0; // @[ReservationStation.scala:26:7] wire [1:0] io_issue_ex_cmd_cmd_status_dprv_0; // @[ReservationStation.scala:26:7] wire io_issue_ex_cmd_cmd_status_dv_0; // @[ReservationStation.scala:26:7] wire [1:0] io_issue_ex_cmd_cmd_status_prv_0; // @[ReservationStation.scala:26:7] wire io_issue_ex_cmd_cmd_status_v_0; // @[ReservationStation.scala:26:7] wire io_issue_ex_cmd_cmd_status_sd_0; // @[ReservationStation.scala:26:7] wire [22:0] io_issue_ex_cmd_cmd_status_zero2_0; // @[ReservationStation.scala:26:7] wire io_issue_ex_cmd_cmd_status_mpv_0; // @[ReservationStation.scala:26:7] wire io_issue_ex_cmd_cmd_status_gva_0; // @[ReservationStation.scala:26:7] wire io_issue_ex_cmd_cmd_status_mbe_0; // @[ReservationStation.scala:26:7] wire io_issue_ex_cmd_cmd_status_sbe_0; // @[ReservationStation.scala:26:7] wire [1:0] io_issue_ex_cmd_cmd_status_sxl_0; // @[ReservationStation.scala:26:7] wire [1:0] io_issue_ex_cmd_cmd_status_uxl_0; // @[ReservationStation.scala:26:7] wire io_issue_ex_cmd_cmd_status_sd_rv32_0; // @[ReservationStation.scala:26:7] wire [7:0] io_issue_ex_cmd_cmd_status_zero1_0; // @[ReservationStation.scala:26:7] wire io_issue_ex_cmd_cmd_status_tsr_0; // @[ReservationStation.scala:26:7] wire io_issue_ex_cmd_cmd_status_tw_0; // @[ReservationStation.scala:26:7] wire io_issue_ex_cmd_cmd_status_tvm_0; // @[ReservationStation.scala:26:7] wire io_issue_ex_cmd_cmd_status_mxr_0; // @[ReservationStation.scala:26:7] wire io_issue_ex_cmd_cmd_status_sum_0; // @[ReservationStation.scala:26:7] wire io_issue_ex_cmd_cmd_status_mprv_0; // @[ReservationStation.scala:26:7] wire [1:0] io_issue_ex_cmd_cmd_status_xs_0; // @[ReservationStation.scala:26:7] wire [1:0] io_issue_ex_cmd_cmd_status_fs_0; // @[ReservationStation.scala:26:7] wire [1:0] io_issue_ex_cmd_cmd_status_mpp_0; // @[ReservationStation.scala:26:7] wire [1:0] io_issue_ex_cmd_cmd_status_vs_0; // @[ReservationStation.scala:26:7] wire io_issue_ex_cmd_cmd_status_spp_0; // @[ReservationStation.scala:26:7] wire io_issue_ex_cmd_cmd_status_mpie_0; // @[ReservationStation.scala:26:7] wire io_issue_ex_cmd_cmd_status_ube_0; // @[ReservationStation.scala:26:7] wire io_issue_ex_cmd_cmd_status_spie_0; // @[ReservationStation.scala:26:7] wire io_issue_ex_cmd_cmd_status_upie_0; // @[ReservationStation.scala:26:7] wire io_issue_ex_cmd_cmd_status_mie_0; // @[ReservationStation.scala:26:7] wire io_issue_ex_cmd_cmd_status_hie_0; // @[ReservationStation.scala:26:7] wire io_issue_ex_cmd_cmd_status_sie_0; // @[ReservationStation.scala:26:7] wire io_issue_ex_cmd_cmd_status_uie_0; // @[ReservationStation.scala:26:7] wire [63:0] io_issue_ex_cmd_cmd_rs1_0; // @[ReservationStation.scala:26:7] wire [63:0] io_issue_ex_cmd_cmd_rs2_0; // @[ReservationStation.scala:26:7] wire io_issue_ex_cmd_rob_id_valid; // @[ReservationStation.scala:26:7] wire [5:0] io_issue_ex_cmd_rob_id_bits; // @[ReservationStation.scala:26:7] wire io_issue_ex_cmd_from_matmul_fsm_0; // @[ReservationStation.scala:26:7] wire io_issue_ex_cmd_from_conv_fsm_0; // @[ReservationStation.scala:26:7] wire io_issue_ex_valid_0; // @[ReservationStation.scala:26:7] wire [5:0] io_issue_ex_rob_id_0; // @[ReservationStation.scala:26:7] wire io_counter_event_signal_41_0; // @[ReservationStation.scala:26:7] wire [31:0] io_counter_external_values_1_0; // @[ReservationStation.scala:26:7] wire [31:0] io_counter_external_values_2_0; // @[ReservationStation.scala:26:7] wire [31:0] io_counter_external_values_3_0; // @[ReservationStation.scala:26:7] wire [1:0] io_conv_ld_completed_0; // @[ReservationStation.scala:26:7] wire [1:0] io_conv_ex_completed_0; // @[ReservationStation.scala:26:7] wire [1:0] io_conv_st_completed_0; // @[ReservationStation.scala:26:7] wire [1:0] io_matmul_ld_completed_0; // @[ReservationStation.scala:26:7] wire [1:0] io_matmul_ex_completed_0; // @[ReservationStation.scala:26:7] wire [1:0] io_matmul_st_completed_0; // @[ReservationStation.scala:26:7] reg [31:0] instructions_allocated; // @[ReservationStation.scala:75:39] wire [31:0] new_entry_allocated_at = instructions_allocated; // @[ReservationStation.scala:75:39, :171:23] wire alloc_fire = io_alloc_ready_0 & io_alloc_valid_0; // @[Decoupled.scala:51:35] wire [32:0] _instructions_allocated_T = {1'h0, instructions_allocated} + 33'h1; // @[ReservationStation.scala:75:39, :77:54] wire [31:0] _instructions_allocated_T_1 = _instructions_allocated_T[31:0]; // @[ReservationStation.scala:77:54] reg entries_ld_0_valid; // @[ReservationStation.scala:117:23] wire valids_0 = entries_ld_0_valid; // @[ReservationStation.scala:117:23, :502:23] reg [1:0] entries_ld_0_bits_q; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_is_config; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_opa_valid; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:117:23] reg [2:0] entries_ld_0_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:117:23] wire [2:0] _issue_entry_T_1674 = entries_ld_0_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ld_0_bits_opa_bits_start_garbage; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:117:23] reg [13:0] entries_ld_0_bits_opa_bits_start_data; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:117:23] reg [2:0] entries_ld_0_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:117:23] wire [2:0] _issue_entry_T_1561 = entries_ld_0_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ld_0_bits_opa_bits_end_garbage; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:117:23] reg [13:0] entries_ld_0_bits_opa_bits_end_data; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_opa_bits_wraps_around; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_opa_is_dst; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_issued; // @[ReservationStation.scala:117:23] wire issueds_0 = entries_ld_0_bits_issued; // @[ReservationStation.scala:117:23, :504:24] reg entries_ld_0_bits_complete_on_issue; // @[ReservationStation.scala:117:23] reg [6:0] entries_ld_0_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:117:23] wire [6:0] functs_0 = entries_ld_0_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:117:23, :503:23] reg [4:0] entries_ld_0_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:117:23] reg [4:0] entries_ld_0_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:117:23] reg [4:0] entries_ld_0_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:117:23] reg [6:0] entries_ld_0_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:117:23] reg [63:0] entries_ld_0_bits_cmd_cmd_rs1; // @[ReservationStation.scala:117:23] reg [63:0] entries_ld_0_bits_cmd_cmd_rs2; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:117:23] reg [31:0] entries_ld_0_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_0_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_0_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_cmd_cmd_status_v; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:117:23] reg [22:0] entries_ld_0_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_0_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_0_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:117:23] reg [7:0] entries_ld_0_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_0_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_0_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_0_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_0_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_cmd_rob_id_valid; // @[ReservationStation.scala:117:23] reg [5:0] entries_ld_0_bits_cmd_rob_id_bits; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_deps_ld_0; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_deps_ld_1; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_deps_ld_2; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_deps_ld_3; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_deps_ld_4; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_deps_ld_5; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_deps_ld_6; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_deps_ld_7; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_deps_ex_0; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_deps_ex_1; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_deps_ex_2; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_deps_ex_3; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_deps_ex_4; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_deps_ex_5; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_deps_ex_6; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_deps_ex_7; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_deps_ex_8; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_deps_ex_9; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_deps_ex_10; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_deps_ex_11; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_deps_ex_12; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_deps_ex_13; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_deps_ex_14; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_deps_ex_15; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_deps_st_0; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_deps_st_1; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_deps_st_2; // @[ReservationStation.scala:117:23] reg entries_ld_0_bits_deps_st_3; // @[ReservationStation.scala:117:23] reg [31:0] entries_ld_0_bits_allocated_at; // @[ReservationStation.scala:117:23] reg entries_ld_1_valid; // @[ReservationStation.scala:117:23] wire valids_1 = entries_ld_1_valid; // @[ReservationStation.scala:117:23, :502:23] reg [1:0] entries_ld_1_bits_q; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_is_config; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_opa_valid; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:117:23] reg [2:0] entries_ld_1_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:117:23] wire [2:0] _issue_entry_T_1676 = entries_ld_1_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ld_1_bits_opa_bits_start_garbage; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:117:23] reg [13:0] entries_ld_1_bits_opa_bits_start_data; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:117:23] reg [2:0] entries_ld_1_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:117:23] wire [2:0] _issue_entry_T_1563 = entries_ld_1_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ld_1_bits_opa_bits_end_garbage; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:117:23] reg [13:0] entries_ld_1_bits_opa_bits_end_data; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_opa_bits_wraps_around; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_opa_is_dst; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_issued; // @[ReservationStation.scala:117:23] wire issueds_1 = entries_ld_1_bits_issued; // @[ReservationStation.scala:117:23, :504:24] reg entries_ld_1_bits_complete_on_issue; // @[ReservationStation.scala:117:23] reg [6:0] entries_ld_1_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:117:23] wire [6:0] functs_1 = entries_ld_1_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:117:23, :503:23] reg [4:0] entries_ld_1_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:117:23] reg [4:0] entries_ld_1_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:117:23] reg [4:0] entries_ld_1_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:117:23] reg [6:0] entries_ld_1_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:117:23] reg [63:0] entries_ld_1_bits_cmd_cmd_rs1; // @[ReservationStation.scala:117:23] reg [63:0] entries_ld_1_bits_cmd_cmd_rs2; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:117:23] reg [31:0] entries_ld_1_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_1_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_1_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_cmd_cmd_status_v; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:117:23] reg [22:0] entries_ld_1_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_1_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_1_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:117:23] reg [7:0] entries_ld_1_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_1_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_1_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_1_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_1_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_cmd_rob_id_valid; // @[ReservationStation.scala:117:23] reg [5:0] entries_ld_1_bits_cmd_rob_id_bits; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_deps_ld_0; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_deps_ld_1; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_deps_ld_2; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_deps_ld_3; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_deps_ld_4; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_deps_ld_5; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_deps_ld_6; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_deps_ld_7; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_deps_ex_0; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_deps_ex_1; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_deps_ex_2; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_deps_ex_3; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_deps_ex_4; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_deps_ex_5; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_deps_ex_6; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_deps_ex_7; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_deps_ex_8; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_deps_ex_9; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_deps_ex_10; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_deps_ex_11; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_deps_ex_12; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_deps_ex_13; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_deps_ex_14; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_deps_ex_15; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_deps_st_0; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_deps_st_1; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_deps_st_2; // @[ReservationStation.scala:117:23] reg entries_ld_1_bits_deps_st_3; // @[ReservationStation.scala:117:23] reg [31:0] entries_ld_1_bits_allocated_at; // @[ReservationStation.scala:117:23] reg entries_ld_2_valid; // @[ReservationStation.scala:117:23] wire valids_2 = entries_ld_2_valid; // @[ReservationStation.scala:117:23, :502:23] reg [1:0] entries_ld_2_bits_q; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_is_config; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_opa_valid; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:117:23] reg [2:0] entries_ld_2_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:117:23] wire [2:0] _issue_entry_T_1678 = entries_ld_2_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ld_2_bits_opa_bits_start_garbage; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:117:23] reg [13:0] entries_ld_2_bits_opa_bits_start_data; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:117:23] reg [2:0] entries_ld_2_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:117:23] wire [2:0] _issue_entry_T_1565 = entries_ld_2_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ld_2_bits_opa_bits_end_garbage; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:117:23] reg [13:0] entries_ld_2_bits_opa_bits_end_data; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_opa_bits_wraps_around; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_opa_is_dst; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_issued; // @[ReservationStation.scala:117:23] wire issueds_2 = entries_ld_2_bits_issued; // @[ReservationStation.scala:117:23, :504:24] reg entries_ld_2_bits_complete_on_issue; // @[ReservationStation.scala:117:23] reg [6:0] entries_ld_2_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:117:23] wire [6:0] functs_2 = entries_ld_2_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:117:23, :503:23] reg [4:0] entries_ld_2_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:117:23] reg [4:0] entries_ld_2_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:117:23] reg [4:0] entries_ld_2_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:117:23] reg [6:0] entries_ld_2_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:117:23] reg [63:0] entries_ld_2_bits_cmd_cmd_rs1; // @[ReservationStation.scala:117:23] reg [63:0] entries_ld_2_bits_cmd_cmd_rs2; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:117:23] reg [31:0] entries_ld_2_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_2_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_2_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_cmd_cmd_status_v; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:117:23] reg [22:0] entries_ld_2_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_2_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_2_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:117:23] reg [7:0] entries_ld_2_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_2_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_2_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_2_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_2_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_cmd_rob_id_valid; // @[ReservationStation.scala:117:23] reg [5:0] entries_ld_2_bits_cmd_rob_id_bits; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_deps_ld_0; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_deps_ld_1; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_deps_ld_2; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_deps_ld_3; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_deps_ld_4; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_deps_ld_5; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_deps_ld_6; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_deps_ld_7; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_deps_ex_0; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_deps_ex_1; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_deps_ex_2; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_deps_ex_3; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_deps_ex_4; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_deps_ex_5; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_deps_ex_6; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_deps_ex_7; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_deps_ex_8; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_deps_ex_9; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_deps_ex_10; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_deps_ex_11; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_deps_ex_12; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_deps_ex_13; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_deps_ex_14; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_deps_ex_15; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_deps_st_0; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_deps_st_1; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_deps_st_2; // @[ReservationStation.scala:117:23] reg entries_ld_2_bits_deps_st_3; // @[ReservationStation.scala:117:23] reg [31:0] entries_ld_2_bits_allocated_at; // @[ReservationStation.scala:117:23] reg entries_ld_3_valid; // @[ReservationStation.scala:117:23] wire valids_3 = entries_ld_3_valid; // @[ReservationStation.scala:117:23, :502:23] reg [1:0] entries_ld_3_bits_q; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_is_config; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_opa_valid; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:117:23] reg [2:0] entries_ld_3_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:117:23] wire [2:0] _issue_entry_T_1680 = entries_ld_3_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ld_3_bits_opa_bits_start_garbage; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:117:23] reg [13:0] entries_ld_3_bits_opa_bits_start_data; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:117:23] reg [2:0] entries_ld_3_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:117:23] wire [2:0] _issue_entry_T_1567 = entries_ld_3_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ld_3_bits_opa_bits_end_garbage; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:117:23] reg [13:0] entries_ld_3_bits_opa_bits_end_data; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_opa_bits_wraps_around; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_opa_is_dst; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_issued; // @[ReservationStation.scala:117:23] wire issueds_3 = entries_ld_3_bits_issued; // @[ReservationStation.scala:117:23, :504:24] reg entries_ld_3_bits_complete_on_issue; // @[ReservationStation.scala:117:23] reg [6:0] entries_ld_3_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:117:23] wire [6:0] functs_3 = entries_ld_3_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:117:23, :503:23] reg [4:0] entries_ld_3_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:117:23] reg [4:0] entries_ld_3_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:117:23] reg [4:0] entries_ld_3_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:117:23] reg [6:0] entries_ld_3_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:117:23] reg [63:0] entries_ld_3_bits_cmd_cmd_rs1; // @[ReservationStation.scala:117:23] reg [63:0] entries_ld_3_bits_cmd_cmd_rs2; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:117:23] reg [31:0] entries_ld_3_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_3_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_3_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_cmd_cmd_status_v; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:117:23] reg [22:0] entries_ld_3_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_3_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_3_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:117:23] reg [7:0] entries_ld_3_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_3_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_3_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_3_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_3_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_cmd_rob_id_valid; // @[ReservationStation.scala:117:23] reg [5:0] entries_ld_3_bits_cmd_rob_id_bits; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_deps_ld_0; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_deps_ld_1; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_deps_ld_2; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_deps_ld_3; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_deps_ld_4; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_deps_ld_5; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_deps_ld_6; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_deps_ld_7; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_deps_ex_0; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_deps_ex_1; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_deps_ex_2; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_deps_ex_3; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_deps_ex_4; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_deps_ex_5; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_deps_ex_6; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_deps_ex_7; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_deps_ex_8; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_deps_ex_9; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_deps_ex_10; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_deps_ex_11; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_deps_ex_12; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_deps_ex_13; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_deps_ex_14; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_deps_ex_15; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_deps_st_0; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_deps_st_1; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_deps_st_2; // @[ReservationStation.scala:117:23] reg entries_ld_3_bits_deps_st_3; // @[ReservationStation.scala:117:23] reg [31:0] entries_ld_3_bits_allocated_at; // @[ReservationStation.scala:117:23] reg entries_ld_4_valid; // @[ReservationStation.scala:117:23] wire valids_4 = entries_ld_4_valid; // @[ReservationStation.scala:117:23, :502:23] reg [1:0] entries_ld_4_bits_q; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_is_config; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_opa_valid; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:117:23] reg [2:0] entries_ld_4_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:117:23] wire [2:0] _issue_entry_T_1682 = entries_ld_4_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ld_4_bits_opa_bits_start_garbage; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:117:23] reg [13:0] entries_ld_4_bits_opa_bits_start_data; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:117:23] reg [2:0] entries_ld_4_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:117:23] wire [2:0] _issue_entry_T_1569 = entries_ld_4_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ld_4_bits_opa_bits_end_garbage; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:117:23] reg [13:0] entries_ld_4_bits_opa_bits_end_data; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_opa_bits_wraps_around; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_opa_is_dst; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_issued; // @[ReservationStation.scala:117:23] wire issueds_4 = entries_ld_4_bits_issued; // @[ReservationStation.scala:117:23, :504:24] reg entries_ld_4_bits_complete_on_issue; // @[ReservationStation.scala:117:23] reg [6:0] entries_ld_4_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:117:23] wire [6:0] functs_4 = entries_ld_4_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:117:23, :503:23] reg [4:0] entries_ld_4_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:117:23] reg [4:0] entries_ld_4_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:117:23] reg [4:0] entries_ld_4_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:117:23] reg [6:0] entries_ld_4_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:117:23] reg [63:0] entries_ld_4_bits_cmd_cmd_rs1; // @[ReservationStation.scala:117:23] reg [63:0] entries_ld_4_bits_cmd_cmd_rs2; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:117:23] reg [31:0] entries_ld_4_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_4_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_4_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_cmd_cmd_status_v; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:117:23] reg [22:0] entries_ld_4_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_4_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_4_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:117:23] reg [7:0] entries_ld_4_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_4_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_4_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_4_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_4_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_cmd_rob_id_valid; // @[ReservationStation.scala:117:23] reg [5:0] entries_ld_4_bits_cmd_rob_id_bits; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_deps_ld_0; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_deps_ld_1; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_deps_ld_2; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_deps_ld_3; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_deps_ld_4; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_deps_ld_5; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_deps_ld_6; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_deps_ld_7; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_deps_ex_0; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_deps_ex_1; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_deps_ex_2; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_deps_ex_3; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_deps_ex_4; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_deps_ex_5; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_deps_ex_6; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_deps_ex_7; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_deps_ex_8; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_deps_ex_9; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_deps_ex_10; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_deps_ex_11; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_deps_ex_12; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_deps_ex_13; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_deps_ex_14; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_deps_ex_15; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_deps_st_0; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_deps_st_1; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_deps_st_2; // @[ReservationStation.scala:117:23] reg entries_ld_4_bits_deps_st_3; // @[ReservationStation.scala:117:23] reg [31:0] entries_ld_4_bits_allocated_at; // @[ReservationStation.scala:117:23] reg entries_ld_5_valid; // @[ReservationStation.scala:117:23] wire valids_5 = entries_ld_5_valid; // @[ReservationStation.scala:117:23, :502:23] reg [1:0] entries_ld_5_bits_q; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_is_config; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_opa_valid; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:117:23] reg [2:0] entries_ld_5_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:117:23] wire [2:0] _issue_entry_T_1684 = entries_ld_5_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ld_5_bits_opa_bits_start_garbage; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:117:23] reg [13:0] entries_ld_5_bits_opa_bits_start_data; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:117:23] reg [2:0] entries_ld_5_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:117:23] wire [2:0] _issue_entry_T_1571 = entries_ld_5_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ld_5_bits_opa_bits_end_garbage; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:117:23] reg [13:0] entries_ld_5_bits_opa_bits_end_data; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_opa_bits_wraps_around; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_opa_is_dst; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_issued; // @[ReservationStation.scala:117:23] wire issueds_5 = entries_ld_5_bits_issued; // @[ReservationStation.scala:117:23, :504:24] reg entries_ld_5_bits_complete_on_issue; // @[ReservationStation.scala:117:23] reg [6:0] entries_ld_5_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:117:23] wire [6:0] functs_5 = entries_ld_5_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:117:23, :503:23] reg [4:0] entries_ld_5_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:117:23] reg [4:0] entries_ld_5_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:117:23] reg [4:0] entries_ld_5_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:117:23] reg [6:0] entries_ld_5_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:117:23] reg [63:0] entries_ld_5_bits_cmd_cmd_rs1; // @[ReservationStation.scala:117:23] reg [63:0] entries_ld_5_bits_cmd_cmd_rs2; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:117:23] reg [31:0] entries_ld_5_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_5_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_5_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_cmd_cmd_status_v; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:117:23] reg [22:0] entries_ld_5_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_5_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_5_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:117:23] reg [7:0] entries_ld_5_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_5_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_5_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_5_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_5_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_cmd_rob_id_valid; // @[ReservationStation.scala:117:23] reg [5:0] entries_ld_5_bits_cmd_rob_id_bits; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_deps_ld_0; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_deps_ld_1; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_deps_ld_2; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_deps_ld_3; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_deps_ld_4; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_deps_ld_5; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_deps_ld_6; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_deps_ld_7; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_deps_ex_0; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_deps_ex_1; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_deps_ex_2; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_deps_ex_3; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_deps_ex_4; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_deps_ex_5; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_deps_ex_6; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_deps_ex_7; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_deps_ex_8; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_deps_ex_9; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_deps_ex_10; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_deps_ex_11; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_deps_ex_12; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_deps_ex_13; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_deps_ex_14; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_deps_ex_15; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_deps_st_0; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_deps_st_1; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_deps_st_2; // @[ReservationStation.scala:117:23] reg entries_ld_5_bits_deps_st_3; // @[ReservationStation.scala:117:23] reg [31:0] entries_ld_5_bits_allocated_at; // @[ReservationStation.scala:117:23] reg entries_ld_6_valid; // @[ReservationStation.scala:117:23] wire valids_6 = entries_ld_6_valid; // @[ReservationStation.scala:117:23, :502:23] reg [1:0] entries_ld_6_bits_q; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_is_config; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_opa_valid; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:117:23] reg [2:0] entries_ld_6_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:117:23] wire [2:0] _issue_entry_T_1686 = entries_ld_6_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ld_6_bits_opa_bits_start_garbage; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:117:23] reg [13:0] entries_ld_6_bits_opa_bits_start_data; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:117:23] reg [2:0] entries_ld_6_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:117:23] wire [2:0] _issue_entry_T_1573 = entries_ld_6_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ld_6_bits_opa_bits_end_garbage; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:117:23] reg [13:0] entries_ld_6_bits_opa_bits_end_data; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_opa_bits_wraps_around; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_opa_is_dst; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_issued; // @[ReservationStation.scala:117:23] wire issueds_6 = entries_ld_6_bits_issued; // @[ReservationStation.scala:117:23, :504:24] reg entries_ld_6_bits_complete_on_issue; // @[ReservationStation.scala:117:23] reg [6:0] entries_ld_6_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:117:23] wire [6:0] functs_6 = entries_ld_6_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:117:23, :503:23] reg [4:0] entries_ld_6_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:117:23] reg [4:0] entries_ld_6_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:117:23] reg [4:0] entries_ld_6_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:117:23] reg [6:0] entries_ld_6_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:117:23] reg [63:0] entries_ld_6_bits_cmd_cmd_rs1; // @[ReservationStation.scala:117:23] reg [63:0] entries_ld_6_bits_cmd_cmd_rs2; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:117:23] reg [31:0] entries_ld_6_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_6_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_6_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_cmd_cmd_status_v; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:117:23] reg [22:0] entries_ld_6_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_6_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_6_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:117:23] reg [7:0] entries_ld_6_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_6_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_6_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_6_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_6_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_cmd_rob_id_valid; // @[ReservationStation.scala:117:23] reg [5:0] entries_ld_6_bits_cmd_rob_id_bits; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_deps_ld_0; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_deps_ld_1; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_deps_ld_2; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_deps_ld_3; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_deps_ld_4; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_deps_ld_5; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_deps_ld_6; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_deps_ld_7; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_deps_ex_0; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_deps_ex_1; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_deps_ex_2; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_deps_ex_3; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_deps_ex_4; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_deps_ex_5; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_deps_ex_6; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_deps_ex_7; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_deps_ex_8; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_deps_ex_9; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_deps_ex_10; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_deps_ex_11; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_deps_ex_12; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_deps_ex_13; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_deps_ex_14; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_deps_ex_15; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_deps_st_0; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_deps_st_1; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_deps_st_2; // @[ReservationStation.scala:117:23] reg entries_ld_6_bits_deps_st_3; // @[ReservationStation.scala:117:23] reg [31:0] entries_ld_6_bits_allocated_at; // @[ReservationStation.scala:117:23] reg entries_ld_7_valid; // @[ReservationStation.scala:117:23] wire valids_7 = entries_ld_7_valid; // @[ReservationStation.scala:117:23, :502:23] reg [1:0] entries_ld_7_bits_q; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_is_config; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_opa_valid; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:117:23] reg [2:0] entries_ld_7_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:117:23] wire [2:0] _issue_entry_T_1688 = entries_ld_7_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ld_7_bits_opa_bits_start_garbage; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:117:23] reg [13:0] entries_ld_7_bits_opa_bits_start_data; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:117:23] reg [2:0] entries_ld_7_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:117:23] wire [2:0] _issue_entry_T_1575 = entries_ld_7_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ld_7_bits_opa_bits_end_garbage; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:117:23] reg [13:0] entries_ld_7_bits_opa_bits_end_data; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_opa_bits_wraps_around; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_opa_is_dst; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_issued; // @[ReservationStation.scala:117:23] wire issueds_7 = entries_ld_7_bits_issued; // @[ReservationStation.scala:117:23, :504:24] reg entries_ld_7_bits_complete_on_issue; // @[ReservationStation.scala:117:23] reg [6:0] entries_ld_7_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:117:23] wire [6:0] functs_7 = entries_ld_7_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:117:23, :503:23] reg [4:0] entries_ld_7_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:117:23] reg [4:0] entries_ld_7_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:117:23] reg [4:0] entries_ld_7_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:117:23] reg [6:0] entries_ld_7_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:117:23] reg [63:0] entries_ld_7_bits_cmd_cmd_rs1; // @[ReservationStation.scala:117:23] reg [63:0] entries_ld_7_bits_cmd_cmd_rs2; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:117:23] reg [31:0] entries_ld_7_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_7_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_7_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_cmd_cmd_status_v; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:117:23] reg [22:0] entries_ld_7_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_7_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_7_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:117:23] reg [7:0] entries_ld_7_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_7_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_7_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_7_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:117:23] reg [1:0] entries_ld_7_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_cmd_rob_id_valid; // @[ReservationStation.scala:117:23] reg [5:0] entries_ld_7_bits_cmd_rob_id_bits; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_deps_ld_0; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_deps_ld_1; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_deps_ld_2; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_deps_ld_3; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_deps_ld_4; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_deps_ld_5; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_deps_ld_6; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_deps_ld_7; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_deps_ex_0; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_deps_ex_1; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_deps_ex_2; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_deps_ex_3; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_deps_ex_4; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_deps_ex_5; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_deps_ex_6; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_deps_ex_7; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_deps_ex_8; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_deps_ex_9; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_deps_ex_10; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_deps_ex_11; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_deps_ex_12; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_deps_ex_13; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_deps_ex_14; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_deps_ex_15; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_deps_st_0; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_deps_st_1; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_deps_st_2; // @[ReservationStation.scala:117:23] reg entries_ld_7_bits_deps_st_3; // @[ReservationStation.scala:117:23] reg [31:0] entries_ld_7_bits_allocated_at; // @[ReservationStation.scala:117:23] reg entries_ex_0_valid; // @[ReservationStation.scala:118:23] wire valids_8 = entries_ex_0_valid; // @[ReservationStation.scala:118:23, :502:23] reg [1:0] entries_ex_0_bits_q; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_is_config; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_opa_valid; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_0_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_5260 = entries_ex_0_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_0_bits_opa_bits_start_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_0_bits_opa_bits_start_data; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_0_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_5027 = entries_ex_0_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_0_bits_opa_bits_end_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_0_bits_opa_bits_end_data; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_opa_bits_wraps_around; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_opa_is_dst; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_opb_valid; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_opb_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_opb_bits_start_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_opb_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_0_bits_opb_bits_start_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_4701 = entries_ex_0_bits_opb_bits_start_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_0_bits_opb_bits_start_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_opb_bits_start_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_0_bits_opb_bits_start_data; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_opb_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_opb_bits_end_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_opb_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_0_bits_opb_bits_end_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_4468 = entries_ex_0_bits_opb_bits_end_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_0_bits_opb_bits_end_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_opb_bits_end_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_0_bits_opb_bits_end_data; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_opb_bits_wraps_around; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_issued; // @[ReservationStation.scala:118:23] wire issueds_8 = entries_ex_0_bits_issued; // @[ReservationStation.scala:118:23, :504:24] reg entries_ex_0_bits_complete_on_issue; // @[ReservationStation.scala:118:23] reg [6:0] entries_ex_0_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23] wire [6:0] functs_8 = entries_ex_0_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23, :503:23] reg [4:0] entries_ex_0_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:118:23] reg [4:0] entries_ex_0_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:118:23] reg [4:0] entries_ex_0_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:118:23] reg [6:0] entries_ex_0_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:118:23] reg [63:0] entries_ex_0_bits_cmd_cmd_rs1; // @[ReservationStation.scala:118:23] reg [63:0] entries_ex_0_bits_cmd_cmd_rs2; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:118:23] reg [31:0] entries_ex_0_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_0_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_0_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_cmd_cmd_status_v; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:118:23] reg [22:0] entries_ex_0_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_0_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_0_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:118:23] reg [7:0] entries_ex_0_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_0_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_0_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_0_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_0_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_cmd_rob_id_valid; // @[ReservationStation.scala:118:23] reg [5:0] entries_ex_0_bits_cmd_rob_id_bits; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_deps_ld_0; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_deps_ld_1; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_deps_ld_2; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_deps_ld_3; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_deps_ld_4; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_deps_ld_5; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_deps_ld_6; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_deps_ld_7; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_deps_ex_0; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_deps_ex_1; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_deps_ex_2; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_deps_ex_3; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_deps_ex_4; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_deps_ex_5; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_deps_ex_6; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_deps_ex_7; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_deps_ex_8; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_deps_ex_9; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_deps_ex_10; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_deps_ex_11; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_deps_ex_12; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_deps_ex_13; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_deps_ex_14; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_deps_ex_15; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_deps_st_0; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_deps_st_1; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_deps_st_2; // @[ReservationStation.scala:118:23] reg entries_ex_0_bits_deps_st_3; // @[ReservationStation.scala:118:23] reg [31:0] entries_ex_0_bits_allocated_at; // @[ReservationStation.scala:118:23] reg entries_ex_1_valid; // @[ReservationStation.scala:118:23] wire valids_9 = entries_ex_1_valid; // @[ReservationStation.scala:118:23, :502:23] reg [1:0] entries_ex_1_bits_q; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_is_config; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_opa_valid; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_1_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_5262 = entries_ex_1_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_1_bits_opa_bits_start_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_1_bits_opa_bits_start_data; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_1_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_5029 = entries_ex_1_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_1_bits_opa_bits_end_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_1_bits_opa_bits_end_data; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_opa_bits_wraps_around; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_opa_is_dst; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_opb_valid; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_opb_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_opb_bits_start_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_opb_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_1_bits_opb_bits_start_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_4703 = entries_ex_1_bits_opb_bits_start_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_1_bits_opb_bits_start_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_opb_bits_start_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_1_bits_opb_bits_start_data; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_opb_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_opb_bits_end_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_opb_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_1_bits_opb_bits_end_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_4470 = entries_ex_1_bits_opb_bits_end_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_1_bits_opb_bits_end_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_opb_bits_end_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_1_bits_opb_bits_end_data; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_opb_bits_wraps_around; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_issued; // @[ReservationStation.scala:118:23] wire issueds_9 = entries_ex_1_bits_issued; // @[ReservationStation.scala:118:23, :504:24] reg entries_ex_1_bits_complete_on_issue; // @[ReservationStation.scala:118:23] reg [6:0] entries_ex_1_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23] wire [6:0] functs_9 = entries_ex_1_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23, :503:23] reg [4:0] entries_ex_1_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:118:23] reg [4:0] entries_ex_1_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:118:23] reg [4:0] entries_ex_1_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:118:23] reg [6:0] entries_ex_1_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:118:23] reg [63:0] entries_ex_1_bits_cmd_cmd_rs1; // @[ReservationStation.scala:118:23] reg [63:0] entries_ex_1_bits_cmd_cmd_rs2; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:118:23] reg [31:0] entries_ex_1_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_1_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_1_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_cmd_cmd_status_v; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:118:23] reg [22:0] entries_ex_1_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_1_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_1_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:118:23] reg [7:0] entries_ex_1_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_1_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_1_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_1_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_1_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_cmd_rob_id_valid; // @[ReservationStation.scala:118:23] reg [5:0] entries_ex_1_bits_cmd_rob_id_bits; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_deps_ld_0; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_deps_ld_1; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_deps_ld_2; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_deps_ld_3; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_deps_ld_4; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_deps_ld_5; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_deps_ld_6; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_deps_ld_7; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_deps_ex_0; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_deps_ex_1; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_deps_ex_2; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_deps_ex_3; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_deps_ex_4; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_deps_ex_5; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_deps_ex_6; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_deps_ex_7; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_deps_ex_8; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_deps_ex_9; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_deps_ex_10; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_deps_ex_11; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_deps_ex_12; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_deps_ex_13; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_deps_ex_14; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_deps_ex_15; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_deps_st_0; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_deps_st_1; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_deps_st_2; // @[ReservationStation.scala:118:23] reg entries_ex_1_bits_deps_st_3; // @[ReservationStation.scala:118:23] reg [31:0] entries_ex_1_bits_allocated_at; // @[ReservationStation.scala:118:23] reg entries_ex_2_valid; // @[ReservationStation.scala:118:23] wire valids_10 = entries_ex_2_valid; // @[ReservationStation.scala:118:23, :502:23] reg [1:0] entries_ex_2_bits_q; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_is_config; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_opa_valid; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_2_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_5264 = entries_ex_2_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_2_bits_opa_bits_start_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_2_bits_opa_bits_start_data; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_2_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_5031 = entries_ex_2_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_2_bits_opa_bits_end_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_2_bits_opa_bits_end_data; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_opa_bits_wraps_around; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_opa_is_dst; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_opb_valid; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_opb_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_opb_bits_start_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_opb_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_2_bits_opb_bits_start_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_4705 = entries_ex_2_bits_opb_bits_start_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_2_bits_opb_bits_start_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_opb_bits_start_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_2_bits_opb_bits_start_data; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_opb_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_opb_bits_end_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_opb_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_2_bits_opb_bits_end_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_4472 = entries_ex_2_bits_opb_bits_end_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_2_bits_opb_bits_end_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_opb_bits_end_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_2_bits_opb_bits_end_data; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_opb_bits_wraps_around; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_issued; // @[ReservationStation.scala:118:23] wire issueds_10 = entries_ex_2_bits_issued; // @[ReservationStation.scala:118:23, :504:24] reg entries_ex_2_bits_complete_on_issue; // @[ReservationStation.scala:118:23] reg [6:0] entries_ex_2_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23] wire [6:0] functs_10 = entries_ex_2_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23, :503:23] reg [4:0] entries_ex_2_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:118:23] reg [4:0] entries_ex_2_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:118:23] reg [4:0] entries_ex_2_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:118:23] reg [6:0] entries_ex_2_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:118:23] reg [63:0] entries_ex_2_bits_cmd_cmd_rs1; // @[ReservationStation.scala:118:23] reg [63:0] entries_ex_2_bits_cmd_cmd_rs2; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:118:23] reg [31:0] entries_ex_2_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_2_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_2_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_cmd_cmd_status_v; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:118:23] reg [22:0] entries_ex_2_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_2_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_2_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:118:23] reg [7:0] entries_ex_2_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_2_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_2_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_2_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_2_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_cmd_rob_id_valid; // @[ReservationStation.scala:118:23] reg [5:0] entries_ex_2_bits_cmd_rob_id_bits; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_deps_ld_0; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_deps_ld_1; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_deps_ld_2; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_deps_ld_3; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_deps_ld_4; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_deps_ld_5; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_deps_ld_6; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_deps_ld_7; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_deps_ex_0; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_deps_ex_1; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_deps_ex_2; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_deps_ex_3; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_deps_ex_4; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_deps_ex_5; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_deps_ex_6; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_deps_ex_7; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_deps_ex_8; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_deps_ex_9; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_deps_ex_10; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_deps_ex_11; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_deps_ex_12; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_deps_ex_13; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_deps_ex_14; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_deps_ex_15; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_deps_st_0; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_deps_st_1; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_deps_st_2; // @[ReservationStation.scala:118:23] reg entries_ex_2_bits_deps_st_3; // @[ReservationStation.scala:118:23] reg [31:0] entries_ex_2_bits_allocated_at; // @[ReservationStation.scala:118:23] reg entries_ex_3_valid; // @[ReservationStation.scala:118:23] wire valids_11 = entries_ex_3_valid; // @[ReservationStation.scala:118:23, :502:23] reg [1:0] entries_ex_3_bits_q; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_is_config; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_opa_valid; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_3_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_5266 = entries_ex_3_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_3_bits_opa_bits_start_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_3_bits_opa_bits_start_data; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_3_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_5033 = entries_ex_3_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_3_bits_opa_bits_end_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_3_bits_opa_bits_end_data; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_opa_bits_wraps_around; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_opa_is_dst; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_opb_valid; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_opb_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_opb_bits_start_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_opb_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_3_bits_opb_bits_start_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_4707 = entries_ex_3_bits_opb_bits_start_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_3_bits_opb_bits_start_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_opb_bits_start_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_3_bits_opb_bits_start_data; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_opb_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_opb_bits_end_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_opb_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_3_bits_opb_bits_end_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_4474 = entries_ex_3_bits_opb_bits_end_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_3_bits_opb_bits_end_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_opb_bits_end_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_3_bits_opb_bits_end_data; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_opb_bits_wraps_around; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_issued; // @[ReservationStation.scala:118:23] wire issueds_11 = entries_ex_3_bits_issued; // @[ReservationStation.scala:118:23, :504:24] reg entries_ex_3_bits_complete_on_issue; // @[ReservationStation.scala:118:23] reg [6:0] entries_ex_3_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23] wire [6:0] functs_11 = entries_ex_3_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23, :503:23] reg [4:0] entries_ex_3_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:118:23] reg [4:0] entries_ex_3_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:118:23] reg [4:0] entries_ex_3_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:118:23] reg [6:0] entries_ex_3_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:118:23] reg [63:0] entries_ex_3_bits_cmd_cmd_rs1; // @[ReservationStation.scala:118:23] reg [63:0] entries_ex_3_bits_cmd_cmd_rs2; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:118:23] reg [31:0] entries_ex_3_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_3_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_3_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_cmd_cmd_status_v; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:118:23] reg [22:0] entries_ex_3_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_3_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_3_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:118:23] reg [7:0] entries_ex_3_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_3_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_3_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_3_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_3_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_cmd_rob_id_valid; // @[ReservationStation.scala:118:23] reg [5:0] entries_ex_3_bits_cmd_rob_id_bits; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_deps_ld_0; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_deps_ld_1; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_deps_ld_2; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_deps_ld_3; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_deps_ld_4; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_deps_ld_5; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_deps_ld_6; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_deps_ld_7; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_deps_ex_0; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_deps_ex_1; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_deps_ex_2; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_deps_ex_3; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_deps_ex_4; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_deps_ex_5; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_deps_ex_6; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_deps_ex_7; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_deps_ex_8; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_deps_ex_9; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_deps_ex_10; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_deps_ex_11; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_deps_ex_12; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_deps_ex_13; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_deps_ex_14; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_deps_ex_15; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_deps_st_0; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_deps_st_1; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_deps_st_2; // @[ReservationStation.scala:118:23] reg entries_ex_3_bits_deps_st_3; // @[ReservationStation.scala:118:23] reg [31:0] entries_ex_3_bits_allocated_at; // @[ReservationStation.scala:118:23] reg entries_ex_4_valid; // @[ReservationStation.scala:118:23] wire valids_12 = entries_ex_4_valid; // @[ReservationStation.scala:118:23, :502:23] reg [1:0] entries_ex_4_bits_q; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_is_config; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_opa_valid; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_4_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_5268 = entries_ex_4_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_4_bits_opa_bits_start_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_4_bits_opa_bits_start_data; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_4_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_5035 = entries_ex_4_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_4_bits_opa_bits_end_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_4_bits_opa_bits_end_data; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_opa_bits_wraps_around; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_opa_is_dst; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_opb_valid; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_opb_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_opb_bits_start_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_opb_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_4_bits_opb_bits_start_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_4709 = entries_ex_4_bits_opb_bits_start_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_4_bits_opb_bits_start_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_opb_bits_start_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_4_bits_opb_bits_start_data; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_opb_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_opb_bits_end_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_opb_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_4_bits_opb_bits_end_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_4476 = entries_ex_4_bits_opb_bits_end_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_4_bits_opb_bits_end_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_opb_bits_end_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_4_bits_opb_bits_end_data; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_opb_bits_wraps_around; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_issued; // @[ReservationStation.scala:118:23] wire issueds_12 = entries_ex_4_bits_issued; // @[ReservationStation.scala:118:23, :504:24] reg entries_ex_4_bits_complete_on_issue; // @[ReservationStation.scala:118:23] reg [6:0] entries_ex_4_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23] wire [6:0] functs_12 = entries_ex_4_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23, :503:23] reg [4:0] entries_ex_4_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:118:23] reg [4:0] entries_ex_4_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:118:23] reg [4:0] entries_ex_4_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:118:23] reg [6:0] entries_ex_4_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:118:23] reg [63:0] entries_ex_4_bits_cmd_cmd_rs1; // @[ReservationStation.scala:118:23] reg [63:0] entries_ex_4_bits_cmd_cmd_rs2; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:118:23] reg [31:0] entries_ex_4_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_4_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_4_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_cmd_cmd_status_v; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:118:23] reg [22:0] entries_ex_4_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_4_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_4_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:118:23] reg [7:0] entries_ex_4_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_4_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_4_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_4_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_4_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_cmd_rob_id_valid; // @[ReservationStation.scala:118:23] reg [5:0] entries_ex_4_bits_cmd_rob_id_bits; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_deps_ld_0; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_deps_ld_1; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_deps_ld_2; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_deps_ld_3; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_deps_ld_4; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_deps_ld_5; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_deps_ld_6; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_deps_ld_7; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_deps_ex_0; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_deps_ex_1; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_deps_ex_2; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_deps_ex_3; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_deps_ex_4; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_deps_ex_5; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_deps_ex_6; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_deps_ex_7; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_deps_ex_8; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_deps_ex_9; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_deps_ex_10; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_deps_ex_11; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_deps_ex_12; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_deps_ex_13; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_deps_ex_14; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_deps_ex_15; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_deps_st_0; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_deps_st_1; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_deps_st_2; // @[ReservationStation.scala:118:23] reg entries_ex_4_bits_deps_st_3; // @[ReservationStation.scala:118:23] reg [31:0] entries_ex_4_bits_allocated_at; // @[ReservationStation.scala:118:23] reg entries_ex_5_valid; // @[ReservationStation.scala:118:23] wire valids_13 = entries_ex_5_valid; // @[ReservationStation.scala:118:23, :502:23] reg [1:0] entries_ex_5_bits_q; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_is_config; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_opa_valid; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_5_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_5270 = entries_ex_5_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_5_bits_opa_bits_start_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_5_bits_opa_bits_start_data; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_5_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_5037 = entries_ex_5_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_5_bits_opa_bits_end_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_5_bits_opa_bits_end_data; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_opa_bits_wraps_around; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_opa_is_dst; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_opb_valid; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_opb_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_opb_bits_start_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_opb_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_5_bits_opb_bits_start_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_4711 = entries_ex_5_bits_opb_bits_start_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_5_bits_opb_bits_start_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_opb_bits_start_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_5_bits_opb_bits_start_data; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_opb_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_opb_bits_end_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_opb_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_5_bits_opb_bits_end_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_4478 = entries_ex_5_bits_opb_bits_end_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_5_bits_opb_bits_end_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_opb_bits_end_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_5_bits_opb_bits_end_data; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_opb_bits_wraps_around; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_issued; // @[ReservationStation.scala:118:23] wire issueds_13 = entries_ex_5_bits_issued; // @[ReservationStation.scala:118:23, :504:24] reg entries_ex_5_bits_complete_on_issue; // @[ReservationStation.scala:118:23] reg [6:0] entries_ex_5_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23] wire [6:0] functs_13 = entries_ex_5_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23, :503:23] reg [4:0] entries_ex_5_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:118:23] reg [4:0] entries_ex_5_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:118:23] reg [4:0] entries_ex_5_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:118:23] reg [6:0] entries_ex_5_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:118:23] reg [63:0] entries_ex_5_bits_cmd_cmd_rs1; // @[ReservationStation.scala:118:23] reg [63:0] entries_ex_5_bits_cmd_cmd_rs2; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:118:23] reg [31:0] entries_ex_5_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_5_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_5_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_cmd_cmd_status_v; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:118:23] reg [22:0] entries_ex_5_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_5_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_5_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:118:23] reg [7:0] entries_ex_5_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_5_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_5_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_5_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_5_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_cmd_rob_id_valid; // @[ReservationStation.scala:118:23] reg [5:0] entries_ex_5_bits_cmd_rob_id_bits; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_deps_ld_0; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_deps_ld_1; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_deps_ld_2; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_deps_ld_3; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_deps_ld_4; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_deps_ld_5; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_deps_ld_6; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_deps_ld_7; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_deps_ex_0; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_deps_ex_1; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_deps_ex_2; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_deps_ex_3; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_deps_ex_4; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_deps_ex_5; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_deps_ex_6; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_deps_ex_7; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_deps_ex_8; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_deps_ex_9; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_deps_ex_10; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_deps_ex_11; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_deps_ex_12; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_deps_ex_13; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_deps_ex_14; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_deps_ex_15; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_deps_st_0; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_deps_st_1; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_deps_st_2; // @[ReservationStation.scala:118:23] reg entries_ex_5_bits_deps_st_3; // @[ReservationStation.scala:118:23] reg [31:0] entries_ex_5_bits_allocated_at; // @[ReservationStation.scala:118:23] reg entries_ex_6_valid; // @[ReservationStation.scala:118:23] wire valids_14 = entries_ex_6_valid; // @[ReservationStation.scala:118:23, :502:23] reg [1:0] entries_ex_6_bits_q; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_is_config; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_opa_valid; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_6_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_5272 = entries_ex_6_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_6_bits_opa_bits_start_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_6_bits_opa_bits_start_data; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_6_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_5039 = entries_ex_6_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_6_bits_opa_bits_end_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_6_bits_opa_bits_end_data; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_opa_bits_wraps_around; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_opa_is_dst; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_opb_valid; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_opb_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_opb_bits_start_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_opb_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_6_bits_opb_bits_start_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_4713 = entries_ex_6_bits_opb_bits_start_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_6_bits_opb_bits_start_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_opb_bits_start_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_6_bits_opb_bits_start_data; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_opb_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_opb_bits_end_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_opb_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_6_bits_opb_bits_end_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_4480 = entries_ex_6_bits_opb_bits_end_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_6_bits_opb_bits_end_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_opb_bits_end_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_6_bits_opb_bits_end_data; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_opb_bits_wraps_around; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_issued; // @[ReservationStation.scala:118:23] wire issueds_14 = entries_ex_6_bits_issued; // @[ReservationStation.scala:118:23, :504:24] reg entries_ex_6_bits_complete_on_issue; // @[ReservationStation.scala:118:23] reg [6:0] entries_ex_6_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23] wire [6:0] functs_14 = entries_ex_6_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23, :503:23] reg [4:0] entries_ex_6_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:118:23] reg [4:0] entries_ex_6_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:118:23] reg [4:0] entries_ex_6_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:118:23] reg [6:0] entries_ex_6_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:118:23] reg [63:0] entries_ex_6_bits_cmd_cmd_rs1; // @[ReservationStation.scala:118:23] reg [63:0] entries_ex_6_bits_cmd_cmd_rs2; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:118:23] reg [31:0] entries_ex_6_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_6_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_6_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_cmd_cmd_status_v; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:118:23] reg [22:0] entries_ex_6_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_6_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_6_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:118:23] reg [7:0] entries_ex_6_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_6_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_6_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_6_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_6_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_cmd_rob_id_valid; // @[ReservationStation.scala:118:23] reg [5:0] entries_ex_6_bits_cmd_rob_id_bits; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_deps_ld_0; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_deps_ld_1; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_deps_ld_2; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_deps_ld_3; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_deps_ld_4; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_deps_ld_5; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_deps_ld_6; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_deps_ld_7; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_deps_ex_0; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_deps_ex_1; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_deps_ex_2; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_deps_ex_3; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_deps_ex_4; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_deps_ex_5; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_deps_ex_6; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_deps_ex_7; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_deps_ex_8; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_deps_ex_9; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_deps_ex_10; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_deps_ex_11; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_deps_ex_12; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_deps_ex_13; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_deps_ex_14; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_deps_ex_15; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_deps_st_0; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_deps_st_1; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_deps_st_2; // @[ReservationStation.scala:118:23] reg entries_ex_6_bits_deps_st_3; // @[ReservationStation.scala:118:23] reg [31:0] entries_ex_6_bits_allocated_at; // @[ReservationStation.scala:118:23] reg entries_ex_7_valid; // @[ReservationStation.scala:118:23] wire valids_15 = entries_ex_7_valid; // @[ReservationStation.scala:118:23, :502:23] reg [1:0] entries_ex_7_bits_q; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_is_config; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_opa_valid; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_7_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_5274 = entries_ex_7_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_7_bits_opa_bits_start_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_7_bits_opa_bits_start_data; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_7_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_5041 = entries_ex_7_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_7_bits_opa_bits_end_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_7_bits_opa_bits_end_data; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_opa_bits_wraps_around; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_opa_is_dst; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_opb_valid; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_opb_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_opb_bits_start_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_opb_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_7_bits_opb_bits_start_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_4715 = entries_ex_7_bits_opb_bits_start_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_7_bits_opb_bits_start_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_opb_bits_start_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_7_bits_opb_bits_start_data; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_opb_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_opb_bits_end_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_opb_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_7_bits_opb_bits_end_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_4482 = entries_ex_7_bits_opb_bits_end_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_7_bits_opb_bits_end_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_opb_bits_end_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_7_bits_opb_bits_end_data; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_opb_bits_wraps_around; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_issued; // @[ReservationStation.scala:118:23] wire issueds_15 = entries_ex_7_bits_issued; // @[ReservationStation.scala:118:23, :504:24] reg entries_ex_7_bits_complete_on_issue; // @[ReservationStation.scala:118:23] reg [6:0] entries_ex_7_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23] wire [6:0] functs_15 = entries_ex_7_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23, :503:23] reg [4:0] entries_ex_7_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:118:23] reg [4:0] entries_ex_7_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:118:23] reg [4:0] entries_ex_7_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:118:23] reg [6:0] entries_ex_7_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:118:23] reg [63:0] entries_ex_7_bits_cmd_cmd_rs1; // @[ReservationStation.scala:118:23] reg [63:0] entries_ex_7_bits_cmd_cmd_rs2; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:118:23] reg [31:0] entries_ex_7_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_7_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_7_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_cmd_cmd_status_v; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:118:23] reg [22:0] entries_ex_7_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_7_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_7_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:118:23] reg [7:0] entries_ex_7_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_7_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_7_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_7_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_7_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_cmd_rob_id_valid; // @[ReservationStation.scala:118:23] reg [5:0] entries_ex_7_bits_cmd_rob_id_bits; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_deps_ld_0; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_deps_ld_1; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_deps_ld_2; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_deps_ld_3; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_deps_ld_4; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_deps_ld_5; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_deps_ld_6; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_deps_ld_7; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_deps_ex_0; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_deps_ex_1; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_deps_ex_2; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_deps_ex_3; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_deps_ex_4; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_deps_ex_5; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_deps_ex_6; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_deps_ex_7; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_deps_ex_8; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_deps_ex_9; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_deps_ex_10; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_deps_ex_11; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_deps_ex_12; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_deps_ex_13; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_deps_ex_14; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_deps_ex_15; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_deps_st_0; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_deps_st_1; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_deps_st_2; // @[ReservationStation.scala:118:23] reg entries_ex_7_bits_deps_st_3; // @[ReservationStation.scala:118:23] reg [31:0] entries_ex_7_bits_allocated_at; // @[ReservationStation.scala:118:23] reg entries_ex_8_valid; // @[ReservationStation.scala:118:23] wire valids_16 = entries_ex_8_valid; // @[ReservationStation.scala:118:23, :502:23] reg [1:0] entries_ex_8_bits_q; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_is_config; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_opa_valid; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_8_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_5276 = entries_ex_8_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_8_bits_opa_bits_start_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_8_bits_opa_bits_start_data; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_8_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_5043 = entries_ex_8_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_8_bits_opa_bits_end_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_8_bits_opa_bits_end_data; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_opa_bits_wraps_around; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_opa_is_dst; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_opb_valid; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_opb_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_opb_bits_start_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_opb_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_8_bits_opb_bits_start_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_4717 = entries_ex_8_bits_opb_bits_start_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_8_bits_opb_bits_start_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_opb_bits_start_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_8_bits_opb_bits_start_data; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_opb_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_opb_bits_end_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_opb_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_8_bits_opb_bits_end_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_4484 = entries_ex_8_bits_opb_bits_end_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_8_bits_opb_bits_end_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_opb_bits_end_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_8_bits_opb_bits_end_data; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_opb_bits_wraps_around; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_issued; // @[ReservationStation.scala:118:23] wire issueds_16 = entries_ex_8_bits_issued; // @[ReservationStation.scala:118:23, :504:24] reg entries_ex_8_bits_complete_on_issue; // @[ReservationStation.scala:118:23] reg [6:0] entries_ex_8_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23] wire [6:0] functs_16 = entries_ex_8_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23, :503:23] reg [4:0] entries_ex_8_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:118:23] reg [4:0] entries_ex_8_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:118:23] reg [4:0] entries_ex_8_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:118:23] reg [6:0] entries_ex_8_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:118:23] reg [63:0] entries_ex_8_bits_cmd_cmd_rs1; // @[ReservationStation.scala:118:23] reg [63:0] entries_ex_8_bits_cmd_cmd_rs2; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:118:23] reg [31:0] entries_ex_8_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_8_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_8_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_cmd_cmd_status_v; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:118:23] reg [22:0] entries_ex_8_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_8_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_8_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:118:23] reg [7:0] entries_ex_8_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_8_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_8_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_8_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_8_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_cmd_rob_id_valid; // @[ReservationStation.scala:118:23] reg [5:0] entries_ex_8_bits_cmd_rob_id_bits; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_deps_ld_0; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_deps_ld_1; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_deps_ld_2; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_deps_ld_3; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_deps_ld_4; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_deps_ld_5; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_deps_ld_6; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_deps_ld_7; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_deps_ex_0; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_deps_ex_1; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_deps_ex_2; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_deps_ex_3; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_deps_ex_4; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_deps_ex_5; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_deps_ex_6; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_deps_ex_7; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_deps_ex_8; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_deps_ex_9; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_deps_ex_10; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_deps_ex_11; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_deps_ex_12; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_deps_ex_13; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_deps_ex_14; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_deps_ex_15; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_deps_st_0; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_deps_st_1; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_deps_st_2; // @[ReservationStation.scala:118:23] reg entries_ex_8_bits_deps_st_3; // @[ReservationStation.scala:118:23] reg [31:0] entries_ex_8_bits_allocated_at; // @[ReservationStation.scala:118:23] reg entries_ex_9_valid; // @[ReservationStation.scala:118:23] wire valids_17 = entries_ex_9_valid; // @[ReservationStation.scala:118:23, :502:23] reg [1:0] entries_ex_9_bits_q; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_is_config; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_opa_valid; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_9_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_5278 = entries_ex_9_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_9_bits_opa_bits_start_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_9_bits_opa_bits_start_data; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_9_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_5045 = entries_ex_9_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_9_bits_opa_bits_end_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_9_bits_opa_bits_end_data; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_opa_bits_wraps_around; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_opa_is_dst; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_opb_valid; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_opb_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_opb_bits_start_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_opb_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_9_bits_opb_bits_start_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_4719 = entries_ex_9_bits_opb_bits_start_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_9_bits_opb_bits_start_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_opb_bits_start_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_9_bits_opb_bits_start_data; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_opb_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_opb_bits_end_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_opb_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_9_bits_opb_bits_end_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_4486 = entries_ex_9_bits_opb_bits_end_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_9_bits_opb_bits_end_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_opb_bits_end_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_9_bits_opb_bits_end_data; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_opb_bits_wraps_around; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_issued; // @[ReservationStation.scala:118:23] wire issueds_17 = entries_ex_9_bits_issued; // @[ReservationStation.scala:118:23, :504:24] reg entries_ex_9_bits_complete_on_issue; // @[ReservationStation.scala:118:23] reg [6:0] entries_ex_9_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23] wire [6:0] functs_17 = entries_ex_9_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23, :503:23] reg [4:0] entries_ex_9_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:118:23] reg [4:0] entries_ex_9_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:118:23] reg [4:0] entries_ex_9_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:118:23] reg [6:0] entries_ex_9_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:118:23] reg [63:0] entries_ex_9_bits_cmd_cmd_rs1; // @[ReservationStation.scala:118:23] reg [63:0] entries_ex_9_bits_cmd_cmd_rs2; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:118:23] reg [31:0] entries_ex_9_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_9_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_9_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_cmd_cmd_status_v; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:118:23] reg [22:0] entries_ex_9_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_9_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_9_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:118:23] reg [7:0] entries_ex_9_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_9_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_9_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_9_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_9_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_cmd_rob_id_valid; // @[ReservationStation.scala:118:23] reg [5:0] entries_ex_9_bits_cmd_rob_id_bits; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_deps_ld_0; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_deps_ld_1; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_deps_ld_2; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_deps_ld_3; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_deps_ld_4; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_deps_ld_5; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_deps_ld_6; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_deps_ld_7; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_deps_ex_0; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_deps_ex_1; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_deps_ex_2; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_deps_ex_3; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_deps_ex_4; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_deps_ex_5; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_deps_ex_6; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_deps_ex_7; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_deps_ex_8; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_deps_ex_9; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_deps_ex_10; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_deps_ex_11; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_deps_ex_12; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_deps_ex_13; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_deps_ex_14; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_deps_ex_15; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_deps_st_0; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_deps_st_1; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_deps_st_2; // @[ReservationStation.scala:118:23] reg entries_ex_9_bits_deps_st_3; // @[ReservationStation.scala:118:23] reg [31:0] entries_ex_9_bits_allocated_at; // @[ReservationStation.scala:118:23] reg entries_ex_10_valid; // @[ReservationStation.scala:118:23] wire valids_18 = entries_ex_10_valid; // @[ReservationStation.scala:118:23, :502:23] reg [1:0] entries_ex_10_bits_q; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_is_config; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_opa_valid; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_10_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_5280 = entries_ex_10_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_10_bits_opa_bits_start_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_10_bits_opa_bits_start_data; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_10_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_5047 = entries_ex_10_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_10_bits_opa_bits_end_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_10_bits_opa_bits_end_data; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_opa_bits_wraps_around; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_opa_is_dst; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_opb_valid; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_opb_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_opb_bits_start_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_opb_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_10_bits_opb_bits_start_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_4721 = entries_ex_10_bits_opb_bits_start_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_10_bits_opb_bits_start_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_opb_bits_start_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_10_bits_opb_bits_start_data; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_opb_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_opb_bits_end_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_opb_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_10_bits_opb_bits_end_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_4488 = entries_ex_10_bits_opb_bits_end_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_10_bits_opb_bits_end_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_opb_bits_end_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_10_bits_opb_bits_end_data; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_opb_bits_wraps_around; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_issued; // @[ReservationStation.scala:118:23] wire issueds_18 = entries_ex_10_bits_issued; // @[ReservationStation.scala:118:23, :504:24] reg entries_ex_10_bits_complete_on_issue; // @[ReservationStation.scala:118:23] reg [6:0] entries_ex_10_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23] wire [6:0] functs_18 = entries_ex_10_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23, :503:23] reg [4:0] entries_ex_10_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:118:23] reg [4:0] entries_ex_10_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:118:23] reg [4:0] entries_ex_10_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:118:23] reg [6:0] entries_ex_10_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:118:23] reg [63:0] entries_ex_10_bits_cmd_cmd_rs1; // @[ReservationStation.scala:118:23] reg [63:0] entries_ex_10_bits_cmd_cmd_rs2; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:118:23] reg [31:0] entries_ex_10_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_10_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_10_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_cmd_cmd_status_v; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:118:23] reg [22:0] entries_ex_10_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_10_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_10_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:118:23] reg [7:0] entries_ex_10_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_10_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_10_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_10_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_10_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_cmd_rob_id_valid; // @[ReservationStation.scala:118:23] reg [5:0] entries_ex_10_bits_cmd_rob_id_bits; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_deps_ld_0; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_deps_ld_1; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_deps_ld_2; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_deps_ld_3; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_deps_ld_4; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_deps_ld_5; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_deps_ld_6; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_deps_ld_7; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_deps_ex_0; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_deps_ex_1; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_deps_ex_2; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_deps_ex_3; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_deps_ex_4; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_deps_ex_5; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_deps_ex_6; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_deps_ex_7; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_deps_ex_8; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_deps_ex_9; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_deps_ex_10; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_deps_ex_11; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_deps_ex_12; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_deps_ex_13; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_deps_ex_14; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_deps_ex_15; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_deps_st_0; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_deps_st_1; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_deps_st_2; // @[ReservationStation.scala:118:23] reg entries_ex_10_bits_deps_st_3; // @[ReservationStation.scala:118:23] reg [31:0] entries_ex_10_bits_allocated_at; // @[ReservationStation.scala:118:23] reg entries_ex_11_valid; // @[ReservationStation.scala:118:23] wire valids_19 = entries_ex_11_valid; // @[ReservationStation.scala:118:23, :502:23] reg [1:0] entries_ex_11_bits_q; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_is_config; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_opa_valid; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_11_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_5282 = entries_ex_11_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_11_bits_opa_bits_start_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_11_bits_opa_bits_start_data; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_11_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_5049 = entries_ex_11_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_11_bits_opa_bits_end_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_11_bits_opa_bits_end_data; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_opa_bits_wraps_around; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_opa_is_dst; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_opb_valid; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_opb_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_opb_bits_start_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_opb_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_11_bits_opb_bits_start_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_4723 = entries_ex_11_bits_opb_bits_start_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_11_bits_opb_bits_start_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_opb_bits_start_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_11_bits_opb_bits_start_data; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_opb_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_opb_bits_end_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_opb_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_11_bits_opb_bits_end_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_4490 = entries_ex_11_bits_opb_bits_end_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_11_bits_opb_bits_end_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_opb_bits_end_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_11_bits_opb_bits_end_data; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_opb_bits_wraps_around; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_issued; // @[ReservationStation.scala:118:23] wire issueds_19 = entries_ex_11_bits_issued; // @[ReservationStation.scala:118:23, :504:24] reg entries_ex_11_bits_complete_on_issue; // @[ReservationStation.scala:118:23] reg [6:0] entries_ex_11_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23] wire [6:0] functs_19 = entries_ex_11_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23, :503:23] reg [4:0] entries_ex_11_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:118:23] reg [4:0] entries_ex_11_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:118:23] reg [4:0] entries_ex_11_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:118:23] reg [6:0] entries_ex_11_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:118:23] reg [63:0] entries_ex_11_bits_cmd_cmd_rs1; // @[ReservationStation.scala:118:23] reg [63:0] entries_ex_11_bits_cmd_cmd_rs2; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:118:23] reg [31:0] entries_ex_11_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_11_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_11_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_cmd_cmd_status_v; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:118:23] reg [22:0] entries_ex_11_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_11_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_11_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:118:23] reg [7:0] entries_ex_11_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_11_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_11_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_11_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_11_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_cmd_rob_id_valid; // @[ReservationStation.scala:118:23] reg [5:0] entries_ex_11_bits_cmd_rob_id_bits; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_deps_ld_0; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_deps_ld_1; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_deps_ld_2; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_deps_ld_3; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_deps_ld_4; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_deps_ld_5; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_deps_ld_6; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_deps_ld_7; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_deps_ex_0; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_deps_ex_1; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_deps_ex_2; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_deps_ex_3; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_deps_ex_4; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_deps_ex_5; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_deps_ex_6; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_deps_ex_7; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_deps_ex_8; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_deps_ex_9; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_deps_ex_10; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_deps_ex_11; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_deps_ex_12; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_deps_ex_13; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_deps_ex_14; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_deps_ex_15; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_deps_st_0; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_deps_st_1; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_deps_st_2; // @[ReservationStation.scala:118:23] reg entries_ex_11_bits_deps_st_3; // @[ReservationStation.scala:118:23] reg [31:0] entries_ex_11_bits_allocated_at; // @[ReservationStation.scala:118:23] reg entries_ex_12_valid; // @[ReservationStation.scala:118:23] wire valids_20 = entries_ex_12_valid; // @[ReservationStation.scala:118:23, :502:23] reg [1:0] entries_ex_12_bits_q; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_is_config; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_opa_valid; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_12_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_5284 = entries_ex_12_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_12_bits_opa_bits_start_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_12_bits_opa_bits_start_data; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_12_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_5051 = entries_ex_12_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_12_bits_opa_bits_end_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_12_bits_opa_bits_end_data; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_opa_bits_wraps_around; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_opa_is_dst; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_opb_valid; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_opb_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_opb_bits_start_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_opb_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_12_bits_opb_bits_start_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_4725 = entries_ex_12_bits_opb_bits_start_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_12_bits_opb_bits_start_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_opb_bits_start_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_12_bits_opb_bits_start_data; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_opb_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_opb_bits_end_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_opb_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_12_bits_opb_bits_end_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_4492 = entries_ex_12_bits_opb_bits_end_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_12_bits_opb_bits_end_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_opb_bits_end_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_12_bits_opb_bits_end_data; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_opb_bits_wraps_around; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_issued; // @[ReservationStation.scala:118:23] wire issueds_20 = entries_ex_12_bits_issued; // @[ReservationStation.scala:118:23, :504:24] reg entries_ex_12_bits_complete_on_issue; // @[ReservationStation.scala:118:23] reg [6:0] entries_ex_12_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23] wire [6:0] functs_20 = entries_ex_12_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23, :503:23] reg [4:0] entries_ex_12_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:118:23] reg [4:0] entries_ex_12_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:118:23] reg [4:0] entries_ex_12_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:118:23] reg [6:0] entries_ex_12_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:118:23] reg [63:0] entries_ex_12_bits_cmd_cmd_rs1; // @[ReservationStation.scala:118:23] reg [63:0] entries_ex_12_bits_cmd_cmd_rs2; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:118:23] reg [31:0] entries_ex_12_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_12_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_12_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_cmd_cmd_status_v; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:118:23] reg [22:0] entries_ex_12_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_12_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_12_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:118:23] reg [7:0] entries_ex_12_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_12_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_12_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_12_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_12_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_cmd_rob_id_valid; // @[ReservationStation.scala:118:23] reg [5:0] entries_ex_12_bits_cmd_rob_id_bits; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_deps_ld_0; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_deps_ld_1; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_deps_ld_2; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_deps_ld_3; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_deps_ld_4; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_deps_ld_5; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_deps_ld_6; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_deps_ld_7; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_deps_ex_0; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_deps_ex_1; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_deps_ex_2; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_deps_ex_3; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_deps_ex_4; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_deps_ex_5; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_deps_ex_6; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_deps_ex_7; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_deps_ex_8; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_deps_ex_9; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_deps_ex_10; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_deps_ex_11; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_deps_ex_12; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_deps_ex_13; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_deps_ex_14; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_deps_ex_15; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_deps_st_0; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_deps_st_1; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_deps_st_2; // @[ReservationStation.scala:118:23] reg entries_ex_12_bits_deps_st_3; // @[ReservationStation.scala:118:23] reg [31:0] entries_ex_12_bits_allocated_at; // @[ReservationStation.scala:118:23] reg entries_ex_13_valid; // @[ReservationStation.scala:118:23] wire valids_21 = entries_ex_13_valid; // @[ReservationStation.scala:118:23, :502:23] reg [1:0] entries_ex_13_bits_q; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_is_config; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_opa_valid; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_13_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_5286 = entries_ex_13_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_13_bits_opa_bits_start_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_13_bits_opa_bits_start_data; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_13_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_5053 = entries_ex_13_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_13_bits_opa_bits_end_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_13_bits_opa_bits_end_data; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_opa_bits_wraps_around; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_opa_is_dst; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_opb_valid; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_opb_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_opb_bits_start_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_opb_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_13_bits_opb_bits_start_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_4727 = entries_ex_13_bits_opb_bits_start_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_13_bits_opb_bits_start_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_opb_bits_start_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_13_bits_opb_bits_start_data; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_opb_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_opb_bits_end_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_opb_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_13_bits_opb_bits_end_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_4494 = entries_ex_13_bits_opb_bits_end_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_13_bits_opb_bits_end_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_opb_bits_end_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_13_bits_opb_bits_end_data; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_opb_bits_wraps_around; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_issued; // @[ReservationStation.scala:118:23] wire issueds_21 = entries_ex_13_bits_issued; // @[ReservationStation.scala:118:23, :504:24] reg entries_ex_13_bits_complete_on_issue; // @[ReservationStation.scala:118:23] reg [6:0] entries_ex_13_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23] wire [6:0] functs_21 = entries_ex_13_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23, :503:23] reg [4:0] entries_ex_13_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:118:23] reg [4:0] entries_ex_13_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:118:23] reg [4:0] entries_ex_13_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:118:23] reg [6:0] entries_ex_13_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:118:23] reg [63:0] entries_ex_13_bits_cmd_cmd_rs1; // @[ReservationStation.scala:118:23] reg [63:0] entries_ex_13_bits_cmd_cmd_rs2; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:118:23] reg [31:0] entries_ex_13_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_13_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_13_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_cmd_cmd_status_v; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:118:23] reg [22:0] entries_ex_13_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_13_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_13_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:118:23] reg [7:0] entries_ex_13_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_13_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_13_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_13_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_13_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_cmd_rob_id_valid; // @[ReservationStation.scala:118:23] reg [5:0] entries_ex_13_bits_cmd_rob_id_bits; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_deps_ld_0; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_deps_ld_1; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_deps_ld_2; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_deps_ld_3; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_deps_ld_4; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_deps_ld_5; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_deps_ld_6; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_deps_ld_7; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_deps_ex_0; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_deps_ex_1; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_deps_ex_2; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_deps_ex_3; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_deps_ex_4; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_deps_ex_5; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_deps_ex_6; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_deps_ex_7; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_deps_ex_8; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_deps_ex_9; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_deps_ex_10; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_deps_ex_11; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_deps_ex_12; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_deps_ex_13; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_deps_ex_14; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_deps_ex_15; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_deps_st_0; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_deps_st_1; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_deps_st_2; // @[ReservationStation.scala:118:23] reg entries_ex_13_bits_deps_st_3; // @[ReservationStation.scala:118:23] reg [31:0] entries_ex_13_bits_allocated_at; // @[ReservationStation.scala:118:23] reg entries_ex_14_valid; // @[ReservationStation.scala:118:23] wire valids_22 = entries_ex_14_valid; // @[ReservationStation.scala:118:23, :502:23] reg [1:0] entries_ex_14_bits_q; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_is_config; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_opa_valid; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_14_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_5288 = entries_ex_14_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_14_bits_opa_bits_start_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_14_bits_opa_bits_start_data; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_14_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_5055 = entries_ex_14_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_14_bits_opa_bits_end_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_14_bits_opa_bits_end_data; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_opa_bits_wraps_around; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_opa_is_dst; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_opb_valid; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_opb_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_opb_bits_start_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_opb_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_14_bits_opb_bits_start_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_4729 = entries_ex_14_bits_opb_bits_start_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_14_bits_opb_bits_start_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_opb_bits_start_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_14_bits_opb_bits_start_data; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_opb_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_opb_bits_end_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_opb_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_14_bits_opb_bits_end_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_4496 = entries_ex_14_bits_opb_bits_end_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_14_bits_opb_bits_end_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_opb_bits_end_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_14_bits_opb_bits_end_data; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_opb_bits_wraps_around; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_issued; // @[ReservationStation.scala:118:23] wire issueds_22 = entries_ex_14_bits_issued; // @[ReservationStation.scala:118:23, :504:24] reg entries_ex_14_bits_complete_on_issue; // @[ReservationStation.scala:118:23] reg [6:0] entries_ex_14_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23] wire [6:0] functs_22 = entries_ex_14_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23, :503:23] reg [4:0] entries_ex_14_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:118:23] reg [4:0] entries_ex_14_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:118:23] reg [4:0] entries_ex_14_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:118:23] reg [6:0] entries_ex_14_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:118:23] reg [63:0] entries_ex_14_bits_cmd_cmd_rs1; // @[ReservationStation.scala:118:23] reg [63:0] entries_ex_14_bits_cmd_cmd_rs2; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:118:23] reg [31:0] entries_ex_14_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_14_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_14_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_cmd_cmd_status_v; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:118:23] reg [22:0] entries_ex_14_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_14_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_14_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:118:23] reg [7:0] entries_ex_14_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_14_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_14_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_14_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_14_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_cmd_rob_id_valid; // @[ReservationStation.scala:118:23] reg [5:0] entries_ex_14_bits_cmd_rob_id_bits; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_deps_ld_0; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_deps_ld_1; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_deps_ld_2; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_deps_ld_3; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_deps_ld_4; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_deps_ld_5; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_deps_ld_6; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_deps_ld_7; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_deps_ex_0; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_deps_ex_1; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_deps_ex_2; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_deps_ex_3; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_deps_ex_4; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_deps_ex_5; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_deps_ex_6; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_deps_ex_7; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_deps_ex_8; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_deps_ex_9; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_deps_ex_10; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_deps_ex_11; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_deps_ex_12; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_deps_ex_13; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_deps_ex_14; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_deps_ex_15; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_deps_st_0; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_deps_st_1; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_deps_st_2; // @[ReservationStation.scala:118:23] reg entries_ex_14_bits_deps_st_3; // @[ReservationStation.scala:118:23] reg [31:0] entries_ex_14_bits_allocated_at; // @[ReservationStation.scala:118:23] reg entries_ex_15_valid; // @[ReservationStation.scala:118:23] wire valids_23 = entries_ex_15_valid; // @[ReservationStation.scala:118:23, :502:23] reg [1:0] entries_ex_15_bits_q; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_is_config; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_opa_valid; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_15_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_5290 = entries_ex_15_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_15_bits_opa_bits_start_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_15_bits_opa_bits_start_data; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_15_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_5057 = entries_ex_15_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_15_bits_opa_bits_end_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_15_bits_opa_bits_end_data; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_opa_bits_wraps_around; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_opa_is_dst; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_opb_valid; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_opb_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_opb_bits_start_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_opb_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_15_bits_opb_bits_start_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_4731 = entries_ex_15_bits_opb_bits_start_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_15_bits_opb_bits_start_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_opb_bits_start_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_15_bits_opb_bits_start_data; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_opb_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_opb_bits_end_accumulate; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_opb_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23] reg [2:0] entries_ex_15_bits_opb_bits_end_norm_cmd; // @[ReservationStation.scala:118:23] wire [2:0] _issue_entry_T_4498 = entries_ex_15_bits_opb_bits_end_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_ex_15_bits_opb_bits_end_garbage; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_opb_bits_end_garbage_bit; // @[ReservationStation.scala:118:23] reg [13:0] entries_ex_15_bits_opb_bits_end_data; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_opb_bits_wraps_around; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_issued; // @[ReservationStation.scala:118:23] wire issueds_23 = entries_ex_15_bits_issued; // @[ReservationStation.scala:118:23, :504:24] reg entries_ex_15_bits_complete_on_issue; // @[ReservationStation.scala:118:23] reg [6:0] entries_ex_15_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23] wire [6:0] functs_23 = entries_ex_15_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23, :503:23] reg [4:0] entries_ex_15_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:118:23] reg [4:0] entries_ex_15_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:118:23] reg [4:0] entries_ex_15_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:118:23] reg [6:0] entries_ex_15_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:118:23] reg [63:0] entries_ex_15_bits_cmd_cmd_rs1; // @[ReservationStation.scala:118:23] reg [63:0] entries_ex_15_bits_cmd_cmd_rs2; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:118:23] reg [31:0] entries_ex_15_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_15_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_15_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_cmd_cmd_status_v; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:118:23] reg [22:0] entries_ex_15_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_15_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_15_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:118:23] reg [7:0] entries_ex_15_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_15_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_15_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_15_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:118:23] reg [1:0] entries_ex_15_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_cmd_rob_id_valid; // @[ReservationStation.scala:118:23] reg [5:0] entries_ex_15_bits_cmd_rob_id_bits; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_deps_ld_0; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_deps_ld_1; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_deps_ld_2; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_deps_ld_3; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_deps_ld_4; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_deps_ld_5; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_deps_ld_6; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_deps_ld_7; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_deps_ex_0; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_deps_ex_1; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_deps_ex_2; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_deps_ex_3; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_deps_ex_4; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_deps_ex_5; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_deps_ex_6; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_deps_ex_7; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_deps_ex_8; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_deps_ex_9; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_deps_ex_10; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_deps_ex_11; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_deps_ex_12; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_deps_ex_13; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_deps_ex_14; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_deps_ex_15; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_deps_st_0; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_deps_st_1; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_deps_st_2; // @[ReservationStation.scala:118:23] reg entries_ex_15_bits_deps_st_3; // @[ReservationStation.scala:118:23] reg [31:0] entries_ex_15_bits_allocated_at; // @[ReservationStation.scala:118:23] reg entries_st_0_valid; // @[ReservationStation.scala:119:23] wire valids_24 = entries_st_0_valid; // @[ReservationStation.scala:119:23, :502:23] reg [1:0] entries_st_0_bits_q; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_is_config; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_opa_valid; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:119:23] reg [2:0] entries_st_0_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:119:23] wire [2:0] _issue_entry_T_6306 = entries_st_0_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_st_0_bits_opa_bits_start_garbage; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:119:23] reg [13:0] entries_st_0_bits_opa_bits_start_data; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:119:23] reg [2:0] entries_st_0_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:119:23] wire [2:0] _issue_entry_T_6253 = entries_st_0_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_st_0_bits_opa_bits_end_garbage; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:119:23] reg [13:0] entries_st_0_bits_opa_bits_end_data; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_opa_bits_wraps_around; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_opa_is_dst; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_issued; // @[ReservationStation.scala:119:23] wire issueds_24 = entries_st_0_bits_issued; // @[ReservationStation.scala:119:23, :504:24] reg entries_st_0_bits_complete_on_issue; // @[ReservationStation.scala:119:23] reg [6:0] entries_st_0_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:119:23] wire [6:0] functs_24 = entries_st_0_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:119:23, :503:23] reg [4:0] entries_st_0_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:119:23] reg [4:0] entries_st_0_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:119:23] reg [4:0] entries_st_0_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:119:23] reg [6:0] entries_st_0_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:119:23] reg [63:0] entries_st_0_bits_cmd_cmd_rs1; // @[ReservationStation.scala:119:23] reg [63:0] entries_st_0_bits_cmd_cmd_rs2; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:119:23] reg [31:0] entries_st_0_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:119:23] reg [1:0] entries_st_0_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:119:23] reg [1:0] entries_st_0_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_cmd_cmd_status_v; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:119:23] reg [22:0] entries_st_0_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:119:23] reg [1:0] entries_st_0_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:119:23] reg [1:0] entries_st_0_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:119:23] reg [7:0] entries_st_0_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:119:23] reg [1:0] entries_st_0_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:119:23] reg [1:0] entries_st_0_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:119:23] reg [1:0] entries_st_0_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:119:23] reg [1:0] entries_st_0_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_cmd_rob_id_valid; // @[ReservationStation.scala:119:23] reg [5:0] entries_st_0_bits_cmd_rob_id_bits; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_deps_ld_0; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_deps_ld_1; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_deps_ld_2; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_deps_ld_3; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_deps_ld_4; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_deps_ld_5; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_deps_ld_6; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_deps_ld_7; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_deps_ex_0; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_deps_ex_1; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_deps_ex_2; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_deps_ex_3; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_deps_ex_4; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_deps_ex_5; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_deps_ex_6; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_deps_ex_7; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_deps_ex_8; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_deps_ex_9; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_deps_ex_10; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_deps_ex_11; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_deps_ex_12; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_deps_ex_13; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_deps_ex_14; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_deps_ex_15; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_deps_st_0; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_deps_st_1; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_deps_st_2; // @[ReservationStation.scala:119:23] reg entries_st_0_bits_deps_st_3; // @[ReservationStation.scala:119:23] reg [31:0] entries_st_0_bits_allocated_at; // @[ReservationStation.scala:119:23] reg entries_st_1_valid; // @[ReservationStation.scala:119:23] wire valids_25 = entries_st_1_valid; // @[ReservationStation.scala:119:23, :502:23] reg [1:0] entries_st_1_bits_q; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_is_config; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_opa_valid; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:119:23] reg [2:0] entries_st_1_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:119:23] wire [2:0] _issue_entry_T_6308 = entries_st_1_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_st_1_bits_opa_bits_start_garbage; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:119:23] reg [13:0] entries_st_1_bits_opa_bits_start_data; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:119:23] reg [2:0] entries_st_1_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:119:23] wire [2:0] _issue_entry_T_6255 = entries_st_1_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_st_1_bits_opa_bits_end_garbage; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:119:23] reg [13:0] entries_st_1_bits_opa_bits_end_data; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_opa_bits_wraps_around; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_opa_is_dst; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_issued; // @[ReservationStation.scala:119:23] wire issueds_25 = entries_st_1_bits_issued; // @[ReservationStation.scala:119:23, :504:24] reg entries_st_1_bits_complete_on_issue; // @[ReservationStation.scala:119:23] reg [6:0] entries_st_1_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:119:23] wire [6:0] functs_25 = entries_st_1_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:119:23, :503:23] reg [4:0] entries_st_1_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:119:23] reg [4:0] entries_st_1_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:119:23] reg [4:0] entries_st_1_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:119:23] reg [6:0] entries_st_1_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:119:23] reg [63:0] entries_st_1_bits_cmd_cmd_rs1; // @[ReservationStation.scala:119:23] reg [63:0] entries_st_1_bits_cmd_cmd_rs2; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:119:23] reg [31:0] entries_st_1_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:119:23] reg [1:0] entries_st_1_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:119:23] reg [1:0] entries_st_1_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_cmd_cmd_status_v; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:119:23] reg [22:0] entries_st_1_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:119:23] reg [1:0] entries_st_1_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:119:23] reg [1:0] entries_st_1_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:119:23] reg [7:0] entries_st_1_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:119:23] reg [1:0] entries_st_1_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:119:23] reg [1:0] entries_st_1_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:119:23] reg [1:0] entries_st_1_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:119:23] reg [1:0] entries_st_1_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_cmd_rob_id_valid; // @[ReservationStation.scala:119:23] reg [5:0] entries_st_1_bits_cmd_rob_id_bits; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_deps_ld_0; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_deps_ld_1; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_deps_ld_2; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_deps_ld_3; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_deps_ld_4; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_deps_ld_5; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_deps_ld_6; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_deps_ld_7; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_deps_ex_0; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_deps_ex_1; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_deps_ex_2; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_deps_ex_3; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_deps_ex_4; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_deps_ex_5; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_deps_ex_6; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_deps_ex_7; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_deps_ex_8; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_deps_ex_9; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_deps_ex_10; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_deps_ex_11; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_deps_ex_12; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_deps_ex_13; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_deps_ex_14; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_deps_ex_15; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_deps_st_0; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_deps_st_1; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_deps_st_2; // @[ReservationStation.scala:119:23] reg entries_st_1_bits_deps_st_3; // @[ReservationStation.scala:119:23] reg [31:0] entries_st_1_bits_allocated_at; // @[ReservationStation.scala:119:23] reg entries_st_2_valid; // @[ReservationStation.scala:119:23] wire valids_26 = entries_st_2_valid; // @[ReservationStation.scala:119:23, :502:23] reg [1:0] entries_st_2_bits_q; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_is_config; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_opa_valid; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:119:23] reg [2:0] entries_st_2_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:119:23] wire [2:0] _issue_entry_T_6310 = entries_st_2_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_st_2_bits_opa_bits_start_garbage; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:119:23] reg [13:0] entries_st_2_bits_opa_bits_start_data; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:119:23] reg [2:0] entries_st_2_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:119:23] wire [2:0] _issue_entry_T_6257 = entries_st_2_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_st_2_bits_opa_bits_end_garbage; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:119:23] reg [13:0] entries_st_2_bits_opa_bits_end_data; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_opa_bits_wraps_around; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_opa_is_dst; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_issued; // @[ReservationStation.scala:119:23] wire issueds_26 = entries_st_2_bits_issued; // @[ReservationStation.scala:119:23, :504:24] reg entries_st_2_bits_complete_on_issue; // @[ReservationStation.scala:119:23] reg [6:0] entries_st_2_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:119:23] wire [6:0] functs_26 = entries_st_2_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:119:23, :503:23] reg [4:0] entries_st_2_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:119:23] reg [4:0] entries_st_2_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:119:23] reg [4:0] entries_st_2_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:119:23] reg [6:0] entries_st_2_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:119:23] reg [63:0] entries_st_2_bits_cmd_cmd_rs1; // @[ReservationStation.scala:119:23] reg [63:0] entries_st_2_bits_cmd_cmd_rs2; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:119:23] reg [31:0] entries_st_2_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:119:23] reg [1:0] entries_st_2_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:119:23] reg [1:0] entries_st_2_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_cmd_cmd_status_v; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:119:23] reg [22:0] entries_st_2_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:119:23] reg [1:0] entries_st_2_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:119:23] reg [1:0] entries_st_2_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:119:23] reg [7:0] entries_st_2_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:119:23] reg [1:0] entries_st_2_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:119:23] reg [1:0] entries_st_2_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:119:23] reg [1:0] entries_st_2_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:119:23] reg [1:0] entries_st_2_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_cmd_rob_id_valid; // @[ReservationStation.scala:119:23] reg [5:0] entries_st_2_bits_cmd_rob_id_bits; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_deps_ld_0; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_deps_ld_1; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_deps_ld_2; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_deps_ld_3; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_deps_ld_4; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_deps_ld_5; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_deps_ld_6; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_deps_ld_7; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_deps_ex_0; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_deps_ex_1; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_deps_ex_2; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_deps_ex_3; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_deps_ex_4; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_deps_ex_5; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_deps_ex_6; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_deps_ex_7; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_deps_ex_8; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_deps_ex_9; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_deps_ex_10; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_deps_ex_11; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_deps_ex_12; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_deps_ex_13; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_deps_ex_14; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_deps_ex_15; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_deps_st_0; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_deps_st_1; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_deps_st_2; // @[ReservationStation.scala:119:23] reg entries_st_2_bits_deps_st_3; // @[ReservationStation.scala:119:23] reg [31:0] entries_st_2_bits_allocated_at; // @[ReservationStation.scala:119:23] reg entries_st_3_valid; // @[ReservationStation.scala:119:23] wire valids_27 = entries_st_3_valid; // @[ReservationStation.scala:119:23, :502:23] reg [1:0] entries_st_3_bits_q; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_is_config; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_opa_valid; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:119:23] reg [2:0] entries_st_3_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:119:23] wire [2:0] _issue_entry_T_6312 = entries_st_3_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_st_3_bits_opa_bits_start_garbage; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:119:23] reg [13:0] entries_st_3_bits_opa_bits_start_data; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:119:23] reg [2:0] entries_st_3_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:119:23] wire [2:0] _issue_entry_T_6259 = entries_st_3_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73] reg [10:0] entries_st_3_bits_opa_bits_end_garbage; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:119:23] reg [13:0] entries_st_3_bits_opa_bits_end_data; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_opa_bits_wraps_around; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_opa_is_dst; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_issued; // @[ReservationStation.scala:119:23] wire issueds_27 = entries_st_3_bits_issued; // @[ReservationStation.scala:119:23, :504:24] reg entries_st_3_bits_complete_on_issue; // @[ReservationStation.scala:119:23] reg [6:0] entries_st_3_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:119:23] wire [6:0] functs_27 = entries_st_3_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:119:23, :503:23] reg [4:0] entries_st_3_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:119:23] reg [4:0] entries_st_3_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:119:23] reg [4:0] entries_st_3_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:119:23] reg [6:0] entries_st_3_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:119:23] reg [63:0] entries_st_3_bits_cmd_cmd_rs1; // @[ReservationStation.scala:119:23] reg [63:0] entries_st_3_bits_cmd_cmd_rs2; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:119:23] reg [31:0] entries_st_3_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:119:23] reg [1:0] entries_st_3_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:119:23] reg [1:0] entries_st_3_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_cmd_cmd_status_v; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:119:23] reg [22:0] entries_st_3_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:119:23] reg [1:0] entries_st_3_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:119:23] reg [1:0] entries_st_3_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:119:23] reg [7:0] entries_st_3_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:119:23] reg [1:0] entries_st_3_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:119:23] reg [1:0] entries_st_3_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:119:23] reg [1:0] entries_st_3_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:119:23] reg [1:0] entries_st_3_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_cmd_rob_id_valid; // @[ReservationStation.scala:119:23] reg [5:0] entries_st_3_bits_cmd_rob_id_bits; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_deps_ld_0; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_deps_ld_1; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_deps_ld_2; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_deps_ld_3; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_deps_ld_4; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_deps_ld_5; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_deps_ld_6; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_deps_ld_7; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_deps_ex_0; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_deps_ex_1; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_deps_ex_2; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_deps_ex_3; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_deps_ex_4; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_deps_ex_5; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_deps_ex_6; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_deps_ex_7; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_deps_ex_8; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_deps_ex_9; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_deps_ex_10; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_deps_ex_11; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_deps_ex_12; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_deps_ex_13; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_deps_ex_14; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_deps_ex_15; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_deps_st_0; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_deps_st_1; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_deps_st_2; // @[ReservationStation.scala:119:23] reg entries_st_3_bits_deps_st_3; // @[ReservationStation.scala:119:23] reg [31:0] entries_st_3_bits_allocated_at; // @[ReservationStation.scala:119:23] wire _GEN = entries_ld_0_valid | entries_ld_1_valid; // @[ReservationStation.scala:117:23, :123:52] wire _empty_ld_T; // @[ReservationStation.scala:123:52] assign _empty_ld_T = _GEN; // @[ReservationStation.scala:123:52] wire _empty_T; // @[ReservationStation.scala:130:46] assign _empty_T = _GEN; // @[ReservationStation.scala:123:52, :130:46] wire _empty_ld_T_1 = _empty_ld_T | entries_ld_2_valid; // @[ReservationStation.scala:117:23, :123:52] wire _empty_ld_T_2 = _empty_ld_T_1 | entries_ld_3_valid; // @[ReservationStation.scala:117:23, :123:52] wire _empty_ld_T_3 = _empty_ld_T_2 | entries_ld_4_valid; // @[ReservationStation.scala:117:23, :123:52] wire _empty_ld_T_4 = _empty_ld_T_3 | entries_ld_5_valid; // @[ReservationStation.scala:117:23, :123:52] wire _empty_ld_T_5 = _empty_ld_T_4 | entries_ld_6_valid; // @[ReservationStation.scala:117:23, :123:52] wire _empty_ld_T_6 = _empty_ld_T_5 | entries_ld_7_valid; // @[ReservationStation.scala:117:23, :123:52] wire empty_ld = ~_empty_ld_T_6; // @[ReservationStation.scala:123:{18,52}] wire _empty_ex_T = entries_ex_0_valid | entries_ex_1_valid; // @[ReservationStation.scala:118:23, :124:52] wire _empty_ex_T_1 = _empty_ex_T | entries_ex_2_valid; // @[ReservationStation.scala:118:23, :124:52] wire _empty_ex_T_2 = _empty_ex_T_1 | entries_ex_3_valid; // @[ReservationStation.scala:118:23, :124:52] wire _empty_ex_T_3 = _empty_ex_T_2 | entries_ex_4_valid; // @[ReservationStation.scala:118:23, :124:52] wire _empty_ex_T_4 = _empty_ex_T_3 | entries_ex_5_valid; // @[ReservationStation.scala:118:23, :124:52] wire _empty_ex_T_5 = _empty_ex_T_4 | entries_ex_6_valid; // @[ReservationStation.scala:118:23, :124:52] wire _empty_ex_T_6 = _empty_ex_T_5 | entries_ex_7_valid; // @[ReservationStation.scala:118:23, :124:52] wire _empty_ex_T_7 = _empty_ex_T_6 | entries_ex_8_valid; // @[ReservationStation.scala:118:23, :124:52] wire _empty_ex_T_8 = _empty_ex_T_7 | entries_ex_9_valid; // @[ReservationStation.scala:118:23, :124:52] wire _empty_ex_T_9 = _empty_ex_T_8 | entries_ex_10_valid; // @[ReservationStation.scala:118:23, :124:52] wire _empty_ex_T_10 = _empty_ex_T_9 | entries_ex_11_valid; // @[ReservationStation.scala:118:23, :124:52] wire _empty_ex_T_11 = _empty_ex_T_10 | entries_ex_12_valid; // @[ReservationStation.scala:118:23, :124:52] wire _empty_ex_T_12 = _empty_ex_T_11 | entries_ex_13_valid; // @[ReservationStation.scala:118:23, :124:52] wire _empty_ex_T_13 = _empty_ex_T_12 | entries_ex_14_valid; // @[ReservationStation.scala:118:23, :124:52] wire _empty_ex_T_14 = _empty_ex_T_13 | entries_ex_15_valid; // @[ReservationStation.scala:118:23, :124:52] wire empty_ex = ~_empty_ex_T_14; // @[ReservationStation.scala:124:{18,52}] wire _empty_st_T = entries_st_0_valid | entries_st_1_valid; // @[ReservationStation.scala:119:23, :125:52] wire _empty_st_T_1 = _empty_st_T | entries_st_2_valid; // @[ReservationStation.scala:119:23, :125:52] wire _empty_st_T_2 = _empty_st_T_1 | entries_st_3_valid; // @[ReservationStation.scala:119:23, :125:52] wire empty_st = ~_empty_st_T_2; // @[ReservationStation.scala:125:{18,52}] wire _GEN_0 = entries_ld_0_valid & entries_ld_1_valid; // @[ReservationStation.scala:117:23, :126:50] wire _full_ld_T; // @[ReservationStation.scala:126:50] assign _full_ld_T = _GEN_0; // @[ReservationStation.scala:126:50] wire _full_T; // @[ReservationStation.scala:131:44] assign _full_T = _GEN_0; // @[ReservationStation.scala:126:50, :131:44] wire _full_ld_T_1 = _full_ld_T & entries_ld_2_valid; // @[ReservationStation.scala:117:23, :126:50] wire _full_ld_T_2 = _full_ld_T_1 & entries_ld_3_valid; // @[ReservationStation.scala:117:23, :126:50] wire _full_ld_T_3 = _full_ld_T_2 & entries_ld_4_valid; // @[ReservationStation.scala:117:23, :126:50] wire _full_ld_T_4 = _full_ld_T_3 & entries_ld_5_valid; // @[ReservationStation.scala:117:23, :126:50] wire _full_ld_T_5 = _full_ld_T_4 & entries_ld_6_valid; // @[ReservationStation.scala:117:23, :126:50] wire full_ld = _full_ld_T_5 & entries_ld_7_valid; // @[ReservationStation.scala:117:23, :126:50] wire _full_ex_T = entries_ex_0_valid & entries_ex_1_valid; // @[ReservationStation.scala:118:23, :127:50] wire _full_ex_T_1 = _full_ex_T & entries_ex_2_valid; // @[ReservationStation.scala:118:23, :127:50] wire _full_ex_T_2 = _full_ex_T_1 & entries_ex_3_valid; // @[ReservationStation.scala:118:23, :127:50] wire _full_ex_T_3 = _full_ex_T_2 & entries_ex_4_valid; // @[ReservationStation.scala:118:23, :127:50] wire _full_ex_T_4 = _full_ex_T_3 & entries_ex_5_valid; // @[ReservationStation.scala:118:23, :127:50] wire _full_ex_T_5 = _full_ex_T_4 & entries_ex_6_valid; // @[ReservationStation.scala:118:23, :127:50] wire _full_ex_T_6 = _full_ex_T_5 & entries_ex_7_valid; // @[ReservationStation.scala:118:23, :127:50] wire _full_ex_T_7 = _full_ex_T_6 & entries_ex_8_valid; // @[ReservationStation.scala:118:23, :127:50] wire _full_ex_T_8 = _full_ex_T_7 & entries_ex_9_valid; // @[ReservationStation.scala:118:23, :127:50] wire _full_ex_T_9 = _full_ex_T_8 & entries_ex_10_valid; // @[ReservationStation.scala:118:23, :127:50] wire _full_ex_T_10 = _full_ex_T_9 & entries_ex_11_valid; // @[ReservationStation.scala:118:23, :127:50] wire _full_ex_T_11 = _full_ex_T_10 & entries_ex_12_valid; // @[ReservationStation.scala:118:23, :127:50] wire _full_ex_T_12 = _full_ex_T_11 & entries_ex_13_valid; // @[ReservationStation.scala:118:23, :127:50] wire _full_ex_T_13 = _full_ex_T_12 & entries_ex_14_valid; // @[ReservationStation.scala:118:23, :127:50] wire full_ex = _full_ex_T_13 & entries_ex_15_valid; // @[ReservationStation.scala:118:23, :127:50] wire _full_st_T = entries_st_0_valid & entries_st_1_valid; // @[ReservationStation.scala:119:23, :128:50] wire _full_st_T_1 = _full_st_T & entries_st_2_valid; // @[ReservationStation.scala:119:23, :128:50] wire full_st = _full_st_T_1 & entries_st_3_valid; // @[ReservationStation.scala:119:23, :128:50] wire _empty_T_1 = _empty_T | entries_ld_2_valid; // @[ReservationStation.scala:117:23, :130:46] wire _empty_T_2 = _empty_T_1 | entries_ld_3_valid; // @[ReservationStation.scala:117:23, :130:46] wire _empty_T_3 = _empty_T_2 | entries_ld_4_valid; // @[ReservationStation.scala:117:23, :130:46] wire _empty_T_4 = _empty_T_3 | entries_ld_5_valid; // @[ReservationStation.scala:117:23, :130:46] wire _empty_T_5 = _empty_T_4 | entries_ld_6_valid; // @[ReservationStation.scala:117:23, :130:46] wire _empty_T_6 = _empty_T_5 | entries_ld_7_valid; // @[ReservationStation.scala:117:23, :130:46] wire _empty_T_7 = _empty_T_6 | entries_ex_0_valid; // @[ReservationStation.scala:118:23, :130:46] wire _empty_T_8 = _empty_T_7 | entries_ex_1_valid; // @[ReservationStation.scala:118:23, :130:46] wire _empty_T_9 = _empty_T_8 | entries_ex_2_valid; // @[ReservationStation.scala:118:23, :130:46] wire _empty_T_10 = _empty_T_9 | entries_ex_3_valid; // @[ReservationStation.scala:118:23, :130:46] wire _empty_T_11 = _empty_T_10 | entries_ex_4_valid; // @[ReservationStation.scala:118:23, :130:46] wire _empty_T_12 = _empty_T_11 | entries_ex_5_valid; // @[ReservationStation.scala:118:23, :130:46] wire _empty_T_13 = _empty_T_12 | entries_ex_6_valid; // @[ReservationStation.scala:118:23, :130:46] wire _empty_T_14 = _empty_T_13 | entries_ex_7_valid; // @[ReservationStation.scala:118:23, :130:46] wire _empty_T_15 = _empty_T_14 | entries_ex_8_valid; // @[ReservationStation.scala:118:23, :130:46] wire _empty_T_16 = _empty_T_15 | entries_ex_9_valid; // @[ReservationStation.scala:118:23, :130:46] wire _empty_T_17 = _empty_T_16 | entries_ex_10_valid; // @[ReservationStation.scala:118:23, :130:46] wire _empty_T_18 = _empty_T_17 | entries_ex_11_valid; // @[ReservationStation.scala:118:23, :130:46] wire _empty_T_19 = _empty_T_18 | entries_ex_12_valid; // @[ReservationStation.scala:118:23, :130:46] wire _empty_T_20 = _empty_T_19 | entries_ex_13_valid; // @[ReservationStation.scala:118:23, :130:46] wire _empty_T_21 = _empty_T_20 | entries_ex_14_valid; // @[ReservationStation.scala:118:23, :130:46] wire _empty_T_22 = _empty_T_21 | entries_ex_15_valid; // @[ReservationStation.scala:118:23, :130:46] wire _empty_T_23 = _empty_T_22 | entries_st_0_valid; // @[ReservationStation.scala:119:23, :130:46] wire _empty_T_24 = _empty_T_23 | entries_st_1_valid; // @[ReservationStation.scala:119:23, :130:46] wire _empty_T_25 = _empty_T_24 | entries_st_2_valid; // @[ReservationStation.scala:119:23, :130:46] wire _empty_T_26 = _empty_T_25 | entries_st_3_valid; // @[ReservationStation.scala:119:23, :130:46] wire empty = ~_empty_T_26; // @[ReservationStation.scala:130:{15,46}] wire _full_T_1 = _full_T & entries_ld_2_valid; // @[ReservationStation.scala:117:23, :131:44] wire _full_T_2 = _full_T_1 & entries_ld_3_valid; // @[ReservationStation.scala:117:23, :131:44] wire _full_T_3 = _full_T_2 & entries_ld_4_valid; // @[ReservationStation.scala:117:23, :131:44] wire _full_T_4 = _full_T_3 & entries_ld_5_valid; // @[ReservationStation.scala:117:23, :131:44] wire _full_T_5 = _full_T_4 & entries_ld_6_valid; // @[ReservationStation.scala:117:23, :131:44] wire _full_T_6 = _full_T_5 & entries_ld_7_valid; // @[ReservationStation.scala:117:23, :131:44] wire _full_T_7 = _full_T_6 & entries_ex_0_valid; // @[ReservationStation.scala:118:23, :131:44] wire _full_T_8 = _full_T_7 & entries_ex_1_valid; // @[ReservationStation.scala:118:23, :131:44] wire _full_T_9 = _full_T_8 & entries_ex_2_valid; // @[ReservationStation.scala:118:23, :131:44] wire _full_T_10 = _full_T_9 & entries_ex_3_valid; // @[ReservationStation.scala:118:23, :131:44] wire _full_T_11 = _full_T_10 & entries_ex_4_valid; // @[ReservationStation.scala:118:23, :131:44] wire _full_T_12 = _full_T_11 & entries_ex_5_valid; // @[ReservationStation.scala:118:23, :131:44] wire _full_T_13 = _full_T_12 & entries_ex_6_valid; // @[ReservationStation.scala:118:23, :131:44] wire _full_T_14 = _full_T_13 & entries_ex_7_valid; // @[ReservationStation.scala:118:23, :131:44] wire _full_T_15 = _full_T_14 & entries_ex_8_valid; // @[ReservationStation.scala:118:23, :131:44] wire _full_T_16 = _full_T_15 & entries_ex_9_valid; // @[ReservationStation.scala:118:23, :131:44] wire _full_T_17 = _full_T_16 & entries_ex_10_valid; // @[ReservationStation.scala:118:23, :131:44] wire _full_T_18 = _full_T_17 & entries_ex_11_valid; // @[ReservationStation.scala:118:23, :131:44] wire _full_T_19 = _full_T_18 & entries_ex_12_valid; // @[ReservationStation.scala:118:23, :131:44] wire _full_T_20 = _full_T_19 & entries_ex_13_valid; // @[ReservationStation.scala:118:23, :131:44] wire _full_T_21 = _full_T_20 & entries_ex_14_valid; // @[ReservationStation.scala:118:23, :131:44] wire _full_T_22 = _full_T_21 & entries_ex_15_valid; // @[ReservationStation.scala:118:23, :131:44] wire _full_T_23 = _full_T_22 & entries_st_0_valid; // @[ReservationStation.scala:119:23, :131:44] wire _full_T_24 = _full_T_23 & entries_st_1_valid; // @[ReservationStation.scala:119:23, :131:44] wire _full_T_25 = _full_T_24 & entries_st_2_valid; // @[ReservationStation.scala:119:23, :131:44] wire full = _full_T_25 & entries_st_3_valid; // @[ReservationStation.scala:119:23, :131:44] wire [1:0] _GEN_1 = {1'h0, entries_ld_1_valid}; // @[ReservationStation.scala:117:23, :133:29] wire [1:0] _GEN_2 = {1'h0, entries_ld_2_valid}; // @[ReservationStation.scala:117:23, :133:29] wire [1:0] _utilization_T = _GEN_1 + _GEN_2; // @[ReservationStation.scala:133:29] wire [1:0] _utilization_T_1 = _utilization_T; // @[ReservationStation.scala:133:29] wire [2:0] _utilization_T_2 = {2'h0, entries_ld_0_valid} + {1'h0, _utilization_T_1}; // @[ReservationStation.scala:117:23, :133:29] wire [1:0] _utilization_T_3 = _utilization_T_2[1:0]; // @[ReservationStation.scala:133:29] wire [1:0] _GEN_3 = {1'h0, entries_ld_3_valid}; // @[ReservationStation.scala:117:23, :133:29] wire [1:0] _GEN_4 = {1'h0, entries_ld_4_valid}; // @[ReservationStation.scala:117:23, :133:29] wire [1:0] _utilization_T_4 = _GEN_3 + _GEN_4; // @[ReservationStation.scala:133:29] wire [1:0] _utilization_T_5 = _utilization_T_4; // @[ReservationStation.scala:133:29] wire [1:0] _GEN_5 = {1'h0, entries_ld_5_valid}; // @[ReservationStation.scala:117:23, :133:29] wire [1:0] _GEN_6 = {1'h0, entries_ld_6_valid}; // @[ReservationStation.scala:117:23, :133:29] wire [1:0] _utilization_T_6 = _GEN_5 + _GEN_6; // @[ReservationStation.scala:133:29] wire [1:0] _utilization_T_7 = _utilization_T_6; // @[ReservationStation.scala:133:29] wire [2:0] _utilization_T_8 = {1'h0, _utilization_T_5} + {1'h0, _utilization_T_7}; // @[ReservationStation.scala:133:29] wire [2:0] _utilization_T_9 = _utilization_T_8; // @[ReservationStation.scala:133:29] wire [3:0] _utilization_T_10 = {2'h0, _utilization_T_3} + {1'h0, _utilization_T_9}; // @[ReservationStation.scala:133:29] wire [2:0] _utilization_T_11 = _utilization_T_10[2:0]; // @[ReservationStation.scala:133:29] wire [1:0] _GEN_7 = {1'h0, entries_ex_0_valid} + {1'h0, entries_ex_1_valid}; // @[ReservationStation.scala:118:23, :133:29] wire [1:0] _utilization_T_12; // @[ReservationStation.scala:133:29] assign _utilization_T_12 = _GEN_7; // @[ReservationStation.scala:133:29] wire [1:0] _utilization_ex_q_T; // @[ReservationStation.scala:500:34] assign _utilization_ex_q_T = _GEN_7; // @[ReservationStation.scala:133:29, :500:34] wire [1:0] _utilization_T_13 = _utilization_T_12; // @[ReservationStation.scala:133:29] wire [2:0] _utilization_T_14 = {2'h0, entries_ld_7_valid} + {1'h0, _utilization_T_13}; // @[ReservationStation.scala:117:23, :133:29] wire [1:0] _utilization_T_15 = _utilization_T_14[1:0]; // @[ReservationStation.scala:133:29] wire [1:0] _GEN_8 = {1'h0, entries_ex_2_valid} + {1'h0, entries_ex_3_valid}; // @[ReservationStation.scala:118:23, :133:29] wire [1:0] _utilization_T_16; // @[ReservationStation.scala:133:29] assign _utilization_T_16 = _GEN_8; // @[ReservationStation.scala:133:29] wire [1:0] _utilization_ex_q_T_2; // @[ReservationStation.scala:500:34] assign _utilization_ex_q_T_2 = _GEN_8; // @[ReservationStation.scala:133:29, :500:34] wire [1:0] _utilization_T_17 = _utilization_T_16; // @[ReservationStation.scala:133:29] wire [1:0] _GEN_9 = {1'h0, entries_ex_4_valid} + {1'h0, entries_ex_5_valid}; // @[ReservationStation.scala:118:23, :133:29] wire [1:0] _utilization_T_18; // @[ReservationStation.scala:133:29] assign _utilization_T_18 = _GEN_9; // @[ReservationStation.scala:133:29] wire [1:0] _utilization_ex_q_T_6; // @[ReservationStation.scala:500:34] assign _utilization_ex_q_T_6 = _GEN_9; // @[ReservationStation.scala:133:29, :500:34] wire [1:0] _utilization_T_19 = _utilization_T_18; // @[ReservationStation.scala:133:29] wire [2:0] _utilization_T_20 = {1'h0, _utilization_T_17} + {1'h0, _utilization_T_19}; // @[ReservationStation.scala:133:29] wire [2:0] _utilization_T_21 = _utilization_T_20; // @[ReservationStation.scala:133:29] wire [3:0] _utilization_T_22 = {2'h0, _utilization_T_15} + {1'h0, _utilization_T_21}; // @[ReservationStation.scala:133:29] wire [2:0] _utilization_T_23 = _utilization_T_22[2:0]; // @[ReservationStation.scala:133:29] wire [3:0] _utilization_T_24 = {1'h0, _utilization_T_11} + {1'h0, _utilization_T_23}; // @[ReservationStation.scala:133:29] wire [3:0] _utilization_T_25 = _utilization_T_24; // @[ReservationStation.scala:133:29] wire [1:0] _GEN_10 = {1'h0, entries_ex_7_valid}; // @[ReservationStation.scala:118:23, :133:29] wire [1:0] _GEN_11 = {1'h0, entries_ex_8_valid}; // @[ReservationStation.scala:118:23, :133:29] wire [1:0] _utilization_T_26 = _GEN_10 + _GEN_11; // @[ReservationStation.scala:133:29] wire [1:0] _utilization_T_27 = _utilization_T_26; // @[ReservationStation.scala:133:29] wire [2:0] _utilization_T_28 = {2'h0, entries_ex_6_valid} + {1'h0, _utilization_T_27}; // @[ReservationStation.scala:118:23, :133:29] wire [1:0] _utilization_T_29 = _utilization_T_28[1:0]; // @[ReservationStation.scala:133:29] wire [1:0] _GEN_12 = {1'h0, entries_ex_9_valid}; // @[ReservationStation.scala:118:23, :133:29] wire [1:0] _GEN_13 = {1'h0, entries_ex_10_valid}; // @[ReservationStation.scala:118:23, :133:29] wire [1:0] _utilization_T_30 = _GEN_12 + _GEN_13; // @[ReservationStation.scala:133:29] wire [1:0] _utilization_T_31 = _utilization_T_30; // @[ReservationStation.scala:133:29] wire [1:0] _GEN_14 = {1'h0, entries_ex_11_valid}; // @[ReservationStation.scala:118:23, :133:29] wire [1:0] _GEN_15 = {1'h0, entries_ex_12_valid}; // @[ReservationStation.scala:118:23, :133:29] wire [1:0] _utilization_T_32 = _GEN_14 + _GEN_15; // @[ReservationStation.scala:133:29] wire [1:0] _utilization_T_33 = _utilization_T_32; // @[ReservationStation.scala:133:29] wire [2:0] _utilization_T_34 = {1'h0, _utilization_T_31} + {1'h0, _utilization_T_33}; // @[ReservationStation.scala:133:29] wire [2:0] _utilization_T_35 = _utilization_T_34; // @[ReservationStation.scala:133:29] wire [3:0] _utilization_T_36 = {2'h0, _utilization_T_29} + {1'h0, _utilization_T_35}; // @[ReservationStation.scala:133:29] wire [2:0] _utilization_T_37 = _utilization_T_36[2:0]; // @[ReservationStation.scala:133:29] wire [1:0] _GEN_16 = {1'h0, entries_ex_14_valid} + {1'h0, entries_ex_15_valid}; // @[ReservationStation.scala:118:23, :133:29] wire [1:0] _utilization_T_38; // @[ReservationStation.scala:133:29] assign _utilization_T_38 = _GEN_16; // @[ReservationStation.scala:133:29] wire [1:0] _utilization_ex_q_T_22; // @[ReservationStation.scala:500:34] assign _utilization_ex_q_T_22 = _GEN_16; // @[ReservationStation.scala:133:29, :500:34] wire [1:0] _utilization_T_39 = _utilization_T_38; // @[ReservationStation.scala:133:29] wire [2:0] _utilization_T_40 = {2'h0, entries_ex_13_valid} + {1'h0, _utilization_T_39}; // @[ReservationStation.scala:118:23, :133:29] wire [1:0] _utilization_T_41 = _utilization_T_40[1:0]; // @[ReservationStation.scala:133:29] wire [1:0] _GEN_17 = {1'h0, entries_st_0_valid} + {1'h0, entries_st_1_valid}; // @[ReservationStation.scala:119:23, :133:29] wire [1:0] _utilization_T_42; // @[ReservationStation.scala:133:29] assign _utilization_T_42 = _GEN_17; // @[ReservationStation.scala:133:29] wire [1:0] _utilization_st_q_T; // @[ReservationStation.scala:499:34] assign _utilization_st_q_T = _GEN_17; // @[ReservationStation.scala:133:29, :499:34] wire [1:0] _utilization_T_43 = _utilization_T_42; // @[ReservationStation.scala:133:29] wire [1:0] _GEN_18 = {1'h0, entries_st_2_valid} + {1'h0, entries_st_3_valid}; // @[ReservationStation.scala:119:23, :133:29] wire [1:0] _utilization_T_44; // @[ReservationStation.scala:133:29] assign _utilization_T_44 = _GEN_18; // @[ReservationStation.scala:133:29] wire [1:0] _utilization_st_q_T_2; // @[ReservationStation.scala:499:34] assign _utilization_st_q_T_2 = _GEN_18; // @[ReservationStation.scala:133:29, :499:34] wire [1:0] _utilization_T_45 = _utilization_T_44; // @[ReservationStation.scala:133:29] wire [2:0] _utilization_T_46 = {1'h0, _utilization_T_43} + {1'h0, _utilization_T_45}; // @[ReservationStation.scala:133:29] wire [2:0] _utilization_T_47 = _utilization_T_46; // @[ReservationStation.scala:133:29] wire [3:0] _utilization_T_48 = {2'h0, _utilization_T_41} + {1'h0, _utilization_T_47}; // @[ReservationStation.scala:133:29] wire [2:0] _utilization_T_49 = _utilization_T_48[2:0]; // @[ReservationStation.scala:133:29] wire [3:0] _utilization_T_50 = {1'h0, _utilization_T_37} + {1'h0, _utilization_T_49}; // @[ReservationStation.scala:133:29] wire [3:0] _utilization_T_51 = _utilization_T_50; // @[ReservationStation.scala:133:29] wire [4:0] _utilization_T_52 = {1'h0, _utilization_T_25} + {1'h0, _utilization_T_51}; // @[ReservationStation.scala:133:29] wire [4:0] utilization = _utilization_T_52; // @[ReservationStation.scala:133:29] reg solitary_preload; // @[ReservationStation.scala:134:33] wire _io_busy_T = ~empty; // @[ReservationStation.scala:130:15, :135:14] wire _io_busy_T_1 = utilization == 5'h1; // @[ReservationStation.scala:133:29, :135:38] wire _io_busy_T_2 = _io_busy_T_1 & solitary_preload; // @[ReservationStation.scala:134:33, :135:{38,46}] wire _io_busy_T_3 = ~_io_busy_T_2; // @[ReservationStation.scala:135:{24,46}] assign _io_busy_T_4 = _io_busy_T & _io_busy_T_3; // @[ReservationStation.scala:135:{14,21,24}] assign io_busy_0 = _io_busy_T_4; // @[ReservationStation.scala:26:7, :135:21] wire conv_ld_issue_completed; // @[ReservationStation.scala:138:41] wire conv_st_issue_completed; // @[ReservationStation.scala:139:41] wire conv_ex_issue_completed; // @[ReservationStation.scala:140:41] wire conv_ld_completed; // @[ReservationStation.scala:142:35] wire conv_st_completed; // @[ReservationStation.scala:143:35] wire conv_ex_completed; // @[ReservationStation.scala:144:35] wire matmul_ld_issue_completed; // @[ReservationStation.scala:146:43] wire matmul_st_issue_completed; // @[ReservationStation.scala:147:43] wire matmul_ex_issue_completed; // @[ReservationStation.scala:148:43] wire matmul_ld_completed; // @[ReservationStation.scala:150:37] wire matmul_st_completed; // @[ReservationStation.scala:151:37] wire matmul_ex_completed; // @[ReservationStation.scala:152:37] assign _io_conv_ld_completed_T = {1'h0, conv_ld_issue_completed} + {1'h0, conv_ld_completed}; // @[ReservationStation.scala:138:41, :142:35, :154:51] assign io_conv_ld_completed_0 = _io_conv_ld_completed_T; // @[ReservationStation.scala:26:7, :154:51] assign _io_conv_st_completed_T = {1'h0, conv_st_issue_completed} + {1'h0, conv_st_completed}; // @[ReservationStation.scala:139:41, :143:35, :155:51] assign io_conv_st_completed_0 = _io_conv_st_completed_T; // @[ReservationStation.scala:26:7, :155:51] assign _io_conv_ex_completed_T = {1'h0, conv_ex_issue_completed} + {1'h0, conv_ex_completed}; // @[ReservationStation.scala:140:41, :144:35, :156:51] assign io_conv_ex_completed_0 = _io_conv_ex_completed_T; // @[ReservationStation.scala:26:7, :156:51] assign _io_matmul_ld_completed_T = {1'h0, matmul_ld_issue_completed} + {1'h0, matmul_ld_completed}; // @[ReservationStation.scala:146:43, :150:37, :158:55] assign io_matmul_ld_completed_0 = _io_matmul_ld_completed_T; // @[ReservationStation.scala:26:7, :158:55] assign _io_matmul_st_completed_T = {1'h0, matmul_st_issue_completed} + {1'h0, matmul_st_completed}; // @[ReservationStation.scala:147:43, :151:37, :159:55] assign io_matmul_st_completed_0 = _io_matmul_st_completed_T; // @[ReservationStation.scala:26:7, :159:55] assign _io_matmul_ex_completed_T = {1'h0, matmul_ex_issue_completed} + {1'h0, matmul_ex_completed}; // @[ReservationStation.scala:148:43, :152:37, :160:55] assign io_matmul_ex_completed_0 = _io_matmul_ex_completed_T; // @[ReservationStation.scala:26:7, :160:55] reg [13:0] a_stride; // @[ReservationStation.scala:163:21] reg [13:0] c_stride; // @[ReservationStation.scala:164:21] reg a_transpose; // @[ReservationStation.scala:165:24] reg [13:0] ld_block_strides_0; // @[ReservationStation.scala:166:29] reg [13:0] ld_block_strides_1; // @[ReservationStation.scala:166:29] reg [13:0] ld_block_strides_2; // @[ReservationStation.scala:166:29] reg pooling_is_enabled; // @[ReservationStation.scala:168:31] reg [2:0] ld_pixel_repeats_0; // @[ReservationStation.scala:169:29] reg [2:0] ld_pixel_repeats_1; // @[ReservationStation.scala:169:29] reg [2:0] ld_pixel_repeats_2; // @[ReservationStation.scala:169:29] wire [1:0] _new_entry_q_WIRE; // @[Mux.scala:30:73] wire _new_entry_is_config_T; // @[ReservationStation.scala:194:34] wire dst_valid; // @[ReservationStation.scala:202:19] wire _new_entry_complete_on_issue_T_1; // @[ReservationStation.scala:343:56] wire new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:171:23] wire new_entry_opa_bits_start_accumulate; // @[ReservationStation.scala:171:23] wire new_entry_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:171:23] wire [2:0] new_entry_opa_bits_start_norm_cmd; // @[ReservationStation.scala:171:23] wire [10:0] new_entry_opa_bits_start_garbage; // @[ReservationStation.scala:171:23] wire new_entry_opa_bits_start_garbage_bit; // @[ReservationStation.scala:171:23] wire [13:0] new_entry_opa_bits_start_data; // @[ReservationStation.scala:171:23] wire new_entry_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:171:23] wire new_entry_opa_bits_end_accumulate; // @[ReservationStation.scala:171:23] wire new_entry_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:171:23] wire [2:0] new_entry_opa_bits_end_norm_cmd; // @[ReservationStation.scala:171:23] wire [10:0] new_entry_opa_bits_end_garbage; // @[ReservationStation.scala:171:23] wire new_entry_opa_bits_end_garbage_bit; // @[ReservationStation.scala:171:23] wire [13:0] new_entry_opa_bits_end_data; // @[ReservationStation.scala:171:23] wire new_entry_opa_bits_wraps_around; // @[ReservationStation.scala:171:23] wire new_entry_opa_valid; // @[ReservationStation.scala:171:23] wire new_entry_opb_bits_start_is_acc_addr; // @[ReservationStation.scala:171:23] wire new_entry_opb_bits_start_accumulate; // @[ReservationStation.scala:171:23] wire new_entry_opb_bits_start_read_full_acc_row; // @[ReservationStation.scala:171:23] wire [2:0] new_entry_opb_bits_start_norm_cmd; // @[ReservationStation.scala:171:23] wire [10:0] new_entry_opb_bits_start_garbage; // @[ReservationStation.scala:171:23] wire new_entry_opb_bits_start_garbage_bit; // @[ReservationStation.scala:171:23] wire [13:0] new_entry_opb_bits_start_data; // @[ReservationStation.scala:171:23] wire new_entry_opb_bits_end_is_acc_addr; // @[ReservationStation.scala:171:23] wire new_entry_opb_bits_end_accumulate; // @[ReservationStation.scala:171:23] wire new_entry_opb_bits_end_read_full_acc_row; // @[ReservationStation.scala:171:23] wire [2:0] new_entry_opb_bits_end_norm_cmd; // @[ReservationStation.scala:171:23] wire [10:0] new_entry_opb_bits_end_garbage; // @[ReservationStation.scala:171:23] wire new_entry_opb_bits_end_garbage_bit; // @[ReservationStation.scala:171:23] wire [13:0] new_entry_opb_bits_end_data; // @[ReservationStation.scala:171:23] wire new_entry_opb_bits_wraps_around; // @[ReservationStation.scala:171:23] wire new_entry_opb_valid; // @[ReservationStation.scala:171:23] wire new_entry_deps_ld_0; // @[ReservationStation.scala:171:23] wire new_entry_deps_ld_1; // @[ReservationStation.scala:171:23] wire new_entry_deps_ld_2; // @[ReservationStation.scala:171:23] wire new_entry_deps_ld_3; // @[ReservationStation.scala:171:23] wire new_entry_deps_ld_4; // @[ReservationStation.scala:171:23] wire new_entry_deps_ld_5; // @[ReservationStation.scala:171:23] wire new_entry_deps_ld_6; // @[ReservationStation.scala:171:23] wire new_entry_deps_ld_7; // @[ReservationStation.scala:171:23] wire new_entry_deps_ex_0; // @[ReservationStation.scala:171:23] wire new_entry_deps_ex_1; // @[ReservationStation.scala:171:23] wire new_entry_deps_ex_2; // @[ReservationStation.scala:171:23] wire new_entry_deps_ex_3; // @[ReservationStation.scala:171:23] wire new_entry_deps_ex_4; // @[ReservationStation.scala:171:23] wire new_entry_deps_ex_5; // @[ReservationStation.scala:171:23] wire new_entry_deps_ex_6; // @[ReservationStation.scala:171:23] wire new_entry_deps_ex_7; // @[ReservationStation.scala:171:23] wire new_entry_deps_ex_8; // @[ReservationStation.scala:171:23] wire new_entry_deps_ex_9; // @[ReservationStation.scala:171:23] wire new_entry_deps_ex_10; // @[ReservationStation.scala:171:23] wire new_entry_deps_ex_11; // @[ReservationStation.scala:171:23] wire new_entry_deps_ex_12; // @[ReservationStation.scala:171:23] wire new_entry_deps_ex_13; // @[ReservationStation.scala:171:23] wire new_entry_deps_ex_14; // @[ReservationStation.scala:171:23] wire new_entry_deps_ex_15; // @[ReservationStation.scala:171:23] wire new_entry_deps_st_0; // @[ReservationStation.scala:171:23] wire new_entry_deps_st_1; // @[ReservationStation.scala:171:23] wire new_entry_deps_st_2; // @[ReservationStation.scala:171:23] wire new_entry_deps_st_3; // @[ReservationStation.scala:171:23] wire [1:0] new_entry_q; // @[ReservationStation.scala:171:23] wire new_entry_is_config; // @[ReservationStation.scala:171:23] wire new_entry_opa_is_dst; // @[ReservationStation.scala:171:23] wire new_entry_complete_on_issue; // @[ReservationStation.scala:171:23] wire new_allocs_oh_ld_0; // @[ReservationStation.scala:174:30] wire new_allocs_oh_ld_1; // @[ReservationStation.scala:174:30] wire new_allocs_oh_ld_2; // @[ReservationStation.scala:174:30] wire new_allocs_oh_ld_3; // @[ReservationStation.scala:174:30] wire new_allocs_oh_ld_4; // @[ReservationStation.scala:174:30] wire new_allocs_oh_ld_5; // @[ReservationStation.scala:174:30] wire new_allocs_oh_ld_6; // @[ReservationStation.scala:174:30] wire new_allocs_oh_ld_7; // @[ReservationStation.scala:174:30] wire new_allocs_oh_ex_0; // @[ReservationStation.scala:175:30] wire new_allocs_oh_ex_1; // @[ReservationStation.scala:175:30] wire new_allocs_oh_ex_2; // @[ReservationStation.scala:175:30] wire new_allocs_oh_ex_3; // @[ReservationStation.scala:175:30] wire new_allocs_oh_ex_4; // @[ReservationStation.scala:175:30] wire new_allocs_oh_ex_5; // @[ReservationStation.scala:175:30] wire new_allocs_oh_ex_6; // @[ReservationStation.scala:175:30] wire new_allocs_oh_ex_7; // @[ReservationStation.scala:175:30] wire new_allocs_oh_ex_8; // @[ReservationStation.scala:175:30] wire new_allocs_oh_ex_9; // @[ReservationStation.scala:175:30] wire new_allocs_oh_ex_10; // @[ReservationStation.scala:175:30] wire new_allocs_oh_ex_11; // @[ReservationStation.scala:175:30] wire new_allocs_oh_ex_12; // @[ReservationStation.scala:175:30] wire new_allocs_oh_ex_13; // @[ReservationStation.scala:175:30] wire new_allocs_oh_ex_14; // @[ReservationStation.scala:175:30] wire new_allocs_oh_ex_15; // @[ReservationStation.scala:175:30] wire new_allocs_oh_st_0; // @[ReservationStation.scala:176:30] wire new_allocs_oh_st_1; // @[ReservationStation.scala:176:30] wire new_allocs_oh_st_2; // @[ReservationStation.scala:176:30] wire new_allocs_oh_st_3; // @[ReservationStation.scala:176:30] wire _funct_is_compute_T = io_alloc_bits_cmd_inst_funct_0 == 7'h5; // @[ReservationStation.scala:26:7, :188:34] wire _funct_is_compute_T_1 = io_alloc_bits_cmd_inst_funct_0 == 7'h4; // @[ReservationStation.scala:26:7, :188:68] wire funct_is_compute = _funct_is_compute_T | _funct_is_compute_T_1; // @[ReservationStation.scala:188:{34,59,68}] wire [1:0] config_cmd_type = io_alloc_bits_cmd_rs1_0[1:0]; // @[ReservationStation.scala:26:7, :189:34] wire _GEN_19 = io_alloc_bits_cmd_inst_funct_0 == 7'h0; // @[ReservationStation.scala:26:7, :194:34] assign _new_entry_is_config_T = _GEN_19; // @[ReservationStation.scala:194:34] wire _is_load_T_5; // @[ReservationStation.scala:295:94] assign _is_load_T_5 = _GEN_19; // @[ReservationStation.scala:194:34, :295:94] wire _is_ex_T_2; // @[ReservationStation.scala:296:69] assign _is_ex_T_2 = _GEN_19; // @[ReservationStation.scala:194:34, :296:69] wire _is_store_T_1; // @[ReservationStation.scala:297:50] assign _is_store_T_1 = _GEN_19; // @[ReservationStation.scala:194:34, :297:50] wire _is_norm_T; // @[ReservationStation.scala:298:25] assign _is_norm_T = _GEN_19; // @[ReservationStation.scala:194:34, :298:25] assign new_entry_is_config = _new_entry_is_config_T; // @[ReservationStation.scala:171:23, :194:34] wire _op1_valid_T_1; // @[ReservationStation.scala:216:40] wire _op1_bits_start_WIRE_is_acc_addr; // @[ReservationStation.scala:217:39] wire _op1_bits_start_WIRE_accumulate; // @[ReservationStation.scala:217:39] wire op1_bits_end_result_is_acc_addr = op1_bits_start_is_acc_addr; // @[ReservationStation.scala:196:19] wire op1_bits_wraps_around_result_is_acc_addr = op1_bits_start_is_acc_addr; // @[ReservationStation.scala:196:19] wire op1_bits_end_result_1_is_acc_addr = op1_bits_start_is_acc_addr; // @[ReservationStation.scala:196:19] wire op1_bits_wraps_around_result_1_is_acc_addr = op1_bits_start_is_acc_addr; // @[ReservationStation.scala:196:19] wire _op1_bits_start_WIRE_read_full_acc_row; // @[ReservationStation.scala:217:39] wire op1_bits_end_result_accumulate = op1_bits_start_accumulate; // @[ReservationStation.scala:196:19] wire op1_bits_wraps_around_result_accumulate = op1_bits_start_accumulate; // @[ReservationStation.scala:196:19] wire op1_bits_end_result_1_accumulate = op1_bits_start_accumulate; // @[ReservationStation.scala:196:19] wire op1_bits_wraps_around_result_1_accumulate = op1_bits_start_accumulate; // @[ReservationStation.scala:196:19] wire [2:0] _op1_bits_start_WIRE_norm_cmd; // @[ReservationStation.scala:217:39] wire op1_bits_end_result_read_full_acc_row = op1_bits_start_read_full_acc_row; // @[ReservationStation.scala:196:19] wire op1_bits_wraps_around_result_read_full_acc_row = op1_bits_start_read_full_acc_row; // @[ReservationStation.scala:196:19] wire op1_bits_end_result_1_read_full_acc_row = op1_bits_start_read_full_acc_row; // @[ReservationStation.scala:196:19] wire op1_bits_wraps_around_result_1_read_full_acc_row = op1_bits_start_read_full_acc_row; // @[ReservationStation.scala:196:19] wire [10:0] _op1_bits_start_WIRE_garbage; // @[ReservationStation.scala:217:39] wire [2:0] op1_bits_end_result_norm_cmd = op1_bits_start_norm_cmd; // @[ReservationStation.scala:196:19] wire [2:0] op1_bits_wraps_around_result_norm_cmd = op1_bits_start_norm_cmd; // @[ReservationStation.scala:196:19] wire [2:0] op1_bits_end_result_1_norm_cmd = op1_bits_start_norm_cmd; // @[ReservationStation.scala:196:19] wire [2:0] op1_bits_wraps_around_result_1_norm_cmd = op1_bits_start_norm_cmd; // @[ReservationStation.scala:196:19] wire _op1_bits_start_WIRE_garbage_bit; // @[ReservationStation.scala:217:39] wire [10:0] op1_bits_end_result_garbage = op1_bits_start_garbage; // @[ReservationStation.scala:196:19] wire [10:0] op1_bits_wraps_around_result_garbage = op1_bits_start_garbage; // @[ReservationStation.scala:196:19] wire [10:0] op1_bits_end_result_1_garbage = op1_bits_start_garbage; // @[ReservationStation.scala:196:19] wire [10:0] op1_bits_wraps_around_result_1_garbage = op1_bits_start_garbage; // @[ReservationStation.scala:196:19] wire [13:0] _op1_bits_start_WIRE_data; // @[ReservationStation.scala:217:39] wire op1_bits_end_result_garbage_bit = op1_bits_start_garbage_bit; // @[ReservationStation.scala:196:19] wire op1_bits_wraps_around_result_garbage_bit = op1_bits_start_garbage_bit; // @[ReservationStation.scala:196:19] wire op1_bits_end_result_1_garbage_bit = op1_bits_start_garbage_bit; // @[ReservationStation.scala:196:19] wire op1_bits_wraps_around_result_1_garbage_bit = op1_bits_start_garbage_bit; // @[ReservationStation.scala:196:19] wire [13:0] op1_bits_start_data; // @[ReservationStation.scala:196:19] wire op1_bits_end_is_acc_addr; // @[ReservationStation.scala:196:19] wire op1_bits_end_accumulate; // @[ReservationStation.scala:196:19] wire op1_bits_end_read_full_acc_row; // @[ReservationStation.scala:196:19] wire [2:0] op1_bits_end_norm_cmd; // @[ReservationStation.scala:196:19] wire [10:0] op1_bits_end_garbage; // @[ReservationStation.scala:196:19] wire op1_bits_end_garbage_bit; // @[ReservationStation.scala:196:19] wire [13:0] op1_bits_end_data; // @[ReservationStation.scala:196:19] wire op1_bits_wraps_around; // @[ReservationStation.scala:196:19] wire op1_valid; // @[ReservationStation.scala:196:19] wire _op2_valid_T_1; // @[ReservationStation.scala:231:35] wire _op2_bits_start_WIRE_is_acc_addr; // @[ReservationStation.scala:232:39] wire _op2_bits_start_WIRE_accumulate; // @[ReservationStation.scala:232:39] wire op2_bits_end_result_is_acc_addr = op2_bits_start_is_acc_addr; // @[ReservationStation.scala:199:19] wire op2_bits_wraps_around_result_is_acc_addr = op2_bits_start_is_acc_addr; // @[ReservationStation.scala:199:19] wire op2_bits_end_result_1_is_acc_addr = op2_bits_start_is_acc_addr; // @[ReservationStation.scala:199:19] wire op2_bits_wraps_around_result_1_is_acc_addr = op2_bits_start_is_acc_addr; // @[ReservationStation.scala:199:19] wire _op2_bits_start_WIRE_read_full_acc_row; // @[ReservationStation.scala:232:39] wire op2_bits_end_result_accumulate = op2_bits_start_accumulate; // @[ReservationStation.scala:199:19] wire op2_bits_wraps_around_result_accumulate = op2_bits_start_accumulate; // @[ReservationStation.scala:199:19] wire op2_bits_end_result_1_accumulate = op2_bits_start_accumulate; // @[ReservationStation.scala:199:19] wire op2_bits_wraps_around_result_1_accumulate = op2_bits_start_accumulate; // @[ReservationStation.scala:199:19] wire [2:0] _op2_bits_start_WIRE_norm_cmd; // @[ReservationStation.scala:232:39] wire op2_bits_end_result_read_full_acc_row = op2_bits_start_read_full_acc_row; // @[ReservationStation.scala:199:19] wire op2_bits_wraps_around_result_read_full_acc_row = op2_bits_start_read_full_acc_row; // @[ReservationStation.scala:199:19] wire op2_bits_end_result_1_read_full_acc_row = op2_bits_start_read_full_acc_row; // @[ReservationStation.scala:199:19] wire op2_bits_wraps_around_result_1_read_full_acc_row = op2_bits_start_read_full_acc_row; // @[ReservationStation.scala:199:19] wire [10:0] _op2_bits_start_WIRE_garbage; // @[ReservationStation.scala:232:39] wire [2:0] op2_bits_end_result_norm_cmd = op2_bits_start_norm_cmd; // @[ReservationStation.scala:199:19] wire [2:0] op2_bits_wraps_around_result_norm_cmd = op2_bits_start_norm_cmd; // @[ReservationStation.scala:199:19] wire [2:0] op2_bits_end_result_1_norm_cmd = op2_bits_start_norm_cmd; // @[ReservationStation.scala:199:19] wire [2:0] op2_bits_wraps_around_result_1_norm_cmd = op2_bits_start_norm_cmd; // @[ReservationStation.scala:199:19] wire _op2_bits_start_WIRE_garbage_bit; // @[ReservationStation.scala:232:39] wire [10:0] op2_bits_end_result_garbage = op2_bits_start_garbage; // @[ReservationStation.scala:199:19] wire [10:0] op2_bits_wraps_around_result_garbage = op2_bits_start_garbage; // @[ReservationStation.scala:199:19] wire [10:0] op2_bits_end_result_1_garbage = op2_bits_start_garbage; // @[ReservationStation.scala:199:19] wire [10:0] op2_bits_wraps_around_result_1_garbage = op2_bits_start_garbage; // @[ReservationStation.scala:199:19] wire [13:0] _op2_bits_start_WIRE_data; // @[ReservationStation.scala:232:39] wire op2_bits_end_result_garbage_bit = op2_bits_start_garbage_bit; // @[ReservationStation.scala:199:19] wire op2_bits_wraps_around_result_garbage_bit = op2_bits_start_garbage_bit; // @[ReservationStation.scala:199:19] wire op2_bits_end_result_1_garbage_bit = op2_bits_start_garbage_bit; // @[ReservationStation.scala:199:19] wire op2_bits_wraps_around_result_1_garbage_bit = op2_bits_start_garbage_bit; // @[ReservationStation.scala:199:19] wire [13:0] op2_bits_start_data; // @[ReservationStation.scala:199:19] wire op2_bits_end_is_acc_addr; // @[ReservationStation.scala:199:19] wire op2_bits_end_accumulate; // @[ReservationStation.scala:199:19] wire op2_bits_end_read_full_acc_row; // @[ReservationStation.scala:199:19] wire [2:0] op2_bits_end_norm_cmd; // @[ReservationStation.scala:199:19] wire [10:0] op2_bits_end_garbage; // @[ReservationStation.scala:199:19] wire op2_bits_end_garbage_bit; // @[ReservationStation.scala:199:19] wire [13:0] op2_bits_end_data; // @[ReservationStation.scala:199:19] wire op2_bits_wraps_around; // @[ReservationStation.scala:199:19] wire op2_valid; // @[ReservationStation.scala:199:19] wire _dst_valid_T_6; // @[ReservationStation.scala:261:85] assign new_entry_opa_is_dst = dst_valid; // @[ReservationStation.scala:171:23, :202:19] wire dst_bits_end_result_is_acc_addr = dst_bits_start_is_acc_addr; // @[ReservationStation.scala:202:19] wire dst_bits_wraps_around_result_is_acc_addr = dst_bits_start_is_acc_addr; // @[ReservationStation.scala:202:19] wire dst_bits_end_result_1_is_acc_addr = dst_bits_start_is_acc_addr; // @[ReservationStation.scala:202:19] wire dst_bits_wraps_around_result_1_is_acc_addr = dst_bits_start_is_acc_addr; // @[ReservationStation.scala:202:19] wire dst_bits_end_result_accumulate = dst_bits_start_accumulate; // @[ReservationStation.scala:202:19] wire dst_bits_wraps_around_result_accumulate = dst_bits_start_accumulate; // @[ReservationStation.scala:202:19] wire dst_bits_end_result_1_accumulate = dst_bits_start_accumulate; // @[ReservationStation.scala:202:19] wire dst_bits_wraps_around_result_1_accumulate = dst_bits_start_accumulate; // @[ReservationStation.scala:202:19] wire dst_bits_end_result_read_full_acc_row = dst_bits_start_read_full_acc_row; // @[ReservationStation.scala:202:19] wire dst_bits_wraps_around_result_read_full_acc_row = dst_bits_start_read_full_acc_row; // @[ReservationStation.scala:202:19] wire dst_bits_end_result_1_read_full_acc_row = dst_bits_start_read_full_acc_row; // @[ReservationStation.scala:202:19] wire dst_bits_wraps_around_result_1_read_full_acc_row = dst_bits_start_read_full_acc_row; // @[ReservationStation.scala:202:19] wire [2:0] dst_bits_end_result_norm_cmd = dst_bits_start_norm_cmd; // @[ReservationStation.scala:202:19] wire [2:0] dst_bits_wraps_around_result_norm_cmd = dst_bits_start_norm_cmd; // @[ReservationStation.scala:202:19] wire [2:0] dst_bits_end_result_1_norm_cmd = dst_bits_start_norm_cmd; // @[ReservationStation.scala:202:19] wire [2:0] dst_bits_wraps_around_result_1_norm_cmd = dst_bits_start_norm_cmd; // @[ReservationStation.scala:202:19] wire [10:0] dst_bits_end_result_garbage = dst_bits_start_garbage; // @[ReservationStation.scala:202:19] wire [10:0] dst_bits_wraps_around_result_garbage = dst_bits_start_garbage; // @[ReservationStation.scala:202:19] wire [10:0] dst_bits_end_result_1_garbage = dst_bits_start_garbage; // @[ReservationStation.scala:202:19] wire [10:0] dst_bits_wraps_around_result_1_garbage = dst_bits_start_garbage; // @[ReservationStation.scala:202:19] wire dst_bits_end_result_garbage_bit = dst_bits_start_garbage_bit; // @[ReservationStation.scala:202:19] wire dst_bits_wraps_around_result_garbage_bit = dst_bits_start_garbage_bit; // @[ReservationStation.scala:202:19] wire dst_bits_end_result_1_garbage_bit = dst_bits_start_garbage_bit; // @[ReservationStation.scala:202:19] wire dst_bits_wraps_around_result_1_garbage_bit = dst_bits_start_garbage_bit; // @[ReservationStation.scala:202:19] wire [13:0] dst_bits_start_data; // @[ReservationStation.scala:202:19] wire dst_bits_end_is_acc_addr; // @[ReservationStation.scala:202:19] wire dst_bits_end_accumulate; // @[ReservationStation.scala:202:19] wire dst_bits_end_read_full_acc_row; // @[ReservationStation.scala:202:19] wire [2:0] dst_bits_end_norm_cmd; // @[ReservationStation.scala:202:19] wire [10:0] dst_bits_end_garbage; // @[ReservationStation.scala:202:19] wire dst_bits_end_garbage_bit; // @[ReservationStation.scala:202:19] wire [13:0] dst_bits_end_data; // @[ReservationStation.scala:202:19] wire dst_bits_wraps_around; // @[ReservationStation.scala:202:19] wire _GEN_20 = op1_valid ? op1_valid : op2_valid; // @[ReservationStation.scala:196:19, :199:19, :210:27] wire _new_entry_opb_T_valid; // @[ReservationStation.scala:210:27] assign _new_entry_opb_T_valid = _GEN_20; // @[ReservationStation.scala:210:27] wire _new_entry_opa_T_valid; // @[ReservationStation.scala:212:27] assign _new_entry_opa_T_valid = _GEN_20; // @[ReservationStation.scala:210:27, :212:27] wire _GEN_21 = op1_valid ? op1_bits_start_is_acc_addr : op2_bits_start_is_acc_addr; // @[ReservationStation.scala:196:19, :199:19, :210:27] wire _new_entry_opb_T_bits_start_is_acc_addr; // @[ReservationStation.scala:210:27] assign _new_entry_opb_T_bits_start_is_acc_addr = _GEN_21; // @[ReservationStation.scala:210:27] wire _new_entry_opa_T_bits_start_is_acc_addr; // @[ReservationStation.scala:212:27] assign _new_entry_opa_T_bits_start_is_acc_addr = _GEN_21; // @[ReservationStation.scala:210:27, :212:27] wire _GEN_22 = op1_valid ? op1_bits_start_accumulate : op2_bits_start_accumulate; // @[ReservationStation.scala:196:19, :199:19, :210:27] wire _new_entry_opb_T_bits_start_accumulate; // @[ReservationStation.scala:210:27] assign _new_entry_opb_T_bits_start_accumulate = _GEN_22; // @[ReservationStation.scala:210:27] wire _new_entry_opa_T_bits_start_accumulate; // @[ReservationStation.scala:212:27] assign _new_entry_opa_T_bits_start_accumulate = _GEN_22; // @[ReservationStation.scala:210:27, :212:27] wire _GEN_23 = op1_valid ? op1_bits_start_read_full_acc_row : op2_bits_start_read_full_acc_row; // @[ReservationStation.scala:196:19, :199:19, :210:27] wire _new_entry_opb_T_bits_start_read_full_acc_row; // @[ReservationStation.scala:210:27] assign _new_entry_opb_T_bits_start_read_full_acc_row = _GEN_23; // @[ReservationStation.scala:210:27] wire _new_entry_opa_T_bits_start_read_full_acc_row; // @[ReservationStation.scala:212:27] assign _new_entry_opa_T_bits_start_read_full_acc_row = _GEN_23; // @[ReservationStation.scala:210:27, :212:27] wire [2:0] _GEN_24 = op1_valid ? op1_bits_start_norm_cmd : op2_bits_start_norm_cmd; // @[ReservationStation.scala:196:19, :199:19, :210:27] wire [2:0] _new_entry_opb_T_bits_start_norm_cmd; // @[ReservationStation.scala:210:27] assign _new_entry_opb_T_bits_start_norm_cmd = _GEN_24; // @[ReservationStation.scala:210:27] wire [2:0] _new_entry_opa_T_bits_start_norm_cmd; // @[ReservationStation.scala:212:27] assign _new_entry_opa_T_bits_start_norm_cmd = _GEN_24; // @[ReservationStation.scala:210:27, :212:27] wire [10:0] _GEN_25 = op1_valid ? op1_bits_start_garbage : op2_bits_start_garbage; // @[ReservationStation.scala:196:19, :199:19, :210:27] wire [10:0] _new_entry_opb_T_bits_start_garbage; // @[ReservationStation.scala:210:27] assign _new_entry_opb_T_bits_start_garbage = _GEN_25; // @[ReservationStation.scala:210:27] wire [10:0] _new_entry_opa_T_bits_start_garbage; // @[ReservationStation.scala:212:27] assign _new_entry_opa_T_bits_start_garbage = _GEN_25; // @[ReservationStation.scala:210:27, :212:27] wire _GEN_26 = op1_valid ? op1_bits_start_garbage_bit : op2_bits_start_garbage_bit; // @[ReservationStation.scala:196:19, :199:19, :210:27] wire _new_entry_opb_T_bits_start_garbage_bit; // @[ReservationStation.scala:210:27] assign _new_entry_opb_T_bits_start_garbage_bit = _GEN_26; // @[ReservationStation.scala:210:27] wire _new_entry_opa_T_bits_start_garbage_bit; // @[ReservationStation.scala:212:27] assign _new_entry_opa_T_bits_start_garbage_bit = _GEN_26; // @[ReservationStation.scala:210:27, :212:27] wire [13:0] _GEN_27 = op1_valid ? op1_bits_start_data : op2_bits_start_data; // @[ReservationStation.scala:196:19, :199:19, :210:27] wire [13:0] _new_entry_opb_T_bits_start_data; // @[ReservationStation.scala:210:27] assign _new_entry_opb_T_bits_start_data = _GEN_27; // @[ReservationStation.scala:210:27] wire [13:0] _new_entry_opa_T_bits_start_data; // @[ReservationStation.scala:212:27] assign _new_entry_opa_T_bits_start_data = _GEN_27; // @[ReservationStation.scala:210:27, :212:27] wire _GEN_28 = op1_valid ? op1_bits_end_is_acc_addr : op2_bits_end_is_acc_addr; // @[ReservationStation.scala:196:19, :199:19, :210:27] wire _new_entry_opb_T_bits_end_is_acc_addr; // @[ReservationStation.scala:210:27] assign _new_entry_opb_T_bits_end_is_acc_addr = _GEN_28; // @[ReservationStation.scala:210:27] wire _new_entry_opa_T_bits_end_is_acc_addr; // @[ReservationStation.scala:212:27] assign _new_entry_opa_T_bits_end_is_acc_addr = _GEN_28; // @[ReservationStation.scala:210:27, :212:27] wire _GEN_29 = op1_valid ? op1_bits_end_accumulate : op2_bits_end_accumulate; // @[ReservationStation.scala:196:19, :199:19, :210:27] wire _new_entry_opb_T_bits_end_accumulate; // @[ReservationStation.scala:210:27] assign _new_entry_opb_T_bits_end_accumulate = _GEN_29; // @[ReservationStation.scala:210:27] wire _new_entry_opa_T_bits_end_accumulate; // @[ReservationStation.scala:212:27] assign _new_entry_opa_T_bits_end_accumulate = _GEN_29; // @[ReservationStation.scala:210:27, :212:27] wire _GEN_30 = op1_valid ? op1_bits_end_read_full_acc_row : op2_bits_end_read_full_acc_row; // @[ReservationStation.scala:196:19, :199:19, :210:27] wire _new_entry_opb_T_bits_end_read_full_acc_row; // @[ReservationStation.scala:210:27] assign _new_entry_opb_T_bits_end_read_full_acc_row = _GEN_30; // @[ReservationStation.scala:210:27] wire _new_entry_opa_T_bits_end_read_full_acc_row; // @[ReservationStation.scala:212:27] assign _new_entry_opa_T_bits_end_read_full_acc_row = _GEN_30; // @[ReservationStation.scala:210:27, :212:27] wire [2:0] _GEN_31 = op1_valid ? op1_bits_end_norm_cmd : op2_bits_end_norm_cmd; // @[ReservationStation.scala:196:19, :199:19, :210:27] wire [2:0] _new_entry_opb_T_bits_end_norm_cmd; // @[ReservationStation.scala:210:27] assign _new_entry_opb_T_bits_end_norm_cmd = _GEN_31; // @[ReservationStation.scala:210:27] wire [2:0] _new_entry_opa_T_bits_end_norm_cmd; // @[ReservationStation.scala:212:27] assign _new_entry_opa_T_bits_end_norm_cmd = _GEN_31; // @[ReservationStation.scala:210:27, :212:27] wire [10:0] _GEN_32 = op1_valid ? op1_bits_end_garbage : op2_bits_end_garbage; // @[ReservationStation.scala:196:19, :199:19, :210:27] wire [10:0] _new_entry_opb_T_bits_end_garbage; // @[ReservationStation.scala:210:27] assign _new_entry_opb_T_bits_end_garbage = _GEN_32; // @[ReservationStation.scala:210:27] wire [10:0] _new_entry_opa_T_bits_end_garbage; // @[ReservationStation.scala:212:27] assign _new_entry_opa_T_bits_end_garbage = _GEN_32; // @[ReservationStation.scala:210:27, :212:27] wire _GEN_33 = op1_valid ? op1_bits_end_garbage_bit : op2_bits_end_garbage_bit; // @[ReservationStation.scala:196:19, :199:19, :210:27] wire _new_entry_opb_T_bits_end_garbage_bit; // @[ReservationStation.scala:210:27] assign _new_entry_opb_T_bits_end_garbage_bit = _GEN_33; // @[ReservationStation.scala:210:27] wire _new_entry_opa_T_bits_end_garbage_bit; // @[ReservationStation.scala:212:27] assign _new_entry_opa_T_bits_end_garbage_bit = _GEN_33; // @[ReservationStation.scala:210:27, :212:27] wire [13:0] _GEN_34 = op1_valid ? op1_bits_end_data : op2_bits_end_data; // @[ReservationStation.scala:196:19, :199:19, :210:27] wire [13:0] _new_entry_opb_T_bits_end_data; // @[ReservationStation.scala:210:27] assign _new_entry_opb_T_bits_end_data = _GEN_34; // @[ReservationStation.scala:210:27] wire [13:0] _new_entry_opa_T_bits_end_data; // @[ReservationStation.scala:212:27] assign _new_entry_opa_T_bits_end_data = _GEN_34; // @[ReservationStation.scala:210:27, :212:27] wire _GEN_35 = op1_valid ? op1_bits_wraps_around : op2_bits_wraps_around; // @[ReservationStation.scala:196:19, :199:19, :210:27] wire _new_entry_opb_T_bits_wraps_around; // @[ReservationStation.scala:210:27] assign _new_entry_opb_T_bits_wraps_around = _GEN_35; // @[ReservationStation.scala:210:27] wire _new_entry_opa_T_bits_wraps_around; // @[ReservationStation.scala:212:27] assign _new_entry_opa_T_bits_wraps_around = _GEN_35; // @[ReservationStation.scala:210:27, :212:27] assign new_entry_opa_valid = dst_valid ? dst_valid : _new_entry_opa_T_valid; // @[ReservationStation.scala:171:23, :202:19, :208:22, :209:21, :212:{21,27}] assign new_entry_opa_bits_start_is_acc_addr = dst_valid ? dst_bits_start_is_acc_addr : _new_entry_opa_T_bits_start_is_acc_addr; // @[ReservationStation.scala:171:23, :202:19, :208:22, :209:21, :212:{21,27}] assign new_entry_opa_bits_start_accumulate = dst_valid ? dst_bits_start_accumulate : _new_entry_opa_T_bits_start_accumulate; // @[ReservationStation.scala:171:23, :202:19, :208:22, :209:21, :212:{21,27}] assign new_entry_opa_bits_start_read_full_acc_row = dst_valid ? dst_bits_start_read_full_acc_row : _new_entry_opa_T_bits_start_read_full_acc_row; // @[ReservationStation.scala:171:23, :202:19, :208:22, :209:21, :212:{21,27}] assign new_entry_opa_bits_start_norm_cmd = dst_valid ? dst_bits_start_norm_cmd : _new_entry_opa_T_bits_start_norm_cmd; // @[ReservationStation.scala:171:23, :202:19, :208:22, :209:21, :212:{21,27}] assign new_entry_opa_bits_start_garbage = dst_valid ? dst_bits_start_garbage : _new_entry_opa_T_bits_start_garbage; // @[ReservationStation.scala:171:23, :202:19, :208:22, :209:21, :212:{21,27}] assign new_entry_opa_bits_start_garbage_bit = dst_valid ? dst_bits_start_garbage_bit : _new_entry_opa_T_bits_start_garbage_bit; // @[ReservationStation.scala:171:23, :202:19, :208:22, :209:21, :212:{21,27}] assign new_entry_opa_bits_start_data = dst_valid ? dst_bits_start_data : _new_entry_opa_T_bits_start_data; // @[ReservationStation.scala:171:23, :202:19, :208:22, :209:21, :212:{21,27}] assign new_entry_opa_bits_end_is_acc_addr = dst_valid ? dst_bits_end_is_acc_addr : _new_entry_opa_T_bits_end_is_acc_addr; // @[ReservationStation.scala:171:23, :202:19, :208:22, :209:21, :212:{21,27}] assign new_entry_opa_bits_end_accumulate = dst_valid ? dst_bits_end_accumulate : _new_entry_opa_T_bits_end_accumulate; // @[ReservationStation.scala:171:23, :202:19, :208:22, :209:21, :212:{21,27}] assign new_entry_opa_bits_end_read_full_acc_row = dst_valid ? dst_bits_end_read_full_acc_row : _new_entry_opa_T_bits_end_read_full_acc_row; // @[ReservationStation.scala:171:23, :202:19, :208:22, :209:21, :212:{21,27}] assign new_entry_opa_bits_end_norm_cmd = dst_valid ? dst_bits_end_norm_cmd : _new_entry_opa_T_bits_end_norm_cmd; // @[ReservationStation.scala:171:23, :202:19, :208:22, :209:21, :212:{21,27}] assign new_entry_opa_bits_end_garbage = dst_valid ? dst_bits_end_garbage : _new_entry_opa_T_bits_end_garbage; // @[ReservationStation.scala:171:23, :202:19, :208:22, :209:21, :212:{21,27}] assign new_entry_opa_bits_end_garbage_bit = dst_valid ? dst_bits_end_garbage_bit : _new_entry_opa_T_bits_end_garbage_bit; // @[ReservationStation.scala:171:23, :202:19, :208:22, :209:21, :212:{21,27}] assign new_entry_opa_bits_end_data = dst_valid ? dst_bits_end_data : _new_entry_opa_T_bits_end_data; // @[ReservationStation.scala:171:23, :202:19, :208:22, :209:21, :212:{21,27}] assign new_entry_opa_bits_wraps_around = dst_valid ? dst_bits_wraps_around : _new_entry_opa_T_bits_wraps_around; // @[ReservationStation.scala:171:23, :202:19, :208:22, :209:21, :212:{21,27}] assign new_entry_opb_valid = dst_valid ? _new_entry_opb_T_valid : op2_valid; // @[ReservationStation.scala:171:23, :199:19, :202:19, :208:22, :210:{21,27}, :213:21] assign new_entry_opb_bits_start_is_acc_addr = dst_valid ? _new_entry_opb_T_bits_start_is_acc_addr : op2_bits_start_is_acc_addr; // @[ReservationStation.scala:171:23, :199:19, :202:19, :208:22, :210:{21,27}, :213:21] assign new_entry_opb_bits_start_accumulate = dst_valid ? _new_entry_opb_T_bits_start_accumulate : op2_bits_start_accumulate; // @[ReservationStation.scala:171:23, :199:19, :202:19, :208:22, :210:{21,27}, :213:21] assign new_entry_opb_bits_start_read_full_acc_row = dst_valid ? _new_entry_opb_T_bits_start_read_full_acc_row : op2_bits_start_read_full_acc_row; // @[ReservationStation.scala:171:23, :199:19, :202:19, :208:22, :210:{21,27}, :213:21] assign new_entry_opb_bits_start_norm_cmd = dst_valid ? _new_entry_opb_T_bits_start_norm_cmd : op2_bits_start_norm_cmd; // @[ReservationStation.scala:171:23, :199:19, :202:19, :208:22, :210:{21,27}, :213:21] assign new_entry_opb_bits_start_garbage = dst_valid ? _new_entry_opb_T_bits_start_garbage : op2_bits_start_garbage; // @[ReservationStation.scala:171:23, :199:19, :202:19, :208:22, :210:{21,27}, :213:21] assign new_entry_opb_bits_start_garbage_bit = dst_valid ? _new_entry_opb_T_bits_start_garbage_bit : op2_bits_start_garbage_bit; // @[ReservationStation.scala:171:23, :199:19, :202:19, :208:22, :210:{21,27}, :213:21] assign new_entry_opb_bits_start_data = dst_valid ? _new_entry_opb_T_bits_start_data : op2_bits_start_data; // @[ReservationStation.scala:171:23, :199:19, :202:19, :208:22, :210:{21,27}, :213:21] assign new_entry_opb_bits_end_is_acc_addr = dst_valid ? _new_entry_opb_T_bits_end_is_acc_addr : op2_bits_end_is_acc_addr; // @[ReservationStation.scala:171:23, :199:19, :202:19, :208:22, :210:{21,27}, :213:21] assign new_entry_opb_bits_end_accumulate = dst_valid ? _new_entry_opb_T_bits_end_accumulate : op2_bits_end_accumulate; // @[ReservationStation.scala:171:23, :199:19, :202:19, :208:22, :210:{21,27}, :213:21] assign new_entry_opb_bits_end_read_full_acc_row = dst_valid ? _new_entry_opb_T_bits_end_read_full_acc_row : op2_bits_end_read_full_acc_row; // @[ReservationStation.scala:171:23, :199:19, :202:19, :208:22, :210:{21,27}, :213:21] assign new_entry_opb_bits_end_norm_cmd = dst_valid ? _new_entry_opb_T_bits_end_norm_cmd : op2_bits_end_norm_cmd; // @[ReservationStation.scala:171:23, :199:19, :202:19, :208:22, :210:{21,27}, :213:21] assign new_entry_opb_bits_end_garbage = dst_valid ? _new_entry_opb_T_bits_end_garbage : op2_bits_end_garbage; // @[ReservationStation.scala:171:23, :199:19, :202:19, :208:22, :210:{21,27}, :213:21] assign new_entry_opb_bits_end_garbage_bit = dst_valid ? _new_entry_opb_T_bits_end_garbage_bit : op2_bits_end_garbage_bit; // @[ReservationStation.scala:171:23, :199:19, :202:19, :208:22, :210:{21,27}, :213:21] assign new_entry_opb_bits_end_data = dst_valid ? _new_entry_opb_T_bits_end_data : op2_bits_end_data; // @[ReservationStation.scala:171:23, :199:19, :202:19, :208:22, :210:{21,27}, :213:21] assign new_entry_opb_bits_wraps_around = dst_valid ? _new_entry_opb_T_bits_wraps_around : op2_bits_wraps_around; // @[ReservationStation.scala:171:23, :199:19, :202:19, :208:22, :210:{21,27}, :213:21] wire _T_4831 = io_alloc_bits_cmd_inst_funct_0 == 7'h6; // @[ReservationStation.scala:26:7, :216:24] wire _op1_valid_T; // @[ReservationStation.scala:216:24] assign _op1_valid_T = _T_4831; // @[ReservationStation.scala:216:24] wire _dst_valid_T; // @[ReservationStation.scala:261:24] assign _dst_valid_T = _T_4831; // @[ReservationStation.scala:216:24, :261:24] wire _is_ex_T; // @[ReservationStation.scala:296:23] assign _is_ex_T = _T_4831; // @[ReservationStation.scala:216:24, :296:23] assign _op1_valid_T_1 = _op1_valid_T | funct_is_compute; // @[ReservationStation.scala:188:59, :216:{24,40}] assign op1_valid = _op1_valid_T_1; // @[ReservationStation.scala:196:19, :216:40] wire _op1_bits_start_T_6; // @[ReservationStation.scala:217:39] assign op1_bits_start_is_acc_addr = _op1_bits_start_WIRE_is_acc_addr; // @[ReservationStation.scala:196:19, :217:39] wire _op1_bits_start_T_5; // @[ReservationStation.scala:217:39] assign op1_bits_start_accumulate = _op1_bits_start_WIRE_accumulate; // @[ReservationStation.scala:196:19, :217:39] wire _op1_bits_start_T_4; // @[ReservationStation.scala:217:39] assign op1_bits_start_read_full_acc_row = _op1_bits_start_WIRE_read_full_acc_row; // @[ReservationStation.scala:196:19, :217:39] wire [2:0] _op1_bits_start_WIRE_3; // @[ReservationStation.scala:217:39] assign op1_bits_start_norm_cmd = _op1_bits_start_WIRE_norm_cmd; // @[ReservationStation.scala:196:19, :217:39] wire [10:0] _op1_bits_start_T_2; // @[ReservationStation.scala:217:39] assign op1_bits_start_garbage = _op1_bits_start_WIRE_garbage; // @[ReservationStation.scala:196:19, :217:39] wire _op1_bits_start_T_1; // @[ReservationStation.scala:217:39] assign op1_bits_start_garbage_bit = _op1_bits_start_WIRE_garbage_bit; // @[ReservationStation.scala:196:19, :217:39] wire [13:0] _op1_bits_start_T; // @[ReservationStation.scala:217:39] assign op1_bits_start_data = _op1_bits_start_WIRE_data; // @[ReservationStation.scala:196:19, :217:39] wire [31:0] _op1_bits_start_WIRE_1 = io_alloc_bits_cmd_rs1_0[31:0]; // @[ReservationStation.scala:26:7, :217:39] assign _op1_bits_start_T = _op1_bits_start_WIRE_1[13:0]; // @[ReservationStation.scala:217:39] assign _op1_bits_start_WIRE_data = _op1_bits_start_T; // @[ReservationStation.scala:217:39] assign _op1_bits_start_T_1 = _op1_bits_start_WIRE_1[14]; // @[ReservationStation.scala:217:39] assign _op1_bits_start_WIRE_garbage_bit = _op1_bits_start_T_1; // @[ReservationStation.scala:217:39] assign _op1_bits_start_T_2 = _op1_bits_start_WIRE_1[25:15]; // @[ReservationStation.scala:217:39] assign _op1_bits_start_WIRE_garbage = _op1_bits_start_T_2; // @[ReservationStation.scala:217:39] wire [2:0] _op1_bits_start_T_3 = _op1_bits_start_WIRE_1[28:26]; // @[ReservationStation.scala:217:39] wire [2:0] _op1_bits_start_WIRE_2 = _op1_bits_start_T_3; // @[ReservationStation.scala:217:39] assign _op1_bits_start_WIRE_3 = _op1_bits_start_WIRE_2; // @[ReservationStation.scala:217:39] assign _op1_bits_start_WIRE_norm_cmd = _op1_bits_start_WIRE_3; // @[ReservationStation.scala:217:39] assign _op1_bits_start_T_4 = _op1_bits_start_WIRE_1[29]; // @[ReservationStation.scala:217:39] assign _op1_bits_start_WIRE_read_full_acc_row = _op1_bits_start_T_4; // @[ReservationStation.scala:217:39] assign _op1_bits_start_T_5 = _op1_bits_start_WIRE_1[30]; // @[ReservationStation.scala:217:39] assign _op1_bits_start_WIRE_accumulate = _op1_bits_start_T_5; // @[ReservationStation.scala:217:39] assign _op1_bits_start_T_6 = _op1_bits_start_WIRE_1[31]; // @[ReservationStation.scala:217:39] assign _op1_bits_start_WIRE_is_acc_addr = _op1_bits_start_T_6; // @[ReservationStation.scala:217:39] wire [2:0] preload_rows = io_alloc_bits_cmd_rs1_0[50:48]; // @[ReservationStation.scala:26:7, :220:33] wire [2:0] rows = io_alloc_bits_cmd_rs1_0[50:48]; // @[ReservationStation.scala:26:7, :220:33, :224:25] wire [13:0] _op1_bits_end_result_data_T_1; // @[LocalAddr.scala:51:25] wire [13:0] op1_bits_end_result_data; // @[LocalAddr.scala:50:26] wire [14:0] _GEN_36 = {1'h0, op1_bits_start_data} + {12'h0, preload_rows}; // @[ReservationStation.scala:196:19, :220:33] wire [14:0] _op1_bits_end_result_data_T; // @[LocalAddr.scala:51:25] assign _op1_bits_end_result_data_T = _GEN_36; // @[LocalAddr.scala:51:25] wire [14:0] op1_bits_wraps_around_sum; // @[LocalAddr.scala:71:20] assign op1_bits_wraps_around_sum = _GEN_36; // @[LocalAddr.scala:51:25, :71:20] assign _op1_bits_end_result_data_T_1 = _op1_bits_end_result_data_T[13:0]; // @[LocalAddr.scala:51:25] assign op1_bits_end_result_data = _op1_bits_end_result_data_T_1; // @[LocalAddr.scala:50:26, :51:25] wire _op1_bits_wraps_around_overflow_T = op1_bits_wraps_around_sum[12]; // @[LocalAddr.scala:71:20, :73:40] wire _op1_bits_wraps_around_overflow_T_1 = op1_bits_wraps_around_sum[14]; // @[LocalAddr.scala:71:20, :73:58] wire op1_bits_wraps_around_overflow = op1_bits_start_is_acc_addr ? _op1_bits_wraps_around_overflow_T : _op1_bits_wraps_around_overflow_T_1; // @[ReservationStation.scala:196:19] wire [13:0] _op1_bits_wraps_around_result_data_T; // @[LocalAddr.scala:76:23] wire [13:0] op1_bits_wraps_around_result_data; // @[LocalAddr.scala:75:26] assign _op1_bits_wraps_around_result_data_T = op1_bits_wraps_around_sum[13:0]; // @[LocalAddr.scala:71:20, :76:23] assign op1_bits_wraps_around_result_data = _op1_bits_wraps_around_result_data_T; // @[LocalAddr.scala:75:26, :76:23] wire [2:0] cols = io_alloc_bits_cmd_rs1_0[34:32]; // @[ReservationStation.scala:26:7, :225:25] wire [2:0] _compute_rows_T = a_transpose ? cols : rows; // @[ReservationStation.scala:165:24, :224:25, :225:25, :226:29] wire [16:0] compute_rows = {14'h0, _compute_rows_T} * {3'h0, a_stride}; // @[ReservationStation.scala:163:21, :226:{29,55}] wire [13:0] op1_bits_end_result_1_data; // @[LocalAddr.scala:50:26] wire [17:0] _GEN_37 = {4'h0, op1_bits_start_data} + {1'h0, compute_rows}; // @[ReservationStation.scala:196:19, :226:55] wire [17:0] _op1_bits_end_result_data_T_2; // @[LocalAddr.scala:51:25] assign _op1_bits_end_result_data_T_2 = _GEN_37; // @[LocalAddr.scala:51:25] wire [17:0] op1_bits_wraps_around_sum_1; // @[LocalAddr.scala:71:20] assign op1_bits_wraps_around_sum_1 = _GEN_37; // @[LocalAddr.scala:51:25, :71:20] wire [16:0] _op1_bits_end_result_data_T_3 = _op1_bits_end_result_data_T_2[16:0]; // @[LocalAddr.scala:51:25] assign op1_bits_end_result_1_data = _op1_bits_end_result_data_T_3[13:0]; // @[LocalAddr.scala:50:26, :51:{17,25}] assign op1_bits_end_is_acc_addr = _T_4831 ? op1_bits_end_result_is_acc_addr : op1_bits_end_result_1_is_acc_addr; // @[ReservationStation.scala:196:19, :216:24, :218:34, :221:20, :227:20] assign op1_bits_end_accumulate = _T_4831 ? op1_bits_end_result_accumulate : op1_bits_end_result_1_accumulate; // @[ReservationStation.scala:196:19, :216:24, :218:34, :221:20, :227:20] assign op1_bits_end_read_full_acc_row = _T_4831 ? op1_bits_end_result_read_full_acc_row : op1_bits_end_result_1_read_full_acc_row; // @[ReservationStation.scala:196:19, :216:24, :218:34, :221:20, :227:20] assign op1_bits_end_norm_cmd = _T_4831 ? op1_bits_end_result_norm_cmd : op1_bits_end_result_1_norm_cmd; // @[ReservationStation.scala:196:19, :216:24, :218:34, :221:20, :227:20] assign op1_bits_end_garbage = _T_4831 ? op1_bits_end_result_garbage : op1_bits_end_result_1_garbage; // @[ReservationStation.scala:196:19, :216:24, :218:34, :221:20, :227:20] assign op1_bits_end_garbage_bit = _T_4831 ? op1_bits_end_result_garbage_bit : op1_bits_end_result_1_garbage_bit; // @[ReservationStation.scala:196:19, :216:24, :218:34, :221:20, :227:20] assign op1_bits_end_data = _T_4831 ? op1_bits_end_result_data : op1_bits_end_result_1_data; // @[ReservationStation.scala:196:19, :216:24, :218:34, :221:20, :227:20] wire _op1_bits_wraps_around_overflow_T_2 = op1_bits_wraps_around_sum_1[12]; // @[LocalAddr.scala:71:20, :73:40] wire _op1_bits_wraps_around_overflow_T_3 = op1_bits_wraps_around_sum_1[14]; // @[LocalAddr.scala:71:20, :73:58] wire op1_bits_wraps_around_overflow_1 = op1_bits_start_is_acc_addr ? _op1_bits_wraps_around_overflow_T_2 : _op1_bits_wraps_around_overflow_T_3; // @[ReservationStation.scala:196:19] wire [13:0] _op1_bits_wraps_around_result_data_T_1; // @[LocalAddr.scala:76:23] wire [13:0] op1_bits_wraps_around_result_1_data; // @[LocalAddr.scala:75:26] assign _op1_bits_wraps_around_result_data_T_1 = op1_bits_wraps_around_sum_1[13:0]; // @[LocalAddr.scala:71:20, :76:23] assign op1_bits_wraps_around_result_1_data = _op1_bits_wraps_around_result_data_T_1; // @[LocalAddr.scala:75:26, :76:23] assign op1_bits_wraps_around = _T_4831 ? op1_bits_wraps_around_overflow : op1_bits_wraps_around_overflow_1; // @[ReservationStation.scala:196:19, :216:24, :218:34, :222:29, :228:29] wire _GEN_38 = io_alloc_bits_cmd_inst_funct_0 == 7'h3; // @[ReservationStation.scala:26:7, :231:44] wire _op2_valid_T; // @[ReservationStation.scala:231:44] assign _op2_valid_T = _GEN_38; // @[ReservationStation.scala:231:44] wire _is_store_T; // @[ReservationStation.scala:297:26] assign _is_store_T = _GEN_38; // @[ReservationStation.scala:231:44, :297:26] assign _op2_valid_T_1 = funct_is_compute | _op2_valid_T; // @[ReservationStation.scala:188:59, :231:{35,44}] assign op2_valid = _op2_valid_T_1; // @[ReservationStation.scala:199:19, :231:35] wire _op2_bits_start_T_6; // @[ReservationStation.scala:232:39] assign op2_bits_start_is_acc_addr = _op2_bits_start_WIRE_is_acc_addr; // @[ReservationStation.scala:199:19, :232:39] wire _op2_bits_start_T_5; // @[ReservationStation.scala:232:39] assign op2_bits_start_accumulate = _op2_bits_start_WIRE_accumulate; // @[ReservationStation.scala:199:19, :232:39] wire _op2_bits_start_T_4; // @[ReservationStation.scala:232:39] assign op2_bits_start_read_full_acc_row = _op2_bits_start_WIRE_read_full_acc_row; // @[ReservationStation.scala:199:19, :232:39] wire [2:0] _op2_bits_start_WIRE_3; // @[ReservationStation.scala:232:39] assign op2_bits_start_norm_cmd = _op2_bits_start_WIRE_norm_cmd; // @[ReservationStation.scala:199:19, :232:39] wire [10:0] _op2_bits_start_T_2; // @[ReservationStation.scala:232:39] assign op2_bits_start_garbage = _op2_bits_start_WIRE_garbage; // @[ReservationStation.scala:199:19, :232:39] wire _op2_bits_start_T_1; // @[ReservationStation.scala:232:39] assign op2_bits_start_garbage_bit = _op2_bits_start_WIRE_garbage_bit; // @[ReservationStation.scala:199:19, :232:39] wire [13:0] _op2_bits_start_T; // @[ReservationStation.scala:232:39] assign op2_bits_start_data = _op2_bits_start_WIRE_data; // @[ReservationStation.scala:199:19, :232:39] wire [31:0] _op2_bits_start_WIRE_1 = io_alloc_bits_cmd_rs2_0[31:0]; // @[ReservationStation.scala:26:7, :232:39] wire [31:0] _dst_bits_start_T = io_alloc_bits_cmd_rs2_0[31:0]; // @[ReservationStation.scala:26:7, :232:39, :262:30] wire [31:0] _start_T = io_alloc_bits_cmd_rs2_0[31:0]; // @[ReservationStation.scala:26:7, :232:39, :281:28] assign _op2_bits_start_T = _op2_bits_start_WIRE_1[13:0]; // @[ReservationStation.scala:232:39] assign _op2_bits_start_WIRE_data = _op2_bits_start_T; // @[ReservationStation.scala:232:39] assign _op2_bits_start_T_1 = _op2_bits_start_WIRE_1[14]; // @[ReservationStation.scala:232:39] assign _op2_bits_start_WIRE_garbage_bit = _op2_bits_start_T_1; // @[ReservationStation.scala:232:39] assign _op2_bits_start_T_2 = _op2_bits_start_WIRE_1[25:15]; // @[ReservationStation.scala:232:39] assign _op2_bits_start_WIRE_garbage = _op2_bits_start_T_2; // @[ReservationStation.scala:232:39] wire [2:0] _op2_bits_start_T_3 = _op2_bits_start_WIRE_1[28:26]; // @[ReservationStation.scala:232:39] wire [2:0] _op2_bits_start_WIRE_2 = _op2_bits_start_T_3; // @[ReservationStation.scala:232:39] assign _op2_bits_start_WIRE_3 = _op2_bits_start_WIRE_2; // @[ReservationStation.scala:232:39] assign _op2_bits_start_WIRE_norm_cmd = _op2_bits_start_WIRE_3; // @[ReservationStation.scala:232:39] assign _op2_bits_start_T_4 = _op2_bits_start_WIRE_1[29]; // @[ReservationStation.scala:232:39] assign _op2_bits_start_WIRE_read_full_acc_row = _op2_bits_start_T_4; // @[ReservationStation.scala:232:39] assign _op2_bits_start_T_5 = _op2_bits_start_WIRE_1[30]; // @[ReservationStation.scala:232:39] assign _op2_bits_start_WIRE_accumulate = _op2_bits_start_T_5; // @[ReservationStation.scala:232:39] assign _op2_bits_start_T_6 = _op2_bits_start_WIRE_1[31]; // @[ReservationStation.scala:232:39] assign _op2_bits_start_WIRE_is_acc_addr = _op2_bits_start_T_6; // @[ReservationStation.scala:232:39] wire [2:0] compute_rows_1 = io_alloc_bits_cmd_rs2_0[50:48]; // @[ReservationStation.scala:26:7, :234:33] wire [2:0] mvout_rows = io_alloc_bits_cmd_rs2_0[50:48]; // @[ReservationStation.scala:26:7, :234:33, :252:31] wire [2:0] _preload_rows_T = io_alloc_bits_cmd_rs2_0[50:48]; // @[ReservationStation.scala:26:7, :234:33, :264:33] wire [2:0] mvin_rows = io_alloc_bits_cmd_rs2_0[50:48]; // @[ReservationStation.scala:26:7, :234:33, :274:30] wire [13:0] _op2_bits_end_result_data_T_1; // @[LocalAddr.scala:51:25] wire [13:0] op2_bits_end_result_data; // @[LocalAddr.scala:50:26] wire [14:0] _GEN_39 = {1'h0, op2_bits_start_data}; // @[ReservationStation.scala:199:19] wire [14:0] _GEN_40 = _GEN_39 + {12'h0, compute_rows_1}; // @[ReservationStation.scala:234:33] wire [14:0] _op2_bits_end_result_data_T; // @[LocalAddr.scala:51:25] assign _op2_bits_end_result_data_T = _GEN_40; // @[LocalAddr.scala:51:25] wire [14:0] op2_bits_wraps_around_sum; // @[LocalAddr.scala:71:20] assign op2_bits_wraps_around_sum = _GEN_40; // @[LocalAddr.scala:51:25, :71:20] assign _op2_bits_end_result_data_T_1 = _op2_bits_end_result_data_T[13:0]; // @[LocalAddr.scala:51:25] assign op2_bits_end_result_data = _op2_bits_end_result_data_T_1; // @[LocalAddr.scala:50:26, :51:25] wire _op2_bits_wraps_around_overflow_T = op2_bits_wraps_around_sum[12]; // @[LocalAddr.scala:71:20, :73:40] wire _op2_bits_wraps_around_overflow_T_1 = op2_bits_wraps_around_sum[14]; // @[LocalAddr.scala:71:20, :73:58] wire op2_bits_wraps_around_overflow = op2_bits_start_is_acc_addr ? _op2_bits_wraps_around_overflow_T : _op2_bits_wraps_around_overflow_T_1; // @[ReservationStation.scala:199:19] wire [13:0] _op2_bits_wraps_around_result_data_T; // @[LocalAddr.scala:76:23] wire [13:0] op2_bits_wraps_around_result_data; // @[LocalAddr.scala:75:26] assign _op2_bits_wraps_around_result_data_T = op2_bits_wraps_around_sum[13:0]; // @[LocalAddr.scala:71:20, :76:23] assign op2_bits_wraps_around_result_data = _op2_bits_wraps_around_result_data_T; // @[LocalAddr.scala:75:26, :76:23] wire [4:0] mvout_cols = io_alloc_bits_cmd_rs2_0[36:32]; // @[ReservationStation.scala:26:7, :251:31] wire [4:0] mvin_cols = io_alloc_bits_cmd_rs2_0[36:32]; // @[ReservationStation.scala:26:7, :251:31, :273:30] wire [4:0] _mvout_mats_T = mvout_cols / 5'h4; // @[ReservationStation.scala:251:31, :254:35] wire [4:0] _GEN_41 = mvout_cols % 5'h4; // @[ReservationStation.scala:251:31, :254:83] wire [2:0] _mvout_mats_T_1 = _GEN_41[2:0]; // @[ReservationStation.scala:254:83] wire _mvout_mats_T_2 = |_mvout_mats_T_1; // @[ReservationStation.scala:254:{83,98}] wire [5:0] _mvout_mats_T_3 = {1'h0, _mvout_mats_T} + {5'h0, _mvout_mats_T_2}; // @[ReservationStation.scala:254:{35,69,98}] wire [4:0] mvout_mats = _mvout_mats_T_3[4:0]; // @[ReservationStation.scala:254:69] wire [5:0] _total_mvout_rows_T = {1'h0, mvout_mats} - 6'h1; // @[ReservationStation.scala:254:69, :255:43] wire [4:0] _total_mvout_rows_T_1 = _total_mvout_rows_T[4:0]; // @[ReservationStation.scala:255:43] wire [7:0] _total_mvout_rows_T_2 = {1'h0, _total_mvout_rows_T_1, 2'h0}; // @[ReservationStation.scala:255:{43,50}] wire [8:0] _total_mvout_rows_T_3 = {1'h0, _total_mvout_rows_T_2} + {6'h0, mvout_rows}; // @[ReservationStation.scala:252:31, :255:{50,66}] wire [7:0] total_mvout_rows = _total_mvout_rows_T_3[7:0]; // @[ReservationStation.scala:255:66] wire [13:0] _op2_bits_end_result_data_T_3; // @[LocalAddr.scala:51:25] wire [13:0] op2_bits_end_result_1_data; // @[LocalAddr.scala:50:26] wire [14:0] _GEN_42 = _GEN_39 + {7'h0, total_mvout_rows}; // @[ReservationStation.scala:255:66] wire [14:0] _op2_bits_end_result_data_T_2; // @[LocalAddr.scala:51:25] assign _op2_bits_end_result_data_T_2 = _GEN_42; // @[LocalAddr.scala:51:25] wire [14:0] op2_bits_wraps_around_sum_1; // @[LocalAddr.scala:71:20] assign op2_bits_wraps_around_sum_1 = _GEN_42; // @[LocalAddr.scala:51:25, :71:20] assign _op2_bits_end_result_data_T_3 = _op2_bits_end_result_data_T_2[13:0]; // @[LocalAddr.scala:51:25] assign op2_bits_end_result_1_data = _op2_bits_end_result_data_T_3; // @[LocalAddr.scala:50:26, :51:25] assign op2_bits_end_is_acc_addr = funct_is_compute ? op2_bits_end_result_is_acc_addr : pooling_is_enabled | op2_bits_end_result_1_is_acc_addr; // @[ReservationStation.scala:168:31, :188:59, :199:19, :233:29, :235:20, :237:37, :246:20, :257:20] assign op2_bits_end_accumulate = funct_is_compute ? op2_bits_end_result_accumulate : ~pooling_is_enabled & op2_bits_end_result_1_accumulate; // @[ReservationStation.scala:168:31, :188:59, :199:19, :233:29, :235:20, :237:37, :246:20, :257:20] assign op2_bits_end_read_full_acc_row = funct_is_compute ? op2_bits_end_result_read_full_acc_row : ~pooling_is_enabled & op2_bits_end_result_1_read_full_acc_row; // @[ReservationStation.scala:168:31, :188:59, :199:19, :233:29, :235:20, :237:37, :246:20, :257:20] assign op2_bits_end_norm_cmd = funct_is_compute ? op2_bits_end_result_norm_cmd : pooling_is_enabled ? 3'h0 : op2_bits_end_result_1_norm_cmd; // @[ReservationStation.scala:168:31, :188:59, :199:19, :233:29, :235:20, :237:37, :246:20, :257:20] assign op2_bits_end_garbage = funct_is_compute ? op2_bits_end_result_garbage : pooling_is_enabled ? 11'h0 : op2_bits_end_result_1_garbage; // @[ReservationStation.scala:168:31, :188:59, :199:19, :233:29, :235:20, :237:37, :246:20, :257:20] assign op2_bits_end_garbage_bit = funct_is_compute ? op2_bits_end_result_garbage_bit : ~pooling_is_enabled & op2_bits_end_result_1_garbage_bit; // @[ReservationStation.scala:168:31, :188:59, :199:19, :233:29, :235:20, :237:37, :246:20, :257:20] assign op2_bits_end_data = funct_is_compute ? op2_bits_end_result_data : pooling_is_enabled ? 14'h1000 : op2_bits_end_result_1_data; // @[ReservationStation.scala:168:31, :188:59, :199:19, :233:29, :235:20, :237:37, :246:20, :257:20] wire _op2_bits_wraps_around_overflow_T_2 = op2_bits_wraps_around_sum_1[12]; // @[LocalAddr.scala:71:20, :73:40] wire _op2_bits_wraps_around_overflow_T_3 = op2_bits_wraps_around_sum_1[14]; // @[LocalAddr.scala:71:20, :73:58] wire op2_bits_wraps_around_overflow_1 = op2_bits_start_is_acc_addr ? _op2_bits_wraps_around_overflow_T_2 : _op2_bits_wraps_around_overflow_T_3; // @[ReservationStation.scala:199:19] wire [13:0] _op2_bits_wraps_around_result_data_T_1; // @[LocalAddr.scala:76:23] wire [13:0] op2_bits_wraps_around_result_1_data; // @[LocalAddr.scala:75:26] assign _op2_bits_wraps_around_result_data_T_1 = op2_bits_wraps_around_sum_1[13:0]; // @[LocalAddr.scala:71:20, :76:23] assign op2_bits_wraps_around_result_1_data = _op2_bits_wraps_around_result_data_T_1; // @[LocalAddr.scala:75:26, :76:23] wire _op2_bits_wraps_around_T_1 = pooling_is_enabled | op2_bits_wraps_around_overflow_1; // @[ReservationStation.scala:168:31, :258:51] assign op2_bits_wraps_around = funct_is_compute ? op2_bits_wraps_around_overflow : pooling_is_enabled | _op2_bits_wraps_around_T_1; // @[ReservationStation.scala:168:31, :188:59, :199:19, :233:29, :236:29, :237:37, :247:29, :258:{29,51}] wire _GEN_43 = io_alloc_bits_cmd_inst_funct_0 == 7'h2; // @[ReservationStation.scala:26:7, :261:49] wire _dst_valid_T_1; // @[ReservationStation.scala:261:49] assign _dst_valid_T_1 = _GEN_43; // @[ReservationStation.scala:261:49] wire _is_load_T; // @[ReservationStation.scala:295:25] assign _is_load_T = _GEN_43; // @[ReservationStation.scala:261:49, :295:25] wire _dst_valid_T_2 = _dst_valid_T | _dst_valid_T_1; // @[ReservationStation.scala:261:{24,40,49}] wire _GEN_44 = io_alloc_bits_cmd_inst_funct_0 == 7'h1; // @[ReservationStation.scala:26:7, :261:71] wire _dst_valid_T_3; // @[ReservationStation.scala:261:71] assign _dst_valid_T_3 = _GEN_44; // @[ReservationStation.scala:261:71] wire _is_load_T_1; // @[ReservationStation.scala:295:47] assign _is_load_T_1 = _GEN_44; // @[ReservationStation.scala:261:71, :295:47] wire _dst_valid_T_4 = _dst_valid_T_2 | _dst_valid_T_3; // @[ReservationStation.scala:261:{40,62,71}] wire _GEN_45 = io_alloc_bits_cmd_inst_funct_0 == 7'hE; // @[ReservationStation.scala:26:7, :261:94] wire _dst_valid_T_5; // @[ReservationStation.scala:261:94] assign _dst_valid_T_5 = _GEN_45; // @[ReservationStation.scala:261:94] wire _is_load_T_3; // @[ReservationStation.scala:295:70] assign _is_load_T_3 = _GEN_45; // @[ReservationStation.scala:261:94, :295:70] assign _dst_valid_T_6 = _dst_valid_T_4 | _dst_valid_T_5; // @[ReservationStation.scala:261:{62,85,94}] assign dst_valid = _dst_valid_T_6; // @[ReservationStation.scala:202:19, :261:85] wire [31:0] _dst_bits_start_WIRE_1 = _dst_bits_start_T; // @[ReservationStation.scala:262:{30,46}] wire _dst_bits_start_T_7; // @[ReservationStation.scala:262:46] wire _dst_bits_start_T_6; // @[ReservationStation.scala:262:46] wire _dst_bits_start_T_5; // @[ReservationStation.scala:262:46] wire [2:0] _dst_bits_start_WIRE_3; // @[ReservationStation.scala:262:46] wire [10:0] _dst_bits_start_T_3; // @[ReservationStation.scala:262:46] wire _dst_bits_start_T_2; // @[ReservationStation.scala:262:46] wire [13:0] _dst_bits_start_T_1; // @[ReservationStation.scala:262:46] assign _dst_bits_start_T_1 = _dst_bits_start_WIRE_1[13:0]; // @[ReservationStation.scala:262:46] wire [13:0] _dst_bits_start_WIRE_data = _dst_bits_start_T_1; // @[ReservationStation.scala:262:46] assign _dst_bits_start_T_2 = _dst_bits_start_WIRE_1[14]; // @[ReservationStation.scala:262:46] wire _dst_bits_start_WIRE_garbage_bit = _dst_bits_start_T_2; // @[ReservationStation.scala:262:46] assign _dst_bits_start_T_3 = _dst_bits_start_WIRE_1[25:15]; // @[ReservationStation.scala:262:46] wire [10:0] _dst_bits_start_WIRE_garbage = _dst_bits_start_T_3; // @[ReservationStation.scala:262:46] wire [2:0] _dst_bits_start_T_4 = _dst_bits_start_WIRE_1[28:26]; // @[ReservationStation.scala:262:46] wire [2:0] _dst_bits_start_WIRE_2 = _dst_bits_start_T_4; // @[ReservationStation.scala:262:46] assign _dst_bits_start_WIRE_3 = _dst_bits_start_WIRE_2; // @[ReservationStation.scala:262:46] wire [2:0] _dst_bits_start_WIRE_norm_cmd = _dst_bits_start_WIRE_3; // @[ReservationStation.scala:262:46] assign _dst_bits_start_T_5 = _dst_bits_start_WIRE_1[29]; // @[ReservationStation.scala:262:46] wire _dst_bits_start_WIRE_read_full_acc_row = _dst_bits_start_T_5; // @[ReservationStation.scala:262:46] assign _dst_bits_start_T_6 = _dst_bits_start_WIRE_1[30]; // @[ReservationStation.scala:262:46] wire _dst_bits_start_WIRE_accumulate = _dst_bits_start_T_6; // @[ReservationStation.scala:262:46] assign _dst_bits_start_T_7 = _dst_bits_start_WIRE_1[31]; // @[ReservationStation.scala:262:46] wire _dst_bits_start_WIRE_is_acc_addr = _dst_bits_start_T_7; // @[ReservationStation.scala:262:46] wire [16:0] preload_rows_1 = {14'h0, _preload_rows_T} * {3'h0, c_stride}; // @[ReservationStation.scala:164:21, :264:{33,71}] wire [13:0] dst_bits_end_result_data; // @[LocalAddr.scala:50:26] wire [17:0] _GEN_46 = {4'h0, dst_bits_start_data} + {1'h0, preload_rows_1}; // @[ReservationStation.scala:202:19, :264:71] wire [17:0] _dst_bits_end_result_data_T; // @[LocalAddr.scala:51:25] assign _dst_bits_end_result_data_T = _GEN_46; // @[LocalAddr.scala:51:25] wire [17:0] dst_bits_wraps_around_sum; // @[LocalAddr.scala:71:20] assign dst_bits_wraps_around_sum = _GEN_46; // @[LocalAddr.scala:51:25, :71:20] wire [16:0] _dst_bits_end_result_data_T_1 = _dst_bits_end_result_data_T[16:0]; // @[LocalAddr.scala:51:25] assign dst_bits_end_result_data = _dst_bits_end_result_data_T_1[13:0]; // @[LocalAddr.scala:50:26, :51:{17,25}] wire _dst_bits_wraps_around_overflow_T = dst_bits_wraps_around_sum[12]; // @[LocalAddr.scala:71:20, :73:40] wire _dst_bits_wraps_around_overflow_T_1 = dst_bits_wraps_around_sum[14]; // @[LocalAddr.scala:71:20, :73:58] wire dst_bits_wraps_around_overflow = dst_bits_start_is_acc_addr ? _dst_bits_wraps_around_overflow_T : _dst_bits_wraps_around_overflow_T_1; // @[ReservationStation.scala:202:19] wire [13:0] _dst_bits_wraps_around_result_data_T; // @[LocalAddr.scala:76:23] wire [13:0] dst_bits_wraps_around_result_data; // @[LocalAddr.scala:75:26] assign _dst_bits_wraps_around_result_data_T = dst_bits_wraps_around_sum[13:0]; // @[LocalAddr.scala:71:20, :76:23] assign dst_bits_wraps_around_result_data = _dst_bits_wraps_around_result_data_T; // @[LocalAddr.scala:75:26, :76:23] wire _id_T = new_entry_cmd_cmd_inst_funct == 7'h1; // @[ReservationStation.scala:171:23, :268:63] wire _id_T_1 = new_entry_cmd_cmd_inst_funct == 7'hE; // @[ReservationStation.scala:171:23, :269:39] wire [1:0] _id_T_2 = {_id_T_1, 1'h0}; // @[Mux.scala:126:16] wire [1:0] id = _id_T ? 2'h1 : _id_T_2; // @[Mux.scala:126:16] wire [4:0] _mvin_mats_T = mvin_cols / 5'h4; // @[ReservationStation.scala:273:30, :276:33] wire [4:0] _GEN_47 = mvin_cols % 5'h4; // @[ReservationStation.scala:273:30, :276:79] wire [2:0] _mvin_mats_T_1 = _GEN_47[2:0]; // @[ReservationStation.scala:276:79] wire _mvin_mats_T_2 = |_mvin_mats_T_1; // @[ReservationStation.scala:276:{79,94}] wire [5:0] _mvin_mats_T_3 = {1'h0, _mvin_mats_T} + {5'h0, _mvin_mats_T_2}; // @[ReservationStation.scala:276:{33,66,94}] wire [4:0] mvin_mats = _mvin_mats_T_3[4:0]; // @[ReservationStation.scala:276:66] wire [5:0] _total_mvin_rows_T = {1'h0, mvin_mats} - 6'h1; // @[ReservationStation.scala:276:66, :277:41] wire [4:0] _total_mvin_rows_T_1 = _total_mvin_rows_T[4:0]; // @[ReservationStation.scala:277:41] wire [3:0][13:0] _GEN_48 = {{ld_block_strides_0}, {ld_block_strides_2}, {ld_block_strides_1}, {ld_block_strides_0}}; // @[ReservationStation.scala:166:29, :277:48] wire [18:0] _total_mvin_rows_T_2 = {14'h0, _total_mvin_rows_T_1} * {5'h0, _GEN_48[id]}; // @[Mux.scala:126:16] wire [19:0] _total_mvin_rows_T_3 = {1'h0, _total_mvin_rows_T_2} + {17'h0, mvin_rows}; // @[ReservationStation.scala:274:30, :277:{48,64}] wire [18:0] total_mvin_rows = _total_mvin_rows_T_3[18:0]; // @[ReservationStation.scala:277:64] wire [31:0] _start_WIRE = _start_T; // @[ReservationStation.scala:281:{28,44}] wire _start_T_7; // @[ReservationStation.scala:281:44] wire _start_T_6; // @[ReservationStation.scala:281:44] wire dst_bits_start_result_is_acc_addr = start_is_acc_addr; // @[ReservationStation.scala:281:44] wire dst_bits_start_result_1_is_acc_addr = start_is_acc_addr; // @[ReservationStation.scala:281:44] wire _start_T_5; // @[ReservationStation.scala:281:44] wire dst_bits_start_result_accumulate = start_accumulate; // @[ReservationStation.scala:281:44] wire dst_bits_start_result_1_accumulate = start_accumulate; // @[ReservationStation.scala:281:44] wire [2:0] _start_WIRE_2; // @[ReservationStation.scala:281:44] wire dst_bits_start_result_read_full_acc_row = start_read_full_acc_row; // @[ReservationStation.scala:281:44] wire dst_bits_start_result_1_read_full_acc_row = start_read_full_acc_row; // @[ReservationStation.scala:281:44] wire [10:0] _start_T_3; // @[ReservationStation.scala:281:44] wire [2:0] dst_bits_start_result_norm_cmd = start_norm_cmd; // @[ReservationStation.scala:281:44] wire [2:0] dst_bits_start_result_1_norm_cmd = start_norm_cmd; // @[ReservationStation.scala:281:44] wire _start_T_2; // @[ReservationStation.scala:281:44] wire [10:0] dst_bits_start_result_garbage = start_garbage; // @[ReservationStation.scala:281:44] wire [10:0] dst_bits_start_result_1_garbage = start_garbage; // @[ReservationStation.scala:281:44] wire [13:0] _start_T_1; // @[ReservationStation.scala:281:44] wire dst_bits_start_result_garbage_bit = start_garbage_bit; // @[ReservationStation.scala:281:44] wire dst_bits_start_result_1_garbage_bit = start_garbage_bit; // @[ReservationStation.scala:281:44] wire [13:0] start_data; // @[ReservationStation.scala:281:44] wire [13:0] _dst_bits_start_T_8 = start_data; // @[ReservationStation.scala:281:44] assign _start_T_1 = _start_WIRE[13:0]; // @[ReservationStation.scala:281:44] assign start_data = _start_T_1; // @[ReservationStation.scala:281:44] assign _start_T_2 = _start_WIRE[14]; // @[ReservationStation.scala:281:44] assign start_garbage_bit = _start_T_2; // @[ReservationStation.scala:281:44] assign _start_T_3 = _start_WIRE[25:15]; // @[ReservationStation.scala:281:44] assign start_garbage = _start_T_3; // @[ReservationStation.scala:281:44] wire [2:0] _start_T_4 = _start_WIRE[28:26]; // @[ReservationStation.scala:281:44] wire [2:0] _start_WIRE_1 = _start_T_4; // @[ReservationStation.scala:281:44] assign _start_WIRE_2 = _start_WIRE_1; // @[ReservationStation.scala:281:44] assign start_norm_cmd = _start_WIRE_2; // @[ReservationStation.scala:281:44] assign _start_T_5 = _start_WIRE[29]; // @[ReservationStation.scala:281:44] assign start_read_full_acc_row = _start_T_5; // @[ReservationStation.scala:281:44] assign _start_T_6 = _start_WIRE[30]; // @[ReservationStation.scala:281:44] assign start_accumulate = _start_T_6; // @[ReservationStation.scala:281:44] assign _start_T_7 = _start_WIRE[31]; // @[ReservationStation.scala:281:44] assign start_is_acc_addr = _start_T_7; // @[ReservationStation.scala:281:44] wire _dst_bits_start_T_9 = _dst_bits_start_T_8 > 14'h2000; // @[ReservationStation.scala:284:36] wire [3:0][2:0] _GEN_49 = {{ld_pixel_repeats_0}, {ld_pixel_repeats_2}, {ld_pixel_repeats_1}, {ld_pixel_repeats_0}}; // @[ReservationStation.scala:169:29] wire [14:0] _GEN_50 = {12'h0, _GEN_49[id]}; // @[Mux.scala:126:16] wire [14:0] _dst_bits_start_underflow_T = _GEN_50 + 15'h2000; // @[LocalAddr.scala:86:35] wire [14:0] _GEN_51 = {1'h0, start_data}; // @[ReservationStation.scala:281:44] wire dst_bits_start_underflow = _GEN_51 < _dst_bits_start_underflow_T; // @[LocalAddr.scala:86:{26,35}] wire [13:0] _dst_bits_start_result_data_T_2; // @[LocalAddr.scala:89:23] wire [13:0] dst_bits_start_result_data; // @[LocalAddr.scala:88:26] wire [14:0] _GEN_52 = _GEN_51 - _GEN_50; // @[LocalAddr.scala:86:{26,35}, :89:47] wire [14:0] _dst_bits_start_result_data_T; // @[LocalAddr.scala:89:47] assign _dst_bits_start_result_data_T = _GEN_52; // @[LocalAddr.scala:89:47] wire [14:0] _dst_bits_start_result_data_T_3; // @[LocalAddr.scala:89:47] assign _dst_bits_start_result_data_T_3 = _GEN_52; // @[LocalAddr.scala:89:47] wire [13:0] _dst_bits_start_result_data_T_1 = _dst_bits_start_result_data_T[13:0]; // @[LocalAddr.scala:89:47] assign _dst_bits_start_result_data_T_2 = dst_bits_start_underflow ? 14'h2000 : _dst_bits_start_result_data_T_1; // @[LocalAddr.scala:86:26, :89:{23,47}] assign dst_bits_start_result_data = _dst_bits_start_result_data_T_2; // @[LocalAddr.scala:88:26, :89:23] wire [3:0] _dst_bits_start_underflow_T_1 = {1'h0, _GEN_49[id]}; // @[Mux.scala:126:16] wire dst_bits_start_underflow_1 = start_data < {10'h0, _dst_bits_start_underflow_T_1}; // @[ReservationStation.scala:281:44] wire [13:0] _dst_bits_start_result_data_T_5; // @[LocalAddr.scala:89:23] wire [13:0] dst_bits_start_result_1_data; // @[LocalAddr.scala:88:26] wire [13:0] _dst_bits_start_result_data_T_4 = _dst_bits_start_result_data_T_3[13:0]; // @[LocalAddr.scala:89:47] assign _dst_bits_start_result_data_T_5 = dst_bits_start_underflow_1 ? 14'h0 : _dst_bits_start_result_data_T_4; // @[LocalAddr.scala:86:26, :89:{23,47}] assign dst_bits_start_result_1_data = _dst_bits_start_result_data_T_5; // @[LocalAddr.scala:88:26, :89:23] wire _dst_bits_start_T_10_is_acc_addr = _dst_bits_start_T_9 ? dst_bits_start_result_is_acc_addr : dst_bits_start_result_1_is_acc_addr; // @[ReservationStation.scala:284:{14,36}] wire _dst_bits_start_T_10_accumulate = _dst_bits_start_T_9 ? dst_bits_start_result_accumulate : dst_bits_start_result_1_accumulate; // @[ReservationStation.scala:284:{14,36}] wire _dst_bits_start_T_10_read_full_acc_row = _dst_bits_start_T_9 ? dst_bits_start_result_read_full_acc_row : dst_bits_start_result_1_read_full_acc_row; // @[ReservationStation.scala:284:{14,36}] wire [2:0] _dst_bits_start_T_10_norm_cmd = _dst_bits_start_T_9 ? dst_bits_start_result_norm_cmd : dst_bits_start_result_1_norm_cmd; // @[ReservationStation.scala:284:{14,36}] wire [10:0] _dst_bits_start_T_10_garbage = _dst_bits_start_T_9 ? dst_bits_start_result_garbage : dst_bits_start_result_1_garbage; // @[ReservationStation.scala:284:{14,36}] wire _dst_bits_start_T_10_garbage_bit = _dst_bits_start_T_9 ? dst_bits_start_result_garbage_bit : dst_bits_start_result_1_garbage_bit; // @[ReservationStation.scala:284:{14,36}] wire [13:0] _dst_bits_start_T_10_data = _dst_bits_start_T_9 ? dst_bits_start_result_data : dst_bits_start_result_1_data; // @[ReservationStation.scala:284:{14,36}] wire _dst_bits_start_T_11_is_acc_addr = start_is_acc_addr ? start_is_acc_addr : _dst_bits_start_T_10_is_acc_addr; // @[ReservationStation.scala:281:44, :283:30, :284:14] wire _dst_bits_start_T_11_accumulate = start_is_acc_addr ? start_accumulate : _dst_bits_start_T_10_accumulate; // @[ReservationStation.scala:281:44, :283:30, :284:14] wire _dst_bits_start_T_11_read_full_acc_row = start_is_acc_addr ? start_read_full_acc_row : _dst_bits_start_T_10_read_full_acc_row; // @[ReservationStation.scala:281:44, :283:30, :284:14] wire [2:0] _dst_bits_start_T_11_norm_cmd = start_is_acc_addr ? start_norm_cmd : _dst_bits_start_T_10_norm_cmd; // @[ReservationStation.scala:281:44, :283:30, :284:14] wire [10:0] _dst_bits_start_T_11_garbage = start_is_acc_addr ? start_garbage : _dst_bits_start_T_10_garbage; // @[ReservationStation.scala:281:44, :283:30, :284:14] wire _dst_bits_start_T_11_garbage_bit = start_is_acc_addr ? start_garbage_bit : _dst_bits_start_T_10_garbage_bit; // @[ReservationStation.scala:281:44, :283:30, :284:14] wire [13:0] _dst_bits_start_T_11_data = start_is_acc_addr ? start_data : _dst_bits_start_T_10_data; // @[ReservationStation.scala:281:44, :283:30, :284:14] assign dst_bits_start_is_acc_addr = _T_4831 ? _dst_bits_start_WIRE_is_acc_addr : _dst_bits_start_T_11_is_acc_addr; // @[ReservationStation.scala:202:19, :216:24, :262:{20,46}, :263:34, :283:{24,30}] assign dst_bits_start_accumulate = _T_4831 ? _dst_bits_start_WIRE_accumulate : _dst_bits_start_T_11_accumulate; // @[ReservationStation.scala:202:19, :216:24, :262:{20,46}, :263:34, :283:{24,30}] assign dst_bits_start_read_full_acc_row = _T_4831 ? _dst_bits_start_WIRE_read_full_acc_row : _dst_bits_start_T_11_read_full_acc_row; // @[ReservationStation.scala:202:19, :216:24, :262:{20,46}, :263:34, :283:{24,30}] assign dst_bits_start_norm_cmd = _T_4831 ? _dst_bits_start_WIRE_norm_cmd : _dst_bits_start_T_11_norm_cmd; // @[ReservationStation.scala:202:19, :216:24, :262:{20,46}, :263:34, :283:{24,30}] assign dst_bits_start_garbage = _T_4831 ? _dst_bits_start_WIRE_garbage : _dst_bits_start_T_11_garbage; // @[ReservationStation.scala:202:19, :216:24, :262:{20,46}, :263:34, :283:{24,30}] assign dst_bits_start_garbage_bit = _T_4831 ? _dst_bits_start_WIRE_garbage_bit : _dst_bits_start_T_11_garbage_bit; // @[ReservationStation.scala:202:19, :216:24, :262:{20,46}, :263:34, :283:{24,30}] assign dst_bits_start_data = _T_4831 ? _dst_bits_start_WIRE_data : _dst_bits_start_T_11_data; // @[ReservationStation.scala:202:19, :216:24, :262:{20,46}, :263:34, :283:{24,30}] wire [13:0] dst_bits_end_result_1_data; // @[LocalAddr.scala:50:26] wire [19:0] _GEN_53 = {6'h0, dst_bits_start_data} + {1'h0, total_mvin_rows}; // @[ReservationStation.scala:202:19, :277:64] wire [19:0] _dst_bits_end_result_data_T_2; // @[LocalAddr.scala:51:25] assign _dst_bits_end_result_data_T_2 = _GEN_53; // @[LocalAddr.scala:51:25] wire [19:0] dst_bits_wraps_around_sum_1; // @[LocalAddr.scala:71:20] assign dst_bits_wraps_around_sum_1 = _GEN_53; // @[LocalAddr.scala:51:25, :71:20] wire [18:0] _dst_bits_end_result_data_T_3 = _dst_bits_end_result_data_T_2[18:0]; // @[LocalAddr.scala:51:25] assign dst_bits_end_result_1_data = _dst_bits_end_result_data_T_3[13:0]; // @[LocalAddr.scala:50:26, :51:{17,25}] assign dst_bits_end_is_acc_addr = _T_4831 ? dst_bits_end_result_is_acc_addr : dst_bits_end_result_1_is_acc_addr; // @[ReservationStation.scala:202:19, :216:24, :263:34, :265:20, :291:20] assign dst_bits_end_accumulate = _T_4831 ? dst_bits_end_result_accumulate : dst_bits_end_result_1_accumulate; // @[ReservationStation.scala:202:19, :216:24, :263:34, :265:20, :291:20] assign dst_bits_end_read_full_acc_row = _T_4831 ? dst_bits_end_result_read_full_acc_row : dst_bits_end_result_1_read_full_acc_row; // @[ReservationStation.scala:202:19, :216:24, :263:34, :265:20, :291:20] assign dst_bits_end_norm_cmd = _T_4831 ? dst_bits_end_result_norm_cmd : dst_bits_end_result_1_norm_cmd; // @[ReservationStation.scala:202:19, :216:24, :263:34, :265:20, :291:20] assign dst_bits_end_garbage = _T_4831 ? dst_bits_end_result_garbage : dst_bits_end_result_1_garbage; // @[ReservationStation.scala:202:19, :216:24, :263:34, :265:20, :291:20] assign dst_bits_end_garbage_bit = _T_4831 ? dst_bits_end_result_garbage_bit : dst_bits_end_result_1_garbage_bit; // @[ReservationStation.scala:202:19, :216:24, :263:34, :265:20, :291:20] assign dst_bits_end_data = _T_4831 ? dst_bits_end_result_data : dst_bits_end_result_1_data; // @[ReservationStation.scala:202:19, :216:24, :263:34, :265:20, :291:20] wire _dst_bits_wraps_around_overflow_T_2 = dst_bits_wraps_around_sum_1[12]; // @[LocalAddr.scala:71:20, :73:40] wire _dst_bits_wraps_around_overflow_T_3 = dst_bits_wraps_around_sum_1[14]; // @[LocalAddr.scala:71:20, :73:58] wire dst_bits_wraps_around_overflow_1 = dst_bits_start_is_acc_addr ? _dst_bits_wraps_around_overflow_T_2 : _dst_bits_wraps_around_overflow_T_3; // @[ReservationStation.scala:202:19] wire [13:0] _dst_bits_wraps_around_result_data_T_1; // @[LocalAddr.scala:76:23] wire [13:0] dst_bits_wraps_around_result_1_data; // @[LocalAddr.scala:75:26] assign _dst_bits_wraps_around_result_data_T_1 = dst_bits_wraps_around_sum_1[13:0]; // @[LocalAddr.scala:71:20, :76:23] assign dst_bits_wraps_around_result_1_data = _dst_bits_wraps_around_result_data_T_1; // @[LocalAddr.scala:75:26, :76:23] assign dst_bits_wraps_around = _T_4831 ? dst_bits_wraps_around_overflow : dst_bits_wraps_around_overflow_1; // @[ReservationStation.scala:202:19, :216:24, :263:34, :266:29, :292:29] wire _is_load_T_2 = _is_load_T | _is_load_T_1; // @[ReservationStation.scala:295:{25,38,47}] wire _is_load_T_4 = _is_load_T_2 | _is_load_T_3; // @[ReservationStation.scala:295:{38,61,70}] wire _is_load_T_6 = config_cmd_type == 2'h1; // @[ReservationStation.scala:189:34, :295:128] wire _is_load_T_7 = _is_load_T_5 & _is_load_T_6; // @[ReservationStation.scala:295:{94,109,128}] wire is_load = _is_load_T_4 | _is_load_T_7; // @[ReservationStation.scala:295:{61,84,109}] wire _is_ex_T_1 = _is_ex_T | funct_is_compute; // @[ReservationStation.scala:188:59, :296:{23,39}] wire _is_ex_T_3 = config_cmd_type == 2'h0; // @[ReservationStation.scala:189:34, :296:103] wire _is_ex_T_4 = _is_ex_T_2 & _is_ex_T_3; // @[ReservationStation.scala:296:{69,84,103}] wire is_ex = _is_ex_T_1 | _is_ex_T_4; // @[ReservationStation.scala:296:{39,59,84}] wire _is_store_T_2 = config_cmd_type == 2'h2; // @[ReservationStation.scala:189:34, :297:85] wire _is_store_T_3 = &config_cmd_type; // @[ReservationStation.scala:189:34, :297:121] wire _is_store_T_4 = _is_store_T_2 | _is_store_T_3; // @[ReservationStation.scala:297:{85,102,121}] wire _is_store_T_5 = _is_store_T_1 & _is_store_T_4; // @[ReservationStation.scala:297:{50,65,102}] wire is_store = _is_store_T | _is_store_T_5; // @[ReservationStation.scala:297:{26,40,65}] wire _is_norm_T_1 = &config_cmd_type; // @[ReservationStation.scala:189:34, :297:121, :298:59] wire is_norm = _is_norm_T & _is_norm_T_1; // @[ReservationStation.scala:298:{25,40,59}] wire [1:0] _new_entry_q_T_1 = {is_store, 1'h0}; // @[Mux.scala:30:73] wire [1:0] _new_entry_q_T_3 = _new_entry_q_T_1; // @[Mux.scala:30:73] wire [1:0] _new_entry_q_T_2 = {1'h0, is_ex}; // @[Mux.scala:30:73] wire [1:0] _new_entry_q_T_4 = _new_entry_q_T_3 | _new_entry_q_T_2; // @[Mux.scala:30:73] assign _new_entry_q_WIRE = _new_entry_q_T_4; // @[Mux.scala:30:73] assign new_entry_q = _new_entry_q_WIRE; // @[Mux.scala:30:73] wire not_config = ~new_entry_is_config; // @[ReservationStation.scala:171:23, :309:22] wire _T_58 = entries_ex_0_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23] wire _T_2144 = new_entry_opa_bits_start_is_acc_addr & new_entry_opa_bits_start_accumulate; // @[ReservationStation.scala:171:23] wire _T_115 = entries_ex_0_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23] wire _T_176 = entries_ex_1_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23] wire _T_233 = entries_ex_1_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23] wire _T_294 = entries_ex_2_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23] wire _T_351 = entries_ex_2_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23] wire _T_412 = entries_ex_3_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23] wire _T_469 = entries_ex_3_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23] wire _T_530 = entries_ex_4_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23] wire _T_587 = entries_ex_4_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23] wire _T_648 = entries_ex_5_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23] wire _T_705 = entries_ex_5_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23] wire _T_766 = entries_ex_6_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23] wire _T_823 = entries_ex_6_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23] wire _T_884 = entries_ex_7_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23] wire _T_941 = entries_ex_7_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23] wire _T_1002 = entries_ex_8_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23] wire _T_1059 = entries_ex_8_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23] wire _T_1120 = entries_ex_9_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23] wire _T_1177 = entries_ex_9_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23] wire _T_1238 = entries_ex_10_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23] wire _T_1295 = entries_ex_10_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23] wire _T_1356 = entries_ex_11_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23] wire _T_1413 = entries_ex_11_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23] wire _T_1474 = entries_ex_12_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23] wire _T_1531 = entries_ex_12_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23] wire _T_1592 = entries_ex_13_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23] wire _T_1649 = entries_ex_13_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23] wire _T_1710 = entries_ex_14_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23] wire _T_1767 = entries_ex_14_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23] wire _T_1828 = entries_ex_15_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23] wire _T_1885 = entries_ex_15_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23] wire _T_1946 = entries_st_0_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:119:23, :171:23] wire _T_2005 = entries_st_1_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:119:23, :171:23] wire _T_2064 = entries_st_2_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:119:23, :171:23] wire _T_2123 = entries_st_3_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:119:23, :171:23] wire _T_2182 = entries_ld_0_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23, :171:23] wire _T_3344 = new_entry_opa_bits_start_is_acc_addr & new_entry_opa_bits_start_accumulate; // @[ReservationStation.scala:171:23] wire _T_2265 = entries_ld_0_bits_opa_bits_start_is_acc_addr & entries_ld_0_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:117:23] wire _T_2238 = entries_ld_0_bits_opa_bits_start_is_acc_addr == new_entry_opb_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23, :171:23] wire _T_3071 = new_entry_opb_bits_start_is_acc_addr & new_entry_opb_bits_start_accumulate; // @[ReservationStation.scala:171:23] wire _T_2298 = entries_ld_1_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23, :171:23] wire _T_2381 = entries_ld_1_bits_opa_bits_start_is_acc_addr & entries_ld_1_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:117:23] wire _T_2354 = entries_ld_1_bits_opa_bits_start_is_acc_addr == new_entry_opb_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23, :171:23] wire _T_2414 = entries_ld_2_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23, :171:23] wire _T_2497 = entries_ld_2_bits_opa_bits_start_is_acc_addr & entries_ld_2_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:117:23] wire _T_2470 = entries_ld_2_bits_opa_bits_start_is_acc_addr == new_entry_opb_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23, :171:23] wire _T_2530 = entries_ld_3_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23, :171:23] wire _T_2613 = entries_ld_3_bits_opa_bits_start_is_acc_addr & entries_ld_3_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:117:23] wire _T_2586 = entries_ld_3_bits_opa_bits_start_is_acc_addr == new_entry_opb_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23, :171:23] wire _T_2646 = entries_ld_4_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23, :171:23] wire _T_2729 = entries_ld_4_bits_opa_bits_start_is_acc_addr & entries_ld_4_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:117:23] wire _T_2702 = entries_ld_4_bits_opa_bits_start_is_acc_addr == new_entry_opb_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23, :171:23] wire _T_2762 = entries_ld_5_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23, :171:23] wire _T_2845 = entries_ld_5_bits_opa_bits_start_is_acc_addr & entries_ld_5_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:117:23] wire _T_2818 = entries_ld_5_bits_opa_bits_start_is_acc_addr == new_entry_opb_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23, :171:23] wire _T_2878 = entries_ld_6_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23, :171:23] wire _T_2961 = entries_ld_6_bits_opa_bits_start_is_acc_addr & entries_ld_6_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:117:23] wire _T_2934 = entries_ld_6_bits_opa_bits_start_is_acc_addr == new_entry_opb_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23, :171:23] wire _T_2994 = entries_ld_7_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23, :171:23] wire _T_3077 = entries_ld_7_bits_opa_bits_start_is_acc_addr & entries_ld_7_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:117:23] wire _T_3050 = entries_ld_7_bits_opa_bits_start_is_acc_addr == new_entry_opb_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23, :171:23] wire _T_3143 = entries_st_0_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:119:23, :171:23] wire _T_3203 = entries_st_1_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:119:23, :171:23] wire _T_3263 = entries_st_2_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:119:23, :171:23] wire _T_3323 = entries_st_3_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:119:23, :171:23] wire _T_3382 = entries_ld_0_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23, :171:23] wire _T_4776 = new_entry_opa_bits_start_is_acc_addr & new_entry_opa_bits_start_accumulate; // @[ReservationStation.scala:171:23] wire _T_3441 = entries_ld_1_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23, :171:23] wire _T_3500 = entries_ld_2_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23, :171:23] wire _T_3559 = entries_ld_3_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23, :171:23] wire _T_3618 = entries_ld_4_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23, :171:23] wire _T_3677 = entries_ld_5_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23, :171:23] wire _T_3736 = entries_ld_6_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23, :171:23] wire _T_3795 = entries_ld_7_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23, :171:23] assign new_entry_deps_ld_0 = is_load ? entries_ld_0_valid & ~entries_ld_0_bits_issued : is_ex ? entries_ld_0_valid & entries_ld_0_bits_opa_valid & not_config & ((_T_2182 & (entries_ld_0_bits_opa_bits_start_is_acc_addr ? entries_ld_0_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ld_0_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ld_0_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ld_0_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ld_0_bits_opa_bits_end_data) | entries_ld_0_bits_opa_bits_wraps_around) | _T_2182 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ld_0_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ld_0_bits_opa_bits_start_data) & (entries_ld_0_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ld_0_bits_opa_bits_start_is_acc_addr ? entries_ld_0_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ld_0_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_3344 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | _T_2265 & entries_ld_0_bits_opa_bits_start_read_full_acc_row & (&entries_ld_0_bits_opa_bits_start_data) & entries_ld_0_bits_opa_bits_start_garbage_bit) | (_T_2238 & (entries_ld_0_bits_opa_bits_start_is_acc_addr ? entries_ld_0_bits_opa_bits_start_data[11:0] <= new_entry_opb_bits_start_data[11:0] : entries_ld_0_bits_opa_bits_start_data <= new_entry_opb_bits_start_data) & (new_entry_opb_bits_start_is_acc_addr == entries_ld_0_bits_opa_bits_end_is_acc_addr & (new_entry_opb_bits_start_is_acc_addr ? new_entry_opb_bits_start_data[11:0] < entries_ld_0_bits_opa_bits_end_data[11:0] : new_entry_opb_bits_start_data < entries_ld_0_bits_opa_bits_end_data) | entries_ld_0_bits_opa_bits_wraps_around) | _T_2238 & (new_entry_opb_bits_start_is_acc_addr ? new_entry_opb_bits_start_data[11:0] <= entries_ld_0_bits_opa_bits_start_data[11:0] : new_entry_opb_bits_start_data <= entries_ld_0_bits_opa_bits_start_data) & (entries_ld_0_bits_opa_bits_start_is_acc_addr == new_entry_opb_bits_end_is_acc_addr & (entries_ld_0_bits_opa_bits_start_is_acc_addr ? entries_ld_0_bits_opa_bits_start_data[11:0] < new_entry_opb_bits_end_data[11:0] : entries_ld_0_bits_opa_bits_start_data < new_entry_opb_bits_end_data) | new_entry_opb_bits_wraps_around)) & ~(_T_3071 & new_entry_opb_bits_start_read_full_acc_row & (&new_entry_opb_bits_start_data) & new_entry_opb_bits_start_garbage_bit | _T_2265 & entries_ld_0_bits_opa_bits_start_read_full_acc_row & (&entries_ld_0_bits_opa_bits_start_data) & entries_ld_0_bits_opa_bits_start_garbage_bit)) : entries_ld_0_valid & entries_ld_0_bits_opa_valid & not_config & (_T_3382 & (entries_ld_0_bits_opa_bits_start_is_acc_addr ? entries_ld_0_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ld_0_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ld_0_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ld_0_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ld_0_bits_opa_bits_end_data) | entries_ld_0_bits_opa_bits_wraps_around) | _T_3382 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ld_0_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ld_0_bits_opa_bits_start_data) & (entries_ld_0_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ld_0_bits_opa_bits_start_is_acc_addr ? entries_ld_0_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ld_0_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_4776 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ld_0_bits_opa_bits_start_is_acc_addr & entries_ld_0_bits_opa_bits_start_accumulate & entries_ld_0_bits_opa_bits_start_read_full_acc_row & (&entries_ld_0_bits_opa_bits_start_data) & entries_ld_0_bits_opa_bits_start_garbage_bit); // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :117:23, :171:23, :295:84, :296:59, :309:22, :310:20, :312:{25,66,69}, :320:24, :322:{25,66,86,100}, :323:54, :332:{25,66,86,100}] assign new_entry_deps_ld_1 = is_load ? entries_ld_1_valid & ~entries_ld_1_bits_issued : is_ex ? entries_ld_1_valid & entries_ld_1_bits_opa_valid & not_config & ((_T_2298 & (entries_ld_1_bits_opa_bits_start_is_acc_addr ? entries_ld_1_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ld_1_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ld_1_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ld_1_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ld_1_bits_opa_bits_end_data) | entries_ld_1_bits_opa_bits_wraps_around) | _T_2298 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ld_1_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ld_1_bits_opa_bits_start_data) & (entries_ld_1_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ld_1_bits_opa_bits_start_is_acc_addr ? entries_ld_1_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ld_1_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_3344 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | _T_2381 & entries_ld_1_bits_opa_bits_start_read_full_acc_row & (&entries_ld_1_bits_opa_bits_start_data) & entries_ld_1_bits_opa_bits_start_garbage_bit) | (_T_2354 & (entries_ld_1_bits_opa_bits_start_is_acc_addr ? entries_ld_1_bits_opa_bits_start_data[11:0] <= new_entry_opb_bits_start_data[11:0] : entries_ld_1_bits_opa_bits_start_data <= new_entry_opb_bits_start_data) & (new_entry_opb_bits_start_is_acc_addr == entries_ld_1_bits_opa_bits_end_is_acc_addr & (new_entry_opb_bits_start_is_acc_addr ? new_entry_opb_bits_start_data[11:0] < entries_ld_1_bits_opa_bits_end_data[11:0] : new_entry_opb_bits_start_data < entries_ld_1_bits_opa_bits_end_data) | entries_ld_1_bits_opa_bits_wraps_around) | _T_2354 & (new_entry_opb_bits_start_is_acc_addr ? new_entry_opb_bits_start_data[11:0] <= entries_ld_1_bits_opa_bits_start_data[11:0] : new_entry_opb_bits_start_data <= entries_ld_1_bits_opa_bits_start_data) & (entries_ld_1_bits_opa_bits_start_is_acc_addr == new_entry_opb_bits_end_is_acc_addr & (entries_ld_1_bits_opa_bits_start_is_acc_addr ? entries_ld_1_bits_opa_bits_start_data[11:0] < new_entry_opb_bits_end_data[11:0] : entries_ld_1_bits_opa_bits_start_data < new_entry_opb_bits_end_data) | new_entry_opb_bits_wraps_around)) & ~(_T_3071 & new_entry_opb_bits_start_read_full_acc_row & (&new_entry_opb_bits_start_data) & new_entry_opb_bits_start_garbage_bit | _T_2381 & entries_ld_1_bits_opa_bits_start_read_full_acc_row & (&entries_ld_1_bits_opa_bits_start_data) & entries_ld_1_bits_opa_bits_start_garbage_bit)) : entries_ld_1_valid & entries_ld_1_bits_opa_valid & not_config & (_T_3441 & (entries_ld_1_bits_opa_bits_start_is_acc_addr ? entries_ld_1_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ld_1_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ld_1_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ld_1_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ld_1_bits_opa_bits_end_data) | entries_ld_1_bits_opa_bits_wraps_around) | _T_3441 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ld_1_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ld_1_bits_opa_bits_start_data) & (entries_ld_1_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ld_1_bits_opa_bits_start_is_acc_addr ? entries_ld_1_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ld_1_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_4776 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ld_1_bits_opa_bits_start_is_acc_addr & entries_ld_1_bits_opa_bits_start_accumulate & entries_ld_1_bits_opa_bits_start_read_full_acc_row & (&entries_ld_1_bits_opa_bits_start_data) & entries_ld_1_bits_opa_bits_start_garbage_bit); // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :117:23, :171:23, :295:84, :296:59, :309:22, :310:20, :312:{25,66,69}, :320:24, :322:{25,66,86,100}, :323:54, :332:{25,66,86,100}] assign new_entry_deps_ld_2 = is_load ? entries_ld_2_valid & ~entries_ld_2_bits_issued : is_ex ? entries_ld_2_valid & entries_ld_2_bits_opa_valid & not_config & ((_T_2414 & (entries_ld_2_bits_opa_bits_start_is_acc_addr ? entries_ld_2_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ld_2_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ld_2_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ld_2_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ld_2_bits_opa_bits_end_data) | entries_ld_2_bits_opa_bits_wraps_around) | _T_2414 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ld_2_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ld_2_bits_opa_bits_start_data) & (entries_ld_2_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ld_2_bits_opa_bits_start_is_acc_addr ? entries_ld_2_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ld_2_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_3344 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | _T_2497 & entries_ld_2_bits_opa_bits_start_read_full_acc_row & (&entries_ld_2_bits_opa_bits_start_data) & entries_ld_2_bits_opa_bits_start_garbage_bit) | (_T_2470 & (entries_ld_2_bits_opa_bits_start_is_acc_addr ? entries_ld_2_bits_opa_bits_start_data[11:0] <= new_entry_opb_bits_start_data[11:0] : entries_ld_2_bits_opa_bits_start_data <= new_entry_opb_bits_start_data) & (new_entry_opb_bits_start_is_acc_addr == entries_ld_2_bits_opa_bits_end_is_acc_addr & (new_entry_opb_bits_start_is_acc_addr ? new_entry_opb_bits_start_data[11:0] < entries_ld_2_bits_opa_bits_end_data[11:0] : new_entry_opb_bits_start_data < entries_ld_2_bits_opa_bits_end_data) | entries_ld_2_bits_opa_bits_wraps_around) | _T_2470 & (new_entry_opb_bits_start_is_acc_addr ? new_entry_opb_bits_start_data[11:0] <= entries_ld_2_bits_opa_bits_start_data[11:0] : new_entry_opb_bits_start_data <= entries_ld_2_bits_opa_bits_start_data) & (entries_ld_2_bits_opa_bits_start_is_acc_addr == new_entry_opb_bits_end_is_acc_addr & (entries_ld_2_bits_opa_bits_start_is_acc_addr ? entries_ld_2_bits_opa_bits_start_data[11:0] < new_entry_opb_bits_end_data[11:0] : entries_ld_2_bits_opa_bits_start_data < new_entry_opb_bits_end_data) | new_entry_opb_bits_wraps_around)) & ~(_T_3071 & new_entry_opb_bits_start_read_full_acc_row & (&new_entry_opb_bits_start_data) & new_entry_opb_bits_start_garbage_bit | _T_2497 & entries_ld_2_bits_opa_bits_start_read_full_acc_row & (&entries_ld_2_bits_opa_bits_start_data) & entries_ld_2_bits_opa_bits_start_garbage_bit)) : entries_ld_2_valid & entries_ld_2_bits_opa_valid & not_config & (_T_3500 & (entries_ld_2_bits_opa_bits_start_is_acc_addr ? entries_ld_2_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ld_2_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ld_2_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ld_2_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ld_2_bits_opa_bits_end_data) | entries_ld_2_bits_opa_bits_wraps_around) | _T_3500 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ld_2_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ld_2_bits_opa_bits_start_data) & (entries_ld_2_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ld_2_bits_opa_bits_start_is_acc_addr ? entries_ld_2_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ld_2_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_4776 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ld_2_bits_opa_bits_start_is_acc_addr & entries_ld_2_bits_opa_bits_start_accumulate & entries_ld_2_bits_opa_bits_start_read_full_acc_row & (&entries_ld_2_bits_opa_bits_start_data) & entries_ld_2_bits_opa_bits_start_garbage_bit); // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :117:23, :171:23, :295:84, :296:59, :309:22, :310:20, :312:{25,66,69}, :320:24, :322:{25,66,86,100}, :323:54, :332:{25,66,86,100}] assign new_entry_deps_ld_3 = is_load ? entries_ld_3_valid & ~entries_ld_3_bits_issued : is_ex ? entries_ld_3_valid & entries_ld_3_bits_opa_valid & not_config & ((_T_2530 & (entries_ld_3_bits_opa_bits_start_is_acc_addr ? entries_ld_3_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ld_3_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ld_3_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ld_3_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ld_3_bits_opa_bits_end_data) | entries_ld_3_bits_opa_bits_wraps_around) | _T_2530 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ld_3_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ld_3_bits_opa_bits_start_data) & (entries_ld_3_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ld_3_bits_opa_bits_start_is_acc_addr ? entries_ld_3_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ld_3_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_3344 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | _T_2613 & entries_ld_3_bits_opa_bits_start_read_full_acc_row & (&entries_ld_3_bits_opa_bits_start_data) & entries_ld_3_bits_opa_bits_start_garbage_bit) | (_T_2586 & (entries_ld_3_bits_opa_bits_start_is_acc_addr ? entries_ld_3_bits_opa_bits_start_data[11:0] <= new_entry_opb_bits_start_data[11:0] : entries_ld_3_bits_opa_bits_start_data <= new_entry_opb_bits_start_data) & (new_entry_opb_bits_start_is_acc_addr == entries_ld_3_bits_opa_bits_end_is_acc_addr & (new_entry_opb_bits_start_is_acc_addr ? new_entry_opb_bits_start_data[11:0] < entries_ld_3_bits_opa_bits_end_data[11:0] : new_entry_opb_bits_start_data < entries_ld_3_bits_opa_bits_end_data) | entries_ld_3_bits_opa_bits_wraps_around) | _T_2586 & (new_entry_opb_bits_start_is_acc_addr ? new_entry_opb_bits_start_data[11:0] <= entries_ld_3_bits_opa_bits_start_data[11:0] : new_entry_opb_bits_start_data <= entries_ld_3_bits_opa_bits_start_data) & (entries_ld_3_bits_opa_bits_start_is_acc_addr == new_entry_opb_bits_end_is_acc_addr & (entries_ld_3_bits_opa_bits_start_is_acc_addr ? entries_ld_3_bits_opa_bits_start_data[11:0] < new_entry_opb_bits_end_data[11:0] : entries_ld_3_bits_opa_bits_start_data < new_entry_opb_bits_end_data) | new_entry_opb_bits_wraps_around)) & ~(_T_3071 & new_entry_opb_bits_start_read_full_acc_row & (&new_entry_opb_bits_start_data) & new_entry_opb_bits_start_garbage_bit | _T_2613 & entries_ld_3_bits_opa_bits_start_read_full_acc_row & (&entries_ld_3_bits_opa_bits_start_data) & entries_ld_3_bits_opa_bits_start_garbage_bit)) : entries_ld_3_valid & entries_ld_3_bits_opa_valid & not_config & (_T_3559 & (entries_ld_3_bits_opa_bits_start_is_acc_addr ? entries_ld_3_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ld_3_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ld_3_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ld_3_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ld_3_bits_opa_bits_end_data) | entries_ld_3_bits_opa_bits_wraps_around) | _T_3559 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ld_3_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ld_3_bits_opa_bits_start_data) & (entries_ld_3_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ld_3_bits_opa_bits_start_is_acc_addr ? entries_ld_3_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ld_3_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_4776 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ld_3_bits_opa_bits_start_is_acc_addr & entries_ld_3_bits_opa_bits_start_accumulate & entries_ld_3_bits_opa_bits_start_read_full_acc_row & (&entries_ld_3_bits_opa_bits_start_data) & entries_ld_3_bits_opa_bits_start_garbage_bit); // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :117:23, :171:23, :295:84, :296:59, :309:22, :310:20, :312:{25,66,69}, :320:24, :322:{25,66,86,100}, :323:54, :332:{25,66,86,100}] assign new_entry_deps_ld_4 = is_load ? entries_ld_4_valid & ~entries_ld_4_bits_issued : is_ex ? entries_ld_4_valid & entries_ld_4_bits_opa_valid & not_config & ((_T_2646 & (entries_ld_4_bits_opa_bits_start_is_acc_addr ? entries_ld_4_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ld_4_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ld_4_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ld_4_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ld_4_bits_opa_bits_end_data) | entries_ld_4_bits_opa_bits_wraps_around) | _T_2646 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ld_4_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ld_4_bits_opa_bits_start_data) & (entries_ld_4_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ld_4_bits_opa_bits_start_is_acc_addr ? entries_ld_4_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ld_4_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_3344 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | _T_2729 & entries_ld_4_bits_opa_bits_start_read_full_acc_row & (&entries_ld_4_bits_opa_bits_start_data) & entries_ld_4_bits_opa_bits_start_garbage_bit) | (_T_2702 & (entries_ld_4_bits_opa_bits_start_is_acc_addr ? entries_ld_4_bits_opa_bits_start_data[11:0] <= new_entry_opb_bits_start_data[11:0] : entries_ld_4_bits_opa_bits_start_data <= new_entry_opb_bits_start_data) & (new_entry_opb_bits_start_is_acc_addr == entries_ld_4_bits_opa_bits_end_is_acc_addr & (new_entry_opb_bits_start_is_acc_addr ? new_entry_opb_bits_start_data[11:0] < entries_ld_4_bits_opa_bits_end_data[11:0] : new_entry_opb_bits_start_data < entries_ld_4_bits_opa_bits_end_data) | entries_ld_4_bits_opa_bits_wraps_around) | _T_2702 & (new_entry_opb_bits_start_is_acc_addr ? new_entry_opb_bits_start_data[11:0] <= entries_ld_4_bits_opa_bits_start_data[11:0] : new_entry_opb_bits_start_data <= entries_ld_4_bits_opa_bits_start_data) & (entries_ld_4_bits_opa_bits_start_is_acc_addr == new_entry_opb_bits_end_is_acc_addr & (entries_ld_4_bits_opa_bits_start_is_acc_addr ? entries_ld_4_bits_opa_bits_start_data[11:0] < new_entry_opb_bits_end_data[11:0] : entries_ld_4_bits_opa_bits_start_data < new_entry_opb_bits_end_data) | new_entry_opb_bits_wraps_around)) & ~(_T_3071 & new_entry_opb_bits_start_read_full_acc_row & (&new_entry_opb_bits_start_data) & new_entry_opb_bits_start_garbage_bit | _T_2729 & entries_ld_4_bits_opa_bits_start_read_full_acc_row & (&entries_ld_4_bits_opa_bits_start_data) & entries_ld_4_bits_opa_bits_start_garbage_bit)) : entries_ld_4_valid & entries_ld_4_bits_opa_valid & not_config & (_T_3618 & (entries_ld_4_bits_opa_bits_start_is_acc_addr ? entries_ld_4_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ld_4_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ld_4_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ld_4_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ld_4_bits_opa_bits_end_data) | entries_ld_4_bits_opa_bits_wraps_around) | _T_3618 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ld_4_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ld_4_bits_opa_bits_start_data) & (entries_ld_4_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ld_4_bits_opa_bits_start_is_acc_addr ? entries_ld_4_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ld_4_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_4776 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ld_4_bits_opa_bits_start_is_acc_addr & entries_ld_4_bits_opa_bits_start_accumulate & entries_ld_4_bits_opa_bits_start_read_full_acc_row & (&entries_ld_4_bits_opa_bits_start_data) & entries_ld_4_bits_opa_bits_start_garbage_bit); // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :117:23, :171:23, :295:84, :296:59, :309:22, :310:20, :312:{25,66,69}, :320:24, :322:{25,66,86,100}, :323:54, :332:{25,66,86,100}] assign new_entry_deps_ld_5 = is_load ? entries_ld_5_valid & ~entries_ld_5_bits_issued : is_ex ? entries_ld_5_valid & entries_ld_5_bits_opa_valid & not_config & ((_T_2762 & (entries_ld_5_bits_opa_bits_start_is_acc_addr ? entries_ld_5_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ld_5_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ld_5_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ld_5_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ld_5_bits_opa_bits_end_data) | entries_ld_5_bits_opa_bits_wraps_around) | _T_2762 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ld_5_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ld_5_bits_opa_bits_start_data) & (entries_ld_5_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ld_5_bits_opa_bits_start_is_acc_addr ? entries_ld_5_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ld_5_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_3344 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | _T_2845 & entries_ld_5_bits_opa_bits_start_read_full_acc_row & (&entries_ld_5_bits_opa_bits_start_data) & entries_ld_5_bits_opa_bits_start_garbage_bit) | (_T_2818 & (entries_ld_5_bits_opa_bits_start_is_acc_addr ? entries_ld_5_bits_opa_bits_start_data[11:0] <= new_entry_opb_bits_start_data[11:0] : entries_ld_5_bits_opa_bits_start_data <= new_entry_opb_bits_start_data) & (new_entry_opb_bits_start_is_acc_addr == entries_ld_5_bits_opa_bits_end_is_acc_addr & (new_entry_opb_bits_start_is_acc_addr ? new_entry_opb_bits_start_data[11:0] < entries_ld_5_bits_opa_bits_end_data[11:0] : new_entry_opb_bits_start_data < entries_ld_5_bits_opa_bits_end_data) | entries_ld_5_bits_opa_bits_wraps_around) | _T_2818 & (new_entry_opb_bits_start_is_acc_addr ? new_entry_opb_bits_start_data[11:0] <= entries_ld_5_bits_opa_bits_start_data[11:0] : new_entry_opb_bits_start_data <= entries_ld_5_bits_opa_bits_start_data) & (entries_ld_5_bits_opa_bits_start_is_acc_addr == new_entry_opb_bits_end_is_acc_addr & (entries_ld_5_bits_opa_bits_start_is_acc_addr ? entries_ld_5_bits_opa_bits_start_data[11:0] < new_entry_opb_bits_end_data[11:0] : entries_ld_5_bits_opa_bits_start_data < new_entry_opb_bits_end_data) | new_entry_opb_bits_wraps_around)) & ~(_T_3071 & new_entry_opb_bits_start_read_full_acc_row & (&new_entry_opb_bits_start_data) & new_entry_opb_bits_start_garbage_bit | _T_2845 & entries_ld_5_bits_opa_bits_start_read_full_acc_row & (&entries_ld_5_bits_opa_bits_start_data) & entries_ld_5_bits_opa_bits_start_garbage_bit)) : entries_ld_5_valid & entries_ld_5_bits_opa_valid & not_config & (_T_3677 & (entries_ld_5_bits_opa_bits_start_is_acc_addr ? entries_ld_5_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ld_5_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ld_5_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ld_5_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ld_5_bits_opa_bits_end_data) | entries_ld_5_bits_opa_bits_wraps_around) | _T_3677 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ld_5_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ld_5_bits_opa_bits_start_data) & (entries_ld_5_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ld_5_bits_opa_bits_start_is_acc_addr ? entries_ld_5_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ld_5_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_4776 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ld_5_bits_opa_bits_start_is_acc_addr & entries_ld_5_bits_opa_bits_start_accumulate & entries_ld_5_bits_opa_bits_start_read_full_acc_row & (&entries_ld_5_bits_opa_bits_start_data) & entries_ld_5_bits_opa_bits_start_garbage_bit); // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :117:23, :171:23, :295:84, :296:59, :309:22, :310:20, :312:{25,66,69}, :320:24, :322:{25,66,86,100}, :323:54, :332:{25,66,86,100}] assign new_entry_deps_ld_6 = is_load ? entries_ld_6_valid & ~entries_ld_6_bits_issued : is_ex ? entries_ld_6_valid & entries_ld_6_bits_opa_valid & not_config & ((_T_2878 & (entries_ld_6_bits_opa_bits_start_is_acc_addr ? entries_ld_6_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ld_6_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ld_6_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ld_6_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ld_6_bits_opa_bits_end_data) | entries_ld_6_bits_opa_bits_wraps_around) | _T_2878 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ld_6_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ld_6_bits_opa_bits_start_data) & (entries_ld_6_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ld_6_bits_opa_bits_start_is_acc_addr ? entries_ld_6_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ld_6_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_3344 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | _T_2961 & entries_ld_6_bits_opa_bits_start_read_full_acc_row & (&entries_ld_6_bits_opa_bits_start_data) & entries_ld_6_bits_opa_bits_start_garbage_bit) | (_T_2934 & (entries_ld_6_bits_opa_bits_start_is_acc_addr ? entries_ld_6_bits_opa_bits_start_data[11:0] <= new_entry_opb_bits_start_data[11:0] : entries_ld_6_bits_opa_bits_start_data <= new_entry_opb_bits_start_data) & (new_entry_opb_bits_start_is_acc_addr == entries_ld_6_bits_opa_bits_end_is_acc_addr & (new_entry_opb_bits_start_is_acc_addr ? new_entry_opb_bits_start_data[11:0] < entries_ld_6_bits_opa_bits_end_data[11:0] : new_entry_opb_bits_start_data < entries_ld_6_bits_opa_bits_end_data) | entries_ld_6_bits_opa_bits_wraps_around) | _T_2934 & (new_entry_opb_bits_start_is_acc_addr ? new_entry_opb_bits_start_data[11:0] <= entries_ld_6_bits_opa_bits_start_data[11:0] : new_entry_opb_bits_start_data <= entries_ld_6_bits_opa_bits_start_data) & (entries_ld_6_bits_opa_bits_start_is_acc_addr == new_entry_opb_bits_end_is_acc_addr & (entries_ld_6_bits_opa_bits_start_is_acc_addr ? entries_ld_6_bits_opa_bits_start_data[11:0] < new_entry_opb_bits_end_data[11:0] : entries_ld_6_bits_opa_bits_start_data < new_entry_opb_bits_end_data) | new_entry_opb_bits_wraps_around)) & ~(_T_3071 & new_entry_opb_bits_start_read_full_acc_row & (&new_entry_opb_bits_start_data) & new_entry_opb_bits_start_garbage_bit | _T_2961 & entries_ld_6_bits_opa_bits_start_read_full_acc_row & (&entries_ld_6_bits_opa_bits_start_data) & entries_ld_6_bits_opa_bits_start_garbage_bit)) : entries_ld_6_valid & entries_ld_6_bits_opa_valid & not_config & (_T_3736 & (entries_ld_6_bits_opa_bits_start_is_acc_addr ? entries_ld_6_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ld_6_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ld_6_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ld_6_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ld_6_bits_opa_bits_end_data) | entries_ld_6_bits_opa_bits_wraps_around) | _T_3736 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ld_6_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ld_6_bits_opa_bits_start_data) & (entries_ld_6_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ld_6_bits_opa_bits_start_is_acc_addr ? entries_ld_6_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ld_6_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_4776 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ld_6_bits_opa_bits_start_is_acc_addr & entries_ld_6_bits_opa_bits_start_accumulate & entries_ld_6_bits_opa_bits_start_read_full_acc_row & (&entries_ld_6_bits_opa_bits_start_data) & entries_ld_6_bits_opa_bits_start_garbage_bit); // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :117:23, :171:23, :295:84, :296:59, :309:22, :310:20, :312:{25,66,69}, :320:24, :322:{25,66,86,100}, :323:54, :332:{25,66,86,100}] assign new_entry_deps_ld_7 = is_load ? entries_ld_7_valid & ~entries_ld_7_bits_issued : is_ex ? entries_ld_7_valid & entries_ld_7_bits_opa_valid & not_config & ((_T_2994 & (entries_ld_7_bits_opa_bits_start_is_acc_addr ? entries_ld_7_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ld_7_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ld_7_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ld_7_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ld_7_bits_opa_bits_end_data) | entries_ld_7_bits_opa_bits_wraps_around) | _T_2994 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ld_7_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ld_7_bits_opa_bits_start_data) & (entries_ld_7_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ld_7_bits_opa_bits_start_is_acc_addr ? entries_ld_7_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ld_7_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_3344 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | _T_3077 & entries_ld_7_bits_opa_bits_start_read_full_acc_row & (&entries_ld_7_bits_opa_bits_start_data) & entries_ld_7_bits_opa_bits_start_garbage_bit) | (_T_3050 & (entries_ld_7_bits_opa_bits_start_is_acc_addr ? entries_ld_7_bits_opa_bits_start_data[11:0] <= new_entry_opb_bits_start_data[11:0] : entries_ld_7_bits_opa_bits_start_data <= new_entry_opb_bits_start_data) & (new_entry_opb_bits_start_is_acc_addr == entries_ld_7_bits_opa_bits_end_is_acc_addr & (new_entry_opb_bits_start_is_acc_addr ? new_entry_opb_bits_start_data[11:0] < entries_ld_7_bits_opa_bits_end_data[11:0] : new_entry_opb_bits_start_data < entries_ld_7_bits_opa_bits_end_data) | entries_ld_7_bits_opa_bits_wraps_around) | _T_3050 & (new_entry_opb_bits_start_is_acc_addr ? new_entry_opb_bits_start_data[11:0] <= entries_ld_7_bits_opa_bits_start_data[11:0] : new_entry_opb_bits_start_data <= entries_ld_7_bits_opa_bits_start_data) & (entries_ld_7_bits_opa_bits_start_is_acc_addr == new_entry_opb_bits_end_is_acc_addr & (entries_ld_7_bits_opa_bits_start_is_acc_addr ? entries_ld_7_bits_opa_bits_start_data[11:0] < new_entry_opb_bits_end_data[11:0] : entries_ld_7_bits_opa_bits_start_data < new_entry_opb_bits_end_data) | new_entry_opb_bits_wraps_around)) & ~(_T_3071 & new_entry_opb_bits_start_read_full_acc_row & (&new_entry_opb_bits_start_data) & new_entry_opb_bits_start_garbage_bit | _T_3077 & entries_ld_7_bits_opa_bits_start_read_full_acc_row & (&entries_ld_7_bits_opa_bits_start_data) & entries_ld_7_bits_opa_bits_start_garbage_bit)) : entries_ld_7_valid & entries_ld_7_bits_opa_valid & not_config & (_T_3795 & (entries_ld_7_bits_opa_bits_start_is_acc_addr ? entries_ld_7_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ld_7_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ld_7_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ld_7_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ld_7_bits_opa_bits_end_data) | entries_ld_7_bits_opa_bits_wraps_around) | _T_3795 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ld_7_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ld_7_bits_opa_bits_start_data) & (entries_ld_7_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ld_7_bits_opa_bits_start_is_acc_addr ? entries_ld_7_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ld_7_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_4776 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ld_7_bits_opa_bits_start_is_acc_addr & entries_ld_7_bits_opa_bits_start_accumulate & entries_ld_7_bits_opa_bits_start_read_full_acc_row & (&entries_ld_7_bits_opa_bits_start_data) & entries_ld_7_bits_opa_bits_start_garbage_bit); // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :117:23, :171:23, :295:84, :296:59, :309:22, :310:20, :312:{25,66,69}, :320:24, :322:{25,66,86,100}, :323:54, :332:{25,66,86,100}] wire _T_3855 = entries_ex_0_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23] wire _T_3915 = entries_ex_1_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23] wire _T_3975 = entries_ex_2_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23] wire _T_4035 = entries_ex_3_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23] wire _T_4095 = entries_ex_4_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23] wire _T_4155 = entries_ex_5_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23] wire _T_4215 = entries_ex_6_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23] wire _T_4275 = entries_ex_7_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23] wire _T_4335 = entries_ex_8_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23] wire _T_4395 = entries_ex_9_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23] wire _T_4455 = entries_ex_10_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23] wire _T_4515 = entries_ex_11_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23] wire _T_4575 = entries_ex_12_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23] wire _T_4635 = entries_ex_13_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23] wire _T_4695 = entries_ex_14_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23] wire _T_4755 = entries_ex_15_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23] assign new_entry_deps_ex_0 = is_load ? entries_ex_0_valid & ~new_entry_is_config & ((_T_58 & (entries_ex_0_bits_opa_bits_start_is_acc_addr ? entries_ex_0_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ex_0_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_0_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ex_0_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ex_0_bits_opa_bits_end_data) | entries_ex_0_bits_opa_bits_wraps_around) | _T_58 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ex_0_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ex_0_bits_opa_bits_start_data) & (entries_ex_0_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_0_bits_opa_bits_start_is_acc_addr ? entries_ex_0_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ex_0_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_0_bits_opa_bits_start_is_acc_addr & entries_ex_0_bits_opa_bits_start_accumulate & entries_ex_0_bits_opa_bits_start_read_full_acc_row & (&entries_ex_0_bits_opa_bits_start_data) & entries_ex_0_bits_opa_bits_start_garbage_bit) & entries_ex_0_bits_opa_valid | (_T_115 & (entries_ex_0_bits_opb_bits_start_is_acc_addr ? entries_ex_0_bits_opb_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ex_0_bits_opb_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_0_bits_opb_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ex_0_bits_opb_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ex_0_bits_opb_bits_end_data) | entries_ex_0_bits_opb_bits_wraps_around) | _T_115 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ex_0_bits_opb_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ex_0_bits_opb_bits_start_data) & (entries_ex_0_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_0_bits_opb_bits_start_is_acc_addr ? entries_ex_0_bits_opb_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ex_0_bits_opb_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_0_bits_opb_bits_start_is_acc_addr & entries_ex_0_bits_opb_bits_start_accumulate & entries_ex_0_bits_opb_bits_start_read_full_acc_row & (&entries_ex_0_bits_opb_bits_start_data) & entries_ex_0_bits_opb_bits_start_garbage_bit) & entries_ex_0_bits_opb_valid) : is_ex ? entries_ex_0_valid & ~entries_ex_0_bits_issued : entries_ex_0_valid & entries_ex_0_bits_opa_valid & not_config & entries_ex_0_bits_opa_is_dst & (_T_3855 & (entries_ex_0_bits_opa_bits_start_is_acc_addr ? entries_ex_0_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ex_0_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_0_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ex_0_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ex_0_bits_opa_bits_end_data) | entries_ex_0_bits_opa_bits_wraps_around) | _T_3855 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ex_0_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ex_0_bits_opa_bits_start_data) & (entries_ex_0_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_0_bits_opa_bits_start_is_acc_addr ? entries_ex_0_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ex_0_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_4776 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_0_bits_opa_bits_start_is_acc_addr & entries_ex_0_bits_opa_bits_start_accumulate & entries_ex_0_bits_opa_bits_start_read_full_acc_row & (&entries_ex_0_bits_opa_bits_start_data) & entries_ex_0_bits_opa_bits_start_garbage_bit); // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :118:23, :171:23, :295:84, :296:59, :309:22, :310:20, :314:{25,66,90}, :315:{55,76}, :316:55, :320:24, :326:{25,66,69}, :335:{25,66,86,100}, :336:27] assign new_entry_deps_ex_1 = is_load ? entries_ex_1_valid & ~new_entry_is_config & ((_T_176 & (entries_ex_1_bits_opa_bits_start_is_acc_addr ? entries_ex_1_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ex_1_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_1_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ex_1_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ex_1_bits_opa_bits_end_data) | entries_ex_1_bits_opa_bits_wraps_around) | _T_176 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ex_1_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ex_1_bits_opa_bits_start_data) & (entries_ex_1_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_1_bits_opa_bits_start_is_acc_addr ? entries_ex_1_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ex_1_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_1_bits_opa_bits_start_is_acc_addr & entries_ex_1_bits_opa_bits_start_accumulate & entries_ex_1_bits_opa_bits_start_read_full_acc_row & (&entries_ex_1_bits_opa_bits_start_data) & entries_ex_1_bits_opa_bits_start_garbage_bit) & entries_ex_1_bits_opa_valid | (_T_233 & (entries_ex_1_bits_opb_bits_start_is_acc_addr ? entries_ex_1_bits_opb_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ex_1_bits_opb_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_1_bits_opb_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ex_1_bits_opb_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ex_1_bits_opb_bits_end_data) | entries_ex_1_bits_opb_bits_wraps_around) | _T_233 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ex_1_bits_opb_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ex_1_bits_opb_bits_start_data) & (entries_ex_1_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_1_bits_opb_bits_start_is_acc_addr ? entries_ex_1_bits_opb_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ex_1_bits_opb_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_1_bits_opb_bits_start_is_acc_addr & entries_ex_1_bits_opb_bits_start_accumulate & entries_ex_1_bits_opb_bits_start_read_full_acc_row & (&entries_ex_1_bits_opb_bits_start_data) & entries_ex_1_bits_opb_bits_start_garbage_bit) & entries_ex_1_bits_opb_valid) : is_ex ? entries_ex_1_valid & ~entries_ex_1_bits_issued : entries_ex_1_valid & entries_ex_1_bits_opa_valid & not_config & entries_ex_1_bits_opa_is_dst & (_T_3915 & (entries_ex_1_bits_opa_bits_start_is_acc_addr ? entries_ex_1_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ex_1_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_1_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ex_1_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ex_1_bits_opa_bits_end_data) | entries_ex_1_bits_opa_bits_wraps_around) | _T_3915 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ex_1_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ex_1_bits_opa_bits_start_data) & (entries_ex_1_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_1_bits_opa_bits_start_is_acc_addr ? entries_ex_1_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ex_1_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_4776 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_1_bits_opa_bits_start_is_acc_addr & entries_ex_1_bits_opa_bits_start_accumulate & entries_ex_1_bits_opa_bits_start_read_full_acc_row & (&entries_ex_1_bits_opa_bits_start_data) & entries_ex_1_bits_opa_bits_start_garbage_bit); // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :118:23, :171:23, :295:84, :296:59, :309:22, :310:20, :314:{25,66,90}, :315:{55,76}, :316:55, :320:24, :326:{25,66,69}, :335:{25,66,86,100}, :336:27] assign new_entry_deps_ex_2 = is_load ? entries_ex_2_valid & ~new_entry_is_config & ((_T_294 & (entries_ex_2_bits_opa_bits_start_is_acc_addr ? entries_ex_2_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ex_2_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_2_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ex_2_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ex_2_bits_opa_bits_end_data) | entries_ex_2_bits_opa_bits_wraps_around) | _T_294 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ex_2_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ex_2_bits_opa_bits_start_data) & (entries_ex_2_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_2_bits_opa_bits_start_is_acc_addr ? entries_ex_2_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ex_2_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_2_bits_opa_bits_start_is_acc_addr & entries_ex_2_bits_opa_bits_start_accumulate & entries_ex_2_bits_opa_bits_start_read_full_acc_row & (&entries_ex_2_bits_opa_bits_start_data) & entries_ex_2_bits_opa_bits_start_garbage_bit) & entries_ex_2_bits_opa_valid | (_T_351 & (entries_ex_2_bits_opb_bits_start_is_acc_addr ? entries_ex_2_bits_opb_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ex_2_bits_opb_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_2_bits_opb_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ex_2_bits_opb_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ex_2_bits_opb_bits_end_data) | entries_ex_2_bits_opb_bits_wraps_around) | _T_351 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ex_2_bits_opb_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ex_2_bits_opb_bits_start_data) & (entries_ex_2_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_2_bits_opb_bits_start_is_acc_addr ? entries_ex_2_bits_opb_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ex_2_bits_opb_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_2_bits_opb_bits_start_is_acc_addr & entries_ex_2_bits_opb_bits_start_accumulate & entries_ex_2_bits_opb_bits_start_read_full_acc_row & (&entries_ex_2_bits_opb_bits_start_data) & entries_ex_2_bits_opb_bits_start_garbage_bit) & entries_ex_2_bits_opb_valid) : is_ex ? entries_ex_2_valid & ~entries_ex_2_bits_issued : entries_ex_2_valid & entries_ex_2_bits_opa_valid & not_config & entries_ex_2_bits_opa_is_dst & (_T_3975 & (entries_ex_2_bits_opa_bits_start_is_acc_addr ? entries_ex_2_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ex_2_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_2_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ex_2_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ex_2_bits_opa_bits_end_data) | entries_ex_2_bits_opa_bits_wraps_around) | _T_3975 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ex_2_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ex_2_bits_opa_bits_start_data) & (entries_ex_2_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_2_bits_opa_bits_start_is_acc_addr ? entries_ex_2_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ex_2_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_4776 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_2_bits_opa_bits_start_is_acc_addr & entries_ex_2_bits_opa_bits_start_accumulate & entries_ex_2_bits_opa_bits_start_read_full_acc_row & (&entries_ex_2_bits_opa_bits_start_data) & entries_ex_2_bits_opa_bits_start_garbage_bit); // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :118:23, :171:23, :295:84, :296:59, :309:22, :310:20, :314:{25,66,90}, :315:{55,76}, :316:55, :320:24, :326:{25,66,69}, :335:{25,66,86,100}, :336:27] assign new_entry_deps_ex_3 = is_load ? entries_ex_3_valid & ~new_entry_is_config & ((_T_412 & (entries_ex_3_bits_opa_bits_start_is_acc_addr ? entries_ex_3_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ex_3_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_3_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ex_3_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ex_3_bits_opa_bits_end_data) | entries_ex_3_bits_opa_bits_wraps_around) | _T_412 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ex_3_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ex_3_bits_opa_bits_start_data) & (entries_ex_3_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_3_bits_opa_bits_start_is_acc_addr ? entries_ex_3_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ex_3_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_3_bits_opa_bits_start_is_acc_addr & entries_ex_3_bits_opa_bits_start_accumulate & entries_ex_3_bits_opa_bits_start_read_full_acc_row & (&entries_ex_3_bits_opa_bits_start_data) & entries_ex_3_bits_opa_bits_start_garbage_bit) & entries_ex_3_bits_opa_valid | (_T_469 & (entries_ex_3_bits_opb_bits_start_is_acc_addr ? entries_ex_3_bits_opb_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ex_3_bits_opb_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_3_bits_opb_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ex_3_bits_opb_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ex_3_bits_opb_bits_end_data) | entries_ex_3_bits_opb_bits_wraps_around) | _T_469 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ex_3_bits_opb_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ex_3_bits_opb_bits_start_data) & (entries_ex_3_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_3_bits_opb_bits_start_is_acc_addr ? entries_ex_3_bits_opb_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ex_3_bits_opb_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_3_bits_opb_bits_start_is_acc_addr & entries_ex_3_bits_opb_bits_start_accumulate & entries_ex_3_bits_opb_bits_start_read_full_acc_row & (&entries_ex_3_bits_opb_bits_start_data) & entries_ex_3_bits_opb_bits_start_garbage_bit) & entries_ex_3_bits_opb_valid) : is_ex ? entries_ex_3_valid & ~entries_ex_3_bits_issued : entries_ex_3_valid & entries_ex_3_bits_opa_valid & not_config & entries_ex_3_bits_opa_is_dst & (_T_4035 & (entries_ex_3_bits_opa_bits_start_is_acc_addr ? entries_ex_3_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ex_3_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_3_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ex_3_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ex_3_bits_opa_bits_end_data) | entries_ex_3_bits_opa_bits_wraps_around) | _T_4035 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ex_3_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ex_3_bits_opa_bits_start_data) & (entries_ex_3_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_3_bits_opa_bits_start_is_acc_addr ? entries_ex_3_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ex_3_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_4776 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_3_bits_opa_bits_start_is_acc_addr & entries_ex_3_bits_opa_bits_start_accumulate & entries_ex_3_bits_opa_bits_start_read_full_acc_row & (&entries_ex_3_bits_opa_bits_start_data) & entries_ex_3_bits_opa_bits_start_garbage_bit); // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :118:23, :171:23, :295:84, :296:59, :309:22, :310:20, :314:{25,66,90}, :315:{55,76}, :316:55, :320:24, :326:{25,66,69}, :335:{25,66,86,100}, :336:27] assign new_entry_deps_ex_4 = is_load ? entries_ex_4_valid & ~new_entry_is_config & ((_T_530 & (entries_ex_4_bits_opa_bits_start_is_acc_addr ? entries_ex_4_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ex_4_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_4_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ex_4_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ex_4_bits_opa_bits_end_data) | entries_ex_4_bits_opa_bits_wraps_around) | _T_530 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ex_4_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ex_4_bits_opa_bits_start_data) & (entries_ex_4_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_4_bits_opa_bits_start_is_acc_addr ? entries_ex_4_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ex_4_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_4_bits_opa_bits_start_is_acc_addr & entries_ex_4_bits_opa_bits_start_accumulate & entries_ex_4_bits_opa_bits_start_read_full_acc_row & (&entries_ex_4_bits_opa_bits_start_data) & entries_ex_4_bits_opa_bits_start_garbage_bit) & entries_ex_4_bits_opa_valid | (_T_587 & (entries_ex_4_bits_opb_bits_start_is_acc_addr ? entries_ex_4_bits_opb_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ex_4_bits_opb_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_4_bits_opb_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ex_4_bits_opb_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ex_4_bits_opb_bits_end_data) | entries_ex_4_bits_opb_bits_wraps_around) | _T_587 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ex_4_bits_opb_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ex_4_bits_opb_bits_start_data) & (entries_ex_4_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_4_bits_opb_bits_start_is_acc_addr ? entries_ex_4_bits_opb_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ex_4_bits_opb_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_4_bits_opb_bits_start_is_acc_addr & entries_ex_4_bits_opb_bits_start_accumulate & entries_ex_4_bits_opb_bits_start_read_full_acc_row & (&entries_ex_4_bits_opb_bits_start_data) & entries_ex_4_bits_opb_bits_start_garbage_bit) & entries_ex_4_bits_opb_valid) : is_ex ? entries_ex_4_valid & ~entries_ex_4_bits_issued : entries_ex_4_valid & entries_ex_4_bits_opa_valid & not_config & entries_ex_4_bits_opa_is_dst & (_T_4095 & (entries_ex_4_bits_opa_bits_start_is_acc_addr ? entries_ex_4_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ex_4_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_4_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ex_4_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ex_4_bits_opa_bits_end_data) | entries_ex_4_bits_opa_bits_wraps_around) | _T_4095 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ex_4_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ex_4_bits_opa_bits_start_data) & (entries_ex_4_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_4_bits_opa_bits_start_is_acc_addr ? entries_ex_4_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ex_4_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_4776 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_4_bits_opa_bits_start_is_acc_addr & entries_ex_4_bits_opa_bits_start_accumulate & entries_ex_4_bits_opa_bits_start_read_full_acc_row & (&entries_ex_4_bits_opa_bits_start_data) & entries_ex_4_bits_opa_bits_start_garbage_bit); // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :118:23, :171:23, :295:84, :296:59, :309:22, :310:20, :314:{25,66,90}, :315:{55,76}, :316:55, :320:24, :326:{25,66,69}, :335:{25,66,86,100}, :336:27] assign new_entry_deps_ex_5 = is_load ? entries_ex_5_valid & ~new_entry_is_config & ((_T_648 & (entries_ex_5_bits_opa_bits_start_is_acc_addr ? entries_ex_5_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ex_5_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_5_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ex_5_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ex_5_bits_opa_bits_end_data) | entries_ex_5_bits_opa_bits_wraps_around) | _T_648 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ex_5_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ex_5_bits_opa_bits_start_data) & (entries_ex_5_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_5_bits_opa_bits_start_is_acc_addr ? entries_ex_5_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ex_5_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_5_bits_opa_bits_start_is_acc_addr & entries_ex_5_bits_opa_bits_start_accumulate & entries_ex_5_bits_opa_bits_start_read_full_acc_row & (&entries_ex_5_bits_opa_bits_start_data) & entries_ex_5_bits_opa_bits_start_garbage_bit) & entries_ex_5_bits_opa_valid | (_T_705 & (entries_ex_5_bits_opb_bits_start_is_acc_addr ? entries_ex_5_bits_opb_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ex_5_bits_opb_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_5_bits_opb_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ex_5_bits_opb_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ex_5_bits_opb_bits_end_data) | entries_ex_5_bits_opb_bits_wraps_around) | _T_705 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ex_5_bits_opb_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ex_5_bits_opb_bits_start_data) & (entries_ex_5_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_5_bits_opb_bits_start_is_acc_addr ? entries_ex_5_bits_opb_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ex_5_bits_opb_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_5_bits_opb_bits_start_is_acc_addr & entries_ex_5_bits_opb_bits_start_accumulate & entries_ex_5_bits_opb_bits_start_read_full_acc_row & (&entries_ex_5_bits_opb_bits_start_data) & entries_ex_5_bits_opb_bits_start_garbage_bit) & entries_ex_5_bits_opb_valid) : is_ex ? entries_ex_5_valid & ~entries_ex_5_bits_issued : entries_ex_5_valid & entries_ex_5_bits_opa_valid & not_config & entries_ex_5_bits_opa_is_dst & (_T_4155 & (entries_ex_5_bits_opa_bits_start_is_acc_addr ? entries_ex_5_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ex_5_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_5_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ex_5_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ex_5_bits_opa_bits_end_data) | entries_ex_5_bits_opa_bits_wraps_around) | _T_4155 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ex_5_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ex_5_bits_opa_bits_start_data) & (entries_ex_5_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_5_bits_opa_bits_start_is_acc_addr ? entries_ex_5_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ex_5_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_4776 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_5_bits_opa_bits_start_is_acc_addr & entries_ex_5_bits_opa_bits_start_accumulate & entries_ex_5_bits_opa_bits_start_read_full_acc_row & (&entries_ex_5_bits_opa_bits_start_data) & entries_ex_5_bits_opa_bits_start_garbage_bit); // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :118:23, :171:23, :295:84, :296:59, :309:22, :310:20, :314:{25,66,90}, :315:{55,76}, :316:55, :320:24, :326:{25,66,69}, :335:{25,66,86,100}, :336:27] assign new_entry_deps_ex_6 = is_load ? entries_ex_6_valid & ~new_entry_is_config & ((_T_766 & (entries_ex_6_bits_opa_bits_start_is_acc_addr ? entries_ex_6_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ex_6_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_6_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ex_6_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ex_6_bits_opa_bits_end_data) | entries_ex_6_bits_opa_bits_wraps_around) | _T_766 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ex_6_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ex_6_bits_opa_bits_start_data) & (entries_ex_6_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_6_bits_opa_bits_start_is_acc_addr ? entries_ex_6_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ex_6_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_6_bits_opa_bits_start_is_acc_addr & entries_ex_6_bits_opa_bits_start_accumulate & entries_ex_6_bits_opa_bits_start_read_full_acc_row & (&entries_ex_6_bits_opa_bits_start_data) & entries_ex_6_bits_opa_bits_start_garbage_bit) & entries_ex_6_bits_opa_valid | (_T_823 & (entries_ex_6_bits_opb_bits_start_is_acc_addr ? entries_ex_6_bits_opb_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ex_6_bits_opb_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_6_bits_opb_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ex_6_bits_opb_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ex_6_bits_opb_bits_end_data) | entries_ex_6_bits_opb_bits_wraps_around) | _T_823 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ex_6_bits_opb_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ex_6_bits_opb_bits_start_data) & (entries_ex_6_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_6_bits_opb_bits_start_is_acc_addr ? entries_ex_6_bits_opb_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ex_6_bits_opb_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_6_bits_opb_bits_start_is_acc_addr & entries_ex_6_bits_opb_bits_start_accumulate & entries_ex_6_bits_opb_bits_start_read_full_acc_row & (&entries_ex_6_bits_opb_bits_start_data) & entries_ex_6_bits_opb_bits_start_garbage_bit) & entries_ex_6_bits_opb_valid) : is_ex ? entries_ex_6_valid & ~entries_ex_6_bits_issued : entries_ex_6_valid & entries_ex_6_bits_opa_valid & not_config & entries_ex_6_bits_opa_is_dst & (_T_4215 & (entries_ex_6_bits_opa_bits_start_is_acc_addr ? entries_ex_6_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ex_6_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_6_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ex_6_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ex_6_bits_opa_bits_end_data) | entries_ex_6_bits_opa_bits_wraps_around) | _T_4215 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ex_6_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ex_6_bits_opa_bits_start_data) & (entries_ex_6_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_6_bits_opa_bits_start_is_acc_addr ? entries_ex_6_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ex_6_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_4776 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_6_bits_opa_bits_start_is_acc_addr & entries_ex_6_bits_opa_bits_start_accumulate & entries_ex_6_bits_opa_bits_start_read_full_acc_row & (&entries_ex_6_bits_opa_bits_start_data) & entries_ex_6_bits_opa_bits_start_garbage_bit); // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :118:23, :171:23, :295:84, :296:59, :309:22, :310:20, :314:{25,66,90}, :315:{55,76}, :316:55, :320:24, :326:{25,66,69}, :335:{25,66,86,100}, :336:27] assign new_entry_deps_ex_7 = is_load ? entries_ex_7_valid & ~new_entry_is_config & ((_T_884 & (entries_ex_7_bits_opa_bits_start_is_acc_addr ? entries_ex_7_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ex_7_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_7_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ex_7_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ex_7_bits_opa_bits_end_data) | entries_ex_7_bits_opa_bits_wraps_around) | _T_884 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ex_7_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ex_7_bits_opa_bits_start_data) & (entries_ex_7_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_7_bits_opa_bits_start_is_acc_addr ? entries_ex_7_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ex_7_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_7_bits_opa_bits_start_is_acc_addr & entries_ex_7_bits_opa_bits_start_accumulate & entries_ex_7_bits_opa_bits_start_read_full_acc_row & (&entries_ex_7_bits_opa_bits_start_data) & entries_ex_7_bits_opa_bits_start_garbage_bit) & entries_ex_7_bits_opa_valid | (_T_941 & (entries_ex_7_bits_opb_bits_start_is_acc_addr ? entries_ex_7_bits_opb_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ex_7_bits_opb_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_7_bits_opb_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ex_7_bits_opb_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ex_7_bits_opb_bits_end_data) | entries_ex_7_bits_opb_bits_wraps_around) | _T_941 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ex_7_bits_opb_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ex_7_bits_opb_bits_start_data) & (entries_ex_7_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_7_bits_opb_bits_start_is_acc_addr ? entries_ex_7_bits_opb_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ex_7_bits_opb_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_7_bits_opb_bits_start_is_acc_addr & entries_ex_7_bits_opb_bits_start_accumulate & entries_ex_7_bits_opb_bits_start_read_full_acc_row & (&entries_ex_7_bits_opb_bits_start_data) & entries_ex_7_bits_opb_bits_start_garbage_bit) & entries_ex_7_bits_opb_valid) : is_ex ? entries_ex_7_valid & ~entries_ex_7_bits_issued : entries_ex_7_valid & entries_ex_7_bits_opa_valid & not_config & entries_ex_7_bits_opa_is_dst & (_T_4275 & (entries_ex_7_bits_opa_bits_start_is_acc_addr ? entries_ex_7_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ex_7_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_7_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ex_7_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ex_7_bits_opa_bits_end_data) | entries_ex_7_bits_opa_bits_wraps_around) | _T_4275 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ex_7_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ex_7_bits_opa_bits_start_data) & (entries_ex_7_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_7_bits_opa_bits_start_is_acc_addr ? entries_ex_7_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ex_7_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_4776 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_7_bits_opa_bits_start_is_acc_addr & entries_ex_7_bits_opa_bits_start_accumulate & entries_ex_7_bits_opa_bits_start_read_full_acc_row & (&entries_ex_7_bits_opa_bits_start_data) & entries_ex_7_bits_opa_bits_start_garbage_bit); // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :118:23, :171:23, :295:84, :296:59, :309:22, :310:20, :314:{25,66,90}, :315:{55,76}, :316:55, :320:24, :326:{25,66,69}, :335:{25,66,86,100}, :336:27] assign new_entry_deps_ex_8 = is_load ? entries_ex_8_valid & ~new_entry_is_config & ((_T_1002 & (entries_ex_8_bits_opa_bits_start_is_acc_addr ? entries_ex_8_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ex_8_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_8_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ex_8_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ex_8_bits_opa_bits_end_data) | entries_ex_8_bits_opa_bits_wraps_around) | _T_1002 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ex_8_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ex_8_bits_opa_bits_start_data) & (entries_ex_8_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_8_bits_opa_bits_start_is_acc_addr ? entries_ex_8_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ex_8_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_8_bits_opa_bits_start_is_acc_addr & entries_ex_8_bits_opa_bits_start_accumulate & entries_ex_8_bits_opa_bits_start_read_full_acc_row & (&entries_ex_8_bits_opa_bits_start_data) & entries_ex_8_bits_opa_bits_start_garbage_bit) & entries_ex_8_bits_opa_valid | (_T_1059 & (entries_ex_8_bits_opb_bits_start_is_acc_addr ? entries_ex_8_bits_opb_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ex_8_bits_opb_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_8_bits_opb_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ex_8_bits_opb_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ex_8_bits_opb_bits_end_data) | entries_ex_8_bits_opb_bits_wraps_around) | _T_1059 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ex_8_bits_opb_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ex_8_bits_opb_bits_start_data) & (entries_ex_8_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_8_bits_opb_bits_start_is_acc_addr ? entries_ex_8_bits_opb_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ex_8_bits_opb_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_8_bits_opb_bits_start_is_acc_addr & entries_ex_8_bits_opb_bits_start_accumulate & entries_ex_8_bits_opb_bits_start_read_full_acc_row & (&entries_ex_8_bits_opb_bits_start_data) & entries_ex_8_bits_opb_bits_start_garbage_bit) & entries_ex_8_bits_opb_valid) : is_ex ? entries_ex_8_valid & ~entries_ex_8_bits_issued : entries_ex_8_valid & entries_ex_8_bits_opa_valid & not_config & entries_ex_8_bits_opa_is_dst & (_T_4335 & (entries_ex_8_bits_opa_bits_start_is_acc_addr ? entries_ex_8_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ex_8_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_8_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ex_8_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ex_8_bits_opa_bits_end_data) | entries_ex_8_bits_opa_bits_wraps_around) | _T_4335 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ex_8_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ex_8_bits_opa_bits_start_data) & (entries_ex_8_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_8_bits_opa_bits_start_is_acc_addr ? entries_ex_8_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ex_8_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_4776 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_8_bits_opa_bits_start_is_acc_addr & entries_ex_8_bits_opa_bits_start_accumulate & entries_ex_8_bits_opa_bits_start_read_full_acc_row & (&entries_ex_8_bits_opa_bits_start_data) & entries_ex_8_bits_opa_bits_start_garbage_bit); // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :118:23, :171:23, :295:84, :296:59, :309:22, :310:20, :314:{25,66,90}, :315:{55,76}, :316:55, :320:24, :326:{25,66,69}, :335:{25,66,86,100}, :336:27] assign new_entry_deps_ex_9 = is_load ? entries_ex_9_valid & ~new_entry_is_config & ((_T_1120 & (entries_ex_9_bits_opa_bits_start_is_acc_addr ? entries_ex_9_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ex_9_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_9_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ex_9_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ex_9_bits_opa_bits_end_data) | entries_ex_9_bits_opa_bits_wraps_around) | _T_1120 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ex_9_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ex_9_bits_opa_bits_start_data) & (entries_ex_9_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_9_bits_opa_bits_start_is_acc_addr ? entries_ex_9_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ex_9_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_9_bits_opa_bits_start_is_acc_addr & entries_ex_9_bits_opa_bits_start_accumulate & entries_ex_9_bits_opa_bits_start_read_full_acc_row & (&entries_ex_9_bits_opa_bits_start_data) & entries_ex_9_bits_opa_bits_start_garbage_bit) & entries_ex_9_bits_opa_valid | (_T_1177 & (entries_ex_9_bits_opb_bits_start_is_acc_addr ? entries_ex_9_bits_opb_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ex_9_bits_opb_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_9_bits_opb_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ex_9_bits_opb_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ex_9_bits_opb_bits_end_data) | entries_ex_9_bits_opb_bits_wraps_around) | _T_1177 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ex_9_bits_opb_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ex_9_bits_opb_bits_start_data) & (entries_ex_9_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_9_bits_opb_bits_start_is_acc_addr ? entries_ex_9_bits_opb_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ex_9_bits_opb_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_9_bits_opb_bits_start_is_acc_addr & entries_ex_9_bits_opb_bits_start_accumulate & entries_ex_9_bits_opb_bits_start_read_full_acc_row & (&entries_ex_9_bits_opb_bits_start_data) & entries_ex_9_bits_opb_bits_start_garbage_bit) & entries_ex_9_bits_opb_valid) : is_ex ? entries_ex_9_valid & ~entries_ex_9_bits_issued : entries_ex_9_valid & entries_ex_9_bits_opa_valid & not_config & entries_ex_9_bits_opa_is_dst & (_T_4395 & (entries_ex_9_bits_opa_bits_start_is_acc_addr ? entries_ex_9_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ex_9_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_9_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ex_9_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ex_9_bits_opa_bits_end_data) | entries_ex_9_bits_opa_bits_wraps_around) | _T_4395 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ex_9_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ex_9_bits_opa_bits_start_data) & (entries_ex_9_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_9_bits_opa_bits_start_is_acc_addr ? entries_ex_9_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ex_9_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_4776 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_9_bits_opa_bits_start_is_acc_addr & entries_ex_9_bits_opa_bits_start_accumulate & entries_ex_9_bits_opa_bits_start_read_full_acc_row & (&entries_ex_9_bits_opa_bits_start_data) & entries_ex_9_bits_opa_bits_start_garbage_bit); // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :118:23, :171:23, :295:84, :296:59, :309:22, :310:20, :314:{25,66,90}, :315:{55,76}, :316:55, :320:24, :326:{25,66,69}, :335:{25,66,86,100}, :336:27] assign new_entry_deps_ex_10 = is_load ? entries_ex_10_valid & ~new_entry_is_config & ((_T_1238 & (entries_ex_10_bits_opa_bits_start_is_acc_addr ? entries_ex_10_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ex_10_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_10_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ex_10_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ex_10_bits_opa_bits_end_data) | entries_ex_10_bits_opa_bits_wraps_around) | _T_1238 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ex_10_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ex_10_bits_opa_bits_start_data) & (entries_ex_10_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_10_bits_opa_bits_start_is_acc_addr ? entries_ex_10_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ex_10_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_10_bits_opa_bits_start_is_acc_addr & entries_ex_10_bits_opa_bits_start_accumulate & entries_ex_10_bits_opa_bits_start_read_full_acc_row & (&entries_ex_10_bits_opa_bits_start_data) & entries_ex_10_bits_opa_bits_start_garbage_bit) & entries_ex_10_bits_opa_valid | (_T_1295 & (entries_ex_10_bits_opb_bits_start_is_acc_addr ? entries_ex_10_bits_opb_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ex_10_bits_opb_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_10_bits_opb_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ex_10_bits_opb_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ex_10_bits_opb_bits_end_data) | entries_ex_10_bits_opb_bits_wraps_around) | _T_1295 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ex_10_bits_opb_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ex_10_bits_opb_bits_start_data) & (entries_ex_10_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_10_bits_opb_bits_start_is_acc_addr ? entries_ex_10_bits_opb_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ex_10_bits_opb_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_10_bits_opb_bits_start_is_acc_addr & entries_ex_10_bits_opb_bits_start_accumulate & entries_ex_10_bits_opb_bits_start_read_full_acc_row & (&entries_ex_10_bits_opb_bits_start_data) & entries_ex_10_bits_opb_bits_start_garbage_bit) & entries_ex_10_bits_opb_valid) : is_ex ? entries_ex_10_valid & ~entries_ex_10_bits_issued : entries_ex_10_valid & entries_ex_10_bits_opa_valid & not_config & entries_ex_10_bits_opa_is_dst & (_T_4455 & (entries_ex_10_bits_opa_bits_start_is_acc_addr ? entries_ex_10_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ex_10_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_10_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ex_10_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ex_10_bits_opa_bits_end_data) | entries_ex_10_bits_opa_bits_wraps_around) | _T_4455 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ex_10_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ex_10_bits_opa_bits_start_data) & (entries_ex_10_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_10_bits_opa_bits_start_is_acc_addr ? entries_ex_10_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ex_10_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_4776 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_10_bits_opa_bits_start_is_acc_addr & entries_ex_10_bits_opa_bits_start_accumulate & entries_ex_10_bits_opa_bits_start_read_full_acc_row & (&entries_ex_10_bits_opa_bits_start_data) & entries_ex_10_bits_opa_bits_start_garbage_bit); // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :118:23, :171:23, :295:84, :296:59, :309:22, :310:20, :314:{25,66,90}, :315:{55,76}, :316:55, :320:24, :326:{25,66,69}, :335:{25,66,86,100}, :336:27] assign new_entry_deps_ex_11 = is_load ? entries_ex_11_valid & ~new_entry_is_config & ((_T_1356 & (entries_ex_11_bits_opa_bits_start_is_acc_addr ? entries_ex_11_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ex_11_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_11_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ex_11_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ex_11_bits_opa_bits_end_data) | entries_ex_11_bits_opa_bits_wraps_around) | _T_1356 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ex_11_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ex_11_bits_opa_bits_start_data) & (entries_ex_11_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_11_bits_opa_bits_start_is_acc_addr ? entries_ex_11_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ex_11_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_11_bits_opa_bits_start_is_acc_addr & entries_ex_11_bits_opa_bits_start_accumulate & entries_ex_11_bits_opa_bits_start_read_full_acc_row & (&entries_ex_11_bits_opa_bits_start_data) & entries_ex_11_bits_opa_bits_start_garbage_bit) & entries_ex_11_bits_opa_valid | (_T_1413 & (entries_ex_11_bits_opb_bits_start_is_acc_addr ? entries_ex_11_bits_opb_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ex_11_bits_opb_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_11_bits_opb_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ex_11_bits_opb_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ex_11_bits_opb_bits_end_data) | entries_ex_11_bits_opb_bits_wraps_around) | _T_1413 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ex_11_bits_opb_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ex_11_bits_opb_bits_start_data) & (entries_ex_11_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_11_bits_opb_bits_start_is_acc_addr ? entries_ex_11_bits_opb_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ex_11_bits_opb_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_11_bits_opb_bits_start_is_acc_addr & entries_ex_11_bits_opb_bits_start_accumulate & entries_ex_11_bits_opb_bits_start_read_full_acc_row & (&entries_ex_11_bits_opb_bits_start_data) & entries_ex_11_bits_opb_bits_start_garbage_bit) & entries_ex_11_bits_opb_valid) : is_ex ? entries_ex_11_valid & ~entries_ex_11_bits_issued : entries_ex_11_valid & entries_ex_11_bits_opa_valid & not_config & entries_ex_11_bits_opa_is_dst & (_T_4515 & (entries_ex_11_bits_opa_bits_start_is_acc_addr ? entries_ex_11_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ex_11_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_11_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ex_11_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ex_11_bits_opa_bits_end_data) | entries_ex_11_bits_opa_bits_wraps_around) | _T_4515 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ex_11_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ex_11_bits_opa_bits_start_data) & (entries_ex_11_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_11_bits_opa_bits_start_is_acc_addr ? entries_ex_11_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ex_11_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_4776 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_11_bits_opa_bits_start_is_acc_addr & entries_ex_11_bits_opa_bits_start_accumulate & entries_ex_11_bits_opa_bits_start_read_full_acc_row & (&entries_ex_11_bits_opa_bits_start_data) & entries_ex_11_bits_opa_bits_start_garbage_bit); // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :118:23, :171:23, :295:84, :296:59, :309:22, :310:20, :314:{25,66,90}, :315:{55,76}, :316:55, :320:24, :326:{25,66,69}, :335:{25,66,86,100}, :336:27] assign new_entry_deps_ex_12 = is_load ? entries_ex_12_valid & ~new_entry_is_config & ((_T_1474 & (entries_ex_12_bits_opa_bits_start_is_acc_addr ? entries_ex_12_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ex_12_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_12_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ex_12_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ex_12_bits_opa_bits_end_data) | entries_ex_12_bits_opa_bits_wraps_around) | _T_1474 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ex_12_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ex_12_bits_opa_bits_start_data) & (entries_ex_12_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_12_bits_opa_bits_start_is_acc_addr ? entries_ex_12_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ex_12_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_12_bits_opa_bits_start_is_acc_addr & entries_ex_12_bits_opa_bits_start_accumulate & entries_ex_12_bits_opa_bits_start_read_full_acc_row & (&entries_ex_12_bits_opa_bits_start_data) & entries_ex_12_bits_opa_bits_start_garbage_bit) & entries_ex_12_bits_opa_valid | (_T_1531 & (entries_ex_12_bits_opb_bits_start_is_acc_addr ? entries_ex_12_bits_opb_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ex_12_bits_opb_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_12_bits_opb_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ex_12_bits_opb_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ex_12_bits_opb_bits_end_data) | entries_ex_12_bits_opb_bits_wraps_around) | _T_1531 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ex_12_bits_opb_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ex_12_bits_opb_bits_start_data) & (entries_ex_12_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_12_bits_opb_bits_start_is_acc_addr ? entries_ex_12_bits_opb_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ex_12_bits_opb_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_12_bits_opb_bits_start_is_acc_addr & entries_ex_12_bits_opb_bits_start_accumulate & entries_ex_12_bits_opb_bits_start_read_full_acc_row & (&entries_ex_12_bits_opb_bits_start_data) & entries_ex_12_bits_opb_bits_start_garbage_bit) & entries_ex_12_bits_opb_valid) : is_ex ? entries_ex_12_valid & ~entries_ex_12_bits_issued : entries_ex_12_valid & entries_ex_12_bits_opa_valid & not_config & entries_ex_12_bits_opa_is_dst & (_T_4575 & (entries_ex_12_bits_opa_bits_start_is_acc_addr ? entries_ex_12_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ex_12_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_12_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ex_12_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ex_12_bits_opa_bits_end_data) | entries_ex_12_bits_opa_bits_wraps_around) | _T_4575 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ex_12_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ex_12_bits_opa_bits_start_data) & (entries_ex_12_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_12_bits_opa_bits_start_is_acc_addr ? entries_ex_12_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ex_12_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_4776 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_12_bits_opa_bits_start_is_acc_addr & entries_ex_12_bits_opa_bits_start_accumulate & entries_ex_12_bits_opa_bits_start_read_full_acc_row & (&entries_ex_12_bits_opa_bits_start_data) & entries_ex_12_bits_opa_bits_start_garbage_bit); // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :118:23, :171:23, :295:84, :296:59, :309:22, :310:20, :314:{25,66,90}, :315:{55,76}, :316:55, :320:24, :326:{25,66,69}, :335:{25,66,86,100}, :336:27] assign new_entry_deps_ex_13 = is_load ? entries_ex_13_valid & ~new_entry_is_config & ((_T_1592 & (entries_ex_13_bits_opa_bits_start_is_acc_addr ? entries_ex_13_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ex_13_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_13_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ex_13_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ex_13_bits_opa_bits_end_data) | entries_ex_13_bits_opa_bits_wraps_around) | _T_1592 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ex_13_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ex_13_bits_opa_bits_start_data) & (entries_ex_13_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_13_bits_opa_bits_start_is_acc_addr ? entries_ex_13_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ex_13_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_13_bits_opa_bits_start_is_acc_addr & entries_ex_13_bits_opa_bits_start_accumulate & entries_ex_13_bits_opa_bits_start_read_full_acc_row & (&entries_ex_13_bits_opa_bits_start_data) & entries_ex_13_bits_opa_bits_start_garbage_bit) & entries_ex_13_bits_opa_valid | (_T_1649 & (entries_ex_13_bits_opb_bits_start_is_acc_addr ? entries_ex_13_bits_opb_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ex_13_bits_opb_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_13_bits_opb_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ex_13_bits_opb_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ex_13_bits_opb_bits_end_data) | entries_ex_13_bits_opb_bits_wraps_around) | _T_1649 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ex_13_bits_opb_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ex_13_bits_opb_bits_start_data) & (entries_ex_13_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_13_bits_opb_bits_start_is_acc_addr ? entries_ex_13_bits_opb_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ex_13_bits_opb_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_13_bits_opb_bits_start_is_acc_addr & entries_ex_13_bits_opb_bits_start_accumulate & entries_ex_13_bits_opb_bits_start_read_full_acc_row & (&entries_ex_13_bits_opb_bits_start_data) & entries_ex_13_bits_opb_bits_start_garbage_bit) & entries_ex_13_bits_opb_valid) : is_ex ? entries_ex_13_valid & ~entries_ex_13_bits_issued : entries_ex_13_valid & entries_ex_13_bits_opa_valid & not_config & entries_ex_13_bits_opa_is_dst & (_T_4635 & (entries_ex_13_bits_opa_bits_start_is_acc_addr ? entries_ex_13_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ex_13_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_13_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ex_13_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ex_13_bits_opa_bits_end_data) | entries_ex_13_bits_opa_bits_wraps_around) | _T_4635 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ex_13_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ex_13_bits_opa_bits_start_data) & (entries_ex_13_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_13_bits_opa_bits_start_is_acc_addr ? entries_ex_13_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ex_13_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_4776 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_13_bits_opa_bits_start_is_acc_addr & entries_ex_13_bits_opa_bits_start_accumulate & entries_ex_13_bits_opa_bits_start_read_full_acc_row & (&entries_ex_13_bits_opa_bits_start_data) & entries_ex_13_bits_opa_bits_start_garbage_bit); // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :118:23, :171:23, :295:84, :296:59, :309:22, :310:20, :314:{25,66,90}, :315:{55,76}, :316:55, :320:24, :326:{25,66,69}, :335:{25,66,86,100}, :336:27] assign new_entry_deps_ex_14 = is_load ? entries_ex_14_valid & ~new_entry_is_config & ((_T_1710 & (entries_ex_14_bits_opa_bits_start_is_acc_addr ? entries_ex_14_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ex_14_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_14_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ex_14_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ex_14_bits_opa_bits_end_data) | entries_ex_14_bits_opa_bits_wraps_around) | _T_1710 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ex_14_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ex_14_bits_opa_bits_start_data) & (entries_ex_14_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_14_bits_opa_bits_start_is_acc_addr ? entries_ex_14_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ex_14_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_14_bits_opa_bits_start_is_acc_addr & entries_ex_14_bits_opa_bits_start_accumulate & entries_ex_14_bits_opa_bits_start_read_full_acc_row & (&entries_ex_14_bits_opa_bits_start_data) & entries_ex_14_bits_opa_bits_start_garbage_bit) & entries_ex_14_bits_opa_valid | (_T_1767 & (entries_ex_14_bits_opb_bits_start_is_acc_addr ? entries_ex_14_bits_opb_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ex_14_bits_opb_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_14_bits_opb_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ex_14_bits_opb_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ex_14_bits_opb_bits_end_data) | entries_ex_14_bits_opb_bits_wraps_around) | _T_1767 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ex_14_bits_opb_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ex_14_bits_opb_bits_start_data) & (entries_ex_14_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_14_bits_opb_bits_start_is_acc_addr ? entries_ex_14_bits_opb_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ex_14_bits_opb_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_14_bits_opb_bits_start_is_acc_addr & entries_ex_14_bits_opb_bits_start_accumulate & entries_ex_14_bits_opb_bits_start_read_full_acc_row & (&entries_ex_14_bits_opb_bits_start_data) & entries_ex_14_bits_opb_bits_start_garbage_bit) & entries_ex_14_bits_opb_valid) : is_ex ? entries_ex_14_valid & ~entries_ex_14_bits_issued : entries_ex_14_valid & entries_ex_14_bits_opa_valid & not_config & entries_ex_14_bits_opa_is_dst & (_T_4695 & (entries_ex_14_bits_opa_bits_start_is_acc_addr ? entries_ex_14_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ex_14_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_14_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ex_14_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ex_14_bits_opa_bits_end_data) | entries_ex_14_bits_opa_bits_wraps_around) | _T_4695 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ex_14_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ex_14_bits_opa_bits_start_data) & (entries_ex_14_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_14_bits_opa_bits_start_is_acc_addr ? entries_ex_14_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ex_14_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_4776 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_14_bits_opa_bits_start_is_acc_addr & entries_ex_14_bits_opa_bits_start_accumulate & entries_ex_14_bits_opa_bits_start_read_full_acc_row & (&entries_ex_14_bits_opa_bits_start_data) & entries_ex_14_bits_opa_bits_start_garbage_bit); // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :118:23, :171:23, :295:84, :296:59, :309:22, :310:20, :314:{25,66,90}, :315:{55,76}, :316:55, :320:24, :326:{25,66,69}, :335:{25,66,86,100}, :336:27] assign new_entry_deps_ex_15 = is_load ? entries_ex_15_valid & ~new_entry_is_config & ((_T_1828 & (entries_ex_15_bits_opa_bits_start_is_acc_addr ? entries_ex_15_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ex_15_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_15_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ex_15_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ex_15_bits_opa_bits_end_data) | entries_ex_15_bits_opa_bits_wraps_around) | _T_1828 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ex_15_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ex_15_bits_opa_bits_start_data) & (entries_ex_15_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_15_bits_opa_bits_start_is_acc_addr ? entries_ex_15_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ex_15_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_15_bits_opa_bits_start_is_acc_addr & entries_ex_15_bits_opa_bits_start_accumulate & entries_ex_15_bits_opa_bits_start_read_full_acc_row & (&entries_ex_15_bits_opa_bits_start_data) & entries_ex_15_bits_opa_bits_start_garbage_bit) & entries_ex_15_bits_opa_valid | (_T_1885 & (entries_ex_15_bits_opb_bits_start_is_acc_addr ? entries_ex_15_bits_opb_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ex_15_bits_opb_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_15_bits_opb_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ex_15_bits_opb_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ex_15_bits_opb_bits_end_data) | entries_ex_15_bits_opb_bits_wraps_around) | _T_1885 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ex_15_bits_opb_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ex_15_bits_opb_bits_start_data) & (entries_ex_15_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_15_bits_opb_bits_start_is_acc_addr ? entries_ex_15_bits_opb_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ex_15_bits_opb_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_15_bits_opb_bits_start_is_acc_addr & entries_ex_15_bits_opb_bits_start_accumulate & entries_ex_15_bits_opb_bits_start_read_full_acc_row & (&entries_ex_15_bits_opb_bits_start_data) & entries_ex_15_bits_opb_bits_start_garbage_bit) & entries_ex_15_bits_opb_valid) : is_ex ? entries_ex_15_valid & ~entries_ex_15_bits_issued : entries_ex_15_valid & entries_ex_15_bits_opa_valid & not_config & entries_ex_15_bits_opa_is_dst & (_T_4755 & (entries_ex_15_bits_opa_bits_start_is_acc_addr ? entries_ex_15_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_ex_15_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_15_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_ex_15_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_ex_15_bits_opa_bits_end_data) | entries_ex_15_bits_opa_bits_wraps_around) | _T_4755 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_ex_15_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_ex_15_bits_opa_bits_start_data) & (entries_ex_15_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_15_bits_opa_bits_start_is_acc_addr ? entries_ex_15_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_ex_15_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_4776 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_15_bits_opa_bits_start_is_acc_addr & entries_ex_15_bits_opa_bits_start_accumulate & entries_ex_15_bits_opa_bits_start_read_full_acc_row & (&entries_ex_15_bits_opa_bits_start_data) & entries_ex_15_bits_opa_bits_start_garbage_bit); // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :118:23, :171:23, :295:84, :296:59, :309:22, :310:20, :314:{25,66,90}, :315:{55,76}, :316:55, :320:24, :326:{25,66,69}, :335:{25,66,86,100}, :336:27] assign new_entry_deps_st_0 = is_load ? entries_st_0_valid & entries_st_0_bits_opa_valid & not_config & (_T_1946 & (entries_st_0_bits_opa_bits_start_is_acc_addr ? entries_st_0_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_st_0_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_st_0_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_st_0_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_st_0_bits_opa_bits_end_data) | entries_st_0_bits_opa_bits_wraps_around) | _T_1946 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_st_0_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_st_0_bits_opa_bits_start_data) & (entries_st_0_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_st_0_bits_opa_bits_start_is_acc_addr ? entries_st_0_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_st_0_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_st_0_bits_opa_bits_start_is_acc_addr & entries_st_0_bits_opa_bits_start_accumulate & entries_st_0_bits_opa_bits_start_read_full_acc_row & (&entries_st_0_bits_opa_bits_start_data) & entries_st_0_bits_opa_bits_start_garbage_bit) : is_ex ? entries_st_0_valid & entries_st_0_bits_opa_valid & not_config & new_entry_opa_is_dst & (_T_3143 & (entries_st_0_bits_opa_bits_start_is_acc_addr ? entries_st_0_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_st_0_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_st_0_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_st_0_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_st_0_bits_opa_bits_end_data) | entries_st_0_bits_opa_bits_wraps_around) | _T_3143 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_st_0_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_st_0_bits_opa_bits_start_data) & (entries_st_0_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_st_0_bits_opa_bits_start_is_acc_addr ? entries_st_0_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_st_0_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_3344 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_st_0_bits_opa_bits_start_is_acc_addr & entries_st_0_bits_opa_bits_start_accumulate & entries_st_0_bits_opa_bits_start_read_full_acc_row & (&entries_st_0_bits_opa_bits_start_data) & entries_st_0_bits_opa_bits_start_garbage_bit) : entries_st_0_valid & ~entries_st_0_bits_issued; // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :119:23, :171:23, :295:84, :296:59, :309:22, :310:20, :318:{25,66,86,100}, :320:24, :328:{25,66,86,100,124}, :338:{25,66,69}] assign new_entry_deps_st_1 = is_load ? entries_st_1_valid & entries_st_1_bits_opa_valid & not_config & (_T_2005 & (entries_st_1_bits_opa_bits_start_is_acc_addr ? entries_st_1_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_st_1_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_st_1_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_st_1_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_st_1_bits_opa_bits_end_data) | entries_st_1_bits_opa_bits_wraps_around) | _T_2005 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_st_1_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_st_1_bits_opa_bits_start_data) & (entries_st_1_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_st_1_bits_opa_bits_start_is_acc_addr ? entries_st_1_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_st_1_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_st_1_bits_opa_bits_start_is_acc_addr & entries_st_1_bits_opa_bits_start_accumulate & entries_st_1_bits_opa_bits_start_read_full_acc_row & (&entries_st_1_bits_opa_bits_start_data) & entries_st_1_bits_opa_bits_start_garbage_bit) : is_ex ? entries_st_1_valid & entries_st_1_bits_opa_valid & not_config & new_entry_opa_is_dst & (_T_3203 & (entries_st_1_bits_opa_bits_start_is_acc_addr ? entries_st_1_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_st_1_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_st_1_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_st_1_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_st_1_bits_opa_bits_end_data) | entries_st_1_bits_opa_bits_wraps_around) | _T_3203 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_st_1_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_st_1_bits_opa_bits_start_data) & (entries_st_1_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_st_1_bits_opa_bits_start_is_acc_addr ? entries_st_1_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_st_1_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_3344 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_st_1_bits_opa_bits_start_is_acc_addr & entries_st_1_bits_opa_bits_start_accumulate & entries_st_1_bits_opa_bits_start_read_full_acc_row & (&entries_st_1_bits_opa_bits_start_data) & entries_st_1_bits_opa_bits_start_garbage_bit) : entries_st_1_valid & ~entries_st_1_bits_issued; // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :119:23, :171:23, :295:84, :296:59, :309:22, :310:20, :318:{25,66,86,100}, :320:24, :328:{25,66,86,100,124}, :338:{25,66,69}] assign new_entry_deps_st_2 = is_load ? entries_st_2_valid & entries_st_2_bits_opa_valid & not_config & (_T_2064 & (entries_st_2_bits_opa_bits_start_is_acc_addr ? entries_st_2_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_st_2_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_st_2_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_st_2_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_st_2_bits_opa_bits_end_data) | entries_st_2_bits_opa_bits_wraps_around) | _T_2064 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_st_2_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_st_2_bits_opa_bits_start_data) & (entries_st_2_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_st_2_bits_opa_bits_start_is_acc_addr ? entries_st_2_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_st_2_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_st_2_bits_opa_bits_start_is_acc_addr & entries_st_2_bits_opa_bits_start_accumulate & entries_st_2_bits_opa_bits_start_read_full_acc_row & (&entries_st_2_bits_opa_bits_start_data) & entries_st_2_bits_opa_bits_start_garbage_bit) : is_ex ? entries_st_2_valid & entries_st_2_bits_opa_valid & not_config & new_entry_opa_is_dst & (_T_3263 & (entries_st_2_bits_opa_bits_start_is_acc_addr ? entries_st_2_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_st_2_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_st_2_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_st_2_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_st_2_bits_opa_bits_end_data) | entries_st_2_bits_opa_bits_wraps_around) | _T_3263 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_st_2_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_st_2_bits_opa_bits_start_data) & (entries_st_2_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_st_2_bits_opa_bits_start_is_acc_addr ? entries_st_2_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_st_2_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_3344 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_st_2_bits_opa_bits_start_is_acc_addr & entries_st_2_bits_opa_bits_start_accumulate & entries_st_2_bits_opa_bits_start_read_full_acc_row & (&entries_st_2_bits_opa_bits_start_data) & entries_st_2_bits_opa_bits_start_garbage_bit) : entries_st_2_valid & ~entries_st_2_bits_issued; // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :119:23, :171:23, :295:84, :296:59, :309:22, :310:20, :318:{25,66,86,100}, :320:24, :328:{25,66,86,100,124}, :338:{25,66,69}] assign new_entry_deps_st_3 = is_load ? entries_st_3_valid & entries_st_3_bits_opa_valid & not_config & (_T_2123 & (entries_st_3_bits_opa_bits_start_is_acc_addr ? entries_st_3_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_st_3_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_st_3_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_st_3_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_st_3_bits_opa_bits_end_data) | entries_st_3_bits_opa_bits_wraps_around) | _T_2123 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_st_3_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_st_3_bits_opa_bits_start_data) & (entries_st_3_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_st_3_bits_opa_bits_start_is_acc_addr ? entries_st_3_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_st_3_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_st_3_bits_opa_bits_start_is_acc_addr & entries_st_3_bits_opa_bits_start_accumulate & entries_st_3_bits_opa_bits_start_read_full_acc_row & (&entries_st_3_bits_opa_bits_start_data) & entries_st_3_bits_opa_bits_start_garbage_bit) : is_ex ? entries_st_3_valid & entries_st_3_bits_opa_valid & not_config & new_entry_opa_is_dst & (_T_3323 & (entries_st_3_bits_opa_bits_start_is_acc_addr ? entries_st_3_bits_opa_bits_start_data[11:0] <= new_entry_opa_bits_start_data[11:0] : entries_st_3_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_st_3_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] < entries_st_3_bits_opa_bits_end_data[11:0] : new_entry_opa_bits_start_data < entries_st_3_bits_opa_bits_end_data) | entries_st_3_bits_opa_bits_wraps_around) | _T_3323 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[11:0] <= entries_st_3_bits_opa_bits_start_data[11:0] : new_entry_opa_bits_start_data <= entries_st_3_bits_opa_bits_start_data) & (entries_st_3_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_st_3_bits_opa_bits_start_is_acc_addr ? entries_st_3_bits_opa_bits_start_data[11:0] < new_entry_opa_bits_end_data[11:0] : entries_st_3_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_3344 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_st_3_bits_opa_bits_start_is_acc_addr & entries_st_3_bits_opa_bits_start_accumulate & entries_st_3_bits_opa_bits_start_read_full_acc_row & (&entries_st_3_bits_opa_bits_start_data) & entries_st_3_bits_opa_bits_start_garbage_bit) : entries_st_3_valid & ~entries_st_3_bits_issued; // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :119:23, :171:23, :295:84, :296:59, :309:22, :310:20, :318:{25,66,86,100}, :320:24, :328:{25,66,86,100,124}, :338:{25,66,69}] wire _new_entry_complete_on_issue_T = new_entry_q != 2'h1; // @[ReservationStation.scala:171:23, :343:71] assign _new_entry_complete_on_issue_T_1 = new_entry_is_config & _new_entry_complete_on_issue_T; // @[ReservationStation.scala:171:23, :343:{56,71}] assign new_entry_complete_on_issue = _new_entry_complete_on_issue_T_1; // @[ReservationStation.scala:171:23, :343:56] wire _T_4825 = new_entry_q == 2'h0; // @[ReservationStation.scala:171:23, :350:27] wire [1:0] _GEN_54 = {1'h0, op1_valid} + {1'h0, op2_valid}; // @[ReservationStation.scala:196:19, :199:19, :351:33] wire [1:0] _is_full_T; // @[ReservationStation.scala:351:33] assign _is_full_T = _GEN_54; // @[ReservationStation.scala:351:33] wire [1:0] _is_full_T_4; // @[ReservationStation.scala:351:33] assign _is_full_T_4 = _GEN_54; // @[ReservationStation.scala:351:33] wire [1:0] _is_full_T_8; // @[ReservationStation.scala:351:33] assign _is_full_T_8 = _GEN_54; // @[ReservationStation.scala:351:33] wire [1:0] _is_full_T_1 = _is_full_T; // @[ReservationStation.scala:351:33] wire [2:0] _GEN_55 = {2'h0, dst_valid}; // @[ReservationStation.scala:202:19, :351:33] wire [2:0] _is_full_T_2 = _GEN_55 + {1'h0, _is_full_T_1}; // @[ReservationStation.scala:351:33] wire [1:0] _is_full_T_3 = _is_full_T_2[1:0]; // @[ReservationStation.scala:351:33] wire is_full = _is_full_T_3[1]; // @[ReservationStation.scala:351:{33,72}] wire _alloc_id_T = ~entries_ld_0_valid; // @[ReservationStation.scala:117:23, :355:104] wire _alloc_id_T_1 = ~entries_ld_1_valid; // @[ReservationStation.scala:117:23, :355:104] wire _alloc_id_T_2 = ~entries_ld_2_valid; // @[ReservationStation.scala:117:23, :355:104] wire _alloc_id_T_3 = ~entries_ld_3_valid; // @[ReservationStation.scala:117:23, :355:104] wire _alloc_id_T_4 = ~entries_ld_4_valid; // @[ReservationStation.scala:117:23, :355:104] wire _alloc_id_T_5 = ~entries_ld_5_valid; // @[ReservationStation.scala:117:23, :355:104] wire _alloc_id_T_6 = ~entries_ld_6_valid; // @[ReservationStation.scala:117:23, :355:104] wire _alloc_id_T_7 = ~entries_ld_7_valid; // @[ReservationStation.scala:117:23, :355:104] wire [2:0] _alloc_id_T_9 = {2'h3, ~_alloc_id_T_6}; // @[Mux.scala:126:16] wire [2:0] _alloc_id_T_10 = _alloc_id_T_5 ? 3'h5 : _alloc_id_T_9; // @[Mux.scala:126:16] wire [2:0] _alloc_id_T_11 = _alloc_id_T_4 ? 3'h4 : _alloc_id_T_10; // @[Mux.scala:126:16] wire [2:0] _alloc_id_T_12 = _alloc_id_T_3 ? 3'h3 : _alloc_id_T_11; // @[Mux.scala:126:16] wire [2:0] _alloc_id_T_13 = _alloc_id_T_2 ? 3'h2 : _alloc_id_T_12; // @[Mux.scala:126:16] wire [2:0] _alloc_id_T_14 = _alloc_id_T_1 ? 3'h1 : _alloc_id_T_13; // @[Mux.scala:126:16] wire [2:0] alloc_id = _alloc_id_T ? 3'h0 : _alloc_id_T_14; // @[Mux.scala:126:16] wire [7:0] _GEN_56 = {{entries_ld_7_valid}, {entries_ld_6_valid}, {entries_ld_5_valid}, {entries_ld_4_valid}, {entries_ld_3_valid}, {entries_ld_2_valid}, {entries_ld_1_valid}, {entries_ld_0_valid}}; // @[ReservationStation.scala:117:23, :357:17] wire _GEN_57 = _T_4825 & ~_GEN_56[alloc_id]; // @[Mux.scala:126:16] wire _GEN_58 = alloc_id == 3'h0; // @[Mux.scala:126:16] wire _GEN_59 = alloc_id == 3'h1; // @[Mux.scala:126:16] wire _GEN_60 = alloc_id == 3'h2; // @[Mux.scala:126:16] wire _GEN_61 = alloc_id == 3'h3; // @[Mux.scala:126:16] wire _GEN_62 = alloc_id == 3'h4; // @[Mux.scala:126:16] wire _GEN_63 = alloc_id == 3'h5; // @[Mux.scala:126:16] wire _GEN_64 = alloc_id == 3'h6; // @[Mux.scala:126:16] wire _GEN_65 = io_alloc_valid_0 & _T_4825 & ~_GEN_56[alloc_id]; // @[Mux.scala:126:16] assign new_allocs_oh_ld_0 = _GEN_65 & _GEN_58; // @[ReservationStation.scala:174:30, :179:26, :184:25, :350:34, :357:48, :359:42, :361:39] assign new_allocs_oh_ld_1 = _GEN_65 & _GEN_59; // @[ReservationStation.scala:174:30, :179:26, :184:25, :350:34, :357:48, :359:42, :361:39] assign new_allocs_oh_ld_2 = _GEN_65 & _GEN_60; // @[ReservationStation.scala:174:30, :179:26, :184:25, :350:34, :357:48, :359:42, :361:39] assign new_allocs_oh_ld_3 = _GEN_65 & _GEN_61; // @[ReservationStation.scala:174:30, :179:26, :184:25, :350:34, :357:48, :359:42, :361:39] assign new_allocs_oh_ld_4 = _GEN_65 & _GEN_62; // @[ReservationStation.scala:174:30, :179:26, :184:25, :350:34, :357:48, :359:42, :361:39] assign new_allocs_oh_ld_5 = _GEN_65 & _GEN_63; // @[ReservationStation.scala:174:30, :179:26, :184:25, :350:34, :357:48, :359:42, :361:39] assign new_allocs_oh_ld_6 = _GEN_65 & _GEN_64; // @[ReservationStation.scala:174:30, :179:26, :184:25, :350:34, :357:48, :359:42, :361:39] assign new_allocs_oh_ld_7 = _GEN_65 & (&alloc_id); // @[Mux.scala:126:16] wire _T_4822 = new_entry_q == 2'h1; // @[ReservationStation.scala:171:23, :350:27] wire [1:0] _is_full_T_5 = _is_full_T_4; // @[ReservationStation.scala:351:33] wire [2:0] _is_full_T_6 = _GEN_55 + {1'h0, _is_full_T_5}; // @[ReservationStation.scala:351:33] wire [1:0] _is_full_T_7 = _is_full_T_6[1:0]; // @[ReservationStation.scala:351:33] wire is_full_1 = _is_full_T_7[1]; // @[ReservationStation.scala:351:{33,72}] wire _alloc_id_T_15 = ~entries_ex_0_valid; // @[ReservationStation.scala:118:23, :355:104] wire _alloc_id_T_16 = ~entries_ex_1_valid; // @[ReservationStation.scala:118:23, :355:104] wire _alloc_id_T_17 = ~entries_ex_2_valid; // @[ReservationStation.scala:118:23, :355:104] wire _alloc_id_T_18 = ~entries_ex_3_valid; // @[ReservationStation.scala:118:23, :355:104] wire _alloc_id_T_19 = ~entries_ex_4_valid; // @[ReservationStation.scala:118:23, :355:104] wire _alloc_id_T_20 = ~entries_ex_5_valid; // @[ReservationStation.scala:118:23, :355:104] wire _alloc_id_T_21 = ~entries_ex_6_valid; // @[ReservationStation.scala:118:23, :355:104] wire _alloc_id_T_22 = ~entries_ex_7_valid; // @[ReservationStation.scala:118:23, :355:104] wire _alloc_id_T_23 = ~entries_ex_8_valid; // @[ReservationStation.scala:118:23, :355:104] wire _alloc_id_T_24 = ~entries_ex_9_valid; // @[ReservationStation.scala:118:23, :355:104] wire _alloc_id_T_25 = ~entries_ex_10_valid; // @[ReservationStation.scala:118:23, :355:104] wire _alloc_id_T_26 = ~entries_ex_11_valid; // @[ReservationStation.scala:118:23, :355:104] wire _alloc_id_T_27 = ~entries_ex_12_valid; // @[ReservationStation.scala:118:23, :355:104] wire _alloc_id_T_28 = ~entries_ex_13_valid; // @[ReservationStation.scala:118:23, :355:104] wire _alloc_id_T_29 = ~entries_ex_14_valid; // @[ReservationStation.scala:118:23, :355:104] wire _alloc_id_T_30 = ~entries_ex_15_valid; // @[ReservationStation.scala:118:23, :355:104] wire [3:0] _alloc_id_T_32 = {3'h7, ~_alloc_id_T_29}; // @[Mux.scala:126:16] wire [3:0] _alloc_id_T_33 = _alloc_id_T_28 ? 4'hD : _alloc_id_T_32; // @[Mux.scala:126:16] wire [3:0] _alloc_id_T_34 = _alloc_id_T_27 ? 4'hC : _alloc_id_T_33; // @[Mux.scala:126:16] wire [3:0] _alloc_id_T_35 = _alloc_id_T_26 ? 4'hB : _alloc_id_T_34; // @[Mux.scala:126:16] wire [3:0] _alloc_id_T_36 = _alloc_id_T_25 ? 4'hA : _alloc_id_T_35; // @[Mux.scala:126:16] wire [3:0] _alloc_id_T_37 = _alloc_id_T_24 ? 4'h9 : _alloc_id_T_36; // @[Mux.scala:126:16] wire [3:0] _alloc_id_T_38 = _alloc_id_T_23 ? 4'h8 : _alloc_id_T_37; // @[Mux.scala:126:16] wire [3:0] _alloc_id_T_39 = _alloc_id_T_22 ? 4'h7 : _alloc_id_T_38; // @[Mux.scala:126:16] wire [3:0] _alloc_id_T_40 = _alloc_id_T_21 ? 4'h6 : _alloc_id_T_39; // @[Mux.scala:126:16] wire [3:0] _alloc_id_T_41 = _alloc_id_T_20 ? 4'h5 : _alloc_id_T_40; // @[Mux.scala:126:16] wire [3:0] _alloc_id_T_42 = _alloc_id_T_19 ? 4'h4 : _alloc_id_T_41; // @[Mux.scala:126:16] wire [3:0] _alloc_id_T_43 = _alloc_id_T_18 ? 4'h3 : _alloc_id_T_42; // @[Mux.scala:126:16] wire [3:0] _alloc_id_T_44 = _alloc_id_T_17 ? 4'h2 : _alloc_id_T_43; // @[Mux.scala:126:16] wire [3:0] _alloc_id_T_45 = _alloc_id_T_16 ? 4'h1 : _alloc_id_T_44; // @[Mux.scala:126:16] wire [3:0] alloc_id_1 = _alloc_id_T_15 ? 4'h0 : _alloc_id_T_45; // @[Mux.scala:126:16] wire [15:0] _GEN_66 = {{entries_ex_15_valid}, {entries_ex_14_valid}, {entries_ex_13_valid}, {entries_ex_12_valid}, {entries_ex_11_valid}, {entries_ex_10_valid}, {entries_ex_9_valid}, {entries_ex_8_valid}, {entries_ex_7_valid}, {entries_ex_6_valid}, {entries_ex_5_valid}, {entries_ex_4_valid}, {entries_ex_3_valid}, {entries_ex_2_valid}, {entries_ex_1_valid}, {entries_ex_0_valid}}; // @[ReservationStation.scala:118:23, :357:17] wire _GEN_67 = _T_4822 & ~_GEN_66[alloc_id_1]; // @[Mux.scala:126:16] wire _GEN_68 = alloc_id_1 == 4'h0; // @[Mux.scala:126:16] wire _GEN_69 = alloc_id_1 == 4'h1; // @[Mux.scala:126:16] wire _GEN_70 = alloc_id_1 == 4'h2; // @[Mux.scala:126:16] wire _GEN_71 = alloc_id_1 == 4'h3; // @[Mux.scala:126:16] wire _GEN_72 = alloc_id_1 == 4'h4; // @[Mux.scala:126:16] wire _GEN_73 = alloc_id_1 == 4'h5; // @[Mux.scala:126:16] wire _GEN_74 = alloc_id_1 == 4'h6; // @[Mux.scala:126:16] wire _GEN_75 = alloc_id_1 == 4'h7; // @[Mux.scala:126:16] wire _GEN_76 = alloc_id_1 == 4'h8; // @[Mux.scala:126:16] wire _GEN_77 = alloc_id_1 == 4'h9; // @[Mux.scala:126:16] wire _GEN_78 = alloc_id_1 == 4'hA; // @[Mux.scala:126:16] wire _GEN_79 = alloc_id_1 == 4'hB; // @[Mux.scala:126:16] wire _GEN_80 = alloc_id_1 == 4'hC; // @[Mux.scala:126:16] wire _GEN_81 = alloc_id_1 == 4'hD; // @[Mux.scala:126:16] wire _GEN_82 = alloc_id_1 == 4'hE; // @[Mux.scala:126:16] wire _GEN_83 = io_alloc_valid_0 & _GEN_67; // @[ReservationStation.scala:26:7, :179:26, :184:25, :350:34, :357:48, :358:28, :361:39] assign new_allocs_oh_ex_0 = _GEN_83 & _GEN_68; // @[ReservationStation.scala:175:30, :179:26, :184:25, :350:34, :357:48, :359:42, :361:39] assign new_allocs_oh_ex_1 = _GEN_83 & _GEN_69; // @[ReservationStation.scala:175:30, :179:26, :184:25, :350:34, :357:48, :359:42, :361:39] assign new_allocs_oh_ex_2 = _GEN_83 & _GEN_70; // @[ReservationStation.scala:175:30, :179:26, :184:25, :350:34, :357:48, :359:42, :361:39] assign new_allocs_oh_ex_3 = _GEN_83 & _GEN_71; // @[ReservationStation.scala:175:30, :179:26, :184:25, :350:34, :357:48, :359:42, :361:39] assign new_allocs_oh_ex_4 = _GEN_83 & _GEN_72; // @[ReservationStation.scala:175:30, :179:26, :184:25, :350:34, :357:48, :359:42, :361:39] assign new_allocs_oh_ex_5 = _GEN_83 & _GEN_73; // @[ReservationStation.scala:175:30, :179:26, :184:25, :350:34, :357:48, :359:42, :361:39] assign new_allocs_oh_ex_6 = _GEN_83 & _GEN_74; // @[ReservationStation.scala:175:30, :179:26, :184:25, :350:34, :357:48, :359:42, :361:39] assign new_allocs_oh_ex_7 = _GEN_83 & _GEN_75; // @[ReservationStation.scala:175:30, :179:26, :184:25, :350:34, :357:48, :359:42, :361:39] assign new_allocs_oh_ex_8 = _GEN_83 & _GEN_76; // @[ReservationStation.scala:175:30, :179:26, :184:25, :350:34, :357:48, :359:42, :361:39] assign new_allocs_oh_ex_9 = _GEN_83 & _GEN_77; // @[ReservationStation.scala:175:30, :179:26, :184:25, :350:34, :357:48, :359:42, :361:39] assign new_allocs_oh_ex_10 = _GEN_83 & _GEN_78; // @[ReservationStation.scala:175:30, :179:26, :184:25, :350:34, :357:48, :359:42, :361:39] assign new_allocs_oh_ex_11 = _GEN_83 & _GEN_79; // @[ReservationStation.scala:175:30, :179:26, :184:25, :350:34, :357:48, :359:42, :361:39] assign new_allocs_oh_ex_12 = _GEN_83 & _GEN_80; // @[ReservationStation.scala:175:30, :179:26, :184:25, :350:34, :357:48, :359:42, :361:39] assign new_allocs_oh_ex_13 = _GEN_83 & _GEN_81; // @[ReservationStation.scala:175:30, :179:26, :184:25, :350:34, :357:48, :359:42, :361:39] assign new_allocs_oh_ex_14 = _GEN_83 & _GEN_82; // @[ReservationStation.scala:175:30, :179:26, :184:25, :350:34, :357:48, :359:42, :361:39] assign new_allocs_oh_ex_15 = _GEN_83 & (&alloc_id_1); // @[Mux.scala:126:16] wire _T_4827 = new_entry_q == 2'h2; // @[ReservationStation.scala:171:23, :350:27] wire [1:0] _is_full_T_9 = _is_full_T_8; // @[ReservationStation.scala:351:33] wire [2:0] _is_full_T_10 = _GEN_55 + {1'h0, _is_full_T_9}; // @[ReservationStation.scala:351:33] wire [1:0] _is_full_T_11 = _is_full_T_10[1:0]; // @[ReservationStation.scala:351:33] wire is_full_2 = _is_full_T_11[1]; // @[ReservationStation.scala:351:{33,72}] wire _alloc_id_T_46 = ~entries_st_0_valid; // @[ReservationStation.scala:119:23, :355:104] wire _alloc_id_T_47 = ~entries_st_1_valid; // @[ReservationStation.scala:119:23, :355:104] wire _alloc_id_T_48 = ~entries_st_2_valid; // @[ReservationStation.scala:119:23, :355:104] wire _alloc_id_T_49 = ~entries_st_3_valid; // @[ReservationStation.scala:119:23, :355:104] wire [1:0] _alloc_id_T_51 = {1'h1, ~_alloc_id_T_48}; // @[Mux.scala:126:16] wire [1:0] _alloc_id_T_52 = _alloc_id_T_47 ? 2'h1 : _alloc_id_T_51; // @[Mux.scala:126:16] wire [1:0] alloc_id_2 = _alloc_id_T_46 ? 2'h0 : _alloc_id_T_52; // @[Mux.scala:126:16] wire [3:0] _GEN_84 = {{entries_st_3_valid}, {entries_st_2_valid}, {entries_st_1_valid}, {entries_st_0_valid}}; // @[ReservationStation.scala:119:23, :357:17] assign io_alloc_ready_0 = io_alloc_valid_0 & (_T_4827 ? ~_GEN_84[alloc_id_2] | _GEN_67 | _GEN_57 : _GEN_67 | _GEN_57); // @[Mux.scala:126:16] wire _GEN_85 = alloc_id_2 == 2'h0; // @[Mux.scala:126:16] wire _GEN_86 = alloc_id_2 == 2'h1; // @[Mux.scala:126:16] wire _GEN_87 = alloc_id_2 == 2'h2; // @[Mux.scala:126:16] wire _GEN_88 = io_alloc_valid_0 & _T_4827 & ~_GEN_84[alloc_id_2]; // @[Mux.scala:126:16] assign new_allocs_oh_st_0 = _GEN_88 & _GEN_85; // @[ReservationStation.scala:176:30, :179:26, :184:25, :350:34, :357:48, :359:42, :361:39] assign new_allocs_oh_st_1 = _GEN_88 & _GEN_86; // @[ReservationStation.scala:176:30, :179:26, :184:25, :350:34, :357:48, :359:42, :361:39] assign new_allocs_oh_st_2 = _GEN_88 & _GEN_87; // @[ReservationStation.scala:176:30, :179:26, :184:25, :350:34, :357:48, :359:42, :361:39] assign new_allocs_oh_st_3 = _GEN_88 & (&alloc_id_2); // @[Mux.scala:126:16] wire [15:0] _a_stride_T = new_entry_cmd_cmd_rs1[31:16]; // @[ReservationStation.scala:171:23, :368:42] wire [15:0] block_stride = new_entry_cmd_cmd_rs1[31:16]; // @[ReservationStation.scala:171:23, :368:42, :376:49] wire [15:0] _c_stride_T = new_entry_cmd_cmd_rs2[63:48]; // @[ReservationStation.scala:171:23, :369:42] wire set_only_strides = new_entry_cmd_cmd_rs1[7]; // @[ReservationStation.scala:171:23, :370:53] wire _a_transpose_T = new_entry_cmd_cmd_rs1[8]; // @[ReservationStation.scala:171:23, :372:47] wire [1:0] id_1 = new_entry_cmd_cmd_rs1[4:3]; // @[ReservationStation.scala:171:23, :375:39] wire [2:0] _repeat_pixels_T = new_entry_cmd_cmd_rs1[10:8]; // @[ReservationStation.scala:171:23, :377:56] wire _repeat_pixels_T_1 = |(_repeat_pixels_T[2:1]); // @[Util.scala:100:12] wire [2:0] repeat_pixels = _repeat_pixels_T_1 ? _repeat_pixels_T : 3'h1; // @[Util.scala:100:{8,12}] wire [3:0] _ld_pixel_repeats_T = {1'h0, repeat_pixels} - 4'h1; // @[Util.scala:100:8] wire [2:0] _ld_pixel_repeats_T_1 = _ld_pixel_repeats_T[2:0]; // @[ReservationStation.scala:379:47] wire [1:0] pool_stride = new_entry_cmd_cmd_rs1[5:4]; // @[ReservationStation.scala:171:23, :381:48] wire _pooling_is_enabled_T = |pool_stride; // @[ReservationStation.scala:381:48, :382:43] wire _issue_valids_T = entries_ld_0_bits_deps_ld_0 | entries_ld_0_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_1 = _issue_valids_T | entries_ld_0_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_2 = _issue_valids_T_1 | entries_ld_0_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_3 = _issue_valids_T_2 | entries_ld_0_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_4 = _issue_valids_T_3 | entries_ld_0_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_5 = _issue_valids_T_4 | entries_ld_0_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_6 = _issue_valids_T_5 | entries_ld_0_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_7 = entries_ld_0_bits_deps_ex_0 | entries_ld_0_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_8 = _issue_valids_T_7 | entries_ld_0_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_9 = _issue_valids_T_8 | entries_ld_0_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_10 = _issue_valids_T_9 | entries_ld_0_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_11 = _issue_valids_T_10 | entries_ld_0_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_12 = _issue_valids_T_11 | entries_ld_0_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_13 = _issue_valids_T_12 | entries_ld_0_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_14 = _issue_valids_T_13 | entries_ld_0_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_15 = _issue_valids_T_14 | entries_ld_0_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_16 = _issue_valids_T_15 | entries_ld_0_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_17 = _issue_valids_T_16 | entries_ld_0_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_18 = _issue_valids_T_17 | entries_ld_0_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_19 = _issue_valids_T_18 | entries_ld_0_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_20 = _issue_valids_T_19 | entries_ld_0_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_21 = _issue_valids_T_20 | entries_ld_0_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_22 = _issue_valids_T_6 | _issue_valids_T_21; // @[ReservationStation.scala:107:{58,64,84}] wire _issue_valids_T_23 = entries_ld_0_bits_deps_st_0 | entries_ld_0_bits_deps_st_1; // @[ReservationStation.scala:107:110, :117:23] wire _issue_valids_T_24 = _issue_valids_T_23 | entries_ld_0_bits_deps_st_2; // @[ReservationStation.scala:107:110, :117:23] wire _issue_valids_T_25 = _issue_valids_T_24 | entries_ld_0_bits_deps_st_3; // @[ReservationStation.scala:107:110, :117:23] wire _issue_valids_T_26 = _issue_valids_T_22 | _issue_valids_T_25; // @[ReservationStation.scala:107:{64,90,110}] wire _issue_valids_T_27 = ~_issue_valids_T_26; // @[ReservationStation.scala:107:{39,90}] wire _issue_valids_T_28 = entries_ld_0_valid & _issue_valids_T_27; // @[ReservationStation.scala:107:39, :117:23, :395:54] wire _issue_valids_T_29 = ~entries_ld_0_bits_issued; // @[ReservationStation.scala:117:23, :395:75] wire issue_valids_0 = _issue_valids_T_28 & _issue_valids_T_29; // @[ReservationStation.scala:395:{54,72,75}] wire _issue_valids_T_30 = entries_ld_1_bits_deps_ld_0 | entries_ld_1_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_31 = _issue_valids_T_30 | entries_ld_1_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_32 = _issue_valids_T_31 | entries_ld_1_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_33 = _issue_valids_T_32 | entries_ld_1_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_34 = _issue_valids_T_33 | entries_ld_1_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_35 = _issue_valids_T_34 | entries_ld_1_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_36 = _issue_valids_T_35 | entries_ld_1_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_37 = entries_ld_1_bits_deps_ex_0 | entries_ld_1_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_38 = _issue_valids_T_37 | entries_ld_1_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_39 = _issue_valids_T_38 | entries_ld_1_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_40 = _issue_valids_T_39 | entries_ld_1_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_41 = _issue_valids_T_40 | entries_ld_1_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_42 = _issue_valids_T_41 | entries_ld_1_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_43 = _issue_valids_T_42 | entries_ld_1_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_44 = _issue_valids_T_43 | entries_ld_1_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_45 = _issue_valids_T_44 | entries_ld_1_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_46 = _issue_valids_T_45 | entries_ld_1_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_47 = _issue_valids_T_46 | entries_ld_1_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_48 = _issue_valids_T_47 | entries_ld_1_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_49 = _issue_valids_T_48 | entries_ld_1_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_50 = _issue_valids_T_49 | entries_ld_1_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_51 = _issue_valids_T_50 | entries_ld_1_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_52 = _issue_valids_T_36 | _issue_valids_T_51; // @[ReservationStation.scala:107:{58,64,84}] wire _issue_valids_T_53 = entries_ld_1_bits_deps_st_0 | entries_ld_1_bits_deps_st_1; // @[ReservationStation.scala:107:110, :117:23] wire _issue_valids_T_54 = _issue_valids_T_53 | entries_ld_1_bits_deps_st_2; // @[ReservationStation.scala:107:110, :117:23] wire _issue_valids_T_55 = _issue_valids_T_54 | entries_ld_1_bits_deps_st_3; // @[ReservationStation.scala:107:110, :117:23] wire _issue_valids_T_56 = _issue_valids_T_52 | _issue_valids_T_55; // @[ReservationStation.scala:107:{64,90,110}] wire _issue_valids_T_57 = ~_issue_valids_T_56; // @[ReservationStation.scala:107:{39,90}] wire _issue_valids_T_58 = entries_ld_1_valid & _issue_valids_T_57; // @[ReservationStation.scala:107:39, :117:23, :395:54] wire _issue_valids_T_59 = ~entries_ld_1_bits_issued; // @[ReservationStation.scala:117:23, :395:75] wire issue_valids_1 = _issue_valids_T_58 & _issue_valids_T_59; // @[ReservationStation.scala:395:{54,72,75}] wire _issue_valids_T_60 = entries_ld_2_bits_deps_ld_0 | entries_ld_2_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_61 = _issue_valids_T_60 | entries_ld_2_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_62 = _issue_valids_T_61 | entries_ld_2_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_63 = _issue_valids_T_62 | entries_ld_2_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_64 = _issue_valids_T_63 | entries_ld_2_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_65 = _issue_valids_T_64 | entries_ld_2_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_66 = _issue_valids_T_65 | entries_ld_2_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_67 = entries_ld_2_bits_deps_ex_0 | entries_ld_2_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_68 = _issue_valids_T_67 | entries_ld_2_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_69 = _issue_valids_T_68 | entries_ld_2_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_70 = _issue_valids_T_69 | entries_ld_2_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_71 = _issue_valids_T_70 | entries_ld_2_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_72 = _issue_valids_T_71 | entries_ld_2_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_73 = _issue_valids_T_72 | entries_ld_2_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_74 = _issue_valids_T_73 | entries_ld_2_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_75 = _issue_valids_T_74 | entries_ld_2_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_76 = _issue_valids_T_75 | entries_ld_2_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_77 = _issue_valids_T_76 | entries_ld_2_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_78 = _issue_valids_T_77 | entries_ld_2_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_79 = _issue_valids_T_78 | entries_ld_2_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_80 = _issue_valids_T_79 | entries_ld_2_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_81 = _issue_valids_T_80 | entries_ld_2_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_82 = _issue_valids_T_66 | _issue_valids_T_81; // @[ReservationStation.scala:107:{58,64,84}] wire _issue_valids_T_83 = entries_ld_2_bits_deps_st_0 | entries_ld_2_bits_deps_st_1; // @[ReservationStation.scala:107:110, :117:23] wire _issue_valids_T_84 = _issue_valids_T_83 | entries_ld_2_bits_deps_st_2; // @[ReservationStation.scala:107:110, :117:23] wire _issue_valids_T_85 = _issue_valids_T_84 | entries_ld_2_bits_deps_st_3; // @[ReservationStation.scala:107:110, :117:23] wire _issue_valids_T_86 = _issue_valids_T_82 | _issue_valids_T_85; // @[ReservationStation.scala:107:{64,90,110}] wire _issue_valids_T_87 = ~_issue_valids_T_86; // @[ReservationStation.scala:107:{39,90}] wire _issue_valids_T_88 = entries_ld_2_valid & _issue_valids_T_87; // @[ReservationStation.scala:107:39, :117:23, :395:54] wire _issue_valids_T_89 = ~entries_ld_2_bits_issued; // @[ReservationStation.scala:117:23, :395:75] wire issue_valids_2 = _issue_valids_T_88 & _issue_valids_T_89; // @[ReservationStation.scala:395:{54,72,75}] wire _issue_valids_T_90 = entries_ld_3_bits_deps_ld_0 | entries_ld_3_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_91 = _issue_valids_T_90 | entries_ld_3_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_92 = _issue_valids_T_91 | entries_ld_3_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_93 = _issue_valids_T_92 | entries_ld_3_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_94 = _issue_valids_T_93 | entries_ld_3_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_95 = _issue_valids_T_94 | entries_ld_3_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_96 = _issue_valids_T_95 | entries_ld_3_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_97 = entries_ld_3_bits_deps_ex_0 | entries_ld_3_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_98 = _issue_valids_T_97 | entries_ld_3_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_99 = _issue_valids_T_98 | entries_ld_3_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_100 = _issue_valids_T_99 | entries_ld_3_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_101 = _issue_valids_T_100 | entries_ld_3_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_102 = _issue_valids_T_101 | entries_ld_3_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_103 = _issue_valids_T_102 | entries_ld_3_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_104 = _issue_valids_T_103 | entries_ld_3_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_105 = _issue_valids_T_104 | entries_ld_3_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_106 = _issue_valids_T_105 | entries_ld_3_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_107 = _issue_valids_T_106 | entries_ld_3_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_108 = _issue_valids_T_107 | entries_ld_3_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_109 = _issue_valids_T_108 | entries_ld_3_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_110 = _issue_valids_T_109 | entries_ld_3_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_111 = _issue_valids_T_110 | entries_ld_3_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_112 = _issue_valids_T_96 | _issue_valids_T_111; // @[ReservationStation.scala:107:{58,64,84}] wire _issue_valids_T_113 = entries_ld_3_bits_deps_st_0 | entries_ld_3_bits_deps_st_1; // @[ReservationStation.scala:107:110, :117:23] wire _issue_valids_T_114 = _issue_valids_T_113 | entries_ld_3_bits_deps_st_2; // @[ReservationStation.scala:107:110, :117:23] wire _issue_valids_T_115 = _issue_valids_T_114 | entries_ld_3_bits_deps_st_3; // @[ReservationStation.scala:107:110, :117:23] wire _issue_valids_T_116 = _issue_valids_T_112 | _issue_valids_T_115; // @[ReservationStation.scala:107:{64,90,110}] wire _issue_valids_T_117 = ~_issue_valids_T_116; // @[ReservationStation.scala:107:{39,90}] wire _issue_valids_T_118 = entries_ld_3_valid & _issue_valids_T_117; // @[ReservationStation.scala:107:39, :117:23, :395:54] wire _issue_valids_T_119 = ~entries_ld_3_bits_issued; // @[ReservationStation.scala:117:23, :395:75] wire issue_valids_3 = _issue_valids_T_118 & _issue_valids_T_119; // @[ReservationStation.scala:395:{54,72,75}] wire _issue_valids_T_120 = entries_ld_4_bits_deps_ld_0 | entries_ld_4_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_121 = _issue_valids_T_120 | entries_ld_4_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_122 = _issue_valids_T_121 | entries_ld_4_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_123 = _issue_valids_T_122 | entries_ld_4_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_124 = _issue_valids_T_123 | entries_ld_4_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_125 = _issue_valids_T_124 | entries_ld_4_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_126 = _issue_valids_T_125 | entries_ld_4_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_127 = entries_ld_4_bits_deps_ex_0 | entries_ld_4_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_128 = _issue_valids_T_127 | entries_ld_4_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_129 = _issue_valids_T_128 | entries_ld_4_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_130 = _issue_valids_T_129 | entries_ld_4_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_131 = _issue_valids_T_130 | entries_ld_4_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_132 = _issue_valids_T_131 | entries_ld_4_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_133 = _issue_valids_T_132 | entries_ld_4_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_134 = _issue_valids_T_133 | entries_ld_4_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_135 = _issue_valids_T_134 | entries_ld_4_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_136 = _issue_valids_T_135 | entries_ld_4_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_137 = _issue_valids_T_136 | entries_ld_4_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_138 = _issue_valids_T_137 | entries_ld_4_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_139 = _issue_valids_T_138 | entries_ld_4_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_140 = _issue_valids_T_139 | entries_ld_4_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_141 = _issue_valids_T_140 | entries_ld_4_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_142 = _issue_valids_T_126 | _issue_valids_T_141; // @[ReservationStation.scala:107:{58,64,84}] wire _issue_valids_T_143 = entries_ld_4_bits_deps_st_0 | entries_ld_4_bits_deps_st_1; // @[ReservationStation.scala:107:110, :117:23] wire _issue_valids_T_144 = _issue_valids_T_143 | entries_ld_4_bits_deps_st_2; // @[ReservationStation.scala:107:110, :117:23] wire _issue_valids_T_145 = _issue_valids_T_144 | entries_ld_4_bits_deps_st_3; // @[ReservationStation.scala:107:110, :117:23] wire _issue_valids_T_146 = _issue_valids_T_142 | _issue_valids_T_145; // @[ReservationStation.scala:107:{64,90,110}] wire _issue_valids_T_147 = ~_issue_valids_T_146; // @[ReservationStation.scala:107:{39,90}] wire _issue_valids_T_148 = entries_ld_4_valid & _issue_valids_T_147; // @[ReservationStation.scala:107:39, :117:23, :395:54] wire _issue_valids_T_149 = ~entries_ld_4_bits_issued; // @[ReservationStation.scala:117:23, :395:75] wire issue_valids_4 = _issue_valids_T_148 & _issue_valids_T_149; // @[ReservationStation.scala:395:{54,72,75}] wire _issue_valids_T_150 = entries_ld_5_bits_deps_ld_0 | entries_ld_5_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_151 = _issue_valids_T_150 | entries_ld_5_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_152 = _issue_valids_T_151 | entries_ld_5_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_153 = _issue_valids_T_152 | entries_ld_5_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_154 = _issue_valids_T_153 | entries_ld_5_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_155 = _issue_valids_T_154 | entries_ld_5_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_156 = _issue_valids_T_155 | entries_ld_5_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_157 = entries_ld_5_bits_deps_ex_0 | entries_ld_5_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_158 = _issue_valids_T_157 | entries_ld_5_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_159 = _issue_valids_T_158 | entries_ld_5_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_160 = _issue_valids_T_159 | entries_ld_5_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_161 = _issue_valids_T_160 | entries_ld_5_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_162 = _issue_valids_T_161 | entries_ld_5_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_163 = _issue_valids_T_162 | entries_ld_5_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_164 = _issue_valids_T_163 | entries_ld_5_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_165 = _issue_valids_T_164 | entries_ld_5_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_166 = _issue_valids_T_165 | entries_ld_5_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_167 = _issue_valids_T_166 | entries_ld_5_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_168 = _issue_valids_T_167 | entries_ld_5_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_169 = _issue_valids_T_168 | entries_ld_5_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_170 = _issue_valids_T_169 | entries_ld_5_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_171 = _issue_valids_T_170 | entries_ld_5_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_172 = _issue_valids_T_156 | _issue_valids_T_171; // @[ReservationStation.scala:107:{58,64,84}] wire _issue_valids_T_173 = entries_ld_5_bits_deps_st_0 | entries_ld_5_bits_deps_st_1; // @[ReservationStation.scala:107:110, :117:23] wire _issue_valids_T_174 = _issue_valids_T_173 | entries_ld_5_bits_deps_st_2; // @[ReservationStation.scala:107:110, :117:23] wire _issue_valids_T_175 = _issue_valids_T_174 | entries_ld_5_bits_deps_st_3; // @[ReservationStation.scala:107:110, :117:23] wire _issue_valids_T_176 = _issue_valids_T_172 | _issue_valids_T_175; // @[ReservationStation.scala:107:{64,90,110}] wire _issue_valids_T_177 = ~_issue_valids_T_176; // @[ReservationStation.scala:107:{39,90}] wire _issue_valids_T_178 = entries_ld_5_valid & _issue_valids_T_177; // @[ReservationStation.scala:107:39, :117:23, :395:54] wire _issue_valids_T_179 = ~entries_ld_5_bits_issued; // @[ReservationStation.scala:117:23, :395:75] wire issue_valids_5 = _issue_valids_T_178 & _issue_valids_T_179; // @[ReservationStation.scala:395:{54,72,75}] wire _issue_valids_T_180 = entries_ld_6_bits_deps_ld_0 | entries_ld_6_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_181 = _issue_valids_T_180 | entries_ld_6_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_182 = _issue_valids_T_181 | entries_ld_6_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_183 = _issue_valids_T_182 | entries_ld_6_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_184 = _issue_valids_T_183 | entries_ld_6_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_185 = _issue_valids_T_184 | entries_ld_6_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_186 = _issue_valids_T_185 | entries_ld_6_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_187 = entries_ld_6_bits_deps_ex_0 | entries_ld_6_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_188 = _issue_valids_T_187 | entries_ld_6_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_189 = _issue_valids_T_188 | entries_ld_6_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_190 = _issue_valids_T_189 | entries_ld_6_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_191 = _issue_valids_T_190 | entries_ld_6_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_192 = _issue_valids_T_191 | entries_ld_6_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_193 = _issue_valids_T_192 | entries_ld_6_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_194 = _issue_valids_T_193 | entries_ld_6_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_195 = _issue_valids_T_194 | entries_ld_6_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_196 = _issue_valids_T_195 | entries_ld_6_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_197 = _issue_valids_T_196 | entries_ld_6_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_198 = _issue_valids_T_197 | entries_ld_6_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_199 = _issue_valids_T_198 | entries_ld_6_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_200 = _issue_valids_T_199 | entries_ld_6_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_201 = _issue_valids_T_200 | entries_ld_6_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_202 = _issue_valids_T_186 | _issue_valids_T_201; // @[ReservationStation.scala:107:{58,64,84}] wire _issue_valids_T_203 = entries_ld_6_bits_deps_st_0 | entries_ld_6_bits_deps_st_1; // @[ReservationStation.scala:107:110, :117:23] wire _issue_valids_T_204 = _issue_valids_T_203 | entries_ld_6_bits_deps_st_2; // @[ReservationStation.scala:107:110, :117:23] wire _issue_valids_T_205 = _issue_valids_T_204 | entries_ld_6_bits_deps_st_3; // @[ReservationStation.scala:107:110, :117:23] wire _issue_valids_T_206 = _issue_valids_T_202 | _issue_valids_T_205; // @[ReservationStation.scala:107:{64,90,110}] wire _issue_valids_T_207 = ~_issue_valids_T_206; // @[ReservationStation.scala:107:{39,90}] wire _issue_valids_T_208 = entries_ld_6_valid & _issue_valids_T_207; // @[ReservationStation.scala:107:39, :117:23, :395:54] wire _issue_valids_T_209 = ~entries_ld_6_bits_issued; // @[ReservationStation.scala:117:23, :395:75] wire issue_valids_6 = _issue_valids_T_208 & _issue_valids_T_209; // @[ReservationStation.scala:395:{54,72,75}] wire _issue_valids_T_210 = entries_ld_7_bits_deps_ld_0 | entries_ld_7_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_211 = _issue_valids_T_210 | entries_ld_7_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_212 = _issue_valids_T_211 | entries_ld_7_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_213 = _issue_valids_T_212 | entries_ld_7_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_214 = _issue_valids_T_213 | entries_ld_7_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_215 = _issue_valids_T_214 | entries_ld_7_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_216 = _issue_valids_T_215 | entries_ld_7_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :117:23] wire _issue_valids_T_217 = entries_ld_7_bits_deps_ex_0 | entries_ld_7_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_218 = _issue_valids_T_217 | entries_ld_7_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_219 = _issue_valids_T_218 | entries_ld_7_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_220 = _issue_valids_T_219 | entries_ld_7_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_221 = _issue_valids_T_220 | entries_ld_7_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_222 = _issue_valids_T_221 | entries_ld_7_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_223 = _issue_valids_T_222 | entries_ld_7_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_224 = _issue_valids_T_223 | entries_ld_7_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_225 = _issue_valids_T_224 | entries_ld_7_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_226 = _issue_valids_T_225 | entries_ld_7_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_227 = _issue_valids_T_226 | entries_ld_7_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_228 = _issue_valids_T_227 | entries_ld_7_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_229 = _issue_valids_T_228 | entries_ld_7_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_230 = _issue_valids_T_229 | entries_ld_7_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_231 = _issue_valids_T_230 | entries_ld_7_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :117:23] wire _issue_valids_T_232 = _issue_valids_T_216 | _issue_valids_T_231; // @[ReservationStation.scala:107:{58,64,84}] wire _issue_valids_T_233 = entries_ld_7_bits_deps_st_0 | entries_ld_7_bits_deps_st_1; // @[ReservationStation.scala:107:110, :117:23] wire _issue_valids_T_234 = _issue_valids_T_233 | entries_ld_7_bits_deps_st_2; // @[ReservationStation.scala:107:110, :117:23] wire _issue_valids_T_235 = _issue_valids_T_234 | entries_ld_7_bits_deps_st_3; // @[ReservationStation.scala:107:110, :117:23] wire _issue_valids_T_236 = _issue_valids_T_232 | _issue_valids_T_235; // @[ReservationStation.scala:107:{64,90,110}] wire _issue_valids_T_237 = ~_issue_valids_T_236; // @[ReservationStation.scala:107:{39,90}] wire _issue_valids_T_238 = entries_ld_7_valid & _issue_valids_T_237; // @[ReservationStation.scala:107:39, :117:23, :395:54] wire _issue_valids_T_239 = ~entries_ld_7_bits_issued; // @[ReservationStation.scala:117:23, :395:75] wire issue_valids_7 = _issue_valids_T_238 & _issue_valids_T_239; // @[ReservationStation.scala:395:{54,72,75}] wire [7:0] _issue_sel_enc_T = {issue_valids_7, 7'h0}; // @[Mux.scala:50:70] wire [7:0] _issue_sel_enc_T_1 = issue_valids_6 ? 8'h40 : _issue_sel_enc_T; // @[Mux.scala:50:70] wire [7:0] _issue_sel_enc_T_2 = issue_valids_5 ? 8'h20 : _issue_sel_enc_T_1; // @[Mux.scala:50:70] wire [7:0] _issue_sel_enc_T_3 = issue_valids_4 ? 8'h10 : _issue_sel_enc_T_2; // @[Mux.scala:50:70] wire [7:0] _issue_sel_enc_T_4 = issue_valids_3 ? 8'h8 : _issue_sel_enc_T_3; // @[Mux.scala:50:70] wire [7:0] _issue_sel_enc_T_5 = issue_valids_2 ? 8'h4 : _issue_sel_enc_T_4; // @[Mux.scala:50:70] wire [7:0] _issue_sel_enc_T_6 = issue_valids_1 ? 8'h2 : _issue_sel_enc_T_5; // @[Mux.scala:50:70] wire [7:0] issue_sel_enc = issue_valids_0 ? 8'h1 : _issue_sel_enc_T_6; // @[Mux.scala:50:70] wire issue_sel_0 = issue_sel_enc[0]; // @[OneHot.scala:83:30] wire issue_sel_1 = issue_sel_enc[1]; // @[OneHot.scala:83:30] wire issue_sel_2 = issue_sel_enc[2]; // @[OneHot.scala:83:30] wire issue_sel_3 = issue_sel_enc[3]; // @[OneHot.scala:83:30] wire issue_sel_4 = issue_sel_enc[4]; // @[OneHot.scala:83:30] wire issue_sel_5 = issue_sel_enc[5]; // @[OneHot.scala:83:30] wire issue_sel_6 = issue_sel_enc[6]; // @[OneHot.scala:83:30] wire issue_sel_7 = issue_sel_enc[7]; // @[OneHot.scala:83:30] wire [1:0] issue_id_lo_lo = {issue_sel_1, issue_sel_0}; // @[OneHot.scala:21:45, :83:30] wire [1:0] issue_id_lo_hi = {issue_sel_3, issue_sel_2}; // @[OneHot.scala:21:45, :83:30] wire [3:0] issue_id_lo = {issue_id_lo_hi, issue_id_lo_lo}; // @[OneHot.scala:21:45] wire [1:0] issue_id_hi_lo = {issue_sel_5, issue_sel_4}; // @[OneHot.scala:21:45, :83:30] wire [1:0] issue_id_hi_hi = {issue_sel_7, issue_sel_6}; // @[OneHot.scala:21:45, :83:30] wire [3:0] issue_id_hi = {issue_id_hi_hi, issue_id_hi_lo}; // @[OneHot.scala:21:45] wire [7:0] _issue_id_T = {issue_id_hi, issue_id_lo}; // @[OneHot.scala:21:45] wire [3:0] issue_id_hi_1 = _issue_id_T[7:4]; // @[OneHot.scala:21:45, :30:18] wire [3:0] issue_id_lo_1 = _issue_id_T[3:0]; // @[OneHot.scala:21:45, :31:18] wire _issue_id_T_1 = |issue_id_hi_1; // @[OneHot.scala:30:18, :32:14] wire [3:0] _issue_id_T_2 = issue_id_hi_1 | issue_id_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] issue_id_hi_2 = _issue_id_T_2[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] issue_id_lo_2 = _issue_id_T_2[1:0]; // @[OneHot.scala:31:18, :32:28] wire _issue_id_T_3 = |issue_id_hi_2; // @[OneHot.scala:30:18, :32:14] wire [1:0] _issue_id_T_4 = issue_id_hi_2 | issue_id_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28] wire _issue_id_T_5 = _issue_id_T_4[1]; // @[OneHot.scala:32:28] wire [1:0] _issue_id_T_6 = {_issue_id_T_3, _issue_id_T_5}; // @[OneHot.scala:32:{10,14}] wire [2:0] issue_id = {_issue_id_T_1, _issue_id_T_6}; // @[OneHot.scala:32:{10,14}] wire [3:0] _global_issue_id_T = {1'h0, issue_id}; // @[OneHot.scala:32:10] assign global_issue_id = {2'h0, _global_issue_id_T}; // @[ReservationStation.scala:398:{30,53}] assign io_issue_ld_rob_id_0 = global_issue_id; // @[ReservationStation.scala:26:7, :398:30] wire _issue_entry_WIRE_142; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_q; // @[Mux.scala:30:73] wire _issue_entry_WIRE_is_config; // @[Mux.scala:30:73] wire _issue_entry_WIRE_opa_valid; // @[Mux.scala:30:73] wire _issue_entry_WIRE_opa_bits_start_is_acc_addr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_opa_bits_start_accumulate; // @[Mux.scala:30:73] wire _issue_entry_WIRE_opa_bits_start_read_full_acc_row; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_opa_bits_start_norm_cmd; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_opa_bits_start_garbage; // @[Mux.scala:30:73] wire _issue_entry_WIRE_opa_bits_start_garbage_bit; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_opa_bits_start_data; // @[Mux.scala:30:73] wire _issue_entry_WIRE_opa_bits_end_is_acc_addr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_opa_bits_end_accumulate; // @[Mux.scala:30:73] wire _issue_entry_WIRE_opa_bits_end_read_full_acc_row; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_opa_bits_end_norm_cmd; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_opa_bits_end_garbage; // @[Mux.scala:30:73] wire _issue_entry_WIRE_opa_bits_end_garbage_bit; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_opa_bits_end_data; // @[Mux.scala:30:73] wire _issue_entry_WIRE_opa_bits_wraps_around; // @[Mux.scala:30:73] wire _issue_entry_WIRE_opa_is_dst; // @[Mux.scala:30:73] wire _issue_entry_WIRE_issued; // @[Mux.scala:30:73] wire _issue_entry_WIRE_complete_on_issue; // @[Mux.scala:30:73] wire [6:0] _issue_entry_WIRE_cmd_cmd_inst_funct; // @[Mux.scala:30:73] assign io_issue_ld_cmd_cmd_inst_funct_0 = issue_entry_bits_cmd_cmd_inst_funct; // @[Mux.scala:30:73] wire [4:0] _issue_entry_WIRE_cmd_cmd_inst_rs2; // @[Mux.scala:30:73] assign io_issue_ld_cmd_cmd_inst_rs2_0 = issue_entry_bits_cmd_cmd_inst_rs2; // @[Mux.scala:30:73] wire [4:0] _issue_entry_WIRE_cmd_cmd_inst_rs1; // @[Mux.scala:30:73] assign io_issue_ld_cmd_cmd_inst_rs1_0 = issue_entry_bits_cmd_cmd_inst_rs1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_cmd_cmd_inst_xd; // @[Mux.scala:30:73] assign io_issue_ld_cmd_cmd_inst_xd_0 = issue_entry_bits_cmd_cmd_inst_xd; // @[Mux.scala:30:73] wire _issue_entry_WIRE_cmd_cmd_inst_xs1; // @[Mux.scala:30:73] assign io_issue_ld_cmd_cmd_inst_xs1_0 = issue_entry_bits_cmd_cmd_inst_xs1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_cmd_cmd_inst_xs2; // @[Mux.scala:30:73] assign io_issue_ld_cmd_cmd_inst_xs2_0 = issue_entry_bits_cmd_cmd_inst_xs2; // @[Mux.scala:30:73] wire [4:0] _issue_entry_WIRE_cmd_cmd_inst_rd; // @[Mux.scala:30:73] assign io_issue_ld_cmd_cmd_inst_rd_0 = issue_entry_bits_cmd_cmd_inst_rd; // @[Mux.scala:30:73] wire [6:0] _issue_entry_WIRE_cmd_cmd_inst_opcode; // @[Mux.scala:30:73] assign io_issue_ld_cmd_cmd_inst_opcode_0 = issue_entry_bits_cmd_cmd_inst_opcode; // @[Mux.scala:30:73] wire [63:0] _issue_entry_WIRE_cmd_cmd_rs1; // @[Mux.scala:30:73] assign io_issue_ld_cmd_cmd_rs1_0 = issue_entry_bits_cmd_cmd_rs1; // @[Mux.scala:30:73] wire [63:0] _issue_entry_WIRE_cmd_cmd_rs2; // @[Mux.scala:30:73] assign io_issue_ld_cmd_cmd_rs2_0 = issue_entry_bits_cmd_cmd_rs2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_cmd_cmd_status_debug; // @[Mux.scala:30:73] assign io_issue_ld_cmd_cmd_status_debug_0 = issue_entry_bits_cmd_cmd_status_debug; // @[Mux.scala:30:73] wire _issue_entry_WIRE_cmd_cmd_status_cease; // @[Mux.scala:30:73] assign io_issue_ld_cmd_cmd_status_cease_0 = issue_entry_bits_cmd_cmd_status_cease; // @[Mux.scala:30:73] wire _issue_entry_WIRE_cmd_cmd_status_wfi; // @[Mux.scala:30:73] assign io_issue_ld_cmd_cmd_status_wfi_0 = issue_entry_bits_cmd_cmd_status_wfi; // @[Mux.scala:30:73] wire [31:0] _issue_entry_WIRE_cmd_cmd_status_isa; // @[Mux.scala:30:73] assign io_issue_ld_cmd_cmd_status_isa_0 = issue_entry_bits_cmd_cmd_status_isa; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_cmd_cmd_status_dprv; // @[Mux.scala:30:73] assign io_issue_ld_cmd_cmd_status_dprv_0 = issue_entry_bits_cmd_cmd_status_dprv; // @[Mux.scala:30:73] wire _issue_entry_WIRE_cmd_cmd_status_dv; // @[Mux.scala:30:73] assign io_issue_ld_cmd_cmd_status_dv_0 = issue_entry_bits_cmd_cmd_status_dv; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_cmd_cmd_status_prv; // @[Mux.scala:30:73] assign io_issue_ld_cmd_cmd_status_prv_0 = issue_entry_bits_cmd_cmd_status_prv; // @[Mux.scala:30:73] wire _issue_entry_WIRE_cmd_cmd_status_v; // @[Mux.scala:30:73] assign io_issue_ld_cmd_cmd_status_v_0 = issue_entry_bits_cmd_cmd_status_v; // @[Mux.scala:30:73] wire _issue_entry_WIRE_cmd_cmd_status_sd; // @[Mux.scala:30:73] assign io_issue_ld_cmd_cmd_status_sd_0 = issue_entry_bits_cmd_cmd_status_sd; // @[Mux.scala:30:73] wire [22:0] _issue_entry_WIRE_cmd_cmd_status_zero2; // @[Mux.scala:30:73] assign io_issue_ld_cmd_cmd_status_zero2_0 = issue_entry_bits_cmd_cmd_status_zero2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_cmd_cmd_status_mpv; // @[Mux.scala:30:73] assign io_issue_ld_cmd_cmd_status_mpv_0 = issue_entry_bits_cmd_cmd_status_mpv; // @[Mux.scala:30:73] wire _issue_entry_WIRE_cmd_cmd_status_gva; // @[Mux.scala:30:73] assign io_issue_ld_cmd_cmd_status_gva_0 = issue_entry_bits_cmd_cmd_status_gva; // @[Mux.scala:30:73] wire _issue_entry_WIRE_cmd_cmd_status_mbe; // @[Mux.scala:30:73] assign io_issue_ld_cmd_cmd_status_mbe_0 = issue_entry_bits_cmd_cmd_status_mbe; // @[Mux.scala:30:73] wire _issue_entry_WIRE_cmd_cmd_status_sbe; // @[Mux.scala:30:73] assign io_issue_ld_cmd_cmd_status_sbe_0 = issue_entry_bits_cmd_cmd_status_sbe; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_cmd_cmd_status_sxl; // @[Mux.scala:30:73] assign io_issue_ld_cmd_cmd_status_sxl_0 = issue_entry_bits_cmd_cmd_status_sxl; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_cmd_cmd_status_uxl; // @[Mux.scala:30:73] assign io_issue_ld_cmd_cmd_status_uxl_0 = issue_entry_bits_cmd_cmd_status_uxl; // @[Mux.scala:30:73] wire _issue_entry_WIRE_cmd_cmd_status_sd_rv32; // @[Mux.scala:30:73] assign io_issue_ld_cmd_cmd_status_sd_rv32_0 = issue_entry_bits_cmd_cmd_status_sd_rv32; // @[Mux.scala:30:73] wire [7:0] _issue_entry_WIRE_cmd_cmd_status_zero1; // @[Mux.scala:30:73] assign io_issue_ld_cmd_cmd_status_zero1_0 = issue_entry_bits_cmd_cmd_status_zero1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_cmd_cmd_status_tsr; // @[Mux.scala:30:73] assign io_issue_ld_cmd_cmd_status_tsr_0 = issue_entry_bits_cmd_cmd_status_tsr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_cmd_cmd_status_tw; // @[Mux.scala:30:73] assign io_issue_ld_cmd_cmd_status_tw_0 = issue_entry_bits_cmd_cmd_status_tw; // @[Mux.scala:30:73] wire _issue_entry_WIRE_cmd_cmd_status_tvm; // @[Mux.scala:30:73] assign io_issue_ld_cmd_cmd_status_tvm_0 = issue_entry_bits_cmd_cmd_status_tvm; // @[Mux.scala:30:73] wire _issue_entry_WIRE_cmd_cmd_status_mxr; // @[Mux.scala:30:73] assign io_issue_ld_cmd_cmd_status_mxr_0 = issue_entry_bits_cmd_cmd_status_mxr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_cmd_cmd_status_sum; // @[Mux.scala:30:73] assign io_issue_ld_cmd_cmd_status_sum_0 = issue_entry_bits_cmd_cmd_status_sum; // @[Mux.scala:30:73] wire _issue_entry_WIRE_cmd_cmd_status_mprv; // @[Mux.scala:30:73] assign io_issue_ld_cmd_cmd_status_mprv_0 = issue_entry_bits_cmd_cmd_status_mprv; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_cmd_cmd_status_xs; // @[Mux.scala:30:73] assign io_issue_ld_cmd_cmd_status_xs_0 = issue_entry_bits_cmd_cmd_status_xs; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_cmd_cmd_status_fs; // @[Mux.scala:30:73] assign io_issue_ld_cmd_cmd_status_fs_0 = issue_entry_bits_cmd_cmd_status_fs; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_cmd_cmd_status_mpp; // @[Mux.scala:30:73] assign io_issue_ld_cmd_cmd_status_mpp_0 = issue_entry_bits_cmd_cmd_status_mpp; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_cmd_cmd_status_vs; // @[Mux.scala:30:73] assign io_issue_ld_cmd_cmd_status_vs_0 = issue_entry_bits_cmd_cmd_status_vs; // @[Mux.scala:30:73] wire _issue_entry_WIRE_cmd_cmd_status_spp; // @[Mux.scala:30:73] assign io_issue_ld_cmd_cmd_status_spp_0 = issue_entry_bits_cmd_cmd_status_spp; // @[Mux.scala:30:73] wire _issue_entry_WIRE_cmd_cmd_status_mpie; // @[Mux.scala:30:73] assign io_issue_ld_cmd_cmd_status_mpie_0 = issue_entry_bits_cmd_cmd_status_mpie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_cmd_cmd_status_ube; // @[Mux.scala:30:73] assign io_issue_ld_cmd_cmd_status_ube_0 = issue_entry_bits_cmd_cmd_status_ube; // @[Mux.scala:30:73] wire _issue_entry_WIRE_cmd_cmd_status_spie; // @[Mux.scala:30:73] assign io_issue_ld_cmd_cmd_status_spie_0 = issue_entry_bits_cmd_cmd_status_spie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_cmd_cmd_status_upie; // @[Mux.scala:30:73] assign io_issue_ld_cmd_cmd_status_upie_0 = issue_entry_bits_cmd_cmd_status_upie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_cmd_cmd_status_mie; // @[Mux.scala:30:73] assign io_issue_ld_cmd_cmd_status_mie_0 = issue_entry_bits_cmd_cmd_status_mie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_cmd_cmd_status_hie; // @[Mux.scala:30:73] assign io_issue_ld_cmd_cmd_status_hie_0 = issue_entry_bits_cmd_cmd_status_hie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_cmd_cmd_status_sie; // @[Mux.scala:30:73] assign io_issue_ld_cmd_cmd_status_sie_0 = issue_entry_bits_cmd_cmd_status_sie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_cmd_cmd_status_uie; // @[Mux.scala:30:73] assign io_issue_ld_cmd_cmd_status_uie_0 = issue_entry_bits_cmd_cmd_status_uie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_cmd_rob_id_valid; // @[Mux.scala:30:73] assign io_issue_ld_cmd_rob_id_valid = issue_entry_bits_cmd_rob_id_valid; // @[Mux.scala:30:73] wire [5:0] _issue_entry_WIRE_cmd_rob_id_bits; // @[Mux.scala:30:73] assign io_issue_ld_cmd_rob_id_bits = issue_entry_bits_cmd_rob_id_bits; // @[Mux.scala:30:73] wire _issue_entry_WIRE_cmd_from_matmul_fsm; // @[Mux.scala:30:73] assign io_issue_ld_cmd_from_matmul_fsm_0 = issue_entry_bits_cmd_from_matmul_fsm; // @[Mux.scala:30:73] wire _issue_entry_WIRE_cmd_from_conv_fsm; // @[Mux.scala:30:73] assign io_issue_ld_cmd_from_conv_fsm_0 = issue_entry_bits_cmd_from_conv_fsm; // @[Mux.scala:30:73] wire _issue_entry_WIRE_deps_ld_0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_deps_ld_1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_deps_ld_2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_deps_ld_3; // @[Mux.scala:30:73] wire _issue_entry_WIRE_deps_ld_4; // @[Mux.scala:30:73] wire _issue_entry_WIRE_deps_ld_5; // @[Mux.scala:30:73] wire _issue_entry_WIRE_deps_ld_6; // @[Mux.scala:30:73] wire _issue_entry_WIRE_deps_ld_7; // @[Mux.scala:30:73] wire _issue_entry_WIRE_deps_ex_0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_deps_ex_1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_deps_ex_2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_deps_ex_3; // @[Mux.scala:30:73] wire _issue_entry_WIRE_deps_ex_4; // @[Mux.scala:30:73] wire _issue_entry_WIRE_deps_ex_5; // @[Mux.scala:30:73] wire _issue_entry_WIRE_deps_ex_6; // @[Mux.scala:30:73] wire _issue_entry_WIRE_deps_ex_7; // @[Mux.scala:30:73] wire _issue_entry_WIRE_deps_ex_8; // @[Mux.scala:30:73] wire _issue_entry_WIRE_deps_ex_9; // @[Mux.scala:30:73] wire _issue_entry_WIRE_deps_ex_10; // @[Mux.scala:30:73] wire _issue_entry_WIRE_deps_ex_11; // @[Mux.scala:30:73] wire _issue_entry_WIRE_deps_ex_12; // @[Mux.scala:30:73] wire _issue_entry_WIRE_deps_ex_13; // @[Mux.scala:30:73] wire _issue_entry_WIRE_deps_ex_14; // @[Mux.scala:30:73] wire _issue_entry_WIRE_deps_ex_15; // @[Mux.scala:30:73] wire _issue_entry_WIRE_deps_st_0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_deps_st_1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_deps_st_2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_deps_st_3; // @[Mux.scala:30:73] wire [31:0] _issue_entry_WIRE_allocated_at; // @[Mux.scala:30:73] wire issue_entry_bits_opa_bits_start_is_acc_addr; // @[Mux.scala:30:73] wire issue_entry_bits_opa_bits_start_accumulate; // @[Mux.scala:30:73] wire issue_entry_bits_opa_bits_start_read_full_acc_row; // @[Mux.scala:30:73] wire [2:0] issue_entry_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73] wire [10:0] issue_entry_bits_opa_bits_start_garbage; // @[Mux.scala:30:73] wire issue_entry_bits_opa_bits_start_garbage_bit; // @[Mux.scala:30:73] wire [13:0] issue_entry_bits_opa_bits_start_data; // @[Mux.scala:30:73] wire issue_entry_bits_opa_bits_end_is_acc_addr; // @[Mux.scala:30:73] wire issue_entry_bits_opa_bits_end_accumulate; // @[Mux.scala:30:73] wire issue_entry_bits_opa_bits_end_read_full_acc_row; // @[Mux.scala:30:73] wire [2:0] issue_entry_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73] wire [10:0] issue_entry_bits_opa_bits_end_garbage; // @[Mux.scala:30:73] wire issue_entry_bits_opa_bits_end_garbage_bit; // @[Mux.scala:30:73] wire [13:0] issue_entry_bits_opa_bits_end_data; // @[Mux.scala:30:73] wire issue_entry_bits_opa_bits_wraps_around; // @[Mux.scala:30:73] wire issue_entry_bits_opa_valid; // @[Mux.scala:30:73] wire issue_entry_bits_deps_ld_0; // @[Mux.scala:30:73] wire issue_entry_bits_deps_ld_1; // @[Mux.scala:30:73] wire issue_entry_bits_deps_ld_2; // @[Mux.scala:30:73] wire issue_entry_bits_deps_ld_3; // @[Mux.scala:30:73] wire issue_entry_bits_deps_ld_4; // @[Mux.scala:30:73] wire issue_entry_bits_deps_ld_5; // @[Mux.scala:30:73] wire issue_entry_bits_deps_ld_6; // @[Mux.scala:30:73] wire issue_entry_bits_deps_ld_7; // @[Mux.scala:30:73] wire issue_entry_bits_deps_ex_0; // @[Mux.scala:30:73] wire issue_entry_bits_deps_ex_1; // @[Mux.scala:30:73] wire issue_entry_bits_deps_ex_2; // @[Mux.scala:30:73] wire issue_entry_bits_deps_ex_3; // @[Mux.scala:30:73] wire issue_entry_bits_deps_ex_4; // @[Mux.scala:30:73] wire issue_entry_bits_deps_ex_5; // @[Mux.scala:30:73] wire issue_entry_bits_deps_ex_6; // @[Mux.scala:30:73] wire issue_entry_bits_deps_ex_7; // @[Mux.scala:30:73] wire issue_entry_bits_deps_ex_8; // @[Mux.scala:30:73] wire issue_entry_bits_deps_ex_9; // @[Mux.scala:30:73] wire issue_entry_bits_deps_ex_10; // @[Mux.scala:30:73] wire issue_entry_bits_deps_ex_11; // @[Mux.scala:30:73] wire issue_entry_bits_deps_ex_12; // @[Mux.scala:30:73] wire issue_entry_bits_deps_ex_13; // @[Mux.scala:30:73] wire issue_entry_bits_deps_ex_14; // @[Mux.scala:30:73] wire issue_entry_bits_deps_ex_15; // @[Mux.scala:30:73] wire issue_entry_bits_deps_st_0; // @[Mux.scala:30:73] wire issue_entry_bits_deps_st_1; // @[Mux.scala:30:73] wire issue_entry_bits_deps_st_2; // @[Mux.scala:30:73] wire issue_entry_bits_deps_st_3; // @[Mux.scala:30:73] wire [1:0] issue_entry_bits_q; // @[Mux.scala:30:73] wire issue_entry_bits_is_config; // @[Mux.scala:30:73] wire issue_entry_bits_opa_is_dst; // @[Mux.scala:30:73] wire issue_entry_bits_issued; // @[Mux.scala:30:73] wire issue_entry_bits_complete_on_issue; // @[Mux.scala:30:73] wire [31:0] issue_entry_bits_allocated_at; // @[Mux.scala:30:73] wire issue_entry_valid; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_141; // @[Mux.scala:30:73] assign issue_entry_bits_q = _issue_entry_WIRE_q; // @[Mux.scala:30:73] wire _issue_entry_WIRE_140; // @[Mux.scala:30:73] assign issue_entry_bits_is_config = _issue_entry_WIRE_is_config; // @[Mux.scala:30:73] wire _issue_entry_WIRE_116_valid; // @[Mux.scala:30:73] assign issue_entry_bits_opa_valid = _issue_entry_WIRE_opa_valid; // @[Mux.scala:30:73] wire _issue_entry_WIRE_116_bits_start_is_acc_addr; // @[Mux.scala:30:73] assign issue_entry_bits_opa_bits_start_is_acc_addr = _issue_entry_WIRE_opa_bits_start_is_acc_addr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_116_bits_start_accumulate; // @[Mux.scala:30:73] assign issue_entry_bits_opa_bits_start_accumulate = _issue_entry_WIRE_opa_bits_start_accumulate; // @[Mux.scala:30:73] wire _issue_entry_WIRE_116_bits_start_read_full_acc_row; // @[Mux.scala:30:73] assign issue_entry_bits_opa_bits_start_read_full_acc_row = _issue_entry_WIRE_opa_bits_start_read_full_acc_row; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_116_bits_start_norm_cmd; // @[Mux.scala:30:73] assign issue_entry_bits_opa_bits_start_norm_cmd = _issue_entry_WIRE_opa_bits_start_norm_cmd; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_116_bits_start_garbage; // @[Mux.scala:30:73] assign issue_entry_bits_opa_bits_start_garbage = _issue_entry_WIRE_opa_bits_start_garbage; // @[Mux.scala:30:73] wire _issue_entry_WIRE_116_bits_start_garbage_bit; // @[Mux.scala:30:73] assign issue_entry_bits_opa_bits_start_garbage_bit = _issue_entry_WIRE_opa_bits_start_garbage_bit; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_116_bits_start_data; // @[Mux.scala:30:73] assign issue_entry_bits_opa_bits_start_data = _issue_entry_WIRE_opa_bits_start_data; // @[Mux.scala:30:73] wire _issue_entry_WIRE_116_bits_end_is_acc_addr; // @[Mux.scala:30:73] assign issue_entry_bits_opa_bits_end_is_acc_addr = _issue_entry_WIRE_opa_bits_end_is_acc_addr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_116_bits_end_accumulate; // @[Mux.scala:30:73] assign issue_entry_bits_opa_bits_end_accumulate = _issue_entry_WIRE_opa_bits_end_accumulate; // @[Mux.scala:30:73] wire _issue_entry_WIRE_116_bits_end_read_full_acc_row; // @[Mux.scala:30:73] assign issue_entry_bits_opa_bits_end_read_full_acc_row = _issue_entry_WIRE_opa_bits_end_read_full_acc_row; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_116_bits_end_norm_cmd; // @[Mux.scala:30:73] assign issue_entry_bits_opa_bits_end_norm_cmd = _issue_entry_WIRE_opa_bits_end_norm_cmd; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_116_bits_end_garbage; // @[Mux.scala:30:73] assign issue_entry_bits_opa_bits_end_garbage = _issue_entry_WIRE_opa_bits_end_garbage; // @[Mux.scala:30:73] wire _issue_entry_WIRE_116_bits_end_garbage_bit; // @[Mux.scala:30:73] assign issue_entry_bits_opa_bits_end_garbage_bit = _issue_entry_WIRE_opa_bits_end_garbage_bit; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_116_bits_end_data; // @[Mux.scala:30:73] assign issue_entry_bits_opa_bits_end_data = _issue_entry_WIRE_opa_bits_end_data; // @[Mux.scala:30:73] wire _issue_entry_WIRE_116_bits_wraps_around; // @[Mux.scala:30:73] assign issue_entry_bits_opa_bits_wraps_around = _issue_entry_WIRE_opa_bits_wraps_around; // @[Mux.scala:30:73] wire _issue_entry_WIRE_115; // @[Mux.scala:30:73] assign issue_entry_bits_opa_is_dst = _issue_entry_WIRE_opa_is_dst; // @[Mux.scala:30:73] wire _issue_entry_WIRE_90; // @[Mux.scala:30:73] assign issue_entry_bits_issued = _issue_entry_WIRE_issued; // @[Mux.scala:30:73] wire _issue_entry_WIRE_89; // @[Mux.scala:30:73] assign issue_entry_bits_complete_on_issue = _issue_entry_WIRE_complete_on_issue; // @[Mux.scala:30:73] wire [6:0] _issue_entry_WIRE_33_cmd_inst_funct; // @[Mux.scala:30:73] assign issue_entry_bits_cmd_cmd_inst_funct = _issue_entry_WIRE_cmd_cmd_inst_funct; // @[Mux.scala:30:73] wire [4:0] _issue_entry_WIRE_33_cmd_inst_rs2; // @[Mux.scala:30:73] assign issue_entry_bits_cmd_cmd_inst_rs2 = _issue_entry_WIRE_cmd_cmd_inst_rs2; // @[Mux.scala:30:73] wire [4:0] _issue_entry_WIRE_33_cmd_inst_rs1; // @[Mux.scala:30:73] assign issue_entry_bits_cmd_cmd_inst_rs1 = _issue_entry_WIRE_cmd_cmd_inst_rs1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_33_cmd_inst_xd; // @[Mux.scala:30:73] assign issue_entry_bits_cmd_cmd_inst_xd = _issue_entry_WIRE_cmd_cmd_inst_xd; // @[Mux.scala:30:73] wire _issue_entry_WIRE_33_cmd_inst_xs1; // @[Mux.scala:30:73] assign issue_entry_bits_cmd_cmd_inst_xs1 = _issue_entry_WIRE_cmd_cmd_inst_xs1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_33_cmd_inst_xs2; // @[Mux.scala:30:73] assign issue_entry_bits_cmd_cmd_inst_xs2 = _issue_entry_WIRE_cmd_cmd_inst_xs2; // @[Mux.scala:30:73] wire [4:0] _issue_entry_WIRE_33_cmd_inst_rd; // @[Mux.scala:30:73] assign issue_entry_bits_cmd_cmd_inst_rd = _issue_entry_WIRE_cmd_cmd_inst_rd; // @[Mux.scala:30:73] wire [6:0] _issue_entry_WIRE_33_cmd_inst_opcode; // @[Mux.scala:30:73] assign issue_entry_bits_cmd_cmd_inst_opcode = _issue_entry_WIRE_cmd_cmd_inst_opcode; // @[Mux.scala:30:73] wire [63:0] _issue_entry_WIRE_33_cmd_rs1; // @[Mux.scala:30:73] assign issue_entry_bits_cmd_cmd_rs1 = _issue_entry_WIRE_cmd_cmd_rs1; // @[Mux.scala:30:73] wire [63:0] _issue_entry_WIRE_33_cmd_rs2; // @[Mux.scala:30:73] assign issue_entry_bits_cmd_cmd_rs2 = _issue_entry_WIRE_cmd_cmd_rs2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_33_cmd_status_debug; // @[Mux.scala:30:73] assign issue_entry_bits_cmd_cmd_status_debug = _issue_entry_WIRE_cmd_cmd_status_debug; // @[Mux.scala:30:73] wire _issue_entry_WIRE_33_cmd_status_cease; // @[Mux.scala:30:73] assign issue_entry_bits_cmd_cmd_status_cease = _issue_entry_WIRE_cmd_cmd_status_cease; // @[Mux.scala:30:73] wire _issue_entry_WIRE_33_cmd_status_wfi; // @[Mux.scala:30:73] assign issue_entry_bits_cmd_cmd_status_wfi = _issue_entry_WIRE_cmd_cmd_status_wfi; // @[Mux.scala:30:73] wire [31:0] _issue_entry_WIRE_33_cmd_status_isa; // @[Mux.scala:30:73] assign issue_entry_bits_cmd_cmd_status_isa = _issue_entry_WIRE_cmd_cmd_status_isa; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_33_cmd_status_dprv; // @[Mux.scala:30:73] assign issue_entry_bits_cmd_cmd_status_dprv = _issue_entry_WIRE_cmd_cmd_status_dprv; // @[Mux.scala:30:73] wire _issue_entry_WIRE_33_cmd_status_dv; // @[Mux.scala:30:73] assign issue_entry_bits_cmd_cmd_status_dv = _issue_entry_WIRE_cmd_cmd_status_dv; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_33_cmd_status_prv; // @[Mux.scala:30:73] assign issue_entry_bits_cmd_cmd_status_prv = _issue_entry_WIRE_cmd_cmd_status_prv; // @[Mux.scala:30:73] wire _issue_entry_WIRE_33_cmd_status_v; // @[Mux.scala:30:73] assign issue_entry_bits_cmd_cmd_status_v = _issue_entry_WIRE_cmd_cmd_status_v; // @[Mux.scala:30:73] wire _issue_entry_WIRE_33_cmd_status_sd; // @[Mux.scala:30:73] assign issue_entry_bits_cmd_cmd_status_sd = _issue_entry_WIRE_cmd_cmd_status_sd; // @[Mux.scala:30:73] wire [22:0] _issue_entry_WIRE_33_cmd_status_zero2; // @[Mux.scala:30:73] assign issue_entry_bits_cmd_cmd_status_zero2 = _issue_entry_WIRE_cmd_cmd_status_zero2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_33_cmd_status_mpv; // @[Mux.scala:30:73] assign issue_entry_bits_cmd_cmd_status_mpv = _issue_entry_WIRE_cmd_cmd_status_mpv; // @[Mux.scala:30:73] wire _issue_entry_WIRE_33_cmd_status_gva; // @[Mux.scala:30:73] assign issue_entry_bits_cmd_cmd_status_gva = _issue_entry_WIRE_cmd_cmd_status_gva; // @[Mux.scala:30:73] wire _issue_entry_WIRE_33_cmd_status_mbe; // @[Mux.scala:30:73] assign issue_entry_bits_cmd_cmd_status_mbe = _issue_entry_WIRE_cmd_cmd_status_mbe; // @[Mux.scala:30:73] wire _issue_entry_WIRE_33_cmd_status_sbe; // @[Mux.scala:30:73] assign issue_entry_bits_cmd_cmd_status_sbe = _issue_entry_WIRE_cmd_cmd_status_sbe; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_33_cmd_status_sxl; // @[Mux.scala:30:73] assign issue_entry_bits_cmd_cmd_status_sxl = _issue_entry_WIRE_cmd_cmd_status_sxl; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_33_cmd_status_uxl; // @[Mux.scala:30:73] assign issue_entry_bits_cmd_cmd_status_uxl = _issue_entry_WIRE_cmd_cmd_status_uxl; // @[Mux.scala:30:73] wire _issue_entry_WIRE_33_cmd_status_sd_rv32; // @[Mux.scala:30:73] assign issue_entry_bits_cmd_cmd_status_sd_rv32 = _issue_entry_WIRE_cmd_cmd_status_sd_rv32; // @[Mux.scala:30:73] wire [7:0] _issue_entry_WIRE_33_cmd_status_zero1; // @[Mux.scala:30:73] assign issue_entry_bits_cmd_cmd_status_zero1 = _issue_entry_WIRE_cmd_cmd_status_zero1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_33_cmd_status_tsr; // @[Mux.scala:30:73] assign issue_entry_bits_cmd_cmd_status_tsr = _issue_entry_WIRE_cmd_cmd_status_tsr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_33_cmd_status_tw; // @[Mux.scala:30:73] assign issue_entry_bits_cmd_cmd_status_tw = _issue_entry_WIRE_cmd_cmd_status_tw; // @[Mux.scala:30:73] wire _issue_entry_WIRE_33_cmd_status_tvm; // @[Mux.scala:30:73] assign issue_entry_bits_cmd_cmd_status_tvm = _issue_entry_WIRE_cmd_cmd_status_tvm; // @[Mux.scala:30:73] wire _issue_entry_WIRE_33_cmd_status_mxr; // @[Mux.scala:30:73] assign issue_entry_bits_cmd_cmd_status_mxr = _issue_entry_WIRE_cmd_cmd_status_mxr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_33_cmd_status_sum; // @[Mux.scala:30:73] assign issue_entry_bits_cmd_cmd_status_sum = _issue_entry_WIRE_cmd_cmd_status_sum; // @[Mux.scala:30:73] wire _issue_entry_WIRE_33_cmd_status_mprv; // @[Mux.scala:30:73] assign issue_entry_bits_cmd_cmd_status_mprv = _issue_entry_WIRE_cmd_cmd_status_mprv; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_33_cmd_status_xs; // @[Mux.scala:30:73] assign issue_entry_bits_cmd_cmd_status_xs = _issue_entry_WIRE_cmd_cmd_status_xs; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_33_cmd_status_fs; // @[Mux.scala:30:73] assign issue_entry_bits_cmd_cmd_status_fs = _issue_entry_WIRE_cmd_cmd_status_fs; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_33_cmd_status_mpp; // @[Mux.scala:30:73] assign issue_entry_bits_cmd_cmd_status_mpp = _issue_entry_WIRE_cmd_cmd_status_mpp; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_33_cmd_status_vs; // @[Mux.scala:30:73] assign issue_entry_bits_cmd_cmd_status_vs = _issue_entry_WIRE_cmd_cmd_status_vs; // @[Mux.scala:30:73] wire _issue_entry_WIRE_33_cmd_status_spp; // @[Mux.scala:30:73] assign issue_entry_bits_cmd_cmd_status_spp = _issue_entry_WIRE_cmd_cmd_status_spp; // @[Mux.scala:30:73] wire _issue_entry_WIRE_33_cmd_status_mpie; // @[Mux.scala:30:73] assign issue_entry_bits_cmd_cmd_status_mpie = _issue_entry_WIRE_cmd_cmd_status_mpie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_33_cmd_status_ube; // @[Mux.scala:30:73] assign issue_entry_bits_cmd_cmd_status_ube = _issue_entry_WIRE_cmd_cmd_status_ube; // @[Mux.scala:30:73] wire _issue_entry_WIRE_33_cmd_status_spie; // @[Mux.scala:30:73] assign issue_entry_bits_cmd_cmd_status_spie = _issue_entry_WIRE_cmd_cmd_status_spie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_33_cmd_status_upie; // @[Mux.scala:30:73] assign issue_entry_bits_cmd_cmd_status_upie = _issue_entry_WIRE_cmd_cmd_status_upie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_33_cmd_status_mie; // @[Mux.scala:30:73] assign issue_entry_bits_cmd_cmd_status_mie = _issue_entry_WIRE_cmd_cmd_status_mie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_33_cmd_status_hie; // @[Mux.scala:30:73] assign issue_entry_bits_cmd_cmd_status_hie = _issue_entry_WIRE_cmd_cmd_status_hie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_33_cmd_status_sie; // @[Mux.scala:30:73] assign issue_entry_bits_cmd_cmd_status_sie = _issue_entry_WIRE_cmd_cmd_status_sie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_33_cmd_status_uie; // @[Mux.scala:30:73] assign issue_entry_bits_cmd_cmd_status_uie = _issue_entry_WIRE_cmd_cmd_status_uie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_33_rob_id_valid; // @[Mux.scala:30:73] assign issue_entry_bits_cmd_rob_id_valid = _issue_entry_WIRE_cmd_rob_id_valid; // @[Mux.scala:30:73] wire [5:0] _issue_entry_WIRE_33_rob_id_bits; // @[Mux.scala:30:73] assign issue_entry_bits_cmd_rob_id_bits = _issue_entry_WIRE_cmd_rob_id_bits; // @[Mux.scala:30:73] wire _issue_entry_WIRE_33_from_matmul_fsm; // @[Mux.scala:30:73] assign issue_entry_bits_cmd_from_matmul_fsm = _issue_entry_WIRE_cmd_from_matmul_fsm; // @[Mux.scala:30:73] wire _issue_entry_WIRE_33_from_conv_fsm; // @[Mux.scala:30:73] assign issue_entry_bits_cmd_from_conv_fsm = _issue_entry_WIRE_cmd_from_conv_fsm; // @[Mux.scala:30:73] wire _issue_entry_WIRE_24_0; // @[Mux.scala:30:73] assign issue_entry_bits_deps_ld_0 = _issue_entry_WIRE_deps_ld_0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_24_1; // @[Mux.scala:30:73] assign issue_entry_bits_deps_ld_1 = _issue_entry_WIRE_deps_ld_1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_24_2; // @[Mux.scala:30:73] assign issue_entry_bits_deps_ld_2 = _issue_entry_WIRE_deps_ld_2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_24_3; // @[Mux.scala:30:73] assign issue_entry_bits_deps_ld_3 = _issue_entry_WIRE_deps_ld_3; // @[Mux.scala:30:73] wire _issue_entry_WIRE_24_4; // @[Mux.scala:30:73] assign issue_entry_bits_deps_ld_4 = _issue_entry_WIRE_deps_ld_4; // @[Mux.scala:30:73] wire _issue_entry_WIRE_24_5; // @[Mux.scala:30:73] assign issue_entry_bits_deps_ld_5 = _issue_entry_WIRE_deps_ld_5; // @[Mux.scala:30:73] wire _issue_entry_WIRE_24_6; // @[Mux.scala:30:73] assign issue_entry_bits_deps_ld_6 = _issue_entry_WIRE_deps_ld_6; // @[Mux.scala:30:73] wire _issue_entry_WIRE_24_7; // @[Mux.scala:30:73] assign issue_entry_bits_deps_ld_7 = _issue_entry_WIRE_deps_ld_7; // @[Mux.scala:30:73] wire _issue_entry_WIRE_7_0; // @[Mux.scala:30:73] assign issue_entry_bits_deps_ex_0 = _issue_entry_WIRE_deps_ex_0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_7_1; // @[Mux.scala:30:73] assign issue_entry_bits_deps_ex_1 = _issue_entry_WIRE_deps_ex_1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_7_2; // @[Mux.scala:30:73] assign issue_entry_bits_deps_ex_2 = _issue_entry_WIRE_deps_ex_2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_7_3; // @[Mux.scala:30:73] assign issue_entry_bits_deps_ex_3 = _issue_entry_WIRE_deps_ex_3; // @[Mux.scala:30:73] wire _issue_entry_WIRE_7_4; // @[Mux.scala:30:73] assign issue_entry_bits_deps_ex_4 = _issue_entry_WIRE_deps_ex_4; // @[Mux.scala:30:73] wire _issue_entry_WIRE_7_5; // @[Mux.scala:30:73] assign issue_entry_bits_deps_ex_5 = _issue_entry_WIRE_deps_ex_5; // @[Mux.scala:30:73] wire _issue_entry_WIRE_7_6; // @[Mux.scala:30:73] assign issue_entry_bits_deps_ex_6 = _issue_entry_WIRE_deps_ex_6; // @[Mux.scala:30:73] wire _issue_entry_WIRE_7_7; // @[Mux.scala:30:73] assign issue_entry_bits_deps_ex_7 = _issue_entry_WIRE_deps_ex_7; // @[Mux.scala:30:73] wire _issue_entry_WIRE_7_8; // @[Mux.scala:30:73] assign issue_entry_bits_deps_ex_8 = _issue_entry_WIRE_deps_ex_8; // @[Mux.scala:30:73] wire _issue_entry_WIRE_7_9; // @[Mux.scala:30:73] assign issue_entry_bits_deps_ex_9 = _issue_entry_WIRE_deps_ex_9; // @[Mux.scala:30:73] wire _issue_entry_WIRE_7_10; // @[Mux.scala:30:73] assign issue_entry_bits_deps_ex_10 = _issue_entry_WIRE_deps_ex_10; // @[Mux.scala:30:73] wire _issue_entry_WIRE_7_11; // @[Mux.scala:30:73] assign issue_entry_bits_deps_ex_11 = _issue_entry_WIRE_deps_ex_11; // @[Mux.scala:30:73] wire _issue_entry_WIRE_7_12; // @[Mux.scala:30:73] assign issue_entry_bits_deps_ex_12 = _issue_entry_WIRE_deps_ex_12; // @[Mux.scala:30:73] wire _issue_entry_WIRE_7_13; // @[Mux.scala:30:73] assign issue_entry_bits_deps_ex_13 = _issue_entry_WIRE_deps_ex_13; // @[Mux.scala:30:73] wire _issue_entry_WIRE_7_14; // @[Mux.scala:30:73] assign issue_entry_bits_deps_ex_14 = _issue_entry_WIRE_deps_ex_14; // @[Mux.scala:30:73] wire _issue_entry_WIRE_7_15; // @[Mux.scala:30:73] assign issue_entry_bits_deps_ex_15 = _issue_entry_WIRE_deps_ex_15; // @[Mux.scala:30:73] wire _issue_entry_WIRE_2_0; // @[Mux.scala:30:73] assign issue_entry_bits_deps_st_0 = _issue_entry_WIRE_deps_st_0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_2_1; // @[Mux.scala:30:73] assign issue_entry_bits_deps_st_1 = _issue_entry_WIRE_deps_st_1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_2_2; // @[Mux.scala:30:73] assign issue_entry_bits_deps_st_2 = _issue_entry_WIRE_deps_st_2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_2_3; // @[Mux.scala:30:73] assign issue_entry_bits_deps_st_3 = _issue_entry_WIRE_deps_st_3; // @[Mux.scala:30:73] wire [31:0] _issue_entry_WIRE_1; // @[Mux.scala:30:73] assign issue_entry_bits_allocated_at = _issue_entry_WIRE_allocated_at; // @[Mux.scala:30:73] wire [31:0] _issue_entry_T = issue_sel_0 ? entries_ld_0_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_1 = issue_sel_1 ? entries_ld_1_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_2 = issue_sel_2 ? entries_ld_2_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_3 = issue_sel_3 ? entries_ld_3_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_4 = issue_sel_4 ? entries_ld_4_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_5 = issue_sel_5 ? entries_ld_5_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_6 = issue_sel_6 ? entries_ld_6_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_7 = issue_sel_7 ? entries_ld_7_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_8 = _issue_entry_T | _issue_entry_T_1; // @[Mux.scala:30:73] wire [31:0] _issue_entry_T_9 = _issue_entry_T_8 | _issue_entry_T_2; // @[Mux.scala:30:73] wire [31:0] _issue_entry_T_10 = _issue_entry_T_9 | _issue_entry_T_3; // @[Mux.scala:30:73] wire [31:0] _issue_entry_T_11 = _issue_entry_T_10 | _issue_entry_T_4; // @[Mux.scala:30:73] wire [31:0] _issue_entry_T_12 = _issue_entry_T_11 | _issue_entry_T_5; // @[Mux.scala:30:73] wire [31:0] _issue_entry_T_13 = _issue_entry_T_12 | _issue_entry_T_6; // @[Mux.scala:30:73] wire [31:0] _issue_entry_T_14 = _issue_entry_T_13 | _issue_entry_T_7; // @[Mux.scala:30:73] assign _issue_entry_WIRE_1 = _issue_entry_T_14; // @[Mux.scala:30:73] assign _issue_entry_WIRE_allocated_at = _issue_entry_WIRE_1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_3; // @[Mux.scala:30:73] assign _issue_entry_WIRE_deps_st_0 = _issue_entry_WIRE_2_0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_4; // @[Mux.scala:30:73] assign _issue_entry_WIRE_deps_st_1 = _issue_entry_WIRE_2_1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_5; // @[Mux.scala:30:73] assign _issue_entry_WIRE_deps_st_2 = _issue_entry_WIRE_2_2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_6; // @[Mux.scala:30:73] assign _issue_entry_WIRE_deps_st_3 = _issue_entry_WIRE_2_3; // @[Mux.scala:30:73] wire _issue_entry_T_15 = issue_sel_0 & entries_ld_0_bits_deps_st_0; // @[OneHot.scala:83:30] wire _issue_entry_T_16 = issue_sel_1 & entries_ld_1_bits_deps_st_0; // @[OneHot.scala:83:30] wire _issue_entry_T_17 = issue_sel_2 & entries_ld_2_bits_deps_st_0; // @[OneHot.scala:83:30] wire _issue_entry_T_18 = issue_sel_3 & entries_ld_3_bits_deps_st_0; // @[OneHot.scala:83:30] wire _issue_entry_T_19 = issue_sel_4 & entries_ld_4_bits_deps_st_0; // @[OneHot.scala:83:30] wire _issue_entry_T_20 = issue_sel_5 & entries_ld_5_bits_deps_st_0; // @[OneHot.scala:83:30] wire _issue_entry_T_21 = issue_sel_6 & entries_ld_6_bits_deps_st_0; // @[OneHot.scala:83:30] wire _issue_entry_T_22 = issue_sel_7 & entries_ld_7_bits_deps_st_0; // @[OneHot.scala:83:30] wire _issue_entry_T_23 = _issue_entry_T_15 | _issue_entry_T_16; // @[Mux.scala:30:73] wire _issue_entry_T_24 = _issue_entry_T_23 | _issue_entry_T_17; // @[Mux.scala:30:73] wire _issue_entry_T_25 = _issue_entry_T_24 | _issue_entry_T_18; // @[Mux.scala:30:73] wire _issue_entry_T_26 = _issue_entry_T_25 | _issue_entry_T_19; // @[Mux.scala:30:73] wire _issue_entry_T_27 = _issue_entry_T_26 | _issue_entry_T_20; // @[Mux.scala:30:73] wire _issue_entry_T_28 = _issue_entry_T_27 | _issue_entry_T_21; // @[Mux.scala:30:73] wire _issue_entry_T_29 = _issue_entry_T_28 | _issue_entry_T_22; // @[Mux.scala:30:73] assign _issue_entry_WIRE_3 = _issue_entry_T_29; // @[Mux.scala:30:73] assign _issue_entry_WIRE_2_0 = _issue_entry_WIRE_3; // @[Mux.scala:30:73] wire _issue_entry_T_30 = issue_sel_0 & entries_ld_0_bits_deps_st_1; // @[OneHot.scala:83:30] wire _issue_entry_T_31 = issue_sel_1 & entries_ld_1_bits_deps_st_1; // @[OneHot.scala:83:30] wire _issue_entry_T_32 = issue_sel_2 & entries_ld_2_bits_deps_st_1; // @[OneHot.scala:83:30] wire _issue_entry_T_33 = issue_sel_3 & entries_ld_3_bits_deps_st_1; // @[OneHot.scala:83:30] wire _issue_entry_T_34 = issue_sel_4 & entries_ld_4_bits_deps_st_1; // @[OneHot.scala:83:30] wire _issue_entry_T_35 = issue_sel_5 & entries_ld_5_bits_deps_st_1; // @[OneHot.scala:83:30] wire _issue_entry_T_36 = issue_sel_6 & entries_ld_6_bits_deps_st_1; // @[OneHot.scala:83:30] wire _issue_entry_T_37 = issue_sel_7 & entries_ld_7_bits_deps_st_1; // @[OneHot.scala:83:30] wire _issue_entry_T_38 = _issue_entry_T_30 | _issue_entry_T_31; // @[Mux.scala:30:73] wire _issue_entry_T_39 = _issue_entry_T_38 | _issue_entry_T_32; // @[Mux.scala:30:73] wire _issue_entry_T_40 = _issue_entry_T_39 | _issue_entry_T_33; // @[Mux.scala:30:73] wire _issue_entry_T_41 = _issue_entry_T_40 | _issue_entry_T_34; // @[Mux.scala:30:73] wire _issue_entry_T_42 = _issue_entry_T_41 | _issue_entry_T_35; // @[Mux.scala:30:73] wire _issue_entry_T_43 = _issue_entry_T_42 | _issue_entry_T_36; // @[Mux.scala:30:73] wire _issue_entry_T_44 = _issue_entry_T_43 | _issue_entry_T_37; // @[Mux.scala:30:73] assign _issue_entry_WIRE_4 = _issue_entry_T_44; // @[Mux.scala:30:73] assign _issue_entry_WIRE_2_1 = _issue_entry_WIRE_4; // @[Mux.scala:30:73] wire _issue_entry_T_45 = issue_sel_0 & entries_ld_0_bits_deps_st_2; // @[OneHot.scala:83:30] wire _issue_entry_T_46 = issue_sel_1 & entries_ld_1_bits_deps_st_2; // @[OneHot.scala:83:30] wire _issue_entry_T_47 = issue_sel_2 & entries_ld_2_bits_deps_st_2; // @[OneHot.scala:83:30] wire _issue_entry_T_48 = issue_sel_3 & entries_ld_3_bits_deps_st_2; // @[OneHot.scala:83:30] wire _issue_entry_T_49 = issue_sel_4 & entries_ld_4_bits_deps_st_2; // @[OneHot.scala:83:30] wire _issue_entry_T_50 = issue_sel_5 & entries_ld_5_bits_deps_st_2; // @[OneHot.scala:83:30] wire _issue_entry_T_51 = issue_sel_6 & entries_ld_6_bits_deps_st_2; // @[OneHot.scala:83:30] wire _issue_entry_T_52 = issue_sel_7 & entries_ld_7_bits_deps_st_2; // @[OneHot.scala:83:30] wire _issue_entry_T_53 = _issue_entry_T_45 | _issue_entry_T_46; // @[Mux.scala:30:73] wire _issue_entry_T_54 = _issue_entry_T_53 | _issue_entry_T_47; // @[Mux.scala:30:73] wire _issue_entry_T_55 = _issue_entry_T_54 | _issue_entry_T_48; // @[Mux.scala:30:73] wire _issue_entry_T_56 = _issue_entry_T_55 | _issue_entry_T_49; // @[Mux.scala:30:73] wire _issue_entry_T_57 = _issue_entry_T_56 | _issue_entry_T_50; // @[Mux.scala:30:73] wire _issue_entry_T_58 = _issue_entry_T_57 | _issue_entry_T_51; // @[Mux.scala:30:73] wire _issue_entry_T_59 = _issue_entry_T_58 | _issue_entry_T_52; // @[Mux.scala:30:73] assign _issue_entry_WIRE_5 = _issue_entry_T_59; // @[Mux.scala:30:73] assign _issue_entry_WIRE_2_2 = _issue_entry_WIRE_5; // @[Mux.scala:30:73] wire _issue_entry_T_60 = issue_sel_0 & entries_ld_0_bits_deps_st_3; // @[OneHot.scala:83:30] wire _issue_entry_T_61 = issue_sel_1 & entries_ld_1_bits_deps_st_3; // @[OneHot.scala:83:30] wire _issue_entry_T_62 = issue_sel_2 & entries_ld_2_bits_deps_st_3; // @[OneHot.scala:83:30] wire _issue_entry_T_63 = issue_sel_3 & entries_ld_3_bits_deps_st_3; // @[OneHot.scala:83:30] wire _issue_entry_T_64 = issue_sel_4 & entries_ld_4_bits_deps_st_3; // @[OneHot.scala:83:30] wire _issue_entry_T_65 = issue_sel_5 & entries_ld_5_bits_deps_st_3; // @[OneHot.scala:83:30] wire _issue_entry_T_66 = issue_sel_6 & entries_ld_6_bits_deps_st_3; // @[OneHot.scala:83:30] wire _issue_entry_T_67 = issue_sel_7 & entries_ld_7_bits_deps_st_3; // @[OneHot.scala:83:30] wire _issue_entry_T_68 = _issue_entry_T_60 | _issue_entry_T_61; // @[Mux.scala:30:73] wire _issue_entry_T_69 = _issue_entry_T_68 | _issue_entry_T_62; // @[Mux.scala:30:73] wire _issue_entry_T_70 = _issue_entry_T_69 | _issue_entry_T_63; // @[Mux.scala:30:73] wire _issue_entry_T_71 = _issue_entry_T_70 | _issue_entry_T_64; // @[Mux.scala:30:73] wire _issue_entry_T_72 = _issue_entry_T_71 | _issue_entry_T_65; // @[Mux.scala:30:73] wire _issue_entry_T_73 = _issue_entry_T_72 | _issue_entry_T_66; // @[Mux.scala:30:73] wire _issue_entry_T_74 = _issue_entry_T_73 | _issue_entry_T_67; // @[Mux.scala:30:73] assign _issue_entry_WIRE_6 = _issue_entry_T_74; // @[Mux.scala:30:73] assign _issue_entry_WIRE_2_3 = _issue_entry_WIRE_6; // @[Mux.scala:30:73] wire _issue_entry_WIRE_8; // @[Mux.scala:30:73] assign _issue_entry_WIRE_deps_ex_0 = _issue_entry_WIRE_7_0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_9; // @[Mux.scala:30:73] assign _issue_entry_WIRE_deps_ex_1 = _issue_entry_WIRE_7_1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_10; // @[Mux.scala:30:73] assign _issue_entry_WIRE_deps_ex_2 = _issue_entry_WIRE_7_2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_11; // @[Mux.scala:30:73] assign _issue_entry_WIRE_deps_ex_3 = _issue_entry_WIRE_7_3; // @[Mux.scala:30:73] wire _issue_entry_WIRE_12; // @[Mux.scala:30:73] assign _issue_entry_WIRE_deps_ex_4 = _issue_entry_WIRE_7_4; // @[Mux.scala:30:73] wire _issue_entry_WIRE_13; // @[Mux.scala:30:73] assign _issue_entry_WIRE_deps_ex_5 = _issue_entry_WIRE_7_5; // @[Mux.scala:30:73] wire _issue_entry_WIRE_14; // @[Mux.scala:30:73] assign _issue_entry_WIRE_deps_ex_6 = _issue_entry_WIRE_7_6; // @[Mux.scala:30:73] wire _issue_entry_WIRE_15; // @[Mux.scala:30:73] assign _issue_entry_WIRE_deps_ex_7 = _issue_entry_WIRE_7_7; // @[Mux.scala:30:73] wire _issue_entry_WIRE_16; // @[Mux.scala:30:73] assign _issue_entry_WIRE_deps_ex_8 = _issue_entry_WIRE_7_8; // @[Mux.scala:30:73] wire _issue_entry_WIRE_17; // @[Mux.scala:30:73] assign _issue_entry_WIRE_deps_ex_9 = _issue_entry_WIRE_7_9; // @[Mux.scala:30:73] wire _issue_entry_WIRE_18; // @[Mux.scala:30:73] assign _issue_entry_WIRE_deps_ex_10 = _issue_entry_WIRE_7_10; // @[Mux.scala:30:73] wire _issue_entry_WIRE_19; // @[Mux.scala:30:73] assign _issue_entry_WIRE_deps_ex_11 = _issue_entry_WIRE_7_11; // @[Mux.scala:30:73] wire _issue_entry_WIRE_20; // @[Mux.scala:30:73] assign _issue_entry_WIRE_deps_ex_12 = _issue_entry_WIRE_7_12; // @[Mux.scala:30:73] wire _issue_entry_WIRE_21; // @[Mux.scala:30:73] assign _issue_entry_WIRE_deps_ex_13 = _issue_entry_WIRE_7_13; // @[Mux.scala:30:73] wire _issue_entry_WIRE_22; // @[Mux.scala:30:73] assign _issue_entry_WIRE_deps_ex_14 = _issue_entry_WIRE_7_14; // @[Mux.scala:30:73] wire _issue_entry_WIRE_23; // @[Mux.scala:30:73] assign _issue_entry_WIRE_deps_ex_15 = _issue_entry_WIRE_7_15; // @[Mux.scala:30:73] wire _issue_entry_T_75 = issue_sel_0 & entries_ld_0_bits_deps_ex_0; // @[OneHot.scala:83:30] wire _issue_entry_T_76 = issue_sel_1 & entries_ld_1_bits_deps_ex_0; // @[OneHot.scala:83:30] wire _issue_entry_T_77 = issue_sel_2 & entries_ld_2_bits_deps_ex_0; // @[OneHot.scala:83:30] wire _issue_entry_T_78 = issue_sel_3 & entries_ld_3_bits_deps_ex_0; // @[OneHot.scala:83:30] wire _issue_entry_T_79 = issue_sel_4 & entries_ld_4_bits_deps_ex_0; // @[OneHot.scala:83:30] wire _issue_entry_T_80 = issue_sel_5 & entries_ld_5_bits_deps_ex_0; // @[OneHot.scala:83:30] wire _issue_entry_T_81 = issue_sel_6 & entries_ld_6_bits_deps_ex_0; // @[OneHot.scala:83:30] wire _issue_entry_T_82 = issue_sel_7 & entries_ld_7_bits_deps_ex_0; // @[OneHot.scala:83:30] wire _issue_entry_T_83 = _issue_entry_T_75 | _issue_entry_T_76; // @[Mux.scala:30:73] wire _issue_entry_T_84 = _issue_entry_T_83 | _issue_entry_T_77; // @[Mux.scala:30:73] wire _issue_entry_T_85 = _issue_entry_T_84 | _issue_entry_T_78; // @[Mux.scala:30:73] wire _issue_entry_T_86 = _issue_entry_T_85 | _issue_entry_T_79; // @[Mux.scala:30:73] wire _issue_entry_T_87 = _issue_entry_T_86 | _issue_entry_T_80; // @[Mux.scala:30:73] wire _issue_entry_T_88 = _issue_entry_T_87 | _issue_entry_T_81; // @[Mux.scala:30:73] wire _issue_entry_T_89 = _issue_entry_T_88 | _issue_entry_T_82; // @[Mux.scala:30:73] assign _issue_entry_WIRE_8 = _issue_entry_T_89; // @[Mux.scala:30:73] assign _issue_entry_WIRE_7_0 = _issue_entry_WIRE_8; // @[Mux.scala:30:73] wire _issue_entry_T_90 = issue_sel_0 & entries_ld_0_bits_deps_ex_1; // @[OneHot.scala:83:30] wire _issue_entry_T_91 = issue_sel_1 & entries_ld_1_bits_deps_ex_1; // @[OneHot.scala:83:30] wire _issue_entry_T_92 = issue_sel_2 & entries_ld_2_bits_deps_ex_1; // @[OneHot.scala:83:30] wire _issue_entry_T_93 = issue_sel_3 & entries_ld_3_bits_deps_ex_1; // @[OneHot.scala:83:30] wire _issue_entry_T_94 = issue_sel_4 & entries_ld_4_bits_deps_ex_1; // @[OneHot.scala:83:30] wire _issue_entry_T_95 = issue_sel_5 & entries_ld_5_bits_deps_ex_1; // @[OneHot.scala:83:30] wire _issue_entry_T_96 = issue_sel_6 & entries_ld_6_bits_deps_ex_1; // @[OneHot.scala:83:30] wire _issue_entry_T_97 = issue_sel_7 & entries_ld_7_bits_deps_ex_1; // @[OneHot.scala:83:30] wire _issue_entry_T_98 = _issue_entry_T_90 | _issue_entry_T_91; // @[Mux.scala:30:73] wire _issue_entry_T_99 = _issue_entry_T_98 | _issue_entry_T_92; // @[Mux.scala:30:73] wire _issue_entry_T_100 = _issue_entry_T_99 | _issue_entry_T_93; // @[Mux.scala:30:73] wire _issue_entry_T_101 = _issue_entry_T_100 | _issue_entry_T_94; // @[Mux.scala:30:73] wire _issue_entry_T_102 = _issue_entry_T_101 | _issue_entry_T_95; // @[Mux.scala:30:73] wire _issue_entry_T_103 = _issue_entry_T_102 | _issue_entry_T_96; // @[Mux.scala:30:73] wire _issue_entry_T_104 = _issue_entry_T_103 | _issue_entry_T_97; // @[Mux.scala:30:73] assign _issue_entry_WIRE_9 = _issue_entry_T_104; // @[Mux.scala:30:73] assign _issue_entry_WIRE_7_1 = _issue_entry_WIRE_9; // @[Mux.scala:30:73] wire _issue_entry_T_105 = issue_sel_0 & entries_ld_0_bits_deps_ex_2; // @[OneHot.scala:83:30] wire _issue_entry_T_106 = issue_sel_1 & entries_ld_1_bits_deps_ex_2; // @[OneHot.scala:83:30] wire _issue_entry_T_107 = issue_sel_2 & entries_ld_2_bits_deps_ex_2; // @[OneHot.scala:83:30] wire _issue_entry_T_108 = issue_sel_3 & entries_ld_3_bits_deps_ex_2; // @[OneHot.scala:83:30] wire _issue_entry_T_109 = issue_sel_4 & entries_ld_4_bits_deps_ex_2; // @[OneHot.scala:83:30] wire _issue_entry_T_110 = issue_sel_5 & entries_ld_5_bits_deps_ex_2; // @[OneHot.scala:83:30] wire _issue_entry_T_111 = issue_sel_6 & entries_ld_6_bits_deps_ex_2; // @[OneHot.scala:83:30] wire _issue_entry_T_112 = issue_sel_7 & entries_ld_7_bits_deps_ex_2; // @[OneHot.scala:83:30] wire _issue_entry_T_113 = _issue_entry_T_105 | _issue_entry_T_106; // @[Mux.scala:30:73] wire _issue_entry_T_114 = _issue_entry_T_113 | _issue_entry_T_107; // @[Mux.scala:30:73] wire _issue_entry_T_115 = _issue_entry_T_114 | _issue_entry_T_108; // @[Mux.scala:30:73] wire _issue_entry_T_116 = _issue_entry_T_115 | _issue_entry_T_109; // @[Mux.scala:30:73] wire _issue_entry_T_117 = _issue_entry_T_116 | _issue_entry_T_110; // @[Mux.scala:30:73] wire _issue_entry_T_118 = _issue_entry_T_117 | _issue_entry_T_111; // @[Mux.scala:30:73] wire _issue_entry_T_119 = _issue_entry_T_118 | _issue_entry_T_112; // @[Mux.scala:30:73] assign _issue_entry_WIRE_10 = _issue_entry_T_119; // @[Mux.scala:30:73] assign _issue_entry_WIRE_7_2 = _issue_entry_WIRE_10; // @[Mux.scala:30:73] wire _issue_entry_T_120 = issue_sel_0 & entries_ld_0_bits_deps_ex_3; // @[OneHot.scala:83:30] wire _issue_entry_T_121 = issue_sel_1 & entries_ld_1_bits_deps_ex_3; // @[OneHot.scala:83:30] wire _issue_entry_T_122 = issue_sel_2 & entries_ld_2_bits_deps_ex_3; // @[OneHot.scala:83:30] wire _issue_entry_T_123 = issue_sel_3 & entries_ld_3_bits_deps_ex_3; // @[OneHot.scala:83:30] wire _issue_entry_T_124 = issue_sel_4 & entries_ld_4_bits_deps_ex_3; // @[OneHot.scala:83:30] wire _issue_entry_T_125 = issue_sel_5 & entries_ld_5_bits_deps_ex_3; // @[OneHot.scala:83:30] wire _issue_entry_T_126 = issue_sel_6 & entries_ld_6_bits_deps_ex_3; // @[OneHot.scala:83:30] wire _issue_entry_T_127 = issue_sel_7 & entries_ld_7_bits_deps_ex_3; // @[OneHot.scala:83:30] wire _issue_entry_T_128 = _issue_entry_T_120 | _issue_entry_T_121; // @[Mux.scala:30:73] wire _issue_entry_T_129 = _issue_entry_T_128 | _issue_entry_T_122; // @[Mux.scala:30:73] wire _issue_entry_T_130 = _issue_entry_T_129 | _issue_entry_T_123; // @[Mux.scala:30:73] wire _issue_entry_T_131 = _issue_entry_T_130 | _issue_entry_T_124; // @[Mux.scala:30:73] wire _issue_entry_T_132 = _issue_entry_T_131 | _issue_entry_T_125; // @[Mux.scala:30:73] wire _issue_entry_T_133 = _issue_entry_T_132 | _issue_entry_T_126; // @[Mux.scala:30:73] wire _issue_entry_T_134 = _issue_entry_T_133 | _issue_entry_T_127; // @[Mux.scala:30:73] assign _issue_entry_WIRE_11 = _issue_entry_T_134; // @[Mux.scala:30:73] assign _issue_entry_WIRE_7_3 = _issue_entry_WIRE_11; // @[Mux.scala:30:73] wire _issue_entry_T_135 = issue_sel_0 & entries_ld_0_bits_deps_ex_4; // @[OneHot.scala:83:30] wire _issue_entry_T_136 = issue_sel_1 & entries_ld_1_bits_deps_ex_4; // @[OneHot.scala:83:30] wire _issue_entry_T_137 = issue_sel_2 & entries_ld_2_bits_deps_ex_4; // @[OneHot.scala:83:30] wire _issue_entry_T_138 = issue_sel_3 & entries_ld_3_bits_deps_ex_4; // @[OneHot.scala:83:30] wire _issue_entry_T_139 = issue_sel_4 & entries_ld_4_bits_deps_ex_4; // @[OneHot.scala:83:30] wire _issue_entry_T_140 = issue_sel_5 & entries_ld_5_bits_deps_ex_4; // @[OneHot.scala:83:30] wire _issue_entry_T_141 = issue_sel_6 & entries_ld_6_bits_deps_ex_4; // @[OneHot.scala:83:30] wire _issue_entry_T_142 = issue_sel_7 & entries_ld_7_bits_deps_ex_4; // @[OneHot.scala:83:30] wire _issue_entry_T_143 = _issue_entry_T_135 | _issue_entry_T_136; // @[Mux.scala:30:73] wire _issue_entry_T_144 = _issue_entry_T_143 | _issue_entry_T_137; // @[Mux.scala:30:73] wire _issue_entry_T_145 = _issue_entry_T_144 | _issue_entry_T_138; // @[Mux.scala:30:73] wire _issue_entry_T_146 = _issue_entry_T_145 | _issue_entry_T_139; // @[Mux.scala:30:73] wire _issue_entry_T_147 = _issue_entry_T_146 | _issue_entry_T_140; // @[Mux.scala:30:73] wire _issue_entry_T_148 = _issue_entry_T_147 | _issue_entry_T_141; // @[Mux.scala:30:73] wire _issue_entry_T_149 = _issue_entry_T_148 | _issue_entry_T_142; // @[Mux.scala:30:73] assign _issue_entry_WIRE_12 = _issue_entry_T_149; // @[Mux.scala:30:73] assign _issue_entry_WIRE_7_4 = _issue_entry_WIRE_12; // @[Mux.scala:30:73] wire _issue_entry_T_150 = issue_sel_0 & entries_ld_0_bits_deps_ex_5; // @[OneHot.scala:83:30] wire _issue_entry_T_151 = issue_sel_1 & entries_ld_1_bits_deps_ex_5; // @[OneHot.scala:83:30] wire _issue_entry_T_152 = issue_sel_2 & entries_ld_2_bits_deps_ex_5; // @[OneHot.scala:83:30] wire _issue_entry_T_153 = issue_sel_3 & entries_ld_3_bits_deps_ex_5; // @[OneHot.scala:83:30] wire _issue_entry_T_154 = issue_sel_4 & entries_ld_4_bits_deps_ex_5; // @[OneHot.scala:83:30] wire _issue_entry_T_155 = issue_sel_5 & entries_ld_5_bits_deps_ex_5; // @[OneHot.scala:83:30] wire _issue_entry_T_156 = issue_sel_6 & entries_ld_6_bits_deps_ex_5; // @[OneHot.scala:83:30] wire _issue_entry_T_157 = issue_sel_7 & entries_ld_7_bits_deps_ex_5; // @[OneHot.scala:83:30] wire _issue_entry_T_158 = _issue_entry_T_150 | _issue_entry_T_151; // @[Mux.scala:30:73] wire _issue_entry_T_159 = _issue_entry_T_158 | _issue_entry_T_152; // @[Mux.scala:30:73] wire _issue_entry_T_160 = _issue_entry_T_159 | _issue_entry_T_153; // @[Mux.scala:30:73] wire _issue_entry_T_161 = _issue_entry_T_160 | _issue_entry_T_154; // @[Mux.scala:30:73] wire _issue_entry_T_162 = _issue_entry_T_161 | _issue_entry_T_155; // @[Mux.scala:30:73] wire _issue_entry_T_163 = _issue_entry_T_162 | _issue_entry_T_156; // @[Mux.scala:30:73] wire _issue_entry_T_164 = _issue_entry_T_163 | _issue_entry_T_157; // @[Mux.scala:30:73] assign _issue_entry_WIRE_13 = _issue_entry_T_164; // @[Mux.scala:30:73] assign _issue_entry_WIRE_7_5 = _issue_entry_WIRE_13; // @[Mux.scala:30:73] wire _issue_entry_T_165 = issue_sel_0 & entries_ld_0_bits_deps_ex_6; // @[OneHot.scala:83:30] wire _issue_entry_T_166 = issue_sel_1 & entries_ld_1_bits_deps_ex_6; // @[OneHot.scala:83:30] wire _issue_entry_T_167 = issue_sel_2 & entries_ld_2_bits_deps_ex_6; // @[OneHot.scala:83:30] wire _issue_entry_T_168 = issue_sel_3 & entries_ld_3_bits_deps_ex_6; // @[OneHot.scala:83:30] wire _issue_entry_T_169 = issue_sel_4 & entries_ld_4_bits_deps_ex_6; // @[OneHot.scala:83:30] wire _issue_entry_T_170 = issue_sel_5 & entries_ld_5_bits_deps_ex_6; // @[OneHot.scala:83:30] wire _issue_entry_T_171 = issue_sel_6 & entries_ld_6_bits_deps_ex_6; // @[OneHot.scala:83:30] wire _issue_entry_T_172 = issue_sel_7 & entries_ld_7_bits_deps_ex_6; // @[OneHot.scala:83:30] wire _issue_entry_T_173 = _issue_entry_T_165 | _issue_entry_T_166; // @[Mux.scala:30:73] wire _issue_entry_T_174 = _issue_entry_T_173 | _issue_entry_T_167; // @[Mux.scala:30:73] wire _issue_entry_T_175 = _issue_entry_T_174 | _issue_entry_T_168; // @[Mux.scala:30:73] wire _issue_entry_T_176 = _issue_entry_T_175 | _issue_entry_T_169; // @[Mux.scala:30:73] wire _issue_entry_T_177 = _issue_entry_T_176 | _issue_entry_T_170; // @[Mux.scala:30:73] wire _issue_entry_T_178 = _issue_entry_T_177 | _issue_entry_T_171; // @[Mux.scala:30:73] wire _issue_entry_T_179 = _issue_entry_T_178 | _issue_entry_T_172; // @[Mux.scala:30:73] assign _issue_entry_WIRE_14 = _issue_entry_T_179; // @[Mux.scala:30:73] assign _issue_entry_WIRE_7_6 = _issue_entry_WIRE_14; // @[Mux.scala:30:73] wire _issue_entry_T_180 = issue_sel_0 & entries_ld_0_bits_deps_ex_7; // @[OneHot.scala:83:30] wire _issue_entry_T_181 = issue_sel_1 & entries_ld_1_bits_deps_ex_7; // @[OneHot.scala:83:30] wire _issue_entry_T_182 = issue_sel_2 & entries_ld_2_bits_deps_ex_7; // @[OneHot.scala:83:30] wire _issue_entry_T_183 = issue_sel_3 & entries_ld_3_bits_deps_ex_7; // @[OneHot.scala:83:30] wire _issue_entry_T_184 = issue_sel_4 & entries_ld_4_bits_deps_ex_7; // @[OneHot.scala:83:30] wire _issue_entry_T_185 = issue_sel_5 & entries_ld_5_bits_deps_ex_7; // @[OneHot.scala:83:30] wire _issue_entry_T_186 = issue_sel_6 & entries_ld_6_bits_deps_ex_7; // @[OneHot.scala:83:30] wire _issue_entry_T_187 = issue_sel_7 & entries_ld_7_bits_deps_ex_7; // @[OneHot.scala:83:30] wire _issue_entry_T_188 = _issue_entry_T_180 | _issue_entry_T_181; // @[Mux.scala:30:73] wire _issue_entry_T_189 = _issue_entry_T_188 | _issue_entry_T_182; // @[Mux.scala:30:73] wire _issue_entry_T_190 = _issue_entry_T_189 | _issue_entry_T_183; // @[Mux.scala:30:73] wire _issue_entry_T_191 = _issue_entry_T_190 | _issue_entry_T_184; // @[Mux.scala:30:73] wire _issue_entry_T_192 = _issue_entry_T_191 | _issue_entry_T_185; // @[Mux.scala:30:73] wire _issue_entry_T_193 = _issue_entry_T_192 | _issue_entry_T_186; // @[Mux.scala:30:73] wire _issue_entry_T_194 = _issue_entry_T_193 | _issue_entry_T_187; // @[Mux.scala:30:73] assign _issue_entry_WIRE_15 = _issue_entry_T_194; // @[Mux.scala:30:73] assign _issue_entry_WIRE_7_7 = _issue_entry_WIRE_15; // @[Mux.scala:30:73] wire _issue_entry_T_195 = issue_sel_0 & entries_ld_0_bits_deps_ex_8; // @[OneHot.scala:83:30] wire _issue_entry_T_196 = issue_sel_1 & entries_ld_1_bits_deps_ex_8; // @[OneHot.scala:83:30] wire _issue_entry_T_197 = issue_sel_2 & entries_ld_2_bits_deps_ex_8; // @[OneHot.scala:83:30] wire _issue_entry_T_198 = issue_sel_3 & entries_ld_3_bits_deps_ex_8; // @[OneHot.scala:83:30] wire _issue_entry_T_199 = issue_sel_4 & entries_ld_4_bits_deps_ex_8; // @[OneHot.scala:83:30] wire _issue_entry_T_200 = issue_sel_5 & entries_ld_5_bits_deps_ex_8; // @[OneHot.scala:83:30] wire _issue_entry_T_201 = issue_sel_6 & entries_ld_6_bits_deps_ex_8; // @[OneHot.scala:83:30] wire _issue_entry_T_202 = issue_sel_7 & entries_ld_7_bits_deps_ex_8; // @[OneHot.scala:83:30] wire _issue_entry_T_203 = _issue_entry_T_195 | _issue_entry_T_196; // @[Mux.scala:30:73] wire _issue_entry_T_204 = _issue_entry_T_203 | _issue_entry_T_197; // @[Mux.scala:30:73] wire _issue_entry_T_205 = _issue_entry_T_204 | _issue_entry_T_198; // @[Mux.scala:30:73] wire _issue_entry_T_206 = _issue_entry_T_205 | _issue_entry_T_199; // @[Mux.scala:30:73] wire _issue_entry_T_207 = _issue_entry_T_206 | _issue_entry_T_200; // @[Mux.scala:30:73] wire _issue_entry_T_208 = _issue_entry_T_207 | _issue_entry_T_201; // @[Mux.scala:30:73] wire _issue_entry_T_209 = _issue_entry_T_208 | _issue_entry_T_202; // @[Mux.scala:30:73] assign _issue_entry_WIRE_16 = _issue_entry_T_209; // @[Mux.scala:30:73] assign _issue_entry_WIRE_7_8 = _issue_entry_WIRE_16; // @[Mux.scala:30:73] wire _issue_entry_T_210 = issue_sel_0 & entries_ld_0_bits_deps_ex_9; // @[OneHot.scala:83:30] wire _issue_entry_T_211 = issue_sel_1 & entries_ld_1_bits_deps_ex_9; // @[OneHot.scala:83:30] wire _issue_entry_T_212 = issue_sel_2 & entries_ld_2_bits_deps_ex_9; // @[OneHot.scala:83:30] wire _issue_entry_T_213 = issue_sel_3 & entries_ld_3_bits_deps_ex_9; // @[OneHot.scala:83:30] wire _issue_entry_T_214 = issue_sel_4 & entries_ld_4_bits_deps_ex_9; // @[OneHot.scala:83:30] wire _issue_entry_T_215 = issue_sel_5 & entries_ld_5_bits_deps_ex_9; // @[OneHot.scala:83:30] wire _issue_entry_T_216 = issue_sel_6 & entries_ld_6_bits_deps_ex_9; // @[OneHot.scala:83:30] wire _issue_entry_T_217 = issue_sel_7 & entries_ld_7_bits_deps_ex_9; // @[OneHot.scala:83:30] wire _issue_entry_T_218 = _issue_entry_T_210 | _issue_entry_T_211; // @[Mux.scala:30:73] wire _issue_entry_T_219 = _issue_entry_T_218 | _issue_entry_T_212; // @[Mux.scala:30:73] wire _issue_entry_T_220 = _issue_entry_T_219 | _issue_entry_T_213; // @[Mux.scala:30:73] wire _issue_entry_T_221 = _issue_entry_T_220 | _issue_entry_T_214; // @[Mux.scala:30:73] wire _issue_entry_T_222 = _issue_entry_T_221 | _issue_entry_T_215; // @[Mux.scala:30:73] wire _issue_entry_T_223 = _issue_entry_T_222 | _issue_entry_T_216; // @[Mux.scala:30:73] wire _issue_entry_T_224 = _issue_entry_T_223 | _issue_entry_T_217; // @[Mux.scala:30:73] assign _issue_entry_WIRE_17 = _issue_entry_T_224; // @[Mux.scala:30:73] assign _issue_entry_WIRE_7_9 = _issue_entry_WIRE_17; // @[Mux.scala:30:73] wire _issue_entry_T_225 = issue_sel_0 & entries_ld_0_bits_deps_ex_10; // @[OneHot.scala:83:30] wire _issue_entry_T_226 = issue_sel_1 & entries_ld_1_bits_deps_ex_10; // @[OneHot.scala:83:30] wire _issue_entry_T_227 = issue_sel_2 & entries_ld_2_bits_deps_ex_10; // @[OneHot.scala:83:30] wire _issue_entry_T_228 = issue_sel_3 & entries_ld_3_bits_deps_ex_10; // @[OneHot.scala:83:30] wire _issue_entry_T_229 = issue_sel_4 & entries_ld_4_bits_deps_ex_10; // @[OneHot.scala:83:30] wire _issue_entry_T_230 = issue_sel_5 & entries_ld_5_bits_deps_ex_10; // @[OneHot.scala:83:30] wire _issue_entry_T_231 = issue_sel_6 & entries_ld_6_bits_deps_ex_10; // @[OneHot.scala:83:30] wire _issue_entry_T_232 = issue_sel_7 & entries_ld_7_bits_deps_ex_10; // @[OneHot.scala:83:30] wire _issue_entry_T_233 = _issue_entry_T_225 | _issue_entry_T_226; // @[Mux.scala:30:73] wire _issue_entry_T_234 = _issue_entry_T_233 | _issue_entry_T_227; // @[Mux.scala:30:73] wire _issue_entry_T_235 = _issue_entry_T_234 | _issue_entry_T_228; // @[Mux.scala:30:73] wire _issue_entry_T_236 = _issue_entry_T_235 | _issue_entry_T_229; // @[Mux.scala:30:73] wire _issue_entry_T_237 = _issue_entry_T_236 | _issue_entry_T_230; // @[Mux.scala:30:73] wire _issue_entry_T_238 = _issue_entry_T_237 | _issue_entry_T_231; // @[Mux.scala:30:73] wire _issue_entry_T_239 = _issue_entry_T_238 | _issue_entry_T_232; // @[Mux.scala:30:73] assign _issue_entry_WIRE_18 = _issue_entry_T_239; // @[Mux.scala:30:73] assign _issue_entry_WIRE_7_10 = _issue_entry_WIRE_18; // @[Mux.scala:30:73] wire _issue_entry_T_240 = issue_sel_0 & entries_ld_0_bits_deps_ex_11; // @[OneHot.scala:83:30] wire _issue_entry_T_241 = issue_sel_1 & entries_ld_1_bits_deps_ex_11; // @[OneHot.scala:83:30] wire _issue_entry_T_242 = issue_sel_2 & entries_ld_2_bits_deps_ex_11; // @[OneHot.scala:83:30] wire _issue_entry_T_243 = issue_sel_3 & entries_ld_3_bits_deps_ex_11; // @[OneHot.scala:83:30] wire _issue_entry_T_244 = issue_sel_4 & entries_ld_4_bits_deps_ex_11; // @[OneHot.scala:83:30] wire _issue_entry_T_245 = issue_sel_5 & entries_ld_5_bits_deps_ex_11; // @[OneHot.scala:83:30] wire _issue_entry_T_246 = issue_sel_6 & entries_ld_6_bits_deps_ex_11; // @[OneHot.scala:83:30] wire _issue_entry_T_247 = issue_sel_7 & entries_ld_7_bits_deps_ex_11; // @[OneHot.scala:83:30] wire _issue_entry_T_248 = _issue_entry_T_240 | _issue_entry_T_241; // @[Mux.scala:30:73] wire _issue_entry_T_249 = _issue_entry_T_248 | _issue_entry_T_242; // @[Mux.scala:30:73] wire _issue_entry_T_250 = _issue_entry_T_249 | _issue_entry_T_243; // @[Mux.scala:30:73] wire _issue_entry_T_251 = _issue_entry_T_250 | _issue_entry_T_244; // @[Mux.scala:30:73] wire _issue_entry_T_252 = _issue_entry_T_251 | _issue_entry_T_245; // @[Mux.scala:30:73] wire _issue_entry_T_253 = _issue_entry_T_252 | _issue_entry_T_246; // @[Mux.scala:30:73] wire _issue_entry_T_254 = _issue_entry_T_253 | _issue_entry_T_247; // @[Mux.scala:30:73] assign _issue_entry_WIRE_19 = _issue_entry_T_254; // @[Mux.scala:30:73] assign _issue_entry_WIRE_7_11 = _issue_entry_WIRE_19; // @[Mux.scala:30:73] wire _issue_entry_T_255 = issue_sel_0 & entries_ld_0_bits_deps_ex_12; // @[OneHot.scala:83:30] wire _issue_entry_T_256 = issue_sel_1 & entries_ld_1_bits_deps_ex_12; // @[OneHot.scala:83:30] wire _issue_entry_T_257 = issue_sel_2 & entries_ld_2_bits_deps_ex_12; // @[OneHot.scala:83:30] wire _issue_entry_T_258 = issue_sel_3 & entries_ld_3_bits_deps_ex_12; // @[OneHot.scala:83:30] wire _issue_entry_T_259 = issue_sel_4 & entries_ld_4_bits_deps_ex_12; // @[OneHot.scala:83:30] wire _issue_entry_T_260 = issue_sel_5 & entries_ld_5_bits_deps_ex_12; // @[OneHot.scala:83:30] wire _issue_entry_T_261 = issue_sel_6 & entries_ld_6_bits_deps_ex_12; // @[OneHot.scala:83:30] wire _issue_entry_T_262 = issue_sel_7 & entries_ld_7_bits_deps_ex_12; // @[OneHot.scala:83:30] wire _issue_entry_T_263 = _issue_entry_T_255 | _issue_entry_T_256; // @[Mux.scala:30:73] wire _issue_entry_T_264 = _issue_entry_T_263 | _issue_entry_T_257; // @[Mux.scala:30:73] wire _issue_entry_T_265 = _issue_entry_T_264 | _issue_entry_T_258; // @[Mux.scala:30:73] wire _issue_entry_T_266 = _issue_entry_T_265 | _issue_entry_T_259; // @[Mux.scala:30:73] wire _issue_entry_T_267 = _issue_entry_T_266 | _issue_entry_T_260; // @[Mux.scala:30:73] wire _issue_entry_T_268 = _issue_entry_T_267 | _issue_entry_T_261; // @[Mux.scala:30:73] wire _issue_entry_T_269 = _issue_entry_T_268 | _issue_entry_T_262; // @[Mux.scala:30:73] assign _issue_entry_WIRE_20 = _issue_entry_T_269; // @[Mux.scala:30:73] assign _issue_entry_WIRE_7_12 = _issue_entry_WIRE_20; // @[Mux.scala:30:73] wire _issue_entry_T_270 = issue_sel_0 & entries_ld_0_bits_deps_ex_13; // @[OneHot.scala:83:30] wire _issue_entry_T_271 = issue_sel_1 & entries_ld_1_bits_deps_ex_13; // @[OneHot.scala:83:30] wire _issue_entry_T_272 = issue_sel_2 & entries_ld_2_bits_deps_ex_13; // @[OneHot.scala:83:30] wire _issue_entry_T_273 = issue_sel_3 & entries_ld_3_bits_deps_ex_13; // @[OneHot.scala:83:30] wire _issue_entry_T_274 = issue_sel_4 & entries_ld_4_bits_deps_ex_13; // @[OneHot.scala:83:30] wire _issue_entry_T_275 = issue_sel_5 & entries_ld_5_bits_deps_ex_13; // @[OneHot.scala:83:30] wire _issue_entry_T_276 = issue_sel_6 & entries_ld_6_bits_deps_ex_13; // @[OneHot.scala:83:30] wire _issue_entry_T_277 = issue_sel_7 & entries_ld_7_bits_deps_ex_13; // @[OneHot.scala:83:30] wire _issue_entry_T_278 = _issue_entry_T_270 | _issue_entry_T_271; // @[Mux.scala:30:73] wire _issue_entry_T_279 = _issue_entry_T_278 | _issue_entry_T_272; // @[Mux.scala:30:73] wire _issue_entry_T_280 = _issue_entry_T_279 | _issue_entry_T_273; // @[Mux.scala:30:73] wire _issue_entry_T_281 = _issue_entry_T_280 | _issue_entry_T_274; // @[Mux.scala:30:73] wire _issue_entry_T_282 = _issue_entry_T_281 | _issue_entry_T_275; // @[Mux.scala:30:73] wire _issue_entry_T_283 = _issue_entry_T_282 | _issue_entry_T_276; // @[Mux.scala:30:73] wire _issue_entry_T_284 = _issue_entry_T_283 | _issue_entry_T_277; // @[Mux.scala:30:73] assign _issue_entry_WIRE_21 = _issue_entry_T_284; // @[Mux.scala:30:73] assign _issue_entry_WIRE_7_13 = _issue_entry_WIRE_21; // @[Mux.scala:30:73] wire _issue_entry_T_285 = issue_sel_0 & entries_ld_0_bits_deps_ex_14; // @[OneHot.scala:83:30] wire _issue_entry_T_286 = issue_sel_1 & entries_ld_1_bits_deps_ex_14; // @[OneHot.scala:83:30] wire _issue_entry_T_287 = issue_sel_2 & entries_ld_2_bits_deps_ex_14; // @[OneHot.scala:83:30] wire _issue_entry_T_288 = issue_sel_3 & entries_ld_3_bits_deps_ex_14; // @[OneHot.scala:83:30] wire _issue_entry_T_289 = issue_sel_4 & entries_ld_4_bits_deps_ex_14; // @[OneHot.scala:83:30] wire _issue_entry_T_290 = issue_sel_5 & entries_ld_5_bits_deps_ex_14; // @[OneHot.scala:83:30] wire _issue_entry_T_291 = issue_sel_6 & entries_ld_6_bits_deps_ex_14; // @[OneHot.scala:83:30] wire _issue_entry_T_292 = issue_sel_7 & entries_ld_7_bits_deps_ex_14; // @[OneHot.scala:83:30] wire _issue_entry_T_293 = _issue_entry_T_285 | _issue_entry_T_286; // @[Mux.scala:30:73] wire _issue_entry_T_294 = _issue_entry_T_293 | _issue_entry_T_287; // @[Mux.scala:30:73] wire _issue_entry_T_295 = _issue_entry_T_294 | _issue_entry_T_288; // @[Mux.scala:30:73] wire _issue_entry_T_296 = _issue_entry_T_295 | _issue_entry_T_289; // @[Mux.scala:30:73] wire _issue_entry_T_297 = _issue_entry_T_296 | _issue_entry_T_290; // @[Mux.scala:30:73] wire _issue_entry_T_298 = _issue_entry_T_297 | _issue_entry_T_291; // @[Mux.scala:30:73] wire _issue_entry_T_299 = _issue_entry_T_298 | _issue_entry_T_292; // @[Mux.scala:30:73] assign _issue_entry_WIRE_22 = _issue_entry_T_299; // @[Mux.scala:30:73] assign _issue_entry_WIRE_7_14 = _issue_entry_WIRE_22; // @[Mux.scala:30:73] wire _issue_entry_T_300 = issue_sel_0 & entries_ld_0_bits_deps_ex_15; // @[OneHot.scala:83:30] wire _issue_entry_T_301 = issue_sel_1 & entries_ld_1_bits_deps_ex_15; // @[OneHot.scala:83:30] wire _issue_entry_T_302 = issue_sel_2 & entries_ld_2_bits_deps_ex_15; // @[OneHot.scala:83:30] wire _issue_entry_T_303 = issue_sel_3 & entries_ld_3_bits_deps_ex_15; // @[OneHot.scala:83:30] wire _issue_entry_T_304 = issue_sel_4 & entries_ld_4_bits_deps_ex_15; // @[OneHot.scala:83:30] wire _issue_entry_T_305 = issue_sel_5 & entries_ld_5_bits_deps_ex_15; // @[OneHot.scala:83:30] wire _issue_entry_T_306 = issue_sel_6 & entries_ld_6_bits_deps_ex_15; // @[OneHot.scala:83:30] wire _issue_entry_T_307 = issue_sel_7 & entries_ld_7_bits_deps_ex_15; // @[OneHot.scala:83:30] wire _issue_entry_T_308 = _issue_entry_T_300 | _issue_entry_T_301; // @[Mux.scala:30:73] wire _issue_entry_T_309 = _issue_entry_T_308 | _issue_entry_T_302; // @[Mux.scala:30:73] wire _issue_entry_T_310 = _issue_entry_T_309 | _issue_entry_T_303; // @[Mux.scala:30:73] wire _issue_entry_T_311 = _issue_entry_T_310 | _issue_entry_T_304; // @[Mux.scala:30:73] wire _issue_entry_T_312 = _issue_entry_T_311 | _issue_entry_T_305; // @[Mux.scala:30:73] wire _issue_entry_T_313 = _issue_entry_T_312 | _issue_entry_T_306; // @[Mux.scala:30:73] wire _issue_entry_T_314 = _issue_entry_T_313 | _issue_entry_T_307; // @[Mux.scala:30:73] assign _issue_entry_WIRE_23 = _issue_entry_T_314; // @[Mux.scala:30:73] assign _issue_entry_WIRE_7_15 = _issue_entry_WIRE_23; // @[Mux.scala:30:73] wire _issue_entry_WIRE_25; // @[Mux.scala:30:73] assign _issue_entry_WIRE_deps_ld_0 = _issue_entry_WIRE_24_0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_26; // @[Mux.scala:30:73] assign _issue_entry_WIRE_deps_ld_1 = _issue_entry_WIRE_24_1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_27; // @[Mux.scala:30:73] assign _issue_entry_WIRE_deps_ld_2 = _issue_entry_WIRE_24_2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_28; // @[Mux.scala:30:73] assign _issue_entry_WIRE_deps_ld_3 = _issue_entry_WIRE_24_3; // @[Mux.scala:30:73] wire _issue_entry_WIRE_29; // @[Mux.scala:30:73] assign _issue_entry_WIRE_deps_ld_4 = _issue_entry_WIRE_24_4; // @[Mux.scala:30:73] wire _issue_entry_WIRE_30; // @[Mux.scala:30:73] assign _issue_entry_WIRE_deps_ld_5 = _issue_entry_WIRE_24_5; // @[Mux.scala:30:73] wire _issue_entry_WIRE_31; // @[Mux.scala:30:73] assign _issue_entry_WIRE_deps_ld_6 = _issue_entry_WIRE_24_6; // @[Mux.scala:30:73] wire _issue_entry_WIRE_32; // @[Mux.scala:30:73] assign _issue_entry_WIRE_deps_ld_7 = _issue_entry_WIRE_24_7; // @[Mux.scala:30:73] wire _issue_entry_T_315 = issue_sel_0 & entries_ld_0_bits_deps_ld_0; // @[OneHot.scala:83:30] wire _issue_entry_T_316 = issue_sel_1 & entries_ld_1_bits_deps_ld_0; // @[OneHot.scala:83:30] wire _issue_entry_T_317 = issue_sel_2 & entries_ld_2_bits_deps_ld_0; // @[OneHot.scala:83:30] wire _issue_entry_T_318 = issue_sel_3 & entries_ld_3_bits_deps_ld_0; // @[OneHot.scala:83:30] wire _issue_entry_T_319 = issue_sel_4 & entries_ld_4_bits_deps_ld_0; // @[OneHot.scala:83:30] wire _issue_entry_T_320 = issue_sel_5 & entries_ld_5_bits_deps_ld_0; // @[OneHot.scala:83:30] wire _issue_entry_T_321 = issue_sel_6 & entries_ld_6_bits_deps_ld_0; // @[OneHot.scala:83:30] wire _issue_entry_T_322 = issue_sel_7 & entries_ld_7_bits_deps_ld_0; // @[OneHot.scala:83:30] wire _issue_entry_T_323 = _issue_entry_T_315 | _issue_entry_T_316; // @[Mux.scala:30:73] wire _issue_entry_T_324 = _issue_entry_T_323 | _issue_entry_T_317; // @[Mux.scala:30:73] wire _issue_entry_T_325 = _issue_entry_T_324 | _issue_entry_T_318; // @[Mux.scala:30:73] wire _issue_entry_T_326 = _issue_entry_T_325 | _issue_entry_T_319; // @[Mux.scala:30:73] wire _issue_entry_T_327 = _issue_entry_T_326 | _issue_entry_T_320; // @[Mux.scala:30:73] wire _issue_entry_T_328 = _issue_entry_T_327 | _issue_entry_T_321; // @[Mux.scala:30:73] wire _issue_entry_T_329 = _issue_entry_T_328 | _issue_entry_T_322; // @[Mux.scala:30:73] assign _issue_entry_WIRE_25 = _issue_entry_T_329; // @[Mux.scala:30:73] assign _issue_entry_WIRE_24_0 = _issue_entry_WIRE_25; // @[Mux.scala:30:73] wire _issue_entry_T_330 = issue_sel_0 & entries_ld_0_bits_deps_ld_1; // @[OneHot.scala:83:30] wire _issue_entry_T_331 = issue_sel_1 & entries_ld_1_bits_deps_ld_1; // @[OneHot.scala:83:30] wire _issue_entry_T_332 = issue_sel_2 & entries_ld_2_bits_deps_ld_1; // @[OneHot.scala:83:30] wire _issue_entry_T_333 = issue_sel_3 & entries_ld_3_bits_deps_ld_1; // @[OneHot.scala:83:30] wire _issue_entry_T_334 = issue_sel_4 & entries_ld_4_bits_deps_ld_1; // @[OneHot.scala:83:30] wire _issue_entry_T_335 = issue_sel_5 & entries_ld_5_bits_deps_ld_1; // @[OneHot.scala:83:30] wire _issue_entry_T_336 = issue_sel_6 & entries_ld_6_bits_deps_ld_1; // @[OneHot.scala:83:30] wire _issue_entry_T_337 = issue_sel_7 & entries_ld_7_bits_deps_ld_1; // @[OneHot.scala:83:30] wire _issue_entry_T_338 = _issue_entry_T_330 | _issue_entry_T_331; // @[Mux.scala:30:73] wire _issue_entry_T_339 = _issue_entry_T_338 | _issue_entry_T_332; // @[Mux.scala:30:73] wire _issue_entry_T_340 = _issue_entry_T_339 | _issue_entry_T_333; // @[Mux.scala:30:73] wire _issue_entry_T_341 = _issue_entry_T_340 | _issue_entry_T_334; // @[Mux.scala:30:73] wire _issue_entry_T_342 = _issue_entry_T_341 | _issue_entry_T_335; // @[Mux.scala:30:73] wire _issue_entry_T_343 = _issue_entry_T_342 | _issue_entry_T_336; // @[Mux.scala:30:73] wire _issue_entry_T_344 = _issue_entry_T_343 | _issue_entry_T_337; // @[Mux.scala:30:73] assign _issue_entry_WIRE_26 = _issue_entry_T_344; // @[Mux.scala:30:73] assign _issue_entry_WIRE_24_1 = _issue_entry_WIRE_26; // @[Mux.scala:30:73] wire _issue_entry_T_345 = issue_sel_0 & entries_ld_0_bits_deps_ld_2; // @[OneHot.scala:83:30] wire _issue_entry_T_346 = issue_sel_1 & entries_ld_1_bits_deps_ld_2; // @[OneHot.scala:83:30] wire _issue_entry_T_347 = issue_sel_2 & entries_ld_2_bits_deps_ld_2; // @[OneHot.scala:83:30] wire _issue_entry_T_348 = issue_sel_3 & entries_ld_3_bits_deps_ld_2; // @[OneHot.scala:83:30] wire _issue_entry_T_349 = issue_sel_4 & entries_ld_4_bits_deps_ld_2; // @[OneHot.scala:83:30] wire _issue_entry_T_350 = issue_sel_5 & entries_ld_5_bits_deps_ld_2; // @[OneHot.scala:83:30] wire _issue_entry_T_351 = issue_sel_6 & entries_ld_6_bits_deps_ld_2; // @[OneHot.scala:83:30] wire _issue_entry_T_352 = issue_sel_7 & entries_ld_7_bits_deps_ld_2; // @[OneHot.scala:83:30] wire _issue_entry_T_353 = _issue_entry_T_345 | _issue_entry_T_346; // @[Mux.scala:30:73] wire _issue_entry_T_354 = _issue_entry_T_353 | _issue_entry_T_347; // @[Mux.scala:30:73] wire _issue_entry_T_355 = _issue_entry_T_354 | _issue_entry_T_348; // @[Mux.scala:30:73] wire _issue_entry_T_356 = _issue_entry_T_355 | _issue_entry_T_349; // @[Mux.scala:30:73] wire _issue_entry_T_357 = _issue_entry_T_356 | _issue_entry_T_350; // @[Mux.scala:30:73] wire _issue_entry_T_358 = _issue_entry_T_357 | _issue_entry_T_351; // @[Mux.scala:30:73] wire _issue_entry_T_359 = _issue_entry_T_358 | _issue_entry_T_352; // @[Mux.scala:30:73] assign _issue_entry_WIRE_27 = _issue_entry_T_359; // @[Mux.scala:30:73] assign _issue_entry_WIRE_24_2 = _issue_entry_WIRE_27; // @[Mux.scala:30:73] wire _issue_entry_T_360 = issue_sel_0 & entries_ld_0_bits_deps_ld_3; // @[OneHot.scala:83:30] wire _issue_entry_T_361 = issue_sel_1 & entries_ld_1_bits_deps_ld_3; // @[OneHot.scala:83:30] wire _issue_entry_T_362 = issue_sel_2 & entries_ld_2_bits_deps_ld_3; // @[OneHot.scala:83:30] wire _issue_entry_T_363 = issue_sel_3 & entries_ld_3_bits_deps_ld_3; // @[OneHot.scala:83:30] wire _issue_entry_T_364 = issue_sel_4 & entries_ld_4_bits_deps_ld_3; // @[OneHot.scala:83:30] wire _issue_entry_T_365 = issue_sel_5 & entries_ld_5_bits_deps_ld_3; // @[OneHot.scala:83:30] wire _issue_entry_T_366 = issue_sel_6 & entries_ld_6_bits_deps_ld_3; // @[OneHot.scala:83:30] wire _issue_entry_T_367 = issue_sel_7 & entries_ld_7_bits_deps_ld_3; // @[OneHot.scala:83:30] wire _issue_entry_T_368 = _issue_entry_T_360 | _issue_entry_T_361; // @[Mux.scala:30:73] wire _issue_entry_T_369 = _issue_entry_T_368 | _issue_entry_T_362; // @[Mux.scala:30:73] wire _issue_entry_T_370 = _issue_entry_T_369 | _issue_entry_T_363; // @[Mux.scala:30:73] wire _issue_entry_T_371 = _issue_entry_T_370 | _issue_entry_T_364; // @[Mux.scala:30:73] wire _issue_entry_T_372 = _issue_entry_T_371 | _issue_entry_T_365; // @[Mux.scala:30:73] wire _issue_entry_T_373 = _issue_entry_T_372 | _issue_entry_T_366; // @[Mux.scala:30:73] wire _issue_entry_T_374 = _issue_entry_T_373 | _issue_entry_T_367; // @[Mux.scala:30:73] assign _issue_entry_WIRE_28 = _issue_entry_T_374; // @[Mux.scala:30:73] assign _issue_entry_WIRE_24_3 = _issue_entry_WIRE_28; // @[Mux.scala:30:73] wire _issue_entry_T_375 = issue_sel_0 & entries_ld_0_bits_deps_ld_4; // @[OneHot.scala:83:30] wire _issue_entry_T_376 = issue_sel_1 & entries_ld_1_bits_deps_ld_4; // @[OneHot.scala:83:30] wire _issue_entry_T_377 = issue_sel_2 & entries_ld_2_bits_deps_ld_4; // @[OneHot.scala:83:30] wire _issue_entry_T_378 = issue_sel_3 & entries_ld_3_bits_deps_ld_4; // @[OneHot.scala:83:30] wire _issue_entry_T_379 = issue_sel_4 & entries_ld_4_bits_deps_ld_4; // @[OneHot.scala:83:30] wire _issue_entry_T_380 = issue_sel_5 & entries_ld_5_bits_deps_ld_4; // @[OneHot.scala:83:30] wire _issue_entry_T_381 = issue_sel_6 & entries_ld_6_bits_deps_ld_4; // @[OneHot.scala:83:30] wire _issue_entry_T_382 = issue_sel_7 & entries_ld_7_bits_deps_ld_4; // @[OneHot.scala:83:30] wire _issue_entry_T_383 = _issue_entry_T_375 | _issue_entry_T_376; // @[Mux.scala:30:73] wire _issue_entry_T_384 = _issue_entry_T_383 | _issue_entry_T_377; // @[Mux.scala:30:73] wire _issue_entry_T_385 = _issue_entry_T_384 | _issue_entry_T_378; // @[Mux.scala:30:73] wire _issue_entry_T_386 = _issue_entry_T_385 | _issue_entry_T_379; // @[Mux.scala:30:73] wire _issue_entry_T_387 = _issue_entry_T_386 | _issue_entry_T_380; // @[Mux.scala:30:73] wire _issue_entry_T_388 = _issue_entry_T_387 | _issue_entry_T_381; // @[Mux.scala:30:73] wire _issue_entry_T_389 = _issue_entry_T_388 | _issue_entry_T_382; // @[Mux.scala:30:73] assign _issue_entry_WIRE_29 = _issue_entry_T_389; // @[Mux.scala:30:73] assign _issue_entry_WIRE_24_4 = _issue_entry_WIRE_29; // @[Mux.scala:30:73] wire _issue_entry_T_390 = issue_sel_0 & entries_ld_0_bits_deps_ld_5; // @[OneHot.scala:83:30] wire _issue_entry_T_391 = issue_sel_1 & entries_ld_1_bits_deps_ld_5; // @[OneHot.scala:83:30] wire _issue_entry_T_392 = issue_sel_2 & entries_ld_2_bits_deps_ld_5; // @[OneHot.scala:83:30] wire _issue_entry_T_393 = issue_sel_3 & entries_ld_3_bits_deps_ld_5; // @[OneHot.scala:83:30] wire _issue_entry_T_394 = issue_sel_4 & entries_ld_4_bits_deps_ld_5; // @[OneHot.scala:83:30] wire _issue_entry_T_395 = issue_sel_5 & entries_ld_5_bits_deps_ld_5; // @[OneHot.scala:83:30] wire _issue_entry_T_396 = issue_sel_6 & entries_ld_6_bits_deps_ld_5; // @[OneHot.scala:83:30] wire _issue_entry_T_397 = issue_sel_7 & entries_ld_7_bits_deps_ld_5; // @[OneHot.scala:83:30] wire _issue_entry_T_398 = _issue_entry_T_390 | _issue_entry_T_391; // @[Mux.scala:30:73] wire _issue_entry_T_399 = _issue_entry_T_398 | _issue_entry_T_392; // @[Mux.scala:30:73] wire _issue_entry_T_400 = _issue_entry_T_399 | _issue_entry_T_393; // @[Mux.scala:30:73] wire _issue_entry_T_401 = _issue_entry_T_400 | _issue_entry_T_394; // @[Mux.scala:30:73] wire _issue_entry_T_402 = _issue_entry_T_401 | _issue_entry_T_395; // @[Mux.scala:30:73] wire _issue_entry_T_403 = _issue_entry_T_402 | _issue_entry_T_396; // @[Mux.scala:30:73] wire _issue_entry_T_404 = _issue_entry_T_403 | _issue_entry_T_397; // @[Mux.scala:30:73] assign _issue_entry_WIRE_30 = _issue_entry_T_404; // @[Mux.scala:30:73] assign _issue_entry_WIRE_24_5 = _issue_entry_WIRE_30; // @[Mux.scala:30:73] wire _issue_entry_T_405 = issue_sel_0 & entries_ld_0_bits_deps_ld_6; // @[OneHot.scala:83:30] wire _issue_entry_T_406 = issue_sel_1 & entries_ld_1_bits_deps_ld_6; // @[OneHot.scala:83:30] wire _issue_entry_T_407 = issue_sel_2 & entries_ld_2_bits_deps_ld_6; // @[OneHot.scala:83:30] wire _issue_entry_T_408 = issue_sel_3 & entries_ld_3_bits_deps_ld_6; // @[OneHot.scala:83:30] wire _issue_entry_T_409 = issue_sel_4 & entries_ld_4_bits_deps_ld_6; // @[OneHot.scala:83:30] wire _issue_entry_T_410 = issue_sel_5 & entries_ld_5_bits_deps_ld_6; // @[OneHot.scala:83:30] wire _issue_entry_T_411 = issue_sel_6 & entries_ld_6_bits_deps_ld_6; // @[OneHot.scala:83:30] wire _issue_entry_T_412 = issue_sel_7 & entries_ld_7_bits_deps_ld_6; // @[OneHot.scala:83:30] wire _issue_entry_T_413 = _issue_entry_T_405 | _issue_entry_T_406; // @[Mux.scala:30:73] wire _issue_entry_T_414 = _issue_entry_T_413 | _issue_entry_T_407; // @[Mux.scala:30:73] wire _issue_entry_T_415 = _issue_entry_T_414 | _issue_entry_T_408; // @[Mux.scala:30:73] wire _issue_entry_T_416 = _issue_entry_T_415 | _issue_entry_T_409; // @[Mux.scala:30:73] wire _issue_entry_T_417 = _issue_entry_T_416 | _issue_entry_T_410; // @[Mux.scala:30:73] wire _issue_entry_T_418 = _issue_entry_T_417 | _issue_entry_T_411; // @[Mux.scala:30:73] wire _issue_entry_T_419 = _issue_entry_T_418 | _issue_entry_T_412; // @[Mux.scala:30:73] assign _issue_entry_WIRE_31 = _issue_entry_T_419; // @[Mux.scala:30:73] assign _issue_entry_WIRE_24_6 = _issue_entry_WIRE_31; // @[Mux.scala:30:73] wire _issue_entry_T_420 = issue_sel_0 & entries_ld_0_bits_deps_ld_7; // @[OneHot.scala:83:30] wire _issue_entry_T_421 = issue_sel_1 & entries_ld_1_bits_deps_ld_7; // @[OneHot.scala:83:30] wire _issue_entry_T_422 = issue_sel_2 & entries_ld_2_bits_deps_ld_7; // @[OneHot.scala:83:30] wire _issue_entry_T_423 = issue_sel_3 & entries_ld_3_bits_deps_ld_7; // @[OneHot.scala:83:30] wire _issue_entry_T_424 = issue_sel_4 & entries_ld_4_bits_deps_ld_7; // @[OneHot.scala:83:30] wire _issue_entry_T_425 = issue_sel_5 & entries_ld_5_bits_deps_ld_7; // @[OneHot.scala:83:30] wire _issue_entry_T_426 = issue_sel_6 & entries_ld_6_bits_deps_ld_7; // @[OneHot.scala:83:30] wire _issue_entry_T_427 = issue_sel_7 & entries_ld_7_bits_deps_ld_7; // @[OneHot.scala:83:30] wire _issue_entry_T_428 = _issue_entry_T_420 | _issue_entry_T_421; // @[Mux.scala:30:73] wire _issue_entry_T_429 = _issue_entry_T_428 | _issue_entry_T_422; // @[Mux.scala:30:73] wire _issue_entry_T_430 = _issue_entry_T_429 | _issue_entry_T_423; // @[Mux.scala:30:73] wire _issue_entry_T_431 = _issue_entry_T_430 | _issue_entry_T_424; // @[Mux.scala:30:73] wire _issue_entry_T_432 = _issue_entry_T_431 | _issue_entry_T_425; // @[Mux.scala:30:73] wire _issue_entry_T_433 = _issue_entry_T_432 | _issue_entry_T_426; // @[Mux.scala:30:73] wire _issue_entry_T_434 = _issue_entry_T_433 | _issue_entry_T_427; // @[Mux.scala:30:73] assign _issue_entry_WIRE_32 = _issue_entry_T_434; // @[Mux.scala:30:73] assign _issue_entry_WIRE_24_7 = _issue_entry_WIRE_32; // @[Mux.scala:30:73] wire [6:0] _issue_entry_WIRE_39_inst_funct; // @[Mux.scala:30:73] assign _issue_entry_WIRE_cmd_cmd_inst_funct = _issue_entry_WIRE_33_cmd_inst_funct; // @[Mux.scala:30:73] wire [4:0] _issue_entry_WIRE_39_inst_rs2; // @[Mux.scala:30:73] assign _issue_entry_WIRE_cmd_cmd_inst_rs2 = _issue_entry_WIRE_33_cmd_inst_rs2; // @[Mux.scala:30:73] wire [4:0] _issue_entry_WIRE_39_inst_rs1; // @[Mux.scala:30:73] assign _issue_entry_WIRE_cmd_cmd_inst_rs1 = _issue_entry_WIRE_33_cmd_inst_rs1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_39_inst_xd; // @[Mux.scala:30:73] assign _issue_entry_WIRE_cmd_cmd_inst_xd = _issue_entry_WIRE_33_cmd_inst_xd; // @[Mux.scala:30:73] wire _issue_entry_WIRE_39_inst_xs1; // @[Mux.scala:30:73] assign _issue_entry_WIRE_cmd_cmd_inst_xs1 = _issue_entry_WIRE_33_cmd_inst_xs1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_39_inst_xs2; // @[Mux.scala:30:73] assign _issue_entry_WIRE_cmd_cmd_inst_xs2 = _issue_entry_WIRE_33_cmd_inst_xs2; // @[Mux.scala:30:73] wire [4:0] _issue_entry_WIRE_39_inst_rd; // @[Mux.scala:30:73] assign _issue_entry_WIRE_cmd_cmd_inst_rd = _issue_entry_WIRE_33_cmd_inst_rd; // @[Mux.scala:30:73] wire [6:0] _issue_entry_WIRE_39_inst_opcode; // @[Mux.scala:30:73] assign _issue_entry_WIRE_cmd_cmd_inst_opcode = _issue_entry_WIRE_33_cmd_inst_opcode; // @[Mux.scala:30:73] wire [63:0] _issue_entry_WIRE_39_rs1; // @[Mux.scala:30:73] assign _issue_entry_WIRE_cmd_cmd_rs1 = _issue_entry_WIRE_33_cmd_rs1; // @[Mux.scala:30:73] wire [63:0] _issue_entry_WIRE_39_rs2; // @[Mux.scala:30:73] assign _issue_entry_WIRE_cmd_cmd_rs2 = _issue_entry_WIRE_33_cmd_rs2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_39_status_debug; // @[Mux.scala:30:73] assign _issue_entry_WIRE_cmd_cmd_status_debug = _issue_entry_WIRE_33_cmd_status_debug; // @[Mux.scala:30:73] wire _issue_entry_WIRE_39_status_cease; // @[Mux.scala:30:73] assign _issue_entry_WIRE_cmd_cmd_status_cease = _issue_entry_WIRE_33_cmd_status_cease; // @[Mux.scala:30:73] wire _issue_entry_WIRE_39_status_wfi; // @[Mux.scala:30:73] assign _issue_entry_WIRE_cmd_cmd_status_wfi = _issue_entry_WIRE_33_cmd_status_wfi; // @[Mux.scala:30:73] wire [31:0] _issue_entry_WIRE_39_status_isa; // @[Mux.scala:30:73] assign _issue_entry_WIRE_cmd_cmd_status_isa = _issue_entry_WIRE_33_cmd_status_isa; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_39_status_dprv; // @[Mux.scala:30:73] assign _issue_entry_WIRE_cmd_cmd_status_dprv = _issue_entry_WIRE_33_cmd_status_dprv; // @[Mux.scala:30:73] wire _issue_entry_WIRE_39_status_dv; // @[Mux.scala:30:73] assign _issue_entry_WIRE_cmd_cmd_status_dv = _issue_entry_WIRE_33_cmd_status_dv; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_39_status_prv; // @[Mux.scala:30:73] assign _issue_entry_WIRE_cmd_cmd_status_prv = _issue_entry_WIRE_33_cmd_status_prv; // @[Mux.scala:30:73] wire _issue_entry_WIRE_39_status_v; // @[Mux.scala:30:73] assign _issue_entry_WIRE_cmd_cmd_status_v = _issue_entry_WIRE_33_cmd_status_v; // @[Mux.scala:30:73] wire _issue_entry_WIRE_39_status_sd; // @[Mux.scala:30:73] assign _issue_entry_WIRE_cmd_cmd_status_sd = _issue_entry_WIRE_33_cmd_status_sd; // @[Mux.scala:30:73] wire [22:0] _issue_entry_WIRE_39_status_zero2; // @[Mux.scala:30:73] assign _issue_entry_WIRE_cmd_cmd_status_zero2 = _issue_entry_WIRE_33_cmd_status_zero2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_39_status_mpv; // @[Mux.scala:30:73] assign _issue_entry_WIRE_cmd_cmd_status_mpv = _issue_entry_WIRE_33_cmd_status_mpv; // @[Mux.scala:30:73] wire _issue_entry_WIRE_39_status_gva; // @[Mux.scala:30:73] assign _issue_entry_WIRE_cmd_cmd_status_gva = _issue_entry_WIRE_33_cmd_status_gva; // @[Mux.scala:30:73] wire _issue_entry_WIRE_39_status_mbe; // @[Mux.scala:30:73] assign _issue_entry_WIRE_cmd_cmd_status_mbe = _issue_entry_WIRE_33_cmd_status_mbe; // @[Mux.scala:30:73] wire _issue_entry_WIRE_39_status_sbe; // @[Mux.scala:30:73] assign _issue_entry_WIRE_cmd_cmd_status_sbe = _issue_entry_WIRE_33_cmd_status_sbe; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_39_status_sxl; // @[Mux.scala:30:73] assign _issue_entry_WIRE_cmd_cmd_status_sxl = _issue_entry_WIRE_33_cmd_status_sxl; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_39_status_uxl; // @[Mux.scala:30:73] assign _issue_entry_WIRE_cmd_cmd_status_uxl = _issue_entry_WIRE_33_cmd_status_uxl; // @[Mux.scala:30:73] wire _issue_entry_WIRE_39_status_sd_rv32; // @[Mux.scala:30:73] assign _issue_entry_WIRE_cmd_cmd_status_sd_rv32 = _issue_entry_WIRE_33_cmd_status_sd_rv32; // @[Mux.scala:30:73] wire [7:0] _issue_entry_WIRE_39_status_zero1; // @[Mux.scala:30:73] assign _issue_entry_WIRE_cmd_cmd_status_zero1 = _issue_entry_WIRE_33_cmd_status_zero1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_39_status_tsr; // @[Mux.scala:30:73] assign _issue_entry_WIRE_cmd_cmd_status_tsr = _issue_entry_WIRE_33_cmd_status_tsr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_39_status_tw; // @[Mux.scala:30:73] assign _issue_entry_WIRE_cmd_cmd_status_tw = _issue_entry_WIRE_33_cmd_status_tw; // @[Mux.scala:30:73] wire _issue_entry_WIRE_39_status_tvm; // @[Mux.scala:30:73] assign _issue_entry_WIRE_cmd_cmd_status_tvm = _issue_entry_WIRE_33_cmd_status_tvm; // @[Mux.scala:30:73] wire _issue_entry_WIRE_39_status_mxr; // @[Mux.scala:30:73] assign _issue_entry_WIRE_cmd_cmd_status_mxr = _issue_entry_WIRE_33_cmd_status_mxr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_39_status_sum; // @[Mux.scala:30:73] assign _issue_entry_WIRE_cmd_cmd_status_sum = _issue_entry_WIRE_33_cmd_status_sum; // @[Mux.scala:30:73] wire _issue_entry_WIRE_39_status_mprv; // @[Mux.scala:30:73] assign _issue_entry_WIRE_cmd_cmd_status_mprv = _issue_entry_WIRE_33_cmd_status_mprv; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_39_status_xs; // @[Mux.scala:30:73] assign _issue_entry_WIRE_cmd_cmd_status_xs = _issue_entry_WIRE_33_cmd_status_xs; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_39_status_fs; // @[Mux.scala:30:73] assign _issue_entry_WIRE_cmd_cmd_status_fs = _issue_entry_WIRE_33_cmd_status_fs; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_39_status_mpp; // @[Mux.scala:30:73] assign _issue_entry_WIRE_cmd_cmd_status_mpp = _issue_entry_WIRE_33_cmd_status_mpp; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_39_status_vs; // @[Mux.scala:30:73] assign _issue_entry_WIRE_cmd_cmd_status_vs = _issue_entry_WIRE_33_cmd_status_vs; // @[Mux.scala:30:73] wire _issue_entry_WIRE_39_status_spp; // @[Mux.scala:30:73] assign _issue_entry_WIRE_cmd_cmd_status_spp = _issue_entry_WIRE_33_cmd_status_spp; // @[Mux.scala:30:73] wire _issue_entry_WIRE_39_status_mpie; // @[Mux.scala:30:73] assign _issue_entry_WIRE_cmd_cmd_status_mpie = _issue_entry_WIRE_33_cmd_status_mpie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_39_status_ube; // @[Mux.scala:30:73] assign _issue_entry_WIRE_cmd_cmd_status_ube = _issue_entry_WIRE_33_cmd_status_ube; // @[Mux.scala:30:73] wire _issue_entry_WIRE_39_status_spie; // @[Mux.scala:30:73] assign _issue_entry_WIRE_cmd_cmd_status_spie = _issue_entry_WIRE_33_cmd_status_spie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_39_status_upie; // @[Mux.scala:30:73] assign _issue_entry_WIRE_cmd_cmd_status_upie = _issue_entry_WIRE_33_cmd_status_upie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_39_status_mie; // @[Mux.scala:30:73] assign _issue_entry_WIRE_cmd_cmd_status_mie = _issue_entry_WIRE_33_cmd_status_mie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_39_status_hie; // @[Mux.scala:30:73] assign _issue_entry_WIRE_cmd_cmd_status_hie = _issue_entry_WIRE_33_cmd_status_hie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_39_status_sie; // @[Mux.scala:30:73] assign _issue_entry_WIRE_cmd_cmd_status_sie = _issue_entry_WIRE_33_cmd_status_sie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_39_status_uie; // @[Mux.scala:30:73] assign _issue_entry_WIRE_cmd_cmd_status_uie = _issue_entry_WIRE_33_cmd_status_uie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_36_valid; // @[Mux.scala:30:73] assign _issue_entry_WIRE_cmd_rob_id_valid = _issue_entry_WIRE_33_rob_id_valid; // @[Mux.scala:30:73] wire [5:0] _issue_entry_WIRE_36_bits; // @[Mux.scala:30:73] assign _issue_entry_WIRE_cmd_rob_id_bits = _issue_entry_WIRE_33_rob_id_bits; // @[Mux.scala:30:73] wire _issue_entry_WIRE_35; // @[Mux.scala:30:73] assign _issue_entry_WIRE_cmd_from_matmul_fsm = _issue_entry_WIRE_33_from_matmul_fsm; // @[Mux.scala:30:73] wire _issue_entry_WIRE_34; // @[Mux.scala:30:73] assign _issue_entry_WIRE_cmd_from_conv_fsm = _issue_entry_WIRE_33_from_conv_fsm; // @[Mux.scala:30:73] wire _issue_entry_T_435 = issue_sel_0 & entries_ld_0_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_436 = issue_sel_1 & entries_ld_1_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_437 = issue_sel_2 & entries_ld_2_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_438 = issue_sel_3 & entries_ld_3_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_439 = issue_sel_4 & entries_ld_4_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_440 = issue_sel_5 & entries_ld_5_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_441 = issue_sel_6 & entries_ld_6_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_442 = issue_sel_7 & entries_ld_7_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_443 = _issue_entry_T_435 | _issue_entry_T_436; // @[Mux.scala:30:73] wire _issue_entry_T_444 = _issue_entry_T_443 | _issue_entry_T_437; // @[Mux.scala:30:73] wire _issue_entry_T_445 = _issue_entry_T_444 | _issue_entry_T_438; // @[Mux.scala:30:73] wire _issue_entry_T_446 = _issue_entry_T_445 | _issue_entry_T_439; // @[Mux.scala:30:73] wire _issue_entry_T_447 = _issue_entry_T_446 | _issue_entry_T_440; // @[Mux.scala:30:73] wire _issue_entry_T_448 = _issue_entry_T_447 | _issue_entry_T_441; // @[Mux.scala:30:73] wire _issue_entry_T_449 = _issue_entry_T_448 | _issue_entry_T_442; // @[Mux.scala:30:73] assign _issue_entry_WIRE_34 = _issue_entry_T_449; // @[Mux.scala:30:73] assign _issue_entry_WIRE_33_from_conv_fsm = _issue_entry_WIRE_34; // @[Mux.scala:30:73] wire _issue_entry_T_450 = issue_sel_0 & entries_ld_0_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_451 = issue_sel_1 & entries_ld_1_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_452 = issue_sel_2 & entries_ld_2_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_453 = issue_sel_3 & entries_ld_3_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_454 = issue_sel_4 & entries_ld_4_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_455 = issue_sel_5 & entries_ld_5_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_456 = issue_sel_6 & entries_ld_6_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_457 = issue_sel_7 & entries_ld_7_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_458 = _issue_entry_T_450 | _issue_entry_T_451; // @[Mux.scala:30:73] wire _issue_entry_T_459 = _issue_entry_T_458 | _issue_entry_T_452; // @[Mux.scala:30:73] wire _issue_entry_T_460 = _issue_entry_T_459 | _issue_entry_T_453; // @[Mux.scala:30:73] wire _issue_entry_T_461 = _issue_entry_T_460 | _issue_entry_T_454; // @[Mux.scala:30:73] wire _issue_entry_T_462 = _issue_entry_T_461 | _issue_entry_T_455; // @[Mux.scala:30:73] wire _issue_entry_T_463 = _issue_entry_T_462 | _issue_entry_T_456; // @[Mux.scala:30:73] wire _issue_entry_T_464 = _issue_entry_T_463 | _issue_entry_T_457; // @[Mux.scala:30:73] assign _issue_entry_WIRE_35 = _issue_entry_T_464; // @[Mux.scala:30:73] assign _issue_entry_WIRE_33_from_matmul_fsm = _issue_entry_WIRE_35; // @[Mux.scala:30:73] wire _issue_entry_WIRE_38; // @[Mux.scala:30:73] assign _issue_entry_WIRE_33_rob_id_valid = _issue_entry_WIRE_36_valid; // @[Mux.scala:30:73] wire [5:0] _issue_entry_WIRE_37; // @[Mux.scala:30:73] assign _issue_entry_WIRE_33_rob_id_bits = _issue_entry_WIRE_36_bits; // @[Mux.scala:30:73] wire [5:0] _issue_entry_T_465 = issue_sel_0 ? entries_ld_0_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30] wire [5:0] _issue_entry_T_466 = issue_sel_1 ? entries_ld_1_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30] wire [5:0] _issue_entry_T_467 = issue_sel_2 ? entries_ld_2_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30] wire [5:0] _issue_entry_T_468 = issue_sel_3 ? entries_ld_3_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30] wire [5:0] _issue_entry_T_469 = issue_sel_4 ? entries_ld_4_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30] wire [5:0] _issue_entry_T_470 = issue_sel_5 ? entries_ld_5_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30] wire [5:0] _issue_entry_T_471 = issue_sel_6 ? entries_ld_6_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30] wire [5:0] _issue_entry_T_472 = issue_sel_7 ? entries_ld_7_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30] wire [5:0] _issue_entry_T_473 = _issue_entry_T_465 | _issue_entry_T_466; // @[Mux.scala:30:73] wire [5:0] _issue_entry_T_474 = _issue_entry_T_473 | _issue_entry_T_467; // @[Mux.scala:30:73] wire [5:0] _issue_entry_T_475 = _issue_entry_T_474 | _issue_entry_T_468; // @[Mux.scala:30:73] wire [5:0] _issue_entry_T_476 = _issue_entry_T_475 | _issue_entry_T_469; // @[Mux.scala:30:73] wire [5:0] _issue_entry_T_477 = _issue_entry_T_476 | _issue_entry_T_470; // @[Mux.scala:30:73] wire [5:0] _issue_entry_T_478 = _issue_entry_T_477 | _issue_entry_T_471; // @[Mux.scala:30:73] wire [5:0] _issue_entry_T_479 = _issue_entry_T_478 | _issue_entry_T_472; // @[Mux.scala:30:73] assign _issue_entry_WIRE_37 = _issue_entry_T_479; // @[Mux.scala:30:73] assign _issue_entry_WIRE_36_bits = _issue_entry_WIRE_37; // @[Mux.scala:30:73] wire _issue_entry_T_480 = issue_sel_0 & entries_ld_0_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_481 = issue_sel_1 & entries_ld_1_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_482 = issue_sel_2 & entries_ld_2_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_483 = issue_sel_3 & entries_ld_3_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_484 = issue_sel_4 & entries_ld_4_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_485 = issue_sel_5 & entries_ld_5_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_486 = issue_sel_6 & entries_ld_6_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_487 = issue_sel_7 & entries_ld_7_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_488 = _issue_entry_T_480 | _issue_entry_T_481; // @[Mux.scala:30:73] wire _issue_entry_T_489 = _issue_entry_T_488 | _issue_entry_T_482; // @[Mux.scala:30:73] wire _issue_entry_T_490 = _issue_entry_T_489 | _issue_entry_T_483; // @[Mux.scala:30:73] wire _issue_entry_T_491 = _issue_entry_T_490 | _issue_entry_T_484; // @[Mux.scala:30:73] wire _issue_entry_T_492 = _issue_entry_T_491 | _issue_entry_T_485; // @[Mux.scala:30:73] wire _issue_entry_T_493 = _issue_entry_T_492 | _issue_entry_T_486; // @[Mux.scala:30:73] wire _issue_entry_T_494 = _issue_entry_T_493 | _issue_entry_T_487; // @[Mux.scala:30:73] assign _issue_entry_WIRE_38 = _issue_entry_T_494; // @[Mux.scala:30:73] assign _issue_entry_WIRE_36_valid = _issue_entry_WIRE_38; // @[Mux.scala:30:73] wire [6:0] _issue_entry_WIRE_80_funct; // @[Mux.scala:30:73] assign _issue_entry_WIRE_33_cmd_inst_funct = _issue_entry_WIRE_39_inst_funct; // @[Mux.scala:30:73] wire [4:0] _issue_entry_WIRE_80_rs2; // @[Mux.scala:30:73] assign _issue_entry_WIRE_33_cmd_inst_rs2 = _issue_entry_WIRE_39_inst_rs2; // @[Mux.scala:30:73] wire [4:0] _issue_entry_WIRE_80_rs1; // @[Mux.scala:30:73] assign _issue_entry_WIRE_33_cmd_inst_rs1 = _issue_entry_WIRE_39_inst_rs1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_80_xd; // @[Mux.scala:30:73] assign _issue_entry_WIRE_33_cmd_inst_xd = _issue_entry_WIRE_39_inst_xd; // @[Mux.scala:30:73] wire _issue_entry_WIRE_80_xs1; // @[Mux.scala:30:73] assign _issue_entry_WIRE_33_cmd_inst_xs1 = _issue_entry_WIRE_39_inst_xs1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_80_xs2; // @[Mux.scala:30:73] assign _issue_entry_WIRE_33_cmd_inst_xs2 = _issue_entry_WIRE_39_inst_xs2; // @[Mux.scala:30:73] wire [4:0] _issue_entry_WIRE_80_rd; // @[Mux.scala:30:73] assign _issue_entry_WIRE_33_cmd_inst_rd = _issue_entry_WIRE_39_inst_rd; // @[Mux.scala:30:73] wire [6:0] _issue_entry_WIRE_80_opcode; // @[Mux.scala:30:73] assign _issue_entry_WIRE_33_cmd_inst_opcode = _issue_entry_WIRE_39_inst_opcode; // @[Mux.scala:30:73] wire [63:0] _issue_entry_WIRE_79; // @[Mux.scala:30:73] assign _issue_entry_WIRE_33_cmd_rs1 = _issue_entry_WIRE_39_rs1; // @[Mux.scala:30:73] wire [63:0] _issue_entry_WIRE_78; // @[Mux.scala:30:73] assign _issue_entry_WIRE_33_cmd_rs2 = _issue_entry_WIRE_39_rs2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_40_debug; // @[Mux.scala:30:73] assign _issue_entry_WIRE_33_cmd_status_debug = _issue_entry_WIRE_39_status_debug; // @[Mux.scala:30:73] wire _issue_entry_WIRE_40_cease; // @[Mux.scala:30:73] assign _issue_entry_WIRE_33_cmd_status_cease = _issue_entry_WIRE_39_status_cease; // @[Mux.scala:30:73] wire _issue_entry_WIRE_40_wfi; // @[Mux.scala:30:73] assign _issue_entry_WIRE_33_cmd_status_wfi = _issue_entry_WIRE_39_status_wfi; // @[Mux.scala:30:73] wire [31:0] _issue_entry_WIRE_40_isa; // @[Mux.scala:30:73] assign _issue_entry_WIRE_33_cmd_status_isa = _issue_entry_WIRE_39_status_isa; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_40_dprv; // @[Mux.scala:30:73] assign _issue_entry_WIRE_33_cmd_status_dprv = _issue_entry_WIRE_39_status_dprv; // @[Mux.scala:30:73] wire _issue_entry_WIRE_40_dv; // @[Mux.scala:30:73] assign _issue_entry_WIRE_33_cmd_status_dv = _issue_entry_WIRE_39_status_dv; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_40_prv; // @[Mux.scala:30:73] assign _issue_entry_WIRE_33_cmd_status_prv = _issue_entry_WIRE_39_status_prv; // @[Mux.scala:30:73] wire _issue_entry_WIRE_40_v; // @[Mux.scala:30:73] assign _issue_entry_WIRE_33_cmd_status_v = _issue_entry_WIRE_39_status_v; // @[Mux.scala:30:73] wire _issue_entry_WIRE_40_sd; // @[Mux.scala:30:73] assign _issue_entry_WIRE_33_cmd_status_sd = _issue_entry_WIRE_39_status_sd; // @[Mux.scala:30:73] wire [22:0] _issue_entry_WIRE_40_zero2; // @[Mux.scala:30:73] assign _issue_entry_WIRE_33_cmd_status_zero2 = _issue_entry_WIRE_39_status_zero2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_40_mpv; // @[Mux.scala:30:73] assign _issue_entry_WIRE_33_cmd_status_mpv = _issue_entry_WIRE_39_status_mpv; // @[Mux.scala:30:73] wire _issue_entry_WIRE_40_gva; // @[Mux.scala:30:73] assign _issue_entry_WIRE_33_cmd_status_gva = _issue_entry_WIRE_39_status_gva; // @[Mux.scala:30:73] wire _issue_entry_WIRE_40_mbe; // @[Mux.scala:30:73] assign _issue_entry_WIRE_33_cmd_status_mbe = _issue_entry_WIRE_39_status_mbe; // @[Mux.scala:30:73] wire _issue_entry_WIRE_40_sbe; // @[Mux.scala:30:73] assign _issue_entry_WIRE_33_cmd_status_sbe = _issue_entry_WIRE_39_status_sbe; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_40_sxl; // @[Mux.scala:30:73] assign _issue_entry_WIRE_33_cmd_status_sxl = _issue_entry_WIRE_39_status_sxl; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_40_uxl; // @[Mux.scala:30:73] assign _issue_entry_WIRE_33_cmd_status_uxl = _issue_entry_WIRE_39_status_uxl; // @[Mux.scala:30:73] wire _issue_entry_WIRE_40_sd_rv32; // @[Mux.scala:30:73] assign _issue_entry_WIRE_33_cmd_status_sd_rv32 = _issue_entry_WIRE_39_status_sd_rv32; // @[Mux.scala:30:73] wire [7:0] _issue_entry_WIRE_40_zero1; // @[Mux.scala:30:73] assign _issue_entry_WIRE_33_cmd_status_zero1 = _issue_entry_WIRE_39_status_zero1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_40_tsr; // @[Mux.scala:30:73] assign _issue_entry_WIRE_33_cmd_status_tsr = _issue_entry_WIRE_39_status_tsr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_40_tw; // @[Mux.scala:30:73] assign _issue_entry_WIRE_33_cmd_status_tw = _issue_entry_WIRE_39_status_tw; // @[Mux.scala:30:73] wire _issue_entry_WIRE_40_tvm; // @[Mux.scala:30:73] assign _issue_entry_WIRE_33_cmd_status_tvm = _issue_entry_WIRE_39_status_tvm; // @[Mux.scala:30:73] wire _issue_entry_WIRE_40_mxr; // @[Mux.scala:30:73] assign _issue_entry_WIRE_33_cmd_status_mxr = _issue_entry_WIRE_39_status_mxr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_40_sum; // @[Mux.scala:30:73] assign _issue_entry_WIRE_33_cmd_status_sum = _issue_entry_WIRE_39_status_sum; // @[Mux.scala:30:73] wire _issue_entry_WIRE_40_mprv; // @[Mux.scala:30:73] assign _issue_entry_WIRE_33_cmd_status_mprv = _issue_entry_WIRE_39_status_mprv; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_40_xs; // @[Mux.scala:30:73] assign _issue_entry_WIRE_33_cmd_status_xs = _issue_entry_WIRE_39_status_xs; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_40_fs; // @[Mux.scala:30:73] assign _issue_entry_WIRE_33_cmd_status_fs = _issue_entry_WIRE_39_status_fs; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_40_mpp; // @[Mux.scala:30:73] assign _issue_entry_WIRE_33_cmd_status_mpp = _issue_entry_WIRE_39_status_mpp; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_40_vs; // @[Mux.scala:30:73] assign _issue_entry_WIRE_33_cmd_status_vs = _issue_entry_WIRE_39_status_vs; // @[Mux.scala:30:73] wire _issue_entry_WIRE_40_spp; // @[Mux.scala:30:73] assign _issue_entry_WIRE_33_cmd_status_spp = _issue_entry_WIRE_39_status_spp; // @[Mux.scala:30:73] wire _issue_entry_WIRE_40_mpie; // @[Mux.scala:30:73] assign _issue_entry_WIRE_33_cmd_status_mpie = _issue_entry_WIRE_39_status_mpie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_40_ube; // @[Mux.scala:30:73] assign _issue_entry_WIRE_33_cmd_status_ube = _issue_entry_WIRE_39_status_ube; // @[Mux.scala:30:73] wire _issue_entry_WIRE_40_spie; // @[Mux.scala:30:73] assign _issue_entry_WIRE_33_cmd_status_spie = _issue_entry_WIRE_39_status_spie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_40_upie; // @[Mux.scala:30:73] assign _issue_entry_WIRE_33_cmd_status_upie = _issue_entry_WIRE_39_status_upie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_40_mie; // @[Mux.scala:30:73] assign _issue_entry_WIRE_33_cmd_status_mie = _issue_entry_WIRE_39_status_mie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_40_hie; // @[Mux.scala:30:73] assign _issue_entry_WIRE_33_cmd_status_hie = _issue_entry_WIRE_39_status_hie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_40_sie; // @[Mux.scala:30:73] assign _issue_entry_WIRE_33_cmd_status_sie = _issue_entry_WIRE_39_status_sie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_40_uie; // @[Mux.scala:30:73] assign _issue_entry_WIRE_33_cmd_status_uie = _issue_entry_WIRE_39_status_uie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_77; // @[Mux.scala:30:73] assign _issue_entry_WIRE_39_status_debug = _issue_entry_WIRE_40_debug; // @[Mux.scala:30:73] wire _issue_entry_WIRE_76; // @[Mux.scala:30:73] assign _issue_entry_WIRE_39_status_cease = _issue_entry_WIRE_40_cease; // @[Mux.scala:30:73] wire _issue_entry_WIRE_75; // @[Mux.scala:30:73] assign _issue_entry_WIRE_39_status_wfi = _issue_entry_WIRE_40_wfi; // @[Mux.scala:30:73] wire [31:0] _issue_entry_WIRE_74; // @[Mux.scala:30:73] assign _issue_entry_WIRE_39_status_isa = _issue_entry_WIRE_40_isa; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_73; // @[Mux.scala:30:73] assign _issue_entry_WIRE_39_status_dprv = _issue_entry_WIRE_40_dprv; // @[Mux.scala:30:73] wire _issue_entry_WIRE_72; // @[Mux.scala:30:73] assign _issue_entry_WIRE_39_status_dv = _issue_entry_WIRE_40_dv; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_71; // @[Mux.scala:30:73] assign _issue_entry_WIRE_39_status_prv = _issue_entry_WIRE_40_prv; // @[Mux.scala:30:73] wire _issue_entry_WIRE_70; // @[Mux.scala:30:73] assign _issue_entry_WIRE_39_status_v = _issue_entry_WIRE_40_v; // @[Mux.scala:30:73] wire _issue_entry_WIRE_69; // @[Mux.scala:30:73] assign _issue_entry_WIRE_39_status_sd = _issue_entry_WIRE_40_sd; // @[Mux.scala:30:73] wire [22:0] _issue_entry_WIRE_68; // @[Mux.scala:30:73] assign _issue_entry_WIRE_39_status_zero2 = _issue_entry_WIRE_40_zero2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_67; // @[Mux.scala:30:73] assign _issue_entry_WIRE_39_status_mpv = _issue_entry_WIRE_40_mpv; // @[Mux.scala:30:73] wire _issue_entry_WIRE_66; // @[Mux.scala:30:73] assign _issue_entry_WIRE_39_status_gva = _issue_entry_WIRE_40_gva; // @[Mux.scala:30:73] wire _issue_entry_WIRE_65; // @[Mux.scala:30:73] assign _issue_entry_WIRE_39_status_mbe = _issue_entry_WIRE_40_mbe; // @[Mux.scala:30:73] wire _issue_entry_WIRE_64; // @[Mux.scala:30:73] assign _issue_entry_WIRE_39_status_sbe = _issue_entry_WIRE_40_sbe; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_63; // @[Mux.scala:30:73] assign _issue_entry_WIRE_39_status_sxl = _issue_entry_WIRE_40_sxl; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_62; // @[Mux.scala:30:73] assign _issue_entry_WIRE_39_status_uxl = _issue_entry_WIRE_40_uxl; // @[Mux.scala:30:73] wire _issue_entry_WIRE_61; // @[Mux.scala:30:73] assign _issue_entry_WIRE_39_status_sd_rv32 = _issue_entry_WIRE_40_sd_rv32; // @[Mux.scala:30:73] wire [7:0] _issue_entry_WIRE_60; // @[Mux.scala:30:73] assign _issue_entry_WIRE_39_status_zero1 = _issue_entry_WIRE_40_zero1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_59; // @[Mux.scala:30:73] assign _issue_entry_WIRE_39_status_tsr = _issue_entry_WIRE_40_tsr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_58; // @[Mux.scala:30:73] assign _issue_entry_WIRE_39_status_tw = _issue_entry_WIRE_40_tw; // @[Mux.scala:30:73] wire _issue_entry_WIRE_57; // @[Mux.scala:30:73] assign _issue_entry_WIRE_39_status_tvm = _issue_entry_WIRE_40_tvm; // @[Mux.scala:30:73] wire _issue_entry_WIRE_56; // @[Mux.scala:30:73] assign _issue_entry_WIRE_39_status_mxr = _issue_entry_WIRE_40_mxr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_55; // @[Mux.scala:30:73] assign _issue_entry_WIRE_39_status_sum = _issue_entry_WIRE_40_sum; // @[Mux.scala:30:73] wire _issue_entry_WIRE_54; // @[Mux.scala:30:73] assign _issue_entry_WIRE_39_status_mprv = _issue_entry_WIRE_40_mprv; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_53; // @[Mux.scala:30:73] assign _issue_entry_WIRE_39_status_xs = _issue_entry_WIRE_40_xs; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_52; // @[Mux.scala:30:73] assign _issue_entry_WIRE_39_status_fs = _issue_entry_WIRE_40_fs; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_51; // @[Mux.scala:30:73] assign _issue_entry_WIRE_39_status_mpp = _issue_entry_WIRE_40_mpp; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_50; // @[Mux.scala:30:73] assign _issue_entry_WIRE_39_status_vs = _issue_entry_WIRE_40_vs; // @[Mux.scala:30:73] wire _issue_entry_WIRE_49; // @[Mux.scala:30:73] assign _issue_entry_WIRE_39_status_spp = _issue_entry_WIRE_40_spp; // @[Mux.scala:30:73] wire _issue_entry_WIRE_48; // @[Mux.scala:30:73] assign _issue_entry_WIRE_39_status_mpie = _issue_entry_WIRE_40_mpie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_47; // @[Mux.scala:30:73] assign _issue_entry_WIRE_39_status_ube = _issue_entry_WIRE_40_ube; // @[Mux.scala:30:73] wire _issue_entry_WIRE_46; // @[Mux.scala:30:73] assign _issue_entry_WIRE_39_status_spie = _issue_entry_WIRE_40_spie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_45; // @[Mux.scala:30:73] assign _issue_entry_WIRE_39_status_upie = _issue_entry_WIRE_40_upie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_44; // @[Mux.scala:30:73] assign _issue_entry_WIRE_39_status_mie = _issue_entry_WIRE_40_mie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_43; // @[Mux.scala:30:73] assign _issue_entry_WIRE_39_status_hie = _issue_entry_WIRE_40_hie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_42; // @[Mux.scala:30:73] assign _issue_entry_WIRE_39_status_sie = _issue_entry_WIRE_40_sie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_41; // @[Mux.scala:30:73] assign _issue_entry_WIRE_39_status_uie = _issue_entry_WIRE_40_uie; // @[Mux.scala:30:73] wire _issue_entry_T_495 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30] wire _issue_entry_T_496 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30] wire _issue_entry_T_497 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30] wire _issue_entry_T_498 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30] wire _issue_entry_T_499 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30] wire _issue_entry_T_500 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30] wire _issue_entry_T_501 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30] wire _issue_entry_T_502 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30] wire _issue_entry_T_503 = _issue_entry_T_495 | _issue_entry_T_496; // @[Mux.scala:30:73] wire _issue_entry_T_504 = _issue_entry_T_503 | _issue_entry_T_497; // @[Mux.scala:30:73] wire _issue_entry_T_505 = _issue_entry_T_504 | _issue_entry_T_498; // @[Mux.scala:30:73] wire _issue_entry_T_506 = _issue_entry_T_505 | _issue_entry_T_499; // @[Mux.scala:30:73] wire _issue_entry_T_507 = _issue_entry_T_506 | _issue_entry_T_500; // @[Mux.scala:30:73] wire _issue_entry_T_508 = _issue_entry_T_507 | _issue_entry_T_501; // @[Mux.scala:30:73] wire _issue_entry_T_509 = _issue_entry_T_508 | _issue_entry_T_502; // @[Mux.scala:30:73] assign _issue_entry_WIRE_41 = _issue_entry_T_509; // @[Mux.scala:30:73] assign _issue_entry_WIRE_40_uie = _issue_entry_WIRE_41; // @[Mux.scala:30:73] wire _issue_entry_T_510 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30] wire _issue_entry_T_511 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30] wire _issue_entry_T_512 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30] wire _issue_entry_T_513 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30] wire _issue_entry_T_514 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30] wire _issue_entry_T_515 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30] wire _issue_entry_T_516 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30] wire _issue_entry_T_517 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30] wire _issue_entry_T_518 = _issue_entry_T_510 | _issue_entry_T_511; // @[Mux.scala:30:73] wire _issue_entry_T_519 = _issue_entry_T_518 | _issue_entry_T_512; // @[Mux.scala:30:73] wire _issue_entry_T_520 = _issue_entry_T_519 | _issue_entry_T_513; // @[Mux.scala:30:73] wire _issue_entry_T_521 = _issue_entry_T_520 | _issue_entry_T_514; // @[Mux.scala:30:73] wire _issue_entry_T_522 = _issue_entry_T_521 | _issue_entry_T_515; // @[Mux.scala:30:73] wire _issue_entry_T_523 = _issue_entry_T_522 | _issue_entry_T_516; // @[Mux.scala:30:73] wire _issue_entry_T_524 = _issue_entry_T_523 | _issue_entry_T_517; // @[Mux.scala:30:73] assign _issue_entry_WIRE_42 = _issue_entry_T_524; // @[Mux.scala:30:73] assign _issue_entry_WIRE_40_sie = _issue_entry_WIRE_42; // @[Mux.scala:30:73] wire _issue_entry_T_525 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30] wire _issue_entry_T_526 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30] wire _issue_entry_T_527 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30] wire _issue_entry_T_528 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30] wire _issue_entry_T_529 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30] wire _issue_entry_T_530 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30] wire _issue_entry_T_531 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30] wire _issue_entry_T_532 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30] wire _issue_entry_T_533 = _issue_entry_T_525 | _issue_entry_T_526; // @[Mux.scala:30:73] wire _issue_entry_T_534 = _issue_entry_T_533 | _issue_entry_T_527; // @[Mux.scala:30:73] wire _issue_entry_T_535 = _issue_entry_T_534 | _issue_entry_T_528; // @[Mux.scala:30:73] wire _issue_entry_T_536 = _issue_entry_T_535 | _issue_entry_T_529; // @[Mux.scala:30:73] wire _issue_entry_T_537 = _issue_entry_T_536 | _issue_entry_T_530; // @[Mux.scala:30:73] wire _issue_entry_T_538 = _issue_entry_T_537 | _issue_entry_T_531; // @[Mux.scala:30:73] wire _issue_entry_T_539 = _issue_entry_T_538 | _issue_entry_T_532; // @[Mux.scala:30:73] assign _issue_entry_WIRE_43 = _issue_entry_T_539; // @[Mux.scala:30:73] assign _issue_entry_WIRE_40_hie = _issue_entry_WIRE_43; // @[Mux.scala:30:73] wire _issue_entry_T_540 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30] wire _issue_entry_T_541 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30] wire _issue_entry_T_542 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30] wire _issue_entry_T_543 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30] wire _issue_entry_T_544 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30] wire _issue_entry_T_545 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30] wire _issue_entry_T_546 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30] wire _issue_entry_T_547 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30] wire _issue_entry_T_548 = _issue_entry_T_540 | _issue_entry_T_541; // @[Mux.scala:30:73] wire _issue_entry_T_549 = _issue_entry_T_548 | _issue_entry_T_542; // @[Mux.scala:30:73] wire _issue_entry_T_550 = _issue_entry_T_549 | _issue_entry_T_543; // @[Mux.scala:30:73] wire _issue_entry_T_551 = _issue_entry_T_550 | _issue_entry_T_544; // @[Mux.scala:30:73] wire _issue_entry_T_552 = _issue_entry_T_551 | _issue_entry_T_545; // @[Mux.scala:30:73] wire _issue_entry_T_553 = _issue_entry_T_552 | _issue_entry_T_546; // @[Mux.scala:30:73] wire _issue_entry_T_554 = _issue_entry_T_553 | _issue_entry_T_547; // @[Mux.scala:30:73] assign _issue_entry_WIRE_44 = _issue_entry_T_554; // @[Mux.scala:30:73] assign _issue_entry_WIRE_40_mie = _issue_entry_WIRE_44; // @[Mux.scala:30:73] wire _issue_entry_T_555 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30] wire _issue_entry_T_556 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30] wire _issue_entry_T_557 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30] wire _issue_entry_T_558 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30] wire _issue_entry_T_559 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30] wire _issue_entry_T_560 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30] wire _issue_entry_T_561 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30] wire _issue_entry_T_562 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30] wire _issue_entry_T_563 = _issue_entry_T_555 | _issue_entry_T_556; // @[Mux.scala:30:73] wire _issue_entry_T_564 = _issue_entry_T_563 | _issue_entry_T_557; // @[Mux.scala:30:73] wire _issue_entry_T_565 = _issue_entry_T_564 | _issue_entry_T_558; // @[Mux.scala:30:73] wire _issue_entry_T_566 = _issue_entry_T_565 | _issue_entry_T_559; // @[Mux.scala:30:73] wire _issue_entry_T_567 = _issue_entry_T_566 | _issue_entry_T_560; // @[Mux.scala:30:73] wire _issue_entry_T_568 = _issue_entry_T_567 | _issue_entry_T_561; // @[Mux.scala:30:73] wire _issue_entry_T_569 = _issue_entry_T_568 | _issue_entry_T_562; // @[Mux.scala:30:73] assign _issue_entry_WIRE_45 = _issue_entry_T_569; // @[Mux.scala:30:73] assign _issue_entry_WIRE_40_upie = _issue_entry_WIRE_45; // @[Mux.scala:30:73] wire _issue_entry_T_570 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30] wire _issue_entry_T_571 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30] wire _issue_entry_T_572 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30] wire _issue_entry_T_573 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30] wire _issue_entry_T_574 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30] wire _issue_entry_T_575 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30] wire _issue_entry_T_576 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30] wire _issue_entry_T_577 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30] wire _issue_entry_T_578 = _issue_entry_T_570 | _issue_entry_T_571; // @[Mux.scala:30:73] wire _issue_entry_T_579 = _issue_entry_T_578 | _issue_entry_T_572; // @[Mux.scala:30:73] wire _issue_entry_T_580 = _issue_entry_T_579 | _issue_entry_T_573; // @[Mux.scala:30:73] wire _issue_entry_T_581 = _issue_entry_T_580 | _issue_entry_T_574; // @[Mux.scala:30:73] wire _issue_entry_T_582 = _issue_entry_T_581 | _issue_entry_T_575; // @[Mux.scala:30:73] wire _issue_entry_T_583 = _issue_entry_T_582 | _issue_entry_T_576; // @[Mux.scala:30:73] wire _issue_entry_T_584 = _issue_entry_T_583 | _issue_entry_T_577; // @[Mux.scala:30:73] assign _issue_entry_WIRE_46 = _issue_entry_T_584; // @[Mux.scala:30:73] assign _issue_entry_WIRE_40_spie = _issue_entry_WIRE_46; // @[Mux.scala:30:73] wire _issue_entry_T_585 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30] wire _issue_entry_T_586 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30] wire _issue_entry_T_587 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30] wire _issue_entry_T_588 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30] wire _issue_entry_T_589 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30] wire _issue_entry_T_590 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30] wire _issue_entry_T_591 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30] wire _issue_entry_T_592 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30] wire _issue_entry_T_593 = _issue_entry_T_585 | _issue_entry_T_586; // @[Mux.scala:30:73] wire _issue_entry_T_594 = _issue_entry_T_593 | _issue_entry_T_587; // @[Mux.scala:30:73] wire _issue_entry_T_595 = _issue_entry_T_594 | _issue_entry_T_588; // @[Mux.scala:30:73] wire _issue_entry_T_596 = _issue_entry_T_595 | _issue_entry_T_589; // @[Mux.scala:30:73] wire _issue_entry_T_597 = _issue_entry_T_596 | _issue_entry_T_590; // @[Mux.scala:30:73] wire _issue_entry_T_598 = _issue_entry_T_597 | _issue_entry_T_591; // @[Mux.scala:30:73] wire _issue_entry_T_599 = _issue_entry_T_598 | _issue_entry_T_592; // @[Mux.scala:30:73] assign _issue_entry_WIRE_47 = _issue_entry_T_599; // @[Mux.scala:30:73] assign _issue_entry_WIRE_40_ube = _issue_entry_WIRE_47; // @[Mux.scala:30:73] wire _issue_entry_T_600 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30] wire _issue_entry_T_601 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30] wire _issue_entry_T_602 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30] wire _issue_entry_T_603 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30] wire _issue_entry_T_604 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30] wire _issue_entry_T_605 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30] wire _issue_entry_T_606 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30] wire _issue_entry_T_607 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30] wire _issue_entry_T_608 = _issue_entry_T_600 | _issue_entry_T_601; // @[Mux.scala:30:73] wire _issue_entry_T_609 = _issue_entry_T_608 | _issue_entry_T_602; // @[Mux.scala:30:73] wire _issue_entry_T_610 = _issue_entry_T_609 | _issue_entry_T_603; // @[Mux.scala:30:73] wire _issue_entry_T_611 = _issue_entry_T_610 | _issue_entry_T_604; // @[Mux.scala:30:73] wire _issue_entry_T_612 = _issue_entry_T_611 | _issue_entry_T_605; // @[Mux.scala:30:73] wire _issue_entry_T_613 = _issue_entry_T_612 | _issue_entry_T_606; // @[Mux.scala:30:73] wire _issue_entry_T_614 = _issue_entry_T_613 | _issue_entry_T_607; // @[Mux.scala:30:73] assign _issue_entry_WIRE_48 = _issue_entry_T_614; // @[Mux.scala:30:73] assign _issue_entry_WIRE_40_mpie = _issue_entry_WIRE_48; // @[Mux.scala:30:73] wire _issue_entry_T_615 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30] wire _issue_entry_T_616 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30] wire _issue_entry_T_617 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30] wire _issue_entry_T_618 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30] wire _issue_entry_T_619 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30] wire _issue_entry_T_620 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30] wire _issue_entry_T_621 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30] wire _issue_entry_T_622 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30] wire _issue_entry_T_623 = _issue_entry_T_615 | _issue_entry_T_616; // @[Mux.scala:30:73] wire _issue_entry_T_624 = _issue_entry_T_623 | _issue_entry_T_617; // @[Mux.scala:30:73] wire _issue_entry_T_625 = _issue_entry_T_624 | _issue_entry_T_618; // @[Mux.scala:30:73] wire _issue_entry_T_626 = _issue_entry_T_625 | _issue_entry_T_619; // @[Mux.scala:30:73] wire _issue_entry_T_627 = _issue_entry_T_626 | _issue_entry_T_620; // @[Mux.scala:30:73] wire _issue_entry_T_628 = _issue_entry_T_627 | _issue_entry_T_621; // @[Mux.scala:30:73] wire _issue_entry_T_629 = _issue_entry_T_628 | _issue_entry_T_622; // @[Mux.scala:30:73] assign _issue_entry_WIRE_49 = _issue_entry_T_629; // @[Mux.scala:30:73] assign _issue_entry_WIRE_40_spp = _issue_entry_WIRE_49; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_630 = issue_sel_0 ? entries_ld_0_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_631 = issue_sel_1 ? entries_ld_1_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_632 = issue_sel_2 ? entries_ld_2_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_633 = issue_sel_3 ? entries_ld_3_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_634 = issue_sel_4 ? entries_ld_4_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_635 = issue_sel_5 ? entries_ld_5_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_636 = issue_sel_6 ? entries_ld_6_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_637 = issue_sel_7 ? entries_ld_7_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_638 = _issue_entry_T_630 | _issue_entry_T_631; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_639 = _issue_entry_T_638 | _issue_entry_T_632; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_640 = _issue_entry_T_639 | _issue_entry_T_633; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_641 = _issue_entry_T_640 | _issue_entry_T_634; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_642 = _issue_entry_T_641 | _issue_entry_T_635; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_643 = _issue_entry_T_642 | _issue_entry_T_636; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_644 = _issue_entry_T_643 | _issue_entry_T_637; // @[Mux.scala:30:73] assign _issue_entry_WIRE_50 = _issue_entry_T_644; // @[Mux.scala:30:73] assign _issue_entry_WIRE_40_vs = _issue_entry_WIRE_50; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_645 = issue_sel_0 ? entries_ld_0_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_646 = issue_sel_1 ? entries_ld_1_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_647 = issue_sel_2 ? entries_ld_2_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_648 = issue_sel_3 ? entries_ld_3_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_649 = issue_sel_4 ? entries_ld_4_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_650 = issue_sel_5 ? entries_ld_5_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_651 = issue_sel_6 ? entries_ld_6_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_652 = issue_sel_7 ? entries_ld_7_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_653 = _issue_entry_T_645 | _issue_entry_T_646; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_654 = _issue_entry_T_653 | _issue_entry_T_647; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_655 = _issue_entry_T_654 | _issue_entry_T_648; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_656 = _issue_entry_T_655 | _issue_entry_T_649; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_657 = _issue_entry_T_656 | _issue_entry_T_650; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_658 = _issue_entry_T_657 | _issue_entry_T_651; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_659 = _issue_entry_T_658 | _issue_entry_T_652; // @[Mux.scala:30:73] assign _issue_entry_WIRE_51 = _issue_entry_T_659; // @[Mux.scala:30:73] assign _issue_entry_WIRE_40_mpp = _issue_entry_WIRE_51; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_660 = issue_sel_0 ? entries_ld_0_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_661 = issue_sel_1 ? entries_ld_1_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_662 = issue_sel_2 ? entries_ld_2_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_663 = issue_sel_3 ? entries_ld_3_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_664 = issue_sel_4 ? entries_ld_4_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_665 = issue_sel_5 ? entries_ld_5_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_666 = issue_sel_6 ? entries_ld_6_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_667 = issue_sel_7 ? entries_ld_7_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_668 = _issue_entry_T_660 | _issue_entry_T_661; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_669 = _issue_entry_T_668 | _issue_entry_T_662; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_670 = _issue_entry_T_669 | _issue_entry_T_663; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_671 = _issue_entry_T_670 | _issue_entry_T_664; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_672 = _issue_entry_T_671 | _issue_entry_T_665; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_673 = _issue_entry_T_672 | _issue_entry_T_666; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_674 = _issue_entry_T_673 | _issue_entry_T_667; // @[Mux.scala:30:73] assign _issue_entry_WIRE_52 = _issue_entry_T_674; // @[Mux.scala:30:73] assign _issue_entry_WIRE_40_fs = _issue_entry_WIRE_52; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_675 = issue_sel_0 ? entries_ld_0_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_676 = issue_sel_1 ? entries_ld_1_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_677 = issue_sel_2 ? entries_ld_2_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_678 = issue_sel_3 ? entries_ld_3_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_679 = issue_sel_4 ? entries_ld_4_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_680 = issue_sel_5 ? entries_ld_5_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_681 = issue_sel_6 ? entries_ld_6_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_682 = issue_sel_7 ? entries_ld_7_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_683 = _issue_entry_T_675 | _issue_entry_T_676; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_684 = _issue_entry_T_683 | _issue_entry_T_677; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_685 = _issue_entry_T_684 | _issue_entry_T_678; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_686 = _issue_entry_T_685 | _issue_entry_T_679; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_687 = _issue_entry_T_686 | _issue_entry_T_680; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_688 = _issue_entry_T_687 | _issue_entry_T_681; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_689 = _issue_entry_T_688 | _issue_entry_T_682; // @[Mux.scala:30:73] assign _issue_entry_WIRE_53 = _issue_entry_T_689; // @[Mux.scala:30:73] assign _issue_entry_WIRE_40_xs = _issue_entry_WIRE_53; // @[Mux.scala:30:73] wire _issue_entry_T_690 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30] wire _issue_entry_T_691 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30] wire _issue_entry_T_692 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30] wire _issue_entry_T_693 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30] wire _issue_entry_T_694 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30] wire _issue_entry_T_695 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30] wire _issue_entry_T_696 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30] wire _issue_entry_T_697 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30] wire _issue_entry_T_698 = _issue_entry_T_690 | _issue_entry_T_691; // @[Mux.scala:30:73] wire _issue_entry_T_699 = _issue_entry_T_698 | _issue_entry_T_692; // @[Mux.scala:30:73] wire _issue_entry_T_700 = _issue_entry_T_699 | _issue_entry_T_693; // @[Mux.scala:30:73] wire _issue_entry_T_701 = _issue_entry_T_700 | _issue_entry_T_694; // @[Mux.scala:30:73] wire _issue_entry_T_702 = _issue_entry_T_701 | _issue_entry_T_695; // @[Mux.scala:30:73] wire _issue_entry_T_703 = _issue_entry_T_702 | _issue_entry_T_696; // @[Mux.scala:30:73] wire _issue_entry_T_704 = _issue_entry_T_703 | _issue_entry_T_697; // @[Mux.scala:30:73] assign _issue_entry_WIRE_54 = _issue_entry_T_704; // @[Mux.scala:30:73] assign _issue_entry_WIRE_40_mprv = _issue_entry_WIRE_54; // @[Mux.scala:30:73] wire _issue_entry_T_705 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30] wire _issue_entry_T_706 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30] wire _issue_entry_T_707 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30] wire _issue_entry_T_708 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30] wire _issue_entry_T_709 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30] wire _issue_entry_T_710 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30] wire _issue_entry_T_711 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30] wire _issue_entry_T_712 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30] wire _issue_entry_T_713 = _issue_entry_T_705 | _issue_entry_T_706; // @[Mux.scala:30:73] wire _issue_entry_T_714 = _issue_entry_T_713 | _issue_entry_T_707; // @[Mux.scala:30:73] wire _issue_entry_T_715 = _issue_entry_T_714 | _issue_entry_T_708; // @[Mux.scala:30:73] wire _issue_entry_T_716 = _issue_entry_T_715 | _issue_entry_T_709; // @[Mux.scala:30:73] wire _issue_entry_T_717 = _issue_entry_T_716 | _issue_entry_T_710; // @[Mux.scala:30:73] wire _issue_entry_T_718 = _issue_entry_T_717 | _issue_entry_T_711; // @[Mux.scala:30:73] wire _issue_entry_T_719 = _issue_entry_T_718 | _issue_entry_T_712; // @[Mux.scala:30:73] assign _issue_entry_WIRE_55 = _issue_entry_T_719; // @[Mux.scala:30:73] assign _issue_entry_WIRE_40_sum = _issue_entry_WIRE_55; // @[Mux.scala:30:73] wire _issue_entry_T_720 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30] wire _issue_entry_T_721 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30] wire _issue_entry_T_722 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30] wire _issue_entry_T_723 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30] wire _issue_entry_T_724 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30] wire _issue_entry_T_725 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30] wire _issue_entry_T_726 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30] wire _issue_entry_T_727 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30] wire _issue_entry_T_728 = _issue_entry_T_720 | _issue_entry_T_721; // @[Mux.scala:30:73] wire _issue_entry_T_729 = _issue_entry_T_728 | _issue_entry_T_722; // @[Mux.scala:30:73] wire _issue_entry_T_730 = _issue_entry_T_729 | _issue_entry_T_723; // @[Mux.scala:30:73] wire _issue_entry_T_731 = _issue_entry_T_730 | _issue_entry_T_724; // @[Mux.scala:30:73] wire _issue_entry_T_732 = _issue_entry_T_731 | _issue_entry_T_725; // @[Mux.scala:30:73] wire _issue_entry_T_733 = _issue_entry_T_732 | _issue_entry_T_726; // @[Mux.scala:30:73] wire _issue_entry_T_734 = _issue_entry_T_733 | _issue_entry_T_727; // @[Mux.scala:30:73] assign _issue_entry_WIRE_56 = _issue_entry_T_734; // @[Mux.scala:30:73] assign _issue_entry_WIRE_40_mxr = _issue_entry_WIRE_56; // @[Mux.scala:30:73] wire _issue_entry_T_735 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30] wire _issue_entry_T_736 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30] wire _issue_entry_T_737 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30] wire _issue_entry_T_738 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30] wire _issue_entry_T_739 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30] wire _issue_entry_T_740 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30] wire _issue_entry_T_741 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30] wire _issue_entry_T_742 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30] wire _issue_entry_T_743 = _issue_entry_T_735 | _issue_entry_T_736; // @[Mux.scala:30:73] wire _issue_entry_T_744 = _issue_entry_T_743 | _issue_entry_T_737; // @[Mux.scala:30:73] wire _issue_entry_T_745 = _issue_entry_T_744 | _issue_entry_T_738; // @[Mux.scala:30:73] wire _issue_entry_T_746 = _issue_entry_T_745 | _issue_entry_T_739; // @[Mux.scala:30:73] wire _issue_entry_T_747 = _issue_entry_T_746 | _issue_entry_T_740; // @[Mux.scala:30:73] wire _issue_entry_T_748 = _issue_entry_T_747 | _issue_entry_T_741; // @[Mux.scala:30:73] wire _issue_entry_T_749 = _issue_entry_T_748 | _issue_entry_T_742; // @[Mux.scala:30:73] assign _issue_entry_WIRE_57 = _issue_entry_T_749; // @[Mux.scala:30:73] assign _issue_entry_WIRE_40_tvm = _issue_entry_WIRE_57; // @[Mux.scala:30:73] wire _issue_entry_T_750 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30] wire _issue_entry_T_751 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30] wire _issue_entry_T_752 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30] wire _issue_entry_T_753 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30] wire _issue_entry_T_754 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30] wire _issue_entry_T_755 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30] wire _issue_entry_T_756 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30] wire _issue_entry_T_757 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30] wire _issue_entry_T_758 = _issue_entry_T_750 | _issue_entry_T_751; // @[Mux.scala:30:73] wire _issue_entry_T_759 = _issue_entry_T_758 | _issue_entry_T_752; // @[Mux.scala:30:73] wire _issue_entry_T_760 = _issue_entry_T_759 | _issue_entry_T_753; // @[Mux.scala:30:73] wire _issue_entry_T_761 = _issue_entry_T_760 | _issue_entry_T_754; // @[Mux.scala:30:73] wire _issue_entry_T_762 = _issue_entry_T_761 | _issue_entry_T_755; // @[Mux.scala:30:73] wire _issue_entry_T_763 = _issue_entry_T_762 | _issue_entry_T_756; // @[Mux.scala:30:73] wire _issue_entry_T_764 = _issue_entry_T_763 | _issue_entry_T_757; // @[Mux.scala:30:73] assign _issue_entry_WIRE_58 = _issue_entry_T_764; // @[Mux.scala:30:73] assign _issue_entry_WIRE_40_tw = _issue_entry_WIRE_58; // @[Mux.scala:30:73] wire _issue_entry_T_765 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30] wire _issue_entry_T_766 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30] wire _issue_entry_T_767 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30] wire _issue_entry_T_768 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30] wire _issue_entry_T_769 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30] wire _issue_entry_T_770 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30] wire _issue_entry_T_771 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30] wire _issue_entry_T_772 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30] wire _issue_entry_T_773 = _issue_entry_T_765 | _issue_entry_T_766; // @[Mux.scala:30:73] wire _issue_entry_T_774 = _issue_entry_T_773 | _issue_entry_T_767; // @[Mux.scala:30:73] wire _issue_entry_T_775 = _issue_entry_T_774 | _issue_entry_T_768; // @[Mux.scala:30:73] wire _issue_entry_T_776 = _issue_entry_T_775 | _issue_entry_T_769; // @[Mux.scala:30:73] wire _issue_entry_T_777 = _issue_entry_T_776 | _issue_entry_T_770; // @[Mux.scala:30:73] wire _issue_entry_T_778 = _issue_entry_T_777 | _issue_entry_T_771; // @[Mux.scala:30:73] wire _issue_entry_T_779 = _issue_entry_T_778 | _issue_entry_T_772; // @[Mux.scala:30:73] assign _issue_entry_WIRE_59 = _issue_entry_T_779; // @[Mux.scala:30:73] assign _issue_entry_WIRE_40_tsr = _issue_entry_WIRE_59; // @[Mux.scala:30:73] wire [7:0] _issue_entry_T_780 = issue_sel_0 ? entries_ld_0_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30] wire [7:0] _issue_entry_T_781 = issue_sel_1 ? entries_ld_1_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30] wire [7:0] _issue_entry_T_782 = issue_sel_2 ? entries_ld_2_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30] wire [7:0] _issue_entry_T_783 = issue_sel_3 ? entries_ld_3_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30] wire [7:0] _issue_entry_T_784 = issue_sel_4 ? entries_ld_4_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30] wire [7:0] _issue_entry_T_785 = issue_sel_5 ? entries_ld_5_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30] wire [7:0] _issue_entry_T_786 = issue_sel_6 ? entries_ld_6_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30] wire [7:0] _issue_entry_T_787 = issue_sel_7 ? entries_ld_7_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30] wire [7:0] _issue_entry_T_788 = _issue_entry_T_780 | _issue_entry_T_781; // @[Mux.scala:30:73] wire [7:0] _issue_entry_T_789 = _issue_entry_T_788 | _issue_entry_T_782; // @[Mux.scala:30:73] wire [7:0] _issue_entry_T_790 = _issue_entry_T_789 | _issue_entry_T_783; // @[Mux.scala:30:73] wire [7:0] _issue_entry_T_791 = _issue_entry_T_790 | _issue_entry_T_784; // @[Mux.scala:30:73] wire [7:0] _issue_entry_T_792 = _issue_entry_T_791 | _issue_entry_T_785; // @[Mux.scala:30:73] wire [7:0] _issue_entry_T_793 = _issue_entry_T_792 | _issue_entry_T_786; // @[Mux.scala:30:73] wire [7:0] _issue_entry_T_794 = _issue_entry_T_793 | _issue_entry_T_787; // @[Mux.scala:30:73] assign _issue_entry_WIRE_60 = _issue_entry_T_794; // @[Mux.scala:30:73] assign _issue_entry_WIRE_40_zero1 = _issue_entry_WIRE_60; // @[Mux.scala:30:73] wire _issue_entry_T_795 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30] wire _issue_entry_T_796 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30] wire _issue_entry_T_797 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30] wire _issue_entry_T_798 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30] wire _issue_entry_T_799 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30] wire _issue_entry_T_800 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30] wire _issue_entry_T_801 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30] wire _issue_entry_T_802 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30] wire _issue_entry_T_803 = _issue_entry_T_795 | _issue_entry_T_796; // @[Mux.scala:30:73] wire _issue_entry_T_804 = _issue_entry_T_803 | _issue_entry_T_797; // @[Mux.scala:30:73] wire _issue_entry_T_805 = _issue_entry_T_804 | _issue_entry_T_798; // @[Mux.scala:30:73] wire _issue_entry_T_806 = _issue_entry_T_805 | _issue_entry_T_799; // @[Mux.scala:30:73] wire _issue_entry_T_807 = _issue_entry_T_806 | _issue_entry_T_800; // @[Mux.scala:30:73] wire _issue_entry_T_808 = _issue_entry_T_807 | _issue_entry_T_801; // @[Mux.scala:30:73] wire _issue_entry_T_809 = _issue_entry_T_808 | _issue_entry_T_802; // @[Mux.scala:30:73] assign _issue_entry_WIRE_61 = _issue_entry_T_809; // @[Mux.scala:30:73] assign _issue_entry_WIRE_40_sd_rv32 = _issue_entry_WIRE_61; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_810 = issue_sel_0 ? entries_ld_0_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_811 = issue_sel_1 ? entries_ld_1_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_812 = issue_sel_2 ? entries_ld_2_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_813 = issue_sel_3 ? entries_ld_3_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_814 = issue_sel_4 ? entries_ld_4_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_815 = issue_sel_5 ? entries_ld_5_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_816 = issue_sel_6 ? entries_ld_6_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_817 = issue_sel_7 ? entries_ld_7_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_818 = _issue_entry_T_810 | _issue_entry_T_811; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_819 = _issue_entry_T_818 | _issue_entry_T_812; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_820 = _issue_entry_T_819 | _issue_entry_T_813; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_821 = _issue_entry_T_820 | _issue_entry_T_814; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_822 = _issue_entry_T_821 | _issue_entry_T_815; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_823 = _issue_entry_T_822 | _issue_entry_T_816; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_824 = _issue_entry_T_823 | _issue_entry_T_817; // @[Mux.scala:30:73] assign _issue_entry_WIRE_62 = _issue_entry_T_824; // @[Mux.scala:30:73] assign _issue_entry_WIRE_40_uxl = _issue_entry_WIRE_62; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_825 = issue_sel_0 ? entries_ld_0_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_826 = issue_sel_1 ? entries_ld_1_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_827 = issue_sel_2 ? entries_ld_2_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_828 = issue_sel_3 ? entries_ld_3_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_829 = issue_sel_4 ? entries_ld_4_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_830 = issue_sel_5 ? entries_ld_5_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_831 = issue_sel_6 ? entries_ld_6_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_832 = issue_sel_7 ? entries_ld_7_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_833 = _issue_entry_T_825 | _issue_entry_T_826; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_834 = _issue_entry_T_833 | _issue_entry_T_827; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_835 = _issue_entry_T_834 | _issue_entry_T_828; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_836 = _issue_entry_T_835 | _issue_entry_T_829; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_837 = _issue_entry_T_836 | _issue_entry_T_830; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_838 = _issue_entry_T_837 | _issue_entry_T_831; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_839 = _issue_entry_T_838 | _issue_entry_T_832; // @[Mux.scala:30:73] assign _issue_entry_WIRE_63 = _issue_entry_T_839; // @[Mux.scala:30:73] assign _issue_entry_WIRE_40_sxl = _issue_entry_WIRE_63; // @[Mux.scala:30:73] wire _issue_entry_T_840 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30] wire _issue_entry_T_841 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30] wire _issue_entry_T_842 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30] wire _issue_entry_T_843 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30] wire _issue_entry_T_844 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30] wire _issue_entry_T_845 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30] wire _issue_entry_T_846 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30] wire _issue_entry_T_847 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30] wire _issue_entry_T_848 = _issue_entry_T_840 | _issue_entry_T_841; // @[Mux.scala:30:73] wire _issue_entry_T_849 = _issue_entry_T_848 | _issue_entry_T_842; // @[Mux.scala:30:73] wire _issue_entry_T_850 = _issue_entry_T_849 | _issue_entry_T_843; // @[Mux.scala:30:73] wire _issue_entry_T_851 = _issue_entry_T_850 | _issue_entry_T_844; // @[Mux.scala:30:73] wire _issue_entry_T_852 = _issue_entry_T_851 | _issue_entry_T_845; // @[Mux.scala:30:73] wire _issue_entry_T_853 = _issue_entry_T_852 | _issue_entry_T_846; // @[Mux.scala:30:73] wire _issue_entry_T_854 = _issue_entry_T_853 | _issue_entry_T_847; // @[Mux.scala:30:73] assign _issue_entry_WIRE_64 = _issue_entry_T_854; // @[Mux.scala:30:73] assign _issue_entry_WIRE_40_sbe = _issue_entry_WIRE_64; // @[Mux.scala:30:73] wire _issue_entry_T_855 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30] wire _issue_entry_T_856 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30] wire _issue_entry_T_857 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30] wire _issue_entry_T_858 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30] wire _issue_entry_T_859 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30] wire _issue_entry_T_860 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30] wire _issue_entry_T_861 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30] wire _issue_entry_T_862 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30] wire _issue_entry_T_863 = _issue_entry_T_855 | _issue_entry_T_856; // @[Mux.scala:30:73] wire _issue_entry_T_864 = _issue_entry_T_863 | _issue_entry_T_857; // @[Mux.scala:30:73] wire _issue_entry_T_865 = _issue_entry_T_864 | _issue_entry_T_858; // @[Mux.scala:30:73] wire _issue_entry_T_866 = _issue_entry_T_865 | _issue_entry_T_859; // @[Mux.scala:30:73] wire _issue_entry_T_867 = _issue_entry_T_866 | _issue_entry_T_860; // @[Mux.scala:30:73] wire _issue_entry_T_868 = _issue_entry_T_867 | _issue_entry_T_861; // @[Mux.scala:30:73] wire _issue_entry_T_869 = _issue_entry_T_868 | _issue_entry_T_862; // @[Mux.scala:30:73] assign _issue_entry_WIRE_65 = _issue_entry_T_869; // @[Mux.scala:30:73] assign _issue_entry_WIRE_40_mbe = _issue_entry_WIRE_65; // @[Mux.scala:30:73] wire _issue_entry_T_870 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30] wire _issue_entry_T_871 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30] wire _issue_entry_T_872 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30] wire _issue_entry_T_873 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30] wire _issue_entry_T_874 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30] wire _issue_entry_T_875 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30] wire _issue_entry_T_876 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30] wire _issue_entry_T_877 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30] wire _issue_entry_T_878 = _issue_entry_T_870 | _issue_entry_T_871; // @[Mux.scala:30:73] wire _issue_entry_T_879 = _issue_entry_T_878 | _issue_entry_T_872; // @[Mux.scala:30:73] wire _issue_entry_T_880 = _issue_entry_T_879 | _issue_entry_T_873; // @[Mux.scala:30:73] wire _issue_entry_T_881 = _issue_entry_T_880 | _issue_entry_T_874; // @[Mux.scala:30:73] wire _issue_entry_T_882 = _issue_entry_T_881 | _issue_entry_T_875; // @[Mux.scala:30:73] wire _issue_entry_T_883 = _issue_entry_T_882 | _issue_entry_T_876; // @[Mux.scala:30:73] wire _issue_entry_T_884 = _issue_entry_T_883 | _issue_entry_T_877; // @[Mux.scala:30:73] assign _issue_entry_WIRE_66 = _issue_entry_T_884; // @[Mux.scala:30:73] assign _issue_entry_WIRE_40_gva = _issue_entry_WIRE_66; // @[Mux.scala:30:73] wire _issue_entry_T_885 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30] wire _issue_entry_T_886 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30] wire _issue_entry_T_887 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30] wire _issue_entry_T_888 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30] wire _issue_entry_T_889 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30] wire _issue_entry_T_890 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30] wire _issue_entry_T_891 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30] wire _issue_entry_T_892 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30] wire _issue_entry_T_893 = _issue_entry_T_885 | _issue_entry_T_886; // @[Mux.scala:30:73] wire _issue_entry_T_894 = _issue_entry_T_893 | _issue_entry_T_887; // @[Mux.scala:30:73] wire _issue_entry_T_895 = _issue_entry_T_894 | _issue_entry_T_888; // @[Mux.scala:30:73] wire _issue_entry_T_896 = _issue_entry_T_895 | _issue_entry_T_889; // @[Mux.scala:30:73] wire _issue_entry_T_897 = _issue_entry_T_896 | _issue_entry_T_890; // @[Mux.scala:30:73] wire _issue_entry_T_898 = _issue_entry_T_897 | _issue_entry_T_891; // @[Mux.scala:30:73] wire _issue_entry_T_899 = _issue_entry_T_898 | _issue_entry_T_892; // @[Mux.scala:30:73] assign _issue_entry_WIRE_67 = _issue_entry_T_899; // @[Mux.scala:30:73] assign _issue_entry_WIRE_40_mpv = _issue_entry_WIRE_67; // @[Mux.scala:30:73] wire [22:0] _issue_entry_T_900 = issue_sel_0 ? entries_ld_0_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30] wire [22:0] _issue_entry_T_901 = issue_sel_1 ? entries_ld_1_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30] wire [22:0] _issue_entry_T_902 = issue_sel_2 ? entries_ld_2_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30] wire [22:0] _issue_entry_T_903 = issue_sel_3 ? entries_ld_3_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30] wire [22:0] _issue_entry_T_904 = issue_sel_4 ? entries_ld_4_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30] wire [22:0] _issue_entry_T_905 = issue_sel_5 ? entries_ld_5_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30] wire [22:0] _issue_entry_T_906 = issue_sel_6 ? entries_ld_6_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30] wire [22:0] _issue_entry_T_907 = issue_sel_7 ? entries_ld_7_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30] wire [22:0] _issue_entry_T_908 = _issue_entry_T_900 | _issue_entry_T_901; // @[Mux.scala:30:73] wire [22:0] _issue_entry_T_909 = _issue_entry_T_908 | _issue_entry_T_902; // @[Mux.scala:30:73] wire [22:0] _issue_entry_T_910 = _issue_entry_T_909 | _issue_entry_T_903; // @[Mux.scala:30:73] wire [22:0] _issue_entry_T_911 = _issue_entry_T_910 | _issue_entry_T_904; // @[Mux.scala:30:73] wire [22:0] _issue_entry_T_912 = _issue_entry_T_911 | _issue_entry_T_905; // @[Mux.scala:30:73] wire [22:0] _issue_entry_T_913 = _issue_entry_T_912 | _issue_entry_T_906; // @[Mux.scala:30:73] wire [22:0] _issue_entry_T_914 = _issue_entry_T_913 | _issue_entry_T_907; // @[Mux.scala:30:73] assign _issue_entry_WIRE_68 = _issue_entry_T_914; // @[Mux.scala:30:73] assign _issue_entry_WIRE_40_zero2 = _issue_entry_WIRE_68; // @[Mux.scala:30:73] wire _issue_entry_T_915 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30] wire _issue_entry_T_916 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30] wire _issue_entry_T_917 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30] wire _issue_entry_T_918 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30] wire _issue_entry_T_919 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30] wire _issue_entry_T_920 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30] wire _issue_entry_T_921 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30] wire _issue_entry_T_922 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30] wire _issue_entry_T_923 = _issue_entry_T_915 | _issue_entry_T_916; // @[Mux.scala:30:73] wire _issue_entry_T_924 = _issue_entry_T_923 | _issue_entry_T_917; // @[Mux.scala:30:73] wire _issue_entry_T_925 = _issue_entry_T_924 | _issue_entry_T_918; // @[Mux.scala:30:73] wire _issue_entry_T_926 = _issue_entry_T_925 | _issue_entry_T_919; // @[Mux.scala:30:73] wire _issue_entry_T_927 = _issue_entry_T_926 | _issue_entry_T_920; // @[Mux.scala:30:73] wire _issue_entry_T_928 = _issue_entry_T_927 | _issue_entry_T_921; // @[Mux.scala:30:73] wire _issue_entry_T_929 = _issue_entry_T_928 | _issue_entry_T_922; // @[Mux.scala:30:73] assign _issue_entry_WIRE_69 = _issue_entry_T_929; // @[Mux.scala:30:73] assign _issue_entry_WIRE_40_sd = _issue_entry_WIRE_69; // @[Mux.scala:30:73] wire _issue_entry_T_930 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30] wire _issue_entry_T_931 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30] wire _issue_entry_T_932 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30] wire _issue_entry_T_933 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30] wire _issue_entry_T_934 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30] wire _issue_entry_T_935 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30] wire _issue_entry_T_936 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30] wire _issue_entry_T_937 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30] wire _issue_entry_T_938 = _issue_entry_T_930 | _issue_entry_T_931; // @[Mux.scala:30:73] wire _issue_entry_T_939 = _issue_entry_T_938 | _issue_entry_T_932; // @[Mux.scala:30:73] wire _issue_entry_T_940 = _issue_entry_T_939 | _issue_entry_T_933; // @[Mux.scala:30:73] wire _issue_entry_T_941 = _issue_entry_T_940 | _issue_entry_T_934; // @[Mux.scala:30:73] wire _issue_entry_T_942 = _issue_entry_T_941 | _issue_entry_T_935; // @[Mux.scala:30:73] wire _issue_entry_T_943 = _issue_entry_T_942 | _issue_entry_T_936; // @[Mux.scala:30:73] wire _issue_entry_T_944 = _issue_entry_T_943 | _issue_entry_T_937; // @[Mux.scala:30:73] assign _issue_entry_WIRE_70 = _issue_entry_T_944; // @[Mux.scala:30:73] assign _issue_entry_WIRE_40_v = _issue_entry_WIRE_70; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_945 = issue_sel_0 ? entries_ld_0_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_946 = issue_sel_1 ? entries_ld_1_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_947 = issue_sel_2 ? entries_ld_2_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_948 = issue_sel_3 ? entries_ld_3_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_949 = issue_sel_4 ? entries_ld_4_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_950 = issue_sel_5 ? entries_ld_5_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_951 = issue_sel_6 ? entries_ld_6_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_952 = issue_sel_7 ? entries_ld_7_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_953 = _issue_entry_T_945 | _issue_entry_T_946; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_954 = _issue_entry_T_953 | _issue_entry_T_947; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_955 = _issue_entry_T_954 | _issue_entry_T_948; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_956 = _issue_entry_T_955 | _issue_entry_T_949; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_957 = _issue_entry_T_956 | _issue_entry_T_950; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_958 = _issue_entry_T_957 | _issue_entry_T_951; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_959 = _issue_entry_T_958 | _issue_entry_T_952; // @[Mux.scala:30:73] assign _issue_entry_WIRE_71 = _issue_entry_T_959; // @[Mux.scala:30:73] assign _issue_entry_WIRE_40_prv = _issue_entry_WIRE_71; // @[Mux.scala:30:73] wire _issue_entry_T_960 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30] wire _issue_entry_T_961 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30] wire _issue_entry_T_962 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30] wire _issue_entry_T_963 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30] wire _issue_entry_T_964 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30] wire _issue_entry_T_965 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30] wire _issue_entry_T_966 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30] wire _issue_entry_T_967 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30] wire _issue_entry_T_968 = _issue_entry_T_960 | _issue_entry_T_961; // @[Mux.scala:30:73] wire _issue_entry_T_969 = _issue_entry_T_968 | _issue_entry_T_962; // @[Mux.scala:30:73] wire _issue_entry_T_970 = _issue_entry_T_969 | _issue_entry_T_963; // @[Mux.scala:30:73] wire _issue_entry_T_971 = _issue_entry_T_970 | _issue_entry_T_964; // @[Mux.scala:30:73] wire _issue_entry_T_972 = _issue_entry_T_971 | _issue_entry_T_965; // @[Mux.scala:30:73] wire _issue_entry_T_973 = _issue_entry_T_972 | _issue_entry_T_966; // @[Mux.scala:30:73] wire _issue_entry_T_974 = _issue_entry_T_973 | _issue_entry_T_967; // @[Mux.scala:30:73] assign _issue_entry_WIRE_72 = _issue_entry_T_974; // @[Mux.scala:30:73] assign _issue_entry_WIRE_40_dv = _issue_entry_WIRE_72; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_975 = issue_sel_0 ? entries_ld_0_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_976 = issue_sel_1 ? entries_ld_1_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_977 = issue_sel_2 ? entries_ld_2_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_978 = issue_sel_3 ? entries_ld_3_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_979 = issue_sel_4 ? entries_ld_4_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_980 = issue_sel_5 ? entries_ld_5_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_981 = issue_sel_6 ? entries_ld_6_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_982 = issue_sel_7 ? entries_ld_7_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_983 = _issue_entry_T_975 | _issue_entry_T_976; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_984 = _issue_entry_T_983 | _issue_entry_T_977; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_985 = _issue_entry_T_984 | _issue_entry_T_978; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_986 = _issue_entry_T_985 | _issue_entry_T_979; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_987 = _issue_entry_T_986 | _issue_entry_T_980; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_988 = _issue_entry_T_987 | _issue_entry_T_981; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_989 = _issue_entry_T_988 | _issue_entry_T_982; // @[Mux.scala:30:73] assign _issue_entry_WIRE_73 = _issue_entry_T_989; // @[Mux.scala:30:73] assign _issue_entry_WIRE_40_dprv = _issue_entry_WIRE_73; // @[Mux.scala:30:73] wire [31:0] _issue_entry_T_990 = issue_sel_0 ? entries_ld_0_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_991 = issue_sel_1 ? entries_ld_1_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_992 = issue_sel_2 ? entries_ld_2_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_993 = issue_sel_3 ? entries_ld_3_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_994 = issue_sel_4 ? entries_ld_4_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_995 = issue_sel_5 ? entries_ld_5_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_996 = issue_sel_6 ? entries_ld_6_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_997 = issue_sel_7 ? entries_ld_7_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_998 = _issue_entry_T_990 | _issue_entry_T_991; // @[Mux.scala:30:73] wire [31:0] _issue_entry_T_999 = _issue_entry_T_998 | _issue_entry_T_992; // @[Mux.scala:30:73] wire [31:0] _issue_entry_T_1000 = _issue_entry_T_999 | _issue_entry_T_993; // @[Mux.scala:30:73] wire [31:0] _issue_entry_T_1001 = _issue_entry_T_1000 | _issue_entry_T_994; // @[Mux.scala:30:73] wire [31:0] _issue_entry_T_1002 = _issue_entry_T_1001 | _issue_entry_T_995; // @[Mux.scala:30:73] wire [31:0] _issue_entry_T_1003 = _issue_entry_T_1002 | _issue_entry_T_996; // @[Mux.scala:30:73] wire [31:0] _issue_entry_T_1004 = _issue_entry_T_1003 | _issue_entry_T_997; // @[Mux.scala:30:73] assign _issue_entry_WIRE_74 = _issue_entry_T_1004; // @[Mux.scala:30:73] assign _issue_entry_WIRE_40_isa = _issue_entry_WIRE_74; // @[Mux.scala:30:73] wire _issue_entry_T_1005 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30] wire _issue_entry_T_1006 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30] wire _issue_entry_T_1007 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30] wire _issue_entry_T_1008 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30] wire _issue_entry_T_1009 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30] wire _issue_entry_T_1010 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30] wire _issue_entry_T_1011 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30] wire _issue_entry_T_1012 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30] wire _issue_entry_T_1013 = _issue_entry_T_1005 | _issue_entry_T_1006; // @[Mux.scala:30:73] wire _issue_entry_T_1014 = _issue_entry_T_1013 | _issue_entry_T_1007; // @[Mux.scala:30:73] wire _issue_entry_T_1015 = _issue_entry_T_1014 | _issue_entry_T_1008; // @[Mux.scala:30:73] wire _issue_entry_T_1016 = _issue_entry_T_1015 | _issue_entry_T_1009; // @[Mux.scala:30:73] wire _issue_entry_T_1017 = _issue_entry_T_1016 | _issue_entry_T_1010; // @[Mux.scala:30:73] wire _issue_entry_T_1018 = _issue_entry_T_1017 | _issue_entry_T_1011; // @[Mux.scala:30:73] wire _issue_entry_T_1019 = _issue_entry_T_1018 | _issue_entry_T_1012; // @[Mux.scala:30:73] assign _issue_entry_WIRE_75 = _issue_entry_T_1019; // @[Mux.scala:30:73] assign _issue_entry_WIRE_40_wfi = _issue_entry_WIRE_75; // @[Mux.scala:30:73] wire _issue_entry_T_1020 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30] wire _issue_entry_T_1021 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30] wire _issue_entry_T_1022 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30] wire _issue_entry_T_1023 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30] wire _issue_entry_T_1024 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30] wire _issue_entry_T_1025 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30] wire _issue_entry_T_1026 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30] wire _issue_entry_T_1027 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30] wire _issue_entry_T_1028 = _issue_entry_T_1020 | _issue_entry_T_1021; // @[Mux.scala:30:73] wire _issue_entry_T_1029 = _issue_entry_T_1028 | _issue_entry_T_1022; // @[Mux.scala:30:73] wire _issue_entry_T_1030 = _issue_entry_T_1029 | _issue_entry_T_1023; // @[Mux.scala:30:73] wire _issue_entry_T_1031 = _issue_entry_T_1030 | _issue_entry_T_1024; // @[Mux.scala:30:73] wire _issue_entry_T_1032 = _issue_entry_T_1031 | _issue_entry_T_1025; // @[Mux.scala:30:73] wire _issue_entry_T_1033 = _issue_entry_T_1032 | _issue_entry_T_1026; // @[Mux.scala:30:73] wire _issue_entry_T_1034 = _issue_entry_T_1033 | _issue_entry_T_1027; // @[Mux.scala:30:73] assign _issue_entry_WIRE_76 = _issue_entry_T_1034; // @[Mux.scala:30:73] assign _issue_entry_WIRE_40_cease = _issue_entry_WIRE_76; // @[Mux.scala:30:73] wire _issue_entry_T_1035 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30] wire _issue_entry_T_1036 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30] wire _issue_entry_T_1037 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30] wire _issue_entry_T_1038 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30] wire _issue_entry_T_1039 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30] wire _issue_entry_T_1040 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30] wire _issue_entry_T_1041 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30] wire _issue_entry_T_1042 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30] wire _issue_entry_T_1043 = _issue_entry_T_1035 | _issue_entry_T_1036; // @[Mux.scala:30:73] wire _issue_entry_T_1044 = _issue_entry_T_1043 | _issue_entry_T_1037; // @[Mux.scala:30:73] wire _issue_entry_T_1045 = _issue_entry_T_1044 | _issue_entry_T_1038; // @[Mux.scala:30:73] wire _issue_entry_T_1046 = _issue_entry_T_1045 | _issue_entry_T_1039; // @[Mux.scala:30:73] wire _issue_entry_T_1047 = _issue_entry_T_1046 | _issue_entry_T_1040; // @[Mux.scala:30:73] wire _issue_entry_T_1048 = _issue_entry_T_1047 | _issue_entry_T_1041; // @[Mux.scala:30:73] wire _issue_entry_T_1049 = _issue_entry_T_1048 | _issue_entry_T_1042; // @[Mux.scala:30:73] assign _issue_entry_WIRE_77 = _issue_entry_T_1049; // @[Mux.scala:30:73] assign _issue_entry_WIRE_40_debug = _issue_entry_WIRE_77; // @[Mux.scala:30:73] wire [63:0] _issue_entry_T_1050 = issue_sel_0 ? entries_ld_0_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_1051 = issue_sel_1 ? entries_ld_1_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_1052 = issue_sel_2 ? entries_ld_2_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_1053 = issue_sel_3 ? entries_ld_3_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_1054 = issue_sel_4 ? entries_ld_4_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_1055 = issue_sel_5 ? entries_ld_5_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_1056 = issue_sel_6 ? entries_ld_6_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_1057 = issue_sel_7 ? entries_ld_7_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_1058 = _issue_entry_T_1050 | _issue_entry_T_1051; // @[Mux.scala:30:73] wire [63:0] _issue_entry_T_1059 = _issue_entry_T_1058 | _issue_entry_T_1052; // @[Mux.scala:30:73] wire [63:0] _issue_entry_T_1060 = _issue_entry_T_1059 | _issue_entry_T_1053; // @[Mux.scala:30:73] wire [63:0] _issue_entry_T_1061 = _issue_entry_T_1060 | _issue_entry_T_1054; // @[Mux.scala:30:73] wire [63:0] _issue_entry_T_1062 = _issue_entry_T_1061 | _issue_entry_T_1055; // @[Mux.scala:30:73] wire [63:0] _issue_entry_T_1063 = _issue_entry_T_1062 | _issue_entry_T_1056; // @[Mux.scala:30:73] wire [63:0] _issue_entry_T_1064 = _issue_entry_T_1063 | _issue_entry_T_1057; // @[Mux.scala:30:73] assign _issue_entry_WIRE_78 = _issue_entry_T_1064; // @[Mux.scala:30:73] assign _issue_entry_WIRE_39_rs2 = _issue_entry_WIRE_78; // @[Mux.scala:30:73] wire [63:0] _issue_entry_T_1065 = issue_sel_0 ? entries_ld_0_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_1066 = issue_sel_1 ? entries_ld_1_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_1067 = issue_sel_2 ? entries_ld_2_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_1068 = issue_sel_3 ? entries_ld_3_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_1069 = issue_sel_4 ? entries_ld_4_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_1070 = issue_sel_5 ? entries_ld_5_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_1071 = issue_sel_6 ? entries_ld_6_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_1072 = issue_sel_7 ? entries_ld_7_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_1073 = _issue_entry_T_1065 | _issue_entry_T_1066; // @[Mux.scala:30:73] wire [63:0] _issue_entry_T_1074 = _issue_entry_T_1073 | _issue_entry_T_1067; // @[Mux.scala:30:73] wire [63:0] _issue_entry_T_1075 = _issue_entry_T_1074 | _issue_entry_T_1068; // @[Mux.scala:30:73] wire [63:0] _issue_entry_T_1076 = _issue_entry_T_1075 | _issue_entry_T_1069; // @[Mux.scala:30:73] wire [63:0] _issue_entry_T_1077 = _issue_entry_T_1076 | _issue_entry_T_1070; // @[Mux.scala:30:73] wire [63:0] _issue_entry_T_1078 = _issue_entry_T_1077 | _issue_entry_T_1071; // @[Mux.scala:30:73] wire [63:0] _issue_entry_T_1079 = _issue_entry_T_1078 | _issue_entry_T_1072; // @[Mux.scala:30:73] assign _issue_entry_WIRE_79 = _issue_entry_T_1079; // @[Mux.scala:30:73] assign _issue_entry_WIRE_39_rs1 = _issue_entry_WIRE_79; // @[Mux.scala:30:73] wire [6:0] _issue_entry_WIRE_88; // @[Mux.scala:30:73] assign _issue_entry_WIRE_39_inst_funct = _issue_entry_WIRE_80_funct; // @[Mux.scala:30:73] wire [4:0] _issue_entry_WIRE_87; // @[Mux.scala:30:73] assign _issue_entry_WIRE_39_inst_rs2 = _issue_entry_WIRE_80_rs2; // @[Mux.scala:30:73] wire [4:0] _issue_entry_WIRE_86; // @[Mux.scala:30:73] assign _issue_entry_WIRE_39_inst_rs1 = _issue_entry_WIRE_80_rs1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_85; // @[Mux.scala:30:73] assign _issue_entry_WIRE_39_inst_xd = _issue_entry_WIRE_80_xd; // @[Mux.scala:30:73] wire _issue_entry_WIRE_84; // @[Mux.scala:30:73] assign _issue_entry_WIRE_39_inst_xs1 = _issue_entry_WIRE_80_xs1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_83; // @[Mux.scala:30:73] assign _issue_entry_WIRE_39_inst_xs2 = _issue_entry_WIRE_80_xs2; // @[Mux.scala:30:73] wire [4:0] _issue_entry_WIRE_82; // @[Mux.scala:30:73] assign _issue_entry_WIRE_39_inst_rd = _issue_entry_WIRE_80_rd; // @[Mux.scala:30:73] wire [6:0] _issue_entry_WIRE_81; // @[Mux.scala:30:73] assign _issue_entry_WIRE_39_inst_opcode = _issue_entry_WIRE_80_opcode; // @[Mux.scala:30:73] wire [6:0] _issue_entry_T_1080 = issue_sel_0 ? entries_ld_0_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_1081 = issue_sel_1 ? entries_ld_1_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_1082 = issue_sel_2 ? entries_ld_2_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_1083 = issue_sel_3 ? entries_ld_3_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_1084 = issue_sel_4 ? entries_ld_4_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_1085 = issue_sel_5 ? entries_ld_5_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_1086 = issue_sel_6 ? entries_ld_6_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_1087 = issue_sel_7 ? entries_ld_7_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_1088 = _issue_entry_T_1080 | _issue_entry_T_1081; // @[Mux.scala:30:73] wire [6:0] _issue_entry_T_1089 = _issue_entry_T_1088 | _issue_entry_T_1082; // @[Mux.scala:30:73] wire [6:0] _issue_entry_T_1090 = _issue_entry_T_1089 | _issue_entry_T_1083; // @[Mux.scala:30:73] wire [6:0] _issue_entry_T_1091 = _issue_entry_T_1090 | _issue_entry_T_1084; // @[Mux.scala:30:73] wire [6:0] _issue_entry_T_1092 = _issue_entry_T_1091 | _issue_entry_T_1085; // @[Mux.scala:30:73] wire [6:0] _issue_entry_T_1093 = _issue_entry_T_1092 | _issue_entry_T_1086; // @[Mux.scala:30:73] wire [6:0] _issue_entry_T_1094 = _issue_entry_T_1093 | _issue_entry_T_1087; // @[Mux.scala:30:73] assign _issue_entry_WIRE_81 = _issue_entry_T_1094; // @[Mux.scala:30:73] assign _issue_entry_WIRE_80_opcode = _issue_entry_WIRE_81; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_1095 = issue_sel_0 ? entries_ld_0_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_1096 = issue_sel_1 ? entries_ld_1_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_1097 = issue_sel_2 ? entries_ld_2_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_1098 = issue_sel_3 ? entries_ld_3_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_1099 = issue_sel_4 ? entries_ld_4_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_1100 = issue_sel_5 ? entries_ld_5_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_1101 = issue_sel_6 ? entries_ld_6_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_1102 = issue_sel_7 ? entries_ld_7_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_1103 = _issue_entry_T_1095 | _issue_entry_T_1096; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_1104 = _issue_entry_T_1103 | _issue_entry_T_1097; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_1105 = _issue_entry_T_1104 | _issue_entry_T_1098; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_1106 = _issue_entry_T_1105 | _issue_entry_T_1099; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_1107 = _issue_entry_T_1106 | _issue_entry_T_1100; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_1108 = _issue_entry_T_1107 | _issue_entry_T_1101; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_1109 = _issue_entry_T_1108 | _issue_entry_T_1102; // @[Mux.scala:30:73] assign _issue_entry_WIRE_82 = _issue_entry_T_1109; // @[Mux.scala:30:73] assign _issue_entry_WIRE_80_rd = _issue_entry_WIRE_82; // @[Mux.scala:30:73] wire _issue_entry_T_1110 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30] wire _issue_entry_T_1111 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30] wire _issue_entry_T_1112 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30] wire _issue_entry_T_1113 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30] wire _issue_entry_T_1114 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30] wire _issue_entry_T_1115 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30] wire _issue_entry_T_1116 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30] wire _issue_entry_T_1117 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30] wire _issue_entry_T_1118 = _issue_entry_T_1110 | _issue_entry_T_1111; // @[Mux.scala:30:73] wire _issue_entry_T_1119 = _issue_entry_T_1118 | _issue_entry_T_1112; // @[Mux.scala:30:73] wire _issue_entry_T_1120 = _issue_entry_T_1119 | _issue_entry_T_1113; // @[Mux.scala:30:73] wire _issue_entry_T_1121 = _issue_entry_T_1120 | _issue_entry_T_1114; // @[Mux.scala:30:73] wire _issue_entry_T_1122 = _issue_entry_T_1121 | _issue_entry_T_1115; // @[Mux.scala:30:73] wire _issue_entry_T_1123 = _issue_entry_T_1122 | _issue_entry_T_1116; // @[Mux.scala:30:73] wire _issue_entry_T_1124 = _issue_entry_T_1123 | _issue_entry_T_1117; // @[Mux.scala:30:73] assign _issue_entry_WIRE_83 = _issue_entry_T_1124; // @[Mux.scala:30:73] assign _issue_entry_WIRE_80_xs2 = _issue_entry_WIRE_83; // @[Mux.scala:30:73] wire _issue_entry_T_1125 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30] wire _issue_entry_T_1126 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30] wire _issue_entry_T_1127 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30] wire _issue_entry_T_1128 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30] wire _issue_entry_T_1129 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30] wire _issue_entry_T_1130 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30] wire _issue_entry_T_1131 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30] wire _issue_entry_T_1132 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30] wire _issue_entry_T_1133 = _issue_entry_T_1125 | _issue_entry_T_1126; // @[Mux.scala:30:73] wire _issue_entry_T_1134 = _issue_entry_T_1133 | _issue_entry_T_1127; // @[Mux.scala:30:73] wire _issue_entry_T_1135 = _issue_entry_T_1134 | _issue_entry_T_1128; // @[Mux.scala:30:73] wire _issue_entry_T_1136 = _issue_entry_T_1135 | _issue_entry_T_1129; // @[Mux.scala:30:73] wire _issue_entry_T_1137 = _issue_entry_T_1136 | _issue_entry_T_1130; // @[Mux.scala:30:73] wire _issue_entry_T_1138 = _issue_entry_T_1137 | _issue_entry_T_1131; // @[Mux.scala:30:73] wire _issue_entry_T_1139 = _issue_entry_T_1138 | _issue_entry_T_1132; // @[Mux.scala:30:73] assign _issue_entry_WIRE_84 = _issue_entry_T_1139; // @[Mux.scala:30:73] assign _issue_entry_WIRE_80_xs1 = _issue_entry_WIRE_84; // @[Mux.scala:30:73] wire _issue_entry_T_1140 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30] wire _issue_entry_T_1141 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30] wire _issue_entry_T_1142 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30] wire _issue_entry_T_1143 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30] wire _issue_entry_T_1144 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30] wire _issue_entry_T_1145 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30] wire _issue_entry_T_1146 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30] wire _issue_entry_T_1147 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30] wire _issue_entry_T_1148 = _issue_entry_T_1140 | _issue_entry_T_1141; // @[Mux.scala:30:73] wire _issue_entry_T_1149 = _issue_entry_T_1148 | _issue_entry_T_1142; // @[Mux.scala:30:73] wire _issue_entry_T_1150 = _issue_entry_T_1149 | _issue_entry_T_1143; // @[Mux.scala:30:73] wire _issue_entry_T_1151 = _issue_entry_T_1150 | _issue_entry_T_1144; // @[Mux.scala:30:73] wire _issue_entry_T_1152 = _issue_entry_T_1151 | _issue_entry_T_1145; // @[Mux.scala:30:73] wire _issue_entry_T_1153 = _issue_entry_T_1152 | _issue_entry_T_1146; // @[Mux.scala:30:73] wire _issue_entry_T_1154 = _issue_entry_T_1153 | _issue_entry_T_1147; // @[Mux.scala:30:73] assign _issue_entry_WIRE_85 = _issue_entry_T_1154; // @[Mux.scala:30:73] assign _issue_entry_WIRE_80_xd = _issue_entry_WIRE_85; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_1155 = issue_sel_0 ? entries_ld_0_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_1156 = issue_sel_1 ? entries_ld_1_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_1157 = issue_sel_2 ? entries_ld_2_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_1158 = issue_sel_3 ? entries_ld_3_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_1159 = issue_sel_4 ? entries_ld_4_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_1160 = issue_sel_5 ? entries_ld_5_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_1161 = issue_sel_6 ? entries_ld_6_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_1162 = issue_sel_7 ? entries_ld_7_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_1163 = _issue_entry_T_1155 | _issue_entry_T_1156; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_1164 = _issue_entry_T_1163 | _issue_entry_T_1157; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_1165 = _issue_entry_T_1164 | _issue_entry_T_1158; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_1166 = _issue_entry_T_1165 | _issue_entry_T_1159; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_1167 = _issue_entry_T_1166 | _issue_entry_T_1160; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_1168 = _issue_entry_T_1167 | _issue_entry_T_1161; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_1169 = _issue_entry_T_1168 | _issue_entry_T_1162; // @[Mux.scala:30:73] assign _issue_entry_WIRE_86 = _issue_entry_T_1169; // @[Mux.scala:30:73] assign _issue_entry_WIRE_80_rs1 = _issue_entry_WIRE_86; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_1170 = issue_sel_0 ? entries_ld_0_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_1171 = issue_sel_1 ? entries_ld_1_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_1172 = issue_sel_2 ? entries_ld_2_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_1173 = issue_sel_3 ? entries_ld_3_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_1174 = issue_sel_4 ? entries_ld_4_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_1175 = issue_sel_5 ? entries_ld_5_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_1176 = issue_sel_6 ? entries_ld_6_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_1177 = issue_sel_7 ? entries_ld_7_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_1178 = _issue_entry_T_1170 | _issue_entry_T_1171; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_1179 = _issue_entry_T_1178 | _issue_entry_T_1172; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_1180 = _issue_entry_T_1179 | _issue_entry_T_1173; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_1181 = _issue_entry_T_1180 | _issue_entry_T_1174; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_1182 = _issue_entry_T_1181 | _issue_entry_T_1175; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_1183 = _issue_entry_T_1182 | _issue_entry_T_1176; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_1184 = _issue_entry_T_1183 | _issue_entry_T_1177; // @[Mux.scala:30:73] assign _issue_entry_WIRE_87 = _issue_entry_T_1184; // @[Mux.scala:30:73] assign _issue_entry_WIRE_80_rs2 = _issue_entry_WIRE_87; // @[Mux.scala:30:73] wire [6:0] _issue_entry_T_1185 = issue_sel_0 ? entries_ld_0_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_1186 = issue_sel_1 ? entries_ld_1_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_1187 = issue_sel_2 ? entries_ld_2_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_1188 = issue_sel_3 ? entries_ld_3_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_1189 = issue_sel_4 ? entries_ld_4_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_1190 = issue_sel_5 ? entries_ld_5_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_1191 = issue_sel_6 ? entries_ld_6_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_1192 = issue_sel_7 ? entries_ld_7_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_1193 = _issue_entry_T_1185 | _issue_entry_T_1186; // @[Mux.scala:30:73] wire [6:0] _issue_entry_T_1194 = _issue_entry_T_1193 | _issue_entry_T_1187; // @[Mux.scala:30:73] wire [6:0] _issue_entry_T_1195 = _issue_entry_T_1194 | _issue_entry_T_1188; // @[Mux.scala:30:73] wire [6:0] _issue_entry_T_1196 = _issue_entry_T_1195 | _issue_entry_T_1189; // @[Mux.scala:30:73] wire [6:0] _issue_entry_T_1197 = _issue_entry_T_1196 | _issue_entry_T_1190; // @[Mux.scala:30:73] wire [6:0] _issue_entry_T_1198 = _issue_entry_T_1197 | _issue_entry_T_1191; // @[Mux.scala:30:73] wire [6:0] _issue_entry_T_1199 = _issue_entry_T_1198 | _issue_entry_T_1192; // @[Mux.scala:30:73] assign _issue_entry_WIRE_88 = _issue_entry_T_1199; // @[Mux.scala:30:73] assign _issue_entry_WIRE_80_funct = _issue_entry_WIRE_88; // @[Mux.scala:30:73] wire _issue_entry_T_1200 = issue_sel_0 & entries_ld_0_bits_complete_on_issue; // @[OneHot.scala:83:30] wire _issue_entry_T_1201 = issue_sel_1 & entries_ld_1_bits_complete_on_issue; // @[OneHot.scala:83:30] wire _issue_entry_T_1202 = issue_sel_2 & entries_ld_2_bits_complete_on_issue; // @[OneHot.scala:83:30] wire _issue_entry_T_1203 = issue_sel_3 & entries_ld_3_bits_complete_on_issue; // @[OneHot.scala:83:30] wire _issue_entry_T_1204 = issue_sel_4 & entries_ld_4_bits_complete_on_issue; // @[OneHot.scala:83:30] wire _issue_entry_T_1205 = issue_sel_5 & entries_ld_5_bits_complete_on_issue; // @[OneHot.scala:83:30] wire _issue_entry_T_1206 = issue_sel_6 & entries_ld_6_bits_complete_on_issue; // @[OneHot.scala:83:30] wire _issue_entry_T_1207 = issue_sel_7 & entries_ld_7_bits_complete_on_issue; // @[OneHot.scala:83:30] wire _issue_entry_T_1208 = _issue_entry_T_1200 | _issue_entry_T_1201; // @[Mux.scala:30:73] wire _issue_entry_T_1209 = _issue_entry_T_1208 | _issue_entry_T_1202; // @[Mux.scala:30:73] wire _issue_entry_T_1210 = _issue_entry_T_1209 | _issue_entry_T_1203; // @[Mux.scala:30:73] wire _issue_entry_T_1211 = _issue_entry_T_1210 | _issue_entry_T_1204; // @[Mux.scala:30:73] wire _issue_entry_T_1212 = _issue_entry_T_1211 | _issue_entry_T_1205; // @[Mux.scala:30:73] wire _issue_entry_T_1213 = _issue_entry_T_1212 | _issue_entry_T_1206; // @[Mux.scala:30:73] wire _issue_entry_T_1214 = _issue_entry_T_1213 | _issue_entry_T_1207; // @[Mux.scala:30:73] assign _issue_entry_WIRE_89 = _issue_entry_T_1214; // @[Mux.scala:30:73] assign _issue_entry_WIRE_complete_on_issue = _issue_entry_WIRE_89; // @[Mux.scala:30:73] wire _issue_entry_T_1215 = issue_sel_0 & entries_ld_0_bits_issued; // @[OneHot.scala:83:30] wire _issue_entry_T_1216 = issue_sel_1 & entries_ld_1_bits_issued; // @[OneHot.scala:83:30] wire _issue_entry_T_1217 = issue_sel_2 & entries_ld_2_bits_issued; // @[OneHot.scala:83:30] wire _issue_entry_T_1218 = issue_sel_3 & entries_ld_3_bits_issued; // @[OneHot.scala:83:30] wire _issue_entry_T_1219 = issue_sel_4 & entries_ld_4_bits_issued; // @[OneHot.scala:83:30] wire _issue_entry_T_1220 = issue_sel_5 & entries_ld_5_bits_issued; // @[OneHot.scala:83:30] wire _issue_entry_T_1221 = issue_sel_6 & entries_ld_6_bits_issued; // @[OneHot.scala:83:30] wire _issue_entry_T_1222 = issue_sel_7 & entries_ld_7_bits_issued; // @[OneHot.scala:83:30] wire _issue_entry_T_1223 = _issue_entry_T_1215 | _issue_entry_T_1216; // @[Mux.scala:30:73] wire _issue_entry_T_1224 = _issue_entry_T_1223 | _issue_entry_T_1217; // @[Mux.scala:30:73] wire _issue_entry_T_1225 = _issue_entry_T_1224 | _issue_entry_T_1218; // @[Mux.scala:30:73] wire _issue_entry_T_1226 = _issue_entry_T_1225 | _issue_entry_T_1219; // @[Mux.scala:30:73] wire _issue_entry_T_1227 = _issue_entry_T_1226 | _issue_entry_T_1220; // @[Mux.scala:30:73] wire _issue_entry_T_1228 = _issue_entry_T_1227 | _issue_entry_T_1221; // @[Mux.scala:30:73] wire _issue_entry_T_1229 = _issue_entry_T_1228 | _issue_entry_T_1222; // @[Mux.scala:30:73] assign _issue_entry_WIRE_90 = _issue_entry_T_1229; // @[Mux.scala:30:73] assign _issue_entry_WIRE_issued = _issue_entry_WIRE_90; // @[Mux.scala:30:73] wire _issue_entry_T_1486 = issue_sel_0 & entries_ld_0_bits_opa_is_dst; // @[OneHot.scala:83:30] wire _issue_entry_T_1487 = issue_sel_1 & entries_ld_1_bits_opa_is_dst; // @[OneHot.scala:83:30] wire _issue_entry_T_1488 = issue_sel_2 & entries_ld_2_bits_opa_is_dst; // @[OneHot.scala:83:30] wire _issue_entry_T_1489 = issue_sel_3 & entries_ld_3_bits_opa_is_dst; // @[OneHot.scala:83:30] wire _issue_entry_T_1490 = issue_sel_4 & entries_ld_4_bits_opa_is_dst; // @[OneHot.scala:83:30] wire _issue_entry_T_1491 = issue_sel_5 & entries_ld_5_bits_opa_is_dst; // @[OneHot.scala:83:30] wire _issue_entry_T_1492 = issue_sel_6 & entries_ld_6_bits_opa_is_dst; // @[OneHot.scala:83:30] wire _issue_entry_T_1493 = issue_sel_7 & entries_ld_7_bits_opa_is_dst; // @[OneHot.scala:83:30] wire _issue_entry_T_1494 = _issue_entry_T_1486 | _issue_entry_T_1487; // @[Mux.scala:30:73] wire _issue_entry_T_1495 = _issue_entry_T_1494 | _issue_entry_T_1488; // @[Mux.scala:30:73] wire _issue_entry_T_1496 = _issue_entry_T_1495 | _issue_entry_T_1489; // @[Mux.scala:30:73] wire _issue_entry_T_1497 = _issue_entry_T_1496 | _issue_entry_T_1490; // @[Mux.scala:30:73] wire _issue_entry_T_1498 = _issue_entry_T_1497 | _issue_entry_T_1491; // @[Mux.scala:30:73] wire _issue_entry_T_1499 = _issue_entry_T_1498 | _issue_entry_T_1492; // @[Mux.scala:30:73] wire _issue_entry_T_1500 = _issue_entry_T_1499 | _issue_entry_T_1493; // @[Mux.scala:30:73] assign _issue_entry_WIRE_115 = _issue_entry_T_1500; // @[Mux.scala:30:73] assign _issue_entry_WIRE_opa_is_dst = _issue_entry_WIRE_115; // @[Mux.scala:30:73] wire _issue_entry_WIRE_139; // @[Mux.scala:30:73] assign _issue_entry_WIRE_opa_valid = _issue_entry_WIRE_116_valid; // @[Mux.scala:30:73] wire _issue_entry_WIRE_117_start_is_acc_addr; // @[Mux.scala:30:73] assign _issue_entry_WIRE_opa_bits_start_is_acc_addr = _issue_entry_WIRE_116_bits_start_is_acc_addr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_117_start_accumulate; // @[Mux.scala:30:73] assign _issue_entry_WIRE_opa_bits_start_accumulate = _issue_entry_WIRE_116_bits_start_accumulate; // @[Mux.scala:30:73] wire _issue_entry_WIRE_117_start_read_full_acc_row; // @[Mux.scala:30:73] assign _issue_entry_WIRE_opa_bits_start_read_full_acc_row = _issue_entry_WIRE_116_bits_start_read_full_acc_row; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_117_start_norm_cmd; // @[Mux.scala:30:73] assign _issue_entry_WIRE_opa_bits_start_norm_cmd = _issue_entry_WIRE_116_bits_start_norm_cmd; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_117_start_garbage; // @[Mux.scala:30:73] assign _issue_entry_WIRE_opa_bits_start_garbage = _issue_entry_WIRE_116_bits_start_garbage; // @[Mux.scala:30:73] wire _issue_entry_WIRE_117_start_garbage_bit; // @[Mux.scala:30:73] assign _issue_entry_WIRE_opa_bits_start_garbage_bit = _issue_entry_WIRE_116_bits_start_garbage_bit; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_117_start_data; // @[Mux.scala:30:73] assign _issue_entry_WIRE_opa_bits_start_data = _issue_entry_WIRE_116_bits_start_data; // @[Mux.scala:30:73] wire _issue_entry_WIRE_117_end_is_acc_addr; // @[Mux.scala:30:73] assign _issue_entry_WIRE_opa_bits_end_is_acc_addr = _issue_entry_WIRE_116_bits_end_is_acc_addr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_117_end_accumulate; // @[Mux.scala:30:73] assign _issue_entry_WIRE_opa_bits_end_accumulate = _issue_entry_WIRE_116_bits_end_accumulate; // @[Mux.scala:30:73] wire _issue_entry_WIRE_117_end_read_full_acc_row; // @[Mux.scala:30:73] assign _issue_entry_WIRE_opa_bits_end_read_full_acc_row = _issue_entry_WIRE_116_bits_end_read_full_acc_row; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_117_end_norm_cmd; // @[Mux.scala:30:73] assign _issue_entry_WIRE_opa_bits_end_norm_cmd = _issue_entry_WIRE_116_bits_end_norm_cmd; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_117_end_garbage; // @[Mux.scala:30:73] assign _issue_entry_WIRE_opa_bits_end_garbage = _issue_entry_WIRE_116_bits_end_garbage; // @[Mux.scala:30:73] wire _issue_entry_WIRE_117_end_garbage_bit; // @[Mux.scala:30:73] assign _issue_entry_WIRE_opa_bits_end_garbage_bit = _issue_entry_WIRE_116_bits_end_garbage_bit; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_117_end_data; // @[Mux.scala:30:73] assign _issue_entry_WIRE_opa_bits_end_data = _issue_entry_WIRE_116_bits_end_data; // @[Mux.scala:30:73] wire _issue_entry_WIRE_117_wraps_around; // @[Mux.scala:30:73] assign _issue_entry_WIRE_opa_bits_wraps_around = _issue_entry_WIRE_116_bits_wraps_around; // @[Mux.scala:30:73] wire _issue_entry_WIRE_129_is_acc_addr; // @[Mux.scala:30:73] assign _issue_entry_WIRE_116_bits_start_is_acc_addr = _issue_entry_WIRE_117_start_is_acc_addr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_129_accumulate; // @[Mux.scala:30:73] assign _issue_entry_WIRE_116_bits_start_accumulate = _issue_entry_WIRE_117_start_accumulate; // @[Mux.scala:30:73] wire _issue_entry_WIRE_129_read_full_acc_row; // @[Mux.scala:30:73] assign _issue_entry_WIRE_116_bits_start_read_full_acc_row = _issue_entry_WIRE_117_start_read_full_acc_row; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_129_norm_cmd; // @[Mux.scala:30:73] assign _issue_entry_WIRE_116_bits_start_norm_cmd = _issue_entry_WIRE_117_start_norm_cmd; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_129_garbage; // @[Mux.scala:30:73] assign _issue_entry_WIRE_116_bits_start_garbage = _issue_entry_WIRE_117_start_garbage; // @[Mux.scala:30:73] wire _issue_entry_WIRE_129_garbage_bit; // @[Mux.scala:30:73] assign _issue_entry_WIRE_116_bits_start_garbage_bit = _issue_entry_WIRE_117_start_garbage_bit; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_129_data; // @[Mux.scala:30:73] assign _issue_entry_WIRE_116_bits_start_data = _issue_entry_WIRE_117_start_data; // @[Mux.scala:30:73] wire _issue_entry_WIRE_119_is_acc_addr; // @[Mux.scala:30:73] assign _issue_entry_WIRE_116_bits_end_is_acc_addr = _issue_entry_WIRE_117_end_is_acc_addr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_119_accumulate; // @[Mux.scala:30:73] assign _issue_entry_WIRE_116_bits_end_accumulate = _issue_entry_WIRE_117_end_accumulate; // @[Mux.scala:30:73] wire _issue_entry_WIRE_119_read_full_acc_row; // @[Mux.scala:30:73] assign _issue_entry_WIRE_116_bits_end_read_full_acc_row = _issue_entry_WIRE_117_end_read_full_acc_row; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_119_norm_cmd; // @[Mux.scala:30:73] assign _issue_entry_WIRE_116_bits_end_norm_cmd = _issue_entry_WIRE_117_end_norm_cmd; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_119_garbage; // @[Mux.scala:30:73] assign _issue_entry_WIRE_116_bits_end_garbage = _issue_entry_WIRE_117_end_garbage; // @[Mux.scala:30:73] wire _issue_entry_WIRE_119_garbage_bit; // @[Mux.scala:30:73] assign _issue_entry_WIRE_116_bits_end_garbage_bit = _issue_entry_WIRE_117_end_garbage_bit; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_119_data; // @[Mux.scala:30:73] assign _issue_entry_WIRE_116_bits_end_data = _issue_entry_WIRE_117_end_data; // @[Mux.scala:30:73] wire _issue_entry_WIRE_118; // @[Mux.scala:30:73] assign _issue_entry_WIRE_116_bits_wraps_around = _issue_entry_WIRE_117_wraps_around; // @[Mux.scala:30:73] wire _issue_entry_T_1501 = issue_sel_0 & entries_ld_0_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30] wire _issue_entry_T_1502 = issue_sel_1 & entries_ld_1_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30] wire _issue_entry_T_1503 = issue_sel_2 & entries_ld_2_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30] wire _issue_entry_T_1504 = issue_sel_3 & entries_ld_3_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30] wire _issue_entry_T_1505 = issue_sel_4 & entries_ld_4_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30] wire _issue_entry_T_1506 = issue_sel_5 & entries_ld_5_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30] wire _issue_entry_T_1507 = issue_sel_6 & entries_ld_6_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30] wire _issue_entry_T_1508 = issue_sel_7 & entries_ld_7_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30] wire _issue_entry_T_1509 = _issue_entry_T_1501 | _issue_entry_T_1502; // @[Mux.scala:30:73] wire _issue_entry_T_1510 = _issue_entry_T_1509 | _issue_entry_T_1503; // @[Mux.scala:30:73] wire _issue_entry_T_1511 = _issue_entry_T_1510 | _issue_entry_T_1504; // @[Mux.scala:30:73] wire _issue_entry_T_1512 = _issue_entry_T_1511 | _issue_entry_T_1505; // @[Mux.scala:30:73] wire _issue_entry_T_1513 = _issue_entry_T_1512 | _issue_entry_T_1506; // @[Mux.scala:30:73] wire _issue_entry_T_1514 = _issue_entry_T_1513 | _issue_entry_T_1507; // @[Mux.scala:30:73] wire _issue_entry_T_1515 = _issue_entry_T_1514 | _issue_entry_T_1508; // @[Mux.scala:30:73] assign _issue_entry_WIRE_118 = _issue_entry_T_1515; // @[Mux.scala:30:73] assign _issue_entry_WIRE_117_wraps_around = _issue_entry_WIRE_118; // @[Mux.scala:30:73] wire _issue_entry_WIRE_128; // @[Mux.scala:30:73] assign _issue_entry_WIRE_117_end_is_acc_addr = _issue_entry_WIRE_119_is_acc_addr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_127; // @[Mux.scala:30:73] assign _issue_entry_WIRE_117_end_accumulate = _issue_entry_WIRE_119_accumulate; // @[Mux.scala:30:73] wire _issue_entry_WIRE_126; // @[Mux.scala:30:73] assign _issue_entry_WIRE_117_end_read_full_acc_row = _issue_entry_WIRE_119_read_full_acc_row; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_123; // @[Mux.scala:30:73] assign _issue_entry_WIRE_117_end_norm_cmd = _issue_entry_WIRE_119_norm_cmd; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_122; // @[Mux.scala:30:73] assign _issue_entry_WIRE_117_end_garbage = _issue_entry_WIRE_119_garbage; // @[Mux.scala:30:73] wire _issue_entry_WIRE_121; // @[Mux.scala:30:73] assign _issue_entry_WIRE_117_end_garbage_bit = _issue_entry_WIRE_119_garbage_bit; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_120; // @[Mux.scala:30:73] assign _issue_entry_WIRE_117_end_data = _issue_entry_WIRE_119_data; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_1516 = issue_sel_0 ? entries_ld_0_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_1517 = issue_sel_1 ? entries_ld_1_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_1518 = issue_sel_2 ? entries_ld_2_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_1519 = issue_sel_3 ? entries_ld_3_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_1520 = issue_sel_4 ? entries_ld_4_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_1521 = issue_sel_5 ? entries_ld_5_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_1522 = issue_sel_6 ? entries_ld_6_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_1523 = issue_sel_7 ? entries_ld_7_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_1524 = _issue_entry_T_1516 | _issue_entry_T_1517; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_1525 = _issue_entry_T_1524 | _issue_entry_T_1518; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_1526 = _issue_entry_T_1525 | _issue_entry_T_1519; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_1527 = _issue_entry_T_1526 | _issue_entry_T_1520; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_1528 = _issue_entry_T_1527 | _issue_entry_T_1521; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_1529 = _issue_entry_T_1528 | _issue_entry_T_1522; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_1530 = _issue_entry_T_1529 | _issue_entry_T_1523; // @[Mux.scala:30:73] assign _issue_entry_WIRE_120 = _issue_entry_T_1530; // @[Mux.scala:30:73] assign _issue_entry_WIRE_119_data = _issue_entry_WIRE_120; // @[Mux.scala:30:73] wire _issue_entry_T_1531 = issue_sel_0 & entries_ld_0_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_1532 = issue_sel_1 & entries_ld_1_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_1533 = issue_sel_2 & entries_ld_2_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_1534 = issue_sel_3 & entries_ld_3_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_1535 = issue_sel_4 & entries_ld_4_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_1536 = issue_sel_5 & entries_ld_5_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_1537 = issue_sel_6 & entries_ld_6_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_1538 = issue_sel_7 & entries_ld_7_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_1539 = _issue_entry_T_1531 | _issue_entry_T_1532; // @[Mux.scala:30:73] wire _issue_entry_T_1540 = _issue_entry_T_1539 | _issue_entry_T_1533; // @[Mux.scala:30:73] wire _issue_entry_T_1541 = _issue_entry_T_1540 | _issue_entry_T_1534; // @[Mux.scala:30:73] wire _issue_entry_T_1542 = _issue_entry_T_1541 | _issue_entry_T_1535; // @[Mux.scala:30:73] wire _issue_entry_T_1543 = _issue_entry_T_1542 | _issue_entry_T_1536; // @[Mux.scala:30:73] wire _issue_entry_T_1544 = _issue_entry_T_1543 | _issue_entry_T_1537; // @[Mux.scala:30:73] wire _issue_entry_T_1545 = _issue_entry_T_1544 | _issue_entry_T_1538; // @[Mux.scala:30:73] assign _issue_entry_WIRE_121 = _issue_entry_T_1545; // @[Mux.scala:30:73] assign _issue_entry_WIRE_119_garbage_bit = _issue_entry_WIRE_121; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_1546 = issue_sel_0 ? entries_ld_0_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_1547 = issue_sel_1 ? entries_ld_1_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_1548 = issue_sel_2 ? entries_ld_2_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_1549 = issue_sel_3 ? entries_ld_3_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_1550 = issue_sel_4 ? entries_ld_4_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_1551 = issue_sel_5 ? entries_ld_5_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_1552 = issue_sel_6 ? entries_ld_6_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_1553 = issue_sel_7 ? entries_ld_7_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_1554 = _issue_entry_T_1546 | _issue_entry_T_1547; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_1555 = _issue_entry_T_1554 | _issue_entry_T_1548; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_1556 = _issue_entry_T_1555 | _issue_entry_T_1549; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_1557 = _issue_entry_T_1556 | _issue_entry_T_1550; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_1558 = _issue_entry_T_1557 | _issue_entry_T_1551; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_1559 = _issue_entry_T_1558 | _issue_entry_T_1552; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_1560 = _issue_entry_T_1559 | _issue_entry_T_1553; // @[Mux.scala:30:73] assign _issue_entry_WIRE_122 = _issue_entry_T_1560; // @[Mux.scala:30:73] assign _issue_entry_WIRE_119_garbage = _issue_entry_WIRE_122; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1562 = issue_sel_0 ? _issue_entry_T_1561 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_1564 = issue_sel_1 ? _issue_entry_T_1563 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_1566 = issue_sel_2 ? _issue_entry_T_1565 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_1568 = issue_sel_3 ? _issue_entry_T_1567 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_1570 = issue_sel_4 ? _issue_entry_T_1569 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_1572 = issue_sel_5 ? _issue_entry_T_1571 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_1574 = issue_sel_6 ? _issue_entry_T_1573 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_1576 = issue_sel_7 ? _issue_entry_T_1575 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_1577 = _issue_entry_T_1562 | _issue_entry_T_1564; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1578 = _issue_entry_T_1577 | _issue_entry_T_1566; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1579 = _issue_entry_T_1578 | _issue_entry_T_1568; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1580 = _issue_entry_T_1579 | _issue_entry_T_1570; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1581 = _issue_entry_T_1580 | _issue_entry_T_1572; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1582 = _issue_entry_T_1581 | _issue_entry_T_1574; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1583 = _issue_entry_T_1582 | _issue_entry_T_1576; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_124 = _issue_entry_T_1583; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_125; // @[Mux.scala:30:73] assign _issue_entry_WIRE_119_norm_cmd = _issue_entry_WIRE_123; // @[Mux.scala:30:73] assign _issue_entry_WIRE_125 = _issue_entry_WIRE_124; // @[Mux.scala:30:73] assign _issue_entry_WIRE_123 = _issue_entry_WIRE_125; // @[Mux.scala:30:73] wire _issue_entry_T_1584 = issue_sel_0 & entries_ld_0_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_1585 = issue_sel_1 & entries_ld_1_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_1586 = issue_sel_2 & entries_ld_2_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_1587 = issue_sel_3 & entries_ld_3_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_1588 = issue_sel_4 & entries_ld_4_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_1589 = issue_sel_5 & entries_ld_5_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_1590 = issue_sel_6 & entries_ld_6_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_1591 = issue_sel_7 & entries_ld_7_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_1592 = _issue_entry_T_1584 | _issue_entry_T_1585; // @[Mux.scala:30:73] wire _issue_entry_T_1593 = _issue_entry_T_1592 | _issue_entry_T_1586; // @[Mux.scala:30:73] wire _issue_entry_T_1594 = _issue_entry_T_1593 | _issue_entry_T_1587; // @[Mux.scala:30:73] wire _issue_entry_T_1595 = _issue_entry_T_1594 | _issue_entry_T_1588; // @[Mux.scala:30:73] wire _issue_entry_T_1596 = _issue_entry_T_1595 | _issue_entry_T_1589; // @[Mux.scala:30:73] wire _issue_entry_T_1597 = _issue_entry_T_1596 | _issue_entry_T_1590; // @[Mux.scala:30:73] wire _issue_entry_T_1598 = _issue_entry_T_1597 | _issue_entry_T_1591; // @[Mux.scala:30:73] assign _issue_entry_WIRE_126 = _issue_entry_T_1598; // @[Mux.scala:30:73] assign _issue_entry_WIRE_119_read_full_acc_row = _issue_entry_WIRE_126; // @[Mux.scala:30:73] wire _issue_entry_T_1599 = issue_sel_0 & entries_ld_0_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_1600 = issue_sel_1 & entries_ld_1_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_1601 = issue_sel_2 & entries_ld_2_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_1602 = issue_sel_3 & entries_ld_3_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_1603 = issue_sel_4 & entries_ld_4_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_1604 = issue_sel_5 & entries_ld_5_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_1605 = issue_sel_6 & entries_ld_6_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_1606 = issue_sel_7 & entries_ld_7_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_1607 = _issue_entry_T_1599 | _issue_entry_T_1600; // @[Mux.scala:30:73] wire _issue_entry_T_1608 = _issue_entry_T_1607 | _issue_entry_T_1601; // @[Mux.scala:30:73] wire _issue_entry_T_1609 = _issue_entry_T_1608 | _issue_entry_T_1602; // @[Mux.scala:30:73] wire _issue_entry_T_1610 = _issue_entry_T_1609 | _issue_entry_T_1603; // @[Mux.scala:30:73] wire _issue_entry_T_1611 = _issue_entry_T_1610 | _issue_entry_T_1604; // @[Mux.scala:30:73] wire _issue_entry_T_1612 = _issue_entry_T_1611 | _issue_entry_T_1605; // @[Mux.scala:30:73] wire _issue_entry_T_1613 = _issue_entry_T_1612 | _issue_entry_T_1606; // @[Mux.scala:30:73] assign _issue_entry_WIRE_127 = _issue_entry_T_1613; // @[Mux.scala:30:73] assign _issue_entry_WIRE_119_accumulate = _issue_entry_WIRE_127; // @[Mux.scala:30:73] wire _issue_entry_T_1614 = issue_sel_0 & entries_ld_0_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_1615 = issue_sel_1 & entries_ld_1_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_1616 = issue_sel_2 & entries_ld_2_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_1617 = issue_sel_3 & entries_ld_3_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_1618 = issue_sel_4 & entries_ld_4_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_1619 = issue_sel_5 & entries_ld_5_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_1620 = issue_sel_6 & entries_ld_6_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_1621 = issue_sel_7 & entries_ld_7_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_1622 = _issue_entry_T_1614 | _issue_entry_T_1615; // @[Mux.scala:30:73] wire _issue_entry_T_1623 = _issue_entry_T_1622 | _issue_entry_T_1616; // @[Mux.scala:30:73] wire _issue_entry_T_1624 = _issue_entry_T_1623 | _issue_entry_T_1617; // @[Mux.scala:30:73] wire _issue_entry_T_1625 = _issue_entry_T_1624 | _issue_entry_T_1618; // @[Mux.scala:30:73] wire _issue_entry_T_1626 = _issue_entry_T_1625 | _issue_entry_T_1619; // @[Mux.scala:30:73] wire _issue_entry_T_1627 = _issue_entry_T_1626 | _issue_entry_T_1620; // @[Mux.scala:30:73] wire _issue_entry_T_1628 = _issue_entry_T_1627 | _issue_entry_T_1621; // @[Mux.scala:30:73] assign _issue_entry_WIRE_128 = _issue_entry_T_1628; // @[Mux.scala:30:73] assign _issue_entry_WIRE_119_is_acc_addr = _issue_entry_WIRE_128; // @[Mux.scala:30:73] wire _issue_entry_WIRE_138; // @[Mux.scala:30:73] assign _issue_entry_WIRE_117_start_is_acc_addr = _issue_entry_WIRE_129_is_acc_addr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_137; // @[Mux.scala:30:73] assign _issue_entry_WIRE_117_start_accumulate = _issue_entry_WIRE_129_accumulate; // @[Mux.scala:30:73] wire _issue_entry_WIRE_136; // @[Mux.scala:30:73] assign _issue_entry_WIRE_117_start_read_full_acc_row = _issue_entry_WIRE_129_read_full_acc_row; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_133; // @[Mux.scala:30:73] assign _issue_entry_WIRE_117_start_norm_cmd = _issue_entry_WIRE_129_norm_cmd; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_132; // @[Mux.scala:30:73] assign _issue_entry_WIRE_117_start_garbage = _issue_entry_WIRE_129_garbage; // @[Mux.scala:30:73] wire _issue_entry_WIRE_131; // @[Mux.scala:30:73] assign _issue_entry_WIRE_117_start_garbage_bit = _issue_entry_WIRE_129_garbage_bit; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_130; // @[Mux.scala:30:73] assign _issue_entry_WIRE_117_start_data = _issue_entry_WIRE_129_data; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_1629 = issue_sel_0 ? entries_ld_0_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_1630 = issue_sel_1 ? entries_ld_1_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_1631 = issue_sel_2 ? entries_ld_2_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_1632 = issue_sel_3 ? entries_ld_3_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_1633 = issue_sel_4 ? entries_ld_4_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_1634 = issue_sel_5 ? entries_ld_5_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_1635 = issue_sel_6 ? entries_ld_6_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_1636 = issue_sel_7 ? entries_ld_7_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_1637 = _issue_entry_T_1629 | _issue_entry_T_1630; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_1638 = _issue_entry_T_1637 | _issue_entry_T_1631; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_1639 = _issue_entry_T_1638 | _issue_entry_T_1632; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_1640 = _issue_entry_T_1639 | _issue_entry_T_1633; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_1641 = _issue_entry_T_1640 | _issue_entry_T_1634; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_1642 = _issue_entry_T_1641 | _issue_entry_T_1635; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_1643 = _issue_entry_T_1642 | _issue_entry_T_1636; // @[Mux.scala:30:73] assign _issue_entry_WIRE_130 = _issue_entry_T_1643; // @[Mux.scala:30:73] assign _issue_entry_WIRE_129_data = _issue_entry_WIRE_130; // @[Mux.scala:30:73] wire _issue_entry_T_1644 = issue_sel_0 & entries_ld_0_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_1645 = issue_sel_1 & entries_ld_1_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_1646 = issue_sel_2 & entries_ld_2_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_1647 = issue_sel_3 & entries_ld_3_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_1648 = issue_sel_4 & entries_ld_4_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_1649 = issue_sel_5 & entries_ld_5_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_1650 = issue_sel_6 & entries_ld_6_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_1651 = issue_sel_7 & entries_ld_7_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_1652 = _issue_entry_T_1644 | _issue_entry_T_1645; // @[Mux.scala:30:73] wire _issue_entry_T_1653 = _issue_entry_T_1652 | _issue_entry_T_1646; // @[Mux.scala:30:73] wire _issue_entry_T_1654 = _issue_entry_T_1653 | _issue_entry_T_1647; // @[Mux.scala:30:73] wire _issue_entry_T_1655 = _issue_entry_T_1654 | _issue_entry_T_1648; // @[Mux.scala:30:73] wire _issue_entry_T_1656 = _issue_entry_T_1655 | _issue_entry_T_1649; // @[Mux.scala:30:73] wire _issue_entry_T_1657 = _issue_entry_T_1656 | _issue_entry_T_1650; // @[Mux.scala:30:73] wire _issue_entry_T_1658 = _issue_entry_T_1657 | _issue_entry_T_1651; // @[Mux.scala:30:73] assign _issue_entry_WIRE_131 = _issue_entry_T_1658; // @[Mux.scala:30:73] assign _issue_entry_WIRE_129_garbage_bit = _issue_entry_WIRE_131; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_1659 = issue_sel_0 ? entries_ld_0_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_1660 = issue_sel_1 ? entries_ld_1_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_1661 = issue_sel_2 ? entries_ld_2_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_1662 = issue_sel_3 ? entries_ld_3_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_1663 = issue_sel_4 ? entries_ld_4_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_1664 = issue_sel_5 ? entries_ld_5_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_1665 = issue_sel_6 ? entries_ld_6_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_1666 = issue_sel_7 ? entries_ld_7_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_1667 = _issue_entry_T_1659 | _issue_entry_T_1660; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_1668 = _issue_entry_T_1667 | _issue_entry_T_1661; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_1669 = _issue_entry_T_1668 | _issue_entry_T_1662; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_1670 = _issue_entry_T_1669 | _issue_entry_T_1663; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_1671 = _issue_entry_T_1670 | _issue_entry_T_1664; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_1672 = _issue_entry_T_1671 | _issue_entry_T_1665; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_1673 = _issue_entry_T_1672 | _issue_entry_T_1666; // @[Mux.scala:30:73] assign _issue_entry_WIRE_132 = _issue_entry_T_1673; // @[Mux.scala:30:73] assign _issue_entry_WIRE_129_garbage = _issue_entry_WIRE_132; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1675 = issue_sel_0 ? _issue_entry_T_1674 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_1677 = issue_sel_1 ? _issue_entry_T_1676 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_1679 = issue_sel_2 ? _issue_entry_T_1678 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_1681 = issue_sel_3 ? _issue_entry_T_1680 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_1683 = issue_sel_4 ? _issue_entry_T_1682 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_1685 = issue_sel_5 ? _issue_entry_T_1684 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_1687 = issue_sel_6 ? _issue_entry_T_1686 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_1689 = issue_sel_7 ? _issue_entry_T_1688 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_1690 = _issue_entry_T_1675 | _issue_entry_T_1677; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1691 = _issue_entry_T_1690 | _issue_entry_T_1679; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1692 = _issue_entry_T_1691 | _issue_entry_T_1681; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1693 = _issue_entry_T_1692 | _issue_entry_T_1683; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1694 = _issue_entry_T_1693 | _issue_entry_T_1685; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1695 = _issue_entry_T_1694 | _issue_entry_T_1687; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_1696 = _issue_entry_T_1695 | _issue_entry_T_1689; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_134 = _issue_entry_T_1696; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_135; // @[Mux.scala:30:73] assign _issue_entry_WIRE_129_norm_cmd = _issue_entry_WIRE_133; // @[Mux.scala:30:73] assign _issue_entry_WIRE_135 = _issue_entry_WIRE_134; // @[Mux.scala:30:73] assign _issue_entry_WIRE_133 = _issue_entry_WIRE_135; // @[Mux.scala:30:73] wire _issue_entry_T_1697 = issue_sel_0 & entries_ld_0_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_1698 = issue_sel_1 & entries_ld_1_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_1699 = issue_sel_2 & entries_ld_2_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_1700 = issue_sel_3 & entries_ld_3_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_1701 = issue_sel_4 & entries_ld_4_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_1702 = issue_sel_5 & entries_ld_5_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_1703 = issue_sel_6 & entries_ld_6_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_1704 = issue_sel_7 & entries_ld_7_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_1705 = _issue_entry_T_1697 | _issue_entry_T_1698; // @[Mux.scala:30:73] wire _issue_entry_T_1706 = _issue_entry_T_1705 | _issue_entry_T_1699; // @[Mux.scala:30:73] wire _issue_entry_T_1707 = _issue_entry_T_1706 | _issue_entry_T_1700; // @[Mux.scala:30:73] wire _issue_entry_T_1708 = _issue_entry_T_1707 | _issue_entry_T_1701; // @[Mux.scala:30:73] wire _issue_entry_T_1709 = _issue_entry_T_1708 | _issue_entry_T_1702; // @[Mux.scala:30:73] wire _issue_entry_T_1710 = _issue_entry_T_1709 | _issue_entry_T_1703; // @[Mux.scala:30:73] wire _issue_entry_T_1711 = _issue_entry_T_1710 | _issue_entry_T_1704; // @[Mux.scala:30:73] assign _issue_entry_WIRE_136 = _issue_entry_T_1711; // @[Mux.scala:30:73] assign _issue_entry_WIRE_129_read_full_acc_row = _issue_entry_WIRE_136; // @[Mux.scala:30:73] wire _issue_entry_T_1712 = issue_sel_0 & entries_ld_0_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_1713 = issue_sel_1 & entries_ld_1_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_1714 = issue_sel_2 & entries_ld_2_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_1715 = issue_sel_3 & entries_ld_3_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_1716 = issue_sel_4 & entries_ld_4_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_1717 = issue_sel_5 & entries_ld_5_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_1718 = issue_sel_6 & entries_ld_6_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_1719 = issue_sel_7 & entries_ld_7_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_1720 = _issue_entry_T_1712 | _issue_entry_T_1713; // @[Mux.scala:30:73] wire _issue_entry_T_1721 = _issue_entry_T_1720 | _issue_entry_T_1714; // @[Mux.scala:30:73] wire _issue_entry_T_1722 = _issue_entry_T_1721 | _issue_entry_T_1715; // @[Mux.scala:30:73] wire _issue_entry_T_1723 = _issue_entry_T_1722 | _issue_entry_T_1716; // @[Mux.scala:30:73] wire _issue_entry_T_1724 = _issue_entry_T_1723 | _issue_entry_T_1717; // @[Mux.scala:30:73] wire _issue_entry_T_1725 = _issue_entry_T_1724 | _issue_entry_T_1718; // @[Mux.scala:30:73] wire _issue_entry_T_1726 = _issue_entry_T_1725 | _issue_entry_T_1719; // @[Mux.scala:30:73] assign _issue_entry_WIRE_137 = _issue_entry_T_1726; // @[Mux.scala:30:73] assign _issue_entry_WIRE_129_accumulate = _issue_entry_WIRE_137; // @[Mux.scala:30:73] wire _issue_entry_T_1727 = issue_sel_0 & entries_ld_0_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_1728 = issue_sel_1 & entries_ld_1_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_1729 = issue_sel_2 & entries_ld_2_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_1730 = issue_sel_3 & entries_ld_3_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_1731 = issue_sel_4 & entries_ld_4_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_1732 = issue_sel_5 & entries_ld_5_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_1733 = issue_sel_6 & entries_ld_6_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_1734 = issue_sel_7 & entries_ld_7_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_1735 = _issue_entry_T_1727 | _issue_entry_T_1728; // @[Mux.scala:30:73] wire _issue_entry_T_1736 = _issue_entry_T_1735 | _issue_entry_T_1729; // @[Mux.scala:30:73] wire _issue_entry_T_1737 = _issue_entry_T_1736 | _issue_entry_T_1730; // @[Mux.scala:30:73] wire _issue_entry_T_1738 = _issue_entry_T_1737 | _issue_entry_T_1731; // @[Mux.scala:30:73] wire _issue_entry_T_1739 = _issue_entry_T_1738 | _issue_entry_T_1732; // @[Mux.scala:30:73] wire _issue_entry_T_1740 = _issue_entry_T_1739 | _issue_entry_T_1733; // @[Mux.scala:30:73] wire _issue_entry_T_1741 = _issue_entry_T_1740 | _issue_entry_T_1734; // @[Mux.scala:30:73] assign _issue_entry_WIRE_138 = _issue_entry_T_1741; // @[Mux.scala:30:73] assign _issue_entry_WIRE_129_is_acc_addr = _issue_entry_WIRE_138; // @[Mux.scala:30:73] wire _issue_entry_T_1742 = issue_sel_0 & entries_ld_0_bits_opa_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_1743 = issue_sel_1 & entries_ld_1_bits_opa_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_1744 = issue_sel_2 & entries_ld_2_bits_opa_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_1745 = issue_sel_3 & entries_ld_3_bits_opa_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_1746 = issue_sel_4 & entries_ld_4_bits_opa_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_1747 = issue_sel_5 & entries_ld_5_bits_opa_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_1748 = issue_sel_6 & entries_ld_6_bits_opa_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_1749 = issue_sel_7 & entries_ld_7_bits_opa_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_1750 = _issue_entry_T_1742 | _issue_entry_T_1743; // @[Mux.scala:30:73] wire _issue_entry_T_1751 = _issue_entry_T_1750 | _issue_entry_T_1744; // @[Mux.scala:30:73] wire _issue_entry_T_1752 = _issue_entry_T_1751 | _issue_entry_T_1745; // @[Mux.scala:30:73] wire _issue_entry_T_1753 = _issue_entry_T_1752 | _issue_entry_T_1746; // @[Mux.scala:30:73] wire _issue_entry_T_1754 = _issue_entry_T_1753 | _issue_entry_T_1747; // @[Mux.scala:30:73] wire _issue_entry_T_1755 = _issue_entry_T_1754 | _issue_entry_T_1748; // @[Mux.scala:30:73] wire _issue_entry_T_1756 = _issue_entry_T_1755 | _issue_entry_T_1749; // @[Mux.scala:30:73] assign _issue_entry_WIRE_139 = _issue_entry_T_1756; // @[Mux.scala:30:73] assign _issue_entry_WIRE_116_valid = _issue_entry_WIRE_139; // @[Mux.scala:30:73] wire _issue_entry_T_1757 = issue_sel_0 & entries_ld_0_bits_is_config; // @[OneHot.scala:83:30] wire _issue_entry_T_1758 = issue_sel_1 & entries_ld_1_bits_is_config; // @[OneHot.scala:83:30] wire _issue_entry_T_1759 = issue_sel_2 & entries_ld_2_bits_is_config; // @[OneHot.scala:83:30] wire _issue_entry_T_1760 = issue_sel_3 & entries_ld_3_bits_is_config; // @[OneHot.scala:83:30] wire _issue_entry_T_1761 = issue_sel_4 & entries_ld_4_bits_is_config; // @[OneHot.scala:83:30] wire _issue_entry_T_1762 = issue_sel_5 & entries_ld_5_bits_is_config; // @[OneHot.scala:83:30] wire _issue_entry_T_1763 = issue_sel_6 & entries_ld_6_bits_is_config; // @[OneHot.scala:83:30] wire _issue_entry_T_1764 = issue_sel_7 & entries_ld_7_bits_is_config; // @[OneHot.scala:83:30] wire _issue_entry_T_1765 = _issue_entry_T_1757 | _issue_entry_T_1758; // @[Mux.scala:30:73] wire _issue_entry_T_1766 = _issue_entry_T_1765 | _issue_entry_T_1759; // @[Mux.scala:30:73] wire _issue_entry_T_1767 = _issue_entry_T_1766 | _issue_entry_T_1760; // @[Mux.scala:30:73] wire _issue_entry_T_1768 = _issue_entry_T_1767 | _issue_entry_T_1761; // @[Mux.scala:30:73] wire _issue_entry_T_1769 = _issue_entry_T_1768 | _issue_entry_T_1762; // @[Mux.scala:30:73] wire _issue_entry_T_1770 = _issue_entry_T_1769 | _issue_entry_T_1763; // @[Mux.scala:30:73] wire _issue_entry_T_1771 = _issue_entry_T_1770 | _issue_entry_T_1764; // @[Mux.scala:30:73] assign _issue_entry_WIRE_140 = _issue_entry_T_1771; // @[Mux.scala:30:73] assign _issue_entry_WIRE_is_config = _issue_entry_WIRE_140; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_1772 = issue_sel_0 ? entries_ld_0_bits_q : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_1773 = issue_sel_1 ? entries_ld_1_bits_q : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_1774 = issue_sel_2 ? entries_ld_2_bits_q : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_1775 = issue_sel_3 ? entries_ld_3_bits_q : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_1776 = issue_sel_4 ? entries_ld_4_bits_q : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_1777 = issue_sel_5 ? entries_ld_5_bits_q : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_1778 = issue_sel_6 ? entries_ld_6_bits_q : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_1779 = issue_sel_7 ? entries_ld_7_bits_q : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_1780 = _issue_entry_T_1772 | _issue_entry_T_1773; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_1781 = _issue_entry_T_1780 | _issue_entry_T_1774; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_1782 = _issue_entry_T_1781 | _issue_entry_T_1775; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_1783 = _issue_entry_T_1782 | _issue_entry_T_1776; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_1784 = _issue_entry_T_1783 | _issue_entry_T_1777; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_1785 = _issue_entry_T_1784 | _issue_entry_T_1778; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_1786 = _issue_entry_T_1785 | _issue_entry_T_1779; // @[Mux.scala:30:73] assign _issue_entry_WIRE_141 = _issue_entry_T_1786; // @[Mux.scala:30:73] assign _issue_entry_WIRE_q = _issue_entry_WIRE_141; // @[Mux.scala:30:73] wire _issue_entry_T_1787 = issue_sel_0 & entries_ld_0_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_1788 = issue_sel_1 & entries_ld_1_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_1789 = issue_sel_2 & entries_ld_2_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_1790 = issue_sel_3 & entries_ld_3_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_1791 = issue_sel_4 & entries_ld_4_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_1792 = issue_sel_5 & entries_ld_5_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_1793 = issue_sel_6 & entries_ld_6_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_1794 = issue_sel_7 & entries_ld_7_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_1795 = _issue_entry_T_1787 | _issue_entry_T_1788; // @[Mux.scala:30:73] wire _issue_entry_T_1796 = _issue_entry_T_1795 | _issue_entry_T_1789; // @[Mux.scala:30:73] wire _issue_entry_T_1797 = _issue_entry_T_1796 | _issue_entry_T_1790; // @[Mux.scala:30:73] wire _issue_entry_T_1798 = _issue_entry_T_1797 | _issue_entry_T_1791; // @[Mux.scala:30:73] wire _issue_entry_T_1799 = _issue_entry_T_1798 | _issue_entry_T_1792; // @[Mux.scala:30:73] wire _issue_entry_T_1800 = _issue_entry_T_1799 | _issue_entry_T_1793; // @[Mux.scala:30:73] wire _issue_entry_T_1801 = _issue_entry_T_1800 | _issue_entry_T_1794; // @[Mux.scala:30:73] assign _issue_entry_WIRE_142 = _issue_entry_T_1801; // @[Mux.scala:30:73] assign issue_entry_valid = _issue_entry_WIRE_142; // @[Mux.scala:30:73] wire _io_issue_ld_valid_T = issue_valids_0 | issue_valids_1; // @[ReservationStation.scala:395:72, :404:38] wire _io_issue_ld_valid_T_1 = _io_issue_ld_valid_T | issue_valids_2; // @[ReservationStation.scala:395:72, :404:38] wire _io_issue_ld_valid_T_2 = _io_issue_ld_valid_T_1 | issue_valids_3; // @[ReservationStation.scala:395:72, :404:38] wire _io_issue_ld_valid_T_3 = _io_issue_ld_valid_T_2 | issue_valids_4; // @[ReservationStation.scala:395:72, :404:38] wire _io_issue_ld_valid_T_4 = _io_issue_ld_valid_T_3 | issue_valids_5; // @[ReservationStation.scala:395:72, :404:38] wire _io_issue_ld_valid_T_5 = _io_issue_ld_valid_T_4 | issue_valids_6; // @[ReservationStation.scala:395:72, :404:38] assign _io_issue_ld_valid_T_6 = _io_issue_ld_valid_T_5 | issue_valids_7; // @[ReservationStation.scala:395:72, :404:38] assign io_issue_ld_valid_0 = _io_issue_ld_valid_T_6; // @[ReservationStation.scala:26:7, :404:38] wire _T_5013 = io_issue_ld_valid_0 & io_issue_ld_ready_0; // @[ReservationStation.scala:22:20, :26:7] wire _entries_ld_0_valid_T = ~entries_ld_0_bits_complete_on_issue; // @[ReservationStation.scala:117:23, :417:22] wire _entries_ld_1_valid_T = ~entries_ld_1_bits_complete_on_issue; // @[ReservationStation.scala:117:23, :417:22] wire _entries_ld_2_valid_T = ~entries_ld_2_bits_complete_on_issue; // @[ReservationStation.scala:117:23, :417:22] wire _entries_ld_3_valid_T = ~entries_ld_3_bits_complete_on_issue; // @[ReservationStation.scala:117:23, :417:22] wire _entries_ld_4_valid_T = ~entries_ld_4_bits_complete_on_issue; // @[ReservationStation.scala:117:23, :417:22] wire _entries_ld_5_valid_T = ~entries_ld_5_bits_complete_on_issue; // @[ReservationStation.scala:117:23, :417:22] wire _entries_ld_6_valid_T = ~entries_ld_6_bits_complete_on_issue; // @[ReservationStation.scala:117:23, :417:22] wire _entries_ld_7_valid_T = ~entries_ld_7_bits_complete_on_issue; // @[ReservationStation.scala:117:23, :417:22] wire [7:0] _GEN_89 = {{entries_ld_7_bits_complete_on_issue}, {entries_ld_6_bits_complete_on_issue}, {entries_ld_5_bits_complete_on_issue}, {entries_ld_4_bits_complete_on_issue}, {entries_ld_3_bits_complete_on_issue}, {entries_ld_2_bits_complete_on_issue}, {entries_ld_1_bits_complete_on_issue}, {entries_ld_0_bits_complete_on_issue}}; // @[ReservationStation.scala:117:23, :440:71] wire [7:0] _GEN_90 = {{entries_ld_7_bits_cmd_from_conv_fsm}, {entries_ld_6_bits_cmd_from_conv_fsm}, {entries_ld_5_bits_cmd_from_conv_fsm}, {entries_ld_4_bits_cmd_from_conv_fsm}, {entries_ld_3_bits_cmd_from_conv_fsm}, {entries_ld_2_bits_cmd_from_conv_fsm}, {entries_ld_1_bits_cmd_from_conv_fsm}, {entries_ld_0_bits_cmd_from_conv_fsm}}; // @[ReservationStation.scala:117:23, :440:71] wire _GEN_91 = _GEN_89[issue_id] & _GEN_90[issue_id]; // @[OneHot.scala:32:10] wire _conv_ld_issue_completed_T; // @[ReservationStation.scala:440:71] assign _conv_ld_issue_completed_T = _GEN_91; // @[ReservationStation.scala:440:71] wire _conv_st_issue_completed_T; // @[ReservationStation.scala:441:71] assign _conv_st_issue_completed_T = _GEN_91; // @[ReservationStation.scala:440:71, :441:71] wire _conv_ex_issue_completed_T; // @[ReservationStation.scala:442:71] assign _conv_ex_issue_completed_T = _GEN_91; // @[ReservationStation.scala:440:71, :442:71] assign conv_ld_issue_completed = _T_5013 & _conv_ld_issue_completed_T; // @[ReservationStation.scala:22:20, :138:41, :413:20, :440:{24,71}] wire [7:0] _GEN_92 = {{entries_ld_7_bits_cmd_from_matmul_fsm}, {entries_ld_6_bits_cmd_from_matmul_fsm}, {entries_ld_5_bits_cmd_from_matmul_fsm}, {entries_ld_4_bits_cmd_from_matmul_fsm}, {entries_ld_3_bits_cmd_from_matmul_fsm}, {entries_ld_2_bits_cmd_from_matmul_fsm}, {entries_ld_1_bits_cmd_from_matmul_fsm}, {entries_ld_0_bits_cmd_from_matmul_fsm}}; // @[ReservationStation.scala:117:23, :444:73] wire _GEN_93 = _GEN_89[issue_id] & _GEN_92[issue_id]; // @[OneHot.scala:32:10] wire _matmul_ld_issue_completed_T; // @[ReservationStation.scala:444:73] assign _matmul_ld_issue_completed_T = _GEN_93; // @[ReservationStation.scala:444:73] wire _matmul_st_issue_completed_T; // @[ReservationStation.scala:445:73] assign _matmul_st_issue_completed_T = _GEN_93; // @[ReservationStation.scala:444:73, :445:73] wire _matmul_ex_issue_completed_T; // @[ReservationStation.scala:446:73] assign _matmul_ex_issue_completed_T = _GEN_93; // @[ReservationStation.scala:444:73, :446:73] assign matmul_ld_issue_completed = _T_5013 & _matmul_ld_issue_completed_T; // @[ReservationStation.scala:22:20, :146:43, :413:20, :444:{24,73}] wire _issue_valids_T_240 = entries_ex_0_bits_deps_ld_0 | entries_ex_0_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_241 = _issue_valids_T_240 | entries_ex_0_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_242 = _issue_valids_T_241 | entries_ex_0_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_243 = _issue_valids_T_242 | entries_ex_0_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_244 = _issue_valids_T_243 | entries_ex_0_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_245 = _issue_valids_T_244 | entries_ex_0_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_246 = _issue_valids_T_245 | entries_ex_0_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_247 = entries_ex_0_bits_deps_ex_0 | entries_ex_0_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_248 = _issue_valids_T_247 | entries_ex_0_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_249 = _issue_valids_T_248 | entries_ex_0_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_250 = _issue_valids_T_249 | entries_ex_0_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_251 = _issue_valids_T_250 | entries_ex_0_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_252 = _issue_valids_T_251 | entries_ex_0_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_253 = _issue_valids_T_252 | entries_ex_0_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_254 = _issue_valids_T_253 | entries_ex_0_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_255 = _issue_valids_T_254 | entries_ex_0_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_256 = _issue_valids_T_255 | entries_ex_0_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_257 = _issue_valids_T_256 | entries_ex_0_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_258 = _issue_valids_T_257 | entries_ex_0_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_259 = _issue_valids_T_258 | entries_ex_0_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_260 = _issue_valids_T_259 | entries_ex_0_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_261 = _issue_valids_T_260 | entries_ex_0_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_262 = _issue_valids_T_246 | _issue_valids_T_261; // @[ReservationStation.scala:107:{58,64,84}] wire _issue_valids_T_263 = entries_ex_0_bits_deps_st_0 | entries_ex_0_bits_deps_st_1; // @[ReservationStation.scala:107:110, :118:23] wire _issue_valids_T_264 = _issue_valids_T_263 | entries_ex_0_bits_deps_st_2; // @[ReservationStation.scala:107:110, :118:23] wire _issue_valids_T_265 = _issue_valids_T_264 | entries_ex_0_bits_deps_st_3; // @[ReservationStation.scala:107:110, :118:23] wire _issue_valids_T_266 = _issue_valids_T_262 | _issue_valids_T_265; // @[ReservationStation.scala:107:{64,90,110}] wire _issue_valids_T_267 = ~_issue_valids_T_266; // @[ReservationStation.scala:107:{39,90}] wire _issue_valids_T_268 = entries_ex_0_valid & _issue_valids_T_267; // @[ReservationStation.scala:107:39, :118:23, :395:54] wire _issue_valids_T_269 = ~entries_ex_0_bits_issued; // @[ReservationStation.scala:118:23, :395:75] wire issue_valids_0_1 = _issue_valids_T_268 & _issue_valids_T_269; // @[ReservationStation.scala:395:{54,72,75}] wire _issue_valids_T_270 = entries_ex_1_bits_deps_ld_0 | entries_ex_1_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_271 = _issue_valids_T_270 | entries_ex_1_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_272 = _issue_valids_T_271 | entries_ex_1_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_273 = _issue_valids_T_272 | entries_ex_1_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_274 = _issue_valids_T_273 | entries_ex_1_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_275 = _issue_valids_T_274 | entries_ex_1_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_276 = _issue_valids_T_275 | entries_ex_1_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_277 = entries_ex_1_bits_deps_ex_0 | entries_ex_1_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_278 = _issue_valids_T_277 | entries_ex_1_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_279 = _issue_valids_T_278 | entries_ex_1_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_280 = _issue_valids_T_279 | entries_ex_1_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_281 = _issue_valids_T_280 | entries_ex_1_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_282 = _issue_valids_T_281 | entries_ex_1_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_283 = _issue_valids_T_282 | entries_ex_1_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_284 = _issue_valids_T_283 | entries_ex_1_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_285 = _issue_valids_T_284 | entries_ex_1_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_286 = _issue_valids_T_285 | entries_ex_1_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_287 = _issue_valids_T_286 | entries_ex_1_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_288 = _issue_valids_T_287 | entries_ex_1_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_289 = _issue_valids_T_288 | entries_ex_1_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_290 = _issue_valids_T_289 | entries_ex_1_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_291 = _issue_valids_T_290 | entries_ex_1_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_292 = _issue_valids_T_276 | _issue_valids_T_291; // @[ReservationStation.scala:107:{58,64,84}] wire _issue_valids_T_293 = entries_ex_1_bits_deps_st_0 | entries_ex_1_bits_deps_st_1; // @[ReservationStation.scala:107:110, :118:23] wire _issue_valids_T_294 = _issue_valids_T_293 | entries_ex_1_bits_deps_st_2; // @[ReservationStation.scala:107:110, :118:23] wire _issue_valids_T_295 = _issue_valids_T_294 | entries_ex_1_bits_deps_st_3; // @[ReservationStation.scala:107:110, :118:23] wire _issue_valids_T_296 = _issue_valids_T_292 | _issue_valids_T_295; // @[ReservationStation.scala:107:{64,90,110}] wire _issue_valids_T_297 = ~_issue_valids_T_296; // @[ReservationStation.scala:107:{39,90}] wire _issue_valids_T_298 = entries_ex_1_valid & _issue_valids_T_297; // @[ReservationStation.scala:107:39, :118:23, :395:54] wire _issue_valids_T_299 = ~entries_ex_1_bits_issued; // @[ReservationStation.scala:118:23, :395:75] wire issue_valids_1_1 = _issue_valids_T_298 & _issue_valids_T_299; // @[ReservationStation.scala:395:{54,72,75}] wire _issue_valids_T_300 = entries_ex_2_bits_deps_ld_0 | entries_ex_2_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_301 = _issue_valids_T_300 | entries_ex_2_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_302 = _issue_valids_T_301 | entries_ex_2_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_303 = _issue_valids_T_302 | entries_ex_2_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_304 = _issue_valids_T_303 | entries_ex_2_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_305 = _issue_valids_T_304 | entries_ex_2_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_306 = _issue_valids_T_305 | entries_ex_2_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_307 = entries_ex_2_bits_deps_ex_0 | entries_ex_2_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_308 = _issue_valids_T_307 | entries_ex_2_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_309 = _issue_valids_T_308 | entries_ex_2_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_310 = _issue_valids_T_309 | entries_ex_2_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_311 = _issue_valids_T_310 | entries_ex_2_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_312 = _issue_valids_T_311 | entries_ex_2_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_313 = _issue_valids_T_312 | entries_ex_2_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_314 = _issue_valids_T_313 | entries_ex_2_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_315 = _issue_valids_T_314 | entries_ex_2_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_316 = _issue_valids_T_315 | entries_ex_2_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_317 = _issue_valids_T_316 | entries_ex_2_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_318 = _issue_valids_T_317 | entries_ex_2_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_319 = _issue_valids_T_318 | entries_ex_2_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_320 = _issue_valids_T_319 | entries_ex_2_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_321 = _issue_valids_T_320 | entries_ex_2_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_322 = _issue_valids_T_306 | _issue_valids_T_321; // @[ReservationStation.scala:107:{58,64,84}] wire _issue_valids_T_323 = entries_ex_2_bits_deps_st_0 | entries_ex_2_bits_deps_st_1; // @[ReservationStation.scala:107:110, :118:23] wire _issue_valids_T_324 = _issue_valids_T_323 | entries_ex_2_bits_deps_st_2; // @[ReservationStation.scala:107:110, :118:23] wire _issue_valids_T_325 = _issue_valids_T_324 | entries_ex_2_bits_deps_st_3; // @[ReservationStation.scala:107:110, :118:23] wire _issue_valids_T_326 = _issue_valids_T_322 | _issue_valids_T_325; // @[ReservationStation.scala:107:{64,90,110}] wire _issue_valids_T_327 = ~_issue_valids_T_326; // @[ReservationStation.scala:107:{39,90}] wire _issue_valids_T_328 = entries_ex_2_valid & _issue_valids_T_327; // @[ReservationStation.scala:107:39, :118:23, :395:54] wire _issue_valids_T_329 = ~entries_ex_2_bits_issued; // @[ReservationStation.scala:118:23, :395:75] wire issue_valids_2_1 = _issue_valids_T_328 & _issue_valids_T_329; // @[ReservationStation.scala:395:{54,72,75}] wire _issue_valids_T_330 = entries_ex_3_bits_deps_ld_0 | entries_ex_3_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_331 = _issue_valids_T_330 | entries_ex_3_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_332 = _issue_valids_T_331 | entries_ex_3_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_333 = _issue_valids_T_332 | entries_ex_3_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_334 = _issue_valids_T_333 | entries_ex_3_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_335 = _issue_valids_T_334 | entries_ex_3_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_336 = _issue_valids_T_335 | entries_ex_3_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_337 = entries_ex_3_bits_deps_ex_0 | entries_ex_3_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_338 = _issue_valids_T_337 | entries_ex_3_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_339 = _issue_valids_T_338 | entries_ex_3_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_340 = _issue_valids_T_339 | entries_ex_3_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_341 = _issue_valids_T_340 | entries_ex_3_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_342 = _issue_valids_T_341 | entries_ex_3_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_343 = _issue_valids_T_342 | entries_ex_3_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_344 = _issue_valids_T_343 | entries_ex_3_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_345 = _issue_valids_T_344 | entries_ex_3_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_346 = _issue_valids_T_345 | entries_ex_3_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_347 = _issue_valids_T_346 | entries_ex_3_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_348 = _issue_valids_T_347 | entries_ex_3_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_349 = _issue_valids_T_348 | entries_ex_3_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_350 = _issue_valids_T_349 | entries_ex_3_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_351 = _issue_valids_T_350 | entries_ex_3_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_352 = _issue_valids_T_336 | _issue_valids_T_351; // @[ReservationStation.scala:107:{58,64,84}] wire _issue_valids_T_353 = entries_ex_3_bits_deps_st_0 | entries_ex_3_bits_deps_st_1; // @[ReservationStation.scala:107:110, :118:23] wire _issue_valids_T_354 = _issue_valids_T_353 | entries_ex_3_bits_deps_st_2; // @[ReservationStation.scala:107:110, :118:23] wire _issue_valids_T_355 = _issue_valids_T_354 | entries_ex_3_bits_deps_st_3; // @[ReservationStation.scala:107:110, :118:23] wire _issue_valids_T_356 = _issue_valids_T_352 | _issue_valids_T_355; // @[ReservationStation.scala:107:{64,90,110}] wire _issue_valids_T_357 = ~_issue_valids_T_356; // @[ReservationStation.scala:107:{39,90}] wire _issue_valids_T_358 = entries_ex_3_valid & _issue_valids_T_357; // @[ReservationStation.scala:107:39, :118:23, :395:54] wire _issue_valids_T_359 = ~entries_ex_3_bits_issued; // @[ReservationStation.scala:118:23, :395:75] wire issue_valids_3_1 = _issue_valids_T_358 & _issue_valids_T_359; // @[ReservationStation.scala:395:{54,72,75}] wire _issue_valids_T_360 = entries_ex_4_bits_deps_ld_0 | entries_ex_4_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_361 = _issue_valids_T_360 | entries_ex_4_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_362 = _issue_valids_T_361 | entries_ex_4_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_363 = _issue_valids_T_362 | entries_ex_4_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_364 = _issue_valids_T_363 | entries_ex_4_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_365 = _issue_valids_T_364 | entries_ex_4_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_366 = _issue_valids_T_365 | entries_ex_4_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_367 = entries_ex_4_bits_deps_ex_0 | entries_ex_4_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_368 = _issue_valids_T_367 | entries_ex_4_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_369 = _issue_valids_T_368 | entries_ex_4_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_370 = _issue_valids_T_369 | entries_ex_4_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_371 = _issue_valids_T_370 | entries_ex_4_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_372 = _issue_valids_T_371 | entries_ex_4_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_373 = _issue_valids_T_372 | entries_ex_4_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_374 = _issue_valids_T_373 | entries_ex_4_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_375 = _issue_valids_T_374 | entries_ex_4_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_376 = _issue_valids_T_375 | entries_ex_4_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_377 = _issue_valids_T_376 | entries_ex_4_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_378 = _issue_valids_T_377 | entries_ex_4_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_379 = _issue_valids_T_378 | entries_ex_4_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_380 = _issue_valids_T_379 | entries_ex_4_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_381 = _issue_valids_T_380 | entries_ex_4_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_382 = _issue_valids_T_366 | _issue_valids_T_381; // @[ReservationStation.scala:107:{58,64,84}] wire _issue_valids_T_383 = entries_ex_4_bits_deps_st_0 | entries_ex_4_bits_deps_st_1; // @[ReservationStation.scala:107:110, :118:23] wire _issue_valids_T_384 = _issue_valids_T_383 | entries_ex_4_bits_deps_st_2; // @[ReservationStation.scala:107:110, :118:23] wire _issue_valids_T_385 = _issue_valids_T_384 | entries_ex_4_bits_deps_st_3; // @[ReservationStation.scala:107:110, :118:23] wire _issue_valids_T_386 = _issue_valids_T_382 | _issue_valids_T_385; // @[ReservationStation.scala:107:{64,90,110}] wire _issue_valids_T_387 = ~_issue_valids_T_386; // @[ReservationStation.scala:107:{39,90}] wire _issue_valids_T_388 = entries_ex_4_valid & _issue_valids_T_387; // @[ReservationStation.scala:107:39, :118:23, :395:54] wire _issue_valids_T_389 = ~entries_ex_4_bits_issued; // @[ReservationStation.scala:118:23, :395:75] wire issue_valids_4_1 = _issue_valids_T_388 & _issue_valids_T_389; // @[ReservationStation.scala:395:{54,72,75}] wire _issue_valids_T_390 = entries_ex_5_bits_deps_ld_0 | entries_ex_5_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_391 = _issue_valids_T_390 | entries_ex_5_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_392 = _issue_valids_T_391 | entries_ex_5_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_393 = _issue_valids_T_392 | entries_ex_5_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_394 = _issue_valids_T_393 | entries_ex_5_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_395 = _issue_valids_T_394 | entries_ex_5_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_396 = _issue_valids_T_395 | entries_ex_5_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_397 = entries_ex_5_bits_deps_ex_0 | entries_ex_5_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_398 = _issue_valids_T_397 | entries_ex_5_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_399 = _issue_valids_T_398 | entries_ex_5_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_400 = _issue_valids_T_399 | entries_ex_5_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_401 = _issue_valids_T_400 | entries_ex_5_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_402 = _issue_valids_T_401 | entries_ex_5_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_403 = _issue_valids_T_402 | entries_ex_5_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_404 = _issue_valids_T_403 | entries_ex_5_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_405 = _issue_valids_T_404 | entries_ex_5_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_406 = _issue_valids_T_405 | entries_ex_5_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_407 = _issue_valids_T_406 | entries_ex_5_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_408 = _issue_valids_T_407 | entries_ex_5_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_409 = _issue_valids_T_408 | entries_ex_5_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_410 = _issue_valids_T_409 | entries_ex_5_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_411 = _issue_valids_T_410 | entries_ex_5_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_412 = _issue_valids_T_396 | _issue_valids_T_411; // @[ReservationStation.scala:107:{58,64,84}] wire _issue_valids_T_413 = entries_ex_5_bits_deps_st_0 | entries_ex_5_bits_deps_st_1; // @[ReservationStation.scala:107:110, :118:23] wire _issue_valids_T_414 = _issue_valids_T_413 | entries_ex_5_bits_deps_st_2; // @[ReservationStation.scala:107:110, :118:23] wire _issue_valids_T_415 = _issue_valids_T_414 | entries_ex_5_bits_deps_st_3; // @[ReservationStation.scala:107:110, :118:23] wire _issue_valids_T_416 = _issue_valids_T_412 | _issue_valids_T_415; // @[ReservationStation.scala:107:{64,90,110}] wire _issue_valids_T_417 = ~_issue_valids_T_416; // @[ReservationStation.scala:107:{39,90}] wire _issue_valids_T_418 = entries_ex_5_valid & _issue_valids_T_417; // @[ReservationStation.scala:107:39, :118:23, :395:54] wire _issue_valids_T_419 = ~entries_ex_5_bits_issued; // @[ReservationStation.scala:118:23, :395:75] wire issue_valids_5_1 = _issue_valids_T_418 & _issue_valids_T_419; // @[ReservationStation.scala:395:{54,72,75}] wire _issue_valids_T_420 = entries_ex_6_bits_deps_ld_0 | entries_ex_6_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_421 = _issue_valids_T_420 | entries_ex_6_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_422 = _issue_valids_T_421 | entries_ex_6_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_423 = _issue_valids_T_422 | entries_ex_6_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_424 = _issue_valids_T_423 | entries_ex_6_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_425 = _issue_valids_T_424 | entries_ex_6_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_426 = _issue_valids_T_425 | entries_ex_6_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_427 = entries_ex_6_bits_deps_ex_0 | entries_ex_6_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_428 = _issue_valids_T_427 | entries_ex_6_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_429 = _issue_valids_T_428 | entries_ex_6_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_430 = _issue_valids_T_429 | entries_ex_6_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_431 = _issue_valids_T_430 | entries_ex_6_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_432 = _issue_valids_T_431 | entries_ex_6_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_433 = _issue_valids_T_432 | entries_ex_6_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_434 = _issue_valids_T_433 | entries_ex_6_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_435 = _issue_valids_T_434 | entries_ex_6_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_436 = _issue_valids_T_435 | entries_ex_6_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_437 = _issue_valids_T_436 | entries_ex_6_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_438 = _issue_valids_T_437 | entries_ex_6_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_439 = _issue_valids_T_438 | entries_ex_6_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_440 = _issue_valids_T_439 | entries_ex_6_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_441 = _issue_valids_T_440 | entries_ex_6_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_442 = _issue_valids_T_426 | _issue_valids_T_441; // @[ReservationStation.scala:107:{58,64,84}] wire _issue_valids_T_443 = entries_ex_6_bits_deps_st_0 | entries_ex_6_bits_deps_st_1; // @[ReservationStation.scala:107:110, :118:23] wire _issue_valids_T_444 = _issue_valids_T_443 | entries_ex_6_bits_deps_st_2; // @[ReservationStation.scala:107:110, :118:23] wire _issue_valids_T_445 = _issue_valids_T_444 | entries_ex_6_bits_deps_st_3; // @[ReservationStation.scala:107:110, :118:23] wire _issue_valids_T_446 = _issue_valids_T_442 | _issue_valids_T_445; // @[ReservationStation.scala:107:{64,90,110}] wire _issue_valids_T_447 = ~_issue_valids_T_446; // @[ReservationStation.scala:107:{39,90}] wire _issue_valids_T_448 = entries_ex_6_valid & _issue_valids_T_447; // @[ReservationStation.scala:107:39, :118:23, :395:54] wire _issue_valids_T_449 = ~entries_ex_6_bits_issued; // @[ReservationStation.scala:118:23, :395:75] wire issue_valids_6_1 = _issue_valids_T_448 & _issue_valids_T_449; // @[ReservationStation.scala:395:{54,72,75}] wire _issue_valids_T_450 = entries_ex_7_bits_deps_ld_0 | entries_ex_7_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_451 = _issue_valids_T_450 | entries_ex_7_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_452 = _issue_valids_T_451 | entries_ex_7_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_453 = _issue_valids_T_452 | entries_ex_7_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_454 = _issue_valids_T_453 | entries_ex_7_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_455 = _issue_valids_T_454 | entries_ex_7_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_456 = _issue_valids_T_455 | entries_ex_7_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_457 = entries_ex_7_bits_deps_ex_0 | entries_ex_7_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_458 = _issue_valids_T_457 | entries_ex_7_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_459 = _issue_valids_T_458 | entries_ex_7_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_460 = _issue_valids_T_459 | entries_ex_7_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_461 = _issue_valids_T_460 | entries_ex_7_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_462 = _issue_valids_T_461 | entries_ex_7_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_463 = _issue_valids_T_462 | entries_ex_7_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_464 = _issue_valids_T_463 | entries_ex_7_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_465 = _issue_valids_T_464 | entries_ex_7_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_466 = _issue_valids_T_465 | entries_ex_7_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_467 = _issue_valids_T_466 | entries_ex_7_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_468 = _issue_valids_T_467 | entries_ex_7_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_469 = _issue_valids_T_468 | entries_ex_7_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_470 = _issue_valids_T_469 | entries_ex_7_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_471 = _issue_valids_T_470 | entries_ex_7_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_472 = _issue_valids_T_456 | _issue_valids_T_471; // @[ReservationStation.scala:107:{58,64,84}] wire _issue_valids_T_473 = entries_ex_7_bits_deps_st_0 | entries_ex_7_bits_deps_st_1; // @[ReservationStation.scala:107:110, :118:23] wire _issue_valids_T_474 = _issue_valids_T_473 | entries_ex_7_bits_deps_st_2; // @[ReservationStation.scala:107:110, :118:23] wire _issue_valids_T_475 = _issue_valids_T_474 | entries_ex_7_bits_deps_st_3; // @[ReservationStation.scala:107:110, :118:23] wire _issue_valids_T_476 = _issue_valids_T_472 | _issue_valids_T_475; // @[ReservationStation.scala:107:{64,90,110}] wire _issue_valids_T_477 = ~_issue_valids_T_476; // @[ReservationStation.scala:107:{39,90}] wire _issue_valids_T_478 = entries_ex_7_valid & _issue_valids_T_477; // @[ReservationStation.scala:107:39, :118:23, :395:54] wire _issue_valids_T_479 = ~entries_ex_7_bits_issued; // @[ReservationStation.scala:118:23, :395:75] wire issue_valids_7_1 = _issue_valids_T_478 & _issue_valids_T_479; // @[ReservationStation.scala:395:{54,72,75}] wire _issue_valids_T_480 = entries_ex_8_bits_deps_ld_0 | entries_ex_8_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_481 = _issue_valids_T_480 | entries_ex_8_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_482 = _issue_valids_T_481 | entries_ex_8_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_483 = _issue_valids_T_482 | entries_ex_8_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_484 = _issue_valids_T_483 | entries_ex_8_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_485 = _issue_valids_T_484 | entries_ex_8_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_486 = _issue_valids_T_485 | entries_ex_8_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_487 = entries_ex_8_bits_deps_ex_0 | entries_ex_8_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_488 = _issue_valids_T_487 | entries_ex_8_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_489 = _issue_valids_T_488 | entries_ex_8_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_490 = _issue_valids_T_489 | entries_ex_8_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_491 = _issue_valids_T_490 | entries_ex_8_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_492 = _issue_valids_T_491 | entries_ex_8_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_493 = _issue_valids_T_492 | entries_ex_8_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_494 = _issue_valids_T_493 | entries_ex_8_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_495 = _issue_valids_T_494 | entries_ex_8_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_496 = _issue_valids_T_495 | entries_ex_8_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_497 = _issue_valids_T_496 | entries_ex_8_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_498 = _issue_valids_T_497 | entries_ex_8_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_499 = _issue_valids_T_498 | entries_ex_8_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_500 = _issue_valids_T_499 | entries_ex_8_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_501 = _issue_valids_T_500 | entries_ex_8_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_502 = _issue_valids_T_486 | _issue_valids_T_501; // @[ReservationStation.scala:107:{58,64,84}] wire _issue_valids_T_503 = entries_ex_8_bits_deps_st_0 | entries_ex_8_bits_deps_st_1; // @[ReservationStation.scala:107:110, :118:23] wire _issue_valids_T_504 = _issue_valids_T_503 | entries_ex_8_bits_deps_st_2; // @[ReservationStation.scala:107:110, :118:23] wire _issue_valids_T_505 = _issue_valids_T_504 | entries_ex_8_bits_deps_st_3; // @[ReservationStation.scala:107:110, :118:23] wire _issue_valids_T_506 = _issue_valids_T_502 | _issue_valids_T_505; // @[ReservationStation.scala:107:{64,90,110}] wire _issue_valids_T_507 = ~_issue_valids_T_506; // @[ReservationStation.scala:107:{39,90}] wire _issue_valids_T_508 = entries_ex_8_valid & _issue_valids_T_507; // @[ReservationStation.scala:107:39, :118:23, :395:54] wire _issue_valids_T_509 = ~entries_ex_8_bits_issued; // @[ReservationStation.scala:118:23, :395:75] wire issue_valids_8 = _issue_valids_T_508 & _issue_valids_T_509; // @[ReservationStation.scala:395:{54,72,75}] wire _issue_valids_T_510 = entries_ex_9_bits_deps_ld_0 | entries_ex_9_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_511 = _issue_valids_T_510 | entries_ex_9_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_512 = _issue_valids_T_511 | entries_ex_9_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_513 = _issue_valids_T_512 | entries_ex_9_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_514 = _issue_valids_T_513 | entries_ex_9_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_515 = _issue_valids_T_514 | entries_ex_9_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_516 = _issue_valids_T_515 | entries_ex_9_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_517 = entries_ex_9_bits_deps_ex_0 | entries_ex_9_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_518 = _issue_valids_T_517 | entries_ex_9_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_519 = _issue_valids_T_518 | entries_ex_9_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_520 = _issue_valids_T_519 | entries_ex_9_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_521 = _issue_valids_T_520 | entries_ex_9_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_522 = _issue_valids_T_521 | entries_ex_9_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_523 = _issue_valids_T_522 | entries_ex_9_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_524 = _issue_valids_T_523 | entries_ex_9_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_525 = _issue_valids_T_524 | entries_ex_9_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_526 = _issue_valids_T_525 | entries_ex_9_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_527 = _issue_valids_T_526 | entries_ex_9_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_528 = _issue_valids_T_527 | entries_ex_9_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_529 = _issue_valids_T_528 | entries_ex_9_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_530 = _issue_valids_T_529 | entries_ex_9_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_531 = _issue_valids_T_530 | entries_ex_9_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_532 = _issue_valids_T_516 | _issue_valids_T_531; // @[ReservationStation.scala:107:{58,64,84}] wire _issue_valids_T_533 = entries_ex_9_bits_deps_st_0 | entries_ex_9_bits_deps_st_1; // @[ReservationStation.scala:107:110, :118:23] wire _issue_valids_T_534 = _issue_valids_T_533 | entries_ex_9_bits_deps_st_2; // @[ReservationStation.scala:107:110, :118:23] wire _issue_valids_T_535 = _issue_valids_T_534 | entries_ex_9_bits_deps_st_3; // @[ReservationStation.scala:107:110, :118:23] wire _issue_valids_T_536 = _issue_valids_T_532 | _issue_valids_T_535; // @[ReservationStation.scala:107:{64,90,110}] wire _issue_valids_T_537 = ~_issue_valids_T_536; // @[ReservationStation.scala:107:{39,90}] wire _issue_valids_T_538 = entries_ex_9_valid & _issue_valids_T_537; // @[ReservationStation.scala:107:39, :118:23, :395:54] wire _issue_valids_T_539 = ~entries_ex_9_bits_issued; // @[ReservationStation.scala:118:23, :395:75] wire issue_valids_9 = _issue_valids_T_538 & _issue_valids_T_539; // @[ReservationStation.scala:395:{54,72,75}] wire _issue_valids_T_540 = entries_ex_10_bits_deps_ld_0 | entries_ex_10_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_541 = _issue_valids_T_540 | entries_ex_10_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_542 = _issue_valids_T_541 | entries_ex_10_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_543 = _issue_valids_T_542 | entries_ex_10_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_544 = _issue_valids_T_543 | entries_ex_10_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_545 = _issue_valids_T_544 | entries_ex_10_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_546 = _issue_valids_T_545 | entries_ex_10_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_547 = entries_ex_10_bits_deps_ex_0 | entries_ex_10_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_548 = _issue_valids_T_547 | entries_ex_10_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_549 = _issue_valids_T_548 | entries_ex_10_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_550 = _issue_valids_T_549 | entries_ex_10_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_551 = _issue_valids_T_550 | entries_ex_10_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_552 = _issue_valids_T_551 | entries_ex_10_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_553 = _issue_valids_T_552 | entries_ex_10_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_554 = _issue_valids_T_553 | entries_ex_10_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_555 = _issue_valids_T_554 | entries_ex_10_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_556 = _issue_valids_T_555 | entries_ex_10_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_557 = _issue_valids_T_556 | entries_ex_10_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_558 = _issue_valids_T_557 | entries_ex_10_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_559 = _issue_valids_T_558 | entries_ex_10_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_560 = _issue_valids_T_559 | entries_ex_10_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_561 = _issue_valids_T_560 | entries_ex_10_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_562 = _issue_valids_T_546 | _issue_valids_T_561; // @[ReservationStation.scala:107:{58,64,84}] wire _issue_valids_T_563 = entries_ex_10_bits_deps_st_0 | entries_ex_10_bits_deps_st_1; // @[ReservationStation.scala:107:110, :118:23] wire _issue_valids_T_564 = _issue_valids_T_563 | entries_ex_10_bits_deps_st_2; // @[ReservationStation.scala:107:110, :118:23] wire _issue_valids_T_565 = _issue_valids_T_564 | entries_ex_10_bits_deps_st_3; // @[ReservationStation.scala:107:110, :118:23] wire _issue_valids_T_566 = _issue_valids_T_562 | _issue_valids_T_565; // @[ReservationStation.scala:107:{64,90,110}] wire _issue_valids_T_567 = ~_issue_valids_T_566; // @[ReservationStation.scala:107:{39,90}] wire _issue_valids_T_568 = entries_ex_10_valid & _issue_valids_T_567; // @[ReservationStation.scala:107:39, :118:23, :395:54] wire _issue_valids_T_569 = ~entries_ex_10_bits_issued; // @[ReservationStation.scala:118:23, :395:75] wire issue_valids_10 = _issue_valids_T_568 & _issue_valids_T_569; // @[ReservationStation.scala:395:{54,72,75}] wire _issue_valids_T_570 = entries_ex_11_bits_deps_ld_0 | entries_ex_11_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_571 = _issue_valids_T_570 | entries_ex_11_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_572 = _issue_valids_T_571 | entries_ex_11_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_573 = _issue_valids_T_572 | entries_ex_11_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_574 = _issue_valids_T_573 | entries_ex_11_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_575 = _issue_valids_T_574 | entries_ex_11_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_576 = _issue_valids_T_575 | entries_ex_11_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_577 = entries_ex_11_bits_deps_ex_0 | entries_ex_11_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_578 = _issue_valids_T_577 | entries_ex_11_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_579 = _issue_valids_T_578 | entries_ex_11_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_580 = _issue_valids_T_579 | entries_ex_11_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_581 = _issue_valids_T_580 | entries_ex_11_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_582 = _issue_valids_T_581 | entries_ex_11_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_583 = _issue_valids_T_582 | entries_ex_11_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_584 = _issue_valids_T_583 | entries_ex_11_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_585 = _issue_valids_T_584 | entries_ex_11_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_586 = _issue_valids_T_585 | entries_ex_11_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_587 = _issue_valids_T_586 | entries_ex_11_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_588 = _issue_valids_T_587 | entries_ex_11_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_589 = _issue_valids_T_588 | entries_ex_11_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_590 = _issue_valids_T_589 | entries_ex_11_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_591 = _issue_valids_T_590 | entries_ex_11_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_592 = _issue_valids_T_576 | _issue_valids_T_591; // @[ReservationStation.scala:107:{58,64,84}] wire _issue_valids_T_593 = entries_ex_11_bits_deps_st_0 | entries_ex_11_bits_deps_st_1; // @[ReservationStation.scala:107:110, :118:23] wire _issue_valids_T_594 = _issue_valids_T_593 | entries_ex_11_bits_deps_st_2; // @[ReservationStation.scala:107:110, :118:23] wire _issue_valids_T_595 = _issue_valids_T_594 | entries_ex_11_bits_deps_st_3; // @[ReservationStation.scala:107:110, :118:23] wire _issue_valids_T_596 = _issue_valids_T_592 | _issue_valids_T_595; // @[ReservationStation.scala:107:{64,90,110}] wire _issue_valids_T_597 = ~_issue_valids_T_596; // @[ReservationStation.scala:107:{39,90}] wire _issue_valids_T_598 = entries_ex_11_valid & _issue_valids_T_597; // @[ReservationStation.scala:107:39, :118:23, :395:54] wire _issue_valids_T_599 = ~entries_ex_11_bits_issued; // @[ReservationStation.scala:118:23, :395:75] wire issue_valids_11 = _issue_valids_T_598 & _issue_valids_T_599; // @[ReservationStation.scala:395:{54,72,75}] wire _issue_valids_T_600 = entries_ex_12_bits_deps_ld_0 | entries_ex_12_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_601 = _issue_valids_T_600 | entries_ex_12_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_602 = _issue_valids_T_601 | entries_ex_12_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_603 = _issue_valids_T_602 | entries_ex_12_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_604 = _issue_valids_T_603 | entries_ex_12_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_605 = _issue_valids_T_604 | entries_ex_12_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_606 = _issue_valids_T_605 | entries_ex_12_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_607 = entries_ex_12_bits_deps_ex_0 | entries_ex_12_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_608 = _issue_valids_T_607 | entries_ex_12_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_609 = _issue_valids_T_608 | entries_ex_12_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_610 = _issue_valids_T_609 | entries_ex_12_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_611 = _issue_valids_T_610 | entries_ex_12_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_612 = _issue_valids_T_611 | entries_ex_12_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_613 = _issue_valids_T_612 | entries_ex_12_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_614 = _issue_valids_T_613 | entries_ex_12_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_615 = _issue_valids_T_614 | entries_ex_12_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_616 = _issue_valids_T_615 | entries_ex_12_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_617 = _issue_valids_T_616 | entries_ex_12_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_618 = _issue_valids_T_617 | entries_ex_12_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_619 = _issue_valids_T_618 | entries_ex_12_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_620 = _issue_valids_T_619 | entries_ex_12_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_621 = _issue_valids_T_620 | entries_ex_12_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_622 = _issue_valids_T_606 | _issue_valids_T_621; // @[ReservationStation.scala:107:{58,64,84}] wire _issue_valids_T_623 = entries_ex_12_bits_deps_st_0 | entries_ex_12_bits_deps_st_1; // @[ReservationStation.scala:107:110, :118:23] wire _issue_valids_T_624 = _issue_valids_T_623 | entries_ex_12_bits_deps_st_2; // @[ReservationStation.scala:107:110, :118:23] wire _issue_valids_T_625 = _issue_valids_T_624 | entries_ex_12_bits_deps_st_3; // @[ReservationStation.scala:107:110, :118:23] wire _issue_valids_T_626 = _issue_valids_T_622 | _issue_valids_T_625; // @[ReservationStation.scala:107:{64,90,110}] wire _issue_valids_T_627 = ~_issue_valids_T_626; // @[ReservationStation.scala:107:{39,90}] wire _issue_valids_T_628 = entries_ex_12_valid & _issue_valids_T_627; // @[ReservationStation.scala:107:39, :118:23, :395:54] wire _issue_valids_T_629 = ~entries_ex_12_bits_issued; // @[ReservationStation.scala:118:23, :395:75] wire issue_valids_12 = _issue_valids_T_628 & _issue_valids_T_629; // @[ReservationStation.scala:395:{54,72,75}] wire _issue_valids_T_630 = entries_ex_13_bits_deps_ld_0 | entries_ex_13_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_631 = _issue_valids_T_630 | entries_ex_13_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_632 = _issue_valids_T_631 | entries_ex_13_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_633 = _issue_valids_T_632 | entries_ex_13_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_634 = _issue_valids_T_633 | entries_ex_13_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_635 = _issue_valids_T_634 | entries_ex_13_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_636 = _issue_valids_T_635 | entries_ex_13_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_637 = entries_ex_13_bits_deps_ex_0 | entries_ex_13_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_638 = _issue_valids_T_637 | entries_ex_13_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_639 = _issue_valids_T_638 | entries_ex_13_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_640 = _issue_valids_T_639 | entries_ex_13_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_641 = _issue_valids_T_640 | entries_ex_13_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_642 = _issue_valids_T_641 | entries_ex_13_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_643 = _issue_valids_T_642 | entries_ex_13_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_644 = _issue_valids_T_643 | entries_ex_13_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_645 = _issue_valids_T_644 | entries_ex_13_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_646 = _issue_valids_T_645 | entries_ex_13_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_647 = _issue_valids_T_646 | entries_ex_13_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_648 = _issue_valids_T_647 | entries_ex_13_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_649 = _issue_valids_T_648 | entries_ex_13_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_650 = _issue_valids_T_649 | entries_ex_13_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_651 = _issue_valids_T_650 | entries_ex_13_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_652 = _issue_valids_T_636 | _issue_valids_T_651; // @[ReservationStation.scala:107:{58,64,84}] wire _issue_valids_T_653 = entries_ex_13_bits_deps_st_0 | entries_ex_13_bits_deps_st_1; // @[ReservationStation.scala:107:110, :118:23] wire _issue_valids_T_654 = _issue_valids_T_653 | entries_ex_13_bits_deps_st_2; // @[ReservationStation.scala:107:110, :118:23] wire _issue_valids_T_655 = _issue_valids_T_654 | entries_ex_13_bits_deps_st_3; // @[ReservationStation.scala:107:110, :118:23] wire _issue_valids_T_656 = _issue_valids_T_652 | _issue_valids_T_655; // @[ReservationStation.scala:107:{64,90,110}] wire _issue_valids_T_657 = ~_issue_valids_T_656; // @[ReservationStation.scala:107:{39,90}] wire _issue_valids_T_658 = entries_ex_13_valid & _issue_valids_T_657; // @[ReservationStation.scala:107:39, :118:23, :395:54] wire _issue_valids_T_659 = ~entries_ex_13_bits_issued; // @[ReservationStation.scala:118:23, :395:75] wire issue_valids_13 = _issue_valids_T_658 & _issue_valids_T_659; // @[ReservationStation.scala:395:{54,72,75}] wire _issue_valids_T_660 = entries_ex_14_bits_deps_ld_0 | entries_ex_14_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_661 = _issue_valids_T_660 | entries_ex_14_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_662 = _issue_valids_T_661 | entries_ex_14_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_663 = _issue_valids_T_662 | entries_ex_14_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_664 = _issue_valids_T_663 | entries_ex_14_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_665 = _issue_valids_T_664 | entries_ex_14_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_666 = _issue_valids_T_665 | entries_ex_14_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_667 = entries_ex_14_bits_deps_ex_0 | entries_ex_14_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_668 = _issue_valids_T_667 | entries_ex_14_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_669 = _issue_valids_T_668 | entries_ex_14_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_670 = _issue_valids_T_669 | entries_ex_14_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_671 = _issue_valids_T_670 | entries_ex_14_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_672 = _issue_valids_T_671 | entries_ex_14_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_673 = _issue_valids_T_672 | entries_ex_14_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_674 = _issue_valids_T_673 | entries_ex_14_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_675 = _issue_valids_T_674 | entries_ex_14_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_676 = _issue_valids_T_675 | entries_ex_14_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_677 = _issue_valids_T_676 | entries_ex_14_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_678 = _issue_valids_T_677 | entries_ex_14_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_679 = _issue_valids_T_678 | entries_ex_14_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_680 = _issue_valids_T_679 | entries_ex_14_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_681 = _issue_valids_T_680 | entries_ex_14_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_682 = _issue_valids_T_666 | _issue_valids_T_681; // @[ReservationStation.scala:107:{58,64,84}] wire _issue_valids_T_683 = entries_ex_14_bits_deps_st_0 | entries_ex_14_bits_deps_st_1; // @[ReservationStation.scala:107:110, :118:23] wire _issue_valids_T_684 = _issue_valids_T_683 | entries_ex_14_bits_deps_st_2; // @[ReservationStation.scala:107:110, :118:23] wire _issue_valids_T_685 = _issue_valids_T_684 | entries_ex_14_bits_deps_st_3; // @[ReservationStation.scala:107:110, :118:23] wire _issue_valids_T_686 = _issue_valids_T_682 | _issue_valids_T_685; // @[ReservationStation.scala:107:{64,90,110}] wire _issue_valids_T_687 = ~_issue_valids_T_686; // @[ReservationStation.scala:107:{39,90}] wire _issue_valids_T_688 = entries_ex_14_valid & _issue_valids_T_687; // @[ReservationStation.scala:107:39, :118:23, :395:54] wire _issue_valids_T_689 = ~entries_ex_14_bits_issued; // @[ReservationStation.scala:118:23, :395:75] wire issue_valids_14 = _issue_valids_T_688 & _issue_valids_T_689; // @[ReservationStation.scala:395:{54,72,75}] wire _issue_valids_T_690 = entries_ex_15_bits_deps_ld_0 | entries_ex_15_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_691 = _issue_valids_T_690 | entries_ex_15_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_692 = _issue_valids_T_691 | entries_ex_15_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_693 = _issue_valids_T_692 | entries_ex_15_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_694 = _issue_valids_T_693 | entries_ex_15_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_695 = _issue_valids_T_694 | entries_ex_15_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_696 = _issue_valids_T_695 | entries_ex_15_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :118:23] wire _issue_valids_T_697 = entries_ex_15_bits_deps_ex_0 | entries_ex_15_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_698 = _issue_valids_T_697 | entries_ex_15_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_699 = _issue_valids_T_698 | entries_ex_15_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_700 = _issue_valids_T_699 | entries_ex_15_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_701 = _issue_valids_T_700 | entries_ex_15_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_702 = _issue_valids_T_701 | entries_ex_15_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_703 = _issue_valids_T_702 | entries_ex_15_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_704 = _issue_valids_T_703 | entries_ex_15_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_705 = _issue_valids_T_704 | entries_ex_15_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_706 = _issue_valids_T_705 | entries_ex_15_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_707 = _issue_valids_T_706 | entries_ex_15_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_708 = _issue_valids_T_707 | entries_ex_15_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_709 = _issue_valids_T_708 | entries_ex_15_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_710 = _issue_valids_T_709 | entries_ex_15_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_711 = _issue_valids_T_710 | entries_ex_15_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :118:23] wire _issue_valids_T_712 = _issue_valids_T_696 | _issue_valids_T_711; // @[ReservationStation.scala:107:{58,64,84}] wire _issue_valids_T_713 = entries_ex_15_bits_deps_st_0 | entries_ex_15_bits_deps_st_1; // @[ReservationStation.scala:107:110, :118:23] wire _issue_valids_T_714 = _issue_valids_T_713 | entries_ex_15_bits_deps_st_2; // @[ReservationStation.scala:107:110, :118:23] wire _issue_valids_T_715 = _issue_valids_T_714 | entries_ex_15_bits_deps_st_3; // @[ReservationStation.scala:107:110, :118:23] wire _issue_valids_T_716 = _issue_valids_T_712 | _issue_valids_T_715; // @[ReservationStation.scala:107:{64,90,110}] wire _issue_valids_T_717 = ~_issue_valids_T_716; // @[ReservationStation.scala:107:{39,90}] wire _issue_valids_T_718 = entries_ex_15_valid & _issue_valids_T_717; // @[ReservationStation.scala:107:39, :118:23, :395:54] wire _issue_valids_T_719 = ~entries_ex_15_bits_issued; // @[ReservationStation.scala:118:23, :395:75] wire issue_valids_15 = _issue_valids_T_718 & _issue_valids_T_719; // @[ReservationStation.scala:395:{54,72,75}] wire [15:0] _issue_sel_enc_T_7 = {issue_valids_15, 15'h0}; // @[Mux.scala:50:70] wire [15:0] _issue_sel_enc_T_8 = issue_valids_14 ? 16'h4000 : _issue_sel_enc_T_7; // @[Mux.scala:50:70] wire [15:0] _issue_sel_enc_T_9 = issue_valids_13 ? 16'h2000 : _issue_sel_enc_T_8; // @[Mux.scala:50:70] wire [15:0] _issue_sel_enc_T_10 = issue_valids_12 ? 16'h1000 : _issue_sel_enc_T_9; // @[Mux.scala:50:70] wire [15:0] _issue_sel_enc_T_11 = issue_valids_11 ? 16'h800 : _issue_sel_enc_T_10; // @[Mux.scala:50:70] wire [15:0] _issue_sel_enc_T_12 = issue_valids_10 ? 16'h400 : _issue_sel_enc_T_11; // @[Mux.scala:50:70] wire [15:0] _issue_sel_enc_T_13 = issue_valids_9 ? 16'h200 : _issue_sel_enc_T_12; // @[Mux.scala:50:70] wire [15:0] _issue_sel_enc_T_14 = issue_valids_8 ? 16'h100 : _issue_sel_enc_T_13; // @[Mux.scala:50:70] wire [15:0] _issue_sel_enc_T_15 = issue_valids_7_1 ? 16'h80 : _issue_sel_enc_T_14; // @[Mux.scala:50:70] wire [15:0] _issue_sel_enc_T_16 = issue_valids_6_1 ? 16'h40 : _issue_sel_enc_T_15; // @[Mux.scala:50:70] wire [15:0] _issue_sel_enc_T_17 = issue_valids_5_1 ? 16'h20 : _issue_sel_enc_T_16; // @[Mux.scala:50:70] wire [15:0] _issue_sel_enc_T_18 = issue_valids_4_1 ? 16'h10 : _issue_sel_enc_T_17; // @[Mux.scala:50:70] wire [15:0] _issue_sel_enc_T_19 = issue_valids_3_1 ? 16'h8 : _issue_sel_enc_T_18; // @[Mux.scala:50:70] wire [15:0] _issue_sel_enc_T_20 = issue_valids_2_1 ? 16'h4 : _issue_sel_enc_T_19; // @[Mux.scala:50:70] wire [15:0] _issue_sel_enc_T_21 = issue_valids_1_1 ? 16'h2 : _issue_sel_enc_T_20; // @[Mux.scala:50:70] wire [15:0] issue_sel_enc_1 = issue_valids_0_1 ? 16'h1 : _issue_sel_enc_T_21; // @[Mux.scala:50:70] wire issue_sel_0_1 = issue_sel_enc_1[0]; // @[OneHot.scala:83:30] wire issue_sel_1_1 = issue_sel_enc_1[1]; // @[OneHot.scala:83:30] wire issue_sel_2_1 = issue_sel_enc_1[2]; // @[OneHot.scala:83:30] wire issue_sel_3_1 = issue_sel_enc_1[3]; // @[OneHot.scala:83:30] wire issue_sel_4_1 = issue_sel_enc_1[4]; // @[OneHot.scala:83:30] wire issue_sel_5_1 = issue_sel_enc_1[5]; // @[OneHot.scala:83:30] wire issue_sel_6_1 = issue_sel_enc_1[6]; // @[OneHot.scala:83:30] wire issue_sel_7_1 = issue_sel_enc_1[7]; // @[OneHot.scala:83:30] wire issue_sel_8 = issue_sel_enc_1[8]; // @[OneHot.scala:83:30] wire issue_sel_9 = issue_sel_enc_1[9]; // @[OneHot.scala:83:30] wire issue_sel_10 = issue_sel_enc_1[10]; // @[OneHot.scala:83:30] wire issue_sel_11 = issue_sel_enc_1[11]; // @[OneHot.scala:83:30] wire issue_sel_12 = issue_sel_enc_1[12]; // @[OneHot.scala:83:30] wire issue_sel_13 = issue_sel_enc_1[13]; // @[OneHot.scala:83:30] wire issue_sel_14 = issue_sel_enc_1[14]; // @[OneHot.scala:83:30] wire issue_sel_15 = issue_sel_enc_1[15]; // @[OneHot.scala:83:30] wire [1:0] issue_id_lo_lo_lo = {issue_sel_1_1, issue_sel_0_1}; // @[OneHot.scala:21:45, :83:30] wire [1:0] issue_id_lo_lo_hi = {issue_sel_3_1, issue_sel_2_1}; // @[OneHot.scala:21:45, :83:30] wire [3:0] issue_id_lo_lo_1 = {issue_id_lo_lo_hi, issue_id_lo_lo_lo}; // @[OneHot.scala:21:45] wire [1:0] issue_id_lo_hi_lo = {issue_sel_5_1, issue_sel_4_1}; // @[OneHot.scala:21:45, :83:30] wire [1:0] issue_id_lo_hi_hi = {issue_sel_7_1, issue_sel_6_1}; // @[OneHot.scala:21:45, :83:30] wire [3:0] issue_id_lo_hi_1 = {issue_id_lo_hi_hi, issue_id_lo_hi_lo}; // @[OneHot.scala:21:45] wire [7:0] issue_id_lo_3 = {issue_id_lo_hi_1, issue_id_lo_lo_1}; // @[OneHot.scala:21:45] wire [1:0] issue_id_hi_lo_lo = {issue_sel_9, issue_sel_8}; // @[OneHot.scala:21:45, :83:30] wire [1:0] issue_id_hi_lo_hi = {issue_sel_11, issue_sel_10}; // @[OneHot.scala:21:45, :83:30] wire [3:0] issue_id_hi_lo_1 = {issue_id_hi_lo_hi, issue_id_hi_lo_lo}; // @[OneHot.scala:21:45] wire [1:0] issue_id_hi_hi_lo = {issue_sel_13, issue_sel_12}; // @[OneHot.scala:21:45, :83:30] wire [1:0] issue_id_hi_hi_hi = {issue_sel_15, issue_sel_14}; // @[OneHot.scala:21:45, :83:30] wire [3:0] issue_id_hi_hi_1 = {issue_id_hi_hi_hi, issue_id_hi_hi_lo}; // @[OneHot.scala:21:45] wire [7:0] issue_id_hi_3 = {issue_id_hi_hi_1, issue_id_hi_lo_1}; // @[OneHot.scala:21:45] wire [15:0] _issue_id_T_7 = {issue_id_hi_3, issue_id_lo_3}; // @[OneHot.scala:21:45] wire [7:0] issue_id_hi_4 = _issue_id_T_7[15:8]; // @[OneHot.scala:21:45, :30:18] wire [7:0] issue_id_lo_4 = _issue_id_T_7[7:0]; // @[OneHot.scala:21:45, :31:18] wire _issue_id_T_8 = |issue_id_hi_4; // @[OneHot.scala:30:18, :32:14] wire [7:0] _issue_id_T_9 = issue_id_hi_4 | issue_id_lo_4; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] issue_id_hi_5 = _issue_id_T_9[7:4]; // @[OneHot.scala:30:18, :32:28] wire [3:0] issue_id_lo_5 = _issue_id_T_9[3:0]; // @[OneHot.scala:31:18, :32:28] wire _issue_id_T_10 = |issue_id_hi_5; // @[OneHot.scala:30:18, :32:14] wire [3:0] _issue_id_T_11 = issue_id_hi_5 | issue_id_lo_5; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] issue_id_hi_6 = _issue_id_T_11[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] issue_id_lo_6 = _issue_id_T_11[1:0]; // @[OneHot.scala:31:18, :32:28] wire _issue_id_T_12 = |issue_id_hi_6; // @[OneHot.scala:30:18, :32:14] wire [1:0] _issue_id_T_13 = issue_id_hi_6 | issue_id_lo_6; // @[OneHot.scala:30:18, :31:18, :32:28] wire _issue_id_T_14 = _issue_id_T_13[1]; // @[OneHot.scala:32:28] wire [1:0] _issue_id_T_15 = {_issue_id_T_12, _issue_id_T_14}; // @[OneHot.scala:32:{10,14}] wire [2:0] _issue_id_T_16 = {_issue_id_T_10, _issue_id_T_15}; // @[OneHot.scala:32:{10,14}] wire [3:0] issue_id_1 = {_issue_id_T_8, _issue_id_T_16}; // @[OneHot.scala:32:{10,14}] assign global_issue_id_1 = {2'h1, issue_id_1}; // @[OneHot.scala:32:10] assign io_issue_ex_rob_id_0 = global_issue_id_1; // @[ReservationStation.scala:26:7, :398:30] wire _issue_entry_WIRE_285; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_143_q; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_is_config; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_opa_valid; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_opa_bits_start_is_acc_addr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_opa_bits_start_accumulate; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_opa_bits_start_read_full_acc_row; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_143_opa_bits_start_norm_cmd; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_143_opa_bits_start_garbage; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_opa_bits_start_garbage_bit; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_143_opa_bits_start_data; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_opa_bits_end_is_acc_addr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_opa_bits_end_accumulate; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_opa_bits_end_read_full_acc_row; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_143_opa_bits_end_norm_cmd; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_143_opa_bits_end_garbage; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_opa_bits_end_garbage_bit; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_143_opa_bits_end_data; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_opa_bits_wraps_around; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_opa_is_dst; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_opb_valid; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_opb_bits_start_is_acc_addr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_opb_bits_start_accumulate; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_opb_bits_start_read_full_acc_row; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_143_opb_bits_start_norm_cmd; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_143_opb_bits_start_garbage; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_opb_bits_start_garbage_bit; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_143_opb_bits_start_data; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_opb_bits_end_is_acc_addr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_opb_bits_end_accumulate; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_opb_bits_end_read_full_acc_row; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_143_opb_bits_end_norm_cmd; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_143_opb_bits_end_garbage; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_opb_bits_end_garbage_bit; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_143_opb_bits_end_data; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_opb_bits_wraps_around; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_issued; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_complete_on_issue; // @[Mux.scala:30:73] wire [6:0] _issue_entry_WIRE_143_cmd_cmd_inst_funct; // @[Mux.scala:30:73] assign io_issue_ex_cmd_cmd_inst_funct_0 = issue_entry_1_bits_cmd_cmd_inst_funct; // @[Mux.scala:30:73] wire [4:0] _issue_entry_WIRE_143_cmd_cmd_inst_rs2; // @[Mux.scala:30:73] assign io_issue_ex_cmd_cmd_inst_rs2_0 = issue_entry_1_bits_cmd_cmd_inst_rs2; // @[Mux.scala:30:73] wire [4:0] _issue_entry_WIRE_143_cmd_cmd_inst_rs1; // @[Mux.scala:30:73] assign io_issue_ex_cmd_cmd_inst_rs1_0 = issue_entry_1_bits_cmd_cmd_inst_rs1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_cmd_cmd_inst_xd; // @[Mux.scala:30:73] assign io_issue_ex_cmd_cmd_inst_xd_0 = issue_entry_1_bits_cmd_cmd_inst_xd; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_cmd_cmd_inst_xs1; // @[Mux.scala:30:73] assign io_issue_ex_cmd_cmd_inst_xs1_0 = issue_entry_1_bits_cmd_cmd_inst_xs1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_cmd_cmd_inst_xs2; // @[Mux.scala:30:73] assign io_issue_ex_cmd_cmd_inst_xs2_0 = issue_entry_1_bits_cmd_cmd_inst_xs2; // @[Mux.scala:30:73] wire [4:0] _issue_entry_WIRE_143_cmd_cmd_inst_rd; // @[Mux.scala:30:73] assign io_issue_ex_cmd_cmd_inst_rd_0 = issue_entry_1_bits_cmd_cmd_inst_rd; // @[Mux.scala:30:73] wire [6:0] _issue_entry_WIRE_143_cmd_cmd_inst_opcode; // @[Mux.scala:30:73] assign io_issue_ex_cmd_cmd_inst_opcode_0 = issue_entry_1_bits_cmd_cmd_inst_opcode; // @[Mux.scala:30:73] wire [63:0] _issue_entry_WIRE_143_cmd_cmd_rs1; // @[Mux.scala:30:73] assign io_issue_ex_cmd_cmd_rs1_0 = issue_entry_1_bits_cmd_cmd_rs1; // @[Mux.scala:30:73] wire [63:0] _issue_entry_WIRE_143_cmd_cmd_rs2; // @[Mux.scala:30:73] assign io_issue_ex_cmd_cmd_rs2_0 = issue_entry_1_bits_cmd_cmd_rs2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_cmd_cmd_status_debug; // @[Mux.scala:30:73] assign io_issue_ex_cmd_cmd_status_debug_0 = issue_entry_1_bits_cmd_cmd_status_debug; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_cmd_cmd_status_cease; // @[Mux.scala:30:73] assign io_issue_ex_cmd_cmd_status_cease_0 = issue_entry_1_bits_cmd_cmd_status_cease; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_cmd_cmd_status_wfi; // @[Mux.scala:30:73] assign io_issue_ex_cmd_cmd_status_wfi_0 = issue_entry_1_bits_cmd_cmd_status_wfi; // @[Mux.scala:30:73] wire [31:0] _issue_entry_WIRE_143_cmd_cmd_status_isa; // @[Mux.scala:30:73] assign io_issue_ex_cmd_cmd_status_isa_0 = issue_entry_1_bits_cmd_cmd_status_isa; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_143_cmd_cmd_status_dprv; // @[Mux.scala:30:73] assign io_issue_ex_cmd_cmd_status_dprv_0 = issue_entry_1_bits_cmd_cmd_status_dprv; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_cmd_cmd_status_dv; // @[Mux.scala:30:73] assign io_issue_ex_cmd_cmd_status_dv_0 = issue_entry_1_bits_cmd_cmd_status_dv; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_143_cmd_cmd_status_prv; // @[Mux.scala:30:73] assign io_issue_ex_cmd_cmd_status_prv_0 = issue_entry_1_bits_cmd_cmd_status_prv; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_cmd_cmd_status_v; // @[Mux.scala:30:73] assign io_issue_ex_cmd_cmd_status_v_0 = issue_entry_1_bits_cmd_cmd_status_v; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_cmd_cmd_status_sd; // @[Mux.scala:30:73] assign io_issue_ex_cmd_cmd_status_sd_0 = issue_entry_1_bits_cmd_cmd_status_sd; // @[Mux.scala:30:73] wire [22:0] _issue_entry_WIRE_143_cmd_cmd_status_zero2; // @[Mux.scala:30:73] assign io_issue_ex_cmd_cmd_status_zero2_0 = issue_entry_1_bits_cmd_cmd_status_zero2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_cmd_cmd_status_mpv; // @[Mux.scala:30:73] assign io_issue_ex_cmd_cmd_status_mpv_0 = issue_entry_1_bits_cmd_cmd_status_mpv; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_cmd_cmd_status_gva; // @[Mux.scala:30:73] assign io_issue_ex_cmd_cmd_status_gva_0 = issue_entry_1_bits_cmd_cmd_status_gva; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_cmd_cmd_status_mbe; // @[Mux.scala:30:73] assign io_issue_ex_cmd_cmd_status_mbe_0 = issue_entry_1_bits_cmd_cmd_status_mbe; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_cmd_cmd_status_sbe; // @[Mux.scala:30:73] assign io_issue_ex_cmd_cmd_status_sbe_0 = issue_entry_1_bits_cmd_cmd_status_sbe; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_143_cmd_cmd_status_sxl; // @[Mux.scala:30:73] assign io_issue_ex_cmd_cmd_status_sxl_0 = issue_entry_1_bits_cmd_cmd_status_sxl; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_143_cmd_cmd_status_uxl; // @[Mux.scala:30:73] assign io_issue_ex_cmd_cmd_status_uxl_0 = issue_entry_1_bits_cmd_cmd_status_uxl; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_cmd_cmd_status_sd_rv32; // @[Mux.scala:30:73] assign io_issue_ex_cmd_cmd_status_sd_rv32_0 = issue_entry_1_bits_cmd_cmd_status_sd_rv32; // @[Mux.scala:30:73] wire [7:0] _issue_entry_WIRE_143_cmd_cmd_status_zero1; // @[Mux.scala:30:73] assign io_issue_ex_cmd_cmd_status_zero1_0 = issue_entry_1_bits_cmd_cmd_status_zero1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_cmd_cmd_status_tsr; // @[Mux.scala:30:73] assign io_issue_ex_cmd_cmd_status_tsr_0 = issue_entry_1_bits_cmd_cmd_status_tsr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_cmd_cmd_status_tw; // @[Mux.scala:30:73] assign io_issue_ex_cmd_cmd_status_tw_0 = issue_entry_1_bits_cmd_cmd_status_tw; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_cmd_cmd_status_tvm; // @[Mux.scala:30:73] assign io_issue_ex_cmd_cmd_status_tvm_0 = issue_entry_1_bits_cmd_cmd_status_tvm; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_cmd_cmd_status_mxr; // @[Mux.scala:30:73] assign io_issue_ex_cmd_cmd_status_mxr_0 = issue_entry_1_bits_cmd_cmd_status_mxr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_cmd_cmd_status_sum; // @[Mux.scala:30:73] assign io_issue_ex_cmd_cmd_status_sum_0 = issue_entry_1_bits_cmd_cmd_status_sum; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_cmd_cmd_status_mprv; // @[Mux.scala:30:73] assign io_issue_ex_cmd_cmd_status_mprv_0 = issue_entry_1_bits_cmd_cmd_status_mprv; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_143_cmd_cmd_status_xs; // @[Mux.scala:30:73] assign io_issue_ex_cmd_cmd_status_xs_0 = issue_entry_1_bits_cmd_cmd_status_xs; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_143_cmd_cmd_status_fs; // @[Mux.scala:30:73] assign io_issue_ex_cmd_cmd_status_fs_0 = issue_entry_1_bits_cmd_cmd_status_fs; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_143_cmd_cmd_status_mpp; // @[Mux.scala:30:73] assign io_issue_ex_cmd_cmd_status_mpp_0 = issue_entry_1_bits_cmd_cmd_status_mpp; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_143_cmd_cmd_status_vs; // @[Mux.scala:30:73] assign io_issue_ex_cmd_cmd_status_vs_0 = issue_entry_1_bits_cmd_cmd_status_vs; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_cmd_cmd_status_spp; // @[Mux.scala:30:73] assign io_issue_ex_cmd_cmd_status_spp_0 = issue_entry_1_bits_cmd_cmd_status_spp; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_cmd_cmd_status_mpie; // @[Mux.scala:30:73] assign io_issue_ex_cmd_cmd_status_mpie_0 = issue_entry_1_bits_cmd_cmd_status_mpie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_cmd_cmd_status_ube; // @[Mux.scala:30:73] assign io_issue_ex_cmd_cmd_status_ube_0 = issue_entry_1_bits_cmd_cmd_status_ube; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_cmd_cmd_status_spie; // @[Mux.scala:30:73] assign io_issue_ex_cmd_cmd_status_spie_0 = issue_entry_1_bits_cmd_cmd_status_spie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_cmd_cmd_status_upie; // @[Mux.scala:30:73] assign io_issue_ex_cmd_cmd_status_upie_0 = issue_entry_1_bits_cmd_cmd_status_upie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_cmd_cmd_status_mie; // @[Mux.scala:30:73] assign io_issue_ex_cmd_cmd_status_mie_0 = issue_entry_1_bits_cmd_cmd_status_mie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_cmd_cmd_status_hie; // @[Mux.scala:30:73] assign io_issue_ex_cmd_cmd_status_hie_0 = issue_entry_1_bits_cmd_cmd_status_hie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_cmd_cmd_status_sie; // @[Mux.scala:30:73] assign io_issue_ex_cmd_cmd_status_sie_0 = issue_entry_1_bits_cmd_cmd_status_sie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_cmd_cmd_status_uie; // @[Mux.scala:30:73] assign io_issue_ex_cmd_cmd_status_uie_0 = issue_entry_1_bits_cmd_cmd_status_uie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_cmd_rob_id_valid; // @[Mux.scala:30:73] assign io_issue_ex_cmd_rob_id_valid = issue_entry_1_bits_cmd_rob_id_valid; // @[Mux.scala:30:73] wire [5:0] _issue_entry_WIRE_143_cmd_rob_id_bits; // @[Mux.scala:30:73] assign io_issue_ex_cmd_rob_id_bits = issue_entry_1_bits_cmd_rob_id_bits; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_cmd_from_matmul_fsm; // @[Mux.scala:30:73] assign io_issue_ex_cmd_from_matmul_fsm_0 = issue_entry_1_bits_cmd_from_matmul_fsm; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_cmd_from_conv_fsm; // @[Mux.scala:30:73] assign io_issue_ex_cmd_from_conv_fsm_0 = issue_entry_1_bits_cmd_from_conv_fsm; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_deps_ld_0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_deps_ld_1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_deps_ld_2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_deps_ld_3; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_deps_ld_4; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_deps_ld_5; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_deps_ld_6; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_deps_ld_7; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_deps_ex_0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_deps_ex_1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_deps_ex_2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_deps_ex_3; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_deps_ex_4; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_deps_ex_5; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_deps_ex_6; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_deps_ex_7; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_deps_ex_8; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_deps_ex_9; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_deps_ex_10; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_deps_ex_11; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_deps_ex_12; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_deps_ex_13; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_deps_ex_14; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_deps_ex_15; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_deps_st_0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_deps_st_1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_deps_st_2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_143_deps_st_3; // @[Mux.scala:30:73] wire [31:0] _issue_entry_WIRE_143_allocated_at; // @[Mux.scala:30:73] wire issue_entry_1_bits_opa_bits_start_is_acc_addr; // @[Mux.scala:30:73] wire issue_entry_1_bits_opa_bits_start_accumulate; // @[Mux.scala:30:73] wire issue_entry_1_bits_opa_bits_start_read_full_acc_row; // @[Mux.scala:30:73] wire [2:0] issue_entry_1_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73] wire [10:0] issue_entry_1_bits_opa_bits_start_garbage; // @[Mux.scala:30:73] wire issue_entry_1_bits_opa_bits_start_garbage_bit; // @[Mux.scala:30:73] wire [13:0] issue_entry_1_bits_opa_bits_start_data; // @[Mux.scala:30:73] wire issue_entry_1_bits_opa_bits_end_is_acc_addr; // @[Mux.scala:30:73] wire issue_entry_1_bits_opa_bits_end_accumulate; // @[Mux.scala:30:73] wire issue_entry_1_bits_opa_bits_end_read_full_acc_row; // @[Mux.scala:30:73] wire [2:0] issue_entry_1_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73] wire [10:0] issue_entry_1_bits_opa_bits_end_garbage; // @[Mux.scala:30:73] wire issue_entry_1_bits_opa_bits_end_garbage_bit; // @[Mux.scala:30:73] wire [13:0] issue_entry_1_bits_opa_bits_end_data; // @[Mux.scala:30:73] wire issue_entry_1_bits_opa_bits_wraps_around; // @[Mux.scala:30:73] wire issue_entry_1_bits_opa_valid; // @[Mux.scala:30:73] wire issue_entry_1_bits_opb_bits_start_is_acc_addr; // @[Mux.scala:30:73] wire issue_entry_1_bits_opb_bits_start_accumulate; // @[Mux.scala:30:73] wire issue_entry_1_bits_opb_bits_start_read_full_acc_row; // @[Mux.scala:30:73] wire [2:0] issue_entry_1_bits_opb_bits_start_norm_cmd; // @[Mux.scala:30:73] wire [10:0] issue_entry_1_bits_opb_bits_start_garbage; // @[Mux.scala:30:73] wire issue_entry_1_bits_opb_bits_start_garbage_bit; // @[Mux.scala:30:73] wire [13:0] issue_entry_1_bits_opb_bits_start_data; // @[Mux.scala:30:73] wire issue_entry_1_bits_opb_bits_end_is_acc_addr; // @[Mux.scala:30:73] wire issue_entry_1_bits_opb_bits_end_accumulate; // @[Mux.scala:30:73] wire issue_entry_1_bits_opb_bits_end_read_full_acc_row; // @[Mux.scala:30:73] wire [2:0] issue_entry_1_bits_opb_bits_end_norm_cmd; // @[Mux.scala:30:73] wire [10:0] issue_entry_1_bits_opb_bits_end_garbage; // @[Mux.scala:30:73] wire issue_entry_1_bits_opb_bits_end_garbage_bit; // @[Mux.scala:30:73] wire [13:0] issue_entry_1_bits_opb_bits_end_data; // @[Mux.scala:30:73] wire issue_entry_1_bits_opb_bits_wraps_around; // @[Mux.scala:30:73] wire issue_entry_1_bits_opb_valid; // @[Mux.scala:30:73] wire issue_entry_1_bits_deps_ld_0; // @[Mux.scala:30:73] wire issue_entry_1_bits_deps_ld_1; // @[Mux.scala:30:73] wire issue_entry_1_bits_deps_ld_2; // @[Mux.scala:30:73] wire issue_entry_1_bits_deps_ld_3; // @[Mux.scala:30:73] wire issue_entry_1_bits_deps_ld_4; // @[Mux.scala:30:73] wire issue_entry_1_bits_deps_ld_5; // @[Mux.scala:30:73] wire issue_entry_1_bits_deps_ld_6; // @[Mux.scala:30:73] wire issue_entry_1_bits_deps_ld_7; // @[Mux.scala:30:73] wire issue_entry_1_bits_deps_ex_0; // @[Mux.scala:30:73] wire issue_entry_1_bits_deps_ex_1; // @[Mux.scala:30:73] wire issue_entry_1_bits_deps_ex_2; // @[Mux.scala:30:73] wire issue_entry_1_bits_deps_ex_3; // @[Mux.scala:30:73] wire issue_entry_1_bits_deps_ex_4; // @[Mux.scala:30:73] wire issue_entry_1_bits_deps_ex_5; // @[Mux.scala:30:73] wire issue_entry_1_bits_deps_ex_6; // @[Mux.scala:30:73] wire issue_entry_1_bits_deps_ex_7; // @[Mux.scala:30:73] wire issue_entry_1_bits_deps_ex_8; // @[Mux.scala:30:73] wire issue_entry_1_bits_deps_ex_9; // @[Mux.scala:30:73] wire issue_entry_1_bits_deps_ex_10; // @[Mux.scala:30:73] wire issue_entry_1_bits_deps_ex_11; // @[Mux.scala:30:73] wire issue_entry_1_bits_deps_ex_12; // @[Mux.scala:30:73] wire issue_entry_1_bits_deps_ex_13; // @[Mux.scala:30:73] wire issue_entry_1_bits_deps_ex_14; // @[Mux.scala:30:73] wire issue_entry_1_bits_deps_ex_15; // @[Mux.scala:30:73] wire issue_entry_1_bits_deps_st_0; // @[Mux.scala:30:73] wire issue_entry_1_bits_deps_st_1; // @[Mux.scala:30:73] wire issue_entry_1_bits_deps_st_2; // @[Mux.scala:30:73] wire issue_entry_1_bits_deps_st_3; // @[Mux.scala:30:73] wire [1:0] issue_entry_1_bits_q; // @[Mux.scala:30:73] wire issue_entry_1_bits_is_config; // @[Mux.scala:30:73] wire issue_entry_1_bits_opa_is_dst; // @[Mux.scala:30:73] wire issue_entry_1_bits_issued; // @[Mux.scala:30:73] wire issue_entry_1_bits_complete_on_issue; // @[Mux.scala:30:73] wire [31:0] issue_entry_1_bits_allocated_at; // @[Mux.scala:30:73] wire issue_entry_1_valid; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_284; // @[Mux.scala:30:73] assign issue_entry_1_bits_q = _issue_entry_WIRE_143_q; // @[Mux.scala:30:73] wire _issue_entry_WIRE_283; // @[Mux.scala:30:73] assign issue_entry_1_bits_is_config = _issue_entry_WIRE_143_is_config; // @[Mux.scala:30:73] wire _issue_entry_WIRE_259_valid; // @[Mux.scala:30:73] assign issue_entry_1_bits_opa_valid = _issue_entry_WIRE_143_opa_valid; // @[Mux.scala:30:73] wire _issue_entry_WIRE_259_bits_start_is_acc_addr; // @[Mux.scala:30:73] assign issue_entry_1_bits_opa_bits_start_is_acc_addr = _issue_entry_WIRE_143_opa_bits_start_is_acc_addr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_259_bits_start_accumulate; // @[Mux.scala:30:73] assign issue_entry_1_bits_opa_bits_start_accumulate = _issue_entry_WIRE_143_opa_bits_start_accumulate; // @[Mux.scala:30:73] wire _issue_entry_WIRE_259_bits_start_read_full_acc_row; // @[Mux.scala:30:73] assign issue_entry_1_bits_opa_bits_start_read_full_acc_row = _issue_entry_WIRE_143_opa_bits_start_read_full_acc_row; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_259_bits_start_norm_cmd; // @[Mux.scala:30:73] assign issue_entry_1_bits_opa_bits_start_norm_cmd = _issue_entry_WIRE_143_opa_bits_start_norm_cmd; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_259_bits_start_garbage; // @[Mux.scala:30:73] assign issue_entry_1_bits_opa_bits_start_garbage = _issue_entry_WIRE_143_opa_bits_start_garbage; // @[Mux.scala:30:73] wire _issue_entry_WIRE_259_bits_start_garbage_bit; // @[Mux.scala:30:73] assign issue_entry_1_bits_opa_bits_start_garbage_bit = _issue_entry_WIRE_143_opa_bits_start_garbage_bit; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_259_bits_start_data; // @[Mux.scala:30:73] assign issue_entry_1_bits_opa_bits_start_data = _issue_entry_WIRE_143_opa_bits_start_data; // @[Mux.scala:30:73] wire _issue_entry_WIRE_259_bits_end_is_acc_addr; // @[Mux.scala:30:73] assign issue_entry_1_bits_opa_bits_end_is_acc_addr = _issue_entry_WIRE_143_opa_bits_end_is_acc_addr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_259_bits_end_accumulate; // @[Mux.scala:30:73] assign issue_entry_1_bits_opa_bits_end_accumulate = _issue_entry_WIRE_143_opa_bits_end_accumulate; // @[Mux.scala:30:73] wire _issue_entry_WIRE_259_bits_end_read_full_acc_row; // @[Mux.scala:30:73] assign issue_entry_1_bits_opa_bits_end_read_full_acc_row = _issue_entry_WIRE_143_opa_bits_end_read_full_acc_row; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_259_bits_end_norm_cmd; // @[Mux.scala:30:73] assign issue_entry_1_bits_opa_bits_end_norm_cmd = _issue_entry_WIRE_143_opa_bits_end_norm_cmd; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_259_bits_end_garbage; // @[Mux.scala:30:73] assign issue_entry_1_bits_opa_bits_end_garbage = _issue_entry_WIRE_143_opa_bits_end_garbage; // @[Mux.scala:30:73] wire _issue_entry_WIRE_259_bits_end_garbage_bit; // @[Mux.scala:30:73] assign issue_entry_1_bits_opa_bits_end_garbage_bit = _issue_entry_WIRE_143_opa_bits_end_garbage_bit; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_259_bits_end_data; // @[Mux.scala:30:73] assign issue_entry_1_bits_opa_bits_end_data = _issue_entry_WIRE_143_opa_bits_end_data; // @[Mux.scala:30:73] wire _issue_entry_WIRE_259_bits_wraps_around; // @[Mux.scala:30:73] assign issue_entry_1_bits_opa_bits_wraps_around = _issue_entry_WIRE_143_opa_bits_wraps_around; // @[Mux.scala:30:73] wire _issue_entry_WIRE_258; // @[Mux.scala:30:73] assign issue_entry_1_bits_opa_is_dst = _issue_entry_WIRE_143_opa_is_dst; // @[Mux.scala:30:73] wire _issue_entry_WIRE_234_valid; // @[Mux.scala:30:73] assign issue_entry_1_bits_opb_valid = _issue_entry_WIRE_143_opb_valid; // @[Mux.scala:30:73] wire _issue_entry_WIRE_234_bits_start_is_acc_addr; // @[Mux.scala:30:73] assign issue_entry_1_bits_opb_bits_start_is_acc_addr = _issue_entry_WIRE_143_opb_bits_start_is_acc_addr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_234_bits_start_accumulate; // @[Mux.scala:30:73] assign issue_entry_1_bits_opb_bits_start_accumulate = _issue_entry_WIRE_143_opb_bits_start_accumulate; // @[Mux.scala:30:73] wire _issue_entry_WIRE_234_bits_start_read_full_acc_row; // @[Mux.scala:30:73] assign issue_entry_1_bits_opb_bits_start_read_full_acc_row = _issue_entry_WIRE_143_opb_bits_start_read_full_acc_row; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_234_bits_start_norm_cmd; // @[Mux.scala:30:73] assign issue_entry_1_bits_opb_bits_start_norm_cmd = _issue_entry_WIRE_143_opb_bits_start_norm_cmd; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_234_bits_start_garbage; // @[Mux.scala:30:73] assign issue_entry_1_bits_opb_bits_start_garbage = _issue_entry_WIRE_143_opb_bits_start_garbage; // @[Mux.scala:30:73] wire _issue_entry_WIRE_234_bits_start_garbage_bit; // @[Mux.scala:30:73] assign issue_entry_1_bits_opb_bits_start_garbage_bit = _issue_entry_WIRE_143_opb_bits_start_garbage_bit; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_234_bits_start_data; // @[Mux.scala:30:73] assign issue_entry_1_bits_opb_bits_start_data = _issue_entry_WIRE_143_opb_bits_start_data; // @[Mux.scala:30:73] wire _issue_entry_WIRE_234_bits_end_is_acc_addr; // @[Mux.scala:30:73] assign issue_entry_1_bits_opb_bits_end_is_acc_addr = _issue_entry_WIRE_143_opb_bits_end_is_acc_addr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_234_bits_end_accumulate; // @[Mux.scala:30:73] assign issue_entry_1_bits_opb_bits_end_accumulate = _issue_entry_WIRE_143_opb_bits_end_accumulate; // @[Mux.scala:30:73] wire _issue_entry_WIRE_234_bits_end_read_full_acc_row; // @[Mux.scala:30:73] assign issue_entry_1_bits_opb_bits_end_read_full_acc_row = _issue_entry_WIRE_143_opb_bits_end_read_full_acc_row; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_234_bits_end_norm_cmd; // @[Mux.scala:30:73] assign issue_entry_1_bits_opb_bits_end_norm_cmd = _issue_entry_WIRE_143_opb_bits_end_norm_cmd; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_234_bits_end_garbage; // @[Mux.scala:30:73] assign issue_entry_1_bits_opb_bits_end_garbage = _issue_entry_WIRE_143_opb_bits_end_garbage; // @[Mux.scala:30:73] wire _issue_entry_WIRE_234_bits_end_garbage_bit; // @[Mux.scala:30:73] assign issue_entry_1_bits_opb_bits_end_garbage_bit = _issue_entry_WIRE_143_opb_bits_end_garbage_bit; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_234_bits_end_data; // @[Mux.scala:30:73] assign issue_entry_1_bits_opb_bits_end_data = _issue_entry_WIRE_143_opb_bits_end_data; // @[Mux.scala:30:73] wire _issue_entry_WIRE_234_bits_wraps_around; // @[Mux.scala:30:73] assign issue_entry_1_bits_opb_bits_wraps_around = _issue_entry_WIRE_143_opb_bits_wraps_around; // @[Mux.scala:30:73] wire _issue_entry_WIRE_233; // @[Mux.scala:30:73] assign issue_entry_1_bits_issued = _issue_entry_WIRE_143_issued; // @[Mux.scala:30:73] wire _issue_entry_WIRE_232; // @[Mux.scala:30:73] assign issue_entry_1_bits_complete_on_issue = _issue_entry_WIRE_143_complete_on_issue; // @[Mux.scala:30:73] wire [6:0] _issue_entry_WIRE_176_cmd_inst_funct; // @[Mux.scala:30:73] assign issue_entry_1_bits_cmd_cmd_inst_funct = _issue_entry_WIRE_143_cmd_cmd_inst_funct; // @[Mux.scala:30:73] wire [4:0] _issue_entry_WIRE_176_cmd_inst_rs2; // @[Mux.scala:30:73] assign issue_entry_1_bits_cmd_cmd_inst_rs2 = _issue_entry_WIRE_143_cmd_cmd_inst_rs2; // @[Mux.scala:30:73] wire [4:0] _issue_entry_WIRE_176_cmd_inst_rs1; // @[Mux.scala:30:73] assign issue_entry_1_bits_cmd_cmd_inst_rs1 = _issue_entry_WIRE_143_cmd_cmd_inst_rs1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_176_cmd_inst_xd; // @[Mux.scala:30:73] assign issue_entry_1_bits_cmd_cmd_inst_xd = _issue_entry_WIRE_143_cmd_cmd_inst_xd; // @[Mux.scala:30:73] wire _issue_entry_WIRE_176_cmd_inst_xs1; // @[Mux.scala:30:73] assign issue_entry_1_bits_cmd_cmd_inst_xs1 = _issue_entry_WIRE_143_cmd_cmd_inst_xs1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_176_cmd_inst_xs2; // @[Mux.scala:30:73] assign issue_entry_1_bits_cmd_cmd_inst_xs2 = _issue_entry_WIRE_143_cmd_cmd_inst_xs2; // @[Mux.scala:30:73] wire [4:0] _issue_entry_WIRE_176_cmd_inst_rd; // @[Mux.scala:30:73] assign issue_entry_1_bits_cmd_cmd_inst_rd = _issue_entry_WIRE_143_cmd_cmd_inst_rd; // @[Mux.scala:30:73] wire [6:0] _issue_entry_WIRE_176_cmd_inst_opcode; // @[Mux.scala:30:73] assign issue_entry_1_bits_cmd_cmd_inst_opcode = _issue_entry_WIRE_143_cmd_cmd_inst_opcode; // @[Mux.scala:30:73] wire [63:0] _issue_entry_WIRE_176_cmd_rs1; // @[Mux.scala:30:73] assign issue_entry_1_bits_cmd_cmd_rs1 = _issue_entry_WIRE_143_cmd_cmd_rs1; // @[Mux.scala:30:73] wire [63:0] _issue_entry_WIRE_176_cmd_rs2; // @[Mux.scala:30:73] assign issue_entry_1_bits_cmd_cmd_rs2 = _issue_entry_WIRE_143_cmd_cmd_rs2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_176_cmd_status_debug; // @[Mux.scala:30:73] assign issue_entry_1_bits_cmd_cmd_status_debug = _issue_entry_WIRE_143_cmd_cmd_status_debug; // @[Mux.scala:30:73] wire _issue_entry_WIRE_176_cmd_status_cease; // @[Mux.scala:30:73] assign issue_entry_1_bits_cmd_cmd_status_cease = _issue_entry_WIRE_143_cmd_cmd_status_cease; // @[Mux.scala:30:73] wire _issue_entry_WIRE_176_cmd_status_wfi; // @[Mux.scala:30:73] assign issue_entry_1_bits_cmd_cmd_status_wfi = _issue_entry_WIRE_143_cmd_cmd_status_wfi; // @[Mux.scala:30:73] wire [31:0] _issue_entry_WIRE_176_cmd_status_isa; // @[Mux.scala:30:73] assign issue_entry_1_bits_cmd_cmd_status_isa = _issue_entry_WIRE_143_cmd_cmd_status_isa; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_176_cmd_status_dprv; // @[Mux.scala:30:73] assign issue_entry_1_bits_cmd_cmd_status_dprv = _issue_entry_WIRE_143_cmd_cmd_status_dprv; // @[Mux.scala:30:73] wire _issue_entry_WIRE_176_cmd_status_dv; // @[Mux.scala:30:73] assign issue_entry_1_bits_cmd_cmd_status_dv = _issue_entry_WIRE_143_cmd_cmd_status_dv; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_176_cmd_status_prv; // @[Mux.scala:30:73] assign issue_entry_1_bits_cmd_cmd_status_prv = _issue_entry_WIRE_143_cmd_cmd_status_prv; // @[Mux.scala:30:73] wire _issue_entry_WIRE_176_cmd_status_v; // @[Mux.scala:30:73] assign issue_entry_1_bits_cmd_cmd_status_v = _issue_entry_WIRE_143_cmd_cmd_status_v; // @[Mux.scala:30:73] wire _issue_entry_WIRE_176_cmd_status_sd; // @[Mux.scala:30:73] assign issue_entry_1_bits_cmd_cmd_status_sd = _issue_entry_WIRE_143_cmd_cmd_status_sd; // @[Mux.scala:30:73] wire [22:0] _issue_entry_WIRE_176_cmd_status_zero2; // @[Mux.scala:30:73] assign issue_entry_1_bits_cmd_cmd_status_zero2 = _issue_entry_WIRE_143_cmd_cmd_status_zero2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_176_cmd_status_mpv; // @[Mux.scala:30:73] assign issue_entry_1_bits_cmd_cmd_status_mpv = _issue_entry_WIRE_143_cmd_cmd_status_mpv; // @[Mux.scala:30:73] wire _issue_entry_WIRE_176_cmd_status_gva; // @[Mux.scala:30:73] assign issue_entry_1_bits_cmd_cmd_status_gva = _issue_entry_WIRE_143_cmd_cmd_status_gva; // @[Mux.scala:30:73] wire _issue_entry_WIRE_176_cmd_status_mbe; // @[Mux.scala:30:73] assign issue_entry_1_bits_cmd_cmd_status_mbe = _issue_entry_WIRE_143_cmd_cmd_status_mbe; // @[Mux.scala:30:73] wire _issue_entry_WIRE_176_cmd_status_sbe; // @[Mux.scala:30:73] assign issue_entry_1_bits_cmd_cmd_status_sbe = _issue_entry_WIRE_143_cmd_cmd_status_sbe; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_176_cmd_status_sxl; // @[Mux.scala:30:73] assign issue_entry_1_bits_cmd_cmd_status_sxl = _issue_entry_WIRE_143_cmd_cmd_status_sxl; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_176_cmd_status_uxl; // @[Mux.scala:30:73] assign issue_entry_1_bits_cmd_cmd_status_uxl = _issue_entry_WIRE_143_cmd_cmd_status_uxl; // @[Mux.scala:30:73] wire _issue_entry_WIRE_176_cmd_status_sd_rv32; // @[Mux.scala:30:73] assign issue_entry_1_bits_cmd_cmd_status_sd_rv32 = _issue_entry_WIRE_143_cmd_cmd_status_sd_rv32; // @[Mux.scala:30:73] wire [7:0] _issue_entry_WIRE_176_cmd_status_zero1; // @[Mux.scala:30:73] assign issue_entry_1_bits_cmd_cmd_status_zero1 = _issue_entry_WIRE_143_cmd_cmd_status_zero1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_176_cmd_status_tsr; // @[Mux.scala:30:73] assign issue_entry_1_bits_cmd_cmd_status_tsr = _issue_entry_WIRE_143_cmd_cmd_status_tsr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_176_cmd_status_tw; // @[Mux.scala:30:73] assign issue_entry_1_bits_cmd_cmd_status_tw = _issue_entry_WIRE_143_cmd_cmd_status_tw; // @[Mux.scala:30:73] wire _issue_entry_WIRE_176_cmd_status_tvm; // @[Mux.scala:30:73] assign issue_entry_1_bits_cmd_cmd_status_tvm = _issue_entry_WIRE_143_cmd_cmd_status_tvm; // @[Mux.scala:30:73] wire _issue_entry_WIRE_176_cmd_status_mxr; // @[Mux.scala:30:73] assign issue_entry_1_bits_cmd_cmd_status_mxr = _issue_entry_WIRE_143_cmd_cmd_status_mxr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_176_cmd_status_sum; // @[Mux.scala:30:73] assign issue_entry_1_bits_cmd_cmd_status_sum = _issue_entry_WIRE_143_cmd_cmd_status_sum; // @[Mux.scala:30:73] wire _issue_entry_WIRE_176_cmd_status_mprv; // @[Mux.scala:30:73] assign issue_entry_1_bits_cmd_cmd_status_mprv = _issue_entry_WIRE_143_cmd_cmd_status_mprv; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_176_cmd_status_xs; // @[Mux.scala:30:73] assign issue_entry_1_bits_cmd_cmd_status_xs = _issue_entry_WIRE_143_cmd_cmd_status_xs; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_176_cmd_status_fs; // @[Mux.scala:30:73] assign issue_entry_1_bits_cmd_cmd_status_fs = _issue_entry_WIRE_143_cmd_cmd_status_fs; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_176_cmd_status_mpp; // @[Mux.scala:30:73] assign issue_entry_1_bits_cmd_cmd_status_mpp = _issue_entry_WIRE_143_cmd_cmd_status_mpp; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_176_cmd_status_vs; // @[Mux.scala:30:73] assign issue_entry_1_bits_cmd_cmd_status_vs = _issue_entry_WIRE_143_cmd_cmd_status_vs; // @[Mux.scala:30:73] wire _issue_entry_WIRE_176_cmd_status_spp; // @[Mux.scala:30:73] assign issue_entry_1_bits_cmd_cmd_status_spp = _issue_entry_WIRE_143_cmd_cmd_status_spp; // @[Mux.scala:30:73] wire _issue_entry_WIRE_176_cmd_status_mpie; // @[Mux.scala:30:73] assign issue_entry_1_bits_cmd_cmd_status_mpie = _issue_entry_WIRE_143_cmd_cmd_status_mpie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_176_cmd_status_ube; // @[Mux.scala:30:73] assign issue_entry_1_bits_cmd_cmd_status_ube = _issue_entry_WIRE_143_cmd_cmd_status_ube; // @[Mux.scala:30:73] wire _issue_entry_WIRE_176_cmd_status_spie; // @[Mux.scala:30:73] assign issue_entry_1_bits_cmd_cmd_status_spie = _issue_entry_WIRE_143_cmd_cmd_status_spie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_176_cmd_status_upie; // @[Mux.scala:30:73] assign issue_entry_1_bits_cmd_cmd_status_upie = _issue_entry_WIRE_143_cmd_cmd_status_upie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_176_cmd_status_mie; // @[Mux.scala:30:73] assign issue_entry_1_bits_cmd_cmd_status_mie = _issue_entry_WIRE_143_cmd_cmd_status_mie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_176_cmd_status_hie; // @[Mux.scala:30:73] assign issue_entry_1_bits_cmd_cmd_status_hie = _issue_entry_WIRE_143_cmd_cmd_status_hie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_176_cmd_status_sie; // @[Mux.scala:30:73] assign issue_entry_1_bits_cmd_cmd_status_sie = _issue_entry_WIRE_143_cmd_cmd_status_sie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_176_cmd_status_uie; // @[Mux.scala:30:73] assign issue_entry_1_bits_cmd_cmd_status_uie = _issue_entry_WIRE_143_cmd_cmd_status_uie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_176_rob_id_valid; // @[Mux.scala:30:73] assign issue_entry_1_bits_cmd_rob_id_valid = _issue_entry_WIRE_143_cmd_rob_id_valid; // @[Mux.scala:30:73] wire [5:0] _issue_entry_WIRE_176_rob_id_bits; // @[Mux.scala:30:73] assign issue_entry_1_bits_cmd_rob_id_bits = _issue_entry_WIRE_143_cmd_rob_id_bits; // @[Mux.scala:30:73] wire _issue_entry_WIRE_176_from_matmul_fsm; // @[Mux.scala:30:73] assign issue_entry_1_bits_cmd_from_matmul_fsm = _issue_entry_WIRE_143_cmd_from_matmul_fsm; // @[Mux.scala:30:73] wire _issue_entry_WIRE_176_from_conv_fsm; // @[Mux.scala:30:73] assign issue_entry_1_bits_cmd_from_conv_fsm = _issue_entry_WIRE_143_cmd_from_conv_fsm; // @[Mux.scala:30:73] wire _issue_entry_WIRE_167_0; // @[Mux.scala:30:73] assign issue_entry_1_bits_deps_ld_0 = _issue_entry_WIRE_143_deps_ld_0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_167_1; // @[Mux.scala:30:73] assign issue_entry_1_bits_deps_ld_1 = _issue_entry_WIRE_143_deps_ld_1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_167_2; // @[Mux.scala:30:73] assign issue_entry_1_bits_deps_ld_2 = _issue_entry_WIRE_143_deps_ld_2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_167_3; // @[Mux.scala:30:73] assign issue_entry_1_bits_deps_ld_3 = _issue_entry_WIRE_143_deps_ld_3; // @[Mux.scala:30:73] wire _issue_entry_WIRE_167_4; // @[Mux.scala:30:73] assign issue_entry_1_bits_deps_ld_4 = _issue_entry_WIRE_143_deps_ld_4; // @[Mux.scala:30:73] wire _issue_entry_WIRE_167_5; // @[Mux.scala:30:73] assign issue_entry_1_bits_deps_ld_5 = _issue_entry_WIRE_143_deps_ld_5; // @[Mux.scala:30:73] wire _issue_entry_WIRE_167_6; // @[Mux.scala:30:73] assign issue_entry_1_bits_deps_ld_6 = _issue_entry_WIRE_143_deps_ld_6; // @[Mux.scala:30:73] wire _issue_entry_WIRE_167_7; // @[Mux.scala:30:73] assign issue_entry_1_bits_deps_ld_7 = _issue_entry_WIRE_143_deps_ld_7; // @[Mux.scala:30:73] wire _issue_entry_WIRE_150_0; // @[Mux.scala:30:73] assign issue_entry_1_bits_deps_ex_0 = _issue_entry_WIRE_143_deps_ex_0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_150_1; // @[Mux.scala:30:73] assign issue_entry_1_bits_deps_ex_1 = _issue_entry_WIRE_143_deps_ex_1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_150_2; // @[Mux.scala:30:73] assign issue_entry_1_bits_deps_ex_2 = _issue_entry_WIRE_143_deps_ex_2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_150_3; // @[Mux.scala:30:73] assign issue_entry_1_bits_deps_ex_3 = _issue_entry_WIRE_143_deps_ex_3; // @[Mux.scala:30:73] wire _issue_entry_WIRE_150_4; // @[Mux.scala:30:73] assign issue_entry_1_bits_deps_ex_4 = _issue_entry_WIRE_143_deps_ex_4; // @[Mux.scala:30:73] wire _issue_entry_WIRE_150_5; // @[Mux.scala:30:73] assign issue_entry_1_bits_deps_ex_5 = _issue_entry_WIRE_143_deps_ex_5; // @[Mux.scala:30:73] wire _issue_entry_WIRE_150_6; // @[Mux.scala:30:73] assign issue_entry_1_bits_deps_ex_6 = _issue_entry_WIRE_143_deps_ex_6; // @[Mux.scala:30:73] wire _issue_entry_WIRE_150_7; // @[Mux.scala:30:73] assign issue_entry_1_bits_deps_ex_7 = _issue_entry_WIRE_143_deps_ex_7; // @[Mux.scala:30:73] wire _issue_entry_WIRE_150_8; // @[Mux.scala:30:73] assign issue_entry_1_bits_deps_ex_8 = _issue_entry_WIRE_143_deps_ex_8; // @[Mux.scala:30:73] wire _issue_entry_WIRE_150_9; // @[Mux.scala:30:73] assign issue_entry_1_bits_deps_ex_9 = _issue_entry_WIRE_143_deps_ex_9; // @[Mux.scala:30:73] wire _issue_entry_WIRE_150_10; // @[Mux.scala:30:73] assign issue_entry_1_bits_deps_ex_10 = _issue_entry_WIRE_143_deps_ex_10; // @[Mux.scala:30:73] wire _issue_entry_WIRE_150_11; // @[Mux.scala:30:73] assign issue_entry_1_bits_deps_ex_11 = _issue_entry_WIRE_143_deps_ex_11; // @[Mux.scala:30:73] wire _issue_entry_WIRE_150_12; // @[Mux.scala:30:73] assign issue_entry_1_bits_deps_ex_12 = _issue_entry_WIRE_143_deps_ex_12; // @[Mux.scala:30:73] wire _issue_entry_WIRE_150_13; // @[Mux.scala:30:73] assign issue_entry_1_bits_deps_ex_13 = _issue_entry_WIRE_143_deps_ex_13; // @[Mux.scala:30:73] wire _issue_entry_WIRE_150_14; // @[Mux.scala:30:73] assign issue_entry_1_bits_deps_ex_14 = _issue_entry_WIRE_143_deps_ex_14; // @[Mux.scala:30:73] wire _issue_entry_WIRE_150_15; // @[Mux.scala:30:73] assign issue_entry_1_bits_deps_ex_15 = _issue_entry_WIRE_143_deps_ex_15; // @[Mux.scala:30:73] wire _issue_entry_WIRE_145_0; // @[Mux.scala:30:73] assign issue_entry_1_bits_deps_st_0 = _issue_entry_WIRE_143_deps_st_0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_145_1; // @[Mux.scala:30:73] assign issue_entry_1_bits_deps_st_1 = _issue_entry_WIRE_143_deps_st_1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_145_2; // @[Mux.scala:30:73] assign issue_entry_1_bits_deps_st_2 = _issue_entry_WIRE_143_deps_st_2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_145_3; // @[Mux.scala:30:73] assign issue_entry_1_bits_deps_st_3 = _issue_entry_WIRE_143_deps_st_3; // @[Mux.scala:30:73] wire [31:0] _issue_entry_WIRE_144; // @[Mux.scala:30:73] assign issue_entry_1_bits_allocated_at = _issue_entry_WIRE_143_allocated_at; // @[Mux.scala:30:73] wire [31:0] _issue_entry_T_1802 = issue_sel_0_1 ? entries_ex_0_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_1803 = issue_sel_1_1 ? entries_ex_1_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_1804 = issue_sel_2_1 ? entries_ex_2_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_1805 = issue_sel_3_1 ? entries_ex_3_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_1806 = issue_sel_4_1 ? entries_ex_4_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_1807 = issue_sel_5_1 ? entries_ex_5_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_1808 = issue_sel_6_1 ? entries_ex_6_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_1809 = issue_sel_7_1 ? entries_ex_7_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_1810 = issue_sel_8 ? entries_ex_8_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_1811 = issue_sel_9 ? entries_ex_9_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_1812 = issue_sel_10 ? entries_ex_10_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_1813 = issue_sel_11 ? entries_ex_11_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_1814 = issue_sel_12 ? entries_ex_12_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_1815 = issue_sel_13 ? entries_ex_13_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_1816 = issue_sel_14 ? entries_ex_14_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_1817 = issue_sel_15 ? entries_ex_15_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_1818 = _issue_entry_T_1802 | _issue_entry_T_1803; // @[Mux.scala:30:73] wire [31:0] _issue_entry_T_1819 = _issue_entry_T_1818 | _issue_entry_T_1804; // @[Mux.scala:30:73] wire [31:0] _issue_entry_T_1820 = _issue_entry_T_1819 | _issue_entry_T_1805; // @[Mux.scala:30:73] wire [31:0] _issue_entry_T_1821 = _issue_entry_T_1820 | _issue_entry_T_1806; // @[Mux.scala:30:73] wire [31:0] _issue_entry_T_1822 = _issue_entry_T_1821 | _issue_entry_T_1807; // @[Mux.scala:30:73] wire [31:0] _issue_entry_T_1823 = _issue_entry_T_1822 | _issue_entry_T_1808; // @[Mux.scala:30:73] wire [31:0] _issue_entry_T_1824 = _issue_entry_T_1823 | _issue_entry_T_1809; // @[Mux.scala:30:73] wire [31:0] _issue_entry_T_1825 = _issue_entry_T_1824 | _issue_entry_T_1810; // @[Mux.scala:30:73] wire [31:0] _issue_entry_T_1826 = _issue_entry_T_1825 | _issue_entry_T_1811; // @[Mux.scala:30:73] wire [31:0] _issue_entry_T_1827 = _issue_entry_T_1826 | _issue_entry_T_1812; // @[Mux.scala:30:73] wire [31:0] _issue_entry_T_1828 = _issue_entry_T_1827 | _issue_entry_T_1813; // @[Mux.scala:30:73] wire [31:0] _issue_entry_T_1829 = _issue_entry_T_1828 | _issue_entry_T_1814; // @[Mux.scala:30:73] wire [31:0] _issue_entry_T_1830 = _issue_entry_T_1829 | _issue_entry_T_1815; // @[Mux.scala:30:73] wire [31:0] _issue_entry_T_1831 = _issue_entry_T_1830 | _issue_entry_T_1816; // @[Mux.scala:30:73] wire [31:0] _issue_entry_T_1832 = _issue_entry_T_1831 | _issue_entry_T_1817; // @[Mux.scala:30:73] assign _issue_entry_WIRE_144 = _issue_entry_T_1832; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_allocated_at = _issue_entry_WIRE_144; // @[Mux.scala:30:73] wire _issue_entry_WIRE_146; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_deps_st_0 = _issue_entry_WIRE_145_0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_147; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_deps_st_1 = _issue_entry_WIRE_145_1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_148; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_deps_st_2 = _issue_entry_WIRE_145_2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_149; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_deps_st_3 = _issue_entry_WIRE_145_3; // @[Mux.scala:30:73] wire _issue_entry_T_1833 = issue_sel_0_1 & entries_ex_0_bits_deps_st_0; // @[OneHot.scala:83:30] wire _issue_entry_T_1834 = issue_sel_1_1 & entries_ex_1_bits_deps_st_0; // @[OneHot.scala:83:30] wire _issue_entry_T_1835 = issue_sel_2_1 & entries_ex_2_bits_deps_st_0; // @[OneHot.scala:83:30] wire _issue_entry_T_1836 = issue_sel_3_1 & entries_ex_3_bits_deps_st_0; // @[OneHot.scala:83:30] wire _issue_entry_T_1837 = issue_sel_4_1 & entries_ex_4_bits_deps_st_0; // @[OneHot.scala:83:30] wire _issue_entry_T_1838 = issue_sel_5_1 & entries_ex_5_bits_deps_st_0; // @[OneHot.scala:83:30] wire _issue_entry_T_1839 = issue_sel_6_1 & entries_ex_6_bits_deps_st_0; // @[OneHot.scala:83:30] wire _issue_entry_T_1840 = issue_sel_7_1 & entries_ex_7_bits_deps_st_0; // @[OneHot.scala:83:30] wire _issue_entry_T_1841 = issue_sel_8 & entries_ex_8_bits_deps_st_0; // @[OneHot.scala:83:30] wire _issue_entry_T_1842 = issue_sel_9 & entries_ex_9_bits_deps_st_0; // @[OneHot.scala:83:30] wire _issue_entry_T_1843 = issue_sel_10 & entries_ex_10_bits_deps_st_0; // @[OneHot.scala:83:30] wire _issue_entry_T_1844 = issue_sel_11 & entries_ex_11_bits_deps_st_0; // @[OneHot.scala:83:30] wire _issue_entry_T_1845 = issue_sel_12 & entries_ex_12_bits_deps_st_0; // @[OneHot.scala:83:30] wire _issue_entry_T_1846 = issue_sel_13 & entries_ex_13_bits_deps_st_0; // @[OneHot.scala:83:30] wire _issue_entry_T_1847 = issue_sel_14 & entries_ex_14_bits_deps_st_0; // @[OneHot.scala:83:30] wire _issue_entry_T_1848 = issue_sel_15 & entries_ex_15_bits_deps_st_0; // @[OneHot.scala:83:30] wire _issue_entry_T_1849 = _issue_entry_T_1833 | _issue_entry_T_1834; // @[Mux.scala:30:73] wire _issue_entry_T_1850 = _issue_entry_T_1849 | _issue_entry_T_1835; // @[Mux.scala:30:73] wire _issue_entry_T_1851 = _issue_entry_T_1850 | _issue_entry_T_1836; // @[Mux.scala:30:73] wire _issue_entry_T_1852 = _issue_entry_T_1851 | _issue_entry_T_1837; // @[Mux.scala:30:73] wire _issue_entry_T_1853 = _issue_entry_T_1852 | _issue_entry_T_1838; // @[Mux.scala:30:73] wire _issue_entry_T_1854 = _issue_entry_T_1853 | _issue_entry_T_1839; // @[Mux.scala:30:73] wire _issue_entry_T_1855 = _issue_entry_T_1854 | _issue_entry_T_1840; // @[Mux.scala:30:73] wire _issue_entry_T_1856 = _issue_entry_T_1855 | _issue_entry_T_1841; // @[Mux.scala:30:73] wire _issue_entry_T_1857 = _issue_entry_T_1856 | _issue_entry_T_1842; // @[Mux.scala:30:73] wire _issue_entry_T_1858 = _issue_entry_T_1857 | _issue_entry_T_1843; // @[Mux.scala:30:73] wire _issue_entry_T_1859 = _issue_entry_T_1858 | _issue_entry_T_1844; // @[Mux.scala:30:73] wire _issue_entry_T_1860 = _issue_entry_T_1859 | _issue_entry_T_1845; // @[Mux.scala:30:73] wire _issue_entry_T_1861 = _issue_entry_T_1860 | _issue_entry_T_1846; // @[Mux.scala:30:73] wire _issue_entry_T_1862 = _issue_entry_T_1861 | _issue_entry_T_1847; // @[Mux.scala:30:73] wire _issue_entry_T_1863 = _issue_entry_T_1862 | _issue_entry_T_1848; // @[Mux.scala:30:73] assign _issue_entry_WIRE_146 = _issue_entry_T_1863; // @[Mux.scala:30:73] assign _issue_entry_WIRE_145_0 = _issue_entry_WIRE_146; // @[Mux.scala:30:73] wire _issue_entry_T_1864 = issue_sel_0_1 & entries_ex_0_bits_deps_st_1; // @[OneHot.scala:83:30] wire _issue_entry_T_1865 = issue_sel_1_1 & entries_ex_1_bits_deps_st_1; // @[OneHot.scala:83:30] wire _issue_entry_T_1866 = issue_sel_2_1 & entries_ex_2_bits_deps_st_1; // @[OneHot.scala:83:30] wire _issue_entry_T_1867 = issue_sel_3_1 & entries_ex_3_bits_deps_st_1; // @[OneHot.scala:83:30] wire _issue_entry_T_1868 = issue_sel_4_1 & entries_ex_4_bits_deps_st_1; // @[OneHot.scala:83:30] wire _issue_entry_T_1869 = issue_sel_5_1 & entries_ex_5_bits_deps_st_1; // @[OneHot.scala:83:30] wire _issue_entry_T_1870 = issue_sel_6_1 & entries_ex_6_bits_deps_st_1; // @[OneHot.scala:83:30] wire _issue_entry_T_1871 = issue_sel_7_1 & entries_ex_7_bits_deps_st_1; // @[OneHot.scala:83:30] wire _issue_entry_T_1872 = issue_sel_8 & entries_ex_8_bits_deps_st_1; // @[OneHot.scala:83:30] wire _issue_entry_T_1873 = issue_sel_9 & entries_ex_9_bits_deps_st_1; // @[OneHot.scala:83:30] wire _issue_entry_T_1874 = issue_sel_10 & entries_ex_10_bits_deps_st_1; // @[OneHot.scala:83:30] wire _issue_entry_T_1875 = issue_sel_11 & entries_ex_11_bits_deps_st_1; // @[OneHot.scala:83:30] wire _issue_entry_T_1876 = issue_sel_12 & entries_ex_12_bits_deps_st_1; // @[OneHot.scala:83:30] wire _issue_entry_T_1877 = issue_sel_13 & entries_ex_13_bits_deps_st_1; // @[OneHot.scala:83:30] wire _issue_entry_T_1878 = issue_sel_14 & entries_ex_14_bits_deps_st_1; // @[OneHot.scala:83:30] wire _issue_entry_T_1879 = issue_sel_15 & entries_ex_15_bits_deps_st_1; // @[OneHot.scala:83:30] wire _issue_entry_T_1880 = _issue_entry_T_1864 | _issue_entry_T_1865; // @[Mux.scala:30:73] wire _issue_entry_T_1881 = _issue_entry_T_1880 | _issue_entry_T_1866; // @[Mux.scala:30:73] wire _issue_entry_T_1882 = _issue_entry_T_1881 | _issue_entry_T_1867; // @[Mux.scala:30:73] wire _issue_entry_T_1883 = _issue_entry_T_1882 | _issue_entry_T_1868; // @[Mux.scala:30:73] wire _issue_entry_T_1884 = _issue_entry_T_1883 | _issue_entry_T_1869; // @[Mux.scala:30:73] wire _issue_entry_T_1885 = _issue_entry_T_1884 | _issue_entry_T_1870; // @[Mux.scala:30:73] wire _issue_entry_T_1886 = _issue_entry_T_1885 | _issue_entry_T_1871; // @[Mux.scala:30:73] wire _issue_entry_T_1887 = _issue_entry_T_1886 | _issue_entry_T_1872; // @[Mux.scala:30:73] wire _issue_entry_T_1888 = _issue_entry_T_1887 | _issue_entry_T_1873; // @[Mux.scala:30:73] wire _issue_entry_T_1889 = _issue_entry_T_1888 | _issue_entry_T_1874; // @[Mux.scala:30:73] wire _issue_entry_T_1890 = _issue_entry_T_1889 | _issue_entry_T_1875; // @[Mux.scala:30:73] wire _issue_entry_T_1891 = _issue_entry_T_1890 | _issue_entry_T_1876; // @[Mux.scala:30:73] wire _issue_entry_T_1892 = _issue_entry_T_1891 | _issue_entry_T_1877; // @[Mux.scala:30:73] wire _issue_entry_T_1893 = _issue_entry_T_1892 | _issue_entry_T_1878; // @[Mux.scala:30:73] wire _issue_entry_T_1894 = _issue_entry_T_1893 | _issue_entry_T_1879; // @[Mux.scala:30:73] assign _issue_entry_WIRE_147 = _issue_entry_T_1894; // @[Mux.scala:30:73] assign _issue_entry_WIRE_145_1 = _issue_entry_WIRE_147; // @[Mux.scala:30:73] wire _issue_entry_T_1895 = issue_sel_0_1 & entries_ex_0_bits_deps_st_2; // @[OneHot.scala:83:30] wire _issue_entry_T_1896 = issue_sel_1_1 & entries_ex_1_bits_deps_st_2; // @[OneHot.scala:83:30] wire _issue_entry_T_1897 = issue_sel_2_1 & entries_ex_2_bits_deps_st_2; // @[OneHot.scala:83:30] wire _issue_entry_T_1898 = issue_sel_3_1 & entries_ex_3_bits_deps_st_2; // @[OneHot.scala:83:30] wire _issue_entry_T_1899 = issue_sel_4_1 & entries_ex_4_bits_deps_st_2; // @[OneHot.scala:83:30] wire _issue_entry_T_1900 = issue_sel_5_1 & entries_ex_5_bits_deps_st_2; // @[OneHot.scala:83:30] wire _issue_entry_T_1901 = issue_sel_6_1 & entries_ex_6_bits_deps_st_2; // @[OneHot.scala:83:30] wire _issue_entry_T_1902 = issue_sel_7_1 & entries_ex_7_bits_deps_st_2; // @[OneHot.scala:83:30] wire _issue_entry_T_1903 = issue_sel_8 & entries_ex_8_bits_deps_st_2; // @[OneHot.scala:83:30] wire _issue_entry_T_1904 = issue_sel_9 & entries_ex_9_bits_deps_st_2; // @[OneHot.scala:83:30] wire _issue_entry_T_1905 = issue_sel_10 & entries_ex_10_bits_deps_st_2; // @[OneHot.scala:83:30] wire _issue_entry_T_1906 = issue_sel_11 & entries_ex_11_bits_deps_st_2; // @[OneHot.scala:83:30] wire _issue_entry_T_1907 = issue_sel_12 & entries_ex_12_bits_deps_st_2; // @[OneHot.scala:83:30] wire _issue_entry_T_1908 = issue_sel_13 & entries_ex_13_bits_deps_st_2; // @[OneHot.scala:83:30] wire _issue_entry_T_1909 = issue_sel_14 & entries_ex_14_bits_deps_st_2; // @[OneHot.scala:83:30] wire _issue_entry_T_1910 = issue_sel_15 & entries_ex_15_bits_deps_st_2; // @[OneHot.scala:83:30] wire _issue_entry_T_1911 = _issue_entry_T_1895 | _issue_entry_T_1896; // @[Mux.scala:30:73] wire _issue_entry_T_1912 = _issue_entry_T_1911 | _issue_entry_T_1897; // @[Mux.scala:30:73] wire _issue_entry_T_1913 = _issue_entry_T_1912 | _issue_entry_T_1898; // @[Mux.scala:30:73] wire _issue_entry_T_1914 = _issue_entry_T_1913 | _issue_entry_T_1899; // @[Mux.scala:30:73] wire _issue_entry_T_1915 = _issue_entry_T_1914 | _issue_entry_T_1900; // @[Mux.scala:30:73] wire _issue_entry_T_1916 = _issue_entry_T_1915 | _issue_entry_T_1901; // @[Mux.scala:30:73] wire _issue_entry_T_1917 = _issue_entry_T_1916 | _issue_entry_T_1902; // @[Mux.scala:30:73] wire _issue_entry_T_1918 = _issue_entry_T_1917 | _issue_entry_T_1903; // @[Mux.scala:30:73] wire _issue_entry_T_1919 = _issue_entry_T_1918 | _issue_entry_T_1904; // @[Mux.scala:30:73] wire _issue_entry_T_1920 = _issue_entry_T_1919 | _issue_entry_T_1905; // @[Mux.scala:30:73] wire _issue_entry_T_1921 = _issue_entry_T_1920 | _issue_entry_T_1906; // @[Mux.scala:30:73] wire _issue_entry_T_1922 = _issue_entry_T_1921 | _issue_entry_T_1907; // @[Mux.scala:30:73] wire _issue_entry_T_1923 = _issue_entry_T_1922 | _issue_entry_T_1908; // @[Mux.scala:30:73] wire _issue_entry_T_1924 = _issue_entry_T_1923 | _issue_entry_T_1909; // @[Mux.scala:30:73] wire _issue_entry_T_1925 = _issue_entry_T_1924 | _issue_entry_T_1910; // @[Mux.scala:30:73] assign _issue_entry_WIRE_148 = _issue_entry_T_1925; // @[Mux.scala:30:73] assign _issue_entry_WIRE_145_2 = _issue_entry_WIRE_148; // @[Mux.scala:30:73] wire _issue_entry_T_1926 = issue_sel_0_1 & entries_ex_0_bits_deps_st_3; // @[OneHot.scala:83:30] wire _issue_entry_T_1927 = issue_sel_1_1 & entries_ex_1_bits_deps_st_3; // @[OneHot.scala:83:30] wire _issue_entry_T_1928 = issue_sel_2_1 & entries_ex_2_bits_deps_st_3; // @[OneHot.scala:83:30] wire _issue_entry_T_1929 = issue_sel_3_1 & entries_ex_3_bits_deps_st_3; // @[OneHot.scala:83:30] wire _issue_entry_T_1930 = issue_sel_4_1 & entries_ex_4_bits_deps_st_3; // @[OneHot.scala:83:30] wire _issue_entry_T_1931 = issue_sel_5_1 & entries_ex_5_bits_deps_st_3; // @[OneHot.scala:83:30] wire _issue_entry_T_1932 = issue_sel_6_1 & entries_ex_6_bits_deps_st_3; // @[OneHot.scala:83:30] wire _issue_entry_T_1933 = issue_sel_7_1 & entries_ex_7_bits_deps_st_3; // @[OneHot.scala:83:30] wire _issue_entry_T_1934 = issue_sel_8 & entries_ex_8_bits_deps_st_3; // @[OneHot.scala:83:30] wire _issue_entry_T_1935 = issue_sel_9 & entries_ex_9_bits_deps_st_3; // @[OneHot.scala:83:30] wire _issue_entry_T_1936 = issue_sel_10 & entries_ex_10_bits_deps_st_3; // @[OneHot.scala:83:30] wire _issue_entry_T_1937 = issue_sel_11 & entries_ex_11_bits_deps_st_3; // @[OneHot.scala:83:30] wire _issue_entry_T_1938 = issue_sel_12 & entries_ex_12_bits_deps_st_3; // @[OneHot.scala:83:30] wire _issue_entry_T_1939 = issue_sel_13 & entries_ex_13_bits_deps_st_3; // @[OneHot.scala:83:30] wire _issue_entry_T_1940 = issue_sel_14 & entries_ex_14_bits_deps_st_3; // @[OneHot.scala:83:30] wire _issue_entry_T_1941 = issue_sel_15 & entries_ex_15_bits_deps_st_3; // @[OneHot.scala:83:30] wire _issue_entry_T_1942 = _issue_entry_T_1926 | _issue_entry_T_1927; // @[Mux.scala:30:73] wire _issue_entry_T_1943 = _issue_entry_T_1942 | _issue_entry_T_1928; // @[Mux.scala:30:73] wire _issue_entry_T_1944 = _issue_entry_T_1943 | _issue_entry_T_1929; // @[Mux.scala:30:73] wire _issue_entry_T_1945 = _issue_entry_T_1944 | _issue_entry_T_1930; // @[Mux.scala:30:73] wire _issue_entry_T_1946 = _issue_entry_T_1945 | _issue_entry_T_1931; // @[Mux.scala:30:73] wire _issue_entry_T_1947 = _issue_entry_T_1946 | _issue_entry_T_1932; // @[Mux.scala:30:73] wire _issue_entry_T_1948 = _issue_entry_T_1947 | _issue_entry_T_1933; // @[Mux.scala:30:73] wire _issue_entry_T_1949 = _issue_entry_T_1948 | _issue_entry_T_1934; // @[Mux.scala:30:73] wire _issue_entry_T_1950 = _issue_entry_T_1949 | _issue_entry_T_1935; // @[Mux.scala:30:73] wire _issue_entry_T_1951 = _issue_entry_T_1950 | _issue_entry_T_1936; // @[Mux.scala:30:73] wire _issue_entry_T_1952 = _issue_entry_T_1951 | _issue_entry_T_1937; // @[Mux.scala:30:73] wire _issue_entry_T_1953 = _issue_entry_T_1952 | _issue_entry_T_1938; // @[Mux.scala:30:73] wire _issue_entry_T_1954 = _issue_entry_T_1953 | _issue_entry_T_1939; // @[Mux.scala:30:73] wire _issue_entry_T_1955 = _issue_entry_T_1954 | _issue_entry_T_1940; // @[Mux.scala:30:73] wire _issue_entry_T_1956 = _issue_entry_T_1955 | _issue_entry_T_1941; // @[Mux.scala:30:73] assign _issue_entry_WIRE_149 = _issue_entry_T_1956; // @[Mux.scala:30:73] assign _issue_entry_WIRE_145_3 = _issue_entry_WIRE_149; // @[Mux.scala:30:73] wire _issue_entry_WIRE_151; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_deps_ex_0 = _issue_entry_WIRE_150_0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_152; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_deps_ex_1 = _issue_entry_WIRE_150_1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_153; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_deps_ex_2 = _issue_entry_WIRE_150_2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_154; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_deps_ex_3 = _issue_entry_WIRE_150_3; // @[Mux.scala:30:73] wire _issue_entry_WIRE_155; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_deps_ex_4 = _issue_entry_WIRE_150_4; // @[Mux.scala:30:73] wire _issue_entry_WIRE_156; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_deps_ex_5 = _issue_entry_WIRE_150_5; // @[Mux.scala:30:73] wire _issue_entry_WIRE_157; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_deps_ex_6 = _issue_entry_WIRE_150_6; // @[Mux.scala:30:73] wire _issue_entry_WIRE_158; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_deps_ex_7 = _issue_entry_WIRE_150_7; // @[Mux.scala:30:73] wire _issue_entry_WIRE_159; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_deps_ex_8 = _issue_entry_WIRE_150_8; // @[Mux.scala:30:73] wire _issue_entry_WIRE_160; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_deps_ex_9 = _issue_entry_WIRE_150_9; // @[Mux.scala:30:73] wire _issue_entry_WIRE_161; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_deps_ex_10 = _issue_entry_WIRE_150_10; // @[Mux.scala:30:73] wire _issue_entry_WIRE_162; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_deps_ex_11 = _issue_entry_WIRE_150_11; // @[Mux.scala:30:73] wire _issue_entry_WIRE_163; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_deps_ex_12 = _issue_entry_WIRE_150_12; // @[Mux.scala:30:73] wire _issue_entry_WIRE_164; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_deps_ex_13 = _issue_entry_WIRE_150_13; // @[Mux.scala:30:73] wire _issue_entry_WIRE_165; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_deps_ex_14 = _issue_entry_WIRE_150_14; // @[Mux.scala:30:73] wire _issue_entry_WIRE_166; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_deps_ex_15 = _issue_entry_WIRE_150_15; // @[Mux.scala:30:73] wire _issue_entry_T_1957 = issue_sel_0_1 & entries_ex_0_bits_deps_ex_0; // @[OneHot.scala:83:30] wire _issue_entry_T_1958 = issue_sel_1_1 & entries_ex_1_bits_deps_ex_0; // @[OneHot.scala:83:30] wire _issue_entry_T_1959 = issue_sel_2_1 & entries_ex_2_bits_deps_ex_0; // @[OneHot.scala:83:30] wire _issue_entry_T_1960 = issue_sel_3_1 & entries_ex_3_bits_deps_ex_0; // @[OneHot.scala:83:30] wire _issue_entry_T_1961 = issue_sel_4_1 & entries_ex_4_bits_deps_ex_0; // @[OneHot.scala:83:30] wire _issue_entry_T_1962 = issue_sel_5_1 & entries_ex_5_bits_deps_ex_0; // @[OneHot.scala:83:30] wire _issue_entry_T_1963 = issue_sel_6_1 & entries_ex_6_bits_deps_ex_0; // @[OneHot.scala:83:30] wire _issue_entry_T_1964 = issue_sel_7_1 & entries_ex_7_bits_deps_ex_0; // @[OneHot.scala:83:30] wire _issue_entry_T_1965 = issue_sel_8 & entries_ex_8_bits_deps_ex_0; // @[OneHot.scala:83:30] wire _issue_entry_T_1966 = issue_sel_9 & entries_ex_9_bits_deps_ex_0; // @[OneHot.scala:83:30] wire _issue_entry_T_1967 = issue_sel_10 & entries_ex_10_bits_deps_ex_0; // @[OneHot.scala:83:30] wire _issue_entry_T_1968 = issue_sel_11 & entries_ex_11_bits_deps_ex_0; // @[OneHot.scala:83:30] wire _issue_entry_T_1969 = issue_sel_12 & entries_ex_12_bits_deps_ex_0; // @[OneHot.scala:83:30] wire _issue_entry_T_1970 = issue_sel_13 & entries_ex_13_bits_deps_ex_0; // @[OneHot.scala:83:30] wire _issue_entry_T_1971 = issue_sel_14 & entries_ex_14_bits_deps_ex_0; // @[OneHot.scala:83:30] wire _issue_entry_T_1972 = issue_sel_15 & entries_ex_15_bits_deps_ex_0; // @[OneHot.scala:83:30] wire _issue_entry_T_1973 = _issue_entry_T_1957 | _issue_entry_T_1958; // @[Mux.scala:30:73] wire _issue_entry_T_1974 = _issue_entry_T_1973 | _issue_entry_T_1959; // @[Mux.scala:30:73] wire _issue_entry_T_1975 = _issue_entry_T_1974 | _issue_entry_T_1960; // @[Mux.scala:30:73] wire _issue_entry_T_1976 = _issue_entry_T_1975 | _issue_entry_T_1961; // @[Mux.scala:30:73] wire _issue_entry_T_1977 = _issue_entry_T_1976 | _issue_entry_T_1962; // @[Mux.scala:30:73] wire _issue_entry_T_1978 = _issue_entry_T_1977 | _issue_entry_T_1963; // @[Mux.scala:30:73] wire _issue_entry_T_1979 = _issue_entry_T_1978 | _issue_entry_T_1964; // @[Mux.scala:30:73] wire _issue_entry_T_1980 = _issue_entry_T_1979 | _issue_entry_T_1965; // @[Mux.scala:30:73] wire _issue_entry_T_1981 = _issue_entry_T_1980 | _issue_entry_T_1966; // @[Mux.scala:30:73] wire _issue_entry_T_1982 = _issue_entry_T_1981 | _issue_entry_T_1967; // @[Mux.scala:30:73] wire _issue_entry_T_1983 = _issue_entry_T_1982 | _issue_entry_T_1968; // @[Mux.scala:30:73] wire _issue_entry_T_1984 = _issue_entry_T_1983 | _issue_entry_T_1969; // @[Mux.scala:30:73] wire _issue_entry_T_1985 = _issue_entry_T_1984 | _issue_entry_T_1970; // @[Mux.scala:30:73] wire _issue_entry_T_1986 = _issue_entry_T_1985 | _issue_entry_T_1971; // @[Mux.scala:30:73] wire _issue_entry_T_1987 = _issue_entry_T_1986 | _issue_entry_T_1972; // @[Mux.scala:30:73] assign _issue_entry_WIRE_151 = _issue_entry_T_1987; // @[Mux.scala:30:73] assign _issue_entry_WIRE_150_0 = _issue_entry_WIRE_151; // @[Mux.scala:30:73] wire _issue_entry_T_1988 = issue_sel_0_1 & entries_ex_0_bits_deps_ex_1; // @[OneHot.scala:83:30] wire _issue_entry_T_1989 = issue_sel_1_1 & entries_ex_1_bits_deps_ex_1; // @[OneHot.scala:83:30] wire _issue_entry_T_1990 = issue_sel_2_1 & entries_ex_2_bits_deps_ex_1; // @[OneHot.scala:83:30] wire _issue_entry_T_1991 = issue_sel_3_1 & entries_ex_3_bits_deps_ex_1; // @[OneHot.scala:83:30] wire _issue_entry_T_1992 = issue_sel_4_1 & entries_ex_4_bits_deps_ex_1; // @[OneHot.scala:83:30] wire _issue_entry_T_1993 = issue_sel_5_1 & entries_ex_5_bits_deps_ex_1; // @[OneHot.scala:83:30] wire _issue_entry_T_1994 = issue_sel_6_1 & entries_ex_6_bits_deps_ex_1; // @[OneHot.scala:83:30] wire _issue_entry_T_1995 = issue_sel_7_1 & entries_ex_7_bits_deps_ex_1; // @[OneHot.scala:83:30] wire _issue_entry_T_1996 = issue_sel_8 & entries_ex_8_bits_deps_ex_1; // @[OneHot.scala:83:30] wire _issue_entry_T_1997 = issue_sel_9 & entries_ex_9_bits_deps_ex_1; // @[OneHot.scala:83:30] wire _issue_entry_T_1998 = issue_sel_10 & entries_ex_10_bits_deps_ex_1; // @[OneHot.scala:83:30] wire _issue_entry_T_1999 = issue_sel_11 & entries_ex_11_bits_deps_ex_1; // @[OneHot.scala:83:30] wire _issue_entry_T_2000 = issue_sel_12 & entries_ex_12_bits_deps_ex_1; // @[OneHot.scala:83:30] wire _issue_entry_T_2001 = issue_sel_13 & entries_ex_13_bits_deps_ex_1; // @[OneHot.scala:83:30] wire _issue_entry_T_2002 = issue_sel_14 & entries_ex_14_bits_deps_ex_1; // @[OneHot.scala:83:30] wire _issue_entry_T_2003 = issue_sel_15 & entries_ex_15_bits_deps_ex_1; // @[OneHot.scala:83:30] wire _issue_entry_T_2004 = _issue_entry_T_1988 | _issue_entry_T_1989; // @[Mux.scala:30:73] wire _issue_entry_T_2005 = _issue_entry_T_2004 | _issue_entry_T_1990; // @[Mux.scala:30:73] wire _issue_entry_T_2006 = _issue_entry_T_2005 | _issue_entry_T_1991; // @[Mux.scala:30:73] wire _issue_entry_T_2007 = _issue_entry_T_2006 | _issue_entry_T_1992; // @[Mux.scala:30:73] wire _issue_entry_T_2008 = _issue_entry_T_2007 | _issue_entry_T_1993; // @[Mux.scala:30:73] wire _issue_entry_T_2009 = _issue_entry_T_2008 | _issue_entry_T_1994; // @[Mux.scala:30:73] wire _issue_entry_T_2010 = _issue_entry_T_2009 | _issue_entry_T_1995; // @[Mux.scala:30:73] wire _issue_entry_T_2011 = _issue_entry_T_2010 | _issue_entry_T_1996; // @[Mux.scala:30:73] wire _issue_entry_T_2012 = _issue_entry_T_2011 | _issue_entry_T_1997; // @[Mux.scala:30:73] wire _issue_entry_T_2013 = _issue_entry_T_2012 | _issue_entry_T_1998; // @[Mux.scala:30:73] wire _issue_entry_T_2014 = _issue_entry_T_2013 | _issue_entry_T_1999; // @[Mux.scala:30:73] wire _issue_entry_T_2015 = _issue_entry_T_2014 | _issue_entry_T_2000; // @[Mux.scala:30:73] wire _issue_entry_T_2016 = _issue_entry_T_2015 | _issue_entry_T_2001; // @[Mux.scala:30:73] wire _issue_entry_T_2017 = _issue_entry_T_2016 | _issue_entry_T_2002; // @[Mux.scala:30:73] wire _issue_entry_T_2018 = _issue_entry_T_2017 | _issue_entry_T_2003; // @[Mux.scala:30:73] assign _issue_entry_WIRE_152 = _issue_entry_T_2018; // @[Mux.scala:30:73] assign _issue_entry_WIRE_150_1 = _issue_entry_WIRE_152; // @[Mux.scala:30:73] wire _issue_entry_T_2019 = issue_sel_0_1 & entries_ex_0_bits_deps_ex_2; // @[OneHot.scala:83:30] wire _issue_entry_T_2020 = issue_sel_1_1 & entries_ex_1_bits_deps_ex_2; // @[OneHot.scala:83:30] wire _issue_entry_T_2021 = issue_sel_2_1 & entries_ex_2_bits_deps_ex_2; // @[OneHot.scala:83:30] wire _issue_entry_T_2022 = issue_sel_3_1 & entries_ex_3_bits_deps_ex_2; // @[OneHot.scala:83:30] wire _issue_entry_T_2023 = issue_sel_4_1 & entries_ex_4_bits_deps_ex_2; // @[OneHot.scala:83:30] wire _issue_entry_T_2024 = issue_sel_5_1 & entries_ex_5_bits_deps_ex_2; // @[OneHot.scala:83:30] wire _issue_entry_T_2025 = issue_sel_6_1 & entries_ex_6_bits_deps_ex_2; // @[OneHot.scala:83:30] wire _issue_entry_T_2026 = issue_sel_7_1 & entries_ex_7_bits_deps_ex_2; // @[OneHot.scala:83:30] wire _issue_entry_T_2027 = issue_sel_8 & entries_ex_8_bits_deps_ex_2; // @[OneHot.scala:83:30] wire _issue_entry_T_2028 = issue_sel_9 & entries_ex_9_bits_deps_ex_2; // @[OneHot.scala:83:30] wire _issue_entry_T_2029 = issue_sel_10 & entries_ex_10_bits_deps_ex_2; // @[OneHot.scala:83:30] wire _issue_entry_T_2030 = issue_sel_11 & entries_ex_11_bits_deps_ex_2; // @[OneHot.scala:83:30] wire _issue_entry_T_2031 = issue_sel_12 & entries_ex_12_bits_deps_ex_2; // @[OneHot.scala:83:30] wire _issue_entry_T_2032 = issue_sel_13 & entries_ex_13_bits_deps_ex_2; // @[OneHot.scala:83:30] wire _issue_entry_T_2033 = issue_sel_14 & entries_ex_14_bits_deps_ex_2; // @[OneHot.scala:83:30] wire _issue_entry_T_2034 = issue_sel_15 & entries_ex_15_bits_deps_ex_2; // @[OneHot.scala:83:30] wire _issue_entry_T_2035 = _issue_entry_T_2019 | _issue_entry_T_2020; // @[Mux.scala:30:73] wire _issue_entry_T_2036 = _issue_entry_T_2035 | _issue_entry_T_2021; // @[Mux.scala:30:73] wire _issue_entry_T_2037 = _issue_entry_T_2036 | _issue_entry_T_2022; // @[Mux.scala:30:73] wire _issue_entry_T_2038 = _issue_entry_T_2037 | _issue_entry_T_2023; // @[Mux.scala:30:73] wire _issue_entry_T_2039 = _issue_entry_T_2038 | _issue_entry_T_2024; // @[Mux.scala:30:73] wire _issue_entry_T_2040 = _issue_entry_T_2039 | _issue_entry_T_2025; // @[Mux.scala:30:73] wire _issue_entry_T_2041 = _issue_entry_T_2040 | _issue_entry_T_2026; // @[Mux.scala:30:73] wire _issue_entry_T_2042 = _issue_entry_T_2041 | _issue_entry_T_2027; // @[Mux.scala:30:73] wire _issue_entry_T_2043 = _issue_entry_T_2042 | _issue_entry_T_2028; // @[Mux.scala:30:73] wire _issue_entry_T_2044 = _issue_entry_T_2043 | _issue_entry_T_2029; // @[Mux.scala:30:73] wire _issue_entry_T_2045 = _issue_entry_T_2044 | _issue_entry_T_2030; // @[Mux.scala:30:73] wire _issue_entry_T_2046 = _issue_entry_T_2045 | _issue_entry_T_2031; // @[Mux.scala:30:73] wire _issue_entry_T_2047 = _issue_entry_T_2046 | _issue_entry_T_2032; // @[Mux.scala:30:73] wire _issue_entry_T_2048 = _issue_entry_T_2047 | _issue_entry_T_2033; // @[Mux.scala:30:73] wire _issue_entry_T_2049 = _issue_entry_T_2048 | _issue_entry_T_2034; // @[Mux.scala:30:73] assign _issue_entry_WIRE_153 = _issue_entry_T_2049; // @[Mux.scala:30:73] assign _issue_entry_WIRE_150_2 = _issue_entry_WIRE_153; // @[Mux.scala:30:73] wire _issue_entry_T_2050 = issue_sel_0_1 & entries_ex_0_bits_deps_ex_3; // @[OneHot.scala:83:30] wire _issue_entry_T_2051 = issue_sel_1_1 & entries_ex_1_bits_deps_ex_3; // @[OneHot.scala:83:30] wire _issue_entry_T_2052 = issue_sel_2_1 & entries_ex_2_bits_deps_ex_3; // @[OneHot.scala:83:30] wire _issue_entry_T_2053 = issue_sel_3_1 & entries_ex_3_bits_deps_ex_3; // @[OneHot.scala:83:30] wire _issue_entry_T_2054 = issue_sel_4_1 & entries_ex_4_bits_deps_ex_3; // @[OneHot.scala:83:30] wire _issue_entry_T_2055 = issue_sel_5_1 & entries_ex_5_bits_deps_ex_3; // @[OneHot.scala:83:30] wire _issue_entry_T_2056 = issue_sel_6_1 & entries_ex_6_bits_deps_ex_3; // @[OneHot.scala:83:30] wire _issue_entry_T_2057 = issue_sel_7_1 & entries_ex_7_bits_deps_ex_3; // @[OneHot.scala:83:30] wire _issue_entry_T_2058 = issue_sel_8 & entries_ex_8_bits_deps_ex_3; // @[OneHot.scala:83:30] wire _issue_entry_T_2059 = issue_sel_9 & entries_ex_9_bits_deps_ex_3; // @[OneHot.scala:83:30] wire _issue_entry_T_2060 = issue_sel_10 & entries_ex_10_bits_deps_ex_3; // @[OneHot.scala:83:30] wire _issue_entry_T_2061 = issue_sel_11 & entries_ex_11_bits_deps_ex_3; // @[OneHot.scala:83:30] wire _issue_entry_T_2062 = issue_sel_12 & entries_ex_12_bits_deps_ex_3; // @[OneHot.scala:83:30] wire _issue_entry_T_2063 = issue_sel_13 & entries_ex_13_bits_deps_ex_3; // @[OneHot.scala:83:30] wire _issue_entry_T_2064 = issue_sel_14 & entries_ex_14_bits_deps_ex_3; // @[OneHot.scala:83:30] wire _issue_entry_T_2065 = issue_sel_15 & entries_ex_15_bits_deps_ex_3; // @[OneHot.scala:83:30] wire _issue_entry_T_2066 = _issue_entry_T_2050 | _issue_entry_T_2051; // @[Mux.scala:30:73] wire _issue_entry_T_2067 = _issue_entry_T_2066 | _issue_entry_T_2052; // @[Mux.scala:30:73] wire _issue_entry_T_2068 = _issue_entry_T_2067 | _issue_entry_T_2053; // @[Mux.scala:30:73] wire _issue_entry_T_2069 = _issue_entry_T_2068 | _issue_entry_T_2054; // @[Mux.scala:30:73] wire _issue_entry_T_2070 = _issue_entry_T_2069 | _issue_entry_T_2055; // @[Mux.scala:30:73] wire _issue_entry_T_2071 = _issue_entry_T_2070 | _issue_entry_T_2056; // @[Mux.scala:30:73] wire _issue_entry_T_2072 = _issue_entry_T_2071 | _issue_entry_T_2057; // @[Mux.scala:30:73] wire _issue_entry_T_2073 = _issue_entry_T_2072 | _issue_entry_T_2058; // @[Mux.scala:30:73] wire _issue_entry_T_2074 = _issue_entry_T_2073 | _issue_entry_T_2059; // @[Mux.scala:30:73] wire _issue_entry_T_2075 = _issue_entry_T_2074 | _issue_entry_T_2060; // @[Mux.scala:30:73] wire _issue_entry_T_2076 = _issue_entry_T_2075 | _issue_entry_T_2061; // @[Mux.scala:30:73] wire _issue_entry_T_2077 = _issue_entry_T_2076 | _issue_entry_T_2062; // @[Mux.scala:30:73] wire _issue_entry_T_2078 = _issue_entry_T_2077 | _issue_entry_T_2063; // @[Mux.scala:30:73] wire _issue_entry_T_2079 = _issue_entry_T_2078 | _issue_entry_T_2064; // @[Mux.scala:30:73] wire _issue_entry_T_2080 = _issue_entry_T_2079 | _issue_entry_T_2065; // @[Mux.scala:30:73] assign _issue_entry_WIRE_154 = _issue_entry_T_2080; // @[Mux.scala:30:73] assign _issue_entry_WIRE_150_3 = _issue_entry_WIRE_154; // @[Mux.scala:30:73] wire _issue_entry_T_2081 = issue_sel_0_1 & entries_ex_0_bits_deps_ex_4; // @[OneHot.scala:83:30] wire _issue_entry_T_2082 = issue_sel_1_1 & entries_ex_1_bits_deps_ex_4; // @[OneHot.scala:83:30] wire _issue_entry_T_2083 = issue_sel_2_1 & entries_ex_2_bits_deps_ex_4; // @[OneHot.scala:83:30] wire _issue_entry_T_2084 = issue_sel_3_1 & entries_ex_3_bits_deps_ex_4; // @[OneHot.scala:83:30] wire _issue_entry_T_2085 = issue_sel_4_1 & entries_ex_4_bits_deps_ex_4; // @[OneHot.scala:83:30] wire _issue_entry_T_2086 = issue_sel_5_1 & entries_ex_5_bits_deps_ex_4; // @[OneHot.scala:83:30] wire _issue_entry_T_2087 = issue_sel_6_1 & entries_ex_6_bits_deps_ex_4; // @[OneHot.scala:83:30] wire _issue_entry_T_2088 = issue_sel_7_1 & entries_ex_7_bits_deps_ex_4; // @[OneHot.scala:83:30] wire _issue_entry_T_2089 = issue_sel_8 & entries_ex_8_bits_deps_ex_4; // @[OneHot.scala:83:30] wire _issue_entry_T_2090 = issue_sel_9 & entries_ex_9_bits_deps_ex_4; // @[OneHot.scala:83:30] wire _issue_entry_T_2091 = issue_sel_10 & entries_ex_10_bits_deps_ex_4; // @[OneHot.scala:83:30] wire _issue_entry_T_2092 = issue_sel_11 & entries_ex_11_bits_deps_ex_4; // @[OneHot.scala:83:30] wire _issue_entry_T_2093 = issue_sel_12 & entries_ex_12_bits_deps_ex_4; // @[OneHot.scala:83:30] wire _issue_entry_T_2094 = issue_sel_13 & entries_ex_13_bits_deps_ex_4; // @[OneHot.scala:83:30] wire _issue_entry_T_2095 = issue_sel_14 & entries_ex_14_bits_deps_ex_4; // @[OneHot.scala:83:30] wire _issue_entry_T_2096 = issue_sel_15 & entries_ex_15_bits_deps_ex_4; // @[OneHot.scala:83:30] wire _issue_entry_T_2097 = _issue_entry_T_2081 | _issue_entry_T_2082; // @[Mux.scala:30:73] wire _issue_entry_T_2098 = _issue_entry_T_2097 | _issue_entry_T_2083; // @[Mux.scala:30:73] wire _issue_entry_T_2099 = _issue_entry_T_2098 | _issue_entry_T_2084; // @[Mux.scala:30:73] wire _issue_entry_T_2100 = _issue_entry_T_2099 | _issue_entry_T_2085; // @[Mux.scala:30:73] wire _issue_entry_T_2101 = _issue_entry_T_2100 | _issue_entry_T_2086; // @[Mux.scala:30:73] wire _issue_entry_T_2102 = _issue_entry_T_2101 | _issue_entry_T_2087; // @[Mux.scala:30:73] wire _issue_entry_T_2103 = _issue_entry_T_2102 | _issue_entry_T_2088; // @[Mux.scala:30:73] wire _issue_entry_T_2104 = _issue_entry_T_2103 | _issue_entry_T_2089; // @[Mux.scala:30:73] wire _issue_entry_T_2105 = _issue_entry_T_2104 | _issue_entry_T_2090; // @[Mux.scala:30:73] wire _issue_entry_T_2106 = _issue_entry_T_2105 | _issue_entry_T_2091; // @[Mux.scala:30:73] wire _issue_entry_T_2107 = _issue_entry_T_2106 | _issue_entry_T_2092; // @[Mux.scala:30:73] wire _issue_entry_T_2108 = _issue_entry_T_2107 | _issue_entry_T_2093; // @[Mux.scala:30:73] wire _issue_entry_T_2109 = _issue_entry_T_2108 | _issue_entry_T_2094; // @[Mux.scala:30:73] wire _issue_entry_T_2110 = _issue_entry_T_2109 | _issue_entry_T_2095; // @[Mux.scala:30:73] wire _issue_entry_T_2111 = _issue_entry_T_2110 | _issue_entry_T_2096; // @[Mux.scala:30:73] assign _issue_entry_WIRE_155 = _issue_entry_T_2111; // @[Mux.scala:30:73] assign _issue_entry_WIRE_150_4 = _issue_entry_WIRE_155; // @[Mux.scala:30:73] wire _issue_entry_T_2112 = issue_sel_0_1 & entries_ex_0_bits_deps_ex_5; // @[OneHot.scala:83:30] wire _issue_entry_T_2113 = issue_sel_1_1 & entries_ex_1_bits_deps_ex_5; // @[OneHot.scala:83:30] wire _issue_entry_T_2114 = issue_sel_2_1 & entries_ex_2_bits_deps_ex_5; // @[OneHot.scala:83:30] wire _issue_entry_T_2115 = issue_sel_3_1 & entries_ex_3_bits_deps_ex_5; // @[OneHot.scala:83:30] wire _issue_entry_T_2116 = issue_sel_4_1 & entries_ex_4_bits_deps_ex_5; // @[OneHot.scala:83:30] wire _issue_entry_T_2117 = issue_sel_5_1 & entries_ex_5_bits_deps_ex_5; // @[OneHot.scala:83:30] wire _issue_entry_T_2118 = issue_sel_6_1 & entries_ex_6_bits_deps_ex_5; // @[OneHot.scala:83:30] wire _issue_entry_T_2119 = issue_sel_7_1 & entries_ex_7_bits_deps_ex_5; // @[OneHot.scala:83:30] wire _issue_entry_T_2120 = issue_sel_8 & entries_ex_8_bits_deps_ex_5; // @[OneHot.scala:83:30] wire _issue_entry_T_2121 = issue_sel_9 & entries_ex_9_bits_deps_ex_5; // @[OneHot.scala:83:30] wire _issue_entry_T_2122 = issue_sel_10 & entries_ex_10_bits_deps_ex_5; // @[OneHot.scala:83:30] wire _issue_entry_T_2123 = issue_sel_11 & entries_ex_11_bits_deps_ex_5; // @[OneHot.scala:83:30] wire _issue_entry_T_2124 = issue_sel_12 & entries_ex_12_bits_deps_ex_5; // @[OneHot.scala:83:30] wire _issue_entry_T_2125 = issue_sel_13 & entries_ex_13_bits_deps_ex_5; // @[OneHot.scala:83:30] wire _issue_entry_T_2126 = issue_sel_14 & entries_ex_14_bits_deps_ex_5; // @[OneHot.scala:83:30] wire _issue_entry_T_2127 = issue_sel_15 & entries_ex_15_bits_deps_ex_5; // @[OneHot.scala:83:30] wire _issue_entry_T_2128 = _issue_entry_T_2112 | _issue_entry_T_2113; // @[Mux.scala:30:73] wire _issue_entry_T_2129 = _issue_entry_T_2128 | _issue_entry_T_2114; // @[Mux.scala:30:73] wire _issue_entry_T_2130 = _issue_entry_T_2129 | _issue_entry_T_2115; // @[Mux.scala:30:73] wire _issue_entry_T_2131 = _issue_entry_T_2130 | _issue_entry_T_2116; // @[Mux.scala:30:73] wire _issue_entry_T_2132 = _issue_entry_T_2131 | _issue_entry_T_2117; // @[Mux.scala:30:73] wire _issue_entry_T_2133 = _issue_entry_T_2132 | _issue_entry_T_2118; // @[Mux.scala:30:73] wire _issue_entry_T_2134 = _issue_entry_T_2133 | _issue_entry_T_2119; // @[Mux.scala:30:73] wire _issue_entry_T_2135 = _issue_entry_T_2134 | _issue_entry_T_2120; // @[Mux.scala:30:73] wire _issue_entry_T_2136 = _issue_entry_T_2135 | _issue_entry_T_2121; // @[Mux.scala:30:73] wire _issue_entry_T_2137 = _issue_entry_T_2136 | _issue_entry_T_2122; // @[Mux.scala:30:73] wire _issue_entry_T_2138 = _issue_entry_T_2137 | _issue_entry_T_2123; // @[Mux.scala:30:73] wire _issue_entry_T_2139 = _issue_entry_T_2138 | _issue_entry_T_2124; // @[Mux.scala:30:73] wire _issue_entry_T_2140 = _issue_entry_T_2139 | _issue_entry_T_2125; // @[Mux.scala:30:73] wire _issue_entry_T_2141 = _issue_entry_T_2140 | _issue_entry_T_2126; // @[Mux.scala:30:73] wire _issue_entry_T_2142 = _issue_entry_T_2141 | _issue_entry_T_2127; // @[Mux.scala:30:73] assign _issue_entry_WIRE_156 = _issue_entry_T_2142; // @[Mux.scala:30:73] assign _issue_entry_WIRE_150_5 = _issue_entry_WIRE_156; // @[Mux.scala:30:73] wire _issue_entry_T_2143 = issue_sel_0_1 & entries_ex_0_bits_deps_ex_6; // @[OneHot.scala:83:30] wire _issue_entry_T_2144 = issue_sel_1_1 & entries_ex_1_bits_deps_ex_6; // @[OneHot.scala:83:30] wire _issue_entry_T_2145 = issue_sel_2_1 & entries_ex_2_bits_deps_ex_6; // @[OneHot.scala:83:30] wire _issue_entry_T_2146 = issue_sel_3_1 & entries_ex_3_bits_deps_ex_6; // @[OneHot.scala:83:30] wire _issue_entry_T_2147 = issue_sel_4_1 & entries_ex_4_bits_deps_ex_6; // @[OneHot.scala:83:30] wire _issue_entry_T_2148 = issue_sel_5_1 & entries_ex_5_bits_deps_ex_6; // @[OneHot.scala:83:30] wire _issue_entry_T_2149 = issue_sel_6_1 & entries_ex_6_bits_deps_ex_6; // @[OneHot.scala:83:30] wire _issue_entry_T_2150 = issue_sel_7_1 & entries_ex_7_bits_deps_ex_6; // @[OneHot.scala:83:30] wire _issue_entry_T_2151 = issue_sel_8 & entries_ex_8_bits_deps_ex_6; // @[OneHot.scala:83:30] wire _issue_entry_T_2152 = issue_sel_9 & entries_ex_9_bits_deps_ex_6; // @[OneHot.scala:83:30] wire _issue_entry_T_2153 = issue_sel_10 & entries_ex_10_bits_deps_ex_6; // @[OneHot.scala:83:30] wire _issue_entry_T_2154 = issue_sel_11 & entries_ex_11_bits_deps_ex_6; // @[OneHot.scala:83:30] wire _issue_entry_T_2155 = issue_sel_12 & entries_ex_12_bits_deps_ex_6; // @[OneHot.scala:83:30] wire _issue_entry_T_2156 = issue_sel_13 & entries_ex_13_bits_deps_ex_6; // @[OneHot.scala:83:30] wire _issue_entry_T_2157 = issue_sel_14 & entries_ex_14_bits_deps_ex_6; // @[OneHot.scala:83:30] wire _issue_entry_T_2158 = issue_sel_15 & entries_ex_15_bits_deps_ex_6; // @[OneHot.scala:83:30] wire _issue_entry_T_2159 = _issue_entry_T_2143 | _issue_entry_T_2144; // @[Mux.scala:30:73] wire _issue_entry_T_2160 = _issue_entry_T_2159 | _issue_entry_T_2145; // @[Mux.scala:30:73] wire _issue_entry_T_2161 = _issue_entry_T_2160 | _issue_entry_T_2146; // @[Mux.scala:30:73] wire _issue_entry_T_2162 = _issue_entry_T_2161 | _issue_entry_T_2147; // @[Mux.scala:30:73] wire _issue_entry_T_2163 = _issue_entry_T_2162 | _issue_entry_T_2148; // @[Mux.scala:30:73] wire _issue_entry_T_2164 = _issue_entry_T_2163 | _issue_entry_T_2149; // @[Mux.scala:30:73] wire _issue_entry_T_2165 = _issue_entry_T_2164 | _issue_entry_T_2150; // @[Mux.scala:30:73] wire _issue_entry_T_2166 = _issue_entry_T_2165 | _issue_entry_T_2151; // @[Mux.scala:30:73] wire _issue_entry_T_2167 = _issue_entry_T_2166 | _issue_entry_T_2152; // @[Mux.scala:30:73] wire _issue_entry_T_2168 = _issue_entry_T_2167 | _issue_entry_T_2153; // @[Mux.scala:30:73] wire _issue_entry_T_2169 = _issue_entry_T_2168 | _issue_entry_T_2154; // @[Mux.scala:30:73] wire _issue_entry_T_2170 = _issue_entry_T_2169 | _issue_entry_T_2155; // @[Mux.scala:30:73] wire _issue_entry_T_2171 = _issue_entry_T_2170 | _issue_entry_T_2156; // @[Mux.scala:30:73] wire _issue_entry_T_2172 = _issue_entry_T_2171 | _issue_entry_T_2157; // @[Mux.scala:30:73] wire _issue_entry_T_2173 = _issue_entry_T_2172 | _issue_entry_T_2158; // @[Mux.scala:30:73] assign _issue_entry_WIRE_157 = _issue_entry_T_2173; // @[Mux.scala:30:73] assign _issue_entry_WIRE_150_6 = _issue_entry_WIRE_157; // @[Mux.scala:30:73] wire _issue_entry_T_2174 = issue_sel_0_1 & entries_ex_0_bits_deps_ex_7; // @[OneHot.scala:83:30] wire _issue_entry_T_2175 = issue_sel_1_1 & entries_ex_1_bits_deps_ex_7; // @[OneHot.scala:83:30] wire _issue_entry_T_2176 = issue_sel_2_1 & entries_ex_2_bits_deps_ex_7; // @[OneHot.scala:83:30] wire _issue_entry_T_2177 = issue_sel_3_1 & entries_ex_3_bits_deps_ex_7; // @[OneHot.scala:83:30] wire _issue_entry_T_2178 = issue_sel_4_1 & entries_ex_4_bits_deps_ex_7; // @[OneHot.scala:83:30] wire _issue_entry_T_2179 = issue_sel_5_1 & entries_ex_5_bits_deps_ex_7; // @[OneHot.scala:83:30] wire _issue_entry_T_2180 = issue_sel_6_1 & entries_ex_6_bits_deps_ex_7; // @[OneHot.scala:83:30] wire _issue_entry_T_2181 = issue_sel_7_1 & entries_ex_7_bits_deps_ex_7; // @[OneHot.scala:83:30] wire _issue_entry_T_2182 = issue_sel_8 & entries_ex_8_bits_deps_ex_7; // @[OneHot.scala:83:30] wire _issue_entry_T_2183 = issue_sel_9 & entries_ex_9_bits_deps_ex_7; // @[OneHot.scala:83:30] wire _issue_entry_T_2184 = issue_sel_10 & entries_ex_10_bits_deps_ex_7; // @[OneHot.scala:83:30] wire _issue_entry_T_2185 = issue_sel_11 & entries_ex_11_bits_deps_ex_7; // @[OneHot.scala:83:30] wire _issue_entry_T_2186 = issue_sel_12 & entries_ex_12_bits_deps_ex_7; // @[OneHot.scala:83:30] wire _issue_entry_T_2187 = issue_sel_13 & entries_ex_13_bits_deps_ex_7; // @[OneHot.scala:83:30] wire _issue_entry_T_2188 = issue_sel_14 & entries_ex_14_bits_deps_ex_7; // @[OneHot.scala:83:30] wire _issue_entry_T_2189 = issue_sel_15 & entries_ex_15_bits_deps_ex_7; // @[OneHot.scala:83:30] wire _issue_entry_T_2190 = _issue_entry_T_2174 | _issue_entry_T_2175; // @[Mux.scala:30:73] wire _issue_entry_T_2191 = _issue_entry_T_2190 | _issue_entry_T_2176; // @[Mux.scala:30:73] wire _issue_entry_T_2192 = _issue_entry_T_2191 | _issue_entry_T_2177; // @[Mux.scala:30:73] wire _issue_entry_T_2193 = _issue_entry_T_2192 | _issue_entry_T_2178; // @[Mux.scala:30:73] wire _issue_entry_T_2194 = _issue_entry_T_2193 | _issue_entry_T_2179; // @[Mux.scala:30:73] wire _issue_entry_T_2195 = _issue_entry_T_2194 | _issue_entry_T_2180; // @[Mux.scala:30:73] wire _issue_entry_T_2196 = _issue_entry_T_2195 | _issue_entry_T_2181; // @[Mux.scala:30:73] wire _issue_entry_T_2197 = _issue_entry_T_2196 | _issue_entry_T_2182; // @[Mux.scala:30:73] wire _issue_entry_T_2198 = _issue_entry_T_2197 | _issue_entry_T_2183; // @[Mux.scala:30:73] wire _issue_entry_T_2199 = _issue_entry_T_2198 | _issue_entry_T_2184; // @[Mux.scala:30:73] wire _issue_entry_T_2200 = _issue_entry_T_2199 | _issue_entry_T_2185; // @[Mux.scala:30:73] wire _issue_entry_T_2201 = _issue_entry_T_2200 | _issue_entry_T_2186; // @[Mux.scala:30:73] wire _issue_entry_T_2202 = _issue_entry_T_2201 | _issue_entry_T_2187; // @[Mux.scala:30:73] wire _issue_entry_T_2203 = _issue_entry_T_2202 | _issue_entry_T_2188; // @[Mux.scala:30:73] wire _issue_entry_T_2204 = _issue_entry_T_2203 | _issue_entry_T_2189; // @[Mux.scala:30:73] assign _issue_entry_WIRE_158 = _issue_entry_T_2204; // @[Mux.scala:30:73] assign _issue_entry_WIRE_150_7 = _issue_entry_WIRE_158; // @[Mux.scala:30:73] wire _issue_entry_T_2205 = issue_sel_0_1 & entries_ex_0_bits_deps_ex_8; // @[OneHot.scala:83:30] wire _issue_entry_T_2206 = issue_sel_1_1 & entries_ex_1_bits_deps_ex_8; // @[OneHot.scala:83:30] wire _issue_entry_T_2207 = issue_sel_2_1 & entries_ex_2_bits_deps_ex_8; // @[OneHot.scala:83:30] wire _issue_entry_T_2208 = issue_sel_3_1 & entries_ex_3_bits_deps_ex_8; // @[OneHot.scala:83:30] wire _issue_entry_T_2209 = issue_sel_4_1 & entries_ex_4_bits_deps_ex_8; // @[OneHot.scala:83:30] wire _issue_entry_T_2210 = issue_sel_5_1 & entries_ex_5_bits_deps_ex_8; // @[OneHot.scala:83:30] wire _issue_entry_T_2211 = issue_sel_6_1 & entries_ex_6_bits_deps_ex_8; // @[OneHot.scala:83:30] wire _issue_entry_T_2212 = issue_sel_7_1 & entries_ex_7_bits_deps_ex_8; // @[OneHot.scala:83:30] wire _issue_entry_T_2213 = issue_sel_8 & entries_ex_8_bits_deps_ex_8; // @[OneHot.scala:83:30] wire _issue_entry_T_2214 = issue_sel_9 & entries_ex_9_bits_deps_ex_8; // @[OneHot.scala:83:30] wire _issue_entry_T_2215 = issue_sel_10 & entries_ex_10_bits_deps_ex_8; // @[OneHot.scala:83:30] wire _issue_entry_T_2216 = issue_sel_11 & entries_ex_11_bits_deps_ex_8; // @[OneHot.scala:83:30] wire _issue_entry_T_2217 = issue_sel_12 & entries_ex_12_bits_deps_ex_8; // @[OneHot.scala:83:30] wire _issue_entry_T_2218 = issue_sel_13 & entries_ex_13_bits_deps_ex_8; // @[OneHot.scala:83:30] wire _issue_entry_T_2219 = issue_sel_14 & entries_ex_14_bits_deps_ex_8; // @[OneHot.scala:83:30] wire _issue_entry_T_2220 = issue_sel_15 & entries_ex_15_bits_deps_ex_8; // @[OneHot.scala:83:30] wire _issue_entry_T_2221 = _issue_entry_T_2205 | _issue_entry_T_2206; // @[Mux.scala:30:73] wire _issue_entry_T_2222 = _issue_entry_T_2221 | _issue_entry_T_2207; // @[Mux.scala:30:73] wire _issue_entry_T_2223 = _issue_entry_T_2222 | _issue_entry_T_2208; // @[Mux.scala:30:73] wire _issue_entry_T_2224 = _issue_entry_T_2223 | _issue_entry_T_2209; // @[Mux.scala:30:73] wire _issue_entry_T_2225 = _issue_entry_T_2224 | _issue_entry_T_2210; // @[Mux.scala:30:73] wire _issue_entry_T_2226 = _issue_entry_T_2225 | _issue_entry_T_2211; // @[Mux.scala:30:73] wire _issue_entry_T_2227 = _issue_entry_T_2226 | _issue_entry_T_2212; // @[Mux.scala:30:73] wire _issue_entry_T_2228 = _issue_entry_T_2227 | _issue_entry_T_2213; // @[Mux.scala:30:73] wire _issue_entry_T_2229 = _issue_entry_T_2228 | _issue_entry_T_2214; // @[Mux.scala:30:73] wire _issue_entry_T_2230 = _issue_entry_T_2229 | _issue_entry_T_2215; // @[Mux.scala:30:73] wire _issue_entry_T_2231 = _issue_entry_T_2230 | _issue_entry_T_2216; // @[Mux.scala:30:73] wire _issue_entry_T_2232 = _issue_entry_T_2231 | _issue_entry_T_2217; // @[Mux.scala:30:73] wire _issue_entry_T_2233 = _issue_entry_T_2232 | _issue_entry_T_2218; // @[Mux.scala:30:73] wire _issue_entry_T_2234 = _issue_entry_T_2233 | _issue_entry_T_2219; // @[Mux.scala:30:73] wire _issue_entry_T_2235 = _issue_entry_T_2234 | _issue_entry_T_2220; // @[Mux.scala:30:73] assign _issue_entry_WIRE_159 = _issue_entry_T_2235; // @[Mux.scala:30:73] assign _issue_entry_WIRE_150_8 = _issue_entry_WIRE_159; // @[Mux.scala:30:73] wire _issue_entry_T_2236 = issue_sel_0_1 & entries_ex_0_bits_deps_ex_9; // @[OneHot.scala:83:30] wire _issue_entry_T_2237 = issue_sel_1_1 & entries_ex_1_bits_deps_ex_9; // @[OneHot.scala:83:30] wire _issue_entry_T_2238 = issue_sel_2_1 & entries_ex_2_bits_deps_ex_9; // @[OneHot.scala:83:30] wire _issue_entry_T_2239 = issue_sel_3_1 & entries_ex_3_bits_deps_ex_9; // @[OneHot.scala:83:30] wire _issue_entry_T_2240 = issue_sel_4_1 & entries_ex_4_bits_deps_ex_9; // @[OneHot.scala:83:30] wire _issue_entry_T_2241 = issue_sel_5_1 & entries_ex_5_bits_deps_ex_9; // @[OneHot.scala:83:30] wire _issue_entry_T_2242 = issue_sel_6_1 & entries_ex_6_bits_deps_ex_9; // @[OneHot.scala:83:30] wire _issue_entry_T_2243 = issue_sel_7_1 & entries_ex_7_bits_deps_ex_9; // @[OneHot.scala:83:30] wire _issue_entry_T_2244 = issue_sel_8 & entries_ex_8_bits_deps_ex_9; // @[OneHot.scala:83:30] wire _issue_entry_T_2245 = issue_sel_9 & entries_ex_9_bits_deps_ex_9; // @[OneHot.scala:83:30] wire _issue_entry_T_2246 = issue_sel_10 & entries_ex_10_bits_deps_ex_9; // @[OneHot.scala:83:30] wire _issue_entry_T_2247 = issue_sel_11 & entries_ex_11_bits_deps_ex_9; // @[OneHot.scala:83:30] wire _issue_entry_T_2248 = issue_sel_12 & entries_ex_12_bits_deps_ex_9; // @[OneHot.scala:83:30] wire _issue_entry_T_2249 = issue_sel_13 & entries_ex_13_bits_deps_ex_9; // @[OneHot.scala:83:30] wire _issue_entry_T_2250 = issue_sel_14 & entries_ex_14_bits_deps_ex_9; // @[OneHot.scala:83:30] wire _issue_entry_T_2251 = issue_sel_15 & entries_ex_15_bits_deps_ex_9; // @[OneHot.scala:83:30] wire _issue_entry_T_2252 = _issue_entry_T_2236 | _issue_entry_T_2237; // @[Mux.scala:30:73] wire _issue_entry_T_2253 = _issue_entry_T_2252 | _issue_entry_T_2238; // @[Mux.scala:30:73] wire _issue_entry_T_2254 = _issue_entry_T_2253 | _issue_entry_T_2239; // @[Mux.scala:30:73] wire _issue_entry_T_2255 = _issue_entry_T_2254 | _issue_entry_T_2240; // @[Mux.scala:30:73] wire _issue_entry_T_2256 = _issue_entry_T_2255 | _issue_entry_T_2241; // @[Mux.scala:30:73] wire _issue_entry_T_2257 = _issue_entry_T_2256 | _issue_entry_T_2242; // @[Mux.scala:30:73] wire _issue_entry_T_2258 = _issue_entry_T_2257 | _issue_entry_T_2243; // @[Mux.scala:30:73] wire _issue_entry_T_2259 = _issue_entry_T_2258 | _issue_entry_T_2244; // @[Mux.scala:30:73] wire _issue_entry_T_2260 = _issue_entry_T_2259 | _issue_entry_T_2245; // @[Mux.scala:30:73] wire _issue_entry_T_2261 = _issue_entry_T_2260 | _issue_entry_T_2246; // @[Mux.scala:30:73] wire _issue_entry_T_2262 = _issue_entry_T_2261 | _issue_entry_T_2247; // @[Mux.scala:30:73] wire _issue_entry_T_2263 = _issue_entry_T_2262 | _issue_entry_T_2248; // @[Mux.scala:30:73] wire _issue_entry_T_2264 = _issue_entry_T_2263 | _issue_entry_T_2249; // @[Mux.scala:30:73] wire _issue_entry_T_2265 = _issue_entry_T_2264 | _issue_entry_T_2250; // @[Mux.scala:30:73] wire _issue_entry_T_2266 = _issue_entry_T_2265 | _issue_entry_T_2251; // @[Mux.scala:30:73] assign _issue_entry_WIRE_160 = _issue_entry_T_2266; // @[Mux.scala:30:73] assign _issue_entry_WIRE_150_9 = _issue_entry_WIRE_160; // @[Mux.scala:30:73] wire _issue_entry_T_2267 = issue_sel_0_1 & entries_ex_0_bits_deps_ex_10; // @[OneHot.scala:83:30] wire _issue_entry_T_2268 = issue_sel_1_1 & entries_ex_1_bits_deps_ex_10; // @[OneHot.scala:83:30] wire _issue_entry_T_2269 = issue_sel_2_1 & entries_ex_2_bits_deps_ex_10; // @[OneHot.scala:83:30] wire _issue_entry_T_2270 = issue_sel_3_1 & entries_ex_3_bits_deps_ex_10; // @[OneHot.scala:83:30] wire _issue_entry_T_2271 = issue_sel_4_1 & entries_ex_4_bits_deps_ex_10; // @[OneHot.scala:83:30] wire _issue_entry_T_2272 = issue_sel_5_1 & entries_ex_5_bits_deps_ex_10; // @[OneHot.scala:83:30] wire _issue_entry_T_2273 = issue_sel_6_1 & entries_ex_6_bits_deps_ex_10; // @[OneHot.scala:83:30] wire _issue_entry_T_2274 = issue_sel_7_1 & entries_ex_7_bits_deps_ex_10; // @[OneHot.scala:83:30] wire _issue_entry_T_2275 = issue_sel_8 & entries_ex_8_bits_deps_ex_10; // @[OneHot.scala:83:30] wire _issue_entry_T_2276 = issue_sel_9 & entries_ex_9_bits_deps_ex_10; // @[OneHot.scala:83:30] wire _issue_entry_T_2277 = issue_sel_10 & entries_ex_10_bits_deps_ex_10; // @[OneHot.scala:83:30] wire _issue_entry_T_2278 = issue_sel_11 & entries_ex_11_bits_deps_ex_10; // @[OneHot.scala:83:30] wire _issue_entry_T_2279 = issue_sel_12 & entries_ex_12_bits_deps_ex_10; // @[OneHot.scala:83:30] wire _issue_entry_T_2280 = issue_sel_13 & entries_ex_13_bits_deps_ex_10; // @[OneHot.scala:83:30] wire _issue_entry_T_2281 = issue_sel_14 & entries_ex_14_bits_deps_ex_10; // @[OneHot.scala:83:30] wire _issue_entry_T_2282 = issue_sel_15 & entries_ex_15_bits_deps_ex_10; // @[OneHot.scala:83:30] wire _issue_entry_T_2283 = _issue_entry_T_2267 | _issue_entry_T_2268; // @[Mux.scala:30:73] wire _issue_entry_T_2284 = _issue_entry_T_2283 | _issue_entry_T_2269; // @[Mux.scala:30:73] wire _issue_entry_T_2285 = _issue_entry_T_2284 | _issue_entry_T_2270; // @[Mux.scala:30:73] wire _issue_entry_T_2286 = _issue_entry_T_2285 | _issue_entry_T_2271; // @[Mux.scala:30:73] wire _issue_entry_T_2287 = _issue_entry_T_2286 | _issue_entry_T_2272; // @[Mux.scala:30:73] wire _issue_entry_T_2288 = _issue_entry_T_2287 | _issue_entry_T_2273; // @[Mux.scala:30:73] wire _issue_entry_T_2289 = _issue_entry_T_2288 | _issue_entry_T_2274; // @[Mux.scala:30:73] wire _issue_entry_T_2290 = _issue_entry_T_2289 | _issue_entry_T_2275; // @[Mux.scala:30:73] wire _issue_entry_T_2291 = _issue_entry_T_2290 | _issue_entry_T_2276; // @[Mux.scala:30:73] wire _issue_entry_T_2292 = _issue_entry_T_2291 | _issue_entry_T_2277; // @[Mux.scala:30:73] wire _issue_entry_T_2293 = _issue_entry_T_2292 | _issue_entry_T_2278; // @[Mux.scala:30:73] wire _issue_entry_T_2294 = _issue_entry_T_2293 | _issue_entry_T_2279; // @[Mux.scala:30:73] wire _issue_entry_T_2295 = _issue_entry_T_2294 | _issue_entry_T_2280; // @[Mux.scala:30:73] wire _issue_entry_T_2296 = _issue_entry_T_2295 | _issue_entry_T_2281; // @[Mux.scala:30:73] wire _issue_entry_T_2297 = _issue_entry_T_2296 | _issue_entry_T_2282; // @[Mux.scala:30:73] assign _issue_entry_WIRE_161 = _issue_entry_T_2297; // @[Mux.scala:30:73] assign _issue_entry_WIRE_150_10 = _issue_entry_WIRE_161; // @[Mux.scala:30:73] wire _issue_entry_T_2298 = issue_sel_0_1 & entries_ex_0_bits_deps_ex_11; // @[OneHot.scala:83:30] wire _issue_entry_T_2299 = issue_sel_1_1 & entries_ex_1_bits_deps_ex_11; // @[OneHot.scala:83:30] wire _issue_entry_T_2300 = issue_sel_2_1 & entries_ex_2_bits_deps_ex_11; // @[OneHot.scala:83:30] wire _issue_entry_T_2301 = issue_sel_3_1 & entries_ex_3_bits_deps_ex_11; // @[OneHot.scala:83:30] wire _issue_entry_T_2302 = issue_sel_4_1 & entries_ex_4_bits_deps_ex_11; // @[OneHot.scala:83:30] wire _issue_entry_T_2303 = issue_sel_5_1 & entries_ex_5_bits_deps_ex_11; // @[OneHot.scala:83:30] wire _issue_entry_T_2304 = issue_sel_6_1 & entries_ex_6_bits_deps_ex_11; // @[OneHot.scala:83:30] wire _issue_entry_T_2305 = issue_sel_7_1 & entries_ex_7_bits_deps_ex_11; // @[OneHot.scala:83:30] wire _issue_entry_T_2306 = issue_sel_8 & entries_ex_8_bits_deps_ex_11; // @[OneHot.scala:83:30] wire _issue_entry_T_2307 = issue_sel_9 & entries_ex_9_bits_deps_ex_11; // @[OneHot.scala:83:30] wire _issue_entry_T_2308 = issue_sel_10 & entries_ex_10_bits_deps_ex_11; // @[OneHot.scala:83:30] wire _issue_entry_T_2309 = issue_sel_11 & entries_ex_11_bits_deps_ex_11; // @[OneHot.scala:83:30] wire _issue_entry_T_2310 = issue_sel_12 & entries_ex_12_bits_deps_ex_11; // @[OneHot.scala:83:30] wire _issue_entry_T_2311 = issue_sel_13 & entries_ex_13_bits_deps_ex_11; // @[OneHot.scala:83:30] wire _issue_entry_T_2312 = issue_sel_14 & entries_ex_14_bits_deps_ex_11; // @[OneHot.scala:83:30] wire _issue_entry_T_2313 = issue_sel_15 & entries_ex_15_bits_deps_ex_11; // @[OneHot.scala:83:30] wire _issue_entry_T_2314 = _issue_entry_T_2298 | _issue_entry_T_2299; // @[Mux.scala:30:73] wire _issue_entry_T_2315 = _issue_entry_T_2314 | _issue_entry_T_2300; // @[Mux.scala:30:73] wire _issue_entry_T_2316 = _issue_entry_T_2315 | _issue_entry_T_2301; // @[Mux.scala:30:73] wire _issue_entry_T_2317 = _issue_entry_T_2316 | _issue_entry_T_2302; // @[Mux.scala:30:73] wire _issue_entry_T_2318 = _issue_entry_T_2317 | _issue_entry_T_2303; // @[Mux.scala:30:73] wire _issue_entry_T_2319 = _issue_entry_T_2318 | _issue_entry_T_2304; // @[Mux.scala:30:73] wire _issue_entry_T_2320 = _issue_entry_T_2319 | _issue_entry_T_2305; // @[Mux.scala:30:73] wire _issue_entry_T_2321 = _issue_entry_T_2320 | _issue_entry_T_2306; // @[Mux.scala:30:73] wire _issue_entry_T_2322 = _issue_entry_T_2321 | _issue_entry_T_2307; // @[Mux.scala:30:73] wire _issue_entry_T_2323 = _issue_entry_T_2322 | _issue_entry_T_2308; // @[Mux.scala:30:73] wire _issue_entry_T_2324 = _issue_entry_T_2323 | _issue_entry_T_2309; // @[Mux.scala:30:73] wire _issue_entry_T_2325 = _issue_entry_T_2324 | _issue_entry_T_2310; // @[Mux.scala:30:73] wire _issue_entry_T_2326 = _issue_entry_T_2325 | _issue_entry_T_2311; // @[Mux.scala:30:73] wire _issue_entry_T_2327 = _issue_entry_T_2326 | _issue_entry_T_2312; // @[Mux.scala:30:73] wire _issue_entry_T_2328 = _issue_entry_T_2327 | _issue_entry_T_2313; // @[Mux.scala:30:73] assign _issue_entry_WIRE_162 = _issue_entry_T_2328; // @[Mux.scala:30:73] assign _issue_entry_WIRE_150_11 = _issue_entry_WIRE_162; // @[Mux.scala:30:73] wire _issue_entry_T_2329 = issue_sel_0_1 & entries_ex_0_bits_deps_ex_12; // @[OneHot.scala:83:30] wire _issue_entry_T_2330 = issue_sel_1_1 & entries_ex_1_bits_deps_ex_12; // @[OneHot.scala:83:30] wire _issue_entry_T_2331 = issue_sel_2_1 & entries_ex_2_bits_deps_ex_12; // @[OneHot.scala:83:30] wire _issue_entry_T_2332 = issue_sel_3_1 & entries_ex_3_bits_deps_ex_12; // @[OneHot.scala:83:30] wire _issue_entry_T_2333 = issue_sel_4_1 & entries_ex_4_bits_deps_ex_12; // @[OneHot.scala:83:30] wire _issue_entry_T_2334 = issue_sel_5_1 & entries_ex_5_bits_deps_ex_12; // @[OneHot.scala:83:30] wire _issue_entry_T_2335 = issue_sel_6_1 & entries_ex_6_bits_deps_ex_12; // @[OneHot.scala:83:30] wire _issue_entry_T_2336 = issue_sel_7_1 & entries_ex_7_bits_deps_ex_12; // @[OneHot.scala:83:30] wire _issue_entry_T_2337 = issue_sel_8 & entries_ex_8_bits_deps_ex_12; // @[OneHot.scala:83:30] wire _issue_entry_T_2338 = issue_sel_9 & entries_ex_9_bits_deps_ex_12; // @[OneHot.scala:83:30] wire _issue_entry_T_2339 = issue_sel_10 & entries_ex_10_bits_deps_ex_12; // @[OneHot.scala:83:30] wire _issue_entry_T_2340 = issue_sel_11 & entries_ex_11_bits_deps_ex_12; // @[OneHot.scala:83:30] wire _issue_entry_T_2341 = issue_sel_12 & entries_ex_12_bits_deps_ex_12; // @[OneHot.scala:83:30] wire _issue_entry_T_2342 = issue_sel_13 & entries_ex_13_bits_deps_ex_12; // @[OneHot.scala:83:30] wire _issue_entry_T_2343 = issue_sel_14 & entries_ex_14_bits_deps_ex_12; // @[OneHot.scala:83:30] wire _issue_entry_T_2344 = issue_sel_15 & entries_ex_15_bits_deps_ex_12; // @[OneHot.scala:83:30] wire _issue_entry_T_2345 = _issue_entry_T_2329 | _issue_entry_T_2330; // @[Mux.scala:30:73] wire _issue_entry_T_2346 = _issue_entry_T_2345 | _issue_entry_T_2331; // @[Mux.scala:30:73] wire _issue_entry_T_2347 = _issue_entry_T_2346 | _issue_entry_T_2332; // @[Mux.scala:30:73] wire _issue_entry_T_2348 = _issue_entry_T_2347 | _issue_entry_T_2333; // @[Mux.scala:30:73] wire _issue_entry_T_2349 = _issue_entry_T_2348 | _issue_entry_T_2334; // @[Mux.scala:30:73] wire _issue_entry_T_2350 = _issue_entry_T_2349 | _issue_entry_T_2335; // @[Mux.scala:30:73] wire _issue_entry_T_2351 = _issue_entry_T_2350 | _issue_entry_T_2336; // @[Mux.scala:30:73] wire _issue_entry_T_2352 = _issue_entry_T_2351 | _issue_entry_T_2337; // @[Mux.scala:30:73] wire _issue_entry_T_2353 = _issue_entry_T_2352 | _issue_entry_T_2338; // @[Mux.scala:30:73] wire _issue_entry_T_2354 = _issue_entry_T_2353 | _issue_entry_T_2339; // @[Mux.scala:30:73] wire _issue_entry_T_2355 = _issue_entry_T_2354 | _issue_entry_T_2340; // @[Mux.scala:30:73] wire _issue_entry_T_2356 = _issue_entry_T_2355 | _issue_entry_T_2341; // @[Mux.scala:30:73] wire _issue_entry_T_2357 = _issue_entry_T_2356 | _issue_entry_T_2342; // @[Mux.scala:30:73] wire _issue_entry_T_2358 = _issue_entry_T_2357 | _issue_entry_T_2343; // @[Mux.scala:30:73] wire _issue_entry_T_2359 = _issue_entry_T_2358 | _issue_entry_T_2344; // @[Mux.scala:30:73] assign _issue_entry_WIRE_163 = _issue_entry_T_2359; // @[Mux.scala:30:73] assign _issue_entry_WIRE_150_12 = _issue_entry_WIRE_163; // @[Mux.scala:30:73] wire _issue_entry_T_2360 = issue_sel_0_1 & entries_ex_0_bits_deps_ex_13; // @[OneHot.scala:83:30] wire _issue_entry_T_2361 = issue_sel_1_1 & entries_ex_1_bits_deps_ex_13; // @[OneHot.scala:83:30] wire _issue_entry_T_2362 = issue_sel_2_1 & entries_ex_2_bits_deps_ex_13; // @[OneHot.scala:83:30] wire _issue_entry_T_2363 = issue_sel_3_1 & entries_ex_3_bits_deps_ex_13; // @[OneHot.scala:83:30] wire _issue_entry_T_2364 = issue_sel_4_1 & entries_ex_4_bits_deps_ex_13; // @[OneHot.scala:83:30] wire _issue_entry_T_2365 = issue_sel_5_1 & entries_ex_5_bits_deps_ex_13; // @[OneHot.scala:83:30] wire _issue_entry_T_2366 = issue_sel_6_1 & entries_ex_6_bits_deps_ex_13; // @[OneHot.scala:83:30] wire _issue_entry_T_2367 = issue_sel_7_1 & entries_ex_7_bits_deps_ex_13; // @[OneHot.scala:83:30] wire _issue_entry_T_2368 = issue_sel_8 & entries_ex_8_bits_deps_ex_13; // @[OneHot.scala:83:30] wire _issue_entry_T_2369 = issue_sel_9 & entries_ex_9_bits_deps_ex_13; // @[OneHot.scala:83:30] wire _issue_entry_T_2370 = issue_sel_10 & entries_ex_10_bits_deps_ex_13; // @[OneHot.scala:83:30] wire _issue_entry_T_2371 = issue_sel_11 & entries_ex_11_bits_deps_ex_13; // @[OneHot.scala:83:30] wire _issue_entry_T_2372 = issue_sel_12 & entries_ex_12_bits_deps_ex_13; // @[OneHot.scala:83:30] wire _issue_entry_T_2373 = issue_sel_13 & entries_ex_13_bits_deps_ex_13; // @[OneHot.scala:83:30] wire _issue_entry_T_2374 = issue_sel_14 & entries_ex_14_bits_deps_ex_13; // @[OneHot.scala:83:30] wire _issue_entry_T_2375 = issue_sel_15 & entries_ex_15_bits_deps_ex_13; // @[OneHot.scala:83:30] wire _issue_entry_T_2376 = _issue_entry_T_2360 | _issue_entry_T_2361; // @[Mux.scala:30:73] wire _issue_entry_T_2377 = _issue_entry_T_2376 | _issue_entry_T_2362; // @[Mux.scala:30:73] wire _issue_entry_T_2378 = _issue_entry_T_2377 | _issue_entry_T_2363; // @[Mux.scala:30:73] wire _issue_entry_T_2379 = _issue_entry_T_2378 | _issue_entry_T_2364; // @[Mux.scala:30:73] wire _issue_entry_T_2380 = _issue_entry_T_2379 | _issue_entry_T_2365; // @[Mux.scala:30:73] wire _issue_entry_T_2381 = _issue_entry_T_2380 | _issue_entry_T_2366; // @[Mux.scala:30:73] wire _issue_entry_T_2382 = _issue_entry_T_2381 | _issue_entry_T_2367; // @[Mux.scala:30:73] wire _issue_entry_T_2383 = _issue_entry_T_2382 | _issue_entry_T_2368; // @[Mux.scala:30:73] wire _issue_entry_T_2384 = _issue_entry_T_2383 | _issue_entry_T_2369; // @[Mux.scala:30:73] wire _issue_entry_T_2385 = _issue_entry_T_2384 | _issue_entry_T_2370; // @[Mux.scala:30:73] wire _issue_entry_T_2386 = _issue_entry_T_2385 | _issue_entry_T_2371; // @[Mux.scala:30:73] wire _issue_entry_T_2387 = _issue_entry_T_2386 | _issue_entry_T_2372; // @[Mux.scala:30:73] wire _issue_entry_T_2388 = _issue_entry_T_2387 | _issue_entry_T_2373; // @[Mux.scala:30:73] wire _issue_entry_T_2389 = _issue_entry_T_2388 | _issue_entry_T_2374; // @[Mux.scala:30:73] wire _issue_entry_T_2390 = _issue_entry_T_2389 | _issue_entry_T_2375; // @[Mux.scala:30:73] assign _issue_entry_WIRE_164 = _issue_entry_T_2390; // @[Mux.scala:30:73] assign _issue_entry_WIRE_150_13 = _issue_entry_WIRE_164; // @[Mux.scala:30:73] wire _issue_entry_T_2391 = issue_sel_0_1 & entries_ex_0_bits_deps_ex_14; // @[OneHot.scala:83:30] wire _issue_entry_T_2392 = issue_sel_1_1 & entries_ex_1_bits_deps_ex_14; // @[OneHot.scala:83:30] wire _issue_entry_T_2393 = issue_sel_2_1 & entries_ex_2_bits_deps_ex_14; // @[OneHot.scala:83:30] wire _issue_entry_T_2394 = issue_sel_3_1 & entries_ex_3_bits_deps_ex_14; // @[OneHot.scala:83:30] wire _issue_entry_T_2395 = issue_sel_4_1 & entries_ex_4_bits_deps_ex_14; // @[OneHot.scala:83:30] wire _issue_entry_T_2396 = issue_sel_5_1 & entries_ex_5_bits_deps_ex_14; // @[OneHot.scala:83:30] wire _issue_entry_T_2397 = issue_sel_6_1 & entries_ex_6_bits_deps_ex_14; // @[OneHot.scala:83:30] wire _issue_entry_T_2398 = issue_sel_7_1 & entries_ex_7_bits_deps_ex_14; // @[OneHot.scala:83:30] wire _issue_entry_T_2399 = issue_sel_8 & entries_ex_8_bits_deps_ex_14; // @[OneHot.scala:83:30] wire _issue_entry_T_2400 = issue_sel_9 & entries_ex_9_bits_deps_ex_14; // @[OneHot.scala:83:30] wire _issue_entry_T_2401 = issue_sel_10 & entries_ex_10_bits_deps_ex_14; // @[OneHot.scala:83:30] wire _issue_entry_T_2402 = issue_sel_11 & entries_ex_11_bits_deps_ex_14; // @[OneHot.scala:83:30] wire _issue_entry_T_2403 = issue_sel_12 & entries_ex_12_bits_deps_ex_14; // @[OneHot.scala:83:30] wire _issue_entry_T_2404 = issue_sel_13 & entries_ex_13_bits_deps_ex_14; // @[OneHot.scala:83:30] wire _issue_entry_T_2405 = issue_sel_14 & entries_ex_14_bits_deps_ex_14; // @[OneHot.scala:83:30] wire _issue_entry_T_2406 = issue_sel_15 & entries_ex_15_bits_deps_ex_14; // @[OneHot.scala:83:30] wire _issue_entry_T_2407 = _issue_entry_T_2391 | _issue_entry_T_2392; // @[Mux.scala:30:73] wire _issue_entry_T_2408 = _issue_entry_T_2407 | _issue_entry_T_2393; // @[Mux.scala:30:73] wire _issue_entry_T_2409 = _issue_entry_T_2408 | _issue_entry_T_2394; // @[Mux.scala:30:73] wire _issue_entry_T_2410 = _issue_entry_T_2409 | _issue_entry_T_2395; // @[Mux.scala:30:73] wire _issue_entry_T_2411 = _issue_entry_T_2410 | _issue_entry_T_2396; // @[Mux.scala:30:73] wire _issue_entry_T_2412 = _issue_entry_T_2411 | _issue_entry_T_2397; // @[Mux.scala:30:73] wire _issue_entry_T_2413 = _issue_entry_T_2412 | _issue_entry_T_2398; // @[Mux.scala:30:73] wire _issue_entry_T_2414 = _issue_entry_T_2413 | _issue_entry_T_2399; // @[Mux.scala:30:73] wire _issue_entry_T_2415 = _issue_entry_T_2414 | _issue_entry_T_2400; // @[Mux.scala:30:73] wire _issue_entry_T_2416 = _issue_entry_T_2415 | _issue_entry_T_2401; // @[Mux.scala:30:73] wire _issue_entry_T_2417 = _issue_entry_T_2416 | _issue_entry_T_2402; // @[Mux.scala:30:73] wire _issue_entry_T_2418 = _issue_entry_T_2417 | _issue_entry_T_2403; // @[Mux.scala:30:73] wire _issue_entry_T_2419 = _issue_entry_T_2418 | _issue_entry_T_2404; // @[Mux.scala:30:73] wire _issue_entry_T_2420 = _issue_entry_T_2419 | _issue_entry_T_2405; // @[Mux.scala:30:73] wire _issue_entry_T_2421 = _issue_entry_T_2420 | _issue_entry_T_2406; // @[Mux.scala:30:73] assign _issue_entry_WIRE_165 = _issue_entry_T_2421; // @[Mux.scala:30:73] assign _issue_entry_WIRE_150_14 = _issue_entry_WIRE_165; // @[Mux.scala:30:73] wire _issue_entry_T_2422 = issue_sel_0_1 & entries_ex_0_bits_deps_ex_15; // @[OneHot.scala:83:30] wire _issue_entry_T_2423 = issue_sel_1_1 & entries_ex_1_bits_deps_ex_15; // @[OneHot.scala:83:30] wire _issue_entry_T_2424 = issue_sel_2_1 & entries_ex_2_bits_deps_ex_15; // @[OneHot.scala:83:30] wire _issue_entry_T_2425 = issue_sel_3_1 & entries_ex_3_bits_deps_ex_15; // @[OneHot.scala:83:30] wire _issue_entry_T_2426 = issue_sel_4_1 & entries_ex_4_bits_deps_ex_15; // @[OneHot.scala:83:30] wire _issue_entry_T_2427 = issue_sel_5_1 & entries_ex_5_bits_deps_ex_15; // @[OneHot.scala:83:30] wire _issue_entry_T_2428 = issue_sel_6_1 & entries_ex_6_bits_deps_ex_15; // @[OneHot.scala:83:30] wire _issue_entry_T_2429 = issue_sel_7_1 & entries_ex_7_bits_deps_ex_15; // @[OneHot.scala:83:30] wire _issue_entry_T_2430 = issue_sel_8 & entries_ex_8_bits_deps_ex_15; // @[OneHot.scala:83:30] wire _issue_entry_T_2431 = issue_sel_9 & entries_ex_9_bits_deps_ex_15; // @[OneHot.scala:83:30] wire _issue_entry_T_2432 = issue_sel_10 & entries_ex_10_bits_deps_ex_15; // @[OneHot.scala:83:30] wire _issue_entry_T_2433 = issue_sel_11 & entries_ex_11_bits_deps_ex_15; // @[OneHot.scala:83:30] wire _issue_entry_T_2434 = issue_sel_12 & entries_ex_12_bits_deps_ex_15; // @[OneHot.scala:83:30] wire _issue_entry_T_2435 = issue_sel_13 & entries_ex_13_bits_deps_ex_15; // @[OneHot.scala:83:30] wire _issue_entry_T_2436 = issue_sel_14 & entries_ex_14_bits_deps_ex_15; // @[OneHot.scala:83:30] wire _issue_entry_T_2437 = issue_sel_15 & entries_ex_15_bits_deps_ex_15; // @[OneHot.scala:83:30] wire _issue_entry_T_2438 = _issue_entry_T_2422 | _issue_entry_T_2423; // @[Mux.scala:30:73] wire _issue_entry_T_2439 = _issue_entry_T_2438 | _issue_entry_T_2424; // @[Mux.scala:30:73] wire _issue_entry_T_2440 = _issue_entry_T_2439 | _issue_entry_T_2425; // @[Mux.scala:30:73] wire _issue_entry_T_2441 = _issue_entry_T_2440 | _issue_entry_T_2426; // @[Mux.scala:30:73] wire _issue_entry_T_2442 = _issue_entry_T_2441 | _issue_entry_T_2427; // @[Mux.scala:30:73] wire _issue_entry_T_2443 = _issue_entry_T_2442 | _issue_entry_T_2428; // @[Mux.scala:30:73] wire _issue_entry_T_2444 = _issue_entry_T_2443 | _issue_entry_T_2429; // @[Mux.scala:30:73] wire _issue_entry_T_2445 = _issue_entry_T_2444 | _issue_entry_T_2430; // @[Mux.scala:30:73] wire _issue_entry_T_2446 = _issue_entry_T_2445 | _issue_entry_T_2431; // @[Mux.scala:30:73] wire _issue_entry_T_2447 = _issue_entry_T_2446 | _issue_entry_T_2432; // @[Mux.scala:30:73] wire _issue_entry_T_2448 = _issue_entry_T_2447 | _issue_entry_T_2433; // @[Mux.scala:30:73] wire _issue_entry_T_2449 = _issue_entry_T_2448 | _issue_entry_T_2434; // @[Mux.scala:30:73] wire _issue_entry_T_2450 = _issue_entry_T_2449 | _issue_entry_T_2435; // @[Mux.scala:30:73] wire _issue_entry_T_2451 = _issue_entry_T_2450 | _issue_entry_T_2436; // @[Mux.scala:30:73] wire _issue_entry_T_2452 = _issue_entry_T_2451 | _issue_entry_T_2437; // @[Mux.scala:30:73] assign _issue_entry_WIRE_166 = _issue_entry_T_2452; // @[Mux.scala:30:73] assign _issue_entry_WIRE_150_15 = _issue_entry_WIRE_166; // @[Mux.scala:30:73] wire _issue_entry_WIRE_168; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_deps_ld_0 = _issue_entry_WIRE_167_0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_169; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_deps_ld_1 = _issue_entry_WIRE_167_1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_170; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_deps_ld_2 = _issue_entry_WIRE_167_2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_171; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_deps_ld_3 = _issue_entry_WIRE_167_3; // @[Mux.scala:30:73] wire _issue_entry_WIRE_172; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_deps_ld_4 = _issue_entry_WIRE_167_4; // @[Mux.scala:30:73] wire _issue_entry_WIRE_173; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_deps_ld_5 = _issue_entry_WIRE_167_5; // @[Mux.scala:30:73] wire _issue_entry_WIRE_174; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_deps_ld_6 = _issue_entry_WIRE_167_6; // @[Mux.scala:30:73] wire _issue_entry_WIRE_175; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_deps_ld_7 = _issue_entry_WIRE_167_7; // @[Mux.scala:30:73] wire _issue_entry_T_2453 = issue_sel_0_1 & entries_ex_0_bits_deps_ld_0; // @[OneHot.scala:83:30] wire _issue_entry_T_2454 = issue_sel_1_1 & entries_ex_1_bits_deps_ld_0; // @[OneHot.scala:83:30] wire _issue_entry_T_2455 = issue_sel_2_1 & entries_ex_2_bits_deps_ld_0; // @[OneHot.scala:83:30] wire _issue_entry_T_2456 = issue_sel_3_1 & entries_ex_3_bits_deps_ld_0; // @[OneHot.scala:83:30] wire _issue_entry_T_2457 = issue_sel_4_1 & entries_ex_4_bits_deps_ld_0; // @[OneHot.scala:83:30] wire _issue_entry_T_2458 = issue_sel_5_1 & entries_ex_5_bits_deps_ld_0; // @[OneHot.scala:83:30] wire _issue_entry_T_2459 = issue_sel_6_1 & entries_ex_6_bits_deps_ld_0; // @[OneHot.scala:83:30] wire _issue_entry_T_2460 = issue_sel_7_1 & entries_ex_7_bits_deps_ld_0; // @[OneHot.scala:83:30] wire _issue_entry_T_2461 = issue_sel_8 & entries_ex_8_bits_deps_ld_0; // @[OneHot.scala:83:30] wire _issue_entry_T_2462 = issue_sel_9 & entries_ex_9_bits_deps_ld_0; // @[OneHot.scala:83:30] wire _issue_entry_T_2463 = issue_sel_10 & entries_ex_10_bits_deps_ld_0; // @[OneHot.scala:83:30] wire _issue_entry_T_2464 = issue_sel_11 & entries_ex_11_bits_deps_ld_0; // @[OneHot.scala:83:30] wire _issue_entry_T_2465 = issue_sel_12 & entries_ex_12_bits_deps_ld_0; // @[OneHot.scala:83:30] wire _issue_entry_T_2466 = issue_sel_13 & entries_ex_13_bits_deps_ld_0; // @[OneHot.scala:83:30] wire _issue_entry_T_2467 = issue_sel_14 & entries_ex_14_bits_deps_ld_0; // @[OneHot.scala:83:30] wire _issue_entry_T_2468 = issue_sel_15 & entries_ex_15_bits_deps_ld_0; // @[OneHot.scala:83:30] wire _issue_entry_T_2469 = _issue_entry_T_2453 | _issue_entry_T_2454; // @[Mux.scala:30:73] wire _issue_entry_T_2470 = _issue_entry_T_2469 | _issue_entry_T_2455; // @[Mux.scala:30:73] wire _issue_entry_T_2471 = _issue_entry_T_2470 | _issue_entry_T_2456; // @[Mux.scala:30:73] wire _issue_entry_T_2472 = _issue_entry_T_2471 | _issue_entry_T_2457; // @[Mux.scala:30:73] wire _issue_entry_T_2473 = _issue_entry_T_2472 | _issue_entry_T_2458; // @[Mux.scala:30:73] wire _issue_entry_T_2474 = _issue_entry_T_2473 | _issue_entry_T_2459; // @[Mux.scala:30:73] wire _issue_entry_T_2475 = _issue_entry_T_2474 | _issue_entry_T_2460; // @[Mux.scala:30:73] wire _issue_entry_T_2476 = _issue_entry_T_2475 | _issue_entry_T_2461; // @[Mux.scala:30:73] wire _issue_entry_T_2477 = _issue_entry_T_2476 | _issue_entry_T_2462; // @[Mux.scala:30:73] wire _issue_entry_T_2478 = _issue_entry_T_2477 | _issue_entry_T_2463; // @[Mux.scala:30:73] wire _issue_entry_T_2479 = _issue_entry_T_2478 | _issue_entry_T_2464; // @[Mux.scala:30:73] wire _issue_entry_T_2480 = _issue_entry_T_2479 | _issue_entry_T_2465; // @[Mux.scala:30:73] wire _issue_entry_T_2481 = _issue_entry_T_2480 | _issue_entry_T_2466; // @[Mux.scala:30:73] wire _issue_entry_T_2482 = _issue_entry_T_2481 | _issue_entry_T_2467; // @[Mux.scala:30:73] wire _issue_entry_T_2483 = _issue_entry_T_2482 | _issue_entry_T_2468; // @[Mux.scala:30:73] assign _issue_entry_WIRE_168 = _issue_entry_T_2483; // @[Mux.scala:30:73] assign _issue_entry_WIRE_167_0 = _issue_entry_WIRE_168; // @[Mux.scala:30:73] wire _issue_entry_T_2484 = issue_sel_0_1 & entries_ex_0_bits_deps_ld_1; // @[OneHot.scala:83:30] wire _issue_entry_T_2485 = issue_sel_1_1 & entries_ex_1_bits_deps_ld_1; // @[OneHot.scala:83:30] wire _issue_entry_T_2486 = issue_sel_2_1 & entries_ex_2_bits_deps_ld_1; // @[OneHot.scala:83:30] wire _issue_entry_T_2487 = issue_sel_3_1 & entries_ex_3_bits_deps_ld_1; // @[OneHot.scala:83:30] wire _issue_entry_T_2488 = issue_sel_4_1 & entries_ex_4_bits_deps_ld_1; // @[OneHot.scala:83:30] wire _issue_entry_T_2489 = issue_sel_5_1 & entries_ex_5_bits_deps_ld_1; // @[OneHot.scala:83:30] wire _issue_entry_T_2490 = issue_sel_6_1 & entries_ex_6_bits_deps_ld_1; // @[OneHot.scala:83:30] wire _issue_entry_T_2491 = issue_sel_7_1 & entries_ex_7_bits_deps_ld_1; // @[OneHot.scala:83:30] wire _issue_entry_T_2492 = issue_sel_8 & entries_ex_8_bits_deps_ld_1; // @[OneHot.scala:83:30] wire _issue_entry_T_2493 = issue_sel_9 & entries_ex_9_bits_deps_ld_1; // @[OneHot.scala:83:30] wire _issue_entry_T_2494 = issue_sel_10 & entries_ex_10_bits_deps_ld_1; // @[OneHot.scala:83:30] wire _issue_entry_T_2495 = issue_sel_11 & entries_ex_11_bits_deps_ld_1; // @[OneHot.scala:83:30] wire _issue_entry_T_2496 = issue_sel_12 & entries_ex_12_bits_deps_ld_1; // @[OneHot.scala:83:30] wire _issue_entry_T_2497 = issue_sel_13 & entries_ex_13_bits_deps_ld_1; // @[OneHot.scala:83:30] wire _issue_entry_T_2498 = issue_sel_14 & entries_ex_14_bits_deps_ld_1; // @[OneHot.scala:83:30] wire _issue_entry_T_2499 = issue_sel_15 & entries_ex_15_bits_deps_ld_1; // @[OneHot.scala:83:30] wire _issue_entry_T_2500 = _issue_entry_T_2484 | _issue_entry_T_2485; // @[Mux.scala:30:73] wire _issue_entry_T_2501 = _issue_entry_T_2500 | _issue_entry_T_2486; // @[Mux.scala:30:73] wire _issue_entry_T_2502 = _issue_entry_T_2501 | _issue_entry_T_2487; // @[Mux.scala:30:73] wire _issue_entry_T_2503 = _issue_entry_T_2502 | _issue_entry_T_2488; // @[Mux.scala:30:73] wire _issue_entry_T_2504 = _issue_entry_T_2503 | _issue_entry_T_2489; // @[Mux.scala:30:73] wire _issue_entry_T_2505 = _issue_entry_T_2504 | _issue_entry_T_2490; // @[Mux.scala:30:73] wire _issue_entry_T_2506 = _issue_entry_T_2505 | _issue_entry_T_2491; // @[Mux.scala:30:73] wire _issue_entry_T_2507 = _issue_entry_T_2506 | _issue_entry_T_2492; // @[Mux.scala:30:73] wire _issue_entry_T_2508 = _issue_entry_T_2507 | _issue_entry_T_2493; // @[Mux.scala:30:73] wire _issue_entry_T_2509 = _issue_entry_T_2508 | _issue_entry_T_2494; // @[Mux.scala:30:73] wire _issue_entry_T_2510 = _issue_entry_T_2509 | _issue_entry_T_2495; // @[Mux.scala:30:73] wire _issue_entry_T_2511 = _issue_entry_T_2510 | _issue_entry_T_2496; // @[Mux.scala:30:73] wire _issue_entry_T_2512 = _issue_entry_T_2511 | _issue_entry_T_2497; // @[Mux.scala:30:73] wire _issue_entry_T_2513 = _issue_entry_T_2512 | _issue_entry_T_2498; // @[Mux.scala:30:73] wire _issue_entry_T_2514 = _issue_entry_T_2513 | _issue_entry_T_2499; // @[Mux.scala:30:73] assign _issue_entry_WIRE_169 = _issue_entry_T_2514; // @[Mux.scala:30:73] assign _issue_entry_WIRE_167_1 = _issue_entry_WIRE_169; // @[Mux.scala:30:73] wire _issue_entry_T_2515 = issue_sel_0_1 & entries_ex_0_bits_deps_ld_2; // @[OneHot.scala:83:30] wire _issue_entry_T_2516 = issue_sel_1_1 & entries_ex_1_bits_deps_ld_2; // @[OneHot.scala:83:30] wire _issue_entry_T_2517 = issue_sel_2_1 & entries_ex_2_bits_deps_ld_2; // @[OneHot.scala:83:30] wire _issue_entry_T_2518 = issue_sel_3_1 & entries_ex_3_bits_deps_ld_2; // @[OneHot.scala:83:30] wire _issue_entry_T_2519 = issue_sel_4_1 & entries_ex_4_bits_deps_ld_2; // @[OneHot.scala:83:30] wire _issue_entry_T_2520 = issue_sel_5_1 & entries_ex_5_bits_deps_ld_2; // @[OneHot.scala:83:30] wire _issue_entry_T_2521 = issue_sel_6_1 & entries_ex_6_bits_deps_ld_2; // @[OneHot.scala:83:30] wire _issue_entry_T_2522 = issue_sel_7_1 & entries_ex_7_bits_deps_ld_2; // @[OneHot.scala:83:30] wire _issue_entry_T_2523 = issue_sel_8 & entries_ex_8_bits_deps_ld_2; // @[OneHot.scala:83:30] wire _issue_entry_T_2524 = issue_sel_9 & entries_ex_9_bits_deps_ld_2; // @[OneHot.scala:83:30] wire _issue_entry_T_2525 = issue_sel_10 & entries_ex_10_bits_deps_ld_2; // @[OneHot.scala:83:30] wire _issue_entry_T_2526 = issue_sel_11 & entries_ex_11_bits_deps_ld_2; // @[OneHot.scala:83:30] wire _issue_entry_T_2527 = issue_sel_12 & entries_ex_12_bits_deps_ld_2; // @[OneHot.scala:83:30] wire _issue_entry_T_2528 = issue_sel_13 & entries_ex_13_bits_deps_ld_2; // @[OneHot.scala:83:30] wire _issue_entry_T_2529 = issue_sel_14 & entries_ex_14_bits_deps_ld_2; // @[OneHot.scala:83:30] wire _issue_entry_T_2530 = issue_sel_15 & entries_ex_15_bits_deps_ld_2; // @[OneHot.scala:83:30] wire _issue_entry_T_2531 = _issue_entry_T_2515 | _issue_entry_T_2516; // @[Mux.scala:30:73] wire _issue_entry_T_2532 = _issue_entry_T_2531 | _issue_entry_T_2517; // @[Mux.scala:30:73] wire _issue_entry_T_2533 = _issue_entry_T_2532 | _issue_entry_T_2518; // @[Mux.scala:30:73] wire _issue_entry_T_2534 = _issue_entry_T_2533 | _issue_entry_T_2519; // @[Mux.scala:30:73] wire _issue_entry_T_2535 = _issue_entry_T_2534 | _issue_entry_T_2520; // @[Mux.scala:30:73] wire _issue_entry_T_2536 = _issue_entry_T_2535 | _issue_entry_T_2521; // @[Mux.scala:30:73] wire _issue_entry_T_2537 = _issue_entry_T_2536 | _issue_entry_T_2522; // @[Mux.scala:30:73] wire _issue_entry_T_2538 = _issue_entry_T_2537 | _issue_entry_T_2523; // @[Mux.scala:30:73] wire _issue_entry_T_2539 = _issue_entry_T_2538 | _issue_entry_T_2524; // @[Mux.scala:30:73] wire _issue_entry_T_2540 = _issue_entry_T_2539 | _issue_entry_T_2525; // @[Mux.scala:30:73] wire _issue_entry_T_2541 = _issue_entry_T_2540 | _issue_entry_T_2526; // @[Mux.scala:30:73] wire _issue_entry_T_2542 = _issue_entry_T_2541 | _issue_entry_T_2527; // @[Mux.scala:30:73] wire _issue_entry_T_2543 = _issue_entry_T_2542 | _issue_entry_T_2528; // @[Mux.scala:30:73] wire _issue_entry_T_2544 = _issue_entry_T_2543 | _issue_entry_T_2529; // @[Mux.scala:30:73] wire _issue_entry_T_2545 = _issue_entry_T_2544 | _issue_entry_T_2530; // @[Mux.scala:30:73] assign _issue_entry_WIRE_170 = _issue_entry_T_2545; // @[Mux.scala:30:73] assign _issue_entry_WIRE_167_2 = _issue_entry_WIRE_170; // @[Mux.scala:30:73] wire _issue_entry_T_2546 = issue_sel_0_1 & entries_ex_0_bits_deps_ld_3; // @[OneHot.scala:83:30] wire _issue_entry_T_2547 = issue_sel_1_1 & entries_ex_1_bits_deps_ld_3; // @[OneHot.scala:83:30] wire _issue_entry_T_2548 = issue_sel_2_1 & entries_ex_2_bits_deps_ld_3; // @[OneHot.scala:83:30] wire _issue_entry_T_2549 = issue_sel_3_1 & entries_ex_3_bits_deps_ld_3; // @[OneHot.scala:83:30] wire _issue_entry_T_2550 = issue_sel_4_1 & entries_ex_4_bits_deps_ld_3; // @[OneHot.scala:83:30] wire _issue_entry_T_2551 = issue_sel_5_1 & entries_ex_5_bits_deps_ld_3; // @[OneHot.scala:83:30] wire _issue_entry_T_2552 = issue_sel_6_1 & entries_ex_6_bits_deps_ld_3; // @[OneHot.scala:83:30] wire _issue_entry_T_2553 = issue_sel_7_1 & entries_ex_7_bits_deps_ld_3; // @[OneHot.scala:83:30] wire _issue_entry_T_2554 = issue_sel_8 & entries_ex_8_bits_deps_ld_3; // @[OneHot.scala:83:30] wire _issue_entry_T_2555 = issue_sel_9 & entries_ex_9_bits_deps_ld_3; // @[OneHot.scala:83:30] wire _issue_entry_T_2556 = issue_sel_10 & entries_ex_10_bits_deps_ld_3; // @[OneHot.scala:83:30] wire _issue_entry_T_2557 = issue_sel_11 & entries_ex_11_bits_deps_ld_3; // @[OneHot.scala:83:30] wire _issue_entry_T_2558 = issue_sel_12 & entries_ex_12_bits_deps_ld_3; // @[OneHot.scala:83:30] wire _issue_entry_T_2559 = issue_sel_13 & entries_ex_13_bits_deps_ld_3; // @[OneHot.scala:83:30] wire _issue_entry_T_2560 = issue_sel_14 & entries_ex_14_bits_deps_ld_3; // @[OneHot.scala:83:30] wire _issue_entry_T_2561 = issue_sel_15 & entries_ex_15_bits_deps_ld_3; // @[OneHot.scala:83:30] wire _issue_entry_T_2562 = _issue_entry_T_2546 | _issue_entry_T_2547; // @[Mux.scala:30:73] wire _issue_entry_T_2563 = _issue_entry_T_2562 | _issue_entry_T_2548; // @[Mux.scala:30:73] wire _issue_entry_T_2564 = _issue_entry_T_2563 | _issue_entry_T_2549; // @[Mux.scala:30:73] wire _issue_entry_T_2565 = _issue_entry_T_2564 | _issue_entry_T_2550; // @[Mux.scala:30:73] wire _issue_entry_T_2566 = _issue_entry_T_2565 | _issue_entry_T_2551; // @[Mux.scala:30:73] wire _issue_entry_T_2567 = _issue_entry_T_2566 | _issue_entry_T_2552; // @[Mux.scala:30:73] wire _issue_entry_T_2568 = _issue_entry_T_2567 | _issue_entry_T_2553; // @[Mux.scala:30:73] wire _issue_entry_T_2569 = _issue_entry_T_2568 | _issue_entry_T_2554; // @[Mux.scala:30:73] wire _issue_entry_T_2570 = _issue_entry_T_2569 | _issue_entry_T_2555; // @[Mux.scala:30:73] wire _issue_entry_T_2571 = _issue_entry_T_2570 | _issue_entry_T_2556; // @[Mux.scala:30:73] wire _issue_entry_T_2572 = _issue_entry_T_2571 | _issue_entry_T_2557; // @[Mux.scala:30:73] wire _issue_entry_T_2573 = _issue_entry_T_2572 | _issue_entry_T_2558; // @[Mux.scala:30:73] wire _issue_entry_T_2574 = _issue_entry_T_2573 | _issue_entry_T_2559; // @[Mux.scala:30:73] wire _issue_entry_T_2575 = _issue_entry_T_2574 | _issue_entry_T_2560; // @[Mux.scala:30:73] wire _issue_entry_T_2576 = _issue_entry_T_2575 | _issue_entry_T_2561; // @[Mux.scala:30:73] assign _issue_entry_WIRE_171 = _issue_entry_T_2576; // @[Mux.scala:30:73] assign _issue_entry_WIRE_167_3 = _issue_entry_WIRE_171; // @[Mux.scala:30:73] wire _issue_entry_T_2577 = issue_sel_0_1 & entries_ex_0_bits_deps_ld_4; // @[OneHot.scala:83:30] wire _issue_entry_T_2578 = issue_sel_1_1 & entries_ex_1_bits_deps_ld_4; // @[OneHot.scala:83:30] wire _issue_entry_T_2579 = issue_sel_2_1 & entries_ex_2_bits_deps_ld_4; // @[OneHot.scala:83:30] wire _issue_entry_T_2580 = issue_sel_3_1 & entries_ex_3_bits_deps_ld_4; // @[OneHot.scala:83:30] wire _issue_entry_T_2581 = issue_sel_4_1 & entries_ex_4_bits_deps_ld_4; // @[OneHot.scala:83:30] wire _issue_entry_T_2582 = issue_sel_5_1 & entries_ex_5_bits_deps_ld_4; // @[OneHot.scala:83:30] wire _issue_entry_T_2583 = issue_sel_6_1 & entries_ex_6_bits_deps_ld_4; // @[OneHot.scala:83:30] wire _issue_entry_T_2584 = issue_sel_7_1 & entries_ex_7_bits_deps_ld_4; // @[OneHot.scala:83:30] wire _issue_entry_T_2585 = issue_sel_8 & entries_ex_8_bits_deps_ld_4; // @[OneHot.scala:83:30] wire _issue_entry_T_2586 = issue_sel_9 & entries_ex_9_bits_deps_ld_4; // @[OneHot.scala:83:30] wire _issue_entry_T_2587 = issue_sel_10 & entries_ex_10_bits_deps_ld_4; // @[OneHot.scala:83:30] wire _issue_entry_T_2588 = issue_sel_11 & entries_ex_11_bits_deps_ld_4; // @[OneHot.scala:83:30] wire _issue_entry_T_2589 = issue_sel_12 & entries_ex_12_bits_deps_ld_4; // @[OneHot.scala:83:30] wire _issue_entry_T_2590 = issue_sel_13 & entries_ex_13_bits_deps_ld_4; // @[OneHot.scala:83:30] wire _issue_entry_T_2591 = issue_sel_14 & entries_ex_14_bits_deps_ld_4; // @[OneHot.scala:83:30] wire _issue_entry_T_2592 = issue_sel_15 & entries_ex_15_bits_deps_ld_4; // @[OneHot.scala:83:30] wire _issue_entry_T_2593 = _issue_entry_T_2577 | _issue_entry_T_2578; // @[Mux.scala:30:73] wire _issue_entry_T_2594 = _issue_entry_T_2593 | _issue_entry_T_2579; // @[Mux.scala:30:73] wire _issue_entry_T_2595 = _issue_entry_T_2594 | _issue_entry_T_2580; // @[Mux.scala:30:73] wire _issue_entry_T_2596 = _issue_entry_T_2595 | _issue_entry_T_2581; // @[Mux.scala:30:73] wire _issue_entry_T_2597 = _issue_entry_T_2596 | _issue_entry_T_2582; // @[Mux.scala:30:73] wire _issue_entry_T_2598 = _issue_entry_T_2597 | _issue_entry_T_2583; // @[Mux.scala:30:73] wire _issue_entry_T_2599 = _issue_entry_T_2598 | _issue_entry_T_2584; // @[Mux.scala:30:73] wire _issue_entry_T_2600 = _issue_entry_T_2599 | _issue_entry_T_2585; // @[Mux.scala:30:73] wire _issue_entry_T_2601 = _issue_entry_T_2600 | _issue_entry_T_2586; // @[Mux.scala:30:73] wire _issue_entry_T_2602 = _issue_entry_T_2601 | _issue_entry_T_2587; // @[Mux.scala:30:73] wire _issue_entry_T_2603 = _issue_entry_T_2602 | _issue_entry_T_2588; // @[Mux.scala:30:73] wire _issue_entry_T_2604 = _issue_entry_T_2603 | _issue_entry_T_2589; // @[Mux.scala:30:73] wire _issue_entry_T_2605 = _issue_entry_T_2604 | _issue_entry_T_2590; // @[Mux.scala:30:73] wire _issue_entry_T_2606 = _issue_entry_T_2605 | _issue_entry_T_2591; // @[Mux.scala:30:73] wire _issue_entry_T_2607 = _issue_entry_T_2606 | _issue_entry_T_2592; // @[Mux.scala:30:73] assign _issue_entry_WIRE_172 = _issue_entry_T_2607; // @[Mux.scala:30:73] assign _issue_entry_WIRE_167_4 = _issue_entry_WIRE_172; // @[Mux.scala:30:73] wire _issue_entry_T_2608 = issue_sel_0_1 & entries_ex_0_bits_deps_ld_5; // @[OneHot.scala:83:30] wire _issue_entry_T_2609 = issue_sel_1_1 & entries_ex_1_bits_deps_ld_5; // @[OneHot.scala:83:30] wire _issue_entry_T_2610 = issue_sel_2_1 & entries_ex_2_bits_deps_ld_5; // @[OneHot.scala:83:30] wire _issue_entry_T_2611 = issue_sel_3_1 & entries_ex_3_bits_deps_ld_5; // @[OneHot.scala:83:30] wire _issue_entry_T_2612 = issue_sel_4_1 & entries_ex_4_bits_deps_ld_5; // @[OneHot.scala:83:30] wire _issue_entry_T_2613 = issue_sel_5_1 & entries_ex_5_bits_deps_ld_5; // @[OneHot.scala:83:30] wire _issue_entry_T_2614 = issue_sel_6_1 & entries_ex_6_bits_deps_ld_5; // @[OneHot.scala:83:30] wire _issue_entry_T_2615 = issue_sel_7_1 & entries_ex_7_bits_deps_ld_5; // @[OneHot.scala:83:30] wire _issue_entry_T_2616 = issue_sel_8 & entries_ex_8_bits_deps_ld_5; // @[OneHot.scala:83:30] wire _issue_entry_T_2617 = issue_sel_9 & entries_ex_9_bits_deps_ld_5; // @[OneHot.scala:83:30] wire _issue_entry_T_2618 = issue_sel_10 & entries_ex_10_bits_deps_ld_5; // @[OneHot.scala:83:30] wire _issue_entry_T_2619 = issue_sel_11 & entries_ex_11_bits_deps_ld_5; // @[OneHot.scala:83:30] wire _issue_entry_T_2620 = issue_sel_12 & entries_ex_12_bits_deps_ld_5; // @[OneHot.scala:83:30] wire _issue_entry_T_2621 = issue_sel_13 & entries_ex_13_bits_deps_ld_5; // @[OneHot.scala:83:30] wire _issue_entry_T_2622 = issue_sel_14 & entries_ex_14_bits_deps_ld_5; // @[OneHot.scala:83:30] wire _issue_entry_T_2623 = issue_sel_15 & entries_ex_15_bits_deps_ld_5; // @[OneHot.scala:83:30] wire _issue_entry_T_2624 = _issue_entry_T_2608 | _issue_entry_T_2609; // @[Mux.scala:30:73] wire _issue_entry_T_2625 = _issue_entry_T_2624 | _issue_entry_T_2610; // @[Mux.scala:30:73] wire _issue_entry_T_2626 = _issue_entry_T_2625 | _issue_entry_T_2611; // @[Mux.scala:30:73] wire _issue_entry_T_2627 = _issue_entry_T_2626 | _issue_entry_T_2612; // @[Mux.scala:30:73] wire _issue_entry_T_2628 = _issue_entry_T_2627 | _issue_entry_T_2613; // @[Mux.scala:30:73] wire _issue_entry_T_2629 = _issue_entry_T_2628 | _issue_entry_T_2614; // @[Mux.scala:30:73] wire _issue_entry_T_2630 = _issue_entry_T_2629 | _issue_entry_T_2615; // @[Mux.scala:30:73] wire _issue_entry_T_2631 = _issue_entry_T_2630 | _issue_entry_T_2616; // @[Mux.scala:30:73] wire _issue_entry_T_2632 = _issue_entry_T_2631 | _issue_entry_T_2617; // @[Mux.scala:30:73] wire _issue_entry_T_2633 = _issue_entry_T_2632 | _issue_entry_T_2618; // @[Mux.scala:30:73] wire _issue_entry_T_2634 = _issue_entry_T_2633 | _issue_entry_T_2619; // @[Mux.scala:30:73] wire _issue_entry_T_2635 = _issue_entry_T_2634 | _issue_entry_T_2620; // @[Mux.scala:30:73] wire _issue_entry_T_2636 = _issue_entry_T_2635 | _issue_entry_T_2621; // @[Mux.scala:30:73] wire _issue_entry_T_2637 = _issue_entry_T_2636 | _issue_entry_T_2622; // @[Mux.scala:30:73] wire _issue_entry_T_2638 = _issue_entry_T_2637 | _issue_entry_T_2623; // @[Mux.scala:30:73] assign _issue_entry_WIRE_173 = _issue_entry_T_2638; // @[Mux.scala:30:73] assign _issue_entry_WIRE_167_5 = _issue_entry_WIRE_173; // @[Mux.scala:30:73] wire _issue_entry_T_2639 = issue_sel_0_1 & entries_ex_0_bits_deps_ld_6; // @[OneHot.scala:83:30] wire _issue_entry_T_2640 = issue_sel_1_1 & entries_ex_1_bits_deps_ld_6; // @[OneHot.scala:83:30] wire _issue_entry_T_2641 = issue_sel_2_1 & entries_ex_2_bits_deps_ld_6; // @[OneHot.scala:83:30] wire _issue_entry_T_2642 = issue_sel_3_1 & entries_ex_3_bits_deps_ld_6; // @[OneHot.scala:83:30] wire _issue_entry_T_2643 = issue_sel_4_1 & entries_ex_4_bits_deps_ld_6; // @[OneHot.scala:83:30] wire _issue_entry_T_2644 = issue_sel_5_1 & entries_ex_5_bits_deps_ld_6; // @[OneHot.scala:83:30] wire _issue_entry_T_2645 = issue_sel_6_1 & entries_ex_6_bits_deps_ld_6; // @[OneHot.scala:83:30] wire _issue_entry_T_2646 = issue_sel_7_1 & entries_ex_7_bits_deps_ld_6; // @[OneHot.scala:83:30] wire _issue_entry_T_2647 = issue_sel_8 & entries_ex_8_bits_deps_ld_6; // @[OneHot.scala:83:30] wire _issue_entry_T_2648 = issue_sel_9 & entries_ex_9_bits_deps_ld_6; // @[OneHot.scala:83:30] wire _issue_entry_T_2649 = issue_sel_10 & entries_ex_10_bits_deps_ld_6; // @[OneHot.scala:83:30] wire _issue_entry_T_2650 = issue_sel_11 & entries_ex_11_bits_deps_ld_6; // @[OneHot.scala:83:30] wire _issue_entry_T_2651 = issue_sel_12 & entries_ex_12_bits_deps_ld_6; // @[OneHot.scala:83:30] wire _issue_entry_T_2652 = issue_sel_13 & entries_ex_13_bits_deps_ld_6; // @[OneHot.scala:83:30] wire _issue_entry_T_2653 = issue_sel_14 & entries_ex_14_bits_deps_ld_6; // @[OneHot.scala:83:30] wire _issue_entry_T_2654 = issue_sel_15 & entries_ex_15_bits_deps_ld_6; // @[OneHot.scala:83:30] wire _issue_entry_T_2655 = _issue_entry_T_2639 | _issue_entry_T_2640; // @[Mux.scala:30:73] wire _issue_entry_T_2656 = _issue_entry_T_2655 | _issue_entry_T_2641; // @[Mux.scala:30:73] wire _issue_entry_T_2657 = _issue_entry_T_2656 | _issue_entry_T_2642; // @[Mux.scala:30:73] wire _issue_entry_T_2658 = _issue_entry_T_2657 | _issue_entry_T_2643; // @[Mux.scala:30:73] wire _issue_entry_T_2659 = _issue_entry_T_2658 | _issue_entry_T_2644; // @[Mux.scala:30:73] wire _issue_entry_T_2660 = _issue_entry_T_2659 | _issue_entry_T_2645; // @[Mux.scala:30:73] wire _issue_entry_T_2661 = _issue_entry_T_2660 | _issue_entry_T_2646; // @[Mux.scala:30:73] wire _issue_entry_T_2662 = _issue_entry_T_2661 | _issue_entry_T_2647; // @[Mux.scala:30:73] wire _issue_entry_T_2663 = _issue_entry_T_2662 | _issue_entry_T_2648; // @[Mux.scala:30:73] wire _issue_entry_T_2664 = _issue_entry_T_2663 | _issue_entry_T_2649; // @[Mux.scala:30:73] wire _issue_entry_T_2665 = _issue_entry_T_2664 | _issue_entry_T_2650; // @[Mux.scala:30:73] wire _issue_entry_T_2666 = _issue_entry_T_2665 | _issue_entry_T_2651; // @[Mux.scala:30:73] wire _issue_entry_T_2667 = _issue_entry_T_2666 | _issue_entry_T_2652; // @[Mux.scala:30:73] wire _issue_entry_T_2668 = _issue_entry_T_2667 | _issue_entry_T_2653; // @[Mux.scala:30:73] wire _issue_entry_T_2669 = _issue_entry_T_2668 | _issue_entry_T_2654; // @[Mux.scala:30:73] assign _issue_entry_WIRE_174 = _issue_entry_T_2669; // @[Mux.scala:30:73] assign _issue_entry_WIRE_167_6 = _issue_entry_WIRE_174; // @[Mux.scala:30:73] wire _issue_entry_T_2670 = issue_sel_0_1 & entries_ex_0_bits_deps_ld_7; // @[OneHot.scala:83:30] wire _issue_entry_T_2671 = issue_sel_1_1 & entries_ex_1_bits_deps_ld_7; // @[OneHot.scala:83:30] wire _issue_entry_T_2672 = issue_sel_2_1 & entries_ex_2_bits_deps_ld_7; // @[OneHot.scala:83:30] wire _issue_entry_T_2673 = issue_sel_3_1 & entries_ex_3_bits_deps_ld_7; // @[OneHot.scala:83:30] wire _issue_entry_T_2674 = issue_sel_4_1 & entries_ex_4_bits_deps_ld_7; // @[OneHot.scala:83:30] wire _issue_entry_T_2675 = issue_sel_5_1 & entries_ex_5_bits_deps_ld_7; // @[OneHot.scala:83:30] wire _issue_entry_T_2676 = issue_sel_6_1 & entries_ex_6_bits_deps_ld_7; // @[OneHot.scala:83:30] wire _issue_entry_T_2677 = issue_sel_7_1 & entries_ex_7_bits_deps_ld_7; // @[OneHot.scala:83:30] wire _issue_entry_T_2678 = issue_sel_8 & entries_ex_8_bits_deps_ld_7; // @[OneHot.scala:83:30] wire _issue_entry_T_2679 = issue_sel_9 & entries_ex_9_bits_deps_ld_7; // @[OneHot.scala:83:30] wire _issue_entry_T_2680 = issue_sel_10 & entries_ex_10_bits_deps_ld_7; // @[OneHot.scala:83:30] wire _issue_entry_T_2681 = issue_sel_11 & entries_ex_11_bits_deps_ld_7; // @[OneHot.scala:83:30] wire _issue_entry_T_2682 = issue_sel_12 & entries_ex_12_bits_deps_ld_7; // @[OneHot.scala:83:30] wire _issue_entry_T_2683 = issue_sel_13 & entries_ex_13_bits_deps_ld_7; // @[OneHot.scala:83:30] wire _issue_entry_T_2684 = issue_sel_14 & entries_ex_14_bits_deps_ld_7; // @[OneHot.scala:83:30] wire _issue_entry_T_2685 = issue_sel_15 & entries_ex_15_bits_deps_ld_7; // @[OneHot.scala:83:30] wire _issue_entry_T_2686 = _issue_entry_T_2670 | _issue_entry_T_2671; // @[Mux.scala:30:73] wire _issue_entry_T_2687 = _issue_entry_T_2686 | _issue_entry_T_2672; // @[Mux.scala:30:73] wire _issue_entry_T_2688 = _issue_entry_T_2687 | _issue_entry_T_2673; // @[Mux.scala:30:73] wire _issue_entry_T_2689 = _issue_entry_T_2688 | _issue_entry_T_2674; // @[Mux.scala:30:73] wire _issue_entry_T_2690 = _issue_entry_T_2689 | _issue_entry_T_2675; // @[Mux.scala:30:73] wire _issue_entry_T_2691 = _issue_entry_T_2690 | _issue_entry_T_2676; // @[Mux.scala:30:73] wire _issue_entry_T_2692 = _issue_entry_T_2691 | _issue_entry_T_2677; // @[Mux.scala:30:73] wire _issue_entry_T_2693 = _issue_entry_T_2692 | _issue_entry_T_2678; // @[Mux.scala:30:73] wire _issue_entry_T_2694 = _issue_entry_T_2693 | _issue_entry_T_2679; // @[Mux.scala:30:73] wire _issue_entry_T_2695 = _issue_entry_T_2694 | _issue_entry_T_2680; // @[Mux.scala:30:73] wire _issue_entry_T_2696 = _issue_entry_T_2695 | _issue_entry_T_2681; // @[Mux.scala:30:73] wire _issue_entry_T_2697 = _issue_entry_T_2696 | _issue_entry_T_2682; // @[Mux.scala:30:73] wire _issue_entry_T_2698 = _issue_entry_T_2697 | _issue_entry_T_2683; // @[Mux.scala:30:73] wire _issue_entry_T_2699 = _issue_entry_T_2698 | _issue_entry_T_2684; // @[Mux.scala:30:73] wire _issue_entry_T_2700 = _issue_entry_T_2699 | _issue_entry_T_2685; // @[Mux.scala:30:73] assign _issue_entry_WIRE_175 = _issue_entry_T_2700; // @[Mux.scala:30:73] assign _issue_entry_WIRE_167_7 = _issue_entry_WIRE_175; // @[Mux.scala:30:73] wire [6:0] _issue_entry_WIRE_182_inst_funct; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_cmd_cmd_inst_funct = _issue_entry_WIRE_176_cmd_inst_funct; // @[Mux.scala:30:73] wire [4:0] _issue_entry_WIRE_182_inst_rs2; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_cmd_cmd_inst_rs2 = _issue_entry_WIRE_176_cmd_inst_rs2; // @[Mux.scala:30:73] wire [4:0] _issue_entry_WIRE_182_inst_rs1; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_cmd_cmd_inst_rs1 = _issue_entry_WIRE_176_cmd_inst_rs1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_182_inst_xd; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_cmd_cmd_inst_xd = _issue_entry_WIRE_176_cmd_inst_xd; // @[Mux.scala:30:73] wire _issue_entry_WIRE_182_inst_xs1; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_cmd_cmd_inst_xs1 = _issue_entry_WIRE_176_cmd_inst_xs1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_182_inst_xs2; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_cmd_cmd_inst_xs2 = _issue_entry_WIRE_176_cmd_inst_xs2; // @[Mux.scala:30:73] wire [4:0] _issue_entry_WIRE_182_inst_rd; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_cmd_cmd_inst_rd = _issue_entry_WIRE_176_cmd_inst_rd; // @[Mux.scala:30:73] wire [6:0] _issue_entry_WIRE_182_inst_opcode; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_cmd_cmd_inst_opcode = _issue_entry_WIRE_176_cmd_inst_opcode; // @[Mux.scala:30:73] wire [63:0] _issue_entry_WIRE_182_rs1; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_cmd_cmd_rs1 = _issue_entry_WIRE_176_cmd_rs1; // @[Mux.scala:30:73] wire [63:0] _issue_entry_WIRE_182_rs2; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_cmd_cmd_rs2 = _issue_entry_WIRE_176_cmd_rs2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_182_status_debug; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_cmd_cmd_status_debug = _issue_entry_WIRE_176_cmd_status_debug; // @[Mux.scala:30:73] wire _issue_entry_WIRE_182_status_cease; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_cmd_cmd_status_cease = _issue_entry_WIRE_176_cmd_status_cease; // @[Mux.scala:30:73] wire _issue_entry_WIRE_182_status_wfi; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_cmd_cmd_status_wfi = _issue_entry_WIRE_176_cmd_status_wfi; // @[Mux.scala:30:73] wire [31:0] _issue_entry_WIRE_182_status_isa; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_cmd_cmd_status_isa = _issue_entry_WIRE_176_cmd_status_isa; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_182_status_dprv; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_cmd_cmd_status_dprv = _issue_entry_WIRE_176_cmd_status_dprv; // @[Mux.scala:30:73] wire _issue_entry_WIRE_182_status_dv; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_cmd_cmd_status_dv = _issue_entry_WIRE_176_cmd_status_dv; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_182_status_prv; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_cmd_cmd_status_prv = _issue_entry_WIRE_176_cmd_status_prv; // @[Mux.scala:30:73] wire _issue_entry_WIRE_182_status_v; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_cmd_cmd_status_v = _issue_entry_WIRE_176_cmd_status_v; // @[Mux.scala:30:73] wire _issue_entry_WIRE_182_status_sd; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_cmd_cmd_status_sd = _issue_entry_WIRE_176_cmd_status_sd; // @[Mux.scala:30:73] wire [22:0] _issue_entry_WIRE_182_status_zero2; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_cmd_cmd_status_zero2 = _issue_entry_WIRE_176_cmd_status_zero2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_182_status_mpv; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_cmd_cmd_status_mpv = _issue_entry_WIRE_176_cmd_status_mpv; // @[Mux.scala:30:73] wire _issue_entry_WIRE_182_status_gva; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_cmd_cmd_status_gva = _issue_entry_WIRE_176_cmd_status_gva; // @[Mux.scala:30:73] wire _issue_entry_WIRE_182_status_mbe; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_cmd_cmd_status_mbe = _issue_entry_WIRE_176_cmd_status_mbe; // @[Mux.scala:30:73] wire _issue_entry_WIRE_182_status_sbe; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_cmd_cmd_status_sbe = _issue_entry_WIRE_176_cmd_status_sbe; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_182_status_sxl; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_cmd_cmd_status_sxl = _issue_entry_WIRE_176_cmd_status_sxl; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_182_status_uxl; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_cmd_cmd_status_uxl = _issue_entry_WIRE_176_cmd_status_uxl; // @[Mux.scala:30:73] wire _issue_entry_WIRE_182_status_sd_rv32; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_cmd_cmd_status_sd_rv32 = _issue_entry_WIRE_176_cmd_status_sd_rv32; // @[Mux.scala:30:73] wire [7:0] _issue_entry_WIRE_182_status_zero1; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_cmd_cmd_status_zero1 = _issue_entry_WIRE_176_cmd_status_zero1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_182_status_tsr; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_cmd_cmd_status_tsr = _issue_entry_WIRE_176_cmd_status_tsr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_182_status_tw; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_cmd_cmd_status_tw = _issue_entry_WIRE_176_cmd_status_tw; // @[Mux.scala:30:73] wire _issue_entry_WIRE_182_status_tvm; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_cmd_cmd_status_tvm = _issue_entry_WIRE_176_cmd_status_tvm; // @[Mux.scala:30:73] wire _issue_entry_WIRE_182_status_mxr; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_cmd_cmd_status_mxr = _issue_entry_WIRE_176_cmd_status_mxr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_182_status_sum; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_cmd_cmd_status_sum = _issue_entry_WIRE_176_cmd_status_sum; // @[Mux.scala:30:73] wire _issue_entry_WIRE_182_status_mprv; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_cmd_cmd_status_mprv = _issue_entry_WIRE_176_cmd_status_mprv; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_182_status_xs; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_cmd_cmd_status_xs = _issue_entry_WIRE_176_cmd_status_xs; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_182_status_fs; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_cmd_cmd_status_fs = _issue_entry_WIRE_176_cmd_status_fs; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_182_status_mpp; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_cmd_cmd_status_mpp = _issue_entry_WIRE_176_cmd_status_mpp; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_182_status_vs; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_cmd_cmd_status_vs = _issue_entry_WIRE_176_cmd_status_vs; // @[Mux.scala:30:73] wire _issue_entry_WIRE_182_status_spp; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_cmd_cmd_status_spp = _issue_entry_WIRE_176_cmd_status_spp; // @[Mux.scala:30:73] wire _issue_entry_WIRE_182_status_mpie; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_cmd_cmd_status_mpie = _issue_entry_WIRE_176_cmd_status_mpie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_182_status_ube; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_cmd_cmd_status_ube = _issue_entry_WIRE_176_cmd_status_ube; // @[Mux.scala:30:73] wire _issue_entry_WIRE_182_status_spie; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_cmd_cmd_status_spie = _issue_entry_WIRE_176_cmd_status_spie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_182_status_upie; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_cmd_cmd_status_upie = _issue_entry_WIRE_176_cmd_status_upie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_182_status_mie; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_cmd_cmd_status_mie = _issue_entry_WIRE_176_cmd_status_mie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_182_status_hie; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_cmd_cmd_status_hie = _issue_entry_WIRE_176_cmd_status_hie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_182_status_sie; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_cmd_cmd_status_sie = _issue_entry_WIRE_176_cmd_status_sie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_182_status_uie; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_cmd_cmd_status_uie = _issue_entry_WIRE_176_cmd_status_uie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_179_valid; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_cmd_rob_id_valid = _issue_entry_WIRE_176_rob_id_valid; // @[Mux.scala:30:73] wire [5:0] _issue_entry_WIRE_179_bits; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_cmd_rob_id_bits = _issue_entry_WIRE_176_rob_id_bits; // @[Mux.scala:30:73] wire _issue_entry_WIRE_178; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_cmd_from_matmul_fsm = _issue_entry_WIRE_176_from_matmul_fsm; // @[Mux.scala:30:73] wire _issue_entry_WIRE_177; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_cmd_from_conv_fsm = _issue_entry_WIRE_176_from_conv_fsm; // @[Mux.scala:30:73] wire _issue_entry_T_2701 = issue_sel_0_1 & entries_ex_0_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_2702 = issue_sel_1_1 & entries_ex_1_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_2703 = issue_sel_2_1 & entries_ex_2_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_2704 = issue_sel_3_1 & entries_ex_3_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_2705 = issue_sel_4_1 & entries_ex_4_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_2706 = issue_sel_5_1 & entries_ex_5_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_2707 = issue_sel_6_1 & entries_ex_6_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_2708 = issue_sel_7_1 & entries_ex_7_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_2709 = issue_sel_8 & entries_ex_8_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_2710 = issue_sel_9 & entries_ex_9_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_2711 = issue_sel_10 & entries_ex_10_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_2712 = issue_sel_11 & entries_ex_11_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_2713 = issue_sel_12 & entries_ex_12_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_2714 = issue_sel_13 & entries_ex_13_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_2715 = issue_sel_14 & entries_ex_14_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_2716 = issue_sel_15 & entries_ex_15_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_2717 = _issue_entry_T_2701 | _issue_entry_T_2702; // @[Mux.scala:30:73] wire _issue_entry_T_2718 = _issue_entry_T_2717 | _issue_entry_T_2703; // @[Mux.scala:30:73] wire _issue_entry_T_2719 = _issue_entry_T_2718 | _issue_entry_T_2704; // @[Mux.scala:30:73] wire _issue_entry_T_2720 = _issue_entry_T_2719 | _issue_entry_T_2705; // @[Mux.scala:30:73] wire _issue_entry_T_2721 = _issue_entry_T_2720 | _issue_entry_T_2706; // @[Mux.scala:30:73] wire _issue_entry_T_2722 = _issue_entry_T_2721 | _issue_entry_T_2707; // @[Mux.scala:30:73] wire _issue_entry_T_2723 = _issue_entry_T_2722 | _issue_entry_T_2708; // @[Mux.scala:30:73] wire _issue_entry_T_2724 = _issue_entry_T_2723 | _issue_entry_T_2709; // @[Mux.scala:30:73] wire _issue_entry_T_2725 = _issue_entry_T_2724 | _issue_entry_T_2710; // @[Mux.scala:30:73] wire _issue_entry_T_2726 = _issue_entry_T_2725 | _issue_entry_T_2711; // @[Mux.scala:30:73] wire _issue_entry_T_2727 = _issue_entry_T_2726 | _issue_entry_T_2712; // @[Mux.scala:30:73] wire _issue_entry_T_2728 = _issue_entry_T_2727 | _issue_entry_T_2713; // @[Mux.scala:30:73] wire _issue_entry_T_2729 = _issue_entry_T_2728 | _issue_entry_T_2714; // @[Mux.scala:30:73] wire _issue_entry_T_2730 = _issue_entry_T_2729 | _issue_entry_T_2715; // @[Mux.scala:30:73] wire _issue_entry_T_2731 = _issue_entry_T_2730 | _issue_entry_T_2716; // @[Mux.scala:30:73] assign _issue_entry_WIRE_177 = _issue_entry_T_2731; // @[Mux.scala:30:73] assign _issue_entry_WIRE_176_from_conv_fsm = _issue_entry_WIRE_177; // @[Mux.scala:30:73] wire _issue_entry_T_2732 = issue_sel_0_1 & entries_ex_0_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_2733 = issue_sel_1_1 & entries_ex_1_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_2734 = issue_sel_2_1 & entries_ex_2_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_2735 = issue_sel_3_1 & entries_ex_3_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_2736 = issue_sel_4_1 & entries_ex_4_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_2737 = issue_sel_5_1 & entries_ex_5_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_2738 = issue_sel_6_1 & entries_ex_6_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_2739 = issue_sel_7_1 & entries_ex_7_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_2740 = issue_sel_8 & entries_ex_8_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_2741 = issue_sel_9 & entries_ex_9_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_2742 = issue_sel_10 & entries_ex_10_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_2743 = issue_sel_11 & entries_ex_11_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_2744 = issue_sel_12 & entries_ex_12_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_2745 = issue_sel_13 & entries_ex_13_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_2746 = issue_sel_14 & entries_ex_14_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_2747 = issue_sel_15 & entries_ex_15_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_2748 = _issue_entry_T_2732 | _issue_entry_T_2733; // @[Mux.scala:30:73] wire _issue_entry_T_2749 = _issue_entry_T_2748 | _issue_entry_T_2734; // @[Mux.scala:30:73] wire _issue_entry_T_2750 = _issue_entry_T_2749 | _issue_entry_T_2735; // @[Mux.scala:30:73] wire _issue_entry_T_2751 = _issue_entry_T_2750 | _issue_entry_T_2736; // @[Mux.scala:30:73] wire _issue_entry_T_2752 = _issue_entry_T_2751 | _issue_entry_T_2737; // @[Mux.scala:30:73] wire _issue_entry_T_2753 = _issue_entry_T_2752 | _issue_entry_T_2738; // @[Mux.scala:30:73] wire _issue_entry_T_2754 = _issue_entry_T_2753 | _issue_entry_T_2739; // @[Mux.scala:30:73] wire _issue_entry_T_2755 = _issue_entry_T_2754 | _issue_entry_T_2740; // @[Mux.scala:30:73] wire _issue_entry_T_2756 = _issue_entry_T_2755 | _issue_entry_T_2741; // @[Mux.scala:30:73] wire _issue_entry_T_2757 = _issue_entry_T_2756 | _issue_entry_T_2742; // @[Mux.scala:30:73] wire _issue_entry_T_2758 = _issue_entry_T_2757 | _issue_entry_T_2743; // @[Mux.scala:30:73] wire _issue_entry_T_2759 = _issue_entry_T_2758 | _issue_entry_T_2744; // @[Mux.scala:30:73] wire _issue_entry_T_2760 = _issue_entry_T_2759 | _issue_entry_T_2745; // @[Mux.scala:30:73] wire _issue_entry_T_2761 = _issue_entry_T_2760 | _issue_entry_T_2746; // @[Mux.scala:30:73] wire _issue_entry_T_2762 = _issue_entry_T_2761 | _issue_entry_T_2747; // @[Mux.scala:30:73] assign _issue_entry_WIRE_178 = _issue_entry_T_2762; // @[Mux.scala:30:73] assign _issue_entry_WIRE_176_from_matmul_fsm = _issue_entry_WIRE_178; // @[Mux.scala:30:73] wire _issue_entry_WIRE_181; // @[Mux.scala:30:73] assign _issue_entry_WIRE_176_rob_id_valid = _issue_entry_WIRE_179_valid; // @[Mux.scala:30:73] wire [5:0] _issue_entry_WIRE_180; // @[Mux.scala:30:73] assign _issue_entry_WIRE_176_rob_id_bits = _issue_entry_WIRE_179_bits; // @[Mux.scala:30:73] wire [5:0] _issue_entry_T_2763 = issue_sel_0_1 ? entries_ex_0_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30] wire [5:0] _issue_entry_T_2764 = issue_sel_1_1 ? entries_ex_1_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30] wire [5:0] _issue_entry_T_2765 = issue_sel_2_1 ? entries_ex_2_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30] wire [5:0] _issue_entry_T_2766 = issue_sel_3_1 ? entries_ex_3_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30] wire [5:0] _issue_entry_T_2767 = issue_sel_4_1 ? entries_ex_4_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30] wire [5:0] _issue_entry_T_2768 = issue_sel_5_1 ? entries_ex_5_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30] wire [5:0] _issue_entry_T_2769 = issue_sel_6_1 ? entries_ex_6_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30] wire [5:0] _issue_entry_T_2770 = issue_sel_7_1 ? entries_ex_7_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30] wire [5:0] _issue_entry_T_2771 = issue_sel_8 ? entries_ex_8_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30] wire [5:0] _issue_entry_T_2772 = issue_sel_9 ? entries_ex_9_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30] wire [5:0] _issue_entry_T_2773 = issue_sel_10 ? entries_ex_10_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30] wire [5:0] _issue_entry_T_2774 = issue_sel_11 ? entries_ex_11_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30] wire [5:0] _issue_entry_T_2775 = issue_sel_12 ? entries_ex_12_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30] wire [5:0] _issue_entry_T_2776 = issue_sel_13 ? entries_ex_13_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30] wire [5:0] _issue_entry_T_2777 = issue_sel_14 ? entries_ex_14_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30] wire [5:0] _issue_entry_T_2778 = issue_sel_15 ? entries_ex_15_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30] wire [5:0] _issue_entry_T_2779 = _issue_entry_T_2763 | _issue_entry_T_2764; // @[Mux.scala:30:73] wire [5:0] _issue_entry_T_2780 = _issue_entry_T_2779 | _issue_entry_T_2765; // @[Mux.scala:30:73] wire [5:0] _issue_entry_T_2781 = _issue_entry_T_2780 | _issue_entry_T_2766; // @[Mux.scala:30:73] wire [5:0] _issue_entry_T_2782 = _issue_entry_T_2781 | _issue_entry_T_2767; // @[Mux.scala:30:73] wire [5:0] _issue_entry_T_2783 = _issue_entry_T_2782 | _issue_entry_T_2768; // @[Mux.scala:30:73] wire [5:0] _issue_entry_T_2784 = _issue_entry_T_2783 | _issue_entry_T_2769; // @[Mux.scala:30:73] wire [5:0] _issue_entry_T_2785 = _issue_entry_T_2784 | _issue_entry_T_2770; // @[Mux.scala:30:73] wire [5:0] _issue_entry_T_2786 = _issue_entry_T_2785 | _issue_entry_T_2771; // @[Mux.scala:30:73] wire [5:0] _issue_entry_T_2787 = _issue_entry_T_2786 | _issue_entry_T_2772; // @[Mux.scala:30:73] wire [5:0] _issue_entry_T_2788 = _issue_entry_T_2787 | _issue_entry_T_2773; // @[Mux.scala:30:73] wire [5:0] _issue_entry_T_2789 = _issue_entry_T_2788 | _issue_entry_T_2774; // @[Mux.scala:30:73] wire [5:0] _issue_entry_T_2790 = _issue_entry_T_2789 | _issue_entry_T_2775; // @[Mux.scala:30:73] wire [5:0] _issue_entry_T_2791 = _issue_entry_T_2790 | _issue_entry_T_2776; // @[Mux.scala:30:73] wire [5:0] _issue_entry_T_2792 = _issue_entry_T_2791 | _issue_entry_T_2777; // @[Mux.scala:30:73] wire [5:0] _issue_entry_T_2793 = _issue_entry_T_2792 | _issue_entry_T_2778; // @[Mux.scala:30:73] assign _issue_entry_WIRE_180 = _issue_entry_T_2793; // @[Mux.scala:30:73] assign _issue_entry_WIRE_179_bits = _issue_entry_WIRE_180; // @[Mux.scala:30:73] wire _issue_entry_T_2794 = issue_sel_0_1 & entries_ex_0_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_2795 = issue_sel_1_1 & entries_ex_1_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_2796 = issue_sel_2_1 & entries_ex_2_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_2797 = issue_sel_3_1 & entries_ex_3_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_2798 = issue_sel_4_1 & entries_ex_4_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_2799 = issue_sel_5_1 & entries_ex_5_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_2800 = issue_sel_6_1 & entries_ex_6_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_2801 = issue_sel_7_1 & entries_ex_7_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_2802 = issue_sel_8 & entries_ex_8_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_2803 = issue_sel_9 & entries_ex_9_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_2804 = issue_sel_10 & entries_ex_10_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_2805 = issue_sel_11 & entries_ex_11_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_2806 = issue_sel_12 & entries_ex_12_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_2807 = issue_sel_13 & entries_ex_13_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_2808 = issue_sel_14 & entries_ex_14_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_2809 = issue_sel_15 & entries_ex_15_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_2810 = _issue_entry_T_2794 | _issue_entry_T_2795; // @[Mux.scala:30:73] wire _issue_entry_T_2811 = _issue_entry_T_2810 | _issue_entry_T_2796; // @[Mux.scala:30:73] wire _issue_entry_T_2812 = _issue_entry_T_2811 | _issue_entry_T_2797; // @[Mux.scala:30:73] wire _issue_entry_T_2813 = _issue_entry_T_2812 | _issue_entry_T_2798; // @[Mux.scala:30:73] wire _issue_entry_T_2814 = _issue_entry_T_2813 | _issue_entry_T_2799; // @[Mux.scala:30:73] wire _issue_entry_T_2815 = _issue_entry_T_2814 | _issue_entry_T_2800; // @[Mux.scala:30:73] wire _issue_entry_T_2816 = _issue_entry_T_2815 | _issue_entry_T_2801; // @[Mux.scala:30:73] wire _issue_entry_T_2817 = _issue_entry_T_2816 | _issue_entry_T_2802; // @[Mux.scala:30:73] wire _issue_entry_T_2818 = _issue_entry_T_2817 | _issue_entry_T_2803; // @[Mux.scala:30:73] wire _issue_entry_T_2819 = _issue_entry_T_2818 | _issue_entry_T_2804; // @[Mux.scala:30:73] wire _issue_entry_T_2820 = _issue_entry_T_2819 | _issue_entry_T_2805; // @[Mux.scala:30:73] wire _issue_entry_T_2821 = _issue_entry_T_2820 | _issue_entry_T_2806; // @[Mux.scala:30:73] wire _issue_entry_T_2822 = _issue_entry_T_2821 | _issue_entry_T_2807; // @[Mux.scala:30:73] wire _issue_entry_T_2823 = _issue_entry_T_2822 | _issue_entry_T_2808; // @[Mux.scala:30:73] wire _issue_entry_T_2824 = _issue_entry_T_2823 | _issue_entry_T_2809; // @[Mux.scala:30:73] assign _issue_entry_WIRE_181 = _issue_entry_T_2824; // @[Mux.scala:30:73] assign _issue_entry_WIRE_179_valid = _issue_entry_WIRE_181; // @[Mux.scala:30:73] wire [6:0] _issue_entry_WIRE_223_funct; // @[Mux.scala:30:73] assign _issue_entry_WIRE_176_cmd_inst_funct = _issue_entry_WIRE_182_inst_funct; // @[Mux.scala:30:73] wire [4:0] _issue_entry_WIRE_223_rs2; // @[Mux.scala:30:73] assign _issue_entry_WIRE_176_cmd_inst_rs2 = _issue_entry_WIRE_182_inst_rs2; // @[Mux.scala:30:73] wire [4:0] _issue_entry_WIRE_223_rs1; // @[Mux.scala:30:73] assign _issue_entry_WIRE_176_cmd_inst_rs1 = _issue_entry_WIRE_182_inst_rs1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_223_xd; // @[Mux.scala:30:73] assign _issue_entry_WIRE_176_cmd_inst_xd = _issue_entry_WIRE_182_inst_xd; // @[Mux.scala:30:73] wire _issue_entry_WIRE_223_xs1; // @[Mux.scala:30:73] assign _issue_entry_WIRE_176_cmd_inst_xs1 = _issue_entry_WIRE_182_inst_xs1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_223_xs2; // @[Mux.scala:30:73] assign _issue_entry_WIRE_176_cmd_inst_xs2 = _issue_entry_WIRE_182_inst_xs2; // @[Mux.scala:30:73] wire [4:0] _issue_entry_WIRE_223_rd; // @[Mux.scala:30:73] assign _issue_entry_WIRE_176_cmd_inst_rd = _issue_entry_WIRE_182_inst_rd; // @[Mux.scala:30:73] wire [6:0] _issue_entry_WIRE_223_opcode; // @[Mux.scala:30:73] assign _issue_entry_WIRE_176_cmd_inst_opcode = _issue_entry_WIRE_182_inst_opcode; // @[Mux.scala:30:73] wire [63:0] _issue_entry_WIRE_222; // @[Mux.scala:30:73] assign _issue_entry_WIRE_176_cmd_rs1 = _issue_entry_WIRE_182_rs1; // @[Mux.scala:30:73] wire [63:0] _issue_entry_WIRE_221; // @[Mux.scala:30:73] assign _issue_entry_WIRE_176_cmd_rs2 = _issue_entry_WIRE_182_rs2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_183_debug; // @[Mux.scala:30:73] assign _issue_entry_WIRE_176_cmd_status_debug = _issue_entry_WIRE_182_status_debug; // @[Mux.scala:30:73] wire _issue_entry_WIRE_183_cease; // @[Mux.scala:30:73] assign _issue_entry_WIRE_176_cmd_status_cease = _issue_entry_WIRE_182_status_cease; // @[Mux.scala:30:73] wire _issue_entry_WIRE_183_wfi; // @[Mux.scala:30:73] assign _issue_entry_WIRE_176_cmd_status_wfi = _issue_entry_WIRE_182_status_wfi; // @[Mux.scala:30:73] wire [31:0] _issue_entry_WIRE_183_isa; // @[Mux.scala:30:73] assign _issue_entry_WIRE_176_cmd_status_isa = _issue_entry_WIRE_182_status_isa; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_183_dprv; // @[Mux.scala:30:73] assign _issue_entry_WIRE_176_cmd_status_dprv = _issue_entry_WIRE_182_status_dprv; // @[Mux.scala:30:73] wire _issue_entry_WIRE_183_dv; // @[Mux.scala:30:73] assign _issue_entry_WIRE_176_cmd_status_dv = _issue_entry_WIRE_182_status_dv; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_183_prv; // @[Mux.scala:30:73] assign _issue_entry_WIRE_176_cmd_status_prv = _issue_entry_WIRE_182_status_prv; // @[Mux.scala:30:73] wire _issue_entry_WIRE_183_v; // @[Mux.scala:30:73] assign _issue_entry_WIRE_176_cmd_status_v = _issue_entry_WIRE_182_status_v; // @[Mux.scala:30:73] wire _issue_entry_WIRE_183_sd; // @[Mux.scala:30:73] assign _issue_entry_WIRE_176_cmd_status_sd = _issue_entry_WIRE_182_status_sd; // @[Mux.scala:30:73] wire [22:0] _issue_entry_WIRE_183_zero2; // @[Mux.scala:30:73] assign _issue_entry_WIRE_176_cmd_status_zero2 = _issue_entry_WIRE_182_status_zero2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_183_mpv; // @[Mux.scala:30:73] assign _issue_entry_WIRE_176_cmd_status_mpv = _issue_entry_WIRE_182_status_mpv; // @[Mux.scala:30:73] wire _issue_entry_WIRE_183_gva; // @[Mux.scala:30:73] assign _issue_entry_WIRE_176_cmd_status_gva = _issue_entry_WIRE_182_status_gva; // @[Mux.scala:30:73] wire _issue_entry_WIRE_183_mbe; // @[Mux.scala:30:73] assign _issue_entry_WIRE_176_cmd_status_mbe = _issue_entry_WIRE_182_status_mbe; // @[Mux.scala:30:73] wire _issue_entry_WIRE_183_sbe; // @[Mux.scala:30:73] assign _issue_entry_WIRE_176_cmd_status_sbe = _issue_entry_WIRE_182_status_sbe; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_183_sxl; // @[Mux.scala:30:73] assign _issue_entry_WIRE_176_cmd_status_sxl = _issue_entry_WIRE_182_status_sxl; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_183_uxl; // @[Mux.scala:30:73] assign _issue_entry_WIRE_176_cmd_status_uxl = _issue_entry_WIRE_182_status_uxl; // @[Mux.scala:30:73] wire _issue_entry_WIRE_183_sd_rv32; // @[Mux.scala:30:73] assign _issue_entry_WIRE_176_cmd_status_sd_rv32 = _issue_entry_WIRE_182_status_sd_rv32; // @[Mux.scala:30:73] wire [7:0] _issue_entry_WIRE_183_zero1; // @[Mux.scala:30:73] assign _issue_entry_WIRE_176_cmd_status_zero1 = _issue_entry_WIRE_182_status_zero1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_183_tsr; // @[Mux.scala:30:73] assign _issue_entry_WIRE_176_cmd_status_tsr = _issue_entry_WIRE_182_status_tsr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_183_tw; // @[Mux.scala:30:73] assign _issue_entry_WIRE_176_cmd_status_tw = _issue_entry_WIRE_182_status_tw; // @[Mux.scala:30:73] wire _issue_entry_WIRE_183_tvm; // @[Mux.scala:30:73] assign _issue_entry_WIRE_176_cmd_status_tvm = _issue_entry_WIRE_182_status_tvm; // @[Mux.scala:30:73] wire _issue_entry_WIRE_183_mxr; // @[Mux.scala:30:73] assign _issue_entry_WIRE_176_cmd_status_mxr = _issue_entry_WIRE_182_status_mxr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_183_sum; // @[Mux.scala:30:73] assign _issue_entry_WIRE_176_cmd_status_sum = _issue_entry_WIRE_182_status_sum; // @[Mux.scala:30:73] wire _issue_entry_WIRE_183_mprv; // @[Mux.scala:30:73] assign _issue_entry_WIRE_176_cmd_status_mprv = _issue_entry_WIRE_182_status_mprv; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_183_xs; // @[Mux.scala:30:73] assign _issue_entry_WIRE_176_cmd_status_xs = _issue_entry_WIRE_182_status_xs; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_183_fs; // @[Mux.scala:30:73] assign _issue_entry_WIRE_176_cmd_status_fs = _issue_entry_WIRE_182_status_fs; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_183_mpp; // @[Mux.scala:30:73] assign _issue_entry_WIRE_176_cmd_status_mpp = _issue_entry_WIRE_182_status_mpp; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_183_vs; // @[Mux.scala:30:73] assign _issue_entry_WIRE_176_cmd_status_vs = _issue_entry_WIRE_182_status_vs; // @[Mux.scala:30:73] wire _issue_entry_WIRE_183_spp; // @[Mux.scala:30:73] assign _issue_entry_WIRE_176_cmd_status_spp = _issue_entry_WIRE_182_status_spp; // @[Mux.scala:30:73] wire _issue_entry_WIRE_183_mpie; // @[Mux.scala:30:73] assign _issue_entry_WIRE_176_cmd_status_mpie = _issue_entry_WIRE_182_status_mpie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_183_ube; // @[Mux.scala:30:73] assign _issue_entry_WIRE_176_cmd_status_ube = _issue_entry_WIRE_182_status_ube; // @[Mux.scala:30:73] wire _issue_entry_WIRE_183_spie; // @[Mux.scala:30:73] assign _issue_entry_WIRE_176_cmd_status_spie = _issue_entry_WIRE_182_status_spie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_183_upie; // @[Mux.scala:30:73] assign _issue_entry_WIRE_176_cmd_status_upie = _issue_entry_WIRE_182_status_upie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_183_mie; // @[Mux.scala:30:73] assign _issue_entry_WIRE_176_cmd_status_mie = _issue_entry_WIRE_182_status_mie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_183_hie; // @[Mux.scala:30:73] assign _issue_entry_WIRE_176_cmd_status_hie = _issue_entry_WIRE_182_status_hie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_183_sie; // @[Mux.scala:30:73] assign _issue_entry_WIRE_176_cmd_status_sie = _issue_entry_WIRE_182_status_sie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_183_uie; // @[Mux.scala:30:73] assign _issue_entry_WIRE_176_cmd_status_uie = _issue_entry_WIRE_182_status_uie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_220; // @[Mux.scala:30:73] assign _issue_entry_WIRE_182_status_debug = _issue_entry_WIRE_183_debug; // @[Mux.scala:30:73] wire _issue_entry_WIRE_219; // @[Mux.scala:30:73] assign _issue_entry_WIRE_182_status_cease = _issue_entry_WIRE_183_cease; // @[Mux.scala:30:73] wire _issue_entry_WIRE_218; // @[Mux.scala:30:73] assign _issue_entry_WIRE_182_status_wfi = _issue_entry_WIRE_183_wfi; // @[Mux.scala:30:73] wire [31:0] _issue_entry_WIRE_217; // @[Mux.scala:30:73] assign _issue_entry_WIRE_182_status_isa = _issue_entry_WIRE_183_isa; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_216; // @[Mux.scala:30:73] assign _issue_entry_WIRE_182_status_dprv = _issue_entry_WIRE_183_dprv; // @[Mux.scala:30:73] wire _issue_entry_WIRE_215; // @[Mux.scala:30:73] assign _issue_entry_WIRE_182_status_dv = _issue_entry_WIRE_183_dv; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_214; // @[Mux.scala:30:73] assign _issue_entry_WIRE_182_status_prv = _issue_entry_WIRE_183_prv; // @[Mux.scala:30:73] wire _issue_entry_WIRE_213; // @[Mux.scala:30:73] assign _issue_entry_WIRE_182_status_v = _issue_entry_WIRE_183_v; // @[Mux.scala:30:73] wire _issue_entry_WIRE_212; // @[Mux.scala:30:73] assign _issue_entry_WIRE_182_status_sd = _issue_entry_WIRE_183_sd; // @[Mux.scala:30:73] wire [22:0] _issue_entry_WIRE_211; // @[Mux.scala:30:73] assign _issue_entry_WIRE_182_status_zero2 = _issue_entry_WIRE_183_zero2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_210; // @[Mux.scala:30:73] assign _issue_entry_WIRE_182_status_mpv = _issue_entry_WIRE_183_mpv; // @[Mux.scala:30:73] wire _issue_entry_WIRE_209; // @[Mux.scala:30:73] assign _issue_entry_WIRE_182_status_gva = _issue_entry_WIRE_183_gva; // @[Mux.scala:30:73] wire _issue_entry_WIRE_208; // @[Mux.scala:30:73] assign _issue_entry_WIRE_182_status_mbe = _issue_entry_WIRE_183_mbe; // @[Mux.scala:30:73] wire _issue_entry_WIRE_207; // @[Mux.scala:30:73] assign _issue_entry_WIRE_182_status_sbe = _issue_entry_WIRE_183_sbe; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_206; // @[Mux.scala:30:73] assign _issue_entry_WIRE_182_status_sxl = _issue_entry_WIRE_183_sxl; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_205; // @[Mux.scala:30:73] assign _issue_entry_WIRE_182_status_uxl = _issue_entry_WIRE_183_uxl; // @[Mux.scala:30:73] wire _issue_entry_WIRE_204; // @[Mux.scala:30:73] assign _issue_entry_WIRE_182_status_sd_rv32 = _issue_entry_WIRE_183_sd_rv32; // @[Mux.scala:30:73] wire [7:0] _issue_entry_WIRE_203; // @[Mux.scala:30:73] assign _issue_entry_WIRE_182_status_zero1 = _issue_entry_WIRE_183_zero1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_202; // @[Mux.scala:30:73] assign _issue_entry_WIRE_182_status_tsr = _issue_entry_WIRE_183_tsr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_201; // @[Mux.scala:30:73] assign _issue_entry_WIRE_182_status_tw = _issue_entry_WIRE_183_tw; // @[Mux.scala:30:73] wire _issue_entry_WIRE_200; // @[Mux.scala:30:73] assign _issue_entry_WIRE_182_status_tvm = _issue_entry_WIRE_183_tvm; // @[Mux.scala:30:73] wire _issue_entry_WIRE_199; // @[Mux.scala:30:73] assign _issue_entry_WIRE_182_status_mxr = _issue_entry_WIRE_183_mxr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_198; // @[Mux.scala:30:73] assign _issue_entry_WIRE_182_status_sum = _issue_entry_WIRE_183_sum; // @[Mux.scala:30:73] wire _issue_entry_WIRE_197; // @[Mux.scala:30:73] assign _issue_entry_WIRE_182_status_mprv = _issue_entry_WIRE_183_mprv; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_196; // @[Mux.scala:30:73] assign _issue_entry_WIRE_182_status_xs = _issue_entry_WIRE_183_xs; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_195; // @[Mux.scala:30:73] assign _issue_entry_WIRE_182_status_fs = _issue_entry_WIRE_183_fs; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_194; // @[Mux.scala:30:73] assign _issue_entry_WIRE_182_status_mpp = _issue_entry_WIRE_183_mpp; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_193; // @[Mux.scala:30:73] assign _issue_entry_WIRE_182_status_vs = _issue_entry_WIRE_183_vs; // @[Mux.scala:30:73] wire _issue_entry_WIRE_192; // @[Mux.scala:30:73] assign _issue_entry_WIRE_182_status_spp = _issue_entry_WIRE_183_spp; // @[Mux.scala:30:73] wire _issue_entry_WIRE_191; // @[Mux.scala:30:73] assign _issue_entry_WIRE_182_status_mpie = _issue_entry_WIRE_183_mpie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_190; // @[Mux.scala:30:73] assign _issue_entry_WIRE_182_status_ube = _issue_entry_WIRE_183_ube; // @[Mux.scala:30:73] wire _issue_entry_WIRE_189; // @[Mux.scala:30:73] assign _issue_entry_WIRE_182_status_spie = _issue_entry_WIRE_183_spie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_188; // @[Mux.scala:30:73] assign _issue_entry_WIRE_182_status_upie = _issue_entry_WIRE_183_upie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_187; // @[Mux.scala:30:73] assign _issue_entry_WIRE_182_status_mie = _issue_entry_WIRE_183_mie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_186; // @[Mux.scala:30:73] assign _issue_entry_WIRE_182_status_hie = _issue_entry_WIRE_183_hie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_185; // @[Mux.scala:30:73] assign _issue_entry_WIRE_182_status_sie = _issue_entry_WIRE_183_sie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_184; // @[Mux.scala:30:73] assign _issue_entry_WIRE_182_status_uie = _issue_entry_WIRE_183_uie; // @[Mux.scala:30:73] wire _issue_entry_T_2825 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30] wire _issue_entry_T_2826 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30] wire _issue_entry_T_2827 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30] wire _issue_entry_T_2828 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30] wire _issue_entry_T_2829 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30] wire _issue_entry_T_2830 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30] wire _issue_entry_T_2831 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30] wire _issue_entry_T_2832 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30] wire _issue_entry_T_2833 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30] wire _issue_entry_T_2834 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30] wire _issue_entry_T_2835 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30] wire _issue_entry_T_2836 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30] wire _issue_entry_T_2837 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30] wire _issue_entry_T_2838 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30] wire _issue_entry_T_2839 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30] wire _issue_entry_T_2840 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30] wire _issue_entry_T_2841 = _issue_entry_T_2825 | _issue_entry_T_2826; // @[Mux.scala:30:73] wire _issue_entry_T_2842 = _issue_entry_T_2841 | _issue_entry_T_2827; // @[Mux.scala:30:73] wire _issue_entry_T_2843 = _issue_entry_T_2842 | _issue_entry_T_2828; // @[Mux.scala:30:73] wire _issue_entry_T_2844 = _issue_entry_T_2843 | _issue_entry_T_2829; // @[Mux.scala:30:73] wire _issue_entry_T_2845 = _issue_entry_T_2844 | _issue_entry_T_2830; // @[Mux.scala:30:73] wire _issue_entry_T_2846 = _issue_entry_T_2845 | _issue_entry_T_2831; // @[Mux.scala:30:73] wire _issue_entry_T_2847 = _issue_entry_T_2846 | _issue_entry_T_2832; // @[Mux.scala:30:73] wire _issue_entry_T_2848 = _issue_entry_T_2847 | _issue_entry_T_2833; // @[Mux.scala:30:73] wire _issue_entry_T_2849 = _issue_entry_T_2848 | _issue_entry_T_2834; // @[Mux.scala:30:73] wire _issue_entry_T_2850 = _issue_entry_T_2849 | _issue_entry_T_2835; // @[Mux.scala:30:73] wire _issue_entry_T_2851 = _issue_entry_T_2850 | _issue_entry_T_2836; // @[Mux.scala:30:73] wire _issue_entry_T_2852 = _issue_entry_T_2851 | _issue_entry_T_2837; // @[Mux.scala:30:73] wire _issue_entry_T_2853 = _issue_entry_T_2852 | _issue_entry_T_2838; // @[Mux.scala:30:73] wire _issue_entry_T_2854 = _issue_entry_T_2853 | _issue_entry_T_2839; // @[Mux.scala:30:73] wire _issue_entry_T_2855 = _issue_entry_T_2854 | _issue_entry_T_2840; // @[Mux.scala:30:73] assign _issue_entry_WIRE_184 = _issue_entry_T_2855; // @[Mux.scala:30:73] assign _issue_entry_WIRE_183_uie = _issue_entry_WIRE_184; // @[Mux.scala:30:73] wire _issue_entry_T_2856 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30] wire _issue_entry_T_2857 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30] wire _issue_entry_T_2858 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30] wire _issue_entry_T_2859 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30] wire _issue_entry_T_2860 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30] wire _issue_entry_T_2861 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30] wire _issue_entry_T_2862 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30] wire _issue_entry_T_2863 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30] wire _issue_entry_T_2864 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30] wire _issue_entry_T_2865 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30] wire _issue_entry_T_2866 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30] wire _issue_entry_T_2867 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30] wire _issue_entry_T_2868 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30] wire _issue_entry_T_2869 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30] wire _issue_entry_T_2870 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30] wire _issue_entry_T_2871 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30] wire _issue_entry_T_2872 = _issue_entry_T_2856 | _issue_entry_T_2857; // @[Mux.scala:30:73] wire _issue_entry_T_2873 = _issue_entry_T_2872 | _issue_entry_T_2858; // @[Mux.scala:30:73] wire _issue_entry_T_2874 = _issue_entry_T_2873 | _issue_entry_T_2859; // @[Mux.scala:30:73] wire _issue_entry_T_2875 = _issue_entry_T_2874 | _issue_entry_T_2860; // @[Mux.scala:30:73] wire _issue_entry_T_2876 = _issue_entry_T_2875 | _issue_entry_T_2861; // @[Mux.scala:30:73] wire _issue_entry_T_2877 = _issue_entry_T_2876 | _issue_entry_T_2862; // @[Mux.scala:30:73] wire _issue_entry_T_2878 = _issue_entry_T_2877 | _issue_entry_T_2863; // @[Mux.scala:30:73] wire _issue_entry_T_2879 = _issue_entry_T_2878 | _issue_entry_T_2864; // @[Mux.scala:30:73] wire _issue_entry_T_2880 = _issue_entry_T_2879 | _issue_entry_T_2865; // @[Mux.scala:30:73] wire _issue_entry_T_2881 = _issue_entry_T_2880 | _issue_entry_T_2866; // @[Mux.scala:30:73] wire _issue_entry_T_2882 = _issue_entry_T_2881 | _issue_entry_T_2867; // @[Mux.scala:30:73] wire _issue_entry_T_2883 = _issue_entry_T_2882 | _issue_entry_T_2868; // @[Mux.scala:30:73] wire _issue_entry_T_2884 = _issue_entry_T_2883 | _issue_entry_T_2869; // @[Mux.scala:30:73] wire _issue_entry_T_2885 = _issue_entry_T_2884 | _issue_entry_T_2870; // @[Mux.scala:30:73] wire _issue_entry_T_2886 = _issue_entry_T_2885 | _issue_entry_T_2871; // @[Mux.scala:30:73] assign _issue_entry_WIRE_185 = _issue_entry_T_2886; // @[Mux.scala:30:73] assign _issue_entry_WIRE_183_sie = _issue_entry_WIRE_185; // @[Mux.scala:30:73] wire _issue_entry_T_2887 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30] wire _issue_entry_T_2888 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30] wire _issue_entry_T_2889 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30] wire _issue_entry_T_2890 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30] wire _issue_entry_T_2891 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30] wire _issue_entry_T_2892 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30] wire _issue_entry_T_2893 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30] wire _issue_entry_T_2894 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30] wire _issue_entry_T_2895 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30] wire _issue_entry_T_2896 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30] wire _issue_entry_T_2897 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30] wire _issue_entry_T_2898 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30] wire _issue_entry_T_2899 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30] wire _issue_entry_T_2900 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30] wire _issue_entry_T_2901 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30] wire _issue_entry_T_2902 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30] wire _issue_entry_T_2903 = _issue_entry_T_2887 | _issue_entry_T_2888; // @[Mux.scala:30:73] wire _issue_entry_T_2904 = _issue_entry_T_2903 | _issue_entry_T_2889; // @[Mux.scala:30:73] wire _issue_entry_T_2905 = _issue_entry_T_2904 | _issue_entry_T_2890; // @[Mux.scala:30:73] wire _issue_entry_T_2906 = _issue_entry_T_2905 | _issue_entry_T_2891; // @[Mux.scala:30:73] wire _issue_entry_T_2907 = _issue_entry_T_2906 | _issue_entry_T_2892; // @[Mux.scala:30:73] wire _issue_entry_T_2908 = _issue_entry_T_2907 | _issue_entry_T_2893; // @[Mux.scala:30:73] wire _issue_entry_T_2909 = _issue_entry_T_2908 | _issue_entry_T_2894; // @[Mux.scala:30:73] wire _issue_entry_T_2910 = _issue_entry_T_2909 | _issue_entry_T_2895; // @[Mux.scala:30:73] wire _issue_entry_T_2911 = _issue_entry_T_2910 | _issue_entry_T_2896; // @[Mux.scala:30:73] wire _issue_entry_T_2912 = _issue_entry_T_2911 | _issue_entry_T_2897; // @[Mux.scala:30:73] wire _issue_entry_T_2913 = _issue_entry_T_2912 | _issue_entry_T_2898; // @[Mux.scala:30:73] wire _issue_entry_T_2914 = _issue_entry_T_2913 | _issue_entry_T_2899; // @[Mux.scala:30:73] wire _issue_entry_T_2915 = _issue_entry_T_2914 | _issue_entry_T_2900; // @[Mux.scala:30:73] wire _issue_entry_T_2916 = _issue_entry_T_2915 | _issue_entry_T_2901; // @[Mux.scala:30:73] wire _issue_entry_T_2917 = _issue_entry_T_2916 | _issue_entry_T_2902; // @[Mux.scala:30:73] assign _issue_entry_WIRE_186 = _issue_entry_T_2917; // @[Mux.scala:30:73] assign _issue_entry_WIRE_183_hie = _issue_entry_WIRE_186; // @[Mux.scala:30:73] wire _issue_entry_T_2918 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30] wire _issue_entry_T_2919 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30] wire _issue_entry_T_2920 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30] wire _issue_entry_T_2921 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30] wire _issue_entry_T_2922 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30] wire _issue_entry_T_2923 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30] wire _issue_entry_T_2924 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30] wire _issue_entry_T_2925 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30] wire _issue_entry_T_2926 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30] wire _issue_entry_T_2927 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30] wire _issue_entry_T_2928 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30] wire _issue_entry_T_2929 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30] wire _issue_entry_T_2930 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30] wire _issue_entry_T_2931 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30] wire _issue_entry_T_2932 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30] wire _issue_entry_T_2933 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30] wire _issue_entry_T_2934 = _issue_entry_T_2918 | _issue_entry_T_2919; // @[Mux.scala:30:73] wire _issue_entry_T_2935 = _issue_entry_T_2934 | _issue_entry_T_2920; // @[Mux.scala:30:73] wire _issue_entry_T_2936 = _issue_entry_T_2935 | _issue_entry_T_2921; // @[Mux.scala:30:73] wire _issue_entry_T_2937 = _issue_entry_T_2936 | _issue_entry_T_2922; // @[Mux.scala:30:73] wire _issue_entry_T_2938 = _issue_entry_T_2937 | _issue_entry_T_2923; // @[Mux.scala:30:73] wire _issue_entry_T_2939 = _issue_entry_T_2938 | _issue_entry_T_2924; // @[Mux.scala:30:73] wire _issue_entry_T_2940 = _issue_entry_T_2939 | _issue_entry_T_2925; // @[Mux.scala:30:73] wire _issue_entry_T_2941 = _issue_entry_T_2940 | _issue_entry_T_2926; // @[Mux.scala:30:73] wire _issue_entry_T_2942 = _issue_entry_T_2941 | _issue_entry_T_2927; // @[Mux.scala:30:73] wire _issue_entry_T_2943 = _issue_entry_T_2942 | _issue_entry_T_2928; // @[Mux.scala:30:73] wire _issue_entry_T_2944 = _issue_entry_T_2943 | _issue_entry_T_2929; // @[Mux.scala:30:73] wire _issue_entry_T_2945 = _issue_entry_T_2944 | _issue_entry_T_2930; // @[Mux.scala:30:73] wire _issue_entry_T_2946 = _issue_entry_T_2945 | _issue_entry_T_2931; // @[Mux.scala:30:73] wire _issue_entry_T_2947 = _issue_entry_T_2946 | _issue_entry_T_2932; // @[Mux.scala:30:73] wire _issue_entry_T_2948 = _issue_entry_T_2947 | _issue_entry_T_2933; // @[Mux.scala:30:73] assign _issue_entry_WIRE_187 = _issue_entry_T_2948; // @[Mux.scala:30:73] assign _issue_entry_WIRE_183_mie = _issue_entry_WIRE_187; // @[Mux.scala:30:73] wire _issue_entry_T_2949 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30] wire _issue_entry_T_2950 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30] wire _issue_entry_T_2951 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30] wire _issue_entry_T_2952 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30] wire _issue_entry_T_2953 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30] wire _issue_entry_T_2954 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30] wire _issue_entry_T_2955 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30] wire _issue_entry_T_2956 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30] wire _issue_entry_T_2957 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30] wire _issue_entry_T_2958 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30] wire _issue_entry_T_2959 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30] wire _issue_entry_T_2960 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30] wire _issue_entry_T_2961 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30] wire _issue_entry_T_2962 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30] wire _issue_entry_T_2963 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30] wire _issue_entry_T_2964 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30] wire _issue_entry_T_2965 = _issue_entry_T_2949 | _issue_entry_T_2950; // @[Mux.scala:30:73] wire _issue_entry_T_2966 = _issue_entry_T_2965 | _issue_entry_T_2951; // @[Mux.scala:30:73] wire _issue_entry_T_2967 = _issue_entry_T_2966 | _issue_entry_T_2952; // @[Mux.scala:30:73] wire _issue_entry_T_2968 = _issue_entry_T_2967 | _issue_entry_T_2953; // @[Mux.scala:30:73] wire _issue_entry_T_2969 = _issue_entry_T_2968 | _issue_entry_T_2954; // @[Mux.scala:30:73] wire _issue_entry_T_2970 = _issue_entry_T_2969 | _issue_entry_T_2955; // @[Mux.scala:30:73] wire _issue_entry_T_2971 = _issue_entry_T_2970 | _issue_entry_T_2956; // @[Mux.scala:30:73] wire _issue_entry_T_2972 = _issue_entry_T_2971 | _issue_entry_T_2957; // @[Mux.scala:30:73] wire _issue_entry_T_2973 = _issue_entry_T_2972 | _issue_entry_T_2958; // @[Mux.scala:30:73] wire _issue_entry_T_2974 = _issue_entry_T_2973 | _issue_entry_T_2959; // @[Mux.scala:30:73] wire _issue_entry_T_2975 = _issue_entry_T_2974 | _issue_entry_T_2960; // @[Mux.scala:30:73] wire _issue_entry_T_2976 = _issue_entry_T_2975 | _issue_entry_T_2961; // @[Mux.scala:30:73] wire _issue_entry_T_2977 = _issue_entry_T_2976 | _issue_entry_T_2962; // @[Mux.scala:30:73] wire _issue_entry_T_2978 = _issue_entry_T_2977 | _issue_entry_T_2963; // @[Mux.scala:30:73] wire _issue_entry_T_2979 = _issue_entry_T_2978 | _issue_entry_T_2964; // @[Mux.scala:30:73] assign _issue_entry_WIRE_188 = _issue_entry_T_2979; // @[Mux.scala:30:73] assign _issue_entry_WIRE_183_upie = _issue_entry_WIRE_188; // @[Mux.scala:30:73] wire _issue_entry_T_2980 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30] wire _issue_entry_T_2981 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30] wire _issue_entry_T_2982 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30] wire _issue_entry_T_2983 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30] wire _issue_entry_T_2984 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30] wire _issue_entry_T_2985 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30] wire _issue_entry_T_2986 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30] wire _issue_entry_T_2987 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30] wire _issue_entry_T_2988 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30] wire _issue_entry_T_2989 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30] wire _issue_entry_T_2990 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30] wire _issue_entry_T_2991 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30] wire _issue_entry_T_2992 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30] wire _issue_entry_T_2993 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30] wire _issue_entry_T_2994 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30] wire _issue_entry_T_2995 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30] wire _issue_entry_T_2996 = _issue_entry_T_2980 | _issue_entry_T_2981; // @[Mux.scala:30:73] wire _issue_entry_T_2997 = _issue_entry_T_2996 | _issue_entry_T_2982; // @[Mux.scala:30:73] wire _issue_entry_T_2998 = _issue_entry_T_2997 | _issue_entry_T_2983; // @[Mux.scala:30:73] wire _issue_entry_T_2999 = _issue_entry_T_2998 | _issue_entry_T_2984; // @[Mux.scala:30:73] wire _issue_entry_T_3000 = _issue_entry_T_2999 | _issue_entry_T_2985; // @[Mux.scala:30:73] wire _issue_entry_T_3001 = _issue_entry_T_3000 | _issue_entry_T_2986; // @[Mux.scala:30:73] wire _issue_entry_T_3002 = _issue_entry_T_3001 | _issue_entry_T_2987; // @[Mux.scala:30:73] wire _issue_entry_T_3003 = _issue_entry_T_3002 | _issue_entry_T_2988; // @[Mux.scala:30:73] wire _issue_entry_T_3004 = _issue_entry_T_3003 | _issue_entry_T_2989; // @[Mux.scala:30:73] wire _issue_entry_T_3005 = _issue_entry_T_3004 | _issue_entry_T_2990; // @[Mux.scala:30:73] wire _issue_entry_T_3006 = _issue_entry_T_3005 | _issue_entry_T_2991; // @[Mux.scala:30:73] wire _issue_entry_T_3007 = _issue_entry_T_3006 | _issue_entry_T_2992; // @[Mux.scala:30:73] wire _issue_entry_T_3008 = _issue_entry_T_3007 | _issue_entry_T_2993; // @[Mux.scala:30:73] wire _issue_entry_T_3009 = _issue_entry_T_3008 | _issue_entry_T_2994; // @[Mux.scala:30:73] wire _issue_entry_T_3010 = _issue_entry_T_3009 | _issue_entry_T_2995; // @[Mux.scala:30:73] assign _issue_entry_WIRE_189 = _issue_entry_T_3010; // @[Mux.scala:30:73] assign _issue_entry_WIRE_183_spie = _issue_entry_WIRE_189; // @[Mux.scala:30:73] wire _issue_entry_T_3011 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30] wire _issue_entry_T_3012 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30] wire _issue_entry_T_3013 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30] wire _issue_entry_T_3014 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30] wire _issue_entry_T_3015 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30] wire _issue_entry_T_3016 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30] wire _issue_entry_T_3017 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30] wire _issue_entry_T_3018 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30] wire _issue_entry_T_3019 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30] wire _issue_entry_T_3020 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30] wire _issue_entry_T_3021 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30] wire _issue_entry_T_3022 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30] wire _issue_entry_T_3023 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30] wire _issue_entry_T_3024 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30] wire _issue_entry_T_3025 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30] wire _issue_entry_T_3026 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30] wire _issue_entry_T_3027 = _issue_entry_T_3011 | _issue_entry_T_3012; // @[Mux.scala:30:73] wire _issue_entry_T_3028 = _issue_entry_T_3027 | _issue_entry_T_3013; // @[Mux.scala:30:73] wire _issue_entry_T_3029 = _issue_entry_T_3028 | _issue_entry_T_3014; // @[Mux.scala:30:73] wire _issue_entry_T_3030 = _issue_entry_T_3029 | _issue_entry_T_3015; // @[Mux.scala:30:73] wire _issue_entry_T_3031 = _issue_entry_T_3030 | _issue_entry_T_3016; // @[Mux.scala:30:73] wire _issue_entry_T_3032 = _issue_entry_T_3031 | _issue_entry_T_3017; // @[Mux.scala:30:73] wire _issue_entry_T_3033 = _issue_entry_T_3032 | _issue_entry_T_3018; // @[Mux.scala:30:73] wire _issue_entry_T_3034 = _issue_entry_T_3033 | _issue_entry_T_3019; // @[Mux.scala:30:73] wire _issue_entry_T_3035 = _issue_entry_T_3034 | _issue_entry_T_3020; // @[Mux.scala:30:73] wire _issue_entry_T_3036 = _issue_entry_T_3035 | _issue_entry_T_3021; // @[Mux.scala:30:73] wire _issue_entry_T_3037 = _issue_entry_T_3036 | _issue_entry_T_3022; // @[Mux.scala:30:73] wire _issue_entry_T_3038 = _issue_entry_T_3037 | _issue_entry_T_3023; // @[Mux.scala:30:73] wire _issue_entry_T_3039 = _issue_entry_T_3038 | _issue_entry_T_3024; // @[Mux.scala:30:73] wire _issue_entry_T_3040 = _issue_entry_T_3039 | _issue_entry_T_3025; // @[Mux.scala:30:73] wire _issue_entry_T_3041 = _issue_entry_T_3040 | _issue_entry_T_3026; // @[Mux.scala:30:73] assign _issue_entry_WIRE_190 = _issue_entry_T_3041; // @[Mux.scala:30:73] assign _issue_entry_WIRE_183_ube = _issue_entry_WIRE_190; // @[Mux.scala:30:73] wire _issue_entry_T_3042 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30] wire _issue_entry_T_3043 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30] wire _issue_entry_T_3044 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30] wire _issue_entry_T_3045 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30] wire _issue_entry_T_3046 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30] wire _issue_entry_T_3047 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30] wire _issue_entry_T_3048 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30] wire _issue_entry_T_3049 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30] wire _issue_entry_T_3050 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30] wire _issue_entry_T_3051 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30] wire _issue_entry_T_3052 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30] wire _issue_entry_T_3053 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30] wire _issue_entry_T_3054 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30] wire _issue_entry_T_3055 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30] wire _issue_entry_T_3056 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30] wire _issue_entry_T_3057 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30] wire _issue_entry_T_3058 = _issue_entry_T_3042 | _issue_entry_T_3043; // @[Mux.scala:30:73] wire _issue_entry_T_3059 = _issue_entry_T_3058 | _issue_entry_T_3044; // @[Mux.scala:30:73] wire _issue_entry_T_3060 = _issue_entry_T_3059 | _issue_entry_T_3045; // @[Mux.scala:30:73] wire _issue_entry_T_3061 = _issue_entry_T_3060 | _issue_entry_T_3046; // @[Mux.scala:30:73] wire _issue_entry_T_3062 = _issue_entry_T_3061 | _issue_entry_T_3047; // @[Mux.scala:30:73] wire _issue_entry_T_3063 = _issue_entry_T_3062 | _issue_entry_T_3048; // @[Mux.scala:30:73] wire _issue_entry_T_3064 = _issue_entry_T_3063 | _issue_entry_T_3049; // @[Mux.scala:30:73] wire _issue_entry_T_3065 = _issue_entry_T_3064 | _issue_entry_T_3050; // @[Mux.scala:30:73] wire _issue_entry_T_3066 = _issue_entry_T_3065 | _issue_entry_T_3051; // @[Mux.scala:30:73] wire _issue_entry_T_3067 = _issue_entry_T_3066 | _issue_entry_T_3052; // @[Mux.scala:30:73] wire _issue_entry_T_3068 = _issue_entry_T_3067 | _issue_entry_T_3053; // @[Mux.scala:30:73] wire _issue_entry_T_3069 = _issue_entry_T_3068 | _issue_entry_T_3054; // @[Mux.scala:30:73] wire _issue_entry_T_3070 = _issue_entry_T_3069 | _issue_entry_T_3055; // @[Mux.scala:30:73] wire _issue_entry_T_3071 = _issue_entry_T_3070 | _issue_entry_T_3056; // @[Mux.scala:30:73] wire _issue_entry_T_3072 = _issue_entry_T_3071 | _issue_entry_T_3057; // @[Mux.scala:30:73] assign _issue_entry_WIRE_191 = _issue_entry_T_3072; // @[Mux.scala:30:73] assign _issue_entry_WIRE_183_mpie = _issue_entry_WIRE_191; // @[Mux.scala:30:73] wire _issue_entry_T_3073 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30] wire _issue_entry_T_3074 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30] wire _issue_entry_T_3075 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30] wire _issue_entry_T_3076 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30] wire _issue_entry_T_3077 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30] wire _issue_entry_T_3078 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30] wire _issue_entry_T_3079 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30] wire _issue_entry_T_3080 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30] wire _issue_entry_T_3081 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30] wire _issue_entry_T_3082 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30] wire _issue_entry_T_3083 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30] wire _issue_entry_T_3084 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30] wire _issue_entry_T_3085 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30] wire _issue_entry_T_3086 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30] wire _issue_entry_T_3087 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30] wire _issue_entry_T_3088 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30] wire _issue_entry_T_3089 = _issue_entry_T_3073 | _issue_entry_T_3074; // @[Mux.scala:30:73] wire _issue_entry_T_3090 = _issue_entry_T_3089 | _issue_entry_T_3075; // @[Mux.scala:30:73] wire _issue_entry_T_3091 = _issue_entry_T_3090 | _issue_entry_T_3076; // @[Mux.scala:30:73] wire _issue_entry_T_3092 = _issue_entry_T_3091 | _issue_entry_T_3077; // @[Mux.scala:30:73] wire _issue_entry_T_3093 = _issue_entry_T_3092 | _issue_entry_T_3078; // @[Mux.scala:30:73] wire _issue_entry_T_3094 = _issue_entry_T_3093 | _issue_entry_T_3079; // @[Mux.scala:30:73] wire _issue_entry_T_3095 = _issue_entry_T_3094 | _issue_entry_T_3080; // @[Mux.scala:30:73] wire _issue_entry_T_3096 = _issue_entry_T_3095 | _issue_entry_T_3081; // @[Mux.scala:30:73] wire _issue_entry_T_3097 = _issue_entry_T_3096 | _issue_entry_T_3082; // @[Mux.scala:30:73] wire _issue_entry_T_3098 = _issue_entry_T_3097 | _issue_entry_T_3083; // @[Mux.scala:30:73] wire _issue_entry_T_3099 = _issue_entry_T_3098 | _issue_entry_T_3084; // @[Mux.scala:30:73] wire _issue_entry_T_3100 = _issue_entry_T_3099 | _issue_entry_T_3085; // @[Mux.scala:30:73] wire _issue_entry_T_3101 = _issue_entry_T_3100 | _issue_entry_T_3086; // @[Mux.scala:30:73] wire _issue_entry_T_3102 = _issue_entry_T_3101 | _issue_entry_T_3087; // @[Mux.scala:30:73] wire _issue_entry_T_3103 = _issue_entry_T_3102 | _issue_entry_T_3088; // @[Mux.scala:30:73] assign _issue_entry_WIRE_192 = _issue_entry_T_3103; // @[Mux.scala:30:73] assign _issue_entry_WIRE_183_spp = _issue_entry_WIRE_192; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3104 = issue_sel_0_1 ? entries_ex_0_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3105 = issue_sel_1_1 ? entries_ex_1_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3106 = issue_sel_2_1 ? entries_ex_2_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3107 = issue_sel_3_1 ? entries_ex_3_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3108 = issue_sel_4_1 ? entries_ex_4_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3109 = issue_sel_5_1 ? entries_ex_5_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3110 = issue_sel_6_1 ? entries_ex_6_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3111 = issue_sel_7_1 ? entries_ex_7_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3112 = issue_sel_8 ? entries_ex_8_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3113 = issue_sel_9 ? entries_ex_9_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3114 = issue_sel_10 ? entries_ex_10_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3115 = issue_sel_11 ? entries_ex_11_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3116 = issue_sel_12 ? entries_ex_12_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3117 = issue_sel_13 ? entries_ex_13_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3118 = issue_sel_14 ? entries_ex_14_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3119 = issue_sel_15 ? entries_ex_15_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3120 = _issue_entry_T_3104 | _issue_entry_T_3105; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3121 = _issue_entry_T_3120 | _issue_entry_T_3106; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3122 = _issue_entry_T_3121 | _issue_entry_T_3107; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3123 = _issue_entry_T_3122 | _issue_entry_T_3108; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3124 = _issue_entry_T_3123 | _issue_entry_T_3109; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3125 = _issue_entry_T_3124 | _issue_entry_T_3110; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3126 = _issue_entry_T_3125 | _issue_entry_T_3111; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3127 = _issue_entry_T_3126 | _issue_entry_T_3112; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3128 = _issue_entry_T_3127 | _issue_entry_T_3113; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3129 = _issue_entry_T_3128 | _issue_entry_T_3114; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3130 = _issue_entry_T_3129 | _issue_entry_T_3115; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3131 = _issue_entry_T_3130 | _issue_entry_T_3116; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3132 = _issue_entry_T_3131 | _issue_entry_T_3117; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3133 = _issue_entry_T_3132 | _issue_entry_T_3118; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3134 = _issue_entry_T_3133 | _issue_entry_T_3119; // @[Mux.scala:30:73] assign _issue_entry_WIRE_193 = _issue_entry_T_3134; // @[Mux.scala:30:73] assign _issue_entry_WIRE_183_vs = _issue_entry_WIRE_193; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3135 = issue_sel_0_1 ? entries_ex_0_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3136 = issue_sel_1_1 ? entries_ex_1_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3137 = issue_sel_2_1 ? entries_ex_2_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3138 = issue_sel_3_1 ? entries_ex_3_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3139 = issue_sel_4_1 ? entries_ex_4_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3140 = issue_sel_5_1 ? entries_ex_5_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3141 = issue_sel_6_1 ? entries_ex_6_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3142 = issue_sel_7_1 ? entries_ex_7_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3143 = issue_sel_8 ? entries_ex_8_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3144 = issue_sel_9 ? entries_ex_9_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3145 = issue_sel_10 ? entries_ex_10_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3146 = issue_sel_11 ? entries_ex_11_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3147 = issue_sel_12 ? entries_ex_12_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3148 = issue_sel_13 ? entries_ex_13_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3149 = issue_sel_14 ? entries_ex_14_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3150 = issue_sel_15 ? entries_ex_15_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3151 = _issue_entry_T_3135 | _issue_entry_T_3136; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3152 = _issue_entry_T_3151 | _issue_entry_T_3137; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3153 = _issue_entry_T_3152 | _issue_entry_T_3138; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3154 = _issue_entry_T_3153 | _issue_entry_T_3139; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3155 = _issue_entry_T_3154 | _issue_entry_T_3140; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3156 = _issue_entry_T_3155 | _issue_entry_T_3141; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3157 = _issue_entry_T_3156 | _issue_entry_T_3142; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3158 = _issue_entry_T_3157 | _issue_entry_T_3143; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3159 = _issue_entry_T_3158 | _issue_entry_T_3144; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3160 = _issue_entry_T_3159 | _issue_entry_T_3145; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3161 = _issue_entry_T_3160 | _issue_entry_T_3146; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3162 = _issue_entry_T_3161 | _issue_entry_T_3147; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3163 = _issue_entry_T_3162 | _issue_entry_T_3148; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3164 = _issue_entry_T_3163 | _issue_entry_T_3149; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3165 = _issue_entry_T_3164 | _issue_entry_T_3150; // @[Mux.scala:30:73] assign _issue_entry_WIRE_194 = _issue_entry_T_3165; // @[Mux.scala:30:73] assign _issue_entry_WIRE_183_mpp = _issue_entry_WIRE_194; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3166 = issue_sel_0_1 ? entries_ex_0_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3167 = issue_sel_1_1 ? entries_ex_1_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3168 = issue_sel_2_1 ? entries_ex_2_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3169 = issue_sel_3_1 ? entries_ex_3_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3170 = issue_sel_4_1 ? entries_ex_4_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3171 = issue_sel_5_1 ? entries_ex_5_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3172 = issue_sel_6_1 ? entries_ex_6_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3173 = issue_sel_7_1 ? entries_ex_7_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3174 = issue_sel_8 ? entries_ex_8_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3175 = issue_sel_9 ? entries_ex_9_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3176 = issue_sel_10 ? entries_ex_10_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3177 = issue_sel_11 ? entries_ex_11_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3178 = issue_sel_12 ? entries_ex_12_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3179 = issue_sel_13 ? entries_ex_13_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3180 = issue_sel_14 ? entries_ex_14_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3181 = issue_sel_15 ? entries_ex_15_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3182 = _issue_entry_T_3166 | _issue_entry_T_3167; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3183 = _issue_entry_T_3182 | _issue_entry_T_3168; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3184 = _issue_entry_T_3183 | _issue_entry_T_3169; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3185 = _issue_entry_T_3184 | _issue_entry_T_3170; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3186 = _issue_entry_T_3185 | _issue_entry_T_3171; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3187 = _issue_entry_T_3186 | _issue_entry_T_3172; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3188 = _issue_entry_T_3187 | _issue_entry_T_3173; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3189 = _issue_entry_T_3188 | _issue_entry_T_3174; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3190 = _issue_entry_T_3189 | _issue_entry_T_3175; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3191 = _issue_entry_T_3190 | _issue_entry_T_3176; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3192 = _issue_entry_T_3191 | _issue_entry_T_3177; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3193 = _issue_entry_T_3192 | _issue_entry_T_3178; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3194 = _issue_entry_T_3193 | _issue_entry_T_3179; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3195 = _issue_entry_T_3194 | _issue_entry_T_3180; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3196 = _issue_entry_T_3195 | _issue_entry_T_3181; // @[Mux.scala:30:73] assign _issue_entry_WIRE_195 = _issue_entry_T_3196; // @[Mux.scala:30:73] assign _issue_entry_WIRE_183_fs = _issue_entry_WIRE_195; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3197 = issue_sel_0_1 ? entries_ex_0_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3198 = issue_sel_1_1 ? entries_ex_1_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3199 = issue_sel_2_1 ? entries_ex_2_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3200 = issue_sel_3_1 ? entries_ex_3_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3201 = issue_sel_4_1 ? entries_ex_4_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3202 = issue_sel_5_1 ? entries_ex_5_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3203 = issue_sel_6_1 ? entries_ex_6_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3204 = issue_sel_7_1 ? entries_ex_7_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3205 = issue_sel_8 ? entries_ex_8_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3206 = issue_sel_9 ? entries_ex_9_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3207 = issue_sel_10 ? entries_ex_10_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3208 = issue_sel_11 ? entries_ex_11_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3209 = issue_sel_12 ? entries_ex_12_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3210 = issue_sel_13 ? entries_ex_13_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3211 = issue_sel_14 ? entries_ex_14_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3212 = issue_sel_15 ? entries_ex_15_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3213 = _issue_entry_T_3197 | _issue_entry_T_3198; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3214 = _issue_entry_T_3213 | _issue_entry_T_3199; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3215 = _issue_entry_T_3214 | _issue_entry_T_3200; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3216 = _issue_entry_T_3215 | _issue_entry_T_3201; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3217 = _issue_entry_T_3216 | _issue_entry_T_3202; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3218 = _issue_entry_T_3217 | _issue_entry_T_3203; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3219 = _issue_entry_T_3218 | _issue_entry_T_3204; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3220 = _issue_entry_T_3219 | _issue_entry_T_3205; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3221 = _issue_entry_T_3220 | _issue_entry_T_3206; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3222 = _issue_entry_T_3221 | _issue_entry_T_3207; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3223 = _issue_entry_T_3222 | _issue_entry_T_3208; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3224 = _issue_entry_T_3223 | _issue_entry_T_3209; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3225 = _issue_entry_T_3224 | _issue_entry_T_3210; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3226 = _issue_entry_T_3225 | _issue_entry_T_3211; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3227 = _issue_entry_T_3226 | _issue_entry_T_3212; // @[Mux.scala:30:73] assign _issue_entry_WIRE_196 = _issue_entry_T_3227; // @[Mux.scala:30:73] assign _issue_entry_WIRE_183_xs = _issue_entry_WIRE_196; // @[Mux.scala:30:73] wire _issue_entry_T_3228 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30] wire _issue_entry_T_3229 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30] wire _issue_entry_T_3230 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30] wire _issue_entry_T_3231 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30] wire _issue_entry_T_3232 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30] wire _issue_entry_T_3233 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30] wire _issue_entry_T_3234 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30] wire _issue_entry_T_3235 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30] wire _issue_entry_T_3236 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30] wire _issue_entry_T_3237 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30] wire _issue_entry_T_3238 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30] wire _issue_entry_T_3239 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30] wire _issue_entry_T_3240 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30] wire _issue_entry_T_3241 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30] wire _issue_entry_T_3242 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30] wire _issue_entry_T_3243 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30] wire _issue_entry_T_3244 = _issue_entry_T_3228 | _issue_entry_T_3229; // @[Mux.scala:30:73] wire _issue_entry_T_3245 = _issue_entry_T_3244 | _issue_entry_T_3230; // @[Mux.scala:30:73] wire _issue_entry_T_3246 = _issue_entry_T_3245 | _issue_entry_T_3231; // @[Mux.scala:30:73] wire _issue_entry_T_3247 = _issue_entry_T_3246 | _issue_entry_T_3232; // @[Mux.scala:30:73] wire _issue_entry_T_3248 = _issue_entry_T_3247 | _issue_entry_T_3233; // @[Mux.scala:30:73] wire _issue_entry_T_3249 = _issue_entry_T_3248 | _issue_entry_T_3234; // @[Mux.scala:30:73] wire _issue_entry_T_3250 = _issue_entry_T_3249 | _issue_entry_T_3235; // @[Mux.scala:30:73] wire _issue_entry_T_3251 = _issue_entry_T_3250 | _issue_entry_T_3236; // @[Mux.scala:30:73] wire _issue_entry_T_3252 = _issue_entry_T_3251 | _issue_entry_T_3237; // @[Mux.scala:30:73] wire _issue_entry_T_3253 = _issue_entry_T_3252 | _issue_entry_T_3238; // @[Mux.scala:30:73] wire _issue_entry_T_3254 = _issue_entry_T_3253 | _issue_entry_T_3239; // @[Mux.scala:30:73] wire _issue_entry_T_3255 = _issue_entry_T_3254 | _issue_entry_T_3240; // @[Mux.scala:30:73] wire _issue_entry_T_3256 = _issue_entry_T_3255 | _issue_entry_T_3241; // @[Mux.scala:30:73] wire _issue_entry_T_3257 = _issue_entry_T_3256 | _issue_entry_T_3242; // @[Mux.scala:30:73] wire _issue_entry_T_3258 = _issue_entry_T_3257 | _issue_entry_T_3243; // @[Mux.scala:30:73] assign _issue_entry_WIRE_197 = _issue_entry_T_3258; // @[Mux.scala:30:73] assign _issue_entry_WIRE_183_mprv = _issue_entry_WIRE_197; // @[Mux.scala:30:73] wire _issue_entry_T_3259 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30] wire _issue_entry_T_3260 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30] wire _issue_entry_T_3261 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30] wire _issue_entry_T_3262 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30] wire _issue_entry_T_3263 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30] wire _issue_entry_T_3264 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30] wire _issue_entry_T_3265 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30] wire _issue_entry_T_3266 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30] wire _issue_entry_T_3267 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30] wire _issue_entry_T_3268 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30] wire _issue_entry_T_3269 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30] wire _issue_entry_T_3270 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30] wire _issue_entry_T_3271 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30] wire _issue_entry_T_3272 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30] wire _issue_entry_T_3273 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30] wire _issue_entry_T_3274 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30] wire _issue_entry_T_3275 = _issue_entry_T_3259 | _issue_entry_T_3260; // @[Mux.scala:30:73] wire _issue_entry_T_3276 = _issue_entry_T_3275 | _issue_entry_T_3261; // @[Mux.scala:30:73] wire _issue_entry_T_3277 = _issue_entry_T_3276 | _issue_entry_T_3262; // @[Mux.scala:30:73] wire _issue_entry_T_3278 = _issue_entry_T_3277 | _issue_entry_T_3263; // @[Mux.scala:30:73] wire _issue_entry_T_3279 = _issue_entry_T_3278 | _issue_entry_T_3264; // @[Mux.scala:30:73] wire _issue_entry_T_3280 = _issue_entry_T_3279 | _issue_entry_T_3265; // @[Mux.scala:30:73] wire _issue_entry_T_3281 = _issue_entry_T_3280 | _issue_entry_T_3266; // @[Mux.scala:30:73] wire _issue_entry_T_3282 = _issue_entry_T_3281 | _issue_entry_T_3267; // @[Mux.scala:30:73] wire _issue_entry_T_3283 = _issue_entry_T_3282 | _issue_entry_T_3268; // @[Mux.scala:30:73] wire _issue_entry_T_3284 = _issue_entry_T_3283 | _issue_entry_T_3269; // @[Mux.scala:30:73] wire _issue_entry_T_3285 = _issue_entry_T_3284 | _issue_entry_T_3270; // @[Mux.scala:30:73] wire _issue_entry_T_3286 = _issue_entry_T_3285 | _issue_entry_T_3271; // @[Mux.scala:30:73] wire _issue_entry_T_3287 = _issue_entry_T_3286 | _issue_entry_T_3272; // @[Mux.scala:30:73] wire _issue_entry_T_3288 = _issue_entry_T_3287 | _issue_entry_T_3273; // @[Mux.scala:30:73] wire _issue_entry_T_3289 = _issue_entry_T_3288 | _issue_entry_T_3274; // @[Mux.scala:30:73] assign _issue_entry_WIRE_198 = _issue_entry_T_3289; // @[Mux.scala:30:73] assign _issue_entry_WIRE_183_sum = _issue_entry_WIRE_198; // @[Mux.scala:30:73] wire _issue_entry_T_3290 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30] wire _issue_entry_T_3291 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30] wire _issue_entry_T_3292 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30] wire _issue_entry_T_3293 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30] wire _issue_entry_T_3294 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30] wire _issue_entry_T_3295 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30] wire _issue_entry_T_3296 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30] wire _issue_entry_T_3297 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30] wire _issue_entry_T_3298 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30] wire _issue_entry_T_3299 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30] wire _issue_entry_T_3300 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30] wire _issue_entry_T_3301 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30] wire _issue_entry_T_3302 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30] wire _issue_entry_T_3303 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30] wire _issue_entry_T_3304 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30] wire _issue_entry_T_3305 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30] wire _issue_entry_T_3306 = _issue_entry_T_3290 | _issue_entry_T_3291; // @[Mux.scala:30:73] wire _issue_entry_T_3307 = _issue_entry_T_3306 | _issue_entry_T_3292; // @[Mux.scala:30:73] wire _issue_entry_T_3308 = _issue_entry_T_3307 | _issue_entry_T_3293; // @[Mux.scala:30:73] wire _issue_entry_T_3309 = _issue_entry_T_3308 | _issue_entry_T_3294; // @[Mux.scala:30:73] wire _issue_entry_T_3310 = _issue_entry_T_3309 | _issue_entry_T_3295; // @[Mux.scala:30:73] wire _issue_entry_T_3311 = _issue_entry_T_3310 | _issue_entry_T_3296; // @[Mux.scala:30:73] wire _issue_entry_T_3312 = _issue_entry_T_3311 | _issue_entry_T_3297; // @[Mux.scala:30:73] wire _issue_entry_T_3313 = _issue_entry_T_3312 | _issue_entry_T_3298; // @[Mux.scala:30:73] wire _issue_entry_T_3314 = _issue_entry_T_3313 | _issue_entry_T_3299; // @[Mux.scala:30:73] wire _issue_entry_T_3315 = _issue_entry_T_3314 | _issue_entry_T_3300; // @[Mux.scala:30:73] wire _issue_entry_T_3316 = _issue_entry_T_3315 | _issue_entry_T_3301; // @[Mux.scala:30:73] wire _issue_entry_T_3317 = _issue_entry_T_3316 | _issue_entry_T_3302; // @[Mux.scala:30:73] wire _issue_entry_T_3318 = _issue_entry_T_3317 | _issue_entry_T_3303; // @[Mux.scala:30:73] wire _issue_entry_T_3319 = _issue_entry_T_3318 | _issue_entry_T_3304; // @[Mux.scala:30:73] wire _issue_entry_T_3320 = _issue_entry_T_3319 | _issue_entry_T_3305; // @[Mux.scala:30:73] assign _issue_entry_WIRE_199 = _issue_entry_T_3320; // @[Mux.scala:30:73] assign _issue_entry_WIRE_183_mxr = _issue_entry_WIRE_199; // @[Mux.scala:30:73] wire _issue_entry_T_3321 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30] wire _issue_entry_T_3322 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30] wire _issue_entry_T_3323 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30] wire _issue_entry_T_3324 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30] wire _issue_entry_T_3325 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30] wire _issue_entry_T_3326 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30] wire _issue_entry_T_3327 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30] wire _issue_entry_T_3328 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30] wire _issue_entry_T_3329 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30] wire _issue_entry_T_3330 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30] wire _issue_entry_T_3331 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30] wire _issue_entry_T_3332 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30] wire _issue_entry_T_3333 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30] wire _issue_entry_T_3334 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30] wire _issue_entry_T_3335 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30] wire _issue_entry_T_3336 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30] wire _issue_entry_T_3337 = _issue_entry_T_3321 | _issue_entry_T_3322; // @[Mux.scala:30:73] wire _issue_entry_T_3338 = _issue_entry_T_3337 | _issue_entry_T_3323; // @[Mux.scala:30:73] wire _issue_entry_T_3339 = _issue_entry_T_3338 | _issue_entry_T_3324; // @[Mux.scala:30:73] wire _issue_entry_T_3340 = _issue_entry_T_3339 | _issue_entry_T_3325; // @[Mux.scala:30:73] wire _issue_entry_T_3341 = _issue_entry_T_3340 | _issue_entry_T_3326; // @[Mux.scala:30:73] wire _issue_entry_T_3342 = _issue_entry_T_3341 | _issue_entry_T_3327; // @[Mux.scala:30:73] wire _issue_entry_T_3343 = _issue_entry_T_3342 | _issue_entry_T_3328; // @[Mux.scala:30:73] wire _issue_entry_T_3344 = _issue_entry_T_3343 | _issue_entry_T_3329; // @[Mux.scala:30:73] wire _issue_entry_T_3345 = _issue_entry_T_3344 | _issue_entry_T_3330; // @[Mux.scala:30:73] wire _issue_entry_T_3346 = _issue_entry_T_3345 | _issue_entry_T_3331; // @[Mux.scala:30:73] wire _issue_entry_T_3347 = _issue_entry_T_3346 | _issue_entry_T_3332; // @[Mux.scala:30:73] wire _issue_entry_T_3348 = _issue_entry_T_3347 | _issue_entry_T_3333; // @[Mux.scala:30:73] wire _issue_entry_T_3349 = _issue_entry_T_3348 | _issue_entry_T_3334; // @[Mux.scala:30:73] wire _issue_entry_T_3350 = _issue_entry_T_3349 | _issue_entry_T_3335; // @[Mux.scala:30:73] wire _issue_entry_T_3351 = _issue_entry_T_3350 | _issue_entry_T_3336; // @[Mux.scala:30:73] assign _issue_entry_WIRE_200 = _issue_entry_T_3351; // @[Mux.scala:30:73] assign _issue_entry_WIRE_183_tvm = _issue_entry_WIRE_200; // @[Mux.scala:30:73] wire _issue_entry_T_3352 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30] wire _issue_entry_T_3353 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30] wire _issue_entry_T_3354 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30] wire _issue_entry_T_3355 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30] wire _issue_entry_T_3356 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30] wire _issue_entry_T_3357 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30] wire _issue_entry_T_3358 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30] wire _issue_entry_T_3359 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30] wire _issue_entry_T_3360 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30] wire _issue_entry_T_3361 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30] wire _issue_entry_T_3362 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30] wire _issue_entry_T_3363 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30] wire _issue_entry_T_3364 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30] wire _issue_entry_T_3365 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30] wire _issue_entry_T_3366 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30] wire _issue_entry_T_3367 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30] wire _issue_entry_T_3368 = _issue_entry_T_3352 | _issue_entry_T_3353; // @[Mux.scala:30:73] wire _issue_entry_T_3369 = _issue_entry_T_3368 | _issue_entry_T_3354; // @[Mux.scala:30:73] wire _issue_entry_T_3370 = _issue_entry_T_3369 | _issue_entry_T_3355; // @[Mux.scala:30:73] wire _issue_entry_T_3371 = _issue_entry_T_3370 | _issue_entry_T_3356; // @[Mux.scala:30:73] wire _issue_entry_T_3372 = _issue_entry_T_3371 | _issue_entry_T_3357; // @[Mux.scala:30:73] wire _issue_entry_T_3373 = _issue_entry_T_3372 | _issue_entry_T_3358; // @[Mux.scala:30:73] wire _issue_entry_T_3374 = _issue_entry_T_3373 | _issue_entry_T_3359; // @[Mux.scala:30:73] wire _issue_entry_T_3375 = _issue_entry_T_3374 | _issue_entry_T_3360; // @[Mux.scala:30:73] wire _issue_entry_T_3376 = _issue_entry_T_3375 | _issue_entry_T_3361; // @[Mux.scala:30:73] wire _issue_entry_T_3377 = _issue_entry_T_3376 | _issue_entry_T_3362; // @[Mux.scala:30:73] wire _issue_entry_T_3378 = _issue_entry_T_3377 | _issue_entry_T_3363; // @[Mux.scala:30:73] wire _issue_entry_T_3379 = _issue_entry_T_3378 | _issue_entry_T_3364; // @[Mux.scala:30:73] wire _issue_entry_T_3380 = _issue_entry_T_3379 | _issue_entry_T_3365; // @[Mux.scala:30:73] wire _issue_entry_T_3381 = _issue_entry_T_3380 | _issue_entry_T_3366; // @[Mux.scala:30:73] wire _issue_entry_T_3382 = _issue_entry_T_3381 | _issue_entry_T_3367; // @[Mux.scala:30:73] assign _issue_entry_WIRE_201 = _issue_entry_T_3382; // @[Mux.scala:30:73] assign _issue_entry_WIRE_183_tw = _issue_entry_WIRE_201; // @[Mux.scala:30:73] wire _issue_entry_T_3383 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30] wire _issue_entry_T_3384 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30] wire _issue_entry_T_3385 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30] wire _issue_entry_T_3386 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30] wire _issue_entry_T_3387 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30] wire _issue_entry_T_3388 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30] wire _issue_entry_T_3389 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30] wire _issue_entry_T_3390 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30] wire _issue_entry_T_3391 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30] wire _issue_entry_T_3392 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30] wire _issue_entry_T_3393 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30] wire _issue_entry_T_3394 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30] wire _issue_entry_T_3395 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30] wire _issue_entry_T_3396 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30] wire _issue_entry_T_3397 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30] wire _issue_entry_T_3398 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30] wire _issue_entry_T_3399 = _issue_entry_T_3383 | _issue_entry_T_3384; // @[Mux.scala:30:73] wire _issue_entry_T_3400 = _issue_entry_T_3399 | _issue_entry_T_3385; // @[Mux.scala:30:73] wire _issue_entry_T_3401 = _issue_entry_T_3400 | _issue_entry_T_3386; // @[Mux.scala:30:73] wire _issue_entry_T_3402 = _issue_entry_T_3401 | _issue_entry_T_3387; // @[Mux.scala:30:73] wire _issue_entry_T_3403 = _issue_entry_T_3402 | _issue_entry_T_3388; // @[Mux.scala:30:73] wire _issue_entry_T_3404 = _issue_entry_T_3403 | _issue_entry_T_3389; // @[Mux.scala:30:73] wire _issue_entry_T_3405 = _issue_entry_T_3404 | _issue_entry_T_3390; // @[Mux.scala:30:73] wire _issue_entry_T_3406 = _issue_entry_T_3405 | _issue_entry_T_3391; // @[Mux.scala:30:73] wire _issue_entry_T_3407 = _issue_entry_T_3406 | _issue_entry_T_3392; // @[Mux.scala:30:73] wire _issue_entry_T_3408 = _issue_entry_T_3407 | _issue_entry_T_3393; // @[Mux.scala:30:73] wire _issue_entry_T_3409 = _issue_entry_T_3408 | _issue_entry_T_3394; // @[Mux.scala:30:73] wire _issue_entry_T_3410 = _issue_entry_T_3409 | _issue_entry_T_3395; // @[Mux.scala:30:73] wire _issue_entry_T_3411 = _issue_entry_T_3410 | _issue_entry_T_3396; // @[Mux.scala:30:73] wire _issue_entry_T_3412 = _issue_entry_T_3411 | _issue_entry_T_3397; // @[Mux.scala:30:73] wire _issue_entry_T_3413 = _issue_entry_T_3412 | _issue_entry_T_3398; // @[Mux.scala:30:73] assign _issue_entry_WIRE_202 = _issue_entry_T_3413; // @[Mux.scala:30:73] assign _issue_entry_WIRE_183_tsr = _issue_entry_WIRE_202; // @[Mux.scala:30:73] wire [7:0] _issue_entry_T_3414 = issue_sel_0_1 ? entries_ex_0_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30] wire [7:0] _issue_entry_T_3415 = issue_sel_1_1 ? entries_ex_1_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30] wire [7:0] _issue_entry_T_3416 = issue_sel_2_1 ? entries_ex_2_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30] wire [7:0] _issue_entry_T_3417 = issue_sel_3_1 ? entries_ex_3_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30] wire [7:0] _issue_entry_T_3418 = issue_sel_4_1 ? entries_ex_4_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30] wire [7:0] _issue_entry_T_3419 = issue_sel_5_1 ? entries_ex_5_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30] wire [7:0] _issue_entry_T_3420 = issue_sel_6_1 ? entries_ex_6_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30] wire [7:0] _issue_entry_T_3421 = issue_sel_7_1 ? entries_ex_7_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30] wire [7:0] _issue_entry_T_3422 = issue_sel_8 ? entries_ex_8_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30] wire [7:0] _issue_entry_T_3423 = issue_sel_9 ? entries_ex_9_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30] wire [7:0] _issue_entry_T_3424 = issue_sel_10 ? entries_ex_10_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30] wire [7:0] _issue_entry_T_3425 = issue_sel_11 ? entries_ex_11_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30] wire [7:0] _issue_entry_T_3426 = issue_sel_12 ? entries_ex_12_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30] wire [7:0] _issue_entry_T_3427 = issue_sel_13 ? entries_ex_13_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30] wire [7:0] _issue_entry_T_3428 = issue_sel_14 ? entries_ex_14_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30] wire [7:0] _issue_entry_T_3429 = issue_sel_15 ? entries_ex_15_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30] wire [7:0] _issue_entry_T_3430 = _issue_entry_T_3414 | _issue_entry_T_3415; // @[Mux.scala:30:73] wire [7:0] _issue_entry_T_3431 = _issue_entry_T_3430 | _issue_entry_T_3416; // @[Mux.scala:30:73] wire [7:0] _issue_entry_T_3432 = _issue_entry_T_3431 | _issue_entry_T_3417; // @[Mux.scala:30:73] wire [7:0] _issue_entry_T_3433 = _issue_entry_T_3432 | _issue_entry_T_3418; // @[Mux.scala:30:73] wire [7:0] _issue_entry_T_3434 = _issue_entry_T_3433 | _issue_entry_T_3419; // @[Mux.scala:30:73] wire [7:0] _issue_entry_T_3435 = _issue_entry_T_3434 | _issue_entry_T_3420; // @[Mux.scala:30:73] wire [7:0] _issue_entry_T_3436 = _issue_entry_T_3435 | _issue_entry_T_3421; // @[Mux.scala:30:73] wire [7:0] _issue_entry_T_3437 = _issue_entry_T_3436 | _issue_entry_T_3422; // @[Mux.scala:30:73] wire [7:0] _issue_entry_T_3438 = _issue_entry_T_3437 | _issue_entry_T_3423; // @[Mux.scala:30:73] wire [7:0] _issue_entry_T_3439 = _issue_entry_T_3438 | _issue_entry_T_3424; // @[Mux.scala:30:73] wire [7:0] _issue_entry_T_3440 = _issue_entry_T_3439 | _issue_entry_T_3425; // @[Mux.scala:30:73] wire [7:0] _issue_entry_T_3441 = _issue_entry_T_3440 | _issue_entry_T_3426; // @[Mux.scala:30:73] wire [7:0] _issue_entry_T_3442 = _issue_entry_T_3441 | _issue_entry_T_3427; // @[Mux.scala:30:73] wire [7:0] _issue_entry_T_3443 = _issue_entry_T_3442 | _issue_entry_T_3428; // @[Mux.scala:30:73] wire [7:0] _issue_entry_T_3444 = _issue_entry_T_3443 | _issue_entry_T_3429; // @[Mux.scala:30:73] assign _issue_entry_WIRE_203 = _issue_entry_T_3444; // @[Mux.scala:30:73] assign _issue_entry_WIRE_183_zero1 = _issue_entry_WIRE_203; // @[Mux.scala:30:73] wire _issue_entry_T_3445 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30] wire _issue_entry_T_3446 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30] wire _issue_entry_T_3447 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30] wire _issue_entry_T_3448 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30] wire _issue_entry_T_3449 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30] wire _issue_entry_T_3450 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30] wire _issue_entry_T_3451 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30] wire _issue_entry_T_3452 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30] wire _issue_entry_T_3453 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30] wire _issue_entry_T_3454 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30] wire _issue_entry_T_3455 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30] wire _issue_entry_T_3456 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30] wire _issue_entry_T_3457 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30] wire _issue_entry_T_3458 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30] wire _issue_entry_T_3459 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30] wire _issue_entry_T_3460 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30] wire _issue_entry_T_3461 = _issue_entry_T_3445 | _issue_entry_T_3446; // @[Mux.scala:30:73] wire _issue_entry_T_3462 = _issue_entry_T_3461 | _issue_entry_T_3447; // @[Mux.scala:30:73] wire _issue_entry_T_3463 = _issue_entry_T_3462 | _issue_entry_T_3448; // @[Mux.scala:30:73] wire _issue_entry_T_3464 = _issue_entry_T_3463 | _issue_entry_T_3449; // @[Mux.scala:30:73] wire _issue_entry_T_3465 = _issue_entry_T_3464 | _issue_entry_T_3450; // @[Mux.scala:30:73] wire _issue_entry_T_3466 = _issue_entry_T_3465 | _issue_entry_T_3451; // @[Mux.scala:30:73] wire _issue_entry_T_3467 = _issue_entry_T_3466 | _issue_entry_T_3452; // @[Mux.scala:30:73] wire _issue_entry_T_3468 = _issue_entry_T_3467 | _issue_entry_T_3453; // @[Mux.scala:30:73] wire _issue_entry_T_3469 = _issue_entry_T_3468 | _issue_entry_T_3454; // @[Mux.scala:30:73] wire _issue_entry_T_3470 = _issue_entry_T_3469 | _issue_entry_T_3455; // @[Mux.scala:30:73] wire _issue_entry_T_3471 = _issue_entry_T_3470 | _issue_entry_T_3456; // @[Mux.scala:30:73] wire _issue_entry_T_3472 = _issue_entry_T_3471 | _issue_entry_T_3457; // @[Mux.scala:30:73] wire _issue_entry_T_3473 = _issue_entry_T_3472 | _issue_entry_T_3458; // @[Mux.scala:30:73] wire _issue_entry_T_3474 = _issue_entry_T_3473 | _issue_entry_T_3459; // @[Mux.scala:30:73] wire _issue_entry_T_3475 = _issue_entry_T_3474 | _issue_entry_T_3460; // @[Mux.scala:30:73] assign _issue_entry_WIRE_204 = _issue_entry_T_3475; // @[Mux.scala:30:73] assign _issue_entry_WIRE_183_sd_rv32 = _issue_entry_WIRE_204; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3476 = issue_sel_0_1 ? entries_ex_0_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3477 = issue_sel_1_1 ? entries_ex_1_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3478 = issue_sel_2_1 ? entries_ex_2_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3479 = issue_sel_3_1 ? entries_ex_3_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3480 = issue_sel_4_1 ? entries_ex_4_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3481 = issue_sel_5_1 ? entries_ex_5_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3482 = issue_sel_6_1 ? entries_ex_6_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3483 = issue_sel_7_1 ? entries_ex_7_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3484 = issue_sel_8 ? entries_ex_8_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3485 = issue_sel_9 ? entries_ex_9_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3486 = issue_sel_10 ? entries_ex_10_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3487 = issue_sel_11 ? entries_ex_11_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3488 = issue_sel_12 ? entries_ex_12_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3489 = issue_sel_13 ? entries_ex_13_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3490 = issue_sel_14 ? entries_ex_14_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3491 = issue_sel_15 ? entries_ex_15_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3492 = _issue_entry_T_3476 | _issue_entry_T_3477; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3493 = _issue_entry_T_3492 | _issue_entry_T_3478; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3494 = _issue_entry_T_3493 | _issue_entry_T_3479; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3495 = _issue_entry_T_3494 | _issue_entry_T_3480; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3496 = _issue_entry_T_3495 | _issue_entry_T_3481; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3497 = _issue_entry_T_3496 | _issue_entry_T_3482; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3498 = _issue_entry_T_3497 | _issue_entry_T_3483; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3499 = _issue_entry_T_3498 | _issue_entry_T_3484; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3500 = _issue_entry_T_3499 | _issue_entry_T_3485; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3501 = _issue_entry_T_3500 | _issue_entry_T_3486; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3502 = _issue_entry_T_3501 | _issue_entry_T_3487; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3503 = _issue_entry_T_3502 | _issue_entry_T_3488; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3504 = _issue_entry_T_3503 | _issue_entry_T_3489; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3505 = _issue_entry_T_3504 | _issue_entry_T_3490; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3506 = _issue_entry_T_3505 | _issue_entry_T_3491; // @[Mux.scala:30:73] assign _issue_entry_WIRE_205 = _issue_entry_T_3506; // @[Mux.scala:30:73] assign _issue_entry_WIRE_183_uxl = _issue_entry_WIRE_205; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3507 = issue_sel_0_1 ? entries_ex_0_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3508 = issue_sel_1_1 ? entries_ex_1_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3509 = issue_sel_2_1 ? entries_ex_2_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3510 = issue_sel_3_1 ? entries_ex_3_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3511 = issue_sel_4_1 ? entries_ex_4_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3512 = issue_sel_5_1 ? entries_ex_5_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3513 = issue_sel_6_1 ? entries_ex_6_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3514 = issue_sel_7_1 ? entries_ex_7_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3515 = issue_sel_8 ? entries_ex_8_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3516 = issue_sel_9 ? entries_ex_9_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3517 = issue_sel_10 ? entries_ex_10_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3518 = issue_sel_11 ? entries_ex_11_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3519 = issue_sel_12 ? entries_ex_12_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3520 = issue_sel_13 ? entries_ex_13_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3521 = issue_sel_14 ? entries_ex_14_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3522 = issue_sel_15 ? entries_ex_15_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3523 = _issue_entry_T_3507 | _issue_entry_T_3508; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3524 = _issue_entry_T_3523 | _issue_entry_T_3509; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3525 = _issue_entry_T_3524 | _issue_entry_T_3510; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3526 = _issue_entry_T_3525 | _issue_entry_T_3511; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3527 = _issue_entry_T_3526 | _issue_entry_T_3512; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3528 = _issue_entry_T_3527 | _issue_entry_T_3513; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3529 = _issue_entry_T_3528 | _issue_entry_T_3514; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3530 = _issue_entry_T_3529 | _issue_entry_T_3515; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3531 = _issue_entry_T_3530 | _issue_entry_T_3516; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3532 = _issue_entry_T_3531 | _issue_entry_T_3517; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3533 = _issue_entry_T_3532 | _issue_entry_T_3518; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3534 = _issue_entry_T_3533 | _issue_entry_T_3519; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3535 = _issue_entry_T_3534 | _issue_entry_T_3520; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3536 = _issue_entry_T_3535 | _issue_entry_T_3521; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3537 = _issue_entry_T_3536 | _issue_entry_T_3522; // @[Mux.scala:30:73] assign _issue_entry_WIRE_206 = _issue_entry_T_3537; // @[Mux.scala:30:73] assign _issue_entry_WIRE_183_sxl = _issue_entry_WIRE_206; // @[Mux.scala:30:73] wire _issue_entry_T_3538 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30] wire _issue_entry_T_3539 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30] wire _issue_entry_T_3540 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30] wire _issue_entry_T_3541 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30] wire _issue_entry_T_3542 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30] wire _issue_entry_T_3543 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30] wire _issue_entry_T_3544 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30] wire _issue_entry_T_3545 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30] wire _issue_entry_T_3546 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30] wire _issue_entry_T_3547 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30] wire _issue_entry_T_3548 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30] wire _issue_entry_T_3549 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30] wire _issue_entry_T_3550 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30] wire _issue_entry_T_3551 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30] wire _issue_entry_T_3552 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30] wire _issue_entry_T_3553 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30] wire _issue_entry_T_3554 = _issue_entry_T_3538 | _issue_entry_T_3539; // @[Mux.scala:30:73] wire _issue_entry_T_3555 = _issue_entry_T_3554 | _issue_entry_T_3540; // @[Mux.scala:30:73] wire _issue_entry_T_3556 = _issue_entry_T_3555 | _issue_entry_T_3541; // @[Mux.scala:30:73] wire _issue_entry_T_3557 = _issue_entry_T_3556 | _issue_entry_T_3542; // @[Mux.scala:30:73] wire _issue_entry_T_3558 = _issue_entry_T_3557 | _issue_entry_T_3543; // @[Mux.scala:30:73] wire _issue_entry_T_3559 = _issue_entry_T_3558 | _issue_entry_T_3544; // @[Mux.scala:30:73] wire _issue_entry_T_3560 = _issue_entry_T_3559 | _issue_entry_T_3545; // @[Mux.scala:30:73] wire _issue_entry_T_3561 = _issue_entry_T_3560 | _issue_entry_T_3546; // @[Mux.scala:30:73] wire _issue_entry_T_3562 = _issue_entry_T_3561 | _issue_entry_T_3547; // @[Mux.scala:30:73] wire _issue_entry_T_3563 = _issue_entry_T_3562 | _issue_entry_T_3548; // @[Mux.scala:30:73] wire _issue_entry_T_3564 = _issue_entry_T_3563 | _issue_entry_T_3549; // @[Mux.scala:30:73] wire _issue_entry_T_3565 = _issue_entry_T_3564 | _issue_entry_T_3550; // @[Mux.scala:30:73] wire _issue_entry_T_3566 = _issue_entry_T_3565 | _issue_entry_T_3551; // @[Mux.scala:30:73] wire _issue_entry_T_3567 = _issue_entry_T_3566 | _issue_entry_T_3552; // @[Mux.scala:30:73] wire _issue_entry_T_3568 = _issue_entry_T_3567 | _issue_entry_T_3553; // @[Mux.scala:30:73] assign _issue_entry_WIRE_207 = _issue_entry_T_3568; // @[Mux.scala:30:73] assign _issue_entry_WIRE_183_sbe = _issue_entry_WIRE_207; // @[Mux.scala:30:73] wire _issue_entry_T_3569 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30] wire _issue_entry_T_3570 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30] wire _issue_entry_T_3571 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30] wire _issue_entry_T_3572 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30] wire _issue_entry_T_3573 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30] wire _issue_entry_T_3574 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30] wire _issue_entry_T_3575 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30] wire _issue_entry_T_3576 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30] wire _issue_entry_T_3577 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30] wire _issue_entry_T_3578 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30] wire _issue_entry_T_3579 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30] wire _issue_entry_T_3580 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30] wire _issue_entry_T_3581 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30] wire _issue_entry_T_3582 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30] wire _issue_entry_T_3583 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30] wire _issue_entry_T_3584 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30] wire _issue_entry_T_3585 = _issue_entry_T_3569 | _issue_entry_T_3570; // @[Mux.scala:30:73] wire _issue_entry_T_3586 = _issue_entry_T_3585 | _issue_entry_T_3571; // @[Mux.scala:30:73] wire _issue_entry_T_3587 = _issue_entry_T_3586 | _issue_entry_T_3572; // @[Mux.scala:30:73] wire _issue_entry_T_3588 = _issue_entry_T_3587 | _issue_entry_T_3573; // @[Mux.scala:30:73] wire _issue_entry_T_3589 = _issue_entry_T_3588 | _issue_entry_T_3574; // @[Mux.scala:30:73] wire _issue_entry_T_3590 = _issue_entry_T_3589 | _issue_entry_T_3575; // @[Mux.scala:30:73] wire _issue_entry_T_3591 = _issue_entry_T_3590 | _issue_entry_T_3576; // @[Mux.scala:30:73] wire _issue_entry_T_3592 = _issue_entry_T_3591 | _issue_entry_T_3577; // @[Mux.scala:30:73] wire _issue_entry_T_3593 = _issue_entry_T_3592 | _issue_entry_T_3578; // @[Mux.scala:30:73] wire _issue_entry_T_3594 = _issue_entry_T_3593 | _issue_entry_T_3579; // @[Mux.scala:30:73] wire _issue_entry_T_3595 = _issue_entry_T_3594 | _issue_entry_T_3580; // @[Mux.scala:30:73] wire _issue_entry_T_3596 = _issue_entry_T_3595 | _issue_entry_T_3581; // @[Mux.scala:30:73] wire _issue_entry_T_3597 = _issue_entry_T_3596 | _issue_entry_T_3582; // @[Mux.scala:30:73] wire _issue_entry_T_3598 = _issue_entry_T_3597 | _issue_entry_T_3583; // @[Mux.scala:30:73] wire _issue_entry_T_3599 = _issue_entry_T_3598 | _issue_entry_T_3584; // @[Mux.scala:30:73] assign _issue_entry_WIRE_208 = _issue_entry_T_3599; // @[Mux.scala:30:73] assign _issue_entry_WIRE_183_mbe = _issue_entry_WIRE_208; // @[Mux.scala:30:73] wire _issue_entry_T_3600 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30] wire _issue_entry_T_3601 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30] wire _issue_entry_T_3602 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30] wire _issue_entry_T_3603 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30] wire _issue_entry_T_3604 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30] wire _issue_entry_T_3605 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30] wire _issue_entry_T_3606 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30] wire _issue_entry_T_3607 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30] wire _issue_entry_T_3608 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30] wire _issue_entry_T_3609 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30] wire _issue_entry_T_3610 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30] wire _issue_entry_T_3611 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30] wire _issue_entry_T_3612 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30] wire _issue_entry_T_3613 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30] wire _issue_entry_T_3614 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30] wire _issue_entry_T_3615 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30] wire _issue_entry_T_3616 = _issue_entry_T_3600 | _issue_entry_T_3601; // @[Mux.scala:30:73] wire _issue_entry_T_3617 = _issue_entry_T_3616 | _issue_entry_T_3602; // @[Mux.scala:30:73] wire _issue_entry_T_3618 = _issue_entry_T_3617 | _issue_entry_T_3603; // @[Mux.scala:30:73] wire _issue_entry_T_3619 = _issue_entry_T_3618 | _issue_entry_T_3604; // @[Mux.scala:30:73] wire _issue_entry_T_3620 = _issue_entry_T_3619 | _issue_entry_T_3605; // @[Mux.scala:30:73] wire _issue_entry_T_3621 = _issue_entry_T_3620 | _issue_entry_T_3606; // @[Mux.scala:30:73] wire _issue_entry_T_3622 = _issue_entry_T_3621 | _issue_entry_T_3607; // @[Mux.scala:30:73] wire _issue_entry_T_3623 = _issue_entry_T_3622 | _issue_entry_T_3608; // @[Mux.scala:30:73] wire _issue_entry_T_3624 = _issue_entry_T_3623 | _issue_entry_T_3609; // @[Mux.scala:30:73] wire _issue_entry_T_3625 = _issue_entry_T_3624 | _issue_entry_T_3610; // @[Mux.scala:30:73] wire _issue_entry_T_3626 = _issue_entry_T_3625 | _issue_entry_T_3611; // @[Mux.scala:30:73] wire _issue_entry_T_3627 = _issue_entry_T_3626 | _issue_entry_T_3612; // @[Mux.scala:30:73] wire _issue_entry_T_3628 = _issue_entry_T_3627 | _issue_entry_T_3613; // @[Mux.scala:30:73] wire _issue_entry_T_3629 = _issue_entry_T_3628 | _issue_entry_T_3614; // @[Mux.scala:30:73] wire _issue_entry_T_3630 = _issue_entry_T_3629 | _issue_entry_T_3615; // @[Mux.scala:30:73] assign _issue_entry_WIRE_209 = _issue_entry_T_3630; // @[Mux.scala:30:73] assign _issue_entry_WIRE_183_gva = _issue_entry_WIRE_209; // @[Mux.scala:30:73] wire _issue_entry_T_3631 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30] wire _issue_entry_T_3632 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30] wire _issue_entry_T_3633 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30] wire _issue_entry_T_3634 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30] wire _issue_entry_T_3635 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30] wire _issue_entry_T_3636 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30] wire _issue_entry_T_3637 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30] wire _issue_entry_T_3638 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30] wire _issue_entry_T_3639 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30] wire _issue_entry_T_3640 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30] wire _issue_entry_T_3641 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30] wire _issue_entry_T_3642 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30] wire _issue_entry_T_3643 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30] wire _issue_entry_T_3644 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30] wire _issue_entry_T_3645 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30] wire _issue_entry_T_3646 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30] wire _issue_entry_T_3647 = _issue_entry_T_3631 | _issue_entry_T_3632; // @[Mux.scala:30:73] wire _issue_entry_T_3648 = _issue_entry_T_3647 | _issue_entry_T_3633; // @[Mux.scala:30:73] wire _issue_entry_T_3649 = _issue_entry_T_3648 | _issue_entry_T_3634; // @[Mux.scala:30:73] wire _issue_entry_T_3650 = _issue_entry_T_3649 | _issue_entry_T_3635; // @[Mux.scala:30:73] wire _issue_entry_T_3651 = _issue_entry_T_3650 | _issue_entry_T_3636; // @[Mux.scala:30:73] wire _issue_entry_T_3652 = _issue_entry_T_3651 | _issue_entry_T_3637; // @[Mux.scala:30:73] wire _issue_entry_T_3653 = _issue_entry_T_3652 | _issue_entry_T_3638; // @[Mux.scala:30:73] wire _issue_entry_T_3654 = _issue_entry_T_3653 | _issue_entry_T_3639; // @[Mux.scala:30:73] wire _issue_entry_T_3655 = _issue_entry_T_3654 | _issue_entry_T_3640; // @[Mux.scala:30:73] wire _issue_entry_T_3656 = _issue_entry_T_3655 | _issue_entry_T_3641; // @[Mux.scala:30:73] wire _issue_entry_T_3657 = _issue_entry_T_3656 | _issue_entry_T_3642; // @[Mux.scala:30:73] wire _issue_entry_T_3658 = _issue_entry_T_3657 | _issue_entry_T_3643; // @[Mux.scala:30:73] wire _issue_entry_T_3659 = _issue_entry_T_3658 | _issue_entry_T_3644; // @[Mux.scala:30:73] wire _issue_entry_T_3660 = _issue_entry_T_3659 | _issue_entry_T_3645; // @[Mux.scala:30:73] wire _issue_entry_T_3661 = _issue_entry_T_3660 | _issue_entry_T_3646; // @[Mux.scala:30:73] assign _issue_entry_WIRE_210 = _issue_entry_T_3661; // @[Mux.scala:30:73] assign _issue_entry_WIRE_183_mpv = _issue_entry_WIRE_210; // @[Mux.scala:30:73] wire [22:0] _issue_entry_T_3662 = issue_sel_0_1 ? entries_ex_0_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30] wire [22:0] _issue_entry_T_3663 = issue_sel_1_1 ? entries_ex_1_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30] wire [22:0] _issue_entry_T_3664 = issue_sel_2_1 ? entries_ex_2_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30] wire [22:0] _issue_entry_T_3665 = issue_sel_3_1 ? entries_ex_3_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30] wire [22:0] _issue_entry_T_3666 = issue_sel_4_1 ? entries_ex_4_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30] wire [22:0] _issue_entry_T_3667 = issue_sel_5_1 ? entries_ex_5_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30] wire [22:0] _issue_entry_T_3668 = issue_sel_6_1 ? entries_ex_6_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30] wire [22:0] _issue_entry_T_3669 = issue_sel_7_1 ? entries_ex_7_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30] wire [22:0] _issue_entry_T_3670 = issue_sel_8 ? entries_ex_8_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30] wire [22:0] _issue_entry_T_3671 = issue_sel_9 ? entries_ex_9_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30] wire [22:0] _issue_entry_T_3672 = issue_sel_10 ? entries_ex_10_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30] wire [22:0] _issue_entry_T_3673 = issue_sel_11 ? entries_ex_11_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30] wire [22:0] _issue_entry_T_3674 = issue_sel_12 ? entries_ex_12_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30] wire [22:0] _issue_entry_T_3675 = issue_sel_13 ? entries_ex_13_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30] wire [22:0] _issue_entry_T_3676 = issue_sel_14 ? entries_ex_14_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30] wire [22:0] _issue_entry_T_3677 = issue_sel_15 ? entries_ex_15_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30] wire [22:0] _issue_entry_T_3678 = _issue_entry_T_3662 | _issue_entry_T_3663; // @[Mux.scala:30:73] wire [22:0] _issue_entry_T_3679 = _issue_entry_T_3678 | _issue_entry_T_3664; // @[Mux.scala:30:73] wire [22:0] _issue_entry_T_3680 = _issue_entry_T_3679 | _issue_entry_T_3665; // @[Mux.scala:30:73] wire [22:0] _issue_entry_T_3681 = _issue_entry_T_3680 | _issue_entry_T_3666; // @[Mux.scala:30:73] wire [22:0] _issue_entry_T_3682 = _issue_entry_T_3681 | _issue_entry_T_3667; // @[Mux.scala:30:73] wire [22:0] _issue_entry_T_3683 = _issue_entry_T_3682 | _issue_entry_T_3668; // @[Mux.scala:30:73] wire [22:0] _issue_entry_T_3684 = _issue_entry_T_3683 | _issue_entry_T_3669; // @[Mux.scala:30:73] wire [22:0] _issue_entry_T_3685 = _issue_entry_T_3684 | _issue_entry_T_3670; // @[Mux.scala:30:73] wire [22:0] _issue_entry_T_3686 = _issue_entry_T_3685 | _issue_entry_T_3671; // @[Mux.scala:30:73] wire [22:0] _issue_entry_T_3687 = _issue_entry_T_3686 | _issue_entry_T_3672; // @[Mux.scala:30:73] wire [22:0] _issue_entry_T_3688 = _issue_entry_T_3687 | _issue_entry_T_3673; // @[Mux.scala:30:73] wire [22:0] _issue_entry_T_3689 = _issue_entry_T_3688 | _issue_entry_T_3674; // @[Mux.scala:30:73] wire [22:0] _issue_entry_T_3690 = _issue_entry_T_3689 | _issue_entry_T_3675; // @[Mux.scala:30:73] wire [22:0] _issue_entry_T_3691 = _issue_entry_T_3690 | _issue_entry_T_3676; // @[Mux.scala:30:73] wire [22:0] _issue_entry_T_3692 = _issue_entry_T_3691 | _issue_entry_T_3677; // @[Mux.scala:30:73] assign _issue_entry_WIRE_211 = _issue_entry_T_3692; // @[Mux.scala:30:73] assign _issue_entry_WIRE_183_zero2 = _issue_entry_WIRE_211; // @[Mux.scala:30:73] wire _issue_entry_T_3693 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30] wire _issue_entry_T_3694 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30] wire _issue_entry_T_3695 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30] wire _issue_entry_T_3696 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30] wire _issue_entry_T_3697 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30] wire _issue_entry_T_3698 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30] wire _issue_entry_T_3699 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30] wire _issue_entry_T_3700 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30] wire _issue_entry_T_3701 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30] wire _issue_entry_T_3702 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30] wire _issue_entry_T_3703 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30] wire _issue_entry_T_3704 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30] wire _issue_entry_T_3705 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30] wire _issue_entry_T_3706 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30] wire _issue_entry_T_3707 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30] wire _issue_entry_T_3708 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30] wire _issue_entry_T_3709 = _issue_entry_T_3693 | _issue_entry_T_3694; // @[Mux.scala:30:73] wire _issue_entry_T_3710 = _issue_entry_T_3709 | _issue_entry_T_3695; // @[Mux.scala:30:73] wire _issue_entry_T_3711 = _issue_entry_T_3710 | _issue_entry_T_3696; // @[Mux.scala:30:73] wire _issue_entry_T_3712 = _issue_entry_T_3711 | _issue_entry_T_3697; // @[Mux.scala:30:73] wire _issue_entry_T_3713 = _issue_entry_T_3712 | _issue_entry_T_3698; // @[Mux.scala:30:73] wire _issue_entry_T_3714 = _issue_entry_T_3713 | _issue_entry_T_3699; // @[Mux.scala:30:73] wire _issue_entry_T_3715 = _issue_entry_T_3714 | _issue_entry_T_3700; // @[Mux.scala:30:73] wire _issue_entry_T_3716 = _issue_entry_T_3715 | _issue_entry_T_3701; // @[Mux.scala:30:73] wire _issue_entry_T_3717 = _issue_entry_T_3716 | _issue_entry_T_3702; // @[Mux.scala:30:73] wire _issue_entry_T_3718 = _issue_entry_T_3717 | _issue_entry_T_3703; // @[Mux.scala:30:73] wire _issue_entry_T_3719 = _issue_entry_T_3718 | _issue_entry_T_3704; // @[Mux.scala:30:73] wire _issue_entry_T_3720 = _issue_entry_T_3719 | _issue_entry_T_3705; // @[Mux.scala:30:73] wire _issue_entry_T_3721 = _issue_entry_T_3720 | _issue_entry_T_3706; // @[Mux.scala:30:73] wire _issue_entry_T_3722 = _issue_entry_T_3721 | _issue_entry_T_3707; // @[Mux.scala:30:73] wire _issue_entry_T_3723 = _issue_entry_T_3722 | _issue_entry_T_3708; // @[Mux.scala:30:73] assign _issue_entry_WIRE_212 = _issue_entry_T_3723; // @[Mux.scala:30:73] assign _issue_entry_WIRE_183_sd = _issue_entry_WIRE_212; // @[Mux.scala:30:73] wire _issue_entry_T_3724 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30] wire _issue_entry_T_3725 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30] wire _issue_entry_T_3726 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30] wire _issue_entry_T_3727 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30] wire _issue_entry_T_3728 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30] wire _issue_entry_T_3729 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30] wire _issue_entry_T_3730 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30] wire _issue_entry_T_3731 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30] wire _issue_entry_T_3732 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30] wire _issue_entry_T_3733 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30] wire _issue_entry_T_3734 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30] wire _issue_entry_T_3735 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30] wire _issue_entry_T_3736 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30] wire _issue_entry_T_3737 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30] wire _issue_entry_T_3738 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30] wire _issue_entry_T_3739 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30] wire _issue_entry_T_3740 = _issue_entry_T_3724 | _issue_entry_T_3725; // @[Mux.scala:30:73] wire _issue_entry_T_3741 = _issue_entry_T_3740 | _issue_entry_T_3726; // @[Mux.scala:30:73] wire _issue_entry_T_3742 = _issue_entry_T_3741 | _issue_entry_T_3727; // @[Mux.scala:30:73] wire _issue_entry_T_3743 = _issue_entry_T_3742 | _issue_entry_T_3728; // @[Mux.scala:30:73] wire _issue_entry_T_3744 = _issue_entry_T_3743 | _issue_entry_T_3729; // @[Mux.scala:30:73] wire _issue_entry_T_3745 = _issue_entry_T_3744 | _issue_entry_T_3730; // @[Mux.scala:30:73] wire _issue_entry_T_3746 = _issue_entry_T_3745 | _issue_entry_T_3731; // @[Mux.scala:30:73] wire _issue_entry_T_3747 = _issue_entry_T_3746 | _issue_entry_T_3732; // @[Mux.scala:30:73] wire _issue_entry_T_3748 = _issue_entry_T_3747 | _issue_entry_T_3733; // @[Mux.scala:30:73] wire _issue_entry_T_3749 = _issue_entry_T_3748 | _issue_entry_T_3734; // @[Mux.scala:30:73] wire _issue_entry_T_3750 = _issue_entry_T_3749 | _issue_entry_T_3735; // @[Mux.scala:30:73] wire _issue_entry_T_3751 = _issue_entry_T_3750 | _issue_entry_T_3736; // @[Mux.scala:30:73] wire _issue_entry_T_3752 = _issue_entry_T_3751 | _issue_entry_T_3737; // @[Mux.scala:30:73] wire _issue_entry_T_3753 = _issue_entry_T_3752 | _issue_entry_T_3738; // @[Mux.scala:30:73] wire _issue_entry_T_3754 = _issue_entry_T_3753 | _issue_entry_T_3739; // @[Mux.scala:30:73] assign _issue_entry_WIRE_213 = _issue_entry_T_3754; // @[Mux.scala:30:73] assign _issue_entry_WIRE_183_v = _issue_entry_WIRE_213; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3755 = issue_sel_0_1 ? entries_ex_0_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3756 = issue_sel_1_1 ? entries_ex_1_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3757 = issue_sel_2_1 ? entries_ex_2_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3758 = issue_sel_3_1 ? entries_ex_3_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3759 = issue_sel_4_1 ? entries_ex_4_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3760 = issue_sel_5_1 ? entries_ex_5_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3761 = issue_sel_6_1 ? entries_ex_6_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3762 = issue_sel_7_1 ? entries_ex_7_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3763 = issue_sel_8 ? entries_ex_8_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3764 = issue_sel_9 ? entries_ex_9_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3765 = issue_sel_10 ? entries_ex_10_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3766 = issue_sel_11 ? entries_ex_11_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3767 = issue_sel_12 ? entries_ex_12_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3768 = issue_sel_13 ? entries_ex_13_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3769 = issue_sel_14 ? entries_ex_14_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3770 = issue_sel_15 ? entries_ex_15_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3771 = _issue_entry_T_3755 | _issue_entry_T_3756; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3772 = _issue_entry_T_3771 | _issue_entry_T_3757; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3773 = _issue_entry_T_3772 | _issue_entry_T_3758; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3774 = _issue_entry_T_3773 | _issue_entry_T_3759; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3775 = _issue_entry_T_3774 | _issue_entry_T_3760; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3776 = _issue_entry_T_3775 | _issue_entry_T_3761; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3777 = _issue_entry_T_3776 | _issue_entry_T_3762; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3778 = _issue_entry_T_3777 | _issue_entry_T_3763; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3779 = _issue_entry_T_3778 | _issue_entry_T_3764; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3780 = _issue_entry_T_3779 | _issue_entry_T_3765; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3781 = _issue_entry_T_3780 | _issue_entry_T_3766; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3782 = _issue_entry_T_3781 | _issue_entry_T_3767; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3783 = _issue_entry_T_3782 | _issue_entry_T_3768; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3784 = _issue_entry_T_3783 | _issue_entry_T_3769; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3785 = _issue_entry_T_3784 | _issue_entry_T_3770; // @[Mux.scala:30:73] assign _issue_entry_WIRE_214 = _issue_entry_T_3785; // @[Mux.scala:30:73] assign _issue_entry_WIRE_183_prv = _issue_entry_WIRE_214; // @[Mux.scala:30:73] wire _issue_entry_T_3786 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30] wire _issue_entry_T_3787 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30] wire _issue_entry_T_3788 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30] wire _issue_entry_T_3789 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30] wire _issue_entry_T_3790 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30] wire _issue_entry_T_3791 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30] wire _issue_entry_T_3792 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30] wire _issue_entry_T_3793 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30] wire _issue_entry_T_3794 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30] wire _issue_entry_T_3795 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30] wire _issue_entry_T_3796 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30] wire _issue_entry_T_3797 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30] wire _issue_entry_T_3798 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30] wire _issue_entry_T_3799 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30] wire _issue_entry_T_3800 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30] wire _issue_entry_T_3801 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30] wire _issue_entry_T_3802 = _issue_entry_T_3786 | _issue_entry_T_3787; // @[Mux.scala:30:73] wire _issue_entry_T_3803 = _issue_entry_T_3802 | _issue_entry_T_3788; // @[Mux.scala:30:73] wire _issue_entry_T_3804 = _issue_entry_T_3803 | _issue_entry_T_3789; // @[Mux.scala:30:73] wire _issue_entry_T_3805 = _issue_entry_T_3804 | _issue_entry_T_3790; // @[Mux.scala:30:73] wire _issue_entry_T_3806 = _issue_entry_T_3805 | _issue_entry_T_3791; // @[Mux.scala:30:73] wire _issue_entry_T_3807 = _issue_entry_T_3806 | _issue_entry_T_3792; // @[Mux.scala:30:73] wire _issue_entry_T_3808 = _issue_entry_T_3807 | _issue_entry_T_3793; // @[Mux.scala:30:73] wire _issue_entry_T_3809 = _issue_entry_T_3808 | _issue_entry_T_3794; // @[Mux.scala:30:73] wire _issue_entry_T_3810 = _issue_entry_T_3809 | _issue_entry_T_3795; // @[Mux.scala:30:73] wire _issue_entry_T_3811 = _issue_entry_T_3810 | _issue_entry_T_3796; // @[Mux.scala:30:73] wire _issue_entry_T_3812 = _issue_entry_T_3811 | _issue_entry_T_3797; // @[Mux.scala:30:73] wire _issue_entry_T_3813 = _issue_entry_T_3812 | _issue_entry_T_3798; // @[Mux.scala:30:73] wire _issue_entry_T_3814 = _issue_entry_T_3813 | _issue_entry_T_3799; // @[Mux.scala:30:73] wire _issue_entry_T_3815 = _issue_entry_T_3814 | _issue_entry_T_3800; // @[Mux.scala:30:73] wire _issue_entry_T_3816 = _issue_entry_T_3815 | _issue_entry_T_3801; // @[Mux.scala:30:73] assign _issue_entry_WIRE_215 = _issue_entry_T_3816; // @[Mux.scala:30:73] assign _issue_entry_WIRE_183_dv = _issue_entry_WIRE_215; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3817 = issue_sel_0_1 ? entries_ex_0_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3818 = issue_sel_1_1 ? entries_ex_1_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3819 = issue_sel_2_1 ? entries_ex_2_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3820 = issue_sel_3_1 ? entries_ex_3_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3821 = issue_sel_4_1 ? entries_ex_4_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3822 = issue_sel_5_1 ? entries_ex_5_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3823 = issue_sel_6_1 ? entries_ex_6_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3824 = issue_sel_7_1 ? entries_ex_7_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3825 = issue_sel_8 ? entries_ex_8_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3826 = issue_sel_9 ? entries_ex_9_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3827 = issue_sel_10 ? entries_ex_10_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3828 = issue_sel_11 ? entries_ex_11_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3829 = issue_sel_12 ? entries_ex_12_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3830 = issue_sel_13 ? entries_ex_13_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3831 = issue_sel_14 ? entries_ex_14_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3832 = issue_sel_15 ? entries_ex_15_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_3833 = _issue_entry_T_3817 | _issue_entry_T_3818; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3834 = _issue_entry_T_3833 | _issue_entry_T_3819; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3835 = _issue_entry_T_3834 | _issue_entry_T_3820; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3836 = _issue_entry_T_3835 | _issue_entry_T_3821; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3837 = _issue_entry_T_3836 | _issue_entry_T_3822; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3838 = _issue_entry_T_3837 | _issue_entry_T_3823; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3839 = _issue_entry_T_3838 | _issue_entry_T_3824; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3840 = _issue_entry_T_3839 | _issue_entry_T_3825; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3841 = _issue_entry_T_3840 | _issue_entry_T_3826; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3842 = _issue_entry_T_3841 | _issue_entry_T_3827; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3843 = _issue_entry_T_3842 | _issue_entry_T_3828; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3844 = _issue_entry_T_3843 | _issue_entry_T_3829; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3845 = _issue_entry_T_3844 | _issue_entry_T_3830; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3846 = _issue_entry_T_3845 | _issue_entry_T_3831; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_3847 = _issue_entry_T_3846 | _issue_entry_T_3832; // @[Mux.scala:30:73] assign _issue_entry_WIRE_216 = _issue_entry_T_3847; // @[Mux.scala:30:73] assign _issue_entry_WIRE_183_dprv = _issue_entry_WIRE_216; // @[Mux.scala:30:73] wire [31:0] _issue_entry_T_3848 = issue_sel_0_1 ? entries_ex_0_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_3849 = issue_sel_1_1 ? entries_ex_1_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_3850 = issue_sel_2_1 ? entries_ex_2_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_3851 = issue_sel_3_1 ? entries_ex_3_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_3852 = issue_sel_4_1 ? entries_ex_4_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_3853 = issue_sel_5_1 ? entries_ex_5_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_3854 = issue_sel_6_1 ? entries_ex_6_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_3855 = issue_sel_7_1 ? entries_ex_7_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_3856 = issue_sel_8 ? entries_ex_8_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_3857 = issue_sel_9 ? entries_ex_9_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_3858 = issue_sel_10 ? entries_ex_10_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_3859 = issue_sel_11 ? entries_ex_11_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_3860 = issue_sel_12 ? entries_ex_12_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_3861 = issue_sel_13 ? entries_ex_13_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_3862 = issue_sel_14 ? entries_ex_14_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_3863 = issue_sel_15 ? entries_ex_15_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_3864 = _issue_entry_T_3848 | _issue_entry_T_3849; // @[Mux.scala:30:73] wire [31:0] _issue_entry_T_3865 = _issue_entry_T_3864 | _issue_entry_T_3850; // @[Mux.scala:30:73] wire [31:0] _issue_entry_T_3866 = _issue_entry_T_3865 | _issue_entry_T_3851; // @[Mux.scala:30:73] wire [31:0] _issue_entry_T_3867 = _issue_entry_T_3866 | _issue_entry_T_3852; // @[Mux.scala:30:73] wire [31:0] _issue_entry_T_3868 = _issue_entry_T_3867 | _issue_entry_T_3853; // @[Mux.scala:30:73] wire [31:0] _issue_entry_T_3869 = _issue_entry_T_3868 | _issue_entry_T_3854; // @[Mux.scala:30:73] wire [31:0] _issue_entry_T_3870 = _issue_entry_T_3869 | _issue_entry_T_3855; // @[Mux.scala:30:73] wire [31:0] _issue_entry_T_3871 = _issue_entry_T_3870 | _issue_entry_T_3856; // @[Mux.scala:30:73] wire [31:0] _issue_entry_T_3872 = _issue_entry_T_3871 | _issue_entry_T_3857; // @[Mux.scala:30:73] wire [31:0] _issue_entry_T_3873 = _issue_entry_T_3872 | _issue_entry_T_3858; // @[Mux.scala:30:73] wire [31:0] _issue_entry_T_3874 = _issue_entry_T_3873 | _issue_entry_T_3859; // @[Mux.scala:30:73] wire [31:0] _issue_entry_T_3875 = _issue_entry_T_3874 | _issue_entry_T_3860; // @[Mux.scala:30:73] wire [31:0] _issue_entry_T_3876 = _issue_entry_T_3875 | _issue_entry_T_3861; // @[Mux.scala:30:73] wire [31:0] _issue_entry_T_3877 = _issue_entry_T_3876 | _issue_entry_T_3862; // @[Mux.scala:30:73] wire [31:0] _issue_entry_T_3878 = _issue_entry_T_3877 | _issue_entry_T_3863; // @[Mux.scala:30:73] assign _issue_entry_WIRE_217 = _issue_entry_T_3878; // @[Mux.scala:30:73] assign _issue_entry_WIRE_183_isa = _issue_entry_WIRE_217; // @[Mux.scala:30:73] wire _issue_entry_T_3879 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30] wire _issue_entry_T_3880 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30] wire _issue_entry_T_3881 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30] wire _issue_entry_T_3882 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30] wire _issue_entry_T_3883 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30] wire _issue_entry_T_3884 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30] wire _issue_entry_T_3885 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30] wire _issue_entry_T_3886 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30] wire _issue_entry_T_3887 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30] wire _issue_entry_T_3888 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30] wire _issue_entry_T_3889 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30] wire _issue_entry_T_3890 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30] wire _issue_entry_T_3891 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30] wire _issue_entry_T_3892 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30] wire _issue_entry_T_3893 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30] wire _issue_entry_T_3894 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30] wire _issue_entry_T_3895 = _issue_entry_T_3879 | _issue_entry_T_3880; // @[Mux.scala:30:73] wire _issue_entry_T_3896 = _issue_entry_T_3895 | _issue_entry_T_3881; // @[Mux.scala:30:73] wire _issue_entry_T_3897 = _issue_entry_T_3896 | _issue_entry_T_3882; // @[Mux.scala:30:73] wire _issue_entry_T_3898 = _issue_entry_T_3897 | _issue_entry_T_3883; // @[Mux.scala:30:73] wire _issue_entry_T_3899 = _issue_entry_T_3898 | _issue_entry_T_3884; // @[Mux.scala:30:73] wire _issue_entry_T_3900 = _issue_entry_T_3899 | _issue_entry_T_3885; // @[Mux.scala:30:73] wire _issue_entry_T_3901 = _issue_entry_T_3900 | _issue_entry_T_3886; // @[Mux.scala:30:73] wire _issue_entry_T_3902 = _issue_entry_T_3901 | _issue_entry_T_3887; // @[Mux.scala:30:73] wire _issue_entry_T_3903 = _issue_entry_T_3902 | _issue_entry_T_3888; // @[Mux.scala:30:73] wire _issue_entry_T_3904 = _issue_entry_T_3903 | _issue_entry_T_3889; // @[Mux.scala:30:73] wire _issue_entry_T_3905 = _issue_entry_T_3904 | _issue_entry_T_3890; // @[Mux.scala:30:73] wire _issue_entry_T_3906 = _issue_entry_T_3905 | _issue_entry_T_3891; // @[Mux.scala:30:73] wire _issue_entry_T_3907 = _issue_entry_T_3906 | _issue_entry_T_3892; // @[Mux.scala:30:73] wire _issue_entry_T_3908 = _issue_entry_T_3907 | _issue_entry_T_3893; // @[Mux.scala:30:73] wire _issue_entry_T_3909 = _issue_entry_T_3908 | _issue_entry_T_3894; // @[Mux.scala:30:73] assign _issue_entry_WIRE_218 = _issue_entry_T_3909; // @[Mux.scala:30:73] assign _issue_entry_WIRE_183_wfi = _issue_entry_WIRE_218; // @[Mux.scala:30:73] wire _issue_entry_T_3910 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30] wire _issue_entry_T_3911 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30] wire _issue_entry_T_3912 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30] wire _issue_entry_T_3913 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30] wire _issue_entry_T_3914 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30] wire _issue_entry_T_3915 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30] wire _issue_entry_T_3916 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30] wire _issue_entry_T_3917 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30] wire _issue_entry_T_3918 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30] wire _issue_entry_T_3919 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30] wire _issue_entry_T_3920 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30] wire _issue_entry_T_3921 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30] wire _issue_entry_T_3922 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30] wire _issue_entry_T_3923 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30] wire _issue_entry_T_3924 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30] wire _issue_entry_T_3925 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30] wire _issue_entry_T_3926 = _issue_entry_T_3910 | _issue_entry_T_3911; // @[Mux.scala:30:73] wire _issue_entry_T_3927 = _issue_entry_T_3926 | _issue_entry_T_3912; // @[Mux.scala:30:73] wire _issue_entry_T_3928 = _issue_entry_T_3927 | _issue_entry_T_3913; // @[Mux.scala:30:73] wire _issue_entry_T_3929 = _issue_entry_T_3928 | _issue_entry_T_3914; // @[Mux.scala:30:73] wire _issue_entry_T_3930 = _issue_entry_T_3929 | _issue_entry_T_3915; // @[Mux.scala:30:73] wire _issue_entry_T_3931 = _issue_entry_T_3930 | _issue_entry_T_3916; // @[Mux.scala:30:73] wire _issue_entry_T_3932 = _issue_entry_T_3931 | _issue_entry_T_3917; // @[Mux.scala:30:73] wire _issue_entry_T_3933 = _issue_entry_T_3932 | _issue_entry_T_3918; // @[Mux.scala:30:73] wire _issue_entry_T_3934 = _issue_entry_T_3933 | _issue_entry_T_3919; // @[Mux.scala:30:73] wire _issue_entry_T_3935 = _issue_entry_T_3934 | _issue_entry_T_3920; // @[Mux.scala:30:73] wire _issue_entry_T_3936 = _issue_entry_T_3935 | _issue_entry_T_3921; // @[Mux.scala:30:73] wire _issue_entry_T_3937 = _issue_entry_T_3936 | _issue_entry_T_3922; // @[Mux.scala:30:73] wire _issue_entry_T_3938 = _issue_entry_T_3937 | _issue_entry_T_3923; // @[Mux.scala:30:73] wire _issue_entry_T_3939 = _issue_entry_T_3938 | _issue_entry_T_3924; // @[Mux.scala:30:73] wire _issue_entry_T_3940 = _issue_entry_T_3939 | _issue_entry_T_3925; // @[Mux.scala:30:73] assign _issue_entry_WIRE_219 = _issue_entry_T_3940; // @[Mux.scala:30:73] assign _issue_entry_WIRE_183_cease = _issue_entry_WIRE_219; // @[Mux.scala:30:73] wire _issue_entry_T_3941 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30] wire _issue_entry_T_3942 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30] wire _issue_entry_T_3943 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30] wire _issue_entry_T_3944 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30] wire _issue_entry_T_3945 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30] wire _issue_entry_T_3946 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30] wire _issue_entry_T_3947 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30] wire _issue_entry_T_3948 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30] wire _issue_entry_T_3949 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30] wire _issue_entry_T_3950 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30] wire _issue_entry_T_3951 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30] wire _issue_entry_T_3952 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30] wire _issue_entry_T_3953 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30] wire _issue_entry_T_3954 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30] wire _issue_entry_T_3955 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30] wire _issue_entry_T_3956 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30] wire _issue_entry_T_3957 = _issue_entry_T_3941 | _issue_entry_T_3942; // @[Mux.scala:30:73] wire _issue_entry_T_3958 = _issue_entry_T_3957 | _issue_entry_T_3943; // @[Mux.scala:30:73] wire _issue_entry_T_3959 = _issue_entry_T_3958 | _issue_entry_T_3944; // @[Mux.scala:30:73] wire _issue_entry_T_3960 = _issue_entry_T_3959 | _issue_entry_T_3945; // @[Mux.scala:30:73] wire _issue_entry_T_3961 = _issue_entry_T_3960 | _issue_entry_T_3946; // @[Mux.scala:30:73] wire _issue_entry_T_3962 = _issue_entry_T_3961 | _issue_entry_T_3947; // @[Mux.scala:30:73] wire _issue_entry_T_3963 = _issue_entry_T_3962 | _issue_entry_T_3948; // @[Mux.scala:30:73] wire _issue_entry_T_3964 = _issue_entry_T_3963 | _issue_entry_T_3949; // @[Mux.scala:30:73] wire _issue_entry_T_3965 = _issue_entry_T_3964 | _issue_entry_T_3950; // @[Mux.scala:30:73] wire _issue_entry_T_3966 = _issue_entry_T_3965 | _issue_entry_T_3951; // @[Mux.scala:30:73] wire _issue_entry_T_3967 = _issue_entry_T_3966 | _issue_entry_T_3952; // @[Mux.scala:30:73] wire _issue_entry_T_3968 = _issue_entry_T_3967 | _issue_entry_T_3953; // @[Mux.scala:30:73] wire _issue_entry_T_3969 = _issue_entry_T_3968 | _issue_entry_T_3954; // @[Mux.scala:30:73] wire _issue_entry_T_3970 = _issue_entry_T_3969 | _issue_entry_T_3955; // @[Mux.scala:30:73] wire _issue_entry_T_3971 = _issue_entry_T_3970 | _issue_entry_T_3956; // @[Mux.scala:30:73] assign _issue_entry_WIRE_220 = _issue_entry_T_3971; // @[Mux.scala:30:73] assign _issue_entry_WIRE_183_debug = _issue_entry_WIRE_220; // @[Mux.scala:30:73] wire [63:0] _issue_entry_T_3972 = issue_sel_0_1 ? entries_ex_0_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_3973 = issue_sel_1_1 ? entries_ex_1_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_3974 = issue_sel_2_1 ? entries_ex_2_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_3975 = issue_sel_3_1 ? entries_ex_3_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_3976 = issue_sel_4_1 ? entries_ex_4_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_3977 = issue_sel_5_1 ? entries_ex_5_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_3978 = issue_sel_6_1 ? entries_ex_6_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_3979 = issue_sel_7_1 ? entries_ex_7_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_3980 = issue_sel_8 ? entries_ex_8_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_3981 = issue_sel_9 ? entries_ex_9_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_3982 = issue_sel_10 ? entries_ex_10_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_3983 = issue_sel_11 ? entries_ex_11_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_3984 = issue_sel_12 ? entries_ex_12_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_3985 = issue_sel_13 ? entries_ex_13_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_3986 = issue_sel_14 ? entries_ex_14_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_3987 = issue_sel_15 ? entries_ex_15_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_3988 = _issue_entry_T_3972 | _issue_entry_T_3973; // @[Mux.scala:30:73] wire [63:0] _issue_entry_T_3989 = _issue_entry_T_3988 | _issue_entry_T_3974; // @[Mux.scala:30:73] wire [63:0] _issue_entry_T_3990 = _issue_entry_T_3989 | _issue_entry_T_3975; // @[Mux.scala:30:73] wire [63:0] _issue_entry_T_3991 = _issue_entry_T_3990 | _issue_entry_T_3976; // @[Mux.scala:30:73] wire [63:0] _issue_entry_T_3992 = _issue_entry_T_3991 | _issue_entry_T_3977; // @[Mux.scala:30:73] wire [63:0] _issue_entry_T_3993 = _issue_entry_T_3992 | _issue_entry_T_3978; // @[Mux.scala:30:73] wire [63:0] _issue_entry_T_3994 = _issue_entry_T_3993 | _issue_entry_T_3979; // @[Mux.scala:30:73] wire [63:0] _issue_entry_T_3995 = _issue_entry_T_3994 | _issue_entry_T_3980; // @[Mux.scala:30:73] wire [63:0] _issue_entry_T_3996 = _issue_entry_T_3995 | _issue_entry_T_3981; // @[Mux.scala:30:73] wire [63:0] _issue_entry_T_3997 = _issue_entry_T_3996 | _issue_entry_T_3982; // @[Mux.scala:30:73] wire [63:0] _issue_entry_T_3998 = _issue_entry_T_3997 | _issue_entry_T_3983; // @[Mux.scala:30:73] wire [63:0] _issue_entry_T_3999 = _issue_entry_T_3998 | _issue_entry_T_3984; // @[Mux.scala:30:73] wire [63:0] _issue_entry_T_4000 = _issue_entry_T_3999 | _issue_entry_T_3985; // @[Mux.scala:30:73] wire [63:0] _issue_entry_T_4001 = _issue_entry_T_4000 | _issue_entry_T_3986; // @[Mux.scala:30:73] wire [63:0] _issue_entry_T_4002 = _issue_entry_T_4001 | _issue_entry_T_3987; // @[Mux.scala:30:73] assign _issue_entry_WIRE_221 = _issue_entry_T_4002; // @[Mux.scala:30:73] assign _issue_entry_WIRE_182_rs2 = _issue_entry_WIRE_221; // @[Mux.scala:30:73] wire [63:0] _issue_entry_T_4003 = issue_sel_0_1 ? entries_ex_0_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_4004 = issue_sel_1_1 ? entries_ex_1_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_4005 = issue_sel_2_1 ? entries_ex_2_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_4006 = issue_sel_3_1 ? entries_ex_3_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_4007 = issue_sel_4_1 ? entries_ex_4_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_4008 = issue_sel_5_1 ? entries_ex_5_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_4009 = issue_sel_6_1 ? entries_ex_6_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_4010 = issue_sel_7_1 ? entries_ex_7_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_4011 = issue_sel_8 ? entries_ex_8_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_4012 = issue_sel_9 ? entries_ex_9_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_4013 = issue_sel_10 ? entries_ex_10_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_4014 = issue_sel_11 ? entries_ex_11_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_4015 = issue_sel_12 ? entries_ex_12_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_4016 = issue_sel_13 ? entries_ex_13_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_4017 = issue_sel_14 ? entries_ex_14_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_4018 = issue_sel_15 ? entries_ex_15_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_4019 = _issue_entry_T_4003 | _issue_entry_T_4004; // @[Mux.scala:30:73] wire [63:0] _issue_entry_T_4020 = _issue_entry_T_4019 | _issue_entry_T_4005; // @[Mux.scala:30:73] wire [63:0] _issue_entry_T_4021 = _issue_entry_T_4020 | _issue_entry_T_4006; // @[Mux.scala:30:73] wire [63:0] _issue_entry_T_4022 = _issue_entry_T_4021 | _issue_entry_T_4007; // @[Mux.scala:30:73] wire [63:0] _issue_entry_T_4023 = _issue_entry_T_4022 | _issue_entry_T_4008; // @[Mux.scala:30:73] wire [63:0] _issue_entry_T_4024 = _issue_entry_T_4023 | _issue_entry_T_4009; // @[Mux.scala:30:73] wire [63:0] _issue_entry_T_4025 = _issue_entry_T_4024 | _issue_entry_T_4010; // @[Mux.scala:30:73] wire [63:0] _issue_entry_T_4026 = _issue_entry_T_4025 | _issue_entry_T_4011; // @[Mux.scala:30:73] wire [63:0] _issue_entry_T_4027 = _issue_entry_T_4026 | _issue_entry_T_4012; // @[Mux.scala:30:73] wire [63:0] _issue_entry_T_4028 = _issue_entry_T_4027 | _issue_entry_T_4013; // @[Mux.scala:30:73] wire [63:0] _issue_entry_T_4029 = _issue_entry_T_4028 | _issue_entry_T_4014; // @[Mux.scala:30:73] wire [63:0] _issue_entry_T_4030 = _issue_entry_T_4029 | _issue_entry_T_4015; // @[Mux.scala:30:73] wire [63:0] _issue_entry_T_4031 = _issue_entry_T_4030 | _issue_entry_T_4016; // @[Mux.scala:30:73] wire [63:0] _issue_entry_T_4032 = _issue_entry_T_4031 | _issue_entry_T_4017; // @[Mux.scala:30:73] wire [63:0] _issue_entry_T_4033 = _issue_entry_T_4032 | _issue_entry_T_4018; // @[Mux.scala:30:73] assign _issue_entry_WIRE_222 = _issue_entry_T_4033; // @[Mux.scala:30:73] assign _issue_entry_WIRE_182_rs1 = _issue_entry_WIRE_222; // @[Mux.scala:30:73] wire [6:0] _issue_entry_WIRE_231; // @[Mux.scala:30:73] assign _issue_entry_WIRE_182_inst_funct = _issue_entry_WIRE_223_funct; // @[Mux.scala:30:73] wire [4:0] _issue_entry_WIRE_230; // @[Mux.scala:30:73] assign _issue_entry_WIRE_182_inst_rs2 = _issue_entry_WIRE_223_rs2; // @[Mux.scala:30:73] wire [4:0] _issue_entry_WIRE_229; // @[Mux.scala:30:73] assign _issue_entry_WIRE_182_inst_rs1 = _issue_entry_WIRE_223_rs1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_228; // @[Mux.scala:30:73] assign _issue_entry_WIRE_182_inst_xd = _issue_entry_WIRE_223_xd; // @[Mux.scala:30:73] wire _issue_entry_WIRE_227; // @[Mux.scala:30:73] assign _issue_entry_WIRE_182_inst_xs1 = _issue_entry_WIRE_223_xs1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_226; // @[Mux.scala:30:73] assign _issue_entry_WIRE_182_inst_xs2 = _issue_entry_WIRE_223_xs2; // @[Mux.scala:30:73] wire [4:0] _issue_entry_WIRE_225; // @[Mux.scala:30:73] assign _issue_entry_WIRE_182_inst_rd = _issue_entry_WIRE_223_rd; // @[Mux.scala:30:73] wire [6:0] _issue_entry_WIRE_224; // @[Mux.scala:30:73] assign _issue_entry_WIRE_182_inst_opcode = _issue_entry_WIRE_223_opcode; // @[Mux.scala:30:73] wire [6:0] _issue_entry_T_4034 = issue_sel_0_1 ? entries_ex_0_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_4035 = issue_sel_1_1 ? entries_ex_1_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_4036 = issue_sel_2_1 ? entries_ex_2_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_4037 = issue_sel_3_1 ? entries_ex_3_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_4038 = issue_sel_4_1 ? entries_ex_4_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_4039 = issue_sel_5_1 ? entries_ex_5_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_4040 = issue_sel_6_1 ? entries_ex_6_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_4041 = issue_sel_7_1 ? entries_ex_7_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_4042 = issue_sel_8 ? entries_ex_8_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_4043 = issue_sel_9 ? entries_ex_9_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_4044 = issue_sel_10 ? entries_ex_10_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_4045 = issue_sel_11 ? entries_ex_11_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_4046 = issue_sel_12 ? entries_ex_12_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_4047 = issue_sel_13 ? entries_ex_13_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_4048 = issue_sel_14 ? entries_ex_14_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_4049 = issue_sel_15 ? entries_ex_15_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_4050 = _issue_entry_T_4034 | _issue_entry_T_4035; // @[Mux.scala:30:73] wire [6:0] _issue_entry_T_4051 = _issue_entry_T_4050 | _issue_entry_T_4036; // @[Mux.scala:30:73] wire [6:0] _issue_entry_T_4052 = _issue_entry_T_4051 | _issue_entry_T_4037; // @[Mux.scala:30:73] wire [6:0] _issue_entry_T_4053 = _issue_entry_T_4052 | _issue_entry_T_4038; // @[Mux.scala:30:73] wire [6:0] _issue_entry_T_4054 = _issue_entry_T_4053 | _issue_entry_T_4039; // @[Mux.scala:30:73] wire [6:0] _issue_entry_T_4055 = _issue_entry_T_4054 | _issue_entry_T_4040; // @[Mux.scala:30:73] wire [6:0] _issue_entry_T_4056 = _issue_entry_T_4055 | _issue_entry_T_4041; // @[Mux.scala:30:73] wire [6:0] _issue_entry_T_4057 = _issue_entry_T_4056 | _issue_entry_T_4042; // @[Mux.scala:30:73] wire [6:0] _issue_entry_T_4058 = _issue_entry_T_4057 | _issue_entry_T_4043; // @[Mux.scala:30:73] wire [6:0] _issue_entry_T_4059 = _issue_entry_T_4058 | _issue_entry_T_4044; // @[Mux.scala:30:73] wire [6:0] _issue_entry_T_4060 = _issue_entry_T_4059 | _issue_entry_T_4045; // @[Mux.scala:30:73] wire [6:0] _issue_entry_T_4061 = _issue_entry_T_4060 | _issue_entry_T_4046; // @[Mux.scala:30:73] wire [6:0] _issue_entry_T_4062 = _issue_entry_T_4061 | _issue_entry_T_4047; // @[Mux.scala:30:73] wire [6:0] _issue_entry_T_4063 = _issue_entry_T_4062 | _issue_entry_T_4048; // @[Mux.scala:30:73] wire [6:0] _issue_entry_T_4064 = _issue_entry_T_4063 | _issue_entry_T_4049; // @[Mux.scala:30:73] assign _issue_entry_WIRE_224 = _issue_entry_T_4064; // @[Mux.scala:30:73] assign _issue_entry_WIRE_223_opcode = _issue_entry_WIRE_224; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_4065 = issue_sel_0_1 ? entries_ex_0_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_4066 = issue_sel_1_1 ? entries_ex_1_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_4067 = issue_sel_2_1 ? entries_ex_2_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_4068 = issue_sel_3_1 ? entries_ex_3_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_4069 = issue_sel_4_1 ? entries_ex_4_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_4070 = issue_sel_5_1 ? entries_ex_5_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_4071 = issue_sel_6_1 ? entries_ex_6_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_4072 = issue_sel_7_1 ? entries_ex_7_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_4073 = issue_sel_8 ? entries_ex_8_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_4074 = issue_sel_9 ? entries_ex_9_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_4075 = issue_sel_10 ? entries_ex_10_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_4076 = issue_sel_11 ? entries_ex_11_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_4077 = issue_sel_12 ? entries_ex_12_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_4078 = issue_sel_13 ? entries_ex_13_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_4079 = issue_sel_14 ? entries_ex_14_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_4080 = issue_sel_15 ? entries_ex_15_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_4081 = _issue_entry_T_4065 | _issue_entry_T_4066; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_4082 = _issue_entry_T_4081 | _issue_entry_T_4067; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_4083 = _issue_entry_T_4082 | _issue_entry_T_4068; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_4084 = _issue_entry_T_4083 | _issue_entry_T_4069; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_4085 = _issue_entry_T_4084 | _issue_entry_T_4070; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_4086 = _issue_entry_T_4085 | _issue_entry_T_4071; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_4087 = _issue_entry_T_4086 | _issue_entry_T_4072; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_4088 = _issue_entry_T_4087 | _issue_entry_T_4073; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_4089 = _issue_entry_T_4088 | _issue_entry_T_4074; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_4090 = _issue_entry_T_4089 | _issue_entry_T_4075; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_4091 = _issue_entry_T_4090 | _issue_entry_T_4076; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_4092 = _issue_entry_T_4091 | _issue_entry_T_4077; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_4093 = _issue_entry_T_4092 | _issue_entry_T_4078; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_4094 = _issue_entry_T_4093 | _issue_entry_T_4079; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_4095 = _issue_entry_T_4094 | _issue_entry_T_4080; // @[Mux.scala:30:73] assign _issue_entry_WIRE_225 = _issue_entry_T_4095; // @[Mux.scala:30:73] assign _issue_entry_WIRE_223_rd = _issue_entry_WIRE_225; // @[Mux.scala:30:73] wire _issue_entry_T_4096 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30] wire _issue_entry_T_4097 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30] wire _issue_entry_T_4098 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30] wire _issue_entry_T_4099 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30] wire _issue_entry_T_4100 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30] wire _issue_entry_T_4101 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30] wire _issue_entry_T_4102 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30] wire _issue_entry_T_4103 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30] wire _issue_entry_T_4104 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30] wire _issue_entry_T_4105 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30] wire _issue_entry_T_4106 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30] wire _issue_entry_T_4107 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30] wire _issue_entry_T_4108 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30] wire _issue_entry_T_4109 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30] wire _issue_entry_T_4110 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30] wire _issue_entry_T_4111 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30] wire _issue_entry_T_4112 = _issue_entry_T_4096 | _issue_entry_T_4097; // @[Mux.scala:30:73] wire _issue_entry_T_4113 = _issue_entry_T_4112 | _issue_entry_T_4098; // @[Mux.scala:30:73] wire _issue_entry_T_4114 = _issue_entry_T_4113 | _issue_entry_T_4099; // @[Mux.scala:30:73] wire _issue_entry_T_4115 = _issue_entry_T_4114 | _issue_entry_T_4100; // @[Mux.scala:30:73] wire _issue_entry_T_4116 = _issue_entry_T_4115 | _issue_entry_T_4101; // @[Mux.scala:30:73] wire _issue_entry_T_4117 = _issue_entry_T_4116 | _issue_entry_T_4102; // @[Mux.scala:30:73] wire _issue_entry_T_4118 = _issue_entry_T_4117 | _issue_entry_T_4103; // @[Mux.scala:30:73] wire _issue_entry_T_4119 = _issue_entry_T_4118 | _issue_entry_T_4104; // @[Mux.scala:30:73] wire _issue_entry_T_4120 = _issue_entry_T_4119 | _issue_entry_T_4105; // @[Mux.scala:30:73] wire _issue_entry_T_4121 = _issue_entry_T_4120 | _issue_entry_T_4106; // @[Mux.scala:30:73] wire _issue_entry_T_4122 = _issue_entry_T_4121 | _issue_entry_T_4107; // @[Mux.scala:30:73] wire _issue_entry_T_4123 = _issue_entry_T_4122 | _issue_entry_T_4108; // @[Mux.scala:30:73] wire _issue_entry_T_4124 = _issue_entry_T_4123 | _issue_entry_T_4109; // @[Mux.scala:30:73] wire _issue_entry_T_4125 = _issue_entry_T_4124 | _issue_entry_T_4110; // @[Mux.scala:30:73] wire _issue_entry_T_4126 = _issue_entry_T_4125 | _issue_entry_T_4111; // @[Mux.scala:30:73] assign _issue_entry_WIRE_226 = _issue_entry_T_4126; // @[Mux.scala:30:73] assign _issue_entry_WIRE_223_xs2 = _issue_entry_WIRE_226; // @[Mux.scala:30:73] wire _issue_entry_T_4127 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30] wire _issue_entry_T_4128 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30] wire _issue_entry_T_4129 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30] wire _issue_entry_T_4130 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30] wire _issue_entry_T_4131 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30] wire _issue_entry_T_4132 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30] wire _issue_entry_T_4133 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30] wire _issue_entry_T_4134 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30] wire _issue_entry_T_4135 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30] wire _issue_entry_T_4136 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30] wire _issue_entry_T_4137 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30] wire _issue_entry_T_4138 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30] wire _issue_entry_T_4139 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30] wire _issue_entry_T_4140 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30] wire _issue_entry_T_4141 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30] wire _issue_entry_T_4142 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30] wire _issue_entry_T_4143 = _issue_entry_T_4127 | _issue_entry_T_4128; // @[Mux.scala:30:73] wire _issue_entry_T_4144 = _issue_entry_T_4143 | _issue_entry_T_4129; // @[Mux.scala:30:73] wire _issue_entry_T_4145 = _issue_entry_T_4144 | _issue_entry_T_4130; // @[Mux.scala:30:73] wire _issue_entry_T_4146 = _issue_entry_T_4145 | _issue_entry_T_4131; // @[Mux.scala:30:73] wire _issue_entry_T_4147 = _issue_entry_T_4146 | _issue_entry_T_4132; // @[Mux.scala:30:73] wire _issue_entry_T_4148 = _issue_entry_T_4147 | _issue_entry_T_4133; // @[Mux.scala:30:73] wire _issue_entry_T_4149 = _issue_entry_T_4148 | _issue_entry_T_4134; // @[Mux.scala:30:73] wire _issue_entry_T_4150 = _issue_entry_T_4149 | _issue_entry_T_4135; // @[Mux.scala:30:73] wire _issue_entry_T_4151 = _issue_entry_T_4150 | _issue_entry_T_4136; // @[Mux.scala:30:73] wire _issue_entry_T_4152 = _issue_entry_T_4151 | _issue_entry_T_4137; // @[Mux.scala:30:73] wire _issue_entry_T_4153 = _issue_entry_T_4152 | _issue_entry_T_4138; // @[Mux.scala:30:73] wire _issue_entry_T_4154 = _issue_entry_T_4153 | _issue_entry_T_4139; // @[Mux.scala:30:73] wire _issue_entry_T_4155 = _issue_entry_T_4154 | _issue_entry_T_4140; // @[Mux.scala:30:73] wire _issue_entry_T_4156 = _issue_entry_T_4155 | _issue_entry_T_4141; // @[Mux.scala:30:73] wire _issue_entry_T_4157 = _issue_entry_T_4156 | _issue_entry_T_4142; // @[Mux.scala:30:73] assign _issue_entry_WIRE_227 = _issue_entry_T_4157; // @[Mux.scala:30:73] assign _issue_entry_WIRE_223_xs1 = _issue_entry_WIRE_227; // @[Mux.scala:30:73] wire _issue_entry_T_4158 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30] wire _issue_entry_T_4159 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30] wire _issue_entry_T_4160 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30] wire _issue_entry_T_4161 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30] wire _issue_entry_T_4162 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30] wire _issue_entry_T_4163 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30] wire _issue_entry_T_4164 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30] wire _issue_entry_T_4165 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30] wire _issue_entry_T_4166 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30] wire _issue_entry_T_4167 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30] wire _issue_entry_T_4168 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30] wire _issue_entry_T_4169 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30] wire _issue_entry_T_4170 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30] wire _issue_entry_T_4171 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30] wire _issue_entry_T_4172 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30] wire _issue_entry_T_4173 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30] wire _issue_entry_T_4174 = _issue_entry_T_4158 | _issue_entry_T_4159; // @[Mux.scala:30:73] wire _issue_entry_T_4175 = _issue_entry_T_4174 | _issue_entry_T_4160; // @[Mux.scala:30:73] wire _issue_entry_T_4176 = _issue_entry_T_4175 | _issue_entry_T_4161; // @[Mux.scala:30:73] wire _issue_entry_T_4177 = _issue_entry_T_4176 | _issue_entry_T_4162; // @[Mux.scala:30:73] wire _issue_entry_T_4178 = _issue_entry_T_4177 | _issue_entry_T_4163; // @[Mux.scala:30:73] wire _issue_entry_T_4179 = _issue_entry_T_4178 | _issue_entry_T_4164; // @[Mux.scala:30:73] wire _issue_entry_T_4180 = _issue_entry_T_4179 | _issue_entry_T_4165; // @[Mux.scala:30:73] wire _issue_entry_T_4181 = _issue_entry_T_4180 | _issue_entry_T_4166; // @[Mux.scala:30:73] wire _issue_entry_T_4182 = _issue_entry_T_4181 | _issue_entry_T_4167; // @[Mux.scala:30:73] wire _issue_entry_T_4183 = _issue_entry_T_4182 | _issue_entry_T_4168; // @[Mux.scala:30:73] wire _issue_entry_T_4184 = _issue_entry_T_4183 | _issue_entry_T_4169; // @[Mux.scala:30:73] wire _issue_entry_T_4185 = _issue_entry_T_4184 | _issue_entry_T_4170; // @[Mux.scala:30:73] wire _issue_entry_T_4186 = _issue_entry_T_4185 | _issue_entry_T_4171; // @[Mux.scala:30:73] wire _issue_entry_T_4187 = _issue_entry_T_4186 | _issue_entry_T_4172; // @[Mux.scala:30:73] wire _issue_entry_T_4188 = _issue_entry_T_4187 | _issue_entry_T_4173; // @[Mux.scala:30:73] assign _issue_entry_WIRE_228 = _issue_entry_T_4188; // @[Mux.scala:30:73] assign _issue_entry_WIRE_223_xd = _issue_entry_WIRE_228; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_4189 = issue_sel_0_1 ? entries_ex_0_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_4190 = issue_sel_1_1 ? entries_ex_1_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_4191 = issue_sel_2_1 ? entries_ex_2_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_4192 = issue_sel_3_1 ? entries_ex_3_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_4193 = issue_sel_4_1 ? entries_ex_4_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_4194 = issue_sel_5_1 ? entries_ex_5_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_4195 = issue_sel_6_1 ? entries_ex_6_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_4196 = issue_sel_7_1 ? entries_ex_7_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_4197 = issue_sel_8 ? entries_ex_8_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_4198 = issue_sel_9 ? entries_ex_9_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_4199 = issue_sel_10 ? entries_ex_10_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_4200 = issue_sel_11 ? entries_ex_11_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_4201 = issue_sel_12 ? entries_ex_12_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_4202 = issue_sel_13 ? entries_ex_13_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_4203 = issue_sel_14 ? entries_ex_14_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_4204 = issue_sel_15 ? entries_ex_15_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_4205 = _issue_entry_T_4189 | _issue_entry_T_4190; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_4206 = _issue_entry_T_4205 | _issue_entry_T_4191; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_4207 = _issue_entry_T_4206 | _issue_entry_T_4192; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_4208 = _issue_entry_T_4207 | _issue_entry_T_4193; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_4209 = _issue_entry_T_4208 | _issue_entry_T_4194; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_4210 = _issue_entry_T_4209 | _issue_entry_T_4195; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_4211 = _issue_entry_T_4210 | _issue_entry_T_4196; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_4212 = _issue_entry_T_4211 | _issue_entry_T_4197; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_4213 = _issue_entry_T_4212 | _issue_entry_T_4198; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_4214 = _issue_entry_T_4213 | _issue_entry_T_4199; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_4215 = _issue_entry_T_4214 | _issue_entry_T_4200; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_4216 = _issue_entry_T_4215 | _issue_entry_T_4201; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_4217 = _issue_entry_T_4216 | _issue_entry_T_4202; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_4218 = _issue_entry_T_4217 | _issue_entry_T_4203; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_4219 = _issue_entry_T_4218 | _issue_entry_T_4204; // @[Mux.scala:30:73] assign _issue_entry_WIRE_229 = _issue_entry_T_4219; // @[Mux.scala:30:73] assign _issue_entry_WIRE_223_rs1 = _issue_entry_WIRE_229; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_4220 = issue_sel_0_1 ? entries_ex_0_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_4221 = issue_sel_1_1 ? entries_ex_1_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_4222 = issue_sel_2_1 ? entries_ex_2_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_4223 = issue_sel_3_1 ? entries_ex_3_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_4224 = issue_sel_4_1 ? entries_ex_4_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_4225 = issue_sel_5_1 ? entries_ex_5_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_4226 = issue_sel_6_1 ? entries_ex_6_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_4227 = issue_sel_7_1 ? entries_ex_7_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_4228 = issue_sel_8 ? entries_ex_8_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_4229 = issue_sel_9 ? entries_ex_9_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_4230 = issue_sel_10 ? entries_ex_10_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_4231 = issue_sel_11 ? entries_ex_11_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_4232 = issue_sel_12 ? entries_ex_12_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_4233 = issue_sel_13 ? entries_ex_13_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_4234 = issue_sel_14 ? entries_ex_14_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_4235 = issue_sel_15 ? entries_ex_15_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_4236 = _issue_entry_T_4220 | _issue_entry_T_4221; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_4237 = _issue_entry_T_4236 | _issue_entry_T_4222; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_4238 = _issue_entry_T_4237 | _issue_entry_T_4223; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_4239 = _issue_entry_T_4238 | _issue_entry_T_4224; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_4240 = _issue_entry_T_4239 | _issue_entry_T_4225; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_4241 = _issue_entry_T_4240 | _issue_entry_T_4226; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_4242 = _issue_entry_T_4241 | _issue_entry_T_4227; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_4243 = _issue_entry_T_4242 | _issue_entry_T_4228; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_4244 = _issue_entry_T_4243 | _issue_entry_T_4229; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_4245 = _issue_entry_T_4244 | _issue_entry_T_4230; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_4246 = _issue_entry_T_4245 | _issue_entry_T_4231; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_4247 = _issue_entry_T_4246 | _issue_entry_T_4232; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_4248 = _issue_entry_T_4247 | _issue_entry_T_4233; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_4249 = _issue_entry_T_4248 | _issue_entry_T_4234; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_4250 = _issue_entry_T_4249 | _issue_entry_T_4235; // @[Mux.scala:30:73] assign _issue_entry_WIRE_230 = _issue_entry_T_4250; // @[Mux.scala:30:73] assign _issue_entry_WIRE_223_rs2 = _issue_entry_WIRE_230; // @[Mux.scala:30:73] wire [6:0] _issue_entry_T_4251 = issue_sel_0_1 ? entries_ex_0_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_4252 = issue_sel_1_1 ? entries_ex_1_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_4253 = issue_sel_2_1 ? entries_ex_2_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_4254 = issue_sel_3_1 ? entries_ex_3_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_4255 = issue_sel_4_1 ? entries_ex_4_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_4256 = issue_sel_5_1 ? entries_ex_5_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_4257 = issue_sel_6_1 ? entries_ex_6_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_4258 = issue_sel_7_1 ? entries_ex_7_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_4259 = issue_sel_8 ? entries_ex_8_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_4260 = issue_sel_9 ? entries_ex_9_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_4261 = issue_sel_10 ? entries_ex_10_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_4262 = issue_sel_11 ? entries_ex_11_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_4263 = issue_sel_12 ? entries_ex_12_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_4264 = issue_sel_13 ? entries_ex_13_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_4265 = issue_sel_14 ? entries_ex_14_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_4266 = issue_sel_15 ? entries_ex_15_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_4267 = _issue_entry_T_4251 | _issue_entry_T_4252; // @[Mux.scala:30:73] wire [6:0] _issue_entry_T_4268 = _issue_entry_T_4267 | _issue_entry_T_4253; // @[Mux.scala:30:73] wire [6:0] _issue_entry_T_4269 = _issue_entry_T_4268 | _issue_entry_T_4254; // @[Mux.scala:30:73] wire [6:0] _issue_entry_T_4270 = _issue_entry_T_4269 | _issue_entry_T_4255; // @[Mux.scala:30:73] wire [6:0] _issue_entry_T_4271 = _issue_entry_T_4270 | _issue_entry_T_4256; // @[Mux.scala:30:73] wire [6:0] _issue_entry_T_4272 = _issue_entry_T_4271 | _issue_entry_T_4257; // @[Mux.scala:30:73] wire [6:0] _issue_entry_T_4273 = _issue_entry_T_4272 | _issue_entry_T_4258; // @[Mux.scala:30:73] wire [6:0] _issue_entry_T_4274 = _issue_entry_T_4273 | _issue_entry_T_4259; // @[Mux.scala:30:73] wire [6:0] _issue_entry_T_4275 = _issue_entry_T_4274 | _issue_entry_T_4260; // @[Mux.scala:30:73] wire [6:0] _issue_entry_T_4276 = _issue_entry_T_4275 | _issue_entry_T_4261; // @[Mux.scala:30:73] wire [6:0] _issue_entry_T_4277 = _issue_entry_T_4276 | _issue_entry_T_4262; // @[Mux.scala:30:73] wire [6:0] _issue_entry_T_4278 = _issue_entry_T_4277 | _issue_entry_T_4263; // @[Mux.scala:30:73] wire [6:0] _issue_entry_T_4279 = _issue_entry_T_4278 | _issue_entry_T_4264; // @[Mux.scala:30:73] wire [6:0] _issue_entry_T_4280 = _issue_entry_T_4279 | _issue_entry_T_4265; // @[Mux.scala:30:73] wire [6:0] _issue_entry_T_4281 = _issue_entry_T_4280 | _issue_entry_T_4266; // @[Mux.scala:30:73] assign _issue_entry_WIRE_231 = _issue_entry_T_4281; // @[Mux.scala:30:73] assign _issue_entry_WIRE_223_funct = _issue_entry_WIRE_231; // @[Mux.scala:30:73] wire _issue_entry_T_4282 = issue_sel_0_1 & entries_ex_0_bits_complete_on_issue; // @[OneHot.scala:83:30] wire _issue_entry_T_4283 = issue_sel_1_1 & entries_ex_1_bits_complete_on_issue; // @[OneHot.scala:83:30] wire _issue_entry_T_4284 = issue_sel_2_1 & entries_ex_2_bits_complete_on_issue; // @[OneHot.scala:83:30] wire _issue_entry_T_4285 = issue_sel_3_1 & entries_ex_3_bits_complete_on_issue; // @[OneHot.scala:83:30] wire _issue_entry_T_4286 = issue_sel_4_1 & entries_ex_4_bits_complete_on_issue; // @[OneHot.scala:83:30] wire _issue_entry_T_4287 = issue_sel_5_1 & entries_ex_5_bits_complete_on_issue; // @[OneHot.scala:83:30] wire _issue_entry_T_4288 = issue_sel_6_1 & entries_ex_6_bits_complete_on_issue; // @[OneHot.scala:83:30] wire _issue_entry_T_4289 = issue_sel_7_1 & entries_ex_7_bits_complete_on_issue; // @[OneHot.scala:83:30] wire _issue_entry_T_4290 = issue_sel_8 & entries_ex_8_bits_complete_on_issue; // @[OneHot.scala:83:30] wire _issue_entry_T_4291 = issue_sel_9 & entries_ex_9_bits_complete_on_issue; // @[OneHot.scala:83:30] wire _issue_entry_T_4292 = issue_sel_10 & entries_ex_10_bits_complete_on_issue; // @[OneHot.scala:83:30] wire _issue_entry_T_4293 = issue_sel_11 & entries_ex_11_bits_complete_on_issue; // @[OneHot.scala:83:30] wire _issue_entry_T_4294 = issue_sel_12 & entries_ex_12_bits_complete_on_issue; // @[OneHot.scala:83:30] wire _issue_entry_T_4295 = issue_sel_13 & entries_ex_13_bits_complete_on_issue; // @[OneHot.scala:83:30] wire _issue_entry_T_4296 = issue_sel_14 & entries_ex_14_bits_complete_on_issue; // @[OneHot.scala:83:30] wire _issue_entry_T_4297 = issue_sel_15 & entries_ex_15_bits_complete_on_issue; // @[OneHot.scala:83:30] wire _issue_entry_T_4298 = _issue_entry_T_4282 | _issue_entry_T_4283; // @[Mux.scala:30:73] wire _issue_entry_T_4299 = _issue_entry_T_4298 | _issue_entry_T_4284; // @[Mux.scala:30:73] wire _issue_entry_T_4300 = _issue_entry_T_4299 | _issue_entry_T_4285; // @[Mux.scala:30:73] wire _issue_entry_T_4301 = _issue_entry_T_4300 | _issue_entry_T_4286; // @[Mux.scala:30:73] wire _issue_entry_T_4302 = _issue_entry_T_4301 | _issue_entry_T_4287; // @[Mux.scala:30:73] wire _issue_entry_T_4303 = _issue_entry_T_4302 | _issue_entry_T_4288; // @[Mux.scala:30:73] wire _issue_entry_T_4304 = _issue_entry_T_4303 | _issue_entry_T_4289; // @[Mux.scala:30:73] wire _issue_entry_T_4305 = _issue_entry_T_4304 | _issue_entry_T_4290; // @[Mux.scala:30:73] wire _issue_entry_T_4306 = _issue_entry_T_4305 | _issue_entry_T_4291; // @[Mux.scala:30:73] wire _issue_entry_T_4307 = _issue_entry_T_4306 | _issue_entry_T_4292; // @[Mux.scala:30:73] wire _issue_entry_T_4308 = _issue_entry_T_4307 | _issue_entry_T_4293; // @[Mux.scala:30:73] wire _issue_entry_T_4309 = _issue_entry_T_4308 | _issue_entry_T_4294; // @[Mux.scala:30:73] wire _issue_entry_T_4310 = _issue_entry_T_4309 | _issue_entry_T_4295; // @[Mux.scala:30:73] wire _issue_entry_T_4311 = _issue_entry_T_4310 | _issue_entry_T_4296; // @[Mux.scala:30:73] wire _issue_entry_T_4312 = _issue_entry_T_4311 | _issue_entry_T_4297; // @[Mux.scala:30:73] assign _issue_entry_WIRE_232 = _issue_entry_T_4312; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_complete_on_issue = _issue_entry_WIRE_232; // @[Mux.scala:30:73] wire _issue_entry_T_4313 = issue_sel_0_1 & entries_ex_0_bits_issued; // @[OneHot.scala:83:30] wire _issue_entry_T_4314 = issue_sel_1_1 & entries_ex_1_bits_issued; // @[OneHot.scala:83:30] wire _issue_entry_T_4315 = issue_sel_2_1 & entries_ex_2_bits_issued; // @[OneHot.scala:83:30] wire _issue_entry_T_4316 = issue_sel_3_1 & entries_ex_3_bits_issued; // @[OneHot.scala:83:30] wire _issue_entry_T_4317 = issue_sel_4_1 & entries_ex_4_bits_issued; // @[OneHot.scala:83:30] wire _issue_entry_T_4318 = issue_sel_5_1 & entries_ex_5_bits_issued; // @[OneHot.scala:83:30] wire _issue_entry_T_4319 = issue_sel_6_1 & entries_ex_6_bits_issued; // @[OneHot.scala:83:30] wire _issue_entry_T_4320 = issue_sel_7_1 & entries_ex_7_bits_issued; // @[OneHot.scala:83:30] wire _issue_entry_T_4321 = issue_sel_8 & entries_ex_8_bits_issued; // @[OneHot.scala:83:30] wire _issue_entry_T_4322 = issue_sel_9 & entries_ex_9_bits_issued; // @[OneHot.scala:83:30] wire _issue_entry_T_4323 = issue_sel_10 & entries_ex_10_bits_issued; // @[OneHot.scala:83:30] wire _issue_entry_T_4324 = issue_sel_11 & entries_ex_11_bits_issued; // @[OneHot.scala:83:30] wire _issue_entry_T_4325 = issue_sel_12 & entries_ex_12_bits_issued; // @[OneHot.scala:83:30] wire _issue_entry_T_4326 = issue_sel_13 & entries_ex_13_bits_issued; // @[OneHot.scala:83:30] wire _issue_entry_T_4327 = issue_sel_14 & entries_ex_14_bits_issued; // @[OneHot.scala:83:30] wire _issue_entry_T_4328 = issue_sel_15 & entries_ex_15_bits_issued; // @[OneHot.scala:83:30] wire _issue_entry_T_4329 = _issue_entry_T_4313 | _issue_entry_T_4314; // @[Mux.scala:30:73] wire _issue_entry_T_4330 = _issue_entry_T_4329 | _issue_entry_T_4315; // @[Mux.scala:30:73] wire _issue_entry_T_4331 = _issue_entry_T_4330 | _issue_entry_T_4316; // @[Mux.scala:30:73] wire _issue_entry_T_4332 = _issue_entry_T_4331 | _issue_entry_T_4317; // @[Mux.scala:30:73] wire _issue_entry_T_4333 = _issue_entry_T_4332 | _issue_entry_T_4318; // @[Mux.scala:30:73] wire _issue_entry_T_4334 = _issue_entry_T_4333 | _issue_entry_T_4319; // @[Mux.scala:30:73] wire _issue_entry_T_4335 = _issue_entry_T_4334 | _issue_entry_T_4320; // @[Mux.scala:30:73] wire _issue_entry_T_4336 = _issue_entry_T_4335 | _issue_entry_T_4321; // @[Mux.scala:30:73] wire _issue_entry_T_4337 = _issue_entry_T_4336 | _issue_entry_T_4322; // @[Mux.scala:30:73] wire _issue_entry_T_4338 = _issue_entry_T_4337 | _issue_entry_T_4323; // @[Mux.scala:30:73] wire _issue_entry_T_4339 = _issue_entry_T_4338 | _issue_entry_T_4324; // @[Mux.scala:30:73] wire _issue_entry_T_4340 = _issue_entry_T_4339 | _issue_entry_T_4325; // @[Mux.scala:30:73] wire _issue_entry_T_4341 = _issue_entry_T_4340 | _issue_entry_T_4326; // @[Mux.scala:30:73] wire _issue_entry_T_4342 = _issue_entry_T_4341 | _issue_entry_T_4327; // @[Mux.scala:30:73] wire _issue_entry_T_4343 = _issue_entry_T_4342 | _issue_entry_T_4328; // @[Mux.scala:30:73] assign _issue_entry_WIRE_233 = _issue_entry_T_4343; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_issued = _issue_entry_WIRE_233; // @[Mux.scala:30:73] wire _issue_entry_WIRE_257; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_opb_valid = _issue_entry_WIRE_234_valid; // @[Mux.scala:30:73] wire _issue_entry_WIRE_235_start_is_acc_addr; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_opb_bits_start_is_acc_addr = _issue_entry_WIRE_234_bits_start_is_acc_addr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_235_start_accumulate; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_opb_bits_start_accumulate = _issue_entry_WIRE_234_bits_start_accumulate; // @[Mux.scala:30:73] wire _issue_entry_WIRE_235_start_read_full_acc_row; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_opb_bits_start_read_full_acc_row = _issue_entry_WIRE_234_bits_start_read_full_acc_row; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_235_start_norm_cmd; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_opb_bits_start_norm_cmd = _issue_entry_WIRE_234_bits_start_norm_cmd; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_235_start_garbage; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_opb_bits_start_garbage = _issue_entry_WIRE_234_bits_start_garbage; // @[Mux.scala:30:73] wire _issue_entry_WIRE_235_start_garbage_bit; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_opb_bits_start_garbage_bit = _issue_entry_WIRE_234_bits_start_garbage_bit; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_235_start_data; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_opb_bits_start_data = _issue_entry_WIRE_234_bits_start_data; // @[Mux.scala:30:73] wire _issue_entry_WIRE_235_end_is_acc_addr; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_opb_bits_end_is_acc_addr = _issue_entry_WIRE_234_bits_end_is_acc_addr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_235_end_accumulate; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_opb_bits_end_accumulate = _issue_entry_WIRE_234_bits_end_accumulate; // @[Mux.scala:30:73] wire _issue_entry_WIRE_235_end_read_full_acc_row; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_opb_bits_end_read_full_acc_row = _issue_entry_WIRE_234_bits_end_read_full_acc_row; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_235_end_norm_cmd; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_opb_bits_end_norm_cmd = _issue_entry_WIRE_234_bits_end_norm_cmd; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_235_end_garbage; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_opb_bits_end_garbage = _issue_entry_WIRE_234_bits_end_garbage; // @[Mux.scala:30:73] wire _issue_entry_WIRE_235_end_garbage_bit; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_opb_bits_end_garbage_bit = _issue_entry_WIRE_234_bits_end_garbage_bit; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_235_end_data; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_opb_bits_end_data = _issue_entry_WIRE_234_bits_end_data; // @[Mux.scala:30:73] wire _issue_entry_WIRE_235_wraps_around; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_opb_bits_wraps_around = _issue_entry_WIRE_234_bits_wraps_around; // @[Mux.scala:30:73] wire _issue_entry_WIRE_247_is_acc_addr; // @[Mux.scala:30:73] assign _issue_entry_WIRE_234_bits_start_is_acc_addr = _issue_entry_WIRE_235_start_is_acc_addr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_247_accumulate; // @[Mux.scala:30:73] assign _issue_entry_WIRE_234_bits_start_accumulate = _issue_entry_WIRE_235_start_accumulate; // @[Mux.scala:30:73] wire _issue_entry_WIRE_247_read_full_acc_row; // @[Mux.scala:30:73] assign _issue_entry_WIRE_234_bits_start_read_full_acc_row = _issue_entry_WIRE_235_start_read_full_acc_row; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_247_norm_cmd; // @[Mux.scala:30:73] assign _issue_entry_WIRE_234_bits_start_norm_cmd = _issue_entry_WIRE_235_start_norm_cmd; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_247_garbage; // @[Mux.scala:30:73] assign _issue_entry_WIRE_234_bits_start_garbage = _issue_entry_WIRE_235_start_garbage; // @[Mux.scala:30:73] wire _issue_entry_WIRE_247_garbage_bit; // @[Mux.scala:30:73] assign _issue_entry_WIRE_234_bits_start_garbage_bit = _issue_entry_WIRE_235_start_garbage_bit; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_247_data; // @[Mux.scala:30:73] assign _issue_entry_WIRE_234_bits_start_data = _issue_entry_WIRE_235_start_data; // @[Mux.scala:30:73] wire _issue_entry_WIRE_237_is_acc_addr; // @[Mux.scala:30:73] assign _issue_entry_WIRE_234_bits_end_is_acc_addr = _issue_entry_WIRE_235_end_is_acc_addr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_237_accumulate; // @[Mux.scala:30:73] assign _issue_entry_WIRE_234_bits_end_accumulate = _issue_entry_WIRE_235_end_accumulate; // @[Mux.scala:30:73] wire _issue_entry_WIRE_237_read_full_acc_row; // @[Mux.scala:30:73] assign _issue_entry_WIRE_234_bits_end_read_full_acc_row = _issue_entry_WIRE_235_end_read_full_acc_row; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_237_norm_cmd; // @[Mux.scala:30:73] assign _issue_entry_WIRE_234_bits_end_norm_cmd = _issue_entry_WIRE_235_end_norm_cmd; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_237_garbage; // @[Mux.scala:30:73] assign _issue_entry_WIRE_234_bits_end_garbage = _issue_entry_WIRE_235_end_garbage; // @[Mux.scala:30:73] wire _issue_entry_WIRE_237_garbage_bit; // @[Mux.scala:30:73] assign _issue_entry_WIRE_234_bits_end_garbage_bit = _issue_entry_WIRE_235_end_garbage_bit; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_237_data; // @[Mux.scala:30:73] assign _issue_entry_WIRE_234_bits_end_data = _issue_entry_WIRE_235_end_data; // @[Mux.scala:30:73] wire _issue_entry_WIRE_236; // @[Mux.scala:30:73] assign _issue_entry_WIRE_234_bits_wraps_around = _issue_entry_WIRE_235_wraps_around; // @[Mux.scala:30:73] wire _issue_entry_T_4344 = issue_sel_0_1 & entries_ex_0_bits_opb_bits_wraps_around; // @[OneHot.scala:83:30] wire _issue_entry_T_4345 = issue_sel_1_1 & entries_ex_1_bits_opb_bits_wraps_around; // @[OneHot.scala:83:30] wire _issue_entry_T_4346 = issue_sel_2_1 & entries_ex_2_bits_opb_bits_wraps_around; // @[OneHot.scala:83:30] wire _issue_entry_T_4347 = issue_sel_3_1 & entries_ex_3_bits_opb_bits_wraps_around; // @[OneHot.scala:83:30] wire _issue_entry_T_4348 = issue_sel_4_1 & entries_ex_4_bits_opb_bits_wraps_around; // @[OneHot.scala:83:30] wire _issue_entry_T_4349 = issue_sel_5_1 & entries_ex_5_bits_opb_bits_wraps_around; // @[OneHot.scala:83:30] wire _issue_entry_T_4350 = issue_sel_6_1 & entries_ex_6_bits_opb_bits_wraps_around; // @[OneHot.scala:83:30] wire _issue_entry_T_4351 = issue_sel_7_1 & entries_ex_7_bits_opb_bits_wraps_around; // @[OneHot.scala:83:30] wire _issue_entry_T_4352 = issue_sel_8 & entries_ex_8_bits_opb_bits_wraps_around; // @[OneHot.scala:83:30] wire _issue_entry_T_4353 = issue_sel_9 & entries_ex_9_bits_opb_bits_wraps_around; // @[OneHot.scala:83:30] wire _issue_entry_T_4354 = issue_sel_10 & entries_ex_10_bits_opb_bits_wraps_around; // @[OneHot.scala:83:30] wire _issue_entry_T_4355 = issue_sel_11 & entries_ex_11_bits_opb_bits_wraps_around; // @[OneHot.scala:83:30] wire _issue_entry_T_4356 = issue_sel_12 & entries_ex_12_bits_opb_bits_wraps_around; // @[OneHot.scala:83:30] wire _issue_entry_T_4357 = issue_sel_13 & entries_ex_13_bits_opb_bits_wraps_around; // @[OneHot.scala:83:30] wire _issue_entry_T_4358 = issue_sel_14 & entries_ex_14_bits_opb_bits_wraps_around; // @[OneHot.scala:83:30] wire _issue_entry_T_4359 = issue_sel_15 & entries_ex_15_bits_opb_bits_wraps_around; // @[OneHot.scala:83:30] wire _issue_entry_T_4360 = _issue_entry_T_4344 | _issue_entry_T_4345; // @[Mux.scala:30:73] wire _issue_entry_T_4361 = _issue_entry_T_4360 | _issue_entry_T_4346; // @[Mux.scala:30:73] wire _issue_entry_T_4362 = _issue_entry_T_4361 | _issue_entry_T_4347; // @[Mux.scala:30:73] wire _issue_entry_T_4363 = _issue_entry_T_4362 | _issue_entry_T_4348; // @[Mux.scala:30:73] wire _issue_entry_T_4364 = _issue_entry_T_4363 | _issue_entry_T_4349; // @[Mux.scala:30:73] wire _issue_entry_T_4365 = _issue_entry_T_4364 | _issue_entry_T_4350; // @[Mux.scala:30:73] wire _issue_entry_T_4366 = _issue_entry_T_4365 | _issue_entry_T_4351; // @[Mux.scala:30:73] wire _issue_entry_T_4367 = _issue_entry_T_4366 | _issue_entry_T_4352; // @[Mux.scala:30:73] wire _issue_entry_T_4368 = _issue_entry_T_4367 | _issue_entry_T_4353; // @[Mux.scala:30:73] wire _issue_entry_T_4369 = _issue_entry_T_4368 | _issue_entry_T_4354; // @[Mux.scala:30:73] wire _issue_entry_T_4370 = _issue_entry_T_4369 | _issue_entry_T_4355; // @[Mux.scala:30:73] wire _issue_entry_T_4371 = _issue_entry_T_4370 | _issue_entry_T_4356; // @[Mux.scala:30:73] wire _issue_entry_T_4372 = _issue_entry_T_4371 | _issue_entry_T_4357; // @[Mux.scala:30:73] wire _issue_entry_T_4373 = _issue_entry_T_4372 | _issue_entry_T_4358; // @[Mux.scala:30:73] wire _issue_entry_T_4374 = _issue_entry_T_4373 | _issue_entry_T_4359; // @[Mux.scala:30:73] assign _issue_entry_WIRE_236 = _issue_entry_T_4374; // @[Mux.scala:30:73] assign _issue_entry_WIRE_235_wraps_around = _issue_entry_WIRE_236; // @[Mux.scala:30:73] wire _issue_entry_WIRE_246; // @[Mux.scala:30:73] assign _issue_entry_WIRE_235_end_is_acc_addr = _issue_entry_WIRE_237_is_acc_addr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_245; // @[Mux.scala:30:73] assign _issue_entry_WIRE_235_end_accumulate = _issue_entry_WIRE_237_accumulate; // @[Mux.scala:30:73] wire _issue_entry_WIRE_244; // @[Mux.scala:30:73] assign _issue_entry_WIRE_235_end_read_full_acc_row = _issue_entry_WIRE_237_read_full_acc_row; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_241; // @[Mux.scala:30:73] assign _issue_entry_WIRE_235_end_norm_cmd = _issue_entry_WIRE_237_norm_cmd; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_240; // @[Mux.scala:30:73] assign _issue_entry_WIRE_235_end_garbage = _issue_entry_WIRE_237_garbage; // @[Mux.scala:30:73] wire _issue_entry_WIRE_239; // @[Mux.scala:30:73] assign _issue_entry_WIRE_235_end_garbage_bit = _issue_entry_WIRE_237_garbage_bit; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_238; // @[Mux.scala:30:73] assign _issue_entry_WIRE_235_end_data = _issue_entry_WIRE_237_data; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_4375 = issue_sel_0_1 ? entries_ex_0_bits_opb_bits_end_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_4376 = issue_sel_1_1 ? entries_ex_1_bits_opb_bits_end_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_4377 = issue_sel_2_1 ? entries_ex_2_bits_opb_bits_end_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_4378 = issue_sel_3_1 ? entries_ex_3_bits_opb_bits_end_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_4379 = issue_sel_4_1 ? entries_ex_4_bits_opb_bits_end_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_4380 = issue_sel_5_1 ? entries_ex_5_bits_opb_bits_end_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_4381 = issue_sel_6_1 ? entries_ex_6_bits_opb_bits_end_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_4382 = issue_sel_7_1 ? entries_ex_7_bits_opb_bits_end_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_4383 = issue_sel_8 ? entries_ex_8_bits_opb_bits_end_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_4384 = issue_sel_9 ? entries_ex_9_bits_opb_bits_end_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_4385 = issue_sel_10 ? entries_ex_10_bits_opb_bits_end_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_4386 = issue_sel_11 ? entries_ex_11_bits_opb_bits_end_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_4387 = issue_sel_12 ? entries_ex_12_bits_opb_bits_end_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_4388 = issue_sel_13 ? entries_ex_13_bits_opb_bits_end_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_4389 = issue_sel_14 ? entries_ex_14_bits_opb_bits_end_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_4390 = issue_sel_15 ? entries_ex_15_bits_opb_bits_end_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_4391 = _issue_entry_T_4375 | _issue_entry_T_4376; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_4392 = _issue_entry_T_4391 | _issue_entry_T_4377; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_4393 = _issue_entry_T_4392 | _issue_entry_T_4378; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_4394 = _issue_entry_T_4393 | _issue_entry_T_4379; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_4395 = _issue_entry_T_4394 | _issue_entry_T_4380; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_4396 = _issue_entry_T_4395 | _issue_entry_T_4381; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_4397 = _issue_entry_T_4396 | _issue_entry_T_4382; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_4398 = _issue_entry_T_4397 | _issue_entry_T_4383; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_4399 = _issue_entry_T_4398 | _issue_entry_T_4384; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_4400 = _issue_entry_T_4399 | _issue_entry_T_4385; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_4401 = _issue_entry_T_4400 | _issue_entry_T_4386; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_4402 = _issue_entry_T_4401 | _issue_entry_T_4387; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_4403 = _issue_entry_T_4402 | _issue_entry_T_4388; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_4404 = _issue_entry_T_4403 | _issue_entry_T_4389; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_4405 = _issue_entry_T_4404 | _issue_entry_T_4390; // @[Mux.scala:30:73] assign _issue_entry_WIRE_238 = _issue_entry_T_4405; // @[Mux.scala:30:73] assign _issue_entry_WIRE_237_data = _issue_entry_WIRE_238; // @[Mux.scala:30:73] wire _issue_entry_T_4406 = issue_sel_0_1 & entries_ex_0_bits_opb_bits_end_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_4407 = issue_sel_1_1 & entries_ex_1_bits_opb_bits_end_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_4408 = issue_sel_2_1 & entries_ex_2_bits_opb_bits_end_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_4409 = issue_sel_3_1 & entries_ex_3_bits_opb_bits_end_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_4410 = issue_sel_4_1 & entries_ex_4_bits_opb_bits_end_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_4411 = issue_sel_5_1 & entries_ex_5_bits_opb_bits_end_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_4412 = issue_sel_6_1 & entries_ex_6_bits_opb_bits_end_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_4413 = issue_sel_7_1 & entries_ex_7_bits_opb_bits_end_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_4414 = issue_sel_8 & entries_ex_8_bits_opb_bits_end_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_4415 = issue_sel_9 & entries_ex_9_bits_opb_bits_end_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_4416 = issue_sel_10 & entries_ex_10_bits_opb_bits_end_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_4417 = issue_sel_11 & entries_ex_11_bits_opb_bits_end_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_4418 = issue_sel_12 & entries_ex_12_bits_opb_bits_end_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_4419 = issue_sel_13 & entries_ex_13_bits_opb_bits_end_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_4420 = issue_sel_14 & entries_ex_14_bits_opb_bits_end_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_4421 = issue_sel_15 & entries_ex_15_bits_opb_bits_end_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_4422 = _issue_entry_T_4406 | _issue_entry_T_4407; // @[Mux.scala:30:73] wire _issue_entry_T_4423 = _issue_entry_T_4422 | _issue_entry_T_4408; // @[Mux.scala:30:73] wire _issue_entry_T_4424 = _issue_entry_T_4423 | _issue_entry_T_4409; // @[Mux.scala:30:73] wire _issue_entry_T_4425 = _issue_entry_T_4424 | _issue_entry_T_4410; // @[Mux.scala:30:73] wire _issue_entry_T_4426 = _issue_entry_T_4425 | _issue_entry_T_4411; // @[Mux.scala:30:73] wire _issue_entry_T_4427 = _issue_entry_T_4426 | _issue_entry_T_4412; // @[Mux.scala:30:73] wire _issue_entry_T_4428 = _issue_entry_T_4427 | _issue_entry_T_4413; // @[Mux.scala:30:73] wire _issue_entry_T_4429 = _issue_entry_T_4428 | _issue_entry_T_4414; // @[Mux.scala:30:73] wire _issue_entry_T_4430 = _issue_entry_T_4429 | _issue_entry_T_4415; // @[Mux.scala:30:73] wire _issue_entry_T_4431 = _issue_entry_T_4430 | _issue_entry_T_4416; // @[Mux.scala:30:73] wire _issue_entry_T_4432 = _issue_entry_T_4431 | _issue_entry_T_4417; // @[Mux.scala:30:73] wire _issue_entry_T_4433 = _issue_entry_T_4432 | _issue_entry_T_4418; // @[Mux.scala:30:73] wire _issue_entry_T_4434 = _issue_entry_T_4433 | _issue_entry_T_4419; // @[Mux.scala:30:73] wire _issue_entry_T_4435 = _issue_entry_T_4434 | _issue_entry_T_4420; // @[Mux.scala:30:73] wire _issue_entry_T_4436 = _issue_entry_T_4435 | _issue_entry_T_4421; // @[Mux.scala:30:73] assign _issue_entry_WIRE_239 = _issue_entry_T_4436; // @[Mux.scala:30:73] assign _issue_entry_WIRE_237_garbage_bit = _issue_entry_WIRE_239; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_4437 = issue_sel_0_1 ? entries_ex_0_bits_opb_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_4438 = issue_sel_1_1 ? entries_ex_1_bits_opb_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_4439 = issue_sel_2_1 ? entries_ex_2_bits_opb_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_4440 = issue_sel_3_1 ? entries_ex_3_bits_opb_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_4441 = issue_sel_4_1 ? entries_ex_4_bits_opb_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_4442 = issue_sel_5_1 ? entries_ex_5_bits_opb_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_4443 = issue_sel_6_1 ? entries_ex_6_bits_opb_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_4444 = issue_sel_7_1 ? entries_ex_7_bits_opb_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_4445 = issue_sel_8 ? entries_ex_8_bits_opb_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_4446 = issue_sel_9 ? entries_ex_9_bits_opb_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_4447 = issue_sel_10 ? entries_ex_10_bits_opb_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_4448 = issue_sel_11 ? entries_ex_11_bits_opb_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_4449 = issue_sel_12 ? entries_ex_12_bits_opb_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_4450 = issue_sel_13 ? entries_ex_13_bits_opb_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_4451 = issue_sel_14 ? entries_ex_14_bits_opb_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_4452 = issue_sel_15 ? entries_ex_15_bits_opb_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_4453 = _issue_entry_T_4437 | _issue_entry_T_4438; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_4454 = _issue_entry_T_4453 | _issue_entry_T_4439; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_4455 = _issue_entry_T_4454 | _issue_entry_T_4440; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_4456 = _issue_entry_T_4455 | _issue_entry_T_4441; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_4457 = _issue_entry_T_4456 | _issue_entry_T_4442; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_4458 = _issue_entry_T_4457 | _issue_entry_T_4443; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_4459 = _issue_entry_T_4458 | _issue_entry_T_4444; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_4460 = _issue_entry_T_4459 | _issue_entry_T_4445; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_4461 = _issue_entry_T_4460 | _issue_entry_T_4446; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_4462 = _issue_entry_T_4461 | _issue_entry_T_4447; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_4463 = _issue_entry_T_4462 | _issue_entry_T_4448; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_4464 = _issue_entry_T_4463 | _issue_entry_T_4449; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_4465 = _issue_entry_T_4464 | _issue_entry_T_4450; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_4466 = _issue_entry_T_4465 | _issue_entry_T_4451; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_4467 = _issue_entry_T_4466 | _issue_entry_T_4452; // @[Mux.scala:30:73] assign _issue_entry_WIRE_240 = _issue_entry_T_4467; // @[Mux.scala:30:73] assign _issue_entry_WIRE_237_garbage = _issue_entry_WIRE_240; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_4469 = issue_sel_0_1 ? _issue_entry_T_4468 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_4471 = issue_sel_1_1 ? _issue_entry_T_4470 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_4473 = issue_sel_2_1 ? _issue_entry_T_4472 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_4475 = issue_sel_3_1 ? _issue_entry_T_4474 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_4477 = issue_sel_4_1 ? _issue_entry_T_4476 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_4479 = issue_sel_5_1 ? _issue_entry_T_4478 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_4481 = issue_sel_6_1 ? _issue_entry_T_4480 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_4483 = issue_sel_7_1 ? _issue_entry_T_4482 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_4485 = issue_sel_8 ? _issue_entry_T_4484 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_4487 = issue_sel_9 ? _issue_entry_T_4486 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_4489 = issue_sel_10 ? _issue_entry_T_4488 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_4491 = issue_sel_11 ? _issue_entry_T_4490 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_4493 = issue_sel_12 ? _issue_entry_T_4492 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_4495 = issue_sel_13 ? _issue_entry_T_4494 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_4497 = issue_sel_14 ? _issue_entry_T_4496 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_4499 = issue_sel_15 ? _issue_entry_T_4498 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_4500 = _issue_entry_T_4469 | _issue_entry_T_4471; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_4501 = _issue_entry_T_4500 | _issue_entry_T_4473; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_4502 = _issue_entry_T_4501 | _issue_entry_T_4475; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_4503 = _issue_entry_T_4502 | _issue_entry_T_4477; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_4504 = _issue_entry_T_4503 | _issue_entry_T_4479; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_4505 = _issue_entry_T_4504 | _issue_entry_T_4481; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_4506 = _issue_entry_T_4505 | _issue_entry_T_4483; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_4507 = _issue_entry_T_4506 | _issue_entry_T_4485; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_4508 = _issue_entry_T_4507 | _issue_entry_T_4487; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_4509 = _issue_entry_T_4508 | _issue_entry_T_4489; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_4510 = _issue_entry_T_4509 | _issue_entry_T_4491; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_4511 = _issue_entry_T_4510 | _issue_entry_T_4493; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_4512 = _issue_entry_T_4511 | _issue_entry_T_4495; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_4513 = _issue_entry_T_4512 | _issue_entry_T_4497; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_4514 = _issue_entry_T_4513 | _issue_entry_T_4499; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_242 = _issue_entry_T_4514; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_243; // @[Mux.scala:30:73] assign _issue_entry_WIRE_237_norm_cmd = _issue_entry_WIRE_241; // @[Mux.scala:30:73] assign _issue_entry_WIRE_243 = _issue_entry_WIRE_242; // @[Mux.scala:30:73] assign _issue_entry_WIRE_241 = _issue_entry_WIRE_243; // @[Mux.scala:30:73] wire _issue_entry_T_4515 = issue_sel_0_1 & entries_ex_0_bits_opb_bits_end_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_4516 = issue_sel_1_1 & entries_ex_1_bits_opb_bits_end_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_4517 = issue_sel_2_1 & entries_ex_2_bits_opb_bits_end_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_4518 = issue_sel_3_1 & entries_ex_3_bits_opb_bits_end_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_4519 = issue_sel_4_1 & entries_ex_4_bits_opb_bits_end_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_4520 = issue_sel_5_1 & entries_ex_5_bits_opb_bits_end_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_4521 = issue_sel_6_1 & entries_ex_6_bits_opb_bits_end_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_4522 = issue_sel_7_1 & entries_ex_7_bits_opb_bits_end_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_4523 = issue_sel_8 & entries_ex_8_bits_opb_bits_end_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_4524 = issue_sel_9 & entries_ex_9_bits_opb_bits_end_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_4525 = issue_sel_10 & entries_ex_10_bits_opb_bits_end_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_4526 = issue_sel_11 & entries_ex_11_bits_opb_bits_end_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_4527 = issue_sel_12 & entries_ex_12_bits_opb_bits_end_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_4528 = issue_sel_13 & entries_ex_13_bits_opb_bits_end_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_4529 = issue_sel_14 & entries_ex_14_bits_opb_bits_end_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_4530 = issue_sel_15 & entries_ex_15_bits_opb_bits_end_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_4531 = _issue_entry_T_4515 | _issue_entry_T_4516; // @[Mux.scala:30:73] wire _issue_entry_T_4532 = _issue_entry_T_4531 | _issue_entry_T_4517; // @[Mux.scala:30:73] wire _issue_entry_T_4533 = _issue_entry_T_4532 | _issue_entry_T_4518; // @[Mux.scala:30:73] wire _issue_entry_T_4534 = _issue_entry_T_4533 | _issue_entry_T_4519; // @[Mux.scala:30:73] wire _issue_entry_T_4535 = _issue_entry_T_4534 | _issue_entry_T_4520; // @[Mux.scala:30:73] wire _issue_entry_T_4536 = _issue_entry_T_4535 | _issue_entry_T_4521; // @[Mux.scala:30:73] wire _issue_entry_T_4537 = _issue_entry_T_4536 | _issue_entry_T_4522; // @[Mux.scala:30:73] wire _issue_entry_T_4538 = _issue_entry_T_4537 | _issue_entry_T_4523; // @[Mux.scala:30:73] wire _issue_entry_T_4539 = _issue_entry_T_4538 | _issue_entry_T_4524; // @[Mux.scala:30:73] wire _issue_entry_T_4540 = _issue_entry_T_4539 | _issue_entry_T_4525; // @[Mux.scala:30:73] wire _issue_entry_T_4541 = _issue_entry_T_4540 | _issue_entry_T_4526; // @[Mux.scala:30:73] wire _issue_entry_T_4542 = _issue_entry_T_4541 | _issue_entry_T_4527; // @[Mux.scala:30:73] wire _issue_entry_T_4543 = _issue_entry_T_4542 | _issue_entry_T_4528; // @[Mux.scala:30:73] wire _issue_entry_T_4544 = _issue_entry_T_4543 | _issue_entry_T_4529; // @[Mux.scala:30:73] wire _issue_entry_T_4545 = _issue_entry_T_4544 | _issue_entry_T_4530; // @[Mux.scala:30:73] assign _issue_entry_WIRE_244 = _issue_entry_T_4545; // @[Mux.scala:30:73] assign _issue_entry_WIRE_237_read_full_acc_row = _issue_entry_WIRE_244; // @[Mux.scala:30:73] wire _issue_entry_T_4546 = issue_sel_0_1 & entries_ex_0_bits_opb_bits_end_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_4547 = issue_sel_1_1 & entries_ex_1_bits_opb_bits_end_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_4548 = issue_sel_2_1 & entries_ex_2_bits_opb_bits_end_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_4549 = issue_sel_3_1 & entries_ex_3_bits_opb_bits_end_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_4550 = issue_sel_4_1 & entries_ex_4_bits_opb_bits_end_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_4551 = issue_sel_5_1 & entries_ex_5_bits_opb_bits_end_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_4552 = issue_sel_6_1 & entries_ex_6_bits_opb_bits_end_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_4553 = issue_sel_7_1 & entries_ex_7_bits_opb_bits_end_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_4554 = issue_sel_8 & entries_ex_8_bits_opb_bits_end_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_4555 = issue_sel_9 & entries_ex_9_bits_opb_bits_end_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_4556 = issue_sel_10 & entries_ex_10_bits_opb_bits_end_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_4557 = issue_sel_11 & entries_ex_11_bits_opb_bits_end_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_4558 = issue_sel_12 & entries_ex_12_bits_opb_bits_end_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_4559 = issue_sel_13 & entries_ex_13_bits_opb_bits_end_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_4560 = issue_sel_14 & entries_ex_14_bits_opb_bits_end_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_4561 = issue_sel_15 & entries_ex_15_bits_opb_bits_end_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_4562 = _issue_entry_T_4546 | _issue_entry_T_4547; // @[Mux.scala:30:73] wire _issue_entry_T_4563 = _issue_entry_T_4562 | _issue_entry_T_4548; // @[Mux.scala:30:73] wire _issue_entry_T_4564 = _issue_entry_T_4563 | _issue_entry_T_4549; // @[Mux.scala:30:73] wire _issue_entry_T_4565 = _issue_entry_T_4564 | _issue_entry_T_4550; // @[Mux.scala:30:73] wire _issue_entry_T_4566 = _issue_entry_T_4565 | _issue_entry_T_4551; // @[Mux.scala:30:73] wire _issue_entry_T_4567 = _issue_entry_T_4566 | _issue_entry_T_4552; // @[Mux.scala:30:73] wire _issue_entry_T_4568 = _issue_entry_T_4567 | _issue_entry_T_4553; // @[Mux.scala:30:73] wire _issue_entry_T_4569 = _issue_entry_T_4568 | _issue_entry_T_4554; // @[Mux.scala:30:73] wire _issue_entry_T_4570 = _issue_entry_T_4569 | _issue_entry_T_4555; // @[Mux.scala:30:73] wire _issue_entry_T_4571 = _issue_entry_T_4570 | _issue_entry_T_4556; // @[Mux.scala:30:73] wire _issue_entry_T_4572 = _issue_entry_T_4571 | _issue_entry_T_4557; // @[Mux.scala:30:73] wire _issue_entry_T_4573 = _issue_entry_T_4572 | _issue_entry_T_4558; // @[Mux.scala:30:73] wire _issue_entry_T_4574 = _issue_entry_T_4573 | _issue_entry_T_4559; // @[Mux.scala:30:73] wire _issue_entry_T_4575 = _issue_entry_T_4574 | _issue_entry_T_4560; // @[Mux.scala:30:73] wire _issue_entry_T_4576 = _issue_entry_T_4575 | _issue_entry_T_4561; // @[Mux.scala:30:73] assign _issue_entry_WIRE_245 = _issue_entry_T_4576; // @[Mux.scala:30:73] assign _issue_entry_WIRE_237_accumulate = _issue_entry_WIRE_245; // @[Mux.scala:30:73] wire _issue_entry_T_4577 = issue_sel_0_1 & entries_ex_0_bits_opb_bits_end_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_4578 = issue_sel_1_1 & entries_ex_1_bits_opb_bits_end_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_4579 = issue_sel_2_1 & entries_ex_2_bits_opb_bits_end_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_4580 = issue_sel_3_1 & entries_ex_3_bits_opb_bits_end_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_4581 = issue_sel_4_1 & entries_ex_4_bits_opb_bits_end_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_4582 = issue_sel_5_1 & entries_ex_5_bits_opb_bits_end_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_4583 = issue_sel_6_1 & entries_ex_6_bits_opb_bits_end_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_4584 = issue_sel_7_1 & entries_ex_7_bits_opb_bits_end_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_4585 = issue_sel_8 & entries_ex_8_bits_opb_bits_end_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_4586 = issue_sel_9 & entries_ex_9_bits_opb_bits_end_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_4587 = issue_sel_10 & entries_ex_10_bits_opb_bits_end_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_4588 = issue_sel_11 & entries_ex_11_bits_opb_bits_end_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_4589 = issue_sel_12 & entries_ex_12_bits_opb_bits_end_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_4590 = issue_sel_13 & entries_ex_13_bits_opb_bits_end_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_4591 = issue_sel_14 & entries_ex_14_bits_opb_bits_end_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_4592 = issue_sel_15 & entries_ex_15_bits_opb_bits_end_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_4593 = _issue_entry_T_4577 | _issue_entry_T_4578; // @[Mux.scala:30:73] wire _issue_entry_T_4594 = _issue_entry_T_4593 | _issue_entry_T_4579; // @[Mux.scala:30:73] wire _issue_entry_T_4595 = _issue_entry_T_4594 | _issue_entry_T_4580; // @[Mux.scala:30:73] wire _issue_entry_T_4596 = _issue_entry_T_4595 | _issue_entry_T_4581; // @[Mux.scala:30:73] wire _issue_entry_T_4597 = _issue_entry_T_4596 | _issue_entry_T_4582; // @[Mux.scala:30:73] wire _issue_entry_T_4598 = _issue_entry_T_4597 | _issue_entry_T_4583; // @[Mux.scala:30:73] wire _issue_entry_T_4599 = _issue_entry_T_4598 | _issue_entry_T_4584; // @[Mux.scala:30:73] wire _issue_entry_T_4600 = _issue_entry_T_4599 | _issue_entry_T_4585; // @[Mux.scala:30:73] wire _issue_entry_T_4601 = _issue_entry_T_4600 | _issue_entry_T_4586; // @[Mux.scala:30:73] wire _issue_entry_T_4602 = _issue_entry_T_4601 | _issue_entry_T_4587; // @[Mux.scala:30:73] wire _issue_entry_T_4603 = _issue_entry_T_4602 | _issue_entry_T_4588; // @[Mux.scala:30:73] wire _issue_entry_T_4604 = _issue_entry_T_4603 | _issue_entry_T_4589; // @[Mux.scala:30:73] wire _issue_entry_T_4605 = _issue_entry_T_4604 | _issue_entry_T_4590; // @[Mux.scala:30:73] wire _issue_entry_T_4606 = _issue_entry_T_4605 | _issue_entry_T_4591; // @[Mux.scala:30:73] wire _issue_entry_T_4607 = _issue_entry_T_4606 | _issue_entry_T_4592; // @[Mux.scala:30:73] assign _issue_entry_WIRE_246 = _issue_entry_T_4607; // @[Mux.scala:30:73] assign _issue_entry_WIRE_237_is_acc_addr = _issue_entry_WIRE_246; // @[Mux.scala:30:73] wire _issue_entry_WIRE_256; // @[Mux.scala:30:73] assign _issue_entry_WIRE_235_start_is_acc_addr = _issue_entry_WIRE_247_is_acc_addr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_255; // @[Mux.scala:30:73] assign _issue_entry_WIRE_235_start_accumulate = _issue_entry_WIRE_247_accumulate; // @[Mux.scala:30:73] wire _issue_entry_WIRE_254; // @[Mux.scala:30:73] assign _issue_entry_WIRE_235_start_read_full_acc_row = _issue_entry_WIRE_247_read_full_acc_row; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_251; // @[Mux.scala:30:73] assign _issue_entry_WIRE_235_start_norm_cmd = _issue_entry_WIRE_247_norm_cmd; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_250; // @[Mux.scala:30:73] assign _issue_entry_WIRE_235_start_garbage = _issue_entry_WIRE_247_garbage; // @[Mux.scala:30:73] wire _issue_entry_WIRE_249; // @[Mux.scala:30:73] assign _issue_entry_WIRE_235_start_garbage_bit = _issue_entry_WIRE_247_garbage_bit; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_248; // @[Mux.scala:30:73] assign _issue_entry_WIRE_235_start_data = _issue_entry_WIRE_247_data; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_4608 = issue_sel_0_1 ? entries_ex_0_bits_opb_bits_start_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_4609 = issue_sel_1_1 ? entries_ex_1_bits_opb_bits_start_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_4610 = issue_sel_2_1 ? entries_ex_2_bits_opb_bits_start_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_4611 = issue_sel_3_1 ? entries_ex_3_bits_opb_bits_start_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_4612 = issue_sel_4_1 ? entries_ex_4_bits_opb_bits_start_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_4613 = issue_sel_5_1 ? entries_ex_5_bits_opb_bits_start_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_4614 = issue_sel_6_1 ? entries_ex_6_bits_opb_bits_start_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_4615 = issue_sel_7_1 ? entries_ex_7_bits_opb_bits_start_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_4616 = issue_sel_8 ? entries_ex_8_bits_opb_bits_start_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_4617 = issue_sel_9 ? entries_ex_9_bits_opb_bits_start_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_4618 = issue_sel_10 ? entries_ex_10_bits_opb_bits_start_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_4619 = issue_sel_11 ? entries_ex_11_bits_opb_bits_start_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_4620 = issue_sel_12 ? entries_ex_12_bits_opb_bits_start_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_4621 = issue_sel_13 ? entries_ex_13_bits_opb_bits_start_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_4622 = issue_sel_14 ? entries_ex_14_bits_opb_bits_start_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_4623 = issue_sel_15 ? entries_ex_15_bits_opb_bits_start_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_4624 = _issue_entry_T_4608 | _issue_entry_T_4609; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_4625 = _issue_entry_T_4624 | _issue_entry_T_4610; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_4626 = _issue_entry_T_4625 | _issue_entry_T_4611; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_4627 = _issue_entry_T_4626 | _issue_entry_T_4612; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_4628 = _issue_entry_T_4627 | _issue_entry_T_4613; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_4629 = _issue_entry_T_4628 | _issue_entry_T_4614; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_4630 = _issue_entry_T_4629 | _issue_entry_T_4615; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_4631 = _issue_entry_T_4630 | _issue_entry_T_4616; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_4632 = _issue_entry_T_4631 | _issue_entry_T_4617; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_4633 = _issue_entry_T_4632 | _issue_entry_T_4618; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_4634 = _issue_entry_T_4633 | _issue_entry_T_4619; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_4635 = _issue_entry_T_4634 | _issue_entry_T_4620; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_4636 = _issue_entry_T_4635 | _issue_entry_T_4621; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_4637 = _issue_entry_T_4636 | _issue_entry_T_4622; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_4638 = _issue_entry_T_4637 | _issue_entry_T_4623; // @[Mux.scala:30:73] assign _issue_entry_WIRE_248 = _issue_entry_T_4638; // @[Mux.scala:30:73] assign _issue_entry_WIRE_247_data = _issue_entry_WIRE_248; // @[Mux.scala:30:73] wire _issue_entry_T_4639 = issue_sel_0_1 & entries_ex_0_bits_opb_bits_start_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_4640 = issue_sel_1_1 & entries_ex_1_bits_opb_bits_start_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_4641 = issue_sel_2_1 & entries_ex_2_bits_opb_bits_start_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_4642 = issue_sel_3_1 & entries_ex_3_bits_opb_bits_start_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_4643 = issue_sel_4_1 & entries_ex_4_bits_opb_bits_start_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_4644 = issue_sel_5_1 & entries_ex_5_bits_opb_bits_start_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_4645 = issue_sel_6_1 & entries_ex_6_bits_opb_bits_start_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_4646 = issue_sel_7_1 & entries_ex_7_bits_opb_bits_start_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_4647 = issue_sel_8 & entries_ex_8_bits_opb_bits_start_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_4648 = issue_sel_9 & entries_ex_9_bits_opb_bits_start_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_4649 = issue_sel_10 & entries_ex_10_bits_opb_bits_start_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_4650 = issue_sel_11 & entries_ex_11_bits_opb_bits_start_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_4651 = issue_sel_12 & entries_ex_12_bits_opb_bits_start_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_4652 = issue_sel_13 & entries_ex_13_bits_opb_bits_start_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_4653 = issue_sel_14 & entries_ex_14_bits_opb_bits_start_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_4654 = issue_sel_15 & entries_ex_15_bits_opb_bits_start_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_4655 = _issue_entry_T_4639 | _issue_entry_T_4640; // @[Mux.scala:30:73] wire _issue_entry_T_4656 = _issue_entry_T_4655 | _issue_entry_T_4641; // @[Mux.scala:30:73] wire _issue_entry_T_4657 = _issue_entry_T_4656 | _issue_entry_T_4642; // @[Mux.scala:30:73] wire _issue_entry_T_4658 = _issue_entry_T_4657 | _issue_entry_T_4643; // @[Mux.scala:30:73] wire _issue_entry_T_4659 = _issue_entry_T_4658 | _issue_entry_T_4644; // @[Mux.scala:30:73] wire _issue_entry_T_4660 = _issue_entry_T_4659 | _issue_entry_T_4645; // @[Mux.scala:30:73] wire _issue_entry_T_4661 = _issue_entry_T_4660 | _issue_entry_T_4646; // @[Mux.scala:30:73] wire _issue_entry_T_4662 = _issue_entry_T_4661 | _issue_entry_T_4647; // @[Mux.scala:30:73] wire _issue_entry_T_4663 = _issue_entry_T_4662 | _issue_entry_T_4648; // @[Mux.scala:30:73] wire _issue_entry_T_4664 = _issue_entry_T_4663 | _issue_entry_T_4649; // @[Mux.scala:30:73] wire _issue_entry_T_4665 = _issue_entry_T_4664 | _issue_entry_T_4650; // @[Mux.scala:30:73] wire _issue_entry_T_4666 = _issue_entry_T_4665 | _issue_entry_T_4651; // @[Mux.scala:30:73] wire _issue_entry_T_4667 = _issue_entry_T_4666 | _issue_entry_T_4652; // @[Mux.scala:30:73] wire _issue_entry_T_4668 = _issue_entry_T_4667 | _issue_entry_T_4653; // @[Mux.scala:30:73] wire _issue_entry_T_4669 = _issue_entry_T_4668 | _issue_entry_T_4654; // @[Mux.scala:30:73] assign _issue_entry_WIRE_249 = _issue_entry_T_4669; // @[Mux.scala:30:73] assign _issue_entry_WIRE_247_garbage_bit = _issue_entry_WIRE_249; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_4670 = issue_sel_0_1 ? entries_ex_0_bits_opb_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_4671 = issue_sel_1_1 ? entries_ex_1_bits_opb_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_4672 = issue_sel_2_1 ? entries_ex_2_bits_opb_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_4673 = issue_sel_3_1 ? entries_ex_3_bits_opb_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_4674 = issue_sel_4_1 ? entries_ex_4_bits_opb_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_4675 = issue_sel_5_1 ? entries_ex_5_bits_opb_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_4676 = issue_sel_6_1 ? entries_ex_6_bits_opb_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_4677 = issue_sel_7_1 ? entries_ex_7_bits_opb_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_4678 = issue_sel_8 ? entries_ex_8_bits_opb_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_4679 = issue_sel_9 ? entries_ex_9_bits_opb_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_4680 = issue_sel_10 ? entries_ex_10_bits_opb_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_4681 = issue_sel_11 ? entries_ex_11_bits_opb_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_4682 = issue_sel_12 ? entries_ex_12_bits_opb_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_4683 = issue_sel_13 ? entries_ex_13_bits_opb_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_4684 = issue_sel_14 ? entries_ex_14_bits_opb_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_4685 = issue_sel_15 ? entries_ex_15_bits_opb_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_4686 = _issue_entry_T_4670 | _issue_entry_T_4671; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_4687 = _issue_entry_T_4686 | _issue_entry_T_4672; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_4688 = _issue_entry_T_4687 | _issue_entry_T_4673; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_4689 = _issue_entry_T_4688 | _issue_entry_T_4674; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_4690 = _issue_entry_T_4689 | _issue_entry_T_4675; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_4691 = _issue_entry_T_4690 | _issue_entry_T_4676; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_4692 = _issue_entry_T_4691 | _issue_entry_T_4677; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_4693 = _issue_entry_T_4692 | _issue_entry_T_4678; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_4694 = _issue_entry_T_4693 | _issue_entry_T_4679; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_4695 = _issue_entry_T_4694 | _issue_entry_T_4680; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_4696 = _issue_entry_T_4695 | _issue_entry_T_4681; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_4697 = _issue_entry_T_4696 | _issue_entry_T_4682; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_4698 = _issue_entry_T_4697 | _issue_entry_T_4683; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_4699 = _issue_entry_T_4698 | _issue_entry_T_4684; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_4700 = _issue_entry_T_4699 | _issue_entry_T_4685; // @[Mux.scala:30:73] assign _issue_entry_WIRE_250 = _issue_entry_T_4700; // @[Mux.scala:30:73] assign _issue_entry_WIRE_247_garbage = _issue_entry_WIRE_250; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_4702 = issue_sel_0_1 ? _issue_entry_T_4701 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_4704 = issue_sel_1_1 ? _issue_entry_T_4703 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_4706 = issue_sel_2_1 ? _issue_entry_T_4705 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_4708 = issue_sel_3_1 ? _issue_entry_T_4707 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_4710 = issue_sel_4_1 ? _issue_entry_T_4709 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_4712 = issue_sel_5_1 ? _issue_entry_T_4711 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_4714 = issue_sel_6_1 ? _issue_entry_T_4713 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_4716 = issue_sel_7_1 ? _issue_entry_T_4715 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_4718 = issue_sel_8 ? _issue_entry_T_4717 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_4720 = issue_sel_9 ? _issue_entry_T_4719 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_4722 = issue_sel_10 ? _issue_entry_T_4721 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_4724 = issue_sel_11 ? _issue_entry_T_4723 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_4726 = issue_sel_12 ? _issue_entry_T_4725 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_4728 = issue_sel_13 ? _issue_entry_T_4727 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_4730 = issue_sel_14 ? _issue_entry_T_4729 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_4732 = issue_sel_15 ? _issue_entry_T_4731 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_4733 = _issue_entry_T_4702 | _issue_entry_T_4704; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_4734 = _issue_entry_T_4733 | _issue_entry_T_4706; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_4735 = _issue_entry_T_4734 | _issue_entry_T_4708; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_4736 = _issue_entry_T_4735 | _issue_entry_T_4710; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_4737 = _issue_entry_T_4736 | _issue_entry_T_4712; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_4738 = _issue_entry_T_4737 | _issue_entry_T_4714; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_4739 = _issue_entry_T_4738 | _issue_entry_T_4716; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_4740 = _issue_entry_T_4739 | _issue_entry_T_4718; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_4741 = _issue_entry_T_4740 | _issue_entry_T_4720; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_4742 = _issue_entry_T_4741 | _issue_entry_T_4722; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_4743 = _issue_entry_T_4742 | _issue_entry_T_4724; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_4744 = _issue_entry_T_4743 | _issue_entry_T_4726; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_4745 = _issue_entry_T_4744 | _issue_entry_T_4728; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_4746 = _issue_entry_T_4745 | _issue_entry_T_4730; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_4747 = _issue_entry_T_4746 | _issue_entry_T_4732; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_252 = _issue_entry_T_4747; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_253; // @[Mux.scala:30:73] assign _issue_entry_WIRE_247_norm_cmd = _issue_entry_WIRE_251; // @[Mux.scala:30:73] assign _issue_entry_WIRE_253 = _issue_entry_WIRE_252; // @[Mux.scala:30:73] assign _issue_entry_WIRE_251 = _issue_entry_WIRE_253; // @[Mux.scala:30:73] wire _issue_entry_T_4748 = issue_sel_0_1 & entries_ex_0_bits_opb_bits_start_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_4749 = issue_sel_1_1 & entries_ex_1_bits_opb_bits_start_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_4750 = issue_sel_2_1 & entries_ex_2_bits_opb_bits_start_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_4751 = issue_sel_3_1 & entries_ex_3_bits_opb_bits_start_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_4752 = issue_sel_4_1 & entries_ex_4_bits_opb_bits_start_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_4753 = issue_sel_5_1 & entries_ex_5_bits_opb_bits_start_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_4754 = issue_sel_6_1 & entries_ex_6_bits_opb_bits_start_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_4755 = issue_sel_7_1 & entries_ex_7_bits_opb_bits_start_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_4756 = issue_sel_8 & entries_ex_8_bits_opb_bits_start_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_4757 = issue_sel_9 & entries_ex_9_bits_opb_bits_start_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_4758 = issue_sel_10 & entries_ex_10_bits_opb_bits_start_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_4759 = issue_sel_11 & entries_ex_11_bits_opb_bits_start_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_4760 = issue_sel_12 & entries_ex_12_bits_opb_bits_start_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_4761 = issue_sel_13 & entries_ex_13_bits_opb_bits_start_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_4762 = issue_sel_14 & entries_ex_14_bits_opb_bits_start_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_4763 = issue_sel_15 & entries_ex_15_bits_opb_bits_start_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_4764 = _issue_entry_T_4748 | _issue_entry_T_4749; // @[Mux.scala:30:73] wire _issue_entry_T_4765 = _issue_entry_T_4764 | _issue_entry_T_4750; // @[Mux.scala:30:73] wire _issue_entry_T_4766 = _issue_entry_T_4765 | _issue_entry_T_4751; // @[Mux.scala:30:73] wire _issue_entry_T_4767 = _issue_entry_T_4766 | _issue_entry_T_4752; // @[Mux.scala:30:73] wire _issue_entry_T_4768 = _issue_entry_T_4767 | _issue_entry_T_4753; // @[Mux.scala:30:73] wire _issue_entry_T_4769 = _issue_entry_T_4768 | _issue_entry_T_4754; // @[Mux.scala:30:73] wire _issue_entry_T_4770 = _issue_entry_T_4769 | _issue_entry_T_4755; // @[Mux.scala:30:73] wire _issue_entry_T_4771 = _issue_entry_T_4770 | _issue_entry_T_4756; // @[Mux.scala:30:73] wire _issue_entry_T_4772 = _issue_entry_T_4771 | _issue_entry_T_4757; // @[Mux.scala:30:73] wire _issue_entry_T_4773 = _issue_entry_T_4772 | _issue_entry_T_4758; // @[Mux.scala:30:73] wire _issue_entry_T_4774 = _issue_entry_T_4773 | _issue_entry_T_4759; // @[Mux.scala:30:73] wire _issue_entry_T_4775 = _issue_entry_T_4774 | _issue_entry_T_4760; // @[Mux.scala:30:73] wire _issue_entry_T_4776 = _issue_entry_T_4775 | _issue_entry_T_4761; // @[Mux.scala:30:73] wire _issue_entry_T_4777 = _issue_entry_T_4776 | _issue_entry_T_4762; // @[Mux.scala:30:73] wire _issue_entry_T_4778 = _issue_entry_T_4777 | _issue_entry_T_4763; // @[Mux.scala:30:73] assign _issue_entry_WIRE_254 = _issue_entry_T_4778; // @[Mux.scala:30:73] assign _issue_entry_WIRE_247_read_full_acc_row = _issue_entry_WIRE_254; // @[Mux.scala:30:73] wire _issue_entry_T_4779 = issue_sel_0_1 & entries_ex_0_bits_opb_bits_start_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_4780 = issue_sel_1_1 & entries_ex_1_bits_opb_bits_start_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_4781 = issue_sel_2_1 & entries_ex_2_bits_opb_bits_start_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_4782 = issue_sel_3_1 & entries_ex_3_bits_opb_bits_start_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_4783 = issue_sel_4_1 & entries_ex_4_bits_opb_bits_start_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_4784 = issue_sel_5_1 & entries_ex_5_bits_opb_bits_start_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_4785 = issue_sel_6_1 & entries_ex_6_bits_opb_bits_start_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_4786 = issue_sel_7_1 & entries_ex_7_bits_opb_bits_start_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_4787 = issue_sel_8 & entries_ex_8_bits_opb_bits_start_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_4788 = issue_sel_9 & entries_ex_9_bits_opb_bits_start_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_4789 = issue_sel_10 & entries_ex_10_bits_opb_bits_start_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_4790 = issue_sel_11 & entries_ex_11_bits_opb_bits_start_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_4791 = issue_sel_12 & entries_ex_12_bits_opb_bits_start_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_4792 = issue_sel_13 & entries_ex_13_bits_opb_bits_start_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_4793 = issue_sel_14 & entries_ex_14_bits_opb_bits_start_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_4794 = issue_sel_15 & entries_ex_15_bits_opb_bits_start_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_4795 = _issue_entry_T_4779 | _issue_entry_T_4780; // @[Mux.scala:30:73] wire _issue_entry_T_4796 = _issue_entry_T_4795 | _issue_entry_T_4781; // @[Mux.scala:30:73] wire _issue_entry_T_4797 = _issue_entry_T_4796 | _issue_entry_T_4782; // @[Mux.scala:30:73] wire _issue_entry_T_4798 = _issue_entry_T_4797 | _issue_entry_T_4783; // @[Mux.scala:30:73] wire _issue_entry_T_4799 = _issue_entry_T_4798 | _issue_entry_T_4784; // @[Mux.scala:30:73] wire _issue_entry_T_4800 = _issue_entry_T_4799 | _issue_entry_T_4785; // @[Mux.scala:30:73] wire _issue_entry_T_4801 = _issue_entry_T_4800 | _issue_entry_T_4786; // @[Mux.scala:30:73] wire _issue_entry_T_4802 = _issue_entry_T_4801 | _issue_entry_T_4787; // @[Mux.scala:30:73] wire _issue_entry_T_4803 = _issue_entry_T_4802 | _issue_entry_T_4788; // @[Mux.scala:30:73] wire _issue_entry_T_4804 = _issue_entry_T_4803 | _issue_entry_T_4789; // @[Mux.scala:30:73] wire _issue_entry_T_4805 = _issue_entry_T_4804 | _issue_entry_T_4790; // @[Mux.scala:30:73] wire _issue_entry_T_4806 = _issue_entry_T_4805 | _issue_entry_T_4791; // @[Mux.scala:30:73] wire _issue_entry_T_4807 = _issue_entry_T_4806 | _issue_entry_T_4792; // @[Mux.scala:30:73] wire _issue_entry_T_4808 = _issue_entry_T_4807 | _issue_entry_T_4793; // @[Mux.scala:30:73] wire _issue_entry_T_4809 = _issue_entry_T_4808 | _issue_entry_T_4794; // @[Mux.scala:30:73] assign _issue_entry_WIRE_255 = _issue_entry_T_4809; // @[Mux.scala:30:73] assign _issue_entry_WIRE_247_accumulate = _issue_entry_WIRE_255; // @[Mux.scala:30:73] wire _issue_entry_T_4810 = issue_sel_0_1 & entries_ex_0_bits_opb_bits_start_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_4811 = issue_sel_1_1 & entries_ex_1_bits_opb_bits_start_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_4812 = issue_sel_2_1 & entries_ex_2_bits_opb_bits_start_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_4813 = issue_sel_3_1 & entries_ex_3_bits_opb_bits_start_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_4814 = issue_sel_4_1 & entries_ex_4_bits_opb_bits_start_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_4815 = issue_sel_5_1 & entries_ex_5_bits_opb_bits_start_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_4816 = issue_sel_6_1 & entries_ex_6_bits_opb_bits_start_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_4817 = issue_sel_7_1 & entries_ex_7_bits_opb_bits_start_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_4818 = issue_sel_8 & entries_ex_8_bits_opb_bits_start_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_4819 = issue_sel_9 & entries_ex_9_bits_opb_bits_start_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_4820 = issue_sel_10 & entries_ex_10_bits_opb_bits_start_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_4821 = issue_sel_11 & entries_ex_11_bits_opb_bits_start_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_4822 = issue_sel_12 & entries_ex_12_bits_opb_bits_start_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_4823 = issue_sel_13 & entries_ex_13_bits_opb_bits_start_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_4824 = issue_sel_14 & entries_ex_14_bits_opb_bits_start_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_4825 = issue_sel_15 & entries_ex_15_bits_opb_bits_start_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_4826 = _issue_entry_T_4810 | _issue_entry_T_4811; // @[Mux.scala:30:73] wire _issue_entry_T_4827 = _issue_entry_T_4826 | _issue_entry_T_4812; // @[Mux.scala:30:73] wire _issue_entry_T_4828 = _issue_entry_T_4827 | _issue_entry_T_4813; // @[Mux.scala:30:73] wire _issue_entry_T_4829 = _issue_entry_T_4828 | _issue_entry_T_4814; // @[Mux.scala:30:73] wire _issue_entry_T_4830 = _issue_entry_T_4829 | _issue_entry_T_4815; // @[Mux.scala:30:73] wire _issue_entry_T_4831 = _issue_entry_T_4830 | _issue_entry_T_4816; // @[Mux.scala:30:73] wire _issue_entry_T_4832 = _issue_entry_T_4831 | _issue_entry_T_4817; // @[Mux.scala:30:73] wire _issue_entry_T_4833 = _issue_entry_T_4832 | _issue_entry_T_4818; // @[Mux.scala:30:73] wire _issue_entry_T_4834 = _issue_entry_T_4833 | _issue_entry_T_4819; // @[Mux.scala:30:73] wire _issue_entry_T_4835 = _issue_entry_T_4834 | _issue_entry_T_4820; // @[Mux.scala:30:73] wire _issue_entry_T_4836 = _issue_entry_T_4835 | _issue_entry_T_4821; // @[Mux.scala:30:73] wire _issue_entry_T_4837 = _issue_entry_T_4836 | _issue_entry_T_4822; // @[Mux.scala:30:73] wire _issue_entry_T_4838 = _issue_entry_T_4837 | _issue_entry_T_4823; // @[Mux.scala:30:73] wire _issue_entry_T_4839 = _issue_entry_T_4838 | _issue_entry_T_4824; // @[Mux.scala:30:73] wire _issue_entry_T_4840 = _issue_entry_T_4839 | _issue_entry_T_4825; // @[Mux.scala:30:73] assign _issue_entry_WIRE_256 = _issue_entry_T_4840; // @[Mux.scala:30:73] assign _issue_entry_WIRE_247_is_acc_addr = _issue_entry_WIRE_256; // @[Mux.scala:30:73] wire _issue_entry_T_4841 = issue_sel_0_1 & entries_ex_0_bits_opb_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_4842 = issue_sel_1_1 & entries_ex_1_bits_opb_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_4843 = issue_sel_2_1 & entries_ex_2_bits_opb_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_4844 = issue_sel_3_1 & entries_ex_3_bits_opb_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_4845 = issue_sel_4_1 & entries_ex_4_bits_opb_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_4846 = issue_sel_5_1 & entries_ex_5_bits_opb_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_4847 = issue_sel_6_1 & entries_ex_6_bits_opb_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_4848 = issue_sel_7_1 & entries_ex_7_bits_opb_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_4849 = issue_sel_8 & entries_ex_8_bits_opb_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_4850 = issue_sel_9 & entries_ex_9_bits_opb_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_4851 = issue_sel_10 & entries_ex_10_bits_opb_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_4852 = issue_sel_11 & entries_ex_11_bits_opb_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_4853 = issue_sel_12 & entries_ex_12_bits_opb_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_4854 = issue_sel_13 & entries_ex_13_bits_opb_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_4855 = issue_sel_14 & entries_ex_14_bits_opb_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_4856 = issue_sel_15 & entries_ex_15_bits_opb_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_4857 = _issue_entry_T_4841 | _issue_entry_T_4842; // @[Mux.scala:30:73] wire _issue_entry_T_4858 = _issue_entry_T_4857 | _issue_entry_T_4843; // @[Mux.scala:30:73] wire _issue_entry_T_4859 = _issue_entry_T_4858 | _issue_entry_T_4844; // @[Mux.scala:30:73] wire _issue_entry_T_4860 = _issue_entry_T_4859 | _issue_entry_T_4845; // @[Mux.scala:30:73] wire _issue_entry_T_4861 = _issue_entry_T_4860 | _issue_entry_T_4846; // @[Mux.scala:30:73] wire _issue_entry_T_4862 = _issue_entry_T_4861 | _issue_entry_T_4847; // @[Mux.scala:30:73] wire _issue_entry_T_4863 = _issue_entry_T_4862 | _issue_entry_T_4848; // @[Mux.scala:30:73] wire _issue_entry_T_4864 = _issue_entry_T_4863 | _issue_entry_T_4849; // @[Mux.scala:30:73] wire _issue_entry_T_4865 = _issue_entry_T_4864 | _issue_entry_T_4850; // @[Mux.scala:30:73] wire _issue_entry_T_4866 = _issue_entry_T_4865 | _issue_entry_T_4851; // @[Mux.scala:30:73] wire _issue_entry_T_4867 = _issue_entry_T_4866 | _issue_entry_T_4852; // @[Mux.scala:30:73] wire _issue_entry_T_4868 = _issue_entry_T_4867 | _issue_entry_T_4853; // @[Mux.scala:30:73] wire _issue_entry_T_4869 = _issue_entry_T_4868 | _issue_entry_T_4854; // @[Mux.scala:30:73] wire _issue_entry_T_4870 = _issue_entry_T_4869 | _issue_entry_T_4855; // @[Mux.scala:30:73] wire _issue_entry_T_4871 = _issue_entry_T_4870 | _issue_entry_T_4856; // @[Mux.scala:30:73] assign _issue_entry_WIRE_257 = _issue_entry_T_4871; // @[Mux.scala:30:73] assign _issue_entry_WIRE_234_valid = _issue_entry_WIRE_257; // @[Mux.scala:30:73] wire _issue_entry_T_4872 = issue_sel_0_1 & entries_ex_0_bits_opa_is_dst; // @[OneHot.scala:83:30] wire _issue_entry_T_4873 = issue_sel_1_1 & entries_ex_1_bits_opa_is_dst; // @[OneHot.scala:83:30] wire _issue_entry_T_4874 = issue_sel_2_1 & entries_ex_2_bits_opa_is_dst; // @[OneHot.scala:83:30] wire _issue_entry_T_4875 = issue_sel_3_1 & entries_ex_3_bits_opa_is_dst; // @[OneHot.scala:83:30] wire _issue_entry_T_4876 = issue_sel_4_1 & entries_ex_4_bits_opa_is_dst; // @[OneHot.scala:83:30] wire _issue_entry_T_4877 = issue_sel_5_1 & entries_ex_5_bits_opa_is_dst; // @[OneHot.scala:83:30] wire _issue_entry_T_4878 = issue_sel_6_1 & entries_ex_6_bits_opa_is_dst; // @[OneHot.scala:83:30] wire _issue_entry_T_4879 = issue_sel_7_1 & entries_ex_7_bits_opa_is_dst; // @[OneHot.scala:83:30] wire _issue_entry_T_4880 = issue_sel_8 & entries_ex_8_bits_opa_is_dst; // @[OneHot.scala:83:30] wire _issue_entry_T_4881 = issue_sel_9 & entries_ex_9_bits_opa_is_dst; // @[OneHot.scala:83:30] wire _issue_entry_T_4882 = issue_sel_10 & entries_ex_10_bits_opa_is_dst; // @[OneHot.scala:83:30] wire _issue_entry_T_4883 = issue_sel_11 & entries_ex_11_bits_opa_is_dst; // @[OneHot.scala:83:30] wire _issue_entry_T_4884 = issue_sel_12 & entries_ex_12_bits_opa_is_dst; // @[OneHot.scala:83:30] wire _issue_entry_T_4885 = issue_sel_13 & entries_ex_13_bits_opa_is_dst; // @[OneHot.scala:83:30] wire _issue_entry_T_4886 = issue_sel_14 & entries_ex_14_bits_opa_is_dst; // @[OneHot.scala:83:30] wire _issue_entry_T_4887 = issue_sel_15 & entries_ex_15_bits_opa_is_dst; // @[OneHot.scala:83:30] wire _issue_entry_T_4888 = _issue_entry_T_4872 | _issue_entry_T_4873; // @[Mux.scala:30:73] wire _issue_entry_T_4889 = _issue_entry_T_4888 | _issue_entry_T_4874; // @[Mux.scala:30:73] wire _issue_entry_T_4890 = _issue_entry_T_4889 | _issue_entry_T_4875; // @[Mux.scala:30:73] wire _issue_entry_T_4891 = _issue_entry_T_4890 | _issue_entry_T_4876; // @[Mux.scala:30:73] wire _issue_entry_T_4892 = _issue_entry_T_4891 | _issue_entry_T_4877; // @[Mux.scala:30:73] wire _issue_entry_T_4893 = _issue_entry_T_4892 | _issue_entry_T_4878; // @[Mux.scala:30:73] wire _issue_entry_T_4894 = _issue_entry_T_4893 | _issue_entry_T_4879; // @[Mux.scala:30:73] wire _issue_entry_T_4895 = _issue_entry_T_4894 | _issue_entry_T_4880; // @[Mux.scala:30:73] wire _issue_entry_T_4896 = _issue_entry_T_4895 | _issue_entry_T_4881; // @[Mux.scala:30:73] wire _issue_entry_T_4897 = _issue_entry_T_4896 | _issue_entry_T_4882; // @[Mux.scala:30:73] wire _issue_entry_T_4898 = _issue_entry_T_4897 | _issue_entry_T_4883; // @[Mux.scala:30:73] wire _issue_entry_T_4899 = _issue_entry_T_4898 | _issue_entry_T_4884; // @[Mux.scala:30:73] wire _issue_entry_T_4900 = _issue_entry_T_4899 | _issue_entry_T_4885; // @[Mux.scala:30:73] wire _issue_entry_T_4901 = _issue_entry_T_4900 | _issue_entry_T_4886; // @[Mux.scala:30:73] wire _issue_entry_T_4902 = _issue_entry_T_4901 | _issue_entry_T_4887; // @[Mux.scala:30:73] assign _issue_entry_WIRE_258 = _issue_entry_T_4902; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_opa_is_dst = _issue_entry_WIRE_258; // @[Mux.scala:30:73] wire _issue_entry_WIRE_282; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_opa_valid = _issue_entry_WIRE_259_valid; // @[Mux.scala:30:73] wire _issue_entry_WIRE_260_start_is_acc_addr; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_opa_bits_start_is_acc_addr = _issue_entry_WIRE_259_bits_start_is_acc_addr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_260_start_accumulate; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_opa_bits_start_accumulate = _issue_entry_WIRE_259_bits_start_accumulate; // @[Mux.scala:30:73] wire _issue_entry_WIRE_260_start_read_full_acc_row; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_opa_bits_start_read_full_acc_row = _issue_entry_WIRE_259_bits_start_read_full_acc_row; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_260_start_norm_cmd; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_opa_bits_start_norm_cmd = _issue_entry_WIRE_259_bits_start_norm_cmd; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_260_start_garbage; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_opa_bits_start_garbage = _issue_entry_WIRE_259_bits_start_garbage; // @[Mux.scala:30:73] wire _issue_entry_WIRE_260_start_garbage_bit; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_opa_bits_start_garbage_bit = _issue_entry_WIRE_259_bits_start_garbage_bit; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_260_start_data; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_opa_bits_start_data = _issue_entry_WIRE_259_bits_start_data; // @[Mux.scala:30:73] wire _issue_entry_WIRE_260_end_is_acc_addr; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_opa_bits_end_is_acc_addr = _issue_entry_WIRE_259_bits_end_is_acc_addr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_260_end_accumulate; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_opa_bits_end_accumulate = _issue_entry_WIRE_259_bits_end_accumulate; // @[Mux.scala:30:73] wire _issue_entry_WIRE_260_end_read_full_acc_row; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_opa_bits_end_read_full_acc_row = _issue_entry_WIRE_259_bits_end_read_full_acc_row; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_260_end_norm_cmd; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_opa_bits_end_norm_cmd = _issue_entry_WIRE_259_bits_end_norm_cmd; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_260_end_garbage; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_opa_bits_end_garbage = _issue_entry_WIRE_259_bits_end_garbage; // @[Mux.scala:30:73] wire _issue_entry_WIRE_260_end_garbage_bit; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_opa_bits_end_garbage_bit = _issue_entry_WIRE_259_bits_end_garbage_bit; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_260_end_data; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_opa_bits_end_data = _issue_entry_WIRE_259_bits_end_data; // @[Mux.scala:30:73] wire _issue_entry_WIRE_260_wraps_around; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_opa_bits_wraps_around = _issue_entry_WIRE_259_bits_wraps_around; // @[Mux.scala:30:73] wire _issue_entry_WIRE_272_is_acc_addr; // @[Mux.scala:30:73] assign _issue_entry_WIRE_259_bits_start_is_acc_addr = _issue_entry_WIRE_260_start_is_acc_addr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_272_accumulate; // @[Mux.scala:30:73] assign _issue_entry_WIRE_259_bits_start_accumulate = _issue_entry_WIRE_260_start_accumulate; // @[Mux.scala:30:73] wire _issue_entry_WIRE_272_read_full_acc_row; // @[Mux.scala:30:73] assign _issue_entry_WIRE_259_bits_start_read_full_acc_row = _issue_entry_WIRE_260_start_read_full_acc_row; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_272_norm_cmd; // @[Mux.scala:30:73] assign _issue_entry_WIRE_259_bits_start_norm_cmd = _issue_entry_WIRE_260_start_norm_cmd; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_272_garbage; // @[Mux.scala:30:73] assign _issue_entry_WIRE_259_bits_start_garbage = _issue_entry_WIRE_260_start_garbage; // @[Mux.scala:30:73] wire _issue_entry_WIRE_272_garbage_bit; // @[Mux.scala:30:73] assign _issue_entry_WIRE_259_bits_start_garbage_bit = _issue_entry_WIRE_260_start_garbage_bit; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_272_data; // @[Mux.scala:30:73] assign _issue_entry_WIRE_259_bits_start_data = _issue_entry_WIRE_260_start_data; // @[Mux.scala:30:73] wire _issue_entry_WIRE_262_is_acc_addr; // @[Mux.scala:30:73] assign _issue_entry_WIRE_259_bits_end_is_acc_addr = _issue_entry_WIRE_260_end_is_acc_addr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_262_accumulate; // @[Mux.scala:30:73] assign _issue_entry_WIRE_259_bits_end_accumulate = _issue_entry_WIRE_260_end_accumulate; // @[Mux.scala:30:73] wire _issue_entry_WIRE_262_read_full_acc_row; // @[Mux.scala:30:73] assign _issue_entry_WIRE_259_bits_end_read_full_acc_row = _issue_entry_WIRE_260_end_read_full_acc_row; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_262_norm_cmd; // @[Mux.scala:30:73] assign _issue_entry_WIRE_259_bits_end_norm_cmd = _issue_entry_WIRE_260_end_norm_cmd; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_262_garbage; // @[Mux.scala:30:73] assign _issue_entry_WIRE_259_bits_end_garbage = _issue_entry_WIRE_260_end_garbage; // @[Mux.scala:30:73] wire _issue_entry_WIRE_262_garbage_bit; // @[Mux.scala:30:73] assign _issue_entry_WIRE_259_bits_end_garbage_bit = _issue_entry_WIRE_260_end_garbage_bit; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_262_data; // @[Mux.scala:30:73] assign _issue_entry_WIRE_259_bits_end_data = _issue_entry_WIRE_260_end_data; // @[Mux.scala:30:73] wire _issue_entry_WIRE_261; // @[Mux.scala:30:73] assign _issue_entry_WIRE_259_bits_wraps_around = _issue_entry_WIRE_260_wraps_around; // @[Mux.scala:30:73] wire _issue_entry_T_4903 = issue_sel_0_1 & entries_ex_0_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30] wire _issue_entry_T_4904 = issue_sel_1_1 & entries_ex_1_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30] wire _issue_entry_T_4905 = issue_sel_2_1 & entries_ex_2_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30] wire _issue_entry_T_4906 = issue_sel_3_1 & entries_ex_3_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30] wire _issue_entry_T_4907 = issue_sel_4_1 & entries_ex_4_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30] wire _issue_entry_T_4908 = issue_sel_5_1 & entries_ex_5_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30] wire _issue_entry_T_4909 = issue_sel_6_1 & entries_ex_6_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30] wire _issue_entry_T_4910 = issue_sel_7_1 & entries_ex_7_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30] wire _issue_entry_T_4911 = issue_sel_8 & entries_ex_8_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30] wire _issue_entry_T_4912 = issue_sel_9 & entries_ex_9_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30] wire _issue_entry_T_4913 = issue_sel_10 & entries_ex_10_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30] wire _issue_entry_T_4914 = issue_sel_11 & entries_ex_11_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30] wire _issue_entry_T_4915 = issue_sel_12 & entries_ex_12_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30] wire _issue_entry_T_4916 = issue_sel_13 & entries_ex_13_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30] wire _issue_entry_T_4917 = issue_sel_14 & entries_ex_14_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30] wire _issue_entry_T_4918 = issue_sel_15 & entries_ex_15_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30] wire _issue_entry_T_4919 = _issue_entry_T_4903 | _issue_entry_T_4904; // @[Mux.scala:30:73] wire _issue_entry_T_4920 = _issue_entry_T_4919 | _issue_entry_T_4905; // @[Mux.scala:30:73] wire _issue_entry_T_4921 = _issue_entry_T_4920 | _issue_entry_T_4906; // @[Mux.scala:30:73] wire _issue_entry_T_4922 = _issue_entry_T_4921 | _issue_entry_T_4907; // @[Mux.scala:30:73] wire _issue_entry_T_4923 = _issue_entry_T_4922 | _issue_entry_T_4908; // @[Mux.scala:30:73] wire _issue_entry_T_4924 = _issue_entry_T_4923 | _issue_entry_T_4909; // @[Mux.scala:30:73] wire _issue_entry_T_4925 = _issue_entry_T_4924 | _issue_entry_T_4910; // @[Mux.scala:30:73] wire _issue_entry_T_4926 = _issue_entry_T_4925 | _issue_entry_T_4911; // @[Mux.scala:30:73] wire _issue_entry_T_4927 = _issue_entry_T_4926 | _issue_entry_T_4912; // @[Mux.scala:30:73] wire _issue_entry_T_4928 = _issue_entry_T_4927 | _issue_entry_T_4913; // @[Mux.scala:30:73] wire _issue_entry_T_4929 = _issue_entry_T_4928 | _issue_entry_T_4914; // @[Mux.scala:30:73] wire _issue_entry_T_4930 = _issue_entry_T_4929 | _issue_entry_T_4915; // @[Mux.scala:30:73] wire _issue_entry_T_4931 = _issue_entry_T_4930 | _issue_entry_T_4916; // @[Mux.scala:30:73] wire _issue_entry_T_4932 = _issue_entry_T_4931 | _issue_entry_T_4917; // @[Mux.scala:30:73] wire _issue_entry_T_4933 = _issue_entry_T_4932 | _issue_entry_T_4918; // @[Mux.scala:30:73] assign _issue_entry_WIRE_261 = _issue_entry_T_4933; // @[Mux.scala:30:73] assign _issue_entry_WIRE_260_wraps_around = _issue_entry_WIRE_261; // @[Mux.scala:30:73] wire _issue_entry_WIRE_271; // @[Mux.scala:30:73] assign _issue_entry_WIRE_260_end_is_acc_addr = _issue_entry_WIRE_262_is_acc_addr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_270; // @[Mux.scala:30:73] assign _issue_entry_WIRE_260_end_accumulate = _issue_entry_WIRE_262_accumulate; // @[Mux.scala:30:73] wire _issue_entry_WIRE_269; // @[Mux.scala:30:73] assign _issue_entry_WIRE_260_end_read_full_acc_row = _issue_entry_WIRE_262_read_full_acc_row; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_266; // @[Mux.scala:30:73] assign _issue_entry_WIRE_260_end_norm_cmd = _issue_entry_WIRE_262_norm_cmd; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_265; // @[Mux.scala:30:73] assign _issue_entry_WIRE_260_end_garbage = _issue_entry_WIRE_262_garbage; // @[Mux.scala:30:73] wire _issue_entry_WIRE_264; // @[Mux.scala:30:73] assign _issue_entry_WIRE_260_end_garbage_bit = _issue_entry_WIRE_262_garbage_bit; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_263; // @[Mux.scala:30:73] assign _issue_entry_WIRE_260_end_data = _issue_entry_WIRE_262_data; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_4934 = issue_sel_0_1 ? entries_ex_0_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_4935 = issue_sel_1_1 ? entries_ex_1_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_4936 = issue_sel_2_1 ? entries_ex_2_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_4937 = issue_sel_3_1 ? entries_ex_3_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_4938 = issue_sel_4_1 ? entries_ex_4_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_4939 = issue_sel_5_1 ? entries_ex_5_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_4940 = issue_sel_6_1 ? entries_ex_6_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_4941 = issue_sel_7_1 ? entries_ex_7_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_4942 = issue_sel_8 ? entries_ex_8_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_4943 = issue_sel_9 ? entries_ex_9_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_4944 = issue_sel_10 ? entries_ex_10_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_4945 = issue_sel_11 ? entries_ex_11_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_4946 = issue_sel_12 ? entries_ex_12_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_4947 = issue_sel_13 ? entries_ex_13_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_4948 = issue_sel_14 ? entries_ex_14_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_4949 = issue_sel_15 ? entries_ex_15_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_4950 = _issue_entry_T_4934 | _issue_entry_T_4935; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_4951 = _issue_entry_T_4950 | _issue_entry_T_4936; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_4952 = _issue_entry_T_4951 | _issue_entry_T_4937; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_4953 = _issue_entry_T_4952 | _issue_entry_T_4938; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_4954 = _issue_entry_T_4953 | _issue_entry_T_4939; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_4955 = _issue_entry_T_4954 | _issue_entry_T_4940; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_4956 = _issue_entry_T_4955 | _issue_entry_T_4941; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_4957 = _issue_entry_T_4956 | _issue_entry_T_4942; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_4958 = _issue_entry_T_4957 | _issue_entry_T_4943; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_4959 = _issue_entry_T_4958 | _issue_entry_T_4944; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_4960 = _issue_entry_T_4959 | _issue_entry_T_4945; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_4961 = _issue_entry_T_4960 | _issue_entry_T_4946; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_4962 = _issue_entry_T_4961 | _issue_entry_T_4947; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_4963 = _issue_entry_T_4962 | _issue_entry_T_4948; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_4964 = _issue_entry_T_4963 | _issue_entry_T_4949; // @[Mux.scala:30:73] assign _issue_entry_WIRE_263 = _issue_entry_T_4964; // @[Mux.scala:30:73] assign _issue_entry_WIRE_262_data = _issue_entry_WIRE_263; // @[Mux.scala:30:73] wire _issue_entry_T_4965 = issue_sel_0_1 & entries_ex_0_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_4966 = issue_sel_1_1 & entries_ex_1_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_4967 = issue_sel_2_1 & entries_ex_2_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_4968 = issue_sel_3_1 & entries_ex_3_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_4969 = issue_sel_4_1 & entries_ex_4_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_4970 = issue_sel_5_1 & entries_ex_5_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_4971 = issue_sel_6_1 & entries_ex_6_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_4972 = issue_sel_7_1 & entries_ex_7_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_4973 = issue_sel_8 & entries_ex_8_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_4974 = issue_sel_9 & entries_ex_9_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_4975 = issue_sel_10 & entries_ex_10_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_4976 = issue_sel_11 & entries_ex_11_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_4977 = issue_sel_12 & entries_ex_12_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_4978 = issue_sel_13 & entries_ex_13_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_4979 = issue_sel_14 & entries_ex_14_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_4980 = issue_sel_15 & entries_ex_15_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_4981 = _issue_entry_T_4965 | _issue_entry_T_4966; // @[Mux.scala:30:73] wire _issue_entry_T_4982 = _issue_entry_T_4981 | _issue_entry_T_4967; // @[Mux.scala:30:73] wire _issue_entry_T_4983 = _issue_entry_T_4982 | _issue_entry_T_4968; // @[Mux.scala:30:73] wire _issue_entry_T_4984 = _issue_entry_T_4983 | _issue_entry_T_4969; // @[Mux.scala:30:73] wire _issue_entry_T_4985 = _issue_entry_T_4984 | _issue_entry_T_4970; // @[Mux.scala:30:73] wire _issue_entry_T_4986 = _issue_entry_T_4985 | _issue_entry_T_4971; // @[Mux.scala:30:73] wire _issue_entry_T_4987 = _issue_entry_T_4986 | _issue_entry_T_4972; // @[Mux.scala:30:73] wire _issue_entry_T_4988 = _issue_entry_T_4987 | _issue_entry_T_4973; // @[Mux.scala:30:73] wire _issue_entry_T_4989 = _issue_entry_T_4988 | _issue_entry_T_4974; // @[Mux.scala:30:73] wire _issue_entry_T_4990 = _issue_entry_T_4989 | _issue_entry_T_4975; // @[Mux.scala:30:73] wire _issue_entry_T_4991 = _issue_entry_T_4990 | _issue_entry_T_4976; // @[Mux.scala:30:73] wire _issue_entry_T_4992 = _issue_entry_T_4991 | _issue_entry_T_4977; // @[Mux.scala:30:73] wire _issue_entry_T_4993 = _issue_entry_T_4992 | _issue_entry_T_4978; // @[Mux.scala:30:73] wire _issue_entry_T_4994 = _issue_entry_T_4993 | _issue_entry_T_4979; // @[Mux.scala:30:73] wire _issue_entry_T_4995 = _issue_entry_T_4994 | _issue_entry_T_4980; // @[Mux.scala:30:73] assign _issue_entry_WIRE_264 = _issue_entry_T_4995; // @[Mux.scala:30:73] assign _issue_entry_WIRE_262_garbage_bit = _issue_entry_WIRE_264; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_4996 = issue_sel_0_1 ? entries_ex_0_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_4997 = issue_sel_1_1 ? entries_ex_1_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_4998 = issue_sel_2_1 ? entries_ex_2_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_4999 = issue_sel_3_1 ? entries_ex_3_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_5000 = issue_sel_4_1 ? entries_ex_4_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_5001 = issue_sel_5_1 ? entries_ex_5_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_5002 = issue_sel_6_1 ? entries_ex_6_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_5003 = issue_sel_7_1 ? entries_ex_7_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_5004 = issue_sel_8 ? entries_ex_8_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_5005 = issue_sel_9 ? entries_ex_9_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_5006 = issue_sel_10 ? entries_ex_10_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_5007 = issue_sel_11 ? entries_ex_11_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_5008 = issue_sel_12 ? entries_ex_12_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_5009 = issue_sel_13 ? entries_ex_13_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_5010 = issue_sel_14 ? entries_ex_14_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_5011 = issue_sel_15 ? entries_ex_15_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_5012 = _issue_entry_T_4996 | _issue_entry_T_4997; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_5013 = _issue_entry_T_5012 | _issue_entry_T_4998; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_5014 = _issue_entry_T_5013 | _issue_entry_T_4999; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_5015 = _issue_entry_T_5014 | _issue_entry_T_5000; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_5016 = _issue_entry_T_5015 | _issue_entry_T_5001; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_5017 = _issue_entry_T_5016 | _issue_entry_T_5002; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_5018 = _issue_entry_T_5017 | _issue_entry_T_5003; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_5019 = _issue_entry_T_5018 | _issue_entry_T_5004; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_5020 = _issue_entry_T_5019 | _issue_entry_T_5005; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_5021 = _issue_entry_T_5020 | _issue_entry_T_5006; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_5022 = _issue_entry_T_5021 | _issue_entry_T_5007; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_5023 = _issue_entry_T_5022 | _issue_entry_T_5008; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_5024 = _issue_entry_T_5023 | _issue_entry_T_5009; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_5025 = _issue_entry_T_5024 | _issue_entry_T_5010; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_5026 = _issue_entry_T_5025 | _issue_entry_T_5011; // @[Mux.scala:30:73] assign _issue_entry_WIRE_265 = _issue_entry_T_5026; // @[Mux.scala:30:73] assign _issue_entry_WIRE_262_garbage = _issue_entry_WIRE_265; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_5028 = issue_sel_0_1 ? _issue_entry_T_5027 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_5030 = issue_sel_1_1 ? _issue_entry_T_5029 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_5032 = issue_sel_2_1 ? _issue_entry_T_5031 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_5034 = issue_sel_3_1 ? _issue_entry_T_5033 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_5036 = issue_sel_4_1 ? _issue_entry_T_5035 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_5038 = issue_sel_5_1 ? _issue_entry_T_5037 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_5040 = issue_sel_6_1 ? _issue_entry_T_5039 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_5042 = issue_sel_7_1 ? _issue_entry_T_5041 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_5044 = issue_sel_8 ? _issue_entry_T_5043 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_5046 = issue_sel_9 ? _issue_entry_T_5045 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_5048 = issue_sel_10 ? _issue_entry_T_5047 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_5050 = issue_sel_11 ? _issue_entry_T_5049 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_5052 = issue_sel_12 ? _issue_entry_T_5051 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_5054 = issue_sel_13 ? _issue_entry_T_5053 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_5056 = issue_sel_14 ? _issue_entry_T_5055 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_5058 = issue_sel_15 ? _issue_entry_T_5057 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_5059 = _issue_entry_T_5028 | _issue_entry_T_5030; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_5060 = _issue_entry_T_5059 | _issue_entry_T_5032; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_5061 = _issue_entry_T_5060 | _issue_entry_T_5034; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_5062 = _issue_entry_T_5061 | _issue_entry_T_5036; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_5063 = _issue_entry_T_5062 | _issue_entry_T_5038; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_5064 = _issue_entry_T_5063 | _issue_entry_T_5040; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_5065 = _issue_entry_T_5064 | _issue_entry_T_5042; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_5066 = _issue_entry_T_5065 | _issue_entry_T_5044; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_5067 = _issue_entry_T_5066 | _issue_entry_T_5046; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_5068 = _issue_entry_T_5067 | _issue_entry_T_5048; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_5069 = _issue_entry_T_5068 | _issue_entry_T_5050; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_5070 = _issue_entry_T_5069 | _issue_entry_T_5052; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_5071 = _issue_entry_T_5070 | _issue_entry_T_5054; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_5072 = _issue_entry_T_5071 | _issue_entry_T_5056; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_5073 = _issue_entry_T_5072 | _issue_entry_T_5058; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_267 = _issue_entry_T_5073; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_268; // @[Mux.scala:30:73] assign _issue_entry_WIRE_262_norm_cmd = _issue_entry_WIRE_266; // @[Mux.scala:30:73] assign _issue_entry_WIRE_268 = _issue_entry_WIRE_267; // @[Mux.scala:30:73] assign _issue_entry_WIRE_266 = _issue_entry_WIRE_268; // @[Mux.scala:30:73] wire _issue_entry_T_5074 = issue_sel_0_1 & entries_ex_0_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_5075 = issue_sel_1_1 & entries_ex_1_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_5076 = issue_sel_2_1 & entries_ex_2_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_5077 = issue_sel_3_1 & entries_ex_3_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_5078 = issue_sel_4_1 & entries_ex_4_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_5079 = issue_sel_5_1 & entries_ex_5_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_5080 = issue_sel_6_1 & entries_ex_6_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_5081 = issue_sel_7_1 & entries_ex_7_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_5082 = issue_sel_8 & entries_ex_8_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_5083 = issue_sel_9 & entries_ex_9_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_5084 = issue_sel_10 & entries_ex_10_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_5085 = issue_sel_11 & entries_ex_11_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_5086 = issue_sel_12 & entries_ex_12_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_5087 = issue_sel_13 & entries_ex_13_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_5088 = issue_sel_14 & entries_ex_14_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_5089 = issue_sel_15 & entries_ex_15_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_5090 = _issue_entry_T_5074 | _issue_entry_T_5075; // @[Mux.scala:30:73] wire _issue_entry_T_5091 = _issue_entry_T_5090 | _issue_entry_T_5076; // @[Mux.scala:30:73] wire _issue_entry_T_5092 = _issue_entry_T_5091 | _issue_entry_T_5077; // @[Mux.scala:30:73] wire _issue_entry_T_5093 = _issue_entry_T_5092 | _issue_entry_T_5078; // @[Mux.scala:30:73] wire _issue_entry_T_5094 = _issue_entry_T_5093 | _issue_entry_T_5079; // @[Mux.scala:30:73] wire _issue_entry_T_5095 = _issue_entry_T_5094 | _issue_entry_T_5080; // @[Mux.scala:30:73] wire _issue_entry_T_5096 = _issue_entry_T_5095 | _issue_entry_T_5081; // @[Mux.scala:30:73] wire _issue_entry_T_5097 = _issue_entry_T_5096 | _issue_entry_T_5082; // @[Mux.scala:30:73] wire _issue_entry_T_5098 = _issue_entry_T_5097 | _issue_entry_T_5083; // @[Mux.scala:30:73] wire _issue_entry_T_5099 = _issue_entry_T_5098 | _issue_entry_T_5084; // @[Mux.scala:30:73] wire _issue_entry_T_5100 = _issue_entry_T_5099 | _issue_entry_T_5085; // @[Mux.scala:30:73] wire _issue_entry_T_5101 = _issue_entry_T_5100 | _issue_entry_T_5086; // @[Mux.scala:30:73] wire _issue_entry_T_5102 = _issue_entry_T_5101 | _issue_entry_T_5087; // @[Mux.scala:30:73] wire _issue_entry_T_5103 = _issue_entry_T_5102 | _issue_entry_T_5088; // @[Mux.scala:30:73] wire _issue_entry_T_5104 = _issue_entry_T_5103 | _issue_entry_T_5089; // @[Mux.scala:30:73] assign _issue_entry_WIRE_269 = _issue_entry_T_5104; // @[Mux.scala:30:73] assign _issue_entry_WIRE_262_read_full_acc_row = _issue_entry_WIRE_269; // @[Mux.scala:30:73] wire _issue_entry_T_5105 = issue_sel_0_1 & entries_ex_0_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_5106 = issue_sel_1_1 & entries_ex_1_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_5107 = issue_sel_2_1 & entries_ex_2_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_5108 = issue_sel_3_1 & entries_ex_3_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_5109 = issue_sel_4_1 & entries_ex_4_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_5110 = issue_sel_5_1 & entries_ex_5_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_5111 = issue_sel_6_1 & entries_ex_6_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_5112 = issue_sel_7_1 & entries_ex_7_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_5113 = issue_sel_8 & entries_ex_8_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_5114 = issue_sel_9 & entries_ex_9_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_5115 = issue_sel_10 & entries_ex_10_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_5116 = issue_sel_11 & entries_ex_11_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_5117 = issue_sel_12 & entries_ex_12_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_5118 = issue_sel_13 & entries_ex_13_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_5119 = issue_sel_14 & entries_ex_14_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_5120 = issue_sel_15 & entries_ex_15_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_5121 = _issue_entry_T_5105 | _issue_entry_T_5106; // @[Mux.scala:30:73] wire _issue_entry_T_5122 = _issue_entry_T_5121 | _issue_entry_T_5107; // @[Mux.scala:30:73] wire _issue_entry_T_5123 = _issue_entry_T_5122 | _issue_entry_T_5108; // @[Mux.scala:30:73] wire _issue_entry_T_5124 = _issue_entry_T_5123 | _issue_entry_T_5109; // @[Mux.scala:30:73] wire _issue_entry_T_5125 = _issue_entry_T_5124 | _issue_entry_T_5110; // @[Mux.scala:30:73] wire _issue_entry_T_5126 = _issue_entry_T_5125 | _issue_entry_T_5111; // @[Mux.scala:30:73] wire _issue_entry_T_5127 = _issue_entry_T_5126 | _issue_entry_T_5112; // @[Mux.scala:30:73] wire _issue_entry_T_5128 = _issue_entry_T_5127 | _issue_entry_T_5113; // @[Mux.scala:30:73] wire _issue_entry_T_5129 = _issue_entry_T_5128 | _issue_entry_T_5114; // @[Mux.scala:30:73] wire _issue_entry_T_5130 = _issue_entry_T_5129 | _issue_entry_T_5115; // @[Mux.scala:30:73] wire _issue_entry_T_5131 = _issue_entry_T_5130 | _issue_entry_T_5116; // @[Mux.scala:30:73] wire _issue_entry_T_5132 = _issue_entry_T_5131 | _issue_entry_T_5117; // @[Mux.scala:30:73] wire _issue_entry_T_5133 = _issue_entry_T_5132 | _issue_entry_T_5118; // @[Mux.scala:30:73] wire _issue_entry_T_5134 = _issue_entry_T_5133 | _issue_entry_T_5119; // @[Mux.scala:30:73] wire _issue_entry_T_5135 = _issue_entry_T_5134 | _issue_entry_T_5120; // @[Mux.scala:30:73] assign _issue_entry_WIRE_270 = _issue_entry_T_5135; // @[Mux.scala:30:73] assign _issue_entry_WIRE_262_accumulate = _issue_entry_WIRE_270; // @[Mux.scala:30:73] wire _issue_entry_T_5136 = issue_sel_0_1 & entries_ex_0_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_5137 = issue_sel_1_1 & entries_ex_1_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_5138 = issue_sel_2_1 & entries_ex_2_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_5139 = issue_sel_3_1 & entries_ex_3_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_5140 = issue_sel_4_1 & entries_ex_4_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_5141 = issue_sel_5_1 & entries_ex_5_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_5142 = issue_sel_6_1 & entries_ex_6_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_5143 = issue_sel_7_1 & entries_ex_7_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_5144 = issue_sel_8 & entries_ex_8_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_5145 = issue_sel_9 & entries_ex_9_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_5146 = issue_sel_10 & entries_ex_10_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_5147 = issue_sel_11 & entries_ex_11_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_5148 = issue_sel_12 & entries_ex_12_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_5149 = issue_sel_13 & entries_ex_13_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_5150 = issue_sel_14 & entries_ex_14_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_5151 = issue_sel_15 & entries_ex_15_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_5152 = _issue_entry_T_5136 | _issue_entry_T_5137; // @[Mux.scala:30:73] wire _issue_entry_T_5153 = _issue_entry_T_5152 | _issue_entry_T_5138; // @[Mux.scala:30:73] wire _issue_entry_T_5154 = _issue_entry_T_5153 | _issue_entry_T_5139; // @[Mux.scala:30:73] wire _issue_entry_T_5155 = _issue_entry_T_5154 | _issue_entry_T_5140; // @[Mux.scala:30:73] wire _issue_entry_T_5156 = _issue_entry_T_5155 | _issue_entry_T_5141; // @[Mux.scala:30:73] wire _issue_entry_T_5157 = _issue_entry_T_5156 | _issue_entry_T_5142; // @[Mux.scala:30:73] wire _issue_entry_T_5158 = _issue_entry_T_5157 | _issue_entry_T_5143; // @[Mux.scala:30:73] wire _issue_entry_T_5159 = _issue_entry_T_5158 | _issue_entry_T_5144; // @[Mux.scala:30:73] wire _issue_entry_T_5160 = _issue_entry_T_5159 | _issue_entry_T_5145; // @[Mux.scala:30:73] wire _issue_entry_T_5161 = _issue_entry_T_5160 | _issue_entry_T_5146; // @[Mux.scala:30:73] wire _issue_entry_T_5162 = _issue_entry_T_5161 | _issue_entry_T_5147; // @[Mux.scala:30:73] wire _issue_entry_T_5163 = _issue_entry_T_5162 | _issue_entry_T_5148; // @[Mux.scala:30:73] wire _issue_entry_T_5164 = _issue_entry_T_5163 | _issue_entry_T_5149; // @[Mux.scala:30:73] wire _issue_entry_T_5165 = _issue_entry_T_5164 | _issue_entry_T_5150; // @[Mux.scala:30:73] wire _issue_entry_T_5166 = _issue_entry_T_5165 | _issue_entry_T_5151; // @[Mux.scala:30:73] assign _issue_entry_WIRE_271 = _issue_entry_T_5166; // @[Mux.scala:30:73] assign _issue_entry_WIRE_262_is_acc_addr = _issue_entry_WIRE_271; // @[Mux.scala:30:73] wire _issue_entry_WIRE_281; // @[Mux.scala:30:73] assign _issue_entry_WIRE_260_start_is_acc_addr = _issue_entry_WIRE_272_is_acc_addr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_280; // @[Mux.scala:30:73] assign _issue_entry_WIRE_260_start_accumulate = _issue_entry_WIRE_272_accumulate; // @[Mux.scala:30:73] wire _issue_entry_WIRE_279; // @[Mux.scala:30:73] assign _issue_entry_WIRE_260_start_read_full_acc_row = _issue_entry_WIRE_272_read_full_acc_row; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_276; // @[Mux.scala:30:73] assign _issue_entry_WIRE_260_start_norm_cmd = _issue_entry_WIRE_272_norm_cmd; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_275; // @[Mux.scala:30:73] assign _issue_entry_WIRE_260_start_garbage = _issue_entry_WIRE_272_garbage; // @[Mux.scala:30:73] wire _issue_entry_WIRE_274; // @[Mux.scala:30:73] assign _issue_entry_WIRE_260_start_garbage_bit = _issue_entry_WIRE_272_garbage_bit; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_273; // @[Mux.scala:30:73] assign _issue_entry_WIRE_260_start_data = _issue_entry_WIRE_272_data; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_5167 = issue_sel_0_1 ? entries_ex_0_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_5168 = issue_sel_1_1 ? entries_ex_1_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_5169 = issue_sel_2_1 ? entries_ex_2_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_5170 = issue_sel_3_1 ? entries_ex_3_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_5171 = issue_sel_4_1 ? entries_ex_4_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_5172 = issue_sel_5_1 ? entries_ex_5_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_5173 = issue_sel_6_1 ? entries_ex_6_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_5174 = issue_sel_7_1 ? entries_ex_7_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_5175 = issue_sel_8 ? entries_ex_8_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_5176 = issue_sel_9 ? entries_ex_9_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_5177 = issue_sel_10 ? entries_ex_10_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_5178 = issue_sel_11 ? entries_ex_11_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_5179 = issue_sel_12 ? entries_ex_12_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_5180 = issue_sel_13 ? entries_ex_13_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_5181 = issue_sel_14 ? entries_ex_14_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_5182 = issue_sel_15 ? entries_ex_15_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_5183 = _issue_entry_T_5167 | _issue_entry_T_5168; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_5184 = _issue_entry_T_5183 | _issue_entry_T_5169; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_5185 = _issue_entry_T_5184 | _issue_entry_T_5170; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_5186 = _issue_entry_T_5185 | _issue_entry_T_5171; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_5187 = _issue_entry_T_5186 | _issue_entry_T_5172; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_5188 = _issue_entry_T_5187 | _issue_entry_T_5173; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_5189 = _issue_entry_T_5188 | _issue_entry_T_5174; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_5190 = _issue_entry_T_5189 | _issue_entry_T_5175; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_5191 = _issue_entry_T_5190 | _issue_entry_T_5176; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_5192 = _issue_entry_T_5191 | _issue_entry_T_5177; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_5193 = _issue_entry_T_5192 | _issue_entry_T_5178; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_5194 = _issue_entry_T_5193 | _issue_entry_T_5179; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_5195 = _issue_entry_T_5194 | _issue_entry_T_5180; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_5196 = _issue_entry_T_5195 | _issue_entry_T_5181; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_5197 = _issue_entry_T_5196 | _issue_entry_T_5182; // @[Mux.scala:30:73] assign _issue_entry_WIRE_273 = _issue_entry_T_5197; // @[Mux.scala:30:73] assign _issue_entry_WIRE_272_data = _issue_entry_WIRE_273; // @[Mux.scala:30:73] wire _issue_entry_T_5198 = issue_sel_0_1 & entries_ex_0_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_5199 = issue_sel_1_1 & entries_ex_1_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_5200 = issue_sel_2_1 & entries_ex_2_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_5201 = issue_sel_3_1 & entries_ex_3_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_5202 = issue_sel_4_1 & entries_ex_4_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_5203 = issue_sel_5_1 & entries_ex_5_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_5204 = issue_sel_6_1 & entries_ex_6_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_5205 = issue_sel_7_1 & entries_ex_7_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_5206 = issue_sel_8 & entries_ex_8_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_5207 = issue_sel_9 & entries_ex_9_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_5208 = issue_sel_10 & entries_ex_10_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_5209 = issue_sel_11 & entries_ex_11_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_5210 = issue_sel_12 & entries_ex_12_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_5211 = issue_sel_13 & entries_ex_13_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_5212 = issue_sel_14 & entries_ex_14_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_5213 = issue_sel_15 & entries_ex_15_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_5214 = _issue_entry_T_5198 | _issue_entry_T_5199; // @[Mux.scala:30:73] wire _issue_entry_T_5215 = _issue_entry_T_5214 | _issue_entry_T_5200; // @[Mux.scala:30:73] wire _issue_entry_T_5216 = _issue_entry_T_5215 | _issue_entry_T_5201; // @[Mux.scala:30:73] wire _issue_entry_T_5217 = _issue_entry_T_5216 | _issue_entry_T_5202; // @[Mux.scala:30:73] wire _issue_entry_T_5218 = _issue_entry_T_5217 | _issue_entry_T_5203; // @[Mux.scala:30:73] wire _issue_entry_T_5219 = _issue_entry_T_5218 | _issue_entry_T_5204; // @[Mux.scala:30:73] wire _issue_entry_T_5220 = _issue_entry_T_5219 | _issue_entry_T_5205; // @[Mux.scala:30:73] wire _issue_entry_T_5221 = _issue_entry_T_5220 | _issue_entry_T_5206; // @[Mux.scala:30:73] wire _issue_entry_T_5222 = _issue_entry_T_5221 | _issue_entry_T_5207; // @[Mux.scala:30:73] wire _issue_entry_T_5223 = _issue_entry_T_5222 | _issue_entry_T_5208; // @[Mux.scala:30:73] wire _issue_entry_T_5224 = _issue_entry_T_5223 | _issue_entry_T_5209; // @[Mux.scala:30:73] wire _issue_entry_T_5225 = _issue_entry_T_5224 | _issue_entry_T_5210; // @[Mux.scala:30:73] wire _issue_entry_T_5226 = _issue_entry_T_5225 | _issue_entry_T_5211; // @[Mux.scala:30:73] wire _issue_entry_T_5227 = _issue_entry_T_5226 | _issue_entry_T_5212; // @[Mux.scala:30:73] wire _issue_entry_T_5228 = _issue_entry_T_5227 | _issue_entry_T_5213; // @[Mux.scala:30:73] assign _issue_entry_WIRE_274 = _issue_entry_T_5228; // @[Mux.scala:30:73] assign _issue_entry_WIRE_272_garbage_bit = _issue_entry_WIRE_274; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_5229 = issue_sel_0_1 ? entries_ex_0_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_5230 = issue_sel_1_1 ? entries_ex_1_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_5231 = issue_sel_2_1 ? entries_ex_2_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_5232 = issue_sel_3_1 ? entries_ex_3_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_5233 = issue_sel_4_1 ? entries_ex_4_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_5234 = issue_sel_5_1 ? entries_ex_5_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_5235 = issue_sel_6_1 ? entries_ex_6_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_5236 = issue_sel_7_1 ? entries_ex_7_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_5237 = issue_sel_8 ? entries_ex_8_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_5238 = issue_sel_9 ? entries_ex_9_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_5239 = issue_sel_10 ? entries_ex_10_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_5240 = issue_sel_11 ? entries_ex_11_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_5241 = issue_sel_12 ? entries_ex_12_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_5242 = issue_sel_13 ? entries_ex_13_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_5243 = issue_sel_14 ? entries_ex_14_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_5244 = issue_sel_15 ? entries_ex_15_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_5245 = _issue_entry_T_5229 | _issue_entry_T_5230; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_5246 = _issue_entry_T_5245 | _issue_entry_T_5231; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_5247 = _issue_entry_T_5246 | _issue_entry_T_5232; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_5248 = _issue_entry_T_5247 | _issue_entry_T_5233; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_5249 = _issue_entry_T_5248 | _issue_entry_T_5234; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_5250 = _issue_entry_T_5249 | _issue_entry_T_5235; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_5251 = _issue_entry_T_5250 | _issue_entry_T_5236; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_5252 = _issue_entry_T_5251 | _issue_entry_T_5237; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_5253 = _issue_entry_T_5252 | _issue_entry_T_5238; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_5254 = _issue_entry_T_5253 | _issue_entry_T_5239; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_5255 = _issue_entry_T_5254 | _issue_entry_T_5240; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_5256 = _issue_entry_T_5255 | _issue_entry_T_5241; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_5257 = _issue_entry_T_5256 | _issue_entry_T_5242; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_5258 = _issue_entry_T_5257 | _issue_entry_T_5243; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_5259 = _issue_entry_T_5258 | _issue_entry_T_5244; // @[Mux.scala:30:73] assign _issue_entry_WIRE_275 = _issue_entry_T_5259; // @[Mux.scala:30:73] assign _issue_entry_WIRE_272_garbage = _issue_entry_WIRE_275; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_5261 = issue_sel_0_1 ? _issue_entry_T_5260 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_5263 = issue_sel_1_1 ? _issue_entry_T_5262 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_5265 = issue_sel_2_1 ? _issue_entry_T_5264 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_5267 = issue_sel_3_1 ? _issue_entry_T_5266 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_5269 = issue_sel_4_1 ? _issue_entry_T_5268 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_5271 = issue_sel_5_1 ? _issue_entry_T_5270 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_5273 = issue_sel_6_1 ? _issue_entry_T_5272 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_5275 = issue_sel_7_1 ? _issue_entry_T_5274 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_5277 = issue_sel_8 ? _issue_entry_T_5276 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_5279 = issue_sel_9 ? _issue_entry_T_5278 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_5281 = issue_sel_10 ? _issue_entry_T_5280 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_5283 = issue_sel_11 ? _issue_entry_T_5282 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_5285 = issue_sel_12 ? _issue_entry_T_5284 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_5287 = issue_sel_13 ? _issue_entry_T_5286 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_5289 = issue_sel_14 ? _issue_entry_T_5288 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_5291 = issue_sel_15 ? _issue_entry_T_5290 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_5292 = _issue_entry_T_5261 | _issue_entry_T_5263; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_5293 = _issue_entry_T_5292 | _issue_entry_T_5265; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_5294 = _issue_entry_T_5293 | _issue_entry_T_5267; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_5295 = _issue_entry_T_5294 | _issue_entry_T_5269; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_5296 = _issue_entry_T_5295 | _issue_entry_T_5271; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_5297 = _issue_entry_T_5296 | _issue_entry_T_5273; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_5298 = _issue_entry_T_5297 | _issue_entry_T_5275; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_5299 = _issue_entry_T_5298 | _issue_entry_T_5277; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_5300 = _issue_entry_T_5299 | _issue_entry_T_5279; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_5301 = _issue_entry_T_5300 | _issue_entry_T_5281; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_5302 = _issue_entry_T_5301 | _issue_entry_T_5283; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_5303 = _issue_entry_T_5302 | _issue_entry_T_5285; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_5304 = _issue_entry_T_5303 | _issue_entry_T_5287; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_5305 = _issue_entry_T_5304 | _issue_entry_T_5289; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_5306 = _issue_entry_T_5305 | _issue_entry_T_5291; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_277 = _issue_entry_T_5306; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_278; // @[Mux.scala:30:73] assign _issue_entry_WIRE_272_norm_cmd = _issue_entry_WIRE_276; // @[Mux.scala:30:73] assign _issue_entry_WIRE_278 = _issue_entry_WIRE_277; // @[Mux.scala:30:73] assign _issue_entry_WIRE_276 = _issue_entry_WIRE_278; // @[Mux.scala:30:73] wire _issue_entry_T_5307 = issue_sel_0_1 & entries_ex_0_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_5308 = issue_sel_1_1 & entries_ex_1_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_5309 = issue_sel_2_1 & entries_ex_2_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_5310 = issue_sel_3_1 & entries_ex_3_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_5311 = issue_sel_4_1 & entries_ex_4_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_5312 = issue_sel_5_1 & entries_ex_5_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_5313 = issue_sel_6_1 & entries_ex_6_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_5314 = issue_sel_7_1 & entries_ex_7_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_5315 = issue_sel_8 & entries_ex_8_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_5316 = issue_sel_9 & entries_ex_9_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_5317 = issue_sel_10 & entries_ex_10_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_5318 = issue_sel_11 & entries_ex_11_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_5319 = issue_sel_12 & entries_ex_12_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_5320 = issue_sel_13 & entries_ex_13_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_5321 = issue_sel_14 & entries_ex_14_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_5322 = issue_sel_15 & entries_ex_15_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_5323 = _issue_entry_T_5307 | _issue_entry_T_5308; // @[Mux.scala:30:73] wire _issue_entry_T_5324 = _issue_entry_T_5323 | _issue_entry_T_5309; // @[Mux.scala:30:73] wire _issue_entry_T_5325 = _issue_entry_T_5324 | _issue_entry_T_5310; // @[Mux.scala:30:73] wire _issue_entry_T_5326 = _issue_entry_T_5325 | _issue_entry_T_5311; // @[Mux.scala:30:73] wire _issue_entry_T_5327 = _issue_entry_T_5326 | _issue_entry_T_5312; // @[Mux.scala:30:73] wire _issue_entry_T_5328 = _issue_entry_T_5327 | _issue_entry_T_5313; // @[Mux.scala:30:73] wire _issue_entry_T_5329 = _issue_entry_T_5328 | _issue_entry_T_5314; // @[Mux.scala:30:73] wire _issue_entry_T_5330 = _issue_entry_T_5329 | _issue_entry_T_5315; // @[Mux.scala:30:73] wire _issue_entry_T_5331 = _issue_entry_T_5330 | _issue_entry_T_5316; // @[Mux.scala:30:73] wire _issue_entry_T_5332 = _issue_entry_T_5331 | _issue_entry_T_5317; // @[Mux.scala:30:73] wire _issue_entry_T_5333 = _issue_entry_T_5332 | _issue_entry_T_5318; // @[Mux.scala:30:73] wire _issue_entry_T_5334 = _issue_entry_T_5333 | _issue_entry_T_5319; // @[Mux.scala:30:73] wire _issue_entry_T_5335 = _issue_entry_T_5334 | _issue_entry_T_5320; // @[Mux.scala:30:73] wire _issue_entry_T_5336 = _issue_entry_T_5335 | _issue_entry_T_5321; // @[Mux.scala:30:73] wire _issue_entry_T_5337 = _issue_entry_T_5336 | _issue_entry_T_5322; // @[Mux.scala:30:73] assign _issue_entry_WIRE_279 = _issue_entry_T_5337; // @[Mux.scala:30:73] assign _issue_entry_WIRE_272_read_full_acc_row = _issue_entry_WIRE_279; // @[Mux.scala:30:73] wire _issue_entry_T_5338 = issue_sel_0_1 & entries_ex_0_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_5339 = issue_sel_1_1 & entries_ex_1_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_5340 = issue_sel_2_1 & entries_ex_2_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_5341 = issue_sel_3_1 & entries_ex_3_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_5342 = issue_sel_4_1 & entries_ex_4_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_5343 = issue_sel_5_1 & entries_ex_5_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_5344 = issue_sel_6_1 & entries_ex_6_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_5345 = issue_sel_7_1 & entries_ex_7_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_5346 = issue_sel_8 & entries_ex_8_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_5347 = issue_sel_9 & entries_ex_9_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_5348 = issue_sel_10 & entries_ex_10_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_5349 = issue_sel_11 & entries_ex_11_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_5350 = issue_sel_12 & entries_ex_12_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_5351 = issue_sel_13 & entries_ex_13_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_5352 = issue_sel_14 & entries_ex_14_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_5353 = issue_sel_15 & entries_ex_15_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_5354 = _issue_entry_T_5338 | _issue_entry_T_5339; // @[Mux.scala:30:73] wire _issue_entry_T_5355 = _issue_entry_T_5354 | _issue_entry_T_5340; // @[Mux.scala:30:73] wire _issue_entry_T_5356 = _issue_entry_T_5355 | _issue_entry_T_5341; // @[Mux.scala:30:73] wire _issue_entry_T_5357 = _issue_entry_T_5356 | _issue_entry_T_5342; // @[Mux.scala:30:73] wire _issue_entry_T_5358 = _issue_entry_T_5357 | _issue_entry_T_5343; // @[Mux.scala:30:73] wire _issue_entry_T_5359 = _issue_entry_T_5358 | _issue_entry_T_5344; // @[Mux.scala:30:73] wire _issue_entry_T_5360 = _issue_entry_T_5359 | _issue_entry_T_5345; // @[Mux.scala:30:73] wire _issue_entry_T_5361 = _issue_entry_T_5360 | _issue_entry_T_5346; // @[Mux.scala:30:73] wire _issue_entry_T_5362 = _issue_entry_T_5361 | _issue_entry_T_5347; // @[Mux.scala:30:73] wire _issue_entry_T_5363 = _issue_entry_T_5362 | _issue_entry_T_5348; // @[Mux.scala:30:73] wire _issue_entry_T_5364 = _issue_entry_T_5363 | _issue_entry_T_5349; // @[Mux.scala:30:73] wire _issue_entry_T_5365 = _issue_entry_T_5364 | _issue_entry_T_5350; // @[Mux.scala:30:73] wire _issue_entry_T_5366 = _issue_entry_T_5365 | _issue_entry_T_5351; // @[Mux.scala:30:73] wire _issue_entry_T_5367 = _issue_entry_T_5366 | _issue_entry_T_5352; // @[Mux.scala:30:73] wire _issue_entry_T_5368 = _issue_entry_T_5367 | _issue_entry_T_5353; // @[Mux.scala:30:73] assign _issue_entry_WIRE_280 = _issue_entry_T_5368; // @[Mux.scala:30:73] assign _issue_entry_WIRE_272_accumulate = _issue_entry_WIRE_280; // @[Mux.scala:30:73] wire _issue_entry_T_5369 = issue_sel_0_1 & entries_ex_0_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_5370 = issue_sel_1_1 & entries_ex_1_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_5371 = issue_sel_2_1 & entries_ex_2_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_5372 = issue_sel_3_1 & entries_ex_3_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_5373 = issue_sel_4_1 & entries_ex_4_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_5374 = issue_sel_5_1 & entries_ex_5_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_5375 = issue_sel_6_1 & entries_ex_6_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_5376 = issue_sel_7_1 & entries_ex_7_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_5377 = issue_sel_8 & entries_ex_8_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_5378 = issue_sel_9 & entries_ex_9_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_5379 = issue_sel_10 & entries_ex_10_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_5380 = issue_sel_11 & entries_ex_11_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_5381 = issue_sel_12 & entries_ex_12_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_5382 = issue_sel_13 & entries_ex_13_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_5383 = issue_sel_14 & entries_ex_14_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_5384 = issue_sel_15 & entries_ex_15_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_5385 = _issue_entry_T_5369 | _issue_entry_T_5370; // @[Mux.scala:30:73] wire _issue_entry_T_5386 = _issue_entry_T_5385 | _issue_entry_T_5371; // @[Mux.scala:30:73] wire _issue_entry_T_5387 = _issue_entry_T_5386 | _issue_entry_T_5372; // @[Mux.scala:30:73] wire _issue_entry_T_5388 = _issue_entry_T_5387 | _issue_entry_T_5373; // @[Mux.scala:30:73] wire _issue_entry_T_5389 = _issue_entry_T_5388 | _issue_entry_T_5374; // @[Mux.scala:30:73] wire _issue_entry_T_5390 = _issue_entry_T_5389 | _issue_entry_T_5375; // @[Mux.scala:30:73] wire _issue_entry_T_5391 = _issue_entry_T_5390 | _issue_entry_T_5376; // @[Mux.scala:30:73] wire _issue_entry_T_5392 = _issue_entry_T_5391 | _issue_entry_T_5377; // @[Mux.scala:30:73] wire _issue_entry_T_5393 = _issue_entry_T_5392 | _issue_entry_T_5378; // @[Mux.scala:30:73] wire _issue_entry_T_5394 = _issue_entry_T_5393 | _issue_entry_T_5379; // @[Mux.scala:30:73] wire _issue_entry_T_5395 = _issue_entry_T_5394 | _issue_entry_T_5380; // @[Mux.scala:30:73] wire _issue_entry_T_5396 = _issue_entry_T_5395 | _issue_entry_T_5381; // @[Mux.scala:30:73] wire _issue_entry_T_5397 = _issue_entry_T_5396 | _issue_entry_T_5382; // @[Mux.scala:30:73] wire _issue_entry_T_5398 = _issue_entry_T_5397 | _issue_entry_T_5383; // @[Mux.scala:30:73] wire _issue_entry_T_5399 = _issue_entry_T_5398 | _issue_entry_T_5384; // @[Mux.scala:30:73] assign _issue_entry_WIRE_281 = _issue_entry_T_5399; // @[Mux.scala:30:73] assign _issue_entry_WIRE_272_is_acc_addr = _issue_entry_WIRE_281; // @[Mux.scala:30:73] wire _issue_entry_T_5400 = issue_sel_0_1 & entries_ex_0_bits_opa_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_5401 = issue_sel_1_1 & entries_ex_1_bits_opa_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_5402 = issue_sel_2_1 & entries_ex_2_bits_opa_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_5403 = issue_sel_3_1 & entries_ex_3_bits_opa_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_5404 = issue_sel_4_1 & entries_ex_4_bits_opa_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_5405 = issue_sel_5_1 & entries_ex_5_bits_opa_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_5406 = issue_sel_6_1 & entries_ex_6_bits_opa_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_5407 = issue_sel_7_1 & entries_ex_7_bits_opa_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_5408 = issue_sel_8 & entries_ex_8_bits_opa_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_5409 = issue_sel_9 & entries_ex_9_bits_opa_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_5410 = issue_sel_10 & entries_ex_10_bits_opa_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_5411 = issue_sel_11 & entries_ex_11_bits_opa_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_5412 = issue_sel_12 & entries_ex_12_bits_opa_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_5413 = issue_sel_13 & entries_ex_13_bits_opa_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_5414 = issue_sel_14 & entries_ex_14_bits_opa_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_5415 = issue_sel_15 & entries_ex_15_bits_opa_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_5416 = _issue_entry_T_5400 | _issue_entry_T_5401; // @[Mux.scala:30:73] wire _issue_entry_T_5417 = _issue_entry_T_5416 | _issue_entry_T_5402; // @[Mux.scala:30:73] wire _issue_entry_T_5418 = _issue_entry_T_5417 | _issue_entry_T_5403; // @[Mux.scala:30:73] wire _issue_entry_T_5419 = _issue_entry_T_5418 | _issue_entry_T_5404; // @[Mux.scala:30:73] wire _issue_entry_T_5420 = _issue_entry_T_5419 | _issue_entry_T_5405; // @[Mux.scala:30:73] wire _issue_entry_T_5421 = _issue_entry_T_5420 | _issue_entry_T_5406; // @[Mux.scala:30:73] wire _issue_entry_T_5422 = _issue_entry_T_5421 | _issue_entry_T_5407; // @[Mux.scala:30:73] wire _issue_entry_T_5423 = _issue_entry_T_5422 | _issue_entry_T_5408; // @[Mux.scala:30:73] wire _issue_entry_T_5424 = _issue_entry_T_5423 | _issue_entry_T_5409; // @[Mux.scala:30:73] wire _issue_entry_T_5425 = _issue_entry_T_5424 | _issue_entry_T_5410; // @[Mux.scala:30:73] wire _issue_entry_T_5426 = _issue_entry_T_5425 | _issue_entry_T_5411; // @[Mux.scala:30:73] wire _issue_entry_T_5427 = _issue_entry_T_5426 | _issue_entry_T_5412; // @[Mux.scala:30:73] wire _issue_entry_T_5428 = _issue_entry_T_5427 | _issue_entry_T_5413; // @[Mux.scala:30:73] wire _issue_entry_T_5429 = _issue_entry_T_5428 | _issue_entry_T_5414; // @[Mux.scala:30:73] wire _issue_entry_T_5430 = _issue_entry_T_5429 | _issue_entry_T_5415; // @[Mux.scala:30:73] assign _issue_entry_WIRE_282 = _issue_entry_T_5430; // @[Mux.scala:30:73] assign _issue_entry_WIRE_259_valid = _issue_entry_WIRE_282; // @[Mux.scala:30:73] wire _issue_entry_T_5431 = issue_sel_0_1 & entries_ex_0_bits_is_config; // @[OneHot.scala:83:30] wire _issue_entry_T_5432 = issue_sel_1_1 & entries_ex_1_bits_is_config; // @[OneHot.scala:83:30] wire _issue_entry_T_5433 = issue_sel_2_1 & entries_ex_2_bits_is_config; // @[OneHot.scala:83:30] wire _issue_entry_T_5434 = issue_sel_3_1 & entries_ex_3_bits_is_config; // @[OneHot.scala:83:30] wire _issue_entry_T_5435 = issue_sel_4_1 & entries_ex_4_bits_is_config; // @[OneHot.scala:83:30] wire _issue_entry_T_5436 = issue_sel_5_1 & entries_ex_5_bits_is_config; // @[OneHot.scala:83:30] wire _issue_entry_T_5437 = issue_sel_6_1 & entries_ex_6_bits_is_config; // @[OneHot.scala:83:30] wire _issue_entry_T_5438 = issue_sel_7_1 & entries_ex_7_bits_is_config; // @[OneHot.scala:83:30] wire _issue_entry_T_5439 = issue_sel_8 & entries_ex_8_bits_is_config; // @[OneHot.scala:83:30] wire _issue_entry_T_5440 = issue_sel_9 & entries_ex_9_bits_is_config; // @[OneHot.scala:83:30] wire _issue_entry_T_5441 = issue_sel_10 & entries_ex_10_bits_is_config; // @[OneHot.scala:83:30] wire _issue_entry_T_5442 = issue_sel_11 & entries_ex_11_bits_is_config; // @[OneHot.scala:83:30] wire _issue_entry_T_5443 = issue_sel_12 & entries_ex_12_bits_is_config; // @[OneHot.scala:83:30] wire _issue_entry_T_5444 = issue_sel_13 & entries_ex_13_bits_is_config; // @[OneHot.scala:83:30] wire _issue_entry_T_5445 = issue_sel_14 & entries_ex_14_bits_is_config; // @[OneHot.scala:83:30] wire _issue_entry_T_5446 = issue_sel_15 & entries_ex_15_bits_is_config; // @[OneHot.scala:83:30] wire _issue_entry_T_5447 = _issue_entry_T_5431 | _issue_entry_T_5432; // @[Mux.scala:30:73] wire _issue_entry_T_5448 = _issue_entry_T_5447 | _issue_entry_T_5433; // @[Mux.scala:30:73] wire _issue_entry_T_5449 = _issue_entry_T_5448 | _issue_entry_T_5434; // @[Mux.scala:30:73] wire _issue_entry_T_5450 = _issue_entry_T_5449 | _issue_entry_T_5435; // @[Mux.scala:30:73] wire _issue_entry_T_5451 = _issue_entry_T_5450 | _issue_entry_T_5436; // @[Mux.scala:30:73] wire _issue_entry_T_5452 = _issue_entry_T_5451 | _issue_entry_T_5437; // @[Mux.scala:30:73] wire _issue_entry_T_5453 = _issue_entry_T_5452 | _issue_entry_T_5438; // @[Mux.scala:30:73] wire _issue_entry_T_5454 = _issue_entry_T_5453 | _issue_entry_T_5439; // @[Mux.scala:30:73] wire _issue_entry_T_5455 = _issue_entry_T_5454 | _issue_entry_T_5440; // @[Mux.scala:30:73] wire _issue_entry_T_5456 = _issue_entry_T_5455 | _issue_entry_T_5441; // @[Mux.scala:30:73] wire _issue_entry_T_5457 = _issue_entry_T_5456 | _issue_entry_T_5442; // @[Mux.scala:30:73] wire _issue_entry_T_5458 = _issue_entry_T_5457 | _issue_entry_T_5443; // @[Mux.scala:30:73] wire _issue_entry_T_5459 = _issue_entry_T_5458 | _issue_entry_T_5444; // @[Mux.scala:30:73] wire _issue_entry_T_5460 = _issue_entry_T_5459 | _issue_entry_T_5445; // @[Mux.scala:30:73] wire _issue_entry_T_5461 = _issue_entry_T_5460 | _issue_entry_T_5446; // @[Mux.scala:30:73] assign _issue_entry_WIRE_283 = _issue_entry_T_5461; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_is_config = _issue_entry_WIRE_283; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_5462 = issue_sel_0_1 ? entries_ex_0_bits_q : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_5463 = issue_sel_1_1 ? entries_ex_1_bits_q : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_5464 = issue_sel_2_1 ? entries_ex_2_bits_q : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_5465 = issue_sel_3_1 ? entries_ex_3_bits_q : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_5466 = issue_sel_4_1 ? entries_ex_4_bits_q : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_5467 = issue_sel_5_1 ? entries_ex_5_bits_q : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_5468 = issue_sel_6_1 ? entries_ex_6_bits_q : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_5469 = issue_sel_7_1 ? entries_ex_7_bits_q : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_5470 = issue_sel_8 ? entries_ex_8_bits_q : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_5471 = issue_sel_9 ? entries_ex_9_bits_q : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_5472 = issue_sel_10 ? entries_ex_10_bits_q : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_5473 = issue_sel_11 ? entries_ex_11_bits_q : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_5474 = issue_sel_12 ? entries_ex_12_bits_q : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_5475 = issue_sel_13 ? entries_ex_13_bits_q : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_5476 = issue_sel_14 ? entries_ex_14_bits_q : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_5477 = issue_sel_15 ? entries_ex_15_bits_q : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_5478 = _issue_entry_T_5462 | _issue_entry_T_5463; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_5479 = _issue_entry_T_5478 | _issue_entry_T_5464; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_5480 = _issue_entry_T_5479 | _issue_entry_T_5465; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_5481 = _issue_entry_T_5480 | _issue_entry_T_5466; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_5482 = _issue_entry_T_5481 | _issue_entry_T_5467; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_5483 = _issue_entry_T_5482 | _issue_entry_T_5468; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_5484 = _issue_entry_T_5483 | _issue_entry_T_5469; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_5485 = _issue_entry_T_5484 | _issue_entry_T_5470; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_5486 = _issue_entry_T_5485 | _issue_entry_T_5471; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_5487 = _issue_entry_T_5486 | _issue_entry_T_5472; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_5488 = _issue_entry_T_5487 | _issue_entry_T_5473; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_5489 = _issue_entry_T_5488 | _issue_entry_T_5474; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_5490 = _issue_entry_T_5489 | _issue_entry_T_5475; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_5491 = _issue_entry_T_5490 | _issue_entry_T_5476; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_5492 = _issue_entry_T_5491 | _issue_entry_T_5477; // @[Mux.scala:30:73] assign _issue_entry_WIRE_284 = _issue_entry_T_5492; // @[Mux.scala:30:73] assign _issue_entry_WIRE_143_q = _issue_entry_WIRE_284; // @[Mux.scala:30:73] wire _issue_entry_T_5493 = issue_sel_0_1 & entries_ex_0_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_5494 = issue_sel_1_1 & entries_ex_1_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_5495 = issue_sel_2_1 & entries_ex_2_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_5496 = issue_sel_3_1 & entries_ex_3_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_5497 = issue_sel_4_1 & entries_ex_4_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_5498 = issue_sel_5_1 & entries_ex_5_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_5499 = issue_sel_6_1 & entries_ex_6_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_5500 = issue_sel_7_1 & entries_ex_7_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_5501 = issue_sel_8 & entries_ex_8_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_5502 = issue_sel_9 & entries_ex_9_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_5503 = issue_sel_10 & entries_ex_10_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_5504 = issue_sel_11 & entries_ex_11_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_5505 = issue_sel_12 & entries_ex_12_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_5506 = issue_sel_13 & entries_ex_13_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_5507 = issue_sel_14 & entries_ex_14_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_5508 = issue_sel_15 & entries_ex_15_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_5509 = _issue_entry_T_5493 | _issue_entry_T_5494; // @[Mux.scala:30:73] wire _issue_entry_T_5510 = _issue_entry_T_5509 | _issue_entry_T_5495; // @[Mux.scala:30:73] wire _issue_entry_T_5511 = _issue_entry_T_5510 | _issue_entry_T_5496; // @[Mux.scala:30:73] wire _issue_entry_T_5512 = _issue_entry_T_5511 | _issue_entry_T_5497; // @[Mux.scala:30:73] wire _issue_entry_T_5513 = _issue_entry_T_5512 | _issue_entry_T_5498; // @[Mux.scala:30:73] wire _issue_entry_T_5514 = _issue_entry_T_5513 | _issue_entry_T_5499; // @[Mux.scala:30:73] wire _issue_entry_T_5515 = _issue_entry_T_5514 | _issue_entry_T_5500; // @[Mux.scala:30:73] wire _issue_entry_T_5516 = _issue_entry_T_5515 | _issue_entry_T_5501; // @[Mux.scala:30:73] wire _issue_entry_T_5517 = _issue_entry_T_5516 | _issue_entry_T_5502; // @[Mux.scala:30:73] wire _issue_entry_T_5518 = _issue_entry_T_5517 | _issue_entry_T_5503; // @[Mux.scala:30:73] wire _issue_entry_T_5519 = _issue_entry_T_5518 | _issue_entry_T_5504; // @[Mux.scala:30:73] wire _issue_entry_T_5520 = _issue_entry_T_5519 | _issue_entry_T_5505; // @[Mux.scala:30:73] wire _issue_entry_T_5521 = _issue_entry_T_5520 | _issue_entry_T_5506; // @[Mux.scala:30:73] wire _issue_entry_T_5522 = _issue_entry_T_5521 | _issue_entry_T_5507; // @[Mux.scala:30:73] wire _issue_entry_T_5523 = _issue_entry_T_5522 | _issue_entry_T_5508; // @[Mux.scala:30:73] assign _issue_entry_WIRE_285 = _issue_entry_T_5523; // @[Mux.scala:30:73] assign issue_entry_1_valid = _issue_entry_WIRE_285; // @[Mux.scala:30:73] wire _io_issue_ex_valid_T = issue_valids_0_1 | issue_valids_1_1; // @[ReservationStation.scala:395:72, :404:38] wire _io_issue_ex_valid_T_1 = _io_issue_ex_valid_T | issue_valids_2_1; // @[ReservationStation.scala:395:72, :404:38] wire _io_issue_ex_valid_T_2 = _io_issue_ex_valid_T_1 | issue_valids_3_1; // @[ReservationStation.scala:395:72, :404:38] wire _io_issue_ex_valid_T_3 = _io_issue_ex_valid_T_2 | issue_valids_4_1; // @[ReservationStation.scala:395:72, :404:38] wire _io_issue_ex_valid_T_4 = _io_issue_ex_valid_T_3 | issue_valids_5_1; // @[ReservationStation.scala:395:72, :404:38] wire _io_issue_ex_valid_T_5 = _io_issue_ex_valid_T_4 | issue_valids_6_1; // @[ReservationStation.scala:395:72, :404:38] wire _io_issue_ex_valid_T_6 = _io_issue_ex_valid_T_5 | issue_valids_7_1; // @[ReservationStation.scala:395:72, :404:38] wire _io_issue_ex_valid_T_7 = _io_issue_ex_valid_T_6 | issue_valids_8; // @[ReservationStation.scala:395:72, :404:38] wire _io_issue_ex_valid_T_8 = _io_issue_ex_valid_T_7 | issue_valids_9; // @[ReservationStation.scala:395:72, :404:38] wire _io_issue_ex_valid_T_9 = _io_issue_ex_valid_T_8 | issue_valids_10; // @[ReservationStation.scala:395:72, :404:38] wire _io_issue_ex_valid_T_10 = _io_issue_ex_valid_T_9 | issue_valids_11; // @[ReservationStation.scala:395:72, :404:38] wire _io_issue_ex_valid_T_11 = _io_issue_ex_valid_T_10 | issue_valids_12; // @[ReservationStation.scala:395:72, :404:38] wire _io_issue_ex_valid_T_12 = _io_issue_ex_valid_T_11 | issue_valids_13; // @[ReservationStation.scala:395:72, :404:38] wire _io_issue_ex_valid_T_13 = _io_issue_ex_valid_T_12 | issue_valids_14; // @[ReservationStation.scala:395:72, :404:38] assign _io_issue_ex_valid_T_14 = _io_issue_ex_valid_T_13 | issue_valids_15; // @[ReservationStation.scala:395:72, :404:38] assign io_issue_ex_valid_0 = _io_issue_ex_valid_T_14; // @[ReservationStation.scala:26:7, :404:38] wire _T_5016 = io_issue_ex_valid_0 & io_issue_ex_ready_0; // @[ReservationStation.scala:22:20, :26:7] wire _entries_ex_0_valid_T = ~entries_ex_0_bits_complete_on_issue; // @[ReservationStation.scala:118:23, :417:22] wire _entries_ex_1_valid_T = ~entries_ex_1_bits_complete_on_issue; // @[ReservationStation.scala:118:23, :417:22] wire _entries_ex_2_valid_T = ~entries_ex_2_bits_complete_on_issue; // @[ReservationStation.scala:118:23, :417:22] wire _entries_ex_3_valid_T = ~entries_ex_3_bits_complete_on_issue; // @[ReservationStation.scala:118:23, :417:22] wire _entries_ex_4_valid_T = ~entries_ex_4_bits_complete_on_issue; // @[ReservationStation.scala:118:23, :417:22] wire _entries_ex_5_valid_T = ~entries_ex_5_bits_complete_on_issue; // @[ReservationStation.scala:118:23, :417:22] wire _entries_ex_6_valid_T = ~entries_ex_6_bits_complete_on_issue; // @[ReservationStation.scala:118:23, :417:22] wire _entries_ex_7_valid_T = ~entries_ex_7_bits_complete_on_issue; // @[ReservationStation.scala:118:23, :417:22] wire _entries_ex_8_valid_T = ~entries_ex_8_bits_complete_on_issue; // @[ReservationStation.scala:118:23, :417:22] wire _entries_ex_9_valid_T = ~entries_ex_9_bits_complete_on_issue; // @[ReservationStation.scala:118:23, :417:22] wire _entries_ex_10_valid_T = ~entries_ex_10_bits_complete_on_issue; // @[ReservationStation.scala:118:23, :417:22] wire _entries_ex_11_valid_T = ~entries_ex_11_bits_complete_on_issue; // @[ReservationStation.scala:118:23, :417:22] wire _entries_ex_12_valid_T = ~entries_ex_12_bits_complete_on_issue; // @[ReservationStation.scala:118:23, :417:22] wire _entries_ex_13_valid_T = ~entries_ex_13_bits_complete_on_issue; // @[ReservationStation.scala:118:23, :417:22] wire _entries_ex_14_valid_T = ~entries_ex_14_bits_complete_on_issue; // @[ReservationStation.scala:118:23, :417:22] wire _entries_ex_15_valid_T = ~entries_ex_15_bits_complete_on_issue; // @[ReservationStation.scala:118:23, :417:22] wire [15:0] _GEN_94 = {{entries_ex_15_bits_complete_on_issue}, {entries_ex_14_bits_complete_on_issue}, {entries_ex_13_bits_complete_on_issue}, {entries_ex_12_bits_complete_on_issue}, {entries_ex_11_bits_complete_on_issue}, {entries_ex_10_bits_complete_on_issue}, {entries_ex_9_bits_complete_on_issue}, {entries_ex_8_bits_complete_on_issue}, {entries_ex_7_bits_complete_on_issue}, {entries_ex_6_bits_complete_on_issue}, {entries_ex_5_bits_complete_on_issue}, {entries_ex_4_bits_complete_on_issue}, {entries_ex_3_bits_complete_on_issue}, {entries_ex_2_bits_complete_on_issue}, {entries_ex_1_bits_complete_on_issue}, {entries_ex_0_bits_complete_on_issue}}; // @[ReservationStation.scala:118:23, :440:71] wire [15:0] _GEN_95 = {{entries_ex_15_bits_cmd_from_conv_fsm}, {entries_ex_14_bits_cmd_from_conv_fsm}, {entries_ex_13_bits_cmd_from_conv_fsm}, {entries_ex_12_bits_cmd_from_conv_fsm}, {entries_ex_11_bits_cmd_from_conv_fsm}, {entries_ex_10_bits_cmd_from_conv_fsm}, {entries_ex_9_bits_cmd_from_conv_fsm}, {entries_ex_8_bits_cmd_from_conv_fsm}, {entries_ex_7_bits_cmd_from_conv_fsm}, {entries_ex_6_bits_cmd_from_conv_fsm}, {entries_ex_5_bits_cmd_from_conv_fsm}, {entries_ex_4_bits_cmd_from_conv_fsm}, {entries_ex_3_bits_cmd_from_conv_fsm}, {entries_ex_2_bits_cmd_from_conv_fsm}, {entries_ex_1_bits_cmd_from_conv_fsm}, {entries_ex_0_bits_cmd_from_conv_fsm}}; // @[ReservationStation.scala:118:23, :440:71] wire _GEN_96 = _GEN_94[issue_id_1] & _GEN_95[issue_id_1]; // @[OneHot.scala:32:10] wire _conv_ld_issue_completed_T_1; // @[ReservationStation.scala:440:71] assign _conv_ld_issue_completed_T_1 = _GEN_96; // @[ReservationStation.scala:440:71] wire _conv_st_issue_completed_T_1; // @[ReservationStation.scala:441:71] assign _conv_st_issue_completed_T_1 = _GEN_96; // @[ReservationStation.scala:440:71, :441:71] wire _conv_ex_issue_completed_T_1; // @[ReservationStation.scala:442:71] assign _conv_ex_issue_completed_T_1 = _GEN_96; // @[ReservationStation.scala:440:71, :442:71] assign conv_ex_issue_completed = _T_5016 & _conv_ex_issue_completed_T_1; // @[ReservationStation.scala:22:20, :140:41, :413:20, :442:{24,71}] wire [15:0] _GEN_97 = {{entries_ex_15_bits_cmd_from_matmul_fsm}, {entries_ex_14_bits_cmd_from_matmul_fsm}, {entries_ex_13_bits_cmd_from_matmul_fsm}, {entries_ex_12_bits_cmd_from_matmul_fsm}, {entries_ex_11_bits_cmd_from_matmul_fsm}, {entries_ex_10_bits_cmd_from_matmul_fsm}, {entries_ex_9_bits_cmd_from_matmul_fsm}, {entries_ex_8_bits_cmd_from_matmul_fsm}, {entries_ex_7_bits_cmd_from_matmul_fsm}, {entries_ex_6_bits_cmd_from_matmul_fsm}, {entries_ex_5_bits_cmd_from_matmul_fsm}, {entries_ex_4_bits_cmd_from_matmul_fsm}, {entries_ex_3_bits_cmd_from_matmul_fsm}, {entries_ex_2_bits_cmd_from_matmul_fsm}, {entries_ex_1_bits_cmd_from_matmul_fsm}, {entries_ex_0_bits_cmd_from_matmul_fsm}}; // @[ReservationStation.scala:118:23, :444:73] wire _GEN_98 = _GEN_94[issue_id_1] & _GEN_97[issue_id_1]; // @[OneHot.scala:32:10] wire _matmul_ld_issue_completed_T_1; // @[ReservationStation.scala:444:73] assign _matmul_ld_issue_completed_T_1 = _GEN_98; // @[ReservationStation.scala:444:73] wire _matmul_st_issue_completed_T_1; // @[ReservationStation.scala:445:73] assign _matmul_st_issue_completed_T_1 = _GEN_98; // @[ReservationStation.scala:444:73, :445:73] wire _matmul_ex_issue_completed_T_1; // @[ReservationStation.scala:446:73] assign _matmul_ex_issue_completed_T_1 = _GEN_98; // @[ReservationStation.scala:444:73, :446:73] assign matmul_ex_issue_completed = _T_5016 & _matmul_ex_issue_completed_T_1; // @[ReservationStation.scala:22:20, :148:43, :413:20, :446:{24,73}] wire _issue_valids_T_720 = entries_st_0_bits_deps_ld_0 | entries_st_0_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :119:23] wire _issue_valids_T_721 = _issue_valids_T_720 | entries_st_0_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :119:23] wire _issue_valids_T_722 = _issue_valids_T_721 | entries_st_0_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :119:23] wire _issue_valids_T_723 = _issue_valids_T_722 | entries_st_0_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :119:23] wire _issue_valids_T_724 = _issue_valids_T_723 | entries_st_0_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :119:23] wire _issue_valids_T_725 = _issue_valids_T_724 | entries_st_0_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :119:23] wire _issue_valids_T_726 = _issue_valids_T_725 | entries_st_0_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :119:23] wire _issue_valids_T_727 = entries_st_0_bits_deps_ex_0 | entries_st_0_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_728 = _issue_valids_T_727 | entries_st_0_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_729 = _issue_valids_T_728 | entries_st_0_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_730 = _issue_valids_T_729 | entries_st_0_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_731 = _issue_valids_T_730 | entries_st_0_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_732 = _issue_valids_T_731 | entries_st_0_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_733 = _issue_valids_T_732 | entries_st_0_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_734 = _issue_valids_T_733 | entries_st_0_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_735 = _issue_valids_T_734 | entries_st_0_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_736 = _issue_valids_T_735 | entries_st_0_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_737 = _issue_valids_T_736 | entries_st_0_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_738 = _issue_valids_T_737 | entries_st_0_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_739 = _issue_valids_T_738 | entries_st_0_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_740 = _issue_valids_T_739 | entries_st_0_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_741 = _issue_valids_T_740 | entries_st_0_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_742 = _issue_valids_T_726 | _issue_valids_T_741; // @[ReservationStation.scala:107:{58,64,84}] wire _issue_valids_T_743 = entries_st_0_bits_deps_st_0 | entries_st_0_bits_deps_st_1; // @[ReservationStation.scala:107:110, :119:23] wire _issue_valids_T_744 = _issue_valids_T_743 | entries_st_0_bits_deps_st_2; // @[ReservationStation.scala:107:110, :119:23] wire _issue_valids_T_745 = _issue_valids_T_744 | entries_st_0_bits_deps_st_3; // @[ReservationStation.scala:107:110, :119:23] wire _issue_valids_T_746 = _issue_valids_T_742 | _issue_valids_T_745; // @[ReservationStation.scala:107:{64,90,110}] wire _issue_valids_T_747 = ~_issue_valids_T_746; // @[ReservationStation.scala:107:{39,90}] wire _issue_valids_T_748 = entries_st_0_valid & _issue_valids_T_747; // @[ReservationStation.scala:107:39, :119:23, :395:54] wire _issue_valids_T_749 = ~entries_st_0_bits_issued; // @[ReservationStation.scala:119:23, :395:75] wire issue_valids_0_2 = _issue_valids_T_748 & _issue_valids_T_749; // @[ReservationStation.scala:395:{54,72,75}] wire _issue_valids_T_750 = entries_st_1_bits_deps_ld_0 | entries_st_1_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :119:23] wire _issue_valids_T_751 = _issue_valids_T_750 | entries_st_1_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :119:23] wire _issue_valids_T_752 = _issue_valids_T_751 | entries_st_1_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :119:23] wire _issue_valids_T_753 = _issue_valids_T_752 | entries_st_1_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :119:23] wire _issue_valids_T_754 = _issue_valids_T_753 | entries_st_1_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :119:23] wire _issue_valids_T_755 = _issue_valids_T_754 | entries_st_1_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :119:23] wire _issue_valids_T_756 = _issue_valids_T_755 | entries_st_1_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :119:23] wire _issue_valids_T_757 = entries_st_1_bits_deps_ex_0 | entries_st_1_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_758 = _issue_valids_T_757 | entries_st_1_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_759 = _issue_valids_T_758 | entries_st_1_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_760 = _issue_valids_T_759 | entries_st_1_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_761 = _issue_valids_T_760 | entries_st_1_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_762 = _issue_valids_T_761 | entries_st_1_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_763 = _issue_valids_T_762 | entries_st_1_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_764 = _issue_valids_T_763 | entries_st_1_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_765 = _issue_valids_T_764 | entries_st_1_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_766 = _issue_valids_T_765 | entries_st_1_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_767 = _issue_valids_T_766 | entries_st_1_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_768 = _issue_valids_T_767 | entries_st_1_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_769 = _issue_valids_T_768 | entries_st_1_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_770 = _issue_valids_T_769 | entries_st_1_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_771 = _issue_valids_T_770 | entries_st_1_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_772 = _issue_valids_T_756 | _issue_valids_T_771; // @[ReservationStation.scala:107:{58,64,84}] wire _issue_valids_T_773 = entries_st_1_bits_deps_st_0 | entries_st_1_bits_deps_st_1; // @[ReservationStation.scala:107:110, :119:23] wire _issue_valids_T_774 = _issue_valids_T_773 | entries_st_1_bits_deps_st_2; // @[ReservationStation.scala:107:110, :119:23] wire _issue_valids_T_775 = _issue_valids_T_774 | entries_st_1_bits_deps_st_3; // @[ReservationStation.scala:107:110, :119:23] wire _issue_valids_T_776 = _issue_valids_T_772 | _issue_valids_T_775; // @[ReservationStation.scala:107:{64,90,110}] wire _issue_valids_T_777 = ~_issue_valids_T_776; // @[ReservationStation.scala:107:{39,90}] wire _issue_valids_T_778 = entries_st_1_valid & _issue_valids_T_777; // @[ReservationStation.scala:107:39, :119:23, :395:54] wire _issue_valids_T_779 = ~entries_st_1_bits_issued; // @[ReservationStation.scala:119:23, :395:75] wire issue_valids_1_2 = _issue_valids_T_778 & _issue_valids_T_779; // @[ReservationStation.scala:395:{54,72,75}] wire _issue_valids_T_780 = entries_st_2_bits_deps_ld_0 | entries_st_2_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :119:23] wire _issue_valids_T_781 = _issue_valids_T_780 | entries_st_2_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :119:23] wire _issue_valids_T_782 = _issue_valids_T_781 | entries_st_2_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :119:23] wire _issue_valids_T_783 = _issue_valids_T_782 | entries_st_2_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :119:23] wire _issue_valids_T_784 = _issue_valids_T_783 | entries_st_2_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :119:23] wire _issue_valids_T_785 = _issue_valids_T_784 | entries_st_2_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :119:23] wire _issue_valids_T_786 = _issue_valids_T_785 | entries_st_2_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :119:23] wire _issue_valids_T_787 = entries_st_2_bits_deps_ex_0 | entries_st_2_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_788 = _issue_valids_T_787 | entries_st_2_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_789 = _issue_valids_T_788 | entries_st_2_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_790 = _issue_valids_T_789 | entries_st_2_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_791 = _issue_valids_T_790 | entries_st_2_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_792 = _issue_valids_T_791 | entries_st_2_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_793 = _issue_valids_T_792 | entries_st_2_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_794 = _issue_valids_T_793 | entries_st_2_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_795 = _issue_valids_T_794 | entries_st_2_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_796 = _issue_valids_T_795 | entries_st_2_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_797 = _issue_valids_T_796 | entries_st_2_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_798 = _issue_valids_T_797 | entries_st_2_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_799 = _issue_valids_T_798 | entries_st_2_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_800 = _issue_valids_T_799 | entries_st_2_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_801 = _issue_valids_T_800 | entries_st_2_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_802 = _issue_valids_T_786 | _issue_valids_T_801; // @[ReservationStation.scala:107:{58,64,84}] wire _issue_valids_T_803 = entries_st_2_bits_deps_st_0 | entries_st_2_bits_deps_st_1; // @[ReservationStation.scala:107:110, :119:23] wire _issue_valids_T_804 = _issue_valids_T_803 | entries_st_2_bits_deps_st_2; // @[ReservationStation.scala:107:110, :119:23] wire _issue_valids_T_805 = _issue_valids_T_804 | entries_st_2_bits_deps_st_3; // @[ReservationStation.scala:107:110, :119:23] wire _issue_valids_T_806 = _issue_valids_T_802 | _issue_valids_T_805; // @[ReservationStation.scala:107:{64,90,110}] wire _issue_valids_T_807 = ~_issue_valids_T_806; // @[ReservationStation.scala:107:{39,90}] wire _issue_valids_T_808 = entries_st_2_valid & _issue_valids_T_807; // @[ReservationStation.scala:107:39, :119:23, :395:54] wire _issue_valids_T_809 = ~entries_st_2_bits_issued; // @[ReservationStation.scala:119:23, :395:75] wire issue_valids_2_2 = _issue_valids_T_808 & _issue_valids_T_809; // @[ReservationStation.scala:395:{54,72,75}] wire _issue_valids_T_810 = entries_st_3_bits_deps_ld_0 | entries_st_3_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :119:23] wire _issue_valids_T_811 = _issue_valids_T_810 | entries_st_3_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :119:23] wire _issue_valids_T_812 = _issue_valids_T_811 | entries_st_3_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :119:23] wire _issue_valids_T_813 = _issue_valids_T_812 | entries_st_3_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :119:23] wire _issue_valids_T_814 = _issue_valids_T_813 | entries_st_3_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :119:23] wire _issue_valids_T_815 = _issue_valids_T_814 | entries_st_3_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :119:23] wire _issue_valids_T_816 = _issue_valids_T_815 | entries_st_3_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :119:23] wire _issue_valids_T_817 = entries_st_3_bits_deps_ex_0 | entries_st_3_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_818 = _issue_valids_T_817 | entries_st_3_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_819 = _issue_valids_T_818 | entries_st_3_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_820 = _issue_valids_T_819 | entries_st_3_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_821 = _issue_valids_T_820 | entries_st_3_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_822 = _issue_valids_T_821 | entries_st_3_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_823 = _issue_valids_T_822 | entries_st_3_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_824 = _issue_valids_T_823 | entries_st_3_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_825 = _issue_valids_T_824 | entries_st_3_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_826 = _issue_valids_T_825 | entries_st_3_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_827 = _issue_valids_T_826 | entries_st_3_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_828 = _issue_valids_T_827 | entries_st_3_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_829 = _issue_valids_T_828 | entries_st_3_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_830 = _issue_valids_T_829 | entries_st_3_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_831 = _issue_valids_T_830 | entries_st_3_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :119:23] wire _issue_valids_T_832 = _issue_valids_T_816 | _issue_valids_T_831; // @[ReservationStation.scala:107:{58,64,84}] wire _issue_valids_T_833 = entries_st_3_bits_deps_st_0 | entries_st_3_bits_deps_st_1; // @[ReservationStation.scala:107:110, :119:23] wire _issue_valids_T_834 = _issue_valids_T_833 | entries_st_3_bits_deps_st_2; // @[ReservationStation.scala:107:110, :119:23] wire _issue_valids_T_835 = _issue_valids_T_834 | entries_st_3_bits_deps_st_3; // @[ReservationStation.scala:107:110, :119:23] wire _issue_valids_T_836 = _issue_valids_T_832 | _issue_valids_T_835; // @[ReservationStation.scala:107:{64,90,110}] wire _issue_valids_T_837 = ~_issue_valids_T_836; // @[ReservationStation.scala:107:{39,90}] wire _issue_valids_T_838 = entries_st_3_valid & _issue_valids_T_837; // @[ReservationStation.scala:107:39, :119:23, :395:54] wire _issue_valids_T_839 = ~entries_st_3_bits_issued; // @[ReservationStation.scala:119:23, :395:75] wire issue_valids_3_2 = _issue_valids_T_838 & _issue_valids_T_839; // @[ReservationStation.scala:395:{54,72,75}] wire [3:0] _issue_sel_enc_T_22 = {issue_valids_3_2, 3'h0}; // @[Mux.scala:50:70] wire [3:0] _issue_sel_enc_T_23 = issue_valids_2_2 ? 4'h4 : _issue_sel_enc_T_22; // @[Mux.scala:50:70] wire [3:0] _issue_sel_enc_T_24 = issue_valids_1_2 ? 4'h2 : _issue_sel_enc_T_23; // @[Mux.scala:50:70] wire [3:0] issue_sel_enc_2 = issue_valids_0_2 ? 4'h1 : _issue_sel_enc_T_24; // @[Mux.scala:50:70] wire issue_sel_0_2 = issue_sel_enc_2[0]; // @[OneHot.scala:83:30] wire issue_sel_1_2 = issue_sel_enc_2[1]; // @[OneHot.scala:83:30] wire issue_sel_2_2 = issue_sel_enc_2[2]; // @[OneHot.scala:83:30] wire issue_sel_3_2 = issue_sel_enc_2[3]; // @[OneHot.scala:83:30] wire [1:0] issue_id_lo_7 = {issue_sel_1_2, issue_sel_0_2}; // @[OneHot.scala:21:45, :83:30] wire [1:0] issue_id_hi_7 = {issue_sel_3_2, issue_sel_2_2}; // @[OneHot.scala:21:45, :83:30] wire [3:0] _issue_id_T_17 = {issue_id_hi_7, issue_id_lo_7}; // @[OneHot.scala:21:45] wire [1:0] issue_id_hi_8 = _issue_id_T_17[3:2]; // @[OneHot.scala:21:45, :30:18] wire [1:0] issue_id_lo_8 = _issue_id_T_17[1:0]; // @[OneHot.scala:21:45, :31:18] wire _issue_id_T_18 = |issue_id_hi_8; // @[OneHot.scala:30:18, :32:14] wire [1:0] _issue_id_T_19 = issue_id_hi_8 | issue_id_lo_8; // @[OneHot.scala:30:18, :31:18, :32:28] wire _issue_id_T_20 = _issue_id_T_19[1]; // @[OneHot.scala:32:28] wire [1:0] issue_id_2 = {_issue_id_T_18, _issue_id_T_20}; // @[OneHot.scala:32:{10,14}] wire [3:0] _global_issue_id_T_1 = {2'h0, issue_id_2}; // @[OneHot.scala:32:10] assign global_issue_id_2 = {2'h2, _global_issue_id_T_1}; // @[ReservationStation.scala:398:{30,53}] assign io_issue_st_rob_id_0 = global_issue_id_2; // @[ReservationStation.scala:26:7, :398:30] wire _issue_entry_WIRE_428; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_286_q; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_is_config; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_opa_valid; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_opa_bits_start_is_acc_addr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_opa_bits_start_accumulate; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_opa_bits_start_read_full_acc_row; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_286_opa_bits_start_norm_cmd; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_286_opa_bits_start_garbage; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_opa_bits_start_garbage_bit; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_286_opa_bits_start_data; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_opa_bits_end_is_acc_addr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_opa_bits_end_accumulate; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_opa_bits_end_read_full_acc_row; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_286_opa_bits_end_norm_cmd; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_286_opa_bits_end_garbage; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_opa_bits_end_garbage_bit; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_286_opa_bits_end_data; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_opa_bits_wraps_around; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_opa_is_dst; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_issued; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_complete_on_issue; // @[Mux.scala:30:73] wire [6:0] _issue_entry_WIRE_286_cmd_cmd_inst_funct; // @[Mux.scala:30:73] assign io_issue_st_cmd_cmd_inst_funct_0 = issue_entry_2_bits_cmd_cmd_inst_funct; // @[Mux.scala:30:73] wire [4:0] _issue_entry_WIRE_286_cmd_cmd_inst_rs2; // @[Mux.scala:30:73] assign io_issue_st_cmd_cmd_inst_rs2_0 = issue_entry_2_bits_cmd_cmd_inst_rs2; // @[Mux.scala:30:73] wire [4:0] _issue_entry_WIRE_286_cmd_cmd_inst_rs1; // @[Mux.scala:30:73] assign io_issue_st_cmd_cmd_inst_rs1_0 = issue_entry_2_bits_cmd_cmd_inst_rs1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_cmd_cmd_inst_xd; // @[Mux.scala:30:73] assign io_issue_st_cmd_cmd_inst_xd_0 = issue_entry_2_bits_cmd_cmd_inst_xd; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_cmd_cmd_inst_xs1; // @[Mux.scala:30:73] assign io_issue_st_cmd_cmd_inst_xs1_0 = issue_entry_2_bits_cmd_cmd_inst_xs1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_cmd_cmd_inst_xs2; // @[Mux.scala:30:73] assign io_issue_st_cmd_cmd_inst_xs2_0 = issue_entry_2_bits_cmd_cmd_inst_xs2; // @[Mux.scala:30:73] wire [4:0] _issue_entry_WIRE_286_cmd_cmd_inst_rd; // @[Mux.scala:30:73] assign io_issue_st_cmd_cmd_inst_rd_0 = issue_entry_2_bits_cmd_cmd_inst_rd; // @[Mux.scala:30:73] wire [6:0] _issue_entry_WIRE_286_cmd_cmd_inst_opcode; // @[Mux.scala:30:73] assign io_issue_st_cmd_cmd_inst_opcode_0 = issue_entry_2_bits_cmd_cmd_inst_opcode; // @[Mux.scala:30:73] wire [63:0] _issue_entry_WIRE_286_cmd_cmd_rs1; // @[Mux.scala:30:73] assign io_issue_st_cmd_cmd_rs1_0 = issue_entry_2_bits_cmd_cmd_rs1; // @[Mux.scala:30:73] wire [63:0] _issue_entry_WIRE_286_cmd_cmd_rs2; // @[Mux.scala:30:73] assign io_issue_st_cmd_cmd_rs2_0 = issue_entry_2_bits_cmd_cmd_rs2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_cmd_cmd_status_debug; // @[Mux.scala:30:73] assign io_issue_st_cmd_cmd_status_debug_0 = issue_entry_2_bits_cmd_cmd_status_debug; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_cmd_cmd_status_cease; // @[Mux.scala:30:73] assign io_issue_st_cmd_cmd_status_cease_0 = issue_entry_2_bits_cmd_cmd_status_cease; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_cmd_cmd_status_wfi; // @[Mux.scala:30:73] assign io_issue_st_cmd_cmd_status_wfi_0 = issue_entry_2_bits_cmd_cmd_status_wfi; // @[Mux.scala:30:73] wire [31:0] _issue_entry_WIRE_286_cmd_cmd_status_isa; // @[Mux.scala:30:73] assign io_issue_st_cmd_cmd_status_isa_0 = issue_entry_2_bits_cmd_cmd_status_isa; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_286_cmd_cmd_status_dprv; // @[Mux.scala:30:73] assign io_issue_st_cmd_cmd_status_dprv_0 = issue_entry_2_bits_cmd_cmd_status_dprv; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_cmd_cmd_status_dv; // @[Mux.scala:30:73] assign io_issue_st_cmd_cmd_status_dv_0 = issue_entry_2_bits_cmd_cmd_status_dv; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_286_cmd_cmd_status_prv; // @[Mux.scala:30:73] assign io_issue_st_cmd_cmd_status_prv_0 = issue_entry_2_bits_cmd_cmd_status_prv; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_cmd_cmd_status_v; // @[Mux.scala:30:73] assign io_issue_st_cmd_cmd_status_v_0 = issue_entry_2_bits_cmd_cmd_status_v; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_cmd_cmd_status_sd; // @[Mux.scala:30:73] assign io_issue_st_cmd_cmd_status_sd_0 = issue_entry_2_bits_cmd_cmd_status_sd; // @[Mux.scala:30:73] wire [22:0] _issue_entry_WIRE_286_cmd_cmd_status_zero2; // @[Mux.scala:30:73] assign io_issue_st_cmd_cmd_status_zero2_0 = issue_entry_2_bits_cmd_cmd_status_zero2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_cmd_cmd_status_mpv; // @[Mux.scala:30:73] assign io_issue_st_cmd_cmd_status_mpv_0 = issue_entry_2_bits_cmd_cmd_status_mpv; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_cmd_cmd_status_gva; // @[Mux.scala:30:73] assign io_issue_st_cmd_cmd_status_gva_0 = issue_entry_2_bits_cmd_cmd_status_gva; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_cmd_cmd_status_mbe; // @[Mux.scala:30:73] assign io_issue_st_cmd_cmd_status_mbe_0 = issue_entry_2_bits_cmd_cmd_status_mbe; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_cmd_cmd_status_sbe; // @[Mux.scala:30:73] assign io_issue_st_cmd_cmd_status_sbe_0 = issue_entry_2_bits_cmd_cmd_status_sbe; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_286_cmd_cmd_status_sxl; // @[Mux.scala:30:73] assign io_issue_st_cmd_cmd_status_sxl_0 = issue_entry_2_bits_cmd_cmd_status_sxl; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_286_cmd_cmd_status_uxl; // @[Mux.scala:30:73] assign io_issue_st_cmd_cmd_status_uxl_0 = issue_entry_2_bits_cmd_cmd_status_uxl; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_cmd_cmd_status_sd_rv32; // @[Mux.scala:30:73] assign io_issue_st_cmd_cmd_status_sd_rv32_0 = issue_entry_2_bits_cmd_cmd_status_sd_rv32; // @[Mux.scala:30:73] wire [7:0] _issue_entry_WIRE_286_cmd_cmd_status_zero1; // @[Mux.scala:30:73] assign io_issue_st_cmd_cmd_status_zero1_0 = issue_entry_2_bits_cmd_cmd_status_zero1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_cmd_cmd_status_tsr; // @[Mux.scala:30:73] assign io_issue_st_cmd_cmd_status_tsr_0 = issue_entry_2_bits_cmd_cmd_status_tsr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_cmd_cmd_status_tw; // @[Mux.scala:30:73] assign io_issue_st_cmd_cmd_status_tw_0 = issue_entry_2_bits_cmd_cmd_status_tw; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_cmd_cmd_status_tvm; // @[Mux.scala:30:73] assign io_issue_st_cmd_cmd_status_tvm_0 = issue_entry_2_bits_cmd_cmd_status_tvm; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_cmd_cmd_status_mxr; // @[Mux.scala:30:73] assign io_issue_st_cmd_cmd_status_mxr_0 = issue_entry_2_bits_cmd_cmd_status_mxr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_cmd_cmd_status_sum; // @[Mux.scala:30:73] assign io_issue_st_cmd_cmd_status_sum_0 = issue_entry_2_bits_cmd_cmd_status_sum; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_cmd_cmd_status_mprv; // @[Mux.scala:30:73] assign io_issue_st_cmd_cmd_status_mprv_0 = issue_entry_2_bits_cmd_cmd_status_mprv; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_286_cmd_cmd_status_xs; // @[Mux.scala:30:73] assign io_issue_st_cmd_cmd_status_xs_0 = issue_entry_2_bits_cmd_cmd_status_xs; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_286_cmd_cmd_status_fs; // @[Mux.scala:30:73] assign io_issue_st_cmd_cmd_status_fs_0 = issue_entry_2_bits_cmd_cmd_status_fs; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_286_cmd_cmd_status_mpp; // @[Mux.scala:30:73] assign io_issue_st_cmd_cmd_status_mpp_0 = issue_entry_2_bits_cmd_cmd_status_mpp; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_286_cmd_cmd_status_vs; // @[Mux.scala:30:73] assign io_issue_st_cmd_cmd_status_vs_0 = issue_entry_2_bits_cmd_cmd_status_vs; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_cmd_cmd_status_spp; // @[Mux.scala:30:73] assign io_issue_st_cmd_cmd_status_spp_0 = issue_entry_2_bits_cmd_cmd_status_spp; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_cmd_cmd_status_mpie; // @[Mux.scala:30:73] assign io_issue_st_cmd_cmd_status_mpie_0 = issue_entry_2_bits_cmd_cmd_status_mpie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_cmd_cmd_status_ube; // @[Mux.scala:30:73] assign io_issue_st_cmd_cmd_status_ube_0 = issue_entry_2_bits_cmd_cmd_status_ube; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_cmd_cmd_status_spie; // @[Mux.scala:30:73] assign io_issue_st_cmd_cmd_status_spie_0 = issue_entry_2_bits_cmd_cmd_status_spie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_cmd_cmd_status_upie; // @[Mux.scala:30:73] assign io_issue_st_cmd_cmd_status_upie_0 = issue_entry_2_bits_cmd_cmd_status_upie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_cmd_cmd_status_mie; // @[Mux.scala:30:73] assign io_issue_st_cmd_cmd_status_mie_0 = issue_entry_2_bits_cmd_cmd_status_mie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_cmd_cmd_status_hie; // @[Mux.scala:30:73] assign io_issue_st_cmd_cmd_status_hie_0 = issue_entry_2_bits_cmd_cmd_status_hie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_cmd_cmd_status_sie; // @[Mux.scala:30:73] assign io_issue_st_cmd_cmd_status_sie_0 = issue_entry_2_bits_cmd_cmd_status_sie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_cmd_cmd_status_uie; // @[Mux.scala:30:73] assign io_issue_st_cmd_cmd_status_uie_0 = issue_entry_2_bits_cmd_cmd_status_uie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_cmd_rob_id_valid; // @[Mux.scala:30:73] assign io_issue_st_cmd_rob_id_valid = issue_entry_2_bits_cmd_rob_id_valid; // @[Mux.scala:30:73] wire [5:0] _issue_entry_WIRE_286_cmd_rob_id_bits; // @[Mux.scala:30:73] assign io_issue_st_cmd_rob_id_bits = issue_entry_2_bits_cmd_rob_id_bits; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_cmd_from_matmul_fsm; // @[Mux.scala:30:73] assign io_issue_st_cmd_from_matmul_fsm_0 = issue_entry_2_bits_cmd_from_matmul_fsm; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_cmd_from_conv_fsm; // @[Mux.scala:30:73] assign io_issue_st_cmd_from_conv_fsm_0 = issue_entry_2_bits_cmd_from_conv_fsm; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_deps_ld_0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_deps_ld_1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_deps_ld_2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_deps_ld_3; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_deps_ld_4; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_deps_ld_5; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_deps_ld_6; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_deps_ld_7; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_deps_ex_0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_deps_ex_1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_deps_ex_2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_deps_ex_3; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_deps_ex_4; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_deps_ex_5; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_deps_ex_6; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_deps_ex_7; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_deps_ex_8; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_deps_ex_9; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_deps_ex_10; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_deps_ex_11; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_deps_ex_12; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_deps_ex_13; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_deps_ex_14; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_deps_ex_15; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_deps_st_0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_deps_st_1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_deps_st_2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_286_deps_st_3; // @[Mux.scala:30:73] wire [31:0] _issue_entry_WIRE_286_allocated_at; // @[Mux.scala:30:73] wire issue_entry_2_bits_opa_bits_start_is_acc_addr; // @[Mux.scala:30:73] wire issue_entry_2_bits_opa_bits_start_accumulate; // @[Mux.scala:30:73] wire issue_entry_2_bits_opa_bits_start_read_full_acc_row; // @[Mux.scala:30:73] wire [2:0] issue_entry_2_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73] wire [10:0] issue_entry_2_bits_opa_bits_start_garbage; // @[Mux.scala:30:73] wire issue_entry_2_bits_opa_bits_start_garbage_bit; // @[Mux.scala:30:73] wire [13:0] issue_entry_2_bits_opa_bits_start_data; // @[Mux.scala:30:73] wire issue_entry_2_bits_opa_bits_end_is_acc_addr; // @[Mux.scala:30:73] wire issue_entry_2_bits_opa_bits_end_accumulate; // @[Mux.scala:30:73] wire issue_entry_2_bits_opa_bits_end_read_full_acc_row; // @[Mux.scala:30:73] wire [2:0] issue_entry_2_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73] wire [10:0] issue_entry_2_bits_opa_bits_end_garbage; // @[Mux.scala:30:73] wire issue_entry_2_bits_opa_bits_end_garbage_bit; // @[Mux.scala:30:73] wire [13:0] issue_entry_2_bits_opa_bits_end_data; // @[Mux.scala:30:73] wire issue_entry_2_bits_opa_bits_wraps_around; // @[Mux.scala:30:73] wire issue_entry_2_bits_opa_valid; // @[Mux.scala:30:73] wire issue_entry_2_bits_deps_ld_0; // @[Mux.scala:30:73] wire issue_entry_2_bits_deps_ld_1; // @[Mux.scala:30:73] wire issue_entry_2_bits_deps_ld_2; // @[Mux.scala:30:73] wire issue_entry_2_bits_deps_ld_3; // @[Mux.scala:30:73] wire issue_entry_2_bits_deps_ld_4; // @[Mux.scala:30:73] wire issue_entry_2_bits_deps_ld_5; // @[Mux.scala:30:73] wire issue_entry_2_bits_deps_ld_6; // @[Mux.scala:30:73] wire issue_entry_2_bits_deps_ld_7; // @[Mux.scala:30:73] wire issue_entry_2_bits_deps_ex_0; // @[Mux.scala:30:73] wire issue_entry_2_bits_deps_ex_1; // @[Mux.scala:30:73] wire issue_entry_2_bits_deps_ex_2; // @[Mux.scala:30:73] wire issue_entry_2_bits_deps_ex_3; // @[Mux.scala:30:73] wire issue_entry_2_bits_deps_ex_4; // @[Mux.scala:30:73] wire issue_entry_2_bits_deps_ex_5; // @[Mux.scala:30:73] wire issue_entry_2_bits_deps_ex_6; // @[Mux.scala:30:73] wire issue_entry_2_bits_deps_ex_7; // @[Mux.scala:30:73] wire issue_entry_2_bits_deps_ex_8; // @[Mux.scala:30:73] wire issue_entry_2_bits_deps_ex_9; // @[Mux.scala:30:73] wire issue_entry_2_bits_deps_ex_10; // @[Mux.scala:30:73] wire issue_entry_2_bits_deps_ex_11; // @[Mux.scala:30:73] wire issue_entry_2_bits_deps_ex_12; // @[Mux.scala:30:73] wire issue_entry_2_bits_deps_ex_13; // @[Mux.scala:30:73] wire issue_entry_2_bits_deps_ex_14; // @[Mux.scala:30:73] wire issue_entry_2_bits_deps_ex_15; // @[Mux.scala:30:73] wire issue_entry_2_bits_deps_st_0; // @[Mux.scala:30:73] wire issue_entry_2_bits_deps_st_1; // @[Mux.scala:30:73] wire issue_entry_2_bits_deps_st_2; // @[Mux.scala:30:73] wire issue_entry_2_bits_deps_st_3; // @[Mux.scala:30:73] wire [1:0] issue_entry_2_bits_q; // @[Mux.scala:30:73] wire issue_entry_2_bits_is_config; // @[Mux.scala:30:73] wire issue_entry_2_bits_opa_is_dst; // @[Mux.scala:30:73] wire issue_entry_2_bits_issued; // @[Mux.scala:30:73] wire issue_entry_2_bits_complete_on_issue; // @[Mux.scala:30:73] wire [31:0] issue_entry_2_bits_allocated_at; // @[Mux.scala:30:73] wire issue_entry_2_valid; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_427; // @[Mux.scala:30:73] assign issue_entry_2_bits_q = _issue_entry_WIRE_286_q; // @[Mux.scala:30:73] wire _issue_entry_WIRE_426; // @[Mux.scala:30:73] assign issue_entry_2_bits_is_config = _issue_entry_WIRE_286_is_config; // @[Mux.scala:30:73] wire _issue_entry_WIRE_402_valid; // @[Mux.scala:30:73] assign issue_entry_2_bits_opa_valid = _issue_entry_WIRE_286_opa_valid; // @[Mux.scala:30:73] wire _issue_entry_WIRE_402_bits_start_is_acc_addr; // @[Mux.scala:30:73] assign issue_entry_2_bits_opa_bits_start_is_acc_addr = _issue_entry_WIRE_286_opa_bits_start_is_acc_addr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_402_bits_start_accumulate; // @[Mux.scala:30:73] assign issue_entry_2_bits_opa_bits_start_accumulate = _issue_entry_WIRE_286_opa_bits_start_accumulate; // @[Mux.scala:30:73] wire _issue_entry_WIRE_402_bits_start_read_full_acc_row; // @[Mux.scala:30:73] assign issue_entry_2_bits_opa_bits_start_read_full_acc_row = _issue_entry_WIRE_286_opa_bits_start_read_full_acc_row; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_402_bits_start_norm_cmd; // @[Mux.scala:30:73] assign issue_entry_2_bits_opa_bits_start_norm_cmd = _issue_entry_WIRE_286_opa_bits_start_norm_cmd; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_402_bits_start_garbage; // @[Mux.scala:30:73] assign issue_entry_2_bits_opa_bits_start_garbage = _issue_entry_WIRE_286_opa_bits_start_garbage; // @[Mux.scala:30:73] wire _issue_entry_WIRE_402_bits_start_garbage_bit; // @[Mux.scala:30:73] assign issue_entry_2_bits_opa_bits_start_garbage_bit = _issue_entry_WIRE_286_opa_bits_start_garbage_bit; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_402_bits_start_data; // @[Mux.scala:30:73] assign issue_entry_2_bits_opa_bits_start_data = _issue_entry_WIRE_286_opa_bits_start_data; // @[Mux.scala:30:73] wire _issue_entry_WIRE_402_bits_end_is_acc_addr; // @[Mux.scala:30:73] assign issue_entry_2_bits_opa_bits_end_is_acc_addr = _issue_entry_WIRE_286_opa_bits_end_is_acc_addr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_402_bits_end_accumulate; // @[Mux.scala:30:73] assign issue_entry_2_bits_opa_bits_end_accumulate = _issue_entry_WIRE_286_opa_bits_end_accumulate; // @[Mux.scala:30:73] wire _issue_entry_WIRE_402_bits_end_read_full_acc_row; // @[Mux.scala:30:73] assign issue_entry_2_bits_opa_bits_end_read_full_acc_row = _issue_entry_WIRE_286_opa_bits_end_read_full_acc_row; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_402_bits_end_norm_cmd; // @[Mux.scala:30:73] assign issue_entry_2_bits_opa_bits_end_norm_cmd = _issue_entry_WIRE_286_opa_bits_end_norm_cmd; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_402_bits_end_garbage; // @[Mux.scala:30:73] assign issue_entry_2_bits_opa_bits_end_garbage = _issue_entry_WIRE_286_opa_bits_end_garbage; // @[Mux.scala:30:73] wire _issue_entry_WIRE_402_bits_end_garbage_bit; // @[Mux.scala:30:73] assign issue_entry_2_bits_opa_bits_end_garbage_bit = _issue_entry_WIRE_286_opa_bits_end_garbage_bit; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_402_bits_end_data; // @[Mux.scala:30:73] assign issue_entry_2_bits_opa_bits_end_data = _issue_entry_WIRE_286_opa_bits_end_data; // @[Mux.scala:30:73] wire _issue_entry_WIRE_402_bits_wraps_around; // @[Mux.scala:30:73] assign issue_entry_2_bits_opa_bits_wraps_around = _issue_entry_WIRE_286_opa_bits_wraps_around; // @[Mux.scala:30:73] wire _issue_entry_WIRE_401; // @[Mux.scala:30:73] assign issue_entry_2_bits_opa_is_dst = _issue_entry_WIRE_286_opa_is_dst; // @[Mux.scala:30:73] wire _issue_entry_WIRE_376; // @[Mux.scala:30:73] assign issue_entry_2_bits_issued = _issue_entry_WIRE_286_issued; // @[Mux.scala:30:73] wire _issue_entry_WIRE_375; // @[Mux.scala:30:73] assign issue_entry_2_bits_complete_on_issue = _issue_entry_WIRE_286_complete_on_issue; // @[Mux.scala:30:73] wire [6:0] _issue_entry_WIRE_319_cmd_inst_funct; // @[Mux.scala:30:73] assign issue_entry_2_bits_cmd_cmd_inst_funct = _issue_entry_WIRE_286_cmd_cmd_inst_funct; // @[Mux.scala:30:73] wire [4:0] _issue_entry_WIRE_319_cmd_inst_rs2; // @[Mux.scala:30:73] assign issue_entry_2_bits_cmd_cmd_inst_rs2 = _issue_entry_WIRE_286_cmd_cmd_inst_rs2; // @[Mux.scala:30:73] wire [4:0] _issue_entry_WIRE_319_cmd_inst_rs1; // @[Mux.scala:30:73] assign issue_entry_2_bits_cmd_cmd_inst_rs1 = _issue_entry_WIRE_286_cmd_cmd_inst_rs1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_319_cmd_inst_xd; // @[Mux.scala:30:73] assign issue_entry_2_bits_cmd_cmd_inst_xd = _issue_entry_WIRE_286_cmd_cmd_inst_xd; // @[Mux.scala:30:73] wire _issue_entry_WIRE_319_cmd_inst_xs1; // @[Mux.scala:30:73] assign issue_entry_2_bits_cmd_cmd_inst_xs1 = _issue_entry_WIRE_286_cmd_cmd_inst_xs1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_319_cmd_inst_xs2; // @[Mux.scala:30:73] assign issue_entry_2_bits_cmd_cmd_inst_xs2 = _issue_entry_WIRE_286_cmd_cmd_inst_xs2; // @[Mux.scala:30:73] wire [4:0] _issue_entry_WIRE_319_cmd_inst_rd; // @[Mux.scala:30:73] assign issue_entry_2_bits_cmd_cmd_inst_rd = _issue_entry_WIRE_286_cmd_cmd_inst_rd; // @[Mux.scala:30:73] wire [6:0] _issue_entry_WIRE_319_cmd_inst_opcode; // @[Mux.scala:30:73] assign issue_entry_2_bits_cmd_cmd_inst_opcode = _issue_entry_WIRE_286_cmd_cmd_inst_opcode; // @[Mux.scala:30:73] wire [63:0] _issue_entry_WIRE_319_cmd_rs1; // @[Mux.scala:30:73] assign issue_entry_2_bits_cmd_cmd_rs1 = _issue_entry_WIRE_286_cmd_cmd_rs1; // @[Mux.scala:30:73] wire [63:0] _issue_entry_WIRE_319_cmd_rs2; // @[Mux.scala:30:73] assign issue_entry_2_bits_cmd_cmd_rs2 = _issue_entry_WIRE_286_cmd_cmd_rs2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_319_cmd_status_debug; // @[Mux.scala:30:73] assign issue_entry_2_bits_cmd_cmd_status_debug = _issue_entry_WIRE_286_cmd_cmd_status_debug; // @[Mux.scala:30:73] wire _issue_entry_WIRE_319_cmd_status_cease; // @[Mux.scala:30:73] assign issue_entry_2_bits_cmd_cmd_status_cease = _issue_entry_WIRE_286_cmd_cmd_status_cease; // @[Mux.scala:30:73] wire _issue_entry_WIRE_319_cmd_status_wfi; // @[Mux.scala:30:73] assign issue_entry_2_bits_cmd_cmd_status_wfi = _issue_entry_WIRE_286_cmd_cmd_status_wfi; // @[Mux.scala:30:73] wire [31:0] _issue_entry_WIRE_319_cmd_status_isa; // @[Mux.scala:30:73] assign issue_entry_2_bits_cmd_cmd_status_isa = _issue_entry_WIRE_286_cmd_cmd_status_isa; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_319_cmd_status_dprv; // @[Mux.scala:30:73] assign issue_entry_2_bits_cmd_cmd_status_dprv = _issue_entry_WIRE_286_cmd_cmd_status_dprv; // @[Mux.scala:30:73] wire _issue_entry_WIRE_319_cmd_status_dv; // @[Mux.scala:30:73] assign issue_entry_2_bits_cmd_cmd_status_dv = _issue_entry_WIRE_286_cmd_cmd_status_dv; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_319_cmd_status_prv; // @[Mux.scala:30:73] assign issue_entry_2_bits_cmd_cmd_status_prv = _issue_entry_WIRE_286_cmd_cmd_status_prv; // @[Mux.scala:30:73] wire _issue_entry_WIRE_319_cmd_status_v; // @[Mux.scala:30:73] assign issue_entry_2_bits_cmd_cmd_status_v = _issue_entry_WIRE_286_cmd_cmd_status_v; // @[Mux.scala:30:73] wire _issue_entry_WIRE_319_cmd_status_sd; // @[Mux.scala:30:73] assign issue_entry_2_bits_cmd_cmd_status_sd = _issue_entry_WIRE_286_cmd_cmd_status_sd; // @[Mux.scala:30:73] wire [22:0] _issue_entry_WIRE_319_cmd_status_zero2; // @[Mux.scala:30:73] assign issue_entry_2_bits_cmd_cmd_status_zero2 = _issue_entry_WIRE_286_cmd_cmd_status_zero2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_319_cmd_status_mpv; // @[Mux.scala:30:73] assign issue_entry_2_bits_cmd_cmd_status_mpv = _issue_entry_WIRE_286_cmd_cmd_status_mpv; // @[Mux.scala:30:73] wire _issue_entry_WIRE_319_cmd_status_gva; // @[Mux.scala:30:73] assign issue_entry_2_bits_cmd_cmd_status_gva = _issue_entry_WIRE_286_cmd_cmd_status_gva; // @[Mux.scala:30:73] wire _issue_entry_WIRE_319_cmd_status_mbe; // @[Mux.scala:30:73] assign issue_entry_2_bits_cmd_cmd_status_mbe = _issue_entry_WIRE_286_cmd_cmd_status_mbe; // @[Mux.scala:30:73] wire _issue_entry_WIRE_319_cmd_status_sbe; // @[Mux.scala:30:73] assign issue_entry_2_bits_cmd_cmd_status_sbe = _issue_entry_WIRE_286_cmd_cmd_status_sbe; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_319_cmd_status_sxl; // @[Mux.scala:30:73] assign issue_entry_2_bits_cmd_cmd_status_sxl = _issue_entry_WIRE_286_cmd_cmd_status_sxl; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_319_cmd_status_uxl; // @[Mux.scala:30:73] assign issue_entry_2_bits_cmd_cmd_status_uxl = _issue_entry_WIRE_286_cmd_cmd_status_uxl; // @[Mux.scala:30:73] wire _issue_entry_WIRE_319_cmd_status_sd_rv32; // @[Mux.scala:30:73] assign issue_entry_2_bits_cmd_cmd_status_sd_rv32 = _issue_entry_WIRE_286_cmd_cmd_status_sd_rv32; // @[Mux.scala:30:73] wire [7:0] _issue_entry_WIRE_319_cmd_status_zero1; // @[Mux.scala:30:73] assign issue_entry_2_bits_cmd_cmd_status_zero1 = _issue_entry_WIRE_286_cmd_cmd_status_zero1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_319_cmd_status_tsr; // @[Mux.scala:30:73] assign issue_entry_2_bits_cmd_cmd_status_tsr = _issue_entry_WIRE_286_cmd_cmd_status_tsr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_319_cmd_status_tw; // @[Mux.scala:30:73] assign issue_entry_2_bits_cmd_cmd_status_tw = _issue_entry_WIRE_286_cmd_cmd_status_tw; // @[Mux.scala:30:73] wire _issue_entry_WIRE_319_cmd_status_tvm; // @[Mux.scala:30:73] assign issue_entry_2_bits_cmd_cmd_status_tvm = _issue_entry_WIRE_286_cmd_cmd_status_tvm; // @[Mux.scala:30:73] wire _issue_entry_WIRE_319_cmd_status_mxr; // @[Mux.scala:30:73] assign issue_entry_2_bits_cmd_cmd_status_mxr = _issue_entry_WIRE_286_cmd_cmd_status_mxr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_319_cmd_status_sum; // @[Mux.scala:30:73] assign issue_entry_2_bits_cmd_cmd_status_sum = _issue_entry_WIRE_286_cmd_cmd_status_sum; // @[Mux.scala:30:73] wire _issue_entry_WIRE_319_cmd_status_mprv; // @[Mux.scala:30:73] assign issue_entry_2_bits_cmd_cmd_status_mprv = _issue_entry_WIRE_286_cmd_cmd_status_mprv; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_319_cmd_status_xs; // @[Mux.scala:30:73] assign issue_entry_2_bits_cmd_cmd_status_xs = _issue_entry_WIRE_286_cmd_cmd_status_xs; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_319_cmd_status_fs; // @[Mux.scala:30:73] assign issue_entry_2_bits_cmd_cmd_status_fs = _issue_entry_WIRE_286_cmd_cmd_status_fs; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_319_cmd_status_mpp; // @[Mux.scala:30:73] assign issue_entry_2_bits_cmd_cmd_status_mpp = _issue_entry_WIRE_286_cmd_cmd_status_mpp; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_319_cmd_status_vs; // @[Mux.scala:30:73] assign issue_entry_2_bits_cmd_cmd_status_vs = _issue_entry_WIRE_286_cmd_cmd_status_vs; // @[Mux.scala:30:73] wire _issue_entry_WIRE_319_cmd_status_spp; // @[Mux.scala:30:73] assign issue_entry_2_bits_cmd_cmd_status_spp = _issue_entry_WIRE_286_cmd_cmd_status_spp; // @[Mux.scala:30:73] wire _issue_entry_WIRE_319_cmd_status_mpie; // @[Mux.scala:30:73] assign issue_entry_2_bits_cmd_cmd_status_mpie = _issue_entry_WIRE_286_cmd_cmd_status_mpie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_319_cmd_status_ube; // @[Mux.scala:30:73] assign issue_entry_2_bits_cmd_cmd_status_ube = _issue_entry_WIRE_286_cmd_cmd_status_ube; // @[Mux.scala:30:73] wire _issue_entry_WIRE_319_cmd_status_spie; // @[Mux.scala:30:73] assign issue_entry_2_bits_cmd_cmd_status_spie = _issue_entry_WIRE_286_cmd_cmd_status_spie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_319_cmd_status_upie; // @[Mux.scala:30:73] assign issue_entry_2_bits_cmd_cmd_status_upie = _issue_entry_WIRE_286_cmd_cmd_status_upie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_319_cmd_status_mie; // @[Mux.scala:30:73] assign issue_entry_2_bits_cmd_cmd_status_mie = _issue_entry_WIRE_286_cmd_cmd_status_mie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_319_cmd_status_hie; // @[Mux.scala:30:73] assign issue_entry_2_bits_cmd_cmd_status_hie = _issue_entry_WIRE_286_cmd_cmd_status_hie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_319_cmd_status_sie; // @[Mux.scala:30:73] assign issue_entry_2_bits_cmd_cmd_status_sie = _issue_entry_WIRE_286_cmd_cmd_status_sie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_319_cmd_status_uie; // @[Mux.scala:30:73] assign issue_entry_2_bits_cmd_cmd_status_uie = _issue_entry_WIRE_286_cmd_cmd_status_uie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_319_rob_id_valid; // @[Mux.scala:30:73] assign issue_entry_2_bits_cmd_rob_id_valid = _issue_entry_WIRE_286_cmd_rob_id_valid; // @[Mux.scala:30:73] wire [5:0] _issue_entry_WIRE_319_rob_id_bits; // @[Mux.scala:30:73] assign issue_entry_2_bits_cmd_rob_id_bits = _issue_entry_WIRE_286_cmd_rob_id_bits; // @[Mux.scala:30:73] wire _issue_entry_WIRE_319_from_matmul_fsm; // @[Mux.scala:30:73] assign issue_entry_2_bits_cmd_from_matmul_fsm = _issue_entry_WIRE_286_cmd_from_matmul_fsm; // @[Mux.scala:30:73] wire _issue_entry_WIRE_319_from_conv_fsm; // @[Mux.scala:30:73] assign issue_entry_2_bits_cmd_from_conv_fsm = _issue_entry_WIRE_286_cmd_from_conv_fsm; // @[Mux.scala:30:73] wire _issue_entry_WIRE_310_0; // @[Mux.scala:30:73] assign issue_entry_2_bits_deps_ld_0 = _issue_entry_WIRE_286_deps_ld_0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_310_1; // @[Mux.scala:30:73] assign issue_entry_2_bits_deps_ld_1 = _issue_entry_WIRE_286_deps_ld_1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_310_2; // @[Mux.scala:30:73] assign issue_entry_2_bits_deps_ld_2 = _issue_entry_WIRE_286_deps_ld_2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_310_3; // @[Mux.scala:30:73] assign issue_entry_2_bits_deps_ld_3 = _issue_entry_WIRE_286_deps_ld_3; // @[Mux.scala:30:73] wire _issue_entry_WIRE_310_4; // @[Mux.scala:30:73] assign issue_entry_2_bits_deps_ld_4 = _issue_entry_WIRE_286_deps_ld_4; // @[Mux.scala:30:73] wire _issue_entry_WIRE_310_5; // @[Mux.scala:30:73] assign issue_entry_2_bits_deps_ld_5 = _issue_entry_WIRE_286_deps_ld_5; // @[Mux.scala:30:73] wire _issue_entry_WIRE_310_6; // @[Mux.scala:30:73] assign issue_entry_2_bits_deps_ld_6 = _issue_entry_WIRE_286_deps_ld_6; // @[Mux.scala:30:73] wire _issue_entry_WIRE_310_7; // @[Mux.scala:30:73] assign issue_entry_2_bits_deps_ld_7 = _issue_entry_WIRE_286_deps_ld_7; // @[Mux.scala:30:73] wire _issue_entry_WIRE_293_0; // @[Mux.scala:30:73] assign issue_entry_2_bits_deps_ex_0 = _issue_entry_WIRE_286_deps_ex_0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_293_1; // @[Mux.scala:30:73] assign issue_entry_2_bits_deps_ex_1 = _issue_entry_WIRE_286_deps_ex_1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_293_2; // @[Mux.scala:30:73] assign issue_entry_2_bits_deps_ex_2 = _issue_entry_WIRE_286_deps_ex_2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_293_3; // @[Mux.scala:30:73] assign issue_entry_2_bits_deps_ex_3 = _issue_entry_WIRE_286_deps_ex_3; // @[Mux.scala:30:73] wire _issue_entry_WIRE_293_4; // @[Mux.scala:30:73] assign issue_entry_2_bits_deps_ex_4 = _issue_entry_WIRE_286_deps_ex_4; // @[Mux.scala:30:73] wire _issue_entry_WIRE_293_5; // @[Mux.scala:30:73] assign issue_entry_2_bits_deps_ex_5 = _issue_entry_WIRE_286_deps_ex_5; // @[Mux.scala:30:73] wire _issue_entry_WIRE_293_6; // @[Mux.scala:30:73] assign issue_entry_2_bits_deps_ex_6 = _issue_entry_WIRE_286_deps_ex_6; // @[Mux.scala:30:73] wire _issue_entry_WIRE_293_7; // @[Mux.scala:30:73] assign issue_entry_2_bits_deps_ex_7 = _issue_entry_WIRE_286_deps_ex_7; // @[Mux.scala:30:73] wire _issue_entry_WIRE_293_8; // @[Mux.scala:30:73] assign issue_entry_2_bits_deps_ex_8 = _issue_entry_WIRE_286_deps_ex_8; // @[Mux.scala:30:73] wire _issue_entry_WIRE_293_9; // @[Mux.scala:30:73] assign issue_entry_2_bits_deps_ex_9 = _issue_entry_WIRE_286_deps_ex_9; // @[Mux.scala:30:73] wire _issue_entry_WIRE_293_10; // @[Mux.scala:30:73] assign issue_entry_2_bits_deps_ex_10 = _issue_entry_WIRE_286_deps_ex_10; // @[Mux.scala:30:73] wire _issue_entry_WIRE_293_11; // @[Mux.scala:30:73] assign issue_entry_2_bits_deps_ex_11 = _issue_entry_WIRE_286_deps_ex_11; // @[Mux.scala:30:73] wire _issue_entry_WIRE_293_12; // @[Mux.scala:30:73] assign issue_entry_2_bits_deps_ex_12 = _issue_entry_WIRE_286_deps_ex_12; // @[Mux.scala:30:73] wire _issue_entry_WIRE_293_13; // @[Mux.scala:30:73] assign issue_entry_2_bits_deps_ex_13 = _issue_entry_WIRE_286_deps_ex_13; // @[Mux.scala:30:73] wire _issue_entry_WIRE_293_14; // @[Mux.scala:30:73] assign issue_entry_2_bits_deps_ex_14 = _issue_entry_WIRE_286_deps_ex_14; // @[Mux.scala:30:73] wire _issue_entry_WIRE_293_15; // @[Mux.scala:30:73] assign issue_entry_2_bits_deps_ex_15 = _issue_entry_WIRE_286_deps_ex_15; // @[Mux.scala:30:73] wire _issue_entry_WIRE_288_0; // @[Mux.scala:30:73] assign issue_entry_2_bits_deps_st_0 = _issue_entry_WIRE_286_deps_st_0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_288_1; // @[Mux.scala:30:73] assign issue_entry_2_bits_deps_st_1 = _issue_entry_WIRE_286_deps_st_1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_288_2; // @[Mux.scala:30:73] assign issue_entry_2_bits_deps_st_2 = _issue_entry_WIRE_286_deps_st_2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_288_3; // @[Mux.scala:30:73] assign issue_entry_2_bits_deps_st_3 = _issue_entry_WIRE_286_deps_st_3; // @[Mux.scala:30:73] wire [31:0] _issue_entry_WIRE_287; // @[Mux.scala:30:73] assign issue_entry_2_bits_allocated_at = _issue_entry_WIRE_286_allocated_at; // @[Mux.scala:30:73] wire [31:0] _issue_entry_T_5524 = issue_sel_0_2 ? entries_st_0_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_5525 = issue_sel_1_2 ? entries_st_1_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_5526 = issue_sel_2_2 ? entries_st_2_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_5527 = issue_sel_3_2 ? entries_st_3_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_5528 = _issue_entry_T_5524 | _issue_entry_T_5525; // @[Mux.scala:30:73] wire [31:0] _issue_entry_T_5529 = _issue_entry_T_5528 | _issue_entry_T_5526; // @[Mux.scala:30:73] wire [31:0] _issue_entry_T_5530 = _issue_entry_T_5529 | _issue_entry_T_5527; // @[Mux.scala:30:73] assign _issue_entry_WIRE_287 = _issue_entry_T_5530; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_allocated_at = _issue_entry_WIRE_287; // @[Mux.scala:30:73] wire _issue_entry_WIRE_289; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_deps_st_0 = _issue_entry_WIRE_288_0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_290; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_deps_st_1 = _issue_entry_WIRE_288_1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_291; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_deps_st_2 = _issue_entry_WIRE_288_2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_292; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_deps_st_3 = _issue_entry_WIRE_288_3; // @[Mux.scala:30:73] wire _issue_entry_T_5531 = issue_sel_0_2 & entries_st_0_bits_deps_st_0; // @[OneHot.scala:83:30] wire _issue_entry_T_5532 = issue_sel_1_2 & entries_st_1_bits_deps_st_0; // @[OneHot.scala:83:30] wire _issue_entry_T_5533 = issue_sel_2_2 & entries_st_2_bits_deps_st_0; // @[OneHot.scala:83:30] wire _issue_entry_T_5534 = issue_sel_3_2 & entries_st_3_bits_deps_st_0; // @[OneHot.scala:83:30] wire _issue_entry_T_5535 = _issue_entry_T_5531 | _issue_entry_T_5532; // @[Mux.scala:30:73] wire _issue_entry_T_5536 = _issue_entry_T_5535 | _issue_entry_T_5533; // @[Mux.scala:30:73] wire _issue_entry_T_5537 = _issue_entry_T_5536 | _issue_entry_T_5534; // @[Mux.scala:30:73] assign _issue_entry_WIRE_289 = _issue_entry_T_5537; // @[Mux.scala:30:73] assign _issue_entry_WIRE_288_0 = _issue_entry_WIRE_289; // @[Mux.scala:30:73] wire _issue_entry_T_5538 = issue_sel_0_2 & entries_st_0_bits_deps_st_1; // @[OneHot.scala:83:30] wire _issue_entry_T_5539 = issue_sel_1_2 & entries_st_1_bits_deps_st_1; // @[OneHot.scala:83:30] wire _issue_entry_T_5540 = issue_sel_2_2 & entries_st_2_bits_deps_st_1; // @[OneHot.scala:83:30] wire _issue_entry_T_5541 = issue_sel_3_2 & entries_st_3_bits_deps_st_1; // @[OneHot.scala:83:30] wire _issue_entry_T_5542 = _issue_entry_T_5538 | _issue_entry_T_5539; // @[Mux.scala:30:73] wire _issue_entry_T_5543 = _issue_entry_T_5542 | _issue_entry_T_5540; // @[Mux.scala:30:73] wire _issue_entry_T_5544 = _issue_entry_T_5543 | _issue_entry_T_5541; // @[Mux.scala:30:73] assign _issue_entry_WIRE_290 = _issue_entry_T_5544; // @[Mux.scala:30:73] assign _issue_entry_WIRE_288_1 = _issue_entry_WIRE_290; // @[Mux.scala:30:73] wire _issue_entry_T_5545 = issue_sel_0_2 & entries_st_0_bits_deps_st_2; // @[OneHot.scala:83:30] wire _issue_entry_T_5546 = issue_sel_1_2 & entries_st_1_bits_deps_st_2; // @[OneHot.scala:83:30] wire _issue_entry_T_5547 = issue_sel_2_2 & entries_st_2_bits_deps_st_2; // @[OneHot.scala:83:30] wire _issue_entry_T_5548 = issue_sel_3_2 & entries_st_3_bits_deps_st_2; // @[OneHot.scala:83:30] wire _issue_entry_T_5549 = _issue_entry_T_5545 | _issue_entry_T_5546; // @[Mux.scala:30:73] wire _issue_entry_T_5550 = _issue_entry_T_5549 | _issue_entry_T_5547; // @[Mux.scala:30:73] wire _issue_entry_T_5551 = _issue_entry_T_5550 | _issue_entry_T_5548; // @[Mux.scala:30:73] assign _issue_entry_WIRE_291 = _issue_entry_T_5551; // @[Mux.scala:30:73] assign _issue_entry_WIRE_288_2 = _issue_entry_WIRE_291; // @[Mux.scala:30:73] wire _issue_entry_T_5552 = issue_sel_0_2 & entries_st_0_bits_deps_st_3; // @[OneHot.scala:83:30] wire _issue_entry_T_5553 = issue_sel_1_2 & entries_st_1_bits_deps_st_3; // @[OneHot.scala:83:30] wire _issue_entry_T_5554 = issue_sel_2_2 & entries_st_2_bits_deps_st_3; // @[OneHot.scala:83:30] wire _issue_entry_T_5555 = issue_sel_3_2 & entries_st_3_bits_deps_st_3; // @[OneHot.scala:83:30] wire _issue_entry_T_5556 = _issue_entry_T_5552 | _issue_entry_T_5553; // @[Mux.scala:30:73] wire _issue_entry_T_5557 = _issue_entry_T_5556 | _issue_entry_T_5554; // @[Mux.scala:30:73] wire _issue_entry_T_5558 = _issue_entry_T_5557 | _issue_entry_T_5555; // @[Mux.scala:30:73] assign _issue_entry_WIRE_292 = _issue_entry_T_5558; // @[Mux.scala:30:73] assign _issue_entry_WIRE_288_3 = _issue_entry_WIRE_292; // @[Mux.scala:30:73] wire _issue_entry_WIRE_294; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_deps_ex_0 = _issue_entry_WIRE_293_0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_295; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_deps_ex_1 = _issue_entry_WIRE_293_1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_296; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_deps_ex_2 = _issue_entry_WIRE_293_2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_297; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_deps_ex_3 = _issue_entry_WIRE_293_3; // @[Mux.scala:30:73] wire _issue_entry_WIRE_298; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_deps_ex_4 = _issue_entry_WIRE_293_4; // @[Mux.scala:30:73] wire _issue_entry_WIRE_299; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_deps_ex_5 = _issue_entry_WIRE_293_5; // @[Mux.scala:30:73] wire _issue_entry_WIRE_300; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_deps_ex_6 = _issue_entry_WIRE_293_6; // @[Mux.scala:30:73] wire _issue_entry_WIRE_301; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_deps_ex_7 = _issue_entry_WIRE_293_7; // @[Mux.scala:30:73] wire _issue_entry_WIRE_302; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_deps_ex_8 = _issue_entry_WIRE_293_8; // @[Mux.scala:30:73] wire _issue_entry_WIRE_303; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_deps_ex_9 = _issue_entry_WIRE_293_9; // @[Mux.scala:30:73] wire _issue_entry_WIRE_304; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_deps_ex_10 = _issue_entry_WIRE_293_10; // @[Mux.scala:30:73] wire _issue_entry_WIRE_305; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_deps_ex_11 = _issue_entry_WIRE_293_11; // @[Mux.scala:30:73] wire _issue_entry_WIRE_306; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_deps_ex_12 = _issue_entry_WIRE_293_12; // @[Mux.scala:30:73] wire _issue_entry_WIRE_307; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_deps_ex_13 = _issue_entry_WIRE_293_13; // @[Mux.scala:30:73] wire _issue_entry_WIRE_308; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_deps_ex_14 = _issue_entry_WIRE_293_14; // @[Mux.scala:30:73] wire _issue_entry_WIRE_309; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_deps_ex_15 = _issue_entry_WIRE_293_15; // @[Mux.scala:30:73] wire _issue_entry_T_5559 = issue_sel_0_2 & entries_st_0_bits_deps_ex_0; // @[OneHot.scala:83:30] wire _issue_entry_T_5560 = issue_sel_1_2 & entries_st_1_bits_deps_ex_0; // @[OneHot.scala:83:30] wire _issue_entry_T_5561 = issue_sel_2_2 & entries_st_2_bits_deps_ex_0; // @[OneHot.scala:83:30] wire _issue_entry_T_5562 = issue_sel_3_2 & entries_st_3_bits_deps_ex_0; // @[OneHot.scala:83:30] wire _issue_entry_T_5563 = _issue_entry_T_5559 | _issue_entry_T_5560; // @[Mux.scala:30:73] wire _issue_entry_T_5564 = _issue_entry_T_5563 | _issue_entry_T_5561; // @[Mux.scala:30:73] wire _issue_entry_T_5565 = _issue_entry_T_5564 | _issue_entry_T_5562; // @[Mux.scala:30:73] assign _issue_entry_WIRE_294 = _issue_entry_T_5565; // @[Mux.scala:30:73] assign _issue_entry_WIRE_293_0 = _issue_entry_WIRE_294; // @[Mux.scala:30:73] wire _issue_entry_T_5566 = issue_sel_0_2 & entries_st_0_bits_deps_ex_1; // @[OneHot.scala:83:30] wire _issue_entry_T_5567 = issue_sel_1_2 & entries_st_1_bits_deps_ex_1; // @[OneHot.scala:83:30] wire _issue_entry_T_5568 = issue_sel_2_2 & entries_st_2_bits_deps_ex_1; // @[OneHot.scala:83:30] wire _issue_entry_T_5569 = issue_sel_3_2 & entries_st_3_bits_deps_ex_1; // @[OneHot.scala:83:30] wire _issue_entry_T_5570 = _issue_entry_T_5566 | _issue_entry_T_5567; // @[Mux.scala:30:73] wire _issue_entry_T_5571 = _issue_entry_T_5570 | _issue_entry_T_5568; // @[Mux.scala:30:73] wire _issue_entry_T_5572 = _issue_entry_T_5571 | _issue_entry_T_5569; // @[Mux.scala:30:73] assign _issue_entry_WIRE_295 = _issue_entry_T_5572; // @[Mux.scala:30:73] assign _issue_entry_WIRE_293_1 = _issue_entry_WIRE_295; // @[Mux.scala:30:73] wire _issue_entry_T_5573 = issue_sel_0_2 & entries_st_0_bits_deps_ex_2; // @[OneHot.scala:83:30] wire _issue_entry_T_5574 = issue_sel_1_2 & entries_st_1_bits_deps_ex_2; // @[OneHot.scala:83:30] wire _issue_entry_T_5575 = issue_sel_2_2 & entries_st_2_bits_deps_ex_2; // @[OneHot.scala:83:30] wire _issue_entry_T_5576 = issue_sel_3_2 & entries_st_3_bits_deps_ex_2; // @[OneHot.scala:83:30] wire _issue_entry_T_5577 = _issue_entry_T_5573 | _issue_entry_T_5574; // @[Mux.scala:30:73] wire _issue_entry_T_5578 = _issue_entry_T_5577 | _issue_entry_T_5575; // @[Mux.scala:30:73] wire _issue_entry_T_5579 = _issue_entry_T_5578 | _issue_entry_T_5576; // @[Mux.scala:30:73] assign _issue_entry_WIRE_296 = _issue_entry_T_5579; // @[Mux.scala:30:73] assign _issue_entry_WIRE_293_2 = _issue_entry_WIRE_296; // @[Mux.scala:30:73] wire _issue_entry_T_5580 = issue_sel_0_2 & entries_st_0_bits_deps_ex_3; // @[OneHot.scala:83:30] wire _issue_entry_T_5581 = issue_sel_1_2 & entries_st_1_bits_deps_ex_3; // @[OneHot.scala:83:30] wire _issue_entry_T_5582 = issue_sel_2_2 & entries_st_2_bits_deps_ex_3; // @[OneHot.scala:83:30] wire _issue_entry_T_5583 = issue_sel_3_2 & entries_st_3_bits_deps_ex_3; // @[OneHot.scala:83:30] wire _issue_entry_T_5584 = _issue_entry_T_5580 | _issue_entry_T_5581; // @[Mux.scala:30:73] wire _issue_entry_T_5585 = _issue_entry_T_5584 | _issue_entry_T_5582; // @[Mux.scala:30:73] wire _issue_entry_T_5586 = _issue_entry_T_5585 | _issue_entry_T_5583; // @[Mux.scala:30:73] assign _issue_entry_WIRE_297 = _issue_entry_T_5586; // @[Mux.scala:30:73] assign _issue_entry_WIRE_293_3 = _issue_entry_WIRE_297; // @[Mux.scala:30:73] wire _issue_entry_T_5587 = issue_sel_0_2 & entries_st_0_bits_deps_ex_4; // @[OneHot.scala:83:30] wire _issue_entry_T_5588 = issue_sel_1_2 & entries_st_1_bits_deps_ex_4; // @[OneHot.scala:83:30] wire _issue_entry_T_5589 = issue_sel_2_2 & entries_st_2_bits_deps_ex_4; // @[OneHot.scala:83:30] wire _issue_entry_T_5590 = issue_sel_3_2 & entries_st_3_bits_deps_ex_4; // @[OneHot.scala:83:30] wire _issue_entry_T_5591 = _issue_entry_T_5587 | _issue_entry_T_5588; // @[Mux.scala:30:73] wire _issue_entry_T_5592 = _issue_entry_T_5591 | _issue_entry_T_5589; // @[Mux.scala:30:73] wire _issue_entry_T_5593 = _issue_entry_T_5592 | _issue_entry_T_5590; // @[Mux.scala:30:73] assign _issue_entry_WIRE_298 = _issue_entry_T_5593; // @[Mux.scala:30:73] assign _issue_entry_WIRE_293_4 = _issue_entry_WIRE_298; // @[Mux.scala:30:73] wire _issue_entry_T_5594 = issue_sel_0_2 & entries_st_0_bits_deps_ex_5; // @[OneHot.scala:83:30] wire _issue_entry_T_5595 = issue_sel_1_2 & entries_st_1_bits_deps_ex_5; // @[OneHot.scala:83:30] wire _issue_entry_T_5596 = issue_sel_2_2 & entries_st_2_bits_deps_ex_5; // @[OneHot.scala:83:30] wire _issue_entry_T_5597 = issue_sel_3_2 & entries_st_3_bits_deps_ex_5; // @[OneHot.scala:83:30] wire _issue_entry_T_5598 = _issue_entry_T_5594 | _issue_entry_T_5595; // @[Mux.scala:30:73] wire _issue_entry_T_5599 = _issue_entry_T_5598 | _issue_entry_T_5596; // @[Mux.scala:30:73] wire _issue_entry_T_5600 = _issue_entry_T_5599 | _issue_entry_T_5597; // @[Mux.scala:30:73] assign _issue_entry_WIRE_299 = _issue_entry_T_5600; // @[Mux.scala:30:73] assign _issue_entry_WIRE_293_5 = _issue_entry_WIRE_299; // @[Mux.scala:30:73] wire _issue_entry_T_5601 = issue_sel_0_2 & entries_st_0_bits_deps_ex_6; // @[OneHot.scala:83:30] wire _issue_entry_T_5602 = issue_sel_1_2 & entries_st_1_bits_deps_ex_6; // @[OneHot.scala:83:30] wire _issue_entry_T_5603 = issue_sel_2_2 & entries_st_2_bits_deps_ex_6; // @[OneHot.scala:83:30] wire _issue_entry_T_5604 = issue_sel_3_2 & entries_st_3_bits_deps_ex_6; // @[OneHot.scala:83:30] wire _issue_entry_T_5605 = _issue_entry_T_5601 | _issue_entry_T_5602; // @[Mux.scala:30:73] wire _issue_entry_T_5606 = _issue_entry_T_5605 | _issue_entry_T_5603; // @[Mux.scala:30:73] wire _issue_entry_T_5607 = _issue_entry_T_5606 | _issue_entry_T_5604; // @[Mux.scala:30:73] assign _issue_entry_WIRE_300 = _issue_entry_T_5607; // @[Mux.scala:30:73] assign _issue_entry_WIRE_293_6 = _issue_entry_WIRE_300; // @[Mux.scala:30:73] wire _issue_entry_T_5608 = issue_sel_0_2 & entries_st_0_bits_deps_ex_7; // @[OneHot.scala:83:30] wire _issue_entry_T_5609 = issue_sel_1_2 & entries_st_1_bits_deps_ex_7; // @[OneHot.scala:83:30] wire _issue_entry_T_5610 = issue_sel_2_2 & entries_st_2_bits_deps_ex_7; // @[OneHot.scala:83:30] wire _issue_entry_T_5611 = issue_sel_3_2 & entries_st_3_bits_deps_ex_7; // @[OneHot.scala:83:30] wire _issue_entry_T_5612 = _issue_entry_T_5608 | _issue_entry_T_5609; // @[Mux.scala:30:73] wire _issue_entry_T_5613 = _issue_entry_T_5612 | _issue_entry_T_5610; // @[Mux.scala:30:73] wire _issue_entry_T_5614 = _issue_entry_T_5613 | _issue_entry_T_5611; // @[Mux.scala:30:73] assign _issue_entry_WIRE_301 = _issue_entry_T_5614; // @[Mux.scala:30:73] assign _issue_entry_WIRE_293_7 = _issue_entry_WIRE_301; // @[Mux.scala:30:73] wire _issue_entry_T_5615 = issue_sel_0_2 & entries_st_0_bits_deps_ex_8; // @[OneHot.scala:83:30] wire _issue_entry_T_5616 = issue_sel_1_2 & entries_st_1_bits_deps_ex_8; // @[OneHot.scala:83:30] wire _issue_entry_T_5617 = issue_sel_2_2 & entries_st_2_bits_deps_ex_8; // @[OneHot.scala:83:30] wire _issue_entry_T_5618 = issue_sel_3_2 & entries_st_3_bits_deps_ex_8; // @[OneHot.scala:83:30] wire _issue_entry_T_5619 = _issue_entry_T_5615 | _issue_entry_T_5616; // @[Mux.scala:30:73] wire _issue_entry_T_5620 = _issue_entry_T_5619 | _issue_entry_T_5617; // @[Mux.scala:30:73] wire _issue_entry_T_5621 = _issue_entry_T_5620 | _issue_entry_T_5618; // @[Mux.scala:30:73] assign _issue_entry_WIRE_302 = _issue_entry_T_5621; // @[Mux.scala:30:73] assign _issue_entry_WIRE_293_8 = _issue_entry_WIRE_302; // @[Mux.scala:30:73] wire _issue_entry_T_5622 = issue_sel_0_2 & entries_st_0_bits_deps_ex_9; // @[OneHot.scala:83:30] wire _issue_entry_T_5623 = issue_sel_1_2 & entries_st_1_bits_deps_ex_9; // @[OneHot.scala:83:30] wire _issue_entry_T_5624 = issue_sel_2_2 & entries_st_2_bits_deps_ex_9; // @[OneHot.scala:83:30] wire _issue_entry_T_5625 = issue_sel_3_2 & entries_st_3_bits_deps_ex_9; // @[OneHot.scala:83:30] wire _issue_entry_T_5626 = _issue_entry_T_5622 | _issue_entry_T_5623; // @[Mux.scala:30:73] wire _issue_entry_T_5627 = _issue_entry_T_5626 | _issue_entry_T_5624; // @[Mux.scala:30:73] wire _issue_entry_T_5628 = _issue_entry_T_5627 | _issue_entry_T_5625; // @[Mux.scala:30:73] assign _issue_entry_WIRE_303 = _issue_entry_T_5628; // @[Mux.scala:30:73] assign _issue_entry_WIRE_293_9 = _issue_entry_WIRE_303; // @[Mux.scala:30:73] wire _issue_entry_T_5629 = issue_sel_0_2 & entries_st_0_bits_deps_ex_10; // @[OneHot.scala:83:30] wire _issue_entry_T_5630 = issue_sel_1_2 & entries_st_1_bits_deps_ex_10; // @[OneHot.scala:83:30] wire _issue_entry_T_5631 = issue_sel_2_2 & entries_st_2_bits_deps_ex_10; // @[OneHot.scala:83:30] wire _issue_entry_T_5632 = issue_sel_3_2 & entries_st_3_bits_deps_ex_10; // @[OneHot.scala:83:30] wire _issue_entry_T_5633 = _issue_entry_T_5629 | _issue_entry_T_5630; // @[Mux.scala:30:73] wire _issue_entry_T_5634 = _issue_entry_T_5633 | _issue_entry_T_5631; // @[Mux.scala:30:73] wire _issue_entry_T_5635 = _issue_entry_T_5634 | _issue_entry_T_5632; // @[Mux.scala:30:73] assign _issue_entry_WIRE_304 = _issue_entry_T_5635; // @[Mux.scala:30:73] assign _issue_entry_WIRE_293_10 = _issue_entry_WIRE_304; // @[Mux.scala:30:73] wire _issue_entry_T_5636 = issue_sel_0_2 & entries_st_0_bits_deps_ex_11; // @[OneHot.scala:83:30] wire _issue_entry_T_5637 = issue_sel_1_2 & entries_st_1_bits_deps_ex_11; // @[OneHot.scala:83:30] wire _issue_entry_T_5638 = issue_sel_2_2 & entries_st_2_bits_deps_ex_11; // @[OneHot.scala:83:30] wire _issue_entry_T_5639 = issue_sel_3_2 & entries_st_3_bits_deps_ex_11; // @[OneHot.scala:83:30] wire _issue_entry_T_5640 = _issue_entry_T_5636 | _issue_entry_T_5637; // @[Mux.scala:30:73] wire _issue_entry_T_5641 = _issue_entry_T_5640 | _issue_entry_T_5638; // @[Mux.scala:30:73] wire _issue_entry_T_5642 = _issue_entry_T_5641 | _issue_entry_T_5639; // @[Mux.scala:30:73] assign _issue_entry_WIRE_305 = _issue_entry_T_5642; // @[Mux.scala:30:73] assign _issue_entry_WIRE_293_11 = _issue_entry_WIRE_305; // @[Mux.scala:30:73] wire _issue_entry_T_5643 = issue_sel_0_2 & entries_st_0_bits_deps_ex_12; // @[OneHot.scala:83:30] wire _issue_entry_T_5644 = issue_sel_1_2 & entries_st_1_bits_deps_ex_12; // @[OneHot.scala:83:30] wire _issue_entry_T_5645 = issue_sel_2_2 & entries_st_2_bits_deps_ex_12; // @[OneHot.scala:83:30] wire _issue_entry_T_5646 = issue_sel_3_2 & entries_st_3_bits_deps_ex_12; // @[OneHot.scala:83:30] wire _issue_entry_T_5647 = _issue_entry_T_5643 | _issue_entry_T_5644; // @[Mux.scala:30:73] wire _issue_entry_T_5648 = _issue_entry_T_5647 | _issue_entry_T_5645; // @[Mux.scala:30:73] wire _issue_entry_T_5649 = _issue_entry_T_5648 | _issue_entry_T_5646; // @[Mux.scala:30:73] assign _issue_entry_WIRE_306 = _issue_entry_T_5649; // @[Mux.scala:30:73] assign _issue_entry_WIRE_293_12 = _issue_entry_WIRE_306; // @[Mux.scala:30:73] wire _issue_entry_T_5650 = issue_sel_0_2 & entries_st_0_bits_deps_ex_13; // @[OneHot.scala:83:30] wire _issue_entry_T_5651 = issue_sel_1_2 & entries_st_1_bits_deps_ex_13; // @[OneHot.scala:83:30] wire _issue_entry_T_5652 = issue_sel_2_2 & entries_st_2_bits_deps_ex_13; // @[OneHot.scala:83:30] wire _issue_entry_T_5653 = issue_sel_3_2 & entries_st_3_bits_deps_ex_13; // @[OneHot.scala:83:30] wire _issue_entry_T_5654 = _issue_entry_T_5650 | _issue_entry_T_5651; // @[Mux.scala:30:73] wire _issue_entry_T_5655 = _issue_entry_T_5654 | _issue_entry_T_5652; // @[Mux.scala:30:73] wire _issue_entry_T_5656 = _issue_entry_T_5655 | _issue_entry_T_5653; // @[Mux.scala:30:73] assign _issue_entry_WIRE_307 = _issue_entry_T_5656; // @[Mux.scala:30:73] assign _issue_entry_WIRE_293_13 = _issue_entry_WIRE_307; // @[Mux.scala:30:73] wire _issue_entry_T_5657 = issue_sel_0_2 & entries_st_0_bits_deps_ex_14; // @[OneHot.scala:83:30] wire _issue_entry_T_5658 = issue_sel_1_2 & entries_st_1_bits_deps_ex_14; // @[OneHot.scala:83:30] wire _issue_entry_T_5659 = issue_sel_2_2 & entries_st_2_bits_deps_ex_14; // @[OneHot.scala:83:30] wire _issue_entry_T_5660 = issue_sel_3_2 & entries_st_3_bits_deps_ex_14; // @[OneHot.scala:83:30] wire _issue_entry_T_5661 = _issue_entry_T_5657 | _issue_entry_T_5658; // @[Mux.scala:30:73] wire _issue_entry_T_5662 = _issue_entry_T_5661 | _issue_entry_T_5659; // @[Mux.scala:30:73] wire _issue_entry_T_5663 = _issue_entry_T_5662 | _issue_entry_T_5660; // @[Mux.scala:30:73] assign _issue_entry_WIRE_308 = _issue_entry_T_5663; // @[Mux.scala:30:73] assign _issue_entry_WIRE_293_14 = _issue_entry_WIRE_308; // @[Mux.scala:30:73] wire _issue_entry_T_5664 = issue_sel_0_2 & entries_st_0_bits_deps_ex_15; // @[OneHot.scala:83:30] wire _issue_entry_T_5665 = issue_sel_1_2 & entries_st_1_bits_deps_ex_15; // @[OneHot.scala:83:30] wire _issue_entry_T_5666 = issue_sel_2_2 & entries_st_2_bits_deps_ex_15; // @[OneHot.scala:83:30] wire _issue_entry_T_5667 = issue_sel_3_2 & entries_st_3_bits_deps_ex_15; // @[OneHot.scala:83:30] wire _issue_entry_T_5668 = _issue_entry_T_5664 | _issue_entry_T_5665; // @[Mux.scala:30:73] wire _issue_entry_T_5669 = _issue_entry_T_5668 | _issue_entry_T_5666; // @[Mux.scala:30:73] wire _issue_entry_T_5670 = _issue_entry_T_5669 | _issue_entry_T_5667; // @[Mux.scala:30:73] assign _issue_entry_WIRE_309 = _issue_entry_T_5670; // @[Mux.scala:30:73] assign _issue_entry_WIRE_293_15 = _issue_entry_WIRE_309; // @[Mux.scala:30:73] wire _issue_entry_WIRE_311; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_deps_ld_0 = _issue_entry_WIRE_310_0; // @[Mux.scala:30:73] wire _issue_entry_WIRE_312; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_deps_ld_1 = _issue_entry_WIRE_310_1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_313; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_deps_ld_2 = _issue_entry_WIRE_310_2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_314; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_deps_ld_3 = _issue_entry_WIRE_310_3; // @[Mux.scala:30:73] wire _issue_entry_WIRE_315; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_deps_ld_4 = _issue_entry_WIRE_310_4; // @[Mux.scala:30:73] wire _issue_entry_WIRE_316; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_deps_ld_5 = _issue_entry_WIRE_310_5; // @[Mux.scala:30:73] wire _issue_entry_WIRE_317; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_deps_ld_6 = _issue_entry_WIRE_310_6; // @[Mux.scala:30:73] wire _issue_entry_WIRE_318; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_deps_ld_7 = _issue_entry_WIRE_310_7; // @[Mux.scala:30:73] wire _issue_entry_T_5671 = issue_sel_0_2 & entries_st_0_bits_deps_ld_0; // @[OneHot.scala:83:30] wire _issue_entry_T_5672 = issue_sel_1_2 & entries_st_1_bits_deps_ld_0; // @[OneHot.scala:83:30] wire _issue_entry_T_5673 = issue_sel_2_2 & entries_st_2_bits_deps_ld_0; // @[OneHot.scala:83:30] wire _issue_entry_T_5674 = issue_sel_3_2 & entries_st_3_bits_deps_ld_0; // @[OneHot.scala:83:30] wire _issue_entry_T_5675 = _issue_entry_T_5671 | _issue_entry_T_5672; // @[Mux.scala:30:73] wire _issue_entry_T_5676 = _issue_entry_T_5675 | _issue_entry_T_5673; // @[Mux.scala:30:73] wire _issue_entry_T_5677 = _issue_entry_T_5676 | _issue_entry_T_5674; // @[Mux.scala:30:73] assign _issue_entry_WIRE_311 = _issue_entry_T_5677; // @[Mux.scala:30:73] assign _issue_entry_WIRE_310_0 = _issue_entry_WIRE_311; // @[Mux.scala:30:73] wire _issue_entry_T_5678 = issue_sel_0_2 & entries_st_0_bits_deps_ld_1; // @[OneHot.scala:83:30] wire _issue_entry_T_5679 = issue_sel_1_2 & entries_st_1_bits_deps_ld_1; // @[OneHot.scala:83:30] wire _issue_entry_T_5680 = issue_sel_2_2 & entries_st_2_bits_deps_ld_1; // @[OneHot.scala:83:30] wire _issue_entry_T_5681 = issue_sel_3_2 & entries_st_3_bits_deps_ld_1; // @[OneHot.scala:83:30] wire _issue_entry_T_5682 = _issue_entry_T_5678 | _issue_entry_T_5679; // @[Mux.scala:30:73] wire _issue_entry_T_5683 = _issue_entry_T_5682 | _issue_entry_T_5680; // @[Mux.scala:30:73] wire _issue_entry_T_5684 = _issue_entry_T_5683 | _issue_entry_T_5681; // @[Mux.scala:30:73] assign _issue_entry_WIRE_312 = _issue_entry_T_5684; // @[Mux.scala:30:73] assign _issue_entry_WIRE_310_1 = _issue_entry_WIRE_312; // @[Mux.scala:30:73] wire _issue_entry_T_5685 = issue_sel_0_2 & entries_st_0_bits_deps_ld_2; // @[OneHot.scala:83:30] wire _issue_entry_T_5686 = issue_sel_1_2 & entries_st_1_bits_deps_ld_2; // @[OneHot.scala:83:30] wire _issue_entry_T_5687 = issue_sel_2_2 & entries_st_2_bits_deps_ld_2; // @[OneHot.scala:83:30] wire _issue_entry_T_5688 = issue_sel_3_2 & entries_st_3_bits_deps_ld_2; // @[OneHot.scala:83:30] wire _issue_entry_T_5689 = _issue_entry_T_5685 | _issue_entry_T_5686; // @[Mux.scala:30:73] wire _issue_entry_T_5690 = _issue_entry_T_5689 | _issue_entry_T_5687; // @[Mux.scala:30:73] wire _issue_entry_T_5691 = _issue_entry_T_5690 | _issue_entry_T_5688; // @[Mux.scala:30:73] assign _issue_entry_WIRE_313 = _issue_entry_T_5691; // @[Mux.scala:30:73] assign _issue_entry_WIRE_310_2 = _issue_entry_WIRE_313; // @[Mux.scala:30:73] wire _issue_entry_T_5692 = issue_sel_0_2 & entries_st_0_bits_deps_ld_3; // @[OneHot.scala:83:30] wire _issue_entry_T_5693 = issue_sel_1_2 & entries_st_1_bits_deps_ld_3; // @[OneHot.scala:83:30] wire _issue_entry_T_5694 = issue_sel_2_2 & entries_st_2_bits_deps_ld_3; // @[OneHot.scala:83:30] wire _issue_entry_T_5695 = issue_sel_3_2 & entries_st_3_bits_deps_ld_3; // @[OneHot.scala:83:30] wire _issue_entry_T_5696 = _issue_entry_T_5692 | _issue_entry_T_5693; // @[Mux.scala:30:73] wire _issue_entry_T_5697 = _issue_entry_T_5696 | _issue_entry_T_5694; // @[Mux.scala:30:73] wire _issue_entry_T_5698 = _issue_entry_T_5697 | _issue_entry_T_5695; // @[Mux.scala:30:73] assign _issue_entry_WIRE_314 = _issue_entry_T_5698; // @[Mux.scala:30:73] assign _issue_entry_WIRE_310_3 = _issue_entry_WIRE_314; // @[Mux.scala:30:73] wire _issue_entry_T_5699 = issue_sel_0_2 & entries_st_0_bits_deps_ld_4; // @[OneHot.scala:83:30] wire _issue_entry_T_5700 = issue_sel_1_2 & entries_st_1_bits_deps_ld_4; // @[OneHot.scala:83:30] wire _issue_entry_T_5701 = issue_sel_2_2 & entries_st_2_bits_deps_ld_4; // @[OneHot.scala:83:30] wire _issue_entry_T_5702 = issue_sel_3_2 & entries_st_3_bits_deps_ld_4; // @[OneHot.scala:83:30] wire _issue_entry_T_5703 = _issue_entry_T_5699 | _issue_entry_T_5700; // @[Mux.scala:30:73] wire _issue_entry_T_5704 = _issue_entry_T_5703 | _issue_entry_T_5701; // @[Mux.scala:30:73] wire _issue_entry_T_5705 = _issue_entry_T_5704 | _issue_entry_T_5702; // @[Mux.scala:30:73] assign _issue_entry_WIRE_315 = _issue_entry_T_5705; // @[Mux.scala:30:73] assign _issue_entry_WIRE_310_4 = _issue_entry_WIRE_315; // @[Mux.scala:30:73] wire _issue_entry_T_5706 = issue_sel_0_2 & entries_st_0_bits_deps_ld_5; // @[OneHot.scala:83:30] wire _issue_entry_T_5707 = issue_sel_1_2 & entries_st_1_bits_deps_ld_5; // @[OneHot.scala:83:30] wire _issue_entry_T_5708 = issue_sel_2_2 & entries_st_2_bits_deps_ld_5; // @[OneHot.scala:83:30] wire _issue_entry_T_5709 = issue_sel_3_2 & entries_st_3_bits_deps_ld_5; // @[OneHot.scala:83:30] wire _issue_entry_T_5710 = _issue_entry_T_5706 | _issue_entry_T_5707; // @[Mux.scala:30:73] wire _issue_entry_T_5711 = _issue_entry_T_5710 | _issue_entry_T_5708; // @[Mux.scala:30:73] wire _issue_entry_T_5712 = _issue_entry_T_5711 | _issue_entry_T_5709; // @[Mux.scala:30:73] assign _issue_entry_WIRE_316 = _issue_entry_T_5712; // @[Mux.scala:30:73] assign _issue_entry_WIRE_310_5 = _issue_entry_WIRE_316; // @[Mux.scala:30:73] wire _issue_entry_T_5713 = issue_sel_0_2 & entries_st_0_bits_deps_ld_6; // @[OneHot.scala:83:30] wire _issue_entry_T_5714 = issue_sel_1_2 & entries_st_1_bits_deps_ld_6; // @[OneHot.scala:83:30] wire _issue_entry_T_5715 = issue_sel_2_2 & entries_st_2_bits_deps_ld_6; // @[OneHot.scala:83:30] wire _issue_entry_T_5716 = issue_sel_3_2 & entries_st_3_bits_deps_ld_6; // @[OneHot.scala:83:30] wire _issue_entry_T_5717 = _issue_entry_T_5713 | _issue_entry_T_5714; // @[Mux.scala:30:73] wire _issue_entry_T_5718 = _issue_entry_T_5717 | _issue_entry_T_5715; // @[Mux.scala:30:73] wire _issue_entry_T_5719 = _issue_entry_T_5718 | _issue_entry_T_5716; // @[Mux.scala:30:73] assign _issue_entry_WIRE_317 = _issue_entry_T_5719; // @[Mux.scala:30:73] assign _issue_entry_WIRE_310_6 = _issue_entry_WIRE_317; // @[Mux.scala:30:73] wire _issue_entry_T_5720 = issue_sel_0_2 & entries_st_0_bits_deps_ld_7; // @[OneHot.scala:83:30] wire _issue_entry_T_5721 = issue_sel_1_2 & entries_st_1_bits_deps_ld_7; // @[OneHot.scala:83:30] wire _issue_entry_T_5722 = issue_sel_2_2 & entries_st_2_bits_deps_ld_7; // @[OneHot.scala:83:30] wire _issue_entry_T_5723 = issue_sel_3_2 & entries_st_3_bits_deps_ld_7; // @[OneHot.scala:83:30] wire _issue_entry_T_5724 = _issue_entry_T_5720 | _issue_entry_T_5721; // @[Mux.scala:30:73] wire _issue_entry_T_5725 = _issue_entry_T_5724 | _issue_entry_T_5722; // @[Mux.scala:30:73] wire _issue_entry_T_5726 = _issue_entry_T_5725 | _issue_entry_T_5723; // @[Mux.scala:30:73] assign _issue_entry_WIRE_318 = _issue_entry_T_5726; // @[Mux.scala:30:73] assign _issue_entry_WIRE_310_7 = _issue_entry_WIRE_318; // @[Mux.scala:30:73] wire [6:0] _issue_entry_WIRE_325_inst_funct; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_cmd_cmd_inst_funct = _issue_entry_WIRE_319_cmd_inst_funct; // @[Mux.scala:30:73] wire [4:0] _issue_entry_WIRE_325_inst_rs2; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_cmd_cmd_inst_rs2 = _issue_entry_WIRE_319_cmd_inst_rs2; // @[Mux.scala:30:73] wire [4:0] _issue_entry_WIRE_325_inst_rs1; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_cmd_cmd_inst_rs1 = _issue_entry_WIRE_319_cmd_inst_rs1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_325_inst_xd; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_cmd_cmd_inst_xd = _issue_entry_WIRE_319_cmd_inst_xd; // @[Mux.scala:30:73] wire _issue_entry_WIRE_325_inst_xs1; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_cmd_cmd_inst_xs1 = _issue_entry_WIRE_319_cmd_inst_xs1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_325_inst_xs2; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_cmd_cmd_inst_xs2 = _issue_entry_WIRE_319_cmd_inst_xs2; // @[Mux.scala:30:73] wire [4:0] _issue_entry_WIRE_325_inst_rd; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_cmd_cmd_inst_rd = _issue_entry_WIRE_319_cmd_inst_rd; // @[Mux.scala:30:73] wire [6:0] _issue_entry_WIRE_325_inst_opcode; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_cmd_cmd_inst_opcode = _issue_entry_WIRE_319_cmd_inst_opcode; // @[Mux.scala:30:73] wire [63:0] _issue_entry_WIRE_325_rs1; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_cmd_cmd_rs1 = _issue_entry_WIRE_319_cmd_rs1; // @[Mux.scala:30:73] wire [63:0] _issue_entry_WIRE_325_rs2; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_cmd_cmd_rs2 = _issue_entry_WIRE_319_cmd_rs2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_325_status_debug; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_cmd_cmd_status_debug = _issue_entry_WIRE_319_cmd_status_debug; // @[Mux.scala:30:73] wire _issue_entry_WIRE_325_status_cease; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_cmd_cmd_status_cease = _issue_entry_WIRE_319_cmd_status_cease; // @[Mux.scala:30:73] wire _issue_entry_WIRE_325_status_wfi; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_cmd_cmd_status_wfi = _issue_entry_WIRE_319_cmd_status_wfi; // @[Mux.scala:30:73] wire [31:0] _issue_entry_WIRE_325_status_isa; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_cmd_cmd_status_isa = _issue_entry_WIRE_319_cmd_status_isa; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_325_status_dprv; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_cmd_cmd_status_dprv = _issue_entry_WIRE_319_cmd_status_dprv; // @[Mux.scala:30:73] wire _issue_entry_WIRE_325_status_dv; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_cmd_cmd_status_dv = _issue_entry_WIRE_319_cmd_status_dv; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_325_status_prv; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_cmd_cmd_status_prv = _issue_entry_WIRE_319_cmd_status_prv; // @[Mux.scala:30:73] wire _issue_entry_WIRE_325_status_v; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_cmd_cmd_status_v = _issue_entry_WIRE_319_cmd_status_v; // @[Mux.scala:30:73] wire _issue_entry_WIRE_325_status_sd; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_cmd_cmd_status_sd = _issue_entry_WIRE_319_cmd_status_sd; // @[Mux.scala:30:73] wire [22:0] _issue_entry_WIRE_325_status_zero2; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_cmd_cmd_status_zero2 = _issue_entry_WIRE_319_cmd_status_zero2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_325_status_mpv; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_cmd_cmd_status_mpv = _issue_entry_WIRE_319_cmd_status_mpv; // @[Mux.scala:30:73] wire _issue_entry_WIRE_325_status_gva; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_cmd_cmd_status_gva = _issue_entry_WIRE_319_cmd_status_gva; // @[Mux.scala:30:73] wire _issue_entry_WIRE_325_status_mbe; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_cmd_cmd_status_mbe = _issue_entry_WIRE_319_cmd_status_mbe; // @[Mux.scala:30:73] wire _issue_entry_WIRE_325_status_sbe; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_cmd_cmd_status_sbe = _issue_entry_WIRE_319_cmd_status_sbe; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_325_status_sxl; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_cmd_cmd_status_sxl = _issue_entry_WIRE_319_cmd_status_sxl; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_325_status_uxl; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_cmd_cmd_status_uxl = _issue_entry_WIRE_319_cmd_status_uxl; // @[Mux.scala:30:73] wire _issue_entry_WIRE_325_status_sd_rv32; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_cmd_cmd_status_sd_rv32 = _issue_entry_WIRE_319_cmd_status_sd_rv32; // @[Mux.scala:30:73] wire [7:0] _issue_entry_WIRE_325_status_zero1; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_cmd_cmd_status_zero1 = _issue_entry_WIRE_319_cmd_status_zero1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_325_status_tsr; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_cmd_cmd_status_tsr = _issue_entry_WIRE_319_cmd_status_tsr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_325_status_tw; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_cmd_cmd_status_tw = _issue_entry_WIRE_319_cmd_status_tw; // @[Mux.scala:30:73] wire _issue_entry_WIRE_325_status_tvm; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_cmd_cmd_status_tvm = _issue_entry_WIRE_319_cmd_status_tvm; // @[Mux.scala:30:73] wire _issue_entry_WIRE_325_status_mxr; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_cmd_cmd_status_mxr = _issue_entry_WIRE_319_cmd_status_mxr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_325_status_sum; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_cmd_cmd_status_sum = _issue_entry_WIRE_319_cmd_status_sum; // @[Mux.scala:30:73] wire _issue_entry_WIRE_325_status_mprv; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_cmd_cmd_status_mprv = _issue_entry_WIRE_319_cmd_status_mprv; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_325_status_xs; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_cmd_cmd_status_xs = _issue_entry_WIRE_319_cmd_status_xs; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_325_status_fs; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_cmd_cmd_status_fs = _issue_entry_WIRE_319_cmd_status_fs; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_325_status_mpp; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_cmd_cmd_status_mpp = _issue_entry_WIRE_319_cmd_status_mpp; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_325_status_vs; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_cmd_cmd_status_vs = _issue_entry_WIRE_319_cmd_status_vs; // @[Mux.scala:30:73] wire _issue_entry_WIRE_325_status_spp; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_cmd_cmd_status_spp = _issue_entry_WIRE_319_cmd_status_spp; // @[Mux.scala:30:73] wire _issue_entry_WIRE_325_status_mpie; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_cmd_cmd_status_mpie = _issue_entry_WIRE_319_cmd_status_mpie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_325_status_ube; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_cmd_cmd_status_ube = _issue_entry_WIRE_319_cmd_status_ube; // @[Mux.scala:30:73] wire _issue_entry_WIRE_325_status_spie; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_cmd_cmd_status_spie = _issue_entry_WIRE_319_cmd_status_spie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_325_status_upie; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_cmd_cmd_status_upie = _issue_entry_WIRE_319_cmd_status_upie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_325_status_mie; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_cmd_cmd_status_mie = _issue_entry_WIRE_319_cmd_status_mie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_325_status_hie; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_cmd_cmd_status_hie = _issue_entry_WIRE_319_cmd_status_hie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_325_status_sie; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_cmd_cmd_status_sie = _issue_entry_WIRE_319_cmd_status_sie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_325_status_uie; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_cmd_cmd_status_uie = _issue_entry_WIRE_319_cmd_status_uie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_322_valid; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_cmd_rob_id_valid = _issue_entry_WIRE_319_rob_id_valid; // @[Mux.scala:30:73] wire [5:0] _issue_entry_WIRE_322_bits; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_cmd_rob_id_bits = _issue_entry_WIRE_319_rob_id_bits; // @[Mux.scala:30:73] wire _issue_entry_WIRE_321; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_cmd_from_matmul_fsm = _issue_entry_WIRE_319_from_matmul_fsm; // @[Mux.scala:30:73] wire _issue_entry_WIRE_320; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_cmd_from_conv_fsm = _issue_entry_WIRE_319_from_conv_fsm; // @[Mux.scala:30:73] wire _issue_entry_T_5727 = issue_sel_0_2 & entries_st_0_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_5728 = issue_sel_1_2 & entries_st_1_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_5729 = issue_sel_2_2 & entries_st_2_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_5730 = issue_sel_3_2 & entries_st_3_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_5731 = _issue_entry_T_5727 | _issue_entry_T_5728; // @[Mux.scala:30:73] wire _issue_entry_T_5732 = _issue_entry_T_5731 | _issue_entry_T_5729; // @[Mux.scala:30:73] wire _issue_entry_T_5733 = _issue_entry_T_5732 | _issue_entry_T_5730; // @[Mux.scala:30:73] assign _issue_entry_WIRE_320 = _issue_entry_T_5733; // @[Mux.scala:30:73] assign _issue_entry_WIRE_319_from_conv_fsm = _issue_entry_WIRE_320; // @[Mux.scala:30:73] wire _issue_entry_T_5734 = issue_sel_0_2 & entries_st_0_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_5735 = issue_sel_1_2 & entries_st_1_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_5736 = issue_sel_2_2 & entries_st_2_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_5737 = issue_sel_3_2 & entries_st_3_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30] wire _issue_entry_T_5738 = _issue_entry_T_5734 | _issue_entry_T_5735; // @[Mux.scala:30:73] wire _issue_entry_T_5739 = _issue_entry_T_5738 | _issue_entry_T_5736; // @[Mux.scala:30:73] wire _issue_entry_T_5740 = _issue_entry_T_5739 | _issue_entry_T_5737; // @[Mux.scala:30:73] assign _issue_entry_WIRE_321 = _issue_entry_T_5740; // @[Mux.scala:30:73] assign _issue_entry_WIRE_319_from_matmul_fsm = _issue_entry_WIRE_321; // @[Mux.scala:30:73] wire _issue_entry_WIRE_324; // @[Mux.scala:30:73] assign _issue_entry_WIRE_319_rob_id_valid = _issue_entry_WIRE_322_valid; // @[Mux.scala:30:73] wire [5:0] _issue_entry_WIRE_323; // @[Mux.scala:30:73] assign _issue_entry_WIRE_319_rob_id_bits = _issue_entry_WIRE_322_bits; // @[Mux.scala:30:73] wire [5:0] _issue_entry_T_5741 = issue_sel_0_2 ? entries_st_0_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30] wire [5:0] _issue_entry_T_5742 = issue_sel_1_2 ? entries_st_1_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30] wire [5:0] _issue_entry_T_5743 = issue_sel_2_2 ? entries_st_2_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30] wire [5:0] _issue_entry_T_5744 = issue_sel_3_2 ? entries_st_3_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30] wire [5:0] _issue_entry_T_5745 = _issue_entry_T_5741 | _issue_entry_T_5742; // @[Mux.scala:30:73] wire [5:0] _issue_entry_T_5746 = _issue_entry_T_5745 | _issue_entry_T_5743; // @[Mux.scala:30:73] wire [5:0] _issue_entry_T_5747 = _issue_entry_T_5746 | _issue_entry_T_5744; // @[Mux.scala:30:73] assign _issue_entry_WIRE_323 = _issue_entry_T_5747; // @[Mux.scala:30:73] assign _issue_entry_WIRE_322_bits = _issue_entry_WIRE_323; // @[Mux.scala:30:73] wire _issue_entry_T_5748 = issue_sel_0_2 & entries_st_0_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_5749 = issue_sel_1_2 & entries_st_1_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_5750 = issue_sel_2_2 & entries_st_2_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_5751 = issue_sel_3_2 & entries_st_3_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_5752 = _issue_entry_T_5748 | _issue_entry_T_5749; // @[Mux.scala:30:73] wire _issue_entry_T_5753 = _issue_entry_T_5752 | _issue_entry_T_5750; // @[Mux.scala:30:73] wire _issue_entry_T_5754 = _issue_entry_T_5753 | _issue_entry_T_5751; // @[Mux.scala:30:73] assign _issue_entry_WIRE_324 = _issue_entry_T_5754; // @[Mux.scala:30:73] assign _issue_entry_WIRE_322_valid = _issue_entry_WIRE_324; // @[Mux.scala:30:73] wire [6:0] _issue_entry_WIRE_366_funct; // @[Mux.scala:30:73] assign _issue_entry_WIRE_319_cmd_inst_funct = _issue_entry_WIRE_325_inst_funct; // @[Mux.scala:30:73] wire [4:0] _issue_entry_WIRE_366_rs2; // @[Mux.scala:30:73] assign _issue_entry_WIRE_319_cmd_inst_rs2 = _issue_entry_WIRE_325_inst_rs2; // @[Mux.scala:30:73] wire [4:0] _issue_entry_WIRE_366_rs1; // @[Mux.scala:30:73] assign _issue_entry_WIRE_319_cmd_inst_rs1 = _issue_entry_WIRE_325_inst_rs1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_366_xd; // @[Mux.scala:30:73] assign _issue_entry_WIRE_319_cmd_inst_xd = _issue_entry_WIRE_325_inst_xd; // @[Mux.scala:30:73] wire _issue_entry_WIRE_366_xs1; // @[Mux.scala:30:73] assign _issue_entry_WIRE_319_cmd_inst_xs1 = _issue_entry_WIRE_325_inst_xs1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_366_xs2; // @[Mux.scala:30:73] assign _issue_entry_WIRE_319_cmd_inst_xs2 = _issue_entry_WIRE_325_inst_xs2; // @[Mux.scala:30:73] wire [4:0] _issue_entry_WIRE_366_rd; // @[Mux.scala:30:73] assign _issue_entry_WIRE_319_cmd_inst_rd = _issue_entry_WIRE_325_inst_rd; // @[Mux.scala:30:73] wire [6:0] _issue_entry_WIRE_366_opcode; // @[Mux.scala:30:73] assign _issue_entry_WIRE_319_cmd_inst_opcode = _issue_entry_WIRE_325_inst_opcode; // @[Mux.scala:30:73] wire [63:0] _issue_entry_WIRE_365; // @[Mux.scala:30:73] assign _issue_entry_WIRE_319_cmd_rs1 = _issue_entry_WIRE_325_rs1; // @[Mux.scala:30:73] wire [63:0] _issue_entry_WIRE_364; // @[Mux.scala:30:73] assign _issue_entry_WIRE_319_cmd_rs2 = _issue_entry_WIRE_325_rs2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_326_debug; // @[Mux.scala:30:73] assign _issue_entry_WIRE_319_cmd_status_debug = _issue_entry_WIRE_325_status_debug; // @[Mux.scala:30:73] wire _issue_entry_WIRE_326_cease; // @[Mux.scala:30:73] assign _issue_entry_WIRE_319_cmd_status_cease = _issue_entry_WIRE_325_status_cease; // @[Mux.scala:30:73] wire _issue_entry_WIRE_326_wfi; // @[Mux.scala:30:73] assign _issue_entry_WIRE_319_cmd_status_wfi = _issue_entry_WIRE_325_status_wfi; // @[Mux.scala:30:73] wire [31:0] _issue_entry_WIRE_326_isa; // @[Mux.scala:30:73] assign _issue_entry_WIRE_319_cmd_status_isa = _issue_entry_WIRE_325_status_isa; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_326_dprv; // @[Mux.scala:30:73] assign _issue_entry_WIRE_319_cmd_status_dprv = _issue_entry_WIRE_325_status_dprv; // @[Mux.scala:30:73] wire _issue_entry_WIRE_326_dv; // @[Mux.scala:30:73] assign _issue_entry_WIRE_319_cmd_status_dv = _issue_entry_WIRE_325_status_dv; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_326_prv; // @[Mux.scala:30:73] assign _issue_entry_WIRE_319_cmd_status_prv = _issue_entry_WIRE_325_status_prv; // @[Mux.scala:30:73] wire _issue_entry_WIRE_326_v; // @[Mux.scala:30:73] assign _issue_entry_WIRE_319_cmd_status_v = _issue_entry_WIRE_325_status_v; // @[Mux.scala:30:73] wire _issue_entry_WIRE_326_sd; // @[Mux.scala:30:73] assign _issue_entry_WIRE_319_cmd_status_sd = _issue_entry_WIRE_325_status_sd; // @[Mux.scala:30:73] wire [22:0] _issue_entry_WIRE_326_zero2; // @[Mux.scala:30:73] assign _issue_entry_WIRE_319_cmd_status_zero2 = _issue_entry_WIRE_325_status_zero2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_326_mpv; // @[Mux.scala:30:73] assign _issue_entry_WIRE_319_cmd_status_mpv = _issue_entry_WIRE_325_status_mpv; // @[Mux.scala:30:73] wire _issue_entry_WIRE_326_gva; // @[Mux.scala:30:73] assign _issue_entry_WIRE_319_cmd_status_gva = _issue_entry_WIRE_325_status_gva; // @[Mux.scala:30:73] wire _issue_entry_WIRE_326_mbe; // @[Mux.scala:30:73] assign _issue_entry_WIRE_319_cmd_status_mbe = _issue_entry_WIRE_325_status_mbe; // @[Mux.scala:30:73] wire _issue_entry_WIRE_326_sbe; // @[Mux.scala:30:73] assign _issue_entry_WIRE_319_cmd_status_sbe = _issue_entry_WIRE_325_status_sbe; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_326_sxl; // @[Mux.scala:30:73] assign _issue_entry_WIRE_319_cmd_status_sxl = _issue_entry_WIRE_325_status_sxl; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_326_uxl; // @[Mux.scala:30:73] assign _issue_entry_WIRE_319_cmd_status_uxl = _issue_entry_WIRE_325_status_uxl; // @[Mux.scala:30:73] wire _issue_entry_WIRE_326_sd_rv32; // @[Mux.scala:30:73] assign _issue_entry_WIRE_319_cmd_status_sd_rv32 = _issue_entry_WIRE_325_status_sd_rv32; // @[Mux.scala:30:73] wire [7:0] _issue_entry_WIRE_326_zero1; // @[Mux.scala:30:73] assign _issue_entry_WIRE_319_cmd_status_zero1 = _issue_entry_WIRE_325_status_zero1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_326_tsr; // @[Mux.scala:30:73] assign _issue_entry_WIRE_319_cmd_status_tsr = _issue_entry_WIRE_325_status_tsr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_326_tw; // @[Mux.scala:30:73] assign _issue_entry_WIRE_319_cmd_status_tw = _issue_entry_WIRE_325_status_tw; // @[Mux.scala:30:73] wire _issue_entry_WIRE_326_tvm; // @[Mux.scala:30:73] assign _issue_entry_WIRE_319_cmd_status_tvm = _issue_entry_WIRE_325_status_tvm; // @[Mux.scala:30:73] wire _issue_entry_WIRE_326_mxr; // @[Mux.scala:30:73] assign _issue_entry_WIRE_319_cmd_status_mxr = _issue_entry_WIRE_325_status_mxr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_326_sum; // @[Mux.scala:30:73] assign _issue_entry_WIRE_319_cmd_status_sum = _issue_entry_WIRE_325_status_sum; // @[Mux.scala:30:73] wire _issue_entry_WIRE_326_mprv; // @[Mux.scala:30:73] assign _issue_entry_WIRE_319_cmd_status_mprv = _issue_entry_WIRE_325_status_mprv; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_326_xs; // @[Mux.scala:30:73] assign _issue_entry_WIRE_319_cmd_status_xs = _issue_entry_WIRE_325_status_xs; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_326_fs; // @[Mux.scala:30:73] assign _issue_entry_WIRE_319_cmd_status_fs = _issue_entry_WIRE_325_status_fs; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_326_mpp; // @[Mux.scala:30:73] assign _issue_entry_WIRE_319_cmd_status_mpp = _issue_entry_WIRE_325_status_mpp; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_326_vs; // @[Mux.scala:30:73] assign _issue_entry_WIRE_319_cmd_status_vs = _issue_entry_WIRE_325_status_vs; // @[Mux.scala:30:73] wire _issue_entry_WIRE_326_spp; // @[Mux.scala:30:73] assign _issue_entry_WIRE_319_cmd_status_spp = _issue_entry_WIRE_325_status_spp; // @[Mux.scala:30:73] wire _issue_entry_WIRE_326_mpie; // @[Mux.scala:30:73] assign _issue_entry_WIRE_319_cmd_status_mpie = _issue_entry_WIRE_325_status_mpie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_326_ube; // @[Mux.scala:30:73] assign _issue_entry_WIRE_319_cmd_status_ube = _issue_entry_WIRE_325_status_ube; // @[Mux.scala:30:73] wire _issue_entry_WIRE_326_spie; // @[Mux.scala:30:73] assign _issue_entry_WIRE_319_cmd_status_spie = _issue_entry_WIRE_325_status_spie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_326_upie; // @[Mux.scala:30:73] assign _issue_entry_WIRE_319_cmd_status_upie = _issue_entry_WIRE_325_status_upie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_326_mie; // @[Mux.scala:30:73] assign _issue_entry_WIRE_319_cmd_status_mie = _issue_entry_WIRE_325_status_mie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_326_hie; // @[Mux.scala:30:73] assign _issue_entry_WIRE_319_cmd_status_hie = _issue_entry_WIRE_325_status_hie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_326_sie; // @[Mux.scala:30:73] assign _issue_entry_WIRE_319_cmd_status_sie = _issue_entry_WIRE_325_status_sie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_326_uie; // @[Mux.scala:30:73] assign _issue_entry_WIRE_319_cmd_status_uie = _issue_entry_WIRE_325_status_uie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_363; // @[Mux.scala:30:73] assign _issue_entry_WIRE_325_status_debug = _issue_entry_WIRE_326_debug; // @[Mux.scala:30:73] wire _issue_entry_WIRE_362; // @[Mux.scala:30:73] assign _issue_entry_WIRE_325_status_cease = _issue_entry_WIRE_326_cease; // @[Mux.scala:30:73] wire _issue_entry_WIRE_361; // @[Mux.scala:30:73] assign _issue_entry_WIRE_325_status_wfi = _issue_entry_WIRE_326_wfi; // @[Mux.scala:30:73] wire [31:0] _issue_entry_WIRE_360; // @[Mux.scala:30:73] assign _issue_entry_WIRE_325_status_isa = _issue_entry_WIRE_326_isa; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_359; // @[Mux.scala:30:73] assign _issue_entry_WIRE_325_status_dprv = _issue_entry_WIRE_326_dprv; // @[Mux.scala:30:73] wire _issue_entry_WIRE_358; // @[Mux.scala:30:73] assign _issue_entry_WIRE_325_status_dv = _issue_entry_WIRE_326_dv; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_357; // @[Mux.scala:30:73] assign _issue_entry_WIRE_325_status_prv = _issue_entry_WIRE_326_prv; // @[Mux.scala:30:73] wire _issue_entry_WIRE_356; // @[Mux.scala:30:73] assign _issue_entry_WIRE_325_status_v = _issue_entry_WIRE_326_v; // @[Mux.scala:30:73] wire _issue_entry_WIRE_355; // @[Mux.scala:30:73] assign _issue_entry_WIRE_325_status_sd = _issue_entry_WIRE_326_sd; // @[Mux.scala:30:73] wire [22:0] _issue_entry_WIRE_354; // @[Mux.scala:30:73] assign _issue_entry_WIRE_325_status_zero2 = _issue_entry_WIRE_326_zero2; // @[Mux.scala:30:73] wire _issue_entry_WIRE_353; // @[Mux.scala:30:73] assign _issue_entry_WIRE_325_status_mpv = _issue_entry_WIRE_326_mpv; // @[Mux.scala:30:73] wire _issue_entry_WIRE_352; // @[Mux.scala:30:73] assign _issue_entry_WIRE_325_status_gva = _issue_entry_WIRE_326_gva; // @[Mux.scala:30:73] wire _issue_entry_WIRE_351; // @[Mux.scala:30:73] assign _issue_entry_WIRE_325_status_mbe = _issue_entry_WIRE_326_mbe; // @[Mux.scala:30:73] wire _issue_entry_WIRE_350; // @[Mux.scala:30:73] assign _issue_entry_WIRE_325_status_sbe = _issue_entry_WIRE_326_sbe; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_349; // @[Mux.scala:30:73] assign _issue_entry_WIRE_325_status_sxl = _issue_entry_WIRE_326_sxl; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_348; // @[Mux.scala:30:73] assign _issue_entry_WIRE_325_status_uxl = _issue_entry_WIRE_326_uxl; // @[Mux.scala:30:73] wire _issue_entry_WIRE_347; // @[Mux.scala:30:73] assign _issue_entry_WIRE_325_status_sd_rv32 = _issue_entry_WIRE_326_sd_rv32; // @[Mux.scala:30:73] wire [7:0] _issue_entry_WIRE_346; // @[Mux.scala:30:73] assign _issue_entry_WIRE_325_status_zero1 = _issue_entry_WIRE_326_zero1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_345; // @[Mux.scala:30:73] assign _issue_entry_WIRE_325_status_tsr = _issue_entry_WIRE_326_tsr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_344; // @[Mux.scala:30:73] assign _issue_entry_WIRE_325_status_tw = _issue_entry_WIRE_326_tw; // @[Mux.scala:30:73] wire _issue_entry_WIRE_343; // @[Mux.scala:30:73] assign _issue_entry_WIRE_325_status_tvm = _issue_entry_WIRE_326_tvm; // @[Mux.scala:30:73] wire _issue_entry_WIRE_342; // @[Mux.scala:30:73] assign _issue_entry_WIRE_325_status_mxr = _issue_entry_WIRE_326_mxr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_341; // @[Mux.scala:30:73] assign _issue_entry_WIRE_325_status_sum = _issue_entry_WIRE_326_sum; // @[Mux.scala:30:73] wire _issue_entry_WIRE_340; // @[Mux.scala:30:73] assign _issue_entry_WIRE_325_status_mprv = _issue_entry_WIRE_326_mprv; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_339; // @[Mux.scala:30:73] assign _issue_entry_WIRE_325_status_xs = _issue_entry_WIRE_326_xs; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_338; // @[Mux.scala:30:73] assign _issue_entry_WIRE_325_status_fs = _issue_entry_WIRE_326_fs; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_337; // @[Mux.scala:30:73] assign _issue_entry_WIRE_325_status_mpp = _issue_entry_WIRE_326_mpp; // @[Mux.scala:30:73] wire [1:0] _issue_entry_WIRE_336; // @[Mux.scala:30:73] assign _issue_entry_WIRE_325_status_vs = _issue_entry_WIRE_326_vs; // @[Mux.scala:30:73] wire _issue_entry_WIRE_335; // @[Mux.scala:30:73] assign _issue_entry_WIRE_325_status_spp = _issue_entry_WIRE_326_spp; // @[Mux.scala:30:73] wire _issue_entry_WIRE_334; // @[Mux.scala:30:73] assign _issue_entry_WIRE_325_status_mpie = _issue_entry_WIRE_326_mpie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_333; // @[Mux.scala:30:73] assign _issue_entry_WIRE_325_status_ube = _issue_entry_WIRE_326_ube; // @[Mux.scala:30:73] wire _issue_entry_WIRE_332; // @[Mux.scala:30:73] assign _issue_entry_WIRE_325_status_spie = _issue_entry_WIRE_326_spie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_331; // @[Mux.scala:30:73] assign _issue_entry_WIRE_325_status_upie = _issue_entry_WIRE_326_upie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_330; // @[Mux.scala:30:73] assign _issue_entry_WIRE_325_status_mie = _issue_entry_WIRE_326_mie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_329; // @[Mux.scala:30:73] assign _issue_entry_WIRE_325_status_hie = _issue_entry_WIRE_326_hie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_328; // @[Mux.scala:30:73] assign _issue_entry_WIRE_325_status_sie = _issue_entry_WIRE_326_sie; // @[Mux.scala:30:73] wire _issue_entry_WIRE_327; // @[Mux.scala:30:73] assign _issue_entry_WIRE_325_status_uie = _issue_entry_WIRE_326_uie; // @[Mux.scala:30:73] wire _issue_entry_T_5755 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30] wire _issue_entry_T_5756 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30] wire _issue_entry_T_5757 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30] wire _issue_entry_T_5758 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30] wire _issue_entry_T_5759 = _issue_entry_T_5755 | _issue_entry_T_5756; // @[Mux.scala:30:73] wire _issue_entry_T_5760 = _issue_entry_T_5759 | _issue_entry_T_5757; // @[Mux.scala:30:73] wire _issue_entry_T_5761 = _issue_entry_T_5760 | _issue_entry_T_5758; // @[Mux.scala:30:73] assign _issue_entry_WIRE_327 = _issue_entry_T_5761; // @[Mux.scala:30:73] assign _issue_entry_WIRE_326_uie = _issue_entry_WIRE_327; // @[Mux.scala:30:73] wire _issue_entry_T_5762 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30] wire _issue_entry_T_5763 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30] wire _issue_entry_T_5764 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30] wire _issue_entry_T_5765 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30] wire _issue_entry_T_5766 = _issue_entry_T_5762 | _issue_entry_T_5763; // @[Mux.scala:30:73] wire _issue_entry_T_5767 = _issue_entry_T_5766 | _issue_entry_T_5764; // @[Mux.scala:30:73] wire _issue_entry_T_5768 = _issue_entry_T_5767 | _issue_entry_T_5765; // @[Mux.scala:30:73] assign _issue_entry_WIRE_328 = _issue_entry_T_5768; // @[Mux.scala:30:73] assign _issue_entry_WIRE_326_sie = _issue_entry_WIRE_328; // @[Mux.scala:30:73] wire _issue_entry_T_5769 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30] wire _issue_entry_T_5770 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30] wire _issue_entry_T_5771 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30] wire _issue_entry_T_5772 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30] wire _issue_entry_T_5773 = _issue_entry_T_5769 | _issue_entry_T_5770; // @[Mux.scala:30:73] wire _issue_entry_T_5774 = _issue_entry_T_5773 | _issue_entry_T_5771; // @[Mux.scala:30:73] wire _issue_entry_T_5775 = _issue_entry_T_5774 | _issue_entry_T_5772; // @[Mux.scala:30:73] assign _issue_entry_WIRE_329 = _issue_entry_T_5775; // @[Mux.scala:30:73] assign _issue_entry_WIRE_326_hie = _issue_entry_WIRE_329; // @[Mux.scala:30:73] wire _issue_entry_T_5776 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30] wire _issue_entry_T_5777 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30] wire _issue_entry_T_5778 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30] wire _issue_entry_T_5779 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30] wire _issue_entry_T_5780 = _issue_entry_T_5776 | _issue_entry_T_5777; // @[Mux.scala:30:73] wire _issue_entry_T_5781 = _issue_entry_T_5780 | _issue_entry_T_5778; // @[Mux.scala:30:73] wire _issue_entry_T_5782 = _issue_entry_T_5781 | _issue_entry_T_5779; // @[Mux.scala:30:73] assign _issue_entry_WIRE_330 = _issue_entry_T_5782; // @[Mux.scala:30:73] assign _issue_entry_WIRE_326_mie = _issue_entry_WIRE_330; // @[Mux.scala:30:73] wire _issue_entry_T_5783 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30] wire _issue_entry_T_5784 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30] wire _issue_entry_T_5785 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30] wire _issue_entry_T_5786 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30] wire _issue_entry_T_5787 = _issue_entry_T_5783 | _issue_entry_T_5784; // @[Mux.scala:30:73] wire _issue_entry_T_5788 = _issue_entry_T_5787 | _issue_entry_T_5785; // @[Mux.scala:30:73] wire _issue_entry_T_5789 = _issue_entry_T_5788 | _issue_entry_T_5786; // @[Mux.scala:30:73] assign _issue_entry_WIRE_331 = _issue_entry_T_5789; // @[Mux.scala:30:73] assign _issue_entry_WIRE_326_upie = _issue_entry_WIRE_331; // @[Mux.scala:30:73] wire _issue_entry_T_5790 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30] wire _issue_entry_T_5791 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30] wire _issue_entry_T_5792 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30] wire _issue_entry_T_5793 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30] wire _issue_entry_T_5794 = _issue_entry_T_5790 | _issue_entry_T_5791; // @[Mux.scala:30:73] wire _issue_entry_T_5795 = _issue_entry_T_5794 | _issue_entry_T_5792; // @[Mux.scala:30:73] wire _issue_entry_T_5796 = _issue_entry_T_5795 | _issue_entry_T_5793; // @[Mux.scala:30:73] assign _issue_entry_WIRE_332 = _issue_entry_T_5796; // @[Mux.scala:30:73] assign _issue_entry_WIRE_326_spie = _issue_entry_WIRE_332; // @[Mux.scala:30:73] wire _issue_entry_T_5797 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30] wire _issue_entry_T_5798 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30] wire _issue_entry_T_5799 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30] wire _issue_entry_T_5800 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30] wire _issue_entry_T_5801 = _issue_entry_T_5797 | _issue_entry_T_5798; // @[Mux.scala:30:73] wire _issue_entry_T_5802 = _issue_entry_T_5801 | _issue_entry_T_5799; // @[Mux.scala:30:73] wire _issue_entry_T_5803 = _issue_entry_T_5802 | _issue_entry_T_5800; // @[Mux.scala:30:73] assign _issue_entry_WIRE_333 = _issue_entry_T_5803; // @[Mux.scala:30:73] assign _issue_entry_WIRE_326_ube = _issue_entry_WIRE_333; // @[Mux.scala:30:73] wire _issue_entry_T_5804 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30] wire _issue_entry_T_5805 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30] wire _issue_entry_T_5806 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30] wire _issue_entry_T_5807 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30] wire _issue_entry_T_5808 = _issue_entry_T_5804 | _issue_entry_T_5805; // @[Mux.scala:30:73] wire _issue_entry_T_5809 = _issue_entry_T_5808 | _issue_entry_T_5806; // @[Mux.scala:30:73] wire _issue_entry_T_5810 = _issue_entry_T_5809 | _issue_entry_T_5807; // @[Mux.scala:30:73] assign _issue_entry_WIRE_334 = _issue_entry_T_5810; // @[Mux.scala:30:73] assign _issue_entry_WIRE_326_mpie = _issue_entry_WIRE_334; // @[Mux.scala:30:73] wire _issue_entry_T_5811 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30] wire _issue_entry_T_5812 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30] wire _issue_entry_T_5813 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30] wire _issue_entry_T_5814 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30] wire _issue_entry_T_5815 = _issue_entry_T_5811 | _issue_entry_T_5812; // @[Mux.scala:30:73] wire _issue_entry_T_5816 = _issue_entry_T_5815 | _issue_entry_T_5813; // @[Mux.scala:30:73] wire _issue_entry_T_5817 = _issue_entry_T_5816 | _issue_entry_T_5814; // @[Mux.scala:30:73] assign _issue_entry_WIRE_335 = _issue_entry_T_5817; // @[Mux.scala:30:73] assign _issue_entry_WIRE_326_spp = _issue_entry_WIRE_335; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_5818 = issue_sel_0_2 ? entries_st_0_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_5819 = issue_sel_1_2 ? entries_st_1_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_5820 = issue_sel_2_2 ? entries_st_2_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_5821 = issue_sel_3_2 ? entries_st_3_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_5822 = _issue_entry_T_5818 | _issue_entry_T_5819; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_5823 = _issue_entry_T_5822 | _issue_entry_T_5820; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_5824 = _issue_entry_T_5823 | _issue_entry_T_5821; // @[Mux.scala:30:73] assign _issue_entry_WIRE_336 = _issue_entry_T_5824; // @[Mux.scala:30:73] assign _issue_entry_WIRE_326_vs = _issue_entry_WIRE_336; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_5825 = issue_sel_0_2 ? entries_st_0_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_5826 = issue_sel_1_2 ? entries_st_1_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_5827 = issue_sel_2_2 ? entries_st_2_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_5828 = issue_sel_3_2 ? entries_st_3_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_5829 = _issue_entry_T_5825 | _issue_entry_T_5826; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_5830 = _issue_entry_T_5829 | _issue_entry_T_5827; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_5831 = _issue_entry_T_5830 | _issue_entry_T_5828; // @[Mux.scala:30:73] assign _issue_entry_WIRE_337 = _issue_entry_T_5831; // @[Mux.scala:30:73] assign _issue_entry_WIRE_326_mpp = _issue_entry_WIRE_337; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_5832 = issue_sel_0_2 ? entries_st_0_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_5833 = issue_sel_1_2 ? entries_st_1_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_5834 = issue_sel_2_2 ? entries_st_2_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_5835 = issue_sel_3_2 ? entries_st_3_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_5836 = _issue_entry_T_5832 | _issue_entry_T_5833; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_5837 = _issue_entry_T_5836 | _issue_entry_T_5834; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_5838 = _issue_entry_T_5837 | _issue_entry_T_5835; // @[Mux.scala:30:73] assign _issue_entry_WIRE_338 = _issue_entry_T_5838; // @[Mux.scala:30:73] assign _issue_entry_WIRE_326_fs = _issue_entry_WIRE_338; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_5839 = issue_sel_0_2 ? entries_st_0_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_5840 = issue_sel_1_2 ? entries_st_1_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_5841 = issue_sel_2_2 ? entries_st_2_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_5842 = issue_sel_3_2 ? entries_st_3_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_5843 = _issue_entry_T_5839 | _issue_entry_T_5840; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_5844 = _issue_entry_T_5843 | _issue_entry_T_5841; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_5845 = _issue_entry_T_5844 | _issue_entry_T_5842; // @[Mux.scala:30:73] assign _issue_entry_WIRE_339 = _issue_entry_T_5845; // @[Mux.scala:30:73] assign _issue_entry_WIRE_326_xs = _issue_entry_WIRE_339; // @[Mux.scala:30:73] wire _issue_entry_T_5846 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30] wire _issue_entry_T_5847 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30] wire _issue_entry_T_5848 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30] wire _issue_entry_T_5849 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30] wire _issue_entry_T_5850 = _issue_entry_T_5846 | _issue_entry_T_5847; // @[Mux.scala:30:73] wire _issue_entry_T_5851 = _issue_entry_T_5850 | _issue_entry_T_5848; // @[Mux.scala:30:73] wire _issue_entry_T_5852 = _issue_entry_T_5851 | _issue_entry_T_5849; // @[Mux.scala:30:73] assign _issue_entry_WIRE_340 = _issue_entry_T_5852; // @[Mux.scala:30:73] assign _issue_entry_WIRE_326_mprv = _issue_entry_WIRE_340; // @[Mux.scala:30:73] wire _issue_entry_T_5853 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30] wire _issue_entry_T_5854 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30] wire _issue_entry_T_5855 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30] wire _issue_entry_T_5856 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30] wire _issue_entry_T_5857 = _issue_entry_T_5853 | _issue_entry_T_5854; // @[Mux.scala:30:73] wire _issue_entry_T_5858 = _issue_entry_T_5857 | _issue_entry_T_5855; // @[Mux.scala:30:73] wire _issue_entry_T_5859 = _issue_entry_T_5858 | _issue_entry_T_5856; // @[Mux.scala:30:73] assign _issue_entry_WIRE_341 = _issue_entry_T_5859; // @[Mux.scala:30:73] assign _issue_entry_WIRE_326_sum = _issue_entry_WIRE_341; // @[Mux.scala:30:73] wire _issue_entry_T_5860 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30] wire _issue_entry_T_5861 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30] wire _issue_entry_T_5862 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30] wire _issue_entry_T_5863 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30] wire _issue_entry_T_5864 = _issue_entry_T_5860 | _issue_entry_T_5861; // @[Mux.scala:30:73] wire _issue_entry_T_5865 = _issue_entry_T_5864 | _issue_entry_T_5862; // @[Mux.scala:30:73] wire _issue_entry_T_5866 = _issue_entry_T_5865 | _issue_entry_T_5863; // @[Mux.scala:30:73] assign _issue_entry_WIRE_342 = _issue_entry_T_5866; // @[Mux.scala:30:73] assign _issue_entry_WIRE_326_mxr = _issue_entry_WIRE_342; // @[Mux.scala:30:73] wire _issue_entry_T_5867 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30] wire _issue_entry_T_5868 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30] wire _issue_entry_T_5869 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30] wire _issue_entry_T_5870 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30] wire _issue_entry_T_5871 = _issue_entry_T_5867 | _issue_entry_T_5868; // @[Mux.scala:30:73] wire _issue_entry_T_5872 = _issue_entry_T_5871 | _issue_entry_T_5869; // @[Mux.scala:30:73] wire _issue_entry_T_5873 = _issue_entry_T_5872 | _issue_entry_T_5870; // @[Mux.scala:30:73] assign _issue_entry_WIRE_343 = _issue_entry_T_5873; // @[Mux.scala:30:73] assign _issue_entry_WIRE_326_tvm = _issue_entry_WIRE_343; // @[Mux.scala:30:73] wire _issue_entry_T_5874 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30] wire _issue_entry_T_5875 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30] wire _issue_entry_T_5876 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30] wire _issue_entry_T_5877 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30] wire _issue_entry_T_5878 = _issue_entry_T_5874 | _issue_entry_T_5875; // @[Mux.scala:30:73] wire _issue_entry_T_5879 = _issue_entry_T_5878 | _issue_entry_T_5876; // @[Mux.scala:30:73] wire _issue_entry_T_5880 = _issue_entry_T_5879 | _issue_entry_T_5877; // @[Mux.scala:30:73] assign _issue_entry_WIRE_344 = _issue_entry_T_5880; // @[Mux.scala:30:73] assign _issue_entry_WIRE_326_tw = _issue_entry_WIRE_344; // @[Mux.scala:30:73] wire _issue_entry_T_5881 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30] wire _issue_entry_T_5882 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30] wire _issue_entry_T_5883 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30] wire _issue_entry_T_5884 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30] wire _issue_entry_T_5885 = _issue_entry_T_5881 | _issue_entry_T_5882; // @[Mux.scala:30:73] wire _issue_entry_T_5886 = _issue_entry_T_5885 | _issue_entry_T_5883; // @[Mux.scala:30:73] wire _issue_entry_T_5887 = _issue_entry_T_5886 | _issue_entry_T_5884; // @[Mux.scala:30:73] assign _issue_entry_WIRE_345 = _issue_entry_T_5887; // @[Mux.scala:30:73] assign _issue_entry_WIRE_326_tsr = _issue_entry_WIRE_345; // @[Mux.scala:30:73] wire [7:0] _issue_entry_T_5888 = issue_sel_0_2 ? entries_st_0_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30] wire [7:0] _issue_entry_T_5889 = issue_sel_1_2 ? entries_st_1_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30] wire [7:0] _issue_entry_T_5890 = issue_sel_2_2 ? entries_st_2_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30] wire [7:0] _issue_entry_T_5891 = issue_sel_3_2 ? entries_st_3_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30] wire [7:0] _issue_entry_T_5892 = _issue_entry_T_5888 | _issue_entry_T_5889; // @[Mux.scala:30:73] wire [7:0] _issue_entry_T_5893 = _issue_entry_T_5892 | _issue_entry_T_5890; // @[Mux.scala:30:73] wire [7:0] _issue_entry_T_5894 = _issue_entry_T_5893 | _issue_entry_T_5891; // @[Mux.scala:30:73] assign _issue_entry_WIRE_346 = _issue_entry_T_5894; // @[Mux.scala:30:73] assign _issue_entry_WIRE_326_zero1 = _issue_entry_WIRE_346; // @[Mux.scala:30:73] wire _issue_entry_T_5895 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30] wire _issue_entry_T_5896 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30] wire _issue_entry_T_5897 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30] wire _issue_entry_T_5898 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30] wire _issue_entry_T_5899 = _issue_entry_T_5895 | _issue_entry_T_5896; // @[Mux.scala:30:73] wire _issue_entry_T_5900 = _issue_entry_T_5899 | _issue_entry_T_5897; // @[Mux.scala:30:73] wire _issue_entry_T_5901 = _issue_entry_T_5900 | _issue_entry_T_5898; // @[Mux.scala:30:73] assign _issue_entry_WIRE_347 = _issue_entry_T_5901; // @[Mux.scala:30:73] assign _issue_entry_WIRE_326_sd_rv32 = _issue_entry_WIRE_347; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_5902 = issue_sel_0_2 ? entries_st_0_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_5903 = issue_sel_1_2 ? entries_st_1_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_5904 = issue_sel_2_2 ? entries_st_2_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_5905 = issue_sel_3_2 ? entries_st_3_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_5906 = _issue_entry_T_5902 | _issue_entry_T_5903; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_5907 = _issue_entry_T_5906 | _issue_entry_T_5904; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_5908 = _issue_entry_T_5907 | _issue_entry_T_5905; // @[Mux.scala:30:73] assign _issue_entry_WIRE_348 = _issue_entry_T_5908; // @[Mux.scala:30:73] assign _issue_entry_WIRE_326_uxl = _issue_entry_WIRE_348; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_5909 = issue_sel_0_2 ? entries_st_0_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_5910 = issue_sel_1_2 ? entries_st_1_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_5911 = issue_sel_2_2 ? entries_st_2_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_5912 = issue_sel_3_2 ? entries_st_3_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_5913 = _issue_entry_T_5909 | _issue_entry_T_5910; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_5914 = _issue_entry_T_5913 | _issue_entry_T_5911; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_5915 = _issue_entry_T_5914 | _issue_entry_T_5912; // @[Mux.scala:30:73] assign _issue_entry_WIRE_349 = _issue_entry_T_5915; // @[Mux.scala:30:73] assign _issue_entry_WIRE_326_sxl = _issue_entry_WIRE_349; // @[Mux.scala:30:73] wire _issue_entry_T_5916 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30] wire _issue_entry_T_5917 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30] wire _issue_entry_T_5918 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30] wire _issue_entry_T_5919 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30] wire _issue_entry_T_5920 = _issue_entry_T_5916 | _issue_entry_T_5917; // @[Mux.scala:30:73] wire _issue_entry_T_5921 = _issue_entry_T_5920 | _issue_entry_T_5918; // @[Mux.scala:30:73] wire _issue_entry_T_5922 = _issue_entry_T_5921 | _issue_entry_T_5919; // @[Mux.scala:30:73] assign _issue_entry_WIRE_350 = _issue_entry_T_5922; // @[Mux.scala:30:73] assign _issue_entry_WIRE_326_sbe = _issue_entry_WIRE_350; // @[Mux.scala:30:73] wire _issue_entry_T_5923 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30] wire _issue_entry_T_5924 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30] wire _issue_entry_T_5925 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30] wire _issue_entry_T_5926 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30] wire _issue_entry_T_5927 = _issue_entry_T_5923 | _issue_entry_T_5924; // @[Mux.scala:30:73] wire _issue_entry_T_5928 = _issue_entry_T_5927 | _issue_entry_T_5925; // @[Mux.scala:30:73] wire _issue_entry_T_5929 = _issue_entry_T_5928 | _issue_entry_T_5926; // @[Mux.scala:30:73] assign _issue_entry_WIRE_351 = _issue_entry_T_5929; // @[Mux.scala:30:73] assign _issue_entry_WIRE_326_mbe = _issue_entry_WIRE_351; // @[Mux.scala:30:73] wire _issue_entry_T_5930 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30] wire _issue_entry_T_5931 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30] wire _issue_entry_T_5932 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30] wire _issue_entry_T_5933 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30] wire _issue_entry_T_5934 = _issue_entry_T_5930 | _issue_entry_T_5931; // @[Mux.scala:30:73] wire _issue_entry_T_5935 = _issue_entry_T_5934 | _issue_entry_T_5932; // @[Mux.scala:30:73] wire _issue_entry_T_5936 = _issue_entry_T_5935 | _issue_entry_T_5933; // @[Mux.scala:30:73] assign _issue_entry_WIRE_352 = _issue_entry_T_5936; // @[Mux.scala:30:73] assign _issue_entry_WIRE_326_gva = _issue_entry_WIRE_352; // @[Mux.scala:30:73] wire _issue_entry_T_5937 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30] wire _issue_entry_T_5938 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30] wire _issue_entry_T_5939 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30] wire _issue_entry_T_5940 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30] wire _issue_entry_T_5941 = _issue_entry_T_5937 | _issue_entry_T_5938; // @[Mux.scala:30:73] wire _issue_entry_T_5942 = _issue_entry_T_5941 | _issue_entry_T_5939; // @[Mux.scala:30:73] wire _issue_entry_T_5943 = _issue_entry_T_5942 | _issue_entry_T_5940; // @[Mux.scala:30:73] assign _issue_entry_WIRE_353 = _issue_entry_T_5943; // @[Mux.scala:30:73] assign _issue_entry_WIRE_326_mpv = _issue_entry_WIRE_353; // @[Mux.scala:30:73] wire [22:0] _issue_entry_T_5944 = issue_sel_0_2 ? entries_st_0_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30] wire [22:0] _issue_entry_T_5945 = issue_sel_1_2 ? entries_st_1_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30] wire [22:0] _issue_entry_T_5946 = issue_sel_2_2 ? entries_st_2_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30] wire [22:0] _issue_entry_T_5947 = issue_sel_3_2 ? entries_st_3_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30] wire [22:0] _issue_entry_T_5948 = _issue_entry_T_5944 | _issue_entry_T_5945; // @[Mux.scala:30:73] wire [22:0] _issue_entry_T_5949 = _issue_entry_T_5948 | _issue_entry_T_5946; // @[Mux.scala:30:73] wire [22:0] _issue_entry_T_5950 = _issue_entry_T_5949 | _issue_entry_T_5947; // @[Mux.scala:30:73] assign _issue_entry_WIRE_354 = _issue_entry_T_5950; // @[Mux.scala:30:73] assign _issue_entry_WIRE_326_zero2 = _issue_entry_WIRE_354; // @[Mux.scala:30:73] wire _issue_entry_T_5951 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30] wire _issue_entry_T_5952 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30] wire _issue_entry_T_5953 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30] wire _issue_entry_T_5954 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30] wire _issue_entry_T_5955 = _issue_entry_T_5951 | _issue_entry_T_5952; // @[Mux.scala:30:73] wire _issue_entry_T_5956 = _issue_entry_T_5955 | _issue_entry_T_5953; // @[Mux.scala:30:73] wire _issue_entry_T_5957 = _issue_entry_T_5956 | _issue_entry_T_5954; // @[Mux.scala:30:73] assign _issue_entry_WIRE_355 = _issue_entry_T_5957; // @[Mux.scala:30:73] assign _issue_entry_WIRE_326_sd = _issue_entry_WIRE_355; // @[Mux.scala:30:73] wire _issue_entry_T_5958 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30] wire _issue_entry_T_5959 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30] wire _issue_entry_T_5960 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30] wire _issue_entry_T_5961 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30] wire _issue_entry_T_5962 = _issue_entry_T_5958 | _issue_entry_T_5959; // @[Mux.scala:30:73] wire _issue_entry_T_5963 = _issue_entry_T_5962 | _issue_entry_T_5960; // @[Mux.scala:30:73] wire _issue_entry_T_5964 = _issue_entry_T_5963 | _issue_entry_T_5961; // @[Mux.scala:30:73] assign _issue_entry_WIRE_356 = _issue_entry_T_5964; // @[Mux.scala:30:73] assign _issue_entry_WIRE_326_v = _issue_entry_WIRE_356; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_5965 = issue_sel_0_2 ? entries_st_0_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_5966 = issue_sel_1_2 ? entries_st_1_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_5967 = issue_sel_2_2 ? entries_st_2_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_5968 = issue_sel_3_2 ? entries_st_3_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_5969 = _issue_entry_T_5965 | _issue_entry_T_5966; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_5970 = _issue_entry_T_5969 | _issue_entry_T_5967; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_5971 = _issue_entry_T_5970 | _issue_entry_T_5968; // @[Mux.scala:30:73] assign _issue_entry_WIRE_357 = _issue_entry_T_5971; // @[Mux.scala:30:73] assign _issue_entry_WIRE_326_prv = _issue_entry_WIRE_357; // @[Mux.scala:30:73] wire _issue_entry_T_5972 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30] wire _issue_entry_T_5973 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30] wire _issue_entry_T_5974 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30] wire _issue_entry_T_5975 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30] wire _issue_entry_T_5976 = _issue_entry_T_5972 | _issue_entry_T_5973; // @[Mux.scala:30:73] wire _issue_entry_T_5977 = _issue_entry_T_5976 | _issue_entry_T_5974; // @[Mux.scala:30:73] wire _issue_entry_T_5978 = _issue_entry_T_5977 | _issue_entry_T_5975; // @[Mux.scala:30:73] assign _issue_entry_WIRE_358 = _issue_entry_T_5978; // @[Mux.scala:30:73] assign _issue_entry_WIRE_326_dv = _issue_entry_WIRE_358; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_5979 = issue_sel_0_2 ? entries_st_0_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_5980 = issue_sel_1_2 ? entries_st_1_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_5981 = issue_sel_2_2 ? entries_st_2_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_5982 = issue_sel_3_2 ? entries_st_3_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_5983 = _issue_entry_T_5979 | _issue_entry_T_5980; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_5984 = _issue_entry_T_5983 | _issue_entry_T_5981; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_5985 = _issue_entry_T_5984 | _issue_entry_T_5982; // @[Mux.scala:30:73] assign _issue_entry_WIRE_359 = _issue_entry_T_5985; // @[Mux.scala:30:73] assign _issue_entry_WIRE_326_dprv = _issue_entry_WIRE_359; // @[Mux.scala:30:73] wire [31:0] _issue_entry_T_5986 = issue_sel_0_2 ? entries_st_0_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_5987 = issue_sel_1_2 ? entries_st_1_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_5988 = issue_sel_2_2 ? entries_st_2_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_5989 = issue_sel_3_2 ? entries_st_3_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30] wire [31:0] _issue_entry_T_5990 = _issue_entry_T_5986 | _issue_entry_T_5987; // @[Mux.scala:30:73] wire [31:0] _issue_entry_T_5991 = _issue_entry_T_5990 | _issue_entry_T_5988; // @[Mux.scala:30:73] wire [31:0] _issue_entry_T_5992 = _issue_entry_T_5991 | _issue_entry_T_5989; // @[Mux.scala:30:73] assign _issue_entry_WIRE_360 = _issue_entry_T_5992; // @[Mux.scala:30:73] assign _issue_entry_WIRE_326_isa = _issue_entry_WIRE_360; // @[Mux.scala:30:73] wire _issue_entry_T_5993 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30] wire _issue_entry_T_5994 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30] wire _issue_entry_T_5995 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30] wire _issue_entry_T_5996 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30] wire _issue_entry_T_5997 = _issue_entry_T_5993 | _issue_entry_T_5994; // @[Mux.scala:30:73] wire _issue_entry_T_5998 = _issue_entry_T_5997 | _issue_entry_T_5995; // @[Mux.scala:30:73] wire _issue_entry_T_5999 = _issue_entry_T_5998 | _issue_entry_T_5996; // @[Mux.scala:30:73] assign _issue_entry_WIRE_361 = _issue_entry_T_5999; // @[Mux.scala:30:73] assign _issue_entry_WIRE_326_wfi = _issue_entry_WIRE_361; // @[Mux.scala:30:73] wire _issue_entry_T_6000 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30] wire _issue_entry_T_6001 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30] wire _issue_entry_T_6002 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30] wire _issue_entry_T_6003 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30] wire _issue_entry_T_6004 = _issue_entry_T_6000 | _issue_entry_T_6001; // @[Mux.scala:30:73] wire _issue_entry_T_6005 = _issue_entry_T_6004 | _issue_entry_T_6002; // @[Mux.scala:30:73] wire _issue_entry_T_6006 = _issue_entry_T_6005 | _issue_entry_T_6003; // @[Mux.scala:30:73] assign _issue_entry_WIRE_362 = _issue_entry_T_6006; // @[Mux.scala:30:73] assign _issue_entry_WIRE_326_cease = _issue_entry_WIRE_362; // @[Mux.scala:30:73] wire _issue_entry_T_6007 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30] wire _issue_entry_T_6008 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30] wire _issue_entry_T_6009 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30] wire _issue_entry_T_6010 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30] wire _issue_entry_T_6011 = _issue_entry_T_6007 | _issue_entry_T_6008; // @[Mux.scala:30:73] wire _issue_entry_T_6012 = _issue_entry_T_6011 | _issue_entry_T_6009; // @[Mux.scala:30:73] wire _issue_entry_T_6013 = _issue_entry_T_6012 | _issue_entry_T_6010; // @[Mux.scala:30:73] assign _issue_entry_WIRE_363 = _issue_entry_T_6013; // @[Mux.scala:30:73] assign _issue_entry_WIRE_326_debug = _issue_entry_WIRE_363; // @[Mux.scala:30:73] wire [63:0] _issue_entry_T_6014 = issue_sel_0_2 ? entries_st_0_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_6015 = issue_sel_1_2 ? entries_st_1_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_6016 = issue_sel_2_2 ? entries_st_2_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_6017 = issue_sel_3_2 ? entries_st_3_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_6018 = _issue_entry_T_6014 | _issue_entry_T_6015; // @[Mux.scala:30:73] wire [63:0] _issue_entry_T_6019 = _issue_entry_T_6018 | _issue_entry_T_6016; // @[Mux.scala:30:73] wire [63:0] _issue_entry_T_6020 = _issue_entry_T_6019 | _issue_entry_T_6017; // @[Mux.scala:30:73] assign _issue_entry_WIRE_364 = _issue_entry_T_6020; // @[Mux.scala:30:73] assign _issue_entry_WIRE_325_rs2 = _issue_entry_WIRE_364; // @[Mux.scala:30:73] wire [63:0] _issue_entry_T_6021 = issue_sel_0_2 ? entries_st_0_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_6022 = issue_sel_1_2 ? entries_st_1_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_6023 = issue_sel_2_2 ? entries_st_2_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_6024 = issue_sel_3_2 ? entries_st_3_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30] wire [63:0] _issue_entry_T_6025 = _issue_entry_T_6021 | _issue_entry_T_6022; // @[Mux.scala:30:73] wire [63:0] _issue_entry_T_6026 = _issue_entry_T_6025 | _issue_entry_T_6023; // @[Mux.scala:30:73] wire [63:0] _issue_entry_T_6027 = _issue_entry_T_6026 | _issue_entry_T_6024; // @[Mux.scala:30:73] assign _issue_entry_WIRE_365 = _issue_entry_T_6027; // @[Mux.scala:30:73] assign _issue_entry_WIRE_325_rs1 = _issue_entry_WIRE_365; // @[Mux.scala:30:73] wire [6:0] _issue_entry_WIRE_374; // @[Mux.scala:30:73] assign _issue_entry_WIRE_325_inst_funct = _issue_entry_WIRE_366_funct; // @[Mux.scala:30:73] wire [4:0] _issue_entry_WIRE_373; // @[Mux.scala:30:73] assign _issue_entry_WIRE_325_inst_rs2 = _issue_entry_WIRE_366_rs2; // @[Mux.scala:30:73] wire [4:0] _issue_entry_WIRE_372; // @[Mux.scala:30:73] assign _issue_entry_WIRE_325_inst_rs1 = _issue_entry_WIRE_366_rs1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_371; // @[Mux.scala:30:73] assign _issue_entry_WIRE_325_inst_xd = _issue_entry_WIRE_366_xd; // @[Mux.scala:30:73] wire _issue_entry_WIRE_370; // @[Mux.scala:30:73] assign _issue_entry_WIRE_325_inst_xs1 = _issue_entry_WIRE_366_xs1; // @[Mux.scala:30:73] wire _issue_entry_WIRE_369; // @[Mux.scala:30:73] assign _issue_entry_WIRE_325_inst_xs2 = _issue_entry_WIRE_366_xs2; // @[Mux.scala:30:73] wire [4:0] _issue_entry_WIRE_368; // @[Mux.scala:30:73] assign _issue_entry_WIRE_325_inst_rd = _issue_entry_WIRE_366_rd; // @[Mux.scala:30:73] wire [6:0] _issue_entry_WIRE_367; // @[Mux.scala:30:73] assign _issue_entry_WIRE_325_inst_opcode = _issue_entry_WIRE_366_opcode; // @[Mux.scala:30:73] wire [6:0] _issue_entry_T_6028 = issue_sel_0_2 ? entries_st_0_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_6029 = issue_sel_1_2 ? entries_st_1_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_6030 = issue_sel_2_2 ? entries_st_2_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_6031 = issue_sel_3_2 ? entries_st_3_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_6032 = _issue_entry_T_6028 | _issue_entry_T_6029; // @[Mux.scala:30:73] wire [6:0] _issue_entry_T_6033 = _issue_entry_T_6032 | _issue_entry_T_6030; // @[Mux.scala:30:73] wire [6:0] _issue_entry_T_6034 = _issue_entry_T_6033 | _issue_entry_T_6031; // @[Mux.scala:30:73] assign _issue_entry_WIRE_367 = _issue_entry_T_6034; // @[Mux.scala:30:73] assign _issue_entry_WIRE_366_opcode = _issue_entry_WIRE_367; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_6035 = issue_sel_0_2 ? entries_st_0_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_6036 = issue_sel_1_2 ? entries_st_1_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_6037 = issue_sel_2_2 ? entries_st_2_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_6038 = issue_sel_3_2 ? entries_st_3_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_6039 = _issue_entry_T_6035 | _issue_entry_T_6036; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_6040 = _issue_entry_T_6039 | _issue_entry_T_6037; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_6041 = _issue_entry_T_6040 | _issue_entry_T_6038; // @[Mux.scala:30:73] assign _issue_entry_WIRE_368 = _issue_entry_T_6041; // @[Mux.scala:30:73] assign _issue_entry_WIRE_366_rd = _issue_entry_WIRE_368; // @[Mux.scala:30:73] wire _issue_entry_T_6042 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30] wire _issue_entry_T_6043 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30] wire _issue_entry_T_6044 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30] wire _issue_entry_T_6045 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30] wire _issue_entry_T_6046 = _issue_entry_T_6042 | _issue_entry_T_6043; // @[Mux.scala:30:73] wire _issue_entry_T_6047 = _issue_entry_T_6046 | _issue_entry_T_6044; // @[Mux.scala:30:73] wire _issue_entry_T_6048 = _issue_entry_T_6047 | _issue_entry_T_6045; // @[Mux.scala:30:73] assign _issue_entry_WIRE_369 = _issue_entry_T_6048; // @[Mux.scala:30:73] assign _issue_entry_WIRE_366_xs2 = _issue_entry_WIRE_369; // @[Mux.scala:30:73] wire _issue_entry_T_6049 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30] wire _issue_entry_T_6050 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30] wire _issue_entry_T_6051 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30] wire _issue_entry_T_6052 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30] wire _issue_entry_T_6053 = _issue_entry_T_6049 | _issue_entry_T_6050; // @[Mux.scala:30:73] wire _issue_entry_T_6054 = _issue_entry_T_6053 | _issue_entry_T_6051; // @[Mux.scala:30:73] wire _issue_entry_T_6055 = _issue_entry_T_6054 | _issue_entry_T_6052; // @[Mux.scala:30:73] assign _issue_entry_WIRE_370 = _issue_entry_T_6055; // @[Mux.scala:30:73] assign _issue_entry_WIRE_366_xs1 = _issue_entry_WIRE_370; // @[Mux.scala:30:73] wire _issue_entry_T_6056 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30] wire _issue_entry_T_6057 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30] wire _issue_entry_T_6058 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30] wire _issue_entry_T_6059 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30] wire _issue_entry_T_6060 = _issue_entry_T_6056 | _issue_entry_T_6057; // @[Mux.scala:30:73] wire _issue_entry_T_6061 = _issue_entry_T_6060 | _issue_entry_T_6058; // @[Mux.scala:30:73] wire _issue_entry_T_6062 = _issue_entry_T_6061 | _issue_entry_T_6059; // @[Mux.scala:30:73] assign _issue_entry_WIRE_371 = _issue_entry_T_6062; // @[Mux.scala:30:73] assign _issue_entry_WIRE_366_xd = _issue_entry_WIRE_371; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_6063 = issue_sel_0_2 ? entries_st_0_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_6064 = issue_sel_1_2 ? entries_st_1_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_6065 = issue_sel_2_2 ? entries_st_2_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_6066 = issue_sel_3_2 ? entries_st_3_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_6067 = _issue_entry_T_6063 | _issue_entry_T_6064; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_6068 = _issue_entry_T_6067 | _issue_entry_T_6065; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_6069 = _issue_entry_T_6068 | _issue_entry_T_6066; // @[Mux.scala:30:73] assign _issue_entry_WIRE_372 = _issue_entry_T_6069; // @[Mux.scala:30:73] assign _issue_entry_WIRE_366_rs1 = _issue_entry_WIRE_372; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_6070 = issue_sel_0_2 ? entries_st_0_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_6071 = issue_sel_1_2 ? entries_st_1_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_6072 = issue_sel_2_2 ? entries_st_2_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_6073 = issue_sel_3_2 ? entries_st_3_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30] wire [4:0] _issue_entry_T_6074 = _issue_entry_T_6070 | _issue_entry_T_6071; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_6075 = _issue_entry_T_6074 | _issue_entry_T_6072; // @[Mux.scala:30:73] wire [4:0] _issue_entry_T_6076 = _issue_entry_T_6075 | _issue_entry_T_6073; // @[Mux.scala:30:73] assign _issue_entry_WIRE_373 = _issue_entry_T_6076; // @[Mux.scala:30:73] assign _issue_entry_WIRE_366_rs2 = _issue_entry_WIRE_373; // @[Mux.scala:30:73] wire [6:0] _issue_entry_T_6077 = issue_sel_0_2 ? entries_st_0_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_6078 = issue_sel_1_2 ? entries_st_1_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_6079 = issue_sel_2_2 ? entries_st_2_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_6080 = issue_sel_3_2 ? entries_st_3_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30] wire [6:0] _issue_entry_T_6081 = _issue_entry_T_6077 | _issue_entry_T_6078; // @[Mux.scala:30:73] wire [6:0] _issue_entry_T_6082 = _issue_entry_T_6081 | _issue_entry_T_6079; // @[Mux.scala:30:73] wire [6:0] _issue_entry_T_6083 = _issue_entry_T_6082 | _issue_entry_T_6080; // @[Mux.scala:30:73] assign _issue_entry_WIRE_374 = _issue_entry_T_6083; // @[Mux.scala:30:73] assign _issue_entry_WIRE_366_funct = _issue_entry_WIRE_374; // @[Mux.scala:30:73] wire _issue_entry_T_6084 = issue_sel_0_2 & entries_st_0_bits_complete_on_issue; // @[OneHot.scala:83:30] wire _issue_entry_T_6085 = issue_sel_1_2 & entries_st_1_bits_complete_on_issue; // @[OneHot.scala:83:30] wire _issue_entry_T_6086 = issue_sel_2_2 & entries_st_2_bits_complete_on_issue; // @[OneHot.scala:83:30] wire _issue_entry_T_6087 = issue_sel_3_2 & entries_st_3_bits_complete_on_issue; // @[OneHot.scala:83:30] wire _issue_entry_T_6088 = _issue_entry_T_6084 | _issue_entry_T_6085; // @[Mux.scala:30:73] wire _issue_entry_T_6089 = _issue_entry_T_6088 | _issue_entry_T_6086; // @[Mux.scala:30:73] wire _issue_entry_T_6090 = _issue_entry_T_6089 | _issue_entry_T_6087; // @[Mux.scala:30:73] assign _issue_entry_WIRE_375 = _issue_entry_T_6090; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_complete_on_issue = _issue_entry_WIRE_375; // @[Mux.scala:30:73] wire _issue_entry_T_6091 = issue_sel_0_2 & entries_st_0_bits_issued; // @[OneHot.scala:83:30] wire _issue_entry_T_6092 = issue_sel_1_2 & entries_st_1_bits_issued; // @[OneHot.scala:83:30] wire _issue_entry_T_6093 = issue_sel_2_2 & entries_st_2_bits_issued; // @[OneHot.scala:83:30] wire _issue_entry_T_6094 = issue_sel_3_2 & entries_st_3_bits_issued; // @[OneHot.scala:83:30] wire _issue_entry_T_6095 = _issue_entry_T_6091 | _issue_entry_T_6092; // @[Mux.scala:30:73] wire _issue_entry_T_6096 = _issue_entry_T_6095 | _issue_entry_T_6093; // @[Mux.scala:30:73] wire _issue_entry_T_6097 = _issue_entry_T_6096 | _issue_entry_T_6094; // @[Mux.scala:30:73] assign _issue_entry_WIRE_376 = _issue_entry_T_6097; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_issued = _issue_entry_WIRE_376; // @[Mux.scala:30:73] wire _issue_entry_T_6218 = issue_sel_0_2 & entries_st_0_bits_opa_is_dst; // @[OneHot.scala:83:30] wire _issue_entry_T_6219 = issue_sel_1_2 & entries_st_1_bits_opa_is_dst; // @[OneHot.scala:83:30] wire _issue_entry_T_6220 = issue_sel_2_2 & entries_st_2_bits_opa_is_dst; // @[OneHot.scala:83:30] wire _issue_entry_T_6221 = issue_sel_3_2 & entries_st_3_bits_opa_is_dst; // @[OneHot.scala:83:30] wire _issue_entry_T_6222 = _issue_entry_T_6218 | _issue_entry_T_6219; // @[Mux.scala:30:73] wire _issue_entry_T_6223 = _issue_entry_T_6222 | _issue_entry_T_6220; // @[Mux.scala:30:73] wire _issue_entry_T_6224 = _issue_entry_T_6223 | _issue_entry_T_6221; // @[Mux.scala:30:73] assign _issue_entry_WIRE_401 = _issue_entry_T_6224; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_opa_is_dst = _issue_entry_WIRE_401; // @[Mux.scala:30:73] wire _issue_entry_WIRE_425; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_opa_valid = _issue_entry_WIRE_402_valid; // @[Mux.scala:30:73] wire _issue_entry_WIRE_403_start_is_acc_addr; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_opa_bits_start_is_acc_addr = _issue_entry_WIRE_402_bits_start_is_acc_addr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_403_start_accumulate; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_opa_bits_start_accumulate = _issue_entry_WIRE_402_bits_start_accumulate; // @[Mux.scala:30:73] wire _issue_entry_WIRE_403_start_read_full_acc_row; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_opa_bits_start_read_full_acc_row = _issue_entry_WIRE_402_bits_start_read_full_acc_row; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_403_start_norm_cmd; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_opa_bits_start_norm_cmd = _issue_entry_WIRE_402_bits_start_norm_cmd; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_403_start_garbage; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_opa_bits_start_garbage = _issue_entry_WIRE_402_bits_start_garbage; // @[Mux.scala:30:73] wire _issue_entry_WIRE_403_start_garbage_bit; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_opa_bits_start_garbage_bit = _issue_entry_WIRE_402_bits_start_garbage_bit; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_403_start_data; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_opa_bits_start_data = _issue_entry_WIRE_402_bits_start_data; // @[Mux.scala:30:73] wire _issue_entry_WIRE_403_end_is_acc_addr; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_opa_bits_end_is_acc_addr = _issue_entry_WIRE_402_bits_end_is_acc_addr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_403_end_accumulate; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_opa_bits_end_accumulate = _issue_entry_WIRE_402_bits_end_accumulate; // @[Mux.scala:30:73] wire _issue_entry_WIRE_403_end_read_full_acc_row; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_opa_bits_end_read_full_acc_row = _issue_entry_WIRE_402_bits_end_read_full_acc_row; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_403_end_norm_cmd; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_opa_bits_end_norm_cmd = _issue_entry_WIRE_402_bits_end_norm_cmd; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_403_end_garbage; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_opa_bits_end_garbage = _issue_entry_WIRE_402_bits_end_garbage; // @[Mux.scala:30:73] wire _issue_entry_WIRE_403_end_garbage_bit; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_opa_bits_end_garbage_bit = _issue_entry_WIRE_402_bits_end_garbage_bit; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_403_end_data; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_opa_bits_end_data = _issue_entry_WIRE_402_bits_end_data; // @[Mux.scala:30:73] wire _issue_entry_WIRE_403_wraps_around; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_opa_bits_wraps_around = _issue_entry_WIRE_402_bits_wraps_around; // @[Mux.scala:30:73] wire _issue_entry_WIRE_415_is_acc_addr; // @[Mux.scala:30:73] assign _issue_entry_WIRE_402_bits_start_is_acc_addr = _issue_entry_WIRE_403_start_is_acc_addr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_415_accumulate; // @[Mux.scala:30:73] assign _issue_entry_WIRE_402_bits_start_accumulate = _issue_entry_WIRE_403_start_accumulate; // @[Mux.scala:30:73] wire _issue_entry_WIRE_415_read_full_acc_row; // @[Mux.scala:30:73] assign _issue_entry_WIRE_402_bits_start_read_full_acc_row = _issue_entry_WIRE_403_start_read_full_acc_row; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_415_norm_cmd; // @[Mux.scala:30:73] assign _issue_entry_WIRE_402_bits_start_norm_cmd = _issue_entry_WIRE_403_start_norm_cmd; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_415_garbage; // @[Mux.scala:30:73] assign _issue_entry_WIRE_402_bits_start_garbage = _issue_entry_WIRE_403_start_garbage; // @[Mux.scala:30:73] wire _issue_entry_WIRE_415_garbage_bit; // @[Mux.scala:30:73] assign _issue_entry_WIRE_402_bits_start_garbage_bit = _issue_entry_WIRE_403_start_garbage_bit; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_415_data; // @[Mux.scala:30:73] assign _issue_entry_WIRE_402_bits_start_data = _issue_entry_WIRE_403_start_data; // @[Mux.scala:30:73] wire _issue_entry_WIRE_405_is_acc_addr; // @[Mux.scala:30:73] assign _issue_entry_WIRE_402_bits_end_is_acc_addr = _issue_entry_WIRE_403_end_is_acc_addr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_405_accumulate; // @[Mux.scala:30:73] assign _issue_entry_WIRE_402_bits_end_accumulate = _issue_entry_WIRE_403_end_accumulate; // @[Mux.scala:30:73] wire _issue_entry_WIRE_405_read_full_acc_row; // @[Mux.scala:30:73] assign _issue_entry_WIRE_402_bits_end_read_full_acc_row = _issue_entry_WIRE_403_end_read_full_acc_row; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_405_norm_cmd; // @[Mux.scala:30:73] assign _issue_entry_WIRE_402_bits_end_norm_cmd = _issue_entry_WIRE_403_end_norm_cmd; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_405_garbage; // @[Mux.scala:30:73] assign _issue_entry_WIRE_402_bits_end_garbage = _issue_entry_WIRE_403_end_garbage; // @[Mux.scala:30:73] wire _issue_entry_WIRE_405_garbage_bit; // @[Mux.scala:30:73] assign _issue_entry_WIRE_402_bits_end_garbage_bit = _issue_entry_WIRE_403_end_garbage_bit; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_405_data; // @[Mux.scala:30:73] assign _issue_entry_WIRE_402_bits_end_data = _issue_entry_WIRE_403_end_data; // @[Mux.scala:30:73] wire _issue_entry_WIRE_404; // @[Mux.scala:30:73] assign _issue_entry_WIRE_402_bits_wraps_around = _issue_entry_WIRE_403_wraps_around; // @[Mux.scala:30:73] wire _issue_entry_T_6225 = issue_sel_0_2 & entries_st_0_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30] wire _issue_entry_T_6226 = issue_sel_1_2 & entries_st_1_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30] wire _issue_entry_T_6227 = issue_sel_2_2 & entries_st_2_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30] wire _issue_entry_T_6228 = issue_sel_3_2 & entries_st_3_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30] wire _issue_entry_T_6229 = _issue_entry_T_6225 | _issue_entry_T_6226; // @[Mux.scala:30:73] wire _issue_entry_T_6230 = _issue_entry_T_6229 | _issue_entry_T_6227; // @[Mux.scala:30:73] wire _issue_entry_T_6231 = _issue_entry_T_6230 | _issue_entry_T_6228; // @[Mux.scala:30:73] assign _issue_entry_WIRE_404 = _issue_entry_T_6231; // @[Mux.scala:30:73] assign _issue_entry_WIRE_403_wraps_around = _issue_entry_WIRE_404; // @[Mux.scala:30:73] wire _issue_entry_WIRE_414; // @[Mux.scala:30:73] assign _issue_entry_WIRE_403_end_is_acc_addr = _issue_entry_WIRE_405_is_acc_addr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_413; // @[Mux.scala:30:73] assign _issue_entry_WIRE_403_end_accumulate = _issue_entry_WIRE_405_accumulate; // @[Mux.scala:30:73] wire _issue_entry_WIRE_412; // @[Mux.scala:30:73] assign _issue_entry_WIRE_403_end_read_full_acc_row = _issue_entry_WIRE_405_read_full_acc_row; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_409; // @[Mux.scala:30:73] assign _issue_entry_WIRE_403_end_norm_cmd = _issue_entry_WIRE_405_norm_cmd; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_408; // @[Mux.scala:30:73] assign _issue_entry_WIRE_403_end_garbage = _issue_entry_WIRE_405_garbage; // @[Mux.scala:30:73] wire _issue_entry_WIRE_407; // @[Mux.scala:30:73] assign _issue_entry_WIRE_403_end_garbage_bit = _issue_entry_WIRE_405_garbage_bit; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_406; // @[Mux.scala:30:73] assign _issue_entry_WIRE_403_end_data = _issue_entry_WIRE_405_data; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_6232 = issue_sel_0_2 ? entries_st_0_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_6233 = issue_sel_1_2 ? entries_st_1_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_6234 = issue_sel_2_2 ? entries_st_2_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_6235 = issue_sel_3_2 ? entries_st_3_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_6236 = _issue_entry_T_6232 | _issue_entry_T_6233; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_6237 = _issue_entry_T_6236 | _issue_entry_T_6234; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_6238 = _issue_entry_T_6237 | _issue_entry_T_6235; // @[Mux.scala:30:73] assign _issue_entry_WIRE_406 = _issue_entry_T_6238; // @[Mux.scala:30:73] assign _issue_entry_WIRE_405_data = _issue_entry_WIRE_406; // @[Mux.scala:30:73] wire _issue_entry_T_6239 = issue_sel_0_2 & entries_st_0_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_6240 = issue_sel_1_2 & entries_st_1_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_6241 = issue_sel_2_2 & entries_st_2_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_6242 = issue_sel_3_2 & entries_st_3_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_6243 = _issue_entry_T_6239 | _issue_entry_T_6240; // @[Mux.scala:30:73] wire _issue_entry_T_6244 = _issue_entry_T_6243 | _issue_entry_T_6241; // @[Mux.scala:30:73] wire _issue_entry_T_6245 = _issue_entry_T_6244 | _issue_entry_T_6242; // @[Mux.scala:30:73] assign _issue_entry_WIRE_407 = _issue_entry_T_6245; // @[Mux.scala:30:73] assign _issue_entry_WIRE_405_garbage_bit = _issue_entry_WIRE_407; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_6246 = issue_sel_0_2 ? entries_st_0_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_6247 = issue_sel_1_2 ? entries_st_1_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_6248 = issue_sel_2_2 ? entries_st_2_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_6249 = issue_sel_3_2 ? entries_st_3_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_6250 = _issue_entry_T_6246 | _issue_entry_T_6247; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_6251 = _issue_entry_T_6250 | _issue_entry_T_6248; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_6252 = _issue_entry_T_6251 | _issue_entry_T_6249; // @[Mux.scala:30:73] assign _issue_entry_WIRE_408 = _issue_entry_T_6252; // @[Mux.scala:30:73] assign _issue_entry_WIRE_405_garbage = _issue_entry_WIRE_408; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_6254 = issue_sel_0_2 ? _issue_entry_T_6253 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_6256 = issue_sel_1_2 ? _issue_entry_T_6255 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_6258 = issue_sel_2_2 ? _issue_entry_T_6257 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_6260 = issue_sel_3_2 ? _issue_entry_T_6259 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_6261 = _issue_entry_T_6254 | _issue_entry_T_6256; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_6262 = _issue_entry_T_6261 | _issue_entry_T_6258; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_6263 = _issue_entry_T_6262 | _issue_entry_T_6260; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_410 = _issue_entry_T_6263; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_411; // @[Mux.scala:30:73] assign _issue_entry_WIRE_405_norm_cmd = _issue_entry_WIRE_409; // @[Mux.scala:30:73] assign _issue_entry_WIRE_411 = _issue_entry_WIRE_410; // @[Mux.scala:30:73] assign _issue_entry_WIRE_409 = _issue_entry_WIRE_411; // @[Mux.scala:30:73] wire _issue_entry_T_6264 = issue_sel_0_2 & entries_st_0_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_6265 = issue_sel_1_2 & entries_st_1_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_6266 = issue_sel_2_2 & entries_st_2_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_6267 = issue_sel_3_2 & entries_st_3_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_6268 = _issue_entry_T_6264 | _issue_entry_T_6265; // @[Mux.scala:30:73] wire _issue_entry_T_6269 = _issue_entry_T_6268 | _issue_entry_T_6266; // @[Mux.scala:30:73] wire _issue_entry_T_6270 = _issue_entry_T_6269 | _issue_entry_T_6267; // @[Mux.scala:30:73] assign _issue_entry_WIRE_412 = _issue_entry_T_6270; // @[Mux.scala:30:73] assign _issue_entry_WIRE_405_read_full_acc_row = _issue_entry_WIRE_412; // @[Mux.scala:30:73] wire _issue_entry_T_6271 = issue_sel_0_2 & entries_st_0_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_6272 = issue_sel_1_2 & entries_st_1_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_6273 = issue_sel_2_2 & entries_st_2_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_6274 = issue_sel_3_2 & entries_st_3_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_6275 = _issue_entry_T_6271 | _issue_entry_T_6272; // @[Mux.scala:30:73] wire _issue_entry_T_6276 = _issue_entry_T_6275 | _issue_entry_T_6273; // @[Mux.scala:30:73] wire _issue_entry_T_6277 = _issue_entry_T_6276 | _issue_entry_T_6274; // @[Mux.scala:30:73] assign _issue_entry_WIRE_413 = _issue_entry_T_6277; // @[Mux.scala:30:73] assign _issue_entry_WIRE_405_accumulate = _issue_entry_WIRE_413; // @[Mux.scala:30:73] wire _issue_entry_T_6278 = issue_sel_0_2 & entries_st_0_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_6279 = issue_sel_1_2 & entries_st_1_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_6280 = issue_sel_2_2 & entries_st_2_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_6281 = issue_sel_3_2 & entries_st_3_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_6282 = _issue_entry_T_6278 | _issue_entry_T_6279; // @[Mux.scala:30:73] wire _issue_entry_T_6283 = _issue_entry_T_6282 | _issue_entry_T_6280; // @[Mux.scala:30:73] wire _issue_entry_T_6284 = _issue_entry_T_6283 | _issue_entry_T_6281; // @[Mux.scala:30:73] assign _issue_entry_WIRE_414 = _issue_entry_T_6284; // @[Mux.scala:30:73] assign _issue_entry_WIRE_405_is_acc_addr = _issue_entry_WIRE_414; // @[Mux.scala:30:73] wire _issue_entry_WIRE_424; // @[Mux.scala:30:73] assign _issue_entry_WIRE_403_start_is_acc_addr = _issue_entry_WIRE_415_is_acc_addr; // @[Mux.scala:30:73] wire _issue_entry_WIRE_423; // @[Mux.scala:30:73] assign _issue_entry_WIRE_403_start_accumulate = _issue_entry_WIRE_415_accumulate; // @[Mux.scala:30:73] wire _issue_entry_WIRE_422; // @[Mux.scala:30:73] assign _issue_entry_WIRE_403_start_read_full_acc_row = _issue_entry_WIRE_415_read_full_acc_row; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_419; // @[Mux.scala:30:73] assign _issue_entry_WIRE_403_start_norm_cmd = _issue_entry_WIRE_415_norm_cmd; // @[Mux.scala:30:73] wire [10:0] _issue_entry_WIRE_418; // @[Mux.scala:30:73] assign _issue_entry_WIRE_403_start_garbage = _issue_entry_WIRE_415_garbage; // @[Mux.scala:30:73] wire _issue_entry_WIRE_417; // @[Mux.scala:30:73] assign _issue_entry_WIRE_403_start_garbage_bit = _issue_entry_WIRE_415_garbage_bit; // @[Mux.scala:30:73] wire [13:0] _issue_entry_WIRE_416; // @[Mux.scala:30:73] assign _issue_entry_WIRE_403_start_data = _issue_entry_WIRE_415_data; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_6285 = issue_sel_0_2 ? entries_st_0_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_6286 = issue_sel_1_2 ? entries_st_1_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_6287 = issue_sel_2_2 ? entries_st_2_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_6288 = issue_sel_3_2 ? entries_st_3_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30] wire [13:0] _issue_entry_T_6289 = _issue_entry_T_6285 | _issue_entry_T_6286; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_6290 = _issue_entry_T_6289 | _issue_entry_T_6287; // @[Mux.scala:30:73] wire [13:0] _issue_entry_T_6291 = _issue_entry_T_6290 | _issue_entry_T_6288; // @[Mux.scala:30:73] assign _issue_entry_WIRE_416 = _issue_entry_T_6291; // @[Mux.scala:30:73] assign _issue_entry_WIRE_415_data = _issue_entry_WIRE_416; // @[Mux.scala:30:73] wire _issue_entry_T_6292 = issue_sel_0_2 & entries_st_0_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_6293 = issue_sel_1_2 & entries_st_1_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_6294 = issue_sel_2_2 & entries_st_2_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_6295 = issue_sel_3_2 & entries_st_3_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30] wire _issue_entry_T_6296 = _issue_entry_T_6292 | _issue_entry_T_6293; // @[Mux.scala:30:73] wire _issue_entry_T_6297 = _issue_entry_T_6296 | _issue_entry_T_6294; // @[Mux.scala:30:73] wire _issue_entry_T_6298 = _issue_entry_T_6297 | _issue_entry_T_6295; // @[Mux.scala:30:73] assign _issue_entry_WIRE_417 = _issue_entry_T_6298; // @[Mux.scala:30:73] assign _issue_entry_WIRE_415_garbage_bit = _issue_entry_WIRE_417; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_6299 = issue_sel_0_2 ? entries_st_0_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_6300 = issue_sel_1_2 ? entries_st_1_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_6301 = issue_sel_2_2 ? entries_st_2_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_6302 = issue_sel_3_2 ? entries_st_3_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30] wire [10:0] _issue_entry_T_6303 = _issue_entry_T_6299 | _issue_entry_T_6300; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_6304 = _issue_entry_T_6303 | _issue_entry_T_6301; // @[Mux.scala:30:73] wire [10:0] _issue_entry_T_6305 = _issue_entry_T_6304 | _issue_entry_T_6302; // @[Mux.scala:30:73] assign _issue_entry_WIRE_418 = _issue_entry_T_6305; // @[Mux.scala:30:73] assign _issue_entry_WIRE_415_garbage = _issue_entry_WIRE_418; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_6307 = issue_sel_0_2 ? _issue_entry_T_6306 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_6309 = issue_sel_1_2 ? _issue_entry_T_6308 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_6311 = issue_sel_2_2 ? _issue_entry_T_6310 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_6313 = issue_sel_3_2 ? _issue_entry_T_6312 : 3'h0; // @[OneHot.scala:83:30] wire [2:0] _issue_entry_T_6314 = _issue_entry_T_6307 | _issue_entry_T_6309; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_6315 = _issue_entry_T_6314 | _issue_entry_T_6311; // @[Mux.scala:30:73] wire [2:0] _issue_entry_T_6316 = _issue_entry_T_6315 | _issue_entry_T_6313; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_420 = _issue_entry_T_6316; // @[Mux.scala:30:73] wire [2:0] _issue_entry_WIRE_421; // @[Mux.scala:30:73] assign _issue_entry_WIRE_415_norm_cmd = _issue_entry_WIRE_419; // @[Mux.scala:30:73] assign _issue_entry_WIRE_421 = _issue_entry_WIRE_420; // @[Mux.scala:30:73] assign _issue_entry_WIRE_419 = _issue_entry_WIRE_421; // @[Mux.scala:30:73] wire _issue_entry_T_6317 = issue_sel_0_2 & entries_st_0_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_6318 = issue_sel_1_2 & entries_st_1_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_6319 = issue_sel_2_2 & entries_st_2_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_6320 = issue_sel_3_2 & entries_st_3_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30] wire _issue_entry_T_6321 = _issue_entry_T_6317 | _issue_entry_T_6318; // @[Mux.scala:30:73] wire _issue_entry_T_6322 = _issue_entry_T_6321 | _issue_entry_T_6319; // @[Mux.scala:30:73] wire _issue_entry_T_6323 = _issue_entry_T_6322 | _issue_entry_T_6320; // @[Mux.scala:30:73] assign _issue_entry_WIRE_422 = _issue_entry_T_6323; // @[Mux.scala:30:73] assign _issue_entry_WIRE_415_read_full_acc_row = _issue_entry_WIRE_422; // @[Mux.scala:30:73] wire _issue_entry_T_6324 = issue_sel_0_2 & entries_st_0_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_6325 = issue_sel_1_2 & entries_st_1_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_6326 = issue_sel_2_2 & entries_st_2_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_6327 = issue_sel_3_2 & entries_st_3_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30] wire _issue_entry_T_6328 = _issue_entry_T_6324 | _issue_entry_T_6325; // @[Mux.scala:30:73] wire _issue_entry_T_6329 = _issue_entry_T_6328 | _issue_entry_T_6326; // @[Mux.scala:30:73] wire _issue_entry_T_6330 = _issue_entry_T_6329 | _issue_entry_T_6327; // @[Mux.scala:30:73] assign _issue_entry_WIRE_423 = _issue_entry_T_6330; // @[Mux.scala:30:73] assign _issue_entry_WIRE_415_accumulate = _issue_entry_WIRE_423; // @[Mux.scala:30:73] wire _issue_entry_T_6331 = issue_sel_0_2 & entries_st_0_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_6332 = issue_sel_1_2 & entries_st_1_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_6333 = issue_sel_2_2 & entries_st_2_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_6334 = issue_sel_3_2 & entries_st_3_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30] wire _issue_entry_T_6335 = _issue_entry_T_6331 | _issue_entry_T_6332; // @[Mux.scala:30:73] wire _issue_entry_T_6336 = _issue_entry_T_6335 | _issue_entry_T_6333; // @[Mux.scala:30:73] wire _issue_entry_T_6337 = _issue_entry_T_6336 | _issue_entry_T_6334; // @[Mux.scala:30:73] assign _issue_entry_WIRE_424 = _issue_entry_T_6337; // @[Mux.scala:30:73] assign _issue_entry_WIRE_415_is_acc_addr = _issue_entry_WIRE_424; // @[Mux.scala:30:73] wire _issue_entry_T_6338 = issue_sel_0_2 & entries_st_0_bits_opa_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_6339 = issue_sel_1_2 & entries_st_1_bits_opa_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_6340 = issue_sel_2_2 & entries_st_2_bits_opa_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_6341 = issue_sel_3_2 & entries_st_3_bits_opa_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_6342 = _issue_entry_T_6338 | _issue_entry_T_6339; // @[Mux.scala:30:73] wire _issue_entry_T_6343 = _issue_entry_T_6342 | _issue_entry_T_6340; // @[Mux.scala:30:73] wire _issue_entry_T_6344 = _issue_entry_T_6343 | _issue_entry_T_6341; // @[Mux.scala:30:73] assign _issue_entry_WIRE_425 = _issue_entry_T_6344; // @[Mux.scala:30:73] assign _issue_entry_WIRE_402_valid = _issue_entry_WIRE_425; // @[Mux.scala:30:73] wire _issue_entry_T_6345 = issue_sel_0_2 & entries_st_0_bits_is_config; // @[OneHot.scala:83:30] wire _issue_entry_T_6346 = issue_sel_1_2 & entries_st_1_bits_is_config; // @[OneHot.scala:83:30] wire _issue_entry_T_6347 = issue_sel_2_2 & entries_st_2_bits_is_config; // @[OneHot.scala:83:30] wire _issue_entry_T_6348 = issue_sel_3_2 & entries_st_3_bits_is_config; // @[OneHot.scala:83:30] wire _issue_entry_T_6349 = _issue_entry_T_6345 | _issue_entry_T_6346; // @[Mux.scala:30:73] wire _issue_entry_T_6350 = _issue_entry_T_6349 | _issue_entry_T_6347; // @[Mux.scala:30:73] wire _issue_entry_T_6351 = _issue_entry_T_6350 | _issue_entry_T_6348; // @[Mux.scala:30:73] assign _issue_entry_WIRE_426 = _issue_entry_T_6351; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_is_config = _issue_entry_WIRE_426; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_6352 = issue_sel_0_2 ? entries_st_0_bits_q : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_6353 = issue_sel_1_2 ? entries_st_1_bits_q : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_6354 = issue_sel_2_2 ? entries_st_2_bits_q : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_6355 = issue_sel_3_2 ? entries_st_3_bits_q : 2'h0; // @[OneHot.scala:83:30] wire [1:0] _issue_entry_T_6356 = _issue_entry_T_6352 | _issue_entry_T_6353; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_6357 = _issue_entry_T_6356 | _issue_entry_T_6354; // @[Mux.scala:30:73] wire [1:0] _issue_entry_T_6358 = _issue_entry_T_6357 | _issue_entry_T_6355; // @[Mux.scala:30:73] assign _issue_entry_WIRE_427 = _issue_entry_T_6358; // @[Mux.scala:30:73] assign _issue_entry_WIRE_286_q = _issue_entry_WIRE_427; // @[Mux.scala:30:73] wire _issue_entry_T_6359 = issue_sel_0_2 & entries_st_0_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_6360 = issue_sel_1_2 & entries_st_1_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_6361 = issue_sel_2_2 & entries_st_2_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_6362 = issue_sel_3_2 & entries_st_3_valid; // @[OneHot.scala:83:30] wire _issue_entry_T_6363 = _issue_entry_T_6359 | _issue_entry_T_6360; // @[Mux.scala:30:73] wire _issue_entry_T_6364 = _issue_entry_T_6363 | _issue_entry_T_6361; // @[Mux.scala:30:73] wire _issue_entry_T_6365 = _issue_entry_T_6364 | _issue_entry_T_6362; // @[Mux.scala:30:73] assign _issue_entry_WIRE_428 = _issue_entry_T_6365; // @[Mux.scala:30:73] assign issue_entry_2_valid = _issue_entry_WIRE_428; // @[Mux.scala:30:73] wire _io_issue_st_valid_T = issue_valids_0_2 | issue_valids_1_2; // @[ReservationStation.scala:395:72, :404:38] wire _io_issue_st_valid_T_1 = _io_issue_st_valid_T | issue_valids_2_2; // @[ReservationStation.scala:395:72, :404:38] assign _io_issue_st_valid_T_2 = _io_issue_st_valid_T_1 | issue_valids_3_2; // @[ReservationStation.scala:395:72, :404:38] assign io_issue_st_valid_0 = _io_issue_st_valid_T_2; // @[ReservationStation.scala:26:7, :404:38] wire _T_5014 = io_issue_st_valid_0 & io_issue_st_ready_0; // @[ReservationStation.scala:22:20, :26:7] wire _entries_st_0_valid_T = ~entries_st_0_bits_complete_on_issue; // @[ReservationStation.scala:119:23, :417:22] wire _entries_st_1_valid_T = ~entries_st_1_bits_complete_on_issue; // @[ReservationStation.scala:119:23, :417:22] wire _entries_st_2_valid_T = ~entries_st_2_bits_complete_on_issue; // @[ReservationStation.scala:119:23, :417:22] wire _entries_st_3_valid_T = ~entries_st_3_bits_complete_on_issue; // @[ReservationStation.scala:119:23, :417:22] wire [3:0] _GEN_99 = {{entries_st_3_bits_complete_on_issue}, {entries_st_2_bits_complete_on_issue}, {entries_st_1_bits_complete_on_issue}, {entries_st_0_bits_complete_on_issue}}; // @[ReservationStation.scala:119:23, :440:71] wire [3:0] _GEN_100 = {{entries_st_3_bits_cmd_from_conv_fsm}, {entries_st_2_bits_cmd_from_conv_fsm}, {entries_st_1_bits_cmd_from_conv_fsm}, {entries_st_0_bits_cmd_from_conv_fsm}}; // @[ReservationStation.scala:119:23, :440:71] wire _GEN_101 = _GEN_99[issue_id_2] & _GEN_100[issue_id_2]; // @[OneHot.scala:32:10] wire _conv_ld_issue_completed_T_2; // @[ReservationStation.scala:440:71] assign _conv_ld_issue_completed_T_2 = _GEN_101; // @[ReservationStation.scala:440:71] wire _conv_st_issue_completed_T_2; // @[ReservationStation.scala:441:71] assign _conv_st_issue_completed_T_2 = _GEN_101; // @[ReservationStation.scala:440:71, :441:71] wire _conv_ex_issue_completed_T_2; // @[ReservationStation.scala:442:71] assign _conv_ex_issue_completed_T_2 = _GEN_101; // @[ReservationStation.scala:440:71, :442:71] assign conv_st_issue_completed = _T_5014 & _conv_st_issue_completed_T_2; // @[ReservationStation.scala:22:20, :139:41, :413:20, :441:{24,71}] wire [3:0] _GEN_102 = {{entries_st_3_bits_cmd_from_matmul_fsm}, {entries_st_2_bits_cmd_from_matmul_fsm}, {entries_st_1_bits_cmd_from_matmul_fsm}, {entries_st_0_bits_cmd_from_matmul_fsm}}; // @[ReservationStation.scala:119:23, :444:73] wire _GEN_103 = _GEN_99[issue_id_2] & _GEN_102[issue_id_2]; // @[OneHot.scala:32:10] wire _matmul_ld_issue_completed_T_2; // @[ReservationStation.scala:444:73] assign _matmul_ld_issue_completed_T_2 = _GEN_103; // @[ReservationStation.scala:444:73] wire _matmul_st_issue_completed_T_2; // @[ReservationStation.scala:445:73] assign _matmul_st_issue_completed_T_2 = _GEN_103; // @[ReservationStation.scala:444:73, :445:73] wire _matmul_ex_issue_completed_T_2; // @[ReservationStation.scala:446:73] assign _matmul_ex_issue_completed_T_2 = _GEN_103; // @[ReservationStation.scala:444:73, :446:73] assign matmul_st_issue_completed = _T_5014 & _matmul_st_issue_completed_T_2; // @[ReservationStation.scala:22:20, :147:43, :413:20, :445:{24,73}] wire [1:0] queue_type = io_completed_bits_0[5:4]; // @[ReservationStation.scala:26:7, :453:39] wire [3:0] issue_id_3 = io_completed_bits_0[3:0]; // @[ReservationStation.scala:26:7, :454:37] wire _GEN_104 = io_completed_valid_0 & ~(|queue_type); // @[ReservationStation.scala:26:7, :453:39, :456:{22,31}] wire [2:0] _conv_ld_completed_T = issue_id_3[2:0]; // @[ReservationStation.scala:454:37] wire [2:0] _matmul_ld_completed_T = issue_id_3[2:0]; // @[ReservationStation.scala:454:37] assign conv_ld_completed = _GEN_104 & _GEN_90[_conv_ld_completed_T]; // @[ReservationStation.scala:142:35, :440:71, :451:28, :456:31, :460:25] assign matmul_ld_completed = _GEN_104 & _GEN_92[_matmul_ld_completed_T]; // @[ReservationStation.scala:150:37, :444:73, :451:28, :456:31, :461:27] wire _GEN_105 = _GEN_104 & ~reset; // @[ReservationStation.scala:456:31, :463:13] wire _GEN_106 = _GEN_56[issue_id_3[2:0]]; // @[ReservationStation.scala:357:17, :454:37, :463:13] wire _GEN_107 = io_completed_valid_0 & (|queue_type); // @[ReservationStation.scala:26:7, :453:39, :456:{22,31}] wire _T_4971 = queue_type == 2'h1; // @[ReservationStation.scala:453:39, :464:28] assign conv_ex_completed = io_completed_valid_0 & (|queue_type) & _T_4971 & _GEN_95[issue_id_3]; // @[ReservationStation.scala:26:7, :144:35, :440:71, :451:28, :453:39, :454:37, :456:{22,31}, :464:{28,37}, :466:34, :468:25] assign matmul_ex_completed = io_completed_valid_0 & (|queue_type) & _T_4971 & _GEN_97[issue_id_3]; // @[ReservationStation.scala:26:7, :152:37, :444:73, :451:28, :453:39, :454:37, :456:{22,31}, :464:{28,37}, :466:34, :469:27] wire _GEN_108 = _GEN_107 & _T_4971 & ~reset; // @[ReservationStation.scala:456:31, :464:{28,37}, :471:13] wire _GEN_109 = _GEN_107 & queue_type != 2'h1; // @[ReservationStation.scala:453:39, :456:31, :464:{28,37}] wire _T_4975 = queue_type == 2'h2; // @[ReservationStation.scala:453:39, :472:28] wire [1:0] _conv_st_completed_T = issue_id_3[1:0]; // @[ReservationStation.scala:454:37] wire [1:0] _matmul_st_completed_T = issue_id_3[1:0]; // @[ReservationStation.scala:454:37] wire _GEN_110 = ~(|queue_type) | _T_4971; // @[ReservationStation.scala:413:20, :453:39, :456:{22,31}, :464:{28,37}, :472:37] assign conv_st_completed = io_completed_valid_0 & ~_GEN_110 & _T_4975 & _GEN_100[_conv_st_completed_T]; // @[ReservationStation.scala:26:7, :143:35, :413:20, :440:71, :451:28, :456:31, :464:37, :472:{28,37}, :476:25] assign matmul_st_completed = io_completed_valid_0 & ~_GEN_110 & _T_4975 & _GEN_102[_matmul_st_completed_T]; // @[ReservationStation.scala:26:7, :143:35, :151:37, :413:20, :444:73, :451:28, :456:31, :464:37, :472:{28,37}, :477:27] wire _GEN_111 = _GEN_109 & _T_4975 & ~reset; // @[ReservationStation.scala:464:37, :472:{28,37}, :479:13] wire _GEN_112 = _GEN_84[issue_id_3[1:0]]; // @[ReservationStation.scala:357:17, :454:37, :479:13] wire _utilization_ld_q_unissued_T = ~entries_ld_0_bits_issued; // @[ReservationStation.scala:117:23, :395:75, :495:72] wire _utilization_ld_q_unissued_T_1 = entries_ld_0_valid & _utilization_ld_q_unissued_T; // @[ReservationStation.scala:117:23, :495:{69,72}] wire _utilization_ld_q_unissued_T_2 = entries_ld_0_bits_q == 2'h0; // @[ReservationStation.scala:117:23, :495:99] wire _utilization_ld_q_unissued_T_3 = _utilization_ld_q_unissued_T_1 & _utilization_ld_q_unissued_T_2; // @[ReservationStation.scala:495:{69,87,99}] wire _utilization_ld_q_unissued_T_4 = ~entries_ld_1_bits_issued; // @[ReservationStation.scala:117:23, :395:75, :495:72] wire _utilization_ld_q_unissued_T_5 = entries_ld_1_valid & _utilization_ld_q_unissued_T_4; // @[ReservationStation.scala:117:23, :495:{69,72}] wire _utilization_ld_q_unissued_T_6 = entries_ld_1_bits_q == 2'h0; // @[ReservationStation.scala:117:23, :495:99] wire _utilization_ld_q_unissued_T_7 = _utilization_ld_q_unissued_T_5 & _utilization_ld_q_unissued_T_6; // @[ReservationStation.scala:495:{69,87,99}] wire _utilization_ld_q_unissued_T_8 = ~entries_ld_2_bits_issued; // @[ReservationStation.scala:117:23, :395:75, :495:72] wire _utilization_ld_q_unissued_T_9 = entries_ld_2_valid & _utilization_ld_q_unissued_T_8; // @[ReservationStation.scala:117:23, :495:{69,72}] wire _utilization_ld_q_unissued_T_10 = entries_ld_2_bits_q == 2'h0; // @[ReservationStation.scala:117:23, :495:99] wire _utilization_ld_q_unissued_T_11 = _utilization_ld_q_unissued_T_9 & _utilization_ld_q_unissued_T_10; // @[ReservationStation.scala:495:{69,87,99}] wire _utilization_ld_q_unissued_T_12 = ~entries_ld_3_bits_issued; // @[ReservationStation.scala:117:23, :395:75, :495:72] wire _utilization_ld_q_unissued_T_13 = entries_ld_3_valid & _utilization_ld_q_unissued_T_12; // @[ReservationStation.scala:117:23, :495:{69,72}] wire _utilization_ld_q_unissued_T_14 = entries_ld_3_bits_q == 2'h0; // @[ReservationStation.scala:117:23, :495:99] wire _utilization_ld_q_unissued_T_15 = _utilization_ld_q_unissued_T_13 & _utilization_ld_q_unissued_T_14; // @[ReservationStation.scala:495:{69,87,99}] wire _utilization_ld_q_unissued_T_16 = ~entries_ld_4_bits_issued; // @[ReservationStation.scala:117:23, :395:75, :495:72] wire _utilization_ld_q_unissued_T_17 = entries_ld_4_valid & _utilization_ld_q_unissued_T_16; // @[ReservationStation.scala:117:23, :495:{69,72}] wire _utilization_ld_q_unissued_T_18 = entries_ld_4_bits_q == 2'h0; // @[ReservationStation.scala:117:23, :495:99] wire _utilization_ld_q_unissued_T_19 = _utilization_ld_q_unissued_T_17 & _utilization_ld_q_unissued_T_18; // @[ReservationStation.scala:495:{69,87,99}] wire _utilization_ld_q_unissued_T_20 = ~entries_ld_5_bits_issued; // @[ReservationStation.scala:117:23, :395:75, :495:72] wire _utilization_ld_q_unissued_T_21 = entries_ld_5_valid & _utilization_ld_q_unissued_T_20; // @[ReservationStation.scala:117:23, :495:{69,72}] wire _utilization_ld_q_unissued_T_22 = entries_ld_5_bits_q == 2'h0; // @[ReservationStation.scala:117:23, :495:99] wire _utilization_ld_q_unissued_T_23 = _utilization_ld_q_unissued_T_21 & _utilization_ld_q_unissued_T_22; // @[ReservationStation.scala:495:{69,87,99}] wire _utilization_ld_q_unissued_T_24 = ~entries_ld_6_bits_issued; // @[ReservationStation.scala:117:23, :395:75, :495:72] wire _utilization_ld_q_unissued_T_25 = entries_ld_6_valid & _utilization_ld_q_unissued_T_24; // @[ReservationStation.scala:117:23, :495:{69,72}] wire _utilization_ld_q_unissued_T_26 = entries_ld_6_bits_q == 2'h0; // @[ReservationStation.scala:117:23, :495:99] wire _utilization_ld_q_unissued_T_27 = _utilization_ld_q_unissued_T_25 & _utilization_ld_q_unissued_T_26; // @[ReservationStation.scala:495:{69,87,99}] wire _utilization_ld_q_unissued_T_28 = ~entries_ld_7_bits_issued; // @[ReservationStation.scala:117:23, :395:75, :495:72] wire _utilization_ld_q_unissued_T_29 = entries_ld_7_valid & _utilization_ld_q_unissued_T_28; // @[ReservationStation.scala:117:23, :495:{69,72}] wire _utilization_ld_q_unissued_T_30 = entries_ld_7_bits_q == 2'h0; // @[ReservationStation.scala:117:23, :495:99] wire _utilization_ld_q_unissued_T_31 = _utilization_ld_q_unissued_T_29 & _utilization_ld_q_unissued_T_30; // @[ReservationStation.scala:495:{69,87,99}] wire _utilization_ld_q_unissued_T_32 = ~entries_ex_0_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :495:72] wire _utilization_ld_q_unissued_T_33 = entries_ex_0_valid & _utilization_ld_q_unissued_T_32; // @[ReservationStation.scala:118:23, :495:{69,72}] wire _utilization_ld_q_unissued_T_34 = entries_ex_0_bits_q == 2'h0; // @[ReservationStation.scala:118:23, :495:99] wire _utilization_ld_q_unissued_T_35 = _utilization_ld_q_unissued_T_33 & _utilization_ld_q_unissued_T_34; // @[ReservationStation.scala:495:{69,87,99}] wire _utilization_ld_q_unissued_T_36 = ~entries_ex_1_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :495:72] wire _utilization_ld_q_unissued_T_37 = entries_ex_1_valid & _utilization_ld_q_unissued_T_36; // @[ReservationStation.scala:118:23, :495:{69,72}] wire _utilization_ld_q_unissued_T_38 = entries_ex_1_bits_q == 2'h0; // @[ReservationStation.scala:118:23, :495:99] wire _utilization_ld_q_unissued_T_39 = _utilization_ld_q_unissued_T_37 & _utilization_ld_q_unissued_T_38; // @[ReservationStation.scala:495:{69,87,99}] wire _utilization_ld_q_unissued_T_40 = ~entries_ex_2_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :495:72] wire _utilization_ld_q_unissued_T_41 = entries_ex_2_valid & _utilization_ld_q_unissued_T_40; // @[ReservationStation.scala:118:23, :495:{69,72}] wire _utilization_ld_q_unissued_T_42 = entries_ex_2_bits_q == 2'h0; // @[ReservationStation.scala:118:23, :495:99] wire _utilization_ld_q_unissued_T_43 = _utilization_ld_q_unissued_T_41 & _utilization_ld_q_unissued_T_42; // @[ReservationStation.scala:495:{69,87,99}] wire _utilization_ld_q_unissued_T_44 = ~entries_ex_3_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :495:72] wire _utilization_ld_q_unissued_T_45 = entries_ex_3_valid & _utilization_ld_q_unissued_T_44; // @[ReservationStation.scala:118:23, :495:{69,72}] wire _utilization_ld_q_unissued_T_46 = entries_ex_3_bits_q == 2'h0; // @[ReservationStation.scala:118:23, :495:99] wire _utilization_ld_q_unissued_T_47 = _utilization_ld_q_unissued_T_45 & _utilization_ld_q_unissued_T_46; // @[ReservationStation.scala:495:{69,87,99}] wire _utilization_ld_q_unissued_T_48 = ~entries_ex_4_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :495:72] wire _utilization_ld_q_unissued_T_49 = entries_ex_4_valid & _utilization_ld_q_unissued_T_48; // @[ReservationStation.scala:118:23, :495:{69,72}] wire _utilization_ld_q_unissued_T_50 = entries_ex_4_bits_q == 2'h0; // @[ReservationStation.scala:118:23, :495:99] wire _utilization_ld_q_unissued_T_51 = _utilization_ld_q_unissued_T_49 & _utilization_ld_q_unissued_T_50; // @[ReservationStation.scala:495:{69,87,99}] wire _utilization_ld_q_unissued_T_52 = ~entries_ex_5_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :495:72] wire _utilization_ld_q_unissued_T_53 = entries_ex_5_valid & _utilization_ld_q_unissued_T_52; // @[ReservationStation.scala:118:23, :495:{69,72}] wire _utilization_ld_q_unissued_T_54 = entries_ex_5_bits_q == 2'h0; // @[ReservationStation.scala:118:23, :495:99] wire _utilization_ld_q_unissued_T_55 = _utilization_ld_q_unissued_T_53 & _utilization_ld_q_unissued_T_54; // @[ReservationStation.scala:495:{69,87,99}] wire _utilization_ld_q_unissued_T_56 = ~entries_ex_6_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :495:72] wire _utilization_ld_q_unissued_T_57 = entries_ex_6_valid & _utilization_ld_q_unissued_T_56; // @[ReservationStation.scala:118:23, :495:{69,72}] wire _utilization_ld_q_unissued_T_58 = entries_ex_6_bits_q == 2'h0; // @[ReservationStation.scala:118:23, :495:99] wire _utilization_ld_q_unissued_T_59 = _utilization_ld_q_unissued_T_57 & _utilization_ld_q_unissued_T_58; // @[ReservationStation.scala:495:{69,87,99}] wire _utilization_ld_q_unissued_T_60 = ~entries_ex_7_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :495:72] wire _utilization_ld_q_unissued_T_61 = entries_ex_7_valid & _utilization_ld_q_unissued_T_60; // @[ReservationStation.scala:118:23, :495:{69,72}] wire _utilization_ld_q_unissued_T_62 = entries_ex_7_bits_q == 2'h0; // @[ReservationStation.scala:118:23, :495:99] wire _utilization_ld_q_unissued_T_63 = _utilization_ld_q_unissued_T_61 & _utilization_ld_q_unissued_T_62; // @[ReservationStation.scala:495:{69,87,99}] wire _utilization_ld_q_unissued_T_64 = ~entries_ex_8_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :495:72] wire _utilization_ld_q_unissued_T_65 = entries_ex_8_valid & _utilization_ld_q_unissued_T_64; // @[ReservationStation.scala:118:23, :495:{69,72}] wire _utilization_ld_q_unissued_T_66 = entries_ex_8_bits_q == 2'h0; // @[ReservationStation.scala:118:23, :495:99] wire _utilization_ld_q_unissued_T_67 = _utilization_ld_q_unissued_T_65 & _utilization_ld_q_unissued_T_66; // @[ReservationStation.scala:495:{69,87,99}] wire _utilization_ld_q_unissued_T_68 = ~entries_ex_9_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :495:72] wire _utilization_ld_q_unissued_T_69 = entries_ex_9_valid & _utilization_ld_q_unissued_T_68; // @[ReservationStation.scala:118:23, :495:{69,72}] wire _utilization_ld_q_unissued_T_70 = entries_ex_9_bits_q == 2'h0; // @[ReservationStation.scala:118:23, :495:99] wire _utilization_ld_q_unissued_T_71 = _utilization_ld_q_unissued_T_69 & _utilization_ld_q_unissued_T_70; // @[ReservationStation.scala:495:{69,87,99}] wire _utilization_ld_q_unissued_T_72 = ~entries_ex_10_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :495:72] wire _utilization_ld_q_unissued_T_73 = entries_ex_10_valid & _utilization_ld_q_unissued_T_72; // @[ReservationStation.scala:118:23, :495:{69,72}] wire _utilization_ld_q_unissued_T_74 = entries_ex_10_bits_q == 2'h0; // @[ReservationStation.scala:118:23, :495:99] wire _utilization_ld_q_unissued_T_75 = _utilization_ld_q_unissued_T_73 & _utilization_ld_q_unissued_T_74; // @[ReservationStation.scala:495:{69,87,99}] wire _utilization_ld_q_unissued_T_76 = ~entries_ex_11_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :495:72] wire _utilization_ld_q_unissued_T_77 = entries_ex_11_valid & _utilization_ld_q_unissued_T_76; // @[ReservationStation.scala:118:23, :495:{69,72}] wire _utilization_ld_q_unissued_T_78 = entries_ex_11_bits_q == 2'h0; // @[ReservationStation.scala:118:23, :495:99] wire _utilization_ld_q_unissued_T_79 = _utilization_ld_q_unissued_T_77 & _utilization_ld_q_unissued_T_78; // @[ReservationStation.scala:495:{69,87,99}] wire _utilization_ld_q_unissued_T_80 = ~entries_ex_12_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :495:72] wire _utilization_ld_q_unissued_T_81 = entries_ex_12_valid & _utilization_ld_q_unissued_T_80; // @[ReservationStation.scala:118:23, :495:{69,72}] wire _utilization_ld_q_unissued_T_82 = entries_ex_12_bits_q == 2'h0; // @[ReservationStation.scala:118:23, :495:99] wire _utilization_ld_q_unissued_T_83 = _utilization_ld_q_unissued_T_81 & _utilization_ld_q_unissued_T_82; // @[ReservationStation.scala:495:{69,87,99}] wire _utilization_ld_q_unissued_T_84 = ~entries_ex_13_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :495:72] wire _utilization_ld_q_unissued_T_85 = entries_ex_13_valid & _utilization_ld_q_unissued_T_84; // @[ReservationStation.scala:118:23, :495:{69,72}] wire _utilization_ld_q_unissued_T_86 = entries_ex_13_bits_q == 2'h0; // @[ReservationStation.scala:118:23, :495:99] wire _utilization_ld_q_unissued_T_87 = _utilization_ld_q_unissued_T_85 & _utilization_ld_q_unissued_T_86; // @[ReservationStation.scala:495:{69,87,99}] wire _utilization_ld_q_unissued_T_88 = ~entries_ex_14_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :495:72] wire _utilization_ld_q_unissued_T_89 = entries_ex_14_valid & _utilization_ld_q_unissued_T_88; // @[ReservationStation.scala:118:23, :495:{69,72}] wire _utilization_ld_q_unissued_T_90 = entries_ex_14_bits_q == 2'h0; // @[ReservationStation.scala:118:23, :495:99] wire _utilization_ld_q_unissued_T_91 = _utilization_ld_q_unissued_T_89 & _utilization_ld_q_unissued_T_90; // @[ReservationStation.scala:495:{69,87,99}] wire _utilization_ld_q_unissued_T_92 = ~entries_ex_15_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :495:72] wire _utilization_ld_q_unissued_T_93 = entries_ex_15_valid & _utilization_ld_q_unissued_T_92; // @[ReservationStation.scala:118:23, :495:{69,72}] wire _utilization_ld_q_unissued_T_94 = entries_ex_15_bits_q == 2'h0; // @[ReservationStation.scala:118:23, :495:99] wire _utilization_ld_q_unissued_T_95 = _utilization_ld_q_unissued_T_93 & _utilization_ld_q_unissued_T_94; // @[ReservationStation.scala:495:{69,87,99}] wire _utilization_ld_q_unissued_T_96 = ~entries_st_0_bits_issued; // @[ReservationStation.scala:119:23, :395:75, :495:72] wire _utilization_ld_q_unissued_T_97 = entries_st_0_valid & _utilization_ld_q_unissued_T_96; // @[ReservationStation.scala:119:23, :495:{69,72}] wire _utilization_ld_q_unissued_T_98 = entries_st_0_bits_q == 2'h0; // @[ReservationStation.scala:119:23, :495:99] wire _utilization_ld_q_unissued_T_99 = _utilization_ld_q_unissued_T_97 & _utilization_ld_q_unissued_T_98; // @[ReservationStation.scala:495:{69,87,99}] wire _utilization_ld_q_unissued_T_100 = ~entries_st_1_bits_issued; // @[ReservationStation.scala:119:23, :395:75, :495:72] wire _utilization_ld_q_unissued_T_101 = entries_st_1_valid & _utilization_ld_q_unissued_T_100; // @[ReservationStation.scala:119:23, :495:{69,72}] wire _utilization_ld_q_unissued_T_102 = entries_st_1_bits_q == 2'h0; // @[ReservationStation.scala:119:23, :495:99] wire _utilization_ld_q_unissued_T_103 = _utilization_ld_q_unissued_T_101 & _utilization_ld_q_unissued_T_102; // @[ReservationStation.scala:495:{69,87,99}] wire _utilization_ld_q_unissued_T_104 = ~entries_st_2_bits_issued; // @[ReservationStation.scala:119:23, :395:75, :495:72] wire _utilization_ld_q_unissued_T_105 = entries_st_2_valid & _utilization_ld_q_unissued_T_104; // @[ReservationStation.scala:119:23, :495:{69,72}] wire _utilization_ld_q_unissued_T_106 = entries_st_2_bits_q == 2'h0; // @[ReservationStation.scala:119:23, :495:99] wire _utilization_ld_q_unissued_T_107 = _utilization_ld_q_unissued_T_105 & _utilization_ld_q_unissued_T_106; // @[ReservationStation.scala:495:{69,87,99}] wire _utilization_ld_q_unissued_T_108 = ~entries_st_3_bits_issued; // @[ReservationStation.scala:119:23, :395:75, :495:72] wire _utilization_ld_q_unissued_T_109 = entries_st_3_valid & _utilization_ld_q_unissued_T_108; // @[ReservationStation.scala:119:23, :495:{69,72}] wire _utilization_ld_q_unissued_T_110 = entries_st_3_bits_q == 2'h0; // @[ReservationStation.scala:119:23, :495:99] wire _utilization_ld_q_unissued_T_111 = _utilization_ld_q_unissued_T_109 & _utilization_ld_q_unissued_T_110; // @[ReservationStation.scala:495:{69,87,99}] wire [1:0] _utilization_ld_q_unissued_T_112 = {1'h0, _utilization_ld_q_unissued_T_7} + {1'h0, _utilization_ld_q_unissued_T_11}; // @[ReservationStation.scala:495:{43,87}] wire [1:0] _utilization_ld_q_unissued_T_113 = _utilization_ld_q_unissued_T_112; // @[ReservationStation.scala:495:43] wire [2:0] _utilization_ld_q_unissued_T_114 = {2'h0, _utilization_ld_q_unissued_T_3} + {1'h0, _utilization_ld_q_unissued_T_113}; // @[ReservationStation.scala:495:{43,87}] wire [1:0] _utilization_ld_q_unissued_T_115 = _utilization_ld_q_unissued_T_114[1:0]; // @[ReservationStation.scala:495:43] wire [1:0] _utilization_ld_q_unissued_T_116 = {1'h0, _utilization_ld_q_unissued_T_15} + {1'h0, _utilization_ld_q_unissued_T_19}; // @[ReservationStation.scala:495:{43,87}] wire [1:0] _utilization_ld_q_unissued_T_117 = _utilization_ld_q_unissued_T_116; // @[ReservationStation.scala:495:43] wire [1:0] _utilization_ld_q_unissued_T_118 = {1'h0, _utilization_ld_q_unissued_T_23} + {1'h0, _utilization_ld_q_unissued_T_27}; // @[ReservationStation.scala:495:{43,87}] wire [1:0] _utilization_ld_q_unissued_T_119 = _utilization_ld_q_unissued_T_118; // @[ReservationStation.scala:495:43] wire [2:0] _utilization_ld_q_unissued_T_120 = {1'h0, _utilization_ld_q_unissued_T_117} + {1'h0, _utilization_ld_q_unissued_T_119}; // @[ReservationStation.scala:495:43] wire [2:0] _utilization_ld_q_unissued_T_121 = _utilization_ld_q_unissued_T_120; // @[ReservationStation.scala:495:43] wire [3:0] _utilization_ld_q_unissued_T_122 = {2'h0, _utilization_ld_q_unissued_T_115} + {1'h0, _utilization_ld_q_unissued_T_121}; // @[ReservationStation.scala:495:43] wire [2:0] _utilization_ld_q_unissued_T_123 = _utilization_ld_q_unissued_T_122[2:0]; // @[ReservationStation.scala:495:43] wire [1:0] _utilization_ld_q_unissued_T_124 = {1'h0, _utilization_ld_q_unissued_T_35} + {1'h0, _utilization_ld_q_unissued_T_39}; // @[ReservationStation.scala:495:{43,87}] wire [1:0] _utilization_ld_q_unissued_T_125 = _utilization_ld_q_unissued_T_124; // @[ReservationStation.scala:495:43] wire [2:0] _utilization_ld_q_unissued_T_126 = {2'h0, _utilization_ld_q_unissued_T_31} + {1'h0, _utilization_ld_q_unissued_T_125}; // @[ReservationStation.scala:495:{43,87}] wire [1:0] _utilization_ld_q_unissued_T_127 = _utilization_ld_q_unissued_T_126[1:0]; // @[ReservationStation.scala:495:43] wire [1:0] _utilization_ld_q_unissued_T_128 = {1'h0, _utilization_ld_q_unissued_T_43} + {1'h0, _utilization_ld_q_unissued_T_47}; // @[ReservationStation.scala:495:{43,87}] wire [1:0] _utilization_ld_q_unissued_T_129 = _utilization_ld_q_unissued_T_128; // @[ReservationStation.scala:495:43] wire [1:0] _utilization_ld_q_unissued_T_130 = {1'h0, _utilization_ld_q_unissued_T_51} + {1'h0, _utilization_ld_q_unissued_T_55}; // @[ReservationStation.scala:495:{43,87}] wire [1:0] _utilization_ld_q_unissued_T_131 = _utilization_ld_q_unissued_T_130; // @[ReservationStation.scala:495:43] wire [2:0] _utilization_ld_q_unissued_T_132 = {1'h0, _utilization_ld_q_unissued_T_129} + {1'h0, _utilization_ld_q_unissued_T_131}; // @[ReservationStation.scala:495:43] wire [2:0] _utilization_ld_q_unissued_T_133 = _utilization_ld_q_unissued_T_132; // @[ReservationStation.scala:495:43] wire [3:0] _utilization_ld_q_unissued_T_134 = {2'h0, _utilization_ld_q_unissued_T_127} + {1'h0, _utilization_ld_q_unissued_T_133}; // @[ReservationStation.scala:495:43] wire [2:0] _utilization_ld_q_unissued_T_135 = _utilization_ld_q_unissued_T_134[2:0]; // @[ReservationStation.scala:495:43] wire [3:0] _utilization_ld_q_unissued_T_136 = {1'h0, _utilization_ld_q_unissued_T_123} + {1'h0, _utilization_ld_q_unissued_T_135}; // @[ReservationStation.scala:495:43] wire [3:0] _utilization_ld_q_unissued_T_137 = _utilization_ld_q_unissued_T_136; // @[ReservationStation.scala:495:43] wire [1:0] _utilization_ld_q_unissued_T_138 = {1'h0, _utilization_ld_q_unissued_T_63} + {1'h0, _utilization_ld_q_unissued_T_67}; // @[ReservationStation.scala:495:{43,87}] wire [1:0] _utilization_ld_q_unissued_T_139 = _utilization_ld_q_unissued_T_138; // @[ReservationStation.scala:495:43] wire [2:0] _utilization_ld_q_unissued_T_140 = {2'h0, _utilization_ld_q_unissued_T_59} + {1'h0, _utilization_ld_q_unissued_T_139}; // @[ReservationStation.scala:495:{43,87}] wire [1:0] _utilization_ld_q_unissued_T_141 = _utilization_ld_q_unissued_T_140[1:0]; // @[ReservationStation.scala:495:43] wire [1:0] _utilization_ld_q_unissued_T_142 = {1'h0, _utilization_ld_q_unissued_T_71} + {1'h0, _utilization_ld_q_unissued_T_75}; // @[ReservationStation.scala:495:{43,87}] wire [1:0] _utilization_ld_q_unissued_T_143 = _utilization_ld_q_unissued_T_142; // @[ReservationStation.scala:495:43] wire [1:0] _utilization_ld_q_unissued_T_144 = {1'h0, _utilization_ld_q_unissued_T_79} + {1'h0, _utilization_ld_q_unissued_T_83}; // @[ReservationStation.scala:495:{43,87}] wire [1:0] _utilization_ld_q_unissued_T_145 = _utilization_ld_q_unissued_T_144; // @[ReservationStation.scala:495:43] wire [2:0] _utilization_ld_q_unissued_T_146 = {1'h0, _utilization_ld_q_unissued_T_143} + {1'h0, _utilization_ld_q_unissued_T_145}; // @[ReservationStation.scala:495:43] wire [2:0] _utilization_ld_q_unissued_T_147 = _utilization_ld_q_unissued_T_146; // @[ReservationStation.scala:495:43] wire [3:0] _utilization_ld_q_unissued_T_148 = {2'h0, _utilization_ld_q_unissued_T_141} + {1'h0, _utilization_ld_q_unissued_T_147}; // @[ReservationStation.scala:495:43] wire [2:0] _utilization_ld_q_unissued_T_149 = _utilization_ld_q_unissued_T_148[2:0]; // @[ReservationStation.scala:495:43] wire [1:0] _utilization_ld_q_unissued_T_150 = {1'h0, _utilization_ld_q_unissued_T_91} + {1'h0, _utilization_ld_q_unissued_T_95}; // @[ReservationStation.scala:495:{43,87}] wire [1:0] _utilization_ld_q_unissued_T_151 = _utilization_ld_q_unissued_T_150; // @[ReservationStation.scala:495:43] wire [2:0] _utilization_ld_q_unissued_T_152 = {2'h0, _utilization_ld_q_unissued_T_87} + {1'h0, _utilization_ld_q_unissued_T_151}; // @[ReservationStation.scala:495:{43,87}] wire [1:0] _utilization_ld_q_unissued_T_153 = _utilization_ld_q_unissued_T_152[1:0]; // @[ReservationStation.scala:495:43] wire [1:0] _utilization_ld_q_unissued_T_154 = {1'h0, _utilization_ld_q_unissued_T_99} + {1'h0, _utilization_ld_q_unissued_T_103}; // @[ReservationStation.scala:495:{43,87}] wire [1:0] _utilization_ld_q_unissued_T_155 = _utilization_ld_q_unissued_T_154; // @[ReservationStation.scala:495:43] wire [1:0] _utilization_ld_q_unissued_T_156 = {1'h0, _utilization_ld_q_unissued_T_107} + {1'h0, _utilization_ld_q_unissued_T_111}; // @[ReservationStation.scala:495:{43,87}] wire [1:0] _utilization_ld_q_unissued_T_157 = _utilization_ld_q_unissued_T_156; // @[ReservationStation.scala:495:43] wire [2:0] _utilization_ld_q_unissued_T_158 = {1'h0, _utilization_ld_q_unissued_T_155} + {1'h0, _utilization_ld_q_unissued_T_157}; // @[ReservationStation.scala:495:43] wire [2:0] _utilization_ld_q_unissued_T_159 = _utilization_ld_q_unissued_T_158; // @[ReservationStation.scala:495:43] wire [3:0] _utilization_ld_q_unissued_T_160 = {2'h0, _utilization_ld_q_unissued_T_153} + {1'h0, _utilization_ld_q_unissued_T_159}; // @[ReservationStation.scala:495:43] wire [2:0] _utilization_ld_q_unissued_T_161 = _utilization_ld_q_unissued_T_160[2:0]; // @[ReservationStation.scala:495:43] wire [3:0] _utilization_ld_q_unissued_T_162 = {1'h0, _utilization_ld_q_unissued_T_149} + {1'h0, _utilization_ld_q_unissued_T_161}; // @[ReservationStation.scala:495:43] wire [3:0] _utilization_ld_q_unissued_T_163 = _utilization_ld_q_unissued_T_162; // @[ReservationStation.scala:495:43] wire [4:0] _utilization_ld_q_unissued_T_164 = {1'h0, _utilization_ld_q_unissued_T_137} + {1'h0, _utilization_ld_q_unissued_T_163}; // @[ReservationStation.scala:495:43] wire [4:0] utilization_ld_q_unissued = _utilization_ld_q_unissued_T_164; // @[ReservationStation.scala:495:43] wire _utilization_st_q_unissued_T = ~entries_ld_0_bits_issued; // @[ReservationStation.scala:117:23, :395:75, :496:72] wire _utilization_st_q_unissued_T_1 = entries_ld_0_valid & _utilization_st_q_unissued_T; // @[ReservationStation.scala:117:23, :496:{69,72}] wire _utilization_st_q_unissued_T_2 = entries_ld_0_bits_q == 2'h2; // @[ReservationStation.scala:117:23, :496:99] wire _utilization_st_q_unissued_T_3 = _utilization_st_q_unissued_T_1 & _utilization_st_q_unissued_T_2; // @[ReservationStation.scala:496:{69,87,99}] wire _utilization_st_q_unissued_T_4 = ~entries_ld_1_bits_issued; // @[ReservationStation.scala:117:23, :395:75, :496:72] wire _utilization_st_q_unissued_T_5 = entries_ld_1_valid & _utilization_st_q_unissued_T_4; // @[ReservationStation.scala:117:23, :496:{69,72}] wire _utilization_st_q_unissued_T_6 = entries_ld_1_bits_q == 2'h2; // @[ReservationStation.scala:117:23, :496:99] wire _utilization_st_q_unissued_T_7 = _utilization_st_q_unissued_T_5 & _utilization_st_q_unissued_T_6; // @[ReservationStation.scala:496:{69,87,99}] wire _utilization_st_q_unissued_T_8 = ~entries_ld_2_bits_issued; // @[ReservationStation.scala:117:23, :395:75, :496:72] wire _utilization_st_q_unissued_T_9 = entries_ld_2_valid & _utilization_st_q_unissued_T_8; // @[ReservationStation.scala:117:23, :496:{69,72}] wire _utilization_st_q_unissued_T_10 = entries_ld_2_bits_q == 2'h2; // @[ReservationStation.scala:117:23, :496:99] wire _utilization_st_q_unissued_T_11 = _utilization_st_q_unissued_T_9 & _utilization_st_q_unissued_T_10; // @[ReservationStation.scala:496:{69,87,99}] wire _utilization_st_q_unissued_T_12 = ~entries_ld_3_bits_issued; // @[ReservationStation.scala:117:23, :395:75, :496:72] wire _utilization_st_q_unissued_T_13 = entries_ld_3_valid & _utilization_st_q_unissued_T_12; // @[ReservationStation.scala:117:23, :496:{69,72}] wire _utilization_st_q_unissued_T_14 = entries_ld_3_bits_q == 2'h2; // @[ReservationStation.scala:117:23, :496:99] wire _utilization_st_q_unissued_T_15 = _utilization_st_q_unissued_T_13 & _utilization_st_q_unissued_T_14; // @[ReservationStation.scala:496:{69,87,99}] wire _utilization_st_q_unissued_T_16 = ~entries_ld_4_bits_issued; // @[ReservationStation.scala:117:23, :395:75, :496:72] wire _utilization_st_q_unissued_T_17 = entries_ld_4_valid & _utilization_st_q_unissued_T_16; // @[ReservationStation.scala:117:23, :496:{69,72}] wire _utilization_st_q_unissued_T_18 = entries_ld_4_bits_q == 2'h2; // @[ReservationStation.scala:117:23, :496:99] wire _utilization_st_q_unissued_T_19 = _utilization_st_q_unissued_T_17 & _utilization_st_q_unissued_T_18; // @[ReservationStation.scala:496:{69,87,99}] wire _utilization_st_q_unissued_T_20 = ~entries_ld_5_bits_issued; // @[ReservationStation.scala:117:23, :395:75, :496:72] wire _utilization_st_q_unissued_T_21 = entries_ld_5_valid & _utilization_st_q_unissued_T_20; // @[ReservationStation.scala:117:23, :496:{69,72}] wire _utilization_st_q_unissued_T_22 = entries_ld_5_bits_q == 2'h2; // @[ReservationStation.scala:117:23, :496:99] wire _utilization_st_q_unissued_T_23 = _utilization_st_q_unissued_T_21 & _utilization_st_q_unissued_T_22; // @[ReservationStation.scala:496:{69,87,99}] wire _utilization_st_q_unissued_T_24 = ~entries_ld_6_bits_issued; // @[ReservationStation.scala:117:23, :395:75, :496:72] wire _utilization_st_q_unissued_T_25 = entries_ld_6_valid & _utilization_st_q_unissued_T_24; // @[ReservationStation.scala:117:23, :496:{69,72}] wire _utilization_st_q_unissued_T_26 = entries_ld_6_bits_q == 2'h2; // @[ReservationStation.scala:117:23, :496:99] wire _utilization_st_q_unissued_T_27 = _utilization_st_q_unissued_T_25 & _utilization_st_q_unissued_T_26; // @[ReservationStation.scala:496:{69,87,99}] wire _utilization_st_q_unissued_T_28 = ~entries_ld_7_bits_issued; // @[ReservationStation.scala:117:23, :395:75, :496:72] wire _utilization_st_q_unissued_T_29 = entries_ld_7_valid & _utilization_st_q_unissued_T_28; // @[ReservationStation.scala:117:23, :496:{69,72}] wire _utilization_st_q_unissued_T_30 = entries_ld_7_bits_q == 2'h2; // @[ReservationStation.scala:117:23, :496:99] wire _utilization_st_q_unissued_T_31 = _utilization_st_q_unissued_T_29 & _utilization_st_q_unissued_T_30; // @[ReservationStation.scala:496:{69,87,99}] wire _utilization_st_q_unissued_T_32 = ~entries_ex_0_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :496:72] wire _utilization_st_q_unissued_T_33 = entries_ex_0_valid & _utilization_st_q_unissued_T_32; // @[ReservationStation.scala:118:23, :496:{69,72}] wire _utilization_st_q_unissued_T_34 = entries_ex_0_bits_q == 2'h2; // @[ReservationStation.scala:118:23, :496:99] wire _utilization_st_q_unissued_T_35 = _utilization_st_q_unissued_T_33 & _utilization_st_q_unissued_T_34; // @[ReservationStation.scala:496:{69,87,99}] wire _utilization_st_q_unissued_T_36 = ~entries_ex_1_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :496:72] wire _utilization_st_q_unissued_T_37 = entries_ex_1_valid & _utilization_st_q_unissued_T_36; // @[ReservationStation.scala:118:23, :496:{69,72}] wire _utilization_st_q_unissued_T_38 = entries_ex_1_bits_q == 2'h2; // @[ReservationStation.scala:118:23, :496:99] wire _utilization_st_q_unissued_T_39 = _utilization_st_q_unissued_T_37 & _utilization_st_q_unissued_T_38; // @[ReservationStation.scala:496:{69,87,99}] wire _utilization_st_q_unissued_T_40 = ~entries_ex_2_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :496:72] wire _utilization_st_q_unissued_T_41 = entries_ex_2_valid & _utilization_st_q_unissued_T_40; // @[ReservationStation.scala:118:23, :496:{69,72}] wire _utilization_st_q_unissued_T_42 = entries_ex_2_bits_q == 2'h2; // @[ReservationStation.scala:118:23, :496:99] wire _utilization_st_q_unissued_T_43 = _utilization_st_q_unissued_T_41 & _utilization_st_q_unissued_T_42; // @[ReservationStation.scala:496:{69,87,99}] wire _utilization_st_q_unissued_T_44 = ~entries_ex_3_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :496:72] wire _utilization_st_q_unissued_T_45 = entries_ex_3_valid & _utilization_st_q_unissued_T_44; // @[ReservationStation.scala:118:23, :496:{69,72}] wire _utilization_st_q_unissued_T_46 = entries_ex_3_bits_q == 2'h2; // @[ReservationStation.scala:118:23, :496:99] wire _utilization_st_q_unissued_T_47 = _utilization_st_q_unissued_T_45 & _utilization_st_q_unissued_T_46; // @[ReservationStation.scala:496:{69,87,99}] wire _utilization_st_q_unissued_T_48 = ~entries_ex_4_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :496:72] wire _utilization_st_q_unissued_T_49 = entries_ex_4_valid & _utilization_st_q_unissued_T_48; // @[ReservationStation.scala:118:23, :496:{69,72}] wire _utilization_st_q_unissued_T_50 = entries_ex_4_bits_q == 2'h2; // @[ReservationStation.scala:118:23, :496:99] wire _utilization_st_q_unissued_T_51 = _utilization_st_q_unissued_T_49 & _utilization_st_q_unissued_T_50; // @[ReservationStation.scala:496:{69,87,99}] wire _utilization_st_q_unissued_T_52 = ~entries_ex_5_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :496:72] wire _utilization_st_q_unissued_T_53 = entries_ex_5_valid & _utilization_st_q_unissued_T_52; // @[ReservationStation.scala:118:23, :496:{69,72}] wire _utilization_st_q_unissued_T_54 = entries_ex_5_bits_q == 2'h2; // @[ReservationStation.scala:118:23, :496:99] wire _utilization_st_q_unissued_T_55 = _utilization_st_q_unissued_T_53 & _utilization_st_q_unissued_T_54; // @[ReservationStation.scala:496:{69,87,99}] wire _utilization_st_q_unissued_T_56 = ~entries_ex_6_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :496:72] wire _utilization_st_q_unissued_T_57 = entries_ex_6_valid & _utilization_st_q_unissued_T_56; // @[ReservationStation.scala:118:23, :496:{69,72}] wire _utilization_st_q_unissued_T_58 = entries_ex_6_bits_q == 2'h2; // @[ReservationStation.scala:118:23, :496:99] wire _utilization_st_q_unissued_T_59 = _utilization_st_q_unissued_T_57 & _utilization_st_q_unissued_T_58; // @[ReservationStation.scala:496:{69,87,99}] wire _utilization_st_q_unissued_T_60 = ~entries_ex_7_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :496:72] wire _utilization_st_q_unissued_T_61 = entries_ex_7_valid & _utilization_st_q_unissued_T_60; // @[ReservationStation.scala:118:23, :496:{69,72}] wire _utilization_st_q_unissued_T_62 = entries_ex_7_bits_q == 2'h2; // @[ReservationStation.scala:118:23, :496:99] wire _utilization_st_q_unissued_T_63 = _utilization_st_q_unissued_T_61 & _utilization_st_q_unissued_T_62; // @[ReservationStation.scala:496:{69,87,99}] wire _utilization_st_q_unissued_T_64 = ~entries_ex_8_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :496:72] wire _utilization_st_q_unissued_T_65 = entries_ex_8_valid & _utilization_st_q_unissued_T_64; // @[ReservationStation.scala:118:23, :496:{69,72}] wire _utilization_st_q_unissued_T_66 = entries_ex_8_bits_q == 2'h2; // @[ReservationStation.scala:118:23, :496:99] wire _utilization_st_q_unissued_T_67 = _utilization_st_q_unissued_T_65 & _utilization_st_q_unissued_T_66; // @[ReservationStation.scala:496:{69,87,99}] wire _utilization_st_q_unissued_T_68 = ~entries_ex_9_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :496:72] wire _utilization_st_q_unissued_T_69 = entries_ex_9_valid & _utilization_st_q_unissued_T_68; // @[ReservationStation.scala:118:23, :496:{69,72}] wire _utilization_st_q_unissued_T_70 = entries_ex_9_bits_q == 2'h2; // @[ReservationStation.scala:118:23, :496:99] wire _utilization_st_q_unissued_T_71 = _utilization_st_q_unissued_T_69 & _utilization_st_q_unissued_T_70; // @[ReservationStation.scala:496:{69,87,99}] wire _utilization_st_q_unissued_T_72 = ~entries_ex_10_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :496:72] wire _utilization_st_q_unissued_T_73 = entries_ex_10_valid & _utilization_st_q_unissued_T_72; // @[ReservationStation.scala:118:23, :496:{69,72}] wire _utilization_st_q_unissued_T_74 = entries_ex_10_bits_q == 2'h2; // @[ReservationStation.scala:118:23, :496:99] wire _utilization_st_q_unissued_T_75 = _utilization_st_q_unissued_T_73 & _utilization_st_q_unissued_T_74; // @[ReservationStation.scala:496:{69,87,99}] wire _utilization_st_q_unissued_T_76 = ~entries_ex_11_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :496:72] wire _utilization_st_q_unissued_T_77 = entries_ex_11_valid & _utilization_st_q_unissued_T_76; // @[ReservationStation.scala:118:23, :496:{69,72}] wire _utilization_st_q_unissued_T_78 = entries_ex_11_bits_q == 2'h2; // @[ReservationStation.scala:118:23, :496:99] wire _utilization_st_q_unissued_T_79 = _utilization_st_q_unissued_T_77 & _utilization_st_q_unissued_T_78; // @[ReservationStation.scala:496:{69,87,99}] wire _utilization_st_q_unissued_T_80 = ~entries_ex_12_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :496:72] wire _utilization_st_q_unissued_T_81 = entries_ex_12_valid & _utilization_st_q_unissued_T_80; // @[ReservationStation.scala:118:23, :496:{69,72}] wire _utilization_st_q_unissued_T_82 = entries_ex_12_bits_q == 2'h2; // @[ReservationStation.scala:118:23, :496:99] wire _utilization_st_q_unissued_T_83 = _utilization_st_q_unissued_T_81 & _utilization_st_q_unissued_T_82; // @[ReservationStation.scala:496:{69,87,99}] wire _utilization_st_q_unissued_T_84 = ~entries_ex_13_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :496:72] wire _utilization_st_q_unissued_T_85 = entries_ex_13_valid & _utilization_st_q_unissued_T_84; // @[ReservationStation.scala:118:23, :496:{69,72}] wire _utilization_st_q_unissued_T_86 = entries_ex_13_bits_q == 2'h2; // @[ReservationStation.scala:118:23, :496:99] wire _utilization_st_q_unissued_T_87 = _utilization_st_q_unissued_T_85 & _utilization_st_q_unissued_T_86; // @[ReservationStation.scala:496:{69,87,99}] wire _utilization_st_q_unissued_T_88 = ~entries_ex_14_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :496:72] wire _utilization_st_q_unissued_T_89 = entries_ex_14_valid & _utilization_st_q_unissued_T_88; // @[ReservationStation.scala:118:23, :496:{69,72}] wire _utilization_st_q_unissued_T_90 = entries_ex_14_bits_q == 2'h2; // @[ReservationStation.scala:118:23, :496:99] wire _utilization_st_q_unissued_T_91 = _utilization_st_q_unissued_T_89 & _utilization_st_q_unissued_T_90; // @[ReservationStation.scala:496:{69,87,99}] wire _utilization_st_q_unissued_T_92 = ~entries_ex_15_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :496:72] wire _utilization_st_q_unissued_T_93 = entries_ex_15_valid & _utilization_st_q_unissued_T_92; // @[ReservationStation.scala:118:23, :496:{69,72}] wire _utilization_st_q_unissued_T_94 = entries_ex_15_bits_q == 2'h2; // @[ReservationStation.scala:118:23, :496:99] wire _utilization_st_q_unissued_T_95 = _utilization_st_q_unissued_T_93 & _utilization_st_q_unissued_T_94; // @[ReservationStation.scala:496:{69,87,99}] wire _utilization_st_q_unissued_T_96 = ~entries_st_0_bits_issued; // @[ReservationStation.scala:119:23, :395:75, :496:72] wire _utilization_st_q_unissued_T_97 = entries_st_0_valid & _utilization_st_q_unissued_T_96; // @[ReservationStation.scala:119:23, :496:{69,72}] wire _utilization_st_q_unissued_T_98 = entries_st_0_bits_q == 2'h2; // @[ReservationStation.scala:119:23, :496:99] wire _utilization_st_q_unissued_T_99 = _utilization_st_q_unissued_T_97 & _utilization_st_q_unissued_T_98; // @[ReservationStation.scala:496:{69,87,99}] wire _utilization_st_q_unissued_T_100 = ~entries_st_1_bits_issued; // @[ReservationStation.scala:119:23, :395:75, :496:72] wire _utilization_st_q_unissued_T_101 = entries_st_1_valid & _utilization_st_q_unissued_T_100; // @[ReservationStation.scala:119:23, :496:{69,72}] wire _utilization_st_q_unissued_T_102 = entries_st_1_bits_q == 2'h2; // @[ReservationStation.scala:119:23, :496:99] wire _utilization_st_q_unissued_T_103 = _utilization_st_q_unissued_T_101 & _utilization_st_q_unissued_T_102; // @[ReservationStation.scala:496:{69,87,99}] wire _utilization_st_q_unissued_T_104 = ~entries_st_2_bits_issued; // @[ReservationStation.scala:119:23, :395:75, :496:72] wire _utilization_st_q_unissued_T_105 = entries_st_2_valid & _utilization_st_q_unissued_T_104; // @[ReservationStation.scala:119:23, :496:{69,72}] wire _utilization_st_q_unissued_T_106 = entries_st_2_bits_q == 2'h2; // @[ReservationStation.scala:119:23, :496:99] wire _utilization_st_q_unissued_T_107 = _utilization_st_q_unissued_T_105 & _utilization_st_q_unissued_T_106; // @[ReservationStation.scala:496:{69,87,99}] wire _utilization_st_q_unissued_T_108 = ~entries_st_3_bits_issued; // @[ReservationStation.scala:119:23, :395:75, :496:72] wire _utilization_st_q_unissued_T_109 = entries_st_3_valid & _utilization_st_q_unissued_T_108; // @[ReservationStation.scala:119:23, :496:{69,72}] wire _utilization_st_q_unissued_T_110 = entries_st_3_bits_q == 2'h2; // @[ReservationStation.scala:119:23, :496:99] wire _utilization_st_q_unissued_T_111 = _utilization_st_q_unissued_T_109 & _utilization_st_q_unissued_T_110; // @[ReservationStation.scala:496:{69,87,99}] wire [1:0] _utilization_st_q_unissued_T_112 = {1'h0, _utilization_st_q_unissued_T_7} + {1'h0, _utilization_st_q_unissued_T_11}; // @[ReservationStation.scala:496:{43,87}] wire [1:0] _utilization_st_q_unissued_T_113 = _utilization_st_q_unissued_T_112; // @[ReservationStation.scala:496:43] wire [2:0] _utilization_st_q_unissued_T_114 = {2'h0, _utilization_st_q_unissued_T_3} + {1'h0, _utilization_st_q_unissued_T_113}; // @[ReservationStation.scala:496:{43,87}] wire [1:0] _utilization_st_q_unissued_T_115 = _utilization_st_q_unissued_T_114[1:0]; // @[ReservationStation.scala:496:43] wire [1:0] _utilization_st_q_unissued_T_116 = {1'h0, _utilization_st_q_unissued_T_15} + {1'h0, _utilization_st_q_unissued_T_19}; // @[ReservationStation.scala:496:{43,87}] wire [1:0] _utilization_st_q_unissued_T_117 = _utilization_st_q_unissued_T_116; // @[ReservationStation.scala:496:43] wire [1:0] _utilization_st_q_unissued_T_118 = {1'h0, _utilization_st_q_unissued_T_23} + {1'h0, _utilization_st_q_unissued_T_27}; // @[ReservationStation.scala:496:{43,87}] wire [1:0] _utilization_st_q_unissued_T_119 = _utilization_st_q_unissued_T_118; // @[ReservationStation.scala:496:43] wire [2:0] _utilization_st_q_unissued_T_120 = {1'h0, _utilization_st_q_unissued_T_117} + {1'h0, _utilization_st_q_unissued_T_119}; // @[ReservationStation.scala:496:43] wire [2:0] _utilization_st_q_unissued_T_121 = _utilization_st_q_unissued_T_120; // @[ReservationStation.scala:496:43] wire [3:0] _utilization_st_q_unissued_T_122 = {2'h0, _utilization_st_q_unissued_T_115} + {1'h0, _utilization_st_q_unissued_T_121}; // @[ReservationStation.scala:496:43] wire [2:0] _utilization_st_q_unissued_T_123 = _utilization_st_q_unissued_T_122[2:0]; // @[ReservationStation.scala:496:43] wire [1:0] _utilization_st_q_unissued_T_124 = {1'h0, _utilization_st_q_unissued_T_35} + {1'h0, _utilization_st_q_unissued_T_39}; // @[ReservationStation.scala:496:{43,87}] wire [1:0] _utilization_st_q_unissued_T_125 = _utilization_st_q_unissued_T_124; // @[ReservationStation.scala:496:43] wire [2:0] _utilization_st_q_unissued_T_126 = {2'h0, _utilization_st_q_unissued_T_31} + {1'h0, _utilization_st_q_unissued_T_125}; // @[ReservationStation.scala:496:{43,87}] wire [1:0] _utilization_st_q_unissued_T_127 = _utilization_st_q_unissued_T_126[1:0]; // @[ReservationStation.scala:496:43] wire [1:0] _utilization_st_q_unissued_T_128 = {1'h0, _utilization_st_q_unissued_T_43} + {1'h0, _utilization_st_q_unissued_T_47}; // @[ReservationStation.scala:496:{43,87}] wire [1:0] _utilization_st_q_unissued_T_129 = _utilization_st_q_unissued_T_128; // @[ReservationStation.scala:496:43] wire [1:0] _utilization_st_q_unissued_T_130 = {1'h0, _utilization_st_q_unissued_T_51} + {1'h0, _utilization_st_q_unissued_T_55}; // @[ReservationStation.scala:496:{43,87}] wire [1:0] _utilization_st_q_unissued_T_131 = _utilization_st_q_unissued_T_130; // @[ReservationStation.scala:496:43] wire [2:0] _utilization_st_q_unissued_T_132 = {1'h0, _utilization_st_q_unissued_T_129} + {1'h0, _utilization_st_q_unissued_T_131}; // @[ReservationStation.scala:496:43] wire [2:0] _utilization_st_q_unissued_T_133 = _utilization_st_q_unissued_T_132; // @[ReservationStation.scala:496:43] wire [3:0] _utilization_st_q_unissued_T_134 = {2'h0, _utilization_st_q_unissued_T_127} + {1'h0, _utilization_st_q_unissued_T_133}; // @[ReservationStation.scala:496:43] wire [2:0] _utilization_st_q_unissued_T_135 = _utilization_st_q_unissued_T_134[2:0]; // @[ReservationStation.scala:496:43] wire [3:0] _utilization_st_q_unissued_T_136 = {1'h0, _utilization_st_q_unissued_T_123} + {1'h0, _utilization_st_q_unissued_T_135}; // @[ReservationStation.scala:496:43] wire [3:0] _utilization_st_q_unissued_T_137 = _utilization_st_q_unissued_T_136; // @[ReservationStation.scala:496:43] wire [1:0] _utilization_st_q_unissued_T_138 = {1'h0, _utilization_st_q_unissued_T_63} + {1'h0, _utilization_st_q_unissued_T_67}; // @[ReservationStation.scala:496:{43,87}] wire [1:0] _utilization_st_q_unissued_T_139 = _utilization_st_q_unissued_T_138; // @[ReservationStation.scala:496:43] wire [2:0] _utilization_st_q_unissued_T_140 = {2'h0, _utilization_st_q_unissued_T_59} + {1'h0, _utilization_st_q_unissued_T_139}; // @[ReservationStation.scala:496:{43,87}] wire [1:0] _utilization_st_q_unissued_T_141 = _utilization_st_q_unissued_T_140[1:0]; // @[ReservationStation.scala:496:43] wire [1:0] _utilization_st_q_unissued_T_142 = {1'h0, _utilization_st_q_unissued_T_71} + {1'h0, _utilization_st_q_unissued_T_75}; // @[ReservationStation.scala:496:{43,87}] wire [1:0] _utilization_st_q_unissued_T_143 = _utilization_st_q_unissued_T_142; // @[ReservationStation.scala:496:43] wire [1:0] _utilization_st_q_unissued_T_144 = {1'h0, _utilization_st_q_unissued_T_79} + {1'h0, _utilization_st_q_unissued_T_83}; // @[ReservationStation.scala:496:{43,87}] wire [1:0] _utilization_st_q_unissued_T_145 = _utilization_st_q_unissued_T_144; // @[ReservationStation.scala:496:43] wire [2:0] _utilization_st_q_unissued_T_146 = {1'h0, _utilization_st_q_unissued_T_143} + {1'h0, _utilization_st_q_unissued_T_145}; // @[ReservationStation.scala:496:43] wire [2:0] _utilization_st_q_unissued_T_147 = _utilization_st_q_unissued_T_146; // @[ReservationStation.scala:496:43] wire [3:0] _utilization_st_q_unissued_T_148 = {2'h0, _utilization_st_q_unissued_T_141} + {1'h0, _utilization_st_q_unissued_T_147}; // @[ReservationStation.scala:496:43] wire [2:0] _utilization_st_q_unissued_T_149 = _utilization_st_q_unissued_T_148[2:0]; // @[ReservationStation.scala:496:43] wire [1:0] _utilization_st_q_unissued_T_150 = {1'h0, _utilization_st_q_unissued_T_91} + {1'h0, _utilization_st_q_unissued_T_95}; // @[ReservationStation.scala:496:{43,87}] wire [1:0] _utilization_st_q_unissued_T_151 = _utilization_st_q_unissued_T_150; // @[ReservationStation.scala:496:43] wire [2:0] _utilization_st_q_unissued_T_152 = {2'h0, _utilization_st_q_unissued_T_87} + {1'h0, _utilization_st_q_unissued_T_151}; // @[ReservationStation.scala:496:{43,87}] wire [1:0] _utilization_st_q_unissued_T_153 = _utilization_st_q_unissued_T_152[1:0]; // @[ReservationStation.scala:496:43] wire [1:0] _utilization_st_q_unissued_T_154 = {1'h0, _utilization_st_q_unissued_T_99} + {1'h0, _utilization_st_q_unissued_T_103}; // @[ReservationStation.scala:496:{43,87}] wire [1:0] _utilization_st_q_unissued_T_155 = _utilization_st_q_unissued_T_154; // @[ReservationStation.scala:496:43] wire [1:0] _utilization_st_q_unissued_T_156 = {1'h0, _utilization_st_q_unissued_T_107} + {1'h0, _utilization_st_q_unissued_T_111}; // @[ReservationStation.scala:496:{43,87}] wire [1:0] _utilization_st_q_unissued_T_157 = _utilization_st_q_unissued_T_156; // @[ReservationStation.scala:496:43] wire [2:0] _utilization_st_q_unissued_T_158 = {1'h0, _utilization_st_q_unissued_T_155} + {1'h0, _utilization_st_q_unissued_T_157}; // @[ReservationStation.scala:496:43] wire [2:0] _utilization_st_q_unissued_T_159 = _utilization_st_q_unissued_T_158; // @[ReservationStation.scala:496:43] wire [3:0] _utilization_st_q_unissued_T_160 = {2'h0, _utilization_st_q_unissued_T_153} + {1'h0, _utilization_st_q_unissued_T_159}; // @[ReservationStation.scala:496:43] wire [2:0] _utilization_st_q_unissued_T_161 = _utilization_st_q_unissued_T_160[2:0]; // @[ReservationStation.scala:496:43] wire [3:0] _utilization_st_q_unissued_T_162 = {1'h0, _utilization_st_q_unissued_T_149} + {1'h0, _utilization_st_q_unissued_T_161}; // @[ReservationStation.scala:496:43] wire [3:0] _utilization_st_q_unissued_T_163 = _utilization_st_q_unissued_T_162; // @[ReservationStation.scala:496:43] wire [4:0] _utilization_st_q_unissued_T_164 = {1'h0, _utilization_st_q_unissued_T_137} + {1'h0, _utilization_st_q_unissued_T_163}; // @[ReservationStation.scala:496:43] wire [4:0] utilization_st_q_unissued = _utilization_st_q_unissued_T_164; // @[ReservationStation.scala:496:43] wire _utilization_ex_q_unissued_T = ~entries_ld_0_bits_issued; // @[ReservationStation.scala:117:23, :395:75, :497:72] wire _utilization_ex_q_unissued_T_1 = entries_ld_0_valid & _utilization_ex_q_unissued_T; // @[ReservationStation.scala:117:23, :497:{69,72}] wire _utilization_ex_q_unissued_T_2 = entries_ld_0_bits_q == 2'h1; // @[ReservationStation.scala:117:23, :497:99] wire _utilization_ex_q_unissued_T_3 = _utilization_ex_q_unissued_T_1 & _utilization_ex_q_unissued_T_2; // @[ReservationStation.scala:497:{69,87,99}] wire _utilization_ex_q_unissued_T_4 = ~entries_ld_1_bits_issued; // @[ReservationStation.scala:117:23, :395:75, :497:72] wire _utilization_ex_q_unissued_T_5 = entries_ld_1_valid & _utilization_ex_q_unissued_T_4; // @[ReservationStation.scala:117:23, :497:{69,72}] wire _utilization_ex_q_unissued_T_6 = entries_ld_1_bits_q == 2'h1; // @[ReservationStation.scala:117:23, :497:99] wire _utilization_ex_q_unissued_T_7 = _utilization_ex_q_unissued_T_5 & _utilization_ex_q_unissued_T_6; // @[ReservationStation.scala:497:{69,87,99}] wire _utilization_ex_q_unissued_T_8 = ~entries_ld_2_bits_issued; // @[ReservationStation.scala:117:23, :395:75, :497:72] wire _utilization_ex_q_unissued_T_9 = entries_ld_2_valid & _utilization_ex_q_unissued_T_8; // @[ReservationStation.scala:117:23, :497:{69,72}] wire _utilization_ex_q_unissued_T_10 = entries_ld_2_bits_q == 2'h1; // @[ReservationStation.scala:117:23, :497:99] wire _utilization_ex_q_unissued_T_11 = _utilization_ex_q_unissued_T_9 & _utilization_ex_q_unissued_T_10; // @[ReservationStation.scala:497:{69,87,99}] wire _utilization_ex_q_unissued_T_12 = ~entries_ld_3_bits_issued; // @[ReservationStation.scala:117:23, :395:75, :497:72] wire _utilization_ex_q_unissued_T_13 = entries_ld_3_valid & _utilization_ex_q_unissued_T_12; // @[ReservationStation.scala:117:23, :497:{69,72}] wire _utilization_ex_q_unissued_T_14 = entries_ld_3_bits_q == 2'h1; // @[ReservationStation.scala:117:23, :497:99] wire _utilization_ex_q_unissued_T_15 = _utilization_ex_q_unissued_T_13 & _utilization_ex_q_unissued_T_14; // @[ReservationStation.scala:497:{69,87,99}] wire _utilization_ex_q_unissued_T_16 = ~entries_ld_4_bits_issued; // @[ReservationStation.scala:117:23, :395:75, :497:72] wire _utilization_ex_q_unissued_T_17 = entries_ld_4_valid & _utilization_ex_q_unissued_T_16; // @[ReservationStation.scala:117:23, :497:{69,72}] wire _utilization_ex_q_unissued_T_18 = entries_ld_4_bits_q == 2'h1; // @[ReservationStation.scala:117:23, :497:99] wire _utilization_ex_q_unissued_T_19 = _utilization_ex_q_unissued_T_17 & _utilization_ex_q_unissued_T_18; // @[ReservationStation.scala:497:{69,87,99}] wire _utilization_ex_q_unissued_T_20 = ~entries_ld_5_bits_issued; // @[ReservationStation.scala:117:23, :395:75, :497:72] wire _utilization_ex_q_unissued_T_21 = entries_ld_5_valid & _utilization_ex_q_unissued_T_20; // @[ReservationStation.scala:117:23, :497:{69,72}] wire _utilization_ex_q_unissued_T_22 = entries_ld_5_bits_q == 2'h1; // @[ReservationStation.scala:117:23, :497:99] wire _utilization_ex_q_unissued_T_23 = _utilization_ex_q_unissued_T_21 & _utilization_ex_q_unissued_T_22; // @[ReservationStation.scala:497:{69,87,99}] wire _utilization_ex_q_unissued_T_24 = ~entries_ld_6_bits_issued; // @[ReservationStation.scala:117:23, :395:75, :497:72] wire _utilization_ex_q_unissued_T_25 = entries_ld_6_valid & _utilization_ex_q_unissued_T_24; // @[ReservationStation.scala:117:23, :497:{69,72}] wire _utilization_ex_q_unissued_T_26 = entries_ld_6_bits_q == 2'h1; // @[ReservationStation.scala:117:23, :497:99] wire _utilization_ex_q_unissued_T_27 = _utilization_ex_q_unissued_T_25 & _utilization_ex_q_unissued_T_26; // @[ReservationStation.scala:497:{69,87,99}] wire _utilization_ex_q_unissued_T_28 = ~entries_ld_7_bits_issued; // @[ReservationStation.scala:117:23, :395:75, :497:72] wire _utilization_ex_q_unissued_T_29 = entries_ld_7_valid & _utilization_ex_q_unissued_T_28; // @[ReservationStation.scala:117:23, :497:{69,72}] wire _utilization_ex_q_unissued_T_30 = entries_ld_7_bits_q == 2'h1; // @[ReservationStation.scala:117:23, :497:99] wire _utilization_ex_q_unissued_T_31 = _utilization_ex_q_unissued_T_29 & _utilization_ex_q_unissued_T_30; // @[ReservationStation.scala:497:{69,87,99}] wire _utilization_ex_q_unissued_T_32 = ~entries_ex_0_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :497:72] wire _utilization_ex_q_unissued_T_33 = entries_ex_0_valid & _utilization_ex_q_unissued_T_32; // @[ReservationStation.scala:118:23, :497:{69,72}] wire _utilization_ex_q_unissued_T_34 = entries_ex_0_bits_q == 2'h1; // @[ReservationStation.scala:118:23, :497:99] wire _utilization_ex_q_unissued_T_35 = _utilization_ex_q_unissued_T_33 & _utilization_ex_q_unissued_T_34; // @[ReservationStation.scala:497:{69,87,99}] wire _utilization_ex_q_unissued_T_36 = ~entries_ex_1_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :497:72] wire _utilization_ex_q_unissued_T_37 = entries_ex_1_valid & _utilization_ex_q_unissued_T_36; // @[ReservationStation.scala:118:23, :497:{69,72}] wire _utilization_ex_q_unissued_T_38 = entries_ex_1_bits_q == 2'h1; // @[ReservationStation.scala:118:23, :497:99] wire _utilization_ex_q_unissued_T_39 = _utilization_ex_q_unissued_T_37 & _utilization_ex_q_unissued_T_38; // @[ReservationStation.scala:497:{69,87,99}] wire _utilization_ex_q_unissued_T_40 = ~entries_ex_2_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :497:72] wire _utilization_ex_q_unissued_T_41 = entries_ex_2_valid & _utilization_ex_q_unissued_T_40; // @[ReservationStation.scala:118:23, :497:{69,72}] wire _utilization_ex_q_unissued_T_42 = entries_ex_2_bits_q == 2'h1; // @[ReservationStation.scala:118:23, :497:99] wire _utilization_ex_q_unissued_T_43 = _utilization_ex_q_unissued_T_41 & _utilization_ex_q_unissued_T_42; // @[ReservationStation.scala:497:{69,87,99}] wire _utilization_ex_q_unissued_T_44 = ~entries_ex_3_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :497:72] wire _utilization_ex_q_unissued_T_45 = entries_ex_3_valid & _utilization_ex_q_unissued_T_44; // @[ReservationStation.scala:118:23, :497:{69,72}] wire _utilization_ex_q_unissued_T_46 = entries_ex_3_bits_q == 2'h1; // @[ReservationStation.scala:118:23, :497:99] wire _utilization_ex_q_unissued_T_47 = _utilization_ex_q_unissued_T_45 & _utilization_ex_q_unissued_T_46; // @[ReservationStation.scala:497:{69,87,99}] wire _utilization_ex_q_unissued_T_48 = ~entries_ex_4_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :497:72] wire _utilization_ex_q_unissued_T_49 = entries_ex_4_valid & _utilization_ex_q_unissued_T_48; // @[ReservationStation.scala:118:23, :497:{69,72}] wire _utilization_ex_q_unissued_T_50 = entries_ex_4_bits_q == 2'h1; // @[ReservationStation.scala:118:23, :497:99] wire _utilization_ex_q_unissued_T_51 = _utilization_ex_q_unissued_T_49 & _utilization_ex_q_unissued_T_50; // @[ReservationStation.scala:497:{69,87,99}] wire _utilization_ex_q_unissued_T_52 = ~entries_ex_5_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :497:72] wire _utilization_ex_q_unissued_T_53 = entries_ex_5_valid & _utilization_ex_q_unissued_T_52; // @[ReservationStation.scala:118:23, :497:{69,72}] wire _utilization_ex_q_unissued_T_54 = entries_ex_5_bits_q == 2'h1; // @[ReservationStation.scala:118:23, :497:99] wire _utilization_ex_q_unissued_T_55 = _utilization_ex_q_unissued_T_53 & _utilization_ex_q_unissued_T_54; // @[ReservationStation.scala:497:{69,87,99}] wire _utilization_ex_q_unissued_T_56 = ~entries_ex_6_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :497:72] wire _utilization_ex_q_unissued_T_57 = entries_ex_6_valid & _utilization_ex_q_unissued_T_56; // @[ReservationStation.scala:118:23, :497:{69,72}] wire _utilization_ex_q_unissued_T_58 = entries_ex_6_bits_q == 2'h1; // @[ReservationStation.scala:118:23, :497:99] wire _utilization_ex_q_unissued_T_59 = _utilization_ex_q_unissued_T_57 & _utilization_ex_q_unissued_T_58; // @[ReservationStation.scala:497:{69,87,99}] wire _utilization_ex_q_unissued_T_60 = ~entries_ex_7_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :497:72] wire _utilization_ex_q_unissued_T_61 = entries_ex_7_valid & _utilization_ex_q_unissued_T_60; // @[ReservationStation.scala:118:23, :497:{69,72}] wire _utilization_ex_q_unissued_T_62 = entries_ex_7_bits_q == 2'h1; // @[ReservationStation.scala:118:23, :497:99] wire _utilization_ex_q_unissued_T_63 = _utilization_ex_q_unissued_T_61 & _utilization_ex_q_unissued_T_62; // @[ReservationStation.scala:497:{69,87,99}] wire _utilization_ex_q_unissued_T_64 = ~entries_ex_8_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :497:72] wire _utilization_ex_q_unissued_T_65 = entries_ex_8_valid & _utilization_ex_q_unissued_T_64; // @[ReservationStation.scala:118:23, :497:{69,72}] wire _utilization_ex_q_unissued_T_66 = entries_ex_8_bits_q == 2'h1; // @[ReservationStation.scala:118:23, :497:99] wire _utilization_ex_q_unissued_T_67 = _utilization_ex_q_unissued_T_65 & _utilization_ex_q_unissued_T_66; // @[ReservationStation.scala:497:{69,87,99}] wire _utilization_ex_q_unissued_T_68 = ~entries_ex_9_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :497:72] wire _utilization_ex_q_unissued_T_69 = entries_ex_9_valid & _utilization_ex_q_unissued_T_68; // @[ReservationStation.scala:118:23, :497:{69,72}] wire _utilization_ex_q_unissued_T_70 = entries_ex_9_bits_q == 2'h1; // @[ReservationStation.scala:118:23, :497:99] wire _utilization_ex_q_unissued_T_71 = _utilization_ex_q_unissued_T_69 & _utilization_ex_q_unissued_T_70; // @[ReservationStation.scala:497:{69,87,99}] wire _utilization_ex_q_unissued_T_72 = ~entries_ex_10_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :497:72] wire _utilization_ex_q_unissued_T_73 = entries_ex_10_valid & _utilization_ex_q_unissued_T_72; // @[ReservationStation.scala:118:23, :497:{69,72}] wire _utilization_ex_q_unissued_T_74 = entries_ex_10_bits_q == 2'h1; // @[ReservationStation.scala:118:23, :497:99] wire _utilization_ex_q_unissued_T_75 = _utilization_ex_q_unissued_T_73 & _utilization_ex_q_unissued_T_74; // @[ReservationStation.scala:497:{69,87,99}] wire _utilization_ex_q_unissued_T_76 = ~entries_ex_11_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :497:72] wire _utilization_ex_q_unissued_T_77 = entries_ex_11_valid & _utilization_ex_q_unissued_T_76; // @[ReservationStation.scala:118:23, :497:{69,72}] wire _utilization_ex_q_unissued_T_78 = entries_ex_11_bits_q == 2'h1; // @[ReservationStation.scala:118:23, :497:99] wire _utilization_ex_q_unissued_T_79 = _utilization_ex_q_unissued_T_77 & _utilization_ex_q_unissued_T_78; // @[ReservationStation.scala:497:{69,87,99}] wire _utilization_ex_q_unissued_T_80 = ~entries_ex_12_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :497:72] wire _utilization_ex_q_unissued_T_81 = entries_ex_12_valid & _utilization_ex_q_unissued_T_80; // @[ReservationStation.scala:118:23, :497:{69,72}] wire _utilization_ex_q_unissued_T_82 = entries_ex_12_bits_q == 2'h1; // @[ReservationStation.scala:118:23, :497:99] wire _utilization_ex_q_unissued_T_83 = _utilization_ex_q_unissued_T_81 & _utilization_ex_q_unissued_T_82; // @[ReservationStation.scala:497:{69,87,99}] wire _utilization_ex_q_unissued_T_84 = ~entries_ex_13_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :497:72] wire _utilization_ex_q_unissued_T_85 = entries_ex_13_valid & _utilization_ex_q_unissued_T_84; // @[ReservationStation.scala:118:23, :497:{69,72}] wire _utilization_ex_q_unissued_T_86 = entries_ex_13_bits_q == 2'h1; // @[ReservationStation.scala:118:23, :497:99] wire _utilization_ex_q_unissued_T_87 = _utilization_ex_q_unissued_T_85 & _utilization_ex_q_unissued_T_86; // @[ReservationStation.scala:497:{69,87,99}] wire _utilization_ex_q_unissued_T_88 = ~entries_ex_14_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :497:72] wire _utilization_ex_q_unissued_T_89 = entries_ex_14_valid & _utilization_ex_q_unissued_T_88; // @[ReservationStation.scala:118:23, :497:{69,72}] wire _utilization_ex_q_unissued_T_90 = entries_ex_14_bits_q == 2'h1; // @[ReservationStation.scala:118:23, :497:99] wire _utilization_ex_q_unissued_T_91 = _utilization_ex_q_unissued_T_89 & _utilization_ex_q_unissued_T_90; // @[ReservationStation.scala:497:{69,87,99}] wire _utilization_ex_q_unissued_T_92 = ~entries_ex_15_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :497:72] wire _utilization_ex_q_unissued_T_93 = entries_ex_15_valid & _utilization_ex_q_unissued_T_92; // @[ReservationStation.scala:118:23, :497:{69,72}] wire _utilization_ex_q_unissued_T_94 = entries_ex_15_bits_q == 2'h1; // @[ReservationStation.scala:118:23, :497:99] wire _utilization_ex_q_unissued_T_95 = _utilization_ex_q_unissued_T_93 & _utilization_ex_q_unissued_T_94; // @[ReservationStation.scala:497:{69,87,99}] wire _utilization_ex_q_unissued_T_96 = ~entries_st_0_bits_issued; // @[ReservationStation.scala:119:23, :395:75, :497:72] wire _utilization_ex_q_unissued_T_97 = entries_st_0_valid & _utilization_ex_q_unissued_T_96; // @[ReservationStation.scala:119:23, :497:{69,72}] wire _utilization_ex_q_unissued_T_98 = entries_st_0_bits_q == 2'h1; // @[ReservationStation.scala:119:23, :497:99] wire _utilization_ex_q_unissued_T_99 = _utilization_ex_q_unissued_T_97 & _utilization_ex_q_unissued_T_98; // @[ReservationStation.scala:497:{69,87,99}] wire _utilization_ex_q_unissued_T_100 = ~entries_st_1_bits_issued; // @[ReservationStation.scala:119:23, :395:75, :497:72] wire _utilization_ex_q_unissued_T_101 = entries_st_1_valid & _utilization_ex_q_unissued_T_100; // @[ReservationStation.scala:119:23, :497:{69,72}] wire _utilization_ex_q_unissued_T_102 = entries_st_1_bits_q == 2'h1; // @[ReservationStation.scala:119:23, :497:99] wire _utilization_ex_q_unissued_T_103 = _utilization_ex_q_unissued_T_101 & _utilization_ex_q_unissued_T_102; // @[ReservationStation.scala:497:{69,87,99}] wire _utilization_ex_q_unissued_T_104 = ~entries_st_2_bits_issued; // @[ReservationStation.scala:119:23, :395:75, :497:72] wire _utilization_ex_q_unissued_T_105 = entries_st_2_valid & _utilization_ex_q_unissued_T_104; // @[ReservationStation.scala:119:23, :497:{69,72}] wire _utilization_ex_q_unissued_T_106 = entries_st_2_bits_q == 2'h1; // @[ReservationStation.scala:119:23, :497:99] wire _utilization_ex_q_unissued_T_107 = _utilization_ex_q_unissued_T_105 & _utilization_ex_q_unissued_T_106; // @[ReservationStation.scala:497:{69,87,99}] wire _utilization_ex_q_unissued_T_108 = ~entries_st_3_bits_issued; // @[ReservationStation.scala:119:23, :395:75, :497:72] wire _utilization_ex_q_unissued_T_109 = entries_st_3_valid & _utilization_ex_q_unissued_T_108; // @[ReservationStation.scala:119:23, :497:{69,72}] wire _utilization_ex_q_unissued_T_110 = entries_st_3_bits_q == 2'h1; // @[ReservationStation.scala:119:23, :497:99] wire _utilization_ex_q_unissued_T_111 = _utilization_ex_q_unissued_T_109 & _utilization_ex_q_unissued_T_110; // @[ReservationStation.scala:497:{69,87,99}] wire [1:0] _utilization_ex_q_unissued_T_112 = {1'h0, _utilization_ex_q_unissued_T_7} + {1'h0, _utilization_ex_q_unissued_T_11}; // @[ReservationStation.scala:497:{43,87}] wire [1:0] _utilization_ex_q_unissued_T_113 = _utilization_ex_q_unissued_T_112; // @[ReservationStation.scala:497:43] wire [2:0] _utilization_ex_q_unissued_T_114 = {2'h0, _utilization_ex_q_unissued_T_3} + {1'h0, _utilization_ex_q_unissued_T_113}; // @[ReservationStation.scala:497:{43,87}] wire [1:0] _utilization_ex_q_unissued_T_115 = _utilization_ex_q_unissued_T_114[1:0]; // @[ReservationStation.scala:497:43] wire [1:0] _utilization_ex_q_unissued_T_116 = {1'h0, _utilization_ex_q_unissued_T_15} + {1'h0, _utilization_ex_q_unissued_T_19}; // @[ReservationStation.scala:497:{43,87}] wire [1:0] _utilization_ex_q_unissued_T_117 = _utilization_ex_q_unissued_T_116; // @[ReservationStation.scala:497:43] wire [1:0] _utilization_ex_q_unissued_T_118 = {1'h0, _utilization_ex_q_unissued_T_23} + {1'h0, _utilization_ex_q_unissued_T_27}; // @[ReservationStation.scala:497:{43,87}] wire [1:0] _utilization_ex_q_unissued_T_119 = _utilization_ex_q_unissued_T_118; // @[ReservationStation.scala:497:43] wire [2:0] _utilization_ex_q_unissued_T_120 = {1'h0, _utilization_ex_q_unissued_T_117} + {1'h0, _utilization_ex_q_unissued_T_119}; // @[ReservationStation.scala:497:43] wire [2:0] _utilization_ex_q_unissued_T_121 = _utilization_ex_q_unissued_T_120; // @[ReservationStation.scala:497:43] wire [3:0] _utilization_ex_q_unissued_T_122 = {2'h0, _utilization_ex_q_unissued_T_115} + {1'h0, _utilization_ex_q_unissued_T_121}; // @[ReservationStation.scala:497:43] wire [2:0] _utilization_ex_q_unissued_T_123 = _utilization_ex_q_unissued_T_122[2:0]; // @[ReservationStation.scala:497:43] wire [1:0] _utilization_ex_q_unissued_T_124 = {1'h0, _utilization_ex_q_unissued_T_35} + {1'h0, _utilization_ex_q_unissued_T_39}; // @[ReservationStation.scala:497:{43,87}] wire [1:0] _utilization_ex_q_unissued_T_125 = _utilization_ex_q_unissued_T_124; // @[ReservationStation.scala:497:43] wire [2:0] _utilization_ex_q_unissued_T_126 = {2'h0, _utilization_ex_q_unissued_T_31} + {1'h0, _utilization_ex_q_unissued_T_125}; // @[ReservationStation.scala:497:{43,87}] wire [1:0] _utilization_ex_q_unissued_T_127 = _utilization_ex_q_unissued_T_126[1:0]; // @[ReservationStation.scala:497:43] wire [1:0] _utilization_ex_q_unissued_T_128 = {1'h0, _utilization_ex_q_unissued_T_43} + {1'h0, _utilization_ex_q_unissued_T_47}; // @[ReservationStation.scala:497:{43,87}] wire [1:0] _utilization_ex_q_unissued_T_129 = _utilization_ex_q_unissued_T_128; // @[ReservationStation.scala:497:43] wire [1:0] _utilization_ex_q_unissued_T_130 = {1'h0, _utilization_ex_q_unissued_T_51} + {1'h0, _utilization_ex_q_unissued_T_55}; // @[ReservationStation.scala:497:{43,87}] wire [1:0] _utilization_ex_q_unissued_T_131 = _utilization_ex_q_unissued_T_130; // @[ReservationStation.scala:497:43] wire [2:0] _utilization_ex_q_unissued_T_132 = {1'h0, _utilization_ex_q_unissued_T_129} + {1'h0, _utilization_ex_q_unissued_T_131}; // @[ReservationStation.scala:497:43] wire [2:0] _utilization_ex_q_unissued_T_133 = _utilization_ex_q_unissued_T_132; // @[ReservationStation.scala:497:43] wire [3:0] _utilization_ex_q_unissued_T_134 = {2'h0, _utilization_ex_q_unissued_T_127} + {1'h0, _utilization_ex_q_unissued_T_133}; // @[ReservationStation.scala:497:43] wire [2:0] _utilization_ex_q_unissued_T_135 = _utilization_ex_q_unissued_T_134[2:0]; // @[ReservationStation.scala:497:43] wire [3:0] _utilization_ex_q_unissued_T_136 = {1'h0, _utilization_ex_q_unissued_T_123} + {1'h0, _utilization_ex_q_unissued_T_135}; // @[ReservationStation.scala:497:43] wire [3:0] _utilization_ex_q_unissued_T_137 = _utilization_ex_q_unissued_T_136; // @[ReservationStation.scala:497:43] wire [1:0] _utilization_ex_q_unissued_T_138 = {1'h0, _utilization_ex_q_unissued_T_63} + {1'h0, _utilization_ex_q_unissued_T_67}; // @[ReservationStation.scala:497:{43,87}] wire [1:0] _utilization_ex_q_unissued_T_139 = _utilization_ex_q_unissued_T_138; // @[ReservationStation.scala:497:43] wire [2:0] _utilization_ex_q_unissued_T_140 = {2'h0, _utilization_ex_q_unissued_T_59} + {1'h0, _utilization_ex_q_unissued_T_139}; // @[ReservationStation.scala:497:{43,87}] wire [1:0] _utilization_ex_q_unissued_T_141 = _utilization_ex_q_unissued_T_140[1:0]; // @[ReservationStation.scala:497:43] wire [1:0] _utilization_ex_q_unissued_T_142 = {1'h0, _utilization_ex_q_unissued_T_71} + {1'h0, _utilization_ex_q_unissued_T_75}; // @[ReservationStation.scala:497:{43,87}] wire [1:0] _utilization_ex_q_unissued_T_143 = _utilization_ex_q_unissued_T_142; // @[ReservationStation.scala:497:43] wire [1:0] _utilization_ex_q_unissued_T_144 = {1'h0, _utilization_ex_q_unissued_T_79} + {1'h0, _utilization_ex_q_unissued_T_83}; // @[ReservationStation.scala:497:{43,87}] wire [1:0] _utilization_ex_q_unissued_T_145 = _utilization_ex_q_unissued_T_144; // @[ReservationStation.scala:497:43] wire [2:0] _utilization_ex_q_unissued_T_146 = {1'h0, _utilization_ex_q_unissued_T_143} + {1'h0, _utilization_ex_q_unissued_T_145}; // @[ReservationStation.scala:497:43] wire [2:0] _utilization_ex_q_unissued_T_147 = _utilization_ex_q_unissued_T_146; // @[ReservationStation.scala:497:43] wire [3:0] _utilization_ex_q_unissued_T_148 = {2'h0, _utilization_ex_q_unissued_T_141} + {1'h0, _utilization_ex_q_unissued_T_147}; // @[ReservationStation.scala:497:43] wire [2:0] _utilization_ex_q_unissued_T_149 = _utilization_ex_q_unissued_T_148[2:0]; // @[ReservationStation.scala:497:43] wire [1:0] _utilization_ex_q_unissued_T_150 = {1'h0, _utilization_ex_q_unissued_T_91} + {1'h0, _utilization_ex_q_unissued_T_95}; // @[ReservationStation.scala:497:{43,87}] wire [1:0] _utilization_ex_q_unissued_T_151 = _utilization_ex_q_unissued_T_150; // @[ReservationStation.scala:497:43] wire [2:0] _utilization_ex_q_unissued_T_152 = {2'h0, _utilization_ex_q_unissued_T_87} + {1'h0, _utilization_ex_q_unissued_T_151}; // @[ReservationStation.scala:497:{43,87}] wire [1:0] _utilization_ex_q_unissued_T_153 = _utilization_ex_q_unissued_T_152[1:0]; // @[ReservationStation.scala:497:43] wire [1:0] _utilization_ex_q_unissued_T_154 = {1'h0, _utilization_ex_q_unissued_T_99} + {1'h0, _utilization_ex_q_unissued_T_103}; // @[ReservationStation.scala:497:{43,87}] wire [1:0] _utilization_ex_q_unissued_T_155 = _utilization_ex_q_unissued_T_154; // @[ReservationStation.scala:497:43] wire [1:0] _utilization_ex_q_unissued_T_156 = {1'h0, _utilization_ex_q_unissued_T_107} + {1'h0, _utilization_ex_q_unissued_T_111}; // @[ReservationStation.scala:497:{43,87}] wire [1:0] _utilization_ex_q_unissued_T_157 = _utilization_ex_q_unissued_T_156; // @[ReservationStation.scala:497:43] wire [2:0] _utilization_ex_q_unissued_T_158 = {1'h0, _utilization_ex_q_unissued_T_155} + {1'h0, _utilization_ex_q_unissued_T_157}; // @[ReservationStation.scala:497:43] wire [2:0] _utilization_ex_q_unissued_T_159 = _utilization_ex_q_unissued_T_158; // @[ReservationStation.scala:497:43] wire [3:0] _utilization_ex_q_unissued_T_160 = {2'h0, _utilization_ex_q_unissued_T_153} + {1'h0, _utilization_ex_q_unissued_T_159}; // @[ReservationStation.scala:497:43] wire [2:0] _utilization_ex_q_unissued_T_161 = _utilization_ex_q_unissued_T_160[2:0]; // @[ReservationStation.scala:497:43] wire [3:0] _utilization_ex_q_unissued_T_162 = {1'h0, _utilization_ex_q_unissued_T_149} + {1'h0, _utilization_ex_q_unissued_T_161}; // @[ReservationStation.scala:497:43] wire [3:0] _utilization_ex_q_unissued_T_163 = _utilization_ex_q_unissued_T_162; // @[ReservationStation.scala:497:43] wire [4:0] _utilization_ex_q_unissued_T_164 = {1'h0, _utilization_ex_q_unissued_T_137} + {1'h0, _utilization_ex_q_unissued_T_163}; // @[ReservationStation.scala:497:43] wire [4:0] utilization_ex_q_unissued = _utilization_ex_q_unissued_T_164; // @[ReservationStation.scala:497:43] wire [1:0] _utilization_ld_q_T = {1'h0, entries_ld_0_valid} + _GEN_1; // @[ReservationStation.scala:117:23, :133:29, :498:34] wire [1:0] _utilization_ld_q_T_1 = _utilization_ld_q_T; // @[ReservationStation.scala:498:34] wire [1:0] _utilization_ld_q_T_2 = _GEN_2 + _GEN_3; // @[ReservationStation.scala:133:29, :498:34] wire [1:0] _utilization_ld_q_T_3 = _utilization_ld_q_T_2; // @[ReservationStation.scala:498:34] wire [2:0] _utilization_ld_q_T_4 = {1'h0, _utilization_ld_q_T_1} + {1'h0, _utilization_ld_q_T_3}; // @[ReservationStation.scala:498:34] wire [2:0] _utilization_ld_q_T_5 = _utilization_ld_q_T_4; // @[ReservationStation.scala:498:34] wire [1:0] _utilization_ld_q_T_6 = _GEN_4 + _GEN_5; // @[ReservationStation.scala:133:29, :498:34] wire [1:0] _utilization_ld_q_T_7 = _utilization_ld_q_T_6; // @[ReservationStation.scala:498:34] wire [1:0] _utilization_ld_q_T_8 = _GEN_6 + {1'h0, entries_ld_7_valid}; // @[ReservationStation.scala:117:23, :133:29, :498:34] wire [1:0] _utilization_ld_q_T_9 = _utilization_ld_q_T_8; // @[ReservationStation.scala:498:34] wire [2:0] _utilization_ld_q_T_10 = {1'h0, _utilization_ld_q_T_7} + {1'h0, _utilization_ld_q_T_9}; // @[ReservationStation.scala:498:34] wire [2:0] _utilization_ld_q_T_11 = _utilization_ld_q_T_10; // @[ReservationStation.scala:498:34] wire [3:0] _utilization_ld_q_T_12 = {1'h0, _utilization_ld_q_T_5} + {1'h0, _utilization_ld_q_T_11}; // @[ReservationStation.scala:498:34] wire [3:0] utilization_ld_q = _utilization_ld_q_T_12; // @[ReservationStation.scala:498:34] wire [1:0] _utilization_st_q_T_1 = _utilization_st_q_T; // @[ReservationStation.scala:499:34] wire [1:0] _utilization_st_q_T_3 = _utilization_st_q_T_2; // @[ReservationStation.scala:499:34] wire [2:0] _utilization_st_q_T_4 = {1'h0, _utilization_st_q_T_1} + {1'h0, _utilization_st_q_T_3}; // @[ReservationStation.scala:499:34] wire [2:0] utilization_st_q = _utilization_st_q_T_4; // @[ReservationStation.scala:499:34] wire [1:0] _utilization_ex_q_T_1 = _utilization_ex_q_T; // @[ReservationStation.scala:500:34] wire [1:0] _utilization_ex_q_T_3 = _utilization_ex_q_T_2; // @[ReservationStation.scala:500:34] wire [2:0] _utilization_ex_q_T_4 = {1'h0, _utilization_ex_q_T_1} + {1'h0, _utilization_ex_q_T_3}; // @[ReservationStation.scala:500:34] wire [2:0] _utilization_ex_q_T_5 = _utilization_ex_q_T_4; // @[ReservationStation.scala:500:34] wire [1:0] _utilization_ex_q_T_7 = _utilization_ex_q_T_6; // @[ReservationStation.scala:500:34] wire [1:0] _utilization_ex_q_T_8 = {1'h0, entries_ex_6_valid} + _GEN_10; // @[ReservationStation.scala:118:23, :133:29, :500:34] wire [1:0] _utilization_ex_q_T_9 = _utilization_ex_q_T_8; // @[ReservationStation.scala:500:34] wire [2:0] _utilization_ex_q_T_10 = {1'h0, _utilization_ex_q_T_7} + {1'h0, _utilization_ex_q_T_9}; // @[ReservationStation.scala:500:34] wire [2:0] _utilization_ex_q_T_11 = _utilization_ex_q_T_10; // @[ReservationStation.scala:500:34] wire [3:0] _utilization_ex_q_T_12 = {1'h0, _utilization_ex_q_T_5} + {1'h0, _utilization_ex_q_T_11}; // @[ReservationStation.scala:500:34] wire [3:0] _utilization_ex_q_T_13 = _utilization_ex_q_T_12; // @[ReservationStation.scala:500:34] wire [1:0] _utilization_ex_q_T_14 = _GEN_11 + _GEN_12; // @[ReservationStation.scala:133:29, :500:34] wire [1:0] _utilization_ex_q_T_15 = _utilization_ex_q_T_14; // @[ReservationStation.scala:500:34] wire [1:0] _utilization_ex_q_T_16 = _GEN_13 + _GEN_14; // @[ReservationStation.scala:133:29, :500:34] wire [1:0] _utilization_ex_q_T_17 = _utilization_ex_q_T_16; // @[ReservationStation.scala:500:34] wire [2:0] _utilization_ex_q_T_18 = {1'h0, _utilization_ex_q_T_15} + {1'h0, _utilization_ex_q_T_17}; // @[ReservationStation.scala:500:34] wire [2:0] _utilization_ex_q_T_19 = _utilization_ex_q_T_18; // @[ReservationStation.scala:500:34] wire [1:0] _utilization_ex_q_T_20 = _GEN_15 + {1'h0, entries_ex_13_valid}; // @[ReservationStation.scala:118:23, :133:29, :500:34] wire [1:0] _utilization_ex_q_T_21 = _utilization_ex_q_T_20; // @[ReservationStation.scala:500:34] wire [1:0] _utilization_ex_q_T_23 = _utilization_ex_q_T_22; // @[ReservationStation.scala:500:34] wire [2:0] _utilization_ex_q_T_24 = {1'h0, _utilization_ex_q_T_21} + {1'h0, _utilization_ex_q_T_23}; // @[ReservationStation.scala:500:34] wire [2:0] _utilization_ex_q_T_25 = _utilization_ex_q_T_24; // @[ReservationStation.scala:500:34] wire [3:0] _utilization_ex_q_T_26 = {1'h0, _utilization_ex_q_T_19} + {1'h0, _utilization_ex_q_T_25}; // @[ReservationStation.scala:500:34] wire [3:0] _utilization_ex_q_T_27 = _utilization_ex_q_T_26; // @[ReservationStation.scala:500:34] wire [4:0] _utilization_ex_q_T_28 = {1'h0, _utilization_ex_q_T_13} + {1'h0, _utilization_ex_q_T_27}; // @[ReservationStation.scala:500:34] wire [4:0] utilization_ex_q = _utilization_ex_q_T_28; // @[ReservationStation.scala:500:34] wire [1:0] packed_deps_lo_lo = {entries_ld_0_bits_deps_ld_1, entries_ld_0_bits_deps_ld_0}; // @[ReservationStation.scala:117:23, :506:12] wire [1:0] packed_deps_lo_hi = {entries_ld_0_bits_deps_ld_3, entries_ld_0_bits_deps_ld_2}; // @[ReservationStation.scala:117:23, :506:12] wire [3:0] packed_deps_lo = {packed_deps_lo_hi, packed_deps_lo_lo}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_hi_lo = {entries_ld_0_bits_deps_ld_5, entries_ld_0_bits_deps_ld_4}; // @[ReservationStation.scala:117:23, :506:12] wire [1:0] packed_deps_hi_hi = {entries_ld_0_bits_deps_ld_7, entries_ld_0_bits_deps_ld_6}; // @[ReservationStation.scala:117:23, :506:12] wire [3:0] packed_deps_hi = {packed_deps_hi_hi, packed_deps_hi_lo}; // @[ReservationStation.scala:506:12] wire [7:0] _packed_deps_T = {packed_deps_hi, packed_deps_lo}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_lo_lo_lo = {entries_ld_0_bits_deps_ex_1, entries_ld_0_bits_deps_ex_0}; // @[ReservationStation.scala:117:23, :506:41] wire [1:0] packed_deps_lo_lo_hi = {entries_ld_0_bits_deps_ex_3, entries_ld_0_bits_deps_ex_2}; // @[ReservationStation.scala:117:23, :506:41] wire [3:0] packed_deps_lo_lo_1 = {packed_deps_lo_lo_hi, packed_deps_lo_lo_lo}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_hi_lo = {entries_ld_0_bits_deps_ex_5, entries_ld_0_bits_deps_ex_4}; // @[ReservationStation.scala:117:23, :506:41] wire [1:0] packed_deps_lo_hi_hi = {entries_ld_0_bits_deps_ex_7, entries_ld_0_bits_deps_ex_6}; // @[ReservationStation.scala:117:23, :506:41] wire [3:0] packed_deps_lo_hi_1 = {packed_deps_lo_hi_hi, packed_deps_lo_hi_lo}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_lo_1 = {packed_deps_lo_hi_1, packed_deps_lo_lo_1}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_lo_lo = {entries_ld_0_bits_deps_ex_9, entries_ld_0_bits_deps_ex_8}; // @[ReservationStation.scala:117:23, :506:41] wire [1:0] packed_deps_hi_lo_hi = {entries_ld_0_bits_deps_ex_11, entries_ld_0_bits_deps_ex_10}; // @[ReservationStation.scala:117:23, :506:41] wire [3:0] packed_deps_hi_lo_1 = {packed_deps_hi_lo_hi, packed_deps_hi_lo_lo}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_hi_lo = {entries_ld_0_bits_deps_ex_13, entries_ld_0_bits_deps_ex_12}; // @[ReservationStation.scala:117:23, :506:41] wire [1:0] packed_deps_hi_hi_hi = {entries_ld_0_bits_deps_ex_15, entries_ld_0_bits_deps_ex_14}; // @[ReservationStation.scala:117:23, :506:41] wire [3:0] packed_deps_hi_hi_1 = {packed_deps_hi_hi_hi, packed_deps_hi_hi_lo}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_hi_1 = {packed_deps_hi_hi_1, packed_deps_hi_lo_1}; // @[ReservationStation.scala:506:41] wire [15:0] _packed_deps_T_1 = {packed_deps_hi_1, packed_deps_lo_1}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_2 = {entries_ld_0_bits_deps_st_1, entries_ld_0_bits_deps_st_0}; // @[ReservationStation.scala:117:23, :506:70] wire [1:0] packed_deps_hi_2 = {entries_ld_0_bits_deps_st_3, entries_ld_0_bits_deps_st_2}; // @[ReservationStation.scala:117:23, :506:70] wire [3:0] _packed_deps_T_2 = {packed_deps_hi_2, packed_deps_lo_2}; // @[ReservationStation.scala:506:70] wire [23:0] packed_deps_hi_3 = {_packed_deps_T, _packed_deps_T_1}; // @[ReservationStation.scala:506:{8,12,41}] wire [27:0] _packed_deps_T_3 = {packed_deps_hi_3, _packed_deps_T_2}; // @[ReservationStation.scala:506:{8,70}] wire [27:0] packed_deps_0 = _packed_deps_T_3; // @[ReservationStation.scala:505:28, :506:8] wire [1:0] packed_deps_lo_lo_2 = {entries_ld_1_bits_deps_ld_1, entries_ld_1_bits_deps_ld_0}; // @[ReservationStation.scala:117:23, :506:12] wire [1:0] packed_deps_lo_hi_2 = {entries_ld_1_bits_deps_ld_3, entries_ld_1_bits_deps_ld_2}; // @[ReservationStation.scala:117:23, :506:12] wire [3:0] packed_deps_lo_3 = {packed_deps_lo_hi_2, packed_deps_lo_lo_2}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_hi_lo_2 = {entries_ld_1_bits_deps_ld_5, entries_ld_1_bits_deps_ld_4}; // @[ReservationStation.scala:117:23, :506:12] wire [1:0] packed_deps_hi_hi_2 = {entries_ld_1_bits_deps_ld_7, entries_ld_1_bits_deps_ld_6}; // @[ReservationStation.scala:117:23, :506:12] wire [3:0] packed_deps_hi_4 = {packed_deps_hi_hi_2, packed_deps_hi_lo_2}; // @[ReservationStation.scala:506:12] wire [7:0] _packed_deps_T_4 = {packed_deps_hi_4, packed_deps_lo_3}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_lo_lo_lo_1 = {entries_ld_1_bits_deps_ex_1, entries_ld_1_bits_deps_ex_0}; // @[ReservationStation.scala:117:23, :506:41] wire [1:0] packed_deps_lo_lo_hi_1 = {entries_ld_1_bits_deps_ex_3, entries_ld_1_bits_deps_ex_2}; // @[ReservationStation.scala:117:23, :506:41] wire [3:0] packed_deps_lo_lo_3 = {packed_deps_lo_lo_hi_1, packed_deps_lo_lo_lo_1}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_hi_lo_1 = {entries_ld_1_bits_deps_ex_5, entries_ld_1_bits_deps_ex_4}; // @[ReservationStation.scala:117:23, :506:41] wire [1:0] packed_deps_lo_hi_hi_1 = {entries_ld_1_bits_deps_ex_7, entries_ld_1_bits_deps_ex_6}; // @[ReservationStation.scala:117:23, :506:41] wire [3:0] packed_deps_lo_hi_3 = {packed_deps_lo_hi_hi_1, packed_deps_lo_hi_lo_1}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_lo_4 = {packed_deps_lo_hi_3, packed_deps_lo_lo_3}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_lo_lo_1 = {entries_ld_1_bits_deps_ex_9, entries_ld_1_bits_deps_ex_8}; // @[ReservationStation.scala:117:23, :506:41] wire [1:0] packed_deps_hi_lo_hi_1 = {entries_ld_1_bits_deps_ex_11, entries_ld_1_bits_deps_ex_10}; // @[ReservationStation.scala:117:23, :506:41] wire [3:0] packed_deps_hi_lo_3 = {packed_deps_hi_lo_hi_1, packed_deps_hi_lo_lo_1}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_hi_lo_1 = {entries_ld_1_bits_deps_ex_13, entries_ld_1_bits_deps_ex_12}; // @[ReservationStation.scala:117:23, :506:41] wire [1:0] packed_deps_hi_hi_hi_1 = {entries_ld_1_bits_deps_ex_15, entries_ld_1_bits_deps_ex_14}; // @[ReservationStation.scala:117:23, :506:41] wire [3:0] packed_deps_hi_hi_3 = {packed_deps_hi_hi_hi_1, packed_deps_hi_hi_lo_1}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_hi_5 = {packed_deps_hi_hi_3, packed_deps_hi_lo_3}; // @[ReservationStation.scala:506:41] wire [15:0] _packed_deps_T_5 = {packed_deps_hi_5, packed_deps_lo_4}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_5 = {entries_ld_1_bits_deps_st_1, entries_ld_1_bits_deps_st_0}; // @[ReservationStation.scala:117:23, :506:70] wire [1:0] packed_deps_hi_6 = {entries_ld_1_bits_deps_st_3, entries_ld_1_bits_deps_st_2}; // @[ReservationStation.scala:117:23, :506:70] wire [3:0] _packed_deps_T_6 = {packed_deps_hi_6, packed_deps_lo_5}; // @[ReservationStation.scala:506:70] wire [23:0] packed_deps_hi_7 = {_packed_deps_T_4, _packed_deps_T_5}; // @[ReservationStation.scala:506:{8,12,41}] wire [27:0] _packed_deps_T_7 = {packed_deps_hi_7, _packed_deps_T_6}; // @[ReservationStation.scala:506:{8,70}] wire [27:0] packed_deps_1 = _packed_deps_T_7; // @[ReservationStation.scala:505:28, :506:8] wire [1:0] packed_deps_lo_lo_4 = {entries_ld_2_bits_deps_ld_1, entries_ld_2_bits_deps_ld_0}; // @[ReservationStation.scala:117:23, :506:12] wire [1:0] packed_deps_lo_hi_4 = {entries_ld_2_bits_deps_ld_3, entries_ld_2_bits_deps_ld_2}; // @[ReservationStation.scala:117:23, :506:12] wire [3:0] packed_deps_lo_6 = {packed_deps_lo_hi_4, packed_deps_lo_lo_4}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_hi_lo_4 = {entries_ld_2_bits_deps_ld_5, entries_ld_2_bits_deps_ld_4}; // @[ReservationStation.scala:117:23, :506:12] wire [1:0] packed_deps_hi_hi_4 = {entries_ld_2_bits_deps_ld_7, entries_ld_2_bits_deps_ld_6}; // @[ReservationStation.scala:117:23, :506:12] wire [3:0] packed_deps_hi_8 = {packed_deps_hi_hi_4, packed_deps_hi_lo_4}; // @[ReservationStation.scala:506:12] wire [7:0] _packed_deps_T_8 = {packed_deps_hi_8, packed_deps_lo_6}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_lo_lo_lo_2 = {entries_ld_2_bits_deps_ex_1, entries_ld_2_bits_deps_ex_0}; // @[ReservationStation.scala:117:23, :506:41] wire [1:0] packed_deps_lo_lo_hi_2 = {entries_ld_2_bits_deps_ex_3, entries_ld_2_bits_deps_ex_2}; // @[ReservationStation.scala:117:23, :506:41] wire [3:0] packed_deps_lo_lo_5 = {packed_deps_lo_lo_hi_2, packed_deps_lo_lo_lo_2}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_hi_lo_2 = {entries_ld_2_bits_deps_ex_5, entries_ld_2_bits_deps_ex_4}; // @[ReservationStation.scala:117:23, :506:41] wire [1:0] packed_deps_lo_hi_hi_2 = {entries_ld_2_bits_deps_ex_7, entries_ld_2_bits_deps_ex_6}; // @[ReservationStation.scala:117:23, :506:41] wire [3:0] packed_deps_lo_hi_5 = {packed_deps_lo_hi_hi_2, packed_deps_lo_hi_lo_2}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_lo_7 = {packed_deps_lo_hi_5, packed_deps_lo_lo_5}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_lo_lo_2 = {entries_ld_2_bits_deps_ex_9, entries_ld_2_bits_deps_ex_8}; // @[ReservationStation.scala:117:23, :506:41] wire [1:0] packed_deps_hi_lo_hi_2 = {entries_ld_2_bits_deps_ex_11, entries_ld_2_bits_deps_ex_10}; // @[ReservationStation.scala:117:23, :506:41] wire [3:0] packed_deps_hi_lo_5 = {packed_deps_hi_lo_hi_2, packed_deps_hi_lo_lo_2}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_hi_lo_2 = {entries_ld_2_bits_deps_ex_13, entries_ld_2_bits_deps_ex_12}; // @[ReservationStation.scala:117:23, :506:41] wire [1:0] packed_deps_hi_hi_hi_2 = {entries_ld_2_bits_deps_ex_15, entries_ld_2_bits_deps_ex_14}; // @[ReservationStation.scala:117:23, :506:41] wire [3:0] packed_deps_hi_hi_5 = {packed_deps_hi_hi_hi_2, packed_deps_hi_hi_lo_2}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_hi_9 = {packed_deps_hi_hi_5, packed_deps_hi_lo_5}; // @[ReservationStation.scala:506:41] wire [15:0] _packed_deps_T_9 = {packed_deps_hi_9, packed_deps_lo_7}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_8 = {entries_ld_2_bits_deps_st_1, entries_ld_2_bits_deps_st_0}; // @[ReservationStation.scala:117:23, :506:70] wire [1:0] packed_deps_hi_10 = {entries_ld_2_bits_deps_st_3, entries_ld_2_bits_deps_st_2}; // @[ReservationStation.scala:117:23, :506:70] wire [3:0] _packed_deps_T_10 = {packed_deps_hi_10, packed_deps_lo_8}; // @[ReservationStation.scala:506:70] wire [23:0] packed_deps_hi_11 = {_packed_deps_T_8, _packed_deps_T_9}; // @[ReservationStation.scala:506:{8,12,41}] wire [27:0] _packed_deps_T_11 = {packed_deps_hi_11, _packed_deps_T_10}; // @[ReservationStation.scala:506:{8,70}] wire [27:0] packed_deps_2 = _packed_deps_T_11; // @[ReservationStation.scala:505:28, :506:8] wire [1:0] packed_deps_lo_lo_6 = {entries_ld_3_bits_deps_ld_1, entries_ld_3_bits_deps_ld_0}; // @[ReservationStation.scala:117:23, :506:12] wire [1:0] packed_deps_lo_hi_6 = {entries_ld_3_bits_deps_ld_3, entries_ld_3_bits_deps_ld_2}; // @[ReservationStation.scala:117:23, :506:12] wire [3:0] packed_deps_lo_9 = {packed_deps_lo_hi_6, packed_deps_lo_lo_6}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_hi_lo_6 = {entries_ld_3_bits_deps_ld_5, entries_ld_3_bits_deps_ld_4}; // @[ReservationStation.scala:117:23, :506:12] wire [1:0] packed_deps_hi_hi_6 = {entries_ld_3_bits_deps_ld_7, entries_ld_3_bits_deps_ld_6}; // @[ReservationStation.scala:117:23, :506:12] wire [3:0] packed_deps_hi_12 = {packed_deps_hi_hi_6, packed_deps_hi_lo_6}; // @[ReservationStation.scala:506:12] wire [7:0] _packed_deps_T_12 = {packed_deps_hi_12, packed_deps_lo_9}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_lo_lo_lo_3 = {entries_ld_3_bits_deps_ex_1, entries_ld_3_bits_deps_ex_0}; // @[ReservationStation.scala:117:23, :506:41] wire [1:0] packed_deps_lo_lo_hi_3 = {entries_ld_3_bits_deps_ex_3, entries_ld_3_bits_deps_ex_2}; // @[ReservationStation.scala:117:23, :506:41] wire [3:0] packed_deps_lo_lo_7 = {packed_deps_lo_lo_hi_3, packed_deps_lo_lo_lo_3}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_hi_lo_3 = {entries_ld_3_bits_deps_ex_5, entries_ld_3_bits_deps_ex_4}; // @[ReservationStation.scala:117:23, :506:41] wire [1:0] packed_deps_lo_hi_hi_3 = {entries_ld_3_bits_deps_ex_7, entries_ld_3_bits_deps_ex_6}; // @[ReservationStation.scala:117:23, :506:41] wire [3:0] packed_deps_lo_hi_7 = {packed_deps_lo_hi_hi_3, packed_deps_lo_hi_lo_3}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_lo_10 = {packed_deps_lo_hi_7, packed_deps_lo_lo_7}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_lo_lo_3 = {entries_ld_3_bits_deps_ex_9, entries_ld_3_bits_deps_ex_8}; // @[ReservationStation.scala:117:23, :506:41] wire [1:0] packed_deps_hi_lo_hi_3 = {entries_ld_3_bits_deps_ex_11, entries_ld_3_bits_deps_ex_10}; // @[ReservationStation.scala:117:23, :506:41] wire [3:0] packed_deps_hi_lo_7 = {packed_deps_hi_lo_hi_3, packed_deps_hi_lo_lo_3}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_hi_lo_3 = {entries_ld_3_bits_deps_ex_13, entries_ld_3_bits_deps_ex_12}; // @[ReservationStation.scala:117:23, :506:41] wire [1:0] packed_deps_hi_hi_hi_3 = {entries_ld_3_bits_deps_ex_15, entries_ld_3_bits_deps_ex_14}; // @[ReservationStation.scala:117:23, :506:41] wire [3:0] packed_deps_hi_hi_7 = {packed_deps_hi_hi_hi_3, packed_deps_hi_hi_lo_3}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_hi_13 = {packed_deps_hi_hi_7, packed_deps_hi_lo_7}; // @[ReservationStation.scala:506:41] wire [15:0] _packed_deps_T_13 = {packed_deps_hi_13, packed_deps_lo_10}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_11 = {entries_ld_3_bits_deps_st_1, entries_ld_3_bits_deps_st_0}; // @[ReservationStation.scala:117:23, :506:70] wire [1:0] packed_deps_hi_14 = {entries_ld_3_bits_deps_st_3, entries_ld_3_bits_deps_st_2}; // @[ReservationStation.scala:117:23, :506:70] wire [3:0] _packed_deps_T_14 = {packed_deps_hi_14, packed_deps_lo_11}; // @[ReservationStation.scala:506:70] wire [23:0] packed_deps_hi_15 = {_packed_deps_T_12, _packed_deps_T_13}; // @[ReservationStation.scala:506:{8,12,41}] wire [27:0] _packed_deps_T_15 = {packed_deps_hi_15, _packed_deps_T_14}; // @[ReservationStation.scala:506:{8,70}] wire [27:0] packed_deps_3 = _packed_deps_T_15; // @[ReservationStation.scala:505:28, :506:8] wire [1:0] packed_deps_lo_lo_8 = {entries_ld_4_bits_deps_ld_1, entries_ld_4_bits_deps_ld_0}; // @[ReservationStation.scala:117:23, :506:12] wire [1:0] packed_deps_lo_hi_8 = {entries_ld_4_bits_deps_ld_3, entries_ld_4_bits_deps_ld_2}; // @[ReservationStation.scala:117:23, :506:12] wire [3:0] packed_deps_lo_12 = {packed_deps_lo_hi_8, packed_deps_lo_lo_8}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_hi_lo_8 = {entries_ld_4_bits_deps_ld_5, entries_ld_4_bits_deps_ld_4}; // @[ReservationStation.scala:117:23, :506:12] wire [1:0] packed_deps_hi_hi_8 = {entries_ld_4_bits_deps_ld_7, entries_ld_4_bits_deps_ld_6}; // @[ReservationStation.scala:117:23, :506:12] wire [3:0] packed_deps_hi_16 = {packed_deps_hi_hi_8, packed_deps_hi_lo_8}; // @[ReservationStation.scala:506:12] wire [7:0] _packed_deps_T_16 = {packed_deps_hi_16, packed_deps_lo_12}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_lo_lo_lo_4 = {entries_ld_4_bits_deps_ex_1, entries_ld_4_bits_deps_ex_0}; // @[ReservationStation.scala:117:23, :506:41] wire [1:0] packed_deps_lo_lo_hi_4 = {entries_ld_4_bits_deps_ex_3, entries_ld_4_bits_deps_ex_2}; // @[ReservationStation.scala:117:23, :506:41] wire [3:0] packed_deps_lo_lo_9 = {packed_deps_lo_lo_hi_4, packed_deps_lo_lo_lo_4}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_hi_lo_4 = {entries_ld_4_bits_deps_ex_5, entries_ld_4_bits_deps_ex_4}; // @[ReservationStation.scala:117:23, :506:41] wire [1:0] packed_deps_lo_hi_hi_4 = {entries_ld_4_bits_deps_ex_7, entries_ld_4_bits_deps_ex_6}; // @[ReservationStation.scala:117:23, :506:41] wire [3:0] packed_deps_lo_hi_9 = {packed_deps_lo_hi_hi_4, packed_deps_lo_hi_lo_4}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_lo_13 = {packed_deps_lo_hi_9, packed_deps_lo_lo_9}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_lo_lo_4 = {entries_ld_4_bits_deps_ex_9, entries_ld_4_bits_deps_ex_8}; // @[ReservationStation.scala:117:23, :506:41] wire [1:0] packed_deps_hi_lo_hi_4 = {entries_ld_4_bits_deps_ex_11, entries_ld_4_bits_deps_ex_10}; // @[ReservationStation.scala:117:23, :506:41] wire [3:0] packed_deps_hi_lo_9 = {packed_deps_hi_lo_hi_4, packed_deps_hi_lo_lo_4}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_hi_lo_4 = {entries_ld_4_bits_deps_ex_13, entries_ld_4_bits_deps_ex_12}; // @[ReservationStation.scala:117:23, :506:41] wire [1:0] packed_deps_hi_hi_hi_4 = {entries_ld_4_bits_deps_ex_15, entries_ld_4_bits_deps_ex_14}; // @[ReservationStation.scala:117:23, :506:41] wire [3:0] packed_deps_hi_hi_9 = {packed_deps_hi_hi_hi_4, packed_deps_hi_hi_lo_4}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_hi_17 = {packed_deps_hi_hi_9, packed_deps_hi_lo_9}; // @[ReservationStation.scala:506:41] wire [15:0] _packed_deps_T_17 = {packed_deps_hi_17, packed_deps_lo_13}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_14 = {entries_ld_4_bits_deps_st_1, entries_ld_4_bits_deps_st_0}; // @[ReservationStation.scala:117:23, :506:70] wire [1:0] packed_deps_hi_18 = {entries_ld_4_bits_deps_st_3, entries_ld_4_bits_deps_st_2}; // @[ReservationStation.scala:117:23, :506:70] wire [3:0] _packed_deps_T_18 = {packed_deps_hi_18, packed_deps_lo_14}; // @[ReservationStation.scala:506:70] wire [23:0] packed_deps_hi_19 = {_packed_deps_T_16, _packed_deps_T_17}; // @[ReservationStation.scala:506:{8,12,41}] wire [27:0] _packed_deps_T_19 = {packed_deps_hi_19, _packed_deps_T_18}; // @[ReservationStation.scala:506:{8,70}] wire [27:0] packed_deps_4 = _packed_deps_T_19; // @[ReservationStation.scala:505:28, :506:8] wire [1:0] packed_deps_lo_lo_10 = {entries_ld_5_bits_deps_ld_1, entries_ld_5_bits_deps_ld_0}; // @[ReservationStation.scala:117:23, :506:12] wire [1:0] packed_deps_lo_hi_10 = {entries_ld_5_bits_deps_ld_3, entries_ld_5_bits_deps_ld_2}; // @[ReservationStation.scala:117:23, :506:12] wire [3:0] packed_deps_lo_15 = {packed_deps_lo_hi_10, packed_deps_lo_lo_10}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_hi_lo_10 = {entries_ld_5_bits_deps_ld_5, entries_ld_5_bits_deps_ld_4}; // @[ReservationStation.scala:117:23, :506:12] wire [1:0] packed_deps_hi_hi_10 = {entries_ld_5_bits_deps_ld_7, entries_ld_5_bits_deps_ld_6}; // @[ReservationStation.scala:117:23, :506:12] wire [3:0] packed_deps_hi_20 = {packed_deps_hi_hi_10, packed_deps_hi_lo_10}; // @[ReservationStation.scala:506:12] wire [7:0] _packed_deps_T_20 = {packed_deps_hi_20, packed_deps_lo_15}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_lo_lo_lo_5 = {entries_ld_5_bits_deps_ex_1, entries_ld_5_bits_deps_ex_0}; // @[ReservationStation.scala:117:23, :506:41] wire [1:0] packed_deps_lo_lo_hi_5 = {entries_ld_5_bits_deps_ex_3, entries_ld_5_bits_deps_ex_2}; // @[ReservationStation.scala:117:23, :506:41] wire [3:0] packed_deps_lo_lo_11 = {packed_deps_lo_lo_hi_5, packed_deps_lo_lo_lo_5}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_hi_lo_5 = {entries_ld_5_bits_deps_ex_5, entries_ld_5_bits_deps_ex_4}; // @[ReservationStation.scala:117:23, :506:41] wire [1:0] packed_deps_lo_hi_hi_5 = {entries_ld_5_bits_deps_ex_7, entries_ld_5_bits_deps_ex_6}; // @[ReservationStation.scala:117:23, :506:41] wire [3:0] packed_deps_lo_hi_11 = {packed_deps_lo_hi_hi_5, packed_deps_lo_hi_lo_5}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_lo_16 = {packed_deps_lo_hi_11, packed_deps_lo_lo_11}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_lo_lo_5 = {entries_ld_5_bits_deps_ex_9, entries_ld_5_bits_deps_ex_8}; // @[ReservationStation.scala:117:23, :506:41] wire [1:0] packed_deps_hi_lo_hi_5 = {entries_ld_5_bits_deps_ex_11, entries_ld_5_bits_deps_ex_10}; // @[ReservationStation.scala:117:23, :506:41] wire [3:0] packed_deps_hi_lo_11 = {packed_deps_hi_lo_hi_5, packed_deps_hi_lo_lo_5}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_hi_lo_5 = {entries_ld_5_bits_deps_ex_13, entries_ld_5_bits_deps_ex_12}; // @[ReservationStation.scala:117:23, :506:41] wire [1:0] packed_deps_hi_hi_hi_5 = {entries_ld_5_bits_deps_ex_15, entries_ld_5_bits_deps_ex_14}; // @[ReservationStation.scala:117:23, :506:41] wire [3:0] packed_deps_hi_hi_11 = {packed_deps_hi_hi_hi_5, packed_deps_hi_hi_lo_5}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_hi_21 = {packed_deps_hi_hi_11, packed_deps_hi_lo_11}; // @[ReservationStation.scala:506:41] wire [15:0] _packed_deps_T_21 = {packed_deps_hi_21, packed_deps_lo_16}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_17 = {entries_ld_5_bits_deps_st_1, entries_ld_5_bits_deps_st_0}; // @[ReservationStation.scala:117:23, :506:70] wire [1:0] packed_deps_hi_22 = {entries_ld_5_bits_deps_st_3, entries_ld_5_bits_deps_st_2}; // @[ReservationStation.scala:117:23, :506:70] wire [3:0] _packed_deps_T_22 = {packed_deps_hi_22, packed_deps_lo_17}; // @[ReservationStation.scala:506:70] wire [23:0] packed_deps_hi_23 = {_packed_deps_T_20, _packed_deps_T_21}; // @[ReservationStation.scala:506:{8,12,41}] wire [27:0] _packed_deps_T_23 = {packed_deps_hi_23, _packed_deps_T_22}; // @[ReservationStation.scala:506:{8,70}] wire [27:0] packed_deps_5 = _packed_deps_T_23; // @[ReservationStation.scala:505:28, :506:8] wire [1:0] packed_deps_lo_lo_12 = {entries_ld_6_bits_deps_ld_1, entries_ld_6_bits_deps_ld_0}; // @[ReservationStation.scala:117:23, :506:12] wire [1:0] packed_deps_lo_hi_12 = {entries_ld_6_bits_deps_ld_3, entries_ld_6_bits_deps_ld_2}; // @[ReservationStation.scala:117:23, :506:12] wire [3:0] packed_deps_lo_18 = {packed_deps_lo_hi_12, packed_deps_lo_lo_12}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_hi_lo_12 = {entries_ld_6_bits_deps_ld_5, entries_ld_6_bits_deps_ld_4}; // @[ReservationStation.scala:117:23, :506:12] wire [1:0] packed_deps_hi_hi_12 = {entries_ld_6_bits_deps_ld_7, entries_ld_6_bits_deps_ld_6}; // @[ReservationStation.scala:117:23, :506:12] wire [3:0] packed_deps_hi_24 = {packed_deps_hi_hi_12, packed_deps_hi_lo_12}; // @[ReservationStation.scala:506:12] wire [7:0] _packed_deps_T_24 = {packed_deps_hi_24, packed_deps_lo_18}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_lo_lo_lo_6 = {entries_ld_6_bits_deps_ex_1, entries_ld_6_bits_deps_ex_0}; // @[ReservationStation.scala:117:23, :506:41] wire [1:0] packed_deps_lo_lo_hi_6 = {entries_ld_6_bits_deps_ex_3, entries_ld_6_bits_deps_ex_2}; // @[ReservationStation.scala:117:23, :506:41] wire [3:0] packed_deps_lo_lo_13 = {packed_deps_lo_lo_hi_6, packed_deps_lo_lo_lo_6}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_hi_lo_6 = {entries_ld_6_bits_deps_ex_5, entries_ld_6_bits_deps_ex_4}; // @[ReservationStation.scala:117:23, :506:41] wire [1:0] packed_deps_lo_hi_hi_6 = {entries_ld_6_bits_deps_ex_7, entries_ld_6_bits_deps_ex_6}; // @[ReservationStation.scala:117:23, :506:41] wire [3:0] packed_deps_lo_hi_13 = {packed_deps_lo_hi_hi_6, packed_deps_lo_hi_lo_6}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_lo_19 = {packed_deps_lo_hi_13, packed_deps_lo_lo_13}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_lo_lo_6 = {entries_ld_6_bits_deps_ex_9, entries_ld_6_bits_deps_ex_8}; // @[ReservationStation.scala:117:23, :506:41] wire [1:0] packed_deps_hi_lo_hi_6 = {entries_ld_6_bits_deps_ex_11, entries_ld_6_bits_deps_ex_10}; // @[ReservationStation.scala:117:23, :506:41] wire [3:0] packed_deps_hi_lo_13 = {packed_deps_hi_lo_hi_6, packed_deps_hi_lo_lo_6}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_hi_lo_6 = {entries_ld_6_bits_deps_ex_13, entries_ld_6_bits_deps_ex_12}; // @[ReservationStation.scala:117:23, :506:41] wire [1:0] packed_deps_hi_hi_hi_6 = {entries_ld_6_bits_deps_ex_15, entries_ld_6_bits_deps_ex_14}; // @[ReservationStation.scala:117:23, :506:41] wire [3:0] packed_deps_hi_hi_13 = {packed_deps_hi_hi_hi_6, packed_deps_hi_hi_lo_6}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_hi_25 = {packed_deps_hi_hi_13, packed_deps_hi_lo_13}; // @[ReservationStation.scala:506:41] wire [15:0] _packed_deps_T_25 = {packed_deps_hi_25, packed_deps_lo_19}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_20 = {entries_ld_6_bits_deps_st_1, entries_ld_6_bits_deps_st_0}; // @[ReservationStation.scala:117:23, :506:70] wire [1:0] packed_deps_hi_26 = {entries_ld_6_bits_deps_st_3, entries_ld_6_bits_deps_st_2}; // @[ReservationStation.scala:117:23, :506:70] wire [3:0] _packed_deps_T_26 = {packed_deps_hi_26, packed_deps_lo_20}; // @[ReservationStation.scala:506:70] wire [23:0] packed_deps_hi_27 = {_packed_deps_T_24, _packed_deps_T_25}; // @[ReservationStation.scala:506:{8,12,41}] wire [27:0] _packed_deps_T_27 = {packed_deps_hi_27, _packed_deps_T_26}; // @[ReservationStation.scala:506:{8,70}] wire [27:0] packed_deps_6 = _packed_deps_T_27; // @[ReservationStation.scala:505:28, :506:8] wire [1:0] packed_deps_lo_lo_14 = {entries_ld_7_bits_deps_ld_1, entries_ld_7_bits_deps_ld_0}; // @[ReservationStation.scala:117:23, :506:12] wire [1:0] packed_deps_lo_hi_14 = {entries_ld_7_bits_deps_ld_3, entries_ld_7_bits_deps_ld_2}; // @[ReservationStation.scala:117:23, :506:12] wire [3:0] packed_deps_lo_21 = {packed_deps_lo_hi_14, packed_deps_lo_lo_14}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_hi_lo_14 = {entries_ld_7_bits_deps_ld_5, entries_ld_7_bits_deps_ld_4}; // @[ReservationStation.scala:117:23, :506:12] wire [1:0] packed_deps_hi_hi_14 = {entries_ld_7_bits_deps_ld_7, entries_ld_7_bits_deps_ld_6}; // @[ReservationStation.scala:117:23, :506:12] wire [3:0] packed_deps_hi_28 = {packed_deps_hi_hi_14, packed_deps_hi_lo_14}; // @[ReservationStation.scala:506:12] wire [7:0] _packed_deps_T_28 = {packed_deps_hi_28, packed_deps_lo_21}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_lo_lo_lo_7 = {entries_ld_7_bits_deps_ex_1, entries_ld_7_bits_deps_ex_0}; // @[ReservationStation.scala:117:23, :506:41] wire [1:0] packed_deps_lo_lo_hi_7 = {entries_ld_7_bits_deps_ex_3, entries_ld_7_bits_deps_ex_2}; // @[ReservationStation.scala:117:23, :506:41] wire [3:0] packed_deps_lo_lo_15 = {packed_deps_lo_lo_hi_7, packed_deps_lo_lo_lo_7}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_hi_lo_7 = {entries_ld_7_bits_deps_ex_5, entries_ld_7_bits_deps_ex_4}; // @[ReservationStation.scala:117:23, :506:41] wire [1:0] packed_deps_lo_hi_hi_7 = {entries_ld_7_bits_deps_ex_7, entries_ld_7_bits_deps_ex_6}; // @[ReservationStation.scala:117:23, :506:41] wire [3:0] packed_deps_lo_hi_15 = {packed_deps_lo_hi_hi_7, packed_deps_lo_hi_lo_7}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_lo_22 = {packed_deps_lo_hi_15, packed_deps_lo_lo_15}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_lo_lo_7 = {entries_ld_7_bits_deps_ex_9, entries_ld_7_bits_deps_ex_8}; // @[ReservationStation.scala:117:23, :506:41] wire [1:0] packed_deps_hi_lo_hi_7 = {entries_ld_7_bits_deps_ex_11, entries_ld_7_bits_deps_ex_10}; // @[ReservationStation.scala:117:23, :506:41] wire [3:0] packed_deps_hi_lo_15 = {packed_deps_hi_lo_hi_7, packed_deps_hi_lo_lo_7}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_hi_lo_7 = {entries_ld_7_bits_deps_ex_13, entries_ld_7_bits_deps_ex_12}; // @[ReservationStation.scala:117:23, :506:41] wire [1:0] packed_deps_hi_hi_hi_7 = {entries_ld_7_bits_deps_ex_15, entries_ld_7_bits_deps_ex_14}; // @[ReservationStation.scala:117:23, :506:41] wire [3:0] packed_deps_hi_hi_15 = {packed_deps_hi_hi_hi_7, packed_deps_hi_hi_lo_7}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_hi_29 = {packed_deps_hi_hi_15, packed_deps_hi_lo_15}; // @[ReservationStation.scala:506:41] wire [15:0] _packed_deps_T_29 = {packed_deps_hi_29, packed_deps_lo_22}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_23 = {entries_ld_7_bits_deps_st_1, entries_ld_7_bits_deps_st_0}; // @[ReservationStation.scala:117:23, :506:70] wire [1:0] packed_deps_hi_30 = {entries_ld_7_bits_deps_st_3, entries_ld_7_bits_deps_st_2}; // @[ReservationStation.scala:117:23, :506:70] wire [3:0] _packed_deps_T_30 = {packed_deps_hi_30, packed_deps_lo_23}; // @[ReservationStation.scala:506:70] wire [23:0] packed_deps_hi_31 = {_packed_deps_T_28, _packed_deps_T_29}; // @[ReservationStation.scala:506:{8,12,41}] wire [27:0] _packed_deps_T_31 = {packed_deps_hi_31, _packed_deps_T_30}; // @[ReservationStation.scala:506:{8,70}] wire [27:0] packed_deps_7 = _packed_deps_T_31; // @[ReservationStation.scala:505:28, :506:8] wire [1:0] packed_deps_lo_lo_16 = {entries_ex_0_bits_deps_ld_1, entries_ex_0_bits_deps_ld_0}; // @[ReservationStation.scala:118:23, :506:12] wire [1:0] packed_deps_lo_hi_16 = {entries_ex_0_bits_deps_ld_3, entries_ex_0_bits_deps_ld_2}; // @[ReservationStation.scala:118:23, :506:12] wire [3:0] packed_deps_lo_24 = {packed_deps_lo_hi_16, packed_deps_lo_lo_16}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_hi_lo_16 = {entries_ex_0_bits_deps_ld_5, entries_ex_0_bits_deps_ld_4}; // @[ReservationStation.scala:118:23, :506:12] wire [1:0] packed_deps_hi_hi_16 = {entries_ex_0_bits_deps_ld_7, entries_ex_0_bits_deps_ld_6}; // @[ReservationStation.scala:118:23, :506:12] wire [3:0] packed_deps_hi_32 = {packed_deps_hi_hi_16, packed_deps_hi_lo_16}; // @[ReservationStation.scala:506:12] wire [7:0] _packed_deps_T_32 = {packed_deps_hi_32, packed_deps_lo_24}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_lo_lo_lo_8 = {entries_ex_0_bits_deps_ex_1, entries_ex_0_bits_deps_ex_0}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_lo_lo_hi_8 = {entries_ex_0_bits_deps_ex_3, entries_ex_0_bits_deps_ex_2}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_lo_lo_17 = {packed_deps_lo_lo_hi_8, packed_deps_lo_lo_lo_8}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_hi_lo_8 = {entries_ex_0_bits_deps_ex_5, entries_ex_0_bits_deps_ex_4}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_lo_hi_hi_8 = {entries_ex_0_bits_deps_ex_7, entries_ex_0_bits_deps_ex_6}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_lo_hi_17 = {packed_deps_lo_hi_hi_8, packed_deps_lo_hi_lo_8}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_lo_25 = {packed_deps_lo_hi_17, packed_deps_lo_lo_17}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_lo_lo_8 = {entries_ex_0_bits_deps_ex_9, entries_ex_0_bits_deps_ex_8}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_hi_lo_hi_8 = {entries_ex_0_bits_deps_ex_11, entries_ex_0_bits_deps_ex_10}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_hi_lo_17 = {packed_deps_hi_lo_hi_8, packed_deps_hi_lo_lo_8}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_hi_lo_8 = {entries_ex_0_bits_deps_ex_13, entries_ex_0_bits_deps_ex_12}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_hi_hi_hi_8 = {entries_ex_0_bits_deps_ex_15, entries_ex_0_bits_deps_ex_14}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_hi_hi_17 = {packed_deps_hi_hi_hi_8, packed_deps_hi_hi_lo_8}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_hi_33 = {packed_deps_hi_hi_17, packed_deps_hi_lo_17}; // @[ReservationStation.scala:506:41] wire [15:0] _packed_deps_T_33 = {packed_deps_hi_33, packed_deps_lo_25}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_26 = {entries_ex_0_bits_deps_st_1, entries_ex_0_bits_deps_st_0}; // @[ReservationStation.scala:118:23, :506:70] wire [1:0] packed_deps_hi_34 = {entries_ex_0_bits_deps_st_3, entries_ex_0_bits_deps_st_2}; // @[ReservationStation.scala:118:23, :506:70] wire [3:0] _packed_deps_T_34 = {packed_deps_hi_34, packed_deps_lo_26}; // @[ReservationStation.scala:506:70] wire [23:0] packed_deps_hi_35 = {_packed_deps_T_32, _packed_deps_T_33}; // @[ReservationStation.scala:506:{8,12,41}] wire [27:0] _packed_deps_T_35 = {packed_deps_hi_35, _packed_deps_T_34}; // @[ReservationStation.scala:506:{8,70}] wire [27:0] packed_deps_8 = _packed_deps_T_35; // @[ReservationStation.scala:505:28, :506:8] wire [1:0] packed_deps_lo_lo_18 = {entries_ex_1_bits_deps_ld_1, entries_ex_1_bits_deps_ld_0}; // @[ReservationStation.scala:118:23, :506:12] wire [1:0] packed_deps_lo_hi_18 = {entries_ex_1_bits_deps_ld_3, entries_ex_1_bits_deps_ld_2}; // @[ReservationStation.scala:118:23, :506:12] wire [3:0] packed_deps_lo_27 = {packed_deps_lo_hi_18, packed_deps_lo_lo_18}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_hi_lo_18 = {entries_ex_1_bits_deps_ld_5, entries_ex_1_bits_deps_ld_4}; // @[ReservationStation.scala:118:23, :506:12] wire [1:0] packed_deps_hi_hi_18 = {entries_ex_1_bits_deps_ld_7, entries_ex_1_bits_deps_ld_6}; // @[ReservationStation.scala:118:23, :506:12] wire [3:0] packed_deps_hi_36 = {packed_deps_hi_hi_18, packed_deps_hi_lo_18}; // @[ReservationStation.scala:506:12] wire [7:0] _packed_deps_T_36 = {packed_deps_hi_36, packed_deps_lo_27}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_lo_lo_lo_9 = {entries_ex_1_bits_deps_ex_1, entries_ex_1_bits_deps_ex_0}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_lo_lo_hi_9 = {entries_ex_1_bits_deps_ex_3, entries_ex_1_bits_deps_ex_2}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_lo_lo_19 = {packed_deps_lo_lo_hi_9, packed_deps_lo_lo_lo_9}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_hi_lo_9 = {entries_ex_1_bits_deps_ex_5, entries_ex_1_bits_deps_ex_4}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_lo_hi_hi_9 = {entries_ex_1_bits_deps_ex_7, entries_ex_1_bits_deps_ex_6}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_lo_hi_19 = {packed_deps_lo_hi_hi_9, packed_deps_lo_hi_lo_9}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_lo_28 = {packed_deps_lo_hi_19, packed_deps_lo_lo_19}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_lo_lo_9 = {entries_ex_1_bits_deps_ex_9, entries_ex_1_bits_deps_ex_8}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_hi_lo_hi_9 = {entries_ex_1_bits_deps_ex_11, entries_ex_1_bits_deps_ex_10}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_hi_lo_19 = {packed_deps_hi_lo_hi_9, packed_deps_hi_lo_lo_9}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_hi_lo_9 = {entries_ex_1_bits_deps_ex_13, entries_ex_1_bits_deps_ex_12}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_hi_hi_hi_9 = {entries_ex_1_bits_deps_ex_15, entries_ex_1_bits_deps_ex_14}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_hi_hi_19 = {packed_deps_hi_hi_hi_9, packed_deps_hi_hi_lo_9}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_hi_37 = {packed_deps_hi_hi_19, packed_deps_hi_lo_19}; // @[ReservationStation.scala:506:41] wire [15:0] _packed_deps_T_37 = {packed_deps_hi_37, packed_deps_lo_28}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_29 = {entries_ex_1_bits_deps_st_1, entries_ex_1_bits_deps_st_0}; // @[ReservationStation.scala:118:23, :506:70] wire [1:0] packed_deps_hi_38 = {entries_ex_1_bits_deps_st_3, entries_ex_1_bits_deps_st_2}; // @[ReservationStation.scala:118:23, :506:70] wire [3:0] _packed_deps_T_38 = {packed_deps_hi_38, packed_deps_lo_29}; // @[ReservationStation.scala:506:70] wire [23:0] packed_deps_hi_39 = {_packed_deps_T_36, _packed_deps_T_37}; // @[ReservationStation.scala:506:{8,12,41}] wire [27:0] _packed_deps_T_39 = {packed_deps_hi_39, _packed_deps_T_38}; // @[ReservationStation.scala:506:{8,70}] wire [27:0] packed_deps_9 = _packed_deps_T_39; // @[ReservationStation.scala:505:28, :506:8] wire [1:0] packed_deps_lo_lo_20 = {entries_ex_2_bits_deps_ld_1, entries_ex_2_bits_deps_ld_0}; // @[ReservationStation.scala:118:23, :506:12] wire [1:0] packed_deps_lo_hi_20 = {entries_ex_2_bits_deps_ld_3, entries_ex_2_bits_deps_ld_2}; // @[ReservationStation.scala:118:23, :506:12] wire [3:0] packed_deps_lo_30 = {packed_deps_lo_hi_20, packed_deps_lo_lo_20}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_hi_lo_20 = {entries_ex_2_bits_deps_ld_5, entries_ex_2_bits_deps_ld_4}; // @[ReservationStation.scala:118:23, :506:12] wire [1:0] packed_deps_hi_hi_20 = {entries_ex_2_bits_deps_ld_7, entries_ex_2_bits_deps_ld_6}; // @[ReservationStation.scala:118:23, :506:12] wire [3:0] packed_deps_hi_40 = {packed_deps_hi_hi_20, packed_deps_hi_lo_20}; // @[ReservationStation.scala:506:12] wire [7:0] _packed_deps_T_40 = {packed_deps_hi_40, packed_deps_lo_30}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_lo_lo_lo_10 = {entries_ex_2_bits_deps_ex_1, entries_ex_2_bits_deps_ex_0}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_lo_lo_hi_10 = {entries_ex_2_bits_deps_ex_3, entries_ex_2_bits_deps_ex_2}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_lo_lo_21 = {packed_deps_lo_lo_hi_10, packed_deps_lo_lo_lo_10}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_hi_lo_10 = {entries_ex_2_bits_deps_ex_5, entries_ex_2_bits_deps_ex_4}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_lo_hi_hi_10 = {entries_ex_2_bits_deps_ex_7, entries_ex_2_bits_deps_ex_6}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_lo_hi_21 = {packed_deps_lo_hi_hi_10, packed_deps_lo_hi_lo_10}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_lo_31 = {packed_deps_lo_hi_21, packed_deps_lo_lo_21}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_lo_lo_10 = {entries_ex_2_bits_deps_ex_9, entries_ex_2_bits_deps_ex_8}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_hi_lo_hi_10 = {entries_ex_2_bits_deps_ex_11, entries_ex_2_bits_deps_ex_10}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_hi_lo_21 = {packed_deps_hi_lo_hi_10, packed_deps_hi_lo_lo_10}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_hi_lo_10 = {entries_ex_2_bits_deps_ex_13, entries_ex_2_bits_deps_ex_12}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_hi_hi_hi_10 = {entries_ex_2_bits_deps_ex_15, entries_ex_2_bits_deps_ex_14}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_hi_hi_21 = {packed_deps_hi_hi_hi_10, packed_deps_hi_hi_lo_10}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_hi_41 = {packed_deps_hi_hi_21, packed_deps_hi_lo_21}; // @[ReservationStation.scala:506:41] wire [15:0] _packed_deps_T_41 = {packed_deps_hi_41, packed_deps_lo_31}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_32 = {entries_ex_2_bits_deps_st_1, entries_ex_2_bits_deps_st_0}; // @[ReservationStation.scala:118:23, :506:70] wire [1:0] packed_deps_hi_42 = {entries_ex_2_bits_deps_st_3, entries_ex_2_bits_deps_st_2}; // @[ReservationStation.scala:118:23, :506:70] wire [3:0] _packed_deps_T_42 = {packed_deps_hi_42, packed_deps_lo_32}; // @[ReservationStation.scala:506:70] wire [23:0] packed_deps_hi_43 = {_packed_deps_T_40, _packed_deps_T_41}; // @[ReservationStation.scala:506:{8,12,41}] wire [27:0] _packed_deps_T_43 = {packed_deps_hi_43, _packed_deps_T_42}; // @[ReservationStation.scala:506:{8,70}] wire [27:0] packed_deps_10 = _packed_deps_T_43; // @[ReservationStation.scala:505:28, :506:8] wire [1:0] packed_deps_lo_lo_22 = {entries_ex_3_bits_deps_ld_1, entries_ex_3_bits_deps_ld_0}; // @[ReservationStation.scala:118:23, :506:12] wire [1:0] packed_deps_lo_hi_22 = {entries_ex_3_bits_deps_ld_3, entries_ex_3_bits_deps_ld_2}; // @[ReservationStation.scala:118:23, :506:12] wire [3:0] packed_deps_lo_33 = {packed_deps_lo_hi_22, packed_deps_lo_lo_22}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_hi_lo_22 = {entries_ex_3_bits_deps_ld_5, entries_ex_3_bits_deps_ld_4}; // @[ReservationStation.scala:118:23, :506:12] wire [1:0] packed_deps_hi_hi_22 = {entries_ex_3_bits_deps_ld_7, entries_ex_3_bits_deps_ld_6}; // @[ReservationStation.scala:118:23, :506:12] wire [3:0] packed_deps_hi_44 = {packed_deps_hi_hi_22, packed_deps_hi_lo_22}; // @[ReservationStation.scala:506:12] wire [7:0] _packed_deps_T_44 = {packed_deps_hi_44, packed_deps_lo_33}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_lo_lo_lo_11 = {entries_ex_3_bits_deps_ex_1, entries_ex_3_bits_deps_ex_0}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_lo_lo_hi_11 = {entries_ex_3_bits_deps_ex_3, entries_ex_3_bits_deps_ex_2}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_lo_lo_23 = {packed_deps_lo_lo_hi_11, packed_deps_lo_lo_lo_11}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_hi_lo_11 = {entries_ex_3_bits_deps_ex_5, entries_ex_3_bits_deps_ex_4}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_lo_hi_hi_11 = {entries_ex_3_bits_deps_ex_7, entries_ex_3_bits_deps_ex_6}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_lo_hi_23 = {packed_deps_lo_hi_hi_11, packed_deps_lo_hi_lo_11}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_lo_34 = {packed_deps_lo_hi_23, packed_deps_lo_lo_23}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_lo_lo_11 = {entries_ex_3_bits_deps_ex_9, entries_ex_3_bits_deps_ex_8}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_hi_lo_hi_11 = {entries_ex_3_bits_deps_ex_11, entries_ex_3_bits_deps_ex_10}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_hi_lo_23 = {packed_deps_hi_lo_hi_11, packed_deps_hi_lo_lo_11}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_hi_lo_11 = {entries_ex_3_bits_deps_ex_13, entries_ex_3_bits_deps_ex_12}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_hi_hi_hi_11 = {entries_ex_3_bits_deps_ex_15, entries_ex_3_bits_deps_ex_14}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_hi_hi_23 = {packed_deps_hi_hi_hi_11, packed_deps_hi_hi_lo_11}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_hi_45 = {packed_deps_hi_hi_23, packed_deps_hi_lo_23}; // @[ReservationStation.scala:506:41] wire [15:0] _packed_deps_T_45 = {packed_deps_hi_45, packed_deps_lo_34}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_35 = {entries_ex_3_bits_deps_st_1, entries_ex_3_bits_deps_st_0}; // @[ReservationStation.scala:118:23, :506:70] wire [1:0] packed_deps_hi_46 = {entries_ex_3_bits_deps_st_3, entries_ex_3_bits_deps_st_2}; // @[ReservationStation.scala:118:23, :506:70] wire [3:0] _packed_deps_T_46 = {packed_deps_hi_46, packed_deps_lo_35}; // @[ReservationStation.scala:506:70] wire [23:0] packed_deps_hi_47 = {_packed_deps_T_44, _packed_deps_T_45}; // @[ReservationStation.scala:506:{8,12,41}] wire [27:0] _packed_deps_T_47 = {packed_deps_hi_47, _packed_deps_T_46}; // @[ReservationStation.scala:506:{8,70}] wire [27:0] packed_deps_11 = _packed_deps_T_47; // @[ReservationStation.scala:505:28, :506:8] wire [1:0] packed_deps_lo_lo_24 = {entries_ex_4_bits_deps_ld_1, entries_ex_4_bits_deps_ld_0}; // @[ReservationStation.scala:118:23, :506:12] wire [1:0] packed_deps_lo_hi_24 = {entries_ex_4_bits_deps_ld_3, entries_ex_4_bits_deps_ld_2}; // @[ReservationStation.scala:118:23, :506:12] wire [3:0] packed_deps_lo_36 = {packed_deps_lo_hi_24, packed_deps_lo_lo_24}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_hi_lo_24 = {entries_ex_4_bits_deps_ld_5, entries_ex_4_bits_deps_ld_4}; // @[ReservationStation.scala:118:23, :506:12] wire [1:0] packed_deps_hi_hi_24 = {entries_ex_4_bits_deps_ld_7, entries_ex_4_bits_deps_ld_6}; // @[ReservationStation.scala:118:23, :506:12] wire [3:0] packed_deps_hi_48 = {packed_deps_hi_hi_24, packed_deps_hi_lo_24}; // @[ReservationStation.scala:506:12] wire [7:0] _packed_deps_T_48 = {packed_deps_hi_48, packed_deps_lo_36}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_lo_lo_lo_12 = {entries_ex_4_bits_deps_ex_1, entries_ex_4_bits_deps_ex_0}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_lo_lo_hi_12 = {entries_ex_4_bits_deps_ex_3, entries_ex_4_bits_deps_ex_2}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_lo_lo_25 = {packed_deps_lo_lo_hi_12, packed_deps_lo_lo_lo_12}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_hi_lo_12 = {entries_ex_4_bits_deps_ex_5, entries_ex_4_bits_deps_ex_4}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_lo_hi_hi_12 = {entries_ex_4_bits_deps_ex_7, entries_ex_4_bits_deps_ex_6}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_lo_hi_25 = {packed_deps_lo_hi_hi_12, packed_deps_lo_hi_lo_12}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_lo_37 = {packed_deps_lo_hi_25, packed_deps_lo_lo_25}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_lo_lo_12 = {entries_ex_4_bits_deps_ex_9, entries_ex_4_bits_deps_ex_8}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_hi_lo_hi_12 = {entries_ex_4_bits_deps_ex_11, entries_ex_4_bits_deps_ex_10}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_hi_lo_25 = {packed_deps_hi_lo_hi_12, packed_deps_hi_lo_lo_12}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_hi_lo_12 = {entries_ex_4_bits_deps_ex_13, entries_ex_4_bits_deps_ex_12}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_hi_hi_hi_12 = {entries_ex_4_bits_deps_ex_15, entries_ex_4_bits_deps_ex_14}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_hi_hi_25 = {packed_deps_hi_hi_hi_12, packed_deps_hi_hi_lo_12}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_hi_49 = {packed_deps_hi_hi_25, packed_deps_hi_lo_25}; // @[ReservationStation.scala:506:41] wire [15:0] _packed_deps_T_49 = {packed_deps_hi_49, packed_deps_lo_37}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_38 = {entries_ex_4_bits_deps_st_1, entries_ex_4_bits_deps_st_0}; // @[ReservationStation.scala:118:23, :506:70] wire [1:0] packed_deps_hi_50 = {entries_ex_4_bits_deps_st_3, entries_ex_4_bits_deps_st_2}; // @[ReservationStation.scala:118:23, :506:70] wire [3:0] _packed_deps_T_50 = {packed_deps_hi_50, packed_deps_lo_38}; // @[ReservationStation.scala:506:70] wire [23:0] packed_deps_hi_51 = {_packed_deps_T_48, _packed_deps_T_49}; // @[ReservationStation.scala:506:{8,12,41}] wire [27:0] _packed_deps_T_51 = {packed_deps_hi_51, _packed_deps_T_50}; // @[ReservationStation.scala:506:{8,70}] wire [27:0] packed_deps_12 = _packed_deps_T_51; // @[ReservationStation.scala:505:28, :506:8] wire [1:0] packed_deps_lo_lo_26 = {entries_ex_5_bits_deps_ld_1, entries_ex_5_bits_deps_ld_0}; // @[ReservationStation.scala:118:23, :506:12] wire [1:0] packed_deps_lo_hi_26 = {entries_ex_5_bits_deps_ld_3, entries_ex_5_bits_deps_ld_2}; // @[ReservationStation.scala:118:23, :506:12] wire [3:0] packed_deps_lo_39 = {packed_deps_lo_hi_26, packed_deps_lo_lo_26}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_hi_lo_26 = {entries_ex_5_bits_deps_ld_5, entries_ex_5_bits_deps_ld_4}; // @[ReservationStation.scala:118:23, :506:12] wire [1:0] packed_deps_hi_hi_26 = {entries_ex_5_bits_deps_ld_7, entries_ex_5_bits_deps_ld_6}; // @[ReservationStation.scala:118:23, :506:12] wire [3:0] packed_deps_hi_52 = {packed_deps_hi_hi_26, packed_deps_hi_lo_26}; // @[ReservationStation.scala:506:12] wire [7:0] _packed_deps_T_52 = {packed_deps_hi_52, packed_deps_lo_39}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_lo_lo_lo_13 = {entries_ex_5_bits_deps_ex_1, entries_ex_5_bits_deps_ex_0}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_lo_lo_hi_13 = {entries_ex_5_bits_deps_ex_3, entries_ex_5_bits_deps_ex_2}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_lo_lo_27 = {packed_deps_lo_lo_hi_13, packed_deps_lo_lo_lo_13}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_hi_lo_13 = {entries_ex_5_bits_deps_ex_5, entries_ex_5_bits_deps_ex_4}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_lo_hi_hi_13 = {entries_ex_5_bits_deps_ex_7, entries_ex_5_bits_deps_ex_6}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_lo_hi_27 = {packed_deps_lo_hi_hi_13, packed_deps_lo_hi_lo_13}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_lo_40 = {packed_deps_lo_hi_27, packed_deps_lo_lo_27}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_lo_lo_13 = {entries_ex_5_bits_deps_ex_9, entries_ex_5_bits_deps_ex_8}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_hi_lo_hi_13 = {entries_ex_5_bits_deps_ex_11, entries_ex_5_bits_deps_ex_10}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_hi_lo_27 = {packed_deps_hi_lo_hi_13, packed_deps_hi_lo_lo_13}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_hi_lo_13 = {entries_ex_5_bits_deps_ex_13, entries_ex_5_bits_deps_ex_12}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_hi_hi_hi_13 = {entries_ex_5_bits_deps_ex_15, entries_ex_5_bits_deps_ex_14}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_hi_hi_27 = {packed_deps_hi_hi_hi_13, packed_deps_hi_hi_lo_13}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_hi_53 = {packed_deps_hi_hi_27, packed_deps_hi_lo_27}; // @[ReservationStation.scala:506:41] wire [15:0] _packed_deps_T_53 = {packed_deps_hi_53, packed_deps_lo_40}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_41 = {entries_ex_5_bits_deps_st_1, entries_ex_5_bits_deps_st_0}; // @[ReservationStation.scala:118:23, :506:70] wire [1:0] packed_deps_hi_54 = {entries_ex_5_bits_deps_st_3, entries_ex_5_bits_deps_st_2}; // @[ReservationStation.scala:118:23, :506:70] wire [3:0] _packed_deps_T_54 = {packed_deps_hi_54, packed_deps_lo_41}; // @[ReservationStation.scala:506:70] wire [23:0] packed_deps_hi_55 = {_packed_deps_T_52, _packed_deps_T_53}; // @[ReservationStation.scala:506:{8,12,41}] wire [27:0] _packed_deps_T_55 = {packed_deps_hi_55, _packed_deps_T_54}; // @[ReservationStation.scala:506:{8,70}] wire [27:0] packed_deps_13 = _packed_deps_T_55; // @[ReservationStation.scala:505:28, :506:8] wire [1:0] packed_deps_lo_lo_28 = {entries_ex_6_bits_deps_ld_1, entries_ex_6_bits_deps_ld_0}; // @[ReservationStation.scala:118:23, :506:12] wire [1:0] packed_deps_lo_hi_28 = {entries_ex_6_bits_deps_ld_3, entries_ex_6_bits_deps_ld_2}; // @[ReservationStation.scala:118:23, :506:12] wire [3:0] packed_deps_lo_42 = {packed_deps_lo_hi_28, packed_deps_lo_lo_28}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_hi_lo_28 = {entries_ex_6_bits_deps_ld_5, entries_ex_6_bits_deps_ld_4}; // @[ReservationStation.scala:118:23, :506:12] wire [1:0] packed_deps_hi_hi_28 = {entries_ex_6_bits_deps_ld_7, entries_ex_6_bits_deps_ld_6}; // @[ReservationStation.scala:118:23, :506:12] wire [3:0] packed_deps_hi_56 = {packed_deps_hi_hi_28, packed_deps_hi_lo_28}; // @[ReservationStation.scala:506:12] wire [7:0] _packed_deps_T_56 = {packed_deps_hi_56, packed_deps_lo_42}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_lo_lo_lo_14 = {entries_ex_6_bits_deps_ex_1, entries_ex_6_bits_deps_ex_0}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_lo_lo_hi_14 = {entries_ex_6_bits_deps_ex_3, entries_ex_6_bits_deps_ex_2}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_lo_lo_29 = {packed_deps_lo_lo_hi_14, packed_deps_lo_lo_lo_14}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_hi_lo_14 = {entries_ex_6_bits_deps_ex_5, entries_ex_6_bits_deps_ex_4}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_lo_hi_hi_14 = {entries_ex_6_bits_deps_ex_7, entries_ex_6_bits_deps_ex_6}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_lo_hi_29 = {packed_deps_lo_hi_hi_14, packed_deps_lo_hi_lo_14}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_lo_43 = {packed_deps_lo_hi_29, packed_deps_lo_lo_29}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_lo_lo_14 = {entries_ex_6_bits_deps_ex_9, entries_ex_6_bits_deps_ex_8}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_hi_lo_hi_14 = {entries_ex_6_bits_deps_ex_11, entries_ex_6_bits_deps_ex_10}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_hi_lo_29 = {packed_deps_hi_lo_hi_14, packed_deps_hi_lo_lo_14}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_hi_lo_14 = {entries_ex_6_bits_deps_ex_13, entries_ex_6_bits_deps_ex_12}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_hi_hi_hi_14 = {entries_ex_6_bits_deps_ex_15, entries_ex_6_bits_deps_ex_14}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_hi_hi_29 = {packed_deps_hi_hi_hi_14, packed_deps_hi_hi_lo_14}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_hi_57 = {packed_deps_hi_hi_29, packed_deps_hi_lo_29}; // @[ReservationStation.scala:506:41] wire [15:0] _packed_deps_T_57 = {packed_deps_hi_57, packed_deps_lo_43}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_44 = {entries_ex_6_bits_deps_st_1, entries_ex_6_bits_deps_st_0}; // @[ReservationStation.scala:118:23, :506:70] wire [1:0] packed_deps_hi_58 = {entries_ex_6_bits_deps_st_3, entries_ex_6_bits_deps_st_2}; // @[ReservationStation.scala:118:23, :506:70] wire [3:0] _packed_deps_T_58 = {packed_deps_hi_58, packed_deps_lo_44}; // @[ReservationStation.scala:506:70] wire [23:0] packed_deps_hi_59 = {_packed_deps_T_56, _packed_deps_T_57}; // @[ReservationStation.scala:506:{8,12,41}] wire [27:0] _packed_deps_T_59 = {packed_deps_hi_59, _packed_deps_T_58}; // @[ReservationStation.scala:506:{8,70}] wire [27:0] packed_deps_14 = _packed_deps_T_59; // @[ReservationStation.scala:505:28, :506:8] wire [1:0] packed_deps_lo_lo_30 = {entries_ex_7_bits_deps_ld_1, entries_ex_7_bits_deps_ld_0}; // @[ReservationStation.scala:118:23, :506:12] wire [1:0] packed_deps_lo_hi_30 = {entries_ex_7_bits_deps_ld_3, entries_ex_7_bits_deps_ld_2}; // @[ReservationStation.scala:118:23, :506:12] wire [3:0] packed_deps_lo_45 = {packed_deps_lo_hi_30, packed_deps_lo_lo_30}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_hi_lo_30 = {entries_ex_7_bits_deps_ld_5, entries_ex_7_bits_deps_ld_4}; // @[ReservationStation.scala:118:23, :506:12] wire [1:0] packed_deps_hi_hi_30 = {entries_ex_7_bits_deps_ld_7, entries_ex_7_bits_deps_ld_6}; // @[ReservationStation.scala:118:23, :506:12] wire [3:0] packed_deps_hi_60 = {packed_deps_hi_hi_30, packed_deps_hi_lo_30}; // @[ReservationStation.scala:506:12] wire [7:0] _packed_deps_T_60 = {packed_deps_hi_60, packed_deps_lo_45}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_lo_lo_lo_15 = {entries_ex_7_bits_deps_ex_1, entries_ex_7_bits_deps_ex_0}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_lo_lo_hi_15 = {entries_ex_7_bits_deps_ex_3, entries_ex_7_bits_deps_ex_2}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_lo_lo_31 = {packed_deps_lo_lo_hi_15, packed_deps_lo_lo_lo_15}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_hi_lo_15 = {entries_ex_7_bits_deps_ex_5, entries_ex_7_bits_deps_ex_4}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_lo_hi_hi_15 = {entries_ex_7_bits_deps_ex_7, entries_ex_7_bits_deps_ex_6}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_lo_hi_31 = {packed_deps_lo_hi_hi_15, packed_deps_lo_hi_lo_15}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_lo_46 = {packed_deps_lo_hi_31, packed_deps_lo_lo_31}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_lo_lo_15 = {entries_ex_7_bits_deps_ex_9, entries_ex_7_bits_deps_ex_8}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_hi_lo_hi_15 = {entries_ex_7_bits_deps_ex_11, entries_ex_7_bits_deps_ex_10}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_hi_lo_31 = {packed_deps_hi_lo_hi_15, packed_deps_hi_lo_lo_15}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_hi_lo_15 = {entries_ex_7_bits_deps_ex_13, entries_ex_7_bits_deps_ex_12}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_hi_hi_hi_15 = {entries_ex_7_bits_deps_ex_15, entries_ex_7_bits_deps_ex_14}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_hi_hi_31 = {packed_deps_hi_hi_hi_15, packed_deps_hi_hi_lo_15}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_hi_61 = {packed_deps_hi_hi_31, packed_deps_hi_lo_31}; // @[ReservationStation.scala:506:41] wire [15:0] _packed_deps_T_61 = {packed_deps_hi_61, packed_deps_lo_46}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_47 = {entries_ex_7_bits_deps_st_1, entries_ex_7_bits_deps_st_0}; // @[ReservationStation.scala:118:23, :506:70] wire [1:0] packed_deps_hi_62 = {entries_ex_7_bits_deps_st_3, entries_ex_7_bits_deps_st_2}; // @[ReservationStation.scala:118:23, :506:70] wire [3:0] _packed_deps_T_62 = {packed_deps_hi_62, packed_deps_lo_47}; // @[ReservationStation.scala:506:70] wire [23:0] packed_deps_hi_63 = {_packed_deps_T_60, _packed_deps_T_61}; // @[ReservationStation.scala:506:{8,12,41}] wire [27:0] _packed_deps_T_63 = {packed_deps_hi_63, _packed_deps_T_62}; // @[ReservationStation.scala:506:{8,70}] wire [27:0] packed_deps_15 = _packed_deps_T_63; // @[ReservationStation.scala:505:28, :506:8] wire [1:0] packed_deps_lo_lo_32 = {entries_ex_8_bits_deps_ld_1, entries_ex_8_bits_deps_ld_0}; // @[ReservationStation.scala:118:23, :506:12] wire [1:0] packed_deps_lo_hi_32 = {entries_ex_8_bits_deps_ld_3, entries_ex_8_bits_deps_ld_2}; // @[ReservationStation.scala:118:23, :506:12] wire [3:0] packed_deps_lo_48 = {packed_deps_lo_hi_32, packed_deps_lo_lo_32}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_hi_lo_32 = {entries_ex_8_bits_deps_ld_5, entries_ex_8_bits_deps_ld_4}; // @[ReservationStation.scala:118:23, :506:12] wire [1:0] packed_deps_hi_hi_32 = {entries_ex_8_bits_deps_ld_7, entries_ex_8_bits_deps_ld_6}; // @[ReservationStation.scala:118:23, :506:12] wire [3:0] packed_deps_hi_64 = {packed_deps_hi_hi_32, packed_deps_hi_lo_32}; // @[ReservationStation.scala:506:12] wire [7:0] _packed_deps_T_64 = {packed_deps_hi_64, packed_deps_lo_48}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_lo_lo_lo_16 = {entries_ex_8_bits_deps_ex_1, entries_ex_8_bits_deps_ex_0}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_lo_lo_hi_16 = {entries_ex_8_bits_deps_ex_3, entries_ex_8_bits_deps_ex_2}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_lo_lo_33 = {packed_deps_lo_lo_hi_16, packed_deps_lo_lo_lo_16}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_hi_lo_16 = {entries_ex_8_bits_deps_ex_5, entries_ex_8_bits_deps_ex_4}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_lo_hi_hi_16 = {entries_ex_8_bits_deps_ex_7, entries_ex_8_bits_deps_ex_6}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_lo_hi_33 = {packed_deps_lo_hi_hi_16, packed_deps_lo_hi_lo_16}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_lo_49 = {packed_deps_lo_hi_33, packed_deps_lo_lo_33}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_lo_lo_16 = {entries_ex_8_bits_deps_ex_9, entries_ex_8_bits_deps_ex_8}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_hi_lo_hi_16 = {entries_ex_8_bits_deps_ex_11, entries_ex_8_bits_deps_ex_10}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_hi_lo_33 = {packed_deps_hi_lo_hi_16, packed_deps_hi_lo_lo_16}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_hi_lo_16 = {entries_ex_8_bits_deps_ex_13, entries_ex_8_bits_deps_ex_12}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_hi_hi_hi_16 = {entries_ex_8_bits_deps_ex_15, entries_ex_8_bits_deps_ex_14}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_hi_hi_33 = {packed_deps_hi_hi_hi_16, packed_deps_hi_hi_lo_16}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_hi_65 = {packed_deps_hi_hi_33, packed_deps_hi_lo_33}; // @[ReservationStation.scala:506:41] wire [15:0] _packed_deps_T_65 = {packed_deps_hi_65, packed_deps_lo_49}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_50 = {entries_ex_8_bits_deps_st_1, entries_ex_8_bits_deps_st_0}; // @[ReservationStation.scala:118:23, :506:70] wire [1:0] packed_deps_hi_66 = {entries_ex_8_bits_deps_st_3, entries_ex_8_bits_deps_st_2}; // @[ReservationStation.scala:118:23, :506:70] wire [3:0] _packed_deps_T_66 = {packed_deps_hi_66, packed_deps_lo_50}; // @[ReservationStation.scala:506:70] wire [23:0] packed_deps_hi_67 = {_packed_deps_T_64, _packed_deps_T_65}; // @[ReservationStation.scala:506:{8,12,41}] wire [27:0] _packed_deps_T_67 = {packed_deps_hi_67, _packed_deps_T_66}; // @[ReservationStation.scala:506:{8,70}] wire [27:0] packed_deps_16 = _packed_deps_T_67; // @[ReservationStation.scala:505:28, :506:8] wire [1:0] packed_deps_lo_lo_34 = {entries_ex_9_bits_deps_ld_1, entries_ex_9_bits_deps_ld_0}; // @[ReservationStation.scala:118:23, :506:12] wire [1:0] packed_deps_lo_hi_34 = {entries_ex_9_bits_deps_ld_3, entries_ex_9_bits_deps_ld_2}; // @[ReservationStation.scala:118:23, :506:12] wire [3:0] packed_deps_lo_51 = {packed_deps_lo_hi_34, packed_deps_lo_lo_34}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_hi_lo_34 = {entries_ex_9_bits_deps_ld_5, entries_ex_9_bits_deps_ld_4}; // @[ReservationStation.scala:118:23, :506:12] wire [1:0] packed_deps_hi_hi_34 = {entries_ex_9_bits_deps_ld_7, entries_ex_9_bits_deps_ld_6}; // @[ReservationStation.scala:118:23, :506:12] wire [3:0] packed_deps_hi_68 = {packed_deps_hi_hi_34, packed_deps_hi_lo_34}; // @[ReservationStation.scala:506:12] wire [7:0] _packed_deps_T_68 = {packed_deps_hi_68, packed_deps_lo_51}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_lo_lo_lo_17 = {entries_ex_9_bits_deps_ex_1, entries_ex_9_bits_deps_ex_0}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_lo_lo_hi_17 = {entries_ex_9_bits_deps_ex_3, entries_ex_9_bits_deps_ex_2}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_lo_lo_35 = {packed_deps_lo_lo_hi_17, packed_deps_lo_lo_lo_17}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_hi_lo_17 = {entries_ex_9_bits_deps_ex_5, entries_ex_9_bits_deps_ex_4}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_lo_hi_hi_17 = {entries_ex_9_bits_deps_ex_7, entries_ex_9_bits_deps_ex_6}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_lo_hi_35 = {packed_deps_lo_hi_hi_17, packed_deps_lo_hi_lo_17}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_lo_52 = {packed_deps_lo_hi_35, packed_deps_lo_lo_35}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_lo_lo_17 = {entries_ex_9_bits_deps_ex_9, entries_ex_9_bits_deps_ex_8}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_hi_lo_hi_17 = {entries_ex_9_bits_deps_ex_11, entries_ex_9_bits_deps_ex_10}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_hi_lo_35 = {packed_deps_hi_lo_hi_17, packed_deps_hi_lo_lo_17}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_hi_lo_17 = {entries_ex_9_bits_deps_ex_13, entries_ex_9_bits_deps_ex_12}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_hi_hi_hi_17 = {entries_ex_9_bits_deps_ex_15, entries_ex_9_bits_deps_ex_14}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_hi_hi_35 = {packed_deps_hi_hi_hi_17, packed_deps_hi_hi_lo_17}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_hi_69 = {packed_deps_hi_hi_35, packed_deps_hi_lo_35}; // @[ReservationStation.scala:506:41] wire [15:0] _packed_deps_T_69 = {packed_deps_hi_69, packed_deps_lo_52}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_53 = {entries_ex_9_bits_deps_st_1, entries_ex_9_bits_deps_st_0}; // @[ReservationStation.scala:118:23, :506:70] wire [1:0] packed_deps_hi_70 = {entries_ex_9_bits_deps_st_3, entries_ex_9_bits_deps_st_2}; // @[ReservationStation.scala:118:23, :506:70] wire [3:0] _packed_deps_T_70 = {packed_deps_hi_70, packed_deps_lo_53}; // @[ReservationStation.scala:506:70] wire [23:0] packed_deps_hi_71 = {_packed_deps_T_68, _packed_deps_T_69}; // @[ReservationStation.scala:506:{8,12,41}] wire [27:0] _packed_deps_T_71 = {packed_deps_hi_71, _packed_deps_T_70}; // @[ReservationStation.scala:506:{8,70}] wire [27:0] packed_deps_17 = _packed_deps_T_71; // @[ReservationStation.scala:505:28, :506:8] wire [1:0] packed_deps_lo_lo_36 = {entries_ex_10_bits_deps_ld_1, entries_ex_10_bits_deps_ld_0}; // @[ReservationStation.scala:118:23, :506:12] wire [1:0] packed_deps_lo_hi_36 = {entries_ex_10_bits_deps_ld_3, entries_ex_10_bits_deps_ld_2}; // @[ReservationStation.scala:118:23, :506:12] wire [3:0] packed_deps_lo_54 = {packed_deps_lo_hi_36, packed_deps_lo_lo_36}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_hi_lo_36 = {entries_ex_10_bits_deps_ld_5, entries_ex_10_bits_deps_ld_4}; // @[ReservationStation.scala:118:23, :506:12] wire [1:0] packed_deps_hi_hi_36 = {entries_ex_10_bits_deps_ld_7, entries_ex_10_bits_deps_ld_6}; // @[ReservationStation.scala:118:23, :506:12] wire [3:0] packed_deps_hi_72 = {packed_deps_hi_hi_36, packed_deps_hi_lo_36}; // @[ReservationStation.scala:506:12] wire [7:0] _packed_deps_T_72 = {packed_deps_hi_72, packed_deps_lo_54}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_lo_lo_lo_18 = {entries_ex_10_bits_deps_ex_1, entries_ex_10_bits_deps_ex_0}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_lo_lo_hi_18 = {entries_ex_10_bits_deps_ex_3, entries_ex_10_bits_deps_ex_2}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_lo_lo_37 = {packed_deps_lo_lo_hi_18, packed_deps_lo_lo_lo_18}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_hi_lo_18 = {entries_ex_10_bits_deps_ex_5, entries_ex_10_bits_deps_ex_4}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_lo_hi_hi_18 = {entries_ex_10_bits_deps_ex_7, entries_ex_10_bits_deps_ex_6}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_lo_hi_37 = {packed_deps_lo_hi_hi_18, packed_deps_lo_hi_lo_18}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_lo_55 = {packed_deps_lo_hi_37, packed_deps_lo_lo_37}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_lo_lo_18 = {entries_ex_10_bits_deps_ex_9, entries_ex_10_bits_deps_ex_8}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_hi_lo_hi_18 = {entries_ex_10_bits_deps_ex_11, entries_ex_10_bits_deps_ex_10}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_hi_lo_37 = {packed_deps_hi_lo_hi_18, packed_deps_hi_lo_lo_18}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_hi_lo_18 = {entries_ex_10_bits_deps_ex_13, entries_ex_10_bits_deps_ex_12}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_hi_hi_hi_18 = {entries_ex_10_bits_deps_ex_15, entries_ex_10_bits_deps_ex_14}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_hi_hi_37 = {packed_deps_hi_hi_hi_18, packed_deps_hi_hi_lo_18}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_hi_73 = {packed_deps_hi_hi_37, packed_deps_hi_lo_37}; // @[ReservationStation.scala:506:41] wire [15:0] _packed_deps_T_73 = {packed_deps_hi_73, packed_deps_lo_55}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_56 = {entries_ex_10_bits_deps_st_1, entries_ex_10_bits_deps_st_0}; // @[ReservationStation.scala:118:23, :506:70] wire [1:0] packed_deps_hi_74 = {entries_ex_10_bits_deps_st_3, entries_ex_10_bits_deps_st_2}; // @[ReservationStation.scala:118:23, :506:70] wire [3:0] _packed_deps_T_74 = {packed_deps_hi_74, packed_deps_lo_56}; // @[ReservationStation.scala:506:70] wire [23:0] packed_deps_hi_75 = {_packed_deps_T_72, _packed_deps_T_73}; // @[ReservationStation.scala:506:{8,12,41}] wire [27:0] _packed_deps_T_75 = {packed_deps_hi_75, _packed_deps_T_74}; // @[ReservationStation.scala:506:{8,70}] wire [27:0] packed_deps_18 = _packed_deps_T_75; // @[ReservationStation.scala:505:28, :506:8] wire [1:0] packed_deps_lo_lo_38 = {entries_ex_11_bits_deps_ld_1, entries_ex_11_bits_deps_ld_0}; // @[ReservationStation.scala:118:23, :506:12] wire [1:0] packed_deps_lo_hi_38 = {entries_ex_11_bits_deps_ld_3, entries_ex_11_bits_deps_ld_2}; // @[ReservationStation.scala:118:23, :506:12] wire [3:0] packed_deps_lo_57 = {packed_deps_lo_hi_38, packed_deps_lo_lo_38}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_hi_lo_38 = {entries_ex_11_bits_deps_ld_5, entries_ex_11_bits_deps_ld_4}; // @[ReservationStation.scala:118:23, :506:12] wire [1:0] packed_deps_hi_hi_38 = {entries_ex_11_bits_deps_ld_7, entries_ex_11_bits_deps_ld_6}; // @[ReservationStation.scala:118:23, :506:12] wire [3:0] packed_deps_hi_76 = {packed_deps_hi_hi_38, packed_deps_hi_lo_38}; // @[ReservationStation.scala:506:12] wire [7:0] _packed_deps_T_76 = {packed_deps_hi_76, packed_deps_lo_57}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_lo_lo_lo_19 = {entries_ex_11_bits_deps_ex_1, entries_ex_11_bits_deps_ex_0}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_lo_lo_hi_19 = {entries_ex_11_bits_deps_ex_3, entries_ex_11_bits_deps_ex_2}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_lo_lo_39 = {packed_deps_lo_lo_hi_19, packed_deps_lo_lo_lo_19}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_hi_lo_19 = {entries_ex_11_bits_deps_ex_5, entries_ex_11_bits_deps_ex_4}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_lo_hi_hi_19 = {entries_ex_11_bits_deps_ex_7, entries_ex_11_bits_deps_ex_6}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_lo_hi_39 = {packed_deps_lo_hi_hi_19, packed_deps_lo_hi_lo_19}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_lo_58 = {packed_deps_lo_hi_39, packed_deps_lo_lo_39}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_lo_lo_19 = {entries_ex_11_bits_deps_ex_9, entries_ex_11_bits_deps_ex_8}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_hi_lo_hi_19 = {entries_ex_11_bits_deps_ex_11, entries_ex_11_bits_deps_ex_10}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_hi_lo_39 = {packed_deps_hi_lo_hi_19, packed_deps_hi_lo_lo_19}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_hi_lo_19 = {entries_ex_11_bits_deps_ex_13, entries_ex_11_bits_deps_ex_12}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_hi_hi_hi_19 = {entries_ex_11_bits_deps_ex_15, entries_ex_11_bits_deps_ex_14}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_hi_hi_39 = {packed_deps_hi_hi_hi_19, packed_deps_hi_hi_lo_19}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_hi_77 = {packed_deps_hi_hi_39, packed_deps_hi_lo_39}; // @[ReservationStation.scala:506:41] wire [15:0] _packed_deps_T_77 = {packed_deps_hi_77, packed_deps_lo_58}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_59 = {entries_ex_11_bits_deps_st_1, entries_ex_11_bits_deps_st_0}; // @[ReservationStation.scala:118:23, :506:70] wire [1:0] packed_deps_hi_78 = {entries_ex_11_bits_deps_st_3, entries_ex_11_bits_deps_st_2}; // @[ReservationStation.scala:118:23, :506:70] wire [3:0] _packed_deps_T_78 = {packed_deps_hi_78, packed_deps_lo_59}; // @[ReservationStation.scala:506:70] wire [23:0] packed_deps_hi_79 = {_packed_deps_T_76, _packed_deps_T_77}; // @[ReservationStation.scala:506:{8,12,41}] wire [27:0] _packed_deps_T_79 = {packed_deps_hi_79, _packed_deps_T_78}; // @[ReservationStation.scala:506:{8,70}] wire [27:0] packed_deps_19 = _packed_deps_T_79; // @[ReservationStation.scala:505:28, :506:8] wire [1:0] packed_deps_lo_lo_40 = {entries_ex_12_bits_deps_ld_1, entries_ex_12_bits_deps_ld_0}; // @[ReservationStation.scala:118:23, :506:12] wire [1:0] packed_deps_lo_hi_40 = {entries_ex_12_bits_deps_ld_3, entries_ex_12_bits_deps_ld_2}; // @[ReservationStation.scala:118:23, :506:12] wire [3:0] packed_deps_lo_60 = {packed_deps_lo_hi_40, packed_deps_lo_lo_40}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_hi_lo_40 = {entries_ex_12_bits_deps_ld_5, entries_ex_12_bits_deps_ld_4}; // @[ReservationStation.scala:118:23, :506:12] wire [1:0] packed_deps_hi_hi_40 = {entries_ex_12_bits_deps_ld_7, entries_ex_12_bits_deps_ld_6}; // @[ReservationStation.scala:118:23, :506:12] wire [3:0] packed_deps_hi_80 = {packed_deps_hi_hi_40, packed_deps_hi_lo_40}; // @[ReservationStation.scala:506:12] wire [7:0] _packed_deps_T_80 = {packed_deps_hi_80, packed_deps_lo_60}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_lo_lo_lo_20 = {entries_ex_12_bits_deps_ex_1, entries_ex_12_bits_deps_ex_0}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_lo_lo_hi_20 = {entries_ex_12_bits_deps_ex_3, entries_ex_12_bits_deps_ex_2}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_lo_lo_41 = {packed_deps_lo_lo_hi_20, packed_deps_lo_lo_lo_20}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_hi_lo_20 = {entries_ex_12_bits_deps_ex_5, entries_ex_12_bits_deps_ex_4}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_lo_hi_hi_20 = {entries_ex_12_bits_deps_ex_7, entries_ex_12_bits_deps_ex_6}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_lo_hi_41 = {packed_deps_lo_hi_hi_20, packed_deps_lo_hi_lo_20}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_lo_61 = {packed_deps_lo_hi_41, packed_deps_lo_lo_41}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_lo_lo_20 = {entries_ex_12_bits_deps_ex_9, entries_ex_12_bits_deps_ex_8}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_hi_lo_hi_20 = {entries_ex_12_bits_deps_ex_11, entries_ex_12_bits_deps_ex_10}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_hi_lo_41 = {packed_deps_hi_lo_hi_20, packed_deps_hi_lo_lo_20}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_hi_lo_20 = {entries_ex_12_bits_deps_ex_13, entries_ex_12_bits_deps_ex_12}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_hi_hi_hi_20 = {entries_ex_12_bits_deps_ex_15, entries_ex_12_bits_deps_ex_14}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_hi_hi_41 = {packed_deps_hi_hi_hi_20, packed_deps_hi_hi_lo_20}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_hi_81 = {packed_deps_hi_hi_41, packed_deps_hi_lo_41}; // @[ReservationStation.scala:506:41] wire [15:0] _packed_deps_T_81 = {packed_deps_hi_81, packed_deps_lo_61}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_62 = {entries_ex_12_bits_deps_st_1, entries_ex_12_bits_deps_st_0}; // @[ReservationStation.scala:118:23, :506:70] wire [1:0] packed_deps_hi_82 = {entries_ex_12_bits_deps_st_3, entries_ex_12_bits_deps_st_2}; // @[ReservationStation.scala:118:23, :506:70] wire [3:0] _packed_deps_T_82 = {packed_deps_hi_82, packed_deps_lo_62}; // @[ReservationStation.scala:506:70] wire [23:0] packed_deps_hi_83 = {_packed_deps_T_80, _packed_deps_T_81}; // @[ReservationStation.scala:506:{8,12,41}] wire [27:0] _packed_deps_T_83 = {packed_deps_hi_83, _packed_deps_T_82}; // @[ReservationStation.scala:506:{8,70}] wire [27:0] packed_deps_20 = _packed_deps_T_83; // @[ReservationStation.scala:505:28, :506:8] wire [1:0] packed_deps_lo_lo_42 = {entries_ex_13_bits_deps_ld_1, entries_ex_13_bits_deps_ld_0}; // @[ReservationStation.scala:118:23, :506:12] wire [1:0] packed_deps_lo_hi_42 = {entries_ex_13_bits_deps_ld_3, entries_ex_13_bits_deps_ld_2}; // @[ReservationStation.scala:118:23, :506:12] wire [3:0] packed_deps_lo_63 = {packed_deps_lo_hi_42, packed_deps_lo_lo_42}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_hi_lo_42 = {entries_ex_13_bits_deps_ld_5, entries_ex_13_bits_deps_ld_4}; // @[ReservationStation.scala:118:23, :506:12] wire [1:0] packed_deps_hi_hi_42 = {entries_ex_13_bits_deps_ld_7, entries_ex_13_bits_deps_ld_6}; // @[ReservationStation.scala:118:23, :506:12] wire [3:0] packed_deps_hi_84 = {packed_deps_hi_hi_42, packed_deps_hi_lo_42}; // @[ReservationStation.scala:506:12] wire [7:0] _packed_deps_T_84 = {packed_deps_hi_84, packed_deps_lo_63}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_lo_lo_lo_21 = {entries_ex_13_bits_deps_ex_1, entries_ex_13_bits_deps_ex_0}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_lo_lo_hi_21 = {entries_ex_13_bits_deps_ex_3, entries_ex_13_bits_deps_ex_2}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_lo_lo_43 = {packed_deps_lo_lo_hi_21, packed_deps_lo_lo_lo_21}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_hi_lo_21 = {entries_ex_13_bits_deps_ex_5, entries_ex_13_bits_deps_ex_4}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_lo_hi_hi_21 = {entries_ex_13_bits_deps_ex_7, entries_ex_13_bits_deps_ex_6}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_lo_hi_43 = {packed_deps_lo_hi_hi_21, packed_deps_lo_hi_lo_21}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_lo_64 = {packed_deps_lo_hi_43, packed_deps_lo_lo_43}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_lo_lo_21 = {entries_ex_13_bits_deps_ex_9, entries_ex_13_bits_deps_ex_8}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_hi_lo_hi_21 = {entries_ex_13_bits_deps_ex_11, entries_ex_13_bits_deps_ex_10}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_hi_lo_43 = {packed_deps_hi_lo_hi_21, packed_deps_hi_lo_lo_21}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_hi_lo_21 = {entries_ex_13_bits_deps_ex_13, entries_ex_13_bits_deps_ex_12}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_hi_hi_hi_21 = {entries_ex_13_bits_deps_ex_15, entries_ex_13_bits_deps_ex_14}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_hi_hi_43 = {packed_deps_hi_hi_hi_21, packed_deps_hi_hi_lo_21}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_hi_85 = {packed_deps_hi_hi_43, packed_deps_hi_lo_43}; // @[ReservationStation.scala:506:41] wire [15:0] _packed_deps_T_85 = {packed_deps_hi_85, packed_deps_lo_64}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_65 = {entries_ex_13_bits_deps_st_1, entries_ex_13_bits_deps_st_0}; // @[ReservationStation.scala:118:23, :506:70] wire [1:0] packed_deps_hi_86 = {entries_ex_13_bits_deps_st_3, entries_ex_13_bits_deps_st_2}; // @[ReservationStation.scala:118:23, :506:70] wire [3:0] _packed_deps_T_86 = {packed_deps_hi_86, packed_deps_lo_65}; // @[ReservationStation.scala:506:70] wire [23:0] packed_deps_hi_87 = {_packed_deps_T_84, _packed_deps_T_85}; // @[ReservationStation.scala:506:{8,12,41}] wire [27:0] _packed_deps_T_87 = {packed_deps_hi_87, _packed_deps_T_86}; // @[ReservationStation.scala:506:{8,70}] wire [27:0] packed_deps_21 = _packed_deps_T_87; // @[ReservationStation.scala:505:28, :506:8] wire [1:0] packed_deps_lo_lo_44 = {entries_ex_14_bits_deps_ld_1, entries_ex_14_bits_deps_ld_0}; // @[ReservationStation.scala:118:23, :506:12] wire [1:0] packed_deps_lo_hi_44 = {entries_ex_14_bits_deps_ld_3, entries_ex_14_bits_deps_ld_2}; // @[ReservationStation.scala:118:23, :506:12] wire [3:0] packed_deps_lo_66 = {packed_deps_lo_hi_44, packed_deps_lo_lo_44}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_hi_lo_44 = {entries_ex_14_bits_deps_ld_5, entries_ex_14_bits_deps_ld_4}; // @[ReservationStation.scala:118:23, :506:12] wire [1:0] packed_deps_hi_hi_44 = {entries_ex_14_bits_deps_ld_7, entries_ex_14_bits_deps_ld_6}; // @[ReservationStation.scala:118:23, :506:12] wire [3:0] packed_deps_hi_88 = {packed_deps_hi_hi_44, packed_deps_hi_lo_44}; // @[ReservationStation.scala:506:12] wire [7:0] _packed_deps_T_88 = {packed_deps_hi_88, packed_deps_lo_66}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_lo_lo_lo_22 = {entries_ex_14_bits_deps_ex_1, entries_ex_14_bits_deps_ex_0}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_lo_lo_hi_22 = {entries_ex_14_bits_deps_ex_3, entries_ex_14_bits_deps_ex_2}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_lo_lo_45 = {packed_deps_lo_lo_hi_22, packed_deps_lo_lo_lo_22}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_hi_lo_22 = {entries_ex_14_bits_deps_ex_5, entries_ex_14_bits_deps_ex_4}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_lo_hi_hi_22 = {entries_ex_14_bits_deps_ex_7, entries_ex_14_bits_deps_ex_6}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_lo_hi_45 = {packed_deps_lo_hi_hi_22, packed_deps_lo_hi_lo_22}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_lo_67 = {packed_deps_lo_hi_45, packed_deps_lo_lo_45}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_lo_lo_22 = {entries_ex_14_bits_deps_ex_9, entries_ex_14_bits_deps_ex_8}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_hi_lo_hi_22 = {entries_ex_14_bits_deps_ex_11, entries_ex_14_bits_deps_ex_10}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_hi_lo_45 = {packed_deps_hi_lo_hi_22, packed_deps_hi_lo_lo_22}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_hi_lo_22 = {entries_ex_14_bits_deps_ex_13, entries_ex_14_bits_deps_ex_12}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_hi_hi_hi_22 = {entries_ex_14_bits_deps_ex_15, entries_ex_14_bits_deps_ex_14}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_hi_hi_45 = {packed_deps_hi_hi_hi_22, packed_deps_hi_hi_lo_22}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_hi_89 = {packed_deps_hi_hi_45, packed_deps_hi_lo_45}; // @[ReservationStation.scala:506:41] wire [15:0] _packed_deps_T_89 = {packed_deps_hi_89, packed_deps_lo_67}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_68 = {entries_ex_14_bits_deps_st_1, entries_ex_14_bits_deps_st_0}; // @[ReservationStation.scala:118:23, :506:70] wire [1:0] packed_deps_hi_90 = {entries_ex_14_bits_deps_st_3, entries_ex_14_bits_deps_st_2}; // @[ReservationStation.scala:118:23, :506:70] wire [3:0] _packed_deps_T_90 = {packed_deps_hi_90, packed_deps_lo_68}; // @[ReservationStation.scala:506:70] wire [23:0] packed_deps_hi_91 = {_packed_deps_T_88, _packed_deps_T_89}; // @[ReservationStation.scala:506:{8,12,41}] wire [27:0] _packed_deps_T_91 = {packed_deps_hi_91, _packed_deps_T_90}; // @[ReservationStation.scala:506:{8,70}] wire [27:0] packed_deps_22 = _packed_deps_T_91; // @[ReservationStation.scala:505:28, :506:8] wire [1:0] packed_deps_lo_lo_46 = {entries_ex_15_bits_deps_ld_1, entries_ex_15_bits_deps_ld_0}; // @[ReservationStation.scala:118:23, :506:12] wire [1:0] packed_deps_lo_hi_46 = {entries_ex_15_bits_deps_ld_3, entries_ex_15_bits_deps_ld_2}; // @[ReservationStation.scala:118:23, :506:12] wire [3:0] packed_deps_lo_69 = {packed_deps_lo_hi_46, packed_deps_lo_lo_46}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_hi_lo_46 = {entries_ex_15_bits_deps_ld_5, entries_ex_15_bits_deps_ld_4}; // @[ReservationStation.scala:118:23, :506:12] wire [1:0] packed_deps_hi_hi_46 = {entries_ex_15_bits_deps_ld_7, entries_ex_15_bits_deps_ld_6}; // @[ReservationStation.scala:118:23, :506:12] wire [3:0] packed_deps_hi_92 = {packed_deps_hi_hi_46, packed_deps_hi_lo_46}; // @[ReservationStation.scala:506:12] wire [7:0] _packed_deps_T_92 = {packed_deps_hi_92, packed_deps_lo_69}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_lo_lo_lo_23 = {entries_ex_15_bits_deps_ex_1, entries_ex_15_bits_deps_ex_0}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_lo_lo_hi_23 = {entries_ex_15_bits_deps_ex_3, entries_ex_15_bits_deps_ex_2}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_lo_lo_47 = {packed_deps_lo_lo_hi_23, packed_deps_lo_lo_lo_23}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_hi_lo_23 = {entries_ex_15_bits_deps_ex_5, entries_ex_15_bits_deps_ex_4}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_lo_hi_hi_23 = {entries_ex_15_bits_deps_ex_7, entries_ex_15_bits_deps_ex_6}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_lo_hi_47 = {packed_deps_lo_hi_hi_23, packed_deps_lo_hi_lo_23}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_lo_70 = {packed_deps_lo_hi_47, packed_deps_lo_lo_47}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_lo_lo_23 = {entries_ex_15_bits_deps_ex_9, entries_ex_15_bits_deps_ex_8}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_hi_lo_hi_23 = {entries_ex_15_bits_deps_ex_11, entries_ex_15_bits_deps_ex_10}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_hi_lo_47 = {packed_deps_hi_lo_hi_23, packed_deps_hi_lo_lo_23}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_hi_lo_23 = {entries_ex_15_bits_deps_ex_13, entries_ex_15_bits_deps_ex_12}; // @[ReservationStation.scala:118:23, :506:41] wire [1:0] packed_deps_hi_hi_hi_23 = {entries_ex_15_bits_deps_ex_15, entries_ex_15_bits_deps_ex_14}; // @[ReservationStation.scala:118:23, :506:41] wire [3:0] packed_deps_hi_hi_47 = {packed_deps_hi_hi_hi_23, packed_deps_hi_hi_lo_23}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_hi_93 = {packed_deps_hi_hi_47, packed_deps_hi_lo_47}; // @[ReservationStation.scala:506:41] wire [15:0] _packed_deps_T_93 = {packed_deps_hi_93, packed_deps_lo_70}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_71 = {entries_ex_15_bits_deps_st_1, entries_ex_15_bits_deps_st_0}; // @[ReservationStation.scala:118:23, :506:70] wire [1:0] packed_deps_hi_94 = {entries_ex_15_bits_deps_st_3, entries_ex_15_bits_deps_st_2}; // @[ReservationStation.scala:118:23, :506:70] wire [3:0] _packed_deps_T_94 = {packed_deps_hi_94, packed_deps_lo_71}; // @[ReservationStation.scala:506:70] wire [23:0] packed_deps_hi_95 = {_packed_deps_T_92, _packed_deps_T_93}; // @[ReservationStation.scala:506:{8,12,41}] wire [27:0] _packed_deps_T_95 = {packed_deps_hi_95, _packed_deps_T_94}; // @[ReservationStation.scala:506:{8,70}] wire [27:0] packed_deps_23 = _packed_deps_T_95; // @[ReservationStation.scala:505:28, :506:8] wire [1:0] packed_deps_lo_lo_48 = {entries_st_0_bits_deps_ld_1, entries_st_0_bits_deps_ld_0}; // @[ReservationStation.scala:119:23, :506:12] wire [1:0] packed_deps_lo_hi_48 = {entries_st_0_bits_deps_ld_3, entries_st_0_bits_deps_ld_2}; // @[ReservationStation.scala:119:23, :506:12] wire [3:0] packed_deps_lo_72 = {packed_deps_lo_hi_48, packed_deps_lo_lo_48}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_hi_lo_48 = {entries_st_0_bits_deps_ld_5, entries_st_0_bits_deps_ld_4}; // @[ReservationStation.scala:119:23, :506:12] wire [1:0] packed_deps_hi_hi_48 = {entries_st_0_bits_deps_ld_7, entries_st_0_bits_deps_ld_6}; // @[ReservationStation.scala:119:23, :506:12] wire [3:0] packed_deps_hi_96 = {packed_deps_hi_hi_48, packed_deps_hi_lo_48}; // @[ReservationStation.scala:506:12] wire [7:0] _packed_deps_T_96 = {packed_deps_hi_96, packed_deps_lo_72}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_lo_lo_lo_24 = {entries_st_0_bits_deps_ex_1, entries_st_0_bits_deps_ex_0}; // @[ReservationStation.scala:119:23, :506:41] wire [1:0] packed_deps_lo_lo_hi_24 = {entries_st_0_bits_deps_ex_3, entries_st_0_bits_deps_ex_2}; // @[ReservationStation.scala:119:23, :506:41] wire [3:0] packed_deps_lo_lo_49 = {packed_deps_lo_lo_hi_24, packed_deps_lo_lo_lo_24}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_hi_lo_24 = {entries_st_0_bits_deps_ex_5, entries_st_0_bits_deps_ex_4}; // @[ReservationStation.scala:119:23, :506:41] wire [1:0] packed_deps_lo_hi_hi_24 = {entries_st_0_bits_deps_ex_7, entries_st_0_bits_deps_ex_6}; // @[ReservationStation.scala:119:23, :506:41] wire [3:0] packed_deps_lo_hi_49 = {packed_deps_lo_hi_hi_24, packed_deps_lo_hi_lo_24}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_lo_73 = {packed_deps_lo_hi_49, packed_deps_lo_lo_49}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_lo_lo_24 = {entries_st_0_bits_deps_ex_9, entries_st_0_bits_deps_ex_8}; // @[ReservationStation.scala:119:23, :506:41] wire [1:0] packed_deps_hi_lo_hi_24 = {entries_st_0_bits_deps_ex_11, entries_st_0_bits_deps_ex_10}; // @[ReservationStation.scala:119:23, :506:41] wire [3:0] packed_deps_hi_lo_49 = {packed_deps_hi_lo_hi_24, packed_deps_hi_lo_lo_24}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_hi_lo_24 = {entries_st_0_bits_deps_ex_13, entries_st_0_bits_deps_ex_12}; // @[ReservationStation.scala:119:23, :506:41] wire [1:0] packed_deps_hi_hi_hi_24 = {entries_st_0_bits_deps_ex_15, entries_st_0_bits_deps_ex_14}; // @[ReservationStation.scala:119:23, :506:41] wire [3:0] packed_deps_hi_hi_49 = {packed_deps_hi_hi_hi_24, packed_deps_hi_hi_lo_24}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_hi_97 = {packed_deps_hi_hi_49, packed_deps_hi_lo_49}; // @[ReservationStation.scala:506:41] wire [15:0] _packed_deps_T_97 = {packed_deps_hi_97, packed_deps_lo_73}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_74 = {entries_st_0_bits_deps_st_1, entries_st_0_bits_deps_st_0}; // @[ReservationStation.scala:119:23, :506:70] wire [1:0] packed_deps_hi_98 = {entries_st_0_bits_deps_st_3, entries_st_0_bits_deps_st_2}; // @[ReservationStation.scala:119:23, :506:70] wire [3:0] _packed_deps_T_98 = {packed_deps_hi_98, packed_deps_lo_74}; // @[ReservationStation.scala:506:70] wire [23:0] packed_deps_hi_99 = {_packed_deps_T_96, _packed_deps_T_97}; // @[ReservationStation.scala:506:{8,12,41}] wire [27:0] _packed_deps_T_99 = {packed_deps_hi_99, _packed_deps_T_98}; // @[ReservationStation.scala:506:{8,70}] wire [27:0] packed_deps_24 = _packed_deps_T_99; // @[ReservationStation.scala:505:28, :506:8] wire [1:0] packed_deps_lo_lo_50 = {entries_st_1_bits_deps_ld_1, entries_st_1_bits_deps_ld_0}; // @[ReservationStation.scala:119:23, :506:12] wire [1:0] packed_deps_lo_hi_50 = {entries_st_1_bits_deps_ld_3, entries_st_1_bits_deps_ld_2}; // @[ReservationStation.scala:119:23, :506:12] wire [3:0] packed_deps_lo_75 = {packed_deps_lo_hi_50, packed_deps_lo_lo_50}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_hi_lo_50 = {entries_st_1_bits_deps_ld_5, entries_st_1_bits_deps_ld_4}; // @[ReservationStation.scala:119:23, :506:12] wire [1:0] packed_deps_hi_hi_50 = {entries_st_1_bits_deps_ld_7, entries_st_1_bits_deps_ld_6}; // @[ReservationStation.scala:119:23, :506:12] wire [3:0] packed_deps_hi_100 = {packed_deps_hi_hi_50, packed_deps_hi_lo_50}; // @[ReservationStation.scala:506:12] wire [7:0] _packed_deps_T_100 = {packed_deps_hi_100, packed_deps_lo_75}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_lo_lo_lo_25 = {entries_st_1_bits_deps_ex_1, entries_st_1_bits_deps_ex_0}; // @[ReservationStation.scala:119:23, :506:41] wire [1:0] packed_deps_lo_lo_hi_25 = {entries_st_1_bits_deps_ex_3, entries_st_1_bits_deps_ex_2}; // @[ReservationStation.scala:119:23, :506:41] wire [3:0] packed_deps_lo_lo_51 = {packed_deps_lo_lo_hi_25, packed_deps_lo_lo_lo_25}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_hi_lo_25 = {entries_st_1_bits_deps_ex_5, entries_st_1_bits_deps_ex_4}; // @[ReservationStation.scala:119:23, :506:41] wire [1:0] packed_deps_lo_hi_hi_25 = {entries_st_1_bits_deps_ex_7, entries_st_1_bits_deps_ex_6}; // @[ReservationStation.scala:119:23, :506:41] wire [3:0] packed_deps_lo_hi_51 = {packed_deps_lo_hi_hi_25, packed_deps_lo_hi_lo_25}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_lo_76 = {packed_deps_lo_hi_51, packed_deps_lo_lo_51}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_lo_lo_25 = {entries_st_1_bits_deps_ex_9, entries_st_1_bits_deps_ex_8}; // @[ReservationStation.scala:119:23, :506:41] wire [1:0] packed_deps_hi_lo_hi_25 = {entries_st_1_bits_deps_ex_11, entries_st_1_bits_deps_ex_10}; // @[ReservationStation.scala:119:23, :506:41] wire [3:0] packed_deps_hi_lo_51 = {packed_deps_hi_lo_hi_25, packed_deps_hi_lo_lo_25}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_hi_lo_25 = {entries_st_1_bits_deps_ex_13, entries_st_1_bits_deps_ex_12}; // @[ReservationStation.scala:119:23, :506:41] wire [1:0] packed_deps_hi_hi_hi_25 = {entries_st_1_bits_deps_ex_15, entries_st_1_bits_deps_ex_14}; // @[ReservationStation.scala:119:23, :506:41] wire [3:0] packed_deps_hi_hi_51 = {packed_deps_hi_hi_hi_25, packed_deps_hi_hi_lo_25}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_hi_101 = {packed_deps_hi_hi_51, packed_deps_hi_lo_51}; // @[ReservationStation.scala:506:41] wire [15:0] _packed_deps_T_101 = {packed_deps_hi_101, packed_deps_lo_76}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_77 = {entries_st_1_bits_deps_st_1, entries_st_1_bits_deps_st_0}; // @[ReservationStation.scala:119:23, :506:70] wire [1:0] packed_deps_hi_102 = {entries_st_1_bits_deps_st_3, entries_st_1_bits_deps_st_2}; // @[ReservationStation.scala:119:23, :506:70] wire [3:0] _packed_deps_T_102 = {packed_deps_hi_102, packed_deps_lo_77}; // @[ReservationStation.scala:506:70] wire [23:0] packed_deps_hi_103 = {_packed_deps_T_100, _packed_deps_T_101}; // @[ReservationStation.scala:506:{8,12,41}] wire [27:0] _packed_deps_T_103 = {packed_deps_hi_103, _packed_deps_T_102}; // @[ReservationStation.scala:506:{8,70}] wire [27:0] packed_deps_25 = _packed_deps_T_103; // @[ReservationStation.scala:505:28, :506:8] wire [1:0] packed_deps_lo_lo_52 = {entries_st_2_bits_deps_ld_1, entries_st_2_bits_deps_ld_0}; // @[ReservationStation.scala:119:23, :506:12] wire [1:0] packed_deps_lo_hi_52 = {entries_st_2_bits_deps_ld_3, entries_st_2_bits_deps_ld_2}; // @[ReservationStation.scala:119:23, :506:12] wire [3:0] packed_deps_lo_78 = {packed_deps_lo_hi_52, packed_deps_lo_lo_52}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_hi_lo_52 = {entries_st_2_bits_deps_ld_5, entries_st_2_bits_deps_ld_4}; // @[ReservationStation.scala:119:23, :506:12] wire [1:0] packed_deps_hi_hi_52 = {entries_st_2_bits_deps_ld_7, entries_st_2_bits_deps_ld_6}; // @[ReservationStation.scala:119:23, :506:12] wire [3:0] packed_deps_hi_104 = {packed_deps_hi_hi_52, packed_deps_hi_lo_52}; // @[ReservationStation.scala:506:12] wire [7:0] _packed_deps_T_104 = {packed_deps_hi_104, packed_deps_lo_78}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_lo_lo_lo_26 = {entries_st_2_bits_deps_ex_1, entries_st_2_bits_deps_ex_0}; // @[ReservationStation.scala:119:23, :506:41] wire [1:0] packed_deps_lo_lo_hi_26 = {entries_st_2_bits_deps_ex_3, entries_st_2_bits_deps_ex_2}; // @[ReservationStation.scala:119:23, :506:41] wire [3:0] packed_deps_lo_lo_53 = {packed_deps_lo_lo_hi_26, packed_deps_lo_lo_lo_26}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_hi_lo_26 = {entries_st_2_bits_deps_ex_5, entries_st_2_bits_deps_ex_4}; // @[ReservationStation.scala:119:23, :506:41] wire [1:0] packed_deps_lo_hi_hi_26 = {entries_st_2_bits_deps_ex_7, entries_st_2_bits_deps_ex_6}; // @[ReservationStation.scala:119:23, :506:41] wire [3:0] packed_deps_lo_hi_53 = {packed_deps_lo_hi_hi_26, packed_deps_lo_hi_lo_26}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_lo_79 = {packed_deps_lo_hi_53, packed_deps_lo_lo_53}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_lo_lo_26 = {entries_st_2_bits_deps_ex_9, entries_st_2_bits_deps_ex_8}; // @[ReservationStation.scala:119:23, :506:41] wire [1:0] packed_deps_hi_lo_hi_26 = {entries_st_2_bits_deps_ex_11, entries_st_2_bits_deps_ex_10}; // @[ReservationStation.scala:119:23, :506:41] wire [3:0] packed_deps_hi_lo_53 = {packed_deps_hi_lo_hi_26, packed_deps_hi_lo_lo_26}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_hi_lo_26 = {entries_st_2_bits_deps_ex_13, entries_st_2_bits_deps_ex_12}; // @[ReservationStation.scala:119:23, :506:41] wire [1:0] packed_deps_hi_hi_hi_26 = {entries_st_2_bits_deps_ex_15, entries_st_2_bits_deps_ex_14}; // @[ReservationStation.scala:119:23, :506:41] wire [3:0] packed_deps_hi_hi_53 = {packed_deps_hi_hi_hi_26, packed_deps_hi_hi_lo_26}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_hi_105 = {packed_deps_hi_hi_53, packed_deps_hi_lo_53}; // @[ReservationStation.scala:506:41] wire [15:0] _packed_deps_T_105 = {packed_deps_hi_105, packed_deps_lo_79}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_80 = {entries_st_2_bits_deps_st_1, entries_st_2_bits_deps_st_0}; // @[ReservationStation.scala:119:23, :506:70] wire [1:0] packed_deps_hi_106 = {entries_st_2_bits_deps_st_3, entries_st_2_bits_deps_st_2}; // @[ReservationStation.scala:119:23, :506:70] wire [3:0] _packed_deps_T_106 = {packed_deps_hi_106, packed_deps_lo_80}; // @[ReservationStation.scala:506:70] wire [23:0] packed_deps_hi_107 = {_packed_deps_T_104, _packed_deps_T_105}; // @[ReservationStation.scala:506:{8,12,41}] wire [27:0] _packed_deps_T_107 = {packed_deps_hi_107, _packed_deps_T_106}; // @[ReservationStation.scala:506:{8,70}] wire [27:0] packed_deps_26 = _packed_deps_T_107; // @[ReservationStation.scala:505:28, :506:8] wire [1:0] packed_deps_lo_lo_54 = {entries_st_3_bits_deps_ld_1, entries_st_3_bits_deps_ld_0}; // @[ReservationStation.scala:119:23, :506:12] wire [1:0] packed_deps_lo_hi_54 = {entries_st_3_bits_deps_ld_3, entries_st_3_bits_deps_ld_2}; // @[ReservationStation.scala:119:23, :506:12] wire [3:0] packed_deps_lo_81 = {packed_deps_lo_hi_54, packed_deps_lo_lo_54}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_hi_lo_54 = {entries_st_3_bits_deps_ld_5, entries_st_3_bits_deps_ld_4}; // @[ReservationStation.scala:119:23, :506:12] wire [1:0] packed_deps_hi_hi_54 = {entries_st_3_bits_deps_ld_7, entries_st_3_bits_deps_ld_6}; // @[ReservationStation.scala:119:23, :506:12] wire [3:0] packed_deps_hi_108 = {packed_deps_hi_hi_54, packed_deps_hi_lo_54}; // @[ReservationStation.scala:506:12] wire [7:0] _packed_deps_T_108 = {packed_deps_hi_108, packed_deps_lo_81}; // @[ReservationStation.scala:506:12] wire [1:0] packed_deps_lo_lo_lo_27 = {entries_st_3_bits_deps_ex_1, entries_st_3_bits_deps_ex_0}; // @[ReservationStation.scala:119:23, :506:41] wire [1:0] packed_deps_lo_lo_hi_27 = {entries_st_3_bits_deps_ex_3, entries_st_3_bits_deps_ex_2}; // @[ReservationStation.scala:119:23, :506:41] wire [3:0] packed_deps_lo_lo_55 = {packed_deps_lo_lo_hi_27, packed_deps_lo_lo_lo_27}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_hi_lo_27 = {entries_st_3_bits_deps_ex_5, entries_st_3_bits_deps_ex_4}; // @[ReservationStation.scala:119:23, :506:41] wire [1:0] packed_deps_lo_hi_hi_27 = {entries_st_3_bits_deps_ex_7, entries_st_3_bits_deps_ex_6}; // @[ReservationStation.scala:119:23, :506:41] wire [3:0] packed_deps_lo_hi_55 = {packed_deps_lo_hi_hi_27, packed_deps_lo_hi_lo_27}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_lo_82 = {packed_deps_lo_hi_55, packed_deps_lo_lo_55}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_lo_lo_27 = {entries_st_3_bits_deps_ex_9, entries_st_3_bits_deps_ex_8}; // @[ReservationStation.scala:119:23, :506:41] wire [1:0] packed_deps_hi_lo_hi_27 = {entries_st_3_bits_deps_ex_11, entries_st_3_bits_deps_ex_10}; // @[ReservationStation.scala:119:23, :506:41] wire [3:0] packed_deps_hi_lo_55 = {packed_deps_hi_lo_hi_27, packed_deps_hi_lo_lo_27}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_hi_hi_lo_27 = {entries_st_3_bits_deps_ex_13, entries_st_3_bits_deps_ex_12}; // @[ReservationStation.scala:119:23, :506:41] wire [1:0] packed_deps_hi_hi_hi_27 = {entries_st_3_bits_deps_ex_15, entries_st_3_bits_deps_ex_14}; // @[ReservationStation.scala:119:23, :506:41] wire [3:0] packed_deps_hi_hi_55 = {packed_deps_hi_hi_hi_27, packed_deps_hi_hi_lo_27}; // @[ReservationStation.scala:506:41] wire [7:0] packed_deps_hi_109 = {packed_deps_hi_hi_55, packed_deps_hi_lo_55}; // @[ReservationStation.scala:506:41] wire [15:0] _packed_deps_T_109 = {packed_deps_hi_109, packed_deps_lo_82}; // @[ReservationStation.scala:506:41] wire [1:0] packed_deps_lo_83 = {entries_st_3_bits_deps_st_1, entries_st_3_bits_deps_st_0}; // @[ReservationStation.scala:119:23, :506:70] wire [1:0] packed_deps_hi_110 = {entries_st_3_bits_deps_st_3, entries_st_3_bits_deps_st_2}; // @[ReservationStation.scala:119:23, :506:70] wire [3:0] _packed_deps_T_110 = {packed_deps_hi_110, packed_deps_lo_83}; // @[ReservationStation.scala:506:70] wire [23:0] packed_deps_hi_111 = {_packed_deps_T_108, _packed_deps_T_109}; // @[ReservationStation.scala:506:{8,12,41}] wire [27:0] _packed_deps_T_111 = {packed_deps_hi_111, _packed_deps_T_110}; // @[ReservationStation.scala:506:{8,70}] wire [27:0] packed_deps_27 = _packed_deps_T_111; // @[ReservationStation.scala:505:28, :506:8] wire [1:0] _pop_count_packed_deps_T = {1'h0, entries_ld_0_bits_deps_ld_0} + {1'h0, entries_ld_0_bits_deps_ld_1}; // @[ReservationStation.scala:117:23, :514:13] wire [1:0] _pop_count_packed_deps_T_1 = _pop_count_packed_deps_T; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_2 = {1'h0, entries_ld_0_bits_deps_ld_2} + {1'h0, entries_ld_0_bits_deps_ld_3}; // @[ReservationStation.scala:117:23, :514:13] wire [1:0] _pop_count_packed_deps_T_3 = _pop_count_packed_deps_T_2; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_4 = {1'h0, _pop_count_packed_deps_T_1} + {1'h0, _pop_count_packed_deps_T_3}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_5 = _pop_count_packed_deps_T_4; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_6 = {1'h0, entries_ld_0_bits_deps_ld_4} + {1'h0, entries_ld_0_bits_deps_ld_5}; // @[ReservationStation.scala:117:23, :514:13] wire [1:0] _pop_count_packed_deps_T_7 = _pop_count_packed_deps_T_6; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_8 = {1'h0, entries_ld_0_bits_deps_ld_6} + {1'h0, entries_ld_0_bits_deps_ld_7}; // @[ReservationStation.scala:117:23, :514:13] wire [1:0] _pop_count_packed_deps_T_9 = _pop_count_packed_deps_T_8; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_10 = {1'h0, _pop_count_packed_deps_T_7} + {1'h0, _pop_count_packed_deps_T_9}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_11 = _pop_count_packed_deps_T_10; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_12 = {1'h0, _pop_count_packed_deps_T_5} + {1'h0, _pop_count_packed_deps_T_11}; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_13 = _pop_count_packed_deps_T_12; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_14 = {1'h0, entries_ld_0_bits_deps_ex_0} + {1'h0, entries_ld_0_bits_deps_ex_1}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_15 = _pop_count_packed_deps_T_14; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_16 = {1'h0, entries_ld_0_bits_deps_ex_2} + {1'h0, entries_ld_0_bits_deps_ex_3}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_17 = _pop_count_packed_deps_T_16; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_18 = {1'h0, _pop_count_packed_deps_T_15} + {1'h0, _pop_count_packed_deps_T_17}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_19 = _pop_count_packed_deps_T_18; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_20 = {1'h0, entries_ld_0_bits_deps_ex_4} + {1'h0, entries_ld_0_bits_deps_ex_5}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_21 = _pop_count_packed_deps_T_20; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_22 = {1'h0, entries_ld_0_bits_deps_ex_6} + {1'h0, entries_ld_0_bits_deps_ex_7}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_23 = _pop_count_packed_deps_T_22; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_24 = {1'h0, _pop_count_packed_deps_T_21} + {1'h0, _pop_count_packed_deps_T_23}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_25 = _pop_count_packed_deps_T_24; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_26 = {1'h0, _pop_count_packed_deps_T_19} + {1'h0, _pop_count_packed_deps_T_25}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_27 = _pop_count_packed_deps_T_26; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_28 = {1'h0, entries_ld_0_bits_deps_ex_8} + {1'h0, entries_ld_0_bits_deps_ex_9}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_29 = _pop_count_packed_deps_T_28; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_30 = {1'h0, entries_ld_0_bits_deps_ex_10} + {1'h0, entries_ld_0_bits_deps_ex_11}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_31 = _pop_count_packed_deps_T_30; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_32 = {1'h0, _pop_count_packed_deps_T_29} + {1'h0, _pop_count_packed_deps_T_31}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_33 = _pop_count_packed_deps_T_32; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_34 = {1'h0, entries_ld_0_bits_deps_ex_12} + {1'h0, entries_ld_0_bits_deps_ex_13}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_35 = _pop_count_packed_deps_T_34; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_36 = {1'h0, entries_ld_0_bits_deps_ex_14} + {1'h0, entries_ld_0_bits_deps_ex_15}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_37 = _pop_count_packed_deps_T_36; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_38 = {1'h0, _pop_count_packed_deps_T_35} + {1'h0, _pop_count_packed_deps_T_37}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_39 = _pop_count_packed_deps_T_38; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_40 = {1'h0, _pop_count_packed_deps_T_33} + {1'h0, _pop_count_packed_deps_T_39}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_41 = _pop_count_packed_deps_T_40; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_42 = {1'h0, _pop_count_packed_deps_T_27} + {1'h0, _pop_count_packed_deps_T_41}; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_43 = _pop_count_packed_deps_T_42; // @[ReservationStation.scala:514:40] wire [5:0] _pop_count_packed_deps_T_44 = {2'h0, _pop_count_packed_deps_T_13} + {1'h0, _pop_count_packed_deps_T_43}; // @[ReservationStation.scala:514:{13,30,40}] wire [4:0] _pop_count_packed_deps_T_45 = _pop_count_packed_deps_T_44[4:0]; // @[ReservationStation.scala:514:30] wire [1:0] _pop_count_packed_deps_T_46 = {1'h0, entries_ld_0_bits_deps_st_0} + {1'h0, entries_ld_0_bits_deps_st_1}; // @[ReservationStation.scala:117:23, :514:67] wire [1:0] _pop_count_packed_deps_T_47 = _pop_count_packed_deps_T_46; // @[ReservationStation.scala:514:67] wire [1:0] _pop_count_packed_deps_T_48 = {1'h0, entries_ld_0_bits_deps_st_2} + {1'h0, entries_ld_0_bits_deps_st_3}; // @[ReservationStation.scala:117:23, :514:67] wire [1:0] _pop_count_packed_deps_T_49 = _pop_count_packed_deps_T_48; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_50 = {1'h0, _pop_count_packed_deps_T_47} + {1'h0, _pop_count_packed_deps_T_49}; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_51 = _pop_count_packed_deps_T_50; // @[ReservationStation.scala:514:67] wire [5:0] _pop_count_packed_deps_T_52 = {1'h0, _pop_count_packed_deps_T_45} + {3'h0, _pop_count_packed_deps_T_51}; // @[ReservationStation.scala:514:{30,57,67}] wire [4:0] _pop_count_packed_deps_T_53 = _pop_count_packed_deps_T_52[4:0]; // @[ReservationStation.scala:514:57] wire [4:0] _pop_count_packed_deps_T_54 = entries_ld_0_valid ? _pop_count_packed_deps_T_53 : 5'h0; // @[ReservationStation.scala:117:23, :513:59, :514:57] wire [4:0] pop_count_packed_deps_0 = _pop_count_packed_deps_T_54; // @[ReservationStation.scala:513:{38,59}] wire [1:0] _pop_count_packed_deps_T_55 = {1'h0, entries_ld_1_bits_deps_ld_0} + {1'h0, entries_ld_1_bits_deps_ld_1}; // @[ReservationStation.scala:117:23, :514:13] wire [1:0] _pop_count_packed_deps_T_56 = _pop_count_packed_deps_T_55; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_57 = {1'h0, entries_ld_1_bits_deps_ld_2} + {1'h0, entries_ld_1_bits_deps_ld_3}; // @[ReservationStation.scala:117:23, :514:13] wire [1:0] _pop_count_packed_deps_T_58 = _pop_count_packed_deps_T_57; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_59 = {1'h0, _pop_count_packed_deps_T_56} + {1'h0, _pop_count_packed_deps_T_58}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_60 = _pop_count_packed_deps_T_59; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_61 = {1'h0, entries_ld_1_bits_deps_ld_4} + {1'h0, entries_ld_1_bits_deps_ld_5}; // @[ReservationStation.scala:117:23, :514:13] wire [1:0] _pop_count_packed_deps_T_62 = _pop_count_packed_deps_T_61; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_63 = {1'h0, entries_ld_1_bits_deps_ld_6} + {1'h0, entries_ld_1_bits_deps_ld_7}; // @[ReservationStation.scala:117:23, :514:13] wire [1:0] _pop_count_packed_deps_T_64 = _pop_count_packed_deps_T_63; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_65 = {1'h0, _pop_count_packed_deps_T_62} + {1'h0, _pop_count_packed_deps_T_64}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_66 = _pop_count_packed_deps_T_65; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_67 = {1'h0, _pop_count_packed_deps_T_60} + {1'h0, _pop_count_packed_deps_T_66}; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_68 = _pop_count_packed_deps_T_67; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_69 = {1'h0, entries_ld_1_bits_deps_ex_0} + {1'h0, entries_ld_1_bits_deps_ex_1}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_70 = _pop_count_packed_deps_T_69; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_71 = {1'h0, entries_ld_1_bits_deps_ex_2} + {1'h0, entries_ld_1_bits_deps_ex_3}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_72 = _pop_count_packed_deps_T_71; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_73 = {1'h0, _pop_count_packed_deps_T_70} + {1'h0, _pop_count_packed_deps_T_72}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_74 = _pop_count_packed_deps_T_73; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_75 = {1'h0, entries_ld_1_bits_deps_ex_4} + {1'h0, entries_ld_1_bits_deps_ex_5}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_76 = _pop_count_packed_deps_T_75; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_77 = {1'h0, entries_ld_1_bits_deps_ex_6} + {1'h0, entries_ld_1_bits_deps_ex_7}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_78 = _pop_count_packed_deps_T_77; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_79 = {1'h0, _pop_count_packed_deps_T_76} + {1'h0, _pop_count_packed_deps_T_78}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_80 = _pop_count_packed_deps_T_79; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_81 = {1'h0, _pop_count_packed_deps_T_74} + {1'h0, _pop_count_packed_deps_T_80}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_82 = _pop_count_packed_deps_T_81; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_83 = {1'h0, entries_ld_1_bits_deps_ex_8} + {1'h0, entries_ld_1_bits_deps_ex_9}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_84 = _pop_count_packed_deps_T_83; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_85 = {1'h0, entries_ld_1_bits_deps_ex_10} + {1'h0, entries_ld_1_bits_deps_ex_11}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_86 = _pop_count_packed_deps_T_85; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_87 = {1'h0, _pop_count_packed_deps_T_84} + {1'h0, _pop_count_packed_deps_T_86}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_88 = _pop_count_packed_deps_T_87; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_89 = {1'h0, entries_ld_1_bits_deps_ex_12} + {1'h0, entries_ld_1_bits_deps_ex_13}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_90 = _pop_count_packed_deps_T_89; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_91 = {1'h0, entries_ld_1_bits_deps_ex_14} + {1'h0, entries_ld_1_bits_deps_ex_15}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_92 = _pop_count_packed_deps_T_91; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_93 = {1'h0, _pop_count_packed_deps_T_90} + {1'h0, _pop_count_packed_deps_T_92}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_94 = _pop_count_packed_deps_T_93; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_95 = {1'h0, _pop_count_packed_deps_T_88} + {1'h0, _pop_count_packed_deps_T_94}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_96 = _pop_count_packed_deps_T_95; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_97 = {1'h0, _pop_count_packed_deps_T_82} + {1'h0, _pop_count_packed_deps_T_96}; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_98 = _pop_count_packed_deps_T_97; // @[ReservationStation.scala:514:40] wire [5:0] _pop_count_packed_deps_T_99 = {2'h0, _pop_count_packed_deps_T_68} + {1'h0, _pop_count_packed_deps_T_98}; // @[ReservationStation.scala:514:{13,30,40}] wire [4:0] _pop_count_packed_deps_T_100 = _pop_count_packed_deps_T_99[4:0]; // @[ReservationStation.scala:514:30] wire [1:0] _pop_count_packed_deps_T_101 = {1'h0, entries_ld_1_bits_deps_st_0} + {1'h0, entries_ld_1_bits_deps_st_1}; // @[ReservationStation.scala:117:23, :514:67] wire [1:0] _pop_count_packed_deps_T_102 = _pop_count_packed_deps_T_101; // @[ReservationStation.scala:514:67] wire [1:0] _pop_count_packed_deps_T_103 = {1'h0, entries_ld_1_bits_deps_st_2} + {1'h0, entries_ld_1_bits_deps_st_3}; // @[ReservationStation.scala:117:23, :514:67] wire [1:0] _pop_count_packed_deps_T_104 = _pop_count_packed_deps_T_103; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_105 = {1'h0, _pop_count_packed_deps_T_102} + {1'h0, _pop_count_packed_deps_T_104}; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_106 = _pop_count_packed_deps_T_105; // @[ReservationStation.scala:514:67] wire [5:0] _pop_count_packed_deps_T_107 = {1'h0, _pop_count_packed_deps_T_100} + {3'h0, _pop_count_packed_deps_T_106}; // @[ReservationStation.scala:514:{30,57,67}] wire [4:0] _pop_count_packed_deps_T_108 = _pop_count_packed_deps_T_107[4:0]; // @[ReservationStation.scala:514:57] wire [4:0] _pop_count_packed_deps_T_109 = entries_ld_1_valid ? _pop_count_packed_deps_T_108 : 5'h0; // @[ReservationStation.scala:117:23, :513:59, :514:57] wire [4:0] pop_count_packed_deps_1 = _pop_count_packed_deps_T_109; // @[ReservationStation.scala:513:{38,59}] wire [1:0] _pop_count_packed_deps_T_110 = {1'h0, entries_ld_2_bits_deps_ld_0} + {1'h0, entries_ld_2_bits_deps_ld_1}; // @[ReservationStation.scala:117:23, :514:13] wire [1:0] _pop_count_packed_deps_T_111 = _pop_count_packed_deps_T_110; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_112 = {1'h0, entries_ld_2_bits_deps_ld_2} + {1'h0, entries_ld_2_bits_deps_ld_3}; // @[ReservationStation.scala:117:23, :514:13] wire [1:0] _pop_count_packed_deps_T_113 = _pop_count_packed_deps_T_112; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_114 = {1'h0, _pop_count_packed_deps_T_111} + {1'h0, _pop_count_packed_deps_T_113}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_115 = _pop_count_packed_deps_T_114; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_116 = {1'h0, entries_ld_2_bits_deps_ld_4} + {1'h0, entries_ld_2_bits_deps_ld_5}; // @[ReservationStation.scala:117:23, :514:13] wire [1:0] _pop_count_packed_deps_T_117 = _pop_count_packed_deps_T_116; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_118 = {1'h0, entries_ld_2_bits_deps_ld_6} + {1'h0, entries_ld_2_bits_deps_ld_7}; // @[ReservationStation.scala:117:23, :514:13] wire [1:0] _pop_count_packed_deps_T_119 = _pop_count_packed_deps_T_118; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_120 = {1'h0, _pop_count_packed_deps_T_117} + {1'h0, _pop_count_packed_deps_T_119}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_121 = _pop_count_packed_deps_T_120; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_122 = {1'h0, _pop_count_packed_deps_T_115} + {1'h0, _pop_count_packed_deps_T_121}; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_123 = _pop_count_packed_deps_T_122; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_124 = {1'h0, entries_ld_2_bits_deps_ex_0} + {1'h0, entries_ld_2_bits_deps_ex_1}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_125 = _pop_count_packed_deps_T_124; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_126 = {1'h0, entries_ld_2_bits_deps_ex_2} + {1'h0, entries_ld_2_bits_deps_ex_3}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_127 = _pop_count_packed_deps_T_126; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_128 = {1'h0, _pop_count_packed_deps_T_125} + {1'h0, _pop_count_packed_deps_T_127}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_129 = _pop_count_packed_deps_T_128; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_130 = {1'h0, entries_ld_2_bits_deps_ex_4} + {1'h0, entries_ld_2_bits_deps_ex_5}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_131 = _pop_count_packed_deps_T_130; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_132 = {1'h0, entries_ld_2_bits_deps_ex_6} + {1'h0, entries_ld_2_bits_deps_ex_7}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_133 = _pop_count_packed_deps_T_132; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_134 = {1'h0, _pop_count_packed_deps_T_131} + {1'h0, _pop_count_packed_deps_T_133}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_135 = _pop_count_packed_deps_T_134; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_136 = {1'h0, _pop_count_packed_deps_T_129} + {1'h0, _pop_count_packed_deps_T_135}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_137 = _pop_count_packed_deps_T_136; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_138 = {1'h0, entries_ld_2_bits_deps_ex_8} + {1'h0, entries_ld_2_bits_deps_ex_9}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_139 = _pop_count_packed_deps_T_138; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_140 = {1'h0, entries_ld_2_bits_deps_ex_10} + {1'h0, entries_ld_2_bits_deps_ex_11}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_141 = _pop_count_packed_deps_T_140; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_142 = {1'h0, _pop_count_packed_deps_T_139} + {1'h0, _pop_count_packed_deps_T_141}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_143 = _pop_count_packed_deps_T_142; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_144 = {1'h0, entries_ld_2_bits_deps_ex_12} + {1'h0, entries_ld_2_bits_deps_ex_13}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_145 = _pop_count_packed_deps_T_144; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_146 = {1'h0, entries_ld_2_bits_deps_ex_14} + {1'h0, entries_ld_2_bits_deps_ex_15}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_147 = _pop_count_packed_deps_T_146; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_148 = {1'h0, _pop_count_packed_deps_T_145} + {1'h0, _pop_count_packed_deps_T_147}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_149 = _pop_count_packed_deps_T_148; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_150 = {1'h0, _pop_count_packed_deps_T_143} + {1'h0, _pop_count_packed_deps_T_149}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_151 = _pop_count_packed_deps_T_150; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_152 = {1'h0, _pop_count_packed_deps_T_137} + {1'h0, _pop_count_packed_deps_T_151}; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_153 = _pop_count_packed_deps_T_152; // @[ReservationStation.scala:514:40] wire [5:0] _pop_count_packed_deps_T_154 = {2'h0, _pop_count_packed_deps_T_123} + {1'h0, _pop_count_packed_deps_T_153}; // @[ReservationStation.scala:514:{13,30,40}] wire [4:0] _pop_count_packed_deps_T_155 = _pop_count_packed_deps_T_154[4:0]; // @[ReservationStation.scala:514:30] wire [1:0] _pop_count_packed_deps_T_156 = {1'h0, entries_ld_2_bits_deps_st_0} + {1'h0, entries_ld_2_bits_deps_st_1}; // @[ReservationStation.scala:117:23, :514:67] wire [1:0] _pop_count_packed_deps_T_157 = _pop_count_packed_deps_T_156; // @[ReservationStation.scala:514:67] wire [1:0] _pop_count_packed_deps_T_158 = {1'h0, entries_ld_2_bits_deps_st_2} + {1'h0, entries_ld_2_bits_deps_st_3}; // @[ReservationStation.scala:117:23, :514:67] wire [1:0] _pop_count_packed_deps_T_159 = _pop_count_packed_deps_T_158; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_160 = {1'h0, _pop_count_packed_deps_T_157} + {1'h0, _pop_count_packed_deps_T_159}; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_161 = _pop_count_packed_deps_T_160; // @[ReservationStation.scala:514:67] wire [5:0] _pop_count_packed_deps_T_162 = {1'h0, _pop_count_packed_deps_T_155} + {3'h0, _pop_count_packed_deps_T_161}; // @[ReservationStation.scala:514:{30,57,67}] wire [4:0] _pop_count_packed_deps_T_163 = _pop_count_packed_deps_T_162[4:0]; // @[ReservationStation.scala:514:57] wire [4:0] _pop_count_packed_deps_T_164 = entries_ld_2_valid ? _pop_count_packed_deps_T_163 : 5'h0; // @[ReservationStation.scala:117:23, :513:59, :514:57] wire [4:0] pop_count_packed_deps_2 = _pop_count_packed_deps_T_164; // @[ReservationStation.scala:513:{38,59}] wire [1:0] _pop_count_packed_deps_T_165 = {1'h0, entries_ld_3_bits_deps_ld_0} + {1'h0, entries_ld_3_bits_deps_ld_1}; // @[ReservationStation.scala:117:23, :514:13] wire [1:0] _pop_count_packed_deps_T_166 = _pop_count_packed_deps_T_165; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_167 = {1'h0, entries_ld_3_bits_deps_ld_2} + {1'h0, entries_ld_3_bits_deps_ld_3}; // @[ReservationStation.scala:117:23, :514:13] wire [1:0] _pop_count_packed_deps_T_168 = _pop_count_packed_deps_T_167; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_169 = {1'h0, _pop_count_packed_deps_T_166} + {1'h0, _pop_count_packed_deps_T_168}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_170 = _pop_count_packed_deps_T_169; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_171 = {1'h0, entries_ld_3_bits_deps_ld_4} + {1'h0, entries_ld_3_bits_deps_ld_5}; // @[ReservationStation.scala:117:23, :514:13] wire [1:0] _pop_count_packed_deps_T_172 = _pop_count_packed_deps_T_171; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_173 = {1'h0, entries_ld_3_bits_deps_ld_6} + {1'h0, entries_ld_3_bits_deps_ld_7}; // @[ReservationStation.scala:117:23, :514:13] wire [1:0] _pop_count_packed_deps_T_174 = _pop_count_packed_deps_T_173; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_175 = {1'h0, _pop_count_packed_deps_T_172} + {1'h0, _pop_count_packed_deps_T_174}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_176 = _pop_count_packed_deps_T_175; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_177 = {1'h0, _pop_count_packed_deps_T_170} + {1'h0, _pop_count_packed_deps_T_176}; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_178 = _pop_count_packed_deps_T_177; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_179 = {1'h0, entries_ld_3_bits_deps_ex_0} + {1'h0, entries_ld_3_bits_deps_ex_1}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_180 = _pop_count_packed_deps_T_179; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_181 = {1'h0, entries_ld_3_bits_deps_ex_2} + {1'h0, entries_ld_3_bits_deps_ex_3}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_182 = _pop_count_packed_deps_T_181; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_183 = {1'h0, _pop_count_packed_deps_T_180} + {1'h0, _pop_count_packed_deps_T_182}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_184 = _pop_count_packed_deps_T_183; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_185 = {1'h0, entries_ld_3_bits_deps_ex_4} + {1'h0, entries_ld_3_bits_deps_ex_5}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_186 = _pop_count_packed_deps_T_185; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_187 = {1'h0, entries_ld_3_bits_deps_ex_6} + {1'h0, entries_ld_3_bits_deps_ex_7}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_188 = _pop_count_packed_deps_T_187; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_189 = {1'h0, _pop_count_packed_deps_T_186} + {1'h0, _pop_count_packed_deps_T_188}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_190 = _pop_count_packed_deps_T_189; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_191 = {1'h0, _pop_count_packed_deps_T_184} + {1'h0, _pop_count_packed_deps_T_190}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_192 = _pop_count_packed_deps_T_191; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_193 = {1'h0, entries_ld_3_bits_deps_ex_8} + {1'h0, entries_ld_3_bits_deps_ex_9}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_194 = _pop_count_packed_deps_T_193; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_195 = {1'h0, entries_ld_3_bits_deps_ex_10} + {1'h0, entries_ld_3_bits_deps_ex_11}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_196 = _pop_count_packed_deps_T_195; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_197 = {1'h0, _pop_count_packed_deps_T_194} + {1'h0, _pop_count_packed_deps_T_196}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_198 = _pop_count_packed_deps_T_197; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_199 = {1'h0, entries_ld_3_bits_deps_ex_12} + {1'h0, entries_ld_3_bits_deps_ex_13}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_200 = _pop_count_packed_deps_T_199; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_201 = {1'h0, entries_ld_3_bits_deps_ex_14} + {1'h0, entries_ld_3_bits_deps_ex_15}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_202 = _pop_count_packed_deps_T_201; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_203 = {1'h0, _pop_count_packed_deps_T_200} + {1'h0, _pop_count_packed_deps_T_202}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_204 = _pop_count_packed_deps_T_203; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_205 = {1'h0, _pop_count_packed_deps_T_198} + {1'h0, _pop_count_packed_deps_T_204}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_206 = _pop_count_packed_deps_T_205; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_207 = {1'h0, _pop_count_packed_deps_T_192} + {1'h0, _pop_count_packed_deps_T_206}; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_208 = _pop_count_packed_deps_T_207; // @[ReservationStation.scala:514:40] wire [5:0] _pop_count_packed_deps_T_209 = {2'h0, _pop_count_packed_deps_T_178} + {1'h0, _pop_count_packed_deps_T_208}; // @[ReservationStation.scala:514:{13,30,40}] wire [4:0] _pop_count_packed_deps_T_210 = _pop_count_packed_deps_T_209[4:0]; // @[ReservationStation.scala:514:30] wire [1:0] _pop_count_packed_deps_T_211 = {1'h0, entries_ld_3_bits_deps_st_0} + {1'h0, entries_ld_3_bits_deps_st_1}; // @[ReservationStation.scala:117:23, :514:67] wire [1:0] _pop_count_packed_deps_T_212 = _pop_count_packed_deps_T_211; // @[ReservationStation.scala:514:67] wire [1:0] _pop_count_packed_deps_T_213 = {1'h0, entries_ld_3_bits_deps_st_2} + {1'h0, entries_ld_3_bits_deps_st_3}; // @[ReservationStation.scala:117:23, :514:67] wire [1:0] _pop_count_packed_deps_T_214 = _pop_count_packed_deps_T_213; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_215 = {1'h0, _pop_count_packed_deps_T_212} + {1'h0, _pop_count_packed_deps_T_214}; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_216 = _pop_count_packed_deps_T_215; // @[ReservationStation.scala:514:67] wire [5:0] _pop_count_packed_deps_T_217 = {1'h0, _pop_count_packed_deps_T_210} + {3'h0, _pop_count_packed_deps_T_216}; // @[ReservationStation.scala:514:{30,57,67}] wire [4:0] _pop_count_packed_deps_T_218 = _pop_count_packed_deps_T_217[4:0]; // @[ReservationStation.scala:514:57] wire [4:0] _pop_count_packed_deps_T_219 = entries_ld_3_valid ? _pop_count_packed_deps_T_218 : 5'h0; // @[ReservationStation.scala:117:23, :513:59, :514:57] wire [4:0] pop_count_packed_deps_3 = _pop_count_packed_deps_T_219; // @[ReservationStation.scala:513:{38,59}] wire [1:0] _pop_count_packed_deps_T_220 = {1'h0, entries_ld_4_bits_deps_ld_0} + {1'h0, entries_ld_4_bits_deps_ld_1}; // @[ReservationStation.scala:117:23, :514:13] wire [1:0] _pop_count_packed_deps_T_221 = _pop_count_packed_deps_T_220; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_222 = {1'h0, entries_ld_4_bits_deps_ld_2} + {1'h0, entries_ld_4_bits_deps_ld_3}; // @[ReservationStation.scala:117:23, :514:13] wire [1:0] _pop_count_packed_deps_T_223 = _pop_count_packed_deps_T_222; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_224 = {1'h0, _pop_count_packed_deps_T_221} + {1'h0, _pop_count_packed_deps_T_223}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_225 = _pop_count_packed_deps_T_224; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_226 = {1'h0, entries_ld_4_bits_deps_ld_4} + {1'h0, entries_ld_4_bits_deps_ld_5}; // @[ReservationStation.scala:117:23, :514:13] wire [1:0] _pop_count_packed_deps_T_227 = _pop_count_packed_deps_T_226; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_228 = {1'h0, entries_ld_4_bits_deps_ld_6} + {1'h0, entries_ld_4_bits_deps_ld_7}; // @[ReservationStation.scala:117:23, :514:13] wire [1:0] _pop_count_packed_deps_T_229 = _pop_count_packed_deps_T_228; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_230 = {1'h0, _pop_count_packed_deps_T_227} + {1'h0, _pop_count_packed_deps_T_229}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_231 = _pop_count_packed_deps_T_230; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_232 = {1'h0, _pop_count_packed_deps_T_225} + {1'h0, _pop_count_packed_deps_T_231}; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_233 = _pop_count_packed_deps_T_232; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_234 = {1'h0, entries_ld_4_bits_deps_ex_0} + {1'h0, entries_ld_4_bits_deps_ex_1}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_235 = _pop_count_packed_deps_T_234; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_236 = {1'h0, entries_ld_4_bits_deps_ex_2} + {1'h0, entries_ld_4_bits_deps_ex_3}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_237 = _pop_count_packed_deps_T_236; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_238 = {1'h0, _pop_count_packed_deps_T_235} + {1'h0, _pop_count_packed_deps_T_237}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_239 = _pop_count_packed_deps_T_238; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_240 = {1'h0, entries_ld_4_bits_deps_ex_4} + {1'h0, entries_ld_4_bits_deps_ex_5}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_241 = _pop_count_packed_deps_T_240; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_242 = {1'h0, entries_ld_4_bits_deps_ex_6} + {1'h0, entries_ld_4_bits_deps_ex_7}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_243 = _pop_count_packed_deps_T_242; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_244 = {1'h0, _pop_count_packed_deps_T_241} + {1'h0, _pop_count_packed_deps_T_243}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_245 = _pop_count_packed_deps_T_244; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_246 = {1'h0, _pop_count_packed_deps_T_239} + {1'h0, _pop_count_packed_deps_T_245}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_247 = _pop_count_packed_deps_T_246; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_248 = {1'h0, entries_ld_4_bits_deps_ex_8} + {1'h0, entries_ld_4_bits_deps_ex_9}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_249 = _pop_count_packed_deps_T_248; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_250 = {1'h0, entries_ld_4_bits_deps_ex_10} + {1'h0, entries_ld_4_bits_deps_ex_11}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_251 = _pop_count_packed_deps_T_250; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_252 = {1'h0, _pop_count_packed_deps_T_249} + {1'h0, _pop_count_packed_deps_T_251}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_253 = _pop_count_packed_deps_T_252; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_254 = {1'h0, entries_ld_4_bits_deps_ex_12} + {1'h0, entries_ld_4_bits_deps_ex_13}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_255 = _pop_count_packed_deps_T_254; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_256 = {1'h0, entries_ld_4_bits_deps_ex_14} + {1'h0, entries_ld_4_bits_deps_ex_15}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_257 = _pop_count_packed_deps_T_256; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_258 = {1'h0, _pop_count_packed_deps_T_255} + {1'h0, _pop_count_packed_deps_T_257}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_259 = _pop_count_packed_deps_T_258; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_260 = {1'h0, _pop_count_packed_deps_T_253} + {1'h0, _pop_count_packed_deps_T_259}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_261 = _pop_count_packed_deps_T_260; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_262 = {1'h0, _pop_count_packed_deps_T_247} + {1'h0, _pop_count_packed_deps_T_261}; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_263 = _pop_count_packed_deps_T_262; // @[ReservationStation.scala:514:40] wire [5:0] _pop_count_packed_deps_T_264 = {2'h0, _pop_count_packed_deps_T_233} + {1'h0, _pop_count_packed_deps_T_263}; // @[ReservationStation.scala:514:{13,30,40}] wire [4:0] _pop_count_packed_deps_T_265 = _pop_count_packed_deps_T_264[4:0]; // @[ReservationStation.scala:514:30] wire [1:0] _pop_count_packed_deps_T_266 = {1'h0, entries_ld_4_bits_deps_st_0} + {1'h0, entries_ld_4_bits_deps_st_1}; // @[ReservationStation.scala:117:23, :514:67] wire [1:0] _pop_count_packed_deps_T_267 = _pop_count_packed_deps_T_266; // @[ReservationStation.scala:514:67] wire [1:0] _pop_count_packed_deps_T_268 = {1'h0, entries_ld_4_bits_deps_st_2} + {1'h0, entries_ld_4_bits_deps_st_3}; // @[ReservationStation.scala:117:23, :514:67] wire [1:0] _pop_count_packed_deps_T_269 = _pop_count_packed_deps_T_268; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_270 = {1'h0, _pop_count_packed_deps_T_267} + {1'h0, _pop_count_packed_deps_T_269}; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_271 = _pop_count_packed_deps_T_270; // @[ReservationStation.scala:514:67] wire [5:0] _pop_count_packed_deps_T_272 = {1'h0, _pop_count_packed_deps_T_265} + {3'h0, _pop_count_packed_deps_T_271}; // @[ReservationStation.scala:514:{30,57,67}] wire [4:0] _pop_count_packed_deps_T_273 = _pop_count_packed_deps_T_272[4:0]; // @[ReservationStation.scala:514:57] wire [4:0] _pop_count_packed_deps_T_274 = entries_ld_4_valid ? _pop_count_packed_deps_T_273 : 5'h0; // @[ReservationStation.scala:117:23, :513:59, :514:57] wire [4:0] pop_count_packed_deps_4 = _pop_count_packed_deps_T_274; // @[ReservationStation.scala:513:{38,59}] wire [1:0] _pop_count_packed_deps_T_275 = {1'h0, entries_ld_5_bits_deps_ld_0} + {1'h0, entries_ld_5_bits_deps_ld_1}; // @[ReservationStation.scala:117:23, :514:13] wire [1:0] _pop_count_packed_deps_T_276 = _pop_count_packed_deps_T_275; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_277 = {1'h0, entries_ld_5_bits_deps_ld_2} + {1'h0, entries_ld_5_bits_deps_ld_3}; // @[ReservationStation.scala:117:23, :514:13] wire [1:0] _pop_count_packed_deps_T_278 = _pop_count_packed_deps_T_277; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_279 = {1'h0, _pop_count_packed_deps_T_276} + {1'h0, _pop_count_packed_deps_T_278}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_280 = _pop_count_packed_deps_T_279; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_281 = {1'h0, entries_ld_5_bits_deps_ld_4} + {1'h0, entries_ld_5_bits_deps_ld_5}; // @[ReservationStation.scala:117:23, :514:13] wire [1:0] _pop_count_packed_deps_T_282 = _pop_count_packed_deps_T_281; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_283 = {1'h0, entries_ld_5_bits_deps_ld_6} + {1'h0, entries_ld_5_bits_deps_ld_7}; // @[ReservationStation.scala:117:23, :514:13] wire [1:0] _pop_count_packed_deps_T_284 = _pop_count_packed_deps_T_283; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_285 = {1'h0, _pop_count_packed_deps_T_282} + {1'h0, _pop_count_packed_deps_T_284}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_286 = _pop_count_packed_deps_T_285; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_287 = {1'h0, _pop_count_packed_deps_T_280} + {1'h0, _pop_count_packed_deps_T_286}; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_288 = _pop_count_packed_deps_T_287; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_289 = {1'h0, entries_ld_5_bits_deps_ex_0} + {1'h0, entries_ld_5_bits_deps_ex_1}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_290 = _pop_count_packed_deps_T_289; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_291 = {1'h0, entries_ld_5_bits_deps_ex_2} + {1'h0, entries_ld_5_bits_deps_ex_3}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_292 = _pop_count_packed_deps_T_291; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_293 = {1'h0, _pop_count_packed_deps_T_290} + {1'h0, _pop_count_packed_deps_T_292}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_294 = _pop_count_packed_deps_T_293; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_295 = {1'h0, entries_ld_5_bits_deps_ex_4} + {1'h0, entries_ld_5_bits_deps_ex_5}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_296 = _pop_count_packed_deps_T_295; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_297 = {1'h0, entries_ld_5_bits_deps_ex_6} + {1'h0, entries_ld_5_bits_deps_ex_7}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_298 = _pop_count_packed_deps_T_297; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_299 = {1'h0, _pop_count_packed_deps_T_296} + {1'h0, _pop_count_packed_deps_T_298}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_300 = _pop_count_packed_deps_T_299; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_301 = {1'h0, _pop_count_packed_deps_T_294} + {1'h0, _pop_count_packed_deps_T_300}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_302 = _pop_count_packed_deps_T_301; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_303 = {1'h0, entries_ld_5_bits_deps_ex_8} + {1'h0, entries_ld_5_bits_deps_ex_9}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_304 = _pop_count_packed_deps_T_303; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_305 = {1'h0, entries_ld_5_bits_deps_ex_10} + {1'h0, entries_ld_5_bits_deps_ex_11}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_306 = _pop_count_packed_deps_T_305; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_307 = {1'h0, _pop_count_packed_deps_T_304} + {1'h0, _pop_count_packed_deps_T_306}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_308 = _pop_count_packed_deps_T_307; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_309 = {1'h0, entries_ld_5_bits_deps_ex_12} + {1'h0, entries_ld_5_bits_deps_ex_13}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_310 = _pop_count_packed_deps_T_309; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_311 = {1'h0, entries_ld_5_bits_deps_ex_14} + {1'h0, entries_ld_5_bits_deps_ex_15}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_312 = _pop_count_packed_deps_T_311; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_313 = {1'h0, _pop_count_packed_deps_T_310} + {1'h0, _pop_count_packed_deps_T_312}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_314 = _pop_count_packed_deps_T_313; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_315 = {1'h0, _pop_count_packed_deps_T_308} + {1'h0, _pop_count_packed_deps_T_314}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_316 = _pop_count_packed_deps_T_315; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_317 = {1'h0, _pop_count_packed_deps_T_302} + {1'h0, _pop_count_packed_deps_T_316}; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_318 = _pop_count_packed_deps_T_317; // @[ReservationStation.scala:514:40] wire [5:0] _pop_count_packed_deps_T_319 = {2'h0, _pop_count_packed_deps_T_288} + {1'h0, _pop_count_packed_deps_T_318}; // @[ReservationStation.scala:514:{13,30,40}] wire [4:0] _pop_count_packed_deps_T_320 = _pop_count_packed_deps_T_319[4:0]; // @[ReservationStation.scala:514:30] wire [1:0] _pop_count_packed_deps_T_321 = {1'h0, entries_ld_5_bits_deps_st_0} + {1'h0, entries_ld_5_bits_deps_st_1}; // @[ReservationStation.scala:117:23, :514:67] wire [1:0] _pop_count_packed_deps_T_322 = _pop_count_packed_deps_T_321; // @[ReservationStation.scala:514:67] wire [1:0] _pop_count_packed_deps_T_323 = {1'h0, entries_ld_5_bits_deps_st_2} + {1'h0, entries_ld_5_bits_deps_st_3}; // @[ReservationStation.scala:117:23, :514:67] wire [1:0] _pop_count_packed_deps_T_324 = _pop_count_packed_deps_T_323; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_325 = {1'h0, _pop_count_packed_deps_T_322} + {1'h0, _pop_count_packed_deps_T_324}; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_326 = _pop_count_packed_deps_T_325; // @[ReservationStation.scala:514:67] wire [5:0] _pop_count_packed_deps_T_327 = {1'h0, _pop_count_packed_deps_T_320} + {3'h0, _pop_count_packed_deps_T_326}; // @[ReservationStation.scala:514:{30,57,67}] wire [4:0] _pop_count_packed_deps_T_328 = _pop_count_packed_deps_T_327[4:0]; // @[ReservationStation.scala:514:57] wire [4:0] _pop_count_packed_deps_T_329 = entries_ld_5_valid ? _pop_count_packed_deps_T_328 : 5'h0; // @[ReservationStation.scala:117:23, :513:59, :514:57] wire [4:0] pop_count_packed_deps_5 = _pop_count_packed_deps_T_329; // @[ReservationStation.scala:513:{38,59}] wire [1:0] _pop_count_packed_deps_T_330 = {1'h0, entries_ld_6_bits_deps_ld_0} + {1'h0, entries_ld_6_bits_deps_ld_1}; // @[ReservationStation.scala:117:23, :514:13] wire [1:0] _pop_count_packed_deps_T_331 = _pop_count_packed_deps_T_330; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_332 = {1'h0, entries_ld_6_bits_deps_ld_2} + {1'h0, entries_ld_6_bits_deps_ld_3}; // @[ReservationStation.scala:117:23, :514:13] wire [1:0] _pop_count_packed_deps_T_333 = _pop_count_packed_deps_T_332; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_334 = {1'h0, _pop_count_packed_deps_T_331} + {1'h0, _pop_count_packed_deps_T_333}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_335 = _pop_count_packed_deps_T_334; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_336 = {1'h0, entries_ld_6_bits_deps_ld_4} + {1'h0, entries_ld_6_bits_deps_ld_5}; // @[ReservationStation.scala:117:23, :514:13] wire [1:0] _pop_count_packed_deps_T_337 = _pop_count_packed_deps_T_336; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_338 = {1'h0, entries_ld_6_bits_deps_ld_6} + {1'h0, entries_ld_6_bits_deps_ld_7}; // @[ReservationStation.scala:117:23, :514:13] wire [1:0] _pop_count_packed_deps_T_339 = _pop_count_packed_deps_T_338; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_340 = {1'h0, _pop_count_packed_deps_T_337} + {1'h0, _pop_count_packed_deps_T_339}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_341 = _pop_count_packed_deps_T_340; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_342 = {1'h0, _pop_count_packed_deps_T_335} + {1'h0, _pop_count_packed_deps_T_341}; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_343 = _pop_count_packed_deps_T_342; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_344 = {1'h0, entries_ld_6_bits_deps_ex_0} + {1'h0, entries_ld_6_bits_deps_ex_1}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_345 = _pop_count_packed_deps_T_344; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_346 = {1'h0, entries_ld_6_bits_deps_ex_2} + {1'h0, entries_ld_6_bits_deps_ex_3}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_347 = _pop_count_packed_deps_T_346; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_348 = {1'h0, _pop_count_packed_deps_T_345} + {1'h0, _pop_count_packed_deps_T_347}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_349 = _pop_count_packed_deps_T_348; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_350 = {1'h0, entries_ld_6_bits_deps_ex_4} + {1'h0, entries_ld_6_bits_deps_ex_5}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_351 = _pop_count_packed_deps_T_350; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_352 = {1'h0, entries_ld_6_bits_deps_ex_6} + {1'h0, entries_ld_6_bits_deps_ex_7}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_353 = _pop_count_packed_deps_T_352; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_354 = {1'h0, _pop_count_packed_deps_T_351} + {1'h0, _pop_count_packed_deps_T_353}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_355 = _pop_count_packed_deps_T_354; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_356 = {1'h0, _pop_count_packed_deps_T_349} + {1'h0, _pop_count_packed_deps_T_355}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_357 = _pop_count_packed_deps_T_356; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_358 = {1'h0, entries_ld_6_bits_deps_ex_8} + {1'h0, entries_ld_6_bits_deps_ex_9}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_359 = _pop_count_packed_deps_T_358; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_360 = {1'h0, entries_ld_6_bits_deps_ex_10} + {1'h0, entries_ld_6_bits_deps_ex_11}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_361 = _pop_count_packed_deps_T_360; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_362 = {1'h0, _pop_count_packed_deps_T_359} + {1'h0, _pop_count_packed_deps_T_361}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_363 = _pop_count_packed_deps_T_362; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_364 = {1'h0, entries_ld_6_bits_deps_ex_12} + {1'h0, entries_ld_6_bits_deps_ex_13}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_365 = _pop_count_packed_deps_T_364; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_366 = {1'h0, entries_ld_6_bits_deps_ex_14} + {1'h0, entries_ld_6_bits_deps_ex_15}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_367 = _pop_count_packed_deps_T_366; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_368 = {1'h0, _pop_count_packed_deps_T_365} + {1'h0, _pop_count_packed_deps_T_367}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_369 = _pop_count_packed_deps_T_368; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_370 = {1'h0, _pop_count_packed_deps_T_363} + {1'h0, _pop_count_packed_deps_T_369}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_371 = _pop_count_packed_deps_T_370; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_372 = {1'h0, _pop_count_packed_deps_T_357} + {1'h0, _pop_count_packed_deps_T_371}; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_373 = _pop_count_packed_deps_T_372; // @[ReservationStation.scala:514:40] wire [5:0] _pop_count_packed_deps_T_374 = {2'h0, _pop_count_packed_deps_T_343} + {1'h0, _pop_count_packed_deps_T_373}; // @[ReservationStation.scala:514:{13,30,40}] wire [4:0] _pop_count_packed_deps_T_375 = _pop_count_packed_deps_T_374[4:0]; // @[ReservationStation.scala:514:30] wire [1:0] _pop_count_packed_deps_T_376 = {1'h0, entries_ld_6_bits_deps_st_0} + {1'h0, entries_ld_6_bits_deps_st_1}; // @[ReservationStation.scala:117:23, :514:67] wire [1:0] _pop_count_packed_deps_T_377 = _pop_count_packed_deps_T_376; // @[ReservationStation.scala:514:67] wire [1:0] _pop_count_packed_deps_T_378 = {1'h0, entries_ld_6_bits_deps_st_2} + {1'h0, entries_ld_6_bits_deps_st_3}; // @[ReservationStation.scala:117:23, :514:67] wire [1:0] _pop_count_packed_deps_T_379 = _pop_count_packed_deps_T_378; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_380 = {1'h0, _pop_count_packed_deps_T_377} + {1'h0, _pop_count_packed_deps_T_379}; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_381 = _pop_count_packed_deps_T_380; // @[ReservationStation.scala:514:67] wire [5:0] _pop_count_packed_deps_T_382 = {1'h0, _pop_count_packed_deps_T_375} + {3'h0, _pop_count_packed_deps_T_381}; // @[ReservationStation.scala:514:{30,57,67}] wire [4:0] _pop_count_packed_deps_T_383 = _pop_count_packed_deps_T_382[4:0]; // @[ReservationStation.scala:514:57] wire [4:0] _pop_count_packed_deps_T_384 = entries_ld_6_valid ? _pop_count_packed_deps_T_383 : 5'h0; // @[ReservationStation.scala:117:23, :513:59, :514:57] wire [4:0] pop_count_packed_deps_6 = _pop_count_packed_deps_T_384; // @[ReservationStation.scala:513:{38,59}] wire [1:0] _pop_count_packed_deps_T_385 = {1'h0, entries_ld_7_bits_deps_ld_0} + {1'h0, entries_ld_7_bits_deps_ld_1}; // @[ReservationStation.scala:117:23, :514:13] wire [1:0] _pop_count_packed_deps_T_386 = _pop_count_packed_deps_T_385; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_387 = {1'h0, entries_ld_7_bits_deps_ld_2} + {1'h0, entries_ld_7_bits_deps_ld_3}; // @[ReservationStation.scala:117:23, :514:13] wire [1:0] _pop_count_packed_deps_T_388 = _pop_count_packed_deps_T_387; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_389 = {1'h0, _pop_count_packed_deps_T_386} + {1'h0, _pop_count_packed_deps_T_388}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_390 = _pop_count_packed_deps_T_389; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_391 = {1'h0, entries_ld_7_bits_deps_ld_4} + {1'h0, entries_ld_7_bits_deps_ld_5}; // @[ReservationStation.scala:117:23, :514:13] wire [1:0] _pop_count_packed_deps_T_392 = _pop_count_packed_deps_T_391; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_393 = {1'h0, entries_ld_7_bits_deps_ld_6} + {1'h0, entries_ld_7_bits_deps_ld_7}; // @[ReservationStation.scala:117:23, :514:13] wire [1:0] _pop_count_packed_deps_T_394 = _pop_count_packed_deps_T_393; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_395 = {1'h0, _pop_count_packed_deps_T_392} + {1'h0, _pop_count_packed_deps_T_394}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_396 = _pop_count_packed_deps_T_395; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_397 = {1'h0, _pop_count_packed_deps_T_390} + {1'h0, _pop_count_packed_deps_T_396}; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_398 = _pop_count_packed_deps_T_397; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_399 = {1'h0, entries_ld_7_bits_deps_ex_0} + {1'h0, entries_ld_7_bits_deps_ex_1}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_400 = _pop_count_packed_deps_T_399; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_401 = {1'h0, entries_ld_7_bits_deps_ex_2} + {1'h0, entries_ld_7_bits_deps_ex_3}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_402 = _pop_count_packed_deps_T_401; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_403 = {1'h0, _pop_count_packed_deps_T_400} + {1'h0, _pop_count_packed_deps_T_402}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_404 = _pop_count_packed_deps_T_403; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_405 = {1'h0, entries_ld_7_bits_deps_ex_4} + {1'h0, entries_ld_7_bits_deps_ex_5}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_406 = _pop_count_packed_deps_T_405; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_407 = {1'h0, entries_ld_7_bits_deps_ex_6} + {1'h0, entries_ld_7_bits_deps_ex_7}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_408 = _pop_count_packed_deps_T_407; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_409 = {1'h0, _pop_count_packed_deps_T_406} + {1'h0, _pop_count_packed_deps_T_408}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_410 = _pop_count_packed_deps_T_409; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_411 = {1'h0, _pop_count_packed_deps_T_404} + {1'h0, _pop_count_packed_deps_T_410}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_412 = _pop_count_packed_deps_T_411; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_413 = {1'h0, entries_ld_7_bits_deps_ex_8} + {1'h0, entries_ld_7_bits_deps_ex_9}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_414 = _pop_count_packed_deps_T_413; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_415 = {1'h0, entries_ld_7_bits_deps_ex_10} + {1'h0, entries_ld_7_bits_deps_ex_11}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_416 = _pop_count_packed_deps_T_415; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_417 = {1'h0, _pop_count_packed_deps_T_414} + {1'h0, _pop_count_packed_deps_T_416}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_418 = _pop_count_packed_deps_T_417; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_419 = {1'h0, entries_ld_7_bits_deps_ex_12} + {1'h0, entries_ld_7_bits_deps_ex_13}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_420 = _pop_count_packed_deps_T_419; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_421 = {1'h0, entries_ld_7_bits_deps_ex_14} + {1'h0, entries_ld_7_bits_deps_ex_15}; // @[ReservationStation.scala:117:23, :514:40] wire [1:0] _pop_count_packed_deps_T_422 = _pop_count_packed_deps_T_421; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_423 = {1'h0, _pop_count_packed_deps_T_420} + {1'h0, _pop_count_packed_deps_T_422}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_424 = _pop_count_packed_deps_T_423; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_425 = {1'h0, _pop_count_packed_deps_T_418} + {1'h0, _pop_count_packed_deps_T_424}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_426 = _pop_count_packed_deps_T_425; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_427 = {1'h0, _pop_count_packed_deps_T_412} + {1'h0, _pop_count_packed_deps_T_426}; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_428 = _pop_count_packed_deps_T_427; // @[ReservationStation.scala:514:40] wire [5:0] _pop_count_packed_deps_T_429 = {2'h0, _pop_count_packed_deps_T_398} + {1'h0, _pop_count_packed_deps_T_428}; // @[ReservationStation.scala:514:{13,30,40}] wire [4:0] _pop_count_packed_deps_T_430 = _pop_count_packed_deps_T_429[4:0]; // @[ReservationStation.scala:514:30] wire [1:0] _pop_count_packed_deps_T_431 = {1'h0, entries_ld_7_bits_deps_st_0} + {1'h0, entries_ld_7_bits_deps_st_1}; // @[ReservationStation.scala:117:23, :514:67] wire [1:0] _pop_count_packed_deps_T_432 = _pop_count_packed_deps_T_431; // @[ReservationStation.scala:514:67] wire [1:0] _pop_count_packed_deps_T_433 = {1'h0, entries_ld_7_bits_deps_st_2} + {1'h0, entries_ld_7_bits_deps_st_3}; // @[ReservationStation.scala:117:23, :514:67] wire [1:0] _pop_count_packed_deps_T_434 = _pop_count_packed_deps_T_433; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_435 = {1'h0, _pop_count_packed_deps_T_432} + {1'h0, _pop_count_packed_deps_T_434}; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_436 = _pop_count_packed_deps_T_435; // @[ReservationStation.scala:514:67] wire [5:0] _pop_count_packed_deps_T_437 = {1'h0, _pop_count_packed_deps_T_430} + {3'h0, _pop_count_packed_deps_T_436}; // @[ReservationStation.scala:514:{30,57,67}] wire [4:0] _pop_count_packed_deps_T_438 = _pop_count_packed_deps_T_437[4:0]; // @[ReservationStation.scala:514:57] wire [4:0] _pop_count_packed_deps_T_439 = entries_ld_7_valid ? _pop_count_packed_deps_T_438 : 5'h0; // @[ReservationStation.scala:117:23, :513:59, :514:57] wire [4:0] pop_count_packed_deps_7 = _pop_count_packed_deps_T_439; // @[ReservationStation.scala:513:{38,59}] wire [1:0] _pop_count_packed_deps_T_440 = {1'h0, entries_ex_0_bits_deps_ld_0} + {1'h0, entries_ex_0_bits_deps_ld_1}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_441 = _pop_count_packed_deps_T_440; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_442 = {1'h0, entries_ex_0_bits_deps_ld_2} + {1'h0, entries_ex_0_bits_deps_ld_3}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_443 = _pop_count_packed_deps_T_442; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_444 = {1'h0, _pop_count_packed_deps_T_441} + {1'h0, _pop_count_packed_deps_T_443}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_445 = _pop_count_packed_deps_T_444; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_446 = {1'h0, entries_ex_0_bits_deps_ld_4} + {1'h0, entries_ex_0_bits_deps_ld_5}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_447 = _pop_count_packed_deps_T_446; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_448 = {1'h0, entries_ex_0_bits_deps_ld_6} + {1'h0, entries_ex_0_bits_deps_ld_7}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_449 = _pop_count_packed_deps_T_448; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_450 = {1'h0, _pop_count_packed_deps_T_447} + {1'h0, _pop_count_packed_deps_T_449}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_451 = _pop_count_packed_deps_T_450; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_452 = {1'h0, _pop_count_packed_deps_T_445} + {1'h0, _pop_count_packed_deps_T_451}; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_453 = _pop_count_packed_deps_T_452; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_454 = {1'h0, entries_ex_0_bits_deps_ex_0} + {1'h0, entries_ex_0_bits_deps_ex_1}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_455 = _pop_count_packed_deps_T_454; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_456 = {1'h0, entries_ex_0_bits_deps_ex_2} + {1'h0, entries_ex_0_bits_deps_ex_3}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_457 = _pop_count_packed_deps_T_456; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_458 = {1'h0, _pop_count_packed_deps_T_455} + {1'h0, _pop_count_packed_deps_T_457}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_459 = _pop_count_packed_deps_T_458; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_460 = {1'h0, entries_ex_0_bits_deps_ex_4} + {1'h0, entries_ex_0_bits_deps_ex_5}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_461 = _pop_count_packed_deps_T_460; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_462 = {1'h0, entries_ex_0_bits_deps_ex_6} + {1'h0, entries_ex_0_bits_deps_ex_7}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_463 = _pop_count_packed_deps_T_462; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_464 = {1'h0, _pop_count_packed_deps_T_461} + {1'h0, _pop_count_packed_deps_T_463}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_465 = _pop_count_packed_deps_T_464; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_466 = {1'h0, _pop_count_packed_deps_T_459} + {1'h0, _pop_count_packed_deps_T_465}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_467 = _pop_count_packed_deps_T_466; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_468 = {1'h0, entries_ex_0_bits_deps_ex_8} + {1'h0, entries_ex_0_bits_deps_ex_9}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_469 = _pop_count_packed_deps_T_468; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_470 = {1'h0, entries_ex_0_bits_deps_ex_10} + {1'h0, entries_ex_0_bits_deps_ex_11}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_471 = _pop_count_packed_deps_T_470; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_472 = {1'h0, _pop_count_packed_deps_T_469} + {1'h0, _pop_count_packed_deps_T_471}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_473 = _pop_count_packed_deps_T_472; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_474 = {1'h0, entries_ex_0_bits_deps_ex_12} + {1'h0, entries_ex_0_bits_deps_ex_13}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_475 = _pop_count_packed_deps_T_474; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_476 = {1'h0, entries_ex_0_bits_deps_ex_14} + {1'h0, entries_ex_0_bits_deps_ex_15}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_477 = _pop_count_packed_deps_T_476; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_478 = {1'h0, _pop_count_packed_deps_T_475} + {1'h0, _pop_count_packed_deps_T_477}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_479 = _pop_count_packed_deps_T_478; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_480 = {1'h0, _pop_count_packed_deps_T_473} + {1'h0, _pop_count_packed_deps_T_479}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_481 = _pop_count_packed_deps_T_480; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_482 = {1'h0, _pop_count_packed_deps_T_467} + {1'h0, _pop_count_packed_deps_T_481}; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_483 = _pop_count_packed_deps_T_482; // @[ReservationStation.scala:514:40] wire [5:0] _pop_count_packed_deps_T_484 = {2'h0, _pop_count_packed_deps_T_453} + {1'h0, _pop_count_packed_deps_T_483}; // @[ReservationStation.scala:514:{13,30,40}] wire [4:0] _pop_count_packed_deps_T_485 = _pop_count_packed_deps_T_484[4:0]; // @[ReservationStation.scala:514:30] wire [1:0] _pop_count_packed_deps_T_486 = {1'h0, entries_ex_0_bits_deps_st_0} + {1'h0, entries_ex_0_bits_deps_st_1}; // @[ReservationStation.scala:118:23, :514:67] wire [1:0] _pop_count_packed_deps_T_487 = _pop_count_packed_deps_T_486; // @[ReservationStation.scala:514:67] wire [1:0] _pop_count_packed_deps_T_488 = {1'h0, entries_ex_0_bits_deps_st_2} + {1'h0, entries_ex_0_bits_deps_st_3}; // @[ReservationStation.scala:118:23, :514:67] wire [1:0] _pop_count_packed_deps_T_489 = _pop_count_packed_deps_T_488; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_490 = {1'h0, _pop_count_packed_deps_T_487} + {1'h0, _pop_count_packed_deps_T_489}; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_491 = _pop_count_packed_deps_T_490; // @[ReservationStation.scala:514:67] wire [5:0] _pop_count_packed_deps_T_492 = {1'h0, _pop_count_packed_deps_T_485} + {3'h0, _pop_count_packed_deps_T_491}; // @[ReservationStation.scala:514:{30,57,67}] wire [4:0] _pop_count_packed_deps_T_493 = _pop_count_packed_deps_T_492[4:0]; // @[ReservationStation.scala:514:57] wire [4:0] _pop_count_packed_deps_T_494 = entries_ex_0_valid ? _pop_count_packed_deps_T_493 : 5'h0; // @[ReservationStation.scala:118:23, :513:59, :514:57] wire [4:0] pop_count_packed_deps_8 = _pop_count_packed_deps_T_494; // @[ReservationStation.scala:513:{38,59}] wire [1:0] _pop_count_packed_deps_T_495 = {1'h0, entries_ex_1_bits_deps_ld_0} + {1'h0, entries_ex_1_bits_deps_ld_1}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_496 = _pop_count_packed_deps_T_495; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_497 = {1'h0, entries_ex_1_bits_deps_ld_2} + {1'h0, entries_ex_1_bits_deps_ld_3}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_498 = _pop_count_packed_deps_T_497; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_499 = {1'h0, _pop_count_packed_deps_T_496} + {1'h0, _pop_count_packed_deps_T_498}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_500 = _pop_count_packed_deps_T_499; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_501 = {1'h0, entries_ex_1_bits_deps_ld_4} + {1'h0, entries_ex_1_bits_deps_ld_5}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_502 = _pop_count_packed_deps_T_501; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_503 = {1'h0, entries_ex_1_bits_deps_ld_6} + {1'h0, entries_ex_1_bits_deps_ld_7}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_504 = _pop_count_packed_deps_T_503; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_505 = {1'h0, _pop_count_packed_deps_T_502} + {1'h0, _pop_count_packed_deps_T_504}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_506 = _pop_count_packed_deps_T_505; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_507 = {1'h0, _pop_count_packed_deps_T_500} + {1'h0, _pop_count_packed_deps_T_506}; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_508 = _pop_count_packed_deps_T_507; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_509 = {1'h0, entries_ex_1_bits_deps_ex_0} + {1'h0, entries_ex_1_bits_deps_ex_1}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_510 = _pop_count_packed_deps_T_509; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_511 = {1'h0, entries_ex_1_bits_deps_ex_2} + {1'h0, entries_ex_1_bits_deps_ex_3}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_512 = _pop_count_packed_deps_T_511; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_513 = {1'h0, _pop_count_packed_deps_T_510} + {1'h0, _pop_count_packed_deps_T_512}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_514 = _pop_count_packed_deps_T_513; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_515 = {1'h0, entries_ex_1_bits_deps_ex_4} + {1'h0, entries_ex_1_bits_deps_ex_5}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_516 = _pop_count_packed_deps_T_515; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_517 = {1'h0, entries_ex_1_bits_deps_ex_6} + {1'h0, entries_ex_1_bits_deps_ex_7}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_518 = _pop_count_packed_deps_T_517; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_519 = {1'h0, _pop_count_packed_deps_T_516} + {1'h0, _pop_count_packed_deps_T_518}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_520 = _pop_count_packed_deps_T_519; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_521 = {1'h0, _pop_count_packed_deps_T_514} + {1'h0, _pop_count_packed_deps_T_520}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_522 = _pop_count_packed_deps_T_521; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_523 = {1'h0, entries_ex_1_bits_deps_ex_8} + {1'h0, entries_ex_1_bits_deps_ex_9}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_524 = _pop_count_packed_deps_T_523; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_525 = {1'h0, entries_ex_1_bits_deps_ex_10} + {1'h0, entries_ex_1_bits_deps_ex_11}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_526 = _pop_count_packed_deps_T_525; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_527 = {1'h0, _pop_count_packed_deps_T_524} + {1'h0, _pop_count_packed_deps_T_526}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_528 = _pop_count_packed_deps_T_527; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_529 = {1'h0, entries_ex_1_bits_deps_ex_12} + {1'h0, entries_ex_1_bits_deps_ex_13}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_530 = _pop_count_packed_deps_T_529; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_531 = {1'h0, entries_ex_1_bits_deps_ex_14} + {1'h0, entries_ex_1_bits_deps_ex_15}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_532 = _pop_count_packed_deps_T_531; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_533 = {1'h0, _pop_count_packed_deps_T_530} + {1'h0, _pop_count_packed_deps_T_532}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_534 = _pop_count_packed_deps_T_533; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_535 = {1'h0, _pop_count_packed_deps_T_528} + {1'h0, _pop_count_packed_deps_T_534}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_536 = _pop_count_packed_deps_T_535; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_537 = {1'h0, _pop_count_packed_deps_T_522} + {1'h0, _pop_count_packed_deps_T_536}; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_538 = _pop_count_packed_deps_T_537; // @[ReservationStation.scala:514:40] wire [5:0] _pop_count_packed_deps_T_539 = {2'h0, _pop_count_packed_deps_T_508} + {1'h0, _pop_count_packed_deps_T_538}; // @[ReservationStation.scala:514:{13,30,40}] wire [4:0] _pop_count_packed_deps_T_540 = _pop_count_packed_deps_T_539[4:0]; // @[ReservationStation.scala:514:30] wire [1:0] _pop_count_packed_deps_T_541 = {1'h0, entries_ex_1_bits_deps_st_0} + {1'h0, entries_ex_1_bits_deps_st_1}; // @[ReservationStation.scala:118:23, :514:67] wire [1:0] _pop_count_packed_deps_T_542 = _pop_count_packed_deps_T_541; // @[ReservationStation.scala:514:67] wire [1:0] _pop_count_packed_deps_T_543 = {1'h0, entries_ex_1_bits_deps_st_2} + {1'h0, entries_ex_1_bits_deps_st_3}; // @[ReservationStation.scala:118:23, :514:67] wire [1:0] _pop_count_packed_deps_T_544 = _pop_count_packed_deps_T_543; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_545 = {1'h0, _pop_count_packed_deps_T_542} + {1'h0, _pop_count_packed_deps_T_544}; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_546 = _pop_count_packed_deps_T_545; // @[ReservationStation.scala:514:67] wire [5:0] _pop_count_packed_deps_T_547 = {1'h0, _pop_count_packed_deps_T_540} + {3'h0, _pop_count_packed_deps_T_546}; // @[ReservationStation.scala:514:{30,57,67}] wire [4:0] _pop_count_packed_deps_T_548 = _pop_count_packed_deps_T_547[4:0]; // @[ReservationStation.scala:514:57] wire [4:0] _pop_count_packed_deps_T_549 = entries_ex_1_valid ? _pop_count_packed_deps_T_548 : 5'h0; // @[ReservationStation.scala:118:23, :513:59, :514:57] wire [4:0] pop_count_packed_deps_9 = _pop_count_packed_deps_T_549; // @[ReservationStation.scala:513:{38,59}] wire [1:0] _pop_count_packed_deps_T_550 = {1'h0, entries_ex_2_bits_deps_ld_0} + {1'h0, entries_ex_2_bits_deps_ld_1}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_551 = _pop_count_packed_deps_T_550; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_552 = {1'h0, entries_ex_2_bits_deps_ld_2} + {1'h0, entries_ex_2_bits_deps_ld_3}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_553 = _pop_count_packed_deps_T_552; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_554 = {1'h0, _pop_count_packed_deps_T_551} + {1'h0, _pop_count_packed_deps_T_553}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_555 = _pop_count_packed_deps_T_554; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_556 = {1'h0, entries_ex_2_bits_deps_ld_4} + {1'h0, entries_ex_2_bits_deps_ld_5}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_557 = _pop_count_packed_deps_T_556; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_558 = {1'h0, entries_ex_2_bits_deps_ld_6} + {1'h0, entries_ex_2_bits_deps_ld_7}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_559 = _pop_count_packed_deps_T_558; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_560 = {1'h0, _pop_count_packed_deps_T_557} + {1'h0, _pop_count_packed_deps_T_559}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_561 = _pop_count_packed_deps_T_560; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_562 = {1'h0, _pop_count_packed_deps_T_555} + {1'h0, _pop_count_packed_deps_T_561}; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_563 = _pop_count_packed_deps_T_562; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_564 = {1'h0, entries_ex_2_bits_deps_ex_0} + {1'h0, entries_ex_2_bits_deps_ex_1}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_565 = _pop_count_packed_deps_T_564; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_566 = {1'h0, entries_ex_2_bits_deps_ex_2} + {1'h0, entries_ex_2_bits_deps_ex_3}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_567 = _pop_count_packed_deps_T_566; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_568 = {1'h0, _pop_count_packed_deps_T_565} + {1'h0, _pop_count_packed_deps_T_567}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_569 = _pop_count_packed_deps_T_568; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_570 = {1'h0, entries_ex_2_bits_deps_ex_4} + {1'h0, entries_ex_2_bits_deps_ex_5}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_571 = _pop_count_packed_deps_T_570; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_572 = {1'h0, entries_ex_2_bits_deps_ex_6} + {1'h0, entries_ex_2_bits_deps_ex_7}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_573 = _pop_count_packed_deps_T_572; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_574 = {1'h0, _pop_count_packed_deps_T_571} + {1'h0, _pop_count_packed_deps_T_573}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_575 = _pop_count_packed_deps_T_574; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_576 = {1'h0, _pop_count_packed_deps_T_569} + {1'h0, _pop_count_packed_deps_T_575}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_577 = _pop_count_packed_deps_T_576; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_578 = {1'h0, entries_ex_2_bits_deps_ex_8} + {1'h0, entries_ex_2_bits_deps_ex_9}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_579 = _pop_count_packed_deps_T_578; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_580 = {1'h0, entries_ex_2_bits_deps_ex_10} + {1'h0, entries_ex_2_bits_deps_ex_11}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_581 = _pop_count_packed_deps_T_580; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_582 = {1'h0, _pop_count_packed_deps_T_579} + {1'h0, _pop_count_packed_deps_T_581}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_583 = _pop_count_packed_deps_T_582; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_584 = {1'h0, entries_ex_2_bits_deps_ex_12} + {1'h0, entries_ex_2_bits_deps_ex_13}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_585 = _pop_count_packed_deps_T_584; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_586 = {1'h0, entries_ex_2_bits_deps_ex_14} + {1'h0, entries_ex_2_bits_deps_ex_15}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_587 = _pop_count_packed_deps_T_586; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_588 = {1'h0, _pop_count_packed_deps_T_585} + {1'h0, _pop_count_packed_deps_T_587}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_589 = _pop_count_packed_deps_T_588; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_590 = {1'h0, _pop_count_packed_deps_T_583} + {1'h0, _pop_count_packed_deps_T_589}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_591 = _pop_count_packed_deps_T_590; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_592 = {1'h0, _pop_count_packed_deps_T_577} + {1'h0, _pop_count_packed_deps_T_591}; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_593 = _pop_count_packed_deps_T_592; // @[ReservationStation.scala:514:40] wire [5:0] _pop_count_packed_deps_T_594 = {2'h0, _pop_count_packed_deps_T_563} + {1'h0, _pop_count_packed_deps_T_593}; // @[ReservationStation.scala:514:{13,30,40}] wire [4:0] _pop_count_packed_deps_T_595 = _pop_count_packed_deps_T_594[4:0]; // @[ReservationStation.scala:514:30] wire [1:0] _pop_count_packed_deps_T_596 = {1'h0, entries_ex_2_bits_deps_st_0} + {1'h0, entries_ex_2_bits_deps_st_1}; // @[ReservationStation.scala:118:23, :514:67] wire [1:0] _pop_count_packed_deps_T_597 = _pop_count_packed_deps_T_596; // @[ReservationStation.scala:514:67] wire [1:0] _pop_count_packed_deps_T_598 = {1'h0, entries_ex_2_bits_deps_st_2} + {1'h0, entries_ex_2_bits_deps_st_3}; // @[ReservationStation.scala:118:23, :514:67] wire [1:0] _pop_count_packed_deps_T_599 = _pop_count_packed_deps_T_598; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_600 = {1'h0, _pop_count_packed_deps_T_597} + {1'h0, _pop_count_packed_deps_T_599}; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_601 = _pop_count_packed_deps_T_600; // @[ReservationStation.scala:514:67] wire [5:0] _pop_count_packed_deps_T_602 = {1'h0, _pop_count_packed_deps_T_595} + {3'h0, _pop_count_packed_deps_T_601}; // @[ReservationStation.scala:514:{30,57,67}] wire [4:0] _pop_count_packed_deps_T_603 = _pop_count_packed_deps_T_602[4:0]; // @[ReservationStation.scala:514:57] wire [4:0] _pop_count_packed_deps_T_604 = entries_ex_2_valid ? _pop_count_packed_deps_T_603 : 5'h0; // @[ReservationStation.scala:118:23, :513:59, :514:57] wire [4:0] pop_count_packed_deps_10 = _pop_count_packed_deps_T_604; // @[ReservationStation.scala:513:{38,59}] wire [1:0] _pop_count_packed_deps_T_605 = {1'h0, entries_ex_3_bits_deps_ld_0} + {1'h0, entries_ex_3_bits_deps_ld_1}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_606 = _pop_count_packed_deps_T_605; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_607 = {1'h0, entries_ex_3_bits_deps_ld_2} + {1'h0, entries_ex_3_bits_deps_ld_3}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_608 = _pop_count_packed_deps_T_607; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_609 = {1'h0, _pop_count_packed_deps_T_606} + {1'h0, _pop_count_packed_deps_T_608}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_610 = _pop_count_packed_deps_T_609; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_611 = {1'h0, entries_ex_3_bits_deps_ld_4} + {1'h0, entries_ex_3_bits_deps_ld_5}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_612 = _pop_count_packed_deps_T_611; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_613 = {1'h0, entries_ex_3_bits_deps_ld_6} + {1'h0, entries_ex_3_bits_deps_ld_7}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_614 = _pop_count_packed_deps_T_613; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_615 = {1'h0, _pop_count_packed_deps_T_612} + {1'h0, _pop_count_packed_deps_T_614}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_616 = _pop_count_packed_deps_T_615; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_617 = {1'h0, _pop_count_packed_deps_T_610} + {1'h0, _pop_count_packed_deps_T_616}; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_618 = _pop_count_packed_deps_T_617; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_619 = {1'h0, entries_ex_3_bits_deps_ex_0} + {1'h0, entries_ex_3_bits_deps_ex_1}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_620 = _pop_count_packed_deps_T_619; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_621 = {1'h0, entries_ex_3_bits_deps_ex_2} + {1'h0, entries_ex_3_bits_deps_ex_3}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_622 = _pop_count_packed_deps_T_621; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_623 = {1'h0, _pop_count_packed_deps_T_620} + {1'h0, _pop_count_packed_deps_T_622}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_624 = _pop_count_packed_deps_T_623; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_625 = {1'h0, entries_ex_3_bits_deps_ex_4} + {1'h0, entries_ex_3_bits_deps_ex_5}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_626 = _pop_count_packed_deps_T_625; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_627 = {1'h0, entries_ex_3_bits_deps_ex_6} + {1'h0, entries_ex_3_bits_deps_ex_7}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_628 = _pop_count_packed_deps_T_627; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_629 = {1'h0, _pop_count_packed_deps_T_626} + {1'h0, _pop_count_packed_deps_T_628}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_630 = _pop_count_packed_deps_T_629; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_631 = {1'h0, _pop_count_packed_deps_T_624} + {1'h0, _pop_count_packed_deps_T_630}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_632 = _pop_count_packed_deps_T_631; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_633 = {1'h0, entries_ex_3_bits_deps_ex_8} + {1'h0, entries_ex_3_bits_deps_ex_9}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_634 = _pop_count_packed_deps_T_633; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_635 = {1'h0, entries_ex_3_bits_deps_ex_10} + {1'h0, entries_ex_3_bits_deps_ex_11}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_636 = _pop_count_packed_deps_T_635; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_637 = {1'h0, _pop_count_packed_deps_T_634} + {1'h0, _pop_count_packed_deps_T_636}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_638 = _pop_count_packed_deps_T_637; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_639 = {1'h0, entries_ex_3_bits_deps_ex_12} + {1'h0, entries_ex_3_bits_deps_ex_13}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_640 = _pop_count_packed_deps_T_639; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_641 = {1'h0, entries_ex_3_bits_deps_ex_14} + {1'h0, entries_ex_3_bits_deps_ex_15}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_642 = _pop_count_packed_deps_T_641; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_643 = {1'h0, _pop_count_packed_deps_T_640} + {1'h0, _pop_count_packed_deps_T_642}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_644 = _pop_count_packed_deps_T_643; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_645 = {1'h0, _pop_count_packed_deps_T_638} + {1'h0, _pop_count_packed_deps_T_644}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_646 = _pop_count_packed_deps_T_645; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_647 = {1'h0, _pop_count_packed_deps_T_632} + {1'h0, _pop_count_packed_deps_T_646}; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_648 = _pop_count_packed_deps_T_647; // @[ReservationStation.scala:514:40] wire [5:0] _pop_count_packed_deps_T_649 = {2'h0, _pop_count_packed_deps_T_618} + {1'h0, _pop_count_packed_deps_T_648}; // @[ReservationStation.scala:514:{13,30,40}] wire [4:0] _pop_count_packed_deps_T_650 = _pop_count_packed_deps_T_649[4:0]; // @[ReservationStation.scala:514:30] wire [1:0] _pop_count_packed_deps_T_651 = {1'h0, entries_ex_3_bits_deps_st_0} + {1'h0, entries_ex_3_bits_deps_st_1}; // @[ReservationStation.scala:118:23, :514:67] wire [1:0] _pop_count_packed_deps_T_652 = _pop_count_packed_deps_T_651; // @[ReservationStation.scala:514:67] wire [1:0] _pop_count_packed_deps_T_653 = {1'h0, entries_ex_3_bits_deps_st_2} + {1'h0, entries_ex_3_bits_deps_st_3}; // @[ReservationStation.scala:118:23, :514:67] wire [1:0] _pop_count_packed_deps_T_654 = _pop_count_packed_deps_T_653; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_655 = {1'h0, _pop_count_packed_deps_T_652} + {1'h0, _pop_count_packed_deps_T_654}; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_656 = _pop_count_packed_deps_T_655; // @[ReservationStation.scala:514:67] wire [5:0] _pop_count_packed_deps_T_657 = {1'h0, _pop_count_packed_deps_T_650} + {3'h0, _pop_count_packed_deps_T_656}; // @[ReservationStation.scala:514:{30,57,67}] wire [4:0] _pop_count_packed_deps_T_658 = _pop_count_packed_deps_T_657[4:0]; // @[ReservationStation.scala:514:57] wire [4:0] _pop_count_packed_deps_T_659 = entries_ex_3_valid ? _pop_count_packed_deps_T_658 : 5'h0; // @[ReservationStation.scala:118:23, :513:59, :514:57] wire [4:0] pop_count_packed_deps_11 = _pop_count_packed_deps_T_659; // @[ReservationStation.scala:513:{38,59}] wire [1:0] _pop_count_packed_deps_T_660 = {1'h0, entries_ex_4_bits_deps_ld_0} + {1'h0, entries_ex_4_bits_deps_ld_1}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_661 = _pop_count_packed_deps_T_660; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_662 = {1'h0, entries_ex_4_bits_deps_ld_2} + {1'h0, entries_ex_4_bits_deps_ld_3}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_663 = _pop_count_packed_deps_T_662; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_664 = {1'h0, _pop_count_packed_deps_T_661} + {1'h0, _pop_count_packed_deps_T_663}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_665 = _pop_count_packed_deps_T_664; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_666 = {1'h0, entries_ex_4_bits_deps_ld_4} + {1'h0, entries_ex_4_bits_deps_ld_5}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_667 = _pop_count_packed_deps_T_666; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_668 = {1'h0, entries_ex_4_bits_deps_ld_6} + {1'h0, entries_ex_4_bits_deps_ld_7}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_669 = _pop_count_packed_deps_T_668; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_670 = {1'h0, _pop_count_packed_deps_T_667} + {1'h0, _pop_count_packed_deps_T_669}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_671 = _pop_count_packed_deps_T_670; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_672 = {1'h0, _pop_count_packed_deps_T_665} + {1'h0, _pop_count_packed_deps_T_671}; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_673 = _pop_count_packed_deps_T_672; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_674 = {1'h0, entries_ex_4_bits_deps_ex_0} + {1'h0, entries_ex_4_bits_deps_ex_1}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_675 = _pop_count_packed_deps_T_674; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_676 = {1'h0, entries_ex_4_bits_deps_ex_2} + {1'h0, entries_ex_4_bits_deps_ex_3}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_677 = _pop_count_packed_deps_T_676; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_678 = {1'h0, _pop_count_packed_deps_T_675} + {1'h0, _pop_count_packed_deps_T_677}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_679 = _pop_count_packed_deps_T_678; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_680 = {1'h0, entries_ex_4_bits_deps_ex_4} + {1'h0, entries_ex_4_bits_deps_ex_5}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_681 = _pop_count_packed_deps_T_680; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_682 = {1'h0, entries_ex_4_bits_deps_ex_6} + {1'h0, entries_ex_4_bits_deps_ex_7}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_683 = _pop_count_packed_deps_T_682; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_684 = {1'h0, _pop_count_packed_deps_T_681} + {1'h0, _pop_count_packed_deps_T_683}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_685 = _pop_count_packed_deps_T_684; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_686 = {1'h0, _pop_count_packed_deps_T_679} + {1'h0, _pop_count_packed_deps_T_685}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_687 = _pop_count_packed_deps_T_686; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_688 = {1'h0, entries_ex_4_bits_deps_ex_8} + {1'h0, entries_ex_4_bits_deps_ex_9}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_689 = _pop_count_packed_deps_T_688; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_690 = {1'h0, entries_ex_4_bits_deps_ex_10} + {1'h0, entries_ex_4_bits_deps_ex_11}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_691 = _pop_count_packed_deps_T_690; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_692 = {1'h0, _pop_count_packed_deps_T_689} + {1'h0, _pop_count_packed_deps_T_691}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_693 = _pop_count_packed_deps_T_692; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_694 = {1'h0, entries_ex_4_bits_deps_ex_12} + {1'h0, entries_ex_4_bits_deps_ex_13}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_695 = _pop_count_packed_deps_T_694; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_696 = {1'h0, entries_ex_4_bits_deps_ex_14} + {1'h0, entries_ex_4_bits_deps_ex_15}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_697 = _pop_count_packed_deps_T_696; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_698 = {1'h0, _pop_count_packed_deps_T_695} + {1'h0, _pop_count_packed_deps_T_697}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_699 = _pop_count_packed_deps_T_698; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_700 = {1'h0, _pop_count_packed_deps_T_693} + {1'h0, _pop_count_packed_deps_T_699}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_701 = _pop_count_packed_deps_T_700; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_702 = {1'h0, _pop_count_packed_deps_T_687} + {1'h0, _pop_count_packed_deps_T_701}; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_703 = _pop_count_packed_deps_T_702; // @[ReservationStation.scala:514:40] wire [5:0] _pop_count_packed_deps_T_704 = {2'h0, _pop_count_packed_deps_T_673} + {1'h0, _pop_count_packed_deps_T_703}; // @[ReservationStation.scala:514:{13,30,40}] wire [4:0] _pop_count_packed_deps_T_705 = _pop_count_packed_deps_T_704[4:0]; // @[ReservationStation.scala:514:30] wire [1:0] _pop_count_packed_deps_T_706 = {1'h0, entries_ex_4_bits_deps_st_0} + {1'h0, entries_ex_4_bits_deps_st_1}; // @[ReservationStation.scala:118:23, :514:67] wire [1:0] _pop_count_packed_deps_T_707 = _pop_count_packed_deps_T_706; // @[ReservationStation.scala:514:67] wire [1:0] _pop_count_packed_deps_T_708 = {1'h0, entries_ex_4_bits_deps_st_2} + {1'h0, entries_ex_4_bits_deps_st_3}; // @[ReservationStation.scala:118:23, :514:67] wire [1:0] _pop_count_packed_deps_T_709 = _pop_count_packed_deps_T_708; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_710 = {1'h0, _pop_count_packed_deps_T_707} + {1'h0, _pop_count_packed_deps_T_709}; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_711 = _pop_count_packed_deps_T_710; // @[ReservationStation.scala:514:67] wire [5:0] _pop_count_packed_deps_T_712 = {1'h0, _pop_count_packed_deps_T_705} + {3'h0, _pop_count_packed_deps_T_711}; // @[ReservationStation.scala:514:{30,57,67}] wire [4:0] _pop_count_packed_deps_T_713 = _pop_count_packed_deps_T_712[4:0]; // @[ReservationStation.scala:514:57] wire [4:0] _pop_count_packed_deps_T_714 = entries_ex_4_valid ? _pop_count_packed_deps_T_713 : 5'h0; // @[ReservationStation.scala:118:23, :513:59, :514:57] wire [4:0] pop_count_packed_deps_12 = _pop_count_packed_deps_T_714; // @[ReservationStation.scala:513:{38,59}] wire [1:0] _pop_count_packed_deps_T_715 = {1'h0, entries_ex_5_bits_deps_ld_0} + {1'h0, entries_ex_5_bits_deps_ld_1}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_716 = _pop_count_packed_deps_T_715; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_717 = {1'h0, entries_ex_5_bits_deps_ld_2} + {1'h0, entries_ex_5_bits_deps_ld_3}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_718 = _pop_count_packed_deps_T_717; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_719 = {1'h0, _pop_count_packed_deps_T_716} + {1'h0, _pop_count_packed_deps_T_718}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_720 = _pop_count_packed_deps_T_719; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_721 = {1'h0, entries_ex_5_bits_deps_ld_4} + {1'h0, entries_ex_5_bits_deps_ld_5}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_722 = _pop_count_packed_deps_T_721; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_723 = {1'h0, entries_ex_5_bits_deps_ld_6} + {1'h0, entries_ex_5_bits_deps_ld_7}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_724 = _pop_count_packed_deps_T_723; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_725 = {1'h0, _pop_count_packed_deps_T_722} + {1'h0, _pop_count_packed_deps_T_724}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_726 = _pop_count_packed_deps_T_725; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_727 = {1'h0, _pop_count_packed_deps_T_720} + {1'h0, _pop_count_packed_deps_T_726}; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_728 = _pop_count_packed_deps_T_727; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_729 = {1'h0, entries_ex_5_bits_deps_ex_0} + {1'h0, entries_ex_5_bits_deps_ex_1}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_730 = _pop_count_packed_deps_T_729; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_731 = {1'h0, entries_ex_5_bits_deps_ex_2} + {1'h0, entries_ex_5_bits_deps_ex_3}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_732 = _pop_count_packed_deps_T_731; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_733 = {1'h0, _pop_count_packed_deps_T_730} + {1'h0, _pop_count_packed_deps_T_732}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_734 = _pop_count_packed_deps_T_733; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_735 = {1'h0, entries_ex_5_bits_deps_ex_4} + {1'h0, entries_ex_5_bits_deps_ex_5}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_736 = _pop_count_packed_deps_T_735; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_737 = {1'h0, entries_ex_5_bits_deps_ex_6} + {1'h0, entries_ex_5_bits_deps_ex_7}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_738 = _pop_count_packed_deps_T_737; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_739 = {1'h0, _pop_count_packed_deps_T_736} + {1'h0, _pop_count_packed_deps_T_738}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_740 = _pop_count_packed_deps_T_739; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_741 = {1'h0, _pop_count_packed_deps_T_734} + {1'h0, _pop_count_packed_deps_T_740}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_742 = _pop_count_packed_deps_T_741; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_743 = {1'h0, entries_ex_5_bits_deps_ex_8} + {1'h0, entries_ex_5_bits_deps_ex_9}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_744 = _pop_count_packed_deps_T_743; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_745 = {1'h0, entries_ex_5_bits_deps_ex_10} + {1'h0, entries_ex_5_bits_deps_ex_11}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_746 = _pop_count_packed_deps_T_745; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_747 = {1'h0, _pop_count_packed_deps_T_744} + {1'h0, _pop_count_packed_deps_T_746}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_748 = _pop_count_packed_deps_T_747; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_749 = {1'h0, entries_ex_5_bits_deps_ex_12} + {1'h0, entries_ex_5_bits_deps_ex_13}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_750 = _pop_count_packed_deps_T_749; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_751 = {1'h0, entries_ex_5_bits_deps_ex_14} + {1'h0, entries_ex_5_bits_deps_ex_15}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_752 = _pop_count_packed_deps_T_751; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_753 = {1'h0, _pop_count_packed_deps_T_750} + {1'h0, _pop_count_packed_deps_T_752}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_754 = _pop_count_packed_deps_T_753; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_755 = {1'h0, _pop_count_packed_deps_T_748} + {1'h0, _pop_count_packed_deps_T_754}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_756 = _pop_count_packed_deps_T_755; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_757 = {1'h0, _pop_count_packed_deps_T_742} + {1'h0, _pop_count_packed_deps_T_756}; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_758 = _pop_count_packed_deps_T_757; // @[ReservationStation.scala:514:40] wire [5:0] _pop_count_packed_deps_T_759 = {2'h0, _pop_count_packed_deps_T_728} + {1'h0, _pop_count_packed_deps_T_758}; // @[ReservationStation.scala:514:{13,30,40}] wire [4:0] _pop_count_packed_deps_T_760 = _pop_count_packed_deps_T_759[4:0]; // @[ReservationStation.scala:514:30] wire [1:0] _pop_count_packed_deps_T_761 = {1'h0, entries_ex_5_bits_deps_st_0} + {1'h0, entries_ex_5_bits_deps_st_1}; // @[ReservationStation.scala:118:23, :514:67] wire [1:0] _pop_count_packed_deps_T_762 = _pop_count_packed_deps_T_761; // @[ReservationStation.scala:514:67] wire [1:0] _pop_count_packed_deps_T_763 = {1'h0, entries_ex_5_bits_deps_st_2} + {1'h0, entries_ex_5_bits_deps_st_3}; // @[ReservationStation.scala:118:23, :514:67] wire [1:0] _pop_count_packed_deps_T_764 = _pop_count_packed_deps_T_763; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_765 = {1'h0, _pop_count_packed_deps_T_762} + {1'h0, _pop_count_packed_deps_T_764}; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_766 = _pop_count_packed_deps_T_765; // @[ReservationStation.scala:514:67] wire [5:0] _pop_count_packed_deps_T_767 = {1'h0, _pop_count_packed_deps_T_760} + {3'h0, _pop_count_packed_deps_T_766}; // @[ReservationStation.scala:514:{30,57,67}] wire [4:0] _pop_count_packed_deps_T_768 = _pop_count_packed_deps_T_767[4:0]; // @[ReservationStation.scala:514:57] wire [4:0] _pop_count_packed_deps_T_769 = entries_ex_5_valid ? _pop_count_packed_deps_T_768 : 5'h0; // @[ReservationStation.scala:118:23, :513:59, :514:57] wire [4:0] pop_count_packed_deps_13 = _pop_count_packed_deps_T_769; // @[ReservationStation.scala:513:{38,59}] wire [1:0] _pop_count_packed_deps_T_770 = {1'h0, entries_ex_6_bits_deps_ld_0} + {1'h0, entries_ex_6_bits_deps_ld_1}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_771 = _pop_count_packed_deps_T_770; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_772 = {1'h0, entries_ex_6_bits_deps_ld_2} + {1'h0, entries_ex_6_bits_deps_ld_3}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_773 = _pop_count_packed_deps_T_772; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_774 = {1'h0, _pop_count_packed_deps_T_771} + {1'h0, _pop_count_packed_deps_T_773}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_775 = _pop_count_packed_deps_T_774; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_776 = {1'h0, entries_ex_6_bits_deps_ld_4} + {1'h0, entries_ex_6_bits_deps_ld_5}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_777 = _pop_count_packed_deps_T_776; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_778 = {1'h0, entries_ex_6_bits_deps_ld_6} + {1'h0, entries_ex_6_bits_deps_ld_7}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_779 = _pop_count_packed_deps_T_778; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_780 = {1'h0, _pop_count_packed_deps_T_777} + {1'h0, _pop_count_packed_deps_T_779}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_781 = _pop_count_packed_deps_T_780; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_782 = {1'h0, _pop_count_packed_deps_T_775} + {1'h0, _pop_count_packed_deps_T_781}; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_783 = _pop_count_packed_deps_T_782; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_784 = {1'h0, entries_ex_6_bits_deps_ex_0} + {1'h0, entries_ex_6_bits_deps_ex_1}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_785 = _pop_count_packed_deps_T_784; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_786 = {1'h0, entries_ex_6_bits_deps_ex_2} + {1'h0, entries_ex_6_bits_deps_ex_3}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_787 = _pop_count_packed_deps_T_786; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_788 = {1'h0, _pop_count_packed_deps_T_785} + {1'h0, _pop_count_packed_deps_T_787}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_789 = _pop_count_packed_deps_T_788; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_790 = {1'h0, entries_ex_6_bits_deps_ex_4} + {1'h0, entries_ex_6_bits_deps_ex_5}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_791 = _pop_count_packed_deps_T_790; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_792 = {1'h0, entries_ex_6_bits_deps_ex_6} + {1'h0, entries_ex_6_bits_deps_ex_7}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_793 = _pop_count_packed_deps_T_792; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_794 = {1'h0, _pop_count_packed_deps_T_791} + {1'h0, _pop_count_packed_deps_T_793}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_795 = _pop_count_packed_deps_T_794; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_796 = {1'h0, _pop_count_packed_deps_T_789} + {1'h0, _pop_count_packed_deps_T_795}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_797 = _pop_count_packed_deps_T_796; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_798 = {1'h0, entries_ex_6_bits_deps_ex_8} + {1'h0, entries_ex_6_bits_deps_ex_9}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_799 = _pop_count_packed_deps_T_798; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_800 = {1'h0, entries_ex_6_bits_deps_ex_10} + {1'h0, entries_ex_6_bits_deps_ex_11}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_801 = _pop_count_packed_deps_T_800; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_802 = {1'h0, _pop_count_packed_deps_T_799} + {1'h0, _pop_count_packed_deps_T_801}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_803 = _pop_count_packed_deps_T_802; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_804 = {1'h0, entries_ex_6_bits_deps_ex_12} + {1'h0, entries_ex_6_bits_deps_ex_13}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_805 = _pop_count_packed_deps_T_804; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_806 = {1'h0, entries_ex_6_bits_deps_ex_14} + {1'h0, entries_ex_6_bits_deps_ex_15}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_807 = _pop_count_packed_deps_T_806; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_808 = {1'h0, _pop_count_packed_deps_T_805} + {1'h0, _pop_count_packed_deps_T_807}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_809 = _pop_count_packed_deps_T_808; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_810 = {1'h0, _pop_count_packed_deps_T_803} + {1'h0, _pop_count_packed_deps_T_809}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_811 = _pop_count_packed_deps_T_810; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_812 = {1'h0, _pop_count_packed_deps_T_797} + {1'h0, _pop_count_packed_deps_T_811}; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_813 = _pop_count_packed_deps_T_812; // @[ReservationStation.scala:514:40] wire [5:0] _pop_count_packed_deps_T_814 = {2'h0, _pop_count_packed_deps_T_783} + {1'h0, _pop_count_packed_deps_T_813}; // @[ReservationStation.scala:514:{13,30,40}] wire [4:0] _pop_count_packed_deps_T_815 = _pop_count_packed_deps_T_814[4:0]; // @[ReservationStation.scala:514:30] wire [1:0] _pop_count_packed_deps_T_816 = {1'h0, entries_ex_6_bits_deps_st_0} + {1'h0, entries_ex_6_bits_deps_st_1}; // @[ReservationStation.scala:118:23, :514:67] wire [1:0] _pop_count_packed_deps_T_817 = _pop_count_packed_deps_T_816; // @[ReservationStation.scala:514:67] wire [1:0] _pop_count_packed_deps_T_818 = {1'h0, entries_ex_6_bits_deps_st_2} + {1'h0, entries_ex_6_bits_deps_st_3}; // @[ReservationStation.scala:118:23, :514:67] wire [1:0] _pop_count_packed_deps_T_819 = _pop_count_packed_deps_T_818; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_820 = {1'h0, _pop_count_packed_deps_T_817} + {1'h0, _pop_count_packed_deps_T_819}; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_821 = _pop_count_packed_deps_T_820; // @[ReservationStation.scala:514:67] wire [5:0] _pop_count_packed_deps_T_822 = {1'h0, _pop_count_packed_deps_T_815} + {3'h0, _pop_count_packed_deps_T_821}; // @[ReservationStation.scala:514:{30,57,67}] wire [4:0] _pop_count_packed_deps_T_823 = _pop_count_packed_deps_T_822[4:0]; // @[ReservationStation.scala:514:57] wire [4:0] _pop_count_packed_deps_T_824 = entries_ex_6_valid ? _pop_count_packed_deps_T_823 : 5'h0; // @[ReservationStation.scala:118:23, :513:59, :514:57] wire [4:0] pop_count_packed_deps_14 = _pop_count_packed_deps_T_824; // @[ReservationStation.scala:513:{38,59}] wire [1:0] _pop_count_packed_deps_T_825 = {1'h0, entries_ex_7_bits_deps_ld_0} + {1'h0, entries_ex_7_bits_deps_ld_1}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_826 = _pop_count_packed_deps_T_825; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_827 = {1'h0, entries_ex_7_bits_deps_ld_2} + {1'h0, entries_ex_7_bits_deps_ld_3}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_828 = _pop_count_packed_deps_T_827; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_829 = {1'h0, _pop_count_packed_deps_T_826} + {1'h0, _pop_count_packed_deps_T_828}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_830 = _pop_count_packed_deps_T_829; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_831 = {1'h0, entries_ex_7_bits_deps_ld_4} + {1'h0, entries_ex_7_bits_deps_ld_5}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_832 = _pop_count_packed_deps_T_831; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_833 = {1'h0, entries_ex_7_bits_deps_ld_6} + {1'h0, entries_ex_7_bits_deps_ld_7}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_834 = _pop_count_packed_deps_T_833; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_835 = {1'h0, _pop_count_packed_deps_T_832} + {1'h0, _pop_count_packed_deps_T_834}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_836 = _pop_count_packed_deps_T_835; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_837 = {1'h0, _pop_count_packed_deps_T_830} + {1'h0, _pop_count_packed_deps_T_836}; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_838 = _pop_count_packed_deps_T_837; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_839 = {1'h0, entries_ex_7_bits_deps_ex_0} + {1'h0, entries_ex_7_bits_deps_ex_1}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_840 = _pop_count_packed_deps_T_839; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_841 = {1'h0, entries_ex_7_bits_deps_ex_2} + {1'h0, entries_ex_7_bits_deps_ex_3}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_842 = _pop_count_packed_deps_T_841; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_843 = {1'h0, _pop_count_packed_deps_T_840} + {1'h0, _pop_count_packed_deps_T_842}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_844 = _pop_count_packed_deps_T_843; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_845 = {1'h0, entries_ex_7_bits_deps_ex_4} + {1'h0, entries_ex_7_bits_deps_ex_5}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_846 = _pop_count_packed_deps_T_845; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_847 = {1'h0, entries_ex_7_bits_deps_ex_6} + {1'h0, entries_ex_7_bits_deps_ex_7}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_848 = _pop_count_packed_deps_T_847; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_849 = {1'h0, _pop_count_packed_deps_T_846} + {1'h0, _pop_count_packed_deps_T_848}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_850 = _pop_count_packed_deps_T_849; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_851 = {1'h0, _pop_count_packed_deps_T_844} + {1'h0, _pop_count_packed_deps_T_850}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_852 = _pop_count_packed_deps_T_851; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_853 = {1'h0, entries_ex_7_bits_deps_ex_8} + {1'h0, entries_ex_7_bits_deps_ex_9}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_854 = _pop_count_packed_deps_T_853; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_855 = {1'h0, entries_ex_7_bits_deps_ex_10} + {1'h0, entries_ex_7_bits_deps_ex_11}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_856 = _pop_count_packed_deps_T_855; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_857 = {1'h0, _pop_count_packed_deps_T_854} + {1'h0, _pop_count_packed_deps_T_856}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_858 = _pop_count_packed_deps_T_857; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_859 = {1'h0, entries_ex_7_bits_deps_ex_12} + {1'h0, entries_ex_7_bits_deps_ex_13}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_860 = _pop_count_packed_deps_T_859; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_861 = {1'h0, entries_ex_7_bits_deps_ex_14} + {1'h0, entries_ex_7_bits_deps_ex_15}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_862 = _pop_count_packed_deps_T_861; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_863 = {1'h0, _pop_count_packed_deps_T_860} + {1'h0, _pop_count_packed_deps_T_862}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_864 = _pop_count_packed_deps_T_863; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_865 = {1'h0, _pop_count_packed_deps_T_858} + {1'h0, _pop_count_packed_deps_T_864}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_866 = _pop_count_packed_deps_T_865; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_867 = {1'h0, _pop_count_packed_deps_T_852} + {1'h0, _pop_count_packed_deps_T_866}; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_868 = _pop_count_packed_deps_T_867; // @[ReservationStation.scala:514:40] wire [5:0] _pop_count_packed_deps_T_869 = {2'h0, _pop_count_packed_deps_T_838} + {1'h0, _pop_count_packed_deps_T_868}; // @[ReservationStation.scala:514:{13,30,40}] wire [4:0] _pop_count_packed_deps_T_870 = _pop_count_packed_deps_T_869[4:0]; // @[ReservationStation.scala:514:30] wire [1:0] _pop_count_packed_deps_T_871 = {1'h0, entries_ex_7_bits_deps_st_0} + {1'h0, entries_ex_7_bits_deps_st_1}; // @[ReservationStation.scala:118:23, :514:67] wire [1:0] _pop_count_packed_deps_T_872 = _pop_count_packed_deps_T_871; // @[ReservationStation.scala:514:67] wire [1:0] _pop_count_packed_deps_T_873 = {1'h0, entries_ex_7_bits_deps_st_2} + {1'h0, entries_ex_7_bits_deps_st_3}; // @[ReservationStation.scala:118:23, :514:67] wire [1:0] _pop_count_packed_deps_T_874 = _pop_count_packed_deps_T_873; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_875 = {1'h0, _pop_count_packed_deps_T_872} + {1'h0, _pop_count_packed_deps_T_874}; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_876 = _pop_count_packed_deps_T_875; // @[ReservationStation.scala:514:67] wire [5:0] _pop_count_packed_deps_T_877 = {1'h0, _pop_count_packed_deps_T_870} + {3'h0, _pop_count_packed_deps_T_876}; // @[ReservationStation.scala:514:{30,57,67}] wire [4:0] _pop_count_packed_deps_T_878 = _pop_count_packed_deps_T_877[4:0]; // @[ReservationStation.scala:514:57] wire [4:0] _pop_count_packed_deps_T_879 = entries_ex_7_valid ? _pop_count_packed_deps_T_878 : 5'h0; // @[ReservationStation.scala:118:23, :513:59, :514:57] wire [4:0] pop_count_packed_deps_15 = _pop_count_packed_deps_T_879; // @[ReservationStation.scala:513:{38,59}] wire [1:0] _pop_count_packed_deps_T_880 = {1'h0, entries_ex_8_bits_deps_ld_0} + {1'h0, entries_ex_8_bits_deps_ld_1}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_881 = _pop_count_packed_deps_T_880; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_882 = {1'h0, entries_ex_8_bits_deps_ld_2} + {1'h0, entries_ex_8_bits_deps_ld_3}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_883 = _pop_count_packed_deps_T_882; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_884 = {1'h0, _pop_count_packed_deps_T_881} + {1'h0, _pop_count_packed_deps_T_883}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_885 = _pop_count_packed_deps_T_884; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_886 = {1'h0, entries_ex_8_bits_deps_ld_4} + {1'h0, entries_ex_8_bits_deps_ld_5}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_887 = _pop_count_packed_deps_T_886; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_888 = {1'h0, entries_ex_8_bits_deps_ld_6} + {1'h0, entries_ex_8_bits_deps_ld_7}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_889 = _pop_count_packed_deps_T_888; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_890 = {1'h0, _pop_count_packed_deps_T_887} + {1'h0, _pop_count_packed_deps_T_889}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_891 = _pop_count_packed_deps_T_890; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_892 = {1'h0, _pop_count_packed_deps_T_885} + {1'h0, _pop_count_packed_deps_T_891}; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_893 = _pop_count_packed_deps_T_892; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_894 = {1'h0, entries_ex_8_bits_deps_ex_0} + {1'h0, entries_ex_8_bits_deps_ex_1}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_895 = _pop_count_packed_deps_T_894; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_896 = {1'h0, entries_ex_8_bits_deps_ex_2} + {1'h0, entries_ex_8_bits_deps_ex_3}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_897 = _pop_count_packed_deps_T_896; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_898 = {1'h0, _pop_count_packed_deps_T_895} + {1'h0, _pop_count_packed_deps_T_897}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_899 = _pop_count_packed_deps_T_898; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_900 = {1'h0, entries_ex_8_bits_deps_ex_4} + {1'h0, entries_ex_8_bits_deps_ex_5}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_901 = _pop_count_packed_deps_T_900; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_902 = {1'h0, entries_ex_8_bits_deps_ex_6} + {1'h0, entries_ex_8_bits_deps_ex_7}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_903 = _pop_count_packed_deps_T_902; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_904 = {1'h0, _pop_count_packed_deps_T_901} + {1'h0, _pop_count_packed_deps_T_903}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_905 = _pop_count_packed_deps_T_904; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_906 = {1'h0, _pop_count_packed_deps_T_899} + {1'h0, _pop_count_packed_deps_T_905}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_907 = _pop_count_packed_deps_T_906; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_908 = {1'h0, entries_ex_8_bits_deps_ex_8} + {1'h0, entries_ex_8_bits_deps_ex_9}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_909 = _pop_count_packed_deps_T_908; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_910 = {1'h0, entries_ex_8_bits_deps_ex_10} + {1'h0, entries_ex_8_bits_deps_ex_11}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_911 = _pop_count_packed_deps_T_910; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_912 = {1'h0, _pop_count_packed_deps_T_909} + {1'h0, _pop_count_packed_deps_T_911}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_913 = _pop_count_packed_deps_T_912; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_914 = {1'h0, entries_ex_8_bits_deps_ex_12} + {1'h0, entries_ex_8_bits_deps_ex_13}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_915 = _pop_count_packed_deps_T_914; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_916 = {1'h0, entries_ex_8_bits_deps_ex_14} + {1'h0, entries_ex_8_bits_deps_ex_15}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_917 = _pop_count_packed_deps_T_916; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_918 = {1'h0, _pop_count_packed_deps_T_915} + {1'h0, _pop_count_packed_deps_T_917}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_919 = _pop_count_packed_deps_T_918; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_920 = {1'h0, _pop_count_packed_deps_T_913} + {1'h0, _pop_count_packed_deps_T_919}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_921 = _pop_count_packed_deps_T_920; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_922 = {1'h0, _pop_count_packed_deps_T_907} + {1'h0, _pop_count_packed_deps_T_921}; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_923 = _pop_count_packed_deps_T_922; // @[ReservationStation.scala:514:40] wire [5:0] _pop_count_packed_deps_T_924 = {2'h0, _pop_count_packed_deps_T_893} + {1'h0, _pop_count_packed_deps_T_923}; // @[ReservationStation.scala:514:{13,30,40}] wire [4:0] _pop_count_packed_deps_T_925 = _pop_count_packed_deps_T_924[4:0]; // @[ReservationStation.scala:514:30] wire [1:0] _pop_count_packed_deps_T_926 = {1'h0, entries_ex_8_bits_deps_st_0} + {1'h0, entries_ex_8_bits_deps_st_1}; // @[ReservationStation.scala:118:23, :514:67] wire [1:0] _pop_count_packed_deps_T_927 = _pop_count_packed_deps_T_926; // @[ReservationStation.scala:514:67] wire [1:0] _pop_count_packed_deps_T_928 = {1'h0, entries_ex_8_bits_deps_st_2} + {1'h0, entries_ex_8_bits_deps_st_3}; // @[ReservationStation.scala:118:23, :514:67] wire [1:0] _pop_count_packed_deps_T_929 = _pop_count_packed_deps_T_928; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_930 = {1'h0, _pop_count_packed_deps_T_927} + {1'h0, _pop_count_packed_deps_T_929}; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_931 = _pop_count_packed_deps_T_930; // @[ReservationStation.scala:514:67] wire [5:0] _pop_count_packed_deps_T_932 = {1'h0, _pop_count_packed_deps_T_925} + {3'h0, _pop_count_packed_deps_T_931}; // @[ReservationStation.scala:514:{30,57,67}] wire [4:0] _pop_count_packed_deps_T_933 = _pop_count_packed_deps_T_932[4:0]; // @[ReservationStation.scala:514:57] wire [4:0] _pop_count_packed_deps_T_934 = entries_ex_8_valid ? _pop_count_packed_deps_T_933 : 5'h0; // @[ReservationStation.scala:118:23, :513:59, :514:57] wire [4:0] pop_count_packed_deps_16 = _pop_count_packed_deps_T_934; // @[ReservationStation.scala:513:{38,59}] wire [1:0] _pop_count_packed_deps_T_935 = {1'h0, entries_ex_9_bits_deps_ld_0} + {1'h0, entries_ex_9_bits_deps_ld_1}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_936 = _pop_count_packed_deps_T_935; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_937 = {1'h0, entries_ex_9_bits_deps_ld_2} + {1'h0, entries_ex_9_bits_deps_ld_3}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_938 = _pop_count_packed_deps_T_937; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_939 = {1'h0, _pop_count_packed_deps_T_936} + {1'h0, _pop_count_packed_deps_T_938}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_940 = _pop_count_packed_deps_T_939; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_941 = {1'h0, entries_ex_9_bits_deps_ld_4} + {1'h0, entries_ex_9_bits_deps_ld_5}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_942 = _pop_count_packed_deps_T_941; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_943 = {1'h0, entries_ex_9_bits_deps_ld_6} + {1'h0, entries_ex_9_bits_deps_ld_7}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_944 = _pop_count_packed_deps_T_943; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_945 = {1'h0, _pop_count_packed_deps_T_942} + {1'h0, _pop_count_packed_deps_T_944}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_946 = _pop_count_packed_deps_T_945; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_947 = {1'h0, _pop_count_packed_deps_T_940} + {1'h0, _pop_count_packed_deps_T_946}; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_948 = _pop_count_packed_deps_T_947; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_949 = {1'h0, entries_ex_9_bits_deps_ex_0} + {1'h0, entries_ex_9_bits_deps_ex_1}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_950 = _pop_count_packed_deps_T_949; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_951 = {1'h0, entries_ex_9_bits_deps_ex_2} + {1'h0, entries_ex_9_bits_deps_ex_3}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_952 = _pop_count_packed_deps_T_951; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_953 = {1'h0, _pop_count_packed_deps_T_950} + {1'h0, _pop_count_packed_deps_T_952}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_954 = _pop_count_packed_deps_T_953; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_955 = {1'h0, entries_ex_9_bits_deps_ex_4} + {1'h0, entries_ex_9_bits_deps_ex_5}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_956 = _pop_count_packed_deps_T_955; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_957 = {1'h0, entries_ex_9_bits_deps_ex_6} + {1'h0, entries_ex_9_bits_deps_ex_7}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_958 = _pop_count_packed_deps_T_957; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_959 = {1'h0, _pop_count_packed_deps_T_956} + {1'h0, _pop_count_packed_deps_T_958}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_960 = _pop_count_packed_deps_T_959; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_961 = {1'h0, _pop_count_packed_deps_T_954} + {1'h0, _pop_count_packed_deps_T_960}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_962 = _pop_count_packed_deps_T_961; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_963 = {1'h0, entries_ex_9_bits_deps_ex_8} + {1'h0, entries_ex_9_bits_deps_ex_9}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_964 = _pop_count_packed_deps_T_963; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_965 = {1'h0, entries_ex_9_bits_deps_ex_10} + {1'h0, entries_ex_9_bits_deps_ex_11}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_966 = _pop_count_packed_deps_T_965; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_967 = {1'h0, _pop_count_packed_deps_T_964} + {1'h0, _pop_count_packed_deps_T_966}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_968 = _pop_count_packed_deps_T_967; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_969 = {1'h0, entries_ex_9_bits_deps_ex_12} + {1'h0, entries_ex_9_bits_deps_ex_13}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_970 = _pop_count_packed_deps_T_969; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_971 = {1'h0, entries_ex_9_bits_deps_ex_14} + {1'h0, entries_ex_9_bits_deps_ex_15}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_972 = _pop_count_packed_deps_T_971; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_973 = {1'h0, _pop_count_packed_deps_T_970} + {1'h0, _pop_count_packed_deps_T_972}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_974 = _pop_count_packed_deps_T_973; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_975 = {1'h0, _pop_count_packed_deps_T_968} + {1'h0, _pop_count_packed_deps_T_974}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_976 = _pop_count_packed_deps_T_975; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_977 = {1'h0, _pop_count_packed_deps_T_962} + {1'h0, _pop_count_packed_deps_T_976}; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_978 = _pop_count_packed_deps_T_977; // @[ReservationStation.scala:514:40] wire [5:0] _pop_count_packed_deps_T_979 = {2'h0, _pop_count_packed_deps_T_948} + {1'h0, _pop_count_packed_deps_T_978}; // @[ReservationStation.scala:514:{13,30,40}] wire [4:0] _pop_count_packed_deps_T_980 = _pop_count_packed_deps_T_979[4:0]; // @[ReservationStation.scala:514:30] wire [1:0] _pop_count_packed_deps_T_981 = {1'h0, entries_ex_9_bits_deps_st_0} + {1'h0, entries_ex_9_bits_deps_st_1}; // @[ReservationStation.scala:118:23, :514:67] wire [1:0] _pop_count_packed_deps_T_982 = _pop_count_packed_deps_T_981; // @[ReservationStation.scala:514:67] wire [1:0] _pop_count_packed_deps_T_983 = {1'h0, entries_ex_9_bits_deps_st_2} + {1'h0, entries_ex_9_bits_deps_st_3}; // @[ReservationStation.scala:118:23, :514:67] wire [1:0] _pop_count_packed_deps_T_984 = _pop_count_packed_deps_T_983; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_985 = {1'h0, _pop_count_packed_deps_T_982} + {1'h0, _pop_count_packed_deps_T_984}; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_986 = _pop_count_packed_deps_T_985; // @[ReservationStation.scala:514:67] wire [5:0] _pop_count_packed_deps_T_987 = {1'h0, _pop_count_packed_deps_T_980} + {3'h0, _pop_count_packed_deps_T_986}; // @[ReservationStation.scala:514:{30,57,67}] wire [4:0] _pop_count_packed_deps_T_988 = _pop_count_packed_deps_T_987[4:0]; // @[ReservationStation.scala:514:57] wire [4:0] _pop_count_packed_deps_T_989 = entries_ex_9_valid ? _pop_count_packed_deps_T_988 : 5'h0; // @[ReservationStation.scala:118:23, :513:59, :514:57] wire [4:0] pop_count_packed_deps_17 = _pop_count_packed_deps_T_989; // @[ReservationStation.scala:513:{38,59}] wire [1:0] _pop_count_packed_deps_T_990 = {1'h0, entries_ex_10_bits_deps_ld_0} + {1'h0, entries_ex_10_bits_deps_ld_1}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_991 = _pop_count_packed_deps_T_990; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_992 = {1'h0, entries_ex_10_bits_deps_ld_2} + {1'h0, entries_ex_10_bits_deps_ld_3}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_993 = _pop_count_packed_deps_T_992; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_994 = {1'h0, _pop_count_packed_deps_T_991} + {1'h0, _pop_count_packed_deps_T_993}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_995 = _pop_count_packed_deps_T_994; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_996 = {1'h0, entries_ex_10_bits_deps_ld_4} + {1'h0, entries_ex_10_bits_deps_ld_5}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_997 = _pop_count_packed_deps_T_996; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_998 = {1'h0, entries_ex_10_bits_deps_ld_6} + {1'h0, entries_ex_10_bits_deps_ld_7}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_999 = _pop_count_packed_deps_T_998; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_1000 = {1'h0, _pop_count_packed_deps_T_997} + {1'h0, _pop_count_packed_deps_T_999}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_1001 = _pop_count_packed_deps_T_1000; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_1002 = {1'h0, _pop_count_packed_deps_T_995} + {1'h0, _pop_count_packed_deps_T_1001}; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_1003 = _pop_count_packed_deps_T_1002; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_1004 = {1'h0, entries_ex_10_bits_deps_ex_0} + {1'h0, entries_ex_10_bits_deps_ex_1}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1005 = _pop_count_packed_deps_T_1004; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1006 = {1'h0, entries_ex_10_bits_deps_ex_2} + {1'h0, entries_ex_10_bits_deps_ex_3}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1007 = _pop_count_packed_deps_T_1006; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1008 = {1'h0, _pop_count_packed_deps_T_1005} + {1'h0, _pop_count_packed_deps_T_1007}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1009 = _pop_count_packed_deps_T_1008; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1010 = {1'h0, entries_ex_10_bits_deps_ex_4} + {1'h0, entries_ex_10_bits_deps_ex_5}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1011 = _pop_count_packed_deps_T_1010; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1012 = {1'h0, entries_ex_10_bits_deps_ex_6} + {1'h0, entries_ex_10_bits_deps_ex_7}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1013 = _pop_count_packed_deps_T_1012; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1014 = {1'h0, _pop_count_packed_deps_T_1011} + {1'h0, _pop_count_packed_deps_T_1013}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1015 = _pop_count_packed_deps_T_1014; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_1016 = {1'h0, _pop_count_packed_deps_T_1009} + {1'h0, _pop_count_packed_deps_T_1015}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_1017 = _pop_count_packed_deps_T_1016; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1018 = {1'h0, entries_ex_10_bits_deps_ex_8} + {1'h0, entries_ex_10_bits_deps_ex_9}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1019 = _pop_count_packed_deps_T_1018; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1020 = {1'h0, entries_ex_10_bits_deps_ex_10} + {1'h0, entries_ex_10_bits_deps_ex_11}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1021 = _pop_count_packed_deps_T_1020; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1022 = {1'h0, _pop_count_packed_deps_T_1019} + {1'h0, _pop_count_packed_deps_T_1021}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1023 = _pop_count_packed_deps_T_1022; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1024 = {1'h0, entries_ex_10_bits_deps_ex_12} + {1'h0, entries_ex_10_bits_deps_ex_13}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1025 = _pop_count_packed_deps_T_1024; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1026 = {1'h0, entries_ex_10_bits_deps_ex_14} + {1'h0, entries_ex_10_bits_deps_ex_15}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1027 = _pop_count_packed_deps_T_1026; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1028 = {1'h0, _pop_count_packed_deps_T_1025} + {1'h0, _pop_count_packed_deps_T_1027}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1029 = _pop_count_packed_deps_T_1028; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_1030 = {1'h0, _pop_count_packed_deps_T_1023} + {1'h0, _pop_count_packed_deps_T_1029}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_1031 = _pop_count_packed_deps_T_1030; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_1032 = {1'h0, _pop_count_packed_deps_T_1017} + {1'h0, _pop_count_packed_deps_T_1031}; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_1033 = _pop_count_packed_deps_T_1032; // @[ReservationStation.scala:514:40] wire [5:0] _pop_count_packed_deps_T_1034 = {2'h0, _pop_count_packed_deps_T_1003} + {1'h0, _pop_count_packed_deps_T_1033}; // @[ReservationStation.scala:514:{13,30,40}] wire [4:0] _pop_count_packed_deps_T_1035 = _pop_count_packed_deps_T_1034[4:0]; // @[ReservationStation.scala:514:30] wire [1:0] _pop_count_packed_deps_T_1036 = {1'h0, entries_ex_10_bits_deps_st_0} + {1'h0, entries_ex_10_bits_deps_st_1}; // @[ReservationStation.scala:118:23, :514:67] wire [1:0] _pop_count_packed_deps_T_1037 = _pop_count_packed_deps_T_1036; // @[ReservationStation.scala:514:67] wire [1:0] _pop_count_packed_deps_T_1038 = {1'h0, entries_ex_10_bits_deps_st_2} + {1'h0, entries_ex_10_bits_deps_st_3}; // @[ReservationStation.scala:118:23, :514:67] wire [1:0] _pop_count_packed_deps_T_1039 = _pop_count_packed_deps_T_1038; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_1040 = {1'h0, _pop_count_packed_deps_T_1037} + {1'h0, _pop_count_packed_deps_T_1039}; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_1041 = _pop_count_packed_deps_T_1040; // @[ReservationStation.scala:514:67] wire [5:0] _pop_count_packed_deps_T_1042 = {1'h0, _pop_count_packed_deps_T_1035} + {3'h0, _pop_count_packed_deps_T_1041}; // @[ReservationStation.scala:514:{30,57,67}] wire [4:0] _pop_count_packed_deps_T_1043 = _pop_count_packed_deps_T_1042[4:0]; // @[ReservationStation.scala:514:57] wire [4:0] _pop_count_packed_deps_T_1044 = entries_ex_10_valid ? _pop_count_packed_deps_T_1043 : 5'h0; // @[ReservationStation.scala:118:23, :513:59, :514:57] wire [4:0] pop_count_packed_deps_18 = _pop_count_packed_deps_T_1044; // @[ReservationStation.scala:513:{38,59}] wire [1:0] _pop_count_packed_deps_T_1045 = {1'h0, entries_ex_11_bits_deps_ld_0} + {1'h0, entries_ex_11_bits_deps_ld_1}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_1046 = _pop_count_packed_deps_T_1045; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_1047 = {1'h0, entries_ex_11_bits_deps_ld_2} + {1'h0, entries_ex_11_bits_deps_ld_3}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_1048 = _pop_count_packed_deps_T_1047; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_1049 = {1'h0, _pop_count_packed_deps_T_1046} + {1'h0, _pop_count_packed_deps_T_1048}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_1050 = _pop_count_packed_deps_T_1049; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_1051 = {1'h0, entries_ex_11_bits_deps_ld_4} + {1'h0, entries_ex_11_bits_deps_ld_5}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_1052 = _pop_count_packed_deps_T_1051; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_1053 = {1'h0, entries_ex_11_bits_deps_ld_6} + {1'h0, entries_ex_11_bits_deps_ld_7}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_1054 = _pop_count_packed_deps_T_1053; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_1055 = {1'h0, _pop_count_packed_deps_T_1052} + {1'h0, _pop_count_packed_deps_T_1054}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_1056 = _pop_count_packed_deps_T_1055; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_1057 = {1'h0, _pop_count_packed_deps_T_1050} + {1'h0, _pop_count_packed_deps_T_1056}; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_1058 = _pop_count_packed_deps_T_1057; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_1059 = {1'h0, entries_ex_11_bits_deps_ex_0} + {1'h0, entries_ex_11_bits_deps_ex_1}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1060 = _pop_count_packed_deps_T_1059; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1061 = {1'h0, entries_ex_11_bits_deps_ex_2} + {1'h0, entries_ex_11_bits_deps_ex_3}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1062 = _pop_count_packed_deps_T_1061; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1063 = {1'h0, _pop_count_packed_deps_T_1060} + {1'h0, _pop_count_packed_deps_T_1062}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1064 = _pop_count_packed_deps_T_1063; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1065 = {1'h0, entries_ex_11_bits_deps_ex_4} + {1'h0, entries_ex_11_bits_deps_ex_5}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1066 = _pop_count_packed_deps_T_1065; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1067 = {1'h0, entries_ex_11_bits_deps_ex_6} + {1'h0, entries_ex_11_bits_deps_ex_7}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1068 = _pop_count_packed_deps_T_1067; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1069 = {1'h0, _pop_count_packed_deps_T_1066} + {1'h0, _pop_count_packed_deps_T_1068}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1070 = _pop_count_packed_deps_T_1069; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_1071 = {1'h0, _pop_count_packed_deps_T_1064} + {1'h0, _pop_count_packed_deps_T_1070}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_1072 = _pop_count_packed_deps_T_1071; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1073 = {1'h0, entries_ex_11_bits_deps_ex_8} + {1'h0, entries_ex_11_bits_deps_ex_9}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1074 = _pop_count_packed_deps_T_1073; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1075 = {1'h0, entries_ex_11_bits_deps_ex_10} + {1'h0, entries_ex_11_bits_deps_ex_11}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1076 = _pop_count_packed_deps_T_1075; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1077 = {1'h0, _pop_count_packed_deps_T_1074} + {1'h0, _pop_count_packed_deps_T_1076}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1078 = _pop_count_packed_deps_T_1077; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1079 = {1'h0, entries_ex_11_bits_deps_ex_12} + {1'h0, entries_ex_11_bits_deps_ex_13}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1080 = _pop_count_packed_deps_T_1079; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1081 = {1'h0, entries_ex_11_bits_deps_ex_14} + {1'h0, entries_ex_11_bits_deps_ex_15}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1082 = _pop_count_packed_deps_T_1081; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1083 = {1'h0, _pop_count_packed_deps_T_1080} + {1'h0, _pop_count_packed_deps_T_1082}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1084 = _pop_count_packed_deps_T_1083; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_1085 = {1'h0, _pop_count_packed_deps_T_1078} + {1'h0, _pop_count_packed_deps_T_1084}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_1086 = _pop_count_packed_deps_T_1085; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_1087 = {1'h0, _pop_count_packed_deps_T_1072} + {1'h0, _pop_count_packed_deps_T_1086}; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_1088 = _pop_count_packed_deps_T_1087; // @[ReservationStation.scala:514:40] wire [5:0] _pop_count_packed_deps_T_1089 = {2'h0, _pop_count_packed_deps_T_1058} + {1'h0, _pop_count_packed_deps_T_1088}; // @[ReservationStation.scala:514:{13,30,40}] wire [4:0] _pop_count_packed_deps_T_1090 = _pop_count_packed_deps_T_1089[4:0]; // @[ReservationStation.scala:514:30] wire [1:0] _pop_count_packed_deps_T_1091 = {1'h0, entries_ex_11_bits_deps_st_0} + {1'h0, entries_ex_11_bits_deps_st_1}; // @[ReservationStation.scala:118:23, :514:67] wire [1:0] _pop_count_packed_deps_T_1092 = _pop_count_packed_deps_T_1091; // @[ReservationStation.scala:514:67] wire [1:0] _pop_count_packed_deps_T_1093 = {1'h0, entries_ex_11_bits_deps_st_2} + {1'h0, entries_ex_11_bits_deps_st_3}; // @[ReservationStation.scala:118:23, :514:67] wire [1:0] _pop_count_packed_deps_T_1094 = _pop_count_packed_deps_T_1093; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_1095 = {1'h0, _pop_count_packed_deps_T_1092} + {1'h0, _pop_count_packed_deps_T_1094}; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_1096 = _pop_count_packed_deps_T_1095; // @[ReservationStation.scala:514:67] wire [5:0] _pop_count_packed_deps_T_1097 = {1'h0, _pop_count_packed_deps_T_1090} + {3'h0, _pop_count_packed_deps_T_1096}; // @[ReservationStation.scala:514:{30,57,67}] wire [4:0] _pop_count_packed_deps_T_1098 = _pop_count_packed_deps_T_1097[4:0]; // @[ReservationStation.scala:514:57] wire [4:0] _pop_count_packed_deps_T_1099 = entries_ex_11_valid ? _pop_count_packed_deps_T_1098 : 5'h0; // @[ReservationStation.scala:118:23, :513:59, :514:57] wire [4:0] pop_count_packed_deps_19 = _pop_count_packed_deps_T_1099; // @[ReservationStation.scala:513:{38,59}] wire [1:0] _pop_count_packed_deps_T_1100 = {1'h0, entries_ex_12_bits_deps_ld_0} + {1'h0, entries_ex_12_bits_deps_ld_1}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_1101 = _pop_count_packed_deps_T_1100; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_1102 = {1'h0, entries_ex_12_bits_deps_ld_2} + {1'h0, entries_ex_12_bits_deps_ld_3}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_1103 = _pop_count_packed_deps_T_1102; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_1104 = {1'h0, _pop_count_packed_deps_T_1101} + {1'h0, _pop_count_packed_deps_T_1103}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_1105 = _pop_count_packed_deps_T_1104; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_1106 = {1'h0, entries_ex_12_bits_deps_ld_4} + {1'h0, entries_ex_12_bits_deps_ld_5}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_1107 = _pop_count_packed_deps_T_1106; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_1108 = {1'h0, entries_ex_12_bits_deps_ld_6} + {1'h0, entries_ex_12_bits_deps_ld_7}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_1109 = _pop_count_packed_deps_T_1108; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_1110 = {1'h0, _pop_count_packed_deps_T_1107} + {1'h0, _pop_count_packed_deps_T_1109}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_1111 = _pop_count_packed_deps_T_1110; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_1112 = {1'h0, _pop_count_packed_deps_T_1105} + {1'h0, _pop_count_packed_deps_T_1111}; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_1113 = _pop_count_packed_deps_T_1112; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_1114 = {1'h0, entries_ex_12_bits_deps_ex_0} + {1'h0, entries_ex_12_bits_deps_ex_1}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1115 = _pop_count_packed_deps_T_1114; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1116 = {1'h0, entries_ex_12_bits_deps_ex_2} + {1'h0, entries_ex_12_bits_deps_ex_3}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1117 = _pop_count_packed_deps_T_1116; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1118 = {1'h0, _pop_count_packed_deps_T_1115} + {1'h0, _pop_count_packed_deps_T_1117}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1119 = _pop_count_packed_deps_T_1118; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1120 = {1'h0, entries_ex_12_bits_deps_ex_4} + {1'h0, entries_ex_12_bits_deps_ex_5}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1121 = _pop_count_packed_deps_T_1120; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1122 = {1'h0, entries_ex_12_bits_deps_ex_6} + {1'h0, entries_ex_12_bits_deps_ex_7}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1123 = _pop_count_packed_deps_T_1122; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1124 = {1'h0, _pop_count_packed_deps_T_1121} + {1'h0, _pop_count_packed_deps_T_1123}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1125 = _pop_count_packed_deps_T_1124; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_1126 = {1'h0, _pop_count_packed_deps_T_1119} + {1'h0, _pop_count_packed_deps_T_1125}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_1127 = _pop_count_packed_deps_T_1126; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1128 = {1'h0, entries_ex_12_bits_deps_ex_8} + {1'h0, entries_ex_12_bits_deps_ex_9}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1129 = _pop_count_packed_deps_T_1128; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1130 = {1'h0, entries_ex_12_bits_deps_ex_10} + {1'h0, entries_ex_12_bits_deps_ex_11}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1131 = _pop_count_packed_deps_T_1130; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1132 = {1'h0, _pop_count_packed_deps_T_1129} + {1'h0, _pop_count_packed_deps_T_1131}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1133 = _pop_count_packed_deps_T_1132; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1134 = {1'h0, entries_ex_12_bits_deps_ex_12} + {1'h0, entries_ex_12_bits_deps_ex_13}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1135 = _pop_count_packed_deps_T_1134; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1136 = {1'h0, entries_ex_12_bits_deps_ex_14} + {1'h0, entries_ex_12_bits_deps_ex_15}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1137 = _pop_count_packed_deps_T_1136; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1138 = {1'h0, _pop_count_packed_deps_T_1135} + {1'h0, _pop_count_packed_deps_T_1137}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1139 = _pop_count_packed_deps_T_1138; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_1140 = {1'h0, _pop_count_packed_deps_T_1133} + {1'h0, _pop_count_packed_deps_T_1139}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_1141 = _pop_count_packed_deps_T_1140; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_1142 = {1'h0, _pop_count_packed_deps_T_1127} + {1'h0, _pop_count_packed_deps_T_1141}; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_1143 = _pop_count_packed_deps_T_1142; // @[ReservationStation.scala:514:40] wire [5:0] _pop_count_packed_deps_T_1144 = {2'h0, _pop_count_packed_deps_T_1113} + {1'h0, _pop_count_packed_deps_T_1143}; // @[ReservationStation.scala:514:{13,30,40}] wire [4:0] _pop_count_packed_deps_T_1145 = _pop_count_packed_deps_T_1144[4:0]; // @[ReservationStation.scala:514:30] wire [1:0] _pop_count_packed_deps_T_1146 = {1'h0, entries_ex_12_bits_deps_st_0} + {1'h0, entries_ex_12_bits_deps_st_1}; // @[ReservationStation.scala:118:23, :514:67] wire [1:0] _pop_count_packed_deps_T_1147 = _pop_count_packed_deps_T_1146; // @[ReservationStation.scala:514:67] wire [1:0] _pop_count_packed_deps_T_1148 = {1'h0, entries_ex_12_bits_deps_st_2} + {1'h0, entries_ex_12_bits_deps_st_3}; // @[ReservationStation.scala:118:23, :514:67] wire [1:0] _pop_count_packed_deps_T_1149 = _pop_count_packed_deps_T_1148; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_1150 = {1'h0, _pop_count_packed_deps_T_1147} + {1'h0, _pop_count_packed_deps_T_1149}; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_1151 = _pop_count_packed_deps_T_1150; // @[ReservationStation.scala:514:67] wire [5:0] _pop_count_packed_deps_T_1152 = {1'h0, _pop_count_packed_deps_T_1145} + {3'h0, _pop_count_packed_deps_T_1151}; // @[ReservationStation.scala:514:{30,57,67}] wire [4:0] _pop_count_packed_deps_T_1153 = _pop_count_packed_deps_T_1152[4:0]; // @[ReservationStation.scala:514:57] wire [4:0] _pop_count_packed_deps_T_1154 = entries_ex_12_valid ? _pop_count_packed_deps_T_1153 : 5'h0; // @[ReservationStation.scala:118:23, :513:59, :514:57] wire [4:0] pop_count_packed_deps_20 = _pop_count_packed_deps_T_1154; // @[ReservationStation.scala:513:{38,59}] wire [1:0] _pop_count_packed_deps_T_1155 = {1'h0, entries_ex_13_bits_deps_ld_0} + {1'h0, entries_ex_13_bits_deps_ld_1}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_1156 = _pop_count_packed_deps_T_1155; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_1157 = {1'h0, entries_ex_13_bits_deps_ld_2} + {1'h0, entries_ex_13_bits_deps_ld_3}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_1158 = _pop_count_packed_deps_T_1157; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_1159 = {1'h0, _pop_count_packed_deps_T_1156} + {1'h0, _pop_count_packed_deps_T_1158}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_1160 = _pop_count_packed_deps_T_1159; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_1161 = {1'h0, entries_ex_13_bits_deps_ld_4} + {1'h0, entries_ex_13_bits_deps_ld_5}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_1162 = _pop_count_packed_deps_T_1161; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_1163 = {1'h0, entries_ex_13_bits_deps_ld_6} + {1'h0, entries_ex_13_bits_deps_ld_7}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_1164 = _pop_count_packed_deps_T_1163; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_1165 = {1'h0, _pop_count_packed_deps_T_1162} + {1'h0, _pop_count_packed_deps_T_1164}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_1166 = _pop_count_packed_deps_T_1165; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_1167 = {1'h0, _pop_count_packed_deps_T_1160} + {1'h0, _pop_count_packed_deps_T_1166}; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_1168 = _pop_count_packed_deps_T_1167; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_1169 = {1'h0, entries_ex_13_bits_deps_ex_0} + {1'h0, entries_ex_13_bits_deps_ex_1}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1170 = _pop_count_packed_deps_T_1169; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1171 = {1'h0, entries_ex_13_bits_deps_ex_2} + {1'h0, entries_ex_13_bits_deps_ex_3}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1172 = _pop_count_packed_deps_T_1171; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1173 = {1'h0, _pop_count_packed_deps_T_1170} + {1'h0, _pop_count_packed_deps_T_1172}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1174 = _pop_count_packed_deps_T_1173; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1175 = {1'h0, entries_ex_13_bits_deps_ex_4} + {1'h0, entries_ex_13_bits_deps_ex_5}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1176 = _pop_count_packed_deps_T_1175; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1177 = {1'h0, entries_ex_13_bits_deps_ex_6} + {1'h0, entries_ex_13_bits_deps_ex_7}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1178 = _pop_count_packed_deps_T_1177; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1179 = {1'h0, _pop_count_packed_deps_T_1176} + {1'h0, _pop_count_packed_deps_T_1178}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1180 = _pop_count_packed_deps_T_1179; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_1181 = {1'h0, _pop_count_packed_deps_T_1174} + {1'h0, _pop_count_packed_deps_T_1180}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_1182 = _pop_count_packed_deps_T_1181; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1183 = {1'h0, entries_ex_13_bits_deps_ex_8} + {1'h0, entries_ex_13_bits_deps_ex_9}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1184 = _pop_count_packed_deps_T_1183; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1185 = {1'h0, entries_ex_13_bits_deps_ex_10} + {1'h0, entries_ex_13_bits_deps_ex_11}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1186 = _pop_count_packed_deps_T_1185; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1187 = {1'h0, _pop_count_packed_deps_T_1184} + {1'h0, _pop_count_packed_deps_T_1186}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1188 = _pop_count_packed_deps_T_1187; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1189 = {1'h0, entries_ex_13_bits_deps_ex_12} + {1'h0, entries_ex_13_bits_deps_ex_13}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1190 = _pop_count_packed_deps_T_1189; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1191 = {1'h0, entries_ex_13_bits_deps_ex_14} + {1'h0, entries_ex_13_bits_deps_ex_15}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1192 = _pop_count_packed_deps_T_1191; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1193 = {1'h0, _pop_count_packed_deps_T_1190} + {1'h0, _pop_count_packed_deps_T_1192}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1194 = _pop_count_packed_deps_T_1193; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_1195 = {1'h0, _pop_count_packed_deps_T_1188} + {1'h0, _pop_count_packed_deps_T_1194}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_1196 = _pop_count_packed_deps_T_1195; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_1197 = {1'h0, _pop_count_packed_deps_T_1182} + {1'h0, _pop_count_packed_deps_T_1196}; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_1198 = _pop_count_packed_deps_T_1197; // @[ReservationStation.scala:514:40] wire [5:0] _pop_count_packed_deps_T_1199 = {2'h0, _pop_count_packed_deps_T_1168} + {1'h0, _pop_count_packed_deps_T_1198}; // @[ReservationStation.scala:514:{13,30,40}] wire [4:0] _pop_count_packed_deps_T_1200 = _pop_count_packed_deps_T_1199[4:0]; // @[ReservationStation.scala:514:30] wire [1:0] _pop_count_packed_deps_T_1201 = {1'h0, entries_ex_13_bits_deps_st_0} + {1'h0, entries_ex_13_bits_deps_st_1}; // @[ReservationStation.scala:118:23, :514:67] wire [1:0] _pop_count_packed_deps_T_1202 = _pop_count_packed_deps_T_1201; // @[ReservationStation.scala:514:67] wire [1:0] _pop_count_packed_deps_T_1203 = {1'h0, entries_ex_13_bits_deps_st_2} + {1'h0, entries_ex_13_bits_deps_st_3}; // @[ReservationStation.scala:118:23, :514:67] wire [1:0] _pop_count_packed_deps_T_1204 = _pop_count_packed_deps_T_1203; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_1205 = {1'h0, _pop_count_packed_deps_T_1202} + {1'h0, _pop_count_packed_deps_T_1204}; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_1206 = _pop_count_packed_deps_T_1205; // @[ReservationStation.scala:514:67] wire [5:0] _pop_count_packed_deps_T_1207 = {1'h0, _pop_count_packed_deps_T_1200} + {3'h0, _pop_count_packed_deps_T_1206}; // @[ReservationStation.scala:514:{30,57,67}] wire [4:0] _pop_count_packed_deps_T_1208 = _pop_count_packed_deps_T_1207[4:0]; // @[ReservationStation.scala:514:57] wire [4:0] _pop_count_packed_deps_T_1209 = entries_ex_13_valid ? _pop_count_packed_deps_T_1208 : 5'h0; // @[ReservationStation.scala:118:23, :513:59, :514:57] wire [4:0] pop_count_packed_deps_21 = _pop_count_packed_deps_T_1209; // @[ReservationStation.scala:513:{38,59}] wire [1:0] _pop_count_packed_deps_T_1210 = {1'h0, entries_ex_14_bits_deps_ld_0} + {1'h0, entries_ex_14_bits_deps_ld_1}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_1211 = _pop_count_packed_deps_T_1210; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_1212 = {1'h0, entries_ex_14_bits_deps_ld_2} + {1'h0, entries_ex_14_bits_deps_ld_3}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_1213 = _pop_count_packed_deps_T_1212; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_1214 = {1'h0, _pop_count_packed_deps_T_1211} + {1'h0, _pop_count_packed_deps_T_1213}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_1215 = _pop_count_packed_deps_T_1214; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_1216 = {1'h0, entries_ex_14_bits_deps_ld_4} + {1'h0, entries_ex_14_bits_deps_ld_5}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_1217 = _pop_count_packed_deps_T_1216; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_1218 = {1'h0, entries_ex_14_bits_deps_ld_6} + {1'h0, entries_ex_14_bits_deps_ld_7}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_1219 = _pop_count_packed_deps_T_1218; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_1220 = {1'h0, _pop_count_packed_deps_T_1217} + {1'h0, _pop_count_packed_deps_T_1219}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_1221 = _pop_count_packed_deps_T_1220; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_1222 = {1'h0, _pop_count_packed_deps_T_1215} + {1'h0, _pop_count_packed_deps_T_1221}; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_1223 = _pop_count_packed_deps_T_1222; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_1224 = {1'h0, entries_ex_14_bits_deps_ex_0} + {1'h0, entries_ex_14_bits_deps_ex_1}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1225 = _pop_count_packed_deps_T_1224; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1226 = {1'h0, entries_ex_14_bits_deps_ex_2} + {1'h0, entries_ex_14_bits_deps_ex_3}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1227 = _pop_count_packed_deps_T_1226; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1228 = {1'h0, _pop_count_packed_deps_T_1225} + {1'h0, _pop_count_packed_deps_T_1227}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1229 = _pop_count_packed_deps_T_1228; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1230 = {1'h0, entries_ex_14_bits_deps_ex_4} + {1'h0, entries_ex_14_bits_deps_ex_5}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1231 = _pop_count_packed_deps_T_1230; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1232 = {1'h0, entries_ex_14_bits_deps_ex_6} + {1'h0, entries_ex_14_bits_deps_ex_7}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1233 = _pop_count_packed_deps_T_1232; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1234 = {1'h0, _pop_count_packed_deps_T_1231} + {1'h0, _pop_count_packed_deps_T_1233}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1235 = _pop_count_packed_deps_T_1234; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_1236 = {1'h0, _pop_count_packed_deps_T_1229} + {1'h0, _pop_count_packed_deps_T_1235}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_1237 = _pop_count_packed_deps_T_1236; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1238 = {1'h0, entries_ex_14_bits_deps_ex_8} + {1'h0, entries_ex_14_bits_deps_ex_9}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1239 = _pop_count_packed_deps_T_1238; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1240 = {1'h0, entries_ex_14_bits_deps_ex_10} + {1'h0, entries_ex_14_bits_deps_ex_11}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1241 = _pop_count_packed_deps_T_1240; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1242 = {1'h0, _pop_count_packed_deps_T_1239} + {1'h0, _pop_count_packed_deps_T_1241}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1243 = _pop_count_packed_deps_T_1242; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1244 = {1'h0, entries_ex_14_bits_deps_ex_12} + {1'h0, entries_ex_14_bits_deps_ex_13}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1245 = _pop_count_packed_deps_T_1244; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1246 = {1'h0, entries_ex_14_bits_deps_ex_14} + {1'h0, entries_ex_14_bits_deps_ex_15}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1247 = _pop_count_packed_deps_T_1246; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1248 = {1'h0, _pop_count_packed_deps_T_1245} + {1'h0, _pop_count_packed_deps_T_1247}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1249 = _pop_count_packed_deps_T_1248; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_1250 = {1'h0, _pop_count_packed_deps_T_1243} + {1'h0, _pop_count_packed_deps_T_1249}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_1251 = _pop_count_packed_deps_T_1250; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_1252 = {1'h0, _pop_count_packed_deps_T_1237} + {1'h0, _pop_count_packed_deps_T_1251}; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_1253 = _pop_count_packed_deps_T_1252; // @[ReservationStation.scala:514:40] wire [5:0] _pop_count_packed_deps_T_1254 = {2'h0, _pop_count_packed_deps_T_1223} + {1'h0, _pop_count_packed_deps_T_1253}; // @[ReservationStation.scala:514:{13,30,40}] wire [4:0] _pop_count_packed_deps_T_1255 = _pop_count_packed_deps_T_1254[4:0]; // @[ReservationStation.scala:514:30] wire [1:0] _pop_count_packed_deps_T_1256 = {1'h0, entries_ex_14_bits_deps_st_0} + {1'h0, entries_ex_14_bits_deps_st_1}; // @[ReservationStation.scala:118:23, :514:67] wire [1:0] _pop_count_packed_deps_T_1257 = _pop_count_packed_deps_T_1256; // @[ReservationStation.scala:514:67] wire [1:0] _pop_count_packed_deps_T_1258 = {1'h0, entries_ex_14_bits_deps_st_2} + {1'h0, entries_ex_14_bits_deps_st_3}; // @[ReservationStation.scala:118:23, :514:67] wire [1:0] _pop_count_packed_deps_T_1259 = _pop_count_packed_deps_T_1258; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_1260 = {1'h0, _pop_count_packed_deps_T_1257} + {1'h0, _pop_count_packed_deps_T_1259}; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_1261 = _pop_count_packed_deps_T_1260; // @[ReservationStation.scala:514:67] wire [5:0] _pop_count_packed_deps_T_1262 = {1'h0, _pop_count_packed_deps_T_1255} + {3'h0, _pop_count_packed_deps_T_1261}; // @[ReservationStation.scala:514:{30,57,67}] wire [4:0] _pop_count_packed_deps_T_1263 = _pop_count_packed_deps_T_1262[4:0]; // @[ReservationStation.scala:514:57] wire [4:0] _pop_count_packed_deps_T_1264 = entries_ex_14_valid ? _pop_count_packed_deps_T_1263 : 5'h0; // @[ReservationStation.scala:118:23, :513:59, :514:57] wire [4:0] pop_count_packed_deps_22 = _pop_count_packed_deps_T_1264; // @[ReservationStation.scala:513:{38,59}] wire [1:0] _pop_count_packed_deps_T_1265 = {1'h0, entries_ex_15_bits_deps_ld_0} + {1'h0, entries_ex_15_bits_deps_ld_1}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_1266 = _pop_count_packed_deps_T_1265; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_1267 = {1'h0, entries_ex_15_bits_deps_ld_2} + {1'h0, entries_ex_15_bits_deps_ld_3}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_1268 = _pop_count_packed_deps_T_1267; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_1269 = {1'h0, _pop_count_packed_deps_T_1266} + {1'h0, _pop_count_packed_deps_T_1268}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_1270 = _pop_count_packed_deps_T_1269; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_1271 = {1'h0, entries_ex_15_bits_deps_ld_4} + {1'h0, entries_ex_15_bits_deps_ld_5}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_1272 = _pop_count_packed_deps_T_1271; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_1273 = {1'h0, entries_ex_15_bits_deps_ld_6} + {1'h0, entries_ex_15_bits_deps_ld_7}; // @[ReservationStation.scala:118:23, :514:13] wire [1:0] _pop_count_packed_deps_T_1274 = _pop_count_packed_deps_T_1273; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_1275 = {1'h0, _pop_count_packed_deps_T_1272} + {1'h0, _pop_count_packed_deps_T_1274}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_1276 = _pop_count_packed_deps_T_1275; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_1277 = {1'h0, _pop_count_packed_deps_T_1270} + {1'h0, _pop_count_packed_deps_T_1276}; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_1278 = _pop_count_packed_deps_T_1277; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_1279 = {1'h0, entries_ex_15_bits_deps_ex_0} + {1'h0, entries_ex_15_bits_deps_ex_1}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1280 = _pop_count_packed_deps_T_1279; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1281 = {1'h0, entries_ex_15_bits_deps_ex_2} + {1'h0, entries_ex_15_bits_deps_ex_3}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1282 = _pop_count_packed_deps_T_1281; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1283 = {1'h0, _pop_count_packed_deps_T_1280} + {1'h0, _pop_count_packed_deps_T_1282}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1284 = _pop_count_packed_deps_T_1283; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1285 = {1'h0, entries_ex_15_bits_deps_ex_4} + {1'h0, entries_ex_15_bits_deps_ex_5}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1286 = _pop_count_packed_deps_T_1285; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1287 = {1'h0, entries_ex_15_bits_deps_ex_6} + {1'h0, entries_ex_15_bits_deps_ex_7}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1288 = _pop_count_packed_deps_T_1287; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1289 = {1'h0, _pop_count_packed_deps_T_1286} + {1'h0, _pop_count_packed_deps_T_1288}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1290 = _pop_count_packed_deps_T_1289; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_1291 = {1'h0, _pop_count_packed_deps_T_1284} + {1'h0, _pop_count_packed_deps_T_1290}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_1292 = _pop_count_packed_deps_T_1291; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1293 = {1'h0, entries_ex_15_bits_deps_ex_8} + {1'h0, entries_ex_15_bits_deps_ex_9}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1294 = _pop_count_packed_deps_T_1293; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1295 = {1'h0, entries_ex_15_bits_deps_ex_10} + {1'h0, entries_ex_15_bits_deps_ex_11}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1296 = _pop_count_packed_deps_T_1295; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1297 = {1'h0, _pop_count_packed_deps_T_1294} + {1'h0, _pop_count_packed_deps_T_1296}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1298 = _pop_count_packed_deps_T_1297; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1299 = {1'h0, entries_ex_15_bits_deps_ex_12} + {1'h0, entries_ex_15_bits_deps_ex_13}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1300 = _pop_count_packed_deps_T_1299; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1301 = {1'h0, entries_ex_15_bits_deps_ex_14} + {1'h0, entries_ex_15_bits_deps_ex_15}; // @[ReservationStation.scala:118:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1302 = _pop_count_packed_deps_T_1301; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1303 = {1'h0, _pop_count_packed_deps_T_1300} + {1'h0, _pop_count_packed_deps_T_1302}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1304 = _pop_count_packed_deps_T_1303; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_1305 = {1'h0, _pop_count_packed_deps_T_1298} + {1'h0, _pop_count_packed_deps_T_1304}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_1306 = _pop_count_packed_deps_T_1305; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_1307 = {1'h0, _pop_count_packed_deps_T_1292} + {1'h0, _pop_count_packed_deps_T_1306}; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_1308 = _pop_count_packed_deps_T_1307; // @[ReservationStation.scala:514:40] wire [5:0] _pop_count_packed_deps_T_1309 = {2'h0, _pop_count_packed_deps_T_1278} + {1'h0, _pop_count_packed_deps_T_1308}; // @[ReservationStation.scala:514:{13,30,40}] wire [4:0] _pop_count_packed_deps_T_1310 = _pop_count_packed_deps_T_1309[4:0]; // @[ReservationStation.scala:514:30] wire [1:0] _pop_count_packed_deps_T_1311 = {1'h0, entries_ex_15_bits_deps_st_0} + {1'h0, entries_ex_15_bits_deps_st_1}; // @[ReservationStation.scala:118:23, :514:67] wire [1:0] _pop_count_packed_deps_T_1312 = _pop_count_packed_deps_T_1311; // @[ReservationStation.scala:514:67] wire [1:0] _pop_count_packed_deps_T_1313 = {1'h0, entries_ex_15_bits_deps_st_2} + {1'h0, entries_ex_15_bits_deps_st_3}; // @[ReservationStation.scala:118:23, :514:67] wire [1:0] _pop_count_packed_deps_T_1314 = _pop_count_packed_deps_T_1313; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_1315 = {1'h0, _pop_count_packed_deps_T_1312} + {1'h0, _pop_count_packed_deps_T_1314}; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_1316 = _pop_count_packed_deps_T_1315; // @[ReservationStation.scala:514:67] wire [5:0] _pop_count_packed_deps_T_1317 = {1'h0, _pop_count_packed_deps_T_1310} + {3'h0, _pop_count_packed_deps_T_1316}; // @[ReservationStation.scala:514:{30,57,67}] wire [4:0] _pop_count_packed_deps_T_1318 = _pop_count_packed_deps_T_1317[4:0]; // @[ReservationStation.scala:514:57] wire [4:0] _pop_count_packed_deps_T_1319 = entries_ex_15_valid ? _pop_count_packed_deps_T_1318 : 5'h0; // @[ReservationStation.scala:118:23, :513:59, :514:57] wire [4:0] pop_count_packed_deps_23 = _pop_count_packed_deps_T_1319; // @[ReservationStation.scala:513:{38,59}] wire [1:0] _pop_count_packed_deps_T_1320 = {1'h0, entries_st_0_bits_deps_ld_0} + {1'h0, entries_st_0_bits_deps_ld_1}; // @[ReservationStation.scala:119:23, :514:13] wire [1:0] _pop_count_packed_deps_T_1321 = _pop_count_packed_deps_T_1320; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_1322 = {1'h0, entries_st_0_bits_deps_ld_2} + {1'h0, entries_st_0_bits_deps_ld_3}; // @[ReservationStation.scala:119:23, :514:13] wire [1:0] _pop_count_packed_deps_T_1323 = _pop_count_packed_deps_T_1322; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_1324 = {1'h0, _pop_count_packed_deps_T_1321} + {1'h0, _pop_count_packed_deps_T_1323}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_1325 = _pop_count_packed_deps_T_1324; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_1326 = {1'h0, entries_st_0_bits_deps_ld_4} + {1'h0, entries_st_0_bits_deps_ld_5}; // @[ReservationStation.scala:119:23, :514:13] wire [1:0] _pop_count_packed_deps_T_1327 = _pop_count_packed_deps_T_1326; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_1328 = {1'h0, entries_st_0_bits_deps_ld_6} + {1'h0, entries_st_0_bits_deps_ld_7}; // @[ReservationStation.scala:119:23, :514:13] wire [1:0] _pop_count_packed_deps_T_1329 = _pop_count_packed_deps_T_1328; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_1330 = {1'h0, _pop_count_packed_deps_T_1327} + {1'h0, _pop_count_packed_deps_T_1329}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_1331 = _pop_count_packed_deps_T_1330; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_1332 = {1'h0, _pop_count_packed_deps_T_1325} + {1'h0, _pop_count_packed_deps_T_1331}; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_1333 = _pop_count_packed_deps_T_1332; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_1334 = {1'h0, entries_st_0_bits_deps_ex_0} + {1'h0, entries_st_0_bits_deps_ex_1}; // @[ReservationStation.scala:119:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1335 = _pop_count_packed_deps_T_1334; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1336 = {1'h0, entries_st_0_bits_deps_ex_2} + {1'h0, entries_st_0_bits_deps_ex_3}; // @[ReservationStation.scala:119:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1337 = _pop_count_packed_deps_T_1336; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1338 = {1'h0, _pop_count_packed_deps_T_1335} + {1'h0, _pop_count_packed_deps_T_1337}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1339 = _pop_count_packed_deps_T_1338; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1340 = {1'h0, entries_st_0_bits_deps_ex_4} + {1'h0, entries_st_0_bits_deps_ex_5}; // @[ReservationStation.scala:119:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1341 = _pop_count_packed_deps_T_1340; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1342 = {1'h0, entries_st_0_bits_deps_ex_6} + {1'h0, entries_st_0_bits_deps_ex_7}; // @[ReservationStation.scala:119:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1343 = _pop_count_packed_deps_T_1342; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1344 = {1'h0, _pop_count_packed_deps_T_1341} + {1'h0, _pop_count_packed_deps_T_1343}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1345 = _pop_count_packed_deps_T_1344; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_1346 = {1'h0, _pop_count_packed_deps_T_1339} + {1'h0, _pop_count_packed_deps_T_1345}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_1347 = _pop_count_packed_deps_T_1346; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1348 = {1'h0, entries_st_0_bits_deps_ex_8} + {1'h0, entries_st_0_bits_deps_ex_9}; // @[ReservationStation.scala:119:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1349 = _pop_count_packed_deps_T_1348; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1350 = {1'h0, entries_st_0_bits_deps_ex_10} + {1'h0, entries_st_0_bits_deps_ex_11}; // @[ReservationStation.scala:119:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1351 = _pop_count_packed_deps_T_1350; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1352 = {1'h0, _pop_count_packed_deps_T_1349} + {1'h0, _pop_count_packed_deps_T_1351}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1353 = _pop_count_packed_deps_T_1352; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1354 = {1'h0, entries_st_0_bits_deps_ex_12} + {1'h0, entries_st_0_bits_deps_ex_13}; // @[ReservationStation.scala:119:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1355 = _pop_count_packed_deps_T_1354; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1356 = {1'h0, entries_st_0_bits_deps_ex_14} + {1'h0, entries_st_0_bits_deps_ex_15}; // @[ReservationStation.scala:119:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1357 = _pop_count_packed_deps_T_1356; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1358 = {1'h0, _pop_count_packed_deps_T_1355} + {1'h0, _pop_count_packed_deps_T_1357}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1359 = _pop_count_packed_deps_T_1358; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_1360 = {1'h0, _pop_count_packed_deps_T_1353} + {1'h0, _pop_count_packed_deps_T_1359}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_1361 = _pop_count_packed_deps_T_1360; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_1362 = {1'h0, _pop_count_packed_deps_T_1347} + {1'h0, _pop_count_packed_deps_T_1361}; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_1363 = _pop_count_packed_deps_T_1362; // @[ReservationStation.scala:514:40] wire [5:0] _pop_count_packed_deps_T_1364 = {2'h0, _pop_count_packed_deps_T_1333} + {1'h0, _pop_count_packed_deps_T_1363}; // @[ReservationStation.scala:514:{13,30,40}] wire [4:0] _pop_count_packed_deps_T_1365 = _pop_count_packed_deps_T_1364[4:0]; // @[ReservationStation.scala:514:30] wire [1:0] _pop_count_packed_deps_T_1366 = {1'h0, entries_st_0_bits_deps_st_0} + {1'h0, entries_st_0_bits_deps_st_1}; // @[ReservationStation.scala:119:23, :514:67] wire [1:0] _pop_count_packed_deps_T_1367 = _pop_count_packed_deps_T_1366; // @[ReservationStation.scala:514:67] wire [1:0] _pop_count_packed_deps_T_1368 = {1'h0, entries_st_0_bits_deps_st_2} + {1'h0, entries_st_0_bits_deps_st_3}; // @[ReservationStation.scala:119:23, :514:67] wire [1:0] _pop_count_packed_deps_T_1369 = _pop_count_packed_deps_T_1368; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_1370 = {1'h0, _pop_count_packed_deps_T_1367} + {1'h0, _pop_count_packed_deps_T_1369}; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_1371 = _pop_count_packed_deps_T_1370; // @[ReservationStation.scala:514:67] wire [5:0] _pop_count_packed_deps_T_1372 = {1'h0, _pop_count_packed_deps_T_1365} + {3'h0, _pop_count_packed_deps_T_1371}; // @[ReservationStation.scala:514:{30,57,67}] wire [4:0] _pop_count_packed_deps_T_1373 = _pop_count_packed_deps_T_1372[4:0]; // @[ReservationStation.scala:514:57] wire [4:0] _pop_count_packed_deps_T_1374 = entries_st_0_valid ? _pop_count_packed_deps_T_1373 : 5'h0; // @[ReservationStation.scala:119:23, :513:59, :514:57] wire [4:0] pop_count_packed_deps_24 = _pop_count_packed_deps_T_1374; // @[ReservationStation.scala:513:{38,59}] wire [1:0] _pop_count_packed_deps_T_1375 = {1'h0, entries_st_1_bits_deps_ld_0} + {1'h0, entries_st_1_bits_deps_ld_1}; // @[ReservationStation.scala:119:23, :514:13] wire [1:0] _pop_count_packed_deps_T_1376 = _pop_count_packed_deps_T_1375; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_1377 = {1'h0, entries_st_1_bits_deps_ld_2} + {1'h0, entries_st_1_bits_deps_ld_3}; // @[ReservationStation.scala:119:23, :514:13] wire [1:0] _pop_count_packed_deps_T_1378 = _pop_count_packed_deps_T_1377; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_1379 = {1'h0, _pop_count_packed_deps_T_1376} + {1'h0, _pop_count_packed_deps_T_1378}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_1380 = _pop_count_packed_deps_T_1379; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_1381 = {1'h0, entries_st_1_bits_deps_ld_4} + {1'h0, entries_st_1_bits_deps_ld_5}; // @[ReservationStation.scala:119:23, :514:13] wire [1:0] _pop_count_packed_deps_T_1382 = _pop_count_packed_deps_T_1381; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_1383 = {1'h0, entries_st_1_bits_deps_ld_6} + {1'h0, entries_st_1_bits_deps_ld_7}; // @[ReservationStation.scala:119:23, :514:13] wire [1:0] _pop_count_packed_deps_T_1384 = _pop_count_packed_deps_T_1383; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_1385 = {1'h0, _pop_count_packed_deps_T_1382} + {1'h0, _pop_count_packed_deps_T_1384}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_1386 = _pop_count_packed_deps_T_1385; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_1387 = {1'h0, _pop_count_packed_deps_T_1380} + {1'h0, _pop_count_packed_deps_T_1386}; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_1388 = _pop_count_packed_deps_T_1387; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_1389 = {1'h0, entries_st_1_bits_deps_ex_0} + {1'h0, entries_st_1_bits_deps_ex_1}; // @[ReservationStation.scala:119:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1390 = _pop_count_packed_deps_T_1389; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1391 = {1'h0, entries_st_1_bits_deps_ex_2} + {1'h0, entries_st_1_bits_deps_ex_3}; // @[ReservationStation.scala:119:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1392 = _pop_count_packed_deps_T_1391; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1393 = {1'h0, _pop_count_packed_deps_T_1390} + {1'h0, _pop_count_packed_deps_T_1392}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1394 = _pop_count_packed_deps_T_1393; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1395 = {1'h0, entries_st_1_bits_deps_ex_4} + {1'h0, entries_st_1_bits_deps_ex_5}; // @[ReservationStation.scala:119:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1396 = _pop_count_packed_deps_T_1395; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1397 = {1'h0, entries_st_1_bits_deps_ex_6} + {1'h0, entries_st_1_bits_deps_ex_7}; // @[ReservationStation.scala:119:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1398 = _pop_count_packed_deps_T_1397; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1399 = {1'h0, _pop_count_packed_deps_T_1396} + {1'h0, _pop_count_packed_deps_T_1398}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1400 = _pop_count_packed_deps_T_1399; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_1401 = {1'h0, _pop_count_packed_deps_T_1394} + {1'h0, _pop_count_packed_deps_T_1400}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_1402 = _pop_count_packed_deps_T_1401; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1403 = {1'h0, entries_st_1_bits_deps_ex_8} + {1'h0, entries_st_1_bits_deps_ex_9}; // @[ReservationStation.scala:119:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1404 = _pop_count_packed_deps_T_1403; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1405 = {1'h0, entries_st_1_bits_deps_ex_10} + {1'h0, entries_st_1_bits_deps_ex_11}; // @[ReservationStation.scala:119:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1406 = _pop_count_packed_deps_T_1405; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1407 = {1'h0, _pop_count_packed_deps_T_1404} + {1'h0, _pop_count_packed_deps_T_1406}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1408 = _pop_count_packed_deps_T_1407; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1409 = {1'h0, entries_st_1_bits_deps_ex_12} + {1'h0, entries_st_1_bits_deps_ex_13}; // @[ReservationStation.scala:119:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1410 = _pop_count_packed_deps_T_1409; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1411 = {1'h0, entries_st_1_bits_deps_ex_14} + {1'h0, entries_st_1_bits_deps_ex_15}; // @[ReservationStation.scala:119:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1412 = _pop_count_packed_deps_T_1411; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1413 = {1'h0, _pop_count_packed_deps_T_1410} + {1'h0, _pop_count_packed_deps_T_1412}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1414 = _pop_count_packed_deps_T_1413; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_1415 = {1'h0, _pop_count_packed_deps_T_1408} + {1'h0, _pop_count_packed_deps_T_1414}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_1416 = _pop_count_packed_deps_T_1415; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_1417 = {1'h0, _pop_count_packed_deps_T_1402} + {1'h0, _pop_count_packed_deps_T_1416}; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_1418 = _pop_count_packed_deps_T_1417; // @[ReservationStation.scala:514:40] wire [5:0] _pop_count_packed_deps_T_1419 = {2'h0, _pop_count_packed_deps_T_1388} + {1'h0, _pop_count_packed_deps_T_1418}; // @[ReservationStation.scala:514:{13,30,40}] wire [4:0] _pop_count_packed_deps_T_1420 = _pop_count_packed_deps_T_1419[4:0]; // @[ReservationStation.scala:514:30] wire [1:0] _pop_count_packed_deps_T_1421 = {1'h0, entries_st_1_bits_deps_st_0} + {1'h0, entries_st_1_bits_deps_st_1}; // @[ReservationStation.scala:119:23, :514:67] wire [1:0] _pop_count_packed_deps_T_1422 = _pop_count_packed_deps_T_1421; // @[ReservationStation.scala:514:67] wire [1:0] _pop_count_packed_deps_T_1423 = {1'h0, entries_st_1_bits_deps_st_2} + {1'h0, entries_st_1_bits_deps_st_3}; // @[ReservationStation.scala:119:23, :514:67] wire [1:0] _pop_count_packed_deps_T_1424 = _pop_count_packed_deps_T_1423; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_1425 = {1'h0, _pop_count_packed_deps_T_1422} + {1'h0, _pop_count_packed_deps_T_1424}; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_1426 = _pop_count_packed_deps_T_1425; // @[ReservationStation.scala:514:67] wire [5:0] _pop_count_packed_deps_T_1427 = {1'h0, _pop_count_packed_deps_T_1420} + {3'h0, _pop_count_packed_deps_T_1426}; // @[ReservationStation.scala:514:{30,57,67}] wire [4:0] _pop_count_packed_deps_T_1428 = _pop_count_packed_deps_T_1427[4:0]; // @[ReservationStation.scala:514:57] wire [4:0] _pop_count_packed_deps_T_1429 = entries_st_1_valid ? _pop_count_packed_deps_T_1428 : 5'h0; // @[ReservationStation.scala:119:23, :513:59, :514:57] wire [4:0] pop_count_packed_deps_25 = _pop_count_packed_deps_T_1429; // @[ReservationStation.scala:513:{38,59}] wire [1:0] _pop_count_packed_deps_T_1430 = {1'h0, entries_st_2_bits_deps_ld_0} + {1'h0, entries_st_2_bits_deps_ld_1}; // @[ReservationStation.scala:119:23, :514:13] wire [1:0] _pop_count_packed_deps_T_1431 = _pop_count_packed_deps_T_1430; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_1432 = {1'h0, entries_st_2_bits_deps_ld_2} + {1'h0, entries_st_2_bits_deps_ld_3}; // @[ReservationStation.scala:119:23, :514:13] wire [1:0] _pop_count_packed_deps_T_1433 = _pop_count_packed_deps_T_1432; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_1434 = {1'h0, _pop_count_packed_deps_T_1431} + {1'h0, _pop_count_packed_deps_T_1433}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_1435 = _pop_count_packed_deps_T_1434; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_1436 = {1'h0, entries_st_2_bits_deps_ld_4} + {1'h0, entries_st_2_bits_deps_ld_5}; // @[ReservationStation.scala:119:23, :514:13] wire [1:0] _pop_count_packed_deps_T_1437 = _pop_count_packed_deps_T_1436; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_1438 = {1'h0, entries_st_2_bits_deps_ld_6} + {1'h0, entries_st_2_bits_deps_ld_7}; // @[ReservationStation.scala:119:23, :514:13] wire [1:0] _pop_count_packed_deps_T_1439 = _pop_count_packed_deps_T_1438; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_1440 = {1'h0, _pop_count_packed_deps_T_1437} + {1'h0, _pop_count_packed_deps_T_1439}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_1441 = _pop_count_packed_deps_T_1440; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_1442 = {1'h0, _pop_count_packed_deps_T_1435} + {1'h0, _pop_count_packed_deps_T_1441}; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_1443 = _pop_count_packed_deps_T_1442; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_1444 = {1'h0, entries_st_2_bits_deps_ex_0} + {1'h0, entries_st_2_bits_deps_ex_1}; // @[ReservationStation.scala:119:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1445 = _pop_count_packed_deps_T_1444; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1446 = {1'h0, entries_st_2_bits_deps_ex_2} + {1'h0, entries_st_2_bits_deps_ex_3}; // @[ReservationStation.scala:119:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1447 = _pop_count_packed_deps_T_1446; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1448 = {1'h0, _pop_count_packed_deps_T_1445} + {1'h0, _pop_count_packed_deps_T_1447}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1449 = _pop_count_packed_deps_T_1448; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1450 = {1'h0, entries_st_2_bits_deps_ex_4} + {1'h0, entries_st_2_bits_deps_ex_5}; // @[ReservationStation.scala:119:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1451 = _pop_count_packed_deps_T_1450; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1452 = {1'h0, entries_st_2_bits_deps_ex_6} + {1'h0, entries_st_2_bits_deps_ex_7}; // @[ReservationStation.scala:119:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1453 = _pop_count_packed_deps_T_1452; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1454 = {1'h0, _pop_count_packed_deps_T_1451} + {1'h0, _pop_count_packed_deps_T_1453}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1455 = _pop_count_packed_deps_T_1454; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_1456 = {1'h0, _pop_count_packed_deps_T_1449} + {1'h0, _pop_count_packed_deps_T_1455}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_1457 = _pop_count_packed_deps_T_1456; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1458 = {1'h0, entries_st_2_bits_deps_ex_8} + {1'h0, entries_st_2_bits_deps_ex_9}; // @[ReservationStation.scala:119:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1459 = _pop_count_packed_deps_T_1458; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1460 = {1'h0, entries_st_2_bits_deps_ex_10} + {1'h0, entries_st_2_bits_deps_ex_11}; // @[ReservationStation.scala:119:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1461 = _pop_count_packed_deps_T_1460; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1462 = {1'h0, _pop_count_packed_deps_T_1459} + {1'h0, _pop_count_packed_deps_T_1461}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1463 = _pop_count_packed_deps_T_1462; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1464 = {1'h0, entries_st_2_bits_deps_ex_12} + {1'h0, entries_st_2_bits_deps_ex_13}; // @[ReservationStation.scala:119:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1465 = _pop_count_packed_deps_T_1464; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1466 = {1'h0, entries_st_2_bits_deps_ex_14} + {1'h0, entries_st_2_bits_deps_ex_15}; // @[ReservationStation.scala:119:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1467 = _pop_count_packed_deps_T_1466; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1468 = {1'h0, _pop_count_packed_deps_T_1465} + {1'h0, _pop_count_packed_deps_T_1467}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1469 = _pop_count_packed_deps_T_1468; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_1470 = {1'h0, _pop_count_packed_deps_T_1463} + {1'h0, _pop_count_packed_deps_T_1469}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_1471 = _pop_count_packed_deps_T_1470; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_1472 = {1'h0, _pop_count_packed_deps_T_1457} + {1'h0, _pop_count_packed_deps_T_1471}; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_1473 = _pop_count_packed_deps_T_1472; // @[ReservationStation.scala:514:40] wire [5:0] _pop_count_packed_deps_T_1474 = {2'h0, _pop_count_packed_deps_T_1443} + {1'h0, _pop_count_packed_deps_T_1473}; // @[ReservationStation.scala:514:{13,30,40}] wire [4:0] _pop_count_packed_deps_T_1475 = _pop_count_packed_deps_T_1474[4:0]; // @[ReservationStation.scala:514:30] wire [1:0] _pop_count_packed_deps_T_1476 = {1'h0, entries_st_2_bits_deps_st_0} + {1'h0, entries_st_2_bits_deps_st_1}; // @[ReservationStation.scala:119:23, :514:67] wire [1:0] _pop_count_packed_deps_T_1477 = _pop_count_packed_deps_T_1476; // @[ReservationStation.scala:514:67] wire [1:0] _pop_count_packed_deps_T_1478 = {1'h0, entries_st_2_bits_deps_st_2} + {1'h0, entries_st_2_bits_deps_st_3}; // @[ReservationStation.scala:119:23, :514:67] wire [1:0] _pop_count_packed_deps_T_1479 = _pop_count_packed_deps_T_1478; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_1480 = {1'h0, _pop_count_packed_deps_T_1477} + {1'h0, _pop_count_packed_deps_T_1479}; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_1481 = _pop_count_packed_deps_T_1480; // @[ReservationStation.scala:514:67] wire [5:0] _pop_count_packed_deps_T_1482 = {1'h0, _pop_count_packed_deps_T_1475} + {3'h0, _pop_count_packed_deps_T_1481}; // @[ReservationStation.scala:514:{30,57,67}] wire [4:0] _pop_count_packed_deps_T_1483 = _pop_count_packed_deps_T_1482[4:0]; // @[ReservationStation.scala:514:57] wire [4:0] _pop_count_packed_deps_T_1484 = entries_st_2_valid ? _pop_count_packed_deps_T_1483 : 5'h0; // @[ReservationStation.scala:119:23, :513:59, :514:57] wire [4:0] pop_count_packed_deps_26 = _pop_count_packed_deps_T_1484; // @[ReservationStation.scala:513:{38,59}] wire [1:0] _pop_count_packed_deps_T_1485 = {1'h0, entries_st_3_bits_deps_ld_0} + {1'h0, entries_st_3_bits_deps_ld_1}; // @[ReservationStation.scala:119:23, :514:13] wire [1:0] _pop_count_packed_deps_T_1486 = _pop_count_packed_deps_T_1485; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_1487 = {1'h0, entries_st_3_bits_deps_ld_2} + {1'h0, entries_st_3_bits_deps_ld_3}; // @[ReservationStation.scala:119:23, :514:13] wire [1:0] _pop_count_packed_deps_T_1488 = _pop_count_packed_deps_T_1487; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_1489 = {1'h0, _pop_count_packed_deps_T_1486} + {1'h0, _pop_count_packed_deps_T_1488}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_1490 = _pop_count_packed_deps_T_1489; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_1491 = {1'h0, entries_st_3_bits_deps_ld_4} + {1'h0, entries_st_3_bits_deps_ld_5}; // @[ReservationStation.scala:119:23, :514:13] wire [1:0] _pop_count_packed_deps_T_1492 = _pop_count_packed_deps_T_1491; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_1493 = {1'h0, entries_st_3_bits_deps_ld_6} + {1'h0, entries_st_3_bits_deps_ld_7}; // @[ReservationStation.scala:119:23, :514:13] wire [1:0] _pop_count_packed_deps_T_1494 = _pop_count_packed_deps_T_1493; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_1495 = {1'h0, _pop_count_packed_deps_T_1492} + {1'h0, _pop_count_packed_deps_T_1494}; // @[ReservationStation.scala:514:13] wire [2:0] _pop_count_packed_deps_T_1496 = _pop_count_packed_deps_T_1495; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_1497 = {1'h0, _pop_count_packed_deps_T_1490} + {1'h0, _pop_count_packed_deps_T_1496}; // @[ReservationStation.scala:514:13] wire [3:0] _pop_count_packed_deps_T_1498 = _pop_count_packed_deps_T_1497; // @[ReservationStation.scala:514:13] wire [1:0] _pop_count_packed_deps_T_1499 = {1'h0, entries_st_3_bits_deps_ex_0} + {1'h0, entries_st_3_bits_deps_ex_1}; // @[ReservationStation.scala:119:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1500 = _pop_count_packed_deps_T_1499; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1501 = {1'h0, entries_st_3_bits_deps_ex_2} + {1'h0, entries_st_3_bits_deps_ex_3}; // @[ReservationStation.scala:119:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1502 = _pop_count_packed_deps_T_1501; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1503 = {1'h0, _pop_count_packed_deps_T_1500} + {1'h0, _pop_count_packed_deps_T_1502}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1504 = _pop_count_packed_deps_T_1503; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1505 = {1'h0, entries_st_3_bits_deps_ex_4} + {1'h0, entries_st_3_bits_deps_ex_5}; // @[ReservationStation.scala:119:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1506 = _pop_count_packed_deps_T_1505; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1507 = {1'h0, entries_st_3_bits_deps_ex_6} + {1'h0, entries_st_3_bits_deps_ex_7}; // @[ReservationStation.scala:119:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1508 = _pop_count_packed_deps_T_1507; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1509 = {1'h0, _pop_count_packed_deps_T_1506} + {1'h0, _pop_count_packed_deps_T_1508}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1510 = _pop_count_packed_deps_T_1509; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_1511 = {1'h0, _pop_count_packed_deps_T_1504} + {1'h0, _pop_count_packed_deps_T_1510}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_1512 = _pop_count_packed_deps_T_1511; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1513 = {1'h0, entries_st_3_bits_deps_ex_8} + {1'h0, entries_st_3_bits_deps_ex_9}; // @[ReservationStation.scala:119:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1514 = _pop_count_packed_deps_T_1513; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1515 = {1'h0, entries_st_3_bits_deps_ex_10} + {1'h0, entries_st_3_bits_deps_ex_11}; // @[ReservationStation.scala:119:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1516 = _pop_count_packed_deps_T_1515; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1517 = {1'h0, _pop_count_packed_deps_T_1514} + {1'h0, _pop_count_packed_deps_T_1516}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1518 = _pop_count_packed_deps_T_1517; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1519 = {1'h0, entries_st_3_bits_deps_ex_12} + {1'h0, entries_st_3_bits_deps_ex_13}; // @[ReservationStation.scala:119:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1520 = _pop_count_packed_deps_T_1519; // @[ReservationStation.scala:514:40] wire [1:0] _pop_count_packed_deps_T_1521 = {1'h0, entries_st_3_bits_deps_ex_14} + {1'h0, entries_st_3_bits_deps_ex_15}; // @[ReservationStation.scala:119:23, :514:40] wire [1:0] _pop_count_packed_deps_T_1522 = _pop_count_packed_deps_T_1521; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1523 = {1'h0, _pop_count_packed_deps_T_1520} + {1'h0, _pop_count_packed_deps_T_1522}; // @[ReservationStation.scala:514:40] wire [2:0] _pop_count_packed_deps_T_1524 = _pop_count_packed_deps_T_1523; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_1525 = {1'h0, _pop_count_packed_deps_T_1518} + {1'h0, _pop_count_packed_deps_T_1524}; // @[ReservationStation.scala:514:40] wire [3:0] _pop_count_packed_deps_T_1526 = _pop_count_packed_deps_T_1525; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_1527 = {1'h0, _pop_count_packed_deps_T_1512} + {1'h0, _pop_count_packed_deps_T_1526}; // @[ReservationStation.scala:514:40] wire [4:0] _pop_count_packed_deps_T_1528 = _pop_count_packed_deps_T_1527; // @[ReservationStation.scala:514:40] wire [5:0] _pop_count_packed_deps_T_1529 = {2'h0, _pop_count_packed_deps_T_1498} + {1'h0, _pop_count_packed_deps_T_1528}; // @[ReservationStation.scala:514:{13,30,40}] wire [4:0] _pop_count_packed_deps_T_1530 = _pop_count_packed_deps_T_1529[4:0]; // @[ReservationStation.scala:514:30] wire [1:0] _pop_count_packed_deps_T_1531 = {1'h0, entries_st_3_bits_deps_st_0} + {1'h0, entries_st_3_bits_deps_st_1}; // @[ReservationStation.scala:119:23, :514:67] wire [1:0] _pop_count_packed_deps_T_1532 = _pop_count_packed_deps_T_1531; // @[ReservationStation.scala:514:67] wire [1:0] _pop_count_packed_deps_T_1533 = {1'h0, entries_st_3_bits_deps_st_2} + {1'h0, entries_st_3_bits_deps_st_3}; // @[ReservationStation.scala:119:23, :514:67] wire [1:0] _pop_count_packed_deps_T_1534 = _pop_count_packed_deps_T_1533; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_1535 = {1'h0, _pop_count_packed_deps_T_1532} + {1'h0, _pop_count_packed_deps_T_1534}; // @[ReservationStation.scala:514:67] wire [2:0] _pop_count_packed_deps_T_1536 = _pop_count_packed_deps_T_1535; // @[ReservationStation.scala:514:67] wire [5:0] _pop_count_packed_deps_T_1537 = {1'h0, _pop_count_packed_deps_T_1530} + {3'h0, _pop_count_packed_deps_T_1536}; // @[ReservationStation.scala:514:{30,57,67}] wire [4:0] _pop_count_packed_deps_T_1538 = _pop_count_packed_deps_T_1537[4:0]; // @[ReservationStation.scala:514:57] wire [4:0] _pop_count_packed_deps_T_1539 = entries_st_3_valid ? _pop_count_packed_deps_T_1538 : 5'h0; // @[ReservationStation.scala:119:23, :513:59, :514:57] wire [4:0] pop_count_packed_deps_27 = _pop_count_packed_deps_T_1539; // @[ReservationStation.scala:513:{38,59}] wire _min_pop_count_T = pop_count_packed_deps_0 < pop_count_packed_deps_1; // @[Util.scala:109:12] wire [4:0] _min_pop_count_T_1 = _min_pop_count_T ? pop_count_packed_deps_0 : pop_count_packed_deps_1; // @[Util.scala:109:{8,12}] wire _min_pop_count_T_2 = _min_pop_count_T_1 < pop_count_packed_deps_2; // @[Util.scala:109:{8,12}] wire [4:0] _min_pop_count_T_3 = _min_pop_count_T_2 ? _min_pop_count_T_1 : pop_count_packed_deps_2; // @[Util.scala:109:{8,12}] wire _min_pop_count_T_4 = _min_pop_count_T_3 < pop_count_packed_deps_3; // @[Util.scala:109:{8,12}] wire [4:0] _min_pop_count_T_5 = _min_pop_count_T_4 ? _min_pop_count_T_3 : pop_count_packed_deps_3; // @[Util.scala:109:{8,12}] wire _min_pop_count_T_6 = _min_pop_count_T_5 < pop_count_packed_deps_4; // @[Util.scala:109:{8,12}] wire [4:0] _min_pop_count_T_7 = _min_pop_count_T_6 ? _min_pop_count_T_5 : pop_count_packed_deps_4; // @[Util.scala:109:{8,12}] wire _min_pop_count_T_8 = _min_pop_count_T_7 < pop_count_packed_deps_5; // @[Util.scala:109:{8,12}] wire [4:0] _min_pop_count_T_9 = _min_pop_count_T_8 ? _min_pop_count_T_7 : pop_count_packed_deps_5; // @[Util.scala:109:{8,12}] wire _min_pop_count_T_10 = _min_pop_count_T_9 < pop_count_packed_deps_6; // @[Util.scala:109:{8,12}] wire [4:0] _min_pop_count_T_11 = _min_pop_count_T_10 ? _min_pop_count_T_9 : pop_count_packed_deps_6; // @[Util.scala:109:{8,12}] wire _min_pop_count_T_12 = _min_pop_count_T_11 < pop_count_packed_deps_7; // @[Util.scala:109:{8,12}] wire [4:0] _min_pop_count_T_13 = _min_pop_count_T_12 ? _min_pop_count_T_11 : pop_count_packed_deps_7; // @[Util.scala:109:{8,12}] wire _min_pop_count_T_14 = _min_pop_count_T_13 < pop_count_packed_deps_8; // @[Util.scala:109:{8,12}] wire [4:0] _min_pop_count_T_15 = _min_pop_count_T_14 ? _min_pop_count_T_13 : pop_count_packed_deps_8; // @[Util.scala:109:{8,12}] wire _min_pop_count_T_16 = _min_pop_count_T_15 < pop_count_packed_deps_9; // @[Util.scala:109:{8,12}] wire [4:0] _min_pop_count_T_17 = _min_pop_count_T_16 ? _min_pop_count_T_15 : pop_count_packed_deps_9; // @[Util.scala:109:{8,12}] wire _min_pop_count_T_18 = _min_pop_count_T_17 < pop_count_packed_deps_10; // @[Util.scala:109:{8,12}] wire [4:0] _min_pop_count_T_19 = _min_pop_count_T_18 ? _min_pop_count_T_17 : pop_count_packed_deps_10; // @[Util.scala:109:{8,12}] wire _min_pop_count_T_20 = _min_pop_count_T_19 < pop_count_packed_deps_11; // @[Util.scala:109:{8,12}] wire [4:0] _min_pop_count_T_21 = _min_pop_count_T_20 ? _min_pop_count_T_19 : pop_count_packed_deps_11; // @[Util.scala:109:{8,12}] wire _min_pop_count_T_22 = _min_pop_count_T_21 < pop_count_packed_deps_12; // @[Util.scala:109:{8,12}] wire [4:0] _min_pop_count_T_23 = _min_pop_count_T_22 ? _min_pop_count_T_21 : pop_count_packed_deps_12; // @[Util.scala:109:{8,12}] wire _min_pop_count_T_24 = _min_pop_count_T_23 < pop_count_packed_deps_13; // @[Util.scala:109:{8,12}] wire [4:0] _min_pop_count_T_25 = _min_pop_count_T_24 ? _min_pop_count_T_23 : pop_count_packed_deps_13; // @[Util.scala:109:{8,12}] wire _min_pop_count_T_26 = _min_pop_count_T_25 < pop_count_packed_deps_14; // @[Util.scala:109:{8,12}] wire [4:0] _min_pop_count_T_27 = _min_pop_count_T_26 ? _min_pop_count_T_25 : pop_count_packed_deps_14; // @[Util.scala:109:{8,12}] wire _min_pop_count_T_28 = _min_pop_count_T_27 < pop_count_packed_deps_15; // @[Util.scala:109:{8,12}] wire [4:0] _min_pop_count_T_29 = _min_pop_count_T_28 ? _min_pop_count_T_27 : pop_count_packed_deps_15; // @[Util.scala:109:{8,12}] wire _min_pop_count_T_30 = _min_pop_count_T_29 < pop_count_packed_deps_16; // @[Util.scala:109:{8,12}] wire [4:0] _min_pop_count_T_31 = _min_pop_count_T_30 ? _min_pop_count_T_29 : pop_count_packed_deps_16; // @[Util.scala:109:{8,12}] wire _min_pop_count_T_32 = _min_pop_count_T_31 < pop_count_packed_deps_17; // @[Util.scala:109:{8,12}] wire [4:0] _min_pop_count_T_33 = _min_pop_count_T_32 ? _min_pop_count_T_31 : pop_count_packed_deps_17; // @[Util.scala:109:{8,12}] wire _min_pop_count_T_34 = _min_pop_count_T_33 < pop_count_packed_deps_18; // @[Util.scala:109:{8,12}] wire [4:0] _min_pop_count_T_35 = _min_pop_count_T_34 ? _min_pop_count_T_33 : pop_count_packed_deps_18; // @[Util.scala:109:{8,12}] wire _min_pop_count_T_36 = _min_pop_count_T_35 < pop_count_packed_deps_19; // @[Util.scala:109:{8,12}] wire [4:0] _min_pop_count_T_37 = _min_pop_count_T_36 ? _min_pop_count_T_35 : pop_count_packed_deps_19; // @[Util.scala:109:{8,12}] wire _min_pop_count_T_38 = _min_pop_count_T_37 < pop_count_packed_deps_20; // @[Util.scala:109:{8,12}] wire [4:0] _min_pop_count_T_39 = _min_pop_count_T_38 ? _min_pop_count_T_37 : pop_count_packed_deps_20; // @[Util.scala:109:{8,12}] wire _min_pop_count_T_40 = _min_pop_count_T_39 < pop_count_packed_deps_21; // @[Util.scala:109:{8,12}] wire [4:0] _min_pop_count_T_41 = _min_pop_count_T_40 ? _min_pop_count_T_39 : pop_count_packed_deps_21; // @[Util.scala:109:{8,12}] wire _min_pop_count_T_42 = _min_pop_count_T_41 < pop_count_packed_deps_22; // @[Util.scala:109:{8,12}] wire [4:0] _min_pop_count_T_43 = _min_pop_count_T_42 ? _min_pop_count_T_41 : pop_count_packed_deps_22; // @[Util.scala:109:{8,12}] wire _min_pop_count_T_44 = _min_pop_count_T_43 < pop_count_packed_deps_23; // @[Util.scala:109:{8,12}] wire [4:0] _min_pop_count_T_45 = _min_pop_count_T_44 ? _min_pop_count_T_43 : pop_count_packed_deps_23; // @[Util.scala:109:{8,12}] wire _min_pop_count_T_46 = _min_pop_count_T_45 < pop_count_packed_deps_24; // @[Util.scala:109:{8,12}] wire [4:0] _min_pop_count_T_47 = _min_pop_count_T_46 ? _min_pop_count_T_45 : pop_count_packed_deps_24; // @[Util.scala:109:{8,12}] wire _min_pop_count_T_48 = _min_pop_count_T_47 < pop_count_packed_deps_25; // @[Util.scala:109:{8,12}] wire [4:0] _min_pop_count_T_49 = _min_pop_count_T_48 ? _min_pop_count_T_47 : pop_count_packed_deps_25; // @[Util.scala:109:{8,12}] wire _min_pop_count_T_50 = _min_pop_count_T_49 < pop_count_packed_deps_26; // @[Util.scala:109:{8,12}] wire [4:0] _min_pop_count_T_51 = _min_pop_count_T_50 ? _min_pop_count_T_49 : pop_count_packed_deps_26; // @[Util.scala:109:{8,12}] wire _min_pop_count_T_52 = _min_pop_count_T_51 < pop_count_packed_deps_27; // @[Util.scala:109:{8,12}] wire [4:0] min_pop_count = _min_pop_count_T_52 ? _min_pop_count_T_51 : pop_count_packed_deps_27; // @[Util.scala:109:{8,12}] reg [15:0] cycles_since_issue; // @[ReservationStation.scala:520:35] wire [16:0] _cycles_since_issue_T = {1'h0, cycles_since_issue} + 17'h1; // @[ReservationStation.scala:520:35, :525:46] wire [15:0] _cycles_since_issue_T_1 = _cycles_since_issue_T[15:0]; // @[ReservationStation.scala:525:46] reg [20:0] cntr_value; // @[Counter.scala:61:40] wire wrap = cntr_value == 21'h1E847F; // @[Counter.scala:61:40, :73:24] wire [21:0] _value_T = {1'h0, cntr_value} + 22'h1; // @[Counter.scala:61:40, :77:24] wire [20:0] _value_T_1 = _value_T[20:0]; // @[Counter.scala:77:24]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_52 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 2, 0) node _source_ok_T = shr(io.in.a.bits.source, 3) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<3>(0h4)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits = bits(_uncommonBits_T, 2, 0) node _T_4 = shr(io.in.a.bits.source, 3) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<3>(0h4)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 2, 0) node _T_24 = shr(io.in.a.bits.source, 3) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<3>(0h4)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_33 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_34 = and(_T_32, _T_33) node _T_35 = or(UInt<1>(0h0), _T_34) node _T_36 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_37 = cvt(_T_36) node _T_38 = and(_T_37, asSInt(UInt<17>(0h100c0))) node _T_39 = asSInt(_T_38) node _T_40 = eq(_T_39, asSInt(UInt<1>(0h0))) node _T_41 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_42 = cvt(_T_41) node _T_43 = and(_T_42, asSInt(UInt<29>(0h100000c0))) node _T_44 = asSInt(_T_43) node _T_45 = eq(_T_44, asSInt(UInt<1>(0h0))) node _T_46 = or(_T_40, _T_45) node _T_47 = and(_T_35, _T_46) node _T_48 = or(UInt<1>(0h0), _T_47) node _T_49 = and(_T_31, _T_48) node _T_50 = asUInt(reset) node _T_51 = eq(_T_50, UInt<1>(0h0)) when _T_51 : node _T_52 = eq(_T_49, UInt<1>(0h0)) when _T_52 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_49, UInt<1>(0h1), "") : assert_2 node _T_53 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_54 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_55 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_56 = and(_T_54, _T_55) node _T_57 = or(UInt<1>(0h0), _T_56) node _T_58 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<17>(0h100c0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_64 = cvt(_T_63) node _T_65 = and(_T_64, asSInt(UInt<29>(0h100000c0))) node _T_66 = asSInt(_T_65) node _T_67 = eq(_T_66, asSInt(UInt<1>(0h0))) node _T_68 = or(_T_62, _T_67) node _T_69 = and(_T_57, _T_68) node _T_70 = or(UInt<1>(0h0), _T_69) node _T_71 = and(_T_53, _T_70) node _T_72 = asUInt(reset) node _T_73 = eq(_T_72, UInt<1>(0h0)) when _T_73 : node _T_74 = eq(_T_71, UInt<1>(0h0)) when _T_74 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_71, UInt<1>(0h1), "") : assert_3 node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_78 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_78, UInt<1>(0h1), "") : assert_5 node _T_82 = asUInt(reset) node _T_83 = eq(_T_82, UInt<1>(0h0)) when _T_83 : node _T_84 = eq(is_aligned, UInt<1>(0h0)) when _T_84 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_85 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_86 = asUInt(reset) node _T_87 = eq(_T_86, UInt<1>(0h0)) when _T_87 : node _T_88 = eq(_T_85, UInt<1>(0h0)) when _T_88 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_85, UInt<1>(0h1), "") : assert_7 node _T_89 = not(io.in.a.bits.mask) node _T_90 = eq(_T_89, UInt<1>(0h0)) node _T_91 = asUInt(reset) node _T_92 = eq(_T_91, UInt<1>(0h0)) when _T_92 : node _T_93 = eq(_T_90, UInt<1>(0h0)) when _T_93 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_90, UInt<1>(0h1), "") : assert_8 node _T_94 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_95 = asUInt(reset) node _T_96 = eq(_T_95, UInt<1>(0h0)) when _T_96 : node _T_97 = eq(_T_94, UInt<1>(0h0)) when _T_97 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_94, UInt<1>(0h1), "") : assert_9 node _T_98 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_98 : node _T_99 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_100 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_101 = and(_T_99, _T_100) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 2, 0) node _T_102 = shr(io.in.a.bits.source, 3) node _T_103 = eq(_T_102, UInt<1>(0h0)) node _T_104 = leq(UInt<1>(0h0), uncommonBits_2) node _T_105 = and(_T_103, _T_104) node _T_106 = leq(uncommonBits_2, UInt<3>(0h4)) node _T_107 = and(_T_105, _T_106) node _T_108 = and(_T_101, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_111 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_112 = and(_T_110, _T_111) node _T_113 = or(UInt<1>(0h0), _T_112) node _T_114 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_115 = cvt(_T_114) node _T_116 = and(_T_115, asSInt(UInt<17>(0h100c0))) node _T_117 = asSInt(_T_116) node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_120 = cvt(_T_119) node _T_121 = and(_T_120, asSInt(UInt<29>(0h100000c0))) node _T_122 = asSInt(_T_121) node _T_123 = eq(_T_122, asSInt(UInt<1>(0h0))) node _T_124 = or(_T_118, _T_123) node _T_125 = and(_T_113, _T_124) node _T_126 = or(UInt<1>(0h0), _T_125) node _T_127 = and(_T_109, _T_126) node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(_T_127, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_127, UInt<1>(0h1), "") : assert_10 node _T_131 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_132 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_133 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_134 = and(_T_132, _T_133) node _T_135 = or(UInt<1>(0h0), _T_134) node _T_136 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_137 = cvt(_T_136) node _T_138 = and(_T_137, asSInt(UInt<17>(0h100c0))) node _T_139 = asSInt(_T_138) node _T_140 = eq(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_142 = cvt(_T_141) node _T_143 = and(_T_142, asSInt(UInt<29>(0h100000c0))) node _T_144 = asSInt(_T_143) node _T_145 = eq(_T_144, asSInt(UInt<1>(0h0))) node _T_146 = or(_T_140, _T_145) node _T_147 = and(_T_135, _T_146) node _T_148 = or(UInt<1>(0h0), _T_147) node _T_149 = and(_T_131, _T_148) node _T_150 = asUInt(reset) node _T_151 = eq(_T_150, UInt<1>(0h0)) when _T_151 : node _T_152 = eq(_T_149, UInt<1>(0h0)) when _T_152 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_149, UInt<1>(0h1), "") : assert_11 node _T_153 = asUInt(reset) node _T_154 = eq(_T_153, UInt<1>(0h0)) when _T_154 : node _T_155 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_155 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_156 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_157 = asUInt(reset) node _T_158 = eq(_T_157, UInt<1>(0h0)) when _T_158 : node _T_159 = eq(_T_156, UInt<1>(0h0)) when _T_159 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_156, UInt<1>(0h1), "") : assert_13 node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(is_aligned, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_163 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_164 = asUInt(reset) node _T_165 = eq(_T_164, UInt<1>(0h0)) when _T_165 : node _T_166 = eq(_T_163, UInt<1>(0h0)) when _T_166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_163, UInt<1>(0h1), "") : assert_15 node _T_167 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_168 = asUInt(reset) node _T_169 = eq(_T_168, UInt<1>(0h0)) when _T_169 : node _T_170 = eq(_T_167, UInt<1>(0h0)) when _T_170 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_167, UInt<1>(0h1), "") : assert_16 node _T_171 = not(io.in.a.bits.mask) node _T_172 = eq(_T_171, UInt<1>(0h0)) node _T_173 = asUInt(reset) node _T_174 = eq(_T_173, UInt<1>(0h0)) when _T_174 : node _T_175 = eq(_T_172, UInt<1>(0h0)) when _T_175 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_172, UInt<1>(0h1), "") : assert_17 node _T_176 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_T_176, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_176, UInt<1>(0h1), "") : assert_18 node _T_180 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_180 : node _T_181 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_182 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_183 = and(_T_181, _T_182) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 2, 0) node _T_184 = shr(io.in.a.bits.source, 3) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = leq(UInt<1>(0h0), uncommonBits_3) node _T_187 = and(_T_185, _T_186) node _T_188 = leq(uncommonBits_3, UInt<3>(0h4)) node _T_189 = and(_T_187, _T_188) node _T_190 = and(_T_183, _T_189) node _T_191 = or(UInt<1>(0h0), _T_190) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_191, UInt<1>(0h1), "") : assert_19 node _T_195 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_196 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_197 = and(_T_195, _T_196) node _T_198 = or(UInt<1>(0h0), _T_197) node _T_199 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_200 = cvt(_T_199) node _T_201 = and(_T_200, asSInt(UInt<17>(0h100c0))) node _T_202 = asSInt(_T_201) node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0))) node _T_204 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_205 = cvt(_T_204) node _T_206 = and(_T_205, asSInt(UInt<29>(0h100000c0))) node _T_207 = asSInt(_T_206) node _T_208 = eq(_T_207, asSInt(UInt<1>(0h0))) node _T_209 = or(_T_203, _T_208) node _T_210 = and(_T_198, _T_209) node _T_211 = or(UInt<1>(0h0), _T_210) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_211, UInt<1>(0h1), "") : assert_20 node _T_215 = asUInt(reset) node _T_216 = eq(_T_215, UInt<1>(0h0)) when _T_216 : node _T_217 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_217 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_218 = asUInt(reset) node _T_219 = eq(_T_218, UInt<1>(0h0)) when _T_219 : node _T_220 = eq(is_aligned, UInt<1>(0h0)) when _T_220 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_221 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_T_221, UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_221, UInt<1>(0h1), "") : assert_23 node _T_225 = eq(io.in.a.bits.mask, mask) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_225, UInt<1>(0h1), "") : assert_24 node _T_229 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_230 = asUInt(reset) node _T_231 = eq(_T_230, UInt<1>(0h0)) when _T_231 : node _T_232 = eq(_T_229, UInt<1>(0h0)) when _T_232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_229, UInt<1>(0h1), "") : assert_25 node _T_233 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_233 : node _T_234 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_235 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_236 = and(_T_234, _T_235) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0) node _T_237 = shr(io.in.a.bits.source, 3) node _T_238 = eq(_T_237, UInt<1>(0h0)) node _T_239 = leq(UInt<1>(0h0), uncommonBits_4) node _T_240 = and(_T_238, _T_239) node _T_241 = leq(uncommonBits_4, UInt<3>(0h4)) node _T_242 = and(_T_240, _T_241) node _T_243 = and(_T_236, _T_242) node _T_244 = or(UInt<1>(0h0), _T_243) node _T_245 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_246 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_247 = and(_T_245, _T_246) node _T_248 = or(UInt<1>(0h0), _T_247) node _T_249 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_250 = cvt(_T_249) node _T_251 = and(_T_250, asSInt(UInt<17>(0h100c0))) node _T_252 = asSInt(_T_251) node _T_253 = eq(_T_252, asSInt(UInt<1>(0h0))) node _T_254 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_255 = cvt(_T_254) node _T_256 = and(_T_255, asSInt(UInt<29>(0h100000c0))) node _T_257 = asSInt(_T_256) node _T_258 = eq(_T_257, asSInt(UInt<1>(0h0))) node _T_259 = or(_T_253, _T_258) node _T_260 = and(_T_248, _T_259) node _T_261 = or(UInt<1>(0h0), _T_260) node _T_262 = and(_T_244, _T_261) node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_T_262, UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_262, UInt<1>(0h1), "") : assert_26 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_269 = asUInt(reset) node _T_270 = eq(_T_269, UInt<1>(0h0)) when _T_270 : node _T_271 = eq(is_aligned, UInt<1>(0h0)) when _T_271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_272 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_273 = asUInt(reset) node _T_274 = eq(_T_273, UInt<1>(0h0)) when _T_274 : node _T_275 = eq(_T_272, UInt<1>(0h0)) when _T_275 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_272, UInt<1>(0h1), "") : assert_29 node _T_276 = eq(io.in.a.bits.mask, mask) node _T_277 = asUInt(reset) node _T_278 = eq(_T_277, UInt<1>(0h0)) when _T_278 : node _T_279 = eq(_T_276, UInt<1>(0h0)) when _T_279 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_276, UInt<1>(0h1), "") : assert_30 node _T_280 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_280 : node _T_281 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_282 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_283 = and(_T_281, _T_282) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 2, 0) node _T_284 = shr(io.in.a.bits.source, 3) node _T_285 = eq(_T_284, UInt<1>(0h0)) node _T_286 = leq(UInt<1>(0h0), uncommonBits_5) node _T_287 = and(_T_285, _T_286) node _T_288 = leq(uncommonBits_5, UInt<3>(0h4)) node _T_289 = and(_T_287, _T_288) node _T_290 = and(_T_283, _T_289) node _T_291 = or(UInt<1>(0h0), _T_290) node _T_292 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_293 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_294 = and(_T_292, _T_293) node _T_295 = or(UInt<1>(0h0), _T_294) node _T_296 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_297 = cvt(_T_296) node _T_298 = and(_T_297, asSInt(UInt<17>(0h100c0))) node _T_299 = asSInt(_T_298) node _T_300 = eq(_T_299, asSInt(UInt<1>(0h0))) node _T_301 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_302 = cvt(_T_301) node _T_303 = and(_T_302, asSInt(UInt<29>(0h100000c0))) node _T_304 = asSInt(_T_303) node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0))) node _T_306 = or(_T_300, _T_305) node _T_307 = and(_T_295, _T_306) node _T_308 = or(UInt<1>(0h0), _T_307) node _T_309 = and(_T_291, _T_308) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_309, UInt<1>(0h1), "") : assert_31 node _T_313 = asUInt(reset) node _T_314 = eq(_T_313, UInt<1>(0h0)) when _T_314 : node _T_315 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_315 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_316 = asUInt(reset) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(is_aligned, UInt<1>(0h0)) when _T_318 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_319 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_320 = asUInt(reset) node _T_321 = eq(_T_320, UInt<1>(0h0)) when _T_321 : node _T_322 = eq(_T_319, UInt<1>(0h0)) when _T_322 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_319, UInt<1>(0h1), "") : assert_34 node _T_323 = not(mask) node _T_324 = and(io.in.a.bits.mask, _T_323) node _T_325 = eq(_T_324, UInt<1>(0h0)) node _T_326 = asUInt(reset) node _T_327 = eq(_T_326, UInt<1>(0h0)) when _T_327 : node _T_328 = eq(_T_325, UInt<1>(0h0)) when _T_328 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_325, UInt<1>(0h1), "") : assert_35 node _T_329 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_329 : node _T_330 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_331 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_332 = and(_T_330, _T_331) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 2, 0) node _T_333 = shr(io.in.a.bits.source, 3) node _T_334 = eq(_T_333, UInt<1>(0h0)) node _T_335 = leq(UInt<1>(0h0), uncommonBits_6) node _T_336 = and(_T_334, _T_335) node _T_337 = leq(uncommonBits_6, UInt<3>(0h4)) node _T_338 = and(_T_336, _T_337) node _T_339 = and(_T_332, _T_338) node _T_340 = or(UInt<1>(0h0), _T_339) node _T_341 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_342 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_343 = cvt(_T_342) node _T_344 = and(_T_343, asSInt(UInt<17>(0h100c0))) node _T_345 = asSInt(_T_344) node _T_346 = eq(_T_345, asSInt(UInt<1>(0h0))) node _T_347 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_348 = cvt(_T_347) node _T_349 = and(_T_348, asSInt(UInt<29>(0h100000c0))) node _T_350 = asSInt(_T_349) node _T_351 = eq(_T_350, asSInt(UInt<1>(0h0))) node _T_352 = or(_T_346, _T_351) node _T_353 = and(_T_341, _T_352) node _T_354 = or(UInt<1>(0h0), _T_353) node _T_355 = and(_T_340, _T_354) node _T_356 = asUInt(reset) node _T_357 = eq(_T_356, UInt<1>(0h0)) when _T_357 : node _T_358 = eq(_T_355, UInt<1>(0h0)) when _T_358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_355, UInt<1>(0h1), "") : assert_36 node _T_359 = asUInt(reset) node _T_360 = eq(_T_359, UInt<1>(0h0)) when _T_360 : node _T_361 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(is_aligned, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_365 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_366 = asUInt(reset) node _T_367 = eq(_T_366, UInt<1>(0h0)) when _T_367 : node _T_368 = eq(_T_365, UInt<1>(0h0)) when _T_368 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_365, UInt<1>(0h1), "") : assert_39 node _T_369 = eq(io.in.a.bits.mask, mask) node _T_370 = asUInt(reset) node _T_371 = eq(_T_370, UInt<1>(0h0)) when _T_371 : node _T_372 = eq(_T_369, UInt<1>(0h0)) when _T_372 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_369, UInt<1>(0h1), "") : assert_40 node _T_373 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_373 : node _T_374 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_375 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_376 = and(_T_374, _T_375) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 2, 0) node _T_377 = shr(io.in.a.bits.source, 3) node _T_378 = eq(_T_377, UInt<1>(0h0)) node _T_379 = leq(UInt<1>(0h0), uncommonBits_7) node _T_380 = and(_T_378, _T_379) node _T_381 = leq(uncommonBits_7, UInt<3>(0h4)) node _T_382 = and(_T_380, _T_381) node _T_383 = and(_T_376, _T_382) node _T_384 = or(UInt<1>(0h0), _T_383) node _T_385 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_386 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_387 = cvt(_T_386) node _T_388 = and(_T_387, asSInt(UInt<17>(0h100c0))) node _T_389 = asSInt(_T_388) node _T_390 = eq(_T_389, asSInt(UInt<1>(0h0))) node _T_391 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_392 = cvt(_T_391) node _T_393 = and(_T_392, asSInt(UInt<29>(0h100000c0))) node _T_394 = asSInt(_T_393) node _T_395 = eq(_T_394, asSInt(UInt<1>(0h0))) node _T_396 = or(_T_390, _T_395) node _T_397 = and(_T_385, _T_396) node _T_398 = or(UInt<1>(0h0), _T_397) node _T_399 = and(_T_384, _T_398) node _T_400 = asUInt(reset) node _T_401 = eq(_T_400, UInt<1>(0h0)) when _T_401 : node _T_402 = eq(_T_399, UInt<1>(0h0)) when _T_402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_399, UInt<1>(0h1), "") : assert_41 node _T_403 = asUInt(reset) node _T_404 = eq(_T_403, UInt<1>(0h0)) when _T_404 : node _T_405 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(is_aligned, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_409 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_409, UInt<1>(0h1), "") : assert_44 node _T_413 = eq(io.in.a.bits.mask, mask) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_413, UInt<1>(0h1), "") : assert_45 node _T_417 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_417 : node _T_418 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_419 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_420 = and(_T_418, _T_419) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 2, 0) node _T_421 = shr(io.in.a.bits.source, 3) node _T_422 = eq(_T_421, UInt<1>(0h0)) node _T_423 = leq(UInt<1>(0h0), uncommonBits_8) node _T_424 = and(_T_422, _T_423) node _T_425 = leq(uncommonBits_8, UInt<3>(0h4)) node _T_426 = and(_T_424, _T_425) node _T_427 = and(_T_420, _T_426) node _T_428 = or(UInt<1>(0h0), _T_427) node _T_429 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_430 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_431 = cvt(_T_430) node _T_432 = and(_T_431, asSInt(UInt<17>(0h100c0))) node _T_433 = asSInt(_T_432) node _T_434 = eq(_T_433, asSInt(UInt<1>(0h0))) node _T_435 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_436 = cvt(_T_435) node _T_437 = and(_T_436, asSInt(UInt<29>(0h100000c0))) node _T_438 = asSInt(_T_437) node _T_439 = eq(_T_438, asSInt(UInt<1>(0h0))) node _T_440 = or(_T_434, _T_439) node _T_441 = and(_T_429, _T_440) node _T_442 = or(UInt<1>(0h0), _T_441) node _T_443 = and(_T_428, _T_442) node _T_444 = asUInt(reset) node _T_445 = eq(_T_444, UInt<1>(0h0)) when _T_445 : node _T_446 = eq(_T_443, UInt<1>(0h0)) when _T_446 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_443, UInt<1>(0h1), "") : assert_46 node _T_447 = asUInt(reset) node _T_448 = eq(_T_447, UInt<1>(0h0)) when _T_448 : node _T_449 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(is_aligned, UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_453 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_454 = asUInt(reset) node _T_455 = eq(_T_454, UInt<1>(0h0)) when _T_455 : node _T_456 = eq(_T_453, UInt<1>(0h0)) when _T_456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_453, UInt<1>(0h1), "") : assert_49 node _T_457 = eq(io.in.a.bits.mask, mask) node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_T_457, UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_457, UInt<1>(0h1), "") : assert_50 node _T_461 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_462 = asUInt(reset) node _T_463 = eq(_T_462, UInt<1>(0h0)) when _T_463 : node _T_464 = eq(_T_461, UInt<1>(0h0)) when _T_464 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_461, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_465 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_466 = asUInt(reset) node _T_467 = eq(_T_466, UInt<1>(0h0)) when _T_467 : node _T_468 = eq(_T_465, UInt<1>(0h0)) when _T_468 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_465, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 2, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 3) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<3>(0h4)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_469 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_469 : node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_473 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_474 = asUInt(reset) node _T_475 = eq(_T_474, UInt<1>(0h0)) when _T_475 : node _T_476 = eq(_T_473, UInt<1>(0h0)) when _T_476 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_473, UInt<1>(0h1), "") : assert_54 node _T_477 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_478 = asUInt(reset) node _T_479 = eq(_T_478, UInt<1>(0h0)) when _T_479 : node _T_480 = eq(_T_477, UInt<1>(0h0)) when _T_480 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_477, UInt<1>(0h1), "") : assert_55 node _T_481 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_481, UInt<1>(0h1), "") : assert_56 node _T_485 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_486 = asUInt(reset) node _T_487 = eq(_T_486, UInt<1>(0h0)) when _T_487 : node _T_488 = eq(_T_485, UInt<1>(0h0)) when _T_488 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_485, UInt<1>(0h1), "") : assert_57 node _T_489 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_489 : node _T_490 = asUInt(reset) node _T_491 = eq(_T_490, UInt<1>(0h0)) when _T_491 : node _T_492 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_492 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_493 = asUInt(reset) node _T_494 = eq(_T_493, UInt<1>(0h0)) when _T_494 : node _T_495 = eq(sink_ok, UInt<1>(0h0)) when _T_495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_496 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_497 = asUInt(reset) node _T_498 = eq(_T_497, UInt<1>(0h0)) when _T_498 : node _T_499 = eq(_T_496, UInt<1>(0h0)) when _T_499 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_496, UInt<1>(0h1), "") : assert_60 node _T_500 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_501 = asUInt(reset) node _T_502 = eq(_T_501, UInt<1>(0h0)) when _T_502 : node _T_503 = eq(_T_500, UInt<1>(0h0)) when _T_503 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_500, UInt<1>(0h1), "") : assert_61 node _T_504 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_504, UInt<1>(0h1), "") : assert_62 node _T_508 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_509 = asUInt(reset) node _T_510 = eq(_T_509, UInt<1>(0h0)) when _T_510 : node _T_511 = eq(_T_508, UInt<1>(0h0)) when _T_511 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_508, UInt<1>(0h1), "") : assert_63 node _T_512 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_513 = or(UInt<1>(0h1), _T_512) node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_T_513, UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_513, UInt<1>(0h1), "") : assert_64 node _T_517 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_517 : node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_521 = asUInt(reset) node _T_522 = eq(_T_521, UInt<1>(0h0)) when _T_522 : node _T_523 = eq(sink_ok, UInt<1>(0h0)) when _T_523 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_524 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_525 = asUInt(reset) node _T_526 = eq(_T_525, UInt<1>(0h0)) when _T_526 : node _T_527 = eq(_T_524, UInt<1>(0h0)) when _T_527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_524, UInt<1>(0h1), "") : assert_67 node _T_528 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_529 = asUInt(reset) node _T_530 = eq(_T_529, UInt<1>(0h0)) when _T_530 : node _T_531 = eq(_T_528, UInt<1>(0h0)) when _T_531 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_528, UInt<1>(0h1), "") : assert_68 node _T_532 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_533 = asUInt(reset) node _T_534 = eq(_T_533, UInt<1>(0h0)) when _T_534 : node _T_535 = eq(_T_532, UInt<1>(0h0)) when _T_535 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_532, UInt<1>(0h1), "") : assert_69 node _T_536 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_537 = or(_T_536, io.in.d.bits.corrupt) node _T_538 = asUInt(reset) node _T_539 = eq(_T_538, UInt<1>(0h0)) when _T_539 : node _T_540 = eq(_T_537, UInt<1>(0h0)) when _T_540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_537, UInt<1>(0h1), "") : assert_70 node _T_541 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_542 = or(UInt<1>(0h1), _T_541) node _T_543 = asUInt(reset) node _T_544 = eq(_T_543, UInt<1>(0h0)) when _T_544 : node _T_545 = eq(_T_542, UInt<1>(0h0)) when _T_545 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_542, UInt<1>(0h1), "") : assert_71 node _T_546 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_546 : node _T_547 = asUInt(reset) node _T_548 = eq(_T_547, UInt<1>(0h0)) when _T_548 : node _T_549 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_549 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_550 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_551 = asUInt(reset) node _T_552 = eq(_T_551, UInt<1>(0h0)) when _T_552 : node _T_553 = eq(_T_550, UInt<1>(0h0)) when _T_553 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_550, UInt<1>(0h1), "") : assert_73 node _T_554 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_555 = asUInt(reset) node _T_556 = eq(_T_555, UInt<1>(0h0)) when _T_556 : node _T_557 = eq(_T_554, UInt<1>(0h0)) when _T_557 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_554, UInt<1>(0h1), "") : assert_74 node _T_558 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_559 = or(UInt<1>(0h1), _T_558) node _T_560 = asUInt(reset) node _T_561 = eq(_T_560, UInt<1>(0h0)) when _T_561 : node _T_562 = eq(_T_559, UInt<1>(0h0)) when _T_562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_559, UInt<1>(0h1), "") : assert_75 node _T_563 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_563 : node _T_564 = asUInt(reset) node _T_565 = eq(_T_564, UInt<1>(0h0)) when _T_565 : node _T_566 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_567 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_568 = asUInt(reset) node _T_569 = eq(_T_568, UInt<1>(0h0)) when _T_569 : node _T_570 = eq(_T_567, UInt<1>(0h0)) when _T_570 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_567, UInt<1>(0h1), "") : assert_77 node _T_571 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_572 = or(_T_571, io.in.d.bits.corrupt) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_572, UInt<1>(0h1), "") : assert_78 node _T_576 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_577 = or(UInt<1>(0h1), _T_576) node _T_578 = asUInt(reset) node _T_579 = eq(_T_578, UInt<1>(0h0)) when _T_579 : node _T_580 = eq(_T_577, UInt<1>(0h0)) when _T_580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_577, UInt<1>(0h1), "") : assert_79 node _T_581 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_581 : node _T_582 = asUInt(reset) node _T_583 = eq(_T_582, UInt<1>(0h0)) when _T_583 : node _T_584 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_584 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_585 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_586 = asUInt(reset) node _T_587 = eq(_T_586, UInt<1>(0h0)) when _T_587 : node _T_588 = eq(_T_585, UInt<1>(0h0)) when _T_588 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_585, UInt<1>(0h1), "") : assert_81 node _T_589 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_590 = asUInt(reset) node _T_591 = eq(_T_590, UInt<1>(0h0)) when _T_591 : node _T_592 = eq(_T_589, UInt<1>(0h0)) when _T_592 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_589, UInt<1>(0h1), "") : assert_82 node _T_593 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_594 = or(UInt<1>(0h1), _T_593) node _T_595 = asUInt(reset) node _T_596 = eq(_T_595, UInt<1>(0h0)) when _T_596 : node _T_597 = eq(_T_594, UInt<1>(0h0)) when _T_597 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_594, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_598 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_599 = asUInt(reset) node _T_600 = eq(_T_599, UInt<1>(0h0)) when _T_600 : node _T_601 = eq(_T_598, UInt<1>(0h0)) when _T_601 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_598, UInt<1>(0h1), "") : assert_84 node _uncommonBits_T_9 = or(io.in.b.bits.source, UInt<3>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 2, 0) node _T_602 = shr(io.in.b.bits.source, 3) node _T_603 = eq(_T_602, UInt<1>(0h0)) node _T_604 = leq(UInt<1>(0h0), uncommonBits_9) node _T_605 = and(_T_603, _T_604) node _T_606 = leq(uncommonBits_9, UInt<3>(0h4)) node _T_607 = and(_T_605, _T_606) node _T_608 = eq(_T_607, UInt<1>(0h0)) node _T_609 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<1>(0h0))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = or(_T_608, _T_613) node _T_615 = asUInt(reset) node _T_616 = eq(_T_615, UInt<1>(0h0)) when _T_616 : node _T_617 = eq(_T_614, UInt<1>(0h0)) when _T_617 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_614, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<17>(0h100c0))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<29>(0h100000c0))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[2] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 node address_ok = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _is_aligned_mask_T_2 = dshl(UInt<6>(0h3f), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 5, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3)) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_8 = and(mask_size_1, mask_eq_8) node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_9 = and(mask_size_1, mask_eq_9) node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_10 = and(mask_size_1, mask_eq_10) node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_11 = and(mask_size_1, mask_eq_11) node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_12 = and(mask_size_1, mask_eq_12) node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_13 = and(mask_size_1, mask_eq_13) node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_14 = and(mask_size_1, mask_eq_14) node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_15 = and(mask_size_1, mask_eq_15) node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15) node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8) node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<3>(0h0)) node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 2, 0) node _legal_source_T = shr(io.in.b.bits.source, 3) node _legal_source_T_1 = eq(_legal_source_T, UInt<1>(0h0)) node _legal_source_T_2 = leq(UInt<1>(0h0), legal_source_uncommonBits) node _legal_source_T_3 = and(_legal_source_T_1, _legal_source_T_2) node _legal_source_T_4 = leq(legal_source_uncommonBits, UInt<3>(0h4)) node _legal_source_T_5 = and(_legal_source_T_3, _legal_source_T_4) wire _legal_source_WIRE : UInt<1>[1] connect _legal_source_WIRE[0], _legal_source_T_5 node legal_source = eq(UInt<1>(0h0), io.in.b.bits.source) node _T_618 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_618 : node _T_619 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_620 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_621 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_622 = and(_T_620, _T_621) node _T_623 = or(UInt<1>(0h0), _T_622) node _T_624 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_625 = cvt(_T_624) node _T_626 = and(_T_625, asSInt(UInt<17>(0h100c0))) node _T_627 = asSInt(_T_626) node _T_628 = eq(_T_627, asSInt(UInt<1>(0h0))) node _T_629 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_630 = cvt(_T_629) node _T_631 = and(_T_630, asSInt(UInt<29>(0h100000c0))) node _T_632 = asSInt(_T_631) node _T_633 = eq(_T_632, asSInt(UInt<1>(0h0))) node _T_634 = or(_T_628, _T_633) node _T_635 = and(_T_623, _T_634) node _T_636 = or(UInt<1>(0h0), _T_635) node _T_637 = and(_T_619, _T_636) node _T_638 = asUInt(reset) node _T_639 = eq(_T_638, UInt<1>(0h0)) when _T_639 : node _T_640 = eq(_T_637, UInt<1>(0h0)) when _T_640 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_637, UInt<1>(0h1), "") : assert_86 node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(address_ok, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_644 = asUInt(reset) node _T_645 = eq(_T_644, UInt<1>(0h0)) when _T_645 : node _T_646 = eq(legal_source, UInt<1>(0h0)) when _T_646 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_647 = asUInt(reset) node _T_648 = eq(_T_647, UInt<1>(0h0)) when _T_648 : node _T_649 = eq(is_aligned_1, UInt<1>(0h0)) when _T_649 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_650 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_651 = asUInt(reset) node _T_652 = eq(_T_651, UInt<1>(0h0)) when _T_652 : node _T_653 = eq(_T_650, UInt<1>(0h0)) when _T_653 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_650, UInt<1>(0h1), "") : assert_90 node _T_654 = eq(io.in.b.bits.mask, mask_1) node _T_655 = asUInt(reset) node _T_656 = eq(_T_655, UInt<1>(0h0)) when _T_656 : node _T_657 = eq(_T_654, UInt<1>(0h0)) when _T_657 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_654, UInt<1>(0h1), "") : assert_91 node _T_658 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_659 = asUInt(reset) node _T_660 = eq(_T_659, UInt<1>(0h0)) when _T_660 : node _T_661 = eq(_T_658, UInt<1>(0h0)) when _T_661 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_658, UInt<1>(0h1), "") : assert_92 node _T_662 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_662 : node _T_663 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_664 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_665 = and(_T_663, _T_664) node _T_666 = or(UInt<1>(0h0), _T_665) node _T_667 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_668 = cvt(_T_667) node _T_669 = and(_T_668, asSInt(UInt<17>(0h100c0))) node _T_670 = asSInt(_T_669) node _T_671 = eq(_T_670, asSInt(UInt<1>(0h0))) node _T_672 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_673 = cvt(_T_672) node _T_674 = and(_T_673, asSInt(UInt<29>(0h100000c0))) node _T_675 = asSInt(_T_674) node _T_676 = eq(_T_675, asSInt(UInt<1>(0h0))) node _T_677 = or(_T_671, _T_676) node _T_678 = and(_T_666, _T_677) node _T_679 = or(UInt<1>(0h0), _T_678) node _T_680 = and(UInt<1>(0h0), _T_679) node _T_681 = asUInt(reset) node _T_682 = eq(_T_681, UInt<1>(0h0)) when _T_682 : node _T_683 = eq(_T_680, UInt<1>(0h0)) when _T_683 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_680, UInt<1>(0h1), "") : assert_93 node _T_684 = asUInt(reset) node _T_685 = eq(_T_684, UInt<1>(0h0)) when _T_685 : node _T_686 = eq(address_ok, UInt<1>(0h0)) when _T_686 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_687 = asUInt(reset) node _T_688 = eq(_T_687, UInt<1>(0h0)) when _T_688 : node _T_689 = eq(legal_source, UInt<1>(0h0)) when _T_689 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_690 = asUInt(reset) node _T_691 = eq(_T_690, UInt<1>(0h0)) when _T_691 : node _T_692 = eq(is_aligned_1, UInt<1>(0h0)) when _T_692 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_693 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_694 = asUInt(reset) node _T_695 = eq(_T_694, UInt<1>(0h0)) when _T_695 : node _T_696 = eq(_T_693, UInt<1>(0h0)) when _T_696 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_693, UInt<1>(0h1), "") : assert_97 node _T_697 = eq(io.in.b.bits.mask, mask_1) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_697, UInt<1>(0h1), "") : assert_98 node _T_701 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_701, UInt<1>(0h1), "") : assert_99 node _T_705 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_705 : node _T_706 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_707 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_708 = and(_T_706, _T_707) node _T_709 = or(UInt<1>(0h0), _T_708) node _T_710 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_711 = cvt(_T_710) node _T_712 = and(_T_711, asSInt(UInt<17>(0h100c0))) node _T_713 = asSInt(_T_712) node _T_714 = eq(_T_713, asSInt(UInt<1>(0h0))) node _T_715 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_716 = cvt(_T_715) node _T_717 = and(_T_716, asSInt(UInt<29>(0h100000c0))) node _T_718 = asSInt(_T_717) node _T_719 = eq(_T_718, asSInt(UInt<1>(0h0))) node _T_720 = or(_T_714, _T_719) node _T_721 = and(_T_709, _T_720) node _T_722 = or(UInt<1>(0h0), _T_721) node _T_723 = and(UInt<1>(0h0), _T_722) node _T_724 = asUInt(reset) node _T_725 = eq(_T_724, UInt<1>(0h0)) when _T_725 : node _T_726 = eq(_T_723, UInt<1>(0h0)) when _T_726 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_723, UInt<1>(0h1), "") : assert_100 node _T_727 = asUInt(reset) node _T_728 = eq(_T_727, UInt<1>(0h0)) when _T_728 : node _T_729 = eq(address_ok, UInt<1>(0h0)) when _T_729 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_730 = asUInt(reset) node _T_731 = eq(_T_730, UInt<1>(0h0)) when _T_731 : node _T_732 = eq(legal_source, UInt<1>(0h0)) when _T_732 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_733 = asUInt(reset) node _T_734 = eq(_T_733, UInt<1>(0h0)) when _T_734 : node _T_735 = eq(is_aligned_1, UInt<1>(0h0)) when _T_735 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_736 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_737 = asUInt(reset) node _T_738 = eq(_T_737, UInt<1>(0h0)) when _T_738 : node _T_739 = eq(_T_736, UInt<1>(0h0)) when _T_739 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_736, UInt<1>(0h1), "") : assert_104 node _T_740 = eq(io.in.b.bits.mask, mask_1) node _T_741 = asUInt(reset) node _T_742 = eq(_T_741, UInt<1>(0h0)) when _T_742 : node _T_743 = eq(_T_740, UInt<1>(0h0)) when _T_743 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_740, UInt<1>(0h1), "") : assert_105 node _T_744 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_744 : node _T_745 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_746 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_747 = and(_T_745, _T_746) node _T_748 = or(UInt<1>(0h0), _T_747) node _T_749 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_750 = cvt(_T_749) node _T_751 = and(_T_750, asSInt(UInt<17>(0h100c0))) node _T_752 = asSInt(_T_751) node _T_753 = eq(_T_752, asSInt(UInt<1>(0h0))) node _T_754 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_755 = cvt(_T_754) node _T_756 = and(_T_755, asSInt(UInt<29>(0h100000c0))) node _T_757 = asSInt(_T_756) node _T_758 = eq(_T_757, asSInt(UInt<1>(0h0))) node _T_759 = or(_T_753, _T_758) node _T_760 = and(_T_748, _T_759) node _T_761 = or(UInt<1>(0h0), _T_760) node _T_762 = and(UInt<1>(0h0), _T_761) node _T_763 = asUInt(reset) node _T_764 = eq(_T_763, UInt<1>(0h0)) when _T_764 : node _T_765 = eq(_T_762, UInt<1>(0h0)) when _T_765 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_762, UInt<1>(0h1), "") : assert_106 node _T_766 = asUInt(reset) node _T_767 = eq(_T_766, UInt<1>(0h0)) when _T_767 : node _T_768 = eq(address_ok, UInt<1>(0h0)) when _T_768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_769 = asUInt(reset) node _T_770 = eq(_T_769, UInt<1>(0h0)) when _T_770 : node _T_771 = eq(legal_source, UInt<1>(0h0)) when _T_771 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_772 = asUInt(reset) node _T_773 = eq(_T_772, UInt<1>(0h0)) when _T_773 : node _T_774 = eq(is_aligned_1, UInt<1>(0h0)) when _T_774 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_775 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_776 = asUInt(reset) node _T_777 = eq(_T_776, UInt<1>(0h0)) when _T_777 : node _T_778 = eq(_T_775, UInt<1>(0h0)) when _T_778 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_775, UInt<1>(0h1), "") : assert_110 node _T_779 = not(mask_1) node _T_780 = and(io.in.b.bits.mask, _T_779) node _T_781 = eq(_T_780, UInt<1>(0h0)) node _T_782 = asUInt(reset) node _T_783 = eq(_T_782, UInt<1>(0h0)) when _T_783 : node _T_784 = eq(_T_781, UInt<1>(0h0)) when _T_784 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_781, UInt<1>(0h1), "") : assert_111 node _T_785 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_785 : node _T_786 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_787 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_788 = and(_T_786, _T_787) node _T_789 = or(UInt<1>(0h0), _T_788) node _T_790 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_791 = cvt(_T_790) node _T_792 = and(_T_791, asSInt(UInt<17>(0h100c0))) node _T_793 = asSInt(_T_792) node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0))) node _T_795 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_796 = cvt(_T_795) node _T_797 = and(_T_796, asSInt(UInt<29>(0h100000c0))) node _T_798 = asSInt(_T_797) node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0))) node _T_800 = or(_T_794, _T_799) node _T_801 = and(_T_789, _T_800) node _T_802 = or(UInt<1>(0h0), _T_801) node _T_803 = and(UInt<1>(0h0), _T_802) node _T_804 = asUInt(reset) node _T_805 = eq(_T_804, UInt<1>(0h0)) when _T_805 : node _T_806 = eq(_T_803, UInt<1>(0h0)) when _T_806 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_803, UInt<1>(0h1), "") : assert_112 node _T_807 = asUInt(reset) node _T_808 = eq(_T_807, UInt<1>(0h0)) when _T_808 : node _T_809 = eq(address_ok, UInt<1>(0h0)) when _T_809 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_810 = asUInt(reset) node _T_811 = eq(_T_810, UInt<1>(0h0)) when _T_811 : node _T_812 = eq(legal_source, UInt<1>(0h0)) when _T_812 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_813 = asUInt(reset) node _T_814 = eq(_T_813, UInt<1>(0h0)) when _T_814 : node _T_815 = eq(is_aligned_1, UInt<1>(0h0)) when _T_815 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_816 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_817 = asUInt(reset) node _T_818 = eq(_T_817, UInt<1>(0h0)) when _T_818 : node _T_819 = eq(_T_816, UInt<1>(0h0)) when _T_819 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_816, UInt<1>(0h1), "") : assert_116 node _T_820 = eq(io.in.b.bits.mask, mask_1) node _T_821 = asUInt(reset) node _T_822 = eq(_T_821, UInt<1>(0h0)) when _T_822 : node _T_823 = eq(_T_820, UInt<1>(0h0)) when _T_823 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_820, UInt<1>(0h1), "") : assert_117 node _T_824 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_824 : node _T_825 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_826 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_827 = and(_T_825, _T_826) node _T_828 = or(UInt<1>(0h0), _T_827) node _T_829 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_830 = cvt(_T_829) node _T_831 = and(_T_830, asSInt(UInt<17>(0h100c0))) node _T_832 = asSInt(_T_831) node _T_833 = eq(_T_832, asSInt(UInt<1>(0h0))) node _T_834 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_835 = cvt(_T_834) node _T_836 = and(_T_835, asSInt(UInt<29>(0h100000c0))) node _T_837 = asSInt(_T_836) node _T_838 = eq(_T_837, asSInt(UInt<1>(0h0))) node _T_839 = or(_T_833, _T_838) node _T_840 = and(_T_828, _T_839) node _T_841 = or(UInt<1>(0h0), _T_840) node _T_842 = and(UInt<1>(0h0), _T_841) node _T_843 = asUInt(reset) node _T_844 = eq(_T_843, UInt<1>(0h0)) when _T_844 : node _T_845 = eq(_T_842, UInt<1>(0h0)) when _T_845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_842, UInt<1>(0h1), "") : assert_118 node _T_846 = asUInt(reset) node _T_847 = eq(_T_846, UInt<1>(0h0)) when _T_847 : node _T_848 = eq(address_ok, UInt<1>(0h0)) when _T_848 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_849 = asUInt(reset) node _T_850 = eq(_T_849, UInt<1>(0h0)) when _T_850 : node _T_851 = eq(legal_source, UInt<1>(0h0)) when _T_851 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_852 = asUInt(reset) node _T_853 = eq(_T_852, UInt<1>(0h0)) when _T_853 : node _T_854 = eq(is_aligned_1, UInt<1>(0h0)) when _T_854 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_855 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_856 = asUInt(reset) node _T_857 = eq(_T_856, UInt<1>(0h0)) when _T_857 : node _T_858 = eq(_T_855, UInt<1>(0h0)) when _T_858 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_855, UInt<1>(0h1), "") : assert_122 node _T_859 = eq(io.in.b.bits.mask, mask_1) node _T_860 = asUInt(reset) node _T_861 = eq(_T_860, UInt<1>(0h0)) when _T_861 : node _T_862 = eq(_T_859, UInt<1>(0h0)) when _T_862 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_859, UInt<1>(0h1), "") : assert_123 node _T_863 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_863 : node _T_864 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_865 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_866 = and(_T_864, _T_865) node _T_867 = or(UInt<1>(0h0), _T_866) node _T_868 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_869 = cvt(_T_868) node _T_870 = and(_T_869, asSInt(UInt<17>(0h100c0))) node _T_871 = asSInt(_T_870) node _T_872 = eq(_T_871, asSInt(UInt<1>(0h0))) node _T_873 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_874 = cvt(_T_873) node _T_875 = and(_T_874, asSInt(UInt<29>(0h100000c0))) node _T_876 = asSInt(_T_875) node _T_877 = eq(_T_876, asSInt(UInt<1>(0h0))) node _T_878 = or(_T_872, _T_877) node _T_879 = and(_T_867, _T_878) node _T_880 = or(UInt<1>(0h0), _T_879) node _T_881 = and(UInt<1>(0h0), _T_880) node _T_882 = asUInt(reset) node _T_883 = eq(_T_882, UInt<1>(0h0)) when _T_883 : node _T_884 = eq(_T_881, UInt<1>(0h0)) when _T_884 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_881, UInt<1>(0h1), "") : assert_124 node _T_885 = asUInt(reset) node _T_886 = eq(_T_885, UInt<1>(0h0)) when _T_886 : node _T_887 = eq(address_ok, UInt<1>(0h0)) when _T_887 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_888 = asUInt(reset) node _T_889 = eq(_T_888, UInt<1>(0h0)) when _T_889 : node _T_890 = eq(legal_source, UInt<1>(0h0)) when _T_890 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_891 = asUInt(reset) node _T_892 = eq(_T_891, UInt<1>(0h0)) when _T_892 : node _T_893 = eq(is_aligned_1, UInt<1>(0h0)) when _T_893 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_894 = eq(io.in.b.bits.mask, mask_1) node _T_895 = asUInt(reset) node _T_896 = eq(_T_895, UInt<1>(0h0)) when _T_896 : node _T_897 = eq(_T_894, UInt<1>(0h0)) when _T_897 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_894, UInt<1>(0h1), "") : assert_128 node _T_898 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_899 = asUInt(reset) node _T_900 = eq(_T_899, UInt<1>(0h0)) when _T_900 : node _T_901 = eq(_T_898, UInt<1>(0h0)) when _T_901 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_898, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_902 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_903 = asUInt(reset) node _T_904 = eq(_T_903, UInt<1>(0h0)) when _T_904 : node _T_905 = eq(_T_902, UInt<1>(0h0)) when _T_905 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_902, UInt<1>(0h1), "") : assert_130 node _source_ok_uncommonBits_T_2 = or(io.in.c.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 2, 0) node _source_ok_T_12 = shr(io.in.c.bits.source, 3) node _source_ok_T_13 = eq(_source_ok_T_12, UInt<1>(0h0)) node _source_ok_T_14 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_15 = and(_source_ok_T_13, _source_ok_T_14) node _source_ok_T_16 = leq(source_ok_uncommonBits_2, UInt<3>(0h4)) node _source_ok_T_17 = and(_source_ok_T_15, _source_ok_T_16) wire _source_ok_WIRE_2 : UInt<1>[1] connect _source_ok_WIRE_2[0], _source_ok_T_17 node _is_aligned_mask_T_4 = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 5, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_10 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<17>(0h100c0))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<29>(0h100000c0))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[2] connect _address_ok_WIRE_1[0], _address_ok_T_14 connect _address_ok_WIRE_1[1], _address_ok_T_19 node address_ok_1 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _uncommonBits_T_10 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 2, 0) node _T_906 = shr(io.in.c.bits.source, 3) node _T_907 = eq(_T_906, UInt<1>(0h0)) node _T_908 = leq(UInt<1>(0h0), uncommonBits_10) node _T_909 = and(_T_907, _T_908) node _T_910 = leq(uncommonBits_10, UInt<3>(0h4)) node _T_911 = and(_T_909, _T_910) node _T_912 = eq(_T_911, UInt<1>(0h0)) node _T_913 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_914 = cvt(_T_913) node _T_915 = and(_T_914, asSInt(UInt<1>(0h0))) node _T_916 = asSInt(_T_915) node _T_917 = eq(_T_916, asSInt(UInt<1>(0h0))) node _T_918 = or(_T_912, _T_917) node _T_919 = asUInt(reset) node _T_920 = eq(_T_919, UInt<1>(0h0)) when _T_920 : node _T_921 = eq(_T_918, UInt<1>(0h0)) when _T_921 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_918, UInt<1>(0h1), "") : assert_131 node _T_922 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_922 : node _T_923 = asUInt(reset) node _T_924 = eq(_T_923, UInt<1>(0h0)) when _T_924 : node _T_925 = eq(address_ok_1, UInt<1>(0h0)) when _T_925 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_133 node _T_929 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_T_929, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_929, UInt<1>(0h1), "") : assert_134 node _T_933 = asUInt(reset) node _T_934 = eq(_T_933, UInt<1>(0h0)) when _T_934 : node _T_935 = eq(is_aligned_2, UInt<1>(0h0)) when _T_935 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_936 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_937 = asUInt(reset) node _T_938 = eq(_T_937, UInt<1>(0h0)) when _T_938 : node _T_939 = eq(_T_936, UInt<1>(0h0)) when _T_939 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_936, UInt<1>(0h1), "") : assert_136 node _T_940 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_941 = asUInt(reset) node _T_942 = eq(_T_941, UInt<1>(0h0)) when _T_942 : node _T_943 = eq(_T_940, UInt<1>(0h0)) when _T_943 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_940, UInt<1>(0h1), "") : assert_137 node _T_944 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_944 : node _T_945 = asUInt(reset) node _T_946 = eq(_T_945, UInt<1>(0h0)) when _T_946 : node _T_947 = eq(address_ok_1, UInt<1>(0h0)) when _T_947 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_948 = asUInt(reset) node _T_949 = eq(_T_948, UInt<1>(0h0)) when _T_949 : node _T_950 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0)) when _T_950 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_139 node _T_951 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_952 = asUInt(reset) node _T_953 = eq(_T_952, UInt<1>(0h0)) when _T_953 : node _T_954 = eq(_T_951, UInt<1>(0h0)) when _T_954 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_951, UInt<1>(0h1), "") : assert_140 node _T_955 = asUInt(reset) node _T_956 = eq(_T_955, UInt<1>(0h0)) when _T_956 : node _T_957 = eq(is_aligned_2, UInt<1>(0h0)) when _T_957 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_958 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_959 = asUInt(reset) node _T_960 = eq(_T_959, UInt<1>(0h0)) when _T_960 : node _T_961 = eq(_T_958, UInt<1>(0h0)) when _T_961 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_958, UInt<1>(0h1), "") : assert_142 node _T_962 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_962 : node _T_963 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_964 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_965 = and(_T_963, _T_964) node _uncommonBits_T_11 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 2, 0) node _T_966 = shr(io.in.c.bits.source, 3) node _T_967 = eq(_T_966, UInt<1>(0h0)) node _T_968 = leq(UInt<1>(0h0), uncommonBits_11) node _T_969 = and(_T_967, _T_968) node _T_970 = leq(uncommonBits_11, UInt<3>(0h4)) node _T_971 = and(_T_969, _T_970) node _T_972 = and(_T_965, _T_971) node _T_973 = or(UInt<1>(0h0), _T_972) node _T_974 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_975 = leq(io.in.c.bits.size, UInt<3>(0h6)) node _T_976 = and(_T_974, _T_975) node _T_977 = or(UInt<1>(0h0), _T_976) node _T_978 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_979 = cvt(_T_978) node _T_980 = and(_T_979, asSInt(UInt<17>(0h100c0))) node _T_981 = asSInt(_T_980) node _T_982 = eq(_T_981, asSInt(UInt<1>(0h0))) node _T_983 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_984 = cvt(_T_983) node _T_985 = and(_T_984, asSInt(UInt<29>(0h100000c0))) node _T_986 = asSInt(_T_985) node _T_987 = eq(_T_986, asSInt(UInt<1>(0h0))) node _T_988 = or(_T_982, _T_987) node _T_989 = and(_T_977, _T_988) node _T_990 = or(UInt<1>(0h0), _T_989) node _T_991 = and(_T_973, _T_990) node _T_992 = asUInt(reset) node _T_993 = eq(_T_992, UInt<1>(0h0)) when _T_993 : node _T_994 = eq(_T_991, UInt<1>(0h0)) when _T_994 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_991, UInt<1>(0h1), "") : assert_143 node _T_995 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_996 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_997 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_998 = and(_T_996, _T_997) node _T_999 = or(UInt<1>(0h0), _T_998) node _T_1000 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1001 = cvt(_T_1000) node _T_1002 = and(_T_1001, asSInt(UInt<17>(0h100c0))) node _T_1003 = asSInt(_T_1002) node _T_1004 = eq(_T_1003, asSInt(UInt<1>(0h0))) node _T_1005 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1006 = cvt(_T_1005) node _T_1007 = and(_T_1006, asSInt(UInt<29>(0h100000c0))) node _T_1008 = asSInt(_T_1007) node _T_1009 = eq(_T_1008, asSInt(UInt<1>(0h0))) node _T_1010 = or(_T_1004, _T_1009) node _T_1011 = and(_T_999, _T_1010) node _T_1012 = or(UInt<1>(0h0), _T_1011) node _T_1013 = and(_T_995, _T_1012) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_144 node _T_1017 = asUInt(reset) node _T_1018 = eq(_T_1017, UInt<1>(0h0)) when _T_1018 : node _T_1019 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0)) when _T_1019 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_145 node _T_1020 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1021 = asUInt(reset) node _T_1022 = eq(_T_1021, UInt<1>(0h0)) when _T_1022 : node _T_1023 = eq(_T_1020, UInt<1>(0h0)) when _T_1023 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_1020, UInt<1>(0h1), "") : assert_146 node _T_1024 = asUInt(reset) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_1027 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1028 = asUInt(reset) node _T_1029 = eq(_T_1028, UInt<1>(0h0)) when _T_1029 : node _T_1030 = eq(_T_1027, UInt<1>(0h0)) when _T_1030 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_1027, UInt<1>(0h1), "") : assert_148 node _T_1031 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1032 = asUInt(reset) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) when _T_1033 : node _T_1034 = eq(_T_1031, UInt<1>(0h0)) when _T_1034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_1031, UInt<1>(0h1), "") : assert_149 node _T_1035 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_1035 : node _T_1036 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1037 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1038 = and(_T_1036, _T_1037) node _uncommonBits_T_12 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 2, 0) node _T_1039 = shr(io.in.c.bits.source, 3) node _T_1040 = eq(_T_1039, UInt<1>(0h0)) node _T_1041 = leq(UInt<1>(0h0), uncommonBits_12) node _T_1042 = and(_T_1040, _T_1041) node _T_1043 = leq(uncommonBits_12, UInt<3>(0h4)) node _T_1044 = and(_T_1042, _T_1043) node _T_1045 = and(_T_1038, _T_1044) node _T_1046 = or(UInt<1>(0h0), _T_1045) node _T_1047 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1048 = leq(io.in.c.bits.size, UInt<3>(0h6)) node _T_1049 = and(_T_1047, _T_1048) node _T_1050 = or(UInt<1>(0h0), _T_1049) node _T_1051 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1052 = cvt(_T_1051) node _T_1053 = and(_T_1052, asSInt(UInt<17>(0h100c0))) node _T_1054 = asSInt(_T_1053) node _T_1055 = eq(_T_1054, asSInt(UInt<1>(0h0))) node _T_1056 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1057 = cvt(_T_1056) node _T_1058 = and(_T_1057, asSInt(UInt<29>(0h100000c0))) node _T_1059 = asSInt(_T_1058) node _T_1060 = eq(_T_1059, asSInt(UInt<1>(0h0))) node _T_1061 = or(_T_1055, _T_1060) node _T_1062 = and(_T_1050, _T_1061) node _T_1063 = or(UInt<1>(0h0), _T_1062) node _T_1064 = and(_T_1046, _T_1063) node _T_1065 = asUInt(reset) node _T_1066 = eq(_T_1065, UInt<1>(0h0)) when _T_1066 : node _T_1067 = eq(_T_1064, UInt<1>(0h0)) when _T_1067 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_1064, UInt<1>(0h1), "") : assert_150 node _T_1068 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1069 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1070 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1071 = and(_T_1069, _T_1070) node _T_1072 = or(UInt<1>(0h0), _T_1071) node _T_1073 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1074 = cvt(_T_1073) node _T_1075 = and(_T_1074, asSInt(UInt<17>(0h100c0))) node _T_1076 = asSInt(_T_1075) node _T_1077 = eq(_T_1076, asSInt(UInt<1>(0h0))) node _T_1078 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1079 = cvt(_T_1078) node _T_1080 = and(_T_1079, asSInt(UInt<29>(0h100000c0))) node _T_1081 = asSInt(_T_1080) node _T_1082 = eq(_T_1081, asSInt(UInt<1>(0h0))) node _T_1083 = or(_T_1077, _T_1082) node _T_1084 = and(_T_1072, _T_1083) node _T_1085 = or(UInt<1>(0h0), _T_1084) node _T_1086 = and(_T_1068, _T_1085) node _T_1087 = asUInt(reset) node _T_1088 = eq(_T_1087, UInt<1>(0h0)) when _T_1088 : node _T_1089 = eq(_T_1086, UInt<1>(0h0)) when _T_1089 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_1086, UInt<1>(0h1), "") : assert_151 node _T_1090 = asUInt(reset) node _T_1091 = eq(_T_1090, UInt<1>(0h0)) when _T_1091 : node _T_1092 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0)) when _T_1092 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_152 node _T_1093 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1094 = asUInt(reset) node _T_1095 = eq(_T_1094, UInt<1>(0h0)) when _T_1095 : node _T_1096 = eq(_T_1093, UInt<1>(0h0)) when _T_1096 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_1093, UInt<1>(0h1), "") : assert_153 node _T_1097 = asUInt(reset) node _T_1098 = eq(_T_1097, UInt<1>(0h0)) when _T_1098 : node _T_1099 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1099 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_1100 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1101 = asUInt(reset) node _T_1102 = eq(_T_1101, UInt<1>(0h0)) when _T_1102 : node _T_1103 = eq(_T_1100, UInt<1>(0h0)) when _T_1103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_1100, UInt<1>(0h1), "") : assert_155 node _T_1104 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_1104 : node _T_1105 = asUInt(reset) node _T_1106 = eq(_T_1105, UInt<1>(0h0)) when _T_1106 : node _T_1107 = eq(address_ok_1, UInt<1>(0h0)) when _T_1107 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_1108 = asUInt(reset) node _T_1109 = eq(_T_1108, UInt<1>(0h0)) when _T_1109 : node _T_1110 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0)) when _T_1110 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_157 node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_1114 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_1115 = asUInt(reset) node _T_1116 = eq(_T_1115, UInt<1>(0h0)) when _T_1116 : node _T_1117 = eq(_T_1114, UInt<1>(0h0)) when _T_1117 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_1114, UInt<1>(0h1), "") : assert_159 node _T_1118 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1119 = asUInt(reset) node _T_1120 = eq(_T_1119, UInt<1>(0h0)) when _T_1120 : node _T_1121 = eq(_T_1118, UInt<1>(0h0)) when _T_1121 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_1118, UInt<1>(0h1), "") : assert_160 node _T_1122 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_1122 : node _T_1123 = asUInt(reset) node _T_1124 = eq(_T_1123, UInt<1>(0h0)) when _T_1124 : node _T_1125 = eq(address_ok_1, UInt<1>(0h0)) when _T_1125 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_1126 = asUInt(reset) node _T_1127 = eq(_T_1126, UInt<1>(0h0)) when _T_1127 : node _T_1128 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0)) when _T_1128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_162 node _T_1129 = asUInt(reset) node _T_1130 = eq(_T_1129, UInt<1>(0h0)) when _T_1130 : node _T_1131 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1131 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_1132 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_1133 = asUInt(reset) node _T_1134 = eq(_T_1133, UInt<1>(0h0)) when _T_1134 : node _T_1135 = eq(_T_1132, UInt<1>(0h0)) when _T_1135 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_1132, UInt<1>(0h1), "") : assert_164 node _T_1136 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_1136 : node _T_1137 = asUInt(reset) node _T_1138 = eq(_T_1137, UInt<1>(0h0)) when _T_1138 : node _T_1139 = eq(address_ok_1, UInt<1>(0h0)) when _T_1139 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_1140 = asUInt(reset) node _T_1141 = eq(_T_1140, UInt<1>(0h0)) when _T_1141 : node _T_1142 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0)) when _T_1142 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_166 node _T_1143 = asUInt(reset) node _T_1144 = eq(_T_1143, UInt<1>(0h0)) when _T_1144 : node _T_1145 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1145 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_1146 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_1147 = asUInt(reset) node _T_1148 = eq(_T_1147, UInt<1>(0h0)) when _T_1148 : node _T_1149 = eq(_T_1146, UInt<1>(0h0)) when _T_1149 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_1146, UInt<1>(0h1), "") : assert_168 node _T_1150 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1151 = asUInt(reset) node _T_1152 = eq(_T_1151, UInt<1>(0h0)) when _T_1152 : node _T_1153 = eq(_T_1150, UInt<1>(0h0)) when _T_1153 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_1150, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0h8)) node _T_1154 = asUInt(reset) node _T_1155 = eq(_T_1154, UInt<1>(0h0)) when _T_1155 : node _T_1156 = eq(sink_ok_1, UInt<1>(0h0)) when _T_1156 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1157 = eq(a_first, UInt<1>(0h0)) node _T_1158 = and(io.in.a.valid, _T_1157) when _T_1158 : node _T_1159 = eq(io.in.a.bits.opcode, opcode) node _T_1160 = asUInt(reset) node _T_1161 = eq(_T_1160, UInt<1>(0h0)) when _T_1161 : node _T_1162 = eq(_T_1159, UInt<1>(0h0)) when _T_1162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_1159, UInt<1>(0h1), "") : assert_171 node _T_1163 = eq(io.in.a.bits.param, param) node _T_1164 = asUInt(reset) node _T_1165 = eq(_T_1164, UInt<1>(0h0)) when _T_1165 : node _T_1166 = eq(_T_1163, UInt<1>(0h0)) when _T_1166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_1163, UInt<1>(0h1), "") : assert_172 node _T_1167 = eq(io.in.a.bits.size, size) node _T_1168 = asUInt(reset) node _T_1169 = eq(_T_1168, UInt<1>(0h0)) when _T_1169 : node _T_1170 = eq(_T_1167, UInt<1>(0h0)) when _T_1170 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_1167, UInt<1>(0h1), "") : assert_173 node _T_1171 = eq(io.in.a.bits.source, source) node _T_1172 = asUInt(reset) node _T_1173 = eq(_T_1172, UInt<1>(0h0)) when _T_1173 : node _T_1174 = eq(_T_1171, UInt<1>(0h0)) when _T_1174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_1171, UInt<1>(0h1), "") : assert_174 node _T_1175 = eq(io.in.a.bits.address, address) node _T_1176 = asUInt(reset) node _T_1177 = eq(_T_1176, UInt<1>(0h0)) when _T_1177 : node _T_1178 = eq(_T_1175, UInt<1>(0h0)) when _T_1178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_1175, UInt<1>(0h1), "") : assert_175 node _T_1179 = and(io.in.a.ready, io.in.a.valid) node _T_1180 = and(_T_1179, a_first) when _T_1180 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1181 = eq(d_first, UInt<1>(0h0)) node _T_1182 = and(io.in.d.valid, _T_1181) when _T_1182 : node _T_1183 = eq(io.in.d.bits.opcode, opcode_1) node _T_1184 = asUInt(reset) node _T_1185 = eq(_T_1184, UInt<1>(0h0)) when _T_1185 : node _T_1186 = eq(_T_1183, UInt<1>(0h0)) when _T_1186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_1183, UInt<1>(0h1), "") : assert_176 node _T_1187 = eq(io.in.d.bits.param, param_1) node _T_1188 = asUInt(reset) node _T_1189 = eq(_T_1188, UInt<1>(0h0)) when _T_1189 : node _T_1190 = eq(_T_1187, UInt<1>(0h0)) when _T_1190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_1187, UInt<1>(0h1), "") : assert_177 node _T_1191 = eq(io.in.d.bits.size, size_1) node _T_1192 = asUInt(reset) node _T_1193 = eq(_T_1192, UInt<1>(0h0)) when _T_1193 : node _T_1194 = eq(_T_1191, UInt<1>(0h0)) when _T_1194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_1191, UInt<1>(0h1), "") : assert_178 node _T_1195 = eq(io.in.d.bits.source, source_1) node _T_1196 = asUInt(reset) node _T_1197 = eq(_T_1196, UInt<1>(0h0)) when _T_1197 : node _T_1198 = eq(_T_1195, UInt<1>(0h0)) when _T_1198 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_1195, UInt<1>(0h1), "") : assert_179 node _T_1199 = eq(io.in.d.bits.sink, sink) node _T_1200 = asUInt(reset) node _T_1201 = eq(_T_1200, UInt<1>(0h0)) when _T_1201 : node _T_1202 = eq(_T_1199, UInt<1>(0h0)) when _T_1202 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_1199, UInt<1>(0h1), "") : assert_180 node _T_1203 = eq(io.in.d.bits.denied, denied) node _T_1204 = asUInt(reset) node _T_1205 = eq(_T_1204, UInt<1>(0h0)) when _T_1205 : node _T_1206 = eq(_T_1203, UInt<1>(0h0)) when _T_1206 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_1203, UInt<1>(0h1), "") : assert_181 node _T_1207 = and(io.in.d.ready, io.in.d.valid) node _T_1208 = and(_T_1207, d_first) when _T_1208 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 5, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_1209 = eq(b_first, UInt<1>(0h0)) node _T_1210 = and(io.in.b.valid, _T_1209) when _T_1210 : node _T_1211 = eq(io.in.b.bits.opcode, opcode_2) node _T_1212 = asUInt(reset) node _T_1213 = eq(_T_1212, UInt<1>(0h0)) when _T_1213 : node _T_1214 = eq(_T_1211, UInt<1>(0h0)) when _T_1214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_1211, UInt<1>(0h1), "") : assert_182 node _T_1215 = eq(io.in.b.bits.param, param_2) node _T_1216 = asUInt(reset) node _T_1217 = eq(_T_1216, UInt<1>(0h0)) when _T_1217 : node _T_1218 = eq(_T_1215, UInt<1>(0h0)) when _T_1218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_1215, UInt<1>(0h1), "") : assert_183 node _T_1219 = eq(io.in.b.bits.size, size_2) node _T_1220 = asUInt(reset) node _T_1221 = eq(_T_1220, UInt<1>(0h0)) when _T_1221 : node _T_1222 = eq(_T_1219, UInt<1>(0h0)) when _T_1222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_1219, UInt<1>(0h1), "") : assert_184 node _T_1223 = eq(io.in.b.bits.source, source_2) node _T_1224 = asUInt(reset) node _T_1225 = eq(_T_1224, UInt<1>(0h0)) when _T_1225 : node _T_1226 = eq(_T_1223, UInt<1>(0h0)) when _T_1226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_1223, UInt<1>(0h1), "") : assert_185 node _T_1227 = eq(io.in.b.bits.address, address_1) node _T_1228 = asUInt(reset) node _T_1229 = eq(_T_1228, UInt<1>(0h0)) when _T_1229 : node _T_1230 = eq(_T_1227, UInt<1>(0h0)) when _T_1230 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_1227, UInt<1>(0h1), "") : assert_186 node _T_1231 = and(io.in.b.ready, io.in.b.valid) node _T_1232 = and(_T_1231, b_first) when _T_1232 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_1233 = eq(c_first, UInt<1>(0h0)) node _T_1234 = and(io.in.c.valid, _T_1233) when _T_1234 : node _T_1235 = eq(io.in.c.bits.opcode, opcode_3) node _T_1236 = asUInt(reset) node _T_1237 = eq(_T_1236, UInt<1>(0h0)) when _T_1237 : node _T_1238 = eq(_T_1235, UInt<1>(0h0)) when _T_1238 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_1235, UInt<1>(0h1), "") : assert_187 node _T_1239 = eq(io.in.c.bits.param, param_3) node _T_1240 = asUInt(reset) node _T_1241 = eq(_T_1240, UInt<1>(0h0)) when _T_1241 : node _T_1242 = eq(_T_1239, UInt<1>(0h0)) when _T_1242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_1239, UInt<1>(0h1), "") : assert_188 node _T_1243 = eq(io.in.c.bits.size, size_3) node _T_1244 = asUInt(reset) node _T_1245 = eq(_T_1244, UInt<1>(0h0)) when _T_1245 : node _T_1246 = eq(_T_1243, UInt<1>(0h0)) when _T_1246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_1243, UInt<1>(0h1), "") : assert_189 node _T_1247 = eq(io.in.c.bits.source, source_3) node _T_1248 = asUInt(reset) node _T_1249 = eq(_T_1248, UInt<1>(0h0)) when _T_1249 : node _T_1250 = eq(_T_1247, UInt<1>(0h0)) when _T_1250 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_1247, UInt<1>(0h1), "") : assert_190 node _T_1251 = eq(io.in.c.bits.address, address_2) node _T_1252 = asUInt(reset) node _T_1253 = eq(_T_1252, UInt<1>(0h0)) when _T_1253 : node _T_1254 = eq(_T_1251, UInt<1>(0h0)) when _T_1254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_1251, UInt<1>(0h1), "") : assert_191 node _T_1255 = and(io.in.c.ready, io.in.c.valid) node _T_1256 = and(_T_1255, c_first) when _T_1256 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<5>, clock, reset, UInt<5>(0h0) regreset inflight_opcodes : UInt<20>, clock, reset, UInt<20>(0h0) regreset inflight_sizes : UInt<20>, clock, reset, UInt<20>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<5> connect a_set, UInt<5>(0h0) wire a_set_wo_ready : UInt<5> connect a_set_wo_ready, UInt<5>(0h0) wire a_opcodes_set : UInt<20> connect a_opcodes_set, UInt<20>(0h0) wire a_sizes_set : UInt<20> connect a_sizes_set, UInt<20>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1257 = and(io.in.a.valid, a_first_1) node _T_1258 = and(_T_1257, UInt<1>(0h1)) when _T_1258 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1259 = and(io.in.a.ready, io.in.a.valid) node _T_1260 = and(_T_1259, a_first_1) node _T_1261 = and(_T_1260, UInt<1>(0h1)) when _T_1261 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1262 = dshr(inflight, io.in.a.bits.source) node _T_1263 = bits(_T_1262, 0, 0) node _T_1264 = eq(_T_1263, UInt<1>(0h0)) node _T_1265 = asUInt(reset) node _T_1266 = eq(_T_1265, UInt<1>(0h0)) when _T_1266 : node _T_1267 = eq(_T_1264, UInt<1>(0h0)) when _T_1267 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_1264, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<5> connect d_clr, UInt<5>(0h0) wire d_clr_wo_ready : UInt<5> connect d_clr_wo_ready, UInt<5>(0h0) wire d_opcodes_clr : UInt<20> connect d_opcodes_clr, UInt<20>(0h0) wire d_sizes_clr : UInt<20> connect d_sizes_clr, UInt<20>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1268 = and(io.in.d.valid, d_first_1) node _T_1269 = and(_T_1268, UInt<1>(0h1)) node _T_1270 = eq(d_release_ack, UInt<1>(0h0)) node _T_1271 = and(_T_1269, _T_1270) when _T_1271 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1272 = and(io.in.d.ready, io.in.d.valid) node _T_1273 = and(_T_1272, d_first_1) node _T_1274 = and(_T_1273, UInt<1>(0h1)) node _T_1275 = eq(d_release_ack, UInt<1>(0h0)) node _T_1276 = and(_T_1274, _T_1275) when _T_1276 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1277 = and(io.in.d.valid, d_first_1) node _T_1278 = and(_T_1277, UInt<1>(0h1)) node _T_1279 = eq(d_release_ack, UInt<1>(0h0)) node _T_1280 = and(_T_1278, _T_1279) when _T_1280 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1281 = dshr(inflight, io.in.d.bits.source) node _T_1282 = bits(_T_1281, 0, 0) node _T_1283 = or(_T_1282, same_cycle_resp) node _T_1284 = asUInt(reset) node _T_1285 = eq(_T_1284, UInt<1>(0h0)) when _T_1285 : node _T_1286 = eq(_T_1283, UInt<1>(0h0)) when _T_1286 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_1283, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_1287 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1288 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1289 = or(_T_1287, _T_1288) node _T_1290 = asUInt(reset) node _T_1291 = eq(_T_1290, UInt<1>(0h0)) when _T_1291 : node _T_1292 = eq(_T_1289, UInt<1>(0h0)) when _T_1292 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_1289, UInt<1>(0h1), "") : assert_194 node _T_1293 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1294 = asUInt(reset) node _T_1295 = eq(_T_1294, UInt<1>(0h0)) when _T_1295 : node _T_1296 = eq(_T_1293, UInt<1>(0h0)) when _T_1296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_1293, UInt<1>(0h1), "") : assert_195 else : node _T_1297 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1298 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1299 = or(_T_1297, _T_1298) node _T_1300 = asUInt(reset) node _T_1301 = eq(_T_1300, UInt<1>(0h0)) when _T_1301 : node _T_1302 = eq(_T_1299, UInt<1>(0h0)) when _T_1302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_1299, UInt<1>(0h1), "") : assert_196 node _T_1303 = eq(io.in.d.bits.size, a_size_lookup) node _T_1304 = asUInt(reset) node _T_1305 = eq(_T_1304, UInt<1>(0h0)) when _T_1305 : node _T_1306 = eq(_T_1303, UInt<1>(0h0)) when _T_1306 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_1303, UInt<1>(0h1), "") : assert_197 node _T_1307 = and(io.in.d.valid, d_first_1) node _T_1308 = and(_T_1307, a_first_1) node _T_1309 = and(_T_1308, io.in.a.valid) node _T_1310 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1311 = and(_T_1309, _T_1310) node _T_1312 = eq(d_release_ack, UInt<1>(0h0)) node _T_1313 = and(_T_1311, _T_1312) when _T_1313 : node _T_1314 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1315 = or(_T_1314, io.in.a.ready) node _T_1316 = asUInt(reset) node _T_1317 = eq(_T_1316, UInt<1>(0h0)) when _T_1317 : node _T_1318 = eq(_T_1315, UInt<1>(0h0)) when _T_1318 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_1315, UInt<1>(0h1), "") : assert_198 node _T_1319 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1320 = orr(a_set_wo_ready) node _T_1321 = eq(_T_1320, UInt<1>(0h0)) node _T_1322 = or(_T_1319, _T_1321) node _T_1323 = asUInt(reset) node _T_1324 = eq(_T_1323, UInt<1>(0h0)) when _T_1324 : node _T_1325 = eq(_T_1322, UInt<1>(0h0)) when _T_1325 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_1322, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_130 node _T_1326 = orr(inflight) node _T_1327 = eq(_T_1326, UInt<1>(0h0)) node _T_1328 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1329 = or(_T_1327, _T_1328) node _T_1330 = lt(watchdog, plusarg_reader.out) node _T_1331 = or(_T_1329, _T_1330) node _T_1332 = asUInt(reset) node _T_1333 = eq(_T_1332, UInt<1>(0h0)) when _T_1333 : node _T_1334 = eq(_T_1331, UInt<1>(0h0)) when _T_1334 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_1331, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1335 = and(io.in.a.ready, io.in.a.valid) node _T_1336 = and(io.in.d.ready, io.in.d.valid) node _T_1337 = or(_T_1335, _T_1336) when _T_1337 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<5>, clock, reset, UInt<5>(0h0) regreset inflight_opcodes_1 : UInt<20>, clock, reset, UInt<20>(0h0) regreset inflight_sizes_1 : UInt<20>, clock, reset, UInt<20>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 5, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<5> connect c_set, UInt<5>(0h0) wire c_set_wo_ready : UInt<5> connect c_set_wo_ready, UInt<5>(0h0) wire c_opcodes_set : UInt<20> connect c_opcodes_set, UInt<20>(0h0) wire c_sizes_set : UInt<20> connect c_sizes_set, UInt<20>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) node _T_1338 = and(io.in.c.valid, c_first_1) node _T_1339 = bits(io.in.c.bits.opcode, 2, 2) node _T_1340 = bits(io.in.c.bits.opcode, 1, 1) node _T_1341 = and(_T_1339, _T_1340) node _T_1342 = and(_T_1338, _T_1341) when _T_1342 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_1343 = and(io.in.c.ready, io.in.c.valid) node _T_1344 = and(_T_1343, c_first_1) node _T_1345 = bits(io.in.c.bits.opcode, 2, 2) node _T_1346 = bits(io.in.c.bits.opcode, 1, 1) node _T_1347 = and(_T_1345, _T_1346) node _T_1348 = and(_T_1344, _T_1347) when _T_1348 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_1349 = dshr(inflight_1, io.in.c.bits.source) node _T_1350 = bits(_T_1349, 0, 0) node _T_1351 = eq(_T_1350, UInt<1>(0h0)) node _T_1352 = asUInt(reset) node _T_1353 = eq(_T_1352, UInt<1>(0h0)) when _T_1353 : node _T_1354 = eq(_T_1351, UInt<1>(0h0)) when _T_1354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_1351, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<5> connect d_clr_1, UInt<5>(0h0) wire d_clr_wo_ready_1 : UInt<5> connect d_clr_wo_ready_1, UInt<5>(0h0) wire d_opcodes_clr_1 : UInt<20> connect d_opcodes_clr_1, UInt<20>(0h0) wire d_sizes_clr_1 : UInt<20> connect d_sizes_clr_1, UInt<20>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1355 = and(io.in.d.valid, d_first_2) node _T_1356 = and(_T_1355, UInt<1>(0h1)) node _T_1357 = and(_T_1356, d_release_ack_1) when _T_1357 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1358 = and(io.in.d.ready, io.in.d.valid) node _T_1359 = and(_T_1358, d_first_2) node _T_1360 = and(_T_1359, UInt<1>(0h1)) node _T_1361 = and(_T_1360, d_release_ack_1) when _T_1361 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1362 = and(io.in.d.valid, d_first_2) node _T_1363 = and(_T_1362, UInt<1>(0h1)) node _T_1364 = and(_T_1363, d_release_ack_1) when _T_1364 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1365 = dshr(inflight_1, io.in.d.bits.source) node _T_1366 = bits(_T_1365, 0, 0) node _T_1367 = or(_T_1366, same_cycle_resp_1) node _T_1368 = asUInt(reset) node _T_1369 = eq(_T_1368, UInt<1>(0h0)) when _T_1369 : node _T_1370 = eq(_T_1367, UInt<1>(0h0)) when _T_1370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_1367, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_1371 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_1372 = asUInt(reset) node _T_1373 = eq(_T_1372, UInt<1>(0h0)) when _T_1373 : node _T_1374 = eq(_T_1371, UInt<1>(0h0)) when _T_1374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_1371, UInt<1>(0h1), "") : assert_203 else : node _T_1375 = eq(io.in.d.bits.size, c_size_lookup) node _T_1376 = asUInt(reset) node _T_1377 = eq(_T_1376, UInt<1>(0h0)) when _T_1377 : node _T_1378 = eq(_T_1375, UInt<1>(0h0)) when _T_1378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_1375, UInt<1>(0h1), "") : assert_204 node _T_1379 = and(io.in.d.valid, d_first_2) node _T_1380 = and(_T_1379, c_first_1) node _T_1381 = and(_T_1380, io.in.c.valid) node _T_1382 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_1383 = and(_T_1381, _T_1382) node _T_1384 = and(_T_1383, d_release_ack_1) node _T_1385 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1386 = and(_T_1384, _T_1385) when _T_1386 : node _T_1387 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1388 = or(_T_1387, io.in.c.ready) node _T_1389 = asUInt(reset) node _T_1390 = eq(_T_1389, UInt<1>(0h0)) when _T_1390 : node _T_1391 = eq(_T_1388, UInt<1>(0h0)) when _T_1391 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_1388, UInt<1>(0h1), "") : assert_205 node _T_1392 = orr(c_set_wo_ready) when _T_1392 : node _T_1393 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1394 = asUInt(reset) node _T_1395 = eq(_T_1394, UInt<1>(0h0)) when _T_1395 : node _T_1396 = eq(_T_1393, UInt<1>(0h0)) when _T_1396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_1393, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_131 node _T_1397 = orr(inflight_1) node _T_1398 = eq(_T_1397, UInt<1>(0h0)) node _T_1399 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1400 = or(_T_1398, _T_1399) node _T_1401 = lt(watchdog_1, plusarg_reader_1.out) node _T_1402 = or(_T_1400, _T_1401) node _T_1403 = asUInt(reset) node _T_1404 = eq(_T_1403, UInt<1>(0h0)) when _T_1404 : node _T_1405 = eq(_T_1402, UInt<1>(0h0)) when _T_1405 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_1402, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_1406 = and(io.in.c.ready, io.in.c.valid) node _T_1407 = and(io.in.d.ready, io.in.d.valid) node _T_1408 = or(_T_1406, _T_1407) when _T_1408 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 5, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<8> connect d_set, UInt<8>(0h0) node _T_1409 = and(io.in.d.ready, io.in.d.valid) node _T_1410 = and(_T_1409, d_first_3) node _T_1411 = bits(io.in.d.bits.opcode, 2, 2) node _T_1412 = bits(io.in.d.bits.opcode, 1, 1) node _T_1413 = eq(_T_1412, UInt<1>(0h0)) node _T_1414 = and(_T_1411, _T_1413) node _T_1415 = and(_T_1410, _T_1414) when _T_1415 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_1416 = dshr(inflight_2, io.in.d.bits.sink) node _T_1417 = bits(_T_1416, 0, 0) node _T_1418 = eq(_T_1417, UInt<1>(0h0)) node _T_1419 = asUInt(reset) node _T_1420 = eq(_T_1419, UInt<1>(0h0)) when _T_1420 : node _T_1421 = eq(_T_1418, UInt<1>(0h0)) when _T_1421 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_1418, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<8> connect e_clr, UInt<8>(0h0) node _T_1422 = and(io.in.e.ready, io.in.e.valid) node _T_1423 = and(_T_1422, UInt<1>(0h1)) node _T_1424 = and(_T_1423, UInt<1>(0h1)) when _T_1424 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_1425 = or(d_set, inflight_2) node _T_1426 = dshr(_T_1425, io.in.e.bits.sink) node _T_1427 = bits(_T_1426, 0, 0) node _T_1428 = asUInt(reset) node _T_1429 = eq(_T_1428, UInt<1>(0h0)) when _T_1429 : node _T_1430 = eq(_T_1427, UInt<1>(0h0)) when _T_1430 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_1427, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8 extmodule plusarg_reader_132 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_133 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32
module TLMonitor_52( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire [12:0] _GEN_0 = {10'h0, io_in_c_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [2:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _d_first_T_3 = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala:51:35] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [2:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _c_first_T_1 = io_in_c_ready & io_in_c_valid; // @[Decoupled.scala:51:35] reg [2:0] c_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [2:0] size_3; // @[Monitor.scala:517:22] reg [2:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [4:0] inflight; // @[Monitor.scala:614:27] reg [19:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [19:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire [7:0] _GEN_1 = {5'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_2 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_3 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [7:0] _GEN_4 = {5'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [4:0] inflight_1; // @[Monitor.scala:726:35] reg [19:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] c_first_counter_1; // @[Edges.scala:229:27] wire c_first_1 = c_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_5 = io_in_c_bits_opcode[2] & io_in_c_bits_opcode[1]; // @[Edges.scala:68:{36,40,51}] wire [7:0] _GEN_6 = {5'h0, io_in_c_bits_source}; // @[OneHot.scala:58:35] wire _GEN_7 = _c_first_T_1 & c_first_1 & _GEN_5; // @[Decoupled.scala:51:35] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] reg [7:0] inflight_2; // @[Monitor.scala:828:27] reg [2:0] d_first_counter_3; // @[Edges.scala:229:27] wire d_first_3 = d_first_counter_3 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_8 = _d_first_T_3 & d_first_3 & io_in_d_bits_opcode[2] & ~(io_in_d_bits_opcode[1]); // @[Decoupled.scala:51:35] wire [7:0] _GEN_9 = {5'h0, io_in_d_bits_sink}; // @[OneHot.scala:58:35] wire [7:0] d_set = _GEN_8 ? 8'h1 << _GEN_9 : 8'h0; // @[OneHot.scala:58:35] wire [7:0] _GEN_10 = {5'h0, io_in_e_bits_sink}; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie6_is32_oe8_os24_5 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<8>, sig : UInt<33>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node _sAdjustedExp_T = add(io.in.sExp, asSInt(UInt<9>(0hc0))) node _sAdjustedExp_T_1 = bits(_sAdjustedExp_T, 8, 0) node sAdjustedExp = cvt(_sAdjustedExp_T_1) node _adjustedSig_T = bits(io.in.sig, 32, 7) node _adjustedSig_T_1 = bits(io.in.sig, 6, 0) node _adjustedSig_T_2 = orr(_adjustedSig_T_1) node adjustedSig = cat(_adjustedSig_T, _adjustedSig_T_2) wire common_expOut : UInt<9> wire common_fractOut : UInt<23> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _roundMask_T = cat(UInt<24>(0h0), UInt<1>(0h0)) node roundMask = cat(_roundMask_T, UInt<2>(0h3)) node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) node _roundPosMask_T = not(shiftedRoundMask) node roundPosMask = and(_roundPosMask_T, roundMask) node _roundPosBit_T = and(adjustedSig, roundPosMask) node roundPosBit = orr(_roundPosBit_T) node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) node anyRoundExtra = orr(_anyRoundExtra_T) node anyRound = or(roundPosBit, anyRoundExtra) node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) node _roundIncr_T_2 = and(roundMagUp, anyRound) node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) node _roundedSig_T = or(adjustedSig, roundMask) node _roundedSig_T_1 = shr(_roundedSig_T, 2) node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) node _roundedSig_T_6 = shr(roundMask, 1) node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0)) node _roundedSig_T_8 = not(_roundedSig_T_7) node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) node _roundedSig_T_10 = not(roundMask) node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) node _roundedSig_T_13 = and(roundingMode_odd, anyRound) node _roundedSig_T_14 = shr(roundPosMask, 1) node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) node _sRoundedExp_T = shr(roundedSig, 24) node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) node sRoundedExp = add(sAdjustedExp, _sRoundedExp_T_1) node _common_expOut_T = bits(sRoundedExp, 8, 0) connect common_expOut, _common_expOut_T node _common_fractOut_T = bits(roundedSig, 23, 1) node _common_fractOut_T_1 = bits(roundedSig, 22, 0) node _common_fractOut_T_2 = mux(UInt<1>(0h0), _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 connect common_overflow, UInt<1>(0h0) connect common_totalUnderflow, UInt<1>(0h0) node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) node unboundedRange_roundPosBit = mux(UInt<1>(0h0), _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) node _unboundedRange_anyRound_T_1 = and(UInt<1>(0h0), _unboundedRange_anyRound_T) node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) node _roundCarry_T = bits(roundedSig, 25, 25) node _roundCarry_T_1 = bits(roundedSig, 24, 24) node roundCarry = mux(UInt<1>(0h0), _roundCarry_T, _roundCarry_T_1) connect common_underflow, UInt<1>(0h0) node _common_inexact_T = or(common_totalUnderflow, anyRound) connect common_inexact, _common_inexact_T node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<9>(0h6b)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3
module RoundAnyRawFNToRecFN_ie6_is32_oe8_os24_5( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [7:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [32:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [7:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [32:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [24:0] _roundMask_T = 25'h0; // @[RoundAnyRawFNToRecFN.scala:153:36] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [26:0] roundMask = 27'h3; // @[RoundAnyRawFNToRecFN.scala:153:55] wire [27:0] _shiftedRoundMask_T = 28'h3; // @[RoundAnyRawFNToRecFN.scala:162:41] wire [26:0] shiftedRoundMask = 27'h1; // @[RoundAnyRawFNToRecFN.scala:162:53] wire [26:0] _roundPosMask_T = 27'h7FFFFFE; // @[RoundAnyRawFNToRecFN.scala:163:28] wire [26:0] roundPosMask = 27'h2; // @[RoundAnyRawFNToRecFN.scala:163:46] wire [26:0] _roundedSig_T_10 = 27'h7FFFFFC; // @[RoundAnyRawFNToRecFN.scala:180:32] wire [25:0] _roundedSig_T_6 = 26'h1; // @[RoundAnyRawFNToRecFN.scala:177:35, :181:67] wire [25:0] _roundedSig_T_14 = 26'h1; // @[RoundAnyRawFNToRecFN.scala:177:35, :181:67] wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14] wire [8:0] _expOut_T_12 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18] wire [8:0] _expOut_T_11 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:265:18] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16] wire [8:0] _expOut_T_18 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:277:16] wire [8:0] _expOut_T_20 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:278:16] wire [22:0] _fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:281:16, :284:13] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:281:16, :284:13] wire [1:0] _io_exceptionFlags_T = 2'h0; // @[RoundAnyRawFNToRecFN.scala:288:23] wire [3:0] _io_exceptionFlags_T_2 = 4'h0; // @[RoundAnyRawFNToRecFN.scala:288:53] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53] wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38] wire _commonCase_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:237:22] wire _commonCase_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:237:36] wire _commonCase_T_2 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:237:33] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41] wire [2:0] _io_exceptionFlags_T_1 = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41] wire io_invalidExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire common_overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:124:37] wire common_totalUnderflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:125:37] wire common_underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29] wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42] wire _unboundedRange_anyRound_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:205:30] wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29] wire isNaNOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:235:34] wire notNaN_isSpecialInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:236:49] wire overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:238:32] wire underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:239:32] wire _pegMinNonzeroMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:20] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire _notNaN_isInfOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:45] wire notNaN_isInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:32] wire _expOut_T = io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :253:32] wire _fractOut_T = io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :280:22] wire signOut = io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :250:22] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire [9:0] _sAdjustedExp_T = {{2{io_in_sExp_0[7]}}, io_in_sExp_0} + 10'hC0; // @[RoundAnyRawFNToRecFN.scala:48:5, :104:25] wire [8:0] _sAdjustedExp_T_1 = _sAdjustedExp_T[8:0]; // @[RoundAnyRawFNToRecFN.scala:104:25, :106:14] wire [9:0] sAdjustedExp = {1'h0, _sAdjustedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:106:{14,31}] wire [25:0] _adjustedSig_T = io_in_sig_0[32:7]; // @[RoundAnyRawFNToRecFN.scala:48:5, :116:23] wire [6:0] _adjustedSig_T_1 = io_in_sig_0[6:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :117:26] wire _adjustedSig_T_2 = |_adjustedSig_T_1; // @[RoundAnyRawFNToRecFN.scala:117:{26,60}] wire [26:0] adjustedSig = {_adjustedSig_T, _adjustedSig_T_2}; // @[RoundAnyRawFNToRecFN.scala:116:{23,66}, :117:60] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [26:0] _roundPosBit_T = adjustedSig & 27'h2; // @[RoundAnyRawFNToRecFN.scala:116:66, :163:46, :164:40] wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67] wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49] wire [26:0] _anyRoundExtra_T = adjustedSig & 27'h1; // @[RoundAnyRawFNToRecFN.scala:116:66, :162:53, :165:42] wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] assign _common_inexact_T = anyRound; // @[RoundAnyRawFNToRecFN.scala:166:36, :230:49] wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31] wire [26:0] _roundedSig_T = adjustedSig | 27'h3; // @[RoundAnyRawFNToRecFN.scala:116:66, :153:55, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}, :177:35, :181:67] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_7 = {25'h0, _roundedSig_T_5}; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_11 = adjustedSig & 27'h7FFFFFC; // @[RoundAnyRawFNToRecFN.scala:116:66, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [10:0] sRoundedExp = {sAdjustedExp[9], sAdjustedExp} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:106:31, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:189:16, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:61] wire unboundedRange_roundPosBit = _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:203:{16,61}] wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:116:66, :205:63] wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{49,70}] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:211:16, :213:27] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{61,64}] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = _inexact_T; // @[RoundAnyRawFNToRecFN.scala:240:{28,43}] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17] wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17] wire [8:0] _expOut_T_13 = _expOut_T_10; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17] wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18] wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15] wire [8:0] _expOut_T_19 = _expOut_T_17; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15] wire [8:0] expOut = _expOut_T_19; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73] wire _fractOut_T_1 = _fractOut_T; // @[RoundAnyRawFNToRecFN.scala:280:{22,38}] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? 23'h0 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16, :284:13] wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] assign _io_exceptionFlags_T_3 = {4'h0, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IBuf : input clock : Clock input reset : Reset output io : { flip imem : { flip ready : UInt<1>, valid : UInt<1>, bits : { btb : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, pc : UInt<40>, data : UInt<32>, mask : UInt<2>, xcpt : { pf : { inst : UInt<1>}, gf : { inst : UInt<1>}, ae : { inst : UInt<1>}}, replay : UInt<1>}}, flip kill : UInt<1>, pc : UInt<40>, btb_resp : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, inst : { flip ready : UInt<1>, valid : UInt<1>, bits : { xcpt0 : { pf : { inst : UInt<1>}, gf : { inst : UInt<1>}, ae : { inst : UInt<1>}}, xcpt1 : { pf : { inst : UInt<1>}, gf : { inst : UInt<1>}, ae : { inst : UInt<1>}}, replay : UInt<1>, rvc : UInt<1>, inst : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}, raw : UInt<32>}}[1]} regreset nBufValid : UInt<1>, clock, reset, UInt<1>(0h0) reg buf : { btb : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, pc : UInt<40>, data : UInt<32>, mask : UInt<2>, xcpt : { pf : { inst : UInt<1>}, gf : { inst : UInt<1>}, ae : { inst : UInt<1>}}, replay : UInt<1>}, clock reg ibufBTBResp : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, clock node pcWordBits = bits(io.imem.bits.pc, 1, 1) wire nReady : UInt<2> connect nReady, UInt<2>(0h0) node _nIC_T = add(io.imem.bits.btb.bridx, UInt<1>(0h1)) node _nIC_T_1 = mux(io.imem.bits.btb.taken, _nIC_T, UInt<2>(0h2)) node _nIC_T_2 = sub(_nIC_T_1, pcWordBits) node nIC = tail(_nIC_T_2, 1) node _nICReady_T = sub(nReady, nBufValid) node nICReady = tail(_nICReady_T, 1) node _nValid_T = mux(io.imem.valid, nIC, UInt<1>(0h0)) node _nValid_T_1 = add(_nValid_T, nBufValid) node nValid = tail(_nValid_T_1, 1) node _io_imem_ready_T = geq(nReady, nBufValid) node _io_imem_ready_T_1 = and(io.inst[0].ready, _io_imem_ready_T) node _io_imem_ready_T_2 = geq(nICReady, nIC) node _io_imem_ready_T_3 = sub(nIC, nICReady) node _io_imem_ready_T_4 = tail(_io_imem_ready_T_3, 1) node _io_imem_ready_T_5 = geq(UInt<1>(0h1), _io_imem_ready_T_4) node _io_imem_ready_T_6 = or(_io_imem_ready_T_2, _io_imem_ready_T_5) node _io_imem_ready_T_7 = and(_io_imem_ready_T_1, _io_imem_ready_T_6) connect io.imem.ready, _io_imem_ready_T_7 when io.inst[0].ready : node _nBufValid_T = geq(nReady, nBufValid) node _nBufValid_T_1 = eq(nBufValid, UInt<1>(0h0)) node _nBufValid_T_2 = or(_nBufValid_T, _nBufValid_T_1) node _nBufValid_T_3 = sub(nBufValid, nReady) node _nBufValid_T_4 = tail(_nBufValid_T_3, 1) node _nBufValid_T_5 = mux(_nBufValid_T_2, UInt<1>(0h0), _nBufValid_T_4) connect nBufValid, _nBufValid_T_5 node _T = geq(nReady, nBufValid) node _T_1 = and(io.imem.valid, _T) node _T_2 = lt(nICReady, nIC) node _T_3 = and(_T_1, _T_2) node _T_4 = sub(nIC, nICReady) node _T_5 = tail(_T_4, 1) node _T_6 = geq(UInt<1>(0h1), _T_5) node _T_7 = and(_T_3, _T_6) when _T_7 : node _shamt_T = add(pcWordBits, nICReady) node shamt = tail(_shamt_T, 1) node _nBufValid_T_6 = sub(nIC, nICReady) node _nBufValid_T_7 = tail(_nBufValid_T_6, 1) connect nBufValid, _nBufValid_T_7 connect buf, io.imem.bits node _buf_data_data_T = shr(io.imem.bits.data, 16) node _buf_data_data_T_1 = cat(_buf_data_data_T, _buf_data_data_T) node buf_data_data = cat(_buf_data_data_T_1, io.imem.bits.data) node _buf_data_T = shl(shamt, 4) node _buf_data_T_1 = dshr(buf_data_data, _buf_data_T) node _buf_data_T_2 = bits(_buf_data_T_1, 15, 0) connect buf.data, _buf_data_T_2 node _buf_pc_T = not(UInt<40>(0h3)) node _buf_pc_T_1 = and(io.imem.bits.pc, _buf_pc_T) node _buf_pc_T_2 = shl(nICReady, 1) node _buf_pc_T_3 = add(io.imem.bits.pc, _buf_pc_T_2) node _buf_pc_T_4 = tail(_buf_pc_T_3, 1) node _buf_pc_T_5 = and(_buf_pc_T_4, UInt<40>(0h3)) node _buf_pc_T_6 = or(_buf_pc_T_1, _buf_pc_T_5) connect buf.pc, _buf_pc_T_6 connect ibufBTBResp, io.imem.bits.btb when io.kill : connect nBufValid, UInt<1>(0h0) node _icShiftAmt_T = add(UInt<2>(0h2), nBufValid) node _icShiftAmt_T_1 = tail(_icShiftAmt_T, 1) node _icShiftAmt_T_2 = sub(_icShiftAmt_T_1, pcWordBits) node _icShiftAmt_T_3 = tail(_icShiftAmt_T_2, 1) node icShiftAmt = bits(_icShiftAmt_T_3, 1, 0) node _icData_T = bits(io.imem.bits.data, 15, 0) node _icData_T_1 = cat(_icData_T, _icData_T) node _icData_T_2 = cat(io.imem.bits.data, _icData_T_1) node _icData_data_T = shr(_icData_T_2, 48) node _icData_data_T_1 = cat(_icData_data_T, _icData_data_T) node _icData_data_T_2 = cat(_icData_data_T_1, _icData_data_T_1) node icData_data = cat(_icData_data_T_2, _icData_T_2) node _icData_T_3 = shl(icShiftAmt, 4) node _icData_T_4 = dshl(icData_data, _icData_T_3) node icData = bits(_icData_T_4, 95, 64) node _icMask_T = not(UInt<32>(0h0)) node _icMask_T_1 = shl(nBufValid, 4) node _icMask_T_2 = dshl(_icMask_T, _icMask_T_1) node icMask = bits(_icMask_T_2, 31, 0) node _inst_T = and(icData, icMask) node _inst_T_1 = not(icMask) node _inst_T_2 = and(buf.data, _inst_T_1) node inst = or(_inst_T, _inst_T_2) node _valid_T = dshl(UInt<1>(0h1), nValid) node _valid_T_1 = sub(_valid_T, UInt<1>(0h1)) node _valid_T_2 = tail(_valid_T_1, 1) node valid = bits(_valid_T_2, 1, 0) node _bufMask_T = dshl(UInt<1>(0h1), nBufValid) node _bufMask_T_1 = sub(_bufMask_T, UInt<1>(0h1)) node bufMask = tail(_bufMask_T_1, 1) node _xcpt_T = bits(bufMask, 0, 0) node xcpt_0 = mux(_xcpt_T, buf.xcpt, io.imem.bits.xcpt) node _xcpt_T_1 = bits(bufMask, 1, 1) node xcpt_1 = mux(_xcpt_T_1, buf.xcpt, io.imem.bits.xcpt) node buf_replay = mux(buf.replay, bufMask, UInt<1>(0h0)) node _ic_replay_T = not(bufMask) node _ic_replay_T_1 = and(valid, _ic_replay_T) node _ic_replay_T_2 = mux(io.imem.bits.replay, _ic_replay_T_1, UInt<1>(0h0)) node ic_replay = or(buf_replay, _ic_replay_T_2) node _T_8 = eq(io.imem.valid, UInt<1>(0h0)) node _T_9 = eq(io.imem.bits.btb.taken, UInt<1>(0h0)) node _T_10 = or(_T_8, _T_9) node _T_11 = geq(io.imem.bits.btb.bridx, pcWordBits) node _T_12 = or(_T_10, _T_11) node _T_13 = asUInt(reset) node _T_14 = eq(_T_13, UInt<1>(0h0)) when _T_14 : node _T_15 = eq(_T_12, UInt<1>(0h0)) when _T_15 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IBuf.scala:79 assert(!io.imem.valid || !io.imem.bits.btb.taken || io.imem.bits.btb.bridx >= pcWordBits)\n") : printf assert(clock, _T_12, UInt<1>(0h1), "") : assert connect io.btb_resp, io.imem.bits.btb node _io_pc_T = gt(nBufValid, UInt<1>(0h0)) node _io_pc_T_1 = mux(_io_pc_T, buf.pc, io.imem.bits.pc) connect io.pc, _io_pc_T_1 inst exp of RVCExpander connect exp.clock, clock connect exp.reset, reset connect exp.io.in, inst connect io.inst[0].bits.inst, exp.io.out connect io.inst[0].bits.raw, inst node _replay_T = dshr(ic_replay, UInt<1>(0h0)) node _replay_T_1 = bits(_replay_T, 0, 0) node _replay_T_2 = eq(exp.io.rvc, UInt<1>(0h0)) node _replay_T_3 = add(UInt<1>(0h0), UInt<1>(0h1)) node _replay_T_4 = tail(_replay_T_3, 1) node _replay_T_5 = dshr(ic_replay, _replay_T_4) node _replay_T_6 = bits(_replay_T_5, 0, 0) node _replay_T_7 = and(_replay_T_2, _replay_T_6) node replay = or(_replay_T_1, _replay_T_7) node _full_insn_T = add(UInt<1>(0h0), UInt<1>(0h1)) node _full_insn_T_1 = tail(_full_insn_T, 1) node _full_insn_T_2 = dshr(valid, _full_insn_T_1) node _full_insn_T_3 = bits(_full_insn_T_2, 0, 0) node _full_insn_T_4 = or(exp.io.rvc, _full_insn_T_3) node _full_insn_T_5 = dshr(buf_replay, UInt<1>(0h0)) node _full_insn_T_6 = bits(_full_insn_T_5, 0, 0) node full_insn = or(_full_insn_T_4, _full_insn_T_6) node _io_inst_0_valid_T = dshr(valid, UInt<1>(0h0)) node _io_inst_0_valid_T_1 = bits(_io_inst_0_valid_T, 0, 0) node _io_inst_0_valid_T_2 = and(_io_inst_0_valid_T_1, full_insn) connect io.inst[0].valid, _io_inst_0_valid_T_2 node _io_inst_0_bits_xcpt0_T = eq(UInt<1>(0h0), UInt<1>(0h1)) node _io_inst_0_bits_xcpt0_T_1 = mux(_io_inst_0_bits_xcpt0_T, xcpt_1, xcpt_0) connect io.inst[0].bits.xcpt0, _io_inst_0_bits_xcpt0_T_1 node _io_inst_0_bits_xcpt1_T = add(UInt<1>(0h0), UInt<1>(0h1)) node _io_inst_0_bits_xcpt1_T_1 = tail(_io_inst_0_bits_xcpt1_T, 1) node _io_inst_0_bits_xcpt1_T_2 = eq(_io_inst_0_bits_xcpt1_T_1, UInt<1>(0h1)) node _io_inst_0_bits_xcpt1_T_3 = mux(_io_inst_0_bits_xcpt1_T_2, xcpt_1, xcpt_0) node io_inst_0_bits_xcpt1_hi = cat(_io_inst_0_bits_xcpt1_T_3.pf.inst, _io_inst_0_bits_xcpt1_T_3.gf.inst) node _io_inst_0_bits_xcpt1_T_4 = cat(io_inst_0_bits_xcpt1_hi, _io_inst_0_bits_xcpt1_T_3.ae.inst) node _io_inst_0_bits_xcpt1_T_5 = mux(exp.io.rvc, UInt<1>(0h0), _io_inst_0_bits_xcpt1_T_4) wire _io_inst_0_bits_xcpt1_WIRE : { pf : { inst : UInt<1>}, gf : { inst : UInt<1>}, ae : { inst : UInt<1>}} wire _io_inst_0_bits_xcpt1_WIRE_1 : UInt<3> connect _io_inst_0_bits_xcpt1_WIRE_1, _io_inst_0_bits_xcpt1_T_5 node _io_inst_0_bits_xcpt1_T_6 = bits(_io_inst_0_bits_xcpt1_WIRE_1, 0, 0) connect _io_inst_0_bits_xcpt1_WIRE.ae.inst, _io_inst_0_bits_xcpt1_T_6 node _io_inst_0_bits_xcpt1_T_7 = bits(_io_inst_0_bits_xcpt1_WIRE_1, 1, 1) connect _io_inst_0_bits_xcpt1_WIRE.gf.inst, _io_inst_0_bits_xcpt1_T_7 node _io_inst_0_bits_xcpt1_T_8 = bits(_io_inst_0_bits_xcpt1_WIRE_1, 2, 2) connect _io_inst_0_bits_xcpt1_WIRE.pf.inst, _io_inst_0_bits_xcpt1_T_8 connect io.inst[0].bits.xcpt1, _io_inst_0_bits_xcpt1_WIRE connect io.inst[0].bits.replay, replay connect io.inst[0].bits.rvc, exp.io.rvc node _T_16 = dshr(bufMask, UInt<1>(0h0)) node _T_17 = bits(_T_16, 0, 0) node _T_18 = and(_T_17, exp.io.rvc) node _T_19 = add(UInt<1>(0h0), UInt<1>(0h1)) node _T_20 = tail(_T_19, 1) node _T_21 = dshr(bufMask, _T_20) node _T_22 = bits(_T_21, 0, 0) node _T_23 = or(_T_18, _T_22) when _T_23 : connect io.btb_resp, ibufBTBResp node _T_24 = or(UInt<1>(0h1), io.inst[0].ready) node _T_25 = and(full_insn, _T_24) when _T_25 : node _nReady_T = add(UInt<1>(0h0), UInt<1>(0h1)) node _nReady_T_1 = tail(_nReady_T, 1) node _nReady_T_2 = add(UInt<1>(0h0), UInt<2>(0h2)) node _nReady_T_3 = tail(_nReady_T_2, 1) node _nReady_T_4 = mux(exp.io.rvc, _nReady_T_1, _nReady_T_3) connect nReady, _nReady_T_4 node _T_26 = add(UInt<1>(0h0), UInt<1>(0h1)) node _T_27 = tail(_T_26, 1) node _T_28 = add(UInt<1>(0h0), UInt<2>(0h2)) node _T_29 = tail(_T_28, 1) node _T_30 = mux(exp.io.rvc, _T_27, _T_29) node _T_31 = shr(inst, 16) node _T_32 = shr(inst, 32) node _T_33 = mux(exp.io.rvc, _T_31, _T_32)
module IBuf( // @[IBuf.scala:21:7] input clock, // @[IBuf.scala:21:7] input reset, // @[IBuf.scala:21:7] output io_imem_ready, // @[IBuf.scala:22:14] input io_imem_valid, // @[IBuf.scala:22:14] input [1:0] io_imem_bits_btb_cfiType, // @[IBuf.scala:22:14] input io_imem_bits_btb_taken, // @[IBuf.scala:22:14] input [1:0] io_imem_bits_btb_mask, // @[IBuf.scala:22:14] input io_imem_bits_btb_bridx, // @[IBuf.scala:22:14] input [38:0] io_imem_bits_btb_target, // @[IBuf.scala:22:14] input [4:0] io_imem_bits_btb_entry, // @[IBuf.scala:22:14] input [7:0] io_imem_bits_btb_bht_history, // @[IBuf.scala:22:14] input io_imem_bits_btb_bht_value, // @[IBuf.scala:22:14] input [39:0] io_imem_bits_pc, // @[IBuf.scala:22:14] input [31:0] io_imem_bits_data, // @[IBuf.scala:22:14] input [1:0] io_imem_bits_mask, // @[IBuf.scala:22:14] input io_imem_bits_xcpt_pf_inst, // @[IBuf.scala:22:14] input io_imem_bits_xcpt_gf_inst, // @[IBuf.scala:22:14] input io_imem_bits_xcpt_ae_inst, // @[IBuf.scala:22:14] input io_imem_bits_replay, // @[IBuf.scala:22:14] input io_kill, // @[IBuf.scala:22:14] output [39:0] io_pc, // @[IBuf.scala:22:14] output [1:0] io_btb_resp_cfiType, // @[IBuf.scala:22:14] output io_btb_resp_taken, // @[IBuf.scala:22:14] output [1:0] io_btb_resp_mask, // @[IBuf.scala:22:14] output io_btb_resp_bridx, // @[IBuf.scala:22:14] output [38:0] io_btb_resp_target, // @[IBuf.scala:22:14] output [4:0] io_btb_resp_entry, // @[IBuf.scala:22:14] output [7:0] io_btb_resp_bht_history, // @[IBuf.scala:22:14] output io_btb_resp_bht_value, // @[IBuf.scala:22:14] input io_inst_0_ready, // @[IBuf.scala:22:14] output io_inst_0_valid, // @[IBuf.scala:22:14] output io_inst_0_bits_xcpt0_pf_inst, // @[IBuf.scala:22:14] output io_inst_0_bits_xcpt0_gf_inst, // @[IBuf.scala:22:14] output io_inst_0_bits_xcpt0_ae_inst, // @[IBuf.scala:22:14] output io_inst_0_bits_xcpt1_pf_inst, // @[IBuf.scala:22:14] output io_inst_0_bits_xcpt1_gf_inst, // @[IBuf.scala:22:14] output io_inst_0_bits_xcpt1_ae_inst, // @[IBuf.scala:22:14] output io_inst_0_bits_replay, // @[IBuf.scala:22:14] output io_inst_0_bits_rvc, // @[IBuf.scala:22:14] output [31:0] io_inst_0_bits_inst_bits, // @[IBuf.scala:22:14] output [4:0] io_inst_0_bits_inst_rd, // @[IBuf.scala:22:14] output [4:0] io_inst_0_bits_inst_rs1, // @[IBuf.scala:22:14] output [4:0] io_inst_0_bits_inst_rs2, // @[IBuf.scala:22:14] output [4:0] io_inst_0_bits_inst_rs3, // @[IBuf.scala:22:14] output [31:0] io_inst_0_bits_raw // @[IBuf.scala:22:14] ); wire _exp_io_rvc; // @[IBuf.scala:86:21] wire io_imem_valid_0 = io_imem_valid; // @[IBuf.scala:21:7] wire [1:0] io_imem_bits_btb_cfiType_0 = io_imem_bits_btb_cfiType; // @[IBuf.scala:21:7] wire io_imem_bits_btb_taken_0 = io_imem_bits_btb_taken; // @[IBuf.scala:21:7] wire [1:0] io_imem_bits_btb_mask_0 = io_imem_bits_btb_mask; // @[IBuf.scala:21:7] wire io_imem_bits_btb_bridx_0 = io_imem_bits_btb_bridx; // @[IBuf.scala:21:7] wire [38:0] io_imem_bits_btb_target_0 = io_imem_bits_btb_target; // @[IBuf.scala:21:7] wire [4:0] io_imem_bits_btb_entry_0 = io_imem_bits_btb_entry; // @[IBuf.scala:21:7] wire [7:0] io_imem_bits_btb_bht_history_0 = io_imem_bits_btb_bht_history; // @[IBuf.scala:21:7] wire io_imem_bits_btb_bht_value_0 = io_imem_bits_btb_bht_value; // @[IBuf.scala:21:7] wire [39:0] io_imem_bits_pc_0 = io_imem_bits_pc; // @[IBuf.scala:21:7] wire [31:0] io_imem_bits_data_0 = io_imem_bits_data; // @[IBuf.scala:21:7] wire [1:0] io_imem_bits_mask_0 = io_imem_bits_mask; // @[IBuf.scala:21:7] wire io_imem_bits_xcpt_pf_inst_0 = io_imem_bits_xcpt_pf_inst; // @[IBuf.scala:21:7] wire io_imem_bits_xcpt_gf_inst_0 = io_imem_bits_xcpt_gf_inst; // @[IBuf.scala:21:7] wire io_imem_bits_xcpt_ae_inst_0 = io_imem_bits_xcpt_ae_inst; // @[IBuf.scala:21:7] wire io_imem_bits_replay_0 = io_imem_bits_replay; // @[IBuf.scala:21:7] wire io_kill_0 = io_kill; // @[IBuf.scala:21:7] wire io_inst_0_ready_0 = io_inst_0_ready; // @[IBuf.scala:21:7] wire [1:0] _replay_T_3 = 2'h1; // @[IBuf.scala:92:63] wire [1:0] _full_insn_T = 2'h1; // @[IBuf.scala:93:44] wire [1:0] _io_inst_0_bits_xcpt1_T = 2'h1; // @[IBuf.scala:96:59] wire [1:0] _nReady_T = 2'h1; // @[IBuf.scala:102:89] wire [1:0] _nReady_T_3 = 2'h2; // @[IBuf.scala:102:96] wire _replay_T_4 = 1'h1; // @[IBuf.scala:92:63] wire _full_insn_T_1 = 1'h1; // @[IBuf.scala:93:44] wire _io_inst_0_bits_xcpt1_T_1 = 1'h1; // @[IBuf.scala:96:59] wire _io_inst_0_bits_xcpt1_T_2 = 1'h1; // @[package.scala:39:86] wire _nReady_T_1 = 1'h1; // @[IBuf.scala:102:89] wire _io_inst_0_bits_xcpt0_T = 1'h0; // @[package.scala:39:86] wire [31:0] _icMask_T = 32'hFFFFFFFF; // @[IBuf.scala:71:17] wire [39:0] _buf_pc_T = 40'hFFFFFFFFFC; // @[IBuf.scala:59:37] wire [2:0] _nReady_T_2 = 3'h2; // @[IBuf.scala:102:96] wire _io_imem_ready_T_7; // @[IBuf.scala:44:60] wire [39:0] _io_pc_T_1; // @[IBuf.scala:82:15] wire _io_inst_0_valid_T_2; // @[IBuf.scala:94:36] wire _io_inst_0_bits_xcpt0_T_1_pf_inst; // @[package.scala:39:76] wire _io_inst_0_bits_xcpt0_T_1_gf_inst; // @[package.scala:39:76] wire _io_inst_0_bits_xcpt0_T_1_ae_inst; // @[package.scala:39:76] wire _io_inst_0_bits_xcpt1_WIRE_pf_inst; // @[IBuf.scala:96:81] wire _io_inst_0_bits_xcpt1_WIRE_gf_inst; // @[IBuf.scala:96:81] wire _io_inst_0_bits_xcpt1_WIRE_ae_inst; // @[IBuf.scala:96:81] wire replay; // @[IBuf.scala:92:33] wire [31:0] inst; // @[IBuf.scala:72:30] wire io_imem_ready_0; // @[IBuf.scala:21:7] wire [7:0] io_btb_resp_bht_history_0; // @[IBuf.scala:21:7] wire io_btb_resp_bht_value_0; // @[IBuf.scala:21:7] wire [1:0] io_btb_resp_cfiType_0; // @[IBuf.scala:21:7] wire io_btb_resp_taken_0; // @[IBuf.scala:21:7] wire [1:0] io_btb_resp_mask_0; // @[IBuf.scala:21:7] wire io_btb_resp_bridx_0; // @[IBuf.scala:21:7] wire [38:0] io_btb_resp_target_0; // @[IBuf.scala:21:7] wire [4:0] io_btb_resp_entry_0; // @[IBuf.scala:21:7] wire io_inst_0_bits_xcpt0_pf_inst_0; // @[IBuf.scala:21:7] wire io_inst_0_bits_xcpt0_gf_inst_0; // @[IBuf.scala:21:7] wire io_inst_0_bits_xcpt0_ae_inst_0; // @[IBuf.scala:21:7] wire io_inst_0_bits_xcpt1_pf_inst_0; // @[IBuf.scala:21:7] wire io_inst_0_bits_xcpt1_gf_inst_0; // @[IBuf.scala:21:7] wire io_inst_0_bits_xcpt1_ae_inst_0; // @[IBuf.scala:21:7] wire [31:0] io_inst_0_bits_inst_bits_0; // @[IBuf.scala:21:7] wire [4:0] io_inst_0_bits_inst_rd_0; // @[IBuf.scala:21:7] wire [4:0] io_inst_0_bits_inst_rs1_0; // @[IBuf.scala:21:7] wire [4:0] io_inst_0_bits_inst_rs2_0; // @[IBuf.scala:21:7] wire [4:0] io_inst_0_bits_inst_rs3_0; // @[IBuf.scala:21:7] wire io_inst_0_bits_replay_0; // @[IBuf.scala:21:7] wire io_inst_0_bits_rvc_0; // @[IBuf.scala:21:7] wire [31:0] io_inst_0_bits_raw_0; // @[IBuf.scala:21:7] wire io_inst_0_valid_0; // @[IBuf.scala:21:7] wire [39:0] io_pc_0; // @[IBuf.scala:21:7] reg nBufValid; // @[IBuf.scala:34:47] wire _io_pc_T = nBufValid; // @[IBuf.scala:34:47, :82:26] reg [1:0] buf_btb_cfiType; // @[IBuf.scala:35:16] reg buf_btb_taken; // @[IBuf.scala:35:16] reg [1:0] buf_btb_mask; // @[IBuf.scala:35:16] reg buf_btb_bridx; // @[IBuf.scala:35:16] reg [38:0] buf_btb_target; // @[IBuf.scala:35:16] reg [4:0] buf_btb_entry; // @[IBuf.scala:35:16] reg [7:0] buf_btb_bht_history; // @[IBuf.scala:35:16] reg buf_btb_bht_value; // @[IBuf.scala:35:16] reg [39:0] buf_pc; // @[IBuf.scala:35:16] reg [31:0] buf_data; // @[IBuf.scala:35:16] reg [1:0] buf_mask; // @[IBuf.scala:35:16] reg buf_xcpt_pf_inst; // @[IBuf.scala:35:16] reg buf_xcpt_gf_inst; // @[IBuf.scala:35:16] reg buf_xcpt_ae_inst; // @[IBuf.scala:35:16] reg buf_replay; // @[IBuf.scala:35:16] reg [1:0] ibufBTBResp_cfiType; // @[IBuf.scala:36:24] reg ibufBTBResp_taken; // @[IBuf.scala:36:24] reg [1:0] ibufBTBResp_mask; // @[IBuf.scala:36:24] reg ibufBTBResp_bridx; // @[IBuf.scala:36:24] reg [38:0] ibufBTBResp_target; // @[IBuf.scala:36:24] reg [4:0] ibufBTBResp_entry; // @[IBuf.scala:36:24] reg [7:0] ibufBTBResp_bht_history; // @[IBuf.scala:36:24] reg ibufBTBResp_bht_value; // @[IBuf.scala:36:24] wire pcWordBits = io_imem_bits_pc_0[1]; // @[package.scala:163:13] wire [1:0] nReady; // @[IBuf.scala:40:27] wire [1:0] _nIC_T = {1'h0, io_imem_bits_btb_bridx_0} + 2'h1; // @[IBuf.scala:21:7, :41:64] wire [1:0] _nIC_T_1 = io_imem_bits_btb_taken_0 ? _nIC_T : 2'h2; // @[IBuf.scala:21:7, :41:{16,64}] wire [2:0] _GEN = {2'h0, pcWordBits}; // @[package.scala:163:13] wire [2:0] _nIC_T_2 = {1'h0, _nIC_T_1} - _GEN; // @[IBuf.scala:41:{16,86}] wire [1:0] nIC = _nIC_T_2[1:0]; // @[IBuf.scala:41:86] wire [2:0] _GEN_0 = {1'h0, nReady}; // @[IBuf.scala:40:27, :42:25] wire [2:0] _GEN_1 = {2'h0, nBufValid}; // @[IBuf.scala:34:47, :42:25] wire [2:0] _nICReady_T = _GEN_0 - _GEN_1; // @[IBuf.scala:42:25] wire [1:0] nICReady = _nICReady_T[1:0]; // @[IBuf.scala:42:25] wire [1:0] _nValid_T = io_imem_valid_0 ? nIC : 2'h0; // @[IBuf.scala:21:7, :41:86, :43:19] wire [2:0] _nValid_T_1 = {1'h0, _nValid_T} + _GEN_1; // @[IBuf.scala:42:25, :43:{19,45}] wire [1:0] nValid = _nValid_T_1[1:0]; // @[IBuf.scala:43:45] wire [1:0] _GEN_2 = {1'h0, nBufValid}; // @[IBuf.scala:34:47, :44:47] wire _T = nReady >= _GEN_2; // @[IBuf.scala:40:27, :44:47] wire _io_imem_ready_T; // @[IBuf.scala:44:47] assign _io_imem_ready_T = _T; // @[IBuf.scala:44:47] wire _nBufValid_T; // @[package.scala:218:33] assign _nBufValid_T = _T; // @[package.scala:218:33] wire _io_imem_ready_T_1 = io_inst_0_ready_0 & _io_imem_ready_T; // @[IBuf.scala:21:7, :44:{37,47}] wire _io_imem_ready_T_2 = nICReady >= nIC; // @[IBuf.scala:41:86, :42:25, :44:73] wire [2:0] _GEN_3 = {1'h0, nICReady}; // @[IBuf.scala:42:25, :44:94] wire [2:0] _T_4 = {1'h0, nIC} - _GEN_3; // @[IBuf.scala:41:86, :44:94] wire [2:0] _io_imem_ready_T_3; // @[IBuf.scala:44:94] assign _io_imem_ready_T_3 = _T_4; // @[IBuf.scala:44:94] wire [2:0] _nBufValid_T_6; // @[IBuf.scala:56:26] assign _nBufValid_T_6 = _T_4; // @[IBuf.scala:44:94, :56:26] wire [1:0] _io_imem_ready_T_4 = _io_imem_ready_T_3[1:0]; // @[IBuf.scala:44:94] wire _io_imem_ready_T_5 = ~(_io_imem_ready_T_4[1]); // @[IBuf.scala:44:{87,94}] wire _io_imem_ready_T_6 = _io_imem_ready_T_2 | _io_imem_ready_T_5; // @[IBuf.scala:44:{73,80,87}] assign _io_imem_ready_T_7 = _io_imem_ready_T_1 & _io_imem_ready_T_6; // @[IBuf.scala:44:{37,60,80}] assign io_imem_ready_0 = _io_imem_ready_T_7; // @[IBuf.scala:21:7, :44:60] wire _nBufValid_T_1 = ~nBufValid; // @[package.scala:218:43] wire _nBufValid_T_2 = _nBufValid_T | _nBufValid_T_1; // @[package.scala:218:{33,38,43}] wire [2:0] _nBufValid_T_3 = _GEN_1 - _GEN_0; // @[IBuf.scala:42:25, :48:61] wire [1:0] _nBufValid_T_4 = _nBufValid_T_3[1:0]; // @[IBuf.scala:48:61] wire [1:0] _nBufValid_T_5 = _nBufValid_T_2 ? 2'h0 : _nBufValid_T_4; // @[package.scala:218:38] wire [2:0] _shamt_T = _GEN + _GEN_3; // @[IBuf.scala:41:86, :44:94, :55:32] wire [1:0] shamt = _shamt_T[1:0]; // @[IBuf.scala:55:32] wire [1:0] _nBufValid_T_7 = _nBufValid_T_6[1:0]; // @[IBuf.scala:56:26] wire [15:0] _buf_data_data_T = io_imem_bits_data_0[31:16]; // @[IBuf.scala:21:7, :127:58] wire [31:0] _buf_data_data_T_1 = {2{_buf_data_data_T}}; // @[IBuf.scala:127:{24,58}] wire [63:0] buf_data_data = {_buf_data_data_T_1, io_imem_bits_data_0}; // @[IBuf.scala:21:7, :127:{19,24}] wire [5:0] _buf_data_T = {shamt, 4'h0}; // @[IBuf.scala:55:32, :128:19] wire [63:0] _buf_data_T_1 = buf_data_data >> _buf_data_T; // @[IBuf.scala:127:19, :128:{10,19}] wire [15:0] _buf_data_T_2 = _buf_data_T_1[15:0]; // @[IBuf.scala:58:61, :128:10] wire [39:0] _buf_pc_T_1 = io_imem_bits_pc_0 & 40'hFFFFFFFFFC; // @[IBuf.scala:21:7, :59:35] wire [2:0] _buf_pc_T_2 = {nICReady, 1'h0}; // @[IBuf.scala:42:25, :59:80] wire [40:0] _buf_pc_T_3 = {1'h0, io_imem_bits_pc_0} + {38'h0, _buf_pc_T_2}; // @[IBuf.scala:21:7, :59:{68,80}] wire [39:0] _buf_pc_T_4 = _buf_pc_T_3[39:0]; // @[IBuf.scala:59:68] wire [39:0] _buf_pc_T_5 = _buf_pc_T_4 & 40'h3; // @[IBuf.scala:59:{68,109}] wire [39:0] _buf_pc_T_6 = _buf_pc_T_1 | _buf_pc_T_5; // @[IBuf.scala:59:{35,49,109}] wire [2:0] _icShiftAmt_T = _GEN_1 + 3'h2; // @[IBuf.scala:42:25, :68:34] wire [1:0] _icShiftAmt_T_1 = _icShiftAmt_T[1:0]; // @[IBuf.scala:68:34] wire [2:0] _icShiftAmt_T_2 = {1'h0, _icShiftAmt_T_1} - _GEN; // @[IBuf.scala:41:86, :68:{34,46}] wire [1:0] _icShiftAmt_T_3 = _icShiftAmt_T_2[1:0]; // @[IBuf.scala:68:46] wire [1:0] icShiftAmt = _icShiftAmt_T_3; // @[IBuf.scala:68:{46,59}] wire [15:0] _icData_T = io_imem_bits_data_0[15:0]; // @[IBuf.scala:21:7, :69:87] wire [31:0] _icData_T_1 = {2{_icData_T}}; // @[IBuf.scala:69:{57,87}] wire [63:0] _icData_T_2 = {io_imem_bits_data_0, _icData_T_1}; // @[IBuf.scala:21:7, :69:{33,57}] wire [15:0] _icData_data_T = _icData_T_2[63:48]; // @[IBuf.scala:69:33, :120:58] wire [31:0] _icData_data_T_1 = {2{_icData_data_T}}; // @[IBuf.scala:120:{24,58}] wire [63:0] _icData_data_T_2 = {2{_icData_data_T_1}}; // @[IBuf.scala:120:24] wire [127:0] icData_data = {_icData_data_T_2, _icData_T_2}; // @[IBuf.scala:69:33, :120:{19,24}] wire [5:0] _icData_T_3 = {icShiftAmt, 4'h0}; // @[IBuf.scala:68:59, :121:19] wire [190:0] _icData_T_4 = {63'h0, icData_data} << _icData_T_3; // @[IBuf.scala:120:19, :121:{10,19}] wire [31:0] icData = _icData_T_4[95:64]; // @[package.scala:163:13] wire [4:0] _icMask_T_1 = {nBufValid, 4'h0}; // @[IBuf.scala:34:47, :71:65] wire [62:0] _icMask_T_2 = 63'hFFFFFFFF << _icMask_T_1; // @[IBuf.scala:71:{51,65}] wire [31:0] icMask = _icMask_T_2[31:0]; // @[IBuf.scala:71:{51,92}] wire [31:0] _inst_T = icData & icMask; // @[package.scala:163:13] wire [31:0] _inst_T_1 = ~icMask; // @[IBuf.scala:71:92, :72:43] wire [31:0] _inst_T_2 = buf_data & _inst_T_1; // @[IBuf.scala:35:16, :72:{41,43}] assign inst = _inst_T | _inst_T_2; // @[IBuf.scala:72:{21,30,41}] assign io_inst_0_bits_raw_0 = inst; // @[IBuf.scala:21:7, :72:30] wire [3:0] _valid_T = 4'h1 << nValid; // @[OneHot.scala:58:35] wire [4:0] _valid_T_1 = {1'h0, _valid_T} - 5'h1; // @[OneHot.scala:58:35] wire [3:0] _valid_T_2 = _valid_T_1[3:0]; // @[IBuf.scala:74:33] wire [1:0] valid = _valid_T_2[1:0]; // @[IBuf.scala:74:{33,39}] wire [1:0] _io_inst_0_valid_T = valid; // @[IBuf.scala:74:39, :94:32] wire [1:0] _bufMask_T = 2'h1 << _GEN_2; // @[OneHot.scala:58:35] wire [2:0] _bufMask_T_1 = {1'h0, _bufMask_T} - 3'h1; // @[OneHot.scala:58:35] wire [1:0] bufMask = _bufMask_T_1[1:0]; // @[IBuf.scala:75:37] wire _xcpt_T = bufMask[0]; // @[IBuf.scala:75:37, :76:61] wire xcpt_0_pf_inst = _xcpt_T ? buf_xcpt_pf_inst : io_imem_bits_xcpt_pf_inst_0; // @[IBuf.scala:21:7, :35:16, :76:{53,61}] wire xcpt_0_gf_inst = _xcpt_T ? buf_xcpt_gf_inst : io_imem_bits_xcpt_gf_inst_0; // @[IBuf.scala:21:7, :35:16, :76:{53,61}] wire xcpt_0_ae_inst = _xcpt_T ? buf_xcpt_ae_inst : io_imem_bits_xcpt_ae_inst_0; // @[IBuf.scala:21:7, :35:16, :76:{53,61}] assign _io_inst_0_bits_xcpt0_T_1_pf_inst = xcpt_0_pf_inst; // @[package.scala:39:76] assign _io_inst_0_bits_xcpt0_T_1_gf_inst = xcpt_0_gf_inst; // @[package.scala:39:76] assign _io_inst_0_bits_xcpt0_T_1_ae_inst = xcpt_0_ae_inst; // @[package.scala:39:76] wire _xcpt_T_1 = bufMask[1]; // @[IBuf.scala:75:37, :76:61] wire xcpt_1_pf_inst = _xcpt_T_1 ? buf_xcpt_pf_inst : io_imem_bits_xcpt_pf_inst_0; // @[IBuf.scala:21:7, :35:16, :76:{53,61}] wire xcpt_1_gf_inst = _xcpt_T_1 ? buf_xcpt_gf_inst : io_imem_bits_xcpt_gf_inst_0; // @[IBuf.scala:21:7, :35:16, :76:{53,61}] wire xcpt_1_ae_inst = _xcpt_T_1 ? buf_xcpt_ae_inst : io_imem_bits_xcpt_ae_inst_0; // @[IBuf.scala:21:7, :35:16, :76:{53,61}] wire _io_inst_0_bits_xcpt1_T_3_pf_inst = xcpt_1_pf_inst; // @[package.scala:39:76] wire _io_inst_0_bits_xcpt1_T_3_gf_inst = xcpt_1_gf_inst; // @[package.scala:39:76] wire _io_inst_0_bits_xcpt1_T_3_ae_inst = xcpt_1_ae_inst; // @[package.scala:39:76] wire [1:0] buf_replay_0 = buf_replay ? bufMask : 2'h0; // @[IBuf.scala:35:16, :75:37, :77:23] wire [1:0] _full_insn_T_5 = buf_replay_0; // @[IBuf.scala:77:23, :93:63] wire [1:0] _ic_replay_T = ~bufMask; // @[IBuf.scala:75:37, :78:65] wire [1:0] _ic_replay_T_1 = valid & _ic_replay_T; // @[IBuf.scala:74:39, :78:{63,65}] wire [1:0] _ic_replay_T_2 = io_imem_bits_replay_0 ? _ic_replay_T_1 : 2'h0; // @[IBuf.scala:21:7, :78:{35,63}] wire [1:0] ic_replay = buf_replay_0 | _ic_replay_T_2; // @[IBuf.scala:77:23, :78:{30,35}] wire [1:0] _replay_T = ic_replay; // @[IBuf.scala:78:30, :92:29]
Generate the Verilog code corresponding to this FIRRTL code module EgressUnit_69 : input clock : Clock input reset : Reset output io : { flip in : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], credit_available : UInt<1>[1], channel_status : { occupied : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}[1], flip allocs : { alloc : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}[1], flip credit_alloc : { alloc : UInt<1>, tail : UInt<1>}[1], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} regreset channel_empty : UInt<1>, clock, reset, UInt<1>(0h1) reg flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, clock inst q of Queue3_EgressFlit_69 connect q.clock, clock connect q.reset, reset connect q.io.enq.valid, io.in[0].valid connect q.io.enq.bits.head, io.in[0].bits.head connect q.io.enq.bits.tail, io.in[0].bits.tail node _q_io_enq_bits_ingress_id_T = eq(UInt<2>(0h2), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_1 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_2 = and(_q_io_enq_bits_ingress_id_T, _q_io_enq_bits_ingress_id_T_1) connect q.io.enq.bits.ingress_id, UInt<5>(0h3) connect q.io.enq.bits.payload, io.in[0].bits.payload connect io.out.bits, q.io.deq.bits connect io.out.valid, q.io.deq.valid connect q.io.deq.ready, io.out.ready node _T = eq(q.io.enq.ready, UInt<1>(0h0)) node _T_1 = and(q.io.enq.valid, _T) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at EgressUnit.scala:38 assert(!(q.io.enq.valid && !q.io.enq.ready))\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _io_credit_available_0_T = eq(q.io.count, UInt<1>(0h0)) connect io.credit_available[0], _io_credit_available_0_T node _io_channel_status_0_occupied_T = eq(channel_empty, UInt<1>(0h0)) connect io.channel_status[0].occupied, _io_channel_status_0_occupied_T connect io.channel_status[0].flow, flow node _T_6 = and(io.credit_alloc[0].alloc, io.credit_alloc[0].tail) when _T_6 : connect channel_empty, UInt<1>(0h1) when io.allocs[0].alloc : connect channel_empty, UInt<1>(0h0) connect flow, io.allocs[0].flow
module EgressUnit_69( // @[EgressUnit.scala:12:7] input clock, // @[EgressUnit.scala:12:7] input reset, // @[EgressUnit.scala:12:7] input io_in_0_valid, // @[EgressUnit.scala:18:14] input io_in_0_bits_head, // @[EgressUnit.scala:18:14] input io_in_0_bits_tail, // @[EgressUnit.scala:18:14] input [72:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14] output io_credit_available_0, // @[EgressUnit.scala:18:14] output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14] input io_allocs_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14] input io_out_ready, // @[EgressUnit.scala:18:14] output io_out_valid, // @[EgressUnit.scala:18:14] output io_out_bits_head, // @[EgressUnit.scala:18:14] output io_out_bits_tail, // @[EgressUnit.scala:18:14] output [72:0] io_out_bits_payload // @[EgressUnit.scala:18:14] ); wire _q_io_enq_ready; // @[EgressUnit.scala:22:17] wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17] reg channel_empty; // @[EgressUnit.scala:20:30]
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_80 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<7>, poisoned : UInt<1>}}[2], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<7>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}} wire next_state : UInt wire next_uopc : UInt wire next_lrs1_rtype : UInt wire next_lrs2_rtype : UInt regreset state : UInt<2>, clock, reset, UInt<2>(0h0) regreset p1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p3 : UInt<1>, clock, reset, UInt<1>(0h0) regreset ppred : UInt<1>, clock, reset, UInt<1>(0h0) regreset p1_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) connect p1_poisoned, UInt<1>(0h0) connect p2_poisoned, UInt<1>(0h0) node next_p1_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) node next_p2_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) wire slot_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} invalidate slot_uop_uop.debug_tsrc invalidate slot_uop_uop.debug_fsrc invalidate slot_uop_uop.bp_xcpt_if invalidate slot_uop_uop.bp_debug_if invalidate slot_uop_uop.xcpt_ma_if invalidate slot_uop_uop.xcpt_ae_if invalidate slot_uop_uop.xcpt_pf_if invalidate slot_uop_uop.fp_single invalidate slot_uop_uop.fp_val invalidate slot_uop_uop.frs3_en invalidate slot_uop_uop.lrs2_rtype invalidate slot_uop_uop.lrs1_rtype invalidate slot_uop_uop.dst_rtype invalidate slot_uop_uop.ldst_val invalidate slot_uop_uop.lrs3 invalidate slot_uop_uop.lrs2 invalidate slot_uop_uop.lrs1 invalidate slot_uop_uop.ldst invalidate slot_uop_uop.ldst_is_rs1 invalidate slot_uop_uop.flush_on_commit invalidate slot_uop_uop.is_unique invalidate slot_uop_uop.is_sys_pc2epc invalidate slot_uop_uop.uses_stq invalidate slot_uop_uop.uses_ldq invalidate slot_uop_uop.is_amo invalidate slot_uop_uop.is_fencei invalidate slot_uop_uop.is_fence invalidate slot_uop_uop.mem_signed invalidate slot_uop_uop.mem_size invalidate slot_uop_uop.mem_cmd invalidate slot_uop_uop.bypassable invalidate slot_uop_uop.exc_cause invalidate slot_uop_uop.exception invalidate slot_uop_uop.stale_pdst invalidate slot_uop_uop.ppred_busy invalidate slot_uop_uop.prs3_busy invalidate slot_uop_uop.prs2_busy invalidate slot_uop_uop.prs1_busy invalidate slot_uop_uop.ppred invalidate slot_uop_uop.prs3 invalidate slot_uop_uop.prs2 invalidate slot_uop_uop.prs1 invalidate slot_uop_uop.pdst invalidate slot_uop_uop.rxq_idx invalidate slot_uop_uop.stq_idx invalidate slot_uop_uop.ldq_idx invalidate slot_uop_uop.rob_idx invalidate slot_uop_uop.csr_addr invalidate slot_uop_uop.imm_packed invalidate slot_uop_uop.taken invalidate slot_uop_uop.pc_lob invalidate slot_uop_uop.edge_inst invalidate slot_uop_uop.ftq_idx invalidate slot_uop_uop.br_tag invalidate slot_uop_uop.br_mask invalidate slot_uop_uop.is_sfb invalidate slot_uop_uop.is_jal invalidate slot_uop_uop.is_jalr invalidate slot_uop_uop.is_br invalidate slot_uop_uop.iw_p2_poisoned invalidate slot_uop_uop.iw_p1_poisoned invalidate slot_uop_uop.iw_state invalidate slot_uop_uop.ctrl.is_std invalidate slot_uop_uop.ctrl.is_sta invalidate slot_uop_uop.ctrl.is_load invalidate slot_uop_uop.ctrl.csr_cmd invalidate slot_uop_uop.ctrl.fcn_dw invalidate slot_uop_uop.ctrl.op_fcn invalidate slot_uop_uop.ctrl.imm_sel invalidate slot_uop_uop.ctrl.op2_sel invalidate slot_uop_uop.ctrl.op1_sel invalidate slot_uop_uop.ctrl.br_type invalidate slot_uop_uop.fu_code invalidate slot_uop_uop.iq_type invalidate slot_uop_uop.debug_pc invalidate slot_uop_uop.is_rvc invalidate slot_uop_uop.debug_inst invalidate slot_uop_uop.inst invalidate slot_uop_uop.uopc connect slot_uop_uop.uopc, UInt<7>(0h0) connect slot_uop_uop.bypassable, UInt<1>(0h0) connect slot_uop_uop.fp_val, UInt<1>(0h0) connect slot_uop_uop.uses_stq, UInt<1>(0h0) connect slot_uop_uop.uses_ldq, UInt<1>(0h0) connect slot_uop_uop.pdst, UInt<1>(0h0) connect slot_uop_uop.dst_rtype, UInt<2>(0h2) wire slot_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>} invalidate slot_uop_cs.is_std invalidate slot_uop_cs.is_sta invalidate slot_uop_cs.is_load invalidate slot_uop_cs.csr_cmd invalidate slot_uop_cs.fcn_dw invalidate slot_uop_cs.op_fcn invalidate slot_uop_cs.imm_sel invalidate slot_uop_cs.op2_sel invalidate slot_uop_cs.op1_sel invalidate slot_uop_cs.br_type connect slot_uop_cs.br_type, UInt<4>(0h0) connect slot_uop_cs.csr_cmd, UInt<3>(0h0) connect slot_uop_cs.is_load, UInt<1>(0h0) connect slot_uop_cs.is_sta, UInt<1>(0h0) connect slot_uop_cs.is_std, UInt<1>(0h0) connect slot_uop_uop.ctrl, slot_uop_cs regreset slot_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock, reset, slot_uop_uop node next_uop = mux(io.in_uop.valid, io.in_uop.bits, slot_uop) when io.kill : connect state, UInt<2>(0h0) else : when io.in_uop.valid : connect state, io.in_uop.bits.iw_state else : when io.clear : connect state, UInt<2>(0h0) else : connect state, next_state connect next_state, state connect next_uopc, slot_uop.uopc connect next_lrs1_rtype, slot_uop.lrs1_rtype connect next_lrs2_rtype, slot_uop.lrs2_rtype when io.kill : connect next_state, UInt<2>(0h0) else : node _T = eq(state, UInt<2>(0h1)) node _T_1 = and(io.grant, _T) node _T_2 = eq(state, UInt<2>(0h2)) node _T_3 = and(io.grant, _T_2) node _T_4 = and(_T_3, p1) node _T_5 = and(_T_4, p2) node _T_6 = and(_T_5, ppred) node _T_7 = or(_T_1, _T_6) when _T_7 : node _T_8 = or(p1_poisoned, p2_poisoned) node _T_9 = and(io.ldspec_miss, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : connect next_state, UInt<2>(0h0) else : node _T_11 = eq(state, UInt<2>(0h2)) node _T_12 = and(io.grant, _T_11) when _T_12 : node _T_13 = or(p1_poisoned, p2_poisoned) node _T_14 = and(io.ldspec_miss, _T_13) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : connect next_state, UInt<2>(0h1) when p1 : connect slot_uop.uopc, UInt<7>(0h3) connect next_uopc, UInt<7>(0h3) connect slot_uop.lrs1_rtype, UInt<2>(0h2) connect next_lrs1_rtype, UInt<2>(0h2) else : connect slot_uop.lrs2_rtype, UInt<2>(0h2) connect next_lrs2_rtype, UInt<2>(0h2) when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T_16 = eq(state, UInt<2>(0h0)) node _T_17 = or(_T_16, io.clear) node _T_18 = or(_T_17, io.kill) node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : node _T_21 = eq(_T_18, UInt<1>(0h0)) when _T_21 : printf(clock, UInt<1>(0h1), "Assertion failed: trying to overwrite a valid issue slot.\n at issue-slot.scala:156 assert (is_invalid || io.clear || io.kill, \"trying to overwrite a valid issue slot.\")\n") : printf assert(clock, _T_18, UInt<1>(0h1), "") : assert wire next_p1 : UInt<1> connect next_p1, p1 wire next_p2 : UInt<1> connect next_p2, p2 wire next_p3 : UInt<1> connect next_p3, p3 wire next_ppred : UInt<1> connect next_ppred, ppred when io.in_uop.valid : node _p1_T = eq(io.in_uop.bits.prs1_busy, UInt<1>(0h0)) connect p1, _p1_T node _p2_T = eq(io.in_uop.bits.prs2_busy, UInt<1>(0h0)) connect p2, _p2_T node _p3_T = eq(io.in_uop.bits.prs3_busy, UInt<1>(0h0)) connect p3, _p3_T node _ppred_T = eq(io.in_uop.bits.ppred_busy, UInt<1>(0h0)) connect ppred, _ppred_T node _T_22 = and(io.ldspec_miss, next_p1_poisoned) when _T_22 : node _T_23 = neq(next_uop.prs1, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs1=x0!\n at issue-slot.scala:176 assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n") : printf_1 assert(clock, _T_23, UInt<1>(0h1), "") : assert_1 connect p1, UInt<1>(0h0) node _T_27 = and(io.ldspec_miss, next_p2_poisoned) when _T_27 : node _T_28 = neq(next_uop.prs2, UInt<1>(0h0)) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs2=x0!\n at issue-slot.scala:180 assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n") : printf_2 assert(clock, _T_28, UInt<1>(0h1), "") : assert_2 connect p2, UInt<1>(0h0) node _T_32 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs1) node _T_33 = and(io.wakeup_ports[0].valid, _T_32) when _T_33 : connect p1, UInt<1>(0h1) node _T_34 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs2) node _T_35 = and(io.wakeup_ports[0].valid, _T_34) when _T_35 : connect p2, UInt<1>(0h1) node _T_36 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs3) node _T_37 = and(io.wakeup_ports[0].valid, _T_36) when _T_37 : connect p3, UInt<1>(0h1) node _T_38 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs1) node _T_39 = and(io.wakeup_ports[1].valid, _T_38) when _T_39 : connect p1, UInt<1>(0h1) node _T_40 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs2) node _T_41 = and(io.wakeup_ports[1].valid, _T_40) when _T_41 : connect p2, UInt<1>(0h1) node _T_42 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs3) node _T_43 = and(io.wakeup_ports[1].valid, _T_42) when _T_43 : connect p3, UInt<1>(0h1) node _T_44 = eq(io.pred_wakeup_port.bits, next_uop.ppred) node _T_45 = and(io.pred_wakeup_port.valid, _T_44) when _T_45 : connect ppred, UInt<1>(0h1) node _T_46 = eq(io.spec_ld_wakeup[0].bits, UInt<1>(0h0)) node _T_47 = and(io.spec_ld_wakeup[0].valid, _T_46) node _T_48 = eq(_T_47, UInt<1>(0h0)) node _T_49 = asUInt(reset) node _T_50 = eq(_T_49, UInt<1>(0h0)) when _T_50 : node _T_51 = eq(_T_48, UInt<1>(0h0)) when _T_51 : printf(clock, UInt<1>(0h1), "Assertion failed: Loads to x0 should never speculatively wakeup other instructions\n at issue-slot.scala:203 assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n") : printf_3 assert(clock, _T_48, UInt<1>(0h1), "") : assert_3 node _T_52 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs1) node _T_53 = and(io.spec_ld_wakeup[0].valid, _T_52) node _T_54 = eq(next_uop.lrs1_rtype, UInt<2>(0h0)) node _T_55 = and(_T_53, _T_54) when _T_55 : connect p1, UInt<1>(0h1) connect p1_poisoned, UInt<1>(0h1) node _T_56 = eq(next_p1_poisoned, UInt<1>(0h0)) node _T_57 = asUInt(reset) node _T_58 = eq(_T_57, UInt<1>(0h0)) when _T_58 : node _T_59 = eq(_T_56, UInt<1>(0h0)) when _T_59 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:214 assert (!next_p1_poisoned)\n") : printf_4 assert(clock, _T_56, UInt<1>(0h1), "") : assert_4 node _T_60 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs2) node _T_61 = and(io.spec_ld_wakeup[0].valid, _T_60) node _T_62 = eq(next_uop.lrs2_rtype, UInt<2>(0h0)) node _T_63 = and(_T_61, _T_62) when _T_63 : connect p2, UInt<1>(0h1) connect p2_poisoned, UInt<1>(0h1) node _T_64 = eq(next_p2_poisoned, UInt<1>(0h0)) node _T_65 = asUInt(reset) node _T_66 = eq(_T_65, UInt<1>(0h0)) when _T_66 : node _T_67 = eq(_T_64, UInt<1>(0h0)) when _T_67 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:221 assert (!next_p2_poisoned)\n") : printf_5 assert(clock, _T_64, UInt<1>(0h1), "") : assert_5 node _next_br_mask_T = not(io.brupdate.b1.resolve_mask) node next_br_mask = and(slot_uop.br_mask, _next_br_mask_T) node _T_68 = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _T_69 = neq(_T_68, UInt<1>(0h0)) when _T_69 : connect next_state, UInt<2>(0h0) node _T_70 = eq(io.in_uop.valid, UInt<1>(0h0)) when _T_70 : connect slot_uop.br_mask, next_br_mask node _io_request_T = neq(state, UInt<2>(0h0)) node _io_request_T_1 = and(_io_request_T, p1) node _io_request_T_2 = and(_io_request_T_1, p2) node _io_request_T_3 = and(_io_request_T_2, p3) node _io_request_T_4 = and(_io_request_T_3, ppred) node _io_request_T_5 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_6 = and(_io_request_T_4, _io_request_T_5) connect io.request, _io_request_T_6 node _high_priority_T = or(slot_uop.is_br, slot_uop.is_jal) node high_priority = or(_high_priority_T, slot_uop.is_jalr) node _io_request_hp_T = and(io.request, high_priority) connect io.request_hp, _io_request_hp_T node _T_71 = eq(state, UInt<2>(0h1)) when _T_71 : node _io_request_T_7 = and(p1, p2) node _io_request_T_8 = and(_io_request_T_7, p3) node _io_request_T_9 = and(_io_request_T_8, ppred) node _io_request_T_10 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_11 = and(_io_request_T_9, _io_request_T_10) connect io.request, _io_request_T_11 else : node _T_72 = eq(state, UInt<2>(0h2)) when _T_72 : node _io_request_T_12 = or(p1, p2) node _io_request_T_13 = and(_io_request_T_12, ppred) node _io_request_T_14 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_15 = and(_io_request_T_13, _io_request_T_14) connect io.request, _io_request_T_15 else : connect io.request, UInt<1>(0h0) node _io_valid_T = neq(state, UInt<2>(0h0)) connect io.valid, _io_valid_T connect io.uop, slot_uop connect io.uop.iw_p1_poisoned, p1_poisoned connect io.uop.iw_p2_poisoned, p2_poisoned node _may_vacate_T = eq(state, UInt<2>(0h1)) node _may_vacate_T_1 = eq(state, UInt<2>(0h2)) node _may_vacate_T_2 = and(_may_vacate_T_1, p1) node _may_vacate_T_3 = and(_may_vacate_T_2, p2) node _may_vacate_T_4 = and(_may_vacate_T_3, ppred) node _may_vacate_T_5 = or(_may_vacate_T, _may_vacate_T_4) node may_vacate = and(io.grant, _may_vacate_T_5) node _squash_grant_T = or(p1_poisoned, p2_poisoned) node squash_grant = and(io.ldspec_miss, _squash_grant_T) node _io_will_be_valid_T = neq(state, UInt<2>(0h0)) node _io_will_be_valid_T_1 = eq(squash_grant, UInt<1>(0h0)) node _io_will_be_valid_T_2 = and(may_vacate, _io_will_be_valid_T_1) node _io_will_be_valid_T_3 = eq(_io_will_be_valid_T_2, UInt<1>(0h0)) node _io_will_be_valid_T_4 = and(_io_will_be_valid_T, _io_will_be_valid_T_3) connect io.will_be_valid, _io_will_be_valid_T_4 connect io.out_uop, slot_uop connect io.out_uop.iw_state, next_state connect io.out_uop.uopc, next_uopc connect io.out_uop.lrs1_rtype, next_lrs1_rtype connect io.out_uop.lrs2_rtype, next_lrs2_rtype connect io.out_uop.br_mask, next_br_mask node _io_out_uop_prs1_busy_T = eq(p1, UInt<1>(0h0)) connect io.out_uop.prs1_busy, _io_out_uop_prs1_busy_T node _io_out_uop_prs2_busy_T = eq(p2, UInt<1>(0h0)) connect io.out_uop.prs2_busy, _io_out_uop_prs2_busy_T node _io_out_uop_prs3_busy_T = eq(p3, UInt<1>(0h0)) connect io.out_uop.prs3_busy, _io_out_uop_prs3_busy_T node _io_out_uop_ppred_busy_T = eq(ppred, UInt<1>(0h0)) connect io.out_uop.ppred_busy, _io_out_uop_ppred_busy_T connect io.out_uop.iw_p1_poisoned, p1_poisoned connect io.out_uop.iw_p2_poisoned, p2_poisoned node _T_73 = eq(state, UInt<2>(0h2)) when _T_73 : node _T_74 = and(p1, p2) node _T_75 = and(_T_74, ppred) when _T_75 : skip else : node _T_76 = and(p1, ppred) when _T_76 : connect io.uop.uopc, slot_uop.uopc connect io.uop.lrs2_rtype, UInt<2>(0h2) else : node _T_77 = and(p2, ppred) when _T_77 : connect io.uop.uopc, UInt<7>(0h3) connect io.uop.lrs1_rtype, UInt<2>(0h2) connect io.debug.p1, p1 connect io.debug.p2, p2 connect io.debug.p3, p3 connect io.debug.ppred, ppred connect io.debug.state, state
module IssueSlot_80( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_ldspec_miss = 1'h0; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire next_p1_poisoned = 1'h0; // @[issue-slot.scala:99:29] wire next_p2_poisoned = 1'h0; // @[issue-slot.scala:100:29] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire _squash_grant_T = 1'h0; // @[issue-slot.scala:261:53] wire squash_grant = 1'h0; // @[issue-slot.scala:261:37] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [6:0] io_spec_ld_wakeup_0_bits = 7'h0; // @[issue-slot.scala:69:7] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire _io_will_be_valid_T_1 = 1'h1; // @[issue-slot.scala:262:51] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [15:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _GEN = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_0 = _GEN | ~(_T_12 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17, :143:23] assign next_uopc = _GEN_0 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_0 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_1 = _GEN | ~_T_12 | p1; // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17] assign next_lrs2_rtype = _GEN_1 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17]
Generate the Verilog code corresponding to this FIRRTL code module EgressUnit_5 : input clock : Clock input reset : Reset output io : { flip in : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], credit_available : UInt<1>[1], channel_status : { occupied : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], flip allocs : { alloc : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], flip credit_alloc : { alloc : UInt<1>, tail : UInt<1>}[1], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, ingress_id : UInt}}} regreset channel_empty : UInt<1>, clock, reset, UInt<1>(0h1) reg flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, clock inst q of Queue2_EgressFlit_5 connect q.clock, clock connect q.reset, reset connect q.io.enq.valid, io.in[0].valid connect q.io.enq.bits.head, io.in[0].bits.head connect q.io.enq.bits.tail, io.in[0].bits.tail node _q_io_enq_bits_ingress_id_T = eq(UInt<4>(0h9), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_1 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_2 = and(_q_io_enq_bits_ingress_id_T, _q_io_enq_bits_ingress_id_T_1) node _q_io_enq_bits_ingress_id_T_3 = eq(UInt<3>(0h6), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_4 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_5 = and(_q_io_enq_bits_ingress_id_T_3, _q_io_enq_bits_ingress_id_T_4) node _q_io_enq_bits_ingress_id_T_6 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_7 = eq(UInt<3>(0h4), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_8 = and(_q_io_enq_bits_ingress_id_T_6, _q_io_enq_bits_ingress_id_T_7) node _q_io_enq_bits_ingress_id_T_9 = eq(UInt<3>(0h5), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_10 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_11 = and(_q_io_enq_bits_ingress_id_T_9, _q_io_enq_bits_ingress_id_T_10) node _q_io_enq_bits_ingress_id_T_12 = eq(UInt<4>(0ha), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_13 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_14 = and(_q_io_enq_bits_ingress_id_T_12, _q_io_enq_bits_ingress_id_T_13) node _q_io_enq_bits_ingress_id_T_15 = mux(_q_io_enq_bits_ingress_id_T_2, UInt<5>(0h1d), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_16 = mux(_q_io_enq_bits_ingress_id_T_5, UInt<5>(0h1c), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_17 = mux(_q_io_enq_bits_ingress_id_T_8, UInt<5>(0h1a), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_18 = mux(_q_io_enq_bits_ingress_id_T_11, UInt<5>(0h1b), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_19 = mux(_q_io_enq_bits_ingress_id_T_14, UInt<5>(0h1e), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_20 = or(_q_io_enq_bits_ingress_id_T_15, _q_io_enq_bits_ingress_id_T_16) node _q_io_enq_bits_ingress_id_T_21 = or(_q_io_enq_bits_ingress_id_T_20, _q_io_enq_bits_ingress_id_T_17) node _q_io_enq_bits_ingress_id_T_22 = or(_q_io_enq_bits_ingress_id_T_21, _q_io_enq_bits_ingress_id_T_18) node _q_io_enq_bits_ingress_id_T_23 = or(_q_io_enq_bits_ingress_id_T_22, _q_io_enq_bits_ingress_id_T_19) wire _q_io_enq_bits_ingress_id_WIRE : UInt<5> connect _q_io_enq_bits_ingress_id_WIRE, _q_io_enq_bits_ingress_id_T_23 connect q.io.enq.bits.ingress_id, _q_io_enq_bits_ingress_id_WIRE connect q.io.enq.bits.payload, io.in[0].bits.payload connect io.out.bits, q.io.deq.bits connect io.out.valid, q.io.deq.valid connect q.io.deq.ready, io.out.ready node _T = eq(q.io.enq.ready, UInt<1>(0h0)) node _T_1 = and(q.io.enq.valid, _T) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at EgressUnit.scala:38 assert(!(q.io.enq.valid && !q.io.enq.ready))\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _io_credit_available_0_T = eq(q.io.count, UInt<1>(0h0)) connect io.credit_available[0], _io_credit_available_0_T node _io_channel_status_0_occupied_T = eq(channel_empty, UInt<1>(0h0)) connect io.channel_status[0].occupied, _io_channel_status_0_occupied_T connect io.channel_status[0].flow, flow node _T_6 = and(io.credit_alloc[0].alloc, io.credit_alloc[0].tail) when _T_6 : connect channel_empty, UInt<1>(0h1) when io.allocs[0].alloc : connect channel_empty, UInt<1>(0h0) connect flow, io.allocs[0].flow
module EgressUnit_5( // @[EgressUnit.scala:12:7] input clock, // @[EgressUnit.scala:12:7] input reset, // @[EgressUnit.scala:12:7] input io_in_0_valid, // @[EgressUnit.scala:18:14] input io_in_0_bits_head, // @[EgressUnit.scala:18:14] input io_in_0_bits_tail, // @[EgressUnit.scala:18:14] input [144:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14] input [3:0] io_in_0_bits_flow_ingress_node, // @[EgressUnit.scala:18:14] input [2:0] io_in_0_bits_flow_ingress_node_id, // @[EgressUnit.scala:18:14] output io_credit_available_0, // @[EgressUnit.scala:18:14] output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14] input io_allocs_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14] input io_out_ready, // @[EgressUnit.scala:18:14] output io_out_valid, // @[EgressUnit.scala:18:14] output io_out_bits_head, // @[EgressUnit.scala:18:14] output io_out_bits_tail, // @[EgressUnit.scala:18:14] output [144:0] io_out_bits_payload // @[EgressUnit.scala:18:14] ); wire _q_io_enq_ready; // @[EgressUnit.scala:22:17] wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17] reg channel_empty; // @[EgressUnit.scala:20:30] wire _q_io_enq_bits_ingress_id_T_13 = io_in_0_bits_flow_ingress_node_id == 3'h0; // @[EgressUnit.scala:32:27]
Generate the Verilog code corresponding to this FIRRTL code module PE_279 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_23 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<32>, clock reg c2 : SInt<32>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node c1_sign = bits(io.in_d, 19, 19) node c1_lo_lo_hi = cat(c1_sign, c1_sign) node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign) node c1_lo_hi_hi = cat(c1_sign, c1_sign) node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign) node c1_lo = cat(c1_lo_hi, c1_lo_lo) node c1_hi_lo_hi = cat(c1_sign, c1_sign) node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign) node c1_hi_hi_hi = cat(c1_sign, c1_sign) node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign) node c1_hi = cat(c1_hi_hi, c1_hi_lo) node _c1_T = cat(c1_hi, c1_lo) node c1_lo_1 = asUInt(io.in_d) node _c1_T_1 = cat(_c1_T, c1_lo_1) wire _c1_WIRE : SInt<32> node _c1_T_2 = asSInt(_c1_T_1) connect _c1_WIRE, _c1_T_2 connect c1, _c1_WIRE else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node c2_sign = bits(io.in_d, 19, 19) node c2_lo_lo_hi = cat(c2_sign, c2_sign) node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign) node c2_lo_hi_hi = cat(c2_sign, c2_sign) node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign) node c2_lo = cat(c2_lo_hi, c2_lo_lo) node c2_hi_lo_hi = cat(c2_sign, c2_sign) node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign) node c2_hi_hi_hi = cat(c2_sign, c2_sign) node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign) node c2_hi = cat(c2_hi_hi, c2_hi_lo) node _c2_T = cat(c2_hi, c2_lo) node c2_lo_1 = asUInt(io.in_d) node _c2_T_1 = cat(_c2_T, c2_lo_1) wire _c2_WIRE : SInt<32> node _c2_T_2 = asSInt(_c2_T_1) connect _c2_WIRE, _c2_T_2 connect c2, _c2_WIRE else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h1), _T_4) node _T_6 = or(UInt<1>(0h0), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c
module PE_279( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_23 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module BranchDecode_5 : input clock : Clock input reset : Reset output io : { flip inst : UInt<32>, flip pc : UInt<40>, out : { is_ret : UInt<1>, is_call : UInt<1>, target : UInt<40>, cfi_type : UInt<3>, sfb_offset : { valid : UInt<1>, bits : UInt<6>}, shadowable : UInt<1>}} wire bpd_csignals_decoded_plaInput : UInt<32> node bpd_csignals_decoded_invInputs = not(bpd_csignals_decoded_plaInput) wire bpd_csignals_decoded : UInt<5> node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2 = bits(bpd_csignals_decoded_invInputs, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3 = bits(bpd_csignals_decoded_invInputs, 3, 3) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4 = bits(bpd_csignals_decoded_plaInput, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5 = bits(bpd_csignals_decoded_invInputs, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6 = bits(bpd_csignals_decoded_invInputs, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7 = bits(bpd_csignals_decoded_invInputs, 12, 12) node bpd_csignals_decoded_andMatrixOutputs_lo_lo = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7) node bpd_csignals_decoded_andMatrixOutputs_lo_hi = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5) node bpd_csignals_decoded_andMatrixOutputs_lo = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi, bpd_csignals_decoded_andMatrixOutputs_lo_lo) node bpd_csignals_decoded_andMatrixOutputs_hi_lo = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3) node bpd_csignals_decoded_andMatrixOutputs_hi_hi = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1) node bpd_csignals_decoded_andMatrixOutputs_hi = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi, bpd_csignals_decoded_andMatrixOutputs_hi_lo) node _bpd_csignals_decoded_andMatrixOutputs_T = cat(bpd_csignals_decoded_andMatrixOutputs_hi, bpd_csignals_decoded_andMatrixOutputs_lo) node bpd_csignals_decoded_andMatrixOutputs_5_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(bpd_csignals_decoded_invInputs, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(bpd_csignals_decoded_plaInput, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(bpd_csignals_decoded_invInputs, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(bpd_csignals_decoded_invInputs, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(bpd_csignals_decoded_invInputs, 12, 12) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_1 = bits(bpd_csignals_decoded_invInputs, 13, 13) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8 = bits(bpd_csignals_decoded_invInputs, 14, 14) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_1 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_1 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_1) node bpd_csignals_decoded_andMatrixOutputs_lo_1 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_1, bpd_csignals_decoded_andMatrixOutputs_lo_lo_1) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_1 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_1) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_1) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_1 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_1) node bpd_csignals_decoded_andMatrixOutputs_hi_1 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_1, bpd_csignals_decoded_andMatrixOutputs_hi_lo_1) node _bpd_csignals_decoded_andMatrixOutputs_T_1 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_1, bpd_csignals_decoded_andMatrixOutputs_lo_1) node bpd_csignals_decoded_andMatrixOutputs_9_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(bpd_csignals_decoded_invInputs, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(bpd_csignals_decoded_plaInput, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(bpd_csignals_decoded_plaInput, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(bpd_csignals_decoded_invInputs, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(bpd_csignals_decoded_invInputs, 12, 12) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_2 = bits(bpd_csignals_decoded_invInputs, 13, 13) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_1 = bits(bpd_csignals_decoded_invInputs, 14, 14) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9 = bits(bpd_csignals_decoded_invInputs, 25, 25) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10 = bits(bpd_csignals_decoded_invInputs, 26, 26) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11 = bits(bpd_csignals_decoded_invInputs, 27, 27) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12 = bits(bpd_csignals_decoded_invInputs, 28, 28) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13 = bits(bpd_csignals_decoded_invInputs, 29, 29) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14 = bits(bpd_csignals_decoded_invInputs, 31, 31) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_2 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_2 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo) node bpd_csignals_decoded_andMatrixOutputs_lo_2 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_2, bpd_csignals_decoded_andMatrixOutputs_lo_lo_2) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_2) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_2) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_2 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_2) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_1 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_2) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_2 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_1, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo) node bpd_csignals_decoded_andMatrixOutputs_hi_2 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_2, bpd_csignals_decoded_andMatrixOutputs_hi_lo_2) node _bpd_csignals_decoded_andMatrixOutputs_T_2 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_2, bpd_csignals_decoded_andMatrixOutputs_lo_2) node bpd_csignals_decoded_andMatrixOutputs_14_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(bpd_csignals_decoded_invInputs, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(bpd_csignals_decoded_invInputs, 3, 3) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(bpd_csignals_decoded_plaInput, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(bpd_csignals_decoded_plaInput, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(bpd_csignals_decoded_invInputs, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_3 = bits(bpd_csignals_decoded_invInputs, 25, 25) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_2 = bits(bpd_csignals_decoded_invInputs, 26, 26) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_1 = bits(bpd_csignals_decoded_invInputs, 27, 27) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_1 = bits(bpd_csignals_decoded_invInputs, 28, 28) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_1 = bits(bpd_csignals_decoded_invInputs, 29, 29) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_1 = bits(bpd_csignals_decoded_invInputs, 30, 30) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_1 = bits(bpd_csignals_decoded_invInputs, 31, 31) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_1 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_1) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_3 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_1) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_1 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_1) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_1 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_2) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_3 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_1, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_1) node bpd_csignals_decoded_andMatrixOutputs_lo_3 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_3, bpd_csignals_decoded_andMatrixOutputs_lo_lo_3) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_1 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_3) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_3 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_3) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_1 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_3) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_2 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_3) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_3 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_2, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_1) node bpd_csignals_decoded_andMatrixOutputs_hi_3 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_3, bpd_csignals_decoded_andMatrixOutputs_hi_lo_3) node _bpd_csignals_decoded_andMatrixOutputs_T_3 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_3, bpd_csignals_decoded_andMatrixOutputs_lo_3) node bpd_csignals_decoded_andMatrixOutputs_0_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_3) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(bpd_csignals_decoded_invInputs, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(bpd_csignals_decoded_plaInput, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(bpd_csignals_decoded_plaInput, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(bpd_csignals_decoded_invInputs, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(bpd_csignals_decoded_invInputs, 13, 13) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_4 = bits(bpd_csignals_decoded_invInputs, 14, 14) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_3 = bits(bpd_csignals_decoded_invInputs, 25, 25) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_2 = bits(bpd_csignals_decoded_invInputs, 26, 26) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_2 = bits(bpd_csignals_decoded_invInputs, 27, 27) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_2 = bits(bpd_csignals_decoded_invInputs, 28, 28) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_2 = bits(bpd_csignals_decoded_invInputs, 29, 29) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_2 = bits(bpd_csignals_decoded_invInputs, 30, 30) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_1 = bits(bpd_csignals_decoded_invInputs, 31, 31) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_2 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_2) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_4 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_1) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_2 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_2) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_2 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_2) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_4 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_2, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_2) node bpd_csignals_decoded_andMatrixOutputs_lo_4 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_4, bpd_csignals_decoded_andMatrixOutputs_lo_lo_4) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_1 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_4) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_2 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_4) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_4 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_2, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_1) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_2 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_4) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_3 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_4) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_4 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_3, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_2) node bpd_csignals_decoded_andMatrixOutputs_hi_4 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_4, bpd_csignals_decoded_andMatrixOutputs_hi_lo_4) node _bpd_csignals_decoded_andMatrixOutputs_T_4 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_4, bpd_csignals_decoded_andMatrixOutputs_lo_4) node bpd_csignals_decoded_andMatrixOutputs_2_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(bpd_csignals_decoded_plaInput, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(bpd_csignals_decoded_invInputs, 3, 3) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(bpd_csignals_decoded_plaInput, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(bpd_csignals_decoded_plaInput, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(bpd_csignals_decoded_invInputs, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_5) node bpd_csignals_decoded_andMatrixOutputs_lo_5 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_5) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_5) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_5) node bpd_csignals_decoded_andMatrixOutputs_hi_5 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_5, bpd_csignals_decoded_andMatrixOutputs_hi_lo_5) node _bpd_csignals_decoded_andMatrixOutputs_T_5 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_5, bpd_csignals_decoded_andMatrixOutputs_lo_5) node bpd_csignals_decoded_andMatrixOutputs_12_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(bpd_csignals_decoded_invInputs, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(bpd_csignals_decoded_invInputs, 3, 3) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(bpd_csignals_decoded_invInputs, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(bpd_csignals_decoded_plaInput, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(bpd_csignals_decoded_plaInput, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_5 = bits(bpd_csignals_decoded_invInputs, 13, 13) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_5) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_6) node bpd_csignals_decoded_andMatrixOutputs_lo_6 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_6, bpd_csignals_decoded_andMatrixOutputs_lo_lo_5) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_6) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_6) node bpd_csignals_decoded_andMatrixOutputs_hi_6 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_6, bpd_csignals_decoded_andMatrixOutputs_hi_lo_6) node _bpd_csignals_decoded_andMatrixOutputs_T_6 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_6, bpd_csignals_decoded_andMatrixOutputs_lo_6) node bpd_csignals_decoded_andMatrixOutputs_6_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(bpd_csignals_decoded_plaInput, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(bpd_csignals_decoded_invInputs, 3, 3) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(bpd_csignals_decoded_invInputs, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(bpd_csignals_decoded_plaInput, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(bpd_csignals_decoded_plaInput, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_6 = bits(bpd_csignals_decoded_invInputs, 12, 12) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_4 = bits(bpd_csignals_decoded_invInputs, 13, 13) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_3 = bits(bpd_csignals_decoded_invInputs, 14, 14) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_3) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_3 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_7) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_7 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_6) node bpd_csignals_decoded_andMatrixOutputs_lo_7 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_7, bpd_csignals_decoded_andMatrixOutputs_lo_lo_6) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_7 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_7) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_4 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_7) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_7 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_7) node bpd_csignals_decoded_andMatrixOutputs_hi_7 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_7, bpd_csignals_decoded_andMatrixOutputs_hi_lo_7) node _bpd_csignals_decoded_andMatrixOutputs_T_7 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_7, bpd_csignals_decoded_andMatrixOutputs_lo_7) node bpd_csignals_decoded_andMatrixOutputs_15_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_7) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(bpd_csignals_decoded_plaInput, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(bpd_csignals_decoded_plaInput, 3, 3) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_8 = bits(bpd_csignals_decoded_invInputs, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_8 = bits(bpd_csignals_decoded_plaInput, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_8 = bits(bpd_csignals_decoded_plaInput, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_8 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_8) node bpd_csignals_decoded_andMatrixOutputs_lo_8 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_8) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_8 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_8) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_8 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_8) node bpd_csignals_decoded_andMatrixOutputs_hi_8 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_8, bpd_csignals_decoded_andMatrixOutputs_hi_lo_8) node _bpd_csignals_decoded_andMatrixOutputs_T_8 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_8, bpd_csignals_decoded_andMatrixOutputs_lo_8) node bpd_csignals_decoded_andMatrixOutputs_11_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_8) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_9 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_9 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_9 = bits(bpd_csignals_decoded_invInputs, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_9 = bits(bpd_csignals_decoded_invInputs, 3, 3) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_9 = bits(bpd_csignals_decoded_plaInput, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_9 = bits(bpd_csignals_decoded_invInputs, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_9 = bits(bpd_csignals_decoded_invInputs, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_7 = bits(bpd_csignals_decoded_plaInput, 12, 12) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_5 = bits(bpd_csignals_decoded_invInputs, 13, 13) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_4 = bits(bpd_csignals_decoded_invInputs, 26, 26) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_3 = bits(bpd_csignals_decoded_invInputs, 27, 27) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_3 = bits(bpd_csignals_decoded_invInputs, 28, 28) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_3 = bits(bpd_csignals_decoded_invInputs, 29, 29) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_3 = bits(bpd_csignals_decoded_invInputs, 30, 30) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_2 = bits(bpd_csignals_decoded_invInputs, 31, 31) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_3 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_3) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_7 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_2) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_3 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_3) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_4 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_4) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_9 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_4, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_3) node bpd_csignals_decoded_andMatrixOutputs_lo_9 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_9, bpd_csignals_decoded_andMatrixOutputs_lo_lo_7) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_2 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_7) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_3 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_9) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_9 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_3, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_2) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_3 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_9) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_9) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_9 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_5, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_3) node bpd_csignals_decoded_andMatrixOutputs_hi_9 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_9, bpd_csignals_decoded_andMatrixOutputs_hi_lo_9) node _bpd_csignals_decoded_andMatrixOutputs_T_9 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_9, bpd_csignals_decoded_andMatrixOutputs_lo_9) node bpd_csignals_decoded_andMatrixOutputs_3_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_9) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_10 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_10 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_10 = bits(bpd_csignals_decoded_invInputs, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_10 = bits(bpd_csignals_decoded_plaInput, 3, 3) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_10 = bits(bpd_csignals_decoded_plaInput, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_10 = bits(bpd_csignals_decoded_invInputs, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_10 = bits(bpd_csignals_decoded_plaInput, 12, 12) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_8 = bits(bpd_csignals_decoded_invInputs, 13, 13) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_6 = bits(bpd_csignals_decoded_invInputs, 25, 25) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_5 = bits(bpd_csignals_decoded_invInputs, 26, 26) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_4 = bits(bpd_csignals_decoded_invInputs, 27, 27) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_4 = bits(bpd_csignals_decoded_invInputs, 28, 28) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_4 = bits(bpd_csignals_decoded_invInputs, 29, 29) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_4 = bits(bpd_csignals_decoded_invInputs, 30, 30) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_3 = bits(bpd_csignals_decoded_invInputs, 31, 31) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_4 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_4) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_8 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_3) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_4 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_4) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_5) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_10 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_5, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_4) node bpd_csignals_decoded_andMatrixOutputs_lo_10 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_10, bpd_csignals_decoded_andMatrixOutputs_lo_lo_8) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_3 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_8) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_4 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_10) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_10 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_4, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_3) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_4 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_10) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_10) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_10 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_6, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_4) node bpd_csignals_decoded_andMatrixOutputs_hi_10 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_10, bpd_csignals_decoded_andMatrixOutputs_hi_lo_10) node _bpd_csignals_decoded_andMatrixOutputs_T_10 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_10, bpd_csignals_decoded_andMatrixOutputs_lo_10) node bpd_csignals_decoded_andMatrixOutputs_7_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_10) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_11 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_11 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_11 = bits(bpd_csignals_decoded_invInputs, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_11 = bits(bpd_csignals_decoded_invInputs, 3, 3) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_11 = bits(bpd_csignals_decoded_plaInput, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_11 = bits(bpd_csignals_decoded_invInputs, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_11 = bits(bpd_csignals_decoded_invInputs, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_9 = bits(bpd_csignals_decoded_plaInput, 13, 13) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_9 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_9) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_11 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_11) node bpd_csignals_decoded_andMatrixOutputs_lo_11 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_11, bpd_csignals_decoded_andMatrixOutputs_lo_lo_9) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_11 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_11) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_11 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_11) node bpd_csignals_decoded_andMatrixOutputs_hi_11 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_11, bpd_csignals_decoded_andMatrixOutputs_hi_lo_11) node _bpd_csignals_decoded_andMatrixOutputs_T_11 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_11, bpd_csignals_decoded_andMatrixOutputs_lo_11) node bpd_csignals_decoded_andMatrixOutputs_1_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_11) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_12 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_12 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_12 = bits(bpd_csignals_decoded_invInputs, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_12 = bits(bpd_csignals_decoded_invInputs, 3, 3) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_12 = bits(bpd_csignals_decoded_invInputs, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_12 = bits(bpd_csignals_decoded_plaInput, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_12 = bits(bpd_csignals_decoded_plaInput, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_10 = bits(bpd_csignals_decoded_plaInput, 14, 14) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_10 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_10) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_12 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_12) node bpd_csignals_decoded_andMatrixOutputs_lo_12 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_12, bpd_csignals_decoded_andMatrixOutputs_lo_lo_10) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_12 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_12) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_12 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_12) node bpd_csignals_decoded_andMatrixOutputs_hi_12 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_12, bpd_csignals_decoded_andMatrixOutputs_hi_lo_12) node _bpd_csignals_decoded_andMatrixOutputs_T_12 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_12, bpd_csignals_decoded_andMatrixOutputs_lo_12) node bpd_csignals_decoded_andMatrixOutputs_13_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_12) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_13 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_13 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_13 = bits(bpd_csignals_decoded_invInputs, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_13 = bits(bpd_csignals_decoded_invInputs, 3, 3) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_13 = bits(bpd_csignals_decoded_plaInput, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_13 = bits(bpd_csignals_decoded_invInputs, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_13 = bits(bpd_csignals_decoded_invInputs, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_11 = bits(bpd_csignals_decoded_plaInput, 12, 12) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_7 = bits(bpd_csignals_decoded_invInputs, 13, 13) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_6 = bits(bpd_csignals_decoded_plaInput, 14, 14) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_5 = bits(bpd_csignals_decoded_invInputs, 26, 26) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_5 = bits(bpd_csignals_decoded_invInputs, 27, 27) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_5 = bits(bpd_csignals_decoded_invInputs, 28, 28) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_5 = bits(bpd_csignals_decoded_invInputs, 29, 29) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_4 = bits(bpd_csignals_decoded_invInputs, 31, 31) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_5) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_11 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_4) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_5) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_6) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_13 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_6, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_5) node bpd_csignals_decoded_andMatrixOutputs_lo_13 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_13, bpd_csignals_decoded_andMatrixOutputs_lo_lo_11) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_4 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_11) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_13) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_13 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_5, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_4) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_13) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_7 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_13) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_13 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_7, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_5) node bpd_csignals_decoded_andMatrixOutputs_hi_13 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_13, bpd_csignals_decoded_andMatrixOutputs_hi_lo_13) node _bpd_csignals_decoded_andMatrixOutputs_T_13 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_13, bpd_csignals_decoded_andMatrixOutputs_lo_13) node bpd_csignals_decoded_andMatrixOutputs_4_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_13) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_14 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_14 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_14 = bits(bpd_csignals_decoded_invInputs, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_14 = bits(bpd_csignals_decoded_plaInput, 3, 3) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_14 = bits(bpd_csignals_decoded_plaInput, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_14 = bits(bpd_csignals_decoded_invInputs, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_14 = bits(bpd_csignals_decoded_plaInput, 12, 12) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_12 = bits(bpd_csignals_decoded_invInputs, 13, 13) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_8 = bits(bpd_csignals_decoded_plaInput, 14, 14) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_7 = bits(bpd_csignals_decoded_invInputs, 25, 25) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_6 = bits(bpd_csignals_decoded_invInputs, 26, 26) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_6 = bits(bpd_csignals_decoded_invInputs, 27, 27) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_6 = bits(bpd_csignals_decoded_invInputs, 28, 28) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_6 = bits(bpd_csignals_decoded_invInputs, 29, 29) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_5 = bits(bpd_csignals_decoded_invInputs, 31, 31) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_6) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_12 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_5) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_6) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_7 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_7) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_14 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_7, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_6) node bpd_csignals_decoded_andMatrixOutputs_lo_14 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_14, bpd_csignals_decoded_andMatrixOutputs_lo_lo_12) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_12) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_14) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_14 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_6, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_5) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_14) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_8 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_14) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_14 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_8, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_6) node bpd_csignals_decoded_andMatrixOutputs_hi_14 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_14, bpd_csignals_decoded_andMatrixOutputs_hi_lo_14) node _bpd_csignals_decoded_andMatrixOutputs_T_14 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_14, bpd_csignals_decoded_andMatrixOutputs_lo_14) node bpd_csignals_decoded_andMatrixOutputs_8_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_14) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_15 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_15 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_15 = bits(bpd_csignals_decoded_invInputs, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_15 = bits(bpd_csignals_decoded_plaInput, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_15 = bits(bpd_csignals_decoded_plaInput, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_15 = bits(bpd_csignals_decoded_invInputs, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_15 = bits(bpd_csignals_decoded_plaInput, 12, 12) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_13 = bits(bpd_csignals_decoded_invInputs, 13, 13) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_9 = bits(bpd_csignals_decoded_plaInput, 14, 14) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_8 = bits(bpd_csignals_decoded_invInputs, 25, 25) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_7 = bits(bpd_csignals_decoded_invInputs, 26, 26) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_7 = bits(bpd_csignals_decoded_invInputs, 27, 27) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_7 = bits(bpd_csignals_decoded_invInputs, 28, 28) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_7 = bits(bpd_csignals_decoded_invInputs, 29, 29) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_6 = bits(bpd_csignals_decoded_invInputs, 31, 31) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_7 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_7) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_13 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_6) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_7 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_7) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_8 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_8) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_15 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_8, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_7) node bpd_csignals_decoded_andMatrixOutputs_lo_15 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_15, bpd_csignals_decoded_andMatrixOutputs_lo_lo_13) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_13) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_7 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_15) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_15 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_7, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_6) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_7 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_15) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_9 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_15) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_15 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_9, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_7) node bpd_csignals_decoded_andMatrixOutputs_hi_15 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_15, bpd_csignals_decoded_andMatrixOutputs_hi_lo_15) node _bpd_csignals_decoded_andMatrixOutputs_T_15 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_15, bpd_csignals_decoded_andMatrixOutputs_lo_15) node bpd_csignals_decoded_andMatrixOutputs_10_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_15) node bpd_csignals_decoded_orMatrixOutputs_lo = cat(bpd_csignals_decoded_andMatrixOutputs_2_2, bpd_csignals_decoded_andMatrixOutputs_10_2) node bpd_csignals_decoded_orMatrixOutputs_hi = cat(bpd_csignals_decoded_andMatrixOutputs_14_2, bpd_csignals_decoded_andMatrixOutputs_0_2) node _bpd_csignals_decoded_orMatrixOutputs_T = cat(bpd_csignals_decoded_orMatrixOutputs_hi, bpd_csignals_decoded_orMatrixOutputs_lo) node _bpd_csignals_decoded_orMatrixOutputs_T_1 = orr(_bpd_csignals_decoded_orMatrixOutputs_T) node bpd_csignals_decoded_orMatrixOutputs_lo_lo = cat(bpd_csignals_decoded_andMatrixOutputs_8_2, bpd_csignals_decoded_andMatrixOutputs_10_2) node bpd_csignals_decoded_orMatrixOutputs_lo_hi_hi = cat(bpd_csignals_decoded_andMatrixOutputs_7_2, bpd_csignals_decoded_andMatrixOutputs_1_2) node bpd_csignals_decoded_orMatrixOutputs_lo_hi = cat(bpd_csignals_decoded_orMatrixOutputs_lo_hi_hi, bpd_csignals_decoded_andMatrixOutputs_4_2) node bpd_csignals_decoded_orMatrixOutputs_lo_1 = cat(bpd_csignals_decoded_orMatrixOutputs_lo_hi, bpd_csignals_decoded_orMatrixOutputs_lo_lo) node bpd_csignals_decoded_orMatrixOutputs_hi_lo_hi = cat(bpd_csignals_decoded_andMatrixOutputs_0_2, bpd_csignals_decoded_andMatrixOutputs_12_2) node bpd_csignals_decoded_orMatrixOutputs_hi_lo = cat(bpd_csignals_decoded_orMatrixOutputs_hi_lo_hi, bpd_csignals_decoded_andMatrixOutputs_3_2) node bpd_csignals_decoded_orMatrixOutputs_hi_hi_hi = cat(bpd_csignals_decoded_andMatrixOutputs_5_2, bpd_csignals_decoded_andMatrixOutputs_9_2) node bpd_csignals_decoded_orMatrixOutputs_hi_hi = cat(bpd_csignals_decoded_orMatrixOutputs_hi_hi_hi, bpd_csignals_decoded_andMatrixOutputs_14_2) node bpd_csignals_decoded_orMatrixOutputs_hi_1 = cat(bpd_csignals_decoded_orMatrixOutputs_hi_hi, bpd_csignals_decoded_orMatrixOutputs_hi_lo) node _bpd_csignals_decoded_orMatrixOutputs_T_2 = cat(bpd_csignals_decoded_orMatrixOutputs_hi_1, bpd_csignals_decoded_orMatrixOutputs_lo_1) node _bpd_csignals_decoded_orMatrixOutputs_T_3 = orr(_bpd_csignals_decoded_orMatrixOutputs_T_2) node _bpd_csignals_decoded_orMatrixOutputs_T_4 = orr(bpd_csignals_decoded_andMatrixOutputs_15_2) node _bpd_csignals_decoded_orMatrixOutputs_T_5 = orr(bpd_csignals_decoded_andMatrixOutputs_11_2) node _bpd_csignals_decoded_orMatrixOutputs_T_6 = cat(bpd_csignals_decoded_andMatrixOutputs_6_2, bpd_csignals_decoded_andMatrixOutputs_13_2) node _bpd_csignals_decoded_orMatrixOutputs_T_7 = orr(_bpd_csignals_decoded_orMatrixOutputs_T_6) node bpd_csignals_decoded_orMatrixOutputs_lo_2 = cat(_bpd_csignals_decoded_orMatrixOutputs_T_3, _bpd_csignals_decoded_orMatrixOutputs_T_1) node bpd_csignals_decoded_orMatrixOutputs_hi_hi_1 = cat(_bpd_csignals_decoded_orMatrixOutputs_T_7, _bpd_csignals_decoded_orMatrixOutputs_T_5) node bpd_csignals_decoded_orMatrixOutputs_hi_2 = cat(bpd_csignals_decoded_orMatrixOutputs_hi_hi_1, _bpd_csignals_decoded_orMatrixOutputs_T_4) node bpd_csignals_decoded_orMatrixOutputs = cat(bpd_csignals_decoded_orMatrixOutputs_hi_2, bpd_csignals_decoded_orMatrixOutputs_lo_2) node _bpd_csignals_decoded_invMatrixOutputs_T = bits(bpd_csignals_decoded_orMatrixOutputs, 0, 0) node _bpd_csignals_decoded_invMatrixOutputs_T_1 = bits(bpd_csignals_decoded_orMatrixOutputs, 1, 1) node _bpd_csignals_decoded_invMatrixOutputs_T_2 = bits(bpd_csignals_decoded_orMatrixOutputs, 2, 2) node _bpd_csignals_decoded_invMatrixOutputs_T_3 = bits(bpd_csignals_decoded_orMatrixOutputs, 3, 3) node _bpd_csignals_decoded_invMatrixOutputs_T_4 = bits(bpd_csignals_decoded_orMatrixOutputs, 4, 4) node bpd_csignals_decoded_invMatrixOutputs_lo = cat(_bpd_csignals_decoded_invMatrixOutputs_T_1, _bpd_csignals_decoded_invMatrixOutputs_T) node bpd_csignals_decoded_invMatrixOutputs_hi_hi = cat(_bpd_csignals_decoded_invMatrixOutputs_T_4, _bpd_csignals_decoded_invMatrixOutputs_T_3) node bpd_csignals_decoded_invMatrixOutputs_hi = cat(bpd_csignals_decoded_invMatrixOutputs_hi_hi, _bpd_csignals_decoded_invMatrixOutputs_T_2) node bpd_csignals_decoded_invMatrixOutputs = cat(bpd_csignals_decoded_invMatrixOutputs_hi, bpd_csignals_decoded_invMatrixOutputs_lo) connect bpd_csignals_decoded, bpd_csignals_decoded_invMatrixOutputs connect bpd_csignals_decoded_plaInput, io.inst node bpd_csignals_0 = bits(bpd_csignals_decoded, 4, 4) node bpd_csignals_1 = bits(bpd_csignals_decoded, 3, 3) node bpd_csignals_2 = bits(bpd_csignals_decoded, 2, 2) node bpd_csignals_3 = bits(bpd_csignals_decoded, 1, 1) node bpd_csignals_4 = bits(bpd_csignals_decoded, 0, 0) node cs_is_br = bits(bpd_csignals_0, 0, 0) node cs_is_jal = bits(bpd_csignals_1, 0, 0) node cs_is_jalr = bits(bpd_csignals_2, 0, 0) node cs_is_shadowable = bits(bpd_csignals_3, 0, 0) node cs_has_rs2 = bits(bpd_csignals_4, 0, 0) node _io_out_is_call_T = or(cs_is_jal, cs_is_jalr) node _io_out_is_call_T_1 = bits(io.inst, 11, 7) node _io_out_is_call_T_2 = eq(_io_out_is_call_T_1, UInt<1>(0h1)) node _io_out_is_call_T_3 = and(_io_out_is_call_T, _io_out_is_call_T_2) connect io.out.is_call, _io_out_is_call_T_3 node _io_out_is_ret_T = bits(io.inst, 19, 15) node _io_out_is_ret_T_1 = and(_io_out_is_ret_T, UInt<5>(0h1b)) node _io_out_is_ret_T_2 = eq(UInt<1>(0h1), _io_out_is_ret_T_1) node _io_out_is_ret_T_3 = and(cs_is_jalr, _io_out_is_ret_T_2) node _io_out_is_ret_T_4 = bits(io.inst, 11, 7) node _io_out_is_ret_T_5 = eq(_io_out_is_ret_T_4, UInt<1>(0h0)) node _io_out_is_ret_T_6 = and(_io_out_is_ret_T_3, _io_out_is_ret_T_5) connect io.out.is_ret, _io_out_is_ret_T_6 node _io_out_target_b_imm32_T = bits(io.inst, 31, 31) node _io_out_target_b_imm32_T_1 = mux(_io_out_target_b_imm32_T, UInt<20>(0hfffff), UInt<20>(0h0)) node _io_out_target_b_imm32_T_2 = bits(io.inst, 7, 7) node _io_out_target_b_imm32_T_3 = bits(io.inst, 30, 25) node _io_out_target_b_imm32_T_4 = bits(io.inst, 11, 8) node io_out_target_b_imm32_lo = cat(_io_out_target_b_imm32_T_4, UInt<1>(0h0)) node io_out_target_b_imm32_hi_hi = cat(_io_out_target_b_imm32_T_1, _io_out_target_b_imm32_T_2) node io_out_target_b_imm32_hi = cat(io_out_target_b_imm32_hi_hi, _io_out_target_b_imm32_T_3) node io_out_target_b_imm32 = cat(io_out_target_b_imm32_hi, io_out_target_b_imm32_lo) node _io_out_target_T = asSInt(io.pc) node _io_out_target_T_1 = asSInt(io_out_target_b_imm32) node _io_out_target_T_2 = add(_io_out_target_T, _io_out_target_T_1) node _io_out_target_T_3 = tail(_io_out_target_T_2, 1) node _io_out_target_T_4 = asSInt(_io_out_target_T_3) node _io_out_target_T_5 = and(_io_out_target_T_4, asSInt(UInt<2>(0h2))) node _io_out_target_T_6 = asSInt(_io_out_target_T_5) node _io_out_target_T_7 = asUInt(_io_out_target_T_6) node _io_out_target_j_imm32_T = bits(io.inst, 31, 31) node _io_out_target_j_imm32_T_1 = mux(_io_out_target_j_imm32_T, UInt<12>(0hfff), UInt<12>(0h0)) node _io_out_target_j_imm32_T_2 = bits(io.inst, 19, 12) node _io_out_target_j_imm32_T_3 = bits(io.inst, 20, 20) node _io_out_target_j_imm32_T_4 = bits(io.inst, 30, 25) node _io_out_target_j_imm32_T_5 = bits(io.inst, 24, 21) node io_out_target_j_imm32_lo_hi = cat(_io_out_target_j_imm32_T_4, _io_out_target_j_imm32_T_5) node io_out_target_j_imm32_lo = cat(io_out_target_j_imm32_lo_hi, UInt<1>(0h0)) node io_out_target_j_imm32_hi_hi = cat(_io_out_target_j_imm32_T_1, _io_out_target_j_imm32_T_2) node io_out_target_j_imm32_hi = cat(io_out_target_j_imm32_hi_hi, _io_out_target_j_imm32_T_3) node io_out_target_j_imm32 = cat(io_out_target_j_imm32_hi, io_out_target_j_imm32_lo) node _io_out_target_T_8 = asSInt(io.pc) node _io_out_target_T_9 = asSInt(io_out_target_j_imm32) node _io_out_target_T_10 = add(_io_out_target_T_8, _io_out_target_T_9) node _io_out_target_T_11 = tail(_io_out_target_T_10, 1) node _io_out_target_T_12 = asSInt(_io_out_target_T_11) node _io_out_target_T_13 = and(_io_out_target_T_12, asSInt(UInt<2>(0h2))) node _io_out_target_T_14 = asSInt(_io_out_target_T_13) node _io_out_target_T_15 = asUInt(_io_out_target_T_14) node _io_out_target_T_16 = mux(cs_is_br, _io_out_target_T_7, _io_out_target_T_15) connect io.out.target, _io_out_target_T_16 node _io_out_cfi_type_T = mux(cs_is_br, UInt<3>(0h1), UInt<3>(0h0)) node _io_out_cfi_type_T_1 = mux(cs_is_jal, UInt<3>(0h2), _io_out_cfi_type_T) node _io_out_cfi_type_T_2 = mux(cs_is_jalr, UInt<3>(0h3), _io_out_cfi_type_T_1) connect io.out.cfi_type, _io_out_cfi_type_T_2 node _br_offset_T = bits(io.inst, 7, 7) node _br_offset_T_1 = bits(io.inst, 30, 25) node _br_offset_T_2 = bits(io.inst, 11, 8) node br_offset_lo = cat(_br_offset_T_2, UInt<1>(0h0)) node br_offset_hi = cat(_br_offset_T, _br_offset_T_1) node br_offset = cat(br_offset_hi, br_offset_lo) node _io_out_sfb_offset_valid_T = bits(io.inst, 31, 31) node _io_out_sfb_offset_valid_T_1 = eq(_io_out_sfb_offset_valid_T, UInt<1>(0h0)) node _io_out_sfb_offset_valid_T_2 = and(cs_is_br, _io_out_sfb_offset_valid_T_1) node _io_out_sfb_offset_valid_T_3 = neq(br_offset, UInt<1>(0h0)) node _io_out_sfb_offset_valid_T_4 = and(_io_out_sfb_offset_valid_T_2, _io_out_sfb_offset_valid_T_3) node _io_out_sfb_offset_valid_T_5 = shr(br_offset, 6) node _io_out_sfb_offset_valid_T_6 = eq(_io_out_sfb_offset_valid_T_5, UInt<1>(0h0)) node _io_out_sfb_offset_valid_T_7 = and(_io_out_sfb_offset_valid_T_4, _io_out_sfb_offset_valid_T_6) connect io.out.sfb_offset.valid, _io_out_sfb_offset_valid_T_7 connect io.out.sfb_offset.bits, br_offset node _io_out_shadowable_T = eq(cs_has_rs2, UInt<1>(0h0)) node _io_out_shadowable_T_1 = bits(io.inst, 19, 15) node _io_out_shadowable_T_2 = bits(io.inst, 11, 7) node _io_out_shadowable_T_3 = eq(_io_out_shadowable_T_1, _io_out_shadowable_T_2) node _io_out_shadowable_T_4 = or(_io_out_shadowable_T, _io_out_shadowable_T_3) node _io_out_shadowable_T_5 = and(io.inst, UInt<32>(0hfe00707f)) node _io_out_shadowable_T_6 = eq(UInt<6>(0h33), _io_out_shadowable_T_5) node _io_out_shadowable_T_7 = bits(io.inst, 19, 15) node _io_out_shadowable_T_8 = eq(_io_out_shadowable_T_7, UInt<1>(0h0)) node _io_out_shadowable_T_9 = and(_io_out_shadowable_T_6, _io_out_shadowable_T_8) node _io_out_shadowable_T_10 = or(_io_out_shadowable_T_4, _io_out_shadowable_T_9) node _io_out_shadowable_T_11 = and(cs_is_shadowable, _io_out_shadowable_T_10) connect io.out.shadowable, _io_out_shadowable_T_11
module BranchDecode_5( // @[decode.scala:629:7] input clock, // @[decode.scala:629:7] input reset, // @[decode.scala:629:7] input [31:0] io_inst, // @[decode.scala:631:14] input [39:0] io_pc, // @[decode.scala:631:14] output io_out_is_ret, // @[decode.scala:631:14] output io_out_is_call, // @[decode.scala:631:14] output [39:0] io_out_target, // @[decode.scala:631:14] output [2:0] io_out_cfi_type, // @[decode.scala:631:14] output io_out_sfb_offset_valid, // @[decode.scala:631:14] output [5:0] io_out_sfb_offset_bits, // @[decode.scala:631:14] output io_out_shadowable // @[decode.scala:631:14] ); wire [31:0] io_inst_0 = io_inst; // @[decode.scala:629:7] wire [39:0] io_pc_0 = io_pc; // @[decode.scala:629:7] wire [31:0] bpd_csignals_decoded_plaInput = io_inst_0; // @[pla.scala:77:22] wire _io_out_is_ret_T_6; // @[decode.scala:701:72] wire [39:0] _io_out_target_T = io_pc_0; // @[decode.scala:629:7] wire [39:0] _io_out_target_T_8 = io_pc_0; // @[decode.scala:629:7] wire _io_out_is_call_T_3; // @[decode.scala:700:47] wire [39:0] _io_out_target_T_16; // @[decode.scala:703:23] wire [2:0] _io_out_cfi_type_T_2; // @[decode.scala:706:8] wire _io_out_sfb_offset_valid_T_7; // @[decode.scala:716:76] wire _io_out_shadowable_T_11; // @[decode.scala:718:41] wire io_out_sfb_offset_valid_0; // @[decode.scala:629:7] wire [5:0] io_out_sfb_offset_bits_0; // @[decode.scala:629:7] wire io_out_is_ret_0; // @[decode.scala:629:7] wire io_out_is_call_0; // @[decode.scala:629:7] wire [39:0] io_out_target_0; // @[decode.scala:629:7] wire [2:0] io_out_cfi_type_0; // @[decode.scala:629:7] wire io_out_shadowable_0; // @[decode.scala:629:7] wire [31:0] bpd_csignals_decoded_invInputs = ~bpd_csignals_decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [4:0] bpd_csignals_decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [4:0] bpd_csignals_decoded; // @[pla.scala:81:23] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_1 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_2 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_3 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_4 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_5 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_6 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_7 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_8 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_9 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_10 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_11 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_12 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_13 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_14 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_15 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_1 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_2 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_3 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_4 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_5 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_6 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_7 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_8 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_9 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_10 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_11 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_12 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_13 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_14 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_15 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_1 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_2 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_3 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_4 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_6 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_9 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_10 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_11 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_12 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_13 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_14 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_15 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_3 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_5 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_6 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_7 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_9 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_11 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_12 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_13 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_1 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_2 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_3 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_4 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_5 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_9 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_10 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_11 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_13 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_14 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_15 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5 = bpd_csignals_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_1 = bpd_csignals_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_9 = bpd_csignals_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_11 = bpd_csignals_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_13 = bpd_csignals_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_1 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_2 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_3 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_4 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_5 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_9 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_10 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_11 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_13 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_14 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_15 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7 = bpd_csignals_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_1 = bpd_csignals_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_2 = bpd_csignals_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_6 = bpd_csignals_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo = {bpd_csignals_decoded_andMatrixOutputs_lo_hi, bpd_csignals_decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi = {bpd_csignals_decoded_andMatrixOutputs_hi_hi, bpd_csignals_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [7:0] _bpd_csignals_decoded_andMatrixOutputs_T = {bpd_csignals_decoded_andMatrixOutputs_hi, bpd_csignals_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_5_2 = &_bpd_csignals_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_1 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_2 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_4 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_5 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_4 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_5 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_8 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_7 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_12 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_13 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8 = bpd_csignals_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_1 = bpd_csignals_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_4 = bpd_csignals_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_3 = bpd_csignals_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_1}; // @[pla.scala:91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_1, bpd_csignals_decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_1}; // @[pla.scala:91:29, :98:53] wire [4:0] bpd_csignals_decoded_andMatrixOutputs_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_1, bpd_csignals_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53] wire [8:0] _bpd_csignals_decoded_andMatrixOutputs_T_1 = {bpd_csignals_decoded_andMatrixOutputs_hi_1, bpd_csignals_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_9_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_2 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_3 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_4 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_5 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_6 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_7 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_8 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_12 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_15 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_3 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_3 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_6 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_7 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_8 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_2 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_2 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_4 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_5 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_5 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_6 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_7 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_1 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_2 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_3 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_4 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_5 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_6 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_7 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_1 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_2 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_3 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_4 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_5 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_6 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_7 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_1 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_2 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_3 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_4 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_5 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_6 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_7 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_1 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_1 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_2 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_3 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_4 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_5 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_6 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9}; // @[pla.scala:91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_2, bpd_csignals_decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_2}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_1, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo}; // @[pla.scala:98:53] wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_2, bpd_csignals_decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53] wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_2 = {bpd_csignals_decoded_andMatrixOutputs_hi_2, bpd_csignals_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_14_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_1 = bpd_csignals_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_2 = bpd_csignals_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_3 = bpd_csignals_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_4 = bpd_csignals_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_1}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_1}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_1}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_2}; // @[pla.scala:91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_1, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_3, bpd_csignals_decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_3}; // @[pla.scala:90:45, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_3}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_2, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_3, bpd_csignals_decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53] wire [13:0] _bpd_csignals_decoded_andMatrixOutputs_T_3 = {bpd_csignals_decoded_andMatrixOutputs_hi_3, bpd_csignals_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_0_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_2}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_1}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_2}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_2}; // @[pla.scala:91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_2, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_4, bpd_csignals_decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_4}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_2, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_3, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:98:53] wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_4, bpd_csignals_decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53] wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_4 = {bpd_csignals_decoded_andMatrixOutputs_hi_4, bpd_csignals_decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_2_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_5 = bpd_csignals_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_7 = bpd_csignals_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_8 = bpd_csignals_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_5}; // @[pla.scala:90:45, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_5}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_5, bpd_csignals_decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53] wire [6:0] _bpd_csignals_decoded_andMatrixOutputs_T_5 = {bpd_csignals_decoded_andMatrixOutputs_hi_5, bpd_csignals_decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_12_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_6 = bpd_csignals_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_7 = bpd_csignals_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_8 = bpd_csignals_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_12 = bpd_csignals_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_6 = bpd_csignals_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_7 = bpd_csignals_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_8 = bpd_csignals_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_12 = bpd_csignals_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_6, bpd_csignals_decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_6}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_6, bpd_csignals_decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53] wire [7:0] _bpd_csignals_decoded_andMatrixOutputs_T_6 = {bpd_csignals_decoded_andMatrixOutputs_hi_6, bpd_csignals_decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_6_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_3}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_7}; // @[pla.scala:90:45, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_6}; // @[pla.scala:91:29, :98:53] wire [4:0] bpd_csignals_decoded_andMatrixOutputs_lo_7 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_7, bpd_csignals_decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:90:45, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:90:45, :98:53] wire [4:0] bpd_csignals_decoded_andMatrixOutputs_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_7, bpd_csignals_decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53] wire [9:0] _bpd_csignals_decoded_andMatrixOutputs_T_7 = {bpd_csignals_decoded_andMatrixOutputs_hi_7, bpd_csignals_decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_15_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}] wire _bpd_csignals_decoded_orMatrixOutputs_T_4 = bpd_csignals_decoded_andMatrixOutputs_15_2; // @[pla.scala:98:70, :114:36] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_8 = bpd_csignals_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_10 = bpd_csignals_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_14 = bpd_csignals_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_8 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_8 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_8}; // @[pla.scala:90:45, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_8 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_8}; // @[pla.scala:90:45, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_8 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_8 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_8, bpd_csignals_decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53] wire [6:0] _bpd_csignals_decoded_andMatrixOutputs_T_8 = {bpd_csignals_decoded_andMatrixOutputs_hi_8, bpd_csignals_decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_11_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}] wire _bpd_csignals_decoded_orMatrixOutputs_T_5 = bpd_csignals_decoded_andMatrixOutputs_11_2; // @[pla.scala:98:70, :114:36] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_7 = bpd_csignals_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_10 = bpd_csignals_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_11 = bpd_csignals_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_14 = bpd_csignals_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_15 = bpd_csignals_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_3}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_7 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_2}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_3}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_4}; // @[pla.scala:91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_9 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_4, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_9 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_9, bpd_csignals_decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_9 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_3, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_9}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_9 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_5, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_9 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_9, bpd_csignals_decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53] wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_9 = {bpd_csignals_decoded_andMatrixOutputs_hi_9, bpd_csignals_decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_3_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_4}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_8 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_3}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_4}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_5}; // @[pla.scala:91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_10 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_5, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_10 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_10, bpd_csignals_decoded_andMatrixOutputs_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_10 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_4, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_10 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_6, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_4}; // @[pla.scala:98:53] wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_10 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_10, bpd_csignals_decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53] wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_10 = {bpd_csignals_decoded_andMatrixOutputs_hi_10, bpd_csignals_decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_7_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_9 = bpd_csignals_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_9 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_11 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_11 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_11, bpd_csignals_decoded_andMatrixOutputs_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_11 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_11}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_11 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_11 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_11, bpd_csignals_decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53] wire [7:0] _bpd_csignals_decoded_andMatrixOutputs_T_11 = {bpd_csignals_decoded_andMatrixOutputs_hi_11, bpd_csignals_decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_1_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_10 = bpd_csignals_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_6 = bpd_csignals_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_8 = bpd_csignals_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_9 = bpd_csignals_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_10 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_10}; // @[pla.scala:90:45, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_12 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_12 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_12, bpd_csignals_decoded_andMatrixOutputs_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_12 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_12}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_12 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_12 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_12, bpd_csignals_decoded_andMatrixOutputs_hi_lo_12}; // @[pla.scala:98:53] wire [7:0] _bpd_csignals_decoded_andMatrixOutputs_T_12 = {bpd_csignals_decoded_andMatrixOutputs_hi_12, bpd_csignals_decoded_andMatrixOutputs_lo_12}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_13_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_5}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_11 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_4}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_5}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_13 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_6, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_5}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_13 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_13, bpd_csignals_decoded_andMatrixOutputs_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_13 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_5, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_13}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_13 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_7, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_13 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_13, bpd_csignals_decoded_andMatrixOutputs_hi_lo_13}; // @[pla.scala:98:53] wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_13 = {bpd_csignals_decoded_andMatrixOutputs_hi_13, bpd_csignals_decoded_andMatrixOutputs_lo_13}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_4_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_6}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_12 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_5}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_6}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_14 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_7, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_14 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_14, bpd_csignals_decoded_andMatrixOutputs_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_14 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_6, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_8 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_14}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_14 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_8, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_6}; // @[pla.scala:98:53] wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_14 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_14, bpd_csignals_decoded_andMatrixOutputs_hi_lo_14}; // @[pla.scala:98:53] wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_14 = {bpd_csignals_decoded_andMatrixOutputs_hi_14, bpd_csignals_decoded_andMatrixOutputs_lo_14}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_8_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_14; // @[pla.scala:98:{53,70}] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_7}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_13 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_6}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_7}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_8 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_15 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_8, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_7}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_15 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_15, bpd_csignals_decoded_andMatrixOutputs_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_15 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_7, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_9 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_15}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_15 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_9, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_15 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_15, bpd_csignals_decoded_andMatrixOutputs_hi_lo_15}; // @[pla.scala:98:53] wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_15 = {bpd_csignals_decoded_andMatrixOutputs_hi_15, bpd_csignals_decoded_andMatrixOutputs_lo_15}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_10_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_15; // @[pla.scala:98:{53,70}] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_lo = {bpd_csignals_decoded_andMatrixOutputs_2_2, bpd_csignals_decoded_andMatrixOutputs_10_2}; // @[pla.scala:98:70, :114:19] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_hi = {bpd_csignals_decoded_andMatrixOutputs_14_2, bpd_csignals_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19] wire [3:0] _bpd_csignals_decoded_orMatrixOutputs_T = {bpd_csignals_decoded_orMatrixOutputs_hi, bpd_csignals_decoded_orMatrixOutputs_lo}; // @[pla.scala:114:19] wire _bpd_csignals_decoded_orMatrixOutputs_T_1 = |_bpd_csignals_decoded_orMatrixOutputs_T; // @[pla.scala:114:{19,36}] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_lo_lo = {bpd_csignals_decoded_andMatrixOutputs_8_2, bpd_csignals_decoded_andMatrixOutputs_10_2}; // @[pla.scala:98:70, :114:19] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_lo_hi_hi = {bpd_csignals_decoded_andMatrixOutputs_7_2, bpd_csignals_decoded_andMatrixOutputs_1_2}; // @[pla.scala:98:70, :114:19] wire [2:0] bpd_csignals_decoded_orMatrixOutputs_lo_hi = {bpd_csignals_decoded_orMatrixOutputs_lo_hi_hi, bpd_csignals_decoded_andMatrixOutputs_4_2}; // @[pla.scala:98:70, :114:19] wire [4:0] bpd_csignals_decoded_orMatrixOutputs_lo_1 = {bpd_csignals_decoded_orMatrixOutputs_lo_hi, bpd_csignals_decoded_orMatrixOutputs_lo_lo}; // @[pla.scala:114:19] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_hi_lo_hi = {bpd_csignals_decoded_andMatrixOutputs_0_2, bpd_csignals_decoded_andMatrixOutputs_12_2}; // @[pla.scala:98:70, :114:19] wire [2:0] bpd_csignals_decoded_orMatrixOutputs_hi_lo = {bpd_csignals_decoded_orMatrixOutputs_hi_lo_hi, bpd_csignals_decoded_andMatrixOutputs_3_2}; // @[pla.scala:98:70, :114:19] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_hi_hi_hi = {bpd_csignals_decoded_andMatrixOutputs_5_2, bpd_csignals_decoded_andMatrixOutputs_9_2}; // @[pla.scala:98:70, :114:19] wire [2:0] bpd_csignals_decoded_orMatrixOutputs_hi_hi = {bpd_csignals_decoded_orMatrixOutputs_hi_hi_hi, bpd_csignals_decoded_andMatrixOutputs_14_2}; // @[pla.scala:98:70, :114:19] wire [5:0] bpd_csignals_decoded_orMatrixOutputs_hi_1 = {bpd_csignals_decoded_orMatrixOutputs_hi_hi, bpd_csignals_decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:114:19] wire [10:0] _bpd_csignals_decoded_orMatrixOutputs_T_2 = {bpd_csignals_decoded_orMatrixOutputs_hi_1, bpd_csignals_decoded_orMatrixOutputs_lo_1}; // @[pla.scala:114:19] wire _bpd_csignals_decoded_orMatrixOutputs_T_3 = |_bpd_csignals_decoded_orMatrixOutputs_T_2; // @[pla.scala:114:{19,36}] wire [1:0] _bpd_csignals_decoded_orMatrixOutputs_T_6 = {bpd_csignals_decoded_andMatrixOutputs_6_2, bpd_csignals_decoded_andMatrixOutputs_13_2}; // @[pla.scala:98:70, :114:19] wire _bpd_csignals_decoded_orMatrixOutputs_T_7 = |_bpd_csignals_decoded_orMatrixOutputs_T_6; // @[pla.scala:114:{19,36}] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_lo_2 = {_bpd_csignals_decoded_orMatrixOutputs_T_3, _bpd_csignals_decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_hi_hi_1 = {_bpd_csignals_decoded_orMatrixOutputs_T_7, _bpd_csignals_decoded_orMatrixOutputs_T_5}; // @[pla.scala:102:36, :114:36] wire [2:0] bpd_csignals_decoded_orMatrixOutputs_hi_2 = {bpd_csignals_decoded_orMatrixOutputs_hi_hi_1, _bpd_csignals_decoded_orMatrixOutputs_T_4}; // @[pla.scala:102:36, :114:36] wire [4:0] bpd_csignals_decoded_orMatrixOutputs = {bpd_csignals_decoded_orMatrixOutputs_hi_2, bpd_csignals_decoded_orMatrixOutputs_lo_2}; // @[pla.scala:102:36] wire _bpd_csignals_decoded_invMatrixOutputs_T = bpd_csignals_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _bpd_csignals_decoded_invMatrixOutputs_T_1 = bpd_csignals_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _bpd_csignals_decoded_invMatrixOutputs_T_2 = bpd_csignals_decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _bpd_csignals_decoded_invMatrixOutputs_T_3 = bpd_csignals_decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire _bpd_csignals_decoded_invMatrixOutputs_T_4 = bpd_csignals_decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31] wire [1:0] bpd_csignals_decoded_invMatrixOutputs_lo = {_bpd_csignals_decoded_invMatrixOutputs_T_1, _bpd_csignals_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] bpd_csignals_decoded_invMatrixOutputs_hi_hi = {_bpd_csignals_decoded_invMatrixOutputs_T_4, _bpd_csignals_decoded_invMatrixOutputs_T_3}; // @[pla.scala:120:37, :124:31] wire [2:0] bpd_csignals_decoded_invMatrixOutputs_hi = {bpd_csignals_decoded_invMatrixOutputs_hi_hi, _bpd_csignals_decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31] assign bpd_csignals_decoded_invMatrixOutputs = {bpd_csignals_decoded_invMatrixOutputs_hi, bpd_csignals_decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign bpd_csignals_decoded = bpd_csignals_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] wire bpd_csignals_0 = bpd_csignals_decoded[4]; // @[pla.scala:81:23] wire cs_is_br = bpd_csignals_0; // @[Decode.scala:50:77] wire bpd_csignals_1 = bpd_csignals_decoded[3]; // @[pla.scala:81:23] wire cs_is_jal = bpd_csignals_1; // @[Decode.scala:50:77] wire bpd_csignals_2 = bpd_csignals_decoded[2]; // @[pla.scala:81:23] wire cs_is_jalr = bpd_csignals_2; // @[Decode.scala:50:77] wire bpd_csignals_3 = bpd_csignals_decoded[1]; // @[pla.scala:81:23] wire cs_is_shadowable = bpd_csignals_3; // @[Decode.scala:50:77] wire bpd_csignals_4 = bpd_csignals_decoded[0]; // @[pla.scala:81:23] wire cs_has_rs2 = bpd_csignals_4; // @[Decode.scala:50:77] wire _io_out_is_call_T = cs_is_jal | cs_is_jalr; // @[decode.scala:695:34, :696:35, :700:32] wire [4:0] _io_out_is_call_T_1 = io_inst_0[11:7]; // @[decode.scala:629:7] wire [4:0] _io_out_is_ret_T_4 = io_inst_0[11:7]; // @[decode.scala:629:7] wire [4:0] _io_out_shadowable_T_2 = io_inst_0[11:7]; // @[decode.scala:629:7] wire _io_out_is_call_T_2 = _io_out_is_call_T_1 == 5'h1; // @[decode.scala:700:65] assign _io_out_is_call_T_3 = _io_out_is_call_T & _io_out_is_call_T_2; // @[decode.scala:700:{32,47,65}] assign io_out_is_call_0 = _io_out_is_call_T_3; // @[decode.scala:629:7, :700:47] wire [4:0] _io_out_is_ret_T = io_inst_0[19:15]; // @[decode.scala:629:7] wire [4:0] _io_out_shadowable_T_1 = io_inst_0[19:15]; // @[decode.scala:629:7] wire [4:0] _io_out_shadowable_T_7 = io_inst_0[19:15]; // @[decode.scala:629:7] wire [4:0] _io_out_is_ret_T_1 = _io_out_is_ret_T & 5'h1B; // @[decode.scala:701:51] wire _io_out_is_ret_T_2 = _io_out_is_ret_T_1 == 5'h1; // @[decode.scala:701:51] wire _io_out_is_ret_T_3 = cs_is_jalr & _io_out_is_ret_T_2; // @[decode.scala:696:35, :701:{32,51}] wire _io_out_is_ret_T_5 = _io_out_is_ret_T_4 == 5'h0; // @[decode.scala:701:90] assign _io_out_is_ret_T_6 = _io_out_is_ret_T_3 & _io_out_is_ret_T_5; // @[decode.scala:701:{32,72,90}] assign io_out_is_ret_0 = _io_out_is_ret_T_6; // @[decode.scala:629:7, :701:72] wire _io_out_target_b_imm32_T = io_inst_0[31]; // @[decode.scala:629:7] wire _io_out_target_j_imm32_T = io_inst_0[31]; // @[decode.scala:629:7] wire _io_out_sfb_offset_valid_T = io_inst_0[31]; // @[decode.scala:629:7, :716:50] wire [19:0] _io_out_target_b_imm32_T_1 = {20{_io_out_target_b_imm32_T}}; // @[consts.scala:189:{27,35}] wire _io_out_target_b_imm32_T_2 = io_inst_0[7]; // @[decode.scala:629:7] wire _br_offset_T = io_inst_0[7]; // @[decode.scala:629:7, :714:30] wire [5:0] _io_out_target_b_imm32_T_3 = io_inst_0[30:25]; // @[decode.scala:629:7] wire [5:0] _io_out_target_j_imm32_T_4 = io_inst_0[30:25]; // @[decode.scala:629:7] wire [5:0] _br_offset_T_1 = io_inst_0[30:25]; // @[decode.scala:629:7, :714:42] wire [3:0] _io_out_target_b_imm32_T_4 = io_inst_0[11:8]; // @[decode.scala:629:7] wire [3:0] _br_offset_T_2 = io_inst_0[11:8]; // @[decode.scala:629:7, :714:58] wire [4:0] io_out_target_b_imm32_lo = {_io_out_target_b_imm32_T_4, 1'h0}; // @[consts.scala:189:{22,68}] wire [20:0] io_out_target_b_imm32_hi_hi = {_io_out_target_b_imm32_T_1, _io_out_target_b_imm32_T_2}; // @[consts.scala:189:{22,27,46}] wire [26:0] io_out_target_b_imm32_hi = {io_out_target_b_imm32_hi_hi, _io_out_target_b_imm32_T_3}; // @[consts.scala:189:{22,55}] wire [31:0] io_out_target_b_imm32 = {io_out_target_b_imm32_hi, io_out_target_b_imm32_lo}; // @[consts.scala:189:22] wire [31:0] _io_out_target_T_1 = io_out_target_b_imm32; // @[consts.scala:189:22, :190:27] wire [40:0] _io_out_target_T_2 = {_io_out_target_T[39], _io_out_target_T} + {{9{_io_out_target_T_1[31]}}, _io_out_target_T_1}; // @[consts.scala:190:{10,17,27}] wire [39:0] _io_out_target_T_3 = _io_out_target_T_2[39:0]; // @[consts.scala:190:17] wire [39:0] _io_out_target_T_4 = _io_out_target_T_3; // @[consts.scala:190:17] wire [39:0] _io_out_target_T_5 = _io_out_target_T_4 & 40'hFFFFFFFFFE; // @[consts.scala:190:{17,42}] wire [39:0] _io_out_target_T_6 = _io_out_target_T_5; // @[consts.scala:190:42] wire [39:0] _io_out_target_T_7 = _io_out_target_T_6; // @[consts.scala:190:{42,52}] wire [11:0] _io_out_target_j_imm32_T_1 = {12{_io_out_target_j_imm32_T}}; // @[consts.scala:195:{27,35}] wire [7:0] _io_out_target_j_imm32_T_2 = io_inst_0[19:12]; // @[decode.scala:629:7] wire _io_out_target_j_imm32_T_3 = io_inst_0[20]; // @[decode.scala:629:7] wire [3:0] _io_out_target_j_imm32_T_5 = io_inst_0[24:21]; // @[decode.scala:629:7] wire [9:0] io_out_target_j_imm32_lo_hi = {_io_out_target_j_imm32_T_4, _io_out_target_j_imm32_T_5}; // @[consts.scala:195:{22,69,82}] wire [10:0] io_out_target_j_imm32_lo = {io_out_target_j_imm32_lo_hi, 1'h0}; // @[consts.scala:195:22] wire [19:0] io_out_target_j_imm32_hi_hi = {_io_out_target_j_imm32_T_1, _io_out_target_j_imm32_T_2}; // @[consts.scala:195:{22,27,46}] wire [20:0] io_out_target_j_imm32_hi = {io_out_target_j_imm32_hi_hi, _io_out_target_j_imm32_T_3}; // @[consts.scala:195:{22,59}] wire [31:0] io_out_target_j_imm32 = {io_out_target_j_imm32_hi, io_out_target_j_imm32_lo}; // @[consts.scala:195:22] wire [31:0] _io_out_target_T_9 = io_out_target_j_imm32; // @[consts.scala:195:22, :196:27] wire [40:0] _io_out_target_T_10 = {_io_out_target_T_8[39], _io_out_target_T_8} + {{9{_io_out_target_T_9[31]}}, _io_out_target_T_9}; // @[consts.scala:196:{10,17,27}] wire [39:0] _io_out_target_T_11 = _io_out_target_T_10[39:0]; // @[consts.scala:196:17] wire [39:0] _io_out_target_T_12 = _io_out_target_T_11; // @[consts.scala:196:17] wire [39:0] _io_out_target_T_13 = _io_out_target_T_12 & 40'hFFFFFFFFFE; // @[consts.scala:196:{17,42}] wire [39:0] _io_out_target_T_14 = _io_out_target_T_13; // @[consts.scala:196:42] wire [39:0] _io_out_target_T_15 = _io_out_target_T_14; // @[consts.scala:196:{42,52}] assign _io_out_target_T_16 = cs_is_br ? _io_out_target_T_7 : _io_out_target_T_15; // @[decode.scala:694:33, :703:23] assign io_out_target_0 = _io_out_target_T_16; // @[decode.scala:629:7, :703:23] wire [2:0] _io_out_cfi_type_T = {2'h0, cs_is_br}; // @[decode.scala:694:33, :710:8] wire [2:0] _io_out_cfi_type_T_1 = cs_is_jal ? 3'h2 : _io_out_cfi_type_T; // @[decode.scala:695:34, :708:8, :710:8] assign _io_out_cfi_type_T_2 = cs_is_jalr ? 3'h3 : _io_out_cfi_type_T_1; // @[decode.scala:696:35, :706:8, :708:8] assign io_out_cfi_type_0 = _io_out_cfi_type_T_2; // @[decode.scala:629:7, :706:8] wire [4:0] br_offset_lo = {_br_offset_T_2, 1'h0}; // @[decode.scala:714:{22,58}] wire [6:0] br_offset_hi = {_br_offset_T, _br_offset_T_1}; // @[decode.scala:714:{22,30,42}] wire [11:0] br_offset = {br_offset_hi, br_offset_lo}; // @[decode.scala:714:22] wire _io_out_sfb_offset_valid_T_1 = ~_io_out_sfb_offset_valid_T; // @[decode.scala:716:{42,50}] wire _io_out_sfb_offset_valid_T_2 = cs_is_br & _io_out_sfb_offset_valid_T_1; // @[decode.scala:694:33, :716:{39,42}] wire _io_out_sfb_offset_valid_T_3 = |br_offset; // @[decode.scala:714:22, :716:68] wire _io_out_sfb_offset_valid_T_4 = _io_out_sfb_offset_valid_T_2 & _io_out_sfb_offset_valid_T_3; // @[decode.scala:716:{39,55,68}] wire [5:0] _io_out_sfb_offset_valid_T_5 = br_offset[11:6]; // @[decode.scala:714:22, :716:90] wire _io_out_sfb_offset_valid_T_6 = _io_out_sfb_offset_valid_T_5 == 6'h0; // @[decode.scala:716:{90,117}] assign _io_out_sfb_offset_valid_T_7 = _io_out_sfb_offset_valid_T_4 & _io_out_sfb_offset_valid_T_6; // @[decode.scala:716:{55,76,117}] assign io_out_sfb_offset_valid_0 = _io_out_sfb_offset_valid_T_7; // @[decode.scala:629:7, :716:76] assign io_out_sfb_offset_bits_0 = br_offset[5:0]; // @[decode.scala:629:7, :714:22, :717:27] wire _io_out_shadowable_T = ~cs_has_rs2; // @[decode.scala:698:35, :719:5] wire _io_out_shadowable_T_3 = _io_out_shadowable_T_1 == _io_out_shadowable_T_2; // @[decode.scala:720:22] wire _io_out_shadowable_T_4 = _io_out_shadowable_T | _io_out_shadowable_T_3; // @[decode.scala:719:{5,17}, :720:22] wire [31:0] _io_out_shadowable_T_5 = io_inst_0 & 32'hFE00707F; // @[decode.scala:629:7, :721:14] wire _io_out_shadowable_T_6 = _io_out_shadowable_T_5 == 32'h33; // @[decode.scala:721:14] wire _io_out_shadowable_T_8 = _io_out_shadowable_T_7 == 5'h0; // @[decode.scala:701:90, :721:41] wire _io_out_shadowable_T_9 = _io_out_shadowable_T_6 & _io_out_shadowable_T_8; // @[decode.scala:721:{14,22,41}] wire _io_out_shadowable_T_10 = _io_out_shadowable_T_4 | _io_out_shadowable_T_9; // @[decode.scala:719:17, :720:42, :721:22] assign _io_out_shadowable_T_11 = cs_is_shadowable & _io_out_shadowable_T_10; // @[decode.scala:697:41, :718:41, :720:42] assign io_out_shadowable_0 = _io_out_shadowable_T_11; // @[decode.scala:629:7, :718:41] assign io_out_is_ret = io_out_is_ret_0; // @[decode.scala:629:7] assign io_out_is_call = io_out_is_call_0; // @[decode.scala:629:7] assign io_out_target = io_out_target_0; // @[decode.scala:629:7] assign io_out_cfi_type = io_out_cfi_type_0; // @[decode.scala:629:7] assign io_out_sfb_offset_valid = io_out_sfb_offset_valid_0; // @[decode.scala:629:7] assign io_out_sfb_offset_bits = io_out_sfb_offset_bits_0; // @[decode.scala:629:7] assign io_out_shadowable = io_out_shadowable_0; // @[decode.scala:629:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_24 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x
module OptimizationBarrier_TLBEntryData_24( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_50 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0) node _source_ok_T = shr(io.in.a.bits.source, 11) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits = bits(_uncommonBits_T, 10, 0) node _T_4 = shr(io.in.a.bits.source, 11) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<11>(0h40f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0) node _T_24 = shr(io.in.a.bits.source, 11) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0) node _T_86 = shr(io.in.a.bits.source, 11) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0) node _T_152 = shr(io.in.a.bits.source, 11) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0) node _T_199 = shr(io.in.a.bits.source, 11) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0) node _T_240 = shr(io.in.a.bits.source, 11) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<11>(0h40f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0) node _T_283 = shr(io.in.a.bits.source, 11) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<11>(0h40f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0) node _T_321 = shr(io.in.a.bits.source, 11) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<11>(0h40f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0) node _T_359 = shr(io.in.a.bits.source, 11) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<11>(0h40f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 11) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<12>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<12>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1040> connect a_set, UInt<1040>(0h0) wire a_set_wo_ready : UInt<1040> connect a_set_wo_ready, UInt<1040>(0h0) wire a_opcodes_set : UInt<4160> connect a_opcodes_set, UInt<4160>(0h0) wire a_sizes_set : UInt<4160> connect a_sizes_set, UInt<4160>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1040> connect d_clr, UInt<1040>(0h0) wire d_clr_wo_ready : UInt<1040> connect d_clr_wo_ready, UInt<1040>(0h0) wire d_opcodes_clr : UInt<4160> connect d_opcodes_clr, UInt<4160>(0h0) wire d_sizes_clr : UInt<4160> connect d_sizes_clr, UInt<4160>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_101 node _T_656 = orr(inflight) node _T_657 = eq(_T_656, UInt<1>(0h0)) node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_659 = or(_T_657, _T_658) node _T_660 = lt(watchdog, plusarg_reader.out) node _T_661 = or(_T_659, _T_660) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_661, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_665 = and(io.in.a.ready, io.in.a.valid) node _T_666 = and(io.in.d.ready, io.in.d.valid) node _T_667 = or(_T_665, _T_666) when _T_667 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<12>(0h0) connect _c_first_WIRE.bits.source, UInt<11>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<12>(0h0) connect _c_first_WIRE_2.bits.source, UInt<11>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1040> connect c_set, UInt<1040>(0h0) wire c_set_wo_ready : UInt<1040> connect c_set_wo_ready, UInt<1040>(0h0) wire c_opcodes_set : UInt<4160> connect c_opcodes_set, UInt<4160>(0h0) wire c_sizes_set : UInt<4160> connect c_sizes_set, UInt<4160>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<12>(0h0) connect _WIRE_6.bits.source, UInt<11>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_668 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<12>(0h0) connect _WIRE_8.bits.source, UInt<11>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_671 = and(_T_669, _T_670) node _T_672 = and(_T_668, _T_671) when _T_672 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<12>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<12>(0h0) connect _WIRE_10.bits.source, UInt<11>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_674 = and(_T_673, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<12>(0h0) connect _WIRE_12.bits.source, UInt<11>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_677 = and(_T_675, _T_676) node _T_678 = and(_T_674, _T_677) when _T_678 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<12>(0h0) connect _c_set_WIRE.bits.source, UInt<11>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<12>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<12>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<12>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<12>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<12>(0h0) connect _WIRE_14.bits.source, UInt<11>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_679 = dshr(inflight_1, _WIRE_15.bits.source) node _T_680 = bits(_T_679, 0, 0) node _T_681 = eq(_T_680, UInt<1>(0h0)) node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(_T_681, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_681, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<12>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<12>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1040> connect d_clr_1, UInt<1040>(0h0) wire d_clr_wo_ready_1 : UInt<1040> connect d_clr_wo_ready_1, UInt<1040>(0h0) wire d_opcodes_clr_1 : UInt<4160> connect d_opcodes_clr_1, UInt<4160>(0h0) wire d_sizes_clr_1 : UInt<4160> connect d_sizes_clr_1, UInt<4160>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_688 = and(io.in.d.ready, io.in.d.valid) node _T_689 = and(_T_688, d_first_2) node _T_690 = and(_T_689, UInt<1>(0h1)) node _T_691 = and(_T_690, d_release_ack_1) when _T_691 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_695 = dshr(inflight_1, io.in.d.bits.source) node _T_696 = bits(_T_695, 0, 0) node _T_697 = or(_T_696, same_cycle_resp_1) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_697, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<12>(0h0) connect _WIRE_16.bits.source, UInt<11>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_701, UInt<1>(0h1), "") : assert_108 else : node _T_705 = eq(io.in.d.bits.size, c_size_lookup) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_705, UInt<1>(0h1), "") : assert_109 node _T_709 = and(io.in.d.valid, d_first_2) node _T_710 = and(_T_709, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<12>(0h0) connect _WIRE_18.bits.source, UInt<11>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_711 = and(_T_710, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<12>(0h0) connect _WIRE_20.bits.source, UInt<11>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_713 = and(_T_711, _T_712) node _T_714 = and(_T_713, d_release_ack_1) node _T_715 = eq(c_probe_ack, UInt<1>(0h0)) node _T_716 = and(_T_714, _T_715) when _T_716 : node _T_717 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<12>(0h0) connect _WIRE_22.bits.source, UInt<11>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_718 = or(_T_717, _WIRE_23.ready) node _T_719 = asUInt(reset) node _T_720 = eq(_T_719, UInt<1>(0h0)) when _T_720 : node _T_721 = eq(_T_718, UInt<1>(0h0)) when _T_721 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_718, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_102 node _T_722 = orr(inflight_1) node _T_723 = eq(_T_722, UInt<1>(0h0)) node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_725 = or(_T_723, _T_724) node _T_726 = lt(watchdog_1, plusarg_reader_1.out) node _T_727 = or(_T_725, _T_726) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_727, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<12>(0h0) connect _WIRE_24.bits.source, UInt<11>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_732 = and(io.in.d.ready, io.in.d.valid) node _T_733 = or(_T_731, _T_732) when _T_733 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_50( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [11:0] address; // @[Monitor.scala:391:22] reg d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] reg a_first_counter_1; // @[Edges.scala:229:27] reg d_first_counter_1; // @[Edges.scala:229:27] wire _GEN = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg d_first_counter_2; // @[Edges.scala:229:27] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_21 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, flip grant : UInt<1>, iss_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip in_uop : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}, out_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip kill : UInt<1>, flip clear : UInt<1>, flip squash_grant : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}}[2], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip child_rebusys : UInt<3>} regreset slot_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg slot_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock wire next_valid : UInt<1> connect next_valid, slot_valid wire next_uop_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect next_uop_out, slot_uop node _next_uop_out_br_mask_T = not(io.brupdate.b1.resolve_mask) node _next_uop_out_br_mask_T_1 = and(slot_uop.br_mask, _next_uop_out_br_mask_T) connect next_uop_out.br_mask, _next_uop_out_br_mask_T_1 wire next_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect next_uop, next_uop_out node _killed_T = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _killed_T_1 = neq(_killed_T, UInt<1>(0h0)) node killed = or(_killed_T_1, io.kill) connect io.valid, slot_valid connect io.out_uop, next_uop node _io_will_be_valid_T = eq(killed, UInt<1>(0h0)) node _io_will_be_valid_T_1 = and(next_valid, _io_will_be_valid_T) connect io.will_be_valid, _io_will_be_valid_T_1 when io.kill : connect slot_valid, UInt<1>(0h0) else : when io.in_uop.valid : connect slot_valid, UInt<1>(0h1) else : when io.clear : connect slot_valid, UInt<1>(0h0) else : node _slot_valid_T = eq(killed, UInt<1>(0h0)) node _slot_valid_T_1 = and(next_valid, _slot_valid_T) connect slot_valid, _slot_valid_T_1 when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T = eq(slot_valid, UInt<1>(0h0)) node _T_1 = or(_T, io.clear) node _T_2 = or(_T_1, io.kill) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:79 assert (!slot_valid || io.clear || io.kill)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert else : connect slot_uop, next_uop connect next_uop.iw_p1_bypass_hint, UInt<1>(0h0) connect next_uop.iw_p2_bypass_hint, UInt<1>(0h0) connect next_uop.iw_p3_bypass_hint, UInt<1>(0h0) connect next_uop.iw_p1_speculative_child, UInt<1>(0h0) connect next_uop.iw_p2_speculative_child, UInt<1>(0h0) wire rebusied_prs1 : UInt<1> connect rebusied_prs1, UInt<1>(0h0) wire rebusied_prs2 : UInt<1> connect rebusied_prs2, UInt<1>(0h0) node rebusied = or(rebusied_prs1, rebusied_prs2) node prs1_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs1) node prs1_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs1) node prs2_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs2) node prs2_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs2) node prs3_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs3) node prs3_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs3) node prs1_wakeups_0 = and(io.wakeup_ports[0].valid, prs1_matches_0) node prs1_wakeups_1 = and(io.wakeup_ports[1].valid, prs1_matches_1) node prs2_wakeups_0 = and(io.wakeup_ports[0].valid, prs2_matches_0) node prs2_wakeups_1 = and(io.wakeup_ports[1].valid, prs2_matches_1) node prs3_wakeups_0 = and(io.wakeup_ports[0].valid, prs3_matches_0) node prs3_wakeups_1 = and(io.wakeup_ports[1].valid, prs3_matches_1) node prs1_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs1_matches_0) node prs1_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs1_matches_1) node prs2_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs2_matches_0) node prs2_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs2_matches_1) node _T_6 = or(prs1_wakeups_0, prs1_wakeups_1) when _T_6 : connect next_uop.prs1_busy, UInt<1>(0h0) node _next_uop_iw_p1_speculative_child_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_2 = or(_next_uop_iw_p1_speculative_child_T, _next_uop_iw_p1_speculative_child_T_1) wire _next_uop_iw_p1_speculative_child_WIRE : UInt<3> connect _next_uop_iw_p1_speculative_child_WIRE, _next_uop_iw_p1_speculative_child_T_2 connect next_uop.iw_p1_speculative_child, _next_uop_iw_p1_speculative_child_WIRE node _next_uop_iw_p1_bypass_hint_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_2 = or(_next_uop_iw_p1_bypass_hint_T, _next_uop_iw_p1_bypass_hint_T_1) wire _next_uop_iw_p1_bypass_hint_WIRE : UInt<1> connect _next_uop_iw_p1_bypass_hint_WIRE, _next_uop_iw_p1_bypass_hint_T_2 connect next_uop.iw_p1_bypass_hint, _next_uop_iw_p1_bypass_hint_WIRE node _T_7 = or(prs1_rebusys_0, prs1_rebusys_1) node _T_8 = and(io.child_rebusys, slot_uop.iw_p1_speculative_child) node _T_9 = neq(_T_8, UInt<1>(0h0)) node _T_10 = or(_T_7, _T_9) node _T_11 = eq(slot_uop.lrs1_rtype, UInt<2>(0h0)) node _T_12 = and(_T_10, _T_11) when _T_12 : connect next_uop.prs1_busy, UInt<1>(0h1) connect rebusied_prs1, UInt<1>(0h1) node _T_13 = or(prs2_wakeups_0, prs2_wakeups_1) when _T_13 : connect next_uop.prs2_busy, UInt<1>(0h0) node _next_uop_iw_p2_speculative_child_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_2 = or(_next_uop_iw_p2_speculative_child_T, _next_uop_iw_p2_speculative_child_T_1) wire _next_uop_iw_p2_speculative_child_WIRE : UInt<3> connect _next_uop_iw_p2_speculative_child_WIRE, _next_uop_iw_p2_speculative_child_T_2 connect next_uop.iw_p2_speculative_child, _next_uop_iw_p2_speculative_child_WIRE node _next_uop_iw_p2_bypass_hint_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_2 = or(_next_uop_iw_p2_bypass_hint_T, _next_uop_iw_p2_bypass_hint_T_1) wire _next_uop_iw_p2_bypass_hint_WIRE : UInt<1> connect _next_uop_iw_p2_bypass_hint_WIRE, _next_uop_iw_p2_bypass_hint_T_2 connect next_uop.iw_p2_bypass_hint, _next_uop_iw_p2_bypass_hint_WIRE node _T_14 = or(prs2_rebusys_0, prs2_rebusys_1) node _T_15 = and(io.child_rebusys, slot_uop.iw_p2_speculative_child) node _T_16 = neq(_T_15, UInt<1>(0h0)) node _T_17 = or(_T_14, _T_16) node _T_18 = eq(slot_uop.lrs2_rtype, UInt<2>(0h0)) node _T_19 = and(_T_17, _T_18) when _T_19 : connect next_uop.prs2_busy, UInt<1>(0h1) connect rebusied_prs2, UInt<1>(0h1) node _T_20 = or(prs3_wakeups_0, prs3_wakeups_1) when _T_20 : connect next_uop.prs3_busy, UInt<1>(0h0) node _next_uop_iw_p3_bypass_hint_T = mux(prs3_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_1 = mux(prs3_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_2 = or(_next_uop_iw_p3_bypass_hint_T, _next_uop_iw_p3_bypass_hint_T_1) wire _next_uop_iw_p3_bypass_hint_WIRE : UInt<1> connect _next_uop_iw_p3_bypass_hint_WIRE, _next_uop_iw_p3_bypass_hint_T_2 connect next_uop.iw_p3_bypass_hint, _next_uop_iw_p3_bypass_hint_WIRE node _T_21 = eq(io.pred_wakeup_port.bits, slot_uop.ppred) node _T_22 = and(io.pred_wakeup_port.valid, _T_21) when _T_22 : connect next_uop.ppred_busy, UInt<1>(0h0) node _iss_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0)) node _iss_ready_T_1 = eq(slot_uop.prs2_busy, UInt<1>(0h0)) node _iss_ready_T_2 = and(_iss_ready_T, _iss_ready_T_1) node _iss_ready_T_3 = and(slot_uop.ppred_busy, UInt<1>(0h1)) node _iss_ready_T_4 = eq(_iss_ready_T_3, UInt<1>(0h0)) node _iss_ready_T_5 = and(_iss_ready_T_2, _iss_ready_T_4) node _iss_ready_T_6 = and(slot_uop.prs3_busy, UInt<1>(0h1)) node _iss_ready_T_7 = eq(_iss_ready_T_6, UInt<1>(0h0)) node iss_ready = and(_iss_ready_T_5, _iss_ready_T_7) node _agen_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0)) node _agen_ready_T_1 = and(slot_uop.fu_code[1], _agen_ready_T) node _agen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1)) node _agen_ready_T_3 = eq(_agen_ready_T_2, UInt<1>(0h0)) node _agen_ready_T_4 = and(_agen_ready_T_1, _agen_ready_T_3) node agen_ready = and(_agen_ready_T_4, UInt<1>(0h0)) node _dgen_ready_T = eq(slot_uop.prs2_busy, UInt<1>(0h0)) node _dgen_ready_T_1 = and(slot_uop.fu_code[2], _dgen_ready_T) node _dgen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1)) node _dgen_ready_T_3 = eq(_dgen_ready_T_2, UInt<1>(0h0)) node _dgen_ready_T_4 = and(_dgen_ready_T_1, _dgen_ready_T_3) node dgen_ready = and(_dgen_ready_T_4, UInt<1>(0h0)) node _io_request_T = eq(slot_uop.iw_issued, UInt<1>(0h0)) node _io_request_T_1 = and(slot_valid, _io_request_T) node _io_request_T_2 = or(iss_ready, agen_ready) node _io_request_T_3 = or(_io_request_T_2, dgen_ready) node _io_request_T_4 = and(_io_request_T_1, _io_request_T_3) connect io.request, _io_request_T_4 connect io.iss_uop, slot_uop connect next_uop.iw_issued, UInt<1>(0h0) connect next_uop.iw_issued_partial_agen, UInt<1>(0h0) connect next_uop.iw_issued_partial_dgen, UInt<1>(0h0) node _T_23 = eq(io.squash_grant, UInt<1>(0h0)) node _T_24 = and(io.grant, _T_23) when _T_24 : connect next_uop.iw_issued, UInt<1>(0h1) node _T_25 = and(slot_valid, slot_uop.iw_issued) when _T_25 : connect next_valid, rebusied
module IssueSlot_21( // @[issue-slot.scala:49:7] input clock, // @[issue-slot.scala:49:7] input reset, // @[issue-slot.scala:49:7] output io_valid, // @[issue-slot.scala:52:14] output io_will_be_valid, // @[issue-slot.scala:52:14] output io_request, // @[issue-slot.scala:52:14] input io_grant, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14] output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14] output io_iss_uop_is_fence, // @[issue-slot.scala:52:14] output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14] output io_iss_uop_is_amo, // @[issue-slot.scala:52:14] output io_iss_uop_is_eret, // @[issue-slot.scala:52:14] output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14] output io_iss_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14] output io_iss_uop_taken, // @[issue-slot.scala:52:14] output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14] output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_iss_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14] output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14] output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14] output io_iss_uop_is_unique, // @[issue-slot.scala:52:14] output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14] output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14] output io_iss_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_in_uop_valid, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14] input io_in_uop_bits_taken, // @[issue-slot.scala:52:14] input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14] input io_in_uop_bits_exception, // @[issue-slot.scala:52:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14] input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14] output io_out_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued, // @[issue-slot.scala:52:14] output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14] output io_out_uop_is_sfb, // @[issue-slot.scala:52:14] output io_out_uop_is_fence, // @[issue-slot.scala:52:14] output io_out_uop_is_fencei, // @[issue-slot.scala:52:14] output io_out_uop_is_sfence, // @[issue-slot.scala:52:14] output io_out_uop_is_amo, // @[issue-slot.scala:52:14] output io_out_uop_is_eret, // @[issue-slot.scala:52:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_out_uop_is_rocc, // @[issue-slot.scala:52:14] output io_out_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_out_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14] output io_out_uop_taken, // @[issue-slot.scala:52:14] output io_out_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_out_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14] output io_out_uop_mem_signed, // @[issue-slot.scala:52:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_out_uop_uses_stq, // @[issue-slot.scala:52:14] output io_out_uop_is_unique, // @[issue-slot.scala:52:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_out_uop_frs3_en, // @[issue-slot.scala:52:14] output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14] output io_out_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14] input io_brupdate_b2_taken, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14] input io_kill, // @[issue-slot.scala:52:14] input io_clear, // @[issue-slot.scala:52:14] input io_squash_grant, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc // @[issue-slot.scala:52:14] ); wire [15:0] next_uop_out_br_mask; // @[util.scala:104:23] wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7] wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7] wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:49:7] wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23] wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23] wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28] wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28] wire rebusied_prs1 = 1'h0; // @[issue-slot.scala:92:31] wire rebusied_prs2 = 1'h0; // @[issue-slot.scala:93:31] wire rebusied = 1'h0; // @[issue-slot.scala:94:32] wire prs1_rebusys_0 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91] wire prs2_rebusys_0 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91] wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire agen_ready = 1'h0; // @[issue-slot.scala:137:114] wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114] wire [2:0] io_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] io_child_rebusys = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] next_uop_iw_p1_speculative_child = 3'h0; // @[issue-slot.scala:59:28] wire [2:0] next_uop_iw_p2_speculative_child = 3'h0; // @[issue-slot.scala:59:28] wire [2:0] _next_uop_iw_p1_speculative_child_T = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p1_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p1_speculative_child_T_2 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p1_speculative_child_WIRE = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p2_speculative_child_T = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p2_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p2_speculative_child_T_2 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p2_speculative_child_WIRE = 3'h0; // @[Mux.scala:30:73] wire io_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:49:7] wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34] wire _io_request_T_4; // @[issue-slot.scala:140:51] wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28] wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28] wire next_uop_is_rvc; // @[issue-slot.scala:59:28] wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28] wire next_uop_iq_type_0; // @[issue-slot.scala:59:28] wire next_uop_iq_type_1; // @[issue-slot.scala:59:28] wire next_uop_iq_type_2; // @[issue-slot.scala:59:28] wire next_uop_iq_type_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_0; // @[issue-slot.scala:59:28] wire next_uop_fu_code_1; // @[issue-slot.scala:59:28] wire next_uop_fu_code_2; // @[issue-slot.scala:59:28] wire next_uop_fu_code_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_4; // @[issue-slot.scala:59:28] wire next_uop_fu_code_5; // @[issue-slot.scala:59:28] wire next_uop_fu_code_6; // @[issue-slot.scala:59:28] wire next_uop_fu_code_7; // @[issue-slot.scala:59:28] wire next_uop_fu_code_8; // @[issue-slot.scala:59:28] wire next_uop_fu_code_9; // @[issue-slot.scala:59:28] wire next_uop_iw_issued; // @[issue-slot.scala:59:28] wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28] wire [2:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28] wire [15:0] next_uop_br_mask; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28] wire next_uop_is_sfb; // @[issue-slot.scala:59:28] wire next_uop_is_fence; // @[issue-slot.scala:59:28] wire next_uop_is_fencei; // @[issue-slot.scala:59:28] wire next_uop_is_sfence; // @[issue-slot.scala:59:28] wire next_uop_is_amo; // @[issue-slot.scala:59:28] wire next_uop_is_eret; // @[issue-slot.scala:59:28] wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28] wire next_uop_is_rocc; // @[issue-slot.scala:59:28] wire next_uop_is_mov; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28] wire next_uop_edge_inst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28] wire next_uop_taken; // @[issue-slot.scala:59:28] wire next_uop_imm_rename; // @[issue-slot.scala:59:28] wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28] wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28] wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28] wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28] wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28] wire [6:0] next_uop_rob_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_stq_idx; // @[issue-slot.scala:59:28] wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28] wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28] wire next_uop_prs1_busy; // @[issue-slot.scala:59:28] wire next_uop_prs2_busy; // @[issue-slot.scala:59:28] wire next_uop_prs3_busy; // @[issue-slot.scala:59:28] wire next_uop_ppred_busy; // @[issue-slot.scala:59:28] wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28] wire next_uop_exception; // @[issue-slot.scala:59:28] wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28] wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28] wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28] wire next_uop_mem_signed; // @[issue-slot.scala:59:28] wire next_uop_uses_ldq; // @[issue-slot.scala:59:28] wire next_uop_uses_stq; // @[issue-slot.scala:59:28] wire next_uop_is_unique; // @[issue-slot.scala:59:28] wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28] wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28] wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28] wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28] wire next_uop_frs3_en; // @[issue-slot.scala:59:28] wire next_uop_fcn_dw; // @[issue-slot.scala:59:28] wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28] wire next_uop_fp_val; // @[issue-slot.scala:59:28] wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28] wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28] wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28] wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28] wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7] wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_out_uop_taken_0; // @[issue-slot.scala:49:7] wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_out_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_valid_0; // @[issue-slot.scala:49:7] wire io_will_be_valid_0; // @[issue-slot.scala:49:7] wire io_request_0; // @[issue-slot.scala:49:7] reg slot_valid; // @[issue-slot.scala:55:27] assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27] reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23] reg slot_uop_is_rvc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21] wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23] reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23] reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23] reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23] reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23] reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23] reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23] reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23] reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23] reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23] reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23] reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23] reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23] reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23] reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23] reg slot_uop_iw_issued; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23] reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23] reg [2:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:56:21] assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21] assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23] reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21] assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23] reg slot_uop_is_sfb; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23] reg slot_uop_is_fence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23] reg slot_uop_is_fencei; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23] reg slot_uop_is_sfence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23] reg slot_uop_is_amo; // @[issue-slot.scala:56:21] assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23] reg slot_uop_is_eret; // @[issue-slot.scala:56:21] assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23] reg slot_uop_is_rocc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23] reg slot_uop_is_mov; // @[issue-slot.scala:56:21] assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23] reg slot_uop_edge_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21] assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23] reg slot_uop_taken; // @[issue-slot.scala:56:21] assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23] reg slot_uop_imm_rename; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23] reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23] reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21] assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21] wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23] reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23] reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23] reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23] reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23] reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23] reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23] reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23] reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23] wire _iss_ready_T_6 = slot_uop_prs3_busy; // @[issue-slot.scala:56:21, :136:131] reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23] wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88] wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95] wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23] reg slot_uop_exception; // @[issue-slot.scala:56:21] assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21] assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21] wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23] reg slot_uop_mem_signed; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23] reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23] reg slot_uop_uses_stq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23] reg slot_uop_is_unique; // @[issue-slot.scala:56:21] assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23] reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21] assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23] reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23] reg slot_uop_frs3_en; // @[issue-slot.scala:56:21] assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23] reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23] reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23] reg slot_uop_fp_val; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23] reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23] reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23] reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23] reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23] wire next_valid; // @[issue-slot.scala:58:28] assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23] assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23] assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23] assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23] assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23] assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23] assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23] assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23] assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23] assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23] assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23] assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23] assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23] assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23] assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23] assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23] assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23] assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25] assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23] assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23] assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23] assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23] assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23] assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23] assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23] assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23] assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23] assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23] assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23] assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23] assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23] assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23] assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23] assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23] assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23] assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23] assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23] assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23] assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23] assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23] assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23] assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23] assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23] assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23] assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23] assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23] assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23] assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23] assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23] assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23] assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23] assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23] assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23] assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23] assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23] assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23] assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23] assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23] assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23] assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23] assign next_uop_ppred_busy = next_uop_out_ppred_busy; // @[util.scala:104:23] assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23] assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23] assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23] assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23] assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23] assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23] assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23] assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23] assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23] assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23] assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23] assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23] assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23] assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23] assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23] assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23] assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23] assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23] assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23] assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23] assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23] assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23] assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23] assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23] assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23] assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23] assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23] assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23] assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23] assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23] assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23] assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28] wire [15:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51] wire _killed_T_1 = |_killed_T; // @[util.scala:126:{51,59}] wire killed = _killed_T_1 | io_kill_0; // @[util.scala:61:61, :126:59] wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61] assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}] assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34] wire _slot_valid_T = ~killed; // @[util.scala:61:61] wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_398 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_398( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_121 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x
module OptimizationBarrier_TLBEntryData_121( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Tile_143 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_399 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a
module Tile_143( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_399 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module ListBuffer_PutBufferAEntry_q40_e40 : input clock : Clock input reset : Reset output io : { flip push : { flip ready : UInt<1>, valid : UInt<1>, bits : { index : UInt<6>, data : { data : UInt<32>, mask : UInt<4>, corrupt : UInt<1>}}}, valid : UInt<40>, flip pop : { valid : UInt<1>, bits : UInt<6>}, data : { data : UInt<32>, mask : UInt<4>, corrupt : UInt<1>}} regreset valid : UInt<40>, clock, reset, UInt<40>(0h0) cmem head : UInt<6> [40] cmem tail : UInt<6> [40] regreset used : UInt<40>, clock, reset, UInt<40>(0h0) cmem next : UInt<6> [40] cmem data : { data : UInt<32>, mask : UInt<4>, corrupt : UInt<1>} [40] node _freeOH_T = not(used) node _freeOH_T_1 = shl(_freeOH_T, 1) node _freeOH_T_2 = bits(_freeOH_T_1, 39, 0) node _freeOH_T_3 = or(_freeOH_T, _freeOH_T_2) node _freeOH_T_4 = shl(_freeOH_T_3, 2) node _freeOH_T_5 = bits(_freeOH_T_4, 39, 0) node _freeOH_T_6 = or(_freeOH_T_3, _freeOH_T_5) node _freeOH_T_7 = shl(_freeOH_T_6, 4) node _freeOH_T_8 = bits(_freeOH_T_7, 39, 0) node _freeOH_T_9 = or(_freeOH_T_6, _freeOH_T_8) node _freeOH_T_10 = shl(_freeOH_T_9, 8) node _freeOH_T_11 = bits(_freeOH_T_10, 39, 0) node _freeOH_T_12 = or(_freeOH_T_9, _freeOH_T_11) node _freeOH_T_13 = shl(_freeOH_T_12, 16) node _freeOH_T_14 = bits(_freeOH_T_13, 39, 0) node _freeOH_T_15 = or(_freeOH_T_12, _freeOH_T_14) node _freeOH_T_16 = shl(_freeOH_T_15, 32) node _freeOH_T_17 = bits(_freeOH_T_16, 39, 0) node _freeOH_T_18 = or(_freeOH_T_15, _freeOH_T_17) node _freeOH_T_19 = bits(_freeOH_T_18, 39, 0) node _freeOH_T_20 = shl(_freeOH_T_19, 1) node _freeOH_T_21 = not(_freeOH_T_20) node _freeOH_T_22 = not(used) node freeOH = and(_freeOH_T_21, _freeOH_T_22) node freeIdx_hi = bits(freeOH, 40, 32) node freeIdx_lo = bits(freeOH, 31, 0) node _freeIdx_T = orr(freeIdx_hi) node _freeIdx_T_1 = or(freeIdx_hi, freeIdx_lo) node freeIdx_hi_1 = bits(_freeIdx_T_1, 31, 16) node freeIdx_lo_1 = bits(_freeIdx_T_1, 15, 0) node _freeIdx_T_2 = orr(freeIdx_hi_1) node _freeIdx_T_3 = or(freeIdx_hi_1, freeIdx_lo_1) node freeIdx_hi_2 = bits(_freeIdx_T_3, 15, 8) node freeIdx_lo_2 = bits(_freeIdx_T_3, 7, 0) node _freeIdx_T_4 = orr(freeIdx_hi_2) node _freeIdx_T_5 = or(freeIdx_hi_2, freeIdx_lo_2) node freeIdx_hi_3 = bits(_freeIdx_T_5, 7, 4) node freeIdx_lo_3 = bits(_freeIdx_T_5, 3, 0) node _freeIdx_T_6 = orr(freeIdx_hi_3) node _freeIdx_T_7 = or(freeIdx_hi_3, freeIdx_lo_3) node freeIdx_hi_4 = bits(_freeIdx_T_7, 3, 2) node freeIdx_lo_4 = bits(_freeIdx_T_7, 1, 0) node _freeIdx_T_8 = orr(freeIdx_hi_4) node _freeIdx_T_9 = or(freeIdx_hi_4, freeIdx_lo_4) node _freeIdx_T_10 = bits(_freeIdx_T_9, 1, 1) node _freeIdx_T_11 = cat(_freeIdx_T_8, _freeIdx_T_10) node _freeIdx_T_12 = cat(_freeIdx_T_6, _freeIdx_T_11) node _freeIdx_T_13 = cat(_freeIdx_T_4, _freeIdx_T_12) node _freeIdx_T_14 = cat(_freeIdx_T_2, _freeIdx_T_13) node freeIdx = cat(_freeIdx_T, _freeIdx_T_14) wire valid_set : UInt<40> connect valid_set, UInt<40>(0h0) wire valid_clr : UInt<40> connect valid_clr, UInt<40>(0h0) wire used_set : UInt<40> connect used_set, UInt<40>(0h0) wire used_clr : UInt<40> connect used_clr, UInt<40>(0h0) read mport push_tail = tail[io.push.bits.index], clock node _push_valid_T = dshr(valid, io.push.bits.index) node push_valid = bits(_push_valid_T, 0, 0) node _io_push_ready_T = andr(used) node _io_push_ready_T_1 = eq(_io_push_ready_T, UInt<1>(0h0)) connect io.push.ready, _io_push_ready_T_1 node _T = and(io.push.ready, io.push.valid) when _T : node valid_set_shiftAmount = bits(io.push.bits.index, 5, 0) node _valid_set_T = dshl(UInt<1>(0h1), valid_set_shiftAmount) node _valid_set_T_1 = bits(_valid_set_T, 39, 0) connect valid_set, _valid_set_T_1 connect used_set, freeOH write mport MPORT = data[freeIdx], clock connect MPORT, io.push.bits.data when push_valid : write mport MPORT_1 = next[push_tail], clock connect MPORT_1, freeIdx else : write mport MPORT_2 = head[io.push.bits.index], clock connect MPORT_2, freeIdx write mport MPORT_3 = tail[io.push.bits.index], clock connect MPORT_3, freeIdx read mport pop_head = head[io.pop.bits], clock node _pop_valid_T = dshr(valid, io.pop.bits) node pop_valid = bits(_pop_valid_T, 0, 0) read mport io_data_MPORT = data[pop_head], clock connect io.data, io_data_MPORT connect io.valid, valid node _T_1 = eq(io.pop.valid, UInt<1>(0h0)) node _T_2 = dshr(io.valid, io.pop.bits) node _T_3 = bits(_T_2, 0, 0) node _T_4 = or(_T_1, _T_3) node _T_5 = asUInt(reset) node _T_6 = eq(_T_5, UInt<1>(0h0)) when _T_6 : node _T_7 = eq(_T_4, UInt<1>(0h0)) when _T_7 : printf(clock, UInt<1>(0h1), "Assertion failed\n at ListBuffer.scala:86 assert (!io.pop.fire || (io.valid)(io.pop.bits))\n") : printf assert(clock, _T_4, UInt<1>(0h1), "") : assert when io.pop.valid : node used_clr_shiftAmount = bits(pop_head, 5, 0) node _used_clr_T = dshl(UInt<1>(0h1), used_clr_shiftAmount) node _used_clr_T_1 = bits(_used_clr_T, 39, 0) connect used_clr, _used_clr_T_1 read mport MPORT_4 = tail[io.pop.bits], clock node _T_8 = eq(pop_head, MPORT_4) when _T_8 : node valid_clr_shiftAmount = bits(io.pop.bits, 5, 0) node _valid_clr_T = dshl(UInt<1>(0h1), valid_clr_shiftAmount) node _valid_clr_T_1 = bits(_valid_clr_T, 39, 0) connect valid_clr, _valid_clr_T_1 node _T_9 = and(io.push.ready, io.push.valid) node _T_10 = and(_T_9, push_valid) node _T_11 = eq(push_tail, pop_head) node _T_12 = and(_T_10, _T_11) read mport MPORT_5 = next[pop_head], clock node _T_13 = mux(_T_12, freeIdx, MPORT_5) write mport MPORT_6 = head[io.pop.bits], clock connect MPORT_6, _T_13 node _T_14 = eq(io.pop.valid, UInt<1>(0h0)) node _T_15 = or(UInt<1>(0h1), _T_14) node _T_16 = or(_T_15, pop_valid) when _T_16 : node _used_T = not(used_clr) node _used_T_1 = and(used, _used_T) node _used_T_2 = or(_used_T_1, used_set) connect used, _used_T_2 node _valid_T = not(valid_clr) node _valid_T_1 = and(valid, _valid_T) node _valid_T_2 = or(_valid_T_1, valid_set) connect valid, _valid_T_2
module ListBuffer_PutBufferAEntry_q40_e40( // @[ListBuffer.scala:36:7] input clock, // @[ListBuffer.scala:36:7] input reset, // @[ListBuffer.scala:36:7] output io_push_ready, // @[ListBuffer.scala:39:14] input io_push_valid, // @[ListBuffer.scala:39:14] input [5:0] io_push_bits_index, // @[ListBuffer.scala:39:14] input [31:0] io_push_bits_data_data, // @[ListBuffer.scala:39:14] input [3:0] io_push_bits_data_mask, // @[ListBuffer.scala:39:14] input io_push_bits_data_corrupt, // @[ListBuffer.scala:39:14] output [39:0] io_valid, // @[ListBuffer.scala:39:14] input io_pop_valid, // @[ListBuffer.scala:39:14] input [5:0] io_pop_bits, // @[ListBuffer.scala:39:14] output [31:0] io_data_data, // @[ListBuffer.scala:39:14] output [3:0] io_data_mask, // @[ListBuffer.scala:39:14] output io_data_corrupt // @[ListBuffer.scala:39:14] ); wire [36:0] _data_ext_R0_data; // @[ListBuffer.scala:52:18] wire [5:0] _next_ext_R0_data; // @[ListBuffer.scala:51:18] wire [5:0] _tail_ext_R0_data; // @[ListBuffer.scala:49:18] wire [5:0] _tail_ext_R1_data; // @[ListBuffer.scala:49:18] wire [5:0] _head_ext_R0_data; // @[ListBuffer.scala:48:18] wire io_push_valid_0 = io_push_valid; // @[ListBuffer.scala:36:7] wire [5:0] io_push_bits_index_0 = io_push_bits_index; // @[ListBuffer.scala:36:7] wire [31:0] io_push_bits_data_data_0 = io_push_bits_data_data; // @[ListBuffer.scala:36:7] wire [3:0] io_push_bits_data_mask_0 = io_push_bits_data_mask; // @[ListBuffer.scala:36:7] wire io_push_bits_data_corrupt_0 = io_push_bits_data_corrupt; // @[ListBuffer.scala:36:7] wire io_pop_valid_0 = io_pop_valid; // @[ListBuffer.scala:36:7] wire [5:0] io_pop_bits_0 = io_pop_bits; // @[ListBuffer.scala:36:7] wire _io_push_ready_T_1; // @[ListBuffer.scala:65:20] wire [5:0] valid_set_shiftAmount = io_push_bits_index_0; // @[OneHot.scala:64:49] wire [5:0] valid_clr_shiftAmount = io_pop_bits_0; // @[OneHot.scala:64:49] wire io_push_ready_0; // @[ListBuffer.scala:36:7] wire [31:0] io_data_data_0; // @[ListBuffer.scala:36:7] wire [3:0] io_data_mask_0; // @[ListBuffer.scala:36:7] wire io_data_corrupt_0; // @[ListBuffer.scala:36:7] wire [39:0] io_valid_0; // @[ListBuffer.scala:36:7] reg [39:0] valid; // @[ListBuffer.scala:47:22] assign io_valid_0 = valid; // @[ListBuffer.scala:36:7, :47:22] reg [39:0] used; // @[ListBuffer.scala:50:22] assign io_data_data_0 = _data_ext_R0_data[31:0]; // @[ListBuffer.scala:36:7, :52:18] assign io_data_mask_0 = _data_ext_R0_data[35:32]; // @[ListBuffer.scala:36:7, :52:18] assign io_data_corrupt_0 = _data_ext_R0_data[36]; // @[ListBuffer.scala:36:7, :52:18] wire [39:0] _freeOH_T = ~used; // @[ListBuffer.scala:50:22, :54:25] wire [40:0] _freeOH_T_1 = {_freeOH_T, 1'h0}; // @[package.scala:253:48] wire [39:0] _freeOH_T_2 = _freeOH_T_1[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_3 = _freeOH_T | _freeOH_T_2; // @[package.scala:253:{43,53}] wire [41:0] _freeOH_T_4 = {_freeOH_T_3, 2'h0}; // @[package.scala:253:{43,48}] wire [39:0] _freeOH_T_5 = _freeOH_T_4[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_6 = _freeOH_T_3 | _freeOH_T_5; // @[package.scala:253:{43,53}] wire [43:0] _freeOH_T_7 = {_freeOH_T_6, 4'h0}; // @[package.scala:253:{43,48}] wire [39:0] _freeOH_T_8 = _freeOH_T_7[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_9 = _freeOH_T_6 | _freeOH_T_8; // @[package.scala:253:{43,53}] wire [47:0] _freeOH_T_10 = {_freeOH_T_9, 8'h0}; // @[package.scala:253:{43,48}] wire [39:0] _freeOH_T_11 = _freeOH_T_10[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_12 = _freeOH_T_9 | _freeOH_T_11; // @[package.scala:253:{43,53}] wire [55:0] _freeOH_T_13 = {_freeOH_T_12, 16'h0}; // @[package.scala:253:{43,48}] wire [39:0] _freeOH_T_14 = _freeOH_T_13[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_15 = _freeOH_T_12 | _freeOH_T_14; // @[package.scala:253:{43,53}] wire [71:0] _freeOH_T_16 = {_freeOH_T_15, 32'h0}; // @[package.scala:253:{43,48}] wire [39:0] _freeOH_T_17 = _freeOH_T_16[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_18 = _freeOH_T_15 | _freeOH_T_17; // @[package.scala:253:{43,53}] wire [39:0] _freeOH_T_19 = _freeOH_T_18; // @[package.scala:253:43, :254:17] wire [40:0] _freeOH_T_20 = {_freeOH_T_19, 1'h0}; // @[package.scala:254:17] wire [40:0] _freeOH_T_21 = ~_freeOH_T_20; // @[ListBuffer.scala:54:{16,32}] wire [39:0] _freeOH_T_22 = ~used; // @[ListBuffer.scala:50:22, :54:{25,40}] wire [40:0] freeOH = {1'h0, _freeOH_T_21[39:0] & _freeOH_T_22}; // @[ListBuffer.scala:54:{16,38,40}] wire [8:0] freeIdx_hi = freeOH[40:32]; // @[OneHot.scala:30:18] wire [31:0] freeIdx_lo = freeOH[31:0]; // @[OneHot.scala:31:18] wire _freeIdx_T = |freeIdx_hi; // @[OneHot.scala:30:18, :32:14] wire [31:0] _freeIdx_T_1 = {23'h0, freeIdx_hi} | freeIdx_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [15:0] freeIdx_hi_1 = _freeIdx_T_1[31:16]; // @[OneHot.scala:30:18, :32:28] wire [15:0] freeIdx_lo_1 = _freeIdx_T_1[15:0]; // @[OneHot.scala:31:18, :32:28] wire _freeIdx_T_2 = |freeIdx_hi_1; // @[OneHot.scala:30:18, :32:14] wire [15:0] _freeIdx_T_3 = freeIdx_hi_1 | freeIdx_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [7:0] freeIdx_hi_2 = _freeIdx_T_3[15:8]; // @[OneHot.scala:30:18, :32:28] wire [7:0] freeIdx_lo_2 = _freeIdx_T_3[7:0]; // @[OneHot.scala:31:18, :32:28] wire _freeIdx_T_4 = |freeIdx_hi_2; // @[OneHot.scala:30:18, :32:14] wire [7:0] _freeIdx_T_5 = freeIdx_hi_2 | freeIdx_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] freeIdx_hi_3 = _freeIdx_T_5[7:4]; // @[OneHot.scala:30:18, :32:28] wire [3:0] freeIdx_lo_3 = _freeIdx_T_5[3:0]; // @[OneHot.scala:31:18, :32:28] wire _freeIdx_T_6 = |freeIdx_hi_3; // @[OneHot.scala:30:18, :32:14] wire [3:0] _freeIdx_T_7 = freeIdx_hi_3 | freeIdx_lo_3; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] freeIdx_hi_4 = _freeIdx_T_7[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] freeIdx_lo_4 = _freeIdx_T_7[1:0]; // @[OneHot.scala:31:18, :32:28] wire _freeIdx_T_8 = |freeIdx_hi_4; // @[OneHot.scala:30:18, :32:14] wire [1:0] _freeIdx_T_9 = freeIdx_hi_4 | freeIdx_lo_4; // @[OneHot.scala:30:18, :31:18, :32:28] wire _freeIdx_T_10 = _freeIdx_T_9[1]; // @[OneHot.scala:32:28] wire [1:0] _freeIdx_T_11 = {_freeIdx_T_8, _freeIdx_T_10}; // @[OneHot.scala:32:{10,14}] wire [2:0] _freeIdx_T_12 = {_freeIdx_T_6, _freeIdx_T_11}; // @[OneHot.scala:32:{10,14}] wire [3:0] _freeIdx_T_13 = {_freeIdx_T_4, _freeIdx_T_12}; // @[OneHot.scala:32:{10,14}] wire [4:0] _freeIdx_T_14 = {_freeIdx_T_2, _freeIdx_T_13}; // @[OneHot.scala:32:{10,14}] wire [5:0] freeIdx = {_freeIdx_T, _freeIdx_T_14}; // @[OneHot.scala:32:{10,14}] wire [39:0] valid_set; // @[ListBuffer.scala:57:30] wire [39:0] valid_clr; // @[ListBuffer.scala:58:30] wire [39:0] used_set; // @[ListBuffer.scala:59:30] wire [39:0] used_clr; // @[ListBuffer.scala:60:30] wire [39:0] _push_valid_T = valid >> io_push_bits_index_0; // @[ListBuffer.scala:36:7, :47:22, :63:25] wire push_valid = _push_valid_T[0]; // @[ListBuffer.scala:63:25] wire _io_push_ready_T = &used; // @[ListBuffer.scala:50:22, :65:26] assign _io_push_ready_T_1 = ~_io_push_ready_T; // @[ListBuffer.scala:65:{20,26}] assign io_push_ready_0 = _io_push_ready_T_1; // @[ListBuffer.scala:36:7, :65:20] wire data_MPORT_en = io_push_ready_0 & io_push_valid_0; // @[Decoupled.scala:51:35] wire [63:0] _valid_set_T = 64'h1 << valid_set_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [39:0] _valid_set_T_1 = _valid_set_T[39:0]; // @[OneHot.scala:65:{12,27}] assign valid_set = data_MPORT_en ? _valid_set_T_1 : 40'h0; // @[OneHot.scala:65:27] assign used_set = data_MPORT_en ? freeOH[39:0] : 40'h0; // @[Decoupled.scala:51:35] wire [39:0] _GEN = {34'h0, io_pop_bits_0}; // @[ListBuffer.scala:36:7, :79:24] wire [39:0] _pop_valid_T = valid >> _GEN; // @[ListBuffer.scala:47:22, :79:24] wire pop_valid = _pop_valid_T[0]; // @[ListBuffer.scala:79:24]
Generate the Verilog code corresponding to this FIRRTL code module InputBuffer_1 : input clock : Clock input reset : Reset output io : { flip enq : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>}}[10]} cmem mem : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>} [28] wire _heads_WIRE : UInt<5>[10] connect _heads_WIRE[0], UInt<5>(0h0) connect _heads_WIRE[1], UInt<5>(0h0) connect _heads_WIRE[2], UInt<5>(0h4) connect _heads_WIRE[3], UInt<5>(0h8) connect _heads_WIRE[4], UInt<5>(0h0) connect _heads_WIRE[5], UInt<5>(0hc) connect _heads_WIRE[6], UInt<5>(0h10) connect _heads_WIRE[7], UInt<5>(0h14) connect _heads_WIRE[8], UInt<5>(0h0) connect _heads_WIRE[9], UInt<5>(0h18) regreset heads : UInt<5>[10], clock, reset, _heads_WIRE wire _tails_WIRE : UInt<5>[10] connect _tails_WIRE[0], UInt<5>(0h0) connect _tails_WIRE[1], UInt<5>(0h0) connect _tails_WIRE[2], UInt<5>(0h4) connect _tails_WIRE[3], UInt<5>(0h8) connect _tails_WIRE[4], UInt<5>(0h0) connect _tails_WIRE[5], UInt<5>(0hc) connect _tails_WIRE[6], UInt<5>(0h10) connect _tails_WIRE[7], UInt<5>(0h14) connect _tails_WIRE[8], UInt<5>(0h0) connect _tails_WIRE[9], UInt<5>(0h18) regreset tails : UInt<5>[10], clock, reset, _tails_WIRE node empty_0 = eq(heads[0], tails[0]) node empty_1 = eq(heads[1], tails[1]) node empty_2 = eq(heads[2], tails[2]) node empty_3 = eq(heads[3], tails[3]) node empty_4 = eq(heads[4], tails[4]) node empty_5 = eq(heads[5], tails[5]) node empty_6 = eq(heads[6], tails[6]) node empty_7 = eq(heads[7], tails[7]) node empty_8 = eq(heads[8], tails[8]) node empty_9 = eq(heads[9], tails[9]) inst qs_0 of Queue1_BaseFlit_10 connect qs_0.clock, clock connect qs_0.reset, reset inst qs_1 of Queue1_BaseFlit_11 connect qs_1.clock, clock connect qs_1.reset, reset inst qs_2 of Queue1_BaseFlit_12 connect qs_2.clock, clock connect qs_2.reset, reset inst qs_3 of Queue1_BaseFlit_13 connect qs_3.clock, clock connect qs_3.reset, reset inst qs_4 of Queue1_BaseFlit_14 connect qs_4.clock, clock connect qs_4.reset, reset inst qs_5 of Queue1_BaseFlit_15 connect qs_5.clock, clock connect qs_5.reset, reset inst qs_6 of Queue1_BaseFlit_16 connect qs_6.clock, clock connect qs_6.reset, reset inst qs_7 of Queue1_BaseFlit_17 connect qs_7.clock, clock connect qs_7.reset, reset inst qs_8 of Queue1_BaseFlit_18 connect qs_8.clock, clock connect qs_8.reset, reset inst qs_9 of Queue1_BaseFlit_19 connect qs_9.clock, clock connect qs_9.reset, reset connect qs_0.io.enq.valid, UInt<1>(0h0) connect qs_1.io.enq.valid, UInt<1>(0h0) connect qs_2.io.enq.valid, UInt<1>(0h0) connect qs_3.io.enq.valid, UInt<1>(0h0) connect qs_4.io.enq.valid, UInt<1>(0h0) connect qs_5.io.enq.valid, UInt<1>(0h0) connect qs_6.io.enq.valid, UInt<1>(0h0) connect qs_7.io.enq.valid, UInt<1>(0h0) connect qs_8.io.enq.valid, UInt<1>(0h0) connect qs_9.io.enq.valid, UInt<1>(0h0) invalidate qs_0.io.enq.bits.payload invalidate qs_0.io.enq.bits.tail invalidate qs_0.io.enq.bits.head invalidate qs_1.io.enq.bits.payload invalidate qs_1.io.enq.bits.tail invalidate qs_1.io.enq.bits.head invalidate qs_2.io.enq.bits.payload invalidate qs_2.io.enq.bits.tail invalidate qs_2.io.enq.bits.head invalidate qs_3.io.enq.bits.payload invalidate qs_3.io.enq.bits.tail invalidate qs_3.io.enq.bits.head invalidate qs_4.io.enq.bits.payload invalidate qs_4.io.enq.bits.tail invalidate qs_4.io.enq.bits.head invalidate qs_5.io.enq.bits.payload invalidate qs_5.io.enq.bits.tail invalidate qs_5.io.enq.bits.head invalidate qs_6.io.enq.bits.payload invalidate qs_6.io.enq.bits.tail invalidate qs_6.io.enq.bits.head invalidate qs_7.io.enq.bits.payload invalidate qs_7.io.enq.bits.tail invalidate qs_7.io.enq.bits.head invalidate qs_8.io.enq.bits.payload invalidate qs_8.io.enq.bits.tail invalidate qs_8.io.enq.bits.head invalidate qs_9.io.enq.bits.payload invalidate qs_9.io.enq.bits.tail invalidate qs_9.io.enq.bits.head node vc_sel = dshl(UInt<1>(0h1), io.enq[0].bits.virt_channel_id) wire flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>} node _direct_to_q_T = bits(vc_sel, 0, 0) node _direct_to_q_T_1 = bits(vc_sel, 1, 1) node _direct_to_q_T_2 = bits(vc_sel, 2, 2) node _direct_to_q_T_3 = bits(vc_sel, 3, 3) node _direct_to_q_T_4 = bits(vc_sel, 4, 4) node _direct_to_q_T_5 = bits(vc_sel, 5, 5) node _direct_to_q_T_6 = bits(vc_sel, 6, 6) node _direct_to_q_T_7 = bits(vc_sel, 7, 7) node _direct_to_q_T_8 = bits(vc_sel, 8, 8) node _direct_to_q_T_9 = bits(vc_sel, 9, 9) node _direct_to_q_T_10 = mux(_direct_to_q_T, qs_0.io.enq.ready, UInt<1>(0h0)) node _direct_to_q_T_11 = mux(_direct_to_q_T_1, qs_1.io.enq.ready, UInt<1>(0h0)) node _direct_to_q_T_12 = mux(_direct_to_q_T_2, qs_2.io.enq.ready, UInt<1>(0h0)) node _direct_to_q_T_13 = mux(_direct_to_q_T_3, qs_3.io.enq.ready, UInt<1>(0h0)) node _direct_to_q_T_14 = mux(_direct_to_q_T_4, qs_4.io.enq.ready, UInt<1>(0h0)) node _direct_to_q_T_15 = mux(_direct_to_q_T_5, qs_5.io.enq.ready, UInt<1>(0h0)) node _direct_to_q_T_16 = mux(_direct_to_q_T_6, qs_6.io.enq.ready, UInt<1>(0h0)) node _direct_to_q_T_17 = mux(_direct_to_q_T_7, qs_7.io.enq.ready, UInt<1>(0h0)) node _direct_to_q_T_18 = mux(_direct_to_q_T_8, qs_8.io.enq.ready, UInt<1>(0h0)) node _direct_to_q_T_19 = mux(_direct_to_q_T_9, qs_9.io.enq.ready, UInt<1>(0h0)) node _direct_to_q_T_20 = or(_direct_to_q_T_10, _direct_to_q_T_11) node _direct_to_q_T_21 = or(_direct_to_q_T_20, _direct_to_q_T_12) node _direct_to_q_T_22 = or(_direct_to_q_T_21, _direct_to_q_T_13) node _direct_to_q_T_23 = or(_direct_to_q_T_22, _direct_to_q_T_14) node _direct_to_q_T_24 = or(_direct_to_q_T_23, _direct_to_q_T_15) node _direct_to_q_T_25 = or(_direct_to_q_T_24, _direct_to_q_T_16) node _direct_to_q_T_26 = or(_direct_to_q_T_25, _direct_to_q_T_17) node _direct_to_q_T_27 = or(_direct_to_q_T_26, _direct_to_q_T_18) node _direct_to_q_T_28 = or(_direct_to_q_T_27, _direct_to_q_T_19) wire _direct_to_q_WIRE : UInt<1> connect _direct_to_q_WIRE, _direct_to_q_T_28 node _direct_to_q_T_29 = bits(vc_sel, 0, 0) node _direct_to_q_T_30 = bits(vc_sel, 1, 1) node _direct_to_q_T_31 = bits(vc_sel, 2, 2) node _direct_to_q_T_32 = bits(vc_sel, 3, 3) node _direct_to_q_T_33 = bits(vc_sel, 4, 4) node _direct_to_q_T_34 = bits(vc_sel, 5, 5) node _direct_to_q_T_35 = bits(vc_sel, 6, 6) node _direct_to_q_T_36 = bits(vc_sel, 7, 7) node _direct_to_q_T_37 = bits(vc_sel, 8, 8) node _direct_to_q_T_38 = bits(vc_sel, 9, 9) node _direct_to_q_T_39 = mux(_direct_to_q_T_29, empty_0, UInt<1>(0h0)) node _direct_to_q_T_40 = mux(_direct_to_q_T_30, empty_1, UInt<1>(0h0)) node _direct_to_q_T_41 = mux(_direct_to_q_T_31, empty_2, UInt<1>(0h0)) node _direct_to_q_T_42 = mux(_direct_to_q_T_32, empty_3, UInt<1>(0h0)) node _direct_to_q_T_43 = mux(_direct_to_q_T_33, empty_4, UInt<1>(0h0)) node _direct_to_q_T_44 = mux(_direct_to_q_T_34, empty_5, UInt<1>(0h0)) node _direct_to_q_T_45 = mux(_direct_to_q_T_35, empty_6, UInt<1>(0h0)) node _direct_to_q_T_46 = mux(_direct_to_q_T_36, empty_7, UInt<1>(0h0)) node _direct_to_q_T_47 = mux(_direct_to_q_T_37, empty_8, UInt<1>(0h0)) node _direct_to_q_T_48 = mux(_direct_to_q_T_38, empty_9, UInt<1>(0h0)) node _direct_to_q_T_49 = or(_direct_to_q_T_39, _direct_to_q_T_40) node _direct_to_q_T_50 = or(_direct_to_q_T_49, _direct_to_q_T_41) node _direct_to_q_T_51 = or(_direct_to_q_T_50, _direct_to_q_T_42) node _direct_to_q_T_52 = or(_direct_to_q_T_51, _direct_to_q_T_43) node _direct_to_q_T_53 = or(_direct_to_q_T_52, _direct_to_q_T_44) node _direct_to_q_T_54 = or(_direct_to_q_T_53, _direct_to_q_T_45) node _direct_to_q_T_55 = or(_direct_to_q_T_54, _direct_to_q_T_46) node _direct_to_q_T_56 = or(_direct_to_q_T_55, _direct_to_q_T_47) node _direct_to_q_T_57 = or(_direct_to_q_T_56, _direct_to_q_T_48) wire _direct_to_q_WIRE_1 : UInt<1> connect _direct_to_q_WIRE_1, _direct_to_q_T_57 node _direct_to_q_T_58 = and(_direct_to_q_WIRE, _direct_to_q_WIRE_1) node direct_to_q = and(_direct_to_q_T_58, UInt<1>(0h1)) connect flit.head, io.enq[0].bits.head connect flit.tail, io.enq[0].bits.tail connect flit.payload, io.enq[0].bits.payload node _T = eq(direct_to_q, UInt<1>(0h0)) node _T_1 = and(io.enq[0].valid, _T) when _T_1 : write mport MPORT = mem[tails[io.enq[0].bits.virt_channel_id]], clock connect MPORT, flit node _tails_T = bits(vc_sel, 0, 0) node _tails_T_1 = bits(vc_sel, 1, 1) node _tails_T_2 = bits(vc_sel, 2, 2) node _tails_T_3 = bits(vc_sel, 3, 3) node _tails_T_4 = bits(vc_sel, 4, 4) node _tails_T_5 = bits(vc_sel, 5, 5) node _tails_T_6 = bits(vc_sel, 6, 6) node _tails_T_7 = bits(vc_sel, 7, 7) node _tails_T_8 = bits(vc_sel, 8, 8) node _tails_T_9 = bits(vc_sel, 9, 9) node _tails_T_10 = mux(_tails_T, UInt<1>(0h0), UInt<1>(0h0)) node _tails_T_11 = mux(_tails_T_1, UInt<2>(0h3), UInt<1>(0h0)) node _tails_T_12 = mux(_tails_T_2, UInt<3>(0h7), UInt<1>(0h0)) node _tails_T_13 = mux(_tails_T_3, UInt<4>(0hb), UInt<1>(0h0)) node _tails_T_14 = mux(_tails_T_4, UInt<1>(0h0), UInt<1>(0h0)) node _tails_T_15 = mux(_tails_T_5, UInt<4>(0hf), UInt<1>(0h0)) node _tails_T_16 = mux(_tails_T_6, UInt<5>(0h13), UInt<1>(0h0)) node _tails_T_17 = mux(_tails_T_7, UInt<5>(0h17), UInt<1>(0h0)) node _tails_T_18 = mux(_tails_T_8, UInt<1>(0h0), UInt<1>(0h0)) node _tails_T_19 = mux(_tails_T_9, UInt<5>(0h1b), UInt<1>(0h0)) node _tails_T_20 = or(_tails_T_10, _tails_T_11) node _tails_T_21 = or(_tails_T_20, _tails_T_12) node _tails_T_22 = or(_tails_T_21, _tails_T_13) node _tails_T_23 = or(_tails_T_22, _tails_T_14) node _tails_T_24 = or(_tails_T_23, _tails_T_15) node _tails_T_25 = or(_tails_T_24, _tails_T_16) node _tails_T_26 = or(_tails_T_25, _tails_T_17) node _tails_T_27 = or(_tails_T_26, _tails_T_18) node _tails_T_28 = or(_tails_T_27, _tails_T_19) wire _tails_WIRE_1 : UInt<5> connect _tails_WIRE_1, _tails_T_28 node _tails_T_29 = eq(tails[io.enq[0].bits.virt_channel_id], _tails_WIRE_1) node _tails_T_30 = bits(vc_sel, 0, 0) node _tails_T_31 = bits(vc_sel, 1, 1) node _tails_T_32 = bits(vc_sel, 2, 2) node _tails_T_33 = bits(vc_sel, 3, 3) node _tails_T_34 = bits(vc_sel, 4, 4) node _tails_T_35 = bits(vc_sel, 5, 5) node _tails_T_36 = bits(vc_sel, 6, 6) node _tails_T_37 = bits(vc_sel, 7, 7) node _tails_T_38 = bits(vc_sel, 8, 8) node _tails_T_39 = bits(vc_sel, 9, 9) node _tails_T_40 = mux(_tails_T_30, UInt<1>(0h0), UInt<1>(0h0)) node _tails_T_41 = mux(_tails_T_31, UInt<1>(0h0), UInt<1>(0h0)) node _tails_T_42 = mux(_tails_T_32, UInt<3>(0h4), UInt<1>(0h0)) node _tails_T_43 = mux(_tails_T_33, UInt<4>(0h8), UInt<1>(0h0)) node _tails_T_44 = mux(_tails_T_34, UInt<1>(0h0), UInt<1>(0h0)) node _tails_T_45 = mux(_tails_T_35, UInt<4>(0hc), UInt<1>(0h0)) node _tails_T_46 = mux(_tails_T_36, UInt<5>(0h10), UInt<1>(0h0)) node _tails_T_47 = mux(_tails_T_37, UInt<5>(0h14), UInt<1>(0h0)) node _tails_T_48 = mux(_tails_T_38, UInt<1>(0h0), UInt<1>(0h0)) node _tails_T_49 = mux(_tails_T_39, UInt<5>(0h18), UInt<1>(0h0)) node _tails_T_50 = or(_tails_T_40, _tails_T_41) node _tails_T_51 = or(_tails_T_50, _tails_T_42) node _tails_T_52 = or(_tails_T_51, _tails_T_43) node _tails_T_53 = or(_tails_T_52, _tails_T_44) node _tails_T_54 = or(_tails_T_53, _tails_T_45) node _tails_T_55 = or(_tails_T_54, _tails_T_46) node _tails_T_56 = or(_tails_T_55, _tails_T_47) node _tails_T_57 = or(_tails_T_56, _tails_T_48) node _tails_T_58 = or(_tails_T_57, _tails_T_49) wire _tails_WIRE_2 : UInt<5> connect _tails_WIRE_2, _tails_T_58 node _tails_T_59 = add(tails[io.enq[0].bits.virt_channel_id], UInt<1>(0h1)) node _tails_T_60 = tail(_tails_T_59, 1) node _tails_T_61 = mux(_tails_T_29, _tails_WIRE_2, _tails_T_60) connect tails[io.enq[0].bits.virt_channel_id], _tails_T_61 else : node _T_2 = and(io.enq[0].valid, direct_to_q) when _T_2 : node _T_3 = eq(io.enq[0].bits.virt_channel_id, UInt<1>(0h0)) when _T_3 : connect qs_0.io.enq.valid, UInt<1>(0h1) connect qs_0.io.enq.bits.payload, flit.payload connect qs_0.io.enq.bits.tail, flit.tail connect qs_0.io.enq.bits.head, flit.head node _T_4 = eq(io.enq[0].bits.virt_channel_id, UInt<1>(0h1)) when _T_4 : connect qs_1.io.enq.valid, UInt<1>(0h1) connect qs_1.io.enq.bits.payload, flit.payload connect qs_1.io.enq.bits.tail, flit.tail connect qs_1.io.enq.bits.head, flit.head node _T_5 = eq(io.enq[0].bits.virt_channel_id, UInt<2>(0h2)) when _T_5 : connect qs_2.io.enq.valid, UInt<1>(0h1) connect qs_2.io.enq.bits.payload, flit.payload connect qs_2.io.enq.bits.tail, flit.tail connect qs_2.io.enq.bits.head, flit.head node _T_6 = eq(io.enq[0].bits.virt_channel_id, UInt<2>(0h3)) when _T_6 : connect qs_3.io.enq.valid, UInt<1>(0h1) connect qs_3.io.enq.bits.payload, flit.payload connect qs_3.io.enq.bits.tail, flit.tail connect qs_3.io.enq.bits.head, flit.head node _T_7 = eq(io.enq[0].bits.virt_channel_id, UInt<3>(0h4)) when _T_7 : connect qs_4.io.enq.valid, UInt<1>(0h1) connect qs_4.io.enq.bits.payload, flit.payload connect qs_4.io.enq.bits.tail, flit.tail connect qs_4.io.enq.bits.head, flit.head node _T_8 = eq(io.enq[0].bits.virt_channel_id, UInt<3>(0h5)) when _T_8 : connect qs_5.io.enq.valid, UInt<1>(0h1) connect qs_5.io.enq.bits.payload, flit.payload connect qs_5.io.enq.bits.tail, flit.tail connect qs_5.io.enq.bits.head, flit.head node _T_9 = eq(io.enq[0].bits.virt_channel_id, UInt<3>(0h6)) when _T_9 : connect qs_6.io.enq.valid, UInt<1>(0h1) connect qs_6.io.enq.bits.payload, flit.payload connect qs_6.io.enq.bits.tail, flit.tail connect qs_6.io.enq.bits.head, flit.head node _T_10 = eq(io.enq[0].bits.virt_channel_id, UInt<3>(0h7)) when _T_10 : connect qs_7.io.enq.valid, UInt<1>(0h1) connect qs_7.io.enq.bits.payload, flit.payload connect qs_7.io.enq.bits.tail, flit.tail connect qs_7.io.enq.bits.head, flit.head node _T_11 = eq(io.enq[0].bits.virt_channel_id, UInt<4>(0h8)) when _T_11 : connect qs_8.io.enq.valid, UInt<1>(0h1) connect qs_8.io.enq.bits.payload, flit.payload connect qs_8.io.enq.bits.tail, flit.tail connect qs_8.io.enq.bits.head, flit.head node _T_12 = eq(io.enq[0].bits.virt_channel_id, UInt<4>(0h9)) when _T_12 : connect qs_9.io.enq.valid, UInt<1>(0h1) connect qs_9.io.enq.bits.payload, flit.payload connect qs_9.io.enq.bits.tail, flit.tail connect qs_9.io.enq.bits.head, flit.head node _can_to_q_T = eq(empty_0, UInt<1>(0h0)) node can_to_q_0 = and(_can_to_q_T, qs_0.io.enq.ready) node _can_to_q_T_1 = eq(empty_1, UInt<1>(0h0)) node can_to_q_1 = and(_can_to_q_T_1, qs_1.io.enq.ready) node _can_to_q_T_2 = eq(empty_2, UInt<1>(0h0)) node can_to_q_2 = and(_can_to_q_T_2, qs_2.io.enq.ready) node _can_to_q_T_3 = eq(empty_3, UInt<1>(0h0)) node can_to_q_3 = and(_can_to_q_T_3, qs_3.io.enq.ready) node _can_to_q_T_4 = eq(empty_4, UInt<1>(0h0)) node can_to_q_4 = and(_can_to_q_T_4, qs_4.io.enq.ready) node _can_to_q_T_5 = eq(empty_5, UInt<1>(0h0)) node can_to_q_5 = and(_can_to_q_T_5, qs_5.io.enq.ready) node _can_to_q_T_6 = eq(empty_6, UInt<1>(0h0)) node can_to_q_6 = and(_can_to_q_T_6, qs_6.io.enq.ready) node _can_to_q_T_7 = eq(empty_7, UInt<1>(0h0)) node can_to_q_7 = and(_can_to_q_T_7, qs_7.io.enq.ready) node _can_to_q_T_8 = eq(empty_8, UInt<1>(0h0)) node can_to_q_8 = and(_can_to_q_T_8, qs_8.io.enq.ready) node _can_to_q_T_9 = eq(empty_9, UInt<1>(0h0)) node can_to_q_9 = and(_can_to_q_T_9, qs_9.io.enq.ready) node _to_q_oh_enc_T = mux(can_to_q_9, UInt<10>(0h200), UInt<10>(0h0)) node _to_q_oh_enc_T_1 = mux(can_to_q_8, UInt<10>(0h100), _to_q_oh_enc_T) node _to_q_oh_enc_T_2 = mux(can_to_q_7, UInt<10>(0h80), _to_q_oh_enc_T_1) node _to_q_oh_enc_T_3 = mux(can_to_q_6, UInt<10>(0h40), _to_q_oh_enc_T_2) node _to_q_oh_enc_T_4 = mux(can_to_q_5, UInt<10>(0h20), _to_q_oh_enc_T_3) node _to_q_oh_enc_T_5 = mux(can_to_q_4, UInt<10>(0h10), _to_q_oh_enc_T_4) node _to_q_oh_enc_T_6 = mux(can_to_q_3, UInt<10>(0h8), _to_q_oh_enc_T_5) node _to_q_oh_enc_T_7 = mux(can_to_q_2, UInt<10>(0h4), _to_q_oh_enc_T_6) node _to_q_oh_enc_T_8 = mux(can_to_q_1, UInt<10>(0h2), _to_q_oh_enc_T_7) node to_q_oh_enc = mux(can_to_q_0, UInt<10>(0h1), _to_q_oh_enc_T_8) node to_q_oh_0 = bits(to_q_oh_enc, 0, 0) node to_q_oh_1 = bits(to_q_oh_enc, 1, 1) node to_q_oh_2 = bits(to_q_oh_enc, 2, 2) node to_q_oh_3 = bits(to_q_oh_enc, 3, 3) node to_q_oh_4 = bits(to_q_oh_enc, 4, 4) node to_q_oh_5 = bits(to_q_oh_enc, 5, 5) node to_q_oh_6 = bits(to_q_oh_enc, 6, 6) node to_q_oh_7 = bits(to_q_oh_enc, 7, 7) node to_q_oh_8 = bits(to_q_oh_enc, 8, 8) node to_q_oh_9 = bits(to_q_oh_enc, 9, 9) node to_q_lo_lo = cat(to_q_oh_1, to_q_oh_0) node to_q_lo_hi_hi = cat(to_q_oh_4, to_q_oh_3) node to_q_lo_hi = cat(to_q_lo_hi_hi, to_q_oh_2) node to_q_lo = cat(to_q_lo_hi, to_q_lo_lo) node to_q_hi_lo = cat(to_q_oh_6, to_q_oh_5) node to_q_hi_hi_hi = cat(to_q_oh_9, to_q_oh_8) node to_q_hi_hi = cat(to_q_hi_hi_hi, to_q_oh_7) node to_q_hi = cat(to_q_hi_hi, to_q_hi_lo) node _to_q_T = cat(to_q_hi, to_q_lo) node to_q_hi_1 = bits(_to_q_T, 9, 8) node to_q_lo_1 = bits(_to_q_T, 7, 0) node _to_q_T_1 = orr(to_q_hi_1) node _to_q_T_2 = or(to_q_hi_1, to_q_lo_1) node to_q_hi_2 = bits(_to_q_T_2, 7, 4) node to_q_lo_2 = bits(_to_q_T_2, 3, 0) node _to_q_T_3 = orr(to_q_hi_2) node _to_q_T_4 = or(to_q_hi_2, to_q_lo_2) node to_q_hi_3 = bits(_to_q_T_4, 3, 2) node to_q_lo_3 = bits(_to_q_T_4, 1, 0) node _to_q_T_5 = orr(to_q_hi_3) node _to_q_T_6 = or(to_q_hi_3, to_q_lo_3) node _to_q_T_7 = bits(_to_q_T_6, 1, 1) node _to_q_T_8 = cat(_to_q_T_5, _to_q_T_7) node _to_q_T_9 = cat(_to_q_T_3, _to_q_T_8) node to_q = cat(_to_q_T_1, _to_q_T_9) node _T_13 = or(can_to_q_0, can_to_q_1) node _T_14 = or(_T_13, can_to_q_2) node _T_15 = or(_T_14, can_to_q_3) node _T_16 = or(_T_15, can_to_q_4) node _T_17 = or(_T_16, can_to_q_5) node _T_18 = or(_T_17, can_to_q_6) node _T_19 = or(_T_18, can_to_q_7) node _T_20 = or(_T_19, can_to_q_8) node _T_21 = or(_T_20, can_to_q_9) when _T_21 : node _head_T = mux(to_q_oh_0, heads[0], UInt<1>(0h0)) node _head_T_1 = mux(to_q_oh_1, heads[1], UInt<1>(0h0)) node _head_T_2 = mux(to_q_oh_2, heads[2], UInt<1>(0h0)) node _head_T_3 = mux(to_q_oh_3, heads[3], UInt<1>(0h0)) node _head_T_4 = mux(to_q_oh_4, heads[4], UInt<1>(0h0)) node _head_T_5 = mux(to_q_oh_5, heads[5], UInt<1>(0h0)) node _head_T_6 = mux(to_q_oh_6, heads[6], UInt<1>(0h0)) node _head_T_7 = mux(to_q_oh_7, heads[7], UInt<1>(0h0)) node _head_T_8 = mux(to_q_oh_8, heads[8], UInt<1>(0h0)) node _head_T_9 = mux(to_q_oh_9, heads[9], UInt<1>(0h0)) node _head_T_10 = or(_head_T, _head_T_1) node _head_T_11 = or(_head_T_10, _head_T_2) node _head_T_12 = or(_head_T_11, _head_T_3) node _head_T_13 = or(_head_T_12, _head_T_4) node _head_T_14 = or(_head_T_13, _head_T_5) node _head_T_15 = or(_head_T_14, _head_T_6) node _head_T_16 = or(_head_T_15, _head_T_7) node _head_T_17 = or(_head_T_16, _head_T_8) node _head_T_18 = or(_head_T_17, _head_T_9) wire head : UInt<5> connect head, _head_T_18 node _heads_T = mux(to_q_oh_0, UInt<1>(0h0), UInt<1>(0h0)) node _heads_T_1 = mux(to_q_oh_1, UInt<2>(0h3), UInt<1>(0h0)) node _heads_T_2 = mux(to_q_oh_2, UInt<3>(0h7), UInt<1>(0h0)) node _heads_T_3 = mux(to_q_oh_3, UInt<4>(0hb), UInt<1>(0h0)) node _heads_T_4 = mux(to_q_oh_4, UInt<1>(0h0), UInt<1>(0h0)) node _heads_T_5 = mux(to_q_oh_5, UInt<4>(0hf), UInt<1>(0h0)) node _heads_T_6 = mux(to_q_oh_6, UInt<5>(0h13), UInt<1>(0h0)) node _heads_T_7 = mux(to_q_oh_7, UInt<5>(0h17), UInt<1>(0h0)) node _heads_T_8 = mux(to_q_oh_8, UInt<1>(0h0), UInt<1>(0h0)) node _heads_T_9 = mux(to_q_oh_9, UInt<5>(0h1b), UInt<1>(0h0)) node _heads_T_10 = or(_heads_T, _heads_T_1) node _heads_T_11 = or(_heads_T_10, _heads_T_2) node _heads_T_12 = or(_heads_T_11, _heads_T_3) node _heads_T_13 = or(_heads_T_12, _heads_T_4) node _heads_T_14 = or(_heads_T_13, _heads_T_5) node _heads_T_15 = or(_heads_T_14, _heads_T_6) node _heads_T_16 = or(_heads_T_15, _heads_T_7) node _heads_T_17 = or(_heads_T_16, _heads_T_8) node _heads_T_18 = or(_heads_T_17, _heads_T_9) wire _heads_WIRE_1 : UInt<5> connect _heads_WIRE_1, _heads_T_18 node _heads_T_19 = eq(head, _heads_WIRE_1) node _heads_T_20 = mux(to_q_oh_0, UInt<1>(0h0), UInt<1>(0h0)) node _heads_T_21 = mux(to_q_oh_1, UInt<1>(0h0), UInt<1>(0h0)) node _heads_T_22 = mux(to_q_oh_2, UInt<3>(0h4), UInt<1>(0h0)) node _heads_T_23 = mux(to_q_oh_3, UInt<4>(0h8), UInt<1>(0h0)) node _heads_T_24 = mux(to_q_oh_4, UInt<1>(0h0), UInt<1>(0h0)) node _heads_T_25 = mux(to_q_oh_5, UInt<4>(0hc), UInt<1>(0h0)) node _heads_T_26 = mux(to_q_oh_6, UInt<5>(0h10), UInt<1>(0h0)) node _heads_T_27 = mux(to_q_oh_7, UInt<5>(0h14), UInt<1>(0h0)) node _heads_T_28 = mux(to_q_oh_8, UInt<1>(0h0), UInt<1>(0h0)) node _heads_T_29 = mux(to_q_oh_9, UInt<5>(0h18), UInt<1>(0h0)) node _heads_T_30 = or(_heads_T_20, _heads_T_21) node _heads_T_31 = or(_heads_T_30, _heads_T_22) node _heads_T_32 = or(_heads_T_31, _heads_T_23) node _heads_T_33 = or(_heads_T_32, _heads_T_24) node _heads_T_34 = or(_heads_T_33, _heads_T_25) node _heads_T_35 = or(_heads_T_34, _heads_T_26) node _heads_T_36 = or(_heads_T_35, _heads_T_27) node _heads_T_37 = or(_heads_T_36, _heads_T_28) node _heads_T_38 = or(_heads_T_37, _heads_T_29) wire _heads_WIRE_2 : UInt<5> connect _heads_WIRE_2, _heads_T_38 node _heads_T_39 = add(head, UInt<1>(0h1)) node _heads_T_40 = tail(_heads_T_39, 1) node _heads_T_41 = mux(_heads_T_19, _heads_WIRE_2, _heads_T_40) connect heads[to_q], _heads_T_41 when to_q_oh_0 : connect qs_0.io.enq.valid, UInt<1>(0h1) read mport qs_0_io_enq_bits_MPORT = mem[head], clock connect qs_0.io.enq.bits.payload, qs_0_io_enq_bits_MPORT.payload connect qs_0.io.enq.bits.tail, qs_0_io_enq_bits_MPORT.tail connect qs_0.io.enq.bits.head, qs_0_io_enq_bits_MPORT.head when to_q_oh_1 : connect qs_1.io.enq.valid, UInt<1>(0h1) read mport qs_1_io_enq_bits_MPORT = mem[head], clock connect qs_1.io.enq.bits.payload, qs_1_io_enq_bits_MPORT.payload connect qs_1.io.enq.bits.tail, qs_1_io_enq_bits_MPORT.tail connect qs_1.io.enq.bits.head, qs_1_io_enq_bits_MPORT.head when to_q_oh_2 : connect qs_2.io.enq.valid, UInt<1>(0h1) read mport qs_2_io_enq_bits_MPORT = mem[head], clock connect qs_2.io.enq.bits.payload, qs_2_io_enq_bits_MPORT.payload connect qs_2.io.enq.bits.tail, qs_2_io_enq_bits_MPORT.tail connect qs_2.io.enq.bits.head, qs_2_io_enq_bits_MPORT.head when to_q_oh_3 : connect qs_3.io.enq.valid, UInt<1>(0h1) read mport qs_3_io_enq_bits_MPORT = mem[head], clock connect qs_3.io.enq.bits.payload, qs_3_io_enq_bits_MPORT.payload connect qs_3.io.enq.bits.tail, qs_3_io_enq_bits_MPORT.tail connect qs_3.io.enq.bits.head, qs_3_io_enq_bits_MPORT.head when to_q_oh_4 : connect qs_4.io.enq.valid, UInt<1>(0h1) read mport qs_4_io_enq_bits_MPORT = mem[head], clock connect qs_4.io.enq.bits.payload, qs_4_io_enq_bits_MPORT.payload connect qs_4.io.enq.bits.tail, qs_4_io_enq_bits_MPORT.tail connect qs_4.io.enq.bits.head, qs_4_io_enq_bits_MPORT.head when to_q_oh_5 : connect qs_5.io.enq.valid, UInt<1>(0h1) read mport qs_5_io_enq_bits_MPORT = mem[head], clock connect qs_5.io.enq.bits.payload, qs_5_io_enq_bits_MPORT.payload connect qs_5.io.enq.bits.tail, qs_5_io_enq_bits_MPORT.tail connect qs_5.io.enq.bits.head, qs_5_io_enq_bits_MPORT.head when to_q_oh_6 : connect qs_6.io.enq.valid, UInt<1>(0h1) read mport qs_6_io_enq_bits_MPORT = mem[head], clock connect qs_6.io.enq.bits.payload, qs_6_io_enq_bits_MPORT.payload connect qs_6.io.enq.bits.tail, qs_6_io_enq_bits_MPORT.tail connect qs_6.io.enq.bits.head, qs_6_io_enq_bits_MPORT.head when to_q_oh_7 : connect qs_7.io.enq.valid, UInt<1>(0h1) read mport qs_7_io_enq_bits_MPORT = mem[head], clock connect qs_7.io.enq.bits.payload, qs_7_io_enq_bits_MPORT.payload connect qs_7.io.enq.bits.tail, qs_7_io_enq_bits_MPORT.tail connect qs_7.io.enq.bits.head, qs_7_io_enq_bits_MPORT.head when to_q_oh_8 : connect qs_8.io.enq.valid, UInt<1>(0h1) read mport qs_8_io_enq_bits_MPORT = mem[head], clock connect qs_8.io.enq.bits.payload, qs_8_io_enq_bits_MPORT.payload connect qs_8.io.enq.bits.tail, qs_8_io_enq_bits_MPORT.tail connect qs_8.io.enq.bits.head, qs_8_io_enq_bits_MPORT.head when to_q_oh_9 : connect qs_9.io.enq.valid, UInt<1>(0h1) read mport qs_9_io_enq_bits_MPORT = mem[head], clock connect qs_9.io.enq.bits.payload, qs_9_io_enq_bits_MPORT.payload connect qs_9.io.enq.bits.tail, qs_9_io_enq_bits_MPORT.tail connect qs_9.io.enq.bits.head, qs_9_io_enq_bits_MPORT.head connect io.deq[0].bits, qs_0.io.deq.bits connect io.deq[0].valid, qs_0.io.deq.valid connect qs_0.io.deq.ready, io.deq[0].ready connect io.deq[1].bits, qs_1.io.deq.bits connect io.deq[1].valid, qs_1.io.deq.valid connect qs_1.io.deq.ready, io.deq[1].ready connect io.deq[2].bits, qs_2.io.deq.bits connect io.deq[2].valid, qs_2.io.deq.valid connect qs_2.io.deq.ready, io.deq[2].ready connect io.deq[3].bits, qs_3.io.deq.bits connect io.deq[3].valid, qs_3.io.deq.valid connect qs_3.io.deq.ready, io.deq[3].ready connect io.deq[4].bits, qs_4.io.deq.bits connect io.deq[4].valid, qs_4.io.deq.valid connect qs_4.io.deq.ready, io.deq[4].ready connect io.deq[5].bits, qs_5.io.deq.bits connect io.deq[5].valid, qs_5.io.deq.valid connect qs_5.io.deq.ready, io.deq[5].ready connect io.deq[6].bits, qs_6.io.deq.bits connect io.deq[6].valid, qs_6.io.deq.valid connect qs_6.io.deq.ready, io.deq[6].ready connect io.deq[7].bits, qs_7.io.deq.bits connect io.deq[7].valid, qs_7.io.deq.valid connect qs_7.io.deq.ready, io.deq[7].ready connect io.deq[8].bits, qs_8.io.deq.bits connect io.deq[8].valid, qs_8.io.deq.valid connect qs_8.io.deq.ready, io.deq[8].ready connect io.deq[9].bits, qs_9.io.deq.bits connect io.deq[9].valid, qs_9.io.deq.valid connect qs_9.io.deq.ready, io.deq[9].ready
module InputBuffer_1( // @[InputUnit.scala:49:7] input clock, // @[InputUnit.scala:49:7] input reset, // @[InputUnit.scala:49:7] input io_enq_0_valid, // @[InputUnit.scala:51:14] input io_enq_0_bits_head, // @[InputUnit.scala:51:14] input io_enq_0_bits_tail, // @[InputUnit.scala:51:14] input [72:0] io_enq_0_bits_payload, // @[InputUnit.scala:51:14] input [3:0] io_enq_0_bits_virt_channel_id, // @[InputUnit.scala:51:14] output io_deq_0_bits_head, // @[InputUnit.scala:51:14] output io_deq_0_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_0_bits_payload, // @[InputUnit.scala:51:14] input io_deq_1_ready, // @[InputUnit.scala:51:14] output io_deq_1_valid, // @[InputUnit.scala:51:14] output io_deq_1_bits_head, // @[InputUnit.scala:51:14] output io_deq_1_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_1_bits_payload, // @[InputUnit.scala:51:14] input io_deq_2_ready, // @[InputUnit.scala:51:14] output io_deq_2_valid, // @[InputUnit.scala:51:14] output io_deq_2_bits_head, // @[InputUnit.scala:51:14] output io_deq_2_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_2_bits_payload, // @[InputUnit.scala:51:14] input io_deq_3_ready, // @[InputUnit.scala:51:14] output io_deq_3_valid, // @[InputUnit.scala:51:14] output io_deq_3_bits_head, // @[InputUnit.scala:51:14] output io_deq_3_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_3_bits_payload, // @[InputUnit.scala:51:14] output io_deq_4_bits_head, // @[InputUnit.scala:51:14] output io_deq_4_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_4_bits_payload, // @[InputUnit.scala:51:14] input io_deq_5_ready, // @[InputUnit.scala:51:14] output io_deq_5_valid, // @[InputUnit.scala:51:14] output io_deq_5_bits_head, // @[InputUnit.scala:51:14] output io_deq_5_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_5_bits_payload, // @[InputUnit.scala:51:14] input io_deq_6_ready, // @[InputUnit.scala:51:14] output io_deq_6_valid, // @[InputUnit.scala:51:14] output io_deq_6_bits_head, // @[InputUnit.scala:51:14] output io_deq_6_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_6_bits_payload, // @[InputUnit.scala:51:14] input io_deq_7_ready, // @[InputUnit.scala:51:14] output io_deq_7_valid, // @[InputUnit.scala:51:14] output io_deq_7_bits_head, // @[InputUnit.scala:51:14] output io_deq_7_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_7_bits_payload, // @[InputUnit.scala:51:14] output io_deq_8_bits_head, // @[InputUnit.scala:51:14] output io_deq_8_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_8_bits_payload, // @[InputUnit.scala:51:14] input io_deq_9_ready, // @[InputUnit.scala:51:14] output io_deq_9_valid, // @[InputUnit.scala:51:14] output io_deq_9_bits_head, // @[InputUnit.scala:51:14] output io_deq_9_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_9_bits_payload // @[InputUnit.scala:51:14] ); wire _qs_9_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_8_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_7_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_6_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_5_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_4_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_3_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_2_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_1_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_0_io_enq_ready; // @[InputUnit.scala:90:49] wire [74:0] _mem_ext_R0_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R1_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R2_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R3_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R4_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R5_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R6_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R7_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R8_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R9_data; // @[InputUnit.scala:85:18] reg [4:0] heads_0; // @[InputUnit.scala:86:24] reg [4:0] heads_1; // @[InputUnit.scala:86:24] reg [4:0] heads_2; // @[InputUnit.scala:86:24] reg [4:0] heads_3; // @[InputUnit.scala:86:24] reg [4:0] heads_4; // @[InputUnit.scala:86:24] reg [4:0] heads_5; // @[InputUnit.scala:86:24] reg [4:0] heads_6; // @[InputUnit.scala:86:24] reg [4:0] heads_7; // @[InputUnit.scala:86:24] reg [4:0] heads_8; // @[InputUnit.scala:86:24] reg [4:0] heads_9; // @[InputUnit.scala:86:24] reg [4:0] tails_0; // @[InputUnit.scala:87:24] reg [4:0] tails_1; // @[InputUnit.scala:87:24] reg [4:0] tails_2; // @[InputUnit.scala:87:24] reg [4:0] tails_3; // @[InputUnit.scala:87:24] reg [4:0] tails_4; // @[InputUnit.scala:87:24] reg [4:0] tails_5; // @[InputUnit.scala:87:24] reg [4:0] tails_6; // @[InputUnit.scala:87:24] reg [4:0] tails_7; // @[InputUnit.scala:87:24] reg [4:0] tails_8; // @[InputUnit.scala:87:24] reg [4:0] tails_9; // @[InputUnit.scala:87:24] wire _tails_T_30 = io_enq_0_bits_virt_channel_id == 4'h0; // @[Mux.scala:32:36] wire _tails_T_31 = io_enq_0_bits_virt_channel_id == 4'h1; // @[Mux.scala:32:36] wire _tails_T_32 = io_enq_0_bits_virt_channel_id == 4'h2; // @[Mux.scala:32:36] wire _tails_T_33 = io_enq_0_bits_virt_channel_id == 4'h3; // @[Mux.scala:32:36] wire _tails_T_34 = io_enq_0_bits_virt_channel_id == 4'h4; // @[Mux.scala:32:36] wire _tails_T_35 = io_enq_0_bits_virt_channel_id == 4'h5; // @[Mux.scala:32:36] wire _tails_T_36 = io_enq_0_bits_virt_channel_id == 4'h6; // @[Mux.scala:32:36] wire _tails_T_37 = io_enq_0_bits_virt_channel_id == 4'h7; // @[Mux.scala:32:36] wire _tails_T_38 = io_enq_0_bits_virt_channel_id == 4'h8; // @[Mux.scala:32:36] wire _tails_T_39 = io_enq_0_bits_virt_channel_id == 4'h9; // @[Mux.scala:32:36] wire direct_to_q = (_tails_T_30 & _qs_0_io_enq_ready | _tails_T_31 & _qs_1_io_enq_ready | _tails_T_32 & _qs_2_io_enq_ready | _tails_T_33 & _qs_3_io_enq_ready | _tails_T_34 & _qs_4_io_enq_ready | _tails_T_35 & _qs_5_io_enq_ready | _tails_T_36 & _qs_6_io_enq_ready | _tails_T_37 & _qs_7_io_enq_ready | _tails_T_38 & _qs_8_io_enq_ready | _tails_T_39 & _qs_9_io_enq_ready) & (_tails_T_30 & heads_0 == tails_0 | _tails_T_31 & heads_1 == tails_1 | _tails_T_32 & heads_2 == tails_2 | _tails_T_33 & heads_3 == tails_3 | _tails_T_34 & heads_4 == tails_4 | _tails_T_35 & heads_5 == tails_5 | _tails_T_36 & heads_6 == tails_6 | _tails_T_37 & heads_7 == tails_7 | _tails_T_38 & heads_8 == tails_8 | _tails_T_39 & heads_9 == tails_9); // @[Mux.scala:30:73, :32:36] wire mem_MPORT_en = io_enq_0_valid & ~direct_to_q; // @[InputUnit.scala:96:62, :100:{27,30}] wire [15:0][4:0] _GEN = {{tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_9}, {tails_8}, {tails_7}, {tails_6}, {tails_5}, {tails_4}, {tails_3}, {tails_2}, {tails_1}, {tails_0}}; // @[InputUnit.scala:87:24, :102:16] wire _GEN_0 = io_enq_0_bits_virt_channel_id == 4'h0; // @[InputUnit.scala:103:45] wire _GEN_1 = io_enq_0_bits_virt_channel_id == 4'h1; // @[InputUnit.scala:103:45] wire _GEN_2 = io_enq_0_bits_virt_channel_id == 4'h2; // @[InputUnit.scala:103:45] wire _GEN_3 = io_enq_0_bits_virt_channel_id == 4'h3; // @[InputUnit.scala:103:45] wire _GEN_4 = io_enq_0_bits_virt_channel_id == 4'h4; // @[InputUnit.scala:103:45] wire _GEN_5 = io_enq_0_bits_virt_channel_id == 4'h5; // @[InputUnit.scala:103:45] wire _GEN_6 = io_enq_0_bits_virt_channel_id == 4'h6; // @[InputUnit.scala:103:45] wire _GEN_7 = io_enq_0_bits_virt_channel_id == 4'h7; // @[InputUnit.scala:103:45] wire _GEN_8 = io_enq_0_bits_virt_channel_id == 4'h8; // @[InputUnit.scala:103:45] wire _GEN_9 = io_enq_0_bits_virt_channel_id == 4'h9; // @[InputUnit.scala:103:45] wire _GEN_10 = io_enq_0_valid & direct_to_q; // @[InputUnit.scala:96:62, :107:34] wire can_to_q_0 = heads_0 != tails_0 & _qs_0_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_1 = heads_1 != tails_1 & _qs_1_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_2 = heads_2 != tails_2 & _qs_2_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_3 = heads_3 != tails_3 & _qs_3_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_4 = heads_4 != tails_4 & _qs_4_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_5 = heads_5 != tails_5 & _qs_5_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_6 = heads_6 != tails_6 & _qs_6_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_7 = heads_7 != tails_7 & _qs_7_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_8 = heads_8 != tails_8 & _qs_8_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_9 = heads_9 != tails_9 & _qs_9_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire [9:0] to_q_oh_enc = can_to_q_0 ? 10'h1 : can_to_q_1 ? 10'h2 : can_to_q_2 ? 10'h4 : can_to_q_3 ? 10'h8 : can_to_q_4 ? 10'h10 : can_to_q_5 ? 10'h20 : can_to_q_6 ? 10'h40 : can_to_q_7 ? 10'h80 : can_to_q_8 ? 10'h100 : {can_to_q_9, 9'h0}; // @[Mux.scala:50:70] wire _GEN_11 = can_to_q_0 | can_to_q_1 | can_to_q_2 | can_to_q_3 | can_to_q_4 | can_to_q_5 | can_to_q_6 | can_to_q_7 | can_to_q_8 | can_to_q_9; // @[package.scala:81:59] wire [4:0] head = (to_q_oh_enc[0] ? heads_0 : 5'h0) | (to_q_oh_enc[1] ? heads_1 : 5'h0) | (to_q_oh_enc[2] ? heads_2 : 5'h0) | (to_q_oh_enc[3] ? heads_3 : 5'h0) | (to_q_oh_enc[4] ? heads_4 : 5'h0) | (to_q_oh_enc[5] ? heads_5 : 5'h0) | (to_q_oh_enc[6] ? heads_6 : 5'h0) | (to_q_oh_enc[7] ? heads_7 : 5'h0) | (to_q_oh_enc[8] ? heads_8 : 5'h0) | (to_q_oh_enc[9] ? heads_9 : 5'h0); // @[OneHot.scala:83:30] wire _GEN_12 = _GEN_11 & to_q_oh_enc[0]; // @[OneHot.scala:83:30] wire _GEN_13 = _GEN_11 & to_q_oh_enc[1]; // @[OneHot.scala:83:30] wire _GEN_14 = _GEN_11 & to_q_oh_enc[2]; // @[OneHot.scala:83:30] wire _GEN_15 = _GEN_11 & to_q_oh_enc[3]; // @[OneHot.scala:83:30] wire _GEN_16 = _GEN_11 & to_q_oh_enc[4]; // @[OneHot.scala:83:30] wire _GEN_17 = _GEN_11 & to_q_oh_enc[5]; // @[OneHot.scala:83:30] wire _GEN_18 = _GEN_11 & to_q_oh_enc[6]; // @[OneHot.scala:83:30] wire _GEN_19 = _GEN_11 & to_q_oh_enc[7]; // @[OneHot.scala:83:30] wire _GEN_20 = _GEN_11 & to_q_oh_enc[8]; // @[OneHot.scala:83:30] wire _GEN_21 = _GEN_11 & to_q_oh_enc[9]; // @[OneHot.scala:83:30] wire [4:0] _tails_T_61 = _GEN[io_enq_0_bits_virt_channel_id] == ({1'h0, {1'h0, {1'h0, {2{_tails_T_31}}} | {3{_tails_T_32}}} | (_tails_T_33 ? 4'hB : 4'h0) | {4{_tails_T_35}}} | (_tails_T_36 ? 5'h13 : 5'h0) | (_tails_T_37 ? 5'h17 : 5'h0) | (_tails_T_39 ? 5'h1B : 5'h0)) ? {_tails_T_36, {_tails_T_33, _tails_T_32, 2'h0} | (_tails_T_35 ? 4'hC : 4'h0)} | (_tails_T_37 ? 5'h14 : 5'h0) | (_tails_T_39 ? 5'h18 : 5'h0) : _GEN[io_enq_0_bits_virt_channel_id] + 5'h1; // @[Mux.scala:30:73, :32:36] wire [6:0] _to_q_T_2 = {6'h0, to_q_oh_enc[9]} | to_q_oh_enc[7:1]; // @[OneHot.scala:31:18, :32:28] wire [2:0] _to_q_T_4 = _to_q_T_2[6:4] | _to_q_T_2[2:0]; // @[OneHot.scala:30:18, :31:18, :32:28] wire _to_q_T_6 = _to_q_T_4[2] | _to_q_T_4[0]; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] to_q = {|(to_q_oh_enc[9:8]), |(_to_q_T_2[6:3]), |(_to_q_T_4[2:1]), _to_q_T_6}; // @[OneHot.scala:30:18, :32:{10,14,28}] wire [4:0] _heads_T_41 = head == ({1'h0, {1'h0, {1'h0, {2{to_q_oh_enc[1]}}} | {3{to_q_oh_enc[2]}}} | (to_q_oh_enc[3] ? 4'hB : 4'h0) | {4{to_q_oh_enc[5]}}} | (to_q_oh_enc[6] ? 5'h13 : 5'h0) | (to_q_oh_enc[7] ? 5'h17 : 5'h0) | (to_q_oh_enc[9] ? 5'h1B : 5'h0)) ? {to_q_oh_enc[6], {to_q_oh_enc[3:2], 2'h0} | (to_q_oh_enc[5] ? 4'hC : 4'h0)} | (to_q_oh_enc[7] ? 5'h14 : 5'h0) | (to_q_oh_enc[9] ? 5'h18 : 5'h0) : head + 5'h1; // @[OneHot.scala:83:30] always @(posedge clock) begin // @[InputUnit.scala:49:7] if (reset) begin // @[InputUnit.scala:49:7] heads_0 <= 5'h0; // @[InputUnit.scala:86:24] heads_1 <= 5'h0; // @[InputUnit.scala:86:24] heads_2 <= 5'h4; // @[InputUnit.scala:86:24] heads_3 <= 5'h8; // @[InputUnit.scala:86:24] heads_4 <= 5'h0; // @[InputUnit.scala:86:24] heads_5 <= 5'hC; // @[InputUnit.scala:86:24] heads_6 <= 5'h10; // @[InputUnit.scala:86:24] heads_7 <= 5'h14; // @[InputUnit.scala:86:24] heads_8 <= 5'h0; // @[InputUnit.scala:86:24] heads_9 <= 5'h18; // @[InputUnit.scala:86:24] tails_0 <= 5'h0; // @[InputUnit.scala:87:24] tails_1 <= 5'h0; // @[InputUnit.scala:87:24] tails_2 <= 5'h4; // @[InputUnit.scala:87:24] tails_3 <= 5'h8; // @[InputUnit.scala:87:24] tails_4 <= 5'h0; // @[InputUnit.scala:87:24] tails_5 <= 5'hC; // @[InputUnit.scala:87:24] tails_6 <= 5'h10; // @[InputUnit.scala:87:24] tails_7 <= 5'h14; // @[InputUnit.scala:87:24] tails_8 <= 5'h0; // @[InputUnit.scala:87:24] tails_9 <= 5'h18; // @[InputUnit.scala:87:24] end else begin // @[InputUnit.scala:49:7] if (_GEN_11 & {to_q_oh_enc[9:8], |(_to_q_T_2[6:3]), |(_to_q_T_4[2:1]), _to_q_T_6} == 5'h0) // @[OneHot.scala:30:18, :32:{10,14,28}] heads_0 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27] if (_GEN_11 & to_q == 4'h1) // @[OneHot.scala:32:10] heads_1 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27] if (_GEN_11 & to_q == 4'h2) // @[OneHot.scala:32:10] heads_2 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27] if (_GEN_11 & to_q == 4'h3) // @[OneHot.scala:32:10] heads_3 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27] if (_GEN_11 & to_q == 4'h4) // @[OneHot.scala:32:10] heads_4 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27] if (_GEN_11 & to_q == 4'h5) // @[OneHot.scala:32:10] heads_5 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27] if (_GEN_11 & to_q == 4'h6) // @[OneHot.scala:32:10] heads_6 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27] if (_GEN_11 & to_q == 4'h7) // @[OneHot.scala:32:10] heads_7 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27] if (_GEN_11 & to_q == 4'h8) // @[OneHot.scala:32:10] heads_8 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27] if (_GEN_11 & to_q == 4'h9) // @[OneHot.scala:32:10] heads_9 <= _heads_T_41; // @[InputUnit.scala:86:24, :122:27] if (mem_MPORT_en & _GEN_0) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_0 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_1) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_1 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_2) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_2 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_3) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_3 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_4) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_4 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_5) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_5 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_6) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_6 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_7) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_7 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_8) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_8 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_9) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_9 <= _tails_T_61; // @[InputUnit.scala:87:24, :103:51] end always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module RoundRawFNToRecFN_e8_s24_5 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_5 connect roundAnyRawFNToRecFN.io.invalidExc, io.invalidExc connect roundAnyRawFNToRecFN.io.infiniteExc, io.infiniteExc connect roundAnyRawFNToRecFN.io.in.sig, io.in.sig connect roundAnyRawFNToRecFN.io.in.sExp, io.in.sExp connect roundAnyRawFNToRecFN.io.in.sign, io.in.sign connect roundAnyRawFNToRecFN.io.in.isZero, io.in.isZero connect roundAnyRawFNToRecFN.io.in.isInf, io.in.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, io.in.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags
module RoundRawFNToRecFN_e8_s24_5( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_infiniteExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:299:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_infiniteExc_0 = io_infiniteExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_5 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_infiniteExc (io_infiniteExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_roundingMode (io_roundingMode_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_3 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_7 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0
module AsyncResetSynchronizerShiftReg_w1_d3_i0_3( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_7 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module ChipTop : output auto : { } output uart_0 : { txd : UInt<1>, flip rxd : UInt<1>} output tl_slave : { } output axi4_mem_0 : { clock : Clock, bits : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<7>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<7>, resp : UInt<2>, user : { }, echo : { }}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<7>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<7>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { }, last : UInt<1>}}}} output axi4_mem_1 : { clock : Clock, bits : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<7>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<7>, resp : UInt<2>, user : { }, echo : { }}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<7>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<7>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { }, last : UInt<1>}}}} output axi4_mem_2 : { clock : Clock, bits : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<7>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<7>, resp : UInt<2>, user : { }, echo : { }}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<7>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<7>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { }, last : UInt<1>}}}} output axi4_mem_3 : { clock : Clock, bits : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<7>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<7>, resp : UInt<2>, user : { }, echo : { }}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<7>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<7>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { }, last : UInt<1>}}}} input custom_boot : UInt<1> output jtag : { flip TCK : Clock, flip TMS : UInt<1>, flip TDI : UInt<1>, TDO : UInt<1>} input reset_io : AsyncReset input clock_uncore : Clock output clock_tap : Clock output serial_tl_0 : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}, flip clock_in : Clock} wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst system of DigitalTop wire clockSinkNodeIn : { clock : Clock, reset : Reset} invalidate clockSinkNodeIn.reset invalidate clockSinkNodeIn.clock wire clockSinkNodeIn_1 : { clock : Clock, reset : Reset} invalidate clockSinkNodeIn_1.reset invalidate clockSinkNodeIn_1.clock wire clockGroupAggNodeOut : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}} invalidate clockGroupAggNodeOut.member.allClocks_uncore.reset invalidate clockGroupAggNodeOut.member.allClocks_uncore.clock wire clockGroupAggNodeIn : { member : { fake_uncore : { clock : Clock, reset : Reset}}} invalidate clockGroupAggNodeIn.member.fake_uncore.reset invalidate clockGroupAggNodeIn.member.fake_uncore.clock wire clockGroupsSourceNodeOut : { member : { fake_uncore : { clock : Clock, reset : Reset}}} invalidate clockGroupsSourceNodeOut.member.fake_uncore.reset invalidate clockGroupsSourceNodeOut.member.fake_uncore.clock connect clockSinkNodeIn_1, system.auto.cbus_fixedClockNode_anon_out connect clockSinkNodeIn, system.auto.mbus_fixedClockNode_anon_out connect system.auto.chipyard_prcictrl_domain_reset_setter_clock_in, clockGroupAggNodeOut connect clockGroupAggNodeIn, clockGroupsSourceNodeOut node _T = bits(uart_0.rxd, 0, 0) inst iocell_uart_0_rxd of GenericDigitalInIOCell connect iocell_uart_0_rxd.pad, _T connect iocell_uart_0_rxd.ie, UInt<1>(0h1) connect system.uart_0.rxd, iocell_uart_0_rxd.i node _T_1 = bits(system.uart_0.txd, 0, 0) inst iocell_uart_0_txd of GenericDigitalOutIOCell connect iocell_uart_0_txd.o, _T_1 connect iocell_uart_0_txd.oe, UInt<1>(0h1) connect uart_0.txd, iocell_uart_0_txd.pad connect tl_slave, system.mem_tl connect system.mem_axi4.`0`.r, axi4_mem_0.bits.r connect axi4_mem_0.bits.ar.bits, system.mem_axi4.`0`.ar.bits connect axi4_mem_0.bits.ar.valid, system.mem_axi4.`0`.ar.valid connect system.mem_axi4.`0`.ar.ready, axi4_mem_0.bits.ar.ready connect system.mem_axi4.`0`.b, axi4_mem_0.bits.b connect axi4_mem_0.bits.w.bits, system.mem_axi4.`0`.w.bits connect axi4_mem_0.bits.w.valid, system.mem_axi4.`0`.w.valid connect system.mem_axi4.`0`.w.ready, axi4_mem_0.bits.w.ready connect axi4_mem_0.bits.aw.bits, system.mem_axi4.`0`.aw.bits connect axi4_mem_0.bits.aw.valid, system.mem_axi4.`0`.aw.valid connect system.mem_axi4.`0`.aw.ready, axi4_mem_0.bits.aw.ready connect axi4_mem_0.clock, clockSinkNodeIn.clock connect system.mem_axi4.`1`.r, axi4_mem_1.bits.r connect axi4_mem_1.bits.ar.bits, system.mem_axi4.`1`.ar.bits connect axi4_mem_1.bits.ar.valid, system.mem_axi4.`1`.ar.valid connect system.mem_axi4.`1`.ar.ready, axi4_mem_1.bits.ar.ready connect system.mem_axi4.`1`.b, axi4_mem_1.bits.b connect axi4_mem_1.bits.w.bits, system.mem_axi4.`1`.w.bits connect axi4_mem_1.bits.w.valid, system.mem_axi4.`1`.w.valid connect system.mem_axi4.`1`.w.ready, axi4_mem_1.bits.w.ready connect axi4_mem_1.bits.aw.bits, system.mem_axi4.`1`.aw.bits connect axi4_mem_1.bits.aw.valid, system.mem_axi4.`1`.aw.valid connect system.mem_axi4.`1`.aw.ready, axi4_mem_1.bits.aw.ready connect axi4_mem_1.clock, clockSinkNodeIn.clock connect system.mem_axi4.`2`.r, axi4_mem_2.bits.r connect axi4_mem_2.bits.ar.bits, system.mem_axi4.`2`.ar.bits connect axi4_mem_2.bits.ar.valid, system.mem_axi4.`2`.ar.valid connect system.mem_axi4.`2`.ar.ready, axi4_mem_2.bits.ar.ready connect system.mem_axi4.`2`.b, axi4_mem_2.bits.b connect axi4_mem_2.bits.w.bits, system.mem_axi4.`2`.w.bits connect axi4_mem_2.bits.w.valid, system.mem_axi4.`2`.w.valid connect system.mem_axi4.`2`.w.ready, axi4_mem_2.bits.w.ready connect axi4_mem_2.bits.aw.bits, system.mem_axi4.`2`.aw.bits connect axi4_mem_2.bits.aw.valid, system.mem_axi4.`2`.aw.valid connect system.mem_axi4.`2`.aw.ready, axi4_mem_2.bits.aw.ready connect axi4_mem_2.clock, clockSinkNodeIn.clock connect system.mem_axi4.`3`.r, axi4_mem_3.bits.r connect axi4_mem_3.bits.ar.bits, system.mem_axi4.`3`.ar.bits connect axi4_mem_3.bits.ar.valid, system.mem_axi4.`3`.ar.valid connect system.mem_axi4.`3`.ar.ready, axi4_mem_3.bits.ar.ready connect system.mem_axi4.`3`.b, axi4_mem_3.bits.b connect axi4_mem_3.bits.w.bits, system.mem_axi4.`3`.w.bits connect axi4_mem_3.bits.w.valid, system.mem_axi4.`3`.w.valid connect system.mem_axi4.`3`.w.ready, axi4_mem_3.bits.w.ready connect axi4_mem_3.bits.aw.bits, system.mem_axi4.`3`.aw.bits connect axi4_mem_3.bits.aw.valid, system.mem_axi4.`3`.aw.valid connect system.mem_axi4.`3`.aw.ready, axi4_mem_3.bits.aw.ready connect axi4_mem_3.clock, clockSinkNodeIn.clock node _T_2 = bits(custom_boot, 0, 0) inst iocell_custom_boot of GenericDigitalInIOCell_1 connect iocell_custom_boot.pad, _T_2 connect iocell_custom_boot.ie, UInt<1>(0h1) connect system.custom_boot, iocell_custom_boot.i node _system_resetctrl_hartIsInReset_0_T = asUInt(clockSinkNodeIn_1.reset) connect system.resetctrl.hartIsInReset[0], _system_resetctrl_hartIsInReset_0_T node _system_debug_systemjtag_reset_T = asUInt(clockSinkNodeIn_1.reset) inst system_debug_systemjtag_reset_catcher of ResetCatchAndSync_d3_3 connect system_debug_systemjtag_reset_catcher.clock, system.debug.systemjtag.jtag.TCK connect system_debug_systemjtag_reset_catcher.reset, _system_debug_systemjtag_reset_T wire _system_debug_systemjtag_reset_catcher_io_psd_WIRE : { test_mode : UInt<1>, test_mode_reset : UInt<1>} connect _system_debug_systemjtag_reset_catcher_io_psd_WIRE.test_mode_reset, UInt<1>(0h0) connect _system_debug_systemjtag_reset_catcher_io_psd_WIRE.test_mode, UInt<1>(0h0) wire _system_debug_systemjtag_reset_catcher_io_psd_WIRE_1 : { test_mode : UInt<1>, test_mode_reset : UInt<1>} connect _system_debug_systemjtag_reset_catcher_io_psd_WIRE_1, _system_debug_systemjtag_reset_catcher_io_psd_WIRE connect system_debug_systemjtag_reset_catcher.io.psd, _system_debug_systemjtag_reset_catcher_io_psd_WIRE_1 connect system.debug.systemjtag.reset, system_debug_systemjtag_reset_catcher.io.sync_reset connect system.debug.systemjtag.mfr_id, UInt<11>(0h0) connect system.debug.systemjtag.part_number, UInt<16>(0h0) connect system.debug.systemjtag.version, UInt<4>(0h0) node _dmi_reset_T = asUInt(system.debug.systemjtag.reset) node _dmi_reset_T_1 = or(UInt<1>(0h0), _dmi_reset_T) node dmi_reset = or(_dmi_reset_T_1, UInt<1>(0h0)) wire debug_reset : UInt<1> inst debug_reset_syncd_debug_reset_sync of AsyncResetSynchronizerShiftReg_w1_d3_i0_117 connect debug_reset_syncd_debug_reset_sync.clock, clockSinkNodeIn_1.clock connect debug_reset_syncd_debug_reset_sync.reset, dmi_reset connect debug_reset_syncd_debug_reset_sync.io.d, UInt<1>(0h1) wire _debug_reset_syncd_WIRE : UInt<1> connect _debug_reset_syncd_WIRE, debug_reset_syncd_debug_reset_sync.io.q node debug_reset_syncd = not(_debug_reset_syncd_WIRE) connect debug_reset, debug_reset_syncd node _T_3 = asAsyncReset(debug_reset) inst dmactiveAck_dmactiveAck of ResetSynchronizerShiftReg_w1_d3_i0 connect dmactiveAck_dmactiveAck.clock, clockSinkNodeIn_1.clock connect dmactiveAck_dmactiveAck.reset, _T_3 connect dmactiveAck_dmactiveAck.io.d, system.debug.dmactive wire dmactiveAck : UInt<1> connect dmactiveAck, dmactiveAck_dmactiveAck.io.q regreset clock_en : UInt<1>, clockSinkNodeIn_1.clock, _T_3, UInt<1>(0h1) connect clock_en, dmactiveAck inst gated_clock_debug_clock_gate of EICG_wrapper connect gated_clock_debug_clock_gate.in, clockSinkNodeIn_1.clock connect gated_clock_debug_clock_gate.test_en, UInt<1>(0h0) connect gated_clock_debug_clock_gate.en, clock_en connect system.debug.clock, gated_clock_debug_clock_gate.out connect system.debug.reset, debug_reset connect system.debug.dmactiveAck, dmactiveAck wire jtag_wire : { flip TCK : Clock, flip TMS : UInt<1>, flip TDI : UInt<1>, TDO : UInt<1>} connect system.debug.systemjtag.jtag.TCK, jtag_wire.TCK connect system.debug.systemjtag.jtag.TMS, jtag_wire.TMS connect system.debug.systemjtag.jtag.TDI, jtag_wire.TDI connect jtag_wire.TDO, system.debug.systemjtag.jtag.TDO.data node _T_4 = bits(jtag_wire.TDO, 0, 0) inst iocell_jtag_TDO of GenericDigitalOutIOCell_1 connect iocell_jtag_TDO.o, _T_4 connect iocell_jtag_TDO.oe, UInt<1>(0h1) connect jtag.TDO, iocell_jtag_TDO.pad node _T_5 = bits(jtag.TDI, 0, 0) inst iocell_jtag_TDI of GenericDigitalInIOCell_2 connect iocell_jtag_TDI.pad, _T_5 connect iocell_jtag_TDI.ie, UInt<1>(0h1) connect jtag_wire.TDI, iocell_jtag_TDI.i node _T_6 = bits(jtag.TMS, 0, 0) inst iocell_jtag_TMS of GenericDigitalInIOCell_3 connect iocell_jtag_TMS.pad, _T_6 connect iocell_jtag_TMS.ie, UInt<1>(0h1) connect jtag_wire.TMS, iocell_jtag_TMS.i inst iocell_jtag_TCK of GenericDigitalInIOCell_4 node _jtag_wire_TCK_T = asClock(iocell_jtag_TCK.i) connect jtag_wire.TCK, _jtag_wire_TCK_T connect iocell_jtag_TCK.ie, UInt<1>(0h1) node _iocell_jtag_TCK_io_pad_T = asUInt(jtag.TCK) node _iocell_jtag_TCK_io_pad_T_1 = bits(_iocell_jtag_TCK_io_pad_T, 0, 0) connect iocell_jtag_TCK.pad, _iocell_jtag_TCK_io_pad_T_1 connect clockGroupAggNodeOut.member.allClocks_uncore.clock, clock_uncore connect clockGroupAggNodeOut.member.allClocks_uncore.reset, reset_io inst iocell_clock_tap of GenericDigitalOutIOCell_2 node _iocell_clock_tap_io_o_T = asUInt(system.clock_tap) node _iocell_clock_tap_io_o_T_1 = bits(_iocell_clock_tap_io_o_T, 0, 0) connect iocell_clock_tap.o, _iocell_clock_tap_io_o_T_1 connect iocell_clock_tap.oe, UInt<1>(0h1) node _clock_tap_T = asClock(iocell_clock_tap.pad) connect clock_tap, _clock_tap_T inst iocell_serial_tl_0_clock_in of GenericDigitalInIOCell_5 node _system_serial_tl_0_clock_in_T = asClock(iocell_serial_tl_0_clock_in.i) connect system.serial_tl_0.clock_in, _system_serial_tl_0_clock_in_T connect iocell_serial_tl_0_clock_in.ie, UInt<1>(0h1) node _iocell_serial_tl_0_clock_in_io_pad_T = asUInt(serial_tl_0.clock_in) node _iocell_serial_tl_0_clock_in_io_pad_T_1 = bits(_iocell_serial_tl_0_clock_in_io_pad_T, 0, 0) connect iocell_serial_tl_0_clock_in.pad, _iocell_serial_tl_0_clock_in_io_pad_T_1 node _T_7 = bits(system.serial_tl_0.out.bits.phit, 0, 0) node _T_8 = bits(system.serial_tl_0.out.bits.phit, 1, 1) node _T_9 = bits(system.serial_tl_0.out.bits.phit, 2, 2) node _T_10 = bits(system.serial_tl_0.out.bits.phit, 3, 3) node _T_11 = bits(system.serial_tl_0.out.bits.phit, 4, 4) node _T_12 = bits(system.serial_tl_0.out.bits.phit, 5, 5) node _T_13 = bits(system.serial_tl_0.out.bits.phit, 6, 6) node _T_14 = bits(system.serial_tl_0.out.bits.phit, 7, 7) node _T_15 = bits(system.serial_tl_0.out.bits.phit, 8, 8) node _T_16 = bits(system.serial_tl_0.out.bits.phit, 9, 9) node _T_17 = bits(system.serial_tl_0.out.bits.phit, 10, 10) node _T_18 = bits(system.serial_tl_0.out.bits.phit, 11, 11) node _T_19 = bits(system.serial_tl_0.out.bits.phit, 12, 12) node _T_20 = bits(system.serial_tl_0.out.bits.phit, 13, 13) node _T_21 = bits(system.serial_tl_0.out.bits.phit, 14, 14) node _T_22 = bits(system.serial_tl_0.out.bits.phit, 15, 15) node _T_23 = bits(system.serial_tl_0.out.bits.phit, 16, 16) node _T_24 = bits(system.serial_tl_0.out.bits.phit, 17, 17) node _T_25 = bits(system.serial_tl_0.out.bits.phit, 18, 18) node _T_26 = bits(system.serial_tl_0.out.bits.phit, 19, 19) node _T_27 = bits(system.serial_tl_0.out.bits.phit, 20, 20) node _T_28 = bits(system.serial_tl_0.out.bits.phit, 21, 21) node _T_29 = bits(system.serial_tl_0.out.bits.phit, 22, 22) node _T_30 = bits(system.serial_tl_0.out.bits.phit, 23, 23) node _T_31 = bits(system.serial_tl_0.out.bits.phit, 24, 24) node _T_32 = bits(system.serial_tl_0.out.bits.phit, 25, 25) node _T_33 = bits(system.serial_tl_0.out.bits.phit, 26, 26) node _T_34 = bits(system.serial_tl_0.out.bits.phit, 27, 27) node _T_35 = bits(system.serial_tl_0.out.bits.phit, 28, 28) node _T_36 = bits(system.serial_tl_0.out.bits.phit, 29, 29) node _T_37 = bits(system.serial_tl_0.out.bits.phit, 30, 30) node _T_38 = bits(system.serial_tl_0.out.bits.phit, 31, 31) inst iocell_serial_tl_0_out_bits_phit of GenericDigitalOutIOCell_3 connect iocell_serial_tl_0_out_bits_phit.o, _T_7 connect iocell_serial_tl_0_out_bits_phit.oe, UInt<1>(0h1) inst iocell_serial_tl_0_out_bits_phit_1 of GenericDigitalOutIOCell_4 connect iocell_serial_tl_0_out_bits_phit_1.o, _T_8 connect iocell_serial_tl_0_out_bits_phit_1.oe, UInt<1>(0h1) inst iocell_serial_tl_0_out_bits_phit_2 of GenericDigitalOutIOCell_5 connect iocell_serial_tl_0_out_bits_phit_2.o, _T_9 connect iocell_serial_tl_0_out_bits_phit_2.oe, UInt<1>(0h1) inst iocell_serial_tl_0_out_bits_phit_3 of GenericDigitalOutIOCell_6 connect iocell_serial_tl_0_out_bits_phit_3.o, _T_10 connect iocell_serial_tl_0_out_bits_phit_3.oe, UInt<1>(0h1) inst iocell_serial_tl_0_out_bits_phit_4 of GenericDigitalOutIOCell_7 connect iocell_serial_tl_0_out_bits_phit_4.o, _T_11 connect iocell_serial_tl_0_out_bits_phit_4.oe, UInt<1>(0h1) inst iocell_serial_tl_0_out_bits_phit_5 of GenericDigitalOutIOCell_8 connect iocell_serial_tl_0_out_bits_phit_5.o, _T_12 connect iocell_serial_tl_0_out_bits_phit_5.oe, UInt<1>(0h1) inst iocell_serial_tl_0_out_bits_phit_6 of GenericDigitalOutIOCell_9 connect iocell_serial_tl_0_out_bits_phit_6.o, _T_13 connect iocell_serial_tl_0_out_bits_phit_6.oe, UInt<1>(0h1) inst iocell_serial_tl_0_out_bits_phit_7 of GenericDigitalOutIOCell_10 connect iocell_serial_tl_0_out_bits_phit_7.o, _T_14 connect iocell_serial_tl_0_out_bits_phit_7.oe, UInt<1>(0h1) inst iocell_serial_tl_0_out_bits_phit_8 of GenericDigitalOutIOCell_11 connect iocell_serial_tl_0_out_bits_phit_8.o, _T_15 connect iocell_serial_tl_0_out_bits_phit_8.oe, UInt<1>(0h1) inst iocell_serial_tl_0_out_bits_phit_9 of GenericDigitalOutIOCell_12 connect iocell_serial_tl_0_out_bits_phit_9.o, _T_16 connect iocell_serial_tl_0_out_bits_phit_9.oe, UInt<1>(0h1) inst iocell_serial_tl_0_out_bits_phit_10 of GenericDigitalOutIOCell_13 connect iocell_serial_tl_0_out_bits_phit_10.o, _T_17 connect iocell_serial_tl_0_out_bits_phit_10.oe, UInt<1>(0h1) inst iocell_serial_tl_0_out_bits_phit_11 of GenericDigitalOutIOCell_14 connect iocell_serial_tl_0_out_bits_phit_11.o, _T_18 connect iocell_serial_tl_0_out_bits_phit_11.oe, UInt<1>(0h1) inst iocell_serial_tl_0_out_bits_phit_12 of GenericDigitalOutIOCell_15 connect iocell_serial_tl_0_out_bits_phit_12.o, _T_19 connect iocell_serial_tl_0_out_bits_phit_12.oe, UInt<1>(0h1) inst iocell_serial_tl_0_out_bits_phit_13 of GenericDigitalOutIOCell_16 connect iocell_serial_tl_0_out_bits_phit_13.o, _T_20 connect iocell_serial_tl_0_out_bits_phit_13.oe, UInt<1>(0h1) inst iocell_serial_tl_0_out_bits_phit_14 of GenericDigitalOutIOCell_17 connect iocell_serial_tl_0_out_bits_phit_14.o, _T_21 connect iocell_serial_tl_0_out_bits_phit_14.oe, UInt<1>(0h1) inst iocell_serial_tl_0_out_bits_phit_15 of GenericDigitalOutIOCell_18 connect iocell_serial_tl_0_out_bits_phit_15.o, _T_22 connect iocell_serial_tl_0_out_bits_phit_15.oe, UInt<1>(0h1) inst iocell_serial_tl_0_out_bits_phit_16 of GenericDigitalOutIOCell_19 connect iocell_serial_tl_0_out_bits_phit_16.o, _T_23 connect iocell_serial_tl_0_out_bits_phit_16.oe, UInt<1>(0h1) inst iocell_serial_tl_0_out_bits_phit_17 of GenericDigitalOutIOCell_20 connect iocell_serial_tl_0_out_bits_phit_17.o, _T_24 connect iocell_serial_tl_0_out_bits_phit_17.oe, UInt<1>(0h1) inst iocell_serial_tl_0_out_bits_phit_18 of GenericDigitalOutIOCell_21 connect iocell_serial_tl_0_out_bits_phit_18.o, _T_25 connect iocell_serial_tl_0_out_bits_phit_18.oe, UInt<1>(0h1) inst iocell_serial_tl_0_out_bits_phit_19 of GenericDigitalOutIOCell_22 connect iocell_serial_tl_0_out_bits_phit_19.o, _T_26 connect iocell_serial_tl_0_out_bits_phit_19.oe, UInt<1>(0h1) inst iocell_serial_tl_0_out_bits_phit_20 of GenericDigitalOutIOCell_23 connect iocell_serial_tl_0_out_bits_phit_20.o, _T_27 connect iocell_serial_tl_0_out_bits_phit_20.oe, UInt<1>(0h1) inst iocell_serial_tl_0_out_bits_phit_21 of GenericDigitalOutIOCell_24 connect iocell_serial_tl_0_out_bits_phit_21.o, _T_28 connect iocell_serial_tl_0_out_bits_phit_21.oe, UInt<1>(0h1) inst iocell_serial_tl_0_out_bits_phit_22 of GenericDigitalOutIOCell_25 connect iocell_serial_tl_0_out_bits_phit_22.o, _T_29 connect iocell_serial_tl_0_out_bits_phit_22.oe, UInt<1>(0h1) inst iocell_serial_tl_0_out_bits_phit_23 of GenericDigitalOutIOCell_26 connect iocell_serial_tl_0_out_bits_phit_23.o, _T_30 connect iocell_serial_tl_0_out_bits_phit_23.oe, UInt<1>(0h1) inst iocell_serial_tl_0_out_bits_phit_24 of GenericDigitalOutIOCell_27 connect iocell_serial_tl_0_out_bits_phit_24.o, _T_31 connect iocell_serial_tl_0_out_bits_phit_24.oe, UInt<1>(0h1) inst iocell_serial_tl_0_out_bits_phit_25 of GenericDigitalOutIOCell_28 connect iocell_serial_tl_0_out_bits_phit_25.o, _T_32 connect iocell_serial_tl_0_out_bits_phit_25.oe, UInt<1>(0h1) inst iocell_serial_tl_0_out_bits_phit_26 of GenericDigitalOutIOCell_29 connect iocell_serial_tl_0_out_bits_phit_26.o, _T_33 connect iocell_serial_tl_0_out_bits_phit_26.oe, UInt<1>(0h1) inst iocell_serial_tl_0_out_bits_phit_27 of GenericDigitalOutIOCell_30 connect iocell_serial_tl_0_out_bits_phit_27.o, _T_34 connect iocell_serial_tl_0_out_bits_phit_27.oe, UInt<1>(0h1) inst iocell_serial_tl_0_out_bits_phit_28 of GenericDigitalOutIOCell_31 connect iocell_serial_tl_0_out_bits_phit_28.o, _T_35 connect iocell_serial_tl_0_out_bits_phit_28.oe, UInt<1>(0h1) inst iocell_serial_tl_0_out_bits_phit_29 of GenericDigitalOutIOCell_32 connect iocell_serial_tl_0_out_bits_phit_29.o, _T_36 connect iocell_serial_tl_0_out_bits_phit_29.oe, UInt<1>(0h1) inst iocell_serial_tl_0_out_bits_phit_30 of GenericDigitalOutIOCell_33 connect iocell_serial_tl_0_out_bits_phit_30.o, _T_37 connect iocell_serial_tl_0_out_bits_phit_30.oe, UInt<1>(0h1) inst iocell_serial_tl_0_out_bits_phit_31 of GenericDigitalOutIOCell_34 connect iocell_serial_tl_0_out_bits_phit_31.o, _T_38 connect iocell_serial_tl_0_out_bits_phit_31.oe, UInt<1>(0h1) node serial_tl_0_out_bits_phit_lo_lo_lo_lo = cat(iocell_serial_tl_0_out_bits_phit_1.pad, iocell_serial_tl_0_out_bits_phit.pad) node serial_tl_0_out_bits_phit_lo_lo_lo_hi = cat(iocell_serial_tl_0_out_bits_phit_3.pad, iocell_serial_tl_0_out_bits_phit_2.pad) node serial_tl_0_out_bits_phit_lo_lo_lo = cat(serial_tl_0_out_bits_phit_lo_lo_lo_hi, serial_tl_0_out_bits_phit_lo_lo_lo_lo) node serial_tl_0_out_bits_phit_lo_lo_hi_lo = cat(iocell_serial_tl_0_out_bits_phit_5.pad, iocell_serial_tl_0_out_bits_phit_4.pad) node serial_tl_0_out_bits_phit_lo_lo_hi_hi = cat(iocell_serial_tl_0_out_bits_phit_7.pad, iocell_serial_tl_0_out_bits_phit_6.pad) node serial_tl_0_out_bits_phit_lo_lo_hi = cat(serial_tl_0_out_bits_phit_lo_lo_hi_hi, serial_tl_0_out_bits_phit_lo_lo_hi_lo) node serial_tl_0_out_bits_phit_lo_lo = cat(serial_tl_0_out_bits_phit_lo_lo_hi, serial_tl_0_out_bits_phit_lo_lo_lo) node serial_tl_0_out_bits_phit_lo_hi_lo_lo = cat(iocell_serial_tl_0_out_bits_phit_9.pad, iocell_serial_tl_0_out_bits_phit_8.pad) node serial_tl_0_out_bits_phit_lo_hi_lo_hi = cat(iocell_serial_tl_0_out_bits_phit_11.pad, iocell_serial_tl_0_out_bits_phit_10.pad) node serial_tl_0_out_bits_phit_lo_hi_lo = cat(serial_tl_0_out_bits_phit_lo_hi_lo_hi, serial_tl_0_out_bits_phit_lo_hi_lo_lo) node serial_tl_0_out_bits_phit_lo_hi_hi_lo = cat(iocell_serial_tl_0_out_bits_phit_13.pad, iocell_serial_tl_0_out_bits_phit_12.pad) node serial_tl_0_out_bits_phit_lo_hi_hi_hi = cat(iocell_serial_tl_0_out_bits_phit_15.pad, iocell_serial_tl_0_out_bits_phit_14.pad) node serial_tl_0_out_bits_phit_lo_hi_hi = cat(serial_tl_0_out_bits_phit_lo_hi_hi_hi, serial_tl_0_out_bits_phit_lo_hi_hi_lo) node serial_tl_0_out_bits_phit_lo_hi = cat(serial_tl_0_out_bits_phit_lo_hi_hi, serial_tl_0_out_bits_phit_lo_hi_lo) node serial_tl_0_out_bits_phit_lo = cat(serial_tl_0_out_bits_phit_lo_hi, serial_tl_0_out_bits_phit_lo_lo) node serial_tl_0_out_bits_phit_hi_lo_lo_lo = cat(iocell_serial_tl_0_out_bits_phit_17.pad, iocell_serial_tl_0_out_bits_phit_16.pad) node serial_tl_0_out_bits_phit_hi_lo_lo_hi = cat(iocell_serial_tl_0_out_bits_phit_19.pad, iocell_serial_tl_0_out_bits_phit_18.pad) node serial_tl_0_out_bits_phit_hi_lo_lo = cat(serial_tl_0_out_bits_phit_hi_lo_lo_hi, serial_tl_0_out_bits_phit_hi_lo_lo_lo) node serial_tl_0_out_bits_phit_hi_lo_hi_lo = cat(iocell_serial_tl_0_out_bits_phit_21.pad, iocell_serial_tl_0_out_bits_phit_20.pad) node serial_tl_0_out_bits_phit_hi_lo_hi_hi = cat(iocell_serial_tl_0_out_bits_phit_23.pad, iocell_serial_tl_0_out_bits_phit_22.pad) node serial_tl_0_out_bits_phit_hi_lo_hi = cat(serial_tl_0_out_bits_phit_hi_lo_hi_hi, serial_tl_0_out_bits_phit_hi_lo_hi_lo) node serial_tl_0_out_bits_phit_hi_lo = cat(serial_tl_0_out_bits_phit_hi_lo_hi, serial_tl_0_out_bits_phit_hi_lo_lo) node serial_tl_0_out_bits_phit_hi_hi_lo_lo = cat(iocell_serial_tl_0_out_bits_phit_25.pad, iocell_serial_tl_0_out_bits_phit_24.pad) node serial_tl_0_out_bits_phit_hi_hi_lo_hi = cat(iocell_serial_tl_0_out_bits_phit_27.pad, iocell_serial_tl_0_out_bits_phit_26.pad) node serial_tl_0_out_bits_phit_hi_hi_lo = cat(serial_tl_0_out_bits_phit_hi_hi_lo_hi, serial_tl_0_out_bits_phit_hi_hi_lo_lo) node serial_tl_0_out_bits_phit_hi_hi_hi_lo = cat(iocell_serial_tl_0_out_bits_phit_29.pad, iocell_serial_tl_0_out_bits_phit_28.pad) node serial_tl_0_out_bits_phit_hi_hi_hi_hi = cat(iocell_serial_tl_0_out_bits_phit_31.pad, iocell_serial_tl_0_out_bits_phit_30.pad) node serial_tl_0_out_bits_phit_hi_hi_hi = cat(serial_tl_0_out_bits_phit_hi_hi_hi_hi, serial_tl_0_out_bits_phit_hi_hi_hi_lo) node serial_tl_0_out_bits_phit_hi_hi = cat(serial_tl_0_out_bits_phit_hi_hi_hi, serial_tl_0_out_bits_phit_hi_hi_lo) node serial_tl_0_out_bits_phit_hi = cat(serial_tl_0_out_bits_phit_hi_hi, serial_tl_0_out_bits_phit_hi_lo) node _serial_tl_0_out_bits_phit_T = cat(serial_tl_0_out_bits_phit_hi, serial_tl_0_out_bits_phit_lo) connect serial_tl_0.out.bits.phit, _serial_tl_0_out_bits_phit_T node _T_39 = bits(system.serial_tl_0.out.valid, 0, 0) inst iocell_serial_tl_0_out_valid of GenericDigitalOutIOCell_35 connect iocell_serial_tl_0_out_valid.o, _T_39 connect iocell_serial_tl_0_out_valid.oe, UInt<1>(0h1) connect serial_tl_0.out.valid, iocell_serial_tl_0_out_valid.pad node _T_40 = bits(serial_tl_0.out.ready, 0, 0) inst iocell_serial_tl_0_out_ready of GenericDigitalInIOCell_6 connect iocell_serial_tl_0_out_ready.pad, _T_40 connect iocell_serial_tl_0_out_ready.ie, UInt<1>(0h1) connect system.serial_tl_0.out.ready, iocell_serial_tl_0_out_ready.i node _T_41 = bits(serial_tl_0.in.bits.phit, 0, 0) node _T_42 = bits(serial_tl_0.in.bits.phit, 1, 1) node _T_43 = bits(serial_tl_0.in.bits.phit, 2, 2) node _T_44 = bits(serial_tl_0.in.bits.phit, 3, 3) node _T_45 = bits(serial_tl_0.in.bits.phit, 4, 4) node _T_46 = bits(serial_tl_0.in.bits.phit, 5, 5) node _T_47 = bits(serial_tl_0.in.bits.phit, 6, 6) node _T_48 = bits(serial_tl_0.in.bits.phit, 7, 7) node _T_49 = bits(serial_tl_0.in.bits.phit, 8, 8) node _T_50 = bits(serial_tl_0.in.bits.phit, 9, 9) node _T_51 = bits(serial_tl_0.in.bits.phit, 10, 10) node _T_52 = bits(serial_tl_0.in.bits.phit, 11, 11) node _T_53 = bits(serial_tl_0.in.bits.phit, 12, 12) node _T_54 = bits(serial_tl_0.in.bits.phit, 13, 13) node _T_55 = bits(serial_tl_0.in.bits.phit, 14, 14) node _T_56 = bits(serial_tl_0.in.bits.phit, 15, 15) node _T_57 = bits(serial_tl_0.in.bits.phit, 16, 16) node _T_58 = bits(serial_tl_0.in.bits.phit, 17, 17) node _T_59 = bits(serial_tl_0.in.bits.phit, 18, 18) node _T_60 = bits(serial_tl_0.in.bits.phit, 19, 19) node _T_61 = bits(serial_tl_0.in.bits.phit, 20, 20) node _T_62 = bits(serial_tl_0.in.bits.phit, 21, 21) node _T_63 = bits(serial_tl_0.in.bits.phit, 22, 22) node _T_64 = bits(serial_tl_0.in.bits.phit, 23, 23) node _T_65 = bits(serial_tl_0.in.bits.phit, 24, 24) node _T_66 = bits(serial_tl_0.in.bits.phit, 25, 25) node _T_67 = bits(serial_tl_0.in.bits.phit, 26, 26) node _T_68 = bits(serial_tl_0.in.bits.phit, 27, 27) node _T_69 = bits(serial_tl_0.in.bits.phit, 28, 28) node _T_70 = bits(serial_tl_0.in.bits.phit, 29, 29) node _T_71 = bits(serial_tl_0.in.bits.phit, 30, 30) node _T_72 = bits(serial_tl_0.in.bits.phit, 31, 31) inst iocell_serial_tl_0_in_bits_phit of GenericDigitalInIOCell_7 connect iocell_serial_tl_0_in_bits_phit.pad, _T_41 connect iocell_serial_tl_0_in_bits_phit.ie, UInt<1>(0h1) inst iocell_serial_tl_0_in_bits_phit_1 of GenericDigitalInIOCell_8 connect iocell_serial_tl_0_in_bits_phit_1.pad, _T_42 connect iocell_serial_tl_0_in_bits_phit_1.ie, UInt<1>(0h1) inst iocell_serial_tl_0_in_bits_phit_2 of GenericDigitalInIOCell_9 connect iocell_serial_tl_0_in_bits_phit_2.pad, _T_43 connect iocell_serial_tl_0_in_bits_phit_2.ie, UInt<1>(0h1) inst iocell_serial_tl_0_in_bits_phit_3 of GenericDigitalInIOCell_10 connect iocell_serial_tl_0_in_bits_phit_3.pad, _T_44 connect iocell_serial_tl_0_in_bits_phit_3.ie, UInt<1>(0h1) inst iocell_serial_tl_0_in_bits_phit_4 of GenericDigitalInIOCell_11 connect iocell_serial_tl_0_in_bits_phit_4.pad, _T_45 connect iocell_serial_tl_0_in_bits_phit_4.ie, UInt<1>(0h1) inst iocell_serial_tl_0_in_bits_phit_5 of GenericDigitalInIOCell_12 connect iocell_serial_tl_0_in_bits_phit_5.pad, _T_46 connect iocell_serial_tl_0_in_bits_phit_5.ie, UInt<1>(0h1) inst iocell_serial_tl_0_in_bits_phit_6 of GenericDigitalInIOCell_13 connect iocell_serial_tl_0_in_bits_phit_6.pad, _T_47 connect iocell_serial_tl_0_in_bits_phit_6.ie, UInt<1>(0h1) inst iocell_serial_tl_0_in_bits_phit_7 of GenericDigitalInIOCell_14 connect iocell_serial_tl_0_in_bits_phit_7.pad, _T_48 connect iocell_serial_tl_0_in_bits_phit_7.ie, UInt<1>(0h1) inst iocell_serial_tl_0_in_bits_phit_8 of GenericDigitalInIOCell_15 connect iocell_serial_tl_0_in_bits_phit_8.pad, _T_49 connect iocell_serial_tl_0_in_bits_phit_8.ie, UInt<1>(0h1) inst iocell_serial_tl_0_in_bits_phit_9 of GenericDigitalInIOCell_16 connect iocell_serial_tl_0_in_bits_phit_9.pad, _T_50 connect iocell_serial_tl_0_in_bits_phit_9.ie, UInt<1>(0h1) inst iocell_serial_tl_0_in_bits_phit_10 of GenericDigitalInIOCell_17 connect iocell_serial_tl_0_in_bits_phit_10.pad, _T_51 connect iocell_serial_tl_0_in_bits_phit_10.ie, UInt<1>(0h1) inst iocell_serial_tl_0_in_bits_phit_11 of GenericDigitalInIOCell_18 connect iocell_serial_tl_0_in_bits_phit_11.pad, _T_52 connect iocell_serial_tl_0_in_bits_phit_11.ie, UInt<1>(0h1) inst iocell_serial_tl_0_in_bits_phit_12 of GenericDigitalInIOCell_19 connect iocell_serial_tl_0_in_bits_phit_12.pad, _T_53 connect iocell_serial_tl_0_in_bits_phit_12.ie, UInt<1>(0h1) inst iocell_serial_tl_0_in_bits_phit_13 of GenericDigitalInIOCell_20 connect iocell_serial_tl_0_in_bits_phit_13.pad, _T_54 connect iocell_serial_tl_0_in_bits_phit_13.ie, UInt<1>(0h1) inst iocell_serial_tl_0_in_bits_phit_14 of GenericDigitalInIOCell_21 connect iocell_serial_tl_0_in_bits_phit_14.pad, _T_55 connect iocell_serial_tl_0_in_bits_phit_14.ie, UInt<1>(0h1) inst iocell_serial_tl_0_in_bits_phit_15 of GenericDigitalInIOCell_22 connect iocell_serial_tl_0_in_bits_phit_15.pad, _T_56 connect iocell_serial_tl_0_in_bits_phit_15.ie, UInt<1>(0h1) inst iocell_serial_tl_0_in_bits_phit_16 of GenericDigitalInIOCell_23 connect iocell_serial_tl_0_in_bits_phit_16.pad, _T_57 connect iocell_serial_tl_0_in_bits_phit_16.ie, UInt<1>(0h1) inst iocell_serial_tl_0_in_bits_phit_17 of GenericDigitalInIOCell_24 connect iocell_serial_tl_0_in_bits_phit_17.pad, _T_58 connect iocell_serial_tl_0_in_bits_phit_17.ie, UInt<1>(0h1) inst iocell_serial_tl_0_in_bits_phit_18 of GenericDigitalInIOCell_25 connect iocell_serial_tl_0_in_bits_phit_18.pad, _T_59 connect iocell_serial_tl_0_in_bits_phit_18.ie, UInt<1>(0h1) inst iocell_serial_tl_0_in_bits_phit_19 of GenericDigitalInIOCell_26 connect iocell_serial_tl_0_in_bits_phit_19.pad, _T_60 connect iocell_serial_tl_0_in_bits_phit_19.ie, UInt<1>(0h1) inst iocell_serial_tl_0_in_bits_phit_20 of GenericDigitalInIOCell_27 connect iocell_serial_tl_0_in_bits_phit_20.pad, _T_61 connect iocell_serial_tl_0_in_bits_phit_20.ie, UInt<1>(0h1) inst iocell_serial_tl_0_in_bits_phit_21 of GenericDigitalInIOCell_28 connect iocell_serial_tl_0_in_bits_phit_21.pad, _T_62 connect iocell_serial_tl_0_in_bits_phit_21.ie, UInt<1>(0h1) inst iocell_serial_tl_0_in_bits_phit_22 of GenericDigitalInIOCell_29 connect iocell_serial_tl_0_in_bits_phit_22.pad, _T_63 connect iocell_serial_tl_0_in_bits_phit_22.ie, UInt<1>(0h1) inst iocell_serial_tl_0_in_bits_phit_23 of GenericDigitalInIOCell_30 connect iocell_serial_tl_0_in_bits_phit_23.pad, _T_64 connect iocell_serial_tl_0_in_bits_phit_23.ie, UInt<1>(0h1) inst iocell_serial_tl_0_in_bits_phit_24 of GenericDigitalInIOCell_31 connect iocell_serial_tl_0_in_bits_phit_24.pad, _T_65 connect iocell_serial_tl_0_in_bits_phit_24.ie, UInt<1>(0h1) inst iocell_serial_tl_0_in_bits_phit_25 of GenericDigitalInIOCell_32 connect iocell_serial_tl_0_in_bits_phit_25.pad, _T_66 connect iocell_serial_tl_0_in_bits_phit_25.ie, UInt<1>(0h1) inst iocell_serial_tl_0_in_bits_phit_26 of GenericDigitalInIOCell_33 connect iocell_serial_tl_0_in_bits_phit_26.pad, _T_67 connect iocell_serial_tl_0_in_bits_phit_26.ie, UInt<1>(0h1) inst iocell_serial_tl_0_in_bits_phit_27 of GenericDigitalInIOCell_34 connect iocell_serial_tl_0_in_bits_phit_27.pad, _T_68 connect iocell_serial_tl_0_in_bits_phit_27.ie, UInt<1>(0h1) inst iocell_serial_tl_0_in_bits_phit_28 of GenericDigitalInIOCell_35 connect iocell_serial_tl_0_in_bits_phit_28.pad, _T_69 connect iocell_serial_tl_0_in_bits_phit_28.ie, UInt<1>(0h1) inst iocell_serial_tl_0_in_bits_phit_29 of GenericDigitalInIOCell_36 connect iocell_serial_tl_0_in_bits_phit_29.pad, _T_70 connect iocell_serial_tl_0_in_bits_phit_29.ie, UInt<1>(0h1) inst iocell_serial_tl_0_in_bits_phit_30 of GenericDigitalInIOCell_37 connect iocell_serial_tl_0_in_bits_phit_30.pad, _T_71 connect iocell_serial_tl_0_in_bits_phit_30.ie, UInt<1>(0h1) inst iocell_serial_tl_0_in_bits_phit_31 of GenericDigitalInIOCell_38 connect iocell_serial_tl_0_in_bits_phit_31.pad, _T_72 connect iocell_serial_tl_0_in_bits_phit_31.ie, UInt<1>(0h1) node system_serial_tl_0_in_bits_phit_lo_lo_lo_lo = cat(iocell_serial_tl_0_in_bits_phit_1.i, iocell_serial_tl_0_in_bits_phit.i) node system_serial_tl_0_in_bits_phit_lo_lo_lo_hi = cat(iocell_serial_tl_0_in_bits_phit_3.i, iocell_serial_tl_0_in_bits_phit_2.i) node system_serial_tl_0_in_bits_phit_lo_lo_lo = cat(system_serial_tl_0_in_bits_phit_lo_lo_lo_hi, system_serial_tl_0_in_bits_phit_lo_lo_lo_lo) node system_serial_tl_0_in_bits_phit_lo_lo_hi_lo = cat(iocell_serial_tl_0_in_bits_phit_5.i, iocell_serial_tl_0_in_bits_phit_4.i) node system_serial_tl_0_in_bits_phit_lo_lo_hi_hi = cat(iocell_serial_tl_0_in_bits_phit_7.i, iocell_serial_tl_0_in_bits_phit_6.i) node system_serial_tl_0_in_bits_phit_lo_lo_hi = cat(system_serial_tl_0_in_bits_phit_lo_lo_hi_hi, system_serial_tl_0_in_bits_phit_lo_lo_hi_lo) node system_serial_tl_0_in_bits_phit_lo_lo = cat(system_serial_tl_0_in_bits_phit_lo_lo_hi, system_serial_tl_0_in_bits_phit_lo_lo_lo) node system_serial_tl_0_in_bits_phit_lo_hi_lo_lo = cat(iocell_serial_tl_0_in_bits_phit_9.i, iocell_serial_tl_0_in_bits_phit_8.i) node system_serial_tl_0_in_bits_phit_lo_hi_lo_hi = cat(iocell_serial_tl_0_in_bits_phit_11.i, iocell_serial_tl_0_in_bits_phit_10.i) node system_serial_tl_0_in_bits_phit_lo_hi_lo = cat(system_serial_tl_0_in_bits_phit_lo_hi_lo_hi, system_serial_tl_0_in_bits_phit_lo_hi_lo_lo) node system_serial_tl_0_in_bits_phit_lo_hi_hi_lo = cat(iocell_serial_tl_0_in_bits_phit_13.i, iocell_serial_tl_0_in_bits_phit_12.i) node system_serial_tl_0_in_bits_phit_lo_hi_hi_hi = cat(iocell_serial_tl_0_in_bits_phit_15.i, iocell_serial_tl_0_in_bits_phit_14.i) node system_serial_tl_0_in_bits_phit_lo_hi_hi = cat(system_serial_tl_0_in_bits_phit_lo_hi_hi_hi, system_serial_tl_0_in_bits_phit_lo_hi_hi_lo) node system_serial_tl_0_in_bits_phit_lo_hi = cat(system_serial_tl_0_in_bits_phit_lo_hi_hi, system_serial_tl_0_in_bits_phit_lo_hi_lo) node system_serial_tl_0_in_bits_phit_lo = cat(system_serial_tl_0_in_bits_phit_lo_hi, system_serial_tl_0_in_bits_phit_lo_lo) node system_serial_tl_0_in_bits_phit_hi_lo_lo_lo = cat(iocell_serial_tl_0_in_bits_phit_17.i, iocell_serial_tl_0_in_bits_phit_16.i) node system_serial_tl_0_in_bits_phit_hi_lo_lo_hi = cat(iocell_serial_tl_0_in_bits_phit_19.i, iocell_serial_tl_0_in_bits_phit_18.i) node system_serial_tl_0_in_bits_phit_hi_lo_lo = cat(system_serial_tl_0_in_bits_phit_hi_lo_lo_hi, system_serial_tl_0_in_bits_phit_hi_lo_lo_lo) node system_serial_tl_0_in_bits_phit_hi_lo_hi_lo = cat(iocell_serial_tl_0_in_bits_phit_21.i, iocell_serial_tl_0_in_bits_phit_20.i) node system_serial_tl_0_in_bits_phit_hi_lo_hi_hi = cat(iocell_serial_tl_0_in_bits_phit_23.i, iocell_serial_tl_0_in_bits_phit_22.i) node system_serial_tl_0_in_bits_phit_hi_lo_hi = cat(system_serial_tl_0_in_bits_phit_hi_lo_hi_hi, system_serial_tl_0_in_bits_phit_hi_lo_hi_lo) node system_serial_tl_0_in_bits_phit_hi_lo = cat(system_serial_tl_0_in_bits_phit_hi_lo_hi, system_serial_tl_0_in_bits_phit_hi_lo_lo) node system_serial_tl_0_in_bits_phit_hi_hi_lo_lo = cat(iocell_serial_tl_0_in_bits_phit_25.i, iocell_serial_tl_0_in_bits_phit_24.i) node system_serial_tl_0_in_bits_phit_hi_hi_lo_hi = cat(iocell_serial_tl_0_in_bits_phit_27.i, iocell_serial_tl_0_in_bits_phit_26.i) node system_serial_tl_0_in_bits_phit_hi_hi_lo = cat(system_serial_tl_0_in_bits_phit_hi_hi_lo_hi, system_serial_tl_0_in_bits_phit_hi_hi_lo_lo) node system_serial_tl_0_in_bits_phit_hi_hi_hi_lo = cat(iocell_serial_tl_0_in_bits_phit_29.i, iocell_serial_tl_0_in_bits_phit_28.i) node system_serial_tl_0_in_bits_phit_hi_hi_hi_hi = cat(iocell_serial_tl_0_in_bits_phit_31.i, iocell_serial_tl_0_in_bits_phit_30.i) node system_serial_tl_0_in_bits_phit_hi_hi_hi = cat(system_serial_tl_0_in_bits_phit_hi_hi_hi_hi, system_serial_tl_0_in_bits_phit_hi_hi_hi_lo) node system_serial_tl_0_in_bits_phit_hi_hi = cat(system_serial_tl_0_in_bits_phit_hi_hi_hi, system_serial_tl_0_in_bits_phit_hi_hi_lo) node system_serial_tl_0_in_bits_phit_hi = cat(system_serial_tl_0_in_bits_phit_hi_hi, system_serial_tl_0_in_bits_phit_hi_lo) node _system_serial_tl_0_in_bits_phit_T = cat(system_serial_tl_0_in_bits_phit_hi, system_serial_tl_0_in_bits_phit_lo) connect system.serial_tl_0.in.bits.phit, _system_serial_tl_0_in_bits_phit_T node _T_73 = bits(serial_tl_0.in.valid, 0, 0) inst iocell_serial_tl_0_in_valid of GenericDigitalInIOCell_39 connect iocell_serial_tl_0_in_valid.pad, _T_73 connect iocell_serial_tl_0_in_valid.ie, UInt<1>(0h1) connect system.serial_tl_0.in.valid, iocell_serial_tl_0_in_valid.i node _T_74 = bits(system.serial_tl_0.in.ready, 0, 0) inst iocell_serial_tl_0_in_ready of GenericDigitalOutIOCell_36 connect iocell_serial_tl_0_in_ready.o, _T_74 connect iocell_serial_tl_0_in_ready.oe, UInt<1>(0h1) connect serial_tl_0.in.ready, iocell_serial_tl_0_in_ready.pad invalidate system.interrupts extmodule SimUART : input clock : Clock input reset : UInt<1> input serial : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<8>}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<8>}} defname = SimUART parameter FORCEPTY = 0 parameter UARTNO = 0
module ChipTop( // @[ChipTop.scala:33:44] output uart_0_txd, // @[IOCell.scala:196:23] input uart_0_rxd, // @[IOCell.scala:196:23] output axi4_mem_0_clock, // @[IOBinders.scala:397:22] input axi4_mem_0_bits_aw_ready, // @[IOBinders.scala:397:22] output axi4_mem_0_bits_aw_valid, // @[IOBinders.scala:397:22] output [6:0] axi4_mem_0_bits_aw_bits_id, // @[IOBinders.scala:397:22] output [31:0] axi4_mem_0_bits_aw_bits_addr, // @[IOBinders.scala:397:22] output [7:0] axi4_mem_0_bits_aw_bits_len, // @[IOBinders.scala:397:22] output [2:0] axi4_mem_0_bits_aw_bits_size, // @[IOBinders.scala:397:22] output [1:0] axi4_mem_0_bits_aw_bits_burst, // @[IOBinders.scala:397:22] output axi4_mem_0_bits_aw_bits_lock, // @[IOBinders.scala:397:22] output [3:0] axi4_mem_0_bits_aw_bits_cache, // @[IOBinders.scala:397:22] output [2:0] axi4_mem_0_bits_aw_bits_prot, // @[IOBinders.scala:397:22] output [3:0] axi4_mem_0_bits_aw_bits_qos, // @[IOBinders.scala:397:22] input axi4_mem_0_bits_w_ready, // @[IOBinders.scala:397:22] output axi4_mem_0_bits_w_valid, // @[IOBinders.scala:397:22] output [63:0] axi4_mem_0_bits_w_bits_data, // @[IOBinders.scala:397:22] output [7:0] axi4_mem_0_bits_w_bits_strb, // @[IOBinders.scala:397:22] output axi4_mem_0_bits_w_bits_last, // @[IOBinders.scala:397:22] output axi4_mem_0_bits_b_ready, // @[IOBinders.scala:397:22] input axi4_mem_0_bits_b_valid, // @[IOBinders.scala:397:22] input [6:0] axi4_mem_0_bits_b_bits_id, // @[IOBinders.scala:397:22] input [1:0] axi4_mem_0_bits_b_bits_resp, // @[IOBinders.scala:397:22] input axi4_mem_0_bits_ar_ready, // @[IOBinders.scala:397:22] output axi4_mem_0_bits_ar_valid, // @[IOBinders.scala:397:22] output [6:0] axi4_mem_0_bits_ar_bits_id, // @[IOBinders.scala:397:22] output [31:0] axi4_mem_0_bits_ar_bits_addr, // @[IOBinders.scala:397:22] output [7:0] axi4_mem_0_bits_ar_bits_len, // @[IOBinders.scala:397:22] output [2:0] axi4_mem_0_bits_ar_bits_size, // @[IOBinders.scala:397:22] output [1:0] axi4_mem_0_bits_ar_bits_burst, // @[IOBinders.scala:397:22] output axi4_mem_0_bits_ar_bits_lock, // @[IOBinders.scala:397:22] output [3:0] axi4_mem_0_bits_ar_bits_cache, // @[IOBinders.scala:397:22] output [2:0] axi4_mem_0_bits_ar_bits_prot, // @[IOBinders.scala:397:22] output [3:0] axi4_mem_0_bits_ar_bits_qos, // @[IOBinders.scala:397:22] output axi4_mem_0_bits_r_ready, // @[IOBinders.scala:397:22] input axi4_mem_0_bits_r_valid, // @[IOBinders.scala:397:22] input [6:0] axi4_mem_0_bits_r_bits_id, // @[IOBinders.scala:397:22] input [63:0] axi4_mem_0_bits_r_bits_data, // @[IOBinders.scala:397:22] input [1:0] axi4_mem_0_bits_r_bits_resp, // @[IOBinders.scala:397:22] input axi4_mem_0_bits_r_bits_last, // @[IOBinders.scala:397:22] output axi4_mem_1_clock, // @[IOBinders.scala:397:22] input axi4_mem_1_bits_aw_ready, // @[IOBinders.scala:397:22] output axi4_mem_1_bits_aw_valid, // @[IOBinders.scala:397:22] output [6:0] axi4_mem_1_bits_aw_bits_id, // @[IOBinders.scala:397:22] output [31:0] axi4_mem_1_bits_aw_bits_addr, // @[IOBinders.scala:397:22] output [7:0] axi4_mem_1_bits_aw_bits_len, // @[IOBinders.scala:397:22] output [2:0] axi4_mem_1_bits_aw_bits_size, // @[IOBinders.scala:397:22] output [1:0] axi4_mem_1_bits_aw_bits_burst, // @[IOBinders.scala:397:22] output axi4_mem_1_bits_aw_bits_lock, // @[IOBinders.scala:397:22] output [3:0] axi4_mem_1_bits_aw_bits_cache, // @[IOBinders.scala:397:22] output [2:0] axi4_mem_1_bits_aw_bits_prot, // @[IOBinders.scala:397:22] output [3:0] axi4_mem_1_bits_aw_bits_qos, // @[IOBinders.scala:397:22] input axi4_mem_1_bits_w_ready, // @[IOBinders.scala:397:22] output axi4_mem_1_bits_w_valid, // @[IOBinders.scala:397:22] output [63:0] axi4_mem_1_bits_w_bits_data, // @[IOBinders.scala:397:22] output [7:0] axi4_mem_1_bits_w_bits_strb, // @[IOBinders.scala:397:22] output axi4_mem_1_bits_w_bits_last, // @[IOBinders.scala:397:22] output axi4_mem_1_bits_b_ready, // @[IOBinders.scala:397:22] input axi4_mem_1_bits_b_valid, // @[IOBinders.scala:397:22] input [6:0] axi4_mem_1_bits_b_bits_id, // @[IOBinders.scala:397:22] input [1:0] axi4_mem_1_bits_b_bits_resp, // @[IOBinders.scala:397:22] input axi4_mem_1_bits_ar_ready, // @[IOBinders.scala:397:22] output axi4_mem_1_bits_ar_valid, // @[IOBinders.scala:397:22] output [6:0] axi4_mem_1_bits_ar_bits_id, // @[IOBinders.scala:397:22] output [31:0] axi4_mem_1_bits_ar_bits_addr, // @[IOBinders.scala:397:22] output [7:0] axi4_mem_1_bits_ar_bits_len, // @[IOBinders.scala:397:22] output [2:0] axi4_mem_1_bits_ar_bits_size, // @[IOBinders.scala:397:22] output [1:0] axi4_mem_1_bits_ar_bits_burst, // @[IOBinders.scala:397:22] output axi4_mem_1_bits_ar_bits_lock, // @[IOBinders.scala:397:22] output [3:0] axi4_mem_1_bits_ar_bits_cache, // @[IOBinders.scala:397:22] output [2:0] axi4_mem_1_bits_ar_bits_prot, // @[IOBinders.scala:397:22] output [3:0] axi4_mem_1_bits_ar_bits_qos, // @[IOBinders.scala:397:22] output axi4_mem_1_bits_r_ready, // @[IOBinders.scala:397:22] input axi4_mem_1_bits_r_valid, // @[IOBinders.scala:397:22] input [6:0] axi4_mem_1_bits_r_bits_id, // @[IOBinders.scala:397:22] input [63:0] axi4_mem_1_bits_r_bits_data, // @[IOBinders.scala:397:22] input [1:0] axi4_mem_1_bits_r_bits_resp, // @[IOBinders.scala:397:22] input axi4_mem_1_bits_r_bits_last, // @[IOBinders.scala:397:22] output axi4_mem_2_clock, // @[IOBinders.scala:397:22] input axi4_mem_2_bits_aw_ready, // @[IOBinders.scala:397:22] output axi4_mem_2_bits_aw_valid, // @[IOBinders.scala:397:22] output [6:0] axi4_mem_2_bits_aw_bits_id, // @[IOBinders.scala:397:22] output [31:0] axi4_mem_2_bits_aw_bits_addr, // @[IOBinders.scala:397:22] output [7:0] axi4_mem_2_bits_aw_bits_len, // @[IOBinders.scala:397:22] output [2:0] axi4_mem_2_bits_aw_bits_size, // @[IOBinders.scala:397:22] output [1:0] axi4_mem_2_bits_aw_bits_burst, // @[IOBinders.scala:397:22] output axi4_mem_2_bits_aw_bits_lock, // @[IOBinders.scala:397:22] output [3:0] axi4_mem_2_bits_aw_bits_cache, // @[IOBinders.scala:397:22] output [2:0] axi4_mem_2_bits_aw_bits_prot, // @[IOBinders.scala:397:22] output [3:0] axi4_mem_2_bits_aw_bits_qos, // @[IOBinders.scala:397:22] input axi4_mem_2_bits_w_ready, // @[IOBinders.scala:397:22] output axi4_mem_2_bits_w_valid, // @[IOBinders.scala:397:22] output [63:0] axi4_mem_2_bits_w_bits_data, // @[IOBinders.scala:397:22] output [7:0] axi4_mem_2_bits_w_bits_strb, // @[IOBinders.scala:397:22] output axi4_mem_2_bits_w_bits_last, // @[IOBinders.scala:397:22] output axi4_mem_2_bits_b_ready, // @[IOBinders.scala:397:22] input axi4_mem_2_bits_b_valid, // @[IOBinders.scala:397:22] input [6:0] axi4_mem_2_bits_b_bits_id, // @[IOBinders.scala:397:22] input [1:0] axi4_mem_2_bits_b_bits_resp, // @[IOBinders.scala:397:22] input axi4_mem_2_bits_ar_ready, // @[IOBinders.scala:397:22] output axi4_mem_2_bits_ar_valid, // @[IOBinders.scala:397:22] output [6:0] axi4_mem_2_bits_ar_bits_id, // @[IOBinders.scala:397:22] output [31:0] axi4_mem_2_bits_ar_bits_addr, // @[IOBinders.scala:397:22] output [7:0] axi4_mem_2_bits_ar_bits_len, // @[IOBinders.scala:397:22] output [2:0] axi4_mem_2_bits_ar_bits_size, // @[IOBinders.scala:397:22] output [1:0] axi4_mem_2_bits_ar_bits_burst, // @[IOBinders.scala:397:22] output axi4_mem_2_bits_ar_bits_lock, // @[IOBinders.scala:397:22] output [3:0] axi4_mem_2_bits_ar_bits_cache, // @[IOBinders.scala:397:22] output [2:0] axi4_mem_2_bits_ar_bits_prot, // @[IOBinders.scala:397:22] output [3:0] axi4_mem_2_bits_ar_bits_qos, // @[IOBinders.scala:397:22] output axi4_mem_2_bits_r_ready, // @[IOBinders.scala:397:22] input axi4_mem_2_bits_r_valid, // @[IOBinders.scala:397:22] input [6:0] axi4_mem_2_bits_r_bits_id, // @[IOBinders.scala:397:22] input [63:0] axi4_mem_2_bits_r_bits_data, // @[IOBinders.scala:397:22] input [1:0] axi4_mem_2_bits_r_bits_resp, // @[IOBinders.scala:397:22] input axi4_mem_2_bits_r_bits_last, // @[IOBinders.scala:397:22] output axi4_mem_3_clock, // @[IOBinders.scala:397:22] input axi4_mem_3_bits_aw_ready, // @[IOBinders.scala:397:22] output axi4_mem_3_bits_aw_valid, // @[IOBinders.scala:397:22] output [6:0] axi4_mem_3_bits_aw_bits_id, // @[IOBinders.scala:397:22] output [31:0] axi4_mem_3_bits_aw_bits_addr, // @[IOBinders.scala:397:22] output [7:0] axi4_mem_3_bits_aw_bits_len, // @[IOBinders.scala:397:22] output [2:0] axi4_mem_3_bits_aw_bits_size, // @[IOBinders.scala:397:22] output [1:0] axi4_mem_3_bits_aw_bits_burst, // @[IOBinders.scala:397:22] output axi4_mem_3_bits_aw_bits_lock, // @[IOBinders.scala:397:22] output [3:0] axi4_mem_3_bits_aw_bits_cache, // @[IOBinders.scala:397:22] output [2:0] axi4_mem_3_bits_aw_bits_prot, // @[IOBinders.scala:397:22] output [3:0] axi4_mem_3_bits_aw_bits_qos, // @[IOBinders.scala:397:22] input axi4_mem_3_bits_w_ready, // @[IOBinders.scala:397:22] output axi4_mem_3_bits_w_valid, // @[IOBinders.scala:397:22] output [63:0] axi4_mem_3_bits_w_bits_data, // @[IOBinders.scala:397:22] output [7:0] axi4_mem_3_bits_w_bits_strb, // @[IOBinders.scala:397:22] output axi4_mem_3_bits_w_bits_last, // @[IOBinders.scala:397:22] output axi4_mem_3_bits_b_ready, // @[IOBinders.scala:397:22] input axi4_mem_3_bits_b_valid, // @[IOBinders.scala:397:22] input [6:0] axi4_mem_3_bits_b_bits_id, // @[IOBinders.scala:397:22] input [1:0] axi4_mem_3_bits_b_bits_resp, // @[IOBinders.scala:397:22] input axi4_mem_3_bits_ar_ready, // @[IOBinders.scala:397:22] output axi4_mem_3_bits_ar_valid, // @[IOBinders.scala:397:22] output [6:0] axi4_mem_3_bits_ar_bits_id, // @[IOBinders.scala:397:22] output [31:0] axi4_mem_3_bits_ar_bits_addr, // @[IOBinders.scala:397:22] output [7:0] axi4_mem_3_bits_ar_bits_len, // @[IOBinders.scala:397:22] output [2:0] axi4_mem_3_bits_ar_bits_size, // @[IOBinders.scala:397:22] output [1:0] axi4_mem_3_bits_ar_bits_burst, // @[IOBinders.scala:397:22] output axi4_mem_3_bits_ar_bits_lock, // @[IOBinders.scala:397:22] output [3:0] axi4_mem_3_bits_ar_bits_cache, // @[IOBinders.scala:397:22] output [2:0] axi4_mem_3_bits_ar_bits_prot, // @[IOBinders.scala:397:22] output [3:0] axi4_mem_3_bits_ar_bits_qos, // @[IOBinders.scala:397:22] output axi4_mem_3_bits_r_ready, // @[IOBinders.scala:397:22] input axi4_mem_3_bits_r_valid, // @[IOBinders.scala:397:22] input [6:0] axi4_mem_3_bits_r_bits_id, // @[IOBinders.scala:397:22] input [63:0] axi4_mem_3_bits_r_bits_data, // @[IOBinders.scala:397:22] input [1:0] axi4_mem_3_bits_r_bits_resp, // @[IOBinders.scala:397:22] input axi4_mem_3_bits_r_bits_last, // @[IOBinders.scala:397:22] input custom_boot, // @[IOCell.scala:196:23] input jtag_TCK, // @[IOCell.scala:196:23] input jtag_TMS, // @[IOCell.scala:196:23] input jtag_TDI, // @[IOCell.scala:196:23] output jtag_TDO, // @[IOCell.scala:196:23] input reset_io, // @[ClockBinders.scala:87:24] input clock_uncore, // @[ClockBinders.scala:95:26] output clock_tap, // @[IOCell.scala:196:23] output serial_tl_0_in_ready, // @[IOCell.scala:196:23] input serial_tl_0_in_valid, // @[IOCell.scala:196:23] input [31:0] serial_tl_0_in_bits_phit, // @[IOCell.scala:196:23] input serial_tl_0_out_ready, // @[IOCell.scala:196:23] output serial_tl_0_out_valid, // @[IOCell.scala:196:23] output [31:0] serial_tl_0_out_bits_phit, // @[IOCell.scala:196:23] input serial_tl_0_clock_in // @[IOCell.scala:196:23] ); wire _iocell_serial_tl_0_in_valid_i; // @[IOCell.scala:176:23] wire _iocell_serial_tl_0_in_bits_phit_31_i; // @[IOCell.scala:176:23] wire _iocell_serial_tl_0_in_bits_phit_30_i; // @[IOCell.scala:176:23] wire _iocell_serial_tl_0_in_bits_phit_29_i; // @[IOCell.scala:176:23] wire _iocell_serial_tl_0_in_bits_phit_28_i; // @[IOCell.scala:176:23] wire _iocell_serial_tl_0_in_bits_phit_27_i; // @[IOCell.scala:176:23] wire _iocell_serial_tl_0_in_bits_phit_26_i; // @[IOCell.scala:176:23] wire _iocell_serial_tl_0_in_bits_phit_25_i; // @[IOCell.scala:176:23] wire _iocell_serial_tl_0_in_bits_phit_24_i; // @[IOCell.scala:176:23] wire _iocell_serial_tl_0_in_bits_phit_23_i; // @[IOCell.scala:176:23] wire _iocell_serial_tl_0_in_bits_phit_22_i; // @[IOCell.scala:176:23] wire _iocell_serial_tl_0_in_bits_phit_21_i; // @[IOCell.scala:176:23] wire _iocell_serial_tl_0_in_bits_phit_20_i; // @[IOCell.scala:176:23] wire _iocell_serial_tl_0_in_bits_phit_19_i; // @[IOCell.scala:176:23] wire _iocell_serial_tl_0_in_bits_phit_18_i; // @[IOCell.scala:176:23] wire _iocell_serial_tl_0_in_bits_phit_17_i; // @[IOCell.scala:176:23] wire _iocell_serial_tl_0_in_bits_phit_16_i; // @[IOCell.scala:176:23] wire _iocell_serial_tl_0_in_bits_phit_15_i; // @[IOCell.scala:176:23] wire _iocell_serial_tl_0_in_bits_phit_14_i; // @[IOCell.scala:176:23] wire _iocell_serial_tl_0_in_bits_phit_13_i; // @[IOCell.scala:176:23] wire _iocell_serial_tl_0_in_bits_phit_12_i; // @[IOCell.scala:176:23] wire _iocell_serial_tl_0_in_bits_phit_11_i; // @[IOCell.scala:176:23] wire _iocell_serial_tl_0_in_bits_phit_10_i; // @[IOCell.scala:176:23] wire _iocell_serial_tl_0_in_bits_phit_9_i; // @[IOCell.scala:176:23] wire _iocell_serial_tl_0_in_bits_phit_8_i; // @[IOCell.scala:176:23] wire _iocell_serial_tl_0_in_bits_phit_7_i; // @[IOCell.scala:176:23] wire _iocell_serial_tl_0_in_bits_phit_6_i; // @[IOCell.scala:176:23] wire _iocell_serial_tl_0_in_bits_phit_5_i; // @[IOCell.scala:176:23] wire _iocell_serial_tl_0_in_bits_phit_4_i; // @[IOCell.scala:176:23] wire _iocell_serial_tl_0_in_bits_phit_3_i; // @[IOCell.scala:176:23] wire _iocell_serial_tl_0_in_bits_phit_2_i; // @[IOCell.scala:176:23] wire _iocell_serial_tl_0_in_bits_phit_1_i; // @[IOCell.scala:176:23] wire _iocell_serial_tl_0_in_bits_phit_i; // @[IOCell.scala:176:23] wire _iocell_serial_tl_0_out_ready_i; // @[IOCell.scala:176:23] wire _iocell_serial_tl_0_out_bits_phit_31_pad; // @[IOCell.scala:177:24] wire _iocell_serial_tl_0_out_bits_phit_30_pad; // @[IOCell.scala:177:24] wire _iocell_serial_tl_0_out_bits_phit_29_pad; // @[IOCell.scala:177:24] wire _iocell_serial_tl_0_out_bits_phit_28_pad; // @[IOCell.scala:177:24] wire _iocell_serial_tl_0_out_bits_phit_27_pad; // @[IOCell.scala:177:24] wire _iocell_serial_tl_0_out_bits_phit_26_pad; // @[IOCell.scala:177:24] wire _iocell_serial_tl_0_out_bits_phit_25_pad; // @[IOCell.scala:177:24] wire _iocell_serial_tl_0_out_bits_phit_24_pad; // @[IOCell.scala:177:24] wire _iocell_serial_tl_0_out_bits_phit_23_pad; // @[IOCell.scala:177:24] wire _iocell_serial_tl_0_out_bits_phit_22_pad; // @[IOCell.scala:177:24] wire _iocell_serial_tl_0_out_bits_phit_21_pad; // @[IOCell.scala:177:24] wire _iocell_serial_tl_0_out_bits_phit_20_pad; // @[IOCell.scala:177:24] wire _iocell_serial_tl_0_out_bits_phit_19_pad; // @[IOCell.scala:177:24] wire _iocell_serial_tl_0_out_bits_phit_18_pad; // @[IOCell.scala:177:24] wire _iocell_serial_tl_0_out_bits_phit_17_pad; // @[IOCell.scala:177:24] wire _iocell_serial_tl_0_out_bits_phit_16_pad; // @[IOCell.scala:177:24] wire _iocell_serial_tl_0_out_bits_phit_15_pad; // @[IOCell.scala:177:24] wire _iocell_serial_tl_0_out_bits_phit_14_pad; // @[IOCell.scala:177:24] wire _iocell_serial_tl_0_out_bits_phit_13_pad; // @[IOCell.scala:177:24] wire _iocell_serial_tl_0_out_bits_phit_12_pad; // @[IOCell.scala:177:24] wire _iocell_serial_tl_0_out_bits_phit_11_pad; // @[IOCell.scala:177:24] wire _iocell_serial_tl_0_out_bits_phit_10_pad; // @[IOCell.scala:177:24] wire _iocell_serial_tl_0_out_bits_phit_9_pad; // @[IOCell.scala:177:24] wire _iocell_serial_tl_0_out_bits_phit_8_pad; // @[IOCell.scala:177:24] wire _iocell_serial_tl_0_out_bits_phit_7_pad; // @[IOCell.scala:177:24] wire _iocell_serial_tl_0_out_bits_phit_6_pad; // @[IOCell.scala:177:24] wire _iocell_serial_tl_0_out_bits_phit_5_pad; // @[IOCell.scala:177:24] wire _iocell_serial_tl_0_out_bits_phit_4_pad; // @[IOCell.scala:177:24] wire _iocell_serial_tl_0_out_bits_phit_3_pad; // @[IOCell.scala:177:24] wire _iocell_serial_tl_0_out_bits_phit_2_pad; // @[IOCell.scala:177:24] wire _iocell_serial_tl_0_out_bits_phit_1_pad; // @[IOCell.scala:177:24] wire _iocell_serial_tl_0_out_bits_phit_pad; // @[IOCell.scala:177:24] wire _gated_clock_debug_clock_gate_out; // @[ClockGate.scala:36:20] wire _system_debug_systemjtag_reset_catcher_io_sync_reset; // @[ResetCatchAndSync.scala:39:28] wire _iocell_custom_boot_i; // @[IOCell.scala:176:23] wire _iocell_uart_0_rxd_i; // @[IOCell.scala:176:23] wire _system_debug_dmactive; // @[ChipTop.scala:27:35] wire _system_serial_tl_0_in_ready; // @[ChipTop.scala:27:35] wire _system_serial_tl_0_out_valid; // @[ChipTop.scala:27:35] wire [31:0] _system_serial_tl_0_out_bits_phit; // @[ChipTop.scala:27:35] wire _system_uart_0_txd; // @[ChipTop.scala:27:35] wire uart_0_rxd_0 = uart_0_rxd; // @[ChipTop.scala:33:44] wire axi4_mem_0_bits_aw_ready_0 = axi4_mem_0_bits_aw_ready; // @[ChipTop.scala:33:44] wire axi4_mem_0_bits_w_ready_0 = axi4_mem_0_bits_w_ready; // @[ChipTop.scala:33:44] wire axi4_mem_0_bits_b_valid_0 = axi4_mem_0_bits_b_valid; // @[ChipTop.scala:33:44] wire [6:0] axi4_mem_0_bits_b_bits_id_0 = axi4_mem_0_bits_b_bits_id; // @[ChipTop.scala:33:44] wire [1:0] axi4_mem_0_bits_b_bits_resp_0 = axi4_mem_0_bits_b_bits_resp; // @[ChipTop.scala:33:44] wire axi4_mem_0_bits_ar_ready_0 = axi4_mem_0_bits_ar_ready; // @[ChipTop.scala:33:44] wire axi4_mem_0_bits_r_valid_0 = axi4_mem_0_bits_r_valid; // @[ChipTop.scala:33:44] wire [6:0] axi4_mem_0_bits_r_bits_id_0 = axi4_mem_0_bits_r_bits_id; // @[ChipTop.scala:33:44] wire [63:0] axi4_mem_0_bits_r_bits_data_0 = axi4_mem_0_bits_r_bits_data; // @[ChipTop.scala:33:44] wire [1:0] axi4_mem_0_bits_r_bits_resp_0 = axi4_mem_0_bits_r_bits_resp; // @[ChipTop.scala:33:44] wire axi4_mem_0_bits_r_bits_last_0 = axi4_mem_0_bits_r_bits_last; // @[ChipTop.scala:33:44] wire axi4_mem_1_bits_aw_ready_0 = axi4_mem_1_bits_aw_ready; // @[ChipTop.scala:33:44] wire axi4_mem_1_bits_w_ready_0 = axi4_mem_1_bits_w_ready; // @[ChipTop.scala:33:44] wire axi4_mem_1_bits_b_valid_0 = axi4_mem_1_bits_b_valid; // @[ChipTop.scala:33:44] wire [6:0] axi4_mem_1_bits_b_bits_id_0 = axi4_mem_1_bits_b_bits_id; // @[ChipTop.scala:33:44] wire [1:0] axi4_mem_1_bits_b_bits_resp_0 = axi4_mem_1_bits_b_bits_resp; // @[ChipTop.scala:33:44] wire axi4_mem_1_bits_ar_ready_0 = axi4_mem_1_bits_ar_ready; // @[ChipTop.scala:33:44] wire axi4_mem_1_bits_r_valid_0 = axi4_mem_1_bits_r_valid; // @[ChipTop.scala:33:44] wire [6:0] axi4_mem_1_bits_r_bits_id_0 = axi4_mem_1_bits_r_bits_id; // @[ChipTop.scala:33:44] wire [63:0] axi4_mem_1_bits_r_bits_data_0 = axi4_mem_1_bits_r_bits_data; // @[ChipTop.scala:33:44] wire [1:0] axi4_mem_1_bits_r_bits_resp_0 = axi4_mem_1_bits_r_bits_resp; // @[ChipTop.scala:33:44] wire axi4_mem_1_bits_r_bits_last_0 = axi4_mem_1_bits_r_bits_last; // @[ChipTop.scala:33:44] wire axi4_mem_2_bits_aw_ready_0 = axi4_mem_2_bits_aw_ready; // @[ChipTop.scala:33:44] wire axi4_mem_2_bits_w_ready_0 = axi4_mem_2_bits_w_ready; // @[ChipTop.scala:33:44] wire axi4_mem_2_bits_b_valid_0 = axi4_mem_2_bits_b_valid; // @[ChipTop.scala:33:44] wire [6:0] axi4_mem_2_bits_b_bits_id_0 = axi4_mem_2_bits_b_bits_id; // @[ChipTop.scala:33:44] wire [1:0] axi4_mem_2_bits_b_bits_resp_0 = axi4_mem_2_bits_b_bits_resp; // @[ChipTop.scala:33:44] wire axi4_mem_2_bits_ar_ready_0 = axi4_mem_2_bits_ar_ready; // @[ChipTop.scala:33:44] wire axi4_mem_2_bits_r_valid_0 = axi4_mem_2_bits_r_valid; // @[ChipTop.scala:33:44] wire [6:0] axi4_mem_2_bits_r_bits_id_0 = axi4_mem_2_bits_r_bits_id; // @[ChipTop.scala:33:44] wire [63:0] axi4_mem_2_bits_r_bits_data_0 = axi4_mem_2_bits_r_bits_data; // @[ChipTop.scala:33:44] wire [1:0] axi4_mem_2_bits_r_bits_resp_0 = axi4_mem_2_bits_r_bits_resp; // @[ChipTop.scala:33:44] wire axi4_mem_2_bits_r_bits_last_0 = axi4_mem_2_bits_r_bits_last; // @[ChipTop.scala:33:44] wire axi4_mem_3_bits_aw_ready_0 = axi4_mem_3_bits_aw_ready; // @[ChipTop.scala:33:44] wire axi4_mem_3_bits_w_ready_0 = axi4_mem_3_bits_w_ready; // @[ChipTop.scala:33:44] wire axi4_mem_3_bits_b_valid_0 = axi4_mem_3_bits_b_valid; // @[ChipTop.scala:33:44] wire [6:0] axi4_mem_3_bits_b_bits_id_0 = axi4_mem_3_bits_b_bits_id; // @[ChipTop.scala:33:44] wire [1:0] axi4_mem_3_bits_b_bits_resp_0 = axi4_mem_3_bits_b_bits_resp; // @[ChipTop.scala:33:44] wire axi4_mem_3_bits_ar_ready_0 = axi4_mem_3_bits_ar_ready; // @[ChipTop.scala:33:44] wire axi4_mem_3_bits_r_valid_0 = axi4_mem_3_bits_r_valid; // @[ChipTop.scala:33:44] wire [6:0] axi4_mem_3_bits_r_bits_id_0 = axi4_mem_3_bits_r_bits_id; // @[ChipTop.scala:33:44] wire [63:0] axi4_mem_3_bits_r_bits_data_0 = axi4_mem_3_bits_r_bits_data; // @[ChipTop.scala:33:44] wire [1:0] axi4_mem_3_bits_r_bits_resp_0 = axi4_mem_3_bits_r_bits_resp; // @[ChipTop.scala:33:44] wire axi4_mem_3_bits_r_bits_last_0 = axi4_mem_3_bits_r_bits_last; // @[ChipTop.scala:33:44] wire jtag_TCK_0 = jtag_TCK; // @[ChipTop.scala:33:44] wire jtag_TMS_0 = jtag_TMS; // @[ChipTop.scala:33:44] wire jtag_TDI_0 = jtag_TDI; // @[ChipTop.scala:33:44] wire serial_tl_0_in_valid_0 = serial_tl_0_in_valid; // @[ChipTop.scala:33:44] wire [31:0] serial_tl_0_in_bits_phit_0 = serial_tl_0_in_bits_phit; // @[ChipTop.scala:33:44] wire serial_tl_0_out_ready_0 = serial_tl_0_out_ready; // @[ChipTop.scala:33:44] wire serial_tl_0_clock_in_0 = serial_tl_0_clock_in; // @[ChipTop.scala:33:44] wire clockGroupAggNodeOut_member_allClocks_uncore_clock = clock_uncore; // @[MixedNode.scala:542:17] wire clockGroupAggNodeOut_member_allClocks_uncore_reset = reset_io; // @[MixedNode.scala:542:17] wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire clockGroupAggNodeIn_member_fake_uncore_clock = 1'h0; // @[MixedNode.scala:551:17] wire clockGroupAggNodeIn_member_fake_uncore_reset = 1'h0; // @[MixedNode.scala:551:17] wire clockGroupsSourceNodeOut_member_fake_uncore_clock = 1'h0; // @[MixedNode.scala:542:17] wire clockGroupsSourceNodeOut_member_fake_uncore_reset = 1'h0; // @[MixedNode.scala:542:17] wire _system_debug_systemjtag_reset_catcher_io_psd_WIRE_test_mode = 1'h0; // @[ResetCatchAndSync.scala:41:63] wire _system_debug_systemjtag_reset_catcher_io_psd_WIRE_test_mode_reset = 1'h0; // @[ResetCatchAndSync.scala:41:63] wire _system_debug_systemjtag_reset_catcher_io_psd_WIRE_1_test_mode = 1'h0; // @[ResetCatchAndSync.scala:41:50] wire _system_debug_systemjtag_reset_catcher_io_psd_WIRE_1_test_mode_reset = 1'h0; // @[ResetCatchAndSync.scala:41:50] wire _clock_tap_T; // @[IOCell.scala:248:61] wire clockSinkNodeIn_clock; // @[MixedNode.scala:551:17] wire _iocell_jtag_TCK_io_pad_T = jtag_TCK_0; // @[IOCell.scala:248:44] wire [31:0] _serial_tl_0_out_bits_phit_T; // @[IOCell.scala:312:31] wire _iocell_serial_tl_0_clock_in_io_pad_T = serial_tl_0_clock_in_0; // @[IOCell.scala:248:44] wire uart_0_txd_0; // @[ChipTop.scala:33:44] wire [6:0] axi4_mem_0_bits_aw_bits_id_0; // @[ChipTop.scala:33:44] wire [31:0] axi4_mem_0_bits_aw_bits_addr_0; // @[ChipTop.scala:33:44] wire [7:0] axi4_mem_0_bits_aw_bits_len_0; // @[ChipTop.scala:33:44] wire [2:0] axi4_mem_0_bits_aw_bits_size_0; // @[ChipTop.scala:33:44] wire [1:0] axi4_mem_0_bits_aw_bits_burst_0; // @[ChipTop.scala:33:44] wire axi4_mem_0_bits_aw_bits_lock_0; // @[ChipTop.scala:33:44] wire [3:0] axi4_mem_0_bits_aw_bits_cache_0; // @[ChipTop.scala:33:44] wire [2:0] axi4_mem_0_bits_aw_bits_prot_0; // @[ChipTop.scala:33:44] wire [3:0] axi4_mem_0_bits_aw_bits_qos_0; // @[ChipTop.scala:33:44] wire axi4_mem_0_bits_aw_valid_0; // @[ChipTop.scala:33:44] wire [63:0] axi4_mem_0_bits_w_bits_data_0; // @[ChipTop.scala:33:44] wire [7:0] axi4_mem_0_bits_w_bits_strb_0; // @[ChipTop.scala:33:44] wire axi4_mem_0_bits_w_bits_last_0; // @[ChipTop.scala:33:44] wire axi4_mem_0_bits_w_valid_0; // @[ChipTop.scala:33:44] wire axi4_mem_0_bits_b_ready_0; // @[ChipTop.scala:33:44] wire [6:0] axi4_mem_0_bits_ar_bits_id_0; // @[ChipTop.scala:33:44] wire [31:0] axi4_mem_0_bits_ar_bits_addr_0; // @[ChipTop.scala:33:44] wire [7:0] axi4_mem_0_bits_ar_bits_len_0; // @[ChipTop.scala:33:44] wire [2:0] axi4_mem_0_bits_ar_bits_size_0; // @[ChipTop.scala:33:44] wire [1:0] axi4_mem_0_bits_ar_bits_burst_0; // @[ChipTop.scala:33:44] wire axi4_mem_0_bits_ar_bits_lock_0; // @[ChipTop.scala:33:44] wire [3:0] axi4_mem_0_bits_ar_bits_cache_0; // @[ChipTop.scala:33:44] wire [2:0] axi4_mem_0_bits_ar_bits_prot_0; // @[ChipTop.scala:33:44] wire [3:0] axi4_mem_0_bits_ar_bits_qos_0; // @[ChipTop.scala:33:44] wire axi4_mem_0_bits_ar_valid_0; // @[ChipTop.scala:33:44] wire axi4_mem_0_bits_r_ready_0; // @[ChipTop.scala:33:44] wire axi4_mem_0_clock_0; // @[ChipTop.scala:33:44] wire [6:0] axi4_mem_1_bits_aw_bits_id_0; // @[ChipTop.scala:33:44] wire [31:0] axi4_mem_1_bits_aw_bits_addr_0; // @[ChipTop.scala:33:44] wire [7:0] axi4_mem_1_bits_aw_bits_len_0; // @[ChipTop.scala:33:44] wire [2:0] axi4_mem_1_bits_aw_bits_size_0; // @[ChipTop.scala:33:44] wire [1:0] axi4_mem_1_bits_aw_bits_burst_0; // @[ChipTop.scala:33:44] wire axi4_mem_1_bits_aw_bits_lock_0; // @[ChipTop.scala:33:44] wire [3:0] axi4_mem_1_bits_aw_bits_cache_0; // @[ChipTop.scala:33:44] wire [2:0] axi4_mem_1_bits_aw_bits_prot_0; // @[ChipTop.scala:33:44] wire [3:0] axi4_mem_1_bits_aw_bits_qos_0; // @[ChipTop.scala:33:44] wire axi4_mem_1_bits_aw_valid_0; // @[ChipTop.scala:33:44] wire [63:0] axi4_mem_1_bits_w_bits_data_0; // @[ChipTop.scala:33:44] wire [7:0] axi4_mem_1_bits_w_bits_strb_0; // @[ChipTop.scala:33:44] wire axi4_mem_1_bits_w_bits_last_0; // @[ChipTop.scala:33:44] wire axi4_mem_1_bits_w_valid_0; // @[ChipTop.scala:33:44] wire axi4_mem_1_bits_b_ready_0; // @[ChipTop.scala:33:44] wire [6:0] axi4_mem_1_bits_ar_bits_id_0; // @[ChipTop.scala:33:44] wire [31:0] axi4_mem_1_bits_ar_bits_addr_0; // @[ChipTop.scala:33:44] wire [7:0] axi4_mem_1_bits_ar_bits_len_0; // @[ChipTop.scala:33:44] wire [2:0] axi4_mem_1_bits_ar_bits_size_0; // @[ChipTop.scala:33:44] wire [1:0] axi4_mem_1_bits_ar_bits_burst_0; // @[ChipTop.scala:33:44] wire axi4_mem_1_bits_ar_bits_lock_0; // @[ChipTop.scala:33:44] wire [3:0] axi4_mem_1_bits_ar_bits_cache_0; // @[ChipTop.scala:33:44] wire [2:0] axi4_mem_1_bits_ar_bits_prot_0; // @[ChipTop.scala:33:44] wire [3:0] axi4_mem_1_bits_ar_bits_qos_0; // @[ChipTop.scala:33:44] wire axi4_mem_1_bits_ar_valid_0; // @[ChipTop.scala:33:44] wire axi4_mem_1_bits_r_ready_0; // @[ChipTop.scala:33:44] wire axi4_mem_1_clock_0; // @[ChipTop.scala:33:44] wire [6:0] axi4_mem_2_bits_aw_bits_id_0; // @[ChipTop.scala:33:44] wire [31:0] axi4_mem_2_bits_aw_bits_addr_0; // @[ChipTop.scala:33:44] wire [7:0] axi4_mem_2_bits_aw_bits_len_0; // @[ChipTop.scala:33:44] wire [2:0] axi4_mem_2_bits_aw_bits_size_0; // @[ChipTop.scala:33:44] wire [1:0] axi4_mem_2_bits_aw_bits_burst_0; // @[ChipTop.scala:33:44] wire axi4_mem_2_bits_aw_bits_lock_0; // @[ChipTop.scala:33:44] wire [3:0] axi4_mem_2_bits_aw_bits_cache_0; // @[ChipTop.scala:33:44] wire [2:0] axi4_mem_2_bits_aw_bits_prot_0; // @[ChipTop.scala:33:44] wire [3:0] axi4_mem_2_bits_aw_bits_qos_0; // @[ChipTop.scala:33:44] wire axi4_mem_2_bits_aw_valid_0; // @[ChipTop.scala:33:44] wire [63:0] axi4_mem_2_bits_w_bits_data_0; // @[ChipTop.scala:33:44] wire [7:0] axi4_mem_2_bits_w_bits_strb_0; // @[ChipTop.scala:33:44] wire axi4_mem_2_bits_w_bits_last_0; // @[ChipTop.scala:33:44] wire axi4_mem_2_bits_w_valid_0; // @[ChipTop.scala:33:44] wire axi4_mem_2_bits_b_ready_0; // @[ChipTop.scala:33:44] wire [6:0] axi4_mem_2_bits_ar_bits_id_0; // @[ChipTop.scala:33:44] wire [31:0] axi4_mem_2_bits_ar_bits_addr_0; // @[ChipTop.scala:33:44] wire [7:0] axi4_mem_2_bits_ar_bits_len_0; // @[ChipTop.scala:33:44] wire [2:0] axi4_mem_2_bits_ar_bits_size_0; // @[ChipTop.scala:33:44] wire [1:0] axi4_mem_2_bits_ar_bits_burst_0; // @[ChipTop.scala:33:44] wire axi4_mem_2_bits_ar_bits_lock_0; // @[ChipTop.scala:33:44] wire [3:0] axi4_mem_2_bits_ar_bits_cache_0; // @[ChipTop.scala:33:44] wire [2:0] axi4_mem_2_bits_ar_bits_prot_0; // @[ChipTop.scala:33:44] wire [3:0] axi4_mem_2_bits_ar_bits_qos_0; // @[ChipTop.scala:33:44] wire axi4_mem_2_bits_ar_valid_0; // @[ChipTop.scala:33:44] wire axi4_mem_2_bits_r_ready_0; // @[ChipTop.scala:33:44] wire axi4_mem_2_clock_0; // @[ChipTop.scala:33:44] wire [6:0] axi4_mem_3_bits_aw_bits_id_0; // @[ChipTop.scala:33:44] wire [31:0] axi4_mem_3_bits_aw_bits_addr_0; // @[ChipTop.scala:33:44] wire [7:0] axi4_mem_3_bits_aw_bits_len_0; // @[ChipTop.scala:33:44] wire [2:0] axi4_mem_3_bits_aw_bits_size_0; // @[ChipTop.scala:33:44] wire [1:0] axi4_mem_3_bits_aw_bits_burst_0; // @[ChipTop.scala:33:44] wire axi4_mem_3_bits_aw_bits_lock_0; // @[ChipTop.scala:33:44] wire [3:0] axi4_mem_3_bits_aw_bits_cache_0; // @[ChipTop.scala:33:44] wire [2:0] axi4_mem_3_bits_aw_bits_prot_0; // @[ChipTop.scala:33:44] wire [3:0] axi4_mem_3_bits_aw_bits_qos_0; // @[ChipTop.scala:33:44] wire axi4_mem_3_bits_aw_valid_0; // @[ChipTop.scala:33:44] wire [63:0] axi4_mem_3_bits_w_bits_data_0; // @[ChipTop.scala:33:44] wire [7:0] axi4_mem_3_bits_w_bits_strb_0; // @[ChipTop.scala:33:44] wire axi4_mem_3_bits_w_bits_last_0; // @[ChipTop.scala:33:44] wire axi4_mem_3_bits_w_valid_0; // @[ChipTop.scala:33:44] wire axi4_mem_3_bits_b_ready_0; // @[ChipTop.scala:33:44] wire [6:0] axi4_mem_3_bits_ar_bits_id_0; // @[ChipTop.scala:33:44] wire [31:0] axi4_mem_3_bits_ar_bits_addr_0; // @[ChipTop.scala:33:44] wire [7:0] axi4_mem_3_bits_ar_bits_len_0; // @[ChipTop.scala:33:44] wire [2:0] axi4_mem_3_bits_ar_bits_size_0; // @[ChipTop.scala:33:44] wire [1:0] axi4_mem_3_bits_ar_bits_burst_0; // @[ChipTop.scala:33:44] wire axi4_mem_3_bits_ar_bits_lock_0; // @[ChipTop.scala:33:44] wire [3:0] axi4_mem_3_bits_ar_bits_cache_0; // @[ChipTop.scala:33:44] wire [2:0] axi4_mem_3_bits_ar_bits_prot_0; // @[ChipTop.scala:33:44] wire [3:0] axi4_mem_3_bits_ar_bits_qos_0; // @[ChipTop.scala:33:44] wire axi4_mem_3_bits_ar_valid_0; // @[ChipTop.scala:33:44] wire axi4_mem_3_bits_r_ready_0; // @[ChipTop.scala:33:44] wire axi4_mem_3_clock_0; // @[ChipTop.scala:33:44] wire jtag_TDO_0; // @[ChipTop.scala:33:44] wire _clock_tap_output; // @[ChipTop.scala:33:44] wire serial_tl_0_in_ready_0; // @[ChipTop.scala:33:44] wire [31:0] serial_tl_0_out_bits_phit_0; // @[ChipTop.scala:33:44] wire serial_tl_0_out_valid_0; // @[ChipTop.scala:33:44] assign axi4_mem_0_clock_0 = clockSinkNodeIn_clock; // @[MixedNode.scala:551:17] assign axi4_mem_1_clock_0 = clockSinkNodeIn_clock; // @[MixedNode.scala:551:17] assign axi4_mem_2_clock_0 = clockSinkNodeIn_clock; // @[MixedNode.scala:551:17] assign axi4_mem_3_clock_0 = clockSinkNodeIn_clock; // @[MixedNode.scala:551:17] wire clockSinkNodeIn_reset; // @[MixedNode.scala:551:17] wire clockSinkNodeIn_1_clock; // @[MixedNode.scala:551:17] wire clockSinkNodeIn_1_reset; // @[MixedNode.scala:551:17] wire _system_resetctrl_hartIsInReset_0_T = clockSinkNodeIn_1_reset; // @[MixedNode.scala:551:17] wire _system_debug_systemjtag_reset_T = clockSinkNodeIn_1_reset; // @[MixedNode.scala:551:17] wire _dmi_reset_T; // @[Periphery.scala:281:38] wire _dmi_reset_T_1 = _dmi_reset_T; // @[Periphery.scala:280:82, :281:38] wire dmi_reset = _dmi_reset_T_1; // @[Periphery.scala:280:82, :281:65] wire debug_reset_syncd; // @[Periphery.scala:290:40] wire debug_reset; // @[Periphery.scala:288:27] wire _debug_reset_syncd_WIRE; // @[ShiftReg.scala:48:24] assign debug_reset_syncd = ~_debug_reset_syncd_WIRE; // @[ShiftReg.scala:48:24] assign debug_reset = debug_reset_syncd; // @[Periphery.scala:288:27, :290:40] wire dmactiveAck; // @[ShiftReg.scala:48:24] reg clock_en; // @[Periphery.scala:298:29] wire _jtag_wire_TCK_T; // @[IOCell.scala:248:61] wire jtag_wire_TCK; // @[IOBinders.scala:339:31] wire jtag_wire_TMS; // @[IOBinders.scala:339:31] wire jtag_wire_TDI; // @[IOBinders.scala:339:31] wire jtag_wire_TDO; // @[IOBinders.scala:339:31] assign jtag_wire_TCK = _jtag_wire_TCK_T; // @[IOCell.scala:248:61] wire _iocell_jtag_TCK_io_pad_T_1 = _iocell_jtag_TCK_io_pad_T; // @[IOCell.scala:248:{44,51}] wire _iocell_clock_tap_io_o_T; // @[IOCell.scala:248:44] wire _iocell_clock_tap_io_o_T_1 = _iocell_clock_tap_io_o_T; // @[IOCell.scala:248:{44,51}] assign _clock_tap_output = _clock_tap_T; // @[IOCell.scala:248:61] wire _iocell_serial_tl_0_clock_in_io_pad_T_1 = _iocell_serial_tl_0_clock_in_io_pad_T; // @[IOCell.scala:248:{44,51}] wire [1:0] serial_tl_0_out_bits_phit_lo_lo_lo_lo = {_iocell_serial_tl_0_out_bits_phit_1_pad, _iocell_serial_tl_0_out_bits_phit_pad}; // @[IOCell.scala:177:24, :312:31] wire [1:0] serial_tl_0_out_bits_phit_lo_lo_lo_hi = {_iocell_serial_tl_0_out_bits_phit_3_pad, _iocell_serial_tl_0_out_bits_phit_2_pad}; // @[IOCell.scala:177:24, :312:31] wire [3:0] serial_tl_0_out_bits_phit_lo_lo_lo = {serial_tl_0_out_bits_phit_lo_lo_lo_hi, serial_tl_0_out_bits_phit_lo_lo_lo_lo}; // @[IOCell.scala:312:31] wire [1:0] serial_tl_0_out_bits_phit_lo_lo_hi_lo = {_iocell_serial_tl_0_out_bits_phit_5_pad, _iocell_serial_tl_0_out_bits_phit_4_pad}; // @[IOCell.scala:177:24, :312:31] wire [1:0] serial_tl_0_out_bits_phit_lo_lo_hi_hi = {_iocell_serial_tl_0_out_bits_phit_7_pad, _iocell_serial_tl_0_out_bits_phit_6_pad}; // @[IOCell.scala:177:24, :312:31] wire [3:0] serial_tl_0_out_bits_phit_lo_lo_hi = {serial_tl_0_out_bits_phit_lo_lo_hi_hi, serial_tl_0_out_bits_phit_lo_lo_hi_lo}; // @[IOCell.scala:312:31] wire [7:0] serial_tl_0_out_bits_phit_lo_lo = {serial_tl_0_out_bits_phit_lo_lo_hi, serial_tl_0_out_bits_phit_lo_lo_lo}; // @[IOCell.scala:312:31] wire [1:0] serial_tl_0_out_bits_phit_lo_hi_lo_lo = {_iocell_serial_tl_0_out_bits_phit_9_pad, _iocell_serial_tl_0_out_bits_phit_8_pad}; // @[IOCell.scala:177:24, :312:31] wire [1:0] serial_tl_0_out_bits_phit_lo_hi_lo_hi = {_iocell_serial_tl_0_out_bits_phit_11_pad, _iocell_serial_tl_0_out_bits_phit_10_pad}; // @[IOCell.scala:177:24, :312:31] wire [3:0] serial_tl_0_out_bits_phit_lo_hi_lo = {serial_tl_0_out_bits_phit_lo_hi_lo_hi, serial_tl_0_out_bits_phit_lo_hi_lo_lo}; // @[IOCell.scala:312:31] wire [1:0] serial_tl_0_out_bits_phit_lo_hi_hi_lo = {_iocell_serial_tl_0_out_bits_phit_13_pad, _iocell_serial_tl_0_out_bits_phit_12_pad}; // @[IOCell.scala:177:24, :312:31] wire [1:0] serial_tl_0_out_bits_phit_lo_hi_hi_hi = {_iocell_serial_tl_0_out_bits_phit_15_pad, _iocell_serial_tl_0_out_bits_phit_14_pad}; // @[IOCell.scala:177:24, :312:31] wire [3:0] serial_tl_0_out_bits_phit_lo_hi_hi = {serial_tl_0_out_bits_phit_lo_hi_hi_hi, serial_tl_0_out_bits_phit_lo_hi_hi_lo}; // @[IOCell.scala:312:31] wire [7:0] serial_tl_0_out_bits_phit_lo_hi = {serial_tl_0_out_bits_phit_lo_hi_hi, serial_tl_0_out_bits_phit_lo_hi_lo}; // @[IOCell.scala:312:31] wire [15:0] serial_tl_0_out_bits_phit_lo = {serial_tl_0_out_bits_phit_lo_hi, serial_tl_0_out_bits_phit_lo_lo}; // @[IOCell.scala:312:31] wire [1:0] serial_tl_0_out_bits_phit_hi_lo_lo_lo = {_iocell_serial_tl_0_out_bits_phit_17_pad, _iocell_serial_tl_0_out_bits_phit_16_pad}; // @[IOCell.scala:177:24, :312:31] wire [1:0] serial_tl_0_out_bits_phit_hi_lo_lo_hi = {_iocell_serial_tl_0_out_bits_phit_19_pad, _iocell_serial_tl_0_out_bits_phit_18_pad}; // @[IOCell.scala:177:24, :312:31] wire [3:0] serial_tl_0_out_bits_phit_hi_lo_lo = {serial_tl_0_out_bits_phit_hi_lo_lo_hi, serial_tl_0_out_bits_phit_hi_lo_lo_lo}; // @[IOCell.scala:312:31] wire [1:0] serial_tl_0_out_bits_phit_hi_lo_hi_lo = {_iocell_serial_tl_0_out_bits_phit_21_pad, _iocell_serial_tl_0_out_bits_phit_20_pad}; // @[IOCell.scala:177:24, :312:31] wire [1:0] serial_tl_0_out_bits_phit_hi_lo_hi_hi = {_iocell_serial_tl_0_out_bits_phit_23_pad, _iocell_serial_tl_0_out_bits_phit_22_pad}; // @[IOCell.scala:177:24, :312:31] wire [3:0] serial_tl_0_out_bits_phit_hi_lo_hi = {serial_tl_0_out_bits_phit_hi_lo_hi_hi, serial_tl_0_out_bits_phit_hi_lo_hi_lo}; // @[IOCell.scala:312:31] wire [7:0] serial_tl_0_out_bits_phit_hi_lo = {serial_tl_0_out_bits_phit_hi_lo_hi, serial_tl_0_out_bits_phit_hi_lo_lo}; // @[IOCell.scala:312:31] wire [1:0] serial_tl_0_out_bits_phit_hi_hi_lo_lo = {_iocell_serial_tl_0_out_bits_phit_25_pad, _iocell_serial_tl_0_out_bits_phit_24_pad}; // @[IOCell.scala:177:24, :312:31] wire [1:0] serial_tl_0_out_bits_phit_hi_hi_lo_hi = {_iocell_serial_tl_0_out_bits_phit_27_pad, _iocell_serial_tl_0_out_bits_phit_26_pad}; // @[IOCell.scala:177:24, :312:31] wire [3:0] serial_tl_0_out_bits_phit_hi_hi_lo = {serial_tl_0_out_bits_phit_hi_hi_lo_hi, serial_tl_0_out_bits_phit_hi_hi_lo_lo}; // @[IOCell.scala:312:31] wire [1:0] serial_tl_0_out_bits_phit_hi_hi_hi_lo = {_iocell_serial_tl_0_out_bits_phit_29_pad, _iocell_serial_tl_0_out_bits_phit_28_pad}; // @[IOCell.scala:177:24, :312:31] wire [1:0] serial_tl_0_out_bits_phit_hi_hi_hi_hi = {_iocell_serial_tl_0_out_bits_phit_31_pad, _iocell_serial_tl_0_out_bits_phit_30_pad}; // @[IOCell.scala:177:24, :312:31] wire [3:0] serial_tl_0_out_bits_phit_hi_hi_hi = {serial_tl_0_out_bits_phit_hi_hi_hi_hi, serial_tl_0_out_bits_phit_hi_hi_hi_lo}; // @[IOCell.scala:312:31] wire [7:0] serial_tl_0_out_bits_phit_hi_hi = {serial_tl_0_out_bits_phit_hi_hi_hi, serial_tl_0_out_bits_phit_hi_hi_lo}; // @[IOCell.scala:312:31] wire [15:0] serial_tl_0_out_bits_phit_hi = {serial_tl_0_out_bits_phit_hi_hi, serial_tl_0_out_bits_phit_hi_lo}; // @[IOCell.scala:312:31] assign _serial_tl_0_out_bits_phit_T = {serial_tl_0_out_bits_phit_hi, serial_tl_0_out_bits_phit_lo}; // @[IOCell.scala:312:31] assign serial_tl_0_out_bits_phit_0 = _serial_tl_0_out_bits_phit_T; // @[IOCell.scala:312:31] wire [1:0] system_serial_tl_0_in_bits_phit_lo_lo_lo_lo = {_iocell_serial_tl_0_in_bits_phit_1_i, _iocell_serial_tl_0_in_bits_phit_i}; // @[IOCell.scala:176:23, :295:32] wire [1:0] system_serial_tl_0_in_bits_phit_lo_lo_lo_hi = {_iocell_serial_tl_0_in_bits_phit_3_i, _iocell_serial_tl_0_in_bits_phit_2_i}; // @[IOCell.scala:176:23, :295:32] wire [3:0] system_serial_tl_0_in_bits_phit_lo_lo_lo = {system_serial_tl_0_in_bits_phit_lo_lo_lo_hi, system_serial_tl_0_in_bits_phit_lo_lo_lo_lo}; // @[IOCell.scala:295:32] wire [1:0] system_serial_tl_0_in_bits_phit_lo_lo_hi_lo = {_iocell_serial_tl_0_in_bits_phit_5_i, _iocell_serial_tl_0_in_bits_phit_4_i}; // @[IOCell.scala:176:23, :295:32] wire [1:0] system_serial_tl_0_in_bits_phit_lo_lo_hi_hi = {_iocell_serial_tl_0_in_bits_phit_7_i, _iocell_serial_tl_0_in_bits_phit_6_i}; // @[IOCell.scala:176:23, :295:32] wire [3:0] system_serial_tl_0_in_bits_phit_lo_lo_hi = {system_serial_tl_0_in_bits_phit_lo_lo_hi_hi, system_serial_tl_0_in_bits_phit_lo_lo_hi_lo}; // @[IOCell.scala:295:32] wire [7:0] system_serial_tl_0_in_bits_phit_lo_lo = {system_serial_tl_0_in_bits_phit_lo_lo_hi, system_serial_tl_0_in_bits_phit_lo_lo_lo}; // @[IOCell.scala:295:32] wire [1:0] system_serial_tl_0_in_bits_phit_lo_hi_lo_lo = {_iocell_serial_tl_0_in_bits_phit_9_i, _iocell_serial_tl_0_in_bits_phit_8_i}; // @[IOCell.scala:176:23, :295:32] wire [1:0] system_serial_tl_0_in_bits_phit_lo_hi_lo_hi = {_iocell_serial_tl_0_in_bits_phit_11_i, _iocell_serial_tl_0_in_bits_phit_10_i}; // @[IOCell.scala:176:23, :295:32] wire [3:0] system_serial_tl_0_in_bits_phit_lo_hi_lo = {system_serial_tl_0_in_bits_phit_lo_hi_lo_hi, system_serial_tl_0_in_bits_phit_lo_hi_lo_lo}; // @[IOCell.scala:295:32] wire [1:0] system_serial_tl_0_in_bits_phit_lo_hi_hi_lo = {_iocell_serial_tl_0_in_bits_phit_13_i, _iocell_serial_tl_0_in_bits_phit_12_i}; // @[IOCell.scala:176:23, :295:32] wire [1:0] system_serial_tl_0_in_bits_phit_lo_hi_hi_hi = {_iocell_serial_tl_0_in_bits_phit_15_i, _iocell_serial_tl_0_in_bits_phit_14_i}; // @[IOCell.scala:176:23, :295:32] wire [3:0] system_serial_tl_0_in_bits_phit_lo_hi_hi = {system_serial_tl_0_in_bits_phit_lo_hi_hi_hi, system_serial_tl_0_in_bits_phit_lo_hi_hi_lo}; // @[IOCell.scala:295:32] wire [7:0] system_serial_tl_0_in_bits_phit_lo_hi = {system_serial_tl_0_in_bits_phit_lo_hi_hi, system_serial_tl_0_in_bits_phit_lo_hi_lo}; // @[IOCell.scala:295:32] wire [15:0] system_serial_tl_0_in_bits_phit_lo = {system_serial_tl_0_in_bits_phit_lo_hi, system_serial_tl_0_in_bits_phit_lo_lo}; // @[IOCell.scala:295:32] wire [1:0] system_serial_tl_0_in_bits_phit_hi_lo_lo_lo = {_iocell_serial_tl_0_in_bits_phit_17_i, _iocell_serial_tl_0_in_bits_phit_16_i}; // @[IOCell.scala:176:23, :295:32] wire [1:0] system_serial_tl_0_in_bits_phit_hi_lo_lo_hi = {_iocell_serial_tl_0_in_bits_phit_19_i, _iocell_serial_tl_0_in_bits_phit_18_i}; // @[IOCell.scala:176:23, :295:32] wire [3:0] system_serial_tl_0_in_bits_phit_hi_lo_lo = {system_serial_tl_0_in_bits_phit_hi_lo_lo_hi, system_serial_tl_0_in_bits_phit_hi_lo_lo_lo}; // @[IOCell.scala:295:32] wire [1:0] system_serial_tl_0_in_bits_phit_hi_lo_hi_lo = {_iocell_serial_tl_0_in_bits_phit_21_i, _iocell_serial_tl_0_in_bits_phit_20_i}; // @[IOCell.scala:176:23, :295:32] wire [1:0] system_serial_tl_0_in_bits_phit_hi_lo_hi_hi = {_iocell_serial_tl_0_in_bits_phit_23_i, _iocell_serial_tl_0_in_bits_phit_22_i}; // @[IOCell.scala:176:23, :295:32] wire [3:0] system_serial_tl_0_in_bits_phit_hi_lo_hi = {system_serial_tl_0_in_bits_phit_hi_lo_hi_hi, system_serial_tl_0_in_bits_phit_hi_lo_hi_lo}; // @[IOCell.scala:295:32] wire [7:0] system_serial_tl_0_in_bits_phit_hi_lo = {system_serial_tl_0_in_bits_phit_hi_lo_hi, system_serial_tl_0_in_bits_phit_hi_lo_lo}; // @[IOCell.scala:295:32] wire [1:0] system_serial_tl_0_in_bits_phit_hi_hi_lo_lo = {_iocell_serial_tl_0_in_bits_phit_25_i, _iocell_serial_tl_0_in_bits_phit_24_i}; // @[IOCell.scala:176:23, :295:32] wire [1:0] system_serial_tl_0_in_bits_phit_hi_hi_lo_hi = {_iocell_serial_tl_0_in_bits_phit_27_i, _iocell_serial_tl_0_in_bits_phit_26_i}; // @[IOCell.scala:176:23, :295:32] wire [3:0] system_serial_tl_0_in_bits_phit_hi_hi_lo = {system_serial_tl_0_in_bits_phit_hi_hi_lo_hi, system_serial_tl_0_in_bits_phit_hi_hi_lo_lo}; // @[IOCell.scala:295:32] wire [1:0] system_serial_tl_0_in_bits_phit_hi_hi_hi_lo = {_iocell_serial_tl_0_in_bits_phit_29_i, _iocell_serial_tl_0_in_bits_phit_28_i}; // @[IOCell.scala:176:23, :295:32] wire [1:0] system_serial_tl_0_in_bits_phit_hi_hi_hi_hi = {_iocell_serial_tl_0_in_bits_phit_31_i, _iocell_serial_tl_0_in_bits_phit_30_i}; // @[IOCell.scala:176:23, :295:32] wire [3:0] system_serial_tl_0_in_bits_phit_hi_hi_hi = {system_serial_tl_0_in_bits_phit_hi_hi_hi_hi, system_serial_tl_0_in_bits_phit_hi_hi_hi_lo}; // @[IOCell.scala:295:32] wire [7:0] system_serial_tl_0_in_bits_phit_hi_hi = {system_serial_tl_0_in_bits_phit_hi_hi_hi, system_serial_tl_0_in_bits_phit_hi_hi_lo}; // @[IOCell.scala:295:32] wire [15:0] system_serial_tl_0_in_bits_phit_hi = {system_serial_tl_0_in_bits_phit_hi_hi, system_serial_tl_0_in_bits_phit_hi_lo}; // @[IOCell.scala:295:32] wire [31:0] _system_serial_tl_0_in_bits_phit_T = {system_serial_tl_0_in_bits_phit_hi, system_serial_tl_0_in_bits_phit_lo}; // @[IOCell.scala:295:32] always @(posedge clockSinkNodeIn_1_clock or posedge debug_reset) begin // @[Periphery.scala:288:27] if (debug_reset) // @[Periphery.scala:288:27] clock_en <= 1'h1; // @[Periphery.scala:298:29] else // @[MixedNode.scala:551:17] clock_en <= dmactiveAck; // @[ShiftReg.scala:48:24] always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module Router_45 : input clock : Clock input reset : Reset output auto : { debug_out : { va_stall : UInt[3], sa_stall : UInt[3]}, source_nodes_out_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}, source_nodes_out_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}, source_nodes_out_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}, flip dest_nodes_in_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}, flip dest_nodes_in_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}, flip dest_nodes_in_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}} wire destNodesIn : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>} invalidate destNodesIn.vc_free invalidate destNodesIn.credit_return invalidate destNodesIn.flit[0].bits.virt_channel_id invalidate destNodesIn.flit[0].bits.flow.egress_node_id invalidate destNodesIn.flit[0].bits.flow.egress_node invalidate destNodesIn.flit[0].bits.flow.ingress_node_id invalidate destNodesIn.flit[0].bits.flow.ingress_node invalidate destNodesIn.flit[0].bits.flow.vnet_id invalidate destNodesIn.flit[0].bits.payload invalidate destNodesIn.flit[0].bits.tail invalidate destNodesIn.flit[0].bits.head invalidate destNodesIn.flit[0].valid inst monitor of NoCMonitor_101 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.vc_free, destNodesIn.vc_free connect monitor.io.in.credit_return, destNodesIn.credit_return connect monitor.io.in.flit[0].bits.virt_channel_id, destNodesIn.flit[0].bits.virt_channel_id connect monitor.io.in.flit[0].bits.flow.egress_node_id, destNodesIn.flit[0].bits.flow.egress_node_id connect monitor.io.in.flit[0].bits.flow.egress_node, destNodesIn.flit[0].bits.flow.egress_node connect monitor.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn.flit[0].bits.flow.ingress_node_id connect monitor.io.in.flit[0].bits.flow.ingress_node, destNodesIn.flit[0].bits.flow.ingress_node connect monitor.io.in.flit[0].bits.flow.vnet_id, destNodesIn.flit[0].bits.flow.vnet_id connect monitor.io.in.flit[0].bits.payload, destNodesIn.flit[0].bits.payload connect monitor.io.in.flit[0].bits.tail, destNodesIn.flit[0].bits.tail connect monitor.io.in.flit[0].bits.head, destNodesIn.flit[0].bits.head connect monitor.io.in.flit[0].valid, destNodesIn.flit[0].valid wire destNodesIn_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>} invalidate destNodesIn_1.vc_free invalidate destNodesIn_1.credit_return invalidate destNodesIn_1.flit[0].bits.virt_channel_id invalidate destNodesIn_1.flit[0].bits.flow.egress_node_id invalidate destNodesIn_1.flit[0].bits.flow.egress_node invalidate destNodesIn_1.flit[0].bits.flow.ingress_node_id invalidate destNodesIn_1.flit[0].bits.flow.ingress_node invalidate destNodesIn_1.flit[0].bits.flow.vnet_id invalidate destNodesIn_1.flit[0].bits.payload invalidate destNodesIn_1.flit[0].bits.tail invalidate destNodesIn_1.flit[0].bits.head invalidate destNodesIn_1.flit[0].valid inst monitor_1 of NoCMonitor_102 connect monitor_1.clock, clock connect monitor_1.reset, reset connect monitor_1.io.in.vc_free, destNodesIn_1.vc_free connect monitor_1.io.in.credit_return, destNodesIn_1.credit_return connect monitor_1.io.in.flit[0].bits.virt_channel_id, destNodesIn_1.flit[0].bits.virt_channel_id connect monitor_1.io.in.flit[0].bits.flow.egress_node_id, destNodesIn_1.flit[0].bits.flow.egress_node_id connect monitor_1.io.in.flit[0].bits.flow.egress_node, destNodesIn_1.flit[0].bits.flow.egress_node connect monitor_1.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn_1.flit[0].bits.flow.ingress_node_id connect monitor_1.io.in.flit[0].bits.flow.ingress_node, destNodesIn_1.flit[0].bits.flow.ingress_node connect monitor_1.io.in.flit[0].bits.flow.vnet_id, destNodesIn_1.flit[0].bits.flow.vnet_id connect monitor_1.io.in.flit[0].bits.payload, destNodesIn_1.flit[0].bits.payload connect monitor_1.io.in.flit[0].bits.tail, destNodesIn_1.flit[0].bits.tail connect monitor_1.io.in.flit[0].bits.head, destNodesIn_1.flit[0].bits.head connect monitor_1.io.in.flit[0].valid, destNodesIn_1.flit[0].valid wire destNodesIn_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>} invalidate destNodesIn_2.vc_free invalidate destNodesIn_2.credit_return invalidate destNodesIn_2.flit[0].bits.virt_channel_id invalidate destNodesIn_2.flit[0].bits.flow.egress_node_id invalidate destNodesIn_2.flit[0].bits.flow.egress_node invalidate destNodesIn_2.flit[0].bits.flow.ingress_node_id invalidate destNodesIn_2.flit[0].bits.flow.ingress_node invalidate destNodesIn_2.flit[0].bits.flow.vnet_id invalidate destNodesIn_2.flit[0].bits.payload invalidate destNodesIn_2.flit[0].bits.tail invalidate destNodesIn_2.flit[0].bits.head invalidate destNodesIn_2.flit[0].valid inst monitor_2 of NoCMonitor_103 connect monitor_2.clock, clock connect monitor_2.reset, reset connect monitor_2.io.in.vc_free, destNodesIn_2.vc_free connect monitor_2.io.in.credit_return, destNodesIn_2.credit_return connect monitor_2.io.in.flit[0].bits.virt_channel_id, destNodesIn_2.flit[0].bits.virt_channel_id connect monitor_2.io.in.flit[0].bits.flow.egress_node_id, destNodesIn_2.flit[0].bits.flow.egress_node_id connect monitor_2.io.in.flit[0].bits.flow.egress_node, destNodesIn_2.flit[0].bits.flow.egress_node connect monitor_2.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn_2.flit[0].bits.flow.ingress_node_id connect monitor_2.io.in.flit[0].bits.flow.ingress_node, destNodesIn_2.flit[0].bits.flow.ingress_node connect monitor_2.io.in.flit[0].bits.flow.vnet_id, destNodesIn_2.flit[0].bits.flow.vnet_id connect monitor_2.io.in.flit[0].bits.payload, destNodesIn_2.flit[0].bits.payload connect monitor_2.io.in.flit[0].bits.tail, destNodesIn_2.flit[0].bits.tail connect monitor_2.io.in.flit[0].bits.head, destNodesIn_2.flit[0].bits.head connect monitor_2.io.in.flit[0].valid, destNodesIn_2.flit[0].valid wire sourceNodesOut : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>} invalidate sourceNodesOut.vc_free invalidate sourceNodesOut.credit_return invalidate sourceNodesOut.flit[0].bits.virt_channel_id invalidate sourceNodesOut.flit[0].bits.flow.egress_node_id invalidate sourceNodesOut.flit[0].bits.flow.egress_node invalidate sourceNodesOut.flit[0].bits.flow.ingress_node_id invalidate sourceNodesOut.flit[0].bits.flow.ingress_node invalidate sourceNodesOut.flit[0].bits.flow.vnet_id invalidate sourceNodesOut.flit[0].bits.payload invalidate sourceNodesOut.flit[0].bits.tail invalidate sourceNodesOut.flit[0].bits.head invalidate sourceNodesOut.flit[0].valid wire sourceNodesOut_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>} invalidate sourceNodesOut_1.vc_free invalidate sourceNodesOut_1.credit_return invalidate sourceNodesOut_1.flit[0].bits.virt_channel_id invalidate sourceNodesOut_1.flit[0].bits.flow.egress_node_id invalidate sourceNodesOut_1.flit[0].bits.flow.egress_node invalidate sourceNodesOut_1.flit[0].bits.flow.ingress_node_id invalidate sourceNodesOut_1.flit[0].bits.flow.ingress_node invalidate sourceNodesOut_1.flit[0].bits.flow.vnet_id invalidate sourceNodesOut_1.flit[0].bits.payload invalidate sourceNodesOut_1.flit[0].bits.tail invalidate sourceNodesOut_1.flit[0].bits.head invalidate sourceNodesOut_1.flit[0].valid wire sourceNodesOut_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>} invalidate sourceNodesOut_2.vc_free invalidate sourceNodesOut_2.credit_return invalidate sourceNodesOut_2.flit[0].bits.virt_channel_id invalidate sourceNodesOut_2.flit[0].bits.flow.egress_node_id invalidate sourceNodesOut_2.flit[0].bits.flow.egress_node invalidate sourceNodesOut_2.flit[0].bits.flow.ingress_node_id invalidate sourceNodesOut_2.flit[0].bits.flow.ingress_node invalidate sourceNodesOut_2.flit[0].bits.flow.vnet_id invalidate sourceNodesOut_2.flit[0].bits.payload invalidate sourceNodesOut_2.flit[0].bits.tail invalidate sourceNodesOut_2.flit[0].bits.head invalidate sourceNodesOut_2.flit[0].valid wire debugNodeOut : { va_stall : UInt[3], sa_stall : UInt[3]} invalidate debugNodeOut.sa_stall[0] invalidate debugNodeOut.sa_stall[1] invalidate debugNodeOut.sa_stall[2] invalidate debugNodeOut.va_stall[0] invalidate debugNodeOut.va_stall[1] invalidate debugNodeOut.va_stall[2] connect destNodesIn, auto.dest_nodes_in_0 connect destNodesIn_1, auto.dest_nodes_in_1 connect destNodesIn_2, auto.dest_nodes_in_2 connect auto.source_nodes_out_0, sourceNodesOut connect auto.source_nodes_out_1, sourceNodesOut_1 connect auto.source_nodes_out_2, sourceNodesOut_2 connect auto.debug_out, debugNodeOut inst input_unit_0_from_7 of InputUnit_101 connect input_unit_0_from_7.clock, clock connect input_unit_0_from_7.reset, reset inst input_unit_1_from_15 of InputUnit_102 connect input_unit_1_from_15.clock, clock connect input_unit_1_from_15.reset, reset inst input_unit_2_from_17 of InputUnit_103 connect input_unit_2_from_17.clock, clock connect input_unit_2_from_17.reset, reset inst output_unit_0_to_7 of OutputUnit_101 connect output_unit_0_to_7.clock, clock connect output_unit_0_to_7.reset, reset inst output_unit_1_to_15 of OutputUnit_102 connect output_unit_1_to_15.clock, clock connect output_unit_1_to_15.reset, reset inst output_unit_2_to_17 of OutputUnit_103 connect output_unit_2_to_17.clock, clock connect output_unit_2_to_17.reset, reset inst switch of Switch_45 connect switch.clock, clock connect switch.reset, reset inst switch_allocator of SwitchAllocator_45 connect switch_allocator.clock, clock connect switch_allocator.reset, reset inst vc_allocator of RotatingSingleVCAllocator_45 connect vc_allocator.clock, clock connect vc_allocator.reset, reset inst route_computer of RouteComputer_45 connect route_computer.clock, clock connect route_computer.reset, reset node _fires_count_T = and(vc_allocator.io.req.`0`.ready, vc_allocator.io.req.`0`.valid) node _fires_count_T_1 = and(vc_allocator.io.req.`1`.ready, vc_allocator.io.req.`1`.valid) node _fires_count_T_2 = and(vc_allocator.io.req.`2`.ready, vc_allocator.io.req.`2`.valid) node _fires_count_T_3 = add(_fires_count_T_1, _fires_count_T_2) node _fires_count_T_4 = bits(_fires_count_T_3, 1, 0) node _fires_count_T_5 = add(_fires_count_T, _fires_count_T_4) node _fires_count_T_6 = bits(_fires_count_T_5, 1, 0) wire fires_count : UInt connect fires_count, _fires_count_T_6 connect input_unit_0_from_7.io.in, destNodesIn connect input_unit_1_from_15.io.in, destNodesIn_1 connect input_unit_2_from_17.io.in, destNodesIn_2 connect output_unit_0_to_7.io.out.vc_free, sourceNodesOut.vc_free connect output_unit_0_to_7.io.out.credit_return, sourceNodesOut.credit_return connect sourceNodesOut.flit, output_unit_0_to_7.io.out.flit connect output_unit_1_to_15.io.out.vc_free, sourceNodesOut_1.vc_free connect output_unit_1_to_15.io.out.credit_return, sourceNodesOut_1.credit_return connect sourceNodesOut_1.flit, output_unit_1_to_15.io.out.flit connect output_unit_2_to_17.io.out.vc_free, sourceNodesOut_2.vc_free connect output_unit_2_to_17.io.out.credit_return, sourceNodesOut_2.credit_return connect sourceNodesOut_2.flit, output_unit_2_to_17.io.out.flit connect route_computer.io.req.`0`, input_unit_0_from_7.io.router_req connect route_computer.io.req.`1`, input_unit_1_from_15.io.router_req connect route_computer.io.req.`2`, input_unit_2_from_17.io.router_req connect input_unit_0_from_7.io.router_resp, route_computer.io.resp.`0` connect input_unit_1_from_15.io.router_resp, route_computer.io.resp.`1` connect input_unit_2_from_17.io.router_resp, route_computer.io.resp.`2` connect vc_allocator.io.req.`0`, input_unit_0_from_7.io.vcalloc_req connect vc_allocator.io.req.`1`, input_unit_1_from_15.io.vcalloc_req connect vc_allocator.io.req.`2`, input_unit_2_from_17.io.vcalloc_req connect input_unit_0_from_7.io.vcalloc_resp, vc_allocator.io.resp.`0` connect input_unit_1_from_15.io.vcalloc_resp, vc_allocator.io.resp.`1` connect input_unit_2_from_17.io.vcalloc_resp, vc_allocator.io.resp.`2` connect output_unit_0_to_7.io.allocs, vc_allocator.io.out_allocs.`0` connect output_unit_1_to_15.io.allocs, vc_allocator.io.out_allocs.`1` connect output_unit_2_to_17.io.allocs, vc_allocator.io.out_allocs.`2` connect vc_allocator.io.channel_status.`0`[0].flow.egress_node_id, output_unit_0_to_7.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[0].flow.egress_node, output_unit_0_to_7.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node_id, output_unit_0_to_7.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node, output_unit_0_to_7.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`0`[0].flow.vnet_id, output_unit_0_to_7.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`0`[0].occupied, output_unit_0_to_7.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`0`[1].flow.egress_node_id, output_unit_0_to_7.io.channel_status[1].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[1].flow.egress_node, output_unit_0_to_7.io.channel_status[1].flow.egress_node connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node_id, output_unit_0_to_7.io.channel_status[1].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node, output_unit_0_to_7.io.channel_status[1].flow.ingress_node connect vc_allocator.io.channel_status.`0`[1].flow.vnet_id, output_unit_0_to_7.io.channel_status[1].flow.vnet_id connect vc_allocator.io.channel_status.`0`[1].occupied, output_unit_0_to_7.io.channel_status[1].occupied connect vc_allocator.io.channel_status.`0`[2].flow.egress_node_id, output_unit_0_to_7.io.channel_status[2].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[2].flow.egress_node, output_unit_0_to_7.io.channel_status[2].flow.egress_node connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node_id, output_unit_0_to_7.io.channel_status[2].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node, output_unit_0_to_7.io.channel_status[2].flow.ingress_node connect vc_allocator.io.channel_status.`0`[2].flow.vnet_id, output_unit_0_to_7.io.channel_status[2].flow.vnet_id connect vc_allocator.io.channel_status.`0`[2].occupied, output_unit_0_to_7.io.channel_status[2].occupied connect vc_allocator.io.channel_status.`0`[3].flow.egress_node_id, output_unit_0_to_7.io.channel_status[3].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[3].flow.egress_node, output_unit_0_to_7.io.channel_status[3].flow.egress_node connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node_id, output_unit_0_to_7.io.channel_status[3].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node, output_unit_0_to_7.io.channel_status[3].flow.ingress_node connect vc_allocator.io.channel_status.`0`[3].flow.vnet_id, output_unit_0_to_7.io.channel_status[3].flow.vnet_id connect vc_allocator.io.channel_status.`0`[3].occupied, output_unit_0_to_7.io.channel_status[3].occupied connect vc_allocator.io.channel_status.`0`[4].flow.egress_node_id, output_unit_0_to_7.io.channel_status[4].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[4].flow.egress_node, output_unit_0_to_7.io.channel_status[4].flow.egress_node connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node_id, output_unit_0_to_7.io.channel_status[4].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node, output_unit_0_to_7.io.channel_status[4].flow.ingress_node connect vc_allocator.io.channel_status.`0`[4].flow.vnet_id, output_unit_0_to_7.io.channel_status[4].flow.vnet_id connect vc_allocator.io.channel_status.`0`[4].occupied, output_unit_0_to_7.io.channel_status[4].occupied connect vc_allocator.io.channel_status.`1`[0].flow.egress_node_id, output_unit_1_to_15.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[0].flow.egress_node, output_unit_1_to_15.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node_id, output_unit_1_to_15.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node, output_unit_1_to_15.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`1`[0].flow.vnet_id, output_unit_1_to_15.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`1`[0].occupied, output_unit_1_to_15.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`1`[1].flow.egress_node_id, output_unit_1_to_15.io.channel_status[1].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[1].flow.egress_node, output_unit_1_to_15.io.channel_status[1].flow.egress_node connect vc_allocator.io.channel_status.`1`[1].flow.ingress_node_id, output_unit_1_to_15.io.channel_status[1].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[1].flow.ingress_node, output_unit_1_to_15.io.channel_status[1].flow.ingress_node connect vc_allocator.io.channel_status.`1`[1].flow.vnet_id, output_unit_1_to_15.io.channel_status[1].flow.vnet_id connect vc_allocator.io.channel_status.`1`[1].occupied, output_unit_1_to_15.io.channel_status[1].occupied connect vc_allocator.io.channel_status.`1`[2].flow.egress_node_id, output_unit_1_to_15.io.channel_status[2].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[2].flow.egress_node, output_unit_1_to_15.io.channel_status[2].flow.egress_node connect vc_allocator.io.channel_status.`1`[2].flow.ingress_node_id, output_unit_1_to_15.io.channel_status[2].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[2].flow.ingress_node, output_unit_1_to_15.io.channel_status[2].flow.ingress_node connect vc_allocator.io.channel_status.`1`[2].flow.vnet_id, output_unit_1_to_15.io.channel_status[2].flow.vnet_id connect vc_allocator.io.channel_status.`1`[2].occupied, output_unit_1_to_15.io.channel_status[2].occupied connect vc_allocator.io.channel_status.`1`[3].flow.egress_node_id, output_unit_1_to_15.io.channel_status[3].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[3].flow.egress_node, output_unit_1_to_15.io.channel_status[3].flow.egress_node connect vc_allocator.io.channel_status.`1`[3].flow.ingress_node_id, output_unit_1_to_15.io.channel_status[3].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[3].flow.ingress_node, output_unit_1_to_15.io.channel_status[3].flow.ingress_node connect vc_allocator.io.channel_status.`1`[3].flow.vnet_id, output_unit_1_to_15.io.channel_status[3].flow.vnet_id connect vc_allocator.io.channel_status.`1`[3].occupied, output_unit_1_to_15.io.channel_status[3].occupied connect vc_allocator.io.channel_status.`1`[4].flow.egress_node_id, output_unit_1_to_15.io.channel_status[4].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[4].flow.egress_node, output_unit_1_to_15.io.channel_status[4].flow.egress_node connect vc_allocator.io.channel_status.`1`[4].flow.ingress_node_id, output_unit_1_to_15.io.channel_status[4].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[4].flow.ingress_node, output_unit_1_to_15.io.channel_status[4].flow.ingress_node connect vc_allocator.io.channel_status.`1`[4].flow.vnet_id, output_unit_1_to_15.io.channel_status[4].flow.vnet_id connect vc_allocator.io.channel_status.`1`[4].occupied, output_unit_1_to_15.io.channel_status[4].occupied connect vc_allocator.io.channel_status.`2`[0].flow.egress_node_id, output_unit_2_to_17.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[0].flow.egress_node, output_unit_2_to_17.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node_id, output_unit_2_to_17.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node, output_unit_2_to_17.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`2`[0].flow.vnet_id, output_unit_2_to_17.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`2`[0].occupied, output_unit_2_to_17.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`2`[1].flow.egress_node_id, output_unit_2_to_17.io.channel_status[1].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[1].flow.egress_node, output_unit_2_to_17.io.channel_status[1].flow.egress_node connect vc_allocator.io.channel_status.`2`[1].flow.ingress_node_id, output_unit_2_to_17.io.channel_status[1].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[1].flow.ingress_node, output_unit_2_to_17.io.channel_status[1].flow.ingress_node connect vc_allocator.io.channel_status.`2`[1].flow.vnet_id, output_unit_2_to_17.io.channel_status[1].flow.vnet_id connect vc_allocator.io.channel_status.`2`[1].occupied, output_unit_2_to_17.io.channel_status[1].occupied connect vc_allocator.io.channel_status.`2`[2].flow.egress_node_id, output_unit_2_to_17.io.channel_status[2].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[2].flow.egress_node, output_unit_2_to_17.io.channel_status[2].flow.egress_node connect vc_allocator.io.channel_status.`2`[2].flow.ingress_node_id, output_unit_2_to_17.io.channel_status[2].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[2].flow.ingress_node, output_unit_2_to_17.io.channel_status[2].flow.ingress_node connect vc_allocator.io.channel_status.`2`[2].flow.vnet_id, output_unit_2_to_17.io.channel_status[2].flow.vnet_id connect vc_allocator.io.channel_status.`2`[2].occupied, output_unit_2_to_17.io.channel_status[2].occupied connect vc_allocator.io.channel_status.`2`[3].flow.egress_node_id, output_unit_2_to_17.io.channel_status[3].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[3].flow.egress_node, output_unit_2_to_17.io.channel_status[3].flow.egress_node connect vc_allocator.io.channel_status.`2`[3].flow.ingress_node_id, output_unit_2_to_17.io.channel_status[3].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[3].flow.ingress_node, output_unit_2_to_17.io.channel_status[3].flow.ingress_node connect vc_allocator.io.channel_status.`2`[3].flow.vnet_id, output_unit_2_to_17.io.channel_status[3].flow.vnet_id connect vc_allocator.io.channel_status.`2`[3].occupied, output_unit_2_to_17.io.channel_status[3].occupied connect vc_allocator.io.channel_status.`2`[4].flow.egress_node_id, output_unit_2_to_17.io.channel_status[4].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[4].flow.egress_node, output_unit_2_to_17.io.channel_status[4].flow.egress_node connect vc_allocator.io.channel_status.`2`[4].flow.ingress_node_id, output_unit_2_to_17.io.channel_status[4].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[4].flow.ingress_node, output_unit_2_to_17.io.channel_status[4].flow.ingress_node connect vc_allocator.io.channel_status.`2`[4].flow.vnet_id, output_unit_2_to_17.io.channel_status[4].flow.vnet_id connect vc_allocator.io.channel_status.`2`[4].occupied, output_unit_2_to_17.io.channel_status[4].occupied connect input_unit_0_from_7.io.out_credit_available.`0`[0], output_unit_0_to_7.io.credit_available[0] connect input_unit_0_from_7.io.out_credit_available.`0`[1], output_unit_0_to_7.io.credit_available[1] connect input_unit_0_from_7.io.out_credit_available.`0`[2], output_unit_0_to_7.io.credit_available[2] connect input_unit_0_from_7.io.out_credit_available.`0`[3], output_unit_0_to_7.io.credit_available[3] connect input_unit_0_from_7.io.out_credit_available.`0`[4], output_unit_0_to_7.io.credit_available[4] connect input_unit_0_from_7.io.out_credit_available.`1`[0], output_unit_1_to_15.io.credit_available[0] connect input_unit_0_from_7.io.out_credit_available.`1`[1], output_unit_1_to_15.io.credit_available[1] connect input_unit_0_from_7.io.out_credit_available.`1`[2], output_unit_1_to_15.io.credit_available[2] connect input_unit_0_from_7.io.out_credit_available.`1`[3], output_unit_1_to_15.io.credit_available[3] connect input_unit_0_from_7.io.out_credit_available.`1`[4], output_unit_1_to_15.io.credit_available[4] connect input_unit_0_from_7.io.out_credit_available.`2`[0], output_unit_2_to_17.io.credit_available[0] connect input_unit_0_from_7.io.out_credit_available.`2`[1], output_unit_2_to_17.io.credit_available[1] connect input_unit_0_from_7.io.out_credit_available.`2`[2], output_unit_2_to_17.io.credit_available[2] connect input_unit_0_from_7.io.out_credit_available.`2`[3], output_unit_2_to_17.io.credit_available[3] connect input_unit_0_from_7.io.out_credit_available.`2`[4], output_unit_2_to_17.io.credit_available[4] connect input_unit_1_from_15.io.out_credit_available.`0`[0], output_unit_0_to_7.io.credit_available[0] connect input_unit_1_from_15.io.out_credit_available.`0`[1], output_unit_0_to_7.io.credit_available[1] connect input_unit_1_from_15.io.out_credit_available.`0`[2], output_unit_0_to_7.io.credit_available[2] connect input_unit_1_from_15.io.out_credit_available.`0`[3], output_unit_0_to_7.io.credit_available[3] connect input_unit_1_from_15.io.out_credit_available.`0`[4], output_unit_0_to_7.io.credit_available[4] connect input_unit_1_from_15.io.out_credit_available.`1`[0], output_unit_1_to_15.io.credit_available[0] connect input_unit_1_from_15.io.out_credit_available.`1`[1], output_unit_1_to_15.io.credit_available[1] connect input_unit_1_from_15.io.out_credit_available.`1`[2], output_unit_1_to_15.io.credit_available[2] connect input_unit_1_from_15.io.out_credit_available.`1`[3], output_unit_1_to_15.io.credit_available[3] connect input_unit_1_from_15.io.out_credit_available.`1`[4], output_unit_1_to_15.io.credit_available[4] connect input_unit_1_from_15.io.out_credit_available.`2`[0], output_unit_2_to_17.io.credit_available[0] connect input_unit_1_from_15.io.out_credit_available.`2`[1], output_unit_2_to_17.io.credit_available[1] connect input_unit_1_from_15.io.out_credit_available.`2`[2], output_unit_2_to_17.io.credit_available[2] connect input_unit_1_from_15.io.out_credit_available.`2`[3], output_unit_2_to_17.io.credit_available[3] connect input_unit_1_from_15.io.out_credit_available.`2`[4], output_unit_2_to_17.io.credit_available[4] connect input_unit_2_from_17.io.out_credit_available.`0`[0], output_unit_0_to_7.io.credit_available[0] connect input_unit_2_from_17.io.out_credit_available.`0`[1], output_unit_0_to_7.io.credit_available[1] connect input_unit_2_from_17.io.out_credit_available.`0`[2], output_unit_0_to_7.io.credit_available[2] connect input_unit_2_from_17.io.out_credit_available.`0`[3], output_unit_0_to_7.io.credit_available[3] connect input_unit_2_from_17.io.out_credit_available.`0`[4], output_unit_0_to_7.io.credit_available[4] connect input_unit_2_from_17.io.out_credit_available.`1`[0], output_unit_1_to_15.io.credit_available[0] connect input_unit_2_from_17.io.out_credit_available.`1`[1], output_unit_1_to_15.io.credit_available[1] connect input_unit_2_from_17.io.out_credit_available.`1`[2], output_unit_1_to_15.io.credit_available[2] connect input_unit_2_from_17.io.out_credit_available.`1`[3], output_unit_1_to_15.io.credit_available[3] connect input_unit_2_from_17.io.out_credit_available.`1`[4], output_unit_1_to_15.io.credit_available[4] connect input_unit_2_from_17.io.out_credit_available.`2`[0], output_unit_2_to_17.io.credit_available[0] connect input_unit_2_from_17.io.out_credit_available.`2`[1], output_unit_2_to_17.io.credit_available[1] connect input_unit_2_from_17.io.out_credit_available.`2`[2], output_unit_2_to_17.io.credit_available[2] connect input_unit_2_from_17.io.out_credit_available.`2`[3], output_unit_2_to_17.io.credit_available[3] connect input_unit_2_from_17.io.out_credit_available.`2`[4], output_unit_2_to_17.io.credit_available[4] connect switch_allocator.io.req.`0`[0], input_unit_0_from_7.io.salloc_req[0] connect switch_allocator.io.req.`1`[0], input_unit_1_from_15.io.salloc_req[0] connect switch_allocator.io.req.`2`[0], input_unit_2_from_17.io.salloc_req[0] connect output_unit_0_to_7.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`0`[0].tail connect output_unit_0_to_7.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`0`[0].alloc connect output_unit_0_to_7.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`0`[1].tail connect output_unit_0_to_7.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`0`[1].alloc connect output_unit_0_to_7.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`0`[2].tail connect output_unit_0_to_7.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`0`[2].alloc connect output_unit_0_to_7.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`0`[3].tail connect output_unit_0_to_7.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`0`[3].alloc connect output_unit_0_to_7.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`0`[4].tail connect output_unit_0_to_7.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`0`[4].alloc connect output_unit_1_to_15.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`1`[0].tail connect output_unit_1_to_15.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`1`[0].alloc connect output_unit_1_to_15.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`1`[1].tail connect output_unit_1_to_15.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`1`[1].alloc connect output_unit_1_to_15.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`1`[2].tail connect output_unit_1_to_15.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`1`[2].alloc connect output_unit_1_to_15.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`1`[3].tail connect output_unit_1_to_15.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`1`[3].alloc connect output_unit_1_to_15.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`1`[4].tail connect output_unit_1_to_15.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`1`[4].alloc connect output_unit_2_to_17.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`2`[0].tail connect output_unit_2_to_17.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`2`[0].alloc connect output_unit_2_to_17.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`2`[1].tail connect output_unit_2_to_17.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`2`[1].alloc connect output_unit_2_to_17.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`2`[2].tail connect output_unit_2_to_17.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`2`[2].alloc connect output_unit_2_to_17.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`2`[3].tail connect output_unit_2_to_17.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`2`[3].alloc connect output_unit_2_to_17.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`2`[4].tail connect output_unit_2_to_17.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`2`[4].alloc connect switch.io.in.`0`[0], input_unit_0_from_7.io.out[0] connect switch.io.in.`1`[0], input_unit_1_from_15.io.out[0] connect switch.io.in.`2`[0], input_unit_2_from_17.io.out[0] connect output_unit_0_to_7.io.in, switch.io.out.`0` connect output_unit_1_to_15.io.in, switch.io.out.`1` connect output_unit_2_to_17.io.in, switch.io.out.`2` reg REG : { `2` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `1` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `0` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1]}, clock connect REG, switch_allocator.io.switch_sel connect switch.io.sel.`0`[0].`0`[0], REG.`0`[0].`0`[0] connect switch.io.sel.`0`[0].`1`[0], REG.`0`[0].`1`[0] connect switch.io.sel.`0`[0].`2`[0], REG.`0`[0].`2`[0] connect switch.io.sel.`1`[0].`0`[0], REG.`1`[0].`0`[0] connect switch.io.sel.`1`[0].`1`[0], REG.`1`[0].`1`[0] connect switch.io.sel.`1`[0].`2`[0], REG.`1`[0].`2`[0] connect switch.io.sel.`2`[0].`0`[0], REG.`2`[0].`0`[0] connect switch.io.sel.`2`[0].`1`[0], REG.`2`[0].`1`[0] connect switch.io.sel.`2`[0].`2`[0], REG.`2`[0].`2`[0] connect input_unit_0_from_7.io.block, UInt<1>(0h0) connect input_unit_1_from_15.io.block, UInt<1>(0h0) connect input_unit_2_from_17.io.block, UInt<1>(0h0) connect debugNodeOut.va_stall[0], input_unit_0_from_7.io.debug.va_stall connect debugNodeOut.va_stall[1], input_unit_1_from_15.io.debug.va_stall connect debugNodeOut.va_stall[2], input_unit_2_from_17.io.debug.va_stall connect debugNodeOut.sa_stall[0], input_unit_0_from_7.io.debug.sa_stall connect debugNodeOut.sa_stall[1], input_unit_1_from_15.io.debug.sa_stall connect debugNodeOut.sa_stall[2], input_unit_2_from_17.io.debug.sa_stall regreset debug_tsc : UInt<64>, clock, reset, UInt<64>(0h0) node _debug_tsc_T = add(debug_tsc, UInt<1>(0h1)) node _debug_tsc_T_1 = tail(_debug_tsc_T, 1) connect debug_tsc, _debug_tsc_T_1 regreset debug_sample : UInt<64>, clock, reset, UInt<64>(0h0) node _debug_sample_T = add(debug_sample, UInt<1>(0h1)) node _debug_sample_T_1 = tail(_debug_sample_T, 1) connect debug_sample, _debug_sample_T_1 inst plusarg_reader of plusarg_reader_93 node _T = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_1 = tail(_T, 1) node _T_2 = eq(debug_sample, _T_1) when _T_2 : connect debug_sample, UInt<1>(0h0) regreset util_ctr : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T = add(util_ctr, destNodesIn.flit[0].valid) node _util_ctr_T_1 = tail(_util_ctr_T, 1) connect util_ctr, _util_ctr_T_1 node _fired_T = or(fired, destNodesIn.flit[0].valid) connect fired, _fired_T node _T_3 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_4 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_5 = tail(_T_4, 1) node _T_6 = eq(debug_sample, _T_5) node _T_7 = and(_T_3, _T_6) node _T_8 = and(_T_7, fired) when _T_8 : node _T_9 = asUInt(reset) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : printf(clock, UInt<1>(0h1), "nocsample %d 7 16 %d\n", debug_tsc, util_ctr) : printf connect fired, destNodesIn.flit[0].valid regreset util_ctr_1 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_2 = add(util_ctr_1, destNodesIn_1.flit[0].valid) node _util_ctr_T_3 = tail(_util_ctr_T_2, 1) connect util_ctr_1, _util_ctr_T_3 node _fired_T_1 = or(fired_1, destNodesIn_1.flit[0].valid) connect fired_1, _fired_T_1 node _T_11 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_12 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_13 = tail(_T_12, 1) node _T_14 = eq(debug_sample, _T_13) node _T_15 = and(_T_11, _T_14) node _T_16 = and(_T_15, fired_1) when _T_16 : node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : printf(clock, UInt<1>(0h1), "nocsample %d 15 16 %d\n", debug_tsc, util_ctr_1) : printf_1 connect fired_1, destNodesIn_1.flit[0].valid regreset util_ctr_2 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_4 = add(util_ctr_2, destNodesIn_2.flit[0].valid) node _util_ctr_T_5 = tail(_util_ctr_T_4, 1) connect util_ctr_2, _util_ctr_T_5 node _fired_T_2 = or(fired_2, destNodesIn_2.flit[0].valid) connect fired_2, _fired_T_2 node _T_19 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_20 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_21 = tail(_T_20, 1) node _T_22 = eq(debug_sample, _T_21) node _T_23 = and(_T_19, _T_22) node _T_24 = and(_T_23, fired_2) when _T_24 : node _T_25 = asUInt(reset) node _T_26 = eq(_T_25, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "nocsample %d 17 16 %d\n", debug_tsc, util_ctr_2) : printf_2 connect fired_2, destNodesIn_2.flit[0].valid
module Router_45( // @[Router.scala:89:25] input clock, // @[Router.scala:89:25] input reset, // @[Router.scala:89:25] output [2:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_source_nodes_out_2_credit_return, // @[LazyModuleImp.scala:107:25] input [4:0] auto_source_nodes_out_2_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25] input [4:0] auto_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25] input [4:0] auto_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_dest_nodes_in_2_credit_return, // @[LazyModuleImp.scala:107:25] output [4:0] auto_dest_nodes_in_2_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25] output [4:0] auto_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25] output [4:0] auto_dest_nodes_in_0_vc_free // @[LazyModuleImp.scala:107:25] ); wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _route_computer_io_resp_2_vc_sel_1_1; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_4; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_4; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_1; // @[Router.scala:136:32] wire _vc_allocator_io_req_2_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_1; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_4_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_1_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_4_alloc; // @[Router.scala:133:30] wire _switch_allocator_io_req_2_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_4_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_4_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34] wire _switch_io_out_2_0_valid; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_2_0_bits_payload; // @[Router.scala:131:24] wire [2:0] _switch_io_out_2_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_2_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_2_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_2_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_2_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [2:0] _switch_io_out_2_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_1_0_valid; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24] wire [2:0] _switch_io_out_1_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_1_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_1_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [2:0] _switch_io_out_1_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_0_0_valid; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _output_unit_2_to_17_io_credit_available_4; // @[Router.scala:122:13] wire _output_unit_2_to_17_io_channel_status_4_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_15_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_1_to_15_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_7_io_credit_available_4; // @[Router.scala:122:13] wire _output_unit_0_to_7_io_channel_status_4_occupied; // @[Router.scala:122:13] wire [2:0] _input_unit_2_from_17_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_17_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_2_from_17_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_17_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_2_from_17_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_17_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_2_from_17_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_2_from_17_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_2_from_17_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_2_from_17_io_salloc_req_0_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_2_from_17_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_2_from_17_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_2_from_17_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_2_from_17_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_2_from_17_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_2_from_17_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_2_from_17_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_17_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_2_from_17_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_17_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_2_from_17_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_17_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_17_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_15_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_15_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_1_from_15_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_15_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_1_from_15_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_15_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_1_from_15_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_1_from_15_io_vcalloc_req_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_1_from_15_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_1_from_15_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_15_io_salloc_req_0_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_1_from_15_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_1_from_15_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_1_from_15_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_1_from_15_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_15_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_1_from_15_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_1_from_15_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_15_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_1_from_15_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_15_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_1_from_15_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_15_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_15_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_7_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_7_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_7_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_7_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_7_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_7_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_0_from_7_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_0_from_7_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_0_from_7_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_7_io_salloc_req_0_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_0_from_7_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_0_from_7_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_0_from_7_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_0_from_7_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_7_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_0_from_7_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_0_from_7_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_7_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_7_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_7_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_7_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_7_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_7_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [1:0] fires_count = {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_7_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _input_unit_1_from_15_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_2_ready & _input_unit_2_from_17_io_vcalloc_req_valid}; // @[Decoupled.scala:51:35] reg REG_2_0_2_0; // @[Router.scala:178:14] reg REG_2_0_1_0; // @[Router.scala:178:14] reg REG_2_0_0_0; // @[Router.scala:178:14] reg REG_1_0_2_0; // @[Router.scala:178:14] reg REG_1_0_1_0; // @[Router.scala:178:14] reg REG_1_0_0_0; // @[Router.scala:178:14] reg REG_0_0_2_0; // @[Router.scala:178:14] reg REG_0_0_1_0; // @[Router.scala:178:14] reg REG_0_0_0_0; // @[Router.scala:178:14] reg [63:0] debug_tsc; // @[Router.scala:195:28] reg [63:0] debug_sample; // @[Router.scala:197:31] wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11] reg [63:0] util_ctr; // @[Router.scala:203:29] reg fired; // @[Router.scala:204:26] wire _GEN_0 = (|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11] wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_1; // @[Router.scala:203:29] reg fired_1; // @[Router.scala:204:26] wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_2; // @[Router.scala:203:29] reg fired_2; // @[Router.scala:204:26] wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}]
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_33 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<8>, mispredict_mask : UInt<8>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<6>, poisoned : UInt<1>}}[3], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<4>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<6>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}} wire next_state : UInt wire next_uopc : UInt wire next_lrs1_rtype : UInt wire next_lrs2_rtype : UInt regreset state : UInt<2>, clock, reset, UInt<2>(0h0) regreset p1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p3 : UInt<1>, clock, reset, UInt<1>(0h0) regreset ppred : UInt<1>, clock, reset, UInt<1>(0h0) regreset p1_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) connect p1_poisoned, UInt<1>(0h0) connect p2_poisoned, UInt<1>(0h0) node next_p1_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) node next_p2_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) wire slot_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} invalidate slot_uop_uop.debug_tsrc invalidate slot_uop_uop.debug_fsrc invalidate slot_uop_uop.bp_xcpt_if invalidate slot_uop_uop.bp_debug_if invalidate slot_uop_uop.xcpt_ma_if invalidate slot_uop_uop.xcpt_ae_if invalidate slot_uop_uop.xcpt_pf_if invalidate slot_uop_uop.fp_single invalidate slot_uop_uop.fp_val invalidate slot_uop_uop.frs3_en invalidate slot_uop_uop.lrs2_rtype invalidate slot_uop_uop.lrs1_rtype invalidate slot_uop_uop.dst_rtype invalidate slot_uop_uop.ldst_val invalidate slot_uop_uop.lrs3 invalidate slot_uop_uop.lrs2 invalidate slot_uop_uop.lrs1 invalidate slot_uop_uop.ldst invalidate slot_uop_uop.ldst_is_rs1 invalidate slot_uop_uop.flush_on_commit invalidate slot_uop_uop.is_unique invalidate slot_uop_uop.is_sys_pc2epc invalidate slot_uop_uop.uses_stq invalidate slot_uop_uop.uses_ldq invalidate slot_uop_uop.is_amo invalidate slot_uop_uop.is_fencei invalidate slot_uop_uop.is_fence invalidate slot_uop_uop.mem_signed invalidate slot_uop_uop.mem_size invalidate slot_uop_uop.mem_cmd invalidate slot_uop_uop.bypassable invalidate slot_uop_uop.exc_cause invalidate slot_uop_uop.exception invalidate slot_uop_uop.stale_pdst invalidate slot_uop_uop.ppred_busy invalidate slot_uop_uop.prs3_busy invalidate slot_uop_uop.prs2_busy invalidate slot_uop_uop.prs1_busy invalidate slot_uop_uop.ppred invalidate slot_uop_uop.prs3 invalidate slot_uop_uop.prs2 invalidate slot_uop_uop.prs1 invalidate slot_uop_uop.pdst invalidate slot_uop_uop.rxq_idx invalidate slot_uop_uop.stq_idx invalidate slot_uop_uop.ldq_idx invalidate slot_uop_uop.rob_idx invalidate slot_uop_uop.csr_addr invalidate slot_uop_uop.imm_packed invalidate slot_uop_uop.taken invalidate slot_uop_uop.pc_lob invalidate slot_uop_uop.edge_inst invalidate slot_uop_uop.ftq_idx invalidate slot_uop_uop.br_tag invalidate slot_uop_uop.br_mask invalidate slot_uop_uop.is_sfb invalidate slot_uop_uop.is_jal invalidate slot_uop_uop.is_jalr invalidate slot_uop_uop.is_br invalidate slot_uop_uop.iw_p2_poisoned invalidate slot_uop_uop.iw_p1_poisoned invalidate slot_uop_uop.iw_state invalidate slot_uop_uop.ctrl.is_std invalidate slot_uop_uop.ctrl.is_sta invalidate slot_uop_uop.ctrl.is_load invalidate slot_uop_uop.ctrl.csr_cmd invalidate slot_uop_uop.ctrl.fcn_dw invalidate slot_uop_uop.ctrl.op_fcn invalidate slot_uop_uop.ctrl.imm_sel invalidate slot_uop_uop.ctrl.op2_sel invalidate slot_uop_uop.ctrl.op1_sel invalidate slot_uop_uop.ctrl.br_type invalidate slot_uop_uop.fu_code invalidate slot_uop_uop.iq_type invalidate slot_uop_uop.debug_pc invalidate slot_uop_uop.is_rvc invalidate slot_uop_uop.debug_inst invalidate slot_uop_uop.inst invalidate slot_uop_uop.uopc connect slot_uop_uop.uopc, UInt<7>(0h0) connect slot_uop_uop.bypassable, UInt<1>(0h0) connect slot_uop_uop.fp_val, UInt<1>(0h0) connect slot_uop_uop.uses_stq, UInt<1>(0h0) connect slot_uop_uop.uses_ldq, UInt<1>(0h0) connect slot_uop_uop.pdst, UInt<1>(0h0) connect slot_uop_uop.dst_rtype, UInt<2>(0h2) wire slot_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>} invalidate slot_uop_cs.is_std invalidate slot_uop_cs.is_sta invalidate slot_uop_cs.is_load invalidate slot_uop_cs.csr_cmd invalidate slot_uop_cs.fcn_dw invalidate slot_uop_cs.op_fcn invalidate slot_uop_cs.imm_sel invalidate slot_uop_cs.op2_sel invalidate slot_uop_cs.op1_sel invalidate slot_uop_cs.br_type connect slot_uop_cs.br_type, UInt<4>(0h0) connect slot_uop_cs.csr_cmd, UInt<3>(0h0) connect slot_uop_cs.is_load, UInt<1>(0h0) connect slot_uop_cs.is_sta, UInt<1>(0h0) connect slot_uop_cs.is_std, UInt<1>(0h0) connect slot_uop_uop.ctrl, slot_uop_cs regreset slot_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock, reset, slot_uop_uop node next_uop = mux(io.in_uop.valid, io.in_uop.bits, slot_uop) when io.kill : connect state, UInt<2>(0h0) else : when io.in_uop.valid : connect state, io.in_uop.bits.iw_state else : when io.clear : connect state, UInt<2>(0h0) else : connect state, next_state connect next_state, state connect next_uopc, slot_uop.uopc connect next_lrs1_rtype, slot_uop.lrs1_rtype connect next_lrs2_rtype, slot_uop.lrs2_rtype when io.kill : connect next_state, UInt<2>(0h0) else : node _T = eq(state, UInt<2>(0h1)) node _T_1 = and(io.grant, _T) node _T_2 = eq(state, UInt<2>(0h2)) node _T_3 = and(io.grant, _T_2) node _T_4 = and(_T_3, p1) node _T_5 = and(_T_4, p2) node _T_6 = and(_T_5, ppred) node _T_7 = or(_T_1, _T_6) when _T_7 : node _T_8 = or(p1_poisoned, p2_poisoned) node _T_9 = and(io.ldspec_miss, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : connect next_state, UInt<2>(0h0) else : node _T_11 = eq(state, UInt<2>(0h2)) node _T_12 = and(io.grant, _T_11) when _T_12 : node _T_13 = or(p1_poisoned, p2_poisoned) node _T_14 = and(io.ldspec_miss, _T_13) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : connect next_state, UInt<2>(0h1) when p1 : connect slot_uop.uopc, UInt<7>(0h3) connect next_uopc, UInt<7>(0h3) connect slot_uop.lrs1_rtype, UInt<2>(0h2) connect next_lrs1_rtype, UInt<2>(0h2) else : connect slot_uop.lrs2_rtype, UInt<2>(0h2) connect next_lrs2_rtype, UInt<2>(0h2) when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T_16 = eq(state, UInt<2>(0h0)) node _T_17 = or(_T_16, io.clear) node _T_18 = or(_T_17, io.kill) node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : node _T_21 = eq(_T_18, UInt<1>(0h0)) when _T_21 : printf(clock, UInt<1>(0h1), "Assertion failed: trying to overwrite a valid issue slot.\n at issue-slot.scala:156 assert (is_invalid || io.clear || io.kill, \"trying to overwrite a valid issue slot.\")\n") : printf assert(clock, _T_18, UInt<1>(0h1), "") : assert wire next_p1 : UInt<1> connect next_p1, p1 wire next_p2 : UInt<1> connect next_p2, p2 wire next_p3 : UInt<1> connect next_p3, p3 wire next_ppred : UInt<1> connect next_ppred, ppred when io.in_uop.valid : node _p1_T = eq(io.in_uop.bits.prs1_busy, UInt<1>(0h0)) connect p1, _p1_T node _p2_T = eq(io.in_uop.bits.prs2_busy, UInt<1>(0h0)) connect p2, _p2_T node _p3_T = eq(io.in_uop.bits.prs3_busy, UInt<1>(0h0)) connect p3, _p3_T node _ppred_T = eq(io.in_uop.bits.ppred_busy, UInt<1>(0h0)) connect ppred, _ppred_T node _T_22 = and(io.ldspec_miss, next_p1_poisoned) when _T_22 : node _T_23 = neq(next_uop.prs1, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs1=x0!\n at issue-slot.scala:176 assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n") : printf_1 assert(clock, _T_23, UInt<1>(0h1), "") : assert_1 connect p1, UInt<1>(0h0) node _T_27 = and(io.ldspec_miss, next_p2_poisoned) when _T_27 : node _T_28 = neq(next_uop.prs2, UInt<1>(0h0)) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs2=x0!\n at issue-slot.scala:180 assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n") : printf_2 assert(clock, _T_28, UInt<1>(0h1), "") : assert_2 connect p2, UInt<1>(0h0) node _T_32 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs1) node _T_33 = and(io.wakeup_ports[0].valid, _T_32) when _T_33 : connect p1, UInt<1>(0h1) node _T_34 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs2) node _T_35 = and(io.wakeup_ports[0].valid, _T_34) when _T_35 : connect p2, UInt<1>(0h1) node _T_36 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs3) node _T_37 = and(io.wakeup_ports[0].valid, _T_36) when _T_37 : connect p3, UInt<1>(0h1) node _T_38 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs1) node _T_39 = and(io.wakeup_ports[1].valid, _T_38) when _T_39 : connect p1, UInt<1>(0h1) node _T_40 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs2) node _T_41 = and(io.wakeup_ports[1].valid, _T_40) when _T_41 : connect p2, UInt<1>(0h1) node _T_42 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs3) node _T_43 = and(io.wakeup_ports[1].valid, _T_42) when _T_43 : connect p3, UInt<1>(0h1) node _T_44 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs1) node _T_45 = and(io.wakeup_ports[2].valid, _T_44) when _T_45 : connect p1, UInt<1>(0h1) node _T_46 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs2) node _T_47 = and(io.wakeup_ports[2].valid, _T_46) when _T_47 : connect p2, UInt<1>(0h1) node _T_48 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs3) node _T_49 = and(io.wakeup_ports[2].valid, _T_48) when _T_49 : connect p3, UInt<1>(0h1) node _T_50 = eq(io.pred_wakeup_port.bits, next_uop.ppred) node _T_51 = and(io.pred_wakeup_port.valid, _T_50) when _T_51 : connect ppred, UInt<1>(0h1) node _T_52 = eq(io.spec_ld_wakeup[0].bits, UInt<1>(0h0)) node _T_53 = and(io.spec_ld_wakeup[0].valid, _T_52) node _T_54 = eq(_T_53, UInt<1>(0h0)) node _T_55 = asUInt(reset) node _T_56 = eq(_T_55, UInt<1>(0h0)) when _T_56 : node _T_57 = eq(_T_54, UInt<1>(0h0)) when _T_57 : printf(clock, UInt<1>(0h1), "Assertion failed: Loads to x0 should never speculatively wakeup other instructions\n at issue-slot.scala:203 assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n") : printf_3 assert(clock, _T_54, UInt<1>(0h1), "") : assert_3 node _T_58 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs1) node _T_59 = and(io.spec_ld_wakeup[0].valid, _T_58) node _T_60 = eq(next_uop.lrs1_rtype, UInt<2>(0h0)) node _T_61 = and(_T_59, _T_60) when _T_61 : connect p1, UInt<1>(0h1) connect p1_poisoned, UInt<1>(0h1) node _T_62 = eq(next_p1_poisoned, UInt<1>(0h0)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:214 assert (!next_p1_poisoned)\n") : printf_4 assert(clock, _T_62, UInt<1>(0h1), "") : assert_4 node _T_66 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs2) node _T_67 = and(io.spec_ld_wakeup[0].valid, _T_66) node _T_68 = eq(next_uop.lrs2_rtype, UInt<2>(0h0)) node _T_69 = and(_T_67, _T_68) when _T_69 : connect p2, UInt<1>(0h1) connect p2_poisoned, UInt<1>(0h1) node _T_70 = eq(next_p2_poisoned, UInt<1>(0h0)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:221 assert (!next_p2_poisoned)\n") : printf_5 assert(clock, _T_70, UInt<1>(0h1), "") : assert_5 node _next_br_mask_T = not(io.brupdate.b1.resolve_mask) node next_br_mask = and(slot_uop.br_mask, _next_br_mask_T) node _T_74 = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _T_75 = neq(_T_74, UInt<1>(0h0)) when _T_75 : connect next_state, UInt<2>(0h0) node _T_76 = eq(io.in_uop.valid, UInt<1>(0h0)) when _T_76 : connect slot_uop.br_mask, next_br_mask node _io_request_T = neq(state, UInt<2>(0h0)) node _io_request_T_1 = and(_io_request_T, p1) node _io_request_T_2 = and(_io_request_T_1, p2) node _io_request_T_3 = and(_io_request_T_2, p3) node _io_request_T_4 = and(_io_request_T_3, ppred) node _io_request_T_5 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_6 = and(_io_request_T_4, _io_request_T_5) connect io.request, _io_request_T_6 node _high_priority_T = or(slot_uop.is_br, slot_uop.is_jal) node high_priority = or(_high_priority_T, slot_uop.is_jalr) node _io_request_hp_T = and(io.request, high_priority) connect io.request_hp, _io_request_hp_T node _T_77 = eq(state, UInt<2>(0h1)) when _T_77 : node _io_request_T_7 = and(p1, p2) node _io_request_T_8 = and(_io_request_T_7, p3) node _io_request_T_9 = and(_io_request_T_8, ppred) node _io_request_T_10 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_11 = and(_io_request_T_9, _io_request_T_10) connect io.request, _io_request_T_11 else : node _T_78 = eq(state, UInt<2>(0h2)) when _T_78 : node _io_request_T_12 = or(p1, p2) node _io_request_T_13 = and(_io_request_T_12, ppred) node _io_request_T_14 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_15 = and(_io_request_T_13, _io_request_T_14) connect io.request, _io_request_T_15 else : connect io.request, UInt<1>(0h0) node _io_valid_T = neq(state, UInt<2>(0h0)) connect io.valid, _io_valid_T connect io.uop, slot_uop connect io.uop.iw_p1_poisoned, p1_poisoned connect io.uop.iw_p2_poisoned, p2_poisoned node _may_vacate_T = eq(state, UInt<2>(0h1)) node _may_vacate_T_1 = eq(state, UInt<2>(0h2)) node _may_vacate_T_2 = and(_may_vacate_T_1, p1) node _may_vacate_T_3 = and(_may_vacate_T_2, p2) node _may_vacate_T_4 = and(_may_vacate_T_3, ppred) node _may_vacate_T_5 = or(_may_vacate_T, _may_vacate_T_4) node may_vacate = and(io.grant, _may_vacate_T_5) node _squash_grant_T = or(p1_poisoned, p2_poisoned) node squash_grant = and(io.ldspec_miss, _squash_grant_T) node _io_will_be_valid_T = neq(state, UInt<2>(0h0)) node _io_will_be_valid_T_1 = eq(squash_grant, UInt<1>(0h0)) node _io_will_be_valid_T_2 = and(may_vacate, _io_will_be_valid_T_1) node _io_will_be_valid_T_3 = eq(_io_will_be_valid_T_2, UInt<1>(0h0)) node _io_will_be_valid_T_4 = and(_io_will_be_valid_T, _io_will_be_valid_T_3) connect io.will_be_valid, _io_will_be_valid_T_4 connect io.out_uop, slot_uop connect io.out_uop.iw_state, next_state connect io.out_uop.uopc, next_uopc connect io.out_uop.lrs1_rtype, next_lrs1_rtype connect io.out_uop.lrs2_rtype, next_lrs2_rtype connect io.out_uop.br_mask, next_br_mask node _io_out_uop_prs1_busy_T = eq(p1, UInt<1>(0h0)) connect io.out_uop.prs1_busy, _io_out_uop_prs1_busy_T node _io_out_uop_prs2_busy_T = eq(p2, UInt<1>(0h0)) connect io.out_uop.prs2_busy, _io_out_uop_prs2_busy_T node _io_out_uop_prs3_busy_T = eq(p3, UInt<1>(0h0)) connect io.out_uop.prs3_busy, _io_out_uop_prs3_busy_T node _io_out_uop_ppred_busy_T = eq(ppred, UInt<1>(0h0)) connect io.out_uop.ppred_busy, _io_out_uop_ppred_busy_T connect io.out_uop.iw_p1_poisoned, p1_poisoned connect io.out_uop.iw_p2_poisoned, p2_poisoned node _T_79 = eq(state, UInt<2>(0h2)) when _T_79 : node _T_80 = and(p1, p2) node _T_81 = and(_T_80, ppred) when _T_81 : skip else : node _T_82 = and(p1, ppred) when _T_82 : connect io.uop.uopc, slot_uop.uopc connect io.uop.lrs2_rtype, UInt<2>(0h2) else : node _T_83 = and(p2, ppred) when _T_83 : connect io.uop.uopc, UInt<7>(0h3) connect io.uop.lrs1_rtype, UInt<2>(0h2) connect io.debug.p1, p1 connect io.debug.p2, p2 connect io.debug.p3, p3 connect io.debug.ppred, ppred connect io.debug.state, state
module IssueSlot_33( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [7:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [7:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [7:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_ldspec_miss, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [5:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [5:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14] input [5:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14] input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14] input [5:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [7:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [7:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [7:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [2:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [3:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [4:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [2:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [2:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [5:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [5:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [3:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [5:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [7:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [7:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [7:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [5:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [5:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7] wire [5:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7] wire [5:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned_0 = io_in_uop_bits_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned_0 = io_in_uop_bits_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [7:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire [3:0] io_pred_wakeup_port_bits = 4'h0; // @[issue-slot.scala:69:7] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_ftq_idx = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_ppred = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_br_tag = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ldq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_stq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_rob_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_prs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_prs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_prs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_stale_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [7:0] slot_uop_uop_br_mask = 8'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [7:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [7:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [7:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg p1_poisoned; // @[issue-slot.scala:95:28] assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] reg p2_poisoned; // @[issue-slot.scala:96:28] assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] wire next_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29] wire next_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :100:29] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [7:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [7:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _T_14 = io_ldspec_miss_0 & (p1_poisoned | p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}] wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18] wire _GEN_0 = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_1 = _GEN_0 | ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23] assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_2 = _GEN_0 | ~_GEN | p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17] assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17] wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11] wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11] wire _p3_T = ~io_in_uop_bits_prs3_busy_0; // @[issue-slot.scala:69:7, :171:11] wire _ppred_T = ~io_in_uop_bits_ppred_busy_0; // @[issue-slot.scala:69:7, :172:14] wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24] wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24] wire _T_61 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27] wire _T_69 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_169 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_301 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0
module AsyncResetSynchronizerShiftReg_w1_d3_i0_169( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_301 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_115 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_125 connect io_out_sink_valid.clock, clock connect io_out_sink_valid.reset, reset connect io_out_sink_valid.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid.io.q connect io.out, _io_out_WIRE
module AsyncValidSync_115( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_125 io_out_sink_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_16 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x
module OptimizationBarrier_TLBEntryData_16( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLSplitACDxBENoC_be_router_8ClockSinkDomain : output auto : { egress_width_widget_out : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<148>, ingress_id : UInt}}}, flip ingress_width_widget_in : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<148>, egress_id : UInt}}}, routers_debug_out : { va_stall : UInt[3], sa_stall : UInt[3]}, routers_source_nodes_out_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>}, routers_source_nodes_out_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>}, routers_source_nodes_out_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>}, flip routers_dest_nodes_in_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>}, flip routers_dest_nodes_in_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>}, flip clock_in : { clock : Clock, reset : Reset}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst routers of Router_24 connect routers.clock, childClock connect routers.reset, childReset inst ingress_width_widget of IngressWidthWidget_10 connect ingress_width_widget.clock, childClock connect ingress_width_widget.reset, childReset inst egress_width_widget of EgressWidthWidget_10 connect egress_width_widget.clock, childClock connect egress_width_widget.reset, childReset wire clockNodeIn : { clock : Clock, reset : Reset} invalidate clockNodeIn.reset invalidate clockNodeIn.clock connect egress_width_widget.auto.in, routers.auto.egress_nodes_out connect routers.auto.ingress_nodes_in, ingress_width_widget.auto.out connect clockNodeIn, auto.clock_in connect routers.auto.dest_nodes_in_0, auto.routers_dest_nodes_in_0 connect routers.auto.dest_nodes_in_1, auto.routers_dest_nodes_in_1 connect routers.auto.source_nodes_out_0.vc_free, auto.routers_source_nodes_out_0.vc_free connect routers.auto.source_nodes_out_0.credit_return, auto.routers_source_nodes_out_0.credit_return connect auto.routers_source_nodes_out_0.flit, routers.auto.source_nodes_out_0.flit connect routers.auto.source_nodes_out_1.vc_free, auto.routers_source_nodes_out_1.vc_free connect routers.auto.source_nodes_out_1.credit_return, auto.routers_source_nodes_out_1.credit_return connect auto.routers_source_nodes_out_1.flit, routers.auto.source_nodes_out_1.flit connect routers.auto.source_nodes_out_2.vc_free, auto.routers_source_nodes_out_2.vc_free connect routers.auto.source_nodes_out_2.credit_return, auto.routers_source_nodes_out_2.credit_return connect auto.routers_source_nodes_out_2.flit, routers.auto.source_nodes_out_2.flit connect auto.routers_debug_out, routers.auto.debug_out connect ingress_width_widget.auto.in, auto.ingress_width_widget_in connect auto.egress_width_widget_out.flit.bits, egress_width_widget.auto.out.flit.bits connect auto.egress_width_widget_out.flit.valid, egress_width_widget.auto.out.flit.valid connect egress_width_widget.auto.out.flit.ready, auto.egress_width_widget_out.flit.ready connect childClock, clockNodeIn.clock connect childReset, clockNodeIn.reset connect clock, clockNodeIn.clock connect reset, clockNodeIn.reset
module TLSplitACDxBENoC_be_router_8ClockSinkDomain( // @[ClockDomain.scala:14:9] input auto_egress_width_widget_out_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_egress_width_widget_out_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_egress_width_widget_out_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_egress_width_widget_out_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [147:0] auto_egress_width_widget_out_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_ingress_width_widget_in_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_width_widget_in_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_width_widget_in_flit_bits_head, // @[LazyModuleImp.scala:107:25] input [147:0] auto_ingress_width_widget_in_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_ingress_width_widget_in_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_routers_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output auto_routers_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output auto_routers_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output auto_routers_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output auto_routers_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output auto_routers_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [36:0] auto_routers_source_nodes_out_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_source_nodes_out_2_credit_return, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_source_nodes_out_2_vc_free, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [36:0] auto_routers_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [36:0] auto_routers_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [36:0] auto_routers_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [36:0] auto_routers_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_dest_nodes_in_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); wire _egress_width_widget_auto_in_flit_ready; // @[WidthWidget.scala:111:43] wire _ingress_width_widget_auto_out_flit_valid; // @[WidthWidget.scala:88:44] wire _ingress_width_widget_auto_out_flit_bits_head; // @[WidthWidget.scala:88:44] wire _ingress_width_widget_auto_out_flit_bits_tail; // @[WidthWidget.scala:88:44] wire [36:0] _ingress_width_widget_auto_out_flit_bits_payload; // @[WidthWidget.scala:88:44] wire [4:0] _ingress_width_widget_auto_out_flit_bits_egress_id; // @[WidthWidget.scala:88:44] wire _routers_auto_egress_nodes_out_flit_valid; // @[NoC.scala:67:22] wire _routers_auto_egress_nodes_out_flit_bits_head; // @[NoC.scala:67:22] wire _routers_auto_egress_nodes_out_flit_bits_tail; // @[NoC.scala:67:22] wire [36:0] _routers_auto_egress_nodes_out_flit_bits_payload; // @[NoC.scala:67:22] wire _routers_auto_ingress_nodes_in_flit_ready; // @[NoC.scala:67:22] Router_24 routers ( // @[NoC.scala:67:22] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_debug_out_va_stall_0 (auto_routers_debug_out_va_stall_0), .auto_debug_out_va_stall_1 (auto_routers_debug_out_va_stall_1), .auto_debug_out_va_stall_2 (auto_routers_debug_out_va_stall_2), .auto_debug_out_sa_stall_0 (auto_routers_debug_out_sa_stall_0), .auto_debug_out_sa_stall_1 (auto_routers_debug_out_sa_stall_1), .auto_debug_out_sa_stall_2 (auto_routers_debug_out_sa_stall_2), .auto_egress_nodes_out_flit_ready (_egress_width_widget_auto_in_flit_ready), // @[WidthWidget.scala:111:43] .auto_egress_nodes_out_flit_valid (_routers_auto_egress_nodes_out_flit_valid), .auto_egress_nodes_out_flit_bits_head (_routers_auto_egress_nodes_out_flit_bits_head), .auto_egress_nodes_out_flit_bits_tail (_routers_auto_egress_nodes_out_flit_bits_tail), .auto_egress_nodes_out_flit_bits_payload (_routers_auto_egress_nodes_out_flit_bits_payload), .auto_ingress_nodes_in_flit_ready (_routers_auto_ingress_nodes_in_flit_ready), .auto_ingress_nodes_in_flit_valid (_ingress_width_widget_auto_out_flit_valid), // @[WidthWidget.scala:88:44] .auto_ingress_nodes_in_flit_bits_head (_ingress_width_widget_auto_out_flit_bits_head), // @[WidthWidget.scala:88:44] .auto_ingress_nodes_in_flit_bits_tail (_ingress_width_widget_auto_out_flit_bits_tail), // @[WidthWidget.scala:88:44] .auto_ingress_nodes_in_flit_bits_payload (_ingress_width_widget_auto_out_flit_bits_payload), // @[WidthWidget.scala:88:44] .auto_ingress_nodes_in_flit_bits_egress_id (_ingress_width_widget_auto_out_flit_bits_egress_id), // @[WidthWidget.scala:88:44] .auto_source_nodes_out_2_flit_0_valid (auto_routers_source_nodes_out_2_flit_0_valid), .auto_source_nodes_out_2_flit_0_bits_head (auto_routers_source_nodes_out_2_flit_0_bits_head), .auto_source_nodes_out_2_flit_0_bits_tail (auto_routers_source_nodes_out_2_flit_0_bits_tail), .auto_source_nodes_out_2_flit_0_bits_payload (auto_routers_source_nodes_out_2_flit_0_bits_payload), .auto_source_nodes_out_2_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_2_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_2_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_2_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node), .auto_source_nodes_out_2_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_2_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id), .auto_source_nodes_out_2_credit_return (auto_routers_source_nodes_out_2_credit_return), .auto_source_nodes_out_2_vc_free (auto_routers_source_nodes_out_2_vc_free), .auto_source_nodes_out_1_flit_0_valid (auto_routers_source_nodes_out_1_flit_0_valid), .auto_source_nodes_out_1_flit_0_bits_head (auto_routers_source_nodes_out_1_flit_0_bits_head), .auto_source_nodes_out_1_flit_0_bits_tail (auto_routers_source_nodes_out_1_flit_0_bits_tail), .auto_source_nodes_out_1_flit_0_bits_payload (auto_routers_source_nodes_out_1_flit_0_bits_payload), .auto_source_nodes_out_1_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_1_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_1_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node), .auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_1_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id), .auto_source_nodes_out_1_credit_return (auto_routers_source_nodes_out_1_credit_return), .auto_source_nodes_out_1_vc_free (auto_routers_source_nodes_out_1_vc_free), .auto_source_nodes_out_0_flit_0_valid (auto_routers_source_nodes_out_0_flit_0_valid), .auto_source_nodes_out_0_flit_0_bits_head (auto_routers_source_nodes_out_0_flit_0_bits_head), .auto_source_nodes_out_0_flit_0_bits_tail (auto_routers_source_nodes_out_0_flit_0_bits_tail), .auto_source_nodes_out_0_flit_0_bits_payload (auto_routers_source_nodes_out_0_flit_0_bits_payload), .auto_source_nodes_out_0_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_0_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_0_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node), .auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_0_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id), .auto_source_nodes_out_0_credit_return (auto_routers_source_nodes_out_0_credit_return), .auto_source_nodes_out_0_vc_free (auto_routers_source_nodes_out_0_vc_free), .auto_dest_nodes_in_1_flit_0_valid (auto_routers_dest_nodes_in_1_flit_0_valid), .auto_dest_nodes_in_1_flit_0_bits_head (auto_routers_dest_nodes_in_1_flit_0_bits_head), .auto_dest_nodes_in_1_flit_0_bits_tail (auto_routers_dest_nodes_in_1_flit_0_bits_tail), .auto_dest_nodes_in_1_flit_0_bits_payload (auto_routers_dest_nodes_in_1_flit_0_bits_payload), .auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_1_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_1_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_1_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_1_credit_return (auto_routers_dest_nodes_in_1_credit_return), .auto_dest_nodes_in_1_vc_free (auto_routers_dest_nodes_in_1_vc_free), .auto_dest_nodes_in_0_flit_0_valid (auto_routers_dest_nodes_in_0_flit_0_valid), .auto_dest_nodes_in_0_flit_0_bits_head (auto_routers_dest_nodes_in_0_flit_0_bits_head), .auto_dest_nodes_in_0_flit_0_bits_tail (auto_routers_dest_nodes_in_0_flit_0_bits_tail), .auto_dest_nodes_in_0_flit_0_bits_payload (auto_routers_dest_nodes_in_0_flit_0_bits_payload), .auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_0_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_0_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_0_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_0_credit_return (auto_routers_dest_nodes_in_0_credit_return), .auto_dest_nodes_in_0_vc_free (auto_routers_dest_nodes_in_0_vc_free) ); // @[NoC.scala:67:22] IngressWidthWidget ingress_width_widget ( // @[WidthWidget.scala:88:44] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_in_flit_ready (auto_ingress_width_widget_in_flit_ready), .auto_in_flit_valid (auto_ingress_width_widget_in_flit_valid), .auto_in_flit_bits_head (auto_ingress_width_widget_in_flit_bits_head), .auto_in_flit_bits_payload (auto_ingress_width_widget_in_flit_bits_payload), .auto_in_flit_bits_egress_id (auto_ingress_width_widget_in_flit_bits_egress_id), .auto_out_flit_ready (_routers_auto_ingress_nodes_in_flit_ready), // @[NoC.scala:67:22] .auto_out_flit_valid (_ingress_width_widget_auto_out_flit_valid), .auto_out_flit_bits_head (_ingress_width_widget_auto_out_flit_bits_head), .auto_out_flit_bits_tail (_ingress_width_widget_auto_out_flit_bits_tail), .auto_out_flit_bits_payload (_ingress_width_widget_auto_out_flit_bits_payload), .auto_out_flit_bits_egress_id (_ingress_width_widget_auto_out_flit_bits_egress_id) ); // @[WidthWidget.scala:88:44] EgressWidthWidget_1 egress_width_widget ( // @[WidthWidget.scala:111:43] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_in_flit_ready (_egress_width_widget_auto_in_flit_ready), .auto_in_flit_valid (_routers_auto_egress_nodes_out_flit_valid), // @[NoC.scala:67:22] .auto_in_flit_bits_head (_routers_auto_egress_nodes_out_flit_bits_head), // @[NoC.scala:67:22] .auto_in_flit_bits_tail (_routers_auto_egress_nodes_out_flit_bits_tail), // @[NoC.scala:67:22] .auto_in_flit_bits_payload (_routers_auto_egress_nodes_out_flit_bits_payload), // @[NoC.scala:67:22] .auto_out_flit_ready (auto_egress_width_widget_out_flit_ready), .auto_out_flit_valid (auto_egress_width_widget_out_flit_valid), .auto_out_flit_bits_head (auto_egress_width_widget_out_flit_bits_head), .auto_out_flit_bits_tail (auto_egress_width_widget_out_flit_bits_tail), .auto_out_flit_bits_payload (auto_egress_width_widget_out_flit_bits_payload) ); // @[WidthWidget.scala:111:43] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Tile_224 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_480 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a
module Tile_224( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_480 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_395 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_139 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c
module PE_395( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_139 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module SwitchArbiter_132 : input clock : Clock input reset : Reset output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[2]}, tail : UInt<1>}}[2], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[2]}, tail : UInt<1>}}[1], chosen_oh : UInt<2>[1]} regreset lock_0 : UInt<2>, clock, reset, UInt<2>(0h0) node _unassigned_T = cat(io.in[1].valid, io.in[0].valid) node _unassigned_T_1 = not(lock_0) node unassigned = and(_unassigned_T, _unassigned_T_1) regreset mask : UInt<2>, clock, reset, UInt<2>(0h0) wire choices : UInt<2>[1] node _sel_T = not(mask) node _sel_T_1 = and(unassigned, _sel_T) node _sel_T_2 = cat(unassigned, _sel_T_1) node _sel_T_3 = bits(_sel_T_2, 0, 0) node _sel_T_4 = bits(_sel_T_2, 1, 1) node _sel_T_5 = bits(_sel_T_2, 2, 2) node _sel_T_6 = bits(_sel_T_2, 3, 3) node _sel_T_7 = mux(_sel_T_6, UInt<4>(0h8), UInt<4>(0h0)) node _sel_T_8 = mux(_sel_T_5, UInt<4>(0h4), _sel_T_7) node _sel_T_9 = mux(_sel_T_4, UInt<4>(0h2), _sel_T_8) node sel = mux(_sel_T_3, UInt<4>(0h1), _sel_T_9) node _choices_0_T = shr(sel, 2) node _choices_0_T_1 = or(sel, _choices_0_T) connect choices[0], _choices_0_T_1 node _T = not(choices[0]) node _T_1 = and(unassigned, _T) node _T_2 = bits(_T_1, 0, 0) node _T_3 = bits(_T_1, 1, 1) node _T_4 = mux(_T_3, UInt<2>(0h2), UInt<2>(0h0)) node _T_5 = mux(_T_2, UInt<2>(0h1), _T_4) connect io.in[0].ready, UInt<1>(0h0) connect io.in[1].ready, UInt<1>(0h0) node in_tails = cat(io.in[1].bits.tail, io.in[0].bits.tail) node _in_valids_T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _in_valids_T_1 = and(io.in[0].valid, _in_valids_T) node _in_valids_T_2 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _in_valids_T_3 = and(io.in[1].valid, _in_valids_T_2) node in_valids = cat(_in_valids_T_3, _in_valids_T_1) node _chosen_T = and(in_valids, lock_0) node _chosen_T_1 = not(UInt<2>(0h0)) node _chosen_T_2 = and(_chosen_T, _chosen_T_1) node _chosen_T_3 = orr(_chosen_T_2) node chosen = mux(_chosen_T_3, lock_0, choices[0]) connect io.chosen_oh[0], chosen node _io_out_0_valid_T = and(in_valids, chosen) node _io_out_0_valid_T_1 = orr(_io_out_0_valid_T) connect io.out[0].valid, _io_out_0_valid_T_1 node _io_out_0_bits_T = bits(chosen, 0, 0) node _io_out_0_bits_T_1 = bits(chosen, 1, 1) wire _io_out_0_bits_WIRE : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[2]}, tail : UInt<1>} node _io_out_0_bits_T_2 = mux(_io_out_0_bits_T, io.in[0].bits.tail, UInt<1>(0h0)) node _io_out_0_bits_T_3 = mux(_io_out_0_bits_T_1, io.in[1].bits.tail, UInt<1>(0h0)) node _io_out_0_bits_T_4 = or(_io_out_0_bits_T_2, _io_out_0_bits_T_3) wire _io_out_0_bits_WIRE_1 : UInt<1> connect _io_out_0_bits_WIRE_1, _io_out_0_bits_T_4 connect _io_out_0_bits_WIRE.tail, _io_out_0_bits_WIRE_1 wire _io_out_0_bits_WIRE_2 : { `1` : UInt<1>[1], `0` : UInt<1>[2]} wire _io_out_0_bits_WIRE_3 : UInt<1>[2] node _io_out_0_bits_T_5 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[0], UInt<1>(0h0)) node _io_out_0_bits_T_6 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[0], UInt<1>(0h0)) node _io_out_0_bits_T_7 = or(_io_out_0_bits_T_5, _io_out_0_bits_T_6) wire _io_out_0_bits_WIRE_4 : UInt<1> connect _io_out_0_bits_WIRE_4, _io_out_0_bits_T_7 connect _io_out_0_bits_WIRE_3[0], _io_out_0_bits_WIRE_4 node _io_out_0_bits_T_8 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[1], UInt<1>(0h0)) node _io_out_0_bits_T_9 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[1], UInt<1>(0h0)) node _io_out_0_bits_T_10 = or(_io_out_0_bits_T_8, _io_out_0_bits_T_9) wire _io_out_0_bits_WIRE_5 : UInt<1> connect _io_out_0_bits_WIRE_5, _io_out_0_bits_T_10 connect _io_out_0_bits_WIRE_3[1], _io_out_0_bits_WIRE_5 connect _io_out_0_bits_WIRE_2.`0`, _io_out_0_bits_WIRE_3 wire _io_out_0_bits_WIRE_6 : UInt<1>[1] node _io_out_0_bits_T_11 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`1`[0], UInt<1>(0h0)) node _io_out_0_bits_T_12 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`1`[0], UInt<1>(0h0)) node _io_out_0_bits_T_13 = or(_io_out_0_bits_T_11, _io_out_0_bits_T_12) wire _io_out_0_bits_WIRE_7 : UInt<1> connect _io_out_0_bits_WIRE_7, _io_out_0_bits_T_13 connect _io_out_0_bits_WIRE_6[0], _io_out_0_bits_WIRE_7 connect _io_out_0_bits_WIRE_2.`1`, _io_out_0_bits_WIRE_6 connect _io_out_0_bits_WIRE.vc_sel, _io_out_0_bits_WIRE_2 connect io.out[0].bits, _io_out_0_bits_WIRE node _T_6 = bits(chosen, 0, 0) node _T_7 = and(_T_6, io.out[0].ready) when _T_7 : connect io.in[0].ready, UInt<1>(0h1) node _T_8 = bits(chosen, 1, 1) node _T_9 = and(_T_8, io.out[0].ready) when _T_9 : connect io.in[1].ready, UInt<1>(0h1) node _T_10 = or(UInt<2>(0h0), chosen) node _T_11 = and(io.out[0].ready, io.out[0].valid) when _T_11 : node _lock_0_T = not(in_tails) node _lock_0_T_1 = and(chosen, _lock_0_T) connect lock_0, _lock_0_T_1 node _T_12 = and(io.out[0].ready, io.out[0].valid) when _T_12 : node _mask_T = shr(io.chosen_oh[0], 0) node _mask_T_1 = shr(io.chosen_oh[0], 1) node _mask_T_2 = or(_mask_T, _mask_T_1) connect mask, _mask_T_2 else : node _mask_T_3 = not(mask) node _mask_T_4 = eq(_mask_T_3, UInt<1>(0h0)) node _mask_T_5 = shl(mask, 1) node _mask_T_6 = or(_mask_T_5, UInt<1>(0h1)) node _mask_T_7 = mux(_mask_T_4, UInt<1>(0h0), _mask_T_6) connect mask, _mask_T_7
module SwitchArbiter_132( // @[SwitchAllocator.scala:17:7] input clock, // @[SwitchAllocator.scala:17:7] input reset, // @[SwitchAllocator.scala:17:7] output io_in_0_ready, // @[SwitchAllocator.scala:18:14] input io_in_0_valid, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_1_ready, // @[SwitchAllocator.scala:18:14] input io_in_1_valid, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_tail, // @[SwitchAllocator.scala:18:14] input io_out_0_ready, // @[SwitchAllocator.scala:18:14] output io_out_0_valid, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_tail, // @[SwitchAllocator.scala:18:14] output [1:0] io_chosen_oh_0 // @[SwitchAllocator.scala:18:14] ); reg [1:0] lock_0; // @[SwitchAllocator.scala:24:38] wire [1:0] unassigned = {io_in_1_valid, io_in_0_valid} & ~lock_0; // @[SwitchAllocator.scala:24:38, :25:{23,52,54}] reg [1:0] mask; // @[SwitchAllocator.scala:27:21] wire [1:0] _sel_T_1 = unassigned & ~mask; // @[SwitchAllocator.scala:25:52, :27:21, :30:{58,60}] wire [3:0] sel = _sel_T_1[0] ? 4'h1 : _sel_T_1[1] ? 4'h2 : unassigned[0] ? 4'h4 : {unassigned[1], 3'h0}; // @[OneHot.scala:85:71] wire [1:0] in_valids = {io_in_1_valid, io_in_0_valid}; // @[SwitchAllocator.scala:41:24] wire [1:0] chosen = (|(in_valids & lock_0)) ? lock_0 : sel[1:0] | sel[3:2]; // @[Mux.scala:50:70] wire [1:0] _io_out_0_valid_T = in_valids & chosen; // @[SwitchAllocator.scala:41:24, :42:21, :44:35] wire _GEN = io_out_0_ready & (|_io_out_0_valid_T); // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[SwitchAllocator.scala:17:7] if (reset) begin // @[SwitchAllocator.scala:17:7] lock_0 <= 2'h0; // @[SwitchAllocator.scala:24:38] mask <= 2'h0; // @[SwitchAllocator.scala:27:21] end else begin // @[SwitchAllocator.scala:17:7] if (_GEN) // @[Decoupled.scala:51:35] lock_0 <= chosen & ~{io_in_1_bits_tail, io_in_0_bits_tail}; // @[SwitchAllocator.scala:24:38, :39:21, :42:21, :53:{25,27}] mask <= _GEN ? {chosen[1], |chosen} : (&mask) ? 2'h0 : {mask[0], 1'h1}; // @[Decoupled.scala:51:35] end always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module MSHR_75 : input clock : Clock input reset : Reset output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}}, status : { valid : UInt<1>, bits : { set : UInt<11>, tag : UInt<9>, way : UInt<4>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<9>, set : UInt<11>, param : UInt<3>, source : UInt<4>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<9>, set : UInt<11>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<9>, set : UInt<11>, way : UInt<4>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<11>, way : UInt<4>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<11>, tag : UInt<9>, source : UInt<6>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<4>}}, flip nestedwb : { set : UInt<11>, tag : UInt<9>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}} regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>}, clock regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}, clock when meta_valid : node _T = eq(meta.state, UInt<2>(0h0)) when _T : node _T_1 = orr(meta.clients) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _T_6 = eq(meta.dirty, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = eq(meta.state, UInt<2>(0h1)) when _T_10 : node _T_11 = eq(meta.dirty, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 node _T_15 = eq(meta.state, UInt<2>(0h2)) when _T_15 : node _T_16 = orr(meta.clients) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3 assert(clock, _T_16, UInt<1>(0h1), "") : assert_3 node _T_20 = sub(meta.clients, UInt<1>(0h1)) node _T_21 = tail(_T_20, 1) node _T_22 = and(meta.clients, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4 assert(clock, _T_23, UInt<1>(0h1), "") : assert_4 node _T_27 = eq(meta.state, UInt<2>(0h3)) when _T_27 : skip regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1) reg sink : UInt<3>, clock reg gotT : UInt<1>, clock reg bad_grant : UInt<1>, clock reg probes_done : UInt<1>, clock reg probes_toN : UInt<1>, clock reg probes_noT : UInt<1>, clock node _T_28 = neq(meta.state, UInt<2>(0h0)) node _T_29 = and(meta_valid, _T_28) node _T_30 = eq(io.nestedwb.set, request.set) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.nestedwb.tag, meta.tag) node _T_33 = and(_T_31, _T_32) when _T_33 : when io.nestedwb.b_clr_dirty : connect meta.dirty, UInt<1>(0h0) when io.nestedwb.c_set_dirty : connect meta.dirty, UInt<1>(0h1) when io.nestedwb.b_toB : connect meta.state, UInt<2>(0h1) when io.nestedwb.b_toN : connect meta.hit, UInt<1>(0h0) connect io.status.valid, request_valid connect io.status.bits.set, request.set connect io.status.bits.tag, request.tag connect io.status.bits.way, meta.way node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0)) node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0)) node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2) node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4) node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6) node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7) connect io.status.bits.blockB, _io_status_bits_blockB_T_8 node _io_status_bits_nestB_T = and(meta_valid, w_releaseack) node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast) node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast) node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3) connect io.status.bits.nestB, _io_status_bits_nestB_T_4 node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0)) connect io.status.bits.blockC, _io_status_bits_blockC_T node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1) node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3) node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4) connect io.status.bits.nestC, _io_status_bits_nestC_T_5 node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0)) node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0)) node _T_36 = or(_T_34, _T_35) node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : node _T_39 = eq(_T_36, UInt<1>(0h0)) when _T_39 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB || !io.status.bits.blockB)\n") : printf_5 assert(clock, _T_36, UInt<1>(0h1), "") : assert_5 node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0)) node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0)) node _T_42 = or(_T_40, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC || !io.status.bits.blockC)\n") : printf_6 assert(clock, _T_42, UInt<1>(0h1), "") : assert_6 node _no_wait_T = and(w_rprobeacklast, w_releaseack) node _no_wait_T_1 = and(_no_wait_T, w_grantlast) node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast) node no_wait = and(_no_wait_T_2, w_grantack) node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0)) node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release) node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe) connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2 node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1) connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2 node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst) node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst) node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3) connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4 node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0)) node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack) node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant) connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2 node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0)) node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst) connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1 node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0)) node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack) connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1 node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst) node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait) node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3) connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4 connect io.schedule.bits.reload, no_wait node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid) node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid) node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid) node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid) node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid) node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid) connect io.schedule.valid, _io_schedule_valid_T_5 when io.schedule.ready : connect s_rprobe, UInt<1>(0h1) when w_rprobeackfirst : connect s_release, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) node _T_46 = and(s_release, s_pprobe) when _T_46 : connect s_acquire, UInt<1>(0h1) when w_releaseack : connect s_flush, UInt<1>(0h1) when w_pprobeackfirst : connect s_probeack, UInt<1>(0h1) when w_grantfirst : connect s_grantack, UInt<1>(0h1) node _T_47 = and(w_pprobeack, w_grant) when _T_47 : connect s_execute, UInt<1>(0h1) when no_wait : connect s_writeback, UInt<1>(0h1) when no_wait : connect request_valid, UInt<1>(0h0) connect meta_valid, UInt<1>(0h0) wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>} connect final_meta_writeback, meta node req_clientBit = eq(request.source, UInt<6>(0h28)) node _req_needT_T = bits(request.opcode, 2, 2) node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0)) node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5)) node _req_needT_T_3 = eq(request.param, UInt<1>(0h1)) node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3) node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4) node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6)) node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7)) node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7) node _req_needT_T_9 = neq(request.param, UInt<2>(0h0)) node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9) node req_needT = or(_req_needT_T_5, _req_needT_T_10) node _req_acquire_T = eq(request.opcode, UInt<3>(0h6)) node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7)) node req_acquire = or(_req_acquire_T, _req_acquire_T_1) node _meta_no_clients_T = orr(meta.clients) node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0)) node _req_promoteT_T = eq(meta.state, UInt<2>(0h3)) node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T) node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT) node req_promoteT = and(req_acquire, _req_promoteT_T_2) node _T_48 = and(request.prio[2], UInt<1>(0h1)) when _T_48 : node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0) node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1 node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3)) node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2)) node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1) node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state) connect final_meta_writeback.state, _final_meta_writeback_state_T_3 node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1)) node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2)) node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1) node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5)) node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3) node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5) node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7 connect final_meta_writeback.hit, UInt<1>(0h1) else : node _T_49 = and(request.control, UInt<1>(0h1)) when _T_49 : when meta.hit : connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) node _final_meta_writeback_clients_T_8 = not(probes_toN) node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9 connect final_meta_writeback.hit, UInt<1>(0h0) else : node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty) node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2) node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0)) node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5 node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0)) node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1)) node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire) node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state) node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1)) node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state) node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11) node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state) node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13) node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15) node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16) connect final_meta_writeback.state, _final_meta_writeback_state_T_17 node _final_meta_writeback_clients_T_10 = not(probes_toN) node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10) node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0)) node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14 connect final_meta_writeback.tag, request.tag connect final_meta_writeback.hit, UInt<1>(0h1) when bad_grant : when meta.hit : node _T_50 = eq(meta_valid, UInt<1>(0h0)) node _T_51 = eq(meta.state, UInt<2>(0h1)) node _T_52 = or(_T_50, _T_51) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid || meta.state === BRANCH)\n") : printf_7 assert(clock, _T_52, UInt<1>(0h1), "") : assert_7 connect final_meta_writeback.hit, UInt<1>(0h1) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h1) node _final_meta_writeback_clients_T_15 = not(probes_toN) node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16 else : connect final_meta_writeback.hit, UInt<1>(0h0) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) connect final_meta_writeback.clients, UInt<1>(0h0) wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} connect invalid.dirty, UInt<1>(0h0) connect invalid.state, UInt<2>(0h0) connect invalid.clients, UInt<1>(0h0) connect invalid.tag, UInt<1>(0h0) node _honour_BtoT_T = and(meta.clients, req_clientBit) node _honour_BtoT_T_1 = orr(_honour_BtoT_T) node honour_BtoT = and(meta.hit, _honour_BtoT_T_1) node _excluded_client_T = and(meta.hit, request.prio[0]) node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6)) node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7)) node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2) node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4)) node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4) node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5)) node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0)) node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7) node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8) node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0)) connect io.schedule.bits.a.bits.tag, request.tag connect io.schedule.bits.a.bits.set, request.set node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0)) connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1 node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6)) node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7)) node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2) node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4) connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5 connect io.schedule.bits.a.bits.source, UInt<1>(0h0) node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1) node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2) connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3 node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag) connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1 connect io.schedule.bits.b.bits.set, request.set node _io_schedule_bits_b_bits_clients_T = not(excluded_client) node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T) connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1 node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6)) connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1)) node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1)) connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1 connect io.schedule.bits.c.bits.source, UInt<1>(0h0) connect io.schedule.bits.c.bits.tag, meta.tag connect io.schedule.bits.c.bits.set, request.set connect io.schedule.bits.c.bits.way, meta.way connect io.schedule.bits.c.bits.dirty, meta.dirty connect io.schedule.bits.d.bits.set, request.set connect io.schedule.bits.d.bits.put, request.put connect io.schedule.bits.d.bits.offset, request.offset connect io.schedule.bits.d.bits.tag, request.tag connect io.schedule.bits.d.bits.source, request.source connect io.schedule.bits.d.bits.size, request.size connect io.schedule.bits.d.bits.param, request.param connect io.schedule.bits.d.bits.opcode, request.opcode connect io.schedule.bits.d.bits.control, request.control connect io.schedule.bits.d.bits.prio, request.prio node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0)) node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0)) node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param) node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param) node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param) node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4) node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param) node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6) node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8) connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9 connect io.schedule.bits.d.bits.sink, UInt<1>(0h0) connect io.schedule.bits.d.bits.way, meta.way connect io.schedule.bits.d.bits.bad, bad_grant connect io.schedule.bits.e.bits.sink, sink connect io.schedule.bits.x.bits.fail, UInt<1>(0h0) connect io.schedule.bits.dir.bits.set, request.set connect io.schedule.bits.dir.bits.way, meta.way node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0)) wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE) connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1 node _evict_T = eq(meta.hit, UInt<1>(0h0)) wire evict : UInt connect evict, UInt<1>(0h0) node evict_c = orr(meta.clients) node _evict_T_1 = eq(UInt<2>(0h1), meta.state) when _evict_T_1 : node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1)) connect evict, _evict_out_T else : node _evict_T_2 = eq(UInt<2>(0h2), meta.state) when _evict_T_2 : node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect evict, _evict_out_T_1 else : node _evict_T_3 = eq(UInt<2>(0h3), meta.state) when _evict_T_3 : node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3) connect evict, _evict_out_T_4 else : node _evict_T_4 = eq(UInt<2>(0h0), meta.state) when _evict_T_4 : connect evict, UInt<4>(0h8) node _evict_T_5 = eq(_evict_T, UInt<1>(0h0)) when _evict_T_5 : connect evict, UInt<4>(0h8) wire before : UInt connect before, UInt<1>(0h0) node before_c = orr(meta.clients) node _before_T = eq(UInt<2>(0h1), meta.state) when _before_T : node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1)) connect before, _before_out_T else : node _before_T_1 = eq(UInt<2>(0h2), meta.state) when _before_T_1 : node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect before, _before_out_T_1 else : node _before_T_2 = eq(UInt<2>(0h3), meta.state) when _before_T_2 : node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3) connect before, _before_out_T_4 else : node _before_T_3 = eq(UInt<2>(0h0), meta.state) when _before_T_3 : connect before, UInt<4>(0h8) node _before_T_4 = eq(meta.hit, UInt<1>(0h0)) when _before_T_4 : connect before, UInt<4>(0h8) wire after : UInt connect after, UInt<1>(0h0) node after_c = orr(final_meta_writeback.clients) node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _after_T : node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1)) connect after, _after_out_T else : node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _after_T_1 : node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect after, _after_out_T_1 else : node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _after_T_2 : node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3) connect after, _after_out_T_4 else : node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _after_T_3 : connect after, UInt<4>(0h8) node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _after_T_4 : connect after, UInt<4>(0h8) node _T_56 = eq(s_release, UInt<1>(0h0)) node _T_57 = and(_T_56, w_rprobeackfirst) node _T_58 = and(_T_57, io.schedule.ready) when _T_58 : node _T_59 = eq(evict, UInt<1>(0h1)) node _T_60 = eq(_T_59, UInt<1>(0h0)) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8 assert(clock, _T_60, UInt<1>(0h1), "") : assert_8 node _T_64 = eq(before, UInt<1>(0h1)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9 assert(clock, _T_65, UInt<1>(0h1), "") : assert_9 node _T_69 = eq(evict, UInt<1>(0h0)) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10 assert(clock, _T_70, UInt<1>(0h1), "") : assert_10 node _T_74 = eq(before, UInt<1>(0h0)) node _T_75 = eq(_T_74, UInt<1>(0h0)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11 assert(clock, _T_75, UInt<1>(0h1), "") : assert_11 node _T_79 = eq(evict, UInt<3>(0h7)) node _T_80 = eq(before, UInt<3>(0h7)) node _T_81 = eq(evict, UInt<3>(0h5)) node _T_82 = eq(before, UInt<3>(0h5)) node _T_83 = eq(evict, UInt<3>(0h4)) node _T_84 = eq(before, UInt<3>(0h4)) node _T_85 = eq(evict, UInt<3>(0h6)) node _T_86 = eq(before, UInt<3>(0h6)) node _T_87 = eq(evict, UInt<2>(0h3)) node _T_88 = eq(before, UInt<2>(0h3)) node _T_89 = eq(evict, UInt<2>(0h2)) node _T_90 = eq(before, UInt<2>(0h2)) node _T_91 = eq(s_writeback, UInt<1>(0h0)) node _T_92 = and(_T_91, no_wait) node _T_93 = and(_T_92, io.schedule.ready) when _T_93 : node _T_94 = eq(before, UInt<4>(0h8)) node _T_95 = eq(after, UInt<1>(0h1)) node _T_96 = and(_T_94, _T_95) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12 assert(clock, _T_97, UInt<1>(0h1), "") : assert_12 node _T_101 = eq(before, UInt<4>(0h8)) node _T_102 = eq(after, UInt<1>(0h0)) node _T_103 = and(_T_101, _T_102) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = asUInt(reset) node _T_106 = eq(_T_105, UInt<1>(0h0)) when _T_106 : node _T_107 = eq(_T_104, UInt<1>(0h0)) when _T_107 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13 assert(clock, _T_104, UInt<1>(0h1), "") : assert_13 node _T_108 = eq(before, UInt<4>(0h8)) node _T_109 = eq(after, UInt<3>(0h7)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(before, UInt<4>(0h8)) node _T_112 = eq(after, UInt<3>(0h5)) node _T_113 = and(_T_111, _T_112) node _T_114 = eq(_T_113, UInt<1>(0h0)) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14 assert(clock, _T_114, UInt<1>(0h1), "") : assert_14 node _T_118 = eq(before, UInt<4>(0h8)) node _T_119 = eq(after, UInt<3>(0h4)) node _T_120 = and(_T_118, _T_119) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(_T_121, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15 assert(clock, _T_121, UInt<1>(0h1), "") : assert_15 node _T_125 = eq(before, UInt<4>(0h8)) node _T_126 = eq(after, UInt<3>(0h6)) node _T_127 = and(_T_125, _T_126) node _T_128 = eq(before, UInt<4>(0h8)) node _T_129 = eq(after, UInt<2>(0h3)) node _T_130 = and(_T_128, _T_129) node _T_131 = eq(before, UInt<4>(0h8)) node _T_132 = eq(after, UInt<2>(0h2)) node _T_133 = and(_T_131, _T_132) node _T_134 = eq(_T_133, UInt<1>(0h0)) node _T_135 = asUInt(reset) node _T_136 = eq(_T_135, UInt<1>(0h0)) when _T_136 : node _T_137 = eq(_T_134, UInt<1>(0h0)) when _T_137 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16 assert(clock, _T_134, UInt<1>(0h1), "") : assert_16 node _T_138 = eq(before, UInt<1>(0h1)) node _T_139 = eq(after, UInt<4>(0h8)) node _T_140 = and(_T_138, _T_139) node _T_141 = eq(_T_140, UInt<1>(0h0)) node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : node _T_144 = eq(_T_141, UInt<1>(0h0)) when _T_144 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17 assert(clock, _T_141, UInt<1>(0h1), "") : assert_17 node _T_145 = eq(before, UInt<1>(0h1)) node _T_146 = eq(after, UInt<1>(0h0)) node _T_147 = and(_T_145, _T_146) node _T_148 = eq(_T_147, UInt<1>(0h0)) node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_T_148, UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18 assert(clock, _T_148, UInt<1>(0h1), "") : assert_18 node _T_152 = eq(before, UInt<1>(0h1)) node _T_153 = eq(after, UInt<3>(0h7)) node _T_154 = and(_T_152, _T_153) node _T_155 = eq(_T_154, UInt<1>(0h0)) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19 assert(clock, _T_155, UInt<1>(0h1), "") : assert_19 node _T_159 = eq(before, UInt<1>(0h1)) node _T_160 = eq(after, UInt<3>(0h5)) node _T_161 = and(_T_159, _T_160) node _T_162 = eq(_T_161, UInt<1>(0h0)) node _T_163 = asUInt(reset) node _T_164 = eq(_T_163, UInt<1>(0h0)) when _T_164 : node _T_165 = eq(_T_162, UInt<1>(0h0)) when _T_165 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20 assert(clock, _T_162, UInt<1>(0h1), "") : assert_20 node _T_166 = eq(before, UInt<1>(0h1)) node _T_167 = eq(after, UInt<3>(0h4)) node _T_168 = and(_T_166, _T_167) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21 assert(clock, _T_169, UInt<1>(0h1), "") : assert_21 node _T_173 = eq(before, UInt<1>(0h1)) node _T_174 = eq(after, UInt<3>(0h6)) node _T_175 = and(_T_173, _T_174) node _T_176 = eq(_T_175, UInt<1>(0h0)) node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_T_176, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22 assert(clock, _T_176, UInt<1>(0h1), "") : assert_22 node _T_180 = eq(before, UInt<1>(0h1)) node _T_181 = eq(after, UInt<2>(0h3)) node _T_182 = and(_T_180, _T_181) node _T_183 = eq(_T_182, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(before, UInt<1>(0h1)) node _T_188 = eq(after, UInt<2>(0h2)) node _T_189 = and(_T_187, _T_188) node _T_190 = eq(_T_189, UInt<1>(0h0)) node _T_191 = asUInt(reset) node _T_192 = eq(_T_191, UInt<1>(0h0)) when _T_192 : node _T_193 = eq(_T_190, UInt<1>(0h0)) when _T_193 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24 assert(clock, _T_190, UInt<1>(0h1), "") : assert_24 node _T_194 = eq(before, UInt<1>(0h0)) node _T_195 = eq(after, UInt<4>(0h8)) node _T_196 = and(_T_194, _T_195) node _T_197 = eq(_T_196, UInt<1>(0h0)) node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(_T_197, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25 assert(clock, _T_197, UInt<1>(0h1), "") : assert_25 node _T_201 = eq(before, UInt<1>(0h0)) node _T_202 = eq(after, UInt<1>(0h1)) node _T_203 = and(_T_201, _T_202) node _T_204 = eq(_T_203, UInt<1>(0h0)) node _T_205 = asUInt(reset) node _T_206 = eq(_T_205, UInt<1>(0h0)) when _T_206 : node _T_207 = eq(_T_204, UInt<1>(0h0)) when _T_207 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26 assert(clock, _T_204, UInt<1>(0h1), "") : assert_26 node _T_208 = eq(before, UInt<1>(0h0)) node _T_209 = eq(after, UInt<3>(0h7)) node _T_210 = and(_T_208, _T_209) node _T_211 = eq(_T_210, UInt<1>(0h0)) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27 assert(clock, _T_211, UInt<1>(0h1), "") : assert_27 node _T_215 = eq(before, UInt<1>(0h0)) node _T_216 = eq(after, UInt<3>(0h5)) node _T_217 = and(_T_215, _T_216) node _T_218 = eq(_T_217, UInt<1>(0h0)) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28 assert(clock, _T_218, UInt<1>(0h1), "") : assert_28 node _T_222 = eq(before, UInt<1>(0h0)) node _T_223 = eq(after, UInt<3>(0h6)) node _T_224 = and(_T_222, _T_223) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29 assert(clock, _T_225, UInt<1>(0h1), "") : assert_29 node _T_229 = eq(before, UInt<1>(0h0)) node _T_230 = eq(after, UInt<3>(0h4)) node _T_231 = and(_T_229, _T_230) node _T_232 = eq(_T_231, UInt<1>(0h0)) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(before, UInt<1>(0h0)) node _T_237 = eq(after, UInt<2>(0h3)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31 assert(clock, _T_239, UInt<1>(0h1), "") : assert_31 node _T_243 = eq(before, UInt<1>(0h0)) node _T_244 = eq(after, UInt<2>(0h2)) node _T_245 = and(_T_243, _T_244) node _T_246 = eq(_T_245, UInt<1>(0h0)) node _T_247 = asUInt(reset) node _T_248 = eq(_T_247, UInt<1>(0h0)) when _T_248 : node _T_249 = eq(_T_246, UInt<1>(0h0)) when _T_249 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32 assert(clock, _T_246, UInt<1>(0h1), "") : assert_32 node _T_250 = eq(before, UInt<3>(0h7)) node _T_251 = eq(after, UInt<4>(0h8)) node _T_252 = and(_T_250, _T_251) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33 assert(clock, _T_253, UInt<1>(0h1), "") : assert_33 node _T_257 = eq(before, UInt<3>(0h7)) node _T_258 = eq(after, UInt<1>(0h1)) node _T_259 = and(_T_257, _T_258) node _T_260 = eq(_T_259, UInt<1>(0h0)) node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(_T_260, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34 assert(clock, _T_260, UInt<1>(0h1), "") : assert_34 node _T_264 = eq(before, UInt<3>(0h7)) node _T_265 = eq(after, UInt<1>(0h0)) node _T_266 = and(_T_264, _T_265) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = asUInt(reset) node _T_269 = eq(_T_268, UInt<1>(0h0)) when _T_269 : node _T_270 = eq(_T_267, UInt<1>(0h0)) when _T_270 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35 assert(clock, _T_267, UInt<1>(0h1), "") : assert_35 node _T_271 = eq(before, UInt<3>(0h7)) node _T_272 = eq(after, UInt<3>(0h5)) node _T_273 = and(_T_271, _T_272) node _T_274 = eq(_T_273, UInt<1>(0h0)) node _T_275 = asUInt(reset) node _T_276 = eq(_T_275, UInt<1>(0h0)) when _T_276 : node _T_277 = eq(_T_274, UInt<1>(0h0)) when _T_277 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36 assert(clock, _T_274, UInt<1>(0h1), "") : assert_36 node _T_278 = eq(before, UInt<3>(0h7)) node _T_279 = eq(after, UInt<3>(0h6)) node _T_280 = and(_T_278, _T_279) node _T_281 = eq(before, UInt<3>(0h7)) node _T_282 = eq(after, UInt<3>(0h4)) node _T_283 = and(_T_281, _T_282) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37 assert(clock, _T_284, UInt<1>(0h1), "") : assert_37 node _T_288 = eq(before, UInt<3>(0h7)) node _T_289 = eq(after, UInt<2>(0h3)) node _T_290 = and(_T_288, _T_289) node _T_291 = eq(before, UInt<3>(0h7)) node _T_292 = eq(after, UInt<2>(0h2)) node _T_293 = and(_T_291, _T_292) node _T_294 = eq(_T_293, UInt<1>(0h0)) node _T_295 = asUInt(reset) node _T_296 = eq(_T_295, UInt<1>(0h0)) when _T_296 : node _T_297 = eq(_T_294, UInt<1>(0h0)) when _T_297 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38 assert(clock, _T_294, UInt<1>(0h1), "") : assert_38 node _T_298 = eq(before, UInt<3>(0h5)) node _T_299 = eq(after, UInt<4>(0h8)) node _T_300 = and(_T_298, _T_299) node _T_301 = eq(_T_300, UInt<1>(0h0)) node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(_T_301, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39 assert(clock, _T_301, UInt<1>(0h1), "") : assert_39 node _T_305 = eq(before, UInt<3>(0h5)) node _T_306 = eq(after, UInt<1>(0h1)) node _T_307 = and(_T_305, _T_306) node _T_308 = eq(_T_307, UInt<1>(0h0)) node _T_309 = asUInt(reset) node _T_310 = eq(_T_309, UInt<1>(0h0)) when _T_310 : node _T_311 = eq(_T_308, UInt<1>(0h0)) when _T_311 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40 assert(clock, _T_308, UInt<1>(0h1), "") : assert_40 node _T_312 = eq(before, UInt<3>(0h5)) node _T_313 = eq(after, UInt<1>(0h0)) node _T_314 = and(_T_312, _T_313) node _T_315 = eq(_T_314, UInt<1>(0h0)) node _T_316 = asUInt(reset) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(_T_315, UInt<1>(0h0)) when _T_318 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41 assert(clock, _T_315, UInt<1>(0h1), "") : assert_41 node _T_319 = eq(before, UInt<3>(0h5)) node _T_320 = eq(after, UInt<3>(0h7)) node _T_321 = and(_T_319, _T_320) node _T_322 = eq(before, UInt<3>(0h5)) node _T_323 = eq(after, UInt<3>(0h6)) node _T_324 = and(_T_322, _T_323) node _T_325 = eq(before, UInt<3>(0h5)) node _T_326 = eq(after, UInt<3>(0h4)) node _T_327 = and(_T_325, _T_326) node _T_328 = eq(_T_327, UInt<1>(0h0)) node _T_329 = asUInt(reset) node _T_330 = eq(_T_329, UInt<1>(0h0)) when _T_330 : node _T_331 = eq(_T_328, UInt<1>(0h0)) when _T_331 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42 assert(clock, _T_328, UInt<1>(0h1), "") : assert_42 node _T_332 = eq(before, UInt<3>(0h5)) node _T_333 = eq(after, UInt<2>(0h3)) node _T_334 = and(_T_332, _T_333) node _T_335 = eq(before, UInt<3>(0h5)) node _T_336 = eq(after, UInt<2>(0h2)) node _T_337 = and(_T_335, _T_336) node _T_338 = eq(_T_337, UInt<1>(0h0)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43 assert(clock, _T_338, UInt<1>(0h1), "") : assert_43 node _T_342 = eq(before, UInt<3>(0h6)) node _T_343 = eq(after, UInt<4>(0h8)) node _T_344 = and(_T_342, _T_343) node _T_345 = eq(_T_344, UInt<1>(0h0)) node _T_346 = asUInt(reset) node _T_347 = eq(_T_346, UInt<1>(0h0)) when _T_347 : node _T_348 = eq(_T_345, UInt<1>(0h0)) when _T_348 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44 assert(clock, _T_345, UInt<1>(0h1), "") : assert_44 node _T_349 = eq(before, UInt<3>(0h6)) node _T_350 = eq(after, UInt<1>(0h1)) node _T_351 = and(_T_349, _T_350) node _T_352 = eq(_T_351, UInt<1>(0h0)) node _T_353 = asUInt(reset) node _T_354 = eq(_T_353, UInt<1>(0h0)) when _T_354 : node _T_355 = eq(_T_352, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45 assert(clock, _T_352, UInt<1>(0h1), "") : assert_45 node _T_356 = eq(before, UInt<3>(0h6)) node _T_357 = eq(after, UInt<1>(0h0)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(_T_358, UInt<1>(0h0)) node _T_360 = asUInt(reset) node _T_361 = eq(_T_360, UInt<1>(0h0)) when _T_361 : node _T_362 = eq(_T_359, UInt<1>(0h0)) when _T_362 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46 assert(clock, _T_359, UInt<1>(0h1), "") : assert_46 node _T_363 = eq(before, UInt<3>(0h6)) node _T_364 = eq(after, UInt<3>(0h7)) node _T_365 = and(_T_363, _T_364) node _T_366 = eq(_T_365, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47 assert(clock, _T_366, UInt<1>(0h1), "") : assert_47 node _T_370 = eq(before, UInt<3>(0h6)) node _T_371 = eq(after, UInt<3>(0h5)) node _T_372 = and(_T_370, _T_371) node _T_373 = eq(_T_372, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48 assert(clock, _T_373, UInt<1>(0h1), "") : assert_48 node _T_377 = eq(before, UInt<3>(0h6)) node _T_378 = eq(after, UInt<3>(0h4)) node _T_379 = and(_T_377, _T_378) node _T_380 = eq(_T_379, UInt<1>(0h0)) node _T_381 = asUInt(reset) node _T_382 = eq(_T_381, UInt<1>(0h0)) when _T_382 : node _T_383 = eq(_T_380, UInt<1>(0h0)) when _T_383 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49 assert(clock, _T_380, UInt<1>(0h1), "") : assert_49 node _T_384 = eq(before, UInt<3>(0h6)) node _T_385 = eq(after, UInt<2>(0h3)) node _T_386 = and(_T_384, _T_385) node _T_387 = eq(_T_386, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50 assert(clock, _T_387, UInt<1>(0h1), "") : assert_50 node _T_391 = eq(before, UInt<3>(0h6)) node _T_392 = eq(after, UInt<2>(0h2)) node _T_393 = and(_T_391, _T_392) node _T_394 = eq(before, UInt<3>(0h4)) node _T_395 = eq(after, UInt<4>(0h8)) node _T_396 = and(_T_394, _T_395) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51 assert(clock, _T_397, UInt<1>(0h1), "") : assert_51 node _T_401 = eq(before, UInt<3>(0h4)) node _T_402 = eq(after, UInt<1>(0h1)) node _T_403 = and(_T_401, _T_402) node _T_404 = eq(_T_403, UInt<1>(0h0)) node _T_405 = asUInt(reset) node _T_406 = eq(_T_405, UInt<1>(0h0)) when _T_406 : node _T_407 = eq(_T_404, UInt<1>(0h0)) when _T_407 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52 assert(clock, _T_404, UInt<1>(0h1), "") : assert_52 node _T_408 = eq(before, UInt<3>(0h4)) node _T_409 = eq(after, UInt<1>(0h0)) node _T_410 = and(_T_408, _T_409) node _T_411 = eq(_T_410, UInt<1>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53 assert(clock, _T_411, UInt<1>(0h1), "") : assert_53 node _T_415 = eq(before, UInt<3>(0h4)) node _T_416 = eq(after, UInt<3>(0h7)) node _T_417 = and(_T_415, _T_416) node _T_418 = eq(_T_417, UInt<1>(0h0)) node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(_T_418, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54 assert(clock, _T_418, UInt<1>(0h1), "") : assert_54 node _T_422 = eq(before, UInt<3>(0h4)) node _T_423 = eq(after, UInt<3>(0h5)) node _T_424 = and(_T_422, _T_423) node _T_425 = eq(_T_424, UInt<1>(0h0)) node _T_426 = asUInt(reset) node _T_427 = eq(_T_426, UInt<1>(0h0)) when _T_427 : node _T_428 = eq(_T_425, UInt<1>(0h0)) when _T_428 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55 assert(clock, _T_425, UInt<1>(0h1), "") : assert_55 node _T_429 = eq(before, UInt<3>(0h4)) node _T_430 = eq(after, UInt<3>(0h6)) node _T_431 = and(_T_429, _T_430) node _T_432 = eq(before, UInt<3>(0h4)) node _T_433 = eq(after, UInt<2>(0h3)) node _T_434 = and(_T_432, _T_433) node _T_435 = eq(_T_434, UInt<1>(0h0)) node _T_436 = asUInt(reset) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(_T_435, UInt<1>(0h0)) when _T_438 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56 assert(clock, _T_435, UInt<1>(0h1), "") : assert_56 node _T_439 = eq(before, UInt<3>(0h4)) node _T_440 = eq(after, UInt<2>(0h2)) node _T_441 = and(_T_439, _T_440) node _T_442 = eq(before, UInt<2>(0h3)) node _T_443 = eq(after, UInt<4>(0h8)) node _T_444 = and(_T_442, _T_443) node _T_445 = eq(_T_444, UInt<1>(0h0)) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57 assert(clock, _T_445, UInt<1>(0h1), "") : assert_57 node _T_449 = eq(before, UInt<2>(0h3)) node _T_450 = eq(after, UInt<1>(0h1)) node _T_451 = and(_T_449, _T_450) node _T_452 = eq(_T_451, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58 assert(clock, _T_452, UInt<1>(0h1), "") : assert_58 node _T_456 = eq(before, UInt<2>(0h3)) node _T_457 = eq(after, UInt<1>(0h0)) node _T_458 = and(_T_456, _T_457) node _T_459 = eq(_T_458, UInt<1>(0h0)) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59 assert(clock, _T_459, UInt<1>(0h1), "") : assert_59 node _T_463 = eq(before, UInt<2>(0h3)) node _T_464 = eq(after, UInt<3>(0h7)) node _T_465 = and(_T_463, _T_464) node _T_466 = eq(before, UInt<2>(0h3)) node _T_467 = eq(after, UInt<3>(0h5)) node _T_468 = and(_T_466, _T_467) node _T_469 = eq(before, UInt<2>(0h3)) node _T_470 = eq(after, UInt<3>(0h6)) node _T_471 = and(_T_469, _T_470) node _T_472 = eq(before, UInt<2>(0h3)) node _T_473 = eq(after, UInt<3>(0h4)) node _T_474 = and(_T_472, _T_473) node _T_475 = eq(before, UInt<2>(0h3)) node _T_476 = eq(after, UInt<2>(0h2)) node _T_477 = and(_T_475, _T_476) node _T_478 = eq(before, UInt<2>(0h2)) node _T_479 = eq(after, UInt<4>(0h8)) node _T_480 = and(_T_478, _T_479) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60 assert(clock, _T_481, UInt<1>(0h1), "") : assert_60 node _T_485 = eq(before, UInt<2>(0h2)) node _T_486 = eq(after, UInt<1>(0h1)) node _T_487 = and(_T_485, _T_486) node _T_488 = eq(_T_487, UInt<1>(0h0)) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61 assert(clock, _T_488, UInt<1>(0h1), "") : assert_61 node _T_492 = eq(before, UInt<2>(0h2)) node _T_493 = eq(after, UInt<1>(0h0)) node _T_494 = and(_T_492, _T_493) node _T_495 = eq(_T_494, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62 assert(clock, _T_495, UInt<1>(0h1), "") : assert_62 node _T_499 = eq(before, UInt<2>(0h2)) node _T_500 = eq(after, UInt<3>(0h7)) node _T_501 = and(_T_499, _T_500) node _T_502 = eq(_T_501, UInt<1>(0h0)) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63 assert(clock, _T_502, UInt<1>(0h1), "") : assert_63 node _T_506 = eq(before, UInt<2>(0h2)) node _T_507 = eq(after, UInt<3>(0h5)) node _T_508 = and(_T_506, _T_507) node _T_509 = eq(_T_508, UInt<1>(0h0)) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64 assert(clock, _T_509, UInt<1>(0h1), "") : assert_64 node _T_513 = eq(before, UInt<2>(0h2)) node _T_514 = eq(after, UInt<3>(0h6)) node _T_515 = and(_T_513, _T_514) node _T_516 = eq(before, UInt<2>(0h2)) node _T_517 = eq(after, UInt<3>(0h4)) node _T_518 = and(_T_516, _T_517) node _T_519 = eq(before, UInt<2>(0h2)) node _T_520 = eq(after, UInt<2>(0h3)) node _T_521 = and(_T_519, _T_520) node _T_522 = eq(_T_521, UInt<1>(0h0)) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65 assert(clock, _T_522, UInt<1>(0h1), "") : assert_65 node probe_bit = eq(io.sinkc.bits.source, UInt<6>(0h28)) node _last_probe_T = or(probes_done, probe_bit) node _last_probe_T_1 = not(excluded_client) node _last_probe_T_2 = and(meta.clients, _last_probe_T_1) node last_probe = eq(_last_probe_T, _last_probe_T_2) node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1)) node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2)) node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1) node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5)) node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3) when io.sinkc.valid : node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_527 = and(probe_toN, _T_526) node _T_528 = eq(probe_toN, UInt<1>(0h0)) node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_530 = and(_T_528, _T_529) node _probes_done_T = or(probes_done, probe_bit) connect probes_done, _probes_done_T node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0)) node _probes_toN_T_1 = or(probes_toN, _probes_toN_T) connect probes_toN, _probes_toN_T_1 node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3)) node _probes_noT_T_1 = or(probes_noT, _probes_noT_T) connect probes_noT, _probes_noT_T_1 node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe) connect w_rprobeackfirst, _w_rprobeackfirst_T node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T) connect w_rprobeacklast, _w_rprobeacklast_T_1 node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe) connect w_pprobeackfirst, _w_pprobeackfirst_T node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T) connect w_pprobeacklast, _w_pprobeacklast_T_1 node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0)) node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T) node set_pprobeack = and(last_probe, _set_pprobeack_T_1) node _w_pprobeack_T = or(w_pprobeack, set_pprobeack) connect w_pprobeack, _w_pprobeack_T node _T_531 = eq(set_pprobeack, UInt<1>(0h0)) node _T_532 = and(_T_531, w_rprobeackfirst) node _T_533 = and(set_pprobeack, w_rprobeackfirst) node _T_534 = neq(meta.state, UInt<2>(0h0)) node _T_535 = eq(io.sinkc.bits.tag, meta.tag) node _T_536 = and(_T_534, _T_535) node _T_537 = and(_T_536, io.sinkc.bits.data) when _T_537 : connect meta.dirty, UInt<1>(0h1) when io.sinkd.valid : node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4)) node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_540 = or(_T_538, _T_539) when _T_540 : connect sink, io.sinkd.bits.sink connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, io.sinkd.bits.last connect bad_grant, io.sinkd.bits.denied node _w_grant_T = eq(request.offset, UInt<1>(0h0)) node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last) connect w_grant, _w_grant_T_1 node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_542 = eq(request.offset, UInt<1>(0h0)) node _T_543 = and(_T_541, _T_542) node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_545 = neq(request.offset, UInt<1>(0h0)) node _T_546 = and(_T_544, _T_545) node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0)) connect gotT, _gotT_T else : node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6)) when _T_547 : connect w_releaseack, UInt<1>(0h1) when io.sinke.valid : connect w_grantack, UInt<1>(0h1) wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>} connect allocate_as_full.set, io.allocate.bits.set connect allocate_as_full.put, io.allocate.bits.put connect allocate_as_full.offset, io.allocate.bits.offset connect allocate_as_full.tag, io.allocate.bits.tag connect allocate_as_full.source, io.allocate.bits.source connect allocate_as_full.size, io.allocate.bits.size connect allocate_as_full.param, io.allocate.bits.param connect allocate_as_full.opcode, io.allocate.bits.opcode connect allocate_as_full.control, io.allocate.bits.control connect allocate_as_full.prio, io.allocate.bits.prio node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat) node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits) node new_request = mux(io.allocate.valid, allocate_as_full, request) node _new_needT_T = bits(new_request.opcode, 2, 2) node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0)) node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5)) node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1)) node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3) node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4) node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6)) node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7)) node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7) node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0)) node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9) node new_needT = or(_new_needT_T_5, _new_needT_T_10) node new_clientBit = eq(new_request.source, UInt<6>(0h28)) node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6)) node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7)) node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1) node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4)) node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3) node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5)) node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0)) node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6) node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0)) wire prior : UInt connect prior, UInt<1>(0h0) node prior_c = orr(final_meta_writeback.clients) node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _prior_T : node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1)) connect prior, _prior_out_T else : node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _prior_T_1 : node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect prior, _prior_out_T_1 else : node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _prior_T_2 : node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3) connect prior, _prior_out_T_4 else : node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _prior_T_3 : connect prior, UInt<4>(0h8) node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _prior_T_4 : connect prior, UInt<4>(0h8) node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat) when _T_548 : node _T_549 = eq(prior, UInt<4>(0h8)) node _T_550 = eq(prior, UInt<1>(0h1)) node _T_551 = eq(_T_550, UInt<1>(0h0)) node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_T_551, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66 assert(clock, _T_551, UInt<1>(0h1), "") : assert_66 node _T_555 = eq(prior, UInt<1>(0h0)) node _T_556 = eq(_T_555, UInt<1>(0h0)) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67 assert(clock, _T_556, UInt<1>(0h1), "") : assert_67 node _T_560 = eq(prior, UInt<3>(0h7)) node _T_561 = eq(prior, UInt<3>(0h5)) node _T_562 = eq(prior, UInt<3>(0h4)) node _T_563 = eq(prior, UInt<3>(0h6)) node _T_564 = eq(prior, UInt<2>(0h3)) node _T_565 = eq(prior, UInt<2>(0h2)) when io.allocate.valid : node _T_566 = eq(request_valid, UInt<1>(0h0)) node _T_567 = and(io.schedule.ready, io.schedule.valid) node _T_568 = and(no_wait, _T_567) node _T_569 = or(_T_566, _T_568) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid || (no_wait && io.schedule.fire))\n") : printf_68 assert(clock, _T_569, UInt<1>(0h1), "") : assert_68 connect request_valid, UInt<1>(0h1) connect request.set, io.allocate.bits.set connect request.put, io.allocate.bits.put connect request.offset, io.allocate.bits.offset connect request.tag, io.allocate.bits.tag connect request.source, io.allocate.bits.source connect request.size, io.allocate.bits.size connect request.param, io.allocate.bits.param connect request.opcode, io.allocate.bits.opcode connect request.control, io.allocate.bits.control connect request.prio, io.allocate.bits.prio node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat) node _T_574 = or(io.directory.valid, _T_573) when _T_574 : connect meta_valid, UInt<1>(0h1) connect meta, new_meta connect probes_done, UInt<1>(0h0) connect probes_toN, UInt<1>(0h0) connect probes_noT, UInt<1>(0h0) connect gotT, UInt<1>(0h0) connect bad_grant, UInt<1>(0h0) connect s_rprobe, UInt<1>(0h1) connect w_rprobeackfirst, UInt<1>(0h1) connect w_rprobeacklast, UInt<1>(0h1) connect s_release, UInt<1>(0h1) connect w_releaseack, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) connect s_acquire, UInt<1>(0h1) connect s_flush, UInt<1>(0h1) connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, UInt<1>(0h1) connect w_grant, UInt<1>(0h1) connect w_pprobeackfirst, UInt<1>(0h1) connect w_pprobeacklast, UInt<1>(0h1) connect w_pprobeack, UInt<1>(0h1) connect s_probeack, UInt<1>(0h1) connect s_grantack, UInt<1>(0h1) connect s_execute, UInt<1>(0h1) connect w_grantack, UInt<1>(0h1) connect s_writeback, UInt<1>(0h1) node _T_575 = and(new_request.prio[2], UInt<1>(0h1)) when _T_575 : connect s_execute, UInt<1>(0h0) node _T_576 = bits(new_request.opcode, 0, 0) node _T_577 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_578 = and(_T_576, _T_577) when _T_578 : connect s_writeback, UInt<1>(0h0) node _T_579 = eq(new_request.param, UInt<3>(0h0)) node _T_580 = eq(new_request.param, UInt<3>(0h4)) node _T_581 = or(_T_579, _T_580) node _T_582 = eq(new_meta.state, UInt<2>(0h2)) node _T_583 = and(_T_581, _T_582) when _T_583 : connect s_writeback, UInt<1>(0h0) node _T_584 = eq(new_request.param, UInt<3>(0h1)) node _T_585 = eq(new_request.param, UInt<3>(0h2)) node _T_586 = or(_T_584, _T_585) node _T_587 = eq(new_request.param, UInt<3>(0h5)) node _T_588 = or(_T_586, _T_587) node _T_589 = and(new_meta.clients, new_clientBit) node _T_590 = neq(_T_589, UInt<1>(0h0)) node _T_591 = and(_T_588, _T_590) when _T_591 : connect s_writeback, UInt<1>(0h0) node _T_592 = asUInt(reset) node _T_593 = eq(_T_592, UInt<1>(0h0)) when _T_593 : node _T_594 = eq(new_meta.hit, UInt<1>(0h0)) when _T_594 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69 assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69 else : node _T_595 = and(new_request.control, UInt<1>(0h1)) when _T_595 : connect s_flush, UInt<1>(0h0) when new_meta.hit : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_596 = neq(new_meta.clients, UInt<1>(0h0)) node _T_597 = and(UInt<1>(0h1), _T_596) when _T_597 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) else : connect s_execute, UInt<1>(0h0) node _T_598 = eq(new_meta.hit, UInt<1>(0h0)) node _T_599 = neq(new_meta.state, UInt<2>(0h0)) node _T_600 = and(_T_598, _T_599) when _T_600 : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_601 = neq(new_meta.clients, UInt<1>(0h0)) node _T_602 = and(UInt<1>(0h1), _T_601) when _T_602 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) node _T_603 = eq(new_meta.hit, UInt<1>(0h0)) node _T_604 = eq(new_meta.state, UInt<2>(0h1)) node _T_605 = and(_T_604, new_needT) node _T_606 = or(_T_603, _T_605) when _T_606 : connect s_acquire, UInt<1>(0h0) connect w_grantfirst, UInt<1>(0h0) connect w_grantlast, UInt<1>(0h0) connect w_grant, UInt<1>(0h0) connect s_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_607 = eq(new_meta.state, UInt<2>(0h2)) node _T_608 = or(new_needT, _T_607) node _T_609 = and(new_meta.hit, _T_608) node _T_610 = not(new_skipProbe) node _T_611 = and(new_meta.clients, _T_610) node _T_612 = neq(_T_611, UInt<1>(0h0)) node _T_613 = and(_T_609, _T_612) node _T_614 = and(UInt<1>(0h1), _T_613) when _T_614 : connect s_pprobe, UInt<1>(0h0) connect w_pprobeackfirst, UInt<1>(0h0) connect w_pprobeacklast, UInt<1>(0h0) connect w_pprobeack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_615 = eq(new_request.opcode, UInt<3>(0h6)) node _T_616 = eq(new_request.opcode, UInt<3>(0h7)) node _T_617 = or(_T_615, _T_616) when _T_617 : connect w_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_618 = bits(new_request.opcode, 2, 2) node _T_619 = eq(_T_618, UInt<1>(0h0)) node _T_620 = and(_T_619, new_meta.hit) node _T_621 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_622 = and(_T_620, _T_621) when _T_622 : connect s_writeback, UInt<1>(0h0)
module MSHR_75( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [8:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [10:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input io_directory_bits_clients, // @[MSHR.scala:86:14] input [8:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [3:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [10:0] io_status_bits_set, // @[MSHR.scala:86:14] output [8:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [3:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [10:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [8:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [10:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [8:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [8:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [8:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [10:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [8:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [3:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [10:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [8:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [10:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [8:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire invalid_clients = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire [8:0] invalid_tag = 9'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [8:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [10:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [8:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [8:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [10:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [8:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [3:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] reg [8:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [10:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg meta_clients; // @[MSHR.scala:100:17] wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39] wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27] reg [8:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [3:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [3:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg probes_done; // @[MSHR.scala:150:24] reg probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire [8:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire req_clientBit = request_source == 6'h28; // @[Parameters.scala:46:9] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}] wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9] wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 9'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire probe_bit = io_sinkc_bits_source_0 == 6'h28; // @[Parameters.scala:46:9] wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:46:9] wire _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9] wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [8:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [3:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [8:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [10:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire new_clientBit = new_request_source == 6'h28; // @[Parameters.scala:46:9] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9] wire [3:0] prior; // @[MSHR.scala:314:26] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_28 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 2, 0) node _source_ok_T_25 = shr(io.in.a.bits.source, 3) node _source_ok_T_26 = eq(_source_ok_T_25, UInt<3>(0h4)) node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27) node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<3>(0h4)) node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[9] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_30 connect _source_ok_WIRE[6], _source_ok_T_31 connect _source_ok_WIRE[7], _source_ok_T_32 connect _source_ok_WIRE[8], _source_ok_T_33 node _source_ok_T_34 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[2]) node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[3]) node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[4]) node _source_ok_T_38 = or(_source_ok_T_37, _source_ok_WIRE[5]) node _source_ok_T_39 = or(_source_ok_T_38, _source_ok_WIRE[6]) node _source_ok_T_40 = or(_source_ok_T_39, _source_ok_WIRE[7]) node source_ok = or(_source_ok_T_40, _source_ok_WIRE[8]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0) node _T_64 = shr(io.in.a.bits.source, 3) node _T_65 = eq(_T_64, UInt<3>(0h4)) node _T_66 = leq(UInt<1>(0h0), uncommonBits_4) node _T_67 = and(_T_65, _T_66) node _T_68 = leq(uncommonBits_4, UInt<3>(0h4)) node _T_69 = and(_T_67, _T_68) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_72 = cvt(_T_71) node _T_73 = and(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = asSInt(_T_73) node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0))) node _T_76 = or(_T_70, _T_75) node _T_77 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_78 = eq(_T_77, UInt<1>(0h0)) node _T_79 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_80 = cvt(_T_79) node _T_81 = and(_T_80, asSInt(UInt<1>(0h0))) node _T_82 = asSInt(_T_81) node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0))) node _T_84 = or(_T_78, _T_83) node _T_85 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_86 = eq(_T_85, UInt<1>(0h0)) node _T_87 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_88 = cvt(_T_87) node _T_89 = and(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = asSInt(_T_89) node _T_91 = eq(_T_90, asSInt(UInt<1>(0h0))) node _T_92 = or(_T_86, _T_91) node _T_93 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_94 = eq(_T_93, UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<1>(0h0))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = or(_T_94, _T_99) node _T_101 = and(_T_11, _T_24) node _T_102 = and(_T_101, _T_37) node _T_103 = and(_T_102, _T_50) node _T_104 = and(_T_103, _T_63) node _T_105 = and(_T_104, _T_76) node _T_106 = and(_T_105, _T_84) node _T_107 = and(_T_106, _T_92) node _T_108 = and(_T_107, _T_100) node _T_109 = asUInt(reset) node _T_110 = eq(_T_109, UInt<1>(0h0)) when _T_110 : node _T_111 = eq(_T_108, UInt<1>(0h0)) when _T_111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_108, UInt<1>(0h1), "") : assert_1 node _T_112 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_112 : node _T_113 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_114 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_115 = and(_T_113, _T_114) node _T_116 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_117 = shr(io.in.a.bits.source, 2) node _T_118 = eq(_T_117, UInt<1>(0h0)) node _T_119 = leq(UInt<1>(0h0), uncommonBits_5) node _T_120 = and(_T_118, _T_119) node _T_121 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_122 = and(_T_120, _T_121) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_123 = shr(io.in.a.bits.source, 2) node _T_124 = eq(_T_123, UInt<1>(0h1)) node _T_125 = leq(UInt<1>(0h0), uncommonBits_6) node _T_126 = and(_T_124, _T_125) node _T_127 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_128 = and(_T_126, _T_127) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_129 = shr(io.in.a.bits.source, 2) node _T_130 = eq(_T_129, UInt<2>(0h2)) node _T_131 = leq(UInt<1>(0h0), uncommonBits_7) node _T_132 = and(_T_130, _T_131) node _T_133 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_134 = and(_T_132, _T_133) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_135 = shr(io.in.a.bits.source, 2) node _T_136 = eq(_T_135, UInt<2>(0h3)) node _T_137 = leq(UInt<1>(0h0), uncommonBits_8) node _T_138 = and(_T_136, _T_137) node _T_139 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_140 = and(_T_138, _T_139) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 2, 0) node _T_141 = shr(io.in.a.bits.source, 3) node _T_142 = eq(_T_141, UInt<3>(0h4)) node _T_143 = leq(UInt<1>(0h0), uncommonBits_9) node _T_144 = and(_T_142, _T_143) node _T_145 = leq(uncommonBits_9, UInt<3>(0h4)) node _T_146 = and(_T_144, _T_145) node _T_147 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_148 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_149 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_150 = or(_T_116, _T_122) node _T_151 = or(_T_150, _T_128) node _T_152 = or(_T_151, _T_134) node _T_153 = or(_T_152, _T_140) node _T_154 = or(_T_153, _T_146) node _T_155 = or(_T_154, _T_147) node _T_156 = or(_T_155, _T_148) node _T_157 = or(_T_156, _T_149) node _T_158 = and(_T_115, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_161 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_162 = cvt(_T_161) node _T_163 = and(_T_162, asSInt(UInt<17>(0h10000))) node _T_164 = asSInt(_T_163) node _T_165 = eq(_T_164, asSInt(UInt<1>(0h0))) node _T_166 = and(_T_160, _T_165) node _T_167 = or(UInt<1>(0h0), _T_166) node _T_168 = and(_T_159, _T_167) node _T_169 = asUInt(reset) node _T_170 = eq(_T_169, UInt<1>(0h0)) when _T_170 : node _T_171 = eq(_T_168, UInt<1>(0h0)) when _T_171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_168, UInt<1>(0h1), "") : assert_2 node _T_172 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_173 = shr(io.in.a.bits.source, 2) node _T_174 = eq(_T_173, UInt<1>(0h0)) node _T_175 = leq(UInt<1>(0h0), uncommonBits_10) node _T_176 = and(_T_174, _T_175) node _T_177 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_178 = and(_T_176, _T_177) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_179 = shr(io.in.a.bits.source, 2) node _T_180 = eq(_T_179, UInt<1>(0h1)) node _T_181 = leq(UInt<1>(0h0), uncommonBits_11) node _T_182 = and(_T_180, _T_181) node _T_183 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_184 = and(_T_182, _T_183) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_185 = shr(io.in.a.bits.source, 2) node _T_186 = eq(_T_185, UInt<2>(0h2)) node _T_187 = leq(UInt<1>(0h0), uncommonBits_12) node _T_188 = and(_T_186, _T_187) node _T_189 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_190 = and(_T_188, _T_189) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_191 = shr(io.in.a.bits.source, 2) node _T_192 = eq(_T_191, UInt<2>(0h3)) node _T_193 = leq(UInt<1>(0h0), uncommonBits_13) node _T_194 = and(_T_192, _T_193) node _T_195 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_196 = and(_T_194, _T_195) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 2, 0) node _T_197 = shr(io.in.a.bits.source, 3) node _T_198 = eq(_T_197, UInt<3>(0h4)) node _T_199 = leq(UInt<1>(0h0), uncommonBits_14) node _T_200 = and(_T_198, _T_199) node _T_201 = leq(uncommonBits_14, UInt<3>(0h4)) node _T_202 = and(_T_200, _T_201) node _T_203 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_204 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_205 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[9] connect _WIRE[0], _T_172 connect _WIRE[1], _T_178 connect _WIRE[2], _T_184 connect _WIRE[3], _T_190 connect _WIRE[4], _T_196 connect _WIRE[5], _T_202 connect _WIRE[6], _T_203 connect _WIRE[7], _T_204 connect _WIRE[8], _T_205 node _T_206 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_207 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_208 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_209 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_210 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_211 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_212 = mux(_WIRE[5], _T_206, UInt<1>(0h0)) node _T_213 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_214 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_215 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_216 = or(_T_207, _T_208) node _T_217 = or(_T_216, _T_209) node _T_218 = or(_T_217, _T_210) node _T_219 = or(_T_218, _T_211) node _T_220 = or(_T_219, _T_212) node _T_221 = or(_T_220, _T_213) node _T_222 = or(_T_221, _T_214) node _T_223 = or(_T_222, _T_215) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_223 node _T_224 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_225 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_226 = and(_T_224, _T_225) node _T_227 = or(UInt<1>(0h0), _T_226) node _T_228 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_229 = cvt(_T_228) node _T_230 = and(_T_229, asSInt(UInt<17>(0h10000))) node _T_231 = asSInt(_T_230) node _T_232 = eq(_T_231, asSInt(UInt<1>(0h0))) node _T_233 = and(_T_227, _T_232) node _T_234 = or(UInt<1>(0h0), _T_233) node _T_235 = and(_WIRE_1, _T_234) node _T_236 = asUInt(reset) node _T_237 = eq(_T_236, UInt<1>(0h0)) when _T_237 : node _T_238 = eq(_T_235, UInt<1>(0h0)) when _T_238 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_235, UInt<1>(0h1), "") : assert_3 node _T_239 = asUInt(reset) node _T_240 = eq(_T_239, UInt<1>(0h0)) when _T_240 : node _T_241 = eq(source_ok, UInt<1>(0h0)) when _T_241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_242 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_243 = asUInt(reset) node _T_244 = eq(_T_243, UInt<1>(0h0)) when _T_244 : node _T_245 = eq(_T_242, UInt<1>(0h0)) when _T_245 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_242, UInt<1>(0h1), "") : assert_5 node _T_246 = asUInt(reset) node _T_247 = eq(_T_246, UInt<1>(0h0)) when _T_247 : node _T_248 = eq(is_aligned, UInt<1>(0h0)) when _T_248 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_249 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_250 = asUInt(reset) node _T_251 = eq(_T_250, UInt<1>(0h0)) when _T_251 : node _T_252 = eq(_T_249, UInt<1>(0h0)) when _T_252 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_249, UInt<1>(0h1), "") : assert_7 node _T_253 = not(io.in.a.bits.mask) node _T_254 = eq(_T_253, UInt<1>(0h0)) node _T_255 = asUInt(reset) node _T_256 = eq(_T_255, UInt<1>(0h0)) when _T_256 : node _T_257 = eq(_T_254, UInt<1>(0h0)) when _T_257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_254, UInt<1>(0h1), "") : assert_8 node _T_258 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_259 = asUInt(reset) node _T_260 = eq(_T_259, UInt<1>(0h0)) when _T_260 : node _T_261 = eq(_T_258, UInt<1>(0h0)) when _T_261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_258, UInt<1>(0h1), "") : assert_9 node _T_262 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_262 : node _T_263 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_264 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_265 = and(_T_263, _T_264) node _T_266 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_267 = shr(io.in.a.bits.source, 2) node _T_268 = eq(_T_267, UInt<1>(0h0)) node _T_269 = leq(UInt<1>(0h0), uncommonBits_15) node _T_270 = and(_T_268, _T_269) node _T_271 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_272 = and(_T_270, _T_271) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_273 = shr(io.in.a.bits.source, 2) node _T_274 = eq(_T_273, UInt<1>(0h1)) node _T_275 = leq(UInt<1>(0h0), uncommonBits_16) node _T_276 = and(_T_274, _T_275) node _T_277 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_278 = and(_T_276, _T_277) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_279 = shr(io.in.a.bits.source, 2) node _T_280 = eq(_T_279, UInt<2>(0h2)) node _T_281 = leq(UInt<1>(0h0), uncommonBits_17) node _T_282 = and(_T_280, _T_281) node _T_283 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_284 = and(_T_282, _T_283) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_285 = shr(io.in.a.bits.source, 2) node _T_286 = eq(_T_285, UInt<2>(0h3)) node _T_287 = leq(UInt<1>(0h0), uncommonBits_18) node _T_288 = and(_T_286, _T_287) node _T_289 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_290 = and(_T_288, _T_289) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 2, 0) node _T_291 = shr(io.in.a.bits.source, 3) node _T_292 = eq(_T_291, UInt<3>(0h4)) node _T_293 = leq(UInt<1>(0h0), uncommonBits_19) node _T_294 = and(_T_292, _T_293) node _T_295 = leq(uncommonBits_19, UInt<3>(0h4)) node _T_296 = and(_T_294, _T_295) node _T_297 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_298 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_299 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_300 = or(_T_266, _T_272) node _T_301 = or(_T_300, _T_278) node _T_302 = or(_T_301, _T_284) node _T_303 = or(_T_302, _T_290) node _T_304 = or(_T_303, _T_296) node _T_305 = or(_T_304, _T_297) node _T_306 = or(_T_305, _T_298) node _T_307 = or(_T_306, _T_299) node _T_308 = and(_T_265, _T_307) node _T_309 = or(UInt<1>(0h0), _T_308) node _T_310 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_311 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_312 = cvt(_T_311) node _T_313 = and(_T_312, asSInt(UInt<17>(0h10000))) node _T_314 = asSInt(_T_313) node _T_315 = eq(_T_314, asSInt(UInt<1>(0h0))) node _T_316 = and(_T_310, _T_315) node _T_317 = or(UInt<1>(0h0), _T_316) node _T_318 = and(_T_309, _T_317) node _T_319 = asUInt(reset) node _T_320 = eq(_T_319, UInt<1>(0h0)) when _T_320 : node _T_321 = eq(_T_318, UInt<1>(0h0)) when _T_321 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_318, UInt<1>(0h1), "") : assert_10 node _T_322 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_323 = shr(io.in.a.bits.source, 2) node _T_324 = eq(_T_323, UInt<1>(0h0)) node _T_325 = leq(UInt<1>(0h0), uncommonBits_20) node _T_326 = and(_T_324, _T_325) node _T_327 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_328 = and(_T_326, _T_327) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_329 = shr(io.in.a.bits.source, 2) node _T_330 = eq(_T_329, UInt<1>(0h1)) node _T_331 = leq(UInt<1>(0h0), uncommonBits_21) node _T_332 = and(_T_330, _T_331) node _T_333 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_334 = and(_T_332, _T_333) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_335 = shr(io.in.a.bits.source, 2) node _T_336 = eq(_T_335, UInt<2>(0h2)) node _T_337 = leq(UInt<1>(0h0), uncommonBits_22) node _T_338 = and(_T_336, _T_337) node _T_339 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_340 = and(_T_338, _T_339) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_341 = shr(io.in.a.bits.source, 2) node _T_342 = eq(_T_341, UInt<2>(0h3)) node _T_343 = leq(UInt<1>(0h0), uncommonBits_23) node _T_344 = and(_T_342, _T_343) node _T_345 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_346 = and(_T_344, _T_345) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 2, 0) node _T_347 = shr(io.in.a.bits.source, 3) node _T_348 = eq(_T_347, UInt<3>(0h4)) node _T_349 = leq(UInt<1>(0h0), uncommonBits_24) node _T_350 = and(_T_348, _T_349) node _T_351 = leq(uncommonBits_24, UInt<3>(0h4)) node _T_352 = and(_T_350, _T_351) node _T_353 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_354 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_355 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[9] connect _WIRE_2[0], _T_322 connect _WIRE_2[1], _T_328 connect _WIRE_2[2], _T_334 connect _WIRE_2[3], _T_340 connect _WIRE_2[4], _T_346 connect _WIRE_2[5], _T_352 connect _WIRE_2[6], _T_353 connect _WIRE_2[7], _T_354 connect _WIRE_2[8], _T_355 node _T_356 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_357 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_358 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_359 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_360 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_361 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_362 = mux(_WIRE_2[5], _T_356, UInt<1>(0h0)) node _T_363 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_364 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_365 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_366 = or(_T_357, _T_358) node _T_367 = or(_T_366, _T_359) node _T_368 = or(_T_367, _T_360) node _T_369 = or(_T_368, _T_361) node _T_370 = or(_T_369, _T_362) node _T_371 = or(_T_370, _T_363) node _T_372 = or(_T_371, _T_364) node _T_373 = or(_T_372, _T_365) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_373 node _T_374 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_375 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_376 = and(_T_374, _T_375) node _T_377 = or(UInt<1>(0h0), _T_376) node _T_378 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_379 = cvt(_T_378) node _T_380 = and(_T_379, asSInt(UInt<17>(0h10000))) node _T_381 = asSInt(_T_380) node _T_382 = eq(_T_381, asSInt(UInt<1>(0h0))) node _T_383 = and(_T_377, _T_382) node _T_384 = or(UInt<1>(0h0), _T_383) node _T_385 = and(_WIRE_3, _T_384) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_385, UInt<1>(0h1), "") : assert_11 node _T_389 = asUInt(reset) node _T_390 = eq(_T_389, UInt<1>(0h0)) when _T_390 : node _T_391 = eq(source_ok, UInt<1>(0h0)) when _T_391 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_392 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_393 = asUInt(reset) node _T_394 = eq(_T_393, UInt<1>(0h0)) when _T_394 : node _T_395 = eq(_T_392, UInt<1>(0h0)) when _T_395 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_392, UInt<1>(0h1), "") : assert_13 node _T_396 = asUInt(reset) node _T_397 = eq(_T_396, UInt<1>(0h0)) when _T_397 : node _T_398 = eq(is_aligned, UInt<1>(0h0)) when _T_398 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_399 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_400 = asUInt(reset) node _T_401 = eq(_T_400, UInt<1>(0h0)) when _T_401 : node _T_402 = eq(_T_399, UInt<1>(0h0)) when _T_402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_399, UInt<1>(0h1), "") : assert_15 node _T_403 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_404 = asUInt(reset) node _T_405 = eq(_T_404, UInt<1>(0h0)) when _T_405 : node _T_406 = eq(_T_403, UInt<1>(0h0)) when _T_406 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_403, UInt<1>(0h1), "") : assert_16 node _T_407 = not(io.in.a.bits.mask) node _T_408 = eq(_T_407, UInt<1>(0h0)) node _T_409 = asUInt(reset) node _T_410 = eq(_T_409, UInt<1>(0h0)) when _T_410 : node _T_411 = eq(_T_408, UInt<1>(0h0)) when _T_411 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_408, UInt<1>(0h1), "") : assert_17 node _T_412 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_413 = asUInt(reset) node _T_414 = eq(_T_413, UInt<1>(0h0)) when _T_414 : node _T_415 = eq(_T_412, UInt<1>(0h0)) when _T_415 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_412, UInt<1>(0h1), "") : assert_18 node _T_416 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_416 : node _T_417 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_418 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_419 = and(_T_417, _T_418) node _T_420 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_421 = shr(io.in.a.bits.source, 2) node _T_422 = eq(_T_421, UInt<1>(0h0)) node _T_423 = leq(UInt<1>(0h0), uncommonBits_25) node _T_424 = and(_T_422, _T_423) node _T_425 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_426 = and(_T_424, _T_425) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_427 = shr(io.in.a.bits.source, 2) node _T_428 = eq(_T_427, UInt<1>(0h1)) node _T_429 = leq(UInt<1>(0h0), uncommonBits_26) node _T_430 = and(_T_428, _T_429) node _T_431 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_432 = and(_T_430, _T_431) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_433 = shr(io.in.a.bits.source, 2) node _T_434 = eq(_T_433, UInt<2>(0h2)) node _T_435 = leq(UInt<1>(0h0), uncommonBits_27) node _T_436 = and(_T_434, _T_435) node _T_437 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_438 = and(_T_436, _T_437) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_439 = shr(io.in.a.bits.source, 2) node _T_440 = eq(_T_439, UInt<2>(0h3)) node _T_441 = leq(UInt<1>(0h0), uncommonBits_28) node _T_442 = and(_T_440, _T_441) node _T_443 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_444 = and(_T_442, _T_443) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 2, 0) node _T_445 = shr(io.in.a.bits.source, 3) node _T_446 = eq(_T_445, UInt<3>(0h4)) node _T_447 = leq(UInt<1>(0h0), uncommonBits_29) node _T_448 = and(_T_446, _T_447) node _T_449 = leq(uncommonBits_29, UInt<3>(0h4)) node _T_450 = and(_T_448, _T_449) node _T_451 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_452 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_453 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_454 = or(_T_420, _T_426) node _T_455 = or(_T_454, _T_432) node _T_456 = or(_T_455, _T_438) node _T_457 = or(_T_456, _T_444) node _T_458 = or(_T_457, _T_450) node _T_459 = or(_T_458, _T_451) node _T_460 = or(_T_459, _T_452) node _T_461 = or(_T_460, _T_453) node _T_462 = and(_T_419, _T_461) node _T_463 = or(UInt<1>(0h0), _T_462) node _T_464 = asUInt(reset) node _T_465 = eq(_T_464, UInt<1>(0h0)) when _T_465 : node _T_466 = eq(_T_463, UInt<1>(0h0)) when _T_466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_463, UInt<1>(0h1), "") : assert_19 node _T_467 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_468 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_469 = and(_T_467, _T_468) node _T_470 = or(UInt<1>(0h0), _T_469) node _T_471 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_472 = cvt(_T_471) node _T_473 = and(_T_472, asSInt(UInt<17>(0h10000))) node _T_474 = asSInt(_T_473) node _T_475 = eq(_T_474, asSInt(UInt<1>(0h0))) node _T_476 = and(_T_470, _T_475) node _T_477 = or(UInt<1>(0h0), _T_476) node _T_478 = asUInt(reset) node _T_479 = eq(_T_478, UInt<1>(0h0)) when _T_479 : node _T_480 = eq(_T_477, UInt<1>(0h0)) when _T_480 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_477, UInt<1>(0h1), "") : assert_20 node _T_481 = asUInt(reset) node _T_482 = eq(_T_481, UInt<1>(0h0)) when _T_482 : node _T_483 = eq(source_ok, UInt<1>(0h0)) when _T_483 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_484 = asUInt(reset) node _T_485 = eq(_T_484, UInt<1>(0h0)) when _T_485 : node _T_486 = eq(is_aligned, UInt<1>(0h0)) when _T_486 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_487 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_488 = asUInt(reset) node _T_489 = eq(_T_488, UInt<1>(0h0)) when _T_489 : node _T_490 = eq(_T_487, UInt<1>(0h0)) when _T_490 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_487, UInt<1>(0h1), "") : assert_23 node _T_491 = eq(io.in.a.bits.mask, mask) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_491, UInt<1>(0h1), "") : assert_24 node _T_495 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_495, UInt<1>(0h1), "") : assert_25 node _T_499 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_499 : node _T_500 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_501 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_502 = and(_T_500, _T_501) node _T_503 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_504 = shr(io.in.a.bits.source, 2) node _T_505 = eq(_T_504, UInt<1>(0h0)) node _T_506 = leq(UInt<1>(0h0), uncommonBits_30) node _T_507 = and(_T_505, _T_506) node _T_508 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_509 = and(_T_507, _T_508) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_510 = shr(io.in.a.bits.source, 2) node _T_511 = eq(_T_510, UInt<1>(0h1)) node _T_512 = leq(UInt<1>(0h0), uncommonBits_31) node _T_513 = and(_T_511, _T_512) node _T_514 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_515 = and(_T_513, _T_514) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_516 = shr(io.in.a.bits.source, 2) node _T_517 = eq(_T_516, UInt<2>(0h2)) node _T_518 = leq(UInt<1>(0h0), uncommonBits_32) node _T_519 = and(_T_517, _T_518) node _T_520 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_521 = and(_T_519, _T_520) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_522 = shr(io.in.a.bits.source, 2) node _T_523 = eq(_T_522, UInt<2>(0h3)) node _T_524 = leq(UInt<1>(0h0), uncommonBits_33) node _T_525 = and(_T_523, _T_524) node _T_526 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_527 = and(_T_525, _T_526) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 2, 0) node _T_528 = shr(io.in.a.bits.source, 3) node _T_529 = eq(_T_528, UInt<3>(0h4)) node _T_530 = leq(UInt<1>(0h0), uncommonBits_34) node _T_531 = and(_T_529, _T_530) node _T_532 = leq(uncommonBits_34, UInt<3>(0h4)) node _T_533 = and(_T_531, _T_532) node _T_534 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_535 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_536 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_537 = or(_T_503, _T_509) node _T_538 = or(_T_537, _T_515) node _T_539 = or(_T_538, _T_521) node _T_540 = or(_T_539, _T_527) node _T_541 = or(_T_540, _T_533) node _T_542 = or(_T_541, _T_534) node _T_543 = or(_T_542, _T_535) node _T_544 = or(_T_543, _T_536) node _T_545 = and(_T_502, _T_544) node _T_546 = or(UInt<1>(0h0), _T_545) node _T_547 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_548 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_549 = cvt(_T_548) node _T_550 = and(_T_549, asSInt(UInt<17>(0h10000))) node _T_551 = asSInt(_T_550) node _T_552 = eq(_T_551, asSInt(UInt<1>(0h0))) node _T_553 = and(_T_547, _T_552) node _T_554 = or(UInt<1>(0h0), _T_553) node _T_555 = and(_T_546, _T_554) node _T_556 = asUInt(reset) node _T_557 = eq(_T_556, UInt<1>(0h0)) when _T_557 : node _T_558 = eq(_T_555, UInt<1>(0h0)) when _T_558 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_555, UInt<1>(0h1), "") : assert_26 node _T_559 = asUInt(reset) node _T_560 = eq(_T_559, UInt<1>(0h0)) when _T_560 : node _T_561 = eq(source_ok, UInt<1>(0h0)) when _T_561 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_562 = asUInt(reset) node _T_563 = eq(_T_562, UInt<1>(0h0)) when _T_563 : node _T_564 = eq(is_aligned, UInt<1>(0h0)) when _T_564 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_565 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_566 = asUInt(reset) node _T_567 = eq(_T_566, UInt<1>(0h0)) when _T_567 : node _T_568 = eq(_T_565, UInt<1>(0h0)) when _T_568 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_565, UInt<1>(0h1), "") : assert_29 node _T_569 = eq(io.in.a.bits.mask, mask) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_569, UInt<1>(0h1), "") : assert_30 node _T_573 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_573 : node _T_574 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_575 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_576 = and(_T_574, _T_575) node _T_577 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_578 = shr(io.in.a.bits.source, 2) node _T_579 = eq(_T_578, UInt<1>(0h0)) node _T_580 = leq(UInt<1>(0h0), uncommonBits_35) node _T_581 = and(_T_579, _T_580) node _T_582 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_583 = and(_T_581, _T_582) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_584 = shr(io.in.a.bits.source, 2) node _T_585 = eq(_T_584, UInt<1>(0h1)) node _T_586 = leq(UInt<1>(0h0), uncommonBits_36) node _T_587 = and(_T_585, _T_586) node _T_588 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_589 = and(_T_587, _T_588) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_590 = shr(io.in.a.bits.source, 2) node _T_591 = eq(_T_590, UInt<2>(0h2)) node _T_592 = leq(UInt<1>(0h0), uncommonBits_37) node _T_593 = and(_T_591, _T_592) node _T_594 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_595 = and(_T_593, _T_594) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_596 = shr(io.in.a.bits.source, 2) node _T_597 = eq(_T_596, UInt<2>(0h3)) node _T_598 = leq(UInt<1>(0h0), uncommonBits_38) node _T_599 = and(_T_597, _T_598) node _T_600 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_601 = and(_T_599, _T_600) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 2, 0) node _T_602 = shr(io.in.a.bits.source, 3) node _T_603 = eq(_T_602, UInt<3>(0h4)) node _T_604 = leq(UInt<1>(0h0), uncommonBits_39) node _T_605 = and(_T_603, _T_604) node _T_606 = leq(uncommonBits_39, UInt<3>(0h4)) node _T_607 = and(_T_605, _T_606) node _T_608 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_609 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_610 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_611 = or(_T_577, _T_583) node _T_612 = or(_T_611, _T_589) node _T_613 = or(_T_612, _T_595) node _T_614 = or(_T_613, _T_601) node _T_615 = or(_T_614, _T_607) node _T_616 = or(_T_615, _T_608) node _T_617 = or(_T_616, _T_609) node _T_618 = or(_T_617, _T_610) node _T_619 = and(_T_576, _T_618) node _T_620 = or(UInt<1>(0h0), _T_619) node _T_621 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_622 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_623 = cvt(_T_622) node _T_624 = and(_T_623, asSInt(UInt<17>(0h10000))) node _T_625 = asSInt(_T_624) node _T_626 = eq(_T_625, asSInt(UInt<1>(0h0))) node _T_627 = and(_T_621, _T_626) node _T_628 = or(UInt<1>(0h0), _T_627) node _T_629 = and(_T_620, _T_628) node _T_630 = asUInt(reset) node _T_631 = eq(_T_630, UInt<1>(0h0)) when _T_631 : node _T_632 = eq(_T_629, UInt<1>(0h0)) when _T_632 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_629, UInt<1>(0h1), "") : assert_31 node _T_633 = asUInt(reset) node _T_634 = eq(_T_633, UInt<1>(0h0)) when _T_634 : node _T_635 = eq(source_ok, UInt<1>(0h0)) when _T_635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_636 = asUInt(reset) node _T_637 = eq(_T_636, UInt<1>(0h0)) when _T_637 : node _T_638 = eq(is_aligned, UInt<1>(0h0)) when _T_638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_639 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_640 = asUInt(reset) node _T_641 = eq(_T_640, UInt<1>(0h0)) when _T_641 : node _T_642 = eq(_T_639, UInt<1>(0h0)) when _T_642 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_639, UInt<1>(0h1), "") : assert_34 node _T_643 = not(mask) node _T_644 = and(io.in.a.bits.mask, _T_643) node _T_645 = eq(_T_644, UInt<1>(0h0)) node _T_646 = asUInt(reset) node _T_647 = eq(_T_646, UInt<1>(0h0)) when _T_647 : node _T_648 = eq(_T_645, UInt<1>(0h0)) when _T_648 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_645, UInt<1>(0h1), "") : assert_35 node _T_649 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_649 : node _T_650 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_651 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_652 = and(_T_650, _T_651) node _T_653 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_654 = shr(io.in.a.bits.source, 2) node _T_655 = eq(_T_654, UInt<1>(0h0)) node _T_656 = leq(UInt<1>(0h0), uncommonBits_40) node _T_657 = and(_T_655, _T_656) node _T_658 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_659 = and(_T_657, _T_658) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_660 = shr(io.in.a.bits.source, 2) node _T_661 = eq(_T_660, UInt<1>(0h1)) node _T_662 = leq(UInt<1>(0h0), uncommonBits_41) node _T_663 = and(_T_661, _T_662) node _T_664 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_665 = and(_T_663, _T_664) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_666 = shr(io.in.a.bits.source, 2) node _T_667 = eq(_T_666, UInt<2>(0h2)) node _T_668 = leq(UInt<1>(0h0), uncommonBits_42) node _T_669 = and(_T_667, _T_668) node _T_670 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_671 = and(_T_669, _T_670) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_672 = shr(io.in.a.bits.source, 2) node _T_673 = eq(_T_672, UInt<2>(0h3)) node _T_674 = leq(UInt<1>(0h0), uncommonBits_43) node _T_675 = and(_T_673, _T_674) node _T_676 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_677 = and(_T_675, _T_676) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 2, 0) node _T_678 = shr(io.in.a.bits.source, 3) node _T_679 = eq(_T_678, UInt<3>(0h4)) node _T_680 = leq(UInt<1>(0h0), uncommonBits_44) node _T_681 = and(_T_679, _T_680) node _T_682 = leq(uncommonBits_44, UInt<3>(0h4)) node _T_683 = and(_T_681, _T_682) node _T_684 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_685 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_686 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_687 = or(_T_653, _T_659) node _T_688 = or(_T_687, _T_665) node _T_689 = or(_T_688, _T_671) node _T_690 = or(_T_689, _T_677) node _T_691 = or(_T_690, _T_683) node _T_692 = or(_T_691, _T_684) node _T_693 = or(_T_692, _T_685) node _T_694 = or(_T_693, _T_686) node _T_695 = and(_T_652, _T_694) node _T_696 = or(UInt<1>(0h0), _T_695) node _T_697 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_698 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_699 = cvt(_T_698) node _T_700 = and(_T_699, asSInt(UInt<17>(0h10000))) node _T_701 = asSInt(_T_700) node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0))) node _T_703 = and(_T_697, _T_702) node _T_704 = or(UInt<1>(0h0), _T_703) node _T_705 = and(_T_696, _T_704) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_705, UInt<1>(0h1), "") : assert_36 node _T_709 = asUInt(reset) node _T_710 = eq(_T_709, UInt<1>(0h0)) when _T_710 : node _T_711 = eq(source_ok, UInt<1>(0h0)) when _T_711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_712 = asUInt(reset) node _T_713 = eq(_T_712, UInt<1>(0h0)) when _T_713 : node _T_714 = eq(is_aligned, UInt<1>(0h0)) when _T_714 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_715 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_716 = asUInt(reset) node _T_717 = eq(_T_716, UInt<1>(0h0)) when _T_717 : node _T_718 = eq(_T_715, UInt<1>(0h0)) when _T_718 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_715, UInt<1>(0h1), "") : assert_39 node _T_719 = eq(io.in.a.bits.mask, mask) node _T_720 = asUInt(reset) node _T_721 = eq(_T_720, UInt<1>(0h0)) when _T_721 : node _T_722 = eq(_T_719, UInt<1>(0h0)) when _T_722 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_719, UInt<1>(0h1), "") : assert_40 node _T_723 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_723 : node _T_724 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_725 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_726 = and(_T_724, _T_725) node _T_727 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_728 = shr(io.in.a.bits.source, 2) node _T_729 = eq(_T_728, UInt<1>(0h0)) node _T_730 = leq(UInt<1>(0h0), uncommonBits_45) node _T_731 = and(_T_729, _T_730) node _T_732 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_733 = and(_T_731, _T_732) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0) node _T_734 = shr(io.in.a.bits.source, 2) node _T_735 = eq(_T_734, UInt<1>(0h1)) node _T_736 = leq(UInt<1>(0h0), uncommonBits_46) node _T_737 = and(_T_735, _T_736) node _T_738 = leq(uncommonBits_46, UInt<2>(0h3)) node _T_739 = and(_T_737, _T_738) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0) node _T_740 = shr(io.in.a.bits.source, 2) node _T_741 = eq(_T_740, UInt<2>(0h2)) node _T_742 = leq(UInt<1>(0h0), uncommonBits_47) node _T_743 = and(_T_741, _T_742) node _T_744 = leq(uncommonBits_47, UInt<2>(0h3)) node _T_745 = and(_T_743, _T_744) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_746 = shr(io.in.a.bits.source, 2) node _T_747 = eq(_T_746, UInt<2>(0h3)) node _T_748 = leq(UInt<1>(0h0), uncommonBits_48) node _T_749 = and(_T_747, _T_748) node _T_750 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_751 = and(_T_749, _T_750) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 2, 0) node _T_752 = shr(io.in.a.bits.source, 3) node _T_753 = eq(_T_752, UInt<3>(0h4)) node _T_754 = leq(UInt<1>(0h0), uncommonBits_49) node _T_755 = and(_T_753, _T_754) node _T_756 = leq(uncommonBits_49, UInt<3>(0h4)) node _T_757 = and(_T_755, _T_756) node _T_758 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_759 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_760 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_761 = or(_T_727, _T_733) node _T_762 = or(_T_761, _T_739) node _T_763 = or(_T_762, _T_745) node _T_764 = or(_T_763, _T_751) node _T_765 = or(_T_764, _T_757) node _T_766 = or(_T_765, _T_758) node _T_767 = or(_T_766, _T_759) node _T_768 = or(_T_767, _T_760) node _T_769 = and(_T_726, _T_768) node _T_770 = or(UInt<1>(0h0), _T_769) node _T_771 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_772 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_773 = cvt(_T_772) node _T_774 = and(_T_773, asSInt(UInt<17>(0h10000))) node _T_775 = asSInt(_T_774) node _T_776 = eq(_T_775, asSInt(UInt<1>(0h0))) node _T_777 = and(_T_771, _T_776) node _T_778 = or(UInt<1>(0h0), _T_777) node _T_779 = and(_T_770, _T_778) node _T_780 = asUInt(reset) node _T_781 = eq(_T_780, UInt<1>(0h0)) when _T_781 : node _T_782 = eq(_T_779, UInt<1>(0h0)) when _T_782 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_779, UInt<1>(0h1), "") : assert_41 node _T_783 = asUInt(reset) node _T_784 = eq(_T_783, UInt<1>(0h0)) when _T_784 : node _T_785 = eq(source_ok, UInt<1>(0h0)) when _T_785 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_786 = asUInt(reset) node _T_787 = eq(_T_786, UInt<1>(0h0)) when _T_787 : node _T_788 = eq(is_aligned, UInt<1>(0h0)) when _T_788 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_789 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_790 = asUInt(reset) node _T_791 = eq(_T_790, UInt<1>(0h0)) when _T_791 : node _T_792 = eq(_T_789, UInt<1>(0h0)) when _T_792 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_789, UInt<1>(0h1), "") : assert_44 node _T_793 = eq(io.in.a.bits.mask, mask) node _T_794 = asUInt(reset) node _T_795 = eq(_T_794, UInt<1>(0h0)) when _T_795 : node _T_796 = eq(_T_793, UInt<1>(0h0)) when _T_796 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_793, UInt<1>(0h1), "") : assert_45 node _T_797 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_797 : node _T_798 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_799 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_800 = and(_T_798, _T_799) node _T_801 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_802 = shr(io.in.a.bits.source, 2) node _T_803 = eq(_T_802, UInt<1>(0h0)) node _T_804 = leq(UInt<1>(0h0), uncommonBits_50) node _T_805 = and(_T_803, _T_804) node _T_806 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_807 = and(_T_805, _T_806) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_808 = shr(io.in.a.bits.source, 2) node _T_809 = eq(_T_808, UInt<1>(0h1)) node _T_810 = leq(UInt<1>(0h0), uncommonBits_51) node _T_811 = and(_T_809, _T_810) node _T_812 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_813 = and(_T_811, _T_812) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0) node _T_814 = shr(io.in.a.bits.source, 2) node _T_815 = eq(_T_814, UInt<2>(0h2)) node _T_816 = leq(UInt<1>(0h0), uncommonBits_52) node _T_817 = and(_T_815, _T_816) node _T_818 = leq(uncommonBits_52, UInt<2>(0h3)) node _T_819 = and(_T_817, _T_818) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 1, 0) node _T_820 = shr(io.in.a.bits.source, 2) node _T_821 = eq(_T_820, UInt<2>(0h3)) node _T_822 = leq(UInt<1>(0h0), uncommonBits_53) node _T_823 = and(_T_821, _T_822) node _T_824 = leq(uncommonBits_53, UInt<2>(0h3)) node _T_825 = and(_T_823, _T_824) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 2, 0) node _T_826 = shr(io.in.a.bits.source, 3) node _T_827 = eq(_T_826, UInt<3>(0h4)) node _T_828 = leq(UInt<1>(0h0), uncommonBits_54) node _T_829 = and(_T_827, _T_828) node _T_830 = leq(uncommonBits_54, UInt<3>(0h4)) node _T_831 = and(_T_829, _T_830) node _T_832 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_833 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_834 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_835 = or(_T_801, _T_807) node _T_836 = or(_T_835, _T_813) node _T_837 = or(_T_836, _T_819) node _T_838 = or(_T_837, _T_825) node _T_839 = or(_T_838, _T_831) node _T_840 = or(_T_839, _T_832) node _T_841 = or(_T_840, _T_833) node _T_842 = or(_T_841, _T_834) node _T_843 = and(_T_800, _T_842) node _T_844 = or(UInt<1>(0h0), _T_843) node _T_845 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_846 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_847 = cvt(_T_846) node _T_848 = and(_T_847, asSInt(UInt<17>(0h10000))) node _T_849 = asSInt(_T_848) node _T_850 = eq(_T_849, asSInt(UInt<1>(0h0))) node _T_851 = and(_T_845, _T_850) node _T_852 = or(UInt<1>(0h0), _T_851) node _T_853 = and(_T_844, _T_852) node _T_854 = asUInt(reset) node _T_855 = eq(_T_854, UInt<1>(0h0)) when _T_855 : node _T_856 = eq(_T_853, UInt<1>(0h0)) when _T_856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_853, UInt<1>(0h1), "") : assert_46 node _T_857 = asUInt(reset) node _T_858 = eq(_T_857, UInt<1>(0h0)) when _T_858 : node _T_859 = eq(source_ok, UInt<1>(0h0)) when _T_859 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_860 = asUInt(reset) node _T_861 = eq(_T_860, UInt<1>(0h0)) when _T_861 : node _T_862 = eq(is_aligned, UInt<1>(0h0)) when _T_862 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_863 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_864 = asUInt(reset) node _T_865 = eq(_T_864, UInt<1>(0h0)) when _T_865 : node _T_866 = eq(_T_863, UInt<1>(0h0)) when _T_866 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_863, UInt<1>(0h1), "") : assert_49 node _T_867 = eq(io.in.a.bits.mask, mask) node _T_868 = asUInt(reset) node _T_869 = eq(_T_868, UInt<1>(0h0)) when _T_869 : node _T_870 = eq(_T_867, UInt<1>(0h0)) when _T_870 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_867, UInt<1>(0h1), "") : assert_50 node _T_871 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_872 = asUInt(reset) node _T_873 = eq(_T_872, UInt<1>(0h0)) when _T_873 : node _T_874 = eq(_T_871, UInt<1>(0h0)) when _T_874 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_871, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_875 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_876 = asUInt(reset) node _T_877 = eq(_T_876, UInt<1>(0h0)) when _T_877 : node _T_878 = eq(_T_875, UInt<1>(0h0)) when _T_878 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_875, UInt<1>(0h1), "") : assert_52 node _source_ok_T_41 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_42 = shr(io.in.d.bits.source, 2) node _source_ok_T_43 = eq(_source_ok_T_42, UInt<1>(0h0)) node _source_ok_T_44 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_45 = and(_source_ok_T_43, _source_ok_T_44) node _source_ok_T_46 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_47 = and(_source_ok_T_45, _source_ok_T_46) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_48 = shr(io.in.d.bits.source, 2) node _source_ok_T_49 = eq(_source_ok_T_48, UInt<1>(0h1)) node _source_ok_T_50 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_51 = and(_source_ok_T_49, _source_ok_T_50) node _source_ok_T_52 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_53 = and(_source_ok_T_51, _source_ok_T_52) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_54 = shr(io.in.d.bits.source, 2) node _source_ok_T_55 = eq(_source_ok_T_54, UInt<2>(0h2)) node _source_ok_T_56 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_57 = and(_source_ok_T_55, _source_ok_T_56) node _source_ok_T_58 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_59 = and(_source_ok_T_57, _source_ok_T_58) node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_60 = shr(io.in.d.bits.source, 2) node _source_ok_T_61 = eq(_source_ok_T_60, UInt<2>(0h3)) node _source_ok_T_62 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_63 = and(_source_ok_T_61, _source_ok_T_62) node _source_ok_T_64 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_65 = and(_source_ok_T_63, _source_ok_T_64) node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 2, 0) node _source_ok_T_66 = shr(io.in.d.bits.source, 3) node _source_ok_T_67 = eq(_source_ok_T_66, UInt<3>(0h4)) node _source_ok_T_68 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_69 = and(_source_ok_T_67, _source_ok_T_68) node _source_ok_T_70 = leq(source_ok_uncommonBits_9, UInt<3>(0h4)) node _source_ok_T_71 = and(_source_ok_T_69, _source_ok_T_70) node _source_ok_T_72 = eq(io.in.d.bits.source, UInt<6>(0h25)) node _source_ok_T_73 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_74 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[9] connect _source_ok_WIRE_1[0], _source_ok_T_41 connect _source_ok_WIRE_1[1], _source_ok_T_47 connect _source_ok_WIRE_1[2], _source_ok_T_53 connect _source_ok_WIRE_1[3], _source_ok_T_59 connect _source_ok_WIRE_1[4], _source_ok_T_65 connect _source_ok_WIRE_1[5], _source_ok_T_71 connect _source_ok_WIRE_1[6], _source_ok_T_72 connect _source_ok_WIRE_1[7], _source_ok_T_73 connect _source_ok_WIRE_1[8], _source_ok_T_74 node _source_ok_T_75 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE_1[2]) node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE_1[3]) node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE_1[4]) node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE_1[5]) node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE_1[6]) node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE_1[7]) node source_ok_1 = or(_source_ok_T_81, _source_ok_WIRE_1[8]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_879 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_879 : node _T_880 = asUInt(reset) node _T_881 = eq(_T_880, UInt<1>(0h0)) when _T_881 : node _T_882 = eq(source_ok_1, UInt<1>(0h0)) when _T_882 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_883 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_884 = asUInt(reset) node _T_885 = eq(_T_884, UInt<1>(0h0)) when _T_885 : node _T_886 = eq(_T_883, UInt<1>(0h0)) when _T_886 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_883, UInt<1>(0h1), "") : assert_54 node _T_887 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_888 = asUInt(reset) node _T_889 = eq(_T_888, UInt<1>(0h0)) when _T_889 : node _T_890 = eq(_T_887, UInt<1>(0h0)) when _T_890 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_887, UInt<1>(0h1), "") : assert_55 node _T_891 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_892 = asUInt(reset) node _T_893 = eq(_T_892, UInt<1>(0h0)) when _T_893 : node _T_894 = eq(_T_891, UInt<1>(0h0)) when _T_894 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_891, UInt<1>(0h1), "") : assert_56 node _T_895 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_896 = asUInt(reset) node _T_897 = eq(_T_896, UInt<1>(0h0)) when _T_897 : node _T_898 = eq(_T_895, UInt<1>(0h0)) when _T_898 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_895, UInt<1>(0h1), "") : assert_57 node _T_899 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_899 : node _T_900 = asUInt(reset) node _T_901 = eq(_T_900, UInt<1>(0h0)) when _T_901 : node _T_902 = eq(source_ok_1, UInt<1>(0h0)) when _T_902 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_903 = asUInt(reset) node _T_904 = eq(_T_903, UInt<1>(0h0)) when _T_904 : node _T_905 = eq(sink_ok, UInt<1>(0h0)) when _T_905 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_906 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_907 = asUInt(reset) node _T_908 = eq(_T_907, UInt<1>(0h0)) when _T_908 : node _T_909 = eq(_T_906, UInt<1>(0h0)) when _T_909 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_906, UInt<1>(0h1), "") : assert_60 node _T_910 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_911 = asUInt(reset) node _T_912 = eq(_T_911, UInt<1>(0h0)) when _T_912 : node _T_913 = eq(_T_910, UInt<1>(0h0)) when _T_913 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_910, UInt<1>(0h1), "") : assert_61 node _T_914 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_915 = asUInt(reset) node _T_916 = eq(_T_915, UInt<1>(0h0)) when _T_916 : node _T_917 = eq(_T_914, UInt<1>(0h0)) when _T_917 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_914, UInt<1>(0h1), "") : assert_62 node _T_918 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_919 = asUInt(reset) node _T_920 = eq(_T_919, UInt<1>(0h0)) when _T_920 : node _T_921 = eq(_T_918, UInt<1>(0h0)) when _T_921 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_918, UInt<1>(0h1), "") : assert_63 node _T_922 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_923 = or(UInt<1>(0h0), _T_922) node _T_924 = asUInt(reset) node _T_925 = eq(_T_924, UInt<1>(0h0)) when _T_925 : node _T_926 = eq(_T_923, UInt<1>(0h0)) when _T_926 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_923, UInt<1>(0h1), "") : assert_64 node _T_927 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_927 : node _T_928 = asUInt(reset) node _T_929 = eq(_T_928, UInt<1>(0h0)) when _T_929 : node _T_930 = eq(source_ok_1, UInt<1>(0h0)) when _T_930 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_931 = asUInt(reset) node _T_932 = eq(_T_931, UInt<1>(0h0)) when _T_932 : node _T_933 = eq(sink_ok, UInt<1>(0h0)) when _T_933 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_934 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_935 = asUInt(reset) node _T_936 = eq(_T_935, UInt<1>(0h0)) when _T_936 : node _T_937 = eq(_T_934, UInt<1>(0h0)) when _T_937 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_934, UInt<1>(0h1), "") : assert_67 node _T_938 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_939 = asUInt(reset) node _T_940 = eq(_T_939, UInt<1>(0h0)) when _T_940 : node _T_941 = eq(_T_938, UInt<1>(0h0)) when _T_941 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_938, UInt<1>(0h1), "") : assert_68 node _T_942 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_943 = asUInt(reset) node _T_944 = eq(_T_943, UInt<1>(0h0)) when _T_944 : node _T_945 = eq(_T_942, UInt<1>(0h0)) when _T_945 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_942, UInt<1>(0h1), "") : assert_69 node _T_946 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_947 = or(_T_946, io.in.d.bits.corrupt) node _T_948 = asUInt(reset) node _T_949 = eq(_T_948, UInt<1>(0h0)) when _T_949 : node _T_950 = eq(_T_947, UInt<1>(0h0)) when _T_950 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_947, UInt<1>(0h1), "") : assert_70 node _T_951 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_952 = or(UInt<1>(0h0), _T_951) node _T_953 = asUInt(reset) node _T_954 = eq(_T_953, UInt<1>(0h0)) when _T_954 : node _T_955 = eq(_T_952, UInt<1>(0h0)) when _T_955 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_952, UInt<1>(0h1), "") : assert_71 node _T_956 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_956 : node _T_957 = asUInt(reset) node _T_958 = eq(_T_957, UInt<1>(0h0)) when _T_958 : node _T_959 = eq(source_ok_1, UInt<1>(0h0)) when _T_959 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_960 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_961 = asUInt(reset) node _T_962 = eq(_T_961, UInt<1>(0h0)) when _T_962 : node _T_963 = eq(_T_960, UInt<1>(0h0)) when _T_963 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_960, UInt<1>(0h1), "") : assert_73 node _T_964 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_965 = asUInt(reset) node _T_966 = eq(_T_965, UInt<1>(0h0)) when _T_966 : node _T_967 = eq(_T_964, UInt<1>(0h0)) when _T_967 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_964, UInt<1>(0h1), "") : assert_74 node _T_968 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_969 = or(UInt<1>(0h0), _T_968) node _T_970 = asUInt(reset) node _T_971 = eq(_T_970, UInt<1>(0h0)) when _T_971 : node _T_972 = eq(_T_969, UInt<1>(0h0)) when _T_972 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_969, UInt<1>(0h1), "") : assert_75 node _T_973 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_973 : node _T_974 = asUInt(reset) node _T_975 = eq(_T_974, UInt<1>(0h0)) when _T_975 : node _T_976 = eq(source_ok_1, UInt<1>(0h0)) when _T_976 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_977 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_978 = asUInt(reset) node _T_979 = eq(_T_978, UInt<1>(0h0)) when _T_979 : node _T_980 = eq(_T_977, UInt<1>(0h0)) when _T_980 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_977, UInt<1>(0h1), "") : assert_77 node _T_981 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_982 = or(_T_981, io.in.d.bits.corrupt) node _T_983 = asUInt(reset) node _T_984 = eq(_T_983, UInt<1>(0h0)) when _T_984 : node _T_985 = eq(_T_982, UInt<1>(0h0)) when _T_985 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_982, UInt<1>(0h1), "") : assert_78 node _T_986 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_987 = or(UInt<1>(0h0), _T_986) node _T_988 = asUInt(reset) node _T_989 = eq(_T_988, UInt<1>(0h0)) when _T_989 : node _T_990 = eq(_T_987, UInt<1>(0h0)) when _T_990 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_987, UInt<1>(0h1), "") : assert_79 node _T_991 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_991 : node _T_992 = asUInt(reset) node _T_993 = eq(_T_992, UInt<1>(0h0)) when _T_993 : node _T_994 = eq(source_ok_1, UInt<1>(0h0)) when _T_994 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_995 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_996 = asUInt(reset) node _T_997 = eq(_T_996, UInt<1>(0h0)) when _T_997 : node _T_998 = eq(_T_995, UInt<1>(0h0)) when _T_998 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_995, UInt<1>(0h1), "") : assert_81 node _T_999 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1000 = asUInt(reset) node _T_1001 = eq(_T_1000, UInt<1>(0h0)) when _T_1001 : node _T_1002 = eq(_T_999, UInt<1>(0h0)) when _T_1002 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_999, UInt<1>(0h1), "") : assert_82 node _T_1003 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1004 = or(UInt<1>(0h0), _T_1003) node _T_1005 = asUInt(reset) node _T_1006 = eq(_T_1005, UInt<1>(0h0)) when _T_1006 : node _T_1007 = eq(_T_1004, UInt<1>(0h0)) when _T_1007 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1004, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<17>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1008 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1009 = asUInt(reset) node _T_1010 = eq(_T_1009, UInt<1>(0h0)) when _T_1010 : node _T_1011 = eq(_T_1008, UInt<1>(0h0)) when _T_1011 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1008, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<17>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1012 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1013 = asUInt(reset) node _T_1014 = eq(_T_1013, UInt<1>(0h0)) when _T_1014 : node _T_1015 = eq(_T_1012, UInt<1>(0h0)) when _T_1015 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1012, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1016 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1017 = asUInt(reset) node _T_1018 = eq(_T_1017, UInt<1>(0h0)) when _T_1018 : node _T_1019 = eq(_T_1016, UInt<1>(0h0)) when _T_1019 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1016, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(UInt<1>(0h0), a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1020 = eq(a_first, UInt<1>(0h0)) node _T_1021 = and(io.in.a.valid, _T_1020) when _T_1021 : node _T_1022 = eq(io.in.a.bits.opcode, opcode) node _T_1023 = asUInt(reset) node _T_1024 = eq(_T_1023, UInt<1>(0h0)) when _T_1024 : node _T_1025 = eq(_T_1022, UInt<1>(0h0)) when _T_1025 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1022, UInt<1>(0h1), "") : assert_87 node _T_1026 = eq(io.in.a.bits.param, param) node _T_1027 = asUInt(reset) node _T_1028 = eq(_T_1027, UInt<1>(0h0)) when _T_1028 : node _T_1029 = eq(_T_1026, UInt<1>(0h0)) when _T_1029 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1026, UInt<1>(0h1), "") : assert_88 node _T_1030 = eq(io.in.a.bits.size, size) node _T_1031 = asUInt(reset) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) when _T_1032 : node _T_1033 = eq(_T_1030, UInt<1>(0h0)) when _T_1033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1030, UInt<1>(0h1), "") : assert_89 node _T_1034 = eq(io.in.a.bits.source, source) node _T_1035 = asUInt(reset) node _T_1036 = eq(_T_1035, UInt<1>(0h0)) when _T_1036 : node _T_1037 = eq(_T_1034, UInt<1>(0h0)) when _T_1037 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1034, UInt<1>(0h1), "") : assert_90 node _T_1038 = eq(io.in.a.bits.address, address) node _T_1039 = asUInt(reset) node _T_1040 = eq(_T_1039, UInt<1>(0h0)) when _T_1040 : node _T_1041 = eq(_T_1038, UInt<1>(0h0)) when _T_1041 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1038, UInt<1>(0h1), "") : assert_91 node _T_1042 = and(io.in.a.ready, io.in.a.valid) node _T_1043 = and(_T_1042, a_first) when _T_1043 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(UInt<1>(0h1), d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1044 = eq(d_first, UInt<1>(0h0)) node _T_1045 = and(io.in.d.valid, _T_1044) when _T_1045 : node _T_1046 = eq(io.in.d.bits.opcode, opcode_1) node _T_1047 = asUInt(reset) node _T_1048 = eq(_T_1047, UInt<1>(0h0)) when _T_1048 : node _T_1049 = eq(_T_1046, UInt<1>(0h0)) when _T_1049 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1046, UInt<1>(0h1), "") : assert_92 node _T_1050 = eq(io.in.d.bits.param, param_1) node _T_1051 = asUInt(reset) node _T_1052 = eq(_T_1051, UInt<1>(0h0)) when _T_1052 : node _T_1053 = eq(_T_1050, UInt<1>(0h0)) when _T_1053 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1050, UInt<1>(0h1), "") : assert_93 node _T_1054 = eq(io.in.d.bits.size, size_1) node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(_T_1054, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1054, UInt<1>(0h1), "") : assert_94 node _T_1058 = eq(io.in.d.bits.source, source_1) node _T_1059 = asUInt(reset) node _T_1060 = eq(_T_1059, UInt<1>(0h0)) when _T_1060 : node _T_1061 = eq(_T_1058, UInt<1>(0h0)) when _T_1061 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1058, UInt<1>(0h1), "") : assert_95 node _T_1062 = eq(io.in.d.bits.sink, sink) node _T_1063 = asUInt(reset) node _T_1064 = eq(_T_1063, UInt<1>(0h0)) when _T_1064 : node _T_1065 = eq(_T_1062, UInt<1>(0h0)) when _T_1065 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1062, UInt<1>(0h1), "") : assert_96 node _T_1066 = eq(io.in.d.bits.denied, denied) node _T_1067 = asUInt(reset) node _T_1068 = eq(_T_1067, UInt<1>(0h0)) when _T_1068 : node _T_1069 = eq(_T_1066, UInt<1>(0h0)) when _T_1069 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1066, UInt<1>(0h1), "") : assert_97 node _T_1070 = and(io.in.d.ready, io.in.d.valid) node _T_1071 = and(_T_1070, d_first) when _T_1071 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(UInt<1>(0h0), a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(UInt<1>(0h1), d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<260> connect a_sizes_set, UInt<260>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1072 = and(io.in.a.valid, a_first_1) node _T_1073 = and(_T_1072, UInt<1>(0h1)) when _T_1073 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1074 = and(io.in.a.ready, io.in.a.valid) node _T_1075 = and(_T_1074, a_first_1) node _T_1076 = and(_T_1075, UInt<1>(0h1)) when _T_1076 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1077 = dshr(inflight, io.in.a.bits.source) node _T_1078 = bits(_T_1077, 0, 0) node _T_1079 = eq(_T_1078, UInt<1>(0h0)) node _T_1080 = asUInt(reset) node _T_1081 = eq(_T_1080, UInt<1>(0h0)) when _T_1081 : node _T_1082 = eq(_T_1079, UInt<1>(0h0)) when _T_1082 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1079, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<260> connect d_sizes_clr, UInt<260>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1083 = and(io.in.d.valid, d_first_1) node _T_1084 = and(_T_1083, UInt<1>(0h1)) node _T_1085 = eq(d_release_ack, UInt<1>(0h0)) node _T_1086 = and(_T_1084, _T_1085) when _T_1086 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1087 = and(io.in.d.ready, io.in.d.valid) node _T_1088 = and(_T_1087, d_first_1) node _T_1089 = and(_T_1088, UInt<1>(0h1)) node _T_1090 = eq(d_release_ack, UInt<1>(0h0)) node _T_1091 = and(_T_1089, _T_1090) when _T_1091 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1092 = and(io.in.d.valid, d_first_1) node _T_1093 = and(_T_1092, UInt<1>(0h1)) node _T_1094 = eq(d_release_ack, UInt<1>(0h0)) node _T_1095 = and(_T_1093, _T_1094) when _T_1095 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1096 = dshr(inflight, io.in.d.bits.source) node _T_1097 = bits(_T_1096, 0, 0) node _T_1098 = or(_T_1097, same_cycle_resp) node _T_1099 = asUInt(reset) node _T_1100 = eq(_T_1099, UInt<1>(0h0)) when _T_1100 : node _T_1101 = eq(_T_1098, UInt<1>(0h0)) when _T_1101 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1098, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1102 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1103 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1104 = or(_T_1102, _T_1103) node _T_1105 = asUInt(reset) node _T_1106 = eq(_T_1105, UInt<1>(0h0)) when _T_1106 : node _T_1107 = eq(_T_1104, UInt<1>(0h0)) when _T_1107 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1104, UInt<1>(0h1), "") : assert_100 node _T_1108 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1109 = asUInt(reset) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) when _T_1110 : node _T_1111 = eq(_T_1108, UInt<1>(0h0)) when _T_1111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1108, UInt<1>(0h1), "") : assert_101 else : node _T_1112 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1113 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1114 = or(_T_1112, _T_1113) node _T_1115 = asUInt(reset) node _T_1116 = eq(_T_1115, UInt<1>(0h0)) when _T_1116 : node _T_1117 = eq(_T_1114, UInt<1>(0h0)) when _T_1117 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1114, UInt<1>(0h1), "") : assert_102 node _T_1118 = eq(io.in.d.bits.size, a_size_lookup) node _T_1119 = asUInt(reset) node _T_1120 = eq(_T_1119, UInt<1>(0h0)) when _T_1120 : node _T_1121 = eq(_T_1118, UInt<1>(0h0)) when _T_1121 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1118, UInt<1>(0h1), "") : assert_103 node _T_1122 = and(io.in.d.valid, d_first_1) node _T_1123 = and(_T_1122, a_first_1) node _T_1124 = and(_T_1123, io.in.a.valid) node _T_1125 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1126 = and(_T_1124, _T_1125) node _T_1127 = eq(d_release_ack, UInt<1>(0h0)) node _T_1128 = and(_T_1126, _T_1127) when _T_1128 : node _T_1129 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1130 = or(_T_1129, io.in.a.ready) node _T_1131 = asUInt(reset) node _T_1132 = eq(_T_1131, UInt<1>(0h0)) when _T_1132 : node _T_1133 = eq(_T_1130, UInt<1>(0h0)) when _T_1133 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1130, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_56 node _T_1134 = orr(inflight) node _T_1135 = eq(_T_1134, UInt<1>(0h0)) node _T_1136 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1137 = or(_T_1135, _T_1136) node _T_1138 = lt(watchdog, plusarg_reader.out) node _T_1139 = or(_T_1137, _T_1138) node _T_1140 = asUInt(reset) node _T_1141 = eq(_T_1140, UInt<1>(0h0)) when _T_1141 : node _T_1142 = eq(_T_1139, UInt<1>(0h0)) when _T_1142 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1139, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1143 = and(io.in.a.ready, io.in.a.valid) node _T_1144 = and(io.in.d.ready, io.in.d.valid) node _T_1145 = or(_T_1143, _T_1144) when _T_1145 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<17>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<17>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(UInt<1>(0h1), d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<260> connect c_sizes_set, UInt<260>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<17>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1146 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<17>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1147 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1148 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1149 = and(_T_1147, _T_1148) node _T_1150 = and(_T_1146, _T_1149) when _T_1150 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<17>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<17>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1151 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1152 = and(_T_1151, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<17>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1153 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1154 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1155 = and(_T_1153, _T_1154) node _T_1156 = and(_T_1152, _T_1155) when _T_1156 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<17>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<17>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<17>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<17>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<17>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<17>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1157 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1158 = bits(_T_1157, 0, 0) node _T_1159 = eq(_T_1158, UInt<1>(0h0)) node _T_1160 = asUInt(reset) node _T_1161 = eq(_T_1160, UInt<1>(0h0)) when _T_1161 : node _T_1162 = eq(_T_1159, UInt<1>(0h0)) when _T_1162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1159, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<17>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<17>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<260> connect d_sizes_clr_1, UInt<260>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1163 = and(io.in.d.valid, d_first_2) node _T_1164 = and(_T_1163, UInt<1>(0h1)) node _T_1165 = and(_T_1164, d_release_ack_1) when _T_1165 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1166 = and(io.in.d.ready, io.in.d.valid) node _T_1167 = and(_T_1166, d_first_2) node _T_1168 = and(_T_1167, UInt<1>(0h1)) node _T_1169 = and(_T_1168, d_release_ack_1) when _T_1169 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1170 = and(io.in.d.valid, d_first_2) node _T_1171 = and(_T_1170, UInt<1>(0h1)) node _T_1172 = and(_T_1171, d_release_ack_1) when _T_1172 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<17>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<17>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<17>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1173 = dshr(inflight_1, io.in.d.bits.source) node _T_1174 = bits(_T_1173, 0, 0) node _T_1175 = or(_T_1174, same_cycle_resp_1) node _T_1176 = asUInt(reset) node _T_1177 = eq(_T_1176, UInt<1>(0h0)) when _T_1177 : node _T_1178 = eq(_T_1175, UInt<1>(0h0)) when _T_1178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_1175, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<17>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1179 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1180 = asUInt(reset) node _T_1181 = eq(_T_1180, UInt<1>(0h0)) when _T_1181 : node _T_1182 = eq(_T_1179, UInt<1>(0h0)) when _T_1182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1179, UInt<1>(0h1), "") : assert_108 else : node _T_1183 = eq(io.in.d.bits.size, c_size_lookup) node _T_1184 = asUInt(reset) node _T_1185 = eq(_T_1184, UInt<1>(0h0)) when _T_1185 : node _T_1186 = eq(_T_1183, UInt<1>(0h0)) when _T_1186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1183, UInt<1>(0h1), "") : assert_109 node _T_1187 = and(io.in.d.valid, d_first_2) node _T_1188 = and(_T_1187, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<17>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1189 = and(_T_1188, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<17>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1190 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1191 = and(_T_1189, _T_1190) node _T_1192 = and(_T_1191, d_release_ack_1) node _T_1193 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1194 = and(_T_1192, _T_1193) when _T_1194 : node _T_1195 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<17>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1196 = or(_T_1195, _WIRE_27.ready) node _T_1197 = asUInt(reset) node _T_1198 = eq(_T_1197, UInt<1>(0h0)) when _T_1198 : node _T_1199 = eq(_T_1196, UInt<1>(0h0)) when _T_1199 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1196, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_57 node _T_1200 = orr(inflight_1) node _T_1201 = eq(_T_1200, UInt<1>(0h0)) node _T_1202 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1203 = or(_T_1201, _T_1202) node _T_1204 = lt(watchdog_1, plusarg_reader_1.out) node _T_1205 = or(_T_1203, _T_1204) node _T_1206 = asUInt(reset) node _T_1207 = eq(_T_1206, UInt<1>(0h0)) when _T_1207 : node _T_1208 = eq(_T_1205, UInt<1>(0h0)) when _T_1208 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1205, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<17>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1209 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1210 = and(io.in.d.ready, io.in.d.valid) node _T_1211 = or(_T_1209, _T_1210) when _T_1211 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_28( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [16:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [16:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire d_release_ack = 1'h0; // @[Monitor.scala:673:46] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire d_release_ack_1 = 1'h0; // @[Monitor.scala:783:46] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] a_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] a_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] a_first_beats1_1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] a_first_count_1 = 3'h0; // @[Edges.scala:234:25] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_44 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_50 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_52 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_58 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_64 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_68 = 1'h1; // @[Parameters.scala:56:32] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata = 1'h1; // @[Edges.scala:106:36] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata_1 = 1'h1; // @[Edges.scala:106:36] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata_2 = 1'h1; // @[Edges.scala:106:36] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode = 3'h1; // @[Monitor.scala:36:7] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [259:0] _inflight_opcodes_T_4 = 260'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:815:62] wire [259:0] _inflight_sizes_T_4 = 260'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:816:58] wire [64:0] _inflight_T_4 = 65'h1FFFFFFFFFFFFFFFF; // @[Monitor.scala:814:46] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [16:0] _c_first_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_first_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_first_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_first_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_set_wo_ready_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_set_wo_ready_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_opcodes_set_interm_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_opcodes_set_interm_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_sizes_set_interm_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_sizes_set_interm_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_opcodes_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_opcodes_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_sizes_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_sizes_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_probe_ack_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_probe_ack_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_probe_ack_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_probe_ack_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_4_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_5_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [259:0] d_opcodes_clr_1 = 260'h0; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1 = 260'h0; // @[Monitor.scala:777:34] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [64:0] d_clr_1 = 65'h0; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1 = 65'h0; // @[Monitor.scala:775:34] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_25 = io_in_a_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire _source_ok_T_26 = _source_ok_T_25 == 4'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_29 = source_ok_uncommonBits_4 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_30 = _source_ok_T_28 & _source_ok_T_29; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire _source_ok_T_33 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_33; // @[Parameters.scala:1138:31] wire _source_ok_T_34 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_36 = _source_ok_T_35 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_37 = _source_ok_T_36 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_38 = _source_ok_T_37 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_39 = _source_ok_T_38 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_40 = _source_ok_T_39 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_40 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [16:0] _is_aligned_T = {11'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 17'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_9 = _uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_14 = _uncommonBits_T_14[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_24 = _uncommonBits_T_24[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_29 = _uncommonBits_T_29[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_39 = _uncommonBits_T_39[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_44 = _uncommonBits_T_44[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_49 = _uncommonBits_T_49[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_54 = _uncommonBits_T_54[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_41 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_41; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_42 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_48 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_54 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_60 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_43 = _source_ok_T_42 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_45 = _source_ok_T_43; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_47; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_49 = _source_ok_T_48 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_51 = _source_ok_T_49; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_53 = _source_ok_T_51; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_53; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_55 = _source_ok_T_54 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_59 = _source_ok_T_57; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_59; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_61 = _source_ok_T_60 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_65 = _source_ok_T_63; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_65; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_66 = io_in_d_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire _source_ok_T_67 = _source_ok_T_66 == 4'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_69 = _source_ok_T_67; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_70 = source_ok_uncommonBits_9 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_71 = _source_ok_T_69 & _source_ok_T_70; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_5 = _source_ok_T_71; // @[Parameters.scala:1138:31] wire _source_ok_T_72 = io_in_d_bits_source_0 == 7'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_72; // @[Parameters.scala:1138:31] wire _source_ok_T_73 = io_in_d_bits_source_0 == 7'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_73; // @[Parameters.scala:1138:31] wire _source_ok_T_74 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_74; // @[Parameters.scala:1138:31] wire _source_ok_T_75 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_76 = _source_ok_T_75 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_77 = _source_ok_T_76 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_78 = _source_ok_T_77 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_79 = _source_ok_T_78 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_80 = _source_ok_T_79 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_81 = _source_ok_T_80 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_81 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _T_1143 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1143; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1143; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] _a_first_counter_T = a_first ? 3'h0 : a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [16:0] address; // @[Monitor.scala:391:22] wire _T_1211 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1211; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1211; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1211; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1 = d_first_beats1_decode; // @[Edges.scala:220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] _a_first_counter_T_1 = a_first_1 ? 3'h0 : a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_decode_1; // @[Edges.scala:220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1076 = _T_1143 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1076 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1076 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1076 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1076 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1076 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _T_1122 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_4 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_4; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_4; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_4; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1122 ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1089 = _T_1211 & d_first_1; // @[Decoupled.scala:51:35] assign d_clr = _T_1089 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1089 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1089 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_decode_2; // @[Edges.scala:220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_5 = _inflight_T_3; // @[Monitor.scala:814:{35,44}] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3; // @[Monitor.scala:815:{43,60}] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3; // @[Monitor.scala:816:{41,56}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_18 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<7>(0h50)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<5>(0h10)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<5>(0h11)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<5>(0h12)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<5>(0h13)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 3, 0) node _source_ok_T_27 = shr(io.in.a.bits.source, 4) node _source_ok_T_28 = eq(_source_ok_T_27, UInt<1>(0h1)) node _source_ok_T_29 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29) node _source_ok_T_31 = leq(source_ok_uncommonBits_4, UInt<4>(0hf)) node _source_ok_T_32 = and(_source_ok_T_30, _source_ok_T_31) node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 3, 0) node _source_ok_T_33 = shr(io.in.a.bits.source, 4) node _source_ok_T_34 = eq(_source_ok_T_33, UInt<1>(0h0)) node _source_ok_T_35 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35) node _source_ok_T_37 = leq(source_ok_uncommonBits_5, UInt<4>(0hf)) node _source_ok_T_38 = and(_source_ok_T_36, _source_ok_T_37) node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_40 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE : UInt<1>[11] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_32 connect _source_ok_WIRE[8], _source_ok_T_38 connect _source_ok_WIRE[9], _source_ok_T_39 connect _source_ok_WIRE[10], _source_ok_T_40 node _source_ok_T_41 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_42 = or(_source_ok_T_41, _source_ok_WIRE[2]) node _source_ok_T_43 = or(_source_ok_T_42, _source_ok_WIRE[3]) node _source_ok_T_44 = or(_source_ok_T_43, _source_ok_WIRE[4]) node _source_ok_T_45 = or(_source_ok_T_44, _source_ok_WIRE[5]) node _source_ok_T_46 = or(_source_ok_T_45, _source_ok_WIRE[6]) node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[7]) node _source_ok_T_48 = or(_source_ok_T_47, _source_ok_WIRE[8]) node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[9]) node source_ok = or(_source_ok_T_49, _source_ok_WIRE[10]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<5>(0h10)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<5>(0h11)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<5>(0h12)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<5>(0h13)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0) node _T_80 = shr(io.in.a.bits.source, 4) node _T_81 = eq(_T_80, UInt<1>(0h1)) node _T_82 = leq(UInt<1>(0h0), uncommonBits_4) node _T_83 = and(_T_81, _T_82) node _T_84 = leq(uncommonBits_4, UInt<4>(0hf)) node _T_85 = and(_T_83, _T_84) node _T_86 = eq(_T_85, UInt<1>(0h0)) node _T_87 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_88 = cvt(_T_87) node _T_89 = and(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = asSInt(_T_89) node _T_91 = eq(_T_90, asSInt(UInt<1>(0h0))) node _T_92 = or(_T_86, _T_91) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0) node _T_93 = shr(io.in.a.bits.source, 4) node _T_94 = eq(_T_93, UInt<1>(0h0)) node _T_95 = leq(UInt<1>(0h0), uncommonBits_5) node _T_96 = and(_T_94, _T_95) node _T_97 = leq(uncommonBits_5, UInt<4>(0hf)) node _T_98 = and(_T_96, _T_97) node _T_99 = eq(_T_98, UInt<1>(0h0)) node _T_100 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = or(_T_99, _T_104) node _T_106 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_107 = eq(_T_106, UInt<1>(0h0)) node _T_108 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_109 = cvt(_T_108) node _T_110 = and(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = asSInt(_T_110) node _T_112 = eq(_T_111, asSInt(UInt<1>(0h0))) node _T_113 = or(_T_107, _T_112) node _T_114 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_115 = eq(_T_114, UInt<1>(0h0)) node _T_116 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_117 = cvt(_T_116) node _T_118 = and(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = asSInt(_T_118) node _T_120 = eq(_T_119, asSInt(UInt<1>(0h0))) node _T_121 = or(_T_115, _T_120) node _T_122 = and(_T_11, _T_24) node _T_123 = and(_T_122, _T_37) node _T_124 = and(_T_123, _T_50) node _T_125 = and(_T_124, _T_63) node _T_126 = and(_T_125, _T_71) node _T_127 = and(_T_126, _T_79) node _T_128 = and(_T_127, _T_92) node _T_129 = and(_T_128, _T_105) node _T_130 = and(_T_129, _T_113) node _T_131 = and(_T_130, _T_121) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_131, UInt<1>(0h1), "") : assert_1 node _T_135 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_135 : node _T_136 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_137 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_138 = and(_T_136, _T_137) node _T_139 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_140 = shr(io.in.a.bits.source, 2) node _T_141 = eq(_T_140, UInt<5>(0h10)) node _T_142 = leq(UInt<1>(0h0), uncommonBits_6) node _T_143 = and(_T_141, _T_142) node _T_144 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_145 = and(_T_143, _T_144) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_146 = shr(io.in.a.bits.source, 2) node _T_147 = eq(_T_146, UInt<5>(0h11)) node _T_148 = leq(UInt<1>(0h0), uncommonBits_7) node _T_149 = and(_T_147, _T_148) node _T_150 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_152 = shr(io.in.a.bits.source, 2) node _T_153 = eq(_T_152, UInt<5>(0h12)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_8) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_157 = and(_T_155, _T_156) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_158 = shr(io.in.a.bits.source, 2) node _T_159 = eq(_T_158, UInt<5>(0h13)) node _T_160 = leq(UInt<1>(0h0), uncommonBits_9) node _T_161 = and(_T_159, _T_160) node _T_162 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_163 = and(_T_161, _T_162) node _T_164 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_165 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 3, 0) node _T_166 = shr(io.in.a.bits.source, 4) node _T_167 = eq(_T_166, UInt<1>(0h1)) node _T_168 = leq(UInt<1>(0h0), uncommonBits_10) node _T_169 = and(_T_167, _T_168) node _T_170 = leq(uncommonBits_10, UInt<4>(0hf)) node _T_171 = and(_T_169, _T_170) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 3, 0) node _T_172 = shr(io.in.a.bits.source, 4) node _T_173 = eq(_T_172, UInt<1>(0h0)) node _T_174 = leq(UInt<1>(0h0), uncommonBits_11) node _T_175 = and(_T_173, _T_174) node _T_176 = leq(uncommonBits_11, UInt<4>(0hf)) node _T_177 = and(_T_175, _T_176) node _T_178 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_179 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_180 = or(_T_139, _T_145) node _T_181 = or(_T_180, _T_151) node _T_182 = or(_T_181, _T_157) node _T_183 = or(_T_182, _T_163) node _T_184 = or(_T_183, _T_164) node _T_185 = or(_T_184, _T_165) node _T_186 = or(_T_185, _T_171) node _T_187 = or(_T_186, _T_177) node _T_188 = or(_T_187, _T_178) node _T_189 = or(_T_188, _T_179) node _T_190 = and(_T_138, _T_189) node _T_191 = or(UInt<1>(0h0), _T_190) node _T_192 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_193 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_194 = cvt(_T_193) node _T_195 = and(_T_194, asSInt(UInt<14>(0h2000))) node _T_196 = asSInt(_T_195) node _T_197 = eq(_T_196, asSInt(UInt<1>(0h0))) node _T_198 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_199 = cvt(_T_198) node _T_200 = and(_T_199, asSInt(UInt<13>(0h1000))) node _T_201 = asSInt(_T_200) node _T_202 = eq(_T_201, asSInt(UInt<1>(0h0))) node _T_203 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_204 = cvt(_T_203) node _T_205 = and(_T_204, asSInt(UInt<17>(0h10000))) node _T_206 = asSInt(_T_205) node _T_207 = eq(_T_206, asSInt(UInt<1>(0h0))) node _T_208 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_209 = cvt(_T_208) node _T_210 = and(_T_209, asSInt(UInt<18>(0h2f000))) node _T_211 = asSInt(_T_210) node _T_212 = eq(_T_211, asSInt(UInt<1>(0h0))) node _T_213 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_214 = cvt(_T_213) node _T_215 = and(_T_214, asSInt(UInt<17>(0h10000))) node _T_216 = asSInt(_T_215) node _T_217 = eq(_T_216, asSInt(UInt<1>(0h0))) node _T_218 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_219 = cvt(_T_218) node _T_220 = and(_T_219, asSInt(UInt<13>(0h1000))) node _T_221 = asSInt(_T_220) node _T_222 = eq(_T_221, asSInt(UInt<1>(0h0))) node _T_223 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_224 = cvt(_T_223) node _T_225 = and(_T_224, asSInt(UInt<27>(0h4000000))) node _T_226 = asSInt(_T_225) node _T_227 = eq(_T_226, asSInt(UInt<1>(0h0))) node _T_228 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_229 = cvt(_T_228) node _T_230 = and(_T_229, asSInt(UInt<13>(0h1000))) node _T_231 = asSInt(_T_230) node _T_232 = eq(_T_231, asSInt(UInt<1>(0h0))) node _T_233 = or(_T_197, _T_202) node _T_234 = or(_T_233, _T_207) node _T_235 = or(_T_234, _T_212) node _T_236 = or(_T_235, _T_217) node _T_237 = or(_T_236, _T_222) node _T_238 = or(_T_237, _T_227) node _T_239 = or(_T_238, _T_232) node _T_240 = and(_T_192, _T_239) node _T_241 = or(UInt<1>(0h0), _T_240) node _T_242 = and(_T_191, _T_241) node _T_243 = asUInt(reset) node _T_244 = eq(_T_243, UInt<1>(0h0)) when _T_244 : node _T_245 = eq(_T_242, UInt<1>(0h0)) when _T_245 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_242, UInt<1>(0h1), "") : assert_2 node _T_246 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_247 = shr(io.in.a.bits.source, 2) node _T_248 = eq(_T_247, UInt<5>(0h10)) node _T_249 = leq(UInt<1>(0h0), uncommonBits_12) node _T_250 = and(_T_248, _T_249) node _T_251 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_252 = and(_T_250, _T_251) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_253 = shr(io.in.a.bits.source, 2) node _T_254 = eq(_T_253, UInt<5>(0h11)) node _T_255 = leq(UInt<1>(0h0), uncommonBits_13) node _T_256 = and(_T_254, _T_255) node _T_257 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_258 = and(_T_256, _T_257) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_259 = shr(io.in.a.bits.source, 2) node _T_260 = eq(_T_259, UInt<5>(0h12)) node _T_261 = leq(UInt<1>(0h0), uncommonBits_14) node _T_262 = and(_T_260, _T_261) node _T_263 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_264 = and(_T_262, _T_263) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_265 = shr(io.in.a.bits.source, 2) node _T_266 = eq(_T_265, UInt<5>(0h13)) node _T_267 = leq(UInt<1>(0h0), uncommonBits_15) node _T_268 = and(_T_266, _T_267) node _T_269 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_270 = and(_T_268, _T_269) node _T_271 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_272 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 3, 0) node _T_273 = shr(io.in.a.bits.source, 4) node _T_274 = eq(_T_273, UInt<1>(0h1)) node _T_275 = leq(UInt<1>(0h0), uncommonBits_16) node _T_276 = and(_T_274, _T_275) node _T_277 = leq(uncommonBits_16, UInt<4>(0hf)) node _T_278 = and(_T_276, _T_277) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 3, 0) node _T_279 = shr(io.in.a.bits.source, 4) node _T_280 = eq(_T_279, UInt<1>(0h0)) node _T_281 = leq(UInt<1>(0h0), uncommonBits_17) node _T_282 = and(_T_280, _T_281) node _T_283 = leq(uncommonBits_17, UInt<4>(0hf)) node _T_284 = and(_T_282, _T_283) node _T_285 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_286 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _WIRE : UInt<1>[11] connect _WIRE[0], _T_246 connect _WIRE[1], _T_252 connect _WIRE[2], _T_258 connect _WIRE[3], _T_264 connect _WIRE[4], _T_270 connect _WIRE[5], _T_271 connect _WIRE[6], _T_272 connect _WIRE[7], _T_278 connect _WIRE[8], _T_284 connect _WIRE[9], _T_285 connect _WIRE[10], _T_286 node _T_287 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_288 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_289 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_290 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_291 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_293 = mux(_WIRE[5], _T_287, UInt<1>(0h0)) node _T_294 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_295 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_296 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_297 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_298 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_299 = or(_T_288, _T_289) node _T_300 = or(_T_299, _T_290) node _T_301 = or(_T_300, _T_291) node _T_302 = or(_T_301, _T_292) node _T_303 = or(_T_302, _T_293) node _T_304 = or(_T_303, _T_294) node _T_305 = or(_T_304, _T_295) node _T_306 = or(_T_305, _T_296) node _T_307 = or(_T_306, _T_297) node _T_308 = or(_T_307, _T_298) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_308 node _T_309 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_310 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_311 = and(_T_309, _T_310) node _T_312 = or(UInt<1>(0h0), _T_311) node _T_313 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_314 = cvt(_T_313) node _T_315 = and(_T_314, asSInt(UInt<14>(0h2000))) node _T_316 = asSInt(_T_315) node _T_317 = eq(_T_316, asSInt(UInt<1>(0h0))) node _T_318 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_319 = cvt(_T_318) node _T_320 = and(_T_319, asSInt(UInt<13>(0h1000))) node _T_321 = asSInt(_T_320) node _T_322 = eq(_T_321, asSInt(UInt<1>(0h0))) node _T_323 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_324 = cvt(_T_323) node _T_325 = and(_T_324, asSInt(UInt<17>(0h10000))) node _T_326 = asSInt(_T_325) node _T_327 = eq(_T_326, asSInt(UInt<1>(0h0))) node _T_328 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_329 = cvt(_T_328) node _T_330 = and(_T_329, asSInt(UInt<18>(0h2f000))) node _T_331 = asSInt(_T_330) node _T_332 = eq(_T_331, asSInt(UInt<1>(0h0))) node _T_333 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_334 = cvt(_T_333) node _T_335 = and(_T_334, asSInt(UInt<17>(0h10000))) node _T_336 = asSInt(_T_335) node _T_337 = eq(_T_336, asSInt(UInt<1>(0h0))) node _T_338 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_339 = cvt(_T_338) node _T_340 = and(_T_339, asSInt(UInt<13>(0h1000))) node _T_341 = asSInt(_T_340) node _T_342 = eq(_T_341, asSInt(UInt<1>(0h0))) node _T_343 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_344 = cvt(_T_343) node _T_345 = and(_T_344, asSInt(UInt<27>(0h4000000))) node _T_346 = asSInt(_T_345) node _T_347 = eq(_T_346, asSInt(UInt<1>(0h0))) node _T_348 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_349 = cvt(_T_348) node _T_350 = and(_T_349, asSInt(UInt<13>(0h1000))) node _T_351 = asSInt(_T_350) node _T_352 = eq(_T_351, asSInt(UInt<1>(0h0))) node _T_353 = or(_T_317, _T_322) node _T_354 = or(_T_353, _T_327) node _T_355 = or(_T_354, _T_332) node _T_356 = or(_T_355, _T_337) node _T_357 = or(_T_356, _T_342) node _T_358 = or(_T_357, _T_347) node _T_359 = or(_T_358, _T_352) node _T_360 = and(_T_312, _T_359) node _T_361 = or(UInt<1>(0h0), _T_360) node _T_362 = and(_WIRE_1, _T_361) node _T_363 = asUInt(reset) node _T_364 = eq(_T_363, UInt<1>(0h0)) when _T_364 : node _T_365 = eq(_T_362, UInt<1>(0h0)) when _T_365 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_362, UInt<1>(0h1), "") : assert_3 node _T_366 = asUInt(reset) node _T_367 = eq(_T_366, UInt<1>(0h0)) when _T_367 : node _T_368 = eq(source_ok, UInt<1>(0h0)) when _T_368 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_369 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_370 = asUInt(reset) node _T_371 = eq(_T_370, UInt<1>(0h0)) when _T_371 : node _T_372 = eq(_T_369, UInt<1>(0h0)) when _T_372 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_369, UInt<1>(0h1), "") : assert_5 node _T_373 = asUInt(reset) node _T_374 = eq(_T_373, UInt<1>(0h0)) when _T_374 : node _T_375 = eq(is_aligned, UInt<1>(0h0)) when _T_375 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_376 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_377 = asUInt(reset) node _T_378 = eq(_T_377, UInt<1>(0h0)) when _T_378 : node _T_379 = eq(_T_376, UInt<1>(0h0)) when _T_379 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_376, UInt<1>(0h1), "") : assert_7 node _T_380 = not(io.in.a.bits.mask) node _T_381 = eq(_T_380, UInt<1>(0h0)) node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(_T_381, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_381, UInt<1>(0h1), "") : assert_8 node _T_385 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_385, UInt<1>(0h1), "") : assert_9 node _T_389 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_389 : node _T_390 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_391 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_392 = and(_T_390, _T_391) node _T_393 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_394 = shr(io.in.a.bits.source, 2) node _T_395 = eq(_T_394, UInt<5>(0h10)) node _T_396 = leq(UInt<1>(0h0), uncommonBits_18) node _T_397 = and(_T_395, _T_396) node _T_398 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_399 = and(_T_397, _T_398) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_400 = shr(io.in.a.bits.source, 2) node _T_401 = eq(_T_400, UInt<5>(0h11)) node _T_402 = leq(UInt<1>(0h0), uncommonBits_19) node _T_403 = and(_T_401, _T_402) node _T_404 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_405 = and(_T_403, _T_404) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_406 = shr(io.in.a.bits.source, 2) node _T_407 = eq(_T_406, UInt<5>(0h12)) node _T_408 = leq(UInt<1>(0h0), uncommonBits_20) node _T_409 = and(_T_407, _T_408) node _T_410 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_411 = and(_T_409, _T_410) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_412 = shr(io.in.a.bits.source, 2) node _T_413 = eq(_T_412, UInt<5>(0h13)) node _T_414 = leq(UInt<1>(0h0), uncommonBits_21) node _T_415 = and(_T_413, _T_414) node _T_416 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_417 = and(_T_415, _T_416) node _T_418 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_419 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 3, 0) node _T_420 = shr(io.in.a.bits.source, 4) node _T_421 = eq(_T_420, UInt<1>(0h1)) node _T_422 = leq(UInt<1>(0h0), uncommonBits_22) node _T_423 = and(_T_421, _T_422) node _T_424 = leq(uncommonBits_22, UInt<4>(0hf)) node _T_425 = and(_T_423, _T_424) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 3, 0) node _T_426 = shr(io.in.a.bits.source, 4) node _T_427 = eq(_T_426, UInt<1>(0h0)) node _T_428 = leq(UInt<1>(0h0), uncommonBits_23) node _T_429 = and(_T_427, _T_428) node _T_430 = leq(uncommonBits_23, UInt<4>(0hf)) node _T_431 = and(_T_429, _T_430) node _T_432 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_433 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_434 = or(_T_393, _T_399) node _T_435 = or(_T_434, _T_405) node _T_436 = or(_T_435, _T_411) node _T_437 = or(_T_436, _T_417) node _T_438 = or(_T_437, _T_418) node _T_439 = or(_T_438, _T_419) node _T_440 = or(_T_439, _T_425) node _T_441 = or(_T_440, _T_431) node _T_442 = or(_T_441, _T_432) node _T_443 = or(_T_442, _T_433) node _T_444 = and(_T_392, _T_443) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_447 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_448 = cvt(_T_447) node _T_449 = and(_T_448, asSInt(UInt<14>(0h2000))) node _T_450 = asSInt(_T_449) node _T_451 = eq(_T_450, asSInt(UInt<1>(0h0))) node _T_452 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_453 = cvt(_T_452) node _T_454 = and(_T_453, asSInt(UInt<13>(0h1000))) node _T_455 = asSInt(_T_454) node _T_456 = eq(_T_455, asSInt(UInt<1>(0h0))) node _T_457 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_458 = cvt(_T_457) node _T_459 = and(_T_458, asSInt(UInt<17>(0h10000))) node _T_460 = asSInt(_T_459) node _T_461 = eq(_T_460, asSInt(UInt<1>(0h0))) node _T_462 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_463 = cvt(_T_462) node _T_464 = and(_T_463, asSInt(UInt<18>(0h2f000))) node _T_465 = asSInt(_T_464) node _T_466 = eq(_T_465, asSInt(UInt<1>(0h0))) node _T_467 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<17>(0h10000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_473 = cvt(_T_472) node _T_474 = and(_T_473, asSInt(UInt<13>(0h1000))) node _T_475 = asSInt(_T_474) node _T_476 = eq(_T_475, asSInt(UInt<1>(0h0))) node _T_477 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_478 = cvt(_T_477) node _T_479 = and(_T_478, asSInt(UInt<27>(0h4000000))) node _T_480 = asSInt(_T_479) node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0))) node _T_482 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_483 = cvt(_T_482) node _T_484 = and(_T_483, asSInt(UInt<13>(0h1000))) node _T_485 = asSInt(_T_484) node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0))) node _T_487 = or(_T_451, _T_456) node _T_488 = or(_T_487, _T_461) node _T_489 = or(_T_488, _T_466) node _T_490 = or(_T_489, _T_471) node _T_491 = or(_T_490, _T_476) node _T_492 = or(_T_491, _T_481) node _T_493 = or(_T_492, _T_486) node _T_494 = and(_T_446, _T_493) node _T_495 = or(UInt<1>(0h0), _T_494) node _T_496 = and(_T_445, _T_495) node _T_497 = asUInt(reset) node _T_498 = eq(_T_497, UInt<1>(0h0)) when _T_498 : node _T_499 = eq(_T_496, UInt<1>(0h0)) when _T_499 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_496, UInt<1>(0h1), "") : assert_10 node _T_500 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_501 = shr(io.in.a.bits.source, 2) node _T_502 = eq(_T_501, UInt<5>(0h10)) node _T_503 = leq(UInt<1>(0h0), uncommonBits_24) node _T_504 = and(_T_502, _T_503) node _T_505 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_506 = and(_T_504, _T_505) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_507 = shr(io.in.a.bits.source, 2) node _T_508 = eq(_T_507, UInt<5>(0h11)) node _T_509 = leq(UInt<1>(0h0), uncommonBits_25) node _T_510 = and(_T_508, _T_509) node _T_511 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_512 = and(_T_510, _T_511) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_513 = shr(io.in.a.bits.source, 2) node _T_514 = eq(_T_513, UInt<5>(0h12)) node _T_515 = leq(UInt<1>(0h0), uncommonBits_26) node _T_516 = and(_T_514, _T_515) node _T_517 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_518 = and(_T_516, _T_517) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_519 = shr(io.in.a.bits.source, 2) node _T_520 = eq(_T_519, UInt<5>(0h13)) node _T_521 = leq(UInt<1>(0h0), uncommonBits_27) node _T_522 = and(_T_520, _T_521) node _T_523 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_524 = and(_T_522, _T_523) node _T_525 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_526 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 3, 0) node _T_527 = shr(io.in.a.bits.source, 4) node _T_528 = eq(_T_527, UInt<1>(0h1)) node _T_529 = leq(UInt<1>(0h0), uncommonBits_28) node _T_530 = and(_T_528, _T_529) node _T_531 = leq(uncommonBits_28, UInt<4>(0hf)) node _T_532 = and(_T_530, _T_531) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 3, 0) node _T_533 = shr(io.in.a.bits.source, 4) node _T_534 = eq(_T_533, UInt<1>(0h0)) node _T_535 = leq(UInt<1>(0h0), uncommonBits_29) node _T_536 = and(_T_534, _T_535) node _T_537 = leq(uncommonBits_29, UInt<4>(0hf)) node _T_538 = and(_T_536, _T_537) node _T_539 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_540 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _WIRE_2 : UInt<1>[11] connect _WIRE_2[0], _T_500 connect _WIRE_2[1], _T_506 connect _WIRE_2[2], _T_512 connect _WIRE_2[3], _T_518 connect _WIRE_2[4], _T_524 connect _WIRE_2[5], _T_525 connect _WIRE_2[6], _T_526 connect _WIRE_2[7], _T_532 connect _WIRE_2[8], _T_538 connect _WIRE_2[9], _T_539 connect _WIRE_2[10], _T_540 node _T_541 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_542 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_543 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_544 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_545 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_546 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_547 = mux(_WIRE_2[5], _T_541, UInt<1>(0h0)) node _T_548 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_549 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_550 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_551 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_552 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_553 = or(_T_542, _T_543) node _T_554 = or(_T_553, _T_544) node _T_555 = or(_T_554, _T_545) node _T_556 = or(_T_555, _T_546) node _T_557 = or(_T_556, _T_547) node _T_558 = or(_T_557, _T_548) node _T_559 = or(_T_558, _T_549) node _T_560 = or(_T_559, _T_550) node _T_561 = or(_T_560, _T_551) node _T_562 = or(_T_561, _T_552) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_562 node _T_563 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_564 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_565 = and(_T_563, _T_564) node _T_566 = or(UInt<1>(0h0), _T_565) node _T_567 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_568 = cvt(_T_567) node _T_569 = and(_T_568, asSInt(UInt<14>(0h2000))) node _T_570 = asSInt(_T_569) node _T_571 = eq(_T_570, asSInt(UInt<1>(0h0))) node _T_572 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_573 = cvt(_T_572) node _T_574 = and(_T_573, asSInt(UInt<13>(0h1000))) node _T_575 = asSInt(_T_574) node _T_576 = eq(_T_575, asSInt(UInt<1>(0h0))) node _T_577 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_578 = cvt(_T_577) node _T_579 = and(_T_578, asSInt(UInt<17>(0h10000))) node _T_580 = asSInt(_T_579) node _T_581 = eq(_T_580, asSInt(UInt<1>(0h0))) node _T_582 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_583 = cvt(_T_582) node _T_584 = and(_T_583, asSInt(UInt<18>(0h2f000))) node _T_585 = asSInt(_T_584) node _T_586 = eq(_T_585, asSInt(UInt<1>(0h0))) node _T_587 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_588 = cvt(_T_587) node _T_589 = and(_T_588, asSInt(UInt<17>(0h10000))) node _T_590 = asSInt(_T_589) node _T_591 = eq(_T_590, asSInt(UInt<1>(0h0))) node _T_592 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_593 = cvt(_T_592) node _T_594 = and(_T_593, asSInt(UInt<13>(0h1000))) node _T_595 = asSInt(_T_594) node _T_596 = eq(_T_595, asSInt(UInt<1>(0h0))) node _T_597 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_598 = cvt(_T_597) node _T_599 = and(_T_598, asSInt(UInt<27>(0h4000000))) node _T_600 = asSInt(_T_599) node _T_601 = eq(_T_600, asSInt(UInt<1>(0h0))) node _T_602 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_603 = cvt(_T_602) node _T_604 = and(_T_603, asSInt(UInt<13>(0h1000))) node _T_605 = asSInt(_T_604) node _T_606 = eq(_T_605, asSInt(UInt<1>(0h0))) node _T_607 = or(_T_571, _T_576) node _T_608 = or(_T_607, _T_581) node _T_609 = or(_T_608, _T_586) node _T_610 = or(_T_609, _T_591) node _T_611 = or(_T_610, _T_596) node _T_612 = or(_T_611, _T_601) node _T_613 = or(_T_612, _T_606) node _T_614 = and(_T_566, _T_613) node _T_615 = or(UInt<1>(0h0), _T_614) node _T_616 = and(_WIRE_3, _T_615) node _T_617 = asUInt(reset) node _T_618 = eq(_T_617, UInt<1>(0h0)) when _T_618 : node _T_619 = eq(_T_616, UInt<1>(0h0)) when _T_619 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_616, UInt<1>(0h1), "") : assert_11 node _T_620 = asUInt(reset) node _T_621 = eq(_T_620, UInt<1>(0h0)) when _T_621 : node _T_622 = eq(source_ok, UInt<1>(0h0)) when _T_622 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_623 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_624 = asUInt(reset) node _T_625 = eq(_T_624, UInt<1>(0h0)) when _T_625 : node _T_626 = eq(_T_623, UInt<1>(0h0)) when _T_626 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_623, UInt<1>(0h1), "") : assert_13 node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(is_aligned, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_630 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_630, UInt<1>(0h1), "") : assert_15 node _T_634 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_635 = asUInt(reset) node _T_636 = eq(_T_635, UInt<1>(0h0)) when _T_636 : node _T_637 = eq(_T_634, UInt<1>(0h0)) when _T_637 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_634, UInt<1>(0h1), "") : assert_16 node _T_638 = not(io.in.a.bits.mask) node _T_639 = eq(_T_638, UInt<1>(0h0)) node _T_640 = asUInt(reset) node _T_641 = eq(_T_640, UInt<1>(0h0)) when _T_641 : node _T_642 = eq(_T_639, UInt<1>(0h0)) when _T_642 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_639, UInt<1>(0h1), "") : assert_17 node _T_643 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_644 = asUInt(reset) node _T_645 = eq(_T_644, UInt<1>(0h0)) when _T_645 : node _T_646 = eq(_T_643, UInt<1>(0h0)) when _T_646 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_643, UInt<1>(0h1), "") : assert_18 node _T_647 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_647 : node _T_648 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_649 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_650 = and(_T_648, _T_649) node _T_651 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_652 = shr(io.in.a.bits.source, 2) node _T_653 = eq(_T_652, UInt<5>(0h10)) node _T_654 = leq(UInt<1>(0h0), uncommonBits_30) node _T_655 = and(_T_653, _T_654) node _T_656 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_657 = and(_T_655, _T_656) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_658 = shr(io.in.a.bits.source, 2) node _T_659 = eq(_T_658, UInt<5>(0h11)) node _T_660 = leq(UInt<1>(0h0), uncommonBits_31) node _T_661 = and(_T_659, _T_660) node _T_662 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_663 = and(_T_661, _T_662) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_664 = shr(io.in.a.bits.source, 2) node _T_665 = eq(_T_664, UInt<5>(0h12)) node _T_666 = leq(UInt<1>(0h0), uncommonBits_32) node _T_667 = and(_T_665, _T_666) node _T_668 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_669 = and(_T_667, _T_668) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_670 = shr(io.in.a.bits.source, 2) node _T_671 = eq(_T_670, UInt<5>(0h13)) node _T_672 = leq(UInt<1>(0h0), uncommonBits_33) node _T_673 = and(_T_671, _T_672) node _T_674 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_675 = and(_T_673, _T_674) node _T_676 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_677 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 3, 0) node _T_678 = shr(io.in.a.bits.source, 4) node _T_679 = eq(_T_678, UInt<1>(0h1)) node _T_680 = leq(UInt<1>(0h0), uncommonBits_34) node _T_681 = and(_T_679, _T_680) node _T_682 = leq(uncommonBits_34, UInt<4>(0hf)) node _T_683 = and(_T_681, _T_682) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 3, 0) node _T_684 = shr(io.in.a.bits.source, 4) node _T_685 = eq(_T_684, UInt<1>(0h0)) node _T_686 = leq(UInt<1>(0h0), uncommonBits_35) node _T_687 = and(_T_685, _T_686) node _T_688 = leq(uncommonBits_35, UInt<4>(0hf)) node _T_689 = and(_T_687, _T_688) node _T_690 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_691 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_692 = or(_T_651, _T_657) node _T_693 = or(_T_692, _T_663) node _T_694 = or(_T_693, _T_669) node _T_695 = or(_T_694, _T_675) node _T_696 = or(_T_695, _T_676) node _T_697 = or(_T_696, _T_677) node _T_698 = or(_T_697, _T_683) node _T_699 = or(_T_698, _T_689) node _T_700 = or(_T_699, _T_690) node _T_701 = or(_T_700, _T_691) node _T_702 = and(_T_650, _T_701) node _T_703 = or(UInt<1>(0h0), _T_702) node _T_704 = asUInt(reset) node _T_705 = eq(_T_704, UInt<1>(0h0)) when _T_705 : node _T_706 = eq(_T_703, UInt<1>(0h0)) when _T_706 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_703, UInt<1>(0h1), "") : assert_19 node _T_707 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_708 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_709 = and(_T_707, _T_708) node _T_710 = or(UInt<1>(0h0), _T_709) node _T_711 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_712 = cvt(_T_711) node _T_713 = and(_T_712, asSInt(UInt<13>(0h1000))) node _T_714 = asSInt(_T_713) node _T_715 = eq(_T_714, asSInt(UInt<1>(0h0))) node _T_716 = and(_T_710, _T_715) node _T_717 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_718 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_719 = and(_T_717, _T_718) node _T_720 = or(UInt<1>(0h0), _T_719) node _T_721 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_722 = cvt(_T_721) node _T_723 = and(_T_722, asSInt(UInt<14>(0h2000))) node _T_724 = asSInt(_T_723) node _T_725 = eq(_T_724, asSInt(UInt<1>(0h0))) node _T_726 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_727 = cvt(_T_726) node _T_728 = and(_T_727, asSInt(UInt<17>(0h10000))) node _T_729 = asSInt(_T_728) node _T_730 = eq(_T_729, asSInt(UInt<1>(0h0))) node _T_731 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_732 = cvt(_T_731) node _T_733 = and(_T_732, asSInt(UInt<18>(0h2f000))) node _T_734 = asSInt(_T_733) node _T_735 = eq(_T_734, asSInt(UInt<1>(0h0))) node _T_736 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_737 = cvt(_T_736) node _T_738 = and(_T_737, asSInt(UInt<17>(0h10000))) node _T_739 = asSInt(_T_738) node _T_740 = eq(_T_739, asSInt(UInt<1>(0h0))) node _T_741 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_742 = cvt(_T_741) node _T_743 = and(_T_742, asSInt(UInt<13>(0h1000))) node _T_744 = asSInt(_T_743) node _T_745 = eq(_T_744, asSInt(UInt<1>(0h0))) node _T_746 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_747 = cvt(_T_746) node _T_748 = and(_T_747, asSInt(UInt<27>(0h4000000))) node _T_749 = asSInt(_T_748) node _T_750 = eq(_T_749, asSInt(UInt<1>(0h0))) node _T_751 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_752 = cvt(_T_751) node _T_753 = and(_T_752, asSInt(UInt<13>(0h1000))) node _T_754 = asSInt(_T_753) node _T_755 = eq(_T_754, asSInt(UInt<1>(0h0))) node _T_756 = or(_T_725, _T_730) node _T_757 = or(_T_756, _T_735) node _T_758 = or(_T_757, _T_740) node _T_759 = or(_T_758, _T_745) node _T_760 = or(_T_759, _T_750) node _T_761 = or(_T_760, _T_755) node _T_762 = and(_T_720, _T_761) node _T_763 = or(UInt<1>(0h0), _T_716) node _T_764 = or(_T_763, _T_762) node _T_765 = asUInt(reset) node _T_766 = eq(_T_765, UInt<1>(0h0)) when _T_766 : node _T_767 = eq(_T_764, UInt<1>(0h0)) when _T_767 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_764, UInt<1>(0h1), "") : assert_20 node _T_768 = asUInt(reset) node _T_769 = eq(_T_768, UInt<1>(0h0)) when _T_769 : node _T_770 = eq(source_ok, UInt<1>(0h0)) when _T_770 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_771 = asUInt(reset) node _T_772 = eq(_T_771, UInt<1>(0h0)) when _T_772 : node _T_773 = eq(is_aligned, UInt<1>(0h0)) when _T_773 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_774 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_775 = asUInt(reset) node _T_776 = eq(_T_775, UInt<1>(0h0)) when _T_776 : node _T_777 = eq(_T_774, UInt<1>(0h0)) when _T_777 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_774, UInt<1>(0h1), "") : assert_23 node _T_778 = eq(io.in.a.bits.mask, mask) node _T_779 = asUInt(reset) node _T_780 = eq(_T_779, UInt<1>(0h0)) when _T_780 : node _T_781 = eq(_T_778, UInt<1>(0h0)) when _T_781 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_778, UInt<1>(0h1), "") : assert_24 node _T_782 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_783 = asUInt(reset) node _T_784 = eq(_T_783, UInt<1>(0h0)) when _T_784 : node _T_785 = eq(_T_782, UInt<1>(0h0)) when _T_785 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_782, UInt<1>(0h1), "") : assert_25 node _T_786 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_786 : node _T_787 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_788 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_789 = and(_T_787, _T_788) node _T_790 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_791 = shr(io.in.a.bits.source, 2) node _T_792 = eq(_T_791, UInt<5>(0h10)) node _T_793 = leq(UInt<1>(0h0), uncommonBits_36) node _T_794 = and(_T_792, _T_793) node _T_795 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_796 = and(_T_794, _T_795) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_797 = shr(io.in.a.bits.source, 2) node _T_798 = eq(_T_797, UInt<5>(0h11)) node _T_799 = leq(UInt<1>(0h0), uncommonBits_37) node _T_800 = and(_T_798, _T_799) node _T_801 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_802 = and(_T_800, _T_801) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_803 = shr(io.in.a.bits.source, 2) node _T_804 = eq(_T_803, UInt<5>(0h12)) node _T_805 = leq(UInt<1>(0h0), uncommonBits_38) node _T_806 = and(_T_804, _T_805) node _T_807 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_808 = and(_T_806, _T_807) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_809 = shr(io.in.a.bits.source, 2) node _T_810 = eq(_T_809, UInt<5>(0h13)) node _T_811 = leq(UInt<1>(0h0), uncommonBits_39) node _T_812 = and(_T_810, _T_811) node _T_813 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_814 = and(_T_812, _T_813) node _T_815 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_816 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 3, 0) node _T_817 = shr(io.in.a.bits.source, 4) node _T_818 = eq(_T_817, UInt<1>(0h1)) node _T_819 = leq(UInt<1>(0h0), uncommonBits_40) node _T_820 = and(_T_818, _T_819) node _T_821 = leq(uncommonBits_40, UInt<4>(0hf)) node _T_822 = and(_T_820, _T_821) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 3, 0) node _T_823 = shr(io.in.a.bits.source, 4) node _T_824 = eq(_T_823, UInt<1>(0h0)) node _T_825 = leq(UInt<1>(0h0), uncommonBits_41) node _T_826 = and(_T_824, _T_825) node _T_827 = leq(uncommonBits_41, UInt<4>(0hf)) node _T_828 = and(_T_826, _T_827) node _T_829 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_830 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_831 = or(_T_790, _T_796) node _T_832 = or(_T_831, _T_802) node _T_833 = or(_T_832, _T_808) node _T_834 = or(_T_833, _T_814) node _T_835 = or(_T_834, _T_815) node _T_836 = or(_T_835, _T_816) node _T_837 = or(_T_836, _T_822) node _T_838 = or(_T_837, _T_828) node _T_839 = or(_T_838, _T_829) node _T_840 = or(_T_839, _T_830) node _T_841 = and(_T_789, _T_840) node _T_842 = or(UInt<1>(0h0), _T_841) node _T_843 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_844 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_845 = and(_T_843, _T_844) node _T_846 = or(UInt<1>(0h0), _T_845) node _T_847 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_848 = cvt(_T_847) node _T_849 = and(_T_848, asSInt(UInt<13>(0h1000))) node _T_850 = asSInt(_T_849) node _T_851 = eq(_T_850, asSInt(UInt<1>(0h0))) node _T_852 = and(_T_846, _T_851) node _T_853 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_854 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_855 = and(_T_853, _T_854) node _T_856 = or(UInt<1>(0h0), _T_855) node _T_857 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_858 = cvt(_T_857) node _T_859 = and(_T_858, asSInt(UInt<14>(0h2000))) node _T_860 = asSInt(_T_859) node _T_861 = eq(_T_860, asSInt(UInt<1>(0h0))) node _T_862 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_863 = cvt(_T_862) node _T_864 = and(_T_863, asSInt(UInt<18>(0h2f000))) node _T_865 = asSInt(_T_864) node _T_866 = eq(_T_865, asSInt(UInt<1>(0h0))) node _T_867 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_868 = cvt(_T_867) node _T_869 = and(_T_868, asSInt(UInt<17>(0h10000))) node _T_870 = asSInt(_T_869) node _T_871 = eq(_T_870, asSInt(UInt<1>(0h0))) node _T_872 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_873 = cvt(_T_872) node _T_874 = and(_T_873, asSInt(UInt<13>(0h1000))) node _T_875 = asSInt(_T_874) node _T_876 = eq(_T_875, asSInt(UInt<1>(0h0))) node _T_877 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_878 = cvt(_T_877) node _T_879 = and(_T_878, asSInt(UInt<27>(0h4000000))) node _T_880 = asSInt(_T_879) node _T_881 = eq(_T_880, asSInt(UInt<1>(0h0))) node _T_882 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_883 = cvt(_T_882) node _T_884 = and(_T_883, asSInt(UInt<13>(0h1000))) node _T_885 = asSInt(_T_884) node _T_886 = eq(_T_885, asSInt(UInt<1>(0h0))) node _T_887 = or(_T_861, _T_866) node _T_888 = or(_T_887, _T_871) node _T_889 = or(_T_888, _T_876) node _T_890 = or(_T_889, _T_881) node _T_891 = or(_T_890, _T_886) node _T_892 = and(_T_856, _T_891) node _T_893 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_894 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_895 = cvt(_T_894) node _T_896 = and(_T_895, asSInt(UInt<17>(0h10000))) node _T_897 = asSInt(_T_896) node _T_898 = eq(_T_897, asSInt(UInt<1>(0h0))) node _T_899 = and(_T_893, _T_898) node _T_900 = or(UInt<1>(0h0), _T_852) node _T_901 = or(_T_900, _T_892) node _T_902 = or(_T_901, _T_899) node _T_903 = and(_T_842, _T_902) node _T_904 = asUInt(reset) node _T_905 = eq(_T_904, UInt<1>(0h0)) when _T_905 : node _T_906 = eq(_T_903, UInt<1>(0h0)) when _T_906 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_903, UInt<1>(0h1), "") : assert_26 node _T_907 = asUInt(reset) node _T_908 = eq(_T_907, UInt<1>(0h0)) when _T_908 : node _T_909 = eq(source_ok, UInt<1>(0h0)) when _T_909 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_910 = asUInt(reset) node _T_911 = eq(_T_910, UInt<1>(0h0)) when _T_911 : node _T_912 = eq(is_aligned, UInt<1>(0h0)) when _T_912 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_913 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_914 = asUInt(reset) node _T_915 = eq(_T_914, UInt<1>(0h0)) when _T_915 : node _T_916 = eq(_T_913, UInt<1>(0h0)) when _T_916 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_913, UInt<1>(0h1), "") : assert_29 node _T_917 = eq(io.in.a.bits.mask, mask) node _T_918 = asUInt(reset) node _T_919 = eq(_T_918, UInt<1>(0h0)) when _T_919 : node _T_920 = eq(_T_917, UInt<1>(0h0)) when _T_920 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_917, UInt<1>(0h1), "") : assert_30 node _T_921 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_921 : node _T_922 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_923 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_924 = and(_T_922, _T_923) node _T_925 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_926 = shr(io.in.a.bits.source, 2) node _T_927 = eq(_T_926, UInt<5>(0h10)) node _T_928 = leq(UInt<1>(0h0), uncommonBits_42) node _T_929 = and(_T_927, _T_928) node _T_930 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_931 = and(_T_929, _T_930) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_932 = shr(io.in.a.bits.source, 2) node _T_933 = eq(_T_932, UInt<5>(0h11)) node _T_934 = leq(UInt<1>(0h0), uncommonBits_43) node _T_935 = and(_T_933, _T_934) node _T_936 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_937 = and(_T_935, _T_936) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0) node _T_938 = shr(io.in.a.bits.source, 2) node _T_939 = eq(_T_938, UInt<5>(0h12)) node _T_940 = leq(UInt<1>(0h0), uncommonBits_44) node _T_941 = and(_T_939, _T_940) node _T_942 = leq(uncommonBits_44, UInt<2>(0h3)) node _T_943 = and(_T_941, _T_942) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_944 = shr(io.in.a.bits.source, 2) node _T_945 = eq(_T_944, UInt<5>(0h13)) node _T_946 = leq(UInt<1>(0h0), uncommonBits_45) node _T_947 = and(_T_945, _T_946) node _T_948 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_949 = and(_T_947, _T_948) node _T_950 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_951 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 3, 0) node _T_952 = shr(io.in.a.bits.source, 4) node _T_953 = eq(_T_952, UInt<1>(0h1)) node _T_954 = leq(UInt<1>(0h0), uncommonBits_46) node _T_955 = and(_T_953, _T_954) node _T_956 = leq(uncommonBits_46, UInt<4>(0hf)) node _T_957 = and(_T_955, _T_956) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 3, 0) node _T_958 = shr(io.in.a.bits.source, 4) node _T_959 = eq(_T_958, UInt<1>(0h0)) node _T_960 = leq(UInt<1>(0h0), uncommonBits_47) node _T_961 = and(_T_959, _T_960) node _T_962 = leq(uncommonBits_47, UInt<4>(0hf)) node _T_963 = and(_T_961, _T_962) node _T_964 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_965 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_966 = or(_T_925, _T_931) node _T_967 = or(_T_966, _T_937) node _T_968 = or(_T_967, _T_943) node _T_969 = or(_T_968, _T_949) node _T_970 = or(_T_969, _T_950) node _T_971 = or(_T_970, _T_951) node _T_972 = or(_T_971, _T_957) node _T_973 = or(_T_972, _T_963) node _T_974 = or(_T_973, _T_964) node _T_975 = or(_T_974, _T_965) node _T_976 = and(_T_924, _T_975) node _T_977 = or(UInt<1>(0h0), _T_976) node _T_978 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_979 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_980 = and(_T_978, _T_979) node _T_981 = or(UInt<1>(0h0), _T_980) node _T_982 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_983 = cvt(_T_982) node _T_984 = and(_T_983, asSInt(UInt<13>(0h1000))) node _T_985 = asSInt(_T_984) node _T_986 = eq(_T_985, asSInt(UInt<1>(0h0))) node _T_987 = and(_T_981, _T_986) node _T_988 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_989 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_990 = and(_T_988, _T_989) node _T_991 = or(UInt<1>(0h0), _T_990) node _T_992 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_993 = cvt(_T_992) node _T_994 = and(_T_993, asSInt(UInt<14>(0h2000))) node _T_995 = asSInt(_T_994) node _T_996 = eq(_T_995, asSInt(UInt<1>(0h0))) node _T_997 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_998 = cvt(_T_997) node _T_999 = and(_T_998, asSInt(UInt<18>(0h2f000))) node _T_1000 = asSInt(_T_999) node _T_1001 = eq(_T_1000, asSInt(UInt<1>(0h0))) node _T_1002 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1003 = cvt(_T_1002) node _T_1004 = and(_T_1003, asSInt(UInt<17>(0h10000))) node _T_1005 = asSInt(_T_1004) node _T_1006 = eq(_T_1005, asSInt(UInt<1>(0h0))) node _T_1007 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1008 = cvt(_T_1007) node _T_1009 = and(_T_1008, asSInt(UInt<13>(0h1000))) node _T_1010 = asSInt(_T_1009) node _T_1011 = eq(_T_1010, asSInt(UInt<1>(0h0))) node _T_1012 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1013 = cvt(_T_1012) node _T_1014 = and(_T_1013, asSInt(UInt<27>(0h4000000))) node _T_1015 = asSInt(_T_1014) node _T_1016 = eq(_T_1015, asSInt(UInt<1>(0h0))) node _T_1017 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1018 = cvt(_T_1017) node _T_1019 = and(_T_1018, asSInt(UInt<13>(0h1000))) node _T_1020 = asSInt(_T_1019) node _T_1021 = eq(_T_1020, asSInt(UInt<1>(0h0))) node _T_1022 = or(_T_996, _T_1001) node _T_1023 = or(_T_1022, _T_1006) node _T_1024 = or(_T_1023, _T_1011) node _T_1025 = or(_T_1024, _T_1016) node _T_1026 = or(_T_1025, _T_1021) node _T_1027 = and(_T_991, _T_1026) node _T_1028 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1029 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1030 = cvt(_T_1029) node _T_1031 = and(_T_1030, asSInt(UInt<17>(0h10000))) node _T_1032 = asSInt(_T_1031) node _T_1033 = eq(_T_1032, asSInt(UInt<1>(0h0))) node _T_1034 = and(_T_1028, _T_1033) node _T_1035 = or(UInt<1>(0h0), _T_987) node _T_1036 = or(_T_1035, _T_1027) node _T_1037 = or(_T_1036, _T_1034) node _T_1038 = and(_T_977, _T_1037) node _T_1039 = asUInt(reset) node _T_1040 = eq(_T_1039, UInt<1>(0h0)) when _T_1040 : node _T_1041 = eq(_T_1038, UInt<1>(0h0)) when _T_1041 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_1038, UInt<1>(0h1), "") : assert_31 node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(source_ok, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_1045 = asUInt(reset) node _T_1046 = eq(_T_1045, UInt<1>(0h0)) when _T_1046 : node _T_1047 = eq(is_aligned, UInt<1>(0h0)) when _T_1047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_1048 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1049 = asUInt(reset) node _T_1050 = eq(_T_1049, UInt<1>(0h0)) when _T_1050 : node _T_1051 = eq(_T_1048, UInt<1>(0h0)) when _T_1051 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_1048, UInt<1>(0h1), "") : assert_34 node _T_1052 = not(mask) node _T_1053 = and(io.in.a.bits.mask, _T_1052) node _T_1054 = eq(_T_1053, UInt<1>(0h0)) node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(_T_1054, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_1054, UInt<1>(0h1), "") : assert_35 node _T_1058 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_1058 : node _T_1059 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1060 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1061 = and(_T_1059, _T_1060) node _T_1062 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_1063 = shr(io.in.a.bits.source, 2) node _T_1064 = eq(_T_1063, UInt<5>(0h10)) node _T_1065 = leq(UInt<1>(0h0), uncommonBits_48) node _T_1066 = and(_T_1064, _T_1065) node _T_1067 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_1068 = and(_T_1066, _T_1067) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0) node _T_1069 = shr(io.in.a.bits.source, 2) node _T_1070 = eq(_T_1069, UInt<5>(0h11)) node _T_1071 = leq(UInt<1>(0h0), uncommonBits_49) node _T_1072 = and(_T_1070, _T_1071) node _T_1073 = leq(uncommonBits_49, UInt<2>(0h3)) node _T_1074 = and(_T_1072, _T_1073) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_1075 = shr(io.in.a.bits.source, 2) node _T_1076 = eq(_T_1075, UInt<5>(0h12)) node _T_1077 = leq(UInt<1>(0h0), uncommonBits_50) node _T_1078 = and(_T_1076, _T_1077) node _T_1079 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_1080 = and(_T_1078, _T_1079) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_1081 = shr(io.in.a.bits.source, 2) node _T_1082 = eq(_T_1081, UInt<5>(0h13)) node _T_1083 = leq(UInt<1>(0h0), uncommonBits_51) node _T_1084 = and(_T_1082, _T_1083) node _T_1085 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_1086 = and(_T_1084, _T_1085) node _T_1087 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1088 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 3, 0) node _T_1089 = shr(io.in.a.bits.source, 4) node _T_1090 = eq(_T_1089, UInt<1>(0h1)) node _T_1091 = leq(UInt<1>(0h0), uncommonBits_52) node _T_1092 = and(_T_1090, _T_1091) node _T_1093 = leq(uncommonBits_52, UInt<4>(0hf)) node _T_1094 = and(_T_1092, _T_1093) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 3, 0) node _T_1095 = shr(io.in.a.bits.source, 4) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) node _T_1097 = leq(UInt<1>(0h0), uncommonBits_53) node _T_1098 = and(_T_1096, _T_1097) node _T_1099 = leq(uncommonBits_53, UInt<4>(0hf)) node _T_1100 = and(_T_1098, _T_1099) node _T_1101 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1102 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1103 = or(_T_1062, _T_1068) node _T_1104 = or(_T_1103, _T_1074) node _T_1105 = or(_T_1104, _T_1080) node _T_1106 = or(_T_1105, _T_1086) node _T_1107 = or(_T_1106, _T_1087) node _T_1108 = or(_T_1107, _T_1088) node _T_1109 = or(_T_1108, _T_1094) node _T_1110 = or(_T_1109, _T_1100) node _T_1111 = or(_T_1110, _T_1101) node _T_1112 = or(_T_1111, _T_1102) node _T_1113 = and(_T_1061, _T_1112) node _T_1114 = or(UInt<1>(0h0), _T_1113) node _T_1115 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1116 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1117 = and(_T_1115, _T_1116) node _T_1118 = or(UInt<1>(0h0), _T_1117) node _T_1119 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1120 = cvt(_T_1119) node _T_1121 = and(_T_1120, asSInt(UInt<15>(0h5000))) node _T_1122 = asSInt(_T_1121) node _T_1123 = eq(_T_1122, asSInt(UInt<1>(0h0))) node _T_1124 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1125 = cvt(_T_1124) node _T_1126 = and(_T_1125, asSInt(UInt<13>(0h1000))) node _T_1127 = asSInt(_T_1126) node _T_1128 = eq(_T_1127, asSInt(UInt<1>(0h0))) node _T_1129 = or(_T_1123, _T_1128) node _T_1130 = and(_T_1118, _T_1129) node _T_1131 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1132 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1133 = cvt(_T_1132) node _T_1134 = and(_T_1133, asSInt(UInt<13>(0h1000))) node _T_1135 = asSInt(_T_1134) node _T_1136 = eq(_T_1135, asSInt(UInt<1>(0h0))) node _T_1137 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1138 = cvt(_T_1137) node _T_1139 = and(_T_1138, asSInt(UInt<17>(0h10000))) node _T_1140 = asSInt(_T_1139) node _T_1141 = eq(_T_1140, asSInt(UInt<1>(0h0))) node _T_1142 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1143 = cvt(_T_1142) node _T_1144 = and(_T_1143, asSInt(UInt<18>(0h2f000))) node _T_1145 = asSInt(_T_1144) node _T_1146 = eq(_T_1145, asSInt(UInt<1>(0h0))) node _T_1147 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1148 = cvt(_T_1147) node _T_1149 = and(_T_1148, asSInt(UInt<17>(0h10000))) node _T_1150 = asSInt(_T_1149) node _T_1151 = eq(_T_1150, asSInt(UInt<1>(0h0))) node _T_1152 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1153 = cvt(_T_1152) node _T_1154 = and(_T_1153, asSInt(UInt<13>(0h1000))) node _T_1155 = asSInt(_T_1154) node _T_1156 = eq(_T_1155, asSInt(UInt<1>(0h0))) node _T_1157 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1158 = cvt(_T_1157) node _T_1159 = and(_T_1158, asSInt(UInt<27>(0h4000000))) node _T_1160 = asSInt(_T_1159) node _T_1161 = eq(_T_1160, asSInt(UInt<1>(0h0))) node _T_1162 = or(_T_1136, _T_1141) node _T_1163 = or(_T_1162, _T_1146) node _T_1164 = or(_T_1163, _T_1151) node _T_1165 = or(_T_1164, _T_1156) node _T_1166 = or(_T_1165, _T_1161) node _T_1167 = and(_T_1131, _T_1166) node _T_1168 = or(UInt<1>(0h0), _T_1130) node _T_1169 = or(_T_1168, _T_1167) node _T_1170 = and(_T_1114, _T_1169) node _T_1171 = asUInt(reset) node _T_1172 = eq(_T_1171, UInt<1>(0h0)) when _T_1172 : node _T_1173 = eq(_T_1170, UInt<1>(0h0)) when _T_1173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1170, UInt<1>(0h1), "") : assert_36 node _T_1174 = asUInt(reset) node _T_1175 = eq(_T_1174, UInt<1>(0h0)) when _T_1175 : node _T_1176 = eq(source_ok, UInt<1>(0h0)) when _T_1176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(is_aligned, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1180 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_39 node _T_1184 = eq(io.in.a.bits.mask, mask) node _T_1185 = asUInt(reset) node _T_1186 = eq(_T_1185, UInt<1>(0h0)) when _T_1186 : node _T_1187 = eq(_T_1184, UInt<1>(0h0)) when _T_1187 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1184, UInt<1>(0h1), "") : assert_40 node _T_1188 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1188 : node _T_1189 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1190 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1191 = and(_T_1189, _T_1190) node _T_1192 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0) node _T_1193 = shr(io.in.a.bits.source, 2) node _T_1194 = eq(_T_1193, UInt<5>(0h10)) node _T_1195 = leq(UInt<1>(0h0), uncommonBits_54) node _T_1196 = and(_T_1194, _T_1195) node _T_1197 = leq(uncommonBits_54, UInt<2>(0h3)) node _T_1198 = and(_T_1196, _T_1197) node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 1, 0) node _T_1199 = shr(io.in.a.bits.source, 2) node _T_1200 = eq(_T_1199, UInt<5>(0h11)) node _T_1201 = leq(UInt<1>(0h0), uncommonBits_55) node _T_1202 = and(_T_1200, _T_1201) node _T_1203 = leq(uncommonBits_55, UInt<2>(0h3)) node _T_1204 = and(_T_1202, _T_1203) node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0) node _T_1205 = shr(io.in.a.bits.source, 2) node _T_1206 = eq(_T_1205, UInt<5>(0h12)) node _T_1207 = leq(UInt<1>(0h0), uncommonBits_56) node _T_1208 = and(_T_1206, _T_1207) node _T_1209 = leq(uncommonBits_56, UInt<2>(0h3)) node _T_1210 = and(_T_1208, _T_1209) node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0) node _T_1211 = shr(io.in.a.bits.source, 2) node _T_1212 = eq(_T_1211, UInt<5>(0h13)) node _T_1213 = leq(UInt<1>(0h0), uncommonBits_57) node _T_1214 = and(_T_1212, _T_1213) node _T_1215 = leq(uncommonBits_57, UInt<2>(0h3)) node _T_1216 = and(_T_1214, _T_1215) node _T_1217 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1218 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 3, 0) node _T_1219 = shr(io.in.a.bits.source, 4) node _T_1220 = eq(_T_1219, UInt<1>(0h1)) node _T_1221 = leq(UInt<1>(0h0), uncommonBits_58) node _T_1222 = and(_T_1220, _T_1221) node _T_1223 = leq(uncommonBits_58, UInt<4>(0hf)) node _T_1224 = and(_T_1222, _T_1223) node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 3, 0) node _T_1225 = shr(io.in.a.bits.source, 4) node _T_1226 = eq(_T_1225, UInt<1>(0h0)) node _T_1227 = leq(UInt<1>(0h0), uncommonBits_59) node _T_1228 = and(_T_1226, _T_1227) node _T_1229 = leq(uncommonBits_59, UInt<4>(0hf)) node _T_1230 = and(_T_1228, _T_1229) node _T_1231 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1232 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1233 = or(_T_1192, _T_1198) node _T_1234 = or(_T_1233, _T_1204) node _T_1235 = or(_T_1234, _T_1210) node _T_1236 = or(_T_1235, _T_1216) node _T_1237 = or(_T_1236, _T_1217) node _T_1238 = or(_T_1237, _T_1218) node _T_1239 = or(_T_1238, _T_1224) node _T_1240 = or(_T_1239, _T_1230) node _T_1241 = or(_T_1240, _T_1231) node _T_1242 = or(_T_1241, _T_1232) node _T_1243 = and(_T_1191, _T_1242) node _T_1244 = or(UInt<1>(0h0), _T_1243) node _T_1245 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1246 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1247 = and(_T_1245, _T_1246) node _T_1248 = or(UInt<1>(0h0), _T_1247) node _T_1249 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1250 = cvt(_T_1249) node _T_1251 = and(_T_1250, asSInt(UInt<15>(0h5000))) node _T_1252 = asSInt(_T_1251) node _T_1253 = eq(_T_1252, asSInt(UInt<1>(0h0))) node _T_1254 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1255 = cvt(_T_1254) node _T_1256 = and(_T_1255, asSInt(UInt<13>(0h1000))) node _T_1257 = asSInt(_T_1256) node _T_1258 = eq(_T_1257, asSInt(UInt<1>(0h0))) node _T_1259 = or(_T_1253, _T_1258) node _T_1260 = and(_T_1248, _T_1259) node _T_1261 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1262 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1263 = cvt(_T_1262) node _T_1264 = and(_T_1263, asSInt(UInt<13>(0h1000))) node _T_1265 = asSInt(_T_1264) node _T_1266 = eq(_T_1265, asSInt(UInt<1>(0h0))) node _T_1267 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1268 = cvt(_T_1267) node _T_1269 = and(_T_1268, asSInt(UInt<17>(0h10000))) node _T_1270 = asSInt(_T_1269) node _T_1271 = eq(_T_1270, asSInt(UInt<1>(0h0))) node _T_1272 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1273 = cvt(_T_1272) node _T_1274 = and(_T_1273, asSInt(UInt<18>(0h2f000))) node _T_1275 = asSInt(_T_1274) node _T_1276 = eq(_T_1275, asSInt(UInt<1>(0h0))) node _T_1277 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1278 = cvt(_T_1277) node _T_1279 = and(_T_1278, asSInt(UInt<17>(0h10000))) node _T_1280 = asSInt(_T_1279) node _T_1281 = eq(_T_1280, asSInt(UInt<1>(0h0))) node _T_1282 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1283 = cvt(_T_1282) node _T_1284 = and(_T_1283, asSInt(UInt<13>(0h1000))) node _T_1285 = asSInt(_T_1284) node _T_1286 = eq(_T_1285, asSInt(UInt<1>(0h0))) node _T_1287 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1288 = cvt(_T_1287) node _T_1289 = and(_T_1288, asSInt(UInt<27>(0h4000000))) node _T_1290 = asSInt(_T_1289) node _T_1291 = eq(_T_1290, asSInt(UInt<1>(0h0))) node _T_1292 = or(_T_1266, _T_1271) node _T_1293 = or(_T_1292, _T_1276) node _T_1294 = or(_T_1293, _T_1281) node _T_1295 = or(_T_1294, _T_1286) node _T_1296 = or(_T_1295, _T_1291) node _T_1297 = and(_T_1261, _T_1296) node _T_1298 = or(UInt<1>(0h0), _T_1260) node _T_1299 = or(_T_1298, _T_1297) node _T_1300 = and(_T_1244, _T_1299) node _T_1301 = asUInt(reset) node _T_1302 = eq(_T_1301, UInt<1>(0h0)) when _T_1302 : node _T_1303 = eq(_T_1300, UInt<1>(0h0)) when _T_1303 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1300, UInt<1>(0h1), "") : assert_41 node _T_1304 = asUInt(reset) node _T_1305 = eq(_T_1304, UInt<1>(0h0)) when _T_1305 : node _T_1306 = eq(source_ok, UInt<1>(0h0)) when _T_1306 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1307 = asUInt(reset) node _T_1308 = eq(_T_1307, UInt<1>(0h0)) when _T_1308 : node _T_1309 = eq(is_aligned, UInt<1>(0h0)) when _T_1309 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1310 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1311 = asUInt(reset) node _T_1312 = eq(_T_1311, UInt<1>(0h0)) when _T_1312 : node _T_1313 = eq(_T_1310, UInt<1>(0h0)) when _T_1313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1310, UInt<1>(0h1), "") : assert_44 node _T_1314 = eq(io.in.a.bits.mask, mask) node _T_1315 = asUInt(reset) node _T_1316 = eq(_T_1315, UInt<1>(0h0)) when _T_1316 : node _T_1317 = eq(_T_1314, UInt<1>(0h0)) when _T_1317 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1314, UInt<1>(0h1), "") : assert_45 node _T_1318 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1318 : node _T_1319 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1320 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1321 = and(_T_1319, _T_1320) node _T_1322 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0) node _T_1323 = shr(io.in.a.bits.source, 2) node _T_1324 = eq(_T_1323, UInt<5>(0h10)) node _T_1325 = leq(UInt<1>(0h0), uncommonBits_60) node _T_1326 = and(_T_1324, _T_1325) node _T_1327 = leq(uncommonBits_60, UInt<2>(0h3)) node _T_1328 = and(_T_1326, _T_1327) node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0) node _T_1329 = shr(io.in.a.bits.source, 2) node _T_1330 = eq(_T_1329, UInt<5>(0h11)) node _T_1331 = leq(UInt<1>(0h0), uncommonBits_61) node _T_1332 = and(_T_1330, _T_1331) node _T_1333 = leq(uncommonBits_61, UInt<2>(0h3)) node _T_1334 = and(_T_1332, _T_1333) node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0) node _T_1335 = shr(io.in.a.bits.source, 2) node _T_1336 = eq(_T_1335, UInt<5>(0h12)) node _T_1337 = leq(UInt<1>(0h0), uncommonBits_62) node _T_1338 = and(_T_1336, _T_1337) node _T_1339 = leq(uncommonBits_62, UInt<2>(0h3)) node _T_1340 = and(_T_1338, _T_1339) node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0) node _T_1341 = shr(io.in.a.bits.source, 2) node _T_1342 = eq(_T_1341, UInt<5>(0h13)) node _T_1343 = leq(UInt<1>(0h0), uncommonBits_63) node _T_1344 = and(_T_1342, _T_1343) node _T_1345 = leq(uncommonBits_63, UInt<2>(0h3)) node _T_1346 = and(_T_1344, _T_1345) node _T_1347 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1348 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 3, 0) node _T_1349 = shr(io.in.a.bits.source, 4) node _T_1350 = eq(_T_1349, UInt<1>(0h1)) node _T_1351 = leq(UInt<1>(0h0), uncommonBits_64) node _T_1352 = and(_T_1350, _T_1351) node _T_1353 = leq(uncommonBits_64, UInt<4>(0hf)) node _T_1354 = and(_T_1352, _T_1353) node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 3, 0) node _T_1355 = shr(io.in.a.bits.source, 4) node _T_1356 = eq(_T_1355, UInt<1>(0h0)) node _T_1357 = leq(UInt<1>(0h0), uncommonBits_65) node _T_1358 = and(_T_1356, _T_1357) node _T_1359 = leq(uncommonBits_65, UInt<4>(0hf)) node _T_1360 = and(_T_1358, _T_1359) node _T_1361 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1362 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1363 = or(_T_1322, _T_1328) node _T_1364 = or(_T_1363, _T_1334) node _T_1365 = or(_T_1364, _T_1340) node _T_1366 = or(_T_1365, _T_1346) node _T_1367 = or(_T_1366, _T_1347) node _T_1368 = or(_T_1367, _T_1348) node _T_1369 = or(_T_1368, _T_1354) node _T_1370 = or(_T_1369, _T_1360) node _T_1371 = or(_T_1370, _T_1361) node _T_1372 = or(_T_1371, _T_1362) node _T_1373 = and(_T_1321, _T_1372) node _T_1374 = or(UInt<1>(0h0), _T_1373) node _T_1375 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1376 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1377 = and(_T_1375, _T_1376) node _T_1378 = or(UInt<1>(0h0), _T_1377) node _T_1379 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1380 = cvt(_T_1379) node _T_1381 = and(_T_1380, asSInt(UInt<13>(0h1000))) node _T_1382 = asSInt(_T_1381) node _T_1383 = eq(_T_1382, asSInt(UInt<1>(0h0))) node _T_1384 = and(_T_1378, _T_1383) node _T_1385 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1386 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1387 = cvt(_T_1386) node _T_1388 = and(_T_1387, asSInt(UInt<14>(0h2000))) node _T_1389 = asSInt(_T_1388) node _T_1390 = eq(_T_1389, asSInt(UInt<1>(0h0))) node _T_1391 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1392 = cvt(_T_1391) node _T_1393 = and(_T_1392, asSInt(UInt<17>(0h10000))) node _T_1394 = asSInt(_T_1393) node _T_1395 = eq(_T_1394, asSInt(UInt<1>(0h0))) node _T_1396 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1397 = cvt(_T_1396) node _T_1398 = and(_T_1397, asSInt(UInt<18>(0h2f000))) node _T_1399 = asSInt(_T_1398) node _T_1400 = eq(_T_1399, asSInt(UInt<1>(0h0))) node _T_1401 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1402 = cvt(_T_1401) node _T_1403 = and(_T_1402, asSInt(UInt<17>(0h10000))) node _T_1404 = asSInt(_T_1403) node _T_1405 = eq(_T_1404, asSInt(UInt<1>(0h0))) node _T_1406 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1407 = cvt(_T_1406) node _T_1408 = and(_T_1407, asSInt(UInt<13>(0h1000))) node _T_1409 = asSInt(_T_1408) node _T_1410 = eq(_T_1409, asSInt(UInt<1>(0h0))) node _T_1411 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1412 = cvt(_T_1411) node _T_1413 = and(_T_1412, asSInt(UInt<27>(0h4000000))) node _T_1414 = asSInt(_T_1413) node _T_1415 = eq(_T_1414, asSInt(UInt<1>(0h0))) node _T_1416 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1417 = cvt(_T_1416) node _T_1418 = and(_T_1417, asSInt(UInt<13>(0h1000))) node _T_1419 = asSInt(_T_1418) node _T_1420 = eq(_T_1419, asSInt(UInt<1>(0h0))) node _T_1421 = or(_T_1390, _T_1395) node _T_1422 = or(_T_1421, _T_1400) node _T_1423 = or(_T_1422, _T_1405) node _T_1424 = or(_T_1423, _T_1410) node _T_1425 = or(_T_1424, _T_1415) node _T_1426 = or(_T_1425, _T_1420) node _T_1427 = and(_T_1385, _T_1426) node _T_1428 = or(UInt<1>(0h0), _T_1384) node _T_1429 = or(_T_1428, _T_1427) node _T_1430 = and(_T_1374, _T_1429) node _T_1431 = asUInt(reset) node _T_1432 = eq(_T_1431, UInt<1>(0h0)) when _T_1432 : node _T_1433 = eq(_T_1430, UInt<1>(0h0)) when _T_1433 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1430, UInt<1>(0h1), "") : assert_46 node _T_1434 = asUInt(reset) node _T_1435 = eq(_T_1434, UInt<1>(0h0)) when _T_1435 : node _T_1436 = eq(source_ok, UInt<1>(0h0)) when _T_1436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1437 = asUInt(reset) node _T_1438 = eq(_T_1437, UInt<1>(0h0)) when _T_1438 : node _T_1439 = eq(is_aligned, UInt<1>(0h0)) when _T_1439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1440 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1441 = asUInt(reset) node _T_1442 = eq(_T_1441, UInt<1>(0h0)) when _T_1442 : node _T_1443 = eq(_T_1440, UInt<1>(0h0)) when _T_1443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1440, UInt<1>(0h1), "") : assert_49 node _T_1444 = eq(io.in.a.bits.mask, mask) node _T_1445 = asUInt(reset) node _T_1446 = eq(_T_1445, UInt<1>(0h0)) when _T_1446 : node _T_1447 = eq(_T_1444, UInt<1>(0h0)) when _T_1447 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1444, UInt<1>(0h1), "") : assert_50 node _T_1448 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1449 = asUInt(reset) node _T_1450 = eq(_T_1449, UInt<1>(0h0)) when _T_1450 : node _T_1451 = eq(_T_1448, UInt<1>(0h0)) when _T_1451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1448, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1452 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1453 = asUInt(reset) node _T_1454 = eq(_T_1453, UInt<1>(0h0)) when _T_1454 : node _T_1455 = eq(_T_1452, UInt<1>(0h0)) when _T_1455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1452, UInt<1>(0h1), "") : assert_52 node _source_ok_T_50 = eq(io.in.d.bits.source, UInt<7>(0h50)) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_51 = shr(io.in.d.bits.source, 2) node _source_ok_T_52 = eq(_source_ok_T_51, UInt<5>(0h10)) node _source_ok_T_53 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_T_55 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_57 = shr(io.in.d.bits.source, 2) node _source_ok_T_58 = eq(_source_ok_T_57, UInt<5>(0h11)) node _source_ok_T_59 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_T_61 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_62 = and(_source_ok_T_60, _source_ok_T_61) node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_63 = shr(io.in.d.bits.source, 2) node _source_ok_T_64 = eq(_source_ok_T_63, UInt<5>(0h12)) node _source_ok_T_65 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_66 = and(_source_ok_T_64, _source_ok_T_65) node _source_ok_T_67 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_68 = and(_source_ok_T_66, _source_ok_T_67) node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0) node _source_ok_T_69 = shr(io.in.d.bits.source, 2) node _source_ok_T_70 = eq(_source_ok_T_69, UInt<5>(0h13)) node _source_ok_T_71 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_72 = and(_source_ok_T_70, _source_ok_T_71) node _source_ok_T_73 = leq(source_ok_uncommonBits_9, UInt<2>(0h3)) node _source_ok_T_74 = and(_source_ok_T_72, _source_ok_T_73) node _source_ok_T_75 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_76 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 3, 0) node _source_ok_T_77 = shr(io.in.d.bits.source, 4) node _source_ok_T_78 = eq(_source_ok_T_77, UInt<1>(0h1)) node _source_ok_T_79 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_80 = and(_source_ok_T_78, _source_ok_T_79) node _source_ok_T_81 = leq(source_ok_uncommonBits_10, UInt<4>(0hf)) node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81) node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 3, 0) node _source_ok_T_83 = shr(io.in.d.bits.source, 4) node _source_ok_T_84 = eq(_source_ok_T_83, UInt<1>(0h0)) node _source_ok_T_85 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_86 = and(_source_ok_T_84, _source_ok_T_85) node _source_ok_T_87 = leq(source_ok_uncommonBits_11, UInt<4>(0hf)) node _source_ok_T_88 = and(_source_ok_T_86, _source_ok_T_87) node _source_ok_T_89 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_90 = eq(io.in.d.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE_1 : UInt<1>[11] connect _source_ok_WIRE_1[0], _source_ok_T_50 connect _source_ok_WIRE_1[1], _source_ok_T_56 connect _source_ok_WIRE_1[2], _source_ok_T_62 connect _source_ok_WIRE_1[3], _source_ok_T_68 connect _source_ok_WIRE_1[4], _source_ok_T_74 connect _source_ok_WIRE_1[5], _source_ok_T_75 connect _source_ok_WIRE_1[6], _source_ok_T_76 connect _source_ok_WIRE_1[7], _source_ok_T_82 connect _source_ok_WIRE_1[8], _source_ok_T_88 connect _source_ok_WIRE_1[9], _source_ok_T_89 connect _source_ok_WIRE_1[10], _source_ok_T_90 node _source_ok_T_91 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_92 = or(_source_ok_T_91, _source_ok_WIRE_1[2]) node _source_ok_T_93 = or(_source_ok_T_92, _source_ok_WIRE_1[3]) node _source_ok_T_94 = or(_source_ok_T_93, _source_ok_WIRE_1[4]) node _source_ok_T_95 = or(_source_ok_T_94, _source_ok_WIRE_1[5]) node _source_ok_T_96 = or(_source_ok_T_95, _source_ok_WIRE_1[6]) node _source_ok_T_97 = or(_source_ok_T_96, _source_ok_WIRE_1[7]) node _source_ok_T_98 = or(_source_ok_T_97, _source_ok_WIRE_1[8]) node _source_ok_T_99 = or(_source_ok_T_98, _source_ok_WIRE_1[9]) node source_ok_1 = or(_source_ok_T_99, _source_ok_WIRE_1[10]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1456 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1456 : node _T_1457 = asUInt(reset) node _T_1458 = eq(_T_1457, UInt<1>(0h0)) when _T_1458 : node _T_1459 = eq(source_ok_1, UInt<1>(0h0)) when _T_1459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1460 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1461 = asUInt(reset) node _T_1462 = eq(_T_1461, UInt<1>(0h0)) when _T_1462 : node _T_1463 = eq(_T_1460, UInt<1>(0h0)) when _T_1463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1460, UInt<1>(0h1), "") : assert_54 node _T_1464 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1465 = asUInt(reset) node _T_1466 = eq(_T_1465, UInt<1>(0h0)) when _T_1466 : node _T_1467 = eq(_T_1464, UInt<1>(0h0)) when _T_1467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1464, UInt<1>(0h1), "") : assert_55 node _T_1468 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1469 = asUInt(reset) node _T_1470 = eq(_T_1469, UInt<1>(0h0)) when _T_1470 : node _T_1471 = eq(_T_1468, UInt<1>(0h0)) when _T_1471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1468, UInt<1>(0h1), "") : assert_56 node _T_1472 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1473 = asUInt(reset) node _T_1474 = eq(_T_1473, UInt<1>(0h0)) when _T_1474 : node _T_1475 = eq(_T_1472, UInt<1>(0h0)) when _T_1475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1472, UInt<1>(0h1), "") : assert_57 node _T_1476 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1476 : node _T_1477 = asUInt(reset) node _T_1478 = eq(_T_1477, UInt<1>(0h0)) when _T_1478 : node _T_1479 = eq(source_ok_1, UInt<1>(0h0)) when _T_1479 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1480 = asUInt(reset) node _T_1481 = eq(_T_1480, UInt<1>(0h0)) when _T_1481 : node _T_1482 = eq(sink_ok, UInt<1>(0h0)) when _T_1482 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1483 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1484 = asUInt(reset) node _T_1485 = eq(_T_1484, UInt<1>(0h0)) when _T_1485 : node _T_1486 = eq(_T_1483, UInt<1>(0h0)) when _T_1486 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1483, UInt<1>(0h1), "") : assert_60 node _T_1487 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1488 = asUInt(reset) node _T_1489 = eq(_T_1488, UInt<1>(0h0)) when _T_1489 : node _T_1490 = eq(_T_1487, UInt<1>(0h0)) when _T_1490 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1487, UInt<1>(0h1), "") : assert_61 node _T_1491 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1492 = asUInt(reset) node _T_1493 = eq(_T_1492, UInt<1>(0h0)) when _T_1493 : node _T_1494 = eq(_T_1491, UInt<1>(0h0)) when _T_1494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1491, UInt<1>(0h1), "") : assert_62 node _T_1495 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1496 = asUInt(reset) node _T_1497 = eq(_T_1496, UInt<1>(0h0)) when _T_1497 : node _T_1498 = eq(_T_1495, UInt<1>(0h0)) when _T_1498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1495, UInt<1>(0h1), "") : assert_63 node _T_1499 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1500 = or(UInt<1>(0h1), _T_1499) node _T_1501 = asUInt(reset) node _T_1502 = eq(_T_1501, UInt<1>(0h0)) when _T_1502 : node _T_1503 = eq(_T_1500, UInt<1>(0h0)) when _T_1503 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1500, UInt<1>(0h1), "") : assert_64 node _T_1504 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1504 : node _T_1505 = asUInt(reset) node _T_1506 = eq(_T_1505, UInt<1>(0h0)) when _T_1506 : node _T_1507 = eq(source_ok_1, UInt<1>(0h0)) when _T_1507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1508 = asUInt(reset) node _T_1509 = eq(_T_1508, UInt<1>(0h0)) when _T_1509 : node _T_1510 = eq(sink_ok, UInt<1>(0h0)) when _T_1510 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1511 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1512 = asUInt(reset) node _T_1513 = eq(_T_1512, UInt<1>(0h0)) when _T_1513 : node _T_1514 = eq(_T_1511, UInt<1>(0h0)) when _T_1514 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1511, UInt<1>(0h1), "") : assert_67 node _T_1515 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1516 = asUInt(reset) node _T_1517 = eq(_T_1516, UInt<1>(0h0)) when _T_1517 : node _T_1518 = eq(_T_1515, UInt<1>(0h0)) when _T_1518 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1515, UInt<1>(0h1), "") : assert_68 node _T_1519 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1520 = asUInt(reset) node _T_1521 = eq(_T_1520, UInt<1>(0h0)) when _T_1521 : node _T_1522 = eq(_T_1519, UInt<1>(0h0)) when _T_1522 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1519, UInt<1>(0h1), "") : assert_69 node _T_1523 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1524 = or(_T_1523, io.in.d.bits.corrupt) node _T_1525 = asUInt(reset) node _T_1526 = eq(_T_1525, UInt<1>(0h0)) when _T_1526 : node _T_1527 = eq(_T_1524, UInt<1>(0h0)) when _T_1527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1524, UInt<1>(0h1), "") : assert_70 node _T_1528 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1529 = or(UInt<1>(0h1), _T_1528) node _T_1530 = asUInt(reset) node _T_1531 = eq(_T_1530, UInt<1>(0h0)) when _T_1531 : node _T_1532 = eq(_T_1529, UInt<1>(0h0)) when _T_1532 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1529, UInt<1>(0h1), "") : assert_71 node _T_1533 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1533 : node _T_1534 = asUInt(reset) node _T_1535 = eq(_T_1534, UInt<1>(0h0)) when _T_1535 : node _T_1536 = eq(source_ok_1, UInt<1>(0h0)) when _T_1536 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1537 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1538 = asUInt(reset) node _T_1539 = eq(_T_1538, UInt<1>(0h0)) when _T_1539 : node _T_1540 = eq(_T_1537, UInt<1>(0h0)) when _T_1540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1537, UInt<1>(0h1), "") : assert_73 node _T_1541 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1542 = asUInt(reset) node _T_1543 = eq(_T_1542, UInt<1>(0h0)) when _T_1543 : node _T_1544 = eq(_T_1541, UInt<1>(0h0)) when _T_1544 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1541, UInt<1>(0h1), "") : assert_74 node _T_1545 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1546 = or(UInt<1>(0h1), _T_1545) node _T_1547 = asUInt(reset) node _T_1548 = eq(_T_1547, UInt<1>(0h0)) when _T_1548 : node _T_1549 = eq(_T_1546, UInt<1>(0h0)) when _T_1549 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1546, UInt<1>(0h1), "") : assert_75 node _T_1550 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1550 : node _T_1551 = asUInt(reset) node _T_1552 = eq(_T_1551, UInt<1>(0h0)) when _T_1552 : node _T_1553 = eq(source_ok_1, UInt<1>(0h0)) when _T_1553 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1554 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1555 = asUInt(reset) node _T_1556 = eq(_T_1555, UInt<1>(0h0)) when _T_1556 : node _T_1557 = eq(_T_1554, UInt<1>(0h0)) when _T_1557 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1554, UInt<1>(0h1), "") : assert_77 node _T_1558 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1559 = or(_T_1558, io.in.d.bits.corrupt) node _T_1560 = asUInt(reset) node _T_1561 = eq(_T_1560, UInt<1>(0h0)) when _T_1561 : node _T_1562 = eq(_T_1559, UInt<1>(0h0)) when _T_1562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1559, UInt<1>(0h1), "") : assert_78 node _T_1563 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1564 = or(UInt<1>(0h1), _T_1563) node _T_1565 = asUInt(reset) node _T_1566 = eq(_T_1565, UInt<1>(0h0)) when _T_1566 : node _T_1567 = eq(_T_1564, UInt<1>(0h0)) when _T_1567 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1564, UInt<1>(0h1), "") : assert_79 node _T_1568 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1568 : node _T_1569 = asUInt(reset) node _T_1570 = eq(_T_1569, UInt<1>(0h0)) when _T_1570 : node _T_1571 = eq(source_ok_1, UInt<1>(0h0)) when _T_1571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1572 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1573 = asUInt(reset) node _T_1574 = eq(_T_1573, UInt<1>(0h0)) when _T_1574 : node _T_1575 = eq(_T_1572, UInt<1>(0h0)) when _T_1575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1572, UInt<1>(0h1), "") : assert_81 node _T_1576 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1577 = asUInt(reset) node _T_1578 = eq(_T_1577, UInt<1>(0h0)) when _T_1578 : node _T_1579 = eq(_T_1576, UInt<1>(0h0)) when _T_1579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1576, UInt<1>(0h1), "") : assert_82 node _T_1580 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1581 = or(UInt<1>(0h1), _T_1580) node _T_1582 = asUInt(reset) node _T_1583 = eq(_T_1582, UInt<1>(0h0)) when _T_1583 : node _T_1584 = eq(_T_1581, UInt<1>(0h0)) when _T_1584 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1581, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<29>(0h0) connect _WIRE_4.bits.source, UInt<8>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1585 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1586 = asUInt(reset) node _T_1587 = eq(_T_1586, UInt<1>(0h0)) when _T_1587 : node _T_1588 = eq(_T_1585, UInt<1>(0h0)) when _T_1588 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1585, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<8>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1589 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1590 = asUInt(reset) node _T_1591 = eq(_T_1590, UInt<1>(0h0)) when _T_1591 : node _T_1592 = eq(_T_1589, UInt<1>(0h0)) when _T_1592 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1589, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1593 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1594 = asUInt(reset) node _T_1595 = eq(_T_1594, UInt<1>(0h0)) when _T_1595 : node _T_1596 = eq(_T_1593, UInt<1>(0h0)) when _T_1596 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1593, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1597 = eq(a_first, UInt<1>(0h0)) node _T_1598 = and(io.in.a.valid, _T_1597) when _T_1598 : node _T_1599 = eq(io.in.a.bits.opcode, opcode) node _T_1600 = asUInt(reset) node _T_1601 = eq(_T_1600, UInt<1>(0h0)) when _T_1601 : node _T_1602 = eq(_T_1599, UInt<1>(0h0)) when _T_1602 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1599, UInt<1>(0h1), "") : assert_87 node _T_1603 = eq(io.in.a.bits.param, param) node _T_1604 = asUInt(reset) node _T_1605 = eq(_T_1604, UInt<1>(0h0)) when _T_1605 : node _T_1606 = eq(_T_1603, UInt<1>(0h0)) when _T_1606 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1603, UInt<1>(0h1), "") : assert_88 node _T_1607 = eq(io.in.a.bits.size, size) node _T_1608 = asUInt(reset) node _T_1609 = eq(_T_1608, UInt<1>(0h0)) when _T_1609 : node _T_1610 = eq(_T_1607, UInt<1>(0h0)) when _T_1610 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1607, UInt<1>(0h1), "") : assert_89 node _T_1611 = eq(io.in.a.bits.source, source) node _T_1612 = asUInt(reset) node _T_1613 = eq(_T_1612, UInt<1>(0h0)) when _T_1613 : node _T_1614 = eq(_T_1611, UInt<1>(0h0)) when _T_1614 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1611, UInt<1>(0h1), "") : assert_90 node _T_1615 = eq(io.in.a.bits.address, address) node _T_1616 = asUInt(reset) node _T_1617 = eq(_T_1616, UInt<1>(0h0)) when _T_1617 : node _T_1618 = eq(_T_1615, UInt<1>(0h0)) when _T_1618 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1615, UInt<1>(0h1), "") : assert_91 node _T_1619 = and(io.in.a.ready, io.in.a.valid) node _T_1620 = and(_T_1619, a_first) when _T_1620 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1621 = eq(d_first, UInt<1>(0h0)) node _T_1622 = and(io.in.d.valid, _T_1621) when _T_1622 : node _T_1623 = eq(io.in.d.bits.opcode, opcode_1) node _T_1624 = asUInt(reset) node _T_1625 = eq(_T_1624, UInt<1>(0h0)) when _T_1625 : node _T_1626 = eq(_T_1623, UInt<1>(0h0)) when _T_1626 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1623, UInt<1>(0h1), "") : assert_92 node _T_1627 = eq(io.in.d.bits.param, param_1) node _T_1628 = asUInt(reset) node _T_1629 = eq(_T_1628, UInt<1>(0h0)) when _T_1629 : node _T_1630 = eq(_T_1627, UInt<1>(0h0)) when _T_1630 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1627, UInt<1>(0h1), "") : assert_93 node _T_1631 = eq(io.in.d.bits.size, size_1) node _T_1632 = asUInt(reset) node _T_1633 = eq(_T_1632, UInt<1>(0h0)) when _T_1633 : node _T_1634 = eq(_T_1631, UInt<1>(0h0)) when _T_1634 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1631, UInt<1>(0h1), "") : assert_94 node _T_1635 = eq(io.in.d.bits.source, source_1) node _T_1636 = asUInt(reset) node _T_1637 = eq(_T_1636, UInt<1>(0h0)) when _T_1637 : node _T_1638 = eq(_T_1635, UInt<1>(0h0)) when _T_1638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1635, UInt<1>(0h1), "") : assert_95 node _T_1639 = eq(io.in.d.bits.sink, sink) node _T_1640 = asUInt(reset) node _T_1641 = eq(_T_1640, UInt<1>(0h0)) when _T_1641 : node _T_1642 = eq(_T_1639, UInt<1>(0h0)) when _T_1642 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1639, UInt<1>(0h1), "") : assert_96 node _T_1643 = eq(io.in.d.bits.denied, denied) node _T_1644 = asUInt(reset) node _T_1645 = eq(_T_1644, UInt<1>(0h0)) when _T_1645 : node _T_1646 = eq(_T_1643, UInt<1>(0h0)) when _T_1646 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1643, UInt<1>(0h1), "") : assert_97 node _T_1647 = and(io.in.d.ready, io.in.d.valid) node _T_1648 = and(_T_1647, d_first) when _T_1648 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes : UInt<1032>, clock, reset, UInt<1032>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<129> connect a_set, UInt<129>(0h0) wire a_set_wo_ready : UInt<129> connect a_set_wo_ready, UInt<129>(0h0) wire a_opcodes_set : UInt<516> connect a_opcodes_set, UInt<516>(0h0) wire a_sizes_set : UInt<1032> connect a_sizes_set, UInt<1032>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1649 = and(io.in.a.valid, a_first_1) node _T_1650 = and(_T_1649, UInt<1>(0h1)) when _T_1650 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1651 = and(io.in.a.ready, io.in.a.valid) node _T_1652 = and(_T_1651, a_first_1) node _T_1653 = and(_T_1652, UInt<1>(0h1)) when _T_1653 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1654 = dshr(inflight, io.in.a.bits.source) node _T_1655 = bits(_T_1654, 0, 0) node _T_1656 = eq(_T_1655, UInt<1>(0h0)) node _T_1657 = asUInt(reset) node _T_1658 = eq(_T_1657, UInt<1>(0h0)) when _T_1658 : node _T_1659 = eq(_T_1656, UInt<1>(0h0)) when _T_1659 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1656, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<129> connect d_clr, UInt<129>(0h0) wire d_clr_wo_ready : UInt<129> connect d_clr_wo_ready, UInt<129>(0h0) wire d_opcodes_clr : UInt<516> connect d_opcodes_clr, UInt<516>(0h0) wire d_sizes_clr : UInt<1032> connect d_sizes_clr, UInt<1032>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1660 = and(io.in.d.valid, d_first_1) node _T_1661 = and(_T_1660, UInt<1>(0h1)) node _T_1662 = eq(d_release_ack, UInt<1>(0h0)) node _T_1663 = and(_T_1661, _T_1662) when _T_1663 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1664 = and(io.in.d.ready, io.in.d.valid) node _T_1665 = and(_T_1664, d_first_1) node _T_1666 = and(_T_1665, UInt<1>(0h1)) node _T_1667 = eq(d_release_ack, UInt<1>(0h0)) node _T_1668 = and(_T_1666, _T_1667) when _T_1668 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1669 = and(io.in.d.valid, d_first_1) node _T_1670 = and(_T_1669, UInt<1>(0h1)) node _T_1671 = eq(d_release_ack, UInt<1>(0h0)) node _T_1672 = and(_T_1670, _T_1671) when _T_1672 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1673 = dshr(inflight, io.in.d.bits.source) node _T_1674 = bits(_T_1673, 0, 0) node _T_1675 = or(_T_1674, same_cycle_resp) node _T_1676 = asUInt(reset) node _T_1677 = eq(_T_1676, UInt<1>(0h0)) when _T_1677 : node _T_1678 = eq(_T_1675, UInt<1>(0h0)) when _T_1678 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1675, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1679 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1680 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1681 = or(_T_1679, _T_1680) node _T_1682 = asUInt(reset) node _T_1683 = eq(_T_1682, UInt<1>(0h0)) when _T_1683 : node _T_1684 = eq(_T_1681, UInt<1>(0h0)) when _T_1684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1681, UInt<1>(0h1), "") : assert_100 node _T_1685 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1686 = asUInt(reset) node _T_1687 = eq(_T_1686, UInt<1>(0h0)) when _T_1687 : node _T_1688 = eq(_T_1685, UInt<1>(0h0)) when _T_1688 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1685, UInt<1>(0h1), "") : assert_101 else : node _T_1689 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1690 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1691 = or(_T_1689, _T_1690) node _T_1692 = asUInt(reset) node _T_1693 = eq(_T_1692, UInt<1>(0h0)) when _T_1693 : node _T_1694 = eq(_T_1691, UInt<1>(0h0)) when _T_1694 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1691, UInt<1>(0h1), "") : assert_102 node _T_1695 = eq(io.in.d.bits.size, a_size_lookup) node _T_1696 = asUInt(reset) node _T_1697 = eq(_T_1696, UInt<1>(0h0)) when _T_1697 : node _T_1698 = eq(_T_1695, UInt<1>(0h0)) when _T_1698 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1695, UInt<1>(0h1), "") : assert_103 node _T_1699 = and(io.in.d.valid, d_first_1) node _T_1700 = and(_T_1699, a_first_1) node _T_1701 = and(_T_1700, io.in.a.valid) node _T_1702 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1703 = and(_T_1701, _T_1702) node _T_1704 = eq(d_release_ack, UInt<1>(0h0)) node _T_1705 = and(_T_1703, _T_1704) when _T_1705 : node _T_1706 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1707 = or(_T_1706, io.in.a.ready) node _T_1708 = asUInt(reset) node _T_1709 = eq(_T_1708, UInt<1>(0h0)) when _T_1709 : node _T_1710 = eq(_T_1707, UInt<1>(0h0)) when _T_1710 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1707, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_36 node _T_1711 = orr(inflight) node _T_1712 = eq(_T_1711, UInt<1>(0h0)) node _T_1713 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1714 = or(_T_1712, _T_1713) node _T_1715 = lt(watchdog, plusarg_reader.out) node _T_1716 = or(_T_1714, _T_1715) node _T_1717 = asUInt(reset) node _T_1718 = eq(_T_1717, UInt<1>(0h0)) when _T_1718 : node _T_1719 = eq(_T_1716, UInt<1>(0h0)) when _T_1719 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1716, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1720 = and(io.in.a.ready, io.in.a.valid) node _T_1721 = and(io.in.d.ready, io.in.d.valid) node _T_1722 = or(_T_1720, _T_1721) when _T_1722 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes_1 : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes_1 : UInt<1032>, clock, reset, UInt<1032>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<8>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<8>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<129> connect c_set, UInt<129>(0h0) wire c_set_wo_ready : UInt<129> connect c_set_wo_ready, UInt<129>(0h0) wire c_opcodes_set : UInt<516> connect c_opcodes_set, UInt<516>(0h0) wire c_sizes_set : UInt<1032> connect c_sizes_set, UInt<1032>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<8>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1723 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<8>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1724 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1725 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1726 = and(_T_1724, _T_1725) node _T_1727 = and(_T_1723, _T_1726) when _T_1727 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<8>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1728 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1729 = and(_T_1728, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<8>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1730 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1731 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1732 = and(_T_1730, _T_1731) node _T_1733 = and(_T_1729, _T_1732) when _T_1733 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<8>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<8>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1734 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1735 = bits(_T_1734, 0, 0) node _T_1736 = eq(_T_1735, UInt<1>(0h0)) node _T_1737 = asUInt(reset) node _T_1738 = eq(_T_1737, UInt<1>(0h0)) when _T_1738 : node _T_1739 = eq(_T_1736, UInt<1>(0h0)) when _T_1739 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1736, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<129> connect d_clr_1, UInt<129>(0h0) wire d_clr_wo_ready_1 : UInt<129> connect d_clr_wo_ready_1, UInt<129>(0h0) wire d_opcodes_clr_1 : UInt<516> connect d_opcodes_clr_1, UInt<516>(0h0) wire d_sizes_clr_1 : UInt<1032> connect d_sizes_clr_1, UInt<1032>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1740 = and(io.in.d.valid, d_first_2) node _T_1741 = and(_T_1740, UInt<1>(0h1)) node _T_1742 = and(_T_1741, d_release_ack_1) when _T_1742 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1743 = and(io.in.d.ready, io.in.d.valid) node _T_1744 = and(_T_1743, d_first_2) node _T_1745 = and(_T_1744, UInt<1>(0h1)) node _T_1746 = and(_T_1745, d_release_ack_1) when _T_1746 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1747 = and(io.in.d.valid, d_first_2) node _T_1748 = and(_T_1747, UInt<1>(0h1)) node _T_1749 = and(_T_1748, d_release_ack_1) when _T_1749 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1750 = dshr(inflight_1, io.in.d.bits.source) node _T_1751 = bits(_T_1750, 0, 0) node _T_1752 = or(_T_1751, same_cycle_resp_1) node _T_1753 = asUInt(reset) node _T_1754 = eq(_T_1753, UInt<1>(0h0)) when _T_1754 : node _T_1755 = eq(_T_1752, UInt<1>(0h0)) when _T_1755 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_1752, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<8>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1756 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1757 = asUInt(reset) node _T_1758 = eq(_T_1757, UInt<1>(0h0)) when _T_1758 : node _T_1759 = eq(_T_1756, UInt<1>(0h0)) when _T_1759 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1756, UInt<1>(0h1), "") : assert_108 else : node _T_1760 = eq(io.in.d.bits.size, c_size_lookup) node _T_1761 = asUInt(reset) node _T_1762 = eq(_T_1761, UInt<1>(0h0)) when _T_1762 : node _T_1763 = eq(_T_1760, UInt<1>(0h0)) when _T_1763 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1760, UInt<1>(0h1), "") : assert_109 node _T_1764 = and(io.in.d.valid, d_first_2) node _T_1765 = and(_T_1764, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<8>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1766 = and(_T_1765, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<8>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1767 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1768 = and(_T_1766, _T_1767) node _T_1769 = and(_T_1768, d_release_ack_1) node _T_1770 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1771 = and(_T_1769, _T_1770) when _T_1771 : node _T_1772 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<29>(0h0) connect _WIRE_26.bits.source, UInt<8>(0h0) connect _WIRE_26.bits.size, UInt<4>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1773 = or(_T_1772, _WIRE_27.ready) node _T_1774 = asUInt(reset) node _T_1775 = eq(_T_1774, UInt<1>(0h0)) when _T_1775 : node _T_1776 = eq(_T_1773, UInt<1>(0h0)) when _T_1776 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1773, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_37 node _T_1777 = orr(inflight_1) node _T_1778 = eq(_T_1777, UInt<1>(0h0)) node _T_1779 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1780 = or(_T_1778, _T_1779) node _T_1781 = lt(watchdog_1, plusarg_reader_1.out) node _T_1782 = or(_T_1780, _T_1781) node _T_1783 = asUInt(reset) node _T_1784 = eq(_T_1783, UInt<1>(0h0)) when _T_1784 : node _T_1785 = eq(_T_1782, UInt<1>(0h0)) when _T_1785 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1782, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<29>(0h0) connect _WIRE_28.bits.source, UInt<8>(0h0) connect _WIRE_28.bits.size, UInt<4>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1786 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1787 = and(io.in.d.ready, io.in.d.valid) node _T_1788 = or(_T_1786, _T_1787) when _T_1788 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_18( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_31 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_85 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2051:0] _c_sizes_set_T_1 = 2052'h0; // @[Monitor.scala:768:52] wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79] wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77] wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35] wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35] wire [1031:0] c_sizes_set = 1032'h0; // @[Monitor.scala:741:34] wire [515:0] c_opcodes_set = 516'h0; // @[Monitor.scala:740:34] wire [128:0] c_set = 129'h0; // @[Monitor.scala:738:34] wire [128:0] c_set_wo_ready = 129'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 8'h50; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_1 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_7 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_13 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_19 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 6'h10; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 6'h11; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 6'h12; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 6'h13; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 8'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 8'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_27 = io_in_a_bits_source_0[7:4]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_33 = io_in_a_bits_source_0[7:4]; // @[Monitor.scala:36:7] wire _source_ok_T_28 = _source_ok_T_27 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_32 = _source_ok_T_30; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_34 = _source_ok_T_33 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31] wire _source_ok_T_39 = io_in_a_bits_source_0 == 8'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_39; // @[Parameters.scala:1138:31] wire _source_ok_T_40 = io_in_a_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire _source_ok_T_41 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_42 = _source_ok_T_41 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_43 = _source_ok_T_42 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_44 = _source_ok_T_43 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_49 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {17'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_4 = _uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_5 = _uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_10 = _uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_11 = _uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_16 = _uncommonBits_T_16[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_17 = _uncommonBits_T_17[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_22 = _uncommonBits_T_22[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_23 = _uncommonBits_T_23[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_28 = _uncommonBits_T_28[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_29 = _uncommonBits_T_29[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_34 = _uncommonBits_T_34[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_35 = _uncommonBits_T_35[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_40 = _uncommonBits_T_40[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_41 = _uncommonBits_T_41[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_46 = _uncommonBits_T_46[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_47 = _uncommonBits_T_47[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_52 = _uncommonBits_T_52[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_53 = _uncommonBits_T_53[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_58 = _uncommonBits_T_58[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_59 = _uncommonBits_T_59[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_64 = _uncommonBits_T_64[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_65 = _uncommonBits_T_65[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_50 = io_in_d_bits_source_0 == 8'h50; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_50; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_51 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_57 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_63 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_69 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_52 = _source_ok_T_51 == 6'h10; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_56; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_58 = _source_ok_T_57 == 6'h11; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_62; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_64 = _source_ok_T_63 == 6'h12; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_68; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_70 = _source_ok_T_69 == 6'h13; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_74; // @[Parameters.scala:1138:31] wire _source_ok_T_75 = io_in_d_bits_source_0 == 8'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_75; // @[Parameters.scala:1138:31] wire _source_ok_T_76 = io_in_d_bits_source_0 == 8'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_76; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_77 = io_in_d_bits_source_0[7:4]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_83 = io_in_d_bits_source_0[7:4]; // @[Monitor.scala:36:7] wire _source_ok_T_78 = _source_ok_T_77 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_7 = _source_ok_T_82; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_84 = _source_ok_T_83 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_86 = _source_ok_T_84; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_8 = _source_ok_T_88; // @[Parameters.scala:1138:31] wire _source_ok_T_89 = io_in_d_bits_source_0 == 8'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_89; // @[Parameters.scala:1138:31] wire _source_ok_T_90 = io_in_d_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_90; // @[Parameters.scala:1138:31] wire _source_ok_T_91 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_92 = _source_ok_T_91 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_93 = _source_ok_T_92 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_94 = _source_ok_T_93 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_95 = _source_ok_T_94 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_96 = _source_ok_T_95 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_97 = _source_ok_T_96 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_98 = _source_ok_T_97 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_99 = _source_ok_T_98 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_99 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire _T_1720 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1720; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1720; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_1788 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1788; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1788; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1788; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [128:0] inflight; // @[Monitor.scala:614:27] reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [1031:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [128:0] a_set; // @[Monitor.scala:626:34] wire [128:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [515:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [1031:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [515:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [515:0] _a_opcode_lookup_T_6 = {512'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [515:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [10:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [1031:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [1031:0] _a_size_lookup_T_6 = {1024'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [1031:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[1031:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [255:0] _GEN_3 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [255:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1653 = _T_1720 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1653 ? _a_set_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1653 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1653 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [10:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1653 ? _a_opcodes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [10:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [2051:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1653 ? _a_sizes_set_T_1[1031:0] : 1032'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [128:0] d_clr; // @[Monitor.scala:664:34] wire [128:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [515:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [1031:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1699 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1699 & ~d_release_ack ? _d_clr_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1668 = _T_1788 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1668 ? _d_clr_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1668 ? _d_opcodes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [2062:0] _d_sizes_clr_T_5 = 2063'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1668 ? _d_sizes_clr_T_5[1031:0] : 1032'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [128:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [128:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [128:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [515:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [515:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [515:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [1031:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [1031:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [1031:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [128:0] inflight_1; // @[Monitor.scala:726:35] wire [128:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [515:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [515:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [1031:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [1031:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [515:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [515:0] _c_opcode_lookup_T_6 = {512'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [515:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [1031:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [1031:0] _c_size_lookup_T_6 = {1024'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [1031:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[1031:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [128:0] d_clr_1; // @[Monitor.scala:774:34] wire [128:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [515:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [1031:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1764 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1764 & d_release_ack_1 ? _d_clr_wo_ready_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1746 = _T_1788 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1746 ? _d_clr_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1746 ? _d_opcodes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [2062:0] _d_sizes_clr_T_11 = 2063'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1746 ? _d_sizes_clr_T_11[1031:0] : 1032'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113] wire [128:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [128:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [515:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [515:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [1031:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [1031:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_24 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<9>(0h110)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<7>(0h40)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<7>(0h41)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<7>(0h42)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<7>(0h43)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 4, 0) node _source_ok_T_28 = shr(io.in.a.bits.source, 5) node _source_ok_T_29 = eq(_source_ok_T_28, UInt<1>(0h0)) node _source_ok_T_30 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_31 = and(_source_ok_T_29, _source_ok_T_30) node _source_ok_T_32 = leq(source_ok_uncommonBits_4, UInt<5>(0h1f)) node _source_ok_T_33 = and(_source_ok_T_31, _source_ok_T_32) node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 4, 0) node _source_ok_T_34 = shr(io.in.a.bits.source, 5) node _source_ok_T_35 = eq(_source_ok_T_34, UInt<1>(0h1)) node _source_ok_T_36 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_37 = and(_source_ok_T_35, _source_ok_T_36) node _source_ok_T_38 = leq(source_ok_uncommonBits_5, UInt<5>(0h1f)) node _source_ok_T_39 = and(_source_ok_T_37, _source_ok_T_38) node _source_ok_uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 4, 0) node _source_ok_T_40 = shr(io.in.a.bits.source, 5) node _source_ok_T_41 = eq(_source_ok_T_40, UInt<2>(0h2)) node _source_ok_T_42 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_43 = and(_source_ok_T_41, _source_ok_T_42) node _source_ok_T_44 = leq(source_ok_uncommonBits_6, UInt<5>(0h1f)) node _source_ok_T_45 = and(_source_ok_T_43, _source_ok_T_44) node _source_ok_uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 4, 0) node _source_ok_T_46 = shr(io.in.a.bits.source, 5) node _source_ok_T_47 = eq(_source_ok_T_46, UInt<2>(0h3)) node _source_ok_T_48 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_49 = and(_source_ok_T_47, _source_ok_T_48) node _source_ok_T_50 = leq(source_ok_uncommonBits_7, UInt<5>(0h1f)) node _source_ok_T_51 = and(_source_ok_T_49, _source_ok_T_50) node _source_ok_uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 4, 0) node _source_ok_T_52 = shr(io.in.a.bits.source, 5) node _source_ok_T_53 = eq(_source_ok_T_52, UInt<3>(0h4)) node _source_ok_T_54 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_55 = and(_source_ok_T_53, _source_ok_T_54) node _source_ok_T_56 = leq(source_ok_uncommonBits_8, UInt<5>(0h1f)) node _source_ok_T_57 = and(_source_ok_T_55, _source_ok_T_56) node _source_ok_uncommonBits_T_9 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 4, 0) node _source_ok_T_58 = shr(io.in.a.bits.source, 5) node _source_ok_T_59 = eq(_source_ok_T_58, UInt<3>(0h5)) node _source_ok_T_60 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_61 = and(_source_ok_T_59, _source_ok_T_60) node _source_ok_T_62 = leq(source_ok_uncommonBits_9, UInt<5>(0h1f)) node _source_ok_T_63 = and(_source_ok_T_61, _source_ok_T_62) node _source_ok_uncommonBits_T_10 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 4, 0) node _source_ok_T_64 = shr(io.in.a.bits.source, 5) node _source_ok_T_65 = eq(_source_ok_T_64, UInt<3>(0h6)) node _source_ok_T_66 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_67 = and(_source_ok_T_65, _source_ok_T_66) node _source_ok_T_68 = leq(source_ok_uncommonBits_10, UInt<5>(0h1f)) node _source_ok_T_69 = and(_source_ok_T_67, _source_ok_T_68) node _source_ok_uncommonBits_T_11 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 4, 0) node _source_ok_T_70 = shr(io.in.a.bits.source, 5) node _source_ok_T_71 = eq(_source_ok_T_70, UInt<3>(0h7)) node _source_ok_T_72 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_73 = and(_source_ok_T_71, _source_ok_T_72) node _source_ok_T_74 = leq(source_ok_uncommonBits_11, UInt<5>(0h1f)) node _source_ok_T_75 = and(_source_ok_T_73, _source_ok_T_74) node _source_ok_T_76 = eq(io.in.a.bits.source, UInt<10>(0h200)) wire _source_ok_WIRE : UInt<1>[17] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_33 connect _source_ok_WIRE[9], _source_ok_T_39 connect _source_ok_WIRE[10], _source_ok_T_45 connect _source_ok_WIRE[11], _source_ok_T_51 connect _source_ok_WIRE[12], _source_ok_T_57 connect _source_ok_WIRE[13], _source_ok_T_63 connect _source_ok_WIRE[14], _source_ok_T_69 connect _source_ok_WIRE[15], _source_ok_T_75 connect _source_ok_WIRE[16], _source_ok_T_76 node _source_ok_T_77 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE[2]) node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE[3]) node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE[4]) node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE[5]) node _source_ok_T_82 = or(_source_ok_T_81, _source_ok_WIRE[6]) node _source_ok_T_83 = or(_source_ok_T_82, _source_ok_WIRE[7]) node _source_ok_T_84 = or(_source_ok_T_83, _source_ok_WIRE[8]) node _source_ok_T_85 = or(_source_ok_T_84, _source_ok_WIRE[9]) node _source_ok_T_86 = or(_source_ok_T_85, _source_ok_WIRE[10]) node _source_ok_T_87 = or(_source_ok_T_86, _source_ok_WIRE[11]) node _source_ok_T_88 = or(_source_ok_T_87, _source_ok_WIRE[12]) node _source_ok_T_89 = or(_source_ok_T_88, _source_ok_WIRE[13]) node _source_ok_T_90 = or(_source_ok_T_89, _source_ok_WIRE[14]) node _source_ok_T_91 = or(_source_ok_T_90, _source_ok_WIRE[15]) node source_ok = or(_source_ok_T_91, _source_ok_WIRE[16]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<7>(0h40)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<7>(0h41)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<7>(0h42)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<7>(0h43)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 4, 0) node _T_88 = shr(io.in.a.bits.source, 5) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = leq(UInt<1>(0h0), uncommonBits_4) node _T_91 = and(_T_89, _T_90) node _T_92 = leq(uncommonBits_4, UInt<5>(0h1f)) node _T_93 = and(_T_91, _T_92) node _T_94 = eq(_T_93, UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<1>(0h0))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = or(_T_94, _T_99) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 4, 0) node _T_101 = shr(io.in.a.bits.source, 5) node _T_102 = eq(_T_101, UInt<1>(0h1)) node _T_103 = leq(UInt<1>(0h0), uncommonBits_5) node _T_104 = and(_T_102, _T_103) node _T_105 = leq(uncommonBits_5, UInt<5>(0h1f)) node _T_106 = and(_T_104, _T_105) node _T_107 = eq(_T_106, UInt<1>(0h0)) node _T_108 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_109 = cvt(_T_108) node _T_110 = and(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = asSInt(_T_110) node _T_112 = eq(_T_111, asSInt(UInt<1>(0h0))) node _T_113 = or(_T_107, _T_112) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 4, 0) node _T_114 = shr(io.in.a.bits.source, 5) node _T_115 = eq(_T_114, UInt<2>(0h2)) node _T_116 = leq(UInt<1>(0h0), uncommonBits_6) node _T_117 = and(_T_115, _T_116) node _T_118 = leq(uncommonBits_6, UInt<5>(0h1f)) node _T_119 = and(_T_117, _T_118) node _T_120 = eq(_T_119, UInt<1>(0h0)) node _T_121 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_122 = cvt(_T_121) node _T_123 = and(_T_122, asSInt(UInt<1>(0h0))) node _T_124 = asSInt(_T_123) node _T_125 = eq(_T_124, asSInt(UInt<1>(0h0))) node _T_126 = or(_T_120, _T_125) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 4, 0) node _T_127 = shr(io.in.a.bits.source, 5) node _T_128 = eq(_T_127, UInt<2>(0h3)) node _T_129 = leq(UInt<1>(0h0), uncommonBits_7) node _T_130 = and(_T_128, _T_129) node _T_131 = leq(uncommonBits_7, UInt<5>(0h1f)) node _T_132 = and(_T_130, _T_131) node _T_133 = eq(_T_132, UInt<1>(0h0)) node _T_134 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_135 = cvt(_T_134) node _T_136 = and(_T_135, asSInt(UInt<1>(0h0))) node _T_137 = asSInt(_T_136) node _T_138 = eq(_T_137, asSInt(UInt<1>(0h0))) node _T_139 = or(_T_133, _T_138) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 4, 0) node _T_140 = shr(io.in.a.bits.source, 5) node _T_141 = eq(_T_140, UInt<3>(0h4)) node _T_142 = leq(UInt<1>(0h0), uncommonBits_8) node _T_143 = and(_T_141, _T_142) node _T_144 = leq(uncommonBits_8, UInt<5>(0h1f)) node _T_145 = and(_T_143, _T_144) node _T_146 = eq(_T_145, UInt<1>(0h0)) node _T_147 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_148 = cvt(_T_147) node _T_149 = and(_T_148, asSInt(UInt<1>(0h0))) node _T_150 = asSInt(_T_149) node _T_151 = eq(_T_150, asSInt(UInt<1>(0h0))) node _T_152 = or(_T_146, _T_151) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 4, 0) node _T_153 = shr(io.in.a.bits.source, 5) node _T_154 = eq(_T_153, UInt<3>(0h5)) node _T_155 = leq(UInt<1>(0h0), uncommonBits_9) node _T_156 = and(_T_154, _T_155) node _T_157 = leq(uncommonBits_9, UInt<5>(0h1f)) node _T_158 = and(_T_156, _T_157) node _T_159 = eq(_T_158, UInt<1>(0h0)) node _T_160 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_161 = cvt(_T_160) node _T_162 = and(_T_161, asSInt(UInt<1>(0h0))) node _T_163 = asSInt(_T_162) node _T_164 = eq(_T_163, asSInt(UInt<1>(0h0))) node _T_165 = or(_T_159, _T_164) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 4, 0) node _T_166 = shr(io.in.a.bits.source, 5) node _T_167 = eq(_T_166, UInt<3>(0h6)) node _T_168 = leq(UInt<1>(0h0), uncommonBits_10) node _T_169 = and(_T_167, _T_168) node _T_170 = leq(uncommonBits_10, UInt<5>(0h1f)) node _T_171 = and(_T_169, _T_170) node _T_172 = eq(_T_171, UInt<1>(0h0)) node _T_173 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_174 = cvt(_T_173) node _T_175 = and(_T_174, asSInt(UInt<1>(0h0))) node _T_176 = asSInt(_T_175) node _T_177 = eq(_T_176, asSInt(UInt<1>(0h0))) node _T_178 = or(_T_172, _T_177) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 4, 0) node _T_179 = shr(io.in.a.bits.source, 5) node _T_180 = eq(_T_179, UInt<3>(0h7)) node _T_181 = leq(UInt<1>(0h0), uncommonBits_11) node _T_182 = and(_T_180, _T_181) node _T_183 = leq(uncommonBits_11, UInt<5>(0h1f)) node _T_184 = and(_T_182, _T_183) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_187 = cvt(_T_186) node _T_188 = and(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = asSInt(_T_188) node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0))) node _T_191 = or(_T_185, _T_190) node _T_192 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_193 = eq(_T_192, UInt<1>(0h0)) node _T_194 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<1>(0h0))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = or(_T_193, _T_198) node _T_200 = and(_T_11, _T_24) node _T_201 = and(_T_200, _T_37) node _T_202 = and(_T_201, _T_50) node _T_203 = and(_T_202, _T_63) node _T_204 = and(_T_203, _T_71) node _T_205 = and(_T_204, _T_79) node _T_206 = and(_T_205, _T_87) node _T_207 = and(_T_206, _T_100) node _T_208 = and(_T_207, _T_113) node _T_209 = and(_T_208, _T_126) node _T_210 = and(_T_209, _T_139) node _T_211 = and(_T_210, _T_152) node _T_212 = and(_T_211, _T_165) node _T_213 = and(_T_212, _T_178) node _T_214 = and(_T_213, _T_191) node _T_215 = and(_T_214, _T_199) node _T_216 = asUInt(reset) node _T_217 = eq(_T_216, UInt<1>(0h0)) when _T_217 : node _T_218 = eq(_T_215, UInt<1>(0h0)) when _T_218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_215, UInt<1>(0h1), "") : assert_1 node _T_219 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_219 : node _T_220 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_221 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_222 = and(_T_220, _T_221) node _T_223 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_224 = shr(io.in.a.bits.source, 2) node _T_225 = eq(_T_224, UInt<7>(0h40)) node _T_226 = leq(UInt<1>(0h0), uncommonBits_12) node _T_227 = and(_T_225, _T_226) node _T_228 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_229 = and(_T_227, _T_228) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_230 = shr(io.in.a.bits.source, 2) node _T_231 = eq(_T_230, UInt<7>(0h41)) node _T_232 = leq(UInt<1>(0h0), uncommonBits_13) node _T_233 = and(_T_231, _T_232) node _T_234 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_235 = and(_T_233, _T_234) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_236 = shr(io.in.a.bits.source, 2) node _T_237 = eq(_T_236, UInt<7>(0h42)) node _T_238 = leq(UInt<1>(0h0), uncommonBits_14) node _T_239 = and(_T_237, _T_238) node _T_240 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_241 = and(_T_239, _T_240) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_242 = shr(io.in.a.bits.source, 2) node _T_243 = eq(_T_242, UInt<7>(0h43)) node _T_244 = leq(UInt<1>(0h0), uncommonBits_15) node _T_245 = and(_T_243, _T_244) node _T_246 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_247 = and(_T_245, _T_246) node _T_248 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_249 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_250 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 4, 0) node _T_251 = shr(io.in.a.bits.source, 5) node _T_252 = eq(_T_251, UInt<1>(0h0)) node _T_253 = leq(UInt<1>(0h0), uncommonBits_16) node _T_254 = and(_T_252, _T_253) node _T_255 = leq(uncommonBits_16, UInt<5>(0h1f)) node _T_256 = and(_T_254, _T_255) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 4, 0) node _T_257 = shr(io.in.a.bits.source, 5) node _T_258 = eq(_T_257, UInt<1>(0h1)) node _T_259 = leq(UInt<1>(0h0), uncommonBits_17) node _T_260 = and(_T_258, _T_259) node _T_261 = leq(uncommonBits_17, UInt<5>(0h1f)) node _T_262 = and(_T_260, _T_261) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 4, 0) node _T_263 = shr(io.in.a.bits.source, 5) node _T_264 = eq(_T_263, UInt<2>(0h2)) node _T_265 = leq(UInt<1>(0h0), uncommonBits_18) node _T_266 = and(_T_264, _T_265) node _T_267 = leq(uncommonBits_18, UInt<5>(0h1f)) node _T_268 = and(_T_266, _T_267) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 4, 0) node _T_269 = shr(io.in.a.bits.source, 5) node _T_270 = eq(_T_269, UInt<2>(0h3)) node _T_271 = leq(UInt<1>(0h0), uncommonBits_19) node _T_272 = and(_T_270, _T_271) node _T_273 = leq(uncommonBits_19, UInt<5>(0h1f)) node _T_274 = and(_T_272, _T_273) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 4, 0) node _T_275 = shr(io.in.a.bits.source, 5) node _T_276 = eq(_T_275, UInt<3>(0h4)) node _T_277 = leq(UInt<1>(0h0), uncommonBits_20) node _T_278 = and(_T_276, _T_277) node _T_279 = leq(uncommonBits_20, UInt<5>(0h1f)) node _T_280 = and(_T_278, _T_279) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 4, 0) node _T_281 = shr(io.in.a.bits.source, 5) node _T_282 = eq(_T_281, UInt<3>(0h5)) node _T_283 = leq(UInt<1>(0h0), uncommonBits_21) node _T_284 = and(_T_282, _T_283) node _T_285 = leq(uncommonBits_21, UInt<5>(0h1f)) node _T_286 = and(_T_284, _T_285) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 4, 0) node _T_287 = shr(io.in.a.bits.source, 5) node _T_288 = eq(_T_287, UInt<3>(0h6)) node _T_289 = leq(UInt<1>(0h0), uncommonBits_22) node _T_290 = and(_T_288, _T_289) node _T_291 = leq(uncommonBits_22, UInt<5>(0h1f)) node _T_292 = and(_T_290, _T_291) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 4, 0) node _T_293 = shr(io.in.a.bits.source, 5) node _T_294 = eq(_T_293, UInt<3>(0h7)) node _T_295 = leq(UInt<1>(0h0), uncommonBits_23) node _T_296 = and(_T_294, _T_295) node _T_297 = leq(uncommonBits_23, UInt<5>(0h1f)) node _T_298 = and(_T_296, _T_297) node _T_299 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_300 = or(_T_223, _T_229) node _T_301 = or(_T_300, _T_235) node _T_302 = or(_T_301, _T_241) node _T_303 = or(_T_302, _T_247) node _T_304 = or(_T_303, _T_248) node _T_305 = or(_T_304, _T_249) node _T_306 = or(_T_305, _T_250) node _T_307 = or(_T_306, _T_256) node _T_308 = or(_T_307, _T_262) node _T_309 = or(_T_308, _T_268) node _T_310 = or(_T_309, _T_274) node _T_311 = or(_T_310, _T_280) node _T_312 = or(_T_311, _T_286) node _T_313 = or(_T_312, _T_292) node _T_314 = or(_T_313, _T_298) node _T_315 = or(_T_314, _T_299) node _T_316 = and(_T_222, _T_315) node _T_317 = or(UInt<1>(0h0), _T_316) node _T_318 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_319 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_320 = cvt(_T_319) node _T_321 = and(_T_320, asSInt(UInt<14>(0h2000))) node _T_322 = asSInt(_T_321) node _T_323 = eq(_T_322, asSInt(UInt<1>(0h0))) node _T_324 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_325 = cvt(_T_324) node _T_326 = and(_T_325, asSInt(UInt<13>(0h1000))) node _T_327 = asSInt(_T_326) node _T_328 = eq(_T_327, asSInt(UInt<1>(0h0))) node _T_329 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_330 = cvt(_T_329) node _T_331 = and(_T_330, asSInt(UInt<17>(0h10000))) node _T_332 = asSInt(_T_331) node _T_333 = eq(_T_332, asSInt(UInt<1>(0h0))) node _T_334 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_335 = cvt(_T_334) node _T_336 = and(_T_335, asSInt(UInt<18>(0h2f000))) node _T_337 = asSInt(_T_336) node _T_338 = eq(_T_337, asSInt(UInt<1>(0h0))) node _T_339 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_340 = cvt(_T_339) node _T_341 = and(_T_340, asSInt(UInt<17>(0h10000))) node _T_342 = asSInt(_T_341) node _T_343 = eq(_T_342, asSInt(UInt<1>(0h0))) node _T_344 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_345 = cvt(_T_344) node _T_346 = and(_T_345, asSInt(UInt<13>(0h1000))) node _T_347 = asSInt(_T_346) node _T_348 = eq(_T_347, asSInt(UInt<1>(0h0))) node _T_349 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_350 = cvt(_T_349) node _T_351 = and(_T_350, asSInt(UInt<27>(0h4000000))) node _T_352 = asSInt(_T_351) node _T_353 = eq(_T_352, asSInt(UInt<1>(0h0))) node _T_354 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_355 = cvt(_T_354) node _T_356 = and(_T_355, asSInt(UInt<13>(0h1000))) node _T_357 = asSInt(_T_356) node _T_358 = eq(_T_357, asSInt(UInt<1>(0h0))) node _T_359 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_360 = cvt(_T_359) node _T_361 = and(_T_360, asSInt(UInt<19>(0h40000))) node _T_362 = asSInt(_T_361) node _T_363 = eq(_T_362, asSInt(UInt<1>(0h0))) node _T_364 = or(_T_323, _T_328) node _T_365 = or(_T_364, _T_333) node _T_366 = or(_T_365, _T_338) node _T_367 = or(_T_366, _T_343) node _T_368 = or(_T_367, _T_348) node _T_369 = or(_T_368, _T_353) node _T_370 = or(_T_369, _T_358) node _T_371 = or(_T_370, _T_363) node _T_372 = and(_T_318, _T_371) node _T_373 = or(UInt<1>(0h0), _T_372) node _T_374 = and(_T_317, _T_373) node _T_375 = asUInt(reset) node _T_376 = eq(_T_375, UInt<1>(0h0)) when _T_376 : node _T_377 = eq(_T_374, UInt<1>(0h0)) when _T_377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_374, UInt<1>(0h1), "") : assert_2 node _T_378 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_379 = shr(io.in.a.bits.source, 2) node _T_380 = eq(_T_379, UInt<7>(0h40)) node _T_381 = leq(UInt<1>(0h0), uncommonBits_24) node _T_382 = and(_T_380, _T_381) node _T_383 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_384 = and(_T_382, _T_383) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_385 = shr(io.in.a.bits.source, 2) node _T_386 = eq(_T_385, UInt<7>(0h41)) node _T_387 = leq(UInt<1>(0h0), uncommonBits_25) node _T_388 = and(_T_386, _T_387) node _T_389 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_390 = and(_T_388, _T_389) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_391 = shr(io.in.a.bits.source, 2) node _T_392 = eq(_T_391, UInt<7>(0h42)) node _T_393 = leq(UInt<1>(0h0), uncommonBits_26) node _T_394 = and(_T_392, _T_393) node _T_395 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_396 = and(_T_394, _T_395) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_397 = shr(io.in.a.bits.source, 2) node _T_398 = eq(_T_397, UInt<7>(0h43)) node _T_399 = leq(UInt<1>(0h0), uncommonBits_27) node _T_400 = and(_T_398, _T_399) node _T_401 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_402 = and(_T_400, _T_401) node _T_403 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_404 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_405 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 4, 0) node _T_406 = shr(io.in.a.bits.source, 5) node _T_407 = eq(_T_406, UInt<1>(0h0)) node _T_408 = leq(UInt<1>(0h0), uncommonBits_28) node _T_409 = and(_T_407, _T_408) node _T_410 = leq(uncommonBits_28, UInt<5>(0h1f)) node _T_411 = and(_T_409, _T_410) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 4, 0) node _T_412 = shr(io.in.a.bits.source, 5) node _T_413 = eq(_T_412, UInt<1>(0h1)) node _T_414 = leq(UInt<1>(0h0), uncommonBits_29) node _T_415 = and(_T_413, _T_414) node _T_416 = leq(uncommonBits_29, UInt<5>(0h1f)) node _T_417 = and(_T_415, _T_416) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 4, 0) node _T_418 = shr(io.in.a.bits.source, 5) node _T_419 = eq(_T_418, UInt<2>(0h2)) node _T_420 = leq(UInt<1>(0h0), uncommonBits_30) node _T_421 = and(_T_419, _T_420) node _T_422 = leq(uncommonBits_30, UInt<5>(0h1f)) node _T_423 = and(_T_421, _T_422) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 4, 0) node _T_424 = shr(io.in.a.bits.source, 5) node _T_425 = eq(_T_424, UInt<2>(0h3)) node _T_426 = leq(UInt<1>(0h0), uncommonBits_31) node _T_427 = and(_T_425, _T_426) node _T_428 = leq(uncommonBits_31, UInt<5>(0h1f)) node _T_429 = and(_T_427, _T_428) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 4, 0) node _T_430 = shr(io.in.a.bits.source, 5) node _T_431 = eq(_T_430, UInt<3>(0h4)) node _T_432 = leq(UInt<1>(0h0), uncommonBits_32) node _T_433 = and(_T_431, _T_432) node _T_434 = leq(uncommonBits_32, UInt<5>(0h1f)) node _T_435 = and(_T_433, _T_434) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 4, 0) node _T_436 = shr(io.in.a.bits.source, 5) node _T_437 = eq(_T_436, UInt<3>(0h5)) node _T_438 = leq(UInt<1>(0h0), uncommonBits_33) node _T_439 = and(_T_437, _T_438) node _T_440 = leq(uncommonBits_33, UInt<5>(0h1f)) node _T_441 = and(_T_439, _T_440) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 4, 0) node _T_442 = shr(io.in.a.bits.source, 5) node _T_443 = eq(_T_442, UInt<3>(0h6)) node _T_444 = leq(UInt<1>(0h0), uncommonBits_34) node _T_445 = and(_T_443, _T_444) node _T_446 = leq(uncommonBits_34, UInt<5>(0h1f)) node _T_447 = and(_T_445, _T_446) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 4, 0) node _T_448 = shr(io.in.a.bits.source, 5) node _T_449 = eq(_T_448, UInt<3>(0h7)) node _T_450 = leq(UInt<1>(0h0), uncommonBits_35) node _T_451 = and(_T_449, _T_450) node _T_452 = leq(uncommonBits_35, UInt<5>(0h1f)) node _T_453 = and(_T_451, _T_452) node _T_454 = eq(io.in.a.bits.source, UInt<10>(0h200)) wire _WIRE : UInt<1>[17] connect _WIRE[0], _T_378 connect _WIRE[1], _T_384 connect _WIRE[2], _T_390 connect _WIRE[3], _T_396 connect _WIRE[4], _T_402 connect _WIRE[5], _T_403 connect _WIRE[6], _T_404 connect _WIRE[7], _T_405 connect _WIRE[8], _T_411 connect _WIRE[9], _T_417 connect _WIRE[10], _T_423 connect _WIRE[11], _T_429 connect _WIRE[12], _T_435 connect _WIRE[13], _T_441 connect _WIRE[14], _T_447 connect _WIRE[15], _T_453 connect _WIRE[16], _T_454 node _T_455 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_456 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_457 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_458 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_459 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_460 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_461 = mux(_WIRE[5], _T_455, UInt<1>(0h0)) node _T_462 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_463 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_464 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_465 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_466 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_467 = mux(_WIRE[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_468 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_469 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_470 = mux(_WIRE[14], UInt<1>(0h0), UInt<1>(0h0)) node _T_471 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_472 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_473 = or(_T_456, _T_457) node _T_474 = or(_T_473, _T_458) node _T_475 = or(_T_474, _T_459) node _T_476 = or(_T_475, _T_460) node _T_477 = or(_T_476, _T_461) node _T_478 = or(_T_477, _T_462) node _T_479 = or(_T_478, _T_463) node _T_480 = or(_T_479, _T_464) node _T_481 = or(_T_480, _T_465) node _T_482 = or(_T_481, _T_466) node _T_483 = or(_T_482, _T_467) node _T_484 = or(_T_483, _T_468) node _T_485 = or(_T_484, _T_469) node _T_486 = or(_T_485, _T_470) node _T_487 = or(_T_486, _T_471) node _T_488 = or(_T_487, _T_472) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_488 node _T_489 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_490 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_491 = and(_T_489, _T_490) node _T_492 = or(UInt<1>(0h0), _T_491) node _T_493 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_494 = cvt(_T_493) node _T_495 = and(_T_494, asSInt(UInt<14>(0h2000))) node _T_496 = asSInt(_T_495) node _T_497 = eq(_T_496, asSInt(UInt<1>(0h0))) node _T_498 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_499 = cvt(_T_498) node _T_500 = and(_T_499, asSInt(UInt<13>(0h1000))) node _T_501 = asSInt(_T_500) node _T_502 = eq(_T_501, asSInt(UInt<1>(0h0))) node _T_503 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_504 = cvt(_T_503) node _T_505 = and(_T_504, asSInt(UInt<17>(0h10000))) node _T_506 = asSInt(_T_505) node _T_507 = eq(_T_506, asSInt(UInt<1>(0h0))) node _T_508 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_509 = cvt(_T_508) node _T_510 = and(_T_509, asSInt(UInt<18>(0h2f000))) node _T_511 = asSInt(_T_510) node _T_512 = eq(_T_511, asSInt(UInt<1>(0h0))) node _T_513 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_514 = cvt(_T_513) node _T_515 = and(_T_514, asSInt(UInt<17>(0h10000))) node _T_516 = asSInt(_T_515) node _T_517 = eq(_T_516, asSInt(UInt<1>(0h0))) node _T_518 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_519 = cvt(_T_518) node _T_520 = and(_T_519, asSInt(UInt<13>(0h1000))) node _T_521 = asSInt(_T_520) node _T_522 = eq(_T_521, asSInt(UInt<1>(0h0))) node _T_523 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_524 = cvt(_T_523) node _T_525 = and(_T_524, asSInt(UInt<27>(0h4000000))) node _T_526 = asSInt(_T_525) node _T_527 = eq(_T_526, asSInt(UInt<1>(0h0))) node _T_528 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_529 = cvt(_T_528) node _T_530 = and(_T_529, asSInt(UInt<13>(0h1000))) node _T_531 = asSInt(_T_530) node _T_532 = eq(_T_531, asSInt(UInt<1>(0h0))) node _T_533 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_534 = cvt(_T_533) node _T_535 = and(_T_534, asSInt(UInt<19>(0h40000))) node _T_536 = asSInt(_T_535) node _T_537 = eq(_T_536, asSInt(UInt<1>(0h0))) node _T_538 = or(_T_497, _T_502) node _T_539 = or(_T_538, _T_507) node _T_540 = or(_T_539, _T_512) node _T_541 = or(_T_540, _T_517) node _T_542 = or(_T_541, _T_522) node _T_543 = or(_T_542, _T_527) node _T_544 = or(_T_543, _T_532) node _T_545 = or(_T_544, _T_537) node _T_546 = and(_T_492, _T_545) node _T_547 = or(UInt<1>(0h0), _T_546) node _T_548 = and(_WIRE_1, _T_547) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_548, UInt<1>(0h1), "") : assert_3 node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(source_ok, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_555 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_556 = asUInt(reset) node _T_557 = eq(_T_556, UInt<1>(0h0)) when _T_557 : node _T_558 = eq(_T_555, UInt<1>(0h0)) when _T_558 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_555, UInt<1>(0h1), "") : assert_5 node _T_559 = asUInt(reset) node _T_560 = eq(_T_559, UInt<1>(0h0)) when _T_560 : node _T_561 = eq(is_aligned, UInt<1>(0h0)) when _T_561 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_562 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_563 = asUInt(reset) node _T_564 = eq(_T_563, UInt<1>(0h0)) when _T_564 : node _T_565 = eq(_T_562, UInt<1>(0h0)) when _T_565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_562, UInt<1>(0h1), "") : assert_7 node _T_566 = not(io.in.a.bits.mask) node _T_567 = eq(_T_566, UInt<1>(0h0)) node _T_568 = asUInt(reset) node _T_569 = eq(_T_568, UInt<1>(0h0)) when _T_569 : node _T_570 = eq(_T_567, UInt<1>(0h0)) when _T_570 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_567, UInt<1>(0h1), "") : assert_8 node _T_571 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_572 = asUInt(reset) node _T_573 = eq(_T_572, UInt<1>(0h0)) when _T_573 : node _T_574 = eq(_T_571, UInt<1>(0h0)) when _T_574 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_571, UInt<1>(0h1), "") : assert_9 node _T_575 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_575 : node _T_576 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_577 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_578 = and(_T_576, _T_577) node _T_579 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_580 = shr(io.in.a.bits.source, 2) node _T_581 = eq(_T_580, UInt<7>(0h40)) node _T_582 = leq(UInt<1>(0h0), uncommonBits_36) node _T_583 = and(_T_581, _T_582) node _T_584 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_585 = and(_T_583, _T_584) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_586 = shr(io.in.a.bits.source, 2) node _T_587 = eq(_T_586, UInt<7>(0h41)) node _T_588 = leq(UInt<1>(0h0), uncommonBits_37) node _T_589 = and(_T_587, _T_588) node _T_590 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_591 = and(_T_589, _T_590) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_592 = shr(io.in.a.bits.source, 2) node _T_593 = eq(_T_592, UInt<7>(0h42)) node _T_594 = leq(UInt<1>(0h0), uncommonBits_38) node _T_595 = and(_T_593, _T_594) node _T_596 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_597 = and(_T_595, _T_596) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_598 = shr(io.in.a.bits.source, 2) node _T_599 = eq(_T_598, UInt<7>(0h43)) node _T_600 = leq(UInt<1>(0h0), uncommonBits_39) node _T_601 = and(_T_599, _T_600) node _T_602 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_603 = and(_T_601, _T_602) node _T_604 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_605 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_606 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 4, 0) node _T_607 = shr(io.in.a.bits.source, 5) node _T_608 = eq(_T_607, UInt<1>(0h0)) node _T_609 = leq(UInt<1>(0h0), uncommonBits_40) node _T_610 = and(_T_608, _T_609) node _T_611 = leq(uncommonBits_40, UInt<5>(0h1f)) node _T_612 = and(_T_610, _T_611) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 4, 0) node _T_613 = shr(io.in.a.bits.source, 5) node _T_614 = eq(_T_613, UInt<1>(0h1)) node _T_615 = leq(UInt<1>(0h0), uncommonBits_41) node _T_616 = and(_T_614, _T_615) node _T_617 = leq(uncommonBits_41, UInt<5>(0h1f)) node _T_618 = and(_T_616, _T_617) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 4, 0) node _T_619 = shr(io.in.a.bits.source, 5) node _T_620 = eq(_T_619, UInt<2>(0h2)) node _T_621 = leq(UInt<1>(0h0), uncommonBits_42) node _T_622 = and(_T_620, _T_621) node _T_623 = leq(uncommonBits_42, UInt<5>(0h1f)) node _T_624 = and(_T_622, _T_623) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 4, 0) node _T_625 = shr(io.in.a.bits.source, 5) node _T_626 = eq(_T_625, UInt<2>(0h3)) node _T_627 = leq(UInt<1>(0h0), uncommonBits_43) node _T_628 = and(_T_626, _T_627) node _T_629 = leq(uncommonBits_43, UInt<5>(0h1f)) node _T_630 = and(_T_628, _T_629) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 4, 0) node _T_631 = shr(io.in.a.bits.source, 5) node _T_632 = eq(_T_631, UInt<3>(0h4)) node _T_633 = leq(UInt<1>(0h0), uncommonBits_44) node _T_634 = and(_T_632, _T_633) node _T_635 = leq(uncommonBits_44, UInt<5>(0h1f)) node _T_636 = and(_T_634, _T_635) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 4, 0) node _T_637 = shr(io.in.a.bits.source, 5) node _T_638 = eq(_T_637, UInt<3>(0h5)) node _T_639 = leq(UInt<1>(0h0), uncommonBits_45) node _T_640 = and(_T_638, _T_639) node _T_641 = leq(uncommonBits_45, UInt<5>(0h1f)) node _T_642 = and(_T_640, _T_641) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 4, 0) node _T_643 = shr(io.in.a.bits.source, 5) node _T_644 = eq(_T_643, UInt<3>(0h6)) node _T_645 = leq(UInt<1>(0h0), uncommonBits_46) node _T_646 = and(_T_644, _T_645) node _T_647 = leq(uncommonBits_46, UInt<5>(0h1f)) node _T_648 = and(_T_646, _T_647) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 4, 0) node _T_649 = shr(io.in.a.bits.source, 5) node _T_650 = eq(_T_649, UInt<3>(0h7)) node _T_651 = leq(UInt<1>(0h0), uncommonBits_47) node _T_652 = and(_T_650, _T_651) node _T_653 = leq(uncommonBits_47, UInt<5>(0h1f)) node _T_654 = and(_T_652, _T_653) node _T_655 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_656 = or(_T_579, _T_585) node _T_657 = or(_T_656, _T_591) node _T_658 = or(_T_657, _T_597) node _T_659 = or(_T_658, _T_603) node _T_660 = or(_T_659, _T_604) node _T_661 = or(_T_660, _T_605) node _T_662 = or(_T_661, _T_606) node _T_663 = or(_T_662, _T_612) node _T_664 = or(_T_663, _T_618) node _T_665 = or(_T_664, _T_624) node _T_666 = or(_T_665, _T_630) node _T_667 = or(_T_666, _T_636) node _T_668 = or(_T_667, _T_642) node _T_669 = or(_T_668, _T_648) node _T_670 = or(_T_669, _T_654) node _T_671 = or(_T_670, _T_655) node _T_672 = and(_T_578, _T_671) node _T_673 = or(UInt<1>(0h0), _T_672) node _T_674 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_675 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_676 = cvt(_T_675) node _T_677 = and(_T_676, asSInt(UInt<14>(0h2000))) node _T_678 = asSInt(_T_677) node _T_679 = eq(_T_678, asSInt(UInt<1>(0h0))) node _T_680 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_681 = cvt(_T_680) node _T_682 = and(_T_681, asSInt(UInt<13>(0h1000))) node _T_683 = asSInt(_T_682) node _T_684 = eq(_T_683, asSInt(UInt<1>(0h0))) node _T_685 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_686 = cvt(_T_685) node _T_687 = and(_T_686, asSInt(UInt<17>(0h10000))) node _T_688 = asSInt(_T_687) node _T_689 = eq(_T_688, asSInt(UInt<1>(0h0))) node _T_690 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_691 = cvt(_T_690) node _T_692 = and(_T_691, asSInt(UInt<18>(0h2f000))) node _T_693 = asSInt(_T_692) node _T_694 = eq(_T_693, asSInt(UInt<1>(0h0))) node _T_695 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_696 = cvt(_T_695) node _T_697 = and(_T_696, asSInt(UInt<17>(0h10000))) node _T_698 = asSInt(_T_697) node _T_699 = eq(_T_698, asSInt(UInt<1>(0h0))) node _T_700 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_701 = cvt(_T_700) node _T_702 = and(_T_701, asSInt(UInt<13>(0h1000))) node _T_703 = asSInt(_T_702) node _T_704 = eq(_T_703, asSInt(UInt<1>(0h0))) node _T_705 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_706 = cvt(_T_705) node _T_707 = and(_T_706, asSInt(UInt<27>(0h4000000))) node _T_708 = asSInt(_T_707) node _T_709 = eq(_T_708, asSInt(UInt<1>(0h0))) node _T_710 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_711 = cvt(_T_710) node _T_712 = and(_T_711, asSInt(UInt<13>(0h1000))) node _T_713 = asSInt(_T_712) node _T_714 = eq(_T_713, asSInt(UInt<1>(0h0))) node _T_715 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_716 = cvt(_T_715) node _T_717 = and(_T_716, asSInt(UInt<19>(0h40000))) node _T_718 = asSInt(_T_717) node _T_719 = eq(_T_718, asSInt(UInt<1>(0h0))) node _T_720 = or(_T_679, _T_684) node _T_721 = or(_T_720, _T_689) node _T_722 = or(_T_721, _T_694) node _T_723 = or(_T_722, _T_699) node _T_724 = or(_T_723, _T_704) node _T_725 = or(_T_724, _T_709) node _T_726 = or(_T_725, _T_714) node _T_727 = or(_T_726, _T_719) node _T_728 = and(_T_674, _T_727) node _T_729 = or(UInt<1>(0h0), _T_728) node _T_730 = and(_T_673, _T_729) node _T_731 = asUInt(reset) node _T_732 = eq(_T_731, UInt<1>(0h0)) when _T_732 : node _T_733 = eq(_T_730, UInt<1>(0h0)) when _T_733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_730, UInt<1>(0h1), "") : assert_10 node _T_734 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_735 = shr(io.in.a.bits.source, 2) node _T_736 = eq(_T_735, UInt<7>(0h40)) node _T_737 = leq(UInt<1>(0h0), uncommonBits_48) node _T_738 = and(_T_736, _T_737) node _T_739 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_740 = and(_T_738, _T_739) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0) node _T_741 = shr(io.in.a.bits.source, 2) node _T_742 = eq(_T_741, UInt<7>(0h41)) node _T_743 = leq(UInt<1>(0h0), uncommonBits_49) node _T_744 = and(_T_742, _T_743) node _T_745 = leq(uncommonBits_49, UInt<2>(0h3)) node _T_746 = and(_T_744, _T_745) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_747 = shr(io.in.a.bits.source, 2) node _T_748 = eq(_T_747, UInt<7>(0h42)) node _T_749 = leq(UInt<1>(0h0), uncommonBits_50) node _T_750 = and(_T_748, _T_749) node _T_751 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_752 = and(_T_750, _T_751) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_753 = shr(io.in.a.bits.source, 2) node _T_754 = eq(_T_753, UInt<7>(0h43)) node _T_755 = leq(UInt<1>(0h0), uncommonBits_51) node _T_756 = and(_T_754, _T_755) node _T_757 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_758 = and(_T_756, _T_757) node _T_759 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_760 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_761 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 4, 0) node _T_762 = shr(io.in.a.bits.source, 5) node _T_763 = eq(_T_762, UInt<1>(0h0)) node _T_764 = leq(UInt<1>(0h0), uncommonBits_52) node _T_765 = and(_T_763, _T_764) node _T_766 = leq(uncommonBits_52, UInt<5>(0h1f)) node _T_767 = and(_T_765, _T_766) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 4, 0) node _T_768 = shr(io.in.a.bits.source, 5) node _T_769 = eq(_T_768, UInt<1>(0h1)) node _T_770 = leq(UInt<1>(0h0), uncommonBits_53) node _T_771 = and(_T_769, _T_770) node _T_772 = leq(uncommonBits_53, UInt<5>(0h1f)) node _T_773 = and(_T_771, _T_772) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 4, 0) node _T_774 = shr(io.in.a.bits.source, 5) node _T_775 = eq(_T_774, UInt<2>(0h2)) node _T_776 = leq(UInt<1>(0h0), uncommonBits_54) node _T_777 = and(_T_775, _T_776) node _T_778 = leq(uncommonBits_54, UInt<5>(0h1f)) node _T_779 = and(_T_777, _T_778) node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 4, 0) node _T_780 = shr(io.in.a.bits.source, 5) node _T_781 = eq(_T_780, UInt<2>(0h3)) node _T_782 = leq(UInt<1>(0h0), uncommonBits_55) node _T_783 = and(_T_781, _T_782) node _T_784 = leq(uncommonBits_55, UInt<5>(0h1f)) node _T_785 = and(_T_783, _T_784) node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 4, 0) node _T_786 = shr(io.in.a.bits.source, 5) node _T_787 = eq(_T_786, UInt<3>(0h4)) node _T_788 = leq(UInt<1>(0h0), uncommonBits_56) node _T_789 = and(_T_787, _T_788) node _T_790 = leq(uncommonBits_56, UInt<5>(0h1f)) node _T_791 = and(_T_789, _T_790) node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 4, 0) node _T_792 = shr(io.in.a.bits.source, 5) node _T_793 = eq(_T_792, UInt<3>(0h5)) node _T_794 = leq(UInt<1>(0h0), uncommonBits_57) node _T_795 = and(_T_793, _T_794) node _T_796 = leq(uncommonBits_57, UInt<5>(0h1f)) node _T_797 = and(_T_795, _T_796) node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 4, 0) node _T_798 = shr(io.in.a.bits.source, 5) node _T_799 = eq(_T_798, UInt<3>(0h6)) node _T_800 = leq(UInt<1>(0h0), uncommonBits_58) node _T_801 = and(_T_799, _T_800) node _T_802 = leq(uncommonBits_58, UInt<5>(0h1f)) node _T_803 = and(_T_801, _T_802) node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 4, 0) node _T_804 = shr(io.in.a.bits.source, 5) node _T_805 = eq(_T_804, UInt<3>(0h7)) node _T_806 = leq(UInt<1>(0h0), uncommonBits_59) node _T_807 = and(_T_805, _T_806) node _T_808 = leq(uncommonBits_59, UInt<5>(0h1f)) node _T_809 = and(_T_807, _T_808) node _T_810 = eq(io.in.a.bits.source, UInt<10>(0h200)) wire _WIRE_2 : UInt<1>[17] connect _WIRE_2[0], _T_734 connect _WIRE_2[1], _T_740 connect _WIRE_2[2], _T_746 connect _WIRE_2[3], _T_752 connect _WIRE_2[4], _T_758 connect _WIRE_2[5], _T_759 connect _WIRE_2[6], _T_760 connect _WIRE_2[7], _T_761 connect _WIRE_2[8], _T_767 connect _WIRE_2[9], _T_773 connect _WIRE_2[10], _T_779 connect _WIRE_2[11], _T_785 connect _WIRE_2[12], _T_791 connect _WIRE_2[13], _T_797 connect _WIRE_2[14], _T_803 connect _WIRE_2[15], _T_809 connect _WIRE_2[16], _T_810 node _T_811 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_812 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_813 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_814 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_815 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_816 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_817 = mux(_WIRE_2[5], _T_811, UInt<1>(0h0)) node _T_818 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_819 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_820 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_821 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_822 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_823 = mux(_WIRE_2[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_824 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_825 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_826 = mux(_WIRE_2[14], UInt<1>(0h0), UInt<1>(0h0)) node _T_827 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_828 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_829 = or(_T_812, _T_813) node _T_830 = or(_T_829, _T_814) node _T_831 = or(_T_830, _T_815) node _T_832 = or(_T_831, _T_816) node _T_833 = or(_T_832, _T_817) node _T_834 = or(_T_833, _T_818) node _T_835 = or(_T_834, _T_819) node _T_836 = or(_T_835, _T_820) node _T_837 = or(_T_836, _T_821) node _T_838 = or(_T_837, _T_822) node _T_839 = or(_T_838, _T_823) node _T_840 = or(_T_839, _T_824) node _T_841 = or(_T_840, _T_825) node _T_842 = or(_T_841, _T_826) node _T_843 = or(_T_842, _T_827) node _T_844 = or(_T_843, _T_828) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_844 node _T_845 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_846 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_847 = and(_T_845, _T_846) node _T_848 = or(UInt<1>(0h0), _T_847) node _T_849 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_850 = cvt(_T_849) node _T_851 = and(_T_850, asSInt(UInt<14>(0h2000))) node _T_852 = asSInt(_T_851) node _T_853 = eq(_T_852, asSInt(UInt<1>(0h0))) node _T_854 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_855 = cvt(_T_854) node _T_856 = and(_T_855, asSInt(UInt<13>(0h1000))) node _T_857 = asSInt(_T_856) node _T_858 = eq(_T_857, asSInt(UInt<1>(0h0))) node _T_859 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_860 = cvt(_T_859) node _T_861 = and(_T_860, asSInt(UInt<17>(0h10000))) node _T_862 = asSInt(_T_861) node _T_863 = eq(_T_862, asSInt(UInt<1>(0h0))) node _T_864 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_865 = cvt(_T_864) node _T_866 = and(_T_865, asSInt(UInt<18>(0h2f000))) node _T_867 = asSInt(_T_866) node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0))) node _T_869 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_870 = cvt(_T_869) node _T_871 = and(_T_870, asSInt(UInt<17>(0h10000))) node _T_872 = asSInt(_T_871) node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0))) node _T_874 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<13>(0h1000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_880 = cvt(_T_879) node _T_881 = and(_T_880, asSInt(UInt<27>(0h4000000))) node _T_882 = asSInt(_T_881) node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0))) node _T_884 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_885 = cvt(_T_884) node _T_886 = and(_T_885, asSInt(UInt<13>(0h1000))) node _T_887 = asSInt(_T_886) node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0))) node _T_889 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_890 = cvt(_T_889) node _T_891 = and(_T_890, asSInt(UInt<19>(0h40000))) node _T_892 = asSInt(_T_891) node _T_893 = eq(_T_892, asSInt(UInt<1>(0h0))) node _T_894 = or(_T_853, _T_858) node _T_895 = or(_T_894, _T_863) node _T_896 = or(_T_895, _T_868) node _T_897 = or(_T_896, _T_873) node _T_898 = or(_T_897, _T_878) node _T_899 = or(_T_898, _T_883) node _T_900 = or(_T_899, _T_888) node _T_901 = or(_T_900, _T_893) node _T_902 = and(_T_848, _T_901) node _T_903 = or(UInt<1>(0h0), _T_902) node _T_904 = and(_WIRE_3, _T_903) node _T_905 = asUInt(reset) node _T_906 = eq(_T_905, UInt<1>(0h0)) when _T_906 : node _T_907 = eq(_T_904, UInt<1>(0h0)) when _T_907 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_904, UInt<1>(0h1), "") : assert_11 node _T_908 = asUInt(reset) node _T_909 = eq(_T_908, UInt<1>(0h0)) when _T_909 : node _T_910 = eq(source_ok, UInt<1>(0h0)) when _T_910 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_911 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_912 = asUInt(reset) node _T_913 = eq(_T_912, UInt<1>(0h0)) when _T_913 : node _T_914 = eq(_T_911, UInt<1>(0h0)) when _T_914 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_911, UInt<1>(0h1), "") : assert_13 node _T_915 = asUInt(reset) node _T_916 = eq(_T_915, UInt<1>(0h0)) when _T_916 : node _T_917 = eq(is_aligned, UInt<1>(0h0)) when _T_917 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_918 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_919 = asUInt(reset) node _T_920 = eq(_T_919, UInt<1>(0h0)) when _T_920 : node _T_921 = eq(_T_918, UInt<1>(0h0)) when _T_921 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_918, UInt<1>(0h1), "") : assert_15 node _T_922 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_923 = asUInt(reset) node _T_924 = eq(_T_923, UInt<1>(0h0)) when _T_924 : node _T_925 = eq(_T_922, UInt<1>(0h0)) when _T_925 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_922, UInt<1>(0h1), "") : assert_16 node _T_926 = not(io.in.a.bits.mask) node _T_927 = eq(_T_926, UInt<1>(0h0)) node _T_928 = asUInt(reset) node _T_929 = eq(_T_928, UInt<1>(0h0)) when _T_929 : node _T_930 = eq(_T_927, UInt<1>(0h0)) when _T_930 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_927, UInt<1>(0h1), "") : assert_17 node _T_931 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_932 = asUInt(reset) node _T_933 = eq(_T_932, UInt<1>(0h0)) when _T_933 : node _T_934 = eq(_T_931, UInt<1>(0h0)) when _T_934 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_931, UInt<1>(0h1), "") : assert_18 node _T_935 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_935 : node _T_936 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_937 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_938 = and(_T_936, _T_937) node _T_939 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0) node _T_940 = shr(io.in.a.bits.source, 2) node _T_941 = eq(_T_940, UInt<7>(0h40)) node _T_942 = leq(UInt<1>(0h0), uncommonBits_60) node _T_943 = and(_T_941, _T_942) node _T_944 = leq(uncommonBits_60, UInt<2>(0h3)) node _T_945 = and(_T_943, _T_944) node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0) node _T_946 = shr(io.in.a.bits.source, 2) node _T_947 = eq(_T_946, UInt<7>(0h41)) node _T_948 = leq(UInt<1>(0h0), uncommonBits_61) node _T_949 = and(_T_947, _T_948) node _T_950 = leq(uncommonBits_61, UInt<2>(0h3)) node _T_951 = and(_T_949, _T_950) node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0) node _T_952 = shr(io.in.a.bits.source, 2) node _T_953 = eq(_T_952, UInt<7>(0h42)) node _T_954 = leq(UInt<1>(0h0), uncommonBits_62) node _T_955 = and(_T_953, _T_954) node _T_956 = leq(uncommonBits_62, UInt<2>(0h3)) node _T_957 = and(_T_955, _T_956) node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0) node _T_958 = shr(io.in.a.bits.source, 2) node _T_959 = eq(_T_958, UInt<7>(0h43)) node _T_960 = leq(UInt<1>(0h0), uncommonBits_63) node _T_961 = and(_T_959, _T_960) node _T_962 = leq(uncommonBits_63, UInt<2>(0h3)) node _T_963 = and(_T_961, _T_962) node _T_964 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_965 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_966 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 4, 0) node _T_967 = shr(io.in.a.bits.source, 5) node _T_968 = eq(_T_967, UInt<1>(0h0)) node _T_969 = leq(UInt<1>(0h0), uncommonBits_64) node _T_970 = and(_T_968, _T_969) node _T_971 = leq(uncommonBits_64, UInt<5>(0h1f)) node _T_972 = and(_T_970, _T_971) node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 4, 0) node _T_973 = shr(io.in.a.bits.source, 5) node _T_974 = eq(_T_973, UInt<1>(0h1)) node _T_975 = leq(UInt<1>(0h0), uncommonBits_65) node _T_976 = and(_T_974, _T_975) node _T_977 = leq(uncommonBits_65, UInt<5>(0h1f)) node _T_978 = and(_T_976, _T_977) node _uncommonBits_T_66 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_66 = bits(_uncommonBits_T_66, 4, 0) node _T_979 = shr(io.in.a.bits.source, 5) node _T_980 = eq(_T_979, UInt<2>(0h2)) node _T_981 = leq(UInt<1>(0h0), uncommonBits_66) node _T_982 = and(_T_980, _T_981) node _T_983 = leq(uncommonBits_66, UInt<5>(0h1f)) node _T_984 = and(_T_982, _T_983) node _uncommonBits_T_67 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_67 = bits(_uncommonBits_T_67, 4, 0) node _T_985 = shr(io.in.a.bits.source, 5) node _T_986 = eq(_T_985, UInt<2>(0h3)) node _T_987 = leq(UInt<1>(0h0), uncommonBits_67) node _T_988 = and(_T_986, _T_987) node _T_989 = leq(uncommonBits_67, UInt<5>(0h1f)) node _T_990 = and(_T_988, _T_989) node _uncommonBits_T_68 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_68 = bits(_uncommonBits_T_68, 4, 0) node _T_991 = shr(io.in.a.bits.source, 5) node _T_992 = eq(_T_991, UInt<3>(0h4)) node _T_993 = leq(UInt<1>(0h0), uncommonBits_68) node _T_994 = and(_T_992, _T_993) node _T_995 = leq(uncommonBits_68, UInt<5>(0h1f)) node _T_996 = and(_T_994, _T_995) node _uncommonBits_T_69 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_69 = bits(_uncommonBits_T_69, 4, 0) node _T_997 = shr(io.in.a.bits.source, 5) node _T_998 = eq(_T_997, UInt<3>(0h5)) node _T_999 = leq(UInt<1>(0h0), uncommonBits_69) node _T_1000 = and(_T_998, _T_999) node _T_1001 = leq(uncommonBits_69, UInt<5>(0h1f)) node _T_1002 = and(_T_1000, _T_1001) node _uncommonBits_T_70 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_70 = bits(_uncommonBits_T_70, 4, 0) node _T_1003 = shr(io.in.a.bits.source, 5) node _T_1004 = eq(_T_1003, UInt<3>(0h6)) node _T_1005 = leq(UInt<1>(0h0), uncommonBits_70) node _T_1006 = and(_T_1004, _T_1005) node _T_1007 = leq(uncommonBits_70, UInt<5>(0h1f)) node _T_1008 = and(_T_1006, _T_1007) node _uncommonBits_T_71 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_71 = bits(_uncommonBits_T_71, 4, 0) node _T_1009 = shr(io.in.a.bits.source, 5) node _T_1010 = eq(_T_1009, UInt<3>(0h7)) node _T_1011 = leq(UInt<1>(0h0), uncommonBits_71) node _T_1012 = and(_T_1010, _T_1011) node _T_1013 = leq(uncommonBits_71, UInt<5>(0h1f)) node _T_1014 = and(_T_1012, _T_1013) node _T_1015 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_1016 = or(_T_939, _T_945) node _T_1017 = or(_T_1016, _T_951) node _T_1018 = or(_T_1017, _T_957) node _T_1019 = or(_T_1018, _T_963) node _T_1020 = or(_T_1019, _T_964) node _T_1021 = or(_T_1020, _T_965) node _T_1022 = or(_T_1021, _T_966) node _T_1023 = or(_T_1022, _T_972) node _T_1024 = or(_T_1023, _T_978) node _T_1025 = or(_T_1024, _T_984) node _T_1026 = or(_T_1025, _T_990) node _T_1027 = or(_T_1026, _T_996) node _T_1028 = or(_T_1027, _T_1002) node _T_1029 = or(_T_1028, _T_1008) node _T_1030 = or(_T_1029, _T_1014) node _T_1031 = or(_T_1030, _T_1015) node _T_1032 = and(_T_938, _T_1031) node _T_1033 = or(UInt<1>(0h0), _T_1032) node _T_1034 = asUInt(reset) node _T_1035 = eq(_T_1034, UInt<1>(0h0)) when _T_1035 : node _T_1036 = eq(_T_1033, UInt<1>(0h0)) when _T_1036 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_1033, UInt<1>(0h1), "") : assert_19 node _T_1037 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1038 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1039 = and(_T_1037, _T_1038) node _T_1040 = or(UInt<1>(0h0), _T_1039) node _T_1041 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1042 = cvt(_T_1041) node _T_1043 = and(_T_1042, asSInt(UInt<13>(0h1000))) node _T_1044 = asSInt(_T_1043) node _T_1045 = eq(_T_1044, asSInt(UInt<1>(0h0))) node _T_1046 = and(_T_1040, _T_1045) node _T_1047 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1048 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1049 = and(_T_1047, _T_1048) node _T_1050 = or(UInt<1>(0h0), _T_1049) node _T_1051 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1052 = cvt(_T_1051) node _T_1053 = and(_T_1052, asSInt(UInt<14>(0h2000))) node _T_1054 = asSInt(_T_1053) node _T_1055 = eq(_T_1054, asSInt(UInt<1>(0h0))) node _T_1056 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1057 = cvt(_T_1056) node _T_1058 = and(_T_1057, asSInt(UInt<17>(0h10000))) node _T_1059 = asSInt(_T_1058) node _T_1060 = eq(_T_1059, asSInt(UInt<1>(0h0))) node _T_1061 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1062 = cvt(_T_1061) node _T_1063 = and(_T_1062, asSInt(UInt<18>(0h2f000))) node _T_1064 = asSInt(_T_1063) node _T_1065 = eq(_T_1064, asSInt(UInt<1>(0h0))) node _T_1066 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1067 = cvt(_T_1066) node _T_1068 = and(_T_1067, asSInt(UInt<17>(0h10000))) node _T_1069 = asSInt(_T_1068) node _T_1070 = eq(_T_1069, asSInt(UInt<1>(0h0))) node _T_1071 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1072 = cvt(_T_1071) node _T_1073 = and(_T_1072, asSInt(UInt<13>(0h1000))) node _T_1074 = asSInt(_T_1073) node _T_1075 = eq(_T_1074, asSInt(UInt<1>(0h0))) node _T_1076 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1077 = cvt(_T_1076) node _T_1078 = and(_T_1077, asSInt(UInt<27>(0h4000000))) node _T_1079 = asSInt(_T_1078) node _T_1080 = eq(_T_1079, asSInt(UInt<1>(0h0))) node _T_1081 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1082 = cvt(_T_1081) node _T_1083 = and(_T_1082, asSInt(UInt<13>(0h1000))) node _T_1084 = asSInt(_T_1083) node _T_1085 = eq(_T_1084, asSInt(UInt<1>(0h0))) node _T_1086 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_1087 = cvt(_T_1086) node _T_1088 = and(_T_1087, asSInt(UInt<19>(0h40000))) node _T_1089 = asSInt(_T_1088) node _T_1090 = eq(_T_1089, asSInt(UInt<1>(0h0))) node _T_1091 = or(_T_1055, _T_1060) node _T_1092 = or(_T_1091, _T_1065) node _T_1093 = or(_T_1092, _T_1070) node _T_1094 = or(_T_1093, _T_1075) node _T_1095 = or(_T_1094, _T_1080) node _T_1096 = or(_T_1095, _T_1085) node _T_1097 = or(_T_1096, _T_1090) node _T_1098 = and(_T_1050, _T_1097) node _T_1099 = or(UInt<1>(0h0), _T_1046) node _T_1100 = or(_T_1099, _T_1098) node _T_1101 = asUInt(reset) node _T_1102 = eq(_T_1101, UInt<1>(0h0)) when _T_1102 : node _T_1103 = eq(_T_1100, UInt<1>(0h0)) when _T_1103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_1100, UInt<1>(0h1), "") : assert_20 node _T_1104 = asUInt(reset) node _T_1105 = eq(_T_1104, UInt<1>(0h0)) when _T_1105 : node _T_1106 = eq(source_ok, UInt<1>(0h0)) when _T_1106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_1107 = asUInt(reset) node _T_1108 = eq(_T_1107, UInt<1>(0h0)) when _T_1108 : node _T_1109 = eq(is_aligned, UInt<1>(0h0)) when _T_1109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_1110 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(_T_1110, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_1110, UInt<1>(0h1), "") : assert_23 node _T_1114 = eq(io.in.a.bits.mask, mask) node _T_1115 = asUInt(reset) node _T_1116 = eq(_T_1115, UInt<1>(0h0)) when _T_1116 : node _T_1117 = eq(_T_1114, UInt<1>(0h0)) when _T_1117 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_1114, UInt<1>(0h1), "") : assert_24 node _T_1118 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1119 = asUInt(reset) node _T_1120 = eq(_T_1119, UInt<1>(0h0)) when _T_1120 : node _T_1121 = eq(_T_1118, UInt<1>(0h0)) when _T_1121 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_1118, UInt<1>(0h1), "") : assert_25 node _T_1122 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_1122 : node _T_1123 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1124 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1125 = and(_T_1123, _T_1124) node _T_1126 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_72 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_72 = bits(_uncommonBits_T_72, 1, 0) node _T_1127 = shr(io.in.a.bits.source, 2) node _T_1128 = eq(_T_1127, UInt<7>(0h40)) node _T_1129 = leq(UInt<1>(0h0), uncommonBits_72) node _T_1130 = and(_T_1128, _T_1129) node _T_1131 = leq(uncommonBits_72, UInt<2>(0h3)) node _T_1132 = and(_T_1130, _T_1131) node _uncommonBits_T_73 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_73 = bits(_uncommonBits_T_73, 1, 0) node _T_1133 = shr(io.in.a.bits.source, 2) node _T_1134 = eq(_T_1133, UInt<7>(0h41)) node _T_1135 = leq(UInt<1>(0h0), uncommonBits_73) node _T_1136 = and(_T_1134, _T_1135) node _T_1137 = leq(uncommonBits_73, UInt<2>(0h3)) node _T_1138 = and(_T_1136, _T_1137) node _uncommonBits_T_74 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_74 = bits(_uncommonBits_T_74, 1, 0) node _T_1139 = shr(io.in.a.bits.source, 2) node _T_1140 = eq(_T_1139, UInt<7>(0h42)) node _T_1141 = leq(UInt<1>(0h0), uncommonBits_74) node _T_1142 = and(_T_1140, _T_1141) node _T_1143 = leq(uncommonBits_74, UInt<2>(0h3)) node _T_1144 = and(_T_1142, _T_1143) node _uncommonBits_T_75 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_75 = bits(_uncommonBits_T_75, 1, 0) node _T_1145 = shr(io.in.a.bits.source, 2) node _T_1146 = eq(_T_1145, UInt<7>(0h43)) node _T_1147 = leq(UInt<1>(0h0), uncommonBits_75) node _T_1148 = and(_T_1146, _T_1147) node _T_1149 = leq(uncommonBits_75, UInt<2>(0h3)) node _T_1150 = and(_T_1148, _T_1149) node _T_1151 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_1152 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_1153 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_76 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_76 = bits(_uncommonBits_T_76, 4, 0) node _T_1154 = shr(io.in.a.bits.source, 5) node _T_1155 = eq(_T_1154, UInt<1>(0h0)) node _T_1156 = leq(UInt<1>(0h0), uncommonBits_76) node _T_1157 = and(_T_1155, _T_1156) node _T_1158 = leq(uncommonBits_76, UInt<5>(0h1f)) node _T_1159 = and(_T_1157, _T_1158) node _uncommonBits_T_77 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_77 = bits(_uncommonBits_T_77, 4, 0) node _T_1160 = shr(io.in.a.bits.source, 5) node _T_1161 = eq(_T_1160, UInt<1>(0h1)) node _T_1162 = leq(UInt<1>(0h0), uncommonBits_77) node _T_1163 = and(_T_1161, _T_1162) node _T_1164 = leq(uncommonBits_77, UInt<5>(0h1f)) node _T_1165 = and(_T_1163, _T_1164) node _uncommonBits_T_78 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_78 = bits(_uncommonBits_T_78, 4, 0) node _T_1166 = shr(io.in.a.bits.source, 5) node _T_1167 = eq(_T_1166, UInt<2>(0h2)) node _T_1168 = leq(UInt<1>(0h0), uncommonBits_78) node _T_1169 = and(_T_1167, _T_1168) node _T_1170 = leq(uncommonBits_78, UInt<5>(0h1f)) node _T_1171 = and(_T_1169, _T_1170) node _uncommonBits_T_79 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_79 = bits(_uncommonBits_T_79, 4, 0) node _T_1172 = shr(io.in.a.bits.source, 5) node _T_1173 = eq(_T_1172, UInt<2>(0h3)) node _T_1174 = leq(UInt<1>(0h0), uncommonBits_79) node _T_1175 = and(_T_1173, _T_1174) node _T_1176 = leq(uncommonBits_79, UInt<5>(0h1f)) node _T_1177 = and(_T_1175, _T_1176) node _uncommonBits_T_80 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_80 = bits(_uncommonBits_T_80, 4, 0) node _T_1178 = shr(io.in.a.bits.source, 5) node _T_1179 = eq(_T_1178, UInt<3>(0h4)) node _T_1180 = leq(UInt<1>(0h0), uncommonBits_80) node _T_1181 = and(_T_1179, _T_1180) node _T_1182 = leq(uncommonBits_80, UInt<5>(0h1f)) node _T_1183 = and(_T_1181, _T_1182) node _uncommonBits_T_81 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_81 = bits(_uncommonBits_T_81, 4, 0) node _T_1184 = shr(io.in.a.bits.source, 5) node _T_1185 = eq(_T_1184, UInt<3>(0h5)) node _T_1186 = leq(UInt<1>(0h0), uncommonBits_81) node _T_1187 = and(_T_1185, _T_1186) node _T_1188 = leq(uncommonBits_81, UInt<5>(0h1f)) node _T_1189 = and(_T_1187, _T_1188) node _uncommonBits_T_82 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_82 = bits(_uncommonBits_T_82, 4, 0) node _T_1190 = shr(io.in.a.bits.source, 5) node _T_1191 = eq(_T_1190, UInt<3>(0h6)) node _T_1192 = leq(UInt<1>(0h0), uncommonBits_82) node _T_1193 = and(_T_1191, _T_1192) node _T_1194 = leq(uncommonBits_82, UInt<5>(0h1f)) node _T_1195 = and(_T_1193, _T_1194) node _uncommonBits_T_83 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_83 = bits(_uncommonBits_T_83, 4, 0) node _T_1196 = shr(io.in.a.bits.source, 5) node _T_1197 = eq(_T_1196, UInt<3>(0h7)) node _T_1198 = leq(UInt<1>(0h0), uncommonBits_83) node _T_1199 = and(_T_1197, _T_1198) node _T_1200 = leq(uncommonBits_83, UInt<5>(0h1f)) node _T_1201 = and(_T_1199, _T_1200) node _T_1202 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_1203 = or(_T_1126, _T_1132) node _T_1204 = or(_T_1203, _T_1138) node _T_1205 = or(_T_1204, _T_1144) node _T_1206 = or(_T_1205, _T_1150) node _T_1207 = or(_T_1206, _T_1151) node _T_1208 = or(_T_1207, _T_1152) node _T_1209 = or(_T_1208, _T_1153) node _T_1210 = or(_T_1209, _T_1159) node _T_1211 = or(_T_1210, _T_1165) node _T_1212 = or(_T_1211, _T_1171) node _T_1213 = or(_T_1212, _T_1177) node _T_1214 = or(_T_1213, _T_1183) node _T_1215 = or(_T_1214, _T_1189) node _T_1216 = or(_T_1215, _T_1195) node _T_1217 = or(_T_1216, _T_1201) node _T_1218 = or(_T_1217, _T_1202) node _T_1219 = and(_T_1125, _T_1218) node _T_1220 = or(UInt<1>(0h0), _T_1219) node _T_1221 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1222 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1223 = and(_T_1221, _T_1222) node _T_1224 = or(UInt<1>(0h0), _T_1223) node _T_1225 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1226 = cvt(_T_1225) node _T_1227 = and(_T_1226, asSInt(UInt<13>(0h1000))) node _T_1228 = asSInt(_T_1227) node _T_1229 = eq(_T_1228, asSInt(UInt<1>(0h0))) node _T_1230 = and(_T_1224, _T_1229) node _T_1231 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1232 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1233 = and(_T_1231, _T_1232) node _T_1234 = or(UInt<1>(0h0), _T_1233) node _T_1235 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1236 = cvt(_T_1235) node _T_1237 = and(_T_1236, asSInt(UInt<14>(0h2000))) node _T_1238 = asSInt(_T_1237) node _T_1239 = eq(_T_1238, asSInt(UInt<1>(0h0))) node _T_1240 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1241 = cvt(_T_1240) node _T_1242 = and(_T_1241, asSInt(UInt<18>(0h2f000))) node _T_1243 = asSInt(_T_1242) node _T_1244 = eq(_T_1243, asSInt(UInt<1>(0h0))) node _T_1245 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1246 = cvt(_T_1245) node _T_1247 = and(_T_1246, asSInt(UInt<17>(0h10000))) node _T_1248 = asSInt(_T_1247) node _T_1249 = eq(_T_1248, asSInt(UInt<1>(0h0))) node _T_1250 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1251 = cvt(_T_1250) node _T_1252 = and(_T_1251, asSInt(UInt<13>(0h1000))) node _T_1253 = asSInt(_T_1252) node _T_1254 = eq(_T_1253, asSInt(UInt<1>(0h0))) node _T_1255 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1256 = cvt(_T_1255) node _T_1257 = and(_T_1256, asSInt(UInt<27>(0h4000000))) node _T_1258 = asSInt(_T_1257) node _T_1259 = eq(_T_1258, asSInt(UInt<1>(0h0))) node _T_1260 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1261 = cvt(_T_1260) node _T_1262 = and(_T_1261, asSInt(UInt<13>(0h1000))) node _T_1263 = asSInt(_T_1262) node _T_1264 = eq(_T_1263, asSInt(UInt<1>(0h0))) node _T_1265 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_1266 = cvt(_T_1265) node _T_1267 = and(_T_1266, asSInt(UInt<19>(0h40000))) node _T_1268 = asSInt(_T_1267) node _T_1269 = eq(_T_1268, asSInt(UInt<1>(0h0))) node _T_1270 = or(_T_1239, _T_1244) node _T_1271 = or(_T_1270, _T_1249) node _T_1272 = or(_T_1271, _T_1254) node _T_1273 = or(_T_1272, _T_1259) node _T_1274 = or(_T_1273, _T_1264) node _T_1275 = or(_T_1274, _T_1269) node _T_1276 = and(_T_1234, _T_1275) node _T_1277 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1278 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1279 = cvt(_T_1278) node _T_1280 = and(_T_1279, asSInt(UInt<17>(0h10000))) node _T_1281 = asSInt(_T_1280) node _T_1282 = eq(_T_1281, asSInt(UInt<1>(0h0))) node _T_1283 = and(_T_1277, _T_1282) node _T_1284 = or(UInt<1>(0h0), _T_1230) node _T_1285 = or(_T_1284, _T_1276) node _T_1286 = or(_T_1285, _T_1283) node _T_1287 = and(_T_1220, _T_1286) node _T_1288 = asUInt(reset) node _T_1289 = eq(_T_1288, UInt<1>(0h0)) when _T_1289 : node _T_1290 = eq(_T_1287, UInt<1>(0h0)) when _T_1290 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_1287, UInt<1>(0h1), "") : assert_26 node _T_1291 = asUInt(reset) node _T_1292 = eq(_T_1291, UInt<1>(0h0)) when _T_1292 : node _T_1293 = eq(source_ok, UInt<1>(0h0)) when _T_1293 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_1294 = asUInt(reset) node _T_1295 = eq(_T_1294, UInt<1>(0h0)) when _T_1295 : node _T_1296 = eq(is_aligned, UInt<1>(0h0)) when _T_1296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_1297 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1298 = asUInt(reset) node _T_1299 = eq(_T_1298, UInt<1>(0h0)) when _T_1299 : node _T_1300 = eq(_T_1297, UInt<1>(0h0)) when _T_1300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_1297, UInt<1>(0h1), "") : assert_29 node _T_1301 = eq(io.in.a.bits.mask, mask) node _T_1302 = asUInt(reset) node _T_1303 = eq(_T_1302, UInt<1>(0h0)) when _T_1303 : node _T_1304 = eq(_T_1301, UInt<1>(0h0)) when _T_1304 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_1301, UInt<1>(0h1), "") : assert_30 node _T_1305 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_1305 : node _T_1306 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1307 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1308 = and(_T_1306, _T_1307) node _T_1309 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_84 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_84 = bits(_uncommonBits_T_84, 1, 0) node _T_1310 = shr(io.in.a.bits.source, 2) node _T_1311 = eq(_T_1310, UInt<7>(0h40)) node _T_1312 = leq(UInt<1>(0h0), uncommonBits_84) node _T_1313 = and(_T_1311, _T_1312) node _T_1314 = leq(uncommonBits_84, UInt<2>(0h3)) node _T_1315 = and(_T_1313, _T_1314) node _uncommonBits_T_85 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_85 = bits(_uncommonBits_T_85, 1, 0) node _T_1316 = shr(io.in.a.bits.source, 2) node _T_1317 = eq(_T_1316, UInt<7>(0h41)) node _T_1318 = leq(UInt<1>(0h0), uncommonBits_85) node _T_1319 = and(_T_1317, _T_1318) node _T_1320 = leq(uncommonBits_85, UInt<2>(0h3)) node _T_1321 = and(_T_1319, _T_1320) node _uncommonBits_T_86 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_86 = bits(_uncommonBits_T_86, 1, 0) node _T_1322 = shr(io.in.a.bits.source, 2) node _T_1323 = eq(_T_1322, UInt<7>(0h42)) node _T_1324 = leq(UInt<1>(0h0), uncommonBits_86) node _T_1325 = and(_T_1323, _T_1324) node _T_1326 = leq(uncommonBits_86, UInt<2>(0h3)) node _T_1327 = and(_T_1325, _T_1326) node _uncommonBits_T_87 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_87 = bits(_uncommonBits_T_87, 1, 0) node _T_1328 = shr(io.in.a.bits.source, 2) node _T_1329 = eq(_T_1328, UInt<7>(0h43)) node _T_1330 = leq(UInt<1>(0h0), uncommonBits_87) node _T_1331 = and(_T_1329, _T_1330) node _T_1332 = leq(uncommonBits_87, UInt<2>(0h3)) node _T_1333 = and(_T_1331, _T_1332) node _T_1334 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_1335 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_1336 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_88 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_88 = bits(_uncommonBits_T_88, 4, 0) node _T_1337 = shr(io.in.a.bits.source, 5) node _T_1338 = eq(_T_1337, UInt<1>(0h0)) node _T_1339 = leq(UInt<1>(0h0), uncommonBits_88) node _T_1340 = and(_T_1338, _T_1339) node _T_1341 = leq(uncommonBits_88, UInt<5>(0h1f)) node _T_1342 = and(_T_1340, _T_1341) node _uncommonBits_T_89 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_89 = bits(_uncommonBits_T_89, 4, 0) node _T_1343 = shr(io.in.a.bits.source, 5) node _T_1344 = eq(_T_1343, UInt<1>(0h1)) node _T_1345 = leq(UInt<1>(0h0), uncommonBits_89) node _T_1346 = and(_T_1344, _T_1345) node _T_1347 = leq(uncommonBits_89, UInt<5>(0h1f)) node _T_1348 = and(_T_1346, _T_1347) node _uncommonBits_T_90 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_90 = bits(_uncommonBits_T_90, 4, 0) node _T_1349 = shr(io.in.a.bits.source, 5) node _T_1350 = eq(_T_1349, UInt<2>(0h2)) node _T_1351 = leq(UInt<1>(0h0), uncommonBits_90) node _T_1352 = and(_T_1350, _T_1351) node _T_1353 = leq(uncommonBits_90, UInt<5>(0h1f)) node _T_1354 = and(_T_1352, _T_1353) node _uncommonBits_T_91 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_91 = bits(_uncommonBits_T_91, 4, 0) node _T_1355 = shr(io.in.a.bits.source, 5) node _T_1356 = eq(_T_1355, UInt<2>(0h3)) node _T_1357 = leq(UInt<1>(0h0), uncommonBits_91) node _T_1358 = and(_T_1356, _T_1357) node _T_1359 = leq(uncommonBits_91, UInt<5>(0h1f)) node _T_1360 = and(_T_1358, _T_1359) node _uncommonBits_T_92 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_92 = bits(_uncommonBits_T_92, 4, 0) node _T_1361 = shr(io.in.a.bits.source, 5) node _T_1362 = eq(_T_1361, UInt<3>(0h4)) node _T_1363 = leq(UInt<1>(0h0), uncommonBits_92) node _T_1364 = and(_T_1362, _T_1363) node _T_1365 = leq(uncommonBits_92, UInt<5>(0h1f)) node _T_1366 = and(_T_1364, _T_1365) node _uncommonBits_T_93 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_93 = bits(_uncommonBits_T_93, 4, 0) node _T_1367 = shr(io.in.a.bits.source, 5) node _T_1368 = eq(_T_1367, UInt<3>(0h5)) node _T_1369 = leq(UInt<1>(0h0), uncommonBits_93) node _T_1370 = and(_T_1368, _T_1369) node _T_1371 = leq(uncommonBits_93, UInt<5>(0h1f)) node _T_1372 = and(_T_1370, _T_1371) node _uncommonBits_T_94 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_94 = bits(_uncommonBits_T_94, 4, 0) node _T_1373 = shr(io.in.a.bits.source, 5) node _T_1374 = eq(_T_1373, UInt<3>(0h6)) node _T_1375 = leq(UInt<1>(0h0), uncommonBits_94) node _T_1376 = and(_T_1374, _T_1375) node _T_1377 = leq(uncommonBits_94, UInt<5>(0h1f)) node _T_1378 = and(_T_1376, _T_1377) node _uncommonBits_T_95 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_95 = bits(_uncommonBits_T_95, 4, 0) node _T_1379 = shr(io.in.a.bits.source, 5) node _T_1380 = eq(_T_1379, UInt<3>(0h7)) node _T_1381 = leq(UInt<1>(0h0), uncommonBits_95) node _T_1382 = and(_T_1380, _T_1381) node _T_1383 = leq(uncommonBits_95, UInt<5>(0h1f)) node _T_1384 = and(_T_1382, _T_1383) node _T_1385 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_1386 = or(_T_1309, _T_1315) node _T_1387 = or(_T_1386, _T_1321) node _T_1388 = or(_T_1387, _T_1327) node _T_1389 = or(_T_1388, _T_1333) node _T_1390 = or(_T_1389, _T_1334) node _T_1391 = or(_T_1390, _T_1335) node _T_1392 = or(_T_1391, _T_1336) node _T_1393 = or(_T_1392, _T_1342) node _T_1394 = or(_T_1393, _T_1348) node _T_1395 = or(_T_1394, _T_1354) node _T_1396 = or(_T_1395, _T_1360) node _T_1397 = or(_T_1396, _T_1366) node _T_1398 = or(_T_1397, _T_1372) node _T_1399 = or(_T_1398, _T_1378) node _T_1400 = or(_T_1399, _T_1384) node _T_1401 = or(_T_1400, _T_1385) node _T_1402 = and(_T_1308, _T_1401) node _T_1403 = or(UInt<1>(0h0), _T_1402) node _T_1404 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1405 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1406 = and(_T_1404, _T_1405) node _T_1407 = or(UInt<1>(0h0), _T_1406) node _T_1408 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1409 = cvt(_T_1408) node _T_1410 = and(_T_1409, asSInt(UInt<13>(0h1000))) node _T_1411 = asSInt(_T_1410) node _T_1412 = eq(_T_1411, asSInt(UInt<1>(0h0))) node _T_1413 = and(_T_1407, _T_1412) node _T_1414 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1415 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1416 = and(_T_1414, _T_1415) node _T_1417 = or(UInt<1>(0h0), _T_1416) node _T_1418 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1419 = cvt(_T_1418) node _T_1420 = and(_T_1419, asSInt(UInt<14>(0h2000))) node _T_1421 = asSInt(_T_1420) node _T_1422 = eq(_T_1421, asSInt(UInt<1>(0h0))) node _T_1423 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1424 = cvt(_T_1423) node _T_1425 = and(_T_1424, asSInt(UInt<18>(0h2f000))) node _T_1426 = asSInt(_T_1425) node _T_1427 = eq(_T_1426, asSInt(UInt<1>(0h0))) node _T_1428 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1429 = cvt(_T_1428) node _T_1430 = and(_T_1429, asSInt(UInt<17>(0h10000))) node _T_1431 = asSInt(_T_1430) node _T_1432 = eq(_T_1431, asSInt(UInt<1>(0h0))) node _T_1433 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1434 = cvt(_T_1433) node _T_1435 = and(_T_1434, asSInt(UInt<13>(0h1000))) node _T_1436 = asSInt(_T_1435) node _T_1437 = eq(_T_1436, asSInt(UInt<1>(0h0))) node _T_1438 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1439 = cvt(_T_1438) node _T_1440 = and(_T_1439, asSInt(UInt<27>(0h4000000))) node _T_1441 = asSInt(_T_1440) node _T_1442 = eq(_T_1441, asSInt(UInt<1>(0h0))) node _T_1443 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1444 = cvt(_T_1443) node _T_1445 = and(_T_1444, asSInt(UInt<13>(0h1000))) node _T_1446 = asSInt(_T_1445) node _T_1447 = eq(_T_1446, asSInt(UInt<1>(0h0))) node _T_1448 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_1449 = cvt(_T_1448) node _T_1450 = and(_T_1449, asSInt(UInt<19>(0h40000))) node _T_1451 = asSInt(_T_1450) node _T_1452 = eq(_T_1451, asSInt(UInt<1>(0h0))) node _T_1453 = or(_T_1422, _T_1427) node _T_1454 = or(_T_1453, _T_1432) node _T_1455 = or(_T_1454, _T_1437) node _T_1456 = or(_T_1455, _T_1442) node _T_1457 = or(_T_1456, _T_1447) node _T_1458 = or(_T_1457, _T_1452) node _T_1459 = and(_T_1417, _T_1458) node _T_1460 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1461 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1462 = cvt(_T_1461) node _T_1463 = and(_T_1462, asSInt(UInt<17>(0h10000))) node _T_1464 = asSInt(_T_1463) node _T_1465 = eq(_T_1464, asSInt(UInt<1>(0h0))) node _T_1466 = and(_T_1460, _T_1465) node _T_1467 = or(UInt<1>(0h0), _T_1413) node _T_1468 = or(_T_1467, _T_1459) node _T_1469 = or(_T_1468, _T_1466) node _T_1470 = and(_T_1403, _T_1469) node _T_1471 = asUInt(reset) node _T_1472 = eq(_T_1471, UInt<1>(0h0)) when _T_1472 : node _T_1473 = eq(_T_1470, UInt<1>(0h0)) when _T_1473 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_1470, UInt<1>(0h1), "") : assert_31 node _T_1474 = asUInt(reset) node _T_1475 = eq(_T_1474, UInt<1>(0h0)) when _T_1475 : node _T_1476 = eq(source_ok, UInt<1>(0h0)) when _T_1476 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_1477 = asUInt(reset) node _T_1478 = eq(_T_1477, UInt<1>(0h0)) when _T_1478 : node _T_1479 = eq(is_aligned, UInt<1>(0h0)) when _T_1479 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_1480 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1481 = asUInt(reset) node _T_1482 = eq(_T_1481, UInt<1>(0h0)) when _T_1482 : node _T_1483 = eq(_T_1480, UInt<1>(0h0)) when _T_1483 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_1480, UInt<1>(0h1), "") : assert_34 node _T_1484 = not(mask) node _T_1485 = and(io.in.a.bits.mask, _T_1484) node _T_1486 = eq(_T_1485, UInt<1>(0h0)) node _T_1487 = asUInt(reset) node _T_1488 = eq(_T_1487, UInt<1>(0h0)) when _T_1488 : node _T_1489 = eq(_T_1486, UInt<1>(0h0)) when _T_1489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_1486, UInt<1>(0h1), "") : assert_35 node _T_1490 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_1490 : node _T_1491 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1492 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1493 = and(_T_1491, _T_1492) node _T_1494 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_96 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_96 = bits(_uncommonBits_T_96, 1, 0) node _T_1495 = shr(io.in.a.bits.source, 2) node _T_1496 = eq(_T_1495, UInt<7>(0h40)) node _T_1497 = leq(UInt<1>(0h0), uncommonBits_96) node _T_1498 = and(_T_1496, _T_1497) node _T_1499 = leq(uncommonBits_96, UInt<2>(0h3)) node _T_1500 = and(_T_1498, _T_1499) node _uncommonBits_T_97 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_97 = bits(_uncommonBits_T_97, 1, 0) node _T_1501 = shr(io.in.a.bits.source, 2) node _T_1502 = eq(_T_1501, UInt<7>(0h41)) node _T_1503 = leq(UInt<1>(0h0), uncommonBits_97) node _T_1504 = and(_T_1502, _T_1503) node _T_1505 = leq(uncommonBits_97, UInt<2>(0h3)) node _T_1506 = and(_T_1504, _T_1505) node _uncommonBits_T_98 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_98 = bits(_uncommonBits_T_98, 1, 0) node _T_1507 = shr(io.in.a.bits.source, 2) node _T_1508 = eq(_T_1507, UInt<7>(0h42)) node _T_1509 = leq(UInt<1>(0h0), uncommonBits_98) node _T_1510 = and(_T_1508, _T_1509) node _T_1511 = leq(uncommonBits_98, UInt<2>(0h3)) node _T_1512 = and(_T_1510, _T_1511) node _uncommonBits_T_99 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_99 = bits(_uncommonBits_T_99, 1, 0) node _T_1513 = shr(io.in.a.bits.source, 2) node _T_1514 = eq(_T_1513, UInt<7>(0h43)) node _T_1515 = leq(UInt<1>(0h0), uncommonBits_99) node _T_1516 = and(_T_1514, _T_1515) node _T_1517 = leq(uncommonBits_99, UInt<2>(0h3)) node _T_1518 = and(_T_1516, _T_1517) node _T_1519 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_1520 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_1521 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_100 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_100 = bits(_uncommonBits_T_100, 4, 0) node _T_1522 = shr(io.in.a.bits.source, 5) node _T_1523 = eq(_T_1522, UInt<1>(0h0)) node _T_1524 = leq(UInt<1>(0h0), uncommonBits_100) node _T_1525 = and(_T_1523, _T_1524) node _T_1526 = leq(uncommonBits_100, UInt<5>(0h1f)) node _T_1527 = and(_T_1525, _T_1526) node _uncommonBits_T_101 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_101 = bits(_uncommonBits_T_101, 4, 0) node _T_1528 = shr(io.in.a.bits.source, 5) node _T_1529 = eq(_T_1528, UInt<1>(0h1)) node _T_1530 = leq(UInt<1>(0h0), uncommonBits_101) node _T_1531 = and(_T_1529, _T_1530) node _T_1532 = leq(uncommonBits_101, UInt<5>(0h1f)) node _T_1533 = and(_T_1531, _T_1532) node _uncommonBits_T_102 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_102 = bits(_uncommonBits_T_102, 4, 0) node _T_1534 = shr(io.in.a.bits.source, 5) node _T_1535 = eq(_T_1534, UInt<2>(0h2)) node _T_1536 = leq(UInt<1>(0h0), uncommonBits_102) node _T_1537 = and(_T_1535, _T_1536) node _T_1538 = leq(uncommonBits_102, UInt<5>(0h1f)) node _T_1539 = and(_T_1537, _T_1538) node _uncommonBits_T_103 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_103 = bits(_uncommonBits_T_103, 4, 0) node _T_1540 = shr(io.in.a.bits.source, 5) node _T_1541 = eq(_T_1540, UInt<2>(0h3)) node _T_1542 = leq(UInt<1>(0h0), uncommonBits_103) node _T_1543 = and(_T_1541, _T_1542) node _T_1544 = leq(uncommonBits_103, UInt<5>(0h1f)) node _T_1545 = and(_T_1543, _T_1544) node _uncommonBits_T_104 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_104 = bits(_uncommonBits_T_104, 4, 0) node _T_1546 = shr(io.in.a.bits.source, 5) node _T_1547 = eq(_T_1546, UInt<3>(0h4)) node _T_1548 = leq(UInt<1>(0h0), uncommonBits_104) node _T_1549 = and(_T_1547, _T_1548) node _T_1550 = leq(uncommonBits_104, UInt<5>(0h1f)) node _T_1551 = and(_T_1549, _T_1550) node _uncommonBits_T_105 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_105 = bits(_uncommonBits_T_105, 4, 0) node _T_1552 = shr(io.in.a.bits.source, 5) node _T_1553 = eq(_T_1552, UInt<3>(0h5)) node _T_1554 = leq(UInt<1>(0h0), uncommonBits_105) node _T_1555 = and(_T_1553, _T_1554) node _T_1556 = leq(uncommonBits_105, UInt<5>(0h1f)) node _T_1557 = and(_T_1555, _T_1556) node _uncommonBits_T_106 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_106 = bits(_uncommonBits_T_106, 4, 0) node _T_1558 = shr(io.in.a.bits.source, 5) node _T_1559 = eq(_T_1558, UInt<3>(0h6)) node _T_1560 = leq(UInt<1>(0h0), uncommonBits_106) node _T_1561 = and(_T_1559, _T_1560) node _T_1562 = leq(uncommonBits_106, UInt<5>(0h1f)) node _T_1563 = and(_T_1561, _T_1562) node _uncommonBits_T_107 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_107 = bits(_uncommonBits_T_107, 4, 0) node _T_1564 = shr(io.in.a.bits.source, 5) node _T_1565 = eq(_T_1564, UInt<3>(0h7)) node _T_1566 = leq(UInt<1>(0h0), uncommonBits_107) node _T_1567 = and(_T_1565, _T_1566) node _T_1568 = leq(uncommonBits_107, UInt<5>(0h1f)) node _T_1569 = and(_T_1567, _T_1568) node _T_1570 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_1571 = or(_T_1494, _T_1500) node _T_1572 = or(_T_1571, _T_1506) node _T_1573 = or(_T_1572, _T_1512) node _T_1574 = or(_T_1573, _T_1518) node _T_1575 = or(_T_1574, _T_1519) node _T_1576 = or(_T_1575, _T_1520) node _T_1577 = or(_T_1576, _T_1521) node _T_1578 = or(_T_1577, _T_1527) node _T_1579 = or(_T_1578, _T_1533) node _T_1580 = or(_T_1579, _T_1539) node _T_1581 = or(_T_1580, _T_1545) node _T_1582 = or(_T_1581, _T_1551) node _T_1583 = or(_T_1582, _T_1557) node _T_1584 = or(_T_1583, _T_1563) node _T_1585 = or(_T_1584, _T_1569) node _T_1586 = or(_T_1585, _T_1570) node _T_1587 = and(_T_1493, _T_1586) node _T_1588 = or(UInt<1>(0h0), _T_1587) node _T_1589 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1590 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1591 = and(_T_1589, _T_1590) node _T_1592 = or(UInt<1>(0h0), _T_1591) node _T_1593 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1594 = cvt(_T_1593) node _T_1595 = and(_T_1594, asSInt(UInt<15>(0h5000))) node _T_1596 = asSInt(_T_1595) node _T_1597 = eq(_T_1596, asSInt(UInt<1>(0h0))) node _T_1598 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1599 = cvt(_T_1598) node _T_1600 = and(_T_1599, asSInt(UInt<13>(0h1000))) node _T_1601 = asSInt(_T_1600) node _T_1602 = eq(_T_1601, asSInt(UInt<1>(0h0))) node _T_1603 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_1604 = cvt(_T_1603) node _T_1605 = and(_T_1604, asSInt(UInt<19>(0h40000))) node _T_1606 = asSInt(_T_1605) node _T_1607 = eq(_T_1606, asSInt(UInt<1>(0h0))) node _T_1608 = or(_T_1597, _T_1602) node _T_1609 = or(_T_1608, _T_1607) node _T_1610 = and(_T_1592, _T_1609) node _T_1611 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1612 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1613 = cvt(_T_1612) node _T_1614 = and(_T_1613, asSInt(UInt<13>(0h1000))) node _T_1615 = asSInt(_T_1614) node _T_1616 = eq(_T_1615, asSInt(UInt<1>(0h0))) node _T_1617 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1618 = cvt(_T_1617) node _T_1619 = and(_T_1618, asSInt(UInt<17>(0h10000))) node _T_1620 = asSInt(_T_1619) node _T_1621 = eq(_T_1620, asSInt(UInt<1>(0h0))) node _T_1622 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1623 = cvt(_T_1622) node _T_1624 = and(_T_1623, asSInt(UInt<18>(0h2f000))) node _T_1625 = asSInt(_T_1624) node _T_1626 = eq(_T_1625, asSInt(UInt<1>(0h0))) node _T_1627 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1628 = cvt(_T_1627) node _T_1629 = and(_T_1628, asSInt(UInt<17>(0h10000))) node _T_1630 = asSInt(_T_1629) node _T_1631 = eq(_T_1630, asSInt(UInt<1>(0h0))) node _T_1632 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1633 = cvt(_T_1632) node _T_1634 = and(_T_1633, asSInt(UInt<13>(0h1000))) node _T_1635 = asSInt(_T_1634) node _T_1636 = eq(_T_1635, asSInt(UInt<1>(0h0))) node _T_1637 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1638 = cvt(_T_1637) node _T_1639 = and(_T_1638, asSInt(UInt<27>(0h4000000))) node _T_1640 = asSInt(_T_1639) node _T_1641 = eq(_T_1640, asSInt(UInt<1>(0h0))) node _T_1642 = or(_T_1616, _T_1621) node _T_1643 = or(_T_1642, _T_1626) node _T_1644 = or(_T_1643, _T_1631) node _T_1645 = or(_T_1644, _T_1636) node _T_1646 = or(_T_1645, _T_1641) node _T_1647 = and(_T_1611, _T_1646) node _T_1648 = or(UInt<1>(0h0), _T_1610) node _T_1649 = or(_T_1648, _T_1647) node _T_1650 = and(_T_1588, _T_1649) node _T_1651 = asUInt(reset) node _T_1652 = eq(_T_1651, UInt<1>(0h0)) when _T_1652 : node _T_1653 = eq(_T_1650, UInt<1>(0h0)) when _T_1653 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1650, UInt<1>(0h1), "") : assert_36 node _T_1654 = asUInt(reset) node _T_1655 = eq(_T_1654, UInt<1>(0h0)) when _T_1655 : node _T_1656 = eq(source_ok, UInt<1>(0h0)) when _T_1656 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1657 = asUInt(reset) node _T_1658 = eq(_T_1657, UInt<1>(0h0)) when _T_1658 : node _T_1659 = eq(is_aligned, UInt<1>(0h0)) when _T_1659 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1660 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1661 = asUInt(reset) node _T_1662 = eq(_T_1661, UInt<1>(0h0)) when _T_1662 : node _T_1663 = eq(_T_1660, UInt<1>(0h0)) when _T_1663 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1660, UInt<1>(0h1), "") : assert_39 node _T_1664 = eq(io.in.a.bits.mask, mask) node _T_1665 = asUInt(reset) node _T_1666 = eq(_T_1665, UInt<1>(0h0)) when _T_1666 : node _T_1667 = eq(_T_1664, UInt<1>(0h0)) when _T_1667 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1664, UInt<1>(0h1), "") : assert_40 node _T_1668 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1668 : node _T_1669 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1670 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1671 = and(_T_1669, _T_1670) node _T_1672 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_108 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_108 = bits(_uncommonBits_T_108, 1, 0) node _T_1673 = shr(io.in.a.bits.source, 2) node _T_1674 = eq(_T_1673, UInt<7>(0h40)) node _T_1675 = leq(UInt<1>(0h0), uncommonBits_108) node _T_1676 = and(_T_1674, _T_1675) node _T_1677 = leq(uncommonBits_108, UInt<2>(0h3)) node _T_1678 = and(_T_1676, _T_1677) node _uncommonBits_T_109 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_109 = bits(_uncommonBits_T_109, 1, 0) node _T_1679 = shr(io.in.a.bits.source, 2) node _T_1680 = eq(_T_1679, UInt<7>(0h41)) node _T_1681 = leq(UInt<1>(0h0), uncommonBits_109) node _T_1682 = and(_T_1680, _T_1681) node _T_1683 = leq(uncommonBits_109, UInt<2>(0h3)) node _T_1684 = and(_T_1682, _T_1683) node _uncommonBits_T_110 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_110 = bits(_uncommonBits_T_110, 1, 0) node _T_1685 = shr(io.in.a.bits.source, 2) node _T_1686 = eq(_T_1685, UInt<7>(0h42)) node _T_1687 = leq(UInt<1>(0h0), uncommonBits_110) node _T_1688 = and(_T_1686, _T_1687) node _T_1689 = leq(uncommonBits_110, UInt<2>(0h3)) node _T_1690 = and(_T_1688, _T_1689) node _uncommonBits_T_111 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_111 = bits(_uncommonBits_T_111, 1, 0) node _T_1691 = shr(io.in.a.bits.source, 2) node _T_1692 = eq(_T_1691, UInt<7>(0h43)) node _T_1693 = leq(UInt<1>(0h0), uncommonBits_111) node _T_1694 = and(_T_1692, _T_1693) node _T_1695 = leq(uncommonBits_111, UInt<2>(0h3)) node _T_1696 = and(_T_1694, _T_1695) node _T_1697 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_1698 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_1699 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_112 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_112 = bits(_uncommonBits_T_112, 4, 0) node _T_1700 = shr(io.in.a.bits.source, 5) node _T_1701 = eq(_T_1700, UInt<1>(0h0)) node _T_1702 = leq(UInt<1>(0h0), uncommonBits_112) node _T_1703 = and(_T_1701, _T_1702) node _T_1704 = leq(uncommonBits_112, UInt<5>(0h1f)) node _T_1705 = and(_T_1703, _T_1704) node _uncommonBits_T_113 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_113 = bits(_uncommonBits_T_113, 4, 0) node _T_1706 = shr(io.in.a.bits.source, 5) node _T_1707 = eq(_T_1706, UInt<1>(0h1)) node _T_1708 = leq(UInt<1>(0h0), uncommonBits_113) node _T_1709 = and(_T_1707, _T_1708) node _T_1710 = leq(uncommonBits_113, UInt<5>(0h1f)) node _T_1711 = and(_T_1709, _T_1710) node _uncommonBits_T_114 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_114 = bits(_uncommonBits_T_114, 4, 0) node _T_1712 = shr(io.in.a.bits.source, 5) node _T_1713 = eq(_T_1712, UInt<2>(0h2)) node _T_1714 = leq(UInt<1>(0h0), uncommonBits_114) node _T_1715 = and(_T_1713, _T_1714) node _T_1716 = leq(uncommonBits_114, UInt<5>(0h1f)) node _T_1717 = and(_T_1715, _T_1716) node _uncommonBits_T_115 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_115 = bits(_uncommonBits_T_115, 4, 0) node _T_1718 = shr(io.in.a.bits.source, 5) node _T_1719 = eq(_T_1718, UInt<2>(0h3)) node _T_1720 = leq(UInt<1>(0h0), uncommonBits_115) node _T_1721 = and(_T_1719, _T_1720) node _T_1722 = leq(uncommonBits_115, UInt<5>(0h1f)) node _T_1723 = and(_T_1721, _T_1722) node _uncommonBits_T_116 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_116 = bits(_uncommonBits_T_116, 4, 0) node _T_1724 = shr(io.in.a.bits.source, 5) node _T_1725 = eq(_T_1724, UInt<3>(0h4)) node _T_1726 = leq(UInt<1>(0h0), uncommonBits_116) node _T_1727 = and(_T_1725, _T_1726) node _T_1728 = leq(uncommonBits_116, UInt<5>(0h1f)) node _T_1729 = and(_T_1727, _T_1728) node _uncommonBits_T_117 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_117 = bits(_uncommonBits_T_117, 4, 0) node _T_1730 = shr(io.in.a.bits.source, 5) node _T_1731 = eq(_T_1730, UInt<3>(0h5)) node _T_1732 = leq(UInt<1>(0h0), uncommonBits_117) node _T_1733 = and(_T_1731, _T_1732) node _T_1734 = leq(uncommonBits_117, UInt<5>(0h1f)) node _T_1735 = and(_T_1733, _T_1734) node _uncommonBits_T_118 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_118 = bits(_uncommonBits_T_118, 4, 0) node _T_1736 = shr(io.in.a.bits.source, 5) node _T_1737 = eq(_T_1736, UInt<3>(0h6)) node _T_1738 = leq(UInt<1>(0h0), uncommonBits_118) node _T_1739 = and(_T_1737, _T_1738) node _T_1740 = leq(uncommonBits_118, UInt<5>(0h1f)) node _T_1741 = and(_T_1739, _T_1740) node _uncommonBits_T_119 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_119 = bits(_uncommonBits_T_119, 4, 0) node _T_1742 = shr(io.in.a.bits.source, 5) node _T_1743 = eq(_T_1742, UInt<3>(0h7)) node _T_1744 = leq(UInt<1>(0h0), uncommonBits_119) node _T_1745 = and(_T_1743, _T_1744) node _T_1746 = leq(uncommonBits_119, UInt<5>(0h1f)) node _T_1747 = and(_T_1745, _T_1746) node _T_1748 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_1749 = or(_T_1672, _T_1678) node _T_1750 = or(_T_1749, _T_1684) node _T_1751 = or(_T_1750, _T_1690) node _T_1752 = or(_T_1751, _T_1696) node _T_1753 = or(_T_1752, _T_1697) node _T_1754 = or(_T_1753, _T_1698) node _T_1755 = or(_T_1754, _T_1699) node _T_1756 = or(_T_1755, _T_1705) node _T_1757 = or(_T_1756, _T_1711) node _T_1758 = or(_T_1757, _T_1717) node _T_1759 = or(_T_1758, _T_1723) node _T_1760 = or(_T_1759, _T_1729) node _T_1761 = or(_T_1760, _T_1735) node _T_1762 = or(_T_1761, _T_1741) node _T_1763 = or(_T_1762, _T_1747) node _T_1764 = or(_T_1763, _T_1748) node _T_1765 = and(_T_1671, _T_1764) node _T_1766 = or(UInt<1>(0h0), _T_1765) node _T_1767 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1768 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1769 = and(_T_1767, _T_1768) node _T_1770 = or(UInt<1>(0h0), _T_1769) node _T_1771 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1772 = cvt(_T_1771) node _T_1773 = and(_T_1772, asSInt(UInt<15>(0h5000))) node _T_1774 = asSInt(_T_1773) node _T_1775 = eq(_T_1774, asSInt(UInt<1>(0h0))) node _T_1776 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1777 = cvt(_T_1776) node _T_1778 = and(_T_1777, asSInt(UInt<13>(0h1000))) node _T_1779 = asSInt(_T_1778) node _T_1780 = eq(_T_1779, asSInt(UInt<1>(0h0))) node _T_1781 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_1782 = cvt(_T_1781) node _T_1783 = and(_T_1782, asSInt(UInt<19>(0h40000))) node _T_1784 = asSInt(_T_1783) node _T_1785 = eq(_T_1784, asSInt(UInt<1>(0h0))) node _T_1786 = or(_T_1775, _T_1780) node _T_1787 = or(_T_1786, _T_1785) node _T_1788 = and(_T_1770, _T_1787) node _T_1789 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1790 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1791 = cvt(_T_1790) node _T_1792 = and(_T_1791, asSInt(UInt<13>(0h1000))) node _T_1793 = asSInt(_T_1792) node _T_1794 = eq(_T_1793, asSInt(UInt<1>(0h0))) node _T_1795 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1796 = cvt(_T_1795) node _T_1797 = and(_T_1796, asSInt(UInt<17>(0h10000))) node _T_1798 = asSInt(_T_1797) node _T_1799 = eq(_T_1798, asSInt(UInt<1>(0h0))) node _T_1800 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1801 = cvt(_T_1800) node _T_1802 = and(_T_1801, asSInt(UInt<18>(0h2f000))) node _T_1803 = asSInt(_T_1802) node _T_1804 = eq(_T_1803, asSInt(UInt<1>(0h0))) node _T_1805 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1806 = cvt(_T_1805) node _T_1807 = and(_T_1806, asSInt(UInt<17>(0h10000))) node _T_1808 = asSInt(_T_1807) node _T_1809 = eq(_T_1808, asSInt(UInt<1>(0h0))) node _T_1810 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1811 = cvt(_T_1810) node _T_1812 = and(_T_1811, asSInt(UInt<13>(0h1000))) node _T_1813 = asSInt(_T_1812) node _T_1814 = eq(_T_1813, asSInt(UInt<1>(0h0))) node _T_1815 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1816 = cvt(_T_1815) node _T_1817 = and(_T_1816, asSInt(UInt<27>(0h4000000))) node _T_1818 = asSInt(_T_1817) node _T_1819 = eq(_T_1818, asSInt(UInt<1>(0h0))) node _T_1820 = or(_T_1794, _T_1799) node _T_1821 = or(_T_1820, _T_1804) node _T_1822 = or(_T_1821, _T_1809) node _T_1823 = or(_T_1822, _T_1814) node _T_1824 = or(_T_1823, _T_1819) node _T_1825 = and(_T_1789, _T_1824) node _T_1826 = or(UInt<1>(0h0), _T_1788) node _T_1827 = or(_T_1826, _T_1825) node _T_1828 = and(_T_1766, _T_1827) node _T_1829 = asUInt(reset) node _T_1830 = eq(_T_1829, UInt<1>(0h0)) when _T_1830 : node _T_1831 = eq(_T_1828, UInt<1>(0h0)) when _T_1831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1828, UInt<1>(0h1), "") : assert_41 node _T_1832 = asUInt(reset) node _T_1833 = eq(_T_1832, UInt<1>(0h0)) when _T_1833 : node _T_1834 = eq(source_ok, UInt<1>(0h0)) when _T_1834 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1835 = asUInt(reset) node _T_1836 = eq(_T_1835, UInt<1>(0h0)) when _T_1836 : node _T_1837 = eq(is_aligned, UInt<1>(0h0)) when _T_1837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1838 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1839 = asUInt(reset) node _T_1840 = eq(_T_1839, UInt<1>(0h0)) when _T_1840 : node _T_1841 = eq(_T_1838, UInt<1>(0h0)) when _T_1841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1838, UInt<1>(0h1), "") : assert_44 node _T_1842 = eq(io.in.a.bits.mask, mask) node _T_1843 = asUInt(reset) node _T_1844 = eq(_T_1843, UInt<1>(0h0)) when _T_1844 : node _T_1845 = eq(_T_1842, UInt<1>(0h0)) when _T_1845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1842, UInt<1>(0h1), "") : assert_45 node _T_1846 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1846 : node _T_1847 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1848 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1849 = and(_T_1847, _T_1848) node _T_1850 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_120 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_120 = bits(_uncommonBits_T_120, 1, 0) node _T_1851 = shr(io.in.a.bits.source, 2) node _T_1852 = eq(_T_1851, UInt<7>(0h40)) node _T_1853 = leq(UInt<1>(0h0), uncommonBits_120) node _T_1854 = and(_T_1852, _T_1853) node _T_1855 = leq(uncommonBits_120, UInt<2>(0h3)) node _T_1856 = and(_T_1854, _T_1855) node _uncommonBits_T_121 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_121 = bits(_uncommonBits_T_121, 1, 0) node _T_1857 = shr(io.in.a.bits.source, 2) node _T_1858 = eq(_T_1857, UInt<7>(0h41)) node _T_1859 = leq(UInt<1>(0h0), uncommonBits_121) node _T_1860 = and(_T_1858, _T_1859) node _T_1861 = leq(uncommonBits_121, UInt<2>(0h3)) node _T_1862 = and(_T_1860, _T_1861) node _uncommonBits_T_122 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_122 = bits(_uncommonBits_T_122, 1, 0) node _T_1863 = shr(io.in.a.bits.source, 2) node _T_1864 = eq(_T_1863, UInt<7>(0h42)) node _T_1865 = leq(UInt<1>(0h0), uncommonBits_122) node _T_1866 = and(_T_1864, _T_1865) node _T_1867 = leq(uncommonBits_122, UInt<2>(0h3)) node _T_1868 = and(_T_1866, _T_1867) node _uncommonBits_T_123 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_123 = bits(_uncommonBits_T_123, 1, 0) node _T_1869 = shr(io.in.a.bits.source, 2) node _T_1870 = eq(_T_1869, UInt<7>(0h43)) node _T_1871 = leq(UInt<1>(0h0), uncommonBits_123) node _T_1872 = and(_T_1870, _T_1871) node _T_1873 = leq(uncommonBits_123, UInt<2>(0h3)) node _T_1874 = and(_T_1872, _T_1873) node _T_1875 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_1876 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_1877 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_124 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_124 = bits(_uncommonBits_T_124, 4, 0) node _T_1878 = shr(io.in.a.bits.source, 5) node _T_1879 = eq(_T_1878, UInt<1>(0h0)) node _T_1880 = leq(UInt<1>(0h0), uncommonBits_124) node _T_1881 = and(_T_1879, _T_1880) node _T_1882 = leq(uncommonBits_124, UInt<5>(0h1f)) node _T_1883 = and(_T_1881, _T_1882) node _uncommonBits_T_125 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_125 = bits(_uncommonBits_T_125, 4, 0) node _T_1884 = shr(io.in.a.bits.source, 5) node _T_1885 = eq(_T_1884, UInt<1>(0h1)) node _T_1886 = leq(UInt<1>(0h0), uncommonBits_125) node _T_1887 = and(_T_1885, _T_1886) node _T_1888 = leq(uncommonBits_125, UInt<5>(0h1f)) node _T_1889 = and(_T_1887, _T_1888) node _uncommonBits_T_126 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_126 = bits(_uncommonBits_T_126, 4, 0) node _T_1890 = shr(io.in.a.bits.source, 5) node _T_1891 = eq(_T_1890, UInt<2>(0h2)) node _T_1892 = leq(UInt<1>(0h0), uncommonBits_126) node _T_1893 = and(_T_1891, _T_1892) node _T_1894 = leq(uncommonBits_126, UInt<5>(0h1f)) node _T_1895 = and(_T_1893, _T_1894) node _uncommonBits_T_127 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_127 = bits(_uncommonBits_T_127, 4, 0) node _T_1896 = shr(io.in.a.bits.source, 5) node _T_1897 = eq(_T_1896, UInt<2>(0h3)) node _T_1898 = leq(UInt<1>(0h0), uncommonBits_127) node _T_1899 = and(_T_1897, _T_1898) node _T_1900 = leq(uncommonBits_127, UInt<5>(0h1f)) node _T_1901 = and(_T_1899, _T_1900) node _uncommonBits_T_128 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_128 = bits(_uncommonBits_T_128, 4, 0) node _T_1902 = shr(io.in.a.bits.source, 5) node _T_1903 = eq(_T_1902, UInt<3>(0h4)) node _T_1904 = leq(UInt<1>(0h0), uncommonBits_128) node _T_1905 = and(_T_1903, _T_1904) node _T_1906 = leq(uncommonBits_128, UInt<5>(0h1f)) node _T_1907 = and(_T_1905, _T_1906) node _uncommonBits_T_129 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_129 = bits(_uncommonBits_T_129, 4, 0) node _T_1908 = shr(io.in.a.bits.source, 5) node _T_1909 = eq(_T_1908, UInt<3>(0h5)) node _T_1910 = leq(UInt<1>(0h0), uncommonBits_129) node _T_1911 = and(_T_1909, _T_1910) node _T_1912 = leq(uncommonBits_129, UInt<5>(0h1f)) node _T_1913 = and(_T_1911, _T_1912) node _uncommonBits_T_130 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_130 = bits(_uncommonBits_T_130, 4, 0) node _T_1914 = shr(io.in.a.bits.source, 5) node _T_1915 = eq(_T_1914, UInt<3>(0h6)) node _T_1916 = leq(UInt<1>(0h0), uncommonBits_130) node _T_1917 = and(_T_1915, _T_1916) node _T_1918 = leq(uncommonBits_130, UInt<5>(0h1f)) node _T_1919 = and(_T_1917, _T_1918) node _uncommonBits_T_131 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_131 = bits(_uncommonBits_T_131, 4, 0) node _T_1920 = shr(io.in.a.bits.source, 5) node _T_1921 = eq(_T_1920, UInt<3>(0h7)) node _T_1922 = leq(UInt<1>(0h0), uncommonBits_131) node _T_1923 = and(_T_1921, _T_1922) node _T_1924 = leq(uncommonBits_131, UInt<5>(0h1f)) node _T_1925 = and(_T_1923, _T_1924) node _T_1926 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_1927 = or(_T_1850, _T_1856) node _T_1928 = or(_T_1927, _T_1862) node _T_1929 = or(_T_1928, _T_1868) node _T_1930 = or(_T_1929, _T_1874) node _T_1931 = or(_T_1930, _T_1875) node _T_1932 = or(_T_1931, _T_1876) node _T_1933 = or(_T_1932, _T_1877) node _T_1934 = or(_T_1933, _T_1883) node _T_1935 = or(_T_1934, _T_1889) node _T_1936 = or(_T_1935, _T_1895) node _T_1937 = or(_T_1936, _T_1901) node _T_1938 = or(_T_1937, _T_1907) node _T_1939 = or(_T_1938, _T_1913) node _T_1940 = or(_T_1939, _T_1919) node _T_1941 = or(_T_1940, _T_1925) node _T_1942 = or(_T_1941, _T_1926) node _T_1943 = and(_T_1849, _T_1942) node _T_1944 = or(UInt<1>(0h0), _T_1943) node _T_1945 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1946 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1947 = and(_T_1945, _T_1946) node _T_1948 = or(UInt<1>(0h0), _T_1947) node _T_1949 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1950 = cvt(_T_1949) node _T_1951 = and(_T_1950, asSInt(UInt<13>(0h1000))) node _T_1952 = asSInt(_T_1951) node _T_1953 = eq(_T_1952, asSInt(UInt<1>(0h0))) node _T_1954 = and(_T_1948, _T_1953) node _T_1955 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1956 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1957 = cvt(_T_1956) node _T_1958 = and(_T_1957, asSInt(UInt<14>(0h2000))) node _T_1959 = asSInt(_T_1958) node _T_1960 = eq(_T_1959, asSInt(UInt<1>(0h0))) node _T_1961 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1962 = cvt(_T_1961) node _T_1963 = and(_T_1962, asSInt(UInt<17>(0h10000))) node _T_1964 = asSInt(_T_1963) node _T_1965 = eq(_T_1964, asSInt(UInt<1>(0h0))) node _T_1966 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1967 = cvt(_T_1966) node _T_1968 = and(_T_1967, asSInt(UInt<18>(0h2f000))) node _T_1969 = asSInt(_T_1968) node _T_1970 = eq(_T_1969, asSInt(UInt<1>(0h0))) node _T_1971 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1972 = cvt(_T_1971) node _T_1973 = and(_T_1972, asSInt(UInt<17>(0h10000))) node _T_1974 = asSInt(_T_1973) node _T_1975 = eq(_T_1974, asSInt(UInt<1>(0h0))) node _T_1976 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1977 = cvt(_T_1976) node _T_1978 = and(_T_1977, asSInt(UInt<13>(0h1000))) node _T_1979 = asSInt(_T_1978) node _T_1980 = eq(_T_1979, asSInt(UInt<1>(0h0))) node _T_1981 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1982 = cvt(_T_1981) node _T_1983 = and(_T_1982, asSInt(UInt<27>(0h4000000))) node _T_1984 = asSInt(_T_1983) node _T_1985 = eq(_T_1984, asSInt(UInt<1>(0h0))) node _T_1986 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1987 = cvt(_T_1986) node _T_1988 = and(_T_1987, asSInt(UInt<13>(0h1000))) node _T_1989 = asSInt(_T_1988) node _T_1990 = eq(_T_1989, asSInt(UInt<1>(0h0))) node _T_1991 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_1992 = cvt(_T_1991) node _T_1993 = and(_T_1992, asSInt(UInt<19>(0h40000))) node _T_1994 = asSInt(_T_1993) node _T_1995 = eq(_T_1994, asSInt(UInt<1>(0h0))) node _T_1996 = or(_T_1960, _T_1965) node _T_1997 = or(_T_1996, _T_1970) node _T_1998 = or(_T_1997, _T_1975) node _T_1999 = or(_T_1998, _T_1980) node _T_2000 = or(_T_1999, _T_1985) node _T_2001 = or(_T_2000, _T_1990) node _T_2002 = or(_T_2001, _T_1995) node _T_2003 = and(_T_1955, _T_2002) node _T_2004 = or(UInt<1>(0h0), _T_1954) node _T_2005 = or(_T_2004, _T_2003) node _T_2006 = and(_T_1944, _T_2005) node _T_2007 = asUInt(reset) node _T_2008 = eq(_T_2007, UInt<1>(0h0)) when _T_2008 : node _T_2009 = eq(_T_2006, UInt<1>(0h0)) when _T_2009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_2006, UInt<1>(0h1), "") : assert_46 node _T_2010 = asUInt(reset) node _T_2011 = eq(_T_2010, UInt<1>(0h0)) when _T_2011 : node _T_2012 = eq(source_ok, UInt<1>(0h0)) when _T_2012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_2013 = asUInt(reset) node _T_2014 = eq(_T_2013, UInt<1>(0h0)) when _T_2014 : node _T_2015 = eq(is_aligned, UInt<1>(0h0)) when _T_2015 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_2016 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_2017 = asUInt(reset) node _T_2018 = eq(_T_2017, UInt<1>(0h0)) when _T_2018 : node _T_2019 = eq(_T_2016, UInt<1>(0h0)) when _T_2019 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_2016, UInt<1>(0h1), "") : assert_49 node _T_2020 = eq(io.in.a.bits.mask, mask) node _T_2021 = asUInt(reset) node _T_2022 = eq(_T_2021, UInt<1>(0h0)) when _T_2022 : node _T_2023 = eq(_T_2020, UInt<1>(0h0)) when _T_2023 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_2020, UInt<1>(0h1), "") : assert_50 node _T_2024 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_2025 = asUInt(reset) node _T_2026 = eq(_T_2025, UInt<1>(0h0)) when _T_2026 : node _T_2027 = eq(_T_2024, UInt<1>(0h0)) when _T_2027 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_2024, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_2028 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2029 = asUInt(reset) node _T_2030 = eq(_T_2029, UInt<1>(0h0)) when _T_2030 : node _T_2031 = eq(_T_2028, UInt<1>(0h0)) when _T_2031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_2028, UInt<1>(0h1), "") : assert_52 node _source_ok_T_92 = eq(io.in.d.bits.source, UInt<9>(0h110)) node _source_ok_uncommonBits_T_12 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_12 = bits(_source_ok_uncommonBits_T_12, 1, 0) node _source_ok_T_93 = shr(io.in.d.bits.source, 2) node _source_ok_T_94 = eq(_source_ok_T_93, UInt<7>(0h40)) node _source_ok_T_95 = leq(UInt<1>(0h0), source_ok_uncommonBits_12) node _source_ok_T_96 = and(_source_ok_T_94, _source_ok_T_95) node _source_ok_T_97 = leq(source_ok_uncommonBits_12, UInt<2>(0h3)) node _source_ok_T_98 = and(_source_ok_T_96, _source_ok_T_97) node _source_ok_uncommonBits_T_13 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_13 = bits(_source_ok_uncommonBits_T_13, 1, 0) node _source_ok_T_99 = shr(io.in.d.bits.source, 2) node _source_ok_T_100 = eq(_source_ok_T_99, UInt<7>(0h41)) node _source_ok_T_101 = leq(UInt<1>(0h0), source_ok_uncommonBits_13) node _source_ok_T_102 = and(_source_ok_T_100, _source_ok_T_101) node _source_ok_T_103 = leq(source_ok_uncommonBits_13, UInt<2>(0h3)) node _source_ok_T_104 = and(_source_ok_T_102, _source_ok_T_103) node _source_ok_uncommonBits_T_14 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_14 = bits(_source_ok_uncommonBits_T_14, 1, 0) node _source_ok_T_105 = shr(io.in.d.bits.source, 2) node _source_ok_T_106 = eq(_source_ok_T_105, UInt<7>(0h42)) node _source_ok_T_107 = leq(UInt<1>(0h0), source_ok_uncommonBits_14) node _source_ok_T_108 = and(_source_ok_T_106, _source_ok_T_107) node _source_ok_T_109 = leq(source_ok_uncommonBits_14, UInt<2>(0h3)) node _source_ok_T_110 = and(_source_ok_T_108, _source_ok_T_109) node _source_ok_uncommonBits_T_15 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_15 = bits(_source_ok_uncommonBits_T_15, 1, 0) node _source_ok_T_111 = shr(io.in.d.bits.source, 2) node _source_ok_T_112 = eq(_source_ok_T_111, UInt<7>(0h43)) node _source_ok_T_113 = leq(UInt<1>(0h0), source_ok_uncommonBits_15) node _source_ok_T_114 = and(_source_ok_T_112, _source_ok_T_113) node _source_ok_T_115 = leq(source_ok_uncommonBits_15, UInt<2>(0h3)) node _source_ok_T_116 = and(_source_ok_T_114, _source_ok_T_115) node _source_ok_T_117 = eq(io.in.d.bits.source, UInt<9>(0h120)) node _source_ok_T_118 = eq(io.in.d.bits.source, UInt<9>(0h121)) node _source_ok_T_119 = eq(io.in.d.bits.source, UInt<9>(0h122)) node _source_ok_uncommonBits_T_16 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_16 = bits(_source_ok_uncommonBits_T_16, 4, 0) node _source_ok_T_120 = shr(io.in.d.bits.source, 5) node _source_ok_T_121 = eq(_source_ok_T_120, UInt<1>(0h0)) node _source_ok_T_122 = leq(UInt<1>(0h0), source_ok_uncommonBits_16) node _source_ok_T_123 = and(_source_ok_T_121, _source_ok_T_122) node _source_ok_T_124 = leq(source_ok_uncommonBits_16, UInt<5>(0h1f)) node _source_ok_T_125 = and(_source_ok_T_123, _source_ok_T_124) node _source_ok_uncommonBits_T_17 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_17 = bits(_source_ok_uncommonBits_T_17, 4, 0) node _source_ok_T_126 = shr(io.in.d.bits.source, 5) node _source_ok_T_127 = eq(_source_ok_T_126, UInt<1>(0h1)) node _source_ok_T_128 = leq(UInt<1>(0h0), source_ok_uncommonBits_17) node _source_ok_T_129 = and(_source_ok_T_127, _source_ok_T_128) node _source_ok_T_130 = leq(source_ok_uncommonBits_17, UInt<5>(0h1f)) node _source_ok_T_131 = and(_source_ok_T_129, _source_ok_T_130) node _source_ok_uncommonBits_T_18 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_18 = bits(_source_ok_uncommonBits_T_18, 4, 0) node _source_ok_T_132 = shr(io.in.d.bits.source, 5) node _source_ok_T_133 = eq(_source_ok_T_132, UInt<2>(0h2)) node _source_ok_T_134 = leq(UInt<1>(0h0), source_ok_uncommonBits_18) node _source_ok_T_135 = and(_source_ok_T_133, _source_ok_T_134) node _source_ok_T_136 = leq(source_ok_uncommonBits_18, UInt<5>(0h1f)) node _source_ok_T_137 = and(_source_ok_T_135, _source_ok_T_136) node _source_ok_uncommonBits_T_19 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_19 = bits(_source_ok_uncommonBits_T_19, 4, 0) node _source_ok_T_138 = shr(io.in.d.bits.source, 5) node _source_ok_T_139 = eq(_source_ok_T_138, UInt<2>(0h3)) node _source_ok_T_140 = leq(UInt<1>(0h0), source_ok_uncommonBits_19) node _source_ok_T_141 = and(_source_ok_T_139, _source_ok_T_140) node _source_ok_T_142 = leq(source_ok_uncommonBits_19, UInt<5>(0h1f)) node _source_ok_T_143 = and(_source_ok_T_141, _source_ok_T_142) node _source_ok_uncommonBits_T_20 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_20 = bits(_source_ok_uncommonBits_T_20, 4, 0) node _source_ok_T_144 = shr(io.in.d.bits.source, 5) node _source_ok_T_145 = eq(_source_ok_T_144, UInt<3>(0h4)) node _source_ok_T_146 = leq(UInt<1>(0h0), source_ok_uncommonBits_20) node _source_ok_T_147 = and(_source_ok_T_145, _source_ok_T_146) node _source_ok_T_148 = leq(source_ok_uncommonBits_20, UInt<5>(0h1f)) node _source_ok_T_149 = and(_source_ok_T_147, _source_ok_T_148) node _source_ok_uncommonBits_T_21 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_21 = bits(_source_ok_uncommonBits_T_21, 4, 0) node _source_ok_T_150 = shr(io.in.d.bits.source, 5) node _source_ok_T_151 = eq(_source_ok_T_150, UInt<3>(0h5)) node _source_ok_T_152 = leq(UInt<1>(0h0), source_ok_uncommonBits_21) node _source_ok_T_153 = and(_source_ok_T_151, _source_ok_T_152) node _source_ok_T_154 = leq(source_ok_uncommonBits_21, UInt<5>(0h1f)) node _source_ok_T_155 = and(_source_ok_T_153, _source_ok_T_154) node _source_ok_uncommonBits_T_22 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_22 = bits(_source_ok_uncommonBits_T_22, 4, 0) node _source_ok_T_156 = shr(io.in.d.bits.source, 5) node _source_ok_T_157 = eq(_source_ok_T_156, UInt<3>(0h6)) node _source_ok_T_158 = leq(UInt<1>(0h0), source_ok_uncommonBits_22) node _source_ok_T_159 = and(_source_ok_T_157, _source_ok_T_158) node _source_ok_T_160 = leq(source_ok_uncommonBits_22, UInt<5>(0h1f)) node _source_ok_T_161 = and(_source_ok_T_159, _source_ok_T_160) node _source_ok_uncommonBits_T_23 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_23 = bits(_source_ok_uncommonBits_T_23, 4, 0) node _source_ok_T_162 = shr(io.in.d.bits.source, 5) node _source_ok_T_163 = eq(_source_ok_T_162, UInt<3>(0h7)) node _source_ok_T_164 = leq(UInt<1>(0h0), source_ok_uncommonBits_23) node _source_ok_T_165 = and(_source_ok_T_163, _source_ok_T_164) node _source_ok_T_166 = leq(source_ok_uncommonBits_23, UInt<5>(0h1f)) node _source_ok_T_167 = and(_source_ok_T_165, _source_ok_T_166) node _source_ok_T_168 = eq(io.in.d.bits.source, UInt<10>(0h200)) wire _source_ok_WIRE_1 : UInt<1>[17] connect _source_ok_WIRE_1[0], _source_ok_T_92 connect _source_ok_WIRE_1[1], _source_ok_T_98 connect _source_ok_WIRE_1[2], _source_ok_T_104 connect _source_ok_WIRE_1[3], _source_ok_T_110 connect _source_ok_WIRE_1[4], _source_ok_T_116 connect _source_ok_WIRE_1[5], _source_ok_T_117 connect _source_ok_WIRE_1[6], _source_ok_T_118 connect _source_ok_WIRE_1[7], _source_ok_T_119 connect _source_ok_WIRE_1[8], _source_ok_T_125 connect _source_ok_WIRE_1[9], _source_ok_T_131 connect _source_ok_WIRE_1[10], _source_ok_T_137 connect _source_ok_WIRE_1[11], _source_ok_T_143 connect _source_ok_WIRE_1[12], _source_ok_T_149 connect _source_ok_WIRE_1[13], _source_ok_T_155 connect _source_ok_WIRE_1[14], _source_ok_T_161 connect _source_ok_WIRE_1[15], _source_ok_T_167 connect _source_ok_WIRE_1[16], _source_ok_T_168 node _source_ok_T_169 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_170 = or(_source_ok_T_169, _source_ok_WIRE_1[2]) node _source_ok_T_171 = or(_source_ok_T_170, _source_ok_WIRE_1[3]) node _source_ok_T_172 = or(_source_ok_T_171, _source_ok_WIRE_1[4]) node _source_ok_T_173 = or(_source_ok_T_172, _source_ok_WIRE_1[5]) node _source_ok_T_174 = or(_source_ok_T_173, _source_ok_WIRE_1[6]) node _source_ok_T_175 = or(_source_ok_T_174, _source_ok_WIRE_1[7]) node _source_ok_T_176 = or(_source_ok_T_175, _source_ok_WIRE_1[8]) node _source_ok_T_177 = or(_source_ok_T_176, _source_ok_WIRE_1[9]) node _source_ok_T_178 = or(_source_ok_T_177, _source_ok_WIRE_1[10]) node _source_ok_T_179 = or(_source_ok_T_178, _source_ok_WIRE_1[11]) node _source_ok_T_180 = or(_source_ok_T_179, _source_ok_WIRE_1[12]) node _source_ok_T_181 = or(_source_ok_T_180, _source_ok_WIRE_1[13]) node _source_ok_T_182 = or(_source_ok_T_181, _source_ok_WIRE_1[14]) node _source_ok_T_183 = or(_source_ok_T_182, _source_ok_WIRE_1[15]) node source_ok_1 = or(_source_ok_T_183, _source_ok_WIRE_1[16]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_2032 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_2032 : node _T_2033 = asUInt(reset) node _T_2034 = eq(_T_2033, UInt<1>(0h0)) when _T_2034 : node _T_2035 = eq(source_ok_1, UInt<1>(0h0)) when _T_2035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_2036 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_2037 = asUInt(reset) node _T_2038 = eq(_T_2037, UInt<1>(0h0)) when _T_2038 : node _T_2039 = eq(_T_2036, UInt<1>(0h0)) when _T_2039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_2036, UInt<1>(0h1), "") : assert_54 node _T_2040 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2041 = asUInt(reset) node _T_2042 = eq(_T_2041, UInt<1>(0h0)) when _T_2042 : node _T_2043 = eq(_T_2040, UInt<1>(0h0)) when _T_2043 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_2040, UInt<1>(0h1), "") : assert_55 node _T_2044 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_2045 = asUInt(reset) node _T_2046 = eq(_T_2045, UInt<1>(0h0)) when _T_2046 : node _T_2047 = eq(_T_2044, UInt<1>(0h0)) when _T_2047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_2044, UInt<1>(0h1), "") : assert_56 node _T_2048 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2049 = asUInt(reset) node _T_2050 = eq(_T_2049, UInt<1>(0h0)) when _T_2050 : node _T_2051 = eq(_T_2048, UInt<1>(0h0)) when _T_2051 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_2048, UInt<1>(0h1), "") : assert_57 node _T_2052 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_2052 : node _T_2053 = asUInt(reset) node _T_2054 = eq(_T_2053, UInt<1>(0h0)) when _T_2054 : node _T_2055 = eq(source_ok_1, UInt<1>(0h0)) when _T_2055 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_2056 = asUInt(reset) node _T_2057 = eq(_T_2056, UInt<1>(0h0)) when _T_2057 : node _T_2058 = eq(sink_ok, UInt<1>(0h0)) when _T_2058 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_2059 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_2060 = asUInt(reset) node _T_2061 = eq(_T_2060, UInt<1>(0h0)) when _T_2061 : node _T_2062 = eq(_T_2059, UInt<1>(0h0)) when _T_2062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_2059, UInt<1>(0h1), "") : assert_60 node _T_2063 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_2064 = asUInt(reset) node _T_2065 = eq(_T_2064, UInt<1>(0h0)) when _T_2065 : node _T_2066 = eq(_T_2063, UInt<1>(0h0)) when _T_2066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_2063, UInt<1>(0h1), "") : assert_61 node _T_2067 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_2068 = asUInt(reset) node _T_2069 = eq(_T_2068, UInt<1>(0h0)) when _T_2069 : node _T_2070 = eq(_T_2067, UInt<1>(0h0)) when _T_2070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_2067, UInt<1>(0h1), "") : assert_62 node _T_2071 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_2072 = asUInt(reset) node _T_2073 = eq(_T_2072, UInt<1>(0h0)) when _T_2073 : node _T_2074 = eq(_T_2071, UInt<1>(0h0)) when _T_2074 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_2071, UInt<1>(0h1), "") : assert_63 node _T_2075 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2076 = or(UInt<1>(0h1), _T_2075) node _T_2077 = asUInt(reset) node _T_2078 = eq(_T_2077, UInt<1>(0h0)) when _T_2078 : node _T_2079 = eq(_T_2076, UInt<1>(0h0)) when _T_2079 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_2076, UInt<1>(0h1), "") : assert_64 node _T_2080 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_2080 : node _T_2081 = asUInt(reset) node _T_2082 = eq(_T_2081, UInt<1>(0h0)) when _T_2082 : node _T_2083 = eq(source_ok_1, UInt<1>(0h0)) when _T_2083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_2084 = asUInt(reset) node _T_2085 = eq(_T_2084, UInt<1>(0h0)) when _T_2085 : node _T_2086 = eq(sink_ok, UInt<1>(0h0)) when _T_2086 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_2087 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_2088 = asUInt(reset) node _T_2089 = eq(_T_2088, UInt<1>(0h0)) when _T_2089 : node _T_2090 = eq(_T_2087, UInt<1>(0h0)) when _T_2090 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_2087, UInt<1>(0h1), "") : assert_67 node _T_2091 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_2092 = asUInt(reset) node _T_2093 = eq(_T_2092, UInt<1>(0h0)) when _T_2093 : node _T_2094 = eq(_T_2091, UInt<1>(0h0)) when _T_2094 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_2091, UInt<1>(0h1), "") : assert_68 node _T_2095 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_2096 = asUInt(reset) node _T_2097 = eq(_T_2096, UInt<1>(0h0)) when _T_2097 : node _T_2098 = eq(_T_2095, UInt<1>(0h0)) when _T_2098 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_2095, UInt<1>(0h1), "") : assert_69 node _T_2099 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2100 = or(_T_2099, io.in.d.bits.corrupt) node _T_2101 = asUInt(reset) node _T_2102 = eq(_T_2101, UInt<1>(0h0)) when _T_2102 : node _T_2103 = eq(_T_2100, UInt<1>(0h0)) when _T_2103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_2100, UInt<1>(0h1), "") : assert_70 node _T_2104 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2105 = or(UInt<1>(0h1), _T_2104) node _T_2106 = asUInt(reset) node _T_2107 = eq(_T_2106, UInt<1>(0h0)) when _T_2107 : node _T_2108 = eq(_T_2105, UInt<1>(0h0)) when _T_2108 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_2105, UInt<1>(0h1), "") : assert_71 node _T_2109 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_2109 : node _T_2110 = asUInt(reset) node _T_2111 = eq(_T_2110, UInt<1>(0h0)) when _T_2111 : node _T_2112 = eq(source_ok_1, UInt<1>(0h0)) when _T_2112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_2113 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2114 = asUInt(reset) node _T_2115 = eq(_T_2114, UInt<1>(0h0)) when _T_2115 : node _T_2116 = eq(_T_2113, UInt<1>(0h0)) when _T_2116 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_2113, UInt<1>(0h1), "") : assert_73 node _T_2117 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_2118 = asUInt(reset) node _T_2119 = eq(_T_2118, UInt<1>(0h0)) when _T_2119 : node _T_2120 = eq(_T_2117, UInt<1>(0h0)) when _T_2120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_2117, UInt<1>(0h1), "") : assert_74 node _T_2121 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2122 = or(UInt<1>(0h1), _T_2121) node _T_2123 = asUInt(reset) node _T_2124 = eq(_T_2123, UInt<1>(0h0)) when _T_2124 : node _T_2125 = eq(_T_2122, UInt<1>(0h0)) when _T_2125 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_2122, UInt<1>(0h1), "") : assert_75 node _T_2126 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_2126 : node _T_2127 = asUInt(reset) node _T_2128 = eq(_T_2127, UInt<1>(0h0)) when _T_2128 : node _T_2129 = eq(source_ok_1, UInt<1>(0h0)) when _T_2129 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_2130 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2131 = asUInt(reset) node _T_2132 = eq(_T_2131, UInt<1>(0h0)) when _T_2132 : node _T_2133 = eq(_T_2130, UInt<1>(0h0)) when _T_2133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_2130, UInt<1>(0h1), "") : assert_77 node _T_2134 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2135 = or(_T_2134, io.in.d.bits.corrupt) node _T_2136 = asUInt(reset) node _T_2137 = eq(_T_2136, UInt<1>(0h0)) when _T_2137 : node _T_2138 = eq(_T_2135, UInt<1>(0h0)) when _T_2138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_2135, UInt<1>(0h1), "") : assert_78 node _T_2139 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2140 = or(UInt<1>(0h1), _T_2139) node _T_2141 = asUInt(reset) node _T_2142 = eq(_T_2141, UInt<1>(0h0)) when _T_2142 : node _T_2143 = eq(_T_2140, UInt<1>(0h0)) when _T_2143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_2140, UInt<1>(0h1), "") : assert_79 node _T_2144 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_2144 : node _T_2145 = asUInt(reset) node _T_2146 = eq(_T_2145, UInt<1>(0h0)) when _T_2146 : node _T_2147 = eq(source_ok_1, UInt<1>(0h0)) when _T_2147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_2148 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2149 = asUInt(reset) node _T_2150 = eq(_T_2149, UInt<1>(0h0)) when _T_2150 : node _T_2151 = eq(_T_2148, UInt<1>(0h0)) when _T_2151 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_2148, UInt<1>(0h1), "") : assert_81 node _T_2152 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_2153 = asUInt(reset) node _T_2154 = eq(_T_2153, UInt<1>(0h0)) when _T_2154 : node _T_2155 = eq(_T_2152, UInt<1>(0h0)) when _T_2155 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_2152, UInt<1>(0h1), "") : assert_82 node _T_2156 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2157 = or(UInt<1>(0h1), _T_2156) node _T_2158 = asUInt(reset) node _T_2159 = eq(_T_2158, UInt<1>(0h0)) when _T_2159 : node _T_2160 = eq(_T_2157, UInt<1>(0h0)) when _T_2160 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_2157, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<29>(0h0) connect _WIRE_4.bits.source, UInt<10>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_2161 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_2162 = asUInt(reset) node _T_2163 = eq(_T_2162, UInt<1>(0h0)) when _T_2163 : node _T_2164 = eq(_T_2161, UInt<1>(0h0)) when _T_2164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_2161, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<10>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_2165 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_2166 = asUInt(reset) node _T_2167 = eq(_T_2166, UInt<1>(0h0)) when _T_2167 : node _T_2168 = eq(_T_2165, UInt<1>(0h0)) when _T_2168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_2165, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_2169 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_2170 = asUInt(reset) node _T_2171 = eq(_T_2170, UInt<1>(0h0)) when _T_2171 : node _T_2172 = eq(_T_2169, UInt<1>(0h0)) when _T_2172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_2169, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2173 = eq(a_first, UInt<1>(0h0)) node _T_2174 = and(io.in.a.valid, _T_2173) when _T_2174 : node _T_2175 = eq(io.in.a.bits.opcode, opcode) node _T_2176 = asUInt(reset) node _T_2177 = eq(_T_2176, UInt<1>(0h0)) when _T_2177 : node _T_2178 = eq(_T_2175, UInt<1>(0h0)) when _T_2178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_2175, UInt<1>(0h1), "") : assert_87 node _T_2179 = eq(io.in.a.bits.param, param) node _T_2180 = asUInt(reset) node _T_2181 = eq(_T_2180, UInt<1>(0h0)) when _T_2181 : node _T_2182 = eq(_T_2179, UInt<1>(0h0)) when _T_2182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_2179, UInt<1>(0h1), "") : assert_88 node _T_2183 = eq(io.in.a.bits.size, size) node _T_2184 = asUInt(reset) node _T_2185 = eq(_T_2184, UInt<1>(0h0)) when _T_2185 : node _T_2186 = eq(_T_2183, UInt<1>(0h0)) when _T_2186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_2183, UInt<1>(0h1), "") : assert_89 node _T_2187 = eq(io.in.a.bits.source, source) node _T_2188 = asUInt(reset) node _T_2189 = eq(_T_2188, UInt<1>(0h0)) when _T_2189 : node _T_2190 = eq(_T_2187, UInt<1>(0h0)) when _T_2190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_2187, UInt<1>(0h1), "") : assert_90 node _T_2191 = eq(io.in.a.bits.address, address) node _T_2192 = asUInt(reset) node _T_2193 = eq(_T_2192, UInt<1>(0h0)) when _T_2193 : node _T_2194 = eq(_T_2191, UInt<1>(0h0)) when _T_2194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_2191, UInt<1>(0h1), "") : assert_91 node _T_2195 = and(io.in.a.ready, io.in.a.valid) node _T_2196 = and(_T_2195, a_first) when _T_2196 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2197 = eq(d_first, UInt<1>(0h0)) node _T_2198 = and(io.in.d.valid, _T_2197) when _T_2198 : node _T_2199 = eq(io.in.d.bits.opcode, opcode_1) node _T_2200 = asUInt(reset) node _T_2201 = eq(_T_2200, UInt<1>(0h0)) when _T_2201 : node _T_2202 = eq(_T_2199, UInt<1>(0h0)) when _T_2202 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_2199, UInt<1>(0h1), "") : assert_92 node _T_2203 = eq(io.in.d.bits.param, param_1) node _T_2204 = asUInt(reset) node _T_2205 = eq(_T_2204, UInt<1>(0h0)) when _T_2205 : node _T_2206 = eq(_T_2203, UInt<1>(0h0)) when _T_2206 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_2203, UInt<1>(0h1), "") : assert_93 node _T_2207 = eq(io.in.d.bits.size, size_1) node _T_2208 = asUInt(reset) node _T_2209 = eq(_T_2208, UInt<1>(0h0)) when _T_2209 : node _T_2210 = eq(_T_2207, UInt<1>(0h0)) when _T_2210 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_2207, UInt<1>(0h1), "") : assert_94 node _T_2211 = eq(io.in.d.bits.source, source_1) node _T_2212 = asUInt(reset) node _T_2213 = eq(_T_2212, UInt<1>(0h0)) when _T_2213 : node _T_2214 = eq(_T_2211, UInt<1>(0h0)) when _T_2214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_2211, UInt<1>(0h1), "") : assert_95 node _T_2215 = eq(io.in.d.bits.sink, sink) node _T_2216 = asUInt(reset) node _T_2217 = eq(_T_2216, UInt<1>(0h0)) when _T_2217 : node _T_2218 = eq(_T_2215, UInt<1>(0h0)) when _T_2218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_2215, UInt<1>(0h1), "") : assert_96 node _T_2219 = eq(io.in.d.bits.denied, denied) node _T_2220 = asUInt(reset) node _T_2221 = eq(_T_2220, UInt<1>(0h0)) when _T_2221 : node _T_2222 = eq(_T_2219, UInt<1>(0h0)) when _T_2222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_2219, UInt<1>(0h1), "") : assert_97 node _T_2223 = and(io.in.d.ready, io.in.d.valid) node _T_2224 = and(_T_2223, d_first) when _T_2224 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<513>, clock, reset, UInt<513>(0h0) regreset inflight_opcodes : UInt<2052>, clock, reset, UInt<2052>(0h0) regreset inflight_sizes : UInt<4104>, clock, reset, UInt<4104>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<513> connect a_set, UInt<513>(0h0) wire a_set_wo_ready : UInt<513> connect a_set_wo_ready, UInt<513>(0h0) wire a_opcodes_set : UInt<2052> connect a_opcodes_set, UInt<2052>(0h0) wire a_sizes_set : UInt<4104> connect a_sizes_set, UInt<4104>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_2225 = and(io.in.a.valid, a_first_1) node _T_2226 = and(_T_2225, UInt<1>(0h1)) when _T_2226 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2227 = and(io.in.a.ready, io.in.a.valid) node _T_2228 = and(_T_2227, a_first_1) node _T_2229 = and(_T_2228, UInt<1>(0h1)) when _T_2229 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2230 = dshr(inflight, io.in.a.bits.source) node _T_2231 = bits(_T_2230, 0, 0) node _T_2232 = eq(_T_2231, UInt<1>(0h0)) node _T_2233 = asUInt(reset) node _T_2234 = eq(_T_2233, UInt<1>(0h0)) when _T_2234 : node _T_2235 = eq(_T_2232, UInt<1>(0h0)) when _T_2235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_2232, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<513> connect d_clr, UInt<513>(0h0) wire d_clr_wo_ready : UInt<513> connect d_clr_wo_ready, UInt<513>(0h0) wire d_opcodes_clr : UInt<2052> connect d_opcodes_clr, UInt<2052>(0h0) wire d_sizes_clr : UInt<4104> connect d_sizes_clr, UInt<4104>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2236 = and(io.in.d.valid, d_first_1) node _T_2237 = and(_T_2236, UInt<1>(0h1)) node _T_2238 = eq(d_release_ack, UInt<1>(0h0)) node _T_2239 = and(_T_2237, _T_2238) when _T_2239 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2240 = and(io.in.d.ready, io.in.d.valid) node _T_2241 = and(_T_2240, d_first_1) node _T_2242 = and(_T_2241, UInt<1>(0h1)) node _T_2243 = eq(d_release_ack, UInt<1>(0h0)) node _T_2244 = and(_T_2242, _T_2243) when _T_2244 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2245 = and(io.in.d.valid, d_first_1) node _T_2246 = and(_T_2245, UInt<1>(0h1)) node _T_2247 = eq(d_release_ack, UInt<1>(0h0)) node _T_2248 = and(_T_2246, _T_2247) when _T_2248 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2249 = dshr(inflight, io.in.d.bits.source) node _T_2250 = bits(_T_2249, 0, 0) node _T_2251 = or(_T_2250, same_cycle_resp) node _T_2252 = asUInt(reset) node _T_2253 = eq(_T_2252, UInt<1>(0h0)) when _T_2253 : node _T_2254 = eq(_T_2251, UInt<1>(0h0)) when _T_2254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_2251, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_2255 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2256 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2257 = or(_T_2255, _T_2256) node _T_2258 = asUInt(reset) node _T_2259 = eq(_T_2258, UInt<1>(0h0)) when _T_2259 : node _T_2260 = eq(_T_2257, UInt<1>(0h0)) when _T_2260 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_2257, UInt<1>(0h1), "") : assert_100 node _T_2261 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2262 = asUInt(reset) node _T_2263 = eq(_T_2262, UInt<1>(0h0)) when _T_2263 : node _T_2264 = eq(_T_2261, UInt<1>(0h0)) when _T_2264 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_2261, UInt<1>(0h1), "") : assert_101 else : node _T_2265 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2266 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2267 = or(_T_2265, _T_2266) node _T_2268 = asUInt(reset) node _T_2269 = eq(_T_2268, UInt<1>(0h0)) when _T_2269 : node _T_2270 = eq(_T_2267, UInt<1>(0h0)) when _T_2270 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_2267, UInt<1>(0h1), "") : assert_102 node _T_2271 = eq(io.in.d.bits.size, a_size_lookup) node _T_2272 = asUInt(reset) node _T_2273 = eq(_T_2272, UInt<1>(0h0)) when _T_2273 : node _T_2274 = eq(_T_2271, UInt<1>(0h0)) when _T_2274 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_2271, UInt<1>(0h1), "") : assert_103 node _T_2275 = and(io.in.d.valid, d_first_1) node _T_2276 = and(_T_2275, a_first_1) node _T_2277 = and(_T_2276, io.in.a.valid) node _T_2278 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2279 = and(_T_2277, _T_2278) node _T_2280 = eq(d_release_ack, UInt<1>(0h0)) node _T_2281 = and(_T_2279, _T_2280) when _T_2281 : node _T_2282 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2283 = or(_T_2282, io.in.a.ready) node _T_2284 = asUInt(reset) node _T_2285 = eq(_T_2284, UInt<1>(0h0)) when _T_2285 : node _T_2286 = eq(_T_2283, UInt<1>(0h0)) when _T_2286 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_2283, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_48 node _T_2287 = orr(inflight) node _T_2288 = eq(_T_2287, UInt<1>(0h0)) node _T_2289 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2290 = or(_T_2288, _T_2289) node _T_2291 = lt(watchdog, plusarg_reader.out) node _T_2292 = or(_T_2290, _T_2291) node _T_2293 = asUInt(reset) node _T_2294 = eq(_T_2293, UInt<1>(0h0)) when _T_2294 : node _T_2295 = eq(_T_2292, UInt<1>(0h0)) when _T_2295 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_2292, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2296 = and(io.in.a.ready, io.in.a.valid) node _T_2297 = and(io.in.d.ready, io.in.d.valid) node _T_2298 = or(_T_2296, _T_2297) when _T_2298 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<513>, clock, reset, UInt<513>(0h0) regreset inflight_opcodes_1 : UInt<2052>, clock, reset, UInt<2052>(0h0) regreset inflight_sizes_1 : UInt<4104>, clock, reset, UInt<4104>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<10>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<10>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<513> connect c_set, UInt<513>(0h0) wire c_set_wo_ready : UInt<513> connect c_set_wo_ready, UInt<513>(0h0) wire c_opcodes_set : UInt<2052> connect c_opcodes_set, UInt<2052>(0h0) wire c_sizes_set : UInt<4104> connect c_sizes_set, UInt<4104>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<10>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_2299 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<10>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_2300 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_2301 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_2302 = and(_T_2300, _T_2301) node _T_2303 = and(_T_2299, _T_2302) when _T_2303 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<10>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<10>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_2304 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_2305 = and(_T_2304, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<10>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_2306 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_2307 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_2308 = and(_T_2306, _T_2307) node _T_2309 = and(_T_2305, _T_2308) when _T_2309 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<10>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<10>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<10>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<10>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<10>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<10>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_2310 = dshr(inflight_1, _WIRE_19.bits.source) node _T_2311 = bits(_T_2310, 0, 0) node _T_2312 = eq(_T_2311, UInt<1>(0h0)) node _T_2313 = asUInt(reset) node _T_2314 = eq(_T_2313, UInt<1>(0h0)) when _T_2314 : node _T_2315 = eq(_T_2312, UInt<1>(0h0)) when _T_2315 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_2312, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<10>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<10>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<513> connect d_clr_1, UInt<513>(0h0) wire d_clr_wo_ready_1 : UInt<513> connect d_clr_wo_ready_1, UInt<513>(0h0) wire d_opcodes_clr_1 : UInt<2052> connect d_opcodes_clr_1, UInt<2052>(0h0) wire d_sizes_clr_1 : UInt<4104> connect d_sizes_clr_1, UInt<4104>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2316 = and(io.in.d.valid, d_first_2) node _T_2317 = and(_T_2316, UInt<1>(0h1)) node _T_2318 = and(_T_2317, d_release_ack_1) when _T_2318 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2319 = and(io.in.d.ready, io.in.d.valid) node _T_2320 = and(_T_2319, d_first_2) node _T_2321 = and(_T_2320, UInt<1>(0h1)) node _T_2322 = and(_T_2321, d_release_ack_1) when _T_2322 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2323 = and(io.in.d.valid, d_first_2) node _T_2324 = and(_T_2323, UInt<1>(0h1)) node _T_2325 = and(_T_2324, d_release_ack_1) when _T_2325 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<10>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<10>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.secure, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<10>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2326 = dshr(inflight_1, io.in.d.bits.source) node _T_2327 = bits(_T_2326, 0, 0) node _T_2328 = or(_T_2327, same_cycle_resp_1) node _T_2329 = asUInt(reset) node _T_2330 = eq(_T_2329, UInt<1>(0h0)) when _T_2330 : node _T_2331 = eq(_T_2328, UInt<1>(0h0)) when _T_2331 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_2328, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<10>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_2332 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_2333 = asUInt(reset) node _T_2334 = eq(_T_2333, UInt<1>(0h0)) when _T_2334 : node _T_2335 = eq(_T_2332, UInt<1>(0h0)) when _T_2335 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_2332, UInt<1>(0h1), "") : assert_108 else : node _T_2336 = eq(io.in.d.bits.size, c_size_lookup) node _T_2337 = asUInt(reset) node _T_2338 = eq(_T_2337, UInt<1>(0h0)) when _T_2338 : node _T_2339 = eq(_T_2336, UInt<1>(0h0)) when _T_2339 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_2336, UInt<1>(0h1), "") : assert_109 node _T_2340 = and(io.in.d.valid, d_first_2) node _T_2341 = and(_T_2340, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<10>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_2342 = and(_T_2341, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<10>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_2343 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_2344 = and(_T_2342, _T_2343) node _T_2345 = and(_T_2344, d_release_ack_1) node _T_2346 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2347 = and(_T_2345, _T_2346) when _T_2347 : node _T_2348 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_26.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_26.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_26.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_26.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_26.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_26.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_26.bits.address, UInt<29>(0h0) connect _WIRE_26.bits.source, UInt<10>(0h0) connect _WIRE_26.bits.size, UInt<4>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_2349 = or(_T_2348, _WIRE_27.ready) node _T_2350 = asUInt(reset) node _T_2351 = eq(_T_2350, UInt<1>(0h0)) when _T_2351 : node _T_2352 = eq(_T_2349, UInt<1>(0h0)) when _T_2352 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_2349, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_49 node _T_2353 = orr(inflight_1) node _T_2354 = eq(_T_2353, UInt<1>(0h0)) node _T_2355 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2356 = or(_T_2354, _T_2355) node _T_2357 = lt(watchdog_1, plusarg_reader_1.out) node _T_2358 = or(_T_2356, _T_2357) node _T_2359 = asUInt(reset) node _T_2360 = eq(_T_2359, UInt<1>(0h0)) when _T_2360 : node _T_2361 = eq(_T_2358, UInt<1>(0h0)) when _T_2361 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_2358, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_28.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_28.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_28.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_28.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_28.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_28.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_28.bits.address, UInt<29>(0h0) connect _WIRE_28.bits.source, UInt<10>(0h0) connect _WIRE_28.bits.size, UInt<4>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_2362 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_2363 = and(io.in.d.ready, io.in.d.valid) node _T_2364 = or(_T_2362, _T_2363) when _T_2364 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_24( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [9:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [9:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [9:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [9:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [512:0] inflight; // @[Monitor.scala:614:27] reg [2051:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4103:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Monitor.scala:36:7] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Monitor.scala:36:7] wire _GEN_0 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [512:0] inflight_1; // @[Monitor.scala:726:35] reg [4103:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Monitor.scala:36:7] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module Tile_124 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_380 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a
module Tile_124( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_380 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_106 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<7>, poisoned : UInt<1>}}[7], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<7>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}} wire next_state : UInt wire next_uopc : UInt wire next_lrs1_rtype : UInt wire next_lrs2_rtype : UInt regreset state : UInt<2>, clock, reset, UInt<2>(0h0) regreset p1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p3 : UInt<1>, clock, reset, UInt<1>(0h0) regreset ppred : UInt<1>, clock, reset, UInt<1>(0h0) regreset p1_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) connect p1_poisoned, UInt<1>(0h0) connect p2_poisoned, UInt<1>(0h0) node next_p1_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) node next_p2_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) wire slot_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} invalidate slot_uop_uop.debug_tsrc invalidate slot_uop_uop.debug_fsrc invalidate slot_uop_uop.bp_xcpt_if invalidate slot_uop_uop.bp_debug_if invalidate slot_uop_uop.xcpt_ma_if invalidate slot_uop_uop.xcpt_ae_if invalidate slot_uop_uop.xcpt_pf_if invalidate slot_uop_uop.fp_single invalidate slot_uop_uop.fp_val invalidate slot_uop_uop.frs3_en invalidate slot_uop_uop.lrs2_rtype invalidate slot_uop_uop.lrs1_rtype invalidate slot_uop_uop.dst_rtype invalidate slot_uop_uop.ldst_val invalidate slot_uop_uop.lrs3 invalidate slot_uop_uop.lrs2 invalidate slot_uop_uop.lrs1 invalidate slot_uop_uop.ldst invalidate slot_uop_uop.ldst_is_rs1 invalidate slot_uop_uop.flush_on_commit invalidate slot_uop_uop.is_unique invalidate slot_uop_uop.is_sys_pc2epc invalidate slot_uop_uop.uses_stq invalidate slot_uop_uop.uses_ldq invalidate slot_uop_uop.is_amo invalidate slot_uop_uop.is_fencei invalidate slot_uop_uop.is_fence invalidate slot_uop_uop.mem_signed invalidate slot_uop_uop.mem_size invalidate slot_uop_uop.mem_cmd invalidate slot_uop_uop.bypassable invalidate slot_uop_uop.exc_cause invalidate slot_uop_uop.exception invalidate slot_uop_uop.stale_pdst invalidate slot_uop_uop.ppred_busy invalidate slot_uop_uop.prs3_busy invalidate slot_uop_uop.prs2_busy invalidate slot_uop_uop.prs1_busy invalidate slot_uop_uop.ppred invalidate slot_uop_uop.prs3 invalidate slot_uop_uop.prs2 invalidate slot_uop_uop.prs1 invalidate slot_uop_uop.pdst invalidate slot_uop_uop.rxq_idx invalidate slot_uop_uop.stq_idx invalidate slot_uop_uop.ldq_idx invalidate slot_uop_uop.rob_idx invalidate slot_uop_uop.csr_addr invalidate slot_uop_uop.imm_packed invalidate slot_uop_uop.taken invalidate slot_uop_uop.pc_lob invalidate slot_uop_uop.edge_inst invalidate slot_uop_uop.ftq_idx invalidate slot_uop_uop.br_tag invalidate slot_uop_uop.br_mask invalidate slot_uop_uop.is_sfb invalidate slot_uop_uop.is_jal invalidate slot_uop_uop.is_jalr invalidate slot_uop_uop.is_br invalidate slot_uop_uop.iw_p2_poisoned invalidate slot_uop_uop.iw_p1_poisoned invalidate slot_uop_uop.iw_state invalidate slot_uop_uop.ctrl.is_std invalidate slot_uop_uop.ctrl.is_sta invalidate slot_uop_uop.ctrl.is_load invalidate slot_uop_uop.ctrl.csr_cmd invalidate slot_uop_uop.ctrl.fcn_dw invalidate slot_uop_uop.ctrl.op_fcn invalidate slot_uop_uop.ctrl.imm_sel invalidate slot_uop_uop.ctrl.op2_sel invalidate slot_uop_uop.ctrl.op1_sel invalidate slot_uop_uop.ctrl.br_type invalidate slot_uop_uop.fu_code invalidate slot_uop_uop.iq_type invalidate slot_uop_uop.debug_pc invalidate slot_uop_uop.is_rvc invalidate slot_uop_uop.debug_inst invalidate slot_uop_uop.inst invalidate slot_uop_uop.uopc connect slot_uop_uop.uopc, UInt<7>(0h0) connect slot_uop_uop.bypassable, UInt<1>(0h0) connect slot_uop_uop.fp_val, UInt<1>(0h0) connect slot_uop_uop.uses_stq, UInt<1>(0h0) connect slot_uop_uop.uses_ldq, UInt<1>(0h0) connect slot_uop_uop.pdst, UInt<1>(0h0) connect slot_uop_uop.dst_rtype, UInt<2>(0h2) wire slot_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>} invalidate slot_uop_cs.is_std invalidate slot_uop_cs.is_sta invalidate slot_uop_cs.is_load invalidate slot_uop_cs.csr_cmd invalidate slot_uop_cs.fcn_dw invalidate slot_uop_cs.op_fcn invalidate slot_uop_cs.imm_sel invalidate slot_uop_cs.op2_sel invalidate slot_uop_cs.op1_sel invalidate slot_uop_cs.br_type connect slot_uop_cs.br_type, UInt<4>(0h0) connect slot_uop_cs.csr_cmd, UInt<3>(0h0) connect slot_uop_cs.is_load, UInt<1>(0h0) connect slot_uop_cs.is_sta, UInt<1>(0h0) connect slot_uop_cs.is_std, UInt<1>(0h0) connect slot_uop_uop.ctrl, slot_uop_cs regreset slot_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock, reset, slot_uop_uop node next_uop = mux(io.in_uop.valid, io.in_uop.bits, slot_uop) when io.kill : connect state, UInt<2>(0h0) else : when io.in_uop.valid : connect state, io.in_uop.bits.iw_state else : when io.clear : connect state, UInt<2>(0h0) else : connect state, next_state connect next_state, state connect next_uopc, slot_uop.uopc connect next_lrs1_rtype, slot_uop.lrs1_rtype connect next_lrs2_rtype, slot_uop.lrs2_rtype when io.kill : connect next_state, UInt<2>(0h0) else : node _T = eq(state, UInt<2>(0h1)) node _T_1 = and(io.grant, _T) node _T_2 = eq(state, UInt<2>(0h2)) node _T_3 = and(io.grant, _T_2) node _T_4 = and(_T_3, p1) node _T_5 = and(_T_4, p2) node _T_6 = and(_T_5, ppred) node _T_7 = or(_T_1, _T_6) when _T_7 : node _T_8 = or(p1_poisoned, p2_poisoned) node _T_9 = and(io.ldspec_miss, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : connect next_state, UInt<2>(0h0) else : node _T_11 = eq(state, UInt<2>(0h2)) node _T_12 = and(io.grant, _T_11) when _T_12 : node _T_13 = or(p1_poisoned, p2_poisoned) node _T_14 = and(io.ldspec_miss, _T_13) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : connect next_state, UInt<2>(0h1) when p1 : connect slot_uop.uopc, UInt<7>(0h3) connect next_uopc, UInt<7>(0h3) connect slot_uop.lrs1_rtype, UInt<2>(0h2) connect next_lrs1_rtype, UInt<2>(0h2) else : connect slot_uop.lrs2_rtype, UInt<2>(0h2) connect next_lrs2_rtype, UInt<2>(0h2) when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T_16 = eq(state, UInt<2>(0h0)) node _T_17 = or(_T_16, io.clear) node _T_18 = or(_T_17, io.kill) node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : node _T_21 = eq(_T_18, UInt<1>(0h0)) when _T_21 : printf(clock, UInt<1>(0h1), "Assertion failed: trying to overwrite a valid issue slot.\n at issue-slot.scala:156 assert (is_invalid || io.clear || io.kill, \"trying to overwrite a valid issue slot.\")\n") : printf assert(clock, _T_18, UInt<1>(0h1), "") : assert wire next_p1 : UInt<1> connect next_p1, p1 wire next_p2 : UInt<1> connect next_p2, p2 wire next_p3 : UInt<1> connect next_p3, p3 wire next_ppred : UInt<1> connect next_ppred, ppred when io.in_uop.valid : node _p1_T = eq(io.in_uop.bits.prs1_busy, UInt<1>(0h0)) connect p1, _p1_T node _p2_T = eq(io.in_uop.bits.prs2_busy, UInt<1>(0h0)) connect p2, _p2_T node _p3_T = eq(io.in_uop.bits.prs3_busy, UInt<1>(0h0)) connect p3, _p3_T node _ppred_T = eq(io.in_uop.bits.ppred_busy, UInt<1>(0h0)) connect ppred, _ppred_T node _T_22 = and(io.ldspec_miss, next_p1_poisoned) when _T_22 : node _T_23 = neq(next_uop.prs1, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs1=x0!\n at issue-slot.scala:176 assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n") : printf_1 assert(clock, _T_23, UInt<1>(0h1), "") : assert_1 connect p1, UInt<1>(0h0) node _T_27 = and(io.ldspec_miss, next_p2_poisoned) when _T_27 : node _T_28 = neq(next_uop.prs2, UInt<1>(0h0)) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs2=x0!\n at issue-slot.scala:180 assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n") : printf_2 assert(clock, _T_28, UInt<1>(0h1), "") : assert_2 connect p2, UInt<1>(0h0) node _T_32 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs1) node _T_33 = and(io.wakeup_ports[0].valid, _T_32) when _T_33 : connect p1, UInt<1>(0h1) node _T_34 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs2) node _T_35 = and(io.wakeup_ports[0].valid, _T_34) when _T_35 : connect p2, UInt<1>(0h1) node _T_36 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs3) node _T_37 = and(io.wakeup_ports[0].valid, _T_36) when _T_37 : connect p3, UInt<1>(0h1) node _T_38 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs1) node _T_39 = and(io.wakeup_ports[1].valid, _T_38) when _T_39 : connect p1, UInt<1>(0h1) node _T_40 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs2) node _T_41 = and(io.wakeup_ports[1].valid, _T_40) when _T_41 : connect p2, UInt<1>(0h1) node _T_42 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs3) node _T_43 = and(io.wakeup_ports[1].valid, _T_42) when _T_43 : connect p3, UInt<1>(0h1) node _T_44 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs1) node _T_45 = and(io.wakeup_ports[2].valid, _T_44) when _T_45 : connect p1, UInt<1>(0h1) node _T_46 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs2) node _T_47 = and(io.wakeup_ports[2].valid, _T_46) when _T_47 : connect p2, UInt<1>(0h1) node _T_48 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs3) node _T_49 = and(io.wakeup_ports[2].valid, _T_48) when _T_49 : connect p3, UInt<1>(0h1) node _T_50 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs1) node _T_51 = and(io.wakeup_ports[3].valid, _T_50) when _T_51 : connect p1, UInt<1>(0h1) node _T_52 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs2) node _T_53 = and(io.wakeup_ports[3].valid, _T_52) when _T_53 : connect p2, UInt<1>(0h1) node _T_54 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs3) node _T_55 = and(io.wakeup_ports[3].valid, _T_54) when _T_55 : connect p3, UInt<1>(0h1) node _T_56 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs1) node _T_57 = and(io.wakeup_ports[4].valid, _T_56) when _T_57 : connect p1, UInt<1>(0h1) node _T_58 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs2) node _T_59 = and(io.wakeup_ports[4].valid, _T_58) when _T_59 : connect p2, UInt<1>(0h1) node _T_60 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs3) node _T_61 = and(io.wakeup_ports[4].valid, _T_60) when _T_61 : connect p3, UInt<1>(0h1) node _T_62 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs1) node _T_63 = and(io.wakeup_ports[5].valid, _T_62) when _T_63 : connect p1, UInt<1>(0h1) node _T_64 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs2) node _T_65 = and(io.wakeup_ports[5].valid, _T_64) when _T_65 : connect p2, UInt<1>(0h1) node _T_66 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs3) node _T_67 = and(io.wakeup_ports[5].valid, _T_66) when _T_67 : connect p3, UInt<1>(0h1) node _T_68 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs1) node _T_69 = and(io.wakeup_ports[6].valid, _T_68) when _T_69 : connect p1, UInt<1>(0h1) node _T_70 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs2) node _T_71 = and(io.wakeup_ports[6].valid, _T_70) when _T_71 : connect p2, UInt<1>(0h1) node _T_72 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs3) node _T_73 = and(io.wakeup_ports[6].valid, _T_72) when _T_73 : connect p3, UInt<1>(0h1) node _T_74 = eq(io.pred_wakeup_port.bits, next_uop.ppred) node _T_75 = and(io.pred_wakeup_port.valid, _T_74) when _T_75 : connect ppred, UInt<1>(0h1) node _T_76 = eq(io.spec_ld_wakeup[0].bits, UInt<1>(0h0)) node _T_77 = and(io.spec_ld_wakeup[0].valid, _T_76) node _T_78 = eq(_T_77, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: Loads to x0 should never speculatively wakeup other instructions\n at issue-slot.scala:203 assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n") : printf_3 assert(clock, _T_78, UInt<1>(0h1), "") : assert_3 node _T_82 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs1) node _T_83 = and(io.spec_ld_wakeup[0].valid, _T_82) node _T_84 = eq(next_uop.lrs1_rtype, UInt<2>(0h0)) node _T_85 = and(_T_83, _T_84) when _T_85 : connect p1, UInt<1>(0h1) connect p1_poisoned, UInt<1>(0h1) node _T_86 = eq(next_p1_poisoned, UInt<1>(0h0)) node _T_87 = asUInt(reset) node _T_88 = eq(_T_87, UInt<1>(0h0)) when _T_88 : node _T_89 = eq(_T_86, UInt<1>(0h0)) when _T_89 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:214 assert (!next_p1_poisoned)\n") : printf_4 assert(clock, _T_86, UInt<1>(0h1), "") : assert_4 node _T_90 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs2) node _T_91 = and(io.spec_ld_wakeup[0].valid, _T_90) node _T_92 = eq(next_uop.lrs2_rtype, UInt<2>(0h0)) node _T_93 = and(_T_91, _T_92) when _T_93 : connect p2, UInt<1>(0h1) connect p2_poisoned, UInt<1>(0h1) node _T_94 = eq(next_p2_poisoned, UInt<1>(0h0)) node _T_95 = asUInt(reset) node _T_96 = eq(_T_95, UInt<1>(0h0)) when _T_96 : node _T_97 = eq(_T_94, UInt<1>(0h0)) when _T_97 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:221 assert (!next_p2_poisoned)\n") : printf_5 assert(clock, _T_94, UInt<1>(0h1), "") : assert_5 node _next_br_mask_T = not(io.brupdate.b1.resolve_mask) node next_br_mask = and(slot_uop.br_mask, _next_br_mask_T) node _T_98 = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _T_99 = neq(_T_98, UInt<1>(0h0)) when _T_99 : connect next_state, UInt<2>(0h0) node _T_100 = eq(io.in_uop.valid, UInt<1>(0h0)) when _T_100 : connect slot_uop.br_mask, next_br_mask node _io_request_T = neq(state, UInt<2>(0h0)) node _io_request_T_1 = and(_io_request_T, p1) node _io_request_T_2 = and(_io_request_T_1, p2) node _io_request_T_3 = and(_io_request_T_2, p3) node _io_request_T_4 = and(_io_request_T_3, ppred) node _io_request_T_5 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_6 = and(_io_request_T_4, _io_request_T_5) connect io.request, _io_request_T_6 node _high_priority_T = or(slot_uop.is_br, slot_uop.is_jal) node high_priority = or(_high_priority_T, slot_uop.is_jalr) node _io_request_hp_T = and(io.request, high_priority) connect io.request_hp, _io_request_hp_T node _T_101 = eq(state, UInt<2>(0h1)) when _T_101 : node _io_request_T_7 = and(p1, p2) node _io_request_T_8 = and(_io_request_T_7, p3) node _io_request_T_9 = and(_io_request_T_8, ppred) node _io_request_T_10 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_11 = and(_io_request_T_9, _io_request_T_10) connect io.request, _io_request_T_11 else : node _T_102 = eq(state, UInt<2>(0h2)) when _T_102 : node _io_request_T_12 = or(p1, p2) node _io_request_T_13 = and(_io_request_T_12, ppred) node _io_request_T_14 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_15 = and(_io_request_T_13, _io_request_T_14) connect io.request, _io_request_T_15 else : connect io.request, UInt<1>(0h0) node _io_valid_T = neq(state, UInt<2>(0h0)) connect io.valid, _io_valid_T connect io.uop, slot_uop connect io.uop.iw_p1_poisoned, p1_poisoned connect io.uop.iw_p2_poisoned, p2_poisoned node _may_vacate_T = eq(state, UInt<2>(0h1)) node _may_vacate_T_1 = eq(state, UInt<2>(0h2)) node _may_vacate_T_2 = and(_may_vacate_T_1, p1) node _may_vacate_T_3 = and(_may_vacate_T_2, p2) node _may_vacate_T_4 = and(_may_vacate_T_3, ppred) node _may_vacate_T_5 = or(_may_vacate_T, _may_vacate_T_4) node may_vacate = and(io.grant, _may_vacate_T_5) node _squash_grant_T = or(p1_poisoned, p2_poisoned) node squash_grant = and(io.ldspec_miss, _squash_grant_T) node _io_will_be_valid_T = neq(state, UInt<2>(0h0)) node _io_will_be_valid_T_1 = eq(squash_grant, UInt<1>(0h0)) node _io_will_be_valid_T_2 = and(may_vacate, _io_will_be_valid_T_1) node _io_will_be_valid_T_3 = eq(_io_will_be_valid_T_2, UInt<1>(0h0)) node _io_will_be_valid_T_4 = and(_io_will_be_valid_T, _io_will_be_valid_T_3) connect io.will_be_valid, _io_will_be_valid_T_4 connect io.out_uop, slot_uop connect io.out_uop.iw_state, next_state connect io.out_uop.uopc, next_uopc connect io.out_uop.lrs1_rtype, next_lrs1_rtype connect io.out_uop.lrs2_rtype, next_lrs2_rtype connect io.out_uop.br_mask, next_br_mask node _io_out_uop_prs1_busy_T = eq(p1, UInt<1>(0h0)) connect io.out_uop.prs1_busy, _io_out_uop_prs1_busy_T node _io_out_uop_prs2_busy_T = eq(p2, UInt<1>(0h0)) connect io.out_uop.prs2_busy, _io_out_uop_prs2_busy_T node _io_out_uop_prs3_busy_T = eq(p3, UInt<1>(0h0)) connect io.out_uop.prs3_busy, _io_out_uop_prs3_busy_T node _io_out_uop_ppred_busy_T = eq(ppred, UInt<1>(0h0)) connect io.out_uop.ppred_busy, _io_out_uop_ppred_busy_T connect io.out_uop.iw_p1_poisoned, p1_poisoned connect io.out_uop.iw_p2_poisoned, p2_poisoned node _T_103 = eq(state, UInt<2>(0h2)) when _T_103 : node _T_104 = and(p1, p2) node _T_105 = and(_T_104, ppred) when _T_105 : skip else : node _T_106 = and(p1, ppred) when _T_106 : connect io.uop.uopc, slot_uop.uopc connect io.uop.lrs2_rtype, UInt<2>(0h2) else : node _T_107 = and(p2, ppred) when _T_107 : connect io.uop.uopc, UInt<7>(0h3) connect io.uop.lrs1_rtype, UInt<2>(0h2) connect io.debug.p1, p1 connect io.debug.p2, p2 connect io.debug.p3, p3 connect io.debug.ppred, ppred connect io.debug.state, state
module IssueSlot_106( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_ldspec_miss, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_3_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_4_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_5_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_6_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_bits_poisoned, // @[issue-slot.scala:73:14] input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_3_bits_pdst_0 = io_wakeup_ports_3_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_bits_poisoned_0 = io_wakeup_ports_3_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_4_bits_pdst_0 = io_wakeup_ports_4_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_bits_poisoned_0 = io_wakeup_ports_4_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_valid_0 = io_wakeup_ports_5_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_5_bits_pdst_0 = io_wakeup_ports_5_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_bits_poisoned_0 = io_wakeup_ports_5_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_valid_0 = io_wakeup_ports_6_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_6_bits_pdst_0 = io_wakeup_ports_6_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_bits_poisoned_0 = io_wakeup_ports_6_bits_poisoned; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned_0 = io_in_uop_bits_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned_0 = io_in_uop_bits_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [15:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg p1_poisoned; // @[issue-slot.scala:95:28] assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] reg p2_poisoned; // @[issue-slot.scala:96:28] assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] wire next_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29] wire next_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :100:29] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _T_14 = io_ldspec_miss_0 & (p1_poisoned | p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}] wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18] wire _GEN_0 = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_1 = _GEN_0 | ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23] assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_2 = _GEN_0 | ~_GEN | p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17] assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17] wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11] wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11] wire _p3_T = ~io_in_uop_bits_prs3_busy_0; // @[issue-slot.scala:69:7, :171:11] wire _ppred_T = ~io_in_uop_bits_ppred_busy_0; // @[issue-slot.scala:69:7, :172:14] wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24] wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24] wire _T_85 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27] wire _T_93 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27]
Generate the Verilog code corresponding to this FIRRTL code module AXI4Fragmenter : input clock : Clock input reset : Reset output auto : { flip in : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { extra_id : UInt<7>}}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, resp : UInt<2>, user : { }, echo : { extra_id : UInt<7>}}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { extra_id : UInt<7>}}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { extra_id : UInt<7>}, last : UInt<1>}}}, out : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { extra_id : UInt<7>, real_last : UInt<1>}}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, resp : UInt<2>, user : { }, echo : { extra_id : UInt<7>, real_last : UInt<1>}}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { extra_id : UInt<7>, real_last : UInt<1>}}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { extra_id : UInt<7>, real_last : UInt<1>}, last : UInt<1>}}}} wire nodeIn : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { extra_id : UInt<7>}}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, resp : UInt<2>, user : { }, echo : { extra_id : UInt<7>}}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { extra_id : UInt<7>}}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { extra_id : UInt<7>}, last : UInt<1>}}} invalidate nodeIn.r.bits.last invalidate nodeIn.r.bits.echo.extra_id invalidate nodeIn.r.bits.resp invalidate nodeIn.r.bits.data invalidate nodeIn.r.bits.id invalidate nodeIn.r.valid invalidate nodeIn.r.ready invalidate nodeIn.ar.bits.echo.extra_id invalidate nodeIn.ar.bits.qos invalidate nodeIn.ar.bits.prot invalidate nodeIn.ar.bits.cache invalidate nodeIn.ar.bits.lock invalidate nodeIn.ar.bits.burst invalidate nodeIn.ar.bits.size invalidate nodeIn.ar.bits.len invalidate nodeIn.ar.bits.addr invalidate nodeIn.ar.bits.id invalidate nodeIn.ar.valid invalidate nodeIn.ar.ready invalidate nodeIn.b.bits.echo.extra_id invalidate nodeIn.b.bits.resp invalidate nodeIn.b.bits.id invalidate nodeIn.b.valid invalidate nodeIn.b.ready invalidate nodeIn.w.bits.last invalidate nodeIn.w.bits.strb invalidate nodeIn.w.bits.data invalidate nodeIn.w.valid invalidate nodeIn.w.ready invalidate nodeIn.aw.bits.echo.extra_id invalidate nodeIn.aw.bits.qos invalidate nodeIn.aw.bits.prot invalidate nodeIn.aw.bits.cache invalidate nodeIn.aw.bits.lock invalidate nodeIn.aw.bits.burst invalidate nodeIn.aw.bits.size invalidate nodeIn.aw.bits.len invalidate nodeIn.aw.bits.addr invalidate nodeIn.aw.bits.id invalidate nodeIn.aw.valid invalidate nodeIn.aw.ready wire nodeOut : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { extra_id : UInt<7>, real_last : UInt<1>}}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, resp : UInt<2>, user : { }, echo : { extra_id : UInt<7>, real_last : UInt<1>}}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { extra_id : UInt<7>, real_last : UInt<1>}}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { extra_id : UInt<7>, real_last : UInt<1>}, last : UInt<1>}}} invalidate nodeOut.r.bits.last invalidate nodeOut.r.bits.echo.real_last invalidate nodeOut.r.bits.echo.extra_id invalidate nodeOut.r.bits.resp invalidate nodeOut.r.bits.data invalidate nodeOut.r.bits.id invalidate nodeOut.r.valid invalidate nodeOut.r.ready invalidate nodeOut.ar.bits.echo.real_last invalidate nodeOut.ar.bits.echo.extra_id invalidate nodeOut.ar.bits.qos invalidate nodeOut.ar.bits.prot invalidate nodeOut.ar.bits.cache invalidate nodeOut.ar.bits.lock invalidate nodeOut.ar.bits.burst invalidate nodeOut.ar.bits.size invalidate nodeOut.ar.bits.len invalidate nodeOut.ar.bits.addr invalidate nodeOut.ar.bits.id invalidate nodeOut.ar.valid invalidate nodeOut.ar.ready invalidate nodeOut.b.bits.echo.real_last invalidate nodeOut.b.bits.echo.extra_id invalidate nodeOut.b.bits.resp invalidate nodeOut.b.bits.id invalidate nodeOut.b.valid invalidate nodeOut.b.ready invalidate nodeOut.w.bits.last invalidate nodeOut.w.bits.strb invalidate nodeOut.w.bits.data invalidate nodeOut.w.valid invalidate nodeOut.w.ready invalidate nodeOut.aw.bits.echo.real_last invalidate nodeOut.aw.bits.echo.extra_id invalidate nodeOut.aw.bits.qos invalidate nodeOut.aw.bits.prot invalidate nodeOut.aw.bits.cache invalidate nodeOut.aw.bits.lock invalidate nodeOut.aw.bits.burst invalidate nodeOut.aw.bits.size invalidate nodeOut.aw.bits.len invalidate nodeOut.aw.bits.addr invalidate nodeOut.aw.bits.id invalidate nodeOut.aw.valid invalidate nodeOut.aw.ready connect auto.out, nodeOut connect nodeIn, auto.in inst deq_q of Queue1_AXI4BundleAR connect deq_q.clock, clock connect deq_q.reset, reset connect deq_q.io.enq.valid, nodeIn.ar.valid connect deq_q.io.enq.bits.echo.extra_id, nodeIn.ar.bits.echo.extra_id connect deq_q.io.enq.bits.qos, nodeIn.ar.bits.qos connect deq_q.io.enq.bits.prot, nodeIn.ar.bits.prot connect deq_q.io.enq.bits.cache, nodeIn.ar.bits.cache connect deq_q.io.enq.bits.lock, nodeIn.ar.bits.lock connect deq_q.io.enq.bits.burst, nodeIn.ar.bits.burst connect deq_q.io.enq.bits.size, nodeIn.ar.bits.size connect deq_q.io.enq.bits.len, nodeIn.ar.bits.len connect deq_q.io.enq.bits.addr, nodeIn.ar.bits.addr connect deq_q.io.enq.bits.id, nodeIn.ar.bits.id connect nodeIn.ar.ready, deq_q.io.enq.ready wire irr : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { extra_id : UInt<7>}}} connect irr.bits, deq_q.io.deq.bits connect irr.valid, deq_q.io.deq.valid connect deq_q.io.deq.ready, irr.ready wire in_ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { extra_id : UInt<7>}}} regreset busy : UInt<1>, clock, reset, UInt<1>(0h0) reg r_addr : UInt<32>, clock reg r_len : UInt<8>, clock node len = mux(busy, r_len, irr.bits.len) node addr = mux(busy, r_addr, irr.bits.addr) node lo = bits(addr, 2, 0) node alignment = bits(addr, 10, 3) node _support1_T = xor(addr, UInt<1>(0h0)) node _support1_T_1 = cvt(_support1_T) node _support1_T_2 = and(_support1_T_1, asSInt(UInt<33>(0hca112000))) node _support1_T_3 = asSInt(_support1_T_2) node _support1_T_4 = eq(_support1_T_3, asSInt(UInt<1>(0h0))) node _support1_T_5 = xor(addr, UInt<17>(0h10000)) node _support1_T_6 = cvt(_support1_T_5) node _support1_T_7 = and(_support1_T_6, asSInt(UInt<33>(0hca110000))) node _support1_T_8 = asSInt(_support1_T_7) node _support1_T_9 = eq(_support1_T_8, asSInt(UInt<1>(0h0))) node _support1_T_10 = xor(addr, UInt<21>(0h100000)) node _support1_T_11 = cvt(_support1_T_10) node _support1_T_12 = and(_support1_T_11, asSInt(UInt<33>(0hca103000))) node _support1_T_13 = asSInt(_support1_T_12) node _support1_T_14 = eq(_support1_T_13, asSInt(UInt<1>(0h0))) node _support1_T_15 = xor(addr, UInt<26>(0h2000000)) node _support1_T_16 = cvt(_support1_T_15) node _support1_T_17 = and(_support1_T_16, asSInt(UInt<33>(0hca110000))) node _support1_T_18 = asSInt(_support1_T_17) node _support1_T_19 = eq(_support1_T_18, asSInt(UInt<1>(0h0))) node _support1_T_20 = xor(addr, UInt<28>(0h8000000)) node _support1_T_21 = cvt(_support1_T_20) node _support1_T_22 = and(_support1_T_21, asSInt(UInt<33>(0hc8000000))) node _support1_T_23 = asSInt(_support1_T_22) node _support1_T_24 = eq(_support1_T_23, asSInt(UInt<1>(0h0))) node _support1_T_25 = xor(addr, UInt<31>(0h40000000)) node _support1_T_26 = cvt(_support1_T_25) node _support1_T_27 = and(_support1_T_26, asSInt(UInt<33>(0hc0000000))) node _support1_T_28 = asSInt(_support1_T_27) node _support1_T_29 = eq(_support1_T_28, asSInt(UInt<1>(0h0))) node _support1_T_30 = xor(addr, UInt<32>(0h80000000)) node _support1_T_31 = cvt(_support1_T_30) node _support1_T_32 = and(_support1_T_31, asSInt(UInt<33>(0hca110000))) node _support1_T_33 = asSInt(_support1_T_32) node _support1_T_34 = eq(_support1_T_33, asSInt(UInt<1>(0h0))) node _support1_T_35 = or(_support1_T_4, _support1_T_9) node _support1_T_36 = or(_support1_T_35, _support1_T_14) node _support1_T_37 = or(_support1_T_36, _support1_T_19) node _support1_T_38 = or(_support1_T_37, _support1_T_24) node _support1_T_39 = or(_support1_T_38, _support1_T_29) node _support1_T_40 = or(_support1_T_39, _support1_T_34) node _support1_T_41 = xor(addr, UInt<14>(0h3000)) node _support1_T_42 = cvt(_support1_T_41) node _support1_T_43 = and(_support1_T_42, asSInt(UInt<33>(0hca113000))) node _support1_T_44 = asSInt(_support1_T_43) node _support1_T_45 = eq(_support1_T_44, asSInt(UInt<1>(0h0))) node _support1_T_46 = mux(_support1_T_40, UInt<3>(0h7), UInt<1>(0h0)) node _support1_T_47 = mux(_support1_T_45, UInt<8>(0hff), UInt<1>(0h0)) node _support1_T_48 = or(_support1_T_46, _support1_T_47) wire support1 : UInt<8> connect support1, _support1_T_48 node _fillLow_T = shr(len, 1) node _fillLow_T_1 = or(len, _fillLow_T) node _fillLow_T_2 = shr(_fillLow_T_1, 2) node _fillLow_T_3 = or(_fillLow_T_1, _fillLow_T_2) node _fillLow_T_4 = shr(_fillLow_T_3, 4) node _fillLow_T_5 = or(_fillLow_T_3, _fillLow_T_4) node _fillLow_T_6 = bits(_fillLow_T_5, 7, 0) node fillLow = shr(_fillLow_T_6, 1) node _wipeHigh_T = not(len) node _wipeHigh_T_1 = shl(_wipeHigh_T, 1) node _wipeHigh_T_2 = bits(_wipeHigh_T_1, 7, 0) node _wipeHigh_T_3 = or(_wipeHigh_T, _wipeHigh_T_2) node _wipeHigh_T_4 = shl(_wipeHigh_T_3, 2) node _wipeHigh_T_5 = bits(_wipeHigh_T_4, 7, 0) node _wipeHigh_T_6 = or(_wipeHigh_T_3, _wipeHigh_T_5) node _wipeHigh_T_7 = shl(_wipeHigh_T_6, 4) node _wipeHigh_T_8 = bits(_wipeHigh_T_7, 7, 0) node _wipeHigh_T_9 = or(_wipeHigh_T_6, _wipeHigh_T_8) node _wipeHigh_T_10 = bits(_wipeHigh_T_9, 7, 0) node wipeHigh = not(_wipeHigh_T_10) node remain1 = or(fillLow, wipeHigh) node _align1_T = shl(alignment, 1) node _align1_T_1 = bits(_align1_T, 7, 0) node _align1_T_2 = or(alignment, _align1_T_1) node _align1_T_3 = shl(_align1_T_2, 2) node _align1_T_4 = bits(_align1_T_3, 7, 0) node _align1_T_5 = or(_align1_T_2, _align1_T_4) node _align1_T_6 = shl(_align1_T_5, 4) node _align1_T_7 = bits(_align1_T_6, 7, 0) node _align1_T_8 = or(_align1_T_5, _align1_T_7) node _align1_T_9 = bits(_align1_T_8, 7, 0) node align1 = not(_align1_T_9) node _maxSupported1_T = and(remain1, align1) node maxSupported1 = and(_maxSupported1_T, support1) node fixed = eq(irr.bits.burst, UInt<2>(0h0)) node narrow = neq(irr.bits.size, UInt<2>(0h3)) node bad = or(fixed, narrow) node beats1 = mux(bad, UInt<1>(0h0), maxSupported1) node _beats_T = shl(beats1, 1) node _beats_T_1 = or(_beats_T, UInt<1>(0h1)) node _beats_T_2 = cat(UInt<1>(0h0), beats1) node _beats_T_3 = not(_beats_T_2) node beats = and(_beats_T_1, _beats_T_3) node _inc_addr_T = dshl(beats, irr.bits.size) node _inc_addr_T_1 = add(addr, _inc_addr_T) node inc_addr = tail(_inc_addr_T_1, 1) node _wrapMask_T = cat(irr.bits.len, UInt<8>(0hff)) node _wrapMask_T_1 = dshl(_wrapMask_T, irr.bits.size) node wrapMask = shr(_wrapMask_T_1, 8) wire mux_addr : UInt connect mux_addr, inc_addr node _T = eq(irr.bits.burst, UInt<2>(0h2)) when _T : node _mux_addr_T = and(inc_addr, wrapMask) node _mux_addr_T_1 = not(irr.bits.addr) node _mux_addr_T_2 = or(_mux_addr_T_1, wrapMask) node _mux_addr_T_3 = not(_mux_addr_T_2) node _mux_addr_T_4 = or(_mux_addr_T, _mux_addr_T_3) connect mux_addr, _mux_addr_T_4 node _T_1 = eq(irr.bits.burst, UInt<2>(0h0)) when _T_1 : connect mux_addr, irr.bits.addr node ar_last = eq(beats1, len) node _irr_ready_T = and(in_ar.ready, ar_last) connect irr.ready, _irr_ready_T connect in_ar.valid, irr.valid connect in_ar.bits.echo.extra_id, irr.bits.echo.extra_id connect in_ar.bits.qos, irr.bits.qos connect in_ar.bits.prot, irr.bits.prot connect in_ar.bits.cache, irr.bits.cache connect in_ar.bits.lock, irr.bits.lock connect in_ar.bits.burst, irr.bits.burst connect in_ar.bits.size, irr.bits.size connect in_ar.bits.len, irr.bits.len connect in_ar.bits.addr, irr.bits.addr connect in_ar.bits.id, irr.bits.id connect in_ar.bits.len, beats1 node _out_bits_addr_T = not(addr) node _out_bits_addr_T_1 = dshl(UInt<3>(0h7), irr.bits.size) node _out_bits_addr_T_2 = bits(_out_bits_addr_T_1, 2, 0) node _out_bits_addr_T_3 = not(_out_bits_addr_T_2) node _out_bits_addr_T_4 = or(_out_bits_addr_T, _out_bits_addr_T_3) node _out_bits_addr_T_5 = not(_out_bits_addr_T_4) connect in_ar.bits.addr, _out_bits_addr_T_5 node _T_2 = and(in_ar.ready, in_ar.valid) when _T_2 : node _busy_T = eq(ar_last, UInt<1>(0h0)) connect busy, _busy_T connect r_addr, mux_addr node _r_len_T = sub(len, beats) node _r_len_T_1 = tail(_r_len_T, 1) connect r_len, _r_len_T_1 inst deq_q_1 of Queue1_AXI4BundleAW connect deq_q_1.clock, clock connect deq_q_1.reset, reset connect deq_q_1.io.enq.valid, nodeIn.aw.valid connect deq_q_1.io.enq.bits.echo.extra_id, nodeIn.aw.bits.echo.extra_id connect deq_q_1.io.enq.bits.qos, nodeIn.aw.bits.qos connect deq_q_1.io.enq.bits.prot, nodeIn.aw.bits.prot connect deq_q_1.io.enq.bits.cache, nodeIn.aw.bits.cache connect deq_q_1.io.enq.bits.lock, nodeIn.aw.bits.lock connect deq_q_1.io.enq.bits.burst, nodeIn.aw.bits.burst connect deq_q_1.io.enq.bits.size, nodeIn.aw.bits.size connect deq_q_1.io.enq.bits.len, nodeIn.aw.bits.len connect deq_q_1.io.enq.bits.addr, nodeIn.aw.bits.addr connect deq_q_1.io.enq.bits.id, nodeIn.aw.bits.id connect nodeIn.aw.ready, deq_q_1.io.enq.ready wire irr_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { extra_id : UInt<7>}}} connect irr_1.bits, deq_q_1.io.deq.bits connect irr_1.valid, deq_q_1.io.deq.valid connect deq_q_1.io.deq.ready, irr_1.ready wire in_aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<1>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { extra_id : UInt<7>}}} regreset busy_1 : UInt<1>, clock, reset, UInt<1>(0h0) reg r_addr_1 : UInt<32>, clock reg r_len_1 : UInt<8>, clock node len_1 = mux(busy_1, r_len_1, irr_1.bits.len) node addr_1 = mux(busy_1, r_addr_1, irr_1.bits.addr) node lo_1 = bits(addr_1, 2, 0) node alignment_1 = bits(addr_1, 10, 3) node _support1_T_49 = xor(addr_1, UInt<1>(0h0)) node _support1_T_50 = cvt(_support1_T_49) node _support1_T_51 = and(_support1_T_50, asSInt(UInt<33>(0hca102000))) node _support1_T_52 = asSInt(_support1_T_51) node _support1_T_53 = eq(_support1_T_52, asSInt(UInt<1>(0h0))) node _support1_T_54 = xor(addr_1, UInt<21>(0h100000)) node _support1_T_55 = cvt(_support1_T_54) node _support1_T_56 = and(_support1_T_55, asSInt(UInt<33>(0hca103000))) node _support1_T_57 = asSInt(_support1_T_56) node _support1_T_58 = eq(_support1_T_57, asSInt(UInt<1>(0h0))) node _support1_T_59 = xor(addr_1, UInt<26>(0h2000000)) node _support1_T_60 = cvt(_support1_T_59) node _support1_T_61 = and(_support1_T_60, asSInt(UInt<33>(0hca100000))) node _support1_T_62 = asSInt(_support1_T_61) node _support1_T_63 = eq(_support1_T_62, asSInt(UInt<1>(0h0))) node _support1_T_64 = xor(addr_1, UInt<28>(0h8000000)) node _support1_T_65 = cvt(_support1_T_64) node _support1_T_66 = and(_support1_T_65, asSInt(UInt<33>(0hc8000000))) node _support1_T_67 = asSInt(_support1_T_66) node _support1_T_68 = eq(_support1_T_67, asSInt(UInt<1>(0h0))) node _support1_T_69 = xor(addr_1, UInt<32>(0h80000000)) node _support1_T_70 = cvt(_support1_T_69) node _support1_T_71 = and(_support1_T_70, asSInt(UInt<33>(0hca100000))) node _support1_T_72 = asSInt(_support1_T_71) node _support1_T_73 = eq(_support1_T_72, asSInt(UInt<1>(0h0))) node _support1_T_74 = or(_support1_T_53, _support1_T_58) node _support1_T_75 = or(_support1_T_74, _support1_T_63) node _support1_T_76 = or(_support1_T_75, _support1_T_68) node _support1_T_77 = or(_support1_T_76, _support1_T_73) node _support1_T_78 = xor(addr_1, UInt<14>(0h3000)) node _support1_T_79 = cvt(_support1_T_78) node _support1_T_80 = and(_support1_T_79, asSInt(UInt<33>(0hca103000))) node _support1_T_81 = asSInt(_support1_T_80) node _support1_T_82 = eq(_support1_T_81, asSInt(UInt<1>(0h0))) node _support1_T_83 = xor(addr_1, UInt<31>(0h40000000)) node _support1_T_84 = cvt(_support1_T_83) node _support1_T_85 = and(_support1_T_84, asSInt(UInt<33>(0hc0000000))) node _support1_T_86 = asSInt(_support1_T_85) node _support1_T_87 = eq(_support1_T_86, asSInt(UInt<1>(0h0))) node _support1_T_88 = mux(_support1_T_77, UInt<3>(0h7), UInt<1>(0h0)) node _support1_T_89 = mux(_support1_T_82, UInt<8>(0hff), UInt<1>(0h0)) node _support1_T_90 = mux(_support1_T_87, UInt<5>(0h1f), UInt<1>(0h0)) node _support1_T_91 = or(_support1_T_88, _support1_T_89) node _support1_T_92 = or(_support1_T_91, _support1_T_90) wire support1_1 : UInt<8> connect support1_1, _support1_T_92 node _fillLow_T_7 = shr(len_1, 1) node _fillLow_T_8 = or(len_1, _fillLow_T_7) node _fillLow_T_9 = shr(_fillLow_T_8, 2) node _fillLow_T_10 = or(_fillLow_T_8, _fillLow_T_9) node _fillLow_T_11 = shr(_fillLow_T_10, 4) node _fillLow_T_12 = or(_fillLow_T_10, _fillLow_T_11) node _fillLow_T_13 = bits(_fillLow_T_12, 7, 0) node fillLow_1 = shr(_fillLow_T_13, 1) node _wipeHigh_T_11 = not(len_1) node _wipeHigh_T_12 = shl(_wipeHigh_T_11, 1) node _wipeHigh_T_13 = bits(_wipeHigh_T_12, 7, 0) node _wipeHigh_T_14 = or(_wipeHigh_T_11, _wipeHigh_T_13) node _wipeHigh_T_15 = shl(_wipeHigh_T_14, 2) node _wipeHigh_T_16 = bits(_wipeHigh_T_15, 7, 0) node _wipeHigh_T_17 = or(_wipeHigh_T_14, _wipeHigh_T_16) node _wipeHigh_T_18 = shl(_wipeHigh_T_17, 4) node _wipeHigh_T_19 = bits(_wipeHigh_T_18, 7, 0) node _wipeHigh_T_20 = or(_wipeHigh_T_17, _wipeHigh_T_19) node _wipeHigh_T_21 = bits(_wipeHigh_T_20, 7, 0) node wipeHigh_1 = not(_wipeHigh_T_21) node remain1_1 = or(fillLow_1, wipeHigh_1) node _align1_T_10 = shl(alignment_1, 1) node _align1_T_11 = bits(_align1_T_10, 7, 0) node _align1_T_12 = or(alignment_1, _align1_T_11) node _align1_T_13 = shl(_align1_T_12, 2) node _align1_T_14 = bits(_align1_T_13, 7, 0) node _align1_T_15 = or(_align1_T_12, _align1_T_14) node _align1_T_16 = shl(_align1_T_15, 4) node _align1_T_17 = bits(_align1_T_16, 7, 0) node _align1_T_18 = or(_align1_T_15, _align1_T_17) node _align1_T_19 = bits(_align1_T_18, 7, 0) node align1_1 = not(_align1_T_19) node _maxSupported1_T_1 = and(remain1_1, align1_1) node maxSupported1_1 = and(_maxSupported1_T_1, support1_1) node fixed_1 = eq(irr_1.bits.burst, UInt<2>(0h0)) node narrow_1 = neq(irr_1.bits.size, UInt<2>(0h3)) node bad_1 = or(fixed_1, narrow_1) node beats1_1 = mux(bad_1, UInt<1>(0h0), maxSupported1_1) node _beats_T_4 = shl(beats1_1, 1) node _beats_T_5 = or(_beats_T_4, UInt<1>(0h1)) node _beats_T_6 = cat(UInt<1>(0h0), beats1_1) node _beats_T_7 = not(_beats_T_6) node w_beats = and(_beats_T_5, _beats_T_7) node _inc_addr_T_2 = dshl(w_beats, irr_1.bits.size) node _inc_addr_T_3 = add(addr_1, _inc_addr_T_2) node inc_addr_1 = tail(_inc_addr_T_3, 1) node _wrapMask_T_2 = cat(irr_1.bits.len, UInt<8>(0hff)) node _wrapMask_T_3 = dshl(_wrapMask_T_2, irr_1.bits.size) node wrapMask_1 = shr(_wrapMask_T_3, 8) wire mux_addr_1 : UInt connect mux_addr_1, inc_addr_1 node _T_3 = eq(irr_1.bits.burst, UInt<2>(0h2)) when _T_3 : node _mux_addr_T_5 = and(inc_addr_1, wrapMask_1) node _mux_addr_T_6 = not(irr_1.bits.addr) node _mux_addr_T_7 = or(_mux_addr_T_6, wrapMask_1) node _mux_addr_T_8 = not(_mux_addr_T_7) node _mux_addr_T_9 = or(_mux_addr_T_5, _mux_addr_T_8) connect mux_addr_1, _mux_addr_T_9 node _T_4 = eq(irr_1.bits.burst, UInt<2>(0h0)) when _T_4 : connect mux_addr_1, irr_1.bits.addr node aw_last = eq(beats1_1, len_1) node _irr_ready_T_1 = and(in_aw.ready, aw_last) connect irr_1.ready, _irr_ready_T_1 connect in_aw.valid, irr_1.valid connect in_aw.bits.echo.extra_id, irr_1.bits.echo.extra_id connect in_aw.bits.qos, irr_1.bits.qos connect in_aw.bits.prot, irr_1.bits.prot connect in_aw.bits.cache, irr_1.bits.cache connect in_aw.bits.lock, irr_1.bits.lock connect in_aw.bits.burst, irr_1.bits.burst connect in_aw.bits.size, irr_1.bits.size connect in_aw.bits.len, irr_1.bits.len connect in_aw.bits.addr, irr_1.bits.addr connect in_aw.bits.id, irr_1.bits.id connect in_aw.bits.len, beats1_1 node _out_bits_addr_T_6 = not(addr_1) node _out_bits_addr_T_7 = dshl(UInt<3>(0h7), irr_1.bits.size) node _out_bits_addr_T_8 = bits(_out_bits_addr_T_7, 2, 0) node _out_bits_addr_T_9 = not(_out_bits_addr_T_8) node _out_bits_addr_T_10 = or(_out_bits_addr_T_6, _out_bits_addr_T_9) node _out_bits_addr_T_11 = not(_out_bits_addr_T_10) connect in_aw.bits.addr, _out_bits_addr_T_11 node _T_5 = and(in_aw.ready, in_aw.valid) when _T_5 : node _busy_T_1 = eq(aw_last, UInt<1>(0h0)) connect busy_1, _busy_T_1 connect r_addr_1, mux_addr_1 node _r_len_T_2 = sub(len_1, w_beats) node _r_len_T_3 = tail(_r_len_T_2, 1) connect r_len_1, _r_len_T_3 inst in_w_deq_q of Queue1_AXI4BundleW_1 connect in_w_deq_q.clock, clock connect in_w_deq_q.reset, reset connect in_w_deq_q.io.enq.valid, nodeIn.w.valid connect in_w_deq_q.io.enq.bits.last, nodeIn.w.bits.last connect in_w_deq_q.io.enq.bits.strb, nodeIn.w.bits.strb connect in_w_deq_q.io.enq.bits.data, nodeIn.w.bits.data connect nodeIn.w.ready, in_w_deq_q.io.enq.ready wire in_w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}} connect in_w.bits, in_w_deq_q.io.deq.bits connect in_w.valid, in_w_deq_q.io.deq.valid connect in_w_deq_q.io.deq.ready, in_w.ready connect nodeOut.ar.bits.echo.extra_id, in_ar.bits.echo.extra_id connect nodeOut.ar.bits.qos, in_ar.bits.qos connect nodeOut.ar.bits.prot, in_ar.bits.prot connect nodeOut.ar.bits.cache, in_ar.bits.cache connect nodeOut.ar.bits.lock, in_ar.bits.lock connect nodeOut.ar.bits.burst, in_ar.bits.burst connect nodeOut.ar.bits.size, in_ar.bits.size connect nodeOut.ar.bits.len, in_ar.bits.len connect nodeOut.ar.bits.addr, in_ar.bits.addr connect nodeOut.ar.bits.id, in_ar.bits.id connect nodeOut.ar.valid, in_ar.valid connect in_ar.ready, nodeOut.ar.ready connect nodeOut.ar.bits.echo.real_last, ar_last regreset wbeats_latched : UInt<1>, clock, reset, UInt<1>(0h0) wire wbeats_ready : UInt<1> wire wbeats_valid : UInt<1> node _T_6 = and(wbeats_valid, wbeats_ready) when _T_6 : connect wbeats_latched, UInt<1>(0h1) node _T_7 = and(nodeOut.aw.ready, nodeOut.aw.valid) when _T_7 : connect wbeats_latched, UInt<1>(0h0) node _nodeOut_aw_valid_T = or(wbeats_ready, wbeats_latched) node _nodeOut_aw_valid_T_1 = and(in_aw.valid, _nodeOut_aw_valid_T) connect nodeOut.aw.valid, _nodeOut_aw_valid_T_1 node _in_aw_ready_T = or(wbeats_ready, wbeats_latched) node _in_aw_ready_T_1 = and(nodeOut.aw.ready, _in_aw_ready_T) connect in_aw.ready, _in_aw_ready_T_1 node _wbeats_valid_T = eq(wbeats_latched, UInt<1>(0h0)) node _wbeats_valid_T_1 = and(in_aw.valid, _wbeats_valid_T) connect wbeats_valid, _wbeats_valid_T_1 connect nodeOut.aw.bits.echo.extra_id, in_aw.bits.echo.extra_id connect nodeOut.aw.bits.qos, in_aw.bits.qos connect nodeOut.aw.bits.prot, in_aw.bits.prot connect nodeOut.aw.bits.cache, in_aw.bits.cache connect nodeOut.aw.bits.lock, in_aw.bits.lock connect nodeOut.aw.bits.burst, in_aw.bits.burst connect nodeOut.aw.bits.size, in_aw.bits.size connect nodeOut.aw.bits.len, in_aw.bits.len connect nodeOut.aw.bits.addr, in_aw.bits.addr connect nodeOut.aw.bits.id, in_aw.bits.id connect nodeOut.aw.bits.echo.real_last, aw_last regreset w_counter : UInt<9>, clock, reset, UInt<9>(0h0) node w_idle = eq(w_counter, UInt<1>(0h0)) node _w_todo_T = mux(wbeats_valid, w_beats, UInt<1>(0h0)) node w_todo = mux(w_idle, _w_todo_T, w_counter) node w_last = eq(w_todo, UInt<1>(0h1)) node _w_counter_T = and(nodeOut.w.ready, nodeOut.w.valid) node _w_counter_T_1 = sub(w_todo, _w_counter_T) node _w_counter_T_2 = tail(_w_counter_T_1, 1) connect w_counter, _w_counter_T_2 node _T_8 = and(nodeOut.w.ready, nodeOut.w.valid) node _T_9 = eq(_T_8, UInt<1>(0h0)) node _T_10 = neq(w_todo, UInt<1>(0h0)) node _T_11 = or(_T_9, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:181 assert (!out.w.fire || w_todo =/= 0.U) // underflow impossible\n") : printf assert(clock, _T_11, UInt<1>(0h1), "") : assert connect wbeats_ready, w_idle node _nodeOut_w_valid_T = eq(wbeats_ready, UInt<1>(0h0)) node _nodeOut_w_valid_T_1 = or(_nodeOut_w_valid_T, wbeats_valid) node _nodeOut_w_valid_T_2 = and(in_w.valid, _nodeOut_w_valid_T_1) connect nodeOut.w.valid, _nodeOut_w_valid_T_2 node _in_w_ready_T = eq(wbeats_ready, UInt<1>(0h0)) node _in_w_ready_T_1 = or(_in_w_ready_T, wbeats_valid) node _in_w_ready_T_2 = and(nodeOut.w.ready, _in_w_ready_T_1) connect in_w.ready, _in_w_ready_T_2 connect nodeOut.w.bits.last, in_w.bits.last connect nodeOut.w.bits.strb, in_w.bits.strb connect nodeOut.w.bits.data, in_w.bits.data connect nodeOut.w.bits.last, w_last node _T_15 = eq(nodeOut.w.valid, UInt<1>(0h0)) node _T_16 = eq(in_w.bits.last, UInt<1>(0h0)) node _T_17 = or(_T_15, _T_16) node _T_18 = or(_T_17, w_last) node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : node _T_21 = eq(_T_18, UInt<1>(0h0)) when _T_21 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:190 assert (!out.w.valid || !in_w.bits.last || w_last)\n") : printf_1 assert(clock, _T_18, UInt<1>(0h1), "") : assert_1 connect nodeIn.r.bits.last, nodeOut.r.bits.last connect nodeIn.r.bits.echo.extra_id, nodeOut.r.bits.echo.extra_id connect nodeIn.r.bits.resp, nodeOut.r.bits.resp connect nodeIn.r.bits.data, nodeOut.r.bits.data connect nodeIn.r.bits.id, nodeOut.r.bits.id connect nodeIn.r.valid, nodeOut.r.valid connect nodeOut.r.ready, nodeIn.r.ready node _nodeIn_r_bits_last_T = and(nodeOut.r.bits.last, nodeOut.r.bits.echo.real_last) connect nodeIn.r.bits.last, _nodeIn_r_bits_last_T connect nodeIn.b.bits.echo.extra_id, nodeOut.b.bits.echo.extra_id connect nodeIn.b.bits.resp, nodeOut.b.bits.resp connect nodeIn.b.bits.id, nodeOut.b.bits.id connect nodeIn.b.valid, nodeOut.b.valid connect nodeOut.b.ready, nodeIn.b.ready node _nodeIn_b_valid_T = and(nodeOut.b.valid, nodeOut.b.bits.echo.real_last) connect nodeIn.b.valid, _nodeIn_b_valid_T node _nodeOut_b_ready_T = eq(nodeOut.b.bits.echo.real_last, UInt<1>(0h0)) node _nodeOut_b_ready_T_1 = or(nodeIn.b.ready, _nodeOut_b_ready_T) connect nodeOut.b.ready, _nodeOut_b_ready_T_1 wire _error_WIRE : UInt<2>[2] connect _error_WIRE[0], UInt<2>(0h0) connect _error_WIRE[1], UInt<2>(0h0) regreset error : UInt<2>[2], clock, reset, _error_WIRE node _nodeIn_b_bits_resp_T = or(nodeOut.b.bits.resp, error[nodeOut.b.bits.id]) connect nodeIn.b.bits.resp, _nodeIn_b_bits_resp_T node shiftAmount = bits(nodeOut.b.bits.id, 0, 0) node _T_22 = dshl(UInt<1>(0h1), shiftAmount) node _T_23 = bits(_T_22, 1, 0) node _T_24 = bits(_T_23, 0, 0) node _T_25 = bits(_T_23, 1, 1) node _T_26 = and(nodeOut.b.ready, nodeOut.b.valid) node _T_27 = and(_T_24, _T_26) when _T_27 : node _error_0_T = or(error[0], nodeOut.b.bits.resp) node _error_0_T_1 = mux(nodeOut.b.bits.echo.real_last, UInt<1>(0h0), _error_0_T) connect error[0], _error_0_T_1 node _T_28 = and(nodeOut.b.ready, nodeOut.b.valid) node _T_29 = and(_T_25, _T_28) when _T_29 : node _error_1_T = or(error[1], nodeOut.b.bits.resp) node _error_1_T_1 = mux(nodeOut.b.bits.echo.real_last, UInt<1>(0h0), _error_1_T) connect error[1], _error_1_T_1
module AXI4Fragmenter( // @[Fragmenter.scala:37:9] input clock, // @[Fragmenter.scala:37:9] input reset, // @[Fragmenter.scala:37:9] output auto_in_aw_ready, // @[LazyModuleImp.scala:107:25] input auto_in_aw_valid, // @[LazyModuleImp.scala:107:25] input auto_in_aw_bits_id, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_aw_bits_addr, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_aw_bits_len, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_aw_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_aw_bits_burst, // @[LazyModuleImp.scala:107:25] input auto_in_aw_bits_lock, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_aw_bits_cache, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_aw_bits_prot, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_aw_bits_qos, // @[LazyModuleImp.scala:107:25] input [6:0] auto_in_aw_bits_echo_extra_id, // @[LazyModuleImp.scala:107:25] output auto_in_w_ready, // @[LazyModuleImp.scala:107:25] input auto_in_w_valid, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_w_bits_data, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_w_bits_strb, // @[LazyModuleImp.scala:107:25] input auto_in_w_bits_last, // @[LazyModuleImp.scala:107:25] input auto_in_b_ready, // @[LazyModuleImp.scala:107:25] output auto_in_b_valid, // @[LazyModuleImp.scala:107:25] output auto_in_b_bits_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_b_bits_resp, // @[LazyModuleImp.scala:107:25] output [6:0] auto_in_b_bits_echo_extra_id, // @[LazyModuleImp.scala:107:25] output auto_in_ar_ready, // @[LazyModuleImp.scala:107:25] input auto_in_ar_valid, // @[LazyModuleImp.scala:107:25] input auto_in_ar_bits_id, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_ar_bits_addr, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_ar_bits_len, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_ar_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_ar_bits_burst, // @[LazyModuleImp.scala:107:25] input auto_in_ar_bits_lock, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_ar_bits_cache, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_ar_bits_prot, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_ar_bits_qos, // @[LazyModuleImp.scala:107:25] input [6:0] auto_in_ar_bits_echo_extra_id, // @[LazyModuleImp.scala:107:25] input auto_in_r_ready, // @[LazyModuleImp.scala:107:25] output auto_in_r_valid, // @[LazyModuleImp.scala:107:25] output auto_in_r_bits_id, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_r_bits_data, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_r_bits_resp, // @[LazyModuleImp.scala:107:25] output [6:0] auto_in_r_bits_echo_extra_id, // @[LazyModuleImp.scala:107:25] output auto_in_r_bits_last, // @[LazyModuleImp.scala:107:25] input auto_out_aw_ready, // @[LazyModuleImp.scala:107:25] output auto_out_aw_valid, // @[LazyModuleImp.scala:107:25] output auto_out_aw_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_aw_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_aw_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_aw_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_aw_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_out_aw_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_aw_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_qos, // @[LazyModuleImp.scala:107:25] output [6:0] auto_out_aw_bits_echo_extra_id, // @[LazyModuleImp.scala:107:25] output auto_out_aw_bits_echo_real_last, // @[LazyModuleImp.scala:107:25] input auto_out_w_ready, // @[LazyModuleImp.scala:107:25] output auto_out_w_valid, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_w_bits_data, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_w_bits_strb, // @[LazyModuleImp.scala:107:25] output auto_out_w_bits_last, // @[LazyModuleImp.scala:107:25] output auto_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_out_b_valid, // @[LazyModuleImp.scala:107:25] input auto_out_b_bits_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_resp, // @[LazyModuleImp.scala:107:25] input [6:0] auto_out_b_bits_echo_extra_id, // @[LazyModuleImp.scala:107:25] input auto_out_b_bits_echo_real_last, // @[LazyModuleImp.scala:107:25] input auto_out_ar_ready, // @[LazyModuleImp.scala:107:25] output auto_out_ar_valid, // @[LazyModuleImp.scala:107:25] output auto_out_ar_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_ar_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_ar_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_ar_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_ar_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_out_ar_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_ar_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_qos, // @[LazyModuleImp.scala:107:25] output [6:0] auto_out_ar_bits_echo_extra_id, // @[LazyModuleImp.scala:107:25] output auto_out_ar_bits_echo_real_last, // @[LazyModuleImp.scala:107:25] output auto_out_r_ready, // @[LazyModuleImp.scala:107:25] input auto_out_r_valid, // @[LazyModuleImp.scala:107:25] input auto_out_r_bits_id, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_r_bits_data, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_r_bits_resp, // @[LazyModuleImp.scala:107:25] input [6:0] auto_out_r_bits_echo_extra_id, // @[LazyModuleImp.scala:107:25] input auto_out_r_bits_echo_real_last, // @[LazyModuleImp.scala:107:25] input auto_out_r_bits_last // @[LazyModuleImp.scala:107:25] ); wire irr_1_valid; // @[Decoupled.scala:401:19] wire [3:0] irr_1_bits_qos; // @[Decoupled.scala:401:19] wire [2:0] irr_1_bits_prot; // @[Decoupled.scala:401:19] wire [3:0] irr_1_bits_cache; // @[Decoupled.scala:401:19] wire irr_1_bits_lock; // @[Decoupled.scala:401:19] wire [1:0] irr_1_bits_burst; // @[Decoupled.scala:401:19] wire [2:0] irr_1_bits_size; // @[Decoupled.scala:401:19] wire irr_1_bits_id; // @[Decoupled.scala:401:19] wire irr_valid; // @[Decoupled.scala:401:19] wire [3:0] irr_bits_qos; // @[Decoupled.scala:401:19] wire [2:0] irr_bits_prot; // @[Decoupled.scala:401:19] wire [3:0] irr_bits_cache; // @[Decoupled.scala:401:19] wire irr_bits_lock; // @[Decoupled.scala:401:19] wire [1:0] irr_bits_burst; // @[Decoupled.scala:401:19] wire [2:0] irr_bits_size; // @[Decoupled.scala:401:19] wire irr_bits_id; // @[Decoupled.scala:401:19] wire auto_in_aw_valid_0 = auto_in_aw_valid; // @[Fragmenter.scala:37:9] wire auto_in_aw_bits_id_0 = auto_in_aw_bits_id; // @[Fragmenter.scala:37:9] wire [31:0] auto_in_aw_bits_addr_0 = auto_in_aw_bits_addr; // @[Fragmenter.scala:37:9] wire [7:0] auto_in_aw_bits_len_0 = auto_in_aw_bits_len; // @[Fragmenter.scala:37:9] wire [2:0] auto_in_aw_bits_size_0 = auto_in_aw_bits_size; // @[Fragmenter.scala:37:9] wire [1:0] auto_in_aw_bits_burst_0 = auto_in_aw_bits_burst; // @[Fragmenter.scala:37:9] wire auto_in_aw_bits_lock_0 = auto_in_aw_bits_lock; // @[Fragmenter.scala:37:9] wire [3:0] auto_in_aw_bits_cache_0 = auto_in_aw_bits_cache; // @[Fragmenter.scala:37:9] wire [2:0] auto_in_aw_bits_prot_0 = auto_in_aw_bits_prot; // @[Fragmenter.scala:37:9] wire [3:0] auto_in_aw_bits_qos_0 = auto_in_aw_bits_qos; // @[Fragmenter.scala:37:9] wire [6:0] auto_in_aw_bits_echo_extra_id_0 = auto_in_aw_bits_echo_extra_id; // @[Fragmenter.scala:37:9] wire auto_in_w_valid_0 = auto_in_w_valid; // @[Fragmenter.scala:37:9] wire [63:0] auto_in_w_bits_data_0 = auto_in_w_bits_data; // @[Fragmenter.scala:37:9] wire [7:0] auto_in_w_bits_strb_0 = auto_in_w_bits_strb; // @[Fragmenter.scala:37:9] wire auto_in_w_bits_last_0 = auto_in_w_bits_last; // @[Fragmenter.scala:37:9] wire auto_in_b_ready_0 = auto_in_b_ready; // @[Fragmenter.scala:37:9] wire auto_in_ar_valid_0 = auto_in_ar_valid; // @[Fragmenter.scala:37:9] wire auto_in_ar_bits_id_0 = auto_in_ar_bits_id; // @[Fragmenter.scala:37:9] wire [31:0] auto_in_ar_bits_addr_0 = auto_in_ar_bits_addr; // @[Fragmenter.scala:37:9] wire [7:0] auto_in_ar_bits_len_0 = auto_in_ar_bits_len; // @[Fragmenter.scala:37:9] wire [2:0] auto_in_ar_bits_size_0 = auto_in_ar_bits_size; // @[Fragmenter.scala:37:9] wire [1:0] auto_in_ar_bits_burst_0 = auto_in_ar_bits_burst; // @[Fragmenter.scala:37:9] wire auto_in_ar_bits_lock_0 = auto_in_ar_bits_lock; // @[Fragmenter.scala:37:9] wire [3:0] auto_in_ar_bits_cache_0 = auto_in_ar_bits_cache; // @[Fragmenter.scala:37:9] wire [2:0] auto_in_ar_bits_prot_0 = auto_in_ar_bits_prot; // @[Fragmenter.scala:37:9] wire [3:0] auto_in_ar_bits_qos_0 = auto_in_ar_bits_qos; // @[Fragmenter.scala:37:9] wire [6:0] auto_in_ar_bits_echo_extra_id_0 = auto_in_ar_bits_echo_extra_id; // @[Fragmenter.scala:37:9] wire auto_in_r_ready_0 = auto_in_r_ready; // @[Fragmenter.scala:37:9] wire auto_out_aw_ready_0 = auto_out_aw_ready; // @[Fragmenter.scala:37:9] wire auto_out_w_ready_0 = auto_out_w_ready; // @[Fragmenter.scala:37:9] wire auto_out_b_valid_0 = auto_out_b_valid; // @[Fragmenter.scala:37:9] wire auto_out_b_bits_id_0 = auto_out_b_bits_id; // @[Fragmenter.scala:37:9] wire [1:0] auto_out_b_bits_resp_0 = auto_out_b_bits_resp; // @[Fragmenter.scala:37:9] wire [6:0] auto_out_b_bits_echo_extra_id_0 = auto_out_b_bits_echo_extra_id; // @[Fragmenter.scala:37:9] wire auto_out_b_bits_echo_real_last_0 = auto_out_b_bits_echo_real_last; // @[Fragmenter.scala:37:9] wire auto_out_ar_ready_0 = auto_out_ar_ready; // @[Fragmenter.scala:37:9] wire auto_out_r_valid_0 = auto_out_r_valid; // @[Fragmenter.scala:37:9] wire auto_out_r_bits_id_0 = auto_out_r_bits_id; // @[Fragmenter.scala:37:9] wire [63:0] auto_out_r_bits_data_0 = auto_out_r_bits_data; // @[Fragmenter.scala:37:9] wire [1:0] auto_out_r_bits_resp_0 = auto_out_r_bits_resp; // @[Fragmenter.scala:37:9] wire [6:0] auto_out_r_bits_echo_extra_id_0 = auto_out_r_bits_echo_extra_id; // @[Fragmenter.scala:37:9] wire auto_out_r_bits_echo_real_last_0 = auto_out_r_bits_echo_real_last; // @[Fragmenter.scala:37:9] wire auto_out_r_bits_last_0 = auto_out_r_bits_last; // @[Fragmenter.scala:37:9] wire [1:0] _error_WIRE_0 = 2'h0; // @[Fragmenter.scala:211:60] wire [1:0] _error_WIRE_1 = 2'h0; // @[Fragmenter.scala:211:60] wire nodeIn_aw_ready; // @[MixedNode.scala:551:17] wire nodeIn_aw_valid = auto_in_aw_valid_0; // @[Fragmenter.scala:37:9] wire nodeIn_aw_bits_id = auto_in_aw_bits_id_0; // @[Fragmenter.scala:37:9] wire [31:0] nodeIn_aw_bits_addr = auto_in_aw_bits_addr_0; // @[Fragmenter.scala:37:9] wire [7:0] nodeIn_aw_bits_len = auto_in_aw_bits_len_0; // @[Fragmenter.scala:37:9] wire [2:0] nodeIn_aw_bits_size = auto_in_aw_bits_size_0; // @[Fragmenter.scala:37:9] wire [1:0] nodeIn_aw_bits_burst = auto_in_aw_bits_burst_0; // @[Fragmenter.scala:37:9] wire nodeIn_aw_bits_lock = auto_in_aw_bits_lock_0; // @[Fragmenter.scala:37:9] wire [3:0] nodeIn_aw_bits_cache = auto_in_aw_bits_cache_0; // @[Fragmenter.scala:37:9] wire [2:0] nodeIn_aw_bits_prot = auto_in_aw_bits_prot_0; // @[Fragmenter.scala:37:9] wire [3:0] nodeIn_aw_bits_qos = auto_in_aw_bits_qos_0; // @[Fragmenter.scala:37:9] wire [6:0] nodeIn_aw_bits_echo_extra_id = auto_in_aw_bits_echo_extra_id_0; // @[Fragmenter.scala:37:9] wire nodeIn_w_ready; // @[MixedNode.scala:551:17] wire nodeIn_w_valid = auto_in_w_valid_0; // @[Fragmenter.scala:37:9] wire [63:0] nodeIn_w_bits_data = auto_in_w_bits_data_0; // @[Fragmenter.scala:37:9] wire [7:0] nodeIn_w_bits_strb = auto_in_w_bits_strb_0; // @[Fragmenter.scala:37:9] wire nodeIn_w_bits_last = auto_in_w_bits_last_0; // @[Fragmenter.scala:37:9] wire nodeIn_b_ready = auto_in_b_ready_0; // @[Fragmenter.scala:37:9] wire nodeIn_b_valid; // @[MixedNode.scala:551:17] wire nodeIn_b_bits_id; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_b_bits_resp; // @[MixedNode.scala:551:17] wire [6:0] nodeIn_b_bits_echo_extra_id; // @[MixedNode.scala:551:17] wire nodeIn_ar_ready; // @[MixedNode.scala:551:17] wire nodeIn_ar_valid = auto_in_ar_valid_0; // @[Fragmenter.scala:37:9] wire nodeIn_ar_bits_id = auto_in_ar_bits_id_0; // @[Fragmenter.scala:37:9] wire [31:0] nodeIn_ar_bits_addr = auto_in_ar_bits_addr_0; // @[Fragmenter.scala:37:9] wire [7:0] nodeIn_ar_bits_len = auto_in_ar_bits_len_0; // @[Fragmenter.scala:37:9] wire [2:0] nodeIn_ar_bits_size = auto_in_ar_bits_size_0; // @[Fragmenter.scala:37:9] wire [1:0] nodeIn_ar_bits_burst = auto_in_ar_bits_burst_0; // @[Fragmenter.scala:37:9] wire nodeIn_ar_bits_lock = auto_in_ar_bits_lock_0; // @[Fragmenter.scala:37:9] wire [3:0] nodeIn_ar_bits_cache = auto_in_ar_bits_cache_0; // @[Fragmenter.scala:37:9] wire [2:0] nodeIn_ar_bits_prot = auto_in_ar_bits_prot_0; // @[Fragmenter.scala:37:9] wire [3:0] nodeIn_ar_bits_qos = auto_in_ar_bits_qos_0; // @[Fragmenter.scala:37:9] wire [6:0] nodeIn_ar_bits_echo_extra_id = auto_in_ar_bits_echo_extra_id_0; // @[Fragmenter.scala:37:9] wire nodeIn_r_ready = auto_in_r_ready_0; // @[Fragmenter.scala:37:9] wire nodeIn_r_valid; // @[MixedNode.scala:551:17] wire nodeIn_r_bits_id; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_r_bits_data; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_r_bits_resp; // @[MixedNode.scala:551:17] wire [6:0] nodeIn_r_bits_echo_extra_id; // @[MixedNode.scala:551:17] wire nodeIn_r_bits_last; // @[MixedNode.scala:551:17] wire nodeOut_aw_ready = auto_out_aw_ready_0; // @[Fragmenter.scala:37:9] wire nodeOut_aw_valid; // @[MixedNode.scala:542:17] wire nodeOut_aw_bits_id; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_aw_bits_addr; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_aw_bits_len; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_aw_bits_size; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_aw_bits_burst; // @[MixedNode.scala:542:17] wire nodeOut_aw_bits_lock; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_aw_bits_cache; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_aw_bits_prot; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_aw_bits_qos; // @[MixedNode.scala:542:17] wire [6:0] nodeOut_aw_bits_echo_extra_id; // @[MixedNode.scala:542:17] wire nodeOut_aw_bits_echo_real_last; // @[MixedNode.scala:542:17] wire nodeOut_w_ready = auto_out_w_ready_0; // @[Fragmenter.scala:37:9] wire nodeOut_w_valid; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_w_bits_data; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_w_bits_strb; // @[MixedNode.scala:542:17] wire nodeOut_w_bits_last; // @[MixedNode.scala:542:17] wire nodeOut_b_ready; // @[MixedNode.scala:542:17] wire nodeOut_b_valid = auto_out_b_valid_0; // @[Fragmenter.scala:37:9] wire nodeOut_b_bits_id = auto_out_b_bits_id_0; // @[Fragmenter.scala:37:9] wire [1:0] nodeOut_b_bits_resp = auto_out_b_bits_resp_0; // @[Fragmenter.scala:37:9] wire [6:0] nodeOut_b_bits_echo_extra_id = auto_out_b_bits_echo_extra_id_0; // @[Fragmenter.scala:37:9] wire nodeOut_b_bits_echo_real_last = auto_out_b_bits_echo_real_last_0; // @[Fragmenter.scala:37:9] wire nodeOut_ar_ready = auto_out_ar_ready_0; // @[Fragmenter.scala:37:9] wire nodeOut_ar_valid; // @[MixedNode.scala:542:17] wire nodeOut_ar_bits_id; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_ar_bits_addr; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_ar_bits_len; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_ar_bits_size; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_ar_bits_burst; // @[MixedNode.scala:542:17] wire nodeOut_ar_bits_lock; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_ar_bits_cache; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_ar_bits_prot; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_ar_bits_qos; // @[MixedNode.scala:542:17] wire [6:0] nodeOut_ar_bits_echo_extra_id; // @[MixedNode.scala:542:17] wire nodeOut_ar_bits_echo_real_last; // @[MixedNode.scala:542:17] wire nodeOut_r_ready; // @[MixedNode.scala:542:17] wire nodeOut_r_valid = auto_out_r_valid_0; // @[Fragmenter.scala:37:9] wire nodeOut_r_bits_id = auto_out_r_bits_id_0; // @[Fragmenter.scala:37:9] wire [63:0] nodeOut_r_bits_data = auto_out_r_bits_data_0; // @[Fragmenter.scala:37:9] wire [1:0] nodeOut_r_bits_resp = auto_out_r_bits_resp_0; // @[Fragmenter.scala:37:9] wire [6:0] nodeOut_r_bits_echo_extra_id = auto_out_r_bits_echo_extra_id_0; // @[Fragmenter.scala:37:9] wire nodeOut_r_bits_echo_real_last = auto_out_r_bits_echo_real_last_0; // @[Fragmenter.scala:37:9] wire nodeOut_r_bits_last = auto_out_r_bits_last_0; // @[Fragmenter.scala:37:9] wire auto_in_aw_ready_0; // @[Fragmenter.scala:37:9] wire auto_in_w_ready_0; // @[Fragmenter.scala:37:9] wire [6:0] auto_in_b_bits_echo_extra_id_0; // @[Fragmenter.scala:37:9] wire auto_in_b_bits_id_0; // @[Fragmenter.scala:37:9] wire [1:0] auto_in_b_bits_resp_0; // @[Fragmenter.scala:37:9] wire auto_in_b_valid_0; // @[Fragmenter.scala:37:9] wire auto_in_ar_ready_0; // @[Fragmenter.scala:37:9] wire [6:0] auto_in_r_bits_echo_extra_id_0; // @[Fragmenter.scala:37:9] wire auto_in_r_bits_id_0; // @[Fragmenter.scala:37:9] wire [63:0] auto_in_r_bits_data_0; // @[Fragmenter.scala:37:9] wire [1:0] auto_in_r_bits_resp_0; // @[Fragmenter.scala:37:9] wire auto_in_r_bits_last_0; // @[Fragmenter.scala:37:9] wire auto_in_r_valid_0; // @[Fragmenter.scala:37:9] wire [6:0] auto_out_aw_bits_echo_extra_id_0; // @[Fragmenter.scala:37:9] wire auto_out_aw_bits_echo_real_last_0; // @[Fragmenter.scala:37:9] wire auto_out_aw_bits_id_0; // @[Fragmenter.scala:37:9] wire [31:0] auto_out_aw_bits_addr_0; // @[Fragmenter.scala:37:9] wire [7:0] auto_out_aw_bits_len_0; // @[Fragmenter.scala:37:9] wire [2:0] auto_out_aw_bits_size_0; // @[Fragmenter.scala:37:9] wire [1:0] auto_out_aw_bits_burst_0; // @[Fragmenter.scala:37:9] wire auto_out_aw_bits_lock_0; // @[Fragmenter.scala:37:9] wire [3:0] auto_out_aw_bits_cache_0; // @[Fragmenter.scala:37:9] wire [2:0] auto_out_aw_bits_prot_0; // @[Fragmenter.scala:37:9] wire [3:0] auto_out_aw_bits_qos_0; // @[Fragmenter.scala:37:9] wire auto_out_aw_valid_0; // @[Fragmenter.scala:37:9] wire [63:0] auto_out_w_bits_data_0; // @[Fragmenter.scala:37:9] wire [7:0] auto_out_w_bits_strb_0; // @[Fragmenter.scala:37:9] wire auto_out_w_bits_last_0; // @[Fragmenter.scala:37:9] wire auto_out_w_valid_0; // @[Fragmenter.scala:37:9] wire auto_out_b_ready_0; // @[Fragmenter.scala:37:9] wire [6:0] auto_out_ar_bits_echo_extra_id_0; // @[Fragmenter.scala:37:9] wire auto_out_ar_bits_echo_real_last_0; // @[Fragmenter.scala:37:9] wire auto_out_ar_bits_id_0; // @[Fragmenter.scala:37:9] wire [31:0] auto_out_ar_bits_addr_0; // @[Fragmenter.scala:37:9] wire [7:0] auto_out_ar_bits_len_0; // @[Fragmenter.scala:37:9] wire [2:0] auto_out_ar_bits_size_0; // @[Fragmenter.scala:37:9] wire [1:0] auto_out_ar_bits_burst_0; // @[Fragmenter.scala:37:9] wire auto_out_ar_bits_lock_0; // @[Fragmenter.scala:37:9] wire [3:0] auto_out_ar_bits_cache_0; // @[Fragmenter.scala:37:9] wire [2:0] auto_out_ar_bits_prot_0; // @[Fragmenter.scala:37:9] wire [3:0] auto_out_ar_bits_qos_0; // @[Fragmenter.scala:37:9] wire auto_out_ar_valid_0; // @[Fragmenter.scala:37:9] wire auto_out_r_ready_0; // @[Fragmenter.scala:37:9] assign auto_in_aw_ready_0 = nodeIn_aw_ready; // @[Fragmenter.scala:37:9] assign auto_in_w_ready_0 = nodeIn_w_ready; // @[Fragmenter.scala:37:9] wire _nodeIn_b_valid_T; // @[Fragmenter.scala:207:33] assign auto_in_b_valid_0 = nodeIn_b_valid; // @[Fragmenter.scala:37:9] assign auto_in_b_bits_id_0 = nodeIn_b_bits_id; // @[Fragmenter.scala:37:9] wire [1:0] _nodeIn_b_bits_resp_T; // @[Fragmenter.scala:212:41] assign auto_in_b_bits_resp_0 = nodeIn_b_bits_resp; // @[Fragmenter.scala:37:9] assign auto_in_b_bits_echo_extra_id_0 = nodeIn_b_bits_echo_extra_id; // @[Fragmenter.scala:37:9] assign auto_in_ar_ready_0 = nodeIn_ar_ready; // @[Fragmenter.scala:37:9] assign nodeOut_r_ready = nodeIn_r_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_in_r_valid_0 = nodeIn_r_valid; // @[Fragmenter.scala:37:9] assign auto_in_r_bits_id_0 = nodeIn_r_bits_id; // @[Fragmenter.scala:37:9] assign auto_in_r_bits_data_0 = nodeIn_r_bits_data; // @[Fragmenter.scala:37:9] assign auto_in_r_bits_resp_0 = nodeIn_r_bits_resp; // @[Fragmenter.scala:37:9] assign auto_in_r_bits_echo_extra_id_0 = nodeIn_r_bits_echo_extra_id; // @[Fragmenter.scala:37:9] wire _nodeIn_r_bits_last_T; // @[Fragmenter.scala:198:41] assign auto_in_r_bits_last_0 = nodeIn_r_bits_last; // @[Fragmenter.scala:37:9] wire _nodeOut_aw_valid_T_1; // @[Fragmenter.scala:167:35] assign auto_out_aw_valid_0 = nodeOut_aw_valid; // @[Fragmenter.scala:37:9] wire in_aw_bits_id; // @[Fragmenter.scala:66:23] assign auto_out_aw_bits_id_0 = nodeOut_aw_bits_id; // @[Fragmenter.scala:37:9] wire [31:0] in_aw_bits_addr; // @[Fragmenter.scala:66:23] assign auto_out_aw_bits_addr_0 = nodeOut_aw_bits_addr; // @[Fragmenter.scala:37:9] wire [7:0] in_aw_bits_len; // @[Fragmenter.scala:66:23] assign auto_out_aw_bits_len_0 = nodeOut_aw_bits_len; // @[Fragmenter.scala:37:9] wire [2:0] in_aw_bits_size; // @[Fragmenter.scala:66:23] assign auto_out_aw_bits_size_0 = nodeOut_aw_bits_size; // @[Fragmenter.scala:37:9] wire [1:0] in_aw_bits_burst; // @[Fragmenter.scala:66:23] assign auto_out_aw_bits_burst_0 = nodeOut_aw_bits_burst; // @[Fragmenter.scala:37:9] wire in_aw_bits_lock; // @[Fragmenter.scala:66:23] assign auto_out_aw_bits_lock_0 = nodeOut_aw_bits_lock; // @[Fragmenter.scala:37:9] wire [3:0] in_aw_bits_cache; // @[Fragmenter.scala:66:23] assign auto_out_aw_bits_cache_0 = nodeOut_aw_bits_cache; // @[Fragmenter.scala:37:9] wire [2:0] in_aw_bits_prot; // @[Fragmenter.scala:66:23] assign auto_out_aw_bits_prot_0 = nodeOut_aw_bits_prot; // @[Fragmenter.scala:37:9] wire [3:0] in_aw_bits_qos; // @[Fragmenter.scala:66:23] assign auto_out_aw_bits_qos_0 = nodeOut_aw_bits_qos; // @[Fragmenter.scala:37:9] wire [6:0] in_aw_bits_echo_extra_id; // @[Fragmenter.scala:66:23] assign auto_out_aw_bits_echo_extra_id_0 = nodeOut_aw_bits_echo_extra_id; // @[Fragmenter.scala:37:9] wire aw_last; // @[Fragmenter.scala:118:27] assign auto_out_aw_bits_echo_real_last_0 = nodeOut_aw_bits_echo_real_last; // @[Fragmenter.scala:37:9] wire _nodeOut_w_valid_T_2; // @[Fragmenter.scala:185:33] assign auto_out_w_valid_0 = nodeOut_w_valid; // @[Fragmenter.scala:37:9] wire [63:0] in_w_bits_data; // @[Decoupled.scala:401:19] assign auto_out_w_bits_data_0 = nodeOut_w_bits_data; // @[Fragmenter.scala:37:9] wire [7:0] in_w_bits_strb; // @[Decoupled.scala:401:19] assign auto_out_w_bits_strb_0 = nodeOut_w_bits_strb; // @[Fragmenter.scala:37:9] wire w_last; // @[Fragmenter.scala:179:27] assign auto_out_w_bits_last_0 = nodeOut_w_bits_last; // @[Fragmenter.scala:37:9] wire _nodeOut_b_ready_T_1; // @[Fragmenter.scala:208:33] assign auto_out_b_ready_0 = nodeOut_b_ready; // @[Fragmenter.scala:37:9] assign nodeIn_b_bits_id = nodeOut_b_bits_id; // @[MixedNode.scala:542:17, :551:17] wire shiftAmount = nodeOut_b_bits_id; // @[OneHot.scala:64:49] assign nodeIn_b_bits_echo_extra_id = nodeOut_b_bits_echo_extra_id; // @[MixedNode.scala:542:17, :551:17] wire in_ar_ready = nodeOut_ar_ready; // @[Fragmenter.scala:66:23] wire in_ar_valid; // @[Fragmenter.scala:66:23] assign auto_out_ar_valid_0 = nodeOut_ar_valid; // @[Fragmenter.scala:37:9] wire in_ar_bits_id; // @[Fragmenter.scala:66:23] assign auto_out_ar_bits_id_0 = nodeOut_ar_bits_id; // @[Fragmenter.scala:37:9] wire [31:0] in_ar_bits_addr; // @[Fragmenter.scala:66:23] assign auto_out_ar_bits_addr_0 = nodeOut_ar_bits_addr; // @[Fragmenter.scala:37:9] wire [7:0] in_ar_bits_len; // @[Fragmenter.scala:66:23] assign auto_out_ar_bits_len_0 = nodeOut_ar_bits_len; // @[Fragmenter.scala:37:9] wire [2:0] in_ar_bits_size; // @[Fragmenter.scala:66:23] assign auto_out_ar_bits_size_0 = nodeOut_ar_bits_size; // @[Fragmenter.scala:37:9] wire [1:0] in_ar_bits_burst; // @[Fragmenter.scala:66:23] assign auto_out_ar_bits_burst_0 = nodeOut_ar_bits_burst; // @[Fragmenter.scala:37:9] wire in_ar_bits_lock; // @[Fragmenter.scala:66:23] assign auto_out_ar_bits_lock_0 = nodeOut_ar_bits_lock; // @[Fragmenter.scala:37:9] wire [3:0] in_ar_bits_cache; // @[Fragmenter.scala:66:23] assign auto_out_ar_bits_cache_0 = nodeOut_ar_bits_cache; // @[Fragmenter.scala:37:9] wire [2:0] in_ar_bits_prot; // @[Fragmenter.scala:66:23] assign auto_out_ar_bits_prot_0 = nodeOut_ar_bits_prot; // @[Fragmenter.scala:37:9] wire [3:0] in_ar_bits_qos; // @[Fragmenter.scala:66:23] assign auto_out_ar_bits_qos_0 = nodeOut_ar_bits_qos; // @[Fragmenter.scala:37:9] wire [6:0] in_ar_bits_echo_extra_id; // @[Fragmenter.scala:66:23] assign auto_out_ar_bits_echo_extra_id_0 = nodeOut_ar_bits_echo_extra_id; // @[Fragmenter.scala:37:9] wire ar_last; // @[Fragmenter.scala:118:27] assign auto_out_ar_bits_echo_real_last_0 = nodeOut_ar_bits_echo_real_last; // @[Fragmenter.scala:37:9] assign auto_out_r_ready_0 = nodeOut_r_ready; // @[Fragmenter.scala:37:9] assign nodeIn_r_valid = nodeOut_r_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_r_bits_id = nodeOut_r_bits_id; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_r_bits_data = nodeOut_r_bits_data; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_r_bits_resp = nodeOut_r_bits_resp; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_r_bits_echo_extra_id = nodeOut_r_bits_echo_extra_id; // @[MixedNode.scala:542:17, :551:17] wire _irr_ready_T; // @[Fragmenter.scala:119:30] assign in_ar_valid = irr_valid; // @[Decoupled.scala:401:19] assign in_ar_bits_id = irr_bits_id; // @[Decoupled.scala:401:19] assign in_ar_bits_size = irr_bits_size; // @[Decoupled.scala:401:19] assign in_ar_bits_burst = irr_bits_burst; // @[Decoupled.scala:401:19] assign in_ar_bits_lock = irr_bits_lock; // @[Decoupled.scala:401:19] assign in_ar_bits_cache = irr_bits_cache; // @[Decoupled.scala:401:19] assign in_ar_bits_prot = irr_bits_prot; // @[Decoupled.scala:401:19] assign in_ar_bits_qos = irr_bits_qos; // @[Decoupled.scala:401:19] wire [6:0] irr_bits_echo_extra_id; // @[Decoupled.scala:401:19] assign in_ar_bits_echo_extra_id = irr_bits_echo_extra_id; // @[Decoupled.scala:401:19] wire [31:0] irr_bits_addr; // @[Decoupled.scala:401:19] wire [7:0] irr_bits_len; // @[Decoupled.scala:401:19] wire irr_ready; // @[Decoupled.scala:401:19] assign nodeOut_ar_valid = in_ar_valid; // @[Fragmenter.scala:66:23] assign nodeOut_ar_bits_id = in_ar_bits_id; // @[Fragmenter.scala:66:23] wire [31:0] _out_bits_addr_T_5; // @[Fragmenter.scala:130:26] assign nodeOut_ar_bits_addr = in_ar_bits_addr; // @[Fragmenter.scala:66:23] wire [7:0] beats1; // @[Fragmenter.scala:105:25] assign nodeOut_ar_bits_len = in_ar_bits_len; // @[Fragmenter.scala:66:23] assign nodeOut_ar_bits_size = in_ar_bits_size; // @[Fragmenter.scala:66:23] assign nodeOut_ar_bits_burst = in_ar_bits_burst; // @[Fragmenter.scala:66:23] assign nodeOut_ar_bits_lock = in_ar_bits_lock; // @[Fragmenter.scala:66:23] assign nodeOut_ar_bits_cache = in_ar_bits_cache; // @[Fragmenter.scala:66:23] assign nodeOut_ar_bits_prot = in_ar_bits_prot; // @[Fragmenter.scala:66:23] assign nodeOut_ar_bits_qos = in_ar_bits_qos; // @[Fragmenter.scala:66:23] assign nodeOut_ar_bits_echo_extra_id = in_ar_bits_echo_extra_id; // @[Fragmenter.scala:66:23] reg busy; // @[Fragmenter.scala:68:29] reg [31:0] r_addr; // @[Fragmenter.scala:69:25] reg [7:0] r_len; // @[Fragmenter.scala:70:25] wire [7:0] len = busy ? r_len : irr_bits_len; // @[Decoupled.scala:401:19] wire [31:0] addr = busy ? r_addr : irr_bits_addr; // @[Decoupled.scala:401:19] wire [31:0] _support1_T = addr; // @[Parameters.scala:137:31] wire [2:0] lo = addr[2:0]; // @[Fragmenter.scala:73:23, :75:49] wire [7:0] alignment = addr[10:3]; // @[Fragmenter.scala:73:23, :77:29] wire [32:0] _support1_T_1 = {1'h0, _support1_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _support1_T_2 = _support1_T_1 & 33'hCA112000; // @[Parameters.scala:137:{41,46}] wire [32:0] _support1_T_3 = _support1_T_2; // @[Parameters.scala:137:46] wire _support1_T_4 = _support1_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _support1_T_5 = {addr[31:17], addr[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [32:0] _support1_T_6 = {1'h0, _support1_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _support1_T_7 = _support1_T_6 & 33'hCA110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _support1_T_8 = _support1_T_7; // @[Parameters.scala:137:46] wire _support1_T_9 = _support1_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _support1_T_10 = {addr[31:21], addr[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31] wire [32:0] _support1_T_11 = {1'h0, _support1_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _support1_T_12 = _support1_T_11 & 33'hCA103000; // @[Parameters.scala:137:{41,46}] wire [32:0] _support1_T_13 = _support1_T_12; // @[Parameters.scala:137:46] wire _support1_T_14 = _support1_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _support1_T_15 = {addr[31:26], addr[25:0] ^ 26'h2000000}; // @[Parameters.scala:137:31] wire [32:0] _support1_T_16 = {1'h0, _support1_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _support1_T_17 = _support1_T_16 & 33'hCA110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _support1_T_18 = _support1_T_17; // @[Parameters.scala:137:46] wire _support1_T_19 = _support1_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _support1_T_20 = {addr[31:28], addr[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [32:0] _support1_T_21 = {1'h0, _support1_T_20}; // @[Parameters.scala:137:{31,41}] wire [32:0] _support1_T_22 = _support1_T_21 & 33'hC8000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _support1_T_23 = _support1_T_22; // @[Parameters.scala:137:46] wire _support1_T_24 = _support1_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _support1_T_25 = {addr[31], addr[30:0] ^ 31'h40000000}; // @[Parameters.scala:137:31] wire [32:0] _support1_T_26 = {1'h0, _support1_T_25}; // @[Parameters.scala:137:{31,41}] wire [32:0] _support1_T_27 = _support1_T_26 & 33'hC0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _support1_T_28 = _support1_T_27; // @[Parameters.scala:137:46] wire _support1_T_29 = _support1_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _support1_T_30 = addr ^ 32'h80000000; // @[Parameters.scala:137:31] wire [32:0] _support1_T_31 = {1'h0, _support1_T_30}; // @[Parameters.scala:137:{31,41}] wire [32:0] _support1_T_32 = _support1_T_31 & 33'hCA110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _support1_T_33 = _support1_T_32; // @[Parameters.scala:137:46] wire _support1_T_34 = _support1_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _support1_T_35 = _support1_T_4 | _support1_T_9; // @[Parameters.scala:137:59] wire _support1_T_36 = _support1_T_35 | _support1_T_14; // @[Parameters.scala:137:59] wire _support1_T_37 = _support1_T_36 | _support1_T_19; // @[Parameters.scala:137:59] wire _support1_T_38 = _support1_T_37 | _support1_T_24; // @[Parameters.scala:137:59] wire _support1_T_39 = _support1_T_38 | _support1_T_29; // @[Parameters.scala:137:59] wire _support1_T_40 = _support1_T_39 | _support1_T_34; // @[Parameters.scala:137:59] wire [31:0] _support1_T_41 = {addr[31:14], addr[13:0] ^ 14'h3000}; // @[Parameters.scala:137:31] wire [32:0] _support1_T_42 = {1'h0, _support1_T_41}; // @[Parameters.scala:137:{31,41}] wire [32:0] _support1_T_43 = _support1_T_42 & 33'hCA113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _support1_T_44 = _support1_T_43; // @[Parameters.scala:137:46] wire _support1_T_45 = _support1_T_44 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [2:0] _support1_T_46 = {3{_support1_T_40}}; // @[Mux.scala:30:73] wire [7:0] _support1_T_47 = {8{_support1_T_45}}; // @[Mux.scala:30:73] wire [7:0] _support1_T_48 = {5'h0, _support1_T_46} | _support1_T_47; // @[Mux.scala:30:73] wire [7:0] support1 = _support1_T_48; // @[Mux.scala:30:73] wire [6:0] _fillLow_T = len[7:1]; // @[package.scala:262:48] wire [7:0] _fillLow_T_1 = {len[7], len[6:0] | _fillLow_T}; // @[package.scala:262:{43,48}] wire [5:0] _fillLow_T_2 = _fillLow_T_1[7:2]; // @[package.scala:262:{43,48}] wire [7:0] _fillLow_T_3 = {_fillLow_T_1[7:6], _fillLow_T_1[5:0] | _fillLow_T_2}; // @[package.scala:262:{43,48}] wire [3:0] _fillLow_T_4 = _fillLow_T_3[7:4]; // @[package.scala:262:{43,48}] wire [7:0] _fillLow_T_5 = {_fillLow_T_4, _fillLow_T_3[3:0] | _fillLow_T_4}; // @[package.scala:262:{43,48}] wire [7:0] _fillLow_T_6 = _fillLow_T_5; // @[package.scala:262:43, :263:17] wire [6:0] fillLow = _fillLow_T_6[7:1]; // @[package.scala:263:17] wire [7:0] _wipeHigh_T = ~len; // @[Fragmenter.scala:72:23, :94:33] wire [8:0] _wipeHigh_T_1 = {_wipeHigh_T, 1'h0}; // @[package.scala:253:48] wire [7:0] _wipeHigh_T_2 = _wipeHigh_T_1[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _wipeHigh_T_3 = _wipeHigh_T | _wipeHigh_T_2; // @[package.scala:253:{43,53}] wire [9:0] _wipeHigh_T_4 = {_wipeHigh_T_3, 2'h0}; // @[package.scala:253:{43,48}] wire [7:0] _wipeHigh_T_5 = _wipeHigh_T_4[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _wipeHigh_T_6 = _wipeHigh_T_3 | _wipeHigh_T_5; // @[package.scala:253:{43,53}] wire [11:0] _wipeHigh_T_7 = {_wipeHigh_T_6, 4'h0}; // @[package.scala:253:{43,48}] wire [7:0] _wipeHigh_T_8 = _wipeHigh_T_7[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _wipeHigh_T_9 = _wipeHigh_T_6 | _wipeHigh_T_8; // @[package.scala:253:{43,53}] wire [7:0] _wipeHigh_T_10 = _wipeHigh_T_9; // @[package.scala:253:43, :254:17] wire [7:0] wipeHigh = ~_wipeHigh_T_10; // @[package.scala:254:17] wire [7:0] remain1 = {1'h0, fillLow} | wipeHigh; // @[Fragmenter.scala:93:37, :94:24, :95:32] wire [8:0] _align1_T = {alignment, 1'h0}; // @[package.scala:253:48] wire [7:0] _align1_T_1 = _align1_T[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _align1_T_2 = alignment | _align1_T_1; // @[package.scala:253:{43,53}] wire [9:0] _align1_T_3 = {_align1_T_2, 2'h0}; // @[package.scala:253:{43,48}] wire [7:0] _align1_T_4 = _align1_T_3[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _align1_T_5 = _align1_T_2 | _align1_T_4; // @[package.scala:253:{43,53}] wire [11:0] _align1_T_6 = {_align1_T_5, 4'h0}; // @[package.scala:253:{43,48}] wire [7:0] _align1_T_7 = _align1_T_6[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _align1_T_8 = _align1_T_5 | _align1_T_7; // @[package.scala:253:{43,53}] wire [7:0] _align1_T_9 = _align1_T_8; // @[package.scala:253:43, :254:17] wire [7:0] align1 = ~_align1_T_9; // @[package.scala:254:17] wire [7:0] _maxSupported1_T = remain1 & align1; // @[Fragmenter.scala:95:32, :96:24, :97:37] wire [7:0] maxSupported1 = _maxSupported1_T & support1; // @[Mux.scala:30:73] wire fixed = irr_bits_burst == 2'h0; // @[Decoupled.scala:401:19] wire narrow = irr_bits_size != 3'h3; // @[Decoupled.scala:401:19] wire bad = fixed | narrow; // @[Fragmenter.scala:100:34, :101:34, :102:25] assign beats1 = bad ? 8'h0 : maxSupported1; // @[Fragmenter.scala:97:46, :102:25, :105:25] assign in_ar_bits_len = beats1; // @[Fragmenter.scala:66:23, :105:25] wire [8:0] _beats_T = {beats1, 1'h0}; // @[package.scala:241:35] wire [8:0] _beats_T_1 = {_beats_T[8:1], 1'h1}; // @[package.scala:241:{35,40}] wire [8:0] _beats_T_2 = {1'h0, beats1}; // @[package.scala:241:53] wire [8:0] _beats_T_3 = ~_beats_T_2; // @[package.scala:241:{49,53}] wire [8:0] beats = _beats_T_1 & _beats_T_3; // @[package.scala:241:{40,47,49}] wire [15:0] _inc_addr_T = {7'h0, beats} << irr_bits_size; // @[Decoupled.scala:401:19] wire [32:0] _inc_addr_T_1 = {1'h0, addr} + {17'h0, _inc_addr_T}; // @[Fragmenter.scala:73:23, :108:{29,38}] wire [31:0] inc_addr = _inc_addr_T_1[31:0]; // @[Fragmenter.scala:108:29] wire [15:0] _wrapMask_T = {irr_bits_len, 8'hFF}; // @[Decoupled.scala:401:19] wire [22:0] _wrapMask_T_1 = {7'h0, _wrapMask_T} << irr_bits_size; // @[Decoupled.scala:401:19] wire [14:0] wrapMask = _wrapMask_T_1[22:8]; // @[Bundles.scala:33:{21,30}] wire [31:0] mux_addr; // @[Fragmenter.scala:110:35] wire [31:0] _mux_addr_T = {17'h0, inc_addr[14:0] & wrapMask}; // @[Fragmenter.scala:108:29, :112:33] wire [31:0] _mux_addr_T_1 = ~irr_bits_addr; // @[Decoupled.scala:401:19] wire [31:0] _mux_addr_T_2 = {_mux_addr_T_1[31:15], _mux_addr_T_1[14:0] | wrapMask}; // @[Fragmenter.scala:112:{49,62}] wire [31:0] _mux_addr_T_3 = ~_mux_addr_T_2; // @[Fragmenter.scala:112:{47,62}] wire [31:0] _mux_addr_T_4 = _mux_addr_T | _mux_addr_T_3; // @[Fragmenter.scala:112:{33,45,47}] assign mux_addr = fixed ? irr_bits_addr : irr_bits_burst == 2'h2 ? _mux_addr_T_4 : inc_addr; // @[Decoupled.scala:401:19] assign ar_last = beats1 == len; // @[Fragmenter.scala:72:23, :105:25, :118:27] assign nodeOut_ar_bits_echo_real_last = ar_last; // @[Fragmenter.scala:118:27] assign _irr_ready_T = in_ar_ready & ar_last; // @[Fragmenter.scala:66:23, :118:27, :119:30] assign irr_ready = _irr_ready_T; // @[Decoupled.scala:401:19] wire [31:0] _out_bits_addr_T = ~addr; // @[Fragmenter.scala:73:23, :130:28] wire [9:0] _out_bits_addr_T_1 = 10'h7 << irr_bits_size; // @[Decoupled.scala:401:19] wire [2:0] _out_bits_addr_T_2 = _out_bits_addr_T_1[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _out_bits_addr_T_3 = ~_out_bits_addr_T_2; // @[package.scala:243:{46,76}] wire [31:0] _out_bits_addr_T_4 = {_out_bits_addr_T[31:3], _out_bits_addr_T[2:0] | _out_bits_addr_T_3}; // @[package.scala:243:46] assign _out_bits_addr_T_5 = ~_out_bits_addr_T_4; // @[Fragmenter.scala:130:{26,34}] assign in_ar_bits_addr = _out_bits_addr_T_5; // @[Fragmenter.scala:66:23, :130:26] wire _busy_T = ~ar_last; // @[Fragmenter.scala:118:27, :133:19] wire [9:0] _r_len_T = {2'h0, len} - {1'h0, beats}; // @[package.scala:241:47] wire [8:0] _r_len_T_1 = _r_len_T[8:0]; // @[Fragmenter.scala:135:25] wire _irr_ready_T_1; // @[Fragmenter.scala:119:30] wire in_aw_valid = irr_1_valid; // @[Decoupled.scala:401:19] assign in_aw_bits_id = irr_1_bits_id; // @[Decoupled.scala:401:19] assign in_aw_bits_size = irr_1_bits_size; // @[Decoupled.scala:401:19] assign in_aw_bits_burst = irr_1_bits_burst; // @[Decoupled.scala:401:19] assign in_aw_bits_lock = irr_1_bits_lock; // @[Decoupled.scala:401:19] assign in_aw_bits_cache = irr_1_bits_cache; // @[Decoupled.scala:401:19] assign in_aw_bits_prot = irr_1_bits_prot; // @[Decoupled.scala:401:19] assign in_aw_bits_qos = irr_1_bits_qos; // @[Decoupled.scala:401:19] wire [6:0] irr_1_bits_echo_extra_id; // @[Decoupled.scala:401:19] assign in_aw_bits_echo_extra_id = irr_1_bits_echo_extra_id; // @[Decoupled.scala:401:19] wire [31:0] irr_1_bits_addr; // @[Decoupled.scala:401:19] wire [7:0] irr_1_bits_len; // @[Decoupled.scala:401:19] wire irr_1_ready; // @[Decoupled.scala:401:19] wire _in_aw_ready_T_1; // @[Fragmenter.scala:168:35] assign nodeOut_aw_bits_id = in_aw_bits_id; // @[Fragmenter.scala:66:23] wire [31:0] _out_bits_addr_T_11; // @[Fragmenter.scala:130:26] assign nodeOut_aw_bits_addr = in_aw_bits_addr; // @[Fragmenter.scala:66:23] wire [7:0] beats1_1; // @[Fragmenter.scala:105:25] assign nodeOut_aw_bits_len = in_aw_bits_len; // @[Fragmenter.scala:66:23] assign nodeOut_aw_bits_size = in_aw_bits_size; // @[Fragmenter.scala:66:23] assign nodeOut_aw_bits_burst = in_aw_bits_burst; // @[Fragmenter.scala:66:23] assign nodeOut_aw_bits_lock = in_aw_bits_lock; // @[Fragmenter.scala:66:23] assign nodeOut_aw_bits_cache = in_aw_bits_cache; // @[Fragmenter.scala:66:23] assign nodeOut_aw_bits_prot = in_aw_bits_prot; // @[Fragmenter.scala:66:23] assign nodeOut_aw_bits_qos = in_aw_bits_qos; // @[Fragmenter.scala:66:23] assign nodeOut_aw_bits_echo_extra_id = in_aw_bits_echo_extra_id; // @[Fragmenter.scala:66:23] wire in_aw_ready; // @[Fragmenter.scala:66:23] reg busy_1; // @[Fragmenter.scala:68:29] reg [31:0] r_addr_1; // @[Fragmenter.scala:69:25] reg [7:0] r_len_1; // @[Fragmenter.scala:70:25] wire [7:0] len_1 = busy_1 ? r_len_1 : irr_1_bits_len; // @[Decoupled.scala:401:19] wire [31:0] addr_1 = busy_1 ? r_addr_1 : irr_1_bits_addr; // @[Decoupled.scala:401:19] wire [31:0] _support1_T_49 = addr_1; // @[Parameters.scala:137:31] wire [2:0] lo_1 = addr_1[2:0]; // @[Fragmenter.scala:73:23, :75:49] wire [7:0] alignment_1 = addr_1[10:3]; // @[Fragmenter.scala:73:23, :77:29] wire [32:0] _support1_T_50 = {1'h0, _support1_T_49}; // @[Parameters.scala:137:{31,41}] wire [32:0] _support1_T_51 = _support1_T_50 & 33'hCA102000; // @[Parameters.scala:137:{41,46}] wire [32:0] _support1_T_52 = _support1_T_51; // @[Parameters.scala:137:46] wire _support1_T_53 = _support1_T_52 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _support1_T_54 = {addr_1[31:21], addr_1[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31] wire [32:0] _support1_T_55 = {1'h0, _support1_T_54}; // @[Parameters.scala:137:{31,41}] wire [32:0] _support1_T_56 = _support1_T_55 & 33'hCA103000; // @[Parameters.scala:137:{41,46}] wire [32:0] _support1_T_57 = _support1_T_56; // @[Parameters.scala:137:46] wire _support1_T_58 = _support1_T_57 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _support1_T_59 = {addr_1[31:26], addr_1[25:0] ^ 26'h2000000}; // @[Parameters.scala:137:31] wire [32:0] _support1_T_60 = {1'h0, _support1_T_59}; // @[Parameters.scala:137:{31,41}] wire [32:0] _support1_T_61 = _support1_T_60 & 33'hCA100000; // @[Parameters.scala:137:{41,46}] wire [32:0] _support1_T_62 = _support1_T_61; // @[Parameters.scala:137:46] wire _support1_T_63 = _support1_T_62 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _support1_T_64 = {addr_1[31:28], addr_1[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [32:0] _support1_T_65 = {1'h0, _support1_T_64}; // @[Parameters.scala:137:{31,41}] wire [32:0] _support1_T_66 = _support1_T_65 & 33'hC8000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _support1_T_67 = _support1_T_66; // @[Parameters.scala:137:46] wire _support1_T_68 = _support1_T_67 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _support1_T_69 = addr_1 ^ 32'h80000000; // @[Parameters.scala:137:31] wire [32:0] _support1_T_70 = {1'h0, _support1_T_69}; // @[Parameters.scala:137:{31,41}] wire [32:0] _support1_T_71 = _support1_T_70 & 33'hCA100000; // @[Parameters.scala:137:{41,46}] wire [32:0] _support1_T_72 = _support1_T_71; // @[Parameters.scala:137:46] wire _support1_T_73 = _support1_T_72 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _support1_T_74 = _support1_T_53 | _support1_T_58; // @[Parameters.scala:137:59] wire _support1_T_75 = _support1_T_74 | _support1_T_63; // @[Parameters.scala:137:59] wire _support1_T_76 = _support1_T_75 | _support1_T_68; // @[Parameters.scala:137:59] wire _support1_T_77 = _support1_T_76 | _support1_T_73; // @[Parameters.scala:137:59] wire [31:0] _support1_T_78 = {addr_1[31:14], addr_1[13:0] ^ 14'h3000}; // @[Parameters.scala:137:31] wire [32:0] _support1_T_79 = {1'h0, _support1_T_78}; // @[Parameters.scala:137:{31,41}] wire [32:0] _support1_T_80 = _support1_T_79 & 33'hCA103000; // @[Parameters.scala:137:{41,46}] wire [32:0] _support1_T_81 = _support1_T_80; // @[Parameters.scala:137:46] wire _support1_T_82 = _support1_T_81 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _support1_T_83 = {addr_1[31], addr_1[30:0] ^ 31'h40000000}; // @[Parameters.scala:137:31] wire [32:0] _support1_T_84 = {1'h0, _support1_T_83}; // @[Parameters.scala:137:{31,41}] wire [32:0] _support1_T_85 = _support1_T_84 & 33'hC0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _support1_T_86 = _support1_T_85; // @[Parameters.scala:137:46] wire _support1_T_87 = _support1_T_86 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [2:0] _support1_T_88 = {3{_support1_T_77}}; // @[Mux.scala:30:73] wire [7:0] _support1_T_89 = {8{_support1_T_82}}; // @[Mux.scala:30:73] wire [4:0] _support1_T_90 = {5{_support1_T_87}}; // @[Mux.scala:30:73] wire [7:0] _support1_T_91 = {5'h0, _support1_T_88} | _support1_T_89; // @[Mux.scala:30:73] wire [7:0] _support1_T_92 = {_support1_T_91[7:5], _support1_T_91[4:0] | _support1_T_90}; // @[Mux.scala:30:73] wire [7:0] support1_1 = _support1_T_92; // @[Mux.scala:30:73] wire [6:0] _fillLow_T_7 = len_1[7:1]; // @[package.scala:262:48] wire [7:0] _fillLow_T_8 = {len_1[7], len_1[6:0] | _fillLow_T_7}; // @[package.scala:262:{43,48}] wire [5:0] _fillLow_T_9 = _fillLow_T_8[7:2]; // @[package.scala:262:{43,48}] wire [7:0] _fillLow_T_10 = {_fillLow_T_8[7:6], _fillLow_T_8[5:0] | _fillLow_T_9}; // @[package.scala:262:{43,48}] wire [3:0] _fillLow_T_11 = _fillLow_T_10[7:4]; // @[package.scala:262:{43,48}] wire [7:0] _fillLow_T_12 = {_fillLow_T_11, _fillLow_T_10[3:0] | _fillLow_T_11}; // @[package.scala:262:{43,48}] wire [7:0] _fillLow_T_13 = _fillLow_T_12; // @[package.scala:262:43, :263:17] wire [6:0] fillLow_1 = _fillLow_T_13[7:1]; // @[package.scala:263:17] wire [7:0] _wipeHigh_T_11 = ~len_1; // @[Fragmenter.scala:72:23, :94:33] wire [8:0] _wipeHigh_T_12 = {_wipeHigh_T_11, 1'h0}; // @[package.scala:253:48] wire [7:0] _wipeHigh_T_13 = _wipeHigh_T_12[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _wipeHigh_T_14 = _wipeHigh_T_11 | _wipeHigh_T_13; // @[package.scala:253:{43,53}] wire [9:0] _wipeHigh_T_15 = {_wipeHigh_T_14, 2'h0}; // @[package.scala:253:{43,48}] wire [7:0] _wipeHigh_T_16 = _wipeHigh_T_15[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _wipeHigh_T_17 = _wipeHigh_T_14 | _wipeHigh_T_16; // @[package.scala:253:{43,53}] wire [11:0] _wipeHigh_T_18 = {_wipeHigh_T_17, 4'h0}; // @[package.scala:253:{43,48}] wire [7:0] _wipeHigh_T_19 = _wipeHigh_T_18[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _wipeHigh_T_20 = _wipeHigh_T_17 | _wipeHigh_T_19; // @[package.scala:253:{43,53}] wire [7:0] _wipeHigh_T_21 = _wipeHigh_T_20; // @[package.scala:253:43, :254:17] wire [7:0] wipeHigh_1 = ~_wipeHigh_T_21; // @[package.scala:254:17] wire [7:0] remain1_1 = {1'h0, fillLow_1} | wipeHigh_1; // @[Fragmenter.scala:93:37, :94:24, :95:32] wire [8:0] _align1_T_10 = {alignment_1, 1'h0}; // @[package.scala:253:48] wire [7:0] _align1_T_11 = _align1_T_10[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _align1_T_12 = alignment_1 | _align1_T_11; // @[package.scala:253:{43,53}] wire [9:0] _align1_T_13 = {_align1_T_12, 2'h0}; // @[package.scala:253:{43,48}] wire [7:0] _align1_T_14 = _align1_T_13[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _align1_T_15 = _align1_T_12 | _align1_T_14; // @[package.scala:253:{43,53}] wire [11:0] _align1_T_16 = {_align1_T_15, 4'h0}; // @[package.scala:253:{43,48}] wire [7:0] _align1_T_17 = _align1_T_16[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _align1_T_18 = _align1_T_15 | _align1_T_17; // @[package.scala:253:{43,53}] wire [7:0] _align1_T_19 = _align1_T_18; // @[package.scala:253:43, :254:17] wire [7:0] align1_1 = ~_align1_T_19; // @[package.scala:254:17] wire [7:0] _maxSupported1_T_1 = remain1_1 & align1_1; // @[Fragmenter.scala:95:32, :96:24, :97:37] wire [7:0] maxSupported1_1 = _maxSupported1_T_1 & support1_1; // @[Mux.scala:30:73] wire fixed_1 = irr_1_bits_burst == 2'h0; // @[Decoupled.scala:401:19] wire narrow_1 = irr_1_bits_size != 3'h3; // @[Decoupled.scala:401:19] wire bad_1 = fixed_1 | narrow_1; // @[Fragmenter.scala:100:34, :101:34, :102:25] assign beats1_1 = bad_1 ? 8'h0 : maxSupported1_1; // @[Fragmenter.scala:97:46, :102:25, :105:25] assign in_aw_bits_len = beats1_1; // @[Fragmenter.scala:66:23, :105:25] wire [8:0] _beats_T_4 = {beats1_1, 1'h0}; // @[package.scala:241:35] wire [8:0] _beats_T_5 = {_beats_T_4[8:1], 1'h1}; // @[package.scala:241:{35,40}] wire [8:0] _beats_T_6 = {1'h0, beats1_1}; // @[package.scala:241:53] wire [8:0] _beats_T_7 = ~_beats_T_6; // @[package.scala:241:{49,53}] wire [8:0] w_beats = _beats_T_5 & _beats_T_7; // @[package.scala:241:{40,47,49}] wire [15:0] _inc_addr_T_2 = {7'h0, w_beats} << irr_1_bits_size; // @[Decoupled.scala:401:19] wire [32:0] _inc_addr_T_3 = {1'h0, addr_1} + {17'h0, _inc_addr_T_2}; // @[Fragmenter.scala:73:23, :108:{29,38}] wire [31:0] inc_addr_1 = _inc_addr_T_3[31:0]; // @[Fragmenter.scala:108:29] wire [15:0] _wrapMask_T_2 = {irr_1_bits_len, 8'hFF}; // @[Decoupled.scala:401:19] wire [22:0] _wrapMask_T_3 = {7'h0, _wrapMask_T_2} << irr_1_bits_size; // @[Decoupled.scala:401:19] wire [14:0] wrapMask_1 = _wrapMask_T_3[22:8]; // @[Bundles.scala:33:{21,30}] wire [31:0] mux_addr_1; // @[Fragmenter.scala:110:35] wire [31:0] _mux_addr_T_5 = {17'h0, inc_addr_1[14:0] & wrapMask_1}; // @[Fragmenter.scala:108:29, :112:33] wire [31:0] _mux_addr_T_6 = ~irr_1_bits_addr; // @[Decoupled.scala:401:19] wire [31:0] _mux_addr_T_7 = {_mux_addr_T_6[31:15], _mux_addr_T_6[14:0] | wrapMask_1}; // @[Fragmenter.scala:112:{49,62}] wire [31:0] _mux_addr_T_8 = ~_mux_addr_T_7; // @[Fragmenter.scala:112:{47,62}] wire [31:0] _mux_addr_T_9 = _mux_addr_T_5 | _mux_addr_T_8; // @[Fragmenter.scala:112:{33,45,47}] assign mux_addr_1 = fixed_1 ? irr_1_bits_addr : irr_1_bits_burst == 2'h2 ? _mux_addr_T_9 : inc_addr_1; // @[Decoupled.scala:401:19] assign aw_last = beats1_1 == len_1; // @[Fragmenter.scala:72:23, :105:25, :118:27] assign nodeOut_aw_bits_echo_real_last = aw_last; // @[Fragmenter.scala:118:27] assign _irr_ready_T_1 = in_aw_ready & aw_last; // @[Fragmenter.scala:66:23, :118:27, :119:30] assign irr_1_ready = _irr_ready_T_1; // @[Decoupled.scala:401:19] wire [31:0] _out_bits_addr_T_6 = ~addr_1; // @[Fragmenter.scala:73:23, :130:28] wire [9:0] _out_bits_addr_T_7 = 10'h7 << irr_1_bits_size; // @[Decoupled.scala:401:19] wire [2:0] _out_bits_addr_T_8 = _out_bits_addr_T_7[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _out_bits_addr_T_9 = ~_out_bits_addr_T_8; // @[package.scala:243:{46,76}] wire [31:0] _out_bits_addr_T_10 = {_out_bits_addr_T_6[31:3], _out_bits_addr_T_6[2:0] | _out_bits_addr_T_9}; // @[package.scala:243:46] assign _out_bits_addr_T_11 = ~_out_bits_addr_T_10; // @[Fragmenter.scala:130:{26,34}] assign in_aw_bits_addr = _out_bits_addr_T_11; // @[Fragmenter.scala:66:23, :130:26] wire _busy_T_1 = ~aw_last; // @[Fragmenter.scala:118:27, :133:19] wire [9:0] _r_len_T_2 = {2'h0, len_1} - {1'h0, w_beats}; // @[package.scala:241:47] wire [8:0] _r_len_T_3 = _r_len_T_2[8:0]; // @[Fragmenter.scala:135:25] wire _in_w_ready_T_2; // @[Fragmenter.scala:186:33] assign nodeOut_w_bits_data = in_w_bits_data; // @[Decoupled.scala:401:19] assign nodeOut_w_bits_strb = in_w_bits_strb; // @[Decoupled.scala:401:19] wire in_w_bits_last; // @[Decoupled.scala:401:19] wire in_w_ready; // @[Decoupled.scala:401:19] wire in_w_valid; // @[Decoupled.scala:401:19] reg wbeats_latched; // @[Fragmenter.scala:160:35] wire w_idle; // @[Fragmenter.scala:177:30] wire wbeats_ready; // @[Fragmenter.scala:161:30] wire _wbeats_valid_T_1; // @[Fragmenter.scala:169:35] wire wbeats_valid; // @[Fragmenter.scala:162:30] wire _GEN = wbeats_ready | wbeats_latched; // @[Fragmenter.scala:160:35, :161:30, :167:52] wire _nodeOut_aw_valid_T; // @[Fragmenter.scala:167:52] assign _nodeOut_aw_valid_T = _GEN; // @[Fragmenter.scala:167:52] wire _in_aw_ready_T; // @[Fragmenter.scala:168:52] assign _in_aw_ready_T = _GEN; // @[Fragmenter.scala:167:52, :168:52] assign _nodeOut_aw_valid_T_1 = in_aw_valid & _nodeOut_aw_valid_T; // @[Fragmenter.scala:66:23, :167:{35,52}] assign nodeOut_aw_valid = _nodeOut_aw_valid_T_1; // @[Fragmenter.scala:167:35] assign _in_aw_ready_T_1 = nodeOut_aw_ready & _in_aw_ready_T; // @[Fragmenter.scala:168:{35,52}] assign in_aw_ready = _in_aw_ready_T_1; // @[Fragmenter.scala:66:23, :168:35] wire _wbeats_valid_T = ~wbeats_latched; // @[Fragmenter.scala:160:35, :169:38] assign _wbeats_valid_T_1 = in_aw_valid & _wbeats_valid_T; // @[Fragmenter.scala:66:23, :169:{35,38}] assign wbeats_valid = _wbeats_valid_T_1; // @[Fragmenter.scala:162:30, :169:35] reg [8:0] w_counter; // @[Fragmenter.scala:176:30] assign w_idle = w_counter == 9'h0; // @[Fragmenter.scala:176:30, :177:30] assign wbeats_ready = w_idle; // @[Fragmenter.scala:161:30, :177:30] wire [8:0] _w_todo_T = wbeats_valid ? w_beats : 9'h0; // @[package.scala:241:47] wire [8:0] w_todo = w_idle ? _w_todo_T : w_counter; // @[Fragmenter.scala:176:30, :177:30, :178:{23,35}] assign w_last = w_todo == 9'h1; // @[Fragmenter.scala:178:23, :179:27] assign nodeOut_w_bits_last = w_last; // @[Fragmenter.scala:179:27] wire _w_counter_T = nodeOut_w_ready & nodeOut_w_valid; // @[Decoupled.scala:51:35] wire [9:0] _w_counter_T_1 = {1'h0, w_todo} - {9'h0, _w_counter_T}; // @[Decoupled.scala:51:35] wire [8:0] _w_counter_T_2 = _w_counter_T_1[8:0]; // @[Fragmenter.scala:180:27] wire _nodeOut_w_valid_T = ~wbeats_ready; // @[Fragmenter.scala:161:30, :185:37] wire _nodeOut_w_valid_T_1 = _nodeOut_w_valid_T | wbeats_valid; // @[Fragmenter.scala:162:30, :185:{37,51}] assign _nodeOut_w_valid_T_2 = in_w_valid & _nodeOut_w_valid_T_1; // @[Decoupled.scala:401:19] assign nodeOut_w_valid = _nodeOut_w_valid_T_2; // @[Fragmenter.scala:185:33] wire _in_w_ready_T = ~wbeats_ready; // @[Fragmenter.scala:161:30, :185:37, :186:37] wire _in_w_ready_T_1 = _in_w_ready_T | wbeats_valid; // @[Fragmenter.scala:162:30, :186:{37,51}] assign _in_w_ready_T_2 = nodeOut_w_ready & _in_w_ready_T_1; // @[Fragmenter.scala:186:{33,51}] assign in_w_ready = _in_w_ready_T_2; // @[Decoupled.scala:401:19]
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d64s1k1z4u_2 : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_55 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue2_TLBundleA_a32d64s1k1z4u_1 connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue2_TLBundleD_a32d64s1k1z4u_1 connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_10.bits.sink, UInt<1>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0)
module TLBuffer_a32d64s1k1z4u_2( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_a_bits_source = 1'h0; // @[Decoupled.scala:362:21] wire auto_in_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_bits_source = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire [2:0] auto_in_a_bits_param = 3'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_a_bits_param = 3'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] TLMonitor_55 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a32d64s1k1z4u_1 nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s1k1z4u_1 nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLFragmenter_UART : input clock : Clock input reset : Reset output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonIn.d.bits.corrupt invalidate anonIn.d.bits.data invalidate anonIn.d.bits.denied invalidate anonIn.d.bits.sink invalidate anonIn.d.bits.source invalidate anonIn.d.bits.size invalidate anonIn.d.bits.param invalidate anonIn.d.bits.opcode invalidate anonIn.d.valid invalidate anonIn.d.ready invalidate anonIn.a.bits.corrupt invalidate anonIn.a.bits.data invalidate anonIn.a.bits.mask invalidate anonIn.a.bits.address invalidate anonIn.a.bits.source invalidate anonIn.a.bits.size invalidate anonIn.a.bits.param invalidate anonIn.a.bits.opcode invalidate anonIn.a.valid invalidate anonIn.a.ready inst monitor of TLMonitor_7 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt connect monitor.io.in.d.bits.data, anonIn.d.bits.data connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink connect monitor.io.in.d.bits.source, anonIn.d.bits.source connect monitor.io.in.d.bits.size, anonIn.d.bits.size connect monitor.io.in.d.bits.param, anonIn.d.bits.param connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode connect monitor.io.in.d.valid, anonIn.d.valid connect monitor.io.in.d.ready, anonIn.d.ready connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt connect monitor.io.in.a.bits.data, anonIn.a.bits.data connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask connect monitor.io.in.a.bits.address, anonIn.a.bits.address connect monitor.io.in.a.bits.source, anonIn.a.bits.source connect monitor.io.in.a.bits.size, anonIn.a.bits.size connect monitor.io.in.a.bits.param, anonIn.a.bits.param connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode connect monitor.io.in.a.valid, anonIn.a.valid connect monitor.io.in.a.ready, anonIn.a.ready wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonOut.d.bits.corrupt invalidate anonOut.d.bits.data invalidate anonOut.d.bits.denied invalidate anonOut.d.bits.sink invalidate anonOut.d.bits.source invalidate anonOut.d.bits.size invalidate anonOut.d.bits.param invalidate anonOut.d.bits.opcode invalidate anonOut.d.valid invalidate anonOut.d.ready invalidate anonOut.a.bits.corrupt invalidate anonOut.a.bits.data invalidate anonOut.a.bits.mask invalidate anonOut.a.bits.address invalidate anonOut.a.bits.source invalidate anonOut.a.bits.size invalidate anonOut.a.bits.param invalidate anonOut.a.bits.opcode invalidate anonOut.a.valid invalidate anonOut.a.ready connect auto.anon_out, anonOut connect anonIn, auto.anon_in regreset acknum : UInt<3>, clock, reset, UInt<3>(0h0) reg dOrig : UInt, clock regreset dToggle : UInt<1>, clock, reset, UInt<1>(0h0) node dFragnum = bits(anonOut.d.bits.source, 2, 0) node dFirst = eq(acknum, UInt<1>(0h0)) node dLast = eq(dFragnum, UInt<1>(0h0)) node dsizeOH_shiftAmount = bits(anonOut.d.bits.size, 1, 0) node _dsizeOH_T = dshl(UInt<1>(0h1), dsizeOH_shiftAmount) node dsizeOH = bits(_dsizeOH_T, 3, 0) node _dsizeOH1_T = dshl(UInt<3>(0h7), anonOut.d.bits.size) node _dsizeOH1_T_1 = bits(_dsizeOH1_T, 2, 0) node dsizeOH1 = not(_dsizeOH1_T_1) node dHasData = bits(anonOut.d.bits.opcode, 0, 0) node acknum_fragment = shl(dFragnum, 0) node acknum_size = shr(dsizeOH1, 3) node _T = eq(anonOut.d.valid, UInt<1>(0h0)) node _T_1 = and(acknum_fragment, acknum_size) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = or(_T, _T_2) node _T_4 = asUInt(reset) node _T_5 = eq(_T_4, UInt<1>(0h0)) when _T_5 : node _T_6 = eq(_T_3, UInt<1>(0h0)) when _T_6 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:214 assert (!out.d.valid || (acknum_fragment & acknum_size) === 0.U)\n") : printf assert(clock, _T_3, UInt<1>(0h1), "") : assert node _dFirst_acknum_T = mux(dHasData, acknum_size, UInt<1>(0h0)) node dFirst_acknum = or(acknum_fragment, _dFirst_acknum_T) node _ack_decrement_T = shr(dsizeOH, 3) node ack_decrement = mux(dHasData, UInt<1>(0h1), _ack_decrement_T) node _dFirst_size_T = shl(dFragnum, 3) node _dFirst_size_T_1 = or(_dFirst_size_T, dsizeOH1) node _dFirst_size_T_2 = shl(_dFirst_size_T_1, 1) node _dFirst_size_T_3 = or(_dFirst_size_T_2, UInt<1>(0h1)) node _dFirst_size_T_4 = cat(UInt<1>(0h0), _dFirst_size_T_1) node _dFirst_size_T_5 = not(_dFirst_size_T_4) node _dFirst_size_T_6 = and(_dFirst_size_T_3, _dFirst_size_T_5) node dFirst_size_hi = bits(_dFirst_size_T_6, 6, 4) node dFirst_size_lo = bits(_dFirst_size_T_6, 3, 0) node _dFirst_size_T_7 = orr(dFirst_size_hi) node _dFirst_size_T_8 = or(dFirst_size_hi, dFirst_size_lo) node dFirst_size_hi_1 = bits(_dFirst_size_T_8, 3, 2) node dFirst_size_lo_1 = bits(_dFirst_size_T_8, 1, 0) node _dFirst_size_T_9 = orr(dFirst_size_hi_1) node _dFirst_size_T_10 = or(dFirst_size_hi_1, dFirst_size_lo_1) node _dFirst_size_T_11 = bits(_dFirst_size_T_10, 1, 1) node _dFirst_size_T_12 = cat(_dFirst_size_T_9, _dFirst_size_T_11) node dFirst_size = cat(_dFirst_size_T_7, _dFirst_size_T_12) node _T_7 = and(anonOut.d.ready, anonOut.d.valid) when _T_7 : node _acknum_T = sub(acknum, ack_decrement) node _acknum_T_1 = tail(_acknum_T, 1) node _acknum_T_2 = mux(dFirst, dFirst_acknum, _acknum_T_1) connect acknum, _acknum_T_2 when dFirst : connect dOrig, dFirst_size node _dToggle_T = bits(anonOut.d.bits.source, 3, 3) connect dToggle, _dToggle_T node _drop_T = eq(dHasData, UInt<1>(0h0)) node _drop_T_1 = mux(UInt<1>(0h0), dFirst, dLast) node _drop_T_2 = eq(_drop_T_1, UInt<1>(0h0)) node drop = and(_drop_T, _drop_T_2) node _anonOut_d_ready_T = or(anonIn.d.ready, drop) connect anonOut.d.ready, _anonOut_d_ready_T node _anonIn_d_valid_T = eq(drop, UInt<1>(0h0)) node _anonIn_d_valid_T_1 = and(anonOut.d.valid, _anonIn_d_valid_T) connect anonIn.d.valid, _anonIn_d_valid_T_1 connect anonIn.d.bits.corrupt, anonOut.d.bits.corrupt connect anonIn.d.bits.data, anonOut.d.bits.data connect anonIn.d.bits.denied, anonOut.d.bits.denied connect anonIn.d.bits.sink, anonOut.d.bits.sink connect anonIn.d.bits.source, anonOut.d.bits.source connect anonIn.d.bits.size, anonOut.d.bits.size connect anonIn.d.bits.param, anonOut.d.bits.param connect anonIn.d.bits.opcode, anonOut.d.bits.opcode node _anonIn_d_bits_source_T = shr(anonOut.d.bits.source, 4) connect anonIn.d.bits.source, _anonIn_d_bits_source_T node _anonIn_d_bits_size_T = mux(dFirst, dFirst_size, dOrig) connect anonIn.d.bits.size, _anonIn_d_bits_size_T inst repeater of Repeater_TLBundleA_a29d64s7k1z3u connect repeater.clock, clock connect repeater.reset, reset connect repeater.io.enq, anonIn.a node _find_T = xor(repeater.io.deq.bits.address, UInt<1>(0h0)) node _find_T_1 = cvt(_find_T) node _find_T_2 = and(_find_T_1, asSInt(UInt<1>(0h0))) node _find_T_3 = asSInt(_find_T_2) node _find_T_4 = eq(_find_T_3, asSInt(UInt<1>(0h0))) wire find : UInt<1>[1] connect find[0], _find_T_4 node _limit_T = eq(UInt<1>(0h0), repeater.io.deq.bits.opcode) node _limit_T_1 = mux(_limit_T, UInt<2>(0h3), UInt<2>(0h3)) node _limit_T_2 = eq(UInt<1>(0h1), repeater.io.deq.bits.opcode) node _limit_T_3 = mux(_limit_T_2, UInt<2>(0h3), _limit_T_1) node _limit_T_4 = eq(UInt<2>(0h2), repeater.io.deq.bits.opcode) node _limit_T_5 = mux(_limit_T_4, UInt<2>(0h3), _limit_T_3) node _limit_T_6 = eq(UInt<2>(0h3), repeater.io.deq.bits.opcode) node _limit_T_7 = mux(_limit_T_6, UInt<2>(0h3), _limit_T_5) node _limit_T_8 = eq(UInt<3>(0h4), repeater.io.deq.bits.opcode) node _limit_T_9 = mux(_limit_T_8, UInt<2>(0h3), _limit_T_7) node _limit_T_10 = eq(UInt<3>(0h5), repeater.io.deq.bits.opcode) node limit = mux(_limit_T_10, UInt<2>(0h3), _limit_T_9) node _aFrag_T = gt(repeater.io.deq.bits.size, limit) node aFrag = mux(_aFrag_T, limit, repeater.io.deq.bits.size) node _aOrigOH1_T = dshl(UInt<6>(0h3f), repeater.io.deq.bits.size) node _aOrigOH1_T_1 = bits(_aOrigOH1_T, 5, 0) node aOrigOH1 = not(_aOrigOH1_T_1) node _aFragOH1_T = dshl(UInt<3>(0h7), aFrag) node _aFragOH1_T_1 = bits(_aFragOH1_T, 2, 0) node aFragOH1 = not(_aFragOH1_T_1) node _aHasData_opdata_T = bits(repeater.io.deq.bits.opcode, 2, 2) node aHasData = eq(_aHasData_opdata_T, UInt<1>(0h0)) node aMask = mux(aHasData, UInt<1>(0h0), aFragOH1) regreset gennum : UInt<3>, clock, reset, UInt<3>(0h0) node aFirst = eq(gennum, UInt<1>(0h0)) node _old_gennum1_T = shr(aOrigOH1, 3) node _old_gennum1_T_1 = sub(gennum, UInt<1>(0h1)) node _old_gennum1_T_2 = tail(_old_gennum1_T_1, 1) node old_gennum1 = mux(aFirst, _old_gennum1_T, _old_gennum1_T_2) node _new_gennum_T = not(old_gennum1) node _new_gennum_T_1 = shr(aMask, 3) node _new_gennum_T_2 = or(_new_gennum_T, _new_gennum_T_1) node new_gennum = not(_new_gennum_T_2) node _aFragnum_T = shr(old_gennum1, 0) node _aFragnum_T_1 = not(_aFragnum_T) node _aFragnum_T_2 = shr(aFragOH1, 3) node _aFragnum_T_3 = or(_aFragnum_T_1, _aFragnum_T_2) node aFragnum = not(_aFragnum_T_3) node aLast = eq(aFragnum, UInt<1>(0h0)) reg aToggle_r : UInt<1>, clock when aFirst : connect aToggle_r, dToggle node _aToggle_T = mux(aFirst, dToggle, aToggle_r) node aToggle = eq(_aToggle_T, UInt<1>(0h0)) node _T_8 = and(anonOut.a.ready, anonOut.a.valid) when _T_8 : connect gennum, new_gennum node _repeater_io_repeat_T = eq(aHasData, UInt<1>(0h0)) node _repeater_io_repeat_T_1 = neq(aFragnum, UInt<1>(0h0)) node _repeater_io_repeat_T_2 = and(_repeater_io_repeat_T, _repeater_io_repeat_T_1) connect repeater.io.repeat, _repeater_io_repeat_T_2 connect anonOut.a.bits, repeater.io.deq.bits connect anonOut.a.valid, repeater.io.deq.valid connect repeater.io.deq.ready, anonOut.a.ready node _anonOut_a_bits_address_T = shl(old_gennum1, 3) node _anonOut_a_bits_address_T_1 = not(aOrigOH1) node _anonOut_a_bits_address_T_2 = or(_anonOut_a_bits_address_T, _anonOut_a_bits_address_T_1) node _anonOut_a_bits_address_T_3 = or(_anonOut_a_bits_address_T_2, aFragOH1) node _anonOut_a_bits_address_T_4 = or(_anonOut_a_bits_address_T_3, UInt<3>(0h7)) node _anonOut_a_bits_address_T_5 = not(_anonOut_a_bits_address_T_4) node _anonOut_a_bits_address_T_6 = or(repeater.io.deq.bits.address, _anonOut_a_bits_address_T_5) connect anonOut.a.bits.address, _anonOut_a_bits_address_T_6 node anonOut_a_bits_source_hi = cat(repeater.io.deq.bits.source, aToggle) node _anonOut_a_bits_source_T = cat(anonOut_a_bits_source_hi, aFragnum) connect anonOut.a.bits.source, _anonOut_a_bits_source_T connect anonOut.a.bits.size, aFrag node _T_9 = eq(repeater.io.full, UInt<1>(0h0)) node _T_10 = eq(aHasData, UInt<1>(0h0)) node _T_11 = or(_T_9, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:321 assert (!repeater.io.full || !aHasData)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 connect anonOut.a.bits.data, anonIn.a.bits.data node _T_15 = eq(repeater.io.full, UInt<1>(0h0)) node _T_16 = eq(repeater.io.deq.bits.mask, UInt<8>(0hff)) node _T_17 = or(_T_15, _T_16) node _T_18 = asUInt(reset) node _T_19 = eq(_T_18, UInt<1>(0h0)) when _T_19 : node _T_20 = eq(_T_17, UInt<1>(0h0)) when _T_20 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:324 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n") : printf_2 assert(clock, _T_17, UInt<1>(0h1), "") : assert_2 node _anonOut_a_bits_mask_T = mux(repeater.io.full, UInt<8>(0hff), anonIn.a.bits.mask) connect anonOut.a.bits.mask, _anonOut_a_bits_mask_T wire anonOut_a_bits_user_out : { } wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<29>(0h0) connect _WIRE.bits.source, UInt<7>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<29>(0h0) connect _WIRE_2.bits.source, UInt<7>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<11>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<29>(0h0) connect _WIRE_8.bits.source, UInt<11>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_10.bits.sink, UInt<1>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0)
module TLFragmenter_UART( // @[Fragmenter.scala:92:9] input clock, // @[Fragmenter.scala:92:9] input reset, // @[Fragmenter.scala:92:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire _repeater_io_full; // @[Fragmenter.scala:274:30] wire _repeater_io_enq_ready; // @[Fragmenter.scala:274:30] wire _repeater_io_deq_valid; // @[Fragmenter.scala:274:30] wire [2:0] _repeater_io_deq_bits_opcode; // @[Fragmenter.scala:274:30] wire [2:0] _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30] wire [6:0] _repeater_io_deq_bits_source; // @[Fragmenter.scala:274:30] wire [28:0] _repeater_io_deq_bits_address; // @[Fragmenter.scala:274:30] wire [7:0] _repeater_io_deq_bits_mask; // @[Fragmenter.scala:274:30] reg [2:0] acknum; // @[Fragmenter.scala:201:29] reg [2:0] dOrig; // @[Fragmenter.scala:202:24] reg dToggle; // @[Fragmenter.scala:203:30] wire dFirst = acknum == 3'h0; // @[Fragmenter.scala:201:29, :205:29] wire [5:0] _dsizeOH1_T = 6'h7 << auto_anon_out_d_bits_size; // @[package.scala:243:71] wire [2:0] _GEN = ~(auto_anon_out_d_bits_source[2:0]); // @[package.scala:241:49] wire [2:0] dFirst_size_hi = auto_anon_out_d_bits_source[2:0] & {1'h1, _GEN[2:1]}; // @[OneHot.scala:30:18] wire [2:0] _dFirst_size_T_8 = {1'h0, dFirst_size_hi[2:1]} | ~(_dsizeOH1_T[2:0]) & {_GEN[0], _dsizeOH1_T[2:1]}; // @[OneHot.scala:30:18, :31:18, :32:28] wire [2:0] dFirst_size = {|dFirst_size_hi, |(_dFirst_size_T_8[2:1]), _dFirst_size_T_8[2] | _dFirst_size_T_8[0]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire drop = ~(auto_anon_out_d_bits_opcode[0]) & (|(auto_anon_out_d_bits_source[2:0])); // @[Fragmenter.scala:204:41, :206:30, :234:{20,30}] wire anonOut_d_ready = auto_anon_in_d_ready | drop; // @[Fragmenter.scala:234:30, :235:35] wire anonIn_d_valid = auto_anon_out_d_valid & ~drop; // @[Fragmenter.scala:234:30, :236:{36,39}] wire [2:0] anonIn_d_bits_size = dFirst ? dFirst_size : dOrig; // @[OneHot.scala:32:10] wire [12:0] _aOrigOH1_T = 13'h3F << _repeater_io_deq_bits_size; // @[package.scala:243:71] reg [2:0] gennum; // @[Fragmenter.scala:303:29] wire aFirst = gennum == 3'h0; // @[Fragmenter.scala:303:29, :304:29] wire [2:0] aFragnum = aFirst ? ~(_aOrigOH1_T[5:3]) : gennum - 3'h1; // @[package.scala:243:{46,71,76}] reg aToggle_r; // @[Fragmenter.scala:309:54]
Generate the Verilog code corresponding to this FIRRTL code module MulRecFN_15 : output io : { flip a : UInt<33>, flip b : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} inst mulRawFN of MulRawFN_15 node mulRawFN_io_a_exp = bits(io.a, 31, 23) node _mulRawFN_io_a_isZero_T = bits(mulRawFN_io_a_exp, 8, 6) node mulRawFN_io_a_isZero = eq(_mulRawFN_io_a_isZero_T, UInt<1>(0h0)) node _mulRawFN_io_a_isSpecial_T = bits(mulRawFN_io_a_exp, 8, 7) node mulRawFN_io_a_isSpecial = eq(_mulRawFN_io_a_isSpecial_T, UInt<2>(0h3)) wire mulRawFN_io_a_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _mulRawFN_io_a_out_isNaN_T = bits(mulRawFN_io_a_exp, 6, 6) node _mulRawFN_io_a_out_isNaN_T_1 = and(mulRawFN_io_a_isSpecial, _mulRawFN_io_a_out_isNaN_T) connect mulRawFN_io_a_out.isNaN, _mulRawFN_io_a_out_isNaN_T_1 node _mulRawFN_io_a_out_isInf_T = bits(mulRawFN_io_a_exp, 6, 6) node _mulRawFN_io_a_out_isInf_T_1 = eq(_mulRawFN_io_a_out_isInf_T, UInt<1>(0h0)) node _mulRawFN_io_a_out_isInf_T_2 = and(mulRawFN_io_a_isSpecial, _mulRawFN_io_a_out_isInf_T_1) connect mulRawFN_io_a_out.isInf, _mulRawFN_io_a_out_isInf_T_2 connect mulRawFN_io_a_out.isZero, mulRawFN_io_a_isZero node _mulRawFN_io_a_out_sign_T = bits(io.a, 32, 32) connect mulRawFN_io_a_out.sign, _mulRawFN_io_a_out_sign_T node _mulRawFN_io_a_out_sExp_T = cvt(mulRawFN_io_a_exp) connect mulRawFN_io_a_out.sExp, _mulRawFN_io_a_out_sExp_T node _mulRawFN_io_a_out_sig_T = eq(mulRawFN_io_a_isZero, UInt<1>(0h0)) node _mulRawFN_io_a_out_sig_T_1 = cat(UInt<1>(0h0), _mulRawFN_io_a_out_sig_T) node _mulRawFN_io_a_out_sig_T_2 = bits(io.a, 22, 0) node _mulRawFN_io_a_out_sig_T_3 = cat(_mulRawFN_io_a_out_sig_T_1, _mulRawFN_io_a_out_sig_T_2) connect mulRawFN_io_a_out.sig, _mulRawFN_io_a_out_sig_T_3 connect mulRawFN.io.a.sig, mulRawFN_io_a_out.sig connect mulRawFN.io.a.sExp, mulRawFN_io_a_out.sExp connect mulRawFN.io.a.sign, mulRawFN_io_a_out.sign connect mulRawFN.io.a.isZero, mulRawFN_io_a_out.isZero connect mulRawFN.io.a.isInf, mulRawFN_io_a_out.isInf connect mulRawFN.io.a.isNaN, mulRawFN_io_a_out.isNaN node mulRawFN_io_b_exp = bits(io.b, 31, 23) node _mulRawFN_io_b_isZero_T = bits(mulRawFN_io_b_exp, 8, 6) node mulRawFN_io_b_isZero = eq(_mulRawFN_io_b_isZero_T, UInt<1>(0h0)) node _mulRawFN_io_b_isSpecial_T = bits(mulRawFN_io_b_exp, 8, 7) node mulRawFN_io_b_isSpecial = eq(_mulRawFN_io_b_isSpecial_T, UInt<2>(0h3)) wire mulRawFN_io_b_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _mulRawFN_io_b_out_isNaN_T = bits(mulRawFN_io_b_exp, 6, 6) node _mulRawFN_io_b_out_isNaN_T_1 = and(mulRawFN_io_b_isSpecial, _mulRawFN_io_b_out_isNaN_T) connect mulRawFN_io_b_out.isNaN, _mulRawFN_io_b_out_isNaN_T_1 node _mulRawFN_io_b_out_isInf_T = bits(mulRawFN_io_b_exp, 6, 6) node _mulRawFN_io_b_out_isInf_T_1 = eq(_mulRawFN_io_b_out_isInf_T, UInt<1>(0h0)) node _mulRawFN_io_b_out_isInf_T_2 = and(mulRawFN_io_b_isSpecial, _mulRawFN_io_b_out_isInf_T_1) connect mulRawFN_io_b_out.isInf, _mulRawFN_io_b_out_isInf_T_2 connect mulRawFN_io_b_out.isZero, mulRawFN_io_b_isZero node _mulRawFN_io_b_out_sign_T = bits(io.b, 32, 32) connect mulRawFN_io_b_out.sign, _mulRawFN_io_b_out_sign_T node _mulRawFN_io_b_out_sExp_T = cvt(mulRawFN_io_b_exp) connect mulRawFN_io_b_out.sExp, _mulRawFN_io_b_out_sExp_T node _mulRawFN_io_b_out_sig_T = eq(mulRawFN_io_b_isZero, UInt<1>(0h0)) node _mulRawFN_io_b_out_sig_T_1 = cat(UInt<1>(0h0), _mulRawFN_io_b_out_sig_T) node _mulRawFN_io_b_out_sig_T_2 = bits(io.b, 22, 0) node _mulRawFN_io_b_out_sig_T_3 = cat(_mulRawFN_io_b_out_sig_T_1, _mulRawFN_io_b_out_sig_T_2) connect mulRawFN_io_b_out.sig, _mulRawFN_io_b_out_sig_T_3 connect mulRawFN.io.b.sig, mulRawFN_io_b_out.sig connect mulRawFN.io.b.sExp, mulRawFN_io_b_out.sExp connect mulRawFN.io.b.sign, mulRawFN_io_b_out.sign connect mulRawFN.io.b.isZero, mulRawFN_io_b_out.isZero connect mulRawFN.io.b.isInf, mulRawFN_io_b_out.isInf connect mulRawFN.io.b.isNaN, mulRawFN_io_b_out.isNaN inst roundRawFNToRecFN of RoundRawFNToRecFN_e8_s24_45 connect roundRawFNToRecFN.io.invalidExc, mulRawFN.io.invalidExc connect roundRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect roundRawFNToRecFN.io.in.sig, mulRawFN.io.rawOut.sig connect roundRawFNToRecFN.io.in.sExp, mulRawFN.io.rawOut.sExp connect roundRawFNToRecFN.io.in.sign, mulRawFN.io.rawOut.sign connect roundRawFNToRecFN.io.in.isZero, mulRawFN.io.rawOut.isZero connect roundRawFNToRecFN.io.in.isInf, mulRawFN.io.rawOut.isInf connect roundRawFNToRecFN.io.in.isNaN, mulRawFN.io.rawOut.isNaN connect roundRawFNToRecFN.io.roundingMode, io.roundingMode connect roundRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundRawFNToRecFN.io.out connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags
module MulRecFN_15( // @[MulRecFN.scala:100:7] input [32:0] io_a, // @[MulRecFN.scala:102:16] input [32:0] io_b, // @[MulRecFN.scala:102:16] output [32:0] io_out // @[MulRecFN.scala:102:16] ); wire _mulRawFN_io_invalidExc; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_isNaN; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_isInf; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_isZero; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_sign; // @[MulRecFN.scala:113:26] wire [9:0] _mulRawFN_io_rawOut_sExp; // @[MulRecFN.scala:113:26] wire [26:0] _mulRawFN_io_rawOut_sig; // @[MulRecFN.scala:113:26] wire [32:0] io_a_0 = io_a; // @[MulRecFN.scala:100:7] wire [32:0] io_b_0 = io_b; // @[MulRecFN.scala:100:7] wire io_detectTininess = 1'h1; // @[MulRecFN.scala:100:7, :102:16, :121:15] wire [2:0] io_roundingMode = 3'h0; // @[MulRecFN.scala:100:7, :102:16, :121:15] wire [32:0] io_out_0; // @[MulRecFN.scala:100:7] wire [4:0] io_exceptionFlags; // @[MulRecFN.scala:100:7] wire [8:0] mulRawFN_io_a_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _mulRawFN_io_a_isZero_T = mulRawFN_io_a_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire mulRawFN_io_a_isZero = _mulRawFN_io_a_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire mulRawFN_io_a_out_isZero = mulRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _mulRawFN_io_a_isSpecial_T = mulRawFN_io_a_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire mulRawFN_io_a_isSpecial = &_mulRawFN_io_a_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _mulRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _mulRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _mulRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _mulRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _mulRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire mulRawFN_io_a_out_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_a_out_isInf; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_a_out_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] mulRawFN_io_a_out_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] mulRawFN_io_a_out_sig; // @[rawFloatFromRecFN.scala:55:23] wire _mulRawFN_io_a_out_isNaN_T = mulRawFN_io_a_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _mulRawFN_io_a_out_isInf_T = mulRawFN_io_a_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _mulRawFN_io_a_out_isNaN_T_1 = mulRawFN_io_a_isSpecial & _mulRawFN_io_a_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign mulRawFN_io_a_out_isNaN = _mulRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _mulRawFN_io_a_out_isInf_T_1 = ~_mulRawFN_io_a_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _mulRawFN_io_a_out_isInf_T_2 = mulRawFN_io_a_isSpecial & _mulRawFN_io_a_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign mulRawFN_io_a_out_isInf = _mulRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _mulRawFN_io_a_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign mulRawFN_io_a_out_sign = _mulRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _mulRawFN_io_a_out_sExp_T = {1'h0, mulRawFN_io_a_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign mulRawFN_io_a_out_sExp = _mulRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _mulRawFN_io_a_out_sig_T = ~mulRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _mulRawFN_io_a_out_sig_T_1 = {1'h0, _mulRawFN_io_a_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _mulRawFN_io_a_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _mulRawFN_io_a_out_sig_T_3 = {_mulRawFN_io_a_out_sig_T_1, _mulRawFN_io_a_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign mulRawFN_io_a_out_sig = _mulRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] mulRawFN_io_b_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _mulRawFN_io_b_isZero_T = mulRawFN_io_b_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire mulRawFN_io_b_isZero = _mulRawFN_io_b_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire mulRawFN_io_b_out_isZero = mulRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _mulRawFN_io_b_isSpecial_T = mulRawFN_io_b_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire mulRawFN_io_b_isSpecial = &_mulRawFN_io_b_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _mulRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _mulRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _mulRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _mulRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _mulRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire mulRawFN_io_b_out_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_b_out_isInf; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_b_out_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] mulRawFN_io_b_out_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] mulRawFN_io_b_out_sig; // @[rawFloatFromRecFN.scala:55:23] wire _mulRawFN_io_b_out_isNaN_T = mulRawFN_io_b_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _mulRawFN_io_b_out_isInf_T = mulRawFN_io_b_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _mulRawFN_io_b_out_isNaN_T_1 = mulRawFN_io_b_isSpecial & _mulRawFN_io_b_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign mulRawFN_io_b_out_isNaN = _mulRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _mulRawFN_io_b_out_isInf_T_1 = ~_mulRawFN_io_b_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _mulRawFN_io_b_out_isInf_T_2 = mulRawFN_io_b_isSpecial & _mulRawFN_io_b_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign mulRawFN_io_b_out_isInf = _mulRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _mulRawFN_io_b_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign mulRawFN_io_b_out_sign = _mulRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _mulRawFN_io_b_out_sExp_T = {1'h0, mulRawFN_io_b_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign mulRawFN_io_b_out_sExp = _mulRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _mulRawFN_io_b_out_sig_T = ~mulRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _mulRawFN_io_b_out_sig_T_1 = {1'h0, _mulRawFN_io_b_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _mulRawFN_io_b_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _mulRawFN_io_b_out_sig_T_3 = {_mulRawFN_io_b_out_sig_T_1, _mulRawFN_io_b_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign mulRawFN_io_b_out_sig = _mulRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] MulRawFN_15 mulRawFN ( // @[MulRecFN.scala:113:26] .io_a_isNaN (mulRawFN_io_a_out_isNaN), // @[rawFloatFromRecFN.scala:55:23] .io_a_isInf (mulRawFN_io_a_out_isInf), // @[rawFloatFromRecFN.scala:55:23] .io_a_isZero (mulRawFN_io_a_out_isZero), // @[rawFloatFromRecFN.scala:55:23] .io_a_sign (mulRawFN_io_a_out_sign), // @[rawFloatFromRecFN.scala:55:23] .io_a_sExp (mulRawFN_io_a_out_sExp), // @[rawFloatFromRecFN.scala:55:23] .io_a_sig (mulRawFN_io_a_out_sig), // @[rawFloatFromRecFN.scala:55:23] .io_b_isNaN (mulRawFN_io_b_out_isNaN), // @[rawFloatFromRecFN.scala:55:23] .io_b_isInf (mulRawFN_io_b_out_isInf), // @[rawFloatFromRecFN.scala:55:23] .io_b_isZero (mulRawFN_io_b_out_isZero), // @[rawFloatFromRecFN.scala:55:23] .io_b_sign (mulRawFN_io_b_out_sign), // @[rawFloatFromRecFN.scala:55:23] .io_b_sExp (mulRawFN_io_b_out_sExp), // @[rawFloatFromRecFN.scala:55:23] .io_b_sig (mulRawFN_io_b_out_sig), // @[rawFloatFromRecFN.scala:55:23] .io_invalidExc (_mulRawFN_io_invalidExc), .io_rawOut_isNaN (_mulRawFN_io_rawOut_isNaN), .io_rawOut_isInf (_mulRawFN_io_rawOut_isInf), .io_rawOut_isZero (_mulRawFN_io_rawOut_isZero), .io_rawOut_sign (_mulRawFN_io_rawOut_sign), .io_rawOut_sExp (_mulRawFN_io_rawOut_sExp), .io_rawOut_sig (_mulRawFN_io_rawOut_sig) ); // @[MulRecFN.scala:113:26] RoundRawFNToRecFN_e8_s24_45 roundRawFNToRecFN ( // @[MulRecFN.scala:121:15] .io_invalidExc (_mulRawFN_io_invalidExc), // @[MulRecFN.scala:113:26] .io_in_isNaN (_mulRawFN_io_rawOut_isNaN), // @[MulRecFN.scala:113:26] .io_in_isInf (_mulRawFN_io_rawOut_isInf), // @[MulRecFN.scala:113:26] .io_in_isZero (_mulRawFN_io_rawOut_isZero), // @[MulRecFN.scala:113:26] .io_in_sign (_mulRawFN_io_rawOut_sign), // @[MulRecFN.scala:113:26] .io_in_sExp (_mulRawFN_io_rawOut_sExp), // @[MulRecFN.scala:113:26] .io_in_sig (_mulRawFN_io_rawOut_sig), // @[MulRecFN.scala:113:26] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags) ); // @[MulRecFN.scala:121:15] assign io_out = io_out_0; // @[MulRecFN.scala:100:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_58 : input clock : Clock input reset : Reset output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], credit_return : UInt<2>, vc_free : UInt<2>}} wire _in_flight_WIRE : UInt<1>[2] connect _in_flight_WIRE[0], UInt<1>(0h0) connect _in_flight_WIRE[1], UInt<1>(0h0) regreset in_flight : UInt<1>[2], clock, reset, _in_flight_WIRE when io.in.flit[0].valid : when io.in.flit[0].bits.head : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1) node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert when io.in.flit[0].bits.tail : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0) node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T_4 : node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0)) node _T_6 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7)) node _T_7 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_8 = and(_T_6, _T_7) node _T_9 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_10 = and(_T_8, _T_9) node _T_11 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_12 = and(_T_10, _T_11) node _T_13 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7)) node _T_14 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_15 = and(_T_13, _T_14) node _T_16 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_19 = and(_T_17, _T_18) node _T_20 = or(_T_12, _T_19) node _T_21 = or(_T_5, _T_20) node _T_22 = asUInt(reset) node _T_23 = eq(_T_22, UInt<1>(0h0)) when _T_23 : node _T_24 = eq(_T_21, UInt<1>(0h0)) when _T_24 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1 assert(clock, _T_21, UInt<1>(0h1), "") : assert_1 node _T_25 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1)) node _T_26 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_27 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_28 = and(_T_26, _T_27) node _T_29 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_32 = and(_T_30, _T_31) node _T_33 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_34 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd)) node _T_35 = and(_T_33, _T_34) node _T_36 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_37 = and(_T_35, _T_36) node _T_38 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_39 = and(_T_37, _T_38) node _T_40 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_41 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_42 = and(_T_40, _T_41) node _T_43 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_44 = and(_T_42, _T_43) node _T_45 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_46 = and(_T_44, _T_45) node _T_47 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_48 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h1)) node _T_49 = and(_T_47, _T_48) node _T_50 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_51 = and(_T_49, _T_50) node _T_52 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_53 = and(_T_51, _T_52) node _T_54 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_55 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_58 = and(_T_56, _T_57) node _T_59 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_60 = and(_T_58, _T_59) node _T_61 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_62 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_63 = and(_T_61, _T_62) node _T_64 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_65 = and(_T_63, _T_64) node _T_66 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_67 = and(_T_65, _T_66) node _T_68 = or(_T_32, _T_39) node _T_69 = or(_T_68, _T_46) node _T_70 = or(_T_69, _T_53) node _T_71 = or(_T_70, _T_60) node _T_72 = or(_T_71, _T_67) node _T_73 = or(_T_25, _T_72) node _T_74 = asUInt(reset) node _T_75 = eq(_T_74, UInt<1>(0h0)) when _T_75 : node _T_76 = eq(_T_73, UInt<1>(0h0)) when _T_76 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2 assert(clock, _T_73, UInt<1>(0h1), "") : assert_2
module NoCMonitor_58( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26]
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_175 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_192 connect io_out_source_valid.clock, clock connect io_out_source_valid.reset, reset connect io_out_source_valid.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid.io.q connect io.out, _io_out_WIRE
module AsyncValidSync_175( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_192 io_out_source_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PMAChecker_22 : input clock : Clock input reset : Reset output io : { flip paddr : UInt, resp : { cacheable : UInt<1>, r : UInt<1>, w : UInt<1>, pp : UInt<1>, al : UInt<1>, aa : UInt<1>, x : UInt<1>, eff : UInt<1>}} node _legal_address_T = xor(io.paddr, UInt<1>(0h0)) node _legal_address_T_1 = cvt(_legal_address_T) node _legal_address_T_2 = and(_legal_address_T_1, asSInt(UInt<13>(0h1000))) node _legal_address_T_3 = asSInt(_legal_address_T_2) node _legal_address_T_4 = eq(_legal_address_T_3, asSInt(UInt<1>(0h0))) node _legal_address_T_5 = xor(io.paddr, UInt<13>(0h1000)) node _legal_address_T_6 = cvt(_legal_address_T_5) node _legal_address_T_7 = and(_legal_address_T_6, asSInt(UInt<13>(0h1000))) node _legal_address_T_8 = asSInt(_legal_address_T_7) node _legal_address_T_9 = eq(_legal_address_T_8, asSInt(UInt<1>(0h0))) node _legal_address_T_10 = xor(io.paddr, UInt<14>(0h3000)) node _legal_address_T_11 = cvt(_legal_address_T_10) node _legal_address_T_12 = and(_legal_address_T_11, asSInt(UInt<13>(0h1000))) node _legal_address_T_13 = asSInt(_legal_address_T_12) node _legal_address_T_14 = eq(_legal_address_T_13, asSInt(UInt<1>(0h0))) node _legal_address_T_15 = xor(io.paddr, UInt<17>(0h10000)) node _legal_address_T_16 = cvt(_legal_address_T_15) node _legal_address_T_17 = and(_legal_address_T_16, asSInt(UInt<17>(0h10000))) node _legal_address_T_18 = asSInt(_legal_address_T_17) node _legal_address_T_19 = eq(_legal_address_T_18, asSInt(UInt<1>(0h0))) node _legal_address_T_20 = xor(io.paddr, UInt<21>(0h100000)) node _legal_address_T_21 = cvt(_legal_address_T_20) node _legal_address_T_22 = and(_legal_address_T_21, asSInt(UInt<13>(0h1000))) node _legal_address_T_23 = asSInt(_legal_address_T_22) node _legal_address_T_24 = eq(_legal_address_T_23, asSInt(UInt<1>(0h0))) node _legal_address_T_25 = xor(io.paddr, UInt<21>(0h110000)) node _legal_address_T_26 = cvt(_legal_address_T_25) node _legal_address_T_27 = and(_legal_address_T_26, asSInt(UInt<13>(0h1000))) node _legal_address_T_28 = asSInt(_legal_address_T_27) node _legal_address_T_29 = eq(_legal_address_T_28, asSInt(UInt<1>(0h0))) node _legal_address_T_30 = xor(io.paddr, UInt<26>(0h2000000)) node _legal_address_T_31 = cvt(_legal_address_T_30) node _legal_address_T_32 = and(_legal_address_T_31, asSInt(UInt<17>(0h10000))) node _legal_address_T_33 = asSInt(_legal_address_T_32) node _legal_address_T_34 = eq(_legal_address_T_33, asSInt(UInt<1>(0h0))) node _legal_address_T_35 = xor(io.paddr, UInt<26>(0h2010000)) node _legal_address_T_36 = cvt(_legal_address_T_35) node _legal_address_T_37 = and(_legal_address_T_36, asSInt(UInt<13>(0h1000))) node _legal_address_T_38 = asSInt(_legal_address_T_37) node _legal_address_T_39 = eq(_legal_address_T_38, asSInt(UInt<1>(0h0))) node _legal_address_T_40 = xor(io.paddr, UInt<28>(0h8000000)) node _legal_address_T_41 = cvt(_legal_address_T_40) node _legal_address_T_42 = and(_legal_address_T_41, asSInt(UInt<17>(0h10000))) node _legal_address_T_43 = asSInt(_legal_address_T_42) node _legal_address_T_44 = eq(_legal_address_T_43, asSInt(UInt<1>(0h0))) node _legal_address_T_45 = xor(io.paddr, UInt<28>(0hc000000)) node _legal_address_T_46 = cvt(_legal_address_T_45) node _legal_address_T_47 = and(_legal_address_T_46, asSInt(UInt<27>(0h4000000))) node _legal_address_T_48 = asSInt(_legal_address_T_47) node _legal_address_T_49 = eq(_legal_address_T_48, asSInt(UInt<1>(0h0))) node _legal_address_T_50 = xor(io.paddr, UInt<29>(0h10020000)) node _legal_address_T_51 = cvt(_legal_address_T_50) node _legal_address_T_52 = and(_legal_address_T_51, asSInt(UInt<13>(0h1000))) node _legal_address_T_53 = asSInt(_legal_address_T_52) node _legal_address_T_54 = eq(_legal_address_T_53, asSInt(UInt<1>(0h0))) node _legal_address_T_55 = xor(io.paddr, UInt<32>(0h80000000)) node _legal_address_T_56 = cvt(_legal_address_T_55) node _legal_address_T_57 = and(_legal_address_T_56, asSInt(UInt<29>(0h10000000))) node _legal_address_T_58 = asSInt(_legal_address_T_57) node _legal_address_T_59 = eq(_legal_address_T_58, asSInt(UInt<1>(0h0))) wire _legal_address_WIRE : UInt<1>[12] connect _legal_address_WIRE[0], _legal_address_T_4 connect _legal_address_WIRE[1], _legal_address_T_9 connect _legal_address_WIRE[2], _legal_address_T_14 connect _legal_address_WIRE[3], _legal_address_T_19 connect _legal_address_WIRE[4], _legal_address_T_24 connect _legal_address_WIRE[5], _legal_address_T_29 connect _legal_address_WIRE[6], _legal_address_T_34 connect _legal_address_WIRE[7], _legal_address_T_39 connect _legal_address_WIRE[8], _legal_address_T_44 connect _legal_address_WIRE[9], _legal_address_T_49 connect _legal_address_WIRE[10], _legal_address_T_54 connect _legal_address_WIRE[11], _legal_address_T_59 node _legal_address_T_60 = or(_legal_address_WIRE[0], _legal_address_WIRE[1]) node _legal_address_T_61 = or(_legal_address_T_60, _legal_address_WIRE[2]) node _legal_address_T_62 = or(_legal_address_T_61, _legal_address_WIRE[3]) node _legal_address_T_63 = or(_legal_address_T_62, _legal_address_WIRE[4]) node _legal_address_T_64 = or(_legal_address_T_63, _legal_address_WIRE[5]) node _legal_address_T_65 = or(_legal_address_T_64, _legal_address_WIRE[6]) node _legal_address_T_66 = or(_legal_address_T_65, _legal_address_WIRE[7]) node _legal_address_T_67 = or(_legal_address_T_66, _legal_address_WIRE[8]) node _legal_address_T_68 = or(_legal_address_T_67, _legal_address_WIRE[9]) node _legal_address_T_69 = or(_legal_address_T_68, _legal_address_WIRE[10]) node legal_address = or(_legal_address_T_69, _legal_address_WIRE[11]) node _io_resp_cacheable_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_cacheable_T_1 = cvt(_io_resp_cacheable_T) node _io_resp_cacheable_T_2 = and(_io_resp_cacheable_T_1, asSInt(UInt<33>(0h8c000000))) node _io_resp_cacheable_T_3 = asSInt(_io_resp_cacheable_T_2) node _io_resp_cacheable_T_4 = eq(_io_resp_cacheable_T_3, asSInt(UInt<1>(0h0))) node _io_resp_cacheable_T_5 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_cacheable_T_6 = cvt(_io_resp_cacheable_T_5) node _io_resp_cacheable_T_7 = and(_io_resp_cacheable_T_6, asSInt(UInt<33>(0h8c011000))) node _io_resp_cacheable_T_8 = asSInt(_io_resp_cacheable_T_7) node _io_resp_cacheable_T_9 = eq(_io_resp_cacheable_T_8, asSInt(UInt<1>(0h0))) node _io_resp_cacheable_T_10 = xor(io.paddr, UInt<28>(0hc000000)) node _io_resp_cacheable_T_11 = cvt(_io_resp_cacheable_T_10) node _io_resp_cacheable_T_12 = and(_io_resp_cacheable_T_11, asSInt(UInt<33>(0h8c000000))) node _io_resp_cacheable_T_13 = asSInt(_io_resp_cacheable_T_12) node _io_resp_cacheable_T_14 = eq(_io_resp_cacheable_T_13, asSInt(UInt<1>(0h0))) node _io_resp_cacheable_T_15 = or(_io_resp_cacheable_T_4, _io_resp_cacheable_T_9) node _io_resp_cacheable_T_16 = or(_io_resp_cacheable_T_15, _io_resp_cacheable_T_14) node _io_resp_cacheable_T_17 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_cacheable_T_18 = cvt(_io_resp_cacheable_T_17) node _io_resp_cacheable_T_19 = and(_io_resp_cacheable_T_18, asSInt(UInt<33>(0h8c010000))) node _io_resp_cacheable_T_20 = asSInt(_io_resp_cacheable_T_19) node _io_resp_cacheable_T_21 = eq(_io_resp_cacheable_T_20, asSInt(UInt<1>(0h0))) node _io_resp_cacheable_T_22 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_cacheable_T_23 = cvt(_io_resp_cacheable_T_22) node _io_resp_cacheable_T_24 = and(_io_resp_cacheable_T_23, asSInt(UInt<33>(0h80000000))) node _io_resp_cacheable_T_25 = asSInt(_io_resp_cacheable_T_24) node _io_resp_cacheable_T_26 = eq(_io_resp_cacheable_T_25, asSInt(UInt<1>(0h0))) node _io_resp_cacheable_T_27 = or(_io_resp_cacheable_T_21, _io_resp_cacheable_T_26) node _io_resp_cacheable_T_28 = mux(_io_resp_cacheable_T_16, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_cacheable_T_29 = mux(_io_resp_cacheable_T_27, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_cacheable_T_30 = or(_io_resp_cacheable_T_28, _io_resp_cacheable_T_29) wire _io_resp_cacheable_WIRE : UInt<1> connect _io_resp_cacheable_WIRE, _io_resp_cacheable_T_30 node _io_resp_cacheable_T_31 = and(legal_address, _io_resp_cacheable_WIRE) connect io.resp.cacheable, _io_resp_cacheable_T_31 node _io_resp_r_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_r_T_1 = cvt(_io_resp_r_T) node _io_resp_r_T_2 = and(_io_resp_r_T_1, asSInt(UInt<1>(0h0))) node _io_resp_r_T_3 = asSInt(_io_resp_r_T_2) node _io_resp_r_T_4 = eq(_io_resp_r_T_3, asSInt(UInt<1>(0h0))) node _io_resp_r_T_5 = and(legal_address, UInt<1>(0h1)) connect io.resp.r, _io_resp_r_T_5 node _io_resp_w_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_w_T_1 = cvt(_io_resp_w_T) node _io_resp_w_T_2 = and(_io_resp_w_T_1, asSInt(UInt<33>(0h98110000))) node _io_resp_w_T_3 = asSInt(_io_resp_w_T_2) node _io_resp_w_T_4 = eq(_io_resp_w_T_3, asSInt(UInt<1>(0h0))) node _io_resp_w_T_5 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_w_T_6 = cvt(_io_resp_w_T_5) node _io_resp_w_T_7 = and(_io_resp_w_T_6, asSInt(UInt<33>(0h9a101000))) node _io_resp_w_T_8 = asSInt(_io_resp_w_T_7) node _io_resp_w_T_9 = eq(_io_resp_w_T_8, asSInt(UInt<1>(0h0))) node _io_resp_w_T_10 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_w_T_11 = cvt(_io_resp_w_T_10) node _io_resp_w_T_12 = and(_io_resp_w_T_11, asSInt(UInt<33>(0h9a111000))) node _io_resp_w_T_13 = asSInt(_io_resp_w_T_12) node _io_resp_w_T_14 = eq(_io_resp_w_T_13, asSInt(UInt<1>(0h0))) node _io_resp_w_T_15 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_w_T_16 = cvt(_io_resp_w_T_15) node _io_resp_w_T_17 = and(_io_resp_w_T_16, asSInt(UInt<33>(0h98000000))) node _io_resp_w_T_18 = asSInt(_io_resp_w_T_17) node _io_resp_w_T_19 = eq(_io_resp_w_T_18, asSInt(UInt<1>(0h0))) node _io_resp_w_T_20 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_w_T_21 = cvt(_io_resp_w_T_20) node _io_resp_w_T_22 = and(_io_resp_w_T_21, asSInt(UInt<33>(0h9a110000))) node _io_resp_w_T_23 = asSInt(_io_resp_w_T_22) node _io_resp_w_T_24 = eq(_io_resp_w_T_23, asSInt(UInt<1>(0h0))) node _io_resp_w_T_25 = xor(io.paddr, UInt<29>(0h10000000)) node _io_resp_w_T_26 = cvt(_io_resp_w_T_25) node _io_resp_w_T_27 = and(_io_resp_w_T_26, asSInt(UInt<33>(0h9a111000))) node _io_resp_w_T_28 = asSInt(_io_resp_w_T_27) node _io_resp_w_T_29 = eq(_io_resp_w_T_28, asSInt(UInt<1>(0h0))) node _io_resp_w_T_30 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_w_T_31 = cvt(_io_resp_w_T_30) node _io_resp_w_T_32 = and(_io_resp_w_T_31, asSInt(UInt<33>(0h90000000))) node _io_resp_w_T_33 = asSInt(_io_resp_w_T_32) node _io_resp_w_T_34 = eq(_io_resp_w_T_33, asSInt(UInt<1>(0h0))) node _io_resp_w_T_35 = or(_io_resp_w_T_4, _io_resp_w_T_9) node _io_resp_w_T_36 = or(_io_resp_w_T_35, _io_resp_w_T_14) node _io_resp_w_T_37 = or(_io_resp_w_T_36, _io_resp_w_T_19) node _io_resp_w_T_38 = or(_io_resp_w_T_37, _io_resp_w_T_24) node _io_resp_w_T_39 = or(_io_resp_w_T_38, _io_resp_w_T_29) node _io_resp_w_T_40 = or(_io_resp_w_T_39, _io_resp_w_T_34) node _io_resp_w_T_41 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_w_T_42 = cvt(_io_resp_w_T_41) node _io_resp_w_T_43 = and(_io_resp_w_T_42, asSInt(UInt<33>(0h9a110000))) node _io_resp_w_T_44 = asSInt(_io_resp_w_T_43) node _io_resp_w_T_45 = eq(_io_resp_w_T_44, asSInt(UInt<1>(0h0))) node _io_resp_w_T_46 = mux(_io_resp_w_T_40, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_w_T_47 = mux(_io_resp_w_T_45, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_w_T_48 = or(_io_resp_w_T_46, _io_resp_w_T_47) wire _io_resp_w_WIRE : UInt<1> connect _io_resp_w_WIRE, _io_resp_w_T_48 node _io_resp_w_T_49 = and(legal_address, _io_resp_w_WIRE) connect io.resp.w, _io_resp_w_T_49 node _io_resp_pp_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_pp_T_1 = cvt(_io_resp_pp_T) node _io_resp_pp_T_2 = and(_io_resp_pp_T_1, asSInt(UInt<33>(0h98110000))) node _io_resp_pp_T_3 = asSInt(_io_resp_pp_T_2) node _io_resp_pp_T_4 = eq(_io_resp_pp_T_3, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_5 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_pp_T_6 = cvt(_io_resp_pp_T_5) node _io_resp_pp_T_7 = and(_io_resp_pp_T_6, asSInt(UInt<33>(0h9a101000))) node _io_resp_pp_T_8 = asSInt(_io_resp_pp_T_7) node _io_resp_pp_T_9 = eq(_io_resp_pp_T_8, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_10 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_pp_T_11 = cvt(_io_resp_pp_T_10) node _io_resp_pp_T_12 = and(_io_resp_pp_T_11, asSInt(UInt<33>(0h9a111000))) node _io_resp_pp_T_13 = asSInt(_io_resp_pp_T_12) node _io_resp_pp_T_14 = eq(_io_resp_pp_T_13, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_15 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_pp_T_16 = cvt(_io_resp_pp_T_15) node _io_resp_pp_T_17 = and(_io_resp_pp_T_16, asSInt(UInt<33>(0h98000000))) node _io_resp_pp_T_18 = asSInt(_io_resp_pp_T_17) node _io_resp_pp_T_19 = eq(_io_resp_pp_T_18, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_20 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_pp_T_21 = cvt(_io_resp_pp_T_20) node _io_resp_pp_T_22 = and(_io_resp_pp_T_21, asSInt(UInt<33>(0h9a110000))) node _io_resp_pp_T_23 = asSInt(_io_resp_pp_T_22) node _io_resp_pp_T_24 = eq(_io_resp_pp_T_23, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_25 = xor(io.paddr, UInt<29>(0h10000000)) node _io_resp_pp_T_26 = cvt(_io_resp_pp_T_25) node _io_resp_pp_T_27 = and(_io_resp_pp_T_26, asSInt(UInt<33>(0h9a111000))) node _io_resp_pp_T_28 = asSInt(_io_resp_pp_T_27) node _io_resp_pp_T_29 = eq(_io_resp_pp_T_28, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_30 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_pp_T_31 = cvt(_io_resp_pp_T_30) node _io_resp_pp_T_32 = and(_io_resp_pp_T_31, asSInt(UInt<33>(0h90000000))) node _io_resp_pp_T_33 = asSInt(_io_resp_pp_T_32) node _io_resp_pp_T_34 = eq(_io_resp_pp_T_33, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_35 = or(_io_resp_pp_T_4, _io_resp_pp_T_9) node _io_resp_pp_T_36 = or(_io_resp_pp_T_35, _io_resp_pp_T_14) node _io_resp_pp_T_37 = or(_io_resp_pp_T_36, _io_resp_pp_T_19) node _io_resp_pp_T_38 = or(_io_resp_pp_T_37, _io_resp_pp_T_24) node _io_resp_pp_T_39 = or(_io_resp_pp_T_38, _io_resp_pp_T_29) node _io_resp_pp_T_40 = or(_io_resp_pp_T_39, _io_resp_pp_T_34) node _io_resp_pp_T_41 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_pp_T_42 = cvt(_io_resp_pp_T_41) node _io_resp_pp_T_43 = and(_io_resp_pp_T_42, asSInt(UInt<33>(0h9a110000))) node _io_resp_pp_T_44 = asSInt(_io_resp_pp_T_43) node _io_resp_pp_T_45 = eq(_io_resp_pp_T_44, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_46 = mux(_io_resp_pp_T_40, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_pp_T_47 = mux(_io_resp_pp_T_45, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_pp_T_48 = or(_io_resp_pp_T_46, _io_resp_pp_T_47) wire _io_resp_pp_WIRE : UInt<1> connect _io_resp_pp_WIRE, _io_resp_pp_T_48 node _io_resp_pp_T_49 = and(legal_address, _io_resp_pp_WIRE) connect io.resp.pp, _io_resp_pp_T_49 node _io_resp_al_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_al_T_1 = cvt(_io_resp_al_T) node _io_resp_al_T_2 = and(_io_resp_al_T_1, asSInt(UInt<33>(0h98110000))) node _io_resp_al_T_3 = asSInt(_io_resp_al_T_2) node _io_resp_al_T_4 = eq(_io_resp_al_T_3, asSInt(UInt<1>(0h0))) node _io_resp_al_T_5 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_al_T_6 = cvt(_io_resp_al_T_5) node _io_resp_al_T_7 = and(_io_resp_al_T_6, asSInt(UInt<33>(0h9a101000))) node _io_resp_al_T_8 = asSInt(_io_resp_al_T_7) node _io_resp_al_T_9 = eq(_io_resp_al_T_8, asSInt(UInt<1>(0h0))) node _io_resp_al_T_10 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_al_T_11 = cvt(_io_resp_al_T_10) node _io_resp_al_T_12 = and(_io_resp_al_T_11, asSInt(UInt<33>(0h9a111000))) node _io_resp_al_T_13 = asSInt(_io_resp_al_T_12) node _io_resp_al_T_14 = eq(_io_resp_al_T_13, asSInt(UInt<1>(0h0))) node _io_resp_al_T_15 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_al_T_16 = cvt(_io_resp_al_T_15) node _io_resp_al_T_17 = and(_io_resp_al_T_16, asSInt(UInt<33>(0h98000000))) node _io_resp_al_T_18 = asSInt(_io_resp_al_T_17) node _io_resp_al_T_19 = eq(_io_resp_al_T_18, asSInt(UInt<1>(0h0))) node _io_resp_al_T_20 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_al_T_21 = cvt(_io_resp_al_T_20) node _io_resp_al_T_22 = and(_io_resp_al_T_21, asSInt(UInt<33>(0h9a110000))) node _io_resp_al_T_23 = asSInt(_io_resp_al_T_22) node _io_resp_al_T_24 = eq(_io_resp_al_T_23, asSInt(UInt<1>(0h0))) node _io_resp_al_T_25 = xor(io.paddr, UInt<29>(0h10000000)) node _io_resp_al_T_26 = cvt(_io_resp_al_T_25) node _io_resp_al_T_27 = and(_io_resp_al_T_26, asSInt(UInt<33>(0h9a111000))) node _io_resp_al_T_28 = asSInt(_io_resp_al_T_27) node _io_resp_al_T_29 = eq(_io_resp_al_T_28, asSInt(UInt<1>(0h0))) node _io_resp_al_T_30 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_al_T_31 = cvt(_io_resp_al_T_30) node _io_resp_al_T_32 = and(_io_resp_al_T_31, asSInt(UInt<33>(0h90000000))) node _io_resp_al_T_33 = asSInt(_io_resp_al_T_32) node _io_resp_al_T_34 = eq(_io_resp_al_T_33, asSInt(UInt<1>(0h0))) node _io_resp_al_T_35 = or(_io_resp_al_T_4, _io_resp_al_T_9) node _io_resp_al_T_36 = or(_io_resp_al_T_35, _io_resp_al_T_14) node _io_resp_al_T_37 = or(_io_resp_al_T_36, _io_resp_al_T_19) node _io_resp_al_T_38 = or(_io_resp_al_T_37, _io_resp_al_T_24) node _io_resp_al_T_39 = or(_io_resp_al_T_38, _io_resp_al_T_29) node _io_resp_al_T_40 = or(_io_resp_al_T_39, _io_resp_al_T_34) node _io_resp_al_T_41 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_al_T_42 = cvt(_io_resp_al_T_41) node _io_resp_al_T_43 = and(_io_resp_al_T_42, asSInt(UInt<33>(0h9a110000))) node _io_resp_al_T_44 = asSInt(_io_resp_al_T_43) node _io_resp_al_T_45 = eq(_io_resp_al_T_44, asSInt(UInt<1>(0h0))) node _io_resp_al_T_46 = mux(_io_resp_al_T_40, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_al_T_47 = mux(_io_resp_al_T_45, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_al_T_48 = or(_io_resp_al_T_46, _io_resp_al_T_47) wire _io_resp_al_WIRE : UInt<1> connect _io_resp_al_WIRE, _io_resp_al_T_48 node _io_resp_al_T_49 = and(legal_address, _io_resp_al_WIRE) connect io.resp.al, _io_resp_al_T_49 node _io_resp_aa_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_aa_T_1 = cvt(_io_resp_aa_T) node _io_resp_aa_T_2 = and(_io_resp_aa_T_1, asSInt(UInt<33>(0h98110000))) node _io_resp_aa_T_3 = asSInt(_io_resp_aa_T_2) node _io_resp_aa_T_4 = eq(_io_resp_aa_T_3, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_5 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_aa_T_6 = cvt(_io_resp_aa_T_5) node _io_resp_aa_T_7 = and(_io_resp_aa_T_6, asSInt(UInt<33>(0h9a101000))) node _io_resp_aa_T_8 = asSInt(_io_resp_aa_T_7) node _io_resp_aa_T_9 = eq(_io_resp_aa_T_8, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_10 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_aa_T_11 = cvt(_io_resp_aa_T_10) node _io_resp_aa_T_12 = and(_io_resp_aa_T_11, asSInt(UInt<33>(0h9a111000))) node _io_resp_aa_T_13 = asSInt(_io_resp_aa_T_12) node _io_resp_aa_T_14 = eq(_io_resp_aa_T_13, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_15 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_aa_T_16 = cvt(_io_resp_aa_T_15) node _io_resp_aa_T_17 = and(_io_resp_aa_T_16, asSInt(UInt<33>(0h98000000))) node _io_resp_aa_T_18 = asSInt(_io_resp_aa_T_17) node _io_resp_aa_T_19 = eq(_io_resp_aa_T_18, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_20 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_aa_T_21 = cvt(_io_resp_aa_T_20) node _io_resp_aa_T_22 = and(_io_resp_aa_T_21, asSInt(UInt<33>(0h9a110000))) node _io_resp_aa_T_23 = asSInt(_io_resp_aa_T_22) node _io_resp_aa_T_24 = eq(_io_resp_aa_T_23, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_25 = xor(io.paddr, UInt<29>(0h10000000)) node _io_resp_aa_T_26 = cvt(_io_resp_aa_T_25) node _io_resp_aa_T_27 = and(_io_resp_aa_T_26, asSInt(UInt<33>(0h9a111000))) node _io_resp_aa_T_28 = asSInt(_io_resp_aa_T_27) node _io_resp_aa_T_29 = eq(_io_resp_aa_T_28, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_30 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_aa_T_31 = cvt(_io_resp_aa_T_30) node _io_resp_aa_T_32 = and(_io_resp_aa_T_31, asSInt(UInt<33>(0h90000000))) node _io_resp_aa_T_33 = asSInt(_io_resp_aa_T_32) node _io_resp_aa_T_34 = eq(_io_resp_aa_T_33, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_35 = or(_io_resp_aa_T_4, _io_resp_aa_T_9) node _io_resp_aa_T_36 = or(_io_resp_aa_T_35, _io_resp_aa_T_14) node _io_resp_aa_T_37 = or(_io_resp_aa_T_36, _io_resp_aa_T_19) node _io_resp_aa_T_38 = or(_io_resp_aa_T_37, _io_resp_aa_T_24) node _io_resp_aa_T_39 = or(_io_resp_aa_T_38, _io_resp_aa_T_29) node _io_resp_aa_T_40 = or(_io_resp_aa_T_39, _io_resp_aa_T_34) node _io_resp_aa_T_41 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_aa_T_42 = cvt(_io_resp_aa_T_41) node _io_resp_aa_T_43 = and(_io_resp_aa_T_42, asSInt(UInt<33>(0h9a110000))) node _io_resp_aa_T_44 = asSInt(_io_resp_aa_T_43) node _io_resp_aa_T_45 = eq(_io_resp_aa_T_44, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_46 = mux(_io_resp_aa_T_40, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_aa_T_47 = mux(_io_resp_aa_T_45, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_aa_T_48 = or(_io_resp_aa_T_46, _io_resp_aa_T_47) wire _io_resp_aa_WIRE : UInt<1> connect _io_resp_aa_WIRE, _io_resp_aa_T_48 node _io_resp_aa_T_49 = and(legal_address, _io_resp_aa_WIRE) connect io.resp.aa, _io_resp_aa_T_49 node _io_resp_x_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_x_T_1 = cvt(_io_resp_x_T) node _io_resp_x_T_2 = and(_io_resp_x_T_1, asSInt(UInt<33>(0h9e113000))) node _io_resp_x_T_3 = asSInt(_io_resp_x_T_2) node _io_resp_x_T_4 = eq(_io_resp_x_T_3, asSInt(UInt<1>(0h0))) node _io_resp_x_T_5 = xor(io.paddr, UInt<14>(0h3000)) node _io_resp_x_T_6 = cvt(_io_resp_x_T_5) node _io_resp_x_T_7 = and(_io_resp_x_T_6, asSInt(UInt<33>(0h9e113000))) node _io_resp_x_T_8 = asSInt(_io_resp_x_T_7) node _io_resp_x_T_9 = eq(_io_resp_x_T_8, asSInt(UInt<1>(0h0))) node _io_resp_x_T_10 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_x_T_11 = cvt(_io_resp_x_T_10) node _io_resp_x_T_12 = and(_io_resp_x_T_11, asSInt(UInt<33>(0h9e110000))) node _io_resp_x_T_13 = asSInt(_io_resp_x_T_12) node _io_resp_x_T_14 = eq(_io_resp_x_T_13, asSInt(UInt<1>(0h0))) node _io_resp_x_T_15 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_x_T_16 = cvt(_io_resp_x_T_15) node _io_resp_x_T_17 = and(_io_resp_x_T_16, asSInt(UInt<33>(0h9e110000))) node _io_resp_x_T_18 = asSInt(_io_resp_x_T_17) node _io_resp_x_T_19 = eq(_io_resp_x_T_18, asSInt(UInt<1>(0h0))) node _io_resp_x_T_20 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_x_T_21 = cvt(_io_resp_x_T_20) node _io_resp_x_T_22 = and(_io_resp_x_T_21, asSInt(UInt<33>(0h90000000))) node _io_resp_x_T_23 = asSInt(_io_resp_x_T_22) node _io_resp_x_T_24 = eq(_io_resp_x_T_23, asSInt(UInt<1>(0h0))) node _io_resp_x_T_25 = or(_io_resp_x_T_4, _io_resp_x_T_9) node _io_resp_x_T_26 = or(_io_resp_x_T_25, _io_resp_x_T_14) node _io_resp_x_T_27 = or(_io_resp_x_T_26, _io_resp_x_T_19) node _io_resp_x_T_28 = or(_io_resp_x_T_27, _io_resp_x_T_24) node _io_resp_x_T_29 = xor(io.paddr, UInt<13>(0h1000)) node _io_resp_x_T_30 = cvt(_io_resp_x_T_29) node _io_resp_x_T_31 = and(_io_resp_x_T_30, asSInt(UInt<33>(0h9e113000))) node _io_resp_x_T_32 = asSInt(_io_resp_x_T_31) node _io_resp_x_T_33 = eq(_io_resp_x_T_32, asSInt(UInt<1>(0h0))) node _io_resp_x_T_34 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_x_T_35 = cvt(_io_resp_x_T_34) node _io_resp_x_T_36 = and(_io_resp_x_T_35, asSInt(UInt<33>(0h9e103000))) node _io_resp_x_T_37 = asSInt(_io_resp_x_T_36) node _io_resp_x_T_38 = eq(_io_resp_x_T_37, asSInt(UInt<1>(0h0))) node _io_resp_x_T_39 = xor(io.paddr, UInt<26>(0h2000000)) node _io_resp_x_T_40 = cvt(_io_resp_x_T_39) node _io_resp_x_T_41 = and(_io_resp_x_T_40, asSInt(UInt<33>(0h9e110000))) node _io_resp_x_T_42 = asSInt(_io_resp_x_T_41) node _io_resp_x_T_43 = eq(_io_resp_x_T_42, asSInt(UInt<1>(0h0))) node _io_resp_x_T_44 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_x_T_45 = cvt(_io_resp_x_T_44) node _io_resp_x_T_46 = and(_io_resp_x_T_45, asSInt(UInt<33>(0h9e113000))) node _io_resp_x_T_47 = asSInt(_io_resp_x_T_46) node _io_resp_x_T_48 = eq(_io_resp_x_T_47, asSInt(UInt<1>(0h0))) node _io_resp_x_T_49 = xor(io.paddr, UInt<28>(0hc000000)) node _io_resp_x_T_50 = cvt(_io_resp_x_T_49) node _io_resp_x_T_51 = and(_io_resp_x_T_50, asSInt(UInt<33>(0h9c000000))) node _io_resp_x_T_52 = asSInt(_io_resp_x_T_51) node _io_resp_x_T_53 = eq(_io_resp_x_T_52, asSInt(UInt<1>(0h0))) node _io_resp_x_T_54 = xor(io.paddr, UInt<29>(0h10000000)) node _io_resp_x_T_55 = cvt(_io_resp_x_T_54) node _io_resp_x_T_56 = and(_io_resp_x_T_55, asSInt(UInt<33>(0h9e113000))) node _io_resp_x_T_57 = asSInt(_io_resp_x_T_56) node _io_resp_x_T_58 = eq(_io_resp_x_T_57, asSInt(UInt<1>(0h0))) node _io_resp_x_T_59 = or(_io_resp_x_T_33, _io_resp_x_T_38) node _io_resp_x_T_60 = or(_io_resp_x_T_59, _io_resp_x_T_43) node _io_resp_x_T_61 = or(_io_resp_x_T_60, _io_resp_x_T_48) node _io_resp_x_T_62 = or(_io_resp_x_T_61, _io_resp_x_T_53) node _io_resp_x_T_63 = or(_io_resp_x_T_62, _io_resp_x_T_58) node _io_resp_x_T_64 = mux(_io_resp_x_T_28, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_x_T_65 = mux(_io_resp_x_T_63, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_x_T_66 = or(_io_resp_x_T_64, _io_resp_x_T_65) wire _io_resp_x_WIRE : UInt<1> connect _io_resp_x_WIRE, _io_resp_x_T_66 node _io_resp_x_T_67 = and(legal_address, _io_resp_x_WIRE) connect io.resp.x, _io_resp_x_T_67 node _io_resp_eff_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_eff_T_1 = cvt(_io_resp_eff_T) node _io_resp_eff_T_2 = and(_io_resp_eff_T_1, asSInt(UInt<33>(0h9e112000))) node _io_resp_eff_T_3 = asSInt(_io_resp_eff_T_2) node _io_resp_eff_T_4 = eq(_io_resp_eff_T_3, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_5 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_eff_T_6 = cvt(_io_resp_eff_T_5) node _io_resp_eff_T_7 = and(_io_resp_eff_T_6, asSInt(UInt<33>(0h9e103000))) node _io_resp_eff_T_8 = asSInt(_io_resp_eff_T_7) node _io_resp_eff_T_9 = eq(_io_resp_eff_T_8, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_10 = xor(io.paddr, UInt<26>(0h2000000)) node _io_resp_eff_T_11 = cvt(_io_resp_eff_T_10) node _io_resp_eff_T_12 = and(_io_resp_eff_T_11, asSInt(UInt<33>(0h9e110000))) node _io_resp_eff_T_13 = asSInt(_io_resp_eff_T_12) node _io_resp_eff_T_14 = eq(_io_resp_eff_T_13, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_15 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_eff_T_16 = cvt(_io_resp_eff_T_15) node _io_resp_eff_T_17 = and(_io_resp_eff_T_16, asSInt(UInt<33>(0h9e113000))) node _io_resp_eff_T_18 = asSInt(_io_resp_eff_T_17) node _io_resp_eff_T_19 = eq(_io_resp_eff_T_18, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_20 = xor(io.paddr, UInt<28>(0hc000000)) node _io_resp_eff_T_21 = cvt(_io_resp_eff_T_20) node _io_resp_eff_T_22 = and(_io_resp_eff_T_21, asSInt(UInt<33>(0h9c000000))) node _io_resp_eff_T_23 = asSInt(_io_resp_eff_T_22) node _io_resp_eff_T_24 = eq(_io_resp_eff_T_23, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_25 = xor(io.paddr, UInt<29>(0h10000000)) node _io_resp_eff_T_26 = cvt(_io_resp_eff_T_25) node _io_resp_eff_T_27 = and(_io_resp_eff_T_26, asSInt(UInt<33>(0h9e113000))) node _io_resp_eff_T_28 = asSInt(_io_resp_eff_T_27) node _io_resp_eff_T_29 = eq(_io_resp_eff_T_28, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_30 = or(_io_resp_eff_T_4, _io_resp_eff_T_9) node _io_resp_eff_T_31 = or(_io_resp_eff_T_30, _io_resp_eff_T_14) node _io_resp_eff_T_32 = or(_io_resp_eff_T_31, _io_resp_eff_T_19) node _io_resp_eff_T_33 = or(_io_resp_eff_T_32, _io_resp_eff_T_24) node _io_resp_eff_T_34 = or(_io_resp_eff_T_33, _io_resp_eff_T_29) node _io_resp_eff_T_35 = xor(io.paddr, UInt<14>(0h3000)) node _io_resp_eff_T_36 = cvt(_io_resp_eff_T_35) node _io_resp_eff_T_37 = and(_io_resp_eff_T_36, asSInt(UInt<33>(0h9e113000))) node _io_resp_eff_T_38 = asSInt(_io_resp_eff_T_37) node _io_resp_eff_T_39 = eq(_io_resp_eff_T_38, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_40 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_eff_T_41 = cvt(_io_resp_eff_T_40) node _io_resp_eff_T_42 = and(_io_resp_eff_T_41, asSInt(UInt<33>(0h9e110000))) node _io_resp_eff_T_43 = asSInt(_io_resp_eff_T_42) node _io_resp_eff_T_44 = eq(_io_resp_eff_T_43, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_45 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_eff_T_46 = cvt(_io_resp_eff_T_45) node _io_resp_eff_T_47 = and(_io_resp_eff_T_46, asSInt(UInt<33>(0h9e110000))) node _io_resp_eff_T_48 = asSInt(_io_resp_eff_T_47) node _io_resp_eff_T_49 = eq(_io_resp_eff_T_48, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_50 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_eff_T_51 = cvt(_io_resp_eff_T_50) node _io_resp_eff_T_52 = and(_io_resp_eff_T_51, asSInt(UInt<33>(0h90000000))) node _io_resp_eff_T_53 = asSInt(_io_resp_eff_T_52) node _io_resp_eff_T_54 = eq(_io_resp_eff_T_53, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_55 = or(_io_resp_eff_T_39, _io_resp_eff_T_44) node _io_resp_eff_T_56 = or(_io_resp_eff_T_55, _io_resp_eff_T_49) node _io_resp_eff_T_57 = or(_io_resp_eff_T_56, _io_resp_eff_T_54) node _io_resp_eff_T_58 = mux(_io_resp_eff_T_34, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_eff_T_59 = mux(_io_resp_eff_T_57, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_eff_T_60 = or(_io_resp_eff_T_58, _io_resp_eff_T_59) wire _io_resp_eff_WIRE : UInt<1> connect _io_resp_eff_WIRE, _io_resp_eff_T_60 node _io_resp_eff_T_61 = and(legal_address, _io_resp_eff_WIRE) connect io.resp.eff, _io_resp_eff_T_61
module PMAChecker_22( // @[PMA.scala:18:7] input clock, // @[PMA.scala:18:7] input reset, // @[PMA.scala:18:7] input [39:0] io_paddr, // @[PMA.scala:19:14] output io_resp_cacheable, // @[PMA.scala:19:14] output io_resp_r, // @[PMA.scala:19:14] output io_resp_w, // @[PMA.scala:19:14] output io_resp_pp, // @[PMA.scala:19:14] output io_resp_al, // @[PMA.scala:19:14] output io_resp_aa, // @[PMA.scala:19:14] output io_resp_x, // @[PMA.scala:19:14] output io_resp_eff // @[PMA.scala:19:14] ); wire [39:0] io_paddr_0 = io_paddr; // @[PMA.scala:18:7] wire [40:0] _io_resp_r_T_2 = 41'h0; // @[Parameters.scala:137:46] wire [40:0] _io_resp_r_T_3 = 41'h0; // @[Parameters.scala:137:46] wire _io_resp_r_T_4 = 1'h1; // @[Parameters.scala:137:59] wire _io_resp_cacheable_T_28 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_w_T_47 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_pp_T_47 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_al_T_47 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_aa_T_47 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_x_T_65 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_eff_T_59 = 1'h0; // @[Mux.scala:30:73] wire [39:0] _legal_address_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_cacheable_T = io_paddr_0; // @[PMA.scala:18:7] wire _io_resp_cacheable_T_31; // @[PMA.scala:39:19] wire [39:0] _io_resp_r_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_w_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_pp_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_al_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_aa_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_x_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_eff_T = io_paddr_0; // @[PMA.scala:18:7] wire _io_resp_r_T_5; // @[PMA.scala:39:19] wire _io_resp_w_T_49; // @[PMA.scala:39:19] wire _io_resp_pp_T_49; // @[PMA.scala:39:19] wire _io_resp_al_T_49; // @[PMA.scala:39:19] wire _io_resp_aa_T_49; // @[PMA.scala:39:19] wire _io_resp_x_T_67; // @[PMA.scala:39:19] wire _io_resp_eff_T_61; // @[PMA.scala:39:19] wire io_resp_cacheable_0; // @[PMA.scala:18:7] wire io_resp_r_0; // @[PMA.scala:18:7] wire io_resp_w_0; // @[PMA.scala:18:7] wire io_resp_pp_0; // @[PMA.scala:18:7] wire io_resp_al_0; // @[PMA.scala:18:7] wire io_resp_aa_0; // @[PMA.scala:18:7] wire io_resp_x_0; // @[PMA.scala:18:7] wire io_resp_eff_0; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_1 = {1'h0, _legal_address_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_2 = _legal_address_T_1 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_3 = _legal_address_T_2; // @[Parameters.scala:137:46] wire _legal_address_T_4 = _legal_address_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_0 = _legal_address_T_4; // @[Parameters.scala:612:40] wire [39:0] _GEN = {io_paddr_0[39:13], io_paddr_0[12:0] ^ 13'h1000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_5; // @[Parameters.scala:137:31] assign _legal_address_T_5 = _GEN; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_29; // @[Parameters.scala:137:31] assign _io_resp_x_T_29 = _GEN; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_6 = {1'h0, _legal_address_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_7 = _legal_address_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_8 = _legal_address_T_7; // @[Parameters.scala:137:46] wire _legal_address_T_9 = _legal_address_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_1 = _legal_address_T_9; // @[Parameters.scala:612:40] wire [39:0] _GEN_0 = {io_paddr_0[39:14], io_paddr_0[13:0] ^ 14'h3000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_10; // @[Parameters.scala:137:31] assign _legal_address_T_10 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_5; // @[Parameters.scala:137:31] assign _io_resp_x_T_5 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_35; // @[Parameters.scala:137:31] assign _io_resp_eff_T_35 = _GEN_0; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_11 = {1'h0, _legal_address_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_12 = _legal_address_T_11 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_13 = _legal_address_T_12; // @[Parameters.scala:137:46] wire _legal_address_T_14 = _legal_address_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_2 = _legal_address_T_14; // @[Parameters.scala:612:40] wire [39:0] _GEN_1 = {io_paddr_0[39:17], io_paddr_0[16:0] ^ 17'h10000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_15; // @[Parameters.scala:137:31] assign _legal_address_T_15 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_cacheable_T_5; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_5 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_41; // @[Parameters.scala:137:31] assign _io_resp_w_T_41 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_41; // @[Parameters.scala:137:31] assign _io_resp_pp_T_41 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_41; // @[Parameters.scala:137:31] assign _io_resp_al_T_41 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_41; // @[Parameters.scala:137:31] assign _io_resp_aa_T_41 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_10; // @[Parameters.scala:137:31] assign _io_resp_x_T_10 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_40; // @[Parameters.scala:137:31] assign _io_resp_eff_T_40 = _GEN_1; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_16 = {1'h0, _legal_address_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_17 = _legal_address_T_16 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_18 = _legal_address_T_17; // @[Parameters.scala:137:46] wire _legal_address_T_19 = _legal_address_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_3 = _legal_address_T_19; // @[Parameters.scala:612:40] wire [39:0] _GEN_2 = {io_paddr_0[39:21], io_paddr_0[20:0] ^ 21'h100000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_20; // @[Parameters.scala:137:31] assign _legal_address_T_20 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_5; // @[Parameters.scala:137:31] assign _io_resp_w_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_5; // @[Parameters.scala:137:31] assign _io_resp_pp_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_5; // @[Parameters.scala:137:31] assign _io_resp_al_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_5; // @[Parameters.scala:137:31] assign _io_resp_aa_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_34; // @[Parameters.scala:137:31] assign _io_resp_x_T_34 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_5; // @[Parameters.scala:137:31] assign _io_resp_eff_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_21 = {1'h0, _legal_address_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_22 = _legal_address_T_21 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_23 = _legal_address_T_22; // @[Parameters.scala:137:46] wire _legal_address_T_24 = _legal_address_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_4 = _legal_address_T_24; // @[Parameters.scala:612:40] wire [39:0] _legal_address_T_25 = {io_paddr_0[39:21], io_paddr_0[20:0] ^ 21'h110000}; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_26 = {1'h0, _legal_address_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_27 = _legal_address_T_26 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_28 = _legal_address_T_27; // @[Parameters.scala:137:46] wire _legal_address_T_29 = _legal_address_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_5 = _legal_address_T_29; // @[Parameters.scala:612:40] wire [39:0] _GEN_3 = {io_paddr_0[39:26], io_paddr_0[25:0] ^ 26'h2000000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_30; // @[Parameters.scala:137:31] assign _legal_address_T_30 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_39; // @[Parameters.scala:137:31] assign _io_resp_x_T_39 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_10; // @[Parameters.scala:137:31] assign _io_resp_eff_T_10 = _GEN_3; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_31 = {1'h0, _legal_address_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_32 = _legal_address_T_31 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_33 = _legal_address_T_32; // @[Parameters.scala:137:46] wire _legal_address_T_34 = _legal_address_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_6 = _legal_address_T_34; // @[Parameters.scala:612:40] wire [39:0] _GEN_4 = {io_paddr_0[39:26], io_paddr_0[25:0] ^ 26'h2010000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_35; // @[Parameters.scala:137:31] assign _legal_address_T_35 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_10; // @[Parameters.scala:137:31] assign _io_resp_w_T_10 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_10; // @[Parameters.scala:137:31] assign _io_resp_pp_T_10 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_10; // @[Parameters.scala:137:31] assign _io_resp_al_T_10 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_10; // @[Parameters.scala:137:31] assign _io_resp_aa_T_10 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_44; // @[Parameters.scala:137:31] assign _io_resp_x_T_44 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_15; // @[Parameters.scala:137:31] assign _io_resp_eff_T_15 = _GEN_4; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_36 = {1'h0, _legal_address_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_37 = _legal_address_T_36 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_38 = _legal_address_T_37; // @[Parameters.scala:137:46] wire _legal_address_T_39 = _legal_address_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_7 = _legal_address_T_39; // @[Parameters.scala:612:40] wire [39:0] _GEN_5 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'h8000000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_40; // @[Parameters.scala:137:31] assign _legal_address_T_40 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_cacheable_T_17; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_17 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_15; // @[Parameters.scala:137:31] assign _io_resp_w_T_15 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_20; // @[Parameters.scala:137:31] assign _io_resp_w_T_20 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_15; // @[Parameters.scala:137:31] assign _io_resp_pp_T_15 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_20; // @[Parameters.scala:137:31] assign _io_resp_pp_T_20 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_15; // @[Parameters.scala:137:31] assign _io_resp_al_T_15 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_20; // @[Parameters.scala:137:31] assign _io_resp_al_T_20 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_15; // @[Parameters.scala:137:31] assign _io_resp_aa_T_15 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_20; // @[Parameters.scala:137:31] assign _io_resp_aa_T_20 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_15; // @[Parameters.scala:137:31] assign _io_resp_x_T_15 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_45; // @[Parameters.scala:137:31] assign _io_resp_eff_T_45 = _GEN_5; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_41 = {1'h0, _legal_address_T_40}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_42 = _legal_address_T_41 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_43 = _legal_address_T_42; // @[Parameters.scala:137:46] wire _legal_address_T_44 = _legal_address_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_8 = _legal_address_T_44; // @[Parameters.scala:612:40] wire [39:0] _GEN_6 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'hC000000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_45; // @[Parameters.scala:137:31] assign _legal_address_T_45 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _io_resp_cacheable_T_10; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_10 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_49; // @[Parameters.scala:137:31] assign _io_resp_x_T_49 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_20; // @[Parameters.scala:137:31] assign _io_resp_eff_T_20 = _GEN_6; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_46 = {1'h0, _legal_address_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_47 = _legal_address_T_46 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_48 = _legal_address_T_47; // @[Parameters.scala:137:46] wire _legal_address_T_49 = _legal_address_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_9 = _legal_address_T_49; // @[Parameters.scala:612:40] wire [39:0] _legal_address_T_50 = {io_paddr_0[39:29], io_paddr_0[28:0] ^ 29'h10020000}; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_51 = {1'h0, _legal_address_T_50}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_52 = _legal_address_T_51 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_53 = _legal_address_T_52; // @[Parameters.scala:137:46] wire _legal_address_T_54 = _legal_address_T_53 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_10 = _legal_address_T_54; // @[Parameters.scala:612:40] wire [39:0] _GEN_7 = {io_paddr_0[39:32], io_paddr_0[31:0] ^ 32'h80000000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_55; // @[Parameters.scala:137:31] assign _legal_address_T_55 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_cacheable_T_22; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_22 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_30; // @[Parameters.scala:137:31] assign _io_resp_w_T_30 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_30; // @[Parameters.scala:137:31] assign _io_resp_pp_T_30 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_30; // @[Parameters.scala:137:31] assign _io_resp_al_T_30 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_30; // @[Parameters.scala:137:31] assign _io_resp_aa_T_30 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_20; // @[Parameters.scala:137:31] assign _io_resp_x_T_20 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_50; // @[Parameters.scala:137:31] assign _io_resp_eff_T_50 = _GEN_7; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_56 = {1'h0, _legal_address_T_55}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_57 = _legal_address_T_56 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_58 = _legal_address_T_57; // @[Parameters.scala:137:46] wire _legal_address_T_59 = _legal_address_T_58 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_11 = _legal_address_T_59; // @[Parameters.scala:612:40] wire _legal_address_T_60 = _legal_address_WIRE_0 | _legal_address_WIRE_1; // @[Parameters.scala:612:40] wire _legal_address_T_61 = _legal_address_T_60 | _legal_address_WIRE_2; // @[Parameters.scala:612:40] wire _legal_address_T_62 = _legal_address_T_61 | _legal_address_WIRE_3; // @[Parameters.scala:612:40] wire _legal_address_T_63 = _legal_address_T_62 | _legal_address_WIRE_4; // @[Parameters.scala:612:40] wire _legal_address_T_64 = _legal_address_T_63 | _legal_address_WIRE_5; // @[Parameters.scala:612:40] wire _legal_address_T_65 = _legal_address_T_64 | _legal_address_WIRE_6; // @[Parameters.scala:612:40] wire _legal_address_T_66 = _legal_address_T_65 | _legal_address_WIRE_7; // @[Parameters.scala:612:40] wire _legal_address_T_67 = _legal_address_T_66 | _legal_address_WIRE_8; // @[Parameters.scala:612:40] wire _legal_address_T_68 = _legal_address_T_67 | _legal_address_WIRE_9; // @[Parameters.scala:612:40] wire _legal_address_T_69 = _legal_address_T_68 | _legal_address_WIRE_10; // @[Parameters.scala:612:40] wire legal_address = _legal_address_T_69 | _legal_address_WIRE_11; // @[Parameters.scala:612:40] assign _io_resp_r_T_5 = legal_address; // @[PMA.scala:36:58, :39:19] wire [40:0] _io_resp_cacheable_T_1 = {1'h0, _io_resp_cacheable_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_2 = _io_resp_cacheable_T_1 & 41'h8C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_3 = _io_resp_cacheable_T_2; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_4 = _io_resp_cacheable_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_cacheable_T_6 = {1'h0, _io_resp_cacheable_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_7 = _io_resp_cacheable_T_6 & 41'h8C011000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_8 = _io_resp_cacheable_T_7; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_9 = _io_resp_cacheable_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_cacheable_T_11 = {1'h0, _io_resp_cacheable_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_12 = _io_resp_cacheable_T_11 & 41'h8C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_13 = _io_resp_cacheable_T_12; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_14 = _io_resp_cacheable_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_cacheable_T_15 = _io_resp_cacheable_T_4 | _io_resp_cacheable_T_9; // @[Parameters.scala:629:89] wire _io_resp_cacheable_T_16 = _io_resp_cacheable_T_15 | _io_resp_cacheable_T_14; // @[Parameters.scala:629:89] wire [40:0] _io_resp_cacheable_T_18 = {1'h0, _io_resp_cacheable_T_17}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_19 = _io_resp_cacheable_T_18 & 41'h8C010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_20 = _io_resp_cacheable_T_19; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_21 = _io_resp_cacheable_T_20 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_cacheable_T_23 = {1'h0, _io_resp_cacheable_T_22}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_24 = _io_resp_cacheable_T_23 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_25 = _io_resp_cacheable_T_24; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_26 = _io_resp_cacheable_T_25 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_cacheable_T_27 = _io_resp_cacheable_T_21 | _io_resp_cacheable_T_26; // @[Parameters.scala:629:89] wire _io_resp_cacheable_T_29 = _io_resp_cacheable_T_27; // @[Mux.scala:30:73] wire _io_resp_cacheable_T_30 = _io_resp_cacheable_T_29; // @[Mux.scala:30:73] wire _io_resp_cacheable_WIRE = _io_resp_cacheable_T_30; // @[Mux.scala:30:73] assign _io_resp_cacheable_T_31 = legal_address & _io_resp_cacheable_WIRE; // @[Mux.scala:30:73] assign io_resp_cacheable_0 = _io_resp_cacheable_T_31; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_r_T_1 = {1'h0, _io_resp_r_T}; // @[Parameters.scala:137:{31,41}] assign io_resp_r_0 = _io_resp_r_T_5; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_w_T_1 = {1'h0, _io_resp_w_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_2 = _io_resp_w_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_3 = _io_resp_w_T_2; // @[Parameters.scala:137:46] wire _io_resp_w_T_4 = _io_resp_w_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_6 = {1'h0, _io_resp_w_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_7 = _io_resp_w_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_8 = _io_resp_w_T_7; // @[Parameters.scala:137:46] wire _io_resp_w_T_9 = _io_resp_w_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_11 = {1'h0, _io_resp_w_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_12 = _io_resp_w_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_13 = _io_resp_w_T_12; // @[Parameters.scala:137:46] wire _io_resp_w_T_14 = _io_resp_w_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_16 = {1'h0, _io_resp_w_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_17 = _io_resp_w_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_18 = _io_resp_w_T_17; // @[Parameters.scala:137:46] wire _io_resp_w_T_19 = _io_resp_w_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_21 = {1'h0, _io_resp_w_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_22 = _io_resp_w_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_23 = _io_resp_w_T_22; // @[Parameters.scala:137:46] wire _io_resp_w_T_24 = _io_resp_w_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_8 = {io_paddr_0[39:29], io_paddr_0[28:0] ^ 29'h10000000}; // @[PMA.scala:18:7] wire [39:0] _io_resp_w_T_25; // @[Parameters.scala:137:31] assign _io_resp_w_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_25; // @[Parameters.scala:137:31] assign _io_resp_pp_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_25; // @[Parameters.scala:137:31] assign _io_resp_al_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_25; // @[Parameters.scala:137:31] assign _io_resp_aa_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_54; // @[Parameters.scala:137:31] assign _io_resp_x_T_54 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_25; // @[Parameters.scala:137:31] assign _io_resp_eff_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [40:0] _io_resp_w_T_26 = {1'h0, _io_resp_w_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_27 = _io_resp_w_T_26 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_28 = _io_resp_w_T_27; // @[Parameters.scala:137:46] wire _io_resp_w_T_29 = _io_resp_w_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_31 = {1'h0, _io_resp_w_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_32 = _io_resp_w_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_33 = _io_resp_w_T_32; // @[Parameters.scala:137:46] wire _io_resp_w_T_34 = _io_resp_w_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_w_T_35 = _io_resp_w_T_4 | _io_resp_w_T_9; // @[Parameters.scala:629:89] wire _io_resp_w_T_36 = _io_resp_w_T_35 | _io_resp_w_T_14; // @[Parameters.scala:629:89] wire _io_resp_w_T_37 = _io_resp_w_T_36 | _io_resp_w_T_19; // @[Parameters.scala:629:89] wire _io_resp_w_T_38 = _io_resp_w_T_37 | _io_resp_w_T_24; // @[Parameters.scala:629:89] wire _io_resp_w_T_39 = _io_resp_w_T_38 | _io_resp_w_T_29; // @[Parameters.scala:629:89] wire _io_resp_w_T_40 = _io_resp_w_T_39 | _io_resp_w_T_34; // @[Parameters.scala:629:89] wire _io_resp_w_T_46 = _io_resp_w_T_40; // @[Mux.scala:30:73] wire [40:0] _io_resp_w_T_42 = {1'h0, _io_resp_w_T_41}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_43 = _io_resp_w_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_44 = _io_resp_w_T_43; // @[Parameters.scala:137:46] wire _io_resp_w_T_45 = _io_resp_w_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_w_T_48 = _io_resp_w_T_46; // @[Mux.scala:30:73] wire _io_resp_w_WIRE = _io_resp_w_T_48; // @[Mux.scala:30:73] assign _io_resp_w_T_49 = legal_address & _io_resp_w_WIRE; // @[Mux.scala:30:73] assign io_resp_w_0 = _io_resp_w_T_49; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_pp_T_1 = {1'h0, _io_resp_pp_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_2 = _io_resp_pp_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_3 = _io_resp_pp_T_2; // @[Parameters.scala:137:46] wire _io_resp_pp_T_4 = _io_resp_pp_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_6 = {1'h0, _io_resp_pp_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_7 = _io_resp_pp_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_8 = _io_resp_pp_T_7; // @[Parameters.scala:137:46] wire _io_resp_pp_T_9 = _io_resp_pp_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_11 = {1'h0, _io_resp_pp_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_12 = _io_resp_pp_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_13 = _io_resp_pp_T_12; // @[Parameters.scala:137:46] wire _io_resp_pp_T_14 = _io_resp_pp_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_16 = {1'h0, _io_resp_pp_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_17 = _io_resp_pp_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_18 = _io_resp_pp_T_17; // @[Parameters.scala:137:46] wire _io_resp_pp_T_19 = _io_resp_pp_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_21 = {1'h0, _io_resp_pp_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_22 = _io_resp_pp_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_23 = _io_resp_pp_T_22; // @[Parameters.scala:137:46] wire _io_resp_pp_T_24 = _io_resp_pp_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_26 = {1'h0, _io_resp_pp_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_27 = _io_resp_pp_T_26 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_28 = _io_resp_pp_T_27; // @[Parameters.scala:137:46] wire _io_resp_pp_T_29 = _io_resp_pp_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_31 = {1'h0, _io_resp_pp_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_32 = _io_resp_pp_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_33 = _io_resp_pp_T_32; // @[Parameters.scala:137:46] wire _io_resp_pp_T_34 = _io_resp_pp_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_pp_T_35 = _io_resp_pp_T_4 | _io_resp_pp_T_9; // @[Parameters.scala:629:89] wire _io_resp_pp_T_36 = _io_resp_pp_T_35 | _io_resp_pp_T_14; // @[Parameters.scala:629:89] wire _io_resp_pp_T_37 = _io_resp_pp_T_36 | _io_resp_pp_T_19; // @[Parameters.scala:629:89] wire _io_resp_pp_T_38 = _io_resp_pp_T_37 | _io_resp_pp_T_24; // @[Parameters.scala:629:89] wire _io_resp_pp_T_39 = _io_resp_pp_T_38 | _io_resp_pp_T_29; // @[Parameters.scala:629:89] wire _io_resp_pp_T_40 = _io_resp_pp_T_39 | _io_resp_pp_T_34; // @[Parameters.scala:629:89] wire _io_resp_pp_T_46 = _io_resp_pp_T_40; // @[Mux.scala:30:73] wire [40:0] _io_resp_pp_T_42 = {1'h0, _io_resp_pp_T_41}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_43 = _io_resp_pp_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_44 = _io_resp_pp_T_43; // @[Parameters.scala:137:46] wire _io_resp_pp_T_45 = _io_resp_pp_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_pp_T_48 = _io_resp_pp_T_46; // @[Mux.scala:30:73] wire _io_resp_pp_WIRE = _io_resp_pp_T_48; // @[Mux.scala:30:73] assign _io_resp_pp_T_49 = legal_address & _io_resp_pp_WIRE; // @[Mux.scala:30:73] assign io_resp_pp_0 = _io_resp_pp_T_49; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_al_T_1 = {1'h0, _io_resp_al_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_2 = _io_resp_al_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_3 = _io_resp_al_T_2; // @[Parameters.scala:137:46] wire _io_resp_al_T_4 = _io_resp_al_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_6 = {1'h0, _io_resp_al_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_7 = _io_resp_al_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_8 = _io_resp_al_T_7; // @[Parameters.scala:137:46] wire _io_resp_al_T_9 = _io_resp_al_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_11 = {1'h0, _io_resp_al_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_12 = _io_resp_al_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_13 = _io_resp_al_T_12; // @[Parameters.scala:137:46] wire _io_resp_al_T_14 = _io_resp_al_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_16 = {1'h0, _io_resp_al_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_17 = _io_resp_al_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_18 = _io_resp_al_T_17; // @[Parameters.scala:137:46] wire _io_resp_al_T_19 = _io_resp_al_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_21 = {1'h0, _io_resp_al_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_22 = _io_resp_al_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_23 = _io_resp_al_T_22; // @[Parameters.scala:137:46] wire _io_resp_al_T_24 = _io_resp_al_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_26 = {1'h0, _io_resp_al_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_27 = _io_resp_al_T_26 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_28 = _io_resp_al_T_27; // @[Parameters.scala:137:46] wire _io_resp_al_T_29 = _io_resp_al_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_31 = {1'h0, _io_resp_al_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_32 = _io_resp_al_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_33 = _io_resp_al_T_32; // @[Parameters.scala:137:46] wire _io_resp_al_T_34 = _io_resp_al_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_al_T_35 = _io_resp_al_T_4 | _io_resp_al_T_9; // @[Parameters.scala:629:89] wire _io_resp_al_T_36 = _io_resp_al_T_35 | _io_resp_al_T_14; // @[Parameters.scala:629:89] wire _io_resp_al_T_37 = _io_resp_al_T_36 | _io_resp_al_T_19; // @[Parameters.scala:629:89] wire _io_resp_al_T_38 = _io_resp_al_T_37 | _io_resp_al_T_24; // @[Parameters.scala:629:89] wire _io_resp_al_T_39 = _io_resp_al_T_38 | _io_resp_al_T_29; // @[Parameters.scala:629:89] wire _io_resp_al_T_40 = _io_resp_al_T_39 | _io_resp_al_T_34; // @[Parameters.scala:629:89] wire _io_resp_al_T_46 = _io_resp_al_T_40; // @[Mux.scala:30:73] wire [40:0] _io_resp_al_T_42 = {1'h0, _io_resp_al_T_41}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_43 = _io_resp_al_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_44 = _io_resp_al_T_43; // @[Parameters.scala:137:46] wire _io_resp_al_T_45 = _io_resp_al_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_al_T_48 = _io_resp_al_T_46; // @[Mux.scala:30:73] wire _io_resp_al_WIRE = _io_resp_al_T_48; // @[Mux.scala:30:73] assign _io_resp_al_T_49 = legal_address & _io_resp_al_WIRE; // @[Mux.scala:30:73] assign io_resp_al_0 = _io_resp_al_T_49; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_aa_T_1 = {1'h0, _io_resp_aa_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_2 = _io_resp_aa_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_3 = _io_resp_aa_T_2; // @[Parameters.scala:137:46] wire _io_resp_aa_T_4 = _io_resp_aa_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_6 = {1'h0, _io_resp_aa_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_7 = _io_resp_aa_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_8 = _io_resp_aa_T_7; // @[Parameters.scala:137:46] wire _io_resp_aa_T_9 = _io_resp_aa_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_11 = {1'h0, _io_resp_aa_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_12 = _io_resp_aa_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_13 = _io_resp_aa_T_12; // @[Parameters.scala:137:46] wire _io_resp_aa_T_14 = _io_resp_aa_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_16 = {1'h0, _io_resp_aa_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_17 = _io_resp_aa_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_18 = _io_resp_aa_T_17; // @[Parameters.scala:137:46] wire _io_resp_aa_T_19 = _io_resp_aa_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_21 = {1'h0, _io_resp_aa_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_22 = _io_resp_aa_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_23 = _io_resp_aa_T_22; // @[Parameters.scala:137:46] wire _io_resp_aa_T_24 = _io_resp_aa_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_26 = {1'h0, _io_resp_aa_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_27 = _io_resp_aa_T_26 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_28 = _io_resp_aa_T_27; // @[Parameters.scala:137:46] wire _io_resp_aa_T_29 = _io_resp_aa_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_31 = {1'h0, _io_resp_aa_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_32 = _io_resp_aa_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_33 = _io_resp_aa_T_32; // @[Parameters.scala:137:46] wire _io_resp_aa_T_34 = _io_resp_aa_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_aa_T_35 = _io_resp_aa_T_4 | _io_resp_aa_T_9; // @[Parameters.scala:629:89] wire _io_resp_aa_T_36 = _io_resp_aa_T_35 | _io_resp_aa_T_14; // @[Parameters.scala:629:89] wire _io_resp_aa_T_37 = _io_resp_aa_T_36 | _io_resp_aa_T_19; // @[Parameters.scala:629:89] wire _io_resp_aa_T_38 = _io_resp_aa_T_37 | _io_resp_aa_T_24; // @[Parameters.scala:629:89] wire _io_resp_aa_T_39 = _io_resp_aa_T_38 | _io_resp_aa_T_29; // @[Parameters.scala:629:89] wire _io_resp_aa_T_40 = _io_resp_aa_T_39 | _io_resp_aa_T_34; // @[Parameters.scala:629:89] wire _io_resp_aa_T_46 = _io_resp_aa_T_40; // @[Mux.scala:30:73] wire [40:0] _io_resp_aa_T_42 = {1'h0, _io_resp_aa_T_41}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_43 = _io_resp_aa_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_44 = _io_resp_aa_T_43; // @[Parameters.scala:137:46] wire _io_resp_aa_T_45 = _io_resp_aa_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_aa_T_48 = _io_resp_aa_T_46; // @[Mux.scala:30:73] wire _io_resp_aa_WIRE = _io_resp_aa_T_48; // @[Mux.scala:30:73] assign _io_resp_aa_T_49 = legal_address & _io_resp_aa_WIRE; // @[Mux.scala:30:73] assign io_resp_aa_0 = _io_resp_aa_T_49; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_x_T_1 = {1'h0, _io_resp_x_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_2 = _io_resp_x_T_1 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_3 = _io_resp_x_T_2; // @[Parameters.scala:137:46] wire _io_resp_x_T_4 = _io_resp_x_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_6 = {1'h0, _io_resp_x_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_7 = _io_resp_x_T_6 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_8 = _io_resp_x_T_7; // @[Parameters.scala:137:46] wire _io_resp_x_T_9 = _io_resp_x_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_11 = {1'h0, _io_resp_x_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_12 = _io_resp_x_T_11 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_13 = _io_resp_x_T_12; // @[Parameters.scala:137:46] wire _io_resp_x_T_14 = _io_resp_x_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_16 = {1'h0, _io_resp_x_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_17 = _io_resp_x_T_16 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_18 = _io_resp_x_T_17; // @[Parameters.scala:137:46] wire _io_resp_x_T_19 = _io_resp_x_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_21 = {1'h0, _io_resp_x_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_22 = _io_resp_x_T_21 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_23 = _io_resp_x_T_22; // @[Parameters.scala:137:46] wire _io_resp_x_T_24 = _io_resp_x_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_x_T_25 = _io_resp_x_T_4 | _io_resp_x_T_9; // @[Parameters.scala:629:89] wire _io_resp_x_T_26 = _io_resp_x_T_25 | _io_resp_x_T_14; // @[Parameters.scala:629:89] wire _io_resp_x_T_27 = _io_resp_x_T_26 | _io_resp_x_T_19; // @[Parameters.scala:629:89] wire _io_resp_x_T_28 = _io_resp_x_T_27 | _io_resp_x_T_24; // @[Parameters.scala:629:89] wire _io_resp_x_T_64 = _io_resp_x_T_28; // @[Mux.scala:30:73] wire [40:0] _io_resp_x_T_30 = {1'h0, _io_resp_x_T_29}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_31 = _io_resp_x_T_30 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_32 = _io_resp_x_T_31; // @[Parameters.scala:137:46] wire _io_resp_x_T_33 = _io_resp_x_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_35 = {1'h0, _io_resp_x_T_34}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_36 = _io_resp_x_T_35 & 41'h9E103000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_37 = _io_resp_x_T_36; // @[Parameters.scala:137:46] wire _io_resp_x_T_38 = _io_resp_x_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_40 = {1'h0, _io_resp_x_T_39}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_41 = _io_resp_x_T_40 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_42 = _io_resp_x_T_41; // @[Parameters.scala:137:46] wire _io_resp_x_T_43 = _io_resp_x_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_45 = {1'h0, _io_resp_x_T_44}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_46 = _io_resp_x_T_45 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_47 = _io_resp_x_T_46; // @[Parameters.scala:137:46] wire _io_resp_x_T_48 = _io_resp_x_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_50 = {1'h0, _io_resp_x_T_49}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_51 = _io_resp_x_T_50 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_52 = _io_resp_x_T_51; // @[Parameters.scala:137:46] wire _io_resp_x_T_53 = _io_resp_x_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_55 = {1'h0, _io_resp_x_T_54}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_56 = _io_resp_x_T_55 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_57 = _io_resp_x_T_56; // @[Parameters.scala:137:46] wire _io_resp_x_T_58 = _io_resp_x_T_57 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_x_T_59 = _io_resp_x_T_33 | _io_resp_x_T_38; // @[Parameters.scala:629:89] wire _io_resp_x_T_60 = _io_resp_x_T_59 | _io_resp_x_T_43; // @[Parameters.scala:629:89] wire _io_resp_x_T_61 = _io_resp_x_T_60 | _io_resp_x_T_48; // @[Parameters.scala:629:89] wire _io_resp_x_T_62 = _io_resp_x_T_61 | _io_resp_x_T_53; // @[Parameters.scala:629:89] wire _io_resp_x_T_63 = _io_resp_x_T_62 | _io_resp_x_T_58; // @[Parameters.scala:629:89] wire _io_resp_x_T_66 = _io_resp_x_T_64; // @[Mux.scala:30:73] wire _io_resp_x_WIRE = _io_resp_x_T_66; // @[Mux.scala:30:73] assign _io_resp_x_T_67 = legal_address & _io_resp_x_WIRE; // @[Mux.scala:30:73] assign io_resp_x_0 = _io_resp_x_T_67; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_eff_T_1 = {1'h0, _io_resp_eff_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_2 = _io_resp_eff_T_1 & 41'h9E112000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_3 = _io_resp_eff_T_2; // @[Parameters.scala:137:46] wire _io_resp_eff_T_4 = _io_resp_eff_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_6 = {1'h0, _io_resp_eff_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_7 = _io_resp_eff_T_6 & 41'h9E103000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_8 = _io_resp_eff_T_7; // @[Parameters.scala:137:46] wire _io_resp_eff_T_9 = _io_resp_eff_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_11 = {1'h0, _io_resp_eff_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_12 = _io_resp_eff_T_11 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_13 = _io_resp_eff_T_12; // @[Parameters.scala:137:46] wire _io_resp_eff_T_14 = _io_resp_eff_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_16 = {1'h0, _io_resp_eff_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_17 = _io_resp_eff_T_16 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_18 = _io_resp_eff_T_17; // @[Parameters.scala:137:46] wire _io_resp_eff_T_19 = _io_resp_eff_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_21 = {1'h0, _io_resp_eff_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_22 = _io_resp_eff_T_21 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_23 = _io_resp_eff_T_22; // @[Parameters.scala:137:46] wire _io_resp_eff_T_24 = _io_resp_eff_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_26 = {1'h0, _io_resp_eff_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_27 = _io_resp_eff_T_26 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_28 = _io_resp_eff_T_27; // @[Parameters.scala:137:46] wire _io_resp_eff_T_29 = _io_resp_eff_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_eff_T_30 = _io_resp_eff_T_4 | _io_resp_eff_T_9; // @[Parameters.scala:629:89] wire _io_resp_eff_T_31 = _io_resp_eff_T_30 | _io_resp_eff_T_14; // @[Parameters.scala:629:89] wire _io_resp_eff_T_32 = _io_resp_eff_T_31 | _io_resp_eff_T_19; // @[Parameters.scala:629:89] wire _io_resp_eff_T_33 = _io_resp_eff_T_32 | _io_resp_eff_T_24; // @[Parameters.scala:629:89] wire _io_resp_eff_T_34 = _io_resp_eff_T_33 | _io_resp_eff_T_29; // @[Parameters.scala:629:89] wire _io_resp_eff_T_58 = _io_resp_eff_T_34; // @[Mux.scala:30:73] wire [40:0] _io_resp_eff_T_36 = {1'h0, _io_resp_eff_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_37 = _io_resp_eff_T_36 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_38 = _io_resp_eff_T_37; // @[Parameters.scala:137:46] wire _io_resp_eff_T_39 = _io_resp_eff_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_41 = {1'h0, _io_resp_eff_T_40}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_42 = _io_resp_eff_T_41 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_43 = _io_resp_eff_T_42; // @[Parameters.scala:137:46] wire _io_resp_eff_T_44 = _io_resp_eff_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_46 = {1'h0, _io_resp_eff_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_47 = _io_resp_eff_T_46 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_48 = _io_resp_eff_T_47; // @[Parameters.scala:137:46] wire _io_resp_eff_T_49 = _io_resp_eff_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_51 = {1'h0, _io_resp_eff_T_50}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_52 = _io_resp_eff_T_51 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_53 = _io_resp_eff_T_52; // @[Parameters.scala:137:46] wire _io_resp_eff_T_54 = _io_resp_eff_T_53 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_eff_T_55 = _io_resp_eff_T_39 | _io_resp_eff_T_44; // @[Parameters.scala:629:89] wire _io_resp_eff_T_56 = _io_resp_eff_T_55 | _io_resp_eff_T_49; // @[Parameters.scala:629:89] wire _io_resp_eff_T_57 = _io_resp_eff_T_56 | _io_resp_eff_T_54; // @[Parameters.scala:629:89] wire _io_resp_eff_T_60 = _io_resp_eff_T_58; // @[Mux.scala:30:73] wire _io_resp_eff_WIRE = _io_resp_eff_T_60; // @[Mux.scala:30:73] assign _io_resp_eff_T_61 = legal_address & _io_resp_eff_WIRE; // @[Mux.scala:30:73] assign io_resp_eff_0 = _io_resp_eff_T_61; // @[PMA.scala:18:7, :39:19] assign io_resp_cacheable = io_resp_cacheable_0; // @[PMA.scala:18:7] assign io_resp_r = io_resp_r_0; // @[PMA.scala:18:7] assign io_resp_w = io_resp_w_0; // @[PMA.scala:18:7] assign io_resp_pp = io_resp_pp_0; // @[PMA.scala:18:7] assign io_resp_al = io_resp_al_0; // @[PMA.scala:18:7] assign io_resp_aa = io_resp_aa_0; // @[PMA.scala:18:7] assign io_resp_x = io_resp_x_0; // @[PMA.scala:18:7] assign io_resp_eff = io_resp_eff_0; // @[PMA.scala:18:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLPLIC : input clock : Clock input reset : Reset output auto : { flip int_in : UInt<1>[1], int_out_7 : UInt<1>[1], int_out_6 : UInt<1>[1], int_out_5 : UInt<1>[1], int_out_4 : UInt<1>[1], int_out_3 : UInt<1>[1], int_out_2 : UInt<1>[1], int_out_1 : UInt<1>[1], int_out_0 : UInt<1>[1], flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_56 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire intnodeIn : UInt<1>[1] invalidate intnodeIn[0] wire intnodeOut : UInt<1>[1] invalidate intnodeOut[0] wire x1_intnodeOut : UInt<1>[1] invalidate x1_intnodeOut[0] wire x1_intnodeOut_1 : UInt<1>[1] invalidate x1_intnodeOut_1[0] wire x1_intnodeOut_2 : UInt<1>[1] invalidate x1_intnodeOut_2[0] wire x1_intnodeOut_3 : UInt<1>[1] invalidate x1_intnodeOut_3[0] wire x1_intnodeOut_4 : UInt<1>[1] invalidate x1_intnodeOut_4[0] wire x1_intnodeOut_5 : UInt<1>[1] invalidate x1_intnodeOut_5[0] wire x1_intnodeOut_6 : UInt<1>[1] invalidate x1_intnodeOut_6[0] connect nodeIn, auto.in connect auto.int_out_0, intnodeOut connect auto.int_out_1, x1_intnodeOut connect auto.int_out_2, x1_intnodeOut_1 connect auto.int_out_3, x1_intnodeOut_2 connect auto.int_out_4, x1_intnodeOut_3 connect auto.int_out_5, x1_intnodeOut_4 connect auto.int_out_6, x1_intnodeOut_5 connect auto.int_out_7, x1_intnodeOut_6 connect intnodeIn, auto.int_in inst gateways_gateway of LevelGateway connect gateways_gateway.clock, clock connect gateways_gateway.reset, reset connect gateways_gateway.io.interrupt, intnodeIn[0] reg priority : UInt<1>[1], clock reg threshold : UInt<1>[8], clock wire _pending_WIRE : UInt<1>[1] connect _pending_WIRE[0], UInt<1>(0h0) regreset pending : UInt<1>[1], clock, reset, _pending_WIRE reg enables_0_0 : UInt<1>, clock reg enables_1_0 : UInt<1>, clock reg enables_2_0 : UInt<1>, clock reg enables_3_0 : UInt<1>, clock reg enables_4_0 : UInt<1>, clock reg enables_5_0 : UInt<1>, clock reg enables_6_0 : UInt<1>, clock reg enables_7_0 : UInt<1>, clock wire enableVec : UInt<1>[8] connect enableVec[0], enables_0_0 connect enableVec[1], enables_1_0 connect enableVec[2], enables_2_0 connect enableVec[3], enables_3_0 connect enableVec[4], enables_4_0 connect enableVec[5], enables_5_0 connect enableVec[6], enables_6_0 connect enableVec[7], enables_7_0 node _enableVec0_T = cat(enableVec[0], UInt<1>(0h0)) node _enableVec0_T_1 = cat(enableVec[1], UInt<1>(0h0)) node _enableVec0_T_2 = cat(enableVec[2], UInt<1>(0h0)) node _enableVec0_T_3 = cat(enableVec[3], UInt<1>(0h0)) node _enableVec0_T_4 = cat(enableVec[4], UInt<1>(0h0)) node _enableVec0_T_5 = cat(enableVec[5], UInt<1>(0h0)) node _enableVec0_T_6 = cat(enableVec[6], UInt<1>(0h0)) node _enableVec0_T_7 = cat(enableVec[7], UInt<1>(0h0)) wire enableVec0 : UInt<2>[8] connect enableVec0[0], _enableVec0_T connect enableVec0[1], _enableVec0_T_1 connect enableVec0[2], _enableVec0_T_2 connect enableVec0[3], _enableVec0_T_3 connect enableVec0[4], _enableVec0_T_4 connect enableVec0[5], _enableVec0_T_5 connect enableVec0[6], _enableVec0_T_6 connect enableVec0[7], _enableVec0_T_7 reg maxDevs : UInt<1>[8], clock inst fanin of PLICFanIn connect fanin.clock, clock connect fanin.reset, reset connect fanin.io.prio[0], priority[0] node _fanin_io_ip_T = and(enableVec[0], pending[0]) connect fanin.io.ip, _fanin_io_ip_T connect maxDevs[0], fanin.io.dev reg intnodeOut_0_REG : UInt, clock connect intnodeOut_0_REG, fanin.io.max node _intnodeOut_0_T = gt(intnodeOut_0_REG, threshold[0]) connect intnodeOut[0], _intnodeOut_0_T inst fanin_1 of PLICFanIn_1 connect fanin_1.clock, clock connect fanin_1.reset, reset connect fanin_1.io.prio[0], priority[0] node _fanin_io_ip_T_1 = and(enableVec[1], pending[0]) connect fanin_1.io.ip, _fanin_io_ip_T_1 connect maxDevs[1], fanin_1.io.dev reg intnodeOut_0_REG_1 : UInt, clock connect intnodeOut_0_REG_1, fanin_1.io.max node _intnodeOut_0_T_1 = gt(intnodeOut_0_REG_1, threshold[1]) connect x1_intnodeOut[0], _intnodeOut_0_T_1 inst fanin_2 of PLICFanIn_2 connect fanin_2.clock, clock connect fanin_2.reset, reset connect fanin_2.io.prio[0], priority[0] node _fanin_io_ip_T_2 = and(enableVec[2], pending[0]) connect fanin_2.io.ip, _fanin_io_ip_T_2 connect maxDevs[2], fanin_2.io.dev reg intnodeOut_0_REG_2 : UInt, clock connect intnodeOut_0_REG_2, fanin_2.io.max node _intnodeOut_0_T_2 = gt(intnodeOut_0_REG_2, threshold[2]) connect x1_intnodeOut_1[0], _intnodeOut_0_T_2 inst fanin_3 of PLICFanIn_3 connect fanin_3.clock, clock connect fanin_3.reset, reset connect fanin_3.io.prio[0], priority[0] node _fanin_io_ip_T_3 = and(enableVec[3], pending[0]) connect fanin_3.io.ip, _fanin_io_ip_T_3 connect maxDevs[3], fanin_3.io.dev reg intnodeOut_0_REG_3 : UInt, clock connect intnodeOut_0_REG_3, fanin_3.io.max node _intnodeOut_0_T_3 = gt(intnodeOut_0_REG_3, threshold[3]) connect x1_intnodeOut_2[0], _intnodeOut_0_T_3 inst fanin_4 of PLICFanIn_4 connect fanin_4.clock, clock connect fanin_4.reset, reset connect fanin_4.io.prio[0], priority[0] node _fanin_io_ip_T_4 = and(enableVec[4], pending[0]) connect fanin_4.io.ip, _fanin_io_ip_T_4 connect maxDevs[4], fanin_4.io.dev reg intnodeOut_0_REG_4 : UInt, clock connect intnodeOut_0_REG_4, fanin_4.io.max node _intnodeOut_0_T_4 = gt(intnodeOut_0_REG_4, threshold[4]) connect x1_intnodeOut_3[0], _intnodeOut_0_T_4 inst fanin_5 of PLICFanIn_5 connect fanin_5.clock, clock connect fanin_5.reset, reset connect fanin_5.io.prio[0], priority[0] node _fanin_io_ip_T_5 = and(enableVec[5], pending[0]) connect fanin_5.io.ip, _fanin_io_ip_T_5 connect maxDevs[5], fanin_5.io.dev reg intnodeOut_0_REG_5 : UInt, clock connect intnodeOut_0_REG_5, fanin_5.io.max node _intnodeOut_0_T_5 = gt(intnodeOut_0_REG_5, threshold[5]) connect x1_intnodeOut_4[0], _intnodeOut_0_T_5 inst fanin_6 of PLICFanIn_6 connect fanin_6.clock, clock connect fanin_6.reset, reset connect fanin_6.io.prio[0], priority[0] node _fanin_io_ip_T_6 = and(enableVec[6], pending[0]) connect fanin_6.io.ip, _fanin_io_ip_T_6 connect maxDevs[6], fanin_6.io.dev reg intnodeOut_0_REG_6 : UInt, clock connect intnodeOut_0_REG_6, fanin_6.io.max node _intnodeOut_0_T_6 = gt(intnodeOut_0_REG_6, threshold[6]) connect x1_intnodeOut_5[0], _intnodeOut_0_T_6 inst fanin_7 of PLICFanIn_7 connect fanin_7.clock, clock connect fanin_7.reset, reset connect fanin_7.io.prio[0], priority[0] node _fanin_io_ip_T_7 = and(enableVec[7], pending[0]) connect fanin_7.io.ip, _fanin_io_ip_T_7 connect maxDevs[7], fanin_7.io.dev reg intnodeOut_0_REG_7 : UInt, clock connect intnodeOut_0_REG_7, fanin_7.io.max node _intnodeOut_0_T_7 = gt(intnodeOut_0_REG_7, threshold[7]) connect x1_intnodeOut_6[0], _intnodeOut_0_T_7 wire claimer : UInt<1>[8] node lo_lo = cat(claimer[1], claimer[0]) node lo_hi = cat(claimer[3], claimer[2]) node lo = cat(lo_hi, lo_lo) node hi_lo = cat(claimer[5], claimer[4]) node hi_hi = cat(claimer[7], claimer[6]) node hi = cat(hi_hi, hi_lo) node _T = cat(hi, lo) node lo_lo_1 = cat(claimer[1], claimer[0]) node lo_hi_1 = cat(claimer[3], claimer[2]) node lo_1 = cat(lo_hi_1, lo_lo_1) node hi_lo_1 = cat(claimer[5], claimer[4]) node hi_hi_1 = cat(claimer[7], claimer[6]) node hi_1 = cat(hi_hi_1, hi_lo_1) node _T_1 = cat(hi_1, lo_1) node _T_2 = sub(_T_1, UInt<1>(0h1)) node _T_3 = tail(_T_2, 1) node _T_4 = and(_T, _T_3) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = asUInt(reset) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(_T_5, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Plic.scala:251 assert((claimer.asUInt & (claimer.asUInt - 1.U)) === 0.U) // One-Hot\n") : printf assert(clock, _T_5, UInt<1>(0h1), "") : assert node _claiming_T = mux(claimer[0], maxDevs[0], UInt<1>(0h0)) node _claiming_T_1 = mux(claimer[1], maxDevs[1], UInt<1>(0h0)) node _claiming_T_2 = mux(claimer[2], maxDevs[2], UInt<1>(0h0)) node _claiming_T_3 = mux(claimer[3], maxDevs[3], UInt<1>(0h0)) node _claiming_T_4 = mux(claimer[4], maxDevs[4], UInt<1>(0h0)) node _claiming_T_5 = mux(claimer[5], maxDevs[5], UInt<1>(0h0)) node _claiming_T_6 = mux(claimer[6], maxDevs[6], UInt<1>(0h0)) node _claiming_T_7 = mux(claimer[7], maxDevs[7], UInt<1>(0h0)) node _claiming_T_8 = or(_claiming_T, _claiming_T_1) node _claiming_T_9 = or(_claiming_T_8, _claiming_T_2) node _claiming_T_10 = or(_claiming_T_9, _claiming_T_3) node _claiming_T_11 = or(_claiming_T_10, _claiming_T_4) node _claiming_T_12 = or(_claiming_T_11, _claiming_T_5) node _claiming_T_13 = or(_claiming_T_12, _claiming_T_6) node claiming = or(_claiming_T_13, _claiming_T_7) node claimedDevs_shiftAmount = bits(claiming, 0, 0) node _claimedDevs_T = dshl(UInt<1>(0h1), claimedDevs_shiftAmount) node _claimedDevs_T_1 = bits(_claimedDevs_T, 1, 0) node _claimedDevs_T_2 = bits(_claimedDevs_T_1, 0, 0) node _claimedDevs_T_3 = bits(_claimedDevs_T_1, 1, 1) wire claimedDevs : UInt<1>[2] connect claimedDevs[0], _claimedDevs_T_2 connect claimedDevs[1], _claimedDevs_T_3 node _gateway_io_plic_ready_T = eq(pending[0], UInt<1>(0h0)) connect gateways_gateway.io.plic.ready, _gateway_io_plic_ready_T node _T_9 = or(claimedDevs[1], gateways_gateway.io.plic.valid) when _T_9 : node _pending_0_T = eq(claimedDevs[1], UInt<1>(0h0)) connect pending[0], _pending_0_T wire completer : UInt<1>[8] node lo_lo_2 = cat(completer[1], completer[0]) node lo_hi_2 = cat(completer[3], completer[2]) node lo_2 = cat(lo_hi_2, lo_lo_2) node hi_lo_2 = cat(completer[5], completer[4]) node hi_hi_2 = cat(completer[7], completer[6]) node hi_2 = cat(hi_hi_2, hi_lo_2) node _T_10 = cat(hi_2, lo_2) node lo_lo_3 = cat(completer[1], completer[0]) node lo_hi_3 = cat(completer[3], completer[2]) node lo_3 = cat(lo_hi_3, lo_lo_3) node hi_lo_3 = cat(completer[5], completer[4]) node hi_hi_3 = cat(completer[7], completer[6]) node hi_3 = cat(hi_hi_3, hi_lo_3) node _T_11 = cat(hi_3, lo_3) node _T_12 = sub(_T_11, UInt<1>(0h1)) node _T_13 = tail(_T_12, 1) node _T_14 = and(_T_10, _T_13) node _T_15 = eq(_T_14, UInt<1>(0h0)) node _T_16 = asUInt(reset) node _T_17 = eq(_T_16, UInt<1>(0h0)) when _T_17 : node _T_18 = eq(_T_15, UInt<1>(0h0)) when _T_18 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Plic.scala:268 assert((completer.asUInt & (completer.asUInt - 1.U)) === 0.U) // One-Hot\n") : printf_1 assert(clock, _T_15, UInt<1>(0h1), "") : assert_1 wire completerDev : UInt<1> node _completedDevs_T = or(completer[0], completer[1]) node _completedDevs_T_1 = or(_completedDevs_T, completer[2]) node _completedDevs_T_2 = or(_completedDevs_T_1, completer[3]) node _completedDevs_T_3 = or(_completedDevs_T_2, completer[4]) node _completedDevs_T_4 = or(_completedDevs_T_3, completer[5]) node _completedDevs_T_5 = or(_completedDevs_T_4, completer[6]) node _completedDevs_T_6 = or(_completedDevs_T_5, completer[7]) node completedDevs_shiftAmount = bits(completerDev, 0, 0) node _completedDevs_T_7 = dshl(UInt<1>(0h1), completedDevs_shiftAmount) node _completedDevs_T_8 = bits(_completedDevs_T_7, 1, 0) node completedDevs = mux(_completedDevs_T_6, _completedDevs_T_8, UInt<1>(0h0)) node _T_19 = bits(completedDevs, 0, 0) node _T_20 = bits(completedDevs, 1, 1) connect gateways_gateway.io.plic.complete, _T_20 wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<23>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} node _in_bits_read_T = eq(nodeIn.a.bits.opcode, UInt<3>(0h4)) connect in.bits.read, _in_bits_read_T node _in_bits_index_T = shr(nodeIn.a.bits.address, 3) connect in.bits.index, _in_bits_index_T connect in.bits.data, nodeIn.a.bits.data connect in.bits.mask, nodeIn.a.bits.mask connect in.bits.extra.tlrr_extra.source, nodeIn.a.bits.source connect in.bits.extra.tlrr_extra.size, nodeIn.a.bits.size wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<23>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} connect out_front.bits, in.bits inst out_back_front_q of Queue1_RegMapperInput_i23_m8 connect out_back_front_q.clock, clock connect out_back_front_q.reset, reset connect out_back_front_q.io.enq, out_front node out_maskMatch = not(UInt<23>(0h40e70)) node out_findex = and(out_front.bits.index, out_maskMatch) node out_bindex = and(out_back_front_q.io.deq.bits.index, out_maskMatch) node _out_T = eq(out_findex, UInt<23>(0h0)) node _out_T_1 = eq(out_bindex, UInt<23>(0h0)) node _out_T_2 = eq(out_findex, UInt<23>(0h0)) node _out_T_3 = eq(out_bindex, UInt<23>(0h0)) node _out_T_4 = eq(out_findex, UInt<23>(0h0)) node _out_T_5 = eq(out_bindex, UInt<23>(0h0)) node _out_T_6 = eq(out_findex, UInt<23>(0h0)) node _out_T_7 = eq(out_bindex, UInt<23>(0h0)) node _out_T_8 = eq(out_findex, UInt<23>(0h0)) node _out_T_9 = eq(out_bindex, UInt<23>(0h0)) node _out_T_10 = eq(out_findex, UInt<23>(0h0)) node _out_T_11 = eq(out_bindex, UInt<23>(0h0)) node _out_T_12 = eq(out_findex, UInt<23>(0h0)) node _out_T_13 = eq(out_bindex, UInt<23>(0h0)) node _out_T_14 = eq(out_findex, UInt<23>(0h0)) node _out_T_15 = eq(out_bindex, UInt<23>(0h0)) node _out_T_16 = eq(out_findex, UInt<23>(0h0)) node _out_T_17 = eq(out_bindex, UInt<23>(0h0)) node _out_T_18 = eq(out_findex, UInt<23>(0h0)) node _out_T_19 = eq(out_bindex, UInt<23>(0h0)) node _out_T_20 = eq(out_findex, UInt<23>(0h0)) node _out_T_21 = eq(out_bindex, UInt<23>(0h0)) node _out_T_22 = eq(out_findex, UInt<23>(0h0)) node _out_T_23 = eq(out_bindex, UInt<23>(0h0)) node _out_T_24 = eq(out_findex, UInt<23>(0h0)) node _out_T_25 = eq(out_bindex, UInt<23>(0h0)) node _out_T_26 = eq(out_findex, UInt<23>(0h0)) node _out_T_27 = eq(out_bindex, UInt<23>(0h0)) node _out_T_28 = eq(out_findex, UInt<23>(0h0)) node _out_T_29 = eq(out_bindex, UInt<23>(0h0)) node _out_T_30 = eq(out_findex, UInt<23>(0h0)) node _out_T_31 = eq(out_bindex, UInt<23>(0h0)) node _out_T_32 = eq(out_findex, UInt<23>(0h0)) node _out_T_33 = eq(out_bindex, UInt<23>(0h0)) node _out_T_34 = eq(out_findex, UInt<23>(0h0)) node _out_T_35 = eq(out_bindex, UInt<23>(0h0)) wire out_rivalid : UInt<1>[43] wire out_wivalid : UInt<1>[43] wire out_roready : UInt<1>[43] wire out_woready : UInt<1>[43] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) node _out_backMask_T = bits(out_back_front_q.io.deq.bits.mask, 0, 0) node _out_backMask_T_1 = bits(out_back_front_q.io.deq.bits.mask, 1, 1) node _out_backMask_T_2 = bits(out_back_front_q.io.deq.bits.mask, 2, 2) node _out_backMask_T_3 = bits(out_back_front_q.io.deq.bits.mask, 3, 3) node _out_backMask_T_4 = bits(out_back_front_q.io.deq.bits.mask, 4, 4) node _out_backMask_T_5 = bits(out_back_front_q.io.deq.bits.mask, 5, 5) node _out_backMask_T_6 = bits(out_back_front_q.io.deq.bits.mask, 6, 6) node _out_backMask_T_7 = bits(out_back_front_q.io.deq.bits.mask, 7, 7) node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) node out_backMask = cat(out_backMask_hi, out_backMask_lo) node _out_rimask_T = bits(out_frontMask, 0, 0) node out_rimask = orr(_out_rimask_T) node _out_wimask_T = bits(out_frontMask, 0, 0) node out_wimask = andr(_out_wimask_T) node _out_romask_T = bits(out_backMask, 0, 0) node out_romask = orr(_out_romask_T) node _out_womask_T = bits(out_backMask, 0, 0) node out_womask = andr(_out_womask_T) node out_f_rivalid = and(out_rivalid[0], out_rimask) node out_f_roready = and(out_roready[0], out_romask) node out_f_wivalid = and(out_wivalid[0], out_wimask) node out_f_woready = and(out_woready[0], out_womask) node _out_T_36 = bits(out_back_front_q.io.deq.bits.data, 0, 0) when out_f_woready : connect threshold[5], _out_T_36 node _out_T_37 = and(out_f_rivalid, UInt<1>(0h1)) node _out_T_38 = and(UInt<1>(0h1), out_f_roready) node _out_T_39 = and(out_f_wivalid, UInt<1>(0h1)) node _out_T_40 = and(UInt<1>(0h1), out_f_woready) node _out_T_41 = eq(out_rimask, UInt<1>(0h0)) node _out_T_42 = eq(out_wimask, UInt<1>(0h0)) node _out_T_43 = eq(out_romask, UInt<1>(0h0)) node _out_T_44 = eq(out_womask, UInt<1>(0h0)) node _out_T_45 = or(threshold[5], UInt<1>(0h0)) node _out_T_46 = bits(_out_T_45, 0, 0) node _out_rimask_T_1 = bits(out_frontMask, 31, 1) node out_rimask_1 = orr(_out_rimask_T_1) node _out_wimask_T_1 = bits(out_frontMask, 31, 1) node out_wimask_1 = andr(_out_wimask_T_1) node _out_romask_T_1 = bits(out_backMask, 31, 1) node out_romask_1 = orr(_out_romask_T_1) node _out_womask_T_1 = bits(out_backMask, 31, 1) node out_womask_1 = andr(_out_womask_T_1) node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1) node out_f_roready_1 = and(out_roready[1], out_romask_1) node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1) node out_f_woready_1 = and(out_woready[1], out_womask_1) node _out_T_47 = bits(out_back_front_q.io.deq.bits.data, 31, 1) node _out_T_48 = and(out_f_rivalid_1, UInt<1>(0h1)) node _out_T_49 = and(UInt<1>(0h1), out_f_roready_1) node _out_T_50 = eq(out_rimask_1, UInt<1>(0h0)) node _out_T_51 = eq(out_wimask_1, UInt<1>(0h0)) node _out_T_52 = eq(out_romask_1, UInt<1>(0h0)) node _out_T_53 = eq(out_womask_1, UInt<1>(0h0)) node _out_prepend_T = or(_out_T_46, UInt<1>(0h0)) node out_prepend = cat(UInt<1>(0h0), _out_prepend_T) node _out_T_54 = or(out_prepend, UInt<32>(0h0)) node _out_T_55 = bits(_out_T_54, 31, 0) node _out_rimask_T_2 = bits(out_frontMask, 63, 32) node out_rimask_2 = orr(_out_rimask_T_2) node _out_wimask_T_2 = bits(out_frontMask, 63, 32) node out_wimask_2 = andr(_out_wimask_T_2) node _out_romask_T_2 = bits(out_backMask, 63, 32) node out_romask_2 = orr(_out_romask_T_2) node _out_womask_T_2 = bits(out_backMask, 63, 32) node out_womask_2 = andr(_out_womask_T_2) node out_f_rivalid_2 = and(out_rivalid[2], out_rimask_2) node out_f_roready_2 = and(out_roready[2], out_romask_2) node out_f_wivalid_2 = and(out_wivalid[2], out_wimask_2) node out_f_woready_2 = and(out_woready[2], out_womask_2) connect claimer[5], out_f_roready_2 node _out_T_56 = bits(out_back_front_q.io.deq.bits.data, 63, 32) node _out_T_57 = bits(_out_T_56, 0, 0) node _out_T_58 = eq(completerDev, _out_T_57) node _out_T_59 = asUInt(reset) node _out_T_60 = eq(_out_T_59, UInt<1>(0h0)) when _out_T_60 : node _out_T_61 = eq(_out_T_58, UInt<1>(0h0)) when _out_T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: completerDev should be consistent for all harts\n at Plic.scala:298 assert(completerDev === data.extract(log2Ceil(nDevices+1)-1, 0),\n") : out_printf assert(clock, _out_T_58, UInt<1>(0h1), "") : out_assert node _out_completerDev_T = bits(_out_T_56, 0, 0) connect completerDev, _out_completerDev_T node _out_completer_5_T = dshr(enableVec0[5], completerDev) node _out_completer_5_T_1 = bits(_out_completer_5_T, 0, 0) node _out_completer_5_T_2 = and(out_f_woready_2, _out_completer_5_T_1) connect completer[5], _out_completer_5_T_2 node _out_T_62 = and(out_f_rivalid_2, UInt<1>(0h1)) node _out_T_63 = and(UInt<1>(0h1), out_f_roready_2) node _out_T_64 = and(out_f_wivalid_2, UInt<1>(0h1)) node _out_T_65 = and(UInt<1>(0h1), out_f_woready_2) node _out_T_66 = eq(out_rimask_2, UInt<1>(0h0)) node _out_T_67 = eq(out_wimask_2, UInt<1>(0h0)) node _out_T_68 = eq(out_romask_2, UInt<1>(0h0)) node _out_T_69 = eq(out_womask_2, UInt<1>(0h0)) node _out_prepend_T_1 = or(_out_T_55, UInt<32>(0h0)) node out_prepend_1 = cat(maxDevs[5], _out_prepend_T_1) node _out_T_70 = or(out_prepend_1, UInt<64>(0h0)) node _out_T_71 = bits(_out_T_70, 63, 0) node _out_rimask_T_3 = bits(out_frontMask, 0, 0) node out_rimask_3 = orr(_out_rimask_T_3) node _out_wimask_T_3 = bits(out_frontMask, 0, 0) node out_wimask_3 = andr(_out_wimask_T_3) node _out_romask_T_3 = bits(out_backMask, 0, 0) node out_romask_3 = orr(_out_romask_T_3) node _out_womask_T_3 = bits(out_backMask, 0, 0) node out_womask_3 = andr(_out_womask_T_3) node out_f_rivalid_3 = and(out_rivalid[3], out_rimask_3) node out_f_roready_3 = and(out_roready[3], out_romask_3) node out_f_wivalid_3 = and(out_wivalid[3], out_wimask_3) node out_f_woready_3 = and(out_woready[3], out_womask_3) node _out_T_72 = bits(out_back_front_q.io.deq.bits.data, 0, 0) node _out_T_73 = and(out_f_rivalid_3, UInt<1>(0h1)) node _out_T_74 = and(UInt<1>(0h1), out_f_roready_3) node _out_T_75 = eq(out_rimask_3, UInt<1>(0h0)) node _out_T_76 = eq(out_wimask_3, UInt<1>(0h0)) node _out_T_77 = eq(out_romask_3, UInt<1>(0h0)) node _out_T_78 = eq(out_womask_3, UInt<1>(0h0)) node _out_T_79 = or(UInt<1>(0h0), UInt<1>(0h0)) node _out_T_80 = bits(_out_T_79, 0, 0) node _out_rimask_T_4 = bits(out_frontMask, 1, 1) node out_rimask_4 = orr(_out_rimask_T_4) node _out_wimask_T_4 = bits(out_frontMask, 1, 1) node out_wimask_4 = andr(_out_wimask_T_4) node _out_romask_T_4 = bits(out_backMask, 1, 1) node out_romask_4 = orr(_out_romask_T_4) node _out_womask_T_4 = bits(out_backMask, 1, 1) node out_womask_4 = andr(_out_womask_T_4) node out_f_rivalid_4 = and(out_rivalid[4], out_rimask_4) node out_f_roready_4 = and(out_roready[4], out_romask_4) node out_f_wivalid_4 = and(out_wivalid[4], out_wimask_4) node out_f_woready_4 = and(out_woready[4], out_womask_4) node _out_T_81 = bits(out_back_front_q.io.deq.bits.data, 1, 1) node _out_T_82 = and(out_f_rivalid_4, UInt<1>(0h1)) node _out_T_83 = and(UInt<1>(0h1), out_f_roready_4) node _out_T_84 = eq(out_rimask_4, UInt<1>(0h0)) node _out_T_85 = eq(out_wimask_4, UInt<1>(0h0)) node _out_T_86 = eq(out_romask_4, UInt<1>(0h0)) node _out_T_87 = eq(out_womask_4, UInt<1>(0h0)) node _out_prepend_T_2 = or(_out_T_80, UInt<1>(0h0)) node out_prepend_2 = cat(pending[0], _out_prepend_T_2) node _out_T_88 = or(out_prepend_2, UInt<2>(0h0)) node _out_T_89 = bits(_out_T_88, 1, 0) node _out_rimask_T_5 = bits(out_frontMask, 0, 0) node out_rimask_5 = orr(_out_rimask_T_5) node _out_wimask_T_5 = bits(out_frontMask, 0, 0) node out_wimask_5 = andr(_out_wimask_T_5) node _out_romask_T_5 = bits(out_backMask, 0, 0) node out_romask_5 = orr(_out_romask_T_5) node _out_womask_T_5 = bits(out_backMask, 0, 0) node out_womask_5 = andr(_out_womask_T_5) node out_f_rivalid_5 = and(out_rivalid[5], out_rimask_5) node out_f_roready_5 = and(out_roready[5], out_romask_5) node out_f_wivalid_5 = and(out_wivalid[5], out_wimask_5) node out_f_woready_5 = and(out_woready[5], out_womask_5) node _out_T_90 = bits(out_back_front_q.io.deq.bits.data, 0, 0) when out_f_woready_5 : connect threshold[4], _out_T_90 node _out_T_91 = and(out_f_rivalid_5, UInt<1>(0h1)) node _out_T_92 = and(UInt<1>(0h1), out_f_roready_5) node _out_T_93 = and(out_f_wivalid_5, UInt<1>(0h1)) node _out_T_94 = and(UInt<1>(0h1), out_f_woready_5) node _out_T_95 = eq(out_rimask_5, UInt<1>(0h0)) node _out_T_96 = eq(out_wimask_5, UInt<1>(0h0)) node _out_T_97 = eq(out_romask_5, UInt<1>(0h0)) node _out_T_98 = eq(out_womask_5, UInt<1>(0h0)) node _out_T_99 = or(threshold[4], UInt<1>(0h0)) node _out_T_100 = bits(_out_T_99, 0, 0) node _out_rimask_T_6 = bits(out_frontMask, 31, 1) node out_rimask_6 = orr(_out_rimask_T_6) node _out_wimask_T_6 = bits(out_frontMask, 31, 1) node out_wimask_6 = andr(_out_wimask_T_6) node _out_romask_T_6 = bits(out_backMask, 31, 1) node out_romask_6 = orr(_out_romask_T_6) node _out_womask_T_6 = bits(out_backMask, 31, 1) node out_womask_6 = andr(_out_womask_T_6) node out_f_rivalid_6 = and(out_rivalid[6], out_rimask_6) node out_f_roready_6 = and(out_roready[6], out_romask_6) node out_f_wivalid_6 = and(out_wivalid[6], out_wimask_6) node out_f_woready_6 = and(out_woready[6], out_womask_6) node _out_T_101 = bits(out_back_front_q.io.deq.bits.data, 31, 1) node _out_T_102 = and(out_f_rivalid_6, UInt<1>(0h1)) node _out_T_103 = and(UInt<1>(0h1), out_f_roready_6) node _out_T_104 = eq(out_rimask_6, UInt<1>(0h0)) node _out_T_105 = eq(out_wimask_6, UInt<1>(0h0)) node _out_T_106 = eq(out_romask_6, UInt<1>(0h0)) node _out_T_107 = eq(out_womask_6, UInt<1>(0h0)) node _out_prepend_T_3 = or(_out_T_100, UInt<1>(0h0)) node out_prepend_3 = cat(UInt<1>(0h0), _out_prepend_T_3) node _out_T_108 = or(out_prepend_3, UInt<32>(0h0)) node _out_T_109 = bits(_out_T_108, 31, 0) node _out_rimask_T_7 = bits(out_frontMask, 63, 32) node out_rimask_7 = orr(_out_rimask_T_7) node _out_wimask_T_7 = bits(out_frontMask, 63, 32) node out_wimask_7 = andr(_out_wimask_T_7) node _out_romask_T_7 = bits(out_backMask, 63, 32) node out_romask_7 = orr(_out_romask_T_7) node _out_womask_T_7 = bits(out_backMask, 63, 32) node out_womask_7 = andr(_out_womask_T_7) node out_f_rivalid_7 = and(out_rivalid[7], out_rimask_7) node out_f_roready_7 = and(out_roready[7], out_romask_7) node out_f_wivalid_7 = and(out_wivalid[7], out_wimask_7) node out_f_woready_7 = and(out_woready[7], out_womask_7) connect claimer[4], out_f_roready_7 node _out_T_110 = bits(out_back_front_q.io.deq.bits.data, 63, 32) node _out_T_111 = bits(_out_T_110, 0, 0) node _out_T_112 = eq(completerDev, _out_T_111) node _out_T_113 = asUInt(reset) node _out_T_114 = eq(_out_T_113, UInt<1>(0h0)) when _out_T_114 : node _out_T_115 = eq(_out_T_112, UInt<1>(0h0)) when _out_T_115 : printf(clock, UInt<1>(0h1), "Assertion failed: completerDev should be consistent for all harts\n at Plic.scala:298 assert(completerDev === data.extract(log2Ceil(nDevices+1)-1, 0),\n") : out_printf_1 assert(clock, _out_T_112, UInt<1>(0h1), "") : out_assert_1 node _out_completerDev_T_1 = bits(_out_T_110, 0, 0) connect completerDev, _out_completerDev_T_1 node _out_completer_4_T = dshr(enableVec0[4], completerDev) node _out_completer_4_T_1 = bits(_out_completer_4_T, 0, 0) node _out_completer_4_T_2 = and(out_f_woready_7, _out_completer_4_T_1) connect completer[4], _out_completer_4_T_2 node _out_T_116 = and(out_f_rivalid_7, UInt<1>(0h1)) node _out_T_117 = and(UInt<1>(0h1), out_f_roready_7) node _out_T_118 = and(out_f_wivalid_7, UInt<1>(0h1)) node _out_T_119 = and(UInt<1>(0h1), out_f_woready_7) node _out_T_120 = eq(out_rimask_7, UInt<1>(0h0)) node _out_T_121 = eq(out_wimask_7, UInt<1>(0h0)) node _out_T_122 = eq(out_romask_7, UInt<1>(0h0)) node _out_T_123 = eq(out_womask_7, UInt<1>(0h0)) node _out_prepend_T_4 = or(_out_T_109, UInt<32>(0h0)) node out_prepend_4 = cat(maxDevs[4], _out_prepend_T_4) node _out_T_124 = or(out_prepend_4, UInt<64>(0h0)) node _out_T_125 = bits(_out_T_124, 63, 0) node _out_rimask_T_8 = bits(out_frontMask, 0, 0) node out_rimask_8 = orr(_out_rimask_T_8) node _out_wimask_T_8 = bits(out_frontMask, 0, 0) node out_wimask_8 = andr(_out_wimask_T_8) node _out_romask_T_8 = bits(out_backMask, 0, 0) node out_romask_8 = orr(_out_romask_T_8) node _out_womask_T_8 = bits(out_backMask, 0, 0) node out_womask_8 = andr(_out_womask_T_8) node out_f_rivalid_8 = and(out_rivalid[8], out_rimask_8) node out_f_roready_8 = and(out_roready[8], out_romask_8) node out_f_wivalid_8 = and(out_wivalid[8], out_wimask_8) node out_f_woready_8 = and(out_woready[8], out_womask_8) node _out_T_126 = bits(out_back_front_q.io.deq.bits.data, 0, 0) when out_f_woready_8 : connect threshold[1], _out_T_126 node _out_T_127 = and(out_f_rivalid_8, UInt<1>(0h1)) node _out_T_128 = and(UInt<1>(0h1), out_f_roready_8) node _out_T_129 = and(out_f_wivalid_8, UInt<1>(0h1)) node _out_T_130 = and(UInt<1>(0h1), out_f_woready_8) node _out_T_131 = eq(out_rimask_8, UInt<1>(0h0)) node _out_T_132 = eq(out_wimask_8, UInt<1>(0h0)) node _out_T_133 = eq(out_romask_8, UInt<1>(0h0)) node _out_T_134 = eq(out_womask_8, UInt<1>(0h0)) node _out_T_135 = or(threshold[1], UInt<1>(0h0)) node _out_T_136 = bits(_out_T_135, 0, 0) node _out_rimask_T_9 = bits(out_frontMask, 31, 1) node out_rimask_9 = orr(_out_rimask_T_9) node _out_wimask_T_9 = bits(out_frontMask, 31, 1) node out_wimask_9 = andr(_out_wimask_T_9) node _out_romask_T_9 = bits(out_backMask, 31, 1) node out_romask_9 = orr(_out_romask_T_9) node _out_womask_T_9 = bits(out_backMask, 31, 1) node out_womask_9 = andr(_out_womask_T_9) node out_f_rivalid_9 = and(out_rivalid[9], out_rimask_9) node out_f_roready_9 = and(out_roready[9], out_romask_9) node out_f_wivalid_9 = and(out_wivalid[9], out_wimask_9) node out_f_woready_9 = and(out_woready[9], out_womask_9) node _out_T_137 = bits(out_back_front_q.io.deq.bits.data, 31, 1) node _out_T_138 = and(out_f_rivalid_9, UInt<1>(0h1)) node _out_T_139 = and(UInt<1>(0h1), out_f_roready_9) node _out_T_140 = eq(out_rimask_9, UInt<1>(0h0)) node _out_T_141 = eq(out_wimask_9, UInt<1>(0h0)) node _out_T_142 = eq(out_romask_9, UInt<1>(0h0)) node _out_T_143 = eq(out_womask_9, UInt<1>(0h0)) node _out_prepend_T_5 = or(_out_T_136, UInt<1>(0h0)) node out_prepend_5 = cat(UInt<1>(0h0), _out_prepend_T_5) node _out_T_144 = or(out_prepend_5, UInt<32>(0h0)) node _out_T_145 = bits(_out_T_144, 31, 0) node _out_rimask_T_10 = bits(out_frontMask, 63, 32) node out_rimask_10 = orr(_out_rimask_T_10) node _out_wimask_T_10 = bits(out_frontMask, 63, 32) node out_wimask_10 = andr(_out_wimask_T_10) node _out_romask_T_10 = bits(out_backMask, 63, 32) node out_romask_10 = orr(_out_romask_T_10) node _out_womask_T_10 = bits(out_backMask, 63, 32) node out_womask_10 = andr(_out_womask_T_10) node out_f_rivalid_10 = and(out_rivalid[10], out_rimask_10) node out_f_roready_10 = and(out_roready[10], out_romask_10) node out_f_wivalid_10 = and(out_wivalid[10], out_wimask_10) node out_f_woready_10 = and(out_woready[10], out_womask_10) connect claimer[1], out_f_roready_10 node _out_T_146 = bits(out_back_front_q.io.deq.bits.data, 63, 32) node _out_T_147 = bits(_out_T_146, 0, 0) node _out_T_148 = eq(completerDev, _out_T_147) node _out_T_149 = asUInt(reset) node _out_T_150 = eq(_out_T_149, UInt<1>(0h0)) when _out_T_150 : node _out_T_151 = eq(_out_T_148, UInt<1>(0h0)) when _out_T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: completerDev should be consistent for all harts\n at Plic.scala:298 assert(completerDev === data.extract(log2Ceil(nDevices+1)-1, 0),\n") : out_printf_2 assert(clock, _out_T_148, UInt<1>(0h1), "") : out_assert_2 node _out_completerDev_T_2 = bits(_out_T_146, 0, 0) connect completerDev, _out_completerDev_T_2 node _out_completer_1_T = dshr(enableVec0[1], completerDev) node _out_completer_1_T_1 = bits(_out_completer_1_T, 0, 0) node _out_completer_1_T_2 = and(out_f_woready_10, _out_completer_1_T_1) connect completer[1], _out_completer_1_T_2 node _out_T_152 = and(out_f_rivalid_10, UInt<1>(0h1)) node _out_T_153 = and(UInt<1>(0h1), out_f_roready_10) node _out_T_154 = and(out_f_wivalid_10, UInt<1>(0h1)) node _out_T_155 = and(UInt<1>(0h1), out_f_woready_10) node _out_T_156 = eq(out_rimask_10, UInt<1>(0h0)) node _out_T_157 = eq(out_wimask_10, UInt<1>(0h0)) node _out_T_158 = eq(out_romask_10, UInt<1>(0h0)) node _out_T_159 = eq(out_womask_10, UInt<1>(0h0)) node _out_prepend_T_6 = or(_out_T_145, UInt<32>(0h0)) node out_prepend_6 = cat(maxDevs[1], _out_prepend_T_6) node _out_T_160 = or(out_prepend_6, UInt<64>(0h0)) node _out_T_161 = bits(_out_T_160, 63, 0) node _out_rimask_T_11 = bits(out_frontMask, 0, 0) node out_rimask_11 = orr(_out_rimask_T_11) node _out_wimask_T_11 = bits(out_frontMask, 0, 0) node out_wimask_11 = andr(_out_wimask_T_11) node _out_romask_T_11 = bits(out_backMask, 0, 0) node out_romask_11 = orr(_out_romask_T_11) node _out_womask_T_11 = bits(out_backMask, 0, 0) node out_womask_11 = andr(_out_womask_T_11) node out_f_rivalid_11 = and(out_rivalid[11], out_rimask_11) node out_f_roready_11 = and(out_roready[11], out_romask_11) node out_f_wivalid_11 = and(out_wivalid[11], out_wimask_11) node out_f_woready_11 = and(out_woready[11], out_womask_11) node _out_T_162 = bits(out_back_front_q.io.deq.bits.data, 0, 0) when out_f_woready_11 : connect threshold[3], _out_T_162 node _out_T_163 = and(out_f_rivalid_11, UInt<1>(0h1)) node _out_T_164 = and(UInt<1>(0h1), out_f_roready_11) node _out_T_165 = and(out_f_wivalid_11, UInt<1>(0h1)) node _out_T_166 = and(UInt<1>(0h1), out_f_woready_11) node _out_T_167 = eq(out_rimask_11, UInt<1>(0h0)) node _out_T_168 = eq(out_wimask_11, UInt<1>(0h0)) node _out_T_169 = eq(out_romask_11, UInt<1>(0h0)) node _out_T_170 = eq(out_womask_11, UInt<1>(0h0)) node _out_T_171 = or(threshold[3], UInt<1>(0h0)) node _out_T_172 = bits(_out_T_171, 0, 0) node _out_rimask_T_12 = bits(out_frontMask, 31, 1) node out_rimask_12 = orr(_out_rimask_T_12) node _out_wimask_T_12 = bits(out_frontMask, 31, 1) node out_wimask_12 = andr(_out_wimask_T_12) node _out_romask_T_12 = bits(out_backMask, 31, 1) node out_romask_12 = orr(_out_romask_T_12) node _out_womask_T_12 = bits(out_backMask, 31, 1) node out_womask_12 = andr(_out_womask_T_12) node out_f_rivalid_12 = and(out_rivalid[12], out_rimask_12) node out_f_roready_12 = and(out_roready[12], out_romask_12) node out_f_wivalid_12 = and(out_wivalid[12], out_wimask_12) node out_f_woready_12 = and(out_woready[12], out_womask_12) node _out_T_173 = bits(out_back_front_q.io.deq.bits.data, 31, 1) node _out_T_174 = and(out_f_rivalid_12, UInt<1>(0h1)) node _out_T_175 = and(UInt<1>(0h1), out_f_roready_12) node _out_T_176 = eq(out_rimask_12, UInt<1>(0h0)) node _out_T_177 = eq(out_wimask_12, UInt<1>(0h0)) node _out_T_178 = eq(out_romask_12, UInt<1>(0h0)) node _out_T_179 = eq(out_womask_12, UInt<1>(0h0)) node _out_prepend_T_7 = or(_out_T_172, UInt<1>(0h0)) node out_prepend_7 = cat(UInt<1>(0h0), _out_prepend_T_7) node _out_T_180 = or(out_prepend_7, UInt<32>(0h0)) node _out_T_181 = bits(_out_T_180, 31, 0) node _out_rimask_T_13 = bits(out_frontMask, 63, 32) node out_rimask_13 = orr(_out_rimask_T_13) node _out_wimask_T_13 = bits(out_frontMask, 63, 32) node out_wimask_13 = andr(_out_wimask_T_13) node _out_romask_T_13 = bits(out_backMask, 63, 32) node out_romask_13 = orr(_out_romask_T_13) node _out_womask_T_13 = bits(out_backMask, 63, 32) node out_womask_13 = andr(_out_womask_T_13) node out_f_rivalid_13 = and(out_rivalid[13], out_rimask_13) node out_f_roready_13 = and(out_roready[13], out_romask_13) node out_f_wivalid_13 = and(out_wivalid[13], out_wimask_13) node out_f_woready_13 = and(out_woready[13], out_womask_13) connect claimer[3], out_f_roready_13 node _out_T_182 = bits(out_back_front_q.io.deq.bits.data, 63, 32) node _out_T_183 = bits(_out_T_182, 0, 0) node _out_T_184 = eq(completerDev, _out_T_183) node _out_T_185 = asUInt(reset) node _out_T_186 = eq(_out_T_185, UInt<1>(0h0)) when _out_T_186 : node _out_T_187 = eq(_out_T_184, UInt<1>(0h0)) when _out_T_187 : printf(clock, UInt<1>(0h1), "Assertion failed: completerDev should be consistent for all harts\n at Plic.scala:298 assert(completerDev === data.extract(log2Ceil(nDevices+1)-1, 0),\n") : out_printf_3 assert(clock, _out_T_184, UInt<1>(0h1), "") : out_assert_3 node _out_completerDev_T_3 = bits(_out_T_182, 0, 0) connect completerDev, _out_completerDev_T_3 node _out_completer_3_T = dshr(enableVec0[3], completerDev) node _out_completer_3_T_1 = bits(_out_completer_3_T, 0, 0) node _out_completer_3_T_2 = and(out_f_woready_13, _out_completer_3_T_1) connect completer[3], _out_completer_3_T_2 node _out_T_188 = and(out_f_rivalid_13, UInt<1>(0h1)) node _out_T_189 = and(UInt<1>(0h1), out_f_roready_13) node _out_T_190 = and(out_f_wivalid_13, UInt<1>(0h1)) node _out_T_191 = and(UInt<1>(0h1), out_f_woready_13) node _out_T_192 = eq(out_rimask_13, UInt<1>(0h0)) node _out_T_193 = eq(out_wimask_13, UInt<1>(0h0)) node _out_T_194 = eq(out_romask_13, UInt<1>(0h0)) node _out_T_195 = eq(out_womask_13, UInt<1>(0h0)) node _out_prepend_T_8 = or(_out_T_181, UInt<32>(0h0)) node out_prepend_8 = cat(maxDevs[3], _out_prepend_T_8) node _out_T_196 = or(out_prepend_8, UInt<64>(0h0)) node _out_T_197 = bits(_out_T_196, 63, 0) node _out_rimask_T_14 = bits(out_frontMask, 0, 0) node out_rimask_14 = orr(_out_rimask_T_14) node _out_wimask_T_14 = bits(out_frontMask, 0, 0) node out_wimask_14 = andr(_out_wimask_T_14) node _out_romask_T_14 = bits(out_backMask, 0, 0) node out_romask_14 = orr(_out_romask_T_14) node _out_womask_T_14 = bits(out_backMask, 0, 0) node out_womask_14 = andr(_out_womask_T_14) node out_f_rivalid_14 = and(out_rivalid[14], out_rimask_14) node out_f_roready_14 = and(out_roready[14], out_romask_14) node out_f_wivalid_14 = and(out_wivalid[14], out_wimask_14) node out_f_woready_14 = and(out_woready[14], out_womask_14) node _out_T_198 = bits(out_back_front_q.io.deq.bits.data, 0, 0) when out_f_woready_14 : connect threshold[7], _out_T_198 node _out_T_199 = and(out_f_rivalid_14, UInt<1>(0h1)) node _out_T_200 = and(UInt<1>(0h1), out_f_roready_14) node _out_T_201 = and(out_f_wivalid_14, UInt<1>(0h1)) node _out_T_202 = and(UInt<1>(0h1), out_f_woready_14) node _out_T_203 = eq(out_rimask_14, UInt<1>(0h0)) node _out_T_204 = eq(out_wimask_14, UInt<1>(0h0)) node _out_T_205 = eq(out_romask_14, UInt<1>(0h0)) node _out_T_206 = eq(out_womask_14, UInt<1>(0h0)) node _out_T_207 = or(threshold[7], UInt<1>(0h0)) node _out_T_208 = bits(_out_T_207, 0, 0) node _out_rimask_T_15 = bits(out_frontMask, 31, 1) node out_rimask_15 = orr(_out_rimask_T_15) node _out_wimask_T_15 = bits(out_frontMask, 31, 1) node out_wimask_15 = andr(_out_wimask_T_15) node _out_romask_T_15 = bits(out_backMask, 31, 1) node out_romask_15 = orr(_out_romask_T_15) node _out_womask_T_15 = bits(out_backMask, 31, 1) node out_womask_15 = andr(_out_womask_T_15) node out_f_rivalid_15 = and(out_rivalid[15], out_rimask_15) node out_f_roready_15 = and(out_roready[15], out_romask_15) node out_f_wivalid_15 = and(out_wivalid[15], out_wimask_15) node out_f_woready_15 = and(out_woready[15], out_womask_15) node _out_T_209 = bits(out_back_front_q.io.deq.bits.data, 31, 1) node _out_T_210 = and(out_f_rivalid_15, UInt<1>(0h1)) node _out_T_211 = and(UInt<1>(0h1), out_f_roready_15) node _out_T_212 = eq(out_rimask_15, UInt<1>(0h0)) node _out_T_213 = eq(out_wimask_15, UInt<1>(0h0)) node _out_T_214 = eq(out_romask_15, UInt<1>(0h0)) node _out_T_215 = eq(out_womask_15, UInt<1>(0h0)) node _out_prepend_T_9 = or(_out_T_208, UInt<1>(0h0)) node out_prepend_9 = cat(UInt<1>(0h0), _out_prepend_T_9) node _out_T_216 = or(out_prepend_9, UInt<32>(0h0)) node _out_T_217 = bits(_out_T_216, 31, 0) node _out_rimask_T_16 = bits(out_frontMask, 63, 32) node out_rimask_16 = orr(_out_rimask_T_16) node _out_wimask_T_16 = bits(out_frontMask, 63, 32) node out_wimask_16 = andr(_out_wimask_T_16) node _out_romask_T_16 = bits(out_backMask, 63, 32) node out_romask_16 = orr(_out_romask_T_16) node _out_womask_T_16 = bits(out_backMask, 63, 32) node out_womask_16 = andr(_out_womask_T_16) node out_f_rivalid_16 = and(out_rivalid[16], out_rimask_16) node out_f_roready_16 = and(out_roready[16], out_romask_16) node out_f_wivalid_16 = and(out_wivalid[16], out_wimask_16) node out_f_woready_16 = and(out_woready[16], out_womask_16) connect claimer[7], out_f_roready_16 node _out_T_218 = bits(out_back_front_q.io.deq.bits.data, 63, 32) node _out_T_219 = bits(_out_T_218, 0, 0) node _out_T_220 = eq(completerDev, _out_T_219) node _out_T_221 = asUInt(reset) node _out_T_222 = eq(_out_T_221, UInt<1>(0h0)) when _out_T_222 : node _out_T_223 = eq(_out_T_220, UInt<1>(0h0)) when _out_T_223 : printf(clock, UInt<1>(0h1), "Assertion failed: completerDev should be consistent for all harts\n at Plic.scala:298 assert(completerDev === data.extract(log2Ceil(nDevices+1)-1, 0),\n") : out_printf_4 assert(clock, _out_T_220, UInt<1>(0h1), "") : out_assert_4 node _out_completerDev_T_4 = bits(_out_T_218, 0, 0) connect completerDev, _out_completerDev_T_4 node _out_completer_7_T = dshr(enableVec0[7], completerDev) node _out_completer_7_T_1 = bits(_out_completer_7_T, 0, 0) node _out_completer_7_T_2 = and(out_f_woready_16, _out_completer_7_T_1) connect completer[7], _out_completer_7_T_2 node _out_T_224 = and(out_f_rivalid_16, UInt<1>(0h1)) node _out_T_225 = and(UInt<1>(0h1), out_f_roready_16) node _out_T_226 = and(out_f_wivalid_16, UInt<1>(0h1)) node _out_T_227 = and(UInt<1>(0h1), out_f_woready_16) node _out_T_228 = eq(out_rimask_16, UInt<1>(0h0)) node _out_T_229 = eq(out_wimask_16, UInt<1>(0h0)) node _out_T_230 = eq(out_romask_16, UInt<1>(0h0)) node _out_T_231 = eq(out_womask_16, UInt<1>(0h0)) node _out_prepend_T_10 = or(_out_T_217, UInt<32>(0h0)) node out_prepend_10 = cat(maxDevs[7], _out_prepend_T_10) node _out_T_232 = or(out_prepend_10, UInt<64>(0h0)) node _out_T_233 = bits(_out_T_232, 63, 0) node _out_rimask_T_17 = bits(out_frontMask, 0, 0) node out_rimask_17 = orr(_out_rimask_T_17) node _out_wimask_T_17 = bits(out_frontMask, 0, 0) node out_wimask_17 = andr(_out_wimask_T_17) node _out_romask_T_17 = bits(out_backMask, 0, 0) node out_romask_17 = orr(_out_romask_T_17) node _out_womask_T_17 = bits(out_backMask, 0, 0) node out_womask_17 = andr(_out_womask_T_17) node out_f_rivalid_17 = and(out_rivalid[17], out_rimask_17) node out_f_roready_17 = and(out_roready[17], out_romask_17) node out_f_wivalid_17 = and(out_wivalid[17], out_wimask_17) node out_f_woready_17 = and(out_woready[17], out_womask_17) node _out_T_234 = bits(out_back_front_q.io.deq.bits.data, 0, 0) when out_f_woready_17 : connect threshold[0], _out_T_234 node _out_T_235 = and(out_f_rivalid_17, UInt<1>(0h1)) node _out_T_236 = and(UInt<1>(0h1), out_f_roready_17) node _out_T_237 = and(out_f_wivalid_17, UInt<1>(0h1)) node _out_T_238 = and(UInt<1>(0h1), out_f_woready_17) node _out_T_239 = eq(out_rimask_17, UInt<1>(0h0)) node _out_T_240 = eq(out_wimask_17, UInt<1>(0h0)) node _out_T_241 = eq(out_romask_17, UInt<1>(0h0)) node _out_T_242 = eq(out_womask_17, UInt<1>(0h0)) node _out_T_243 = or(threshold[0], UInt<1>(0h0)) node _out_T_244 = bits(_out_T_243, 0, 0) node _out_rimask_T_18 = bits(out_frontMask, 31, 1) node out_rimask_18 = orr(_out_rimask_T_18) node _out_wimask_T_18 = bits(out_frontMask, 31, 1) node out_wimask_18 = andr(_out_wimask_T_18) node _out_romask_T_18 = bits(out_backMask, 31, 1) node out_romask_18 = orr(_out_romask_T_18) node _out_womask_T_18 = bits(out_backMask, 31, 1) node out_womask_18 = andr(_out_womask_T_18) node out_f_rivalid_18 = and(out_rivalid[18], out_rimask_18) node out_f_roready_18 = and(out_roready[18], out_romask_18) node out_f_wivalid_18 = and(out_wivalid[18], out_wimask_18) node out_f_woready_18 = and(out_woready[18], out_womask_18) node _out_T_245 = bits(out_back_front_q.io.deq.bits.data, 31, 1) node _out_T_246 = and(out_f_rivalid_18, UInt<1>(0h1)) node _out_T_247 = and(UInt<1>(0h1), out_f_roready_18) node _out_T_248 = eq(out_rimask_18, UInt<1>(0h0)) node _out_T_249 = eq(out_wimask_18, UInt<1>(0h0)) node _out_T_250 = eq(out_romask_18, UInt<1>(0h0)) node _out_T_251 = eq(out_womask_18, UInt<1>(0h0)) node _out_prepend_T_11 = or(_out_T_244, UInt<1>(0h0)) node out_prepend_11 = cat(UInt<1>(0h0), _out_prepend_T_11) node _out_T_252 = or(out_prepend_11, UInt<32>(0h0)) node _out_T_253 = bits(_out_T_252, 31, 0) node _out_rimask_T_19 = bits(out_frontMask, 63, 32) node out_rimask_19 = orr(_out_rimask_T_19) node _out_wimask_T_19 = bits(out_frontMask, 63, 32) node out_wimask_19 = andr(_out_wimask_T_19) node _out_romask_T_19 = bits(out_backMask, 63, 32) node out_romask_19 = orr(_out_romask_T_19) node _out_womask_T_19 = bits(out_backMask, 63, 32) node out_womask_19 = andr(_out_womask_T_19) node out_f_rivalid_19 = and(out_rivalid[19], out_rimask_19) node out_f_roready_19 = and(out_roready[19], out_romask_19) node out_f_wivalid_19 = and(out_wivalid[19], out_wimask_19) node out_f_woready_19 = and(out_woready[19], out_womask_19) connect claimer[0], out_f_roready_19 node _out_T_254 = bits(out_back_front_q.io.deq.bits.data, 63, 32) node _out_T_255 = bits(_out_T_254, 0, 0) node _out_T_256 = eq(completerDev, _out_T_255) node _out_T_257 = asUInt(reset) node _out_T_258 = eq(_out_T_257, UInt<1>(0h0)) when _out_T_258 : node _out_T_259 = eq(_out_T_256, UInt<1>(0h0)) when _out_T_259 : printf(clock, UInt<1>(0h1), "Assertion failed: completerDev should be consistent for all harts\n at Plic.scala:298 assert(completerDev === data.extract(log2Ceil(nDevices+1)-1, 0),\n") : out_printf_5 assert(clock, _out_T_256, UInt<1>(0h1), "") : out_assert_5 node _out_completerDev_T_5 = bits(_out_T_254, 0, 0) connect completerDev, _out_completerDev_T_5 node _out_completer_0_T = dshr(enableVec0[0], completerDev) node _out_completer_0_T_1 = bits(_out_completer_0_T, 0, 0) node _out_completer_0_T_2 = and(out_f_woready_19, _out_completer_0_T_1) connect completer[0], _out_completer_0_T_2 node _out_T_260 = and(out_f_rivalid_19, UInt<1>(0h1)) node _out_T_261 = and(UInt<1>(0h1), out_f_roready_19) node _out_T_262 = and(out_f_wivalid_19, UInt<1>(0h1)) node _out_T_263 = and(UInt<1>(0h1), out_f_woready_19) node _out_T_264 = eq(out_rimask_19, UInt<1>(0h0)) node _out_T_265 = eq(out_wimask_19, UInt<1>(0h0)) node _out_T_266 = eq(out_romask_19, UInt<1>(0h0)) node _out_T_267 = eq(out_womask_19, UInt<1>(0h0)) node _out_prepend_T_12 = or(_out_T_253, UInt<32>(0h0)) node out_prepend_12 = cat(maxDevs[0], _out_prepend_T_12) node _out_T_268 = or(out_prepend_12, UInt<64>(0h0)) node _out_T_269 = bits(_out_T_268, 63, 0) node _out_rimask_T_20 = bits(out_frontMask, 0, 0) node out_rimask_20 = orr(_out_rimask_T_20) node _out_wimask_T_20 = bits(out_frontMask, 0, 0) node out_wimask_20 = andr(_out_wimask_T_20) node _out_romask_T_20 = bits(out_backMask, 0, 0) node out_romask_20 = orr(_out_romask_T_20) node _out_womask_T_20 = bits(out_backMask, 0, 0) node out_womask_20 = andr(_out_womask_T_20) node out_f_rivalid_20 = and(out_rivalid[20], out_rimask_20) node out_f_roready_20 = and(out_roready[20], out_romask_20) node out_f_wivalid_20 = and(out_wivalid[20], out_wimask_20) node out_f_woready_20 = and(out_woready[20], out_womask_20) node _out_T_270 = bits(out_back_front_q.io.deq.bits.data, 0, 0) when out_f_woready_20 : connect threshold[2], _out_T_270 node _out_T_271 = and(out_f_rivalid_20, UInt<1>(0h1)) node _out_T_272 = and(UInt<1>(0h1), out_f_roready_20) node _out_T_273 = and(out_f_wivalid_20, UInt<1>(0h1)) node _out_T_274 = and(UInt<1>(0h1), out_f_woready_20) node _out_T_275 = eq(out_rimask_20, UInt<1>(0h0)) node _out_T_276 = eq(out_wimask_20, UInt<1>(0h0)) node _out_T_277 = eq(out_romask_20, UInt<1>(0h0)) node _out_T_278 = eq(out_womask_20, UInt<1>(0h0)) node _out_T_279 = or(threshold[2], UInt<1>(0h0)) node _out_T_280 = bits(_out_T_279, 0, 0) node _out_rimask_T_21 = bits(out_frontMask, 31, 1) node out_rimask_21 = orr(_out_rimask_T_21) node _out_wimask_T_21 = bits(out_frontMask, 31, 1) node out_wimask_21 = andr(_out_wimask_T_21) node _out_romask_T_21 = bits(out_backMask, 31, 1) node out_romask_21 = orr(_out_romask_T_21) node _out_womask_T_21 = bits(out_backMask, 31, 1) node out_womask_21 = andr(_out_womask_T_21) node out_f_rivalid_21 = and(out_rivalid[21], out_rimask_21) node out_f_roready_21 = and(out_roready[21], out_romask_21) node out_f_wivalid_21 = and(out_wivalid[21], out_wimask_21) node out_f_woready_21 = and(out_woready[21], out_womask_21) node _out_T_281 = bits(out_back_front_q.io.deq.bits.data, 31, 1) node _out_T_282 = and(out_f_rivalid_21, UInt<1>(0h1)) node _out_T_283 = and(UInt<1>(0h1), out_f_roready_21) node _out_T_284 = eq(out_rimask_21, UInt<1>(0h0)) node _out_T_285 = eq(out_wimask_21, UInt<1>(0h0)) node _out_T_286 = eq(out_romask_21, UInt<1>(0h0)) node _out_T_287 = eq(out_womask_21, UInt<1>(0h0)) node _out_prepend_T_13 = or(_out_T_280, UInt<1>(0h0)) node out_prepend_13 = cat(UInt<1>(0h0), _out_prepend_T_13) node _out_T_288 = or(out_prepend_13, UInt<32>(0h0)) node _out_T_289 = bits(_out_T_288, 31, 0) node _out_rimask_T_22 = bits(out_frontMask, 63, 32) node out_rimask_22 = orr(_out_rimask_T_22) node _out_wimask_T_22 = bits(out_frontMask, 63, 32) node out_wimask_22 = andr(_out_wimask_T_22) node _out_romask_T_22 = bits(out_backMask, 63, 32) node out_romask_22 = orr(_out_romask_T_22) node _out_womask_T_22 = bits(out_backMask, 63, 32) node out_womask_22 = andr(_out_womask_T_22) node out_f_rivalid_22 = and(out_rivalid[22], out_rimask_22) node out_f_roready_22 = and(out_roready[22], out_romask_22) node out_f_wivalid_22 = and(out_wivalid[22], out_wimask_22) node out_f_woready_22 = and(out_woready[22], out_womask_22) connect claimer[2], out_f_roready_22 node _out_T_290 = bits(out_back_front_q.io.deq.bits.data, 63, 32) node _out_T_291 = bits(_out_T_290, 0, 0) node _out_T_292 = eq(completerDev, _out_T_291) node _out_T_293 = asUInt(reset) node _out_T_294 = eq(_out_T_293, UInt<1>(0h0)) when _out_T_294 : node _out_T_295 = eq(_out_T_292, UInt<1>(0h0)) when _out_T_295 : printf(clock, UInt<1>(0h1), "Assertion failed: completerDev should be consistent for all harts\n at Plic.scala:298 assert(completerDev === data.extract(log2Ceil(nDevices+1)-1, 0),\n") : out_printf_6 assert(clock, _out_T_292, UInt<1>(0h1), "") : out_assert_6 node _out_completerDev_T_6 = bits(_out_T_290, 0, 0) connect completerDev, _out_completerDev_T_6 node _out_completer_2_T = dshr(enableVec0[2], completerDev) node _out_completer_2_T_1 = bits(_out_completer_2_T, 0, 0) node _out_completer_2_T_2 = and(out_f_woready_22, _out_completer_2_T_1) connect completer[2], _out_completer_2_T_2 node _out_T_296 = and(out_f_rivalid_22, UInt<1>(0h1)) node _out_T_297 = and(UInt<1>(0h1), out_f_roready_22) node _out_T_298 = and(out_f_wivalid_22, UInt<1>(0h1)) node _out_T_299 = and(UInt<1>(0h1), out_f_woready_22) node _out_T_300 = eq(out_rimask_22, UInt<1>(0h0)) node _out_T_301 = eq(out_wimask_22, UInt<1>(0h0)) node _out_T_302 = eq(out_romask_22, UInt<1>(0h0)) node _out_T_303 = eq(out_womask_22, UInt<1>(0h0)) node _out_prepend_T_14 = or(_out_T_289, UInt<32>(0h0)) node out_prepend_14 = cat(maxDevs[2], _out_prepend_T_14) node _out_T_304 = or(out_prepend_14, UInt<64>(0h0)) node _out_T_305 = bits(_out_T_304, 63, 0) node _out_rimask_T_23 = bits(out_frontMask, 0, 0) node out_rimask_23 = orr(_out_rimask_T_23) node _out_wimask_T_23 = bits(out_frontMask, 0, 0) node out_wimask_23 = andr(_out_wimask_T_23) node _out_romask_T_23 = bits(out_backMask, 0, 0) node out_romask_23 = orr(_out_romask_T_23) node _out_womask_T_23 = bits(out_backMask, 0, 0) node out_womask_23 = andr(_out_womask_T_23) node out_f_rivalid_23 = and(out_rivalid[23], out_rimask_23) node out_f_roready_23 = and(out_roready[23], out_romask_23) node out_f_wivalid_23 = and(out_wivalid[23], out_wimask_23) node out_f_woready_23 = and(out_woready[23], out_womask_23) node _out_T_306 = bits(out_back_front_q.io.deq.bits.data, 0, 0) when out_f_woready_23 : connect threshold[6], _out_T_306 node _out_T_307 = and(out_f_rivalid_23, UInt<1>(0h1)) node _out_T_308 = and(UInt<1>(0h1), out_f_roready_23) node _out_T_309 = and(out_f_wivalid_23, UInt<1>(0h1)) node _out_T_310 = and(UInt<1>(0h1), out_f_woready_23) node _out_T_311 = eq(out_rimask_23, UInt<1>(0h0)) node _out_T_312 = eq(out_wimask_23, UInt<1>(0h0)) node _out_T_313 = eq(out_romask_23, UInt<1>(0h0)) node _out_T_314 = eq(out_womask_23, UInt<1>(0h0)) node _out_T_315 = or(threshold[6], UInt<1>(0h0)) node _out_T_316 = bits(_out_T_315, 0, 0) node _out_rimask_T_24 = bits(out_frontMask, 31, 1) node out_rimask_24 = orr(_out_rimask_T_24) node _out_wimask_T_24 = bits(out_frontMask, 31, 1) node out_wimask_24 = andr(_out_wimask_T_24) node _out_romask_T_24 = bits(out_backMask, 31, 1) node out_romask_24 = orr(_out_romask_T_24) node _out_womask_T_24 = bits(out_backMask, 31, 1) node out_womask_24 = andr(_out_womask_T_24) node out_f_rivalid_24 = and(out_rivalid[24], out_rimask_24) node out_f_roready_24 = and(out_roready[24], out_romask_24) node out_f_wivalid_24 = and(out_wivalid[24], out_wimask_24) node out_f_woready_24 = and(out_woready[24], out_womask_24) node _out_T_317 = bits(out_back_front_q.io.deq.bits.data, 31, 1) node _out_T_318 = and(out_f_rivalid_24, UInt<1>(0h1)) node _out_T_319 = and(UInt<1>(0h1), out_f_roready_24) node _out_T_320 = eq(out_rimask_24, UInt<1>(0h0)) node _out_T_321 = eq(out_wimask_24, UInt<1>(0h0)) node _out_T_322 = eq(out_romask_24, UInt<1>(0h0)) node _out_T_323 = eq(out_womask_24, UInt<1>(0h0)) node _out_prepend_T_15 = or(_out_T_316, UInt<1>(0h0)) node out_prepend_15 = cat(UInt<1>(0h0), _out_prepend_T_15) node _out_T_324 = or(out_prepend_15, UInt<32>(0h0)) node _out_T_325 = bits(_out_T_324, 31, 0) node _out_rimask_T_25 = bits(out_frontMask, 63, 32) node out_rimask_25 = orr(_out_rimask_T_25) node _out_wimask_T_25 = bits(out_frontMask, 63, 32) node out_wimask_25 = andr(_out_wimask_T_25) node _out_romask_T_25 = bits(out_backMask, 63, 32) node out_romask_25 = orr(_out_romask_T_25) node _out_womask_T_25 = bits(out_backMask, 63, 32) node out_womask_25 = andr(_out_womask_T_25) node out_f_rivalid_25 = and(out_rivalid[25], out_rimask_25) node out_f_roready_25 = and(out_roready[25], out_romask_25) node out_f_wivalid_25 = and(out_wivalid[25], out_wimask_25) node out_f_woready_25 = and(out_woready[25], out_womask_25) connect claimer[6], out_f_roready_25 node _out_T_326 = bits(out_back_front_q.io.deq.bits.data, 63, 32) node _out_T_327 = bits(_out_T_326, 0, 0) node _out_T_328 = eq(completerDev, _out_T_327) node _out_T_329 = asUInt(reset) node _out_T_330 = eq(_out_T_329, UInt<1>(0h0)) when _out_T_330 : node _out_T_331 = eq(_out_T_328, UInt<1>(0h0)) when _out_T_331 : printf(clock, UInt<1>(0h1), "Assertion failed: completerDev should be consistent for all harts\n at Plic.scala:298 assert(completerDev === data.extract(log2Ceil(nDevices+1)-1, 0),\n") : out_printf_7 assert(clock, _out_T_328, UInt<1>(0h1), "") : out_assert_7 node _out_completerDev_T_7 = bits(_out_T_326, 0, 0) connect completerDev, _out_completerDev_T_7 node _out_completer_6_T = dshr(enableVec0[6], completerDev) node _out_completer_6_T_1 = bits(_out_completer_6_T, 0, 0) node _out_completer_6_T_2 = and(out_f_woready_25, _out_completer_6_T_1) connect completer[6], _out_completer_6_T_2 node _out_T_332 = and(out_f_rivalid_25, UInt<1>(0h1)) node _out_T_333 = and(UInt<1>(0h1), out_f_roready_25) node _out_T_334 = and(out_f_wivalid_25, UInt<1>(0h1)) node _out_T_335 = and(UInt<1>(0h1), out_f_woready_25) node _out_T_336 = eq(out_rimask_25, UInt<1>(0h0)) node _out_T_337 = eq(out_wimask_25, UInt<1>(0h0)) node _out_T_338 = eq(out_romask_25, UInt<1>(0h0)) node _out_T_339 = eq(out_womask_25, UInt<1>(0h0)) node _out_prepend_T_16 = or(_out_T_325, UInt<32>(0h0)) node out_prepend_16 = cat(maxDevs[6], _out_prepend_T_16) node _out_T_340 = or(out_prepend_16, UInt<64>(0h0)) node _out_T_341 = bits(_out_T_340, 63, 0) node _out_rimask_T_26 = bits(out_frontMask, 0, 0) node out_rimask_26 = orr(_out_rimask_T_26) node _out_wimask_T_26 = bits(out_frontMask, 0, 0) node out_wimask_26 = andr(_out_wimask_T_26) node _out_romask_T_26 = bits(out_backMask, 0, 0) node out_romask_26 = orr(_out_romask_T_26) node _out_womask_T_26 = bits(out_backMask, 0, 0) node out_womask_26 = andr(_out_womask_T_26) node out_f_rivalid_26 = and(out_rivalid[26], out_rimask_26) node out_f_roready_26 = and(out_roready[26], out_romask_26) node out_f_wivalid_26 = and(out_wivalid[26], out_wimask_26) node out_f_woready_26 = and(out_woready[26], out_womask_26) node _out_T_342 = bits(out_back_front_q.io.deq.bits.data, 0, 0) node _out_T_343 = and(out_f_rivalid_26, UInt<1>(0h1)) node _out_T_344 = and(UInt<1>(0h1), out_f_roready_26) node _out_T_345 = eq(out_rimask_26, UInt<1>(0h0)) node _out_T_346 = eq(out_wimask_26, UInt<1>(0h0)) node _out_T_347 = eq(out_romask_26, UInt<1>(0h0)) node _out_T_348 = eq(out_womask_26, UInt<1>(0h0)) node _out_T_349 = or(UInt<1>(0h0), UInt<1>(0h0)) node _out_T_350 = bits(_out_T_349, 0, 0) node _out_rimask_T_27 = bits(out_frontMask, 1, 1) node out_rimask_27 = orr(_out_rimask_T_27) node _out_wimask_T_27 = bits(out_frontMask, 1, 1) node out_wimask_27 = andr(_out_wimask_T_27) node _out_romask_T_27 = bits(out_backMask, 1, 1) node out_romask_27 = orr(_out_romask_T_27) node _out_womask_T_27 = bits(out_backMask, 1, 1) node out_womask_27 = andr(_out_womask_T_27) node out_f_rivalid_27 = and(out_rivalid[27], out_rimask_27) node out_f_roready_27 = and(out_roready[27], out_romask_27) node out_f_wivalid_27 = and(out_wivalid[27], out_wimask_27) node out_f_woready_27 = and(out_woready[27], out_womask_27) node _out_T_351 = bits(out_back_front_q.io.deq.bits.data, 1, 1) when out_f_woready_27 : connect enables_2_0, _out_T_351 node _out_T_352 = and(out_f_rivalid_27, UInt<1>(0h1)) node _out_T_353 = and(UInt<1>(0h1), out_f_roready_27) node _out_T_354 = and(out_f_wivalid_27, UInt<1>(0h1)) node _out_T_355 = and(UInt<1>(0h1), out_f_woready_27) node _out_T_356 = eq(out_rimask_27, UInt<1>(0h0)) node _out_T_357 = eq(out_wimask_27, UInt<1>(0h0)) node _out_T_358 = eq(out_romask_27, UInt<1>(0h0)) node _out_T_359 = eq(out_womask_27, UInt<1>(0h0)) node _out_prepend_T_17 = or(_out_T_350, UInt<1>(0h0)) node out_prepend_17 = cat(enables_2_0, _out_prepend_T_17) node _out_T_360 = or(out_prepend_17, UInt<2>(0h0)) node _out_T_361 = bits(_out_T_360, 1, 0) node _out_rimask_T_28 = bits(out_frontMask, 0, 0) node out_rimask_28 = orr(_out_rimask_T_28) node _out_wimask_T_28 = bits(out_frontMask, 0, 0) node out_wimask_28 = andr(_out_wimask_T_28) node _out_romask_T_28 = bits(out_backMask, 0, 0) node out_romask_28 = orr(_out_romask_T_28) node _out_womask_T_28 = bits(out_backMask, 0, 0) node out_womask_28 = andr(_out_womask_T_28) node out_f_rivalid_28 = and(out_rivalid[28], out_rimask_28) node out_f_roready_28 = and(out_roready[28], out_romask_28) node out_f_wivalid_28 = and(out_wivalid[28], out_wimask_28) node out_f_woready_28 = and(out_woready[28], out_womask_28) node _out_T_362 = bits(out_back_front_q.io.deq.bits.data, 0, 0) node _out_T_363 = and(out_f_rivalid_28, UInt<1>(0h1)) node _out_T_364 = and(UInt<1>(0h1), out_f_roready_28) node _out_T_365 = eq(out_rimask_28, UInt<1>(0h0)) node _out_T_366 = eq(out_wimask_28, UInt<1>(0h0)) node _out_T_367 = eq(out_romask_28, UInt<1>(0h0)) node _out_T_368 = eq(out_womask_28, UInt<1>(0h0)) node _out_T_369 = or(UInt<1>(0h0), UInt<1>(0h0)) node _out_T_370 = bits(_out_T_369, 0, 0) node _out_rimask_T_29 = bits(out_frontMask, 1, 1) node out_rimask_29 = orr(_out_rimask_T_29) node _out_wimask_T_29 = bits(out_frontMask, 1, 1) node out_wimask_29 = andr(_out_wimask_T_29) node _out_romask_T_29 = bits(out_backMask, 1, 1) node out_romask_29 = orr(_out_romask_T_29) node _out_womask_T_29 = bits(out_backMask, 1, 1) node out_womask_29 = andr(_out_womask_T_29) node out_f_rivalid_29 = and(out_rivalid[29], out_rimask_29) node out_f_roready_29 = and(out_roready[29], out_romask_29) node out_f_wivalid_29 = and(out_wivalid[29], out_wimask_29) node out_f_woready_29 = and(out_woready[29], out_womask_29) node _out_T_371 = bits(out_back_front_q.io.deq.bits.data, 1, 1) when out_f_woready_29 : connect enables_6_0, _out_T_371 node _out_T_372 = and(out_f_rivalid_29, UInt<1>(0h1)) node _out_T_373 = and(UInt<1>(0h1), out_f_roready_29) node _out_T_374 = and(out_f_wivalid_29, UInt<1>(0h1)) node _out_T_375 = and(UInt<1>(0h1), out_f_woready_29) node _out_T_376 = eq(out_rimask_29, UInt<1>(0h0)) node _out_T_377 = eq(out_wimask_29, UInt<1>(0h0)) node _out_T_378 = eq(out_romask_29, UInt<1>(0h0)) node _out_T_379 = eq(out_womask_29, UInt<1>(0h0)) node _out_prepend_T_18 = or(_out_T_370, UInt<1>(0h0)) node out_prepend_18 = cat(enables_6_0, _out_prepend_T_18) node _out_T_380 = or(out_prepend_18, UInt<2>(0h0)) node _out_T_381 = bits(_out_T_380, 1, 0) node _out_rimask_T_30 = bits(out_frontMask, 0, 0) node out_rimask_30 = orr(_out_rimask_T_30) node _out_wimask_T_30 = bits(out_frontMask, 0, 0) node out_wimask_30 = andr(_out_wimask_T_30) node _out_romask_T_30 = bits(out_backMask, 0, 0) node out_romask_30 = orr(_out_romask_T_30) node _out_womask_T_30 = bits(out_backMask, 0, 0) node out_womask_30 = andr(_out_womask_T_30) node out_f_rivalid_30 = and(out_rivalid[30], out_rimask_30) node out_f_roready_30 = and(out_roready[30], out_romask_30) node out_f_wivalid_30 = and(out_wivalid[30], out_wimask_30) node out_f_woready_30 = and(out_woready[30], out_womask_30) node _out_T_382 = bits(out_back_front_q.io.deq.bits.data, 0, 0) node _out_T_383 = and(out_f_rivalid_30, UInt<1>(0h1)) node _out_T_384 = and(UInt<1>(0h1), out_f_roready_30) node _out_T_385 = eq(out_rimask_30, UInt<1>(0h0)) node _out_T_386 = eq(out_wimask_30, UInt<1>(0h0)) node _out_T_387 = eq(out_romask_30, UInt<1>(0h0)) node _out_T_388 = eq(out_womask_30, UInt<1>(0h0)) node _out_T_389 = or(UInt<1>(0h0), UInt<1>(0h0)) node _out_T_390 = bits(_out_T_389, 0, 0) node _out_rimask_T_31 = bits(out_frontMask, 1, 1) node out_rimask_31 = orr(_out_rimask_T_31) node _out_wimask_T_31 = bits(out_frontMask, 1, 1) node out_wimask_31 = andr(_out_wimask_T_31) node _out_romask_T_31 = bits(out_backMask, 1, 1) node out_romask_31 = orr(_out_romask_T_31) node _out_womask_T_31 = bits(out_backMask, 1, 1) node out_womask_31 = andr(_out_womask_T_31) node out_f_rivalid_31 = and(out_rivalid[31], out_rimask_31) node out_f_roready_31 = and(out_roready[31], out_romask_31) node out_f_wivalid_31 = and(out_wivalid[31], out_wimask_31) node out_f_woready_31 = and(out_woready[31], out_womask_31) node _out_T_391 = bits(out_back_front_q.io.deq.bits.data, 1, 1) when out_f_woready_31 : connect enables_4_0, _out_T_391 node _out_T_392 = and(out_f_rivalid_31, UInt<1>(0h1)) node _out_T_393 = and(UInt<1>(0h1), out_f_roready_31) node _out_T_394 = and(out_f_wivalid_31, UInt<1>(0h1)) node _out_T_395 = and(UInt<1>(0h1), out_f_woready_31) node _out_T_396 = eq(out_rimask_31, UInt<1>(0h0)) node _out_T_397 = eq(out_wimask_31, UInt<1>(0h0)) node _out_T_398 = eq(out_romask_31, UInt<1>(0h0)) node _out_T_399 = eq(out_womask_31, UInt<1>(0h0)) node _out_prepend_T_19 = or(_out_T_390, UInt<1>(0h0)) node out_prepend_19 = cat(enables_4_0, _out_prepend_T_19) node _out_T_400 = or(out_prepend_19, UInt<2>(0h0)) node _out_T_401 = bits(_out_T_400, 1, 0) node _out_rimask_T_32 = bits(out_frontMask, 0, 0) node out_rimask_32 = orr(_out_rimask_T_32) node _out_wimask_T_32 = bits(out_frontMask, 0, 0) node out_wimask_32 = andr(_out_wimask_T_32) node _out_romask_T_32 = bits(out_backMask, 0, 0) node out_romask_32 = orr(_out_romask_T_32) node _out_womask_T_32 = bits(out_backMask, 0, 0) node out_womask_32 = andr(_out_womask_T_32) node out_f_rivalid_32 = and(out_rivalid[32], out_rimask_32) node out_f_roready_32 = and(out_roready[32], out_romask_32) node out_f_wivalid_32 = and(out_wivalid[32], out_wimask_32) node out_f_woready_32 = and(out_woready[32], out_womask_32) node _out_T_402 = bits(out_back_front_q.io.deq.bits.data, 0, 0) node _out_T_403 = and(out_f_rivalid_32, UInt<1>(0h1)) node _out_T_404 = and(UInt<1>(0h1), out_f_roready_32) node _out_T_405 = eq(out_rimask_32, UInt<1>(0h0)) node _out_T_406 = eq(out_wimask_32, UInt<1>(0h0)) node _out_T_407 = eq(out_romask_32, UInt<1>(0h0)) node _out_T_408 = eq(out_womask_32, UInt<1>(0h0)) node _out_T_409 = or(UInt<1>(0h0), UInt<1>(0h0)) node _out_T_410 = bits(_out_T_409, 0, 0) node _out_rimask_T_33 = bits(out_frontMask, 1, 1) node out_rimask_33 = orr(_out_rimask_T_33) node _out_wimask_T_33 = bits(out_frontMask, 1, 1) node out_wimask_33 = andr(_out_wimask_T_33) node _out_romask_T_33 = bits(out_backMask, 1, 1) node out_romask_33 = orr(_out_romask_T_33) node _out_womask_T_33 = bits(out_backMask, 1, 1) node out_womask_33 = andr(_out_womask_T_33) node out_f_rivalid_33 = and(out_rivalid[33], out_rimask_33) node out_f_roready_33 = and(out_roready[33], out_romask_33) node out_f_wivalid_33 = and(out_wivalid[33], out_wimask_33) node out_f_woready_33 = and(out_woready[33], out_womask_33) node _out_T_411 = bits(out_back_front_q.io.deq.bits.data, 1, 1) when out_f_woready_33 : connect enables_0_0, _out_T_411 node _out_T_412 = and(out_f_rivalid_33, UInt<1>(0h1)) node _out_T_413 = and(UInt<1>(0h1), out_f_roready_33) node _out_T_414 = and(out_f_wivalid_33, UInt<1>(0h1)) node _out_T_415 = and(UInt<1>(0h1), out_f_woready_33) node _out_T_416 = eq(out_rimask_33, UInt<1>(0h0)) node _out_T_417 = eq(out_wimask_33, UInt<1>(0h0)) node _out_T_418 = eq(out_romask_33, UInt<1>(0h0)) node _out_T_419 = eq(out_womask_33, UInt<1>(0h0)) node _out_prepend_T_20 = or(_out_T_410, UInt<1>(0h0)) node out_prepend_20 = cat(enables_0_0, _out_prepend_T_20) node _out_T_420 = or(out_prepend_20, UInt<2>(0h0)) node _out_T_421 = bits(_out_T_420, 1, 0) node _out_rimask_T_34 = bits(out_frontMask, 32, 32) node out_rimask_34 = orr(_out_rimask_T_34) node _out_wimask_T_34 = bits(out_frontMask, 32, 32) node out_wimask_34 = andr(_out_wimask_T_34) node _out_romask_T_34 = bits(out_backMask, 32, 32) node out_romask_34 = orr(_out_romask_T_34) node _out_womask_T_34 = bits(out_backMask, 32, 32) node out_womask_34 = andr(_out_womask_T_34) node out_f_rivalid_34 = and(out_rivalid[34], out_rimask_34) node out_f_roready_34 = and(out_roready[34], out_romask_34) node out_f_wivalid_34 = and(out_wivalid[34], out_wimask_34) node out_f_woready_34 = and(out_woready[34], out_womask_34) node _out_T_422 = bits(out_back_front_q.io.deq.bits.data, 32, 32) when out_f_woready_34 : connect priority[0], _out_T_422 node _out_T_423 = and(out_f_rivalid_34, UInt<1>(0h1)) node _out_T_424 = and(UInt<1>(0h1), out_f_roready_34) node _out_T_425 = and(out_f_wivalid_34, UInt<1>(0h1)) node _out_T_426 = and(UInt<1>(0h1), out_f_woready_34) node _out_T_427 = eq(out_rimask_34, UInt<1>(0h0)) node _out_T_428 = eq(out_wimask_34, UInt<1>(0h0)) node _out_T_429 = eq(out_romask_34, UInt<1>(0h0)) node _out_T_430 = eq(out_womask_34, UInt<1>(0h0)) node _out_prepend_T_21 = or(UInt<1>(0h0), UInt<32>(0h0)) node out_prepend_21 = cat(priority[0], _out_prepend_T_21) node _out_T_431 = or(out_prepend_21, UInt<33>(0h0)) node _out_T_432 = bits(_out_T_431, 32, 0) node _out_rimask_T_35 = bits(out_frontMask, 0, 0) node out_rimask_35 = orr(_out_rimask_T_35) node _out_wimask_T_35 = bits(out_frontMask, 0, 0) node out_wimask_35 = andr(_out_wimask_T_35) node _out_romask_T_35 = bits(out_backMask, 0, 0) node out_romask_35 = orr(_out_romask_T_35) node _out_womask_T_35 = bits(out_backMask, 0, 0) node out_womask_35 = andr(_out_womask_T_35) node out_f_rivalid_35 = and(out_rivalid[35], out_rimask_35) node out_f_roready_35 = and(out_roready[35], out_romask_35) node out_f_wivalid_35 = and(out_wivalid[35], out_wimask_35) node out_f_woready_35 = and(out_woready[35], out_womask_35) node _out_T_433 = bits(out_back_front_q.io.deq.bits.data, 0, 0) node _out_T_434 = and(out_f_rivalid_35, UInt<1>(0h1)) node _out_T_435 = and(UInt<1>(0h1), out_f_roready_35) node _out_T_436 = eq(out_rimask_35, UInt<1>(0h0)) node _out_T_437 = eq(out_wimask_35, UInt<1>(0h0)) node _out_T_438 = eq(out_romask_35, UInt<1>(0h0)) node _out_T_439 = eq(out_womask_35, UInt<1>(0h0)) node _out_T_440 = or(UInt<1>(0h0), UInt<1>(0h0)) node _out_T_441 = bits(_out_T_440, 0, 0) node _out_rimask_T_36 = bits(out_frontMask, 1, 1) node out_rimask_36 = orr(_out_rimask_T_36) node _out_wimask_T_36 = bits(out_frontMask, 1, 1) node out_wimask_36 = andr(_out_wimask_T_36) node _out_romask_T_36 = bits(out_backMask, 1, 1) node out_romask_36 = orr(_out_romask_T_36) node _out_womask_T_36 = bits(out_backMask, 1, 1) node out_womask_36 = andr(_out_womask_T_36) node out_f_rivalid_36 = and(out_rivalid[36], out_rimask_36) node out_f_roready_36 = and(out_roready[36], out_romask_36) node out_f_wivalid_36 = and(out_wivalid[36], out_wimask_36) node out_f_woready_36 = and(out_woready[36], out_womask_36) node _out_T_442 = bits(out_back_front_q.io.deq.bits.data, 1, 1) when out_f_woready_36 : connect enables_1_0, _out_T_442 node _out_T_443 = and(out_f_rivalid_36, UInt<1>(0h1)) node _out_T_444 = and(UInt<1>(0h1), out_f_roready_36) node _out_T_445 = and(out_f_wivalid_36, UInt<1>(0h1)) node _out_T_446 = and(UInt<1>(0h1), out_f_woready_36) node _out_T_447 = eq(out_rimask_36, UInt<1>(0h0)) node _out_T_448 = eq(out_wimask_36, UInt<1>(0h0)) node _out_T_449 = eq(out_romask_36, UInt<1>(0h0)) node _out_T_450 = eq(out_womask_36, UInt<1>(0h0)) node _out_prepend_T_22 = or(_out_T_441, UInt<1>(0h0)) node out_prepend_22 = cat(enables_1_0, _out_prepend_T_22) node _out_T_451 = or(out_prepend_22, UInt<2>(0h0)) node _out_T_452 = bits(_out_T_451, 1, 0) node _out_rimask_T_37 = bits(out_frontMask, 0, 0) node out_rimask_37 = orr(_out_rimask_T_37) node _out_wimask_T_37 = bits(out_frontMask, 0, 0) node out_wimask_37 = andr(_out_wimask_T_37) node _out_romask_T_37 = bits(out_backMask, 0, 0) node out_romask_37 = orr(_out_romask_T_37) node _out_womask_T_37 = bits(out_backMask, 0, 0) node out_womask_37 = andr(_out_womask_T_37) node out_f_rivalid_37 = and(out_rivalid[37], out_rimask_37) node out_f_roready_37 = and(out_roready[37], out_romask_37) node out_f_wivalid_37 = and(out_wivalid[37], out_wimask_37) node out_f_woready_37 = and(out_woready[37], out_womask_37) node _out_T_453 = bits(out_back_front_q.io.deq.bits.data, 0, 0) node _out_T_454 = and(out_f_rivalid_37, UInt<1>(0h1)) node _out_T_455 = and(UInt<1>(0h1), out_f_roready_37) node _out_T_456 = eq(out_rimask_37, UInt<1>(0h0)) node _out_T_457 = eq(out_wimask_37, UInt<1>(0h0)) node _out_T_458 = eq(out_romask_37, UInt<1>(0h0)) node _out_T_459 = eq(out_womask_37, UInt<1>(0h0)) node _out_T_460 = or(UInt<1>(0h0), UInt<1>(0h0)) node _out_T_461 = bits(_out_T_460, 0, 0) node _out_rimask_T_38 = bits(out_frontMask, 1, 1) node out_rimask_38 = orr(_out_rimask_T_38) node _out_wimask_T_38 = bits(out_frontMask, 1, 1) node out_wimask_38 = andr(_out_wimask_T_38) node _out_romask_T_38 = bits(out_backMask, 1, 1) node out_romask_38 = orr(_out_romask_T_38) node _out_womask_T_38 = bits(out_backMask, 1, 1) node out_womask_38 = andr(_out_womask_T_38) node out_f_rivalid_38 = and(out_rivalid[38], out_rimask_38) node out_f_roready_38 = and(out_roready[38], out_romask_38) node out_f_wivalid_38 = and(out_wivalid[38], out_wimask_38) node out_f_woready_38 = and(out_woready[38], out_womask_38) node _out_T_462 = bits(out_back_front_q.io.deq.bits.data, 1, 1) when out_f_woready_38 : connect enables_7_0, _out_T_462 node _out_T_463 = and(out_f_rivalid_38, UInt<1>(0h1)) node _out_T_464 = and(UInt<1>(0h1), out_f_roready_38) node _out_T_465 = and(out_f_wivalid_38, UInt<1>(0h1)) node _out_T_466 = and(UInt<1>(0h1), out_f_woready_38) node _out_T_467 = eq(out_rimask_38, UInt<1>(0h0)) node _out_T_468 = eq(out_wimask_38, UInt<1>(0h0)) node _out_T_469 = eq(out_romask_38, UInt<1>(0h0)) node _out_T_470 = eq(out_womask_38, UInt<1>(0h0)) node _out_prepend_T_23 = or(_out_T_461, UInt<1>(0h0)) node out_prepend_23 = cat(enables_7_0, _out_prepend_T_23) node _out_T_471 = or(out_prepend_23, UInt<2>(0h0)) node _out_T_472 = bits(_out_T_471, 1, 0) node _out_rimask_T_39 = bits(out_frontMask, 0, 0) node out_rimask_39 = orr(_out_rimask_T_39) node _out_wimask_T_39 = bits(out_frontMask, 0, 0) node out_wimask_39 = andr(_out_wimask_T_39) node _out_romask_T_39 = bits(out_backMask, 0, 0) node out_romask_39 = orr(_out_romask_T_39) node _out_womask_T_39 = bits(out_backMask, 0, 0) node out_womask_39 = andr(_out_womask_T_39) node out_f_rivalid_39 = and(out_rivalid[39], out_rimask_39) node out_f_roready_39 = and(out_roready[39], out_romask_39) node out_f_wivalid_39 = and(out_wivalid[39], out_wimask_39) node out_f_woready_39 = and(out_woready[39], out_womask_39) node _out_T_473 = bits(out_back_front_q.io.deq.bits.data, 0, 0) node _out_T_474 = and(out_f_rivalid_39, UInt<1>(0h1)) node _out_T_475 = and(UInt<1>(0h1), out_f_roready_39) node _out_T_476 = eq(out_rimask_39, UInt<1>(0h0)) node _out_T_477 = eq(out_wimask_39, UInt<1>(0h0)) node _out_T_478 = eq(out_romask_39, UInt<1>(0h0)) node _out_T_479 = eq(out_womask_39, UInt<1>(0h0)) node _out_T_480 = or(UInt<1>(0h0), UInt<1>(0h0)) node _out_T_481 = bits(_out_T_480, 0, 0) node _out_rimask_T_40 = bits(out_frontMask, 1, 1) node out_rimask_40 = orr(_out_rimask_T_40) node _out_wimask_T_40 = bits(out_frontMask, 1, 1) node out_wimask_40 = andr(_out_wimask_T_40) node _out_romask_T_40 = bits(out_backMask, 1, 1) node out_romask_40 = orr(_out_romask_T_40) node _out_womask_T_40 = bits(out_backMask, 1, 1) node out_womask_40 = andr(_out_womask_T_40) node out_f_rivalid_40 = and(out_rivalid[40], out_rimask_40) node out_f_roready_40 = and(out_roready[40], out_romask_40) node out_f_wivalid_40 = and(out_wivalid[40], out_wimask_40) node out_f_woready_40 = and(out_woready[40], out_womask_40) node _out_T_482 = bits(out_back_front_q.io.deq.bits.data, 1, 1) when out_f_woready_40 : connect enables_3_0, _out_T_482 node _out_T_483 = and(out_f_rivalid_40, UInt<1>(0h1)) node _out_T_484 = and(UInt<1>(0h1), out_f_roready_40) node _out_T_485 = and(out_f_wivalid_40, UInt<1>(0h1)) node _out_T_486 = and(UInt<1>(0h1), out_f_woready_40) node _out_T_487 = eq(out_rimask_40, UInt<1>(0h0)) node _out_T_488 = eq(out_wimask_40, UInt<1>(0h0)) node _out_T_489 = eq(out_romask_40, UInt<1>(0h0)) node _out_T_490 = eq(out_womask_40, UInt<1>(0h0)) node _out_prepend_T_24 = or(_out_T_481, UInt<1>(0h0)) node out_prepend_24 = cat(enables_3_0, _out_prepend_T_24) node _out_T_491 = or(out_prepend_24, UInt<2>(0h0)) node _out_T_492 = bits(_out_T_491, 1, 0) node _out_rimask_T_41 = bits(out_frontMask, 0, 0) node out_rimask_41 = orr(_out_rimask_T_41) node _out_wimask_T_41 = bits(out_frontMask, 0, 0) node out_wimask_41 = andr(_out_wimask_T_41) node _out_romask_T_41 = bits(out_backMask, 0, 0) node out_romask_41 = orr(_out_romask_T_41) node _out_womask_T_41 = bits(out_backMask, 0, 0) node out_womask_41 = andr(_out_womask_T_41) node out_f_rivalid_41 = and(out_rivalid[41], out_rimask_41) node out_f_roready_41 = and(out_roready[41], out_romask_41) node out_f_wivalid_41 = and(out_wivalid[41], out_wimask_41) node out_f_woready_41 = and(out_woready[41], out_womask_41) node _out_T_493 = bits(out_back_front_q.io.deq.bits.data, 0, 0) node _out_T_494 = and(out_f_rivalid_41, UInt<1>(0h1)) node _out_T_495 = and(UInt<1>(0h1), out_f_roready_41) node _out_T_496 = eq(out_rimask_41, UInt<1>(0h0)) node _out_T_497 = eq(out_wimask_41, UInt<1>(0h0)) node _out_T_498 = eq(out_romask_41, UInt<1>(0h0)) node _out_T_499 = eq(out_womask_41, UInt<1>(0h0)) node _out_T_500 = or(UInt<1>(0h0), UInt<1>(0h0)) node _out_T_501 = bits(_out_T_500, 0, 0) node _out_rimask_T_42 = bits(out_frontMask, 1, 1) node out_rimask_42 = orr(_out_rimask_T_42) node _out_wimask_T_42 = bits(out_frontMask, 1, 1) node out_wimask_42 = andr(_out_wimask_T_42) node _out_romask_T_42 = bits(out_backMask, 1, 1) node out_romask_42 = orr(_out_romask_T_42) node _out_womask_T_42 = bits(out_backMask, 1, 1) node out_womask_42 = andr(_out_womask_T_42) node out_f_rivalid_42 = and(out_rivalid[42], out_rimask_42) node out_f_roready_42 = and(out_roready[42], out_romask_42) node out_f_wivalid_42 = and(out_wivalid[42], out_wimask_42) node out_f_woready_42 = and(out_woready[42], out_womask_42) node _out_T_502 = bits(out_back_front_q.io.deq.bits.data, 1, 1) when out_f_woready_42 : connect enables_5_0, _out_T_502 node _out_T_503 = and(out_f_rivalid_42, UInt<1>(0h1)) node _out_T_504 = and(UInt<1>(0h1), out_f_roready_42) node _out_T_505 = and(out_f_wivalid_42, UInt<1>(0h1)) node _out_T_506 = and(UInt<1>(0h1), out_f_woready_42) node _out_T_507 = eq(out_rimask_42, UInt<1>(0h0)) node _out_T_508 = eq(out_wimask_42, UInt<1>(0h0)) node _out_T_509 = eq(out_romask_42, UInt<1>(0h0)) node _out_T_510 = eq(out_womask_42, UInt<1>(0h0)) node _out_prepend_T_25 = or(_out_T_501, UInt<1>(0h0)) node out_prepend_25 = cat(enables_5_0, _out_prepend_T_25) node _out_T_511 = or(out_prepend_25, UInt<2>(0h0)) node _out_T_512 = bits(_out_T_511, 1, 0) node _out_iindex_T = bits(out_front.bits.index, 0, 0) node _out_iindex_T_1 = bits(out_front.bits.index, 1, 1) node _out_iindex_T_2 = bits(out_front.bits.index, 2, 2) node _out_iindex_T_3 = bits(out_front.bits.index, 3, 3) node _out_iindex_T_4 = bits(out_front.bits.index, 4, 4) node _out_iindex_T_5 = bits(out_front.bits.index, 5, 5) node _out_iindex_T_6 = bits(out_front.bits.index, 6, 6) node _out_iindex_T_7 = bits(out_front.bits.index, 7, 7) node _out_iindex_T_8 = bits(out_front.bits.index, 8, 8) node _out_iindex_T_9 = bits(out_front.bits.index, 9, 9) node _out_iindex_T_10 = bits(out_front.bits.index, 10, 10) node _out_iindex_T_11 = bits(out_front.bits.index, 11, 11) node _out_iindex_T_12 = bits(out_front.bits.index, 12, 12) node _out_iindex_T_13 = bits(out_front.bits.index, 13, 13) node _out_iindex_T_14 = bits(out_front.bits.index, 14, 14) node _out_iindex_T_15 = bits(out_front.bits.index, 15, 15) node _out_iindex_T_16 = bits(out_front.bits.index, 16, 16) node _out_iindex_T_17 = bits(out_front.bits.index, 17, 17) node _out_iindex_T_18 = bits(out_front.bits.index, 18, 18) node _out_iindex_T_19 = bits(out_front.bits.index, 19, 19) node _out_iindex_T_20 = bits(out_front.bits.index, 20, 20) node _out_iindex_T_21 = bits(out_front.bits.index, 21, 21) node _out_iindex_T_22 = bits(out_front.bits.index, 22, 22) node out_iindex_lo_hi = cat(_out_iindex_T_6, _out_iindex_T_5) node out_iindex_lo = cat(out_iindex_lo_hi, _out_iindex_T_4) node out_iindex_hi_lo = cat(_out_iindex_T_10, _out_iindex_T_9) node out_iindex_hi_hi = cat(_out_iindex_T_18, _out_iindex_T_11) node out_iindex_hi = cat(out_iindex_hi_hi, out_iindex_hi_lo) node out_iindex = cat(out_iindex_hi, out_iindex_lo) node _out_oindex_T = bits(out_back_front_q.io.deq.bits.index, 0, 0) node _out_oindex_T_1 = bits(out_back_front_q.io.deq.bits.index, 1, 1) node _out_oindex_T_2 = bits(out_back_front_q.io.deq.bits.index, 2, 2) node _out_oindex_T_3 = bits(out_back_front_q.io.deq.bits.index, 3, 3) node _out_oindex_T_4 = bits(out_back_front_q.io.deq.bits.index, 4, 4) node _out_oindex_T_5 = bits(out_back_front_q.io.deq.bits.index, 5, 5) node _out_oindex_T_6 = bits(out_back_front_q.io.deq.bits.index, 6, 6) node _out_oindex_T_7 = bits(out_back_front_q.io.deq.bits.index, 7, 7) node _out_oindex_T_8 = bits(out_back_front_q.io.deq.bits.index, 8, 8) node _out_oindex_T_9 = bits(out_back_front_q.io.deq.bits.index, 9, 9) node _out_oindex_T_10 = bits(out_back_front_q.io.deq.bits.index, 10, 10) node _out_oindex_T_11 = bits(out_back_front_q.io.deq.bits.index, 11, 11) node _out_oindex_T_12 = bits(out_back_front_q.io.deq.bits.index, 12, 12) node _out_oindex_T_13 = bits(out_back_front_q.io.deq.bits.index, 13, 13) node _out_oindex_T_14 = bits(out_back_front_q.io.deq.bits.index, 14, 14) node _out_oindex_T_15 = bits(out_back_front_q.io.deq.bits.index, 15, 15) node _out_oindex_T_16 = bits(out_back_front_q.io.deq.bits.index, 16, 16) node _out_oindex_T_17 = bits(out_back_front_q.io.deq.bits.index, 17, 17) node _out_oindex_T_18 = bits(out_back_front_q.io.deq.bits.index, 18, 18) node _out_oindex_T_19 = bits(out_back_front_q.io.deq.bits.index, 19, 19) node _out_oindex_T_20 = bits(out_back_front_q.io.deq.bits.index, 20, 20) node _out_oindex_T_21 = bits(out_back_front_q.io.deq.bits.index, 21, 21) node _out_oindex_T_22 = bits(out_back_front_q.io.deq.bits.index, 22, 22) node out_oindex_lo_hi = cat(_out_oindex_T_6, _out_oindex_T_5) node out_oindex_lo = cat(out_oindex_lo_hi, _out_oindex_T_4) node out_oindex_hi_lo = cat(_out_oindex_T_10, _out_oindex_T_9) node out_oindex_hi_hi = cat(_out_oindex_T_18, _out_oindex_T_11) node out_oindex_hi = cat(out_oindex_hi_hi, out_oindex_hi_lo) node out_oindex = cat(out_oindex_hi, out_oindex_lo) node _out_frontSel_T = dshl(UInt<1>(0h1), out_iindex) node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) node out_frontSel_2 = bits(_out_frontSel_T, 2, 2) node out_frontSel_3 = bits(_out_frontSel_T, 3, 3) node out_frontSel_4 = bits(_out_frontSel_T, 4, 4) node out_frontSel_5 = bits(_out_frontSel_T, 5, 5) node out_frontSel_6 = bits(_out_frontSel_T, 6, 6) node out_frontSel_7 = bits(_out_frontSel_T, 7, 7) node out_frontSel_8 = bits(_out_frontSel_T, 8, 8) node out_frontSel_9 = bits(_out_frontSel_T, 9, 9) node out_frontSel_10 = bits(_out_frontSel_T, 10, 10) node out_frontSel_11 = bits(_out_frontSel_T, 11, 11) node out_frontSel_12 = bits(_out_frontSel_T, 12, 12) node out_frontSel_13 = bits(_out_frontSel_T, 13, 13) node out_frontSel_14 = bits(_out_frontSel_T, 14, 14) node out_frontSel_15 = bits(_out_frontSel_T, 15, 15) node out_frontSel_16 = bits(_out_frontSel_T, 16, 16) node out_frontSel_17 = bits(_out_frontSel_T, 17, 17) node out_frontSel_18 = bits(_out_frontSel_T, 18, 18) node out_frontSel_19 = bits(_out_frontSel_T, 19, 19) node out_frontSel_20 = bits(_out_frontSel_T, 20, 20) node out_frontSel_21 = bits(_out_frontSel_T, 21, 21) node out_frontSel_22 = bits(_out_frontSel_T, 22, 22) node out_frontSel_23 = bits(_out_frontSel_T, 23, 23) node out_frontSel_24 = bits(_out_frontSel_T, 24, 24) node out_frontSel_25 = bits(_out_frontSel_T, 25, 25) node out_frontSel_26 = bits(_out_frontSel_T, 26, 26) node out_frontSel_27 = bits(_out_frontSel_T, 27, 27) node out_frontSel_28 = bits(_out_frontSel_T, 28, 28) node out_frontSel_29 = bits(_out_frontSel_T, 29, 29) node out_frontSel_30 = bits(_out_frontSel_T, 30, 30) node out_frontSel_31 = bits(_out_frontSel_T, 31, 31) node out_frontSel_32 = bits(_out_frontSel_T, 32, 32) node out_frontSel_33 = bits(_out_frontSel_T, 33, 33) node out_frontSel_34 = bits(_out_frontSel_T, 34, 34) node out_frontSel_35 = bits(_out_frontSel_T, 35, 35) node out_frontSel_36 = bits(_out_frontSel_T, 36, 36) node out_frontSel_37 = bits(_out_frontSel_T, 37, 37) node out_frontSel_38 = bits(_out_frontSel_T, 38, 38) node out_frontSel_39 = bits(_out_frontSel_T, 39, 39) node out_frontSel_40 = bits(_out_frontSel_T, 40, 40) node out_frontSel_41 = bits(_out_frontSel_T, 41, 41) node out_frontSel_42 = bits(_out_frontSel_T, 42, 42) node out_frontSel_43 = bits(_out_frontSel_T, 43, 43) node out_frontSel_44 = bits(_out_frontSel_T, 44, 44) node out_frontSel_45 = bits(_out_frontSel_T, 45, 45) node out_frontSel_46 = bits(_out_frontSel_T, 46, 46) node out_frontSel_47 = bits(_out_frontSel_T, 47, 47) node out_frontSel_48 = bits(_out_frontSel_T, 48, 48) node out_frontSel_49 = bits(_out_frontSel_T, 49, 49) node out_frontSel_50 = bits(_out_frontSel_T, 50, 50) node out_frontSel_51 = bits(_out_frontSel_T, 51, 51) node out_frontSel_52 = bits(_out_frontSel_T, 52, 52) node out_frontSel_53 = bits(_out_frontSel_T, 53, 53) node out_frontSel_54 = bits(_out_frontSel_T, 54, 54) node out_frontSel_55 = bits(_out_frontSel_T, 55, 55) node out_frontSel_56 = bits(_out_frontSel_T, 56, 56) node out_frontSel_57 = bits(_out_frontSel_T, 57, 57) node out_frontSel_58 = bits(_out_frontSel_T, 58, 58) node out_frontSel_59 = bits(_out_frontSel_T, 59, 59) node out_frontSel_60 = bits(_out_frontSel_T, 60, 60) node out_frontSel_61 = bits(_out_frontSel_T, 61, 61) node out_frontSel_62 = bits(_out_frontSel_T, 62, 62) node out_frontSel_63 = bits(_out_frontSel_T, 63, 63) node out_frontSel_64 = bits(_out_frontSel_T, 64, 64) node out_frontSel_65 = bits(_out_frontSel_T, 65, 65) node out_frontSel_66 = bits(_out_frontSel_T, 66, 66) node out_frontSel_67 = bits(_out_frontSel_T, 67, 67) node out_frontSel_68 = bits(_out_frontSel_T, 68, 68) node out_frontSel_69 = bits(_out_frontSel_T, 69, 69) node out_frontSel_70 = bits(_out_frontSel_T, 70, 70) node out_frontSel_71 = bits(_out_frontSel_T, 71, 71) node out_frontSel_72 = bits(_out_frontSel_T, 72, 72) node out_frontSel_73 = bits(_out_frontSel_T, 73, 73) node out_frontSel_74 = bits(_out_frontSel_T, 74, 74) node out_frontSel_75 = bits(_out_frontSel_T, 75, 75) node out_frontSel_76 = bits(_out_frontSel_T, 76, 76) node out_frontSel_77 = bits(_out_frontSel_T, 77, 77) node out_frontSel_78 = bits(_out_frontSel_T, 78, 78) node out_frontSel_79 = bits(_out_frontSel_T, 79, 79) node out_frontSel_80 = bits(_out_frontSel_T, 80, 80) node out_frontSel_81 = bits(_out_frontSel_T, 81, 81) node out_frontSel_82 = bits(_out_frontSel_T, 82, 82) node out_frontSel_83 = bits(_out_frontSel_T, 83, 83) node out_frontSel_84 = bits(_out_frontSel_T, 84, 84) node out_frontSel_85 = bits(_out_frontSel_T, 85, 85) node out_frontSel_86 = bits(_out_frontSel_T, 86, 86) node out_frontSel_87 = bits(_out_frontSel_T, 87, 87) node out_frontSel_88 = bits(_out_frontSel_T, 88, 88) node out_frontSel_89 = bits(_out_frontSel_T, 89, 89) node out_frontSel_90 = bits(_out_frontSel_T, 90, 90) node out_frontSel_91 = bits(_out_frontSel_T, 91, 91) node out_frontSel_92 = bits(_out_frontSel_T, 92, 92) node out_frontSel_93 = bits(_out_frontSel_T, 93, 93) node out_frontSel_94 = bits(_out_frontSel_T, 94, 94) node out_frontSel_95 = bits(_out_frontSel_T, 95, 95) node out_frontSel_96 = bits(_out_frontSel_T, 96, 96) node out_frontSel_97 = bits(_out_frontSel_T, 97, 97) node out_frontSel_98 = bits(_out_frontSel_T, 98, 98) node out_frontSel_99 = bits(_out_frontSel_T, 99, 99) node out_frontSel_100 = bits(_out_frontSel_T, 100, 100) node out_frontSel_101 = bits(_out_frontSel_T, 101, 101) node out_frontSel_102 = bits(_out_frontSel_T, 102, 102) node out_frontSel_103 = bits(_out_frontSel_T, 103, 103) node out_frontSel_104 = bits(_out_frontSel_T, 104, 104) node out_frontSel_105 = bits(_out_frontSel_T, 105, 105) node out_frontSel_106 = bits(_out_frontSel_T, 106, 106) node out_frontSel_107 = bits(_out_frontSel_T, 107, 107) node out_frontSel_108 = bits(_out_frontSel_T, 108, 108) node out_frontSel_109 = bits(_out_frontSel_T, 109, 109) node out_frontSel_110 = bits(_out_frontSel_T, 110, 110) node out_frontSel_111 = bits(_out_frontSel_T, 111, 111) node out_frontSel_112 = bits(_out_frontSel_T, 112, 112) node out_frontSel_113 = bits(_out_frontSel_T, 113, 113) node out_frontSel_114 = bits(_out_frontSel_T, 114, 114) node out_frontSel_115 = bits(_out_frontSel_T, 115, 115) node out_frontSel_116 = bits(_out_frontSel_T, 116, 116) node out_frontSel_117 = bits(_out_frontSel_T, 117, 117) node out_frontSel_118 = bits(_out_frontSel_T, 118, 118) node out_frontSel_119 = bits(_out_frontSel_T, 119, 119) node out_frontSel_120 = bits(_out_frontSel_T, 120, 120) node out_frontSel_121 = bits(_out_frontSel_T, 121, 121) node out_frontSel_122 = bits(_out_frontSel_T, 122, 122) node out_frontSel_123 = bits(_out_frontSel_T, 123, 123) node out_frontSel_124 = bits(_out_frontSel_T, 124, 124) node out_frontSel_125 = bits(_out_frontSel_T, 125, 125) node out_frontSel_126 = bits(_out_frontSel_T, 126, 126) node out_frontSel_127 = bits(_out_frontSel_T, 127, 127) node _out_backSel_T = dshl(UInt<1>(0h1), out_oindex) node out_backSel_0 = bits(_out_backSel_T, 0, 0) node out_backSel_1 = bits(_out_backSel_T, 1, 1) node out_backSel_2 = bits(_out_backSel_T, 2, 2) node out_backSel_3 = bits(_out_backSel_T, 3, 3) node out_backSel_4 = bits(_out_backSel_T, 4, 4) node out_backSel_5 = bits(_out_backSel_T, 5, 5) node out_backSel_6 = bits(_out_backSel_T, 6, 6) node out_backSel_7 = bits(_out_backSel_T, 7, 7) node out_backSel_8 = bits(_out_backSel_T, 8, 8) node out_backSel_9 = bits(_out_backSel_T, 9, 9) node out_backSel_10 = bits(_out_backSel_T, 10, 10) node out_backSel_11 = bits(_out_backSel_T, 11, 11) node out_backSel_12 = bits(_out_backSel_T, 12, 12) node out_backSel_13 = bits(_out_backSel_T, 13, 13) node out_backSel_14 = bits(_out_backSel_T, 14, 14) node out_backSel_15 = bits(_out_backSel_T, 15, 15) node out_backSel_16 = bits(_out_backSel_T, 16, 16) node out_backSel_17 = bits(_out_backSel_T, 17, 17) node out_backSel_18 = bits(_out_backSel_T, 18, 18) node out_backSel_19 = bits(_out_backSel_T, 19, 19) node out_backSel_20 = bits(_out_backSel_T, 20, 20) node out_backSel_21 = bits(_out_backSel_T, 21, 21) node out_backSel_22 = bits(_out_backSel_T, 22, 22) node out_backSel_23 = bits(_out_backSel_T, 23, 23) node out_backSel_24 = bits(_out_backSel_T, 24, 24) node out_backSel_25 = bits(_out_backSel_T, 25, 25) node out_backSel_26 = bits(_out_backSel_T, 26, 26) node out_backSel_27 = bits(_out_backSel_T, 27, 27) node out_backSel_28 = bits(_out_backSel_T, 28, 28) node out_backSel_29 = bits(_out_backSel_T, 29, 29) node out_backSel_30 = bits(_out_backSel_T, 30, 30) node out_backSel_31 = bits(_out_backSel_T, 31, 31) node out_backSel_32 = bits(_out_backSel_T, 32, 32) node out_backSel_33 = bits(_out_backSel_T, 33, 33) node out_backSel_34 = bits(_out_backSel_T, 34, 34) node out_backSel_35 = bits(_out_backSel_T, 35, 35) node out_backSel_36 = bits(_out_backSel_T, 36, 36) node out_backSel_37 = bits(_out_backSel_T, 37, 37) node out_backSel_38 = bits(_out_backSel_T, 38, 38) node out_backSel_39 = bits(_out_backSel_T, 39, 39) node out_backSel_40 = bits(_out_backSel_T, 40, 40) node out_backSel_41 = bits(_out_backSel_T, 41, 41) node out_backSel_42 = bits(_out_backSel_T, 42, 42) node out_backSel_43 = bits(_out_backSel_T, 43, 43) node out_backSel_44 = bits(_out_backSel_T, 44, 44) node out_backSel_45 = bits(_out_backSel_T, 45, 45) node out_backSel_46 = bits(_out_backSel_T, 46, 46) node out_backSel_47 = bits(_out_backSel_T, 47, 47) node out_backSel_48 = bits(_out_backSel_T, 48, 48) node out_backSel_49 = bits(_out_backSel_T, 49, 49) node out_backSel_50 = bits(_out_backSel_T, 50, 50) node out_backSel_51 = bits(_out_backSel_T, 51, 51) node out_backSel_52 = bits(_out_backSel_T, 52, 52) node out_backSel_53 = bits(_out_backSel_T, 53, 53) node out_backSel_54 = bits(_out_backSel_T, 54, 54) node out_backSel_55 = bits(_out_backSel_T, 55, 55) node out_backSel_56 = bits(_out_backSel_T, 56, 56) node out_backSel_57 = bits(_out_backSel_T, 57, 57) node out_backSel_58 = bits(_out_backSel_T, 58, 58) node out_backSel_59 = bits(_out_backSel_T, 59, 59) node out_backSel_60 = bits(_out_backSel_T, 60, 60) node out_backSel_61 = bits(_out_backSel_T, 61, 61) node out_backSel_62 = bits(_out_backSel_T, 62, 62) node out_backSel_63 = bits(_out_backSel_T, 63, 63) node out_backSel_64 = bits(_out_backSel_T, 64, 64) node out_backSel_65 = bits(_out_backSel_T, 65, 65) node out_backSel_66 = bits(_out_backSel_T, 66, 66) node out_backSel_67 = bits(_out_backSel_T, 67, 67) node out_backSel_68 = bits(_out_backSel_T, 68, 68) node out_backSel_69 = bits(_out_backSel_T, 69, 69) node out_backSel_70 = bits(_out_backSel_T, 70, 70) node out_backSel_71 = bits(_out_backSel_T, 71, 71) node out_backSel_72 = bits(_out_backSel_T, 72, 72) node out_backSel_73 = bits(_out_backSel_T, 73, 73) node out_backSel_74 = bits(_out_backSel_T, 74, 74) node out_backSel_75 = bits(_out_backSel_T, 75, 75) node out_backSel_76 = bits(_out_backSel_T, 76, 76) node out_backSel_77 = bits(_out_backSel_T, 77, 77) node out_backSel_78 = bits(_out_backSel_T, 78, 78) node out_backSel_79 = bits(_out_backSel_T, 79, 79) node out_backSel_80 = bits(_out_backSel_T, 80, 80) node out_backSel_81 = bits(_out_backSel_T, 81, 81) node out_backSel_82 = bits(_out_backSel_T, 82, 82) node out_backSel_83 = bits(_out_backSel_T, 83, 83) node out_backSel_84 = bits(_out_backSel_T, 84, 84) node out_backSel_85 = bits(_out_backSel_T, 85, 85) node out_backSel_86 = bits(_out_backSel_T, 86, 86) node out_backSel_87 = bits(_out_backSel_T, 87, 87) node out_backSel_88 = bits(_out_backSel_T, 88, 88) node out_backSel_89 = bits(_out_backSel_T, 89, 89) node out_backSel_90 = bits(_out_backSel_T, 90, 90) node out_backSel_91 = bits(_out_backSel_T, 91, 91) node out_backSel_92 = bits(_out_backSel_T, 92, 92) node out_backSel_93 = bits(_out_backSel_T, 93, 93) node out_backSel_94 = bits(_out_backSel_T, 94, 94) node out_backSel_95 = bits(_out_backSel_T, 95, 95) node out_backSel_96 = bits(_out_backSel_T, 96, 96) node out_backSel_97 = bits(_out_backSel_T, 97, 97) node out_backSel_98 = bits(_out_backSel_T, 98, 98) node out_backSel_99 = bits(_out_backSel_T, 99, 99) node out_backSel_100 = bits(_out_backSel_T, 100, 100) node out_backSel_101 = bits(_out_backSel_T, 101, 101) node out_backSel_102 = bits(_out_backSel_T, 102, 102) node out_backSel_103 = bits(_out_backSel_T, 103, 103) node out_backSel_104 = bits(_out_backSel_T, 104, 104) node out_backSel_105 = bits(_out_backSel_T, 105, 105) node out_backSel_106 = bits(_out_backSel_T, 106, 106) node out_backSel_107 = bits(_out_backSel_T, 107, 107) node out_backSel_108 = bits(_out_backSel_T, 108, 108) node out_backSel_109 = bits(_out_backSel_T, 109, 109) node out_backSel_110 = bits(_out_backSel_T, 110, 110) node out_backSel_111 = bits(_out_backSel_T, 111, 111) node out_backSel_112 = bits(_out_backSel_T, 112, 112) node out_backSel_113 = bits(_out_backSel_T, 113, 113) node out_backSel_114 = bits(_out_backSel_T, 114, 114) node out_backSel_115 = bits(_out_backSel_T, 115, 115) node out_backSel_116 = bits(_out_backSel_T, 116, 116) node out_backSel_117 = bits(_out_backSel_T, 117, 117) node out_backSel_118 = bits(_out_backSel_T, 118, 118) node out_backSel_119 = bits(_out_backSel_T, 119, 119) node out_backSel_120 = bits(_out_backSel_T, 120, 120) node out_backSel_121 = bits(_out_backSel_T, 121, 121) node out_backSel_122 = bits(_out_backSel_T, 122, 122) node out_backSel_123 = bits(_out_backSel_T, 123, 123) node out_backSel_124 = bits(_out_backSel_T, 124, 124) node out_backSel_125 = bits(_out_backSel_T, 125, 125) node out_backSel_126 = bits(_out_backSel_T, 126, 126) node out_backSel_127 = bits(_out_backSel_T, 127, 127) node _out_rifireMux_T = and(in.valid, out_front.ready) node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) wire out_rifireMux_out : UInt<1> node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T_26) connect out_rifireMux_out, UInt<1>(0h1) connect out_rivalid[34], _out_rifireMux_T_3 node _out_rifireMux_T_4 = eq(_out_T_26, UInt<1>(0h0)) node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) wire out_rifireMux_out_1 : UInt<1> node _out_rifireMux_T_6 = and(_out_rifireMux_T_1, out_frontSel_1) node _out_rifireMux_T_7 = and(_out_rifireMux_T_6, UInt<1>(0h1)) connect out_rifireMux_out_1, UInt<1>(0h1) node _out_rifireMux_T_8 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_9 = or(out_rifireMux_out_1, _out_rifireMux_T_8) wire out_rifireMux_out_2 : UInt<1> node _out_rifireMux_T_10 = and(_out_rifireMux_T_1, out_frontSel_2) node _out_rifireMux_T_11 = and(_out_rifireMux_T_10, UInt<1>(0h1)) connect out_rifireMux_out_2, UInt<1>(0h1) node _out_rifireMux_T_12 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_13 = or(out_rifireMux_out_2, _out_rifireMux_T_12) wire out_rifireMux_out_3 : UInt<1> node _out_rifireMux_T_14 = and(_out_rifireMux_T_1, out_frontSel_3) node _out_rifireMux_T_15 = and(_out_rifireMux_T_14, UInt<1>(0h1)) connect out_rifireMux_out_3, UInt<1>(0h1) node _out_rifireMux_T_16 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_17 = or(out_rifireMux_out_3, _out_rifireMux_T_16) wire out_rifireMux_out_4 : UInt<1> node _out_rifireMux_T_18 = and(_out_rifireMux_T_1, out_frontSel_4) node _out_rifireMux_T_19 = and(_out_rifireMux_T_18, UInt<1>(0h1)) connect out_rifireMux_out_4, UInt<1>(0h1) node _out_rifireMux_T_20 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_21 = or(out_rifireMux_out_4, _out_rifireMux_T_20) wire out_rifireMux_out_5 : UInt<1> node _out_rifireMux_T_22 = and(_out_rifireMux_T_1, out_frontSel_5) node _out_rifireMux_T_23 = and(_out_rifireMux_T_22, UInt<1>(0h1)) connect out_rifireMux_out_5, UInt<1>(0h1) node _out_rifireMux_T_24 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_25 = or(out_rifireMux_out_5, _out_rifireMux_T_24) wire out_rifireMux_out_6 : UInt<1> node _out_rifireMux_T_26 = and(_out_rifireMux_T_1, out_frontSel_6) node _out_rifireMux_T_27 = and(_out_rifireMux_T_26, UInt<1>(0h1)) connect out_rifireMux_out_6, UInt<1>(0h1) node _out_rifireMux_T_28 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_29 = or(out_rifireMux_out_6, _out_rifireMux_T_28) wire out_rifireMux_out_7 : UInt<1> node _out_rifireMux_T_30 = and(_out_rifireMux_T_1, out_frontSel_7) node _out_rifireMux_T_31 = and(_out_rifireMux_T_30, UInt<1>(0h1)) connect out_rifireMux_out_7, UInt<1>(0h1) node _out_rifireMux_T_32 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_33 = or(out_rifireMux_out_7, _out_rifireMux_T_32) wire out_rifireMux_out_8 : UInt<1> node _out_rifireMux_T_34 = and(_out_rifireMux_T_1, out_frontSel_8) node _out_rifireMux_T_35 = and(_out_rifireMux_T_34, _out_T_2) connect out_rifireMux_out_8, UInt<1>(0h1) connect out_rivalid[4], _out_rifireMux_T_35 connect out_rivalid[3], _out_rifireMux_T_35 node _out_rifireMux_T_36 = eq(_out_T_2, UInt<1>(0h0)) node _out_rifireMux_T_37 = or(out_rifireMux_out_8, _out_rifireMux_T_36) wire out_rifireMux_out_9 : UInt<1> node _out_rifireMux_T_38 = and(_out_rifireMux_T_1, out_frontSel_9) node _out_rifireMux_T_39 = and(_out_rifireMux_T_38, UInt<1>(0h1)) connect out_rifireMux_out_9, UInt<1>(0h1) node _out_rifireMux_T_40 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_41 = or(out_rifireMux_out_9, _out_rifireMux_T_40) wire out_rifireMux_out_10 : UInt<1> node _out_rifireMux_T_42 = and(_out_rifireMux_T_1, out_frontSel_10) node _out_rifireMux_T_43 = and(_out_rifireMux_T_42, UInt<1>(0h1)) connect out_rifireMux_out_10, UInt<1>(0h1) node _out_rifireMux_T_44 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_45 = or(out_rifireMux_out_10, _out_rifireMux_T_44) wire out_rifireMux_out_11 : UInt<1> node _out_rifireMux_T_46 = and(_out_rifireMux_T_1, out_frontSel_11) node _out_rifireMux_T_47 = and(_out_rifireMux_T_46, UInt<1>(0h1)) connect out_rifireMux_out_11, UInt<1>(0h1) node _out_rifireMux_T_48 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_49 = or(out_rifireMux_out_11, _out_rifireMux_T_48) wire out_rifireMux_out_12 : UInt<1> node _out_rifireMux_T_50 = and(_out_rifireMux_T_1, out_frontSel_12) node _out_rifireMux_T_51 = and(_out_rifireMux_T_50, UInt<1>(0h1)) connect out_rifireMux_out_12, UInt<1>(0h1) node _out_rifireMux_T_52 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_53 = or(out_rifireMux_out_12, _out_rifireMux_T_52) wire out_rifireMux_out_13 : UInt<1> node _out_rifireMux_T_54 = and(_out_rifireMux_T_1, out_frontSel_13) node _out_rifireMux_T_55 = and(_out_rifireMux_T_54, UInt<1>(0h1)) connect out_rifireMux_out_13, UInt<1>(0h1) node _out_rifireMux_T_56 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_57 = or(out_rifireMux_out_13, _out_rifireMux_T_56) wire out_rifireMux_out_14 : UInt<1> node _out_rifireMux_T_58 = and(_out_rifireMux_T_1, out_frontSel_14) node _out_rifireMux_T_59 = and(_out_rifireMux_T_58, UInt<1>(0h1)) connect out_rifireMux_out_14, UInt<1>(0h1) node _out_rifireMux_T_60 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_61 = or(out_rifireMux_out_14, _out_rifireMux_T_60) wire out_rifireMux_out_15 : UInt<1> node _out_rifireMux_T_62 = and(_out_rifireMux_T_1, out_frontSel_15) node _out_rifireMux_T_63 = and(_out_rifireMux_T_62, UInt<1>(0h1)) connect out_rifireMux_out_15, UInt<1>(0h1) node _out_rifireMux_T_64 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_65 = or(out_rifireMux_out_15, _out_rifireMux_T_64) wire out_rifireMux_out_16 : UInt<1> node _out_rifireMux_T_66 = and(_out_rifireMux_T_1, out_frontSel_16) node _out_rifireMux_T_67 = and(_out_rifireMux_T_66, _out_T_24) connect out_rifireMux_out_16, UInt<1>(0h1) connect out_rivalid[33], _out_rifireMux_T_67 connect out_rivalid[32], _out_rifireMux_T_67 node _out_rifireMux_T_68 = eq(_out_T_24, UInt<1>(0h0)) node _out_rifireMux_T_69 = or(out_rifireMux_out_16, _out_rifireMux_T_68) wire out_rifireMux_out_17 : UInt<1> node _out_rifireMux_T_70 = and(_out_rifireMux_T_1, out_frontSel_17) node _out_rifireMux_T_71 = and(_out_rifireMux_T_70, _out_T_28) connect out_rifireMux_out_17, UInt<1>(0h1) connect out_rivalid[36], _out_rifireMux_T_71 connect out_rivalid[35], _out_rifireMux_T_71 node _out_rifireMux_T_72 = eq(_out_T_28, UInt<1>(0h0)) node _out_rifireMux_T_73 = or(out_rifireMux_out_17, _out_rifireMux_T_72) wire out_rifireMux_out_18 : UInt<1> node _out_rifireMux_T_74 = and(_out_rifireMux_T_1, out_frontSel_18) node _out_rifireMux_T_75 = and(_out_rifireMux_T_74, _out_T_18) connect out_rifireMux_out_18, UInt<1>(0h1) connect out_rivalid[27], _out_rifireMux_T_75 connect out_rivalid[26], _out_rifireMux_T_75 node _out_rifireMux_T_76 = eq(_out_T_18, UInt<1>(0h0)) node _out_rifireMux_T_77 = or(out_rifireMux_out_18, _out_rifireMux_T_76) wire out_rifireMux_out_19 : UInt<1> node _out_rifireMux_T_78 = and(_out_rifireMux_T_1, out_frontSel_19) node _out_rifireMux_T_79 = and(_out_rifireMux_T_78, _out_T_32) connect out_rifireMux_out_19, UInt<1>(0h1) connect out_rivalid[40], _out_rifireMux_T_79 connect out_rivalid[39], _out_rifireMux_T_79 node _out_rifireMux_T_80 = eq(_out_T_32, UInt<1>(0h0)) node _out_rifireMux_T_81 = or(out_rifireMux_out_19, _out_rifireMux_T_80) wire out_rifireMux_out_20 : UInt<1> node _out_rifireMux_T_82 = and(_out_rifireMux_T_1, out_frontSel_20) node _out_rifireMux_T_83 = and(_out_rifireMux_T_82, _out_T_22) connect out_rifireMux_out_20, UInt<1>(0h1) connect out_rivalid[31], _out_rifireMux_T_83 connect out_rivalid[30], _out_rifireMux_T_83 node _out_rifireMux_T_84 = eq(_out_T_22, UInt<1>(0h0)) node _out_rifireMux_T_85 = or(out_rifireMux_out_20, _out_rifireMux_T_84) wire out_rifireMux_out_21 : UInt<1> node _out_rifireMux_T_86 = and(_out_rifireMux_T_1, out_frontSel_21) node _out_rifireMux_T_87 = and(_out_rifireMux_T_86, _out_T_34) connect out_rifireMux_out_21, UInt<1>(0h1) connect out_rivalid[42], _out_rifireMux_T_87 connect out_rivalid[41], _out_rifireMux_T_87 node _out_rifireMux_T_88 = eq(_out_T_34, UInt<1>(0h0)) node _out_rifireMux_T_89 = or(out_rifireMux_out_21, _out_rifireMux_T_88) wire out_rifireMux_out_22 : UInt<1> node _out_rifireMux_T_90 = and(_out_rifireMux_T_1, out_frontSel_22) node _out_rifireMux_T_91 = and(_out_rifireMux_T_90, _out_T_20) connect out_rifireMux_out_22, UInt<1>(0h1) connect out_rivalid[29], _out_rifireMux_T_91 connect out_rivalid[28], _out_rifireMux_T_91 node _out_rifireMux_T_92 = eq(_out_T_20, UInt<1>(0h0)) node _out_rifireMux_T_93 = or(out_rifireMux_out_22, _out_rifireMux_T_92) wire out_rifireMux_out_23 : UInt<1> node _out_rifireMux_T_94 = and(_out_rifireMux_T_1, out_frontSel_23) node _out_rifireMux_T_95 = and(_out_rifireMux_T_94, _out_T_30) connect out_rifireMux_out_23, UInt<1>(0h1) connect out_rivalid[38], _out_rifireMux_T_95 connect out_rivalid[37], _out_rifireMux_T_95 node _out_rifireMux_T_96 = eq(_out_T_30, UInt<1>(0h0)) node _out_rifireMux_T_97 = or(out_rifireMux_out_23, _out_rifireMux_T_96) wire out_rifireMux_out_24 : UInt<1> node _out_rifireMux_T_98 = and(_out_rifireMux_T_1, out_frontSel_24) node _out_rifireMux_T_99 = and(_out_rifireMux_T_98, UInt<1>(0h1)) connect out_rifireMux_out_24, UInt<1>(0h1) node _out_rifireMux_T_100 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_101 = or(out_rifireMux_out_24, _out_rifireMux_T_100) wire out_rifireMux_out_25 : UInt<1> node _out_rifireMux_T_102 = and(_out_rifireMux_T_1, out_frontSel_25) node _out_rifireMux_T_103 = and(_out_rifireMux_T_102, UInt<1>(0h1)) connect out_rifireMux_out_25, UInt<1>(0h1) node _out_rifireMux_T_104 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_105 = or(out_rifireMux_out_25, _out_rifireMux_T_104) wire out_rifireMux_out_26 : UInt<1> node _out_rifireMux_T_106 = and(_out_rifireMux_T_1, out_frontSel_26) node _out_rifireMux_T_107 = and(_out_rifireMux_T_106, UInt<1>(0h1)) connect out_rifireMux_out_26, UInt<1>(0h1) node _out_rifireMux_T_108 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_109 = or(out_rifireMux_out_26, _out_rifireMux_T_108) wire out_rifireMux_out_27 : UInt<1> node _out_rifireMux_T_110 = and(_out_rifireMux_T_1, out_frontSel_27) node _out_rifireMux_T_111 = and(_out_rifireMux_T_110, UInt<1>(0h1)) connect out_rifireMux_out_27, UInt<1>(0h1) node _out_rifireMux_T_112 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_113 = or(out_rifireMux_out_27, _out_rifireMux_T_112) wire out_rifireMux_out_28 : UInt<1> node _out_rifireMux_T_114 = and(_out_rifireMux_T_1, out_frontSel_28) node _out_rifireMux_T_115 = and(_out_rifireMux_T_114, UInt<1>(0h1)) connect out_rifireMux_out_28, UInt<1>(0h1) node _out_rifireMux_T_116 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_117 = or(out_rifireMux_out_28, _out_rifireMux_T_116) wire out_rifireMux_out_29 : UInt<1> node _out_rifireMux_T_118 = and(_out_rifireMux_T_1, out_frontSel_29) node _out_rifireMux_T_119 = and(_out_rifireMux_T_118, UInt<1>(0h1)) connect out_rifireMux_out_29, UInt<1>(0h1) node _out_rifireMux_T_120 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_121 = or(out_rifireMux_out_29, _out_rifireMux_T_120) wire out_rifireMux_out_30 : UInt<1> node _out_rifireMux_T_122 = and(_out_rifireMux_T_1, out_frontSel_30) node _out_rifireMux_T_123 = and(_out_rifireMux_T_122, UInt<1>(0h1)) connect out_rifireMux_out_30, UInt<1>(0h1) node _out_rifireMux_T_124 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_125 = or(out_rifireMux_out_30, _out_rifireMux_T_124) wire out_rifireMux_out_31 : UInt<1> node _out_rifireMux_T_126 = and(_out_rifireMux_T_1, out_frontSel_31) node _out_rifireMux_T_127 = and(_out_rifireMux_T_126, UInt<1>(0h1)) connect out_rifireMux_out_31, UInt<1>(0h1) node _out_rifireMux_T_128 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_129 = or(out_rifireMux_out_31, _out_rifireMux_T_128) wire out_rifireMux_out_32 : UInt<1> node _out_rifireMux_T_130 = and(_out_rifireMux_T_1, out_frontSel_32) node _out_rifireMux_T_131 = and(_out_rifireMux_T_130, UInt<1>(0h1)) connect out_rifireMux_out_32, UInt<1>(0h1) node _out_rifireMux_T_132 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_133 = or(out_rifireMux_out_32, _out_rifireMux_T_132) wire out_rifireMux_out_33 : UInt<1> node _out_rifireMux_T_134 = and(_out_rifireMux_T_1, out_frontSel_33) node _out_rifireMux_T_135 = and(_out_rifireMux_T_134, UInt<1>(0h1)) connect out_rifireMux_out_33, UInt<1>(0h1) node _out_rifireMux_T_136 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_137 = or(out_rifireMux_out_33, _out_rifireMux_T_136) wire out_rifireMux_out_34 : UInt<1> node _out_rifireMux_T_138 = and(_out_rifireMux_T_1, out_frontSel_34) node _out_rifireMux_T_139 = and(_out_rifireMux_T_138, UInt<1>(0h1)) connect out_rifireMux_out_34, UInt<1>(0h1) node _out_rifireMux_T_140 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_141 = or(out_rifireMux_out_34, _out_rifireMux_T_140) wire out_rifireMux_out_35 : UInt<1> node _out_rifireMux_T_142 = and(_out_rifireMux_T_1, out_frontSel_35) node _out_rifireMux_T_143 = and(_out_rifireMux_T_142, UInt<1>(0h1)) connect out_rifireMux_out_35, UInt<1>(0h1) node _out_rifireMux_T_144 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_145 = or(out_rifireMux_out_35, _out_rifireMux_T_144) wire out_rifireMux_out_36 : UInt<1> node _out_rifireMux_T_146 = and(_out_rifireMux_T_1, out_frontSel_36) node _out_rifireMux_T_147 = and(_out_rifireMux_T_146, UInt<1>(0h1)) connect out_rifireMux_out_36, UInt<1>(0h1) node _out_rifireMux_T_148 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_149 = or(out_rifireMux_out_36, _out_rifireMux_T_148) wire out_rifireMux_out_37 : UInt<1> node _out_rifireMux_T_150 = and(_out_rifireMux_T_1, out_frontSel_37) node _out_rifireMux_T_151 = and(_out_rifireMux_T_150, UInt<1>(0h1)) connect out_rifireMux_out_37, UInt<1>(0h1) node _out_rifireMux_T_152 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_153 = or(out_rifireMux_out_37, _out_rifireMux_T_152) wire out_rifireMux_out_38 : UInt<1> node _out_rifireMux_T_154 = and(_out_rifireMux_T_1, out_frontSel_38) node _out_rifireMux_T_155 = and(_out_rifireMux_T_154, UInt<1>(0h1)) connect out_rifireMux_out_38, UInt<1>(0h1) node _out_rifireMux_T_156 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_157 = or(out_rifireMux_out_38, _out_rifireMux_T_156) wire out_rifireMux_out_39 : UInt<1> node _out_rifireMux_T_158 = and(_out_rifireMux_T_1, out_frontSel_39) node _out_rifireMux_T_159 = and(_out_rifireMux_T_158, UInt<1>(0h1)) connect out_rifireMux_out_39, UInt<1>(0h1) node _out_rifireMux_T_160 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_161 = or(out_rifireMux_out_39, _out_rifireMux_T_160) wire out_rifireMux_out_40 : UInt<1> node _out_rifireMux_T_162 = and(_out_rifireMux_T_1, out_frontSel_40) node _out_rifireMux_T_163 = and(_out_rifireMux_T_162, UInt<1>(0h1)) connect out_rifireMux_out_40, UInt<1>(0h1) node _out_rifireMux_T_164 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_165 = or(out_rifireMux_out_40, _out_rifireMux_T_164) wire out_rifireMux_out_41 : UInt<1> node _out_rifireMux_T_166 = and(_out_rifireMux_T_1, out_frontSel_41) node _out_rifireMux_T_167 = and(_out_rifireMux_T_166, UInt<1>(0h1)) connect out_rifireMux_out_41, UInt<1>(0h1) node _out_rifireMux_T_168 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_169 = or(out_rifireMux_out_41, _out_rifireMux_T_168) wire out_rifireMux_out_42 : UInt<1> node _out_rifireMux_T_170 = and(_out_rifireMux_T_1, out_frontSel_42) node _out_rifireMux_T_171 = and(_out_rifireMux_T_170, UInt<1>(0h1)) connect out_rifireMux_out_42, UInt<1>(0h1) node _out_rifireMux_T_172 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_173 = or(out_rifireMux_out_42, _out_rifireMux_T_172) wire out_rifireMux_out_43 : UInt<1> node _out_rifireMux_T_174 = and(_out_rifireMux_T_1, out_frontSel_43) node _out_rifireMux_T_175 = and(_out_rifireMux_T_174, UInt<1>(0h1)) connect out_rifireMux_out_43, UInt<1>(0h1) node _out_rifireMux_T_176 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_177 = or(out_rifireMux_out_43, _out_rifireMux_T_176) wire out_rifireMux_out_44 : UInt<1> node _out_rifireMux_T_178 = and(_out_rifireMux_T_1, out_frontSel_44) node _out_rifireMux_T_179 = and(_out_rifireMux_T_178, UInt<1>(0h1)) connect out_rifireMux_out_44, UInt<1>(0h1) node _out_rifireMux_T_180 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_181 = or(out_rifireMux_out_44, _out_rifireMux_T_180) wire out_rifireMux_out_45 : UInt<1> node _out_rifireMux_T_182 = and(_out_rifireMux_T_1, out_frontSel_45) node _out_rifireMux_T_183 = and(_out_rifireMux_T_182, UInt<1>(0h1)) connect out_rifireMux_out_45, UInt<1>(0h1) node _out_rifireMux_T_184 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_185 = or(out_rifireMux_out_45, _out_rifireMux_T_184) wire out_rifireMux_out_46 : UInt<1> node _out_rifireMux_T_186 = and(_out_rifireMux_T_1, out_frontSel_46) node _out_rifireMux_T_187 = and(_out_rifireMux_T_186, UInt<1>(0h1)) connect out_rifireMux_out_46, UInt<1>(0h1) node _out_rifireMux_T_188 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_189 = or(out_rifireMux_out_46, _out_rifireMux_T_188) wire out_rifireMux_out_47 : UInt<1> node _out_rifireMux_T_190 = and(_out_rifireMux_T_1, out_frontSel_47) node _out_rifireMux_T_191 = and(_out_rifireMux_T_190, UInt<1>(0h1)) connect out_rifireMux_out_47, UInt<1>(0h1) node _out_rifireMux_T_192 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_193 = or(out_rifireMux_out_47, _out_rifireMux_T_192) wire out_rifireMux_out_48 : UInt<1> node _out_rifireMux_T_194 = and(_out_rifireMux_T_1, out_frontSel_48) node _out_rifireMux_T_195 = and(_out_rifireMux_T_194, UInt<1>(0h1)) connect out_rifireMux_out_48, UInt<1>(0h1) node _out_rifireMux_T_196 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_197 = or(out_rifireMux_out_48, _out_rifireMux_T_196) wire out_rifireMux_out_49 : UInt<1> node _out_rifireMux_T_198 = and(_out_rifireMux_T_1, out_frontSel_49) node _out_rifireMux_T_199 = and(_out_rifireMux_T_198, UInt<1>(0h1)) connect out_rifireMux_out_49, UInt<1>(0h1) node _out_rifireMux_T_200 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_201 = or(out_rifireMux_out_49, _out_rifireMux_T_200) wire out_rifireMux_out_50 : UInt<1> node _out_rifireMux_T_202 = and(_out_rifireMux_T_1, out_frontSel_50) node _out_rifireMux_T_203 = and(_out_rifireMux_T_202, UInt<1>(0h1)) connect out_rifireMux_out_50, UInt<1>(0h1) node _out_rifireMux_T_204 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_205 = or(out_rifireMux_out_50, _out_rifireMux_T_204) wire out_rifireMux_out_51 : UInt<1> node _out_rifireMux_T_206 = and(_out_rifireMux_T_1, out_frontSel_51) node _out_rifireMux_T_207 = and(_out_rifireMux_T_206, UInt<1>(0h1)) connect out_rifireMux_out_51, UInt<1>(0h1) node _out_rifireMux_T_208 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_209 = or(out_rifireMux_out_51, _out_rifireMux_T_208) wire out_rifireMux_out_52 : UInt<1> node _out_rifireMux_T_210 = and(_out_rifireMux_T_1, out_frontSel_52) node _out_rifireMux_T_211 = and(_out_rifireMux_T_210, UInt<1>(0h1)) connect out_rifireMux_out_52, UInt<1>(0h1) node _out_rifireMux_T_212 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_213 = or(out_rifireMux_out_52, _out_rifireMux_T_212) wire out_rifireMux_out_53 : UInt<1> node _out_rifireMux_T_214 = and(_out_rifireMux_T_1, out_frontSel_53) node _out_rifireMux_T_215 = and(_out_rifireMux_T_214, UInt<1>(0h1)) connect out_rifireMux_out_53, UInt<1>(0h1) node _out_rifireMux_T_216 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_217 = or(out_rifireMux_out_53, _out_rifireMux_T_216) wire out_rifireMux_out_54 : UInt<1> node _out_rifireMux_T_218 = and(_out_rifireMux_T_1, out_frontSel_54) node _out_rifireMux_T_219 = and(_out_rifireMux_T_218, UInt<1>(0h1)) connect out_rifireMux_out_54, UInt<1>(0h1) node _out_rifireMux_T_220 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_221 = or(out_rifireMux_out_54, _out_rifireMux_T_220) wire out_rifireMux_out_55 : UInt<1> node _out_rifireMux_T_222 = and(_out_rifireMux_T_1, out_frontSel_55) node _out_rifireMux_T_223 = and(_out_rifireMux_T_222, UInt<1>(0h1)) connect out_rifireMux_out_55, UInt<1>(0h1) node _out_rifireMux_T_224 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_225 = or(out_rifireMux_out_55, _out_rifireMux_T_224) wire out_rifireMux_out_56 : UInt<1> node _out_rifireMux_T_226 = and(_out_rifireMux_T_1, out_frontSel_56) node _out_rifireMux_T_227 = and(_out_rifireMux_T_226, UInt<1>(0h1)) connect out_rifireMux_out_56, UInt<1>(0h1) node _out_rifireMux_T_228 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_229 = or(out_rifireMux_out_56, _out_rifireMux_T_228) wire out_rifireMux_out_57 : UInt<1> node _out_rifireMux_T_230 = and(_out_rifireMux_T_1, out_frontSel_57) node _out_rifireMux_T_231 = and(_out_rifireMux_T_230, UInt<1>(0h1)) connect out_rifireMux_out_57, UInt<1>(0h1) node _out_rifireMux_T_232 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_233 = or(out_rifireMux_out_57, _out_rifireMux_T_232) wire out_rifireMux_out_58 : UInt<1> node _out_rifireMux_T_234 = and(_out_rifireMux_T_1, out_frontSel_58) node _out_rifireMux_T_235 = and(_out_rifireMux_T_234, UInt<1>(0h1)) connect out_rifireMux_out_58, UInt<1>(0h1) node _out_rifireMux_T_236 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_237 = or(out_rifireMux_out_58, _out_rifireMux_T_236) wire out_rifireMux_out_59 : UInt<1> node _out_rifireMux_T_238 = and(_out_rifireMux_T_1, out_frontSel_59) node _out_rifireMux_T_239 = and(_out_rifireMux_T_238, UInt<1>(0h1)) connect out_rifireMux_out_59, UInt<1>(0h1) node _out_rifireMux_T_240 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_241 = or(out_rifireMux_out_59, _out_rifireMux_T_240) wire out_rifireMux_out_60 : UInt<1> node _out_rifireMux_T_242 = and(_out_rifireMux_T_1, out_frontSel_60) node _out_rifireMux_T_243 = and(_out_rifireMux_T_242, UInt<1>(0h1)) connect out_rifireMux_out_60, UInt<1>(0h1) node _out_rifireMux_T_244 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_245 = or(out_rifireMux_out_60, _out_rifireMux_T_244) wire out_rifireMux_out_61 : UInt<1> node _out_rifireMux_T_246 = and(_out_rifireMux_T_1, out_frontSel_61) node _out_rifireMux_T_247 = and(_out_rifireMux_T_246, UInt<1>(0h1)) connect out_rifireMux_out_61, UInt<1>(0h1) node _out_rifireMux_T_248 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_249 = or(out_rifireMux_out_61, _out_rifireMux_T_248) wire out_rifireMux_out_62 : UInt<1> node _out_rifireMux_T_250 = and(_out_rifireMux_T_1, out_frontSel_62) node _out_rifireMux_T_251 = and(_out_rifireMux_T_250, UInt<1>(0h1)) connect out_rifireMux_out_62, UInt<1>(0h1) node _out_rifireMux_T_252 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_253 = or(out_rifireMux_out_62, _out_rifireMux_T_252) wire out_rifireMux_out_63 : UInt<1> node _out_rifireMux_T_254 = and(_out_rifireMux_T_1, out_frontSel_63) node _out_rifireMux_T_255 = and(_out_rifireMux_T_254, UInt<1>(0h1)) connect out_rifireMux_out_63, UInt<1>(0h1) node _out_rifireMux_T_256 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_257 = or(out_rifireMux_out_63, _out_rifireMux_T_256) wire out_rifireMux_out_64 : UInt<1> node _out_rifireMux_T_258 = and(_out_rifireMux_T_1, out_frontSel_64) node _out_rifireMux_T_259 = and(_out_rifireMux_T_258, _out_T_12) connect out_rifireMux_out_64, UInt<1>(0h1) connect out_rivalid[19], _out_rifireMux_T_259 connect out_rivalid[18], _out_rifireMux_T_259 connect out_rivalid[17], _out_rifireMux_T_259 node _out_rifireMux_T_260 = eq(_out_T_12, UInt<1>(0h0)) node _out_rifireMux_T_261 = or(out_rifireMux_out_64, _out_rifireMux_T_260) wire out_rifireMux_out_65 : UInt<1> node _out_rifireMux_T_262 = and(_out_rifireMux_T_1, out_frontSel_65) node _out_rifireMux_T_263 = and(_out_rifireMux_T_262, UInt<1>(0h1)) connect out_rifireMux_out_65, UInt<1>(0h1) node _out_rifireMux_T_264 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_265 = or(out_rifireMux_out_65, _out_rifireMux_T_264) wire out_rifireMux_out_66 : UInt<1> node _out_rifireMux_T_266 = and(_out_rifireMux_T_1, out_frontSel_66) node _out_rifireMux_T_267 = and(_out_rifireMux_T_266, UInt<1>(0h1)) connect out_rifireMux_out_66, UInt<1>(0h1) node _out_rifireMux_T_268 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_269 = or(out_rifireMux_out_66, _out_rifireMux_T_268) wire out_rifireMux_out_67 : UInt<1> node _out_rifireMux_T_270 = and(_out_rifireMux_T_1, out_frontSel_67) node _out_rifireMux_T_271 = and(_out_rifireMux_T_270, UInt<1>(0h1)) connect out_rifireMux_out_67, UInt<1>(0h1) node _out_rifireMux_T_272 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_273 = or(out_rifireMux_out_67, _out_rifireMux_T_272) wire out_rifireMux_out_68 : UInt<1> node _out_rifireMux_T_274 = and(_out_rifireMux_T_1, out_frontSel_68) node _out_rifireMux_T_275 = and(_out_rifireMux_T_274, UInt<1>(0h1)) connect out_rifireMux_out_68, UInt<1>(0h1) node _out_rifireMux_T_276 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_277 = or(out_rifireMux_out_68, _out_rifireMux_T_276) wire out_rifireMux_out_69 : UInt<1> node _out_rifireMux_T_278 = and(_out_rifireMux_T_1, out_frontSel_69) node _out_rifireMux_T_279 = and(_out_rifireMux_T_278, UInt<1>(0h1)) connect out_rifireMux_out_69, UInt<1>(0h1) node _out_rifireMux_T_280 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_281 = or(out_rifireMux_out_69, _out_rifireMux_T_280) wire out_rifireMux_out_70 : UInt<1> node _out_rifireMux_T_282 = and(_out_rifireMux_T_1, out_frontSel_70) node _out_rifireMux_T_283 = and(_out_rifireMux_T_282, UInt<1>(0h1)) connect out_rifireMux_out_70, UInt<1>(0h1) node _out_rifireMux_T_284 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_285 = or(out_rifireMux_out_70, _out_rifireMux_T_284) wire out_rifireMux_out_71 : UInt<1> node _out_rifireMux_T_286 = and(_out_rifireMux_T_1, out_frontSel_71) node _out_rifireMux_T_287 = and(_out_rifireMux_T_286, UInt<1>(0h1)) connect out_rifireMux_out_71, UInt<1>(0h1) node _out_rifireMux_T_288 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_289 = or(out_rifireMux_out_71, _out_rifireMux_T_288) wire out_rifireMux_out_72 : UInt<1> node _out_rifireMux_T_290 = and(_out_rifireMux_T_1, out_frontSel_72) node _out_rifireMux_T_291 = and(_out_rifireMux_T_290, _out_T_6) connect out_rifireMux_out_72, UInt<1>(0h1) connect out_rivalid[10], _out_rifireMux_T_291 connect out_rivalid[9], _out_rifireMux_T_291 connect out_rivalid[8], _out_rifireMux_T_291 node _out_rifireMux_T_292 = eq(_out_T_6, UInt<1>(0h0)) node _out_rifireMux_T_293 = or(out_rifireMux_out_72, _out_rifireMux_T_292) wire out_rifireMux_out_73 : UInt<1> node _out_rifireMux_T_294 = and(_out_rifireMux_T_1, out_frontSel_73) node _out_rifireMux_T_295 = and(_out_rifireMux_T_294, UInt<1>(0h1)) connect out_rifireMux_out_73, UInt<1>(0h1) node _out_rifireMux_T_296 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_297 = or(out_rifireMux_out_73, _out_rifireMux_T_296) wire out_rifireMux_out_74 : UInt<1> node _out_rifireMux_T_298 = and(_out_rifireMux_T_1, out_frontSel_74) node _out_rifireMux_T_299 = and(_out_rifireMux_T_298, UInt<1>(0h1)) connect out_rifireMux_out_74, UInt<1>(0h1) node _out_rifireMux_T_300 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_301 = or(out_rifireMux_out_74, _out_rifireMux_T_300) wire out_rifireMux_out_75 : UInt<1> node _out_rifireMux_T_302 = and(_out_rifireMux_T_1, out_frontSel_75) node _out_rifireMux_T_303 = and(_out_rifireMux_T_302, UInt<1>(0h1)) connect out_rifireMux_out_75, UInt<1>(0h1) node _out_rifireMux_T_304 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_305 = or(out_rifireMux_out_75, _out_rifireMux_T_304) wire out_rifireMux_out_76 : UInt<1> node _out_rifireMux_T_306 = and(_out_rifireMux_T_1, out_frontSel_76) node _out_rifireMux_T_307 = and(_out_rifireMux_T_306, UInt<1>(0h1)) connect out_rifireMux_out_76, UInt<1>(0h1) node _out_rifireMux_T_308 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_309 = or(out_rifireMux_out_76, _out_rifireMux_T_308) wire out_rifireMux_out_77 : UInt<1> node _out_rifireMux_T_310 = and(_out_rifireMux_T_1, out_frontSel_77) node _out_rifireMux_T_311 = and(_out_rifireMux_T_310, UInt<1>(0h1)) connect out_rifireMux_out_77, UInt<1>(0h1) node _out_rifireMux_T_312 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_313 = or(out_rifireMux_out_77, _out_rifireMux_T_312) wire out_rifireMux_out_78 : UInt<1> node _out_rifireMux_T_314 = and(_out_rifireMux_T_1, out_frontSel_78) node _out_rifireMux_T_315 = and(_out_rifireMux_T_314, UInt<1>(0h1)) connect out_rifireMux_out_78, UInt<1>(0h1) node _out_rifireMux_T_316 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_317 = or(out_rifireMux_out_78, _out_rifireMux_T_316) wire out_rifireMux_out_79 : UInt<1> node _out_rifireMux_T_318 = and(_out_rifireMux_T_1, out_frontSel_79) node _out_rifireMux_T_319 = and(_out_rifireMux_T_318, UInt<1>(0h1)) connect out_rifireMux_out_79, UInt<1>(0h1) node _out_rifireMux_T_320 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_321 = or(out_rifireMux_out_79, _out_rifireMux_T_320) wire out_rifireMux_out_80 : UInt<1> node _out_rifireMux_T_322 = and(_out_rifireMux_T_1, out_frontSel_80) node _out_rifireMux_T_323 = and(_out_rifireMux_T_322, _out_T_14) connect out_rifireMux_out_80, UInt<1>(0h1) connect out_rivalid[22], _out_rifireMux_T_323 connect out_rivalid[21], _out_rifireMux_T_323 connect out_rivalid[20], _out_rifireMux_T_323 node _out_rifireMux_T_324 = eq(_out_T_14, UInt<1>(0h0)) node _out_rifireMux_T_325 = or(out_rifireMux_out_80, _out_rifireMux_T_324) wire out_rifireMux_out_81 : UInt<1> node _out_rifireMux_T_326 = and(_out_rifireMux_T_1, out_frontSel_81) node _out_rifireMux_T_327 = and(_out_rifireMux_T_326, UInt<1>(0h1)) connect out_rifireMux_out_81, UInt<1>(0h1) node _out_rifireMux_T_328 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_329 = or(out_rifireMux_out_81, _out_rifireMux_T_328) wire out_rifireMux_out_82 : UInt<1> node _out_rifireMux_T_330 = and(_out_rifireMux_T_1, out_frontSel_82) node _out_rifireMux_T_331 = and(_out_rifireMux_T_330, UInt<1>(0h1)) connect out_rifireMux_out_82, UInt<1>(0h1) node _out_rifireMux_T_332 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_333 = or(out_rifireMux_out_82, _out_rifireMux_T_332) wire out_rifireMux_out_83 : UInt<1> node _out_rifireMux_T_334 = and(_out_rifireMux_T_1, out_frontSel_83) node _out_rifireMux_T_335 = and(_out_rifireMux_T_334, UInt<1>(0h1)) connect out_rifireMux_out_83, UInt<1>(0h1) node _out_rifireMux_T_336 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_337 = or(out_rifireMux_out_83, _out_rifireMux_T_336) wire out_rifireMux_out_84 : UInt<1> node _out_rifireMux_T_338 = and(_out_rifireMux_T_1, out_frontSel_84) node _out_rifireMux_T_339 = and(_out_rifireMux_T_338, UInt<1>(0h1)) connect out_rifireMux_out_84, UInt<1>(0h1) node _out_rifireMux_T_340 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_341 = or(out_rifireMux_out_84, _out_rifireMux_T_340) wire out_rifireMux_out_85 : UInt<1> node _out_rifireMux_T_342 = and(_out_rifireMux_T_1, out_frontSel_85) node _out_rifireMux_T_343 = and(_out_rifireMux_T_342, UInt<1>(0h1)) connect out_rifireMux_out_85, UInt<1>(0h1) node _out_rifireMux_T_344 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_345 = or(out_rifireMux_out_85, _out_rifireMux_T_344) wire out_rifireMux_out_86 : UInt<1> node _out_rifireMux_T_346 = and(_out_rifireMux_T_1, out_frontSel_86) node _out_rifireMux_T_347 = and(_out_rifireMux_T_346, UInt<1>(0h1)) connect out_rifireMux_out_86, UInt<1>(0h1) node _out_rifireMux_T_348 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_349 = or(out_rifireMux_out_86, _out_rifireMux_T_348) wire out_rifireMux_out_87 : UInt<1> node _out_rifireMux_T_350 = and(_out_rifireMux_T_1, out_frontSel_87) node _out_rifireMux_T_351 = and(_out_rifireMux_T_350, UInt<1>(0h1)) connect out_rifireMux_out_87, UInt<1>(0h1) node _out_rifireMux_T_352 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_353 = or(out_rifireMux_out_87, _out_rifireMux_T_352) wire out_rifireMux_out_88 : UInt<1> node _out_rifireMux_T_354 = and(_out_rifireMux_T_1, out_frontSel_88) node _out_rifireMux_T_355 = and(_out_rifireMux_T_354, _out_T_8) connect out_rifireMux_out_88, UInt<1>(0h1) connect out_rivalid[13], _out_rifireMux_T_355 connect out_rivalid[12], _out_rifireMux_T_355 connect out_rivalid[11], _out_rifireMux_T_355 node _out_rifireMux_T_356 = eq(_out_T_8, UInt<1>(0h0)) node _out_rifireMux_T_357 = or(out_rifireMux_out_88, _out_rifireMux_T_356) wire out_rifireMux_out_89 : UInt<1> node _out_rifireMux_T_358 = and(_out_rifireMux_T_1, out_frontSel_89) node _out_rifireMux_T_359 = and(_out_rifireMux_T_358, UInt<1>(0h1)) connect out_rifireMux_out_89, UInt<1>(0h1) node _out_rifireMux_T_360 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_361 = or(out_rifireMux_out_89, _out_rifireMux_T_360) wire out_rifireMux_out_90 : UInt<1> node _out_rifireMux_T_362 = and(_out_rifireMux_T_1, out_frontSel_90) node _out_rifireMux_T_363 = and(_out_rifireMux_T_362, UInt<1>(0h1)) connect out_rifireMux_out_90, UInt<1>(0h1) node _out_rifireMux_T_364 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_365 = or(out_rifireMux_out_90, _out_rifireMux_T_364) wire out_rifireMux_out_91 : UInt<1> node _out_rifireMux_T_366 = and(_out_rifireMux_T_1, out_frontSel_91) node _out_rifireMux_T_367 = and(_out_rifireMux_T_366, UInt<1>(0h1)) connect out_rifireMux_out_91, UInt<1>(0h1) node _out_rifireMux_T_368 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_369 = or(out_rifireMux_out_91, _out_rifireMux_T_368) wire out_rifireMux_out_92 : UInt<1> node _out_rifireMux_T_370 = and(_out_rifireMux_T_1, out_frontSel_92) node _out_rifireMux_T_371 = and(_out_rifireMux_T_370, UInt<1>(0h1)) connect out_rifireMux_out_92, UInt<1>(0h1) node _out_rifireMux_T_372 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_373 = or(out_rifireMux_out_92, _out_rifireMux_T_372) wire out_rifireMux_out_93 : UInt<1> node _out_rifireMux_T_374 = and(_out_rifireMux_T_1, out_frontSel_93) node _out_rifireMux_T_375 = and(_out_rifireMux_T_374, UInt<1>(0h1)) connect out_rifireMux_out_93, UInt<1>(0h1) node _out_rifireMux_T_376 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_377 = or(out_rifireMux_out_93, _out_rifireMux_T_376) wire out_rifireMux_out_94 : UInt<1> node _out_rifireMux_T_378 = and(_out_rifireMux_T_1, out_frontSel_94) node _out_rifireMux_T_379 = and(_out_rifireMux_T_378, UInt<1>(0h1)) connect out_rifireMux_out_94, UInt<1>(0h1) node _out_rifireMux_T_380 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_381 = or(out_rifireMux_out_94, _out_rifireMux_T_380) wire out_rifireMux_out_95 : UInt<1> node _out_rifireMux_T_382 = and(_out_rifireMux_T_1, out_frontSel_95) node _out_rifireMux_T_383 = and(_out_rifireMux_T_382, UInt<1>(0h1)) connect out_rifireMux_out_95, UInt<1>(0h1) node _out_rifireMux_T_384 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_385 = or(out_rifireMux_out_95, _out_rifireMux_T_384) wire out_rifireMux_out_96 : UInt<1> node _out_rifireMux_T_386 = and(_out_rifireMux_T_1, out_frontSel_96) node _out_rifireMux_T_387 = and(_out_rifireMux_T_386, _out_T_4) connect out_rifireMux_out_96, UInt<1>(0h1) connect out_rivalid[7], _out_rifireMux_T_387 connect out_rivalid[6], _out_rifireMux_T_387 connect out_rivalid[5], _out_rifireMux_T_387 node _out_rifireMux_T_388 = eq(_out_T_4, UInt<1>(0h0)) node _out_rifireMux_T_389 = or(out_rifireMux_out_96, _out_rifireMux_T_388) wire out_rifireMux_out_97 : UInt<1> node _out_rifireMux_T_390 = and(_out_rifireMux_T_1, out_frontSel_97) node _out_rifireMux_T_391 = and(_out_rifireMux_T_390, UInt<1>(0h1)) connect out_rifireMux_out_97, UInt<1>(0h1) node _out_rifireMux_T_392 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_393 = or(out_rifireMux_out_97, _out_rifireMux_T_392) wire out_rifireMux_out_98 : UInt<1> node _out_rifireMux_T_394 = and(_out_rifireMux_T_1, out_frontSel_98) node _out_rifireMux_T_395 = and(_out_rifireMux_T_394, UInt<1>(0h1)) connect out_rifireMux_out_98, UInt<1>(0h1) node _out_rifireMux_T_396 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_397 = or(out_rifireMux_out_98, _out_rifireMux_T_396) wire out_rifireMux_out_99 : UInt<1> node _out_rifireMux_T_398 = and(_out_rifireMux_T_1, out_frontSel_99) node _out_rifireMux_T_399 = and(_out_rifireMux_T_398, UInt<1>(0h1)) connect out_rifireMux_out_99, UInt<1>(0h1) node _out_rifireMux_T_400 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_401 = or(out_rifireMux_out_99, _out_rifireMux_T_400) wire out_rifireMux_out_100 : UInt<1> node _out_rifireMux_T_402 = and(_out_rifireMux_T_1, out_frontSel_100) node _out_rifireMux_T_403 = and(_out_rifireMux_T_402, UInt<1>(0h1)) connect out_rifireMux_out_100, UInt<1>(0h1) node _out_rifireMux_T_404 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_405 = or(out_rifireMux_out_100, _out_rifireMux_T_404) wire out_rifireMux_out_101 : UInt<1> node _out_rifireMux_T_406 = and(_out_rifireMux_T_1, out_frontSel_101) node _out_rifireMux_T_407 = and(_out_rifireMux_T_406, UInt<1>(0h1)) connect out_rifireMux_out_101, UInt<1>(0h1) node _out_rifireMux_T_408 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_409 = or(out_rifireMux_out_101, _out_rifireMux_T_408) wire out_rifireMux_out_102 : UInt<1> node _out_rifireMux_T_410 = and(_out_rifireMux_T_1, out_frontSel_102) node _out_rifireMux_T_411 = and(_out_rifireMux_T_410, UInt<1>(0h1)) connect out_rifireMux_out_102, UInt<1>(0h1) node _out_rifireMux_T_412 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_413 = or(out_rifireMux_out_102, _out_rifireMux_T_412) wire out_rifireMux_out_103 : UInt<1> node _out_rifireMux_T_414 = and(_out_rifireMux_T_1, out_frontSel_103) node _out_rifireMux_T_415 = and(_out_rifireMux_T_414, UInt<1>(0h1)) connect out_rifireMux_out_103, UInt<1>(0h1) node _out_rifireMux_T_416 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_417 = or(out_rifireMux_out_103, _out_rifireMux_T_416) wire out_rifireMux_out_104 : UInt<1> node _out_rifireMux_T_418 = and(_out_rifireMux_T_1, out_frontSel_104) node _out_rifireMux_T_419 = and(_out_rifireMux_T_418, _out_T) connect out_rifireMux_out_104, UInt<1>(0h1) connect out_rivalid[2], _out_rifireMux_T_419 connect out_rivalid[1], _out_rifireMux_T_419 connect out_rivalid[0], _out_rifireMux_T_419 node _out_rifireMux_T_420 = eq(_out_T, UInt<1>(0h0)) node _out_rifireMux_T_421 = or(out_rifireMux_out_104, _out_rifireMux_T_420) wire out_rifireMux_out_105 : UInt<1> node _out_rifireMux_T_422 = and(_out_rifireMux_T_1, out_frontSel_105) node _out_rifireMux_T_423 = and(_out_rifireMux_T_422, UInt<1>(0h1)) connect out_rifireMux_out_105, UInt<1>(0h1) node _out_rifireMux_T_424 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_425 = or(out_rifireMux_out_105, _out_rifireMux_T_424) wire out_rifireMux_out_106 : UInt<1> node _out_rifireMux_T_426 = and(_out_rifireMux_T_1, out_frontSel_106) node _out_rifireMux_T_427 = and(_out_rifireMux_T_426, UInt<1>(0h1)) connect out_rifireMux_out_106, UInt<1>(0h1) node _out_rifireMux_T_428 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_429 = or(out_rifireMux_out_106, _out_rifireMux_T_428) wire out_rifireMux_out_107 : UInt<1> node _out_rifireMux_T_430 = and(_out_rifireMux_T_1, out_frontSel_107) node _out_rifireMux_T_431 = and(_out_rifireMux_T_430, UInt<1>(0h1)) connect out_rifireMux_out_107, UInt<1>(0h1) node _out_rifireMux_T_432 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_433 = or(out_rifireMux_out_107, _out_rifireMux_T_432) wire out_rifireMux_out_108 : UInt<1> node _out_rifireMux_T_434 = and(_out_rifireMux_T_1, out_frontSel_108) node _out_rifireMux_T_435 = and(_out_rifireMux_T_434, UInt<1>(0h1)) connect out_rifireMux_out_108, UInt<1>(0h1) node _out_rifireMux_T_436 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_437 = or(out_rifireMux_out_108, _out_rifireMux_T_436) wire out_rifireMux_out_109 : UInt<1> node _out_rifireMux_T_438 = and(_out_rifireMux_T_1, out_frontSel_109) node _out_rifireMux_T_439 = and(_out_rifireMux_T_438, UInt<1>(0h1)) connect out_rifireMux_out_109, UInt<1>(0h1) node _out_rifireMux_T_440 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_441 = or(out_rifireMux_out_109, _out_rifireMux_T_440) wire out_rifireMux_out_110 : UInt<1> node _out_rifireMux_T_442 = and(_out_rifireMux_T_1, out_frontSel_110) node _out_rifireMux_T_443 = and(_out_rifireMux_T_442, UInt<1>(0h1)) connect out_rifireMux_out_110, UInt<1>(0h1) node _out_rifireMux_T_444 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_445 = or(out_rifireMux_out_110, _out_rifireMux_T_444) wire out_rifireMux_out_111 : UInt<1> node _out_rifireMux_T_446 = and(_out_rifireMux_T_1, out_frontSel_111) node _out_rifireMux_T_447 = and(_out_rifireMux_T_446, UInt<1>(0h1)) connect out_rifireMux_out_111, UInt<1>(0h1) node _out_rifireMux_T_448 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_449 = or(out_rifireMux_out_111, _out_rifireMux_T_448) wire out_rifireMux_out_112 : UInt<1> node _out_rifireMux_T_450 = and(_out_rifireMux_T_1, out_frontSel_112) node _out_rifireMux_T_451 = and(_out_rifireMux_T_450, _out_T_16) connect out_rifireMux_out_112, UInt<1>(0h1) connect out_rivalid[25], _out_rifireMux_T_451 connect out_rivalid[24], _out_rifireMux_T_451 connect out_rivalid[23], _out_rifireMux_T_451 node _out_rifireMux_T_452 = eq(_out_T_16, UInt<1>(0h0)) node _out_rifireMux_T_453 = or(out_rifireMux_out_112, _out_rifireMux_T_452) wire out_rifireMux_out_113 : UInt<1> node _out_rifireMux_T_454 = and(_out_rifireMux_T_1, out_frontSel_113) node _out_rifireMux_T_455 = and(_out_rifireMux_T_454, UInt<1>(0h1)) connect out_rifireMux_out_113, UInt<1>(0h1) node _out_rifireMux_T_456 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_457 = or(out_rifireMux_out_113, _out_rifireMux_T_456) wire out_rifireMux_out_114 : UInt<1> node _out_rifireMux_T_458 = and(_out_rifireMux_T_1, out_frontSel_114) node _out_rifireMux_T_459 = and(_out_rifireMux_T_458, UInt<1>(0h1)) connect out_rifireMux_out_114, UInt<1>(0h1) node _out_rifireMux_T_460 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_461 = or(out_rifireMux_out_114, _out_rifireMux_T_460) wire out_rifireMux_out_115 : UInt<1> node _out_rifireMux_T_462 = and(_out_rifireMux_T_1, out_frontSel_115) node _out_rifireMux_T_463 = and(_out_rifireMux_T_462, UInt<1>(0h1)) connect out_rifireMux_out_115, UInt<1>(0h1) node _out_rifireMux_T_464 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_465 = or(out_rifireMux_out_115, _out_rifireMux_T_464) wire out_rifireMux_out_116 : UInt<1> node _out_rifireMux_T_466 = and(_out_rifireMux_T_1, out_frontSel_116) node _out_rifireMux_T_467 = and(_out_rifireMux_T_466, UInt<1>(0h1)) connect out_rifireMux_out_116, UInt<1>(0h1) node _out_rifireMux_T_468 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_469 = or(out_rifireMux_out_116, _out_rifireMux_T_468) wire out_rifireMux_out_117 : UInt<1> node _out_rifireMux_T_470 = and(_out_rifireMux_T_1, out_frontSel_117) node _out_rifireMux_T_471 = and(_out_rifireMux_T_470, UInt<1>(0h1)) connect out_rifireMux_out_117, UInt<1>(0h1) node _out_rifireMux_T_472 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_473 = or(out_rifireMux_out_117, _out_rifireMux_T_472) wire out_rifireMux_out_118 : UInt<1> node _out_rifireMux_T_474 = and(_out_rifireMux_T_1, out_frontSel_118) node _out_rifireMux_T_475 = and(_out_rifireMux_T_474, UInt<1>(0h1)) connect out_rifireMux_out_118, UInt<1>(0h1) node _out_rifireMux_T_476 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_477 = or(out_rifireMux_out_118, _out_rifireMux_T_476) wire out_rifireMux_out_119 : UInt<1> node _out_rifireMux_T_478 = and(_out_rifireMux_T_1, out_frontSel_119) node _out_rifireMux_T_479 = and(_out_rifireMux_T_478, UInt<1>(0h1)) connect out_rifireMux_out_119, UInt<1>(0h1) node _out_rifireMux_T_480 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_481 = or(out_rifireMux_out_119, _out_rifireMux_T_480) wire out_rifireMux_out_120 : UInt<1> node _out_rifireMux_T_482 = and(_out_rifireMux_T_1, out_frontSel_120) node _out_rifireMux_T_483 = and(_out_rifireMux_T_482, _out_T_10) connect out_rifireMux_out_120, UInt<1>(0h1) connect out_rivalid[16], _out_rifireMux_T_483 connect out_rivalid[15], _out_rifireMux_T_483 connect out_rivalid[14], _out_rifireMux_T_483 node _out_rifireMux_T_484 = eq(_out_T_10, UInt<1>(0h0)) node _out_rifireMux_T_485 = or(out_rifireMux_out_120, _out_rifireMux_T_484) wire out_rifireMux_out_121 : UInt<1> node _out_rifireMux_T_486 = and(_out_rifireMux_T_1, out_frontSel_121) node _out_rifireMux_T_487 = and(_out_rifireMux_T_486, UInt<1>(0h1)) connect out_rifireMux_out_121, UInt<1>(0h1) node _out_rifireMux_T_488 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_489 = or(out_rifireMux_out_121, _out_rifireMux_T_488) wire out_rifireMux_out_122 : UInt<1> node _out_rifireMux_T_490 = and(_out_rifireMux_T_1, out_frontSel_122) node _out_rifireMux_T_491 = and(_out_rifireMux_T_490, UInt<1>(0h1)) connect out_rifireMux_out_122, UInt<1>(0h1) node _out_rifireMux_T_492 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_493 = or(out_rifireMux_out_122, _out_rifireMux_T_492) wire out_rifireMux_out_123 : UInt<1> node _out_rifireMux_T_494 = and(_out_rifireMux_T_1, out_frontSel_123) node _out_rifireMux_T_495 = and(_out_rifireMux_T_494, UInt<1>(0h1)) connect out_rifireMux_out_123, UInt<1>(0h1) node _out_rifireMux_T_496 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_497 = or(out_rifireMux_out_123, _out_rifireMux_T_496) wire out_rifireMux_out_124 : UInt<1> node _out_rifireMux_T_498 = and(_out_rifireMux_T_1, out_frontSel_124) node _out_rifireMux_T_499 = and(_out_rifireMux_T_498, UInt<1>(0h1)) connect out_rifireMux_out_124, UInt<1>(0h1) node _out_rifireMux_T_500 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_501 = or(out_rifireMux_out_124, _out_rifireMux_T_500) wire out_rifireMux_out_125 : UInt<1> node _out_rifireMux_T_502 = and(_out_rifireMux_T_1, out_frontSel_125) node _out_rifireMux_T_503 = and(_out_rifireMux_T_502, UInt<1>(0h1)) connect out_rifireMux_out_125, UInt<1>(0h1) node _out_rifireMux_T_504 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_505 = or(out_rifireMux_out_125, _out_rifireMux_T_504) wire out_rifireMux_out_126 : UInt<1> node _out_rifireMux_T_506 = and(_out_rifireMux_T_1, out_frontSel_126) node _out_rifireMux_T_507 = and(_out_rifireMux_T_506, UInt<1>(0h1)) connect out_rifireMux_out_126, UInt<1>(0h1) node _out_rifireMux_T_508 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_509 = or(out_rifireMux_out_126, _out_rifireMux_T_508) wire out_rifireMux_out_127 : UInt<1> node _out_rifireMux_T_510 = and(_out_rifireMux_T_1, out_frontSel_127) node _out_rifireMux_T_511 = and(_out_rifireMux_T_510, UInt<1>(0h1)) connect out_rifireMux_out_127, UInt<1>(0h1) node _out_rifireMux_T_512 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_513 = or(out_rifireMux_out_127, _out_rifireMux_T_512) node _out_rifireMux_T_514 = geq(out_iindex, UInt<8>(0h80)) wire _out_rifireMux_WIRE : UInt<1>[128] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 connect _out_rifireMux_WIRE[1], _out_rifireMux_T_9 connect _out_rifireMux_WIRE[2], _out_rifireMux_T_13 connect _out_rifireMux_WIRE[3], _out_rifireMux_T_17 connect _out_rifireMux_WIRE[4], _out_rifireMux_T_21 connect _out_rifireMux_WIRE[5], _out_rifireMux_T_25 connect _out_rifireMux_WIRE[6], _out_rifireMux_T_29 connect _out_rifireMux_WIRE[7], _out_rifireMux_T_33 connect _out_rifireMux_WIRE[8], _out_rifireMux_T_37 connect _out_rifireMux_WIRE[9], _out_rifireMux_T_41 connect _out_rifireMux_WIRE[10], _out_rifireMux_T_45 connect _out_rifireMux_WIRE[11], _out_rifireMux_T_49 connect _out_rifireMux_WIRE[12], _out_rifireMux_T_53 connect _out_rifireMux_WIRE[13], _out_rifireMux_T_57 connect _out_rifireMux_WIRE[14], _out_rifireMux_T_61 connect _out_rifireMux_WIRE[15], _out_rifireMux_T_65 connect _out_rifireMux_WIRE[16], _out_rifireMux_T_69 connect _out_rifireMux_WIRE[17], _out_rifireMux_T_73 connect _out_rifireMux_WIRE[18], _out_rifireMux_T_77 connect _out_rifireMux_WIRE[19], _out_rifireMux_T_81 connect _out_rifireMux_WIRE[20], _out_rifireMux_T_85 connect _out_rifireMux_WIRE[21], _out_rifireMux_T_89 connect _out_rifireMux_WIRE[22], _out_rifireMux_T_93 connect _out_rifireMux_WIRE[23], _out_rifireMux_T_97 connect _out_rifireMux_WIRE[24], _out_rifireMux_T_101 connect _out_rifireMux_WIRE[25], _out_rifireMux_T_105 connect _out_rifireMux_WIRE[26], _out_rifireMux_T_109 connect _out_rifireMux_WIRE[27], _out_rifireMux_T_113 connect _out_rifireMux_WIRE[28], _out_rifireMux_T_117 connect _out_rifireMux_WIRE[29], _out_rifireMux_T_121 connect _out_rifireMux_WIRE[30], _out_rifireMux_T_125 connect _out_rifireMux_WIRE[31], _out_rifireMux_T_129 connect _out_rifireMux_WIRE[32], _out_rifireMux_T_133 connect _out_rifireMux_WIRE[33], _out_rifireMux_T_137 connect _out_rifireMux_WIRE[34], _out_rifireMux_T_141 connect _out_rifireMux_WIRE[35], _out_rifireMux_T_145 connect _out_rifireMux_WIRE[36], _out_rifireMux_T_149 connect _out_rifireMux_WIRE[37], _out_rifireMux_T_153 connect _out_rifireMux_WIRE[38], _out_rifireMux_T_157 connect _out_rifireMux_WIRE[39], _out_rifireMux_T_161 connect _out_rifireMux_WIRE[40], _out_rifireMux_T_165 connect _out_rifireMux_WIRE[41], _out_rifireMux_T_169 connect _out_rifireMux_WIRE[42], _out_rifireMux_T_173 connect _out_rifireMux_WIRE[43], _out_rifireMux_T_177 connect _out_rifireMux_WIRE[44], _out_rifireMux_T_181 connect _out_rifireMux_WIRE[45], _out_rifireMux_T_185 connect _out_rifireMux_WIRE[46], _out_rifireMux_T_189 connect _out_rifireMux_WIRE[47], _out_rifireMux_T_193 connect _out_rifireMux_WIRE[48], _out_rifireMux_T_197 connect _out_rifireMux_WIRE[49], _out_rifireMux_T_201 connect _out_rifireMux_WIRE[50], _out_rifireMux_T_205 connect _out_rifireMux_WIRE[51], _out_rifireMux_T_209 connect _out_rifireMux_WIRE[52], _out_rifireMux_T_213 connect _out_rifireMux_WIRE[53], _out_rifireMux_T_217 connect _out_rifireMux_WIRE[54], _out_rifireMux_T_221 connect _out_rifireMux_WIRE[55], _out_rifireMux_T_225 connect _out_rifireMux_WIRE[56], _out_rifireMux_T_229 connect _out_rifireMux_WIRE[57], _out_rifireMux_T_233 connect _out_rifireMux_WIRE[58], _out_rifireMux_T_237 connect _out_rifireMux_WIRE[59], _out_rifireMux_T_241 connect _out_rifireMux_WIRE[60], _out_rifireMux_T_245 connect _out_rifireMux_WIRE[61], _out_rifireMux_T_249 connect _out_rifireMux_WIRE[62], _out_rifireMux_T_253 connect _out_rifireMux_WIRE[63], _out_rifireMux_T_257 connect _out_rifireMux_WIRE[64], _out_rifireMux_T_261 connect _out_rifireMux_WIRE[65], _out_rifireMux_T_265 connect _out_rifireMux_WIRE[66], _out_rifireMux_T_269 connect _out_rifireMux_WIRE[67], _out_rifireMux_T_273 connect _out_rifireMux_WIRE[68], _out_rifireMux_T_277 connect _out_rifireMux_WIRE[69], _out_rifireMux_T_281 connect _out_rifireMux_WIRE[70], _out_rifireMux_T_285 connect _out_rifireMux_WIRE[71], _out_rifireMux_T_289 connect _out_rifireMux_WIRE[72], _out_rifireMux_T_293 connect _out_rifireMux_WIRE[73], _out_rifireMux_T_297 connect _out_rifireMux_WIRE[74], _out_rifireMux_T_301 connect _out_rifireMux_WIRE[75], _out_rifireMux_T_305 connect _out_rifireMux_WIRE[76], _out_rifireMux_T_309 connect _out_rifireMux_WIRE[77], _out_rifireMux_T_313 connect _out_rifireMux_WIRE[78], _out_rifireMux_T_317 connect _out_rifireMux_WIRE[79], _out_rifireMux_T_321 connect _out_rifireMux_WIRE[80], _out_rifireMux_T_325 connect _out_rifireMux_WIRE[81], _out_rifireMux_T_329 connect _out_rifireMux_WIRE[82], _out_rifireMux_T_333 connect _out_rifireMux_WIRE[83], _out_rifireMux_T_337 connect _out_rifireMux_WIRE[84], _out_rifireMux_T_341 connect _out_rifireMux_WIRE[85], _out_rifireMux_T_345 connect _out_rifireMux_WIRE[86], _out_rifireMux_T_349 connect _out_rifireMux_WIRE[87], _out_rifireMux_T_353 connect _out_rifireMux_WIRE[88], _out_rifireMux_T_357 connect _out_rifireMux_WIRE[89], _out_rifireMux_T_361 connect _out_rifireMux_WIRE[90], _out_rifireMux_T_365 connect _out_rifireMux_WIRE[91], _out_rifireMux_T_369 connect _out_rifireMux_WIRE[92], _out_rifireMux_T_373 connect _out_rifireMux_WIRE[93], _out_rifireMux_T_377 connect _out_rifireMux_WIRE[94], _out_rifireMux_T_381 connect _out_rifireMux_WIRE[95], _out_rifireMux_T_385 connect _out_rifireMux_WIRE[96], _out_rifireMux_T_389 connect _out_rifireMux_WIRE[97], _out_rifireMux_T_393 connect _out_rifireMux_WIRE[98], _out_rifireMux_T_397 connect _out_rifireMux_WIRE[99], _out_rifireMux_T_401 connect _out_rifireMux_WIRE[100], _out_rifireMux_T_405 connect _out_rifireMux_WIRE[101], _out_rifireMux_T_409 connect _out_rifireMux_WIRE[102], _out_rifireMux_T_413 connect _out_rifireMux_WIRE[103], _out_rifireMux_T_417 connect _out_rifireMux_WIRE[104], _out_rifireMux_T_421 connect _out_rifireMux_WIRE[105], _out_rifireMux_T_425 connect _out_rifireMux_WIRE[106], _out_rifireMux_T_429 connect _out_rifireMux_WIRE[107], _out_rifireMux_T_433 connect _out_rifireMux_WIRE[108], _out_rifireMux_T_437 connect _out_rifireMux_WIRE[109], _out_rifireMux_T_441 connect _out_rifireMux_WIRE[110], _out_rifireMux_T_445 connect _out_rifireMux_WIRE[111], _out_rifireMux_T_449 connect _out_rifireMux_WIRE[112], _out_rifireMux_T_453 connect _out_rifireMux_WIRE[113], _out_rifireMux_T_457 connect _out_rifireMux_WIRE[114], _out_rifireMux_T_461 connect _out_rifireMux_WIRE[115], _out_rifireMux_T_465 connect _out_rifireMux_WIRE[116], _out_rifireMux_T_469 connect _out_rifireMux_WIRE[117], _out_rifireMux_T_473 connect _out_rifireMux_WIRE[118], _out_rifireMux_T_477 connect _out_rifireMux_WIRE[119], _out_rifireMux_T_481 connect _out_rifireMux_WIRE[120], _out_rifireMux_T_485 connect _out_rifireMux_WIRE[121], _out_rifireMux_T_489 connect _out_rifireMux_WIRE[122], _out_rifireMux_T_493 connect _out_rifireMux_WIRE[123], _out_rifireMux_T_497 connect _out_rifireMux_WIRE[124], _out_rifireMux_T_501 connect _out_rifireMux_WIRE[125], _out_rifireMux_T_505 connect _out_rifireMux_WIRE[126], _out_rifireMux_T_509 connect _out_rifireMux_WIRE[127], _out_rifireMux_T_513 node out_rifireMux = mux(_out_rifireMux_T_514, UInt<1>(0h1), _out_rifireMux_WIRE[out_iindex]) node _out_wifireMux_T = and(in.valid, out_front.ready) node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) wire out_wifireMux_out : UInt<1> node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T_26) connect out_wifireMux_out, UInt<1>(0h1) connect out_wivalid[34], _out_wifireMux_T_4 node _out_wifireMux_T_5 = eq(_out_T_26, UInt<1>(0h0)) node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) wire out_wifireMux_out_1 : UInt<1> node _out_wifireMux_T_7 = and(_out_wifireMux_T_2, out_frontSel_1) node _out_wifireMux_T_8 = and(_out_wifireMux_T_7, UInt<1>(0h1)) connect out_wifireMux_out_1, UInt<1>(0h1) node _out_wifireMux_T_9 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_10 = or(out_wifireMux_out_1, _out_wifireMux_T_9) wire out_wifireMux_out_2 : UInt<1> node _out_wifireMux_T_11 = and(_out_wifireMux_T_2, out_frontSel_2) node _out_wifireMux_T_12 = and(_out_wifireMux_T_11, UInt<1>(0h1)) connect out_wifireMux_out_2, UInt<1>(0h1) node _out_wifireMux_T_13 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_14 = or(out_wifireMux_out_2, _out_wifireMux_T_13) wire out_wifireMux_out_3 : UInt<1> node _out_wifireMux_T_15 = and(_out_wifireMux_T_2, out_frontSel_3) node _out_wifireMux_T_16 = and(_out_wifireMux_T_15, UInt<1>(0h1)) connect out_wifireMux_out_3, UInt<1>(0h1) node _out_wifireMux_T_17 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_18 = or(out_wifireMux_out_3, _out_wifireMux_T_17) wire out_wifireMux_out_4 : UInt<1> node _out_wifireMux_T_19 = and(_out_wifireMux_T_2, out_frontSel_4) node _out_wifireMux_T_20 = and(_out_wifireMux_T_19, UInt<1>(0h1)) connect out_wifireMux_out_4, UInt<1>(0h1) node _out_wifireMux_T_21 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_22 = or(out_wifireMux_out_4, _out_wifireMux_T_21) wire out_wifireMux_out_5 : UInt<1> node _out_wifireMux_T_23 = and(_out_wifireMux_T_2, out_frontSel_5) node _out_wifireMux_T_24 = and(_out_wifireMux_T_23, UInt<1>(0h1)) connect out_wifireMux_out_5, UInt<1>(0h1) node _out_wifireMux_T_25 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_26 = or(out_wifireMux_out_5, _out_wifireMux_T_25) wire out_wifireMux_out_6 : UInt<1> node _out_wifireMux_T_27 = and(_out_wifireMux_T_2, out_frontSel_6) node _out_wifireMux_T_28 = and(_out_wifireMux_T_27, UInt<1>(0h1)) connect out_wifireMux_out_6, UInt<1>(0h1) node _out_wifireMux_T_29 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_30 = or(out_wifireMux_out_6, _out_wifireMux_T_29) wire out_wifireMux_out_7 : UInt<1> node _out_wifireMux_T_31 = and(_out_wifireMux_T_2, out_frontSel_7) node _out_wifireMux_T_32 = and(_out_wifireMux_T_31, UInt<1>(0h1)) connect out_wifireMux_out_7, UInt<1>(0h1) node _out_wifireMux_T_33 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_34 = or(out_wifireMux_out_7, _out_wifireMux_T_33) wire out_wifireMux_out_8 : UInt<1> node _out_wifireMux_T_35 = and(_out_wifireMux_T_2, out_frontSel_8) node _out_wifireMux_T_36 = and(_out_wifireMux_T_35, _out_T_2) connect out_wifireMux_out_8, UInt<1>(0h1) connect out_wivalid[4], _out_wifireMux_T_36 connect out_wivalid[3], _out_wifireMux_T_36 node _out_wifireMux_T_37 = eq(_out_T_2, UInt<1>(0h0)) node _out_wifireMux_T_38 = or(out_wifireMux_out_8, _out_wifireMux_T_37) wire out_wifireMux_out_9 : UInt<1> node _out_wifireMux_T_39 = and(_out_wifireMux_T_2, out_frontSel_9) node _out_wifireMux_T_40 = and(_out_wifireMux_T_39, UInt<1>(0h1)) connect out_wifireMux_out_9, UInt<1>(0h1) node _out_wifireMux_T_41 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_42 = or(out_wifireMux_out_9, _out_wifireMux_T_41) wire out_wifireMux_out_10 : UInt<1> node _out_wifireMux_T_43 = and(_out_wifireMux_T_2, out_frontSel_10) node _out_wifireMux_T_44 = and(_out_wifireMux_T_43, UInt<1>(0h1)) connect out_wifireMux_out_10, UInt<1>(0h1) node _out_wifireMux_T_45 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_46 = or(out_wifireMux_out_10, _out_wifireMux_T_45) wire out_wifireMux_out_11 : UInt<1> node _out_wifireMux_T_47 = and(_out_wifireMux_T_2, out_frontSel_11) node _out_wifireMux_T_48 = and(_out_wifireMux_T_47, UInt<1>(0h1)) connect out_wifireMux_out_11, UInt<1>(0h1) node _out_wifireMux_T_49 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_50 = or(out_wifireMux_out_11, _out_wifireMux_T_49) wire out_wifireMux_out_12 : UInt<1> node _out_wifireMux_T_51 = and(_out_wifireMux_T_2, out_frontSel_12) node _out_wifireMux_T_52 = and(_out_wifireMux_T_51, UInt<1>(0h1)) connect out_wifireMux_out_12, UInt<1>(0h1) node _out_wifireMux_T_53 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_54 = or(out_wifireMux_out_12, _out_wifireMux_T_53) wire out_wifireMux_out_13 : UInt<1> node _out_wifireMux_T_55 = and(_out_wifireMux_T_2, out_frontSel_13) node _out_wifireMux_T_56 = and(_out_wifireMux_T_55, UInt<1>(0h1)) connect out_wifireMux_out_13, UInt<1>(0h1) node _out_wifireMux_T_57 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_58 = or(out_wifireMux_out_13, _out_wifireMux_T_57) wire out_wifireMux_out_14 : UInt<1> node _out_wifireMux_T_59 = and(_out_wifireMux_T_2, out_frontSel_14) node _out_wifireMux_T_60 = and(_out_wifireMux_T_59, UInt<1>(0h1)) connect out_wifireMux_out_14, UInt<1>(0h1) node _out_wifireMux_T_61 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_62 = or(out_wifireMux_out_14, _out_wifireMux_T_61) wire out_wifireMux_out_15 : UInt<1> node _out_wifireMux_T_63 = and(_out_wifireMux_T_2, out_frontSel_15) node _out_wifireMux_T_64 = and(_out_wifireMux_T_63, UInt<1>(0h1)) connect out_wifireMux_out_15, UInt<1>(0h1) node _out_wifireMux_T_65 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_66 = or(out_wifireMux_out_15, _out_wifireMux_T_65) wire out_wifireMux_out_16 : UInt<1> node _out_wifireMux_T_67 = and(_out_wifireMux_T_2, out_frontSel_16) node _out_wifireMux_T_68 = and(_out_wifireMux_T_67, _out_T_24) connect out_wifireMux_out_16, UInt<1>(0h1) connect out_wivalid[33], _out_wifireMux_T_68 connect out_wivalid[32], _out_wifireMux_T_68 node _out_wifireMux_T_69 = eq(_out_T_24, UInt<1>(0h0)) node _out_wifireMux_T_70 = or(out_wifireMux_out_16, _out_wifireMux_T_69) wire out_wifireMux_out_17 : UInt<1> node _out_wifireMux_T_71 = and(_out_wifireMux_T_2, out_frontSel_17) node _out_wifireMux_T_72 = and(_out_wifireMux_T_71, _out_T_28) connect out_wifireMux_out_17, UInt<1>(0h1) connect out_wivalid[36], _out_wifireMux_T_72 connect out_wivalid[35], _out_wifireMux_T_72 node _out_wifireMux_T_73 = eq(_out_T_28, UInt<1>(0h0)) node _out_wifireMux_T_74 = or(out_wifireMux_out_17, _out_wifireMux_T_73) wire out_wifireMux_out_18 : UInt<1> node _out_wifireMux_T_75 = and(_out_wifireMux_T_2, out_frontSel_18) node _out_wifireMux_T_76 = and(_out_wifireMux_T_75, _out_T_18) connect out_wifireMux_out_18, UInt<1>(0h1) connect out_wivalid[27], _out_wifireMux_T_76 connect out_wivalid[26], _out_wifireMux_T_76 node _out_wifireMux_T_77 = eq(_out_T_18, UInt<1>(0h0)) node _out_wifireMux_T_78 = or(out_wifireMux_out_18, _out_wifireMux_T_77) wire out_wifireMux_out_19 : UInt<1> node _out_wifireMux_T_79 = and(_out_wifireMux_T_2, out_frontSel_19) node _out_wifireMux_T_80 = and(_out_wifireMux_T_79, _out_T_32) connect out_wifireMux_out_19, UInt<1>(0h1) connect out_wivalid[40], _out_wifireMux_T_80 connect out_wivalid[39], _out_wifireMux_T_80 node _out_wifireMux_T_81 = eq(_out_T_32, UInt<1>(0h0)) node _out_wifireMux_T_82 = or(out_wifireMux_out_19, _out_wifireMux_T_81) wire out_wifireMux_out_20 : UInt<1> node _out_wifireMux_T_83 = and(_out_wifireMux_T_2, out_frontSel_20) node _out_wifireMux_T_84 = and(_out_wifireMux_T_83, _out_T_22) connect out_wifireMux_out_20, UInt<1>(0h1) connect out_wivalid[31], _out_wifireMux_T_84 connect out_wivalid[30], _out_wifireMux_T_84 node _out_wifireMux_T_85 = eq(_out_T_22, UInt<1>(0h0)) node _out_wifireMux_T_86 = or(out_wifireMux_out_20, _out_wifireMux_T_85) wire out_wifireMux_out_21 : UInt<1> node _out_wifireMux_T_87 = and(_out_wifireMux_T_2, out_frontSel_21) node _out_wifireMux_T_88 = and(_out_wifireMux_T_87, _out_T_34) connect out_wifireMux_out_21, UInt<1>(0h1) connect out_wivalid[42], _out_wifireMux_T_88 connect out_wivalid[41], _out_wifireMux_T_88 node _out_wifireMux_T_89 = eq(_out_T_34, UInt<1>(0h0)) node _out_wifireMux_T_90 = or(out_wifireMux_out_21, _out_wifireMux_T_89) wire out_wifireMux_out_22 : UInt<1> node _out_wifireMux_T_91 = and(_out_wifireMux_T_2, out_frontSel_22) node _out_wifireMux_T_92 = and(_out_wifireMux_T_91, _out_T_20) connect out_wifireMux_out_22, UInt<1>(0h1) connect out_wivalid[29], _out_wifireMux_T_92 connect out_wivalid[28], _out_wifireMux_T_92 node _out_wifireMux_T_93 = eq(_out_T_20, UInt<1>(0h0)) node _out_wifireMux_T_94 = or(out_wifireMux_out_22, _out_wifireMux_T_93) wire out_wifireMux_out_23 : UInt<1> node _out_wifireMux_T_95 = and(_out_wifireMux_T_2, out_frontSel_23) node _out_wifireMux_T_96 = and(_out_wifireMux_T_95, _out_T_30) connect out_wifireMux_out_23, UInt<1>(0h1) connect out_wivalid[38], _out_wifireMux_T_96 connect out_wivalid[37], _out_wifireMux_T_96 node _out_wifireMux_T_97 = eq(_out_T_30, UInt<1>(0h0)) node _out_wifireMux_T_98 = or(out_wifireMux_out_23, _out_wifireMux_T_97) wire out_wifireMux_out_24 : UInt<1> node _out_wifireMux_T_99 = and(_out_wifireMux_T_2, out_frontSel_24) node _out_wifireMux_T_100 = and(_out_wifireMux_T_99, UInt<1>(0h1)) connect out_wifireMux_out_24, UInt<1>(0h1) node _out_wifireMux_T_101 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_102 = or(out_wifireMux_out_24, _out_wifireMux_T_101) wire out_wifireMux_out_25 : UInt<1> node _out_wifireMux_T_103 = and(_out_wifireMux_T_2, out_frontSel_25) node _out_wifireMux_T_104 = and(_out_wifireMux_T_103, UInt<1>(0h1)) connect out_wifireMux_out_25, UInt<1>(0h1) node _out_wifireMux_T_105 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_106 = or(out_wifireMux_out_25, _out_wifireMux_T_105) wire out_wifireMux_out_26 : UInt<1> node _out_wifireMux_T_107 = and(_out_wifireMux_T_2, out_frontSel_26) node _out_wifireMux_T_108 = and(_out_wifireMux_T_107, UInt<1>(0h1)) connect out_wifireMux_out_26, UInt<1>(0h1) node _out_wifireMux_T_109 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_110 = or(out_wifireMux_out_26, _out_wifireMux_T_109) wire out_wifireMux_out_27 : UInt<1> node _out_wifireMux_T_111 = and(_out_wifireMux_T_2, out_frontSel_27) node _out_wifireMux_T_112 = and(_out_wifireMux_T_111, UInt<1>(0h1)) connect out_wifireMux_out_27, UInt<1>(0h1) node _out_wifireMux_T_113 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_114 = or(out_wifireMux_out_27, _out_wifireMux_T_113) wire out_wifireMux_out_28 : UInt<1> node _out_wifireMux_T_115 = and(_out_wifireMux_T_2, out_frontSel_28) node _out_wifireMux_T_116 = and(_out_wifireMux_T_115, UInt<1>(0h1)) connect out_wifireMux_out_28, UInt<1>(0h1) node _out_wifireMux_T_117 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_118 = or(out_wifireMux_out_28, _out_wifireMux_T_117) wire out_wifireMux_out_29 : UInt<1> node _out_wifireMux_T_119 = and(_out_wifireMux_T_2, out_frontSel_29) node _out_wifireMux_T_120 = and(_out_wifireMux_T_119, UInt<1>(0h1)) connect out_wifireMux_out_29, UInt<1>(0h1) node _out_wifireMux_T_121 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_122 = or(out_wifireMux_out_29, _out_wifireMux_T_121) wire out_wifireMux_out_30 : UInt<1> node _out_wifireMux_T_123 = and(_out_wifireMux_T_2, out_frontSel_30) node _out_wifireMux_T_124 = and(_out_wifireMux_T_123, UInt<1>(0h1)) connect out_wifireMux_out_30, UInt<1>(0h1) node _out_wifireMux_T_125 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_126 = or(out_wifireMux_out_30, _out_wifireMux_T_125) wire out_wifireMux_out_31 : UInt<1> node _out_wifireMux_T_127 = and(_out_wifireMux_T_2, out_frontSel_31) node _out_wifireMux_T_128 = and(_out_wifireMux_T_127, UInt<1>(0h1)) connect out_wifireMux_out_31, UInt<1>(0h1) node _out_wifireMux_T_129 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_130 = or(out_wifireMux_out_31, _out_wifireMux_T_129) wire out_wifireMux_out_32 : UInt<1> node _out_wifireMux_T_131 = and(_out_wifireMux_T_2, out_frontSel_32) node _out_wifireMux_T_132 = and(_out_wifireMux_T_131, UInt<1>(0h1)) connect out_wifireMux_out_32, UInt<1>(0h1) node _out_wifireMux_T_133 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_134 = or(out_wifireMux_out_32, _out_wifireMux_T_133) wire out_wifireMux_out_33 : UInt<1> node _out_wifireMux_T_135 = and(_out_wifireMux_T_2, out_frontSel_33) node _out_wifireMux_T_136 = and(_out_wifireMux_T_135, UInt<1>(0h1)) connect out_wifireMux_out_33, UInt<1>(0h1) node _out_wifireMux_T_137 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_138 = or(out_wifireMux_out_33, _out_wifireMux_T_137) wire out_wifireMux_out_34 : UInt<1> node _out_wifireMux_T_139 = and(_out_wifireMux_T_2, out_frontSel_34) node _out_wifireMux_T_140 = and(_out_wifireMux_T_139, UInt<1>(0h1)) connect out_wifireMux_out_34, UInt<1>(0h1) node _out_wifireMux_T_141 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_142 = or(out_wifireMux_out_34, _out_wifireMux_T_141) wire out_wifireMux_out_35 : UInt<1> node _out_wifireMux_T_143 = and(_out_wifireMux_T_2, out_frontSel_35) node _out_wifireMux_T_144 = and(_out_wifireMux_T_143, UInt<1>(0h1)) connect out_wifireMux_out_35, UInt<1>(0h1) node _out_wifireMux_T_145 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_146 = or(out_wifireMux_out_35, _out_wifireMux_T_145) wire out_wifireMux_out_36 : UInt<1> node _out_wifireMux_T_147 = and(_out_wifireMux_T_2, out_frontSel_36) node _out_wifireMux_T_148 = and(_out_wifireMux_T_147, UInt<1>(0h1)) connect out_wifireMux_out_36, UInt<1>(0h1) node _out_wifireMux_T_149 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_150 = or(out_wifireMux_out_36, _out_wifireMux_T_149) wire out_wifireMux_out_37 : UInt<1> node _out_wifireMux_T_151 = and(_out_wifireMux_T_2, out_frontSel_37) node _out_wifireMux_T_152 = and(_out_wifireMux_T_151, UInt<1>(0h1)) connect out_wifireMux_out_37, UInt<1>(0h1) node _out_wifireMux_T_153 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_154 = or(out_wifireMux_out_37, _out_wifireMux_T_153) wire out_wifireMux_out_38 : UInt<1> node _out_wifireMux_T_155 = and(_out_wifireMux_T_2, out_frontSel_38) node _out_wifireMux_T_156 = and(_out_wifireMux_T_155, UInt<1>(0h1)) connect out_wifireMux_out_38, UInt<1>(0h1) node _out_wifireMux_T_157 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_158 = or(out_wifireMux_out_38, _out_wifireMux_T_157) wire out_wifireMux_out_39 : UInt<1> node _out_wifireMux_T_159 = and(_out_wifireMux_T_2, out_frontSel_39) node _out_wifireMux_T_160 = and(_out_wifireMux_T_159, UInt<1>(0h1)) connect out_wifireMux_out_39, UInt<1>(0h1) node _out_wifireMux_T_161 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_162 = or(out_wifireMux_out_39, _out_wifireMux_T_161) wire out_wifireMux_out_40 : UInt<1> node _out_wifireMux_T_163 = and(_out_wifireMux_T_2, out_frontSel_40) node _out_wifireMux_T_164 = and(_out_wifireMux_T_163, UInt<1>(0h1)) connect out_wifireMux_out_40, UInt<1>(0h1) node _out_wifireMux_T_165 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_166 = or(out_wifireMux_out_40, _out_wifireMux_T_165) wire out_wifireMux_out_41 : UInt<1> node _out_wifireMux_T_167 = and(_out_wifireMux_T_2, out_frontSel_41) node _out_wifireMux_T_168 = and(_out_wifireMux_T_167, UInt<1>(0h1)) connect out_wifireMux_out_41, UInt<1>(0h1) node _out_wifireMux_T_169 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_170 = or(out_wifireMux_out_41, _out_wifireMux_T_169) wire out_wifireMux_out_42 : UInt<1> node _out_wifireMux_T_171 = and(_out_wifireMux_T_2, out_frontSel_42) node _out_wifireMux_T_172 = and(_out_wifireMux_T_171, UInt<1>(0h1)) connect out_wifireMux_out_42, UInt<1>(0h1) node _out_wifireMux_T_173 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_174 = or(out_wifireMux_out_42, _out_wifireMux_T_173) wire out_wifireMux_out_43 : UInt<1> node _out_wifireMux_T_175 = and(_out_wifireMux_T_2, out_frontSel_43) node _out_wifireMux_T_176 = and(_out_wifireMux_T_175, UInt<1>(0h1)) connect out_wifireMux_out_43, UInt<1>(0h1) node _out_wifireMux_T_177 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_178 = or(out_wifireMux_out_43, _out_wifireMux_T_177) wire out_wifireMux_out_44 : UInt<1> node _out_wifireMux_T_179 = and(_out_wifireMux_T_2, out_frontSel_44) node _out_wifireMux_T_180 = and(_out_wifireMux_T_179, UInt<1>(0h1)) connect out_wifireMux_out_44, UInt<1>(0h1) node _out_wifireMux_T_181 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_182 = or(out_wifireMux_out_44, _out_wifireMux_T_181) wire out_wifireMux_out_45 : UInt<1> node _out_wifireMux_T_183 = and(_out_wifireMux_T_2, out_frontSel_45) node _out_wifireMux_T_184 = and(_out_wifireMux_T_183, UInt<1>(0h1)) connect out_wifireMux_out_45, UInt<1>(0h1) node _out_wifireMux_T_185 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_186 = or(out_wifireMux_out_45, _out_wifireMux_T_185) wire out_wifireMux_out_46 : UInt<1> node _out_wifireMux_T_187 = and(_out_wifireMux_T_2, out_frontSel_46) node _out_wifireMux_T_188 = and(_out_wifireMux_T_187, UInt<1>(0h1)) connect out_wifireMux_out_46, UInt<1>(0h1) node _out_wifireMux_T_189 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_190 = or(out_wifireMux_out_46, _out_wifireMux_T_189) wire out_wifireMux_out_47 : UInt<1> node _out_wifireMux_T_191 = and(_out_wifireMux_T_2, out_frontSel_47) node _out_wifireMux_T_192 = and(_out_wifireMux_T_191, UInt<1>(0h1)) connect out_wifireMux_out_47, UInt<1>(0h1) node _out_wifireMux_T_193 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_194 = or(out_wifireMux_out_47, _out_wifireMux_T_193) wire out_wifireMux_out_48 : UInt<1> node _out_wifireMux_T_195 = and(_out_wifireMux_T_2, out_frontSel_48) node _out_wifireMux_T_196 = and(_out_wifireMux_T_195, UInt<1>(0h1)) connect out_wifireMux_out_48, UInt<1>(0h1) node _out_wifireMux_T_197 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_198 = or(out_wifireMux_out_48, _out_wifireMux_T_197) wire out_wifireMux_out_49 : UInt<1> node _out_wifireMux_T_199 = and(_out_wifireMux_T_2, out_frontSel_49) node _out_wifireMux_T_200 = and(_out_wifireMux_T_199, UInt<1>(0h1)) connect out_wifireMux_out_49, UInt<1>(0h1) node _out_wifireMux_T_201 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_202 = or(out_wifireMux_out_49, _out_wifireMux_T_201) wire out_wifireMux_out_50 : UInt<1> node _out_wifireMux_T_203 = and(_out_wifireMux_T_2, out_frontSel_50) node _out_wifireMux_T_204 = and(_out_wifireMux_T_203, UInt<1>(0h1)) connect out_wifireMux_out_50, UInt<1>(0h1) node _out_wifireMux_T_205 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_206 = or(out_wifireMux_out_50, _out_wifireMux_T_205) wire out_wifireMux_out_51 : UInt<1> node _out_wifireMux_T_207 = and(_out_wifireMux_T_2, out_frontSel_51) node _out_wifireMux_T_208 = and(_out_wifireMux_T_207, UInt<1>(0h1)) connect out_wifireMux_out_51, UInt<1>(0h1) node _out_wifireMux_T_209 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_210 = or(out_wifireMux_out_51, _out_wifireMux_T_209) wire out_wifireMux_out_52 : UInt<1> node _out_wifireMux_T_211 = and(_out_wifireMux_T_2, out_frontSel_52) node _out_wifireMux_T_212 = and(_out_wifireMux_T_211, UInt<1>(0h1)) connect out_wifireMux_out_52, UInt<1>(0h1) node _out_wifireMux_T_213 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_214 = or(out_wifireMux_out_52, _out_wifireMux_T_213) wire out_wifireMux_out_53 : UInt<1> node _out_wifireMux_T_215 = and(_out_wifireMux_T_2, out_frontSel_53) node _out_wifireMux_T_216 = and(_out_wifireMux_T_215, UInt<1>(0h1)) connect out_wifireMux_out_53, UInt<1>(0h1) node _out_wifireMux_T_217 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_218 = or(out_wifireMux_out_53, _out_wifireMux_T_217) wire out_wifireMux_out_54 : UInt<1> node _out_wifireMux_T_219 = and(_out_wifireMux_T_2, out_frontSel_54) node _out_wifireMux_T_220 = and(_out_wifireMux_T_219, UInt<1>(0h1)) connect out_wifireMux_out_54, UInt<1>(0h1) node _out_wifireMux_T_221 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_222 = or(out_wifireMux_out_54, _out_wifireMux_T_221) wire out_wifireMux_out_55 : UInt<1> node _out_wifireMux_T_223 = and(_out_wifireMux_T_2, out_frontSel_55) node _out_wifireMux_T_224 = and(_out_wifireMux_T_223, UInt<1>(0h1)) connect out_wifireMux_out_55, UInt<1>(0h1) node _out_wifireMux_T_225 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_226 = or(out_wifireMux_out_55, _out_wifireMux_T_225) wire out_wifireMux_out_56 : UInt<1> node _out_wifireMux_T_227 = and(_out_wifireMux_T_2, out_frontSel_56) node _out_wifireMux_T_228 = and(_out_wifireMux_T_227, UInt<1>(0h1)) connect out_wifireMux_out_56, UInt<1>(0h1) node _out_wifireMux_T_229 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_230 = or(out_wifireMux_out_56, _out_wifireMux_T_229) wire out_wifireMux_out_57 : UInt<1> node _out_wifireMux_T_231 = and(_out_wifireMux_T_2, out_frontSel_57) node _out_wifireMux_T_232 = and(_out_wifireMux_T_231, UInt<1>(0h1)) connect out_wifireMux_out_57, UInt<1>(0h1) node _out_wifireMux_T_233 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_234 = or(out_wifireMux_out_57, _out_wifireMux_T_233) wire out_wifireMux_out_58 : UInt<1> node _out_wifireMux_T_235 = and(_out_wifireMux_T_2, out_frontSel_58) node _out_wifireMux_T_236 = and(_out_wifireMux_T_235, UInt<1>(0h1)) connect out_wifireMux_out_58, UInt<1>(0h1) node _out_wifireMux_T_237 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_238 = or(out_wifireMux_out_58, _out_wifireMux_T_237) wire out_wifireMux_out_59 : UInt<1> node _out_wifireMux_T_239 = and(_out_wifireMux_T_2, out_frontSel_59) node _out_wifireMux_T_240 = and(_out_wifireMux_T_239, UInt<1>(0h1)) connect out_wifireMux_out_59, UInt<1>(0h1) node _out_wifireMux_T_241 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_242 = or(out_wifireMux_out_59, _out_wifireMux_T_241) wire out_wifireMux_out_60 : UInt<1> node _out_wifireMux_T_243 = and(_out_wifireMux_T_2, out_frontSel_60) node _out_wifireMux_T_244 = and(_out_wifireMux_T_243, UInt<1>(0h1)) connect out_wifireMux_out_60, UInt<1>(0h1) node _out_wifireMux_T_245 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_246 = or(out_wifireMux_out_60, _out_wifireMux_T_245) wire out_wifireMux_out_61 : UInt<1> node _out_wifireMux_T_247 = and(_out_wifireMux_T_2, out_frontSel_61) node _out_wifireMux_T_248 = and(_out_wifireMux_T_247, UInt<1>(0h1)) connect out_wifireMux_out_61, UInt<1>(0h1) node _out_wifireMux_T_249 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_250 = or(out_wifireMux_out_61, _out_wifireMux_T_249) wire out_wifireMux_out_62 : UInt<1> node _out_wifireMux_T_251 = and(_out_wifireMux_T_2, out_frontSel_62) node _out_wifireMux_T_252 = and(_out_wifireMux_T_251, UInt<1>(0h1)) connect out_wifireMux_out_62, UInt<1>(0h1) node _out_wifireMux_T_253 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_254 = or(out_wifireMux_out_62, _out_wifireMux_T_253) wire out_wifireMux_out_63 : UInt<1> node _out_wifireMux_T_255 = and(_out_wifireMux_T_2, out_frontSel_63) node _out_wifireMux_T_256 = and(_out_wifireMux_T_255, UInt<1>(0h1)) connect out_wifireMux_out_63, UInt<1>(0h1) node _out_wifireMux_T_257 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_258 = or(out_wifireMux_out_63, _out_wifireMux_T_257) wire out_wifireMux_out_64 : UInt<1> node _out_wifireMux_T_259 = and(_out_wifireMux_T_2, out_frontSel_64) node _out_wifireMux_T_260 = and(_out_wifireMux_T_259, _out_T_12) connect out_wifireMux_out_64, UInt<1>(0h1) connect out_wivalid[19], _out_wifireMux_T_260 connect out_wivalid[18], _out_wifireMux_T_260 connect out_wivalid[17], _out_wifireMux_T_260 node _out_wifireMux_T_261 = eq(_out_T_12, UInt<1>(0h0)) node _out_wifireMux_T_262 = or(out_wifireMux_out_64, _out_wifireMux_T_261) wire out_wifireMux_out_65 : UInt<1> node _out_wifireMux_T_263 = and(_out_wifireMux_T_2, out_frontSel_65) node _out_wifireMux_T_264 = and(_out_wifireMux_T_263, UInt<1>(0h1)) connect out_wifireMux_out_65, UInt<1>(0h1) node _out_wifireMux_T_265 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_266 = or(out_wifireMux_out_65, _out_wifireMux_T_265) wire out_wifireMux_out_66 : UInt<1> node _out_wifireMux_T_267 = and(_out_wifireMux_T_2, out_frontSel_66) node _out_wifireMux_T_268 = and(_out_wifireMux_T_267, UInt<1>(0h1)) connect out_wifireMux_out_66, UInt<1>(0h1) node _out_wifireMux_T_269 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_270 = or(out_wifireMux_out_66, _out_wifireMux_T_269) wire out_wifireMux_out_67 : UInt<1> node _out_wifireMux_T_271 = and(_out_wifireMux_T_2, out_frontSel_67) node _out_wifireMux_T_272 = and(_out_wifireMux_T_271, UInt<1>(0h1)) connect out_wifireMux_out_67, UInt<1>(0h1) node _out_wifireMux_T_273 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_274 = or(out_wifireMux_out_67, _out_wifireMux_T_273) wire out_wifireMux_out_68 : UInt<1> node _out_wifireMux_T_275 = and(_out_wifireMux_T_2, out_frontSel_68) node _out_wifireMux_T_276 = and(_out_wifireMux_T_275, UInt<1>(0h1)) connect out_wifireMux_out_68, UInt<1>(0h1) node _out_wifireMux_T_277 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_278 = or(out_wifireMux_out_68, _out_wifireMux_T_277) wire out_wifireMux_out_69 : UInt<1> node _out_wifireMux_T_279 = and(_out_wifireMux_T_2, out_frontSel_69) node _out_wifireMux_T_280 = and(_out_wifireMux_T_279, UInt<1>(0h1)) connect out_wifireMux_out_69, UInt<1>(0h1) node _out_wifireMux_T_281 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_282 = or(out_wifireMux_out_69, _out_wifireMux_T_281) wire out_wifireMux_out_70 : UInt<1> node _out_wifireMux_T_283 = and(_out_wifireMux_T_2, out_frontSel_70) node _out_wifireMux_T_284 = and(_out_wifireMux_T_283, UInt<1>(0h1)) connect out_wifireMux_out_70, UInt<1>(0h1) node _out_wifireMux_T_285 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_286 = or(out_wifireMux_out_70, _out_wifireMux_T_285) wire out_wifireMux_out_71 : UInt<1> node _out_wifireMux_T_287 = and(_out_wifireMux_T_2, out_frontSel_71) node _out_wifireMux_T_288 = and(_out_wifireMux_T_287, UInt<1>(0h1)) connect out_wifireMux_out_71, UInt<1>(0h1) node _out_wifireMux_T_289 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_290 = or(out_wifireMux_out_71, _out_wifireMux_T_289) wire out_wifireMux_out_72 : UInt<1> node _out_wifireMux_T_291 = and(_out_wifireMux_T_2, out_frontSel_72) node _out_wifireMux_T_292 = and(_out_wifireMux_T_291, _out_T_6) connect out_wifireMux_out_72, UInt<1>(0h1) connect out_wivalid[10], _out_wifireMux_T_292 connect out_wivalid[9], _out_wifireMux_T_292 connect out_wivalid[8], _out_wifireMux_T_292 node _out_wifireMux_T_293 = eq(_out_T_6, UInt<1>(0h0)) node _out_wifireMux_T_294 = or(out_wifireMux_out_72, _out_wifireMux_T_293) wire out_wifireMux_out_73 : UInt<1> node _out_wifireMux_T_295 = and(_out_wifireMux_T_2, out_frontSel_73) node _out_wifireMux_T_296 = and(_out_wifireMux_T_295, UInt<1>(0h1)) connect out_wifireMux_out_73, UInt<1>(0h1) node _out_wifireMux_T_297 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_298 = or(out_wifireMux_out_73, _out_wifireMux_T_297) wire out_wifireMux_out_74 : UInt<1> node _out_wifireMux_T_299 = and(_out_wifireMux_T_2, out_frontSel_74) node _out_wifireMux_T_300 = and(_out_wifireMux_T_299, UInt<1>(0h1)) connect out_wifireMux_out_74, UInt<1>(0h1) node _out_wifireMux_T_301 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_302 = or(out_wifireMux_out_74, _out_wifireMux_T_301) wire out_wifireMux_out_75 : UInt<1> node _out_wifireMux_T_303 = and(_out_wifireMux_T_2, out_frontSel_75) node _out_wifireMux_T_304 = and(_out_wifireMux_T_303, UInt<1>(0h1)) connect out_wifireMux_out_75, UInt<1>(0h1) node _out_wifireMux_T_305 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_306 = or(out_wifireMux_out_75, _out_wifireMux_T_305) wire out_wifireMux_out_76 : UInt<1> node _out_wifireMux_T_307 = and(_out_wifireMux_T_2, out_frontSel_76) node _out_wifireMux_T_308 = and(_out_wifireMux_T_307, UInt<1>(0h1)) connect out_wifireMux_out_76, UInt<1>(0h1) node _out_wifireMux_T_309 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_310 = or(out_wifireMux_out_76, _out_wifireMux_T_309) wire out_wifireMux_out_77 : UInt<1> node _out_wifireMux_T_311 = and(_out_wifireMux_T_2, out_frontSel_77) node _out_wifireMux_T_312 = and(_out_wifireMux_T_311, UInt<1>(0h1)) connect out_wifireMux_out_77, UInt<1>(0h1) node _out_wifireMux_T_313 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_314 = or(out_wifireMux_out_77, _out_wifireMux_T_313) wire out_wifireMux_out_78 : UInt<1> node _out_wifireMux_T_315 = and(_out_wifireMux_T_2, out_frontSel_78) node _out_wifireMux_T_316 = and(_out_wifireMux_T_315, UInt<1>(0h1)) connect out_wifireMux_out_78, UInt<1>(0h1) node _out_wifireMux_T_317 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_318 = or(out_wifireMux_out_78, _out_wifireMux_T_317) wire out_wifireMux_out_79 : UInt<1> node _out_wifireMux_T_319 = and(_out_wifireMux_T_2, out_frontSel_79) node _out_wifireMux_T_320 = and(_out_wifireMux_T_319, UInt<1>(0h1)) connect out_wifireMux_out_79, UInt<1>(0h1) node _out_wifireMux_T_321 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_322 = or(out_wifireMux_out_79, _out_wifireMux_T_321) wire out_wifireMux_out_80 : UInt<1> node _out_wifireMux_T_323 = and(_out_wifireMux_T_2, out_frontSel_80) node _out_wifireMux_T_324 = and(_out_wifireMux_T_323, _out_T_14) connect out_wifireMux_out_80, UInt<1>(0h1) connect out_wivalid[22], _out_wifireMux_T_324 connect out_wivalid[21], _out_wifireMux_T_324 connect out_wivalid[20], _out_wifireMux_T_324 node _out_wifireMux_T_325 = eq(_out_T_14, UInt<1>(0h0)) node _out_wifireMux_T_326 = or(out_wifireMux_out_80, _out_wifireMux_T_325) wire out_wifireMux_out_81 : UInt<1> node _out_wifireMux_T_327 = and(_out_wifireMux_T_2, out_frontSel_81) node _out_wifireMux_T_328 = and(_out_wifireMux_T_327, UInt<1>(0h1)) connect out_wifireMux_out_81, UInt<1>(0h1) node _out_wifireMux_T_329 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_330 = or(out_wifireMux_out_81, _out_wifireMux_T_329) wire out_wifireMux_out_82 : UInt<1> node _out_wifireMux_T_331 = and(_out_wifireMux_T_2, out_frontSel_82) node _out_wifireMux_T_332 = and(_out_wifireMux_T_331, UInt<1>(0h1)) connect out_wifireMux_out_82, UInt<1>(0h1) node _out_wifireMux_T_333 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_334 = or(out_wifireMux_out_82, _out_wifireMux_T_333) wire out_wifireMux_out_83 : UInt<1> node _out_wifireMux_T_335 = and(_out_wifireMux_T_2, out_frontSel_83) node _out_wifireMux_T_336 = and(_out_wifireMux_T_335, UInt<1>(0h1)) connect out_wifireMux_out_83, UInt<1>(0h1) node _out_wifireMux_T_337 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_338 = or(out_wifireMux_out_83, _out_wifireMux_T_337) wire out_wifireMux_out_84 : UInt<1> node _out_wifireMux_T_339 = and(_out_wifireMux_T_2, out_frontSel_84) node _out_wifireMux_T_340 = and(_out_wifireMux_T_339, UInt<1>(0h1)) connect out_wifireMux_out_84, UInt<1>(0h1) node _out_wifireMux_T_341 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_342 = or(out_wifireMux_out_84, _out_wifireMux_T_341) wire out_wifireMux_out_85 : UInt<1> node _out_wifireMux_T_343 = and(_out_wifireMux_T_2, out_frontSel_85) node _out_wifireMux_T_344 = and(_out_wifireMux_T_343, UInt<1>(0h1)) connect out_wifireMux_out_85, UInt<1>(0h1) node _out_wifireMux_T_345 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_346 = or(out_wifireMux_out_85, _out_wifireMux_T_345) wire out_wifireMux_out_86 : UInt<1> node _out_wifireMux_T_347 = and(_out_wifireMux_T_2, out_frontSel_86) node _out_wifireMux_T_348 = and(_out_wifireMux_T_347, UInt<1>(0h1)) connect out_wifireMux_out_86, UInt<1>(0h1) node _out_wifireMux_T_349 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_350 = or(out_wifireMux_out_86, _out_wifireMux_T_349) wire out_wifireMux_out_87 : UInt<1> node _out_wifireMux_T_351 = and(_out_wifireMux_T_2, out_frontSel_87) node _out_wifireMux_T_352 = and(_out_wifireMux_T_351, UInt<1>(0h1)) connect out_wifireMux_out_87, UInt<1>(0h1) node _out_wifireMux_T_353 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_354 = or(out_wifireMux_out_87, _out_wifireMux_T_353) wire out_wifireMux_out_88 : UInt<1> node _out_wifireMux_T_355 = and(_out_wifireMux_T_2, out_frontSel_88) node _out_wifireMux_T_356 = and(_out_wifireMux_T_355, _out_T_8) connect out_wifireMux_out_88, UInt<1>(0h1) connect out_wivalid[13], _out_wifireMux_T_356 connect out_wivalid[12], _out_wifireMux_T_356 connect out_wivalid[11], _out_wifireMux_T_356 node _out_wifireMux_T_357 = eq(_out_T_8, UInt<1>(0h0)) node _out_wifireMux_T_358 = or(out_wifireMux_out_88, _out_wifireMux_T_357) wire out_wifireMux_out_89 : UInt<1> node _out_wifireMux_T_359 = and(_out_wifireMux_T_2, out_frontSel_89) node _out_wifireMux_T_360 = and(_out_wifireMux_T_359, UInt<1>(0h1)) connect out_wifireMux_out_89, UInt<1>(0h1) node _out_wifireMux_T_361 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_362 = or(out_wifireMux_out_89, _out_wifireMux_T_361) wire out_wifireMux_out_90 : UInt<1> node _out_wifireMux_T_363 = and(_out_wifireMux_T_2, out_frontSel_90) node _out_wifireMux_T_364 = and(_out_wifireMux_T_363, UInt<1>(0h1)) connect out_wifireMux_out_90, UInt<1>(0h1) node _out_wifireMux_T_365 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_366 = or(out_wifireMux_out_90, _out_wifireMux_T_365) wire out_wifireMux_out_91 : UInt<1> node _out_wifireMux_T_367 = and(_out_wifireMux_T_2, out_frontSel_91) node _out_wifireMux_T_368 = and(_out_wifireMux_T_367, UInt<1>(0h1)) connect out_wifireMux_out_91, UInt<1>(0h1) node _out_wifireMux_T_369 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_370 = or(out_wifireMux_out_91, _out_wifireMux_T_369) wire out_wifireMux_out_92 : UInt<1> node _out_wifireMux_T_371 = and(_out_wifireMux_T_2, out_frontSel_92) node _out_wifireMux_T_372 = and(_out_wifireMux_T_371, UInt<1>(0h1)) connect out_wifireMux_out_92, UInt<1>(0h1) node _out_wifireMux_T_373 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_374 = or(out_wifireMux_out_92, _out_wifireMux_T_373) wire out_wifireMux_out_93 : UInt<1> node _out_wifireMux_T_375 = and(_out_wifireMux_T_2, out_frontSel_93) node _out_wifireMux_T_376 = and(_out_wifireMux_T_375, UInt<1>(0h1)) connect out_wifireMux_out_93, UInt<1>(0h1) node _out_wifireMux_T_377 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_378 = or(out_wifireMux_out_93, _out_wifireMux_T_377) wire out_wifireMux_out_94 : UInt<1> node _out_wifireMux_T_379 = and(_out_wifireMux_T_2, out_frontSel_94) node _out_wifireMux_T_380 = and(_out_wifireMux_T_379, UInt<1>(0h1)) connect out_wifireMux_out_94, UInt<1>(0h1) node _out_wifireMux_T_381 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_382 = or(out_wifireMux_out_94, _out_wifireMux_T_381) wire out_wifireMux_out_95 : UInt<1> node _out_wifireMux_T_383 = and(_out_wifireMux_T_2, out_frontSel_95) node _out_wifireMux_T_384 = and(_out_wifireMux_T_383, UInt<1>(0h1)) connect out_wifireMux_out_95, UInt<1>(0h1) node _out_wifireMux_T_385 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_386 = or(out_wifireMux_out_95, _out_wifireMux_T_385) wire out_wifireMux_out_96 : UInt<1> node _out_wifireMux_T_387 = and(_out_wifireMux_T_2, out_frontSel_96) node _out_wifireMux_T_388 = and(_out_wifireMux_T_387, _out_T_4) connect out_wifireMux_out_96, UInt<1>(0h1) connect out_wivalid[7], _out_wifireMux_T_388 connect out_wivalid[6], _out_wifireMux_T_388 connect out_wivalid[5], _out_wifireMux_T_388 node _out_wifireMux_T_389 = eq(_out_T_4, UInt<1>(0h0)) node _out_wifireMux_T_390 = or(out_wifireMux_out_96, _out_wifireMux_T_389) wire out_wifireMux_out_97 : UInt<1> node _out_wifireMux_T_391 = and(_out_wifireMux_T_2, out_frontSel_97) node _out_wifireMux_T_392 = and(_out_wifireMux_T_391, UInt<1>(0h1)) connect out_wifireMux_out_97, UInt<1>(0h1) node _out_wifireMux_T_393 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_394 = or(out_wifireMux_out_97, _out_wifireMux_T_393) wire out_wifireMux_out_98 : UInt<1> node _out_wifireMux_T_395 = and(_out_wifireMux_T_2, out_frontSel_98) node _out_wifireMux_T_396 = and(_out_wifireMux_T_395, UInt<1>(0h1)) connect out_wifireMux_out_98, UInt<1>(0h1) node _out_wifireMux_T_397 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_398 = or(out_wifireMux_out_98, _out_wifireMux_T_397) wire out_wifireMux_out_99 : UInt<1> node _out_wifireMux_T_399 = and(_out_wifireMux_T_2, out_frontSel_99) node _out_wifireMux_T_400 = and(_out_wifireMux_T_399, UInt<1>(0h1)) connect out_wifireMux_out_99, UInt<1>(0h1) node _out_wifireMux_T_401 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_402 = or(out_wifireMux_out_99, _out_wifireMux_T_401) wire out_wifireMux_out_100 : UInt<1> node _out_wifireMux_T_403 = and(_out_wifireMux_T_2, out_frontSel_100) node _out_wifireMux_T_404 = and(_out_wifireMux_T_403, UInt<1>(0h1)) connect out_wifireMux_out_100, UInt<1>(0h1) node _out_wifireMux_T_405 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_406 = or(out_wifireMux_out_100, _out_wifireMux_T_405) wire out_wifireMux_out_101 : UInt<1> node _out_wifireMux_T_407 = and(_out_wifireMux_T_2, out_frontSel_101) node _out_wifireMux_T_408 = and(_out_wifireMux_T_407, UInt<1>(0h1)) connect out_wifireMux_out_101, UInt<1>(0h1) node _out_wifireMux_T_409 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_410 = or(out_wifireMux_out_101, _out_wifireMux_T_409) wire out_wifireMux_out_102 : UInt<1> node _out_wifireMux_T_411 = and(_out_wifireMux_T_2, out_frontSel_102) node _out_wifireMux_T_412 = and(_out_wifireMux_T_411, UInt<1>(0h1)) connect out_wifireMux_out_102, UInt<1>(0h1) node _out_wifireMux_T_413 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_414 = or(out_wifireMux_out_102, _out_wifireMux_T_413) wire out_wifireMux_out_103 : UInt<1> node _out_wifireMux_T_415 = and(_out_wifireMux_T_2, out_frontSel_103) node _out_wifireMux_T_416 = and(_out_wifireMux_T_415, UInt<1>(0h1)) connect out_wifireMux_out_103, UInt<1>(0h1) node _out_wifireMux_T_417 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_418 = or(out_wifireMux_out_103, _out_wifireMux_T_417) wire out_wifireMux_out_104 : UInt<1> node _out_wifireMux_T_419 = and(_out_wifireMux_T_2, out_frontSel_104) node _out_wifireMux_T_420 = and(_out_wifireMux_T_419, _out_T) connect out_wifireMux_out_104, UInt<1>(0h1) connect out_wivalid[2], _out_wifireMux_T_420 connect out_wivalid[1], _out_wifireMux_T_420 connect out_wivalid[0], _out_wifireMux_T_420 node _out_wifireMux_T_421 = eq(_out_T, UInt<1>(0h0)) node _out_wifireMux_T_422 = or(out_wifireMux_out_104, _out_wifireMux_T_421) wire out_wifireMux_out_105 : UInt<1> node _out_wifireMux_T_423 = and(_out_wifireMux_T_2, out_frontSel_105) node _out_wifireMux_T_424 = and(_out_wifireMux_T_423, UInt<1>(0h1)) connect out_wifireMux_out_105, UInt<1>(0h1) node _out_wifireMux_T_425 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_426 = or(out_wifireMux_out_105, _out_wifireMux_T_425) wire out_wifireMux_out_106 : UInt<1> node _out_wifireMux_T_427 = and(_out_wifireMux_T_2, out_frontSel_106) node _out_wifireMux_T_428 = and(_out_wifireMux_T_427, UInt<1>(0h1)) connect out_wifireMux_out_106, UInt<1>(0h1) node _out_wifireMux_T_429 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_430 = or(out_wifireMux_out_106, _out_wifireMux_T_429) wire out_wifireMux_out_107 : UInt<1> node _out_wifireMux_T_431 = and(_out_wifireMux_T_2, out_frontSel_107) node _out_wifireMux_T_432 = and(_out_wifireMux_T_431, UInt<1>(0h1)) connect out_wifireMux_out_107, UInt<1>(0h1) node _out_wifireMux_T_433 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_434 = or(out_wifireMux_out_107, _out_wifireMux_T_433) wire out_wifireMux_out_108 : UInt<1> node _out_wifireMux_T_435 = and(_out_wifireMux_T_2, out_frontSel_108) node _out_wifireMux_T_436 = and(_out_wifireMux_T_435, UInt<1>(0h1)) connect out_wifireMux_out_108, UInt<1>(0h1) node _out_wifireMux_T_437 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_438 = or(out_wifireMux_out_108, _out_wifireMux_T_437) wire out_wifireMux_out_109 : UInt<1> node _out_wifireMux_T_439 = and(_out_wifireMux_T_2, out_frontSel_109) node _out_wifireMux_T_440 = and(_out_wifireMux_T_439, UInt<1>(0h1)) connect out_wifireMux_out_109, UInt<1>(0h1) node _out_wifireMux_T_441 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_442 = or(out_wifireMux_out_109, _out_wifireMux_T_441) wire out_wifireMux_out_110 : UInt<1> node _out_wifireMux_T_443 = and(_out_wifireMux_T_2, out_frontSel_110) node _out_wifireMux_T_444 = and(_out_wifireMux_T_443, UInt<1>(0h1)) connect out_wifireMux_out_110, UInt<1>(0h1) node _out_wifireMux_T_445 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_446 = or(out_wifireMux_out_110, _out_wifireMux_T_445) wire out_wifireMux_out_111 : UInt<1> node _out_wifireMux_T_447 = and(_out_wifireMux_T_2, out_frontSel_111) node _out_wifireMux_T_448 = and(_out_wifireMux_T_447, UInt<1>(0h1)) connect out_wifireMux_out_111, UInt<1>(0h1) node _out_wifireMux_T_449 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_450 = or(out_wifireMux_out_111, _out_wifireMux_T_449) wire out_wifireMux_out_112 : UInt<1> node _out_wifireMux_T_451 = and(_out_wifireMux_T_2, out_frontSel_112) node _out_wifireMux_T_452 = and(_out_wifireMux_T_451, _out_T_16) connect out_wifireMux_out_112, UInt<1>(0h1) connect out_wivalid[25], _out_wifireMux_T_452 connect out_wivalid[24], _out_wifireMux_T_452 connect out_wivalid[23], _out_wifireMux_T_452 node _out_wifireMux_T_453 = eq(_out_T_16, UInt<1>(0h0)) node _out_wifireMux_T_454 = or(out_wifireMux_out_112, _out_wifireMux_T_453) wire out_wifireMux_out_113 : UInt<1> node _out_wifireMux_T_455 = and(_out_wifireMux_T_2, out_frontSel_113) node _out_wifireMux_T_456 = and(_out_wifireMux_T_455, UInt<1>(0h1)) connect out_wifireMux_out_113, UInt<1>(0h1) node _out_wifireMux_T_457 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_458 = or(out_wifireMux_out_113, _out_wifireMux_T_457) wire out_wifireMux_out_114 : UInt<1> node _out_wifireMux_T_459 = and(_out_wifireMux_T_2, out_frontSel_114) node _out_wifireMux_T_460 = and(_out_wifireMux_T_459, UInt<1>(0h1)) connect out_wifireMux_out_114, UInt<1>(0h1) node _out_wifireMux_T_461 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_462 = or(out_wifireMux_out_114, _out_wifireMux_T_461) wire out_wifireMux_out_115 : UInt<1> node _out_wifireMux_T_463 = and(_out_wifireMux_T_2, out_frontSel_115) node _out_wifireMux_T_464 = and(_out_wifireMux_T_463, UInt<1>(0h1)) connect out_wifireMux_out_115, UInt<1>(0h1) node _out_wifireMux_T_465 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_466 = or(out_wifireMux_out_115, _out_wifireMux_T_465) wire out_wifireMux_out_116 : UInt<1> node _out_wifireMux_T_467 = and(_out_wifireMux_T_2, out_frontSel_116) node _out_wifireMux_T_468 = and(_out_wifireMux_T_467, UInt<1>(0h1)) connect out_wifireMux_out_116, UInt<1>(0h1) node _out_wifireMux_T_469 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_470 = or(out_wifireMux_out_116, _out_wifireMux_T_469) wire out_wifireMux_out_117 : UInt<1> node _out_wifireMux_T_471 = and(_out_wifireMux_T_2, out_frontSel_117) node _out_wifireMux_T_472 = and(_out_wifireMux_T_471, UInt<1>(0h1)) connect out_wifireMux_out_117, UInt<1>(0h1) node _out_wifireMux_T_473 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_474 = or(out_wifireMux_out_117, _out_wifireMux_T_473) wire out_wifireMux_out_118 : UInt<1> node _out_wifireMux_T_475 = and(_out_wifireMux_T_2, out_frontSel_118) node _out_wifireMux_T_476 = and(_out_wifireMux_T_475, UInt<1>(0h1)) connect out_wifireMux_out_118, UInt<1>(0h1) node _out_wifireMux_T_477 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_478 = or(out_wifireMux_out_118, _out_wifireMux_T_477) wire out_wifireMux_out_119 : UInt<1> node _out_wifireMux_T_479 = and(_out_wifireMux_T_2, out_frontSel_119) node _out_wifireMux_T_480 = and(_out_wifireMux_T_479, UInt<1>(0h1)) connect out_wifireMux_out_119, UInt<1>(0h1) node _out_wifireMux_T_481 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_482 = or(out_wifireMux_out_119, _out_wifireMux_T_481) wire out_wifireMux_out_120 : UInt<1> node _out_wifireMux_T_483 = and(_out_wifireMux_T_2, out_frontSel_120) node _out_wifireMux_T_484 = and(_out_wifireMux_T_483, _out_T_10) connect out_wifireMux_out_120, UInt<1>(0h1) connect out_wivalid[16], _out_wifireMux_T_484 connect out_wivalid[15], _out_wifireMux_T_484 connect out_wivalid[14], _out_wifireMux_T_484 node _out_wifireMux_T_485 = eq(_out_T_10, UInt<1>(0h0)) node _out_wifireMux_T_486 = or(out_wifireMux_out_120, _out_wifireMux_T_485) wire out_wifireMux_out_121 : UInt<1> node _out_wifireMux_T_487 = and(_out_wifireMux_T_2, out_frontSel_121) node _out_wifireMux_T_488 = and(_out_wifireMux_T_487, UInt<1>(0h1)) connect out_wifireMux_out_121, UInt<1>(0h1) node _out_wifireMux_T_489 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_490 = or(out_wifireMux_out_121, _out_wifireMux_T_489) wire out_wifireMux_out_122 : UInt<1> node _out_wifireMux_T_491 = and(_out_wifireMux_T_2, out_frontSel_122) node _out_wifireMux_T_492 = and(_out_wifireMux_T_491, UInt<1>(0h1)) connect out_wifireMux_out_122, UInt<1>(0h1) node _out_wifireMux_T_493 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_494 = or(out_wifireMux_out_122, _out_wifireMux_T_493) wire out_wifireMux_out_123 : UInt<1> node _out_wifireMux_T_495 = and(_out_wifireMux_T_2, out_frontSel_123) node _out_wifireMux_T_496 = and(_out_wifireMux_T_495, UInt<1>(0h1)) connect out_wifireMux_out_123, UInt<1>(0h1) node _out_wifireMux_T_497 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_498 = or(out_wifireMux_out_123, _out_wifireMux_T_497) wire out_wifireMux_out_124 : UInt<1> node _out_wifireMux_T_499 = and(_out_wifireMux_T_2, out_frontSel_124) node _out_wifireMux_T_500 = and(_out_wifireMux_T_499, UInt<1>(0h1)) connect out_wifireMux_out_124, UInt<1>(0h1) node _out_wifireMux_T_501 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_502 = or(out_wifireMux_out_124, _out_wifireMux_T_501) wire out_wifireMux_out_125 : UInt<1> node _out_wifireMux_T_503 = and(_out_wifireMux_T_2, out_frontSel_125) node _out_wifireMux_T_504 = and(_out_wifireMux_T_503, UInt<1>(0h1)) connect out_wifireMux_out_125, UInt<1>(0h1) node _out_wifireMux_T_505 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_506 = or(out_wifireMux_out_125, _out_wifireMux_T_505) wire out_wifireMux_out_126 : UInt<1> node _out_wifireMux_T_507 = and(_out_wifireMux_T_2, out_frontSel_126) node _out_wifireMux_T_508 = and(_out_wifireMux_T_507, UInt<1>(0h1)) connect out_wifireMux_out_126, UInt<1>(0h1) node _out_wifireMux_T_509 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_510 = or(out_wifireMux_out_126, _out_wifireMux_T_509) wire out_wifireMux_out_127 : UInt<1> node _out_wifireMux_T_511 = and(_out_wifireMux_T_2, out_frontSel_127) node _out_wifireMux_T_512 = and(_out_wifireMux_T_511, UInt<1>(0h1)) connect out_wifireMux_out_127, UInt<1>(0h1) node _out_wifireMux_T_513 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_514 = or(out_wifireMux_out_127, _out_wifireMux_T_513) node _out_wifireMux_T_515 = geq(out_iindex, UInt<8>(0h80)) wire _out_wifireMux_WIRE : UInt<1>[128] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 connect _out_wifireMux_WIRE[1], _out_wifireMux_T_10 connect _out_wifireMux_WIRE[2], _out_wifireMux_T_14 connect _out_wifireMux_WIRE[3], _out_wifireMux_T_18 connect _out_wifireMux_WIRE[4], _out_wifireMux_T_22 connect _out_wifireMux_WIRE[5], _out_wifireMux_T_26 connect _out_wifireMux_WIRE[6], _out_wifireMux_T_30 connect _out_wifireMux_WIRE[7], _out_wifireMux_T_34 connect _out_wifireMux_WIRE[8], _out_wifireMux_T_38 connect _out_wifireMux_WIRE[9], _out_wifireMux_T_42 connect _out_wifireMux_WIRE[10], _out_wifireMux_T_46 connect _out_wifireMux_WIRE[11], _out_wifireMux_T_50 connect _out_wifireMux_WIRE[12], _out_wifireMux_T_54 connect _out_wifireMux_WIRE[13], _out_wifireMux_T_58 connect _out_wifireMux_WIRE[14], _out_wifireMux_T_62 connect _out_wifireMux_WIRE[15], _out_wifireMux_T_66 connect _out_wifireMux_WIRE[16], _out_wifireMux_T_70 connect _out_wifireMux_WIRE[17], _out_wifireMux_T_74 connect _out_wifireMux_WIRE[18], _out_wifireMux_T_78 connect _out_wifireMux_WIRE[19], _out_wifireMux_T_82 connect _out_wifireMux_WIRE[20], _out_wifireMux_T_86 connect _out_wifireMux_WIRE[21], _out_wifireMux_T_90 connect _out_wifireMux_WIRE[22], _out_wifireMux_T_94 connect _out_wifireMux_WIRE[23], _out_wifireMux_T_98 connect _out_wifireMux_WIRE[24], _out_wifireMux_T_102 connect _out_wifireMux_WIRE[25], _out_wifireMux_T_106 connect _out_wifireMux_WIRE[26], _out_wifireMux_T_110 connect _out_wifireMux_WIRE[27], _out_wifireMux_T_114 connect _out_wifireMux_WIRE[28], _out_wifireMux_T_118 connect _out_wifireMux_WIRE[29], _out_wifireMux_T_122 connect _out_wifireMux_WIRE[30], _out_wifireMux_T_126 connect _out_wifireMux_WIRE[31], _out_wifireMux_T_130 connect _out_wifireMux_WIRE[32], _out_wifireMux_T_134 connect _out_wifireMux_WIRE[33], _out_wifireMux_T_138 connect _out_wifireMux_WIRE[34], _out_wifireMux_T_142 connect _out_wifireMux_WIRE[35], _out_wifireMux_T_146 connect _out_wifireMux_WIRE[36], _out_wifireMux_T_150 connect _out_wifireMux_WIRE[37], _out_wifireMux_T_154 connect _out_wifireMux_WIRE[38], _out_wifireMux_T_158 connect _out_wifireMux_WIRE[39], _out_wifireMux_T_162 connect _out_wifireMux_WIRE[40], _out_wifireMux_T_166 connect _out_wifireMux_WIRE[41], _out_wifireMux_T_170 connect _out_wifireMux_WIRE[42], _out_wifireMux_T_174 connect _out_wifireMux_WIRE[43], _out_wifireMux_T_178 connect _out_wifireMux_WIRE[44], _out_wifireMux_T_182 connect _out_wifireMux_WIRE[45], _out_wifireMux_T_186 connect _out_wifireMux_WIRE[46], _out_wifireMux_T_190 connect _out_wifireMux_WIRE[47], _out_wifireMux_T_194 connect _out_wifireMux_WIRE[48], _out_wifireMux_T_198 connect _out_wifireMux_WIRE[49], _out_wifireMux_T_202 connect _out_wifireMux_WIRE[50], _out_wifireMux_T_206 connect _out_wifireMux_WIRE[51], _out_wifireMux_T_210 connect _out_wifireMux_WIRE[52], _out_wifireMux_T_214 connect _out_wifireMux_WIRE[53], _out_wifireMux_T_218 connect _out_wifireMux_WIRE[54], _out_wifireMux_T_222 connect _out_wifireMux_WIRE[55], _out_wifireMux_T_226 connect _out_wifireMux_WIRE[56], _out_wifireMux_T_230 connect _out_wifireMux_WIRE[57], _out_wifireMux_T_234 connect _out_wifireMux_WIRE[58], _out_wifireMux_T_238 connect _out_wifireMux_WIRE[59], _out_wifireMux_T_242 connect _out_wifireMux_WIRE[60], _out_wifireMux_T_246 connect _out_wifireMux_WIRE[61], _out_wifireMux_T_250 connect _out_wifireMux_WIRE[62], _out_wifireMux_T_254 connect _out_wifireMux_WIRE[63], _out_wifireMux_T_258 connect _out_wifireMux_WIRE[64], _out_wifireMux_T_262 connect _out_wifireMux_WIRE[65], _out_wifireMux_T_266 connect _out_wifireMux_WIRE[66], _out_wifireMux_T_270 connect _out_wifireMux_WIRE[67], _out_wifireMux_T_274 connect _out_wifireMux_WIRE[68], _out_wifireMux_T_278 connect _out_wifireMux_WIRE[69], _out_wifireMux_T_282 connect _out_wifireMux_WIRE[70], _out_wifireMux_T_286 connect _out_wifireMux_WIRE[71], _out_wifireMux_T_290 connect _out_wifireMux_WIRE[72], _out_wifireMux_T_294 connect _out_wifireMux_WIRE[73], _out_wifireMux_T_298 connect _out_wifireMux_WIRE[74], _out_wifireMux_T_302 connect _out_wifireMux_WIRE[75], _out_wifireMux_T_306 connect _out_wifireMux_WIRE[76], _out_wifireMux_T_310 connect _out_wifireMux_WIRE[77], _out_wifireMux_T_314 connect _out_wifireMux_WIRE[78], _out_wifireMux_T_318 connect _out_wifireMux_WIRE[79], _out_wifireMux_T_322 connect _out_wifireMux_WIRE[80], _out_wifireMux_T_326 connect _out_wifireMux_WIRE[81], _out_wifireMux_T_330 connect _out_wifireMux_WIRE[82], _out_wifireMux_T_334 connect _out_wifireMux_WIRE[83], _out_wifireMux_T_338 connect _out_wifireMux_WIRE[84], _out_wifireMux_T_342 connect _out_wifireMux_WIRE[85], _out_wifireMux_T_346 connect _out_wifireMux_WIRE[86], _out_wifireMux_T_350 connect _out_wifireMux_WIRE[87], _out_wifireMux_T_354 connect _out_wifireMux_WIRE[88], _out_wifireMux_T_358 connect _out_wifireMux_WIRE[89], _out_wifireMux_T_362 connect _out_wifireMux_WIRE[90], _out_wifireMux_T_366 connect _out_wifireMux_WIRE[91], _out_wifireMux_T_370 connect _out_wifireMux_WIRE[92], _out_wifireMux_T_374 connect _out_wifireMux_WIRE[93], _out_wifireMux_T_378 connect _out_wifireMux_WIRE[94], _out_wifireMux_T_382 connect _out_wifireMux_WIRE[95], _out_wifireMux_T_386 connect _out_wifireMux_WIRE[96], _out_wifireMux_T_390 connect _out_wifireMux_WIRE[97], _out_wifireMux_T_394 connect _out_wifireMux_WIRE[98], _out_wifireMux_T_398 connect _out_wifireMux_WIRE[99], _out_wifireMux_T_402 connect _out_wifireMux_WIRE[100], _out_wifireMux_T_406 connect _out_wifireMux_WIRE[101], _out_wifireMux_T_410 connect _out_wifireMux_WIRE[102], _out_wifireMux_T_414 connect _out_wifireMux_WIRE[103], _out_wifireMux_T_418 connect _out_wifireMux_WIRE[104], _out_wifireMux_T_422 connect _out_wifireMux_WIRE[105], _out_wifireMux_T_426 connect _out_wifireMux_WIRE[106], _out_wifireMux_T_430 connect _out_wifireMux_WIRE[107], _out_wifireMux_T_434 connect _out_wifireMux_WIRE[108], _out_wifireMux_T_438 connect _out_wifireMux_WIRE[109], _out_wifireMux_T_442 connect _out_wifireMux_WIRE[110], _out_wifireMux_T_446 connect _out_wifireMux_WIRE[111], _out_wifireMux_T_450 connect _out_wifireMux_WIRE[112], _out_wifireMux_T_454 connect _out_wifireMux_WIRE[113], _out_wifireMux_T_458 connect _out_wifireMux_WIRE[114], _out_wifireMux_T_462 connect _out_wifireMux_WIRE[115], _out_wifireMux_T_466 connect _out_wifireMux_WIRE[116], _out_wifireMux_T_470 connect _out_wifireMux_WIRE[117], _out_wifireMux_T_474 connect _out_wifireMux_WIRE[118], _out_wifireMux_T_478 connect _out_wifireMux_WIRE[119], _out_wifireMux_T_482 connect _out_wifireMux_WIRE[120], _out_wifireMux_T_486 connect _out_wifireMux_WIRE[121], _out_wifireMux_T_490 connect _out_wifireMux_WIRE[122], _out_wifireMux_T_494 connect _out_wifireMux_WIRE[123], _out_wifireMux_T_498 connect _out_wifireMux_WIRE[124], _out_wifireMux_T_502 connect _out_wifireMux_WIRE[125], _out_wifireMux_T_506 connect _out_wifireMux_WIRE[126], _out_wifireMux_T_510 connect _out_wifireMux_WIRE[127], _out_wifireMux_T_514 node out_wifireMux = mux(_out_wifireMux_T_515, UInt<1>(0h1), _out_wifireMux_WIRE[out_iindex]) node _out_rofireMux_T = and(out_back_front_q.io.deq.valid, out.ready) node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_back_front_q.io.deq.bits.read) wire out_rofireMux_out : UInt<1> node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_27) connect out_rofireMux_out, UInt<1>(0h1) connect out_roready[34], _out_rofireMux_T_3 node _out_rofireMux_T_4 = eq(_out_T_27, UInt<1>(0h0)) node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) wire out_rofireMux_out_1 : UInt<1> node _out_rofireMux_T_6 = and(_out_rofireMux_T_1, out_backSel_1) node _out_rofireMux_T_7 = and(_out_rofireMux_T_6, UInt<1>(0h1)) connect out_rofireMux_out_1, UInt<1>(0h1) node _out_rofireMux_T_8 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_9 = or(out_rofireMux_out_1, _out_rofireMux_T_8) wire out_rofireMux_out_2 : UInt<1> node _out_rofireMux_T_10 = and(_out_rofireMux_T_1, out_backSel_2) node _out_rofireMux_T_11 = and(_out_rofireMux_T_10, UInt<1>(0h1)) connect out_rofireMux_out_2, UInt<1>(0h1) node _out_rofireMux_T_12 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_13 = or(out_rofireMux_out_2, _out_rofireMux_T_12) wire out_rofireMux_out_3 : UInt<1> node _out_rofireMux_T_14 = and(_out_rofireMux_T_1, out_backSel_3) node _out_rofireMux_T_15 = and(_out_rofireMux_T_14, UInt<1>(0h1)) connect out_rofireMux_out_3, UInt<1>(0h1) node _out_rofireMux_T_16 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_17 = or(out_rofireMux_out_3, _out_rofireMux_T_16) wire out_rofireMux_out_4 : UInt<1> node _out_rofireMux_T_18 = and(_out_rofireMux_T_1, out_backSel_4) node _out_rofireMux_T_19 = and(_out_rofireMux_T_18, UInt<1>(0h1)) connect out_rofireMux_out_4, UInt<1>(0h1) node _out_rofireMux_T_20 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_21 = or(out_rofireMux_out_4, _out_rofireMux_T_20) wire out_rofireMux_out_5 : UInt<1> node _out_rofireMux_T_22 = and(_out_rofireMux_T_1, out_backSel_5) node _out_rofireMux_T_23 = and(_out_rofireMux_T_22, UInt<1>(0h1)) connect out_rofireMux_out_5, UInt<1>(0h1) node _out_rofireMux_T_24 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_25 = or(out_rofireMux_out_5, _out_rofireMux_T_24) wire out_rofireMux_out_6 : UInt<1> node _out_rofireMux_T_26 = and(_out_rofireMux_T_1, out_backSel_6) node _out_rofireMux_T_27 = and(_out_rofireMux_T_26, UInt<1>(0h1)) connect out_rofireMux_out_6, UInt<1>(0h1) node _out_rofireMux_T_28 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_29 = or(out_rofireMux_out_6, _out_rofireMux_T_28) wire out_rofireMux_out_7 : UInt<1> node _out_rofireMux_T_30 = and(_out_rofireMux_T_1, out_backSel_7) node _out_rofireMux_T_31 = and(_out_rofireMux_T_30, UInt<1>(0h1)) connect out_rofireMux_out_7, UInt<1>(0h1) node _out_rofireMux_T_32 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_33 = or(out_rofireMux_out_7, _out_rofireMux_T_32) wire out_rofireMux_out_8 : UInt<1> node _out_rofireMux_T_34 = and(_out_rofireMux_T_1, out_backSel_8) node _out_rofireMux_T_35 = and(_out_rofireMux_T_34, _out_T_3) connect out_rofireMux_out_8, UInt<1>(0h1) connect out_roready[4], _out_rofireMux_T_35 connect out_roready[3], _out_rofireMux_T_35 node _out_rofireMux_T_36 = eq(_out_T_3, UInt<1>(0h0)) node _out_rofireMux_T_37 = or(out_rofireMux_out_8, _out_rofireMux_T_36) wire out_rofireMux_out_9 : UInt<1> node _out_rofireMux_T_38 = and(_out_rofireMux_T_1, out_backSel_9) node _out_rofireMux_T_39 = and(_out_rofireMux_T_38, UInt<1>(0h1)) connect out_rofireMux_out_9, UInt<1>(0h1) node _out_rofireMux_T_40 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_41 = or(out_rofireMux_out_9, _out_rofireMux_T_40) wire out_rofireMux_out_10 : UInt<1> node _out_rofireMux_T_42 = and(_out_rofireMux_T_1, out_backSel_10) node _out_rofireMux_T_43 = and(_out_rofireMux_T_42, UInt<1>(0h1)) connect out_rofireMux_out_10, UInt<1>(0h1) node _out_rofireMux_T_44 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_45 = or(out_rofireMux_out_10, _out_rofireMux_T_44) wire out_rofireMux_out_11 : UInt<1> node _out_rofireMux_T_46 = and(_out_rofireMux_T_1, out_backSel_11) node _out_rofireMux_T_47 = and(_out_rofireMux_T_46, UInt<1>(0h1)) connect out_rofireMux_out_11, UInt<1>(0h1) node _out_rofireMux_T_48 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_49 = or(out_rofireMux_out_11, _out_rofireMux_T_48) wire out_rofireMux_out_12 : UInt<1> node _out_rofireMux_T_50 = and(_out_rofireMux_T_1, out_backSel_12) node _out_rofireMux_T_51 = and(_out_rofireMux_T_50, UInt<1>(0h1)) connect out_rofireMux_out_12, UInt<1>(0h1) node _out_rofireMux_T_52 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_53 = or(out_rofireMux_out_12, _out_rofireMux_T_52) wire out_rofireMux_out_13 : UInt<1> node _out_rofireMux_T_54 = and(_out_rofireMux_T_1, out_backSel_13) node _out_rofireMux_T_55 = and(_out_rofireMux_T_54, UInt<1>(0h1)) connect out_rofireMux_out_13, UInt<1>(0h1) node _out_rofireMux_T_56 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_57 = or(out_rofireMux_out_13, _out_rofireMux_T_56) wire out_rofireMux_out_14 : UInt<1> node _out_rofireMux_T_58 = and(_out_rofireMux_T_1, out_backSel_14) node _out_rofireMux_T_59 = and(_out_rofireMux_T_58, UInt<1>(0h1)) connect out_rofireMux_out_14, UInt<1>(0h1) node _out_rofireMux_T_60 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_61 = or(out_rofireMux_out_14, _out_rofireMux_T_60) wire out_rofireMux_out_15 : UInt<1> node _out_rofireMux_T_62 = and(_out_rofireMux_T_1, out_backSel_15) node _out_rofireMux_T_63 = and(_out_rofireMux_T_62, UInt<1>(0h1)) connect out_rofireMux_out_15, UInt<1>(0h1) node _out_rofireMux_T_64 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_65 = or(out_rofireMux_out_15, _out_rofireMux_T_64) wire out_rofireMux_out_16 : UInt<1> node _out_rofireMux_T_66 = and(_out_rofireMux_T_1, out_backSel_16) node _out_rofireMux_T_67 = and(_out_rofireMux_T_66, _out_T_25) connect out_rofireMux_out_16, UInt<1>(0h1) connect out_roready[33], _out_rofireMux_T_67 connect out_roready[32], _out_rofireMux_T_67 node _out_rofireMux_T_68 = eq(_out_T_25, UInt<1>(0h0)) node _out_rofireMux_T_69 = or(out_rofireMux_out_16, _out_rofireMux_T_68) wire out_rofireMux_out_17 : UInt<1> node _out_rofireMux_T_70 = and(_out_rofireMux_T_1, out_backSel_17) node _out_rofireMux_T_71 = and(_out_rofireMux_T_70, _out_T_29) connect out_rofireMux_out_17, UInt<1>(0h1) connect out_roready[36], _out_rofireMux_T_71 connect out_roready[35], _out_rofireMux_T_71 node _out_rofireMux_T_72 = eq(_out_T_29, UInt<1>(0h0)) node _out_rofireMux_T_73 = or(out_rofireMux_out_17, _out_rofireMux_T_72) wire out_rofireMux_out_18 : UInt<1> node _out_rofireMux_T_74 = and(_out_rofireMux_T_1, out_backSel_18) node _out_rofireMux_T_75 = and(_out_rofireMux_T_74, _out_T_19) connect out_rofireMux_out_18, UInt<1>(0h1) connect out_roready[27], _out_rofireMux_T_75 connect out_roready[26], _out_rofireMux_T_75 node _out_rofireMux_T_76 = eq(_out_T_19, UInt<1>(0h0)) node _out_rofireMux_T_77 = or(out_rofireMux_out_18, _out_rofireMux_T_76) wire out_rofireMux_out_19 : UInt<1> node _out_rofireMux_T_78 = and(_out_rofireMux_T_1, out_backSel_19) node _out_rofireMux_T_79 = and(_out_rofireMux_T_78, _out_T_33) connect out_rofireMux_out_19, UInt<1>(0h1) connect out_roready[40], _out_rofireMux_T_79 connect out_roready[39], _out_rofireMux_T_79 node _out_rofireMux_T_80 = eq(_out_T_33, UInt<1>(0h0)) node _out_rofireMux_T_81 = or(out_rofireMux_out_19, _out_rofireMux_T_80) wire out_rofireMux_out_20 : UInt<1> node _out_rofireMux_T_82 = and(_out_rofireMux_T_1, out_backSel_20) node _out_rofireMux_T_83 = and(_out_rofireMux_T_82, _out_T_23) connect out_rofireMux_out_20, UInt<1>(0h1) connect out_roready[31], _out_rofireMux_T_83 connect out_roready[30], _out_rofireMux_T_83 node _out_rofireMux_T_84 = eq(_out_T_23, UInt<1>(0h0)) node _out_rofireMux_T_85 = or(out_rofireMux_out_20, _out_rofireMux_T_84) wire out_rofireMux_out_21 : UInt<1> node _out_rofireMux_T_86 = and(_out_rofireMux_T_1, out_backSel_21) node _out_rofireMux_T_87 = and(_out_rofireMux_T_86, _out_T_35) connect out_rofireMux_out_21, UInt<1>(0h1) connect out_roready[42], _out_rofireMux_T_87 connect out_roready[41], _out_rofireMux_T_87 node _out_rofireMux_T_88 = eq(_out_T_35, UInt<1>(0h0)) node _out_rofireMux_T_89 = or(out_rofireMux_out_21, _out_rofireMux_T_88) wire out_rofireMux_out_22 : UInt<1> node _out_rofireMux_T_90 = and(_out_rofireMux_T_1, out_backSel_22) node _out_rofireMux_T_91 = and(_out_rofireMux_T_90, _out_T_21) connect out_rofireMux_out_22, UInt<1>(0h1) connect out_roready[29], _out_rofireMux_T_91 connect out_roready[28], _out_rofireMux_T_91 node _out_rofireMux_T_92 = eq(_out_T_21, UInt<1>(0h0)) node _out_rofireMux_T_93 = or(out_rofireMux_out_22, _out_rofireMux_T_92) wire out_rofireMux_out_23 : UInt<1> node _out_rofireMux_T_94 = and(_out_rofireMux_T_1, out_backSel_23) node _out_rofireMux_T_95 = and(_out_rofireMux_T_94, _out_T_31) connect out_rofireMux_out_23, UInt<1>(0h1) connect out_roready[38], _out_rofireMux_T_95 connect out_roready[37], _out_rofireMux_T_95 node _out_rofireMux_T_96 = eq(_out_T_31, UInt<1>(0h0)) node _out_rofireMux_T_97 = or(out_rofireMux_out_23, _out_rofireMux_T_96) wire out_rofireMux_out_24 : UInt<1> node _out_rofireMux_T_98 = and(_out_rofireMux_T_1, out_backSel_24) node _out_rofireMux_T_99 = and(_out_rofireMux_T_98, UInt<1>(0h1)) connect out_rofireMux_out_24, UInt<1>(0h1) node _out_rofireMux_T_100 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_101 = or(out_rofireMux_out_24, _out_rofireMux_T_100) wire out_rofireMux_out_25 : UInt<1> node _out_rofireMux_T_102 = and(_out_rofireMux_T_1, out_backSel_25) node _out_rofireMux_T_103 = and(_out_rofireMux_T_102, UInt<1>(0h1)) connect out_rofireMux_out_25, UInt<1>(0h1) node _out_rofireMux_T_104 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_105 = or(out_rofireMux_out_25, _out_rofireMux_T_104) wire out_rofireMux_out_26 : UInt<1> node _out_rofireMux_T_106 = and(_out_rofireMux_T_1, out_backSel_26) node _out_rofireMux_T_107 = and(_out_rofireMux_T_106, UInt<1>(0h1)) connect out_rofireMux_out_26, UInt<1>(0h1) node _out_rofireMux_T_108 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_109 = or(out_rofireMux_out_26, _out_rofireMux_T_108) wire out_rofireMux_out_27 : UInt<1> node _out_rofireMux_T_110 = and(_out_rofireMux_T_1, out_backSel_27) node _out_rofireMux_T_111 = and(_out_rofireMux_T_110, UInt<1>(0h1)) connect out_rofireMux_out_27, UInt<1>(0h1) node _out_rofireMux_T_112 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_113 = or(out_rofireMux_out_27, _out_rofireMux_T_112) wire out_rofireMux_out_28 : UInt<1> node _out_rofireMux_T_114 = and(_out_rofireMux_T_1, out_backSel_28) node _out_rofireMux_T_115 = and(_out_rofireMux_T_114, UInt<1>(0h1)) connect out_rofireMux_out_28, UInt<1>(0h1) node _out_rofireMux_T_116 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_117 = or(out_rofireMux_out_28, _out_rofireMux_T_116) wire out_rofireMux_out_29 : UInt<1> node _out_rofireMux_T_118 = and(_out_rofireMux_T_1, out_backSel_29) node _out_rofireMux_T_119 = and(_out_rofireMux_T_118, UInt<1>(0h1)) connect out_rofireMux_out_29, UInt<1>(0h1) node _out_rofireMux_T_120 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_121 = or(out_rofireMux_out_29, _out_rofireMux_T_120) wire out_rofireMux_out_30 : UInt<1> node _out_rofireMux_T_122 = and(_out_rofireMux_T_1, out_backSel_30) node _out_rofireMux_T_123 = and(_out_rofireMux_T_122, UInt<1>(0h1)) connect out_rofireMux_out_30, UInt<1>(0h1) node _out_rofireMux_T_124 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_125 = or(out_rofireMux_out_30, _out_rofireMux_T_124) wire out_rofireMux_out_31 : UInt<1> node _out_rofireMux_T_126 = and(_out_rofireMux_T_1, out_backSel_31) node _out_rofireMux_T_127 = and(_out_rofireMux_T_126, UInt<1>(0h1)) connect out_rofireMux_out_31, UInt<1>(0h1) node _out_rofireMux_T_128 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_129 = or(out_rofireMux_out_31, _out_rofireMux_T_128) wire out_rofireMux_out_32 : UInt<1> node _out_rofireMux_T_130 = and(_out_rofireMux_T_1, out_backSel_32) node _out_rofireMux_T_131 = and(_out_rofireMux_T_130, UInt<1>(0h1)) connect out_rofireMux_out_32, UInt<1>(0h1) node _out_rofireMux_T_132 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_133 = or(out_rofireMux_out_32, _out_rofireMux_T_132) wire out_rofireMux_out_33 : UInt<1> node _out_rofireMux_T_134 = and(_out_rofireMux_T_1, out_backSel_33) node _out_rofireMux_T_135 = and(_out_rofireMux_T_134, UInt<1>(0h1)) connect out_rofireMux_out_33, UInt<1>(0h1) node _out_rofireMux_T_136 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_137 = or(out_rofireMux_out_33, _out_rofireMux_T_136) wire out_rofireMux_out_34 : UInt<1> node _out_rofireMux_T_138 = and(_out_rofireMux_T_1, out_backSel_34) node _out_rofireMux_T_139 = and(_out_rofireMux_T_138, UInt<1>(0h1)) connect out_rofireMux_out_34, UInt<1>(0h1) node _out_rofireMux_T_140 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_141 = or(out_rofireMux_out_34, _out_rofireMux_T_140) wire out_rofireMux_out_35 : UInt<1> node _out_rofireMux_T_142 = and(_out_rofireMux_T_1, out_backSel_35) node _out_rofireMux_T_143 = and(_out_rofireMux_T_142, UInt<1>(0h1)) connect out_rofireMux_out_35, UInt<1>(0h1) node _out_rofireMux_T_144 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_145 = or(out_rofireMux_out_35, _out_rofireMux_T_144) wire out_rofireMux_out_36 : UInt<1> node _out_rofireMux_T_146 = and(_out_rofireMux_T_1, out_backSel_36) node _out_rofireMux_T_147 = and(_out_rofireMux_T_146, UInt<1>(0h1)) connect out_rofireMux_out_36, UInt<1>(0h1) node _out_rofireMux_T_148 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_149 = or(out_rofireMux_out_36, _out_rofireMux_T_148) wire out_rofireMux_out_37 : UInt<1> node _out_rofireMux_T_150 = and(_out_rofireMux_T_1, out_backSel_37) node _out_rofireMux_T_151 = and(_out_rofireMux_T_150, UInt<1>(0h1)) connect out_rofireMux_out_37, UInt<1>(0h1) node _out_rofireMux_T_152 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_153 = or(out_rofireMux_out_37, _out_rofireMux_T_152) wire out_rofireMux_out_38 : UInt<1> node _out_rofireMux_T_154 = and(_out_rofireMux_T_1, out_backSel_38) node _out_rofireMux_T_155 = and(_out_rofireMux_T_154, UInt<1>(0h1)) connect out_rofireMux_out_38, UInt<1>(0h1) node _out_rofireMux_T_156 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_157 = or(out_rofireMux_out_38, _out_rofireMux_T_156) wire out_rofireMux_out_39 : UInt<1> node _out_rofireMux_T_158 = and(_out_rofireMux_T_1, out_backSel_39) node _out_rofireMux_T_159 = and(_out_rofireMux_T_158, UInt<1>(0h1)) connect out_rofireMux_out_39, UInt<1>(0h1) node _out_rofireMux_T_160 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_161 = or(out_rofireMux_out_39, _out_rofireMux_T_160) wire out_rofireMux_out_40 : UInt<1> node _out_rofireMux_T_162 = and(_out_rofireMux_T_1, out_backSel_40) node _out_rofireMux_T_163 = and(_out_rofireMux_T_162, UInt<1>(0h1)) connect out_rofireMux_out_40, UInt<1>(0h1) node _out_rofireMux_T_164 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_165 = or(out_rofireMux_out_40, _out_rofireMux_T_164) wire out_rofireMux_out_41 : UInt<1> node _out_rofireMux_T_166 = and(_out_rofireMux_T_1, out_backSel_41) node _out_rofireMux_T_167 = and(_out_rofireMux_T_166, UInt<1>(0h1)) connect out_rofireMux_out_41, UInt<1>(0h1) node _out_rofireMux_T_168 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_169 = or(out_rofireMux_out_41, _out_rofireMux_T_168) wire out_rofireMux_out_42 : UInt<1> node _out_rofireMux_T_170 = and(_out_rofireMux_T_1, out_backSel_42) node _out_rofireMux_T_171 = and(_out_rofireMux_T_170, UInt<1>(0h1)) connect out_rofireMux_out_42, UInt<1>(0h1) node _out_rofireMux_T_172 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_173 = or(out_rofireMux_out_42, _out_rofireMux_T_172) wire out_rofireMux_out_43 : UInt<1> node _out_rofireMux_T_174 = and(_out_rofireMux_T_1, out_backSel_43) node _out_rofireMux_T_175 = and(_out_rofireMux_T_174, UInt<1>(0h1)) connect out_rofireMux_out_43, UInt<1>(0h1) node _out_rofireMux_T_176 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_177 = or(out_rofireMux_out_43, _out_rofireMux_T_176) wire out_rofireMux_out_44 : UInt<1> node _out_rofireMux_T_178 = and(_out_rofireMux_T_1, out_backSel_44) node _out_rofireMux_T_179 = and(_out_rofireMux_T_178, UInt<1>(0h1)) connect out_rofireMux_out_44, UInt<1>(0h1) node _out_rofireMux_T_180 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_181 = or(out_rofireMux_out_44, _out_rofireMux_T_180) wire out_rofireMux_out_45 : UInt<1> node _out_rofireMux_T_182 = and(_out_rofireMux_T_1, out_backSel_45) node _out_rofireMux_T_183 = and(_out_rofireMux_T_182, UInt<1>(0h1)) connect out_rofireMux_out_45, UInt<1>(0h1) node _out_rofireMux_T_184 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_185 = or(out_rofireMux_out_45, _out_rofireMux_T_184) wire out_rofireMux_out_46 : UInt<1> node _out_rofireMux_T_186 = and(_out_rofireMux_T_1, out_backSel_46) node _out_rofireMux_T_187 = and(_out_rofireMux_T_186, UInt<1>(0h1)) connect out_rofireMux_out_46, UInt<1>(0h1) node _out_rofireMux_T_188 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_189 = or(out_rofireMux_out_46, _out_rofireMux_T_188) wire out_rofireMux_out_47 : UInt<1> node _out_rofireMux_T_190 = and(_out_rofireMux_T_1, out_backSel_47) node _out_rofireMux_T_191 = and(_out_rofireMux_T_190, UInt<1>(0h1)) connect out_rofireMux_out_47, UInt<1>(0h1) node _out_rofireMux_T_192 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_193 = or(out_rofireMux_out_47, _out_rofireMux_T_192) wire out_rofireMux_out_48 : UInt<1> node _out_rofireMux_T_194 = and(_out_rofireMux_T_1, out_backSel_48) node _out_rofireMux_T_195 = and(_out_rofireMux_T_194, UInt<1>(0h1)) connect out_rofireMux_out_48, UInt<1>(0h1) node _out_rofireMux_T_196 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_197 = or(out_rofireMux_out_48, _out_rofireMux_T_196) wire out_rofireMux_out_49 : UInt<1> node _out_rofireMux_T_198 = and(_out_rofireMux_T_1, out_backSel_49) node _out_rofireMux_T_199 = and(_out_rofireMux_T_198, UInt<1>(0h1)) connect out_rofireMux_out_49, UInt<1>(0h1) node _out_rofireMux_T_200 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_201 = or(out_rofireMux_out_49, _out_rofireMux_T_200) wire out_rofireMux_out_50 : UInt<1> node _out_rofireMux_T_202 = and(_out_rofireMux_T_1, out_backSel_50) node _out_rofireMux_T_203 = and(_out_rofireMux_T_202, UInt<1>(0h1)) connect out_rofireMux_out_50, UInt<1>(0h1) node _out_rofireMux_T_204 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_205 = or(out_rofireMux_out_50, _out_rofireMux_T_204) wire out_rofireMux_out_51 : UInt<1> node _out_rofireMux_T_206 = and(_out_rofireMux_T_1, out_backSel_51) node _out_rofireMux_T_207 = and(_out_rofireMux_T_206, UInt<1>(0h1)) connect out_rofireMux_out_51, UInt<1>(0h1) node _out_rofireMux_T_208 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_209 = or(out_rofireMux_out_51, _out_rofireMux_T_208) wire out_rofireMux_out_52 : UInt<1> node _out_rofireMux_T_210 = and(_out_rofireMux_T_1, out_backSel_52) node _out_rofireMux_T_211 = and(_out_rofireMux_T_210, UInt<1>(0h1)) connect out_rofireMux_out_52, UInt<1>(0h1) node _out_rofireMux_T_212 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_213 = or(out_rofireMux_out_52, _out_rofireMux_T_212) wire out_rofireMux_out_53 : UInt<1> node _out_rofireMux_T_214 = and(_out_rofireMux_T_1, out_backSel_53) node _out_rofireMux_T_215 = and(_out_rofireMux_T_214, UInt<1>(0h1)) connect out_rofireMux_out_53, UInt<1>(0h1) node _out_rofireMux_T_216 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_217 = or(out_rofireMux_out_53, _out_rofireMux_T_216) wire out_rofireMux_out_54 : UInt<1> node _out_rofireMux_T_218 = and(_out_rofireMux_T_1, out_backSel_54) node _out_rofireMux_T_219 = and(_out_rofireMux_T_218, UInt<1>(0h1)) connect out_rofireMux_out_54, UInt<1>(0h1) node _out_rofireMux_T_220 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_221 = or(out_rofireMux_out_54, _out_rofireMux_T_220) wire out_rofireMux_out_55 : UInt<1> node _out_rofireMux_T_222 = and(_out_rofireMux_T_1, out_backSel_55) node _out_rofireMux_T_223 = and(_out_rofireMux_T_222, UInt<1>(0h1)) connect out_rofireMux_out_55, UInt<1>(0h1) node _out_rofireMux_T_224 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_225 = or(out_rofireMux_out_55, _out_rofireMux_T_224) wire out_rofireMux_out_56 : UInt<1> node _out_rofireMux_T_226 = and(_out_rofireMux_T_1, out_backSel_56) node _out_rofireMux_T_227 = and(_out_rofireMux_T_226, UInt<1>(0h1)) connect out_rofireMux_out_56, UInt<1>(0h1) node _out_rofireMux_T_228 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_229 = or(out_rofireMux_out_56, _out_rofireMux_T_228) wire out_rofireMux_out_57 : UInt<1> node _out_rofireMux_T_230 = and(_out_rofireMux_T_1, out_backSel_57) node _out_rofireMux_T_231 = and(_out_rofireMux_T_230, UInt<1>(0h1)) connect out_rofireMux_out_57, UInt<1>(0h1) node _out_rofireMux_T_232 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_233 = or(out_rofireMux_out_57, _out_rofireMux_T_232) wire out_rofireMux_out_58 : UInt<1> node _out_rofireMux_T_234 = and(_out_rofireMux_T_1, out_backSel_58) node _out_rofireMux_T_235 = and(_out_rofireMux_T_234, UInt<1>(0h1)) connect out_rofireMux_out_58, UInt<1>(0h1) node _out_rofireMux_T_236 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_237 = or(out_rofireMux_out_58, _out_rofireMux_T_236) wire out_rofireMux_out_59 : UInt<1> node _out_rofireMux_T_238 = and(_out_rofireMux_T_1, out_backSel_59) node _out_rofireMux_T_239 = and(_out_rofireMux_T_238, UInt<1>(0h1)) connect out_rofireMux_out_59, UInt<1>(0h1) node _out_rofireMux_T_240 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_241 = or(out_rofireMux_out_59, _out_rofireMux_T_240) wire out_rofireMux_out_60 : UInt<1> node _out_rofireMux_T_242 = and(_out_rofireMux_T_1, out_backSel_60) node _out_rofireMux_T_243 = and(_out_rofireMux_T_242, UInt<1>(0h1)) connect out_rofireMux_out_60, UInt<1>(0h1) node _out_rofireMux_T_244 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_245 = or(out_rofireMux_out_60, _out_rofireMux_T_244) wire out_rofireMux_out_61 : UInt<1> node _out_rofireMux_T_246 = and(_out_rofireMux_T_1, out_backSel_61) node _out_rofireMux_T_247 = and(_out_rofireMux_T_246, UInt<1>(0h1)) connect out_rofireMux_out_61, UInt<1>(0h1) node _out_rofireMux_T_248 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_249 = or(out_rofireMux_out_61, _out_rofireMux_T_248) wire out_rofireMux_out_62 : UInt<1> node _out_rofireMux_T_250 = and(_out_rofireMux_T_1, out_backSel_62) node _out_rofireMux_T_251 = and(_out_rofireMux_T_250, UInt<1>(0h1)) connect out_rofireMux_out_62, UInt<1>(0h1) node _out_rofireMux_T_252 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_253 = or(out_rofireMux_out_62, _out_rofireMux_T_252) wire out_rofireMux_out_63 : UInt<1> node _out_rofireMux_T_254 = and(_out_rofireMux_T_1, out_backSel_63) node _out_rofireMux_T_255 = and(_out_rofireMux_T_254, UInt<1>(0h1)) connect out_rofireMux_out_63, UInt<1>(0h1) node _out_rofireMux_T_256 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_257 = or(out_rofireMux_out_63, _out_rofireMux_T_256) wire out_rofireMux_out_64 : UInt<1> node _out_rofireMux_T_258 = and(_out_rofireMux_T_1, out_backSel_64) node _out_rofireMux_T_259 = and(_out_rofireMux_T_258, _out_T_13) connect out_rofireMux_out_64, UInt<1>(0h1) connect out_roready[19], _out_rofireMux_T_259 connect out_roready[18], _out_rofireMux_T_259 connect out_roready[17], _out_rofireMux_T_259 node _out_rofireMux_T_260 = eq(_out_T_13, UInt<1>(0h0)) node _out_rofireMux_T_261 = or(out_rofireMux_out_64, _out_rofireMux_T_260) wire out_rofireMux_out_65 : UInt<1> node _out_rofireMux_T_262 = and(_out_rofireMux_T_1, out_backSel_65) node _out_rofireMux_T_263 = and(_out_rofireMux_T_262, UInt<1>(0h1)) connect out_rofireMux_out_65, UInt<1>(0h1) node _out_rofireMux_T_264 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_265 = or(out_rofireMux_out_65, _out_rofireMux_T_264) wire out_rofireMux_out_66 : UInt<1> node _out_rofireMux_T_266 = and(_out_rofireMux_T_1, out_backSel_66) node _out_rofireMux_T_267 = and(_out_rofireMux_T_266, UInt<1>(0h1)) connect out_rofireMux_out_66, UInt<1>(0h1) node _out_rofireMux_T_268 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_269 = or(out_rofireMux_out_66, _out_rofireMux_T_268) wire out_rofireMux_out_67 : UInt<1> node _out_rofireMux_T_270 = and(_out_rofireMux_T_1, out_backSel_67) node _out_rofireMux_T_271 = and(_out_rofireMux_T_270, UInt<1>(0h1)) connect out_rofireMux_out_67, UInt<1>(0h1) node _out_rofireMux_T_272 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_273 = or(out_rofireMux_out_67, _out_rofireMux_T_272) wire out_rofireMux_out_68 : UInt<1> node _out_rofireMux_T_274 = and(_out_rofireMux_T_1, out_backSel_68) node _out_rofireMux_T_275 = and(_out_rofireMux_T_274, UInt<1>(0h1)) connect out_rofireMux_out_68, UInt<1>(0h1) node _out_rofireMux_T_276 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_277 = or(out_rofireMux_out_68, _out_rofireMux_T_276) wire out_rofireMux_out_69 : UInt<1> node _out_rofireMux_T_278 = and(_out_rofireMux_T_1, out_backSel_69) node _out_rofireMux_T_279 = and(_out_rofireMux_T_278, UInt<1>(0h1)) connect out_rofireMux_out_69, UInt<1>(0h1) node _out_rofireMux_T_280 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_281 = or(out_rofireMux_out_69, _out_rofireMux_T_280) wire out_rofireMux_out_70 : UInt<1> node _out_rofireMux_T_282 = and(_out_rofireMux_T_1, out_backSel_70) node _out_rofireMux_T_283 = and(_out_rofireMux_T_282, UInt<1>(0h1)) connect out_rofireMux_out_70, UInt<1>(0h1) node _out_rofireMux_T_284 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_285 = or(out_rofireMux_out_70, _out_rofireMux_T_284) wire out_rofireMux_out_71 : UInt<1> node _out_rofireMux_T_286 = and(_out_rofireMux_T_1, out_backSel_71) node _out_rofireMux_T_287 = and(_out_rofireMux_T_286, UInt<1>(0h1)) connect out_rofireMux_out_71, UInt<1>(0h1) node _out_rofireMux_T_288 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_289 = or(out_rofireMux_out_71, _out_rofireMux_T_288) wire out_rofireMux_out_72 : UInt<1> node _out_rofireMux_T_290 = and(_out_rofireMux_T_1, out_backSel_72) node _out_rofireMux_T_291 = and(_out_rofireMux_T_290, _out_T_7) connect out_rofireMux_out_72, UInt<1>(0h1) connect out_roready[10], _out_rofireMux_T_291 connect out_roready[9], _out_rofireMux_T_291 connect out_roready[8], _out_rofireMux_T_291 node _out_rofireMux_T_292 = eq(_out_T_7, UInt<1>(0h0)) node _out_rofireMux_T_293 = or(out_rofireMux_out_72, _out_rofireMux_T_292) wire out_rofireMux_out_73 : UInt<1> node _out_rofireMux_T_294 = and(_out_rofireMux_T_1, out_backSel_73) node _out_rofireMux_T_295 = and(_out_rofireMux_T_294, UInt<1>(0h1)) connect out_rofireMux_out_73, UInt<1>(0h1) node _out_rofireMux_T_296 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_297 = or(out_rofireMux_out_73, _out_rofireMux_T_296) wire out_rofireMux_out_74 : UInt<1> node _out_rofireMux_T_298 = and(_out_rofireMux_T_1, out_backSel_74) node _out_rofireMux_T_299 = and(_out_rofireMux_T_298, UInt<1>(0h1)) connect out_rofireMux_out_74, UInt<1>(0h1) node _out_rofireMux_T_300 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_301 = or(out_rofireMux_out_74, _out_rofireMux_T_300) wire out_rofireMux_out_75 : UInt<1> node _out_rofireMux_T_302 = and(_out_rofireMux_T_1, out_backSel_75) node _out_rofireMux_T_303 = and(_out_rofireMux_T_302, UInt<1>(0h1)) connect out_rofireMux_out_75, UInt<1>(0h1) node _out_rofireMux_T_304 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_305 = or(out_rofireMux_out_75, _out_rofireMux_T_304) wire out_rofireMux_out_76 : UInt<1> node _out_rofireMux_T_306 = and(_out_rofireMux_T_1, out_backSel_76) node _out_rofireMux_T_307 = and(_out_rofireMux_T_306, UInt<1>(0h1)) connect out_rofireMux_out_76, UInt<1>(0h1) node _out_rofireMux_T_308 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_309 = or(out_rofireMux_out_76, _out_rofireMux_T_308) wire out_rofireMux_out_77 : UInt<1> node _out_rofireMux_T_310 = and(_out_rofireMux_T_1, out_backSel_77) node _out_rofireMux_T_311 = and(_out_rofireMux_T_310, UInt<1>(0h1)) connect out_rofireMux_out_77, UInt<1>(0h1) node _out_rofireMux_T_312 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_313 = or(out_rofireMux_out_77, _out_rofireMux_T_312) wire out_rofireMux_out_78 : UInt<1> node _out_rofireMux_T_314 = and(_out_rofireMux_T_1, out_backSel_78) node _out_rofireMux_T_315 = and(_out_rofireMux_T_314, UInt<1>(0h1)) connect out_rofireMux_out_78, UInt<1>(0h1) node _out_rofireMux_T_316 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_317 = or(out_rofireMux_out_78, _out_rofireMux_T_316) wire out_rofireMux_out_79 : UInt<1> node _out_rofireMux_T_318 = and(_out_rofireMux_T_1, out_backSel_79) node _out_rofireMux_T_319 = and(_out_rofireMux_T_318, UInt<1>(0h1)) connect out_rofireMux_out_79, UInt<1>(0h1) node _out_rofireMux_T_320 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_321 = or(out_rofireMux_out_79, _out_rofireMux_T_320) wire out_rofireMux_out_80 : UInt<1> node _out_rofireMux_T_322 = and(_out_rofireMux_T_1, out_backSel_80) node _out_rofireMux_T_323 = and(_out_rofireMux_T_322, _out_T_15) connect out_rofireMux_out_80, UInt<1>(0h1) connect out_roready[22], _out_rofireMux_T_323 connect out_roready[21], _out_rofireMux_T_323 connect out_roready[20], _out_rofireMux_T_323 node _out_rofireMux_T_324 = eq(_out_T_15, UInt<1>(0h0)) node _out_rofireMux_T_325 = or(out_rofireMux_out_80, _out_rofireMux_T_324) wire out_rofireMux_out_81 : UInt<1> node _out_rofireMux_T_326 = and(_out_rofireMux_T_1, out_backSel_81) node _out_rofireMux_T_327 = and(_out_rofireMux_T_326, UInt<1>(0h1)) connect out_rofireMux_out_81, UInt<1>(0h1) node _out_rofireMux_T_328 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_329 = or(out_rofireMux_out_81, _out_rofireMux_T_328) wire out_rofireMux_out_82 : UInt<1> node _out_rofireMux_T_330 = and(_out_rofireMux_T_1, out_backSel_82) node _out_rofireMux_T_331 = and(_out_rofireMux_T_330, UInt<1>(0h1)) connect out_rofireMux_out_82, UInt<1>(0h1) node _out_rofireMux_T_332 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_333 = or(out_rofireMux_out_82, _out_rofireMux_T_332) wire out_rofireMux_out_83 : UInt<1> node _out_rofireMux_T_334 = and(_out_rofireMux_T_1, out_backSel_83) node _out_rofireMux_T_335 = and(_out_rofireMux_T_334, UInt<1>(0h1)) connect out_rofireMux_out_83, UInt<1>(0h1) node _out_rofireMux_T_336 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_337 = or(out_rofireMux_out_83, _out_rofireMux_T_336) wire out_rofireMux_out_84 : UInt<1> node _out_rofireMux_T_338 = and(_out_rofireMux_T_1, out_backSel_84) node _out_rofireMux_T_339 = and(_out_rofireMux_T_338, UInt<1>(0h1)) connect out_rofireMux_out_84, UInt<1>(0h1) node _out_rofireMux_T_340 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_341 = or(out_rofireMux_out_84, _out_rofireMux_T_340) wire out_rofireMux_out_85 : UInt<1> node _out_rofireMux_T_342 = and(_out_rofireMux_T_1, out_backSel_85) node _out_rofireMux_T_343 = and(_out_rofireMux_T_342, UInt<1>(0h1)) connect out_rofireMux_out_85, UInt<1>(0h1) node _out_rofireMux_T_344 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_345 = or(out_rofireMux_out_85, _out_rofireMux_T_344) wire out_rofireMux_out_86 : UInt<1> node _out_rofireMux_T_346 = and(_out_rofireMux_T_1, out_backSel_86) node _out_rofireMux_T_347 = and(_out_rofireMux_T_346, UInt<1>(0h1)) connect out_rofireMux_out_86, UInt<1>(0h1) node _out_rofireMux_T_348 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_349 = or(out_rofireMux_out_86, _out_rofireMux_T_348) wire out_rofireMux_out_87 : UInt<1> node _out_rofireMux_T_350 = and(_out_rofireMux_T_1, out_backSel_87) node _out_rofireMux_T_351 = and(_out_rofireMux_T_350, UInt<1>(0h1)) connect out_rofireMux_out_87, UInt<1>(0h1) node _out_rofireMux_T_352 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_353 = or(out_rofireMux_out_87, _out_rofireMux_T_352) wire out_rofireMux_out_88 : UInt<1> node _out_rofireMux_T_354 = and(_out_rofireMux_T_1, out_backSel_88) node _out_rofireMux_T_355 = and(_out_rofireMux_T_354, _out_T_9) connect out_rofireMux_out_88, UInt<1>(0h1) connect out_roready[13], _out_rofireMux_T_355 connect out_roready[12], _out_rofireMux_T_355 connect out_roready[11], _out_rofireMux_T_355 node _out_rofireMux_T_356 = eq(_out_T_9, UInt<1>(0h0)) node _out_rofireMux_T_357 = or(out_rofireMux_out_88, _out_rofireMux_T_356) wire out_rofireMux_out_89 : UInt<1> node _out_rofireMux_T_358 = and(_out_rofireMux_T_1, out_backSel_89) node _out_rofireMux_T_359 = and(_out_rofireMux_T_358, UInt<1>(0h1)) connect out_rofireMux_out_89, UInt<1>(0h1) node _out_rofireMux_T_360 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_361 = or(out_rofireMux_out_89, _out_rofireMux_T_360) wire out_rofireMux_out_90 : UInt<1> node _out_rofireMux_T_362 = and(_out_rofireMux_T_1, out_backSel_90) node _out_rofireMux_T_363 = and(_out_rofireMux_T_362, UInt<1>(0h1)) connect out_rofireMux_out_90, UInt<1>(0h1) node _out_rofireMux_T_364 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_365 = or(out_rofireMux_out_90, _out_rofireMux_T_364) wire out_rofireMux_out_91 : UInt<1> node _out_rofireMux_T_366 = and(_out_rofireMux_T_1, out_backSel_91) node _out_rofireMux_T_367 = and(_out_rofireMux_T_366, UInt<1>(0h1)) connect out_rofireMux_out_91, UInt<1>(0h1) node _out_rofireMux_T_368 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_369 = or(out_rofireMux_out_91, _out_rofireMux_T_368) wire out_rofireMux_out_92 : UInt<1> node _out_rofireMux_T_370 = and(_out_rofireMux_T_1, out_backSel_92) node _out_rofireMux_T_371 = and(_out_rofireMux_T_370, UInt<1>(0h1)) connect out_rofireMux_out_92, UInt<1>(0h1) node _out_rofireMux_T_372 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_373 = or(out_rofireMux_out_92, _out_rofireMux_T_372) wire out_rofireMux_out_93 : UInt<1> node _out_rofireMux_T_374 = and(_out_rofireMux_T_1, out_backSel_93) node _out_rofireMux_T_375 = and(_out_rofireMux_T_374, UInt<1>(0h1)) connect out_rofireMux_out_93, UInt<1>(0h1) node _out_rofireMux_T_376 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_377 = or(out_rofireMux_out_93, _out_rofireMux_T_376) wire out_rofireMux_out_94 : UInt<1> node _out_rofireMux_T_378 = and(_out_rofireMux_T_1, out_backSel_94) node _out_rofireMux_T_379 = and(_out_rofireMux_T_378, UInt<1>(0h1)) connect out_rofireMux_out_94, UInt<1>(0h1) node _out_rofireMux_T_380 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_381 = or(out_rofireMux_out_94, _out_rofireMux_T_380) wire out_rofireMux_out_95 : UInt<1> node _out_rofireMux_T_382 = and(_out_rofireMux_T_1, out_backSel_95) node _out_rofireMux_T_383 = and(_out_rofireMux_T_382, UInt<1>(0h1)) connect out_rofireMux_out_95, UInt<1>(0h1) node _out_rofireMux_T_384 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_385 = or(out_rofireMux_out_95, _out_rofireMux_T_384) wire out_rofireMux_out_96 : UInt<1> node _out_rofireMux_T_386 = and(_out_rofireMux_T_1, out_backSel_96) node _out_rofireMux_T_387 = and(_out_rofireMux_T_386, _out_T_5) connect out_rofireMux_out_96, UInt<1>(0h1) connect out_roready[7], _out_rofireMux_T_387 connect out_roready[6], _out_rofireMux_T_387 connect out_roready[5], _out_rofireMux_T_387 node _out_rofireMux_T_388 = eq(_out_T_5, UInt<1>(0h0)) node _out_rofireMux_T_389 = or(out_rofireMux_out_96, _out_rofireMux_T_388) wire out_rofireMux_out_97 : UInt<1> node _out_rofireMux_T_390 = and(_out_rofireMux_T_1, out_backSel_97) node _out_rofireMux_T_391 = and(_out_rofireMux_T_390, UInt<1>(0h1)) connect out_rofireMux_out_97, UInt<1>(0h1) node _out_rofireMux_T_392 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_393 = or(out_rofireMux_out_97, _out_rofireMux_T_392) wire out_rofireMux_out_98 : UInt<1> node _out_rofireMux_T_394 = and(_out_rofireMux_T_1, out_backSel_98) node _out_rofireMux_T_395 = and(_out_rofireMux_T_394, UInt<1>(0h1)) connect out_rofireMux_out_98, UInt<1>(0h1) node _out_rofireMux_T_396 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_397 = or(out_rofireMux_out_98, _out_rofireMux_T_396) wire out_rofireMux_out_99 : UInt<1> node _out_rofireMux_T_398 = and(_out_rofireMux_T_1, out_backSel_99) node _out_rofireMux_T_399 = and(_out_rofireMux_T_398, UInt<1>(0h1)) connect out_rofireMux_out_99, UInt<1>(0h1) node _out_rofireMux_T_400 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_401 = or(out_rofireMux_out_99, _out_rofireMux_T_400) wire out_rofireMux_out_100 : UInt<1> node _out_rofireMux_T_402 = and(_out_rofireMux_T_1, out_backSel_100) node _out_rofireMux_T_403 = and(_out_rofireMux_T_402, UInt<1>(0h1)) connect out_rofireMux_out_100, UInt<1>(0h1) node _out_rofireMux_T_404 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_405 = or(out_rofireMux_out_100, _out_rofireMux_T_404) wire out_rofireMux_out_101 : UInt<1> node _out_rofireMux_T_406 = and(_out_rofireMux_T_1, out_backSel_101) node _out_rofireMux_T_407 = and(_out_rofireMux_T_406, UInt<1>(0h1)) connect out_rofireMux_out_101, UInt<1>(0h1) node _out_rofireMux_T_408 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_409 = or(out_rofireMux_out_101, _out_rofireMux_T_408) wire out_rofireMux_out_102 : UInt<1> node _out_rofireMux_T_410 = and(_out_rofireMux_T_1, out_backSel_102) node _out_rofireMux_T_411 = and(_out_rofireMux_T_410, UInt<1>(0h1)) connect out_rofireMux_out_102, UInt<1>(0h1) node _out_rofireMux_T_412 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_413 = or(out_rofireMux_out_102, _out_rofireMux_T_412) wire out_rofireMux_out_103 : UInt<1> node _out_rofireMux_T_414 = and(_out_rofireMux_T_1, out_backSel_103) node _out_rofireMux_T_415 = and(_out_rofireMux_T_414, UInt<1>(0h1)) connect out_rofireMux_out_103, UInt<1>(0h1) node _out_rofireMux_T_416 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_417 = or(out_rofireMux_out_103, _out_rofireMux_T_416) wire out_rofireMux_out_104 : UInt<1> node _out_rofireMux_T_418 = and(_out_rofireMux_T_1, out_backSel_104) node _out_rofireMux_T_419 = and(_out_rofireMux_T_418, _out_T_1) connect out_rofireMux_out_104, UInt<1>(0h1) connect out_roready[2], _out_rofireMux_T_419 connect out_roready[1], _out_rofireMux_T_419 connect out_roready[0], _out_rofireMux_T_419 node _out_rofireMux_T_420 = eq(_out_T_1, UInt<1>(0h0)) node _out_rofireMux_T_421 = or(out_rofireMux_out_104, _out_rofireMux_T_420) wire out_rofireMux_out_105 : UInt<1> node _out_rofireMux_T_422 = and(_out_rofireMux_T_1, out_backSel_105) node _out_rofireMux_T_423 = and(_out_rofireMux_T_422, UInt<1>(0h1)) connect out_rofireMux_out_105, UInt<1>(0h1) node _out_rofireMux_T_424 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_425 = or(out_rofireMux_out_105, _out_rofireMux_T_424) wire out_rofireMux_out_106 : UInt<1> node _out_rofireMux_T_426 = and(_out_rofireMux_T_1, out_backSel_106) node _out_rofireMux_T_427 = and(_out_rofireMux_T_426, UInt<1>(0h1)) connect out_rofireMux_out_106, UInt<1>(0h1) node _out_rofireMux_T_428 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_429 = or(out_rofireMux_out_106, _out_rofireMux_T_428) wire out_rofireMux_out_107 : UInt<1> node _out_rofireMux_T_430 = and(_out_rofireMux_T_1, out_backSel_107) node _out_rofireMux_T_431 = and(_out_rofireMux_T_430, UInt<1>(0h1)) connect out_rofireMux_out_107, UInt<1>(0h1) node _out_rofireMux_T_432 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_433 = or(out_rofireMux_out_107, _out_rofireMux_T_432) wire out_rofireMux_out_108 : UInt<1> node _out_rofireMux_T_434 = and(_out_rofireMux_T_1, out_backSel_108) node _out_rofireMux_T_435 = and(_out_rofireMux_T_434, UInt<1>(0h1)) connect out_rofireMux_out_108, UInt<1>(0h1) node _out_rofireMux_T_436 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_437 = or(out_rofireMux_out_108, _out_rofireMux_T_436) wire out_rofireMux_out_109 : UInt<1> node _out_rofireMux_T_438 = and(_out_rofireMux_T_1, out_backSel_109) node _out_rofireMux_T_439 = and(_out_rofireMux_T_438, UInt<1>(0h1)) connect out_rofireMux_out_109, UInt<1>(0h1) node _out_rofireMux_T_440 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_441 = or(out_rofireMux_out_109, _out_rofireMux_T_440) wire out_rofireMux_out_110 : UInt<1> node _out_rofireMux_T_442 = and(_out_rofireMux_T_1, out_backSel_110) node _out_rofireMux_T_443 = and(_out_rofireMux_T_442, UInt<1>(0h1)) connect out_rofireMux_out_110, UInt<1>(0h1) node _out_rofireMux_T_444 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_445 = or(out_rofireMux_out_110, _out_rofireMux_T_444) wire out_rofireMux_out_111 : UInt<1> node _out_rofireMux_T_446 = and(_out_rofireMux_T_1, out_backSel_111) node _out_rofireMux_T_447 = and(_out_rofireMux_T_446, UInt<1>(0h1)) connect out_rofireMux_out_111, UInt<1>(0h1) node _out_rofireMux_T_448 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_449 = or(out_rofireMux_out_111, _out_rofireMux_T_448) wire out_rofireMux_out_112 : UInt<1> node _out_rofireMux_T_450 = and(_out_rofireMux_T_1, out_backSel_112) node _out_rofireMux_T_451 = and(_out_rofireMux_T_450, _out_T_17) connect out_rofireMux_out_112, UInt<1>(0h1) connect out_roready[25], _out_rofireMux_T_451 connect out_roready[24], _out_rofireMux_T_451 connect out_roready[23], _out_rofireMux_T_451 node _out_rofireMux_T_452 = eq(_out_T_17, UInt<1>(0h0)) node _out_rofireMux_T_453 = or(out_rofireMux_out_112, _out_rofireMux_T_452) wire out_rofireMux_out_113 : UInt<1> node _out_rofireMux_T_454 = and(_out_rofireMux_T_1, out_backSel_113) node _out_rofireMux_T_455 = and(_out_rofireMux_T_454, UInt<1>(0h1)) connect out_rofireMux_out_113, UInt<1>(0h1) node _out_rofireMux_T_456 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_457 = or(out_rofireMux_out_113, _out_rofireMux_T_456) wire out_rofireMux_out_114 : UInt<1> node _out_rofireMux_T_458 = and(_out_rofireMux_T_1, out_backSel_114) node _out_rofireMux_T_459 = and(_out_rofireMux_T_458, UInt<1>(0h1)) connect out_rofireMux_out_114, UInt<1>(0h1) node _out_rofireMux_T_460 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_461 = or(out_rofireMux_out_114, _out_rofireMux_T_460) wire out_rofireMux_out_115 : UInt<1> node _out_rofireMux_T_462 = and(_out_rofireMux_T_1, out_backSel_115) node _out_rofireMux_T_463 = and(_out_rofireMux_T_462, UInt<1>(0h1)) connect out_rofireMux_out_115, UInt<1>(0h1) node _out_rofireMux_T_464 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_465 = or(out_rofireMux_out_115, _out_rofireMux_T_464) wire out_rofireMux_out_116 : UInt<1> node _out_rofireMux_T_466 = and(_out_rofireMux_T_1, out_backSel_116) node _out_rofireMux_T_467 = and(_out_rofireMux_T_466, UInt<1>(0h1)) connect out_rofireMux_out_116, UInt<1>(0h1) node _out_rofireMux_T_468 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_469 = or(out_rofireMux_out_116, _out_rofireMux_T_468) wire out_rofireMux_out_117 : UInt<1> node _out_rofireMux_T_470 = and(_out_rofireMux_T_1, out_backSel_117) node _out_rofireMux_T_471 = and(_out_rofireMux_T_470, UInt<1>(0h1)) connect out_rofireMux_out_117, UInt<1>(0h1) node _out_rofireMux_T_472 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_473 = or(out_rofireMux_out_117, _out_rofireMux_T_472) wire out_rofireMux_out_118 : UInt<1> node _out_rofireMux_T_474 = and(_out_rofireMux_T_1, out_backSel_118) node _out_rofireMux_T_475 = and(_out_rofireMux_T_474, UInt<1>(0h1)) connect out_rofireMux_out_118, UInt<1>(0h1) node _out_rofireMux_T_476 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_477 = or(out_rofireMux_out_118, _out_rofireMux_T_476) wire out_rofireMux_out_119 : UInt<1> node _out_rofireMux_T_478 = and(_out_rofireMux_T_1, out_backSel_119) node _out_rofireMux_T_479 = and(_out_rofireMux_T_478, UInt<1>(0h1)) connect out_rofireMux_out_119, UInt<1>(0h1) node _out_rofireMux_T_480 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_481 = or(out_rofireMux_out_119, _out_rofireMux_T_480) wire out_rofireMux_out_120 : UInt<1> node _out_rofireMux_T_482 = and(_out_rofireMux_T_1, out_backSel_120) node _out_rofireMux_T_483 = and(_out_rofireMux_T_482, _out_T_11) connect out_rofireMux_out_120, UInt<1>(0h1) connect out_roready[16], _out_rofireMux_T_483 connect out_roready[15], _out_rofireMux_T_483 connect out_roready[14], _out_rofireMux_T_483 node _out_rofireMux_T_484 = eq(_out_T_11, UInt<1>(0h0)) node _out_rofireMux_T_485 = or(out_rofireMux_out_120, _out_rofireMux_T_484) wire out_rofireMux_out_121 : UInt<1> node _out_rofireMux_T_486 = and(_out_rofireMux_T_1, out_backSel_121) node _out_rofireMux_T_487 = and(_out_rofireMux_T_486, UInt<1>(0h1)) connect out_rofireMux_out_121, UInt<1>(0h1) node _out_rofireMux_T_488 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_489 = or(out_rofireMux_out_121, _out_rofireMux_T_488) wire out_rofireMux_out_122 : UInt<1> node _out_rofireMux_T_490 = and(_out_rofireMux_T_1, out_backSel_122) node _out_rofireMux_T_491 = and(_out_rofireMux_T_490, UInt<1>(0h1)) connect out_rofireMux_out_122, UInt<1>(0h1) node _out_rofireMux_T_492 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_493 = or(out_rofireMux_out_122, _out_rofireMux_T_492) wire out_rofireMux_out_123 : UInt<1> node _out_rofireMux_T_494 = and(_out_rofireMux_T_1, out_backSel_123) node _out_rofireMux_T_495 = and(_out_rofireMux_T_494, UInt<1>(0h1)) connect out_rofireMux_out_123, UInt<1>(0h1) node _out_rofireMux_T_496 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_497 = or(out_rofireMux_out_123, _out_rofireMux_T_496) wire out_rofireMux_out_124 : UInt<1> node _out_rofireMux_T_498 = and(_out_rofireMux_T_1, out_backSel_124) node _out_rofireMux_T_499 = and(_out_rofireMux_T_498, UInt<1>(0h1)) connect out_rofireMux_out_124, UInt<1>(0h1) node _out_rofireMux_T_500 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_501 = or(out_rofireMux_out_124, _out_rofireMux_T_500) wire out_rofireMux_out_125 : UInt<1> node _out_rofireMux_T_502 = and(_out_rofireMux_T_1, out_backSel_125) node _out_rofireMux_T_503 = and(_out_rofireMux_T_502, UInt<1>(0h1)) connect out_rofireMux_out_125, UInt<1>(0h1) node _out_rofireMux_T_504 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_505 = or(out_rofireMux_out_125, _out_rofireMux_T_504) wire out_rofireMux_out_126 : UInt<1> node _out_rofireMux_T_506 = and(_out_rofireMux_T_1, out_backSel_126) node _out_rofireMux_T_507 = and(_out_rofireMux_T_506, UInt<1>(0h1)) connect out_rofireMux_out_126, UInt<1>(0h1) node _out_rofireMux_T_508 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_509 = or(out_rofireMux_out_126, _out_rofireMux_T_508) wire out_rofireMux_out_127 : UInt<1> node _out_rofireMux_T_510 = and(_out_rofireMux_T_1, out_backSel_127) node _out_rofireMux_T_511 = and(_out_rofireMux_T_510, UInt<1>(0h1)) connect out_rofireMux_out_127, UInt<1>(0h1) node _out_rofireMux_T_512 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_513 = or(out_rofireMux_out_127, _out_rofireMux_T_512) node _out_rofireMux_T_514 = geq(out_oindex, UInt<8>(0h80)) wire _out_rofireMux_WIRE : UInt<1>[128] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 connect _out_rofireMux_WIRE[1], _out_rofireMux_T_9 connect _out_rofireMux_WIRE[2], _out_rofireMux_T_13 connect _out_rofireMux_WIRE[3], _out_rofireMux_T_17 connect _out_rofireMux_WIRE[4], _out_rofireMux_T_21 connect _out_rofireMux_WIRE[5], _out_rofireMux_T_25 connect _out_rofireMux_WIRE[6], _out_rofireMux_T_29 connect _out_rofireMux_WIRE[7], _out_rofireMux_T_33 connect _out_rofireMux_WIRE[8], _out_rofireMux_T_37 connect _out_rofireMux_WIRE[9], _out_rofireMux_T_41 connect _out_rofireMux_WIRE[10], _out_rofireMux_T_45 connect _out_rofireMux_WIRE[11], _out_rofireMux_T_49 connect _out_rofireMux_WIRE[12], _out_rofireMux_T_53 connect _out_rofireMux_WIRE[13], _out_rofireMux_T_57 connect _out_rofireMux_WIRE[14], _out_rofireMux_T_61 connect _out_rofireMux_WIRE[15], _out_rofireMux_T_65 connect _out_rofireMux_WIRE[16], _out_rofireMux_T_69 connect _out_rofireMux_WIRE[17], _out_rofireMux_T_73 connect _out_rofireMux_WIRE[18], _out_rofireMux_T_77 connect _out_rofireMux_WIRE[19], _out_rofireMux_T_81 connect _out_rofireMux_WIRE[20], _out_rofireMux_T_85 connect _out_rofireMux_WIRE[21], _out_rofireMux_T_89 connect _out_rofireMux_WIRE[22], _out_rofireMux_T_93 connect _out_rofireMux_WIRE[23], _out_rofireMux_T_97 connect _out_rofireMux_WIRE[24], _out_rofireMux_T_101 connect _out_rofireMux_WIRE[25], _out_rofireMux_T_105 connect _out_rofireMux_WIRE[26], _out_rofireMux_T_109 connect _out_rofireMux_WIRE[27], _out_rofireMux_T_113 connect _out_rofireMux_WIRE[28], _out_rofireMux_T_117 connect _out_rofireMux_WIRE[29], _out_rofireMux_T_121 connect _out_rofireMux_WIRE[30], _out_rofireMux_T_125 connect _out_rofireMux_WIRE[31], _out_rofireMux_T_129 connect _out_rofireMux_WIRE[32], _out_rofireMux_T_133 connect _out_rofireMux_WIRE[33], _out_rofireMux_T_137 connect _out_rofireMux_WIRE[34], _out_rofireMux_T_141 connect _out_rofireMux_WIRE[35], _out_rofireMux_T_145 connect _out_rofireMux_WIRE[36], _out_rofireMux_T_149 connect _out_rofireMux_WIRE[37], _out_rofireMux_T_153 connect _out_rofireMux_WIRE[38], _out_rofireMux_T_157 connect _out_rofireMux_WIRE[39], _out_rofireMux_T_161 connect _out_rofireMux_WIRE[40], _out_rofireMux_T_165 connect _out_rofireMux_WIRE[41], _out_rofireMux_T_169 connect _out_rofireMux_WIRE[42], _out_rofireMux_T_173 connect _out_rofireMux_WIRE[43], _out_rofireMux_T_177 connect _out_rofireMux_WIRE[44], _out_rofireMux_T_181 connect _out_rofireMux_WIRE[45], _out_rofireMux_T_185 connect _out_rofireMux_WIRE[46], _out_rofireMux_T_189 connect _out_rofireMux_WIRE[47], _out_rofireMux_T_193 connect _out_rofireMux_WIRE[48], _out_rofireMux_T_197 connect _out_rofireMux_WIRE[49], _out_rofireMux_T_201 connect _out_rofireMux_WIRE[50], _out_rofireMux_T_205 connect _out_rofireMux_WIRE[51], _out_rofireMux_T_209 connect _out_rofireMux_WIRE[52], _out_rofireMux_T_213 connect _out_rofireMux_WIRE[53], _out_rofireMux_T_217 connect _out_rofireMux_WIRE[54], _out_rofireMux_T_221 connect _out_rofireMux_WIRE[55], _out_rofireMux_T_225 connect _out_rofireMux_WIRE[56], _out_rofireMux_T_229 connect _out_rofireMux_WIRE[57], _out_rofireMux_T_233 connect _out_rofireMux_WIRE[58], _out_rofireMux_T_237 connect _out_rofireMux_WIRE[59], _out_rofireMux_T_241 connect _out_rofireMux_WIRE[60], _out_rofireMux_T_245 connect _out_rofireMux_WIRE[61], _out_rofireMux_T_249 connect _out_rofireMux_WIRE[62], _out_rofireMux_T_253 connect _out_rofireMux_WIRE[63], _out_rofireMux_T_257 connect _out_rofireMux_WIRE[64], _out_rofireMux_T_261 connect _out_rofireMux_WIRE[65], _out_rofireMux_T_265 connect _out_rofireMux_WIRE[66], _out_rofireMux_T_269 connect _out_rofireMux_WIRE[67], _out_rofireMux_T_273 connect _out_rofireMux_WIRE[68], _out_rofireMux_T_277 connect _out_rofireMux_WIRE[69], _out_rofireMux_T_281 connect _out_rofireMux_WIRE[70], _out_rofireMux_T_285 connect _out_rofireMux_WIRE[71], _out_rofireMux_T_289 connect _out_rofireMux_WIRE[72], _out_rofireMux_T_293 connect _out_rofireMux_WIRE[73], _out_rofireMux_T_297 connect _out_rofireMux_WIRE[74], _out_rofireMux_T_301 connect _out_rofireMux_WIRE[75], _out_rofireMux_T_305 connect _out_rofireMux_WIRE[76], _out_rofireMux_T_309 connect _out_rofireMux_WIRE[77], _out_rofireMux_T_313 connect _out_rofireMux_WIRE[78], _out_rofireMux_T_317 connect _out_rofireMux_WIRE[79], _out_rofireMux_T_321 connect _out_rofireMux_WIRE[80], _out_rofireMux_T_325 connect _out_rofireMux_WIRE[81], _out_rofireMux_T_329 connect _out_rofireMux_WIRE[82], _out_rofireMux_T_333 connect _out_rofireMux_WIRE[83], _out_rofireMux_T_337 connect _out_rofireMux_WIRE[84], _out_rofireMux_T_341 connect _out_rofireMux_WIRE[85], _out_rofireMux_T_345 connect _out_rofireMux_WIRE[86], _out_rofireMux_T_349 connect _out_rofireMux_WIRE[87], _out_rofireMux_T_353 connect _out_rofireMux_WIRE[88], _out_rofireMux_T_357 connect _out_rofireMux_WIRE[89], _out_rofireMux_T_361 connect _out_rofireMux_WIRE[90], _out_rofireMux_T_365 connect _out_rofireMux_WIRE[91], _out_rofireMux_T_369 connect _out_rofireMux_WIRE[92], _out_rofireMux_T_373 connect _out_rofireMux_WIRE[93], _out_rofireMux_T_377 connect _out_rofireMux_WIRE[94], _out_rofireMux_T_381 connect _out_rofireMux_WIRE[95], _out_rofireMux_T_385 connect _out_rofireMux_WIRE[96], _out_rofireMux_T_389 connect _out_rofireMux_WIRE[97], _out_rofireMux_T_393 connect _out_rofireMux_WIRE[98], _out_rofireMux_T_397 connect _out_rofireMux_WIRE[99], _out_rofireMux_T_401 connect _out_rofireMux_WIRE[100], _out_rofireMux_T_405 connect _out_rofireMux_WIRE[101], _out_rofireMux_T_409 connect _out_rofireMux_WIRE[102], _out_rofireMux_T_413 connect _out_rofireMux_WIRE[103], _out_rofireMux_T_417 connect _out_rofireMux_WIRE[104], _out_rofireMux_T_421 connect _out_rofireMux_WIRE[105], _out_rofireMux_T_425 connect _out_rofireMux_WIRE[106], _out_rofireMux_T_429 connect _out_rofireMux_WIRE[107], _out_rofireMux_T_433 connect _out_rofireMux_WIRE[108], _out_rofireMux_T_437 connect _out_rofireMux_WIRE[109], _out_rofireMux_T_441 connect _out_rofireMux_WIRE[110], _out_rofireMux_T_445 connect _out_rofireMux_WIRE[111], _out_rofireMux_T_449 connect _out_rofireMux_WIRE[112], _out_rofireMux_T_453 connect _out_rofireMux_WIRE[113], _out_rofireMux_T_457 connect _out_rofireMux_WIRE[114], _out_rofireMux_T_461 connect _out_rofireMux_WIRE[115], _out_rofireMux_T_465 connect _out_rofireMux_WIRE[116], _out_rofireMux_T_469 connect _out_rofireMux_WIRE[117], _out_rofireMux_T_473 connect _out_rofireMux_WIRE[118], _out_rofireMux_T_477 connect _out_rofireMux_WIRE[119], _out_rofireMux_T_481 connect _out_rofireMux_WIRE[120], _out_rofireMux_T_485 connect _out_rofireMux_WIRE[121], _out_rofireMux_T_489 connect _out_rofireMux_WIRE[122], _out_rofireMux_T_493 connect _out_rofireMux_WIRE[123], _out_rofireMux_T_497 connect _out_rofireMux_WIRE[124], _out_rofireMux_T_501 connect _out_rofireMux_WIRE[125], _out_rofireMux_T_505 connect _out_rofireMux_WIRE[126], _out_rofireMux_T_509 connect _out_rofireMux_WIRE[127], _out_rofireMux_T_513 node out_rofireMux = mux(_out_rofireMux_T_514, UInt<1>(0h1), _out_rofireMux_WIRE[out_oindex]) node _out_wofireMux_T = and(out_back_front_q.io.deq.valid, out.ready) node _out_wofireMux_T_1 = eq(out_back_front_q.io.deq.bits.read, UInt<1>(0h0)) node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) wire out_wofireMux_out : UInt<1> node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_27) connect out_wofireMux_out, UInt<1>(0h1) connect out_woready[34], _out_wofireMux_T_4 node _out_wofireMux_T_5 = eq(_out_T_27, UInt<1>(0h0)) node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) wire out_wofireMux_out_1 : UInt<1> node _out_wofireMux_T_7 = and(_out_wofireMux_T_2, out_backSel_1) node _out_wofireMux_T_8 = and(_out_wofireMux_T_7, UInt<1>(0h1)) connect out_wofireMux_out_1, UInt<1>(0h1) node _out_wofireMux_T_9 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_10 = or(out_wofireMux_out_1, _out_wofireMux_T_9) wire out_wofireMux_out_2 : UInt<1> node _out_wofireMux_T_11 = and(_out_wofireMux_T_2, out_backSel_2) node _out_wofireMux_T_12 = and(_out_wofireMux_T_11, UInt<1>(0h1)) connect out_wofireMux_out_2, UInt<1>(0h1) node _out_wofireMux_T_13 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_14 = or(out_wofireMux_out_2, _out_wofireMux_T_13) wire out_wofireMux_out_3 : UInt<1> node _out_wofireMux_T_15 = and(_out_wofireMux_T_2, out_backSel_3) node _out_wofireMux_T_16 = and(_out_wofireMux_T_15, UInt<1>(0h1)) connect out_wofireMux_out_3, UInt<1>(0h1) node _out_wofireMux_T_17 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_18 = or(out_wofireMux_out_3, _out_wofireMux_T_17) wire out_wofireMux_out_4 : UInt<1> node _out_wofireMux_T_19 = and(_out_wofireMux_T_2, out_backSel_4) node _out_wofireMux_T_20 = and(_out_wofireMux_T_19, UInt<1>(0h1)) connect out_wofireMux_out_4, UInt<1>(0h1) node _out_wofireMux_T_21 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_22 = or(out_wofireMux_out_4, _out_wofireMux_T_21) wire out_wofireMux_out_5 : UInt<1> node _out_wofireMux_T_23 = and(_out_wofireMux_T_2, out_backSel_5) node _out_wofireMux_T_24 = and(_out_wofireMux_T_23, UInt<1>(0h1)) connect out_wofireMux_out_5, UInt<1>(0h1) node _out_wofireMux_T_25 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_26 = or(out_wofireMux_out_5, _out_wofireMux_T_25) wire out_wofireMux_out_6 : UInt<1> node _out_wofireMux_T_27 = and(_out_wofireMux_T_2, out_backSel_6) node _out_wofireMux_T_28 = and(_out_wofireMux_T_27, UInt<1>(0h1)) connect out_wofireMux_out_6, UInt<1>(0h1) node _out_wofireMux_T_29 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_30 = or(out_wofireMux_out_6, _out_wofireMux_T_29) wire out_wofireMux_out_7 : UInt<1> node _out_wofireMux_T_31 = and(_out_wofireMux_T_2, out_backSel_7) node _out_wofireMux_T_32 = and(_out_wofireMux_T_31, UInt<1>(0h1)) connect out_wofireMux_out_7, UInt<1>(0h1) node _out_wofireMux_T_33 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_34 = or(out_wofireMux_out_7, _out_wofireMux_T_33) wire out_wofireMux_out_8 : UInt<1> node _out_wofireMux_T_35 = and(_out_wofireMux_T_2, out_backSel_8) node _out_wofireMux_T_36 = and(_out_wofireMux_T_35, _out_T_3) connect out_wofireMux_out_8, UInt<1>(0h1) connect out_woready[4], _out_wofireMux_T_36 connect out_woready[3], _out_wofireMux_T_36 node _out_wofireMux_T_37 = eq(_out_T_3, UInt<1>(0h0)) node _out_wofireMux_T_38 = or(out_wofireMux_out_8, _out_wofireMux_T_37) wire out_wofireMux_out_9 : UInt<1> node _out_wofireMux_T_39 = and(_out_wofireMux_T_2, out_backSel_9) node _out_wofireMux_T_40 = and(_out_wofireMux_T_39, UInt<1>(0h1)) connect out_wofireMux_out_9, UInt<1>(0h1) node _out_wofireMux_T_41 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_42 = or(out_wofireMux_out_9, _out_wofireMux_T_41) wire out_wofireMux_out_10 : UInt<1> node _out_wofireMux_T_43 = and(_out_wofireMux_T_2, out_backSel_10) node _out_wofireMux_T_44 = and(_out_wofireMux_T_43, UInt<1>(0h1)) connect out_wofireMux_out_10, UInt<1>(0h1) node _out_wofireMux_T_45 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_46 = or(out_wofireMux_out_10, _out_wofireMux_T_45) wire out_wofireMux_out_11 : UInt<1> node _out_wofireMux_T_47 = and(_out_wofireMux_T_2, out_backSel_11) node _out_wofireMux_T_48 = and(_out_wofireMux_T_47, UInt<1>(0h1)) connect out_wofireMux_out_11, UInt<1>(0h1) node _out_wofireMux_T_49 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_50 = or(out_wofireMux_out_11, _out_wofireMux_T_49) wire out_wofireMux_out_12 : UInt<1> node _out_wofireMux_T_51 = and(_out_wofireMux_T_2, out_backSel_12) node _out_wofireMux_T_52 = and(_out_wofireMux_T_51, UInt<1>(0h1)) connect out_wofireMux_out_12, UInt<1>(0h1) node _out_wofireMux_T_53 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_54 = or(out_wofireMux_out_12, _out_wofireMux_T_53) wire out_wofireMux_out_13 : UInt<1> node _out_wofireMux_T_55 = and(_out_wofireMux_T_2, out_backSel_13) node _out_wofireMux_T_56 = and(_out_wofireMux_T_55, UInt<1>(0h1)) connect out_wofireMux_out_13, UInt<1>(0h1) node _out_wofireMux_T_57 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_58 = or(out_wofireMux_out_13, _out_wofireMux_T_57) wire out_wofireMux_out_14 : UInt<1> node _out_wofireMux_T_59 = and(_out_wofireMux_T_2, out_backSel_14) node _out_wofireMux_T_60 = and(_out_wofireMux_T_59, UInt<1>(0h1)) connect out_wofireMux_out_14, UInt<1>(0h1) node _out_wofireMux_T_61 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_62 = or(out_wofireMux_out_14, _out_wofireMux_T_61) wire out_wofireMux_out_15 : UInt<1> node _out_wofireMux_T_63 = and(_out_wofireMux_T_2, out_backSel_15) node _out_wofireMux_T_64 = and(_out_wofireMux_T_63, UInt<1>(0h1)) connect out_wofireMux_out_15, UInt<1>(0h1) node _out_wofireMux_T_65 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_66 = or(out_wofireMux_out_15, _out_wofireMux_T_65) wire out_wofireMux_out_16 : UInt<1> node _out_wofireMux_T_67 = and(_out_wofireMux_T_2, out_backSel_16) node _out_wofireMux_T_68 = and(_out_wofireMux_T_67, _out_T_25) connect out_wofireMux_out_16, UInt<1>(0h1) connect out_woready[33], _out_wofireMux_T_68 connect out_woready[32], _out_wofireMux_T_68 node _out_wofireMux_T_69 = eq(_out_T_25, UInt<1>(0h0)) node _out_wofireMux_T_70 = or(out_wofireMux_out_16, _out_wofireMux_T_69) wire out_wofireMux_out_17 : UInt<1> node _out_wofireMux_T_71 = and(_out_wofireMux_T_2, out_backSel_17) node _out_wofireMux_T_72 = and(_out_wofireMux_T_71, _out_T_29) connect out_wofireMux_out_17, UInt<1>(0h1) connect out_woready[36], _out_wofireMux_T_72 connect out_woready[35], _out_wofireMux_T_72 node _out_wofireMux_T_73 = eq(_out_T_29, UInt<1>(0h0)) node _out_wofireMux_T_74 = or(out_wofireMux_out_17, _out_wofireMux_T_73) wire out_wofireMux_out_18 : UInt<1> node _out_wofireMux_T_75 = and(_out_wofireMux_T_2, out_backSel_18) node _out_wofireMux_T_76 = and(_out_wofireMux_T_75, _out_T_19) connect out_wofireMux_out_18, UInt<1>(0h1) connect out_woready[27], _out_wofireMux_T_76 connect out_woready[26], _out_wofireMux_T_76 node _out_wofireMux_T_77 = eq(_out_T_19, UInt<1>(0h0)) node _out_wofireMux_T_78 = or(out_wofireMux_out_18, _out_wofireMux_T_77) wire out_wofireMux_out_19 : UInt<1> node _out_wofireMux_T_79 = and(_out_wofireMux_T_2, out_backSel_19) node _out_wofireMux_T_80 = and(_out_wofireMux_T_79, _out_T_33) connect out_wofireMux_out_19, UInt<1>(0h1) connect out_woready[40], _out_wofireMux_T_80 connect out_woready[39], _out_wofireMux_T_80 node _out_wofireMux_T_81 = eq(_out_T_33, UInt<1>(0h0)) node _out_wofireMux_T_82 = or(out_wofireMux_out_19, _out_wofireMux_T_81) wire out_wofireMux_out_20 : UInt<1> node _out_wofireMux_T_83 = and(_out_wofireMux_T_2, out_backSel_20) node _out_wofireMux_T_84 = and(_out_wofireMux_T_83, _out_T_23) connect out_wofireMux_out_20, UInt<1>(0h1) connect out_woready[31], _out_wofireMux_T_84 connect out_woready[30], _out_wofireMux_T_84 node _out_wofireMux_T_85 = eq(_out_T_23, UInt<1>(0h0)) node _out_wofireMux_T_86 = or(out_wofireMux_out_20, _out_wofireMux_T_85) wire out_wofireMux_out_21 : UInt<1> node _out_wofireMux_T_87 = and(_out_wofireMux_T_2, out_backSel_21) node _out_wofireMux_T_88 = and(_out_wofireMux_T_87, _out_T_35) connect out_wofireMux_out_21, UInt<1>(0h1) connect out_woready[42], _out_wofireMux_T_88 connect out_woready[41], _out_wofireMux_T_88 node _out_wofireMux_T_89 = eq(_out_T_35, UInt<1>(0h0)) node _out_wofireMux_T_90 = or(out_wofireMux_out_21, _out_wofireMux_T_89) wire out_wofireMux_out_22 : UInt<1> node _out_wofireMux_T_91 = and(_out_wofireMux_T_2, out_backSel_22) node _out_wofireMux_T_92 = and(_out_wofireMux_T_91, _out_T_21) connect out_wofireMux_out_22, UInt<1>(0h1) connect out_woready[29], _out_wofireMux_T_92 connect out_woready[28], _out_wofireMux_T_92 node _out_wofireMux_T_93 = eq(_out_T_21, UInt<1>(0h0)) node _out_wofireMux_T_94 = or(out_wofireMux_out_22, _out_wofireMux_T_93) wire out_wofireMux_out_23 : UInt<1> node _out_wofireMux_T_95 = and(_out_wofireMux_T_2, out_backSel_23) node _out_wofireMux_T_96 = and(_out_wofireMux_T_95, _out_T_31) connect out_wofireMux_out_23, UInt<1>(0h1) connect out_woready[38], _out_wofireMux_T_96 connect out_woready[37], _out_wofireMux_T_96 node _out_wofireMux_T_97 = eq(_out_T_31, UInt<1>(0h0)) node _out_wofireMux_T_98 = or(out_wofireMux_out_23, _out_wofireMux_T_97) wire out_wofireMux_out_24 : UInt<1> node _out_wofireMux_T_99 = and(_out_wofireMux_T_2, out_backSel_24) node _out_wofireMux_T_100 = and(_out_wofireMux_T_99, UInt<1>(0h1)) connect out_wofireMux_out_24, UInt<1>(0h1) node _out_wofireMux_T_101 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_102 = or(out_wofireMux_out_24, _out_wofireMux_T_101) wire out_wofireMux_out_25 : UInt<1> node _out_wofireMux_T_103 = and(_out_wofireMux_T_2, out_backSel_25) node _out_wofireMux_T_104 = and(_out_wofireMux_T_103, UInt<1>(0h1)) connect out_wofireMux_out_25, UInt<1>(0h1) node _out_wofireMux_T_105 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_106 = or(out_wofireMux_out_25, _out_wofireMux_T_105) wire out_wofireMux_out_26 : UInt<1> node _out_wofireMux_T_107 = and(_out_wofireMux_T_2, out_backSel_26) node _out_wofireMux_T_108 = and(_out_wofireMux_T_107, UInt<1>(0h1)) connect out_wofireMux_out_26, UInt<1>(0h1) node _out_wofireMux_T_109 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_110 = or(out_wofireMux_out_26, _out_wofireMux_T_109) wire out_wofireMux_out_27 : UInt<1> node _out_wofireMux_T_111 = and(_out_wofireMux_T_2, out_backSel_27) node _out_wofireMux_T_112 = and(_out_wofireMux_T_111, UInt<1>(0h1)) connect out_wofireMux_out_27, UInt<1>(0h1) node _out_wofireMux_T_113 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_114 = or(out_wofireMux_out_27, _out_wofireMux_T_113) wire out_wofireMux_out_28 : UInt<1> node _out_wofireMux_T_115 = and(_out_wofireMux_T_2, out_backSel_28) node _out_wofireMux_T_116 = and(_out_wofireMux_T_115, UInt<1>(0h1)) connect out_wofireMux_out_28, UInt<1>(0h1) node _out_wofireMux_T_117 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_118 = or(out_wofireMux_out_28, _out_wofireMux_T_117) wire out_wofireMux_out_29 : UInt<1> node _out_wofireMux_T_119 = and(_out_wofireMux_T_2, out_backSel_29) node _out_wofireMux_T_120 = and(_out_wofireMux_T_119, UInt<1>(0h1)) connect out_wofireMux_out_29, UInt<1>(0h1) node _out_wofireMux_T_121 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_122 = or(out_wofireMux_out_29, _out_wofireMux_T_121) wire out_wofireMux_out_30 : UInt<1> node _out_wofireMux_T_123 = and(_out_wofireMux_T_2, out_backSel_30) node _out_wofireMux_T_124 = and(_out_wofireMux_T_123, UInt<1>(0h1)) connect out_wofireMux_out_30, UInt<1>(0h1) node _out_wofireMux_T_125 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_126 = or(out_wofireMux_out_30, _out_wofireMux_T_125) wire out_wofireMux_out_31 : UInt<1> node _out_wofireMux_T_127 = and(_out_wofireMux_T_2, out_backSel_31) node _out_wofireMux_T_128 = and(_out_wofireMux_T_127, UInt<1>(0h1)) connect out_wofireMux_out_31, UInt<1>(0h1) node _out_wofireMux_T_129 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_130 = or(out_wofireMux_out_31, _out_wofireMux_T_129) wire out_wofireMux_out_32 : UInt<1> node _out_wofireMux_T_131 = and(_out_wofireMux_T_2, out_backSel_32) node _out_wofireMux_T_132 = and(_out_wofireMux_T_131, UInt<1>(0h1)) connect out_wofireMux_out_32, UInt<1>(0h1) node _out_wofireMux_T_133 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_134 = or(out_wofireMux_out_32, _out_wofireMux_T_133) wire out_wofireMux_out_33 : UInt<1> node _out_wofireMux_T_135 = and(_out_wofireMux_T_2, out_backSel_33) node _out_wofireMux_T_136 = and(_out_wofireMux_T_135, UInt<1>(0h1)) connect out_wofireMux_out_33, UInt<1>(0h1) node _out_wofireMux_T_137 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_138 = or(out_wofireMux_out_33, _out_wofireMux_T_137) wire out_wofireMux_out_34 : UInt<1> node _out_wofireMux_T_139 = and(_out_wofireMux_T_2, out_backSel_34) node _out_wofireMux_T_140 = and(_out_wofireMux_T_139, UInt<1>(0h1)) connect out_wofireMux_out_34, UInt<1>(0h1) node _out_wofireMux_T_141 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_142 = or(out_wofireMux_out_34, _out_wofireMux_T_141) wire out_wofireMux_out_35 : UInt<1> node _out_wofireMux_T_143 = and(_out_wofireMux_T_2, out_backSel_35) node _out_wofireMux_T_144 = and(_out_wofireMux_T_143, UInt<1>(0h1)) connect out_wofireMux_out_35, UInt<1>(0h1) node _out_wofireMux_T_145 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_146 = or(out_wofireMux_out_35, _out_wofireMux_T_145) wire out_wofireMux_out_36 : UInt<1> node _out_wofireMux_T_147 = and(_out_wofireMux_T_2, out_backSel_36) node _out_wofireMux_T_148 = and(_out_wofireMux_T_147, UInt<1>(0h1)) connect out_wofireMux_out_36, UInt<1>(0h1) node _out_wofireMux_T_149 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_150 = or(out_wofireMux_out_36, _out_wofireMux_T_149) wire out_wofireMux_out_37 : UInt<1> node _out_wofireMux_T_151 = and(_out_wofireMux_T_2, out_backSel_37) node _out_wofireMux_T_152 = and(_out_wofireMux_T_151, UInt<1>(0h1)) connect out_wofireMux_out_37, UInt<1>(0h1) node _out_wofireMux_T_153 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_154 = or(out_wofireMux_out_37, _out_wofireMux_T_153) wire out_wofireMux_out_38 : UInt<1> node _out_wofireMux_T_155 = and(_out_wofireMux_T_2, out_backSel_38) node _out_wofireMux_T_156 = and(_out_wofireMux_T_155, UInt<1>(0h1)) connect out_wofireMux_out_38, UInt<1>(0h1) node _out_wofireMux_T_157 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_158 = or(out_wofireMux_out_38, _out_wofireMux_T_157) wire out_wofireMux_out_39 : UInt<1> node _out_wofireMux_T_159 = and(_out_wofireMux_T_2, out_backSel_39) node _out_wofireMux_T_160 = and(_out_wofireMux_T_159, UInt<1>(0h1)) connect out_wofireMux_out_39, UInt<1>(0h1) node _out_wofireMux_T_161 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_162 = or(out_wofireMux_out_39, _out_wofireMux_T_161) wire out_wofireMux_out_40 : UInt<1> node _out_wofireMux_T_163 = and(_out_wofireMux_T_2, out_backSel_40) node _out_wofireMux_T_164 = and(_out_wofireMux_T_163, UInt<1>(0h1)) connect out_wofireMux_out_40, UInt<1>(0h1) node _out_wofireMux_T_165 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_166 = or(out_wofireMux_out_40, _out_wofireMux_T_165) wire out_wofireMux_out_41 : UInt<1> node _out_wofireMux_T_167 = and(_out_wofireMux_T_2, out_backSel_41) node _out_wofireMux_T_168 = and(_out_wofireMux_T_167, UInt<1>(0h1)) connect out_wofireMux_out_41, UInt<1>(0h1) node _out_wofireMux_T_169 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_170 = or(out_wofireMux_out_41, _out_wofireMux_T_169) wire out_wofireMux_out_42 : UInt<1> node _out_wofireMux_T_171 = and(_out_wofireMux_T_2, out_backSel_42) node _out_wofireMux_T_172 = and(_out_wofireMux_T_171, UInt<1>(0h1)) connect out_wofireMux_out_42, UInt<1>(0h1) node _out_wofireMux_T_173 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_174 = or(out_wofireMux_out_42, _out_wofireMux_T_173) wire out_wofireMux_out_43 : UInt<1> node _out_wofireMux_T_175 = and(_out_wofireMux_T_2, out_backSel_43) node _out_wofireMux_T_176 = and(_out_wofireMux_T_175, UInt<1>(0h1)) connect out_wofireMux_out_43, UInt<1>(0h1) node _out_wofireMux_T_177 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_178 = or(out_wofireMux_out_43, _out_wofireMux_T_177) wire out_wofireMux_out_44 : UInt<1> node _out_wofireMux_T_179 = and(_out_wofireMux_T_2, out_backSel_44) node _out_wofireMux_T_180 = and(_out_wofireMux_T_179, UInt<1>(0h1)) connect out_wofireMux_out_44, UInt<1>(0h1) node _out_wofireMux_T_181 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_182 = or(out_wofireMux_out_44, _out_wofireMux_T_181) wire out_wofireMux_out_45 : UInt<1> node _out_wofireMux_T_183 = and(_out_wofireMux_T_2, out_backSel_45) node _out_wofireMux_T_184 = and(_out_wofireMux_T_183, UInt<1>(0h1)) connect out_wofireMux_out_45, UInt<1>(0h1) node _out_wofireMux_T_185 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_186 = or(out_wofireMux_out_45, _out_wofireMux_T_185) wire out_wofireMux_out_46 : UInt<1> node _out_wofireMux_T_187 = and(_out_wofireMux_T_2, out_backSel_46) node _out_wofireMux_T_188 = and(_out_wofireMux_T_187, UInt<1>(0h1)) connect out_wofireMux_out_46, UInt<1>(0h1) node _out_wofireMux_T_189 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_190 = or(out_wofireMux_out_46, _out_wofireMux_T_189) wire out_wofireMux_out_47 : UInt<1> node _out_wofireMux_T_191 = and(_out_wofireMux_T_2, out_backSel_47) node _out_wofireMux_T_192 = and(_out_wofireMux_T_191, UInt<1>(0h1)) connect out_wofireMux_out_47, UInt<1>(0h1) node _out_wofireMux_T_193 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_194 = or(out_wofireMux_out_47, _out_wofireMux_T_193) wire out_wofireMux_out_48 : UInt<1> node _out_wofireMux_T_195 = and(_out_wofireMux_T_2, out_backSel_48) node _out_wofireMux_T_196 = and(_out_wofireMux_T_195, UInt<1>(0h1)) connect out_wofireMux_out_48, UInt<1>(0h1) node _out_wofireMux_T_197 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_198 = or(out_wofireMux_out_48, _out_wofireMux_T_197) wire out_wofireMux_out_49 : UInt<1> node _out_wofireMux_T_199 = and(_out_wofireMux_T_2, out_backSel_49) node _out_wofireMux_T_200 = and(_out_wofireMux_T_199, UInt<1>(0h1)) connect out_wofireMux_out_49, UInt<1>(0h1) node _out_wofireMux_T_201 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_202 = or(out_wofireMux_out_49, _out_wofireMux_T_201) wire out_wofireMux_out_50 : UInt<1> node _out_wofireMux_T_203 = and(_out_wofireMux_T_2, out_backSel_50) node _out_wofireMux_T_204 = and(_out_wofireMux_T_203, UInt<1>(0h1)) connect out_wofireMux_out_50, UInt<1>(0h1) node _out_wofireMux_T_205 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_206 = or(out_wofireMux_out_50, _out_wofireMux_T_205) wire out_wofireMux_out_51 : UInt<1> node _out_wofireMux_T_207 = and(_out_wofireMux_T_2, out_backSel_51) node _out_wofireMux_T_208 = and(_out_wofireMux_T_207, UInt<1>(0h1)) connect out_wofireMux_out_51, UInt<1>(0h1) node _out_wofireMux_T_209 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_210 = or(out_wofireMux_out_51, _out_wofireMux_T_209) wire out_wofireMux_out_52 : UInt<1> node _out_wofireMux_T_211 = and(_out_wofireMux_T_2, out_backSel_52) node _out_wofireMux_T_212 = and(_out_wofireMux_T_211, UInt<1>(0h1)) connect out_wofireMux_out_52, UInt<1>(0h1) node _out_wofireMux_T_213 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_214 = or(out_wofireMux_out_52, _out_wofireMux_T_213) wire out_wofireMux_out_53 : UInt<1> node _out_wofireMux_T_215 = and(_out_wofireMux_T_2, out_backSel_53) node _out_wofireMux_T_216 = and(_out_wofireMux_T_215, UInt<1>(0h1)) connect out_wofireMux_out_53, UInt<1>(0h1) node _out_wofireMux_T_217 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_218 = or(out_wofireMux_out_53, _out_wofireMux_T_217) wire out_wofireMux_out_54 : UInt<1> node _out_wofireMux_T_219 = and(_out_wofireMux_T_2, out_backSel_54) node _out_wofireMux_T_220 = and(_out_wofireMux_T_219, UInt<1>(0h1)) connect out_wofireMux_out_54, UInt<1>(0h1) node _out_wofireMux_T_221 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_222 = or(out_wofireMux_out_54, _out_wofireMux_T_221) wire out_wofireMux_out_55 : UInt<1> node _out_wofireMux_T_223 = and(_out_wofireMux_T_2, out_backSel_55) node _out_wofireMux_T_224 = and(_out_wofireMux_T_223, UInt<1>(0h1)) connect out_wofireMux_out_55, UInt<1>(0h1) node _out_wofireMux_T_225 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_226 = or(out_wofireMux_out_55, _out_wofireMux_T_225) wire out_wofireMux_out_56 : UInt<1> node _out_wofireMux_T_227 = and(_out_wofireMux_T_2, out_backSel_56) node _out_wofireMux_T_228 = and(_out_wofireMux_T_227, UInt<1>(0h1)) connect out_wofireMux_out_56, UInt<1>(0h1) node _out_wofireMux_T_229 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_230 = or(out_wofireMux_out_56, _out_wofireMux_T_229) wire out_wofireMux_out_57 : UInt<1> node _out_wofireMux_T_231 = and(_out_wofireMux_T_2, out_backSel_57) node _out_wofireMux_T_232 = and(_out_wofireMux_T_231, UInt<1>(0h1)) connect out_wofireMux_out_57, UInt<1>(0h1) node _out_wofireMux_T_233 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_234 = or(out_wofireMux_out_57, _out_wofireMux_T_233) wire out_wofireMux_out_58 : UInt<1> node _out_wofireMux_T_235 = and(_out_wofireMux_T_2, out_backSel_58) node _out_wofireMux_T_236 = and(_out_wofireMux_T_235, UInt<1>(0h1)) connect out_wofireMux_out_58, UInt<1>(0h1) node _out_wofireMux_T_237 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_238 = or(out_wofireMux_out_58, _out_wofireMux_T_237) wire out_wofireMux_out_59 : UInt<1> node _out_wofireMux_T_239 = and(_out_wofireMux_T_2, out_backSel_59) node _out_wofireMux_T_240 = and(_out_wofireMux_T_239, UInt<1>(0h1)) connect out_wofireMux_out_59, UInt<1>(0h1) node _out_wofireMux_T_241 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_242 = or(out_wofireMux_out_59, _out_wofireMux_T_241) wire out_wofireMux_out_60 : UInt<1> node _out_wofireMux_T_243 = and(_out_wofireMux_T_2, out_backSel_60) node _out_wofireMux_T_244 = and(_out_wofireMux_T_243, UInt<1>(0h1)) connect out_wofireMux_out_60, UInt<1>(0h1) node _out_wofireMux_T_245 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_246 = or(out_wofireMux_out_60, _out_wofireMux_T_245) wire out_wofireMux_out_61 : UInt<1> node _out_wofireMux_T_247 = and(_out_wofireMux_T_2, out_backSel_61) node _out_wofireMux_T_248 = and(_out_wofireMux_T_247, UInt<1>(0h1)) connect out_wofireMux_out_61, UInt<1>(0h1) node _out_wofireMux_T_249 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_250 = or(out_wofireMux_out_61, _out_wofireMux_T_249) wire out_wofireMux_out_62 : UInt<1> node _out_wofireMux_T_251 = and(_out_wofireMux_T_2, out_backSel_62) node _out_wofireMux_T_252 = and(_out_wofireMux_T_251, UInt<1>(0h1)) connect out_wofireMux_out_62, UInt<1>(0h1) node _out_wofireMux_T_253 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_254 = or(out_wofireMux_out_62, _out_wofireMux_T_253) wire out_wofireMux_out_63 : UInt<1> node _out_wofireMux_T_255 = and(_out_wofireMux_T_2, out_backSel_63) node _out_wofireMux_T_256 = and(_out_wofireMux_T_255, UInt<1>(0h1)) connect out_wofireMux_out_63, UInt<1>(0h1) node _out_wofireMux_T_257 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_258 = or(out_wofireMux_out_63, _out_wofireMux_T_257) wire out_wofireMux_out_64 : UInt<1> node _out_wofireMux_T_259 = and(_out_wofireMux_T_2, out_backSel_64) node _out_wofireMux_T_260 = and(_out_wofireMux_T_259, _out_T_13) connect out_wofireMux_out_64, UInt<1>(0h1) connect out_woready[19], _out_wofireMux_T_260 connect out_woready[18], _out_wofireMux_T_260 connect out_woready[17], _out_wofireMux_T_260 node _out_wofireMux_T_261 = eq(_out_T_13, UInt<1>(0h0)) node _out_wofireMux_T_262 = or(out_wofireMux_out_64, _out_wofireMux_T_261) wire out_wofireMux_out_65 : UInt<1> node _out_wofireMux_T_263 = and(_out_wofireMux_T_2, out_backSel_65) node _out_wofireMux_T_264 = and(_out_wofireMux_T_263, UInt<1>(0h1)) connect out_wofireMux_out_65, UInt<1>(0h1) node _out_wofireMux_T_265 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_266 = or(out_wofireMux_out_65, _out_wofireMux_T_265) wire out_wofireMux_out_66 : UInt<1> node _out_wofireMux_T_267 = and(_out_wofireMux_T_2, out_backSel_66) node _out_wofireMux_T_268 = and(_out_wofireMux_T_267, UInt<1>(0h1)) connect out_wofireMux_out_66, UInt<1>(0h1) node _out_wofireMux_T_269 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_270 = or(out_wofireMux_out_66, _out_wofireMux_T_269) wire out_wofireMux_out_67 : UInt<1> node _out_wofireMux_T_271 = and(_out_wofireMux_T_2, out_backSel_67) node _out_wofireMux_T_272 = and(_out_wofireMux_T_271, UInt<1>(0h1)) connect out_wofireMux_out_67, UInt<1>(0h1) node _out_wofireMux_T_273 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_274 = or(out_wofireMux_out_67, _out_wofireMux_T_273) wire out_wofireMux_out_68 : UInt<1> node _out_wofireMux_T_275 = and(_out_wofireMux_T_2, out_backSel_68) node _out_wofireMux_T_276 = and(_out_wofireMux_T_275, UInt<1>(0h1)) connect out_wofireMux_out_68, UInt<1>(0h1) node _out_wofireMux_T_277 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_278 = or(out_wofireMux_out_68, _out_wofireMux_T_277) wire out_wofireMux_out_69 : UInt<1> node _out_wofireMux_T_279 = and(_out_wofireMux_T_2, out_backSel_69) node _out_wofireMux_T_280 = and(_out_wofireMux_T_279, UInt<1>(0h1)) connect out_wofireMux_out_69, UInt<1>(0h1) node _out_wofireMux_T_281 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_282 = or(out_wofireMux_out_69, _out_wofireMux_T_281) wire out_wofireMux_out_70 : UInt<1> node _out_wofireMux_T_283 = and(_out_wofireMux_T_2, out_backSel_70) node _out_wofireMux_T_284 = and(_out_wofireMux_T_283, UInt<1>(0h1)) connect out_wofireMux_out_70, UInt<1>(0h1) node _out_wofireMux_T_285 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_286 = or(out_wofireMux_out_70, _out_wofireMux_T_285) wire out_wofireMux_out_71 : UInt<1> node _out_wofireMux_T_287 = and(_out_wofireMux_T_2, out_backSel_71) node _out_wofireMux_T_288 = and(_out_wofireMux_T_287, UInt<1>(0h1)) connect out_wofireMux_out_71, UInt<1>(0h1) node _out_wofireMux_T_289 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_290 = or(out_wofireMux_out_71, _out_wofireMux_T_289) wire out_wofireMux_out_72 : UInt<1> node _out_wofireMux_T_291 = and(_out_wofireMux_T_2, out_backSel_72) node _out_wofireMux_T_292 = and(_out_wofireMux_T_291, _out_T_7) connect out_wofireMux_out_72, UInt<1>(0h1) connect out_woready[10], _out_wofireMux_T_292 connect out_woready[9], _out_wofireMux_T_292 connect out_woready[8], _out_wofireMux_T_292 node _out_wofireMux_T_293 = eq(_out_T_7, UInt<1>(0h0)) node _out_wofireMux_T_294 = or(out_wofireMux_out_72, _out_wofireMux_T_293) wire out_wofireMux_out_73 : UInt<1> node _out_wofireMux_T_295 = and(_out_wofireMux_T_2, out_backSel_73) node _out_wofireMux_T_296 = and(_out_wofireMux_T_295, UInt<1>(0h1)) connect out_wofireMux_out_73, UInt<1>(0h1) node _out_wofireMux_T_297 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_298 = or(out_wofireMux_out_73, _out_wofireMux_T_297) wire out_wofireMux_out_74 : UInt<1> node _out_wofireMux_T_299 = and(_out_wofireMux_T_2, out_backSel_74) node _out_wofireMux_T_300 = and(_out_wofireMux_T_299, UInt<1>(0h1)) connect out_wofireMux_out_74, UInt<1>(0h1) node _out_wofireMux_T_301 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_302 = or(out_wofireMux_out_74, _out_wofireMux_T_301) wire out_wofireMux_out_75 : UInt<1> node _out_wofireMux_T_303 = and(_out_wofireMux_T_2, out_backSel_75) node _out_wofireMux_T_304 = and(_out_wofireMux_T_303, UInt<1>(0h1)) connect out_wofireMux_out_75, UInt<1>(0h1) node _out_wofireMux_T_305 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_306 = or(out_wofireMux_out_75, _out_wofireMux_T_305) wire out_wofireMux_out_76 : UInt<1> node _out_wofireMux_T_307 = and(_out_wofireMux_T_2, out_backSel_76) node _out_wofireMux_T_308 = and(_out_wofireMux_T_307, UInt<1>(0h1)) connect out_wofireMux_out_76, UInt<1>(0h1) node _out_wofireMux_T_309 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_310 = or(out_wofireMux_out_76, _out_wofireMux_T_309) wire out_wofireMux_out_77 : UInt<1> node _out_wofireMux_T_311 = and(_out_wofireMux_T_2, out_backSel_77) node _out_wofireMux_T_312 = and(_out_wofireMux_T_311, UInt<1>(0h1)) connect out_wofireMux_out_77, UInt<1>(0h1) node _out_wofireMux_T_313 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_314 = or(out_wofireMux_out_77, _out_wofireMux_T_313) wire out_wofireMux_out_78 : UInt<1> node _out_wofireMux_T_315 = and(_out_wofireMux_T_2, out_backSel_78) node _out_wofireMux_T_316 = and(_out_wofireMux_T_315, UInt<1>(0h1)) connect out_wofireMux_out_78, UInt<1>(0h1) node _out_wofireMux_T_317 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_318 = or(out_wofireMux_out_78, _out_wofireMux_T_317) wire out_wofireMux_out_79 : UInt<1> node _out_wofireMux_T_319 = and(_out_wofireMux_T_2, out_backSel_79) node _out_wofireMux_T_320 = and(_out_wofireMux_T_319, UInt<1>(0h1)) connect out_wofireMux_out_79, UInt<1>(0h1) node _out_wofireMux_T_321 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_322 = or(out_wofireMux_out_79, _out_wofireMux_T_321) wire out_wofireMux_out_80 : UInt<1> node _out_wofireMux_T_323 = and(_out_wofireMux_T_2, out_backSel_80) node _out_wofireMux_T_324 = and(_out_wofireMux_T_323, _out_T_15) connect out_wofireMux_out_80, UInt<1>(0h1) connect out_woready[22], _out_wofireMux_T_324 connect out_woready[21], _out_wofireMux_T_324 connect out_woready[20], _out_wofireMux_T_324 node _out_wofireMux_T_325 = eq(_out_T_15, UInt<1>(0h0)) node _out_wofireMux_T_326 = or(out_wofireMux_out_80, _out_wofireMux_T_325) wire out_wofireMux_out_81 : UInt<1> node _out_wofireMux_T_327 = and(_out_wofireMux_T_2, out_backSel_81) node _out_wofireMux_T_328 = and(_out_wofireMux_T_327, UInt<1>(0h1)) connect out_wofireMux_out_81, UInt<1>(0h1) node _out_wofireMux_T_329 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_330 = or(out_wofireMux_out_81, _out_wofireMux_T_329) wire out_wofireMux_out_82 : UInt<1> node _out_wofireMux_T_331 = and(_out_wofireMux_T_2, out_backSel_82) node _out_wofireMux_T_332 = and(_out_wofireMux_T_331, UInt<1>(0h1)) connect out_wofireMux_out_82, UInt<1>(0h1) node _out_wofireMux_T_333 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_334 = or(out_wofireMux_out_82, _out_wofireMux_T_333) wire out_wofireMux_out_83 : UInt<1> node _out_wofireMux_T_335 = and(_out_wofireMux_T_2, out_backSel_83) node _out_wofireMux_T_336 = and(_out_wofireMux_T_335, UInt<1>(0h1)) connect out_wofireMux_out_83, UInt<1>(0h1) node _out_wofireMux_T_337 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_338 = or(out_wofireMux_out_83, _out_wofireMux_T_337) wire out_wofireMux_out_84 : UInt<1> node _out_wofireMux_T_339 = and(_out_wofireMux_T_2, out_backSel_84) node _out_wofireMux_T_340 = and(_out_wofireMux_T_339, UInt<1>(0h1)) connect out_wofireMux_out_84, UInt<1>(0h1) node _out_wofireMux_T_341 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_342 = or(out_wofireMux_out_84, _out_wofireMux_T_341) wire out_wofireMux_out_85 : UInt<1> node _out_wofireMux_T_343 = and(_out_wofireMux_T_2, out_backSel_85) node _out_wofireMux_T_344 = and(_out_wofireMux_T_343, UInt<1>(0h1)) connect out_wofireMux_out_85, UInt<1>(0h1) node _out_wofireMux_T_345 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_346 = or(out_wofireMux_out_85, _out_wofireMux_T_345) wire out_wofireMux_out_86 : UInt<1> node _out_wofireMux_T_347 = and(_out_wofireMux_T_2, out_backSel_86) node _out_wofireMux_T_348 = and(_out_wofireMux_T_347, UInt<1>(0h1)) connect out_wofireMux_out_86, UInt<1>(0h1) node _out_wofireMux_T_349 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_350 = or(out_wofireMux_out_86, _out_wofireMux_T_349) wire out_wofireMux_out_87 : UInt<1> node _out_wofireMux_T_351 = and(_out_wofireMux_T_2, out_backSel_87) node _out_wofireMux_T_352 = and(_out_wofireMux_T_351, UInt<1>(0h1)) connect out_wofireMux_out_87, UInt<1>(0h1) node _out_wofireMux_T_353 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_354 = or(out_wofireMux_out_87, _out_wofireMux_T_353) wire out_wofireMux_out_88 : UInt<1> node _out_wofireMux_T_355 = and(_out_wofireMux_T_2, out_backSel_88) node _out_wofireMux_T_356 = and(_out_wofireMux_T_355, _out_T_9) connect out_wofireMux_out_88, UInt<1>(0h1) connect out_woready[13], _out_wofireMux_T_356 connect out_woready[12], _out_wofireMux_T_356 connect out_woready[11], _out_wofireMux_T_356 node _out_wofireMux_T_357 = eq(_out_T_9, UInt<1>(0h0)) node _out_wofireMux_T_358 = or(out_wofireMux_out_88, _out_wofireMux_T_357) wire out_wofireMux_out_89 : UInt<1> node _out_wofireMux_T_359 = and(_out_wofireMux_T_2, out_backSel_89) node _out_wofireMux_T_360 = and(_out_wofireMux_T_359, UInt<1>(0h1)) connect out_wofireMux_out_89, UInt<1>(0h1) node _out_wofireMux_T_361 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_362 = or(out_wofireMux_out_89, _out_wofireMux_T_361) wire out_wofireMux_out_90 : UInt<1> node _out_wofireMux_T_363 = and(_out_wofireMux_T_2, out_backSel_90) node _out_wofireMux_T_364 = and(_out_wofireMux_T_363, UInt<1>(0h1)) connect out_wofireMux_out_90, UInt<1>(0h1) node _out_wofireMux_T_365 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_366 = or(out_wofireMux_out_90, _out_wofireMux_T_365) wire out_wofireMux_out_91 : UInt<1> node _out_wofireMux_T_367 = and(_out_wofireMux_T_2, out_backSel_91) node _out_wofireMux_T_368 = and(_out_wofireMux_T_367, UInt<1>(0h1)) connect out_wofireMux_out_91, UInt<1>(0h1) node _out_wofireMux_T_369 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_370 = or(out_wofireMux_out_91, _out_wofireMux_T_369) wire out_wofireMux_out_92 : UInt<1> node _out_wofireMux_T_371 = and(_out_wofireMux_T_2, out_backSel_92) node _out_wofireMux_T_372 = and(_out_wofireMux_T_371, UInt<1>(0h1)) connect out_wofireMux_out_92, UInt<1>(0h1) node _out_wofireMux_T_373 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_374 = or(out_wofireMux_out_92, _out_wofireMux_T_373) wire out_wofireMux_out_93 : UInt<1> node _out_wofireMux_T_375 = and(_out_wofireMux_T_2, out_backSel_93) node _out_wofireMux_T_376 = and(_out_wofireMux_T_375, UInt<1>(0h1)) connect out_wofireMux_out_93, UInt<1>(0h1) node _out_wofireMux_T_377 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_378 = or(out_wofireMux_out_93, _out_wofireMux_T_377) wire out_wofireMux_out_94 : UInt<1> node _out_wofireMux_T_379 = and(_out_wofireMux_T_2, out_backSel_94) node _out_wofireMux_T_380 = and(_out_wofireMux_T_379, UInt<1>(0h1)) connect out_wofireMux_out_94, UInt<1>(0h1) node _out_wofireMux_T_381 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_382 = or(out_wofireMux_out_94, _out_wofireMux_T_381) wire out_wofireMux_out_95 : UInt<1> node _out_wofireMux_T_383 = and(_out_wofireMux_T_2, out_backSel_95) node _out_wofireMux_T_384 = and(_out_wofireMux_T_383, UInt<1>(0h1)) connect out_wofireMux_out_95, UInt<1>(0h1) node _out_wofireMux_T_385 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_386 = or(out_wofireMux_out_95, _out_wofireMux_T_385) wire out_wofireMux_out_96 : UInt<1> node _out_wofireMux_T_387 = and(_out_wofireMux_T_2, out_backSel_96) node _out_wofireMux_T_388 = and(_out_wofireMux_T_387, _out_T_5) connect out_wofireMux_out_96, UInt<1>(0h1) connect out_woready[7], _out_wofireMux_T_388 connect out_woready[6], _out_wofireMux_T_388 connect out_woready[5], _out_wofireMux_T_388 node _out_wofireMux_T_389 = eq(_out_T_5, UInt<1>(0h0)) node _out_wofireMux_T_390 = or(out_wofireMux_out_96, _out_wofireMux_T_389) wire out_wofireMux_out_97 : UInt<1> node _out_wofireMux_T_391 = and(_out_wofireMux_T_2, out_backSel_97) node _out_wofireMux_T_392 = and(_out_wofireMux_T_391, UInt<1>(0h1)) connect out_wofireMux_out_97, UInt<1>(0h1) node _out_wofireMux_T_393 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_394 = or(out_wofireMux_out_97, _out_wofireMux_T_393) wire out_wofireMux_out_98 : UInt<1> node _out_wofireMux_T_395 = and(_out_wofireMux_T_2, out_backSel_98) node _out_wofireMux_T_396 = and(_out_wofireMux_T_395, UInt<1>(0h1)) connect out_wofireMux_out_98, UInt<1>(0h1) node _out_wofireMux_T_397 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_398 = or(out_wofireMux_out_98, _out_wofireMux_T_397) wire out_wofireMux_out_99 : UInt<1> node _out_wofireMux_T_399 = and(_out_wofireMux_T_2, out_backSel_99) node _out_wofireMux_T_400 = and(_out_wofireMux_T_399, UInt<1>(0h1)) connect out_wofireMux_out_99, UInt<1>(0h1) node _out_wofireMux_T_401 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_402 = or(out_wofireMux_out_99, _out_wofireMux_T_401) wire out_wofireMux_out_100 : UInt<1> node _out_wofireMux_T_403 = and(_out_wofireMux_T_2, out_backSel_100) node _out_wofireMux_T_404 = and(_out_wofireMux_T_403, UInt<1>(0h1)) connect out_wofireMux_out_100, UInt<1>(0h1) node _out_wofireMux_T_405 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_406 = or(out_wofireMux_out_100, _out_wofireMux_T_405) wire out_wofireMux_out_101 : UInt<1> node _out_wofireMux_T_407 = and(_out_wofireMux_T_2, out_backSel_101) node _out_wofireMux_T_408 = and(_out_wofireMux_T_407, UInt<1>(0h1)) connect out_wofireMux_out_101, UInt<1>(0h1) node _out_wofireMux_T_409 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_410 = or(out_wofireMux_out_101, _out_wofireMux_T_409) wire out_wofireMux_out_102 : UInt<1> node _out_wofireMux_T_411 = and(_out_wofireMux_T_2, out_backSel_102) node _out_wofireMux_T_412 = and(_out_wofireMux_T_411, UInt<1>(0h1)) connect out_wofireMux_out_102, UInt<1>(0h1) node _out_wofireMux_T_413 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_414 = or(out_wofireMux_out_102, _out_wofireMux_T_413) wire out_wofireMux_out_103 : UInt<1> node _out_wofireMux_T_415 = and(_out_wofireMux_T_2, out_backSel_103) node _out_wofireMux_T_416 = and(_out_wofireMux_T_415, UInt<1>(0h1)) connect out_wofireMux_out_103, UInt<1>(0h1) node _out_wofireMux_T_417 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_418 = or(out_wofireMux_out_103, _out_wofireMux_T_417) wire out_wofireMux_out_104 : UInt<1> node _out_wofireMux_T_419 = and(_out_wofireMux_T_2, out_backSel_104) node _out_wofireMux_T_420 = and(_out_wofireMux_T_419, _out_T_1) connect out_wofireMux_out_104, UInt<1>(0h1) connect out_woready[2], _out_wofireMux_T_420 connect out_woready[1], _out_wofireMux_T_420 connect out_woready[0], _out_wofireMux_T_420 node _out_wofireMux_T_421 = eq(_out_T_1, UInt<1>(0h0)) node _out_wofireMux_T_422 = or(out_wofireMux_out_104, _out_wofireMux_T_421) wire out_wofireMux_out_105 : UInt<1> node _out_wofireMux_T_423 = and(_out_wofireMux_T_2, out_backSel_105) node _out_wofireMux_T_424 = and(_out_wofireMux_T_423, UInt<1>(0h1)) connect out_wofireMux_out_105, UInt<1>(0h1) node _out_wofireMux_T_425 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_426 = or(out_wofireMux_out_105, _out_wofireMux_T_425) wire out_wofireMux_out_106 : UInt<1> node _out_wofireMux_T_427 = and(_out_wofireMux_T_2, out_backSel_106) node _out_wofireMux_T_428 = and(_out_wofireMux_T_427, UInt<1>(0h1)) connect out_wofireMux_out_106, UInt<1>(0h1) node _out_wofireMux_T_429 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_430 = or(out_wofireMux_out_106, _out_wofireMux_T_429) wire out_wofireMux_out_107 : UInt<1> node _out_wofireMux_T_431 = and(_out_wofireMux_T_2, out_backSel_107) node _out_wofireMux_T_432 = and(_out_wofireMux_T_431, UInt<1>(0h1)) connect out_wofireMux_out_107, UInt<1>(0h1) node _out_wofireMux_T_433 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_434 = or(out_wofireMux_out_107, _out_wofireMux_T_433) wire out_wofireMux_out_108 : UInt<1> node _out_wofireMux_T_435 = and(_out_wofireMux_T_2, out_backSel_108) node _out_wofireMux_T_436 = and(_out_wofireMux_T_435, UInt<1>(0h1)) connect out_wofireMux_out_108, UInt<1>(0h1) node _out_wofireMux_T_437 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_438 = or(out_wofireMux_out_108, _out_wofireMux_T_437) wire out_wofireMux_out_109 : UInt<1> node _out_wofireMux_T_439 = and(_out_wofireMux_T_2, out_backSel_109) node _out_wofireMux_T_440 = and(_out_wofireMux_T_439, UInt<1>(0h1)) connect out_wofireMux_out_109, UInt<1>(0h1) node _out_wofireMux_T_441 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_442 = or(out_wofireMux_out_109, _out_wofireMux_T_441) wire out_wofireMux_out_110 : UInt<1> node _out_wofireMux_T_443 = and(_out_wofireMux_T_2, out_backSel_110) node _out_wofireMux_T_444 = and(_out_wofireMux_T_443, UInt<1>(0h1)) connect out_wofireMux_out_110, UInt<1>(0h1) node _out_wofireMux_T_445 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_446 = or(out_wofireMux_out_110, _out_wofireMux_T_445) wire out_wofireMux_out_111 : UInt<1> node _out_wofireMux_T_447 = and(_out_wofireMux_T_2, out_backSel_111) node _out_wofireMux_T_448 = and(_out_wofireMux_T_447, UInt<1>(0h1)) connect out_wofireMux_out_111, UInt<1>(0h1) node _out_wofireMux_T_449 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_450 = or(out_wofireMux_out_111, _out_wofireMux_T_449) wire out_wofireMux_out_112 : UInt<1> node _out_wofireMux_T_451 = and(_out_wofireMux_T_2, out_backSel_112) node _out_wofireMux_T_452 = and(_out_wofireMux_T_451, _out_T_17) connect out_wofireMux_out_112, UInt<1>(0h1) connect out_woready[25], _out_wofireMux_T_452 connect out_woready[24], _out_wofireMux_T_452 connect out_woready[23], _out_wofireMux_T_452 node _out_wofireMux_T_453 = eq(_out_T_17, UInt<1>(0h0)) node _out_wofireMux_T_454 = or(out_wofireMux_out_112, _out_wofireMux_T_453) wire out_wofireMux_out_113 : UInt<1> node _out_wofireMux_T_455 = and(_out_wofireMux_T_2, out_backSel_113) node _out_wofireMux_T_456 = and(_out_wofireMux_T_455, UInt<1>(0h1)) connect out_wofireMux_out_113, UInt<1>(0h1) node _out_wofireMux_T_457 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_458 = or(out_wofireMux_out_113, _out_wofireMux_T_457) wire out_wofireMux_out_114 : UInt<1> node _out_wofireMux_T_459 = and(_out_wofireMux_T_2, out_backSel_114) node _out_wofireMux_T_460 = and(_out_wofireMux_T_459, UInt<1>(0h1)) connect out_wofireMux_out_114, UInt<1>(0h1) node _out_wofireMux_T_461 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_462 = or(out_wofireMux_out_114, _out_wofireMux_T_461) wire out_wofireMux_out_115 : UInt<1> node _out_wofireMux_T_463 = and(_out_wofireMux_T_2, out_backSel_115) node _out_wofireMux_T_464 = and(_out_wofireMux_T_463, UInt<1>(0h1)) connect out_wofireMux_out_115, UInt<1>(0h1) node _out_wofireMux_T_465 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_466 = or(out_wofireMux_out_115, _out_wofireMux_T_465) wire out_wofireMux_out_116 : UInt<1> node _out_wofireMux_T_467 = and(_out_wofireMux_T_2, out_backSel_116) node _out_wofireMux_T_468 = and(_out_wofireMux_T_467, UInt<1>(0h1)) connect out_wofireMux_out_116, UInt<1>(0h1) node _out_wofireMux_T_469 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_470 = or(out_wofireMux_out_116, _out_wofireMux_T_469) wire out_wofireMux_out_117 : UInt<1> node _out_wofireMux_T_471 = and(_out_wofireMux_T_2, out_backSel_117) node _out_wofireMux_T_472 = and(_out_wofireMux_T_471, UInt<1>(0h1)) connect out_wofireMux_out_117, UInt<1>(0h1) node _out_wofireMux_T_473 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_474 = or(out_wofireMux_out_117, _out_wofireMux_T_473) wire out_wofireMux_out_118 : UInt<1> node _out_wofireMux_T_475 = and(_out_wofireMux_T_2, out_backSel_118) node _out_wofireMux_T_476 = and(_out_wofireMux_T_475, UInt<1>(0h1)) connect out_wofireMux_out_118, UInt<1>(0h1) node _out_wofireMux_T_477 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_478 = or(out_wofireMux_out_118, _out_wofireMux_T_477) wire out_wofireMux_out_119 : UInt<1> node _out_wofireMux_T_479 = and(_out_wofireMux_T_2, out_backSel_119) node _out_wofireMux_T_480 = and(_out_wofireMux_T_479, UInt<1>(0h1)) connect out_wofireMux_out_119, UInt<1>(0h1) node _out_wofireMux_T_481 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_482 = or(out_wofireMux_out_119, _out_wofireMux_T_481) wire out_wofireMux_out_120 : UInt<1> node _out_wofireMux_T_483 = and(_out_wofireMux_T_2, out_backSel_120) node _out_wofireMux_T_484 = and(_out_wofireMux_T_483, _out_T_11) connect out_wofireMux_out_120, UInt<1>(0h1) connect out_woready[16], _out_wofireMux_T_484 connect out_woready[15], _out_wofireMux_T_484 connect out_woready[14], _out_wofireMux_T_484 node _out_wofireMux_T_485 = eq(_out_T_11, UInt<1>(0h0)) node _out_wofireMux_T_486 = or(out_wofireMux_out_120, _out_wofireMux_T_485) wire out_wofireMux_out_121 : UInt<1> node _out_wofireMux_T_487 = and(_out_wofireMux_T_2, out_backSel_121) node _out_wofireMux_T_488 = and(_out_wofireMux_T_487, UInt<1>(0h1)) connect out_wofireMux_out_121, UInt<1>(0h1) node _out_wofireMux_T_489 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_490 = or(out_wofireMux_out_121, _out_wofireMux_T_489) wire out_wofireMux_out_122 : UInt<1> node _out_wofireMux_T_491 = and(_out_wofireMux_T_2, out_backSel_122) node _out_wofireMux_T_492 = and(_out_wofireMux_T_491, UInt<1>(0h1)) connect out_wofireMux_out_122, UInt<1>(0h1) node _out_wofireMux_T_493 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_494 = or(out_wofireMux_out_122, _out_wofireMux_T_493) wire out_wofireMux_out_123 : UInt<1> node _out_wofireMux_T_495 = and(_out_wofireMux_T_2, out_backSel_123) node _out_wofireMux_T_496 = and(_out_wofireMux_T_495, UInt<1>(0h1)) connect out_wofireMux_out_123, UInt<1>(0h1) node _out_wofireMux_T_497 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_498 = or(out_wofireMux_out_123, _out_wofireMux_T_497) wire out_wofireMux_out_124 : UInt<1> node _out_wofireMux_T_499 = and(_out_wofireMux_T_2, out_backSel_124) node _out_wofireMux_T_500 = and(_out_wofireMux_T_499, UInt<1>(0h1)) connect out_wofireMux_out_124, UInt<1>(0h1) node _out_wofireMux_T_501 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_502 = or(out_wofireMux_out_124, _out_wofireMux_T_501) wire out_wofireMux_out_125 : UInt<1> node _out_wofireMux_T_503 = and(_out_wofireMux_T_2, out_backSel_125) node _out_wofireMux_T_504 = and(_out_wofireMux_T_503, UInt<1>(0h1)) connect out_wofireMux_out_125, UInt<1>(0h1) node _out_wofireMux_T_505 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_506 = or(out_wofireMux_out_125, _out_wofireMux_T_505) wire out_wofireMux_out_126 : UInt<1> node _out_wofireMux_T_507 = and(_out_wofireMux_T_2, out_backSel_126) node _out_wofireMux_T_508 = and(_out_wofireMux_T_507, UInt<1>(0h1)) connect out_wofireMux_out_126, UInt<1>(0h1) node _out_wofireMux_T_509 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_510 = or(out_wofireMux_out_126, _out_wofireMux_T_509) wire out_wofireMux_out_127 : UInt<1> node _out_wofireMux_T_511 = and(_out_wofireMux_T_2, out_backSel_127) node _out_wofireMux_T_512 = and(_out_wofireMux_T_511, UInt<1>(0h1)) connect out_wofireMux_out_127, UInt<1>(0h1) node _out_wofireMux_T_513 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_514 = or(out_wofireMux_out_127, _out_wofireMux_T_513) node _out_wofireMux_T_515 = geq(out_oindex, UInt<8>(0h80)) wire _out_wofireMux_WIRE : UInt<1>[128] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 connect _out_wofireMux_WIRE[1], _out_wofireMux_T_10 connect _out_wofireMux_WIRE[2], _out_wofireMux_T_14 connect _out_wofireMux_WIRE[3], _out_wofireMux_T_18 connect _out_wofireMux_WIRE[4], _out_wofireMux_T_22 connect _out_wofireMux_WIRE[5], _out_wofireMux_T_26 connect _out_wofireMux_WIRE[6], _out_wofireMux_T_30 connect _out_wofireMux_WIRE[7], _out_wofireMux_T_34 connect _out_wofireMux_WIRE[8], _out_wofireMux_T_38 connect _out_wofireMux_WIRE[9], _out_wofireMux_T_42 connect _out_wofireMux_WIRE[10], _out_wofireMux_T_46 connect _out_wofireMux_WIRE[11], _out_wofireMux_T_50 connect _out_wofireMux_WIRE[12], _out_wofireMux_T_54 connect _out_wofireMux_WIRE[13], _out_wofireMux_T_58 connect _out_wofireMux_WIRE[14], _out_wofireMux_T_62 connect _out_wofireMux_WIRE[15], _out_wofireMux_T_66 connect _out_wofireMux_WIRE[16], _out_wofireMux_T_70 connect _out_wofireMux_WIRE[17], _out_wofireMux_T_74 connect _out_wofireMux_WIRE[18], _out_wofireMux_T_78 connect _out_wofireMux_WIRE[19], _out_wofireMux_T_82 connect _out_wofireMux_WIRE[20], _out_wofireMux_T_86 connect _out_wofireMux_WIRE[21], _out_wofireMux_T_90 connect _out_wofireMux_WIRE[22], _out_wofireMux_T_94 connect _out_wofireMux_WIRE[23], _out_wofireMux_T_98 connect _out_wofireMux_WIRE[24], _out_wofireMux_T_102 connect _out_wofireMux_WIRE[25], _out_wofireMux_T_106 connect _out_wofireMux_WIRE[26], _out_wofireMux_T_110 connect _out_wofireMux_WIRE[27], _out_wofireMux_T_114 connect _out_wofireMux_WIRE[28], _out_wofireMux_T_118 connect _out_wofireMux_WIRE[29], _out_wofireMux_T_122 connect _out_wofireMux_WIRE[30], _out_wofireMux_T_126 connect _out_wofireMux_WIRE[31], _out_wofireMux_T_130 connect _out_wofireMux_WIRE[32], _out_wofireMux_T_134 connect _out_wofireMux_WIRE[33], _out_wofireMux_T_138 connect _out_wofireMux_WIRE[34], _out_wofireMux_T_142 connect _out_wofireMux_WIRE[35], _out_wofireMux_T_146 connect _out_wofireMux_WIRE[36], _out_wofireMux_T_150 connect _out_wofireMux_WIRE[37], _out_wofireMux_T_154 connect _out_wofireMux_WIRE[38], _out_wofireMux_T_158 connect _out_wofireMux_WIRE[39], _out_wofireMux_T_162 connect _out_wofireMux_WIRE[40], _out_wofireMux_T_166 connect _out_wofireMux_WIRE[41], _out_wofireMux_T_170 connect _out_wofireMux_WIRE[42], _out_wofireMux_T_174 connect _out_wofireMux_WIRE[43], _out_wofireMux_T_178 connect _out_wofireMux_WIRE[44], _out_wofireMux_T_182 connect _out_wofireMux_WIRE[45], _out_wofireMux_T_186 connect _out_wofireMux_WIRE[46], _out_wofireMux_T_190 connect _out_wofireMux_WIRE[47], _out_wofireMux_T_194 connect _out_wofireMux_WIRE[48], _out_wofireMux_T_198 connect _out_wofireMux_WIRE[49], _out_wofireMux_T_202 connect _out_wofireMux_WIRE[50], _out_wofireMux_T_206 connect _out_wofireMux_WIRE[51], _out_wofireMux_T_210 connect _out_wofireMux_WIRE[52], _out_wofireMux_T_214 connect _out_wofireMux_WIRE[53], _out_wofireMux_T_218 connect _out_wofireMux_WIRE[54], _out_wofireMux_T_222 connect _out_wofireMux_WIRE[55], _out_wofireMux_T_226 connect _out_wofireMux_WIRE[56], _out_wofireMux_T_230 connect _out_wofireMux_WIRE[57], _out_wofireMux_T_234 connect _out_wofireMux_WIRE[58], _out_wofireMux_T_238 connect _out_wofireMux_WIRE[59], _out_wofireMux_T_242 connect _out_wofireMux_WIRE[60], _out_wofireMux_T_246 connect _out_wofireMux_WIRE[61], _out_wofireMux_T_250 connect _out_wofireMux_WIRE[62], _out_wofireMux_T_254 connect _out_wofireMux_WIRE[63], _out_wofireMux_T_258 connect _out_wofireMux_WIRE[64], _out_wofireMux_T_262 connect _out_wofireMux_WIRE[65], _out_wofireMux_T_266 connect _out_wofireMux_WIRE[66], _out_wofireMux_T_270 connect _out_wofireMux_WIRE[67], _out_wofireMux_T_274 connect _out_wofireMux_WIRE[68], _out_wofireMux_T_278 connect _out_wofireMux_WIRE[69], _out_wofireMux_T_282 connect _out_wofireMux_WIRE[70], _out_wofireMux_T_286 connect _out_wofireMux_WIRE[71], _out_wofireMux_T_290 connect _out_wofireMux_WIRE[72], _out_wofireMux_T_294 connect _out_wofireMux_WIRE[73], _out_wofireMux_T_298 connect _out_wofireMux_WIRE[74], _out_wofireMux_T_302 connect _out_wofireMux_WIRE[75], _out_wofireMux_T_306 connect _out_wofireMux_WIRE[76], _out_wofireMux_T_310 connect _out_wofireMux_WIRE[77], _out_wofireMux_T_314 connect _out_wofireMux_WIRE[78], _out_wofireMux_T_318 connect _out_wofireMux_WIRE[79], _out_wofireMux_T_322 connect _out_wofireMux_WIRE[80], _out_wofireMux_T_326 connect _out_wofireMux_WIRE[81], _out_wofireMux_T_330 connect _out_wofireMux_WIRE[82], _out_wofireMux_T_334 connect _out_wofireMux_WIRE[83], _out_wofireMux_T_338 connect _out_wofireMux_WIRE[84], _out_wofireMux_T_342 connect _out_wofireMux_WIRE[85], _out_wofireMux_T_346 connect _out_wofireMux_WIRE[86], _out_wofireMux_T_350 connect _out_wofireMux_WIRE[87], _out_wofireMux_T_354 connect _out_wofireMux_WIRE[88], _out_wofireMux_T_358 connect _out_wofireMux_WIRE[89], _out_wofireMux_T_362 connect _out_wofireMux_WIRE[90], _out_wofireMux_T_366 connect _out_wofireMux_WIRE[91], _out_wofireMux_T_370 connect _out_wofireMux_WIRE[92], _out_wofireMux_T_374 connect _out_wofireMux_WIRE[93], _out_wofireMux_T_378 connect _out_wofireMux_WIRE[94], _out_wofireMux_T_382 connect _out_wofireMux_WIRE[95], _out_wofireMux_T_386 connect _out_wofireMux_WIRE[96], _out_wofireMux_T_390 connect _out_wofireMux_WIRE[97], _out_wofireMux_T_394 connect _out_wofireMux_WIRE[98], _out_wofireMux_T_398 connect _out_wofireMux_WIRE[99], _out_wofireMux_T_402 connect _out_wofireMux_WIRE[100], _out_wofireMux_T_406 connect _out_wofireMux_WIRE[101], _out_wofireMux_T_410 connect _out_wofireMux_WIRE[102], _out_wofireMux_T_414 connect _out_wofireMux_WIRE[103], _out_wofireMux_T_418 connect _out_wofireMux_WIRE[104], _out_wofireMux_T_422 connect _out_wofireMux_WIRE[105], _out_wofireMux_T_426 connect _out_wofireMux_WIRE[106], _out_wofireMux_T_430 connect _out_wofireMux_WIRE[107], _out_wofireMux_T_434 connect _out_wofireMux_WIRE[108], _out_wofireMux_T_438 connect _out_wofireMux_WIRE[109], _out_wofireMux_T_442 connect _out_wofireMux_WIRE[110], _out_wofireMux_T_446 connect _out_wofireMux_WIRE[111], _out_wofireMux_T_450 connect _out_wofireMux_WIRE[112], _out_wofireMux_T_454 connect _out_wofireMux_WIRE[113], _out_wofireMux_T_458 connect _out_wofireMux_WIRE[114], _out_wofireMux_T_462 connect _out_wofireMux_WIRE[115], _out_wofireMux_T_466 connect _out_wofireMux_WIRE[116], _out_wofireMux_T_470 connect _out_wofireMux_WIRE[117], _out_wofireMux_T_474 connect _out_wofireMux_WIRE[118], _out_wofireMux_T_478 connect _out_wofireMux_WIRE[119], _out_wofireMux_T_482 connect _out_wofireMux_WIRE[120], _out_wofireMux_T_486 connect _out_wofireMux_WIRE[121], _out_wofireMux_T_490 connect _out_wofireMux_WIRE[122], _out_wofireMux_T_494 connect _out_wofireMux_WIRE[123], _out_wofireMux_T_498 connect _out_wofireMux_WIRE[124], _out_wofireMux_T_502 connect _out_wofireMux_WIRE[125], _out_wofireMux_T_506 connect _out_wofireMux_WIRE[126], _out_wofireMux_T_510 connect _out_wofireMux_WIRE[127], _out_wofireMux_T_514 node out_wofireMux = mux(_out_wofireMux_T_515, UInt<1>(0h1), _out_wofireMux_WIRE[out_oindex]) node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) node out_oready = mux(out_back_front_q.io.deq.bits.read, out_rofireMux, out_wofireMux) node _out_in_ready_T = and(out_front.ready, out_iready) connect in.ready, _out_in_ready_T node _out_front_valid_T = and(in.valid, out_iready) connect out_front.valid, _out_front_valid_T node _out_front_q_io_deq_ready_T = and(out.ready, out_oready) connect out_back_front_q.io.deq.ready, _out_front_q_io_deq_ready_T node _out_out_valid_T = and(out_back_front_q.io.deq.valid, out_oready) connect out.valid, _out_out_valid_T connect out.bits.read, out_back_front_q.io.deq.bits.read wire out_out_bits_data_out : UInt<1> connect out_out_bits_data_out, UInt<1>(0h1) node _out_out_bits_data_T = eq(UInt<1>(0h0), out_oindex) when _out_out_bits_data_T : connect out_out_bits_data_out, _out_T_27 else : node _out_out_bits_data_T_1 = eq(UInt<4>(0h8), out_oindex) when _out_out_bits_data_T_1 : connect out_out_bits_data_out, _out_T_3 else : node _out_out_bits_data_T_2 = eq(UInt<5>(0h10), out_oindex) when _out_out_bits_data_T_2 : connect out_out_bits_data_out, _out_T_25 else : node _out_out_bits_data_T_3 = eq(UInt<5>(0h11), out_oindex) when _out_out_bits_data_T_3 : connect out_out_bits_data_out, _out_T_29 else : node _out_out_bits_data_T_4 = eq(UInt<5>(0h12), out_oindex) when _out_out_bits_data_T_4 : connect out_out_bits_data_out, _out_T_19 else : node _out_out_bits_data_T_5 = eq(UInt<5>(0h13), out_oindex) when _out_out_bits_data_T_5 : connect out_out_bits_data_out, _out_T_33 else : node _out_out_bits_data_T_6 = eq(UInt<5>(0h14), out_oindex) when _out_out_bits_data_T_6 : connect out_out_bits_data_out, _out_T_23 else : node _out_out_bits_data_T_7 = eq(UInt<5>(0h15), out_oindex) when _out_out_bits_data_T_7 : connect out_out_bits_data_out, _out_T_35 else : node _out_out_bits_data_T_8 = eq(UInt<5>(0h16), out_oindex) when _out_out_bits_data_T_8 : connect out_out_bits_data_out, _out_T_21 else : node _out_out_bits_data_T_9 = eq(UInt<5>(0h17), out_oindex) when _out_out_bits_data_T_9 : connect out_out_bits_data_out, _out_T_31 else : node _out_out_bits_data_T_10 = eq(UInt<7>(0h40), out_oindex) when _out_out_bits_data_T_10 : connect out_out_bits_data_out, _out_T_13 else : node _out_out_bits_data_T_11 = eq(UInt<7>(0h48), out_oindex) when _out_out_bits_data_T_11 : connect out_out_bits_data_out, _out_T_7 else : node _out_out_bits_data_T_12 = eq(UInt<7>(0h50), out_oindex) when _out_out_bits_data_T_12 : connect out_out_bits_data_out, _out_T_15 else : node _out_out_bits_data_T_13 = eq(UInt<7>(0h58), out_oindex) when _out_out_bits_data_T_13 : connect out_out_bits_data_out, _out_T_9 else : node _out_out_bits_data_T_14 = eq(UInt<7>(0h60), out_oindex) when _out_out_bits_data_T_14 : connect out_out_bits_data_out, _out_T_5 else : node _out_out_bits_data_T_15 = eq(UInt<7>(0h68), out_oindex) when _out_out_bits_data_T_15 : connect out_out_bits_data_out, _out_T_1 else : node _out_out_bits_data_T_16 = eq(UInt<7>(0h70), out_oindex) when _out_out_bits_data_T_16 : connect out_out_bits_data_out, _out_T_17 else : node _out_out_bits_data_T_17 = eq(UInt<7>(0h78), out_oindex) when _out_out_bits_data_T_17 : connect out_out_bits_data_out, _out_T_11 wire out_out_bits_data_out_1 : UInt connect out_out_bits_data_out_1, UInt<1>(0h0) node _out_out_bits_data_T_18 = eq(UInt<1>(0h0), out_oindex) when _out_out_bits_data_T_18 : connect out_out_bits_data_out_1, _out_T_432 else : node _out_out_bits_data_T_19 = eq(UInt<4>(0h8), out_oindex) when _out_out_bits_data_T_19 : connect out_out_bits_data_out_1, _out_T_89 else : node _out_out_bits_data_T_20 = eq(UInt<5>(0h10), out_oindex) when _out_out_bits_data_T_20 : connect out_out_bits_data_out_1, _out_T_421 else : node _out_out_bits_data_T_21 = eq(UInt<5>(0h11), out_oindex) when _out_out_bits_data_T_21 : connect out_out_bits_data_out_1, _out_T_452 else : node _out_out_bits_data_T_22 = eq(UInt<5>(0h12), out_oindex) when _out_out_bits_data_T_22 : connect out_out_bits_data_out_1, _out_T_361 else : node _out_out_bits_data_T_23 = eq(UInt<5>(0h13), out_oindex) when _out_out_bits_data_T_23 : connect out_out_bits_data_out_1, _out_T_492 else : node _out_out_bits_data_T_24 = eq(UInt<5>(0h14), out_oindex) when _out_out_bits_data_T_24 : connect out_out_bits_data_out_1, _out_T_401 else : node _out_out_bits_data_T_25 = eq(UInt<5>(0h15), out_oindex) when _out_out_bits_data_T_25 : connect out_out_bits_data_out_1, _out_T_512 else : node _out_out_bits_data_T_26 = eq(UInt<5>(0h16), out_oindex) when _out_out_bits_data_T_26 : connect out_out_bits_data_out_1, _out_T_381 else : node _out_out_bits_data_T_27 = eq(UInt<5>(0h17), out_oindex) when _out_out_bits_data_T_27 : connect out_out_bits_data_out_1, _out_T_472 else : node _out_out_bits_data_T_28 = eq(UInt<7>(0h40), out_oindex) when _out_out_bits_data_T_28 : connect out_out_bits_data_out_1, _out_T_269 else : node _out_out_bits_data_T_29 = eq(UInt<7>(0h48), out_oindex) when _out_out_bits_data_T_29 : connect out_out_bits_data_out_1, _out_T_161 else : node _out_out_bits_data_T_30 = eq(UInt<7>(0h50), out_oindex) when _out_out_bits_data_T_30 : connect out_out_bits_data_out_1, _out_T_305 else : node _out_out_bits_data_T_31 = eq(UInt<7>(0h58), out_oindex) when _out_out_bits_data_T_31 : connect out_out_bits_data_out_1, _out_T_197 else : node _out_out_bits_data_T_32 = eq(UInt<7>(0h60), out_oindex) when _out_out_bits_data_T_32 : connect out_out_bits_data_out_1, _out_T_125 else : node _out_out_bits_data_T_33 = eq(UInt<7>(0h68), out_oindex) when _out_out_bits_data_T_33 : connect out_out_bits_data_out_1, _out_T_71 else : node _out_out_bits_data_T_34 = eq(UInt<7>(0h70), out_oindex) when _out_out_bits_data_T_34 : connect out_out_bits_data_out_1, _out_T_341 else : node _out_out_bits_data_T_35 = eq(UInt<7>(0h78), out_oindex) when _out_out_bits_data_T_35 : connect out_out_bits_data_out_1, _out_T_233 node _out_out_bits_data_T_36 = mux(out_out_bits_data_out, out_out_bits_data_out_1, UInt<1>(0h0)) connect out.bits.data, _out_out_bits_data_T_36 connect out.bits.extra, out_back_front_q.io.deq.bits.extra connect in.valid, nodeIn.a.valid connect nodeIn.a.ready, in.ready connect nodeIn.d.valid, out.valid connect out.ready, nodeIn.d.ready wire nodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect nodeIn_d_bits_d.opcode, UInt<1>(0h0) connect nodeIn_d_bits_d.param, UInt<1>(0h0) connect nodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size connect nodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source connect nodeIn_d_bits_d.sink, UInt<1>(0h0) connect nodeIn_d_bits_d.denied, UInt<1>(0h0) invalidate nodeIn_d_bits_d.data connect nodeIn_d_bits_d.corrupt, UInt<1>(0h0) connect nodeIn.d.bits.corrupt, nodeIn_d_bits_d.corrupt connect nodeIn.d.bits.data, nodeIn_d_bits_d.data connect nodeIn.d.bits.denied, nodeIn_d_bits_d.denied connect nodeIn.d.bits.sink, nodeIn_d_bits_d.sink connect nodeIn.d.bits.source, nodeIn_d_bits_d.source connect nodeIn.d.bits.size, nodeIn_d_bits_d.size connect nodeIn.d.bits.param, nodeIn_d_bits_d.param connect nodeIn.d.bits.opcode, nodeIn_d_bits_d.opcode connect nodeIn.d.bits.data, out.bits.data node _nodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) connect nodeIn.d.bits.opcode, _nodeIn_d_bits_opcode_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<28>(0h0) connect _WIRE.bits.source, UInt<12>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<28>(0h0) connect _WIRE_2.bits.source, UInt<12>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1)
module TLPLIC( // @[Plic.scala:132:9] input clock, // @[Plic.scala:132:9] input reset, // @[Plic.scala:132:9] input auto_int_in_0, // @[LazyModuleImp.scala:107:25] output auto_int_out_7_0, // @[LazyModuleImp.scala:107:25] output auto_int_out_6_0, // @[LazyModuleImp.scala:107:25] output auto_int_out_5_0, // @[LazyModuleImp.scala:107:25] output auto_int_out_4_0, // @[LazyModuleImp.scala:107:25] output auto_int_out_3_0, // @[LazyModuleImp.scala:107:25] output auto_int_out_2_0, // @[LazyModuleImp.scala:107:25] output auto_int_out_1_0, // @[LazyModuleImp.scala:107:25] output auto_int_out_0_0, // @[LazyModuleImp.scala:107:25] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [27:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [11:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [22:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire _out_back_front_q_io_deq_valid; // @[RegisterRouter.scala:87:24] wire _out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24] wire [22:0] _out_back_front_q_io_deq_bits_index; // @[RegisterRouter.scala:87:24] wire [63:0] _out_back_front_q_io_deq_bits_data; // @[RegisterRouter.scala:87:24] wire [7:0] _out_back_front_q_io_deq_bits_mask; // @[RegisterRouter.scala:87:24] wire _fanin_7_io_dev; // @[Plic.scala:189:27] wire _fanin_7_io_max; // @[Plic.scala:189:27] wire _fanin_6_io_dev; // @[Plic.scala:189:27] wire _fanin_6_io_max; // @[Plic.scala:189:27] wire _fanin_5_io_dev; // @[Plic.scala:189:27] wire _fanin_5_io_max; // @[Plic.scala:189:27] wire _fanin_4_io_dev; // @[Plic.scala:189:27] wire _fanin_4_io_max; // @[Plic.scala:189:27] wire _fanin_3_io_dev; // @[Plic.scala:189:27] wire _fanin_3_io_max; // @[Plic.scala:189:27] wire _fanin_2_io_dev; // @[Plic.scala:189:27] wire _fanin_2_io_max; // @[Plic.scala:189:27] wire _fanin_1_io_dev; // @[Plic.scala:189:27] wire _fanin_1_io_max; // @[Plic.scala:189:27] wire _fanin_io_dev; // @[Plic.scala:189:27] wire _fanin_io_max; // @[Plic.scala:189:27] wire _gateways_gateway_io_plic_valid; // @[Plic.scala:160:27] wire auto_int_in_0_0 = auto_int_in_0; // @[Plic.scala:132:9] wire auto_in_a_valid_0 = auto_in_a_valid; // @[Plic.scala:132:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Plic.scala:132:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Plic.scala:132:9] wire [1:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Plic.scala:132:9] wire [11:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Plic.scala:132:9] wire [27:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Plic.scala:132:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Plic.scala:132:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Plic.scala:132:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Plic.scala:132:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Plic.scala:132:9] wire _out_T_59 = reset; // @[Plic.scala:298:19] wire _out_T_113 = reset; // @[Plic.scala:298:19] wire _out_T_149 = reset; // @[Plic.scala:298:19] wire _out_T_185 = reset; // @[Plic.scala:298:19] wire _out_T_221 = reset; // @[Plic.scala:298:19] wire _out_T_257 = reset; // @[Plic.scala:298:19] wire _out_T_293 = reset; // @[Plic.scala:298:19] wire _out_T_329 = reset; // @[Plic.scala:298:19] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_21 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_25 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_29 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_33 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_8 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_37 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_41 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_45 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_11 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_49 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_12 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_53 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_57 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_61 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_15 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_65 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_16 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_69 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_73 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_77 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_19 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_81 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_20 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_85 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_21 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_89 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_93 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_23 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_97 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_24 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_101 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_25 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_105 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_109 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_27 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_113 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_28 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_117 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_29 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_121 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_125 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_31 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_129 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_32 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_133 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_33 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_137 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_34 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_141 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_35 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_145 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_36 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_149 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_37 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_153 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_38 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_157 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_39 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_161 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_40 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_165 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_41 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_169 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_42 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_173 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_43 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_177 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_44 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_181 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_45 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_185 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_46 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_189 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_47 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_193 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_48 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_197 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_49 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_201 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_50 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_205 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_51 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_209 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_52 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_213 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_53 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_217 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_54 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_221 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_55 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_225 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_56 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_229 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_57 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_233 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_58 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_237 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_59 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_241 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_60 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_245 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_61 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_249 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_62 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_253 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_63 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_257 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_64 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_261 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_65 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_265 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_66 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_269 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_67 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_273 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_68 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_277 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_69 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_281 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_70 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_285 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_71 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_289 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_72 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_293 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_73 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_297 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_74 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_301 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_75 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_305 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_76 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_309 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_77 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_313 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_78 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_317 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_79 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_321 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_80 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_325 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_81 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_329 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_82 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_333 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_83 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_337 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_84 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_341 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_85 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_345 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_86 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_349 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_87 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_353 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_88 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_357 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_89 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_361 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_90 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_365 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_91 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_369 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_92 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_373 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_93 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_377 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_94 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_381 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_95 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_385 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_96 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_389 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_97 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_393 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_98 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_397 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_99 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_401 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_100 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_405 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_101 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_409 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_102 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_413 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_103 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_417 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_104 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_421 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_105 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_425 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_106 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_429 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_107 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_433 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_108 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_437 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_109 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_441 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_110 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_445 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_111 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_449 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_112 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_453 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_113 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_457 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_114 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_461 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_115 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_465 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_116 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_469 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_117 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_473 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_118 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_477 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_119 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_481 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_120 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_485 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_121 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_489 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_122 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_493 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_123 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_497 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_124 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_501 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_125 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_505 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_126 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_509 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_127 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_513 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_16 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_17 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_18 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_19 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_20 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_21 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_22 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_23 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_24 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_25 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_26 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_27 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_28 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_29 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_30 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_31 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_32 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_33 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_34 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_35 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_36 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_37 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_38 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_39 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_40 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_41 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_42 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_43 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_44 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_45 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_46 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_47 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_48 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_49 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_50 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_51 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_52 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_53 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_54 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_55 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_56 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_57 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_58 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_59 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_60 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_61 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_62 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_63 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_64 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_65 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_66 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_67 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_68 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_69 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_70 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_71 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_72 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_73 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_74 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_75 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_76 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_77 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_78 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_79 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_80 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_81 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_82 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_83 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_84 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_85 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_86 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_87 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_88 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_89 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_90 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_91 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_92 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_93 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_94 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_95 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_96 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_97 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_98 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_99 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_100 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_101 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_102 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_103 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_104 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_105 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_106 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_107 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_108 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_109 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_110 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_111 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_112 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_113 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_114 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_115 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_116 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_117 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_118 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_119 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_120 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_121 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_122 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_123 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_124 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_125 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_126 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_127 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_34 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_8 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_38 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_42 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_46 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_11 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_50 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_12 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_54 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_58 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_62 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_15 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_66 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_16 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_70 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_74 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_78 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_19 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_82 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_20 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_86 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_21 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_90 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_94 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_23 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_98 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_24 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_102 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_25 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_106 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_110 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_27 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_114 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_28 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_118 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_29 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_122 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_126 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_31 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_130 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_32 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_134 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_33 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_138 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_34 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_142 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_35 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_146 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_36 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_150 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_37 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_154 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_38 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_158 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_39 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_162 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_40 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_166 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_41 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_170 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_42 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_174 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_43 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_178 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_44 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_182 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_45 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_186 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_46 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_190 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_47 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_194 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_48 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_198 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_49 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_202 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_50 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_206 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_51 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_210 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_52 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_214 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_53 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_218 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_54 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_222 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_55 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_226 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_56 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_230 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_57 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_234 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_58 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_238 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_59 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_242 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_60 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_246 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_61 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_250 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_62 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_254 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_63 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_258 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_64 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_262 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_65 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_266 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_66 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_270 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_67 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_274 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_68 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_278 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_69 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_282 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_70 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_286 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_71 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_290 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_72 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_294 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_73 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_298 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_74 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_302 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_75 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_306 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_76 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_310 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_77 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_314 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_78 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_318 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_79 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_322 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_80 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_326 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_81 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_330 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_82 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_334 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_83 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_338 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_84 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_342 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_85 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_346 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_86 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_350 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_87 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_354 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_88 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_358 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_89 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_362 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_90 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_366 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_91 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_370 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_92 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_374 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_93 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_378 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_94 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_382 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_95 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_386 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_96 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_390 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_97 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_394 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_98 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_398 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_99 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_402 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_100 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_406 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_101 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_410 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_102 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_414 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_103 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_418 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_104 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_422 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_105 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_426 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_106 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_430 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_107 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_434 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_108 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_438 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_109 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_442 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_110 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_446 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_111 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_450 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_112 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_454 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_113 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_458 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_114 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_462 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_115 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_466 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_116 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_470 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_117 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_474 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_118 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_478 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_119 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_482 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_120 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_486 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_121 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_490 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_122 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_494 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_123 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_498 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_124 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_502 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_125 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_506 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_126 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_510 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_127 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_514 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_16 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_17 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_18 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_19 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_20 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_21 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_22 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_23 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_24 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_25 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_26 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_27 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_28 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_29 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_30 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_31 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_32 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_33 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_34 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_35 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_36 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_37 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_38 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_39 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_40 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_41 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_42 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_43 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_44 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_45 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_46 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_47 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_48 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_49 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_50 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_51 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_52 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_53 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_54 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_55 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_56 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_57 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_58 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_59 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_60 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_61 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_62 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_63 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_64 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_65 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_66 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_67 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_68 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_69 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_70 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_71 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_72 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_73 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_74 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_75 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_76 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_77 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_78 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_79 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_80 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_81 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_82 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_83 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_84 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_85 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_86 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_87 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_88 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_89 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_90 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_91 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_92 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_93 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_94 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_95 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_96 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_97 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_98 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_99 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_100 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_101 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_102 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_103 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_104 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_105 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_106 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_107 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_108 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_109 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_110 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_111 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_112 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_113 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_114 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_115 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_116 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_117 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_118 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_119 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_120 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_121 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_122 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_123 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_124 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_125 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_126 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_127 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_21 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_25 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_29 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_33 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_8 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_37 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_41 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_45 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_11 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_49 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_12 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_53 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_57 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_61 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_15 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_65 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_16 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_69 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_73 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_77 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_19 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_81 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_20 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_85 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_21 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_89 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_93 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_23 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_97 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_24 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_101 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_25 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_105 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_109 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_27 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_113 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_28 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_117 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_29 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_121 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_125 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_31 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_129 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_32 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_133 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_33 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_137 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_34 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_141 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_35 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_145 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_36 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_149 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_37 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_153 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_38 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_157 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_39 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_161 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_40 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_165 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_41 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_169 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_42 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_173 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_43 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_177 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_44 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_181 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_45 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_185 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_46 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_189 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_47 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_193 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_48 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_197 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_49 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_201 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_50 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_205 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_51 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_209 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_52 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_213 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_53 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_217 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_54 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_221 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_55 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_225 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_56 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_229 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_57 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_233 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_58 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_237 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_59 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_241 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_60 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_245 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_61 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_249 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_62 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_253 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_63 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_257 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_64 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_261 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_65 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_265 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_66 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_269 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_67 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_273 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_68 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_277 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_69 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_281 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_70 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_285 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_71 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_289 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_72 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_293 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_73 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_297 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_74 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_301 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_75 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_305 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_76 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_309 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_77 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_313 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_78 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_317 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_79 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_321 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_80 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_325 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_81 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_329 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_82 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_333 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_83 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_337 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_84 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_341 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_85 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_345 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_86 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_349 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_87 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_353 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_88 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_357 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_89 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_361 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_90 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_365 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_91 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_369 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_92 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_373 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_93 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_377 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_94 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_381 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_95 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_385 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_96 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_389 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_97 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_393 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_98 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_397 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_99 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_401 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_100 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_405 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_101 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_409 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_102 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_413 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_103 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_417 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_104 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_421 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_105 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_425 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_106 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_429 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_107 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_433 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_108 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_437 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_109 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_441 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_110 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_445 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_111 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_449 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_112 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_453 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_113 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_457 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_114 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_461 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_115 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_465 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_116 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_469 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_117 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_473 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_118 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_477 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_119 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_481 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_120 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_485 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_121 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_489 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_122 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_493 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_123 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_497 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_124 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_501 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_125 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_505 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_126 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_509 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_127 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_513 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_16 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_17 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_18 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_19 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_20 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_21 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_22 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_23 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_24 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_25 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_26 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_27 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_28 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_29 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_30 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_31 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_32 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_33 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_34 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_35 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_36 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_37 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_38 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_39 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_40 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_41 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_42 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_43 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_44 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_45 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_46 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_47 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_48 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_49 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_50 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_51 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_52 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_53 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_54 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_55 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_56 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_57 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_58 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_59 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_60 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_61 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_62 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_63 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_64 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_65 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_66 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_67 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_68 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_69 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_70 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_71 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_72 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_73 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_74 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_75 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_76 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_77 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_78 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_79 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_80 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_81 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_82 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_83 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_84 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_85 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_86 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_87 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_88 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_89 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_90 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_91 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_92 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_93 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_94 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_95 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_96 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_97 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_98 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_99 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_100 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_101 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_102 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_103 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_104 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_105 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_106 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_107 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_108 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_109 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_110 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_111 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_112 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_113 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_114 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_115 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_116 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_117 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_118 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_119 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_120 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_121 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_122 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_123 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_124 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_125 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_126 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_127 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_34 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_8 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_38 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_42 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_46 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_11 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_50 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_12 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_54 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_58 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_62 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_15 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_66 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_16 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_70 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_74 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_78 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_19 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_82 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_20 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_86 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_21 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_90 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_94 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_23 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_98 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_24 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_102 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_25 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_106 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_110 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_27 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_114 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_28 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_118 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_29 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_122 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_126 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_31 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_130 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_32 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_134 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_33 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_138 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_34 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_142 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_35 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_146 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_36 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_150 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_37 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_154 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_38 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_158 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_39 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_162 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_40 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_166 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_41 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_170 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_42 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_174 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_43 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_178 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_44 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_182 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_45 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_186 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_46 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_190 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_47 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_194 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_48 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_198 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_49 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_202 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_50 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_206 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_51 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_210 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_52 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_214 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_53 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_218 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_54 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_222 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_55 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_226 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_56 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_230 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_57 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_234 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_58 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_238 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_59 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_242 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_60 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_246 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_61 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_250 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_62 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_254 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_63 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_258 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_64 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_262 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_65 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_266 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_66 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_270 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_67 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_274 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_68 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_278 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_69 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_282 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_70 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_286 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_71 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_290 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_72 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_294 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_73 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_298 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_74 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_302 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_75 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_306 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_76 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_310 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_77 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_314 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_78 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_318 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_79 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_322 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_80 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_326 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_81 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_330 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_82 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_334 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_83 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_338 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_84 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_342 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_85 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_346 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_86 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_350 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_87 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_354 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_88 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_358 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_89 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_362 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_90 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_366 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_91 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_370 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_92 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_374 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_93 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_378 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_94 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_382 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_95 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_386 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_96 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_390 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_97 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_394 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_98 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_398 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_99 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_402 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_100 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_406 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_101 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_410 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_102 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_414 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_103 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_418 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_104 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_422 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_105 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_426 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_106 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_430 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_107 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_434 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_108 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_438 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_109 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_442 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_110 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_446 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_111 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_450 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_112 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_454 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_113 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_458 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_114 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_462 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_115 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_466 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_116 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_470 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_117 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_474 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_118 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_478 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_119 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_482 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_120 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_486 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_121 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_490 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_122 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_494 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_123 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_498 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_124 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_502 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_125 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_506 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_126 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_510 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_127 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_514 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_16 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_17 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_18 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_19 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_20 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_21 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_22 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_23 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_24 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_25 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_26 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_27 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_28 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_29 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_30 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_31 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_32 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_33 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_34 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_35 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_36 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_37 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_38 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_39 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_40 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_41 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_42 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_43 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_44 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_45 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_46 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_47 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_48 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_49 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_50 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_51 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_52 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_53 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_54 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_55 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_56 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_57 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_58 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_59 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_60 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_61 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_62 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_63 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_64 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_65 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_66 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_67 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_68 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_69 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_70 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_71 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_72 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_73 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_74 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_75 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_76 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_77 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_78 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_79 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_80 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_81 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_82 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_83 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_84 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_85 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_86 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_87 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_88 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_89 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_90 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_91 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_92 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_93 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_94 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_95 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_96 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_97 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_98 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_99 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_100 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_101 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_102 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_103 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_104 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_105 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_106 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_107 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_108 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_109 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_110 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_111 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_112 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_113 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_114 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_115 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_116 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_117 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_118 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_119 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_120 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_121 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_122 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_123 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_124 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_125 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_126 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_127 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24] wire [1:0] auto_in_d_bits_param = 2'h0; // @[Plic.scala:132:9] wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire auto_in_d_bits_sink = 1'h0; // @[Plic.scala:132:9] wire auto_in_d_bits_denied = 1'h0; // @[Plic.scala:132:9] wire auto_in_d_bits_corrupt = 1'h0; // @[Plic.scala:132:9] wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire _pending_WIRE_0 = 1'h0; // @[Plic.scala:172:55] wire _out_T_79 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_T_80 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_prepend_T_2 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_T_349 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_T_350 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_prepend_T_17 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_T_369 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_T_370 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_prepend_T_18 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_T_389 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_T_390 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_prepend_T_19 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_T_409 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_T_410 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_prepend_T_20 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_T_440 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_T_441 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_prepend_T_22 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_T_460 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_T_461 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_prepend_T_23 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_T_480 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_T_481 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_prepend_T_24 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_T_500 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_T_501 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_prepend_T_25 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_8 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_12 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_16 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_20 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_24 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_28 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_32 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_40 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_44 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_48 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_52 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_56 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_60 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_64 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_100 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_104 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_108 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_112 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_116 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_120 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_124 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_128 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_132 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_136 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_140 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_144 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_148 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_152 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_156 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_160 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_164 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_168 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_172 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_176 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_180 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_184 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_188 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_192 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_196 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_200 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_204 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_208 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_212 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_216 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_220 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_224 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_228 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_232 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_236 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_240 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_244 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_248 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_252 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_256 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_264 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_268 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_272 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_276 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_280 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_284 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_288 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_296 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_300 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_304 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_308 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_312 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_316 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_320 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_328 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_332 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_336 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_340 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_344 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_348 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_352 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_360 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_364 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_368 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_372 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_376 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_380 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_384 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_392 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_396 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_400 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_404 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_408 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_412 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_416 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_424 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_428 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_432 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_436 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_440 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_444 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_448 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_456 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_460 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_464 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_468 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_472 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_476 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_480 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_488 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_492 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_496 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_500 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_504 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_508 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_512 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_514 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_9 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_13 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_17 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_21 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_25 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_29 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_33 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_41 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_45 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_49 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_53 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_57 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_61 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_65 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_101 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_105 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_109 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_113 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_117 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_121 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_125 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_129 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_133 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_137 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_141 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_145 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_149 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_153 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_157 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_161 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_165 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_169 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_173 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_177 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_181 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_185 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_189 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_193 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_197 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_201 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_205 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_209 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_213 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_217 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_221 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_225 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_229 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_233 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_237 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_241 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_245 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_249 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_253 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_257 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_265 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_269 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_273 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_277 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_281 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_285 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_289 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_297 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_301 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_305 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_309 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_313 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_317 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_321 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_329 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_333 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_337 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_341 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_345 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_349 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_353 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_361 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_365 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_369 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_373 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_377 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_381 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_385 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_393 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_397 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_401 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_405 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_409 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_413 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_417 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_425 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_429 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_433 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_437 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_441 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_445 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_449 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_457 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_461 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_465 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_469 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_473 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_477 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_481 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_489 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_493 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_497 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_501 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_505 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_509 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_513 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_515 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_8 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_12 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_16 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_20 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_24 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_28 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_32 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_40 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_44 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_48 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_52 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_56 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_60 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_64 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_100 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_104 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_108 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_112 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_116 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_120 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_124 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_128 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_132 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_136 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_140 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_144 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_148 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_152 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_156 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_160 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_164 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_168 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_172 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_176 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_180 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_184 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_188 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_192 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_196 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_200 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_204 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_208 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_212 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_216 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_220 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_224 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_228 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_232 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_236 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_240 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_244 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_248 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_252 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_256 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_264 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_268 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_272 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_276 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_280 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_284 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_288 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_296 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_300 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_304 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_308 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_312 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_316 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_320 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_328 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_332 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_336 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_340 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_344 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_348 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_352 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_360 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_364 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_368 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_372 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_376 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_380 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_384 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_392 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_396 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_400 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_404 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_408 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_412 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_416 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_424 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_428 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_432 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_436 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_440 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_444 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_448 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_456 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_460 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_464 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_468 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_472 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_476 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_480 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_488 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_492 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_496 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_500 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_504 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_508 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_512 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_514 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_9 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_13 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_17 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_21 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_25 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_29 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_33 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_41 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_45 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_49 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_53 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_57 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_61 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_65 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_101 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_105 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_109 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_113 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_117 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_121 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_125 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_129 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_133 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_137 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_141 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_145 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_149 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_153 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_157 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_161 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_165 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_169 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_173 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_177 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_181 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_185 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_189 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_193 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_197 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_201 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_205 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_209 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_213 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_217 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_221 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_225 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_229 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_233 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_237 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_241 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_245 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_249 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_253 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_257 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_265 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_269 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_273 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_277 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_281 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_285 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_289 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_297 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_301 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_305 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_309 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_313 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_317 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_321 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_329 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_333 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_337 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_341 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_345 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_349 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_353 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_361 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_365 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_369 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_373 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_377 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_381 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_385 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_393 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_397 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_401 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_405 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_409 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_413 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_417 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_425 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_429 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_433 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_437 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_441 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_445 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_449 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_457 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_461 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_465 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_469 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_473 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_477 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_481 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_489 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_493 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_497 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_501 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_505 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_509 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_513 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_515 = 1'h0; // @[MuxLiteral.scala:49:17] wire nodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire nodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire nodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [63:0] nodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire [2:0] nodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [31:0] _out_prepend_T_21 = 32'h0; // @[RegisterRouter.scala:87:24] wire [22:0] out_maskMatch = 23'h7BF18F; // @[RegisterRouter.scala:87:24] wire intnodeIn_0 = auto_int_in_0_0; // @[Plic.scala:132:9] wire x1_intnodeOut_6_0; // @[MixedNode.scala:542:17] wire x1_intnodeOut_5_0; // @[MixedNode.scala:542:17] wire x1_intnodeOut_4_0; // @[MixedNode.scala:542:17] wire x1_intnodeOut_3_0; // @[MixedNode.scala:542:17] wire x1_intnodeOut_2_0; // @[MixedNode.scala:542:17] wire x1_intnodeOut_1_0; // @[MixedNode.scala:542:17] wire x1_intnodeOut_0; // @[MixedNode.scala:542:17] wire intnodeOut_0; // @[MixedNode.scala:542:17] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Plic.scala:132:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Plic.scala:132:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Plic.scala:132:9] wire [1:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Plic.scala:132:9] wire [11:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Plic.scala:132:9] wire [27:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Plic.scala:132:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Plic.scala:132:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Plic.scala:132:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Plic.scala:132:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Plic.scala:132:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [11:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire auto_int_out_7_0_0; // @[Plic.scala:132:9] wire auto_int_out_6_0_0; // @[Plic.scala:132:9] wire auto_int_out_5_0_0; // @[Plic.scala:132:9] wire auto_int_out_4_0_0; // @[Plic.scala:132:9] wire auto_int_out_3_0_0; // @[Plic.scala:132:9] wire auto_int_out_2_0_0; // @[Plic.scala:132:9] wire auto_int_out_1_0_0; // @[Plic.scala:132:9] wire auto_int_out_0_0_0; // @[Plic.scala:132:9] wire auto_in_a_ready_0; // @[Plic.scala:132:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Plic.scala:132:9] wire [1:0] auto_in_d_bits_size_0; // @[Plic.scala:132:9] wire [11:0] auto_in_d_bits_source_0; // @[Plic.scala:132:9] wire [63:0] auto_in_d_bits_data_0; // @[Plic.scala:132:9] wire auto_in_d_valid_0; // @[Plic.scala:132:9] wire in_ready; // @[RegisterRouter.scala:73:18] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Plic.scala:132:9] wire in_valid = nodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = nodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [11:0] in_bits_extra_tlrr_extra_source = nodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = nodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = nodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = nodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Plic.scala:132:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Plic.scala:132:9] wire [1:0] nodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Plic.scala:132:9] wire [11:0] nodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Plic.scala:132:9] wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Plic.scala:132:9] wire _intnodeOut_0_T; // @[Plic.scala:193:60] assign auto_int_out_0_0_0 = intnodeOut_0; // @[Plic.scala:132:9] wire _intnodeOut_0_T_1; // @[Plic.scala:193:60] assign auto_int_out_1_0_0 = x1_intnodeOut_0; // @[Plic.scala:132:9] wire _intnodeOut_0_T_2; // @[Plic.scala:193:60] assign auto_int_out_2_0_0 = x1_intnodeOut_1_0; // @[Plic.scala:132:9] wire _intnodeOut_0_T_3; // @[Plic.scala:193:60] assign auto_int_out_3_0_0 = x1_intnodeOut_2_0; // @[Plic.scala:132:9] wire _intnodeOut_0_T_4; // @[Plic.scala:193:60] assign auto_int_out_4_0_0 = x1_intnodeOut_3_0; // @[Plic.scala:132:9] wire _intnodeOut_0_T_5; // @[Plic.scala:193:60] assign auto_int_out_5_0_0 = x1_intnodeOut_4_0; // @[Plic.scala:132:9] wire _intnodeOut_0_T_6; // @[Plic.scala:193:60] assign auto_int_out_6_0_0 = x1_intnodeOut_5_0; // @[Plic.scala:132:9] wire _intnodeOut_0_T_7; // @[Plic.scala:193:60] assign auto_int_out_7_0_0 = x1_intnodeOut_6_0; // @[Plic.scala:132:9] reg priority_0; // @[Plic.scala:167:31] reg threshold_0; // @[Plic.scala:170:31] wire _out_T_243 = threshold_0; // @[RegisterRouter.scala:87:24] reg threshold_1; // @[Plic.scala:170:31] wire _out_T_135 = threshold_1; // @[RegisterRouter.scala:87:24] reg threshold_2; // @[Plic.scala:170:31] wire _out_T_279 = threshold_2; // @[RegisterRouter.scala:87:24] reg threshold_3; // @[Plic.scala:170:31] wire _out_T_171 = threshold_3; // @[RegisterRouter.scala:87:24] reg threshold_4; // @[Plic.scala:170:31] wire _out_T_99 = threshold_4; // @[RegisterRouter.scala:87:24] reg threshold_5; // @[Plic.scala:170:31] wire _out_T_45 = threshold_5; // @[RegisterRouter.scala:87:24] reg threshold_6; // @[Plic.scala:170:31] wire _out_T_315 = threshold_6; // @[RegisterRouter.scala:87:24] reg threshold_7; // @[Plic.scala:170:31] wire _out_T_207 = threshold_7; // @[RegisterRouter.scala:87:24] reg pending_0; // @[Plic.scala:172:26] reg enables_0_0; // @[Plic.scala:178:26] wire enableVec_0 = enables_0_0; // @[Plic.scala:178:26, :182:28] reg enables_1_0; // @[Plic.scala:178:26] wire enableVec_1 = enables_1_0; // @[Plic.scala:178:26, :182:28] reg enables_2_0; // @[Plic.scala:178:26] wire enableVec_2 = enables_2_0; // @[Plic.scala:178:26, :182:28] reg enables_3_0; // @[Plic.scala:178:26] wire enableVec_3 = enables_3_0; // @[Plic.scala:178:26, :182:28] reg enables_4_0; // @[Plic.scala:178:26] wire enableVec_4 = enables_4_0; // @[Plic.scala:178:26, :182:28] reg enables_5_0; // @[Plic.scala:178:26] wire enableVec_5 = enables_5_0; // @[Plic.scala:178:26, :182:28] reg enables_6_0; // @[Plic.scala:178:26] wire enableVec_6 = enables_6_0; // @[Plic.scala:178:26, :182:28] reg enables_7_0; // @[Plic.scala:178:26] wire enableVec_7 = enables_7_0; // @[Plic.scala:178:26, :182:28] wire [1:0] _enableVec0_T = {enableVec_0, 1'h0}; // @[Plic.scala:182:28, :183:52] wire [1:0] enableVec0_0 = _enableVec0_T; // @[Plic.scala:183:{29,52}] wire [1:0] _enableVec0_T_1 = {enableVec_1, 1'h0}; // @[Plic.scala:182:28, :183:52] wire [1:0] enableVec0_1 = _enableVec0_T_1; // @[Plic.scala:183:{29,52}] wire [1:0] _enableVec0_T_2 = {enableVec_2, 1'h0}; // @[Plic.scala:182:28, :183:52] wire [1:0] enableVec0_2 = _enableVec0_T_2; // @[Plic.scala:183:{29,52}] wire [1:0] _enableVec0_T_3 = {enableVec_3, 1'h0}; // @[Plic.scala:182:28, :183:52] wire [1:0] enableVec0_3 = _enableVec0_T_3; // @[Plic.scala:183:{29,52}] wire [1:0] _enableVec0_T_4 = {enableVec_4, 1'h0}; // @[Plic.scala:182:28, :183:52] wire [1:0] enableVec0_4 = _enableVec0_T_4; // @[Plic.scala:183:{29,52}] wire [1:0] _enableVec0_T_5 = {enableVec_5, 1'h0}; // @[Plic.scala:182:28, :183:52] wire [1:0] enableVec0_5 = _enableVec0_T_5; // @[Plic.scala:183:{29,52}] wire [1:0] _enableVec0_T_6 = {enableVec_6, 1'h0}; // @[Plic.scala:182:28, :183:52] wire [1:0] enableVec0_6 = _enableVec0_T_6; // @[Plic.scala:183:{29,52}] wire [1:0] _enableVec0_T_7 = {enableVec_7, 1'h0}; // @[Plic.scala:182:28, :183:52] wire [1:0] enableVec0_7 = _enableVec0_T_7; // @[Plic.scala:183:{29,52}] reg maxDevs_0; // @[Plic.scala:185:22] reg maxDevs_1; // @[Plic.scala:185:22] reg maxDevs_2; // @[Plic.scala:185:22] reg maxDevs_3; // @[Plic.scala:185:22] reg maxDevs_4; // @[Plic.scala:185:22] reg maxDevs_5; // @[Plic.scala:185:22] reg maxDevs_6; // @[Plic.scala:185:22] reg maxDevs_7; // @[Plic.scala:185:22] wire _fanin_io_ip_T = enableVec_0 & pending_0; // @[Plic.scala:172:26, :182:28, :191:40] reg intnodeOut_0_REG; // @[Plic.scala:193:45] assign _intnodeOut_0_T = intnodeOut_0_REG > threshold_0; // @[Plic.scala:170:31, :193:{45,60}] assign intnodeOut_0 = _intnodeOut_0_T; // @[Plic.scala:193:60] wire _fanin_io_ip_T_1 = enableVec_1 & pending_0; // @[Plic.scala:172:26, :182:28, :191:40] reg intnodeOut_0_REG_1; // @[Plic.scala:193:45] assign _intnodeOut_0_T_1 = intnodeOut_0_REG_1 > threshold_1; // @[Plic.scala:170:31, :193:{45,60}] assign x1_intnodeOut_0 = _intnodeOut_0_T_1; // @[Plic.scala:193:60] wire _fanin_io_ip_T_2 = enableVec_2 & pending_0; // @[Plic.scala:172:26, :182:28, :191:40] reg intnodeOut_0_REG_2; // @[Plic.scala:193:45] assign _intnodeOut_0_T_2 = intnodeOut_0_REG_2 > threshold_2; // @[Plic.scala:170:31, :193:{45,60}] assign x1_intnodeOut_1_0 = _intnodeOut_0_T_2; // @[Plic.scala:193:60] wire _fanin_io_ip_T_3 = enableVec_3 & pending_0; // @[Plic.scala:172:26, :182:28, :191:40] reg intnodeOut_0_REG_3; // @[Plic.scala:193:45] assign _intnodeOut_0_T_3 = intnodeOut_0_REG_3 > threshold_3; // @[Plic.scala:170:31, :193:{45,60}] assign x1_intnodeOut_2_0 = _intnodeOut_0_T_3; // @[Plic.scala:193:60] wire _fanin_io_ip_T_4 = enableVec_4 & pending_0; // @[Plic.scala:172:26, :182:28, :191:40] reg intnodeOut_0_REG_4; // @[Plic.scala:193:45] assign _intnodeOut_0_T_4 = intnodeOut_0_REG_4 > threshold_4; // @[Plic.scala:170:31, :193:{45,60}] assign x1_intnodeOut_3_0 = _intnodeOut_0_T_4; // @[Plic.scala:193:60] wire _fanin_io_ip_T_5 = enableVec_5 & pending_0; // @[Plic.scala:172:26, :182:28, :191:40] reg intnodeOut_0_REG_5; // @[Plic.scala:193:45] assign _intnodeOut_0_T_5 = intnodeOut_0_REG_5 > threshold_5; // @[Plic.scala:170:31, :193:{45,60}] assign x1_intnodeOut_4_0 = _intnodeOut_0_T_5; // @[Plic.scala:193:60] wire _fanin_io_ip_T_6 = enableVec_6 & pending_0; // @[Plic.scala:172:26, :182:28, :191:40] reg intnodeOut_0_REG_6; // @[Plic.scala:193:45] assign _intnodeOut_0_T_6 = intnodeOut_0_REG_6 > threshold_6; // @[Plic.scala:170:31, :193:{45,60}] assign x1_intnodeOut_5_0 = _intnodeOut_0_T_6; // @[Plic.scala:193:60] wire _fanin_io_ip_T_7 = enableVec_7 & pending_0; // @[Plic.scala:172:26, :182:28, :191:40] reg intnodeOut_0_REG_7; // @[Plic.scala:193:45] assign _intnodeOut_0_T_7 = intnodeOut_0_REG_7 > threshold_7; // @[Plic.scala:170:31, :193:{45,60}] assign x1_intnodeOut_6_0 = _intnodeOut_0_T_7; // @[Plic.scala:193:60] wire out_f_roready_19; // @[RegisterRouter.scala:87:24] wire out_f_roready_10; // @[RegisterRouter.scala:87:24] wire out_f_roready_22; // @[RegisterRouter.scala:87:24] wire out_f_roready_13; // @[RegisterRouter.scala:87:24] wire out_f_roready_7; // @[RegisterRouter.scala:87:24] wire out_f_roready_2; // @[RegisterRouter.scala:87:24] wire out_f_roready_25; // @[RegisterRouter.scala:87:24] wire out_f_roready_16; // @[RegisterRouter.scala:87:24] wire claimer_0; // @[Plic.scala:250:23] wire claimer_1; // @[Plic.scala:250:23] wire claimer_2; // @[Plic.scala:250:23] wire claimer_3; // @[Plic.scala:250:23] wire claimer_4; // @[Plic.scala:250:23] wire claimer_5; // @[Plic.scala:250:23] wire claimer_6; // @[Plic.scala:250:23] wire claimer_7; // @[Plic.scala:250:23] wire [1:0] _GEN = {claimer_1, claimer_0}; // @[Plic.scala:250:23, :251:21] wire [1:0] lo_lo; // @[Plic.scala:251:21] assign lo_lo = _GEN; // @[Plic.scala:251:21] wire [1:0] lo_lo_1; // @[Plic.scala:251:39] assign lo_lo_1 = _GEN; // @[Plic.scala:251:{21,39}] wire [1:0] _GEN_0 = {claimer_3, claimer_2}; // @[Plic.scala:250:23, :251:21] wire [1:0] lo_hi; // @[Plic.scala:251:21] assign lo_hi = _GEN_0; // @[Plic.scala:251:21] wire [1:0] lo_hi_1; // @[Plic.scala:251:39] assign lo_hi_1 = _GEN_0; // @[Plic.scala:251:{21,39}] wire [3:0] lo = {lo_hi, lo_lo}; // @[Plic.scala:251:21] wire [1:0] _GEN_1 = {claimer_5, claimer_4}; // @[Plic.scala:250:23, :251:21] wire [1:0] hi_lo; // @[Plic.scala:251:21] assign hi_lo = _GEN_1; // @[Plic.scala:251:21] wire [1:0] hi_lo_1; // @[Plic.scala:251:39] assign hi_lo_1 = _GEN_1; // @[Plic.scala:251:{21,39}] wire [1:0] _GEN_2 = {claimer_7, claimer_6}; // @[Plic.scala:250:23, :251:21] wire [1:0] hi_hi; // @[Plic.scala:251:21] assign hi_hi = _GEN_2; // @[Plic.scala:251:21] wire [1:0] hi_hi_1; // @[Plic.scala:251:39] assign hi_hi_1 = _GEN_2; // @[Plic.scala:251:{21,39}] wire [3:0] hi = {hi_hi, hi_lo}; // @[Plic.scala:251:21] wire [3:0] lo_1 = {lo_hi_1, lo_lo_1}; // @[Plic.scala:251:39] wire [3:0] hi_1 = {hi_hi_1, hi_lo_1}; // @[Plic.scala:251:39] wire _claiming_T = claimer_0 & maxDevs_0; // @[Plic.scala:185:22, :250:23, :252:49] wire _claiming_T_1 = claimer_1 & maxDevs_1; // @[Plic.scala:185:22, :250:23, :252:49] wire _claiming_T_2 = claimer_2 & maxDevs_2; // @[Plic.scala:185:22, :250:23, :252:49] wire _claiming_T_3 = claimer_3 & maxDevs_3; // @[Plic.scala:185:22, :250:23, :252:49] wire _claiming_T_4 = claimer_4 & maxDevs_4; // @[Plic.scala:185:22, :250:23, :252:49] wire _claiming_T_5 = claimer_5 & maxDevs_5; // @[Plic.scala:185:22, :250:23, :252:49] wire _claiming_T_6 = claimer_6 & maxDevs_6; // @[Plic.scala:185:22, :250:23, :252:49] wire _claiming_T_7 = claimer_7 & maxDevs_7; // @[Plic.scala:185:22, :250:23, :252:49] wire _claiming_T_8 = _claiming_T | _claiming_T_1; // @[Plic.scala:252:{49,92}] wire _claiming_T_9 = _claiming_T_8 | _claiming_T_2; // @[Plic.scala:252:{49,92}] wire _claiming_T_10 = _claiming_T_9 | _claiming_T_3; // @[Plic.scala:252:{49,92}] wire _claiming_T_11 = _claiming_T_10 | _claiming_T_4; // @[Plic.scala:252:{49,92}] wire _claiming_T_12 = _claiming_T_11 | _claiming_T_5; // @[Plic.scala:252:{49,92}] wire _claiming_T_13 = _claiming_T_12 | _claiming_T_6; // @[Plic.scala:252:{49,92}] wire claiming = _claiming_T_13 | _claiming_T_7; // @[Plic.scala:252:{49,92}] wire claimedDevs_shiftAmount = claiming; // @[OneHot.scala:64:49] wire [1:0] _claimedDevs_T = 2'h1 << claimedDevs_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [1:0] _claimedDevs_T_1 = _claimedDevs_T; // @[OneHot.scala:65:{12,27}] wire _claimedDevs_T_2 = _claimedDevs_T_1[0]; // @[OneHot.scala:65:27] wire claimedDevs_0 = _claimedDevs_T_2; // @[Plic.scala:253:{30,62}] wire _claimedDevs_T_3 = _claimedDevs_T_1[1]; // @[OneHot.scala:65:27] wire claimedDevs_1 = _claimedDevs_T_3; // @[Plic.scala:253:{30,62}] wire _gateway_io_plic_ready_T = ~pending_0; // @[Plic.scala:172:26, :256:18] wire _pending_0_T = ~claimedDevs_1; // @[Plic.scala:253:30, :257:34] wire _out_completer_0_T_2; // @[Plic.scala:301:35] wire _out_completer_1_T_2; // @[Plic.scala:301:35] wire _out_completer_2_T_2; // @[Plic.scala:301:35] wire _out_completer_3_T_2; // @[Plic.scala:301:35] wire _out_completer_4_T_2; // @[Plic.scala:301:35] wire _out_completer_5_T_2; // @[Plic.scala:301:35] wire _out_completer_6_T_2; // @[Plic.scala:301:35] wire _out_completer_7_T_2; // @[Plic.scala:301:35] wire completer_0; // @[Plic.scala:267:25] wire completer_1; // @[Plic.scala:267:25] wire completer_2; // @[Plic.scala:267:25] wire completer_3; // @[Plic.scala:267:25] wire completer_4; // @[Plic.scala:267:25] wire completer_5; // @[Plic.scala:267:25] wire completer_6; // @[Plic.scala:267:25] wire completer_7; // @[Plic.scala:267:25] wire [1:0] _GEN_3 = {completer_1, completer_0}; // @[Plic.scala:267:25, :268:23] wire [1:0] lo_lo_2; // @[Plic.scala:268:23] assign lo_lo_2 = _GEN_3; // @[Plic.scala:268:23] wire [1:0] lo_lo_3; // @[Plic.scala:268:43] assign lo_lo_3 = _GEN_3; // @[Plic.scala:268:{23,43}] wire [1:0] _GEN_4 = {completer_3, completer_2}; // @[Plic.scala:267:25, :268:23] wire [1:0] lo_hi_2; // @[Plic.scala:268:23] assign lo_hi_2 = _GEN_4; // @[Plic.scala:268:23] wire [1:0] lo_hi_3; // @[Plic.scala:268:43] assign lo_hi_3 = _GEN_4; // @[Plic.scala:268:{23,43}] wire [3:0] lo_2 = {lo_hi_2, lo_lo_2}; // @[Plic.scala:268:23] wire [1:0] _GEN_5 = {completer_5, completer_4}; // @[Plic.scala:267:25, :268:23] wire [1:0] hi_lo_2; // @[Plic.scala:268:23] assign hi_lo_2 = _GEN_5; // @[Plic.scala:268:23] wire [1:0] hi_lo_3; // @[Plic.scala:268:43] assign hi_lo_3 = _GEN_5; // @[Plic.scala:268:{23,43}] wire [1:0] _GEN_6 = {completer_7, completer_6}; // @[Plic.scala:267:25, :268:23] wire [1:0] hi_hi_2; // @[Plic.scala:268:23] assign hi_hi_2 = _GEN_6; // @[Plic.scala:268:23] wire [1:0] hi_hi_3; // @[Plic.scala:268:43] assign hi_hi_3 = _GEN_6; // @[Plic.scala:268:{23,43}] wire [3:0] hi_2 = {hi_hi_2, hi_lo_2}; // @[Plic.scala:268:23] wire [3:0] lo_3 = {lo_hi_3, lo_lo_3}; // @[Plic.scala:268:43] wire [3:0] hi_3 = {hi_hi_3, hi_lo_3}; // @[Plic.scala:268:43] wire _out_completerDev_T_7; // @[package.scala:163:13] wire completerDev; // @[Plic.scala:269:28] wire completedDevs_shiftAmount = completerDev; // @[OneHot.scala:64:49] wire _completedDevs_T = completer_0 | completer_1; // @[Plic.scala:267:25, :270:48] wire _completedDevs_T_1 = _completedDevs_T | completer_2; // @[Plic.scala:267:25, :270:48] wire _completedDevs_T_2 = _completedDevs_T_1 | completer_3; // @[Plic.scala:267:25, :270:48] wire _completedDevs_T_3 = _completedDevs_T_2 | completer_4; // @[Plic.scala:267:25, :270:48] wire _completedDevs_T_4 = _completedDevs_T_3 | completer_5; // @[Plic.scala:267:25, :270:48] wire _completedDevs_T_5 = _completedDevs_T_4 | completer_6; // @[Plic.scala:267:25, :270:48] wire _completedDevs_T_6 = _completedDevs_T_5 | completer_7; // @[Plic.scala:267:25, :270:48] wire [1:0] _completedDevs_T_7 = 2'h1 << completedDevs_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [1:0] _completedDevs_T_8 = _completedDevs_T_7; // @[OneHot.scala:65:{12,27}] wire [1:0] completedDevs = _completedDevs_T_6 ? _completedDevs_T_8 : 2'h0; // @[OneHot.scala:65:27] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign nodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [22:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [11:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = nodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] wire [24:0] _in_bits_index_T = nodeIn_a_bits_address[27:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T[22:0]; // @[RegisterRouter.scala:73:18, :75:19] wire _out_front_q_io_deq_ready_T = out_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign nodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_T_36; // @[RegisterRouter.scala:87:24] wire _nodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign nodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24] wire out_front_valid; // @[RegisterRouter.scala:87:24] wire [22:0] out_findex = out_front_bits_index & 23'h7BF18F; // @[RegisterRouter.scala:87:24] wire [22:0] out_bindex = _out_back_front_q_io_deq_bits_index & 23'h7BF18F; // @[RegisterRouter.scala:87:24] wire _GEN_7 = out_findex == 23'h0; // @[RegisterRouter.scala:87:24] wire _out_T; // @[RegisterRouter.scala:87:24] assign _out_T = _GEN_7; // @[RegisterRouter.scala:87:24] wire _out_T_2; // @[RegisterRouter.scala:87:24] assign _out_T_2 = _GEN_7; // @[RegisterRouter.scala:87:24] wire _out_T_4; // @[RegisterRouter.scala:87:24] assign _out_T_4 = _GEN_7; // @[RegisterRouter.scala:87:24] wire _out_T_6; // @[RegisterRouter.scala:87:24] assign _out_T_6 = _GEN_7; // @[RegisterRouter.scala:87:24] wire _out_T_8; // @[RegisterRouter.scala:87:24] assign _out_T_8 = _GEN_7; // @[RegisterRouter.scala:87:24] wire _out_T_10; // @[RegisterRouter.scala:87:24] assign _out_T_10 = _GEN_7; // @[RegisterRouter.scala:87:24] wire _out_T_12; // @[RegisterRouter.scala:87:24] assign _out_T_12 = _GEN_7; // @[RegisterRouter.scala:87:24] wire _out_T_14; // @[RegisterRouter.scala:87:24] assign _out_T_14 = _GEN_7; // @[RegisterRouter.scala:87:24] wire _out_T_16; // @[RegisterRouter.scala:87:24] assign _out_T_16 = _GEN_7; // @[RegisterRouter.scala:87:24] wire _out_T_18; // @[RegisterRouter.scala:87:24] assign _out_T_18 = _GEN_7; // @[RegisterRouter.scala:87:24] wire _out_T_20; // @[RegisterRouter.scala:87:24] assign _out_T_20 = _GEN_7; // @[RegisterRouter.scala:87:24] wire _out_T_22; // @[RegisterRouter.scala:87:24] assign _out_T_22 = _GEN_7; // @[RegisterRouter.scala:87:24] wire _out_T_24; // @[RegisterRouter.scala:87:24] assign _out_T_24 = _GEN_7; // @[RegisterRouter.scala:87:24] wire _out_T_26; // @[RegisterRouter.scala:87:24] assign _out_T_26 = _GEN_7; // @[RegisterRouter.scala:87:24] wire _out_T_28; // @[RegisterRouter.scala:87:24] assign _out_T_28 = _GEN_7; // @[RegisterRouter.scala:87:24] wire _out_T_30; // @[RegisterRouter.scala:87:24] assign _out_T_30 = _GEN_7; // @[RegisterRouter.scala:87:24] wire _out_T_32; // @[RegisterRouter.scala:87:24] assign _out_T_32 = _GEN_7; // @[RegisterRouter.scala:87:24] wire _out_T_34; // @[RegisterRouter.scala:87:24] assign _out_T_34 = _GEN_7; // @[RegisterRouter.scala:87:24] wire _GEN_8 = out_bindex == 23'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1; // @[RegisterRouter.scala:87:24] assign _out_T_1 = _GEN_8; // @[RegisterRouter.scala:87:24] wire _out_T_3; // @[RegisterRouter.scala:87:24] assign _out_T_3 = _GEN_8; // @[RegisterRouter.scala:87:24] wire _out_T_5; // @[RegisterRouter.scala:87:24] assign _out_T_5 = _GEN_8; // @[RegisterRouter.scala:87:24] wire _out_T_7; // @[RegisterRouter.scala:87:24] assign _out_T_7 = _GEN_8; // @[RegisterRouter.scala:87:24] wire _out_T_9; // @[RegisterRouter.scala:87:24] assign _out_T_9 = _GEN_8; // @[RegisterRouter.scala:87:24] wire _out_T_11; // @[RegisterRouter.scala:87:24] assign _out_T_11 = _GEN_8; // @[RegisterRouter.scala:87:24] wire _out_T_13; // @[RegisterRouter.scala:87:24] assign _out_T_13 = _GEN_8; // @[RegisterRouter.scala:87:24] wire _out_T_15; // @[RegisterRouter.scala:87:24] assign _out_T_15 = _GEN_8; // @[RegisterRouter.scala:87:24] wire _out_T_17; // @[RegisterRouter.scala:87:24] assign _out_T_17 = _GEN_8; // @[RegisterRouter.scala:87:24] wire _out_T_19; // @[RegisterRouter.scala:87:24] assign _out_T_19 = _GEN_8; // @[RegisterRouter.scala:87:24] wire _out_T_21; // @[RegisterRouter.scala:87:24] assign _out_T_21 = _GEN_8; // @[RegisterRouter.scala:87:24] wire _out_T_23; // @[RegisterRouter.scala:87:24] assign _out_T_23 = _GEN_8; // @[RegisterRouter.scala:87:24] wire _out_T_25; // @[RegisterRouter.scala:87:24] assign _out_T_25 = _GEN_8; // @[RegisterRouter.scala:87:24] wire _out_T_27; // @[RegisterRouter.scala:87:24] assign _out_T_27 = _GEN_8; // @[RegisterRouter.scala:87:24] wire _out_T_29; // @[RegisterRouter.scala:87:24] assign _out_T_29 = _GEN_8; // @[RegisterRouter.scala:87:24] wire _out_T_31; // @[RegisterRouter.scala:87:24] assign _out_T_31 = _GEN_8; // @[RegisterRouter.scala:87:24] wire _out_T_33; // @[RegisterRouter.scala:87:24] assign _out_T_33 = _GEN_8; // @[RegisterRouter.scala:87:24] wire _out_T_35; // @[RegisterRouter.scala:87:24] assign _out_T_35 = _GEN_8; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_419; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_35; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_387; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_291; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_355; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_483; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_259; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_323; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_451; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_75; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_91; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_83; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_67; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_95; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_79; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_87; // @[RegisterRouter.scala:87:24] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire out_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_rivalid_7; // @[RegisterRouter.scala:87:24] wire out_rivalid_8; // @[RegisterRouter.scala:87:24] wire out_rivalid_9; // @[RegisterRouter.scala:87:24] wire out_rivalid_10; // @[RegisterRouter.scala:87:24] wire out_rivalid_11; // @[RegisterRouter.scala:87:24] wire out_rivalid_12; // @[RegisterRouter.scala:87:24] wire out_rivalid_13; // @[RegisterRouter.scala:87:24] wire out_rivalid_14; // @[RegisterRouter.scala:87:24] wire out_rivalid_15; // @[RegisterRouter.scala:87:24] wire out_rivalid_16; // @[RegisterRouter.scala:87:24] wire out_rivalid_17; // @[RegisterRouter.scala:87:24] wire out_rivalid_18; // @[RegisterRouter.scala:87:24] wire out_rivalid_19; // @[RegisterRouter.scala:87:24] wire out_rivalid_20; // @[RegisterRouter.scala:87:24] wire out_rivalid_21; // @[RegisterRouter.scala:87:24] wire out_rivalid_22; // @[RegisterRouter.scala:87:24] wire out_rivalid_23; // @[RegisterRouter.scala:87:24] wire out_rivalid_24; // @[RegisterRouter.scala:87:24] wire out_rivalid_25; // @[RegisterRouter.scala:87:24] wire out_rivalid_26; // @[RegisterRouter.scala:87:24] wire out_rivalid_27; // @[RegisterRouter.scala:87:24] wire out_rivalid_28; // @[RegisterRouter.scala:87:24] wire out_rivalid_29; // @[RegisterRouter.scala:87:24] wire out_rivalid_30; // @[RegisterRouter.scala:87:24] wire out_rivalid_31; // @[RegisterRouter.scala:87:24] wire out_rivalid_32; // @[RegisterRouter.scala:87:24] wire out_rivalid_33; // @[RegisterRouter.scala:87:24] wire out_rivalid_34; // @[RegisterRouter.scala:87:24] wire out_rivalid_35; // @[RegisterRouter.scala:87:24] wire out_rivalid_36; // @[RegisterRouter.scala:87:24] wire out_rivalid_37; // @[RegisterRouter.scala:87:24] wire out_rivalid_38; // @[RegisterRouter.scala:87:24] wire out_rivalid_39; // @[RegisterRouter.scala:87:24] wire out_rivalid_40; // @[RegisterRouter.scala:87:24] wire out_rivalid_41; // @[RegisterRouter.scala:87:24] wire out_rivalid_42; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_420; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_36; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_388; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_292; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_356; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_484; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_260; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_324; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_452; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_76; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_92; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_84; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_68; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_96; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_80; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_88; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire out_wivalid_1; // @[RegisterRouter.scala:87:24] wire out_wivalid_2; // @[RegisterRouter.scala:87:24] wire out_wivalid_3; // @[RegisterRouter.scala:87:24] wire out_wivalid_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_5; // @[RegisterRouter.scala:87:24] wire out_wivalid_6; // @[RegisterRouter.scala:87:24] wire out_wivalid_7; // @[RegisterRouter.scala:87:24] wire out_wivalid_8; // @[RegisterRouter.scala:87:24] wire out_wivalid_9; // @[RegisterRouter.scala:87:24] wire out_wivalid_10; // @[RegisterRouter.scala:87:24] wire out_wivalid_11; // @[RegisterRouter.scala:87:24] wire out_wivalid_12; // @[RegisterRouter.scala:87:24] wire out_wivalid_13; // @[RegisterRouter.scala:87:24] wire out_wivalid_14; // @[RegisterRouter.scala:87:24] wire out_wivalid_15; // @[RegisterRouter.scala:87:24] wire out_wivalid_16; // @[RegisterRouter.scala:87:24] wire out_wivalid_17; // @[RegisterRouter.scala:87:24] wire out_wivalid_18; // @[RegisterRouter.scala:87:24] wire out_wivalid_19; // @[RegisterRouter.scala:87:24] wire out_wivalid_20; // @[RegisterRouter.scala:87:24] wire out_wivalid_21; // @[RegisterRouter.scala:87:24] wire out_wivalid_22; // @[RegisterRouter.scala:87:24] wire out_wivalid_23; // @[RegisterRouter.scala:87:24] wire out_wivalid_24; // @[RegisterRouter.scala:87:24] wire out_wivalid_25; // @[RegisterRouter.scala:87:24] wire out_wivalid_26; // @[RegisterRouter.scala:87:24] wire out_wivalid_27; // @[RegisterRouter.scala:87:24] wire out_wivalid_28; // @[RegisterRouter.scala:87:24] wire out_wivalid_29; // @[RegisterRouter.scala:87:24] wire out_wivalid_30; // @[RegisterRouter.scala:87:24] wire out_wivalid_31; // @[RegisterRouter.scala:87:24] wire out_wivalid_32; // @[RegisterRouter.scala:87:24] wire out_wivalid_33; // @[RegisterRouter.scala:87:24] wire out_wivalid_34; // @[RegisterRouter.scala:87:24] wire out_wivalid_35; // @[RegisterRouter.scala:87:24] wire out_wivalid_36; // @[RegisterRouter.scala:87:24] wire out_wivalid_37; // @[RegisterRouter.scala:87:24] wire out_wivalid_38; // @[RegisterRouter.scala:87:24] wire out_wivalid_39; // @[RegisterRouter.scala:87:24] wire out_wivalid_40; // @[RegisterRouter.scala:87:24] wire out_wivalid_41; // @[RegisterRouter.scala:87:24] wire out_wivalid_42; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_419; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_35; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_387; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_291; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_355; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_483; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_259; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_323; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_451; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_75; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_91; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_83; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_67; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_95; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_79; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_87; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire out_roready_1; // @[RegisterRouter.scala:87:24] wire out_roready_2; // @[RegisterRouter.scala:87:24] wire out_roready_3; // @[RegisterRouter.scala:87:24] wire out_roready_4; // @[RegisterRouter.scala:87:24] wire out_roready_5; // @[RegisterRouter.scala:87:24] wire out_roready_6; // @[RegisterRouter.scala:87:24] wire out_roready_7; // @[RegisterRouter.scala:87:24] wire out_roready_8; // @[RegisterRouter.scala:87:24] wire out_roready_9; // @[RegisterRouter.scala:87:24] wire out_roready_10; // @[RegisterRouter.scala:87:24] wire out_roready_11; // @[RegisterRouter.scala:87:24] wire out_roready_12; // @[RegisterRouter.scala:87:24] wire out_roready_13; // @[RegisterRouter.scala:87:24] wire out_roready_14; // @[RegisterRouter.scala:87:24] wire out_roready_15; // @[RegisterRouter.scala:87:24] wire out_roready_16; // @[RegisterRouter.scala:87:24] wire out_roready_17; // @[RegisterRouter.scala:87:24] wire out_roready_18; // @[RegisterRouter.scala:87:24] wire out_roready_19; // @[RegisterRouter.scala:87:24] wire out_roready_20; // @[RegisterRouter.scala:87:24] wire out_roready_21; // @[RegisterRouter.scala:87:24] wire out_roready_22; // @[RegisterRouter.scala:87:24] wire out_roready_23; // @[RegisterRouter.scala:87:24] wire out_roready_24; // @[RegisterRouter.scala:87:24] wire out_roready_25; // @[RegisterRouter.scala:87:24] wire out_roready_26; // @[RegisterRouter.scala:87:24] wire out_roready_27; // @[RegisterRouter.scala:87:24] wire out_roready_28; // @[RegisterRouter.scala:87:24] wire out_roready_29; // @[RegisterRouter.scala:87:24] wire out_roready_30; // @[RegisterRouter.scala:87:24] wire out_roready_31; // @[RegisterRouter.scala:87:24] wire out_roready_32; // @[RegisterRouter.scala:87:24] wire out_roready_33; // @[RegisterRouter.scala:87:24] wire out_roready_34; // @[RegisterRouter.scala:87:24] wire out_roready_35; // @[RegisterRouter.scala:87:24] wire out_roready_36; // @[RegisterRouter.scala:87:24] wire out_roready_37; // @[RegisterRouter.scala:87:24] wire out_roready_38; // @[RegisterRouter.scala:87:24] wire out_roready_39; // @[RegisterRouter.scala:87:24] wire out_roready_40; // @[RegisterRouter.scala:87:24] wire out_roready_41; // @[RegisterRouter.scala:87:24] wire out_roready_42; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_420; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_36; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_388; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_292; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_356; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_484; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_260; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_324; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_452; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_76; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_92; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_84; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_68; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_96; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_80; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_88; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire out_woready_1; // @[RegisterRouter.scala:87:24] wire out_woready_2; // @[RegisterRouter.scala:87:24] wire out_woready_3; // @[RegisterRouter.scala:87:24] wire out_woready_4; // @[RegisterRouter.scala:87:24] wire out_woready_5; // @[RegisterRouter.scala:87:24] wire out_woready_6; // @[RegisterRouter.scala:87:24] wire out_woready_7; // @[RegisterRouter.scala:87:24] wire out_woready_8; // @[RegisterRouter.scala:87:24] wire out_woready_9; // @[RegisterRouter.scala:87:24] wire out_woready_10; // @[RegisterRouter.scala:87:24] wire out_woready_11; // @[RegisterRouter.scala:87:24] wire out_woready_12; // @[RegisterRouter.scala:87:24] wire out_woready_13; // @[RegisterRouter.scala:87:24] wire out_woready_14; // @[RegisterRouter.scala:87:24] wire out_woready_15; // @[RegisterRouter.scala:87:24] wire out_woready_16; // @[RegisterRouter.scala:87:24] wire out_woready_17; // @[RegisterRouter.scala:87:24] wire out_woready_18; // @[RegisterRouter.scala:87:24] wire out_woready_19; // @[RegisterRouter.scala:87:24] wire out_woready_20; // @[RegisterRouter.scala:87:24] wire out_woready_21; // @[RegisterRouter.scala:87:24] wire out_woready_22; // @[RegisterRouter.scala:87:24] wire out_woready_23; // @[RegisterRouter.scala:87:24] wire out_woready_24; // @[RegisterRouter.scala:87:24] wire out_woready_25; // @[RegisterRouter.scala:87:24] wire out_woready_26; // @[RegisterRouter.scala:87:24] wire out_woready_27; // @[RegisterRouter.scala:87:24] wire out_woready_28; // @[RegisterRouter.scala:87:24] wire out_woready_29; // @[RegisterRouter.scala:87:24] wire out_woready_30; // @[RegisterRouter.scala:87:24] wire out_woready_31; // @[RegisterRouter.scala:87:24] wire out_woready_32; // @[RegisterRouter.scala:87:24] wire out_woready_33; // @[RegisterRouter.scala:87:24] wire out_woready_34; // @[RegisterRouter.scala:87:24] wire out_woready_35; // @[RegisterRouter.scala:87:24] wire out_woready_36; // @[RegisterRouter.scala:87:24] wire out_woready_37; // @[RegisterRouter.scala:87:24] wire out_woready_38; // @[RegisterRouter.scala:87:24] wire out_woready_39; // @[RegisterRouter.scala:87:24] wire out_woready_40; // @[RegisterRouter.scala:87:24] wire out_woready_41; // @[RegisterRouter.scala:87:24] wire out_woready_42; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = _out_back_front_q_io_deq_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = _out_back_front_q_io_deq_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = _out_back_front_q_io_deq_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = _out_back_front_q_io_deq_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = _out_back_front_q_io_deq_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = _out_back_front_q_io_deq_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = _out_back_front_q_io_deq_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = _out_back_front_q_io_deq_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire _out_rimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_3 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_3 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_5 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_5 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_8 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_8 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_11 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_11 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_14 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_14 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_17 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_17 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_20 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_20 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_23 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_23 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_26 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_26 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_28 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_28 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_30 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_30 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_32 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_32 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_35 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_35 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_37 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_37 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_39 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_39 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_41 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_41 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire out_rimask = _out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = _out_wimask_T; // @[RegisterRouter.scala:87:24] wire _out_romask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_3 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_3 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_5 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_5 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_8 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_8 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_11 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_11 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_14 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_14 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_17 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_17 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_20 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_20 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_23 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_23 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_26 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_26 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_28 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_28 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_30 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_30 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_32 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_32 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_35 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_35 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_37 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_37 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_39 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_39 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_41 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_41 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire out_romask = _out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = _out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_37 = out_f_rivalid; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_38 = out_f_roready; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_39 = out_f_wivalid; // @[RegisterRouter.scala:87:24] wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_40 = out_f_woready; // @[RegisterRouter.scala:87:24] wire _out_T_36 = _out_back_front_q_io_deq_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_72 = _out_back_front_q_io_deq_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_90 = _out_back_front_q_io_deq_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_126 = _out_back_front_q_io_deq_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_162 = _out_back_front_q_io_deq_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_198 = _out_back_front_q_io_deq_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_234 = _out_back_front_q_io_deq_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_270 = _out_back_front_q_io_deq_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_306 = _out_back_front_q_io_deq_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_342 = _out_back_front_q_io_deq_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_362 = _out_back_front_q_io_deq_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_382 = _out_back_front_q_io_deq_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_402 = _out_back_front_q_io_deq_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_433 = _out_back_front_q_io_deq_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_453 = _out_back_front_q_io_deq_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_473 = _out_back_front_q_io_deq_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_493 = _out_back_front_q_io_deq_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_41 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_42 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_43 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_44 = ~out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_46 = _out_T_45; // @[RegisterRouter.scala:87:24] wire _out_prepend_T = _out_T_46; // @[RegisterRouter.scala:87:24] wire [30:0] _out_rimask_T_1 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_wimask_T_1 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_rimask_T_6 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_wimask_T_6 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_rimask_T_9 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_wimask_T_9 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_rimask_T_12 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_wimask_T_12 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_rimask_T_15 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_wimask_T_15 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_rimask_T_18 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_wimask_T_18 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_rimask_T_21 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_wimask_T_21 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_rimask_T_24 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_wimask_T_24 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24] wire out_rimask_1 = |_out_rimask_T_1; // @[RegisterRouter.scala:87:24] wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24] wire [30:0] _out_romask_T_1 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_womask_T_1 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_romask_T_6 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_womask_T_6 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_romask_T_9 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_womask_T_9 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_romask_T_12 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_womask_T_12 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_romask_T_15 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_womask_T_15 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_romask_T_18 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_womask_T_18 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_romask_T_21 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_womask_T_21 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_romask_T_24 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_womask_T_24 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24] wire out_romask_1 = |_out_romask_T_1; // @[RegisterRouter.scala:87:24] wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_48 = out_f_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_49 = out_f_roready_1; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24] wire out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24] wire [30:0] _out_T_47 = _out_back_front_q_io_deq_bits_data[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_T_101 = _out_back_front_q_io_deq_bits_data[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_T_137 = _out_back_front_q_io_deq_bits_data[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_T_173 = _out_back_front_q_io_deq_bits_data[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_T_209 = _out_back_front_q_io_deq_bits_data[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_T_245 = _out_back_front_q_io_deq_bits_data[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_T_281 = _out_back_front_q_io_deq_bits_data[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_T_317 = _out_back_front_q_io_deq_bits_data[31:1]; // @[RegisterRouter.scala:87:24] wire _out_T_50 = ~out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_51 = ~out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_52 = ~out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_53 = ~out_womask_1; // @[RegisterRouter.scala:87:24] wire [1:0] out_prepend = {1'h0, _out_prepend_T}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_54 = {30'h0, out_prepend}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_55 = _out_T_54; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1 = _out_T_55; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_2 = out_frontMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_2 = out_frontMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_7 = out_frontMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_7 = out_frontMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_10 = out_frontMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_10 = out_frontMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_13 = out_frontMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_13 = out_frontMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_16 = out_frontMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_16 = out_frontMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_19 = out_frontMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_19 = out_frontMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_22 = out_frontMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_22 = out_frontMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_25 = out_frontMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_25 = out_frontMask[63:32]; // @[RegisterRouter.scala:87:24] wire out_rimask_2 = |_out_rimask_T_2; // @[RegisterRouter.scala:87:24] wire out_wimask_2 = &_out_wimask_T_2; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_2 = out_backMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_2 = out_backMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_7 = out_backMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_7 = out_backMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_10 = out_backMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_10 = out_backMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_13 = out_backMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_13 = out_backMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_16 = out_backMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_16 = out_backMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_19 = out_backMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_19 = out_backMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_22 = out_backMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_22 = out_backMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_25 = out_backMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_25 = out_backMask[63:32]; // @[RegisterRouter.scala:87:24] wire out_romask_2 = |_out_romask_T_2; // @[RegisterRouter.scala:87:24] wire out_womask_2 = &_out_womask_T_2; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_62 = out_f_rivalid_2; // @[RegisterRouter.scala:87:24] assign out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24] assign claimer_5 = out_f_roready_2; // @[RegisterRouter.scala:87:24] wire _out_T_63 = out_f_roready_2; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_64 = out_f_wivalid_2; // @[RegisterRouter.scala:87:24] wire out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24] wire _out_T_65 = out_f_woready_2; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_56 = _out_back_front_q_io_deq_bits_data[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_110 = _out_back_front_q_io_deq_bits_data[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_146 = _out_back_front_q_io_deq_bits_data[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_182 = _out_back_front_q_io_deq_bits_data[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_218 = _out_back_front_q_io_deq_bits_data[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_254 = _out_back_front_q_io_deq_bits_data[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_290 = _out_back_front_q_io_deq_bits_data[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_326 = _out_back_front_q_io_deq_bits_data[63:32]; // @[RegisterRouter.scala:87:24] wire _out_T_57 = _out_T_56[0]; // @[package.scala:163:13] wire _out_completerDev_T = _out_T_56[0]; // @[package.scala:163:13] wire _out_T_58 = completerDev == _out_T_57; // @[package.scala:163:13] wire _out_T_60 = ~_out_T_59; // @[Plic.scala:298:19] wire _out_T_61 = ~_out_T_58; // @[Plic.scala:298:{19,33}] wire [1:0] _GEN_9 = {1'h0, completerDev}; // @[Plic.scala:269:28, :301:51] wire [1:0] _out_completer_5_T = enableVec0_5 >> _GEN_9; // @[Plic.scala:183:29, :301:51] wire _out_completer_5_T_1 = _out_completer_5_T[0]; // @[Plic.scala:301:51] assign _out_completer_5_T_2 = out_f_woready_2 & _out_completer_5_T_1; // @[RegisterRouter.scala:87:24] assign completer_5 = _out_completer_5_T_2; // @[Plic.scala:267:25, :301:35] wire _out_T_66 = ~out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_67 = ~out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_68 = ~out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_69 = ~out_womask_2; // @[RegisterRouter.scala:87:24] wire [32:0] out_prepend_1 = {maxDevs_5, _out_prepend_T_1}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_70 = {31'h0, out_prepend_1}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_71 = _out_T_70; // @[RegisterRouter.scala:87:24] wire out_rimask_3 = _out_rimask_T_3; // @[RegisterRouter.scala:87:24] wire out_wimask_3 = _out_wimask_T_3; // @[RegisterRouter.scala:87:24] wire out_romask_3 = _out_romask_T_3; // @[RegisterRouter.scala:87:24] wire out_womask_3 = _out_womask_T_3; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_73 = out_f_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_74 = out_f_roready_3; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24] wire out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24] wire _out_T_75 = ~out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_76 = ~out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_77 = ~out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_78 = ~out_womask_3; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_4 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_4 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_27 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_27 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_29 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_29 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_31 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_31 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_33 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_33 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_36 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_36 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_38 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_38 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_40 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_40 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_42 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_42 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire out_rimask_4 = _out_rimask_T_4; // @[RegisterRouter.scala:87:24] wire out_wimask_4 = _out_wimask_T_4; // @[RegisterRouter.scala:87:24] wire _out_romask_T_4 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_4 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_27 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_27 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_29 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_29 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_31 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_31 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_33 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_33 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_36 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_36 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_38 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_38 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_40 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_40 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_42 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_42 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire out_romask_4 = _out_romask_T_4; // @[RegisterRouter.scala:87:24] wire out_womask_4 = _out_womask_T_4; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_82 = out_f_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_83 = out_f_roready_4; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24] wire out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24] wire _out_T_81 = _out_back_front_q_io_deq_bits_data[1]; // @[RegisterRouter.scala:87:24] wire _out_T_351 = _out_back_front_q_io_deq_bits_data[1]; // @[RegisterRouter.scala:87:24] wire _out_T_371 = _out_back_front_q_io_deq_bits_data[1]; // @[RegisterRouter.scala:87:24] wire _out_T_391 = _out_back_front_q_io_deq_bits_data[1]; // @[RegisterRouter.scala:87:24] wire _out_T_411 = _out_back_front_q_io_deq_bits_data[1]; // @[RegisterRouter.scala:87:24] wire _out_T_442 = _out_back_front_q_io_deq_bits_data[1]; // @[RegisterRouter.scala:87:24] wire _out_T_462 = _out_back_front_q_io_deq_bits_data[1]; // @[RegisterRouter.scala:87:24] wire _out_T_482 = _out_back_front_q_io_deq_bits_data[1]; // @[RegisterRouter.scala:87:24] wire _out_T_502 = _out_back_front_q_io_deq_bits_data[1]; // @[RegisterRouter.scala:87:24] wire _out_T_84 = ~out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_85 = ~out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_86 = ~out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_87 = ~out_womask_4; // @[RegisterRouter.scala:87:24] wire [1:0] out_prepend_2 = {pending_0, 1'h0}; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_88 = out_prepend_2; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_89 = _out_T_88; // @[RegisterRouter.scala:87:24] wire out_rimask_5 = _out_rimask_T_5; // @[RegisterRouter.scala:87:24] wire out_wimask_5 = _out_wimask_T_5; // @[RegisterRouter.scala:87:24] wire out_romask_5 = _out_romask_T_5; // @[RegisterRouter.scala:87:24] wire out_womask_5 = _out_womask_T_5; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_91 = out_f_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_92 = out_f_roready_5; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_93 = out_f_wivalid_5; // @[RegisterRouter.scala:87:24] wire out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24] wire _out_T_94 = out_f_woready_5; // @[RegisterRouter.scala:87:24] wire _out_T_95 = ~out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_96 = ~out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_97 = ~out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_98 = ~out_womask_5; // @[RegisterRouter.scala:87:24] wire _out_T_100 = _out_T_99; // @[RegisterRouter.scala:87:24] wire _out_prepend_T_3 = _out_T_100; // @[RegisterRouter.scala:87:24] wire out_rimask_6 = |_out_rimask_T_6; // @[RegisterRouter.scala:87:24] wire out_wimask_6 = &_out_wimask_T_6; // @[RegisterRouter.scala:87:24] wire out_romask_6 = |_out_romask_T_6; // @[RegisterRouter.scala:87:24] wire out_womask_6 = &_out_womask_T_6; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_6 = out_rivalid_6 & out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_102 = out_f_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_f_roready_6 = out_roready_6 & out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_103 = out_f_roready_6; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_6 = out_wivalid_6 & out_wimask_6; // @[RegisterRouter.scala:87:24] wire out_f_woready_6 = out_woready_6 & out_womask_6; // @[RegisterRouter.scala:87:24] wire _out_T_104 = ~out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_105 = ~out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_106 = ~out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_107 = ~out_womask_6; // @[RegisterRouter.scala:87:24] wire [1:0] out_prepend_3 = {1'h0, _out_prepend_T_3}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_108 = {30'h0, out_prepend_3}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_109 = _out_T_108; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_4 = _out_T_109; // @[RegisterRouter.scala:87:24] wire out_rimask_7 = |_out_rimask_T_7; // @[RegisterRouter.scala:87:24] wire out_wimask_7 = &_out_wimask_T_7; // @[RegisterRouter.scala:87:24] wire out_romask_7 = |_out_romask_T_7; // @[RegisterRouter.scala:87:24] wire out_womask_7 = &_out_womask_T_7; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_7 = out_rivalid_7 & out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_116 = out_f_rivalid_7; // @[RegisterRouter.scala:87:24] assign out_f_roready_7 = out_roready_7 & out_romask_7; // @[RegisterRouter.scala:87:24] assign claimer_4 = out_f_roready_7; // @[RegisterRouter.scala:87:24] wire _out_T_117 = out_f_roready_7; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_7 = out_wivalid_7 & out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_118 = out_f_wivalid_7; // @[RegisterRouter.scala:87:24] wire out_f_woready_7 = out_woready_7 & out_womask_7; // @[RegisterRouter.scala:87:24] wire _out_T_119 = out_f_woready_7; // @[RegisterRouter.scala:87:24] wire _out_T_111 = _out_T_110[0]; // @[package.scala:163:13] wire _out_completerDev_T_1 = _out_T_110[0]; // @[package.scala:163:13] wire _out_T_112 = completerDev == _out_T_111; // @[package.scala:163:13] wire _out_T_114 = ~_out_T_113; // @[Plic.scala:298:19] wire _out_T_115 = ~_out_T_112; // @[Plic.scala:298:{19,33}] wire [1:0] _out_completer_4_T = enableVec0_4 >> _GEN_9; // @[Plic.scala:183:29, :301:51] wire _out_completer_4_T_1 = _out_completer_4_T[0]; // @[Plic.scala:301:51] assign _out_completer_4_T_2 = out_f_woready_7 & _out_completer_4_T_1; // @[RegisterRouter.scala:87:24] assign completer_4 = _out_completer_4_T_2; // @[Plic.scala:267:25, :301:35] wire _out_T_120 = ~out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_121 = ~out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_122 = ~out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_123 = ~out_womask_7; // @[RegisterRouter.scala:87:24] wire [32:0] out_prepend_4 = {maxDevs_4, _out_prepend_T_4}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_124 = {31'h0, out_prepend_4}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_125 = _out_T_124; // @[RegisterRouter.scala:87:24] wire out_rimask_8 = _out_rimask_T_8; // @[RegisterRouter.scala:87:24] wire out_wimask_8 = _out_wimask_T_8; // @[RegisterRouter.scala:87:24] wire out_romask_8 = _out_romask_T_8; // @[RegisterRouter.scala:87:24] wire out_womask_8 = _out_womask_T_8; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_8 = out_rivalid_8 & out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_127 = out_f_rivalid_8; // @[RegisterRouter.scala:87:24] wire out_f_roready_8 = out_roready_8 & out_romask_8; // @[RegisterRouter.scala:87:24] wire _out_T_128 = out_f_roready_8; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_8 = out_wivalid_8 & out_wimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_129 = out_f_wivalid_8; // @[RegisterRouter.scala:87:24] wire out_f_woready_8 = out_woready_8 & out_womask_8; // @[RegisterRouter.scala:87:24] wire _out_T_130 = out_f_woready_8; // @[RegisterRouter.scala:87:24] wire _out_T_131 = ~out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_132 = ~out_wimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_133 = ~out_romask_8; // @[RegisterRouter.scala:87:24] wire _out_T_134 = ~out_womask_8; // @[RegisterRouter.scala:87:24] wire _out_T_136 = _out_T_135; // @[RegisterRouter.scala:87:24] wire _out_prepend_T_5 = _out_T_136; // @[RegisterRouter.scala:87:24] wire out_rimask_9 = |_out_rimask_T_9; // @[RegisterRouter.scala:87:24] wire out_wimask_9 = &_out_wimask_T_9; // @[RegisterRouter.scala:87:24] wire out_romask_9 = |_out_romask_T_9; // @[RegisterRouter.scala:87:24] wire out_womask_9 = &_out_womask_T_9; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_9 = out_rivalid_9 & out_rimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_138 = out_f_rivalid_9; // @[RegisterRouter.scala:87:24] wire out_f_roready_9 = out_roready_9 & out_romask_9; // @[RegisterRouter.scala:87:24] wire _out_T_139 = out_f_roready_9; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_9 = out_wivalid_9 & out_wimask_9; // @[RegisterRouter.scala:87:24] wire out_f_woready_9 = out_woready_9 & out_womask_9; // @[RegisterRouter.scala:87:24] wire _out_T_140 = ~out_rimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_141 = ~out_wimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_142 = ~out_romask_9; // @[RegisterRouter.scala:87:24] wire _out_T_143 = ~out_womask_9; // @[RegisterRouter.scala:87:24] wire [1:0] out_prepend_5 = {1'h0, _out_prepend_T_5}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_144 = {30'h0, out_prepend_5}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_145 = _out_T_144; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_6 = _out_T_145; // @[RegisterRouter.scala:87:24] wire out_rimask_10 = |_out_rimask_T_10; // @[RegisterRouter.scala:87:24] wire out_wimask_10 = &_out_wimask_T_10; // @[RegisterRouter.scala:87:24] wire out_romask_10 = |_out_romask_T_10; // @[RegisterRouter.scala:87:24] wire out_womask_10 = &_out_womask_T_10; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_10 = out_rivalid_10 & out_rimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_152 = out_f_rivalid_10; // @[RegisterRouter.scala:87:24] assign out_f_roready_10 = out_roready_10 & out_romask_10; // @[RegisterRouter.scala:87:24] assign claimer_1 = out_f_roready_10; // @[RegisterRouter.scala:87:24] wire _out_T_153 = out_f_roready_10; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_10 = out_wivalid_10 & out_wimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_154 = out_f_wivalid_10; // @[RegisterRouter.scala:87:24] wire out_f_woready_10 = out_woready_10 & out_womask_10; // @[RegisterRouter.scala:87:24] wire _out_T_155 = out_f_woready_10; // @[RegisterRouter.scala:87:24] wire _out_T_147 = _out_T_146[0]; // @[package.scala:163:13] wire _out_completerDev_T_2 = _out_T_146[0]; // @[package.scala:163:13] wire _out_T_148 = completerDev == _out_T_147; // @[package.scala:163:13] wire _out_T_150 = ~_out_T_149; // @[Plic.scala:298:19] wire _out_T_151 = ~_out_T_148; // @[Plic.scala:298:{19,33}] wire [1:0] _out_completer_1_T = enableVec0_1 >> _GEN_9; // @[Plic.scala:183:29, :301:51] wire _out_completer_1_T_1 = _out_completer_1_T[0]; // @[Plic.scala:301:51] assign _out_completer_1_T_2 = out_f_woready_10 & _out_completer_1_T_1; // @[RegisterRouter.scala:87:24] assign completer_1 = _out_completer_1_T_2; // @[Plic.scala:267:25, :301:35] wire _out_T_156 = ~out_rimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_157 = ~out_wimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_158 = ~out_romask_10; // @[RegisterRouter.scala:87:24] wire _out_T_159 = ~out_womask_10; // @[RegisterRouter.scala:87:24] wire [32:0] out_prepend_6 = {maxDevs_1, _out_prepend_T_6}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_160 = {31'h0, out_prepend_6}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_161 = _out_T_160; // @[RegisterRouter.scala:87:24] wire out_rimask_11 = _out_rimask_T_11; // @[RegisterRouter.scala:87:24] wire out_wimask_11 = _out_wimask_T_11; // @[RegisterRouter.scala:87:24] wire out_romask_11 = _out_romask_T_11; // @[RegisterRouter.scala:87:24] wire out_womask_11 = _out_womask_T_11; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_11 = out_rivalid_11 & out_rimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_163 = out_f_rivalid_11; // @[RegisterRouter.scala:87:24] wire out_f_roready_11 = out_roready_11 & out_romask_11; // @[RegisterRouter.scala:87:24] wire _out_T_164 = out_f_roready_11; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_11 = out_wivalid_11 & out_wimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_165 = out_f_wivalid_11; // @[RegisterRouter.scala:87:24] wire out_f_woready_11 = out_woready_11 & out_womask_11; // @[RegisterRouter.scala:87:24] wire _out_T_166 = out_f_woready_11; // @[RegisterRouter.scala:87:24] wire _out_T_167 = ~out_rimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_168 = ~out_wimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_169 = ~out_romask_11; // @[RegisterRouter.scala:87:24] wire _out_T_170 = ~out_womask_11; // @[RegisterRouter.scala:87:24] wire _out_T_172 = _out_T_171; // @[RegisterRouter.scala:87:24] wire _out_prepend_T_7 = _out_T_172; // @[RegisterRouter.scala:87:24] wire out_rimask_12 = |_out_rimask_T_12; // @[RegisterRouter.scala:87:24] wire out_wimask_12 = &_out_wimask_T_12; // @[RegisterRouter.scala:87:24] wire out_romask_12 = |_out_romask_T_12; // @[RegisterRouter.scala:87:24] wire out_womask_12 = &_out_womask_T_12; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_12 = out_rivalid_12 & out_rimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_174 = out_f_rivalid_12; // @[RegisterRouter.scala:87:24] wire out_f_roready_12 = out_roready_12 & out_romask_12; // @[RegisterRouter.scala:87:24] wire _out_T_175 = out_f_roready_12; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_12 = out_wivalid_12 & out_wimask_12; // @[RegisterRouter.scala:87:24] wire out_f_woready_12 = out_woready_12 & out_womask_12; // @[RegisterRouter.scala:87:24] wire _out_T_176 = ~out_rimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_177 = ~out_wimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_178 = ~out_romask_12; // @[RegisterRouter.scala:87:24] wire _out_T_179 = ~out_womask_12; // @[RegisterRouter.scala:87:24] wire [1:0] out_prepend_7 = {1'h0, _out_prepend_T_7}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_180 = {30'h0, out_prepend_7}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_181 = _out_T_180; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_8 = _out_T_181; // @[RegisterRouter.scala:87:24] wire out_rimask_13 = |_out_rimask_T_13; // @[RegisterRouter.scala:87:24] wire out_wimask_13 = &_out_wimask_T_13; // @[RegisterRouter.scala:87:24] wire out_romask_13 = |_out_romask_T_13; // @[RegisterRouter.scala:87:24] wire out_womask_13 = &_out_womask_T_13; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_13 = out_rivalid_13 & out_rimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_188 = out_f_rivalid_13; // @[RegisterRouter.scala:87:24] assign out_f_roready_13 = out_roready_13 & out_romask_13; // @[RegisterRouter.scala:87:24] assign claimer_3 = out_f_roready_13; // @[RegisterRouter.scala:87:24] wire _out_T_189 = out_f_roready_13; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_13 = out_wivalid_13 & out_wimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_190 = out_f_wivalid_13; // @[RegisterRouter.scala:87:24] wire out_f_woready_13 = out_woready_13 & out_womask_13; // @[RegisterRouter.scala:87:24] wire _out_T_191 = out_f_woready_13; // @[RegisterRouter.scala:87:24] wire _out_T_183 = _out_T_182[0]; // @[package.scala:163:13] wire _out_completerDev_T_3 = _out_T_182[0]; // @[package.scala:163:13] wire _out_T_184 = completerDev == _out_T_183; // @[package.scala:163:13] wire _out_T_186 = ~_out_T_185; // @[Plic.scala:298:19] wire _out_T_187 = ~_out_T_184; // @[Plic.scala:298:{19,33}] wire [1:0] _out_completer_3_T = enableVec0_3 >> _GEN_9; // @[Plic.scala:183:29, :301:51] wire _out_completer_3_T_1 = _out_completer_3_T[0]; // @[Plic.scala:301:51] assign _out_completer_3_T_2 = out_f_woready_13 & _out_completer_3_T_1; // @[RegisterRouter.scala:87:24] assign completer_3 = _out_completer_3_T_2; // @[Plic.scala:267:25, :301:35] wire _out_T_192 = ~out_rimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_193 = ~out_wimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_194 = ~out_romask_13; // @[RegisterRouter.scala:87:24] wire _out_T_195 = ~out_womask_13; // @[RegisterRouter.scala:87:24] wire [32:0] out_prepend_8 = {maxDevs_3, _out_prepend_T_8}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_196 = {31'h0, out_prepend_8}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_197 = _out_T_196; // @[RegisterRouter.scala:87:24] wire out_rimask_14 = _out_rimask_T_14; // @[RegisterRouter.scala:87:24] wire out_wimask_14 = _out_wimask_T_14; // @[RegisterRouter.scala:87:24] wire out_romask_14 = _out_romask_T_14; // @[RegisterRouter.scala:87:24] wire out_womask_14 = _out_womask_T_14; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_14 = out_rivalid_14 & out_rimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_199 = out_f_rivalid_14; // @[RegisterRouter.scala:87:24] wire out_f_roready_14 = out_roready_14 & out_romask_14; // @[RegisterRouter.scala:87:24] wire _out_T_200 = out_f_roready_14; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_14 = out_wivalid_14 & out_wimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_201 = out_f_wivalid_14; // @[RegisterRouter.scala:87:24] wire out_f_woready_14 = out_woready_14 & out_womask_14; // @[RegisterRouter.scala:87:24] wire _out_T_202 = out_f_woready_14; // @[RegisterRouter.scala:87:24] wire _out_T_203 = ~out_rimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_204 = ~out_wimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_205 = ~out_romask_14; // @[RegisterRouter.scala:87:24] wire _out_T_206 = ~out_womask_14; // @[RegisterRouter.scala:87:24] wire _out_T_208 = _out_T_207; // @[RegisterRouter.scala:87:24] wire _out_prepend_T_9 = _out_T_208; // @[RegisterRouter.scala:87:24] wire out_rimask_15 = |_out_rimask_T_15; // @[RegisterRouter.scala:87:24] wire out_wimask_15 = &_out_wimask_T_15; // @[RegisterRouter.scala:87:24] wire out_romask_15 = |_out_romask_T_15; // @[RegisterRouter.scala:87:24] wire out_womask_15 = &_out_womask_T_15; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_15 = out_rivalid_15 & out_rimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_210 = out_f_rivalid_15; // @[RegisterRouter.scala:87:24] wire out_f_roready_15 = out_roready_15 & out_romask_15; // @[RegisterRouter.scala:87:24] wire _out_T_211 = out_f_roready_15; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_15 = out_wivalid_15 & out_wimask_15; // @[RegisterRouter.scala:87:24] wire out_f_woready_15 = out_woready_15 & out_womask_15; // @[RegisterRouter.scala:87:24] wire _out_T_212 = ~out_rimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_213 = ~out_wimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_214 = ~out_romask_15; // @[RegisterRouter.scala:87:24] wire _out_T_215 = ~out_womask_15; // @[RegisterRouter.scala:87:24] wire [1:0] out_prepend_9 = {1'h0, _out_prepend_T_9}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_216 = {30'h0, out_prepend_9}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_217 = _out_T_216; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_10 = _out_T_217; // @[RegisterRouter.scala:87:24] wire out_rimask_16 = |_out_rimask_T_16; // @[RegisterRouter.scala:87:24] wire out_wimask_16 = &_out_wimask_T_16; // @[RegisterRouter.scala:87:24] wire out_romask_16 = |_out_romask_T_16; // @[RegisterRouter.scala:87:24] wire out_womask_16 = &_out_womask_T_16; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_16 = out_rivalid_16 & out_rimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_224 = out_f_rivalid_16; // @[RegisterRouter.scala:87:24] assign out_f_roready_16 = out_roready_16 & out_romask_16; // @[RegisterRouter.scala:87:24] assign claimer_7 = out_f_roready_16; // @[RegisterRouter.scala:87:24] wire _out_T_225 = out_f_roready_16; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_16 = out_wivalid_16 & out_wimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_226 = out_f_wivalid_16; // @[RegisterRouter.scala:87:24] wire out_f_woready_16 = out_woready_16 & out_womask_16; // @[RegisterRouter.scala:87:24] wire _out_T_227 = out_f_woready_16; // @[RegisterRouter.scala:87:24] wire _out_T_219 = _out_T_218[0]; // @[package.scala:163:13] wire _out_completerDev_T_4 = _out_T_218[0]; // @[package.scala:163:13] wire _out_T_220 = completerDev == _out_T_219; // @[package.scala:163:13] wire _out_T_222 = ~_out_T_221; // @[Plic.scala:298:19] wire _out_T_223 = ~_out_T_220; // @[Plic.scala:298:{19,33}] wire [1:0] _out_completer_7_T = enableVec0_7 >> _GEN_9; // @[Plic.scala:183:29, :301:51] wire _out_completer_7_T_1 = _out_completer_7_T[0]; // @[Plic.scala:301:51] assign _out_completer_7_T_2 = out_f_woready_16 & _out_completer_7_T_1; // @[RegisterRouter.scala:87:24] assign completer_7 = _out_completer_7_T_2; // @[Plic.scala:267:25, :301:35] wire _out_T_228 = ~out_rimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_229 = ~out_wimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_230 = ~out_romask_16; // @[RegisterRouter.scala:87:24] wire _out_T_231 = ~out_womask_16; // @[RegisterRouter.scala:87:24] wire [32:0] out_prepend_10 = {maxDevs_7, _out_prepend_T_10}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_232 = {31'h0, out_prepend_10}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_233 = _out_T_232; // @[RegisterRouter.scala:87:24] wire out_rimask_17 = _out_rimask_T_17; // @[RegisterRouter.scala:87:24] wire out_wimask_17 = _out_wimask_T_17; // @[RegisterRouter.scala:87:24] wire out_romask_17 = _out_romask_T_17; // @[RegisterRouter.scala:87:24] wire out_womask_17 = _out_womask_T_17; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_17 = out_rivalid_17 & out_rimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_235 = out_f_rivalid_17; // @[RegisterRouter.scala:87:24] wire out_f_roready_17 = out_roready_17 & out_romask_17; // @[RegisterRouter.scala:87:24] wire _out_T_236 = out_f_roready_17; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_17 = out_wivalid_17 & out_wimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_237 = out_f_wivalid_17; // @[RegisterRouter.scala:87:24] wire out_f_woready_17 = out_woready_17 & out_womask_17; // @[RegisterRouter.scala:87:24] wire _out_T_238 = out_f_woready_17; // @[RegisterRouter.scala:87:24] wire _out_T_239 = ~out_rimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_240 = ~out_wimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_241 = ~out_romask_17; // @[RegisterRouter.scala:87:24] wire _out_T_242 = ~out_womask_17; // @[RegisterRouter.scala:87:24] wire _out_T_244 = _out_T_243; // @[RegisterRouter.scala:87:24] wire _out_prepend_T_11 = _out_T_244; // @[RegisterRouter.scala:87:24] wire out_rimask_18 = |_out_rimask_T_18; // @[RegisterRouter.scala:87:24] wire out_wimask_18 = &_out_wimask_T_18; // @[RegisterRouter.scala:87:24] wire out_romask_18 = |_out_romask_T_18; // @[RegisterRouter.scala:87:24] wire out_womask_18 = &_out_womask_T_18; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_18 = out_rivalid_18 & out_rimask_18; // @[RegisterRouter.scala:87:24] wire _out_T_246 = out_f_rivalid_18; // @[RegisterRouter.scala:87:24] wire out_f_roready_18 = out_roready_18 & out_romask_18; // @[RegisterRouter.scala:87:24] wire _out_T_247 = out_f_roready_18; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_18 = out_wivalid_18 & out_wimask_18; // @[RegisterRouter.scala:87:24] wire out_f_woready_18 = out_woready_18 & out_womask_18; // @[RegisterRouter.scala:87:24] wire _out_T_248 = ~out_rimask_18; // @[RegisterRouter.scala:87:24] wire _out_T_249 = ~out_wimask_18; // @[RegisterRouter.scala:87:24] wire _out_T_250 = ~out_romask_18; // @[RegisterRouter.scala:87:24] wire _out_T_251 = ~out_womask_18; // @[RegisterRouter.scala:87:24] wire [1:0] out_prepend_11 = {1'h0, _out_prepend_T_11}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_252 = {30'h0, out_prepend_11}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_253 = _out_T_252; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_12 = _out_T_253; // @[RegisterRouter.scala:87:24] wire out_rimask_19 = |_out_rimask_T_19; // @[RegisterRouter.scala:87:24] wire out_wimask_19 = &_out_wimask_T_19; // @[RegisterRouter.scala:87:24] wire out_romask_19 = |_out_romask_T_19; // @[RegisterRouter.scala:87:24] wire out_womask_19 = &_out_womask_T_19; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_19 = out_rivalid_19 & out_rimask_19; // @[RegisterRouter.scala:87:24] wire _out_T_260 = out_f_rivalid_19; // @[RegisterRouter.scala:87:24] assign out_f_roready_19 = out_roready_19 & out_romask_19; // @[RegisterRouter.scala:87:24] assign claimer_0 = out_f_roready_19; // @[RegisterRouter.scala:87:24] wire _out_T_261 = out_f_roready_19; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_19 = out_wivalid_19 & out_wimask_19; // @[RegisterRouter.scala:87:24] wire _out_T_262 = out_f_wivalid_19; // @[RegisterRouter.scala:87:24] wire out_f_woready_19 = out_woready_19 & out_womask_19; // @[RegisterRouter.scala:87:24] wire _out_T_263 = out_f_woready_19; // @[RegisterRouter.scala:87:24] wire _out_T_255 = _out_T_254[0]; // @[package.scala:163:13] wire _out_completerDev_T_5 = _out_T_254[0]; // @[package.scala:163:13] wire _out_T_256 = completerDev == _out_T_255; // @[package.scala:163:13] wire _out_T_258 = ~_out_T_257; // @[Plic.scala:298:19] wire _out_T_259 = ~_out_T_256; // @[Plic.scala:298:{19,33}] wire [1:0] _out_completer_0_T = enableVec0_0 >> _GEN_9; // @[Plic.scala:183:29, :301:51] wire _out_completer_0_T_1 = _out_completer_0_T[0]; // @[Plic.scala:301:51] assign _out_completer_0_T_2 = out_f_woready_19 & _out_completer_0_T_1; // @[RegisterRouter.scala:87:24] assign completer_0 = _out_completer_0_T_2; // @[Plic.scala:267:25, :301:35] wire _out_T_264 = ~out_rimask_19; // @[RegisterRouter.scala:87:24] wire _out_T_265 = ~out_wimask_19; // @[RegisterRouter.scala:87:24] wire _out_T_266 = ~out_romask_19; // @[RegisterRouter.scala:87:24] wire _out_T_267 = ~out_womask_19; // @[RegisterRouter.scala:87:24] wire [32:0] out_prepend_12 = {maxDevs_0, _out_prepend_T_12}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_268 = {31'h0, out_prepend_12}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_269 = _out_T_268; // @[RegisterRouter.scala:87:24] wire out_rimask_20 = _out_rimask_T_20; // @[RegisterRouter.scala:87:24] wire out_wimask_20 = _out_wimask_T_20; // @[RegisterRouter.scala:87:24] wire out_romask_20 = _out_romask_T_20; // @[RegisterRouter.scala:87:24] wire out_womask_20 = _out_womask_T_20; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_20 = out_rivalid_20 & out_rimask_20; // @[RegisterRouter.scala:87:24] wire _out_T_271 = out_f_rivalid_20; // @[RegisterRouter.scala:87:24] wire out_f_roready_20 = out_roready_20 & out_romask_20; // @[RegisterRouter.scala:87:24] wire _out_T_272 = out_f_roready_20; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_20 = out_wivalid_20 & out_wimask_20; // @[RegisterRouter.scala:87:24] wire _out_T_273 = out_f_wivalid_20; // @[RegisterRouter.scala:87:24] wire out_f_woready_20 = out_woready_20 & out_womask_20; // @[RegisterRouter.scala:87:24] wire _out_T_274 = out_f_woready_20; // @[RegisterRouter.scala:87:24] wire _out_T_275 = ~out_rimask_20; // @[RegisterRouter.scala:87:24] wire _out_T_276 = ~out_wimask_20; // @[RegisterRouter.scala:87:24] wire _out_T_277 = ~out_romask_20; // @[RegisterRouter.scala:87:24] wire _out_T_278 = ~out_womask_20; // @[RegisterRouter.scala:87:24] wire _out_T_280 = _out_T_279; // @[RegisterRouter.scala:87:24] wire _out_prepend_T_13 = _out_T_280; // @[RegisterRouter.scala:87:24] wire out_rimask_21 = |_out_rimask_T_21; // @[RegisterRouter.scala:87:24] wire out_wimask_21 = &_out_wimask_T_21; // @[RegisterRouter.scala:87:24] wire out_romask_21 = |_out_romask_T_21; // @[RegisterRouter.scala:87:24] wire out_womask_21 = &_out_womask_T_21; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_21 = out_rivalid_21 & out_rimask_21; // @[RegisterRouter.scala:87:24] wire _out_T_282 = out_f_rivalid_21; // @[RegisterRouter.scala:87:24] wire out_f_roready_21 = out_roready_21 & out_romask_21; // @[RegisterRouter.scala:87:24] wire _out_T_283 = out_f_roready_21; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_21 = out_wivalid_21 & out_wimask_21; // @[RegisterRouter.scala:87:24] wire out_f_woready_21 = out_woready_21 & out_womask_21; // @[RegisterRouter.scala:87:24] wire _out_T_284 = ~out_rimask_21; // @[RegisterRouter.scala:87:24] wire _out_T_285 = ~out_wimask_21; // @[RegisterRouter.scala:87:24] wire _out_T_286 = ~out_romask_21; // @[RegisterRouter.scala:87:24] wire _out_T_287 = ~out_womask_21; // @[RegisterRouter.scala:87:24] wire [1:0] out_prepend_13 = {1'h0, _out_prepend_T_13}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_288 = {30'h0, out_prepend_13}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_289 = _out_T_288; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_14 = _out_T_289; // @[RegisterRouter.scala:87:24] wire out_rimask_22 = |_out_rimask_T_22; // @[RegisterRouter.scala:87:24] wire out_wimask_22 = &_out_wimask_T_22; // @[RegisterRouter.scala:87:24] wire out_romask_22 = |_out_romask_T_22; // @[RegisterRouter.scala:87:24] wire out_womask_22 = &_out_womask_T_22; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_22 = out_rivalid_22 & out_rimask_22; // @[RegisterRouter.scala:87:24] wire _out_T_296 = out_f_rivalid_22; // @[RegisterRouter.scala:87:24] assign out_f_roready_22 = out_roready_22 & out_romask_22; // @[RegisterRouter.scala:87:24] assign claimer_2 = out_f_roready_22; // @[RegisterRouter.scala:87:24] wire _out_T_297 = out_f_roready_22; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_22 = out_wivalid_22 & out_wimask_22; // @[RegisterRouter.scala:87:24] wire _out_T_298 = out_f_wivalid_22; // @[RegisterRouter.scala:87:24] wire out_f_woready_22 = out_woready_22 & out_womask_22; // @[RegisterRouter.scala:87:24] wire _out_T_299 = out_f_woready_22; // @[RegisterRouter.scala:87:24] wire _out_T_291 = _out_T_290[0]; // @[package.scala:163:13] wire _out_completerDev_T_6 = _out_T_290[0]; // @[package.scala:163:13] wire _out_T_292 = completerDev == _out_T_291; // @[package.scala:163:13] wire _out_T_294 = ~_out_T_293; // @[Plic.scala:298:19] wire _out_T_295 = ~_out_T_292; // @[Plic.scala:298:{19,33}] wire [1:0] _out_completer_2_T = enableVec0_2 >> _GEN_9; // @[Plic.scala:183:29, :301:51] wire _out_completer_2_T_1 = _out_completer_2_T[0]; // @[Plic.scala:301:51] assign _out_completer_2_T_2 = out_f_woready_22 & _out_completer_2_T_1; // @[RegisterRouter.scala:87:24] assign completer_2 = _out_completer_2_T_2; // @[Plic.scala:267:25, :301:35] wire _out_T_300 = ~out_rimask_22; // @[RegisterRouter.scala:87:24] wire _out_T_301 = ~out_wimask_22; // @[RegisterRouter.scala:87:24] wire _out_T_302 = ~out_romask_22; // @[RegisterRouter.scala:87:24] wire _out_T_303 = ~out_womask_22; // @[RegisterRouter.scala:87:24] wire [32:0] out_prepend_14 = {maxDevs_2, _out_prepend_T_14}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_304 = {31'h0, out_prepend_14}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_305 = _out_T_304; // @[RegisterRouter.scala:87:24] wire out_rimask_23 = _out_rimask_T_23; // @[RegisterRouter.scala:87:24] wire out_wimask_23 = _out_wimask_T_23; // @[RegisterRouter.scala:87:24] wire out_romask_23 = _out_romask_T_23; // @[RegisterRouter.scala:87:24] wire out_womask_23 = _out_womask_T_23; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_23 = out_rivalid_23 & out_rimask_23; // @[RegisterRouter.scala:87:24] wire _out_T_307 = out_f_rivalid_23; // @[RegisterRouter.scala:87:24] wire out_f_roready_23 = out_roready_23 & out_romask_23; // @[RegisterRouter.scala:87:24] wire _out_T_308 = out_f_roready_23; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_23 = out_wivalid_23 & out_wimask_23; // @[RegisterRouter.scala:87:24] wire _out_T_309 = out_f_wivalid_23; // @[RegisterRouter.scala:87:24] wire out_f_woready_23 = out_woready_23 & out_womask_23; // @[RegisterRouter.scala:87:24] wire _out_T_310 = out_f_woready_23; // @[RegisterRouter.scala:87:24] wire _out_T_311 = ~out_rimask_23; // @[RegisterRouter.scala:87:24] wire _out_T_312 = ~out_wimask_23; // @[RegisterRouter.scala:87:24] wire _out_T_313 = ~out_romask_23; // @[RegisterRouter.scala:87:24] wire _out_T_314 = ~out_womask_23; // @[RegisterRouter.scala:87:24] wire _out_T_316 = _out_T_315; // @[RegisterRouter.scala:87:24] wire _out_prepend_T_15 = _out_T_316; // @[RegisterRouter.scala:87:24] wire out_rimask_24 = |_out_rimask_T_24; // @[RegisterRouter.scala:87:24] wire out_wimask_24 = &_out_wimask_T_24; // @[RegisterRouter.scala:87:24] wire out_romask_24 = |_out_romask_T_24; // @[RegisterRouter.scala:87:24] wire out_womask_24 = &_out_womask_T_24; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_24 = out_rivalid_24 & out_rimask_24; // @[RegisterRouter.scala:87:24] wire _out_T_318 = out_f_rivalid_24; // @[RegisterRouter.scala:87:24] wire out_f_roready_24 = out_roready_24 & out_romask_24; // @[RegisterRouter.scala:87:24] wire _out_T_319 = out_f_roready_24; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_24 = out_wivalid_24 & out_wimask_24; // @[RegisterRouter.scala:87:24] wire out_f_woready_24 = out_woready_24 & out_womask_24; // @[RegisterRouter.scala:87:24] wire _out_T_320 = ~out_rimask_24; // @[RegisterRouter.scala:87:24] wire _out_T_321 = ~out_wimask_24; // @[RegisterRouter.scala:87:24] wire _out_T_322 = ~out_romask_24; // @[RegisterRouter.scala:87:24] wire _out_T_323 = ~out_womask_24; // @[RegisterRouter.scala:87:24] wire [1:0] out_prepend_15 = {1'h0, _out_prepend_T_15}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_324 = {30'h0, out_prepend_15}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_325 = _out_T_324; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_16 = _out_T_325; // @[RegisterRouter.scala:87:24] wire out_rimask_25 = |_out_rimask_T_25; // @[RegisterRouter.scala:87:24] wire out_wimask_25 = &_out_wimask_T_25; // @[RegisterRouter.scala:87:24] wire out_romask_25 = |_out_romask_T_25; // @[RegisterRouter.scala:87:24] wire out_womask_25 = &_out_womask_T_25; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_25 = out_rivalid_25 & out_rimask_25; // @[RegisterRouter.scala:87:24] wire _out_T_332 = out_f_rivalid_25; // @[RegisterRouter.scala:87:24] assign out_f_roready_25 = out_roready_25 & out_romask_25; // @[RegisterRouter.scala:87:24] assign claimer_6 = out_f_roready_25; // @[RegisterRouter.scala:87:24] wire _out_T_333 = out_f_roready_25; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_25 = out_wivalid_25 & out_wimask_25; // @[RegisterRouter.scala:87:24] wire _out_T_334 = out_f_wivalid_25; // @[RegisterRouter.scala:87:24] wire out_f_woready_25 = out_woready_25 & out_womask_25; // @[RegisterRouter.scala:87:24] wire _out_T_335 = out_f_woready_25; // @[RegisterRouter.scala:87:24] wire _out_T_327 = _out_T_326[0]; // @[package.scala:163:13] assign _out_completerDev_T_7 = _out_T_326[0]; // @[package.scala:163:13] wire _out_T_328 = completerDev == _out_T_327; // @[package.scala:163:13] wire _out_T_330 = ~_out_T_329; // @[Plic.scala:298:19] wire _out_T_331 = ~_out_T_328; // @[Plic.scala:298:{19,33}]
Generate the Verilog code corresponding to this FIRRTL code module TLDFromNoC : input clock : Clock input reset : Reset output io : { protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<65>, ingress_id : UInt}}} wire protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} regreset is_const : UInt<1>, clock, reset, UInt<1>(0h1) reg const_reg : UInt<21>, clock node const = mux(io.flit.bits.head, io.flit.bits.payload, const_reg) node _io_flit_ready_T = eq(io.flit.bits.tail, UInt<1>(0h0)) node _io_flit_ready_T_1 = and(is_const, _io_flit_ready_T) node _io_flit_ready_T_2 = or(_io_flit_ready_T_1, protocol.ready) connect io.flit.ready, _io_flit_ready_T_2 node _protocol_valid_T = eq(is_const, UInt<1>(0h0)) node _protocol_valid_T_1 = or(_protocol_valid_T, io.flit.bits.tail) node _protocol_valid_T_2 = and(_protocol_valid_T_1, io.flit.valid) connect protocol.valid, _protocol_valid_T_2 wire _protocol_bits_denied_WIRE : UInt<1> connect _protocol_bits_denied_WIRE, const connect protocol.bits.denied, _protocol_bits_denied_WIRE node _T = shr(const, 1) wire _protocol_bits_sink_WIRE : UInt<5> connect _protocol_bits_sink_WIRE, _T connect protocol.bits.sink, _protocol_bits_sink_WIRE node _T_1 = shr(_T, 5) wire _protocol_bits_echo_WIRE : { } wire _protocol_bits_echo_WIRE_1 : UInt<0> connect _protocol_bits_echo_WIRE_1, _T_1 connect protocol.bits.echo, _protocol_bits_echo_WIRE node _T_2 = shr(_T_1, 0) wire _protocol_bits_user_WIRE : { } wire _protocol_bits_user_WIRE_1 : UInt<0> connect _protocol_bits_user_WIRE_1, _T_2 connect protocol.bits.user, _protocol_bits_user_WIRE node _T_3 = shr(_T_2, 0) wire _protocol_bits_source_WIRE : UInt<6> connect _protocol_bits_source_WIRE, _T_3 connect protocol.bits.source, _protocol_bits_source_WIRE node _T_4 = shr(_T_3, 6) wire _protocol_bits_size_WIRE : UInt<4> connect _protocol_bits_size_WIRE, _T_4 connect protocol.bits.size, _protocol_bits_size_WIRE node _T_5 = shr(_T_4, 4) wire _protocol_bits_param_WIRE : UInt<2> connect _protocol_bits_param_WIRE, _T_5 connect protocol.bits.param, _protocol_bits_param_WIRE node _T_6 = shr(_T_5, 2) wire _protocol_bits_opcode_WIRE : UInt<3> connect _protocol_bits_opcode_WIRE, _T_6 connect protocol.bits.opcode, _protocol_bits_opcode_WIRE node _T_7 = shr(_T_6, 3) wire _protocol_bits_corrupt_WIRE : UInt<1> connect _protocol_bits_corrupt_WIRE, io.flit.bits.payload connect protocol.bits.corrupt, _protocol_bits_corrupt_WIRE node _T_8 = shr(io.flit.bits.payload, 1) wire _protocol_bits_data_WIRE : UInt<64> connect _protocol_bits_data_WIRE, _T_8 connect protocol.bits.data, _protocol_bits_data_WIRE node _T_9 = shr(_T_8, 64) node _T_10 = and(io.flit.ready, io.flit.valid) node _T_11 = and(_T_10, io.flit.bits.head) when _T_11 : connect is_const, UInt<1>(0h0) connect const_reg, io.flit.bits.payload node _T_12 = and(io.flit.ready, io.flit.valid) node _T_13 = and(_T_12, io.flit.bits.tail) when _T_13 : connect is_const, UInt<1>(0h1) connect io.protocol, protocol node _io_protocol_bits_source_T = bits(protocol.bits.source, 4, 0) connect io.protocol.bits.source, _io_protocol_bits_source_T
module TLDFromNoC( // @[TilelinkAdapters.scala:185:7] input clock, // @[TilelinkAdapters.scala:185:7] input reset, // @[TilelinkAdapters.scala:185:7] input io_protocol_ready, // @[TilelinkAdapters.scala:56:14] output io_protocol_valid, // @[TilelinkAdapters.scala:56:14] output [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:56:14] output [1:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:56:14] output [3:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:56:14] output [5:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:56:14] output [4:0] io_protocol_bits_sink, // @[TilelinkAdapters.scala:56:14] output io_protocol_bits_denied, // @[TilelinkAdapters.scala:56:14] output [63:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:56:14] output io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:56:14] output io_flit_ready, // @[TilelinkAdapters.scala:56:14] input io_flit_valid, // @[TilelinkAdapters.scala:56:14] input io_flit_bits_head, // @[TilelinkAdapters.scala:56:14] input io_flit_bits_tail, // @[TilelinkAdapters.scala:56:14] input [64:0] io_flit_bits_payload // @[TilelinkAdapters.scala:56:14] ); reg is_const; // @[TilelinkAdapters.scala:68:25] reg [20:0] const_reg; // @[TilelinkAdapters.scala:69:22] wire [20:0] const_0 = io_flit_bits_head ? io_flit_bits_payload[20:0] : const_reg; // @[TilelinkAdapters.scala:56:14, :69:22, :70:18] wire io_flit_ready_0 = is_const & ~io_flit_bits_tail | io_protocol_ready; // @[TilelinkAdapters.scala:68:25, :71:{30,33,53}] wire _GEN = io_flit_ready_0 & io_flit_valid; // @[Decoupled.scala:51:35] wire _GEN_0 = _GEN & io_flit_bits_head; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[TilelinkAdapters.scala:185:7] if (reset) // @[TilelinkAdapters.scala:185:7] is_const <= 1'h1; // @[TilelinkAdapters.scala:68:25, :185:7] else // @[TilelinkAdapters.scala:185:7] is_const <= _GEN & io_flit_bits_tail | ~_GEN_0 & is_const; // @[Decoupled.scala:51:35] if (_GEN_0) // @[TilelinkAdapters.scala:84:22] const_reg <= io_flit_bits_payload[20:0]; // @[TilelinkAdapters.scala:56:14, :69:22] always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module PeripheryBus_cbus : output auto : { coupler_to_prci_ctrl_fixer_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, coupler_to_bootrom_fragmenter_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, coupler_to_debug_fragmenter_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, coupler_to_plic_fragmenter_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, coupler_to_clint_fragmenter_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, coupler_to_bus_named_pbus_bus_xing_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, coupler_to_l2_ctrl_buffer_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, fixedClockNode_anon_out_5 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_4 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_3 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_2 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_1 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_0 : { clock : Clock, reset : Reset}, flip cbus_clock_groups_in : { member : { cbus_0 : { clock : Clock, reset : Reset}}}, flip bus_xing_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} input custom_boot : UInt<1> output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst cbus_clock_groups of ClockGroupAggregator_cbus inst clockGroup of ClockGroup_3 inst fixedClockNode of FixedClockBroadcast_7 inst broadcast of BundleBridgeNexus_NoOutput_3 inst fixer of TLFIFOFixer_2 connect fixer.clock, childClock connect fixer.reset, childReset inst in_xbar of TLXbar_cbus_in_i2_o1_a29d64s7k1z4u connect in_xbar.clock, childClock connect in_xbar.reset, childReset inst out_xbar of TLXbar_cbus_out_i1_o8_a29d64s7k1z4u connect out_xbar.clock, childClock connect out_xbar.reset, childReset inst buffer of TLBuffer_a29d64s7k1z4u connect buffer.clock, childClock connect buffer.reset, childReset inst atomics of TLAtomicAutomata_cbus connect atomics.clock, childClock connect atomics.reset, childReset inst wrapped_error_device of ErrorDeviceWrapper connect wrapped_error_device.clock, childClock connect wrapped_error_device.reset, childReset inst coupler_to_l2_ctrl of TLInterconnectCoupler_cbus_to_l2_ctrl connect coupler_to_l2_ctrl.clock, childClock connect coupler_to_l2_ctrl.reset, childReset inst buffer_1 of TLBuffer_a29d64s6k1z4u connect buffer_1.clock, childClock connect buffer_1.reset, childReset inst coupler_to_bus_named_pbus of TLInterconnectCoupler_cbus_to_bus_named_pbus connect coupler_to_bus_named_pbus.clock, childClock connect coupler_to_bus_named_pbus.reset, childReset inst coupler_to_clint of TLInterconnectCoupler_cbus_to_clint connect coupler_to_clint.clock, childClock connect coupler_to_clint.reset, childReset inst coupler_to_plic of TLInterconnectCoupler_cbus_to_plic connect coupler_to_plic.clock, childClock connect coupler_to_plic.reset, childReset inst coupler_to_debug of TLInterconnectCoupler_cbus_to_debug connect coupler_to_debug.clock, childClock connect coupler_to_debug.reset, childReset inst coupler_to_rockettile of TLInterconnectCoupler_cbus_to_rockettile connect coupler_to_rockettile.clock, childClock connect coupler_to_rockettile.reset, childReset inst coupler_to_bootrom of TLInterconnectCoupler_cbus_to_bootrom connect coupler_to_bootrom.clock, childClock connect coupler_to_bootrom.reset, childReset inst coupler_from_port_named_custom_boot_pin of TLInterconnectCoupler_cbus_from_port_named_custom_boot_pin connect coupler_from_port_named_custom_boot_pin.clock, childClock connect coupler_from_port_named_custom_boot_pin.reset, childReset inst coupler_to_prci_ctrl of TLInterconnectCoupler_cbus_to_prci_ctrl connect coupler_to_prci_ctrl.clock, childClock connect coupler_to_prci_ctrl.reset, childReset wire clockSinkNodeIn : { clock : Clock, reset : Reset} invalidate clockSinkNodeIn.reset invalidate clockSinkNodeIn.clock wire bus_xingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate bus_xingOut.d.bits.corrupt invalidate bus_xingOut.d.bits.data invalidate bus_xingOut.d.bits.denied invalidate bus_xingOut.d.bits.sink invalidate bus_xingOut.d.bits.source invalidate bus_xingOut.d.bits.size invalidate bus_xingOut.d.bits.param invalidate bus_xingOut.d.bits.opcode invalidate bus_xingOut.d.valid invalidate bus_xingOut.d.ready invalidate bus_xingOut.a.bits.corrupt invalidate bus_xingOut.a.bits.data invalidate bus_xingOut.a.bits.mask invalidate bus_xingOut.a.bits.user.amba_prot.fetch invalidate bus_xingOut.a.bits.user.amba_prot.secure invalidate bus_xingOut.a.bits.user.amba_prot.privileged invalidate bus_xingOut.a.bits.user.amba_prot.writealloc invalidate bus_xingOut.a.bits.user.amba_prot.readalloc invalidate bus_xingOut.a.bits.user.amba_prot.modifiable invalidate bus_xingOut.a.bits.user.amba_prot.bufferable invalidate bus_xingOut.a.bits.address invalidate bus_xingOut.a.bits.source invalidate bus_xingOut.a.bits.size invalidate bus_xingOut.a.bits.param invalidate bus_xingOut.a.bits.opcode invalidate bus_xingOut.a.valid invalidate bus_xingOut.a.ready wire bus_xingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate bus_xingIn.d.bits.corrupt invalidate bus_xingIn.d.bits.data invalidate bus_xingIn.d.bits.denied invalidate bus_xingIn.d.bits.sink invalidate bus_xingIn.d.bits.source invalidate bus_xingIn.d.bits.size invalidate bus_xingIn.d.bits.param invalidate bus_xingIn.d.bits.opcode invalidate bus_xingIn.d.valid invalidate bus_xingIn.d.ready invalidate bus_xingIn.a.bits.corrupt invalidate bus_xingIn.a.bits.data invalidate bus_xingIn.a.bits.mask invalidate bus_xingIn.a.bits.user.amba_prot.fetch invalidate bus_xingIn.a.bits.user.amba_prot.secure invalidate bus_xingIn.a.bits.user.amba_prot.privileged invalidate bus_xingIn.a.bits.user.amba_prot.writealloc invalidate bus_xingIn.a.bits.user.amba_prot.readalloc invalidate bus_xingIn.a.bits.user.amba_prot.modifiable invalidate bus_xingIn.a.bits.user.amba_prot.bufferable invalidate bus_xingIn.a.bits.address invalidate bus_xingIn.a.bits.source invalidate bus_xingIn.a.bits.size invalidate bus_xingIn.a.bits.param invalidate bus_xingIn.a.bits.opcode invalidate bus_xingIn.a.valid invalidate bus_xingIn.a.ready connect bus_xingOut, bus_xingIn wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect clockGroup.auto.in, cbus_clock_groups.auto.out connect fixedClockNode.auto.anon_in, clockGroup.auto.out connect clockSinkNodeIn, fixedClockNode.auto.anon_out_0 connect out_xbar.auto.anon_in, fixer.auto.anon_out connect atomics.auto.in, in_xbar.auto.anon_out connect wrapped_error_device.auto.buffer_in, out_xbar.auto.anon_out_0 connect coupler_to_l2_ctrl.auto.tl_in, out_xbar.auto.anon_out_1 connect coupler_to_bus_named_pbus.auto.widget_anon_in, out_xbar.auto.anon_out_2 connect coupler_to_clint.auto.tl_in, out_xbar.auto.anon_out_3 connect coupler_to_plic.auto.tl_in, out_xbar.auto.anon_out_4 connect coupler_to_debug.auto.tl_in, out_xbar.auto.anon_out_5 connect coupler_to_bootrom.auto.tl_in, out_xbar.auto.anon_out_6 connect coupler_to_prci_ctrl.auto.tl_in, out_xbar.auto.anon_out_7 connect fixer.auto.anon_in, buffer.auto.out connect buffer.auto.in, atomics.auto.out connect in_xbar.auto.anon_in_0, buffer_1.auto.out connect buffer_1.auto.in, bus_xingOut connect coupler_from_port_named_custom_boot_pin.auto.tl_in, nodeOut connect in_xbar.auto.anon_in_1, coupler_from_port_named_custom_boot_pin.auto.tl_out connect bus_xingIn, auto.bus_xing_in connect cbus_clock_groups.auto.in, auto.cbus_clock_groups_in connect auto.fixedClockNode_anon_out_0, fixedClockNode.auto.anon_out_1 connect auto.fixedClockNode_anon_out_1, fixedClockNode.auto.anon_out_2 connect auto.fixedClockNode_anon_out_2, fixedClockNode.auto.anon_out_3 connect auto.fixedClockNode_anon_out_3, fixedClockNode.auto.anon_out_4 connect auto.fixedClockNode_anon_out_4, fixedClockNode.auto.anon_out_5 connect auto.fixedClockNode_anon_out_5, fixedClockNode.auto.anon_out_6 connect coupler_to_l2_ctrl.auto.buffer_out.d, auto.coupler_to_l2_ctrl_buffer_out.d connect auto.coupler_to_l2_ctrl_buffer_out.a.bits, coupler_to_l2_ctrl.auto.buffer_out.a.bits connect auto.coupler_to_l2_ctrl_buffer_out.a.valid, coupler_to_l2_ctrl.auto.buffer_out.a.valid connect coupler_to_l2_ctrl.auto.buffer_out.a.ready, auto.coupler_to_l2_ctrl_buffer_out.a.ready connect coupler_to_bus_named_pbus.auto.bus_xing_out.d, auto.coupler_to_bus_named_pbus_bus_xing_out.d connect auto.coupler_to_bus_named_pbus_bus_xing_out.a.bits, coupler_to_bus_named_pbus.auto.bus_xing_out.a.bits connect auto.coupler_to_bus_named_pbus_bus_xing_out.a.valid, coupler_to_bus_named_pbus.auto.bus_xing_out.a.valid connect coupler_to_bus_named_pbus.auto.bus_xing_out.a.ready, auto.coupler_to_bus_named_pbus_bus_xing_out.a.ready connect coupler_to_clint.auto.fragmenter_anon_out.d, auto.coupler_to_clint_fragmenter_anon_out.d connect auto.coupler_to_clint_fragmenter_anon_out.a.bits, coupler_to_clint.auto.fragmenter_anon_out.a.bits connect auto.coupler_to_clint_fragmenter_anon_out.a.valid, coupler_to_clint.auto.fragmenter_anon_out.a.valid connect coupler_to_clint.auto.fragmenter_anon_out.a.ready, auto.coupler_to_clint_fragmenter_anon_out.a.ready connect coupler_to_plic.auto.fragmenter_anon_out.d, auto.coupler_to_plic_fragmenter_anon_out.d connect auto.coupler_to_plic_fragmenter_anon_out.a.bits, coupler_to_plic.auto.fragmenter_anon_out.a.bits connect auto.coupler_to_plic_fragmenter_anon_out.a.valid, coupler_to_plic.auto.fragmenter_anon_out.a.valid connect coupler_to_plic.auto.fragmenter_anon_out.a.ready, auto.coupler_to_plic_fragmenter_anon_out.a.ready connect coupler_to_debug.auto.fragmenter_anon_out.d, auto.coupler_to_debug_fragmenter_anon_out.d connect auto.coupler_to_debug_fragmenter_anon_out.a.bits, coupler_to_debug.auto.fragmenter_anon_out.a.bits connect auto.coupler_to_debug_fragmenter_anon_out.a.valid, coupler_to_debug.auto.fragmenter_anon_out.a.valid connect coupler_to_debug.auto.fragmenter_anon_out.a.ready, auto.coupler_to_debug_fragmenter_anon_out.a.ready connect coupler_to_bootrom.auto.fragmenter_anon_out.d, auto.coupler_to_bootrom_fragmenter_anon_out.d connect auto.coupler_to_bootrom_fragmenter_anon_out.a.bits, coupler_to_bootrom.auto.fragmenter_anon_out.a.bits connect auto.coupler_to_bootrom_fragmenter_anon_out.a.valid, coupler_to_bootrom.auto.fragmenter_anon_out.a.valid connect coupler_to_bootrom.auto.fragmenter_anon_out.a.ready, auto.coupler_to_bootrom_fragmenter_anon_out.a.ready connect coupler_to_prci_ctrl.auto.fixer_anon_out.d, auto.coupler_to_prci_ctrl_fixer_anon_out.d connect auto.coupler_to_prci_ctrl_fixer_anon_out.a.bits, coupler_to_prci_ctrl.auto.fixer_anon_out.a.bits connect auto.coupler_to_prci_ctrl_fixer_anon_out.a.valid, coupler_to_prci_ctrl.auto.fixer_anon_out.a.valid connect coupler_to_prci_ctrl.auto.fixer_anon_out.a.ready, auto.coupler_to_prci_ctrl_fixer_anon_out.a.ready regreset state : UInt<3>, childClock, childReset, UInt<3>(0h0) connect nodeOut.a.valid, UInt<1>(0h0) invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode connect nodeOut.d.ready, UInt<1>(0h1) node _T = eq(UInt<3>(0h0), state) when _T : when custom_boot : connect state, UInt<3>(0h1) else : node _T_1 = eq(UInt<3>(0h1), state) when _T_1 : connect nodeOut.a.valid, UInt<1>(0h1) node _nodeOut_a_bits_legal_T = leq(UInt<1>(0h0), UInt<2>(0h2)) node _nodeOut_a_bits_legal_T_1 = leq(UInt<2>(0h2), UInt<4>(0hc)) node _nodeOut_a_bits_legal_T_2 = and(_nodeOut_a_bits_legal_T, _nodeOut_a_bits_legal_T_1) node _nodeOut_a_bits_legal_T_3 = or(UInt<1>(0h0), _nodeOut_a_bits_legal_T_2) node _nodeOut_a_bits_legal_T_4 = xor(UInt<13>(0h1000), UInt<14>(0h3000)) node _nodeOut_a_bits_legal_T_5 = cvt(_nodeOut_a_bits_legal_T_4) node _nodeOut_a_bits_legal_T_6 = and(_nodeOut_a_bits_legal_T_5, asSInt(UInt<30>(0h1a113000))) node _nodeOut_a_bits_legal_T_7 = asSInt(_nodeOut_a_bits_legal_T_6) node _nodeOut_a_bits_legal_T_8 = eq(_nodeOut_a_bits_legal_T_7, asSInt(UInt<1>(0h0))) node _nodeOut_a_bits_legal_T_9 = and(_nodeOut_a_bits_legal_T_3, _nodeOut_a_bits_legal_T_8) node _nodeOut_a_bits_legal_T_10 = leq(UInt<1>(0h0), UInt<2>(0h2)) node _nodeOut_a_bits_legal_T_11 = leq(UInt<2>(0h2), UInt<3>(0h6)) node _nodeOut_a_bits_legal_T_12 = and(_nodeOut_a_bits_legal_T_10, _nodeOut_a_bits_legal_T_11) node _nodeOut_a_bits_legal_T_13 = or(UInt<1>(0h0), _nodeOut_a_bits_legal_T_12) node _nodeOut_a_bits_legal_T_14 = xor(UInt<13>(0h1000), UInt<1>(0h0)) node _nodeOut_a_bits_legal_T_15 = cvt(_nodeOut_a_bits_legal_T_14) node _nodeOut_a_bits_legal_T_16 = and(_nodeOut_a_bits_legal_T_15, asSInt(UInt<30>(0h1a112000))) node _nodeOut_a_bits_legal_T_17 = asSInt(_nodeOut_a_bits_legal_T_16) node _nodeOut_a_bits_legal_T_18 = eq(_nodeOut_a_bits_legal_T_17, asSInt(UInt<1>(0h0))) node _nodeOut_a_bits_legal_T_19 = xor(UInt<13>(0h1000), UInt<21>(0h100000)) node _nodeOut_a_bits_legal_T_20 = cvt(_nodeOut_a_bits_legal_T_19) node _nodeOut_a_bits_legal_T_21 = and(_nodeOut_a_bits_legal_T_20, asSInt(UInt<30>(0h1a103000))) node _nodeOut_a_bits_legal_T_22 = asSInt(_nodeOut_a_bits_legal_T_21) node _nodeOut_a_bits_legal_T_23 = eq(_nodeOut_a_bits_legal_T_22, asSInt(UInt<1>(0h0))) node _nodeOut_a_bits_legal_T_24 = xor(UInt<13>(0h1000), UInt<26>(0h2000000)) node _nodeOut_a_bits_legal_T_25 = cvt(_nodeOut_a_bits_legal_T_24) node _nodeOut_a_bits_legal_T_26 = and(_nodeOut_a_bits_legal_T_25, asSInt(UInt<30>(0h1a110000))) node _nodeOut_a_bits_legal_T_27 = asSInt(_nodeOut_a_bits_legal_T_26) node _nodeOut_a_bits_legal_T_28 = eq(_nodeOut_a_bits_legal_T_27, asSInt(UInt<1>(0h0))) node _nodeOut_a_bits_legal_T_29 = xor(UInt<13>(0h1000), UInt<26>(0h2010000)) node _nodeOut_a_bits_legal_T_30 = cvt(_nodeOut_a_bits_legal_T_29) node _nodeOut_a_bits_legal_T_31 = and(_nodeOut_a_bits_legal_T_30, asSInt(UInt<30>(0h1a113000))) node _nodeOut_a_bits_legal_T_32 = asSInt(_nodeOut_a_bits_legal_T_31) node _nodeOut_a_bits_legal_T_33 = eq(_nodeOut_a_bits_legal_T_32, asSInt(UInt<1>(0h0))) node _nodeOut_a_bits_legal_T_34 = xor(UInt<13>(0h1000), UInt<28>(0h8000000)) node _nodeOut_a_bits_legal_T_35 = cvt(_nodeOut_a_bits_legal_T_34) node _nodeOut_a_bits_legal_T_36 = and(_nodeOut_a_bits_legal_T_35, asSInt(UInt<30>(0h18000000))) node _nodeOut_a_bits_legal_T_37 = asSInt(_nodeOut_a_bits_legal_T_36) node _nodeOut_a_bits_legal_T_38 = eq(_nodeOut_a_bits_legal_T_37, asSInt(UInt<1>(0h0))) node _nodeOut_a_bits_legal_T_39 = xor(UInt<13>(0h1000), UInt<29>(0h10000000)) node _nodeOut_a_bits_legal_T_40 = cvt(_nodeOut_a_bits_legal_T_39) node _nodeOut_a_bits_legal_T_41 = and(_nodeOut_a_bits_legal_T_40, asSInt(UInt<30>(0h1a113000))) node _nodeOut_a_bits_legal_T_42 = asSInt(_nodeOut_a_bits_legal_T_41) node _nodeOut_a_bits_legal_T_43 = eq(_nodeOut_a_bits_legal_T_42, asSInt(UInt<1>(0h0))) node _nodeOut_a_bits_legal_T_44 = or(_nodeOut_a_bits_legal_T_18, _nodeOut_a_bits_legal_T_23) node _nodeOut_a_bits_legal_T_45 = or(_nodeOut_a_bits_legal_T_44, _nodeOut_a_bits_legal_T_28) node _nodeOut_a_bits_legal_T_46 = or(_nodeOut_a_bits_legal_T_45, _nodeOut_a_bits_legal_T_33) node _nodeOut_a_bits_legal_T_47 = or(_nodeOut_a_bits_legal_T_46, _nodeOut_a_bits_legal_T_38) node _nodeOut_a_bits_legal_T_48 = or(_nodeOut_a_bits_legal_T_47, _nodeOut_a_bits_legal_T_43) node _nodeOut_a_bits_legal_T_49 = and(_nodeOut_a_bits_legal_T_13, _nodeOut_a_bits_legal_T_48) node _nodeOut_a_bits_legal_T_50 = or(UInt<1>(0h0), UInt<1>(0h0)) node _nodeOut_a_bits_legal_T_51 = xor(UInt<13>(0h1000), UInt<17>(0h10000)) node _nodeOut_a_bits_legal_T_52 = cvt(_nodeOut_a_bits_legal_T_51) node _nodeOut_a_bits_legal_T_53 = and(_nodeOut_a_bits_legal_T_52, asSInt(UInt<30>(0h1a110000))) node _nodeOut_a_bits_legal_T_54 = asSInt(_nodeOut_a_bits_legal_T_53) node _nodeOut_a_bits_legal_T_55 = eq(_nodeOut_a_bits_legal_T_54, asSInt(UInt<1>(0h0))) node _nodeOut_a_bits_legal_T_56 = and(_nodeOut_a_bits_legal_T_50, _nodeOut_a_bits_legal_T_55) node _nodeOut_a_bits_legal_T_57 = or(UInt<1>(0h0), _nodeOut_a_bits_legal_T_9) node _nodeOut_a_bits_legal_T_58 = or(_nodeOut_a_bits_legal_T_57, _nodeOut_a_bits_legal_T_49) node nodeOut_a_bits_legal = or(_nodeOut_a_bits_legal_T_58, _nodeOut_a_bits_legal_T_56) wire nodeOut_a_bits_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} connect nodeOut_a_bits_a.opcode, UInt<1>(0h0) connect nodeOut_a_bits_a.param, UInt<1>(0h0) connect nodeOut_a_bits_a.size, UInt<2>(0h2) connect nodeOut_a_bits_a.source, UInt<1>(0h0) connect nodeOut_a_bits_a.address, UInt<13>(0h1000) node _nodeOut_a_bits_a_mask_sizeOH_T = or(UInt<2>(0h2), UInt<3>(0h0)) node nodeOut_a_bits_a_mask_sizeOH_shiftAmount = bits(_nodeOut_a_bits_a_mask_sizeOH_T, 1, 0) node _nodeOut_a_bits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), nodeOut_a_bits_a_mask_sizeOH_shiftAmount) node _nodeOut_a_bits_a_mask_sizeOH_T_2 = bits(_nodeOut_a_bits_a_mask_sizeOH_T_1, 2, 0) node nodeOut_a_bits_a_mask_sizeOH = or(_nodeOut_a_bits_a_mask_sizeOH_T_2, UInt<1>(0h1)) node nodeOut_a_bits_a_mask_sub_sub_sub_0_1 = geq(UInt<2>(0h2), UInt<2>(0h3)) node nodeOut_a_bits_a_mask_sub_sub_size = bits(nodeOut_a_bits_a_mask_sizeOH, 2, 2) node nodeOut_a_bits_a_mask_sub_sub_nbit = eq(UInt<1>(0h0), UInt<1>(0h0)) node nodeOut_a_bits_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), nodeOut_a_bits_a_mask_sub_sub_nbit) node _nodeOut_a_bits_a_mask_sub_sub_acc_T = and(nodeOut_a_bits_a_mask_sub_sub_size, nodeOut_a_bits_a_mask_sub_sub_0_2) node nodeOut_a_bits_a_mask_sub_sub_0_1 = or(nodeOut_a_bits_a_mask_sub_sub_sub_0_1, _nodeOut_a_bits_a_mask_sub_sub_acc_T) node nodeOut_a_bits_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), UInt<1>(0h0)) node _nodeOut_a_bits_a_mask_sub_sub_acc_T_1 = and(nodeOut_a_bits_a_mask_sub_sub_size, nodeOut_a_bits_a_mask_sub_sub_1_2) node nodeOut_a_bits_a_mask_sub_sub_1_1 = or(nodeOut_a_bits_a_mask_sub_sub_sub_0_1, _nodeOut_a_bits_a_mask_sub_sub_acc_T_1) node nodeOut_a_bits_a_mask_sub_size = bits(nodeOut_a_bits_a_mask_sizeOH, 1, 1) node nodeOut_a_bits_a_mask_sub_nbit = eq(UInt<1>(0h0), UInt<1>(0h0)) node nodeOut_a_bits_a_mask_sub_0_2 = and(nodeOut_a_bits_a_mask_sub_sub_0_2, nodeOut_a_bits_a_mask_sub_nbit) node _nodeOut_a_bits_a_mask_sub_acc_T = and(nodeOut_a_bits_a_mask_sub_size, nodeOut_a_bits_a_mask_sub_0_2) node nodeOut_a_bits_a_mask_sub_0_1 = or(nodeOut_a_bits_a_mask_sub_sub_0_1, _nodeOut_a_bits_a_mask_sub_acc_T) node nodeOut_a_bits_a_mask_sub_1_2 = and(nodeOut_a_bits_a_mask_sub_sub_0_2, UInt<1>(0h0)) node _nodeOut_a_bits_a_mask_sub_acc_T_1 = and(nodeOut_a_bits_a_mask_sub_size, nodeOut_a_bits_a_mask_sub_1_2) node nodeOut_a_bits_a_mask_sub_1_1 = or(nodeOut_a_bits_a_mask_sub_sub_0_1, _nodeOut_a_bits_a_mask_sub_acc_T_1) node nodeOut_a_bits_a_mask_sub_2_2 = and(nodeOut_a_bits_a_mask_sub_sub_1_2, nodeOut_a_bits_a_mask_sub_nbit) node _nodeOut_a_bits_a_mask_sub_acc_T_2 = and(nodeOut_a_bits_a_mask_sub_size, nodeOut_a_bits_a_mask_sub_2_2) node nodeOut_a_bits_a_mask_sub_2_1 = or(nodeOut_a_bits_a_mask_sub_sub_1_1, _nodeOut_a_bits_a_mask_sub_acc_T_2) node nodeOut_a_bits_a_mask_sub_3_2 = and(nodeOut_a_bits_a_mask_sub_sub_1_2, UInt<1>(0h0)) node _nodeOut_a_bits_a_mask_sub_acc_T_3 = and(nodeOut_a_bits_a_mask_sub_size, nodeOut_a_bits_a_mask_sub_3_2) node nodeOut_a_bits_a_mask_sub_3_1 = or(nodeOut_a_bits_a_mask_sub_sub_1_1, _nodeOut_a_bits_a_mask_sub_acc_T_3) node nodeOut_a_bits_a_mask_size = bits(nodeOut_a_bits_a_mask_sizeOH, 0, 0) node nodeOut_a_bits_a_mask_nbit = eq(UInt<1>(0h0), UInt<1>(0h0)) node nodeOut_a_bits_a_mask_eq = and(nodeOut_a_bits_a_mask_sub_0_2, nodeOut_a_bits_a_mask_nbit) node _nodeOut_a_bits_a_mask_acc_T = and(nodeOut_a_bits_a_mask_size, nodeOut_a_bits_a_mask_eq) node nodeOut_a_bits_a_mask_acc = or(nodeOut_a_bits_a_mask_sub_0_1, _nodeOut_a_bits_a_mask_acc_T) node nodeOut_a_bits_a_mask_eq_1 = and(nodeOut_a_bits_a_mask_sub_0_2, UInt<1>(0h0)) node _nodeOut_a_bits_a_mask_acc_T_1 = and(nodeOut_a_bits_a_mask_size, nodeOut_a_bits_a_mask_eq_1) node nodeOut_a_bits_a_mask_acc_1 = or(nodeOut_a_bits_a_mask_sub_0_1, _nodeOut_a_bits_a_mask_acc_T_1) node nodeOut_a_bits_a_mask_eq_2 = and(nodeOut_a_bits_a_mask_sub_1_2, nodeOut_a_bits_a_mask_nbit) node _nodeOut_a_bits_a_mask_acc_T_2 = and(nodeOut_a_bits_a_mask_size, nodeOut_a_bits_a_mask_eq_2) node nodeOut_a_bits_a_mask_acc_2 = or(nodeOut_a_bits_a_mask_sub_1_1, _nodeOut_a_bits_a_mask_acc_T_2) node nodeOut_a_bits_a_mask_eq_3 = and(nodeOut_a_bits_a_mask_sub_1_2, UInt<1>(0h0)) node _nodeOut_a_bits_a_mask_acc_T_3 = and(nodeOut_a_bits_a_mask_size, nodeOut_a_bits_a_mask_eq_3) node nodeOut_a_bits_a_mask_acc_3 = or(nodeOut_a_bits_a_mask_sub_1_1, _nodeOut_a_bits_a_mask_acc_T_3) node nodeOut_a_bits_a_mask_eq_4 = and(nodeOut_a_bits_a_mask_sub_2_2, nodeOut_a_bits_a_mask_nbit) node _nodeOut_a_bits_a_mask_acc_T_4 = and(nodeOut_a_bits_a_mask_size, nodeOut_a_bits_a_mask_eq_4) node nodeOut_a_bits_a_mask_acc_4 = or(nodeOut_a_bits_a_mask_sub_2_1, _nodeOut_a_bits_a_mask_acc_T_4) node nodeOut_a_bits_a_mask_eq_5 = and(nodeOut_a_bits_a_mask_sub_2_2, UInt<1>(0h0)) node _nodeOut_a_bits_a_mask_acc_T_5 = and(nodeOut_a_bits_a_mask_size, nodeOut_a_bits_a_mask_eq_5) node nodeOut_a_bits_a_mask_acc_5 = or(nodeOut_a_bits_a_mask_sub_2_1, _nodeOut_a_bits_a_mask_acc_T_5) node nodeOut_a_bits_a_mask_eq_6 = and(nodeOut_a_bits_a_mask_sub_3_2, nodeOut_a_bits_a_mask_nbit) node _nodeOut_a_bits_a_mask_acc_T_6 = and(nodeOut_a_bits_a_mask_size, nodeOut_a_bits_a_mask_eq_6) node nodeOut_a_bits_a_mask_acc_6 = or(nodeOut_a_bits_a_mask_sub_3_1, _nodeOut_a_bits_a_mask_acc_T_6) node nodeOut_a_bits_a_mask_eq_7 = and(nodeOut_a_bits_a_mask_sub_3_2, UInt<1>(0h0)) node _nodeOut_a_bits_a_mask_acc_T_7 = and(nodeOut_a_bits_a_mask_size, nodeOut_a_bits_a_mask_eq_7) node nodeOut_a_bits_a_mask_acc_7 = or(nodeOut_a_bits_a_mask_sub_3_1, _nodeOut_a_bits_a_mask_acc_T_7) node nodeOut_a_bits_a_mask_lo_lo = cat(nodeOut_a_bits_a_mask_acc_1, nodeOut_a_bits_a_mask_acc) node nodeOut_a_bits_a_mask_lo_hi = cat(nodeOut_a_bits_a_mask_acc_3, nodeOut_a_bits_a_mask_acc_2) node nodeOut_a_bits_a_mask_lo = cat(nodeOut_a_bits_a_mask_lo_hi, nodeOut_a_bits_a_mask_lo_lo) node nodeOut_a_bits_a_mask_hi_lo = cat(nodeOut_a_bits_a_mask_acc_5, nodeOut_a_bits_a_mask_acc_4) node nodeOut_a_bits_a_mask_hi_hi = cat(nodeOut_a_bits_a_mask_acc_7, nodeOut_a_bits_a_mask_acc_6) node nodeOut_a_bits_a_mask_hi = cat(nodeOut_a_bits_a_mask_hi_hi, nodeOut_a_bits_a_mask_hi_lo) node _nodeOut_a_bits_a_mask_T = cat(nodeOut_a_bits_a_mask_hi, nodeOut_a_bits_a_mask_lo) connect nodeOut_a_bits_a.mask, _nodeOut_a_bits_a_mask_T connect nodeOut_a_bits_a.data, UInt<32>(0h80000000) connect nodeOut_a_bits_a.corrupt, UInt<1>(0h0) connect nodeOut.a.bits, nodeOut_a_bits_a node _T_2 = and(nodeOut.a.ready, nodeOut.a.valid) when _T_2 : connect state, UInt<3>(0h2) else : node _T_3 = eq(UInt<3>(0h2), state) when _T_3 : node _T_4 = and(nodeOut.d.ready, nodeOut.d.valid) when _T_4 : connect state, UInt<3>(0h3) else : node _T_5 = eq(UInt<3>(0h3), state) when _T_5 : connect nodeOut.a.valid, UInt<1>(0h1) node _nodeOut_a_bits_legal_T_59 = leq(UInt<1>(0h0), UInt<2>(0h2)) node _nodeOut_a_bits_legal_T_60 = leq(UInt<2>(0h2), UInt<4>(0hc)) node _nodeOut_a_bits_legal_T_61 = and(_nodeOut_a_bits_legal_T_59, _nodeOut_a_bits_legal_T_60) node _nodeOut_a_bits_legal_T_62 = or(UInt<1>(0h0), _nodeOut_a_bits_legal_T_61) node _nodeOut_a_bits_legal_T_63 = xor(UInt<26>(0h2000000), UInt<14>(0h3000)) node _nodeOut_a_bits_legal_T_64 = cvt(_nodeOut_a_bits_legal_T_63) node _nodeOut_a_bits_legal_T_65 = and(_nodeOut_a_bits_legal_T_64, asSInt(UInt<30>(0h1a113000))) node _nodeOut_a_bits_legal_T_66 = asSInt(_nodeOut_a_bits_legal_T_65) node _nodeOut_a_bits_legal_T_67 = eq(_nodeOut_a_bits_legal_T_66, asSInt(UInt<1>(0h0))) node _nodeOut_a_bits_legal_T_68 = and(_nodeOut_a_bits_legal_T_62, _nodeOut_a_bits_legal_T_67) node _nodeOut_a_bits_legal_T_69 = leq(UInt<1>(0h0), UInt<2>(0h2)) node _nodeOut_a_bits_legal_T_70 = leq(UInt<2>(0h2), UInt<3>(0h6)) node _nodeOut_a_bits_legal_T_71 = and(_nodeOut_a_bits_legal_T_69, _nodeOut_a_bits_legal_T_70) node _nodeOut_a_bits_legal_T_72 = or(UInt<1>(0h0), _nodeOut_a_bits_legal_T_71) node _nodeOut_a_bits_legal_T_73 = xor(UInt<26>(0h2000000), UInt<1>(0h0)) node _nodeOut_a_bits_legal_T_74 = cvt(_nodeOut_a_bits_legal_T_73) node _nodeOut_a_bits_legal_T_75 = and(_nodeOut_a_bits_legal_T_74, asSInt(UInt<30>(0h1a112000))) node _nodeOut_a_bits_legal_T_76 = asSInt(_nodeOut_a_bits_legal_T_75) node _nodeOut_a_bits_legal_T_77 = eq(_nodeOut_a_bits_legal_T_76, asSInt(UInt<1>(0h0))) node _nodeOut_a_bits_legal_T_78 = xor(UInt<26>(0h2000000), UInt<21>(0h100000)) node _nodeOut_a_bits_legal_T_79 = cvt(_nodeOut_a_bits_legal_T_78) node _nodeOut_a_bits_legal_T_80 = and(_nodeOut_a_bits_legal_T_79, asSInt(UInt<30>(0h1a103000))) node _nodeOut_a_bits_legal_T_81 = asSInt(_nodeOut_a_bits_legal_T_80) node _nodeOut_a_bits_legal_T_82 = eq(_nodeOut_a_bits_legal_T_81, asSInt(UInt<1>(0h0))) node _nodeOut_a_bits_legal_T_83 = xor(UInt<26>(0h2000000), UInt<26>(0h2000000)) node _nodeOut_a_bits_legal_T_84 = cvt(_nodeOut_a_bits_legal_T_83) node _nodeOut_a_bits_legal_T_85 = and(_nodeOut_a_bits_legal_T_84, asSInt(UInt<30>(0h1a110000))) node _nodeOut_a_bits_legal_T_86 = asSInt(_nodeOut_a_bits_legal_T_85) node _nodeOut_a_bits_legal_T_87 = eq(_nodeOut_a_bits_legal_T_86, asSInt(UInt<1>(0h0))) node _nodeOut_a_bits_legal_T_88 = xor(UInt<26>(0h2000000), UInt<26>(0h2010000)) node _nodeOut_a_bits_legal_T_89 = cvt(_nodeOut_a_bits_legal_T_88) node _nodeOut_a_bits_legal_T_90 = and(_nodeOut_a_bits_legal_T_89, asSInt(UInt<30>(0h1a113000))) node _nodeOut_a_bits_legal_T_91 = asSInt(_nodeOut_a_bits_legal_T_90) node _nodeOut_a_bits_legal_T_92 = eq(_nodeOut_a_bits_legal_T_91, asSInt(UInt<1>(0h0))) node _nodeOut_a_bits_legal_T_93 = xor(UInt<26>(0h2000000), UInt<28>(0h8000000)) node _nodeOut_a_bits_legal_T_94 = cvt(_nodeOut_a_bits_legal_T_93) node _nodeOut_a_bits_legal_T_95 = and(_nodeOut_a_bits_legal_T_94, asSInt(UInt<30>(0h18000000))) node _nodeOut_a_bits_legal_T_96 = asSInt(_nodeOut_a_bits_legal_T_95) node _nodeOut_a_bits_legal_T_97 = eq(_nodeOut_a_bits_legal_T_96, asSInt(UInt<1>(0h0))) node _nodeOut_a_bits_legal_T_98 = xor(UInt<26>(0h2000000), UInt<29>(0h10000000)) node _nodeOut_a_bits_legal_T_99 = cvt(_nodeOut_a_bits_legal_T_98) node _nodeOut_a_bits_legal_T_100 = and(_nodeOut_a_bits_legal_T_99, asSInt(UInt<30>(0h1a113000))) node _nodeOut_a_bits_legal_T_101 = asSInt(_nodeOut_a_bits_legal_T_100) node _nodeOut_a_bits_legal_T_102 = eq(_nodeOut_a_bits_legal_T_101, asSInt(UInt<1>(0h0))) node _nodeOut_a_bits_legal_T_103 = or(_nodeOut_a_bits_legal_T_77, _nodeOut_a_bits_legal_T_82) node _nodeOut_a_bits_legal_T_104 = or(_nodeOut_a_bits_legal_T_103, _nodeOut_a_bits_legal_T_87) node _nodeOut_a_bits_legal_T_105 = or(_nodeOut_a_bits_legal_T_104, _nodeOut_a_bits_legal_T_92) node _nodeOut_a_bits_legal_T_106 = or(_nodeOut_a_bits_legal_T_105, _nodeOut_a_bits_legal_T_97) node _nodeOut_a_bits_legal_T_107 = or(_nodeOut_a_bits_legal_T_106, _nodeOut_a_bits_legal_T_102) node _nodeOut_a_bits_legal_T_108 = and(_nodeOut_a_bits_legal_T_72, _nodeOut_a_bits_legal_T_107) node _nodeOut_a_bits_legal_T_109 = or(UInt<1>(0h0), UInt<1>(0h0)) node _nodeOut_a_bits_legal_T_110 = xor(UInt<26>(0h2000000), UInt<17>(0h10000)) node _nodeOut_a_bits_legal_T_111 = cvt(_nodeOut_a_bits_legal_T_110) node _nodeOut_a_bits_legal_T_112 = and(_nodeOut_a_bits_legal_T_111, asSInt(UInt<30>(0h1a110000))) node _nodeOut_a_bits_legal_T_113 = asSInt(_nodeOut_a_bits_legal_T_112) node _nodeOut_a_bits_legal_T_114 = eq(_nodeOut_a_bits_legal_T_113, asSInt(UInt<1>(0h0))) node _nodeOut_a_bits_legal_T_115 = and(_nodeOut_a_bits_legal_T_109, _nodeOut_a_bits_legal_T_114) node _nodeOut_a_bits_legal_T_116 = or(UInt<1>(0h0), _nodeOut_a_bits_legal_T_68) node _nodeOut_a_bits_legal_T_117 = or(_nodeOut_a_bits_legal_T_116, _nodeOut_a_bits_legal_T_108) node nodeOut_a_bits_legal_1 = or(_nodeOut_a_bits_legal_T_117, _nodeOut_a_bits_legal_T_115) wire nodeOut_a_bits_a_1 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} connect nodeOut_a_bits_a_1.opcode, UInt<1>(0h0) connect nodeOut_a_bits_a_1.param, UInt<1>(0h0) connect nodeOut_a_bits_a_1.size, UInt<2>(0h2) connect nodeOut_a_bits_a_1.source, UInt<1>(0h0) connect nodeOut_a_bits_a_1.address, UInt<26>(0h2000000) node _nodeOut_a_bits_a_mask_sizeOH_T_3 = or(UInt<2>(0h2), UInt<3>(0h0)) node nodeOut_a_bits_a_mask_sizeOH_shiftAmount_1 = bits(_nodeOut_a_bits_a_mask_sizeOH_T_3, 1, 0) node _nodeOut_a_bits_a_mask_sizeOH_T_4 = dshl(UInt<1>(0h1), nodeOut_a_bits_a_mask_sizeOH_shiftAmount_1) node _nodeOut_a_bits_a_mask_sizeOH_T_5 = bits(_nodeOut_a_bits_a_mask_sizeOH_T_4, 2, 0) node nodeOut_a_bits_a_mask_sizeOH_1 = or(_nodeOut_a_bits_a_mask_sizeOH_T_5, UInt<1>(0h1)) node nodeOut_a_bits_a_mask_sub_sub_sub_0_1_1 = geq(UInt<2>(0h2), UInt<2>(0h3)) node nodeOut_a_bits_a_mask_sub_sub_size_1 = bits(nodeOut_a_bits_a_mask_sizeOH_1, 2, 2) node nodeOut_a_bits_a_mask_sub_sub_nbit_1 = eq(UInt<1>(0h0), UInt<1>(0h0)) node nodeOut_a_bits_a_mask_sub_sub_0_2_1 = and(UInt<1>(0h1), nodeOut_a_bits_a_mask_sub_sub_nbit_1) node _nodeOut_a_bits_a_mask_sub_sub_acc_T_2 = and(nodeOut_a_bits_a_mask_sub_sub_size_1, nodeOut_a_bits_a_mask_sub_sub_0_2_1) node nodeOut_a_bits_a_mask_sub_sub_0_1_1 = or(nodeOut_a_bits_a_mask_sub_sub_sub_0_1_1, _nodeOut_a_bits_a_mask_sub_sub_acc_T_2) node nodeOut_a_bits_a_mask_sub_sub_1_2_1 = and(UInt<1>(0h1), UInt<1>(0h0)) node _nodeOut_a_bits_a_mask_sub_sub_acc_T_3 = and(nodeOut_a_bits_a_mask_sub_sub_size_1, nodeOut_a_bits_a_mask_sub_sub_1_2_1) node nodeOut_a_bits_a_mask_sub_sub_1_1_1 = or(nodeOut_a_bits_a_mask_sub_sub_sub_0_1_1, _nodeOut_a_bits_a_mask_sub_sub_acc_T_3) node nodeOut_a_bits_a_mask_sub_size_1 = bits(nodeOut_a_bits_a_mask_sizeOH_1, 1, 1) node nodeOut_a_bits_a_mask_sub_nbit_1 = eq(UInt<1>(0h0), UInt<1>(0h0)) node nodeOut_a_bits_a_mask_sub_0_2_1 = and(nodeOut_a_bits_a_mask_sub_sub_0_2_1, nodeOut_a_bits_a_mask_sub_nbit_1) node _nodeOut_a_bits_a_mask_sub_acc_T_4 = and(nodeOut_a_bits_a_mask_sub_size_1, nodeOut_a_bits_a_mask_sub_0_2_1) node nodeOut_a_bits_a_mask_sub_0_1_1 = or(nodeOut_a_bits_a_mask_sub_sub_0_1_1, _nodeOut_a_bits_a_mask_sub_acc_T_4) node nodeOut_a_bits_a_mask_sub_1_2_1 = and(nodeOut_a_bits_a_mask_sub_sub_0_2_1, UInt<1>(0h0)) node _nodeOut_a_bits_a_mask_sub_acc_T_5 = and(nodeOut_a_bits_a_mask_sub_size_1, nodeOut_a_bits_a_mask_sub_1_2_1) node nodeOut_a_bits_a_mask_sub_1_1_1 = or(nodeOut_a_bits_a_mask_sub_sub_0_1_1, _nodeOut_a_bits_a_mask_sub_acc_T_5) node nodeOut_a_bits_a_mask_sub_2_2_1 = and(nodeOut_a_bits_a_mask_sub_sub_1_2_1, nodeOut_a_bits_a_mask_sub_nbit_1) node _nodeOut_a_bits_a_mask_sub_acc_T_6 = and(nodeOut_a_bits_a_mask_sub_size_1, nodeOut_a_bits_a_mask_sub_2_2_1) node nodeOut_a_bits_a_mask_sub_2_1_1 = or(nodeOut_a_bits_a_mask_sub_sub_1_1_1, _nodeOut_a_bits_a_mask_sub_acc_T_6) node nodeOut_a_bits_a_mask_sub_3_2_1 = and(nodeOut_a_bits_a_mask_sub_sub_1_2_1, UInt<1>(0h0)) node _nodeOut_a_bits_a_mask_sub_acc_T_7 = and(nodeOut_a_bits_a_mask_sub_size_1, nodeOut_a_bits_a_mask_sub_3_2_1) node nodeOut_a_bits_a_mask_sub_3_1_1 = or(nodeOut_a_bits_a_mask_sub_sub_1_1_1, _nodeOut_a_bits_a_mask_sub_acc_T_7) node nodeOut_a_bits_a_mask_size_1 = bits(nodeOut_a_bits_a_mask_sizeOH_1, 0, 0) node nodeOut_a_bits_a_mask_nbit_1 = eq(UInt<1>(0h0), UInt<1>(0h0)) node nodeOut_a_bits_a_mask_eq_8 = and(nodeOut_a_bits_a_mask_sub_0_2_1, nodeOut_a_bits_a_mask_nbit_1) node _nodeOut_a_bits_a_mask_acc_T_8 = and(nodeOut_a_bits_a_mask_size_1, nodeOut_a_bits_a_mask_eq_8) node nodeOut_a_bits_a_mask_acc_8 = or(nodeOut_a_bits_a_mask_sub_0_1_1, _nodeOut_a_bits_a_mask_acc_T_8) node nodeOut_a_bits_a_mask_eq_9 = and(nodeOut_a_bits_a_mask_sub_0_2_1, UInt<1>(0h0)) node _nodeOut_a_bits_a_mask_acc_T_9 = and(nodeOut_a_bits_a_mask_size_1, nodeOut_a_bits_a_mask_eq_9) node nodeOut_a_bits_a_mask_acc_9 = or(nodeOut_a_bits_a_mask_sub_0_1_1, _nodeOut_a_bits_a_mask_acc_T_9) node nodeOut_a_bits_a_mask_eq_10 = and(nodeOut_a_bits_a_mask_sub_1_2_1, nodeOut_a_bits_a_mask_nbit_1) node _nodeOut_a_bits_a_mask_acc_T_10 = and(nodeOut_a_bits_a_mask_size_1, nodeOut_a_bits_a_mask_eq_10) node nodeOut_a_bits_a_mask_acc_10 = or(nodeOut_a_bits_a_mask_sub_1_1_1, _nodeOut_a_bits_a_mask_acc_T_10) node nodeOut_a_bits_a_mask_eq_11 = and(nodeOut_a_bits_a_mask_sub_1_2_1, UInt<1>(0h0)) node _nodeOut_a_bits_a_mask_acc_T_11 = and(nodeOut_a_bits_a_mask_size_1, nodeOut_a_bits_a_mask_eq_11) node nodeOut_a_bits_a_mask_acc_11 = or(nodeOut_a_bits_a_mask_sub_1_1_1, _nodeOut_a_bits_a_mask_acc_T_11) node nodeOut_a_bits_a_mask_eq_12 = and(nodeOut_a_bits_a_mask_sub_2_2_1, nodeOut_a_bits_a_mask_nbit_1) node _nodeOut_a_bits_a_mask_acc_T_12 = and(nodeOut_a_bits_a_mask_size_1, nodeOut_a_bits_a_mask_eq_12) node nodeOut_a_bits_a_mask_acc_12 = or(nodeOut_a_bits_a_mask_sub_2_1_1, _nodeOut_a_bits_a_mask_acc_T_12) node nodeOut_a_bits_a_mask_eq_13 = and(nodeOut_a_bits_a_mask_sub_2_2_1, UInt<1>(0h0)) node _nodeOut_a_bits_a_mask_acc_T_13 = and(nodeOut_a_bits_a_mask_size_1, nodeOut_a_bits_a_mask_eq_13) node nodeOut_a_bits_a_mask_acc_13 = or(nodeOut_a_bits_a_mask_sub_2_1_1, _nodeOut_a_bits_a_mask_acc_T_13) node nodeOut_a_bits_a_mask_eq_14 = and(nodeOut_a_bits_a_mask_sub_3_2_1, nodeOut_a_bits_a_mask_nbit_1) node _nodeOut_a_bits_a_mask_acc_T_14 = and(nodeOut_a_bits_a_mask_size_1, nodeOut_a_bits_a_mask_eq_14) node nodeOut_a_bits_a_mask_acc_14 = or(nodeOut_a_bits_a_mask_sub_3_1_1, _nodeOut_a_bits_a_mask_acc_T_14) node nodeOut_a_bits_a_mask_eq_15 = and(nodeOut_a_bits_a_mask_sub_3_2_1, UInt<1>(0h0)) node _nodeOut_a_bits_a_mask_acc_T_15 = and(nodeOut_a_bits_a_mask_size_1, nodeOut_a_bits_a_mask_eq_15) node nodeOut_a_bits_a_mask_acc_15 = or(nodeOut_a_bits_a_mask_sub_3_1_1, _nodeOut_a_bits_a_mask_acc_T_15) node nodeOut_a_bits_a_mask_lo_lo_1 = cat(nodeOut_a_bits_a_mask_acc_9, nodeOut_a_bits_a_mask_acc_8) node nodeOut_a_bits_a_mask_lo_hi_1 = cat(nodeOut_a_bits_a_mask_acc_11, nodeOut_a_bits_a_mask_acc_10) node nodeOut_a_bits_a_mask_lo_1 = cat(nodeOut_a_bits_a_mask_lo_hi_1, nodeOut_a_bits_a_mask_lo_lo_1) node nodeOut_a_bits_a_mask_hi_lo_1 = cat(nodeOut_a_bits_a_mask_acc_13, nodeOut_a_bits_a_mask_acc_12) node nodeOut_a_bits_a_mask_hi_hi_1 = cat(nodeOut_a_bits_a_mask_acc_15, nodeOut_a_bits_a_mask_acc_14) node nodeOut_a_bits_a_mask_hi_1 = cat(nodeOut_a_bits_a_mask_hi_hi_1, nodeOut_a_bits_a_mask_hi_lo_1) node _nodeOut_a_bits_a_mask_T_1 = cat(nodeOut_a_bits_a_mask_hi_1, nodeOut_a_bits_a_mask_lo_1) connect nodeOut_a_bits_a_1.mask, _nodeOut_a_bits_a_mask_T_1 connect nodeOut_a_bits_a_1.data, UInt<1>(0h1) connect nodeOut_a_bits_a_1.corrupt, UInt<1>(0h0) connect nodeOut.a.bits, nodeOut_a_bits_a_1 node _T_6 = and(nodeOut.a.ready, nodeOut.a.valid) when _T_6 : connect state, UInt<3>(0h4) else : node _T_7 = eq(UInt<3>(0h4), state) when _T_7 : node _T_8 = and(nodeOut.d.ready, nodeOut.d.valid) when _T_8 : connect state, UInt<3>(0h5) else : node _T_9 = eq(UInt<3>(0h5), state) when _T_9 : node _T_10 = eq(custom_boot, UInt<1>(0h0)) when _T_10 : connect state, UInt<3>(0h0) connect childClock, clockSinkNodeIn.clock connect childReset, clockSinkNodeIn.reset connect clock, clockSinkNodeIn.clock connect reset, clockSinkNodeIn.reset
module PeripheryBus_cbus( // @[ClockDomain.scala:14:9] input auto_coupler_to_prci_ctrl_fixer_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [20:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_prci_ctrl_fixer_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bootrom_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bootrom_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [16:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bootrom_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bootrom_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_debug_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_debug_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [11:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_debug_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_debug_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_plic_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_plic_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [27:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_plic_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_plic_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_clint_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_clint_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [25:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_clint_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_clint_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_pbus_bus_xing_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_pbus_bus_xing_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_l2_ctrl_buffer_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_l2_ctrl_buffer_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [25:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_l2_ctrl_buffer_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_l2_ctrl_buffer_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_5_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_5_reset, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_4_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_4_reset, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_3_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_3_reset, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_2_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_2_reset, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_1_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_1_reset, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_0_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_0_reset, // @[LazyModuleImp.scala:107:25] input auto_cbus_clock_groups_in_member_cbus_0_clock, // @[LazyModuleImp.scala:107:25] input auto_cbus_clock_groups_in_member_cbus_0_reset, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_bus_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_bus_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_bus_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25] input [7:0] auto_bus_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_bus_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_bus_xing_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_bus_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_bus_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_bus_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input custom_boot // @[CustomBootPin.scala:36:29] ); wire _coupler_to_prci_ctrl_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_prci_ctrl_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_prci_ctrl_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [1:0] _coupler_to_prci_ctrl_auto_tl_in_d_bits_param; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_prci_ctrl_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [6:0] _coupler_to_prci_ctrl_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire _coupler_to_prci_ctrl_auto_tl_in_d_bits_sink; // @[LazyScope.scala:98:27] wire _coupler_to_prci_ctrl_auto_tl_in_d_bits_denied; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_prci_ctrl_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_prci_ctrl_auto_tl_in_d_bits_corrupt; // @[LazyScope.scala:98:27] wire _coupler_to_bootrom_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_bootrom_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_bootrom_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [6:0] _coupler_to_bootrom_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_bootrom_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_debug_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_debug_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_debug_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_debug_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [6:0] _coupler_to_debug_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_debug_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_plic_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_plic_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_plic_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_plic_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [6:0] _coupler_to_plic_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_plic_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_clint_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_clint_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_clint_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_clint_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [6:0] _coupler_to_clint_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_clint_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_l2_ctrl_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_l2_ctrl_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_l2_ctrl_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [1:0] _coupler_to_l2_ctrl_auto_tl_in_d_bits_param; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_l2_ctrl_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [6:0] _coupler_to_l2_ctrl_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire _coupler_to_l2_ctrl_auto_tl_in_d_bits_sink; // @[LazyScope.scala:98:27] wire _coupler_to_l2_ctrl_auto_tl_in_d_bits_denied; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_l2_ctrl_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_l2_ctrl_auto_tl_in_d_bits_corrupt; // @[LazyScope.scala:98:27] wire _wrapped_error_device_auto_buffer_in_a_ready; // @[LazyScope.scala:98:27] wire _wrapped_error_device_auto_buffer_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _wrapped_error_device_auto_buffer_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [1:0] _wrapped_error_device_auto_buffer_in_d_bits_param; // @[LazyScope.scala:98:27] wire [3:0] _wrapped_error_device_auto_buffer_in_d_bits_size; // @[LazyScope.scala:98:27] wire [6:0] _wrapped_error_device_auto_buffer_in_d_bits_source; // @[LazyScope.scala:98:27] wire _wrapped_error_device_auto_buffer_in_d_bits_sink; // @[LazyScope.scala:98:27] wire _wrapped_error_device_auto_buffer_in_d_bits_denied; // @[LazyScope.scala:98:27] wire [63:0] _wrapped_error_device_auto_buffer_in_d_bits_data; // @[LazyScope.scala:98:27] wire _wrapped_error_device_auto_buffer_in_d_bits_corrupt; // @[LazyScope.scala:98:27] wire _atomics_auto_in_a_ready; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_in_d_valid; // @[AtomicAutomata.scala:289:29] wire [2:0] _atomics_auto_in_d_bits_opcode; // @[AtomicAutomata.scala:289:29] wire [1:0] _atomics_auto_in_d_bits_param; // @[AtomicAutomata.scala:289:29] wire [3:0] _atomics_auto_in_d_bits_size; // @[AtomicAutomata.scala:289:29] wire [6:0] _atomics_auto_in_d_bits_source; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_in_d_bits_sink; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_in_d_bits_denied; // @[AtomicAutomata.scala:289:29] wire [63:0] _atomics_auto_in_d_bits_data; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_in_d_bits_corrupt; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_out_a_valid; // @[AtomicAutomata.scala:289:29] wire [2:0] _atomics_auto_out_a_bits_opcode; // @[AtomicAutomata.scala:289:29] wire [2:0] _atomics_auto_out_a_bits_param; // @[AtomicAutomata.scala:289:29] wire [3:0] _atomics_auto_out_a_bits_size; // @[AtomicAutomata.scala:289:29] wire [6:0] _atomics_auto_out_a_bits_source; // @[AtomicAutomata.scala:289:29] wire [28:0] _atomics_auto_out_a_bits_address; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_out_a_bits_user_amba_prot_bufferable; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_out_a_bits_user_amba_prot_modifiable; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_out_a_bits_user_amba_prot_readalloc; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_out_a_bits_user_amba_prot_writealloc; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_out_a_bits_user_amba_prot_privileged; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_out_a_bits_user_amba_prot_secure; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_out_a_bits_user_amba_prot_fetch; // @[AtomicAutomata.scala:289:29] wire [7:0] _atomics_auto_out_a_bits_mask; // @[AtomicAutomata.scala:289:29] wire [63:0] _atomics_auto_out_a_bits_data; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_out_a_bits_corrupt; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_out_d_ready; // @[AtomicAutomata.scala:289:29] wire _buffer_auto_in_a_ready; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_valid; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_in_d_bits_opcode; // @[Buffer.scala:75:28] wire [1:0] _buffer_auto_in_d_bits_param; // @[Buffer.scala:75:28] wire [3:0] _buffer_auto_in_d_bits_size; // @[Buffer.scala:75:28] wire [6:0] _buffer_auto_in_d_bits_source; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_sink; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_denied; // @[Buffer.scala:75:28] wire [63:0] _buffer_auto_in_d_bits_data; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:75:28] wire _buffer_auto_out_a_valid; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_out_a_bits_opcode; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_out_a_bits_param; // @[Buffer.scala:75:28] wire [3:0] _buffer_auto_out_a_bits_size; // @[Buffer.scala:75:28] wire [6:0] _buffer_auto_out_a_bits_source; // @[Buffer.scala:75:28] wire [28:0] _buffer_auto_out_a_bits_address; // @[Buffer.scala:75:28] wire _buffer_auto_out_a_bits_user_amba_prot_bufferable; // @[Buffer.scala:75:28] wire _buffer_auto_out_a_bits_user_amba_prot_modifiable; // @[Buffer.scala:75:28] wire _buffer_auto_out_a_bits_user_amba_prot_readalloc; // @[Buffer.scala:75:28] wire _buffer_auto_out_a_bits_user_amba_prot_writealloc; // @[Buffer.scala:75:28] wire _buffer_auto_out_a_bits_user_amba_prot_privileged; // @[Buffer.scala:75:28] wire _buffer_auto_out_a_bits_user_amba_prot_secure; // @[Buffer.scala:75:28] wire _buffer_auto_out_a_bits_user_amba_prot_fetch; // @[Buffer.scala:75:28] wire [7:0] _buffer_auto_out_a_bits_mask; // @[Buffer.scala:75:28] wire [63:0] _buffer_auto_out_a_bits_data; // @[Buffer.scala:75:28] wire _buffer_auto_out_a_bits_corrupt; // @[Buffer.scala:75:28] wire _buffer_auto_out_d_ready; // @[Buffer.scala:75:28] wire _out_xbar_auto_anon_in_a_ready; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_in_d_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_in_d_bits_opcode; // @[PeripheryBus.scala:57:30] wire [1:0] _out_xbar_auto_anon_in_d_bits_param; // @[PeripheryBus.scala:57:30] wire [3:0] _out_xbar_auto_anon_in_d_bits_size; // @[PeripheryBus.scala:57:30] wire [6:0] _out_xbar_auto_anon_in_d_bits_source; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_in_d_bits_sink; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_in_d_bits_denied; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_in_d_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_in_d_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_7_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_7_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_7_a_bits_param; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_7_a_bits_size; // @[PeripheryBus.scala:57:30] wire [6:0] _out_xbar_auto_anon_out_7_a_bits_source; // @[PeripheryBus.scala:57:30] wire [20:0] _out_xbar_auto_anon_out_7_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_7_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_7_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_7_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_7_d_ready; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_6_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_6_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_6_a_bits_param; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_6_a_bits_size; // @[PeripheryBus.scala:57:30] wire [6:0] _out_xbar_auto_anon_out_6_a_bits_source; // @[PeripheryBus.scala:57:30] wire [16:0] _out_xbar_auto_anon_out_6_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_6_a_bits_mask; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_6_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_6_d_ready; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_5_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_5_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_5_a_bits_param; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_5_a_bits_size; // @[PeripheryBus.scala:57:30] wire [6:0] _out_xbar_auto_anon_out_5_a_bits_source; // @[PeripheryBus.scala:57:30] wire [11:0] _out_xbar_auto_anon_out_5_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_5_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_5_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_5_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_5_d_ready; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_4_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_4_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_4_a_bits_param; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_4_a_bits_size; // @[PeripheryBus.scala:57:30] wire [6:0] _out_xbar_auto_anon_out_4_a_bits_source; // @[PeripheryBus.scala:57:30] wire [27:0] _out_xbar_auto_anon_out_4_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_4_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_4_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_4_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_4_d_ready; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_3_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_3_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_3_a_bits_param; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_3_a_bits_size; // @[PeripheryBus.scala:57:30] wire [6:0] _out_xbar_auto_anon_out_3_a_bits_source; // @[PeripheryBus.scala:57:30] wire [25:0] _out_xbar_auto_anon_out_3_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_3_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_3_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_3_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_3_d_ready; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_1_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_1_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_1_a_bits_param; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_1_a_bits_size; // @[PeripheryBus.scala:57:30] wire [6:0] _out_xbar_auto_anon_out_1_a_bits_source; // @[PeripheryBus.scala:57:30] wire [25:0] _out_xbar_auto_anon_out_1_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_1_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_1_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_1_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_1_d_ready; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_0_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_0_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_0_a_bits_param; // @[PeripheryBus.scala:57:30] wire [3:0] _out_xbar_auto_anon_out_0_a_bits_size; // @[PeripheryBus.scala:57:30] wire [6:0] _out_xbar_auto_anon_out_0_a_bits_source; // @[PeripheryBus.scala:57:30] wire [13:0] _out_xbar_auto_anon_out_0_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_0_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_0_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_0_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_0_d_ready; // @[PeripheryBus.scala:57:30] wire _in_xbar_auto_anon_in_1_a_ready; // @[PeripheryBus.scala:56:29] wire _in_xbar_auto_anon_in_1_d_valid; // @[PeripheryBus.scala:56:29] wire _in_xbar_auto_anon_out_a_valid; // @[PeripheryBus.scala:56:29] wire [2:0] _in_xbar_auto_anon_out_a_bits_opcode; // @[PeripheryBus.scala:56:29] wire [2:0] _in_xbar_auto_anon_out_a_bits_param; // @[PeripheryBus.scala:56:29] wire [3:0] _in_xbar_auto_anon_out_a_bits_size; // @[PeripheryBus.scala:56:29] wire [6:0] _in_xbar_auto_anon_out_a_bits_source; // @[PeripheryBus.scala:56:29] wire [28:0] _in_xbar_auto_anon_out_a_bits_address; // @[PeripheryBus.scala:56:29] wire _in_xbar_auto_anon_out_a_bits_user_amba_prot_bufferable; // @[PeripheryBus.scala:56:29] wire _in_xbar_auto_anon_out_a_bits_user_amba_prot_modifiable; // @[PeripheryBus.scala:56:29] wire _in_xbar_auto_anon_out_a_bits_user_amba_prot_readalloc; // @[PeripheryBus.scala:56:29] wire _in_xbar_auto_anon_out_a_bits_user_amba_prot_writealloc; // @[PeripheryBus.scala:56:29] wire _in_xbar_auto_anon_out_a_bits_user_amba_prot_privileged; // @[PeripheryBus.scala:56:29] wire _in_xbar_auto_anon_out_a_bits_user_amba_prot_secure; // @[PeripheryBus.scala:56:29] wire _in_xbar_auto_anon_out_a_bits_user_amba_prot_fetch; // @[PeripheryBus.scala:56:29] wire [7:0] _in_xbar_auto_anon_out_a_bits_mask; // @[PeripheryBus.scala:56:29] wire [63:0] _in_xbar_auto_anon_out_a_bits_data; // @[PeripheryBus.scala:56:29] wire _in_xbar_auto_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:56:29] wire _in_xbar_auto_anon_out_d_ready; // @[PeripheryBus.scala:56:29] wire _fixedClockNode_auto_anon_out_0_clock; // @[ClockGroup.scala:115:114] wire _fixedClockNode_auto_anon_out_0_reset; // @[ClockGroup.scala:115:114] reg [2:0] state; // @[CustomBootPin.scala:39:28] wire _GEN = state == 3'h1; // @[CustomBootPin.scala:39:28, :43:24] wire nodeOut_a_valid = (|state) & (_GEN | state != 3'h2 & state == 3'h3); // @[CustomBootPin.scala:39:28, :40:20, :43:24, :46:24] wire _GEN_0 = _in_xbar_auto_anon_in_1_a_ready & nodeOut_a_valid; // @[Decoupled.scala:51:35] wire [2:0] _GEN_1 = state == 3'h5 & ~custom_boot ? 3'h0 : state; // @[CustomBootPin.scala:39:28, :43:24, :67:{29,43,51}] wire [7:0][2:0] _GEN_2 = {{_GEN_1}, {_GEN_1}, {_GEN_1}, {_in_xbar_auto_anon_in_1_d_valid ? 3'h5 : state}, {_GEN_0 ? 3'h4 : state}, {_in_xbar_auto_anon_in_1_d_valid ? 3'h3 : state}, {_GEN_0 ? 3'h2 : state}, {custom_boot ? 3'h1 : state}}; // @[Decoupled.scala:51:35] always @(posedge _fixedClockNode_auto_anon_out_0_clock) begin // @[ClockGroup.scala:115:114] if (_fixedClockNode_auto_anon_out_0_reset) // @[ClockGroup.scala:115:114] state <= 3'h0; // @[CustomBootPin.scala:39:28] else // @[ClockGroup.scala:115:114] state <= _GEN_2[state]; // @[CustomBootPin.scala:39:28, :43:24, :44:46, :53:30, :55:58, :64:30, :66:50] always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module IssueUnitCollapsing_2 : input clock : Clock input reset : Reset output io : { flip dis_uops : { flip ready : UInt<1>, valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}[3], iss_uops : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}[1], flip wakeup_ports : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}}[5], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip child_rebusys : UInt<3>, flip fu_types : UInt<1>[10][1], flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip flush_pipeline : UInt<1>, flip squash_grant : UInt<1>, flip tsc_reg : UInt<64>} wire _WIRE : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} wire _WIRE_1 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} wire _WIRE_2 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect _WIRE, io.dis_uops[0].bits connect _WIRE.iw_issued, UInt<1>(0h0) connect _WIRE.iw_issued_partial_agen, UInt<1>(0h0) connect _WIRE.iw_issued_partial_dgen, UInt<1>(0h0) connect _WIRE.iw_p1_bypass_hint, UInt<1>(0h0) connect _WIRE.iw_p2_bypass_hint, UInt<1>(0h0) connect _WIRE.iw_p3_bypass_hint, UInt<1>(0h0) node prs1_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, io.dis_uops[0].bits.prs1) node prs1_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, io.dis_uops[0].bits.prs1) node prs1_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, io.dis_uops[0].bits.prs1) node prs1_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, io.dis_uops[0].bits.prs1) node prs1_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, io.dis_uops[0].bits.prs1) node prs2_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, io.dis_uops[0].bits.prs2) node prs2_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, io.dis_uops[0].bits.prs2) node prs2_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, io.dis_uops[0].bits.prs2) node prs2_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, io.dis_uops[0].bits.prs2) node prs2_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, io.dis_uops[0].bits.prs2) node prs3_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, io.dis_uops[0].bits.prs3) node prs3_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, io.dis_uops[0].bits.prs3) node prs3_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, io.dis_uops[0].bits.prs3) node prs3_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, io.dis_uops[0].bits.prs3) node prs3_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, io.dis_uops[0].bits.prs3) node prs1_wakeups_0 = and(io.wakeup_ports[0].valid, prs1_matches_0) node prs1_wakeups_1 = and(io.wakeup_ports[1].valid, prs1_matches_1) node prs1_wakeups_2 = and(io.wakeup_ports[2].valid, prs1_matches_2) node prs1_wakeups_3 = and(io.wakeup_ports[3].valid, prs1_matches_3) node prs1_wakeups_4 = and(io.wakeup_ports[4].valid, prs1_matches_4) node prs2_wakeups_0 = and(io.wakeup_ports[0].valid, prs2_matches_0) node prs2_wakeups_1 = and(io.wakeup_ports[1].valid, prs2_matches_1) node prs2_wakeups_2 = and(io.wakeup_ports[2].valid, prs2_matches_2) node prs2_wakeups_3 = and(io.wakeup_ports[3].valid, prs2_matches_3) node prs2_wakeups_4 = and(io.wakeup_ports[4].valid, prs2_matches_4) node prs3_wakeups_0 = and(io.wakeup_ports[0].valid, prs3_matches_0) node prs3_wakeups_1 = and(io.wakeup_ports[1].valid, prs3_matches_1) node prs3_wakeups_2 = and(io.wakeup_ports[2].valid, prs3_matches_2) node prs3_wakeups_3 = and(io.wakeup_ports[3].valid, prs3_matches_3) node prs3_wakeups_4 = and(io.wakeup_ports[4].valid, prs3_matches_4) node prs1_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs1_matches_0) node prs1_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs1_matches_1) node prs1_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs1_matches_2) node prs1_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs1_matches_3) node prs1_rebusys_4 = and(io.wakeup_ports[4].bits.rebusy, prs1_matches_4) node prs2_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs2_matches_0) node prs2_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs2_matches_1) node prs2_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs2_matches_2) node prs2_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs2_matches_3) node prs2_rebusys_4 = and(io.wakeup_ports[4].bits.rebusy, prs2_matches_4) node _T = or(prs1_wakeups_0, prs1_wakeups_1) node _T_1 = or(_T, prs1_wakeups_2) node _T_2 = or(_T_1, prs1_wakeups_3) node _T_3 = or(_T_2, prs1_wakeups_4) when _T_3 : connect _WIRE.prs1_busy, UInt<1>(0h0) node _T_4 = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) node _T_5 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) node _T_6 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0)) node _T_7 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0)) node _T_8 = mux(prs1_wakeups_4, io.wakeup_ports[4].bits.speculative_mask, UInt<1>(0h0)) node _T_9 = or(_T_4, _T_5) node _T_10 = or(_T_9, _T_6) node _T_11 = or(_T_10, _T_7) node _T_12 = or(_T_11, _T_8) wire _WIRE_3 : UInt<3> connect _WIRE_3, _T_12 connect _WIRE.iw_p1_speculative_child, _WIRE_3 node _T_13 = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _T_14 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _T_15 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) node _T_16 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) node _T_17 = mux(prs1_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0)) node _T_18 = or(_T_13, _T_14) node _T_19 = or(_T_18, _T_15) node _T_20 = or(_T_19, _T_16) node _T_21 = or(_T_20, _T_17) wire _WIRE_4 : UInt<1> connect _WIRE_4, _T_21 connect _WIRE.iw_p1_bypass_hint, _WIRE_4 node _T_22 = or(prs1_rebusys_0, prs1_rebusys_1) node _T_23 = or(_T_22, prs1_rebusys_2) node _T_24 = or(_T_23, prs1_rebusys_3) node _T_25 = or(_T_24, prs1_rebusys_4) node _T_26 = and(io.child_rebusys, io.dis_uops[0].bits.iw_p1_speculative_child) node _T_27 = neq(_T_26, UInt<1>(0h0)) node _T_28 = or(_T_25, _T_27) when _T_28 : node _T_29 = eq(io.dis_uops[0].bits.lrs1_rtype, UInt<2>(0h0)) connect _WIRE.prs1_busy, _T_29 node _T_30 = or(prs2_wakeups_0, prs2_wakeups_1) node _T_31 = or(_T_30, prs2_wakeups_2) node _T_32 = or(_T_31, prs2_wakeups_3) node _T_33 = or(_T_32, prs2_wakeups_4) when _T_33 : connect _WIRE.prs2_busy, UInt<1>(0h0) node _T_34 = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) node _T_35 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) node _T_36 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0)) node _T_37 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0)) node _T_38 = mux(prs2_wakeups_4, io.wakeup_ports[4].bits.speculative_mask, UInt<1>(0h0)) node _T_39 = or(_T_34, _T_35) node _T_40 = or(_T_39, _T_36) node _T_41 = or(_T_40, _T_37) node _T_42 = or(_T_41, _T_38) wire _WIRE_5 : UInt<3> connect _WIRE_5, _T_42 connect _WIRE.iw_p2_speculative_child, _WIRE_5 node _T_43 = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _T_44 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _T_45 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) node _T_46 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) node _T_47 = mux(prs2_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0)) node _T_48 = or(_T_43, _T_44) node _T_49 = or(_T_48, _T_45) node _T_50 = or(_T_49, _T_46) node _T_51 = or(_T_50, _T_47) wire _WIRE_6 : UInt<1> connect _WIRE_6, _T_51 connect _WIRE.iw_p2_bypass_hint, _WIRE_6 node _T_52 = or(prs2_rebusys_0, prs2_rebusys_1) node _T_53 = or(_T_52, prs2_rebusys_2) node _T_54 = or(_T_53, prs2_rebusys_3) node _T_55 = or(_T_54, prs2_rebusys_4) node _T_56 = and(io.child_rebusys, io.dis_uops[0].bits.iw_p2_speculative_child) node _T_57 = neq(_T_56, UInt<1>(0h0)) node _T_58 = or(_T_55, _T_57) when _T_58 : node _T_59 = eq(io.dis_uops[0].bits.lrs2_rtype, UInt<2>(0h0)) connect _WIRE.prs2_busy, _T_59 node _T_60 = or(prs3_wakeups_0, prs3_wakeups_1) node _T_61 = or(_T_60, prs3_wakeups_2) node _T_62 = or(_T_61, prs3_wakeups_3) node _T_63 = or(_T_62, prs3_wakeups_4) when _T_63 : connect _WIRE.prs3_busy, UInt<1>(0h0) node _T_64 = mux(prs3_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _T_65 = mux(prs3_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _T_66 = mux(prs3_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) node _T_67 = mux(prs3_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) node _T_68 = mux(prs3_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0)) node _T_69 = or(_T_64, _T_65) node _T_70 = or(_T_69, _T_66) node _T_71 = or(_T_70, _T_67) node _T_72 = or(_T_71, _T_68) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_72 connect _WIRE.iw_p3_bypass_hint, _WIRE_7 node _T_73 = eq(io.pred_wakeup_port.bits, io.dis_uops[0].bits.ppred) node _T_74 = and(io.pred_wakeup_port.valid, _T_73) when _T_74 : connect _WIRE.ppred_busy, UInt<1>(0h0) when io.dis_uops[0].bits.fu_code[8] : node _T_75 = cat(io.dis_uops[0].bits.fp_rm, io.dis_uops[0].bits.fp_typ) connect _WIRE.prs2, _T_75 when io.dis_uops[0].bits.is_sfence : connect _WIRE.pimm, io.dis_uops[0].bits.mem_size node _T_76 = and(io.dis_uops[0].bits.ppred_busy, io.dis_uops[0].valid) node _T_77 = eq(_T_76, UInt<1>(0h0)) node _T_78 = asUInt(reset) node _T_79 = eq(_T_78, UInt<1>(0h0)) when _T_79 : node _T_80 = eq(_T_77, UInt<1>(0h0)) when _T_80 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-unit-age-ordered.scala:110 assert(!(io.dis_uops(w).bits.ppred_busy && io.dis_uops(w).valid))\n") : printf assert(clock, _T_77, UInt<1>(0h1), "") : assert connect _WIRE.ppred_busy, UInt<1>(0h0) connect _WIRE_1, io.dis_uops[1].bits connect _WIRE_1.iw_issued, UInt<1>(0h0) connect _WIRE_1.iw_issued_partial_agen, UInt<1>(0h0) connect _WIRE_1.iw_issued_partial_dgen, UInt<1>(0h0) connect _WIRE_1.iw_p1_bypass_hint, UInt<1>(0h0) connect _WIRE_1.iw_p2_bypass_hint, UInt<1>(0h0) connect _WIRE_1.iw_p3_bypass_hint, UInt<1>(0h0) node prs1_matches_0_1 = eq(io.wakeup_ports[0].bits.uop.pdst, io.dis_uops[1].bits.prs1) node prs1_matches_1_1 = eq(io.wakeup_ports[1].bits.uop.pdst, io.dis_uops[1].bits.prs1) node prs1_matches_2_1 = eq(io.wakeup_ports[2].bits.uop.pdst, io.dis_uops[1].bits.prs1) node prs1_matches_3_1 = eq(io.wakeup_ports[3].bits.uop.pdst, io.dis_uops[1].bits.prs1) node prs1_matches_4_1 = eq(io.wakeup_ports[4].bits.uop.pdst, io.dis_uops[1].bits.prs1) node prs2_matches_0_1 = eq(io.wakeup_ports[0].bits.uop.pdst, io.dis_uops[1].bits.prs2) node prs2_matches_1_1 = eq(io.wakeup_ports[1].bits.uop.pdst, io.dis_uops[1].bits.prs2) node prs2_matches_2_1 = eq(io.wakeup_ports[2].bits.uop.pdst, io.dis_uops[1].bits.prs2) node prs2_matches_3_1 = eq(io.wakeup_ports[3].bits.uop.pdst, io.dis_uops[1].bits.prs2) node prs2_matches_4_1 = eq(io.wakeup_ports[4].bits.uop.pdst, io.dis_uops[1].bits.prs2) node prs3_matches_0_1 = eq(io.wakeup_ports[0].bits.uop.pdst, io.dis_uops[1].bits.prs3) node prs3_matches_1_1 = eq(io.wakeup_ports[1].bits.uop.pdst, io.dis_uops[1].bits.prs3) node prs3_matches_2_1 = eq(io.wakeup_ports[2].bits.uop.pdst, io.dis_uops[1].bits.prs3) node prs3_matches_3_1 = eq(io.wakeup_ports[3].bits.uop.pdst, io.dis_uops[1].bits.prs3) node prs3_matches_4_1 = eq(io.wakeup_ports[4].bits.uop.pdst, io.dis_uops[1].bits.prs3) node prs1_wakeups_0_1 = and(io.wakeup_ports[0].valid, prs1_matches_0_1) node prs1_wakeups_1_1 = and(io.wakeup_ports[1].valid, prs1_matches_1_1) node prs1_wakeups_2_1 = and(io.wakeup_ports[2].valid, prs1_matches_2_1) node prs1_wakeups_3_1 = and(io.wakeup_ports[3].valid, prs1_matches_3_1) node prs1_wakeups_4_1 = and(io.wakeup_ports[4].valid, prs1_matches_4_1) node prs2_wakeups_0_1 = and(io.wakeup_ports[0].valid, prs2_matches_0_1) node prs2_wakeups_1_1 = and(io.wakeup_ports[1].valid, prs2_matches_1_1) node prs2_wakeups_2_1 = and(io.wakeup_ports[2].valid, prs2_matches_2_1) node prs2_wakeups_3_1 = and(io.wakeup_ports[3].valid, prs2_matches_3_1) node prs2_wakeups_4_1 = and(io.wakeup_ports[4].valid, prs2_matches_4_1) node prs3_wakeups_0_1 = and(io.wakeup_ports[0].valid, prs3_matches_0_1) node prs3_wakeups_1_1 = and(io.wakeup_ports[1].valid, prs3_matches_1_1) node prs3_wakeups_2_1 = and(io.wakeup_ports[2].valid, prs3_matches_2_1) node prs3_wakeups_3_1 = and(io.wakeup_ports[3].valid, prs3_matches_3_1) node prs3_wakeups_4_1 = and(io.wakeup_ports[4].valid, prs3_matches_4_1) node prs1_rebusys_0_1 = and(io.wakeup_ports[0].bits.rebusy, prs1_matches_0_1) node prs1_rebusys_1_1 = and(io.wakeup_ports[1].bits.rebusy, prs1_matches_1_1) node prs1_rebusys_2_1 = and(io.wakeup_ports[2].bits.rebusy, prs1_matches_2_1) node prs1_rebusys_3_1 = and(io.wakeup_ports[3].bits.rebusy, prs1_matches_3_1) node prs1_rebusys_4_1 = and(io.wakeup_ports[4].bits.rebusy, prs1_matches_4_1) node prs2_rebusys_0_1 = and(io.wakeup_ports[0].bits.rebusy, prs2_matches_0_1) node prs2_rebusys_1_1 = and(io.wakeup_ports[1].bits.rebusy, prs2_matches_1_1) node prs2_rebusys_2_1 = and(io.wakeup_ports[2].bits.rebusy, prs2_matches_2_1) node prs2_rebusys_3_1 = and(io.wakeup_ports[3].bits.rebusy, prs2_matches_3_1) node prs2_rebusys_4_1 = and(io.wakeup_ports[4].bits.rebusy, prs2_matches_4_1) node _T_81 = or(prs1_wakeups_0_1, prs1_wakeups_1_1) node _T_82 = or(_T_81, prs1_wakeups_2_1) node _T_83 = or(_T_82, prs1_wakeups_3_1) node _T_84 = or(_T_83, prs1_wakeups_4_1) when _T_84 : connect _WIRE_1.prs1_busy, UInt<1>(0h0) node _T_85 = mux(prs1_wakeups_0_1, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) node _T_86 = mux(prs1_wakeups_1_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) node _T_87 = mux(prs1_wakeups_2_1, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0)) node _T_88 = mux(prs1_wakeups_3_1, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0)) node _T_89 = mux(prs1_wakeups_4_1, io.wakeup_ports[4].bits.speculative_mask, UInt<1>(0h0)) node _T_90 = or(_T_85, _T_86) node _T_91 = or(_T_90, _T_87) node _T_92 = or(_T_91, _T_88) node _T_93 = or(_T_92, _T_89) wire _WIRE_8 : UInt<3> connect _WIRE_8, _T_93 connect _WIRE_1.iw_p1_speculative_child, _WIRE_8 node _T_94 = mux(prs1_wakeups_0_1, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _T_95 = mux(prs1_wakeups_1_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _T_96 = mux(prs1_wakeups_2_1, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) node _T_97 = mux(prs1_wakeups_3_1, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) node _T_98 = mux(prs1_wakeups_4_1, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0)) node _T_99 = or(_T_94, _T_95) node _T_100 = or(_T_99, _T_96) node _T_101 = or(_T_100, _T_97) node _T_102 = or(_T_101, _T_98) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_102 connect _WIRE_1.iw_p1_bypass_hint, _WIRE_9 node _T_103 = or(prs1_rebusys_0_1, prs1_rebusys_1_1) node _T_104 = or(_T_103, prs1_rebusys_2_1) node _T_105 = or(_T_104, prs1_rebusys_3_1) node _T_106 = or(_T_105, prs1_rebusys_4_1) node _T_107 = and(io.child_rebusys, io.dis_uops[1].bits.iw_p1_speculative_child) node _T_108 = neq(_T_107, UInt<1>(0h0)) node _T_109 = or(_T_106, _T_108) when _T_109 : node _T_110 = eq(io.dis_uops[1].bits.lrs1_rtype, UInt<2>(0h0)) connect _WIRE_1.prs1_busy, _T_110 node _T_111 = or(prs2_wakeups_0_1, prs2_wakeups_1_1) node _T_112 = or(_T_111, prs2_wakeups_2_1) node _T_113 = or(_T_112, prs2_wakeups_3_1) node _T_114 = or(_T_113, prs2_wakeups_4_1) when _T_114 : connect _WIRE_1.prs2_busy, UInt<1>(0h0) node _T_115 = mux(prs2_wakeups_0_1, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) node _T_116 = mux(prs2_wakeups_1_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) node _T_117 = mux(prs2_wakeups_2_1, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0)) node _T_118 = mux(prs2_wakeups_3_1, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0)) node _T_119 = mux(prs2_wakeups_4_1, io.wakeup_ports[4].bits.speculative_mask, UInt<1>(0h0)) node _T_120 = or(_T_115, _T_116) node _T_121 = or(_T_120, _T_117) node _T_122 = or(_T_121, _T_118) node _T_123 = or(_T_122, _T_119) wire _WIRE_10 : UInt<3> connect _WIRE_10, _T_123 connect _WIRE_1.iw_p2_speculative_child, _WIRE_10 node _T_124 = mux(prs2_wakeups_0_1, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _T_125 = mux(prs2_wakeups_1_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _T_126 = mux(prs2_wakeups_2_1, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) node _T_127 = mux(prs2_wakeups_3_1, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) node _T_128 = mux(prs2_wakeups_4_1, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0)) node _T_129 = or(_T_124, _T_125) node _T_130 = or(_T_129, _T_126) node _T_131 = or(_T_130, _T_127) node _T_132 = or(_T_131, _T_128) wire _WIRE_11 : UInt<1> connect _WIRE_11, _T_132 connect _WIRE_1.iw_p2_bypass_hint, _WIRE_11 node _T_133 = or(prs2_rebusys_0_1, prs2_rebusys_1_1) node _T_134 = or(_T_133, prs2_rebusys_2_1) node _T_135 = or(_T_134, prs2_rebusys_3_1) node _T_136 = or(_T_135, prs2_rebusys_4_1) node _T_137 = and(io.child_rebusys, io.dis_uops[1].bits.iw_p2_speculative_child) node _T_138 = neq(_T_137, UInt<1>(0h0)) node _T_139 = or(_T_136, _T_138) when _T_139 : node _T_140 = eq(io.dis_uops[1].bits.lrs2_rtype, UInt<2>(0h0)) connect _WIRE_1.prs2_busy, _T_140 node _T_141 = or(prs3_wakeups_0_1, prs3_wakeups_1_1) node _T_142 = or(_T_141, prs3_wakeups_2_1) node _T_143 = or(_T_142, prs3_wakeups_3_1) node _T_144 = or(_T_143, prs3_wakeups_4_1) when _T_144 : connect _WIRE_1.prs3_busy, UInt<1>(0h0) node _T_145 = mux(prs3_wakeups_0_1, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _T_146 = mux(prs3_wakeups_1_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _T_147 = mux(prs3_wakeups_2_1, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) node _T_148 = mux(prs3_wakeups_3_1, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) node _T_149 = mux(prs3_wakeups_4_1, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0)) node _T_150 = or(_T_145, _T_146) node _T_151 = or(_T_150, _T_147) node _T_152 = or(_T_151, _T_148) node _T_153 = or(_T_152, _T_149) wire _WIRE_12 : UInt<1> connect _WIRE_12, _T_153 connect _WIRE_1.iw_p3_bypass_hint, _WIRE_12 node _T_154 = eq(io.pred_wakeup_port.bits, io.dis_uops[1].bits.ppred) node _T_155 = and(io.pred_wakeup_port.valid, _T_154) when _T_155 : connect _WIRE_1.ppred_busy, UInt<1>(0h0) when io.dis_uops[1].bits.fu_code[8] : node _T_156 = cat(io.dis_uops[1].bits.fp_rm, io.dis_uops[1].bits.fp_typ) connect _WIRE_1.prs2, _T_156 when io.dis_uops[1].bits.is_sfence : connect _WIRE_1.pimm, io.dis_uops[1].bits.mem_size node _T_157 = and(io.dis_uops[1].bits.ppred_busy, io.dis_uops[1].valid) node _T_158 = eq(_T_157, UInt<1>(0h0)) node _T_159 = asUInt(reset) node _T_160 = eq(_T_159, UInt<1>(0h0)) when _T_160 : node _T_161 = eq(_T_158, UInt<1>(0h0)) when _T_161 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-unit-age-ordered.scala:110 assert(!(io.dis_uops(w).bits.ppred_busy && io.dis_uops(w).valid))\n") : printf_1 assert(clock, _T_158, UInt<1>(0h1), "") : assert_1 connect _WIRE_1.ppred_busy, UInt<1>(0h0) connect _WIRE_2, io.dis_uops[2].bits connect _WIRE_2.iw_issued, UInt<1>(0h0) connect _WIRE_2.iw_issued_partial_agen, UInt<1>(0h0) connect _WIRE_2.iw_issued_partial_dgen, UInt<1>(0h0) connect _WIRE_2.iw_p1_bypass_hint, UInt<1>(0h0) connect _WIRE_2.iw_p2_bypass_hint, UInt<1>(0h0) connect _WIRE_2.iw_p3_bypass_hint, UInt<1>(0h0) node prs1_matches_0_2 = eq(io.wakeup_ports[0].bits.uop.pdst, io.dis_uops[2].bits.prs1) node prs1_matches_1_2 = eq(io.wakeup_ports[1].bits.uop.pdst, io.dis_uops[2].bits.prs1) node prs1_matches_2_2 = eq(io.wakeup_ports[2].bits.uop.pdst, io.dis_uops[2].bits.prs1) node prs1_matches_3_2 = eq(io.wakeup_ports[3].bits.uop.pdst, io.dis_uops[2].bits.prs1) node prs1_matches_4_2 = eq(io.wakeup_ports[4].bits.uop.pdst, io.dis_uops[2].bits.prs1) node prs2_matches_0_2 = eq(io.wakeup_ports[0].bits.uop.pdst, io.dis_uops[2].bits.prs2) node prs2_matches_1_2 = eq(io.wakeup_ports[1].bits.uop.pdst, io.dis_uops[2].bits.prs2) node prs2_matches_2_2 = eq(io.wakeup_ports[2].bits.uop.pdst, io.dis_uops[2].bits.prs2) node prs2_matches_3_2 = eq(io.wakeup_ports[3].bits.uop.pdst, io.dis_uops[2].bits.prs2) node prs2_matches_4_2 = eq(io.wakeup_ports[4].bits.uop.pdst, io.dis_uops[2].bits.prs2) node prs3_matches_0_2 = eq(io.wakeup_ports[0].bits.uop.pdst, io.dis_uops[2].bits.prs3) node prs3_matches_1_2 = eq(io.wakeup_ports[1].bits.uop.pdst, io.dis_uops[2].bits.prs3) node prs3_matches_2_2 = eq(io.wakeup_ports[2].bits.uop.pdst, io.dis_uops[2].bits.prs3) node prs3_matches_3_2 = eq(io.wakeup_ports[3].bits.uop.pdst, io.dis_uops[2].bits.prs3) node prs3_matches_4_2 = eq(io.wakeup_ports[4].bits.uop.pdst, io.dis_uops[2].bits.prs3) node prs1_wakeups_0_2 = and(io.wakeup_ports[0].valid, prs1_matches_0_2) node prs1_wakeups_1_2 = and(io.wakeup_ports[1].valid, prs1_matches_1_2) node prs1_wakeups_2_2 = and(io.wakeup_ports[2].valid, prs1_matches_2_2) node prs1_wakeups_3_2 = and(io.wakeup_ports[3].valid, prs1_matches_3_2) node prs1_wakeups_4_2 = and(io.wakeup_ports[4].valid, prs1_matches_4_2) node prs2_wakeups_0_2 = and(io.wakeup_ports[0].valid, prs2_matches_0_2) node prs2_wakeups_1_2 = and(io.wakeup_ports[1].valid, prs2_matches_1_2) node prs2_wakeups_2_2 = and(io.wakeup_ports[2].valid, prs2_matches_2_2) node prs2_wakeups_3_2 = and(io.wakeup_ports[3].valid, prs2_matches_3_2) node prs2_wakeups_4_2 = and(io.wakeup_ports[4].valid, prs2_matches_4_2) node prs3_wakeups_0_2 = and(io.wakeup_ports[0].valid, prs3_matches_0_2) node prs3_wakeups_1_2 = and(io.wakeup_ports[1].valid, prs3_matches_1_2) node prs3_wakeups_2_2 = and(io.wakeup_ports[2].valid, prs3_matches_2_2) node prs3_wakeups_3_2 = and(io.wakeup_ports[3].valid, prs3_matches_3_2) node prs3_wakeups_4_2 = and(io.wakeup_ports[4].valid, prs3_matches_4_2) node prs1_rebusys_0_2 = and(io.wakeup_ports[0].bits.rebusy, prs1_matches_0_2) node prs1_rebusys_1_2 = and(io.wakeup_ports[1].bits.rebusy, prs1_matches_1_2) node prs1_rebusys_2_2 = and(io.wakeup_ports[2].bits.rebusy, prs1_matches_2_2) node prs1_rebusys_3_2 = and(io.wakeup_ports[3].bits.rebusy, prs1_matches_3_2) node prs1_rebusys_4_2 = and(io.wakeup_ports[4].bits.rebusy, prs1_matches_4_2) node prs2_rebusys_0_2 = and(io.wakeup_ports[0].bits.rebusy, prs2_matches_0_2) node prs2_rebusys_1_2 = and(io.wakeup_ports[1].bits.rebusy, prs2_matches_1_2) node prs2_rebusys_2_2 = and(io.wakeup_ports[2].bits.rebusy, prs2_matches_2_2) node prs2_rebusys_3_2 = and(io.wakeup_ports[3].bits.rebusy, prs2_matches_3_2) node prs2_rebusys_4_2 = and(io.wakeup_ports[4].bits.rebusy, prs2_matches_4_2) node _T_162 = or(prs1_wakeups_0_2, prs1_wakeups_1_2) node _T_163 = or(_T_162, prs1_wakeups_2_2) node _T_164 = or(_T_163, prs1_wakeups_3_2) node _T_165 = or(_T_164, prs1_wakeups_4_2) when _T_165 : connect _WIRE_2.prs1_busy, UInt<1>(0h0) node _T_166 = mux(prs1_wakeups_0_2, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) node _T_167 = mux(prs1_wakeups_1_2, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) node _T_168 = mux(prs1_wakeups_2_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0)) node _T_169 = mux(prs1_wakeups_3_2, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0)) node _T_170 = mux(prs1_wakeups_4_2, io.wakeup_ports[4].bits.speculative_mask, UInt<1>(0h0)) node _T_171 = or(_T_166, _T_167) node _T_172 = or(_T_171, _T_168) node _T_173 = or(_T_172, _T_169) node _T_174 = or(_T_173, _T_170) wire _WIRE_13 : UInt<3> connect _WIRE_13, _T_174 connect _WIRE_2.iw_p1_speculative_child, _WIRE_13 node _T_175 = mux(prs1_wakeups_0_2, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _T_176 = mux(prs1_wakeups_1_2, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _T_177 = mux(prs1_wakeups_2_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) node _T_178 = mux(prs1_wakeups_3_2, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) node _T_179 = mux(prs1_wakeups_4_2, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0)) node _T_180 = or(_T_175, _T_176) node _T_181 = or(_T_180, _T_177) node _T_182 = or(_T_181, _T_178) node _T_183 = or(_T_182, _T_179) wire _WIRE_14 : UInt<1> connect _WIRE_14, _T_183 connect _WIRE_2.iw_p1_bypass_hint, _WIRE_14 node _T_184 = or(prs1_rebusys_0_2, prs1_rebusys_1_2) node _T_185 = or(_T_184, prs1_rebusys_2_2) node _T_186 = or(_T_185, prs1_rebusys_3_2) node _T_187 = or(_T_186, prs1_rebusys_4_2) node _T_188 = and(io.child_rebusys, io.dis_uops[2].bits.iw_p1_speculative_child) node _T_189 = neq(_T_188, UInt<1>(0h0)) node _T_190 = or(_T_187, _T_189) when _T_190 : node _T_191 = eq(io.dis_uops[2].bits.lrs1_rtype, UInt<2>(0h0)) connect _WIRE_2.prs1_busy, _T_191 node _T_192 = or(prs2_wakeups_0_2, prs2_wakeups_1_2) node _T_193 = or(_T_192, prs2_wakeups_2_2) node _T_194 = or(_T_193, prs2_wakeups_3_2) node _T_195 = or(_T_194, prs2_wakeups_4_2) when _T_195 : connect _WIRE_2.prs2_busy, UInt<1>(0h0) node _T_196 = mux(prs2_wakeups_0_2, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) node _T_197 = mux(prs2_wakeups_1_2, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) node _T_198 = mux(prs2_wakeups_2_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0)) node _T_199 = mux(prs2_wakeups_3_2, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0)) node _T_200 = mux(prs2_wakeups_4_2, io.wakeup_ports[4].bits.speculative_mask, UInt<1>(0h0)) node _T_201 = or(_T_196, _T_197) node _T_202 = or(_T_201, _T_198) node _T_203 = or(_T_202, _T_199) node _T_204 = or(_T_203, _T_200) wire _WIRE_15 : UInt<3> connect _WIRE_15, _T_204 connect _WIRE_2.iw_p2_speculative_child, _WIRE_15 node _T_205 = mux(prs2_wakeups_0_2, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _T_206 = mux(prs2_wakeups_1_2, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _T_207 = mux(prs2_wakeups_2_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) node _T_208 = mux(prs2_wakeups_3_2, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) node _T_209 = mux(prs2_wakeups_4_2, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0)) node _T_210 = or(_T_205, _T_206) node _T_211 = or(_T_210, _T_207) node _T_212 = or(_T_211, _T_208) node _T_213 = or(_T_212, _T_209) wire _WIRE_16 : UInt<1> connect _WIRE_16, _T_213 connect _WIRE_2.iw_p2_bypass_hint, _WIRE_16 node _T_214 = or(prs2_rebusys_0_2, prs2_rebusys_1_2) node _T_215 = or(_T_214, prs2_rebusys_2_2) node _T_216 = or(_T_215, prs2_rebusys_3_2) node _T_217 = or(_T_216, prs2_rebusys_4_2) node _T_218 = and(io.child_rebusys, io.dis_uops[2].bits.iw_p2_speculative_child) node _T_219 = neq(_T_218, UInt<1>(0h0)) node _T_220 = or(_T_217, _T_219) when _T_220 : node _T_221 = eq(io.dis_uops[2].bits.lrs2_rtype, UInt<2>(0h0)) connect _WIRE_2.prs2_busy, _T_221 node _T_222 = or(prs3_wakeups_0_2, prs3_wakeups_1_2) node _T_223 = or(_T_222, prs3_wakeups_2_2) node _T_224 = or(_T_223, prs3_wakeups_3_2) node _T_225 = or(_T_224, prs3_wakeups_4_2) when _T_225 : connect _WIRE_2.prs3_busy, UInt<1>(0h0) node _T_226 = mux(prs3_wakeups_0_2, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _T_227 = mux(prs3_wakeups_1_2, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _T_228 = mux(prs3_wakeups_2_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) node _T_229 = mux(prs3_wakeups_3_2, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) node _T_230 = mux(prs3_wakeups_4_2, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0)) node _T_231 = or(_T_226, _T_227) node _T_232 = or(_T_231, _T_228) node _T_233 = or(_T_232, _T_229) node _T_234 = or(_T_233, _T_230) wire _WIRE_17 : UInt<1> connect _WIRE_17, _T_234 connect _WIRE_2.iw_p3_bypass_hint, _WIRE_17 node _T_235 = eq(io.pred_wakeup_port.bits, io.dis_uops[2].bits.ppred) node _T_236 = and(io.pred_wakeup_port.valid, _T_235) when _T_236 : connect _WIRE_2.ppred_busy, UInt<1>(0h0) when io.dis_uops[2].bits.fu_code[8] : node _T_237 = cat(io.dis_uops[2].bits.fp_rm, io.dis_uops[2].bits.fp_typ) connect _WIRE_2.prs2, _T_237 when io.dis_uops[2].bits.is_sfence : connect _WIRE_2.pimm, io.dis_uops[2].bits.mem_size node _T_238 = and(io.dis_uops[2].bits.ppred_busy, io.dis_uops[2].valid) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-unit-age-ordered.scala:110 assert(!(io.dis_uops(w).bits.ppred_busy && io.dis_uops(w).valid))\n") : printf_2 assert(clock, _T_239, UInt<1>(0h1), "") : assert_2 connect _WIRE_2.ppred_busy, UInt<1>(0h0) inst slots_0 of IssueSlot_40 connect slots_0.clock, clock connect slots_0.reset, reset inst slots_1 of IssueSlot_41 connect slots_1.clock, clock connect slots_1.reset, reset inst slots_2 of IssueSlot_42 connect slots_2.clock, clock connect slots_2.reset, reset inst slots_3 of IssueSlot_43 connect slots_3.clock, clock connect slots_3.reset, reset inst slots_4 of IssueSlot_44 connect slots_4.clock, clock connect slots_4.reset, reset inst slots_5 of IssueSlot_45 connect slots_5.clock, clock connect slots_5.reset, reset inst slots_6 of IssueSlot_46 connect slots_6.clock, clock connect slots_6.reset, reset inst slots_7 of IssueSlot_47 connect slots_7.clock, clock connect slots_7.reset, reset inst slots_8 of IssueSlot_48 connect slots_8.clock, clock connect slots_8.reset, reset inst slots_9 of IssueSlot_49 connect slots_9.clock, clock connect slots_9.reset, reset inst slots_10 of IssueSlot_50 connect slots_10.clock, clock connect slots_10.reset, reset inst slots_11 of IssueSlot_51 connect slots_11.clock, clock connect slots_11.reset, reset inst slots_12 of IssueSlot_52 connect slots_12.clock, clock connect slots_12.reset, reset inst slots_13 of IssueSlot_53 connect slots_13.clock, clock connect slots_13.reset, reset inst slots_14 of IssueSlot_54 connect slots_14.clock, clock connect slots_14.reset, reset inst slots_15 of IssueSlot_55 connect slots_15.clock, clock connect slots_15.reset, reset wire issue_slots : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, flip grant : UInt<1>, iss_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip in_uop : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}, out_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip kill : UInt<1>, flip clear : UInt<1>, flip squash_grant : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}}[5], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip child_rebusys : UInt<3>}[16] connect slots_0.io.child_rebusys, issue_slots[0].child_rebusys connect slots_0.io.pred_wakeup_port.bits, issue_slots[0].pred_wakeup_port.bits connect slots_0.io.pred_wakeup_port.valid, issue_slots[0].pred_wakeup_port.valid connect slots_0.io.wakeup_ports[0].bits.rebusy, issue_slots[0].wakeup_ports[0].bits.rebusy connect slots_0.io.wakeup_ports[0].bits.speculative_mask, issue_slots[0].wakeup_ports[0].bits.speculative_mask connect slots_0.io.wakeup_ports[0].bits.bypassable, issue_slots[0].wakeup_ports[0].bits.bypassable connect slots_0.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[0].wakeup_ports[0].bits.uop.debug_tsrc connect slots_0.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[0].wakeup_ports[0].bits.uop.debug_fsrc connect slots_0.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[0].wakeup_ports[0].bits.uop.bp_xcpt_if connect slots_0.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[0].wakeup_ports[0].bits.uop.bp_debug_if connect slots_0.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[0].wakeup_ports[0].bits.uop.xcpt_ma_if connect slots_0.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[0].wakeup_ports[0].bits.uop.xcpt_ae_if connect slots_0.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[0].wakeup_ports[0].bits.uop.xcpt_pf_if connect slots_0.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[0].wakeup_ports[0].bits.uop.fp_typ connect slots_0.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[0].wakeup_ports[0].bits.uop.fp_rm connect slots_0.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[0].wakeup_ports[0].bits.uop.fp_val connect slots_0.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[0].wakeup_ports[0].bits.uop.fcn_op connect slots_0.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[0].wakeup_ports[0].bits.uop.fcn_dw connect slots_0.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[0].wakeup_ports[0].bits.uop.frs3_en connect slots_0.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[0].wakeup_ports[0].bits.uop.lrs2_rtype connect slots_0.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[0].wakeup_ports[0].bits.uop.lrs1_rtype connect slots_0.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[0].wakeup_ports[0].bits.uop.dst_rtype connect slots_0.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[0].wakeup_ports[0].bits.uop.lrs3 connect slots_0.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[0].wakeup_ports[0].bits.uop.lrs2 connect slots_0.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[0].wakeup_ports[0].bits.uop.lrs1 connect slots_0.io.wakeup_ports[0].bits.uop.ldst, issue_slots[0].wakeup_ports[0].bits.uop.ldst connect slots_0.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[0].wakeup_ports[0].bits.uop.ldst_is_rs1 connect slots_0.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[0].wakeup_ports[0].bits.uop.csr_cmd connect slots_0.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[0].wakeup_ports[0].bits.uop.flush_on_commit connect slots_0.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[0].wakeup_ports[0].bits.uop.is_unique connect slots_0.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[0].wakeup_ports[0].bits.uop.uses_stq connect slots_0.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[0].wakeup_ports[0].bits.uop.uses_ldq connect slots_0.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[0].wakeup_ports[0].bits.uop.mem_signed connect slots_0.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[0].wakeup_ports[0].bits.uop.mem_size connect slots_0.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[0].wakeup_ports[0].bits.uop.mem_cmd connect slots_0.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[0].wakeup_ports[0].bits.uop.exc_cause connect slots_0.io.wakeup_ports[0].bits.uop.exception, issue_slots[0].wakeup_ports[0].bits.uop.exception connect slots_0.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[0].wakeup_ports[0].bits.uop.stale_pdst connect slots_0.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[0].wakeup_ports[0].bits.uop.ppred_busy connect slots_0.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[0].wakeup_ports[0].bits.uop.prs3_busy connect slots_0.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[0].wakeup_ports[0].bits.uop.prs2_busy connect slots_0.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[0].wakeup_ports[0].bits.uop.prs1_busy connect slots_0.io.wakeup_ports[0].bits.uop.ppred, issue_slots[0].wakeup_ports[0].bits.uop.ppred connect slots_0.io.wakeup_ports[0].bits.uop.prs3, issue_slots[0].wakeup_ports[0].bits.uop.prs3 connect slots_0.io.wakeup_ports[0].bits.uop.prs2, issue_slots[0].wakeup_ports[0].bits.uop.prs2 connect slots_0.io.wakeup_ports[0].bits.uop.prs1, issue_slots[0].wakeup_ports[0].bits.uop.prs1 connect slots_0.io.wakeup_ports[0].bits.uop.pdst, issue_slots[0].wakeup_ports[0].bits.uop.pdst connect slots_0.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[0].wakeup_ports[0].bits.uop.rxq_idx connect slots_0.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[0].wakeup_ports[0].bits.uop.stq_idx connect slots_0.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[0].wakeup_ports[0].bits.uop.ldq_idx connect slots_0.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[0].wakeup_ports[0].bits.uop.rob_idx connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.vec connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.wflags connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.div connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.fma connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.toint connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.fromint connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.wen connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.ldst connect slots_0.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[0].wakeup_ports[0].bits.uop.op2_sel connect slots_0.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[0].wakeup_ports[0].bits.uop.op1_sel connect slots_0.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[0].wakeup_ports[0].bits.uop.imm_packed connect slots_0.io.wakeup_ports[0].bits.uop.pimm, issue_slots[0].wakeup_ports[0].bits.uop.pimm connect slots_0.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[0].wakeup_ports[0].bits.uop.imm_sel connect slots_0.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[0].wakeup_ports[0].bits.uop.imm_rename connect slots_0.io.wakeup_ports[0].bits.uop.taken, issue_slots[0].wakeup_ports[0].bits.uop.taken connect slots_0.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[0].wakeup_ports[0].bits.uop.pc_lob connect slots_0.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[0].wakeup_ports[0].bits.uop.edge_inst connect slots_0.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[0].wakeup_ports[0].bits.uop.ftq_idx connect slots_0.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[0].wakeup_ports[0].bits.uop.is_mov connect slots_0.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[0].wakeup_ports[0].bits.uop.is_rocc connect slots_0.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[0].wakeup_ports[0].bits.uop.is_sys_pc2epc connect slots_0.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[0].wakeup_ports[0].bits.uop.is_eret connect slots_0.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[0].wakeup_ports[0].bits.uop.is_amo connect slots_0.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[0].wakeup_ports[0].bits.uop.is_sfence connect slots_0.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[0].wakeup_ports[0].bits.uop.is_fencei connect slots_0.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[0].wakeup_ports[0].bits.uop.is_fence connect slots_0.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[0].wakeup_ports[0].bits.uop.is_sfb connect slots_0.io.wakeup_ports[0].bits.uop.br_type, issue_slots[0].wakeup_ports[0].bits.uop.br_type connect slots_0.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[0].wakeup_ports[0].bits.uop.br_tag connect slots_0.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[0].wakeup_ports[0].bits.uop.br_mask connect slots_0.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[0].wakeup_ports[0].bits.uop.dis_col_sel connect slots_0.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[0].wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect slots_0.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[0].wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect slots_0.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[0].wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect slots_0.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[0].wakeup_ports[0].bits.uop.iw_p2_speculative_child connect slots_0.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[0].wakeup_ports[0].bits.uop.iw_p1_speculative_child connect slots_0.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[0].wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect slots_0.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[0].wakeup_ports[0].bits.uop.iw_issued_partial_agen connect slots_0.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[0].wakeup_ports[0].bits.uop.iw_issued connect slots_0.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[0].wakeup_ports[0].bits.uop.fu_code[0] connect slots_0.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[0].wakeup_ports[0].bits.uop.fu_code[1] connect slots_0.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[0].wakeup_ports[0].bits.uop.fu_code[2] connect slots_0.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[0].wakeup_ports[0].bits.uop.fu_code[3] connect slots_0.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[0].wakeup_ports[0].bits.uop.fu_code[4] connect slots_0.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[0].wakeup_ports[0].bits.uop.fu_code[5] connect slots_0.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[0].wakeup_ports[0].bits.uop.fu_code[6] connect slots_0.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[0].wakeup_ports[0].bits.uop.fu_code[7] connect slots_0.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[0].wakeup_ports[0].bits.uop.fu_code[8] connect slots_0.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[0].wakeup_ports[0].bits.uop.fu_code[9] connect slots_0.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[0].wakeup_ports[0].bits.uop.iq_type[0] connect slots_0.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[0].wakeup_ports[0].bits.uop.iq_type[1] connect slots_0.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[0].wakeup_ports[0].bits.uop.iq_type[2] connect slots_0.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[0].wakeup_ports[0].bits.uop.iq_type[3] connect slots_0.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[0].wakeup_ports[0].bits.uop.debug_pc connect slots_0.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[0].wakeup_ports[0].bits.uop.is_rvc connect slots_0.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[0].wakeup_ports[0].bits.uop.debug_inst connect slots_0.io.wakeup_ports[0].bits.uop.inst, issue_slots[0].wakeup_ports[0].bits.uop.inst connect slots_0.io.wakeup_ports[0].valid, issue_slots[0].wakeup_ports[0].valid connect slots_0.io.wakeup_ports[1].bits.rebusy, issue_slots[0].wakeup_ports[1].bits.rebusy connect slots_0.io.wakeup_ports[1].bits.speculative_mask, issue_slots[0].wakeup_ports[1].bits.speculative_mask connect slots_0.io.wakeup_ports[1].bits.bypassable, issue_slots[0].wakeup_ports[1].bits.bypassable connect slots_0.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[0].wakeup_ports[1].bits.uop.debug_tsrc connect slots_0.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[0].wakeup_ports[1].bits.uop.debug_fsrc connect slots_0.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[0].wakeup_ports[1].bits.uop.bp_xcpt_if connect slots_0.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[0].wakeup_ports[1].bits.uop.bp_debug_if connect slots_0.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[0].wakeup_ports[1].bits.uop.xcpt_ma_if connect slots_0.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[0].wakeup_ports[1].bits.uop.xcpt_ae_if connect slots_0.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[0].wakeup_ports[1].bits.uop.xcpt_pf_if connect slots_0.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[0].wakeup_ports[1].bits.uop.fp_typ connect slots_0.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[0].wakeup_ports[1].bits.uop.fp_rm connect slots_0.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[0].wakeup_ports[1].bits.uop.fp_val connect slots_0.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[0].wakeup_ports[1].bits.uop.fcn_op connect slots_0.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[0].wakeup_ports[1].bits.uop.fcn_dw connect slots_0.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[0].wakeup_ports[1].bits.uop.frs3_en connect slots_0.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[0].wakeup_ports[1].bits.uop.lrs2_rtype connect slots_0.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[0].wakeup_ports[1].bits.uop.lrs1_rtype connect slots_0.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[0].wakeup_ports[1].bits.uop.dst_rtype connect slots_0.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[0].wakeup_ports[1].bits.uop.lrs3 connect slots_0.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[0].wakeup_ports[1].bits.uop.lrs2 connect slots_0.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[0].wakeup_ports[1].bits.uop.lrs1 connect slots_0.io.wakeup_ports[1].bits.uop.ldst, issue_slots[0].wakeup_ports[1].bits.uop.ldst connect slots_0.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[0].wakeup_ports[1].bits.uop.ldst_is_rs1 connect slots_0.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[0].wakeup_ports[1].bits.uop.csr_cmd connect slots_0.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[0].wakeup_ports[1].bits.uop.flush_on_commit connect slots_0.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[0].wakeup_ports[1].bits.uop.is_unique connect slots_0.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[0].wakeup_ports[1].bits.uop.uses_stq connect slots_0.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[0].wakeup_ports[1].bits.uop.uses_ldq connect slots_0.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[0].wakeup_ports[1].bits.uop.mem_signed connect slots_0.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[0].wakeup_ports[1].bits.uop.mem_size connect slots_0.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[0].wakeup_ports[1].bits.uop.mem_cmd connect slots_0.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[0].wakeup_ports[1].bits.uop.exc_cause connect slots_0.io.wakeup_ports[1].bits.uop.exception, issue_slots[0].wakeup_ports[1].bits.uop.exception connect slots_0.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[0].wakeup_ports[1].bits.uop.stale_pdst connect slots_0.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[0].wakeup_ports[1].bits.uop.ppred_busy connect slots_0.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[0].wakeup_ports[1].bits.uop.prs3_busy connect slots_0.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[0].wakeup_ports[1].bits.uop.prs2_busy connect slots_0.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[0].wakeup_ports[1].bits.uop.prs1_busy connect slots_0.io.wakeup_ports[1].bits.uop.ppred, issue_slots[0].wakeup_ports[1].bits.uop.ppred connect slots_0.io.wakeup_ports[1].bits.uop.prs3, issue_slots[0].wakeup_ports[1].bits.uop.prs3 connect slots_0.io.wakeup_ports[1].bits.uop.prs2, issue_slots[0].wakeup_ports[1].bits.uop.prs2 connect slots_0.io.wakeup_ports[1].bits.uop.prs1, issue_slots[0].wakeup_ports[1].bits.uop.prs1 connect slots_0.io.wakeup_ports[1].bits.uop.pdst, issue_slots[0].wakeup_ports[1].bits.uop.pdst connect slots_0.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[0].wakeup_ports[1].bits.uop.rxq_idx connect slots_0.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[0].wakeup_ports[1].bits.uop.stq_idx connect slots_0.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[0].wakeup_ports[1].bits.uop.ldq_idx connect slots_0.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[0].wakeup_ports[1].bits.uop.rob_idx connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.vec connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.wflags connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.div connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.fma connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.toint connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.fromint connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.wen connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.ldst connect slots_0.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[0].wakeup_ports[1].bits.uop.op2_sel connect slots_0.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[0].wakeup_ports[1].bits.uop.op1_sel connect slots_0.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[0].wakeup_ports[1].bits.uop.imm_packed connect slots_0.io.wakeup_ports[1].bits.uop.pimm, issue_slots[0].wakeup_ports[1].bits.uop.pimm connect slots_0.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[0].wakeup_ports[1].bits.uop.imm_sel connect slots_0.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[0].wakeup_ports[1].bits.uop.imm_rename connect slots_0.io.wakeup_ports[1].bits.uop.taken, issue_slots[0].wakeup_ports[1].bits.uop.taken connect slots_0.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[0].wakeup_ports[1].bits.uop.pc_lob connect slots_0.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[0].wakeup_ports[1].bits.uop.edge_inst connect slots_0.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[0].wakeup_ports[1].bits.uop.ftq_idx connect slots_0.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[0].wakeup_ports[1].bits.uop.is_mov connect slots_0.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[0].wakeup_ports[1].bits.uop.is_rocc connect slots_0.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[0].wakeup_ports[1].bits.uop.is_sys_pc2epc connect slots_0.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[0].wakeup_ports[1].bits.uop.is_eret connect slots_0.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[0].wakeup_ports[1].bits.uop.is_amo connect slots_0.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[0].wakeup_ports[1].bits.uop.is_sfence connect slots_0.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[0].wakeup_ports[1].bits.uop.is_fencei connect slots_0.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[0].wakeup_ports[1].bits.uop.is_fence connect slots_0.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[0].wakeup_ports[1].bits.uop.is_sfb connect slots_0.io.wakeup_ports[1].bits.uop.br_type, issue_slots[0].wakeup_ports[1].bits.uop.br_type connect slots_0.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[0].wakeup_ports[1].bits.uop.br_tag connect slots_0.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[0].wakeup_ports[1].bits.uop.br_mask connect slots_0.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[0].wakeup_ports[1].bits.uop.dis_col_sel connect slots_0.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[0].wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect slots_0.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[0].wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect slots_0.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[0].wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect slots_0.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[0].wakeup_ports[1].bits.uop.iw_p2_speculative_child connect slots_0.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[0].wakeup_ports[1].bits.uop.iw_p1_speculative_child connect slots_0.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[0].wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect slots_0.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[0].wakeup_ports[1].bits.uop.iw_issued_partial_agen connect slots_0.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[0].wakeup_ports[1].bits.uop.iw_issued connect slots_0.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[0].wakeup_ports[1].bits.uop.fu_code[0] connect slots_0.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[0].wakeup_ports[1].bits.uop.fu_code[1] connect slots_0.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[0].wakeup_ports[1].bits.uop.fu_code[2] connect slots_0.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[0].wakeup_ports[1].bits.uop.fu_code[3] connect slots_0.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[0].wakeup_ports[1].bits.uop.fu_code[4] connect slots_0.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[0].wakeup_ports[1].bits.uop.fu_code[5] connect slots_0.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[0].wakeup_ports[1].bits.uop.fu_code[6] connect slots_0.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[0].wakeup_ports[1].bits.uop.fu_code[7] connect slots_0.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[0].wakeup_ports[1].bits.uop.fu_code[8] connect slots_0.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[0].wakeup_ports[1].bits.uop.fu_code[9] connect slots_0.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[0].wakeup_ports[1].bits.uop.iq_type[0] connect slots_0.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[0].wakeup_ports[1].bits.uop.iq_type[1] connect slots_0.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[0].wakeup_ports[1].bits.uop.iq_type[2] connect slots_0.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[0].wakeup_ports[1].bits.uop.iq_type[3] connect slots_0.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[0].wakeup_ports[1].bits.uop.debug_pc connect slots_0.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[0].wakeup_ports[1].bits.uop.is_rvc connect slots_0.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[0].wakeup_ports[1].bits.uop.debug_inst connect slots_0.io.wakeup_ports[1].bits.uop.inst, issue_slots[0].wakeup_ports[1].bits.uop.inst connect slots_0.io.wakeup_ports[1].valid, issue_slots[0].wakeup_ports[1].valid connect slots_0.io.wakeup_ports[2].bits.rebusy, issue_slots[0].wakeup_ports[2].bits.rebusy connect slots_0.io.wakeup_ports[2].bits.speculative_mask, issue_slots[0].wakeup_ports[2].bits.speculative_mask connect slots_0.io.wakeup_ports[2].bits.bypassable, issue_slots[0].wakeup_ports[2].bits.bypassable connect slots_0.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[0].wakeup_ports[2].bits.uop.debug_tsrc connect slots_0.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[0].wakeup_ports[2].bits.uop.debug_fsrc connect slots_0.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[0].wakeup_ports[2].bits.uop.bp_xcpt_if connect slots_0.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[0].wakeup_ports[2].bits.uop.bp_debug_if connect slots_0.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[0].wakeup_ports[2].bits.uop.xcpt_ma_if connect slots_0.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[0].wakeup_ports[2].bits.uop.xcpt_ae_if connect slots_0.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[0].wakeup_ports[2].bits.uop.xcpt_pf_if connect slots_0.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[0].wakeup_ports[2].bits.uop.fp_typ connect slots_0.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[0].wakeup_ports[2].bits.uop.fp_rm connect slots_0.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[0].wakeup_ports[2].bits.uop.fp_val connect slots_0.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[0].wakeup_ports[2].bits.uop.fcn_op connect slots_0.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[0].wakeup_ports[2].bits.uop.fcn_dw connect slots_0.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[0].wakeup_ports[2].bits.uop.frs3_en connect slots_0.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[0].wakeup_ports[2].bits.uop.lrs2_rtype connect slots_0.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[0].wakeup_ports[2].bits.uop.lrs1_rtype connect slots_0.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[0].wakeup_ports[2].bits.uop.dst_rtype connect slots_0.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[0].wakeup_ports[2].bits.uop.lrs3 connect slots_0.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[0].wakeup_ports[2].bits.uop.lrs2 connect slots_0.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[0].wakeup_ports[2].bits.uop.lrs1 connect slots_0.io.wakeup_ports[2].bits.uop.ldst, issue_slots[0].wakeup_ports[2].bits.uop.ldst connect slots_0.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[0].wakeup_ports[2].bits.uop.ldst_is_rs1 connect slots_0.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[0].wakeup_ports[2].bits.uop.csr_cmd connect slots_0.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[0].wakeup_ports[2].bits.uop.flush_on_commit connect slots_0.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[0].wakeup_ports[2].bits.uop.is_unique connect slots_0.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[0].wakeup_ports[2].bits.uop.uses_stq connect slots_0.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[0].wakeup_ports[2].bits.uop.uses_ldq connect slots_0.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[0].wakeup_ports[2].bits.uop.mem_signed connect slots_0.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[0].wakeup_ports[2].bits.uop.mem_size connect slots_0.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[0].wakeup_ports[2].bits.uop.mem_cmd connect slots_0.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[0].wakeup_ports[2].bits.uop.exc_cause connect slots_0.io.wakeup_ports[2].bits.uop.exception, issue_slots[0].wakeup_ports[2].bits.uop.exception connect slots_0.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[0].wakeup_ports[2].bits.uop.stale_pdst connect slots_0.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[0].wakeup_ports[2].bits.uop.ppred_busy connect slots_0.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[0].wakeup_ports[2].bits.uop.prs3_busy connect slots_0.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[0].wakeup_ports[2].bits.uop.prs2_busy connect slots_0.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[0].wakeup_ports[2].bits.uop.prs1_busy connect slots_0.io.wakeup_ports[2].bits.uop.ppred, issue_slots[0].wakeup_ports[2].bits.uop.ppred connect slots_0.io.wakeup_ports[2].bits.uop.prs3, issue_slots[0].wakeup_ports[2].bits.uop.prs3 connect slots_0.io.wakeup_ports[2].bits.uop.prs2, issue_slots[0].wakeup_ports[2].bits.uop.prs2 connect slots_0.io.wakeup_ports[2].bits.uop.prs1, issue_slots[0].wakeup_ports[2].bits.uop.prs1 connect slots_0.io.wakeup_ports[2].bits.uop.pdst, issue_slots[0].wakeup_ports[2].bits.uop.pdst connect slots_0.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[0].wakeup_ports[2].bits.uop.rxq_idx connect slots_0.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[0].wakeup_ports[2].bits.uop.stq_idx connect slots_0.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[0].wakeup_ports[2].bits.uop.ldq_idx connect slots_0.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[0].wakeup_ports[2].bits.uop.rob_idx connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.vec connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.wflags connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.div connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.fma connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.toint connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.fromint connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.wen connect slots_0.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.ldst connect slots_0.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[0].wakeup_ports[2].bits.uop.op2_sel connect slots_0.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[0].wakeup_ports[2].bits.uop.op1_sel connect slots_0.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[0].wakeup_ports[2].bits.uop.imm_packed connect slots_0.io.wakeup_ports[2].bits.uop.pimm, issue_slots[0].wakeup_ports[2].bits.uop.pimm connect slots_0.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[0].wakeup_ports[2].bits.uop.imm_sel connect slots_0.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[0].wakeup_ports[2].bits.uop.imm_rename connect slots_0.io.wakeup_ports[2].bits.uop.taken, issue_slots[0].wakeup_ports[2].bits.uop.taken connect slots_0.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[0].wakeup_ports[2].bits.uop.pc_lob connect slots_0.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[0].wakeup_ports[2].bits.uop.edge_inst connect slots_0.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[0].wakeup_ports[2].bits.uop.ftq_idx connect slots_0.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[0].wakeup_ports[2].bits.uop.is_mov connect slots_0.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[0].wakeup_ports[2].bits.uop.is_rocc connect slots_0.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[0].wakeup_ports[2].bits.uop.is_sys_pc2epc connect slots_0.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[0].wakeup_ports[2].bits.uop.is_eret connect slots_0.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[0].wakeup_ports[2].bits.uop.is_amo connect slots_0.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[0].wakeup_ports[2].bits.uop.is_sfence connect slots_0.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[0].wakeup_ports[2].bits.uop.is_fencei connect slots_0.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[0].wakeup_ports[2].bits.uop.is_fence connect slots_0.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[0].wakeup_ports[2].bits.uop.is_sfb connect slots_0.io.wakeup_ports[2].bits.uop.br_type, issue_slots[0].wakeup_ports[2].bits.uop.br_type connect slots_0.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[0].wakeup_ports[2].bits.uop.br_tag connect slots_0.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[0].wakeup_ports[2].bits.uop.br_mask connect slots_0.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[0].wakeup_ports[2].bits.uop.dis_col_sel connect slots_0.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[0].wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect slots_0.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[0].wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect slots_0.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[0].wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect slots_0.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[0].wakeup_ports[2].bits.uop.iw_p2_speculative_child connect slots_0.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[0].wakeup_ports[2].bits.uop.iw_p1_speculative_child connect slots_0.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[0].wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect slots_0.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[0].wakeup_ports[2].bits.uop.iw_issued_partial_agen connect slots_0.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[0].wakeup_ports[2].bits.uop.iw_issued connect slots_0.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[0].wakeup_ports[2].bits.uop.fu_code[0] connect slots_0.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[0].wakeup_ports[2].bits.uop.fu_code[1] connect slots_0.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[0].wakeup_ports[2].bits.uop.fu_code[2] connect slots_0.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[0].wakeup_ports[2].bits.uop.fu_code[3] connect slots_0.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[0].wakeup_ports[2].bits.uop.fu_code[4] connect slots_0.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[0].wakeup_ports[2].bits.uop.fu_code[5] connect slots_0.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[0].wakeup_ports[2].bits.uop.fu_code[6] connect slots_0.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[0].wakeup_ports[2].bits.uop.fu_code[7] connect slots_0.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[0].wakeup_ports[2].bits.uop.fu_code[8] connect slots_0.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[0].wakeup_ports[2].bits.uop.fu_code[9] connect slots_0.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[0].wakeup_ports[2].bits.uop.iq_type[0] connect slots_0.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[0].wakeup_ports[2].bits.uop.iq_type[1] connect slots_0.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[0].wakeup_ports[2].bits.uop.iq_type[2] connect slots_0.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[0].wakeup_ports[2].bits.uop.iq_type[3] connect slots_0.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[0].wakeup_ports[2].bits.uop.debug_pc connect slots_0.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[0].wakeup_ports[2].bits.uop.is_rvc connect slots_0.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[0].wakeup_ports[2].bits.uop.debug_inst connect slots_0.io.wakeup_ports[2].bits.uop.inst, issue_slots[0].wakeup_ports[2].bits.uop.inst connect slots_0.io.wakeup_ports[2].valid, issue_slots[0].wakeup_ports[2].valid connect slots_0.io.wakeup_ports[3].bits.rebusy, issue_slots[0].wakeup_ports[3].bits.rebusy connect slots_0.io.wakeup_ports[3].bits.speculative_mask, issue_slots[0].wakeup_ports[3].bits.speculative_mask connect slots_0.io.wakeup_ports[3].bits.bypassable, issue_slots[0].wakeup_ports[3].bits.bypassable connect slots_0.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[0].wakeup_ports[3].bits.uop.debug_tsrc connect slots_0.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[0].wakeup_ports[3].bits.uop.debug_fsrc connect slots_0.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[0].wakeup_ports[3].bits.uop.bp_xcpt_if connect slots_0.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[0].wakeup_ports[3].bits.uop.bp_debug_if connect slots_0.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[0].wakeup_ports[3].bits.uop.xcpt_ma_if connect slots_0.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[0].wakeup_ports[3].bits.uop.xcpt_ae_if connect slots_0.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[0].wakeup_ports[3].bits.uop.xcpt_pf_if connect slots_0.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[0].wakeup_ports[3].bits.uop.fp_typ connect slots_0.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[0].wakeup_ports[3].bits.uop.fp_rm connect slots_0.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[0].wakeup_ports[3].bits.uop.fp_val connect slots_0.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[0].wakeup_ports[3].bits.uop.fcn_op connect slots_0.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[0].wakeup_ports[3].bits.uop.fcn_dw connect slots_0.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[0].wakeup_ports[3].bits.uop.frs3_en connect slots_0.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[0].wakeup_ports[3].bits.uop.lrs2_rtype connect slots_0.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[0].wakeup_ports[3].bits.uop.lrs1_rtype connect slots_0.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[0].wakeup_ports[3].bits.uop.dst_rtype connect slots_0.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[0].wakeup_ports[3].bits.uop.lrs3 connect slots_0.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[0].wakeup_ports[3].bits.uop.lrs2 connect slots_0.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[0].wakeup_ports[3].bits.uop.lrs1 connect slots_0.io.wakeup_ports[3].bits.uop.ldst, issue_slots[0].wakeup_ports[3].bits.uop.ldst connect slots_0.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[0].wakeup_ports[3].bits.uop.ldst_is_rs1 connect slots_0.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[0].wakeup_ports[3].bits.uop.csr_cmd connect slots_0.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[0].wakeup_ports[3].bits.uop.flush_on_commit connect slots_0.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[0].wakeup_ports[3].bits.uop.is_unique connect slots_0.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[0].wakeup_ports[3].bits.uop.uses_stq connect slots_0.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[0].wakeup_ports[3].bits.uop.uses_ldq connect slots_0.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[0].wakeup_ports[3].bits.uop.mem_signed connect slots_0.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[0].wakeup_ports[3].bits.uop.mem_size connect slots_0.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[0].wakeup_ports[3].bits.uop.mem_cmd connect slots_0.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[0].wakeup_ports[3].bits.uop.exc_cause connect slots_0.io.wakeup_ports[3].bits.uop.exception, issue_slots[0].wakeup_ports[3].bits.uop.exception connect slots_0.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[0].wakeup_ports[3].bits.uop.stale_pdst connect slots_0.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[0].wakeup_ports[3].bits.uop.ppred_busy connect slots_0.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[0].wakeup_ports[3].bits.uop.prs3_busy connect slots_0.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[0].wakeup_ports[3].bits.uop.prs2_busy connect slots_0.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[0].wakeup_ports[3].bits.uop.prs1_busy connect slots_0.io.wakeup_ports[3].bits.uop.ppred, issue_slots[0].wakeup_ports[3].bits.uop.ppred connect slots_0.io.wakeup_ports[3].bits.uop.prs3, issue_slots[0].wakeup_ports[3].bits.uop.prs3 connect slots_0.io.wakeup_ports[3].bits.uop.prs2, issue_slots[0].wakeup_ports[3].bits.uop.prs2 connect slots_0.io.wakeup_ports[3].bits.uop.prs1, issue_slots[0].wakeup_ports[3].bits.uop.prs1 connect slots_0.io.wakeup_ports[3].bits.uop.pdst, issue_slots[0].wakeup_ports[3].bits.uop.pdst connect slots_0.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[0].wakeup_ports[3].bits.uop.rxq_idx connect slots_0.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[0].wakeup_ports[3].bits.uop.stq_idx connect slots_0.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[0].wakeup_ports[3].bits.uop.ldq_idx connect slots_0.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[0].wakeup_ports[3].bits.uop.rob_idx connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.vec connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.wflags connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.div connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.fma connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.toint connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.fromint connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.wen connect slots_0.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.ldst connect slots_0.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[0].wakeup_ports[3].bits.uop.op2_sel connect slots_0.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[0].wakeup_ports[3].bits.uop.op1_sel connect slots_0.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[0].wakeup_ports[3].bits.uop.imm_packed connect slots_0.io.wakeup_ports[3].bits.uop.pimm, issue_slots[0].wakeup_ports[3].bits.uop.pimm connect slots_0.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[0].wakeup_ports[3].bits.uop.imm_sel connect slots_0.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[0].wakeup_ports[3].bits.uop.imm_rename connect slots_0.io.wakeup_ports[3].bits.uop.taken, issue_slots[0].wakeup_ports[3].bits.uop.taken connect slots_0.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[0].wakeup_ports[3].bits.uop.pc_lob connect slots_0.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[0].wakeup_ports[3].bits.uop.edge_inst connect slots_0.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[0].wakeup_ports[3].bits.uop.ftq_idx connect slots_0.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[0].wakeup_ports[3].bits.uop.is_mov connect slots_0.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[0].wakeup_ports[3].bits.uop.is_rocc connect slots_0.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[0].wakeup_ports[3].bits.uop.is_sys_pc2epc connect slots_0.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[0].wakeup_ports[3].bits.uop.is_eret connect slots_0.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[0].wakeup_ports[3].bits.uop.is_amo connect slots_0.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[0].wakeup_ports[3].bits.uop.is_sfence connect slots_0.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[0].wakeup_ports[3].bits.uop.is_fencei connect slots_0.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[0].wakeup_ports[3].bits.uop.is_fence connect slots_0.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[0].wakeup_ports[3].bits.uop.is_sfb connect slots_0.io.wakeup_ports[3].bits.uop.br_type, issue_slots[0].wakeup_ports[3].bits.uop.br_type connect slots_0.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[0].wakeup_ports[3].bits.uop.br_tag connect slots_0.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[0].wakeup_ports[3].bits.uop.br_mask connect slots_0.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[0].wakeup_ports[3].bits.uop.dis_col_sel connect slots_0.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[0].wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect slots_0.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[0].wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect slots_0.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[0].wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect slots_0.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[0].wakeup_ports[3].bits.uop.iw_p2_speculative_child connect slots_0.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[0].wakeup_ports[3].bits.uop.iw_p1_speculative_child connect slots_0.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[0].wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect slots_0.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[0].wakeup_ports[3].bits.uop.iw_issued_partial_agen connect slots_0.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[0].wakeup_ports[3].bits.uop.iw_issued connect slots_0.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[0].wakeup_ports[3].bits.uop.fu_code[0] connect slots_0.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[0].wakeup_ports[3].bits.uop.fu_code[1] connect slots_0.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[0].wakeup_ports[3].bits.uop.fu_code[2] connect slots_0.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[0].wakeup_ports[3].bits.uop.fu_code[3] connect slots_0.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[0].wakeup_ports[3].bits.uop.fu_code[4] connect slots_0.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[0].wakeup_ports[3].bits.uop.fu_code[5] connect slots_0.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[0].wakeup_ports[3].bits.uop.fu_code[6] connect slots_0.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[0].wakeup_ports[3].bits.uop.fu_code[7] connect slots_0.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[0].wakeup_ports[3].bits.uop.fu_code[8] connect slots_0.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[0].wakeup_ports[3].bits.uop.fu_code[9] connect slots_0.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[0].wakeup_ports[3].bits.uop.iq_type[0] connect slots_0.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[0].wakeup_ports[3].bits.uop.iq_type[1] connect slots_0.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[0].wakeup_ports[3].bits.uop.iq_type[2] connect slots_0.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[0].wakeup_ports[3].bits.uop.iq_type[3] connect slots_0.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[0].wakeup_ports[3].bits.uop.debug_pc connect slots_0.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[0].wakeup_ports[3].bits.uop.is_rvc connect slots_0.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[0].wakeup_ports[3].bits.uop.debug_inst connect slots_0.io.wakeup_ports[3].bits.uop.inst, issue_slots[0].wakeup_ports[3].bits.uop.inst connect slots_0.io.wakeup_ports[3].valid, issue_slots[0].wakeup_ports[3].valid connect slots_0.io.wakeup_ports[4].bits.rebusy, issue_slots[0].wakeup_ports[4].bits.rebusy connect slots_0.io.wakeup_ports[4].bits.speculative_mask, issue_slots[0].wakeup_ports[4].bits.speculative_mask connect slots_0.io.wakeup_ports[4].bits.bypassable, issue_slots[0].wakeup_ports[4].bits.bypassable connect slots_0.io.wakeup_ports[4].bits.uop.debug_tsrc, issue_slots[0].wakeup_ports[4].bits.uop.debug_tsrc connect slots_0.io.wakeup_ports[4].bits.uop.debug_fsrc, issue_slots[0].wakeup_ports[4].bits.uop.debug_fsrc connect slots_0.io.wakeup_ports[4].bits.uop.bp_xcpt_if, issue_slots[0].wakeup_ports[4].bits.uop.bp_xcpt_if connect slots_0.io.wakeup_ports[4].bits.uop.bp_debug_if, issue_slots[0].wakeup_ports[4].bits.uop.bp_debug_if connect slots_0.io.wakeup_ports[4].bits.uop.xcpt_ma_if, issue_slots[0].wakeup_ports[4].bits.uop.xcpt_ma_if connect slots_0.io.wakeup_ports[4].bits.uop.xcpt_ae_if, issue_slots[0].wakeup_ports[4].bits.uop.xcpt_ae_if connect slots_0.io.wakeup_ports[4].bits.uop.xcpt_pf_if, issue_slots[0].wakeup_ports[4].bits.uop.xcpt_pf_if connect slots_0.io.wakeup_ports[4].bits.uop.fp_typ, issue_slots[0].wakeup_ports[4].bits.uop.fp_typ connect slots_0.io.wakeup_ports[4].bits.uop.fp_rm, issue_slots[0].wakeup_ports[4].bits.uop.fp_rm connect slots_0.io.wakeup_ports[4].bits.uop.fp_val, issue_slots[0].wakeup_ports[4].bits.uop.fp_val connect slots_0.io.wakeup_ports[4].bits.uop.fcn_op, issue_slots[0].wakeup_ports[4].bits.uop.fcn_op connect slots_0.io.wakeup_ports[4].bits.uop.fcn_dw, issue_slots[0].wakeup_ports[4].bits.uop.fcn_dw connect slots_0.io.wakeup_ports[4].bits.uop.frs3_en, issue_slots[0].wakeup_ports[4].bits.uop.frs3_en connect slots_0.io.wakeup_ports[4].bits.uop.lrs2_rtype, issue_slots[0].wakeup_ports[4].bits.uop.lrs2_rtype connect slots_0.io.wakeup_ports[4].bits.uop.lrs1_rtype, issue_slots[0].wakeup_ports[4].bits.uop.lrs1_rtype connect slots_0.io.wakeup_ports[4].bits.uop.dst_rtype, issue_slots[0].wakeup_ports[4].bits.uop.dst_rtype connect slots_0.io.wakeup_ports[4].bits.uop.lrs3, issue_slots[0].wakeup_ports[4].bits.uop.lrs3 connect slots_0.io.wakeup_ports[4].bits.uop.lrs2, issue_slots[0].wakeup_ports[4].bits.uop.lrs2 connect slots_0.io.wakeup_ports[4].bits.uop.lrs1, issue_slots[0].wakeup_ports[4].bits.uop.lrs1 connect slots_0.io.wakeup_ports[4].bits.uop.ldst, issue_slots[0].wakeup_ports[4].bits.uop.ldst connect slots_0.io.wakeup_ports[4].bits.uop.ldst_is_rs1, issue_slots[0].wakeup_ports[4].bits.uop.ldst_is_rs1 connect slots_0.io.wakeup_ports[4].bits.uop.csr_cmd, issue_slots[0].wakeup_ports[4].bits.uop.csr_cmd connect slots_0.io.wakeup_ports[4].bits.uop.flush_on_commit, issue_slots[0].wakeup_ports[4].bits.uop.flush_on_commit connect slots_0.io.wakeup_ports[4].bits.uop.is_unique, issue_slots[0].wakeup_ports[4].bits.uop.is_unique connect slots_0.io.wakeup_ports[4].bits.uop.uses_stq, issue_slots[0].wakeup_ports[4].bits.uop.uses_stq connect slots_0.io.wakeup_ports[4].bits.uop.uses_ldq, issue_slots[0].wakeup_ports[4].bits.uop.uses_ldq connect slots_0.io.wakeup_ports[4].bits.uop.mem_signed, issue_slots[0].wakeup_ports[4].bits.uop.mem_signed connect slots_0.io.wakeup_ports[4].bits.uop.mem_size, issue_slots[0].wakeup_ports[4].bits.uop.mem_size connect slots_0.io.wakeup_ports[4].bits.uop.mem_cmd, issue_slots[0].wakeup_ports[4].bits.uop.mem_cmd connect slots_0.io.wakeup_ports[4].bits.uop.exc_cause, issue_slots[0].wakeup_ports[4].bits.uop.exc_cause connect slots_0.io.wakeup_ports[4].bits.uop.exception, issue_slots[0].wakeup_ports[4].bits.uop.exception connect slots_0.io.wakeup_ports[4].bits.uop.stale_pdst, issue_slots[0].wakeup_ports[4].bits.uop.stale_pdst connect slots_0.io.wakeup_ports[4].bits.uop.ppred_busy, issue_slots[0].wakeup_ports[4].bits.uop.ppred_busy connect slots_0.io.wakeup_ports[4].bits.uop.prs3_busy, issue_slots[0].wakeup_ports[4].bits.uop.prs3_busy connect slots_0.io.wakeup_ports[4].bits.uop.prs2_busy, issue_slots[0].wakeup_ports[4].bits.uop.prs2_busy connect slots_0.io.wakeup_ports[4].bits.uop.prs1_busy, issue_slots[0].wakeup_ports[4].bits.uop.prs1_busy connect slots_0.io.wakeup_ports[4].bits.uop.ppred, issue_slots[0].wakeup_ports[4].bits.uop.ppred connect slots_0.io.wakeup_ports[4].bits.uop.prs3, issue_slots[0].wakeup_ports[4].bits.uop.prs3 connect slots_0.io.wakeup_ports[4].bits.uop.prs2, issue_slots[0].wakeup_ports[4].bits.uop.prs2 connect slots_0.io.wakeup_ports[4].bits.uop.prs1, issue_slots[0].wakeup_ports[4].bits.uop.prs1 connect slots_0.io.wakeup_ports[4].bits.uop.pdst, issue_slots[0].wakeup_ports[4].bits.uop.pdst connect slots_0.io.wakeup_ports[4].bits.uop.rxq_idx, issue_slots[0].wakeup_ports[4].bits.uop.rxq_idx connect slots_0.io.wakeup_ports[4].bits.uop.stq_idx, issue_slots[0].wakeup_ports[4].bits.uop.stq_idx connect slots_0.io.wakeup_ports[4].bits.uop.ldq_idx, issue_slots[0].wakeup_ports[4].bits.uop.ldq_idx connect slots_0.io.wakeup_ports[4].bits.uop.rob_idx, issue_slots[0].wakeup_ports[4].bits.uop.rob_idx connect slots_0.io.wakeup_ports[4].bits.uop.fp_ctrl.vec, issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.vec connect slots_0.io.wakeup_ports[4].bits.uop.fp_ctrl.wflags, issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.wflags connect slots_0.io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt, issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect slots_0.io.wakeup_ports[4].bits.uop.fp_ctrl.div, issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.div connect slots_0.io.wakeup_ports[4].bits.uop.fp_ctrl.fma, issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.fma connect slots_0.io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect slots_0.io.wakeup_ports[4].bits.uop.fp_ctrl.toint, issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.toint connect slots_0.io.wakeup_ports[4].bits.uop.fp_ctrl.fromint, issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.fromint connect slots_0.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect slots_0.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect slots_0.io.wakeup_ports[4].bits.uop.fp_ctrl.swap23, issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect slots_0.io.wakeup_ports[4].bits.uop.fp_ctrl.swap12, issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect slots_0.io.wakeup_ports[4].bits.uop.fp_ctrl.ren3, issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect slots_0.io.wakeup_ports[4].bits.uop.fp_ctrl.ren2, issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect slots_0.io.wakeup_ports[4].bits.uop.fp_ctrl.ren1, issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect slots_0.io.wakeup_ports[4].bits.uop.fp_ctrl.wen, issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.wen connect slots_0.io.wakeup_ports[4].bits.uop.fp_ctrl.ldst, issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.ldst connect slots_0.io.wakeup_ports[4].bits.uop.op2_sel, issue_slots[0].wakeup_ports[4].bits.uop.op2_sel connect slots_0.io.wakeup_ports[4].bits.uop.op1_sel, issue_slots[0].wakeup_ports[4].bits.uop.op1_sel connect slots_0.io.wakeup_ports[4].bits.uop.imm_packed, issue_slots[0].wakeup_ports[4].bits.uop.imm_packed connect slots_0.io.wakeup_ports[4].bits.uop.pimm, issue_slots[0].wakeup_ports[4].bits.uop.pimm connect slots_0.io.wakeup_ports[4].bits.uop.imm_sel, issue_slots[0].wakeup_ports[4].bits.uop.imm_sel connect slots_0.io.wakeup_ports[4].bits.uop.imm_rename, issue_slots[0].wakeup_ports[4].bits.uop.imm_rename connect slots_0.io.wakeup_ports[4].bits.uop.taken, issue_slots[0].wakeup_ports[4].bits.uop.taken connect slots_0.io.wakeup_ports[4].bits.uop.pc_lob, issue_slots[0].wakeup_ports[4].bits.uop.pc_lob connect slots_0.io.wakeup_ports[4].bits.uop.edge_inst, issue_slots[0].wakeup_ports[4].bits.uop.edge_inst connect slots_0.io.wakeup_ports[4].bits.uop.ftq_idx, issue_slots[0].wakeup_ports[4].bits.uop.ftq_idx connect slots_0.io.wakeup_ports[4].bits.uop.is_mov, issue_slots[0].wakeup_ports[4].bits.uop.is_mov connect slots_0.io.wakeup_ports[4].bits.uop.is_rocc, issue_slots[0].wakeup_ports[4].bits.uop.is_rocc connect slots_0.io.wakeup_ports[4].bits.uop.is_sys_pc2epc, issue_slots[0].wakeup_ports[4].bits.uop.is_sys_pc2epc connect slots_0.io.wakeup_ports[4].bits.uop.is_eret, issue_slots[0].wakeup_ports[4].bits.uop.is_eret connect slots_0.io.wakeup_ports[4].bits.uop.is_amo, issue_slots[0].wakeup_ports[4].bits.uop.is_amo connect slots_0.io.wakeup_ports[4].bits.uop.is_sfence, issue_slots[0].wakeup_ports[4].bits.uop.is_sfence connect slots_0.io.wakeup_ports[4].bits.uop.is_fencei, issue_slots[0].wakeup_ports[4].bits.uop.is_fencei connect slots_0.io.wakeup_ports[4].bits.uop.is_fence, issue_slots[0].wakeup_ports[4].bits.uop.is_fence connect slots_0.io.wakeup_ports[4].bits.uop.is_sfb, issue_slots[0].wakeup_ports[4].bits.uop.is_sfb connect slots_0.io.wakeup_ports[4].bits.uop.br_type, issue_slots[0].wakeup_ports[4].bits.uop.br_type connect slots_0.io.wakeup_ports[4].bits.uop.br_tag, issue_slots[0].wakeup_ports[4].bits.uop.br_tag connect slots_0.io.wakeup_ports[4].bits.uop.br_mask, issue_slots[0].wakeup_ports[4].bits.uop.br_mask connect slots_0.io.wakeup_ports[4].bits.uop.dis_col_sel, issue_slots[0].wakeup_ports[4].bits.uop.dis_col_sel connect slots_0.io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint, issue_slots[0].wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect slots_0.io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint, issue_slots[0].wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect slots_0.io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint, issue_slots[0].wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect slots_0.io.wakeup_ports[4].bits.uop.iw_p2_speculative_child, issue_slots[0].wakeup_ports[4].bits.uop.iw_p2_speculative_child connect slots_0.io.wakeup_ports[4].bits.uop.iw_p1_speculative_child, issue_slots[0].wakeup_ports[4].bits.uop.iw_p1_speculative_child connect slots_0.io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen, issue_slots[0].wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect slots_0.io.wakeup_ports[4].bits.uop.iw_issued_partial_agen, issue_slots[0].wakeup_ports[4].bits.uop.iw_issued_partial_agen connect slots_0.io.wakeup_ports[4].bits.uop.iw_issued, issue_slots[0].wakeup_ports[4].bits.uop.iw_issued connect slots_0.io.wakeup_ports[4].bits.uop.fu_code[0], issue_slots[0].wakeup_ports[4].bits.uop.fu_code[0] connect slots_0.io.wakeup_ports[4].bits.uop.fu_code[1], issue_slots[0].wakeup_ports[4].bits.uop.fu_code[1] connect slots_0.io.wakeup_ports[4].bits.uop.fu_code[2], issue_slots[0].wakeup_ports[4].bits.uop.fu_code[2] connect slots_0.io.wakeup_ports[4].bits.uop.fu_code[3], issue_slots[0].wakeup_ports[4].bits.uop.fu_code[3] connect slots_0.io.wakeup_ports[4].bits.uop.fu_code[4], issue_slots[0].wakeup_ports[4].bits.uop.fu_code[4] connect slots_0.io.wakeup_ports[4].bits.uop.fu_code[5], issue_slots[0].wakeup_ports[4].bits.uop.fu_code[5] connect slots_0.io.wakeup_ports[4].bits.uop.fu_code[6], issue_slots[0].wakeup_ports[4].bits.uop.fu_code[6] connect slots_0.io.wakeup_ports[4].bits.uop.fu_code[7], issue_slots[0].wakeup_ports[4].bits.uop.fu_code[7] connect slots_0.io.wakeup_ports[4].bits.uop.fu_code[8], issue_slots[0].wakeup_ports[4].bits.uop.fu_code[8] connect slots_0.io.wakeup_ports[4].bits.uop.fu_code[9], issue_slots[0].wakeup_ports[4].bits.uop.fu_code[9] connect slots_0.io.wakeup_ports[4].bits.uop.iq_type[0], issue_slots[0].wakeup_ports[4].bits.uop.iq_type[0] connect slots_0.io.wakeup_ports[4].bits.uop.iq_type[1], issue_slots[0].wakeup_ports[4].bits.uop.iq_type[1] connect slots_0.io.wakeup_ports[4].bits.uop.iq_type[2], issue_slots[0].wakeup_ports[4].bits.uop.iq_type[2] connect slots_0.io.wakeup_ports[4].bits.uop.iq_type[3], issue_slots[0].wakeup_ports[4].bits.uop.iq_type[3] connect slots_0.io.wakeup_ports[4].bits.uop.debug_pc, issue_slots[0].wakeup_ports[4].bits.uop.debug_pc connect slots_0.io.wakeup_ports[4].bits.uop.is_rvc, issue_slots[0].wakeup_ports[4].bits.uop.is_rvc connect slots_0.io.wakeup_ports[4].bits.uop.debug_inst, issue_slots[0].wakeup_ports[4].bits.uop.debug_inst connect slots_0.io.wakeup_ports[4].bits.uop.inst, issue_slots[0].wakeup_ports[4].bits.uop.inst connect slots_0.io.wakeup_ports[4].valid, issue_slots[0].wakeup_ports[4].valid connect slots_0.io.squash_grant, issue_slots[0].squash_grant connect slots_0.io.clear, issue_slots[0].clear connect slots_0.io.kill, issue_slots[0].kill connect slots_0.io.brupdate.b2.target_offset, issue_slots[0].brupdate.b2.target_offset connect slots_0.io.brupdate.b2.jalr_target, issue_slots[0].brupdate.b2.jalr_target connect slots_0.io.brupdate.b2.pc_sel, issue_slots[0].brupdate.b2.pc_sel connect slots_0.io.brupdate.b2.cfi_type, issue_slots[0].brupdate.b2.cfi_type connect slots_0.io.brupdate.b2.taken, issue_slots[0].brupdate.b2.taken connect slots_0.io.brupdate.b2.mispredict, issue_slots[0].brupdate.b2.mispredict connect slots_0.io.brupdate.b2.uop.debug_tsrc, issue_slots[0].brupdate.b2.uop.debug_tsrc connect slots_0.io.brupdate.b2.uop.debug_fsrc, issue_slots[0].brupdate.b2.uop.debug_fsrc connect slots_0.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[0].brupdate.b2.uop.bp_xcpt_if connect slots_0.io.brupdate.b2.uop.bp_debug_if, issue_slots[0].brupdate.b2.uop.bp_debug_if connect slots_0.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[0].brupdate.b2.uop.xcpt_ma_if connect slots_0.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[0].brupdate.b2.uop.xcpt_ae_if connect slots_0.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[0].brupdate.b2.uop.xcpt_pf_if connect slots_0.io.brupdate.b2.uop.fp_typ, issue_slots[0].brupdate.b2.uop.fp_typ connect slots_0.io.brupdate.b2.uop.fp_rm, issue_slots[0].brupdate.b2.uop.fp_rm connect slots_0.io.brupdate.b2.uop.fp_val, issue_slots[0].brupdate.b2.uop.fp_val connect slots_0.io.brupdate.b2.uop.fcn_op, issue_slots[0].brupdate.b2.uop.fcn_op connect slots_0.io.brupdate.b2.uop.fcn_dw, issue_slots[0].brupdate.b2.uop.fcn_dw connect slots_0.io.brupdate.b2.uop.frs3_en, issue_slots[0].brupdate.b2.uop.frs3_en connect slots_0.io.brupdate.b2.uop.lrs2_rtype, issue_slots[0].brupdate.b2.uop.lrs2_rtype connect slots_0.io.brupdate.b2.uop.lrs1_rtype, issue_slots[0].brupdate.b2.uop.lrs1_rtype connect slots_0.io.brupdate.b2.uop.dst_rtype, issue_slots[0].brupdate.b2.uop.dst_rtype connect slots_0.io.brupdate.b2.uop.lrs3, issue_slots[0].brupdate.b2.uop.lrs3 connect slots_0.io.brupdate.b2.uop.lrs2, issue_slots[0].brupdate.b2.uop.lrs2 connect slots_0.io.brupdate.b2.uop.lrs1, issue_slots[0].brupdate.b2.uop.lrs1 connect slots_0.io.brupdate.b2.uop.ldst, issue_slots[0].brupdate.b2.uop.ldst connect slots_0.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[0].brupdate.b2.uop.ldst_is_rs1 connect slots_0.io.brupdate.b2.uop.csr_cmd, issue_slots[0].brupdate.b2.uop.csr_cmd connect slots_0.io.brupdate.b2.uop.flush_on_commit, issue_slots[0].brupdate.b2.uop.flush_on_commit connect slots_0.io.brupdate.b2.uop.is_unique, issue_slots[0].brupdate.b2.uop.is_unique connect slots_0.io.brupdate.b2.uop.uses_stq, issue_slots[0].brupdate.b2.uop.uses_stq connect slots_0.io.brupdate.b2.uop.uses_ldq, issue_slots[0].brupdate.b2.uop.uses_ldq connect slots_0.io.brupdate.b2.uop.mem_signed, issue_slots[0].brupdate.b2.uop.mem_signed connect slots_0.io.brupdate.b2.uop.mem_size, issue_slots[0].brupdate.b2.uop.mem_size connect slots_0.io.brupdate.b2.uop.mem_cmd, issue_slots[0].brupdate.b2.uop.mem_cmd connect slots_0.io.brupdate.b2.uop.exc_cause, issue_slots[0].brupdate.b2.uop.exc_cause connect slots_0.io.brupdate.b2.uop.exception, issue_slots[0].brupdate.b2.uop.exception connect slots_0.io.brupdate.b2.uop.stale_pdst, issue_slots[0].brupdate.b2.uop.stale_pdst connect slots_0.io.brupdate.b2.uop.ppred_busy, issue_slots[0].brupdate.b2.uop.ppred_busy connect slots_0.io.brupdate.b2.uop.prs3_busy, issue_slots[0].brupdate.b2.uop.prs3_busy connect slots_0.io.brupdate.b2.uop.prs2_busy, issue_slots[0].brupdate.b2.uop.prs2_busy connect slots_0.io.brupdate.b2.uop.prs1_busy, issue_slots[0].brupdate.b2.uop.prs1_busy connect slots_0.io.brupdate.b2.uop.ppred, issue_slots[0].brupdate.b2.uop.ppred connect slots_0.io.brupdate.b2.uop.prs3, issue_slots[0].brupdate.b2.uop.prs3 connect slots_0.io.brupdate.b2.uop.prs2, issue_slots[0].brupdate.b2.uop.prs2 connect slots_0.io.brupdate.b2.uop.prs1, issue_slots[0].brupdate.b2.uop.prs1 connect slots_0.io.brupdate.b2.uop.pdst, issue_slots[0].brupdate.b2.uop.pdst connect slots_0.io.brupdate.b2.uop.rxq_idx, issue_slots[0].brupdate.b2.uop.rxq_idx connect slots_0.io.brupdate.b2.uop.stq_idx, issue_slots[0].brupdate.b2.uop.stq_idx connect slots_0.io.brupdate.b2.uop.ldq_idx, issue_slots[0].brupdate.b2.uop.ldq_idx connect slots_0.io.brupdate.b2.uop.rob_idx, issue_slots[0].brupdate.b2.uop.rob_idx connect slots_0.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[0].brupdate.b2.uop.fp_ctrl.vec connect slots_0.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[0].brupdate.b2.uop.fp_ctrl.wflags connect slots_0.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[0].brupdate.b2.uop.fp_ctrl.sqrt connect slots_0.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[0].brupdate.b2.uop.fp_ctrl.div connect slots_0.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[0].brupdate.b2.uop.fp_ctrl.fma connect slots_0.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[0].brupdate.b2.uop.fp_ctrl.fastpipe connect slots_0.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[0].brupdate.b2.uop.fp_ctrl.toint connect slots_0.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[0].brupdate.b2.uop.fp_ctrl.fromint connect slots_0.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[0].brupdate.b2.uop.fp_ctrl.typeTagOut connect slots_0.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[0].brupdate.b2.uop.fp_ctrl.typeTagIn connect slots_0.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[0].brupdate.b2.uop.fp_ctrl.swap23 connect slots_0.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[0].brupdate.b2.uop.fp_ctrl.swap12 connect slots_0.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[0].brupdate.b2.uop.fp_ctrl.ren3 connect slots_0.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[0].brupdate.b2.uop.fp_ctrl.ren2 connect slots_0.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[0].brupdate.b2.uop.fp_ctrl.ren1 connect slots_0.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[0].brupdate.b2.uop.fp_ctrl.wen connect slots_0.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[0].brupdate.b2.uop.fp_ctrl.ldst connect slots_0.io.brupdate.b2.uop.op2_sel, issue_slots[0].brupdate.b2.uop.op2_sel connect slots_0.io.brupdate.b2.uop.op1_sel, issue_slots[0].brupdate.b2.uop.op1_sel connect slots_0.io.brupdate.b2.uop.imm_packed, issue_slots[0].brupdate.b2.uop.imm_packed connect slots_0.io.brupdate.b2.uop.pimm, issue_slots[0].brupdate.b2.uop.pimm connect slots_0.io.brupdate.b2.uop.imm_sel, issue_slots[0].brupdate.b2.uop.imm_sel connect slots_0.io.brupdate.b2.uop.imm_rename, issue_slots[0].brupdate.b2.uop.imm_rename connect slots_0.io.brupdate.b2.uop.taken, issue_slots[0].brupdate.b2.uop.taken connect slots_0.io.brupdate.b2.uop.pc_lob, issue_slots[0].brupdate.b2.uop.pc_lob connect slots_0.io.brupdate.b2.uop.edge_inst, issue_slots[0].brupdate.b2.uop.edge_inst connect slots_0.io.brupdate.b2.uop.ftq_idx, issue_slots[0].brupdate.b2.uop.ftq_idx connect slots_0.io.brupdate.b2.uop.is_mov, issue_slots[0].brupdate.b2.uop.is_mov connect slots_0.io.brupdate.b2.uop.is_rocc, issue_slots[0].brupdate.b2.uop.is_rocc connect slots_0.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[0].brupdate.b2.uop.is_sys_pc2epc connect slots_0.io.brupdate.b2.uop.is_eret, issue_slots[0].brupdate.b2.uop.is_eret connect slots_0.io.brupdate.b2.uop.is_amo, issue_slots[0].brupdate.b2.uop.is_amo connect slots_0.io.brupdate.b2.uop.is_sfence, issue_slots[0].brupdate.b2.uop.is_sfence connect slots_0.io.brupdate.b2.uop.is_fencei, issue_slots[0].brupdate.b2.uop.is_fencei connect slots_0.io.brupdate.b2.uop.is_fence, issue_slots[0].brupdate.b2.uop.is_fence connect slots_0.io.brupdate.b2.uop.is_sfb, issue_slots[0].brupdate.b2.uop.is_sfb connect slots_0.io.brupdate.b2.uop.br_type, issue_slots[0].brupdate.b2.uop.br_type connect slots_0.io.brupdate.b2.uop.br_tag, issue_slots[0].brupdate.b2.uop.br_tag connect slots_0.io.brupdate.b2.uop.br_mask, issue_slots[0].brupdate.b2.uop.br_mask connect slots_0.io.brupdate.b2.uop.dis_col_sel, issue_slots[0].brupdate.b2.uop.dis_col_sel connect slots_0.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[0].brupdate.b2.uop.iw_p3_bypass_hint connect slots_0.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[0].brupdate.b2.uop.iw_p2_bypass_hint connect slots_0.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[0].brupdate.b2.uop.iw_p1_bypass_hint connect slots_0.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[0].brupdate.b2.uop.iw_p2_speculative_child connect slots_0.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[0].brupdate.b2.uop.iw_p1_speculative_child connect slots_0.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[0].brupdate.b2.uop.iw_issued_partial_dgen connect slots_0.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[0].brupdate.b2.uop.iw_issued_partial_agen connect slots_0.io.brupdate.b2.uop.iw_issued, issue_slots[0].brupdate.b2.uop.iw_issued connect slots_0.io.brupdate.b2.uop.fu_code[0], issue_slots[0].brupdate.b2.uop.fu_code[0] connect slots_0.io.brupdate.b2.uop.fu_code[1], issue_slots[0].brupdate.b2.uop.fu_code[1] connect slots_0.io.brupdate.b2.uop.fu_code[2], issue_slots[0].brupdate.b2.uop.fu_code[2] connect slots_0.io.brupdate.b2.uop.fu_code[3], issue_slots[0].brupdate.b2.uop.fu_code[3] connect slots_0.io.brupdate.b2.uop.fu_code[4], issue_slots[0].brupdate.b2.uop.fu_code[4] connect slots_0.io.brupdate.b2.uop.fu_code[5], issue_slots[0].brupdate.b2.uop.fu_code[5] connect slots_0.io.brupdate.b2.uop.fu_code[6], issue_slots[0].brupdate.b2.uop.fu_code[6] connect slots_0.io.brupdate.b2.uop.fu_code[7], issue_slots[0].brupdate.b2.uop.fu_code[7] connect slots_0.io.brupdate.b2.uop.fu_code[8], issue_slots[0].brupdate.b2.uop.fu_code[8] connect slots_0.io.brupdate.b2.uop.fu_code[9], issue_slots[0].brupdate.b2.uop.fu_code[9] connect slots_0.io.brupdate.b2.uop.iq_type[0], issue_slots[0].brupdate.b2.uop.iq_type[0] connect slots_0.io.brupdate.b2.uop.iq_type[1], issue_slots[0].brupdate.b2.uop.iq_type[1] connect slots_0.io.brupdate.b2.uop.iq_type[2], issue_slots[0].brupdate.b2.uop.iq_type[2] connect slots_0.io.brupdate.b2.uop.iq_type[3], issue_slots[0].brupdate.b2.uop.iq_type[3] connect slots_0.io.brupdate.b2.uop.debug_pc, issue_slots[0].brupdate.b2.uop.debug_pc connect slots_0.io.brupdate.b2.uop.is_rvc, issue_slots[0].brupdate.b2.uop.is_rvc connect slots_0.io.brupdate.b2.uop.debug_inst, issue_slots[0].brupdate.b2.uop.debug_inst connect slots_0.io.brupdate.b2.uop.inst, issue_slots[0].brupdate.b2.uop.inst connect slots_0.io.brupdate.b1.mispredict_mask, issue_slots[0].brupdate.b1.mispredict_mask connect slots_0.io.brupdate.b1.resolve_mask, issue_slots[0].brupdate.b1.resolve_mask connect issue_slots[0].out_uop.debug_tsrc, slots_0.io.out_uop.debug_tsrc connect issue_slots[0].out_uop.debug_fsrc, slots_0.io.out_uop.debug_fsrc connect issue_slots[0].out_uop.bp_xcpt_if, slots_0.io.out_uop.bp_xcpt_if connect issue_slots[0].out_uop.bp_debug_if, slots_0.io.out_uop.bp_debug_if connect issue_slots[0].out_uop.xcpt_ma_if, slots_0.io.out_uop.xcpt_ma_if connect issue_slots[0].out_uop.xcpt_ae_if, slots_0.io.out_uop.xcpt_ae_if connect issue_slots[0].out_uop.xcpt_pf_if, slots_0.io.out_uop.xcpt_pf_if connect issue_slots[0].out_uop.fp_typ, slots_0.io.out_uop.fp_typ connect issue_slots[0].out_uop.fp_rm, slots_0.io.out_uop.fp_rm connect issue_slots[0].out_uop.fp_val, slots_0.io.out_uop.fp_val connect issue_slots[0].out_uop.fcn_op, slots_0.io.out_uop.fcn_op connect issue_slots[0].out_uop.fcn_dw, slots_0.io.out_uop.fcn_dw connect issue_slots[0].out_uop.frs3_en, slots_0.io.out_uop.frs3_en connect issue_slots[0].out_uop.lrs2_rtype, slots_0.io.out_uop.lrs2_rtype connect issue_slots[0].out_uop.lrs1_rtype, slots_0.io.out_uop.lrs1_rtype connect issue_slots[0].out_uop.dst_rtype, slots_0.io.out_uop.dst_rtype connect issue_slots[0].out_uop.lrs3, slots_0.io.out_uop.lrs3 connect issue_slots[0].out_uop.lrs2, slots_0.io.out_uop.lrs2 connect issue_slots[0].out_uop.lrs1, slots_0.io.out_uop.lrs1 connect issue_slots[0].out_uop.ldst, slots_0.io.out_uop.ldst connect issue_slots[0].out_uop.ldst_is_rs1, slots_0.io.out_uop.ldst_is_rs1 connect issue_slots[0].out_uop.csr_cmd, slots_0.io.out_uop.csr_cmd connect issue_slots[0].out_uop.flush_on_commit, slots_0.io.out_uop.flush_on_commit connect issue_slots[0].out_uop.is_unique, slots_0.io.out_uop.is_unique connect issue_slots[0].out_uop.uses_stq, slots_0.io.out_uop.uses_stq connect issue_slots[0].out_uop.uses_ldq, slots_0.io.out_uop.uses_ldq connect issue_slots[0].out_uop.mem_signed, slots_0.io.out_uop.mem_signed connect issue_slots[0].out_uop.mem_size, slots_0.io.out_uop.mem_size connect issue_slots[0].out_uop.mem_cmd, slots_0.io.out_uop.mem_cmd connect issue_slots[0].out_uop.exc_cause, slots_0.io.out_uop.exc_cause connect issue_slots[0].out_uop.exception, slots_0.io.out_uop.exception connect issue_slots[0].out_uop.stale_pdst, slots_0.io.out_uop.stale_pdst connect issue_slots[0].out_uop.ppred_busy, slots_0.io.out_uop.ppred_busy connect issue_slots[0].out_uop.prs3_busy, slots_0.io.out_uop.prs3_busy connect issue_slots[0].out_uop.prs2_busy, slots_0.io.out_uop.prs2_busy connect issue_slots[0].out_uop.prs1_busy, slots_0.io.out_uop.prs1_busy connect issue_slots[0].out_uop.ppred, slots_0.io.out_uop.ppred connect issue_slots[0].out_uop.prs3, slots_0.io.out_uop.prs3 connect issue_slots[0].out_uop.prs2, slots_0.io.out_uop.prs2 connect issue_slots[0].out_uop.prs1, slots_0.io.out_uop.prs1 connect issue_slots[0].out_uop.pdst, slots_0.io.out_uop.pdst connect issue_slots[0].out_uop.rxq_idx, slots_0.io.out_uop.rxq_idx connect issue_slots[0].out_uop.stq_idx, slots_0.io.out_uop.stq_idx connect issue_slots[0].out_uop.ldq_idx, slots_0.io.out_uop.ldq_idx connect issue_slots[0].out_uop.rob_idx, slots_0.io.out_uop.rob_idx connect issue_slots[0].out_uop.fp_ctrl.vec, slots_0.io.out_uop.fp_ctrl.vec connect issue_slots[0].out_uop.fp_ctrl.wflags, slots_0.io.out_uop.fp_ctrl.wflags connect issue_slots[0].out_uop.fp_ctrl.sqrt, slots_0.io.out_uop.fp_ctrl.sqrt connect issue_slots[0].out_uop.fp_ctrl.div, slots_0.io.out_uop.fp_ctrl.div connect issue_slots[0].out_uop.fp_ctrl.fma, slots_0.io.out_uop.fp_ctrl.fma connect issue_slots[0].out_uop.fp_ctrl.fastpipe, slots_0.io.out_uop.fp_ctrl.fastpipe connect issue_slots[0].out_uop.fp_ctrl.toint, slots_0.io.out_uop.fp_ctrl.toint connect issue_slots[0].out_uop.fp_ctrl.fromint, slots_0.io.out_uop.fp_ctrl.fromint connect issue_slots[0].out_uop.fp_ctrl.typeTagOut, slots_0.io.out_uop.fp_ctrl.typeTagOut connect issue_slots[0].out_uop.fp_ctrl.typeTagIn, slots_0.io.out_uop.fp_ctrl.typeTagIn connect issue_slots[0].out_uop.fp_ctrl.swap23, slots_0.io.out_uop.fp_ctrl.swap23 connect issue_slots[0].out_uop.fp_ctrl.swap12, slots_0.io.out_uop.fp_ctrl.swap12 connect issue_slots[0].out_uop.fp_ctrl.ren3, slots_0.io.out_uop.fp_ctrl.ren3 connect issue_slots[0].out_uop.fp_ctrl.ren2, slots_0.io.out_uop.fp_ctrl.ren2 connect issue_slots[0].out_uop.fp_ctrl.ren1, slots_0.io.out_uop.fp_ctrl.ren1 connect issue_slots[0].out_uop.fp_ctrl.wen, slots_0.io.out_uop.fp_ctrl.wen connect issue_slots[0].out_uop.fp_ctrl.ldst, slots_0.io.out_uop.fp_ctrl.ldst connect issue_slots[0].out_uop.op2_sel, slots_0.io.out_uop.op2_sel connect issue_slots[0].out_uop.op1_sel, slots_0.io.out_uop.op1_sel connect issue_slots[0].out_uop.imm_packed, slots_0.io.out_uop.imm_packed connect issue_slots[0].out_uop.pimm, slots_0.io.out_uop.pimm connect issue_slots[0].out_uop.imm_sel, slots_0.io.out_uop.imm_sel connect issue_slots[0].out_uop.imm_rename, slots_0.io.out_uop.imm_rename connect issue_slots[0].out_uop.taken, slots_0.io.out_uop.taken connect issue_slots[0].out_uop.pc_lob, slots_0.io.out_uop.pc_lob connect issue_slots[0].out_uop.edge_inst, slots_0.io.out_uop.edge_inst connect issue_slots[0].out_uop.ftq_idx, slots_0.io.out_uop.ftq_idx connect issue_slots[0].out_uop.is_mov, slots_0.io.out_uop.is_mov connect issue_slots[0].out_uop.is_rocc, slots_0.io.out_uop.is_rocc connect issue_slots[0].out_uop.is_sys_pc2epc, slots_0.io.out_uop.is_sys_pc2epc connect issue_slots[0].out_uop.is_eret, slots_0.io.out_uop.is_eret connect issue_slots[0].out_uop.is_amo, slots_0.io.out_uop.is_amo connect issue_slots[0].out_uop.is_sfence, slots_0.io.out_uop.is_sfence connect issue_slots[0].out_uop.is_fencei, slots_0.io.out_uop.is_fencei connect issue_slots[0].out_uop.is_fence, slots_0.io.out_uop.is_fence connect issue_slots[0].out_uop.is_sfb, slots_0.io.out_uop.is_sfb connect issue_slots[0].out_uop.br_type, slots_0.io.out_uop.br_type connect issue_slots[0].out_uop.br_tag, slots_0.io.out_uop.br_tag connect issue_slots[0].out_uop.br_mask, slots_0.io.out_uop.br_mask connect issue_slots[0].out_uop.dis_col_sel, slots_0.io.out_uop.dis_col_sel connect issue_slots[0].out_uop.iw_p3_bypass_hint, slots_0.io.out_uop.iw_p3_bypass_hint connect issue_slots[0].out_uop.iw_p2_bypass_hint, slots_0.io.out_uop.iw_p2_bypass_hint connect issue_slots[0].out_uop.iw_p1_bypass_hint, slots_0.io.out_uop.iw_p1_bypass_hint connect issue_slots[0].out_uop.iw_p2_speculative_child, slots_0.io.out_uop.iw_p2_speculative_child connect issue_slots[0].out_uop.iw_p1_speculative_child, slots_0.io.out_uop.iw_p1_speculative_child connect issue_slots[0].out_uop.iw_issued_partial_dgen, slots_0.io.out_uop.iw_issued_partial_dgen connect issue_slots[0].out_uop.iw_issued_partial_agen, slots_0.io.out_uop.iw_issued_partial_agen connect issue_slots[0].out_uop.iw_issued, slots_0.io.out_uop.iw_issued connect issue_slots[0].out_uop.fu_code[0], slots_0.io.out_uop.fu_code[0] connect issue_slots[0].out_uop.fu_code[1], slots_0.io.out_uop.fu_code[1] connect issue_slots[0].out_uop.fu_code[2], slots_0.io.out_uop.fu_code[2] connect issue_slots[0].out_uop.fu_code[3], slots_0.io.out_uop.fu_code[3] connect issue_slots[0].out_uop.fu_code[4], slots_0.io.out_uop.fu_code[4] connect issue_slots[0].out_uop.fu_code[5], slots_0.io.out_uop.fu_code[5] connect issue_slots[0].out_uop.fu_code[6], slots_0.io.out_uop.fu_code[6] connect issue_slots[0].out_uop.fu_code[7], slots_0.io.out_uop.fu_code[7] connect issue_slots[0].out_uop.fu_code[8], slots_0.io.out_uop.fu_code[8] connect issue_slots[0].out_uop.fu_code[9], slots_0.io.out_uop.fu_code[9] connect issue_slots[0].out_uop.iq_type[0], slots_0.io.out_uop.iq_type[0] connect issue_slots[0].out_uop.iq_type[1], slots_0.io.out_uop.iq_type[1] connect issue_slots[0].out_uop.iq_type[2], slots_0.io.out_uop.iq_type[2] connect issue_slots[0].out_uop.iq_type[3], slots_0.io.out_uop.iq_type[3] connect issue_slots[0].out_uop.debug_pc, slots_0.io.out_uop.debug_pc connect issue_slots[0].out_uop.is_rvc, slots_0.io.out_uop.is_rvc connect issue_slots[0].out_uop.debug_inst, slots_0.io.out_uop.debug_inst connect issue_slots[0].out_uop.inst, slots_0.io.out_uop.inst connect slots_0.io.in_uop.bits.debug_tsrc, issue_slots[0].in_uop.bits.debug_tsrc connect slots_0.io.in_uop.bits.debug_fsrc, issue_slots[0].in_uop.bits.debug_fsrc connect slots_0.io.in_uop.bits.bp_xcpt_if, issue_slots[0].in_uop.bits.bp_xcpt_if connect slots_0.io.in_uop.bits.bp_debug_if, issue_slots[0].in_uop.bits.bp_debug_if connect slots_0.io.in_uop.bits.xcpt_ma_if, issue_slots[0].in_uop.bits.xcpt_ma_if connect slots_0.io.in_uop.bits.xcpt_ae_if, issue_slots[0].in_uop.bits.xcpt_ae_if connect slots_0.io.in_uop.bits.xcpt_pf_if, issue_slots[0].in_uop.bits.xcpt_pf_if connect slots_0.io.in_uop.bits.fp_typ, issue_slots[0].in_uop.bits.fp_typ connect slots_0.io.in_uop.bits.fp_rm, issue_slots[0].in_uop.bits.fp_rm connect slots_0.io.in_uop.bits.fp_val, issue_slots[0].in_uop.bits.fp_val connect slots_0.io.in_uop.bits.fcn_op, issue_slots[0].in_uop.bits.fcn_op connect slots_0.io.in_uop.bits.fcn_dw, issue_slots[0].in_uop.bits.fcn_dw connect slots_0.io.in_uop.bits.frs3_en, issue_slots[0].in_uop.bits.frs3_en connect slots_0.io.in_uop.bits.lrs2_rtype, issue_slots[0].in_uop.bits.lrs2_rtype connect slots_0.io.in_uop.bits.lrs1_rtype, issue_slots[0].in_uop.bits.lrs1_rtype connect slots_0.io.in_uop.bits.dst_rtype, issue_slots[0].in_uop.bits.dst_rtype connect slots_0.io.in_uop.bits.lrs3, issue_slots[0].in_uop.bits.lrs3 connect slots_0.io.in_uop.bits.lrs2, issue_slots[0].in_uop.bits.lrs2 connect slots_0.io.in_uop.bits.lrs1, issue_slots[0].in_uop.bits.lrs1 connect slots_0.io.in_uop.bits.ldst, issue_slots[0].in_uop.bits.ldst connect slots_0.io.in_uop.bits.ldst_is_rs1, issue_slots[0].in_uop.bits.ldst_is_rs1 connect slots_0.io.in_uop.bits.csr_cmd, issue_slots[0].in_uop.bits.csr_cmd connect slots_0.io.in_uop.bits.flush_on_commit, issue_slots[0].in_uop.bits.flush_on_commit connect slots_0.io.in_uop.bits.is_unique, issue_slots[0].in_uop.bits.is_unique connect slots_0.io.in_uop.bits.uses_stq, issue_slots[0].in_uop.bits.uses_stq connect slots_0.io.in_uop.bits.uses_ldq, issue_slots[0].in_uop.bits.uses_ldq connect slots_0.io.in_uop.bits.mem_signed, issue_slots[0].in_uop.bits.mem_signed connect slots_0.io.in_uop.bits.mem_size, issue_slots[0].in_uop.bits.mem_size connect slots_0.io.in_uop.bits.mem_cmd, issue_slots[0].in_uop.bits.mem_cmd connect slots_0.io.in_uop.bits.exc_cause, issue_slots[0].in_uop.bits.exc_cause connect slots_0.io.in_uop.bits.exception, issue_slots[0].in_uop.bits.exception connect slots_0.io.in_uop.bits.stale_pdst, issue_slots[0].in_uop.bits.stale_pdst connect slots_0.io.in_uop.bits.ppred_busy, issue_slots[0].in_uop.bits.ppred_busy connect slots_0.io.in_uop.bits.prs3_busy, issue_slots[0].in_uop.bits.prs3_busy connect slots_0.io.in_uop.bits.prs2_busy, issue_slots[0].in_uop.bits.prs2_busy connect slots_0.io.in_uop.bits.prs1_busy, issue_slots[0].in_uop.bits.prs1_busy connect slots_0.io.in_uop.bits.ppred, issue_slots[0].in_uop.bits.ppred connect slots_0.io.in_uop.bits.prs3, issue_slots[0].in_uop.bits.prs3 connect slots_0.io.in_uop.bits.prs2, issue_slots[0].in_uop.bits.prs2 connect slots_0.io.in_uop.bits.prs1, issue_slots[0].in_uop.bits.prs1 connect slots_0.io.in_uop.bits.pdst, issue_slots[0].in_uop.bits.pdst connect slots_0.io.in_uop.bits.rxq_idx, issue_slots[0].in_uop.bits.rxq_idx connect slots_0.io.in_uop.bits.stq_idx, issue_slots[0].in_uop.bits.stq_idx connect slots_0.io.in_uop.bits.ldq_idx, issue_slots[0].in_uop.bits.ldq_idx connect slots_0.io.in_uop.bits.rob_idx, issue_slots[0].in_uop.bits.rob_idx connect slots_0.io.in_uop.bits.fp_ctrl.vec, issue_slots[0].in_uop.bits.fp_ctrl.vec connect slots_0.io.in_uop.bits.fp_ctrl.wflags, issue_slots[0].in_uop.bits.fp_ctrl.wflags connect slots_0.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[0].in_uop.bits.fp_ctrl.sqrt connect slots_0.io.in_uop.bits.fp_ctrl.div, issue_slots[0].in_uop.bits.fp_ctrl.div connect slots_0.io.in_uop.bits.fp_ctrl.fma, issue_slots[0].in_uop.bits.fp_ctrl.fma connect slots_0.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[0].in_uop.bits.fp_ctrl.fastpipe connect slots_0.io.in_uop.bits.fp_ctrl.toint, issue_slots[0].in_uop.bits.fp_ctrl.toint connect slots_0.io.in_uop.bits.fp_ctrl.fromint, issue_slots[0].in_uop.bits.fp_ctrl.fromint connect slots_0.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[0].in_uop.bits.fp_ctrl.typeTagOut connect slots_0.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[0].in_uop.bits.fp_ctrl.typeTagIn connect slots_0.io.in_uop.bits.fp_ctrl.swap23, issue_slots[0].in_uop.bits.fp_ctrl.swap23 connect slots_0.io.in_uop.bits.fp_ctrl.swap12, issue_slots[0].in_uop.bits.fp_ctrl.swap12 connect slots_0.io.in_uop.bits.fp_ctrl.ren3, issue_slots[0].in_uop.bits.fp_ctrl.ren3 connect slots_0.io.in_uop.bits.fp_ctrl.ren2, issue_slots[0].in_uop.bits.fp_ctrl.ren2 connect slots_0.io.in_uop.bits.fp_ctrl.ren1, issue_slots[0].in_uop.bits.fp_ctrl.ren1 connect slots_0.io.in_uop.bits.fp_ctrl.wen, issue_slots[0].in_uop.bits.fp_ctrl.wen connect slots_0.io.in_uop.bits.fp_ctrl.ldst, issue_slots[0].in_uop.bits.fp_ctrl.ldst connect slots_0.io.in_uop.bits.op2_sel, issue_slots[0].in_uop.bits.op2_sel connect slots_0.io.in_uop.bits.op1_sel, issue_slots[0].in_uop.bits.op1_sel connect slots_0.io.in_uop.bits.imm_packed, issue_slots[0].in_uop.bits.imm_packed connect slots_0.io.in_uop.bits.pimm, issue_slots[0].in_uop.bits.pimm connect slots_0.io.in_uop.bits.imm_sel, issue_slots[0].in_uop.bits.imm_sel connect slots_0.io.in_uop.bits.imm_rename, issue_slots[0].in_uop.bits.imm_rename connect slots_0.io.in_uop.bits.taken, issue_slots[0].in_uop.bits.taken connect slots_0.io.in_uop.bits.pc_lob, issue_slots[0].in_uop.bits.pc_lob connect slots_0.io.in_uop.bits.edge_inst, issue_slots[0].in_uop.bits.edge_inst connect slots_0.io.in_uop.bits.ftq_idx, issue_slots[0].in_uop.bits.ftq_idx connect slots_0.io.in_uop.bits.is_mov, issue_slots[0].in_uop.bits.is_mov connect slots_0.io.in_uop.bits.is_rocc, issue_slots[0].in_uop.bits.is_rocc connect slots_0.io.in_uop.bits.is_sys_pc2epc, issue_slots[0].in_uop.bits.is_sys_pc2epc connect slots_0.io.in_uop.bits.is_eret, issue_slots[0].in_uop.bits.is_eret connect slots_0.io.in_uop.bits.is_amo, issue_slots[0].in_uop.bits.is_amo connect slots_0.io.in_uop.bits.is_sfence, issue_slots[0].in_uop.bits.is_sfence connect slots_0.io.in_uop.bits.is_fencei, issue_slots[0].in_uop.bits.is_fencei connect slots_0.io.in_uop.bits.is_fence, issue_slots[0].in_uop.bits.is_fence connect slots_0.io.in_uop.bits.is_sfb, issue_slots[0].in_uop.bits.is_sfb connect slots_0.io.in_uop.bits.br_type, issue_slots[0].in_uop.bits.br_type connect slots_0.io.in_uop.bits.br_tag, issue_slots[0].in_uop.bits.br_tag connect slots_0.io.in_uop.bits.br_mask, issue_slots[0].in_uop.bits.br_mask connect slots_0.io.in_uop.bits.dis_col_sel, issue_slots[0].in_uop.bits.dis_col_sel connect slots_0.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[0].in_uop.bits.iw_p3_bypass_hint connect slots_0.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[0].in_uop.bits.iw_p2_bypass_hint connect slots_0.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[0].in_uop.bits.iw_p1_bypass_hint connect slots_0.io.in_uop.bits.iw_p2_speculative_child, issue_slots[0].in_uop.bits.iw_p2_speculative_child connect slots_0.io.in_uop.bits.iw_p1_speculative_child, issue_slots[0].in_uop.bits.iw_p1_speculative_child connect slots_0.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[0].in_uop.bits.iw_issued_partial_dgen connect slots_0.io.in_uop.bits.iw_issued_partial_agen, issue_slots[0].in_uop.bits.iw_issued_partial_agen connect slots_0.io.in_uop.bits.iw_issued, issue_slots[0].in_uop.bits.iw_issued connect slots_0.io.in_uop.bits.fu_code[0], issue_slots[0].in_uop.bits.fu_code[0] connect slots_0.io.in_uop.bits.fu_code[1], issue_slots[0].in_uop.bits.fu_code[1] connect slots_0.io.in_uop.bits.fu_code[2], issue_slots[0].in_uop.bits.fu_code[2] connect slots_0.io.in_uop.bits.fu_code[3], issue_slots[0].in_uop.bits.fu_code[3] connect slots_0.io.in_uop.bits.fu_code[4], issue_slots[0].in_uop.bits.fu_code[4] connect slots_0.io.in_uop.bits.fu_code[5], issue_slots[0].in_uop.bits.fu_code[5] connect slots_0.io.in_uop.bits.fu_code[6], issue_slots[0].in_uop.bits.fu_code[6] connect slots_0.io.in_uop.bits.fu_code[7], issue_slots[0].in_uop.bits.fu_code[7] connect slots_0.io.in_uop.bits.fu_code[8], issue_slots[0].in_uop.bits.fu_code[8] connect slots_0.io.in_uop.bits.fu_code[9], issue_slots[0].in_uop.bits.fu_code[9] connect slots_0.io.in_uop.bits.iq_type[0], issue_slots[0].in_uop.bits.iq_type[0] connect slots_0.io.in_uop.bits.iq_type[1], issue_slots[0].in_uop.bits.iq_type[1] connect slots_0.io.in_uop.bits.iq_type[2], issue_slots[0].in_uop.bits.iq_type[2] connect slots_0.io.in_uop.bits.iq_type[3], issue_slots[0].in_uop.bits.iq_type[3] connect slots_0.io.in_uop.bits.debug_pc, issue_slots[0].in_uop.bits.debug_pc connect slots_0.io.in_uop.bits.is_rvc, issue_slots[0].in_uop.bits.is_rvc connect slots_0.io.in_uop.bits.debug_inst, issue_slots[0].in_uop.bits.debug_inst connect slots_0.io.in_uop.bits.inst, issue_slots[0].in_uop.bits.inst connect slots_0.io.in_uop.valid, issue_slots[0].in_uop.valid connect issue_slots[0].iss_uop.debug_tsrc, slots_0.io.iss_uop.debug_tsrc connect issue_slots[0].iss_uop.debug_fsrc, slots_0.io.iss_uop.debug_fsrc connect issue_slots[0].iss_uop.bp_xcpt_if, slots_0.io.iss_uop.bp_xcpt_if connect issue_slots[0].iss_uop.bp_debug_if, slots_0.io.iss_uop.bp_debug_if connect issue_slots[0].iss_uop.xcpt_ma_if, slots_0.io.iss_uop.xcpt_ma_if connect issue_slots[0].iss_uop.xcpt_ae_if, slots_0.io.iss_uop.xcpt_ae_if connect issue_slots[0].iss_uop.xcpt_pf_if, slots_0.io.iss_uop.xcpt_pf_if connect issue_slots[0].iss_uop.fp_typ, slots_0.io.iss_uop.fp_typ connect issue_slots[0].iss_uop.fp_rm, slots_0.io.iss_uop.fp_rm connect issue_slots[0].iss_uop.fp_val, slots_0.io.iss_uop.fp_val connect issue_slots[0].iss_uop.fcn_op, slots_0.io.iss_uop.fcn_op connect issue_slots[0].iss_uop.fcn_dw, slots_0.io.iss_uop.fcn_dw connect issue_slots[0].iss_uop.frs3_en, slots_0.io.iss_uop.frs3_en connect issue_slots[0].iss_uop.lrs2_rtype, slots_0.io.iss_uop.lrs2_rtype connect issue_slots[0].iss_uop.lrs1_rtype, slots_0.io.iss_uop.lrs1_rtype connect issue_slots[0].iss_uop.dst_rtype, slots_0.io.iss_uop.dst_rtype connect issue_slots[0].iss_uop.lrs3, slots_0.io.iss_uop.lrs3 connect issue_slots[0].iss_uop.lrs2, slots_0.io.iss_uop.lrs2 connect issue_slots[0].iss_uop.lrs1, slots_0.io.iss_uop.lrs1 connect issue_slots[0].iss_uop.ldst, slots_0.io.iss_uop.ldst connect issue_slots[0].iss_uop.ldst_is_rs1, slots_0.io.iss_uop.ldst_is_rs1 connect issue_slots[0].iss_uop.csr_cmd, slots_0.io.iss_uop.csr_cmd connect issue_slots[0].iss_uop.flush_on_commit, slots_0.io.iss_uop.flush_on_commit connect issue_slots[0].iss_uop.is_unique, slots_0.io.iss_uop.is_unique connect issue_slots[0].iss_uop.uses_stq, slots_0.io.iss_uop.uses_stq connect issue_slots[0].iss_uop.uses_ldq, slots_0.io.iss_uop.uses_ldq connect issue_slots[0].iss_uop.mem_signed, slots_0.io.iss_uop.mem_signed connect issue_slots[0].iss_uop.mem_size, slots_0.io.iss_uop.mem_size connect issue_slots[0].iss_uop.mem_cmd, slots_0.io.iss_uop.mem_cmd connect issue_slots[0].iss_uop.exc_cause, slots_0.io.iss_uop.exc_cause connect issue_slots[0].iss_uop.exception, slots_0.io.iss_uop.exception connect issue_slots[0].iss_uop.stale_pdst, slots_0.io.iss_uop.stale_pdst connect issue_slots[0].iss_uop.ppred_busy, slots_0.io.iss_uop.ppred_busy connect issue_slots[0].iss_uop.prs3_busy, slots_0.io.iss_uop.prs3_busy connect issue_slots[0].iss_uop.prs2_busy, slots_0.io.iss_uop.prs2_busy connect issue_slots[0].iss_uop.prs1_busy, slots_0.io.iss_uop.prs1_busy connect issue_slots[0].iss_uop.ppred, slots_0.io.iss_uop.ppred connect issue_slots[0].iss_uop.prs3, slots_0.io.iss_uop.prs3 connect issue_slots[0].iss_uop.prs2, slots_0.io.iss_uop.prs2 connect issue_slots[0].iss_uop.prs1, slots_0.io.iss_uop.prs1 connect issue_slots[0].iss_uop.pdst, slots_0.io.iss_uop.pdst connect issue_slots[0].iss_uop.rxq_idx, slots_0.io.iss_uop.rxq_idx connect issue_slots[0].iss_uop.stq_idx, slots_0.io.iss_uop.stq_idx connect issue_slots[0].iss_uop.ldq_idx, slots_0.io.iss_uop.ldq_idx connect issue_slots[0].iss_uop.rob_idx, slots_0.io.iss_uop.rob_idx connect issue_slots[0].iss_uop.fp_ctrl.vec, slots_0.io.iss_uop.fp_ctrl.vec connect issue_slots[0].iss_uop.fp_ctrl.wflags, slots_0.io.iss_uop.fp_ctrl.wflags connect issue_slots[0].iss_uop.fp_ctrl.sqrt, slots_0.io.iss_uop.fp_ctrl.sqrt connect issue_slots[0].iss_uop.fp_ctrl.div, slots_0.io.iss_uop.fp_ctrl.div connect issue_slots[0].iss_uop.fp_ctrl.fma, slots_0.io.iss_uop.fp_ctrl.fma connect issue_slots[0].iss_uop.fp_ctrl.fastpipe, slots_0.io.iss_uop.fp_ctrl.fastpipe connect issue_slots[0].iss_uop.fp_ctrl.toint, slots_0.io.iss_uop.fp_ctrl.toint connect issue_slots[0].iss_uop.fp_ctrl.fromint, slots_0.io.iss_uop.fp_ctrl.fromint connect issue_slots[0].iss_uop.fp_ctrl.typeTagOut, slots_0.io.iss_uop.fp_ctrl.typeTagOut connect issue_slots[0].iss_uop.fp_ctrl.typeTagIn, slots_0.io.iss_uop.fp_ctrl.typeTagIn connect issue_slots[0].iss_uop.fp_ctrl.swap23, slots_0.io.iss_uop.fp_ctrl.swap23 connect issue_slots[0].iss_uop.fp_ctrl.swap12, slots_0.io.iss_uop.fp_ctrl.swap12 connect issue_slots[0].iss_uop.fp_ctrl.ren3, slots_0.io.iss_uop.fp_ctrl.ren3 connect issue_slots[0].iss_uop.fp_ctrl.ren2, slots_0.io.iss_uop.fp_ctrl.ren2 connect issue_slots[0].iss_uop.fp_ctrl.ren1, slots_0.io.iss_uop.fp_ctrl.ren1 connect issue_slots[0].iss_uop.fp_ctrl.wen, slots_0.io.iss_uop.fp_ctrl.wen connect issue_slots[0].iss_uop.fp_ctrl.ldst, slots_0.io.iss_uop.fp_ctrl.ldst connect issue_slots[0].iss_uop.op2_sel, slots_0.io.iss_uop.op2_sel connect issue_slots[0].iss_uop.op1_sel, slots_0.io.iss_uop.op1_sel connect issue_slots[0].iss_uop.imm_packed, slots_0.io.iss_uop.imm_packed connect issue_slots[0].iss_uop.pimm, slots_0.io.iss_uop.pimm connect issue_slots[0].iss_uop.imm_sel, slots_0.io.iss_uop.imm_sel connect issue_slots[0].iss_uop.imm_rename, slots_0.io.iss_uop.imm_rename connect issue_slots[0].iss_uop.taken, slots_0.io.iss_uop.taken connect issue_slots[0].iss_uop.pc_lob, slots_0.io.iss_uop.pc_lob connect issue_slots[0].iss_uop.edge_inst, slots_0.io.iss_uop.edge_inst connect issue_slots[0].iss_uop.ftq_idx, slots_0.io.iss_uop.ftq_idx connect issue_slots[0].iss_uop.is_mov, slots_0.io.iss_uop.is_mov connect issue_slots[0].iss_uop.is_rocc, slots_0.io.iss_uop.is_rocc connect issue_slots[0].iss_uop.is_sys_pc2epc, slots_0.io.iss_uop.is_sys_pc2epc connect issue_slots[0].iss_uop.is_eret, slots_0.io.iss_uop.is_eret connect issue_slots[0].iss_uop.is_amo, slots_0.io.iss_uop.is_amo connect issue_slots[0].iss_uop.is_sfence, slots_0.io.iss_uop.is_sfence connect issue_slots[0].iss_uop.is_fencei, slots_0.io.iss_uop.is_fencei connect issue_slots[0].iss_uop.is_fence, slots_0.io.iss_uop.is_fence connect issue_slots[0].iss_uop.is_sfb, slots_0.io.iss_uop.is_sfb connect issue_slots[0].iss_uop.br_type, slots_0.io.iss_uop.br_type connect issue_slots[0].iss_uop.br_tag, slots_0.io.iss_uop.br_tag connect issue_slots[0].iss_uop.br_mask, slots_0.io.iss_uop.br_mask connect issue_slots[0].iss_uop.dis_col_sel, slots_0.io.iss_uop.dis_col_sel connect issue_slots[0].iss_uop.iw_p3_bypass_hint, slots_0.io.iss_uop.iw_p3_bypass_hint connect issue_slots[0].iss_uop.iw_p2_bypass_hint, slots_0.io.iss_uop.iw_p2_bypass_hint connect issue_slots[0].iss_uop.iw_p1_bypass_hint, slots_0.io.iss_uop.iw_p1_bypass_hint connect issue_slots[0].iss_uop.iw_p2_speculative_child, slots_0.io.iss_uop.iw_p2_speculative_child connect issue_slots[0].iss_uop.iw_p1_speculative_child, slots_0.io.iss_uop.iw_p1_speculative_child connect issue_slots[0].iss_uop.iw_issued_partial_dgen, slots_0.io.iss_uop.iw_issued_partial_dgen connect issue_slots[0].iss_uop.iw_issued_partial_agen, slots_0.io.iss_uop.iw_issued_partial_agen connect issue_slots[0].iss_uop.iw_issued, slots_0.io.iss_uop.iw_issued connect issue_slots[0].iss_uop.fu_code[0], slots_0.io.iss_uop.fu_code[0] connect issue_slots[0].iss_uop.fu_code[1], slots_0.io.iss_uop.fu_code[1] connect issue_slots[0].iss_uop.fu_code[2], slots_0.io.iss_uop.fu_code[2] connect issue_slots[0].iss_uop.fu_code[3], slots_0.io.iss_uop.fu_code[3] connect issue_slots[0].iss_uop.fu_code[4], slots_0.io.iss_uop.fu_code[4] connect issue_slots[0].iss_uop.fu_code[5], slots_0.io.iss_uop.fu_code[5] connect issue_slots[0].iss_uop.fu_code[6], slots_0.io.iss_uop.fu_code[6] connect issue_slots[0].iss_uop.fu_code[7], slots_0.io.iss_uop.fu_code[7] connect issue_slots[0].iss_uop.fu_code[8], slots_0.io.iss_uop.fu_code[8] connect issue_slots[0].iss_uop.fu_code[9], slots_0.io.iss_uop.fu_code[9] connect issue_slots[0].iss_uop.iq_type[0], slots_0.io.iss_uop.iq_type[0] connect issue_slots[0].iss_uop.iq_type[1], slots_0.io.iss_uop.iq_type[1] connect issue_slots[0].iss_uop.iq_type[2], slots_0.io.iss_uop.iq_type[2] connect issue_slots[0].iss_uop.iq_type[3], slots_0.io.iss_uop.iq_type[3] connect issue_slots[0].iss_uop.debug_pc, slots_0.io.iss_uop.debug_pc connect issue_slots[0].iss_uop.is_rvc, slots_0.io.iss_uop.is_rvc connect issue_slots[0].iss_uop.debug_inst, slots_0.io.iss_uop.debug_inst connect issue_slots[0].iss_uop.inst, slots_0.io.iss_uop.inst connect slots_0.io.grant, issue_slots[0].grant connect issue_slots[0].request, slots_0.io.request connect issue_slots[0].will_be_valid, slots_0.io.will_be_valid connect issue_slots[0].valid, slots_0.io.valid connect slots_1.io.child_rebusys, issue_slots[1].child_rebusys connect slots_1.io.pred_wakeup_port.bits, issue_slots[1].pred_wakeup_port.bits connect slots_1.io.pred_wakeup_port.valid, issue_slots[1].pred_wakeup_port.valid connect slots_1.io.wakeup_ports[0].bits.rebusy, issue_slots[1].wakeup_ports[0].bits.rebusy connect slots_1.io.wakeup_ports[0].bits.speculative_mask, issue_slots[1].wakeup_ports[0].bits.speculative_mask connect slots_1.io.wakeup_ports[0].bits.bypassable, issue_slots[1].wakeup_ports[0].bits.bypassable connect slots_1.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[1].wakeup_ports[0].bits.uop.debug_tsrc connect slots_1.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[1].wakeup_ports[0].bits.uop.debug_fsrc connect slots_1.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[1].wakeup_ports[0].bits.uop.bp_xcpt_if connect slots_1.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[1].wakeup_ports[0].bits.uop.bp_debug_if connect slots_1.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[1].wakeup_ports[0].bits.uop.xcpt_ma_if connect slots_1.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[1].wakeup_ports[0].bits.uop.xcpt_ae_if connect slots_1.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[1].wakeup_ports[0].bits.uop.xcpt_pf_if connect slots_1.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[1].wakeup_ports[0].bits.uop.fp_typ connect slots_1.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[1].wakeup_ports[0].bits.uop.fp_rm connect slots_1.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[1].wakeup_ports[0].bits.uop.fp_val connect slots_1.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[1].wakeup_ports[0].bits.uop.fcn_op connect slots_1.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[1].wakeup_ports[0].bits.uop.fcn_dw connect slots_1.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[1].wakeup_ports[0].bits.uop.frs3_en connect slots_1.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[1].wakeup_ports[0].bits.uop.lrs2_rtype connect slots_1.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[1].wakeup_ports[0].bits.uop.lrs1_rtype connect slots_1.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[1].wakeup_ports[0].bits.uop.dst_rtype connect slots_1.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[1].wakeup_ports[0].bits.uop.lrs3 connect slots_1.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[1].wakeup_ports[0].bits.uop.lrs2 connect slots_1.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[1].wakeup_ports[0].bits.uop.lrs1 connect slots_1.io.wakeup_ports[0].bits.uop.ldst, issue_slots[1].wakeup_ports[0].bits.uop.ldst connect slots_1.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[1].wakeup_ports[0].bits.uop.ldst_is_rs1 connect slots_1.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[1].wakeup_ports[0].bits.uop.csr_cmd connect slots_1.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[1].wakeup_ports[0].bits.uop.flush_on_commit connect slots_1.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[1].wakeup_ports[0].bits.uop.is_unique connect slots_1.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[1].wakeup_ports[0].bits.uop.uses_stq connect slots_1.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[1].wakeup_ports[0].bits.uop.uses_ldq connect slots_1.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[1].wakeup_ports[0].bits.uop.mem_signed connect slots_1.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[1].wakeup_ports[0].bits.uop.mem_size connect slots_1.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[1].wakeup_ports[0].bits.uop.mem_cmd connect slots_1.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[1].wakeup_ports[0].bits.uop.exc_cause connect slots_1.io.wakeup_ports[0].bits.uop.exception, issue_slots[1].wakeup_ports[0].bits.uop.exception connect slots_1.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[1].wakeup_ports[0].bits.uop.stale_pdst connect slots_1.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[1].wakeup_ports[0].bits.uop.ppred_busy connect slots_1.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[1].wakeup_ports[0].bits.uop.prs3_busy connect slots_1.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[1].wakeup_ports[0].bits.uop.prs2_busy connect slots_1.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[1].wakeup_ports[0].bits.uop.prs1_busy connect slots_1.io.wakeup_ports[0].bits.uop.ppred, issue_slots[1].wakeup_ports[0].bits.uop.ppred connect slots_1.io.wakeup_ports[0].bits.uop.prs3, issue_slots[1].wakeup_ports[0].bits.uop.prs3 connect slots_1.io.wakeup_ports[0].bits.uop.prs2, issue_slots[1].wakeup_ports[0].bits.uop.prs2 connect slots_1.io.wakeup_ports[0].bits.uop.prs1, issue_slots[1].wakeup_ports[0].bits.uop.prs1 connect slots_1.io.wakeup_ports[0].bits.uop.pdst, issue_slots[1].wakeup_ports[0].bits.uop.pdst connect slots_1.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[1].wakeup_ports[0].bits.uop.rxq_idx connect slots_1.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[1].wakeup_ports[0].bits.uop.stq_idx connect slots_1.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[1].wakeup_ports[0].bits.uop.ldq_idx connect slots_1.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[1].wakeup_ports[0].bits.uop.rob_idx connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.vec connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.wflags connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.div connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.fma connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.toint connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.fromint connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.wen connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.ldst connect slots_1.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[1].wakeup_ports[0].bits.uop.op2_sel connect slots_1.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[1].wakeup_ports[0].bits.uop.op1_sel connect slots_1.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[1].wakeup_ports[0].bits.uop.imm_packed connect slots_1.io.wakeup_ports[0].bits.uop.pimm, issue_slots[1].wakeup_ports[0].bits.uop.pimm connect slots_1.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[1].wakeup_ports[0].bits.uop.imm_sel connect slots_1.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[1].wakeup_ports[0].bits.uop.imm_rename connect slots_1.io.wakeup_ports[0].bits.uop.taken, issue_slots[1].wakeup_ports[0].bits.uop.taken connect slots_1.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[1].wakeup_ports[0].bits.uop.pc_lob connect slots_1.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[1].wakeup_ports[0].bits.uop.edge_inst connect slots_1.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[1].wakeup_ports[0].bits.uop.ftq_idx connect slots_1.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[1].wakeup_ports[0].bits.uop.is_mov connect slots_1.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[1].wakeup_ports[0].bits.uop.is_rocc connect slots_1.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[1].wakeup_ports[0].bits.uop.is_sys_pc2epc connect slots_1.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[1].wakeup_ports[0].bits.uop.is_eret connect slots_1.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[1].wakeup_ports[0].bits.uop.is_amo connect slots_1.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[1].wakeup_ports[0].bits.uop.is_sfence connect slots_1.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[1].wakeup_ports[0].bits.uop.is_fencei connect slots_1.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[1].wakeup_ports[0].bits.uop.is_fence connect slots_1.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[1].wakeup_ports[0].bits.uop.is_sfb connect slots_1.io.wakeup_ports[0].bits.uop.br_type, issue_slots[1].wakeup_ports[0].bits.uop.br_type connect slots_1.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[1].wakeup_ports[0].bits.uop.br_tag connect slots_1.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[1].wakeup_ports[0].bits.uop.br_mask connect slots_1.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[1].wakeup_ports[0].bits.uop.dis_col_sel connect slots_1.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[1].wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect slots_1.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[1].wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect slots_1.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[1].wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect slots_1.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[1].wakeup_ports[0].bits.uop.iw_p2_speculative_child connect slots_1.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[1].wakeup_ports[0].bits.uop.iw_p1_speculative_child connect slots_1.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[1].wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect slots_1.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[1].wakeup_ports[0].bits.uop.iw_issued_partial_agen connect slots_1.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[1].wakeup_ports[0].bits.uop.iw_issued connect slots_1.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[1].wakeup_ports[0].bits.uop.fu_code[0] connect slots_1.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[1].wakeup_ports[0].bits.uop.fu_code[1] connect slots_1.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[1].wakeup_ports[0].bits.uop.fu_code[2] connect slots_1.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[1].wakeup_ports[0].bits.uop.fu_code[3] connect slots_1.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[1].wakeup_ports[0].bits.uop.fu_code[4] connect slots_1.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[1].wakeup_ports[0].bits.uop.fu_code[5] connect slots_1.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[1].wakeup_ports[0].bits.uop.fu_code[6] connect slots_1.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[1].wakeup_ports[0].bits.uop.fu_code[7] connect slots_1.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[1].wakeup_ports[0].bits.uop.fu_code[8] connect slots_1.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[1].wakeup_ports[0].bits.uop.fu_code[9] connect slots_1.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[1].wakeup_ports[0].bits.uop.iq_type[0] connect slots_1.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[1].wakeup_ports[0].bits.uop.iq_type[1] connect slots_1.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[1].wakeup_ports[0].bits.uop.iq_type[2] connect slots_1.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[1].wakeup_ports[0].bits.uop.iq_type[3] connect slots_1.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[1].wakeup_ports[0].bits.uop.debug_pc connect slots_1.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[1].wakeup_ports[0].bits.uop.is_rvc connect slots_1.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[1].wakeup_ports[0].bits.uop.debug_inst connect slots_1.io.wakeup_ports[0].bits.uop.inst, issue_slots[1].wakeup_ports[0].bits.uop.inst connect slots_1.io.wakeup_ports[0].valid, issue_slots[1].wakeup_ports[0].valid connect slots_1.io.wakeup_ports[1].bits.rebusy, issue_slots[1].wakeup_ports[1].bits.rebusy connect slots_1.io.wakeup_ports[1].bits.speculative_mask, issue_slots[1].wakeup_ports[1].bits.speculative_mask connect slots_1.io.wakeup_ports[1].bits.bypassable, issue_slots[1].wakeup_ports[1].bits.bypassable connect slots_1.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[1].wakeup_ports[1].bits.uop.debug_tsrc connect slots_1.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[1].wakeup_ports[1].bits.uop.debug_fsrc connect slots_1.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[1].wakeup_ports[1].bits.uop.bp_xcpt_if connect slots_1.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[1].wakeup_ports[1].bits.uop.bp_debug_if connect slots_1.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[1].wakeup_ports[1].bits.uop.xcpt_ma_if connect slots_1.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[1].wakeup_ports[1].bits.uop.xcpt_ae_if connect slots_1.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[1].wakeup_ports[1].bits.uop.xcpt_pf_if connect slots_1.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[1].wakeup_ports[1].bits.uop.fp_typ connect slots_1.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[1].wakeup_ports[1].bits.uop.fp_rm connect slots_1.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[1].wakeup_ports[1].bits.uop.fp_val connect slots_1.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[1].wakeup_ports[1].bits.uop.fcn_op connect slots_1.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[1].wakeup_ports[1].bits.uop.fcn_dw connect slots_1.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[1].wakeup_ports[1].bits.uop.frs3_en connect slots_1.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[1].wakeup_ports[1].bits.uop.lrs2_rtype connect slots_1.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[1].wakeup_ports[1].bits.uop.lrs1_rtype connect slots_1.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[1].wakeup_ports[1].bits.uop.dst_rtype connect slots_1.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[1].wakeup_ports[1].bits.uop.lrs3 connect slots_1.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[1].wakeup_ports[1].bits.uop.lrs2 connect slots_1.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[1].wakeup_ports[1].bits.uop.lrs1 connect slots_1.io.wakeup_ports[1].bits.uop.ldst, issue_slots[1].wakeup_ports[1].bits.uop.ldst connect slots_1.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[1].wakeup_ports[1].bits.uop.ldst_is_rs1 connect slots_1.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[1].wakeup_ports[1].bits.uop.csr_cmd connect slots_1.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[1].wakeup_ports[1].bits.uop.flush_on_commit connect slots_1.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[1].wakeup_ports[1].bits.uop.is_unique connect slots_1.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[1].wakeup_ports[1].bits.uop.uses_stq connect slots_1.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[1].wakeup_ports[1].bits.uop.uses_ldq connect slots_1.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[1].wakeup_ports[1].bits.uop.mem_signed connect slots_1.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[1].wakeup_ports[1].bits.uop.mem_size connect slots_1.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[1].wakeup_ports[1].bits.uop.mem_cmd connect slots_1.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[1].wakeup_ports[1].bits.uop.exc_cause connect slots_1.io.wakeup_ports[1].bits.uop.exception, issue_slots[1].wakeup_ports[1].bits.uop.exception connect slots_1.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[1].wakeup_ports[1].bits.uop.stale_pdst connect slots_1.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[1].wakeup_ports[1].bits.uop.ppred_busy connect slots_1.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[1].wakeup_ports[1].bits.uop.prs3_busy connect slots_1.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[1].wakeup_ports[1].bits.uop.prs2_busy connect slots_1.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[1].wakeup_ports[1].bits.uop.prs1_busy connect slots_1.io.wakeup_ports[1].bits.uop.ppred, issue_slots[1].wakeup_ports[1].bits.uop.ppred connect slots_1.io.wakeup_ports[1].bits.uop.prs3, issue_slots[1].wakeup_ports[1].bits.uop.prs3 connect slots_1.io.wakeup_ports[1].bits.uop.prs2, issue_slots[1].wakeup_ports[1].bits.uop.prs2 connect slots_1.io.wakeup_ports[1].bits.uop.prs1, issue_slots[1].wakeup_ports[1].bits.uop.prs1 connect slots_1.io.wakeup_ports[1].bits.uop.pdst, issue_slots[1].wakeup_ports[1].bits.uop.pdst connect slots_1.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[1].wakeup_ports[1].bits.uop.rxq_idx connect slots_1.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[1].wakeup_ports[1].bits.uop.stq_idx connect slots_1.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[1].wakeup_ports[1].bits.uop.ldq_idx connect slots_1.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[1].wakeup_ports[1].bits.uop.rob_idx connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.vec connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.wflags connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.div connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.fma connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.toint connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.fromint connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.wen connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.ldst connect slots_1.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[1].wakeup_ports[1].bits.uop.op2_sel connect slots_1.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[1].wakeup_ports[1].bits.uop.op1_sel connect slots_1.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[1].wakeup_ports[1].bits.uop.imm_packed connect slots_1.io.wakeup_ports[1].bits.uop.pimm, issue_slots[1].wakeup_ports[1].bits.uop.pimm connect slots_1.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[1].wakeup_ports[1].bits.uop.imm_sel connect slots_1.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[1].wakeup_ports[1].bits.uop.imm_rename connect slots_1.io.wakeup_ports[1].bits.uop.taken, issue_slots[1].wakeup_ports[1].bits.uop.taken connect slots_1.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[1].wakeup_ports[1].bits.uop.pc_lob connect slots_1.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[1].wakeup_ports[1].bits.uop.edge_inst connect slots_1.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[1].wakeup_ports[1].bits.uop.ftq_idx connect slots_1.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[1].wakeup_ports[1].bits.uop.is_mov connect slots_1.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[1].wakeup_ports[1].bits.uop.is_rocc connect slots_1.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[1].wakeup_ports[1].bits.uop.is_sys_pc2epc connect slots_1.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[1].wakeup_ports[1].bits.uop.is_eret connect slots_1.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[1].wakeup_ports[1].bits.uop.is_amo connect slots_1.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[1].wakeup_ports[1].bits.uop.is_sfence connect slots_1.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[1].wakeup_ports[1].bits.uop.is_fencei connect slots_1.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[1].wakeup_ports[1].bits.uop.is_fence connect slots_1.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[1].wakeup_ports[1].bits.uop.is_sfb connect slots_1.io.wakeup_ports[1].bits.uop.br_type, issue_slots[1].wakeup_ports[1].bits.uop.br_type connect slots_1.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[1].wakeup_ports[1].bits.uop.br_tag connect slots_1.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[1].wakeup_ports[1].bits.uop.br_mask connect slots_1.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[1].wakeup_ports[1].bits.uop.dis_col_sel connect slots_1.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[1].wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect slots_1.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[1].wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect slots_1.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[1].wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect slots_1.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[1].wakeup_ports[1].bits.uop.iw_p2_speculative_child connect slots_1.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[1].wakeup_ports[1].bits.uop.iw_p1_speculative_child connect slots_1.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[1].wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect slots_1.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[1].wakeup_ports[1].bits.uop.iw_issued_partial_agen connect slots_1.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[1].wakeup_ports[1].bits.uop.iw_issued connect slots_1.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[1].wakeup_ports[1].bits.uop.fu_code[0] connect slots_1.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[1].wakeup_ports[1].bits.uop.fu_code[1] connect slots_1.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[1].wakeup_ports[1].bits.uop.fu_code[2] connect slots_1.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[1].wakeup_ports[1].bits.uop.fu_code[3] connect slots_1.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[1].wakeup_ports[1].bits.uop.fu_code[4] connect slots_1.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[1].wakeup_ports[1].bits.uop.fu_code[5] connect slots_1.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[1].wakeup_ports[1].bits.uop.fu_code[6] connect slots_1.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[1].wakeup_ports[1].bits.uop.fu_code[7] connect slots_1.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[1].wakeup_ports[1].bits.uop.fu_code[8] connect slots_1.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[1].wakeup_ports[1].bits.uop.fu_code[9] connect slots_1.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[1].wakeup_ports[1].bits.uop.iq_type[0] connect slots_1.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[1].wakeup_ports[1].bits.uop.iq_type[1] connect slots_1.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[1].wakeup_ports[1].bits.uop.iq_type[2] connect slots_1.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[1].wakeup_ports[1].bits.uop.iq_type[3] connect slots_1.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[1].wakeup_ports[1].bits.uop.debug_pc connect slots_1.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[1].wakeup_ports[1].bits.uop.is_rvc connect slots_1.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[1].wakeup_ports[1].bits.uop.debug_inst connect slots_1.io.wakeup_ports[1].bits.uop.inst, issue_slots[1].wakeup_ports[1].bits.uop.inst connect slots_1.io.wakeup_ports[1].valid, issue_slots[1].wakeup_ports[1].valid connect slots_1.io.wakeup_ports[2].bits.rebusy, issue_slots[1].wakeup_ports[2].bits.rebusy connect slots_1.io.wakeup_ports[2].bits.speculative_mask, issue_slots[1].wakeup_ports[2].bits.speculative_mask connect slots_1.io.wakeup_ports[2].bits.bypassable, issue_slots[1].wakeup_ports[2].bits.bypassable connect slots_1.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[1].wakeup_ports[2].bits.uop.debug_tsrc connect slots_1.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[1].wakeup_ports[2].bits.uop.debug_fsrc connect slots_1.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[1].wakeup_ports[2].bits.uop.bp_xcpt_if connect slots_1.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[1].wakeup_ports[2].bits.uop.bp_debug_if connect slots_1.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[1].wakeup_ports[2].bits.uop.xcpt_ma_if connect slots_1.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[1].wakeup_ports[2].bits.uop.xcpt_ae_if connect slots_1.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[1].wakeup_ports[2].bits.uop.xcpt_pf_if connect slots_1.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[1].wakeup_ports[2].bits.uop.fp_typ connect slots_1.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[1].wakeup_ports[2].bits.uop.fp_rm connect slots_1.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[1].wakeup_ports[2].bits.uop.fp_val connect slots_1.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[1].wakeup_ports[2].bits.uop.fcn_op connect slots_1.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[1].wakeup_ports[2].bits.uop.fcn_dw connect slots_1.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[1].wakeup_ports[2].bits.uop.frs3_en connect slots_1.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[1].wakeup_ports[2].bits.uop.lrs2_rtype connect slots_1.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[1].wakeup_ports[2].bits.uop.lrs1_rtype connect slots_1.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[1].wakeup_ports[2].bits.uop.dst_rtype connect slots_1.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[1].wakeup_ports[2].bits.uop.lrs3 connect slots_1.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[1].wakeup_ports[2].bits.uop.lrs2 connect slots_1.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[1].wakeup_ports[2].bits.uop.lrs1 connect slots_1.io.wakeup_ports[2].bits.uop.ldst, issue_slots[1].wakeup_ports[2].bits.uop.ldst connect slots_1.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[1].wakeup_ports[2].bits.uop.ldst_is_rs1 connect slots_1.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[1].wakeup_ports[2].bits.uop.csr_cmd connect slots_1.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[1].wakeup_ports[2].bits.uop.flush_on_commit connect slots_1.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[1].wakeup_ports[2].bits.uop.is_unique connect slots_1.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[1].wakeup_ports[2].bits.uop.uses_stq connect slots_1.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[1].wakeup_ports[2].bits.uop.uses_ldq connect slots_1.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[1].wakeup_ports[2].bits.uop.mem_signed connect slots_1.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[1].wakeup_ports[2].bits.uop.mem_size connect slots_1.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[1].wakeup_ports[2].bits.uop.mem_cmd connect slots_1.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[1].wakeup_ports[2].bits.uop.exc_cause connect slots_1.io.wakeup_ports[2].bits.uop.exception, issue_slots[1].wakeup_ports[2].bits.uop.exception connect slots_1.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[1].wakeup_ports[2].bits.uop.stale_pdst connect slots_1.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[1].wakeup_ports[2].bits.uop.ppred_busy connect slots_1.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[1].wakeup_ports[2].bits.uop.prs3_busy connect slots_1.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[1].wakeup_ports[2].bits.uop.prs2_busy connect slots_1.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[1].wakeup_ports[2].bits.uop.prs1_busy connect slots_1.io.wakeup_ports[2].bits.uop.ppred, issue_slots[1].wakeup_ports[2].bits.uop.ppred connect slots_1.io.wakeup_ports[2].bits.uop.prs3, issue_slots[1].wakeup_ports[2].bits.uop.prs3 connect slots_1.io.wakeup_ports[2].bits.uop.prs2, issue_slots[1].wakeup_ports[2].bits.uop.prs2 connect slots_1.io.wakeup_ports[2].bits.uop.prs1, issue_slots[1].wakeup_ports[2].bits.uop.prs1 connect slots_1.io.wakeup_ports[2].bits.uop.pdst, issue_slots[1].wakeup_ports[2].bits.uop.pdst connect slots_1.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[1].wakeup_ports[2].bits.uop.rxq_idx connect slots_1.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[1].wakeup_ports[2].bits.uop.stq_idx connect slots_1.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[1].wakeup_ports[2].bits.uop.ldq_idx connect slots_1.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[1].wakeup_ports[2].bits.uop.rob_idx connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.vec connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.wflags connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.div connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.fma connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.toint connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.fromint connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.wen connect slots_1.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.ldst connect slots_1.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[1].wakeup_ports[2].bits.uop.op2_sel connect slots_1.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[1].wakeup_ports[2].bits.uop.op1_sel connect slots_1.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[1].wakeup_ports[2].bits.uop.imm_packed connect slots_1.io.wakeup_ports[2].bits.uop.pimm, issue_slots[1].wakeup_ports[2].bits.uop.pimm connect slots_1.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[1].wakeup_ports[2].bits.uop.imm_sel connect slots_1.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[1].wakeup_ports[2].bits.uop.imm_rename connect slots_1.io.wakeup_ports[2].bits.uop.taken, issue_slots[1].wakeup_ports[2].bits.uop.taken connect slots_1.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[1].wakeup_ports[2].bits.uop.pc_lob connect slots_1.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[1].wakeup_ports[2].bits.uop.edge_inst connect slots_1.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[1].wakeup_ports[2].bits.uop.ftq_idx connect slots_1.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[1].wakeup_ports[2].bits.uop.is_mov connect slots_1.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[1].wakeup_ports[2].bits.uop.is_rocc connect slots_1.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[1].wakeup_ports[2].bits.uop.is_sys_pc2epc connect slots_1.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[1].wakeup_ports[2].bits.uop.is_eret connect slots_1.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[1].wakeup_ports[2].bits.uop.is_amo connect slots_1.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[1].wakeup_ports[2].bits.uop.is_sfence connect slots_1.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[1].wakeup_ports[2].bits.uop.is_fencei connect slots_1.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[1].wakeup_ports[2].bits.uop.is_fence connect slots_1.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[1].wakeup_ports[2].bits.uop.is_sfb connect slots_1.io.wakeup_ports[2].bits.uop.br_type, issue_slots[1].wakeup_ports[2].bits.uop.br_type connect slots_1.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[1].wakeup_ports[2].bits.uop.br_tag connect slots_1.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[1].wakeup_ports[2].bits.uop.br_mask connect slots_1.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[1].wakeup_ports[2].bits.uop.dis_col_sel connect slots_1.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[1].wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect slots_1.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[1].wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect slots_1.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[1].wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect slots_1.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[1].wakeup_ports[2].bits.uop.iw_p2_speculative_child connect slots_1.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[1].wakeup_ports[2].bits.uop.iw_p1_speculative_child connect slots_1.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[1].wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect slots_1.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[1].wakeup_ports[2].bits.uop.iw_issued_partial_agen connect slots_1.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[1].wakeup_ports[2].bits.uop.iw_issued connect slots_1.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[1].wakeup_ports[2].bits.uop.fu_code[0] connect slots_1.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[1].wakeup_ports[2].bits.uop.fu_code[1] connect slots_1.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[1].wakeup_ports[2].bits.uop.fu_code[2] connect slots_1.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[1].wakeup_ports[2].bits.uop.fu_code[3] connect slots_1.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[1].wakeup_ports[2].bits.uop.fu_code[4] connect slots_1.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[1].wakeup_ports[2].bits.uop.fu_code[5] connect slots_1.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[1].wakeup_ports[2].bits.uop.fu_code[6] connect slots_1.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[1].wakeup_ports[2].bits.uop.fu_code[7] connect slots_1.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[1].wakeup_ports[2].bits.uop.fu_code[8] connect slots_1.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[1].wakeup_ports[2].bits.uop.fu_code[9] connect slots_1.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[1].wakeup_ports[2].bits.uop.iq_type[0] connect slots_1.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[1].wakeup_ports[2].bits.uop.iq_type[1] connect slots_1.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[1].wakeup_ports[2].bits.uop.iq_type[2] connect slots_1.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[1].wakeup_ports[2].bits.uop.iq_type[3] connect slots_1.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[1].wakeup_ports[2].bits.uop.debug_pc connect slots_1.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[1].wakeup_ports[2].bits.uop.is_rvc connect slots_1.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[1].wakeup_ports[2].bits.uop.debug_inst connect slots_1.io.wakeup_ports[2].bits.uop.inst, issue_slots[1].wakeup_ports[2].bits.uop.inst connect slots_1.io.wakeup_ports[2].valid, issue_slots[1].wakeup_ports[2].valid connect slots_1.io.wakeup_ports[3].bits.rebusy, issue_slots[1].wakeup_ports[3].bits.rebusy connect slots_1.io.wakeup_ports[3].bits.speculative_mask, issue_slots[1].wakeup_ports[3].bits.speculative_mask connect slots_1.io.wakeup_ports[3].bits.bypassable, issue_slots[1].wakeup_ports[3].bits.bypassable connect slots_1.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[1].wakeup_ports[3].bits.uop.debug_tsrc connect slots_1.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[1].wakeup_ports[3].bits.uop.debug_fsrc connect slots_1.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[1].wakeup_ports[3].bits.uop.bp_xcpt_if connect slots_1.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[1].wakeup_ports[3].bits.uop.bp_debug_if connect slots_1.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[1].wakeup_ports[3].bits.uop.xcpt_ma_if connect slots_1.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[1].wakeup_ports[3].bits.uop.xcpt_ae_if connect slots_1.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[1].wakeup_ports[3].bits.uop.xcpt_pf_if connect slots_1.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[1].wakeup_ports[3].bits.uop.fp_typ connect slots_1.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[1].wakeup_ports[3].bits.uop.fp_rm connect slots_1.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[1].wakeup_ports[3].bits.uop.fp_val connect slots_1.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[1].wakeup_ports[3].bits.uop.fcn_op connect slots_1.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[1].wakeup_ports[3].bits.uop.fcn_dw connect slots_1.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[1].wakeup_ports[3].bits.uop.frs3_en connect slots_1.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[1].wakeup_ports[3].bits.uop.lrs2_rtype connect slots_1.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[1].wakeup_ports[3].bits.uop.lrs1_rtype connect slots_1.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[1].wakeup_ports[3].bits.uop.dst_rtype connect slots_1.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[1].wakeup_ports[3].bits.uop.lrs3 connect slots_1.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[1].wakeup_ports[3].bits.uop.lrs2 connect slots_1.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[1].wakeup_ports[3].bits.uop.lrs1 connect slots_1.io.wakeup_ports[3].bits.uop.ldst, issue_slots[1].wakeup_ports[3].bits.uop.ldst connect slots_1.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[1].wakeup_ports[3].bits.uop.ldst_is_rs1 connect slots_1.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[1].wakeup_ports[3].bits.uop.csr_cmd connect slots_1.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[1].wakeup_ports[3].bits.uop.flush_on_commit connect slots_1.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[1].wakeup_ports[3].bits.uop.is_unique connect slots_1.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[1].wakeup_ports[3].bits.uop.uses_stq connect slots_1.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[1].wakeup_ports[3].bits.uop.uses_ldq connect slots_1.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[1].wakeup_ports[3].bits.uop.mem_signed connect slots_1.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[1].wakeup_ports[3].bits.uop.mem_size connect slots_1.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[1].wakeup_ports[3].bits.uop.mem_cmd connect slots_1.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[1].wakeup_ports[3].bits.uop.exc_cause connect slots_1.io.wakeup_ports[3].bits.uop.exception, issue_slots[1].wakeup_ports[3].bits.uop.exception connect slots_1.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[1].wakeup_ports[3].bits.uop.stale_pdst connect slots_1.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[1].wakeup_ports[3].bits.uop.ppred_busy connect slots_1.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[1].wakeup_ports[3].bits.uop.prs3_busy connect slots_1.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[1].wakeup_ports[3].bits.uop.prs2_busy connect slots_1.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[1].wakeup_ports[3].bits.uop.prs1_busy connect slots_1.io.wakeup_ports[3].bits.uop.ppred, issue_slots[1].wakeup_ports[3].bits.uop.ppred connect slots_1.io.wakeup_ports[3].bits.uop.prs3, issue_slots[1].wakeup_ports[3].bits.uop.prs3 connect slots_1.io.wakeup_ports[3].bits.uop.prs2, issue_slots[1].wakeup_ports[3].bits.uop.prs2 connect slots_1.io.wakeup_ports[3].bits.uop.prs1, issue_slots[1].wakeup_ports[3].bits.uop.prs1 connect slots_1.io.wakeup_ports[3].bits.uop.pdst, issue_slots[1].wakeup_ports[3].bits.uop.pdst connect slots_1.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[1].wakeup_ports[3].bits.uop.rxq_idx connect slots_1.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[1].wakeup_ports[3].bits.uop.stq_idx connect slots_1.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[1].wakeup_ports[3].bits.uop.ldq_idx connect slots_1.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[1].wakeup_ports[3].bits.uop.rob_idx connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.vec connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.wflags connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.div connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.fma connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.toint connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.fromint connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.wen connect slots_1.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.ldst connect slots_1.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[1].wakeup_ports[3].bits.uop.op2_sel connect slots_1.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[1].wakeup_ports[3].bits.uop.op1_sel connect slots_1.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[1].wakeup_ports[3].bits.uop.imm_packed connect slots_1.io.wakeup_ports[3].bits.uop.pimm, issue_slots[1].wakeup_ports[3].bits.uop.pimm connect slots_1.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[1].wakeup_ports[3].bits.uop.imm_sel connect slots_1.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[1].wakeup_ports[3].bits.uop.imm_rename connect slots_1.io.wakeup_ports[3].bits.uop.taken, issue_slots[1].wakeup_ports[3].bits.uop.taken connect slots_1.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[1].wakeup_ports[3].bits.uop.pc_lob connect slots_1.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[1].wakeup_ports[3].bits.uop.edge_inst connect slots_1.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[1].wakeup_ports[3].bits.uop.ftq_idx connect slots_1.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[1].wakeup_ports[3].bits.uop.is_mov connect slots_1.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[1].wakeup_ports[3].bits.uop.is_rocc connect slots_1.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[1].wakeup_ports[3].bits.uop.is_sys_pc2epc connect slots_1.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[1].wakeup_ports[3].bits.uop.is_eret connect slots_1.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[1].wakeup_ports[3].bits.uop.is_amo connect slots_1.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[1].wakeup_ports[3].bits.uop.is_sfence connect slots_1.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[1].wakeup_ports[3].bits.uop.is_fencei connect slots_1.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[1].wakeup_ports[3].bits.uop.is_fence connect slots_1.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[1].wakeup_ports[3].bits.uop.is_sfb connect slots_1.io.wakeup_ports[3].bits.uop.br_type, issue_slots[1].wakeup_ports[3].bits.uop.br_type connect slots_1.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[1].wakeup_ports[3].bits.uop.br_tag connect slots_1.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[1].wakeup_ports[3].bits.uop.br_mask connect slots_1.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[1].wakeup_ports[3].bits.uop.dis_col_sel connect slots_1.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[1].wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect slots_1.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[1].wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect slots_1.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[1].wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect slots_1.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[1].wakeup_ports[3].bits.uop.iw_p2_speculative_child connect slots_1.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[1].wakeup_ports[3].bits.uop.iw_p1_speculative_child connect slots_1.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[1].wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect slots_1.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[1].wakeup_ports[3].bits.uop.iw_issued_partial_agen connect slots_1.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[1].wakeup_ports[3].bits.uop.iw_issued connect slots_1.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[1].wakeup_ports[3].bits.uop.fu_code[0] connect slots_1.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[1].wakeup_ports[3].bits.uop.fu_code[1] connect slots_1.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[1].wakeup_ports[3].bits.uop.fu_code[2] connect slots_1.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[1].wakeup_ports[3].bits.uop.fu_code[3] connect slots_1.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[1].wakeup_ports[3].bits.uop.fu_code[4] connect slots_1.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[1].wakeup_ports[3].bits.uop.fu_code[5] connect slots_1.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[1].wakeup_ports[3].bits.uop.fu_code[6] connect slots_1.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[1].wakeup_ports[3].bits.uop.fu_code[7] connect slots_1.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[1].wakeup_ports[3].bits.uop.fu_code[8] connect slots_1.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[1].wakeup_ports[3].bits.uop.fu_code[9] connect slots_1.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[1].wakeup_ports[3].bits.uop.iq_type[0] connect slots_1.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[1].wakeup_ports[3].bits.uop.iq_type[1] connect slots_1.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[1].wakeup_ports[3].bits.uop.iq_type[2] connect slots_1.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[1].wakeup_ports[3].bits.uop.iq_type[3] connect slots_1.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[1].wakeup_ports[3].bits.uop.debug_pc connect slots_1.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[1].wakeup_ports[3].bits.uop.is_rvc connect slots_1.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[1].wakeup_ports[3].bits.uop.debug_inst connect slots_1.io.wakeup_ports[3].bits.uop.inst, issue_slots[1].wakeup_ports[3].bits.uop.inst connect slots_1.io.wakeup_ports[3].valid, issue_slots[1].wakeup_ports[3].valid connect slots_1.io.wakeup_ports[4].bits.rebusy, issue_slots[1].wakeup_ports[4].bits.rebusy connect slots_1.io.wakeup_ports[4].bits.speculative_mask, issue_slots[1].wakeup_ports[4].bits.speculative_mask connect slots_1.io.wakeup_ports[4].bits.bypassable, issue_slots[1].wakeup_ports[4].bits.bypassable connect slots_1.io.wakeup_ports[4].bits.uop.debug_tsrc, issue_slots[1].wakeup_ports[4].bits.uop.debug_tsrc connect slots_1.io.wakeup_ports[4].bits.uop.debug_fsrc, issue_slots[1].wakeup_ports[4].bits.uop.debug_fsrc connect slots_1.io.wakeup_ports[4].bits.uop.bp_xcpt_if, issue_slots[1].wakeup_ports[4].bits.uop.bp_xcpt_if connect slots_1.io.wakeup_ports[4].bits.uop.bp_debug_if, issue_slots[1].wakeup_ports[4].bits.uop.bp_debug_if connect slots_1.io.wakeup_ports[4].bits.uop.xcpt_ma_if, issue_slots[1].wakeup_ports[4].bits.uop.xcpt_ma_if connect slots_1.io.wakeup_ports[4].bits.uop.xcpt_ae_if, issue_slots[1].wakeup_ports[4].bits.uop.xcpt_ae_if connect slots_1.io.wakeup_ports[4].bits.uop.xcpt_pf_if, issue_slots[1].wakeup_ports[4].bits.uop.xcpt_pf_if connect slots_1.io.wakeup_ports[4].bits.uop.fp_typ, issue_slots[1].wakeup_ports[4].bits.uop.fp_typ connect slots_1.io.wakeup_ports[4].bits.uop.fp_rm, issue_slots[1].wakeup_ports[4].bits.uop.fp_rm connect slots_1.io.wakeup_ports[4].bits.uop.fp_val, issue_slots[1].wakeup_ports[4].bits.uop.fp_val connect slots_1.io.wakeup_ports[4].bits.uop.fcn_op, issue_slots[1].wakeup_ports[4].bits.uop.fcn_op connect slots_1.io.wakeup_ports[4].bits.uop.fcn_dw, issue_slots[1].wakeup_ports[4].bits.uop.fcn_dw connect slots_1.io.wakeup_ports[4].bits.uop.frs3_en, issue_slots[1].wakeup_ports[4].bits.uop.frs3_en connect slots_1.io.wakeup_ports[4].bits.uop.lrs2_rtype, issue_slots[1].wakeup_ports[4].bits.uop.lrs2_rtype connect slots_1.io.wakeup_ports[4].bits.uop.lrs1_rtype, issue_slots[1].wakeup_ports[4].bits.uop.lrs1_rtype connect slots_1.io.wakeup_ports[4].bits.uop.dst_rtype, issue_slots[1].wakeup_ports[4].bits.uop.dst_rtype connect slots_1.io.wakeup_ports[4].bits.uop.lrs3, issue_slots[1].wakeup_ports[4].bits.uop.lrs3 connect slots_1.io.wakeup_ports[4].bits.uop.lrs2, issue_slots[1].wakeup_ports[4].bits.uop.lrs2 connect slots_1.io.wakeup_ports[4].bits.uop.lrs1, issue_slots[1].wakeup_ports[4].bits.uop.lrs1 connect slots_1.io.wakeup_ports[4].bits.uop.ldst, issue_slots[1].wakeup_ports[4].bits.uop.ldst connect slots_1.io.wakeup_ports[4].bits.uop.ldst_is_rs1, issue_slots[1].wakeup_ports[4].bits.uop.ldst_is_rs1 connect slots_1.io.wakeup_ports[4].bits.uop.csr_cmd, issue_slots[1].wakeup_ports[4].bits.uop.csr_cmd connect slots_1.io.wakeup_ports[4].bits.uop.flush_on_commit, issue_slots[1].wakeup_ports[4].bits.uop.flush_on_commit connect slots_1.io.wakeup_ports[4].bits.uop.is_unique, issue_slots[1].wakeup_ports[4].bits.uop.is_unique connect slots_1.io.wakeup_ports[4].bits.uop.uses_stq, issue_slots[1].wakeup_ports[4].bits.uop.uses_stq connect slots_1.io.wakeup_ports[4].bits.uop.uses_ldq, issue_slots[1].wakeup_ports[4].bits.uop.uses_ldq connect slots_1.io.wakeup_ports[4].bits.uop.mem_signed, issue_slots[1].wakeup_ports[4].bits.uop.mem_signed connect slots_1.io.wakeup_ports[4].bits.uop.mem_size, issue_slots[1].wakeup_ports[4].bits.uop.mem_size connect slots_1.io.wakeup_ports[4].bits.uop.mem_cmd, issue_slots[1].wakeup_ports[4].bits.uop.mem_cmd connect slots_1.io.wakeup_ports[4].bits.uop.exc_cause, issue_slots[1].wakeup_ports[4].bits.uop.exc_cause connect slots_1.io.wakeup_ports[4].bits.uop.exception, issue_slots[1].wakeup_ports[4].bits.uop.exception connect slots_1.io.wakeup_ports[4].bits.uop.stale_pdst, issue_slots[1].wakeup_ports[4].bits.uop.stale_pdst connect slots_1.io.wakeup_ports[4].bits.uop.ppred_busy, issue_slots[1].wakeup_ports[4].bits.uop.ppred_busy connect slots_1.io.wakeup_ports[4].bits.uop.prs3_busy, issue_slots[1].wakeup_ports[4].bits.uop.prs3_busy connect slots_1.io.wakeup_ports[4].bits.uop.prs2_busy, issue_slots[1].wakeup_ports[4].bits.uop.prs2_busy connect slots_1.io.wakeup_ports[4].bits.uop.prs1_busy, issue_slots[1].wakeup_ports[4].bits.uop.prs1_busy connect slots_1.io.wakeup_ports[4].bits.uop.ppred, issue_slots[1].wakeup_ports[4].bits.uop.ppred connect slots_1.io.wakeup_ports[4].bits.uop.prs3, issue_slots[1].wakeup_ports[4].bits.uop.prs3 connect slots_1.io.wakeup_ports[4].bits.uop.prs2, issue_slots[1].wakeup_ports[4].bits.uop.prs2 connect slots_1.io.wakeup_ports[4].bits.uop.prs1, issue_slots[1].wakeup_ports[4].bits.uop.prs1 connect slots_1.io.wakeup_ports[4].bits.uop.pdst, issue_slots[1].wakeup_ports[4].bits.uop.pdst connect slots_1.io.wakeup_ports[4].bits.uop.rxq_idx, issue_slots[1].wakeup_ports[4].bits.uop.rxq_idx connect slots_1.io.wakeup_ports[4].bits.uop.stq_idx, issue_slots[1].wakeup_ports[4].bits.uop.stq_idx connect slots_1.io.wakeup_ports[4].bits.uop.ldq_idx, issue_slots[1].wakeup_ports[4].bits.uop.ldq_idx connect slots_1.io.wakeup_ports[4].bits.uop.rob_idx, issue_slots[1].wakeup_ports[4].bits.uop.rob_idx connect slots_1.io.wakeup_ports[4].bits.uop.fp_ctrl.vec, issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.vec connect slots_1.io.wakeup_ports[4].bits.uop.fp_ctrl.wflags, issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.wflags connect slots_1.io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt, issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect slots_1.io.wakeup_ports[4].bits.uop.fp_ctrl.div, issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.div connect slots_1.io.wakeup_ports[4].bits.uop.fp_ctrl.fma, issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.fma connect slots_1.io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect slots_1.io.wakeup_ports[4].bits.uop.fp_ctrl.toint, issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.toint connect slots_1.io.wakeup_ports[4].bits.uop.fp_ctrl.fromint, issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.fromint connect slots_1.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect slots_1.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect slots_1.io.wakeup_ports[4].bits.uop.fp_ctrl.swap23, issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect slots_1.io.wakeup_ports[4].bits.uop.fp_ctrl.swap12, issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect slots_1.io.wakeup_ports[4].bits.uop.fp_ctrl.ren3, issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect slots_1.io.wakeup_ports[4].bits.uop.fp_ctrl.ren2, issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect slots_1.io.wakeup_ports[4].bits.uop.fp_ctrl.ren1, issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect slots_1.io.wakeup_ports[4].bits.uop.fp_ctrl.wen, issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.wen connect slots_1.io.wakeup_ports[4].bits.uop.fp_ctrl.ldst, issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.ldst connect slots_1.io.wakeup_ports[4].bits.uop.op2_sel, issue_slots[1].wakeup_ports[4].bits.uop.op2_sel connect slots_1.io.wakeup_ports[4].bits.uop.op1_sel, issue_slots[1].wakeup_ports[4].bits.uop.op1_sel connect slots_1.io.wakeup_ports[4].bits.uop.imm_packed, issue_slots[1].wakeup_ports[4].bits.uop.imm_packed connect slots_1.io.wakeup_ports[4].bits.uop.pimm, issue_slots[1].wakeup_ports[4].bits.uop.pimm connect slots_1.io.wakeup_ports[4].bits.uop.imm_sel, issue_slots[1].wakeup_ports[4].bits.uop.imm_sel connect slots_1.io.wakeup_ports[4].bits.uop.imm_rename, issue_slots[1].wakeup_ports[4].bits.uop.imm_rename connect slots_1.io.wakeup_ports[4].bits.uop.taken, issue_slots[1].wakeup_ports[4].bits.uop.taken connect slots_1.io.wakeup_ports[4].bits.uop.pc_lob, issue_slots[1].wakeup_ports[4].bits.uop.pc_lob connect slots_1.io.wakeup_ports[4].bits.uop.edge_inst, issue_slots[1].wakeup_ports[4].bits.uop.edge_inst connect slots_1.io.wakeup_ports[4].bits.uop.ftq_idx, issue_slots[1].wakeup_ports[4].bits.uop.ftq_idx connect slots_1.io.wakeup_ports[4].bits.uop.is_mov, issue_slots[1].wakeup_ports[4].bits.uop.is_mov connect slots_1.io.wakeup_ports[4].bits.uop.is_rocc, issue_slots[1].wakeup_ports[4].bits.uop.is_rocc connect slots_1.io.wakeup_ports[4].bits.uop.is_sys_pc2epc, issue_slots[1].wakeup_ports[4].bits.uop.is_sys_pc2epc connect slots_1.io.wakeup_ports[4].bits.uop.is_eret, issue_slots[1].wakeup_ports[4].bits.uop.is_eret connect slots_1.io.wakeup_ports[4].bits.uop.is_amo, issue_slots[1].wakeup_ports[4].bits.uop.is_amo connect slots_1.io.wakeup_ports[4].bits.uop.is_sfence, issue_slots[1].wakeup_ports[4].bits.uop.is_sfence connect slots_1.io.wakeup_ports[4].bits.uop.is_fencei, issue_slots[1].wakeup_ports[4].bits.uop.is_fencei connect slots_1.io.wakeup_ports[4].bits.uop.is_fence, issue_slots[1].wakeup_ports[4].bits.uop.is_fence connect slots_1.io.wakeup_ports[4].bits.uop.is_sfb, issue_slots[1].wakeup_ports[4].bits.uop.is_sfb connect slots_1.io.wakeup_ports[4].bits.uop.br_type, issue_slots[1].wakeup_ports[4].bits.uop.br_type connect slots_1.io.wakeup_ports[4].bits.uop.br_tag, issue_slots[1].wakeup_ports[4].bits.uop.br_tag connect slots_1.io.wakeup_ports[4].bits.uop.br_mask, issue_slots[1].wakeup_ports[4].bits.uop.br_mask connect slots_1.io.wakeup_ports[4].bits.uop.dis_col_sel, issue_slots[1].wakeup_ports[4].bits.uop.dis_col_sel connect slots_1.io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint, issue_slots[1].wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect slots_1.io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint, issue_slots[1].wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect slots_1.io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint, issue_slots[1].wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect slots_1.io.wakeup_ports[4].bits.uop.iw_p2_speculative_child, issue_slots[1].wakeup_ports[4].bits.uop.iw_p2_speculative_child connect slots_1.io.wakeup_ports[4].bits.uop.iw_p1_speculative_child, issue_slots[1].wakeup_ports[4].bits.uop.iw_p1_speculative_child connect slots_1.io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen, issue_slots[1].wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect slots_1.io.wakeup_ports[4].bits.uop.iw_issued_partial_agen, issue_slots[1].wakeup_ports[4].bits.uop.iw_issued_partial_agen connect slots_1.io.wakeup_ports[4].bits.uop.iw_issued, issue_slots[1].wakeup_ports[4].bits.uop.iw_issued connect slots_1.io.wakeup_ports[4].bits.uop.fu_code[0], issue_slots[1].wakeup_ports[4].bits.uop.fu_code[0] connect slots_1.io.wakeup_ports[4].bits.uop.fu_code[1], issue_slots[1].wakeup_ports[4].bits.uop.fu_code[1] connect slots_1.io.wakeup_ports[4].bits.uop.fu_code[2], issue_slots[1].wakeup_ports[4].bits.uop.fu_code[2] connect slots_1.io.wakeup_ports[4].bits.uop.fu_code[3], issue_slots[1].wakeup_ports[4].bits.uop.fu_code[3] connect slots_1.io.wakeup_ports[4].bits.uop.fu_code[4], issue_slots[1].wakeup_ports[4].bits.uop.fu_code[4] connect slots_1.io.wakeup_ports[4].bits.uop.fu_code[5], issue_slots[1].wakeup_ports[4].bits.uop.fu_code[5] connect slots_1.io.wakeup_ports[4].bits.uop.fu_code[6], issue_slots[1].wakeup_ports[4].bits.uop.fu_code[6] connect slots_1.io.wakeup_ports[4].bits.uop.fu_code[7], issue_slots[1].wakeup_ports[4].bits.uop.fu_code[7] connect slots_1.io.wakeup_ports[4].bits.uop.fu_code[8], issue_slots[1].wakeup_ports[4].bits.uop.fu_code[8] connect slots_1.io.wakeup_ports[4].bits.uop.fu_code[9], issue_slots[1].wakeup_ports[4].bits.uop.fu_code[9] connect slots_1.io.wakeup_ports[4].bits.uop.iq_type[0], issue_slots[1].wakeup_ports[4].bits.uop.iq_type[0] connect slots_1.io.wakeup_ports[4].bits.uop.iq_type[1], issue_slots[1].wakeup_ports[4].bits.uop.iq_type[1] connect slots_1.io.wakeup_ports[4].bits.uop.iq_type[2], issue_slots[1].wakeup_ports[4].bits.uop.iq_type[2] connect slots_1.io.wakeup_ports[4].bits.uop.iq_type[3], issue_slots[1].wakeup_ports[4].bits.uop.iq_type[3] connect slots_1.io.wakeup_ports[4].bits.uop.debug_pc, issue_slots[1].wakeup_ports[4].bits.uop.debug_pc connect slots_1.io.wakeup_ports[4].bits.uop.is_rvc, issue_slots[1].wakeup_ports[4].bits.uop.is_rvc connect slots_1.io.wakeup_ports[4].bits.uop.debug_inst, issue_slots[1].wakeup_ports[4].bits.uop.debug_inst connect slots_1.io.wakeup_ports[4].bits.uop.inst, issue_slots[1].wakeup_ports[4].bits.uop.inst connect slots_1.io.wakeup_ports[4].valid, issue_slots[1].wakeup_ports[4].valid connect slots_1.io.squash_grant, issue_slots[1].squash_grant connect slots_1.io.clear, issue_slots[1].clear connect slots_1.io.kill, issue_slots[1].kill connect slots_1.io.brupdate.b2.target_offset, issue_slots[1].brupdate.b2.target_offset connect slots_1.io.brupdate.b2.jalr_target, issue_slots[1].brupdate.b2.jalr_target connect slots_1.io.brupdate.b2.pc_sel, issue_slots[1].brupdate.b2.pc_sel connect slots_1.io.brupdate.b2.cfi_type, issue_slots[1].brupdate.b2.cfi_type connect slots_1.io.brupdate.b2.taken, issue_slots[1].brupdate.b2.taken connect slots_1.io.brupdate.b2.mispredict, issue_slots[1].brupdate.b2.mispredict connect slots_1.io.brupdate.b2.uop.debug_tsrc, issue_slots[1].brupdate.b2.uop.debug_tsrc connect slots_1.io.brupdate.b2.uop.debug_fsrc, issue_slots[1].brupdate.b2.uop.debug_fsrc connect slots_1.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[1].brupdate.b2.uop.bp_xcpt_if connect slots_1.io.brupdate.b2.uop.bp_debug_if, issue_slots[1].brupdate.b2.uop.bp_debug_if connect slots_1.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[1].brupdate.b2.uop.xcpt_ma_if connect slots_1.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[1].brupdate.b2.uop.xcpt_ae_if connect slots_1.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[1].brupdate.b2.uop.xcpt_pf_if connect slots_1.io.brupdate.b2.uop.fp_typ, issue_slots[1].brupdate.b2.uop.fp_typ connect slots_1.io.brupdate.b2.uop.fp_rm, issue_slots[1].brupdate.b2.uop.fp_rm connect slots_1.io.brupdate.b2.uop.fp_val, issue_slots[1].brupdate.b2.uop.fp_val connect slots_1.io.brupdate.b2.uop.fcn_op, issue_slots[1].brupdate.b2.uop.fcn_op connect slots_1.io.brupdate.b2.uop.fcn_dw, issue_slots[1].brupdate.b2.uop.fcn_dw connect slots_1.io.brupdate.b2.uop.frs3_en, issue_slots[1].brupdate.b2.uop.frs3_en connect slots_1.io.brupdate.b2.uop.lrs2_rtype, issue_slots[1].brupdate.b2.uop.lrs2_rtype connect slots_1.io.brupdate.b2.uop.lrs1_rtype, issue_slots[1].brupdate.b2.uop.lrs1_rtype connect slots_1.io.brupdate.b2.uop.dst_rtype, issue_slots[1].brupdate.b2.uop.dst_rtype connect slots_1.io.brupdate.b2.uop.lrs3, issue_slots[1].brupdate.b2.uop.lrs3 connect slots_1.io.brupdate.b2.uop.lrs2, issue_slots[1].brupdate.b2.uop.lrs2 connect slots_1.io.brupdate.b2.uop.lrs1, issue_slots[1].brupdate.b2.uop.lrs1 connect slots_1.io.brupdate.b2.uop.ldst, issue_slots[1].brupdate.b2.uop.ldst connect slots_1.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[1].brupdate.b2.uop.ldst_is_rs1 connect slots_1.io.brupdate.b2.uop.csr_cmd, issue_slots[1].brupdate.b2.uop.csr_cmd connect slots_1.io.brupdate.b2.uop.flush_on_commit, issue_slots[1].brupdate.b2.uop.flush_on_commit connect slots_1.io.brupdate.b2.uop.is_unique, issue_slots[1].brupdate.b2.uop.is_unique connect slots_1.io.brupdate.b2.uop.uses_stq, issue_slots[1].brupdate.b2.uop.uses_stq connect slots_1.io.brupdate.b2.uop.uses_ldq, issue_slots[1].brupdate.b2.uop.uses_ldq connect slots_1.io.brupdate.b2.uop.mem_signed, issue_slots[1].brupdate.b2.uop.mem_signed connect slots_1.io.brupdate.b2.uop.mem_size, issue_slots[1].brupdate.b2.uop.mem_size connect slots_1.io.brupdate.b2.uop.mem_cmd, issue_slots[1].brupdate.b2.uop.mem_cmd connect slots_1.io.brupdate.b2.uop.exc_cause, issue_slots[1].brupdate.b2.uop.exc_cause connect slots_1.io.brupdate.b2.uop.exception, issue_slots[1].brupdate.b2.uop.exception connect slots_1.io.brupdate.b2.uop.stale_pdst, issue_slots[1].brupdate.b2.uop.stale_pdst connect slots_1.io.brupdate.b2.uop.ppred_busy, issue_slots[1].brupdate.b2.uop.ppred_busy connect slots_1.io.brupdate.b2.uop.prs3_busy, issue_slots[1].brupdate.b2.uop.prs3_busy connect slots_1.io.brupdate.b2.uop.prs2_busy, issue_slots[1].brupdate.b2.uop.prs2_busy connect slots_1.io.brupdate.b2.uop.prs1_busy, issue_slots[1].brupdate.b2.uop.prs1_busy connect slots_1.io.brupdate.b2.uop.ppred, issue_slots[1].brupdate.b2.uop.ppred connect slots_1.io.brupdate.b2.uop.prs3, issue_slots[1].brupdate.b2.uop.prs3 connect slots_1.io.brupdate.b2.uop.prs2, issue_slots[1].brupdate.b2.uop.prs2 connect slots_1.io.brupdate.b2.uop.prs1, issue_slots[1].brupdate.b2.uop.prs1 connect slots_1.io.brupdate.b2.uop.pdst, issue_slots[1].brupdate.b2.uop.pdst connect slots_1.io.brupdate.b2.uop.rxq_idx, issue_slots[1].brupdate.b2.uop.rxq_idx connect slots_1.io.brupdate.b2.uop.stq_idx, issue_slots[1].brupdate.b2.uop.stq_idx connect slots_1.io.brupdate.b2.uop.ldq_idx, issue_slots[1].brupdate.b2.uop.ldq_idx connect slots_1.io.brupdate.b2.uop.rob_idx, issue_slots[1].brupdate.b2.uop.rob_idx connect slots_1.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[1].brupdate.b2.uop.fp_ctrl.vec connect slots_1.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[1].brupdate.b2.uop.fp_ctrl.wflags connect slots_1.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[1].brupdate.b2.uop.fp_ctrl.sqrt connect slots_1.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[1].brupdate.b2.uop.fp_ctrl.div connect slots_1.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[1].brupdate.b2.uop.fp_ctrl.fma connect slots_1.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[1].brupdate.b2.uop.fp_ctrl.fastpipe connect slots_1.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[1].brupdate.b2.uop.fp_ctrl.toint connect slots_1.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[1].brupdate.b2.uop.fp_ctrl.fromint connect slots_1.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[1].brupdate.b2.uop.fp_ctrl.typeTagOut connect slots_1.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[1].brupdate.b2.uop.fp_ctrl.typeTagIn connect slots_1.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[1].brupdate.b2.uop.fp_ctrl.swap23 connect slots_1.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[1].brupdate.b2.uop.fp_ctrl.swap12 connect slots_1.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[1].brupdate.b2.uop.fp_ctrl.ren3 connect slots_1.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[1].brupdate.b2.uop.fp_ctrl.ren2 connect slots_1.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[1].brupdate.b2.uop.fp_ctrl.ren1 connect slots_1.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[1].brupdate.b2.uop.fp_ctrl.wen connect slots_1.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[1].brupdate.b2.uop.fp_ctrl.ldst connect slots_1.io.brupdate.b2.uop.op2_sel, issue_slots[1].brupdate.b2.uop.op2_sel connect slots_1.io.brupdate.b2.uop.op1_sel, issue_slots[1].brupdate.b2.uop.op1_sel connect slots_1.io.brupdate.b2.uop.imm_packed, issue_slots[1].brupdate.b2.uop.imm_packed connect slots_1.io.brupdate.b2.uop.pimm, issue_slots[1].brupdate.b2.uop.pimm connect slots_1.io.brupdate.b2.uop.imm_sel, issue_slots[1].brupdate.b2.uop.imm_sel connect slots_1.io.brupdate.b2.uop.imm_rename, issue_slots[1].brupdate.b2.uop.imm_rename connect slots_1.io.brupdate.b2.uop.taken, issue_slots[1].brupdate.b2.uop.taken connect slots_1.io.brupdate.b2.uop.pc_lob, issue_slots[1].brupdate.b2.uop.pc_lob connect slots_1.io.brupdate.b2.uop.edge_inst, issue_slots[1].brupdate.b2.uop.edge_inst connect slots_1.io.brupdate.b2.uop.ftq_idx, issue_slots[1].brupdate.b2.uop.ftq_idx connect slots_1.io.brupdate.b2.uop.is_mov, issue_slots[1].brupdate.b2.uop.is_mov connect slots_1.io.brupdate.b2.uop.is_rocc, issue_slots[1].brupdate.b2.uop.is_rocc connect slots_1.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[1].brupdate.b2.uop.is_sys_pc2epc connect slots_1.io.brupdate.b2.uop.is_eret, issue_slots[1].brupdate.b2.uop.is_eret connect slots_1.io.brupdate.b2.uop.is_amo, issue_slots[1].brupdate.b2.uop.is_amo connect slots_1.io.brupdate.b2.uop.is_sfence, issue_slots[1].brupdate.b2.uop.is_sfence connect slots_1.io.brupdate.b2.uop.is_fencei, issue_slots[1].brupdate.b2.uop.is_fencei connect slots_1.io.brupdate.b2.uop.is_fence, issue_slots[1].brupdate.b2.uop.is_fence connect slots_1.io.brupdate.b2.uop.is_sfb, issue_slots[1].brupdate.b2.uop.is_sfb connect slots_1.io.brupdate.b2.uop.br_type, issue_slots[1].brupdate.b2.uop.br_type connect slots_1.io.brupdate.b2.uop.br_tag, issue_slots[1].brupdate.b2.uop.br_tag connect slots_1.io.brupdate.b2.uop.br_mask, issue_slots[1].brupdate.b2.uop.br_mask connect slots_1.io.brupdate.b2.uop.dis_col_sel, issue_slots[1].brupdate.b2.uop.dis_col_sel connect slots_1.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[1].brupdate.b2.uop.iw_p3_bypass_hint connect slots_1.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[1].brupdate.b2.uop.iw_p2_bypass_hint connect slots_1.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[1].brupdate.b2.uop.iw_p1_bypass_hint connect slots_1.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[1].brupdate.b2.uop.iw_p2_speculative_child connect slots_1.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[1].brupdate.b2.uop.iw_p1_speculative_child connect slots_1.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[1].brupdate.b2.uop.iw_issued_partial_dgen connect slots_1.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[1].brupdate.b2.uop.iw_issued_partial_agen connect slots_1.io.brupdate.b2.uop.iw_issued, issue_slots[1].brupdate.b2.uop.iw_issued connect slots_1.io.brupdate.b2.uop.fu_code[0], issue_slots[1].brupdate.b2.uop.fu_code[0] connect slots_1.io.brupdate.b2.uop.fu_code[1], issue_slots[1].brupdate.b2.uop.fu_code[1] connect slots_1.io.brupdate.b2.uop.fu_code[2], issue_slots[1].brupdate.b2.uop.fu_code[2] connect slots_1.io.brupdate.b2.uop.fu_code[3], issue_slots[1].brupdate.b2.uop.fu_code[3] connect slots_1.io.brupdate.b2.uop.fu_code[4], issue_slots[1].brupdate.b2.uop.fu_code[4] connect slots_1.io.brupdate.b2.uop.fu_code[5], issue_slots[1].brupdate.b2.uop.fu_code[5] connect slots_1.io.brupdate.b2.uop.fu_code[6], issue_slots[1].brupdate.b2.uop.fu_code[6] connect slots_1.io.brupdate.b2.uop.fu_code[7], issue_slots[1].brupdate.b2.uop.fu_code[7] connect slots_1.io.brupdate.b2.uop.fu_code[8], issue_slots[1].brupdate.b2.uop.fu_code[8] connect slots_1.io.brupdate.b2.uop.fu_code[9], issue_slots[1].brupdate.b2.uop.fu_code[9] connect slots_1.io.brupdate.b2.uop.iq_type[0], issue_slots[1].brupdate.b2.uop.iq_type[0] connect slots_1.io.brupdate.b2.uop.iq_type[1], issue_slots[1].brupdate.b2.uop.iq_type[1] connect slots_1.io.brupdate.b2.uop.iq_type[2], issue_slots[1].brupdate.b2.uop.iq_type[2] connect slots_1.io.brupdate.b2.uop.iq_type[3], issue_slots[1].brupdate.b2.uop.iq_type[3] connect slots_1.io.brupdate.b2.uop.debug_pc, issue_slots[1].brupdate.b2.uop.debug_pc connect slots_1.io.brupdate.b2.uop.is_rvc, issue_slots[1].brupdate.b2.uop.is_rvc connect slots_1.io.brupdate.b2.uop.debug_inst, issue_slots[1].brupdate.b2.uop.debug_inst connect slots_1.io.brupdate.b2.uop.inst, issue_slots[1].brupdate.b2.uop.inst connect slots_1.io.brupdate.b1.mispredict_mask, issue_slots[1].brupdate.b1.mispredict_mask connect slots_1.io.brupdate.b1.resolve_mask, issue_slots[1].brupdate.b1.resolve_mask connect issue_slots[1].out_uop.debug_tsrc, slots_1.io.out_uop.debug_tsrc connect issue_slots[1].out_uop.debug_fsrc, slots_1.io.out_uop.debug_fsrc connect issue_slots[1].out_uop.bp_xcpt_if, slots_1.io.out_uop.bp_xcpt_if connect issue_slots[1].out_uop.bp_debug_if, slots_1.io.out_uop.bp_debug_if connect issue_slots[1].out_uop.xcpt_ma_if, slots_1.io.out_uop.xcpt_ma_if connect issue_slots[1].out_uop.xcpt_ae_if, slots_1.io.out_uop.xcpt_ae_if connect issue_slots[1].out_uop.xcpt_pf_if, slots_1.io.out_uop.xcpt_pf_if connect issue_slots[1].out_uop.fp_typ, slots_1.io.out_uop.fp_typ connect issue_slots[1].out_uop.fp_rm, slots_1.io.out_uop.fp_rm connect issue_slots[1].out_uop.fp_val, slots_1.io.out_uop.fp_val connect issue_slots[1].out_uop.fcn_op, slots_1.io.out_uop.fcn_op connect issue_slots[1].out_uop.fcn_dw, slots_1.io.out_uop.fcn_dw connect issue_slots[1].out_uop.frs3_en, slots_1.io.out_uop.frs3_en connect issue_slots[1].out_uop.lrs2_rtype, slots_1.io.out_uop.lrs2_rtype connect issue_slots[1].out_uop.lrs1_rtype, slots_1.io.out_uop.lrs1_rtype connect issue_slots[1].out_uop.dst_rtype, slots_1.io.out_uop.dst_rtype connect issue_slots[1].out_uop.lrs3, slots_1.io.out_uop.lrs3 connect issue_slots[1].out_uop.lrs2, slots_1.io.out_uop.lrs2 connect issue_slots[1].out_uop.lrs1, slots_1.io.out_uop.lrs1 connect issue_slots[1].out_uop.ldst, slots_1.io.out_uop.ldst connect issue_slots[1].out_uop.ldst_is_rs1, slots_1.io.out_uop.ldst_is_rs1 connect issue_slots[1].out_uop.csr_cmd, slots_1.io.out_uop.csr_cmd connect issue_slots[1].out_uop.flush_on_commit, slots_1.io.out_uop.flush_on_commit connect issue_slots[1].out_uop.is_unique, slots_1.io.out_uop.is_unique connect issue_slots[1].out_uop.uses_stq, slots_1.io.out_uop.uses_stq connect issue_slots[1].out_uop.uses_ldq, slots_1.io.out_uop.uses_ldq connect issue_slots[1].out_uop.mem_signed, slots_1.io.out_uop.mem_signed connect issue_slots[1].out_uop.mem_size, slots_1.io.out_uop.mem_size connect issue_slots[1].out_uop.mem_cmd, slots_1.io.out_uop.mem_cmd connect issue_slots[1].out_uop.exc_cause, slots_1.io.out_uop.exc_cause connect issue_slots[1].out_uop.exception, slots_1.io.out_uop.exception connect issue_slots[1].out_uop.stale_pdst, slots_1.io.out_uop.stale_pdst connect issue_slots[1].out_uop.ppred_busy, slots_1.io.out_uop.ppred_busy connect issue_slots[1].out_uop.prs3_busy, slots_1.io.out_uop.prs3_busy connect issue_slots[1].out_uop.prs2_busy, slots_1.io.out_uop.prs2_busy connect issue_slots[1].out_uop.prs1_busy, slots_1.io.out_uop.prs1_busy connect issue_slots[1].out_uop.ppred, slots_1.io.out_uop.ppred connect issue_slots[1].out_uop.prs3, slots_1.io.out_uop.prs3 connect issue_slots[1].out_uop.prs2, slots_1.io.out_uop.prs2 connect issue_slots[1].out_uop.prs1, slots_1.io.out_uop.prs1 connect issue_slots[1].out_uop.pdst, slots_1.io.out_uop.pdst connect issue_slots[1].out_uop.rxq_idx, slots_1.io.out_uop.rxq_idx connect issue_slots[1].out_uop.stq_idx, slots_1.io.out_uop.stq_idx connect issue_slots[1].out_uop.ldq_idx, slots_1.io.out_uop.ldq_idx connect issue_slots[1].out_uop.rob_idx, slots_1.io.out_uop.rob_idx connect issue_slots[1].out_uop.fp_ctrl.vec, slots_1.io.out_uop.fp_ctrl.vec connect issue_slots[1].out_uop.fp_ctrl.wflags, slots_1.io.out_uop.fp_ctrl.wflags connect issue_slots[1].out_uop.fp_ctrl.sqrt, slots_1.io.out_uop.fp_ctrl.sqrt connect issue_slots[1].out_uop.fp_ctrl.div, slots_1.io.out_uop.fp_ctrl.div connect issue_slots[1].out_uop.fp_ctrl.fma, slots_1.io.out_uop.fp_ctrl.fma connect issue_slots[1].out_uop.fp_ctrl.fastpipe, slots_1.io.out_uop.fp_ctrl.fastpipe connect issue_slots[1].out_uop.fp_ctrl.toint, slots_1.io.out_uop.fp_ctrl.toint connect issue_slots[1].out_uop.fp_ctrl.fromint, slots_1.io.out_uop.fp_ctrl.fromint connect issue_slots[1].out_uop.fp_ctrl.typeTagOut, slots_1.io.out_uop.fp_ctrl.typeTagOut connect issue_slots[1].out_uop.fp_ctrl.typeTagIn, slots_1.io.out_uop.fp_ctrl.typeTagIn connect issue_slots[1].out_uop.fp_ctrl.swap23, slots_1.io.out_uop.fp_ctrl.swap23 connect issue_slots[1].out_uop.fp_ctrl.swap12, slots_1.io.out_uop.fp_ctrl.swap12 connect issue_slots[1].out_uop.fp_ctrl.ren3, slots_1.io.out_uop.fp_ctrl.ren3 connect issue_slots[1].out_uop.fp_ctrl.ren2, slots_1.io.out_uop.fp_ctrl.ren2 connect issue_slots[1].out_uop.fp_ctrl.ren1, slots_1.io.out_uop.fp_ctrl.ren1 connect issue_slots[1].out_uop.fp_ctrl.wen, slots_1.io.out_uop.fp_ctrl.wen connect issue_slots[1].out_uop.fp_ctrl.ldst, slots_1.io.out_uop.fp_ctrl.ldst connect issue_slots[1].out_uop.op2_sel, slots_1.io.out_uop.op2_sel connect issue_slots[1].out_uop.op1_sel, slots_1.io.out_uop.op1_sel connect issue_slots[1].out_uop.imm_packed, slots_1.io.out_uop.imm_packed connect issue_slots[1].out_uop.pimm, slots_1.io.out_uop.pimm connect issue_slots[1].out_uop.imm_sel, slots_1.io.out_uop.imm_sel connect issue_slots[1].out_uop.imm_rename, slots_1.io.out_uop.imm_rename connect issue_slots[1].out_uop.taken, slots_1.io.out_uop.taken connect issue_slots[1].out_uop.pc_lob, slots_1.io.out_uop.pc_lob connect issue_slots[1].out_uop.edge_inst, slots_1.io.out_uop.edge_inst connect issue_slots[1].out_uop.ftq_idx, slots_1.io.out_uop.ftq_idx connect issue_slots[1].out_uop.is_mov, slots_1.io.out_uop.is_mov connect issue_slots[1].out_uop.is_rocc, slots_1.io.out_uop.is_rocc connect issue_slots[1].out_uop.is_sys_pc2epc, slots_1.io.out_uop.is_sys_pc2epc connect issue_slots[1].out_uop.is_eret, slots_1.io.out_uop.is_eret connect issue_slots[1].out_uop.is_amo, slots_1.io.out_uop.is_amo connect issue_slots[1].out_uop.is_sfence, slots_1.io.out_uop.is_sfence connect issue_slots[1].out_uop.is_fencei, slots_1.io.out_uop.is_fencei connect issue_slots[1].out_uop.is_fence, slots_1.io.out_uop.is_fence connect issue_slots[1].out_uop.is_sfb, slots_1.io.out_uop.is_sfb connect issue_slots[1].out_uop.br_type, slots_1.io.out_uop.br_type connect issue_slots[1].out_uop.br_tag, slots_1.io.out_uop.br_tag connect issue_slots[1].out_uop.br_mask, slots_1.io.out_uop.br_mask connect issue_slots[1].out_uop.dis_col_sel, slots_1.io.out_uop.dis_col_sel connect issue_slots[1].out_uop.iw_p3_bypass_hint, slots_1.io.out_uop.iw_p3_bypass_hint connect issue_slots[1].out_uop.iw_p2_bypass_hint, slots_1.io.out_uop.iw_p2_bypass_hint connect issue_slots[1].out_uop.iw_p1_bypass_hint, slots_1.io.out_uop.iw_p1_bypass_hint connect issue_slots[1].out_uop.iw_p2_speculative_child, slots_1.io.out_uop.iw_p2_speculative_child connect issue_slots[1].out_uop.iw_p1_speculative_child, slots_1.io.out_uop.iw_p1_speculative_child connect issue_slots[1].out_uop.iw_issued_partial_dgen, slots_1.io.out_uop.iw_issued_partial_dgen connect issue_slots[1].out_uop.iw_issued_partial_agen, slots_1.io.out_uop.iw_issued_partial_agen connect issue_slots[1].out_uop.iw_issued, slots_1.io.out_uop.iw_issued connect issue_slots[1].out_uop.fu_code[0], slots_1.io.out_uop.fu_code[0] connect issue_slots[1].out_uop.fu_code[1], slots_1.io.out_uop.fu_code[1] connect issue_slots[1].out_uop.fu_code[2], slots_1.io.out_uop.fu_code[2] connect issue_slots[1].out_uop.fu_code[3], slots_1.io.out_uop.fu_code[3] connect issue_slots[1].out_uop.fu_code[4], slots_1.io.out_uop.fu_code[4] connect issue_slots[1].out_uop.fu_code[5], slots_1.io.out_uop.fu_code[5] connect issue_slots[1].out_uop.fu_code[6], slots_1.io.out_uop.fu_code[6] connect issue_slots[1].out_uop.fu_code[7], slots_1.io.out_uop.fu_code[7] connect issue_slots[1].out_uop.fu_code[8], slots_1.io.out_uop.fu_code[8] connect issue_slots[1].out_uop.fu_code[9], slots_1.io.out_uop.fu_code[9] connect issue_slots[1].out_uop.iq_type[0], slots_1.io.out_uop.iq_type[0] connect issue_slots[1].out_uop.iq_type[1], slots_1.io.out_uop.iq_type[1] connect issue_slots[1].out_uop.iq_type[2], slots_1.io.out_uop.iq_type[2] connect issue_slots[1].out_uop.iq_type[3], slots_1.io.out_uop.iq_type[3] connect issue_slots[1].out_uop.debug_pc, slots_1.io.out_uop.debug_pc connect issue_slots[1].out_uop.is_rvc, slots_1.io.out_uop.is_rvc connect issue_slots[1].out_uop.debug_inst, slots_1.io.out_uop.debug_inst connect issue_slots[1].out_uop.inst, slots_1.io.out_uop.inst connect slots_1.io.in_uop.bits.debug_tsrc, issue_slots[1].in_uop.bits.debug_tsrc connect slots_1.io.in_uop.bits.debug_fsrc, issue_slots[1].in_uop.bits.debug_fsrc connect slots_1.io.in_uop.bits.bp_xcpt_if, issue_slots[1].in_uop.bits.bp_xcpt_if connect slots_1.io.in_uop.bits.bp_debug_if, issue_slots[1].in_uop.bits.bp_debug_if connect slots_1.io.in_uop.bits.xcpt_ma_if, issue_slots[1].in_uop.bits.xcpt_ma_if connect slots_1.io.in_uop.bits.xcpt_ae_if, issue_slots[1].in_uop.bits.xcpt_ae_if connect slots_1.io.in_uop.bits.xcpt_pf_if, issue_slots[1].in_uop.bits.xcpt_pf_if connect slots_1.io.in_uop.bits.fp_typ, issue_slots[1].in_uop.bits.fp_typ connect slots_1.io.in_uop.bits.fp_rm, issue_slots[1].in_uop.bits.fp_rm connect slots_1.io.in_uop.bits.fp_val, issue_slots[1].in_uop.bits.fp_val connect slots_1.io.in_uop.bits.fcn_op, issue_slots[1].in_uop.bits.fcn_op connect slots_1.io.in_uop.bits.fcn_dw, issue_slots[1].in_uop.bits.fcn_dw connect slots_1.io.in_uop.bits.frs3_en, issue_slots[1].in_uop.bits.frs3_en connect slots_1.io.in_uop.bits.lrs2_rtype, issue_slots[1].in_uop.bits.lrs2_rtype connect slots_1.io.in_uop.bits.lrs1_rtype, issue_slots[1].in_uop.bits.lrs1_rtype connect slots_1.io.in_uop.bits.dst_rtype, issue_slots[1].in_uop.bits.dst_rtype connect slots_1.io.in_uop.bits.lrs3, issue_slots[1].in_uop.bits.lrs3 connect slots_1.io.in_uop.bits.lrs2, issue_slots[1].in_uop.bits.lrs2 connect slots_1.io.in_uop.bits.lrs1, issue_slots[1].in_uop.bits.lrs1 connect slots_1.io.in_uop.bits.ldst, issue_slots[1].in_uop.bits.ldst connect slots_1.io.in_uop.bits.ldst_is_rs1, issue_slots[1].in_uop.bits.ldst_is_rs1 connect slots_1.io.in_uop.bits.csr_cmd, issue_slots[1].in_uop.bits.csr_cmd connect slots_1.io.in_uop.bits.flush_on_commit, issue_slots[1].in_uop.bits.flush_on_commit connect slots_1.io.in_uop.bits.is_unique, issue_slots[1].in_uop.bits.is_unique connect slots_1.io.in_uop.bits.uses_stq, issue_slots[1].in_uop.bits.uses_stq connect slots_1.io.in_uop.bits.uses_ldq, issue_slots[1].in_uop.bits.uses_ldq connect slots_1.io.in_uop.bits.mem_signed, issue_slots[1].in_uop.bits.mem_signed connect slots_1.io.in_uop.bits.mem_size, issue_slots[1].in_uop.bits.mem_size connect slots_1.io.in_uop.bits.mem_cmd, issue_slots[1].in_uop.bits.mem_cmd connect slots_1.io.in_uop.bits.exc_cause, issue_slots[1].in_uop.bits.exc_cause connect slots_1.io.in_uop.bits.exception, issue_slots[1].in_uop.bits.exception connect slots_1.io.in_uop.bits.stale_pdst, issue_slots[1].in_uop.bits.stale_pdst connect slots_1.io.in_uop.bits.ppred_busy, issue_slots[1].in_uop.bits.ppred_busy connect slots_1.io.in_uop.bits.prs3_busy, issue_slots[1].in_uop.bits.prs3_busy connect slots_1.io.in_uop.bits.prs2_busy, issue_slots[1].in_uop.bits.prs2_busy connect slots_1.io.in_uop.bits.prs1_busy, issue_slots[1].in_uop.bits.prs1_busy connect slots_1.io.in_uop.bits.ppred, issue_slots[1].in_uop.bits.ppred connect slots_1.io.in_uop.bits.prs3, issue_slots[1].in_uop.bits.prs3 connect slots_1.io.in_uop.bits.prs2, issue_slots[1].in_uop.bits.prs2 connect slots_1.io.in_uop.bits.prs1, issue_slots[1].in_uop.bits.prs1 connect slots_1.io.in_uop.bits.pdst, issue_slots[1].in_uop.bits.pdst connect slots_1.io.in_uop.bits.rxq_idx, issue_slots[1].in_uop.bits.rxq_idx connect slots_1.io.in_uop.bits.stq_idx, issue_slots[1].in_uop.bits.stq_idx connect slots_1.io.in_uop.bits.ldq_idx, issue_slots[1].in_uop.bits.ldq_idx connect slots_1.io.in_uop.bits.rob_idx, issue_slots[1].in_uop.bits.rob_idx connect slots_1.io.in_uop.bits.fp_ctrl.vec, issue_slots[1].in_uop.bits.fp_ctrl.vec connect slots_1.io.in_uop.bits.fp_ctrl.wflags, issue_slots[1].in_uop.bits.fp_ctrl.wflags connect slots_1.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[1].in_uop.bits.fp_ctrl.sqrt connect slots_1.io.in_uop.bits.fp_ctrl.div, issue_slots[1].in_uop.bits.fp_ctrl.div connect slots_1.io.in_uop.bits.fp_ctrl.fma, issue_slots[1].in_uop.bits.fp_ctrl.fma connect slots_1.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[1].in_uop.bits.fp_ctrl.fastpipe connect slots_1.io.in_uop.bits.fp_ctrl.toint, issue_slots[1].in_uop.bits.fp_ctrl.toint connect slots_1.io.in_uop.bits.fp_ctrl.fromint, issue_slots[1].in_uop.bits.fp_ctrl.fromint connect slots_1.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[1].in_uop.bits.fp_ctrl.typeTagOut connect slots_1.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[1].in_uop.bits.fp_ctrl.typeTagIn connect slots_1.io.in_uop.bits.fp_ctrl.swap23, issue_slots[1].in_uop.bits.fp_ctrl.swap23 connect slots_1.io.in_uop.bits.fp_ctrl.swap12, issue_slots[1].in_uop.bits.fp_ctrl.swap12 connect slots_1.io.in_uop.bits.fp_ctrl.ren3, issue_slots[1].in_uop.bits.fp_ctrl.ren3 connect slots_1.io.in_uop.bits.fp_ctrl.ren2, issue_slots[1].in_uop.bits.fp_ctrl.ren2 connect slots_1.io.in_uop.bits.fp_ctrl.ren1, issue_slots[1].in_uop.bits.fp_ctrl.ren1 connect slots_1.io.in_uop.bits.fp_ctrl.wen, issue_slots[1].in_uop.bits.fp_ctrl.wen connect slots_1.io.in_uop.bits.fp_ctrl.ldst, issue_slots[1].in_uop.bits.fp_ctrl.ldst connect slots_1.io.in_uop.bits.op2_sel, issue_slots[1].in_uop.bits.op2_sel connect slots_1.io.in_uop.bits.op1_sel, issue_slots[1].in_uop.bits.op1_sel connect slots_1.io.in_uop.bits.imm_packed, issue_slots[1].in_uop.bits.imm_packed connect slots_1.io.in_uop.bits.pimm, issue_slots[1].in_uop.bits.pimm connect slots_1.io.in_uop.bits.imm_sel, issue_slots[1].in_uop.bits.imm_sel connect slots_1.io.in_uop.bits.imm_rename, issue_slots[1].in_uop.bits.imm_rename connect slots_1.io.in_uop.bits.taken, issue_slots[1].in_uop.bits.taken connect slots_1.io.in_uop.bits.pc_lob, issue_slots[1].in_uop.bits.pc_lob connect slots_1.io.in_uop.bits.edge_inst, issue_slots[1].in_uop.bits.edge_inst connect slots_1.io.in_uop.bits.ftq_idx, issue_slots[1].in_uop.bits.ftq_idx connect slots_1.io.in_uop.bits.is_mov, issue_slots[1].in_uop.bits.is_mov connect slots_1.io.in_uop.bits.is_rocc, issue_slots[1].in_uop.bits.is_rocc connect slots_1.io.in_uop.bits.is_sys_pc2epc, issue_slots[1].in_uop.bits.is_sys_pc2epc connect slots_1.io.in_uop.bits.is_eret, issue_slots[1].in_uop.bits.is_eret connect slots_1.io.in_uop.bits.is_amo, issue_slots[1].in_uop.bits.is_amo connect slots_1.io.in_uop.bits.is_sfence, issue_slots[1].in_uop.bits.is_sfence connect slots_1.io.in_uop.bits.is_fencei, issue_slots[1].in_uop.bits.is_fencei connect slots_1.io.in_uop.bits.is_fence, issue_slots[1].in_uop.bits.is_fence connect slots_1.io.in_uop.bits.is_sfb, issue_slots[1].in_uop.bits.is_sfb connect slots_1.io.in_uop.bits.br_type, issue_slots[1].in_uop.bits.br_type connect slots_1.io.in_uop.bits.br_tag, issue_slots[1].in_uop.bits.br_tag connect slots_1.io.in_uop.bits.br_mask, issue_slots[1].in_uop.bits.br_mask connect slots_1.io.in_uop.bits.dis_col_sel, issue_slots[1].in_uop.bits.dis_col_sel connect slots_1.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[1].in_uop.bits.iw_p3_bypass_hint connect slots_1.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[1].in_uop.bits.iw_p2_bypass_hint connect slots_1.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[1].in_uop.bits.iw_p1_bypass_hint connect slots_1.io.in_uop.bits.iw_p2_speculative_child, issue_slots[1].in_uop.bits.iw_p2_speculative_child connect slots_1.io.in_uop.bits.iw_p1_speculative_child, issue_slots[1].in_uop.bits.iw_p1_speculative_child connect slots_1.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[1].in_uop.bits.iw_issued_partial_dgen connect slots_1.io.in_uop.bits.iw_issued_partial_agen, issue_slots[1].in_uop.bits.iw_issued_partial_agen connect slots_1.io.in_uop.bits.iw_issued, issue_slots[1].in_uop.bits.iw_issued connect slots_1.io.in_uop.bits.fu_code[0], issue_slots[1].in_uop.bits.fu_code[0] connect slots_1.io.in_uop.bits.fu_code[1], issue_slots[1].in_uop.bits.fu_code[1] connect slots_1.io.in_uop.bits.fu_code[2], issue_slots[1].in_uop.bits.fu_code[2] connect slots_1.io.in_uop.bits.fu_code[3], issue_slots[1].in_uop.bits.fu_code[3] connect slots_1.io.in_uop.bits.fu_code[4], issue_slots[1].in_uop.bits.fu_code[4] connect slots_1.io.in_uop.bits.fu_code[5], issue_slots[1].in_uop.bits.fu_code[5] connect slots_1.io.in_uop.bits.fu_code[6], issue_slots[1].in_uop.bits.fu_code[6] connect slots_1.io.in_uop.bits.fu_code[7], issue_slots[1].in_uop.bits.fu_code[7] connect slots_1.io.in_uop.bits.fu_code[8], issue_slots[1].in_uop.bits.fu_code[8] connect slots_1.io.in_uop.bits.fu_code[9], issue_slots[1].in_uop.bits.fu_code[9] connect slots_1.io.in_uop.bits.iq_type[0], issue_slots[1].in_uop.bits.iq_type[0] connect slots_1.io.in_uop.bits.iq_type[1], issue_slots[1].in_uop.bits.iq_type[1] connect slots_1.io.in_uop.bits.iq_type[2], issue_slots[1].in_uop.bits.iq_type[2] connect slots_1.io.in_uop.bits.iq_type[3], issue_slots[1].in_uop.bits.iq_type[3] connect slots_1.io.in_uop.bits.debug_pc, issue_slots[1].in_uop.bits.debug_pc connect slots_1.io.in_uop.bits.is_rvc, issue_slots[1].in_uop.bits.is_rvc connect slots_1.io.in_uop.bits.debug_inst, issue_slots[1].in_uop.bits.debug_inst connect slots_1.io.in_uop.bits.inst, issue_slots[1].in_uop.bits.inst connect slots_1.io.in_uop.valid, issue_slots[1].in_uop.valid connect issue_slots[1].iss_uop.debug_tsrc, slots_1.io.iss_uop.debug_tsrc connect issue_slots[1].iss_uop.debug_fsrc, slots_1.io.iss_uop.debug_fsrc connect issue_slots[1].iss_uop.bp_xcpt_if, slots_1.io.iss_uop.bp_xcpt_if connect issue_slots[1].iss_uop.bp_debug_if, slots_1.io.iss_uop.bp_debug_if connect issue_slots[1].iss_uop.xcpt_ma_if, slots_1.io.iss_uop.xcpt_ma_if connect issue_slots[1].iss_uop.xcpt_ae_if, slots_1.io.iss_uop.xcpt_ae_if connect issue_slots[1].iss_uop.xcpt_pf_if, slots_1.io.iss_uop.xcpt_pf_if connect issue_slots[1].iss_uop.fp_typ, slots_1.io.iss_uop.fp_typ connect issue_slots[1].iss_uop.fp_rm, slots_1.io.iss_uop.fp_rm connect issue_slots[1].iss_uop.fp_val, slots_1.io.iss_uop.fp_val connect issue_slots[1].iss_uop.fcn_op, slots_1.io.iss_uop.fcn_op connect issue_slots[1].iss_uop.fcn_dw, slots_1.io.iss_uop.fcn_dw connect issue_slots[1].iss_uop.frs3_en, slots_1.io.iss_uop.frs3_en connect issue_slots[1].iss_uop.lrs2_rtype, slots_1.io.iss_uop.lrs2_rtype connect issue_slots[1].iss_uop.lrs1_rtype, slots_1.io.iss_uop.lrs1_rtype connect issue_slots[1].iss_uop.dst_rtype, slots_1.io.iss_uop.dst_rtype connect issue_slots[1].iss_uop.lrs3, slots_1.io.iss_uop.lrs3 connect issue_slots[1].iss_uop.lrs2, slots_1.io.iss_uop.lrs2 connect issue_slots[1].iss_uop.lrs1, slots_1.io.iss_uop.lrs1 connect issue_slots[1].iss_uop.ldst, slots_1.io.iss_uop.ldst connect issue_slots[1].iss_uop.ldst_is_rs1, slots_1.io.iss_uop.ldst_is_rs1 connect issue_slots[1].iss_uop.csr_cmd, slots_1.io.iss_uop.csr_cmd connect issue_slots[1].iss_uop.flush_on_commit, slots_1.io.iss_uop.flush_on_commit connect issue_slots[1].iss_uop.is_unique, slots_1.io.iss_uop.is_unique connect issue_slots[1].iss_uop.uses_stq, slots_1.io.iss_uop.uses_stq connect issue_slots[1].iss_uop.uses_ldq, slots_1.io.iss_uop.uses_ldq connect issue_slots[1].iss_uop.mem_signed, slots_1.io.iss_uop.mem_signed connect issue_slots[1].iss_uop.mem_size, slots_1.io.iss_uop.mem_size connect issue_slots[1].iss_uop.mem_cmd, slots_1.io.iss_uop.mem_cmd connect issue_slots[1].iss_uop.exc_cause, slots_1.io.iss_uop.exc_cause connect issue_slots[1].iss_uop.exception, slots_1.io.iss_uop.exception connect issue_slots[1].iss_uop.stale_pdst, slots_1.io.iss_uop.stale_pdst connect issue_slots[1].iss_uop.ppred_busy, slots_1.io.iss_uop.ppred_busy connect issue_slots[1].iss_uop.prs3_busy, slots_1.io.iss_uop.prs3_busy connect issue_slots[1].iss_uop.prs2_busy, slots_1.io.iss_uop.prs2_busy connect issue_slots[1].iss_uop.prs1_busy, slots_1.io.iss_uop.prs1_busy connect issue_slots[1].iss_uop.ppred, slots_1.io.iss_uop.ppred connect issue_slots[1].iss_uop.prs3, slots_1.io.iss_uop.prs3 connect issue_slots[1].iss_uop.prs2, slots_1.io.iss_uop.prs2 connect issue_slots[1].iss_uop.prs1, slots_1.io.iss_uop.prs1 connect issue_slots[1].iss_uop.pdst, slots_1.io.iss_uop.pdst connect issue_slots[1].iss_uop.rxq_idx, slots_1.io.iss_uop.rxq_idx connect issue_slots[1].iss_uop.stq_idx, slots_1.io.iss_uop.stq_idx connect issue_slots[1].iss_uop.ldq_idx, slots_1.io.iss_uop.ldq_idx connect issue_slots[1].iss_uop.rob_idx, slots_1.io.iss_uop.rob_idx connect issue_slots[1].iss_uop.fp_ctrl.vec, slots_1.io.iss_uop.fp_ctrl.vec connect issue_slots[1].iss_uop.fp_ctrl.wflags, slots_1.io.iss_uop.fp_ctrl.wflags connect issue_slots[1].iss_uop.fp_ctrl.sqrt, slots_1.io.iss_uop.fp_ctrl.sqrt connect issue_slots[1].iss_uop.fp_ctrl.div, slots_1.io.iss_uop.fp_ctrl.div connect issue_slots[1].iss_uop.fp_ctrl.fma, slots_1.io.iss_uop.fp_ctrl.fma connect issue_slots[1].iss_uop.fp_ctrl.fastpipe, slots_1.io.iss_uop.fp_ctrl.fastpipe connect issue_slots[1].iss_uop.fp_ctrl.toint, slots_1.io.iss_uop.fp_ctrl.toint connect issue_slots[1].iss_uop.fp_ctrl.fromint, slots_1.io.iss_uop.fp_ctrl.fromint connect issue_slots[1].iss_uop.fp_ctrl.typeTagOut, slots_1.io.iss_uop.fp_ctrl.typeTagOut connect issue_slots[1].iss_uop.fp_ctrl.typeTagIn, slots_1.io.iss_uop.fp_ctrl.typeTagIn connect issue_slots[1].iss_uop.fp_ctrl.swap23, slots_1.io.iss_uop.fp_ctrl.swap23 connect issue_slots[1].iss_uop.fp_ctrl.swap12, slots_1.io.iss_uop.fp_ctrl.swap12 connect issue_slots[1].iss_uop.fp_ctrl.ren3, slots_1.io.iss_uop.fp_ctrl.ren3 connect issue_slots[1].iss_uop.fp_ctrl.ren2, slots_1.io.iss_uop.fp_ctrl.ren2 connect issue_slots[1].iss_uop.fp_ctrl.ren1, slots_1.io.iss_uop.fp_ctrl.ren1 connect issue_slots[1].iss_uop.fp_ctrl.wen, slots_1.io.iss_uop.fp_ctrl.wen connect issue_slots[1].iss_uop.fp_ctrl.ldst, slots_1.io.iss_uop.fp_ctrl.ldst connect issue_slots[1].iss_uop.op2_sel, slots_1.io.iss_uop.op2_sel connect issue_slots[1].iss_uop.op1_sel, slots_1.io.iss_uop.op1_sel connect issue_slots[1].iss_uop.imm_packed, slots_1.io.iss_uop.imm_packed connect issue_slots[1].iss_uop.pimm, slots_1.io.iss_uop.pimm connect issue_slots[1].iss_uop.imm_sel, slots_1.io.iss_uop.imm_sel connect issue_slots[1].iss_uop.imm_rename, slots_1.io.iss_uop.imm_rename connect issue_slots[1].iss_uop.taken, slots_1.io.iss_uop.taken connect issue_slots[1].iss_uop.pc_lob, slots_1.io.iss_uop.pc_lob connect issue_slots[1].iss_uop.edge_inst, slots_1.io.iss_uop.edge_inst connect issue_slots[1].iss_uop.ftq_idx, slots_1.io.iss_uop.ftq_idx connect issue_slots[1].iss_uop.is_mov, slots_1.io.iss_uop.is_mov connect issue_slots[1].iss_uop.is_rocc, slots_1.io.iss_uop.is_rocc connect issue_slots[1].iss_uop.is_sys_pc2epc, slots_1.io.iss_uop.is_sys_pc2epc connect issue_slots[1].iss_uop.is_eret, slots_1.io.iss_uop.is_eret connect issue_slots[1].iss_uop.is_amo, slots_1.io.iss_uop.is_amo connect issue_slots[1].iss_uop.is_sfence, slots_1.io.iss_uop.is_sfence connect issue_slots[1].iss_uop.is_fencei, slots_1.io.iss_uop.is_fencei connect issue_slots[1].iss_uop.is_fence, slots_1.io.iss_uop.is_fence connect issue_slots[1].iss_uop.is_sfb, slots_1.io.iss_uop.is_sfb connect issue_slots[1].iss_uop.br_type, slots_1.io.iss_uop.br_type connect issue_slots[1].iss_uop.br_tag, slots_1.io.iss_uop.br_tag connect issue_slots[1].iss_uop.br_mask, slots_1.io.iss_uop.br_mask connect issue_slots[1].iss_uop.dis_col_sel, slots_1.io.iss_uop.dis_col_sel connect issue_slots[1].iss_uop.iw_p3_bypass_hint, slots_1.io.iss_uop.iw_p3_bypass_hint connect issue_slots[1].iss_uop.iw_p2_bypass_hint, slots_1.io.iss_uop.iw_p2_bypass_hint connect issue_slots[1].iss_uop.iw_p1_bypass_hint, slots_1.io.iss_uop.iw_p1_bypass_hint connect issue_slots[1].iss_uop.iw_p2_speculative_child, slots_1.io.iss_uop.iw_p2_speculative_child connect issue_slots[1].iss_uop.iw_p1_speculative_child, slots_1.io.iss_uop.iw_p1_speculative_child connect issue_slots[1].iss_uop.iw_issued_partial_dgen, slots_1.io.iss_uop.iw_issued_partial_dgen connect issue_slots[1].iss_uop.iw_issued_partial_agen, slots_1.io.iss_uop.iw_issued_partial_agen connect issue_slots[1].iss_uop.iw_issued, slots_1.io.iss_uop.iw_issued connect issue_slots[1].iss_uop.fu_code[0], slots_1.io.iss_uop.fu_code[0] connect issue_slots[1].iss_uop.fu_code[1], slots_1.io.iss_uop.fu_code[1] connect issue_slots[1].iss_uop.fu_code[2], slots_1.io.iss_uop.fu_code[2] connect issue_slots[1].iss_uop.fu_code[3], slots_1.io.iss_uop.fu_code[3] connect issue_slots[1].iss_uop.fu_code[4], slots_1.io.iss_uop.fu_code[4] connect issue_slots[1].iss_uop.fu_code[5], slots_1.io.iss_uop.fu_code[5] connect issue_slots[1].iss_uop.fu_code[6], slots_1.io.iss_uop.fu_code[6] connect issue_slots[1].iss_uop.fu_code[7], slots_1.io.iss_uop.fu_code[7] connect issue_slots[1].iss_uop.fu_code[8], slots_1.io.iss_uop.fu_code[8] connect issue_slots[1].iss_uop.fu_code[9], slots_1.io.iss_uop.fu_code[9] connect issue_slots[1].iss_uop.iq_type[0], slots_1.io.iss_uop.iq_type[0] connect issue_slots[1].iss_uop.iq_type[1], slots_1.io.iss_uop.iq_type[1] connect issue_slots[1].iss_uop.iq_type[2], slots_1.io.iss_uop.iq_type[2] connect issue_slots[1].iss_uop.iq_type[3], slots_1.io.iss_uop.iq_type[3] connect issue_slots[1].iss_uop.debug_pc, slots_1.io.iss_uop.debug_pc connect issue_slots[1].iss_uop.is_rvc, slots_1.io.iss_uop.is_rvc connect issue_slots[1].iss_uop.debug_inst, slots_1.io.iss_uop.debug_inst connect issue_slots[1].iss_uop.inst, slots_1.io.iss_uop.inst connect slots_1.io.grant, issue_slots[1].grant connect issue_slots[1].request, slots_1.io.request connect issue_slots[1].will_be_valid, slots_1.io.will_be_valid connect issue_slots[1].valid, slots_1.io.valid connect slots_2.io.child_rebusys, issue_slots[2].child_rebusys connect slots_2.io.pred_wakeup_port.bits, issue_slots[2].pred_wakeup_port.bits connect slots_2.io.pred_wakeup_port.valid, issue_slots[2].pred_wakeup_port.valid connect slots_2.io.wakeup_ports[0].bits.rebusy, issue_slots[2].wakeup_ports[0].bits.rebusy connect slots_2.io.wakeup_ports[0].bits.speculative_mask, issue_slots[2].wakeup_ports[0].bits.speculative_mask connect slots_2.io.wakeup_ports[0].bits.bypassable, issue_slots[2].wakeup_ports[0].bits.bypassable connect slots_2.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[2].wakeup_ports[0].bits.uop.debug_tsrc connect slots_2.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[2].wakeup_ports[0].bits.uop.debug_fsrc connect slots_2.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[2].wakeup_ports[0].bits.uop.bp_xcpt_if connect slots_2.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[2].wakeup_ports[0].bits.uop.bp_debug_if connect slots_2.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[2].wakeup_ports[0].bits.uop.xcpt_ma_if connect slots_2.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[2].wakeup_ports[0].bits.uop.xcpt_ae_if connect slots_2.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[2].wakeup_ports[0].bits.uop.xcpt_pf_if connect slots_2.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[2].wakeup_ports[0].bits.uop.fp_typ connect slots_2.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[2].wakeup_ports[0].bits.uop.fp_rm connect slots_2.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[2].wakeup_ports[0].bits.uop.fp_val connect slots_2.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[2].wakeup_ports[0].bits.uop.fcn_op connect slots_2.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[2].wakeup_ports[0].bits.uop.fcn_dw connect slots_2.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[2].wakeup_ports[0].bits.uop.frs3_en connect slots_2.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[2].wakeup_ports[0].bits.uop.lrs2_rtype connect slots_2.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[2].wakeup_ports[0].bits.uop.lrs1_rtype connect slots_2.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[2].wakeup_ports[0].bits.uop.dst_rtype connect slots_2.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[2].wakeup_ports[0].bits.uop.lrs3 connect slots_2.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[2].wakeup_ports[0].bits.uop.lrs2 connect slots_2.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[2].wakeup_ports[0].bits.uop.lrs1 connect slots_2.io.wakeup_ports[0].bits.uop.ldst, issue_slots[2].wakeup_ports[0].bits.uop.ldst connect slots_2.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[2].wakeup_ports[0].bits.uop.ldst_is_rs1 connect slots_2.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[2].wakeup_ports[0].bits.uop.csr_cmd connect slots_2.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[2].wakeup_ports[0].bits.uop.flush_on_commit connect slots_2.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[2].wakeup_ports[0].bits.uop.is_unique connect slots_2.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[2].wakeup_ports[0].bits.uop.uses_stq connect slots_2.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[2].wakeup_ports[0].bits.uop.uses_ldq connect slots_2.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[2].wakeup_ports[0].bits.uop.mem_signed connect slots_2.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[2].wakeup_ports[0].bits.uop.mem_size connect slots_2.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[2].wakeup_ports[0].bits.uop.mem_cmd connect slots_2.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[2].wakeup_ports[0].bits.uop.exc_cause connect slots_2.io.wakeup_ports[0].bits.uop.exception, issue_slots[2].wakeup_ports[0].bits.uop.exception connect slots_2.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[2].wakeup_ports[0].bits.uop.stale_pdst connect slots_2.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[2].wakeup_ports[0].bits.uop.ppred_busy connect slots_2.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[2].wakeup_ports[0].bits.uop.prs3_busy connect slots_2.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[2].wakeup_ports[0].bits.uop.prs2_busy connect slots_2.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[2].wakeup_ports[0].bits.uop.prs1_busy connect slots_2.io.wakeup_ports[0].bits.uop.ppred, issue_slots[2].wakeup_ports[0].bits.uop.ppred connect slots_2.io.wakeup_ports[0].bits.uop.prs3, issue_slots[2].wakeup_ports[0].bits.uop.prs3 connect slots_2.io.wakeup_ports[0].bits.uop.prs2, issue_slots[2].wakeup_ports[0].bits.uop.prs2 connect slots_2.io.wakeup_ports[0].bits.uop.prs1, issue_slots[2].wakeup_ports[0].bits.uop.prs1 connect slots_2.io.wakeup_ports[0].bits.uop.pdst, issue_slots[2].wakeup_ports[0].bits.uop.pdst connect slots_2.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[2].wakeup_ports[0].bits.uop.rxq_idx connect slots_2.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[2].wakeup_ports[0].bits.uop.stq_idx connect slots_2.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[2].wakeup_ports[0].bits.uop.ldq_idx connect slots_2.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[2].wakeup_ports[0].bits.uop.rob_idx connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.vec connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.wflags connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.div connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.fma connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.toint connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.fromint connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.wen connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.ldst connect slots_2.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[2].wakeup_ports[0].bits.uop.op2_sel connect slots_2.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[2].wakeup_ports[0].bits.uop.op1_sel connect slots_2.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[2].wakeup_ports[0].bits.uop.imm_packed connect slots_2.io.wakeup_ports[0].bits.uop.pimm, issue_slots[2].wakeup_ports[0].bits.uop.pimm connect slots_2.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[2].wakeup_ports[0].bits.uop.imm_sel connect slots_2.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[2].wakeup_ports[0].bits.uop.imm_rename connect slots_2.io.wakeup_ports[0].bits.uop.taken, issue_slots[2].wakeup_ports[0].bits.uop.taken connect slots_2.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[2].wakeup_ports[0].bits.uop.pc_lob connect slots_2.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[2].wakeup_ports[0].bits.uop.edge_inst connect slots_2.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[2].wakeup_ports[0].bits.uop.ftq_idx connect slots_2.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[2].wakeup_ports[0].bits.uop.is_mov connect slots_2.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[2].wakeup_ports[0].bits.uop.is_rocc connect slots_2.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[2].wakeup_ports[0].bits.uop.is_sys_pc2epc connect slots_2.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[2].wakeup_ports[0].bits.uop.is_eret connect slots_2.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[2].wakeup_ports[0].bits.uop.is_amo connect slots_2.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[2].wakeup_ports[0].bits.uop.is_sfence connect slots_2.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[2].wakeup_ports[0].bits.uop.is_fencei connect slots_2.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[2].wakeup_ports[0].bits.uop.is_fence connect slots_2.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[2].wakeup_ports[0].bits.uop.is_sfb connect slots_2.io.wakeup_ports[0].bits.uop.br_type, issue_slots[2].wakeup_ports[0].bits.uop.br_type connect slots_2.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[2].wakeup_ports[0].bits.uop.br_tag connect slots_2.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[2].wakeup_ports[0].bits.uop.br_mask connect slots_2.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[2].wakeup_ports[0].bits.uop.dis_col_sel connect slots_2.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[2].wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect slots_2.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[2].wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect slots_2.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[2].wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect slots_2.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[2].wakeup_ports[0].bits.uop.iw_p2_speculative_child connect slots_2.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[2].wakeup_ports[0].bits.uop.iw_p1_speculative_child connect slots_2.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[2].wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect slots_2.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[2].wakeup_ports[0].bits.uop.iw_issued_partial_agen connect slots_2.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[2].wakeup_ports[0].bits.uop.iw_issued connect slots_2.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[2].wakeup_ports[0].bits.uop.fu_code[0] connect slots_2.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[2].wakeup_ports[0].bits.uop.fu_code[1] connect slots_2.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[2].wakeup_ports[0].bits.uop.fu_code[2] connect slots_2.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[2].wakeup_ports[0].bits.uop.fu_code[3] connect slots_2.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[2].wakeup_ports[0].bits.uop.fu_code[4] connect slots_2.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[2].wakeup_ports[0].bits.uop.fu_code[5] connect slots_2.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[2].wakeup_ports[0].bits.uop.fu_code[6] connect slots_2.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[2].wakeup_ports[0].bits.uop.fu_code[7] connect slots_2.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[2].wakeup_ports[0].bits.uop.fu_code[8] connect slots_2.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[2].wakeup_ports[0].bits.uop.fu_code[9] connect slots_2.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[2].wakeup_ports[0].bits.uop.iq_type[0] connect slots_2.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[2].wakeup_ports[0].bits.uop.iq_type[1] connect slots_2.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[2].wakeup_ports[0].bits.uop.iq_type[2] connect slots_2.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[2].wakeup_ports[0].bits.uop.iq_type[3] connect slots_2.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[2].wakeup_ports[0].bits.uop.debug_pc connect slots_2.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[2].wakeup_ports[0].bits.uop.is_rvc connect slots_2.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[2].wakeup_ports[0].bits.uop.debug_inst connect slots_2.io.wakeup_ports[0].bits.uop.inst, issue_slots[2].wakeup_ports[0].bits.uop.inst connect slots_2.io.wakeup_ports[0].valid, issue_slots[2].wakeup_ports[0].valid connect slots_2.io.wakeup_ports[1].bits.rebusy, issue_slots[2].wakeup_ports[1].bits.rebusy connect slots_2.io.wakeup_ports[1].bits.speculative_mask, issue_slots[2].wakeup_ports[1].bits.speculative_mask connect slots_2.io.wakeup_ports[1].bits.bypassable, issue_slots[2].wakeup_ports[1].bits.bypassable connect slots_2.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[2].wakeup_ports[1].bits.uop.debug_tsrc connect slots_2.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[2].wakeup_ports[1].bits.uop.debug_fsrc connect slots_2.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[2].wakeup_ports[1].bits.uop.bp_xcpt_if connect slots_2.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[2].wakeup_ports[1].bits.uop.bp_debug_if connect slots_2.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[2].wakeup_ports[1].bits.uop.xcpt_ma_if connect slots_2.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[2].wakeup_ports[1].bits.uop.xcpt_ae_if connect slots_2.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[2].wakeup_ports[1].bits.uop.xcpt_pf_if connect slots_2.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[2].wakeup_ports[1].bits.uop.fp_typ connect slots_2.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[2].wakeup_ports[1].bits.uop.fp_rm connect slots_2.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[2].wakeup_ports[1].bits.uop.fp_val connect slots_2.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[2].wakeup_ports[1].bits.uop.fcn_op connect slots_2.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[2].wakeup_ports[1].bits.uop.fcn_dw connect slots_2.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[2].wakeup_ports[1].bits.uop.frs3_en connect slots_2.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[2].wakeup_ports[1].bits.uop.lrs2_rtype connect slots_2.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[2].wakeup_ports[1].bits.uop.lrs1_rtype connect slots_2.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[2].wakeup_ports[1].bits.uop.dst_rtype connect slots_2.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[2].wakeup_ports[1].bits.uop.lrs3 connect slots_2.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[2].wakeup_ports[1].bits.uop.lrs2 connect slots_2.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[2].wakeup_ports[1].bits.uop.lrs1 connect slots_2.io.wakeup_ports[1].bits.uop.ldst, issue_slots[2].wakeup_ports[1].bits.uop.ldst connect slots_2.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[2].wakeup_ports[1].bits.uop.ldst_is_rs1 connect slots_2.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[2].wakeup_ports[1].bits.uop.csr_cmd connect slots_2.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[2].wakeup_ports[1].bits.uop.flush_on_commit connect slots_2.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[2].wakeup_ports[1].bits.uop.is_unique connect slots_2.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[2].wakeup_ports[1].bits.uop.uses_stq connect slots_2.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[2].wakeup_ports[1].bits.uop.uses_ldq connect slots_2.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[2].wakeup_ports[1].bits.uop.mem_signed connect slots_2.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[2].wakeup_ports[1].bits.uop.mem_size connect slots_2.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[2].wakeup_ports[1].bits.uop.mem_cmd connect slots_2.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[2].wakeup_ports[1].bits.uop.exc_cause connect slots_2.io.wakeup_ports[1].bits.uop.exception, issue_slots[2].wakeup_ports[1].bits.uop.exception connect slots_2.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[2].wakeup_ports[1].bits.uop.stale_pdst connect slots_2.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[2].wakeup_ports[1].bits.uop.ppred_busy connect slots_2.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[2].wakeup_ports[1].bits.uop.prs3_busy connect slots_2.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[2].wakeup_ports[1].bits.uop.prs2_busy connect slots_2.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[2].wakeup_ports[1].bits.uop.prs1_busy connect slots_2.io.wakeup_ports[1].bits.uop.ppred, issue_slots[2].wakeup_ports[1].bits.uop.ppred connect slots_2.io.wakeup_ports[1].bits.uop.prs3, issue_slots[2].wakeup_ports[1].bits.uop.prs3 connect slots_2.io.wakeup_ports[1].bits.uop.prs2, issue_slots[2].wakeup_ports[1].bits.uop.prs2 connect slots_2.io.wakeup_ports[1].bits.uop.prs1, issue_slots[2].wakeup_ports[1].bits.uop.prs1 connect slots_2.io.wakeup_ports[1].bits.uop.pdst, issue_slots[2].wakeup_ports[1].bits.uop.pdst connect slots_2.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[2].wakeup_ports[1].bits.uop.rxq_idx connect slots_2.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[2].wakeup_ports[1].bits.uop.stq_idx connect slots_2.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[2].wakeup_ports[1].bits.uop.ldq_idx connect slots_2.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[2].wakeup_ports[1].bits.uop.rob_idx connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.vec connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.wflags connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.div connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.fma connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.toint connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.fromint connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.wen connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.ldst connect slots_2.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[2].wakeup_ports[1].bits.uop.op2_sel connect slots_2.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[2].wakeup_ports[1].bits.uop.op1_sel connect slots_2.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[2].wakeup_ports[1].bits.uop.imm_packed connect slots_2.io.wakeup_ports[1].bits.uop.pimm, issue_slots[2].wakeup_ports[1].bits.uop.pimm connect slots_2.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[2].wakeup_ports[1].bits.uop.imm_sel connect slots_2.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[2].wakeup_ports[1].bits.uop.imm_rename connect slots_2.io.wakeup_ports[1].bits.uop.taken, issue_slots[2].wakeup_ports[1].bits.uop.taken connect slots_2.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[2].wakeup_ports[1].bits.uop.pc_lob connect slots_2.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[2].wakeup_ports[1].bits.uop.edge_inst connect slots_2.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[2].wakeup_ports[1].bits.uop.ftq_idx connect slots_2.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[2].wakeup_ports[1].bits.uop.is_mov connect slots_2.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[2].wakeup_ports[1].bits.uop.is_rocc connect slots_2.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[2].wakeup_ports[1].bits.uop.is_sys_pc2epc connect slots_2.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[2].wakeup_ports[1].bits.uop.is_eret connect slots_2.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[2].wakeup_ports[1].bits.uop.is_amo connect slots_2.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[2].wakeup_ports[1].bits.uop.is_sfence connect slots_2.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[2].wakeup_ports[1].bits.uop.is_fencei connect slots_2.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[2].wakeup_ports[1].bits.uop.is_fence connect slots_2.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[2].wakeup_ports[1].bits.uop.is_sfb connect slots_2.io.wakeup_ports[1].bits.uop.br_type, issue_slots[2].wakeup_ports[1].bits.uop.br_type connect slots_2.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[2].wakeup_ports[1].bits.uop.br_tag connect slots_2.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[2].wakeup_ports[1].bits.uop.br_mask connect slots_2.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[2].wakeup_ports[1].bits.uop.dis_col_sel connect slots_2.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[2].wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect slots_2.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[2].wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect slots_2.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[2].wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect slots_2.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[2].wakeup_ports[1].bits.uop.iw_p2_speculative_child connect slots_2.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[2].wakeup_ports[1].bits.uop.iw_p1_speculative_child connect slots_2.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[2].wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect slots_2.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[2].wakeup_ports[1].bits.uop.iw_issued_partial_agen connect slots_2.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[2].wakeup_ports[1].bits.uop.iw_issued connect slots_2.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[2].wakeup_ports[1].bits.uop.fu_code[0] connect slots_2.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[2].wakeup_ports[1].bits.uop.fu_code[1] connect slots_2.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[2].wakeup_ports[1].bits.uop.fu_code[2] connect slots_2.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[2].wakeup_ports[1].bits.uop.fu_code[3] connect slots_2.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[2].wakeup_ports[1].bits.uop.fu_code[4] connect slots_2.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[2].wakeup_ports[1].bits.uop.fu_code[5] connect slots_2.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[2].wakeup_ports[1].bits.uop.fu_code[6] connect slots_2.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[2].wakeup_ports[1].bits.uop.fu_code[7] connect slots_2.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[2].wakeup_ports[1].bits.uop.fu_code[8] connect slots_2.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[2].wakeup_ports[1].bits.uop.fu_code[9] connect slots_2.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[2].wakeup_ports[1].bits.uop.iq_type[0] connect slots_2.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[2].wakeup_ports[1].bits.uop.iq_type[1] connect slots_2.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[2].wakeup_ports[1].bits.uop.iq_type[2] connect slots_2.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[2].wakeup_ports[1].bits.uop.iq_type[3] connect slots_2.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[2].wakeup_ports[1].bits.uop.debug_pc connect slots_2.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[2].wakeup_ports[1].bits.uop.is_rvc connect slots_2.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[2].wakeup_ports[1].bits.uop.debug_inst connect slots_2.io.wakeup_ports[1].bits.uop.inst, issue_slots[2].wakeup_ports[1].bits.uop.inst connect slots_2.io.wakeup_ports[1].valid, issue_slots[2].wakeup_ports[1].valid connect slots_2.io.wakeup_ports[2].bits.rebusy, issue_slots[2].wakeup_ports[2].bits.rebusy connect slots_2.io.wakeup_ports[2].bits.speculative_mask, issue_slots[2].wakeup_ports[2].bits.speculative_mask connect slots_2.io.wakeup_ports[2].bits.bypassable, issue_slots[2].wakeup_ports[2].bits.bypassable connect slots_2.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[2].wakeup_ports[2].bits.uop.debug_tsrc connect slots_2.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[2].wakeup_ports[2].bits.uop.debug_fsrc connect slots_2.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[2].wakeup_ports[2].bits.uop.bp_xcpt_if connect slots_2.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[2].wakeup_ports[2].bits.uop.bp_debug_if connect slots_2.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[2].wakeup_ports[2].bits.uop.xcpt_ma_if connect slots_2.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[2].wakeup_ports[2].bits.uop.xcpt_ae_if connect slots_2.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[2].wakeup_ports[2].bits.uop.xcpt_pf_if connect slots_2.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[2].wakeup_ports[2].bits.uop.fp_typ connect slots_2.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[2].wakeup_ports[2].bits.uop.fp_rm connect slots_2.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[2].wakeup_ports[2].bits.uop.fp_val connect slots_2.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[2].wakeup_ports[2].bits.uop.fcn_op connect slots_2.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[2].wakeup_ports[2].bits.uop.fcn_dw connect slots_2.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[2].wakeup_ports[2].bits.uop.frs3_en connect slots_2.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[2].wakeup_ports[2].bits.uop.lrs2_rtype connect slots_2.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[2].wakeup_ports[2].bits.uop.lrs1_rtype connect slots_2.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[2].wakeup_ports[2].bits.uop.dst_rtype connect slots_2.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[2].wakeup_ports[2].bits.uop.lrs3 connect slots_2.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[2].wakeup_ports[2].bits.uop.lrs2 connect slots_2.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[2].wakeup_ports[2].bits.uop.lrs1 connect slots_2.io.wakeup_ports[2].bits.uop.ldst, issue_slots[2].wakeup_ports[2].bits.uop.ldst connect slots_2.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[2].wakeup_ports[2].bits.uop.ldst_is_rs1 connect slots_2.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[2].wakeup_ports[2].bits.uop.csr_cmd connect slots_2.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[2].wakeup_ports[2].bits.uop.flush_on_commit connect slots_2.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[2].wakeup_ports[2].bits.uop.is_unique connect slots_2.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[2].wakeup_ports[2].bits.uop.uses_stq connect slots_2.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[2].wakeup_ports[2].bits.uop.uses_ldq connect slots_2.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[2].wakeup_ports[2].bits.uop.mem_signed connect slots_2.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[2].wakeup_ports[2].bits.uop.mem_size connect slots_2.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[2].wakeup_ports[2].bits.uop.mem_cmd connect slots_2.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[2].wakeup_ports[2].bits.uop.exc_cause connect slots_2.io.wakeup_ports[2].bits.uop.exception, issue_slots[2].wakeup_ports[2].bits.uop.exception connect slots_2.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[2].wakeup_ports[2].bits.uop.stale_pdst connect slots_2.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[2].wakeup_ports[2].bits.uop.ppred_busy connect slots_2.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[2].wakeup_ports[2].bits.uop.prs3_busy connect slots_2.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[2].wakeup_ports[2].bits.uop.prs2_busy connect slots_2.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[2].wakeup_ports[2].bits.uop.prs1_busy connect slots_2.io.wakeup_ports[2].bits.uop.ppred, issue_slots[2].wakeup_ports[2].bits.uop.ppred connect slots_2.io.wakeup_ports[2].bits.uop.prs3, issue_slots[2].wakeup_ports[2].bits.uop.prs3 connect slots_2.io.wakeup_ports[2].bits.uop.prs2, issue_slots[2].wakeup_ports[2].bits.uop.prs2 connect slots_2.io.wakeup_ports[2].bits.uop.prs1, issue_slots[2].wakeup_ports[2].bits.uop.prs1 connect slots_2.io.wakeup_ports[2].bits.uop.pdst, issue_slots[2].wakeup_ports[2].bits.uop.pdst connect slots_2.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[2].wakeup_ports[2].bits.uop.rxq_idx connect slots_2.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[2].wakeup_ports[2].bits.uop.stq_idx connect slots_2.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[2].wakeup_ports[2].bits.uop.ldq_idx connect slots_2.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[2].wakeup_ports[2].bits.uop.rob_idx connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.vec connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.wflags connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.div connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.fma connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.toint connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.fromint connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.wen connect slots_2.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.ldst connect slots_2.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[2].wakeup_ports[2].bits.uop.op2_sel connect slots_2.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[2].wakeup_ports[2].bits.uop.op1_sel connect slots_2.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[2].wakeup_ports[2].bits.uop.imm_packed connect slots_2.io.wakeup_ports[2].bits.uop.pimm, issue_slots[2].wakeup_ports[2].bits.uop.pimm connect slots_2.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[2].wakeup_ports[2].bits.uop.imm_sel connect slots_2.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[2].wakeup_ports[2].bits.uop.imm_rename connect slots_2.io.wakeup_ports[2].bits.uop.taken, issue_slots[2].wakeup_ports[2].bits.uop.taken connect slots_2.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[2].wakeup_ports[2].bits.uop.pc_lob connect slots_2.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[2].wakeup_ports[2].bits.uop.edge_inst connect slots_2.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[2].wakeup_ports[2].bits.uop.ftq_idx connect slots_2.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[2].wakeup_ports[2].bits.uop.is_mov connect slots_2.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[2].wakeup_ports[2].bits.uop.is_rocc connect slots_2.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[2].wakeup_ports[2].bits.uop.is_sys_pc2epc connect slots_2.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[2].wakeup_ports[2].bits.uop.is_eret connect slots_2.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[2].wakeup_ports[2].bits.uop.is_amo connect slots_2.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[2].wakeup_ports[2].bits.uop.is_sfence connect slots_2.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[2].wakeup_ports[2].bits.uop.is_fencei connect slots_2.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[2].wakeup_ports[2].bits.uop.is_fence connect slots_2.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[2].wakeup_ports[2].bits.uop.is_sfb connect slots_2.io.wakeup_ports[2].bits.uop.br_type, issue_slots[2].wakeup_ports[2].bits.uop.br_type connect slots_2.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[2].wakeup_ports[2].bits.uop.br_tag connect slots_2.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[2].wakeup_ports[2].bits.uop.br_mask connect slots_2.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[2].wakeup_ports[2].bits.uop.dis_col_sel connect slots_2.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[2].wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect slots_2.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[2].wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect slots_2.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[2].wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect slots_2.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[2].wakeup_ports[2].bits.uop.iw_p2_speculative_child connect slots_2.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[2].wakeup_ports[2].bits.uop.iw_p1_speculative_child connect slots_2.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[2].wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect slots_2.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[2].wakeup_ports[2].bits.uop.iw_issued_partial_agen connect slots_2.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[2].wakeup_ports[2].bits.uop.iw_issued connect slots_2.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[2].wakeup_ports[2].bits.uop.fu_code[0] connect slots_2.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[2].wakeup_ports[2].bits.uop.fu_code[1] connect slots_2.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[2].wakeup_ports[2].bits.uop.fu_code[2] connect slots_2.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[2].wakeup_ports[2].bits.uop.fu_code[3] connect slots_2.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[2].wakeup_ports[2].bits.uop.fu_code[4] connect slots_2.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[2].wakeup_ports[2].bits.uop.fu_code[5] connect slots_2.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[2].wakeup_ports[2].bits.uop.fu_code[6] connect slots_2.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[2].wakeup_ports[2].bits.uop.fu_code[7] connect slots_2.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[2].wakeup_ports[2].bits.uop.fu_code[8] connect slots_2.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[2].wakeup_ports[2].bits.uop.fu_code[9] connect slots_2.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[2].wakeup_ports[2].bits.uop.iq_type[0] connect slots_2.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[2].wakeup_ports[2].bits.uop.iq_type[1] connect slots_2.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[2].wakeup_ports[2].bits.uop.iq_type[2] connect slots_2.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[2].wakeup_ports[2].bits.uop.iq_type[3] connect slots_2.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[2].wakeup_ports[2].bits.uop.debug_pc connect slots_2.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[2].wakeup_ports[2].bits.uop.is_rvc connect slots_2.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[2].wakeup_ports[2].bits.uop.debug_inst connect slots_2.io.wakeup_ports[2].bits.uop.inst, issue_slots[2].wakeup_ports[2].bits.uop.inst connect slots_2.io.wakeup_ports[2].valid, issue_slots[2].wakeup_ports[2].valid connect slots_2.io.wakeup_ports[3].bits.rebusy, issue_slots[2].wakeup_ports[3].bits.rebusy connect slots_2.io.wakeup_ports[3].bits.speculative_mask, issue_slots[2].wakeup_ports[3].bits.speculative_mask connect slots_2.io.wakeup_ports[3].bits.bypassable, issue_slots[2].wakeup_ports[3].bits.bypassable connect slots_2.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[2].wakeup_ports[3].bits.uop.debug_tsrc connect slots_2.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[2].wakeup_ports[3].bits.uop.debug_fsrc connect slots_2.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[2].wakeup_ports[3].bits.uop.bp_xcpt_if connect slots_2.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[2].wakeup_ports[3].bits.uop.bp_debug_if connect slots_2.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[2].wakeup_ports[3].bits.uop.xcpt_ma_if connect slots_2.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[2].wakeup_ports[3].bits.uop.xcpt_ae_if connect slots_2.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[2].wakeup_ports[3].bits.uop.xcpt_pf_if connect slots_2.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[2].wakeup_ports[3].bits.uop.fp_typ connect slots_2.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[2].wakeup_ports[3].bits.uop.fp_rm connect slots_2.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[2].wakeup_ports[3].bits.uop.fp_val connect slots_2.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[2].wakeup_ports[3].bits.uop.fcn_op connect slots_2.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[2].wakeup_ports[3].bits.uop.fcn_dw connect slots_2.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[2].wakeup_ports[3].bits.uop.frs3_en connect slots_2.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[2].wakeup_ports[3].bits.uop.lrs2_rtype connect slots_2.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[2].wakeup_ports[3].bits.uop.lrs1_rtype connect slots_2.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[2].wakeup_ports[3].bits.uop.dst_rtype connect slots_2.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[2].wakeup_ports[3].bits.uop.lrs3 connect slots_2.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[2].wakeup_ports[3].bits.uop.lrs2 connect slots_2.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[2].wakeup_ports[3].bits.uop.lrs1 connect slots_2.io.wakeup_ports[3].bits.uop.ldst, issue_slots[2].wakeup_ports[3].bits.uop.ldst connect slots_2.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[2].wakeup_ports[3].bits.uop.ldst_is_rs1 connect slots_2.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[2].wakeup_ports[3].bits.uop.csr_cmd connect slots_2.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[2].wakeup_ports[3].bits.uop.flush_on_commit connect slots_2.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[2].wakeup_ports[3].bits.uop.is_unique connect slots_2.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[2].wakeup_ports[3].bits.uop.uses_stq connect slots_2.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[2].wakeup_ports[3].bits.uop.uses_ldq connect slots_2.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[2].wakeup_ports[3].bits.uop.mem_signed connect slots_2.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[2].wakeup_ports[3].bits.uop.mem_size connect slots_2.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[2].wakeup_ports[3].bits.uop.mem_cmd connect slots_2.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[2].wakeup_ports[3].bits.uop.exc_cause connect slots_2.io.wakeup_ports[3].bits.uop.exception, issue_slots[2].wakeup_ports[3].bits.uop.exception connect slots_2.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[2].wakeup_ports[3].bits.uop.stale_pdst connect slots_2.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[2].wakeup_ports[3].bits.uop.ppred_busy connect slots_2.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[2].wakeup_ports[3].bits.uop.prs3_busy connect slots_2.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[2].wakeup_ports[3].bits.uop.prs2_busy connect slots_2.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[2].wakeup_ports[3].bits.uop.prs1_busy connect slots_2.io.wakeup_ports[3].bits.uop.ppred, issue_slots[2].wakeup_ports[3].bits.uop.ppred connect slots_2.io.wakeup_ports[3].bits.uop.prs3, issue_slots[2].wakeup_ports[3].bits.uop.prs3 connect slots_2.io.wakeup_ports[3].bits.uop.prs2, issue_slots[2].wakeup_ports[3].bits.uop.prs2 connect slots_2.io.wakeup_ports[3].bits.uop.prs1, issue_slots[2].wakeup_ports[3].bits.uop.prs1 connect slots_2.io.wakeup_ports[3].bits.uop.pdst, issue_slots[2].wakeup_ports[3].bits.uop.pdst connect slots_2.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[2].wakeup_ports[3].bits.uop.rxq_idx connect slots_2.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[2].wakeup_ports[3].bits.uop.stq_idx connect slots_2.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[2].wakeup_ports[3].bits.uop.ldq_idx connect slots_2.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[2].wakeup_ports[3].bits.uop.rob_idx connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.vec connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.wflags connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.div connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.fma connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.toint connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.fromint connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.wen connect slots_2.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.ldst connect slots_2.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[2].wakeup_ports[3].bits.uop.op2_sel connect slots_2.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[2].wakeup_ports[3].bits.uop.op1_sel connect slots_2.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[2].wakeup_ports[3].bits.uop.imm_packed connect slots_2.io.wakeup_ports[3].bits.uop.pimm, issue_slots[2].wakeup_ports[3].bits.uop.pimm connect slots_2.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[2].wakeup_ports[3].bits.uop.imm_sel connect slots_2.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[2].wakeup_ports[3].bits.uop.imm_rename connect slots_2.io.wakeup_ports[3].bits.uop.taken, issue_slots[2].wakeup_ports[3].bits.uop.taken connect slots_2.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[2].wakeup_ports[3].bits.uop.pc_lob connect slots_2.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[2].wakeup_ports[3].bits.uop.edge_inst connect slots_2.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[2].wakeup_ports[3].bits.uop.ftq_idx connect slots_2.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[2].wakeup_ports[3].bits.uop.is_mov connect slots_2.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[2].wakeup_ports[3].bits.uop.is_rocc connect slots_2.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[2].wakeup_ports[3].bits.uop.is_sys_pc2epc connect slots_2.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[2].wakeup_ports[3].bits.uop.is_eret connect slots_2.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[2].wakeup_ports[3].bits.uop.is_amo connect slots_2.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[2].wakeup_ports[3].bits.uop.is_sfence connect slots_2.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[2].wakeup_ports[3].bits.uop.is_fencei connect slots_2.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[2].wakeup_ports[3].bits.uop.is_fence connect slots_2.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[2].wakeup_ports[3].bits.uop.is_sfb connect slots_2.io.wakeup_ports[3].bits.uop.br_type, issue_slots[2].wakeup_ports[3].bits.uop.br_type connect slots_2.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[2].wakeup_ports[3].bits.uop.br_tag connect slots_2.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[2].wakeup_ports[3].bits.uop.br_mask connect slots_2.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[2].wakeup_ports[3].bits.uop.dis_col_sel connect slots_2.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[2].wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect slots_2.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[2].wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect slots_2.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[2].wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect slots_2.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[2].wakeup_ports[3].bits.uop.iw_p2_speculative_child connect slots_2.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[2].wakeup_ports[3].bits.uop.iw_p1_speculative_child connect slots_2.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[2].wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect slots_2.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[2].wakeup_ports[3].bits.uop.iw_issued_partial_agen connect slots_2.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[2].wakeup_ports[3].bits.uop.iw_issued connect slots_2.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[2].wakeup_ports[3].bits.uop.fu_code[0] connect slots_2.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[2].wakeup_ports[3].bits.uop.fu_code[1] connect slots_2.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[2].wakeup_ports[3].bits.uop.fu_code[2] connect slots_2.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[2].wakeup_ports[3].bits.uop.fu_code[3] connect slots_2.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[2].wakeup_ports[3].bits.uop.fu_code[4] connect slots_2.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[2].wakeup_ports[3].bits.uop.fu_code[5] connect slots_2.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[2].wakeup_ports[3].bits.uop.fu_code[6] connect slots_2.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[2].wakeup_ports[3].bits.uop.fu_code[7] connect slots_2.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[2].wakeup_ports[3].bits.uop.fu_code[8] connect slots_2.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[2].wakeup_ports[3].bits.uop.fu_code[9] connect slots_2.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[2].wakeup_ports[3].bits.uop.iq_type[0] connect slots_2.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[2].wakeup_ports[3].bits.uop.iq_type[1] connect slots_2.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[2].wakeup_ports[3].bits.uop.iq_type[2] connect slots_2.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[2].wakeup_ports[3].bits.uop.iq_type[3] connect slots_2.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[2].wakeup_ports[3].bits.uop.debug_pc connect slots_2.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[2].wakeup_ports[3].bits.uop.is_rvc connect slots_2.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[2].wakeup_ports[3].bits.uop.debug_inst connect slots_2.io.wakeup_ports[3].bits.uop.inst, issue_slots[2].wakeup_ports[3].bits.uop.inst connect slots_2.io.wakeup_ports[3].valid, issue_slots[2].wakeup_ports[3].valid connect slots_2.io.wakeup_ports[4].bits.rebusy, issue_slots[2].wakeup_ports[4].bits.rebusy connect slots_2.io.wakeup_ports[4].bits.speculative_mask, issue_slots[2].wakeup_ports[4].bits.speculative_mask connect slots_2.io.wakeup_ports[4].bits.bypassable, issue_slots[2].wakeup_ports[4].bits.bypassable connect slots_2.io.wakeup_ports[4].bits.uop.debug_tsrc, issue_slots[2].wakeup_ports[4].bits.uop.debug_tsrc connect slots_2.io.wakeup_ports[4].bits.uop.debug_fsrc, issue_slots[2].wakeup_ports[4].bits.uop.debug_fsrc connect slots_2.io.wakeup_ports[4].bits.uop.bp_xcpt_if, issue_slots[2].wakeup_ports[4].bits.uop.bp_xcpt_if connect slots_2.io.wakeup_ports[4].bits.uop.bp_debug_if, issue_slots[2].wakeup_ports[4].bits.uop.bp_debug_if connect slots_2.io.wakeup_ports[4].bits.uop.xcpt_ma_if, issue_slots[2].wakeup_ports[4].bits.uop.xcpt_ma_if connect slots_2.io.wakeup_ports[4].bits.uop.xcpt_ae_if, issue_slots[2].wakeup_ports[4].bits.uop.xcpt_ae_if connect slots_2.io.wakeup_ports[4].bits.uop.xcpt_pf_if, issue_slots[2].wakeup_ports[4].bits.uop.xcpt_pf_if connect slots_2.io.wakeup_ports[4].bits.uop.fp_typ, issue_slots[2].wakeup_ports[4].bits.uop.fp_typ connect slots_2.io.wakeup_ports[4].bits.uop.fp_rm, issue_slots[2].wakeup_ports[4].bits.uop.fp_rm connect slots_2.io.wakeup_ports[4].bits.uop.fp_val, issue_slots[2].wakeup_ports[4].bits.uop.fp_val connect slots_2.io.wakeup_ports[4].bits.uop.fcn_op, issue_slots[2].wakeup_ports[4].bits.uop.fcn_op connect slots_2.io.wakeup_ports[4].bits.uop.fcn_dw, issue_slots[2].wakeup_ports[4].bits.uop.fcn_dw connect slots_2.io.wakeup_ports[4].bits.uop.frs3_en, issue_slots[2].wakeup_ports[4].bits.uop.frs3_en connect slots_2.io.wakeup_ports[4].bits.uop.lrs2_rtype, issue_slots[2].wakeup_ports[4].bits.uop.lrs2_rtype connect slots_2.io.wakeup_ports[4].bits.uop.lrs1_rtype, issue_slots[2].wakeup_ports[4].bits.uop.lrs1_rtype connect slots_2.io.wakeup_ports[4].bits.uop.dst_rtype, issue_slots[2].wakeup_ports[4].bits.uop.dst_rtype connect slots_2.io.wakeup_ports[4].bits.uop.lrs3, issue_slots[2].wakeup_ports[4].bits.uop.lrs3 connect slots_2.io.wakeup_ports[4].bits.uop.lrs2, issue_slots[2].wakeup_ports[4].bits.uop.lrs2 connect slots_2.io.wakeup_ports[4].bits.uop.lrs1, issue_slots[2].wakeup_ports[4].bits.uop.lrs1 connect slots_2.io.wakeup_ports[4].bits.uop.ldst, issue_slots[2].wakeup_ports[4].bits.uop.ldst connect slots_2.io.wakeup_ports[4].bits.uop.ldst_is_rs1, issue_slots[2].wakeup_ports[4].bits.uop.ldst_is_rs1 connect slots_2.io.wakeup_ports[4].bits.uop.csr_cmd, issue_slots[2].wakeup_ports[4].bits.uop.csr_cmd connect slots_2.io.wakeup_ports[4].bits.uop.flush_on_commit, issue_slots[2].wakeup_ports[4].bits.uop.flush_on_commit connect slots_2.io.wakeup_ports[4].bits.uop.is_unique, issue_slots[2].wakeup_ports[4].bits.uop.is_unique connect slots_2.io.wakeup_ports[4].bits.uop.uses_stq, issue_slots[2].wakeup_ports[4].bits.uop.uses_stq connect slots_2.io.wakeup_ports[4].bits.uop.uses_ldq, issue_slots[2].wakeup_ports[4].bits.uop.uses_ldq connect slots_2.io.wakeup_ports[4].bits.uop.mem_signed, issue_slots[2].wakeup_ports[4].bits.uop.mem_signed connect slots_2.io.wakeup_ports[4].bits.uop.mem_size, issue_slots[2].wakeup_ports[4].bits.uop.mem_size connect slots_2.io.wakeup_ports[4].bits.uop.mem_cmd, issue_slots[2].wakeup_ports[4].bits.uop.mem_cmd connect slots_2.io.wakeup_ports[4].bits.uop.exc_cause, issue_slots[2].wakeup_ports[4].bits.uop.exc_cause connect slots_2.io.wakeup_ports[4].bits.uop.exception, issue_slots[2].wakeup_ports[4].bits.uop.exception connect slots_2.io.wakeup_ports[4].bits.uop.stale_pdst, issue_slots[2].wakeup_ports[4].bits.uop.stale_pdst connect slots_2.io.wakeup_ports[4].bits.uop.ppred_busy, issue_slots[2].wakeup_ports[4].bits.uop.ppred_busy connect slots_2.io.wakeup_ports[4].bits.uop.prs3_busy, issue_slots[2].wakeup_ports[4].bits.uop.prs3_busy connect slots_2.io.wakeup_ports[4].bits.uop.prs2_busy, issue_slots[2].wakeup_ports[4].bits.uop.prs2_busy connect slots_2.io.wakeup_ports[4].bits.uop.prs1_busy, issue_slots[2].wakeup_ports[4].bits.uop.prs1_busy connect slots_2.io.wakeup_ports[4].bits.uop.ppred, issue_slots[2].wakeup_ports[4].bits.uop.ppred connect slots_2.io.wakeup_ports[4].bits.uop.prs3, issue_slots[2].wakeup_ports[4].bits.uop.prs3 connect slots_2.io.wakeup_ports[4].bits.uop.prs2, issue_slots[2].wakeup_ports[4].bits.uop.prs2 connect slots_2.io.wakeup_ports[4].bits.uop.prs1, issue_slots[2].wakeup_ports[4].bits.uop.prs1 connect slots_2.io.wakeup_ports[4].bits.uop.pdst, issue_slots[2].wakeup_ports[4].bits.uop.pdst connect slots_2.io.wakeup_ports[4].bits.uop.rxq_idx, issue_slots[2].wakeup_ports[4].bits.uop.rxq_idx connect slots_2.io.wakeup_ports[4].bits.uop.stq_idx, issue_slots[2].wakeup_ports[4].bits.uop.stq_idx connect slots_2.io.wakeup_ports[4].bits.uop.ldq_idx, issue_slots[2].wakeup_ports[4].bits.uop.ldq_idx connect slots_2.io.wakeup_ports[4].bits.uop.rob_idx, issue_slots[2].wakeup_ports[4].bits.uop.rob_idx connect slots_2.io.wakeup_ports[4].bits.uop.fp_ctrl.vec, issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.vec connect slots_2.io.wakeup_ports[4].bits.uop.fp_ctrl.wflags, issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.wflags connect slots_2.io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt, issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect slots_2.io.wakeup_ports[4].bits.uop.fp_ctrl.div, issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.div connect slots_2.io.wakeup_ports[4].bits.uop.fp_ctrl.fma, issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.fma connect slots_2.io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect slots_2.io.wakeup_ports[4].bits.uop.fp_ctrl.toint, issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.toint connect slots_2.io.wakeup_ports[4].bits.uop.fp_ctrl.fromint, issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.fromint connect slots_2.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect slots_2.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect slots_2.io.wakeup_ports[4].bits.uop.fp_ctrl.swap23, issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect slots_2.io.wakeup_ports[4].bits.uop.fp_ctrl.swap12, issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect slots_2.io.wakeup_ports[4].bits.uop.fp_ctrl.ren3, issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect slots_2.io.wakeup_ports[4].bits.uop.fp_ctrl.ren2, issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect slots_2.io.wakeup_ports[4].bits.uop.fp_ctrl.ren1, issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect slots_2.io.wakeup_ports[4].bits.uop.fp_ctrl.wen, issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.wen connect slots_2.io.wakeup_ports[4].bits.uop.fp_ctrl.ldst, issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.ldst connect slots_2.io.wakeup_ports[4].bits.uop.op2_sel, issue_slots[2].wakeup_ports[4].bits.uop.op2_sel connect slots_2.io.wakeup_ports[4].bits.uop.op1_sel, issue_slots[2].wakeup_ports[4].bits.uop.op1_sel connect slots_2.io.wakeup_ports[4].bits.uop.imm_packed, issue_slots[2].wakeup_ports[4].bits.uop.imm_packed connect slots_2.io.wakeup_ports[4].bits.uop.pimm, issue_slots[2].wakeup_ports[4].bits.uop.pimm connect slots_2.io.wakeup_ports[4].bits.uop.imm_sel, issue_slots[2].wakeup_ports[4].bits.uop.imm_sel connect slots_2.io.wakeup_ports[4].bits.uop.imm_rename, issue_slots[2].wakeup_ports[4].bits.uop.imm_rename connect slots_2.io.wakeup_ports[4].bits.uop.taken, issue_slots[2].wakeup_ports[4].bits.uop.taken connect slots_2.io.wakeup_ports[4].bits.uop.pc_lob, issue_slots[2].wakeup_ports[4].bits.uop.pc_lob connect slots_2.io.wakeup_ports[4].bits.uop.edge_inst, issue_slots[2].wakeup_ports[4].bits.uop.edge_inst connect slots_2.io.wakeup_ports[4].bits.uop.ftq_idx, issue_slots[2].wakeup_ports[4].bits.uop.ftq_idx connect slots_2.io.wakeup_ports[4].bits.uop.is_mov, issue_slots[2].wakeup_ports[4].bits.uop.is_mov connect slots_2.io.wakeup_ports[4].bits.uop.is_rocc, issue_slots[2].wakeup_ports[4].bits.uop.is_rocc connect slots_2.io.wakeup_ports[4].bits.uop.is_sys_pc2epc, issue_slots[2].wakeup_ports[4].bits.uop.is_sys_pc2epc connect slots_2.io.wakeup_ports[4].bits.uop.is_eret, issue_slots[2].wakeup_ports[4].bits.uop.is_eret connect slots_2.io.wakeup_ports[4].bits.uop.is_amo, issue_slots[2].wakeup_ports[4].bits.uop.is_amo connect slots_2.io.wakeup_ports[4].bits.uop.is_sfence, issue_slots[2].wakeup_ports[4].bits.uop.is_sfence connect slots_2.io.wakeup_ports[4].bits.uop.is_fencei, issue_slots[2].wakeup_ports[4].bits.uop.is_fencei connect slots_2.io.wakeup_ports[4].bits.uop.is_fence, issue_slots[2].wakeup_ports[4].bits.uop.is_fence connect slots_2.io.wakeup_ports[4].bits.uop.is_sfb, issue_slots[2].wakeup_ports[4].bits.uop.is_sfb connect slots_2.io.wakeup_ports[4].bits.uop.br_type, issue_slots[2].wakeup_ports[4].bits.uop.br_type connect slots_2.io.wakeup_ports[4].bits.uop.br_tag, issue_slots[2].wakeup_ports[4].bits.uop.br_tag connect slots_2.io.wakeup_ports[4].bits.uop.br_mask, issue_slots[2].wakeup_ports[4].bits.uop.br_mask connect slots_2.io.wakeup_ports[4].bits.uop.dis_col_sel, issue_slots[2].wakeup_ports[4].bits.uop.dis_col_sel connect slots_2.io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint, issue_slots[2].wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect slots_2.io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint, issue_slots[2].wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect slots_2.io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint, issue_slots[2].wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect slots_2.io.wakeup_ports[4].bits.uop.iw_p2_speculative_child, issue_slots[2].wakeup_ports[4].bits.uop.iw_p2_speculative_child connect slots_2.io.wakeup_ports[4].bits.uop.iw_p1_speculative_child, issue_slots[2].wakeup_ports[4].bits.uop.iw_p1_speculative_child connect slots_2.io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen, issue_slots[2].wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect slots_2.io.wakeup_ports[4].bits.uop.iw_issued_partial_agen, issue_slots[2].wakeup_ports[4].bits.uop.iw_issued_partial_agen connect slots_2.io.wakeup_ports[4].bits.uop.iw_issued, issue_slots[2].wakeup_ports[4].bits.uop.iw_issued connect slots_2.io.wakeup_ports[4].bits.uop.fu_code[0], issue_slots[2].wakeup_ports[4].bits.uop.fu_code[0] connect slots_2.io.wakeup_ports[4].bits.uop.fu_code[1], issue_slots[2].wakeup_ports[4].bits.uop.fu_code[1] connect slots_2.io.wakeup_ports[4].bits.uop.fu_code[2], issue_slots[2].wakeup_ports[4].bits.uop.fu_code[2] connect slots_2.io.wakeup_ports[4].bits.uop.fu_code[3], issue_slots[2].wakeup_ports[4].bits.uop.fu_code[3] connect slots_2.io.wakeup_ports[4].bits.uop.fu_code[4], issue_slots[2].wakeup_ports[4].bits.uop.fu_code[4] connect slots_2.io.wakeup_ports[4].bits.uop.fu_code[5], issue_slots[2].wakeup_ports[4].bits.uop.fu_code[5] connect slots_2.io.wakeup_ports[4].bits.uop.fu_code[6], issue_slots[2].wakeup_ports[4].bits.uop.fu_code[6] connect slots_2.io.wakeup_ports[4].bits.uop.fu_code[7], issue_slots[2].wakeup_ports[4].bits.uop.fu_code[7] connect slots_2.io.wakeup_ports[4].bits.uop.fu_code[8], issue_slots[2].wakeup_ports[4].bits.uop.fu_code[8] connect slots_2.io.wakeup_ports[4].bits.uop.fu_code[9], issue_slots[2].wakeup_ports[4].bits.uop.fu_code[9] connect slots_2.io.wakeup_ports[4].bits.uop.iq_type[0], issue_slots[2].wakeup_ports[4].bits.uop.iq_type[0] connect slots_2.io.wakeup_ports[4].bits.uop.iq_type[1], issue_slots[2].wakeup_ports[4].bits.uop.iq_type[1] connect slots_2.io.wakeup_ports[4].bits.uop.iq_type[2], issue_slots[2].wakeup_ports[4].bits.uop.iq_type[2] connect slots_2.io.wakeup_ports[4].bits.uop.iq_type[3], issue_slots[2].wakeup_ports[4].bits.uop.iq_type[3] connect slots_2.io.wakeup_ports[4].bits.uop.debug_pc, issue_slots[2].wakeup_ports[4].bits.uop.debug_pc connect slots_2.io.wakeup_ports[4].bits.uop.is_rvc, issue_slots[2].wakeup_ports[4].bits.uop.is_rvc connect slots_2.io.wakeup_ports[4].bits.uop.debug_inst, issue_slots[2].wakeup_ports[4].bits.uop.debug_inst connect slots_2.io.wakeup_ports[4].bits.uop.inst, issue_slots[2].wakeup_ports[4].bits.uop.inst connect slots_2.io.wakeup_ports[4].valid, issue_slots[2].wakeup_ports[4].valid connect slots_2.io.squash_grant, issue_slots[2].squash_grant connect slots_2.io.clear, issue_slots[2].clear connect slots_2.io.kill, issue_slots[2].kill connect slots_2.io.brupdate.b2.target_offset, issue_slots[2].brupdate.b2.target_offset connect slots_2.io.brupdate.b2.jalr_target, issue_slots[2].brupdate.b2.jalr_target connect slots_2.io.brupdate.b2.pc_sel, issue_slots[2].brupdate.b2.pc_sel connect slots_2.io.brupdate.b2.cfi_type, issue_slots[2].brupdate.b2.cfi_type connect slots_2.io.brupdate.b2.taken, issue_slots[2].brupdate.b2.taken connect slots_2.io.brupdate.b2.mispredict, issue_slots[2].brupdate.b2.mispredict connect slots_2.io.brupdate.b2.uop.debug_tsrc, issue_slots[2].brupdate.b2.uop.debug_tsrc connect slots_2.io.brupdate.b2.uop.debug_fsrc, issue_slots[2].brupdate.b2.uop.debug_fsrc connect slots_2.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[2].brupdate.b2.uop.bp_xcpt_if connect slots_2.io.brupdate.b2.uop.bp_debug_if, issue_slots[2].brupdate.b2.uop.bp_debug_if connect slots_2.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[2].brupdate.b2.uop.xcpt_ma_if connect slots_2.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[2].brupdate.b2.uop.xcpt_ae_if connect slots_2.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[2].brupdate.b2.uop.xcpt_pf_if connect slots_2.io.brupdate.b2.uop.fp_typ, issue_slots[2].brupdate.b2.uop.fp_typ connect slots_2.io.brupdate.b2.uop.fp_rm, issue_slots[2].brupdate.b2.uop.fp_rm connect slots_2.io.brupdate.b2.uop.fp_val, issue_slots[2].brupdate.b2.uop.fp_val connect slots_2.io.brupdate.b2.uop.fcn_op, issue_slots[2].brupdate.b2.uop.fcn_op connect slots_2.io.brupdate.b2.uop.fcn_dw, issue_slots[2].brupdate.b2.uop.fcn_dw connect slots_2.io.brupdate.b2.uop.frs3_en, issue_slots[2].brupdate.b2.uop.frs3_en connect slots_2.io.brupdate.b2.uop.lrs2_rtype, issue_slots[2].brupdate.b2.uop.lrs2_rtype connect slots_2.io.brupdate.b2.uop.lrs1_rtype, issue_slots[2].brupdate.b2.uop.lrs1_rtype connect slots_2.io.brupdate.b2.uop.dst_rtype, issue_slots[2].brupdate.b2.uop.dst_rtype connect slots_2.io.brupdate.b2.uop.lrs3, issue_slots[2].brupdate.b2.uop.lrs3 connect slots_2.io.brupdate.b2.uop.lrs2, issue_slots[2].brupdate.b2.uop.lrs2 connect slots_2.io.brupdate.b2.uop.lrs1, issue_slots[2].brupdate.b2.uop.lrs1 connect slots_2.io.brupdate.b2.uop.ldst, issue_slots[2].brupdate.b2.uop.ldst connect slots_2.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[2].brupdate.b2.uop.ldst_is_rs1 connect slots_2.io.brupdate.b2.uop.csr_cmd, issue_slots[2].brupdate.b2.uop.csr_cmd connect slots_2.io.brupdate.b2.uop.flush_on_commit, issue_slots[2].brupdate.b2.uop.flush_on_commit connect slots_2.io.brupdate.b2.uop.is_unique, issue_slots[2].brupdate.b2.uop.is_unique connect slots_2.io.brupdate.b2.uop.uses_stq, issue_slots[2].brupdate.b2.uop.uses_stq connect slots_2.io.brupdate.b2.uop.uses_ldq, issue_slots[2].brupdate.b2.uop.uses_ldq connect slots_2.io.brupdate.b2.uop.mem_signed, issue_slots[2].brupdate.b2.uop.mem_signed connect slots_2.io.brupdate.b2.uop.mem_size, issue_slots[2].brupdate.b2.uop.mem_size connect slots_2.io.brupdate.b2.uop.mem_cmd, issue_slots[2].brupdate.b2.uop.mem_cmd connect slots_2.io.brupdate.b2.uop.exc_cause, issue_slots[2].brupdate.b2.uop.exc_cause connect slots_2.io.brupdate.b2.uop.exception, issue_slots[2].brupdate.b2.uop.exception connect slots_2.io.brupdate.b2.uop.stale_pdst, issue_slots[2].brupdate.b2.uop.stale_pdst connect slots_2.io.brupdate.b2.uop.ppred_busy, issue_slots[2].brupdate.b2.uop.ppred_busy connect slots_2.io.brupdate.b2.uop.prs3_busy, issue_slots[2].brupdate.b2.uop.prs3_busy connect slots_2.io.brupdate.b2.uop.prs2_busy, issue_slots[2].brupdate.b2.uop.prs2_busy connect slots_2.io.brupdate.b2.uop.prs1_busy, issue_slots[2].brupdate.b2.uop.prs1_busy connect slots_2.io.brupdate.b2.uop.ppred, issue_slots[2].brupdate.b2.uop.ppred connect slots_2.io.brupdate.b2.uop.prs3, issue_slots[2].brupdate.b2.uop.prs3 connect slots_2.io.brupdate.b2.uop.prs2, issue_slots[2].brupdate.b2.uop.prs2 connect slots_2.io.brupdate.b2.uop.prs1, issue_slots[2].brupdate.b2.uop.prs1 connect slots_2.io.brupdate.b2.uop.pdst, issue_slots[2].brupdate.b2.uop.pdst connect slots_2.io.brupdate.b2.uop.rxq_idx, issue_slots[2].brupdate.b2.uop.rxq_idx connect slots_2.io.brupdate.b2.uop.stq_idx, issue_slots[2].brupdate.b2.uop.stq_idx connect slots_2.io.brupdate.b2.uop.ldq_idx, issue_slots[2].brupdate.b2.uop.ldq_idx connect slots_2.io.brupdate.b2.uop.rob_idx, issue_slots[2].brupdate.b2.uop.rob_idx connect slots_2.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[2].brupdate.b2.uop.fp_ctrl.vec connect slots_2.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[2].brupdate.b2.uop.fp_ctrl.wflags connect slots_2.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[2].brupdate.b2.uop.fp_ctrl.sqrt connect slots_2.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[2].brupdate.b2.uop.fp_ctrl.div connect slots_2.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[2].brupdate.b2.uop.fp_ctrl.fma connect slots_2.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[2].brupdate.b2.uop.fp_ctrl.fastpipe connect slots_2.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[2].brupdate.b2.uop.fp_ctrl.toint connect slots_2.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[2].brupdate.b2.uop.fp_ctrl.fromint connect slots_2.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[2].brupdate.b2.uop.fp_ctrl.typeTagOut connect slots_2.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[2].brupdate.b2.uop.fp_ctrl.typeTagIn connect slots_2.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[2].brupdate.b2.uop.fp_ctrl.swap23 connect slots_2.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[2].brupdate.b2.uop.fp_ctrl.swap12 connect slots_2.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[2].brupdate.b2.uop.fp_ctrl.ren3 connect slots_2.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[2].brupdate.b2.uop.fp_ctrl.ren2 connect slots_2.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[2].brupdate.b2.uop.fp_ctrl.ren1 connect slots_2.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[2].brupdate.b2.uop.fp_ctrl.wen connect slots_2.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[2].brupdate.b2.uop.fp_ctrl.ldst connect slots_2.io.brupdate.b2.uop.op2_sel, issue_slots[2].brupdate.b2.uop.op2_sel connect slots_2.io.brupdate.b2.uop.op1_sel, issue_slots[2].brupdate.b2.uop.op1_sel connect slots_2.io.brupdate.b2.uop.imm_packed, issue_slots[2].brupdate.b2.uop.imm_packed connect slots_2.io.brupdate.b2.uop.pimm, issue_slots[2].brupdate.b2.uop.pimm connect slots_2.io.brupdate.b2.uop.imm_sel, issue_slots[2].brupdate.b2.uop.imm_sel connect slots_2.io.brupdate.b2.uop.imm_rename, issue_slots[2].brupdate.b2.uop.imm_rename connect slots_2.io.brupdate.b2.uop.taken, issue_slots[2].brupdate.b2.uop.taken connect slots_2.io.brupdate.b2.uop.pc_lob, issue_slots[2].brupdate.b2.uop.pc_lob connect slots_2.io.brupdate.b2.uop.edge_inst, issue_slots[2].brupdate.b2.uop.edge_inst connect slots_2.io.brupdate.b2.uop.ftq_idx, issue_slots[2].brupdate.b2.uop.ftq_idx connect slots_2.io.brupdate.b2.uop.is_mov, issue_slots[2].brupdate.b2.uop.is_mov connect slots_2.io.brupdate.b2.uop.is_rocc, issue_slots[2].brupdate.b2.uop.is_rocc connect slots_2.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[2].brupdate.b2.uop.is_sys_pc2epc connect slots_2.io.brupdate.b2.uop.is_eret, issue_slots[2].brupdate.b2.uop.is_eret connect slots_2.io.brupdate.b2.uop.is_amo, issue_slots[2].brupdate.b2.uop.is_amo connect slots_2.io.brupdate.b2.uop.is_sfence, issue_slots[2].brupdate.b2.uop.is_sfence connect slots_2.io.brupdate.b2.uop.is_fencei, issue_slots[2].brupdate.b2.uop.is_fencei connect slots_2.io.brupdate.b2.uop.is_fence, issue_slots[2].brupdate.b2.uop.is_fence connect slots_2.io.brupdate.b2.uop.is_sfb, issue_slots[2].brupdate.b2.uop.is_sfb connect slots_2.io.brupdate.b2.uop.br_type, issue_slots[2].brupdate.b2.uop.br_type connect slots_2.io.brupdate.b2.uop.br_tag, issue_slots[2].brupdate.b2.uop.br_tag connect slots_2.io.brupdate.b2.uop.br_mask, issue_slots[2].brupdate.b2.uop.br_mask connect slots_2.io.brupdate.b2.uop.dis_col_sel, issue_slots[2].brupdate.b2.uop.dis_col_sel connect slots_2.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[2].brupdate.b2.uop.iw_p3_bypass_hint connect slots_2.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[2].brupdate.b2.uop.iw_p2_bypass_hint connect slots_2.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[2].brupdate.b2.uop.iw_p1_bypass_hint connect slots_2.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[2].brupdate.b2.uop.iw_p2_speculative_child connect slots_2.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[2].brupdate.b2.uop.iw_p1_speculative_child connect slots_2.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[2].brupdate.b2.uop.iw_issued_partial_dgen connect slots_2.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[2].brupdate.b2.uop.iw_issued_partial_agen connect slots_2.io.brupdate.b2.uop.iw_issued, issue_slots[2].brupdate.b2.uop.iw_issued connect slots_2.io.brupdate.b2.uop.fu_code[0], issue_slots[2].brupdate.b2.uop.fu_code[0] connect slots_2.io.brupdate.b2.uop.fu_code[1], issue_slots[2].brupdate.b2.uop.fu_code[1] connect slots_2.io.brupdate.b2.uop.fu_code[2], issue_slots[2].brupdate.b2.uop.fu_code[2] connect slots_2.io.brupdate.b2.uop.fu_code[3], issue_slots[2].brupdate.b2.uop.fu_code[3] connect slots_2.io.brupdate.b2.uop.fu_code[4], issue_slots[2].brupdate.b2.uop.fu_code[4] connect slots_2.io.brupdate.b2.uop.fu_code[5], issue_slots[2].brupdate.b2.uop.fu_code[5] connect slots_2.io.brupdate.b2.uop.fu_code[6], issue_slots[2].brupdate.b2.uop.fu_code[6] connect slots_2.io.brupdate.b2.uop.fu_code[7], issue_slots[2].brupdate.b2.uop.fu_code[7] connect slots_2.io.brupdate.b2.uop.fu_code[8], issue_slots[2].brupdate.b2.uop.fu_code[8] connect slots_2.io.brupdate.b2.uop.fu_code[9], issue_slots[2].brupdate.b2.uop.fu_code[9] connect slots_2.io.brupdate.b2.uop.iq_type[0], issue_slots[2].brupdate.b2.uop.iq_type[0] connect slots_2.io.brupdate.b2.uop.iq_type[1], issue_slots[2].brupdate.b2.uop.iq_type[1] connect slots_2.io.brupdate.b2.uop.iq_type[2], issue_slots[2].brupdate.b2.uop.iq_type[2] connect slots_2.io.brupdate.b2.uop.iq_type[3], issue_slots[2].brupdate.b2.uop.iq_type[3] connect slots_2.io.brupdate.b2.uop.debug_pc, issue_slots[2].brupdate.b2.uop.debug_pc connect slots_2.io.brupdate.b2.uop.is_rvc, issue_slots[2].brupdate.b2.uop.is_rvc connect slots_2.io.brupdate.b2.uop.debug_inst, issue_slots[2].brupdate.b2.uop.debug_inst connect slots_2.io.brupdate.b2.uop.inst, issue_slots[2].brupdate.b2.uop.inst connect slots_2.io.brupdate.b1.mispredict_mask, issue_slots[2].brupdate.b1.mispredict_mask connect slots_2.io.brupdate.b1.resolve_mask, issue_slots[2].brupdate.b1.resolve_mask connect issue_slots[2].out_uop.debug_tsrc, slots_2.io.out_uop.debug_tsrc connect issue_slots[2].out_uop.debug_fsrc, slots_2.io.out_uop.debug_fsrc connect issue_slots[2].out_uop.bp_xcpt_if, slots_2.io.out_uop.bp_xcpt_if connect issue_slots[2].out_uop.bp_debug_if, slots_2.io.out_uop.bp_debug_if connect issue_slots[2].out_uop.xcpt_ma_if, slots_2.io.out_uop.xcpt_ma_if connect issue_slots[2].out_uop.xcpt_ae_if, slots_2.io.out_uop.xcpt_ae_if connect issue_slots[2].out_uop.xcpt_pf_if, slots_2.io.out_uop.xcpt_pf_if connect issue_slots[2].out_uop.fp_typ, slots_2.io.out_uop.fp_typ connect issue_slots[2].out_uop.fp_rm, slots_2.io.out_uop.fp_rm connect issue_slots[2].out_uop.fp_val, slots_2.io.out_uop.fp_val connect issue_slots[2].out_uop.fcn_op, slots_2.io.out_uop.fcn_op connect issue_slots[2].out_uop.fcn_dw, slots_2.io.out_uop.fcn_dw connect issue_slots[2].out_uop.frs3_en, slots_2.io.out_uop.frs3_en connect issue_slots[2].out_uop.lrs2_rtype, slots_2.io.out_uop.lrs2_rtype connect issue_slots[2].out_uop.lrs1_rtype, slots_2.io.out_uop.lrs1_rtype connect issue_slots[2].out_uop.dst_rtype, slots_2.io.out_uop.dst_rtype connect issue_slots[2].out_uop.lrs3, slots_2.io.out_uop.lrs3 connect issue_slots[2].out_uop.lrs2, slots_2.io.out_uop.lrs2 connect issue_slots[2].out_uop.lrs1, slots_2.io.out_uop.lrs1 connect issue_slots[2].out_uop.ldst, slots_2.io.out_uop.ldst connect issue_slots[2].out_uop.ldst_is_rs1, slots_2.io.out_uop.ldst_is_rs1 connect issue_slots[2].out_uop.csr_cmd, slots_2.io.out_uop.csr_cmd connect issue_slots[2].out_uop.flush_on_commit, slots_2.io.out_uop.flush_on_commit connect issue_slots[2].out_uop.is_unique, slots_2.io.out_uop.is_unique connect issue_slots[2].out_uop.uses_stq, slots_2.io.out_uop.uses_stq connect issue_slots[2].out_uop.uses_ldq, slots_2.io.out_uop.uses_ldq connect issue_slots[2].out_uop.mem_signed, slots_2.io.out_uop.mem_signed connect issue_slots[2].out_uop.mem_size, slots_2.io.out_uop.mem_size connect issue_slots[2].out_uop.mem_cmd, slots_2.io.out_uop.mem_cmd connect issue_slots[2].out_uop.exc_cause, slots_2.io.out_uop.exc_cause connect issue_slots[2].out_uop.exception, slots_2.io.out_uop.exception connect issue_slots[2].out_uop.stale_pdst, slots_2.io.out_uop.stale_pdst connect issue_slots[2].out_uop.ppred_busy, slots_2.io.out_uop.ppred_busy connect issue_slots[2].out_uop.prs3_busy, slots_2.io.out_uop.prs3_busy connect issue_slots[2].out_uop.prs2_busy, slots_2.io.out_uop.prs2_busy connect issue_slots[2].out_uop.prs1_busy, slots_2.io.out_uop.prs1_busy connect issue_slots[2].out_uop.ppred, slots_2.io.out_uop.ppred connect issue_slots[2].out_uop.prs3, slots_2.io.out_uop.prs3 connect issue_slots[2].out_uop.prs2, slots_2.io.out_uop.prs2 connect issue_slots[2].out_uop.prs1, slots_2.io.out_uop.prs1 connect issue_slots[2].out_uop.pdst, slots_2.io.out_uop.pdst connect issue_slots[2].out_uop.rxq_idx, slots_2.io.out_uop.rxq_idx connect issue_slots[2].out_uop.stq_idx, slots_2.io.out_uop.stq_idx connect issue_slots[2].out_uop.ldq_idx, slots_2.io.out_uop.ldq_idx connect issue_slots[2].out_uop.rob_idx, slots_2.io.out_uop.rob_idx connect issue_slots[2].out_uop.fp_ctrl.vec, slots_2.io.out_uop.fp_ctrl.vec connect issue_slots[2].out_uop.fp_ctrl.wflags, slots_2.io.out_uop.fp_ctrl.wflags connect issue_slots[2].out_uop.fp_ctrl.sqrt, slots_2.io.out_uop.fp_ctrl.sqrt connect issue_slots[2].out_uop.fp_ctrl.div, slots_2.io.out_uop.fp_ctrl.div connect issue_slots[2].out_uop.fp_ctrl.fma, slots_2.io.out_uop.fp_ctrl.fma connect issue_slots[2].out_uop.fp_ctrl.fastpipe, slots_2.io.out_uop.fp_ctrl.fastpipe connect issue_slots[2].out_uop.fp_ctrl.toint, slots_2.io.out_uop.fp_ctrl.toint connect issue_slots[2].out_uop.fp_ctrl.fromint, slots_2.io.out_uop.fp_ctrl.fromint connect issue_slots[2].out_uop.fp_ctrl.typeTagOut, slots_2.io.out_uop.fp_ctrl.typeTagOut connect issue_slots[2].out_uop.fp_ctrl.typeTagIn, slots_2.io.out_uop.fp_ctrl.typeTagIn connect issue_slots[2].out_uop.fp_ctrl.swap23, slots_2.io.out_uop.fp_ctrl.swap23 connect issue_slots[2].out_uop.fp_ctrl.swap12, slots_2.io.out_uop.fp_ctrl.swap12 connect issue_slots[2].out_uop.fp_ctrl.ren3, slots_2.io.out_uop.fp_ctrl.ren3 connect issue_slots[2].out_uop.fp_ctrl.ren2, slots_2.io.out_uop.fp_ctrl.ren2 connect issue_slots[2].out_uop.fp_ctrl.ren1, slots_2.io.out_uop.fp_ctrl.ren1 connect issue_slots[2].out_uop.fp_ctrl.wen, slots_2.io.out_uop.fp_ctrl.wen connect issue_slots[2].out_uop.fp_ctrl.ldst, slots_2.io.out_uop.fp_ctrl.ldst connect issue_slots[2].out_uop.op2_sel, slots_2.io.out_uop.op2_sel connect issue_slots[2].out_uop.op1_sel, slots_2.io.out_uop.op1_sel connect issue_slots[2].out_uop.imm_packed, slots_2.io.out_uop.imm_packed connect issue_slots[2].out_uop.pimm, slots_2.io.out_uop.pimm connect issue_slots[2].out_uop.imm_sel, slots_2.io.out_uop.imm_sel connect issue_slots[2].out_uop.imm_rename, slots_2.io.out_uop.imm_rename connect issue_slots[2].out_uop.taken, slots_2.io.out_uop.taken connect issue_slots[2].out_uop.pc_lob, slots_2.io.out_uop.pc_lob connect issue_slots[2].out_uop.edge_inst, slots_2.io.out_uop.edge_inst connect issue_slots[2].out_uop.ftq_idx, slots_2.io.out_uop.ftq_idx connect issue_slots[2].out_uop.is_mov, slots_2.io.out_uop.is_mov connect issue_slots[2].out_uop.is_rocc, slots_2.io.out_uop.is_rocc connect issue_slots[2].out_uop.is_sys_pc2epc, slots_2.io.out_uop.is_sys_pc2epc connect issue_slots[2].out_uop.is_eret, slots_2.io.out_uop.is_eret connect issue_slots[2].out_uop.is_amo, slots_2.io.out_uop.is_amo connect issue_slots[2].out_uop.is_sfence, slots_2.io.out_uop.is_sfence connect issue_slots[2].out_uop.is_fencei, slots_2.io.out_uop.is_fencei connect issue_slots[2].out_uop.is_fence, slots_2.io.out_uop.is_fence connect issue_slots[2].out_uop.is_sfb, slots_2.io.out_uop.is_sfb connect issue_slots[2].out_uop.br_type, slots_2.io.out_uop.br_type connect issue_slots[2].out_uop.br_tag, slots_2.io.out_uop.br_tag connect issue_slots[2].out_uop.br_mask, slots_2.io.out_uop.br_mask connect issue_slots[2].out_uop.dis_col_sel, slots_2.io.out_uop.dis_col_sel connect issue_slots[2].out_uop.iw_p3_bypass_hint, slots_2.io.out_uop.iw_p3_bypass_hint connect issue_slots[2].out_uop.iw_p2_bypass_hint, slots_2.io.out_uop.iw_p2_bypass_hint connect issue_slots[2].out_uop.iw_p1_bypass_hint, slots_2.io.out_uop.iw_p1_bypass_hint connect issue_slots[2].out_uop.iw_p2_speculative_child, slots_2.io.out_uop.iw_p2_speculative_child connect issue_slots[2].out_uop.iw_p1_speculative_child, slots_2.io.out_uop.iw_p1_speculative_child connect issue_slots[2].out_uop.iw_issued_partial_dgen, slots_2.io.out_uop.iw_issued_partial_dgen connect issue_slots[2].out_uop.iw_issued_partial_agen, slots_2.io.out_uop.iw_issued_partial_agen connect issue_slots[2].out_uop.iw_issued, slots_2.io.out_uop.iw_issued connect issue_slots[2].out_uop.fu_code[0], slots_2.io.out_uop.fu_code[0] connect issue_slots[2].out_uop.fu_code[1], slots_2.io.out_uop.fu_code[1] connect issue_slots[2].out_uop.fu_code[2], slots_2.io.out_uop.fu_code[2] connect issue_slots[2].out_uop.fu_code[3], slots_2.io.out_uop.fu_code[3] connect issue_slots[2].out_uop.fu_code[4], slots_2.io.out_uop.fu_code[4] connect issue_slots[2].out_uop.fu_code[5], slots_2.io.out_uop.fu_code[5] connect issue_slots[2].out_uop.fu_code[6], slots_2.io.out_uop.fu_code[6] connect issue_slots[2].out_uop.fu_code[7], slots_2.io.out_uop.fu_code[7] connect issue_slots[2].out_uop.fu_code[8], slots_2.io.out_uop.fu_code[8] connect issue_slots[2].out_uop.fu_code[9], slots_2.io.out_uop.fu_code[9] connect issue_slots[2].out_uop.iq_type[0], slots_2.io.out_uop.iq_type[0] connect issue_slots[2].out_uop.iq_type[1], slots_2.io.out_uop.iq_type[1] connect issue_slots[2].out_uop.iq_type[2], slots_2.io.out_uop.iq_type[2] connect issue_slots[2].out_uop.iq_type[3], slots_2.io.out_uop.iq_type[3] connect issue_slots[2].out_uop.debug_pc, slots_2.io.out_uop.debug_pc connect issue_slots[2].out_uop.is_rvc, slots_2.io.out_uop.is_rvc connect issue_slots[2].out_uop.debug_inst, slots_2.io.out_uop.debug_inst connect issue_slots[2].out_uop.inst, slots_2.io.out_uop.inst connect slots_2.io.in_uop.bits.debug_tsrc, issue_slots[2].in_uop.bits.debug_tsrc connect slots_2.io.in_uop.bits.debug_fsrc, issue_slots[2].in_uop.bits.debug_fsrc connect slots_2.io.in_uop.bits.bp_xcpt_if, issue_slots[2].in_uop.bits.bp_xcpt_if connect slots_2.io.in_uop.bits.bp_debug_if, issue_slots[2].in_uop.bits.bp_debug_if connect slots_2.io.in_uop.bits.xcpt_ma_if, issue_slots[2].in_uop.bits.xcpt_ma_if connect slots_2.io.in_uop.bits.xcpt_ae_if, issue_slots[2].in_uop.bits.xcpt_ae_if connect slots_2.io.in_uop.bits.xcpt_pf_if, issue_slots[2].in_uop.bits.xcpt_pf_if connect slots_2.io.in_uop.bits.fp_typ, issue_slots[2].in_uop.bits.fp_typ connect slots_2.io.in_uop.bits.fp_rm, issue_slots[2].in_uop.bits.fp_rm connect slots_2.io.in_uop.bits.fp_val, issue_slots[2].in_uop.bits.fp_val connect slots_2.io.in_uop.bits.fcn_op, issue_slots[2].in_uop.bits.fcn_op connect slots_2.io.in_uop.bits.fcn_dw, issue_slots[2].in_uop.bits.fcn_dw connect slots_2.io.in_uop.bits.frs3_en, issue_slots[2].in_uop.bits.frs3_en connect slots_2.io.in_uop.bits.lrs2_rtype, issue_slots[2].in_uop.bits.lrs2_rtype connect slots_2.io.in_uop.bits.lrs1_rtype, issue_slots[2].in_uop.bits.lrs1_rtype connect slots_2.io.in_uop.bits.dst_rtype, issue_slots[2].in_uop.bits.dst_rtype connect slots_2.io.in_uop.bits.lrs3, issue_slots[2].in_uop.bits.lrs3 connect slots_2.io.in_uop.bits.lrs2, issue_slots[2].in_uop.bits.lrs2 connect slots_2.io.in_uop.bits.lrs1, issue_slots[2].in_uop.bits.lrs1 connect slots_2.io.in_uop.bits.ldst, issue_slots[2].in_uop.bits.ldst connect slots_2.io.in_uop.bits.ldst_is_rs1, issue_slots[2].in_uop.bits.ldst_is_rs1 connect slots_2.io.in_uop.bits.csr_cmd, issue_slots[2].in_uop.bits.csr_cmd connect slots_2.io.in_uop.bits.flush_on_commit, issue_slots[2].in_uop.bits.flush_on_commit connect slots_2.io.in_uop.bits.is_unique, issue_slots[2].in_uop.bits.is_unique connect slots_2.io.in_uop.bits.uses_stq, issue_slots[2].in_uop.bits.uses_stq connect slots_2.io.in_uop.bits.uses_ldq, issue_slots[2].in_uop.bits.uses_ldq connect slots_2.io.in_uop.bits.mem_signed, issue_slots[2].in_uop.bits.mem_signed connect slots_2.io.in_uop.bits.mem_size, issue_slots[2].in_uop.bits.mem_size connect slots_2.io.in_uop.bits.mem_cmd, issue_slots[2].in_uop.bits.mem_cmd connect slots_2.io.in_uop.bits.exc_cause, issue_slots[2].in_uop.bits.exc_cause connect slots_2.io.in_uop.bits.exception, issue_slots[2].in_uop.bits.exception connect slots_2.io.in_uop.bits.stale_pdst, issue_slots[2].in_uop.bits.stale_pdst connect slots_2.io.in_uop.bits.ppred_busy, issue_slots[2].in_uop.bits.ppred_busy connect slots_2.io.in_uop.bits.prs3_busy, issue_slots[2].in_uop.bits.prs3_busy connect slots_2.io.in_uop.bits.prs2_busy, issue_slots[2].in_uop.bits.prs2_busy connect slots_2.io.in_uop.bits.prs1_busy, issue_slots[2].in_uop.bits.prs1_busy connect slots_2.io.in_uop.bits.ppred, issue_slots[2].in_uop.bits.ppred connect slots_2.io.in_uop.bits.prs3, issue_slots[2].in_uop.bits.prs3 connect slots_2.io.in_uop.bits.prs2, issue_slots[2].in_uop.bits.prs2 connect slots_2.io.in_uop.bits.prs1, issue_slots[2].in_uop.bits.prs1 connect slots_2.io.in_uop.bits.pdst, issue_slots[2].in_uop.bits.pdst connect slots_2.io.in_uop.bits.rxq_idx, issue_slots[2].in_uop.bits.rxq_idx connect slots_2.io.in_uop.bits.stq_idx, issue_slots[2].in_uop.bits.stq_idx connect slots_2.io.in_uop.bits.ldq_idx, issue_slots[2].in_uop.bits.ldq_idx connect slots_2.io.in_uop.bits.rob_idx, issue_slots[2].in_uop.bits.rob_idx connect slots_2.io.in_uop.bits.fp_ctrl.vec, issue_slots[2].in_uop.bits.fp_ctrl.vec connect slots_2.io.in_uop.bits.fp_ctrl.wflags, issue_slots[2].in_uop.bits.fp_ctrl.wflags connect slots_2.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[2].in_uop.bits.fp_ctrl.sqrt connect slots_2.io.in_uop.bits.fp_ctrl.div, issue_slots[2].in_uop.bits.fp_ctrl.div connect slots_2.io.in_uop.bits.fp_ctrl.fma, issue_slots[2].in_uop.bits.fp_ctrl.fma connect slots_2.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[2].in_uop.bits.fp_ctrl.fastpipe connect slots_2.io.in_uop.bits.fp_ctrl.toint, issue_slots[2].in_uop.bits.fp_ctrl.toint connect slots_2.io.in_uop.bits.fp_ctrl.fromint, issue_slots[2].in_uop.bits.fp_ctrl.fromint connect slots_2.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[2].in_uop.bits.fp_ctrl.typeTagOut connect slots_2.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[2].in_uop.bits.fp_ctrl.typeTagIn connect slots_2.io.in_uop.bits.fp_ctrl.swap23, issue_slots[2].in_uop.bits.fp_ctrl.swap23 connect slots_2.io.in_uop.bits.fp_ctrl.swap12, issue_slots[2].in_uop.bits.fp_ctrl.swap12 connect slots_2.io.in_uop.bits.fp_ctrl.ren3, issue_slots[2].in_uop.bits.fp_ctrl.ren3 connect slots_2.io.in_uop.bits.fp_ctrl.ren2, issue_slots[2].in_uop.bits.fp_ctrl.ren2 connect slots_2.io.in_uop.bits.fp_ctrl.ren1, issue_slots[2].in_uop.bits.fp_ctrl.ren1 connect slots_2.io.in_uop.bits.fp_ctrl.wen, issue_slots[2].in_uop.bits.fp_ctrl.wen connect slots_2.io.in_uop.bits.fp_ctrl.ldst, issue_slots[2].in_uop.bits.fp_ctrl.ldst connect slots_2.io.in_uop.bits.op2_sel, issue_slots[2].in_uop.bits.op2_sel connect slots_2.io.in_uop.bits.op1_sel, issue_slots[2].in_uop.bits.op1_sel connect slots_2.io.in_uop.bits.imm_packed, issue_slots[2].in_uop.bits.imm_packed connect slots_2.io.in_uop.bits.pimm, issue_slots[2].in_uop.bits.pimm connect slots_2.io.in_uop.bits.imm_sel, issue_slots[2].in_uop.bits.imm_sel connect slots_2.io.in_uop.bits.imm_rename, issue_slots[2].in_uop.bits.imm_rename connect slots_2.io.in_uop.bits.taken, issue_slots[2].in_uop.bits.taken connect slots_2.io.in_uop.bits.pc_lob, issue_slots[2].in_uop.bits.pc_lob connect slots_2.io.in_uop.bits.edge_inst, issue_slots[2].in_uop.bits.edge_inst connect slots_2.io.in_uop.bits.ftq_idx, issue_slots[2].in_uop.bits.ftq_idx connect slots_2.io.in_uop.bits.is_mov, issue_slots[2].in_uop.bits.is_mov connect slots_2.io.in_uop.bits.is_rocc, issue_slots[2].in_uop.bits.is_rocc connect slots_2.io.in_uop.bits.is_sys_pc2epc, issue_slots[2].in_uop.bits.is_sys_pc2epc connect slots_2.io.in_uop.bits.is_eret, issue_slots[2].in_uop.bits.is_eret connect slots_2.io.in_uop.bits.is_amo, issue_slots[2].in_uop.bits.is_amo connect slots_2.io.in_uop.bits.is_sfence, issue_slots[2].in_uop.bits.is_sfence connect slots_2.io.in_uop.bits.is_fencei, issue_slots[2].in_uop.bits.is_fencei connect slots_2.io.in_uop.bits.is_fence, issue_slots[2].in_uop.bits.is_fence connect slots_2.io.in_uop.bits.is_sfb, issue_slots[2].in_uop.bits.is_sfb connect slots_2.io.in_uop.bits.br_type, issue_slots[2].in_uop.bits.br_type connect slots_2.io.in_uop.bits.br_tag, issue_slots[2].in_uop.bits.br_tag connect slots_2.io.in_uop.bits.br_mask, issue_slots[2].in_uop.bits.br_mask connect slots_2.io.in_uop.bits.dis_col_sel, issue_slots[2].in_uop.bits.dis_col_sel connect slots_2.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[2].in_uop.bits.iw_p3_bypass_hint connect slots_2.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[2].in_uop.bits.iw_p2_bypass_hint connect slots_2.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[2].in_uop.bits.iw_p1_bypass_hint connect slots_2.io.in_uop.bits.iw_p2_speculative_child, issue_slots[2].in_uop.bits.iw_p2_speculative_child connect slots_2.io.in_uop.bits.iw_p1_speculative_child, issue_slots[2].in_uop.bits.iw_p1_speculative_child connect slots_2.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[2].in_uop.bits.iw_issued_partial_dgen connect slots_2.io.in_uop.bits.iw_issued_partial_agen, issue_slots[2].in_uop.bits.iw_issued_partial_agen connect slots_2.io.in_uop.bits.iw_issued, issue_slots[2].in_uop.bits.iw_issued connect slots_2.io.in_uop.bits.fu_code[0], issue_slots[2].in_uop.bits.fu_code[0] connect slots_2.io.in_uop.bits.fu_code[1], issue_slots[2].in_uop.bits.fu_code[1] connect slots_2.io.in_uop.bits.fu_code[2], issue_slots[2].in_uop.bits.fu_code[2] connect slots_2.io.in_uop.bits.fu_code[3], issue_slots[2].in_uop.bits.fu_code[3] connect slots_2.io.in_uop.bits.fu_code[4], issue_slots[2].in_uop.bits.fu_code[4] connect slots_2.io.in_uop.bits.fu_code[5], issue_slots[2].in_uop.bits.fu_code[5] connect slots_2.io.in_uop.bits.fu_code[6], issue_slots[2].in_uop.bits.fu_code[6] connect slots_2.io.in_uop.bits.fu_code[7], issue_slots[2].in_uop.bits.fu_code[7] connect slots_2.io.in_uop.bits.fu_code[8], issue_slots[2].in_uop.bits.fu_code[8] connect slots_2.io.in_uop.bits.fu_code[9], issue_slots[2].in_uop.bits.fu_code[9] connect slots_2.io.in_uop.bits.iq_type[0], issue_slots[2].in_uop.bits.iq_type[0] connect slots_2.io.in_uop.bits.iq_type[1], issue_slots[2].in_uop.bits.iq_type[1] connect slots_2.io.in_uop.bits.iq_type[2], issue_slots[2].in_uop.bits.iq_type[2] connect slots_2.io.in_uop.bits.iq_type[3], issue_slots[2].in_uop.bits.iq_type[3] connect slots_2.io.in_uop.bits.debug_pc, issue_slots[2].in_uop.bits.debug_pc connect slots_2.io.in_uop.bits.is_rvc, issue_slots[2].in_uop.bits.is_rvc connect slots_2.io.in_uop.bits.debug_inst, issue_slots[2].in_uop.bits.debug_inst connect slots_2.io.in_uop.bits.inst, issue_slots[2].in_uop.bits.inst connect slots_2.io.in_uop.valid, issue_slots[2].in_uop.valid connect issue_slots[2].iss_uop.debug_tsrc, slots_2.io.iss_uop.debug_tsrc connect issue_slots[2].iss_uop.debug_fsrc, slots_2.io.iss_uop.debug_fsrc connect issue_slots[2].iss_uop.bp_xcpt_if, slots_2.io.iss_uop.bp_xcpt_if connect issue_slots[2].iss_uop.bp_debug_if, slots_2.io.iss_uop.bp_debug_if connect issue_slots[2].iss_uop.xcpt_ma_if, slots_2.io.iss_uop.xcpt_ma_if connect issue_slots[2].iss_uop.xcpt_ae_if, slots_2.io.iss_uop.xcpt_ae_if connect issue_slots[2].iss_uop.xcpt_pf_if, slots_2.io.iss_uop.xcpt_pf_if connect issue_slots[2].iss_uop.fp_typ, slots_2.io.iss_uop.fp_typ connect issue_slots[2].iss_uop.fp_rm, slots_2.io.iss_uop.fp_rm connect issue_slots[2].iss_uop.fp_val, slots_2.io.iss_uop.fp_val connect issue_slots[2].iss_uop.fcn_op, slots_2.io.iss_uop.fcn_op connect issue_slots[2].iss_uop.fcn_dw, slots_2.io.iss_uop.fcn_dw connect issue_slots[2].iss_uop.frs3_en, slots_2.io.iss_uop.frs3_en connect issue_slots[2].iss_uop.lrs2_rtype, slots_2.io.iss_uop.lrs2_rtype connect issue_slots[2].iss_uop.lrs1_rtype, slots_2.io.iss_uop.lrs1_rtype connect issue_slots[2].iss_uop.dst_rtype, slots_2.io.iss_uop.dst_rtype connect issue_slots[2].iss_uop.lrs3, slots_2.io.iss_uop.lrs3 connect issue_slots[2].iss_uop.lrs2, slots_2.io.iss_uop.lrs2 connect issue_slots[2].iss_uop.lrs1, slots_2.io.iss_uop.lrs1 connect issue_slots[2].iss_uop.ldst, slots_2.io.iss_uop.ldst connect issue_slots[2].iss_uop.ldst_is_rs1, slots_2.io.iss_uop.ldst_is_rs1 connect issue_slots[2].iss_uop.csr_cmd, slots_2.io.iss_uop.csr_cmd connect issue_slots[2].iss_uop.flush_on_commit, slots_2.io.iss_uop.flush_on_commit connect issue_slots[2].iss_uop.is_unique, slots_2.io.iss_uop.is_unique connect issue_slots[2].iss_uop.uses_stq, slots_2.io.iss_uop.uses_stq connect issue_slots[2].iss_uop.uses_ldq, slots_2.io.iss_uop.uses_ldq connect issue_slots[2].iss_uop.mem_signed, slots_2.io.iss_uop.mem_signed connect issue_slots[2].iss_uop.mem_size, slots_2.io.iss_uop.mem_size connect issue_slots[2].iss_uop.mem_cmd, slots_2.io.iss_uop.mem_cmd connect issue_slots[2].iss_uop.exc_cause, slots_2.io.iss_uop.exc_cause connect issue_slots[2].iss_uop.exception, slots_2.io.iss_uop.exception connect issue_slots[2].iss_uop.stale_pdst, slots_2.io.iss_uop.stale_pdst connect issue_slots[2].iss_uop.ppred_busy, slots_2.io.iss_uop.ppred_busy connect issue_slots[2].iss_uop.prs3_busy, slots_2.io.iss_uop.prs3_busy connect issue_slots[2].iss_uop.prs2_busy, slots_2.io.iss_uop.prs2_busy connect issue_slots[2].iss_uop.prs1_busy, slots_2.io.iss_uop.prs1_busy connect issue_slots[2].iss_uop.ppred, slots_2.io.iss_uop.ppred connect issue_slots[2].iss_uop.prs3, slots_2.io.iss_uop.prs3 connect issue_slots[2].iss_uop.prs2, slots_2.io.iss_uop.prs2 connect issue_slots[2].iss_uop.prs1, slots_2.io.iss_uop.prs1 connect issue_slots[2].iss_uop.pdst, slots_2.io.iss_uop.pdst connect issue_slots[2].iss_uop.rxq_idx, slots_2.io.iss_uop.rxq_idx connect issue_slots[2].iss_uop.stq_idx, slots_2.io.iss_uop.stq_idx connect issue_slots[2].iss_uop.ldq_idx, slots_2.io.iss_uop.ldq_idx connect issue_slots[2].iss_uop.rob_idx, slots_2.io.iss_uop.rob_idx connect issue_slots[2].iss_uop.fp_ctrl.vec, slots_2.io.iss_uop.fp_ctrl.vec connect issue_slots[2].iss_uop.fp_ctrl.wflags, slots_2.io.iss_uop.fp_ctrl.wflags connect issue_slots[2].iss_uop.fp_ctrl.sqrt, slots_2.io.iss_uop.fp_ctrl.sqrt connect issue_slots[2].iss_uop.fp_ctrl.div, slots_2.io.iss_uop.fp_ctrl.div connect issue_slots[2].iss_uop.fp_ctrl.fma, slots_2.io.iss_uop.fp_ctrl.fma connect issue_slots[2].iss_uop.fp_ctrl.fastpipe, slots_2.io.iss_uop.fp_ctrl.fastpipe connect issue_slots[2].iss_uop.fp_ctrl.toint, slots_2.io.iss_uop.fp_ctrl.toint connect issue_slots[2].iss_uop.fp_ctrl.fromint, slots_2.io.iss_uop.fp_ctrl.fromint connect issue_slots[2].iss_uop.fp_ctrl.typeTagOut, slots_2.io.iss_uop.fp_ctrl.typeTagOut connect issue_slots[2].iss_uop.fp_ctrl.typeTagIn, slots_2.io.iss_uop.fp_ctrl.typeTagIn connect issue_slots[2].iss_uop.fp_ctrl.swap23, slots_2.io.iss_uop.fp_ctrl.swap23 connect issue_slots[2].iss_uop.fp_ctrl.swap12, slots_2.io.iss_uop.fp_ctrl.swap12 connect issue_slots[2].iss_uop.fp_ctrl.ren3, slots_2.io.iss_uop.fp_ctrl.ren3 connect issue_slots[2].iss_uop.fp_ctrl.ren2, slots_2.io.iss_uop.fp_ctrl.ren2 connect issue_slots[2].iss_uop.fp_ctrl.ren1, slots_2.io.iss_uop.fp_ctrl.ren1 connect issue_slots[2].iss_uop.fp_ctrl.wen, slots_2.io.iss_uop.fp_ctrl.wen connect issue_slots[2].iss_uop.fp_ctrl.ldst, slots_2.io.iss_uop.fp_ctrl.ldst connect issue_slots[2].iss_uop.op2_sel, slots_2.io.iss_uop.op2_sel connect issue_slots[2].iss_uop.op1_sel, slots_2.io.iss_uop.op1_sel connect issue_slots[2].iss_uop.imm_packed, slots_2.io.iss_uop.imm_packed connect issue_slots[2].iss_uop.pimm, slots_2.io.iss_uop.pimm connect issue_slots[2].iss_uop.imm_sel, slots_2.io.iss_uop.imm_sel connect issue_slots[2].iss_uop.imm_rename, slots_2.io.iss_uop.imm_rename connect issue_slots[2].iss_uop.taken, slots_2.io.iss_uop.taken connect issue_slots[2].iss_uop.pc_lob, slots_2.io.iss_uop.pc_lob connect issue_slots[2].iss_uop.edge_inst, slots_2.io.iss_uop.edge_inst connect issue_slots[2].iss_uop.ftq_idx, slots_2.io.iss_uop.ftq_idx connect issue_slots[2].iss_uop.is_mov, slots_2.io.iss_uop.is_mov connect issue_slots[2].iss_uop.is_rocc, slots_2.io.iss_uop.is_rocc connect issue_slots[2].iss_uop.is_sys_pc2epc, slots_2.io.iss_uop.is_sys_pc2epc connect issue_slots[2].iss_uop.is_eret, slots_2.io.iss_uop.is_eret connect issue_slots[2].iss_uop.is_amo, slots_2.io.iss_uop.is_amo connect issue_slots[2].iss_uop.is_sfence, slots_2.io.iss_uop.is_sfence connect issue_slots[2].iss_uop.is_fencei, slots_2.io.iss_uop.is_fencei connect issue_slots[2].iss_uop.is_fence, slots_2.io.iss_uop.is_fence connect issue_slots[2].iss_uop.is_sfb, slots_2.io.iss_uop.is_sfb connect issue_slots[2].iss_uop.br_type, slots_2.io.iss_uop.br_type connect issue_slots[2].iss_uop.br_tag, slots_2.io.iss_uop.br_tag connect issue_slots[2].iss_uop.br_mask, slots_2.io.iss_uop.br_mask connect issue_slots[2].iss_uop.dis_col_sel, slots_2.io.iss_uop.dis_col_sel connect issue_slots[2].iss_uop.iw_p3_bypass_hint, slots_2.io.iss_uop.iw_p3_bypass_hint connect issue_slots[2].iss_uop.iw_p2_bypass_hint, slots_2.io.iss_uop.iw_p2_bypass_hint connect issue_slots[2].iss_uop.iw_p1_bypass_hint, slots_2.io.iss_uop.iw_p1_bypass_hint connect issue_slots[2].iss_uop.iw_p2_speculative_child, slots_2.io.iss_uop.iw_p2_speculative_child connect issue_slots[2].iss_uop.iw_p1_speculative_child, slots_2.io.iss_uop.iw_p1_speculative_child connect issue_slots[2].iss_uop.iw_issued_partial_dgen, slots_2.io.iss_uop.iw_issued_partial_dgen connect issue_slots[2].iss_uop.iw_issued_partial_agen, slots_2.io.iss_uop.iw_issued_partial_agen connect issue_slots[2].iss_uop.iw_issued, slots_2.io.iss_uop.iw_issued connect issue_slots[2].iss_uop.fu_code[0], slots_2.io.iss_uop.fu_code[0] connect issue_slots[2].iss_uop.fu_code[1], slots_2.io.iss_uop.fu_code[1] connect issue_slots[2].iss_uop.fu_code[2], slots_2.io.iss_uop.fu_code[2] connect issue_slots[2].iss_uop.fu_code[3], slots_2.io.iss_uop.fu_code[3] connect issue_slots[2].iss_uop.fu_code[4], slots_2.io.iss_uop.fu_code[4] connect issue_slots[2].iss_uop.fu_code[5], slots_2.io.iss_uop.fu_code[5] connect issue_slots[2].iss_uop.fu_code[6], slots_2.io.iss_uop.fu_code[6] connect issue_slots[2].iss_uop.fu_code[7], slots_2.io.iss_uop.fu_code[7] connect issue_slots[2].iss_uop.fu_code[8], slots_2.io.iss_uop.fu_code[8] connect issue_slots[2].iss_uop.fu_code[9], slots_2.io.iss_uop.fu_code[9] connect issue_slots[2].iss_uop.iq_type[0], slots_2.io.iss_uop.iq_type[0] connect issue_slots[2].iss_uop.iq_type[1], slots_2.io.iss_uop.iq_type[1] connect issue_slots[2].iss_uop.iq_type[2], slots_2.io.iss_uop.iq_type[2] connect issue_slots[2].iss_uop.iq_type[3], slots_2.io.iss_uop.iq_type[3] connect issue_slots[2].iss_uop.debug_pc, slots_2.io.iss_uop.debug_pc connect issue_slots[2].iss_uop.is_rvc, slots_2.io.iss_uop.is_rvc connect issue_slots[2].iss_uop.debug_inst, slots_2.io.iss_uop.debug_inst connect issue_slots[2].iss_uop.inst, slots_2.io.iss_uop.inst connect slots_2.io.grant, issue_slots[2].grant connect issue_slots[2].request, slots_2.io.request connect issue_slots[2].will_be_valid, slots_2.io.will_be_valid connect issue_slots[2].valid, slots_2.io.valid connect slots_3.io.child_rebusys, issue_slots[3].child_rebusys connect slots_3.io.pred_wakeup_port.bits, issue_slots[3].pred_wakeup_port.bits connect slots_3.io.pred_wakeup_port.valid, issue_slots[3].pred_wakeup_port.valid connect slots_3.io.wakeup_ports[0].bits.rebusy, issue_slots[3].wakeup_ports[0].bits.rebusy connect slots_3.io.wakeup_ports[0].bits.speculative_mask, issue_slots[3].wakeup_ports[0].bits.speculative_mask connect slots_3.io.wakeup_ports[0].bits.bypassable, issue_slots[3].wakeup_ports[0].bits.bypassable connect slots_3.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[3].wakeup_ports[0].bits.uop.debug_tsrc connect slots_3.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[3].wakeup_ports[0].bits.uop.debug_fsrc connect slots_3.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[3].wakeup_ports[0].bits.uop.bp_xcpt_if connect slots_3.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[3].wakeup_ports[0].bits.uop.bp_debug_if connect slots_3.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[3].wakeup_ports[0].bits.uop.xcpt_ma_if connect slots_3.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[3].wakeup_ports[0].bits.uop.xcpt_ae_if connect slots_3.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[3].wakeup_ports[0].bits.uop.xcpt_pf_if connect slots_3.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[3].wakeup_ports[0].bits.uop.fp_typ connect slots_3.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[3].wakeup_ports[0].bits.uop.fp_rm connect slots_3.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[3].wakeup_ports[0].bits.uop.fp_val connect slots_3.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[3].wakeup_ports[0].bits.uop.fcn_op connect slots_3.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[3].wakeup_ports[0].bits.uop.fcn_dw connect slots_3.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[3].wakeup_ports[0].bits.uop.frs3_en connect slots_3.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[3].wakeup_ports[0].bits.uop.lrs2_rtype connect slots_3.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[3].wakeup_ports[0].bits.uop.lrs1_rtype connect slots_3.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[3].wakeup_ports[0].bits.uop.dst_rtype connect slots_3.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[3].wakeup_ports[0].bits.uop.lrs3 connect slots_3.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[3].wakeup_ports[0].bits.uop.lrs2 connect slots_3.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[3].wakeup_ports[0].bits.uop.lrs1 connect slots_3.io.wakeup_ports[0].bits.uop.ldst, issue_slots[3].wakeup_ports[0].bits.uop.ldst connect slots_3.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[3].wakeup_ports[0].bits.uop.ldst_is_rs1 connect slots_3.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[3].wakeup_ports[0].bits.uop.csr_cmd connect slots_3.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[3].wakeup_ports[0].bits.uop.flush_on_commit connect slots_3.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[3].wakeup_ports[0].bits.uop.is_unique connect slots_3.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[3].wakeup_ports[0].bits.uop.uses_stq connect slots_3.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[3].wakeup_ports[0].bits.uop.uses_ldq connect slots_3.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[3].wakeup_ports[0].bits.uop.mem_signed connect slots_3.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[3].wakeup_ports[0].bits.uop.mem_size connect slots_3.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[3].wakeup_ports[0].bits.uop.mem_cmd connect slots_3.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[3].wakeup_ports[0].bits.uop.exc_cause connect slots_3.io.wakeup_ports[0].bits.uop.exception, issue_slots[3].wakeup_ports[0].bits.uop.exception connect slots_3.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[3].wakeup_ports[0].bits.uop.stale_pdst connect slots_3.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[3].wakeup_ports[0].bits.uop.ppred_busy connect slots_3.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[3].wakeup_ports[0].bits.uop.prs3_busy connect slots_3.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[3].wakeup_ports[0].bits.uop.prs2_busy connect slots_3.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[3].wakeup_ports[0].bits.uop.prs1_busy connect slots_3.io.wakeup_ports[0].bits.uop.ppred, issue_slots[3].wakeup_ports[0].bits.uop.ppred connect slots_3.io.wakeup_ports[0].bits.uop.prs3, issue_slots[3].wakeup_ports[0].bits.uop.prs3 connect slots_3.io.wakeup_ports[0].bits.uop.prs2, issue_slots[3].wakeup_ports[0].bits.uop.prs2 connect slots_3.io.wakeup_ports[0].bits.uop.prs1, issue_slots[3].wakeup_ports[0].bits.uop.prs1 connect slots_3.io.wakeup_ports[0].bits.uop.pdst, issue_slots[3].wakeup_ports[0].bits.uop.pdst connect slots_3.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[3].wakeup_ports[0].bits.uop.rxq_idx connect slots_3.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[3].wakeup_ports[0].bits.uop.stq_idx connect slots_3.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[3].wakeup_ports[0].bits.uop.ldq_idx connect slots_3.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[3].wakeup_ports[0].bits.uop.rob_idx connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.vec connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.wflags connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.div connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.fma connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.toint connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.fromint connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.wen connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.ldst connect slots_3.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[3].wakeup_ports[0].bits.uop.op2_sel connect slots_3.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[3].wakeup_ports[0].bits.uop.op1_sel connect slots_3.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[3].wakeup_ports[0].bits.uop.imm_packed connect slots_3.io.wakeup_ports[0].bits.uop.pimm, issue_slots[3].wakeup_ports[0].bits.uop.pimm connect slots_3.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[3].wakeup_ports[0].bits.uop.imm_sel connect slots_3.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[3].wakeup_ports[0].bits.uop.imm_rename connect slots_3.io.wakeup_ports[0].bits.uop.taken, issue_slots[3].wakeup_ports[0].bits.uop.taken connect slots_3.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[3].wakeup_ports[0].bits.uop.pc_lob connect slots_3.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[3].wakeup_ports[0].bits.uop.edge_inst connect slots_3.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[3].wakeup_ports[0].bits.uop.ftq_idx connect slots_3.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[3].wakeup_ports[0].bits.uop.is_mov connect slots_3.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[3].wakeup_ports[0].bits.uop.is_rocc connect slots_3.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[3].wakeup_ports[0].bits.uop.is_sys_pc2epc connect slots_3.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[3].wakeup_ports[0].bits.uop.is_eret connect slots_3.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[3].wakeup_ports[0].bits.uop.is_amo connect slots_3.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[3].wakeup_ports[0].bits.uop.is_sfence connect slots_3.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[3].wakeup_ports[0].bits.uop.is_fencei connect slots_3.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[3].wakeup_ports[0].bits.uop.is_fence connect slots_3.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[3].wakeup_ports[0].bits.uop.is_sfb connect slots_3.io.wakeup_ports[0].bits.uop.br_type, issue_slots[3].wakeup_ports[0].bits.uop.br_type connect slots_3.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[3].wakeup_ports[0].bits.uop.br_tag connect slots_3.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[3].wakeup_ports[0].bits.uop.br_mask connect slots_3.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[3].wakeup_ports[0].bits.uop.dis_col_sel connect slots_3.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[3].wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect slots_3.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[3].wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect slots_3.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[3].wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect slots_3.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[3].wakeup_ports[0].bits.uop.iw_p2_speculative_child connect slots_3.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[3].wakeup_ports[0].bits.uop.iw_p1_speculative_child connect slots_3.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[3].wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect slots_3.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[3].wakeup_ports[0].bits.uop.iw_issued_partial_agen connect slots_3.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[3].wakeup_ports[0].bits.uop.iw_issued connect slots_3.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[3].wakeup_ports[0].bits.uop.fu_code[0] connect slots_3.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[3].wakeup_ports[0].bits.uop.fu_code[1] connect slots_3.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[3].wakeup_ports[0].bits.uop.fu_code[2] connect slots_3.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[3].wakeup_ports[0].bits.uop.fu_code[3] connect slots_3.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[3].wakeup_ports[0].bits.uop.fu_code[4] connect slots_3.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[3].wakeup_ports[0].bits.uop.fu_code[5] connect slots_3.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[3].wakeup_ports[0].bits.uop.fu_code[6] connect slots_3.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[3].wakeup_ports[0].bits.uop.fu_code[7] connect slots_3.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[3].wakeup_ports[0].bits.uop.fu_code[8] connect slots_3.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[3].wakeup_ports[0].bits.uop.fu_code[9] connect slots_3.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[3].wakeup_ports[0].bits.uop.iq_type[0] connect slots_3.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[3].wakeup_ports[0].bits.uop.iq_type[1] connect slots_3.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[3].wakeup_ports[0].bits.uop.iq_type[2] connect slots_3.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[3].wakeup_ports[0].bits.uop.iq_type[3] connect slots_3.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[3].wakeup_ports[0].bits.uop.debug_pc connect slots_3.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[3].wakeup_ports[0].bits.uop.is_rvc connect slots_3.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[3].wakeup_ports[0].bits.uop.debug_inst connect slots_3.io.wakeup_ports[0].bits.uop.inst, issue_slots[3].wakeup_ports[0].bits.uop.inst connect slots_3.io.wakeup_ports[0].valid, issue_slots[3].wakeup_ports[0].valid connect slots_3.io.wakeup_ports[1].bits.rebusy, issue_slots[3].wakeup_ports[1].bits.rebusy connect slots_3.io.wakeup_ports[1].bits.speculative_mask, issue_slots[3].wakeup_ports[1].bits.speculative_mask connect slots_3.io.wakeup_ports[1].bits.bypassable, issue_slots[3].wakeup_ports[1].bits.bypassable connect slots_3.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[3].wakeup_ports[1].bits.uop.debug_tsrc connect slots_3.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[3].wakeup_ports[1].bits.uop.debug_fsrc connect slots_3.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[3].wakeup_ports[1].bits.uop.bp_xcpt_if connect slots_3.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[3].wakeup_ports[1].bits.uop.bp_debug_if connect slots_3.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[3].wakeup_ports[1].bits.uop.xcpt_ma_if connect slots_3.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[3].wakeup_ports[1].bits.uop.xcpt_ae_if connect slots_3.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[3].wakeup_ports[1].bits.uop.xcpt_pf_if connect slots_3.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[3].wakeup_ports[1].bits.uop.fp_typ connect slots_3.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[3].wakeup_ports[1].bits.uop.fp_rm connect slots_3.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[3].wakeup_ports[1].bits.uop.fp_val connect slots_3.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[3].wakeup_ports[1].bits.uop.fcn_op connect slots_3.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[3].wakeup_ports[1].bits.uop.fcn_dw connect slots_3.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[3].wakeup_ports[1].bits.uop.frs3_en connect slots_3.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[3].wakeup_ports[1].bits.uop.lrs2_rtype connect slots_3.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[3].wakeup_ports[1].bits.uop.lrs1_rtype connect slots_3.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[3].wakeup_ports[1].bits.uop.dst_rtype connect slots_3.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[3].wakeup_ports[1].bits.uop.lrs3 connect slots_3.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[3].wakeup_ports[1].bits.uop.lrs2 connect slots_3.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[3].wakeup_ports[1].bits.uop.lrs1 connect slots_3.io.wakeup_ports[1].bits.uop.ldst, issue_slots[3].wakeup_ports[1].bits.uop.ldst connect slots_3.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[3].wakeup_ports[1].bits.uop.ldst_is_rs1 connect slots_3.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[3].wakeup_ports[1].bits.uop.csr_cmd connect slots_3.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[3].wakeup_ports[1].bits.uop.flush_on_commit connect slots_3.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[3].wakeup_ports[1].bits.uop.is_unique connect slots_3.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[3].wakeup_ports[1].bits.uop.uses_stq connect slots_3.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[3].wakeup_ports[1].bits.uop.uses_ldq connect slots_3.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[3].wakeup_ports[1].bits.uop.mem_signed connect slots_3.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[3].wakeup_ports[1].bits.uop.mem_size connect slots_3.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[3].wakeup_ports[1].bits.uop.mem_cmd connect slots_3.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[3].wakeup_ports[1].bits.uop.exc_cause connect slots_3.io.wakeup_ports[1].bits.uop.exception, issue_slots[3].wakeup_ports[1].bits.uop.exception connect slots_3.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[3].wakeup_ports[1].bits.uop.stale_pdst connect slots_3.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[3].wakeup_ports[1].bits.uop.ppred_busy connect slots_3.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[3].wakeup_ports[1].bits.uop.prs3_busy connect slots_3.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[3].wakeup_ports[1].bits.uop.prs2_busy connect slots_3.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[3].wakeup_ports[1].bits.uop.prs1_busy connect slots_3.io.wakeup_ports[1].bits.uop.ppred, issue_slots[3].wakeup_ports[1].bits.uop.ppred connect slots_3.io.wakeup_ports[1].bits.uop.prs3, issue_slots[3].wakeup_ports[1].bits.uop.prs3 connect slots_3.io.wakeup_ports[1].bits.uop.prs2, issue_slots[3].wakeup_ports[1].bits.uop.prs2 connect slots_3.io.wakeup_ports[1].bits.uop.prs1, issue_slots[3].wakeup_ports[1].bits.uop.prs1 connect slots_3.io.wakeup_ports[1].bits.uop.pdst, issue_slots[3].wakeup_ports[1].bits.uop.pdst connect slots_3.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[3].wakeup_ports[1].bits.uop.rxq_idx connect slots_3.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[3].wakeup_ports[1].bits.uop.stq_idx connect slots_3.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[3].wakeup_ports[1].bits.uop.ldq_idx connect slots_3.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[3].wakeup_ports[1].bits.uop.rob_idx connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.vec connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.wflags connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.div connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.fma connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.toint connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.fromint connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.wen connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.ldst connect slots_3.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[3].wakeup_ports[1].bits.uop.op2_sel connect slots_3.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[3].wakeup_ports[1].bits.uop.op1_sel connect slots_3.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[3].wakeup_ports[1].bits.uop.imm_packed connect slots_3.io.wakeup_ports[1].bits.uop.pimm, issue_slots[3].wakeup_ports[1].bits.uop.pimm connect slots_3.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[3].wakeup_ports[1].bits.uop.imm_sel connect slots_3.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[3].wakeup_ports[1].bits.uop.imm_rename connect slots_3.io.wakeup_ports[1].bits.uop.taken, issue_slots[3].wakeup_ports[1].bits.uop.taken connect slots_3.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[3].wakeup_ports[1].bits.uop.pc_lob connect slots_3.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[3].wakeup_ports[1].bits.uop.edge_inst connect slots_3.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[3].wakeup_ports[1].bits.uop.ftq_idx connect slots_3.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[3].wakeup_ports[1].bits.uop.is_mov connect slots_3.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[3].wakeup_ports[1].bits.uop.is_rocc connect slots_3.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[3].wakeup_ports[1].bits.uop.is_sys_pc2epc connect slots_3.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[3].wakeup_ports[1].bits.uop.is_eret connect slots_3.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[3].wakeup_ports[1].bits.uop.is_amo connect slots_3.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[3].wakeup_ports[1].bits.uop.is_sfence connect slots_3.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[3].wakeup_ports[1].bits.uop.is_fencei connect slots_3.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[3].wakeup_ports[1].bits.uop.is_fence connect slots_3.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[3].wakeup_ports[1].bits.uop.is_sfb connect slots_3.io.wakeup_ports[1].bits.uop.br_type, issue_slots[3].wakeup_ports[1].bits.uop.br_type connect slots_3.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[3].wakeup_ports[1].bits.uop.br_tag connect slots_3.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[3].wakeup_ports[1].bits.uop.br_mask connect slots_3.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[3].wakeup_ports[1].bits.uop.dis_col_sel connect slots_3.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[3].wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect slots_3.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[3].wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect slots_3.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[3].wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect slots_3.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[3].wakeup_ports[1].bits.uop.iw_p2_speculative_child connect slots_3.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[3].wakeup_ports[1].bits.uop.iw_p1_speculative_child connect slots_3.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[3].wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect slots_3.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[3].wakeup_ports[1].bits.uop.iw_issued_partial_agen connect slots_3.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[3].wakeup_ports[1].bits.uop.iw_issued connect slots_3.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[3].wakeup_ports[1].bits.uop.fu_code[0] connect slots_3.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[3].wakeup_ports[1].bits.uop.fu_code[1] connect slots_3.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[3].wakeup_ports[1].bits.uop.fu_code[2] connect slots_3.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[3].wakeup_ports[1].bits.uop.fu_code[3] connect slots_3.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[3].wakeup_ports[1].bits.uop.fu_code[4] connect slots_3.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[3].wakeup_ports[1].bits.uop.fu_code[5] connect slots_3.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[3].wakeup_ports[1].bits.uop.fu_code[6] connect slots_3.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[3].wakeup_ports[1].bits.uop.fu_code[7] connect slots_3.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[3].wakeup_ports[1].bits.uop.fu_code[8] connect slots_3.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[3].wakeup_ports[1].bits.uop.fu_code[9] connect slots_3.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[3].wakeup_ports[1].bits.uop.iq_type[0] connect slots_3.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[3].wakeup_ports[1].bits.uop.iq_type[1] connect slots_3.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[3].wakeup_ports[1].bits.uop.iq_type[2] connect slots_3.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[3].wakeup_ports[1].bits.uop.iq_type[3] connect slots_3.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[3].wakeup_ports[1].bits.uop.debug_pc connect slots_3.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[3].wakeup_ports[1].bits.uop.is_rvc connect slots_3.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[3].wakeup_ports[1].bits.uop.debug_inst connect slots_3.io.wakeup_ports[1].bits.uop.inst, issue_slots[3].wakeup_ports[1].bits.uop.inst connect slots_3.io.wakeup_ports[1].valid, issue_slots[3].wakeup_ports[1].valid connect slots_3.io.wakeup_ports[2].bits.rebusy, issue_slots[3].wakeup_ports[2].bits.rebusy connect slots_3.io.wakeup_ports[2].bits.speculative_mask, issue_slots[3].wakeup_ports[2].bits.speculative_mask connect slots_3.io.wakeup_ports[2].bits.bypassable, issue_slots[3].wakeup_ports[2].bits.bypassable connect slots_3.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[3].wakeup_ports[2].bits.uop.debug_tsrc connect slots_3.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[3].wakeup_ports[2].bits.uop.debug_fsrc connect slots_3.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[3].wakeup_ports[2].bits.uop.bp_xcpt_if connect slots_3.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[3].wakeup_ports[2].bits.uop.bp_debug_if connect slots_3.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[3].wakeup_ports[2].bits.uop.xcpt_ma_if connect slots_3.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[3].wakeup_ports[2].bits.uop.xcpt_ae_if connect slots_3.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[3].wakeup_ports[2].bits.uop.xcpt_pf_if connect slots_3.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[3].wakeup_ports[2].bits.uop.fp_typ connect slots_3.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[3].wakeup_ports[2].bits.uop.fp_rm connect slots_3.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[3].wakeup_ports[2].bits.uop.fp_val connect slots_3.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[3].wakeup_ports[2].bits.uop.fcn_op connect slots_3.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[3].wakeup_ports[2].bits.uop.fcn_dw connect slots_3.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[3].wakeup_ports[2].bits.uop.frs3_en connect slots_3.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[3].wakeup_ports[2].bits.uop.lrs2_rtype connect slots_3.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[3].wakeup_ports[2].bits.uop.lrs1_rtype connect slots_3.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[3].wakeup_ports[2].bits.uop.dst_rtype connect slots_3.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[3].wakeup_ports[2].bits.uop.lrs3 connect slots_3.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[3].wakeup_ports[2].bits.uop.lrs2 connect slots_3.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[3].wakeup_ports[2].bits.uop.lrs1 connect slots_3.io.wakeup_ports[2].bits.uop.ldst, issue_slots[3].wakeup_ports[2].bits.uop.ldst connect slots_3.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[3].wakeup_ports[2].bits.uop.ldst_is_rs1 connect slots_3.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[3].wakeup_ports[2].bits.uop.csr_cmd connect slots_3.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[3].wakeup_ports[2].bits.uop.flush_on_commit connect slots_3.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[3].wakeup_ports[2].bits.uop.is_unique connect slots_3.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[3].wakeup_ports[2].bits.uop.uses_stq connect slots_3.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[3].wakeup_ports[2].bits.uop.uses_ldq connect slots_3.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[3].wakeup_ports[2].bits.uop.mem_signed connect slots_3.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[3].wakeup_ports[2].bits.uop.mem_size connect slots_3.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[3].wakeup_ports[2].bits.uop.mem_cmd connect slots_3.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[3].wakeup_ports[2].bits.uop.exc_cause connect slots_3.io.wakeup_ports[2].bits.uop.exception, issue_slots[3].wakeup_ports[2].bits.uop.exception connect slots_3.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[3].wakeup_ports[2].bits.uop.stale_pdst connect slots_3.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[3].wakeup_ports[2].bits.uop.ppred_busy connect slots_3.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[3].wakeup_ports[2].bits.uop.prs3_busy connect slots_3.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[3].wakeup_ports[2].bits.uop.prs2_busy connect slots_3.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[3].wakeup_ports[2].bits.uop.prs1_busy connect slots_3.io.wakeup_ports[2].bits.uop.ppred, issue_slots[3].wakeup_ports[2].bits.uop.ppred connect slots_3.io.wakeup_ports[2].bits.uop.prs3, issue_slots[3].wakeup_ports[2].bits.uop.prs3 connect slots_3.io.wakeup_ports[2].bits.uop.prs2, issue_slots[3].wakeup_ports[2].bits.uop.prs2 connect slots_3.io.wakeup_ports[2].bits.uop.prs1, issue_slots[3].wakeup_ports[2].bits.uop.prs1 connect slots_3.io.wakeup_ports[2].bits.uop.pdst, issue_slots[3].wakeup_ports[2].bits.uop.pdst connect slots_3.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[3].wakeup_ports[2].bits.uop.rxq_idx connect slots_3.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[3].wakeup_ports[2].bits.uop.stq_idx connect slots_3.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[3].wakeup_ports[2].bits.uop.ldq_idx connect slots_3.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[3].wakeup_ports[2].bits.uop.rob_idx connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.vec connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.wflags connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.div connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.fma connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.toint connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.fromint connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.wen connect slots_3.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.ldst connect slots_3.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[3].wakeup_ports[2].bits.uop.op2_sel connect slots_3.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[3].wakeup_ports[2].bits.uop.op1_sel connect slots_3.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[3].wakeup_ports[2].bits.uop.imm_packed connect slots_3.io.wakeup_ports[2].bits.uop.pimm, issue_slots[3].wakeup_ports[2].bits.uop.pimm connect slots_3.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[3].wakeup_ports[2].bits.uop.imm_sel connect slots_3.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[3].wakeup_ports[2].bits.uop.imm_rename connect slots_3.io.wakeup_ports[2].bits.uop.taken, issue_slots[3].wakeup_ports[2].bits.uop.taken connect slots_3.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[3].wakeup_ports[2].bits.uop.pc_lob connect slots_3.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[3].wakeup_ports[2].bits.uop.edge_inst connect slots_3.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[3].wakeup_ports[2].bits.uop.ftq_idx connect slots_3.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[3].wakeup_ports[2].bits.uop.is_mov connect slots_3.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[3].wakeup_ports[2].bits.uop.is_rocc connect slots_3.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[3].wakeup_ports[2].bits.uop.is_sys_pc2epc connect slots_3.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[3].wakeup_ports[2].bits.uop.is_eret connect slots_3.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[3].wakeup_ports[2].bits.uop.is_amo connect slots_3.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[3].wakeup_ports[2].bits.uop.is_sfence connect slots_3.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[3].wakeup_ports[2].bits.uop.is_fencei connect slots_3.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[3].wakeup_ports[2].bits.uop.is_fence connect slots_3.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[3].wakeup_ports[2].bits.uop.is_sfb connect slots_3.io.wakeup_ports[2].bits.uop.br_type, issue_slots[3].wakeup_ports[2].bits.uop.br_type connect slots_3.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[3].wakeup_ports[2].bits.uop.br_tag connect slots_3.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[3].wakeup_ports[2].bits.uop.br_mask connect slots_3.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[3].wakeup_ports[2].bits.uop.dis_col_sel connect slots_3.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[3].wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect slots_3.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[3].wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect slots_3.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[3].wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect slots_3.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[3].wakeup_ports[2].bits.uop.iw_p2_speculative_child connect slots_3.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[3].wakeup_ports[2].bits.uop.iw_p1_speculative_child connect slots_3.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[3].wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect slots_3.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[3].wakeup_ports[2].bits.uop.iw_issued_partial_agen connect slots_3.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[3].wakeup_ports[2].bits.uop.iw_issued connect slots_3.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[3].wakeup_ports[2].bits.uop.fu_code[0] connect slots_3.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[3].wakeup_ports[2].bits.uop.fu_code[1] connect slots_3.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[3].wakeup_ports[2].bits.uop.fu_code[2] connect slots_3.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[3].wakeup_ports[2].bits.uop.fu_code[3] connect slots_3.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[3].wakeup_ports[2].bits.uop.fu_code[4] connect slots_3.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[3].wakeup_ports[2].bits.uop.fu_code[5] connect slots_3.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[3].wakeup_ports[2].bits.uop.fu_code[6] connect slots_3.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[3].wakeup_ports[2].bits.uop.fu_code[7] connect slots_3.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[3].wakeup_ports[2].bits.uop.fu_code[8] connect slots_3.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[3].wakeup_ports[2].bits.uop.fu_code[9] connect slots_3.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[3].wakeup_ports[2].bits.uop.iq_type[0] connect slots_3.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[3].wakeup_ports[2].bits.uop.iq_type[1] connect slots_3.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[3].wakeup_ports[2].bits.uop.iq_type[2] connect slots_3.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[3].wakeup_ports[2].bits.uop.iq_type[3] connect slots_3.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[3].wakeup_ports[2].bits.uop.debug_pc connect slots_3.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[3].wakeup_ports[2].bits.uop.is_rvc connect slots_3.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[3].wakeup_ports[2].bits.uop.debug_inst connect slots_3.io.wakeup_ports[2].bits.uop.inst, issue_slots[3].wakeup_ports[2].bits.uop.inst connect slots_3.io.wakeup_ports[2].valid, issue_slots[3].wakeup_ports[2].valid connect slots_3.io.wakeup_ports[3].bits.rebusy, issue_slots[3].wakeup_ports[3].bits.rebusy connect slots_3.io.wakeup_ports[3].bits.speculative_mask, issue_slots[3].wakeup_ports[3].bits.speculative_mask connect slots_3.io.wakeup_ports[3].bits.bypassable, issue_slots[3].wakeup_ports[3].bits.bypassable connect slots_3.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[3].wakeup_ports[3].bits.uop.debug_tsrc connect slots_3.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[3].wakeup_ports[3].bits.uop.debug_fsrc connect slots_3.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[3].wakeup_ports[3].bits.uop.bp_xcpt_if connect slots_3.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[3].wakeup_ports[3].bits.uop.bp_debug_if connect slots_3.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[3].wakeup_ports[3].bits.uop.xcpt_ma_if connect slots_3.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[3].wakeup_ports[3].bits.uop.xcpt_ae_if connect slots_3.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[3].wakeup_ports[3].bits.uop.xcpt_pf_if connect slots_3.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[3].wakeup_ports[3].bits.uop.fp_typ connect slots_3.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[3].wakeup_ports[3].bits.uop.fp_rm connect slots_3.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[3].wakeup_ports[3].bits.uop.fp_val connect slots_3.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[3].wakeup_ports[3].bits.uop.fcn_op connect slots_3.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[3].wakeup_ports[3].bits.uop.fcn_dw connect slots_3.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[3].wakeup_ports[3].bits.uop.frs3_en connect slots_3.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[3].wakeup_ports[3].bits.uop.lrs2_rtype connect slots_3.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[3].wakeup_ports[3].bits.uop.lrs1_rtype connect slots_3.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[3].wakeup_ports[3].bits.uop.dst_rtype connect slots_3.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[3].wakeup_ports[3].bits.uop.lrs3 connect slots_3.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[3].wakeup_ports[3].bits.uop.lrs2 connect slots_3.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[3].wakeup_ports[3].bits.uop.lrs1 connect slots_3.io.wakeup_ports[3].bits.uop.ldst, issue_slots[3].wakeup_ports[3].bits.uop.ldst connect slots_3.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[3].wakeup_ports[3].bits.uop.ldst_is_rs1 connect slots_3.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[3].wakeup_ports[3].bits.uop.csr_cmd connect slots_3.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[3].wakeup_ports[3].bits.uop.flush_on_commit connect slots_3.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[3].wakeup_ports[3].bits.uop.is_unique connect slots_3.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[3].wakeup_ports[3].bits.uop.uses_stq connect slots_3.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[3].wakeup_ports[3].bits.uop.uses_ldq connect slots_3.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[3].wakeup_ports[3].bits.uop.mem_signed connect slots_3.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[3].wakeup_ports[3].bits.uop.mem_size connect slots_3.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[3].wakeup_ports[3].bits.uop.mem_cmd connect slots_3.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[3].wakeup_ports[3].bits.uop.exc_cause connect slots_3.io.wakeup_ports[3].bits.uop.exception, issue_slots[3].wakeup_ports[3].bits.uop.exception connect slots_3.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[3].wakeup_ports[3].bits.uop.stale_pdst connect slots_3.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[3].wakeup_ports[3].bits.uop.ppred_busy connect slots_3.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[3].wakeup_ports[3].bits.uop.prs3_busy connect slots_3.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[3].wakeup_ports[3].bits.uop.prs2_busy connect slots_3.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[3].wakeup_ports[3].bits.uop.prs1_busy connect slots_3.io.wakeup_ports[3].bits.uop.ppred, issue_slots[3].wakeup_ports[3].bits.uop.ppred connect slots_3.io.wakeup_ports[3].bits.uop.prs3, issue_slots[3].wakeup_ports[3].bits.uop.prs3 connect slots_3.io.wakeup_ports[3].bits.uop.prs2, issue_slots[3].wakeup_ports[3].bits.uop.prs2 connect slots_3.io.wakeup_ports[3].bits.uop.prs1, issue_slots[3].wakeup_ports[3].bits.uop.prs1 connect slots_3.io.wakeup_ports[3].bits.uop.pdst, issue_slots[3].wakeup_ports[3].bits.uop.pdst connect slots_3.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[3].wakeup_ports[3].bits.uop.rxq_idx connect slots_3.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[3].wakeup_ports[3].bits.uop.stq_idx connect slots_3.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[3].wakeup_ports[3].bits.uop.ldq_idx connect slots_3.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[3].wakeup_ports[3].bits.uop.rob_idx connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.vec connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.wflags connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.div connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.fma connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.toint connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.fromint connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.wen connect slots_3.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.ldst connect slots_3.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[3].wakeup_ports[3].bits.uop.op2_sel connect slots_3.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[3].wakeup_ports[3].bits.uop.op1_sel connect slots_3.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[3].wakeup_ports[3].bits.uop.imm_packed connect slots_3.io.wakeup_ports[3].bits.uop.pimm, issue_slots[3].wakeup_ports[3].bits.uop.pimm connect slots_3.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[3].wakeup_ports[3].bits.uop.imm_sel connect slots_3.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[3].wakeup_ports[3].bits.uop.imm_rename connect slots_3.io.wakeup_ports[3].bits.uop.taken, issue_slots[3].wakeup_ports[3].bits.uop.taken connect slots_3.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[3].wakeup_ports[3].bits.uop.pc_lob connect slots_3.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[3].wakeup_ports[3].bits.uop.edge_inst connect slots_3.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[3].wakeup_ports[3].bits.uop.ftq_idx connect slots_3.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[3].wakeup_ports[3].bits.uop.is_mov connect slots_3.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[3].wakeup_ports[3].bits.uop.is_rocc connect slots_3.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[3].wakeup_ports[3].bits.uop.is_sys_pc2epc connect slots_3.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[3].wakeup_ports[3].bits.uop.is_eret connect slots_3.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[3].wakeup_ports[3].bits.uop.is_amo connect slots_3.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[3].wakeup_ports[3].bits.uop.is_sfence connect slots_3.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[3].wakeup_ports[3].bits.uop.is_fencei connect slots_3.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[3].wakeup_ports[3].bits.uop.is_fence connect slots_3.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[3].wakeup_ports[3].bits.uop.is_sfb connect slots_3.io.wakeup_ports[3].bits.uop.br_type, issue_slots[3].wakeup_ports[3].bits.uop.br_type connect slots_3.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[3].wakeup_ports[3].bits.uop.br_tag connect slots_3.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[3].wakeup_ports[3].bits.uop.br_mask connect slots_3.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[3].wakeup_ports[3].bits.uop.dis_col_sel connect slots_3.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[3].wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect slots_3.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[3].wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect slots_3.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[3].wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect slots_3.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[3].wakeup_ports[3].bits.uop.iw_p2_speculative_child connect slots_3.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[3].wakeup_ports[3].bits.uop.iw_p1_speculative_child connect slots_3.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[3].wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect slots_3.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[3].wakeup_ports[3].bits.uop.iw_issued_partial_agen connect slots_3.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[3].wakeup_ports[3].bits.uop.iw_issued connect slots_3.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[3].wakeup_ports[3].bits.uop.fu_code[0] connect slots_3.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[3].wakeup_ports[3].bits.uop.fu_code[1] connect slots_3.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[3].wakeup_ports[3].bits.uop.fu_code[2] connect slots_3.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[3].wakeup_ports[3].bits.uop.fu_code[3] connect slots_3.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[3].wakeup_ports[3].bits.uop.fu_code[4] connect slots_3.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[3].wakeup_ports[3].bits.uop.fu_code[5] connect slots_3.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[3].wakeup_ports[3].bits.uop.fu_code[6] connect slots_3.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[3].wakeup_ports[3].bits.uop.fu_code[7] connect slots_3.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[3].wakeup_ports[3].bits.uop.fu_code[8] connect slots_3.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[3].wakeup_ports[3].bits.uop.fu_code[9] connect slots_3.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[3].wakeup_ports[3].bits.uop.iq_type[0] connect slots_3.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[3].wakeup_ports[3].bits.uop.iq_type[1] connect slots_3.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[3].wakeup_ports[3].bits.uop.iq_type[2] connect slots_3.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[3].wakeup_ports[3].bits.uop.iq_type[3] connect slots_3.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[3].wakeup_ports[3].bits.uop.debug_pc connect slots_3.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[3].wakeup_ports[3].bits.uop.is_rvc connect slots_3.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[3].wakeup_ports[3].bits.uop.debug_inst connect slots_3.io.wakeup_ports[3].bits.uop.inst, issue_slots[3].wakeup_ports[3].bits.uop.inst connect slots_3.io.wakeup_ports[3].valid, issue_slots[3].wakeup_ports[3].valid connect slots_3.io.wakeup_ports[4].bits.rebusy, issue_slots[3].wakeup_ports[4].bits.rebusy connect slots_3.io.wakeup_ports[4].bits.speculative_mask, issue_slots[3].wakeup_ports[4].bits.speculative_mask connect slots_3.io.wakeup_ports[4].bits.bypassable, issue_slots[3].wakeup_ports[4].bits.bypassable connect slots_3.io.wakeup_ports[4].bits.uop.debug_tsrc, issue_slots[3].wakeup_ports[4].bits.uop.debug_tsrc connect slots_3.io.wakeup_ports[4].bits.uop.debug_fsrc, issue_slots[3].wakeup_ports[4].bits.uop.debug_fsrc connect slots_3.io.wakeup_ports[4].bits.uop.bp_xcpt_if, issue_slots[3].wakeup_ports[4].bits.uop.bp_xcpt_if connect slots_3.io.wakeup_ports[4].bits.uop.bp_debug_if, issue_slots[3].wakeup_ports[4].bits.uop.bp_debug_if connect slots_3.io.wakeup_ports[4].bits.uop.xcpt_ma_if, issue_slots[3].wakeup_ports[4].bits.uop.xcpt_ma_if connect slots_3.io.wakeup_ports[4].bits.uop.xcpt_ae_if, issue_slots[3].wakeup_ports[4].bits.uop.xcpt_ae_if connect slots_3.io.wakeup_ports[4].bits.uop.xcpt_pf_if, issue_slots[3].wakeup_ports[4].bits.uop.xcpt_pf_if connect slots_3.io.wakeup_ports[4].bits.uop.fp_typ, issue_slots[3].wakeup_ports[4].bits.uop.fp_typ connect slots_3.io.wakeup_ports[4].bits.uop.fp_rm, issue_slots[3].wakeup_ports[4].bits.uop.fp_rm connect slots_3.io.wakeup_ports[4].bits.uop.fp_val, issue_slots[3].wakeup_ports[4].bits.uop.fp_val connect slots_3.io.wakeup_ports[4].bits.uop.fcn_op, issue_slots[3].wakeup_ports[4].bits.uop.fcn_op connect slots_3.io.wakeup_ports[4].bits.uop.fcn_dw, issue_slots[3].wakeup_ports[4].bits.uop.fcn_dw connect slots_3.io.wakeup_ports[4].bits.uop.frs3_en, issue_slots[3].wakeup_ports[4].bits.uop.frs3_en connect slots_3.io.wakeup_ports[4].bits.uop.lrs2_rtype, issue_slots[3].wakeup_ports[4].bits.uop.lrs2_rtype connect slots_3.io.wakeup_ports[4].bits.uop.lrs1_rtype, issue_slots[3].wakeup_ports[4].bits.uop.lrs1_rtype connect slots_3.io.wakeup_ports[4].bits.uop.dst_rtype, issue_slots[3].wakeup_ports[4].bits.uop.dst_rtype connect slots_3.io.wakeup_ports[4].bits.uop.lrs3, issue_slots[3].wakeup_ports[4].bits.uop.lrs3 connect slots_3.io.wakeup_ports[4].bits.uop.lrs2, issue_slots[3].wakeup_ports[4].bits.uop.lrs2 connect slots_3.io.wakeup_ports[4].bits.uop.lrs1, issue_slots[3].wakeup_ports[4].bits.uop.lrs1 connect slots_3.io.wakeup_ports[4].bits.uop.ldst, issue_slots[3].wakeup_ports[4].bits.uop.ldst connect slots_3.io.wakeup_ports[4].bits.uop.ldst_is_rs1, issue_slots[3].wakeup_ports[4].bits.uop.ldst_is_rs1 connect slots_3.io.wakeup_ports[4].bits.uop.csr_cmd, issue_slots[3].wakeup_ports[4].bits.uop.csr_cmd connect slots_3.io.wakeup_ports[4].bits.uop.flush_on_commit, issue_slots[3].wakeup_ports[4].bits.uop.flush_on_commit connect slots_3.io.wakeup_ports[4].bits.uop.is_unique, issue_slots[3].wakeup_ports[4].bits.uop.is_unique connect slots_3.io.wakeup_ports[4].bits.uop.uses_stq, issue_slots[3].wakeup_ports[4].bits.uop.uses_stq connect slots_3.io.wakeup_ports[4].bits.uop.uses_ldq, issue_slots[3].wakeup_ports[4].bits.uop.uses_ldq connect slots_3.io.wakeup_ports[4].bits.uop.mem_signed, issue_slots[3].wakeup_ports[4].bits.uop.mem_signed connect slots_3.io.wakeup_ports[4].bits.uop.mem_size, issue_slots[3].wakeup_ports[4].bits.uop.mem_size connect slots_3.io.wakeup_ports[4].bits.uop.mem_cmd, issue_slots[3].wakeup_ports[4].bits.uop.mem_cmd connect slots_3.io.wakeup_ports[4].bits.uop.exc_cause, issue_slots[3].wakeup_ports[4].bits.uop.exc_cause connect slots_3.io.wakeup_ports[4].bits.uop.exception, issue_slots[3].wakeup_ports[4].bits.uop.exception connect slots_3.io.wakeup_ports[4].bits.uop.stale_pdst, issue_slots[3].wakeup_ports[4].bits.uop.stale_pdst connect slots_3.io.wakeup_ports[4].bits.uop.ppred_busy, issue_slots[3].wakeup_ports[4].bits.uop.ppred_busy connect slots_3.io.wakeup_ports[4].bits.uop.prs3_busy, issue_slots[3].wakeup_ports[4].bits.uop.prs3_busy connect slots_3.io.wakeup_ports[4].bits.uop.prs2_busy, issue_slots[3].wakeup_ports[4].bits.uop.prs2_busy connect slots_3.io.wakeup_ports[4].bits.uop.prs1_busy, issue_slots[3].wakeup_ports[4].bits.uop.prs1_busy connect slots_3.io.wakeup_ports[4].bits.uop.ppred, issue_slots[3].wakeup_ports[4].bits.uop.ppred connect slots_3.io.wakeup_ports[4].bits.uop.prs3, issue_slots[3].wakeup_ports[4].bits.uop.prs3 connect slots_3.io.wakeup_ports[4].bits.uop.prs2, issue_slots[3].wakeup_ports[4].bits.uop.prs2 connect slots_3.io.wakeup_ports[4].bits.uop.prs1, issue_slots[3].wakeup_ports[4].bits.uop.prs1 connect slots_3.io.wakeup_ports[4].bits.uop.pdst, issue_slots[3].wakeup_ports[4].bits.uop.pdst connect slots_3.io.wakeup_ports[4].bits.uop.rxq_idx, issue_slots[3].wakeup_ports[4].bits.uop.rxq_idx connect slots_3.io.wakeup_ports[4].bits.uop.stq_idx, issue_slots[3].wakeup_ports[4].bits.uop.stq_idx connect slots_3.io.wakeup_ports[4].bits.uop.ldq_idx, issue_slots[3].wakeup_ports[4].bits.uop.ldq_idx connect slots_3.io.wakeup_ports[4].bits.uop.rob_idx, issue_slots[3].wakeup_ports[4].bits.uop.rob_idx connect slots_3.io.wakeup_ports[4].bits.uop.fp_ctrl.vec, issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.vec connect slots_3.io.wakeup_ports[4].bits.uop.fp_ctrl.wflags, issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.wflags connect slots_3.io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt, issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect slots_3.io.wakeup_ports[4].bits.uop.fp_ctrl.div, issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.div connect slots_3.io.wakeup_ports[4].bits.uop.fp_ctrl.fma, issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.fma connect slots_3.io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect slots_3.io.wakeup_ports[4].bits.uop.fp_ctrl.toint, issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.toint connect slots_3.io.wakeup_ports[4].bits.uop.fp_ctrl.fromint, issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.fromint connect slots_3.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect slots_3.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect slots_3.io.wakeup_ports[4].bits.uop.fp_ctrl.swap23, issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect slots_3.io.wakeup_ports[4].bits.uop.fp_ctrl.swap12, issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect slots_3.io.wakeup_ports[4].bits.uop.fp_ctrl.ren3, issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect slots_3.io.wakeup_ports[4].bits.uop.fp_ctrl.ren2, issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect slots_3.io.wakeup_ports[4].bits.uop.fp_ctrl.ren1, issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect slots_3.io.wakeup_ports[4].bits.uop.fp_ctrl.wen, issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.wen connect slots_3.io.wakeup_ports[4].bits.uop.fp_ctrl.ldst, issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.ldst connect slots_3.io.wakeup_ports[4].bits.uop.op2_sel, issue_slots[3].wakeup_ports[4].bits.uop.op2_sel connect slots_3.io.wakeup_ports[4].bits.uop.op1_sel, issue_slots[3].wakeup_ports[4].bits.uop.op1_sel connect slots_3.io.wakeup_ports[4].bits.uop.imm_packed, issue_slots[3].wakeup_ports[4].bits.uop.imm_packed connect slots_3.io.wakeup_ports[4].bits.uop.pimm, issue_slots[3].wakeup_ports[4].bits.uop.pimm connect slots_3.io.wakeup_ports[4].bits.uop.imm_sel, issue_slots[3].wakeup_ports[4].bits.uop.imm_sel connect slots_3.io.wakeup_ports[4].bits.uop.imm_rename, issue_slots[3].wakeup_ports[4].bits.uop.imm_rename connect slots_3.io.wakeup_ports[4].bits.uop.taken, issue_slots[3].wakeup_ports[4].bits.uop.taken connect slots_3.io.wakeup_ports[4].bits.uop.pc_lob, issue_slots[3].wakeup_ports[4].bits.uop.pc_lob connect slots_3.io.wakeup_ports[4].bits.uop.edge_inst, issue_slots[3].wakeup_ports[4].bits.uop.edge_inst connect slots_3.io.wakeup_ports[4].bits.uop.ftq_idx, issue_slots[3].wakeup_ports[4].bits.uop.ftq_idx connect slots_3.io.wakeup_ports[4].bits.uop.is_mov, issue_slots[3].wakeup_ports[4].bits.uop.is_mov connect slots_3.io.wakeup_ports[4].bits.uop.is_rocc, issue_slots[3].wakeup_ports[4].bits.uop.is_rocc connect slots_3.io.wakeup_ports[4].bits.uop.is_sys_pc2epc, issue_slots[3].wakeup_ports[4].bits.uop.is_sys_pc2epc connect slots_3.io.wakeup_ports[4].bits.uop.is_eret, issue_slots[3].wakeup_ports[4].bits.uop.is_eret connect slots_3.io.wakeup_ports[4].bits.uop.is_amo, issue_slots[3].wakeup_ports[4].bits.uop.is_amo connect slots_3.io.wakeup_ports[4].bits.uop.is_sfence, issue_slots[3].wakeup_ports[4].bits.uop.is_sfence connect slots_3.io.wakeup_ports[4].bits.uop.is_fencei, issue_slots[3].wakeup_ports[4].bits.uop.is_fencei connect slots_3.io.wakeup_ports[4].bits.uop.is_fence, issue_slots[3].wakeup_ports[4].bits.uop.is_fence connect slots_3.io.wakeup_ports[4].bits.uop.is_sfb, issue_slots[3].wakeup_ports[4].bits.uop.is_sfb connect slots_3.io.wakeup_ports[4].bits.uop.br_type, issue_slots[3].wakeup_ports[4].bits.uop.br_type connect slots_3.io.wakeup_ports[4].bits.uop.br_tag, issue_slots[3].wakeup_ports[4].bits.uop.br_tag connect slots_3.io.wakeup_ports[4].bits.uop.br_mask, issue_slots[3].wakeup_ports[4].bits.uop.br_mask connect slots_3.io.wakeup_ports[4].bits.uop.dis_col_sel, issue_slots[3].wakeup_ports[4].bits.uop.dis_col_sel connect slots_3.io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint, issue_slots[3].wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect slots_3.io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint, issue_slots[3].wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect slots_3.io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint, issue_slots[3].wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect slots_3.io.wakeup_ports[4].bits.uop.iw_p2_speculative_child, issue_slots[3].wakeup_ports[4].bits.uop.iw_p2_speculative_child connect slots_3.io.wakeup_ports[4].bits.uop.iw_p1_speculative_child, issue_slots[3].wakeup_ports[4].bits.uop.iw_p1_speculative_child connect slots_3.io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen, issue_slots[3].wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect slots_3.io.wakeup_ports[4].bits.uop.iw_issued_partial_agen, issue_slots[3].wakeup_ports[4].bits.uop.iw_issued_partial_agen connect slots_3.io.wakeup_ports[4].bits.uop.iw_issued, issue_slots[3].wakeup_ports[4].bits.uop.iw_issued connect slots_3.io.wakeup_ports[4].bits.uop.fu_code[0], issue_slots[3].wakeup_ports[4].bits.uop.fu_code[0] connect slots_3.io.wakeup_ports[4].bits.uop.fu_code[1], issue_slots[3].wakeup_ports[4].bits.uop.fu_code[1] connect slots_3.io.wakeup_ports[4].bits.uop.fu_code[2], issue_slots[3].wakeup_ports[4].bits.uop.fu_code[2] connect slots_3.io.wakeup_ports[4].bits.uop.fu_code[3], issue_slots[3].wakeup_ports[4].bits.uop.fu_code[3] connect slots_3.io.wakeup_ports[4].bits.uop.fu_code[4], issue_slots[3].wakeup_ports[4].bits.uop.fu_code[4] connect slots_3.io.wakeup_ports[4].bits.uop.fu_code[5], issue_slots[3].wakeup_ports[4].bits.uop.fu_code[5] connect slots_3.io.wakeup_ports[4].bits.uop.fu_code[6], issue_slots[3].wakeup_ports[4].bits.uop.fu_code[6] connect slots_3.io.wakeup_ports[4].bits.uop.fu_code[7], issue_slots[3].wakeup_ports[4].bits.uop.fu_code[7] connect slots_3.io.wakeup_ports[4].bits.uop.fu_code[8], issue_slots[3].wakeup_ports[4].bits.uop.fu_code[8] connect slots_3.io.wakeup_ports[4].bits.uop.fu_code[9], issue_slots[3].wakeup_ports[4].bits.uop.fu_code[9] connect slots_3.io.wakeup_ports[4].bits.uop.iq_type[0], issue_slots[3].wakeup_ports[4].bits.uop.iq_type[0] connect slots_3.io.wakeup_ports[4].bits.uop.iq_type[1], issue_slots[3].wakeup_ports[4].bits.uop.iq_type[1] connect slots_3.io.wakeup_ports[4].bits.uop.iq_type[2], issue_slots[3].wakeup_ports[4].bits.uop.iq_type[2] connect slots_3.io.wakeup_ports[4].bits.uop.iq_type[3], issue_slots[3].wakeup_ports[4].bits.uop.iq_type[3] connect slots_3.io.wakeup_ports[4].bits.uop.debug_pc, issue_slots[3].wakeup_ports[4].bits.uop.debug_pc connect slots_3.io.wakeup_ports[4].bits.uop.is_rvc, issue_slots[3].wakeup_ports[4].bits.uop.is_rvc connect slots_3.io.wakeup_ports[4].bits.uop.debug_inst, issue_slots[3].wakeup_ports[4].bits.uop.debug_inst connect slots_3.io.wakeup_ports[4].bits.uop.inst, issue_slots[3].wakeup_ports[4].bits.uop.inst connect slots_3.io.wakeup_ports[4].valid, issue_slots[3].wakeup_ports[4].valid connect slots_3.io.squash_grant, issue_slots[3].squash_grant connect slots_3.io.clear, issue_slots[3].clear connect slots_3.io.kill, issue_slots[3].kill connect slots_3.io.brupdate.b2.target_offset, issue_slots[3].brupdate.b2.target_offset connect slots_3.io.brupdate.b2.jalr_target, issue_slots[3].brupdate.b2.jalr_target connect slots_3.io.brupdate.b2.pc_sel, issue_slots[3].brupdate.b2.pc_sel connect slots_3.io.brupdate.b2.cfi_type, issue_slots[3].brupdate.b2.cfi_type connect slots_3.io.brupdate.b2.taken, issue_slots[3].brupdate.b2.taken connect slots_3.io.brupdate.b2.mispredict, issue_slots[3].brupdate.b2.mispredict connect slots_3.io.brupdate.b2.uop.debug_tsrc, issue_slots[3].brupdate.b2.uop.debug_tsrc connect slots_3.io.brupdate.b2.uop.debug_fsrc, issue_slots[3].brupdate.b2.uop.debug_fsrc connect slots_3.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[3].brupdate.b2.uop.bp_xcpt_if connect slots_3.io.brupdate.b2.uop.bp_debug_if, issue_slots[3].brupdate.b2.uop.bp_debug_if connect slots_3.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[3].brupdate.b2.uop.xcpt_ma_if connect slots_3.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[3].brupdate.b2.uop.xcpt_ae_if connect slots_3.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[3].brupdate.b2.uop.xcpt_pf_if connect slots_3.io.brupdate.b2.uop.fp_typ, issue_slots[3].brupdate.b2.uop.fp_typ connect slots_3.io.brupdate.b2.uop.fp_rm, issue_slots[3].brupdate.b2.uop.fp_rm connect slots_3.io.brupdate.b2.uop.fp_val, issue_slots[3].brupdate.b2.uop.fp_val connect slots_3.io.brupdate.b2.uop.fcn_op, issue_slots[3].brupdate.b2.uop.fcn_op connect slots_3.io.brupdate.b2.uop.fcn_dw, issue_slots[3].brupdate.b2.uop.fcn_dw connect slots_3.io.brupdate.b2.uop.frs3_en, issue_slots[3].brupdate.b2.uop.frs3_en connect slots_3.io.brupdate.b2.uop.lrs2_rtype, issue_slots[3].brupdate.b2.uop.lrs2_rtype connect slots_3.io.brupdate.b2.uop.lrs1_rtype, issue_slots[3].brupdate.b2.uop.lrs1_rtype connect slots_3.io.brupdate.b2.uop.dst_rtype, issue_slots[3].brupdate.b2.uop.dst_rtype connect slots_3.io.brupdate.b2.uop.lrs3, issue_slots[3].brupdate.b2.uop.lrs3 connect slots_3.io.brupdate.b2.uop.lrs2, issue_slots[3].brupdate.b2.uop.lrs2 connect slots_3.io.brupdate.b2.uop.lrs1, issue_slots[3].brupdate.b2.uop.lrs1 connect slots_3.io.brupdate.b2.uop.ldst, issue_slots[3].brupdate.b2.uop.ldst connect slots_3.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[3].brupdate.b2.uop.ldst_is_rs1 connect slots_3.io.brupdate.b2.uop.csr_cmd, issue_slots[3].brupdate.b2.uop.csr_cmd connect slots_3.io.brupdate.b2.uop.flush_on_commit, issue_slots[3].brupdate.b2.uop.flush_on_commit connect slots_3.io.brupdate.b2.uop.is_unique, issue_slots[3].brupdate.b2.uop.is_unique connect slots_3.io.brupdate.b2.uop.uses_stq, issue_slots[3].brupdate.b2.uop.uses_stq connect slots_3.io.brupdate.b2.uop.uses_ldq, issue_slots[3].brupdate.b2.uop.uses_ldq connect slots_3.io.brupdate.b2.uop.mem_signed, issue_slots[3].brupdate.b2.uop.mem_signed connect slots_3.io.brupdate.b2.uop.mem_size, issue_slots[3].brupdate.b2.uop.mem_size connect slots_3.io.brupdate.b2.uop.mem_cmd, issue_slots[3].brupdate.b2.uop.mem_cmd connect slots_3.io.brupdate.b2.uop.exc_cause, issue_slots[3].brupdate.b2.uop.exc_cause connect slots_3.io.brupdate.b2.uop.exception, issue_slots[3].brupdate.b2.uop.exception connect slots_3.io.brupdate.b2.uop.stale_pdst, issue_slots[3].brupdate.b2.uop.stale_pdst connect slots_3.io.brupdate.b2.uop.ppred_busy, issue_slots[3].brupdate.b2.uop.ppred_busy connect slots_3.io.brupdate.b2.uop.prs3_busy, issue_slots[3].brupdate.b2.uop.prs3_busy connect slots_3.io.brupdate.b2.uop.prs2_busy, issue_slots[3].brupdate.b2.uop.prs2_busy connect slots_3.io.brupdate.b2.uop.prs1_busy, issue_slots[3].brupdate.b2.uop.prs1_busy connect slots_3.io.brupdate.b2.uop.ppred, issue_slots[3].brupdate.b2.uop.ppred connect slots_3.io.brupdate.b2.uop.prs3, issue_slots[3].brupdate.b2.uop.prs3 connect slots_3.io.brupdate.b2.uop.prs2, issue_slots[3].brupdate.b2.uop.prs2 connect slots_3.io.brupdate.b2.uop.prs1, issue_slots[3].brupdate.b2.uop.prs1 connect slots_3.io.brupdate.b2.uop.pdst, issue_slots[3].brupdate.b2.uop.pdst connect slots_3.io.brupdate.b2.uop.rxq_idx, issue_slots[3].brupdate.b2.uop.rxq_idx connect slots_3.io.brupdate.b2.uop.stq_idx, issue_slots[3].brupdate.b2.uop.stq_idx connect slots_3.io.brupdate.b2.uop.ldq_idx, issue_slots[3].brupdate.b2.uop.ldq_idx connect slots_3.io.brupdate.b2.uop.rob_idx, issue_slots[3].brupdate.b2.uop.rob_idx connect slots_3.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[3].brupdate.b2.uop.fp_ctrl.vec connect slots_3.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[3].brupdate.b2.uop.fp_ctrl.wflags connect slots_3.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[3].brupdate.b2.uop.fp_ctrl.sqrt connect slots_3.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[3].brupdate.b2.uop.fp_ctrl.div connect slots_3.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[3].brupdate.b2.uop.fp_ctrl.fma connect slots_3.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[3].brupdate.b2.uop.fp_ctrl.fastpipe connect slots_3.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[3].brupdate.b2.uop.fp_ctrl.toint connect slots_3.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[3].brupdate.b2.uop.fp_ctrl.fromint connect slots_3.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[3].brupdate.b2.uop.fp_ctrl.typeTagOut connect slots_3.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[3].brupdate.b2.uop.fp_ctrl.typeTagIn connect slots_3.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[3].brupdate.b2.uop.fp_ctrl.swap23 connect slots_3.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[3].brupdate.b2.uop.fp_ctrl.swap12 connect slots_3.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[3].brupdate.b2.uop.fp_ctrl.ren3 connect slots_3.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[3].brupdate.b2.uop.fp_ctrl.ren2 connect slots_3.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[3].brupdate.b2.uop.fp_ctrl.ren1 connect slots_3.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[3].brupdate.b2.uop.fp_ctrl.wen connect slots_3.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[3].brupdate.b2.uop.fp_ctrl.ldst connect slots_3.io.brupdate.b2.uop.op2_sel, issue_slots[3].brupdate.b2.uop.op2_sel connect slots_3.io.brupdate.b2.uop.op1_sel, issue_slots[3].brupdate.b2.uop.op1_sel connect slots_3.io.brupdate.b2.uop.imm_packed, issue_slots[3].brupdate.b2.uop.imm_packed connect slots_3.io.brupdate.b2.uop.pimm, issue_slots[3].brupdate.b2.uop.pimm connect slots_3.io.brupdate.b2.uop.imm_sel, issue_slots[3].brupdate.b2.uop.imm_sel connect slots_3.io.brupdate.b2.uop.imm_rename, issue_slots[3].brupdate.b2.uop.imm_rename connect slots_3.io.brupdate.b2.uop.taken, issue_slots[3].brupdate.b2.uop.taken connect slots_3.io.brupdate.b2.uop.pc_lob, issue_slots[3].brupdate.b2.uop.pc_lob connect slots_3.io.brupdate.b2.uop.edge_inst, issue_slots[3].brupdate.b2.uop.edge_inst connect slots_3.io.brupdate.b2.uop.ftq_idx, issue_slots[3].brupdate.b2.uop.ftq_idx connect slots_3.io.brupdate.b2.uop.is_mov, issue_slots[3].brupdate.b2.uop.is_mov connect slots_3.io.brupdate.b2.uop.is_rocc, issue_slots[3].brupdate.b2.uop.is_rocc connect slots_3.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[3].brupdate.b2.uop.is_sys_pc2epc connect slots_3.io.brupdate.b2.uop.is_eret, issue_slots[3].brupdate.b2.uop.is_eret connect slots_3.io.brupdate.b2.uop.is_amo, issue_slots[3].brupdate.b2.uop.is_amo connect slots_3.io.brupdate.b2.uop.is_sfence, issue_slots[3].brupdate.b2.uop.is_sfence connect slots_3.io.brupdate.b2.uop.is_fencei, issue_slots[3].brupdate.b2.uop.is_fencei connect slots_3.io.brupdate.b2.uop.is_fence, issue_slots[3].brupdate.b2.uop.is_fence connect slots_3.io.brupdate.b2.uop.is_sfb, issue_slots[3].brupdate.b2.uop.is_sfb connect slots_3.io.brupdate.b2.uop.br_type, issue_slots[3].brupdate.b2.uop.br_type connect slots_3.io.brupdate.b2.uop.br_tag, issue_slots[3].brupdate.b2.uop.br_tag connect slots_3.io.brupdate.b2.uop.br_mask, issue_slots[3].brupdate.b2.uop.br_mask connect slots_3.io.brupdate.b2.uop.dis_col_sel, issue_slots[3].brupdate.b2.uop.dis_col_sel connect slots_3.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[3].brupdate.b2.uop.iw_p3_bypass_hint connect slots_3.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[3].brupdate.b2.uop.iw_p2_bypass_hint connect slots_3.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[3].brupdate.b2.uop.iw_p1_bypass_hint connect slots_3.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[3].brupdate.b2.uop.iw_p2_speculative_child connect slots_3.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[3].brupdate.b2.uop.iw_p1_speculative_child connect slots_3.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[3].brupdate.b2.uop.iw_issued_partial_dgen connect slots_3.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[3].brupdate.b2.uop.iw_issued_partial_agen connect slots_3.io.brupdate.b2.uop.iw_issued, issue_slots[3].brupdate.b2.uop.iw_issued connect slots_3.io.brupdate.b2.uop.fu_code[0], issue_slots[3].brupdate.b2.uop.fu_code[0] connect slots_3.io.brupdate.b2.uop.fu_code[1], issue_slots[3].brupdate.b2.uop.fu_code[1] connect slots_3.io.brupdate.b2.uop.fu_code[2], issue_slots[3].brupdate.b2.uop.fu_code[2] connect slots_3.io.brupdate.b2.uop.fu_code[3], issue_slots[3].brupdate.b2.uop.fu_code[3] connect slots_3.io.brupdate.b2.uop.fu_code[4], issue_slots[3].brupdate.b2.uop.fu_code[4] connect slots_3.io.brupdate.b2.uop.fu_code[5], issue_slots[3].brupdate.b2.uop.fu_code[5] connect slots_3.io.brupdate.b2.uop.fu_code[6], issue_slots[3].brupdate.b2.uop.fu_code[6] connect slots_3.io.brupdate.b2.uop.fu_code[7], issue_slots[3].brupdate.b2.uop.fu_code[7] connect slots_3.io.brupdate.b2.uop.fu_code[8], issue_slots[3].brupdate.b2.uop.fu_code[8] connect slots_3.io.brupdate.b2.uop.fu_code[9], issue_slots[3].brupdate.b2.uop.fu_code[9] connect slots_3.io.brupdate.b2.uop.iq_type[0], issue_slots[3].brupdate.b2.uop.iq_type[0] connect slots_3.io.brupdate.b2.uop.iq_type[1], issue_slots[3].brupdate.b2.uop.iq_type[1] connect slots_3.io.brupdate.b2.uop.iq_type[2], issue_slots[3].brupdate.b2.uop.iq_type[2] connect slots_3.io.brupdate.b2.uop.iq_type[3], issue_slots[3].brupdate.b2.uop.iq_type[3] connect slots_3.io.brupdate.b2.uop.debug_pc, issue_slots[3].brupdate.b2.uop.debug_pc connect slots_3.io.brupdate.b2.uop.is_rvc, issue_slots[3].brupdate.b2.uop.is_rvc connect slots_3.io.brupdate.b2.uop.debug_inst, issue_slots[3].brupdate.b2.uop.debug_inst connect slots_3.io.brupdate.b2.uop.inst, issue_slots[3].brupdate.b2.uop.inst connect slots_3.io.brupdate.b1.mispredict_mask, issue_slots[3].brupdate.b1.mispredict_mask connect slots_3.io.brupdate.b1.resolve_mask, issue_slots[3].brupdate.b1.resolve_mask connect issue_slots[3].out_uop.debug_tsrc, slots_3.io.out_uop.debug_tsrc connect issue_slots[3].out_uop.debug_fsrc, slots_3.io.out_uop.debug_fsrc connect issue_slots[3].out_uop.bp_xcpt_if, slots_3.io.out_uop.bp_xcpt_if connect issue_slots[3].out_uop.bp_debug_if, slots_3.io.out_uop.bp_debug_if connect issue_slots[3].out_uop.xcpt_ma_if, slots_3.io.out_uop.xcpt_ma_if connect issue_slots[3].out_uop.xcpt_ae_if, slots_3.io.out_uop.xcpt_ae_if connect issue_slots[3].out_uop.xcpt_pf_if, slots_3.io.out_uop.xcpt_pf_if connect issue_slots[3].out_uop.fp_typ, slots_3.io.out_uop.fp_typ connect issue_slots[3].out_uop.fp_rm, slots_3.io.out_uop.fp_rm connect issue_slots[3].out_uop.fp_val, slots_3.io.out_uop.fp_val connect issue_slots[3].out_uop.fcn_op, slots_3.io.out_uop.fcn_op connect issue_slots[3].out_uop.fcn_dw, slots_3.io.out_uop.fcn_dw connect issue_slots[3].out_uop.frs3_en, slots_3.io.out_uop.frs3_en connect issue_slots[3].out_uop.lrs2_rtype, slots_3.io.out_uop.lrs2_rtype connect issue_slots[3].out_uop.lrs1_rtype, slots_3.io.out_uop.lrs1_rtype connect issue_slots[3].out_uop.dst_rtype, slots_3.io.out_uop.dst_rtype connect issue_slots[3].out_uop.lrs3, slots_3.io.out_uop.lrs3 connect issue_slots[3].out_uop.lrs2, slots_3.io.out_uop.lrs2 connect issue_slots[3].out_uop.lrs1, slots_3.io.out_uop.lrs1 connect issue_slots[3].out_uop.ldst, slots_3.io.out_uop.ldst connect issue_slots[3].out_uop.ldst_is_rs1, slots_3.io.out_uop.ldst_is_rs1 connect issue_slots[3].out_uop.csr_cmd, slots_3.io.out_uop.csr_cmd connect issue_slots[3].out_uop.flush_on_commit, slots_3.io.out_uop.flush_on_commit connect issue_slots[3].out_uop.is_unique, slots_3.io.out_uop.is_unique connect issue_slots[3].out_uop.uses_stq, slots_3.io.out_uop.uses_stq connect issue_slots[3].out_uop.uses_ldq, slots_3.io.out_uop.uses_ldq connect issue_slots[3].out_uop.mem_signed, slots_3.io.out_uop.mem_signed connect issue_slots[3].out_uop.mem_size, slots_3.io.out_uop.mem_size connect issue_slots[3].out_uop.mem_cmd, slots_3.io.out_uop.mem_cmd connect issue_slots[3].out_uop.exc_cause, slots_3.io.out_uop.exc_cause connect issue_slots[3].out_uop.exception, slots_3.io.out_uop.exception connect issue_slots[3].out_uop.stale_pdst, slots_3.io.out_uop.stale_pdst connect issue_slots[3].out_uop.ppred_busy, slots_3.io.out_uop.ppred_busy connect issue_slots[3].out_uop.prs3_busy, slots_3.io.out_uop.prs3_busy connect issue_slots[3].out_uop.prs2_busy, slots_3.io.out_uop.prs2_busy connect issue_slots[3].out_uop.prs1_busy, slots_3.io.out_uop.prs1_busy connect issue_slots[3].out_uop.ppred, slots_3.io.out_uop.ppred connect issue_slots[3].out_uop.prs3, slots_3.io.out_uop.prs3 connect issue_slots[3].out_uop.prs2, slots_3.io.out_uop.prs2 connect issue_slots[3].out_uop.prs1, slots_3.io.out_uop.prs1 connect issue_slots[3].out_uop.pdst, slots_3.io.out_uop.pdst connect issue_slots[3].out_uop.rxq_idx, slots_3.io.out_uop.rxq_idx connect issue_slots[3].out_uop.stq_idx, slots_3.io.out_uop.stq_idx connect issue_slots[3].out_uop.ldq_idx, slots_3.io.out_uop.ldq_idx connect issue_slots[3].out_uop.rob_idx, slots_3.io.out_uop.rob_idx connect issue_slots[3].out_uop.fp_ctrl.vec, slots_3.io.out_uop.fp_ctrl.vec connect issue_slots[3].out_uop.fp_ctrl.wflags, slots_3.io.out_uop.fp_ctrl.wflags connect issue_slots[3].out_uop.fp_ctrl.sqrt, slots_3.io.out_uop.fp_ctrl.sqrt connect issue_slots[3].out_uop.fp_ctrl.div, slots_3.io.out_uop.fp_ctrl.div connect issue_slots[3].out_uop.fp_ctrl.fma, slots_3.io.out_uop.fp_ctrl.fma connect issue_slots[3].out_uop.fp_ctrl.fastpipe, slots_3.io.out_uop.fp_ctrl.fastpipe connect issue_slots[3].out_uop.fp_ctrl.toint, slots_3.io.out_uop.fp_ctrl.toint connect issue_slots[3].out_uop.fp_ctrl.fromint, slots_3.io.out_uop.fp_ctrl.fromint connect issue_slots[3].out_uop.fp_ctrl.typeTagOut, slots_3.io.out_uop.fp_ctrl.typeTagOut connect issue_slots[3].out_uop.fp_ctrl.typeTagIn, slots_3.io.out_uop.fp_ctrl.typeTagIn connect issue_slots[3].out_uop.fp_ctrl.swap23, slots_3.io.out_uop.fp_ctrl.swap23 connect issue_slots[3].out_uop.fp_ctrl.swap12, slots_3.io.out_uop.fp_ctrl.swap12 connect issue_slots[3].out_uop.fp_ctrl.ren3, slots_3.io.out_uop.fp_ctrl.ren3 connect issue_slots[3].out_uop.fp_ctrl.ren2, slots_3.io.out_uop.fp_ctrl.ren2 connect issue_slots[3].out_uop.fp_ctrl.ren1, slots_3.io.out_uop.fp_ctrl.ren1 connect issue_slots[3].out_uop.fp_ctrl.wen, slots_3.io.out_uop.fp_ctrl.wen connect issue_slots[3].out_uop.fp_ctrl.ldst, slots_3.io.out_uop.fp_ctrl.ldst connect issue_slots[3].out_uop.op2_sel, slots_3.io.out_uop.op2_sel connect issue_slots[3].out_uop.op1_sel, slots_3.io.out_uop.op1_sel connect issue_slots[3].out_uop.imm_packed, slots_3.io.out_uop.imm_packed connect issue_slots[3].out_uop.pimm, slots_3.io.out_uop.pimm connect issue_slots[3].out_uop.imm_sel, slots_3.io.out_uop.imm_sel connect issue_slots[3].out_uop.imm_rename, slots_3.io.out_uop.imm_rename connect issue_slots[3].out_uop.taken, slots_3.io.out_uop.taken connect issue_slots[3].out_uop.pc_lob, slots_3.io.out_uop.pc_lob connect issue_slots[3].out_uop.edge_inst, slots_3.io.out_uop.edge_inst connect issue_slots[3].out_uop.ftq_idx, slots_3.io.out_uop.ftq_idx connect issue_slots[3].out_uop.is_mov, slots_3.io.out_uop.is_mov connect issue_slots[3].out_uop.is_rocc, slots_3.io.out_uop.is_rocc connect issue_slots[3].out_uop.is_sys_pc2epc, slots_3.io.out_uop.is_sys_pc2epc connect issue_slots[3].out_uop.is_eret, slots_3.io.out_uop.is_eret connect issue_slots[3].out_uop.is_amo, slots_3.io.out_uop.is_amo connect issue_slots[3].out_uop.is_sfence, slots_3.io.out_uop.is_sfence connect issue_slots[3].out_uop.is_fencei, slots_3.io.out_uop.is_fencei connect issue_slots[3].out_uop.is_fence, slots_3.io.out_uop.is_fence connect issue_slots[3].out_uop.is_sfb, slots_3.io.out_uop.is_sfb connect issue_slots[3].out_uop.br_type, slots_3.io.out_uop.br_type connect issue_slots[3].out_uop.br_tag, slots_3.io.out_uop.br_tag connect issue_slots[3].out_uop.br_mask, slots_3.io.out_uop.br_mask connect issue_slots[3].out_uop.dis_col_sel, slots_3.io.out_uop.dis_col_sel connect issue_slots[3].out_uop.iw_p3_bypass_hint, slots_3.io.out_uop.iw_p3_bypass_hint connect issue_slots[3].out_uop.iw_p2_bypass_hint, slots_3.io.out_uop.iw_p2_bypass_hint connect issue_slots[3].out_uop.iw_p1_bypass_hint, slots_3.io.out_uop.iw_p1_bypass_hint connect issue_slots[3].out_uop.iw_p2_speculative_child, slots_3.io.out_uop.iw_p2_speculative_child connect issue_slots[3].out_uop.iw_p1_speculative_child, slots_3.io.out_uop.iw_p1_speculative_child connect issue_slots[3].out_uop.iw_issued_partial_dgen, slots_3.io.out_uop.iw_issued_partial_dgen connect issue_slots[3].out_uop.iw_issued_partial_agen, slots_3.io.out_uop.iw_issued_partial_agen connect issue_slots[3].out_uop.iw_issued, slots_3.io.out_uop.iw_issued connect issue_slots[3].out_uop.fu_code[0], slots_3.io.out_uop.fu_code[0] connect issue_slots[3].out_uop.fu_code[1], slots_3.io.out_uop.fu_code[1] connect issue_slots[3].out_uop.fu_code[2], slots_3.io.out_uop.fu_code[2] connect issue_slots[3].out_uop.fu_code[3], slots_3.io.out_uop.fu_code[3] connect issue_slots[3].out_uop.fu_code[4], slots_3.io.out_uop.fu_code[4] connect issue_slots[3].out_uop.fu_code[5], slots_3.io.out_uop.fu_code[5] connect issue_slots[3].out_uop.fu_code[6], slots_3.io.out_uop.fu_code[6] connect issue_slots[3].out_uop.fu_code[7], slots_3.io.out_uop.fu_code[7] connect issue_slots[3].out_uop.fu_code[8], slots_3.io.out_uop.fu_code[8] connect issue_slots[3].out_uop.fu_code[9], slots_3.io.out_uop.fu_code[9] connect issue_slots[3].out_uop.iq_type[0], slots_3.io.out_uop.iq_type[0] connect issue_slots[3].out_uop.iq_type[1], slots_3.io.out_uop.iq_type[1] connect issue_slots[3].out_uop.iq_type[2], slots_3.io.out_uop.iq_type[2] connect issue_slots[3].out_uop.iq_type[3], slots_3.io.out_uop.iq_type[3] connect issue_slots[3].out_uop.debug_pc, slots_3.io.out_uop.debug_pc connect issue_slots[3].out_uop.is_rvc, slots_3.io.out_uop.is_rvc connect issue_slots[3].out_uop.debug_inst, slots_3.io.out_uop.debug_inst connect issue_slots[3].out_uop.inst, slots_3.io.out_uop.inst connect slots_3.io.in_uop.bits.debug_tsrc, issue_slots[3].in_uop.bits.debug_tsrc connect slots_3.io.in_uop.bits.debug_fsrc, issue_slots[3].in_uop.bits.debug_fsrc connect slots_3.io.in_uop.bits.bp_xcpt_if, issue_slots[3].in_uop.bits.bp_xcpt_if connect slots_3.io.in_uop.bits.bp_debug_if, issue_slots[3].in_uop.bits.bp_debug_if connect slots_3.io.in_uop.bits.xcpt_ma_if, issue_slots[3].in_uop.bits.xcpt_ma_if connect slots_3.io.in_uop.bits.xcpt_ae_if, issue_slots[3].in_uop.bits.xcpt_ae_if connect slots_3.io.in_uop.bits.xcpt_pf_if, issue_slots[3].in_uop.bits.xcpt_pf_if connect slots_3.io.in_uop.bits.fp_typ, issue_slots[3].in_uop.bits.fp_typ connect slots_3.io.in_uop.bits.fp_rm, issue_slots[3].in_uop.bits.fp_rm connect slots_3.io.in_uop.bits.fp_val, issue_slots[3].in_uop.bits.fp_val connect slots_3.io.in_uop.bits.fcn_op, issue_slots[3].in_uop.bits.fcn_op connect slots_3.io.in_uop.bits.fcn_dw, issue_slots[3].in_uop.bits.fcn_dw connect slots_3.io.in_uop.bits.frs3_en, issue_slots[3].in_uop.bits.frs3_en connect slots_3.io.in_uop.bits.lrs2_rtype, issue_slots[3].in_uop.bits.lrs2_rtype connect slots_3.io.in_uop.bits.lrs1_rtype, issue_slots[3].in_uop.bits.lrs1_rtype connect slots_3.io.in_uop.bits.dst_rtype, issue_slots[3].in_uop.bits.dst_rtype connect slots_3.io.in_uop.bits.lrs3, issue_slots[3].in_uop.bits.lrs3 connect slots_3.io.in_uop.bits.lrs2, issue_slots[3].in_uop.bits.lrs2 connect slots_3.io.in_uop.bits.lrs1, issue_slots[3].in_uop.bits.lrs1 connect slots_3.io.in_uop.bits.ldst, issue_slots[3].in_uop.bits.ldst connect slots_3.io.in_uop.bits.ldst_is_rs1, issue_slots[3].in_uop.bits.ldst_is_rs1 connect slots_3.io.in_uop.bits.csr_cmd, issue_slots[3].in_uop.bits.csr_cmd connect slots_3.io.in_uop.bits.flush_on_commit, issue_slots[3].in_uop.bits.flush_on_commit connect slots_3.io.in_uop.bits.is_unique, issue_slots[3].in_uop.bits.is_unique connect slots_3.io.in_uop.bits.uses_stq, issue_slots[3].in_uop.bits.uses_stq connect slots_3.io.in_uop.bits.uses_ldq, issue_slots[3].in_uop.bits.uses_ldq connect slots_3.io.in_uop.bits.mem_signed, issue_slots[3].in_uop.bits.mem_signed connect slots_3.io.in_uop.bits.mem_size, issue_slots[3].in_uop.bits.mem_size connect slots_3.io.in_uop.bits.mem_cmd, issue_slots[3].in_uop.bits.mem_cmd connect slots_3.io.in_uop.bits.exc_cause, issue_slots[3].in_uop.bits.exc_cause connect slots_3.io.in_uop.bits.exception, issue_slots[3].in_uop.bits.exception connect slots_3.io.in_uop.bits.stale_pdst, issue_slots[3].in_uop.bits.stale_pdst connect slots_3.io.in_uop.bits.ppred_busy, issue_slots[3].in_uop.bits.ppred_busy connect slots_3.io.in_uop.bits.prs3_busy, issue_slots[3].in_uop.bits.prs3_busy connect slots_3.io.in_uop.bits.prs2_busy, issue_slots[3].in_uop.bits.prs2_busy connect slots_3.io.in_uop.bits.prs1_busy, issue_slots[3].in_uop.bits.prs1_busy connect slots_3.io.in_uop.bits.ppred, issue_slots[3].in_uop.bits.ppred connect slots_3.io.in_uop.bits.prs3, issue_slots[3].in_uop.bits.prs3 connect slots_3.io.in_uop.bits.prs2, issue_slots[3].in_uop.bits.prs2 connect slots_3.io.in_uop.bits.prs1, issue_slots[3].in_uop.bits.prs1 connect slots_3.io.in_uop.bits.pdst, issue_slots[3].in_uop.bits.pdst connect slots_3.io.in_uop.bits.rxq_idx, issue_slots[3].in_uop.bits.rxq_idx connect slots_3.io.in_uop.bits.stq_idx, issue_slots[3].in_uop.bits.stq_idx connect slots_3.io.in_uop.bits.ldq_idx, issue_slots[3].in_uop.bits.ldq_idx connect slots_3.io.in_uop.bits.rob_idx, issue_slots[3].in_uop.bits.rob_idx connect slots_3.io.in_uop.bits.fp_ctrl.vec, issue_slots[3].in_uop.bits.fp_ctrl.vec connect slots_3.io.in_uop.bits.fp_ctrl.wflags, issue_slots[3].in_uop.bits.fp_ctrl.wflags connect slots_3.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[3].in_uop.bits.fp_ctrl.sqrt connect slots_3.io.in_uop.bits.fp_ctrl.div, issue_slots[3].in_uop.bits.fp_ctrl.div connect slots_3.io.in_uop.bits.fp_ctrl.fma, issue_slots[3].in_uop.bits.fp_ctrl.fma connect slots_3.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[3].in_uop.bits.fp_ctrl.fastpipe connect slots_3.io.in_uop.bits.fp_ctrl.toint, issue_slots[3].in_uop.bits.fp_ctrl.toint connect slots_3.io.in_uop.bits.fp_ctrl.fromint, issue_slots[3].in_uop.bits.fp_ctrl.fromint connect slots_3.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[3].in_uop.bits.fp_ctrl.typeTagOut connect slots_3.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[3].in_uop.bits.fp_ctrl.typeTagIn connect slots_3.io.in_uop.bits.fp_ctrl.swap23, issue_slots[3].in_uop.bits.fp_ctrl.swap23 connect slots_3.io.in_uop.bits.fp_ctrl.swap12, issue_slots[3].in_uop.bits.fp_ctrl.swap12 connect slots_3.io.in_uop.bits.fp_ctrl.ren3, issue_slots[3].in_uop.bits.fp_ctrl.ren3 connect slots_3.io.in_uop.bits.fp_ctrl.ren2, issue_slots[3].in_uop.bits.fp_ctrl.ren2 connect slots_3.io.in_uop.bits.fp_ctrl.ren1, issue_slots[3].in_uop.bits.fp_ctrl.ren1 connect slots_3.io.in_uop.bits.fp_ctrl.wen, issue_slots[3].in_uop.bits.fp_ctrl.wen connect slots_3.io.in_uop.bits.fp_ctrl.ldst, issue_slots[3].in_uop.bits.fp_ctrl.ldst connect slots_3.io.in_uop.bits.op2_sel, issue_slots[3].in_uop.bits.op2_sel connect slots_3.io.in_uop.bits.op1_sel, issue_slots[3].in_uop.bits.op1_sel connect slots_3.io.in_uop.bits.imm_packed, issue_slots[3].in_uop.bits.imm_packed connect slots_3.io.in_uop.bits.pimm, issue_slots[3].in_uop.bits.pimm connect slots_3.io.in_uop.bits.imm_sel, issue_slots[3].in_uop.bits.imm_sel connect slots_3.io.in_uop.bits.imm_rename, issue_slots[3].in_uop.bits.imm_rename connect slots_3.io.in_uop.bits.taken, issue_slots[3].in_uop.bits.taken connect slots_3.io.in_uop.bits.pc_lob, issue_slots[3].in_uop.bits.pc_lob connect slots_3.io.in_uop.bits.edge_inst, issue_slots[3].in_uop.bits.edge_inst connect slots_3.io.in_uop.bits.ftq_idx, issue_slots[3].in_uop.bits.ftq_idx connect slots_3.io.in_uop.bits.is_mov, issue_slots[3].in_uop.bits.is_mov connect slots_3.io.in_uop.bits.is_rocc, issue_slots[3].in_uop.bits.is_rocc connect slots_3.io.in_uop.bits.is_sys_pc2epc, issue_slots[3].in_uop.bits.is_sys_pc2epc connect slots_3.io.in_uop.bits.is_eret, issue_slots[3].in_uop.bits.is_eret connect slots_3.io.in_uop.bits.is_amo, issue_slots[3].in_uop.bits.is_amo connect slots_3.io.in_uop.bits.is_sfence, issue_slots[3].in_uop.bits.is_sfence connect slots_3.io.in_uop.bits.is_fencei, issue_slots[3].in_uop.bits.is_fencei connect slots_3.io.in_uop.bits.is_fence, issue_slots[3].in_uop.bits.is_fence connect slots_3.io.in_uop.bits.is_sfb, issue_slots[3].in_uop.bits.is_sfb connect slots_3.io.in_uop.bits.br_type, issue_slots[3].in_uop.bits.br_type connect slots_3.io.in_uop.bits.br_tag, issue_slots[3].in_uop.bits.br_tag connect slots_3.io.in_uop.bits.br_mask, issue_slots[3].in_uop.bits.br_mask connect slots_3.io.in_uop.bits.dis_col_sel, issue_slots[3].in_uop.bits.dis_col_sel connect slots_3.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[3].in_uop.bits.iw_p3_bypass_hint connect slots_3.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[3].in_uop.bits.iw_p2_bypass_hint connect slots_3.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[3].in_uop.bits.iw_p1_bypass_hint connect slots_3.io.in_uop.bits.iw_p2_speculative_child, issue_slots[3].in_uop.bits.iw_p2_speculative_child connect slots_3.io.in_uop.bits.iw_p1_speculative_child, issue_slots[3].in_uop.bits.iw_p1_speculative_child connect slots_3.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[3].in_uop.bits.iw_issued_partial_dgen connect slots_3.io.in_uop.bits.iw_issued_partial_agen, issue_slots[3].in_uop.bits.iw_issued_partial_agen connect slots_3.io.in_uop.bits.iw_issued, issue_slots[3].in_uop.bits.iw_issued connect slots_3.io.in_uop.bits.fu_code[0], issue_slots[3].in_uop.bits.fu_code[0] connect slots_3.io.in_uop.bits.fu_code[1], issue_slots[3].in_uop.bits.fu_code[1] connect slots_3.io.in_uop.bits.fu_code[2], issue_slots[3].in_uop.bits.fu_code[2] connect slots_3.io.in_uop.bits.fu_code[3], issue_slots[3].in_uop.bits.fu_code[3] connect slots_3.io.in_uop.bits.fu_code[4], issue_slots[3].in_uop.bits.fu_code[4] connect slots_3.io.in_uop.bits.fu_code[5], issue_slots[3].in_uop.bits.fu_code[5] connect slots_3.io.in_uop.bits.fu_code[6], issue_slots[3].in_uop.bits.fu_code[6] connect slots_3.io.in_uop.bits.fu_code[7], issue_slots[3].in_uop.bits.fu_code[7] connect slots_3.io.in_uop.bits.fu_code[8], issue_slots[3].in_uop.bits.fu_code[8] connect slots_3.io.in_uop.bits.fu_code[9], issue_slots[3].in_uop.bits.fu_code[9] connect slots_3.io.in_uop.bits.iq_type[0], issue_slots[3].in_uop.bits.iq_type[0] connect slots_3.io.in_uop.bits.iq_type[1], issue_slots[3].in_uop.bits.iq_type[1] connect slots_3.io.in_uop.bits.iq_type[2], issue_slots[3].in_uop.bits.iq_type[2] connect slots_3.io.in_uop.bits.iq_type[3], issue_slots[3].in_uop.bits.iq_type[3] connect slots_3.io.in_uop.bits.debug_pc, issue_slots[3].in_uop.bits.debug_pc connect slots_3.io.in_uop.bits.is_rvc, issue_slots[3].in_uop.bits.is_rvc connect slots_3.io.in_uop.bits.debug_inst, issue_slots[3].in_uop.bits.debug_inst connect slots_3.io.in_uop.bits.inst, issue_slots[3].in_uop.bits.inst connect slots_3.io.in_uop.valid, issue_slots[3].in_uop.valid connect issue_slots[3].iss_uop.debug_tsrc, slots_3.io.iss_uop.debug_tsrc connect issue_slots[3].iss_uop.debug_fsrc, slots_3.io.iss_uop.debug_fsrc connect issue_slots[3].iss_uop.bp_xcpt_if, slots_3.io.iss_uop.bp_xcpt_if connect issue_slots[3].iss_uop.bp_debug_if, slots_3.io.iss_uop.bp_debug_if connect issue_slots[3].iss_uop.xcpt_ma_if, slots_3.io.iss_uop.xcpt_ma_if connect issue_slots[3].iss_uop.xcpt_ae_if, slots_3.io.iss_uop.xcpt_ae_if connect issue_slots[3].iss_uop.xcpt_pf_if, slots_3.io.iss_uop.xcpt_pf_if connect issue_slots[3].iss_uop.fp_typ, slots_3.io.iss_uop.fp_typ connect issue_slots[3].iss_uop.fp_rm, slots_3.io.iss_uop.fp_rm connect issue_slots[3].iss_uop.fp_val, slots_3.io.iss_uop.fp_val connect issue_slots[3].iss_uop.fcn_op, slots_3.io.iss_uop.fcn_op connect issue_slots[3].iss_uop.fcn_dw, slots_3.io.iss_uop.fcn_dw connect issue_slots[3].iss_uop.frs3_en, slots_3.io.iss_uop.frs3_en connect issue_slots[3].iss_uop.lrs2_rtype, slots_3.io.iss_uop.lrs2_rtype connect issue_slots[3].iss_uop.lrs1_rtype, slots_3.io.iss_uop.lrs1_rtype connect issue_slots[3].iss_uop.dst_rtype, slots_3.io.iss_uop.dst_rtype connect issue_slots[3].iss_uop.lrs3, slots_3.io.iss_uop.lrs3 connect issue_slots[3].iss_uop.lrs2, slots_3.io.iss_uop.lrs2 connect issue_slots[3].iss_uop.lrs1, slots_3.io.iss_uop.lrs1 connect issue_slots[3].iss_uop.ldst, slots_3.io.iss_uop.ldst connect issue_slots[3].iss_uop.ldst_is_rs1, slots_3.io.iss_uop.ldst_is_rs1 connect issue_slots[3].iss_uop.csr_cmd, slots_3.io.iss_uop.csr_cmd connect issue_slots[3].iss_uop.flush_on_commit, slots_3.io.iss_uop.flush_on_commit connect issue_slots[3].iss_uop.is_unique, slots_3.io.iss_uop.is_unique connect issue_slots[3].iss_uop.uses_stq, slots_3.io.iss_uop.uses_stq connect issue_slots[3].iss_uop.uses_ldq, slots_3.io.iss_uop.uses_ldq connect issue_slots[3].iss_uop.mem_signed, slots_3.io.iss_uop.mem_signed connect issue_slots[3].iss_uop.mem_size, slots_3.io.iss_uop.mem_size connect issue_slots[3].iss_uop.mem_cmd, slots_3.io.iss_uop.mem_cmd connect issue_slots[3].iss_uop.exc_cause, slots_3.io.iss_uop.exc_cause connect issue_slots[3].iss_uop.exception, slots_3.io.iss_uop.exception connect issue_slots[3].iss_uop.stale_pdst, slots_3.io.iss_uop.stale_pdst connect issue_slots[3].iss_uop.ppred_busy, slots_3.io.iss_uop.ppred_busy connect issue_slots[3].iss_uop.prs3_busy, slots_3.io.iss_uop.prs3_busy connect issue_slots[3].iss_uop.prs2_busy, slots_3.io.iss_uop.prs2_busy connect issue_slots[3].iss_uop.prs1_busy, slots_3.io.iss_uop.prs1_busy connect issue_slots[3].iss_uop.ppred, slots_3.io.iss_uop.ppred connect issue_slots[3].iss_uop.prs3, slots_3.io.iss_uop.prs3 connect issue_slots[3].iss_uop.prs2, slots_3.io.iss_uop.prs2 connect issue_slots[3].iss_uop.prs1, slots_3.io.iss_uop.prs1 connect issue_slots[3].iss_uop.pdst, slots_3.io.iss_uop.pdst connect issue_slots[3].iss_uop.rxq_idx, slots_3.io.iss_uop.rxq_idx connect issue_slots[3].iss_uop.stq_idx, slots_3.io.iss_uop.stq_idx connect issue_slots[3].iss_uop.ldq_idx, slots_3.io.iss_uop.ldq_idx connect issue_slots[3].iss_uop.rob_idx, slots_3.io.iss_uop.rob_idx connect issue_slots[3].iss_uop.fp_ctrl.vec, slots_3.io.iss_uop.fp_ctrl.vec connect issue_slots[3].iss_uop.fp_ctrl.wflags, slots_3.io.iss_uop.fp_ctrl.wflags connect issue_slots[3].iss_uop.fp_ctrl.sqrt, slots_3.io.iss_uop.fp_ctrl.sqrt connect issue_slots[3].iss_uop.fp_ctrl.div, slots_3.io.iss_uop.fp_ctrl.div connect issue_slots[3].iss_uop.fp_ctrl.fma, slots_3.io.iss_uop.fp_ctrl.fma connect issue_slots[3].iss_uop.fp_ctrl.fastpipe, slots_3.io.iss_uop.fp_ctrl.fastpipe connect issue_slots[3].iss_uop.fp_ctrl.toint, slots_3.io.iss_uop.fp_ctrl.toint connect issue_slots[3].iss_uop.fp_ctrl.fromint, slots_3.io.iss_uop.fp_ctrl.fromint connect issue_slots[3].iss_uop.fp_ctrl.typeTagOut, slots_3.io.iss_uop.fp_ctrl.typeTagOut connect issue_slots[3].iss_uop.fp_ctrl.typeTagIn, slots_3.io.iss_uop.fp_ctrl.typeTagIn connect issue_slots[3].iss_uop.fp_ctrl.swap23, slots_3.io.iss_uop.fp_ctrl.swap23 connect issue_slots[3].iss_uop.fp_ctrl.swap12, slots_3.io.iss_uop.fp_ctrl.swap12 connect issue_slots[3].iss_uop.fp_ctrl.ren3, slots_3.io.iss_uop.fp_ctrl.ren3 connect issue_slots[3].iss_uop.fp_ctrl.ren2, slots_3.io.iss_uop.fp_ctrl.ren2 connect issue_slots[3].iss_uop.fp_ctrl.ren1, slots_3.io.iss_uop.fp_ctrl.ren1 connect issue_slots[3].iss_uop.fp_ctrl.wen, slots_3.io.iss_uop.fp_ctrl.wen connect issue_slots[3].iss_uop.fp_ctrl.ldst, slots_3.io.iss_uop.fp_ctrl.ldst connect issue_slots[3].iss_uop.op2_sel, slots_3.io.iss_uop.op2_sel connect issue_slots[3].iss_uop.op1_sel, slots_3.io.iss_uop.op1_sel connect issue_slots[3].iss_uop.imm_packed, slots_3.io.iss_uop.imm_packed connect issue_slots[3].iss_uop.pimm, slots_3.io.iss_uop.pimm connect issue_slots[3].iss_uop.imm_sel, slots_3.io.iss_uop.imm_sel connect issue_slots[3].iss_uop.imm_rename, slots_3.io.iss_uop.imm_rename connect issue_slots[3].iss_uop.taken, slots_3.io.iss_uop.taken connect issue_slots[3].iss_uop.pc_lob, slots_3.io.iss_uop.pc_lob connect issue_slots[3].iss_uop.edge_inst, slots_3.io.iss_uop.edge_inst connect issue_slots[3].iss_uop.ftq_idx, slots_3.io.iss_uop.ftq_idx connect issue_slots[3].iss_uop.is_mov, slots_3.io.iss_uop.is_mov connect issue_slots[3].iss_uop.is_rocc, slots_3.io.iss_uop.is_rocc connect issue_slots[3].iss_uop.is_sys_pc2epc, slots_3.io.iss_uop.is_sys_pc2epc connect issue_slots[3].iss_uop.is_eret, slots_3.io.iss_uop.is_eret connect issue_slots[3].iss_uop.is_amo, slots_3.io.iss_uop.is_amo connect issue_slots[3].iss_uop.is_sfence, slots_3.io.iss_uop.is_sfence connect issue_slots[3].iss_uop.is_fencei, slots_3.io.iss_uop.is_fencei connect issue_slots[3].iss_uop.is_fence, slots_3.io.iss_uop.is_fence connect issue_slots[3].iss_uop.is_sfb, slots_3.io.iss_uop.is_sfb connect issue_slots[3].iss_uop.br_type, slots_3.io.iss_uop.br_type connect issue_slots[3].iss_uop.br_tag, slots_3.io.iss_uop.br_tag connect issue_slots[3].iss_uop.br_mask, slots_3.io.iss_uop.br_mask connect issue_slots[3].iss_uop.dis_col_sel, slots_3.io.iss_uop.dis_col_sel connect issue_slots[3].iss_uop.iw_p3_bypass_hint, slots_3.io.iss_uop.iw_p3_bypass_hint connect issue_slots[3].iss_uop.iw_p2_bypass_hint, slots_3.io.iss_uop.iw_p2_bypass_hint connect issue_slots[3].iss_uop.iw_p1_bypass_hint, slots_3.io.iss_uop.iw_p1_bypass_hint connect issue_slots[3].iss_uop.iw_p2_speculative_child, slots_3.io.iss_uop.iw_p2_speculative_child connect issue_slots[3].iss_uop.iw_p1_speculative_child, slots_3.io.iss_uop.iw_p1_speculative_child connect issue_slots[3].iss_uop.iw_issued_partial_dgen, slots_3.io.iss_uop.iw_issued_partial_dgen connect issue_slots[3].iss_uop.iw_issued_partial_agen, slots_3.io.iss_uop.iw_issued_partial_agen connect issue_slots[3].iss_uop.iw_issued, slots_3.io.iss_uop.iw_issued connect issue_slots[3].iss_uop.fu_code[0], slots_3.io.iss_uop.fu_code[0] connect issue_slots[3].iss_uop.fu_code[1], slots_3.io.iss_uop.fu_code[1] connect issue_slots[3].iss_uop.fu_code[2], slots_3.io.iss_uop.fu_code[2] connect issue_slots[3].iss_uop.fu_code[3], slots_3.io.iss_uop.fu_code[3] connect issue_slots[3].iss_uop.fu_code[4], slots_3.io.iss_uop.fu_code[4] connect issue_slots[3].iss_uop.fu_code[5], slots_3.io.iss_uop.fu_code[5] connect issue_slots[3].iss_uop.fu_code[6], slots_3.io.iss_uop.fu_code[6] connect issue_slots[3].iss_uop.fu_code[7], slots_3.io.iss_uop.fu_code[7] connect issue_slots[3].iss_uop.fu_code[8], slots_3.io.iss_uop.fu_code[8] connect issue_slots[3].iss_uop.fu_code[9], slots_3.io.iss_uop.fu_code[9] connect issue_slots[3].iss_uop.iq_type[0], slots_3.io.iss_uop.iq_type[0] connect issue_slots[3].iss_uop.iq_type[1], slots_3.io.iss_uop.iq_type[1] connect issue_slots[3].iss_uop.iq_type[2], slots_3.io.iss_uop.iq_type[2] connect issue_slots[3].iss_uop.iq_type[3], slots_3.io.iss_uop.iq_type[3] connect issue_slots[3].iss_uop.debug_pc, slots_3.io.iss_uop.debug_pc connect issue_slots[3].iss_uop.is_rvc, slots_3.io.iss_uop.is_rvc connect issue_slots[3].iss_uop.debug_inst, slots_3.io.iss_uop.debug_inst connect issue_slots[3].iss_uop.inst, slots_3.io.iss_uop.inst connect slots_3.io.grant, issue_slots[3].grant connect issue_slots[3].request, slots_3.io.request connect issue_slots[3].will_be_valid, slots_3.io.will_be_valid connect issue_slots[3].valid, slots_3.io.valid connect slots_4.io.child_rebusys, issue_slots[4].child_rebusys connect slots_4.io.pred_wakeup_port.bits, issue_slots[4].pred_wakeup_port.bits connect slots_4.io.pred_wakeup_port.valid, issue_slots[4].pred_wakeup_port.valid connect slots_4.io.wakeup_ports[0].bits.rebusy, issue_slots[4].wakeup_ports[0].bits.rebusy connect slots_4.io.wakeup_ports[0].bits.speculative_mask, issue_slots[4].wakeup_ports[0].bits.speculative_mask connect slots_4.io.wakeup_ports[0].bits.bypassable, issue_slots[4].wakeup_ports[0].bits.bypassable connect slots_4.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[4].wakeup_ports[0].bits.uop.debug_tsrc connect slots_4.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[4].wakeup_ports[0].bits.uop.debug_fsrc connect slots_4.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[4].wakeup_ports[0].bits.uop.bp_xcpt_if connect slots_4.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[4].wakeup_ports[0].bits.uop.bp_debug_if connect slots_4.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[4].wakeup_ports[0].bits.uop.xcpt_ma_if connect slots_4.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[4].wakeup_ports[0].bits.uop.xcpt_ae_if connect slots_4.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[4].wakeup_ports[0].bits.uop.xcpt_pf_if connect slots_4.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[4].wakeup_ports[0].bits.uop.fp_typ connect slots_4.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[4].wakeup_ports[0].bits.uop.fp_rm connect slots_4.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[4].wakeup_ports[0].bits.uop.fp_val connect slots_4.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[4].wakeup_ports[0].bits.uop.fcn_op connect slots_4.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[4].wakeup_ports[0].bits.uop.fcn_dw connect slots_4.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[4].wakeup_ports[0].bits.uop.frs3_en connect slots_4.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[4].wakeup_ports[0].bits.uop.lrs2_rtype connect slots_4.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[4].wakeup_ports[0].bits.uop.lrs1_rtype connect slots_4.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[4].wakeup_ports[0].bits.uop.dst_rtype connect slots_4.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[4].wakeup_ports[0].bits.uop.lrs3 connect slots_4.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[4].wakeup_ports[0].bits.uop.lrs2 connect slots_4.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[4].wakeup_ports[0].bits.uop.lrs1 connect slots_4.io.wakeup_ports[0].bits.uop.ldst, issue_slots[4].wakeup_ports[0].bits.uop.ldst connect slots_4.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[4].wakeup_ports[0].bits.uop.ldst_is_rs1 connect slots_4.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[4].wakeup_ports[0].bits.uop.csr_cmd connect slots_4.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[4].wakeup_ports[0].bits.uop.flush_on_commit connect slots_4.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[4].wakeup_ports[0].bits.uop.is_unique connect slots_4.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[4].wakeup_ports[0].bits.uop.uses_stq connect slots_4.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[4].wakeup_ports[0].bits.uop.uses_ldq connect slots_4.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[4].wakeup_ports[0].bits.uop.mem_signed connect slots_4.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[4].wakeup_ports[0].bits.uop.mem_size connect slots_4.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[4].wakeup_ports[0].bits.uop.mem_cmd connect slots_4.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[4].wakeup_ports[0].bits.uop.exc_cause connect slots_4.io.wakeup_ports[0].bits.uop.exception, issue_slots[4].wakeup_ports[0].bits.uop.exception connect slots_4.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[4].wakeup_ports[0].bits.uop.stale_pdst connect slots_4.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[4].wakeup_ports[0].bits.uop.ppred_busy connect slots_4.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[4].wakeup_ports[0].bits.uop.prs3_busy connect slots_4.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[4].wakeup_ports[0].bits.uop.prs2_busy connect slots_4.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[4].wakeup_ports[0].bits.uop.prs1_busy connect slots_4.io.wakeup_ports[0].bits.uop.ppred, issue_slots[4].wakeup_ports[0].bits.uop.ppred connect slots_4.io.wakeup_ports[0].bits.uop.prs3, issue_slots[4].wakeup_ports[0].bits.uop.prs3 connect slots_4.io.wakeup_ports[0].bits.uop.prs2, issue_slots[4].wakeup_ports[0].bits.uop.prs2 connect slots_4.io.wakeup_ports[0].bits.uop.prs1, issue_slots[4].wakeup_ports[0].bits.uop.prs1 connect slots_4.io.wakeup_ports[0].bits.uop.pdst, issue_slots[4].wakeup_ports[0].bits.uop.pdst connect slots_4.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[4].wakeup_ports[0].bits.uop.rxq_idx connect slots_4.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[4].wakeup_ports[0].bits.uop.stq_idx connect slots_4.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[4].wakeup_ports[0].bits.uop.ldq_idx connect slots_4.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[4].wakeup_ports[0].bits.uop.rob_idx connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.vec connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.wflags connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.div connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.fma connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.toint connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.fromint connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.wen connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.ldst connect slots_4.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[4].wakeup_ports[0].bits.uop.op2_sel connect slots_4.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[4].wakeup_ports[0].bits.uop.op1_sel connect slots_4.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[4].wakeup_ports[0].bits.uop.imm_packed connect slots_4.io.wakeup_ports[0].bits.uop.pimm, issue_slots[4].wakeup_ports[0].bits.uop.pimm connect slots_4.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[4].wakeup_ports[0].bits.uop.imm_sel connect slots_4.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[4].wakeup_ports[0].bits.uop.imm_rename connect slots_4.io.wakeup_ports[0].bits.uop.taken, issue_slots[4].wakeup_ports[0].bits.uop.taken connect slots_4.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[4].wakeup_ports[0].bits.uop.pc_lob connect slots_4.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[4].wakeup_ports[0].bits.uop.edge_inst connect slots_4.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[4].wakeup_ports[0].bits.uop.ftq_idx connect slots_4.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[4].wakeup_ports[0].bits.uop.is_mov connect slots_4.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[4].wakeup_ports[0].bits.uop.is_rocc connect slots_4.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[4].wakeup_ports[0].bits.uop.is_sys_pc2epc connect slots_4.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[4].wakeup_ports[0].bits.uop.is_eret connect slots_4.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[4].wakeup_ports[0].bits.uop.is_amo connect slots_4.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[4].wakeup_ports[0].bits.uop.is_sfence connect slots_4.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[4].wakeup_ports[0].bits.uop.is_fencei connect slots_4.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[4].wakeup_ports[0].bits.uop.is_fence connect slots_4.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[4].wakeup_ports[0].bits.uop.is_sfb connect slots_4.io.wakeup_ports[0].bits.uop.br_type, issue_slots[4].wakeup_ports[0].bits.uop.br_type connect slots_4.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[4].wakeup_ports[0].bits.uop.br_tag connect slots_4.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[4].wakeup_ports[0].bits.uop.br_mask connect slots_4.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[4].wakeup_ports[0].bits.uop.dis_col_sel connect slots_4.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[4].wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect slots_4.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[4].wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect slots_4.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[4].wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect slots_4.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[4].wakeup_ports[0].bits.uop.iw_p2_speculative_child connect slots_4.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[4].wakeup_ports[0].bits.uop.iw_p1_speculative_child connect slots_4.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[4].wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect slots_4.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[4].wakeup_ports[0].bits.uop.iw_issued_partial_agen connect slots_4.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[4].wakeup_ports[0].bits.uop.iw_issued connect slots_4.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[4].wakeup_ports[0].bits.uop.fu_code[0] connect slots_4.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[4].wakeup_ports[0].bits.uop.fu_code[1] connect slots_4.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[4].wakeup_ports[0].bits.uop.fu_code[2] connect slots_4.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[4].wakeup_ports[0].bits.uop.fu_code[3] connect slots_4.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[4].wakeup_ports[0].bits.uop.fu_code[4] connect slots_4.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[4].wakeup_ports[0].bits.uop.fu_code[5] connect slots_4.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[4].wakeup_ports[0].bits.uop.fu_code[6] connect slots_4.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[4].wakeup_ports[0].bits.uop.fu_code[7] connect slots_4.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[4].wakeup_ports[0].bits.uop.fu_code[8] connect slots_4.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[4].wakeup_ports[0].bits.uop.fu_code[9] connect slots_4.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[4].wakeup_ports[0].bits.uop.iq_type[0] connect slots_4.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[4].wakeup_ports[0].bits.uop.iq_type[1] connect slots_4.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[4].wakeup_ports[0].bits.uop.iq_type[2] connect slots_4.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[4].wakeup_ports[0].bits.uop.iq_type[3] connect slots_4.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[4].wakeup_ports[0].bits.uop.debug_pc connect slots_4.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[4].wakeup_ports[0].bits.uop.is_rvc connect slots_4.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[4].wakeup_ports[0].bits.uop.debug_inst connect slots_4.io.wakeup_ports[0].bits.uop.inst, issue_slots[4].wakeup_ports[0].bits.uop.inst connect slots_4.io.wakeup_ports[0].valid, issue_slots[4].wakeup_ports[0].valid connect slots_4.io.wakeup_ports[1].bits.rebusy, issue_slots[4].wakeup_ports[1].bits.rebusy connect slots_4.io.wakeup_ports[1].bits.speculative_mask, issue_slots[4].wakeup_ports[1].bits.speculative_mask connect slots_4.io.wakeup_ports[1].bits.bypassable, issue_slots[4].wakeup_ports[1].bits.bypassable connect slots_4.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[4].wakeup_ports[1].bits.uop.debug_tsrc connect slots_4.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[4].wakeup_ports[1].bits.uop.debug_fsrc connect slots_4.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[4].wakeup_ports[1].bits.uop.bp_xcpt_if connect slots_4.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[4].wakeup_ports[1].bits.uop.bp_debug_if connect slots_4.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[4].wakeup_ports[1].bits.uop.xcpt_ma_if connect slots_4.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[4].wakeup_ports[1].bits.uop.xcpt_ae_if connect slots_4.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[4].wakeup_ports[1].bits.uop.xcpt_pf_if connect slots_4.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[4].wakeup_ports[1].bits.uop.fp_typ connect slots_4.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[4].wakeup_ports[1].bits.uop.fp_rm connect slots_4.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[4].wakeup_ports[1].bits.uop.fp_val connect slots_4.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[4].wakeup_ports[1].bits.uop.fcn_op connect slots_4.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[4].wakeup_ports[1].bits.uop.fcn_dw connect slots_4.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[4].wakeup_ports[1].bits.uop.frs3_en connect slots_4.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[4].wakeup_ports[1].bits.uop.lrs2_rtype connect slots_4.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[4].wakeup_ports[1].bits.uop.lrs1_rtype connect slots_4.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[4].wakeup_ports[1].bits.uop.dst_rtype connect slots_4.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[4].wakeup_ports[1].bits.uop.lrs3 connect slots_4.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[4].wakeup_ports[1].bits.uop.lrs2 connect slots_4.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[4].wakeup_ports[1].bits.uop.lrs1 connect slots_4.io.wakeup_ports[1].bits.uop.ldst, issue_slots[4].wakeup_ports[1].bits.uop.ldst connect slots_4.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[4].wakeup_ports[1].bits.uop.ldst_is_rs1 connect slots_4.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[4].wakeup_ports[1].bits.uop.csr_cmd connect slots_4.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[4].wakeup_ports[1].bits.uop.flush_on_commit connect slots_4.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[4].wakeup_ports[1].bits.uop.is_unique connect slots_4.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[4].wakeup_ports[1].bits.uop.uses_stq connect slots_4.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[4].wakeup_ports[1].bits.uop.uses_ldq connect slots_4.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[4].wakeup_ports[1].bits.uop.mem_signed connect slots_4.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[4].wakeup_ports[1].bits.uop.mem_size connect slots_4.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[4].wakeup_ports[1].bits.uop.mem_cmd connect slots_4.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[4].wakeup_ports[1].bits.uop.exc_cause connect slots_4.io.wakeup_ports[1].bits.uop.exception, issue_slots[4].wakeup_ports[1].bits.uop.exception connect slots_4.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[4].wakeup_ports[1].bits.uop.stale_pdst connect slots_4.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[4].wakeup_ports[1].bits.uop.ppred_busy connect slots_4.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[4].wakeup_ports[1].bits.uop.prs3_busy connect slots_4.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[4].wakeup_ports[1].bits.uop.prs2_busy connect slots_4.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[4].wakeup_ports[1].bits.uop.prs1_busy connect slots_4.io.wakeup_ports[1].bits.uop.ppred, issue_slots[4].wakeup_ports[1].bits.uop.ppred connect slots_4.io.wakeup_ports[1].bits.uop.prs3, issue_slots[4].wakeup_ports[1].bits.uop.prs3 connect slots_4.io.wakeup_ports[1].bits.uop.prs2, issue_slots[4].wakeup_ports[1].bits.uop.prs2 connect slots_4.io.wakeup_ports[1].bits.uop.prs1, issue_slots[4].wakeup_ports[1].bits.uop.prs1 connect slots_4.io.wakeup_ports[1].bits.uop.pdst, issue_slots[4].wakeup_ports[1].bits.uop.pdst connect slots_4.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[4].wakeup_ports[1].bits.uop.rxq_idx connect slots_4.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[4].wakeup_ports[1].bits.uop.stq_idx connect slots_4.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[4].wakeup_ports[1].bits.uop.ldq_idx connect slots_4.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[4].wakeup_ports[1].bits.uop.rob_idx connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.vec connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.wflags connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.div connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.fma connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.toint connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.fromint connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.wen connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.ldst connect slots_4.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[4].wakeup_ports[1].bits.uop.op2_sel connect slots_4.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[4].wakeup_ports[1].bits.uop.op1_sel connect slots_4.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[4].wakeup_ports[1].bits.uop.imm_packed connect slots_4.io.wakeup_ports[1].bits.uop.pimm, issue_slots[4].wakeup_ports[1].bits.uop.pimm connect slots_4.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[4].wakeup_ports[1].bits.uop.imm_sel connect slots_4.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[4].wakeup_ports[1].bits.uop.imm_rename connect slots_4.io.wakeup_ports[1].bits.uop.taken, issue_slots[4].wakeup_ports[1].bits.uop.taken connect slots_4.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[4].wakeup_ports[1].bits.uop.pc_lob connect slots_4.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[4].wakeup_ports[1].bits.uop.edge_inst connect slots_4.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[4].wakeup_ports[1].bits.uop.ftq_idx connect slots_4.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[4].wakeup_ports[1].bits.uop.is_mov connect slots_4.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[4].wakeup_ports[1].bits.uop.is_rocc connect slots_4.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[4].wakeup_ports[1].bits.uop.is_sys_pc2epc connect slots_4.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[4].wakeup_ports[1].bits.uop.is_eret connect slots_4.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[4].wakeup_ports[1].bits.uop.is_amo connect slots_4.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[4].wakeup_ports[1].bits.uop.is_sfence connect slots_4.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[4].wakeup_ports[1].bits.uop.is_fencei connect slots_4.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[4].wakeup_ports[1].bits.uop.is_fence connect slots_4.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[4].wakeup_ports[1].bits.uop.is_sfb connect slots_4.io.wakeup_ports[1].bits.uop.br_type, issue_slots[4].wakeup_ports[1].bits.uop.br_type connect slots_4.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[4].wakeup_ports[1].bits.uop.br_tag connect slots_4.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[4].wakeup_ports[1].bits.uop.br_mask connect slots_4.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[4].wakeup_ports[1].bits.uop.dis_col_sel connect slots_4.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[4].wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect slots_4.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[4].wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect slots_4.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[4].wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect slots_4.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[4].wakeup_ports[1].bits.uop.iw_p2_speculative_child connect slots_4.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[4].wakeup_ports[1].bits.uop.iw_p1_speculative_child connect slots_4.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[4].wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect slots_4.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[4].wakeup_ports[1].bits.uop.iw_issued_partial_agen connect slots_4.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[4].wakeup_ports[1].bits.uop.iw_issued connect slots_4.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[4].wakeup_ports[1].bits.uop.fu_code[0] connect slots_4.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[4].wakeup_ports[1].bits.uop.fu_code[1] connect slots_4.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[4].wakeup_ports[1].bits.uop.fu_code[2] connect slots_4.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[4].wakeup_ports[1].bits.uop.fu_code[3] connect slots_4.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[4].wakeup_ports[1].bits.uop.fu_code[4] connect slots_4.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[4].wakeup_ports[1].bits.uop.fu_code[5] connect slots_4.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[4].wakeup_ports[1].bits.uop.fu_code[6] connect slots_4.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[4].wakeup_ports[1].bits.uop.fu_code[7] connect slots_4.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[4].wakeup_ports[1].bits.uop.fu_code[8] connect slots_4.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[4].wakeup_ports[1].bits.uop.fu_code[9] connect slots_4.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[4].wakeup_ports[1].bits.uop.iq_type[0] connect slots_4.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[4].wakeup_ports[1].bits.uop.iq_type[1] connect slots_4.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[4].wakeup_ports[1].bits.uop.iq_type[2] connect slots_4.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[4].wakeup_ports[1].bits.uop.iq_type[3] connect slots_4.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[4].wakeup_ports[1].bits.uop.debug_pc connect slots_4.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[4].wakeup_ports[1].bits.uop.is_rvc connect slots_4.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[4].wakeup_ports[1].bits.uop.debug_inst connect slots_4.io.wakeup_ports[1].bits.uop.inst, issue_slots[4].wakeup_ports[1].bits.uop.inst connect slots_4.io.wakeup_ports[1].valid, issue_slots[4].wakeup_ports[1].valid connect slots_4.io.wakeup_ports[2].bits.rebusy, issue_slots[4].wakeup_ports[2].bits.rebusy connect slots_4.io.wakeup_ports[2].bits.speculative_mask, issue_slots[4].wakeup_ports[2].bits.speculative_mask connect slots_4.io.wakeup_ports[2].bits.bypassable, issue_slots[4].wakeup_ports[2].bits.bypassable connect slots_4.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[4].wakeup_ports[2].bits.uop.debug_tsrc connect slots_4.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[4].wakeup_ports[2].bits.uop.debug_fsrc connect slots_4.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[4].wakeup_ports[2].bits.uop.bp_xcpt_if connect slots_4.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[4].wakeup_ports[2].bits.uop.bp_debug_if connect slots_4.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[4].wakeup_ports[2].bits.uop.xcpt_ma_if connect slots_4.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[4].wakeup_ports[2].bits.uop.xcpt_ae_if connect slots_4.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[4].wakeup_ports[2].bits.uop.xcpt_pf_if connect slots_4.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[4].wakeup_ports[2].bits.uop.fp_typ connect slots_4.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[4].wakeup_ports[2].bits.uop.fp_rm connect slots_4.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[4].wakeup_ports[2].bits.uop.fp_val connect slots_4.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[4].wakeup_ports[2].bits.uop.fcn_op connect slots_4.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[4].wakeup_ports[2].bits.uop.fcn_dw connect slots_4.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[4].wakeup_ports[2].bits.uop.frs3_en connect slots_4.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[4].wakeup_ports[2].bits.uop.lrs2_rtype connect slots_4.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[4].wakeup_ports[2].bits.uop.lrs1_rtype connect slots_4.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[4].wakeup_ports[2].bits.uop.dst_rtype connect slots_4.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[4].wakeup_ports[2].bits.uop.lrs3 connect slots_4.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[4].wakeup_ports[2].bits.uop.lrs2 connect slots_4.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[4].wakeup_ports[2].bits.uop.lrs1 connect slots_4.io.wakeup_ports[2].bits.uop.ldst, issue_slots[4].wakeup_ports[2].bits.uop.ldst connect slots_4.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[4].wakeup_ports[2].bits.uop.ldst_is_rs1 connect slots_4.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[4].wakeup_ports[2].bits.uop.csr_cmd connect slots_4.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[4].wakeup_ports[2].bits.uop.flush_on_commit connect slots_4.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[4].wakeup_ports[2].bits.uop.is_unique connect slots_4.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[4].wakeup_ports[2].bits.uop.uses_stq connect slots_4.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[4].wakeup_ports[2].bits.uop.uses_ldq connect slots_4.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[4].wakeup_ports[2].bits.uop.mem_signed connect slots_4.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[4].wakeup_ports[2].bits.uop.mem_size connect slots_4.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[4].wakeup_ports[2].bits.uop.mem_cmd connect slots_4.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[4].wakeup_ports[2].bits.uop.exc_cause connect slots_4.io.wakeup_ports[2].bits.uop.exception, issue_slots[4].wakeup_ports[2].bits.uop.exception connect slots_4.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[4].wakeup_ports[2].bits.uop.stale_pdst connect slots_4.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[4].wakeup_ports[2].bits.uop.ppred_busy connect slots_4.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[4].wakeup_ports[2].bits.uop.prs3_busy connect slots_4.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[4].wakeup_ports[2].bits.uop.prs2_busy connect slots_4.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[4].wakeup_ports[2].bits.uop.prs1_busy connect slots_4.io.wakeup_ports[2].bits.uop.ppred, issue_slots[4].wakeup_ports[2].bits.uop.ppred connect slots_4.io.wakeup_ports[2].bits.uop.prs3, issue_slots[4].wakeup_ports[2].bits.uop.prs3 connect slots_4.io.wakeup_ports[2].bits.uop.prs2, issue_slots[4].wakeup_ports[2].bits.uop.prs2 connect slots_4.io.wakeup_ports[2].bits.uop.prs1, issue_slots[4].wakeup_ports[2].bits.uop.prs1 connect slots_4.io.wakeup_ports[2].bits.uop.pdst, issue_slots[4].wakeup_ports[2].bits.uop.pdst connect slots_4.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[4].wakeup_ports[2].bits.uop.rxq_idx connect slots_4.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[4].wakeup_ports[2].bits.uop.stq_idx connect slots_4.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[4].wakeup_ports[2].bits.uop.ldq_idx connect slots_4.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[4].wakeup_ports[2].bits.uop.rob_idx connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.vec connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.wflags connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.div connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.fma connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.toint connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.fromint connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.wen connect slots_4.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.ldst connect slots_4.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[4].wakeup_ports[2].bits.uop.op2_sel connect slots_4.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[4].wakeup_ports[2].bits.uop.op1_sel connect slots_4.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[4].wakeup_ports[2].bits.uop.imm_packed connect slots_4.io.wakeup_ports[2].bits.uop.pimm, issue_slots[4].wakeup_ports[2].bits.uop.pimm connect slots_4.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[4].wakeup_ports[2].bits.uop.imm_sel connect slots_4.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[4].wakeup_ports[2].bits.uop.imm_rename connect slots_4.io.wakeup_ports[2].bits.uop.taken, issue_slots[4].wakeup_ports[2].bits.uop.taken connect slots_4.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[4].wakeup_ports[2].bits.uop.pc_lob connect slots_4.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[4].wakeup_ports[2].bits.uop.edge_inst connect slots_4.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[4].wakeup_ports[2].bits.uop.ftq_idx connect slots_4.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[4].wakeup_ports[2].bits.uop.is_mov connect slots_4.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[4].wakeup_ports[2].bits.uop.is_rocc connect slots_4.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[4].wakeup_ports[2].bits.uop.is_sys_pc2epc connect slots_4.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[4].wakeup_ports[2].bits.uop.is_eret connect slots_4.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[4].wakeup_ports[2].bits.uop.is_amo connect slots_4.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[4].wakeup_ports[2].bits.uop.is_sfence connect slots_4.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[4].wakeup_ports[2].bits.uop.is_fencei connect slots_4.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[4].wakeup_ports[2].bits.uop.is_fence connect slots_4.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[4].wakeup_ports[2].bits.uop.is_sfb connect slots_4.io.wakeup_ports[2].bits.uop.br_type, issue_slots[4].wakeup_ports[2].bits.uop.br_type connect slots_4.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[4].wakeup_ports[2].bits.uop.br_tag connect slots_4.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[4].wakeup_ports[2].bits.uop.br_mask connect slots_4.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[4].wakeup_ports[2].bits.uop.dis_col_sel connect slots_4.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[4].wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect slots_4.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[4].wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect slots_4.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[4].wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect slots_4.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[4].wakeup_ports[2].bits.uop.iw_p2_speculative_child connect slots_4.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[4].wakeup_ports[2].bits.uop.iw_p1_speculative_child connect slots_4.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[4].wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect slots_4.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[4].wakeup_ports[2].bits.uop.iw_issued_partial_agen connect slots_4.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[4].wakeup_ports[2].bits.uop.iw_issued connect slots_4.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[4].wakeup_ports[2].bits.uop.fu_code[0] connect slots_4.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[4].wakeup_ports[2].bits.uop.fu_code[1] connect slots_4.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[4].wakeup_ports[2].bits.uop.fu_code[2] connect slots_4.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[4].wakeup_ports[2].bits.uop.fu_code[3] connect slots_4.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[4].wakeup_ports[2].bits.uop.fu_code[4] connect slots_4.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[4].wakeup_ports[2].bits.uop.fu_code[5] connect slots_4.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[4].wakeup_ports[2].bits.uop.fu_code[6] connect slots_4.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[4].wakeup_ports[2].bits.uop.fu_code[7] connect slots_4.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[4].wakeup_ports[2].bits.uop.fu_code[8] connect slots_4.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[4].wakeup_ports[2].bits.uop.fu_code[9] connect slots_4.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[4].wakeup_ports[2].bits.uop.iq_type[0] connect slots_4.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[4].wakeup_ports[2].bits.uop.iq_type[1] connect slots_4.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[4].wakeup_ports[2].bits.uop.iq_type[2] connect slots_4.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[4].wakeup_ports[2].bits.uop.iq_type[3] connect slots_4.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[4].wakeup_ports[2].bits.uop.debug_pc connect slots_4.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[4].wakeup_ports[2].bits.uop.is_rvc connect slots_4.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[4].wakeup_ports[2].bits.uop.debug_inst connect slots_4.io.wakeup_ports[2].bits.uop.inst, issue_slots[4].wakeup_ports[2].bits.uop.inst connect slots_4.io.wakeup_ports[2].valid, issue_slots[4].wakeup_ports[2].valid connect slots_4.io.wakeup_ports[3].bits.rebusy, issue_slots[4].wakeup_ports[3].bits.rebusy connect slots_4.io.wakeup_ports[3].bits.speculative_mask, issue_slots[4].wakeup_ports[3].bits.speculative_mask connect slots_4.io.wakeup_ports[3].bits.bypassable, issue_slots[4].wakeup_ports[3].bits.bypassable connect slots_4.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[4].wakeup_ports[3].bits.uop.debug_tsrc connect slots_4.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[4].wakeup_ports[3].bits.uop.debug_fsrc connect slots_4.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[4].wakeup_ports[3].bits.uop.bp_xcpt_if connect slots_4.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[4].wakeup_ports[3].bits.uop.bp_debug_if connect slots_4.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[4].wakeup_ports[3].bits.uop.xcpt_ma_if connect slots_4.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[4].wakeup_ports[3].bits.uop.xcpt_ae_if connect slots_4.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[4].wakeup_ports[3].bits.uop.xcpt_pf_if connect slots_4.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[4].wakeup_ports[3].bits.uop.fp_typ connect slots_4.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[4].wakeup_ports[3].bits.uop.fp_rm connect slots_4.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[4].wakeup_ports[3].bits.uop.fp_val connect slots_4.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[4].wakeup_ports[3].bits.uop.fcn_op connect slots_4.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[4].wakeup_ports[3].bits.uop.fcn_dw connect slots_4.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[4].wakeup_ports[3].bits.uop.frs3_en connect slots_4.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[4].wakeup_ports[3].bits.uop.lrs2_rtype connect slots_4.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[4].wakeup_ports[3].bits.uop.lrs1_rtype connect slots_4.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[4].wakeup_ports[3].bits.uop.dst_rtype connect slots_4.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[4].wakeup_ports[3].bits.uop.lrs3 connect slots_4.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[4].wakeup_ports[3].bits.uop.lrs2 connect slots_4.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[4].wakeup_ports[3].bits.uop.lrs1 connect slots_4.io.wakeup_ports[3].bits.uop.ldst, issue_slots[4].wakeup_ports[3].bits.uop.ldst connect slots_4.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[4].wakeup_ports[3].bits.uop.ldst_is_rs1 connect slots_4.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[4].wakeup_ports[3].bits.uop.csr_cmd connect slots_4.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[4].wakeup_ports[3].bits.uop.flush_on_commit connect slots_4.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[4].wakeup_ports[3].bits.uop.is_unique connect slots_4.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[4].wakeup_ports[3].bits.uop.uses_stq connect slots_4.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[4].wakeup_ports[3].bits.uop.uses_ldq connect slots_4.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[4].wakeup_ports[3].bits.uop.mem_signed connect slots_4.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[4].wakeup_ports[3].bits.uop.mem_size connect slots_4.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[4].wakeup_ports[3].bits.uop.mem_cmd connect slots_4.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[4].wakeup_ports[3].bits.uop.exc_cause connect slots_4.io.wakeup_ports[3].bits.uop.exception, issue_slots[4].wakeup_ports[3].bits.uop.exception connect slots_4.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[4].wakeup_ports[3].bits.uop.stale_pdst connect slots_4.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[4].wakeup_ports[3].bits.uop.ppred_busy connect slots_4.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[4].wakeup_ports[3].bits.uop.prs3_busy connect slots_4.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[4].wakeup_ports[3].bits.uop.prs2_busy connect slots_4.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[4].wakeup_ports[3].bits.uop.prs1_busy connect slots_4.io.wakeup_ports[3].bits.uop.ppred, issue_slots[4].wakeup_ports[3].bits.uop.ppred connect slots_4.io.wakeup_ports[3].bits.uop.prs3, issue_slots[4].wakeup_ports[3].bits.uop.prs3 connect slots_4.io.wakeup_ports[3].bits.uop.prs2, issue_slots[4].wakeup_ports[3].bits.uop.prs2 connect slots_4.io.wakeup_ports[3].bits.uop.prs1, issue_slots[4].wakeup_ports[3].bits.uop.prs1 connect slots_4.io.wakeup_ports[3].bits.uop.pdst, issue_slots[4].wakeup_ports[3].bits.uop.pdst connect slots_4.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[4].wakeup_ports[3].bits.uop.rxq_idx connect slots_4.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[4].wakeup_ports[3].bits.uop.stq_idx connect slots_4.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[4].wakeup_ports[3].bits.uop.ldq_idx connect slots_4.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[4].wakeup_ports[3].bits.uop.rob_idx connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.vec connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.wflags connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.div connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.fma connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.toint connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.fromint connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.wen connect slots_4.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.ldst connect slots_4.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[4].wakeup_ports[3].bits.uop.op2_sel connect slots_4.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[4].wakeup_ports[3].bits.uop.op1_sel connect slots_4.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[4].wakeup_ports[3].bits.uop.imm_packed connect slots_4.io.wakeup_ports[3].bits.uop.pimm, issue_slots[4].wakeup_ports[3].bits.uop.pimm connect slots_4.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[4].wakeup_ports[3].bits.uop.imm_sel connect slots_4.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[4].wakeup_ports[3].bits.uop.imm_rename connect slots_4.io.wakeup_ports[3].bits.uop.taken, issue_slots[4].wakeup_ports[3].bits.uop.taken connect slots_4.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[4].wakeup_ports[3].bits.uop.pc_lob connect slots_4.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[4].wakeup_ports[3].bits.uop.edge_inst connect slots_4.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[4].wakeup_ports[3].bits.uop.ftq_idx connect slots_4.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[4].wakeup_ports[3].bits.uop.is_mov connect slots_4.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[4].wakeup_ports[3].bits.uop.is_rocc connect slots_4.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[4].wakeup_ports[3].bits.uop.is_sys_pc2epc connect slots_4.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[4].wakeup_ports[3].bits.uop.is_eret connect slots_4.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[4].wakeup_ports[3].bits.uop.is_amo connect slots_4.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[4].wakeup_ports[3].bits.uop.is_sfence connect slots_4.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[4].wakeup_ports[3].bits.uop.is_fencei connect slots_4.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[4].wakeup_ports[3].bits.uop.is_fence connect slots_4.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[4].wakeup_ports[3].bits.uop.is_sfb connect slots_4.io.wakeup_ports[3].bits.uop.br_type, issue_slots[4].wakeup_ports[3].bits.uop.br_type connect slots_4.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[4].wakeup_ports[3].bits.uop.br_tag connect slots_4.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[4].wakeup_ports[3].bits.uop.br_mask connect slots_4.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[4].wakeup_ports[3].bits.uop.dis_col_sel connect slots_4.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[4].wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect slots_4.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[4].wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect slots_4.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[4].wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect slots_4.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[4].wakeup_ports[3].bits.uop.iw_p2_speculative_child connect slots_4.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[4].wakeup_ports[3].bits.uop.iw_p1_speculative_child connect slots_4.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[4].wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect slots_4.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[4].wakeup_ports[3].bits.uop.iw_issued_partial_agen connect slots_4.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[4].wakeup_ports[3].bits.uop.iw_issued connect slots_4.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[4].wakeup_ports[3].bits.uop.fu_code[0] connect slots_4.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[4].wakeup_ports[3].bits.uop.fu_code[1] connect slots_4.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[4].wakeup_ports[3].bits.uop.fu_code[2] connect slots_4.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[4].wakeup_ports[3].bits.uop.fu_code[3] connect slots_4.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[4].wakeup_ports[3].bits.uop.fu_code[4] connect slots_4.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[4].wakeup_ports[3].bits.uop.fu_code[5] connect slots_4.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[4].wakeup_ports[3].bits.uop.fu_code[6] connect slots_4.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[4].wakeup_ports[3].bits.uop.fu_code[7] connect slots_4.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[4].wakeup_ports[3].bits.uop.fu_code[8] connect slots_4.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[4].wakeup_ports[3].bits.uop.fu_code[9] connect slots_4.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[4].wakeup_ports[3].bits.uop.iq_type[0] connect slots_4.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[4].wakeup_ports[3].bits.uop.iq_type[1] connect slots_4.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[4].wakeup_ports[3].bits.uop.iq_type[2] connect slots_4.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[4].wakeup_ports[3].bits.uop.iq_type[3] connect slots_4.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[4].wakeup_ports[3].bits.uop.debug_pc connect slots_4.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[4].wakeup_ports[3].bits.uop.is_rvc connect slots_4.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[4].wakeup_ports[3].bits.uop.debug_inst connect slots_4.io.wakeup_ports[3].bits.uop.inst, issue_slots[4].wakeup_ports[3].bits.uop.inst connect slots_4.io.wakeup_ports[3].valid, issue_slots[4].wakeup_ports[3].valid connect slots_4.io.wakeup_ports[4].bits.rebusy, issue_slots[4].wakeup_ports[4].bits.rebusy connect slots_4.io.wakeup_ports[4].bits.speculative_mask, issue_slots[4].wakeup_ports[4].bits.speculative_mask connect slots_4.io.wakeup_ports[4].bits.bypassable, issue_slots[4].wakeup_ports[4].bits.bypassable connect slots_4.io.wakeup_ports[4].bits.uop.debug_tsrc, issue_slots[4].wakeup_ports[4].bits.uop.debug_tsrc connect slots_4.io.wakeup_ports[4].bits.uop.debug_fsrc, issue_slots[4].wakeup_ports[4].bits.uop.debug_fsrc connect slots_4.io.wakeup_ports[4].bits.uop.bp_xcpt_if, issue_slots[4].wakeup_ports[4].bits.uop.bp_xcpt_if connect slots_4.io.wakeup_ports[4].bits.uop.bp_debug_if, issue_slots[4].wakeup_ports[4].bits.uop.bp_debug_if connect slots_4.io.wakeup_ports[4].bits.uop.xcpt_ma_if, issue_slots[4].wakeup_ports[4].bits.uop.xcpt_ma_if connect slots_4.io.wakeup_ports[4].bits.uop.xcpt_ae_if, issue_slots[4].wakeup_ports[4].bits.uop.xcpt_ae_if connect slots_4.io.wakeup_ports[4].bits.uop.xcpt_pf_if, issue_slots[4].wakeup_ports[4].bits.uop.xcpt_pf_if connect slots_4.io.wakeup_ports[4].bits.uop.fp_typ, issue_slots[4].wakeup_ports[4].bits.uop.fp_typ connect slots_4.io.wakeup_ports[4].bits.uop.fp_rm, issue_slots[4].wakeup_ports[4].bits.uop.fp_rm connect slots_4.io.wakeup_ports[4].bits.uop.fp_val, issue_slots[4].wakeup_ports[4].bits.uop.fp_val connect slots_4.io.wakeup_ports[4].bits.uop.fcn_op, issue_slots[4].wakeup_ports[4].bits.uop.fcn_op connect slots_4.io.wakeup_ports[4].bits.uop.fcn_dw, issue_slots[4].wakeup_ports[4].bits.uop.fcn_dw connect slots_4.io.wakeup_ports[4].bits.uop.frs3_en, issue_slots[4].wakeup_ports[4].bits.uop.frs3_en connect slots_4.io.wakeup_ports[4].bits.uop.lrs2_rtype, issue_slots[4].wakeup_ports[4].bits.uop.lrs2_rtype connect slots_4.io.wakeup_ports[4].bits.uop.lrs1_rtype, issue_slots[4].wakeup_ports[4].bits.uop.lrs1_rtype connect slots_4.io.wakeup_ports[4].bits.uop.dst_rtype, issue_slots[4].wakeup_ports[4].bits.uop.dst_rtype connect slots_4.io.wakeup_ports[4].bits.uop.lrs3, issue_slots[4].wakeup_ports[4].bits.uop.lrs3 connect slots_4.io.wakeup_ports[4].bits.uop.lrs2, issue_slots[4].wakeup_ports[4].bits.uop.lrs2 connect slots_4.io.wakeup_ports[4].bits.uop.lrs1, issue_slots[4].wakeup_ports[4].bits.uop.lrs1 connect slots_4.io.wakeup_ports[4].bits.uop.ldst, issue_slots[4].wakeup_ports[4].bits.uop.ldst connect slots_4.io.wakeup_ports[4].bits.uop.ldst_is_rs1, issue_slots[4].wakeup_ports[4].bits.uop.ldst_is_rs1 connect slots_4.io.wakeup_ports[4].bits.uop.csr_cmd, issue_slots[4].wakeup_ports[4].bits.uop.csr_cmd connect slots_4.io.wakeup_ports[4].bits.uop.flush_on_commit, issue_slots[4].wakeup_ports[4].bits.uop.flush_on_commit connect slots_4.io.wakeup_ports[4].bits.uop.is_unique, issue_slots[4].wakeup_ports[4].bits.uop.is_unique connect slots_4.io.wakeup_ports[4].bits.uop.uses_stq, issue_slots[4].wakeup_ports[4].bits.uop.uses_stq connect slots_4.io.wakeup_ports[4].bits.uop.uses_ldq, issue_slots[4].wakeup_ports[4].bits.uop.uses_ldq connect slots_4.io.wakeup_ports[4].bits.uop.mem_signed, issue_slots[4].wakeup_ports[4].bits.uop.mem_signed connect slots_4.io.wakeup_ports[4].bits.uop.mem_size, issue_slots[4].wakeup_ports[4].bits.uop.mem_size connect slots_4.io.wakeup_ports[4].bits.uop.mem_cmd, issue_slots[4].wakeup_ports[4].bits.uop.mem_cmd connect slots_4.io.wakeup_ports[4].bits.uop.exc_cause, issue_slots[4].wakeup_ports[4].bits.uop.exc_cause connect slots_4.io.wakeup_ports[4].bits.uop.exception, issue_slots[4].wakeup_ports[4].bits.uop.exception connect slots_4.io.wakeup_ports[4].bits.uop.stale_pdst, issue_slots[4].wakeup_ports[4].bits.uop.stale_pdst connect slots_4.io.wakeup_ports[4].bits.uop.ppred_busy, issue_slots[4].wakeup_ports[4].bits.uop.ppred_busy connect slots_4.io.wakeup_ports[4].bits.uop.prs3_busy, issue_slots[4].wakeup_ports[4].bits.uop.prs3_busy connect slots_4.io.wakeup_ports[4].bits.uop.prs2_busy, issue_slots[4].wakeup_ports[4].bits.uop.prs2_busy connect slots_4.io.wakeup_ports[4].bits.uop.prs1_busy, issue_slots[4].wakeup_ports[4].bits.uop.prs1_busy connect slots_4.io.wakeup_ports[4].bits.uop.ppred, issue_slots[4].wakeup_ports[4].bits.uop.ppred connect slots_4.io.wakeup_ports[4].bits.uop.prs3, issue_slots[4].wakeup_ports[4].bits.uop.prs3 connect slots_4.io.wakeup_ports[4].bits.uop.prs2, issue_slots[4].wakeup_ports[4].bits.uop.prs2 connect slots_4.io.wakeup_ports[4].bits.uop.prs1, issue_slots[4].wakeup_ports[4].bits.uop.prs1 connect slots_4.io.wakeup_ports[4].bits.uop.pdst, issue_slots[4].wakeup_ports[4].bits.uop.pdst connect slots_4.io.wakeup_ports[4].bits.uop.rxq_idx, issue_slots[4].wakeup_ports[4].bits.uop.rxq_idx connect slots_4.io.wakeup_ports[4].bits.uop.stq_idx, issue_slots[4].wakeup_ports[4].bits.uop.stq_idx connect slots_4.io.wakeup_ports[4].bits.uop.ldq_idx, issue_slots[4].wakeup_ports[4].bits.uop.ldq_idx connect slots_4.io.wakeup_ports[4].bits.uop.rob_idx, issue_slots[4].wakeup_ports[4].bits.uop.rob_idx connect slots_4.io.wakeup_ports[4].bits.uop.fp_ctrl.vec, issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.vec connect slots_4.io.wakeup_ports[4].bits.uop.fp_ctrl.wflags, issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.wflags connect slots_4.io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt, issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect slots_4.io.wakeup_ports[4].bits.uop.fp_ctrl.div, issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.div connect slots_4.io.wakeup_ports[4].bits.uop.fp_ctrl.fma, issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.fma connect slots_4.io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect slots_4.io.wakeup_ports[4].bits.uop.fp_ctrl.toint, issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.toint connect slots_4.io.wakeup_ports[4].bits.uop.fp_ctrl.fromint, issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.fromint connect slots_4.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect slots_4.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect slots_4.io.wakeup_ports[4].bits.uop.fp_ctrl.swap23, issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect slots_4.io.wakeup_ports[4].bits.uop.fp_ctrl.swap12, issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect slots_4.io.wakeup_ports[4].bits.uop.fp_ctrl.ren3, issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect slots_4.io.wakeup_ports[4].bits.uop.fp_ctrl.ren2, issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect slots_4.io.wakeup_ports[4].bits.uop.fp_ctrl.ren1, issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect slots_4.io.wakeup_ports[4].bits.uop.fp_ctrl.wen, issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.wen connect slots_4.io.wakeup_ports[4].bits.uop.fp_ctrl.ldst, issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.ldst connect slots_4.io.wakeup_ports[4].bits.uop.op2_sel, issue_slots[4].wakeup_ports[4].bits.uop.op2_sel connect slots_4.io.wakeup_ports[4].bits.uop.op1_sel, issue_slots[4].wakeup_ports[4].bits.uop.op1_sel connect slots_4.io.wakeup_ports[4].bits.uop.imm_packed, issue_slots[4].wakeup_ports[4].bits.uop.imm_packed connect slots_4.io.wakeup_ports[4].bits.uop.pimm, issue_slots[4].wakeup_ports[4].bits.uop.pimm connect slots_4.io.wakeup_ports[4].bits.uop.imm_sel, issue_slots[4].wakeup_ports[4].bits.uop.imm_sel connect slots_4.io.wakeup_ports[4].bits.uop.imm_rename, issue_slots[4].wakeup_ports[4].bits.uop.imm_rename connect slots_4.io.wakeup_ports[4].bits.uop.taken, issue_slots[4].wakeup_ports[4].bits.uop.taken connect slots_4.io.wakeup_ports[4].bits.uop.pc_lob, issue_slots[4].wakeup_ports[4].bits.uop.pc_lob connect slots_4.io.wakeup_ports[4].bits.uop.edge_inst, issue_slots[4].wakeup_ports[4].bits.uop.edge_inst connect slots_4.io.wakeup_ports[4].bits.uop.ftq_idx, issue_slots[4].wakeup_ports[4].bits.uop.ftq_idx connect slots_4.io.wakeup_ports[4].bits.uop.is_mov, issue_slots[4].wakeup_ports[4].bits.uop.is_mov connect slots_4.io.wakeup_ports[4].bits.uop.is_rocc, issue_slots[4].wakeup_ports[4].bits.uop.is_rocc connect slots_4.io.wakeup_ports[4].bits.uop.is_sys_pc2epc, issue_slots[4].wakeup_ports[4].bits.uop.is_sys_pc2epc connect slots_4.io.wakeup_ports[4].bits.uop.is_eret, issue_slots[4].wakeup_ports[4].bits.uop.is_eret connect slots_4.io.wakeup_ports[4].bits.uop.is_amo, issue_slots[4].wakeup_ports[4].bits.uop.is_amo connect slots_4.io.wakeup_ports[4].bits.uop.is_sfence, issue_slots[4].wakeup_ports[4].bits.uop.is_sfence connect slots_4.io.wakeup_ports[4].bits.uop.is_fencei, issue_slots[4].wakeup_ports[4].bits.uop.is_fencei connect slots_4.io.wakeup_ports[4].bits.uop.is_fence, issue_slots[4].wakeup_ports[4].bits.uop.is_fence connect slots_4.io.wakeup_ports[4].bits.uop.is_sfb, issue_slots[4].wakeup_ports[4].bits.uop.is_sfb connect slots_4.io.wakeup_ports[4].bits.uop.br_type, issue_slots[4].wakeup_ports[4].bits.uop.br_type connect slots_4.io.wakeup_ports[4].bits.uop.br_tag, issue_slots[4].wakeup_ports[4].bits.uop.br_tag connect slots_4.io.wakeup_ports[4].bits.uop.br_mask, issue_slots[4].wakeup_ports[4].bits.uop.br_mask connect slots_4.io.wakeup_ports[4].bits.uop.dis_col_sel, issue_slots[4].wakeup_ports[4].bits.uop.dis_col_sel connect slots_4.io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint, issue_slots[4].wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect slots_4.io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint, issue_slots[4].wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect slots_4.io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint, issue_slots[4].wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect slots_4.io.wakeup_ports[4].bits.uop.iw_p2_speculative_child, issue_slots[4].wakeup_ports[4].bits.uop.iw_p2_speculative_child connect slots_4.io.wakeup_ports[4].bits.uop.iw_p1_speculative_child, issue_slots[4].wakeup_ports[4].bits.uop.iw_p1_speculative_child connect slots_4.io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen, issue_slots[4].wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect slots_4.io.wakeup_ports[4].bits.uop.iw_issued_partial_agen, issue_slots[4].wakeup_ports[4].bits.uop.iw_issued_partial_agen connect slots_4.io.wakeup_ports[4].bits.uop.iw_issued, issue_slots[4].wakeup_ports[4].bits.uop.iw_issued connect slots_4.io.wakeup_ports[4].bits.uop.fu_code[0], issue_slots[4].wakeup_ports[4].bits.uop.fu_code[0] connect slots_4.io.wakeup_ports[4].bits.uop.fu_code[1], issue_slots[4].wakeup_ports[4].bits.uop.fu_code[1] connect slots_4.io.wakeup_ports[4].bits.uop.fu_code[2], issue_slots[4].wakeup_ports[4].bits.uop.fu_code[2] connect slots_4.io.wakeup_ports[4].bits.uop.fu_code[3], issue_slots[4].wakeup_ports[4].bits.uop.fu_code[3] connect slots_4.io.wakeup_ports[4].bits.uop.fu_code[4], issue_slots[4].wakeup_ports[4].bits.uop.fu_code[4] connect slots_4.io.wakeup_ports[4].bits.uop.fu_code[5], issue_slots[4].wakeup_ports[4].bits.uop.fu_code[5] connect slots_4.io.wakeup_ports[4].bits.uop.fu_code[6], issue_slots[4].wakeup_ports[4].bits.uop.fu_code[6] connect slots_4.io.wakeup_ports[4].bits.uop.fu_code[7], issue_slots[4].wakeup_ports[4].bits.uop.fu_code[7] connect slots_4.io.wakeup_ports[4].bits.uop.fu_code[8], issue_slots[4].wakeup_ports[4].bits.uop.fu_code[8] connect slots_4.io.wakeup_ports[4].bits.uop.fu_code[9], issue_slots[4].wakeup_ports[4].bits.uop.fu_code[9] connect slots_4.io.wakeup_ports[4].bits.uop.iq_type[0], issue_slots[4].wakeup_ports[4].bits.uop.iq_type[0] connect slots_4.io.wakeup_ports[4].bits.uop.iq_type[1], issue_slots[4].wakeup_ports[4].bits.uop.iq_type[1] connect slots_4.io.wakeup_ports[4].bits.uop.iq_type[2], issue_slots[4].wakeup_ports[4].bits.uop.iq_type[2] connect slots_4.io.wakeup_ports[4].bits.uop.iq_type[3], issue_slots[4].wakeup_ports[4].bits.uop.iq_type[3] connect slots_4.io.wakeup_ports[4].bits.uop.debug_pc, issue_slots[4].wakeup_ports[4].bits.uop.debug_pc connect slots_4.io.wakeup_ports[4].bits.uop.is_rvc, issue_slots[4].wakeup_ports[4].bits.uop.is_rvc connect slots_4.io.wakeup_ports[4].bits.uop.debug_inst, issue_slots[4].wakeup_ports[4].bits.uop.debug_inst connect slots_4.io.wakeup_ports[4].bits.uop.inst, issue_slots[4].wakeup_ports[4].bits.uop.inst connect slots_4.io.wakeup_ports[4].valid, issue_slots[4].wakeup_ports[4].valid connect slots_4.io.squash_grant, issue_slots[4].squash_grant connect slots_4.io.clear, issue_slots[4].clear connect slots_4.io.kill, issue_slots[4].kill connect slots_4.io.brupdate.b2.target_offset, issue_slots[4].brupdate.b2.target_offset connect slots_4.io.brupdate.b2.jalr_target, issue_slots[4].brupdate.b2.jalr_target connect slots_4.io.brupdate.b2.pc_sel, issue_slots[4].brupdate.b2.pc_sel connect slots_4.io.brupdate.b2.cfi_type, issue_slots[4].brupdate.b2.cfi_type connect slots_4.io.brupdate.b2.taken, issue_slots[4].brupdate.b2.taken connect slots_4.io.brupdate.b2.mispredict, issue_slots[4].brupdate.b2.mispredict connect slots_4.io.brupdate.b2.uop.debug_tsrc, issue_slots[4].brupdate.b2.uop.debug_tsrc connect slots_4.io.brupdate.b2.uop.debug_fsrc, issue_slots[4].brupdate.b2.uop.debug_fsrc connect slots_4.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[4].brupdate.b2.uop.bp_xcpt_if connect slots_4.io.brupdate.b2.uop.bp_debug_if, issue_slots[4].brupdate.b2.uop.bp_debug_if connect slots_4.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[4].brupdate.b2.uop.xcpt_ma_if connect slots_4.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[4].brupdate.b2.uop.xcpt_ae_if connect slots_4.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[4].brupdate.b2.uop.xcpt_pf_if connect slots_4.io.brupdate.b2.uop.fp_typ, issue_slots[4].brupdate.b2.uop.fp_typ connect slots_4.io.brupdate.b2.uop.fp_rm, issue_slots[4].brupdate.b2.uop.fp_rm connect slots_4.io.brupdate.b2.uop.fp_val, issue_slots[4].brupdate.b2.uop.fp_val connect slots_4.io.brupdate.b2.uop.fcn_op, issue_slots[4].brupdate.b2.uop.fcn_op connect slots_4.io.brupdate.b2.uop.fcn_dw, issue_slots[4].brupdate.b2.uop.fcn_dw connect slots_4.io.brupdate.b2.uop.frs3_en, issue_slots[4].brupdate.b2.uop.frs3_en connect slots_4.io.brupdate.b2.uop.lrs2_rtype, issue_slots[4].brupdate.b2.uop.lrs2_rtype connect slots_4.io.brupdate.b2.uop.lrs1_rtype, issue_slots[4].brupdate.b2.uop.lrs1_rtype connect slots_4.io.brupdate.b2.uop.dst_rtype, issue_slots[4].brupdate.b2.uop.dst_rtype connect slots_4.io.brupdate.b2.uop.lrs3, issue_slots[4].brupdate.b2.uop.lrs3 connect slots_4.io.brupdate.b2.uop.lrs2, issue_slots[4].brupdate.b2.uop.lrs2 connect slots_4.io.brupdate.b2.uop.lrs1, issue_slots[4].brupdate.b2.uop.lrs1 connect slots_4.io.brupdate.b2.uop.ldst, issue_slots[4].brupdate.b2.uop.ldst connect slots_4.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[4].brupdate.b2.uop.ldst_is_rs1 connect slots_4.io.brupdate.b2.uop.csr_cmd, issue_slots[4].brupdate.b2.uop.csr_cmd connect slots_4.io.brupdate.b2.uop.flush_on_commit, issue_slots[4].brupdate.b2.uop.flush_on_commit connect slots_4.io.brupdate.b2.uop.is_unique, issue_slots[4].brupdate.b2.uop.is_unique connect slots_4.io.brupdate.b2.uop.uses_stq, issue_slots[4].brupdate.b2.uop.uses_stq connect slots_4.io.brupdate.b2.uop.uses_ldq, issue_slots[4].brupdate.b2.uop.uses_ldq connect slots_4.io.brupdate.b2.uop.mem_signed, issue_slots[4].brupdate.b2.uop.mem_signed connect slots_4.io.brupdate.b2.uop.mem_size, issue_slots[4].brupdate.b2.uop.mem_size connect slots_4.io.brupdate.b2.uop.mem_cmd, issue_slots[4].brupdate.b2.uop.mem_cmd connect slots_4.io.brupdate.b2.uop.exc_cause, issue_slots[4].brupdate.b2.uop.exc_cause connect slots_4.io.brupdate.b2.uop.exception, issue_slots[4].brupdate.b2.uop.exception connect slots_4.io.brupdate.b2.uop.stale_pdst, issue_slots[4].brupdate.b2.uop.stale_pdst connect slots_4.io.brupdate.b2.uop.ppred_busy, issue_slots[4].brupdate.b2.uop.ppred_busy connect slots_4.io.brupdate.b2.uop.prs3_busy, issue_slots[4].brupdate.b2.uop.prs3_busy connect slots_4.io.brupdate.b2.uop.prs2_busy, issue_slots[4].brupdate.b2.uop.prs2_busy connect slots_4.io.brupdate.b2.uop.prs1_busy, issue_slots[4].brupdate.b2.uop.prs1_busy connect slots_4.io.brupdate.b2.uop.ppred, issue_slots[4].brupdate.b2.uop.ppred connect slots_4.io.brupdate.b2.uop.prs3, issue_slots[4].brupdate.b2.uop.prs3 connect slots_4.io.brupdate.b2.uop.prs2, issue_slots[4].brupdate.b2.uop.prs2 connect slots_4.io.brupdate.b2.uop.prs1, issue_slots[4].brupdate.b2.uop.prs1 connect slots_4.io.brupdate.b2.uop.pdst, issue_slots[4].brupdate.b2.uop.pdst connect slots_4.io.brupdate.b2.uop.rxq_idx, issue_slots[4].brupdate.b2.uop.rxq_idx connect slots_4.io.brupdate.b2.uop.stq_idx, issue_slots[4].brupdate.b2.uop.stq_idx connect slots_4.io.brupdate.b2.uop.ldq_idx, issue_slots[4].brupdate.b2.uop.ldq_idx connect slots_4.io.brupdate.b2.uop.rob_idx, issue_slots[4].brupdate.b2.uop.rob_idx connect slots_4.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[4].brupdate.b2.uop.fp_ctrl.vec connect slots_4.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[4].brupdate.b2.uop.fp_ctrl.wflags connect slots_4.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[4].brupdate.b2.uop.fp_ctrl.sqrt connect slots_4.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[4].brupdate.b2.uop.fp_ctrl.div connect slots_4.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[4].brupdate.b2.uop.fp_ctrl.fma connect slots_4.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[4].brupdate.b2.uop.fp_ctrl.fastpipe connect slots_4.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[4].brupdate.b2.uop.fp_ctrl.toint connect slots_4.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[4].brupdate.b2.uop.fp_ctrl.fromint connect slots_4.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[4].brupdate.b2.uop.fp_ctrl.typeTagOut connect slots_4.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[4].brupdate.b2.uop.fp_ctrl.typeTagIn connect slots_4.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[4].brupdate.b2.uop.fp_ctrl.swap23 connect slots_4.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[4].brupdate.b2.uop.fp_ctrl.swap12 connect slots_4.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[4].brupdate.b2.uop.fp_ctrl.ren3 connect slots_4.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[4].brupdate.b2.uop.fp_ctrl.ren2 connect slots_4.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[4].brupdate.b2.uop.fp_ctrl.ren1 connect slots_4.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[4].brupdate.b2.uop.fp_ctrl.wen connect slots_4.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[4].brupdate.b2.uop.fp_ctrl.ldst connect slots_4.io.brupdate.b2.uop.op2_sel, issue_slots[4].brupdate.b2.uop.op2_sel connect slots_4.io.brupdate.b2.uop.op1_sel, issue_slots[4].brupdate.b2.uop.op1_sel connect slots_4.io.brupdate.b2.uop.imm_packed, issue_slots[4].brupdate.b2.uop.imm_packed connect slots_4.io.brupdate.b2.uop.pimm, issue_slots[4].brupdate.b2.uop.pimm connect slots_4.io.brupdate.b2.uop.imm_sel, issue_slots[4].brupdate.b2.uop.imm_sel connect slots_4.io.brupdate.b2.uop.imm_rename, issue_slots[4].brupdate.b2.uop.imm_rename connect slots_4.io.brupdate.b2.uop.taken, issue_slots[4].brupdate.b2.uop.taken connect slots_4.io.brupdate.b2.uop.pc_lob, issue_slots[4].brupdate.b2.uop.pc_lob connect slots_4.io.brupdate.b2.uop.edge_inst, issue_slots[4].brupdate.b2.uop.edge_inst connect slots_4.io.brupdate.b2.uop.ftq_idx, issue_slots[4].brupdate.b2.uop.ftq_idx connect slots_4.io.brupdate.b2.uop.is_mov, issue_slots[4].brupdate.b2.uop.is_mov connect slots_4.io.brupdate.b2.uop.is_rocc, issue_slots[4].brupdate.b2.uop.is_rocc connect slots_4.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[4].brupdate.b2.uop.is_sys_pc2epc connect slots_4.io.brupdate.b2.uop.is_eret, issue_slots[4].brupdate.b2.uop.is_eret connect slots_4.io.brupdate.b2.uop.is_amo, issue_slots[4].brupdate.b2.uop.is_amo connect slots_4.io.brupdate.b2.uop.is_sfence, issue_slots[4].brupdate.b2.uop.is_sfence connect slots_4.io.brupdate.b2.uop.is_fencei, issue_slots[4].brupdate.b2.uop.is_fencei connect slots_4.io.brupdate.b2.uop.is_fence, issue_slots[4].brupdate.b2.uop.is_fence connect slots_4.io.brupdate.b2.uop.is_sfb, issue_slots[4].brupdate.b2.uop.is_sfb connect slots_4.io.brupdate.b2.uop.br_type, issue_slots[4].brupdate.b2.uop.br_type connect slots_4.io.brupdate.b2.uop.br_tag, issue_slots[4].brupdate.b2.uop.br_tag connect slots_4.io.brupdate.b2.uop.br_mask, issue_slots[4].brupdate.b2.uop.br_mask connect slots_4.io.brupdate.b2.uop.dis_col_sel, issue_slots[4].brupdate.b2.uop.dis_col_sel connect slots_4.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[4].brupdate.b2.uop.iw_p3_bypass_hint connect slots_4.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[4].brupdate.b2.uop.iw_p2_bypass_hint connect slots_4.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[4].brupdate.b2.uop.iw_p1_bypass_hint connect slots_4.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[4].brupdate.b2.uop.iw_p2_speculative_child connect slots_4.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[4].brupdate.b2.uop.iw_p1_speculative_child connect slots_4.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[4].brupdate.b2.uop.iw_issued_partial_dgen connect slots_4.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[4].brupdate.b2.uop.iw_issued_partial_agen connect slots_4.io.brupdate.b2.uop.iw_issued, issue_slots[4].brupdate.b2.uop.iw_issued connect slots_4.io.brupdate.b2.uop.fu_code[0], issue_slots[4].brupdate.b2.uop.fu_code[0] connect slots_4.io.brupdate.b2.uop.fu_code[1], issue_slots[4].brupdate.b2.uop.fu_code[1] connect slots_4.io.brupdate.b2.uop.fu_code[2], issue_slots[4].brupdate.b2.uop.fu_code[2] connect slots_4.io.brupdate.b2.uop.fu_code[3], issue_slots[4].brupdate.b2.uop.fu_code[3] connect slots_4.io.brupdate.b2.uop.fu_code[4], issue_slots[4].brupdate.b2.uop.fu_code[4] connect slots_4.io.brupdate.b2.uop.fu_code[5], issue_slots[4].brupdate.b2.uop.fu_code[5] connect slots_4.io.brupdate.b2.uop.fu_code[6], issue_slots[4].brupdate.b2.uop.fu_code[6] connect slots_4.io.brupdate.b2.uop.fu_code[7], issue_slots[4].brupdate.b2.uop.fu_code[7] connect slots_4.io.brupdate.b2.uop.fu_code[8], issue_slots[4].brupdate.b2.uop.fu_code[8] connect slots_4.io.brupdate.b2.uop.fu_code[9], issue_slots[4].brupdate.b2.uop.fu_code[9] connect slots_4.io.brupdate.b2.uop.iq_type[0], issue_slots[4].brupdate.b2.uop.iq_type[0] connect slots_4.io.brupdate.b2.uop.iq_type[1], issue_slots[4].brupdate.b2.uop.iq_type[1] connect slots_4.io.brupdate.b2.uop.iq_type[2], issue_slots[4].brupdate.b2.uop.iq_type[2] connect slots_4.io.brupdate.b2.uop.iq_type[3], issue_slots[4].brupdate.b2.uop.iq_type[3] connect slots_4.io.brupdate.b2.uop.debug_pc, issue_slots[4].brupdate.b2.uop.debug_pc connect slots_4.io.brupdate.b2.uop.is_rvc, issue_slots[4].brupdate.b2.uop.is_rvc connect slots_4.io.brupdate.b2.uop.debug_inst, issue_slots[4].brupdate.b2.uop.debug_inst connect slots_4.io.brupdate.b2.uop.inst, issue_slots[4].brupdate.b2.uop.inst connect slots_4.io.brupdate.b1.mispredict_mask, issue_slots[4].brupdate.b1.mispredict_mask connect slots_4.io.brupdate.b1.resolve_mask, issue_slots[4].brupdate.b1.resolve_mask connect issue_slots[4].out_uop.debug_tsrc, slots_4.io.out_uop.debug_tsrc connect issue_slots[4].out_uop.debug_fsrc, slots_4.io.out_uop.debug_fsrc connect issue_slots[4].out_uop.bp_xcpt_if, slots_4.io.out_uop.bp_xcpt_if connect issue_slots[4].out_uop.bp_debug_if, slots_4.io.out_uop.bp_debug_if connect issue_slots[4].out_uop.xcpt_ma_if, slots_4.io.out_uop.xcpt_ma_if connect issue_slots[4].out_uop.xcpt_ae_if, slots_4.io.out_uop.xcpt_ae_if connect issue_slots[4].out_uop.xcpt_pf_if, slots_4.io.out_uop.xcpt_pf_if connect issue_slots[4].out_uop.fp_typ, slots_4.io.out_uop.fp_typ connect issue_slots[4].out_uop.fp_rm, slots_4.io.out_uop.fp_rm connect issue_slots[4].out_uop.fp_val, slots_4.io.out_uop.fp_val connect issue_slots[4].out_uop.fcn_op, slots_4.io.out_uop.fcn_op connect issue_slots[4].out_uop.fcn_dw, slots_4.io.out_uop.fcn_dw connect issue_slots[4].out_uop.frs3_en, slots_4.io.out_uop.frs3_en connect issue_slots[4].out_uop.lrs2_rtype, slots_4.io.out_uop.lrs2_rtype connect issue_slots[4].out_uop.lrs1_rtype, slots_4.io.out_uop.lrs1_rtype connect issue_slots[4].out_uop.dst_rtype, slots_4.io.out_uop.dst_rtype connect issue_slots[4].out_uop.lrs3, slots_4.io.out_uop.lrs3 connect issue_slots[4].out_uop.lrs2, slots_4.io.out_uop.lrs2 connect issue_slots[4].out_uop.lrs1, slots_4.io.out_uop.lrs1 connect issue_slots[4].out_uop.ldst, slots_4.io.out_uop.ldst connect issue_slots[4].out_uop.ldst_is_rs1, slots_4.io.out_uop.ldst_is_rs1 connect issue_slots[4].out_uop.csr_cmd, slots_4.io.out_uop.csr_cmd connect issue_slots[4].out_uop.flush_on_commit, slots_4.io.out_uop.flush_on_commit connect issue_slots[4].out_uop.is_unique, slots_4.io.out_uop.is_unique connect issue_slots[4].out_uop.uses_stq, slots_4.io.out_uop.uses_stq connect issue_slots[4].out_uop.uses_ldq, slots_4.io.out_uop.uses_ldq connect issue_slots[4].out_uop.mem_signed, slots_4.io.out_uop.mem_signed connect issue_slots[4].out_uop.mem_size, slots_4.io.out_uop.mem_size connect issue_slots[4].out_uop.mem_cmd, slots_4.io.out_uop.mem_cmd connect issue_slots[4].out_uop.exc_cause, slots_4.io.out_uop.exc_cause connect issue_slots[4].out_uop.exception, slots_4.io.out_uop.exception connect issue_slots[4].out_uop.stale_pdst, slots_4.io.out_uop.stale_pdst connect issue_slots[4].out_uop.ppred_busy, slots_4.io.out_uop.ppred_busy connect issue_slots[4].out_uop.prs3_busy, slots_4.io.out_uop.prs3_busy connect issue_slots[4].out_uop.prs2_busy, slots_4.io.out_uop.prs2_busy connect issue_slots[4].out_uop.prs1_busy, slots_4.io.out_uop.prs1_busy connect issue_slots[4].out_uop.ppred, slots_4.io.out_uop.ppred connect issue_slots[4].out_uop.prs3, slots_4.io.out_uop.prs3 connect issue_slots[4].out_uop.prs2, slots_4.io.out_uop.prs2 connect issue_slots[4].out_uop.prs1, slots_4.io.out_uop.prs1 connect issue_slots[4].out_uop.pdst, slots_4.io.out_uop.pdst connect issue_slots[4].out_uop.rxq_idx, slots_4.io.out_uop.rxq_idx connect issue_slots[4].out_uop.stq_idx, slots_4.io.out_uop.stq_idx connect issue_slots[4].out_uop.ldq_idx, slots_4.io.out_uop.ldq_idx connect issue_slots[4].out_uop.rob_idx, slots_4.io.out_uop.rob_idx connect issue_slots[4].out_uop.fp_ctrl.vec, slots_4.io.out_uop.fp_ctrl.vec connect issue_slots[4].out_uop.fp_ctrl.wflags, slots_4.io.out_uop.fp_ctrl.wflags connect issue_slots[4].out_uop.fp_ctrl.sqrt, slots_4.io.out_uop.fp_ctrl.sqrt connect issue_slots[4].out_uop.fp_ctrl.div, slots_4.io.out_uop.fp_ctrl.div connect issue_slots[4].out_uop.fp_ctrl.fma, slots_4.io.out_uop.fp_ctrl.fma connect issue_slots[4].out_uop.fp_ctrl.fastpipe, slots_4.io.out_uop.fp_ctrl.fastpipe connect issue_slots[4].out_uop.fp_ctrl.toint, slots_4.io.out_uop.fp_ctrl.toint connect issue_slots[4].out_uop.fp_ctrl.fromint, slots_4.io.out_uop.fp_ctrl.fromint connect issue_slots[4].out_uop.fp_ctrl.typeTagOut, slots_4.io.out_uop.fp_ctrl.typeTagOut connect issue_slots[4].out_uop.fp_ctrl.typeTagIn, slots_4.io.out_uop.fp_ctrl.typeTagIn connect issue_slots[4].out_uop.fp_ctrl.swap23, slots_4.io.out_uop.fp_ctrl.swap23 connect issue_slots[4].out_uop.fp_ctrl.swap12, slots_4.io.out_uop.fp_ctrl.swap12 connect issue_slots[4].out_uop.fp_ctrl.ren3, slots_4.io.out_uop.fp_ctrl.ren3 connect issue_slots[4].out_uop.fp_ctrl.ren2, slots_4.io.out_uop.fp_ctrl.ren2 connect issue_slots[4].out_uop.fp_ctrl.ren1, slots_4.io.out_uop.fp_ctrl.ren1 connect issue_slots[4].out_uop.fp_ctrl.wen, slots_4.io.out_uop.fp_ctrl.wen connect issue_slots[4].out_uop.fp_ctrl.ldst, slots_4.io.out_uop.fp_ctrl.ldst connect issue_slots[4].out_uop.op2_sel, slots_4.io.out_uop.op2_sel connect issue_slots[4].out_uop.op1_sel, slots_4.io.out_uop.op1_sel connect issue_slots[4].out_uop.imm_packed, slots_4.io.out_uop.imm_packed connect issue_slots[4].out_uop.pimm, slots_4.io.out_uop.pimm connect issue_slots[4].out_uop.imm_sel, slots_4.io.out_uop.imm_sel connect issue_slots[4].out_uop.imm_rename, slots_4.io.out_uop.imm_rename connect issue_slots[4].out_uop.taken, slots_4.io.out_uop.taken connect issue_slots[4].out_uop.pc_lob, slots_4.io.out_uop.pc_lob connect issue_slots[4].out_uop.edge_inst, slots_4.io.out_uop.edge_inst connect issue_slots[4].out_uop.ftq_idx, slots_4.io.out_uop.ftq_idx connect issue_slots[4].out_uop.is_mov, slots_4.io.out_uop.is_mov connect issue_slots[4].out_uop.is_rocc, slots_4.io.out_uop.is_rocc connect issue_slots[4].out_uop.is_sys_pc2epc, slots_4.io.out_uop.is_sys_pc2epc connect issue_slots[4].out_uop.is_eret, slots_4.io.out_uop.is_eret connect issue_slots[4].out_uop.is_amo, slots_4.io.out_uop.is_amo connect issue_slots[4].out_uop.is_sfence, slots_4.io.out_uop.is_sfence connect issue_slots[4].out_uop.is_fencei, slots_4.io.out_uop.is_fencei connect issue_slots[4].out_uop.is_fence, slots_4.io.out_uop.is_fence connect issue_slots[4].out_uop.is_sfb, slots_4.io.out_uop.is_sfb connect issue_slots[4].out_uop.br_type, slots_4.io.out_uop.br_type connect issue_slots[4].out_uop.br_tag, slots_4.io.out_uop.br_tag connect issue_slots[4].out_uop.br_mask, slots_4.io.out_uop.br_mask connect issue_slots[4].out_uop.dis_col_sel, slots_4.io.out_uop.dis_col_sel connect issue_slots[4].out_uop.iw_p3_bypass_hint, slots_4.io.out_uop.iw_p3_bypass_hint connect issue_slots[4].out_uop.iw_p2_bypass_hint, slots_4.io.out_uop.iw_p2_bypass_hint connect issue_slots[4].out_uop.iw_p1_bypass_hint, slots_4.io.out_uop.iw_p1_bypass_hint connect issue_slots[4].out_uop.iw_p2_speculative_child, slots_4.io.out_uop.iw_p2_speculative_child connect issue_slots[4].out_uop.iw_p1_speculative_child, slots_4.io.out_uop.iw_p1_speculative_child connect issue_slots[4].out_uop.iw_issued_partial_dgen, slots_4.io.out_uop.iw_issued_partial_dgen connect issue_slots[4].out_uop.iw_issued_partial_agen, slots_4.io.out_uop.iw_issued_partial_agen connect issue_slots[4].out_uop.iw_issued, slots_4.io.out_uop.iw_issued connect issue_slots[4].out_uop.fu_code[0], slots_4.io.out_uop.fu_code[0] connect issue_slots[4].out_uop.fu_code[1], slots_4.io.out_uop.fu_code[1] connect issue_slots[4].out_uop.fu_code[2], slots_4.io.out_uop.fu_code[2] connect issue_slots[4].out_uop.fu_code[3], slots_4.io.out_uop.fu_code[3] connect issue_slots[4].out_uop.fu_code[4], slots_4.io.out_uop.fu_code[4] connect issue_slots[4].out_uop.fu_code[5], slots_4.io.out_uop.fu_code[5] connect issue_slots[4].out_uop.fu_code[6], slots_4.io.out_uop.fu_code[6] connect issue_slots[4].out_uop.fu_code[7], slots_4.io.out_uop.fu_code[7] connect issue_slots[4].out_uop.fu_code[8], slots_4.io.out_uop.fu_code[8] connect issue_slots[4].out_uop.fu_code[9], slots_4.io.out_uop.fu_code[9] connect issue_slots[4].out_uop.iq_type[0], slots_4.io.out_uop.iq_type[0] connect issue_slots[4].out_uop.iq_type[1], slots_4.io.out_uop.iq_type[1] connect issue_slots[4].out_uop.iq_type[2], slots_4.io.out_uop.iq_type[2] connect issue_slots[4].out_uop.iq_type[3], slots_4.io.out_uop.iq_type[3] connect issue_slots[4].out_uop.debug_pc, slots_4.io.out_uop.debug_pc connect issue_slots[4].out_uop.is_rvc, slots_4.io.out_uop.is_rvc connect issue_slots[4].out_uop.debug_inst, slots_4.io.out_uop.debug_inst connect issue_slots[4].out_uop.inst, slots_4.io.out_uop.inst connect slots_4.io.in_uop.bits.debug_tsrc, issue_slots[4].in_uop.bits.debug_tsrc connect slots_4.io.in_uop.bits.debug_fsrc, issue_slots[4].in_uop.bits.debug_fsrc connect slots_4.io.in_uop.bits.bp_xcpt_if, issue_slots[4].in_uop.bits.bp_xcpt_if connect slots_4.io.in_uop.bits.bp_debug_if, issue_slots[4].in_uop.bits.bp_debug_if connect slots_4.io.in_uop.bits.xcpt_ma_if, issue_slots[4].in_uop.bits.xcpt_ma_if connect slots_4.io.in_uop.bits.xcpt_ae_if, issue_slots[4].in_uop.bits.xcpt_ae_if connect slots_4.io.in_uop.bits.xcpt_pf_if, issue_slots[4].in_uop.bits.xcpt_pf_if connect slots_4.io.in_uop.bits.fp_typ, issue_slots[4].in_uop.bits.fp_typ connect slots_4.io.in_uop.bits.fp_rm, issue_slots[4].in_uop.bits.fp_rm connect slots_4.io.in_uop.bits.fp_val, issue_slots[4].in_uop.bits.fp_val connect slots_4.io.in_uop.bits.fcn_op, issue_slots[4].in_uop.bits.fcn_op connect slots_4.io.in_uop.bits.fcn_dw, issue_slots[4].in_uop.bits.fcn_dw connect slots_4.io.in_uop.bits.frs3_en, issue_slots[4].in_uop.bits.frs3_en connect slots_4.io.in_uop.bits.lrs2_rtype, issue_slots[4].in_uop.bits.lrs2_rtype connect slots_4.io.in_uop.bits.lrs1_rtype, issue_slots[4].in_uop.bits.lrs1_rtype connect slots_4.io.in_uop.bits.dst_rtype, issue_slots[4].in_uop.bits.dst_rtype connect slots_4.io.in_uop.bits.lrs3, issue_slots[4].in_uop.bits.lrs3 connect slots_4.io.in_uop.bits.lrs2, issue_slots[4].in_uop.bits.lrs2 connect slots_4.io.in_uop.bits.lrs1, issue_slots[4].in_uop.bits.lrs1 connect slots_4.io.in_uop.bits.ldst, issue_slots[4].in_uop.bits.ldst connect slots_4.io.in_uop.bits.ldst_is_rs1, issue_slots[4].in_uop.bits.ldst_is_rs1 connect slots_4.io.in_uop.bits.csr_cmd, issue_slots[4].in_uop.bits.csr_cmd connect slots_4.io.in_uop.bits.flush_on_commit, issue_slots[4].in_uop.bits.flush_on_commit connect slots_4.io.in_uop.bits.is_unique, issue_slots[4].in_uop.bits.is_unique connect slots_4.io.in_uop.bits.uses_stq, issue_slots[4].in_uop.bits.uses_stq connect slots_4.io.in_uop.bits.uses_ldq, issue_slots[4].in_uop.bits.uses_ldq connect slots_4.io.in_uop.bits.mem_signed, issue_slots[4].in_uop.bits.mem_signed connect slots_4.io.in_uop.bits.mem_size, issue_slots[4].in_uop.bits.mem_size connect slots_4.io.in_uop.bits.mem_cmd, issue_slots[4].in_uop.bits.mem_cmd connect slots_4.io.in_uop.bits.exc_cause, issue_slots[4].in_uop.bits.exc_cause connect slots_4.io.in_uop.bits.exception, issue_slots[4].in_uop.bits.exception connect slots_4.io.in_uop.bits.stale_pdst, issue_slots[4].in_uop.bits.stale_pdst connect slots_4.io.in_uop.bits.ppred_busy, issue_slots[4].in_uop.bits.ppred_busy connect slots_4.io.in_uop.bits.prs3_busy, issue_slots[4].in_uop.bits.prs3_busy connect slots_4.io.in_uop.bits.prs2_busy, issue_slots[4].in_uop.bits.prs2_busy connect slots_4.io.in_uop.bits.prs1_busy, issue_slots[4].in_uop.bits.prs1_busy connect slots_4.io.in_uop.bits.ppred, issue_slots[4].in_uop.bits.ppred connect slots_4.io.in_uop.bits.prs3, issue_slots[4].in_uop.bits.prs3 connect slots_4.io.in_uop.bits.prs2, issue_slots[4].in_uop.bits.prs2 connect slots_4.io.in_uop.bits.prs1, issue_slots[4].in_uop.bits.prs1 connect slots_4.io.in_uop.bits.pdst, issue_slots[4].in_uop.bits.pdst connect slots_4.io.in_uop.bits.rxq_idx, issue_slots[4].in_uop.bits.rxq_idx connect slots_4.io.in_uop.bits.stq_idx, issue_slots[4].in_uop.bits.stq_idx connect slots_4.io.in_uop.bits.ldq_idx, issue_slots[4].in_uop.bits.ldq_idx connect slots_4.io.in_uop.bits.rob_idx, issue_slots[4].in_uop.bits.rob_idx connect slots_4.io.in_uop.bits.fp_ctrl.vec, issue_slots[4].in_uop.bits.fp_ctrl.vec connect slots_4.io.in_uop.bits.fp_ctrl.wflags, issue_slots[4].in_uop.bits.fp_ctrl.wflags connect slots_4.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[4].in_uop.bits.fp_ctrl.sqrt connect slots_4.io.in_uop.bits.fp_ctrl.div, issue_slots[4].in_uop.bits.fp_ctrl.div connect slots_4.io.in_uop.bits.fp_ctrl.fma, issue_slots[4].in_uop.bits.fp_ctrl.fma connect slots_4.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[4].in_uop.bits.fp_ctrl.fastpipe connect slots_4.io.in_uop.bits.fp_ctrl.toint, issue_slots[4].in_uop.bits.fp_ctrl.toint connect slots_4.io.in_uop.bits.fp_ctrl.fromint, issue_slots[4].in_uop.bits.fp_ctrl.fromint connect slots_4.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[4].in_uop.bits.fp_ctrl.typeTagOut connect slots_4.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[4].in_uop.bits.fp_ctrl.typeTagIn connect slots_4.io.in_uop.bits.fp_ctrl.swap23, issue_slots[4].in_uop.bits.fp_ctrl.swap23 connect slots_4.io.in_uop.bits.fp_ctrl.swap12, issue_slots[4].in_uop.bits.fp_ctrl.swap12 connect slots_4.io.in_uop.bits.fp_ctrl.ren3, issue_slots[4].in_uop.bits.fp_ctrl.ren3 connect slots_4.io.in_uop.bits.fp_ctrl.ren2, issue_slots[4].in_uop.bits.fp_ctrl.ren2 connect slots_4.io.in_uop.bits.fp_ctrl.ren1, issue_slots[4].in_uop.bits.fp_ctrl.ren1 connect slots_4.io.in_uop.bits.fp_ctrl.wen, issue_slots[4].in_uop.bits.fp_ctrl.wen connect slots_4.io.in_uop.bits.fp_ctrl.ldst, issue_slots[4].in_uop.bits.fp_ctrl.ldst connect slots_4.io.in_uop.bits.op2_sel, issue_slots[4].in_uop.bits.op2_sel connect slots_4.io.in_uop.bits.op1_sel, issue_slots[4].in_uop.bits.op1_sel connect slots_4.io.in_uop.bits.imm_packed, issue_slots[4].in_uop.bits.imm_packed connect slots_4.io.in_uop.bits.pimm, issue_slots[4].in_uop.bits.pimm connect slots_4.io.in_uop.bits.imm_sel, issue_slots[4].in_uop.bits.imm_sel connect slots_4.io.in_uop.bits.imm_rename, issue_slots[4].in_uop.bits.imm_rename connect slots_4.io.in_uop.bits.taken, issue_slots[4].in_uop.bits.taken connect slots_4.io.in_uop.bits.pc_lob, issue_slots[4].in_uop.bits.pc_lob connect slots_4.io.in_uop.bits.edge_inst, issue_slots[4].in_uop.bits.edge_inst connect slots_4.io.in_uop.bits.ftq_idx, issue_slots[4].in_uop.bits.ftq_idx connect slots_4.io.in_uop.bits.is_mov, issue_slots[4].in_uop.bits.is_mov connect slots_4.io.in_uop.bits.is_rocc, issue_slots[4].in_uop.bits.is_rocc connect slots_4.io.in_uop.bits.is_sys_pc2epc, issue_slots[4].in_uop.bits.is_sys_pc2epc connect slots_4.io.in_uop.bits.is_eret, issue_slots[4].in_uop.bits.is_eret connect slots_4.io.in_uop.bits.is_amo, issue_slots[4].in_uop.bits.is_amo connect slots_4.io.in_uop.bits.is_sfence, issue_slots[4].in_uop.bits.is_sfence connect slots_4.io.in_uop.bits.is_fencei, issue_slots[4].in_uop.bits.is_fencei connect slots_4.io.in_uop.bits.is_fence, issue_slots[4].in_uop.bits.is_fence connect slots_4.io.in_uop.bits.is_sfb, issue_slots[4].in_uop.bits.is_sfb connect slots_4.io.in_uop.bits.br_type, issue_slots[4].in_uop.bits.br_type connect slots_4.io.in_uop.bits.br_tag, issue_slots[4].in_uop.bits.br_tag connect slots_4.io.in_uop.bits.br_mask, issue_slots[4].in_uop.bits.br_mask connect slots_4.io.in_uop.bits.dis_col_sel, issue_slots[4].in_uop.bits.dis_col_sel connect slots_4.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[4].in_uop.bits.iw_p3_bypass_hint connect slots_4.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[4].in_uop.bits.iw_p2_bypass_hint connect slots_4.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[4].in_uop.bits.iw_p1_bypass_hint connect slots_4.io.in_uop.bits.iw_p2_speculative_child, issue_slots[4].in_uop.bits.iw_p2_speculative_child connect slots_4.io.in_uop.bits.iw_p1_speculative_child, issue_slots[4].in_uop.bits.iw_p1_speculative_child connect slots_4.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[4].in_uop.bits.iw_issued_partial_dgen connect slots_4.io.in_uop.bits.iw_issued_partial_agen, issue_slots[4].in_uop.bits.iw_issued_partial_agen connect slots_4.io.in_uop.bits.iw_issued, issue_slots[4].in_uop.bits.iw_issued connect slots_4.io.in_uop.bits.fu_code[0], issue_slots[4].in_uop.bits.fu_code[0] connect slots_4.io.in_uop.bits.fu_code[1], issue_slots[4].in_uop.bits.fu_code[1] connect slots_4.io.in_uop.bits.fu_code[2], issue_slots[4].in_uop.bits.fu_code[2] connect slots_4.io.in_uop.bits.fu_code[3], issue_slots[4].in_uop.bits.fu_code[3] connect slots_4.io.in_uop.bits.fu_code[4], issue_slots[4].in_uop.bits.fu_code[4] connect slots_4.io.in_uop.bits.fu_code[5], issue_slots[4].in_uop.bits.fu_code[5] connect slots_4.io.in_uop.bits.fu_code[6], issue_slots[4].in_uop.bits.fu_code[6] connect slots_4.io.in_uop.bits.fu_code[7], issue_slots[4].in_uop.bits.fu_code[7] connect slots_4.io.in_uop.bits.fu_code[8], issue_slots[4].in_uop.bits.fu_code[8] connect slots_4.io.in_uop.bits.fu_code[9], issue_slots[4].in_uop.bits.fu_code[9] connect slots_4.io.in_uop.bits.iq_type[0], issue_slots[4].in_uop.bits.iq_type[0] connect slots_4.io.in_uop.bits.iq_type[1], issue_slots[4].in_uop.bits.iq_type[1] connect slots_4.io.in_uop.bits.iq_type[2], issue_slots[4].in_uop.bits.iq_type[2] connect slots_4.io.in_uop.bits.iq_type[3], issue_slots[4].in_uop.bits.iq_type[3] connect slots_4.io.in_uop.bits.debug_pc, issue_slots[4].in_uop.bits.debug_pc connect slots_4.io.in_uop.bits.is_rvc, issue_slots[4].in_uop.bits.is_rvc connect slots_4.io.in_uop.bits.debug_inst, issue_slots[4].in_uop.bits.debug_inst connect slots_4.io.in_uop.bits.inst, issue_slots[4].in_uop.bits.inst connect slots_4.io.in_uop.valid, issue_slots[4].in_uop.valid connect issue_slots[4].iss_uop.debug_tsrc, slots_4.io.iss_uop.debug_tsrc connect issue_slots[4].iss_uop.debug_fsrc, slots_4.io.iss_uop.debug_fsrc connect issue_slots[4].iss_uop.bp_xcpt_if, slots_4.io.iss_uop.bp_xcpt_if connect issue_slots[4].iss_uop.bp_debug_if, slots_4.io.iss_uop.bp_debug_if connect issue_slots[4].iss_uop.xcpt_ma_if, slots_4.io.iss_uop.xcpt_ma_if connect issue_slots[4].iss_uop.xcpt_ae_if, slots_4.io.iss_uop.xcpt_ae_if connect issue_slots[4].iss_uop.xcpt_pf_if, slots_4.io.iss_uop.xcpt_pf_if connect issue_slots[4].iss_uop.fp_typ, slots_4.io.iss_uop.fp_typ connect issue_slots[4].iss_uop.fp_rm, slots_4.io.iss_uop.fp_rm connect issue_slots[4].iss_uop.fp_val, slots_4.io.iss_uop.fp_val connect issue_slots[4].iss_uop.fcn_op, slots_4.io.iss_uop.fcn_op connect issue_slots[4].iss_uop.fcn_dw, slots_4.io.iss_uop.fcn_dw connect issue_slots[4].iss_uop.frs3_en, slots_4.io.iss_uop.frs3_en connect issue_slots[4].iss_uop.lrs2_rtype, slots_4.io.iss_uop.lrs2_rtype connect issue_slots[4].iss_uop.lrs1_rtype, slots_4.io.iss_uop.lrs1_rtype connect issue_slots[4].iss_uop.dst_rtype, slots_4.io.iss_uop.dst_rtype connect issue_slots[4].iss_uop.lrs3, slots_4.io.iss_uop.lrs3 connect issue_slots[4].iss_uop.lrs2, slots_4.io.iss_uop.lrs2 connect issue_slots[4].iss_uop.lrs1, slots_4.io.iss_uop.lrs1 connect issue_slots[4].iss_uop.ldst, slots_4.io.iss_uop.ldst connect issue_slots[4].iss_uop.ldst_is_rs1, slots_4.io.iss_uop.ldst_is_rs1 connect issue_slots[4].iss_uop.csr_cmd, slots_4.io.iss_uop.csr_cmd connect issue_slots[4].iss_uop.flush_on_commit, slots_4.io.iss_uop.flush_on_commit connect issue_slots[4].iss_uop.is_unique, slots_4.io.iss_uop.is_unique connect issue_slots[4].iss_uop.uses_stq, slots_4.io.iss_uop.uses_stq connect issue_slots[4].iss_uop.uses_ldq, slots_4.io.iss_uop.uses_ldq connect issue_slots[4].iss_uop.mem_signed, slots_4.io.iss_uop.mem_signed connect issue_slots[4].iss_uop.mem_size, slots_4.io.iss_uop.mem_size connect issue_slots[4].iss_uop.mem_cmd, slots_4.io.iss_uop.mem_cmd connect issue_slots[4].iss_uop.exc_cause, slots_4.io.iss_uop.exc_cause connect issue_slots[4].iss_uop.exception, slots_4.io.iss_uop.exception connect issue_slots[4].iss_uop.stale_pdst, slots_4.io.iss_uop.stale_pdst connect issue_slots[4].iss_uop.ppred_busy, slots_4.io.iss_uop.ppred_busy connect issue_slots[4].iss_uop.prs3_busy, slots_4.io.iss_uop.prs3_busy connect issue_slots[4].iss_uop.prs2_busy, slots_4.io.iss_uop.prs2_busy connect issue_slots[4].iss_uop.prs1_busy, slots_4.io.iss_uop.prs1_busy connect issue_slots[4].iss_uop.ppred, slots_4.io.iss_uop.ppred connect issue_slots[4].iss_uop.prs3, slots_4.io.iss_uop.prs3 connect issue_slots[4].iss_uop.prs2, slots_4.io.iss_uop.prs2 connect issue_slots[4].iss_uop.prs1, slots_4.io.iss_uop.prs1 connect issue_slots[4].iss_uop.pdst, slots_4.io.iss_uop.pdst connect issue_slots[4].iss_uop.rxq_idx, slots_4.io.iss_uop.rxq_idx connect issue_slots[4].iss_uop.stq_idx, slots_4.io.iss_uop.stq_idx connect issue_slots[4].iss_uop.ldq_idx, slots_4.io.iss_uop.ldq_idx connect issue_slots[4].iss_uop.rob_idx, slots_4.io.iss_uop.rob_idx connect issue_slots[4].iss_uop.fp_ctrl.vec, slots_4.io.iss_uop.fp_ctrl.vec connect issue_slots[4].iss_uop.fp_ctrl.wflags, slots_4.io.iss_uop.fp_ctrl.wflags connect issue_slots[4].iss_uop.fp_ctrl.sqrt, slots_4.io.iss_uop.fp_ctrl.sqrt connect issue_slots[4].iss_uop.fp_ctrl.div, slots_4.io.iss_uop.fp_ctrl.div connect issue_slots[4].iss_uop.fp_ctrl.fma, slots_4.io.iss_uop.fp_ctrl.fma connect issue_slots[4].iss_uop.fp_ctrl.fastpipe, slots_4.io.iss_uop.fp_ctrl.fastpipe connect issue_slots[4].iss_uop.fp_ctrl.toint, slots_4.io.iss_uop.fp_ctrl.toint connect issue_slots[4].iss_uop.fp_ctrl.fromint, slots_4.io.iss_uop.fp_ctrl.fromint connect issue_slots[4].iss_uop.fp_ctrl.typeTagOut, slots_4.io.iss_uop.fp_ctrl.typeTagOut connect issue_slots[4].iss_uop.fp_ctrl.typeTagIn, slots_4.io.iss_uop.fp_ctrl.typeTagIn connect issue_slots[4].iss_uop.fp_ctrl.swap23, slots_4.io.iss_uop.fp_ctrl.swap23 connect issue_slots[4].iss_uop.fp_ctrl.swap12, slots_4.io.iss_uop.fp_ctrl.swap12 connect issue_slots[4].iss_uop.fp_ctrl.ren3, slots_4.io.iss_uop.fp_ctrl.ren3 connect issue_slots[4].iss_uop.fp_ctrl.ren2, slots_4.io.iss_uop.fp_ctrl.ren2 connect issue_slots[4].iss_uop.fp_ctrl.ren1, slots_4.io.iss_uop.fp_ctrl.ren1 connect issue_slots[4].iss_uop.fp_ctrl.wen, slots_4.io.iss_uop.fp_ctrl.wen connect issue_slots[4].iss_uop.fp_ctrl.ldst, slots_4.io.iss_uop.fp_ctrl.ldst connect issue_slots[4].iss_uop.op2_sel, slots_4.io.iss_uop.op2_sel connect issue_slots[4].iss_uop.op1_sel, slots_4.io.iss_uop.op1_sel connect issue_slots[4].iss_uop.imm_packed, slots_4.io.iss_uop.imm_packed connect issue_slots[4].iss_uop.pimm, slots_4.io.iss_uop.pimm connect issue_slots[4].iss_uop.imm_sel, slots_4.io.iss_uop.imm_sel connect issue_slots[4].iss_uop.imm_rename, slots_4.io.iss_uop.imm_rename connect issue_slots[4].iss_uop.taken, slots_4.io.iss_uop.taken connect issue_slots[4].iss_uop.pc_lob, slots_4.io.iss_uop.pc_lob connect issue_slots[4].iss_uop.edge_inst, slots_4.io.iss_uop.edge_inst connect issue_slots[4].iss_uop.ftq_idx, slots_4.io.iss_uop.ftq_idx connect issue_slots[4].iss_uop.is_mov, slots_4.io.iss_uop.is_mov connect issue_slots[4].iss_uop.is_rocc, slots_4.io.iss_uop.is_rocc connect issue_slots[4].iss_uop.is_sys_pc2epc, slots_4.io.iss_uop.is_sys_pc2epc connect issue_slots[4].iss_uop.is_eret, slots_4.io.iss_uop.is_eret connect issue_slots[4].iss_uop.is_amo, slots_4.io.iss_uop.is_amo connect issue_slots[4].iss_uop.is_sfence, slots_4.io.iss_uop.is_sfence connect issue_slots[4].iss_uop.is_fencei, slots_4.io.iss_uop.is_fencei connect issue_slots[4].iss_uop.is_fence, slots_4.io.iss_uop.is_fence connect issue_slots[4].iss_uop.is_sfb, slots_4.io.iss_uop.is_sfb connect issue_slots[4].iss_uop.br_type, slots_4.io.iss_uop.br_type connect issue_slots[4].iss_uop.br_tag, slots_4.io.iss_uop.br_tag connect issue_slots[4].iss_uop.br_mask, slots_4.io.iss_uop.br_mask connect issue_slots[4].iss_uop.dis_col_sel, slots_4.io.iss_uop.dis_col_sel connect issue_slots[4].iss_uop.iw_p3_bypass_hint, slots_4.io.iss_uop.iw_p3_bypass_hint connect issue_slots[4].iss_uop.iw_p2_bypass_hint, slots_4.io.iss_uop.iw_p2_bypass_hint connect issue_slots[4].iss_uop.iw_p1_bypass_hint, slots_4.io.iss_uop.iw_p1_bypass_hint connect issue_slots[4].iss_uop.iw_p2_speculative_child, slots_4.io.iss_uop.iw_p2_speculative_child connect issue_slots[4].iss_uop.iw_p1_speculative_child, slots_4.io.iss_uop.iw_p1_speculative_child connect issue_slots[4].iss_uop.iw_issued_partial_dgen, slots_4.io.iss_uop.iw_issued_partial_dgen connect issue_slots[4].iss_uop.iw_issued_partial_agen, slots_4.io.iss_uop.iw_issued_partial_agen connect issue_slots[4].iss_uop.iw_issued, slots_4.io.iss_uop.iw_issued connect issue_slots[4].iss_uop.fu_code[0], slots_4.io.iss_uop.fu_code[0] connect issue_slots[4].iss_uop.fu_code[1], slots_4.io.iss_uop.fu_code[1] connect issue_slots[4].iss_uop.fu_code[2], slots_4.io.iss_uop.fu_code[2] connect issue_slots[4].iss_uop.fu_code[3], slots_4.io.iss_uop.fu_code[3] connect issue_slots[4].iss_uop.fu_code[4], slots_4.io.iss_uop.fu_code[4] connect issue_slots[4].iss_uop.fu_code[5], slots_4.io.iss_uop.fu_code[5] connect issue_slots[4].iss_uop.fu_code[6], slots_4.io.iss_uop.fu_code[6] connect issue_slots[4].iss_uop.fu_code[7], slots_4.io.iss_uop.fu_code[7] connect issue_slots[4].iss_uop.fu_code[8], slots_4.io.iss_uop.fu_code[8] connect issue_slots[4].iss_uop.fu_code[9], slots_4.io.iss_uop.fu_code[9] connect issue_slots[4].iss_uop.iq_type[0], slots_4.io.iss_uop.iq_type[0] connect issue_slots[4].iss_uop.iq_type[1], slots_4.io.iss_uop.iq_type[1] connect issue_slots[4].iss_uop.iq_type[2], slots_4.io.iss_uop.iq_type[2] connect issue_slots[4].iss_uop.iq_type[3], slots_4.io.iss_uop.iq_type[3] connect issue_slots[4].iss_uop.debug_pc, slots_4.io.iss_uop.debug_pc connect issue_slots[4].iss_uop.is_rvc, slots_4.io.iss_uop.is_rvc connect issue_slots[4].iss_uop.debug_inst, slots_4.io.iss_uop.debug_inst connect issue_slots[4].iss_uop.inst, slots_4.io.iss_uop.inst connect slots_4.io.grant, issue_slots[4].grant connect issue_slots[4].request, slots_4.io.request connect issue_slots[4].will_be_valid, slots_4.io.will_be_valid connect issue_slots[4].valid, slots_4.io.valid connect slots_5.io.child_rebusys, issue_slots[5].child_rebusys connect slots_5.io.pred_wakeup_port.bits, issue_slots[5].pred_wakeup_port.bits connect slots_5.io.pred_wakeup_port.valid, issue_slots[5].pred_wakeup_port.valid connect slots_5.io.wakeup_ports[0].bits.rebusy, issue_slots[5].wakeup_ports[0].bits.rebusy connect slots_5.io.wakeup_ports[0].bits.speculative_mask, issue_slots[5].wakeup_ports[0].bits.speculative_mask connect slots_5.io.wakeup_ports[0].bits.bypassable, issue_slots[5].wakeup_ports[0].bits.bypassable connect slots_5.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[5].wakeup_ports[0].bits.uop.debug_tsrc connect slots_5.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[5].wakeup_ports[0].bits.uop.debug_fsrc connect slots_5.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[5].wakeup_ports[0].bits.uop.bp_xcpt_if connect slots_5.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[5].wakeup_ports[0].bits.uop.bp_debug_if connect slots_5.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[5].wakeup_ports[0].bits.uop.xcpt_ma_if connect slots_5.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[5].wakeup_ports[0].bits.uop.xcpt_ae_if connect slots_5.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[5].wakeup_ports[0].bits.uop.xcpt_pf_if connect slots_5.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[5].wakeup_ports[0].bits.uop.fp_typ connect slots_5.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[5].wakeup_ports[0].bits.uop.fp_rm connect slots_5.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[5].wakeup_ports[0].bits.uop.fp_val connect slots_5.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[5].wakeup_ports[0].bits.uop.fcn_op connect slots_5.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[5].wakeup_ports[0].bits.uop.fcn_dw connect slots_5.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[5].wakeup_ports[0].bits.uop.frs3_en connect slots_5.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[5].wakeup_ports[0].bits.uop.lrs2_rtype connect slots_5.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[5].wakeup_ports[0].bits.uop.lrs1_rtype connect slots_5.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[5].wakeup_ports[0].bits.uop.dst_rtype connect slots_5.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[5].wakeup_ports[0].bits.uop.lrs3 connect slots_5.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[5].wakeup_ports[0].bits.uop.lrs2 connect slots_5.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[5].wakeup_ports[0].bits.uop.lrs1 connect slots_5.io.wakeup_ports[0].bits.uop.ldst, issue_slots[5].wakeup_ports[0].bits.uop.ldst connect slots_5.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[5].wakeup_ports[0].bits.uop.ldst_is_rs1 connect slots_5.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[5].wakeup_ports[0].bits.uop.csr_cmd connect slots_5.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[5].wakeup_ports[0].bits.uop.flush_on_commit connect slots_5.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[5].wakeup_ports[0].bits.uop.is_unique connect slots_5.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[5].wakeup_ports[0].bits.uop.uses_stq connect slots_5.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[5].wakeup_ports[0].bits.uop.uses_ldq connect slots_5.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[5].wakeup_ports[0].bits.uop.mem_signed connect slots_5.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[5].wakeup_ports[0].bits.uop.mem_size connect slots_5.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[5].wakeup_ports[0].bits.uop.mem_cmd connect slots_5.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[5].wakeup_ports[0].bits.uop.exc_cause connect slots_5.io.wakeup_ports[0].bits.uop.exception, issue_slots[5].wakeup_ports[0].bits.uop.exception connect slots_5.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[5].wakeup_ports[0].bits.uop.stale_pdst connect slots_5.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[5].wakeup_ports[0].bits.uop.ppred_busy connect slots_5.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[5].wakeup_ports[0].bits.uop.prs3_busy connect slots_5.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[5].wakeup_ports[0].bits.uop.prs2_busy connect slots_5.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[5].wakeup_ports[0].bits.uop.prs1_busy connect slots_5.io.wakeup_ports[0].bits.uop.ppred, issue_slots[5].wakeup_ports[0].bits.uop.ppred connect slots_5.io.wakeup_ports[0].bits.uop.prs3, issue_slots[5].wakeup_ports[0].bits.uop.prs3 connect slots_5.io.wakeup_ports[0].bits.uop.prs2, issue_slots[5].wakeup_ports[0].bits.uop.prs2 connect slots_5.io.wakeup_ports[0].bits.uop.prs1, issue_slots[5].wakeup_ports[0].bits.uop.prs1 connect slots_5.io.wakeup_ports[0].bits.uop.pdst, issue_slots[5].wakeup_ports[0].bits.uop.pdst connect slots_5.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[5].wakeup_ports[0].bits.uop.rxq_idx connect slots_5.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[5].wakeup_ports[0].bits.uop.stq_idx connect slots_5.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[5].wakeup_ports[0].bits.uop.ldq_idx connect slots_5.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[5].wakeup_ports[0].bits.uop.rob_idx connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.vec connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.wflags connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.div connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.fma connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.toint connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.fromint connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.wen connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.ldst connect slots_5.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[5].wakeup_ports[0].bits.uop.op2_sel connect slots_5.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[5].wakeup_ports[0].bits.uop.op1_sel connect slots_5.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[5].wakeup_ports[0].bits.uop.imm_packed connect slots_5.io.wakeup_ports[0].bits.uop.pimm, issue_slots[5].wakeup_ports[0].bits.uop.pimm connect slots_5.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[5].wakeup_ports[0].bits.uop.imm_sel connect slots_5.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[5].wakeup_ports[0].bits.uop.imm_rename connect slots_5.io.wakeup_ports[0].bits.uop.taken, issue_slots[5].wakeup_ports[0].bits.uop.taken connect slots_5.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[5].wakeup_ports[0].bits.uop.pc_lob connect slots_5.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[5].wakeup_ports[0].bits.uop.edge_inst connect slots_5.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[5].wakeup_ports[0].bits.uop.ftq_idx connect slots_5.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[5].wakeup_ports[0].bits.uop.is_mov connect slots_5.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[5].wakeup_ports[0].bits.uop.is_rocc connect slots_5.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[5].wakeup_ports[0].bits.uop.is_sys_pc2epc connect slots_5.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[5].wakeup_ports[0].bits.uop.is_eret connect slots_5.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[5].wakeup_ports[0].bits.uop.is_amo connect slots_5.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[5].wakeup_ports[0].bits.uop.is_sfence connect slots_5.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[5].wakeup_ports[0].bits.uop.is_fencei connect slots_5.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[5].wakeup_ports[0].bits.uop.is_fence connect slots_5.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[5].wakeup_ports[0].bits.uop.is_sfb connect slots_5.io.wakeup_ports[0].bits.uop.br_type, issue_slots[5].wakeup_ports[0].bits.uop.br_type connect slots_5.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[5].wakeup_ports[0].bits.uop.br_tag connect slots_5.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[5].wakeup_ports[0].bits.uop.br_mask connect slots_5.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[5].wakeup_ports[0].bits.uop.dis_col_sel connect slots_5.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[5].wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect slots_5.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[5].wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect slots_5.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[5].wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect slots_5.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[5].wakeup_ports[0].bits.uop.iw_p2_speculative_child connect slots_5.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[5].wakeup_ports[0].bits.uop.iw_p1_speculative_child connect slots_5.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[5].wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect slots_5.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[5].wakeup_ports[0].bits.uop.iw_issued_partial_agen connect slots_5.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[5].wakeup_ports[0].bits.uop.iw_issued connect slots_5.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[5].wakeup_ports[0].bits.uop.fu_code[0] connect slots_5.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[5].wakeup_ports[0].bits.uop.fu_code[1] connect slots_5.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[5].wakeup_ports[0].bits.uop.fu_code[2] connect slots_5.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[5].wakeup_ports[0].bits.uop.fu_code[3] connect slots_5.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[5].wakeup_ports[0].bits.uop.fu_code[4] connect slots_5.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[5].wakeup_ports[0].bits.uop.fu_code[5] connect slots_5.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[5].wakeup_ports[0].bits.uop.fu_code[6] connect slots_5.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[5].wakeup_ports[0].bits.uop.fu_code[7] connect slots_5.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[5].wakeup_ports[0].bits.uop.fu_code[8] connect slots_5.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[5].wakeup_ports[0].bits.uop.fu_code[9] connect slots_5.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[5].wakeup_ports[0].bits.uop.iq_type[0] connect slots_5.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[5].wakeup_ports[0].bits.uop.iq_type[1] connect slots_5.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[5].wakeup_ports[0].bits.uop.iq_type[2] connect slots_5.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[5].wakeup_ports[0].bits.uop.iq_type[3] connect slots_5.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[5].wakeup_ports[0].bits.uop.debug_pc connect slots_5.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[5].wakeup_ports[0].bits.uop.is_rvc connect slots_5.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[5].wakeup_ports[0].bits.uop.debug_inst connect slots_5.io.wakeup_ports[0].bits.uop.inst, issue_slots[5].wakeup_ports[0].bits.uop.inst connect slots_5.io.wakeup_ports[0].valid, issue_slots[5].wakeup_ports[0].valid connect slots_5.io.wakeup_ports[1].bits.rebusy, issue_slots[5].wakeup_ports[1].bits.rebusy connect slots_5.io.wakeup_ports[1].bits.speculative_mask, issue_slots[5].wakeup_ports[1].bits.speculative_mask connect slots_5.io.wakeup_ports[1].bits.bypassable, issue_slots[5].wakeup_ports[1].bits.bypassable connect slots_5.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[5].wakeup_ports[1].bits.uop.debug_tsrc connect slots_5.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[5].wakeup_ports[1].bits.uop.debug_fsrc connect slots_5.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[5].wakeup_ports[1].bits.uop.bp_xcpt_if connect slots_5.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[5].wakeup_ports[1].bits.uop.bp_debug_if connect slots_5.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[5].wakeup_ports[1].bits.uop.xcpt_ma_if connect slots_5.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[5].wakeup_ports[1].bits.uop.xcpt_ae_if connect slots_5.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[5].wakeup_ports[1].bits.uop.xcpt_pf_if connect slots_5.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[5].wakeup_ports[1].bits.uop.fp_typ connect slots_5.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[5].wakeup_ports[1].bits.uop.fp_rm connect slots_5.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[5].wakeup_ports[1].bits.uop.fp_val connect slots_5.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[5].wakeup_ports[1].bits.uop.fcn_op connect slots_5.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[5].wakeup_ports[1].bits.uop.fcn_dw connect slots_5.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[5].wakeup_ports[1].bits.uop.frs3_en connect slots_5.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[5].wakeup_ports[1].bits.uop.lrs2_rtype connect slots_5.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[5].wakeup_ports[1].bits.uop.lrs1_rtype connect slots_5.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[5].wakeup_ports[1].bits.uop.dst_rtype connect slots_5.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[5].wakeup_ports[1].bits.uop.lrs3 connect slots_5.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[5].wakeup_ports[1].bits.uop.lrs2 connect slots_5.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[5].wakeup_ports[1].bits.uop.lrs1 connect slots_5.io.wakeup_ports[1].bits.uop.ldst, issue_slots[5].wakeup_ports[1].bits.uop.ldst connect slots_5.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[5].wakeup_ports[1].bits.uop.ldst_is_rs1 connect slots_5.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[5].wakeup_ports[1].bits.uop.csr_cmd connect slots_5.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[5].wakeup_ports[1].bits.uop.flush_on_commit connect slots_5.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[5].wakeup_ports[1].bits.uop.is_unique connect slots_5.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[5].wakeup_ports[1].bits.uop.uses_stq connect slots_5.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[5].wakeup_ports[1].bits.uop.uses_ldq connect slots_5.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[5].wakeup_ports[1].bits.uop.mem_signed connect slots_5.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[5].wakeup_ports[1].bits.uop.mem_size connect slots_5.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[5].wakeup_ports[1].bits.uop.mem_cmd connect slots_5.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[5].wakeup_ports[1].bits.uop.exc_cause connect slots_5.io.wakeup_ports[1].bits.uop.exception, issue_slots[5].wakeup_ports[1].bits.uop.exception connect slots_5.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[5].wakeup_ports[1].bits.uop.stale_pdst connect slots_5.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[5].wakeup_ports[1].bits.uop.ppred_busy connect slots_5.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[5].wakeup_ports[1].bits.uop.prs3_busy connect slots_5.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[5].wakeup_ports[1].bits.uop.prs2_busy connect slots_5.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[5].wakeup_ports[1].bits.uop.prs1_busy connect slots_5.io.wakeup_ports[1].bits.uop.ppred, issue_slots[5].wakeup_ports[1].bits.uop.ppred connect slots_5.io.wakeup_ports[1].bits.uop.prs3, issue_slots[5].wakeup_ports[1].bits.uop.prs3 connect slots_5.io.wakeup_ports[1].bits.uop.prs2, issue_slots[5].wakeup_ports[1].bits.uop.prs2 connect slots_5.io.wakeup_ports[1].bits.uop.prs1, issue_slots[5].wakeup_ports[1].bits.uop.prs1 connect slots_5.io.wakeup_ports[1].bits.uop.pdst, issue_slots[5].wakeup_ports[1].bits.uop.pdst connect slots_5.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[5].wakeup_ports[1].bits.uop.rxq_idx connect slots_5.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[5].wakeup_ports[1].bits.uop.stq_idx connect slots_5.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[5].wakeup_ports[1].bits.uop.ldq_idx connect slots_5.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[5].wakeup_ports[1].bits.uop.rob_idx connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.vec connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.wflags connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.div connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.fma connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.toint connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.fromint connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.wen connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.ldst connect slots_5.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[5].wakeup_ports[1].bits.uop.op2_sel connect slots_5.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[5].wakeup_ports[1].bits.uop.op1_sel connect slots_5.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[5].wakeup_ports[1].bits.uop.imm_packed connect slots_5.io.wakeup_ports[1].bits.uop.pimm, issue_slots[5].wakeup_ports[1].bits.uop.pimm connect slots_5.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[5].wakeup_ports[1].bits.uop.imm_sel connect slots_5.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[5].wakeup_ports[1].bits.uop.imm_rename connect slots_5.io.wakeup_ports[1].bits.uop.taken, issue_slots[5].wakeup_ports[1].bits.uop.taken connect slots_5.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[5].wakeup_ports[1].bits.uop.pc_lob connect slots_5.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[5].wakeup_ports[1].bits.uop.edge_inst connect slots_5.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[5].wakeup_ports[1].bits.uop.ftq_idx connect slots_5.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[5].wakeup_ports[1].bits.uop.is_mov connect slots_5.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[5].wakeup_ports[1].bits.uop.is_rocc connect slots_5.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[5].wakeup_ports[1].bits.uop.is_sys_pc2epc connect slots_5.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[5].wakeup_ports[1].bits.uop.is_eret connect slots_5.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[5].wakeup_ports[1].bits.uop.is_amo connect slots_5.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[5].wakeup_ports[1].bits.uop.is_sfence connect slots_5.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[5].wakeup_ports[1].bits.uop.is_fencei connect slots_5.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[5].wakeup_ports[1].bits.uop.is_fence connect slots_5.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[5].wakeup_ports[1].bits.uop.is_sfb connect slots_5.io.wakeup_ports[1].bits.uop.br_type, issue_slots[5].wakeup_ports[1].bits.uop.br_type connect slots_5.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[5].wakeup_ports[1].bits.uop.br_tag connect slots_5.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[5].wakeup_ports[1].bits.uop.br_mask connect slots_5.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[5].wakeup_ports[1].bits.uop.dis_col_sel connect slots_5.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[5].wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect slots_5.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[5].wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect slots_5.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[5].wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect slots_5.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[5].wakeup_ports[1].bits.uop.iw_p2_speculative_child connect slots_5.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[5].wakeup_ports[1].bits.uop.iw_p1_speculative_child connect slots_5.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[5].wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect slots_5.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[5].wakeup_ports[1].bits.uop.iw_issued_partial_agen connect slots_5.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[5].wakeup_ports[1].bits.uop.iw_issued connect slots_5.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[5].wakeup_ports[1].bits.uop.fu_code[0] connect slots_5.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[5].wakeup_ports[1].bits.uop.fu_code[1] connect slots_5.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[5].wakeup_ports[1].bits.uop.fu_code[2] connect slots_5.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[5].wakeup_ports[1].bits.uop.fu_code[3] connect slots_5.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[5].wakeup_ports[1].bits.uop.fu_code[4] connect slots_5.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[5].wakeup_ports[1].bits.uop.fu_code[5] connect slots_5.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[5].wakeup_ports[1].bits.uop.fu_code[6] connect slots_5.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[5].wakeup_ports[1].bits.uop.fu_code[7] connect slots_5.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[5].wakeup_ports[1].bits.uop.fu_code[8] connect slots_5.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[5].wakeup_ports[1].bits.uop.fu_code[9] connect slots_5.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[5].wakeup_ports[1].bits.uop.iq_type[0] connect slots_5.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[5].wakeup_ports[1].bits.uop.iq_type[1] connect slots_5.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[5].wakeup_ports[1].bits.uop.iq_type[2] connect slots_5.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[5].wakeup_ports[1].bits.uop.iq_type[3] connect slots_5.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[5].wakeup_ports[1].bits.uop.debug_pc connect slots_5.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[5].wakeup_ports[1].bits.uop.is_rvc connect slots_5.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[5].wakeup_ports[1].bits.uop.debug_inst connect slots_5.io.wakeup_ports[1].bits.uop.inst, issue_slots[5].wakeup_ports[1].bits.uop.inst connect slots_5.io.wakeup_ports[1].valid, issue_slots[5].wakeup_ports[1].valid connect slots_5.io.wakeup_ports[2].bits.rebusy, issue_slots[5].wakeup_ports[2].bits.rebusy connect slots_5.io.wakeup_ports[2].bits.speculative_mask, issue_slots[5].wakeup_ports[2].bits.speculative_mask connect slots_5.io.wakeup_ports[2].bits.bypassable, issue_slots[5].wakeup_ports[2].bits.bypassable connect slots_5.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[5].wakeup_ports[2].bits.uop.debug_tsrc connect slots_5.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[5].wakeup_ports[2].bits.uop.debug_fsrc connect slots_5.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[5].wakeup_ports[2].bits.uop.bp_xcpt_if connect slots_5.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[5].wakeup_ports[2].bits.uop.bp_debug_if connect slots_5.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[5].wakeup_ports[2].bits.uop.xcpt_ma_if connect slots_5.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[5].wakeup_ports[2].bits.uop.xcpt_ae_if connect slots_5.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[5].wakeup_ports[2].bits.uop.xcpt_pf_if connect slots_5.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[5].wakeup_ports[2].bits.uop.fp_typ connect slots_5.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[5].wakeup_ports[2].bits.uop.fp_rm connect slots_5.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[5].wakeup_ports[2].bits.uop.fp_val connect slots_5.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[5].wakeup_ports[2].bits.uop.fcn_op connect slots_5.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[5].wakeup_ports[2].bits.uop.fcn_dw connect slots_5.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[5].wakeup_ports[2].bits.uop.frs3_en connect slots_5.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[5].wakeup_ports[2].bits.uop.lrs2_rtype connect slots_5.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[5].wakeup_ports[2].bits.uop.lrs1_rtype connect slots_5.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[5].wakeup_ports[2].bits.uop.dst_rtype connect slots_5.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[5].wakeup_ports[2].bits.uop.lrs3 connect slots_5.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[5].wakeup_ports[2].bits.uop.lrs2 connect slots_5.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[5].wakeup_ports[2].bits.uop.lrs1 connect slots_5.io.wakeup_ports[2].bits.uop.ldst, issue_slots[5].wakeup_ports[2].bits.uop.ldst connect slots_5.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[5].wakeup_ports[2].bits.uop.ldst_is_rs1 connect slots_5.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[5].wakeup_ports[2].bits.uop.csr_cmd connect slots_5.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[5].wakeup_ports[2].bits.uop.flush_on_commit connect slots_5.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[5].wakeup_ports[2].bits.uop.is_unique connect slots_5.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[5].wakeup_ports[2].bits.uop.uses_stq connect slots_5.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[5].wakeup_ports[2].bits.uop.uses_ldq connect slots_5.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[5].wakeup_ports[2].bits.uop.mem_signed connect slots_5.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[5].wakeup_ports[2].bits.uop.mem_size connect slots_5.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[5].wakeup_ports[2].bits.uop.mem_cmd connect slots_5.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[5].wakeup_ports[2].bits.uop.exc_cause connect slots_5.io.wakeup_ports[2].bits.uop.exception, issue_slots[5].wakeup_ports[2].bits.uop.exception connect slots_5.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[5].wakeup_ports[2].bits.uop.stale_pdst connect slots_5.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[5].wakeup_ports[2].bits.uop.ppred_busy connect slots_5.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[5].wakeup_ports[2].bits.uop.prs3_busy connect slots_5.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[5].wakeup_ports[2].bits.uop.prs2_busy connect slots_5.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[5].wakeup_ports[2].bits.uop.prs1_busy connect slots_5.io.wakeup_ports[2].bits.uop.ppred, issue_slots[5].wakeup_ports[2].bits.uop.ppred connect slots_5.io.wakeup_ports[2].bits.uop.prs3, issue_slots[5].wakeup_ports[2].bits.uop.prs3 connect slots_5.io.wakeup_ports[2].bits.uop.prs2, issue_slots[5].wakeup_ports[2].bits.uop.prs2 connect slots_5.io.wakeup_ports[2].bits.uop.prs1, issue_slots[5].wakeup_ports[2].bits.uop.prs1 connect slots_5.io.wakeup_ports[2].bits.uop.pdst, issue_slots[5].wakeup_ports[2].bits.uop.pdst connect slots_5.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[5].wakeup_ports[2].bits.uop.rxq_idx connect slots_5.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[5].wakeup_ports[2].bits.uop.stq_idx connect slots_5.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[5].wakeup_ports[2].bits.uop.ldq_idx connect slots_5.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[5].wakeup_ports[2].bits.uop.rob_idx connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.vec connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.wflags connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.div connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.fma connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.toint connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.fromint connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.wen connect slots_5.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.ldst connect slots_5.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[5].wakeup_ports[2].bits.uop.op2_sel connect slots_5.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[5].wakeup_ports[2].bits.uop.op1_sel connect slots_5.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[5].wakeup_ports[2].bits.uop.imm_packed connect slots_5.io.wakeup_ports[2].bits.uop.pimm, issue_slots[5].wakeup_ports[2].bits.uop.pimm connect slots_5.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[5].wakeup_ports[2].bits.uop.imm_sel connect slots_5.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[5].wakeup_ports[2].bits.uop.imm_rename connect slots_5.io.wakeup_ports[2].bits.uop.taken, issue_slots[5].wakeup_ports[2].bits.uop.taken connect slots_5.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[5].wakeup_ports[2].bits.uop.pc_lob connect slots_5.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[5].wakeup_ports[2].bits.uop.edge_inst connect slots_5.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[5].wakeup_ports[2].bits.uop.ftq_idx connect slots_5.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[5].wakeup_ports[2].bits.uop.is_mov connect slots_5.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[5].wakeup_ports[2].bits.uop.is_rocc connect slots_5.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[5].wakeup_ports[2].bits.uop.is_sys_pc2epc connect slots_5.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[5].wakeup_ports[2].bits.uop.is_eret connect slots_5.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[5].wakeup_ports[2].bits.uop.is_amo connect slots_5.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[5].wakeup_ports[2].bits.uop.is_sfence connect slots_5.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[5].wakeup_ports[2].bits.uop.is_fencei connect slots_5.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[5].wakeup_ports[2].bits.uop.is_fence connect slots_5.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[5].wakeup_ports[2].bits.uop.is_sfb connect slots_5.io.wakeup_ports[2].bits.uop.br_type, issue_slots[5].wakeup_ports[2].bits.uop.br_type connect slots_5.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[5].wakeup_ports[2].bits.uop.br_tag connect slots_5.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[5].wakeup_ports[2].bits.uop.br_mask connect slots_5.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[5].wakeup_ports[2].bits.uop.dis_col_sel connect slots_5.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[5].wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect slots_5.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[5].wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect slots_5.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[5].wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect slots_5.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[5].wakeup_ports[2].bits.uop.iw_p2_speculative_child connect slots_5.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[5].wakeup_ports[2].bits.uop.iw_p1_speculative_child connect slots_5.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[5].wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect slots_5.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[5].wakeup_ports[2].bits.uop.iw_issued_partial_agen connect slots_5.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[5].wakeup_ports[2].bits.uop.iw_issued connect slots_5.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[5].wakeup_ports[2].bits.uop.fu_code[0] connect slots_5.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[5].wakeup_ports[2].bits.uop.fu_code[1] connect slots_5.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[5].wakeup_ports[2].bits.uop.fu_code[2] connect slots_5.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[5].wakeup_ports[2].bits.uop.fu_code[3] connect slots_5.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[5].wakeup_ports[2].bits.uop.fu_code[4] connect slots_5.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[5].wakeup_ports[2].bits.uop.fu_code[5] connect slots_5.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[5].wakeup_ports[2].bits.uop.fu_code[6] connect slots_5.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[5].wakeup_ports[2].bits.uop.fu_code[7] connect slots_5.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[5].wakeup_ports[2].bits.uop.fu_code[8] connect slots_5.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[5].wakeup_ports[2].bits.uop.fu_code[9] connect slots_5.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[5].wakeup_ports[2].bits.uop.iq_type[0] connect slots_5.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[5].wakeup_ports[2].bits.uop.iq_type[1] connect slots_5.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[5].wakeup_ports[2].bits.uop.iq_type[2] connect slots_5.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[5].wakeup_ports[2].bits.uop.iq_type[3] connect slots_5.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[5].wakeup_ports[2].bits.uop.debug_pc connect slots_5.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[5].wakeup_ports[2].bits.uop.is_rvc connect slots_5.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[5].wakeup_ports[2].bits.uop.debug_inst connect slots_5.io.wakeup_ports[2].bits.uop.inst, issue_slots[5].wakeup_ports[2].bits.uop.inst connect slots_5.io.wakeup_ports[2].valid, issue_slots[5].wakeup_ports[2].valid connect slots_5.io.wakeup_ports[3].bits.rebusy, issue_slots[5].wakeup_ports[3].bits.rebusy connect slots_5.io.wakeup_ports[3].bits.speculative_mask, issue_slots[5].wakeup_ports[3].bits.speculative_mask connect slots_5.io.wakeup_ports[3].bits.bypassable, issue_slots[5].wakeup_ports[3].bits.bypassable connect slots_5.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[5].wakeup_ports[3].bits.uop.debug_tsrc connect slots_5.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[5].wakeup_ports[3].bits.uop.debug_fsrc connect slots_5.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[5].wakeup_ports[3].bits.uop.bp_xcpt_if connect slots_5.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[5].wakeup_ports[3].bits.uop.bp_debug_if connect slots_5.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[5].wakeup_ports[3].bits.uop.xcpt_ma_if connect slots_5.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[5].wakeup_ports[3].bits.uop.xcpt_ae_if connect slots_5.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[5].wakeup_ports[3].bits.uop.xcpt_pf_if connect slots_5.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[5].wakeup_ports[3].bits.uop.fp_typ connect slots_5.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[5].wakeup_ports[3].bits.uop.fp_rm connect slots_5.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[5].wakeup_ports[3].bits.uop.fp_val connect slots_5.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[5].wakeup_ports[3].bits.uop.fcn_op connect slots_5.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[5].wakeup_ports[3].bits.uop.fcn_dw connect slots_5.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[5].wakeup_ports[3].bits.uop.frs3_en connect slots_5.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[5].wakeup_ports[3].bits.uop.lrs2_rtype connect slots_5.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[5].wakeup_ports[3].bits.uop.lrs1_rtype connect slots_5.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[5].wakeup_ports[3].bits.uop.dst_rtype connect slots_5.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[5].wakeup_ports[3].bits.uop.lrs3 connect slots_5.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[5].wakeup_ports[3].bits.uop.lrs2 connect slots_5.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[5].wakeup_ports[3].bits.uop.lrs1 connect slots_5.io.wakeup_ports[3].bits.uop.ldst, issue_slots[5].wakeup_ports[3].bits.uop.ldst connect slots_5.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[5].wakeup_ports[3].bits.uop.ldst_is_rs1 connect slots_5.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[5].wakeup_ports[3].bits.uop.csr_cmd connect slots_5.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[5].wakeup_ports[3].bits.uop.flush_on_commit connect slots_5.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[5].wakeup_ports[3].bits.uop.is_unique connect slots_5.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[5].wakeup_ports[3].bits.uop.uses_stq connect slots_5.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[5].wakeup_ports[3].bits.uop.uses_ldq connect slots_5.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[5].wakeup_ports[3].bits.uop.mem_signed connect slots_5.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[5].wakeup_ports[3].bits.uop.mem_size connect slots_5.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[5].wakeup_ports[3].bits.uop.mem_cmd connect slots_5.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[5].wakeup_ports[3].bits.uop.exc_cause connect slots_5.io.wakeup_ports[3].bits.uop.exception, issue_slots[5].wakeup_ports[3].bits.uop.exception connect slots_5.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[5].wakeup_ports[3].bits.uop.stale_pdst connect slots_5.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[5].wakeup_ports[3].bits.uop.ppred_busy connect slots_5.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[5].wakeup_ports[3].bits.uop.prs3_busy connect slots_5.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[5].wakeup_ports[3].bits.uop.prs2_busy connect slots_5.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[5].wakeup_ports[3].bits.uop.prs1_busy connect slots_5.io.wakeup_ports[3].bits.uop.ppred, issue_slots[5].wakeup_ports[3].bits.uop.ppred connect slots_5.io.wakeup_ports[3].bits.uop.prs3, issue_slots[5].wakeup_ports[3].bits.uop.prs3 connect slots_5.io.wakeup_ports[3].bits.uop.prs2, issue_slots[5].wakeup_ports[3].bits.uop.prs2 connect slots_5.io.wakeup_ports[3].bits.uop.prs1, issue_slots[5].wakeup_ports[3].bits.uop.prs1 connect slots_5.io.wakeup_ports[3].bits.uop.pdst, issue_slots[5].wakeup_ports[3].bits.uop.pdst connect slots_5.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[5].wakeup_ports[3].bits.uop.rxq_idx connect slots_5.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[5].wakeup_ports[3].bits.uop.stq_idx connect slots_5.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[5].wakeup_ports[3].bits.uop.ldq_idx connect slots_5.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[5].wakeup_ports[3].bits.uop.rob_idx connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.vec connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.wflags connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.div connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.fma connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.toint connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.fromint connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.wen connect slots_5.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.ldst connect slots_5.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[5].wakeup_ports[3].bits.uop.op2_sel connect slots_5.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[5].wakeup_ports[3].bits.uop.op1_sel connect slots_5.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[5].wakeup_ports[3].bits.uop.imm_packed connect slots_5.io.wakeup_ports[3].bits.uop.pimm, issue_slots[5].wakeup_ports[3].bits.uop.pimm connect slots_5.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[5].wakeup_ports[3].bits.uop.imm_sel connect slots_5.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[5].wakeup_ports[3].bits.uop.imm_rename connect slots_5.io.wakeup_ports[3].bits.uop.taken, issue_slots[5].wakeup_ports[3].bits.uop.taken connect slots_5.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[5].wakeup_ports[3].bits.uop.pc_lob connect slots_5.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[5].wakeup_ports[3].bits.uop.edge_inst connect slots_5.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[5].wakeup_ports[3].bits.uop.ftq_idx connect slots_5.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[5].wakeup_ports[3].bits.uop.is_mov connect slots_5.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[5].wakeup_ports[3].bits.uop.is_rocc connect slots_5.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[5].wakeup_ports[3].bits.uop.is_sys_pc2epc connect slots_5.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[5].wakeup_ports[3].bits.uop.is_eret connect slots_5.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[5].wakeup_ports[3].bits.uop.is_amo connect slots_5.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[5].wakeup_ports[3].bits.uop.is_sfence connect slots_5.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[5].wakeup_ports[3].bits.uop.is_fencei connect slots_5.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[5].wakeup_ports[3].bits.uop.is_fence connect slots_5.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[5].wakeup_ports[3].bits.uop.is_sfb connect slots_5.io.wakeup_ports[3].bits.uop.br_type, issue_slots[5].wakeup_ports[3].bits.uop.br_type connect slots_5.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[5].wakeup_ports[3].bits.uop.br_tag connect slots_5.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[5].wakeup_ports[3].bits.uop.br_mask connect slots_5.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[5].wakeup_ports[3].bits.uop.dis_col_sel connect slots_5.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[5].wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect slots_5.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[5].wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect slots_5.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[5].wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect slots_5.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[5].wakeup_ports[3].bits.uop.iw_p2_speculative_child connect slots_5.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[5].wakeup_ports[3].bits.uop.iw_p1_speculative_child connect slots_5.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[5].wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect slots_5.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[5].wakeup_ports[3].bits.uop.iw_issued_partial_agen connect slots_5.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[5].wakeup_ports[3].bits.uop.iw_issued connect slots_5.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[5].wakeup_ports[3].bits.uop.fu_code[0] connect slots_5.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[5].wakeup_ports[3].bits.uop.fu_code[1] connect slots_5.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[5].wakeup_ports[3].bits.uop.fu_code[2] connect slots_5.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[5].wakeup_ports[3].bits.uop.fu_code[3] connect slots_5.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[5].wakeup_ports[3].bits.uop.fu_code[4] connect slots_5.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[5].wakeup_ports[3].bits.uop.fu_code[5] connect slots_5.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[5].wakeup_ports[3].bits.uop.fu_code[6] connect slots_5.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[5].wakeup_ports[3].bits.uop.fu_code[7] connect slots_5.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[5].wakeup_ports[3].bits.uop.fu_code[8] connect slots_5.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[5].wakeup_ports[3].bits.uop.fu_code[9] connect slots_5.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[5].wakeup_ports[3].bits.uop.iq_type[0] connect slots_5.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[5].wakeup_ports[3].bits.uop.iq_type[1] connect slots_5.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[5].wakeup_ports[3].bits.uop.iq_type[2] connect slots_5.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[5].wakeup_ports[3].bits.uop.iq_type[3] connect slots_5.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[5].wakeup_ports[3].bits.uop.debug_pc connect slots_5.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[5].wakeup_ports[3].bits.uop.is_rvc connect slots_5.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[5].wakeup_ports[3].bits.uop.debug_inst connect slots_5.io.wakeup_ports[3].bits.uop.inst, issue_slots[5].wakeup_ports[3].bits.uop.inst connect slots_5.io.wakeup_ports[3].valid, issue_slots[5].wakeup_ports[3].valid connect slots_5.io.wakeup_ports[4].bits.rebusy, issue_slots[5].wakeup_ports[4].bits.rebusy connect slots_5.io.wakeup_ports[4].bits.speculative_mask, issue_slots[5].wakeup_ports[4].bits.speculative_mask connect slots_5.io.wakeup_ports[4].bits.bypassable, issue_slots[5].wakeup_ports[4].bits.bypassable connect slots_5.io.wakeup_ports[4].bits.uop.debug_tsrc, issue_slots[5].wakeup_ports[4].bits.uop.debug_tsrc connect slots_5.io.wakeup_ports[4].bits.uop.debug_fsrc, issue_slots[5].wakeup_ports[4].bits.uop.debug_fsrc connect slots_5.io.wakeup_ports[4].bits.uop.bp_xcpt_if, issue_slots[5].wakeup_ports[4].bits.uop.bp_xcpt_if connect slots_5.io.wakeup_ports[4].bits.uop.bp_debug_if, issue_slots[5].wakeup_ports[4].bits.uop.bp_debug_if connect slots_5.io.wakeup_ports[4].bits.uop.xcpt_ma_if, issue_slots[5].wakeup_ports[4].bits.uop.xcpt_ma_if connect slots_5.io.wakeup_ports[4].bits.uop.xcpt_ae_if, issue_slots[5].wakeup_ports[4].bits.uop.xcpt_ae_if connect slots_5.io.wakeup_ports[4].bits.uop.xcpt_pf_if, issue_slots[5].wakeup_ports[4].bits.uop.xcpt_pf_if connect slots_5.io.wakeup_ports[4].bits.uop.fp_typ, issue_slots[5].wakeup_ports[4].bits.uop.fp_typ connect slots_5.io.wakeup_ports[4].bits.uop.fp_rm, issue_slots[5].wakeup_ports[4].bits.uop.fp_rm connect slots_5.io.wakeup_ports[4].bits.uop.fp_val, issue_slots[5].wakeup_ports[4].bits.uop.fp_val connect slots_5.io.wakeup_ports[4].bits.uop.fcn_op, issue_slots[5].wakeup_ports[4].bits.uop.fcn_op connect slots_5.io.wakeup_ports[4].bits.uop.fcn_dw, issue_slots[5].wakeup_ports[4].bits.uop.fcn_dw connect slots_5.io.wakeup_ports[4].bits.uop.frs3_en, issue_slots[5].wakeup_ports[4].bits.uop.frs3_en connect slots_5.io.wakeup_ports[4].bits.uop.lrs2_rtype, issue_slots[5].wakeup_ports[4].bits.uop.lrs2_rtype connect slots_5.io.wakeup_ports[4].bits.uop.lrs1_rtype, issue_slots[5].wakeup_ports[4].bits.uop.lrs1_rtype connect slots_5.io.wakeup_ports[4].bits.uop.dst_rtype, issue_slots[5].wakeup_ports[4].bits.uop.dst_rtype connect slots_5.io.wakeup_ports[4].bits.uop.lrs3, issue_slots[5].wakeup_ports[4].bits.uop.lrs3 connect slots_5.io.wakeup_ports[4].bits.uop.lrs2, issue_slots[5].wakeup_ports[4].bits.uop.lrs2 connect slots_5.io.wakeup_ports[4].bits.uop.lrs1, issue_slots[5].wakeup_ports[4].bits.uop.lrs1 connect slots_5.io.wakeup_ports[4].bits.uop.ldst, issue_slots[5].wakeup_ports[4].bits.uop.ldst connect slots_5.io.wakeup_ports[4].bits.uop.ldst_is_rs1, issue_slots[5].wakeup_ports[4].bits.uop.ldst_is_rs1 connect slots_5.io.wakeup_ports[4].bits.uop.csr_cmd, issue_slots[5].wakeup_ports[4].bits.uop.csr_cmd connect slots_5.io.wakeup_ports[4].bits.uop.flush_on_commit, issue_slots[5].wakeup_ports[4].bits.uop.flush_on_commit connect slots_5.io.wakeup_ports[4].bits.uop.is_unique, issue_slots[5].wakeup_ports[4].bits.uop.is_unique connect slots_5.io.wakeup_ports[4].bits.uop.uses_stq, issue_slots[5].wakeup_ports[4].bits.uop.uses_stq connect slots_5.io.wakeup_ports[4].bits.uop.uses_ldq, issue_slots[5].wakeup_ports[4].bits.uop.uses_ldq connect slots_5.io.wakeup_ports[4].bits.uop.mem_signed, issue_slots[5].wakeup_ports[4].bits.uop.mem_signed connect slots_5.io.wakeup_ports[4].bits.uop.mem_size, issue_slots[5].wakeup_ports[4].bits.uop.mem_size connect slots_5.io.wakeup_ports[4].bits.uop.mem_cmd, issue_slots[5].wakeup_ports[4].bits.uop.mem_cmd connect slots_5.io.wakeup_ports[4].bits.uop.exc_cause, issue_slots[5].wakeup_ports[4].bits.uop.exc_cause connect slots_5.io.wakeup_ports[4].bits.uop.exception, issue_slots[5].wakeup_ports[4].bits.uop.exception connect slots_5.io.wakeup_ports[4].bits.uop.stale_pdst, issue_slots[5].wakeup_ports[4].bits.uop.stale_pdst connect slots_5.io.wakeup_ports[4].bits.uop.ppred_busy, issue_slots[5].wakeup_ports[4].bits.uop.ppred_busy connect slots_5.io.wakeup_ports[4].bits.uop.prs3_busy, issue_slots[5].wakeup_ports[4].bits.uop.prs3_busy connect slots_5.io.wakeup_ports[4].bits.uop.prs2_busy, issue_slots[5].wakeup_ports[4].bits.uop.prs2_busy connect slots_5.io.wakeup_ports[4].bits.uop.prs1_busy, issue_slots[5].wakeup_ports[4].bits.uop.prs1_busy connect slots_5.io.wakeup_ports[4].bits.uop.ppred, issue_slots[5].wakeup_ports[4].bits.uop.ppred connect slots_5.io.wakeup_ports[4].bits.uop.prs3, issue_slots[5].wakeup_ports[4].bits.uop.prs3 connect slots_5.io.wakeup_ports[4].bits.uop.prs2, issue_slots[5].wakeup_ports[4].bits.uop.prs2 connect slots_5.io.wakeup_ports[4].bits.uop.prs1, issue_slots[5].wakeup_ports[4].bits.uop.prs1 connect slots_5.io.wakeup_ports[4].bits.uop.pdst, issue_slots[5].wakeup_ports[4].bits.uop.pdst connect slots_5.io.wakeup_ports[4].bits.uop.rxq_idx, issue_slots[5].wakeup_ports[4].bits.uop.rxq_idx connect slots_5.io.wakeup_ports[4].bits.uop.stq_idx, issue_slots[5].wakeup_ports[4].bits.uop.stq_idx connect slots_5.io.wakeup_ports[4].bits.uop.ldq_idx, issue_slots[5].wakeup_ports[4].bits.uop.ldq_idx connect slots_5.io.wakeup_ports[4].bits.uop.rob_idx, issue_slots[5].wakeup_ports[4].bits.uop.rob_idx connect slots_5.io.wakeup_ports[4].bits.uop.fp_ctrl.vec, issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.vec connect slots_5.io.wakeup_ports[4].bits.uop.fp_ctrl.wflags, issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.wflags connect slots_5.io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt, issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect slots_5.io.wakeup_ports[4].bits.uop.fp_ctrl.div, issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.div connect slots_5.io.wakeup_ports[4].bits.uop.fp_ctrl.fma, issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.fma connect slots_5.io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect slots_5.io.wakeup_ports[4].bits.uop.fp_ctrl.toint, issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.toint connect slots_5.io.wakeup_ports[4].bits.uop.fp_ctrl.fromint, issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.fromint connect slots_5.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect slots_5.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect slots_5.io.wakeup_ports[4].bits.uop.fp_ctrl.swap23, issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect slots_5.io.wakeup_ports[4].bits.uop.fp_ctrl.swap12, issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect slots_5.io.wakeup_ports[4].bits.uop.fp_ctrl.ren3, issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect slots_5.io.wakeup_ports[4].bits.uop.fp_ctrl.ren2, issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect slots_5.io.wakeup_ports[4].bits.uop.fp_ctrl.ren1, issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect slots_5.io.wakeup_ports[4].bits.uop.fp_ctrl.wen, issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.wen connect slots_5.io.wakeup_ports[4].bits.uop.fp_ctrl.ldst, issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.ldst connect slots_5.io.wakeup_ports[4].bits.uop.op2_sel, issue_slots[5].wakeup_ports[4].bits.uop.op2_sel connect slots_5.io.wakeup_ports[4].bits.uop.op1_sel, issue_slots[5].wakeup_ports[4].bits.uop.op1_sel connect slots_5.io.wakeup_ports[4].bits.uop.imm_packed, issue_slots[5].wakeup_ports[4].bits.uop.imm_packed connect slots_5.io.wakeup_ports[4].bits.uop.pimm, issue_slots[5].wakeup_ports[4].bits.uop.pimm connect slots_5.io.wakeup_ports[4].bits.uop.imm_sel, issue_slots[5].wakeup_ports[4].bits.uop.imm_sel connect slots_5.io.wakeup_ports[4].bits.uop.imm_rename, issue_slots[5].wakeup_ports[4].bits.uop.imm_rename connect slots_5.io.wakeup_ports[4].bits.uop.taken, issue_slots[5].wakeup_ports[4].bits.uop.taken connect slots_5.io.wakeup_ports[4].bits.uop.pc_lob, issue_slots[5].wakeup_ports[4].bits.uop.pc_lob connect slots_5.io.wakeup_ports[4].bits.uop.edge_inst, issue_slots[5].wakeup_ports[4].bits.uop.edge_inst connect slots_5.io.wakeup_ports[4].bits.uop.ftq_idx, issue_slots[5].wakeup_ports[4].bits.uop.ftq_idx connect slots_5.io.wakeup_ports[4].bits.uop.is_mov, issue_slots[5].wakeup_ports[4].bits.uop.is_mov connect slots_5.io.wakeup_ports[4].bits.uop.is_rocc, issue_slots[5].wakeup_ports[4].bits.uop.is_rocc connect slots_5.io.wakeup_ports[4].bits.uop.is_sys_pc2epc, issue_slots[5].wakeup_ports[4].bits.uop.is_sys_pc2epc connect slots_5.io.wakeup_ports[4].bits.uop.is_eret, issue_slots[5].wakeup_ports[4].bits.uop.is_eret connect slots_5.io.wakeup_ports[4].bits.uop.is_amo, issue_slots[5].wakeup_ports[4].bits.uop.is_amo connect slots_5.io.wakeup_ports[4].bits.uop.is_sfence, issue_slots[5].wakeup_ports[4].bits.uop.is_sfence connect slots_5.io.wakeup_ports[4].bits.uop.is_fencei, issue_slots[5].wakeup_ports[4].bits.uop.is_fencei connect slots_5.io.wakeup_ports[4].bits.uop.is_fence, issue_slots[5].wakeup_ports[4].bits.uop.is_fence connect slots_5.io.wakeup_ports[4].bits.uop.is_sfb, issue_slots[5].wakeup_ports[4].bits.uop.is_sfb connect slots_5.io.wakeup_ports[4].bits.uop.br_type, issue_slots[5].wakeup_ports[4].bits.uop.br_type connect slots_5.io.wakeup_ports[4].bits.uop.br_tag, issue_slots[5].wakeup_ports[4].bits.uop.br_tag connect slots_5.io.wakeup_ports[4].bits.uop.br_mask, issue_slots[5].wakeup_ports[4].bits.uop.br_mask connect slots_5.io.wakeup_ports[4].bits.uop.dis_col_sel, issue_slots[5].wakeup_ports[4].bits.uop.dis_col_sel connect slots_5.io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint, issue_slots[5].wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect slots_5.io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint, issue_slots[5].wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect slots_5.io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint, issue_slots[5].wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect slots_5.io.wakeup_ports[4].bits.uop.iw_p2_speculative_child, issue_slots[5].wakeup_ports[4].bits.uop.iw_p2_speculative_child connect slots_5.io.wakeup_ports[4].bits.uop.iw_p1_speculative_child, issue_slots[5].wakeup_ports[4].bits.uop.iw_p1_speculative_child connect slots_5.io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen, issue_slots[5].wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect slots_5.io.wakeup_ports[4].bits.uop.iw_issued_partial_agen, issue_slots[5].wakeup_ports[4].bits.uop.iw_issued_partial_agen connect slots_5.io.wakeup_ports[4].bits.uop.iw_issued, issue_slots[5].wakeup_ports[4].bits.uop.iw_issued connect slots_5.io.wakeup_ports[4].bits.uop.fu_code[0], issue_slots[5].wakeup_ports[4].bits.uop.fu_code[0] connect slots_5.io.wakeup_ports[4].bits.uop.fu_code[1], issue_slots[5].wakeup_ports[4].bits.uop.fu_code[1] connect slots_5.io.wakeup_ports[4].bits.uop.fu_code[2], issue_slots[5].wakeup_ports[4].bits.uop.fu_code[2] connect slots_5.io.wakeup_ports[4].bits.uop.fu_code[3], issue_slots[5].wakeup_ports[4].bits.uop.fu_code[3] connect slots_5.io.wakeup_ports[4].bits.uop.fu_code[4], issue_slots[5].wakeup_ports[4].bits.uop.fu_code[4] connect slots_5.io.wakeup_ports[4].bits.uop.fu_code[5], issue_slots[5].wakeup_ports[4].bits.uop.fu_code[5] connect slots_5.io.wakeup_ports[4].bits.uop.fu_code[6], issue_slots[5].wakeup_ports[4].bits.uop.fu_code[6] connect slots_5.io.wakeup_ports[4].bits.uop.fu_code[7], issue_slots[5].wakeup_ports[4].bits.uop.fu_code[7] connect slots_5.io.wakeup_ports[4].bits.uop.fu_code[8], issue_slots[5].wakeup_ports[4].bits.uop.fu_code[8] connect slots_5.io.wakeup_ports[4].bits.uop.fu_code[9], issue_slots[5].wakeup_ports[4].bits.uop.fu_code[9] connect slots_5.io.wakeup_ports[4].bits.uop.iq_type[0], issue_slots[5].wakeup_ports[4].bits.uop.iq_type[0] connect slots_5.io.wakeup_ports[4].bits.uop.iq_type[1], issue_slots[5].wakeup_ports[4].bits.uop.iq_type[1] connect slots_5.io.wakeup_ports[4].bits.uop.iq_type[2], issue_slots[5].wakeup_ports[4].bits.uop.iq_type[2] connect slots_5.io.wakeup_ports[4].bits.uop.iq_type[3], issue_slots[5].wakeup_ports[4].bits.uop.iq_type[3] connect slots_5.io.wakeup_ports[4].bits.uop.debug_pc, issue_slots[5].wakeup_ports[4].bits.uop.debug_pc connect slots_5.io.wakeup_ports[4].bits.uop.is_rvc, issue_slots[5].wakeup_ports[4].bits.uop.is_rvc connect slots_5.io.wakeup_ports[4].bits.uop.debug_inst, issue_slots[5].wakeup_ports[4].bits.uop.debug_inst connect slots_5.io.wakeup_ports[4].bits.uop.inst, issue_slots[5].wakeup_ports[4].bits.uop.inst connect slots_5.io.wakeup_ports[4].valid, issue_slots[5].wakeup_ports[4].valid connect slots_5.io.squash_grant, issue_slots[5].squash_grant connect slots_5.io.clear, issue_slots[5].clear connect slots_5.io.kill, issue_slots[5].kill connect slots_5.io.brupdate.b2.target_offset, issue_slots[5].brupdate.b2.target_offset connect slots_5.io.brupdate.b2.jalr_target, issue_slots[5].brupdate.b2.jalr_target connect slots_5.io.brupdate.b2.pc_sel, issue_slots[5].brupdate.b2.pc_sel connect slots_5.io.brupdate.b2.cfi_type, issue_slots[5].brupdate.b2.cfi_type connect slots_5.io.brupdate.b2.taken, issue_slots[5].brupdate.b2.taken connect slots_5.io.brupdate.b2.mispredict, issue_slots[5].brupdate.b2.mispredict connect slots_5.io.brupdate.b2.uop.debug_tsrc, issue_slots[5].brupdate.b2.uop.debug_tsrc connect slots_5.io.brupdate.b2.uop.debug_fsrc, issue_slots[5].brupdate.b2.uop.debug_fsrc connect slots_5.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[5].brupdate.b2.uop.bp_xcpt_if connect slots_5.io.brupdate.b2.uop.bp_debug_if, issue_slots[5].brupdate.b2.uop.bp_debug_if connect slots_5.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[5].brupdate.b2.uop.xcpt_ma_if connect slots_5.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[5].brupdate.b2.uop.xcpt_ae_if connect slots_5.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[5].brupdate.b2.uop.xcpt_pf_if connect slots_5.io.brupdate.b2.uop.fp_typ, issue_slots[5].brupdate.b2.uop.fp_typ connect slots_5.io.brupdate.b2.uop.fp_rm, issue_slots[5].brupdate.b2.uop.fp_rm connect slots_5.io.brupdate.b2.uop.fp_val, issue_slots[5].brupdate.b2.uop.fp_val connect slots_5.io.brupdate.b2.uop.fcn_op, issue_slots[5].brupdate.b2.uop.fcn_op connect slots_5.io.brupdate.b2.uop.fcn_dw, issue_slots[5].brupdate.b2.uop.fcn_dw connect slots_5.io.brupdate.b2.uop.frs3_en, issue_slots[5].brupdate.b2.uop.frs3_en connect slots_5.io.brupdate.b2.uop.lrs2_rtype, issue_slots[5].brupdate.b2.uop.lrs2_rtype connect slots_5.io.brupdate.b2.uop.lrs1_rtype, issue_slots[5].brupdate.b2.uop.lrs1_rtype connect slots_5.io.brupdate.b2.uop.dst_rtype, issue_slots[5].brupdate.b2.uop.dst_rtype connect slots_5.io.brupdate.b2.uop.lrs3, issue_slots[5].brupdate.b2.uop.lrs3 connect slots_5.io.brupdate.b2.uop.lrs2, issue_slots[5].brupdate.b2.uop.lrs2 connect slots_5.io.brupdate.b2.uop.lrs1, issue_slots[5].brupdate.b2.uop.lrs1 connect slots_5.io.brupdate.b2.uop.ldst, issue_slots[5].brupdate.b2.uop.ldst connect slots_5.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[5].brupdate.b2.uop.ldst_is_rs1 connect slots_5.io.brupdate.b2.uop.csr_cmd, issue_slots[5].brupdate.b2.uop.csr_cmd connect slots_5.io.brupdate.b2.uop.flush_on_commit, issue_slots[5].brupdate.b2.uop.flush_on_commit connect slots_5.io.brupdate.b2.uop.is_unique, issue_slots[5].brupdate.b2.uop.is_unique connect slots_5.io.brupdate.b2.uop.uses_stq, issue_slots[5].brupdate.b2.uop.uses_stq connect slots_5.io.brupdate.b2.uop.uses_ldq, issue_slots[5].brupdate.b2.uop.uses_ldq connect slots_5.io.brupdate.b2.uop.mem_signed, issue_slots[5].brupdate.b2.uop.mem_signed connect slots_5.io.brupdate.b2.uop.mem_size, issue_slots[5].brupdate.b2.uop.mem_size connect slots_5.io.brupdate.b2.uop.mem_cmd, issue_slots[5].brupdate.b2.uop.mem_cmd connect slots_5.io.brupdate.b2.uop.exc_cause, issue_slots[5].brupdate.b2.uop.exc_cause connect slots_5.io.brupdate.b2.uop.exception, issue_slots[5].brupdate.b2.uop.exception connect slots_5.io.brupdate.b2.uop.stale_pdst, issue_slots[5].brupdate.b2.uop.stale_pdst connect slots_5.io.brupdate.b2.uop.ppred_busy, issue_slots[5].brupdate.b2.uop.ppred_busy connect slots_5.io.brupdate.b2.uop.prs3_busy, issue_slots[5].brupdate.b2.uop.prs3_busy connect slots_5.io.brupdate.b2.uop.prs2_busy, issue_slots[5].brupdate.b2.uop.prs2_busy connect slots_5.io.brupdate.b2.uop.prs1_busy, issue_slots[5].brupdate.b2.uop.prs1_busy connect slots_5.io.brupdate.b2.uop.ppred, issue_slots[5].brupdate.b2.uop.ppred connect slots_5.io.brupdate.b2.uop.prs3, issue_slots[5].brupdate.b2.uop.prs3 connect slots_5.io.brupdate.b2.uop.prs2, issue_slots[5].brupdate.b2.uop.prs2 connect slots_5.io.brupdate.b2.uop.prs1, issue_slots[5].brupdate.b2.uop.prs1 connect slots_5.io.brupdate.b2.uop.pdst, issue_slots[5].brupdate.b2.uop.pdst connect slots_5.io.brupdate.b2.uop.rxq_idx, issue_slots[5].brupdate.b2.uop.rxq_idx connect slots_5.io.brupdate.b2.uop.stq_idx, issue_slots[5].brupdate.b2.uop.stq_idx connect slots_5.io.brupdate.b2.uop.ldq_idx, issue_slots[5].brupdate.b2.uop.ldq_idx connect slots_5.io.brupdate.b2.uop.rob_idx, issue_slots[5].brupdate.b2.uop.rob_idx connect slots_5.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[5].brupdate.b2.uop.fp_ctrl.vec connect slots_5.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[5].brupdate.b2.uop.fp_ctrl.wflags connect slots_5.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[5].brupdate.b2.uop.fp_ctrl.sqrt connect slots_5.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[5].brupdate.b2.uop.fp_ctrl.div connect slots_5.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[5].brupdate.b2.uop.fp_ctrl.fma connect slots_5.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[5].brupdate.b2.uop.fp_ctrl.fastpipe connect slots_5.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[5].brupdate.b2.uop.fp_ctrl.toint connect slots_5.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[5].brupdate.b2.uop.fp_ctrl.fromint connect slots_5.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[5].brupdate.b2.uop.fp_ctrl.typeTagOut connect slots_5.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[5].brupdate.b2.uop.fp_ctrl.typeTagIn connect slots_5.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[5].brupdate.b2.uop.fp_ctrl.swap23 connect slots_5.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[5].brupdate.b2.uop.fp_ctrl.swap12 connect slots_5.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[5].brupdate.b2.uop.fp_ctrl.ren3 connect slots_5.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[5].brupdate.b2.uop.fp_ctrl.ren2 connect slots_5.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[5].brupdate.b2.uop.fp_ctrl.ren1 connect slots_5.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[5].brupdate.b2.uop.fp_ctrl.wen connect slots_5.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[5].brupdate.b2.uop.fp_ctrl.ldst connect slots_5.io.brupdate.b2.uop.op2_sel, issue_slots[5].brupdate.b2.uop.op2_sel connect slots_5.io.brupdate.b2.uop.op1_sel, issue_slots[5].brupdate.b2.uop.op1_sel connect slots_5.io.brupdate.b2.uop.imm_packed, issue_slots[5].brupdate.b2.uop.imm_packed connect slots_5.io.brupdate.b2.uop.pimm, issue_slots[5].brupdate.b2.uop.pimm connect slots_5.io.brupdate.b2.uop.imm_sel, issue_slots[5].brupdate.b2.uop.imm_sel connect slots_5.io.brupdate.b2.uop.imm_rename, issue_slots[5].brupdate.b2.uop.imm_rename connect slots_5.io.brupdate.b2.uop.taken, issue_slots[5].brupdate.b2.uop.taken connect slots_5.io.brupdate.b2.uop.pc_lob, issue_slots[5].brupdate.b2.uop.pc_lob connect slots_5.io.brupdate.b2.uop.edge_inst, issue_slots[5].brupdate.b2.uop.edge_inst connect slots_5.io.brupdate.b2.uop.ftq_idx, issue_slots[5].brupdate.b2.uop.ftq_idx connect slots_5.io.brupdate.b2.uop.is_mov, issue_slots[5].brupdate.b2.uop.is_mov connect slots_5.io.brupdate.b2.uop.is_rocc, issue_slots[5].brupdate.b2.uop.is_rocc connect slots_5.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[5].brupdate.b2.uop.is_sys_pc2epc connect slots_5.io.brupdate.b2.uop.is_eret, issue_slots[5].brupdate.b2.uop.is_eret connect slots_5.io.brupdate.b2.uop.is_amo, issue_slots[5].brupdate.b2.uop.is_amo connect slots_5.io.brupdate.b2.uop.is_sfence, issue_slots[5].brupdate.b2.uop.is_sfence connect slots_5.io.brupdate.b2.uop.is_fencei, issue_slots[5].brupdate.b2.uop.is_fencei connect slots_5.io.brupdate.b2.uop.is_fence, issue_slots[5].brupdate.b2.uop.is_fence connect slots_5.io.brupdate.b2.uop.is_sfb, issue_slots[5].brupdate.b2.uop.is_sfb connect slots_5.io.brupdate.b2.uop.br_type, issue_slots[5].brupdate.b2.uop.br_type connect slots_5.io.brupdate.b2.uop.br_tag, issue_slots[5].brupdate.b2.uop.br_tag connect slots_5.io.brupdate.b2.uop.br_mask, issue_slots[5].brupdate.b2.uop.br_mask connect slots_5.io.brupdate.b2.uop.dis_col_sel, issue_slots[5].brupdate.b2.uop.dis_col_sel connect slots_5.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[5].brupdate.b2.uop.iw_p3_bypass_hint connect slots_5.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[5].brupdate.b2.uop.iw_p2_bypass_hint connect slots_5.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[5].brupdate.b2.uop.iw_p1_bypass_hint connect slots_5.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[5].brupdate.b2.uop.iw_p2_speculative_child connect slots_5.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[5].brupdate.b2.uop.iw_p1_speculative_child connect slots_5.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[5].brupdate.b2.uop.iw_issued_partial_dgen connect slots_5.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[5].brupdate.b2.uop.iw_issued_partial_agen connect slots_5.io.brupdate.b2.uop.iw_issued, issue_slots[5].brupdate.b2.uop.iw_issued connect slots_5.io.brupdate.b2.uop.fu_code[0], issue_slots[5].brupdate.b2.uop.fu_code[0] connect slots_5.io.brupdate.b2.uop.fu_code[1], issue_slots[5].brupdate.b2.uop.fu_code[1] connect slots_5.io.brupdate.b2.uop.fu_code[2], issue_slots[5].brupdate.b2.uop.fu_code[2] connect slots_5.io.brupdate.b2.uop.fu_code[3], issue_slots[5].brupdate.b2.uop.fu_code[3] connect slots_5.io.brupdate.b2.uop.fu_code[4], issue_slots[5].brupdate.b2.uop.fu_code[4] connect slots_5.io.brupdate.b2.uop.fu_code[5], issue_slots[5].brupdate.b2.uop.fu_code[5] connect slots_5.io.brupdate.b2.uop.fu_code[6], issue_slots[5].brupdate.b2.uop.fu_code[6] connect slots_5.io.brupdate.b2.uop.fu_code[7], issue_slots[5].brupdate.b2.uop.fu_code[7] connect slots_5.io.brupdate.b2.uop.fu_code[8], issue_slots[5].brupdate.b2.uop.fu_code[8] connect slots_5.io.brupdate.b2.uop.fu_code[9], issue_slots[5].brupdate.b2.uop.fu_code[9] connect slots_5.io.brupdate.b2.uop.iq_type[0], issue_slots[5].brupdate.b2.uop.iq_type[0] connect slots_5.io.brupdate.b2.uop.iq_type[1], issue_slots[5].brupdate.b2.uop.iq_type[1] connect slots_5.io.brupdate.b2.uop.iq_type[2], issue_slots[5].brupdate.b2.uop.iq_type[2] connect slots_5.io.brupdate.b2.uop.iq_type[3], issue_slots[5].brupdate.b2.uop.iq_type[3] connect slots_5.io.brupdate.b2.uop.debug_pc, issue_slots[5].brupdate.b2.uop.debug_pc connect slots_5.io.brupdate.b2.uop.is_rvc, issue_slots[5].brupdate.b2.uop.is_rvc connect slots_5.io.brupdate.b2.uop.debug_inst, issue_slots[5].brupdate.b2.uop.debug_inst connect slots_5.io.brupdate.b2.uop.inst, issue_slots[5].brupdate.b2.uop.inst connect slots_5.io.brupdate.b1.mispredict_mask, issue_slots[5].brupdate.b1.mispredict_mask connect slots_5.io.brupdate.b1.resolve_mask, issue_slots[5].brupdate.b1.resolve_mask connect issue_slots[5].out_uop.debug_tsrc, slots_5.io.out_uop.debug_tsrc connect issue_slots[5].out_uop.debug_fsrc, slots_5.io.out_uop.debug_fsrc connect issue_slots[5].out_uop.bp_xcpt_if, slots_5.io.out_uop.bp_xcpt_if connect issue_slots[5].out_uop.bp_debug_if, slots_5.io.out_uop.bp_debug_if connect issue_slots[5].out_uop.xcpt_ma_if, slots_5.io.out_uop.xcpt_ma_if connect issue_slots[5].out_uop.xcpt_ae_if, slots_5.io.out_uop.xcpt_ae_if connect issue_slots[5].out_uop.xcpt_pf_if, slots_5.io.out_uop.xcpt_pf_if connect issue_slots[5].out_uop.fp_typ, slots_5.io.out_uop.fp_typ connect issue_slots[5].out_uop.fp_rm, slots_5.io.out_uop.fp_rm connect issue_slots[5].out_uop.fp_val, slots_5.io.out_uop.fp_val connect issue_slots[5].out_uop.fcn_op, slots_5.io.out_uop.fcn_op connect issue_slots[5].out_uop.fcn_dw, slots_5.io.out_uop.fcn_dw connect issue_slots[5].out_uop.frs3_en, slots_5.io.out_uop.frs3_en connect issue_slots[5].out_uop.lrs2_rtype, slots_5.io.out_uop.lrs2_rtype connect issue_slots[5].out_uop.lrs1_rtype, slots_5.io.out_uop.lrs1_rtype connect issue_slots[5].out_uop.dst_rtype, slots_5.io.out_uop.dst_rtype connect issue_slots[5].out_uop.lrs3, slots_5.io.out_uop.lrs3 connect issue_slots[5].out_uop.lrs2, slots_5.io.out_uop.lrs2 connect issue_slots[5].out_uop.lrs1, slots_5.io.out_uop.lrs1 connect issue_slots[5].out_uop.ldst, slots_5.io.out_uop.ldst connect issue_slots[5].out_uop.ldst_is_rs1, slots_5.io.out_uop.ldst_is_rs1 connect issue_slots[5].out_uop.csr_cmd, slots_5.io.out_uop.csr_cmd connect issue_slots[5].out_uop.flush_on_commit, slots_5.io.out_uop.flush_on_commit connect issue_slots[5].out_uop.is_unique, slots_5.io.out_uop.is_unique connect issue_slots[5].out_uop.uses_stq, slots_5.io.out_uop.uses_stq connect issue_slots[5].out_uop.uses_ldq, slots_5.io.out_uop.uses_ldq connect issue_slots[5].out_uop.mem_signed, slots_5.io.out_uop.mem_signed connect issue_slots[5].out_uop.mem_size, slots_5.io.out_uop.mem_size connect issue_slots[5].out_uop.mem_cmd, slots_5.io.out_uop.mem_cmd connect issue_slots[5].out_uop.exc_cause, slots_5.io.out_uop.exc_cause connect issue_slots[5].out_uop.exception, slots_5.io.out_uop.exception connect issue_slots[5].out_uop.stale_pdst, slots_5.io.out_uop.stale_pdst connect issue_slots[5].out_uop.ppred_busy, slots_5.io.out_uop.ppred_busy connect issue_slots[5].out_uop.prs3_busy, slots_5.io.out_uop.prs3_busy connect issue_slots[5].out_uop.prs2_busy, slots_5.io.out_uop.prs2_busy connect issue_slots[5].out_uop.prs1_busy, slots_5.io.out_uop.prs1_busy connect issue_slots[5].out_uop.ppred, slots_5.io.out_uop.ppred connect issue_slots[5].out_uop.prs3, slots_5.io.out_uop.prs3 connect issue_slots[5].out_uop.prs2, slots_5.io.out_uop.prs2 connect issue_slots[5].out_uop.prs1, slots_5.io.out_uop.prs1 connect issue_slots[5].out_uop.pdst, slots_5.io.out_uop.pdst connect issue_slots[5].out_uop.rxq_idx, slots_5.io.out_uop.rxq_idx connect issue_slots[5].out_uop.stq_idx, slots_5.io.out_uop.stq_idx connect issue_slots[5].out_uop.ldq_idx, slots_5.io.out_uop.ldq_idx connect issue_slots[5].out_uop.rob_idx, slots_5.io.out_uop.rob_idx connect issue_slots[5].out_uop.fp_ctrl.vec, slots_5.io.out_uop.fp_ctrl.vec connect issue_slots[5].out_uop.fp_ctrl.wflags, slots_5.io.out_uop.fp_ctrl.wflags connect issue_slots[5].out_uop.fp_ctrl.sqrt, slots_5.io.out_uop.fp_ctrl.sqrt connect issue_slots[5].out_uop.fp_ctrl.div, slots_5.io.out_uop.fp_ctrl.div connect issue_slots[5].out_uop.fp_ctrl.fma, slots_5.io.out_uop.fp_ctrl.fma connect issue_slots[5].out_uop.fp_ctrl.fastpipe, slots_5.io.out_uop.fp_ctrl.fastpipe connect issue_slots[5].out_uop.fp_ctrl.toint, slots_5.io.out_uop.fp_ctrl.toint connect issue_slots[5].out_uop.fp_ctrl.fromint, slots_5.io.out_uop.fp_ctrl.fromint connect issue_slots[5].out_uop.fp_ctrl.typeTagOut, slots_5.io.out_uop.fp_ctrl.typeTagOut connect issue_slots[5].out_uop.fp_ctrl.typeTagIn, slots_5.io.out_uop.fp_ctrl.typeTagIn connect issue_slots[5].out_uop.fp_ctrl.swap23, slots_5.io.out_uop.fp_ctrl.swap23 connect issue_slots[5].out_uop.fp_ctrl.swap12, slots_5.io.out_uop.fp_ctrl.swap12 connect issue_slots[5].out_uop.fp_ctrl.ren3, slots_5.io.out_uop.fp_ctrl.ren3 connect issue_slots[5].out_uop.fp_ctrl.ren2, slots_5.io.out_uop.fp_ctrl.ren2 connect issue_slots[5].out_uop.fp_ctrl.ren1, slots_5.io.out_uop.fp_ctrl.ren1 connect issue_slots[5].out_uop.fp_ctrl.wen, slots_5.io.out_uop.fp_ctrl.wen connect issue_slots[5].out_uop.fp_ctrl.ldst, slots_5.io.out_uop.fp_ctrl.ldst connect issue_slots[5].out_uop.op2_sel, slots_5.io.out_uop.op2_sel connect issue_slots[5].out_uop.op1_sel, slots_5.io.out_uop.op1_sel connect issue_slots[5].out_uop.imm_packed, slots_5.io.out_uop.imm_packed connect issue_slots[5].out_uop.pimm, slots_5.io.out_uop.pimm connect issue_slots[5].out_uop.imm_sel, slots_5.io.out_uop.imm_sel connect issue_slots[5].out_uop.imm_rename, slots_5.io.out_uop.imm_rename connect issue_slots[5].out_uop.taken, slots_5.io.out_uop.taken connect issue_slots[5].out_uop.pc_lob, slots_5.io.out_uop.pc_lob connect issue_slots[5].out_uop.edge_inst, slots_5.io.out_uop.edge_inst connect issue_slots[5].out_uop.ftq_idx, slots_5.io.out_uop.ftq_idx connect issue_slots[5].out_uop.is_mov, slots_5.io.out_uop.is_mov connect issue_slots[5].out_uop.is_rocc, slots_5.io.out_uop.is_rocc connect issue_slots[5].out_uop.is_sys_pc2epc, slots_5.io.out_uop.is_sys_pc2epc connect issue_slots[5].out_uop.is_eret, slots_5.io.out_uop.is_eret connect issue_slots[5].out_uop.is_amo, slots_5.io.out_uop.is_amo connect issue_slots[5].out_uop.is_sfence, slots_5.io.out_uop.is_sfence connect issue_slots[5].out_uop.is_fencei, slots_5.io.out_uop.is_fencei connect issue_slots[5].out_uop.is_fence, slots_5.io.out_uop.is_fence connect issue_slots[5].out_uop.is_sfb, slots_5.io.out_uop.is_sfb connect issue_slots[5].out_uop.br_type, slots_5.io.out_uop.br_type connect issue_slots[5].out_uop.br_tag, slots_5.io.out_uop.br_tag connect issue_slots[5].out_uop.br_mask, slots_5.io.out_uop.br_mask connect issue_slots[5].out_uop.dis_col_sel, slots_5.io.out_uop.dis_col_sel connect issue_slots[5].out_uop.iw_p3_bypass_hint, slots_5.io.out_uop.iw_p3_bypass_hint connect issue_slots[5].out_uop.iw_p2_bypass_hint, slots_5.io.out_uop.iw_p2_bypass_hint connect issue_slots[5].out_uop.iw_p1_bypass_hint, slots_5.io.out_uop.iw_p1_bypass_hint connect issue_slots[5].out_uop.iw_p2_speculative_child, slots_5.io.out_uop.iw_p2_speculative_child connect issue_slots[5].out_uop.iw_p1_speculative_child, slots_5.io.out_uop.iw_p1_speculative_child connect issue_slots[5].out_uop.iw_issued_partial_dgen, slots_5.io.out_uop.iw_issued_partial_dgen connect issue_slots[5].out_uop.iw_issued_partial_agen, slots_5.io.out_uop.iw_issued_partial_agen connect issue_slots[5].out_uop.iw_issued, slots_5.io.out_uop.iw_issued connect issue_slots[5].out_uop.fu_code[0], slots_5.io.out_uop.fu_code[0] connect issue_slots[5].out_uop.fu_code[1], slots_5.io.out_uop.fu_code[1] connect issue_slots[5].out_uop.fu_code[2], slots_5.io.out_uop.fu_code[2] connect issue_slots[5].out_uop.fu_code[3], slots_5.io.out_uop.fu_code[3] connect issue_slots[5].out_uop.fu_code[4], slots_5.io.out_uop.fu_code[4] connect issue_slots[5].out_uop.fu_code[5], slots_5.io.out_uop.fu_code[5] connect issue_slots[5].out_uop.fu_code[6], slots_5.io.out_uop.fu_code[6] connect issue_slots[5].out_uop.fu_code[7], slots_5.io.out_uop.fu_code[7] connect issue_slots[5].out_uop.fu_code[8], slots_5.io.out_uop.fu_code[8] connect issue_slots[5].out_uop.fu_code[9], slots_5.io.out_uop.fu_code[9] connect issue_slots[5].out_uop.iq_type[0], slots_5.io.out_uop.iq_type[0] connect issue_slots[5].out_uop.iq_type[1], slots_5.io.out_uop.iq_type[1] connect issue_slots[5].out_uop.iq_type[2], slots_5.io.out_uop.iq_type[2] connect issue_slots[5].out_uop.iq_type[3], slots_5.io.out_uop.iq_type[3] connect issue_slots[5].out_uop.debug_pc, slots_5.io.out_uop.debug_pc connect issue_slots[5].out_uop.is_rvc, slots_5.io.out_uop.is_rvc connect issue_slots[5].out_uop.debug_inst, slots_5.io.out_uop.debug_inst connect issue_slots[5].out_uop.inst, slots_5.io.out_uop.inst connect slots_5.io.in_uop.bits.debug_tsrc, issue_slots[5].in_uop.bits.debug_tsrc connect slots_5.io.in_uop.bits.debug_fsrc, issue_slots[5].in_uop.bits.debug_fsrc connect slots_5.io.in_uop.bits.bp_xcpt_if, issue_slots[5].in_uop.bits.bp_xcpt_if connect slots_5.io.in_uop.bits.bp_debug_if, issue_slots[5].in_uop.bits.bp_debug_if connect slots_5.io.in_uop.bits.xcpt_ma_if, issue_slots[5].in_uop.bits.xcpt_ma_if connect slots_5.io.in_uop.bits.xcpt_ae_if, issue_slots[5].in_uop.bits.xcpt_ae_if connect slots_5.io.in_uop.bits.xcpt_pf_if, issue_slots[5].in_uop.bits.xcpt_pf_if connect slots_5.io.in_uop.bits.fp_typ, issue_slots[5].in_uop.bits.fp_typ connect slots_5.io.in_uop.bits.fp_rm, issue_slots[5].in_uop.bits.fp_rm connect slots_5.io.in_uop.bits.fp_val, issue_slots[5].in_uop.bits.fp_val connect slots_5.io.in_uop.bits.fcn_op, issue_slots[5].in_uop.bits.fcn_op connect slots_5.io.in_uop.bits.fcn_dw, issue_slots[5].in_uop.bits.fcn_dw connect slots_5.io.in_uop.bits.frs3_en, issue_slots[5].in_uop.bits.frs3_en connect slots_5.io.in_uop.bits.lrs2_rtype, issue_slots[5].in_uop.bits.lrs2_rtype connect slots_5.io.in_uop.bits.lrs1_rtype, issue_slots[5].in_uop.bits.lrs1_rtype connect slots_5.io.in_uop.bits.dst_rtype, issue_slots[5].in_uop.bits.dst_rtype connect slots_5.io.in_uop.bits.lrs3, issue_slots[5].in_uop.bits.lrs3 connect slots_5.io.in_uop.bits.lrs2, issue_slots[5].in_uop.bits.lrs2 connect slots_5.io.in_uop.bits.lrs1, issue_slots[5].in_uop.bits.lrs1 connect slots_5.io.in_uop.bits.ldst, issue_slots[5].in_uop.bits.ldst connect slots_5.io.in_uop.bits.ldst_is_rs1, issue_slots[5].in_uop.bits.ldst_is_rs1 connect slots_5.io.in_uop.bits.csr_cmd, issue_slots[5].in_uop.bits.csr_cmd connect slots_5.io.in_uop.bits.flush_on_commit, issue_slots[5].in_uop.bits.flush_on_commit connect slots_5.io.in_uop.bits.is_unique, issue_slots[5].in_uop.bits.is_unique connect slots_5.io.in_uop.bits.uses_stq, issue_slots[5].in_uop.bits.uses_stq connect slots_5.io.in_uop.bits.uses_ldq, issue_slots[5].in_uop.bits.uses_ldq connect slots_5.io.in_uop.bits.mem_signed, issue_slots[5].in_uop.bits.mem_signed connect slots_5.io.in_uop.bits.mem_size, issue_slots[5].in_uop.bits.mem_size connect slots_5.io.in_uop.bits.mem_cmd, issue_slots[5].in_uop.bits.mem_cmd connect slots_5.io.in_uop.bits.exc_cause, issue_slots[5].in_uop.bits.exc_cause connect slots_5.io.in_uop.bits.exception, issue_slots[5].in_uop.bits.exception connect slots_5.io.in_uop.bits.stale_pdst, issue_slots[5].in_uop.bits.stale_pdst connect slots_5.io.in_uop.bits.ppred_busy, issue_slots[5].in_uop.bits.ppred_busy connect slots_5.io.in_uop.bits.prs3_busy, issue_slots[5].in_uop.bits.prs3_busy connect slots_5.io.in_uop.bits.prs2_busy, issue_slots[5].in_uop.bits.prs2_busy connect slots_5.io.in_uop.bits.prs1_busy, issue_slots[5].in_uop.bits.prs1_busy connect slots_5.io.in_uop.bits.ppred, issue_slots[5].in_uop.bits.ppred connect slots_5.io.in_uop.bits.prs3, issue_slots[5].in_uop.bits.prs3 connect slots_5.io.in_uop.bits.prs2, issue_slots[5].in_uop.bits.prs2 connect slots_5.io.in_uop.bits.prs1, issue_slots[5].in_uop.bits.prs1 connect slots_5.io.in_uop.bits.pdst, issue_slots[5].in_uop.bits.pdst connect slots_5.io.in_uop.bits.rxq_idx, issue_slots[5].in_uop.bits.rxq_idx connect slots_5.io.in_uop.bits.stq_idx, issue_slots[5].in_uop.bits.stq_idx connect slots_5.io.in_uop.bits.ldq_idx, issue_slots[5].in_uop.bits.ldq_idx connect slots_5.io.in_uop.bits.rob_idx, issue_slots[5].in_uop.bits.rob_idx connect slots_5.io.in_uop.bits.fp_ctrl.vec, issue_slots[5].in_uop.bits.fp_ctrl.vec connect slots_5.io.in_uop.bits.fp_ctrl.wflags, issue_slots[5].in_uop.bits.fp_ctrl.wflags connect slots_5.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[5].in_uop.bits.fp_ctrl.sqrt connect slots_5.io.in_uop.bits.fp_ctrl.div, issue_slots[5].in_uop.bits.fp_ctrl.div connect slots_5.io.in_uop.bits.fp_ctrl.fma, issue_slots[5].in_uop.bits.fp_ctrl.fma connect slots_5.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[5].in_uop.bits.fp_ctrl.fastpipe connect slots_5.io.in_uop.bits.fp_ctrl.toint, issue_slots[5].in_uop.bits.fp_ctrl.toint connect slots_5.io.in_uop.bits.fp_ctrl.fromint, issue_slots[5].in_uop.bits.fp_ctrl.fromint connect slots_5.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[5].in_uop.bits.fp_ctrl.typeTagOut connect slots_5.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[5].in_uop.bits.fp_ctrl.typeTagIn connect slots_5.io.in_uop.bits.fp_ctrl.swap23, issue_slots[5].in_uop.bits.fp_ctrl.swap23 connect slots_5.io.in_uop.bits.fp_ctrl.swap12, issue_slots[5].in_uop.bits.fp_ctrl.swap12 connect slots_5.io.in_uop.bits.fp_ctrl.ren3, issue_slots[5].in_uop.bits.fp_ctrl.ren3 connect slots_5.io.in_uop.bits.fp_ctrl.ren2, issue_slots[5].in_uop.bits.fp_ctrl.ren2 connect slots_5.io.in_uop.bits.fp_ctrl.ren1, issue_slots[5].in_uop.bits.fp_ctrl.ren1 connect slots_5.io.in_uop.bits.fp_ctrl.wen, issue_slots[5].in_uop.bits.fp_ctrl.wen connect slots_5.io.in_uop.bits.fp_ctrl.ldst, issue_slots[5].in_uop.bits.fp_ctrl.ldst connect slots_5.io.in_uop.bits.op2_sel, issue_slots[5].in_uop.bits.op2_sel connect slots_5.io.in_uop.bits.op1_sel, issue_slots[5].in_uop.bits.op1_sel connect slots_5.io.in_uop.bits.imm_packed, issue_slots[5].in_uop.bits.imm_packed connect slots_5.io.in_uop.bits.pimm, issue_slots[5].in_uop.bits.pimm connect slots_5.io.in_uop.bits.imm_sel, issue_slots[5].in_uop.bits.imm_sel connect slots_5.io.in_uop.bits.imm_rename, issue_slots[5].in_uop.bits.imm_rename connect slots_5.io.in_uop.bits.taken, issue_slots[5].in_uop.bits.taken connect slots_5.io.in_uop.bits.pc_lob, issue_slots[5].in_uop.bits.pc_lob connect slots_5.io.in_uop.bits.edge_inst, issue_slots[5].in_uop.bits.edge_inst connect slots_5.io.in_uop.bits.ftq_idx, issue_slots[5].in_uop.bits.ftq_idx connect slots_5.io.in_uop.bits.is_mov, issue_slots[5].in_uop.bits.is_mov connect slots_5.io.in_uop.bits.is_rocc, issue_slots[5].in_uop.bits.is_rocc connect slots_5.io.in_uop.bits.is_sys_pc2epc, issue_slots[5].in_uop.bits.is_sys_pc2epc connect slots_5.io.in_uop.bits.is_eret, issue_slots[5].in_uop.bits.is_eret connect slots_5.io.in_uop.bits.is_amo, issue_slots[5].in_uop.bits.is_amo connect slots_5.io.in_uop.bits.is_sfence, issue_slots[5].in_uop.bits.is_sfence connect slots_5.io.in_uop.bits.is_fencei, issue_slots[5].in_uop.bits.is_fencei connect slots_5.io.in_uop.bits.is_fence, issue_slots[5].in_uop.bits.is_fence connect slots_5.io.in_uop.bits.is_sfb, issue_slots[5].in_uop.bits.is_sfb connect slots_5.io.in_uop.bits.br_type, issue_slots[5].in_uop.bits.br_type connect slots_5.io.in_uop.bits.br_tag, issue_slots[5].in_uop.bits.br_tag connect slots_5.io.in_uop.bits.br_mask, issue_slots[5].in_uop.bits.br_mask connect slots_5.io.in_uop.bits.dis_col_sel, issue_slots[5].in_uop.bits.dis_col_sel connect slots_5.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[5].in_uop.bits.iw_p3_bypass_hint connect slots_5.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[5].in_uop.bits.iw_p2_bypass_hint connect slots_5.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[5].in_uop.bits.iw_p1_bypass_hint connect slots_5.io.in_uop.bits.iw_p2_speculative_child, issue_slots[5].in_uop.bits.iw_p2_speculative_child connect slots_5.io.in_uop.bits.iw_p1_speculative_child, issue_slots[5].in_uop.bits.iw_p1_speculative_child connect slots_5.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[5].in_uop.bits.iw_issued_partial_dgen connect slots_5.io.in_uop.bits.iw_issued_partial_agen, issue_slots[5].in_uop.bits.iw_issued_partial_agen connect slots_5.io.in_uop.bits.iw_issued, issue_slots[5].in_uop.bits.iw_issued connect slots_5.io.in_uop.bits.fu_code[0], issue_slots[5].in_uop.bits.fu_code[0] connect slots_5.io.in_uop.bits.fu_code[1], issue_slots[5].in_uop.bits.fu_code[1] connect slots_5.io.in_uop.bits.fu_code[2], issue_slots[5].in_uop.bits.fu_code[2] connect slots_5.io.in_uop.bits.fu_code[3], issue_slots[5].in_uop.bits.fu_code[3] connect slots_5.io.in_uop.bits.fu_code[4], issue_slots[5].in_uop.bits.fu_code[4] connect slots_5.io.in_uop.bits.fu_code[5], issue_slots[5].in_uop.bits.fu_code[5] connect slots_5.io.in_uop.bits.fu_code[6], issue_slots[5].in_uop.bits.fu_code[6] connect slots_5.io.in_uop.bits.fu_code[7], issue_slots[5].in_uop.bits.fu_code[7] connect slots_5.io.in_uop.bits.fu_code[8], issue_slots[5].in_uop.bits.fu_code[8] connect slots_5.io.in_uop.bits.fu_code[9], issue_slots[5].in_uop.bits.fu_code[9] connect slots_5.io.in_uop.bits.iq_type[0], issue_slots[5].in_uop.bits.iq_type[0] connect slots_5.io.in_uop.bits.iq_type[1], issue_slots[5].in_uop.bits.iq_type[1] connect slots_5.io.in_uop.bits.iq_type[2], issue_slots[5].in_uop.bits.iq_type[2] connect slots_5.io.in_uop.bits.iq_type[3], issue_slots[5].in_uop.bits.iq_type[3] connect slots_5.io.in_uop.bits.debug_pc, issue_slots[5].in_uop.bits.debug_pc connect slots_5.io.in_uop.bits.is_rvc, issue_slots[5].in_uop.bits.is_rvc connect slots_5.io.in_uop.bits.debug_inst, issue_slots[5].in_uop.bits.debug_inst connect slots_5.io.in_uop.bits.inst, issue_slots[5].in_uop.bits.inst connect slots_5.io.in_uop.valid, issue_slots[5].in_uop.valid connect issue_slots[5].iss_uop.debug_tsrc, slots_5.io.iss_uop.debug_tsrc connect issue_slots[5].iss_uop.debug_fsrc, slots_5.io.iss_uop.debug_fsrc connect issue_slots[5].iss_uop.bp_xcpt_if, slots_5.io.iss_uop.bp_xcpt_if connect issue_slots[5].iss_uop.bp_debug_if, slots_5.io.iss_uop.bp_debug_if connect issue_slots[5].iss_uop.xcpt_ma_if, slots_5.io.iss_uop.xcpt_ma_if connect issue_slots[5].iss_uop.xcpt_ae_if, slots_5.io.iss_uop.xcpt_ae_if connect issue_slots[5].iss_uop.xcpt_pf_if, slots_5.io.iss_uop.xcpt_pf_if connect issue_slots[5].iss_uop.fp_typ, slots_5.io.iss_uop.fp_typ connect issue_slots[5].iss_uop.fp_rm, slots_5.io.iss_uop.fp_rm connect issue_slots[5].iss_uop.fp_val, slots_5.io.iss_uop.fp_val connect issue_slots[5].iss_uop.fcn_op, slots_5.io.iss_uop.fcn_op connect issue_slots[5].iss_uop.fcn_dw, slots_5.io.iss_uop.fcn_dw connect issue_slots[5].iss_uop.frs3_en, slots_5.io.iss_uop.frs3_en connect issue_slots[5].iss_uop.lrs2_rtype, slots_5.io.iss_uop.lrs2_rtype connect issue_slots[5].iss_uop.lrs1_rtype, slots_5.io.iss_uop.lrs1_rtype connect issue_slots[5].iss_uop.dst_rtype, slots_5.io.iss_uop.dst_rtype connect issue_slots[5].iss_uop.lrs3, slots_5.io.iss_uop.lrs3 connect issue_slots[5].iss_uop.lrs2, slots_5.io.iss_uop.lrs2 connect issue_slots[5].iss_uop.lrs1, slots_5.io.iss_uop.lrs1 connect issue_slots[5].iss_uop.ldst, slots_5.io.iss_uop.ldst connect issue_slots[5].iss_uop.ldst_is_rs1, slots_5.io.iss_uop.ldst_is_rs1 connect issue_slots[5].iss_uop.csr_cmd, slots_5.io.iss_uop.csr_cmd connect issue_slots[5].iss_uop.flush_on_commit, slots_5.io.iss_uop.flush_on_commit connect issue_slots[5].iss_uop.is_unique, slots_5.io.iss_uop.is_unique connect issue_slots[5].iss_uop.uses_stq, slots_5.io.iss_uop.uses_stq connect issue_slots[5].iss_uop.uses_ldq, slots_5.io.iss_uop.uses_ldq connect issue_slots[5].iss_uop.mem_signed, slots_5.io.iss_uop.mem_signed connect issue_slots[5].iss_uop.mem_size, slots_5.io.iss_uop.mem_size connect issue_slots[5].iss_uop.mem_cmd, slots_5.io.iss_uop.mem_cmd connect issue_slots[5].iss_uop.exc_cause, slots_5.io.iss_uop.exc_cause connect issue_slots[5].iss_uop.exception, slots_5.io.iss_uop.exception connect issue_slots[5].iss_uop.stale_pdst, slots_5.io.iss_uop.stale_pdst connect issue_slots[5].iss_uop.ppred_busy, slots_5.io.iss_uop.ppred_busy connect issue_slots[5].iss_uop.prs3_busy, slots_5.io.iss_uop.prs3_busy connect issue_slots[5].iss_uop.prs2_busy, slots_5.io.iss_uop.prs2_busy connect issue_slots[5].iss_uop.prs1_busy, slots_5.io.iss_uop.prs1_busy connect issue_slots[5].iss_uop.ppred, slots_5.io.iss_uop.ppred connect issue_slots[5].iss_uop.prs3, slots_5.io.iss_uop.prs3 connect issue_slots[5].iss_uop.prs2, slots_5.io.iss_uop.prs2 connect issue_slots[5].iss_uop.prs1, slots_5.io.iss_uop.prs1 connect issue_slots[5].iss_uop.pdst, slots_5.io.iss_uop.pdst connect issue_slots[5].iss_uop.rxq_idx, slots_5.io.iss_uop.rxq_idx connect issue_slots[5].iss_uop.stq_idx, slots_5.io.iss_uop.stq_idx connect issue_slots[5].iss_uop.ldq_idx, slots_5.io.iss_uop.ldq_idx connect issue_slots[5].iss_uop.rob_idx, slots_5.io.iss_uop.rob_idx connect issue_slots[5].iss_uop.fp_ctrl.vec, slots_5.io.iss_uop.fp_ctrl.vec connect issue_slots[5].iss_uop.fp_ctrl.wflags, slots_5.io.iss_uop.fp_ctrl.wflags connect issue_slots[5].iss_uop.fp_ctrl.sqrt, slots_5.io.iss_uop.fp_ctrl.sqrt connect issue_slots[5].iss_uop.fp_ctrl.div, slots_5.io.iss_uop.fp_ctrl.div connect issue_slots[5].iss_uop.fp_ctrl.fma, slots_5.io.iss_uop.fp_ctrl.fma connect issue_slots[5].iss_uop.fp_ctrl.fastpipe, slots_5.io.iss_uop.fp_ctrl.fastpipe connect issue_slots[5].iss_uop.fp_ctrl.toint, slots_5.io.iss_uop.fp_ctrl.toint connect issue_slots[5].iss_uop.fp_ctrl.fromint, slots_5.io.iss_uop.fp_ctrl.fromint connect issue_slots[5].iss_uop.fp_ctrl.typeTagOut, slots_5.io.iss_uop.fp_ctrl.typeTagOut connect issue_slots[5].iss_uop.fp_ctrl.typeTagIn, slots_5.io.iss_uop.fp_ctrl.typeTagIn connect issue_slots[5].iss_uop.fp_ctrl.swap23, slots_5.io.iss_uop.fp_ctrl.swap23 connect issue_slots[5].iss_uop.fp_ctrl.swap12, slots_5.io.iss_uop.fp_ctrl.swap12 connect issue_slots[5].iss_uop.fp_ctrl.ren3, slots_5.io.iss_uop.fp_ctrl.ren3 connect issue_slots[5].iss_uop.fp_ctrl.ren2, slots_5.io.iss_uop.fp_ctrl.ren2 connect issue_slots[5].iss_uop.fp_ctrl.ren1, slots_5.io.iss_uop.fp_ctrl.ren1 connect issue_slots[5].iss_uop.fp_ctrl.wen, slots_5.io.iss_uop.fp_ctrl.wen connect issue_slots[5].iss_uop.fp_ctrl.ldst, slots_5.io.iss_uop.fp_ctrl.ldst connect issue_slots[5].iss_uop.op2_sel, slots_5.io.iss_uop.op2_sel connect issue_slots[5].iss_uop.op1_sel, slots_5.io.iss_uop.op1_sel connect issue_slots[5].iss_uop.imm_packed, slots_5.io.iss_uop.imm_packed connect issue_slots[5].iss_uop.pimm, slots_5.io.iss_uop.pimm connect issue_slots[5].iss_uop.imm_sel, slots_5.io.iss_uop.imm_sel connect issue_slots[5].iss_uop.imm_rename, slots_5.io.iss_uop.imm_rename connect issue_slots[5].iss_uop.taken, slots_5.io.iss_uop.taken connect issue_slots[5].iss_uop.pc_lob, slots_5.io.iss_uop.pc_lob connect issue_slots[5].iss_uop.edge_inst, slots_5.io.iss_uop.edge_inst connect issue_slots[5].iss_uop.ftq_idx, slots_5.io.iss_uop.ftq_idx connect issue_slots[5].iss_uop.is_mov, slots_5.io.iss_uop.is_mov connect issue_slots[5].iss_uop.is_rocc, slots_5.io.iss_uop.is_rocc connect issue_slots[5].iss_uop.is_sys_pc2epc, slots_5.io.iss_uop.is_sys_pc2epc connect issue_slots[5].iss_uop.is_eret, slots_5.io.iss_uop.is_eret connect issue_slots[5].iss_uop.is_amo, slots_5.io.iss_uop.is_amo connect issue_slots[5].iss_uop.is_sfence, slots_5.io.iss_uop.is_sfence connect issue_slots[5].iss_uop.is_fencei, slots_5.io.iss_uop.is_fencei connect issue_slots[5].iss_uop.is_fence, slots_5.io.iss_uop.is_fence connect issue_slots[5].iss_uop.is_sfb, slots_5.io.iss_uop.is_sfb connect issue_slots[5].iss_uop.br_type, slots_5.io.iss_uop.br_type connect issue_slots[5].iss_uop.br_tag, slots_5.io.iss_uop.br_tag connect issue_slots[5].iss_uop.br_mask, slots_5.io.iss_uop.br_mask connect issue_slots[5].iss_uop.dis_col_sel, slots_5.io.iss_uop.dis_col_sel connect issue_slots[5].iss_uop.iw_p3_bypass_hint, slots_5.io.iss_uop.iw_p3_bypass_hint connect issue_slots[5].iss_uop.iw_p2_bypass_hint, slots_5.io.iss_uop.iw_p2_bypass_hint connect issue_slots[5].iss_uop.iw_p1_bypass_hint, slots_5.io.iss_uop.iw_p1_bypass_hint connect issue_slots[5].iss_uop.iw_p2_speculative_child, slots_5.io.iss_uop.iw_p2_speculative_child connect issue_slots[5].iss_uop.iw_p1_speculative_child, slots_5.io.iss_uop.iw_p1_speculative_child connect issue_slots[5].iss_uop.iw_issued_partial_dgen, slots_5.io.iss_uop.iw_issued_partial_dgen connect issue_slots[5].iss_uop.iw_issued_partial_agen, slots_5.io.iss_uop.iw_issued_partial_agen connect issue_slots[5].iss_uop.iw_issued, slots_5.io.iss_uop.iw_issued connect issue_slots[5].iss_uop.fu_code[0], slots_5.io.iss_uop.fu_code[0] connect issue_slots[5].iss_uop.fu_code[1], slots_5.io.iss_uop.fu_code[1] connect issue_slots[5].iss_uop.fu_code[2], slots_5.io.iss_uop.fu_code[2] connect issue_slots[5].iss_uop.fu_code[3], slots_5.io.iss_uop.fu_code[3] connect issue_slots[5].iss_uop.fu_code[4], slots_5.io.iss_uop.fu_code[4] connect issue_slots[5].iss_uop.fu_code[5], slots_5.io.iss_uop.fu_code[5] connect issue_slots[5].iss_uop.fu_code[6], slots_5.io.iss_uop.fu_code[6] connect issue_slots[5].iss_uop.fu_code[7], slots_5.io.iss_uop.fu_code[7] connect issue_slots[5].iss_uop.fu_code[8], slots_5.io.iss_uop.fu_code[8] connect issue_slots[5].iss_uop.fu_code[9], slots_5.io.iss_uop.fu_code[9] connect issue_slots[5].iss_uop.iq_type[0], slots_5.io.iss_uop.iq_type[0] connect issue_slots[5].iss_uop.iq_type[1], slots_5.io.iss_uop.iq_type[1] connect issue_slots[5].iss_uop.iq_type[2], slots_5.io.iss_uop.iq_type[2] connect issue_slots[5].iss_uop.iq_type[3], slots_5.io.iss_uop.iq_type[3] connect issue_slots[5].iss_uop.debug_pc, slots_5.io.iss_uop.debug_pc connect issue_slots[5].iss_uop.is_rvc, slots_5.io.iss_uop.is_rvc connect issue_slots[5].iss_uop.debug_inst, slots_5.io.iss_uop.debug_inst connect issue_slots[5].iss_uop.inst, slots_5.io.iss_uop.inst connect slots_5.io.grant, issue_slots[5].grant connect issue_slots[5].request, slots_5.io.request connect issue_slots[5].will_be_valid, slots_5.io.will_be_valid connect issue_slots[5].valid, slots_5.io.valid connect slots_6.io.child_rebusys, issue_slots[6].child_rebusys connect slots_6.io.pred_wakeup_port.bits, issue_slots[6].pred_wakeup_port.bits connect slots_6.io.pred_wakeup_port.valid, issue_slots[6].pred_wakeup_port.valid connect slots_6.io.wakeup_ports[0].bits.rebusy, issue_slots[6].wakeup_ports[0].bits.rebusy connect slots_6.io.wakeup_ports[0].bits.speculative_mask, issue_slots[6].wakeup_ports[0].bits.speculative_mask connect slots_6.io.wakeup_ports[0].bits.bypassable, issue_slots[6].wakeup_ports[0].bits.bypassable connect slots_6.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[6].wakeup_ports[0].bits.uop.debug_tsrc connect slots_6.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[6].wakeup_ports[0].bits.uop.debug_fsrc connect slots_6.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[6].wakeup_ports[0].bits.uop.bp_xcpt_if connect slots_6.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[6].wakeup_ports[0].bits.uop.bp_debug_if connect slots_6.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[6].wakeup_ports[0].bits.uop.xcpt_ma_if connect slots_6.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[6].wakeup_ports[0].bits.uop.xcpt_ae_if connect slots_6.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[6].wakeup_ports[0].bits.uop.xcpt_pf_if connect slots_6.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[6].wakeup_ports[0].bits.uop.fp_typ connect slots_6.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[6].wakeup_ports[0].bits.uop.fp_rm connect slots_6.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[6].wakeup_ports[0].bits.uop.fp_val connect slots_6.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[6].wakeup_ports[0].bits.uop.fcn_op connect slots_6.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[6].wakeup_ports[0].bits.uop.fcn_dw connect slots_6.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[6].wakeup_ports[0].bits.uop.frs3_en connect slots_6.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[6].wakeup_ports[0].bits.uop.lrs2_rtype connect slots_6.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[6].wakeup_ports[0].bits.uop.lrs1_rtype connect slots_6.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[6].wakeup_ports[0].bits.uop.dst_rtype connect slots_6.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[6].wakeup_ports[0].bits.uop.lrs3 connect slots_6.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[6].wakeup_ports[0].bits.uop.lrs2 connect slots_6.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[6].wakeup_ports[0].bits.uop.lrs1 connect slots_6.io.wakeup_ports[0].bits.uop.ldst, issue_slots[6].wakeup_ports[0].bits.uop.ldst connect slots_6.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[6].wakeup_ports[0].bits.uop.ldst_is_rs1 connect slots_6.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[6].wakeup_ports[0].bits.uop.csr_cmd connect slots_6.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[6].wakeup_ports[0].bits.uop.flush_on_commit connect slots_6.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[6].wakeup_ports[0].bits.uop.is_unique connect slots_6.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[6].wakeup_ports[0].bits.uop.uses_stq connect slots_6.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[6].wakeup_ports[0].bits.uop.uses_ldq connect slots_6.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[6].wakeup_ports[0].bits.uop.mem_signed connect slots_6.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[6].wakeup_ports[0].bits.uop.mem_size connect slots_6.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[6].wakeup_ports[0].bits.uop.mem_cmd connect slots_6.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[6].wakeup_ports[0].bits.uop.exc_cause connect slots_6.io.wakeup_ports[0].bits.uop.exception, issue_slots[6].wakeup_ports[0].bits.uop.exception connect slots_6.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[6].wakeup_ports[0].bits.uop.stale_pdst connect slots_6.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[6].wakeup_ports[0].bits.uop.ppred_busy connect slots_6.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[6].wakeup_ports[0].bits.uop.prs3_busy connect slots_6.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[6].wakeup_ports[0].bits.uop.prs2_busy connect slots_6.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[6].wakeup_ports[0].bits.uop.prs1_busy connect slots_6.io.wakeup_ports[0].bits.uop.ppred, issue_slots[6].wakeup_ports[0].bits.uop.ppred connect slots_6.io.wakeup_ports[0].bits.uop.prs3, issue_slots[6].wakeup_ports[0].bits.uop.prs3 connect slots_6.io.wakeup_ports[0].bits.uop.prs2, issue_slots[6].wakeup_ports[0].bits.uop.prs2 connect slots_6.io.wakeup_ports[0].bits.uop.prs1, issue_slots[6].wakeup_ports[0].bits.uop.prs1 connect slots_6.io.wakeup_ports[0].bits.uop.pdst, issue_slots[6].wakeup_ports[0].bits.uop.pdst connect slots_6.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[6].wakeup_ports[0].bits.uop.rxq_idx connect slots_6.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[6].wakeup_ports[0].bits.uop.stq_idx connect slots_6.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[6].wakeup_ports[0].bits.uop.ldq_idx connect slots_6.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[6].wakeup_ports[0].bits.uop.rob_idx connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.vec connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.wflags connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.div connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.fma connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.toint connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.fromint connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.wen connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.ldst connect slots_6.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[6].wakeup_ports[0].bits.uop.op2_sel connect slots_6.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[6].wakeup_ports[0].bits.uop.op1_sel connect slots_6.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[6].wakeup_ports[0].bits.uop.imm_packed connect slots_6.io.wakeup_ports[0].bits.uop.pimm, issue_slots[6].wakeup_ports[0].bits.uop.pimm connect slots_6.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[6].wakeup_ports[0].bits.uop.imm_sel connect slots_6.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[6].wakeup_ports[0].bits.uop.imm_rename connect slots_6.io.wakeup_ports[0].bits.uop.taken, issue_slots[6].wakeup_ports[0].bits.uop.taken connect slots_6.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[6].wakeup_ports[0].bits.uop.pc_lob connect slots_6.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[6].wakeup_ports[0].bits.uop.edge_inst connect slots_6.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[6].wakeup_ports[0].bits.uop.ftq_idx connect slots_6.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[6].wakeup_ports[0].bits.uop.is_mov connect slots_6.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[6].wakeup_ports[0].bits.uop.is_rocc connect slots_6.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[6].wakeup_ports[0].bits.uop.is_sys_pc2epc connect slots_6.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[6].wakeup_ports[0].bits.uop.is_eret connect slots_6.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[6].wakeup_ports[0].bits.uop.is_amo connect slots_6.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[6].wakeup_ports[0].bits.uop.is_sfence connect slots_6.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[6].wakeup_ports[0].bits.uop.is_fencei connect slots_6.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[6].wakeup_ports[0].bits.uop.is_fence connect slots_6.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[6].wakeup_ports[0].bits.uop.is_sfb connect slots_6.io.wakeup_ports[0].bits.uop.br_type, issue_slots[6].wakeup_ports[0].bits.uop.br_type connect slots_6.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[6].wakeup_ports[0].bits.uop.br_tag connect slots_6.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[6].wakeup_ports[0].bits.uop.br_mask connect slots_6.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[6].wakeup_ports[0].bits.uop.dis_col_sel connect slots_6.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[6].wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect slots_6.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[6].wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect slots_6.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[6].wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect slots_6.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[6].wakeup_ports[0].bits.uop.iw_p2_speculative_child connect slots_6.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[6].wakeup_ports[0].bits.uop.iw_p1_speculative_child connect slots_6.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[6].wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect slots_6.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[6].wakeup_ports[0].bits.uop.iw_issued_partial_agen connect slots_6.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[6].wakeup_ports[0].bits.uop.iw_issued connect slots_6.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[6].wakeup_ports[0].bits.uop.fu_code[0] connect slots_6.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[6].wakeup_ports[0].bits.uop.fu_code[1] connect slots_6.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[6].wakeup_ports[0].bits.uop.fu_code[2] connect slots_6.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[6].wakeup_ports[0].bits.uop.fu_code[3] connect slots_6.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[6].wakeup_ports[0].bits.uop.fu_code[4] connect slots_6.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[6].wakeup_ports[0].bits.uop.fu_code[5] connect slots_6.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[6].wakeup_ports[0].bits.uop.fu_code[6] connect slots_6.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[6].wakeup_ports[0].bits.uop.fu_code[7] connect slots_6.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[6].wakeup_ports[0].bits.uop.fu_code[8] connect slots_6.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[6].wakeup_ports[0].bits.uop.fu_code[9] connect slots_6.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[6].wakeup_ports[0].bits.uop.iq_type[0] connect slots_6.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[6].wakeup_ports[0].bits.uop.iq_type[1] connect slots_6.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[6].wakeup_ports[0].bits.uop.iq_type[2] connect slots_6.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[6].wakeup_ports[0].bits.uop.iq_type[3] connect slots_6.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[6].wakeup_ports[0].bits.uop.debug_pc connect slots_6.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[6].wakeup_ports[0].bits.uop.is_rvc connect slots_6.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[6].wakeup_ports[0].bits.uop.debug_inst connect slots_6.io.wakeup_ports[0].bits.uop.inst, issue_slots[6].wakeup_ports[0].bits.uop.inst connect slots_6.io.wakeup_ports[0].valid, issue_slots[6].wakeup_ports[0].valid connect slots_6.io.wakeup_ports[1].bits.rebusy, issue_slots[6].wakeup_ports[1].bits.rebusy connect slots_6.io.wakeup_ports[1].bits.speculative_mask, issue_slots[6].wakeup_ports[1].bits.speculative_mask connect slots_6.io.wakeup_ports[1].bits.bypassable, issue_slots[6].wakeup_ports[1].bits.bypassable connect slots_6.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[6].wakeup_ports[1].bits.uop.debug_tsrc connect slots_6.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[6].wakeup_ports[1].bits.uop.debug_fsrc connect slots_6.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[6].wakeup_ports[1].bits.uop.bp_xcpt_if connect slots_6.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[6].wakeup_ports[1].bits.uop.bp_debug_if connect slots_6.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[6].wakeup_ports[1].bits.uop.xcpt_ma_if connect slots_6.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[6].wakeup_ports[1].bits.uop.xcpt_ae_if connect slots_6.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[6].wakeup_ports[1].bits.uop.xcpt_pf_if connect slots_6.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[6].wakeup_ports[1].bits.uop.fp_typ connect slots_6.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[6].wakeup_ports[1].bits.uop.fp_rm connect slots_6.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[6].wakeup_ports[1].bits.uop.fp_val connect slots_6.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[6].wakeup_ports[1].bits.uop.fcn_op connect slots_6.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[6].wakeup_ports[1].bits.uop.fcn_dw connect slots_6.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[6].wakeup_ports[1].bits.uop.frs3_en connect slots_6.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[6].wakeup_ports[1].bits.uop.lrs2_rtype connect slots_6.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[6].wakeup_ports[1].bits.uop.lrs1_rtype connect slots_6.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[6].wakeup_ports[1].bits.uop.dst_rtype connect slots_6.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[6].wakeup_ports[1].bits.uop.lrs3 connect slots_6.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[6].wakeup_ports[1].bits.uop.lrs2 connect slots_6.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[6].wakeup_ports[1].bits.uop.lrs1 connect slots_6.io.wakeup_ports[1].bits.uop.ldst, issue_slots[6].wakeup_ports[1].bits.uop.ldst connect slots_6.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[6].wakeup_ports[1].bits.uop.ldst_is_rs1 connect slots_6.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[6].wakeup_ports[1].bits.uop.csr_cmd connect slots_6.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[6].wakeup_ports[1].bits.uop.flush_on_commit connect slots_6.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[6].wakeup_ports[1].bits.uop.is_unique connect slots_6.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[6].wakeup_ports[1].bits.uop.uses_stq connect slots_6.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[6].wakeup_ports[1].bits.uop.uses_ldq connect slots_6.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[6].wakeup_ports[1].bits.uop.mem_signed connect slots_6.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[6].wakeup_ports[1].bits.uop.mem_size connect slots_6.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[6].wakeup_ports[1].bits.uop.mem_cmd connect slots_6.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[6].wakeup_ports[1].bits.uop.exc_cause connect slots_6.io.wakeup_ports[1].bits.uop.exception, issue_slots[6].wakeup_ports[1].bits.uop.exception connect slots_6.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[6].wakeup_ports[1].bits.uop.stale_pdst connect slots_6.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[6].wakeup_ports[1].bits.uop.ppred_busy connect slots_6.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[6].wakeup_ports[1].bits.uop.prs3_busy connect slots_6.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[6].wakeup_ports[1].bits.uop.prs2_busy connect slots_6.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[6].wakeup_ports[1].bits.uop.prs1_busy connect slots_6.io.wakeup_ports[1].bits.uop.ppred, issue_slots[6].wakeup_ports[1].bits.uop.ppred connect slots_6.io.wakeup_ports[1].bits.uop.prs3, issue_slots[6].wakeup_ports[1].bits.uop.prs3 connect slots_6.io.wakeup_ports[1].bits.uop.prs2, issue_slots[6].wakeup_ports[1].bits.uop.prs2 connect slots_6.io.wakeup_ports[1].bits.uop.prs1, issue_slots[6].wakeup_ports[1].bits.uop.prs1 connect slots_6.io.wakeup_ports[1].bits.uop.pdst, issue_slots[6].wakeup_ports[1].bits.uop.pdst connect slots_6.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[6].wakeup_ports[1].bits.uop.rxq_idx connect slots_6.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[6].wakeup_ports[1].bits.uop.stq_idx connect slots_6.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[6].wakeup_ports[1].bits.uop.ldq_idx connect slots_6.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[6].wakeup_ports[1].bits.uop.rob_idx connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.vec connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.wflags connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.div connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.fma connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.toint connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.fromint connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.wen connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.ldst connect slots_6.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[6].wakeup_ports[1].bits.uop.op2_sel connect slots_6.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[6].wakeup_ports[1].bits.uop.op1_sel connect slots_6.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[6].wakeup_ports[1].bits.uop.imm_packed connect slots_6.io.wakeup_ports[1].bits.uop.pimm, issue_slots[6].wakeup_ports[1].bits.uop.pimm connect slots_6.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[6].wakeup_ports[1].bits.uop.imm_sel connect slots_6.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[6].wakeup_ports[1].bits.uop.imm_rename connect slots_6.io.wakeup_ports[1].bits.uop.taken, issue_slots[6].wakeup_ports[1].bits.uop.taken connect slots_6.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[6].wakeup_ports[1].bits.uop.pc_lob connect slots_6.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[6].wakeup_ports[1].bits.uop.edge_inst connect slots_6.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[6].wakeup_ports[1].bits.uop.ftq_idx connect slots_6.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[6].wakeup_ports[1].bits.uop.is_mov connect slots_6.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[6].wakeup_ports[1].bits.uop.is_rocc connect slots_6.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[6].wakeup_ports[1].bits.uop.is_sys_pc2epc connect slots_6.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[6].wakeup_ports[1].bits.uop.is_eret connect slots_6.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[6].wakeup_ports[1].bits.uop.is_amo connect slots_6.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[6].wakeup_ports[1].bits.uop.is_sfence connect slots_6.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[6].wakeup_ports[1].bits.uop.is_fencei connect slots_6.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[6].wakeup_ports[1].bits.uop.is_fence connect slots_6.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[6].wakeup_ports[1].bits.uop.is_sfb connect slots_6.io.wakeup_ports[1].bits.uop.br_type, issue_slots[6].wakeup_ports[1].bits.uop.br_type connect slots_6.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[6].wakeup_ports[1].bits.uop.br_tag connect slots_6.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[6].wakeup_ports[1].bits.uop.br_mask connect slots_6.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[6].wakeup_ports[1].bits.uop.dis_col_sel connect slots_6.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[6].wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect slots_6.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[6].wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect slots_6.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[6].wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect slots_6.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[6].wakeup_ports[1].bits.uop.iw_p2_speculative_child connect slots_6.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[6].wakeup_ports[1].bits.uop.iw_p1_speculative_child connect slots_6.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[6].wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect slots_6.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[6].wakeup_ports[1].bits.uop.iw_issued_partial_agen connect slots_6.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[6].wakeup_ports[1].bits.uop.iw_issued connect slots_6.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[6].wakeup_ports[1].bits.uop.fu_code[0] connect slots_6.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[6].wakeup_ports[1].bits.uop.fu_code[1] connect slots_6.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[6].wakeup_ports[1].bits.uop.fu_code[2] connect slots_6.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[6].wakeup_ports[1].bits.uop.fu_code[3] connect slots_6.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[6].wakeup_ports[1].bits.uop.fu_code[4] connect slots_6.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[6].wakeup_ports[1].bits.uop.fu_code[5] connect slots_6.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[6].wakeup_ports[1].bits.uop.fu_code[6] connect slots_6.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[6].wakeup_ports[1].bits.uop.fu_code[7] connect slots_6.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[6].wakeup_ports[1].bits.uop.fu_code[8] connect slots_6.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[6].wakeup_ports[1].bits.uop.fu_code[9] connect slots_6.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[6].wakeup_ports[1].bits.uop.iq_type[0] connect slots_6.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[6].wakeup_ports[1].bits.uop.iq_type[1] connect slots_6.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[6].wakeup_ports[1].bits.uop.iq_type[2] connect slots_6.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[6].wakeup_ports[1].bits.uop.iq_type[3] connect slots_6.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[6].wakeup_ports[1].bits.uop.debug_pc connect slots_6.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[6].wakeup_ports[1].bits.uop.is_rvc connect slots_6.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[6].wakeup_ports[1].bits.uop.debug_inst connect slots_6.io.wakeup_ports[1].bits.uop.inst, issue_slots[6].wakeup_ports[1].bits.uop.inst connect slots_6.io.wakeup_ports[1].valid, issue_slots[6].wakeup_ports[1].valid connect slots_6.io.wakeup_ports[2].bits.rebusy, issue_slots[6].wakeup_ports[2].bits.rebusy connect slots_6.io.wakeup_ports[2].bits.speculative_mask, issue_slots[6].wakeup_ports[2].bits.speculative_mask connect slots_6.io.wakeup_ports[2].bits.bypassable, issue_slots[6].wakeup_ports[2].bits.bypassable connect slots_6.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[6].wakeup_ports[2].bits.uop.debug_tsrc connect slots_6.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[6].wakeup_ports[2].bits.uop.debug_fsrc connect slots_6.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[6].wakeup_ports[2].bits.uop.bp_xcpt_if connect slots_6.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[6].wakeup_ports[2].bits.uop.bp_debug_if connect slots_6.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[6].wakeup_ports[2].bits.uop.xcpt_ma_if connect slots_6.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[6].wakeup_ports[2].bits.uop.xcpt_ae_if connect slots_6.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[6].wakeup_ports[2].bits.uop.xcpt_pf_if connect slots_6.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[6].wakeup_ports[2].bits.uop.fp_typ connect slots_6.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[6].wakeup_ports[2].bits.uop.fp_rm connect slots_6.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[6].wakeup_ports[2].bits.uop.fp_val connect slots_6.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[6].wakeup_ports[2].bits.uop.fcn_op connect slots_6.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[6].wakeup_ports[2].bits.uop.fcn_dw connect slots_6.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[6].wakeup_ports[2].bits.uop.frs3_en connect slots_6.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[6].wakeup_ports[2].bits.uop.lrs2_rtype connect slots_6.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[6].wakeup_ports[2].bits.uop.lrs1_rtype connect slots_6.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[6].wakeup_ports[2].bits.uop.dst_rtype connect slots_6.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[6].wakeup_ports[2].bits.uop.lrs3 connect slots_6.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[6].wakeup_ports[2].bits.uop.lrs2 connect slots_6.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[6].wakeup_ports[2].bits.uop.lrs1 connect slots_6.io.wakeup_ports[2].bits.uop.ldst, issue_slots[6].wakeup_ports[2].bits.uop.ldst connect slots_6.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[6].wakeup_ports[2].bits.uop.ldst_is_rs1 connect slots_6.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[6].wakeup_ports[2].bits.uop.csr_cmd connect slots_6.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[6].wakeup_ports[2].bits.uop.flush_on_commit connect slots_6.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[6].wakeup_ports[2].bits.uop.is_unique connect slots_6.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[6].wakeup_ports[2].bits.uop.uses_stq connect slots_6.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[6].wakeup_ports[2].bits.uop.uses_ldq connect slots_6.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[6].wakeup_ports[2].bits.uop.mem_signed connect slots_6.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[6].wakeup_ports[2].bits.uop.mem_size connect slots_6.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[6].wakeup_ports[2].bits.uop.mem_cmd connect slots_6.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[6].wakeup_ports[2].bits.uop.exc_cause connect slots_6.io.wakeup_ports[2].bits.uop.exception, issue_slots[6].wakeup_ports[2].bits.uop.exception connect slots_6.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[6].wakeup_ports[2].bits.uop.stale_pdst connect slots_6.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[6].wakeup_ports[2].bits.uop.ppred_busy connect slots_6.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[6].wakeup_ports[2].bits.uop.prs3_busy connect slots_6.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[6].wakeup_ports[2].bits.uop.prs2_busy connect slots_6.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[6].wakeup_ports[2].bits.uop.prs1_busy connect slots_6.io.wakeup_ports[2].bits.uop.ppred, issue_slots[6].wakeup_ports[2].bits.uop.ppred connect slots_6.io.wakeup_ports[2].bits.uop.prs3, issue_slots[6].wakeup_ports[2].bits.uop.prs3 connect slots_6.io.wakeup_ports[2].bits.uop.prs2, issue_slots[6].wakeup_ports[2].bits.uop.prs2 connect slots_6.io.wakeup_ports[2].bits.uop.prs1, issue_slots[6].wakeup_ports[2].bits.uop.prs1 connect slots_6.io.wakeup_ports[2].bits.uop.pdst, issue_slots[6].wakeup_ports[2].bits.uop.pdst connect slots_6.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[6].wakeup_ports[2].bits.uop.rxq_idx connect slots_6.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[6].wakeup_ports[2].bits.uop.stq_idx connect slots_6.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[6].wakeup_ports[2].bits.uop.ldq_idx connect slots_6.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[6].wakeup_ports[2].bits.uop.rob_idx connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.vec connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.wflags connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.div connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.fma connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.toint connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.fromint connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.wen connect slots_6.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.ldst connect slots_6.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[6].wakeup_ports[2].bits.uop.op2_sel connect slots_6.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[6].wakeup_ports[2].bits.uop.op1_sel connect slots_6.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[6].wakeup_ports[2].bits.uop.imm_packed connect slots_6.io.wakeup_ports[2].bits.uop.pimm, issue_slots[6].wakeup_ports[2].bits.uop.pimm connect slots_6.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[6].wakeup_ports[2].bits.uop.imm_sel connect slots_6.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[6].wakeup_ports[2].bits.uop.imm_rename connect slots_6.io.wakeup_ports[2].bits.uop.taken, issue_slots[6].wakeup_ports[2].bits.uop.taken connect slots_6.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[6].wakeup_ports[2].bits.uop.pc_lob connect slots_6.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[6].wakeup_ports[2].bits.uop.edge_inst connect slots_6.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[6].wakeup_ports[2].bits.uop.ftq_idx connect slots_6.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[6].wakeup_ports[2].bits.uop.is_mov connect slots_6.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[6].wakeup_ports[2].bits.uop.is_rocc connect slots_6.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[6].wakeup_ports[2].bits.uop.is_sys_pc2epc connect slots_6.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[6].wakeup_ports[2].bits.uop.is_eret connect slots_6.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[6].wakeup_ports[2].bits.uop.is_amo connect slots_6.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[6].wakeup_ports[2].bits.uop.is_sfence connect slots_6.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[6].wakeup_ports[2].bits.uop.is_fencei connect slots_6.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[6].wakeup_ports[2].bits.uop.is_fence connect slots_6.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[6].wakeup_ports[2].bits.uop.is_sfb connect slots_6.io.wakeup_ports[2].bits.uop.br_type, issue_slots[6].wakeup_ports[2].bits.uop.br_type connect slots_6.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[6].wakeup_ports[2].bits.uop.br_tag connect slots_6.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[6].wakeup_ports[2].bits.uop.br_mask connect slots_6.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[6].wakeup_ports[2].bits.uop.dis_col_sel connect slots_6.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[6].wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect slots_6.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[6].wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect slots_6.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[6].wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect slots_6.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[6].wakeup_ports[2].bits.uop.iw_p2_speculative_child connect slots_6.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[6].wakeup_ports[2].bits.uop.iw_p1_speculative_child connect slots_6.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[6].wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect slots_6.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[6].wakeup_ports[2].bits.uop.iw_issued_partial_agen connect slots_6.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[6].wakeup_ports[2].bits.uop.iw_issued connect slots_6.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[6].wakeup_ports[2].bits.uop.fu_code[0] connect slots_6.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[6].wakeup_ports[2].bits.uop.fu_code[1] connect slots_6.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[6].wakeup_ports[2].bits.uop.fu_code[2] connect slots_6.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[6].wakeup_ports[2].bits.uop.fu_code[3] connect slots_6.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[6].wakeup_ports[2].bits.uop.fu_code[4] connect slots_6.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[6].wakeup_ports[2].bits.uop.fu_code[5] connect slots_6.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[6].wakeup_ports[2].bits.uop.fu_code[6] connect slots_6.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[6].wakeup_ports[2].bits.uop.fu_code[7] connect slots_6.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[6].wakeup_ports[2].bits.uop.fu_code[8] connect slots_6.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[6].wakeup_ports[2].bits.uop.fu_code[9] connect slots_6.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[6].wakeup_ports[2].bits.uop.iq_type[0] connect slots_6.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[6].wakeup_ports[2].bits.uop.iq_type[1] connect slots_6.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[6].wakeup_ports[2].bits.uop.iq_type[2] connect slots_6.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[6].wakeup_ports[2].bits.uop.iq_type[3] connect slots_6.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[6].wakeup_ports[2].bits.uop.debug_pc connect slots_6.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[6].wakeup_ports[2].bits.uop.is_rvc connect slots_6.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[6].wakeup_ports[2].bits.uop.debug_inst connect slots_6.io.wakeup_ports[2].bits.uop.inst, issue_slots[6].wakeup_ports[2].bits.uop.inst connect slots_6.io.wakeup_ports[2].valid, issue_slots[6].wakeup_ports[2].valid connect slots_6.io.wakeup_ports[3].bits.rebusy, issue_slots[6].wakeup_ports[3].bits.rebusy connect slots_6.io.wakeup_ports[3].bits.speculative_mask, issue_slots[6].wakeup_ports[3].bits.speculative_mask connect slots_6.io.wakeup_ports[3].bits.bypassable, issue_slots[6].wakeup_ports[3].bits.bypassable connect slots_6.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[6].wakeup_ports[3].bits.uop.debug_tsrc connect slots_6.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[6].wakeup_ports[3].bits.uop.debug_fsrc connect slots_6.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[6].wakeup_ports[3].bits.uop.bp_xcpt_if connect slots_6.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[6].wakeup_ports[3].bits.uop.bp_debug_if connect slots_6.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[6].wakeup_ports[3].bits.uop.xcpt_ma_if connect slots_6.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[6].wakeup_ports[3].bits.uop.xcpt_ae_if connect slots_6.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[6].wakeup_ports[3].bits.uop.xcpt_pf_if connect slots_6.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[6].wakeup_ports[3].bits.uop.fp_typ connect slots_6.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[6].wakeup_ports[3].bits.uop.fp_rm connect slots_6.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[6].wakeup_ports[3].bits.uop.fp_val connect slots_6.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[6].wakeup_ports[3].bits.uop.fcn_op connect slots_6.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[6].wakeup_ports[3].bits.uop.fcn_dw connect slots_6.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[6].wakeup_ports[3].bits.uop.frs3_en connect slots_6.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[6].wakeup_ports[3].bits.uop.lrs2_rtype connect slots_6.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[6].wakeup_ports[3].bits.uop.lrs1_rtype connect slots_6.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[6].wakeup_ports[3].bits.uop.dst_rtype connect slots_6.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[6].wakeup_ports[3].bits.uop.lrs3 connect slots_6.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[6].wakeup_ports[3].bits.uop.lrs2 connect slots_6.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[6].wakeup_ports[3].bits.uop.lrs1 connect slots_6.io.wakeup_ports[3].bits.uop.ldst, issue_slots[6].wakeup_ports[3].bits.uop.ldst connect slots_6.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[6].wakeup_ports[3].bits.uop.ldst_is_rs1 connect slots_6.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[6].wakeup_ports[3].bits.uop.csr_cmd connect slots_6.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[6].wakeup_ports[3].bits.uop.flush_on_commit connect slots_6.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[6].wakeup_ports[3].bits.uop.is_unique connect slots_6.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[6].wakeup_ports[3].bits.uop.uses_stq connect slots_6.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[6].wakeup_ports[3].bits.uop.uses_ldq connect slots_6.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[6].wakeup_ports[3].bits.uop.mem_signed connect slots_6.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[6].wakeup_ports[3].bits.uop.mem_size connect slots_6.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[6].wakeup_ports[3].bits.uop.mem_cmd connect slots_6.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[6].wakeup_ports[3].bits.uop.exc_cause connect slots_6.io.wakeup_ports[3].bits.uop.exception, issue_slots[6].wakeup_ports[3].bits.uop.exception connect slots_6.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[6].wakeup_ports[3].bits.uop.stale_pdst connect slots_6.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[6].wakeup_ports[3].bits.uop.ppred_busy connect slots_6.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[6].wakeup_ports[3].bits.uop.prs3_busy connect slots_6.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[6].wakeup_ports[3].bits.uop.prs2_busy connect slots_6.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[6].wakeup_ports[3].bits.uop.prs1_busy connect slots_6.io.wakeup_ports[3].bits.uop.ppred, issue_slots[6].wakeup_ports[3].bits.uop.ppred connect slots_6.io.wakeup_ports[3].bits.uop.prs3, issue_slots[6].wakeup_ports[3].bits.uop.prs3 connect slots_6.io.wakeup_ports[3].bits.uop.prs2, issue_slots[6].wakeup_ports[3].bits.uop.prs2 connect slots_6.io.wakeup_ports[3].bits.uop.prs1, issue_slots[6].wakeup_ports[3].bits.uop.prs1 connect slots_6.io.wakeup_ports[3].bits.uop.pdst, issue_slots[6].wakeup_ports[3].bits.uop.pdst connect slots_6.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[6].wakeup_ports[3].bits.uop.rxq_idx connect slots_6.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[6].wakeup_ports[3].bits.uop.stq_idx connect slots_6.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[6].wakeup_ports[3].bits.uop.ldq_idx connect slots_6.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[6].wakeup_ports[3].bits.uop.rob_idx connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.vec connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.wflags connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.div connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.fma connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.toint connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.fromint connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.wen connect slots_6.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.ldst connect slots_6.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[6].wakeup_ports[3].bits.uop.op2_sel connect slots_6.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[6].wakeup_ports[3].bits.uop.op1_sel connect slots_6.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[6].wakeup_ports[3].bits.uop.imm_packed connect slots_6.io.wakeup_ports[3].bits.uop.pimm, issue_slots[6].wakeup_ports[3].bits.uop.pimm connect slots_6.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[6].wakeup_ports[3].bits.uop.imm_sel connect slots_6.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[6].wakeup_ports[3].bits.uop.imm_rename connect slots_6.io.wakeup_ports[3].bits.uop.taken, issue_slots[6].wakeup_ports[3].bits.uop.taken connect slots_6.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[6].wakeup_ports[3].bits.uop.pc_lob connect slots_6.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[6].wakeup_ports[3].bits.uop.edge_inst connect slots_6.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[6].wakeup_ports[3].bits.uop.ftq_idx connect slots_6.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[6].wakeup_ports[3].bits.uop.is_mov connect slots_6.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[6].wakeup_ports[3].bits.uop.is_rocc connect slots_6.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[6].wakeup_ports[3].bits.uop.is_sys_pc2epc connect slots_6.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[6].wakeup_ports[3].bits.uop.is_eret connect slots_6.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[6].wakeup_ports[3].bits.uop.is_amo connect slots_6.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[6].wakeup_ports[3].bits.uop.is_sfence connect slots_6.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[6].wakeup_ports[3].bits.uop.is_fencei connect slots_6.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[6].wakeup_ports[3].bits.uop.is_fence connect slots_6.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[6].wakeup_ports[3].bits.uop.is_sfb connect slots_6.io.wakeup_ports[3].bits.uop.br_type, issue_slots[6].wakeup_ports[3].bits.uop.br_type connect slots_6.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[6].wakeup_ports[3].bits.uop.br_tag connect slots_6.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[6].wakeup_ports[3].bits.uop.br_mask connect slots_6.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[6].wakeup_ports[3].bits.uop.dis_col_sel connect slots_6.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[6].wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect slots_6.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[6].wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect slots_6.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[6].wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect slots_6.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[6].wakeup_ports[3].bits.uop.iw_p2_speculative_child connect slots_6.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[6].wakeup_ports[3].bits.uop.iw_p1_speculative_child connect slots_6.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[6].wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect slots_6.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[6].wakeup_ports[3].bits.uop.iw_issued_partial_agen connect slots_6.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[6].wakeup_ports[3].bits.uop.iw_issued connect slots_6.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[6].wakeup_ports[3].bits.uop.fu_code[0] connect slots_6.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[6].wakeup_ports[3].bits.uop.fu_code[1] connect slots_6.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[6].wakeup_ports[3].bits.uop.fu_code[2] connect slots_6.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[6].wakeup_ports[3].bits.uop.fu_code[3] connect slots_6.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[6].wakeup_ports[3].bits.uop.fu_code[4] connect slots_6.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[6].wakeup_ports[3].bits.uop.fu_code[5] connect slots_6.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[6].wakeup_ports[3].bits.uop.fu_code[6] connect slots_6.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[6].wakeup_ports[3].bits.uop.fu_code[7] connect slots_6.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[6].wakeup_ports[3].bits.uop.fu_code[8] connect slots_6.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[6].wakeup_ports[3].bits.uop.fu_code[9] connect slots_6.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[6].wakeup_ports[3].bits.uop.iq_type[0] connect slots_6.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[6].wakeup_ports[3].bits.uop.iq_type[1] connect slots_6.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[6].wakeup_ports[3].bits.uop.iq_type[2] connect slots_6.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[6].wakeup_ports[3].bits.uop.iq_type[3] connect slots_6.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[6].wakeup_ports[3].bits.uop.debug_pc connect slots_6.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[6].wakeup_ports[3].bits.uop.is_rvc connect slots_6.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[6].wakeup_ports[3].bits.uop.debug_inst connect slots_6.io.wakeup_ports[3].bits.uop.inst, issue_slots[6].wakeup_ports[3].bits.uop.inst connect slots_6.io.wakeup_ports[3].valid, issue_slots[6].wakeup_ports[3].valid connect slots_6.io.wakeup_ports[4].bits.rebusy, issue_slots[6].wakeup_ports[4].bits.rebusy connect slots_6.io.wakeup_ports[4].bits.speculative_mask, issue_slots[6].wakeup_ports[4].bits.speculative_mask connect slots_6.io.wakeup_ports[4].bits.bypassable, issue_slots[6].wakeup_ports[4].bits.bypassable connect slots_6.io.wakeup_ports[4].bits.uop.debug_tsrc, issue_slots[6].wakeup_ports[4].bits.uop.debug_tsrc connect slots_6.io.wakeup_ports[4].bits.uop.debug_fsrc, issue_slots[6].wakeup_ports[4].bits.uop.debug_fsrc connect slots_6.io.wakeup_ports[4].bits.uop.bp_xcpt_if, issue_slots[6].wakeup_ports[4].bits.uop.bp_xcpt_if connect slots_6.io.wakeup_ports[4].bits.uop.bp_debug_if, issue_slots[6].wakeup_ports[4].bits.uop.bp_debug_if connect slots_6.io.wakeup_ports[4].bits.uop.xcpt_ma_if, issue_slots[6].wakeup_ports[4].bits.uop.xcpt_ma_if connect slots_6.io.wakeup_ports[4].bits.uop.xcpt_ae_if, issue_slots[6].wakeup_ports[4].bits.uop.xcpt_ae_if connect slots_6.io.wakeup_ports[4].bits.uop.xcpt_pf_if, issue_slots[6].wakeup_ports[4].bits.uop.xcpt_pf_if connect slots_6.io.wakeup_ports[4].bits.uop.fp_typ, issue_slots[6].wakeup_ports[4].bits.uop.fp_typ connect slots_6.io.wakeup_ports[4].bits.uop.fp_rm, issue_slots[6].wakeup_ports[4].bits.uop.fp_rm connect slots_6.io.wakeup_ports[4].bits.uop.fp_val, issue_slots[6].wakeup_ports[4].bits.uop.fp_val connect slots_6.io.wakeup_ports[4].bits.uop.fcn_op, issue_slots[6].wakeup_ports[4].bits.uop.fcn_op connect slots_6.io.wakeup_ports[4].bits.uop.fcn_dw, issue_slots[6].wakeup_ports[4].bits.uop.fcn_dw connect slots_6.io.wakeup_ports[4].bits.uop.frs3_en, issue_slots[6].wakeup_ports[4].bits.uop.frs3_en connect slots_6.io.wakeup_ports[4].bits.uop.lrs2_rtype, issue_slots[6].wakeup_ports[4].bits.uop.lrs2_rtype connect slots_6.io.wakeup_ports[4].bits.uop.lrs1_rtype, issue_slots[6].wakeup_ports[4].bits.uop.lrs1_rtype connect slots_6.io.wakeup_ports[4].bits.uop.dst_rtype, issue_slots[6].wakeup_ports[4].bits.uop.dst_rtype connect slots_6.io.wakeup_ports[4].bits.uop.lrs3, issue_slots[6].wakeup_ports[4].bits.uop.lrs3 connect slots_6.io.wakeup_ports[4].bits.uop.lrs2, issue_slots[6].wakeup_ports[4].bits.uop.lrs2 connect slots_6.io.wakeup_ports[4].bits.uop.lrs1, issue_slots[6].wakeup_ports[4].bits.uop.lrs1 connect slots_6.io.wakeup_ports[4].bits.uop.ldst, issue_slots[6].wakeup_ports[4].bits.uop.ldst connect slots_6.io.wakeup_ports[4].bits.uop.ldst_is_rs1, issue_slots[6].wakeup_ports[4].bits.uop.ldst_is_rs1 connect slots_6.io.wakeup_ports[4].bits.uop.csr_cmd, issue_slots[6].wakeup_ports[4].bits.uop.csr_cmd connect slots_6.io.wakeup_ports[4].bits.uop.flush_on_commit, issue_slots[6].wakeup_ports[4].bits.uop.flush_on_commit connect slots_6.io.wakeup_ports[4].bits.uop.is_unique, issue_slots[6].wakeup_ports[4].bits.uop.is_unique connect slots_6.io.wakeup_ports[4].bits.uop.uses_stq, issue_slots[6].wakeup_ports[4].bits.uop.uses_stq connect slots_6.io.wakeup_ports[4].bits.uop.uses_ldq, issue_slots[6].wakeup_ports[4].bits.uop.uses_ldq connect slots_6.io.wakeup_ports[4].bits.uop.mem_signed, issue_slots[6].wakeup_ports[4].bits.uop.mem_signed connect slots_6.io.wakeup_ports[4].bits.uop.mem_size, issue_slots[6].wakeup_ports[4].bits.uop.mem_size connect slots_6.io.wakeup_ports[4].bits.uop.mem_cmd, issue_slots[6].wakeup_ports[4].bits.uop.mem_cmd connect slots_6.io.wakeup_ports[4].bits.uop.exc_cause, issue_slots[6].wakeup_ports[4].bits.uop.exc_cause connect slots_6.io.wakeup_ports[4].bits.uop.exception, issue_slots[6].wakeup_ports[4].bits.uop.exception connect slots_6.io.wakeup_ports[4].bits.uop.stale_pdst, issue_slots[6].wakeup_ports[4].bits.uop.stale_pdst connect slots_6.io.wakeup_ports[4].bits.uop.ppred_busy, issue_slots[6].wakeup_ports[4].bits.uop.ppred_busy connect slots_6.io.wakeup_ports[4].bits.uop.prs3_busy, issue_slots[6].wakeup_ports[4].bits.uop.prs3_busy connect slots_6.io.wakeup_ports[4].bits.uop.prs2_busy, issue_slots[6].wakeup_ports[4].bits.uop.prs2_busy connect slots_6.io.wakeup_ports[4].bits.uop.prs1_busy, issue_slots[6].wakeup_ports[4].bits.uop.prs1_busy connect slots_6.io.wakeup_ports[4].bits.uop.ppred, issue_slots[6].wakeup_ports[4].bits.uop.ppred connect slots_6.io.wakeup_ports[4].bits.uop.prs3, issue_slots[6].wakeup_ports[4].bits.uop.prs3 connect slots_6.io.wakeup_ports[4].bits.uop.prs2, issue_slots[6].wakeup_ports[4].bits.uop.prs2 connect slots_6.io.wakeup_ports[4].bits.uop.prs1, issue_slots[6].wakeup_ports[4].bits.uop.prs1 connect slots_6.io.wakeup_ports[4].bits.uop.pdst, issue_slots[6].wakeup_ports[4].bits.uop.pdst connect slots_6.io.wakeup_ports[4].bits.uop.rxq_idx, issue_slots[6].wakeup_ports[4].bits.uop.rxq_idx connect slots_6.io.wakeup_ports[4].bits.uop.stq_idx, issue_slots[6].wakeup_ports[4].bits.uop.stq_idx connect slots_6.io.wakeup_ports[4].bits.uop.ldq_idx, issue_slots[6].wakeup_ports[4].bits.uop.ldq_idx connect slots_6.io.wakeup_ports[4].bits.uop.rob_idx, issue_slots[6].wakeup_ports[4].bits.uop.rob_idx connect slots_6.io.wakeup_ports[4].bits.uop.fp_ctrl.vec, issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.vec connect slots_6.io.wakeup_ports[4].bits.uop.fp_ctrl.wflags, issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.wflags connect slots_6.io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt, issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect slots_6.io.wakeup_ports[4].bits.uop.fp_ctrl.div, issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.div connect slots_6.io.wakeup_ports[4].bits.uop.fp_ctrl.fma, issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.fma connect slots_6.io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect slots_6.io.wakeup_ports[4].bits.uop.fp_ctrl.toint, issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.toint connect slots_6.io.wakeup_ports[4].bits.uop.fp_ctrl.fromint, issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.fromint connect slots_6.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect slots_6.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect slots_6.io.wakeup_ports[4].bits.uop.fp_ctrl.swap23, issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect slots_6.io.wakeup_ports[4].bits.uop.fp_ctrl.swap12, issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect slots_6.io.wakeup_ports[4].bits.uop.fp_ctrl.ren3, issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect slots_6.io.wakeup_ports[4].bits.uop.fp_ctrl.ren2, issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect slots_6.io.wakeup_ports[4].bits.uop.fp_ctrl.ren1, issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect slots_6.io.wakeup_ports[4].bits.uop.fp_ctrl.wen, issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.wen connect slots_6.io.wakeup_ports[4].bits.uop.fp_ctrl.ldst, issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.ldst connect slots_6.io.wakeup_ports[4].bits.uop.op2_sel, issue_slots[6].wakeup_ports[4].bits.uop.op2_sel connect slots_6.io.wakeup_ports[4].bits.uop.op1_sel, issue_slots[6].wakeup_ports[4].bits.uop.op1_sel connect slots_6.io.wakeup_ports[4].bits.uop.imm_packed, issue_slots[6].wakeup_ports[4].bits.uop.imm_packed connect slots_6.io.wakeup_ports[4].bits.uop.pimm, issue_slots[6].wakeup_ports[4].bits.uop.pimm connect slots_6.io.wakeup_ports[4].bits.uop.imm_sel, issue_slots[6].wakeup_ports[4].bits.uop.imm_sel connect slots_6.io.wakeup_ports[4].bits.uop.imm_rename, issue_slots[6].wakeup_ports[4].bits.uop.imm_rename connect slots_6.io.wakeup_ports[4].bits.uop.taken, issue_slots[6].wakeup_ports[4].bits.uop.taken connect slots_6.io.wakeup_ports[4].bits.uop.pc_lob, issue_slots[6].wakeup_ports[4].bits.uop.pc_lob connect slots_6.io.wakeup_ports[4].bits.uop.edge_inst, issue_slots[6].wakeup_ports[4].bits.uop.edge_inst connect slots_6.io.wakeup_ports[4].bits.uop.ftq_idx, issue_slots[6].wakeup_ports[4].bits.uop.ftq_idx connect slots_6.io.wakeup_ports[4].bits.uop.is_mov, issue_slots[6].wakeup_ports[4].bits.uop.is_mov connect slots_6.io.wakeup_ports[4].bits.uop.is_rocc, issue_slots[6].wakeup_ports[4].bits.uop.is_rocc connect slots_6.io.wakeup_ports[4].bits.uop.is_sys_pc2epc, issue_slots[6].wakeup_ports[4].bits.uop.is_sys_pc2epc connect slots_6.io.wakeup_ports[4].bits.uop.is_eret, issue_slots[6].wakeup_ports[4].bits.uop.is_eret connect slots_6.io.wakeup_ports[4].bits.uop.is_amo, issue_slots[6].wakeup_ports[4].bits.uop.is_amo connect slots_6.io.wakeup_ports[4].bits.uop.is_sfence, issue_slots[6].wakeup_ports[4].bits.uop.is_sfence connect slots_6.io.wakeup_ports[4].bits.uop.is_fencei, issue_slots[6].wakeup_ports[4].bits.uop.is_fencei connect slots_6.io.wakeup_ports[4].bits.uop.is_fence, issue_slots[6].wakeup_ports[4].bits.uop.is_fence connect slots_6.io.wakeup_ports[4].bits.uop.is_sfb, issue_slots[6].wakeup_ports[4].bits.uop.is_sfb connect slots_6.io.wakeup_ports[4].bits.uop.br_type, issue_slots[6].wakeup_ports[4].bits.uop.br_type connect slots_6.io.wakeup_ports[4].bits.uop.br_tag, issue_slots[6].wakeup_ports[4].bits.uop.br_tag connect slots_6.io.wakeup_ports[4].bits.uop.br_mask, issue_slots[6].wakeup_ports[4].bits.uop.br_mask connect slots_6.io.wakeup_ports[4].bits.uop.dis_col_sel, issue_slots[6].wakeup_ports[4].bits.uop.dis_col_sel connect slots_6.io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint, issue_slots[6].wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect slots_6.io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint, issue_slots[6].wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect slots_6.io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint, issue_slots[6].wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect slots_6.io.wakeup_ports[4].bits.uop.iw_p2_speculative_child, issue_slots[6].wakeup_ports[4].bits.uop.iw_p2_speculative_child connect slots_6.io.wakeup_ports[4].bits.uop.iw_p1_speculative_child, issue_slots[6].wakeup_ports[4].bits.uop.iw_p1_speculative_child connect slots_6.io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen, issue_slots[6].wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect slots_6.io.wakeup_ports[4].bits.uop.iw_issued_partial_agen, issue_slots[6].wakeup_ports[4].bits.uop.iw_issued_partial_agen connect slots_6.io.wakeup_ports[4].bits.uop.iw_issued, issue_slots[6].wakeup_ports[4].bits.uop.iw_issued connect slots_6.io.wakeup_ports[4].bits.uop.fu_code[0], issue_slots[6].wakeup_ports[4].bits.uop.fu_code[0] connect slots_6.io.wakeup_ports[4].bits.uop.fu_code[1], issue_slots[6].wakeup_ports[4].bits.uop.fu_code[1] connect slots_6.io.wakeup_ports[4].bits.uop.fu_code[2], issue_slots[6].wakeup_ports[4].bits.uop.fu_code[2] connect slots_6.io.wakeup_ports[4].bits.uop.fu_code[3], issue_slots[6].wakeup_ports[4].bits.uop.fu_code[3] connect slots_6.io.wakeup_ports[4].bits.uop.fu_code[4], issue_slots[6].wakeup_ports[4].bits.uop.fu_code[4] connect slots_6.io.wakeup_ports[4].bits.uop.fu_code[5], issue_slots[6].wakeup_ports[4].bits.uop.fu_code[5] connect slots_6.io.wakeup_ports[4].bits.uop.fu_code[6], issue_slots[6].wakeup_ports[4].bits.uop.fu_code[6] connect slots_6.io.wakeup_ports[4].bits.uop.fu_code[7], issue_slots[6].wakeup_ports[4].bits.uop.fu_code[7] connect slots_6.io.wakeup_ports[4].bits.uop.fu_code[8], issue_slots[6].wakeup_ports[4].bits.uop.fu_code[8] connect slots_6.io.wakeup_ports[4].bits.uop.fu_code[9], issue_slots[6].wakeup_ports[4].bits.uop.fu_code[9] connect slots_6.io.wakeup_ports[4].bits.uop.iq_type[0], issue_slots[6].wakeup_ports[4].bits.uop.iq_type[0] connect slots_6.io.wakeup_ports[4].bits.uop.iq_type[1], issue_slots[6].wakeup_ports[4].bits.uop.iq_type[1] connect slots_6.io.wakeup_ports[4].bits.uop.iq_type[2], issue_slots[6].wakeup_ports[4].bits.uop.iq_type[2] connect slots_6.io.wakeup_ports[4].bits.uop.iq_type[3], issue_slots[6].wakeup_ports[4].bits.uop.iq_type[3] connect slots_6.io.wakeup_ports[4].bits.uop.debug_pc, issue_slots[6].wakeup_ports[4].bits.uop.debug_pc connect slots_6.io.wakeup_ports[4].bits.uop.is_rvc, issue_slots[6].wakeup_ports[4].bits.uop.is_rvc connect slots_6.io.wakeup_ports[4].bits.uop.debug_inst, issue_slots[6].wakeup_ports[4].bits.uop.debug_inst connect slots_6.io.wakeup_ports[4].bits.uop.inst, issue_slots[6].wakeup_ports[4].bits.uop.inst connect slots_6.io.wakeup_ports[4].valid, issue_slots[6].wakeup_ports[4].valid connect slots_6.io.squash_grant, issue_slots[6].squash_grant connect slots_6.io.clear, issue_slots[6].clear connect slots_6.io.kill, issue_slots[6].kill connect slots_6.io.brupdate.b2.target_offset, issue_slots[6].brupdate.b2.target_offset connect slots_6.io.brupdate.b2.jalr_target, issue_slots[6].brupdate.b2.jalr_target connect slots_6.io.brupdate.b2.pc_sel, issue_slots[6].brupdate.b2.pc_sel connect slots_6.io.brupdate.b2.cfi_type, issue_slots[6].brupdate.b2.cfi_type connect slots_6.io.brupdate.b2.taken, issue_slots[6].brupdate.b2.taken connect slots_6.io.brupdate.b2.mispredict, issue_slots[6].brupdate.b2.mispredict connect slots_6.io.brupdate.b2.uop.debug_tsrc, issue_slots[6].brupdate.b2.uop.debug_tsrc connect slots_6.io.brupdate.b2.uop.debug_fsrc, issue_slots[6].brupdate.b2.uop.debug_fsrc connect slots_6.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[6].brupdate.b2.uop.bp_xcpt_if connect slots_6.io.brupdate.b2.uop.bp_debug_if, issue_slots[6].brupdate.b2.uop.bp_debug_if connect slots_6.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[6].brupdate.b2.uop.xcpt_ma_if connect slots_6.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[6].brupdate.b2.uop.xcpt_ae_if connect slots_6.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[6].brupdate.b2.uop.xcpt_pf_if connect slots_6.io.brupdate.b2.uop.fp_typ, issue_slots[6].brupdate.b2.uop.fp_typ connect slots_6.io.brupdate.b2.uop.fp_rm, issue_slots[6].brupdate.b2.uop.fp_rm connect slots_6.io.brupdate.b2.uop.fp_val, issue_slots[6].brupdate.b2.uop.fp_val connect slots_6.io.brupdate.b2.uop.fcn_op, issue_slots[6].brupdate.b2.uop.fcn_op connect slots_6.io.brupdate.b2.uop.fcn_dw, issue_slots[6].brupdate.b2.uop.fcn_dw connect slots_6.io.brupdate.b2.uop.frs3_en, issue_slots[6].brupdate.b2.uop.frs3_en connect slots_6.io.brupdate.b2.uop.lrs2_rtype, issue_slots[6].brupdate.b2.uop.lrs2_rtype connect slots_6.io.brupdate.b2.uop.lrs1_rtype, issue_slots[6].brupdate.b2.uop.lrs1_rtype connect slots_6.io.brupdate.b2.uop.dst_rtype, issue_slots[6].brupdate.b2.uop.dst_rtype connect slots_6.io.brupdate.b2.uop.lrs3, issue_slots[6].brupdate.b2.uop.lrs3 connect slots_6.io.brupdate.b2.uop.lrs2, issue_slots[6].brupdate.b2.uop.lrs2 connect slots_6.io.brupdate.b2.uop.lrs1, issue_slots[6].brupdate.b2.uop.lrs1 connect slots_6.io.brupdate.b2.uop.ldst, issue_slots[6].brupdate.b2.uop.ldst connect slots_6.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[6].brupdate.b2.uop.ldst_is_rs1 connect slots_6.io.brupdate.b2.uop.csr_cmd, issue_slots[6].brupdate.b2.uop.csr_cmd connect slots_6.io.brupdate.b2.uop.flush_on_commit, issue_slots[6].brupdate.b2.uop.flush_on_commit connect slots_6.io.brupdate.b2.uop.is_unique, issue_slots[6].brupdate.b2.uop.is_unique connect slots_6.io.brupdate.b2.uop.uses_stq, issue_slots[6].brupdate.b2.uop.uses_stq connect slots_6.io.brupdate.b2.uop.uses_ldq, issue_slots[6].brupdate.b2.uop.uses_ldq connect slots_6.io.brupdate.b2.uop.mem_signed, issue_slots[6].brupdate.b2.uop.mem_signed connect slots_6.io.brupdate.b2.uop.mem_size, issue_slots[6].brupdate.b2.uop.mem_size connect slots_6.io.brupdate.b2.uop.mem_cmd, issue_slots[6].brupdate.b2.uop.mem_cmd connect slots_6.io.brupdate.b2.uop.exc_cause, issue_slots[6].brupdate.b2.uop.exc_cause connect slots_6.io.brupdate.b2.uop.exception, issue_slots[6].brupdate.b2.uop.exception connect slots_6.io.brupdate.b2.uop.stale_pdst, issue_slots[6].brupdate.b2.uop.stale_pdst connect slots_6.io.brupdate.b2.uop.ppred_busy, issue_slots[6].brupdate.b2.uop.ppred_busy connect slots_6.io.brupdate.b2.uop.prs3_busy, issue_slots[6].brupdate.b2.uop.prs3_busy connect slots_6.io.brupdate.b2.uop.prs2_busy, issue_slots[6].brupdate.b2.uop.prs2_busy connect slots_6.io.brupdate.b2.uop.prs1_busy, issue_slots[6].brupdate.b2.uop.prs1_busy connect slots_6.io.brupdate.b2.uop.ppred, issue_slots[6].brupdate.b2.uop.ppred connect slots_6.io.brupdate.b2.uop.prs3, issue_slots[6].brupdate.b2.uop.prs3 connect slots_6.io.brupdate.b2.uop.prs2, issue_slots[6].brupdate.b2.uop.prs2 connect slots_6.io.brupdate.b2.uop.prs1, issue_slots[6].brupdate.b2.uop.prs1 connect slots_6.io.brupdate.b2.uop.pdst, issue_slots[6].brupdate.b2.uop.pdst connect slots_6.io.brupdate.b2.uop.rxq_idx, issue_slots[6].brupdate.b2.uop.rxq_idx connect slots_6.io.brupdate.b2.uop.stq_idx, issue_slots[6].brupdate.b2.uop.stq_idx connect slots_6.io.brupdate.b2.uop.ldq_idx, issue_slots[6].brupdate.b2.uop.ldq_idx connect slots_6.io.brupdate.b2.uop.rob_idx, issue_slots[6].brupdate.b2.uop.rob_idx connect slots_6.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[6].brupdate.b2.uop.fp_ctrl.vec connect slots_6.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[6].brupdate.b2.uop.fp_ctrl.wflags connect slots_6.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[6].brupdate.b2.uop.fp_ctrl.sqrt connect slots_6.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[6].brupdate.b2.uop.fp_ctrl.div connect slots_6.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[6].brupdate.b2.uop.fp_ctrl.fma connect slots_6.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[6].brupdate.b2.uop.fp_ctrl.fastpipe connect slots_6.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[6].brupdate.b2.uop.fp_ctrl.toint connect slots_6.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[6].brupdate.b2.uop.fp_ctrl.fromint connect slots_6.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[6].brupdate.b2.uop.fp_ctrl.typeTagOut connect slots_6.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[6].brupdate.b2.uop.fp_ctrl.typeTagIn connect slots_6.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[6].brupdate.b2.uop.fp_ctrl.swap23 connect slots_6.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[6].brupdate.b2.uop.fp_ctrl.swap12 connect slots_6.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[6].brupdate.b2.uop.fp_ctrl.ren3 connect slots_6.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[6].brupdate.b2.uop.fp_ctrl.ren2 connect slots_6.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[6].brupdate.b2.uop.fp_ctrl.ren1 connect slots_6.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[6].brupdate.b2.uop.fp_ctrl.wen connect slots_6.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[6].brupdate.b2.uop.fp_ctrl.ldst connect slots_6.io.brupdate.b2.uop.op2_sel, issue_slots[6].brupdate.b2.uop.op2_sel connect slots_6.io.brupdate.b2.uop.op1_sel, issue_slots[6].brupdate.b2.uop.op1_sel connect slots_6.io.brupdate.b2.uop.imm_packed, issue_slots[6].brupdate.b2.uop.imm_packed connect slots_6.io.brupdate.b2.uop.pimm, issue_slots[6].brupdate.b2.uop.pimm connect slots_6.io.brupdate.b2.uop.imm_sel, issue_slots[6].brupdate.b2.uop.imm_sel connect slots_6.io.brupdate.b2.uop.imm_rename, issue_slots[6].brupdate.b2.uop.imm_rename connect slots_6.io.brupdate.b2.uop.taken, issue_slots[6].brupdate.b2.uop.taken connect slots_6.io.brupdate.b2.uop.pc_lob, issue_slots[6].brupdate.b2.uop.pc_lob connect slots_6.io.brupdate.b2.uop.edge_inst, issue_slots[6].brupdate.b2.uop.edge_inst connect slots_6.io.brupdate.b2.uop.ftq_idx, issue_slots[6].brupdate.b2.uop.ftq_idx connect slots_6.io.brupdate.b2.uop.is_mov, issue_slots[6].brupdate.b2.uop.is_mov connect slots_6.io.brupdate.b2.uop.is_rocc, issue_slots[6].brupdate.b2.uop.is_rocc connect slots_6.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[6].brupdate.b2.uop.is_sys_pc2epc connect slots_6.io.brupdate.b2.uop.is_eret, issue_slots[6].brupdate.b2.uop.is_eret connect slots_6.io.brupdate.b2.uop.is_amo, issue_slots[6].brupdate.b2.uop.is_amo connect slots_6.io.brupdate.b2.uop.is_sfence, issue_slots[6].brupdate.b2.uop.is_sfence connect slots_6.io.brupdate.b2.uop.is_fencei, issue_slots[6].brupdate.b2.uop.is_fencei connect slots_6.io.brupdate.b2.uop.is_fence, issue_slots[6].brupdate.b2.uop.is_fence connect slots_6.io.brupdate.b2.uop.is_sfb, issue_slots[6].brupdate.b2.uop.is_sfb connect slots_6.io.brupdate.b2.uop.br_type, issue_slots[6].brupdate.b2.uop.br_type connect slots_6.io.brupdate.b2.uop.br_tag, issue_slots[6].brupdate.b2.uop.br_tag connect slots_6.io.brupdate.b2.uop.br_mask, issue_slots[6].brupdate.b2.uop.br_mask connect slots_6.io.brupdate.b2.uop.dis_col_sel, issue_slots[6].brupdate.b2.uop.dis_col_sel connect slots_6.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[6].brupdate.b2.uop.iw_p3_bypass_hint connect slots_6.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[6].brupdate.b2.uop.iw_p2_bypass_hint connect slots_6.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[6].brupdate.b2.uop.iw_p1_bypass_hint connect slots_6.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[6].brupdate.b2.uop.iw_p2_speculative_child connect slots_6.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[6].brupdate.b2.uop.iw_p1_speculative_child connect slots_6.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[6].brupdate.b2.uop.iw_issued_partial_dgen connect slots_6.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[6].brupdate.b2.uop.iw_issued_partial_agen connect slots_6.io.brupdate.b2.uop.iw_issued, issue_slots[6].brupdate.b2.uop.iw_issued connect slots_6.io.brupdate.b2.uop.fu_code[0], issue_slots[6].brupdate.b2.uop.fu_code[0] connect slots_6.io.brupdate.b2.uop.fu_code[1], issue_slots[6].brupdate.b2.uop.fu_code[1] connect slots_6.io.brupdate.b2.uop.fu_code[2], issue_slots[6].brupdate.b2.uop.fu_code[2] connect slots_6.io.brupdate.b2.uop.fu_code[3], issue_slots[6].brupdate.b2.uop.fu_code[3] connect slots_6.io.brupdate.b2.uop.fu_code[4], issue_slots[6].brupdate.b2.uop.fu_code[4] connect slots_6.io.brupdate.b2.uop.fu_code[5], issue_slots[6].brupdate.b2.uop.fu_code[5] connect slots_6.io.brupdate.b2.uop.fu_code[6], issue_slots[6].brupdate.b2.uop.fu_code[6] connect slots_6.io.brupdate.b2.uop.fu_code[7], issue_slots[6].brupdate.b2.uop.fu_code[7] connect slots_6.io.brupdate.b2.uop.fu_code[8], issue_slots[6].brupdate.b2.uop.fu_code[8] connect slots_6.io.brupdate.b2.uop.fu_code[9], issue_slots[6].brupdate.b2.uop.fu_code[9] connect slots_6.io.brupdate.b2.uop.iq_type[0], issue_slots[6].brupdate.b2.uop.iq_type[0] connect slots_6.io.brupdate.b2.uop.iq_type[1], issue_slots[6].brupdate.b2.uop.iq_type[1] connect slots_6.io.brupdate.b2.uop.iq_type[2], issue_slots[6].brupdate.b2.uop.iq_type[2] connect slots_6.io.brupdate.b2.uop.iq_type[3], issue_slots[6].brupdate.b2.uop.iq_type[3] connect slots_6.io.brupdate.b2.uop.debug_pc, issue_slots[6].brupdate.b2.uop.debug_pc connect slots_6.io.brupdate.b2.uop.is_rvc, issue_slots[6].brupdate.b2.uop.is_rvc connect slots_6.io.brupdate.b2.uop.debug_inst, issue_slots[6].brupdate.b2.uop.debug_inst connect slots_6.io.brupdate.b2.uop.inst, issue_slots[6].brupdate.b2.uop.inst connect slots_6.io.brupdate.b1.mispredict_mask, issue_slots[6].brupdate.b1.mispredict_mask connect slots_6.io.brupdate.b1.resolve_mask, issue_slots[6].brupdate.b1.resolve_mask connect issue_slots[6].out_uop.debug_tsrc, slots_6.io.out_uop.debug_tsrc connect issue_slots[6].out_uop.debug_fsrc, slots_6.io.out_uop.debug_fsrc connect issue_slots[6].out_uop.bp_xcpt_if, slots_6.io.out_uop.bp_xcpt_if connect issue_slots[6].out_uop.bp_debug_if, slots_6.io.out_uop.bp_debug_if connect issue_slots[6].out_uop.xcpt_ma_if, slots_6.io.out_uop.xcpt_ma_if connect issue_slots[6].out_uop.xcpt_ae_if, slots_6.io.out_uop.xcpt_ae_if connect issue_slots[6].out_uop.xcpt_pf_if, slots_6.io.out_uop.xcpt_pf_if connect issue_slots[6].out_uop.fp_typ, slots_6.io.out_uop.fp_typ connect issue_slots[6].out_uop.fp_rm, slots_6.io.out_uop.fp_rm connect issue_slots[6].out_uop.fp_val, slots_6.io.out_uop.fp_val connect issue_slots[6].out_uop.fcn_op, slots_6.io.out_uop.fcn_op connect issue_slots[6].out_uop.fcn_dw, slots_6.io.out_uop.fcn_dw connect issue_slots[6].out_uop.frs3_en, slots_6.io.out_uop.frs3_en connect issue_slots[6].out_uop.lrs2_rtype, slots_6.io.out_uop.lrs2_rtype connect issue_slots[6].out_uop.lrs1_rtype, slots_6.io.out_uop.lrs1_rtype connect issue_slots[6].out_uop.dst_rtype, slots_6.io.out_uop.dst_rtype connect issue_slots[6].out_uop.lrs3, slots_6.io.out_uop.lrs3 connect issue_slots[6].out_uop.lrs2, slots_6.io.out_uop.lrs2 connect issue_slots[6].out_uop.lrs1, slots_6.io.out_uop.lrs1 connect issue_slots[6].out_uop.ldst, slots_6.io.out_uop.ldst connect issue_slots[6].out_uop.ldst_is_rs1, slots_6.io.out_uop.ldst_is_rs1 connect issue_slots[6].out_uop.csr_cmd, slots_6.io.out_uop.csr_cmd connect issue_slots[6].out_uop.flush_on_commit, slots_6.io.out_uop.flush_on_commit connect issue_slots[6].out_uop.is_unique, slots_6.io.out_uop.is_unique connect issue_slots[6].out_uop.uses_stq, slots_6.io.out_uop.uses_stq connect issue_slots[6].out_uop.uses_ldq, slots_6.io.out_uop.uses_ldq connect issue_slots[6].out_uop.mem_signed, slots_6.io.out_uop.mem_signed connect issue_slots[6].out_uop.mem_size, slots_6.io.out_uop.mem_size connect issue_slots[6].out_uop.mem_cmd, slots_6.io.out_uop.mem_cmd connect issue_slots[6].out_uop.exc_cause, slots_6.io.out_uop.exc_cause connect issue_slots[6].out_uop.exception, slots_6.io.out_uop.exception connect issue_slots[6].out_uop.stale_pdst, slots_6.io.out_uop.stale_pdst connect issue_slots[6].out_uop.ppred_busy, slots_6.io.out_uop.ppred_busy connect issue_slots[6].out_uop.prs3_busy, slots_6.io.out_uop.prs3_busy connect issue_slots[6].out_uop.prs2_busy, slots_6.io.out_uop.prs2_busy connect issue_slots[6].out_uop.prs1_busy, slots_6.io.out_uop.prs1_busy connect issue_slots[6].out_uop.ppred, slots_6.io.out_uop.ppred connect issue_slots[6].out_uop.prs3, slots_6.io.out_uop.prs3 connect issue_slots[6].out_uop.prs2, slots_6.io.out_uop.prs2 connect issue_slots[6].out_uop.prs1, slots_6.io.out_uop.prs1 connect issue_slots[6].out_uop.pdst, slots_6.io.out_uop.pdst connect issue_slots[6].out_uop.rxq_idx, slots_6.io.out_uop.rxq_idx connect issue_slots[6].out_uop.stq_idx, slots_6.io.out_uop.stq_idx connect issue_slots[6].out_uop.ldq_idx, slots_6.io.out_uop.ldq_idx connect issue_slots[6].out_uop.rob_idx, slots_6.io.out_uop.rob_idx connect issue_slots[6].out_uop.fp_ctrl.vec, slots_6.io.out_uop.fp_ctrl.vec connect issue_slots[6].out_uop.fp_ctrl.wflags, slots_6.io.out_uop.fp_ctrl.wflags connect issue_slots[6].out_uop.fp_ctrl.sqrt, slots_6.io.out_uop.fp_ctrl.sqrt connect issue_slots[6].out_uop.fp_ctrl.div, slots_6.io.out_uop.fp_ctrl.div connect issue_slots[6].out_uop.fp_ctrl.fma, slots_6.io.out_uop.fp_ctrl.fma connect issue_slots[6].out_uop.fp_ctrl.fastpipe, slots_6.io.out_uop.fp_ctrl.fastpipe connect issue_slots[6].out_uop.fp_ctrl.toint, slots_6.io.out_uop.fp_ctrl.toint connect issue_slots[6].out_uop.fp_ctrl.fromint, slots_6.io.out_uop.fp_ctrl.fromint connect issue_slots[6].out_uop.fp_ctrl.typeTagOut, slots_6.io.out_uop.fp_ctrl.typeTagOut connect issue_slots[6].out_uop.fp_ctrl.typeTagIn, slots_6.io.out_uop.fp_ctrl.typeTagIn connect issue_slots[6].out_uop.fp_ctrl.swap23, slots_6.io.out_uop.fp_ctrl.swap23 connect issue_slots[6].out_uop.fp_ctrl.swap12, slots_6.io.out_uop.fp_ctrl.swap12 connect issue_slots[6].out_uop.fp_ctrl.ren3, slots_6.io.out_uop.fp_ctrl.ren3 connect issue_slots[6].out_uop.fp_ctrl.ren2, slots_6.io.out_uop.fp_ctrl.ren2 connect issue_slots[6].out_uop.fp_ctrl.ren1, slots_6.io.out_uop.fp_ctrl.ren1 connect issue_slots[6].out_uop.fp_ctrl.wen, slots_6.io.out_uop.fp_ctrl.wen connect issue_slots[6].out_uop.fp_ctrl.ldst, slots_6.io.out_uop.fp_ctrl.ldst connect issue_slots[6].out_uop.op2_sel, slots_6.io.out_uop.op2_sel connect issue_slots[6].out_uop.op1_sel, slots_6.io.out_uop.op1_sel connect issue_slots[6].out_uop.imm_packed, slots_6.io.out_uop.imm_packed connect issue_slots[6].out_uop.pimm, slots_6.io.out_uop.pimm connect issue_slots[6].out_uop.imm_sel, slots_6.io.out_uop.imm_sel connect issue_slots[6].out_uop.imm_rename, slots_6.io.out_uop.imm_rename connect issue_slots[6].out_uop.taken, slots_6.io.out_uop.taken connect issue_slots[6].out_uop.pc_lob, slots_6.io.out_uop.pc_lob connect issue_slots[6].out_uop.edge_inst, slots_6.io.out_uop.edge_inst connect issue_slots[6].out_uop.ftq_idx, slots_6.io.out_uop.ftq_idx connect issue_slots[6].out_uop.is_mov, slots_6.io.out_uop.is_mov connect issue_slots[6].out_uop.is_rocc, slots_6.io.out_uop.is_rocc connect issue_slots[6].out_uop.is_sys_pc2epc, slots_6.io.out_uop.is_sys_pc2epc connect issue_slots[6].out_uop.is_eret, slots_6.io.out_uop.is_eret connect issue_slots[6].out_uop.is_amo, slots_6.io.out_uop.is_amo connect issue_slots[6].out_uop.is_sfence, slots_6.io.out_uop.is_sfence connect issue_slots[6].out_uop.is_fencei, slots_6.io.out_uop.is_fencei connect issue_slots[6].out_uop.is_fence, slots_6.io.out_uop.is_fence connect issue_slots[6].out_uop.is_sfb, slots_6.io.out_uop.is_sfb connect issue_slots[6].out_uop.br_type, slots_6.io.out_uop.br_type connect issue_slots[6].out_uop.br_tag, slots_6.io.out_uop.br_tag connect issue_slots[6].out_uop.br_mask, slots_6.io.out_uop.br_mask connect issue_slots[6].out_uop.dis_col_sel, slots_6.io.out_uop.dis_col_sel connect issue_slots[6].out_uop.iw_p3_bypass_hint, slots_6.io.out_uop.iw_p3_bypass_hint connect issue_slots[6].out_uop.iw_p2_bypass_hint, slots_6.io.out_uop.iw_p2_bypass_hint connect issue_slots[6].out_uop.iw_p1_bypass_hint, slots_6.io.out_uop.iw_p1_bypass_hint connect issue_slots[6].out_uop.iw_p2_speculative_child, slots_6.io.out_uop.iw_p2_speculative_child connect issue_slots[6].out_uop.iw_p1_speculative_child, slots_6.io.out_uop.iw_p1_speculative_child connect issue_slots[6].out_uop.iw_issued_partial_dgen, slots_6.io.out_uop.iw_issued_partial_dgen connect issue_slots[6].out_uop.iw_issued_partial_agen, slots_6.io.out_uop.iw_issued_partial_agen connect issue_slots[6].out_uop.iw_issued, slots_6.io.out_uop.iw_issued connect issue_slots[6].out_uop.fu_code[0], slots_6.io.out_uop.fu_code[0] connect issue_slots[6].out_uop.fu_code[1], slots_6.io.out_uop.fu_code[1] connect issue_slots[6].out_uop.fu_code[2], slots_6.io.out_uop.fu_code[2] connect issue_slots[6].out_uop.fu_code[3], slots_6.io.out_uop.fu_code[3] connect issue_slots[6].out_uop.fu_code[4], slots_6.io.out_uop.fu_code[4] connect issue_slots[6].out_uop.fu_code[5], slots_6.io.out_uop.fu_code[5] connect issue_slots[6].out_uop.fu_code[6], slots_6.io.out_uop.fu_code[6] connect issue_slots[6].out_uop.fu_code[7], slots_6.io.out_uop.fu_code[7] connect issue_slots[6].out_uop.fu_code[8], slots_6.io.out_uop.fu_code[8] connect issue_slots[6].out_uop.fu_code[9], slots_6.io.out_uop.fu_code[9] connect issue_slots[6].out_uop.iq_type[0], slots_6.io.out_uop.iq_type[0] connect issue_slots[6].out_uop.iq_type[1], slots_6.io.out_uop.iq_type[1] connect issue_slots[6].out_uop.iq_type[2], slots_6.io.out_uop.iq_type[2] connect issue_slots[6].out_uop.iq_type[3], slots_6.io.out_uop.iq_type[3] connect issue_slots[6].out_uop.debug_pc, slots_6.io.out_uop.debug_pc connect issue_slots[6].out_uop.is_rvc, slots_6.io.out_uop.is_rvc connect issue_slots[6].out_uop.debug_inst, slots_6.io.out_uop.debug_inst connect issue_slots[6].out_uop.inst, slots_6.io.out_uop.inst connect slots_6.io.in_uop.bits.debug_tsrc, issue_slots[6].in_uop.bits.debug_tsrc connect slots_6.io.in_uop.bits.debug_fsrc, issue_slots[6].in_uop.bits.debug_fsrc connect slots_6.io.in_uop.bits.bp_xcpt_if, issue_slots[6].in_uop.bits.bp_xcpt_if connect slots_6.io.in_uop.bits.bp_debug_if, issue_slots[6].in_uop.bits.bp_debug_if connect slots_6.io.in_uop.bits.xcpt_ma_if, issue_slots[6].in_uop.bits.xcpt_ma_if connect slots_6.io.in_uop.bits.xcpt_ae_if, issue_slots[6].in_uop.bits.xcpt_ae_if connect slots_6.io.in_uop.bits.xcpt_pf_if, issue_slots[6].in_uop.bits.xcpt_pf_if connect slots_6.io.in_uop.bits.fp_typ, issue_slots[6].in_uop.bits.fp_typ connect slots_6.io.in_uop.bits.fp_rm, issue_slots[6].in_uop.bits.fp_rm connect slots_6.io.in_uop.bits.fp_val, issue_slots[6].in_uop.bits.fp_val connect slots_6.io.in_uop.bits.fcn_op, issue_slots[6].in_uop.bits.fcn_op connect slots_6.io.in_uop.bits.fcn_dw, issue_slots[6].in_uop.bits.fcn_dw connect slots_6.io.in_uop.bits.frs3_en, issue_slots[6].in_uop.bits.frs3_en connect slots_6.io.in_uop.bits.lrs2_rtype, issue_slots[6].in_uop.bits.lrs2_rtype connect slots_6.io.in_uop.bits.lrs1_rtype, issue_slots[6].in_uop.bits.lrs1_rtype connect slots_6.io.in_uop.bits.dst_rtype, issue_slots[6].in_uop.bits.dst_rtype connect slots_6.io.in_uop.bits.lrs3, issue_slots[6].in_uop.bits.lrs3 connect slots_6.io.in_uop.bits.lrs2, issue_slots[6].in_uop.bits.lrs2 connect slots_6.io.in_uop.bits.lrs1, issue_slots[6].in_uop.bits.lrs1 connect slots_6.io.in_uop.bits.ldst, issue_slots[6].in_uop.bits.ldst connect slots_6.io.in_uop.bits.ldst_is_rs1, issue_slots[6].in_uop.bits.ldst_is_rs1 connect slots_6.io.in_uop.bits.csr_cmd, issue_slots[6].in_uop.bits.csr_cmd connect slots_6.io.in_uop.bits.flush_on_commit, issue_slots[6].in_uop.bits.flush_on_commit connect slots_6.io.in_uop.bits.is_unique, issue_slots[6].in_uop.bits.is_unique connect slots_6.io.in_uop.bits.uses_stq, issue_slots[6].in_uop.bits.uses_stq connect slots_6.io.in_uop.bits.uses_ldq, issue_slots[6].in_uop.bits.uses_ldq connect slots_6.io.in_uop.bits.mem_signed, issue_slots[6].in_uop.bits.mem_signed connect slots_6.io.in_uop.bits.mem_size, issue_slots[6].in_uop.bits.mem_size connect slots_6.io.in_uop.bits.mem_cmd, issue_slots[6].in_uop.bits.mem_cmd connect slots_6.io.in_uop.bits.exc_cause, issue_slots[6].in_uop.bits.exc_cause connect slots_6.io.in_uop.bits.exception, issue_slots[6].in_uop.bits.exception connect slots_6.io.in_uop.bits.stale_pdst, issue_slots[6].in_uop.bits.stale_pdst connect slots_6.io.in_uop.bits.ppred_busy, issue_slots[6].in_uop.bits.ppred_busy connect slots_6.io.in_uop.bits.prs3_busy, issue_slots[6].in_uop.bits.prs3_busy connect slots_6.io.in_uop.bits.prs2_busy, issue_slots[6].in_uop.bits.prs2_busy connect slots_6.io.in_uop.bits.prs1_busy, issue_slots[6].in_uop.bits.prs1_busy connect slots_6.io.in_uop.bits.ppred, issue_slots[6].in_uop.bits.ppred connect slots_6.io.in_uop.bits.prs3, issue_slots[6].in_uop.bits.prs3 connect slots_6.io.in_uop.bits.prs2, issue_slots[6].in_uop.bits.prs2 connect slots_6.io.in_uop.bits.prs1, issue_slots[6].in_uop.bits.prs1 connect slots_6.io.in_uop.bits.pdst, issue_slots[6].in_uop.bits.pdst connect slots_6.io.in_uop.bits.rxq_idx, issue_slots[6].in_uop.bits.rxq_idx connect slots_6.io.in_uop.bits.stq_idx, issue_slots[6].in_uop.bits.stq_idx connect slots_6.io.in_uop.bits.ldq_idx, issue_slots[6].in_uop.bits.ldq_idx connect slots_6.io.in_uop.bits.rob_idx, issue_slots[6].in_uop.bits.rob_idx connect slots_6.io.in_uop.bits.fp_ctrl.vec, issue_slots[6].in_uop.bits.fp_ctrl.vec connect slots_6.io.in_uop.bits.fp_ctrl.wflags, issue_slots[6].in_uop.bits.fp_ctrl.wflags connect slots_6.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[6].in_uop.bits.fp_ctrl.sqrt connect slots_6.io.in_uop.bits.fp_ctrl.div, issue_slots[6].in_uop.bits.fp_ctrl.div connect slots_6.io.in_uop.bits.fp_ctrl.fma, issue_slots[6].in_uop.bits.fp_ctrl.fma connect slots_6.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[6].in_uop.bits.fp_ctrl.fastpipe connect slots_6.io.in_uop.bits.fp_ctrl.toint, issue_slots[6].in_uop.bits.fp_ctrl.toint connect slots_6.io.in_uop.bits.fp_ctrl.fromint, issue_slots[6].in_uop.bits.fp_ctrl.fromint connect slots_6.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[6].in_uop.bits.fp_ctrl.typeTagOut connect slots_6.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[6].in_uop.bits.fp_ctrl.typeTagIn connect slots_6.io.in_uop.bits.fp_ctrl.swap23, issue_slots[6].in_uop.bits.fp_ctrl.swap23 connect slots_6.io.in_uop.bits.fp_ctrl.swap12, issue_slots[6].in_uop.bits.fp_ctrl.swap12 connect slots_6.io.in_uop.bits.fp_ctrl.ren3, issue_slots[6].in_uop.bits.fp_ctrl.ren3 connect slots_6.io.in_uop.bits.fp_ctrl.ren2, issue_slots[6].in_uop.bits.fp_ctrl.ren2 connect slots_6.io.in_uop.bits.fp_ctrl.ren1, issue_slots[6].in_uop.bits.fp_ctrl.ren1 connect slots_6.io.in_uop.bits.fp_ctrl.wen, issue_slots[6].in_uop.bits.fp_ctrl.wen connect slots_6.io.in_uop.bits.fp_ctrl.ldst, issue_slots[6].in_uop.bits.fp_ctrl.ldst connect slots_6.io.in_uop.bits.op2_sel, issue_slots[6].in_uop.bits.op2_sel connect slots_6.io.in_uop.bits.op1_sel, issue_slots[6].in_uop.bits.op1_sel connect slots_6.io.in_uop.bits.imm_packed, issue_slots[6].in_uop.bits.imm_packed connect slots_6.io.in_uop.bits.pimm, issue_slots[6].in_uop.bits.pimm connect slots_6.io.in_uop.bits.imm_sel, issue_slots[6].in_uop.bits.imm_sel connect slots_6.io.in_uop.bits.imm_rename, issue_slots[6].in_uop.bits.imm_rename connect slots_6.io.in_uop.bits.taken, issue_slots[6].in_uop.bits.taken connect slots_6.io.in_uop.bits.pc_lob, issue_slots[6].in_uop.bits.pc_lob connect slots_6.io.in_uop.bits.edge_inst, issue_slots[6].in_uop.bits.edge_inst connect slots_6.io.in_uop.bits.ftq_idx, issue_slots[6].in_uop.bits.ftq_idx connect slots_6.io.in_uop.bits.is_mov, issue_slots[6].in_uop.bits.is_mov connect slots_6.io.in_uop.bits.is_rocc, issue_slots[6].in_uop.bits.is_rocc connect slots_6.io.in_uop.bits.is_sys_pc2epc, issue_slots[6].in_uop.bits.is_sys_pc2epc connect slots_6.io.in_uop.bits.is_eret, issue_slots[6].in_uop.bits.is_eret connect slots_6.io.in_uop.bits.is_amo, issue_slots[6].in_uop.bits.is_amo connect slots_6.io.in_uop.bits.is_sfence, issue_slots[6].in_uop.bits.is_sfence connect slots_6.io.in_uop.bits.is_fencei, issue_slots[6].in_uop.bits.is_fencei connect slots_6.io.in_uop.bits.is_fence, issue_slots[6].in_uop.bits.is_fence connect slots_6.io.in_uop.bits.is_sfb, issue_slots[6].in_uop.bits.is_sfb connect slots_6.io.in_uop.bits.br_type, issue_slots[6].in_uop.bits.br_type connect slots_6.io.in_uop.bits.br_tag, issue_slots[6].in_uop.bits.br_tag connect slots_6.io.in_uop.bits.br_mask, issue_slots[6].in_uop.bits.br_mask connect slots_6.io.in_uop.bits.dis_col_sel, issue_slots[6].in_uop.bits.dis_col_sel connect slots_6.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[6].in_uop.bits.iw_p3_bypass_hint connect slots_6.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[6].in_uop.bits.iw_p2_bypass_hint connect slots_6.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[6].in_uop.bits.iw_p1_bypass_hint connect slots_6.io.in_uop.bits.iw_p2_speculative_child, issue_slots[6].in_uop.bits.iw_p2_speculative_child connect slots_6.io.in_uop.bits.iw_p1_speculative_child, issue_slots[6].in_uop.bits.iw_p1_speculative_child connect slots_6.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[6].in_uop.bits.iw_issued_partial_dgen connect slots_6.io.in_uop.bits.iw_issued_partial_agen, issue_slots[6].in_uop.bits.iw_issued_partial_agen connect slots_6.io.in_uop.bits.iw_issued, issue_slots[6].in_uop.bits.iw_issued connect slots_6.io.in_uop.bits.fu_code[0], issue_slots[6].in_uop.bits.fu_code[0] connect slots_6.io.in_uop.bits.fu_code[1], issue_slots[6].in_uop.bits.fu_code[1] connect slots_6.io.in_uop.bits.fu_code[2], issue_slots[6].in_uop.bits.fu_code[2] connect slots_6.io.in_uop.bits.fu_code[3], issue_slots[6].in_uop.bits.fu_code[3] connect slots_6.io.in_uop.bits.fu_code[4], issue_slots[6].in_uop.bits.fu_code[4] connect slots_6.io.in_uop.bits.fu_code[5], issue_slots[6].in_uop.bits.fu_code[5] connect slots_6.io.in_uop.bits.fu_code[6], issue_slots[6].in_uop.bits.fu_code[6] connect slots_6.io.in_uop.bits.fu_code[7], issue_slots[6].in_uop.bits.fu_code[7] connect slots_6.io.in_uop.bits.fu_code[8], issue_slots[6].in_uop.bits.fu_code[8] connect slots_6.io.in_uop.bits.fu_code[9], issue_slots[6].in_uop.bits.fu_code[9] connect slots_6.io.in_uop.bits.iq_type[0], issue_slots[6].in_uop.bits.iq_type[0] connect slots_6.io.in_uop.bits.iq_type[1], issue_slots[6].in_uop.bits.iq_type[1] connect slots_6.io.in_uop.bits.iq_type[2], issue_slots[6].in_uop.bits.iq_type[2] connect slots_6.io.in_uop.bits.iq_type[3], issue_slots[6].in_uop.bits.iq_type[3] connect slots_6.io.in_uop.bits.debug_pc, issue_slots[6].in_uop.bits.debug_pc connect slots_6.io.in_uop.bits.is_rvc, issue_slots[6].in_uop.bits.is_rvc connect slots_6.io.in_uop.bits.debug_inst, issue_slots[6].in_uop.bits.debug_inst connect slots_6.io.in_uop.bits.inst, issue_slots[6].in_uop.bits.inst connect slots_6.io.in_uop.valid, issue_slots[6].in_uop.valid connect issue_slots[6].iss_uop.debug_tsrc, slots_6.io.iss_uop.debug_tsrc connect issue_slots[6].iss_uop.debug_fsrc, slots_6.io.iss_uop.debug_fsrc connect issue_slots[6].iss_uop.bp_xcpt_if, slots_6.io.iss_uop.bp_xcpt_if connect issue_slots[6].iss_uop.bp_debug_if, slots_6.io.iss_uop.bp_debug_if connect issue_slots[6].iss_uop.xcpt_ma_if, slots_6.io.iss_uop.xcpt_ma_if connect issue_slots[6].iss_uop.xcpt_ae_if, slots_6.io.iss_uop.xcpt_ae_if connect issue_slots[6].iss_uop.xcpt_pf_if, slots_6.io.iss_uop.xcpt_pf_if connect issue_slots[6].iss_uop.fp_typ, slots_6.io.iss_uop.fp_typ connect issue_slots[6].iss_uop.fp_rm, slots_6.io.iss_uop.fp_rm connect issue_slots[6].iss_uop.fp_val, slots_6.io.iss_uop.fp_val connect issue_slots[6].iss_uop.fcn_op, slots_6.io.iss_uop.fcn_op connect issue_slots[6].iss_uop.fcn_dw, slots_6.io.iss_uop.fcn_dw connect issue_slots[6].iss_uop.frs3_en, slots_6.io.iss_uop.frs3_en connect issue_slots[6].iss_uop.lrs2_rtype, slots_6.io.iss_uop.lrs2_rtype connect issue_slots[6].iss_uop.lrs1_rtype, slots_6.io.iss_uop.lrs1_rtype connect issue_slots[6].iss_uop.dst_rtype, slots_6.io.iss_uop.dst_rtype connect issue_slots[6].iss_uop.lrs3, slots_6.io.iss_uop.lrs3 connect issue_slots[6].iss_uop.lrs2, slots_6.io.iss_uop.lrs2 connect issue_slots[6].iss_uop.lrs1, slots_6.io.iss_uop.lrs1 connect issue_slots[6].iss_uop.ldst, slots_6.io.iss_uop.ldst connect issue_slots[6].iss_uop.ldst_is_rs1, slots_6.io.iss_uop.ldst_is_rs1 connect issue_slots[6].iss_uop.csr_cmd, slots_6.io.iss_uop.csr_cmd connect issue_slots[6].iss_uop.flush_on_commit, slots_6.io.iss_uop.flush_on_commit connect issue_slots[6].iss_uop.is_unique, slots_6.io.iss_uop.is_unique connect issue_slots[6].iss_uop.uses_stq, slots_6.io.iss_uop.uses_stq connect issue_slots[6].iss_uop.uses_ldq, slots_6.io.iss_uop.uses_ldq connect issue_slots[6].iss_uop.mem_signed, slots_6.io.iss_uop.mem_signed connect issue_slots[6].iss_uop.mem_size, slots_6.io.iss_uop.mem_size connect issue_slots[6].iss_uop.mem_cmd, slots_6.io.iss_uop.mem_cmd connect issue_slots[6].iss_uop.exc_cause, slots_6.io.iss_uop.exc_cause connect issue_slots[6].iss_uop.exception, slots_6.io.iss_uop.exception connect issue_slots[6].iss_uop.stale_pdst, slots_6.io.iss_uop.stale_pdst connect issue_slots[6].iss_uop.ppred_busy, slots_6.io.iss_uop.ppred_busy connect issue_slots[6].iss_uop.prs3_busy, slots_6.io.iss_uop.prs3_busy connect issue_slots[6].iss_uop.prs2_busy, slots_6.io.iss_uop.prs2_busy connect issue_slots[6].iss_uop.prs1_busy, slots_6.io.iss_uop.prs1_busy connect issue_slots[6].iss_uop.ppred, slots_6.io.iss_uop.ppred connect issue_slots[6].iss_uop.prs3, slots_6.io.iss_uop.prs3 connect issue_slots[6].iss_uop.prs2, slots_6.io.iss_uop.prs2 connect issue_slots[6].iss_uop.prs1, slots_6.io.iss_uop.prs1 connect issue_slots[6].iss_uop.pdst, slots_6.io.iss_uop.pdst connect issue_slots[6].iss_uop.rxq_idx, slots_6.io.iss_uop.rxq_idx connect issue_slots[6].iss_uop.stq_idx, slots_6.io.iss_uop.stq_idx connect issue_slots[6].iss_uop.ldq_idx, slots_6.io.iss_uop.ldq_idx connect issue_slots[6].iss_uop.rob_idx, slots_6.io.iss_uop.rob_idx connect issue_slots[6].iss_uop.fp_ctrl.vec, slots_6.io.iss_uop.fp_ctrl.vec connect issue_slots[6].iss_uop.fp_ctrl.wflags, slots_6.io.iss_uop.fp_ctrl.wflags connect issue_slots[6].iss_uop.fp_ctrl.sqrt, slots_6.io.iss_uop.fp_ctrl.sqrt connect issue_slots[6].iss_uop.fp_ctrl.div, slots_6.io.iss_uop.fp_ctrl.div connect issue_slots[6].iss_uop.fp_ctrl.fma, slots_6.io.iss_uop.fp_ctrl.fma connect issue_slots[6].iss_uop.fp_ctrl.fastpipe, slots_6.io.iss_uop.fp_ctrl.fastpipe connect issue_slots[6].iss_uop.fp_ctrl.toint, slots_6.io.iss_uop.fp_ctrl.toint connect issue_slots[6].iss_uop.fp_ctrl.fromint, slots_6.io.iss_uop.fp_ctrl.fromint connect issue_slots[6].iss_uop.fp_ctrl.typeTagOut, slots_6.io.iss_uop.fp_ctrl.typeTagOut connect issue_slots[6].iss_uop.fp_ctrl.typeTagIn, slots_6.io.iss_uop.fp_ctrl.typeTagIn connect issue_slots[6].iss_uop.fp_ctrl.swap23, slots_6.io.iss_uop.fp_ctrl.swap23 connect issue_slots[6].iss_uop.fp_ctrl.swap12, slots_6.io.iss_uop.fp_ctrl.swap12 connect issue_slots[6].iss_uop.fp_ctrl.ren3, slots_6.io.iss_uop.fp_ctrl.ren3 connect issue_slots[6].iss_uop.fp_ctrl.ren2, slots_6.io.iss_uop.fp_ctrl.ren2 connect issue_slots[6].iss_uop.fp_ctrl.ren1, slots_6.io.iss_uop.fp_ctrl.ren1 connect issue_slots[6].iss_uop.fp_ctrl.wen, slots_6.io.iss_uop.fp_ctrl.wen connect issue_slots[6].iss_uop.fp_ctrl.ldst, slots_6.io.iss_uop.fp_ctrl.ldst connect issue_slots[6].iss_uop.op2_sel, slots_6.io.iss_uop.op2_sel connect issue_slots[6].iss_uop.op1_sel, slots_6.io.iss_uop.op1_sel connect issue_slots[6].iss_uop.imm_packed, slots_6.io.iss_uop.imm_packed connect issue_slots[6].iss_uop.pimm, slots_6.io.iss_uop.pimm connect issue_slots[6].iss_uop.imm_sel, slots_6.io.iss_uop.imm_sel connect issue_slots[6].iss_uop.imm_rename, slots_6.io.iss_uop.imm_rename connect issue_slots[6].iss_uop.taken, slots_6.io.iss_uop.taken connect issue_slots[6].iss_uop.pc_lob, slots_6.io.iss_uop.pc_lob connect issue_slots[6].iss_uop.edge_inst, slots_6.io.iss_uop.edge_inst connect issue_slots[6].iss_uop.ftq_idx, slots_6.io.iss_uop.ftq_idx connect issue_slots[6].iss_uop.is_mov, slots_6.io.iss_uop.is_mov connect issue_slots[6].iss_uop.is_rocc, slots_6.io.iss_uop.is_rocc connect issue_slots[6].iss_uop.is_sys_pc2epc, slots_6.io.iss_uop.is_sys_pc2epc connect issue_slots[6].iss_uop.is_eret, slots_6.io.iss_uop.is_eret connect issue_slots[6].iss_uop.is_amo, slots_6.io.iss_uop.is_amo connect issue_slots[6].iss_uop.is_sfence, slots_6.io.iss_uop.is_sfence connect issue_slots[6].iss_uop.is_fencei, slots_6.io.iss_uop.is_fencei connect issue_slots[6].iss_uop.is_fence, slots_6.io.iss_uop.is_fence connect issue_slots[6].iss_uop.is_sfb, slots_6.io.iss_uop.is_sfb connect issue_slots[6].iss_uop.br_type, slots_6.io.iss_uop.br_type connect issue_slots[6].iss_uop.br_tag, slots_6.io.iss_uop.br_tag connect issue_slots[6].iss_uop.br_mask, slots_6.io.iss_uop.br_mask connect issue_slots[6].iss_uop.dis_col_sel, slots_6.io.iss_uop.dis_col_sel connect issue_slots[6].iss_uop.iw_p3_bypass_hint, slots_6.io.iss_uop.iw_p3_bypass_hint connect issue_slots[6].iss_uop.iw_p2_bypass_hint, slots_6.io.iss_uop.iw_p2_bypass_hint connect issue_slots[6].iss_uop.iw_p1_bypass_hint, slots_6.io.iss_uop.iw_p1_bypass_hint connect issue_slots[6].iss_uop.iw_p2_speculative_child, slots_6.io.iss_uop.iw_p2_speculative_child connect issue_slots[6].iss_uop.iw_p1_speculative_child, slots_6.io.iss_uop.iw_p1_speculative_child connect issue_slots[6].iss_uop.iw_issued_partial_dgen, slots_6.io.iss_uop.iw_issued_partial_dgen connect issue_slots[6].iss_uop.iw_issued_partial_agen, slots_6.io.iss_uop.iw_issued_partial_agen connect issue_slots[6].iss_uop.iw_issued, slots_6.io.iss_uop.iw_issued connect issue_slots[6].iss_uop.fu_code[0], slots_6.io.iss_uop.fu_code[0] connect issue_slots[6].iss_uop.fu_code[1], slots_6.io.iss_uop.fu_code[1] connect issue_slots[6].iss_uop.fu_code[2], slots_6.io.iss_uop.fu_code[2] connect issue_slots[6].iss_uop.fu_code[3], slots_6.io.iss_uop.fu_code[3] connect issue_slots[6].iss_uop.fu_code[4], slots_6.io.iss_uop.fu_code[4] connect issue_slots[6].iss_uop.fu_code[5], slots_6.io.iss_uop.fu_code[5] connect issue_slots[6].iss_uop.fu_code[6], slots_6.io.iss_uop.fu_code[6] connect issue_slots[6].iss_uop.fu_code[7], slots_6.io.iss_uop.fu_code[7] connect issue_slots[6].iss_uop.fu_code[8], slots_6.io.iss_uop.fu_code[8] connect issue_slots[6].iss_uop.fu_code[9], slots_6.io.iss_uop.fu_code[9] connect issue_slots[6].iss_uop.iq_type[0], slots_6.io.iss_uop.iq_type[0] connect issue_slots[6].iss_uop.iq_type[1], slots_6.io.iss_uop.iq_type[1] connect issue_slots[6].iss_uop.iq_type[2], slots_6.io.iss_uop.iq_type[2] connect issue_slots[6].iss_uop.iq_type[3], slots_6.io.iss_uop.iq_type[3] connect issue_slots[6].iss_uop.debug_pc, slots_6.io.iss_uop.debug_pc connect issue_slots[6].iss_uop.is_rvc, slots_6.io.iss_uop.is_rvc connect issue_slots[6].iss_uop.debug_inst, slots_6.io.iss_uop.debug_inst connect issue_slots[6].iss_uop.inst, slots_6.io.iss_uop.inst connect slots_6.io.grant, issue_slots[6].grant connect issue_slots[6].request, slots_6.io.request connect issue_slots[6].will_be_valid, slots_6.io.will_be_valid connect issue_slots[6].valid, slots_6.io.valid connect slots_7.io.child_rebusys, issue_slots[7].child_rebusys connect slots_7.io.pred_wakeup_port.bits, issue_slots[7].pred_wakeup_port.bits connect slots_7.io.pred_wakeup_port.valid, issue_slots[7].pred_wakeup_port.valid connect slots_7.io.wakeup_ports[0].bits.rebusy, issue_slots[7].wakeup_ports[0].bits.rebusy connect slots_7.io.wakeup_ports[0].bits.speculative_mask, issue_slots[7].wakeup_ports[0].bits.speculative_mask connect slots_7.io.wakeup_ports[0].bits.bypassable, issue_slots[7].wakeup_ports[0].bits.bypassable connect slots_7.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[7].wakeup_ports[0].bits.uop.debug_tsrc connect slots_7.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[7].wakeup_ports[0].bits.uop.debug_fsrc connect slots_7.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[7].wakeup_ports[0].bits.uop.bp_xcpt_if connect slots_7.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[7].wakeup_ports[0].bits.uop.bp_debug_if connect slots_7.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[7].wakeup_ports[0].bits.uop.xcpt_ma_if connect slots_7.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[7].wakeup_ports[0].bits.uop.xcpt_ae_if connect slots_7.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[7].wakeup_ports[0].bits.uop.xcpt_pf_if connect slots_7.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[7].wakeup_ports[0].bits.uop.fp_typ connect slots_7.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[7].wakeup_ports[0].bits.uop.fp_rm connect slots_7.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[7].wakeup_ports[0].bits.uop.fp_val connect slots_7.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[7].wakeup_ports[0].bits.uop.fcn_op connect slots_7.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[7].wakeup_ports[0].bits.uop.fcn_dw connect slots_7.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[7].wakeup_ports[0].bits.uop.frs3_en connect slots_7.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[7].wakeup_ports[0].bits.uop.lrs2_rtype connect slots_7.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[7].wakeup_ports[0].bits.uop.lrs1_rtype connect slots_7.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[7].wakeup_ports[0].bits.uop.dst_rtype connect slots_7.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[7].wakeup_ports[0].bits.uop.lrs3 connect slots_7.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[7].wakeup_ports[0].bits.uop.lrs2 connect slots_7.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[7].wakeup_ports[0].bits.uop.lrs1 connect slots_7.io.wakeup_ports[0].bits.uop.ldst, issue_slots[7].wakeup_ports[0].bits.uop.ldst connect slots_7.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[7].wakeup_ports[0].bits.uop.ldst_is_rs1 connect slots_7.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[7].wakeup_ports[0].bits.uop.csr_cmd connect slots_7.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[7].wakeup_ports[0].bits.uop.flush_on_commit connect slots_7.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[7].wakeup_ports[0].bits.uop.is_unique connect slots_7.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[7].wakeup_ports[0].bits.uop.uses_stq connect slots_7.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[7].wakeup_ports[0].bits.uop.uses_ldq connect slots_7.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[7].wakeup_ports[0].bits.uop.mem_signed connect slots_7.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[7].wakeup_ports[0].bits.uop.mem_size connect slots_7.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[7].wakeup_ports[0].bits.uop.mem_cmd connect slots_7.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[7].wakeup_ports[0].bits.uop.exc_cause connect slots_7.io.wakeup_ports[0].bits.uop.exception, issue_slots[7].wakeup_ports[0].bits.uop.exception connect slots_7.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[7].wakeup_ports[0].bits.uop.stale_pdst connect slots_7.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[7].wakeup_ports[0].bits.uop.ppred_busy connect slots_7.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[7].wakeup_ports[0].bits.uop.prs3_busy connect slots_7.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[7].wakeup_ports[0].bits.uop.prs2_busy connect slots_7.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[7].wakeup_ports[0].bits.uop.prs1_busy connect slots_7.io.wakeup_ports[0].bits.uop.ppred, issue_slots[7].wakeup_ports[0].bits.uop.ppred connect slots_7.io.wakeup_ports[0].bits.uop.prs3, issue_slots[7].wakeup_ports[0].bits.uop.prs3 connect slots_7.io.wakeup_ports[0].bits.uop.prs2, issue_slots[7].wakeup_ports[0].bits.uop.prs2 connect slots_7.io.wakeup_ports[0].bits.uop.prs1, issue_slots[7].wakeup_ports[0].bits.uop.prs1 connect slots_7.io.wakeup_ports[0].bits.uop.pdst, issue_slots[7].wakeup_ports[0].bits.uop.pdst connect slots_7.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[7].wakeup_ports[0].bits.uop.rxq_idx connect slots_7.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[7].wakeup_ports[0].bits.uop.stq_idx connect slots_7.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[7].wakeup_ports[0].bits.uop.ldq_idx connect slots_7.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[7].wakeup_ports[0].bits.uop.rob_idx connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.vec connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.wflags connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.div connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.fma connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.toint connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.fromint connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.wen connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.ldst connect slots_7.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[7].wakeup_ports[0].bits.uop.op2_sel connect slots_7.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[7].wakeup_ports[0].bits.uop.op1_sel connect slots_7.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[7].wakeup_ports[0].bits.uop.imm_packed connect slots_7.io.wakeup_ports[0].bits.uop.pimm, issue_slots[7].wakeup_ports[0].bits.uop.pimm connect slots_7.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[7].wakeup_ports[0].bits.uop.imm_sel connect slots_7.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[7].wakeup_ports[0].bits.uop.imm_rename connect slots_7.io.wakeup_ports[0].bits.uop.taken, issue_slots[7].wakeup_ports[0].bits.uop.taken connect slots_7.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[7].wakeup_ports[0].bits.uop.pc_lob connect slots_7.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[7].wakeup_ports[0].bits.uop.edge_inst connect slots_7.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[7].wakeup_ports[0].bits.uop.ftq_idx connect slots_7.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[7].wakeup_ports[0].bits.uop.is_mov connect slots_7.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[7].wakeup_ports[0].bits.uop.is_rocc connect slots_7.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[7].wakeup_ports[0].bits.uop.is_sys_pc2epc connect slots_7.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[7].wakeup_ports[0].bits.uop.is_eret connect slots_7.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[7].wakeup_ports[0].bits.uop.is_amo connect slots_7.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[7].wakeup_ports[0].bits.uop.is_sfence connect slots_7.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[7].wakeup_ports[0].bits.uop.is_fencei connect slots_7.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[7].wakeup_ports[0].bits.uop.is_fence connect slots_7.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[7].wakeup_ports[0].bits.uop.is_sfb connect slots_7.io.wakeup_ports[0].bits.uop.br_type, issue_slots[7].wakeup_ports[0].bits.uop.br_type connect slots_7.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[7].wakeup_ports[0].bits.uop.br_tag connect slots_7.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[7].wakeup_ports[0].bits.uop.br_mask connect slots_7.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[7].wakeup_ports[0].bits.uop.dis_col_sel connect slots_7.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[7].wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect slots_7.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[7].wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect slots_7.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[7].wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect slots_7.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[7].wakeup_ports[0].bits.uop.iw_p2_speculative_child connect slots_7.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[7].wakeup_ports[0].bits.uop.iw_p1_speculative_child connect slots_7.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[7].wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect slots_7.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[7].wakeup_ports[0].bits.uop.iw_issued_partial_agen connect slots_7.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[7].wakeup_ports[0].bits.uop.iw_issued connect slots_7.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[7].wakeup_ports[0].bits.uop.fu_code[0] connect slots_7.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[7].wakeup_ports[0].bits.uop.fu_code[1] connect slots_7.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[7].wakeup_ports[0].bits.uop.fu_code[2] connect slots_7.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[7].wakeup_ports[0].bits.uop.fu_code[3] connect slots_7.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[7].wakeup_ports[0].bits.uop.fu_code[4] connect slots_7.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[7].wakeup_ports[0].bits.uop.fu_code[5] connect slots_7.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[7].wakeup_ports[0].bits.uop.fu_code[6] connect slots_7.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[7].wakeup_ports[0].bits.uop.fu_code[7] connect slots_7.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[7].wakeup_ports[0].bits.uop.fu_code[8] connect slots_7.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[7].wakeup_ports[0].bits.uop.fu_code[9] connect slots_7.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[7].wakeup_ports[0].bits.uop.iq_type[0] connect slots_7.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[7].wakeup_ports[0].bits.uop.iq_type[1] connect slots_7.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[7].wakeup_ports[0].bits.uop.iq_type[2] connect slots_7.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[7].wakeup_ports[0].bits.uop.iq_type[3] connect slots_7.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[7].wakeup_ports[0].bits.uop.debug_pc connect slots_7.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[7].wakeup_ports[0].bits.uop.is_rvc connect slots_7.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[7].wakeup_ports[0].bits.uop.debug_inst connect slots_7.io.wakeup_ports[0].bits.uop.inst, issue_slots[7].wakeup_ports[0].bits.uop.inst connect slots_7.io.wakeup_ports[0].valid, issue_slots[7].wakeup_ports[0].valid connect slots_7.io.wakeup_ports[1].bits.rebusy, issue_slots[7].wakeup_ports[1].bits.rebusy connect slots_7.io.wakeup_ports[1].bits.speculative_mask, issue_slots[7].wakeup_ports[1].bits.speculative_mask connect slots_7.io.wakeup_ports[1].bits.bypassable, issue_slots[7].wakeup_ports[1].bits.bypassable connect slots_7.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[7].wakeup_ports[1].bits.uop.debug_tsrc connect slots_7.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[7].wakeup_ports[1].bits.uop.debug_fsrc connect slots_7.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[7].wakeup_ports[1].bits.uop.bp_xcpt_if connect slots_7.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[7].wakeup_ports[1].bits.uop.bp_debug_if connect slots_7.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[7].wakeup_ports[1].bits.uop.xcpt_ma_if connect slots_7.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[7].wakeup_ports[1].bits.uop.xcpt_ae_if connect slots_7.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[7].wakeup_ports[1].bits.uop.xcpt_pf_if connect slots_7.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[7].wakeup_ports[1].bits.uop.fp_typ connect slots_7.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[7].wakeup_ports[1].bits.uop.fp_rm connect slots_7.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[7].wakeup_ports[1].bits.uop.fp_val connect slots_7.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[7].wakeup_ports[1].bits.uop.fcn_op connect slots_7.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[7].wakeup_ports[1].bits.uop.fcn_dw connect slots_7.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[7].wakeup_ports[1].bits.uop.frs3_en connect slots_7.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[7].wakeup_ports[1].bits.uop.lrs2_rtype connect slots_7.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[7].wakeup_ports[1].bits.uop.lrs1_rtype connect slots_7.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[7].wakeup_ports[1].bits.uop.dst_rtype connect slots_7.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[7].wakeup_ports[1].bits.uop.lrs3 connect slots_7.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[7].wakeup_ports[1].bits.uop.lrs2 connect slots_7.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[7].wakeup_ports[1].bits.uop.lrs1 connect slots_7.io.wakeup_ports[1].bits.uop.ldst, issue_slots[7].wakeup_ports[1].bits.uop.ldst connect slots_7.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[7].wakeup_ports[1].bits.uop.ldst_is_rs1 connect slots_7.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[7].wakeup_ports[1].bits.uop.csr_cmd connect slots_7.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[7].wakeup_ports[1].bits.uop.flush_on_commit connect slots_7.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[7].wakeup_ports[1].bits.uop.is_unique connect slots_7.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[7].wakeup_ports[1].bits.uop.uses_stq connect slots_7.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[7].wakeup_ports[1].bits.uop.uses_ldq connect slots_7.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[7].wakeup_ports[1].bits.uop.mem_signed connect slots_7.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[7].wakeup_ports[1].bits.uop.mem_size connect slots_7.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[7].wakeup_ports[1].bits.uop.mem_cmd connect slots_7.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[7].wakeup_ports[1].bits.uop.exc_cause connect slots_7.io.wakeup_ports[1].bits.uop.exception, issue_slots[7].wakeup_ports[1].bits.uop.exception connect slots_7.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[7].wakeup_ports[1].bits.uop.stale_pdst connect slots_7.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[7].wakeup_ports[1].bits.uop.ppred_busy connect slots_7.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[7].wakeup_ports[1].bits.uop.prs3_busy connect slots_7.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[7].wakeup_ports[1].bits.uop.prs2_busy connect slots_7.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[7].wakeup_ports[1].bits.uop.prs1_busy connect slots_7.io.wakeup_ports[1].bits.uop.ppred, issue_slots[7].wakeup_ports[1].bits.uop.ppred connect slots_7.io.wakeup_ports[1].bits.uop.prs3, issue_slots[7].wakeup_ports[1].bits.uop.prs3 connect slots_7.io.wakeup_ports[1].bits.uop.prs2, issue_slots[7].wakeup_ports[1].bits.uop.prs2 connect slots_7.io.wakeup_ports[1].bits.uop.prs1, issue_slots[7].wakeup_ports[1].bits.uop.prs1 connect slots_7.io.wakeup_ports[1].bits.uop.pdst, issue_slots[7].wakeup_ports[1].bits.uop.pdst connect slots_7.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[7].wakeup_ports[1].bits.uop.rxq_idx connect slots_7.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[7].wakeup_ports[1].bits.uop.stq_idx connect slots_7.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[7].wakeup_ports[1].bits.uop.ldq_idx connect slots_7.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[7].wakeup_ports[1].bits.uop.rob_idx connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.vec connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.wflags connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.div connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.fma connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.toint connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.fromint connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.wen connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.ldst connect slots_7.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[7].wakeup_ports[1].bits.uop.op2_sel connect slots_7.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[7].wakeup_ports[1].bits.uop.op1_sel connect slots_7.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[7].wakeup_ports[1].bits.uop.imm_packed connect slots_7.io.wakeup_ports[1].bits.uop.pimm, issue_slots[7].wakeup_ports[1].bits.uop.pimm connect slots_7.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[7].wakeup_ports[1].bits.uop.imm_sel connect slots_7.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[7].wakeup_ports[1].bits.uop.imm_rename connect slots_7.io.wakeup_ports[1].bits.uop.taken, issue_slots[7].wakeup_ports[1].bits.uop.taken connect slots_7.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[7].wakeup_ports[1].bits.uop.pc_lob connect slots_7.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[7].wakeup_ports[1].bits.uop.edge_inst connect slots_7.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[7].wakeup_ports[1].bits.uop.ftq_idx connect slots_7.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[7].wakeup_ports[1].bits.uop.is_mov connect slots_7.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[7].wakeup_ports[1].bits.uop.is_rocc connect slots_7.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[7].wakeup_ports[1].bits.uop.is_sys_pc2epc connect slots_7.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[7].wakeup_ports[1].bits.uop.is_eret connect slots_7.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[7].wakeup_ports[1].bits.uop.is_amo connect slots_7.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[7].wakeup_ports[1].bits.uop.is_sfence connect slots_7.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[7].wakeup_ports[1].bits.uop.is_fencei connect slots_7.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[7].wakeup_ports[1].bits.uop.is_fence connect slots_7.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[7].wakeup_ports[1].bits.uop.is_sfb connect slots_7.io.wakeup_ports[1].bits.uop.br_type, issue_slots[7].wakeup_ports[1].bits.uop.br_type connect slots_7.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[7].wakeup_ports[1].bits.uop.br_tag connect slots_7.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[7].wakeup_ports[1].bits.uop.br_mask connect slots_7.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[7].wakeup_ports[1].bits.uop.dis_col_sel connect slots_7.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[7].wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect slots_7.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[7].wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect slots_7.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[7].wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect slots_7.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[7].wakeup_ports[1].bits.uop.iw_p2_speculative_child connect slots_7.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[7].wakeup_ports[1].bits.uop.iw_p1_speculative_child connect slots_7.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[7].wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect slots_7.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[7].wakeup_ports[1].bits.uop.iw_issued_partial_agen connect slots_7.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[7].wakeup_ports[1].bits.uop.iw_issued connect slots_7.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[7].wakeup_ports[1].bits.uop.fu_code[0] connect slots_7.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[7].wakeup_ports[1].bits.uop.fu_code[1] connect slots_7.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[7].wakeup_ports[1].bits.uop.fu_code[2] connect slots_7.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[7].wakeup_ports[1].bits.uop.fu_code[3] connect slots_7.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[7].wakeup_ports[1].bits.uop.fu_code[4] connect slots_7.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[7].wakeup_ports[1].bits.uop.fu_code[5] connect slots_7.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[7].wakeup_ports[1].bits.uop.fu_code[6] connect slots_7.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[7].wakeup_ports[1].bits.uop.fu_code[7] connect slots_7.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[7].wakeup_ports[1].bits.uop.fu_code[8] connect slots_7.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[7].wakeup_ports[1].bits.uop.fu_code[9] connect slots_7.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[7].wakeup_ports[1].bits.uop.iq_type[0] connect slots_7.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[7].wakeup_ports[1].bits.uop.iq_type[1] connect slots_7.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[7].wakeup_ports[1].bits.uop.iq_type[2] connect slots_7.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[7].wakeup_ports[1].bits.uop.iq_type[3] connect slots_7.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[7].wakeup_ports[1].bits.uop.debug_pc connect slots_7.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[7].wakeup_ports[1].bits.uop.is_rvc connect slots_7.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[7].wakeup_ports[1].bits.uop.debug_inst connect slots_7.io.wakeup_ports[1].bits.uop.inst, issue_slots[7].wakeup_ports[1].bits.uop.inst connect slots_7.io.wakeup_ports[1].valid, issue_slots[7].wakeup_ports[1].valid connect slots_7.io.wakeup_ports[2].bits.rebusy, issue_slots[7].wakeup_ports[2].bits.rebusy connect slots_7.io.wakeup_ports[2].bits.speculative_mask, issue_slots[7].wakeup_ports[2].bits.speculative_mask connect slots_7.io.wakeup_ports[2].bits.bypassable, issue_slots[7].wakeup_ports[2].bits.bypassable connect slots_7.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[7].wakeup_ports[2].bits.uop.debug_tsrc connect slots_7.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[7].wakeup_ports[2].bits.uop.debug_fsrc connect slots_7.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[7].wakeup_ports[2].bits.uop.bp_xcpt_if connect slots_7.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[7].wakeup_ports[2].bits.uop.bp_debug_if connect slots_7.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[7].wakeup_ports[2].bits.uop.xcpt_ma_if connect slots_7.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[7].wakeup_ports[2].bits.uop.xcpt_ae_if connect slots_7.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[7].wakeup_ports[2].bits.uop.xcpt_pf_if connect slots_7.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[7].wakeup_ports[2].bits.uop.fp_typ connect slots_7.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[7].wakeup_ports[2].bits.uop.fp_rm connect slots_7.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[7].wakeup_ports[2].bits.uop.fp_val connect slots_7.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[7].wakeup_ports[2].bits.uop.fcn_op connect slots_7.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[7].wakeup_ports[2].bits.uop.fcn_dw connect slots_7.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[7].wakeup_ports[2].bits.uop.frs3_en connect slots_7.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[7].wakeup_ports[2].bits.uop.lrs2_rtype connect slots_7.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[7].wakeup_ports[2].bits.uop.lrs1_rtype connect slots_7.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[7].wakeup_ports[2].bits.uop.dst_rtype connect slots_7.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[7].wakeup_ports[2].bits.uop.lrs3 connect slots_7.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[7].wakeup_ports[2].bits.uop.lrs2 connect slots_7.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[7].wakeup_ports[2].bits.uop.lrs1 connect slots_7.io.wakeup_ports[2].bits.uop.ldst, issue_slots[7].wakeup_ports[2].bits.uop.ldst connect slots_7.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[7].wakeup_ports[2].bits.uop.ldst_is_rs1 connect slots_7.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[7].wakeup_ports[2].bits.uop.csr_cmd connect slots_7.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[7].wakeup_ports[2].bits.uop.flush_on_commit connect slots_7.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[7].wakeup_ports[2].bits.uop.is_unique connect slots_7.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[7].wakeup_ports[2].bits.uop.uses_stq connect slots_7.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[7].wakeup_ports[2].bits.uop.uses_ldq connect slots_7.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[7].wakeup_ports[2].bits.uop.mem_signed connect slots_7.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[7].wakeup_ports[2].bits.uop.mem_size connect slots_7.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[7].wakeup_ports[2].bits.uop.mem_cmd connect slots_7.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[7].wakeup_ports[2].bits.uop.exc_cause connect slots_7.io.wakeup_ports[2].bits.uop.exception, issue_slots[7].wakeup_ports[2].bits.uop.exception connect slots_7.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[7].wakeup_ports[2].bits.uop.stale_pdst connect slots_7.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[7].wakeup_ports[2].bits.uop.ppred_busy connect slots_7.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[7].wakeup_ports[2].bits.uop.prs3_busy connect slots_7.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[7].wakeup_ports[2].bits.uop.prs2_busy connect slots_7.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[7].wakeup_ports[2].bits.uop.prs1_busy connect slots_7.io.wakeup_ports[2].bits.uop.ppred, issue_slots[7].wakeup_ports[2].bits.uop.ppred connect slots_7.io.wakeup_ports[2].bits.uop.prs3, issue_slots[7].wakeup_ports[2].bits.uop.prs3 connect slots_7.io.wakeup_ports[2].bits.uop.prs2, issue_slots[7].wakeup_ports[2].bits.uop.prs2 connect slots_7.io.wakeup_ports[2].bits.uop.prs1, issue_slots[7].wakeup_ports[2].bits.uop.prs1 connect slots_7.io.wakeup_ports[2].bits.uop.pdst, issue_slots[7].wakeup_ports[2].bits.uop.pdst connect slots_7.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[7].wakeup_ports[2].bits.uop.rxq_idx connect slots_7.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[7].wakeup_ports[2].bits.uop.stq_idx connect slots_7.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[7].wakeup_ports[2].bits.uop.ldq_idx connect slots_7.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[7].wakeup_ports[2].bits.uop.rob_idx connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.vec connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.wflags connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.div connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.fma connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.toint connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.fromint connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.wen connect slots_7.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.ldst connect slots_7.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[7].wakeup_ports[2].bits.uop.op2_sel connect slots_7.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[7].wakeup_ports[2].bits.uop.op1_sel connect slots_7.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[7].wakeup_ports[2].bits.uop.imm_packed connect slots_7.io.wakeup_ports[2].bits.uop.pimm, issue_slots[7].wakeup_ports[2].bits.uop.pimm connect slots_7.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[7].wakeup_ports[2].bits.uop.imm_sel connect slots_7.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[7].wakeup_ports[2].bits.uop.imm_rename connect slots_7.io.wakeup_ports[2].bits.uop.taken, issue_slots[7].wakeup_ports[2].bits.uop.taken connect slots_7.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[7].wakeup_ports[2].bits.uop.pc_lob connect slots_7.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[7].wakeup_ports[2].bits.uop.edge_inst connect slots_7.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[7].wakeup_ports[2].bits.uop.ftq_idx connect slots_7.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[7].wakeup_ports[2].bits.uop.is_mov connect slots_7.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[7].wakeup_ports[2].bits.uop.is_rocc connect slots_7.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[7].wakeup_ports[2].bits.uop.is_sys_pc2epc connect slots_7.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[7].wakeup_ports[2].bits.uop.is_eret connect slots_7.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[7].wakeup_ports[2].bits.uop.is_amo connect slots_7.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[7].wakeup_ports[2].bits.uop.is_sfence connect slots_7.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[7].wakeup_ports[2].bits.uop.is_fencei connect slots_7.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[7].wakeup_ports[2].bits.uop.is_fence connect slots_7.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[7].wakeup_ports[2].bits.uop.is_sfb connect slots_7.io.wakeup_ports[2].bits.uop.br_type, issue_slots[7].wakeup_ports[2].bits.uop.br_type connect slots_7.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[7].wakeup_ports[2].bits.uop.br_tag connect slots_7.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[7].wakeup_ports[2].bits.uop.br_mask connect slots_7.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[7].wakeup_ports[2].bits.uop.dis_col_sel connect slots_7.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[7].wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect slots_7.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[7].wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect slots_7.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[7].wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect slots_7.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[7].wakeup_ports[2].bits.uop.iw_p2_speculative_child connect slots_7.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[7].wakeup_ports[2].bits.uop.iw_p1_speculative_child connect slots_7.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[7].wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect slots_7.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[7].wakeup_ports[2].bits.uop.iw_issued_partial_agen connect slots_7.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[7].wakeup_ports[2].bits.uop.iw_issued connect slots_7.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[7].wakeup_ports[2].bits.uop.fu_code[0] connect slots_7.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[7].wakeup_ports[2].bits.uop.fu_code[1] connect slots_7.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[7].wakeup_ports[2].bits.uop.fu_code[2] connect slots_7.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[7].wakeup_ports[2].bits.uop.fu_code[3] connect slots_7.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[7].wakeup_ports[2].bits.uop.fu_code[4] connect slots_7.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[7].wakeup_ports[2].bits.uop.fu_code[5] connect slots_7.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[7].wakeup_ports[2].bits.uop.fu_code[6] connect slots_7.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[7].wakeup_ports[2].bits.uop.fu_code[7] connect slots_7.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[7].wakeup_ports[2].bits.uop.fu_code[8] connect slots_7.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[7].wakeup_ports[2].bits.uop.fu_code[9] connect slots_7.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[7].wakeup_ports[2].bits.uop.iq_type[0] connect slots_7.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[7].wakeup_ports[2].bits.uop.iq_type[1] connect slots_7.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[7].wakeup_ports[2].bits.uop.iq_type[2] connect slots_7.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[7].wakeup_ports[2].bits.uop.iq_type[3] connect slots_7.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[7].wakeup_ports[2].bits.uop.debug_pc connect slots_7.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[7].wakeup_ports[2].bits.uop.is_rvc connect slots_7.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[7].wakeup_ports[2].bits.uop.debug_inst connect slots_7.io.wakeup_ports[2].bits.uop.inst, issue_slots[7].wakeup_ports[2].bits.uop.inst connect slots_7.io.wakeup_ports[2].valid, issue_slots[7].wakeup_ports[2].valid connect slots_7.io.wakeup_ports[3].bits.rebusy, issue_slots[7].wakeup_ports[3].bits.rebusy connect slots_7.io.wakeup_ports[3].bits.speculative_mask, issue_slots[7].wakeup_ports[3].bits.speculative_mask connect slots_7.io.wakeup_ports[3].bits.bypassable, issue_slots[7].wakeup_ports[3].bits.bypassable connect slots_7.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[7].wakeup_ports[3].bits.uop.debug_tsrc connect slots_7.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[7].wakeup_ports[3].bits.uop.debug_fsrc connect slots_7.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[7].wakeup_ports[3].bits.uop.bp_xcpt_if connect slots_7.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[7].wakeup_ports[3].bits.uop.bp_debug_if connect slots_7.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[7].wakeup_ports[3].bits.uop.xcpt_ma_if connect slots_7.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[7].wakeup_ports[3].bits.uop.xcpt_ae_if connect slots_7.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[7].wakeup_ports[3].bits.uop.xcpt_pf_if connect slots_7.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[7].wakeup_ports[3].bits.uop.fp_typ connect slots_7.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[7].wakeup_ports[3].bits.uop.fp_rm connect slots_7.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[7].wakeup_ports[3].bits.uop.fp_val connect slots_7.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[7].wakeup_ports[3].bits.uop.fcn_op connect slots_7.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[7].wakeup_ports[3].bits.uop.fcn_dw connect slots_7.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[7].wakeup_ports[3].bits.uop.frs3_en connect slots_7.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[7].wakeup_ports[3].bits.uop.lrs2_rtype connect slots_7.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[7].wakeup_ports[3].bits.uop.lrs1_rtype connect slots_7.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[7].wakeup_ports[3].bits.uop.dst_rtype connect slots_7.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[7].wakeup_ports[3].bits.uop.lrs3 connect slots_7.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[7].wakeup_ports[3].bits.uop.lrs2 connect slots_7.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[7].wakeup_ports[3].bits.uop.lrs1 connect slots_7.io.wakeup_ports[3].bits.uop.ldst, issue_slots[7].wakeup_ports[3].bits.uop.ldst connect slots_7.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[7].wakeup_ports[3].bits.uop.ldst_is_rs1 connect slots_7.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[7].wakeup_ports[3].bits.uop.csr_cmd connect slots_7.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[7].wakeup_ports[3].bits.uop.flush_on_commit connect slots_7.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[7].wakeup_ports[3].bits.uop.is_unique connect slots_7.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[7].wakeup_ports[3].bits.uop.uses_stq connect slots_7.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[7].wakeup_ports[3].bits.uop.uses_ldq connect slots_7.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[7].wakeup_ports[3].bits.uop.mem_signed connect slots_7.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[7].wakeup_ports[3].bits.uop.mem_size connect slots_7.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[7].wakeup_ports[3].bits.uop.mem_cmd connect slots_7.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[7].wakeup_ports[3].bits.uop.exc_cause connect slots_7.io.wakeup_ports[3].bits.uop.exception, issue_slots[7].wakeup_ports[3].bits.uop.exception connect slots_7.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[7].wakeup_ports[3].bits.uop.stale_pdst connect slots_7.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[7].wakeup_ports[3].bits.uop.ppred_busy connect slots_7.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[7].wakeup_ports[3].bits.uop.prs3_busy connect slots_7.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[7].wakeup_ports[3].bits.uop.prs2_busy connect slots_7.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[7].wakeup_ports[3].bits.uop.prs1_busy connect slots_7.io.wakeup_ports[3].bits.uop.ppred, issue_slots[7].wakeup_ports[3].bits.uop.ppred connect slots_7.io.wakeup_ports[3].bits.uop.prs3, issue_slots[7].wakeup_ports[3].bits.uop.prs3 connect slots_7.io.wakeup_ports[3].bits.uop.prs2, issue_slots[7].wakeup_ports[3].bits.uop.prs2 connect slots_7.io.wakeup_ports[3].bits.uop.prs1, issue_slots[7].wakeup_ports[3].bits.uop.prs1 connect slots_7.io.wakeup_ports[3].bits.uop.pdst, issue_slots[7].wakeup_ports[3].bits.uop.pdst connect slots_7.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[7].wakeup_ports[3].bits.uop.rxq_idx connect slots_7.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[7].wakeup_ports[3].bits.uop.stq_idx connect slots_7.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[7].wakeup_ports[3].bits.uop.ldq_idx connect slots_7.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[7].wakeup_ports[3].bits.uop.rob_idx connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.vec connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.wflags connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.div connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.fma connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.toint connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.fromint connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.wen connect slots_7.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.ldst connect slots_7.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[7].wakeup_ports[3].bits.uop.op2_sel connect slots_7.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[7].wakeup_ports[3].bits.uop.op1_sel connect slots_7.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[7].wakeup_ports[3].bits.uop.imm_packed connect slots_7.io.wakeup_ports[3].bits.uop.pimm, issue_slots[7].wakeup_ports[3].bits.uop.pimm connect slots_7.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[7].wakeup_ports[3].bits.uop.imm_sel connect slots_7.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[7].wakeup_ports[3].bits.uop.imm_rename connect slots_7.io.wakeup_ports[3].bits.uop.taken, issue_slots[7].wakeup_ports[3].bits.uop.taken connect slots_7.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[7].wakeup_ports[3].bits.uop.pc_lob connect slots_7.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[7].wakeup_ports[3].bits.uop.edge_inst connect slots_7.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[7].wakeup_ports[3].bits.uop.ftq_idx connect slots_7.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[7].wakeup_ports[3].bits.uop.is_mov connect slots_7.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[7].wakeup_ports[3].bits.uop.is_rocc connect slots_7.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[7].wakeup_ports[3].bits.uop.is_sys_pc2epc connect slots_7.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[7].wakeup_ports[3].bits.uop.is_eret connect slots_7.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[7].wakeup_ports[3].bits.uop.is_amo connect slots_7.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[7].wakeup_ports[3].bits.uop.is_sfence connect slots_7.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[7].wakeup_ports[3].bits.uop.is_fencei connect slots_7.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[7].wakeup_ports[3].bits.uop.is_fence connect slots_7.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[7].wakeup_ports[3].bits.uop.is_sfb connect slots_7.io.wakeup_ports[3].bits.uop.br_type, issue_slots[7].wakeup_ports[3].bits.uop.br_type connect slots_7.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[7].wakeup_ports[3].bits.uop.br_tag connect slots_7.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[7].wakeup_ports[3].bits.uop.br_mask connect slots_7.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[7].wakeup_ports[3].bits.uop.dis_col_sel connect slots_7.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[7].wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect slots_7.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[7].wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect slots_7.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[7].wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect slots_7.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[7].wakeup_ports[3].bits.uop.iw_p2_speculative_child connect slots_7.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[7].wakeup_ports[3].bits.uop.iw_p1_speculative_child connect slots_7.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[7].wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect slots_7.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[7].wakeup_ports[3].bits.uop.iw_issued_partial_agen connect slots_7.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[7].wakeup_ports[3].bits.uop.iw_issued connect slots_7.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[7].wakeup_ports[3].bits.uop.fu_code[0] connect slots_7.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[7].wakeup_ports[3].bits.uop.fu_code[1] connect slots_7.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[7].wakeup_ports[3].bits.uop.fu_code[2] connect slots_7.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[7].wakeup_ports[3].bits.uop.fu_code[3] connect slots_7.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[7].wakeup_ports[3].bits.uop.fu_code[4] connect slots_7.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[7].wakeup_ports[3].bits.uop.fu_code[5] connect slots_7.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[7].wakeup_ports[3].bits.uop.fu_code[6] connect slots_7.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[7].wakeup_ports[3].bits.uop.fu_code[7] connect slots_7.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[7].wakeup_ports[3].bits.uop.fu_code[8] connect slots_7.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[7].wakeup_ports[3].bits.uop.fu_code[9] connect slots_7.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[7].wakeup_ports[3].bits.uop.iq_type[0] connect slots_7.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[7].wakeup_ports[3].bits.uop.iq_type[1] connect slots_7.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[7].wakeup_ports[3].bits.uop.iq_type[2] connect slots_7.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[7].wakeup_ports[3].bits.uop.iq_type[3] connect slots_7.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[7].wakeup_ports[3].bits.uop.debug_pc connect slots_7.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[7].wakeup_ports[3].bits.uop.is_rvc connect slots_7.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[7].wakeup_ports[3].bits.uop.debug_inst connect slots_7.io.wakeup_ports[3].bits.uop.inst, issue_slots[7].wakeup_ports[3].bits.uop.inst connect slots_7.io.wakeup_ports[3].valid, issue_slots[7].wakeup_ports[3].valid connect slots_7.io.wakeup_ports[4].bits.rebusy, issue_slots[7].wakeup_ports[4].bits.rebusy connect slots_7.io.wakeup_ports[4].bits.speculative_mask, issue_slots[7].wakeup_ports[4].bits.speculative_mask connect slots_7.io.wakeup_ports[4].bits.bypassable, issue_slots[7].wakeup_ports[4].bits.bypassable connect slots_7.io.wakeup_ports[4].bits.uop.debug_tsrc, issue_slots[7].wakeup_ports[4].bits.uop.debug_tsrc connect slots_7.io.wakeup_ports[4].bits.uop.debug_fsrc, issue_slots[7].wakeup_ports[4].bits.uop.debug_fsrc connect slots_7.io.wakeup_ports[4].bits.uop.bp_xcpt_if, issue_slots[7].wakeup_ports[4].bits.uop.bp_xcpt_if connect slots_7.io.wakeup_ports[4].bits.uop.bp_debug_if, issue_slots[7].wakeup_ports[4].bits.uop.bp_debug_if connect slots_7.io.wakeup_ports[4].bits.uop.xcpt_ma_if, issue_slots[7].wakeup_ports[4].bits.uop.xcpt_ma_if connect slots_7.io.wakeup_ports[4].bits.uop.xcpt_ae_if, issue_slots[7].wakeup_ports[4].bits.uop.xcpt_ae_if connect slots_7.io.wakeup_ports[4].bits.uop.xcpt_pf_if, issue_slots[7].wakeup_ports[4].bits.uop.xcpt_pf_if connect slots_7.io.wakeup_ports[4].bits.uop.fp_typ, issue_slots[7].wakeup_ports[4].bits.uop.fp_typ connect slots_7.io.wakeup_ports[4].bits.uop.fp_rm, issue_slots[7].wakeup_ports[4].bits.uop.fp_rm connect slots_7.io.wakeup_ports[4].bits.uop.fp_val, issue_slots[7].wakeup_ports[4].bits.uop.fp_val connect slots_7.io.wakeup_ports[4].bits.uop.fcn_op, issue_slots[7].wakeup_ports[4].bits.uop.fcn_op connect slots_7.io.wakeup_ports[4].bits.uop.fcn_dw, issue_slots[7].wakeup_ports[4].bits.uop.fcn_dw connect slots_7.io.wakeup_ports[4].bits.uop.frs3_en, issue_slots[7].wakeup_ports[4].bits.uop.frs3_en connect slots_7.io.wakeup_ports[4].bits.uop.lrs2_rtype, issue_slots[7].wakeup_ports[4].bits.uop.lrs2_rtype connect slots_7.io.wakeup_ports[4].bits.uop.lrs1_rtype, issue_slots[7].wakeup_ports[4].bits.uop.lrs1_rtype connect slots_7.io.wakeup_ports[4].bits.uop.dst_rtype, issue_slots[7].wakeup_ports[4].bits.uop.dst_rtype connect slots_7.io.wakeup_ports[4].bits.uop.lrs3, issue_slots[7].wakeup_ports[4].bits.uop.lrs3 connect slots_7.io.wakeup_ports[4].bits.uop.lrs2, issue_slots[7].wakeup_ports[4].bits.uop.lrs2 connect slots_7.io.wakeup_ports[4].bits.uop.lrs1, issue_slots[7].wakeup_ports[4].bits.uop.lrs1 connect slots_7.io.wakeup_ports[4].bits.uop.ldst, issue_slots[7].wakeup_ports[4].bits.uop.ldst connect slots_7.io.wakeup_ports[4].bits.uop.ldst_is_rs1, issue_slots[7].wakeup_ports[4].bits.uop.ldst_is_rs1 connect slots_7.io.wakeup_ports[4].bits.uop.csr_cmd, issue_slots[7].wakeup_ports[4].bits.uop.csr_cmd connect slots_7.io.wakeup_ports[4].bits.uop.flush_on_commit, issue_slots[7].wakeup_ports[4].bits.uop.flush_on_commit connect slots_7.io.wakeup_ports[4].bits.uop.is_unique, issue_slots[7].wakeup_ports[4].bits.uop.is_unique connect slots_7.io.wakeup_ports[4].bits.uop.uses_stq, issue_slots[7].wakeup_ports[4].bits.uop.uses_stq connect slots_7.io.wakeup_ports[4].bits.uop.uses_ldq, issue_slots[7].wakeup_ports[4].bits.uop.uses_ldq connect slots_7.io.wakeup_ports[4].bits.uop.mem_signed, issue_slots[7].wakeup_ports[4].bits.uop.mem_signed connect slots_7.io.wakeup_ports[4].bits.uop.mem_size, issue_slots[7].wakeup_ports[4].bits.uop.mem_size connect slots_7.io.wakeup_ports[4].bits.uop.mem_cmd, issue_slots[7].wakeup_ports[4].bits.uop.mem_cmd connect slots_7.io.wakeup_ports[4].bits.uop.exc_cause, issue_slots[7].wakeup_ports[4].bits.uop.exc_cause connect slots_7.io.wakeup_ports[4].bits.uop.exception, issue_slots[7].wakeup_ports[4].bits.uop.exception connect slots_7.io.wakeup_ports[4].bits.uop.stale_pdst, issue_slots[7].wakeup_ports[4].bits.uop.stale_pdst connect slots_7.io.wakeup_ports[4].bits.uop.ppred_busy, issue_slots[7].wakeup_ports[4].bits.uop.ppred_busy connect slots_7.io.wakeup_ports[4].bits.uop.prs3_busy, issue_slots[7].wakeup_ports[4].bits.uop.prs3_busy connect slots_7.io.wakeup_ports[4].bits.uop.prs2_busy, issue_slots[7].wakeup_ports[4].bits.uop.prs2_busy connect slots_7.io.wakeup_ports[4].bits.uop.prs1_busy, issue_slots[7].wakeup_ports[4].bits.uop.prs1_busy connect slots_7.io.wakeup_ports[4].bits.uop.ppred, issue_slots[7].wakeup_ports[4].bits.uop.ppred connect slots_7.io.wakeup_ports[4].bits.uop.prs3, issue_slots[7].wakeup_ports[4].bits.uop.prs3 connect slots_7.io.wakeup_ports[4].bits.uop.prs2, issue_slots[7].wakeup_ports[4].bits.uop.prs2 connect slots_7.io.wakeup_ports[4].bits.uop.prs1, issue_slots[7].wakeup_ports[4].bits.uop.prs1 connect slots_7.io.wakeup_ports[4].bits.uop.pdst, issue_slots[7].wakeup_ports[4].bits.uop.pdst connect slots_7.io.wakeup_ports[4].bits.uop.rxq_idx, issue_slots[7].wakeup_ports[4].bits.uop.rxq_idx connect slots_7.io.wakeup_ports[4].bits.uop.stq_idx, issue_slots[7].wakeup_ports[4].bits.uop.stq_idx connect slots_7.io.wakeup_ports[4].bits.uop.ldq_idx, issue_slots[7].wakeup_ports[4].bits.uop.ldq_idx connect slots_7.io.wakeup_ports[4].bits.uop.rob_idx, issue_slots[7].wakeup_ports[4].bits.uop.rob_idx connect slots_7.io.wakeup_ports[4].bits.uop.fp_ctrl.vec, issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.vec connect slots_7.io.wakeup_ports[4].bits.uop.fp_ctrl.wflags, issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.wflags connect slots_7.io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt, issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect slots_7.io.wakeup_ports[4].bits.uop.fp_ctrl.div, issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.div connect slots_7.io.wakeup_ports[4].bits.uop.fp_ctrl.fma, issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.fma connect slots_7.io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect slots_7.io.wakeup_ports[4].bits.uop.fp_ctrl.toint, issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.toint connect slots_7.io.wakeup_ports[4].bits.uop.fp_ctrl.fromint, issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.fromint connect slots_7.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect slots_7.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect slots_7.io.wakeup_ports[4].bits.uop.fp_ctrl.swap23, issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect slots_7.io.wakeup_ports[4].bits.uop.fp_ctrl.swap12, issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect slots_7.io.wakeup_ports[4].bits.uop.fp_ctrl.ren3, issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect slots_7.io.wakeup_ports[4].bits.uop.fp_ctrl.ren2, issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect slots_7.io.wakeup_ports[4].bits.uop.fp_ctrl.ren1, issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect slots_7.io.wakeup_ports[4].bits.uop.fp_ctrl.wen, issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.wen connect slots_7.io.wakeup_ports[4].bits.uop.fp_ctrl.ldst, issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.ldst connect slots_7.io.wakeup_ports[4].bits.uop.op2_sel, issue_slots[7].wakeup_ports[4].bits.uop.op2_sel connect slots_7.io.wakeup_ports[4].bits.uop.op1_sel, issue_slots[7].wakeup_ports[4].bits.uop.op1_sel connect slots_7.io.wakeup_ports[4].bits.uop.imm_packed, issue_slots[7].wakeup_ports[4].bits.uop.imm_packed connect slots_7.io.wakeup_ports[4].bits.uop.pimm, issue_slots[7].wakeup_ports[4].bits.uop.pimm connect slots_7.io.wakeup_ports[4].bits.uop.imm_sel, issue_slots[7].wakeup_ports[4].bits.uop.imm_sel connect slots_7.io.wakeup_ports[4].bits.uop.imm_rename, issue_slots[7].wakeup_ports[4].bits.uop.imm_rename connect slots_7.io.wakeup_ports[4].bits.uop.taken, issue_slots[7].wakeup_ports[4].bits.uop.taken connect slots_7.io.wakeup_ports[4].bits.uop.pc_lob, issue_slots[7].wakeup_ports[4].bits.uop.pc_lob connect slots_7.io.wakeup_ports[4].bits.uop.edge_inst, issue_slots[7].wakeup_ports[4].bits.uop.edge_inst connect slots_7.io.wakeup_ports[4].bits.uop.ftq_idx, issue_slots[7].wakeup_ports[4].bits.uop.ftq_idx connect slots_7.io.wakeup_ports[4].bits.uop.is_mov, issue_slots[7].wakeup_ports[4].bits.uop.is_mov connect slots_7.io.wakeup_ports[4].bits.uop.is_rocc, issue_slots[7].wakeup_ports[4].bits.uop.is_rocc connect slots_7.io.wakeup_ports[4].bits.uop.is_sys_pc2epc, issue_slots[7].wakeup_ports[4].bits.uop.is_sys_pc2epc connect slots_7.io.wakeup_ports[4].bits.uop.is_eret, issue_slots[7].wakeup_ports[4].bits.uop.is_eret connect slots_7.io.wakeup_ports[4].bits.uop.is_amo, issue_slots[7].wakeup_ports[4].bits.uop.is_amo connect slots_7.io.wakeup_ports[4].bits.uop.is_sfence, issue_slots[7].wakeup_ports[4].bits.uop.is_sfence connect slots_7.io.wakeup_ports[4].bits.uop.is_fencei, issue_slots[7].wakeup_ports[4].bits.uop.is_fencei connect slots_7.io.wakeup_ports[4].bits.uop.is_fence, issue_slots[7].wakeup_ports[4].bits.uop.is_fence connect slots_7.io.wakeup_ports[4].bits.uop.is_sfb, issue_slots[7].wakeup_ports[4].bits.uop.is_sfb connect slots_7.io.wakeup_ports[4].bits.uop.br_type, issue_slots[7].wakeup_ports[4].bits.uop.br_type connect slots_7.io.wakeup_ports[4].bits.uop.br_tag, issue_slots[7].wakeup_ports[4].bits.uop.br_tag connect slots_7.io.wakeup_ports[4].bits.uop.br_mask, issue_slots[7].wakeup_ports[4].bits.uop.br_mask connect slots_7.io.wakeup_ports[4].bits.uop.dis_col_sel, issue_slots[7].wakeup_ports[4].bits.uop.dis_col_sel connect slots_7.io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint, issue_slots[7].wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect slots_7.io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint, issue_slots[7].wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect slots_7.io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint, issue_slots[7].wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect slots_7.io.wakeup_ports[4].bits.uop.iw_p2_speculative_child, issue_slots[7].wakeup_ports[4].bits.uop.iw_p2_speculative_child connect slots_7.io.wakeup_ports[4].bits.uop.iw_p1_speculative_child, issue_slots[7].wakeup_ports[4].bits.uop.iw_p1_speculative_child connect slots_7.io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen, issue_slots[7].wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect slots_7.io.wakeup_ports[4].bits.uop.iw_issued_partial_agen, issue_slots[7].wakeup_ports[4].bits.uop.iw_issued_partial_agen connect slots_7.io.wakeup_ports[4].bits.uop.iw_issued, issue_slots[7].wakeup_ports[4].bits.uop.iw_issued connect slots_7.io.wakeup_ports[4].bits.uop.fu_code[0], issue_slots[7].wakeup_ports[4].bits.uop.fu_code[0] connect slots_7.io.wakeup_ports[4].bits.uop.fu_code[1], issue_slots[7].wakeup_ports[4].bits.uop.fu_code[1] connect slots_7.io.wakeup_ports[4].bits.uop.fu_code[2], issue_slots[7].wakeup_ports[4].bits.uop.fu_code[2] connect slots_7.io.wakeup_ports[4].bits.uop.fu_code[3], issue_slots[7].wakeup_ports[4].bits.uop.fu_code[3] connect slots_7.io.wakeup_ports[4].bits.uop.fu_code[4], issue_slots[7].wakeup_ports[4].bits.uop.fu_code[4] connect slots_7.io.wakeup_ports[4].bits.uop.fu_code[5], issue_slots[7].wakeup_ports[4].bits.uop.fu_code[5] connect slots_7.io.wakeup_ports[4].bits.uop.fu_code[6], issue_slots[7].wakeup_ports[4].bits.uop.fu_code[6] connect slots_7.io.wakeup_ports[4].bits.uop.fu_code[7], issue_slots[7].wakeup_ports[4].bits.uop.fu_code[7] connect slots_7.io.wakeup_ports[4].bits.uop.fu_code[8], issue_slots[7].wakeup_ports[4].bits.uop.fu_code[8] connect slots_7.io.wakeup_ports[4].bits.uop.fu_code[9], issue_slots[7].wakeup_ports[4].bits.uop.fu_code[9] connect slots_7.io.wakeup_ports[4].bits.uop.iq_type[0], issue_slots[7].wakeup_ports[4].bits.uop.iq_type[0] connect slots_7.io.wakeup_ports[4].bits.uop.iq_type[1], issue_slots[7].wakeup_ports[4].bits.uop.iq_type[1] connect slots_7.io.wakeup_ports[4].bits.uop.iq_type[2], issue_slots[7].wakeup_ports[4].bits.uop.iq_type[2] connect slots_7.io.wakeup_ports[4].bits.uop.iq_type[3], issue_slots[7].wakeup_ports[4].bits.uop.iq_type[3] connect slots_7.io.wakeup_ports[4].bits.uop.debug_pc, issue_slots[7].wakeup_ports[4].bits.uop.debug_pc connect slots_7.io.wakeup_ports[4].bits.uop.is_rvc, issue_slots[7].wakeup_ports[4].bits.uop.is_rvc connect slots_7.io.wakeup_ports[4].bits.uop.debug_inst, issue_slots[7].wakeup_ports[4].bits.uop.debug_inst connect slots_7.io.wakeup_ports[4].bits.uop.inst, issue_slots[7].wakeup_ports[4].bits.uop.inst connect slots_7.io.wakeup_ports[4].valid, issue_slots[7].wakeup_ports[4].valid connect slots_7.io.squash_grant, issue_slots[7].squash_grant connect slots_7.io.clear, issue_slots[7].clear connect slots_7.io.kill, issue_slots[7].kill connect slots_7.io.brupdate.b2.target_offset, issue_slots[7].brupdate.b2.target_offset connect slots_7.io.brupdate.b2.jalr_target, issue_slots[7].brupdate.b2.jalr_target connect slots_7.io.brupdate.b2.pc_sel, issue_slots[7].brupdate.b2.pc_sel connect slots_7.io.brupdate.b2.cfi_type, issue_slots[7].brupdate.b2.cfi_type connect slots_7.io.brupdate.b2.taken, issue_slots[7].brupdate.b2.taken connect slots_7.io.brupdate.b2.mispredict, issue_slots[7].brupdate.b2.mispredict connect slots_7.io.brupdate.b2.uop.debug_tsrc, issue_slots[7].brupdate.b2.uop.debug_tsrc connect slots_7.io.brupdate.b2.uop.debug_fsrc, issue_slots[7].brupdate.b2.uop.debug_fsrc connect slots_7.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[7].brupdate.b2.uop.bp_xcpt_if connect slots_7.io.brupdate.b2.uop.bp_debug_if, issue_slots[7].brupdate.b2.uop.bp_debug_if connect slots_7.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[7].brupdate.b2.uop.xcpt_ma_if connect slots_7.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[7].brupdate.b2.uop.xcpt_ae_if connect slots_7.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[7].brupdate.b2.uop.xcpt_pf_if connect slots_7.io.brupdate.b2.uop.fp_typ, issue_slots[7].brupdate.b2.uop.fp_typ connect slots_7.io.brupdate.b2.uop.fp_rm, issue_slots[7].brupdate.b2.uop.fp_rm connect slots_7.io.brupdate.b2.uop.fp_val, issue_slots[7].brupdate.b2.uop.fp_val connect slots_7.io.brupdate.b2.uop.fcn_op, issue_slots[7].brupdate.b2.uop.fcn_op connect slots_7.io.brupdate.b2.uop.fcn_dw, issue_slots[7].brupdate.b2.uop.fcn_dw connect slots_7.io.brupdate.b2.uop.frs3_en, issue_slots[7].brupdate.b2.uop.frs3_en connect slots_7.io.brupdate.b2.uop.lrs2_rtype, issue_slots[7].brupdate.b2.uop.lrs2_rtype connect slots_7.io.brupdate.b2.uop.lrs1_rtype, issue_slots[7].brupdate.b2.uop.lrs1_rtype connect slots_7.io.brupdate.b2.uop.dst_rtype, issue_slots[7].brupdate.b2.uop.dst_rtype connect slots_7.io.brupdate.b2.uop.lrs3, issue_slots[7].brupdate.b2.uop.lrs3 connect slots_7.io.brupdate.b2.uop.lrs2, issue_slots[7].brupdate.b2.uop.lrs2 connect slots_7.io.brupdate.b2.uop.lrs1, issue_slots[7].brupdate.b2.uop.lrs1 connect slots_7.io.brupdate.b2.uop.ldst, issue_slots[7].brupdate.b2.uop.ldst connect slots_7.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[7].brupdate.b2.uop.ldst_is_rs1 connect slots_7.io.brupdate.b2.uop.csr_cmd, issue_slots[7].brupdate.b2.uop.csr_cmd connect slots_7.io.brupdate.b2.uop.flush_on_commit, issue_slots[7].brupdate.b2.uop.flush_on_commit connect slots_7.io.brupdate.b2.uop.is_unique, issue_slots[7].brupdate.b2.uop.is_unique connect slots_7.io.brupdate.b2.uop.uses_stq, issue_slots[7].brupdate.b2.uop.uses_stq connect slots_7.io.brupdate.b2.uop.uses_ldq, issue_slots[7].brupdate.b2.uop.uses_ldq connect slots_7.io.brupdate.b2.uop.mem_signed, issue_slots[7].brupdate.b2.uop.mem_signed connect slots_7.io.brupdate.b2.uop.mem_size, issue_slots[7].brupdate.b2.uop.mem_size connect slots_7.io.brupdate.b2.uop.mem_cmd, issue_slots[7].brupdate.b2.uop.mem_cmd connect slots_7.io.brupdate.b2.uop.exc_cause, issue_slots[7].brupdate.b2.uop.exc_cause connect slots_7.io.brupdate.b2.uop.exception, issue_slots[7].brupdate.b2.uop.exception connect slots_7.io.brupdate.b2.uop.stale_pdst, issue_slots[7].brupdate.b2.uop.stale_pdst connect slots_7.io.brupdate.b2.uop.ppred_busy, issue_slots[7].brupdate.b2.uop.ppred_busy connect slots_7.io.brupdate.b2.uop.prs3_busy, issue_slots[7].brupdate.b2.uop.prs3_busy connect slots_7.io.brupdate.b2.uop.prs2_busy, issue_slots[7].brupdate.b2.uop.prs2_busy connect slots_7.io.brupdate.b2.uop.prs1_busy, issue_slots[7].brupdate.b2.uop.prs1_busy connect slots_7.io.brupdate.b2.uop.ppred, issue_slots[7].brupdate.b2.uop.ppred connect slots_7.io.brupdate.b2.uop.prs3, issue_slots[7].brupdate.b2.uop.prs3 connect slots_7.io.brupdate.b2.uop.prs2, issue_slots[7].brupdate.b2.uop.prs2 connect slots_7.io.brupdate.b2.uop.prs1, issue_slots[7].brupdate.b2.uop.prs1 connect slots_7.io.brupdate.b2.uop.pdst, issue_slots[7].brupdate.b2.uop.pdst connect slots_7.io.brupdate.b2.uop.rxq_idx, issue_slots[7].brupdate.b2.uop.rxq_idx connect slots_7.io.brupdate.b2.uop.stq_idx, issue_slots[7].brupdate.b2.uop.stq_idx connect slots_7.io.brupdate.b2.uop.ldq_idx, issue_slots[7].brupdate.b2.uop.ldq_idx connect slots_7.io.brupdate.b2.uop.rob_idx, issue_slots[7].brupdate.b2.uop.rob_idx connect slots_7.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[7].brupdate.b2.uop.fp_ctrl.vec connect slots_7.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[7].brupdate.b2.uop.fp_ctrl.wflags connect slots_7.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[7].brupdate.b2.uop.fp_ctrl.sqrt connect slots_7.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[7].brupdate.b2.uop.fp_ctrl.div connect slots_7.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[7].brupdate.b2.uop.fp_ctrl.fma connect slots_7.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[7].brupdate.b2.uop.fp_ctrl.fastpipe connect slots_7.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[7].brupdate.b2.uop.fp_ctrl.toint connect slots_7.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[7].brupdate.b2.uop.fp_ctrl.fromint connect slots_7.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[7].brupdate.b2.uop.fp_ctrl.typeTagOut connect slots_7.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[7].brupdate.b2.uop.fp_ctrl.typeTagIn connect slots_7.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[7].brupdate.b2.uop.fp_ctrl.swap23 connect slots_7.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[7].brupdate.b2.uop.fp_ctrl.swap12 connect slots_7.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[7].brupdate.b2.uop.fp_ctrl.ren3 connect slots_7.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[7].brupdate.b2.uop.fp_ctrl.ren2 connect slots_7.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[7].brupdate.b2.uop.fp_ctrl.ren1 connect slots_7.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[7].brupdate.b2.uop.fp_ctrl.wen connect slots_7.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[7].brupdate.b2.uop.fp_ctrl.ldst connect slots_7.io.brupdate.b2.uop.op2_sel, issue_slots[7].brupdate.b2.uop.op2_sel connect slots_7.io.brupdate.b2.uop.op1_sel, issue_slots[7].brupdate.b2.uop.op1_sel connect slots_7.io.brupdate.b2.uop.imm_packed, issue_slots[7].brupdate.b2.uop.imm_packed connect slots_7.io.brupdate.b2.uop.pimm, issue_slots[7].brupdate.b2.uop.pimm connect slots_7.io.brupdate.b2.uop.imm_sel, issue_slots[7].brupdate.b2.uop.imm_sel connect slots_7.io.brupdate.b2.uop.imm_rename, issue_slots[7].brupdate.b2.uop.imm_rename connect slots_7.io.brupdate.b2.uop.taken, issue_slots[7].brupdate.b2.uop.taken connect slots_7.io.brupdate.b2.uop.pc_lob, issue_slots[7].brupdate.b2.uop.pc_lob connect slots_7.io.brupdate.b2.uop.edge_inst, issue_slots[7].brupdate.b2.uop.edge_inst connect slots_7.io.brupdate.b2.uop.ftq_idx, issue_slots[7].brupdate.b2.uop.ftq_idx connect slots_7.io.brupdate.b2.uop.is_mov, issue_slots[7].brupdate.b2.uop.is_mov connect slots_7.io.brupdate.b2.uop.is_rocc, issue_slots[7].brupdate.b2.uop.is_rocc connect slots_7.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[7].brupdate.b2.uop.is_sys_pc2epc connect slots_7.io.brupdate.b2.uop.is_eret, issue_slots[7].brupdate.b2.uop.is_eret connect slots_7.io.brupdate.b2.uop.is_amo, issue_slots[7].brupdate.b2.uop.is_amo connect slots_7.io.brupdate.b2.uop.is_sfence, issue_slots[7].brupdate.b2.uop.is_sfence connect slots_7.io.brupdate.b2.uop.is_fencei, issue_slots[7].brupdate.b2.uop.is_fencei connect slots_7.io.brupdate.b2.uop.is_fence, issue_slots[7].brupdate.b2.uop.is_fence connect slots_7.io.brupdate.b2.uop.is_sfb, issue_slots[7].brupdate.b2.uop.is_sfb connect slots_7.io.brupdate.b2.uop.br_type, issue_slots[7].brupdate.b2.uop.br_type connect slots_7.io.brupdate.b2.uop.br_tag, issue_slots[7].brupdate.b2.uop.br_tag connect slots_7.io.brupdate.b2.uop.br_mask, issue_slots[7].brupdate.b2.uop.br_mask connect slots_7.io.brupdate.b2.uop.dis_col_sel, issue_slots[7].brupdate.b2.uop.dis_col_sel connect slots_7.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[7].brupdate.b2.uop.iw_p3_bypass_hint connect slots_7.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[7].brupdate.b2.uop.iw_p2_bypass_hint connect slots_7.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[7].brupdate.b2.uop.iw_p1_bypass_hint connect slots_7.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[7].brupdate.b2.uop.iw_p2_speculative_child connect slots_7.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[7].brupdate.b2.uop.iw_p1_speculative_child connect slots_7.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[7].brupdate.b2.uop.iw_issued_partial_dgen connect slots_7.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[7].brupdate.b2.uop.iw_issued_partial_agen connect slots_7.io.brupdate.b2.uop.iw_issued, issue_slots[7].brupdate.b2.uop.iw_issued connect slots_7.io.brupdate.b2.uop.fu_code[0], issue_slots[7].brupdate.b2.uop.fu_code[0] connect slots_7.io.brupdate.b2.uop.fu_code[1], issue_slots[7].brupdate.b2.uop.fu_code[1] connect slots_7.io.brupdate.b2.uop.fu_code[2], issue_slots[7].brupdate.b2.uop.fu_code[2] connect slots_7.io.brupdate.b2.uop.fu_code[3], issue_slots[7].brupdate.b2.uop.fu_code[3] connect slots_7.io.brupdate.b2.uop.fu_code[4], issue_slots[7].brupdate.b2.uop.fu_code[4] connect slots_7.io.brupdate.b2.uop.fu_code[5], issue_slots[7].brupdate.b2.uop.fu_code[5] connect slots_7.io.brupdate.b2.uop.fu_code[6], issue_slots[7].brupdate.b2.uop.fu_code[6] connect slots_7.io.brupdate.b2.uop.fu_code[7], issue_slots[7].brupdate.b2.uop.fu_code[7] connect slots_7.io.brupdate.b2.uop.fu_code[8], issue_slots[7].brupdate.b2.uop.fu_code[8] connect slots_7.io.brupdate.b2.uop.fu_code[9], issue_slots[7].brupdate.b2.uop.fu_code[9] connect slots_7.io.brupdate.b2.uop.iq_type[0], issue_slots[7].brupdate.b2.uop.iq_type[0] connect slots_7.io.brupdate.b2.uop.iq_type[1], issue_slots[7].brupdate.b2.uop.iq_type[1] connect slots_7.io.brupdate.b2.uop.iq_type[2], issue_slots[7].brupdate.b2.uop.iq_type[2] connect slots_7.io.brupdate.b2.uop.iq_type[3], issue_slots[7].brupdate.b2.uop.iq_type[3] connect slots_7.io.brupdate.b2.uop.debug_pc, issue_slots[7].brupdate.b2.uop.debug_pc connect slots_7.io.brupdate.b2.uop.is_rvc, issue_slots[7].brupdate.b2.uop.is_rvc connect slots_7.io.brupdate.b2.uop.debug_inst, issue_slots[7].brupdate.b2.uop.debug_inst connect slots_7.io.brupdate.b2.uop.inst, issue_slots[7].brupdate.b2.uop.inst connect slots_7.io.brupdate.b1.mispredict_mask, issue_slots[7].brupdate.b1.mispredict_mask connect slots_7.io.brupdate.b1.resolve_mask, issue_slots[7].brupdate.b1.resolve_mask connect issue_slots[7].out_uop.debug_tsrc, slots_7.io.out_uop.debug_tsrc connect issue_slots[7].out_uop.debug_fsrc, slots_7.io.out_uop.debug_fsrc connect issue_slots[7].out_uop.bp_xcpt_if, slots_7.io.out_uop.bp_xcpt_if connect issue_slots[7].out_uop.bp_debug_if, slots_7.io.out_uop.bp_debug_if connect issue_slots[7].out_uop.xcpt_ma_if, slots_7.io.out_uop.xcpt_ma_if connect issue_slots[7].out_uop.xcpt_ae_if, slots_7.io.out_uop.xcpt_ae_if connect issue_slots[7].out_uop.xcpt_pf_if, slots_7.io.out_uop.xcpt_pf_if connect issue_slots[7].out_uop.fp_typ, slots_7.io.out_uop.fp_typ connect issue_slots[7].out_uop.fp_rm, slots_7.io.out_uop.fp_rm connect issue_slots[7].out_uop.fp_val, slots_7.io.out_uop.fp_val connect issue_slots[7].out_uop.fcn_op, slots_7.io.out_uop.fcn_op connect issue_slots[7].out_uop.fcn_dw, slots_7.io.out_uop.fcn_dw connect issue_slots[7].out_uop.frs3_en, slots_7.io.out_uop.frs3_en connect issue_slots[7].out_uop.lrs2_rtype, slots_7.io.out_uop.lrs2_rtype connect issue_slots[7].out_uop.lrs1_rtype, slots_7.io.out_uop.lrs1_rtype connect issue_slots[7].out_uop.dst_rtype, slots_7.io.out_uop.dst_rtype connect issue_slots[7].out_uop.lrs3, slots_7.io.out_uop.lrs3 connect issue_slots[7].out_uop.lrs2, slots_7.io.out_uop.lrs2 connect issue_slots[7].out_uop.lrs1, slots_7.io.out_uop.lrs1 connect issue_slots[7].out_uop.ldst, slots_7.io.out_uop.ldst connect issue_slots[7].out_uop.ldst_is_rs1, slots_7.io.out_uop.ldst_is_rs1 connect issue_slots[7].out_uop.csr_cmd, slots_7.io.out_uop.csr_cmd connect issue_slots[7].out_uop.flush_on_commit, slots_7.io.out_uop.flush_on_commit connect issue_slots[7].out_uop.is_unique, slots_7.io.out_uop.is_unique connect issue_slots[7].out_uop.uses_stq, slots_7.io.out_uop.uses_stq connect issue_slots[7].out_uop.uses_ldq, slots_7.io.out_uop.uses_ldq connect issue_slots[7].out_uop.mem_signed, slots_7.io.out_uop.mem_signed connect issue_slots[7].out_uop.mem_size, slots_7.io.out_uop.mem_size connect issue_slots[7].out_uop.mem_cmd, slots_7.io.out_uop.mem_cmd connect issue_slots[7].out_uop.exc_cause, slots_7.io.out_uop.exc_cause connect issue_slots[7].out_uop.exception, slots_7.io.out_uop.exception connect issue_slots[7].out_uop.stale_pdst, slots_7.io.out_uop.stale_pdst connect issue_slots[7].out_uop.ppred_busy, slots_7.io.out_uop.ppred_busy connect issue_slots[7].out_uop.prs3_busy, slots_7.io.out_uop.prs3_busy connect issue_slots[7].out_uop.prs2_busy, slots_7.io.out_uop.prs2_busy connect issue_slots[7].out_uop.prs1_busy, slots_7.io.out_uop.prs1_busy connect issue_slots[7].out_uop.ppred, slots_7.io.out_uop.ppred connect issue_slots[7].out_uop.prs3, slots_7.io.out_uop.prs3 connect issue_slots[7].out_uop.prs2, slots_7.io.out_uop.prs2 connect issue_slots[7].out_uop.prs1, slots_7.io.out_uop.prs1 connect issue_slots[7].out_uop.pdst, slots_7.io.out_uop.pdst connect issue_slots[7].out_uop.rxq_idx, slots_7.io.out_uop.rxq_idx connect issue_slots[7].out_uop.stq_idx, slots_7.io.out_uop.stq_idx connect issue_slots[7].out_uop.ldq_idx, slots_7.io.out_uop.ldq_idx connect issue_slots[7].out_uop.rob_idx, slots_7.io.out_uop.rob_idx connect issue_slots[7].out_uop.fp_ctrl.vec, slots_7.io.out_uop.fp_ctrl.vec connect issue_slots[7].out_uop.fp_ctrl.wflags, slots_7.io.out_uop.fp_ctrl.wflags connect issue_slots[7].out_uop.fp_ctrl.sqrt, slots_7.io.out_uop.fp_ctrl.sqrt connect issue_slots[7].out_uop.fp_ctrl.div, slots_7.io.out_uop.fp_ctrl.div connect issue_slots[7].out_uop.fp_ctrl.fma, slots_7.io.out_uop.fp_ctrl.fma connect issue_slots[7].out_uop.fp_ctrl.fastpipe, slots_7.io.out_uop.fp_ctrl.fastpipe connect issue_slots[7].out_uop.fp_ctrl.toint, slots_7.io.out_uop.fp_ctrl.toint connect issue_slots[7].out_uop.fp_ctrl.fromint, slots_7.io.out_uop.fp_ctrl.fromint connect issue_slots[7].out_uop.fp_ctrl.typeTagOut, slots_7.io.out_uop.fp_ctrl.typeTagOut connect issue_slots[7].out_uop.fp_ctrl.typeTagIn, slots_7.io.out_uop.fp_ctrl.typeTagIn connect issue_slots[7].out_uop.fp_ctrl.swap23, slots_7.io.out_uop.fp_ctrl.swap23 connect issue_slots[7].out_uop.fp_ctrl.swap12, slots_7.io.out_uop.fp_ctrl.swap12 connect issue_slots[7].out_uop.fp_ctrl.ren3, slots_7.io.out_uop.fp_ctrl.ren3 connect issue_slots[7].out_uop.fp_ctrl.ren2, slots_7.io.out_uop.fp_ctrl.ren2 connect issue_slots[7].out_uop.fp_ctrl.ren1, slots_7.io.out_uop.fp_ctrl.ren1 connect issue_slots[7].out_uop.fp_ctrl.wen, slots_7.io.out_uop.fp_ctrl.wen connect issue_slots[7].out_uop.fp_ctrl.ldst, slots_7.io.out_uop.fp_ctrl.ldst connect issue_slots[7].out_uop.op2_sel, slots_7.io.out_uop.op2_sel connect issue_slots[7].out_uop.op1_sel, slots_7.io.out_uop.op1_sel connect issue_slots[7].out_uop.imm_packed, slots_7.io.out_uop.imm_packed connect issue_slots[7].out_uop.pimm, slots_7.io.out_uop.pimm connect issue_slots[7].out_uop.imm_sel, slots_7.io.out_uop.imm_sel connect issue_slots[7].out_uop.imm_rename, slots_7.io.out_uop.imm_rename connect issue_slots[7].out_uop.taken, slots_7.io.out_uop.taken connect issue_slots[7].out_uop.pc_lob, slots_7.io.out_uop.pc_lob connect issue_slots[7].out_uop.edge_inst, slots_7.io.out_uop.edge_inst connect issue_slots[7].out_uop.ftq_idx, slots_7.io.out_uop.ftq_idx connect issue_slots[7].out_uop.is_mov, slots_7.io.out_uop.is_mov connect issue_slots[7].out_uop.is_rocc, slots_7.io.out_uop.is_rocc connect issue_slots[7].out_uop.is_sys_pc2epc, slots_7.io.out_uop.is_sys_pc2epc connect issue_slots[7].out_uop.is_eret, slots_7.io.out_uop.is_eret connect issue_slots[7].out_uop.is_amo, slots_7.io.out_uop.is_amo connect issue_slots[7].out_uop.is_sfence, slots_7.io.out_uop.is_sfence connect issue_slots[7].out_uop.is_fencei, slots_7.io.out_uop.is_fencei connect issue_slots[7].out_uop.is_fence, slots_7.io.out_uop.is_fence connect issue_slots[7].out_uop.is_sfb, slots_7.io.out_uop.is_sfb connect issue_slots[7].out_uop.br_type, slots_7.io.out_uop.br_type connect issue_slots[7].out_uop.br_tag, slots_7.io.out_uop.br_tag connect issue_slots[7].out_uop.br_mask, slots_7.io.out_uop.br_mask connect issue_slots[7].out_uop.dis_col_sel, slots_7.io.out_uop.dis_col_sel connect issue_slots[7].out_uop.iw_p3_bypass_hint, slots_7.io.out_uop.iw_p3_bypass_hint connect issue_slots[7].out_uop.iw_p2_bypass_hint, slots_7.io.out_uop.iw_p2_bypass_hint connect issue_slots[7].out_uop.iw_p1_bypass_hint, slots_7.io.out_uop.iw_p1_bypass_hint connect issue_slots[7].out_uop.iw_p2_speculative_child, slots_7.io.out_uop.iw_p2_speculative_child connect issue_slots[7].out_uop.iw_p1_speculative_child, slots_7.io.out_uop.iw_p1_speculative_child connect issue_slots[7].out_uop.iw_issued_partial_dgen, slots_7.io.out_uop.iw_issued_partial_dgen connect issue_slots[7].out_uop.iw_issued_partial_agen, slots_7.io.out_uop.iw_issued_partial_agen connect issue_slots[7].out_uop.iw_issued, slots_7.io.out_uop.iw_issued connect issue_slots[7].out_uop.fu_code[0], slots_7.io.out_uop.fu_code[0] connect issue_slots[7].out_uop.fu_code[1], slots_7.io.out_uop.fu_code[1] connect issue_slots[7].out_uop.fu_code[2], slots_7.io.out_uop.fu_code[2] connect issue_slots[7].out_uop.fu_code[3], slots_7.io.out_uop.fu_code[3] connect issue_slots[7].out_uop.fu_code[4], slots_7.io.out_uop.fu_code[4] connect issue_slots[7].out_uop.fu_code[5], slots_7.io.out_uop.fu_code[5] connect issue_slots[7].out_uop.fu_code[6], slots_7.io.out_uop.fu_code[6] connect issue_slots[7].out_uop.fu_code[7], slots_7.io.out_uop.fu_code[7] connect issue_slots[7].out_uop.fu_code[8], slots_7.io.out_uop.fu_code[8] connect issue_slots[7].out_uop.fu_code[9], slots_7.io.out_uop.fu_code[9] connect issue_slots[7].out_uop.iq_type[0], slots_7.io.out_uop.iq_type[0] connect issue_slots[7].out_uop.iq_type[1], slots_7.io.out_uop.iq_type[1] connect issue_slots[7].out_uop.iq_type[2], slots_7.io.out_uop.iq_type[2] connect issue_slots[7].out_uop.iq_type[3], slots_7.io.out_uop.iq_type[3] connect issue_slots[7].out_uop.debug_pc, slots_7.io.out_uop.debug_pc connect issue_slots[7].out_uop.is_rvc, slots_7.io.out_uop.is_rvc connect issue_slots[7].out_uop.debug_inst, slots_7.io.out_uop.debug_inst connect issue_slots[7].out_uop.inst, slots_7.io.out_uop.inst connect slots_7.io.in_uop.bits.debug_tsrc, issue_slots[7].in_uop.bits.debug_tsrc connect slots_7.io.in_uop.bits.debug_fsrc, issue_slots[7].in_uop.bits.debug_fsrc connect slots_7.io.in_uop.bits.bp_xcpt_if, issue_slots[7].in_uop.bits.bp_xcpt_if connect slots_7.io.in_uop.bits.bp_debug_if, issue_slots[7].in_uop.bits.bp_debug_if connect slots_7.io.in_uop.bits.xcpt_ma_if, issue_slots[7].in_uop.bits.xcpt_ma_if connect slots_7.io.in_uop.bits.xcpt_ae_if, issue_slots[7].in_uop.bits.xcpt_ae_if connect slots_7.io.in_uop.bits.xcpt_pf_if, issue_slots[7].in_uop.bits.xcpt_pf_if connect slots_7.io.in_uop.bits.fp_typ, issue_slots[7].in_uop.bits.fp_typ connect slots_7.io.in_uop.bits.fp_rm, issue_slots[7].in_uop.bits.fp_rm connect slots_7.io.in_uop.bits.fp_val, issue_slots[7].in_uop.bits.fp_val connect slots_7.io.in_uop.bits.fcn_op, issue_slots[7].in_uop.bits.fcn_op connect slots_7.io.in_uop.bits.fcn_dw, issue_slots[7].in_uop.bits.fcn_dw connect slots_7.io.in_uop.bits.frs3_en, issue_slots[7].in_uop.bits.frs3_en connect slots_7.io.in_uop.bits.lrs2_rtype, issue_slots[7].in_uop.bits.lrs2_rtype connect slots_7.io.in_uop.bits.lrs1_rtype, issue_slots[7].in_uop.bits.lrs1_rtype connect slots_7.io.in_uop.bits.dst_rtype, issue_slots[7].in_uop.bits.dst_rtype connect slots_7.io.in_uop.bits.lrs3, issue_slots[7].in_uop.bits.lrs3 connect slots_7.io.in_uop.bits.lrs2, issue_slots[7].in_uop.bits.lrs2 connect slots_7.io.in_uop.bits.lrs1, issue_slots[7].in_uop.bits.lrs1 connect slots_7.io.in_uop.bits.ldst, issue_slots[7].in_uop.bits.ldst connect slots_7.io.in_uop.bits.ldst_is_rs1, issue_slots[7].in_uop.bits.ldst_is_rs1 connect slots_7.io.in_uop.bits.csr_cmd, issue_slots[7].in_uop.bits.csr_cmd connect slots_7.io.in_uop.bits.flush_on_commit, issue_slots[7].in_uop.bits.flush_on_commit connect slots_7.io.in_uop.bits.is_unique, issue_slots[7].in_uop.bits.is_unique connect slots_7.io.in_uop.bits.uses_stq, issue_slots[7].in_uop.bits.uses_stq connect slots_7.io.in_uop.bits.uses_ldq, issue_slots[7].in_uop.bits.uses_ldq connect slots_7.io.in_uop.bits.mem_signed, issue_slots[7].in_uop.bits.mem_signed connect slots_7.io.in_uop.bits.mem_size, issue_slots[7].in_uop.bits.mem_size connect slots_7.io.in_uop.bits.mem_cmd, issue_slots[7].in_uop.bits.mem_cmd connect slots_7.io.in_uop.bits.exc_cause, issue_slots[7].in_uop.bits.exc_cause connect slots_7.io.in_uop.bits.exception, issue_slots[7].in_uop.bits.exception connect slots_7.io.in_uop.bits.stale_pdst, issue_slots[7].in_uop.bits.stale_pdst connect slots_7.io.in_uop.bits.ppred_busy, issue_slots[7].in_uop.bits.ppred_busy connect slots_7.io.in_uop.bits.prs3_busy, issue_slots[7].in_uop.bits.prs3_busy connect slots_7.io.in_uop.bits.prs2_busy, issue_slots[7].in_uop.bits.prs2_busy connect slots_7.io.in_uop.bits.prs1_busy, issue_slots[7].in_uop.bits.prs1_busy connect slots_7.io.in_uop.bits.ppred, issue_slots[7].in_uop.bits.ppred connect slots_7.io.in_uop.bits.prs3, issue_slots[7].in_uop.bits.prs3 connect slots_7.io.in_uop.bits.prs2, issue_slots[7].in_uop.bits.prs2 connect slots_7.io.in_uop.bits.prs1, issue_slots[7].in_uop.bits.prs1 connect slots_7.io.in_uop.bits.pdst, issue_slots[7].in_uop.bits.pdst connect slots_7.io.in_uop.bits.rxq_idx, issue_slots[7].in_uop.bits.rxq_idx connect slots_7.io.in_uop.bits.stq_idx, issue_slots[7].in_uop.bits.stq_idx connect slots_7.io.in_uop.bits.ldq_idx, issue_slots[7].in_uop.bits.ldq_idx connect slots_7.io.in_uop.bits.rob_idx, issue_slots[7].in_uop.bits.rob_idx connect slots_7.io.in_uop.bits.fp_ctrl.vec, issue_slots[7].in_uop.bits.fp_ctrl.vec connect slots_7.io.in_uop.bits.fp_ctrl.wflags, issue_slots[7].in_uop.bits.fp_ctrl.wflags connect slots_7.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[7].in_uop.bits.fp_ctrl.sqrt connect slots_7.io.in_uop.bits.fp_ctrl.div, issue_slots[7].in_uop.bits.fp_ctrl.div connect slots_7.io.in_uop.bits.fp_ctrl.fma, issue_slots[7].in_uop.bits.fp_ctrl.fma connect slots_7.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[7].in_uop.bits.fp_ctrl.fastpipe connect slots_7.io.in_uop.bits.fp_ctrl.toint, issue_slots[7].in_uop.bits.fp_ctrl.toint connect slots_7.io.in_uop.bits.fp_ctrl.fromint, issue_slots[7].in_uop.bits.fp_ctrl.fromint connect slots_7.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[7].in_uop.bits.fp_ctrl.typeTagOut connect slots_7.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[7].in_uop.bits.fp_ctrl.typeTagIn connect slots_7.io.in_uop.bits.fp_ctrl.swap23, issue_slots[7].in_uop.bits.fp_ctrl.swap23 connect slots_7.io.in_uop.bits.fp_ctrl.swap12, issue_slots[7].in_uop.bits.fp_ctrl.swap12 connect slots_7.io.in_uop.bits.fp_ctrl.ren3, issue_slots[7].in_uop.bits.fp_ctrl.ren3 connect slots_7.io.in_uop.bits.fp_ctrl.ren2, issue_slots[7].in_uop.bits.fp_ctrl.ren2 connect slots_7.io.in_uop.bits.fp_ctrl.ren1, issue_slots[7].in_uop.bits.fp_ctrl.ren1 connect slots_7.io.in_uop.bits.fp_ctrl.wen, issue_slots[7].in_uop.bits.fp_ctrl.wen connect slots_7.io.in_uop.bits.fp_ctrl.ldst, issue_slots[7].in_uop.bits.fp_ctrl.ldst connect slots_7.io.in_uop.bits.op2_sel, issue_slots[7].in_uop.bits.op2_sel connect slots_7.io.in_uop.bits.op1_sel, issue_slots[7].in_uop.bits.op1_sel connect slots_7.io.in_uop.bits.imm_packed, issue_slots[7].in_uop.bits.imm_packed connect slots_7.io.in_uop.bits.pimm, issue_slots[7].in_uop.bits.pimm connect slots_7.io.in_uop.bits.imm_sel, issue_slots[7].in_uop.bits.imm_sel connect slots_7.io.in_uop.bits.imm_rename, issue_slots[7].in_uop.bits.imm_rename connect slots_7.io.in_uop.bits.taken, issue_slots[7].in_uop.bits.taken connect slots_7.io.in_uop.bits.pc_lob, issue_slots[7].in_uop.bits.pc_lob connect slots_7.io.in_uop.bits.edge_inst, issue_slots[7].in_uop.bits.edge_inst connect slots_7.io.in_uop.bits.ftq_idx, issue_slots[7].in_uop.bits.ftq_idx connect slots_7.io.in_uop.bits.is_mov, issue_slots[7].in_uop.bits.is_mov connect slots_7.io.in_uop.bits.is_rocc, issue_slots[7].in_uop.bits.is_rocc connect slots_7.io.in_uop.bits.is_sys_pc2epc, issue_slots[7].in_uop.bits.is_sys_pc2epc connect slots_7.io.in_uop.bits.is_eret, issue_slots[7].in_uop.bits.is_eret connect slots_7.io.in_uop.bits.is_amo, issue_slots[7].in_uop.bits.is_amo connect slots_7.io.in_uop.bits.is_sfence, issue_slots[7].in_uop.bits.is_sfence connect slots_7.io.in_uop.bits.is_fencei, issue_slots[7].in_uop.bits.is_fencei connect slots_7.io.in_uop.bits.is_fence, issue_slots[7].in_uop.bits.is_fence connect slots_7.io.in_uop.bits.is_sfb, issue_slots[7].in_uop.bits.is_sfb connect slots_7.io.in_uop.bits.br_type, issue_slots[7].in_uop.bits.br_type connect slots_7.io.in_uop.bits.br_tag, issue_slots[7].in_uop.bits.br_tag connect slots_7.io.in_uop.bits.br_mask, issue_slots[7].in_uop.bits.br_mask connect slots_7.io.in_uop.bits.dis_col_sel, issue_slots[7].in_uop.bits.dis_col_sel connect slots_7.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[7].in_uop.bits.iw_p3_bypass_hint connect slots_7.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[7].in_uop.bits.iw_p2_bypass_hint connect slots_7.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[7].in_uop.bits.iw_p1_bypass_hint connect slots_7.io.in_uop.bits.iw_p2_speculative_child, issue_slots[7].in_uop.bits.iw_p2_speculative_child connect slots_7.io.in_uop.bits.iw_p1_speculative_child, issue_slots[7].in_uop.bits.iw_p1_speculative_child connect slots_7.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[7].in_uop.bits.iw_issued_partial_dgen connect slots_7.io.in_uop.bits.iw_issued_partial_agen, issue_slots[7].in_uop.bits.iw_issued_partial_agen connect slots_7.io.in_uop.bits.iw_issued, issue_slots[7].in_uop.bits.iw_issued connect slots_7.io.in_uop.bits.fu_code[0], issue_slots[7].in_uop.bits.fu_code[0] connect slots_7.io.in_uop.bits.fu_code[1], issue_slots[7].in_uop.bits.fu_code[1] connect slots_7.io.in_uop.bits.fu_code[2], issue_slots[7].in_uop.bits.fu_code[2] connect slots_7.io.in_uop.bits.fu_code[3], issue_slots[7].in_uop.bits.fu_code[3] connect slots_7.io.in_uop.bits.fu_code[4], issue_slots[7].in_uop.bits.fu_code[4] connect slots_7.io.in_uop.bits.fu_code[5], issue_slots[7].in_uop.bits.fu_code[5] connect slots_7.io.in_uop.bits.fu_code[6], issue_slots[7].in_uop.bits.fu_code[6] connect slots_7.io.in_uop.bits.fu_code[7], issue_slots[7].in_uop.bits.fu_code[7] connect slots_7.io.in_uop.bits.fu_code[8], issue_slots[7].in_uop.bits.fu_code[8] connect slots_7.io.in_uop.bits.fu_code[9], issue_slots[7].in_uop.bits.fu_code[9] connect slots_7.io.in_uop.bits.iq_type[0], issue_slots[7].in_uop.bits.iq_type[0] connect slots_7.io.in_uop.bits.iq_type[1], issue_slots[7].in_uop.bits.iq_type[1] connect slots_7.io.in_uop.bits.iq_type[2], issue_slots[7].in_uop.bits.iq_type[2] connect slots_7.io.in_uop.bits.iq_type[3], issue_slots[7].in_uop.bits.iq_type[3] connect slots_7.io.in_uop.bits.debug_pc, issue_slots[7].in_uop.bits.debug_pc connect slots_7.io.in_uop.bits.is_rvc, issue_slots[7].in_uop.bits.is_rvc connect slots_7.io.in_uop.bits.debug_inst, issue_slots[7].in_uop.bits.debug_inst connect slots_7.io.in_uop.bits.inst, issue_slots[7].in_uop.bits.inst connect slots_7.io.in_uop.valid, issue_slots[7].in_uop.valid connect issue_slots[7].iss_uop.debug_tsrc, slots_7.io.iss_uop.debug_tsrc connect issue_slots[7].iss_uop.debug_fsrc, slots_7.io.iss_uop.debug_fsrc connect issue_slots[7].iss_uop.bp_xcpt_if, slots_7.io.iss_uop.bp_xcpt_if connect issue_slots[7].iss_uop.bp_debug_if, slots_7.io.iss_uop.bp_debug_if connect issue_slots[7].iss_uop.xcpt_ma_if, slots_7.io.iss_uop.xcpt_ma_if connect issue_slots[7].iss_uop.xcpt_ae_if, slots_7.io.iss_uop.xcpt_ae_if connect issue_slots[7].iss_uop.xcpt_pf_if, slots_7.io.iss_uop.xcpt_pf_if connect issue_slots[7].iss_uop.fp_typ, slots_7.io.iss_uop.fp_typ connect issue_slots[7].iss_uop.fp_rm, slots_7.io.iss_uop.fp_rm connect issue_slots[7].iss_uop.fp_val, slots_7.io.iss_uop.fp_val connect issue_slots[7].iss_uop.fcn_op, slots_7.io.iss_uop.fcn_op connect issue_slots[7].iss_uop.fcn_dw, slots_7.io.iss_uop.fcn_dw connect issue_slots[7].iss_uop.frs3_en, slots_7.io.iss_uop.frs3_en connect issue_slots[7].iss_uop.lrs2_rtype, slots_7.io.iss_uop.lrs2_rtype connect issue_slots[7].iss_uop.lrs1_rtype, slots_7.io.iss_uop.lrs1_rtype connect issue_slots[7].iss_uop.dst_rtype, slots_7.io.iss_uop.dst_rtype connect issue_slots[7].iss_uop.lrs3, slots_7.io.iss_uop.lrs3 connect issue_slots[7].iss_uop.lrs2, slots_7.io.iss_uop.lrs2 connect issue_slots[7].iss_uop.lrs1, slots_7.io.iss_uop.lrs1 connect issue_slots[7].iss_uop.ldst, slots_7.io.iss_uop.ldst connect issue_slots[7].iss_uop.ldst_is_rs1, slots_7.io.iss_uop.ldst_is_rs1 connect issue_slots[7].iss_uop.csr_cmd, slots_7.io.iss_uop.csr_cmd connect issue_slots[7].iss_uop.flush_on_commit, slots_7.io.iss_uop.flush_on_commit connect issue_slots[7].iss_uop.is_unique, slots_7.io.iss_uop.is_unique connect issue_slots[7].iss_uop.uses_stq, slots_7.io.iss_uop.uses_stq connect issue_slots[7].iss_uop.uses_ldq, slots_7.io.iss_uop.uses_ldq connect issue_slots[7].iss_uop.mem_signed, slots_7.io.iss_uop.mem_signed connect issue_slots[7].iss_uop.mem_size, slots_7.io.iss_uop.mem_size connect issue_slots[7].iss_uop.mem_cmd, slots_7.io.iss_uop.mem_cmd connect issue_slots[7].iss_uop.exc_cause, slots_7.io.iss_uop.exc_cause connect issue_slots[7].iss_uop.exception, slots_7.io.iss_uop.exception connect issue_slots[7].iss_uop.stale_pdst, slots_7.io.iss_uop.stale_pdst connect issue_slots[7].iss_uop.ppred_busy, slots_7.io.iss_uop.ppred_busy connect issue_slots[7].iss_uop.prs3_busy, slots_7.io.iss_uop.prs3_busy connect issue_slots[7].iss_uop.prs2_busy, slots_7.io.iss_uop.prs2_busy connect issue_slots[7].iss_uop.prs1_busy, slots_7.io.iss_uop.prs1_busy connect issue_slots[7].iss_uop.ppred, slots_7.io.iss_uop.ppred connect issue_slots[7].iss_uop.prs3, slots_7.io.iss_uop.prs3 connect issue_slots[7].iss_uop.prs2, slots_7.io.iss_uop.prs2 connect issue_slots[7].iss_uop.prs1, slots_7.io.iss_uop.prs1 connect issue_slots[7].iss_uop.pdst, slots_7.io.iss_uop.pdst connect issue_slots[7].iss_uop.rxq_idx, slots_7.io.iss_uop.rxq_idx connect issue_slots[7].iss_uop.stq_idx, slots_7.io.iss_uop.stq_idx connect issue_slots[7].iss_uop.ldq_idx, slots_7.io.iss_uop.ldq_idx connect issue_slots[7].iss_uop.rob_idx, slots_7.io.iss_uop.rob_idx connect issue_slots[7].iss_uop.fp_ctrl.vec, slots_7.io.iss_uop.fp_ctrl.vec connect issue_slots[7].iss_uop.fp_ctrl.wflags, slots_7.io.iss_uop.fp_ctrl.wflags connect issue_slots[7].iss_uop.fp_ctrl.sqrt, slots_7.io.iss_uop.fp_ctrl.sqrt connect issue_slots[7].iss_uop.fp_ctrl.div, slots_7.io.iss_uop.fp_ctrl.div connect issue_slots[7].iss_uop.fp_ctrl.fma, slots_7.io.iss_uop.fp_ctrl.fma connect issue_slots[7].iss_uop.fp_ctrl.fastpipe, slots_7.io.iss_uop.fp_ctrl.fastpipe connect issue_slots[7].iss_uop.fp_ctrl.toint, slots_7.io.iss_uop.fp_ctrl.toint connect issue_slots[7].iss_uop.fp_ctrl.fromint, slots_7.io.iss_uop.fp_ctrl.fromint connect issue_slots[7].iss_uop.fp_ctrl.typeTagOut, slots_7.io.iss_uop.fp_ctrl.typeTagOut connect issue_slots[7].iss_uop.fp_ctrl.typeTagIn, slots_7.io.iss_uop.fp_ctrl.typeTagIn connect issue_slots[7].iss_uop.fp_ctrl.swap23, slots_7.io.iss_uop.fp_ctrl.swap23 connect issue_slots[7].iss_uop.fp_ctrl.swap12, slots_7.io.iss_uop.fp_ctrl.swap12 connect issue_slots[7].iss_uop.fp_ctrl.ren3, slots_7.io.iss_uop.fp_ctrl.ren3 connect issue_slots[7].iss_uop.fp_ctrl.ren2, slots_7.io.iss_uop.fp_ctrl.ren2 connect issue_slots[7].iss_uop.fp_ctrl.ren1, slots_7.io.iss_uop.fp_ctrl.ren1 connect issue_slots[7].iss_uop.fp_ctrl.wen, slots_7.io.iss_uop.fp_ctrl.wen connect issue_slots[7].iss_uop.fp_ctrl.ldst, slots_7.io.iss_uop.fp_ctrl.ldst connect issue_slots[7].iss_uop.op2_sel, slots_7.io.iss_uop.op2_sel connect issue_slots[7].iss_uop.op1_sel, slots_7.io.iss_uop.op1_sel connect issue_slots[7].iss_uop.imm_packed, slots_7.io.iss_uop.imm_packed connect issue_slots[7].iss_uop.pimm, slots_7.io.iss_uop.pimm connect issue_slots[7].iss_uop.imm_sel, slots_7.io.iss_uop.imm_sel connect issue_slots[7].iss_uop.imm_rename, slots_7.io.iss_uop.imm_rename connect issue_slots[7].iss_uop.taken, slots_7.io.iss_uop.taken connect issue_slots[7].iss_uop.pc_lob, slots_7.io.iss_uop.pc_lob connect issue_slots[7].iss_uop.edge_inst, slots_7.io.iss_uop.edge_inst connect issue_slots[7].iss_uop.ftq_idx, slots_7.io.iss_uop.ftq_idx connect issue_slots[7].iss_uop.is_mov, slots_7.io.iss_uop.is_mov connect issue_slots[7].iss_uop.is_rocc, slots_7.io.iss_uop.is_rocc connect issue_slots[7].iss_uop.is_sys_pc2epc, slots_7.io.iss_uop.is_sys_pc2epc connect issue_slots[7].iss_uop.is_eret, slots_7.io.iss_uop.is_eret connect issue_slots[7].iss_uop.is_amo, slots_7.io.iss_uop.is_amo connect issue_slots[7].iss_uop.is_sfence, slots_7.io.iss_uop.is_sfence connect issue_slots[7].iss_uop.is_fencei, slots_7.io.iss_uop.is_fencei connect issue_slots[7].iss_uop.is_fence, slots_7.io.iss_uop.is_fence connect issue_slots[7].iss_uop.is_sfb, slots_7.io.iss_uop.is_sfb connect issue_slots[7].iss_uop.br_type, slots_7.io.iss_uop.br_type connect issue_slots[7].iss_uop.br_tag, slots_7.io.iss_uop.br_tag connect issue_slots[7].iss_uop.br_mask, slots_7.io.iss_uop.br_mask connect issue_slots[7].iss_uop.dis_col_sel, slots_7.io.iss_uop.dis_col_sel connect issue_slots[7].iss_uop.iw_p3_bypass_hint, slots_7.io.iss_uop.iw_p3_bypass_hint connect issue_slots[7].iss_uop.iw_p2_bypass_hint, slots_7.io.iss_uop.iw_p2_bypass_hint connect issue_slots[7].iss_uop.iw_p1_bypass_hint, slots_7.io.iss_uop.iw_p1_bypass_hint connect issue_slots[7].iss_uop.iw_p2_speculative_child, slots_7.io.iss_uop.iw_p2_speculative_child connect issue_slots[7].iss_uop.iw_p1_speculative_child, slots_7.io.iss_uop.iw_p1_speculative_child connect issue_slots[7].iss_uop.iw_issued_partial_dgen, slots_7.io.iss_uop.iw_issued_partial_dgen connect issue_slots[7].iss_uop.iw_issued_partial_agen, slots_7.io.iss_uop.iw_issued_partial_agen connect issue_slots[7].iss_uop.iw_issued, slots_7.io.iss_uop.iw_issued connect issue_slots[7].iss_uop.fu_code[0], slots_7.io.iss_uop.fu_code[0] connect issue_slots[7].iss_uop.fu_code[1], slots_7.io.iss_uop.fu_code[1] connect issue_slots[7].iss_uop.fu_code[2], slots_7.io.iss_uop.fu_code[2] connect issue_slots[7].iss_uop.fu_code[3], slots_7.io.iss_uop.fu_code[3] connect issue_slots[7].iss_uop.fu_code[4], slots_7.io.iss_uop.fu_code[4] connect issue_slots[7].iss_uop.fu_code[5], slots_7.io.iss_uop.fu_code[5] connect issue_slots[7].iss_uop.fu_code[6], slots_7.io.iss_uop.fu_code[6] connect issue_slots[7].iss_uop.fu_code[7], slots_7.io.iss_uop.fu_code[7] connect issue_slots[7].iss_uop.fu_code[8], slots_7.io.iss_uop.fu_code[8] connect issue_slots[7].iss_uop.fu_code[9], slots_7.io.iss_uop.fu_code[9] connect issue_slots[7].iss_uop.iq_type[0], slots_7.io.iss_uop.iq_type[0] connect issue_slots[7].iss_uop.iq_type[1], slots_7.io.iss_uop.iq_type[1] connect issue_slots[7].iss_uop.iq_type[2], slots_7.io.iss_uop.iq_type[2] connect issue_slots[7].iss_uop.iq_type[3], slots_7.io.iss_uop.iq_type[3] connect issue_slots[7].iss_uop.debug_pc, slots_7.io.iss_uop.debug_pc connect issue_slots[7].iss_uop.is_rvc, slots_7.io.iss_uop.is_rvc connect issue_slots[7].iss_uop.debug_inst, slots_7.io.iss_uop.debug_inst connect issue_slots[7].iss_uop.inst, slots_7.io.iss_uop.inst connect slots_7.io.grant, issue_slots[7].grant connect issue_slots[7].request, slots_7.io.request connect issue_slots[7].will_be_valid, slots_7.io.will_be_valid connect issue_slots[7].valid, slots_7.io.valid connect slots_8.io.child_rebusys, issue_slots[8].child_rebusys connect slots_8.io.pred_wakeup_port.bits, issue_slots[8].pred_wakeup_port.bits connect slots_8.io.pred_wakeup_port.valid, issue_slots[8].pred_wakeup_port.valid connect slots_8.io.wakeup_ports[0].bits.rebusy, issue_slots[8].wakeup_ports[0].bits.rebusy connect slots_8.io.wakeup_ports[0].bits.speculative_mask, issue_slots[8].wakeup_ports[0].bits.speculative_mask connect slots_8.io.wakeup_ports[0].bits.bypassable, issue_slots[8].wakeup_ports[0].bits.bypassable connect slots_8.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[8].wakeup_ports[0].bits.uop.debug_tsrc connect slots_8.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[8].wakeup_ports[0].bits.uop.debug_fsrc connect slots_8.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[8].wakeup_ports[0].bits.uop.bp_xcpt_if connect slots_8.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[8].wakeup_ports[0].bits.uop.bp_debug_if connect slots_8.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[8].wakeup_ports[0].bits.uop.xcpt_ma_if connect slots_8.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[8].wakeup_ports[0].bits.uop.xcpt_ae_if connect slots_8.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[8].wakeup_ports[0].bits.uop.xcpt_pf_if connect slots_8.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[8].wakeup_ports[0].bits.uop.fp_typ connect slots_8.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[8].wakeup_ports[0].bits.uop.fp_rm connect slots_8.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[8].wakeup_ports[0].bits.uop.fp_val connect slots_8.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[8].wakeup_ports[0].bits.uop.fcn_op connect slots_8.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[8].wakeup_ports[0].bits.uop.fcn_dw connect slots_8.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[8].wakeup_ports[0].bits.uop.frs3_en connect slots_8.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[8].wakeup_ports[0].bits.uop.lrs2_rtype connect slots_8.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[8].wakeup_ports[0].bits.uop.lrs1_rtype connect slots_8.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[8].wakeup_ports[0].bits.uop.dst_rtype connect slots_8.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[8].wakeup_ports[0].bits.uop.lrs3 connect slots_8.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[8].wakeup_ports[0].bits.uop.lrs2 connect slots_8.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[8].wakeup_ports[0].bits.uop.lrs1 connect slots_8.io.wakeup_ports[0].bits.uop.ldst, issue_slots[8].wakeup_ports[0].bits.uop.ldst connect slots_8.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[8].wakeup_ports[0].bits.uop.ldst_is_rs1 connect slots_8.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[8].wakeup_ports[0].bits.uop.csr_cmd connect slots_8.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[8].wakeup_ports[0].bits.uop.flush_on_commit connect slots_8.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[8].wakeup_ports[0].bits.uop.is_unique connect slots_8.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[8].wakeup_ports[0].bits.uop.uses_stq connect slots_8.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[8].wakeup_ports[0].bits.uop.uses_ldq connect slots_8.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[8].wakeup_ports[0].bits.uop.mem_signed connect slots_8.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[8].wakeup_ports[0].bits.uop.mem_size connect slots_8.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[8].wakeup_ports[0].bits.uop.mem_cmd connect slots_8.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[8].wakeup_ports[0].bits.uop.exc_cause connect slots_8.io.wakeup_ports[0].bits.uop.exception, issue_slots[8].wakeup_ports[0].bits.uop.exception connect slots_8.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[8].wakeup_ports[0].bits.uop.stale_pdst connect slots_8.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[8].wakeup_ports[0].bits.uop.ppred_busy connect slots_8.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[8].wakeup_ports[0].bits.uop.prs3_busy connect slots_8.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[8].wakeup_ports[0].bits.uop.prs2_busy connect slots_8.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[8].wakeup_ports[0].bits.uop.prs1_busy connect slots_8.io.wakeup_ports[0].bits.uop.ppred, issue_slots[8].wakeup_ports[0].bits.uop.ppred connect slots_8.io.wakeup_ports[0].bits.uop.prs3, issue_slots[8].wakeup_ports[0].bits.uop.prs3 connect slots_8.io.wakeup_ports[0].bits.uop.prs2, issue_slots[8].wakeup_ports[0].bits.uop.prs2 connect slots_8.io.wakeup_ports[0].bits.uop.prs1, issue_slots[8].wakeup_ports[0].bits.uop.prs1 connect slots_8.io.wakeup_ports[0].bits.uop.pdst, issue_slots[8].wakeup_ports[0].bits.uop.pdst connect slots_8.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[8].wakeup_ports[0].bits.uop.rxq_idx connect slots_8.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[8].wakeup_ports[0].bits.uop.stq_idx connect slots_8.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[8].wakeup_ports[0].bits.uop.ldq_idx connect slots_8.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[8].wakeup_ports[0].bits.uop.rob_idx connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.vec connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.wflags connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.div connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.fma connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.toint connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.fromint connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.wen connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.ldst connect slots_8.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[8].wakeup_ports[0].bits.uop.op2_sel connect slots_8.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[8].wakeup_ports[0].bits.uop.op1_sel connect slots_8.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[8].wakeup_ports[0].bits.uop.imm_packed connect slots_8.io.wakeup_ports[0].bits.uop.pimm, issue_slots[8].wakeup_ports[0].bits.uop.pimm connect slots_8.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[8].wakeup_ports[0].bits.uop.imm_sel connect slots_8.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[8].wakeup_ports[0].bits.uop.imm_rename connect slots_8.io.wakeup_ports[0].bits.uop.taken, issue_slots[8].wakeup_ports[0].bits.uop.taken connect slots_8.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[8].wakeup_ports[0].bits.uop.pc_lob connect slots_8.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[8].wakeup_ports[0].bits.uop.edge_inst connect slots_8.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[8].wakeup_ports[0].bits.uop.ftq_idx connect slots_8.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[8].wakeup_ports[0].bits.uop.is_mov connect slots_8.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[8].wakeup_ports[0].bits.uop.is_rocc connect slots_8.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[8].wakeup_ports[0].bits.uop.is_sys_pc2epc connect slots_8.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[8].wakeup_ports[0].bits.uop.is_eret connect slots_8.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[8].wakeup_ports[0].bits.uop.is_amo connect slots_8.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[8].wakeup_ports[0].bits.uop.is_sfence connect slots_8.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[8].wakeup_ports[0].bits.uop.is_fencei connect slots_8.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[8].wakeup_ports[0].bits.uop.is_fence connect slots_8.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[8].wakeup_ports[0].bits.uop.is_sfb connect slots_8.io.wakeup_ports[0].bits.uop.br_type, issue_slots[8].wakeup_ports[0].bits.uop.br_type connect slots_8.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[8].wakeup_ports[0].bits.uop.br_tag connect slots_8.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[8].wakeup_ports[0].bits.uop.br_mask connect slots_8.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[8].wakeup_ports[0].bits.uop.dis_col_sel connect slots_8.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[8].wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect slots_8.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[8].wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect slots_8.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[8].wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect slots_8.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[8].wakeup_ports[0].bits.uop.iw_p2_speculative_child connect slots_8.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[8].wakeup_ports[0].bits.uop.iw_p1_speculative_child connect slots_8.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[8].wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect slots_8.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[8].wakeup_ports[0].bits.uop.iw_issued_partial_agen connect slots_8.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[8].wakeup_ports[0].bits.uop.iw_issued connect slots_8.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[8].wakeup_ports[0].bits.uop.fu_code[0] connect slots_8.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[8].wakeup_ports[0].bits.uop.fu_code[1] connect slots_8.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[8].wakeup_ports[0].bits.uop.fu_code[2] connect slots_8.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[8].wakeup_ports[0].bits.uop.fu_code[3] connect slots_8.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[8].wakeup_ports[0].bits.uop.fu_code[4] connect slots_8.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[8].wakeup_ports[0].bits.uop.fu_code[5] connect slots_8.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[8].wakeup_ports[0].bits.uop.fu_code[6] connect slots_8.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[8].wakeup_ports[0].bits.uop.fu_code[7] connect slots_8.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[8].wakeup_ports[0].bits.uop.fu_code[8] connect slots_8.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[8].wakeup_ports[0].bits.uop.fu_code[9] connect slots_8.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[8].wakeup_ports[0].bits.uop.iq_type[0] connect slots_8.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[8].wakeup_ports[0].bits.uop.iq_type[1] connect slots_8.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[8].wakeup_ports[0].bits.uop.iq_type[2] connect slots_8.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[8].wakeup_ports[0].bits.uop.iq_type[3] connect slots_8.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[8].wakeup_ports[0].bits.uop.debug_pc connect slots_8.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[8].wakeup_ports[0].bits.uop.is_rvc connect slots_8.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[8].wakeup_ports[0].bits.uop.debug_inst connect slots_8.io.wakeup_ports[0].bits.uop.inst, issue_slots[8].wakeup_ports[0].bits.uop.inst connect slots_8.io.wakeup_ports[0].valid, issue_slots[8].wakeup_ports[0].valid connect slots_8.io.wakeup_ports[1].bits.rebusy, issue_slots[8].wakeup_ports[1].bits.rebusy connect slots_8.io.wakeup_ports[1].bits.speculative_mask, issue_slots[8].wakeup_ports[1].bits.speculative_mask connect slots_8.io.wakeup_ports[1].bits.bypassable, issue_slots[8].wakeup_ports[1].bits.bypassable connect slots_8.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[8].wakeup_ports[1].bits.uop.debug_tsrc connect slots_8.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[8].wakeup_ports[1].bits.uop.debug_fsrc connect slots_8.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[8].wakeup_ports[1].bits.uop.bp_xcpt_if connect slots_8.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[8].wakeup_ports[1].bits.uop.bp_debug_if connect slots_8.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[8].wakeup_ports[1].bits.uop.xcpt_ma_if connect slots_8.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[8].wakeup_ports[1].bits.uop.xcpt_ae_if connect slots_8.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[8].wakeup_ports[1].bits.uop.xcpt_pf_if connect slots_8.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[8].wakeup_ports[1].bits.uop.fp_typ connect slots_8.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[8].wakeup_ports[1].bits.uop.fp_rm connect slots_8.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[8].wakeup_ports[1].bits.uop.fp_val connect slots_8.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[8].wakeup_ports[1].bits.uop.fcn_op connect slots_8.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[8].wakeup_ports[1].bits.uop.fcn_dw connect slots_8.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[8].wakeup_ports[1].bits.uop.frs3_en connect slots_8.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[8].wakeup_ports[1].bits.uop.lrs2_rtype connect slots_8.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[8].wakeup_ports[1].bits.uop.lrs1_rtype connect slots_8.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[8].wakeup_ports[1].bits.uop.dst_rtype connect slots_8.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[8].wakeup_ports[1].bits.uop.lrs3 connect slots_8.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[8].wakeup_ports[1].bits.uop.lrs2 connect slots_8.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[8].wakeup_ports[1].bits.uop.lrs1 connect slots_8.io.wakeup_ports[1].bits.uop.ldst, issue_slots[8].wakeup_ports[1].bits.uop.ldst connect slots_8.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[8].wakeup_ports[1].bits.uop.ldst_is_rs1 connect slots_8.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[8].wakeup_ports[1].bits.uop.csr_cmd connect slots_8.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[8].wakeup_ports[1].bits.uop.flush_on_commit connect slots_8.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[8].wakeup_ports[1].bits.uop.is_unique connect slots_8.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[8].wakeup_ports[1].bits.uop.uses_stq connect slots_8.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[8].wakeup_ports[1].bits.uop.uses_ldq connect slots_8.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[8].wakeup_ports[1].bits.uop.mem_signed connect slots_8.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[8].wakeup_ports[1].bits.uop.mem_size connect slots_8.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[8].wakeup_ports[1].bits.uop.mem_cmd connect slots_8.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[8].wakeup_ports[1].bits.uop.exc_cause connect slots_8.io.wakeup_ports[1].bits.uop.exception, issue_slots[8].wakeup_ports[1].bits.uop.exception connect slots_8.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[8].wakeup_ports[1].bits.uop.stale_pdst connect slots_8.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[8].wakeup_ports[1].bits.uop.ppred_busy connect slots_8.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[8].wakeup_ports[1].bits.uop.prs3_busy connect slots_8.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[8].wakeup_ports[1].bits.uop.prs2_busy connect slots_8.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[8].wakeup_ports[1].bits.uop.prs1_busy connect slots_8.io.wakeup_ports[1].bits.uop.ppred, issue_slots[8].wakeup_ports[1].bits.uop.ppred connect slots_8.io.wakeup_ports[1].bits.uop.prs3, issue_slots[8].wakeup_ports[1].bits.uop.prs3 connect slots_8.io.wakeup_ports[1].bits.uop.prs2, issue_slots[8].wakeup_ports[1].bits.uop.prs2 connect slots_8.io.wakeup_ports[1].bits.uop.prs1, issue_slots[8].wakeup_ports[1].bits.uop.prs1 connect slots_8.io.wakeup_ports[1].bits.uop.pdst, issue_slots[8].wakeup_ports[1].bits.uop.pdst connect slots_8.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[8].wakeup_ports[1].bits.uop.rxq_idx connect slots_8.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[8].wakeup_ports[1].bits.uop.stq_idx connect slots_8.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[8].wakeup_ports[1].bits.uop.ldq_idx connect slots_8.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[8].wakeup_ports[1].bits.uop.rob_idx connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.vec connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.wflags connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.div connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.fma connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.toint connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.fromint connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.wen connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.ldst connect slots_8.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[8].wakeup_ports[1].bits.uop.op2_sel connect slots_8.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[8].wakeup_ports[1].bits.uop.op1_sel connect slots_8.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[8].wakeup_ports[1].bits.uop.imm_packed connect slots_8.io.wakeup_ports[1].bits.uop.pimm, issue_slots[8].wakeup_ports[1].bits.uop.pimm connect slots_8.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[8].wakeup_ports[1].bits.uop.imm_sel connect slots_8.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[8].wakeup_ports[1].bits.uop.imm_rename connect slots_8.io.wakeup_ports[1].bits.uop.taken, issue_slots[8].wakeup_ports[1].bits.uop.taken connect slots_8.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[8].wakeup_ports[1].bits.uop.pc_lob connect slots_8.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[8].wakeup_ports[1].bits.uop.edge_inst connect slots_8.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[8].wakeup_ports[1].bits.uop.ftq_idx connect slots_8.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[8].wakeup_ports[1].bits.uop.is_mov connect slots_8.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[8].wakeup_ports[1].bits.uop.is_rocc connect slots_8.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[8].wakeup_ports[1].bits.uop.is_sys_pc2epc connect slots_8.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[8].wakeup_ports[1].bits.uop.is_eret connect slots_8.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[8].wakeup_ports[1].bits.uop.is_amo connect slots_8.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[8].wakeup_ports[1].bits.uop.is_sfence connect slots_8.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[8].wakeup_ports[1].bits.uop.is_fencei connect slots_8.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[8].wakeup_ports[1].bits.uop.is_fence connect slots_8.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[8].wakeup_ports[1].bits.uop.is_sfb connect slots_8.io.wakeup_ports[1].bits.uop.br_type, issue_slots[8].wakeup_ports[1].bits.uop.br_type connect slots_8.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[8].wakeup_ports[1].bits.uop.br_tag connect slots_8.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[8].wakeup_ports[1].bits.uop.br_mask connect slots_8.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[8].wakeup_ports[1].bits.uop.dis_col_sel connect slots_8.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[8].wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect slots_8.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[8].wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect slots_8.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[8].wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect slots_8.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[8].wakeup_ports[1].bits.uop.iw_p2_speculative_child connect slots_8.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[8].wakeup_ports[1].bits.uop.iw_p1_speculative_child connect slots_8.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[8].wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect slots_8.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[8].wakeup_ports[1].bits.uop.iw_issued_partial_agen connect slots_8.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[8].wakeup_ports[1].bits.uop.iw_issued connect slots_8.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[8].wakeup_ports[1].bits.uop.fu_code[0] connect slots_8.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[8].wakeup_ports[1].bits.uop.fu_code[1] connect slots_8.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[8].wakeup_ports[1].bits.uop.fu_code[2] connect slots_8.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[8].wakeup_ports[1].bits.uop.fu_code[3] connect slots_8.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[8].wakeup_ports[1].bits.uop.fu_code[4] connect slots_8.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[8].wakeup_ports[1].bits.uop.fu_code[5] connect slots_8.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[8].wakeup_ports[1].bits.uop.fu_code[6] connect slots_8.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[8].wakeup_ports[1].bits.uop.fu_code[7] connect slots_8.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[8].wakeup_ports[1].bits.uop.fu_code[8] connect slots_8.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[8].wakeup_ports[1].bits.uop.fu_code[9] connect slots_8.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[8].wakeup_ports[1].bits.uop.iq_type[0] connect slots_8.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[8].wakeup_ports[1].bits.uop.iq_type[1] connect slots_8.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[8].wakeup_ports[1].bits.uop.iq_type[2] connect slots_8.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[8].wakeup_ports[1].bits.uop.iq_type[3] connect slots_8.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[8].wakeup_ports[1].bits.uop.debug_pc connect slots_8.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[8].wakeup_ports[1].bits.uop.is_rvc connect slots_8.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[8].wakeup_ports[1].bits.uop.debug_inst connect slots_8.io.wakeup_ports[1].bits.uop.inst, issue_slots[8].wakeup_ports[1].bits.uop.inst connect slots_8.io.wakeup_ports[1].valid, issue_slots[8].wakeup_ports[1].valid connect slots_8.io.wakeup_ports[2].bits.rebusy, issue_slots[8].wakeup_ports[2].bits.rebusy connect slots_8.io.wakeup_ports[2].bits.speculative_mask, issue_slots[8].wakeup_ports[2].bits.speculative_mask connect slots_8.io.wakeup_ports[2].bits.bypassable, issue_slots[8].wakeup_ports[2].bits.bypassable connect slots_8.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[8].wakeup_ports[2].bits.uop.debug_tsrc connect slots_8.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[8].wakeup_ports[2].bits.uop.debug_fsrc connect slots_8.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[8].wakeup_ports[2].bits.uop.bp_xcpt_if connect slots_8.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[8].wakeup_ports[2].bits.uop.bp_debug_if connect slots_8.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[8].wakeup_ports[2].bits.uop.xcpt_ma_if connect slots_8.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[8].wakeup_ports[2].bits.uop.xcpt_ae_if connect slots_8.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[8].wakeup_ports[2].bits.uop.xcpt_pf_if connect slots_8.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[8].wakeup_ports[2].bits.uop.fp_typ connect slots_8.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[8].wakeup_ports[2].bits.uop.fp_rm connect slots_8.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[8].wakeup_ports[2].bits.uop.fp_val connect slots_8.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[8].wakeup_ports[2].bits.uop.fcn_op connect slots_8.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[8].wakeup_ports[2].bits.uop.fcn_dw connect slots_8.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[8].wakeup_ports[2].bits.uop.frs3_en connect slots_8.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[8].wakeup_ports[2].bits.uop.lrs2_rtype connect slots_8.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[8].wakeup_ports[2].bits.uop.lrs1_rtype connect slots_8.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[8].wakeup_ports[2].bits.uop.dst_rtype connect slots_8.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[8].wakeup_ports[2].bits.uop.lrs3 connect slots_8.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[8].wakeup_ports[2].bits.uop.lrs2 connect slots_8.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[8].wakeup_ports[2].bits.uop.lrs1 connect slots_8.io.wakeup_ports[2].bits.uop.ldst, issue_slots[8].wakeup_ports[2].bits.uop.ldst connect slots_8.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[8].wakeup_ports[2].bits.uop.ldst_is_rs1 connect slots_8.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[8].wakeup_ports[2].bits.uop.csr_cmd connect slots_8.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[8].wakeup_ports[2].bits.uop.flush_on_commit connect slots_8.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[8].wakeup_ports[2].bits.uop.is_unique connect slots_8.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[8].wakeup_ports[2].bits.uop.uses_stq connect slots_8.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[8].wakeup_ports[2].bits.uop.uses_ldq connect slots_8.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[8].wakeup_ports[2].bits.uop.mem_signed connect slots_8.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[8].wakeup_ports[2].bits.uop.mem_size connect slots_8.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[8].wakeup_ports[2].bits.uop.mem_cmd connect slots_8.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[8].wakeup_ports[2].bits.uop.exc_cause connect slots_8.io.wakeup_ports[2].bits.uop.exception, issue_slots[8].wakeup_ports[2].bits.uop.exception connect slots_8.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[8].wakeup_ports[2].bits.uop.stale_pdst connect slots_8.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[8].wakeup_ports[2].bits.uop.ppred_busy connect slots_8.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[8].wakeup_ports[2].bits.uop.prs3_busy connect slots_8.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[8].wakeup_ports[2].bits.uop.prs2_busy connect slots_8.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[8].wakeup_ports[2].bits.uop.prs1_busy connect slots_8.io.wakeup_ports[2].bits.uop.ppred, issue_slots[8].wakeup_ports[2].bits.uop.ppred connect slots_8.io.wakeup_ports[2].bits.uop.prs3, issue_slots[8].wakeup_ports[2].bits.uop.prs3 connect slots_8.io.wakeup_ports[2].bits.uop.prs2, issue_slots[8].wakeup_ports[2].bits.uop.prs2 connect slots_8.io.wakeup_ports[2].bits.uop.prs1, issue_slots[8].wakeup_ports[2].bits.uop.prs1 connect slots_8.io.wakeup_ports[2].bits.uop.pdst, issue_slots[8].wakeup_ports[2].bits.uop.pdst connect slots_8.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[8].wakeup_ports[2].bits.uop.rxq_idx connect slots_8.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[8].wakeup_ports[2].bits.uop.stq_idx connect slots_8.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[8].wakeup_ports[2].bits.uop.ldq_idx connect slots_8.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[8].wakeup_ports[2].bits.uop.rob_idx connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.vec connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.wflags connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.div connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.fma connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.toint connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.fromint connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.wen connect slots_8.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.ldst connect slots_8.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[8].wakeup_ports[2].bits.uop.op2_sel connect slots_8.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[8].wakeup_ports[2].bits.uop.op1_sel connect slots_8.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[8].wakeup_ports[2].bits.uop.imm_packed connect slots_8.io.wakeup_ports[2].bits.uop.pimm, issue_slots[8].wakeup_ports[2].bits.uop.pimm connect slots_8.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[8].wakeup_ports[2].bits.uop.imm_sel connect slots_8.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[8].wakeup_ports[2].bits.uop.imm_rename connect slots_8.io.wakeup_ports[2].bits.uop.taken, issue_slots[8].wakeup_ports[2].bits.uop.taken connect slots_8.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[8].wakeup_ports[2].bits.uop.pc_lob connect slots_8.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[8].wakeup_ports[2].bits.uop.edge_inst connect slots_8.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[8].wakeup_ports[2].bits.uop.ftq_idx connect slots_8.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[8].wakeup_ports[2].bits.uop.is_mov connect slots_8.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[8].wakeup_ports[2].bits.uop.is_rocc connect slots_8.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[8].wakeup_ports[2].bits.uop.is_sys_pc2epc connect slots_8.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[8].wakeup_ports[2].bits.uop.is_eret connect slots_8.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[8].wakeup_ports[2].bits.uop.is_amo connect slots_8.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[8].wakeup_ports[2].bits.uop.is_sfence connect slots_8.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[8].wakeup_ports[2].bits.uop.is_fencei connect slots_8.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[8].wakeup_ports[2].bits.uop.is_fence connect slots_8.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[8].wakeup_ports[2].bits.uop.is_sfb connect slots_8.io.wakeup_ports[2].bits.uop.br_type, issue_slots[8].wakeup_ports[2].bits.uop.br_type connect slots_8.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[8].wakeup_ports[2].bits.uop.br_tag connect slots_8.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[8].wakeup_ports[2].bits.uop.br_mask connect slots_8.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[8].wakeup_ports[2].bits.uop.dis_col_sel connect slots_8.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[8].wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect slots_8.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[8].wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect slots_8.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[8].wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect slots_8.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[8].wakeup_ports[2].bits.uop.iw_p2_speculative_child connect slots_8.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[8].wakeup_ports[2].bits.uop.iw_p1_speculative_child connect slots_8.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[8].wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect slots_8.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[8].wakeup_ports[2].bits.uop.iw_issued_partial_agen connect slots_8.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[8].wakeup_ports[2].bits.uop.iw_issued connect slots_8.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[8].wakeup_ports[2].bits.uop.fu_code[0] connect slots_8.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[8].wakeup_ports[2].bits.uop.fu_code[1] connect slots_8.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[8].wakeup_ports[2].bits.uop.fu_code[2] connect slots_8.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[8].wakeup_ports[2].bits.uop.fu_code[3] connect slots_8.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[8].wakeup_ports[2].bits.uop.fu_code[4] connect slots_8.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[8].wakeup_ports[2].bits.uop.fu_code[5] connect slots_8.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[8].wakeup_ports[2].bits.uop.fu_code[6] connect slots_8.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[8].wakeup_ports[2].bits.uop.fu_code[7] connect slots_8.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[8].wakeup_ports[2].bits.uop.fu_code[8] connect slots_8.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[8].wakeup_ports[2].bits.uop.fu_code[9] connect slots_8.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[8].wakeup_ports[2].bits.uop.iq_type[0] connect slots_8.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[8].wakeup_ports[2].bits.uop.iq_type[1] connect slots_8.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[8].wakeup_ports[2].bits.uop.iq_type[2] connect slots_8.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[8].wakeup_ports[2].bits.uop.iq_type[3] connect slots_8.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[8].wakeup_ports[2].bits.uop.debug_pc connect slots_8.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[8].wakeup_ports[2].bits.uop.is_rvc connect slots_8.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[8].wakeup_ports[2].bits.uop.debug_inst connect slots_8.io.wakeup_ports[2].bits.uop.inst, issue_slots[8].wakeup_ports[2].bits.uop.inst connect slots_8.io.wakeup_ports[2].valid, issue_slots[8].wakeup_ports[2].valid connect slots_8.io.wakeup_ports[3].bits.rebusy, issue_slots[8].wakeup_ports[3].bits.rebusy connect slots_8.io.wakeup_ports[3].bits.speculative_mask, issue_slots[8].wakeup_ports[3].bits.speculative_mask connect slots_8.io.wakeup_ports[3].bits.bypassable, issue_slots[8].wakeup_ports[3].bits.bypassable connect slots_8.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[8].wakeup_ports[3].bits.uop.debug_tsrc connect slots_8.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[8].wakeup_ports[3].bits.uop.debug_fsrc connect slots_8.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[8].wakeup_ports[3].bits.uop.bp_xcpt_if connect slots_8.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[8].wakeup_ports[3].bits.uop.bp_debug_if connect slots_8.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[8].wakeup_ports[3].bits.uop.xcpt_ma_if connect slots_8.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[8].wakeup_ports[3].bits.uop.xcpt_ae_if connect slots_8.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[8].wakeup_ports[3].bits.uop.xcpt_pf_if connect slots_8.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[8].wakeup_ports[3].bits.uop.fp_typ connect slots_8.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[8].wakeup_ports[3].bits.uop.fp_rm connect slots_8.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[8].wakeup_ports[3].bits.uop.fp_val connect slots_8.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[8].wakeup_ports[3].bits.uop.fcn_op connect slots_8.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[8].wakeup_ports[3].bits.uop.fcn_dw connect slots_8.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[8].wakeup_ports[3].bits.uop.frs3_en connect slots_8.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[8].wakeup_ports[3].bits.uop.lrs2_rtype connect slots_8.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[8].wakeup_ports[3].bits.uop.lrs1_rtype connect slots_8.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[8].wakeup_ports[3].bits.uop.dst_rtype connect slots_8.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[8].wakeup_ports[3].bits.uop.lrs3 connect slots_8.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[8].wakeup_ports[3].bits.uop.lrs2 connect slots_8.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[8].wakeup_ports[3].bits.uop.lrs1 connect slots_8.io.wakeup_ports[3].bits.uop.ldst, issue_slots[8].wakeup_ports[3].bits.uop.ldst connect slots_8.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[8].wakeup_ports[3].bits.uop.ldst_is_rs1 connect slots_8.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[8].wakeup_ports[3].bits.uop.csr_cmd connect slots_8.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[8].wakeup_ports[3].bits.uop.flush_on_commit connect slots_8.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[8].wakeup_ports[3].bits.uop.is_unique connect slots_8.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[8].wakeup_ports[3].bits.uop.uses_stq connect slots_8.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[8].wakeup_ports[3].bits.uop.uses_ldq connect slots_8.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[8].wakeup_ports[3].bits.uop.mem_signed connect slots_8.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[8].wakeup_ports[3].bits.uop.mem_size connect slots_8.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[8].wakeup_ports[3].bits.uop.mem_cmd connect slots_8.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[8].wakeup_ports[3].bits.uop.exc_cause connect slots_8.io.wakeup_ports[3].bits.uop.exception, issue_slots[8].wakeup_ports[3].bits.uop.exception connect slots_8.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[8].wakeup_ports[3].bits.uop.stale_pdst connect slots_8.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[8].wakeup_ports[3].bits.uop.ppred_busy connect slots_8.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[8].wakeup_ports[3].bits.uop.prs3_busy connect slots_8.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[8].wakeup_ports[3].bits.uop.prs2_busy connect slots_8.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[8].wakeup_ports[3].bits.uop.prs1_busy connect slots_8.io.wakeup_ports[3].bits.uop.ppred, issue_slots[8].wakeup_ports[3].bits.uop.ppred connect slots_8.io.wakeup_ports[3].bits.uop.prs3, issue_slots[8].wakeup_ports[3].bits.uop.prs3 connect slots_8.io.wakeup_ports[3].bits.uop.prs2, issue_slots[8].wakeup_ports[3].bits.uop.prs2 connect slots_8.io.wakeup_ports[3].bits.uop.prs1, issue_slots[8].wakeup_ports[3].bits.uop.prs1 connect slots_8.io.wakeup_ports[3].bits.uop.pdst, issue_slots[8].wakeup_ports[3].bits.uop.pdst connect slots_8.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[8].wakeup_ports[3].bits.uop.rxq_idx connect slots_8.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[8].wakeup_ports[3].bits.uop.stq_idx connect slots_8.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[8].wakeup_ports[3].bits.uop.ldq_idx connect slots_8.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[8].wakeup_ports[3].bits.uop.rob_idx connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.vec connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.wflags connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.div connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.fma connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.toint connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.fromint connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.wen connect slots_8.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.ldst connect slots_8.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[8].wakeup_ports[3].bits.uop.op2_sel connect slots_8.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[8].wakeup_ports[3].bits.uop.op1_sel connect slots_8.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[8].wakeup_ports[3].bits.uop.imm_packed connect slots_8.io.wakeup_ports[3].bits.uop.pimm, issue_slots[8].wakeup_ports[3].bits.uop.pimm connect slots_8.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[8].wakeup_ports[3].bits.uop.imm_sel connect slots_8.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[8].wakeup_ports[3].bits.uop.imm_rename connect slots_8.io.wakeup_ports[3].bits.uop.taken, issue_slots[8].wakeup_ports[3].bits.uop.taken connect slots_8.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[8].wakeup_ports[3].bits.uop.pc_lob connect slots_8.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[8].wakeup_ports[3].bits.uop.edge_inst connect slots_8.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[8].wakeup_ports[3].bits.uop.ftq_idx connect slots_8.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[8].wakeup_ports[3].bits.uop.is_mov connect slots_8.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[8].wakeup_ports[3].bits.uop.is_rocc connect slots_8.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[8].wakeup_ports[3].bits.uop.is_sys_pc2epc connect slots_8.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[8].wakeup_ports[3].bits.uop.is_eret connect slots_8.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[8].wakeup_ports[3].bits.uop.is_amo connect slots_8.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[8].wakeup_ports[3].bits.uop.is_sfence connect slots_8.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[8].wakeup_ports[3].bits.uop.is_fencei connect slots_8.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[8].wakeup_ports[3].bits.uop.is_fence connect slots_8.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[8].wakeup_ports[3].bits.uop.is_sfb connect slots_8.io.wakeup_ports[3].bits.uop.br_type, issue_slots[8].wakeup_ports[3].bits.uop.br_type connect slots_8.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[8].wakeup_ports[3].bits.uop.br_tag connect slots_8.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[8].wakeup_ports[3].bits.uop.br_mask connect slots_8.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[8].wakeup_ports[3].bits.uop.dis_col_sel connect slots_8.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[8].wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect slots_8.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[8].wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect slots_8.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[8].wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect slots_8.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[8].wakeup_ports[3].bits.uop.iw_p2_speculative_child connect slots_8.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[8].wakeup_ports[3].bits.uop.iw_p1_speculative_child connect slots_8.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[8].wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect slots_8.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[8].wakeup_ports[3].bits.uop.iw_issued_partial_agen connect slots_8.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[8].wakeup_ports[3].bits.uop.iw_issued connect slots_8.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[8].wakeup_ports[3].bits.uop.fu_code[0] connect slots_8.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[8].wakeup_ports[3].bits.uop.fu_code[1] connect slots_8.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[8].wakeup_ports[3].bits.uop.fu_code[2] connect slots_8.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[8].wakeup_ports[3].bits.uop.fu_code[3] connect slots_8.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[8].wakeup_ports[3].bits.uop.fu_code[4] connect slots_8.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[8].wakeup_ports[3].bits.uop.fu_code[5] connect slots_8.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[8].wakeup_ports[3].bits.uop.fu_code[6] connect slots_8.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[8].wakeup_ports[3].bits.uop.fu_code[7] connect slots_8.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[8].wakeup_ports[3].bits.uop.fu_code[8] connect slots_8.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[8].wakeup_ports[3].bits.uop.fu_code[9] connect slots_8.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[8].wakeup_ports[3].bits.uop.iq_type[0] connect slots_8.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[8].wakeup_ports[3].bits.uop.iq_type[1] connect slots_8.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[8].wakeup_ports[3].bits.uop.iq_type[2] connect slots_8.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[8].wakeup_ports[3].bits.uop.iq_type[3] connect slots_8.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[8].wakeup_ports[3].bits.uop.debug_pc connect slots_8.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[8].wakeup_ports[3].bits.uop.is_rvc connect slots_8.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[8].wakeup_ports[3].bits.uop.debug_inst connect slots_8.io.wakeup_ports[3].bits.uop.inst, issue_slots[8].wakeup_ports[3].bits.uop.inst connect slots_8.io.wakeup_ports[3].valid, issue_slots[8].wakeup_ports[3].valid connect slots_8.io.wakeup_ports[4].bits.rebusy, issue_slots[8].wakeup_ports[4].bits.rebusy connect slots_8.io.wakeup_ports[4].bits.speculative_mask, issue_slots[8].wakeup_ports[4].bits.speculative_mask connect slots_8.io.wakeup_ports[4].bits.bypassable, issue_slots[8].wakeup_ports[4].bits.bypassable connect slots_8.io.wakeup_ports[4].bits.uop.debug_tsrc, issue_slots[8].wakeup_ports[4].bits.uop.debug_tsrc connect slots_8.io.wakeup_ports[4].bits.uop.debug_fsrc, issue_slots[8].wakeup_ports[4].bits.uop.debug_fsrc connect slots_8.io.wakeup_ports[4].bits.uop.bp_xcpt_if, issue_slots[8].wakeup_ports[4].bits.uop.bp_xcpt_if connect slots_8.io.wakeup_ports[4].bits.uop.bp_debug_if, issue_slots[8].wakeup_ports[4].bits.uop.bp_debug_if connect slots_8.io.wakeup_ports[4].bits.uop.xcpt_ma_if, issue_slots[8].wakeup_ports[4].bits.uop.xcpt_ma_if connect slots_8.io.wakeup_ports[4].bits.uop.xcpt_ae_if, issue_slots[8].wakeup_ports[4].bits.uop.xcpt_ae_if connect slots_8.io.wakeup_ports[4].bits.uop.xcpt_pf_if, issue_slots[8].wakeup_ports[4].bits.uop.xcpt_pf_if connect slots_8.io.wakeup_ports[4].bits.uop.fp_typ, issue_slots[8].wakeup_ports[4].bits.uop.fp_typ connect slots_8.io.wakeup_ports[4].bits.uop.fp_rm, issue_slots[8].wakeup_ports[4].bits.uop.fp_rm connect slots_8.io.wakeup_ports[4].bits.uop.fp_val, issue_slots[8].wakeup_ports[4].bits.uop.fp_val connect slots_8.io.wakeup_ports[4].bits.uop.fcn_op, issue_slots[8].wakeup_ports[4].bits.uop.fcn_op connect slots_8.io.wakeup_ports[4].bits.uop.fcn_dw, issue_slots[8].wakeup_ports[4].bits.uop.fcn_dw connect slots_8.io.wakeup_ports[4].bits.uop.frs3_en, issue_slots[8].wakeup_ports[4].bits.uop.frs3_en connect slots_8.io.wakeup_ports[4].bits.uop.lrs2_rtype, issue_slots[8].wakeup_ports[4].bits.uop.lrs2_rtype connect slots_8.io.wakeup_ports[4].bits.uop.lrs1_rtype, issue_slots[8].wakeup_ports[4].bits.uop.lrs1_rtype connect slots_8.io.wakeup_ports[4].bits.uop.dst_rtype, issue_slots[8].wakeup_ports[4].bits.uop.dst_rtype connect slots_8.io.wakeup_ports[4].bits.uop.lrs3, issue_slots[8].wakeup_ports[4].bits.uop.lrs3 connect slots_8.io.wakeup_ports[4].bits.uop.lrs2, issue_slots[8].wakeup_ports[4].bits.uop.lrs2 connect slots_8.io.wakeup_ports[4].bits.uop.lrs1, issue_slots[8].wakeup_ports[4].bits.uop.lrs1 connect slots_8.io.wakeup_ports[4].bits.uop.ldst, issue_slots[8].wakeup_ports[4].bits.uop.ldst connect slots_8.io.wakeup_ports[4].bits.uop.ldst_is_rs1, issue_slots[8].wakeup_ports[4].bits.uop.ldst_is_rs1 connect slots_8.io.wakeup_ports[4].bits.uop.csr_cmd, issue_slots[8].wakeup_ports[4].bits.uop.csr_cmd connect slots_8.io.wakeup_ports[4].bits.uop.flush_on_commit, issue_slots[8].wakeup_ports[4].bits.uop.flush_on_commit connect slots_8.io.wakeup_ports[4].bits.uop.is_unique, issue_slots[8].wakeup_ports[4].bits.uop.is_unique connect slots_8.io.wakeup_ports[4].bits.uop.uses_stq, issue_slots[8].wakeup_ports[4].bits.uop.uses_stq connect slots_8.io.wakeup_ports[4].bits.uop.uses_ldq, issue_slots[8].wakeup_ports[4].bits.uop.uses_ldq connect slots_8.io.wakeup_ports[4].bits.uop.mem_signed, issue_slots[8].wakeup_ports[4].bits.uop.mem_signed connect slots_8.io.wakeup_ports[4].bits.uop.mem_size, issue_slots[8].wakeup_ports[4].bits.uop.mem_size connect slots_8.io.wakeup_ports[4].bits.uop.mem_cmd, issue_slots[8].wakeup_ports[4].bits.uop.mem_cmd connect slots_8.io.wakeup_ports[4].bits.uop.exc_cause, issue_slots[8].wakeup_ports[4].bits.uop.exc_cause connect slots_8.io.wakeup_ports[4].bits.uop.exception, issue_slots[8].wakeup_ports[4].bits.uop.exception connect slots_8.io.wakeup_ports[4].bits.uop.stale_pdst, issue_slots[8].wakeup_ports[4].bits.uop.stale_pdst connect slots_8.io.wakeup_ports[4].bits.uop.ppred_busy, issue_slots[8].wakeup_ports[4].bits.uop.ppred_busy connect slots_8.io.wakeup_ports[4].bits.uop.prs3_busy, issue_slots[8].wakeup_ports[4].bits.uop.prs3_busy connect slots_8.io.wakeup_ports[4].bits.uop.prs2_busy, issue_slots[8].wakeup_ports[4].bits.uop.prs2_busy connect slots_8.io.wakeup_ports[4].bits.uop.prs1_busy, issue_slots[8].wakeup_ports[4].bits.uop.prs1_busy connect slots_8.io.wakeup_ports[4].bits.uop.ppred, issue_slots[8].wakeup_ports[4].bits.uop.ppred connect slots_8.io.wakeup_ports[4].bits.uop.prs3, issue_slots[8].wakeup_ports[4].bits.uop.prs3 connect slots_8.io.wakeup_ports[4].bits.uop.prs2, issue_slots[8].wakeup_ports[4].bits.uop.prs2 connect slots_8.io.wakeup_ports[4].bits.uop.prs1, issue_slots[8].wakeup_ports[4].bits.uop.prs1 connect slots_8.io.wakeup_ports[4].bits.uop.pdst, issue_slots[8].wakeup_ports[4].bits.uop.pdst connect slots_8.io.wakeup_ports[4].bits.uop.rxq_idx, issue_slots[8].wakeup_ports[4].bits.uop.rxq_idx connect slots_8.io.wakeup_ports[4].bits.uop.stq_idx, issue_slots[8].wakeup_ports[4].bits.uop.stq_idx connect slots_8.io.wakeup_ports[4].bits.uop.ldq_idx, issue_slots[8].wakeup_ports[4].bits.uop.ldq_idx connect slots_8.io.wakeup_ports[4].bits.uop.rob_idx, issue_slots[8].wakeup_ports[4].bits.uop.rob_idx connect slots_8.io.wakeup_ports[4].bits.uop.fp_ctrl.vec, issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.vec connect slots_8.io.wakeup_ports[4].bits.uop.fp_ctrl.wflags, issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.wflags connect slots_8.io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt, issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect slots_8.io.wakeup_ports[4].bits.uop.fp_ctrl.div, issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.div connect slots_8.io.wakeup_ports[4].bits.uop.fp_ctrl.fma, issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.fma connect slots_8.io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect slots_8.io.wakeup_ports[4].bits.uop.fp_ctrl.toint, issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.toint connect slots_8.io.wakeup_ports[4].bits.uop.fp_ctrl.fromint, issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.fromint connect slots_8.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect slots_8.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect slots_8.io.wakeup_ports[4].bits.uop.fp_ctrl.swap23, issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect slots_8.io.wakeup_ports[4].bits.uop.fp_ctrl.swap12, issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect slots_8.io.wakeup_ports[4].bits.uop.fp_ctrl.ren3, issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect slots_8.io.wakeup_ports[4].bits.uop.fp_ctrl.ren2, issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect slots_8.io.wakeup_ports[4].bits.uop.fp_ctrl.ren1, issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect slots_8.io.wakeup_ports[4].bits.uop.fp_ctrl.wen, issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.wen connect slots_8.io.wakeup_ports[4].bits.uop.fp_ctrl.ldst, issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.ldst connect slots_8.io.wakeup_ports[4].bits.uop.op2_sel, issue_slots[8].wakeup_ports[4].bits.uop.op2_sel connect slots_8.io.wakeup_ports[4].bits.uop.op1_sel, issue_slots[8].wakeup_ports[4].bits.uop.op1_sel connect slots_8.io.wakeup_ports[4].bits.uop.imm_packed, issue_slots[8].wakeup_ports[4].bits.uop.imm_packed connect slots_8.io.wakeup_ports[4].bits.uop.pimm, issue_slots[8].wakeup_ports[4].bits.uop.pimm connect slots_8.io.wakeup_ports[4].bits.uop.imm_sel, issue_slots[8].wakeup_ports[4].bits.uop.imm_sel connect slots_8.io.wakeup_ports[4].bits.uop.imm_rename, issue_slots[8].wakeup_ports[4].bits.uop.imm_rename connect slots_8.io.wakeup_ports[4].bits.uop.taken, issue_slots[8].wakeup_ports[4].bits.uop.taken connect slots_8.io.wakeup_ports[4].bits.uop.pc_lob, issue_slots[8].wakeup_ports[4].bits.uop.pc_lob connect slots_8.io.wakeup_ports[4].bits.uop.edge_inst, issue_slots[8].wakeup_ports[4].bits.uop.edge_inst connect slots_8.io.wakeup_ports[4].bits.uop.ftq_idx, issue_slots[8].wakeup_ports[4].bits.uop.ftq_idx connect slots_8.io.wakeup_ports[4].bits.uop.is_mov, issue_slots[8].wakeup_ports[4].bits.uop.is_mov connect slots_8.io.wakeup_ports[4].bits.uop.is_rocc, issue_slots[8].wakeup_ports[4].bits.uop.is_rocc connect slots_8.io.wakeup_ports[4].bits.uop.is_sys_pc2epc, issue_slots[8].wakeup_ports[4].bits.uop.is_sys_pc2epc connect slots_8.io.wakeup_ports[4].bits.uop.is_eret, issue_slots[8].wakeup_ports[4].bits.uop.is_eret connect slots_8.io.wakeup_ports[4].bits.uop.is_amo, issue_slots[8].wakeup_ports[4].bits.uop.is_amo connect slots_8.io.wakeup_ports[4].bits.uop.is_sfence, issue_slots[8].wakeup_ports[4].bits.uop.is_sfence connect slots_8.io.wakeup_ports[4].bits.uop.is_fencei, issue_slots[8].wakeup_ports[4].bits.uop.is_fencei connect slots_8.io.wakeup_ports[4].bits.uop.is_fence, issue_slots[8].wakeup_ports[4].bits.uop.is_fence connect slots_8.io.wakeup_ports[4].bits.uop.is_sfb, issue_slots[8].wakeup_ports[4].bits.uop.is_sfb connect slots_8.io.wakeup_ports[4].bits.uop.br_type, issue_slots[8].wakeup_ports[4].bits.uop.br_type connect slots_8.io.wakeup_ports[4].bits.uop.br_tag, issue_slots[8].wakeup_ports[4].bits.uop.br_tag connect slots_8.io.wakeup_ports[4].bits.uop.br_mask, issue_slots[8].wakeup_ports[4].bits.uop.br_mask connect slots_8.io.wakeup_ports[4].bits.uop.dis_col_sel, issue_slots[8].wakeup_ports[4].bits.uop.dis_col_sel connect slots_8.io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint, issue_slots[8].wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect slots_8.io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint, issue_slots[8].wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect slots_8.io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint, issue_slots[8].wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect slots_8.io.wakeup_ports[4].bits.uop.iw_p2_speculative_child, issue_slots[8].wakeup_ports[4].bits.uop.iw_p2_speculative_child connect slots_8.io.wakeup_ports[4].bits.uop.iw_p1_speculative_child, issue_slots[8].wakeup_ports[4].bits.uop.iw_p1_speculative_child connect slots_8.io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen, issue_slots[8].wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect slots_8.io.wakeup_ports[4].bits.uop.iw_issued_partial_agen, issue_slots[8].wakeup_ports[4].bits.uop.iw_issued_partial_agen connect slots_8.io.wakeup_ports[4].bits.uop.iw_issued, issue_slots[8].wakeup_ports[4].bits.uop.iw_issued connect slots_8.io.wakeup_ports[4].bits.uop.fu_code[0], issue_slots[8].wakeup_ports[4].bits.uop.fu_code[0] connect slots_8.io.wakeup_ports[4].bits.uop.fu_code[1], issue_slots[8].wakeup_ports[4].bits.uop.fu_code[1] connect slots_8.io.wakeup_ports[4].bits.uop.fu_code[2], issue_slots[8].wakeup_ports[4].bits.uop.fu_code[2] connect slots_8.io.wakeup_ports[4].bits.uop.fu_code[3], issue_slots[8].wakeup_ports[4].bits.uop.fu_code[3] connect slots_8.io.wakeup_ports[4].bits.uop.fu_code[4], issue_slots[8].wakeup_ports[4].bits.uop.fu_code[4] connect slots_8.io.wakeup_ports[4].bits.uop.fu_code[5], issue_slots[8].wakeup_ports[4].bits.uop.fu_code[5] connect slots_8.io.wakeup_ports[4].bits.uop.fu_code[6], issue_slots[8].wakeup_ports[4].bits.uop.fu_code[6] connect slots_8.io.wakeup_ports[4].bits.uop.fu_code[7], issue_slots[8].wakeup_ports[4].bits.uop.fu_code[7] connect slots_8.io.wakeup_ports[4].bits.uop.fu_code[8], issue_slots[8].wakeup_ports[4].bits.uop.fu_code[8] connect slots_8.io.wakeup_ports[4].bits.uop.fu_code[9], issue_slots[8].wakeup_ports[4].bits.uop.fu_code[9] connect slots_8.io.wakeup_ports[4].bits.uop.iq_type[0], issue_slots[8].wakeup_ports[4].bits.uop.iq_type[0] connect slots_8.io.wakeup_ports[4].bits.uop.iq_type[1], issue_slots[8].wakeup_ports[4].bits.uop.iq_type[1] connect slots_8.io.wakeup_ports[4].bits.uop.iq_type[2], issue_slots[8].wakeup_ports[4].bits.uop.iq_type[2] connect slots_8.io.wakeup_ports[4].bits.uop.iq_type[3], issue_slots[8].wakeup_ports[4].bits.uop.iq_type[3] connect slots_8.io.wakeup_ports[4].bits.uop.debug_pc, issue_slots[8].wakeup_ports[4].bits.uop.debug_pc connect slots_8.io.wakeup_ports[4].bits.uop.is_rvc, issue_slots[8].wakeup_ports[4].bits.uop.is_rvc connect slots_8.io.wakeup_ports[4].bits.uop.debug_inst, issue_slots[8].wakeup_ports[4].bits.uop.debug_inst connect slots_8.io.wakeup_ports[4].bits.uop.inst, issue_slots[8].wakeup_ports[4].bits.uop.inst connect slots_8.io.wakeup_ports[4].valid, issue_slots[8].wakeup_ports[4].valid connect slots_8.io.squash_grant, issue_slots[8].squash_grant connect slots_8.io.clear, issue_slots[8].clear connect slots_8.io.kill, issue_slots[8].kill connect slots_8.io.brupdate.b2.target_offset, issue_slots[8].brupdate.b2.target_offset connect slots_8.io.brupdate.b2.jalr_target, issue_slots[8].brupdate.b2.jalr_target connect slots_8.io.brupdate.b2.pc_sel, issue_slots[8].brupdate.b2.pc_sel connect slots_8.io.brupdate.b2.cfi_type, issue_slots[8].brupdate.b2.cfi_type connect slots_8.io.brupdate.b2.taken, issue_slots[8].brupdate.b2.taken connect slots_8.io.brupdate.b2.mispredict, issue_slots[8].brupdate.b2.mispredict connect slots_8.io.brupdate.b2.uop.debug_tsrc, issue_slots[8].brupdate.b2.uop.debug_tsrc connect slots_8.io.brupdate.b2.uop.debug_fsrc, issue_slots[8].brupdate.b2.uop.debug_fsrc connect slots_8.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[8].brupdate.b2.uop.bp_xcpt_if connect slots_8.io.brupdate.b2.uop.bp_debug_if, issue_slots[8].brupdate.b2.uop.bp_debug_if connect slots_8.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[8].brupdate.b2.uop.xcpt_ma_if connect slots_8.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[8].brupdate.b2.uop.xcpt_ae_if connect slots_8.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[8].brupdate.b2.uop.xcpt_pf_if connect slots_8.io.brupdate.b2.uop.fp_typ, issue_slots[8].brupdate.b2.uop.fp_typ connect slots_8.io.brupdate.b2.uop.fp_rm, issue_slots[8].brupdate.b2.uop.fp_rm connect slots_8.io.brupdate.b2.uop.fp_val, issue_slots[8].brupdate.b2.uop.fp_val connect slots_8.io.brupdate.b2.uop.fcn_op, issue_slots[8].brupdate.b2.uop.fcn_op connect slots_8.io.brupdate.b2.uop.fcn_dw, issue_slots[8].brupdate.b2.uop.fcn_dw connect slots_8.io.brupdate.b2.uop.frs3_en, issue_slots[8].brupdate.b2.uop.frs3_en connect slots_8.io.brupdate.b2.uop.lrs2_rtype, issue_slots[8].brupdate.b2.uop.lrs2_rtype connect slots_8.io.brupdate.b2.uop.lrs1_rtype, issue_slots[8].brupdate.b2.uop.lrs1_rtype connect slots_8.io.brupdate.b2.uop.dst_rtype, issue_slots[8].brupdate.b2.uop.dst_rtype connect slots_8.io.brupdate.b2.uop.lrs3, issue_slots[8].brupdate.b2.uop.lrs3 connect slots_8.io.brupdate.b2.uop.lrs2, issue_slots[8].brupdate.b2.uop.lrs2 connect slots_8.io.brupdate.b2.uop.lrs1, issue_slots[8].brupdate.b2.uop.lrs1 connect slots_8.io.brupdate.b2.uop.ldst, issue_slots[8].brupdate.b2.uop.ldst connect slots_8.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[8].brupdate.b2.uop.ldst_is_rs1 connect slots_8.io.brupdate.b2.uop.csr_cmd, issue_slots[8].brupdate.b2.uop.csr_cmd connect slots_8.io.brupdate.b2.uop.flush_on_commit, issue_slots[8].brupdate.b2.uop.flush_on_commit connect slots_8.io.brupdate.b2.uop.is_unique, issue_slots[8].brupdate.b2.uop.is_unique connect slots_8.io.brupdate.b2.uop.uses_stq, issue_slots[8].brupdate.b2.uop.uses_stq connect slots_8.io.brupdate.b2.uop.uses_ldq, issue_slots[8].brupdate.b2.uop.uses_ldq connect slots_8.io.brupdate.b2.uop.mem_signed, issue_slots[8].brupdate.b2.uop.mem_signed connect slots_8.io.brupdate.b2.uop.mem_size, issue_slots[8].brupdate.b2.uop.mem_size connect slots_8.io.brupdate.b2.uop.mem_cmd, issue_slots[8].brupdate.b2.uop.mem_cmd connect slots_8.io.brupdate.b2.uop.exc_cause, issue_slots[8].brupdate.b2.uop.exc_cause connect slots_8.io.brupdate.b2.uop.exception, issue_slots[8].brupdate.b2.uop.exception connect slots_8.io.brupdate.b2.uop.stale_pdst, issue_slots[8].brupdate.b2.uop.stale_pdst connect slots_8.io.brupdate.b2.uop.ppred_busy, issue_slots[8].brupdate.b2.uop.ppred_busy connect slots_8.io.brupdate.b2.uop.prs3_busy, issue_slots[8].brupdate.b2.uop.prs3_busy connect slots_8.io.brupdate.b2.uop.prs2_busy, issue_slots[8].brupdate.b2.uop.prs2_busy connect slots_8.io.brupdate.b2.uop.prs1_busy, issue_slots[8].brupdate.b2.uop.prs1_busy connect slots_8.io.brupdate.b2.uop.ppred, issue_slots[8].brupdate.b2.uop.ppred connect slots_8.io.brupdate.b2.uop.prs3, issue_slots[8].brupdate.b2.uop.prs3 connect slots_8.io.brupdate.b2.uop.prs2, issue_slots[8].brupdate.b2.uop.prs2 connect slots_8.io.brupdate.b2.uop.prs1, issue_slots[8].brupdate.b2.uop.prs1 connect slots_8.io.brupdate.b2.uop.pdst, issue_slots[8].brupdate.b2.uop.pdst connect slots_8.io.brupdate.b2.uop.rxq_idx, issue_slots[8].brupdate.b2.uop.rxq_idx connect slots_8.io.brupdate.b2.uop.stq_idx, issue_slots[8].brupdate.b2.uop.stq_idx connect slots_8.io.brupdate.b2.uop.ldq_idx, issue_slots[8].brupdate.b2.uop.ldq_idx connect slots_8.io.brupdate.b2.uop.rob_idx, issue_slots[8].brupdate.b2.uop.rob_idx connect slots_8.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[8].brupdate.b2.uop.fp_ctrl.vec connect slots_8.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[8].brupdate.b2.uop.fp_ctrl.wflags connect slots_8.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[8].brupdate.b2.uop.fp_ctrl.sqrt connect slots_8.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[8].brupdate.b2.uop.fp_ctrl.div connect slots_8.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[8].brupdate.b2.uop.fp_ctrl.fma connect slots_8.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[8].brupdate.b2.uop.fp_ctrl.fastpipe connect slots_8.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[8].brupdate.b2.uop.fp_ctrl.toint connect slots_8.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[8].brupdate.b2.uop.fp_ctrl.fromint connect slots_8.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[8].brupdate.b2.uop.fp_ctrl.typeTagOut connect slots_8.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[8].brupdate.b2.uop.fp_ctrl.typeTagIn connect slots_8.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[8].brupdate.b2.uop.fp_ctrl.swap23 connect slots_8.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[8].brupdate.b2.uop.fp_ctrl.swap12 connect slots_8.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[8].brupdate.b2.uop.fp_ctrl.ren3 connect slots_8.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[8].brupdate.b2.uop.fp_ctrl.ren2 connect slots_8.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[8].brupdate.b2.uop.fp_ctrl.ren1 connect slots_8.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[8].brupdate.b2.uop.fp_ctrl.wen connect slots_8.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[8].brupdate.b2.uop.fp_ctrl.ldst connect slots_8.io.brupdate.b2.uop.op2_sel, issue_slots[8].brupdate.b2.uop.op2_sel connect slots_8.io.brupdate.b2.uop.op1_sel, issue_slots[8].brupdate.b2.uop.op1_sel connect slots_8.io.brupdate.b2.uop.imm_packed, issue_slots[8].brupdate.b2.uop.imm_packed connect slots_8.io.brupdate.b2.uop.pimm, issue_slots[8].brupdate.b2.uop.pimm connect slots_8.io.brupdate.b2.uop.imm_sel, issue_slots[8].brupdate.b2.uop.imm_sel connect slots_8.io.brupdate.b2.uop.imm_rename, issue_slots[8].brupdate.b2.uop.imm_rename connect slots_8.io.brupdate.b2.uop.taken, issue_slots[8].brupdate.b2.uop.taken connect slots_8.io.brupdate.b2.uop.pc_lob, issue_slots[8].brupdate.b2.uop.pc_lob connect slots_8.io.brupdate.b2.uop.edge_inst, issue_slots[8].brupdate.b2.uop.edge_inst connect slots_8.io.brupdate.b2.uop.ftq_idx, issue_slots[8].brupdate.b2.uop.ftq_idx connect slots_8.io.brupdate.b2.uop.is_mov, issue_slots[8].brupdate.b2.uop.is_mov connect slots_8.io.brupdate.b2.uop.is_rocc, issue_slots[8].brupdate.b2.uop.is_rocc connect slots_8.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[8].brupdate.b2.uop.is_sys_pc2epc connect slots_8.io.brupdate.b2.uop.is_eret, issue_slots[8].brupdate.b2.uop.is_eret connect slots_8.io.brupdate.b2.uop.is_amo, issue_slots[8].brupdate.b2.uop.is_amo connect slots_8.io.brupdate.b2.uop.is_sfence, issue_slots[8].brupdate.b2.uop.is_sfence connect slots_8.io.brupdate.b2.uop.is_fencei, issue_slots[8].brupdate.b2.uop.is_fencei connect slots_8.io.brupdate.b2.uop.is_fence, issue_slots[8].brupdate.b2.uop.is_fence connect slots_8.io.brupdate.b2.uop.is_sfb, issue_slots[8].brupdate.b2.uop.is_sfb connect slots_8.io.brupdate.b2.uop.br_type, issue_slots[8].brupdate.b2.uop.br_type connect slots_8.io.brupdate.b2.uop.br_tag, issue_slots[8].brupdate.b2.uop.br_tag connect slots_8.io.brupdate.b2.uop.br_mask, issue_slots[8].brupdate.b2.uop.br_mask connect slots_8.io.brupdate.b2.uop.dis_col_sel, issue_slots[8].brupdate.b2.uop.dis_col_sel connect slots_8.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[8].brupdate.b2.uop.iw_p3_bypass_hint connect slots_8.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[8].brupdate.b2.uop.iw_p2_bypass_hint connect slots_8.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[8].brupdate.b2.uop.iw_p1_bypass_hint connect slots_8.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[8].brupdate.b2.uop.iw_p2_speculative_child connect slots_8.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[8].brupdate.b2.uop.iw_p1_speculative_child connect slots_8.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[8].brupdate.b2.uop.iw_issued_partial_dgen connect slots_8.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[8].brupdate.b2.uop.iw_issued_partial_agen connect slots_8.io.brupdate.b2.uop.iw_issued, issue_slots[8].brupdate.b2.uop.iw_issued connect slots_8.io.brupdate.b2.uop.fu_code[0], issue_slots[8].brupdate.b2.uop.fu_code[0] connect slots_8.io.brupdate.b2.uop.fu_code[1], issue_slots[8].brupdate.b2.uop.fu_code[1] connect slots_8.io.brupdate.b2.uop.fu_code[2], issue_slots[8].brupdate.b2.uop.fu_code[2] connect slots_8.io.brupdate.b2.uop.fu_code[3], issue_slots[8].brupdate.b2.uop.fu_code[3] connect slots_8.io.brupdate.b2.uop.fu_code[4], issue_slots[8].brupdate.b2.uop.fu_code[4] connect slots_8.io.brupdate.b2.uop.fu_code[5], issue_slots[8].brupdate.b2.uop.fu_code[5] connect slots_8.io.brupdate.b2.uop.fu_code[6], issue_slots[8].brupdate.b2.uop.fu_code[6] connect slots_8.io.brupdate.b2.uop.fu_code[7], issue_slots[8].brupdate.b2.uop.fu_code[7] connect slots_8.io.brupdate.b2.uop.fu_code[8], issue_slots[8].brupdate.b2.uop.fu_code[8] connect slots_8.io.brupdate.b2.uop.fu_code[9], issue_slots[8].brupdate.b2.uop.fu_code[9] connect slots_8.io.brupdate.b2.uop.iq_type[0], issue_slots[8].brupdate.b2.uop.iq_type[0] connect slots_8.io.brupdate.b2.uop.iq_type[1], issue_slots[8].brupdate.b2.uop.iq_type[1] connect slots_8.io.brupdate.b2.uop.iq_type[2], issue_slots[8].brupdate.b2.uop.iq_type[2] connect slots_8.io.brupdate.b2.uop.iq_type[3], issue_slots[8].brupdate.b2.uop.iq_type[3] connect slots_8.io.brupdate.b2.uop.debug_pc, issue_slots[8].brupdate.b2.uop.debug_pc connect slots_8.io.brupdate.b2.uop.is_rvc, issue_slots[8].brupdate.b2.uop.is_rvc connect slots_8.io.brupdate.b2.uop.debug_inst, issue_slots[8].brupdate.b2.uop.debug_inst connect slots_8.io.brupdate.b2.uop.inst, issue_slots[8].brupdate.b2.uop.inst connect slots_8.io.brupdate.b1.mispredict_mask, issue_slots[8].brupdate.b1.mispredict_mask connect slots_8.io.brupdate.b1.resolve_mask, issue_slots[8].brupdate.b1.resolve_mask connect issue_slots[8].out_uop.debug_tsrc, slots_8.io.out_uop.debug_tsrc connect issue_slots[8].out_uop.debug_fsrc, slots_8.io.out_uop.debug_fsrc connect issue_slots[8].out_uop.bp_xcpt_if, slots_8.io.out_uop.bp_xcpt_if connect issue_slots[8].out_uop.bp_debug_if, slots_8.io.out_uop.bp_debug_if connect issue_slots[8].out_uop.xcpt_ma_if, slots_8.io.out_uop.xcpt_ma_if connect issue_slots[8].out_uop.xcpt_ae_if, slots_8.io.out_uop.xcpt_ae_if connect issue_slots[8].out_uop.xcpt_pf_if, slots_8.io.out_uop.xcpt_pf_if connect issue_slots[8].out_uop.fp_typ, slots_8.io.out_uop.fp_typ connect issue_slots[8].out_uop.fp_rm, slots_8.io.out_uop.fp_rm connect issue_slots[8].out_uop.fp_val, slots_8.io.out_uop.fp_val connect issue_slots[8].out_uop.fcn_op, slots_8.io.out_uop.fcn_op connect issue_slots[8].out_uop.fcn_dw, slots_8.io.out_uop.fcn_dw connect issue_slots[8].out_uop.frs3_en, slots_8.io.out_uop.frs3_en connect issue_slots[8].out_uop.lrs2_rtype, slots_8.io.out_uop.lrs2_rtype connect issue_slots[8].out_uop.lrs1_rtype, slots_8.io.out_uop.lrs1_rtype connect issue_slots[8].out_uop.dst_rtype, slots_8.io.out_uop.dst_rtype connect issue_slots[8].out_uop.lrs3, slots_8.io.out_uop.lrs3 connect issue_slots[8].out_uop.lrs2, slots_8.io.out_uop.lrs2 connect issue_slots[8].out_uop.lrs1, slots_8.io.out_uop.lrs1 connect issue_slots[8].out_uop.ldst, slots_8.io.out_uop.ldst connect issue_slots[8].out_uop.ldst_is_rs1, slots_8.io.out_uop.ldst_is_rs1 connect issue_slots[8].out_uop.csr_cmd, slots_8.io.out_uop.csr_cmd connect issue_slots[8].out_uop.flush_on_commit, slots_8.io.out_uop.flush_on_commit connect issue_slots[8].out_uop.is_unique, slots_8.io.out_uop.is_unique connect issue_slots[8].out_uop.uses_stq, slots_8.io.out_uop.uses_stq connect issue_slots[8].out_uop.uses_ldq, slots_8.io.out_uop.uses_ldq connect issue_slots[8].out_uop.mem_signed, slots_8.io.out_uop.mem_signed connect issue_slots[8].out_uop.mem_size, slots_8.io.out_uop.mem_size connect issue_slots[8].out_uop.mem_cmd, slots_8.io.out_uop.mem_cmd connect issue_slots[8].out_uop.exc_cause, slots_8.io.out_uop.exc_cause connect issue_slots[8].out_uop.exception, slots_8.io.out_uop.exception connect issue_slots[8].out_uop.stale_pdst, slots_8.io.out_uop.stale_pdst connect issue_slots[8].out_uop.ppred_busy, slots_8.io.out_uop.ppred_busy connect issue_slots[8].out_uop.prs3_busy, slots_8.io.out_uop.prs3_busy connect issue_slots[8].out_uop.prs2_busy, slots_8.io.out_uop.prs2_busy connect issue_slots[8].out_uop.prs1_busy, slots_8.io.out_uop.prs1_busy connect issue_slots[8].out_uop.ppred, slots_8.io.out_uop.ppred connect issue_slots[8].out_uop.prs3, slots_8.io.out_uop.prs3 connect issue_slots[8].out_uop.prs2, slots_8.io.out_uop.prs2 connect issue_slots[8].out_uop.prs1, slots_8.io.out_uop.prs1 connect issue_slots[8].out_uop.pdst, slots_8.io.out_uop.pdst connect issue_slots[8].out_uop.rxq_idx, slots_8.io.out_uop.rxq_idx connect issue_slots[8].out_uop.stq_idx, slots_8.io.out_uop.stq_idx connect issue_slots[8].out_uop.ldq_idx, slots_8.io.out_uop.ldq_idx connect issue_slots[8].out_uop.rob_idx, slots_8.io.out_uop.rob_idx connect issue_slots[8].out_uop.fp_ctrl.vec, slots_8.io.out_uop.fp_ctrl.vec connect issue_slots[8].out_uop.fp_ctrl.wflags, slots_8.io.out_uop.fp_ctrl.wflags connect issue_slots[8].out_uop.fp_ctrl.sqrt, slots_8.io.out_uop.fp_ctrl.sqrt connect issue_slots[8].out_uop.fp_ctrl.div, slots_8.io.out_uop.fp_ctrl.div connect issue_slots[8].out_uop.fp_ctrl.fma, slots_8.io.out_uop.fp_ctrl.fma connect issue_slots[8].out_uop.fp_ctrl.fastpipe, slots_8.io.out_uop.fp_ctrl.fastpipe connect issue_slots[8].out_uop.fp_ctrl.toint, slots_8.io.out_uop.fp_ctrl.toint connect issue_slots[8].out_uop.fp_ctrl.fromint, slots_8.io.out_uop.fp_ctrl.fromint connect issue_slots[8].out_uop.fp_ctrl.typeTagOut, slots_8.io.out_uop.fp_ctrl.typeTagOut connect issue_slots[8].out_uop.fp_ctrl.typeTagIn, slots_8.io.out_uop.fp_ctrl.typeTagIn connect issue_slots[8].out_uop.fp_ctrl.swap23, slots_8.io.out_uop.fp_ctrl.swap23 connect issue_slots[8].out_uop.fp_ctrl.swap12, slots_8.io.out_uop.fp_ctrl.swap12 connect issue_slots[8].out_uop.fp_ctrl.ren3, slots_8.io.out_uop.fp_ctrl.ren3 connect issue_slots[8].out_uop.fp_ctrl.ren2, slots_8.io.out_uop.fp_ctrl.ren2 connect issue_slots[8].out_uop.fp_ctrl.ren1, slots_8.io.out_uop.fp_ctrl.ren1 connect issue_slots[8].out_uop.fp_ctrl.wen, slots_8.io.out_uop.fp_ctrl.wen connect issue_slots[8].out_uop.fp_ctrl.ldst, slots_8.io.out_uop.fp_ctrl.ldst connect issue_slots[8].out_uop.op2_sel, slots_8.io.out_uop.op2_sel connect issue_slots[8].out_uop.op1_sel, slots_8.io.out_uop.op1_sel connect issue_slots[8].out_uop.imm_packed, slots_8.io.out_uop.imm_packed connect issue_slots[8].out_uop.pimm, slots_8.io.out_uop.pimm connect issue_slots[8].out_uop.imm_sel, slots_8.io.out_uop.imm_sel connect issue_slots[8].out_uop.imm_rename, slots_8.io.out_uop.imm_rename connect issue_slots[8].out_uop.taken, slots_8.io.out_uop.taken connect issue_slots[8].out_uop.pc_lob, slots_8.io.out_uop.pc_lob connect issue_slots[8].out_uop.edge_inst, slots_8.io.out_uop.edge_inst connect issue_slots[8].out_uop.ftq_idx, slots_8.io.out_uop.ftq_idx connect issue_slots[8].out_uop.is_mov, slots_8.io.out_uop.is_mov connect issue_slots[8].out_uop.is_rocc, slots_8.io.out_uop.is_rocc connect issue_slots[8].out_uop.is_sys_pc2epc, slots_8.io.out_uop.is_sys_pc2epc connect issue_slots[8].out_uop.is_eret, slots_8.io.out_uop.is_eret connect issue_slots[8].out_uop.is_amo, slots_8.io.out_uop.is_amo connect issue_slots[8].out_uop.is_sfence, slots_8.io.out_uop.is_sfence connect issue_slots[8].out_uop.is_fencei, slots_8.io.out_uop.is_fencei connect issue_slots[8].out_uop.is_fence, slots_8.io.out_uop.is_fence connect issue_slots[8].out_uop.is_sfb, slots_8.io.out_uop.is_sfb connect issue_slots[8].out_uop.br_type, slots_8.io.out_uop.br_type connect issue_slots[8].out_uop.br_tag, slots_8.io.out_uop.br_tag connect issue_slots[8].out_uop.br_mask, slots_8.io.out_uop.br_mask connect issue_slots[8].out_uop.dis_col_sel, slots_8.io.out_uop.dis_col_sel connect issue_slots[8].out_uop.iw_p3_bypass_hint, slots_8.io.out_uop.iw_p3_bypass_hint connect issue_slots[8].out_uop.iw_p2_bypass_hint, slots_8.io.out_uop.iw_p2_bypass_hint connect issue_slots[8].out_uop.iw_p1_bypass_hint, slots_8.io.out_uop.iw_p1_bypass_hint connect issue_slots[8].out_uop.iw_p2_speculative_child, slots_8.io.out_uop.iw_p2_speculative_child connect issue_slots[8].out_uop.iw_p1_speculative_child, slots_8.io.out_uop.iw_p1_speculative_child connect issue_slots[8].out_uop.iw_issued_partial_dgen, slots_8.io.out_uop.iw_issued_partial_dgen connect issue_slots[8].out_uop.iw_issued_partial_agen, slots_8.io.out_uop.iw_issued_partial_agen connect issue_slots[8].out_uop.iw_issued, slots_8.io.out_uop.iw_issued connect issue_slots[8].out_uop.fu_code[0], slots_8.io.out_uop.fu_code[0] connect issue_slots[8].out_uop.fu_code[1], slots_8.io.out_uop.fu_code[1] connect issue_slots[8].out_uop.fu_code[2], slots_8.io.out_uop.fu_code[2] connect issue_slots[8].out_uop.fu_code[3], slots_8.io.out_uop.fu_code[3] connect issue_slots[8].out_uop.fu_code[4], slots_8.io.out_uop.fu_code[4] connect issue_slots[8].out_uop.fu_code[5], slots_8.io.out_uop.fu_code[5] connect issue_slots[8].out_uop.fu_code[6], slots_8.io.out_uop.fu_code[6] connect issue_slots[8].out_uop.fu_code[7], slots_8.io.out_uop.fu_code[7] connect issue_slots[8].out_uop.fu_code[8], slots_8.io.out_uop.fu_code[8] connect issue_slots[8].out_uop.fu_code[9], slots_8.io.out_uop.fu_code[9] connect issue_slots[8].out_uop.iq_type[0], slots_8.io.out_uop.iq_type[0] connect issue_slots[8].out_uop.iq_type[1], slots_8.io.out_uop.iq_type[1] connect issue_slots[8].out_uop.iq_type[2], slots_8.io.out_uop.iq_type[2] connect issue_slots[8].out_uop.iq_type[3], slots_8.io.out_uop.iq_type[3] connect issue_slots[8].out_uop.debug_pc, slots_8.io.out_uop.debug_pc connect issue_slots[8].out_uop.is_rvc, slots_8.io.out_uop.is_rvc connect issue_slots[8].out_uop.debug_inst, slots_8.io.out_uop.debug_inst connect issue_slots[8].out_uop.inst, slots_8.io.out_uop.inst connect slots_8.io.in_uop.bits.debug_tsrc, issue_slots[8].in_uop.bits.debug_tsrc connect slots_8.io.in_uop.bits.debug_fsrc, issue_slots[8].in_uop.bits.debug_fsrc connect slots_8.io.in_uop.bits.bp_xcpt_if, issue_slots[8].in_uop.bits.bp_xcpt_if connect slots_8.io.in_uop.bits.bp_debug_if, issue_slots[8].in_uop.bits.bp_debug_if connect slots_8.io.in_uop.bits.xcpt_ma_if, issue_slots[8].in_uop.bits.xcpt_ma_if connect slots_8.io.in_uop.bits.xcpt_ae_if, issue_slots[8].in_uop.bits.xcpt_ae_if connect slots_8.io.in_uop.bits.xcpt_pf_if, issue_slots[8].in_uop.bits.xcpt_pf_if connect slots_8.io.in_uop.bits.fp_typ, issue_slots[8].in_uop.bits.fp_typ connect slots_8.io.in_uop.bits.fp_rm, issue_slots[8].in_uop.bits.fp_rm connect slots_8.io.in_uop.bits.fp_val, issue_slots[8].in_uop.bits.fp_val connect slots_8.io.in_uop.bits.fcn_op, issue_slots[8].in_uop.bits.fcn_op connect slots_8.io.in_uop.bits.fcn_dw, issue_slots[8].in_uop.bits.fcn_dw connect slots_8.io.in_uop.bits.frs3_en, issue_slots[8].in_uop.bits.frs3_en connect slots_8.io.in_uop.bits.lrs2_rtype, issue_slots[8].in_uop.bits.lrs2_rtype connect slots_8.io.in_uop.bits.lrs1_rtype, issue_slots[8].in_uop.bits.lrs1_rtype connect slots_8.io.in_uop.bits.dst_rtype, issue_slots[8].in_uop.bits.dst_rtype connect slots_8.io.in_uop.bits.lrs3, issue_slots[8].in_uop.bits.lrs3 connect slots_8.io.in_uop.bits.lrs2, issue_slots[8].in_uop.bits.lrs2 connect slots_8.io.in_uop.bits.lrs1, issue_slots[8].in_uop.bits.lrs1 connect slots_8.io.in_uop.bits.ldst, issue_slots[8].in_uop.bits.ldst connect slots_8.io.in_uop.bits.ldst_is_rs1, issue_slots[8].in_uop.bits.ldst_is_rs1 connect slots_8.io.in_uop.bits.csr_cmd, issue_slots[8].in_uop.bits.csr_cmd connect slots_8.io.in_uop.bits.flush_on_commit, issue_slots[8].in_uop.bits.flush_on_commit connect slots_8.io.in_uop.bits.is_unique, issue_slots[8].in_uop.bits.is_unique connect slots_8.io.in_uop.bits.uses_stq, issue_slots[8].in_uop.bits.uses_stq connect slots_8.io.in_uop.bits.uses_ldq, issue_slots[8].in_uop.bits.uses_ldq connect slots_8.io.in_uop.bits.mem_signed, issue_slots[8].in_uop.bits.mem_signed connect slots_8.io.in_uop.bits.mem_size, issue_slots[8].in_uop.bits.mem_size connect slots_8.io.in_uop.bits.mem_cmd, issue_slots[8].in_uop.bits.mem_cmd connect slots_8.io.in_uop.bits.exc_cause, issue_slots[8].in_uop.bits.exc_cause connect slots_8.io.in_uop.bits.exception, issue_slots[8].in_uop.bits.exception connect slots_8.io.in_uop.bits.stale_pdst, issue_slots[8].in_uop.bits.stale_pdst connect slots_8.io.in_uop.bits.ppred_busy, issue_slots[8].in_uop.bits.ppred_busy connect slots_8.io.in_uop.bits.prs3_busy, issue_slots[8].in_uop.bits.prs3_busy connect slots_8.io.in_uop.bits.prs2_busy, issue_slots[8].in_uop.bits.prs2_busy connect slots_8.io.in_uop.bits.prs1_busy, issue_slots[8].in_uop.bits.prs1_busy connect slots_8.io.in_uop.bits.ppred, issue_slots[8].in_uop.bits.ppred connect slots_8.io.in_uop.bits.prs3, issue_slots[8].in_uop.bits.prs3 connect slots_8.io.in_uop.bits.prs2, issue_slots[8].in_uop.bits.prs2 connect slots_8.io.in_uop.bits.prs1, issue_slots[8].in_uop.bits.prs1 connect slots_8.io.in_uop.bits.pdst, issue_slots[8].in_uop.bits.pdst connect slots_8.io.in_uop.bits.rxq_idx, issue_slots[8].in_uop.bits.rxq_idx connect slots_8.io.in_uop.bits.stq_idx, issue_slots[8].in_uop.bits.stq_idx connect slots_8.io.in_uop.bits.ldq_idx, issue_slots[8].in_uop.bits.ldq_idx connect slots_8.io.in_uop.bits.rob_idx, issue_slots[8].in_uop.bits.rob_idx connect slots_8.io.in_uop.bits.fp_ctrl.vec, issue_slots[8].in_uop.bits.fp_ctrl.vec connect slots_8.io.in_uop.bits.fp_ctrl.wflags, issue_slots[8].in_uop.bits.fp_ctrl.wflags connect slots_8.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[8].in_uop.bits.fp_ctrl.sqrt connect slots_8.io.in_uop.bits.fp_ctrl.div, issue_slots[8].in_uop.bits.fp_ctrl.div connect slots_8.io.in_uop.bits.fp_ctrl.fma, issue_slots[8].in_uop.bits.fp_ctrl.fma connect slots_8.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[8].in_uop.bits.fp_ctrl.fastpipe connect slots_8.io.in_uop.bits.fp_ctrl.toint, issue_slots[8].in_uop.bits.fp_ctrl.toint connect slots_8.io.in_uop.bits.fp_ctrl.fromint, issue_slots[8].in_uop.bits.fp_ctrl.fromint connect slots_8.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[8].in_uop.bits.fp_ctrl.typeTagOut connect slots_8.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[8].in_uop.bits.fp_ctrl.typeTagIn connect slots_8.io.in_uop.bits.fp_ctrl.swap23, issue_slots[8].in_uop.bits.fp_ctrl.swap23 connect slots_8.io.in_uop.bits.fp_ctrl.swap12, issue_slots[8].in_uop.bits.fp_ctrl.swap12 connect slots_8.io.in_uop.bits.fp_ctrl.ren3, issue_slots[8].in_uop.bits.fp_ctrl.ren3 connect slots_8.io.in_uop.bits.fp_ctrl.ren2, issue_slots[8].in_uop.bits.fp_ctrl.ren2 connect slots_8.io.in_uop.bits.fp_ctrl.ren1, issue_slots[8].in_uop.bits.fp_ctrl.ren1 connect slots_8.io.in_uop.bits.fp_ctrl.wen, issue_slots[8].in_uop.bits.fp_ctrl.wen connect slots_8.io.in_uop.bits.fp_ctrl.ldst, issue_slots[8].in_uop.bits.fp_ctrl.ldst connect slots_8.io.in_uop.bits.op2_sel, issue_slots[8].in_uop.bits.op2_sel connect slots_8.io.in_uop.bits.op1_sel, issue_slots[8].in_uop.bits.op1_sel connect slots_8.io.in_uop.bits.imm_packed, issue_slots[8].in_uop.bits.imm_packed connect slots_8.io.in_uop.bits.pimm, issue_slots[8].in_uop.bits.pimm connect slots_8.io.in_uop.bits.imm_sel, issue_slots[8].in_uop.bits.imm_sel connect slots_8.io.in_uop.bits.imm_rename, issue_slots[8].in_uop.bits.imm_rename connect slots_8.io.in_uop.bits.taken, issue_slots[8].in_uop.bits.taken connect slots_8.io.in_uop.bits.pc_lob, issue_slots[8].in_uop.bits.pc_lob connect slots_8.io.in_uop.bits.edge_inst, issue_slots[8].in_uop.bits.edge_inst connect slots_8.io.in_uop.bits.ftq_idx, issue_slots[8].in_uop.bits.ftq_idx connect slots_8.io.in_uop.bits.is_mov, issue_slots[8].in_uop.bits.is_mov connect slots_8.io.in_uop.bits.is_rocc, issue_slots[8].in_uop.bits.is_rocc connect slots_8.io.in_uop.bits.is_sys_pc2epc, issue_slots[8].in_uop.bits.is_sys_pc2epc connect slots_8.io.in_uop.bits.is_eret, issue_slots[8].in_uop.bits.is_eret connect slots_8.io.in_uop.bits.is_amo, issue_slots[8].in_uop.bits.is_amo connect slots_8.io.in_uop.bits.is_sfence, issue_slots[8].in_uop.bits.is_sfence connect slots_8.io.in_uop.bits.is_fencei, issue_slots[8].in_uop.bits.is_fencei connect slots_8.io.in_uop.bits.is_fence, issue_slots[8].in_uop.bits.is_fence connect slots_8.io.in_uop.bits.is_sfb, issue_slots[8].in_uop.bits.is_sfb connect slots_8.io.in_uop.bits.br_type, issue_slots[8].in_uop.bits.br_type connect slots_8.io.in_uop.bits.br_tag, issue_slots[8].in_uop.bits.br_tag connect slots_8.io.in_uop.bits.br_mask, issue_slots[8].in_uop.bits.br_mask connect slots_8.io.in_uop.bits.dis_col_sel, issue_slots[8].in_uop.bits.dis_col_sel connect slots_8.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[8].in_uop.bits.iw_p3_bypass_hint connect slots_8.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[8].in_uop.bits.iw_p2_bypass_hint connect slots_8.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[8].in_uop.bits.iw_p1_bypass_hint connect slots_8.io.in_uop.bits.iw_p2_speculative_child, issue_slots[8].in_uop.bits.iw_p2_speculative_child connect slots_8.io.in_uop.bits.iw_p1_speculative_child, issue_slots[8].in_uop.bits.iw_p1_speculative_child connect slots_8.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[8].in_uop.bits.iw_issued_partial_dgen connect slots_8.io.in_uop.bits.iw_issued_partial_agen, issue_slots[8].in_uop.bits.iw_issued_partial_agen connect slots_8.io.in_uop.bits.iw_issued, issue_slots[8].in_uop.bits.iw_issued connect slots_8.io.in_uop.bits.fu_code[0], issue_slots[8].in_uop.bits.fu_code[0] connect slots_8.io.in_uop.bits.fu_code[1], issue_slots[8].in_uop.bits.fu_code[1] connect slots_8.io.in_uop.bits.fu_code[2], issue_slots[8].in_uop.bits.fu_code[2] connect slots_8.io.in_uop.bits.fu_code[3], issue_slots[8].in_uop.bits.fu_code[3] connect slots_8.io.in_uop.bits.fu_code[4], issue_slots[8].in_uop.bits.fu_code[4] connect slots_8.io.in_uop.bits.fu_code[5], issue_slots[8].in_uop.bits.fu_code[5] connect slots_8.io.in_uop.bits.fu_code[6], issue_slots[8].in_uop.bits.fu_code[6] connect slots_8.io.in_uop.bits.fu_code[7], issue_slots[8].in_uop.bits.fu_code[7] connect slots_8.io.in_uop.bits.fu_code[8], issue_slots[8].in_uop.bits.fu_code[8] connect slots_8.io.in_uop.bits.fu_code[9], issue_slots[8].in_uop.bits.fu_code[9] connect slots_8.io.in_uop.bits.iq_type[0], issue_slots[8].in_uop.bits.iq_type[0] connect slots_8.io.in_uop.bits.iq_type[1], issue_slots[8].in_uop.bits.iq_type[1] connect slots_8.io.in_uop.bits.iq_type[2], issue_slots[8].in_uop.bits.iq_type[2] connect slots_8.io.in_uop.bits.iq_type[3], issue_slots[8].in_uop.bits.iq_type[3] connect slots_8.io.in_uop.bits.debug_pc, issue_slots[8].in_uop.bits.debug_pc connect slots_8.io.in_uop.bits.is_rvc, issue_slots[8].in_uop.bits.is_rvc connect slots_8.io.in_uop.bits.debug_inst, issue_slots[8].in_uop.bits.debug_inst connect slots_8.io.in_uop.bits.inst, issue_slots[8].in_uop.bits.inst connect slots_8.io.in_uop.valid, issue_slots[8].in_uop.valid connect issue_slots[8].iss_uop.debug_tsrc, slots_8.io.iss_uop.debug_tsrc connect issue_slots[8].iss_uop.debug_fsrc, slots_8.io.iss_uop.debug_fsrc connect issue_slots[8].iss_uop.bp_xcpt_if, slots_8.io.iss_uop.bp_xcpt_if connect issue_slots[8].iss_uop.bp_debug_if, slots_8.io.iss_uop.bp_debug_if connect issue_slots[8].iss_uop.xcpt_ma_if, slots_8.io.iss_uop.xcpt_ma_if connect issue_slots[8].iss_uop.xcpt_ae_if, slots_8.io.iss_uop.xcpt_ae_if connect issue_slots[8].iss_uop.xcpt_pf_if, slots_8.io.iss_uop.xcpt_pf_if connect issue_slots[8].iss_uop.fp_typ, slots_8.io.iss_uop.fp_typ connect issue_slots[8].iss_uop.fp_rm, slots_8.io.iss_uop.fp_rm connect issue_slots[8].iss_uop.fp_val, slots_8.io.iss_uop.fp_val connect issue_slots[8].iss_uop.fcn_op, slots_8.io.iss_uop.fcn_op connect issue_slots[8].iss_uop.fcn_dw, slots_8.io.iss_uop.fcn_dw connect issue_slots[8].iss_uop.frs3_en, slots_8.io.iss_uop.frs3_en connect issue_slots[8].iss_uop.lrs2_rtype, slots_8.io.iss_uop.lrs2_rtype connect issue_slots[8].iss_uop.lrs1_rtype, slots_8.io.iss_uop.lrs1_rtype connect issue_slots[8].iss_uop.dst_rtype, slots_8.io.iss_uop.dst_rtype connect issue_slots[8].iss_uop.lrs3, slots_8.io.iss_uop.lrs3 connect issue_slots[8].iss_uop.lrs2, slots_8.io.iss_uop.lrs2 connect issue_slots[8].iss_uop.lrs1, slots_8.io.iss_uop.lrs1 connect issue_slots[8].iss_uop.ldst, slots_8.io.iss_uop.ldst connect issue_slots[8].iss_uop.ldst_is_rs1, slots_8.io.iss_uop.ldst_is_rs1 connect issue_slots[8].iss_uop.csr_cmd, slots_8.io.iss_uop.csr_cmd connect issue_slots[8].iss_uop.flush_on_commit, slots_8.io.iss_uop.flush_on_commit connect issue_slots[8].iss_uop.is_unique, slots_8.io.iss_uop.is_unique connect issue_slots[8].iss_uop.uses_stq, slots_8.io.iss_uop.uses_stq connect issue_slots[8].iss_uop.uses_ldq, slots_8.io.iss_uop.uses_ldq connect issue_slots[8].iss_uop.mem_signed, slots_8.io.iss_uop.mem_signed connect issue_slots[8].iss_uop.mem_size, slots_8.io.iss_uop.mem_size connect issue_slots[8].iss_uop.mem_cmd, slots_8.io.iss_uop.mem_cmd connect issue_slots[8].iss_uop.exc_cause, slots_8.io.iss_uop.exc_cause connect issue_slots[8].iss_uop.exception, slots_8.io.iss_uop.exception connect issue_slots[8].iss_uop.stale_pdst, slots_8.io.iss_uop.stale_pdst connect issue_slots[8].iss_uop.ppred_busy, slots_8.io.iss_uop.ppred_busy connect issue_slots[8].iss_uop.prs3_busy, slots_8.io.iss_uop.prs3_busy connect issue_slots[8].iss_uop.prs2_busy, slots_8.io.iss_uop.prs2_busy connect issue_slots[8].iss_uop.prs1_busy, slots_8.io.iss_uop.prs1_busy connect issue_slots[8].iss_uop.ppred, slots_8.io.iss_uop.ppred connect issue_slots[8].iss_uop.prs3, slots_8.io.iss_uop.prs3 connect issue_slots[8].iss_uop.prs2, slots_8.io.iss_uop.prs2 connect issue_slots[8].iss_uop.prs1, slots_8.io.iss_uop.prs1 connect issue_slots[8].iss_uop.pdst, slots_8.io.iss_uop.pdst connect issue_slots[8].iss_uop.rxq_idx, slots_8.io.iss_uop.rxq_idx connect issue_slots[8].iss_uop.stq_idx, slots_8.io.iss_uop.stq_idx connect issue_slots[8].iss_uop.ldq_idx, slots_8.io.iss_uop.ldq_idx connect issue_slots[8].iss_uop.rob_idx, slots_8.io.iss_uop.rob_idx connect issue_slots[8].iss_uop.fp_ctrl.vec, slots_8.io.iss_uop.fp_ctrl.vec connect issue_slots[8].iss_uop.fp_ctrl.wflags, slots_8.io.iss_uop.fp_ctrl.wflags connect issue_slots[8].iss_uop.fp_ctrl.sqrt, slots_8.io.iss_uop.fp_ctrl.sqrt connect issue_slots[8].iss_uop.fp_ctrl.div, slots_8.io.iss_uop.fp_ctrl.div connect issue_slots[8].iss_uop.fp_ctrl.fma, slots_8.io.iss_uop.fp_ctrl.fma connect issue_slots[8].iss_uop.fp_ctrl.fastpipe, slots_8.io.iss_uop.fp_ctrl.fastpipe connect issue_slots[8].iss_uop.fp_ctrl.toint, slots_8.io.iss_uop.fp_ctrl.toint connect issue_slots[8].iss_uop.fp_ctrl.fromint, slots_8.io.iss_uop.fp_ctrl.fromint connect issue_slots[8].iss_uop.fp_ctrl.typeTagOut, slots_8.io.iss_uop.fp_ctrl.typeTagOut connect issue_slots[8].iss_uop.fp_ctrl.typeTagIn, slots_8.io.iss_uop.fp_ctrl.typeTagIn connect issue_slots[8].iss_uop.fp_ctrl.swap23, slots_8.io.iss_uop.fp_ctrl.swap23 connect issue_slots[8].iss_uop.fp_ctrl.swap12, slots_8.io.iss_uop.fp_ctrl.swap12 connect issue_slots[8].iss_uop.fp_ctrl.ren3, slots_8.io.iss_uop.fp_ctrl.ren3 connect issue_slots[8].iss_uop.fp_ctrl.ren2, slots_8.io.iss_uop.fp_ctrl.ren2 connect issue_slots[8].iss_uop.fp_ctrl.ren1, slots_8.io.iss_uop.fp_ctrl.ren1 connect issue_slots[8].iss_uop.fp_ctrl.wen, slots_8.io.iss_uop.fp_ctrl.wen connect issue_slots[8].iss_uop.fp_ctrl.ldst, slots_8.io.iss_uop.fp_ctrl.ldst connect issue_slots[8].iss_uop.op2_sel, slots_8.io.iss_uop.op2_sel connect issue_slots[8].iss_uop.op1_sel, slots_8.io.iss_uop.op1_sel connect issue_slots[8].iss_uop.imm_packed, slots_8.io.iss_uop.imm_packed connect issue_slots[8].iss_uop.pimm, slots_8.io.iss_uop.pimm connect issue_slots[8].iss_uop.imm_sel, slots_8.io.iss_uop.imm_sel connect issue_slots[8].iss_uop.imm_rename, slots_8.io.iss_uop.imm_rename connect issue_slots[8].iss_uop.taken, slots_8.io.iss_uop.taken connect issue_slots[8].iss_uop.pc_lob, slots_8.io.iss_uop.pc_lob connect issue_slots[8].iss_uop.edge_inst, slots_8.io.iss_uop.edge_inst connect issue_slots[8].iss_uop.ftq_idx, slots_8.io.iss_uop.ftq_idx connect issue_slots[8].iss_uop.is_mov, slots_8.io.iss_uop.is_mov connect issue_slots[8].iss_uop.is_rocc, slots_8.io.iss_uop.is_rocc connect issue_slots[8].iss_uop.is_sys_pc2epc, slots_8.io.iss_uop.is_sys_pc2epc connect issue_slots[8].iss_uop.is_eret, slots_8.io.iss_uop.is_eret connect issue_slots[8].iss_uop.is_amo, slots_8.io.iss_uop.is_amo connect issue_slots[8].iss_uop.is_sfence, slots_8.io.iss_uop.is_sfence connect issue_slots[8].iss_uop.is_fencei, slots_8.io.iss_uop.is_fencei connect issue_slots[8].iss_uop.is_fence, slots_8.io.iss_uop.is_fence connect issue_slots[8].iss_uop.is_sfb, slots_8.io.iss_uop.is_sfb connect issue_slots[8].iss_uop.br_type, slots_8.io.iss_uop.br_type connect issue_slots[8].iss_uop.br_tag, slots_8.io.iss_uop.br_tag connect issue_slots[8].iss_uop.br_mask, slots_8.io.iss_uop.br_mask connect issue_slots[8].iss_uop.dis_col_sel, slots_8.io.iss_uop.dis_col_sel connect issue_slots[8].iss_uop.iw_p3_bypass_hint, slots_8.io.iss_uop.iw_p3_bypass_hint connect issue_slots[8].iss_uop.iw_p2_bypass_hint, slots_8.io.iss_uop.iw_p2_bypass_hint connect issue_slots[8].iss_uop.iw_p1_bypass_hint, slots_8.io.iss_uop.iw_p1_bypass_hint connect issue_slots[8].iss_uop.iw_p2_speculative_child, slots_8.io.iss_uop.iw_p2_speculative_child connect issue_slots[8].iss_uop.iw_p1_speculative_child, slots_8.io.iss_uop.iw_p1_speculative_child connect issue_slots[8].iss_uop.iw_issued_partial_dgen, slots_8.io.iss_uop.iw_issued_partial_dgen connect issue_slots[8].iss_uop.iw_issued_partial_agen, slots_8.io.iss_uop.iw_issued_partial_agen connect issue_slots[8].iss_uop.iw_issued, slots_8.io.iss_uop.iw_issued connect issue_slots[8].iss_uop.fu_code[0], slots_8.io.iss_uop.fu_code[0] connect issue_slots[8].iss_uop.fu_code[1], slots_8.io.iss_uop.fu_code[1] connect issue_slots[8].iss_uop.fu_code[2], slots_8.io.iss_uop.fu_code[2] connect issue_slots[8].iss_uop.fu_code[3], slots_8.io.iss_uop.fu_code[3] connect issue_slots[8].iss_uop.fu_code[4], slots_8.io.iss_uop.fu_code[4] connect issue_slots[8].iss_uop.fu_code[5], slots_8.io.iss_uop.fu_code[5] connect issue_slots[8].iss_uop.fu_code[6], slots_8.io.iss_uop.fu_code[6] connect issue_slots[8].iss_uop.fu_code[7], slots_8.io.iss_uop.fu_code[7] connect issue_slots[8].iss_uop.fu_code[8], slots_8.io.iss_uop.fu_code[8] connect issue_slots[8].iss_uop.fu_code[9], slots_8.io.iss_uop.fu_code[9] connect issue_slots[8].iss_uop.iq_type[0], slots_8.io.iss_uop.iq_type[0] connect issue_slots[8].iss_uop.iq_type[1], slots_8.io.iss_uop.iq_type[1] connect issue_slots[8].iss_uop.iq_type[2], slots_8.io.iss_uop.iq_type[2] connect issue_slots[8].iss_uop.iq_type[3], slots_8.io.iss_uop.iq_type[3] connect issue_slots[8].iss_uop.debug_pc, slots_8.io.iss_uop.debug_pc connect issue_slots[8].iss_uop.is_rvc, slots_8.io.iss_uop.is_rvc connect issue_slots[8].iss_uop.debug_inst, slots_8.io.iss_uop.debug_inst connect issue_slots[8].iss_uop.inst, slots_8.io.iss_uop.inst connect slots_8.io.grant, issue_slots[8].grant connect issue_slots[8].request, slots_8.io.request connect issue_slots[8].will_be_valid, slots_8.io.will_be_valid connect issue_slots[8].valid, slots_8.io.valid connect slots_9.io.child_rebusys, issue_slots[9].child_rebusys connect slots_9.io.pred_wakeup_port.bits, issue_slots[9].pred_wakeup_port.bits connect slots_9.io.pred_wakeup_port.valid, issue_slots[9].pred_wakeup_port.valid connect slots_9.io.wakeup_ports[0].bits.rebusy, issue_slots[9].wakeup_ports[0].bits.rebusy connect slots_9.io.wakeup_ports[0].bits.speculative_mask, issue_slots[9].wakeup_ports[0].bits.speculative_mask connect slots_9.io.wakeup_ports[0].bits.bypassable, issue_slots[9].wakeup_ports[0].bits.bypassable connect slots_9.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[9].wakeup_ports[0].bits.uop.debug_tsrc connect slots_9.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[9].wakeup_ports[0].bits.uop.debug_fsrc connect slots_9.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[9].wakeup_ports[0].bits.uop.bp_xcpt_if connect slots_9.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[9].wakeup_ports[0].bits.uop.bp_debug_if connect slots_9.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[9].wakeup_ports[0].bits.uop.xcpt_ma_if connect slots_9.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[9].wakeup_ports[0].bits.uop.xcpt_ae_if connect slots_9.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[9].wakeup_ports[0].bits.uop.xcpt_pf_if connect slots_9.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[9].wakeup_ports[0].bits.uop.fp_typ connect slots_9.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[9].wakeup_ports[0].bits.uop.fp_rm connect slots_9.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[9].wakeup_ports[0].bits.uop.fp_val connect slots_9.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[9].wakeup_ports[0].bits.uop.fcn_op connect slots_9.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[9].wakeup_ports[0].bits.uop.fcn_dw connect slots_9.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[9].wakeup_ports[0].bits.uop.frs3_en connect slots_9.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[9].wakeup_ports[0].bits.uop.lrs2_rtype connect slots_9.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[9].wakeup_ports[0].bits.uop.lrs1_rtype connect slots_9.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[9].wakeup_ports[0].bits.uop.dst_rtype connect slots_9.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[9].wakeup_ports[0].bits.uop.lrs3 connect slots_9.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[9].wakeup_ports[0].bits.uop.lrs2 connect slots_9.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[9].wakeup_ports[0].bits.uop.lrs1 connect slots_9.io.wakeup_ports[0].bits.uop.ldst, issue_slots[9].wakeup_ports[0].bits.uop.ldst connect slots_9.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[9].wakeup_ports[0].bits.uop.ldst_is_rs1 connect slots_9.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[9].wakeup_ports[0].bits.uop.csr_cmd connect slots_9.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[9].wakeup_ports[0].bits.uop.flush_on_commit connect slots_9.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[9].wakeup_ports[0].bits.uop.is_unique connect slots_9.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[9].wakeup_ports[0].bits.uop.uses_stq connect slots_9.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[9].wakeup_ports[0].bits.uop.uses_ldq connect slots_9.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[9].wakeup_ports[0].bits.uop.mem_signed connect slots_9.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[9].wakeup_ports[0].bits.uop.mem_size connect slots_9.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[9].wakeup_ports[0].bits.uop.mem_cmd connect slots_9.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[9].wakeup_ports[0].bits.uop.exc_cause connect slots_9.io.wakeup_ports[0].bits.uop.exception, issue_slots[9].wakeup_ports[0].bits.uop.exception connect slots_9.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[9].wakeup_ports[0].bits.uop.stale_pdst connect slots_9.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[9].wakeup_ports[0].bits.uop.ppred_busy connect slots_9.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[9].wakeup_ports[0].bits.uop.prs3_busy connect slots_9.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[9].wakeup_ports[0].bits.uop.prs2_busy connect slots_9.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[9].wakeup_ports[0].bits.uop.prs1_busy connect slots_9.io.wakeup_ports[0].bits.uop.ppred, issue_slots[9].wakeup_ports[0].bits.uop.ppred connect slots_9.io.wakeup_ports[0].bits.uop.prs3, issue_slots[9].wakeup_ports[0].bits.uop.prs3 connect slots_9.io.wakeup_ports[0].bits.uop.prs2, issue_slots[9].wakeup_ports[0].bits.uop.prs2 connect slots_9.io.wakeup_ports[0].bits.uop.prs1, issue_slots[9].wakeup_ports[0].bits.uop.prs1 connect slots_9.io.wakeup_ports[0].bits.uop.pdst, issue_slots[9].wakeup_ports[0].bits.uop.pdst connect slots_9.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[9].wakeup_ports[0].bits.uop.rxq_idx connect slots_9.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[9].wakeup_ports[0].bits.uop.stq_idx connect slots_9.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[9].wakeup_ports[0].bits.uop.ldq_idx connect slots_9.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[9].wakeup_ports[0].bits.uop.rob_idx connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.vec connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.wflags connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.div connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.fma connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.toint connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.fromint connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.wen connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.ldst connect slots_9.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[9].wakeup_ports[0].bits.uop.op2_sel connect slots_9.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[9].wakeup_ports[0].bits.uop.op1_sel connect slots_9.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[9].wakeup_ports[0].bits.uop.imm_packed connect slots_9.io.wakeup_ports[0].bits.uop.pimm, issue_slots[9].wakeup_ports[0].bits.uop.pimm connect slots_9.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[9].wakeup_ports[0].bits.uop.imm_sel connect slots_9.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[9].wakeup_ports[0].bits.uop.imm_rename connect slots_9.io.wakeup_ports[0].bits.uop.taken, issue_slots[9].wakeup_ports[0].bits.uop.taken connect slots_9.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[9].wakeup_ports[0].bits.uop.pc_lob connect slots_9.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[9].wakeup_ports[0].bits.uop.edge_inst connect slots_9.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[9].wakeup_ports[0].bits.uop.ftq_idx connect slots_9.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[9].wakeup_ports[0].bits.uop.is_mov connect slots_9.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[9].wakeup_ports[0].bits.uop.is_rocc connect slots_9.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[9].wakeup_ports[0].bits.uop.is_sys_pc2epc connect slots_9.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[9].wakeup_ports[0].bits.uop.is_eret connect slots_9.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[9].wakeup_ports[0].bits.uop.is_amo connect slots_9.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[9].wakeup_ports[0].bits.uop.is_sfence connect slots_9.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[9].wakeup_ports[0].bits.uop.is_fencei connect slots_9.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[9].wakeup_ports[0].bits.uop.is_fence connect slots_9.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[9].wakeup_ports[0].bits.uop.is_sfb connect slots_9.io.wakeup_ports[0].bits.uop.br_type, issue_slots[9].wakeup_ports[0].bits.uop.br_type connect slots_9.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[9].wakeup_ports[0].bits.uop.br_tag connect slots_9.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[9].wakeup_ports[0].bits.uop.br_mask connect slots_9.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[9].wakeup_ports[0].bits.uop.dis_col_sel connect slots_9.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[9].wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect slots_9.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[9].wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect slots_9.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[9].wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect slots_9.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[9].wakeup_ports[0].bits.uop.iw_p2_speculative_child connect slots_9.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[9].wakeup_ports[0].bits.uop.iw_p1_speculative_child connect slots_9.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[9].wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect slots_9.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[9].wakeup_ports[0].bits.uop.iw_issued_partial_agen connect slots_9.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[9].wakeup_ports[0].bits.uop.iw_issued connect slots_9.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[9].wakeup_ports[0].bits.uop.fu_code[0] connect slots_9.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[9].wakeup_ports[0].bits.uop.fu_code[1] connect slots_9.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[9].wakeup_ports[0].bits.uop.fu_code[2] connect slots_9.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[9].wakeup_ports[0].bits.uop.fu_code[3] connect slots_9.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[9].wakeup_ports[0].bits.uop.fu_code[4] connect slots_9.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[9].wakeup_ports[0].bits.uop.fu_code[5] connect slots_9.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[9].wakeup_ports[0].bits.uop.fu_code[6] connect slots_9.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[9].wakeup_ports[0].bits.uop.fu_code[7] connect slots_9.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[9].wakeup_ports[0].bits.uop.fu_code[8] connect slots_9.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[9].wakeup_ports[0].bits.uop.fu_code[9] connect slots_9.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[9].wakeup_ports[0].bits.uop.iq_type[0] connect slots_9.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[9].wakeup_ports[0].bits.uop.iq_type[1] connect slots_9.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[9].wakeup_ports[0].bits.uop.iq_type[2] connect slots_9.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[9].wakeup_ports[0].bits.uop.iq_type[3] connect slots_9.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[9].wakeup_ports[0].bits.uop.debug_pc connect slots_9.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[9].wakeup_ports[0].bits.uop.is_rvc connect slots_9.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[9].wakeup_ports[0].bits.uop.debug_inst connect slots_9.io.wakeup_ports[0].bits.uop.inst, issue_slots[9].wakeup_ports[0].bits.uop.inst connect slots_9.io.wakeup_ports[0].valid, issue_slots[9].wakeup_ports[0].valid connect slots_9.io.wakeup_ports[1].bits.rebusy, issue_slots[9].wakeup_ports[1].bits.rebusy connect slots_9.io.wakeup_ports[1].bits.speculative_mask, issue_slots[9].wakeup_ports[1].bits.speculative_mask connect slots_9.io.wakeup_ports[1].bits.bypassable, issue_slots[9].wakeup_ports[1].bits.bypassable connect slots_9.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[9].wakeup_ports[1].bits.uop.debug_tsrc connect slots_9.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[9].wakeup_ports[1].bits.uop.debug_fsrc connect slots_9.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[9].wakeup_ports[1].bits.uop.bp_xcpt_if connect slots_9.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[9].wakeup_ports[1].bits.uop.bp_debug_if connect slots_9.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[9].wakeup_ports[1].bits.uop.xcpt_ma_if connect slots_9.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[9].wakeup_ports[1].bits.uop.xcpt_ae_if connect slots_9.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[9].wakeup_ports[1].bits.uop.xcpt_pf_if connect slots_9.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[9].wakeup_ports[1].bits.uop.fp_typ connect slots_9.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[9].wakeup_ports[1].bits.uop.fp_rm connect slots_9.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[9].wakeup_ports[1].bits.uop.fp_val connect slots_9.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[9].wakeup_ports[1].bits.uop.fcn_op connect slots_9.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[9].wakeup_ports[1].bits.uop.fcn_dw connect slots_9.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[9].wakeup_ports[1].bits.uop.frs3_en connect slots_9.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[9].wakeup_ports[1].bits.uop.lrs2_rtype connect slots_9.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[9].wakeup_ports[1].bits.uop.lrs1_rtype connect slots_9.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[9].wakeup_ports[1].bits.uop.dst_rtype connect slots_9.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[9].wakeup_ports[1].bits.uop.lrs3 connect slots_9.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[9].wakeup_ports[1].bits.uop.lrs2 connect slots_9.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[9].wakeup_ports[1].bits.uop.lrs1 connect slots_9.io.wakeup_ports[1].bits.uop.ldst, issue_slots[9].wakeup_ports[1].bits.uop.ldst connect slots_9.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[9].wakeup_ports[1].bits.uop.ldst_is_rs1 connect slots_9.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[9].wakeup_ports[1].bits.uop.csr_cmd connect slots_9.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[9].wakeup_ports[1].bits.uop.flush_on_commit connect slots_9.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[9].wakeup_ports[1].bits.uop.is_unique connect slots_9.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[9].wakeup_ports[1].bits.uop.uses_stq connect slots_9.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[9].wakeup_ports[1].bits.uop.uses_ldq connect slots_9.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[9].wakeup_ports[1].bits.uop.mem_signed connect slots_9.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[9].wakeup_ports[1].bits.uop.mem_size connect slots_9.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[9].wakeup_ports[1].bits.uop.mem_cmd connect slots_9.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[9].wakeup_ports[1].bits.uop.exc_cause connect slots_9.io.wakeup_ports[1].bits.uop.exception, issue_slots[9].wakeup_ports[1].bits.uop.exception connect slots_9.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[9].wakeup_ports[1].bits.uop.stale_pdst connect slots_9.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[9].wakeup_ports[1].bits.uop.ppred_busy connect slots_9.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[9].wakeup_ports[1].bits.uop.prs3_busy connect slots_9.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[9].wakeup_ports[1].bits.uop.prs2_busy connect slots_9.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[9].wakeup_ports[1].bits.uop.prs1_busy connect slots_9.io.wakeup_ports[1].bits.uop.ppred, issue_slots[9].wakeup_ports[1].bits.uop.ppred connect slots_9.io.wakeup_ports[1].bits.uop.prs3, issue_slots[9].wakeup_ports[1].bits.uop.prs3 connect slots_9.io.wakeup_ports[1].bits.uop.prs2, issue_slots[9].wakeup_ports[1].bits.uop.prs2 connect slots_9.io.wakeup_ports[1].bits.uop.prs1, issue_slots[9].wakeup_ports[1].bits.uop.prs1 connect slots_9.io.wakeup_ports[1].bits.uop.pdst, issue_slots[9].wakeup_ports[1].bits.uop.pdst connect slots_9.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[9].wakeup_ports[1].bits.uop.rxq_idx connect slots_9.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[9].wakeup_ports[1].bits.uop.stq_idx connect slots_9.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[9].wakeup_ports[1].bits.uop.ldq_idx connect slots_9.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[9].wakeup_ports[1].bits.uop.rob_idx connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.vec connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.wflags connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.div connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.fma connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.toint connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.fromint connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.wen connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.ldst connect slots_9.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[9].wakeup_ports[1].bits.uop.op2_sel connect slots_9.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[9].wakeup_ports[1].bits.uop.op1_sel connect slots_9.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[9].wakeup_ports[1].bits.uop.imm_packed connect slots_9.io.wakeup_ports[1].bits.uop.pimm, issue_slots[9].wakeup_ports[1].bits.uop.pimm connect slots_9.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[9].wakeup_ports[1].bits.uop.imm_sel connect slots_9.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[9].wakeup_ports[1].bits.uop.imm_rename connect slots_9.io.wakeup_ports[1].bits.uop.taken, issue_slots[9].wakeup_ports[1].bits.uop.taken connect slots_9.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[9].wakeup_ports[1].bits.uop.pc_lob connect slots_9.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[9].wakeup_ports[1].bits.uop.edge_inst connect slots_9.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[9].wakeup_ports[1].bits.uop.ftq_idx connect slots_9.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[9].wakeup_ports[1].bits.uop.is_mov connect slots_9.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[9].wakeup_ports[1].bits.uop.is_rocc connect slots_9.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[9].wakeup_ports[1].bits.uop.is_sys_pc2epc connect slots_9.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[9].wakeup_ports[1].bits.uop.is_eret connect slots_9.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[9].wakeup_ports[1].bits.uop.is_amo connect slots_9.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[9].wakeup_ports[1].bits.uop.is_sfence connect slots_9.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[9].wakeup_ports[1].bits.uop.is_fencei connect slots_9.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[9].wakeup_ports[1].bits.uop.is_fence connect slots_9.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[9].wakeup_ports[1].bits.uop.is_sfb connect slots_9.io.wakeup_ports[1].bits.uop.br_type, issue_slots[9].wakeup_ports[1].bits.uop.br_type connect slots_9.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[9].wakeup_ports[1].bits.uop.br_tag connect slots_9.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[9].wakeup_ports[1].bits.uop.br_mask connect slots_9.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[9].wakeup_ports[1].bits.uop.dis_col_sel connect slots_9.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[9].wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect slots_9.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[9].wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect slots_9.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[9].wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect slots_9.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[9].wakeup_ports[1].bits.uop.iw_p2_speculative_child connect slots_9.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[9].wakeup_ports[1].bits.uop.iw_p1_speculative_child connect slots_9.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[9].wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect slots_9.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[9].wakeup_ports[1].bits.uop.iw_issued_partial_agen connect slots_9.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[9].wakeup_ports[1].bits.uop.iw_issued connect slots_9.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[9].wakeup_ports[1].bits.uop.fu_code[0] connect slots_9.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[9].wakeup_ports[1].bits.uop.fu_code[1] connect slots_9.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[9].wakeup_ports[1].bits.uop.fu_code[2] connect slots_9.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[9].wakeup_ports[1].bits.uop.fu_code[3] connect slots_9.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[9].wakeup_ports[1].bits.uop.fu_code[4] connect slots_9.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[9].wakeup_ports[1].bits.uop.fu_code[5] connect slots_9.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[9].wakeup_ports[1].bits.uop.fu_code[6] connect slots_9.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[9].wakeup_ports[1].bits.uop.fu_code[7] connect slots_9.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[9].wakeup_ports[1].bits.uop.fu_code[8] connect slots_9.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[9].wakeup_ports[1].bits.uop.fu_code[9] connect slots_9.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[9].wakeup_ports[1].bits.uop.iq_type[0] connect slots_9.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[9].wakeup_ports[1].bits.uop.iq_type[1] connect slots_9.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[9].wakeup_ports[1].bits.uop.iq_type[2] connect slots_9.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[9].wakeup_ports[1].bits.uop.iq_type[3] connect slots_9.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[9].wakeup_ports[1].bits.uop.debug_pc connect slots_9.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[9].wakeup_ports[1].bits.uop.is_rvc connect slots_9.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[9].wakeup_ports[1].bits.uop.debug_inst connect slots_9.io.wakeup_ports[1].bits.uop.inst, issue_slots[9].wakeup_ports[1].bits.uop.inst connect slots_9.io.wakeup_ports[1].valid, issue_slots[9].wakeup_ports[1].valid connect slots_9.io.wakeup_ports[2].bits.rebusy, issue_slots[9].wakeup_ports[2].bits.rebusy connect slots_9.io.wakeup_ports[2].bits.speculative_mask, issue_slots[9].wakeup_ports[2].bits.speculative_mask connect slots_9.io.wakeup_ports[2].bits.bypassable, issue_slots[9].wakeup_ports[2].bits.bypassable connect slots_9.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[9].wakeup_ports[2].bits.uop.debug_tsrc connect slots_9.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[9].wakeup_ports[2].bits.uop.debug_fsrc connect slots_9.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[9].wakeup_ports[2].bits.uop.bp_xcpt_if connect slots_9.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[9].wakeup_ports[2].bits.uop.bp_debug_if connect slots_9.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[9].wakeup_ports[2].bits.uop.xcpt_ma_if connect slots_9.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[9].wakeup_ports[2].bits.uop.xcpt_ae_if connect slots_9.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[9].wakeup_ports[2].bits.uop.xcpt_pf_if connect slots_9.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[9].wakeup_ports[2].bits.uop.fp_typ connect slots_9.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[9].wakeup_ports[2].bits.uop.fp_rm connect slots_9.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[9].wakeup_ports[2].bits.uop.fp_val connect slots_9.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[9].wakeup_ports[2].bits.uop.fcn_op connect slots_9.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[9].wakeup_ports[2].bits.uop.fcn_dw connect slots_9.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[9].wakeup_ports[2].bits.uop.frs3_en connect slots_9.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[9].wakeup_ports[2].bits.uop.lrs2_rtype connect slots_9.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[9].wakeup_ports[2].bits.uop.lrs1_rtype connect slots_9.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[9].wakeup_ports[2].bits.uop.dst_rtype connect slots_9.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[9].wakeup_ports[2].bits.uop.lrs3 connect slots_9.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[9].wakeup_ports[2].bits.uop.lrs2 connect slots_9.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[9].wakeup_ports[2].bits.uop.lrs1 connect slots_9.io.wakeup_ports[2].bits.uop.ldst, issue_slots[9].wakeup_ports[2].bits.uop.ldst connect slots_9.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[9].wakeup_ports[2].bits.uop.ldst_is_rs1 connect slots_9.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[9].wakeup_ports[2].bits.uop.csr_cmd connect slots_9.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[9].wakeup_ports[2].bits.uop.flush_on_commit connect slots_9.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[9].wakeup_ports[2].bits.uop.is_unique connect slots_9.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[9].wakeup_ports[2].bits.uop.uses_stq connect slots_9.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[9].wakeup_ports[2].bits.uop.uses_ldq connect slots_9.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[9].wakeup_ports[2].bits.uop.mem_signed connect slots_9.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[9].wakeup_ports[2].bits.uop.mem_size connect slots_9.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[9].wakeup_ports[2].bits.uop.mem_cmd connect slots_9.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[9].wakeup_ports[2].bits.uop.exc_cause connect slots_9.io.wakeup_ports[2].bits.uop.exception, issue_slots[9].wakeup_ports[2].bits.uop.exception connect slots_9.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[9].wakeup_ports[2].bits.uop.stale_pdst connect slots_9.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[9].wakeup_ports[2].bits.uop.ppred_busy connect slots_9.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[9].wakeup_ports[2].bits.uop.prs3_busy connect slots_9.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[9].wakeup_ports[2].bits.uop.prs2_busy connect slots_9.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[9].wakeup_ports[2].bits.uop.prs1_busy connect slots_9.io.wakeup_ports[2].bits.uop.ppred, issue_slots[9].wakeup_ports[2].bits.uop.ppred connect slots_9.io.wakeup_ports[2].bits.uop.prs3, issue_slots[9].wakeup_ports[2].bits.uop.prs3 connect slots_9.io.wakeup_ports[2].bits.uop.prs2, issue_slots[9].wakeup_ports[2].bits.uop.prs2 connect slots_9.io.wakeup_ports[2].bits.uop.prs1, issue_slots[9].wakeup_ports[2].bits.uop.prs1 connect slots_9.io.wakeup_ports[2].bits.uop.pdst, issue_slots[9].wakeup_ports[2].bits.uop.pdst connect slots_9.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[9].wakeup_ports[2].bits.uop.rxq_idx connect slots_9.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[9].wakeup_ports[2].bits.uop.stq_idx connect slots_9.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[9].wakeup_ports[2].bits.uop.ldq_idx connect slots_9.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[9].wakeup_ports[2].bits.uop.rob_idx connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.vec connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.wflags connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.div connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.fma connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.toint connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.fromint connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.wen connect slots_9.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.ldst connect slots_9.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[9].wakeup_ports[2].bits.uop.op2_sel connect slots_9.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[9].wakeup_ports[2].bits.uop.op1_sel connect slots_9.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[9].wakeup_ports[2].bits.uop.imm_packed connect slots_9.io.wakeup_ports[2].bits.uop.pimm, issue_slots[9].wakeup_ports[2].bits.uop.pimm connect slots_9.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[9].wakeup_ports[2].bits.uop.imm_sel connect slots_9.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[9].wakeup_ports[2].bits.uop.imm_rename connect slots_9.io.wakeup_ports[2].bits.uop.taken, issue_slots[9].wakeup_ports[2].bits.uop.taken connect slots_9.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[9].wakeup_ports[2].bits.uop.pc_lob connect slots_9.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[9].wakeup_ports[2].bits.uop.edge_inst connect slots_9.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[9].wakeup_ports[2].bits.uop.ftq_idx connect slots_9.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[9].wakeup_ports[2].bits.uop.is_mov connect slots_9.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[9].wakeup_ports[2].bits.uop.is_rocc connect slots_9.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[9].wakeup_ports[2].bits.uop.is_sys_pc2epc connect slots_9.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[9].wakeup_ports[2].bits.uop.is_eret connect slots_9.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[9].wakeup_ports[2].bits.uop.is_amo connect slots_9.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[9].wakeup_ports[2].bits.uop.is_sfence connect slots_9.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[9].wakeup_ports[2].bits.uop.is_fencei connect slots_9.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[9].wakeup_ports[2].bits.uop.is_fence connect slots_9.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[9].wakeup_ports[2].bits.uop.is_sfb connect slots_9.io.wakeup_ports[2].bits.uop.br_type, issue_slots[9].wakeup_ports[2].bits.uop.br_type connect slots_9.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[9].wakeup_ports[2].bits.uop.br_tag connect slots_9.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[9].wakeup_ports[2].bits.uop.br_mask connect slots_9.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[9].wakeup_ports[2].bits.uop.dis_col_sel connect slots_9.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[9].wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect slots_9.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[9].wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect slots_9.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[9].wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect slots_9.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[9].wakeup_ports[2].bits.uop.iw_p2_speculative_child connect slots_9.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[9].wakeup_ports[2].bits.uop.iw_p1_speculative_child connect slots_9.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[9].wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect slots_9.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[9].wakeup_ports[2].bits.uop.iw_issued_partial_agen connect slots_9.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[9].wakeup_ports[2].bits.uop.iw_issued connect slots_9.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[9].wakeup_ports[2].bits.uop.fu_code[0] connect slots_9.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[9].wakeup_ports[2].bits.uop.fu_code[1] connect slots_9.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[9].wakeup_ports[2].bits.uop.fu_code[2] connect slots_9.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[9].wakeup_ports[2].bits.uop.fu_code[3] connect slots_9.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[9].wakeup_ports[2].bits.uop.fu_code[4] connect slots_9.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[9].wakeup_ports[2].bits.uop.fu_code[5] connect slots_9.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[9].wakeup_ports[2].bits.uop.fu_code[6] connect slots_9.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[9].wakeup_ports[2].bits.uop.fu_code[7] connect slots_9.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[9].wakeup_ports[2].bits.uop.fu_code[8] connect slots_9.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[9].wakeup_ports[2].bits.uop.fu_code[9] connect slots_9.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[9].wakeup_ports[2].bits.uop.iq_type[0] connect slots_9.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[9].wakeup_ports[2].bits.uop.iq_type[1] connect slots_9.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[9].wakeup_ports[2].bits.uop.iq_type[2] connect slots_9.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[9].wakeup_ports[2].bits.uop.iq_type[3] connect slots_9.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[9].wakeup_ports[2].bits.uop.debug_pc connect slots_9.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[9].wakeup_ports[2].bits.uop.is_rvc connect slots_9.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[9].wakeup_ports[2].bits.uop.debug_inst connect slots_9.io.wakeup_ports[2].bits.uop.inst, issue_slots[9].wakeup_ports[2].bits.uop.inst connect slots_9.io.wakeup_ports[2].valid, issue_slots[9].wakeup_ports[2].valid connect slots_9.io.wakeup_ports[3].bits.rebusy, issue_slots[9].wakeup_ports[3].bits.rebusy connect slots_9.io.wakeup_ports[3].bits.speculative_mask, issue_slots[9].wakeup_ports[3].bits.speculative_mask connect slots_9.io.wakeup_ports[3].bits.bypassable, issue_slots[9].wakeup_ports[3].bits.bypassable connect slots_9.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[9].wakeup_ports[3].bits.uop.debug_tsrc connect slots_9.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[9].wakeup_ports[3].bits.uop.debug_fsrc connect slots_9.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[9].wakeup_ports[3].bits.uop.bp_xcpt_if connect slots_9.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[9].wakeup_ports[3].bits.uop.bp_debug_if connect slots_9.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[9].wakeup_ports[3].bits.uop.xcpt_ma_if connect slots_9.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[9].wakeup_ports[3].bits.uop.xcpt_ae_if connect slots_9.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[9].wakeup_ports[3].bits.uop.xcpt_pf_if connect slots_9.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[9].wakeup_ports[3].bits.uop.fp_typ connect slots_9.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[9].wakeup_ports[3].bits.uop.fp_rm connect slots_9.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[9].wakeup_ports[3].bits.uop.fp_val connect slots_9.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[9].wakeup_ports[3].bits.uop.fcn_op connect slots_9.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[9].wakeup_ports[3].bits.uop.fcn_dw connect slots_9.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[9].wakeup_ports[3].bits.uop.frs3_en connect slots_9.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[9].wakeup_ports[3].bits.uop.lrs2_rtype connect slots_9.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[9].wakeup_ports[3].bits.uop.lrs1_rtype connect slots_9.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[9].wakeup_ports[3].bits.uop.dst_rtype connect slots_9.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[9].wakeup_ports[3].bits.uop.lrs3 connect slots_9.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[9].wakeup_ports[3].bits.uop.lrs2 connect slots_9.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[9].wakeup_ports[3].bits.uop.lrs1 connect slots_9.io.wakeup_ports[3].bits.uop.ldst, issue_slots[9].wakeup_ports[3].bits.uop.ldst connect slots_9.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[9].wakeup_ports[3].bits.uop.ldst_is_rs1 connect slots_9.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[9].wakeup_ports[3].bits.uop.csr_cmd connect slots_9.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[9].wakeup_ports[3].bits.uop.flush_on_commit connect slots_9.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[9].wakeup_ports[3].bits.uop.is_unique connect slots_9.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[9].wakeup_ports[3].bits.uop.uses_stq connect slots_9.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[9].wakeup_ports[3].bits.uop.uses_ldq connect slots_9.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[9].wakeup_ports[3].bits.uop.mem_signed connect slots_9.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[9].wakeup_ports[3].bits.uop.mem_size connect slots_9.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[9].wakeup_ports[3].bits.uop.mem_cmd connect slots_9.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[9].wakeup_ports[3].bits.uop.exc_cause connect slots_9.io.wakeup_ports[3].bits.uop.exception, issue_slots[9].wakeup_ports[3].bits.uop.exception connect slots_9.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[9].wakeup_ports[3].bits.uop.stale_pdst connect slots_9.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[9].wakeup_ports[3].bits.uop.ppred_busy connect slots_9.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[9].wakeup_ports[3].bits.uop.prs3_busy connect slots_9.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[9].wakeup_ports[3].bits.uop.prs2_busy connect slots_9.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[9].wakeup_ports[3].bits.uop.prs1_busy connect slots_9.io.wakeup_ports[3].bits.uop.ppred, issue_slots[9].wakeup_ports[3].bits.uop.ppred connect slots_9.io.wakeup_ports[3].bits.uop.prs3, issue_slots[9].wakeup_ports[3].bits.uop.prs3 connect slots_9.io.wakeup_ports[3].bits.uop.prs2, issue_slots[9].wakeup_ports[3].bits.uop.prs2 connect slots_9.io.wakeup_ports[3].bits.uop.prs1, issue_slots[9].wakeup_ports[3].bits.uop.prs1 connect slots_9.io.wakeup_ports[3].bits.uop.pdst, issue_slots[9].wakeup_ports[3].bits.uop.pdst connect slots_9.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[9].wakeup_ports[3].bits.uop.rxq_idx connect slots_9.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[9].wakeup_ports[3].bits.uop.stq_idx connect slots_9.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[9].wakeup_ports[3].bits.uop.ldq_idx connect slots_9.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[9].wakeup_ports[3].bits.uop.rob_idx connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.vec connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.wflags connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.div connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.fma connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.toint connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.fromint connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.wen connect slots_9.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.ldst connect slots_9.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[9].wakeup_ports[3].bits.uop.op2_sel connect slots_9.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[9].wakeup_ports[3].bits.uop.op1_sel connect slots_9.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[9].wakeup_ports[3].bits.uop.imm_packed connect slots_9.io.wakeup_ports[3].bits.uop.pimm, issue_slots[9].wakeup_ports[3].bits.uop.pimm connect slots_9.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[9].wakeup_ports[3].bits.uop.imm_sel connect slots_9.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[9].wakeup_ports[3].bits.uop.imm_rename connect slots_9.io.wakeup_ports[3].bits.uop.taken, issue_slots[9].wakeup_ports[3].bits.uop.taken connect slots_9.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[9].wakeup_ports[3].bits.uop.pc_lob connect slots_9.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[9].wakeup_ports[3].bits.uop.edge_inst connect slots_9.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[9].wakeup_ports[3].bits.uop.ftq_idx connect slots_9.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[9].wakeup_ports[3].bits.uop.is_mov connect slots_9.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[9].wakeup_ports[3].bits.uop.is_rocc connect slots_9.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[9].wakeup_ports[3].bits.uop.is_sys_pc2epc connect slots_9.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[9].wakeup_ports[3].bits.uop.is_eret connect slots_9.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[9].wakeup_ports[3].bits.uop.is_amo connect slots_9.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[9].wakeup_ports[3].bits.uop.is_sfence connect slots_9.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[9].wakeup_ports[3].bits.uop.is_fencei connect slots_9.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[9].wakeup_ports[3].bits.uop.is_fence connect slots_9.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[9].wakeup_ports[3].bits.uop.is_sfb connect slots_9.io.wakeup_ports[3].bits.uop.br_type, issue_slots[9].wakeup_ports[3].bits.uop.br_type connect slots_9.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[9].wakeup_ports[3].bits.uop.br_tag connect slots_9.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[9].wakeup_ports[3].bits.uop.br_mask connect slots_9.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[9].wakeup_ports[3].bits.uop.dis_col_sel connect slots_9.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[9].wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect slots_9.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[9].wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect slots_9.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[9].wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect slots_9.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[9].wakeup_ports[3].bits.uop.iw_p2_speculative_child connect slots_9.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[9].wakeup_ports[3].bits.uop.iw_p1_speculative_child connect slots_9.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[9].wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect slots_9.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[9].wakeup_ports[3].bits.uop.iw_issued_partial_agen connect slots_9.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[9].wakeup_ports[3].bits.uop.iw_issued connect slots_9.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[9].wakeup_ports[3].bits.uop.fu_code[0] connect slots_9.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[9].wakeup_ports[3].bits.uop.fu_code[1] connect slots_9.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[9].wakeup_ports[3].bits.uop.fu_code[2] connect slots_9.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[9].wakeup_ports[3].bits.uop.fu_code[3] connect slots_9.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[9].wakeup_ports[3].bits.uop.fu_code[4] connect slots_9.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[9].wakeup_ports[3].bits.uop.fu_code[5] connect slots_9.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[9].wakeup_ports[3].bits.uop.fu_code[6] connect slots_9.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[9].wakeup_ports[3].bits.uop.fu_code[7] connect slots_9.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[9].wakeup_ports[3].bits.uop.fu_code[8] connect slots_9.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[9].wakeup_ports[3].bits.uop.fu_code[9] connect slots_9.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[9].wakeup_ports[3].bits.uop.iq_type[0] connect slots_9.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[9].wakeup_ports[3].bits.uop.iq_type[1] connect slots_9.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[9].wakeup_ports[3].bits.uop.iq_type[2] connect slots_9.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[9].wakeup_ports[3].bits.uop.iq_type[3] connect slots_9.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[9].wakeup_ports[3].bits.uop.debug_pc connect slots_9.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[9].wakeup_ports[3].bits.uop.is_rvc connect slots_9.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[9].wakeup_ports[3].bits.uop.debug_inst connect slots_9.io.wakeup_ports[3].bits.uop.inst, issue_slots[9].wakeup_ports[3].bits.uop.inst connect slots_9.io.wakeup_ports[3].valid, issue_slots[9].wakeup_ports[3].valid connect slots_9.io.wakeup_ports[4].bits.rebusy, issue_slots[9].wakeup_ports[4].bits.rebusy connect slots_9.io.wakeup_ports[4].bits.speculative_mask, issue_slots[9].wakeup_ports[4].bits.speculative_mask connect slots_9.io.wakeup_ports[4].bits.bypassable, issue_slots[9].wakeup_ports[4].bits.bypassable connect slots_9.io.wakeup_ports[4].bits.uop.debug_tsrc, issue_slots[9].wakeup_ports[4].bits.uop.debug_tsrc connect slots_9.io.wakeup_ports[4].bits.uop.debug_fsrc, issue_slots[9].wakeup_ports[4].bits.uop.debug_fsrc connect slots_9.io.wakeup_ports[4].bits.uop.bp_xcpt_if, issue_slots[9].wakeup_ports[4].bits.uop.bp_xcpt_if connect slots_9.io.wakeup_ports[4].bits.uop.bp_debug_if, issue_slots[9].wakeup_ports[4].bits.uop.bp_debug_if connect slots_9.io.wakeup_ports[4].bits.uop.xcpt_ma_if, issue_slots[9].wakeup_ports[4].bits.uop.xcpt_ma_if connect slots_9.io.wakeup_ports[4].bits.uop.xcpt_ae_if, issue_slots[9].wakeup_ports[4].bits.uop.xcpt_ae_if connect slots_9.io.wakeup_ports[4].bits.uop.xcpt_pf_if, issue_slots[9].wakeup_ports[4].bits.uop.xcpt_pf_if connect slots_9.io.wakeup_ports[4].bits.uop.fp_typ, issue_slots[9].wakeup_ports[4].bits.uop.fp_typ connect slots_9.io.wakeup_ports[4].bits.uop.fp_rm, issue_slots[9].wakeup_ports[4].bits.uop.fp_rm connect slots_9.io.wakeup_ports[4].bits.uop.fp_val, issue_slots[9].wakeup_ports[4].bits.uop.fp_val connect slots_9.io.wakeup_ports[4].bits.uop.fcn_op, issue_slots[9].wakeup_ports[4].bits.uop.fcn_op connect slots_9.io.wakeup_ports[4].bits.uop.fcn_dw, issue_slots[9].wakeup_ports[4].bits.uop.fcn_dw connect slots_9.io.wakeup_ports[4].bits.uop.frs3_en, issue_slots[9].wakeup_ports[4].bits.uop.frs3_en connect slots_9.io.wakeup_ports[4].bits.uop.lrs2_rtype, issue_slots[9].wakeup_ports[4].bits.uop.lrs2_rtype connect slots_9.io.wakeup_ports[4].bits.uop.lrs1_rtype, issue_slots[9].wakeup_ports[4].bits.uop.lrs1_rtype connect slots_9.io.wakeup_ports[4].bits.uop.dst_rtype, issue_slots[9].wakeup_ports[4].bits.uop.dst_rtype connect slots_9.io.wakeup_ports[4].bits.uop.lrs3, issue_slots[9].wakeup_ports[4].bits.uop.lrs3 connect slots_9.io.wakeup_ports[4].bits.uop.lrs2, issue_slots[9].wakeup_ports[4].bits.uop.lrs2 connect slots_9.io.wakeup_ports[4].bits.uop.lrs1, issue_slots[9].wakeup_ports[4].bits.uop.lrs1 connect slots_9.io.wakeup_ports[4].bits.uop.ldst, issue_slots[9].wakeup_ports[4].bits.uop.ldst connect slots_9.io.wakeup_ports[4].bits.uop.ldst_is_rs1, issue_slots[9].wakeup_ports[4].bits.uop.ldst_is_rs1 connect slots_9.io.wakeup_ports[4].bits.uop.csr_cmd, issue_slots[9].wakeup_ports[4].bits.uop.csr_cmd connect slots_9.io.wakeup_ports[4].bits.uop.flush_on_commit, issue_slots[9].wakeup_ports[4].bits.uop.flush_on_commit connect slots_9.io.wakeup_ports[4].bits.uop.is_unique, issue_slots[9].wakeup_ports[4].bits.uop.is_unique connect slots_9.io.wakeup_ports[4].bits.uop.uses_stq, issue_slots[9].wakeup_ports[4].bits.uop.uses_stq connect slots_9.io.wakeup_ports[4].bits.uop.uses_ldq, issue_slots[9].wakeup_ports[4].bits.uop.uses_ldq connect slots_9.io.wakeup_ports[4].bits.uop.mem_signed, issue_slots[9].wakeup_ports[4].bits.uop.mem_signed connect slots_9.io.wakeup_ports[4].bits.uop.mem_size, issue_slots[9].wakeup_ports[4].bits.uop.mem_size connect slots_9.io.wakeup_ports[4].bits.uop.mem_cmd, issue_slots[9].wakeup_ports[4].bits.uop.mem_cmd connect slots_9.io.wakeup_ports[4].bits.uop.exc_cause, issue_slots[9].wakeup_ports[4].bits.uop.exc_cause connect slots_9.io.wakeup_ports[4].bits.uop.exception, issue_slots[9].wakeup_ports[4].bits.uop.exception connect slots_9.io.wakeup_ports[4].bits.uop.stale_pdst, issue_slots[9].wakeup_ports[4].bits.uop.stale_pdst connect slots_9.io.wakeup_ports[4].bits.uop.ppred_busy, issue_slots[9].wakeup_ports[4].bits.uop.ppred_busy connect slots_9.io.wakeup_ports[4].bits.uop.prs3_busy, issue_slots[9].wakeup_ports[4].bits.uop.prs3_busy connect slots_9.io.wakeup_ports[4].bits.uop.prs2_busy, issue_slots[9].wakeup_ports[4].bits.uop.prs2_busy connect slots_9.io.wakeup_ports[4].bits.uop.prs1_busy, issue_slots[9].wakeup_ports[4].bits.uop.prs1_busy connect slots_9.io.wakeup_ports[4].bits.uop.ppred, issue_slots[9].wakeup_ports[4].bits.uop.ppred connect slots_9.io.wakeup_ports[4].bits.uop.prs3, issue_slots[9].wakeup_ports[4].bits.uop.prs3 connect slots_9.io.wakeup_ports[4].bits.uop.prs2, issue_slots[9].wakeup_ports[4].bits.uop.prs2 connect slots_9.io.wakeup_ports[4].bits.uop.prs1, issue_slots[9].wakeup_ports[4].bits.uop.prs1 connect slots_9.io.wakeup_ports[4].bits.uop.pdst, issue_slots[9].wakeup_ports[4].bits.uop.pdst connect slots_9.io.wakeup_ports[4].bits.uop.rxq_idx, issue_slots[9].wakeup_ports[4].bits.uop.rxq_idx connect slots_9.io.wakeup_ports[4].bits.uop.stq_idx, issue_slots[9].wakeup_ports[4].bits.uop.stq_idx connect slots_9.io.wakeup_ports[4].bits.uop.ldq_idx, issue_slots[9].wakeup_ports[4].bits.uop.ldq_idx connect slots_9.io.wakeup_ports[4].bits.uop.rob_idx, issue_slots[9].wakeup_ports[4].bits.uop.rob_idx connect slots_9.io.wakeup_ports[4].bits.uop.fp_ctrl.vec, issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.vec connect slots_9.io.wakeup_ports[4].bits.uop.fp_ctrl.wflags, issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.wflags connect slots_9.io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt, issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect slots_9.io.wakeup_ports[4].bits.uop.fp_ctrl.div, issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.div connect slots_9.io.wakeup_ports[4].bits.uop.fp_ctrl.fma, issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.fma connect slots_9.io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect slots_9.io.wakeup_ports[4].bits.uop.fp_ctrl.toint, issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.toint connect slots_9.io.wakeup_ports[4].bits.uop.fp_ctrl.fromint, issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.fromint connect slots_9.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect slots_9.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect slots_9.io.wakeup_ports[4].bits.uop.fp_ctrl.swap23, issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect slots_9.io.wakeup_ports[4].bits.uop.fp_ctrl.swap12, issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect slots_9.io.wakeup_ports[4].bits.uop.fp_ctrl.ren3, issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect slots_9.io.wakeup_ports[4].bits.uop.fp_ctrl.ren2, issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect slots_9.io.wakeup_ports[4].bits.uop.fp_ctrl.ren1, issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect slots_9.io.wakeup_ports[4].bits.uop.fp_ctrl.wen, issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.wen connect slots_9.io.wakeup_ports[4].bits.uop.fp_ctrl.ldst, issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.ldst connect slots_9.io.wakeup_ports[4].bits.uop.op2_sel, issue_slots[9].wakeup_ports[4].bits.uop.op2_sel connect slots_9.io.wakeup_ports[4].bits.uop.op1_sel, issue_slots[9].wakeup_ports[4].bits.uop.op1_sel connect slots_9.io.wakeup_ports[4].bits.uop.imm_packed, issue_slots[9].wakeup_ports[4].bits.uop.imm_packed connect slots_9.io.wakeup_ports[4].bits.uop.pimm, issue_slots[9].wakeup_ports[4].bits.uop.pimm connect slots_9.io.wakeup_ports[4].bits.uop.imm_sel, issue_slots[9].wakeup_ports[4].bits.uop.imm_sel connect slots_9.io.wakeup_ports[4].bits.uop.imm_rename, issue_slots[9].wakeup_ports[4].bits.uop.imm_rename connect slots_9.io.wakeup_ports[4].bits.uop.taken, issue_slots[9].wakeup_ports[4].bits.uop.taken connect slots_9.io.wakeup_ports[4].bits.uop.pc_lob, issue_slots[9].wakeup_ports[4].bits.uop.pc_lob connect slots_9.io.wakeup_ports[4].bits.uop.edge_inst, issue_slots[9].wakeup_ports[4].bits.uop.edge_inst connect slots_9.io.wakeup_ports[4].bits.uop.ftq_idx, issue_slots[9].wakeup_ports[4].bits.uop.ftq_idx connect slots_9.io.wakeup_ports[4].bits.uop.is_mov, issue_slots[9].wakeup_ports[4].bits.uop.is_mov connect slots_9.io.wakeup_ports[4].bits.uop.is_rocc, issue_slots[9].wakeup_ports[4].bits.uop.is_rocc connect slots_9.io.wakeup_ports[4].bits.uop.is_sys_pc2epc, issue_slots[9].wakeup_ports[4].bits.uop.is_sys_pc2epc connect slots_9.io.wakeup_ports[4].bits.uop.is_eret, issue_slots[9].wakeup_ports[4].bits.uop.is_eret connect slots_9.io.wakeup_ports[4].bits.uop.is_amo, issue_slots[9].wakeup_ports[4].bits.uop.is_amo connect slots_9.io.wakeup_ports[4].bits.uop.is_sfence, issue_slots[9].wakeup_ports[4].bits.uop.is_sfence connect slots_9.io.wakeup_ports[4].bits.uop.is_fencei, issue_slots[9].wakeup_ports[4].bits.uop.is_fencei connect slots_9.io.wakeup_ports[4].bits.uop.is_fence, issue_slots[9].wakeup_ports[4].bits.uop.is_fence connect slots_9.io.wakeup_ports[4].bits.uop.is_sfb, issue_slots[9].wakeup_ports[4].bits.uop.is_sfb connect slots_9.io.wakeup_ports[4].bits.uop.br_type, issue_slots[9].wakeup_ports[4].bits.uop.br_type connect slots_9.io.wakeup_ports[4].bits.uop.br_tag, issue_slots[9].wakeup_ports[4].bits.uop.br_tag connect slots_9.io.wakeup_ports[4].bits.uop.br_mask, issue_slots[9].wakeup_ports[4].bits.uop.br_mask connect slots_9.io.wakeup_ports[4].bits.uop.dis_col_sel, issue_slots[9].wakeup_ports[4].bits.uop.dis_col_sel connect slots_9.io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint, issue_slots[9].wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect slots_9.io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint, issue_slots[9].wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect slots_9.io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint, issue_slots[9].wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect slots_9.io.wakeup_ports[4].bits.uop.iw_p2_speculative_child, issue_slots[9].wakeup_ports[4].bits.uop.iw_p2_speculative_child connect slots_9.io.wakeup_ports[4].bits.uop.iw_p1_speculative_child, issue_slots[9].wakeup_ports[4].bits.uop.iw_p1_speculative_child connect slots_9.io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen, issue_slots[9].wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect slots_9.io.wakeup_ports[4].bits.uop.iw_issued_partial_agen, issue_slots[9].wakeup_ports[4].bits.uop.iw_issued_partial_agen connect slots_9.io.wakeup_ports[4].bits.uop.iw_issued, issue_slots[9].wakeup_ports[4].bits.uop.iw_issued connect slots_9.io.wakeup_ports[4].bits.uop.fu_code[0], issue_slots[9].wakeup_ports[4].bits.uop.fu_code[0] connect slots_9.io.wakeup_ports[4].bits.uop.fu_code[1], issue_slots[9].wakeup_ports[4].bits.uop.fu_code[1] connect slots_9.io.wakeup_ports[4].bits.uop.fu_code[2], issue_slots[9].wakeup_ports[4].bits.uop.fu_code[2] connect slots_9.io.wakeup_ports[4].bits.uop.fu_code[3], issue_slots[9].wakeup_ports[4].bits.uop.fu_code[3] connect slots_9.io.wakeup_ports[4].bits.uop.fu_code[4], issue_slots[9].wakeup_ports[4].bits.uop.fu_code[4] connect slots_9.io.wakeup_ports[4].bits.uop.fu_code[5], issue_slots[9].wakeup_ports[4].bits.uop.fu_code[5] connect slots_9.io.wakeup_ports[4].bits.uop.fu_code[6], issue_slots[9].wakeup_ports[4].bits.uop.fu_code[6] connect slots_9.io.wakeup_ports[4].bits.uop.fu_code[7], issue_slots[9].wakeup_ports[4].bits.uop.fu_code[7] connect slots_9.io.wakeup_ports[4].bits.uop.fu_code[8], issue_slots[9].wakeup_ports[4].bits.uop.fu_code[8] connect slots_9.io.wakeup_ports[4].bits.uop.fu_code[9], issue_slots[9].wakeup_ports[4].bits.uop.fu_code[9] connect slots_9.io.wakeup_ports[4].bits.uop.iq_type[0], issue_slots[9].wakeup_ports[4].bits.uop.iq_type[0] connect slots_9.io.wakeup_ports[4].bits.uop.iq_type[1], issue_slots[9].wakeup_ports[4].bits.uop.iq_type[1] connect slots_9.io.wakeup_ports[4].bits.uop.iq_type[2], issue_slots[9].wakeup_ports[4].bits.uop.iq_type[2] connect slots_9.io.wakeup_ports[4].bits.uop.iq_type[3], issue_slots[9].wakeup_ports[4].bits.uop.iq_type[3] connect slots_9.io.wakeup_ports[4].bits.uop.debug_pc, issue_slots[9].wakeup_ports[4].bits.uop.debug_pc connect slots_9.io.wakeup_ports[4].bits.uop.is_rvc, issue_slots[9].wakeup_ports[4].bits.uop.is_rvc connect slots_9.io.wakeup_ports[4].bits.uop.debug_inst, issue_slots[9].wakeup_ports[4].bits.uop.debug_inst connect slots_9.io.wakeup_ports[4].bits.uop.inst, issue_slots[9].wakeup_ports[4].bits.uop.inst connect slots_9.io.wakeup_ports[4].valid, issue_slots[9].wakeup_ports[4].valid connect slots_9.io.squash_grant, issue_slots[9].squash_grant connect slots_9.io.clear, issue_slots[9].clear connect slots_9.io.kill, issue_slots[9].kill connect slots_9.io.brupdate.b2.target_offset, issue_slots[9].brupdate.b2.target_offset connect slots_9.io.brupdate.b2.jalr_target, issue_slots[9].brupdate.b2.jalr_target connect slots_9.io.brupdate.b2.pc_sel, issue_slots[9].brupdate.b2.pc_sel connect slots_9.io.brupdate.b2.cfi_type, issue_slots[9].brupdate.b2.cfi_type connect slots_9.io.brupdate.b2.taken, issue_slots[9].brupdate.b2.taken connect slots_9.io.brupdate.b2.mispredict, issue_slots[9].brupdate.b2.mispredict connect slots_9.io.brupdate.b2.uop.debug_tsrc, issue_slots[9].brupdate.b2.uop.debug_tsrc connect slots_9.io.brupdate.b2.uop.debug_fsrc, issue_slots[9].brupdate.b2.uop.debug_fsrc connect slots_9.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[9].brupdate.b2.uop.bp_xcpt_if connect slots_9.io.brupdate.b2.uop.bp_debug_if, issue_slots[9].brupdate.b2.uop.bp_debug_if connect slots_9.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[9].brupdate.b2.uop.xcpt_ma_if connect slots_9.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[9].brupdate.b2.uop.xcpt_ae_if connect slots_9.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[9].brupdate.b2.uop.xcpt_pf_if connect slots_9.io.brupdate.b2.uop.fp_typ, issue_slots[9].brupdate.b2.uop.fp_typ connect slots_9.io.brupdate.b2.uop.fp_rm, issue_slots[9].brupdate.b2.uop.fp_rm connect slots_9.io.brupdate.b2.uop.fp_val, issue_slots[9].brupdate.b2.uop.fp_val connect slots_9.io.brupdate.b2.uop.fcn_op, issue_slots[9].brupdate.b2.uop.fcn_op connect slots_9.io.brupdate.b2.uop.fcn_dw, issue_slots[9].brupdate.b2.uop.fcn_dw connect slots_9.io.brupdate.b2.uop.frs3_en, issue_slots[9].brupdate.b2.uop.frs3_en connect slots_9.io.brupdate.b2.uop.lrs2_rtype, issue_slots[9].brupdate.b2.uop.lrs2_rtype connect slots_9.io.brupdate.b2.uop.lrs1_rtype, issue_slots[9].brupdate.b2.uop.lrs1_rtype connect slots_9.io.brupdate.b2.uop.dst_rtype, issue_slots[9].brupdate.b2.uop.dst_rtype connect slots_9.io.brupdate.b2.uop.lrs3, issue_slots[9].brupdate.b2.uop.lrs3 connect slots_9.io.brupdate.b2.uop.lrs2, issue_slots[9].brupdate.b2.uop.lrs2 connect slots_9.io.brupdate.b2.uop.lrs1, issue_slots[9].brupdate.b2.uop.lrs1 connect slots_9.io.brupdate.b2.uop.ldst, issue_slots[9].brupdate.b2.uop.ldst connect slots_9.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[9].brupdate.b2.uop.ldst_is_rs1 connect slots_9.io.brupdate.b2.uop.csr_cmd, issue_slots[9].brupdate.b2.uop.csr_cmd connect slots_9.io.brupdate.b2.uop.flush_on_commit, issue_slots[9].brupdate.b2.uop.flush_on_commit connect slots_9.io.brupdate.b2.uop.is_unique, issue_slots[9].brupdate.b2.uop.is_unique connect slots_9.io.brupdate.b2.uop.uses_stq, issue_slots[9].brupdate.b2.uop.uses_stq connect slots_9.io.brupdate.b2.uop.uses_ldq, issue_slots[9].brupdate.b2.uop.uses_ldq connect slots_9.io.brupdate.b2.uop.mem_signed, issue_slots[9].brupdate.b2.uop.mem_signed connect slots_9.io.brupdate.b2.uop.mem_size, issue_slots[9].brupdate.b2.uop.mem_size connect slots_9.io.brupdate.b2.uop.mem_cmd, issue_slots[9].brupdate.b2.uop.mem_cmd connect slots_9.io.brupdate.b2.uop.exc_cause, issue_slots[9].brupdate.b2.uop.exc_cause connect slots_9.io.brupdate.b2.uop.exception, issue_slots[9].brupdate.b2.uop.exception connect slots_9.io.brupdate.b2.uop.stale_pdst, issue_slots[9].brupdate.b2.uop.stale_pdst connect slots_9.io.brupdate.b2.uop.ppred_busy, issue_slots[9].brupdate.b2.uop.ppred_busy connect slots_9.io.brupdate.b2.uop.prs3_busy, issue_slots[9].brupdate.b2.uop.prs3_busy connect slots_9.io.brupdate.b2.uop.prs2_busy, issue_slots[9].brupdate.b2.uop.prs2_busy connect slots_9.io.brupdate.b2.uop.prs1_busy, issue_slots[9].brupdate.b2.uop.prs1_busy connect slots_9.io.brupdate.b2.uop.ppred, issue_slots[9].brupdate.b2.uop.ppred connect slots_9.io.brupdate.b2.uop.prs3, issue_slots[9].brupdate.b2.uop.prs3 connect slots_9.io.brupdate.b2.uop.prs2, issue_slots[9].brupdate.b2.uop.prs2 connect slots_9.io.brupdate.b2.uop.prs1, issue_slots[9].brupdate.b2.uop.prs1 connect slots_9.io.brupdate.b2.uop.pdst, issue_slots[9].brupdate.b2.uop.pdst connect slots_9.io.brupdate.b2.uop.rxq_idx, issue_slots[9].brupdate.b2.uop.rxq_idx connect slots_9.io.brupdate.b2.uop.stq_idx, issue_slots[9].brupdate.b2.uop.stq_idx connect slots_9.io.brupdate.b2.uop.ldq_idx, issue_slots[9].brupdate.b2.uop.ldq_idx connect slots_9.io.brupdate.b2.uop.rob_idx, issue_slots[9].brupdate.b2.uop.rob_idx connect slots_9.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[9].brupdate.b2.uop.fp_ctrl.vec connect slots_9.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[9].brupdate.b2.uop.fp_ctrl.wflags connect slots_9.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[9].brupdate.b2.uop.fp_ctrl.sqrt connect slots_9.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[9].brupdate.b2.uop.fp_ctrl.div connect slots_9.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[9].brupdate.b2.uop.fp_ctrl.fma connect slots_9.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[9].brupdate.b2.uop.fp_ctrl.fastpipe connect slots_9.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[9].brupdate.b2.uop.fp_ctrl.toint connect slots_9.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[9].brupdate.b2.uop.fp_ctrl.fromint connect slots_9.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[9].brupdate.b2.uop.fp_ctrl.typeTagOut connect slots_9.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[9].brupdate.b2.uop.fp_ctrl.typeTagIn connect slots_9.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[9].brupdate.b2.uop.fp_ctrl.swap23 connect slots_9.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[9].brupdate.b2.uop.fp_ctrl.swap12 connect slots_9.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[9].brupdate.b2.uop.fp_ctrl.ren3 connect slots_9.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[9].brupdate.b2.uop.fp_ctrl.ren2 connect slots_9.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[9].brupdate.b2.uop.fp_ctrl.ren1 connect slots_9.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[9].brupdate.b2.uop.fp_ctrl.wen connect slots_9.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[9].brupdate.b2.uop.fp_ctrl.ldst connect slots_9.io.brupdate.b2.uop.op2_sel, issue_slots[9].brupdate.b2.uop.op2_sel connect slots_9.io.brupdate.b2.uop.op1_sel, issue_slots[9].brupdate.b2.uop.op1_sel connect slots_9.io.brupdate.b2.uop.imm_packed, issue_slots[9].brupdate.b2.uop.imm_packed connect slots_9.io.brupdate.b2.uop.pimm, issue_slots[9].brupdate.b2.uop.pimm connect slots_9.io.brupdate.b2.uop.imm_sel, issue_slots[9].brupdate.b2.uop.imm_sel connect slots_9.io.brupdate.b2.uop.imm_rename, issue_slots[9].brupdate.b2.uop.imm_rename connect slots_9.io.brupdate.b2.uop.taken, issue_slots[9].brupdate.b2.uop.taken connect slots_9.io.brupdate.b2.uop.pc_lob, issue_slots[9].brupdate.b2.uop.pc_lob connect slots_9.io.brupdate.b2.uop.edge_inst, issue_slots[9].brupdate.b2.uop.edge_inst connect slots_9.io.brupdate.b2.uop.ftq_idx, issue_slots[9].brupdate.b2.uop.ftq_idx connect slots_9.io.brupdate.b2.uop.is_mov, issue_slots[9].brupdate.b2.uop.is_mov connect slots_9.io.brupdate.b2.uop.is_rocc, issue_slots[9].brupdate.b2.uop.is_rocc connect slots_9.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[9].brupdate.b2.uop.is_sys_pc2epc connect slots_9.io.brupdate.b2.uop.is_eret, issue_slots[9].brupdate.b2.uop.is_eret connect slots_9.io.brupdate.b2.uop.is_amo, issue_slots[9].brupdate.b2.uop.is_amo connect slots_9.io.brupdate.b2.uop.is_sfence, issue_slots[9].brupdate.b2.uop.is_sfence connect slots_9.io.brupdate.b2.uop.is_fencei, issue_slots[9].brupdate.b2.uop.is_fencei connect slots_9.io.brupdate.b2.uop.is_fence, issue_slots[9].brupdate.b2.uop.is_fence connect slots_9.io.brupdate.b2.uop.is_sfb, issue_slots[9].brupdate.b2.uop.is_sfb connect slots_9.io.brupdate.b2.uop.br_type, issue_slots[9].brupdate.b2.uop.br_type connect slots_9.io.brupdate.b2.uop.br_tag, issue_slots[9].brupdate.b2.uop.br_tag connect slots_9.io.brupdate.b2.uop.br_mask, issue_slots[9].brupdate.b2.uop.br_mask connect slots_9.io.brupdate.b2.uop.dis_col_sel, issue_slots[9].brupdate.b2.uop.dis_col_sel connect slots_9.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[9].brupdate.b2.uop.iw_p3_bypass_hint connect slots_9.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[9].brupdate.b2.uop.iw_p2_bypass_hint connect slots_9.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[9].brupdate.b2.uop.iw_p1_bypass_hint connect slots_9.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[9].brupdate.b2.uop.iw_p2_speculative_child connect slots_9.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[9].brupdate.b2.uop.iw_p1_speculative_child connect slots_9.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[9].brupdate.b2.uop.iw_issued_partial_dgen connect slots_9.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[9].brupdate.b2.uop.iw_issued_partial_agen connect slots_9.io.brupdate.b2.uop.iw_issued, issue_slots[9].brupdate.b2.uop.iw_issued connect slots_9.io.brupdate.b2.uop.fu_code[0], issue_slots[9].brupdate.b2.uop.fu_code[0] connect slots_9.io.brupdate.b2.uop.fu_code[1], issue_slots[9].brupdate.b2.uop.fu_code[1] connect slots_9.io.brupdate.b2.uop.fu_code[2], issue_slots[9].brupdate.b2.uop.fu_code[2] connect slots_9.io.brupdate.b2.uop.fu_code[3], issue_slots[9].brupdate.b2.uop.fu_code[3] connect slots_9.io.brupdate.b2.uop.fu_code[4], issue_slots[9].brupdate.b2.uop.fu_code[4] connect slots_9.io.brupdate.b2.uop.fu_code[5], issue_slots[9].brupdate.b2.uop.fu_code[5] connect slots_9.io.brupdate.b2.uop.fu_code[6], issue_slots[9].brupdate.b2.uop.fu_code[6] connect slots_9.io.brupdate.b2.uop.fu_code[7], issue_slots[9].brupdate.b2.uop.fu_code[7] connect slots_9.io.brupdate.b2.uop.fu_code[8], issue_slots[9].brupdate.b2.uop.fu_code[8] connect slots_9.io.brupdate.b2.uop.fu_code[9], issue_slots[9].brupdate.b2.uop.fu_code[9] connect slots_9.io.brupdate.b2.uop.iq_type[0], issue_slots[9].brupdate.b2.uop.iq_type[0] connect slots_9.io.brupdate.b2.uop.iq_type[1], issue_slots[9].brupdate.b2.uop.iq_type[1] connect slots_9.io.brupdate.b2.uop.iq_type[2], issue_slots[9].brupdate.b2.uop.iq_type[2] connect slots_9.io.brupdate.b2.uop.iq_type[3], issue_slots[9].brupdate.b2.uop.iq_type[3] connect slots_9.io.brupdate.b2.uop.debug_pc, issue_slots[9].brupdate.b2.uop.debug_pc connect slots_9.io.brupdate.b2.uop.is_rvc, issue_slots[9].brupdate.b2.uop.is_rvc connect slots_9.io.brupdate.b2.uop.debug_inst, issue_slots[9].brupdate.b2.uop.debug_inst connect slots_9.io.brupdate.b2.uop.inst, issue_slots[9].brupdate.b2.uop.inst connect slots_9.io.brupdate.b1.mispredict_mask, issue_slots[9].brupdate.b1.mispredict_mask connect slots_9.io.brupdate.b1.resolve_mask, issue_slots[9].brupdate.b1.resolve_mask connect issue_slots[9].out_uop.debug_tsrc, slots_9.io.out_uop.debug_tsrc connect issue_slots[9].out_uop.debug_fsrc, slots_9.io.out_uop.debug_fsrc connect issue_slots[9].out_uop.bp_xcpt_if, slots_9.io.out_uop.bp_xcpt_if connect issue_slots[9].out_uop.bp_debug_if, slots_9.io.out_uop.bp_debug_if connect issue_slots[9].out_uop.xcpt_ma_if, slots_9.io.out_uop.xcpt_ma_if connect issue_slots[9].out_uop.xcpt_ae_if, slots_9.io.out_uop.xcpt_ae_if connect issue_slots[9].out_uop.xcpt_pf_if, slots_9.io.out_uop.xcpt_pf_if connect issue_slots[9].out_uop.fp_typ, slots_9.io.out_uop.fp_typ connect issue_slots[9].out_uop.fp_rm, slots_9.io.out_uop.fp_rm connect issue_slots[9].out_uop.fp_val, slots_9.io.out_uop.fp_val connect issue_slots[9].out_uop.fcn_op, slots_9.io.out_uop.fcn_op connect issue_slots[9].out_uop.fcn_dw, slots_9.io.out_uop.fcn_dw connect issue_slots[9].out_uop.frs3_en, slots_9.io.out_uop.frs3_en connect issue_slots[9].out_uop.lrs2_rtype, slots_9.io.out_uop.lrs2_rtype connect issue_slots[9].out_uop.lrs1_rtype, slots_9.io.out_uop.lrs1_rtype connect issue_slots[9].out_uop.dst_rtype, slots_9.io.out_uop.dst_rtype connect issue_slots[9].out_uop.lrs3, slots_9.io.out_uop.lrs3 connect issue_slots[9].out_uop.lrs2, slots_9.io.out_uop.lrs2 connect issue_slots[9].out_uop.lrs1, slots_9.io.out_uop.lrs1 connect issue_slots[9].out_uop.ldst, slots_9.io.out_uop.ldst connect issue_slots[9].out_uop.ldst_is_rs1, slots_9.io.out_uop.ldst_is_rs1 connect issue_slots[9].out_uop.csr_cmd, slots_9.io.out_uop.csr_cmd connect issue_slots[9].out_uop.flush_on_commit, slots_9.io.out_uop.flush_on_commit connect issue_slots[9].out_uop.is_unique, slots_9.io.out_uop.is_unique connect issue_slots[9].out_uop.uses_stq, slots_9.io.out_uop.uses_stq connect issue_slots[9].out_uop.uses_ldq, slots_9.io.out_uop.uses_ldq connect issue_slots[9].out_uop.mem_signed, slots_9.io.out_uop.mem_signed connect issue_slots[9].out_uop.mem_size, slots_9.io.out_uop.mem_size connect issue_slots[9].out_uop.mem_cmd, slots_9.io.out_uop.mem_cmd connect issue_slots[9].out_uop.exc_cause, slots_9.io.out_uop.exc_cause connect issue_slots[9].out_uop.exception, slots_9.io.out_uop.exception connect issue_slots[9].out_uop.stale_pdst, slots_9.io.out_uop.stale_pdst connect issue_slots[9].out_uop.ppred_busy, slots_9.io.out_uop.ppred_busy connect issue_slots[9].out_uop.prs3_busy, slots_9.io.out_uop.prs3_busy connect issue_slots[9].out_uop.prs2_busy, slots_9.io.out_uop.prs2_busy connect issue_slots[9].out_uop.prs1_busy, slots_9.io.out_uop.prs1_busy connect issue_slots[9].out_uop.ppred, slots_9.io.out_uop.ppred connect issue_slots[9].out_uop.prs3, slots_9.io.out_uop.prs3 connect issue_slots[9].out_uop.prs2, slots_9.io.out_uop.prs2 connect issue_slots[9].out_uop.prs1, slots_9.io.out_uop.prs1 connect issue_slots[9].out_uop.pdst, slots_9.io.out_uop.pdst connect issue_slots[9].out_uop.rxq_idx, slots_9.io.out_uop.rxq_idx connect issue_slots[9].out_uop.stq_idx, slots_9.io.out_uop.stq_idx connect issue_slots[9].out_uop.ldq_idx, slots_9.io.out_uop.ldq_idx connect issue_slots[9].out_uop.rob_idx, slots_9.io.out_uop.rob_idx connect issue_slots[9].out_uop.fp_ctrl.vec, slots_9.io.out_uop.fp_ctrl.vec connect issue_slots[9].out_uop.fp_ctrl.wflags, slots_9.io.out_uop.fp_ctrl.wflags connect issue_slots[9].out_uop.fp_ctrl.sqrt, slots_9.io.out_uop.fp_ctrl.sqrt connect issue_slots[9].out_uop.fp_ctrl.div, slots_9.io.out_uop.fp_ctrl.div connect issue_slots[9].out_uop.fp_ctrl.fma, slots_9.io.out_uop.fp_ctrl.fma connect issue_slots[9].out_uop.fp_ctrl.fastpipe, slots_9.io.out_uop.fp_ctrl.fastpipe connect issue_slots[9].out_uop.fp_ctrl.toint, slots_9.io.out_uop.fp_ctrl.toint connect issue_slots[9].out_uop.fp_ctrl.fromint, slots_9.io.out_uop.fp_ctrl.fromint connect issue_slots[9].out_uop.fp_ctrl.typeTagOut, slots_9.io.out_uop.fp_ctrl.typeTagOut connect issue_slots[9].out_uop.fp_ctrl.typeTagIn, slots_9.io.out_uop.fp_ctrl.typeTagIn connect issue_slots[9].out_uop.fp_ctrl.swap23, slots_9.io.out_uop.fp_ctrl.swap23 connect issue_slots[9].out_uop.fp_ctrl.swap12, slots_9.io.out_uop.fp_ctrl.swap12 connect issue_slots[9].out_uop.fp_ctrl.ren3, slots_9.io.out_uop.fp_ctrl.ren3 connect issue_slots[9].out_uop.fp_ctrl.ren2, slots_9.io.out_uop.fp_ctrl.ren2 connect issue_slots[9].out_uop.fp_ctrl.ren1, slots_9.io.out_uop.fp_ctrl.ren1 connect issue_slots[9].out_uop.fp_ctrl.wen, slots_9.io.out_uop.fp_ctrl.wen connect issue_slots[9].out_uop.fp_ctrl.ldst, slots_9.io.out_uop.fp_ctrl.ldst connect issue_slots[9].out_uop.op2_sel, slots_9.io.out_uop.op2_sel connect issue_slots[9].out_uop.op1_sel, slots_9.io.out_uop.op1_sel connect issue_slots[9].out_uop.imm_packed, slots_9.io.out_uop.imm_packed connect issue_slots[9].out_uop.pimm, slots_9.io.out_uop.pimm connect issue_slots[9].out_uop.imm_sel, slots_9.io.out_uop.imm_sel connect issue_slots[9].out_uop.imm_rename, slots_9.io.out_uop.imm_rename connect issue_slots[9].out_uop.taken, slots_9.io.out_uop.taken connect issue_slots[9].out_uop.pc_lob, slots_9.io.out_uop.pc_lob connect issue_slots[9].out_uop.edge_inst, slots_9.io.out_uop.edge_inst connect issue_slots[9].out_uop.ftq_idx, slots_9.io.out_uop.ftq_idx connect issue_slots[9].out_uop.is_mov, slots_9.io.out_uop.is_mov connect issue_slots[9].out_uop.is_rocc, slots_9.io.out_uop.is_rocc connect issue_slots[9].out_uop.is_sys_pc2epc, slots_9.io.out_uop.is_sys_pc2epc connect issue_slots[9].out_uop.is_eret, slots_9.io.out_uop.is_eret connect issue_slots[9].out_uop.is_amo, slots_9.io.out_uop.is_amo connect issue_slots[9].out_uop.is_sfence, slots_9.io.out_uop.is_sfence connect issue_slots[9].out_uop.is_fencei, slots_9.io.out_uop.is_fencei connect issue_slots[9].out_uop.is_fence, slots_9.io.out_uop.is_fence connect issue_slots[9].out_uop.is_sfb, slots_9.io.out_uop.is_sfb connect issue_slots[9].out_uop.br_type, slots_9.io.out_uop.br_type connect issue_slots[9].out_uop.br_tag, slots_9.io.out_uop.br_tag connect issue_slots[9].out_uop.br_mask, slots_9.io.out_uop.br_mask connect issue_slots[9].out_uop.dis_col_sel, slots_9.io.out_uop.dis_col_sel connect issue_slots[9].out_uop.iw_p3_bypass_hint, slots_9.io.out_uop.iw_p3_bypass_hint connect issue_slots[9].out_uop.iw_p2_bypass_hint, slots_9.io.out_uop.iw_p2_bypass_hint connect issue_slots[9].out_uop.iw_p1_bypass_hint, slots_9.io.out_uop.iw_p1_bypass_hint connect issue_slots[9].out_uop.iw_p2_speculative_child, slots_9.io.out_uop.iw_p2_speculative_child connect issue_slots[9].out_uop.iw_p1_speculative_child, slots_9.io.out_uop.iw_p1_speculative_child connect issue_slots[9].out_uop.iw_issued_partial_dgen, slots_9.io.out_uop.iw_issued_partial_dgen connect issue_slots[9].out_uop.iw_issued_partial_agen, slots_9.io.out_uop.iw_issued_partial_agen connect issue_slots[9].out_uop.iw_issued, slots_9.io.out_uop.iw_issued connect issue_slots[9].out_uop.fu_code[0], slots_9.io.out_uop.fu_code[0] connect issue_slots[9].out_uop.fu_code[1], slots_9.io.out_uop.fu_code[1] connect issue_slots[9].out_uop.fu_code[2], slots_9.io.out_uop.fu_code[2] connect issue_slots[9].out_uop.fu_code[3], slots_9.io.out_uop.fu_code[3] connect issue_slots[9].out_uop.fu_code[4], slots_9.io.out_uop.fu_code[4] connect issue_slots[9].out_uop.fu_code[5], slots_9.io.out_uop.fu_code[5] connect issue_slots[9].out_uop.fu_code[6], slots_9.io.out_uop.fu_code[6] connect issue_slots[9].out_uop.fu_code[7], slots_9.io.out_uop.fu_code[7] connect issue_slots[9].out_uop.fu_code[8], slots_9.io.out_uop.fu_code[8] connect issue_slots[9].out_uop.fu_code[9], slots_9.io.out_uop.fu_code[9] connect issue_slots[9].out_uop.iq_type[0], slots_9.io.out_uop.iq_type[0] connect issue_slots[9].out_uop.iq_type[1], slots_9.io.out_uop.iq_type[1] connect issue_slots[9].out_uop.iq_type[2], slots_9.io.out_uop.iq_type[2] connect issue_slots[9].out_uop.iq_type[3], slots_9.io.out_uop.iq_type[3] connect issue_slots[9].out_uop.debug_pc, slots_9.io.out_uop.debug_pc connect issue_slots[9].out_uop.is_rvc, slots_9.io.out_uop.is_rvc connect issue_slots[9].out_uop.debug_inst, slots_9.io.out_uop.debug_inst connect issue_slots[9].out_uop.inst, slots_9.io.out_uop.inst connect slots_9.io.in_uop.bits.debug_tsrc, issue_slots[9].in_uop.bits.debug_tsrc connect slots_9.io.in_uop.bits.debug_fsrc, issue_slots[9].in_uop.bits.debug_fsrc connect slots_9.io.in_uop.bits.bp_xcpt_if, issue_slots[9].in_uop.bits.bp_xcpt_if connect slots_9.io.in_uop.bits.bp_debug_if, issue_slots[9].in_uop.bits.bp_debug_if connect slots_9.io.in_uop.bits.xcpt_ma_if, issue_slots[9].in_uop.bits.xcpt_ma_if connect slots_9.io.in_uop.bits.xcpt_ae_if, issue_slots[9].in_uop.bits.xcpt_ae_if connect slots_9.io.in_uop.bits.xcpt_pf_if, issue_slots[9].in_uop.bits.xcpt_pf_if connect slots_9.io.in_uop.bits.fp_typ, issue_slots[9].in_uop.bits.fp_typ connect slots_9.io.in_uop.bits.fp_rm, issue_slots[9].in_uop.bits.fp_rm connect slots_9.io.in_uop.bits.fp_val, issue_slots[9].in_uop.bits.fp_val connect slots_9.io.in_uop.bits.fcn_op, issue_slots[9].in_uop.bits.fcn_op connect slots_9.io.in_uop.bits.fcn_dw, issue_slots[9].in_uop.bits.fcn_dw connect slots_9.io.in_uop.bits.frs3_en, issue_slots[9].in_uop.bits.frs3_en connect slots_9.io.in_uop.bits.lrs2_rtype, issue_slots[9].in_uop.bits.lrs2_rtype connect slots_9.io.in_uop.bits.lrs1_rtype, issue_slots[9].in_uop.bits.lrs1_rtype connect slots_9.io.in_uop.bits.dst_rtype, issue_slots[9].in_uop.bits.dst_rtype connect slots_9.io.in_uop.bits.lrs3, issue_slots[9].in_uop.bits.lrs3 connect slots_9.io.in_uop.bits.lrs2, issue_slots[9].in_uop.bits.lrs2 connect slots_9.io.in_uop.bits.lrs1, issue_slots[9].in_uop.bits.lrs1 connect slots_9.io.in_uop.bits.ldst, issue_slots[9].in_uop.bits.ldst connect slots_9.io.in_uop.bits.ldst_is_rs1, issue_slots[9].in_uop.bits.ldst_is_rs1 connect slots_9.io.in_uop.bits.csr_cmd, issue_slots[9].in_uop.bits.csr_cmd connect slots_9.io.in_uop.bits.flush_on_commit, issue_slots[9].in_uop.bits.flush_on_commit connect slots_9.io.in_uop.bits.is_unique, issue_slots[9].in_uop.bits.is_unique connect slots_9.io.in_uop.bits.uses_stq, issue_slots[9].in_uop.bits.uses_stq connect slots_9.io.in_uop.bits.uses_ldq, issue_slots[9].in_uop.bits.uses_ldq connect slots_9.io.in_uop.bits.mem_signed, issue_slots[9].in_uop.bits.mem_signed connect slots_9.io.in_uop.bits.mem_size, issue_slots[9].in_uop.bits.mem_size connect slots_9.io.in_uop.bits.mem_cmd, issue_slots[9].in_uop.bits.mem_cmd connect slots_9.io.in_uop.bits.exc_cause, issue_slots[9].in_uop.bits.exc_cause connect slots_9.io.in_uop.bits.exception, issue_slots[9].in_uop.bits.exception connect slots_9.io.in_uop.bits.stale_pdst, issue_slots[9].in_uop.bits.stale_pdst connect slots_9.io.in_uop.bits.ppred_busy, issue_slots[9].in_uop.bits.ppred_busy connect slots_9.io.in_uop.bits.prs3_busy, issue_slots[9].in_uop.bits.prs3_busy connect slots_9.io.in_uop.bits.prs2_busy, issue_slots[9].in_uop.bits.prs2_busy connect slots_9.io.in_uop.bits.prs1_busy, issue_slots[9].in_uop.bits.prs1_busy connect slots_9.io.in_uop.bits.ppred, issue_slots[9].in_uop.bits.ppred connect slots_9.io.in_uop.bits.prs3, issue_slots[9].in_uop.bits.prs3 connect slots_9.io.in_uop.bits.prs2, issue_slots[9].in_uop.bits.prs2 connect slots_9.io.in_uop.bits.prs1, issue_slots[9].in_uop.bits.prs1 connect slots_9.io.in_uop.bits.pdst, issue_slots[9].in_uop.bits.pdst connect slots_9.io.in_uop.bits.rxq_idx, issue_slots[9].in_uop.bits.rxq_idx connect slots_9.io.in_uop.bits.stq_idx, issue_slots[9].in_uop.bits.stq_idx connect slots_9.io.in_uop.bits.ldq_idx, issue_slots[9].in_uop.bits.ldq_idx connect slots_9.io.in_uop.bits.rob_idx, issue_slots[9].in_uop.bits.rob_idx connect slots_9.io.in_uop.bits.fp_ctrl.vec, issue_slots[9].in_uop.bits.fp_ctrl.vec connect slots_9.io.in_uop.bits.fp_ctrl.wflags, issue_slots[9].in_uop.bits.fp_ctrl.wflags connect slots_9.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[9].in_uop.bits.fp_ctrl.sqrt connect slots_9.io.in_uop.bits.fp_ctrl.div, issue_slots[9].in_uop.bits.fp_ctrl.div connect slots_9.io.in_uop.bits.fp_ctrl.fma, issue_slots[9].in_uop.bits.fp_ctrl.fma connect slots_9.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[9].in_uop.bits.fp_ctrl.fastpipe connect slots_9.io.in_uop.bits.fp_ctrl.toint, issue_slots[9].in_uop.bits.fp_ctrl.toint connect slots_9.io.in_uop.bits.fp_ctrl.fromint, issue_slots[9].in_uop.bits.fp_ctrl.fromint connect slots_9.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[9].in_uop.bits.fp_ctrl.typeTagOut connect slots_9.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[9].in_uop.bits.fp_ctrl.typeTagIn connect slots_9.io.in_uop.bits.fp_ctrl.swap23, issue_slots[9].in_uop.bits.fp_ctrl.swap23 connect slots_9.io.in_uop.bits.fp_ctrl.swap12, issue_slots[9].in_uop.bits.fp_ctrl.swap12 connect slots_9.io.in_uop.bits.fp_ctrl.ren3, issue_slots[9].in_uop.bits.fp_ctrl.ren3 connect slots_9.io.in_uop.bits.fp_ctrl.ren2, issue_slots[9].in_uop.bits.fp_ctrl.ren2 connect slots_9.io.in_uop.bits.fp_ctrl.ren1, issue_slots[9].in_uop.bits.fp_ctrl.ren1 connect slots_9.io.in_uop.bits.fp_ctrl.wen, issue_slots[9].in_uop.bits.fp_ctrl.wen connect slots_9.io.in_uop.bits.fp_ctrl.ldst, issue_slots[9].in_uop.bits.fp_ctrl.ldst connect slots_9.io.in_uop.bits.op2_sel, issue_slots[9].in_uop.bits.op2_sel connect slots_9.io.in_uop.bits.op1_sel, issue_slots[9].in_uop.bits.op1_sel connect slots_9.io.in_uop.bits.imm_packed, issue_slots[9].in_uop.bits.imm_packed connect slots_9.io.in_uop.bits.pimm, issue_slots[9].in_uop.bits.pimm connect slots_9.io.in_uop.bits.imm_sel, issue_slots[9].in_uop.bits.imm_sel connect slots_9.io.in_uop.bits.imm_rename, issue_slots[9].in_uop.bits.imm_rename connect slots_9.io.in_uop.bits.taken, issue_slots[9].in_uop.bits.taken connect slots_9.io.in_uop.bits.pc_lob, issue_slots[9].in_uop.bits.pc_lob connect slots_9.io.in_uop.bits.edge_inst, issue_slots[9].in_uop.bits.edge_inst connect slots_9.io.in_uop.bits.ftq_idx, issue_slots[9].in_uop.bits.ftq_idx connect slots_9.io.in_uop.bits.is_mov, issue_slots[9].in_uop.bits.is_mov connect slots_9.io.in_uop.bits.is_rocc, issue_slots[9].in_uop.bits.is_rocc connect slots_9.io.in_uop.bits.is_sys_pc2epc, issue_slots[9].in_uop.bits.is_sys_pc2epc connect slots_9.io.in_uop.bits.is_eret, issue_slots[9].in_uop.bits.is_eret connect slots_9.io.in_uop.bits.is_amo, issue_slots[9].in_uop.bits.is_amo connect slots_9.io.in_uop.bits.is_sfence, issue_slots[9].in_uop.bits.is_sfence connect slots_9.io.in_uop.bits.is_fencei, issue_slots[9].in_uop.bits.is_fencei connect slots_9.io.in_uop.bits.is_fence, issue_slots[9].in_uop.bits.is_fence connect slots_9.io.in_uop.bits.is_sfb, issue_slots[9].in_uop.bits.is_sfb connect slots_9.io.in_uop.bits.br_type, issue_slots[9].in_uop.bits.br_type connect slots_9.io.in_uop.bits.br_tag, issue_slots[9].in_uop.bits.br_tag connect slots_9.io.in_uop.bits.br_mask, issue_slots[9].in_uop.bits.br_mask connect slots_9.io.in_uop.bits.dis_col_sel, issue_slots[9].in_uop.bits.dis_col_sel connect slots_9.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[9].in_uop.bits.iw_p3_bypass_hint connect slots_9.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[9].in_uop.bits.iw_p2_bypass_hint connect slots_9.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[9].in_uop.bits.iw_p1_bypass_hint connect slots_9.io.in_uop.bits.iw_p2_speculative_child, issue_slots[9].in_uop.bits.iw_p2_speculative_child connect slots_9.io.in_uop.bits.iw_p1_speculative_child, issue_slots[9].in_uop.bits.iw_p1_speculative_child connect slots_9.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[9].in_uop.bits.iw_issued_partial_dgen connect slots_9.io.in_uop.bits.iw_issued_partial_agen, issue_slots[9].in_uop.bits.iw_issued_partial_agen connect slots_9.io.in_uop.bits.iw_issued, issue_slots[9].in_uop.bits.iw_issued connect slots_9.io.in_uop.bits.fu_code[0], issue_slots[9].in_uop.bits.fu_code[0] connect slots_9.io.in_uop.bits.fu_code[1], issue_slots[9].in_uop.bits.fu_code[1] connect slots_9.io.in_uop.bits.fu_code[2], issue_slots[9].in_uop.bits.fu_code[2] connect slots_9.io.in_uop.bits.fu_code[3], issue_slots[9].in_uop.bits.fu_code[3] connect slots_9.io.in_uop.bits.fu_code[4], issue_slots[9].in_uop.bits.fu_code[4] connect slots_9.io.in_uop.bits.fu_code[5], issue_slots[9].in_uop.bits.fu_code[5] connect slots_9.io.in_uop.bits.fu_code[6], issue_slots[9].in_uop.bits.fu_code[6] connect slots_9.io.in_uop.bits.fu_code[7], issue_slots[9].in_uop.bits.fu_code[7] connect slots_9.io.in_uop.bits.fu_code[8], issue_slots[9].in_uop.bits.fu_code[8] connect slots_9.io.in_uop.bits.fu_code[9], issue_slots[9].in_uop.bits.fu_code[9] connect slots_9.io.in_uop.bits.iq_type[0], issue_slots[9].in_uop.bits.iq_type[0] connect slots_9.io.in_uop.bits.iq_type[1], issue_slots[9].in_uop.bits.iq_type[1] connect slots_9.io.in_uop.bits.iq_type[2], issue_slots[9].in_uop.bits.iq_type[2] connect slots_9.io.in_uop.bits.iq_type[3], issue_slots[9].in_uop.bits.iq_type[3] connect slots_9.io.in_uop.bits.debug_pc, issue_slots[9].in_uop.bits.debug_pc connect slots_9.io.in_uop.bits.is_rvc, issue_slots[9].in_uop.bits.is_rvc connect slots_9.io.in_uop.bits.debug_inst, issue_slots[9].in_uop.bits.debug_inst connect slots_9.io.in_uop.bits.inst, issue_slots[9].in_uop.bits.inst connect slots_9.io.in_uop.valid, issue_slots[9].in_uop.valid connect issue_slots[9].iss_uop.debug_tsrc, slots_9.io.iss_uop.debug_tsrc connect issue_slots[9].iss_uop.debug_fsrc, slots_9.io.iss_uop.debug_fsrc connect issue_slots[9].iss_uop.bp_xcpt_if, slots_9.io.iss_uop.bp_xcpt_if connect issue_slots[9].iss_uop.bp_debug_if, slots_9.io.iss_uop.bp_debug_if connect issue_slots[9].iss_uop.xcpt_ma_if, slots_9.io.iss_uop.xcpt_ma_if connect issue_slots[9].iss_uop.xcpt_ae_if, slots_9.io.iss_uop.xcpt_ae_if connect issue_slots[9].iss_uop.xcpt_pf_if, slots_9.io.iss_uop.xcpt_pf_if connect issue_slots[9].iss_uop.fp_typ, slots_9.io.iss_uop.fp_typ connect issue_slots[9].iss_uop.fp_rm, slots_9.io.iss_uop.fp_rm connect issue_slots[9].iss_uop.fp_val, slots_9.io.iss_uop.fp_val connect issue_slots[9].iss_uop.fcn_op, slots_9.io.iss_uop.fcn_op connect issue_slots[9].iss_uop.fcn_dw, slots_9.io.iss_uop.fcn_dw connect issue_slots[9].iss_uop.frs3_en, slots_9.io.iss_uop.frs3_en connect issue_slots[9].iss_uop.lrs2_rtype, slots_9.io.iss_uop.lrs2_rtype connect issue_slots[9].iss_uop.lrs1_rtype, slots_9.io.iss_uop.lrs1_rtype connect issue_slots[9].iss_uop.dst_rtype, slots_9.io.iss_uop.dst_rtype connect issue_slots[9].iss_uop.lrs3, slots_9.io.iss_uop.lrs3 connect issue_slots[9].iss_uop.lrs2, slots_9.io.iss_uop.lrs2 connect issue_slots[9].iss_uop.lrs1, slots_9.io.iss_uop.lrs1 connect issue_slots[9].iss_uop.ldst, slots_9.io.iss_uop.ldst connect issue_slots[9].iss_uop.ldst_is_rs1, slots_9.io.iss_uop.ldst_is_rs1 connect issue_slots[9].iss_uop.csr_cmd, slots_9.io.iss_uop.csr_cmd connect issue_slots[9].iss_uop.flush_on_commit, slots_9.io.iss_uop.flush_on_commit connect issue_slots[9].iss_uop.is_unique, slots_9.io.iss_uop.is_unique connect issue_slots[9].iss_uop.uses_stq, slots_9.io.iss_uop.uses_stq connect issue_slots[9].iss_uop.uses_ldq, slots_9.io.iss_uop.uses_ldq connect issue_slots[9].iss_uop.mem_signed, slots_9.io.iss_uop.mem_signed connect issue_slots[9].iss_uop.mem_size, slots_9.io.iss_uop.mem_size connect issue_slots[9].iss_uop.mem_cmd, slots_9.io.iss_uop.mem_cmd connect issue_slots[9].iss_uop.exc_cause, slots_9.io.iss_uop.exc_cause connect issue_slots[9].iss_uop.exception, slots_9.io.iss_uop.exception connect issue_slots[9].iss_uop.stale_pdst, slots_9.io.iss_uop.stale_pdst connect issue_slots[9].iss_uop.ppred_busy, slots_9.io.iss_uop.ppred_busy connect issue_slots[9].iss_uop.prs3_busy, slots_9.io.iss_uop.prs3_busy connect issue_slots[9].iss_uop.prs2_busy, slots_9.io.iss_uop.prs2_busy connect issue_slots[9].iss_uop.prs1_busy, slots_9.io.iss_uop.prs1_busy connect issue_slots[9].iss_uop.ppred, slots_9.io.iss_uop.ppred connect issue_slots[9].iss_uop.prs3, slots_9.io.iss_uop.prs3 connect issue_slots[9].iss_uop.prs2, slots_9.io.iss_uop.prs2 connect issue_slots[9].iss_uop.prs1, slots_9.io.iss_uop.prs1 connect issue_slots[9].iss_uop.pdst, slots_9.io.iss_uop.pdst connect issue_slots[9].iss_uop.rxq_idx, slots_9.io.iss_uop.rxq_idx connect issue_slots[9].iss_uop.stq_idx, slots_9.io.iss_uop.stq_idx connect issue_slots[9].iss_uop.ldq_idx, slots_9.io.iss_uop.ldq_idx connect issue_slots[9].iss_uop.rob_idx, slots_9.io.iss_uop.rob_idx connect issue_slots[9].iss_uop.fp_ctrl.vec, slots_9.io.iss_uop.fp_ctrl.vec connect issue_slots[9].iss_uop.fp_ctrl.wflags, slots_9.io.iss_uop.fp_ctrl.wflags connect issue_slots[9].iss_uop.fp_ctrl.sqrt, slots_9.io.iss_uop.fp_ctrl.sqrt connect issue_slots[9].iss_uop.fp_ctrl.div, slots_9.io.iss_uop.fp_ctrl.div connect issue_slots[9].iss_uop.fp_ctrl.fma, slots_9.io.iss_uop.fp_ctrl.fma connect issue_slots[9].iss_uop.fp_ctrl.fastpipe, slots_9.io.iss_uop.fp_ctrl.fastpipe connect issue_slots[9].iss_uop.fp_ctrl.toint, slots_9.io.iss_uop.fp_ctrl.toint connect issue_slots[9].iss_uop.fp_ctrl.fromint, slots_9.io.iss_uop.fp_ctrl.fromint connect issue_slots[9].iss_uop.fp_ctrl.typeTagOut, slots_9.io.iss_uop.fp_ctrl.typeTagOut connect issue_slots[9].iss_uop.fp_ctrl.typeTagIn, slots_9.io.iss_uop.fp_ctrl.typeTagIn connect issue_slots[9].iss_uop.fp_ctrl.swap23, slots_9.io.iss_uop.fp_ctrl.swap23 connect issue_slots[9].iss_uop.fp_ctrl.swap12, slots_9.io.iss_uop.fp_ctrl.swap12 connect issue_slots[9].iss_uop.fp_ctrl.ren3, slots_9.io.iss_uop.fp_ctrl.ren3 connect issue_slots[9].iss_uop.fp_ctrl.ren2, slots_9.io.iss_uop.fp_ctrl.ren2 connect issue_slots[9].iss_uop.fp_ctrl.ren1, slots_9.io.iss_uop.fp_ctrl.ren1 connect issue_slots[9].iss_uop.fp_ctrl.wen, slots_9.io.iss_uop.fp_ctrl.wen connect issue_slots[9].iss_uop.fp_ctrl.ldst, slots_9.io.iss_uop.fp_ctrl.ldst connect issue_slots[9].iss_uop.op2_sel, slots_9.io.iss_uop.op2_sel connect issue_slots[9].iss_uop.op1_sel, slots_9.io.iss_uop.op1_sel connect issue_slots[9].iss_uop.imm_packed, slots_9.io.iss_uop.imm_packed connect issue_slots[9].iss_uop.pimm, slots_9.io.iss_uop.pimm connect issue_slots[9].iss_uop.imm_sel, slots_9.io.iss_uop.imm_sel connect issue_slots[9].iss_uop.imm_rename, slots_9.io.iss_uop.imm_rename connect issue_slots[9].iss_uop.taken, slots_9.io.iss_uop.taken connect issue_slots[9].iss_uop.pc_lob, slots_9.io.iss_uop.pc_lob connect issue_slots[9].iss_uop.edge_inst, slots_9.io.iss_uop.edge_inst connect issue_slots[9].iss_uop.ftq_idx, slots_9.io.iss_uop.ftq_idx connect issue_slots[9].iss_uop.is_mov, slots_9.io.iss_uop.is_mov connect issue_slots[9].iss_uop.is_rocc, slots_9.io.iss_uop.is_rocc connect issue_slots[9].iss_uop.is_sys_pc2epc, slots_9.io.iss_uop.is_sys_pc2epc connect issue_slots[9].iss_uop.is_eret, slots_9.io.iss_uop.is_eret connect issue_slots[9].iss_uop.is_amo, slots_9.io.iss_uop.is_amo connect issue_slots[9].iss_uop.is_sfence, slots_9.io.iss_uop.is_sfence connect issue_slots[9].iss_uop.is_fencei, slots_9.io.iss_uop.is_fencei connect issue_slots[9].iss_uop.is_fence, slots_9.io.iss_uop.is_fence connect issue_slots[9].iss_uop.is_sfb, slots_9.io.iss_uop.is_sfb connect issue_slots[9].iss_uop.br_type, slots_9.io.iss_uop.br_type connect issue_slots[9].iss_uop.br_tag, slots_9.io.iss_uop.br_tag connect issue_slots[9].iss_uop.br_mask, slots_9.io.iss_uop.br_mask connect issue_slots[9].iss_uop.dis_col_sel, slots_9.io.iss_uop.dis_col_sel connect issue_slots[9].iss_uop.iw_p3_bypass_hint, slots_9.io.iss_uop.iw_p3_bypass_hint connect issue_slots[9].iss_uop.iw_p2_bypass_hint, slots_9.io.iss_uop.iw_p2_bypass_hint connect issue_slots[9].iss_uop.iw_p1_bypass_hint, slots_9.io.iss_uop.iw_p1_bypass_hint connect issue_slots[9].iss_uop.iw_p2_speculative_child, slots_9.io.iss_uop.iw_p2_speculative_child connect issue_slots[9].iss_uop.iw_p1_speculative_child, slots_9.io.iss_uop.iw_p1_speculative_child connect issue_slots[9].iss_uop.iw_issued_partial_dgen, slots_9.io.iss_uop.iw_issued_partial_dgen connect issue_slots[9].iss_uop.iw_issued_partial_agen, slots_9.io.iss_uop.iw_issued_partial_agen connect issue_slots[9].iss_uop.iw_issued, slots_9.io.iss_uop.iw_issued connect issue_slots[9].iss_uop.fu_code[0], slots_9.io.iss_uop.fu_code[0] connect issue_slots[9].iss_uop.fu_code[1], slots_9.io.iss_uop.fu_code[1] connect issue_slots[9].iss_uop.fu_code[2], slots_9.io.iss_uop.fu_code[2] connect issue_slots[9].iss_uop.fu_code[3], slots_9.io.iss_uop.fu_code[3] connect issue_slots[9].iss_uop.fu_code[4], slots_9.io.iss_uop.fu_code[4] connect issue_slots[9].iss_uop.fu_code[5], slots_9.io.iss_uop.fu_code[5] connect issue_slots[9].iss_uop.fu_code[6], slots_9.io.iss_uop.fu_code[6] connect issue_slots[9].iss_uop.fu_code[7], slots_9.io.iss_uop.fu_code[7] connect issue_slots[9].iss_uop.fu_code[8], slots_9.io.iss_uop.fu_code[8] connect issue_slots[9].iss_uop.fu_code[9], slots_9.io.iss_uop.fu_code[9] connect issue_slots[9].iss_uop.iq_type[0], slots_9.io.iss_uop.iq_type[0] connect issue_slots[9].iss_uop.iq_type[1], slots_9.io.iss_uop.iq_type[1] connect issue_slots[9].iss_uop.iq_type[2], slots_9.io.iss_uop.iq_type[2] connect issue_slots[9].iss_uop.iq_type[3], slots_9.io.iss_uop.iq_type[3] connect issue_slots[9].iss_uop.debug_pc, slots_9.io.iss_uop.debug_pc connect issue_slots[9].iss_uop.is_rvc, slots_9.io.iss_uop.is_rvc connect issue_slots[9].iss_uop.debug_inst, slots_9.io.iss_uop.debug_inst connect issue_slots[9].iss_uop.inst, slots_9.io.iss_uop.inst connect slots_9.io.grant, issue_slots[9].grant connect issue_slots[9].request, slots_9.io.request connect issue_slots[9].will_be_valid, slots_9.io.will_be_valid connect issue_slots[9].valid, slots_9.io.valid connect slots_10.io.child_rebusys, issue_slots[10].child_rebusys connect slots_10.io.pred_wakeup_port.bits, issue_slots[10].pred_wakeup_port.bits connect slots_10.io.pred_wakeup_port.valid, issue_slots[10].pred_wakeup_port.valid connect slots_10.io.wakeup_ports[0].bits.rebusy, issue_slots[10].wakeup_ports[0].bits.rebusy connect slots_10.io.wakeup_ports[0].bits.speculative_mask, issue_slots[10].wakeup_ports[0].bits.speculative_mask connect slots_10.io.wakeup_ports[0].bits.bypassable, issue_slots[10].wakeup_ports[0].bits.bypassable connect slots_10.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[10].wakeup_ports[0].bits.uop.debug_tsrc connect slots_10.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[10].wakeup_ports[0].bits.uop.debug_fsrc connect slots_10.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[10].wakeup_ports[0].bits.uop.bp_xcpt_if connect slots_10.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[10].wakeup_ports[0].bits.uop.bp_debug_if connect slots_10.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[10].wakeup_ports[0].bits.uop.xcpt_ma_if connect slots_10.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[10].wakeup_ports[0].bits.uop.xcpt_ae_if connect slots_10.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[10].wakeup_ports[0].bits.uop.xcpt_pf_if connect slots_10.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[10].wakeup_ports[0].bits.uop.fp_typ connect slots_10.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[10].wakeup_ports[0].bits.uop.fp_rm connect slots_10.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[10].wakeup_ports[0].bits.uop.fp_val connect slots_10.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[10].wakeup_ports[0].bits.uop.fcn_op connect slots_10.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[10].wakeup_ports[0].bits.uop.fcn_dw connect slots_10.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[10].wakeup_ports[0].bits.uop.frs3_en connect slots_10.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[10].wakeup_ports[0].bits.uop.lrs2_rtype connect slots_10.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[10].wakeup_ports[0].bits.uop.lrs1_rtype connect slots_10.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[10].wakeup_ports[0].bits.uop.dst_rtype connect slots_10.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[10].wakeup_ports[0].bits.uop.lrs3 connect slots_10.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[10].wakeup_ports[0].bits.uop.lrs2 connect slots_10.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[10].wakeup_ports[0].bits.uop.lrs1 connect slots_10.io.wakeup_ports[0].bits.uop.ldst, issue_slots[10].wakeup_ports[0].bits.uop.ldst connect slots_10.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[10].wakeup_ports[0].bits.uop.ldst_is_rs1 connect slots_10.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[10].wakeup_ports[0].bits.uop.csr_cmd connect slots_10.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[10].wakeup_ports[0].bits.uop.flush_on_commit connect slots_10.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[10].wakeup_ports[0].bits.uop.is_unique connect slots_10.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[10].wakeup_ports[0].bits.uop.uses_stq connect slots_10.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[10].wakeup_ports[0].bits.uop.uses_ldq connect slots_10.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[10].wakeup_ports[0].bits.uop.mem_signed connect slots_10.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[10].wakeup_ports[0].bits.uop.mem_size connect slots_10.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[10].wakeup_ports[0].bits.uop.mem_cmd connect slots_10.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[10].wakeup_ports[0].bits.uop.exc_cause connect slots_10.io.wakeup_ports[0].bits.uop.exception, issue_slots[10].wakeup_ports[0].bits.uop.exception connect slots_10.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[10].wakeup_ports[0].bits.uop.stale_pdst connect slots_10.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[10].wakeup_ports[0].bits.uop.ppred_busy connect slots_10.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[10].wakeup_ports[0].bits.uop.prs3_busy connect slots_10.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[10].wakeup_ports[0].bits.uop.prs2_busy connect slots_10.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[10].wakeup_ports[0].bits.uop.prs1_busy connect slots_10.io.wakeup_ports[0].bits.uop.ppred, issue_slots[10].wakeup_ports[0].bits.uop.ppred connect slots_10.io.wakeup_ports[0].bits.uop.prs3, issue_slots[10].wakeup_ports[0].bits.uop.prs3 connect slots_10.io.wakeup_ports[0].bits.uop.prs2, issue_slots[10].wakeup_ports[0].bits.uop.prs2 connect slots_10.io.wakeup_ports[0].bits.uop.prs1, issue_slots[10].wakeup_ports[0].bits.uop.prs1 connect slots_10.io.wakeup_ports[0].bits.uop.pdst, issue_slots[10].wakeup_ports[0].bits.uop.pdst connect slots_10.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[10].wakeup_ports[0].bits.uop.rxq_idx connect slots_10.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[10].wakeup_ports[0].bits.uop.stq_idx connect slots_10.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[10].wakeup_ports[0].bits.uop.ldq_idx connect slots_10.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[10].wakeup_ports[0].bits.uop.rob_idx connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.vec connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.wflags connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.div connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.fma connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.toint connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.fromint connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.wen connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.ldst connect slots_10.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[10].wakeup_ports[0].bits.uop.op2_sel connect slots_10.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[10].wakeup_ports[0].bits.uop.op1_sel connect slots_10.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[10].wakeup_ports[0].bits.uop.imm_packed connect slots_10.io.wakeup_ports[0].bits.uop.pimm, issue_slots[10].wakeup_ports[0].bits.uop.pimm connect slots_10.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[10].wakeup_ports[0].bits.uop.imm_sel connect slots_10.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[10].wakeup_ports[0].bits.uop.imm_rename connect slots_10.io.wakeup_ports[0].bits.uop.taken, issue_slots[10].wakeup_ports[0].bits.uop.taken connect slots_10.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[10].wakeup_ports[0].bits.uop.pc_lob connect slots_10.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[10].wakeup_ports[0].bits.uop.edge_inst connect slots_10.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[10].wakeup_ports[0].bits.uop.ftq_idx connect slots_10.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[10].wakeup_ports[0].bits.uop.is_mov connect slots_10.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[10].wakeup_ports[0].bits.uop.is_rocc connect slots_10.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[10].wakeup_ports[0].bits.uop.is_sys_pc2epc connect slots_10.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[10].wakeup_ports[0].bits.uop.is_eret connect slots_10.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[10].wakeup_ports[0].bits.uop.is_amo connect slots_10.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[10].wakeup_ports[0].bits.uop.is_sfence connect slots_10.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[10].wakeup_ports[0].bits.uop.is_fencei connect slots_10.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[10].wakeup_ports[0].bits.uop.is_fence connect slots_10.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[10].wakeup_ports[0].bits.uop.is_sfb connect slots_10.io.wakeup_ports[0].bits.uop.br_type, issue_slots[10].wakeup_ports[0].bits.uop.br_type connect slots_10.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[10].wakeup_ports[0].bits.uop.br_tag connect slots_10.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[10].wakeup_ports[0].bits.uop.br_mask connect slots_10.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[10].wakeup_ports[0].bits.uop.dis_col_sel connect slots_10.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[10].wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect slots_10.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[10].wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect slots_10.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[10].wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect slots_10.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[10].wakeup_ports[0].bits.uop.iw_p2_speculative_child connect slots_10.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[10].wakeup_ports[0].bits.uop.iw_p1_speculative_child connect slots_10.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[10].wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect slots_10.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[10].wakeup_ports[0].bits.uop.iw_issued_partial_agen connect slots_10.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[10].wakeup_ports[0].bits.uop.iw_issued connect slots_10.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[10].wakeup_ports[0].bits.uop.fu_code[0] connect slots_10.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[10].wakeup_ports[0].bits.uop.fu_code[1] connect slots_10.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[10].wakeup_ports[0].bits.uop.fu_code[2] connect slots_10.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[10].wakeup_ports[0].bits.uop.fu_code[3] connect slots_10.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[10].wakeup_ports[0].bits.uop.fu_code[4] connect slots_10.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[10].wakeup_ports[0].bits.uop.fu_code[5] connect slots_10.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[10].wakeup_ports[0].bits.uop.fu_code[6] connect slots_10.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[10].wakeup_ports[0].bits.uop.fu_code[7] connect slots_10.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[10].wakeup_ports[0].bits.uop.fu_code[8] connect slots_10.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[10].wakeup_ports[0].bits.uop.fu_code[9] connect slots_10.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[10].wakeup_ports[0].bits.uop.iq_type[0] connect slots_10.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[10].wakeup_ports[0].bits.uop.iq_type[1] connect slots_10.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[10].wakeup_ports[0].bits.uop.iq_type[2] connect slots_10.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[10].wakeup_ports[0].bits.uop.iq_type[3] connect slots_10.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[10].wakeup_ports[0].bits.uop.debug_pc connect slots_10.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[10].wakeup_ports[0].bits.uop.is_rvc connect slots_10.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[10].wakeup_ports[0].bits.uop.debug_inst connect slots_10.io.wakeup_ports[0].bits.uop.inst, issue_slots[10].wakeup_ports[0].bits.uop.inst connect slots_10.io.wakeup_ports[0].valid, issue_slots[10].wakeup_ports[0].valid connect slots_10.io.wakeup_ports[1].bits.rebusy, issue_slots[10].wakeup_ports[1].bits.rebusy connect slots_10.io.wakeup_ports[1].bits.speculative_mask, issue_slots[10].wakeup_ports[1].bits.speculative_mask connect slots_10.io.wakeup_ports[1].bits.bypassable, issue_slots[10].wakeup_ports[1].bits.bypassable connect slots_10.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[10].wakeup_ports[1].bits.uop.debug_tsrc connect slots_10.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[10].wakeup_ports[1].bits.uop.debug_fsrc connect slots_10.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[10].wakeup_ports[1].bits.uop.bp_xcpt_if connect slots_10.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[10].wakeup_ports[1].bits.uop.bp_debug_if connect slots_10.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[10].wakeup_ports[1].bits.uop.xcpt_ma_if connect slots_10.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[10].wakeup_ports[1].bits.uop.xcpt_ae_if connect slots_10.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[10].wakeup_ports[1].bits.uop.xcpt_pf_if connect slots_10.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[10].wakeup_ports[1].bits.uop.fp_typ connect slots_10.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[10].wakeup_ports[1].bits.uop.fp_rm connect slots_10.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[10].wakeup_ports[1].bits.uop.fp_val connect slots_10.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[10].wakeup_ports[1].bits.uop.fcn_op connect slots_10.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[10].wakeup_ports[1].bits.uop.fcn_dw connect slots_10.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[10].wakeup_ports[1].bits.uop.frs3_en connect slots_10.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[10].wakeup_ports[1].bits.uop.lrs2_rtype connect slots_10.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[10].wakeup_ports[1].bits.uop.lrs1_rtype connect slots_10.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[10].wakeup_ports[1].bits.uop.dst_rtype connect slots_10.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[10].wakeup_ports[1].bits.uop.lrs3 connect slots_10.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[10].wakeup_ports[1].bits.uop.lrs2 connect slots_10.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[10].wakeup_ports[1].bits.uop.lrs1 connect slots_10.io.wakeup_ports[1].bits.uop.ldst, issue_slots[10].wakeup_ports[1].bits.uop.ldst connect slots_10.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[10].wakeup_ports[1].bits.uop.ldst_is_rs1 connect slots_10.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[10].wakeup_ports[1].bits.uop.csr_cmd connect slots_10.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[10].wakeup_ports[1].bits.uop.flush_on_commit connect slots_10.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[10].wakeup_ports[1].bits.uop.is_unique connect slots_10.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[10].wakeup_ports[1].bits.uop.uses_stq connect slots_10.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[10].wakeup_ports[1].bits.uop.uses_ldq connect slots_10.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[10].wakeup_ports[1].bits.uop.mem_signed connect slots_10.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[10].wakeup_ports[1].bits.uop.mem_size connect slots_10.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[10].wakeup_ports[1].bits.uop.mem_cmd connect slots_10.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[10].wakeup_ports[1].bits.uop.exc_cause connect slots_10.io.wakeup_ports[1].bits.uop.exception, issue_slots[10].wakeup_ports[1].bits.uop.exception connect slots_10.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[10].wakeup_ports[1].bits.uop.stale_pdst connect slots_10.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[10].wakeup_ports[1].bits.uop.ppred_busy connect slots_10.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[10].wakeup_ports[1].bits.uop.prs3_busy connect slots_10.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[10].wakeup_ports[1].bits.uop.prs2_busy connect slots_10.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[10].wakeup_ports[1].bits.uop.prs1_busy connect slots_10.io.wakeup_ports[1].bits.uop.ppred, issue_slots[10].wakeup_ports[1].bits.uop.ppred connect slots_10.io.wakeup_ports[1].bits.uop.prs3, issue_slots[10].wakeup_ports[1].bits.uop.prs3 connect slots_10.io.wakeup_ports[1].bits.uop.prs2, issue_slots[10].wakeup_ports[1].bits.uop.prs2 connect slots_10.io.wakeup_ports[1].bits.uop.prs1, issue_slots[10].wakeup_ports[1].bits.uop.prs1 connect slots_10.io.wakeup_ports[1].bits.uop.pdst, issue_slots[10].wakeup_ports[1].bits.uop.pdst connect slots_10.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[10].wakeup_ports[1].bits.uop.rxq_idx connect slots_10.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[10].wakeup_ports[1].bits.uop.stq_idx connect slots_10.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[10].wakeup_ports[1].bits.uop.ldq_idx connect slots_10.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[10].wakeup_ports[1].bits.uop.rob_idx connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.vec connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.wflags connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.div connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.fma connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.toint connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.fromint connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.wen connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.ldst connect slots_10.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[10].wakeup_ports[1].bits.uop.op2_sel connect slots_10.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[10].wakeup_ports[1].bits.uop.op1_sel connect slots_10.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[10].wakeup_ports[1].bits.uop.imm_packed connect slots_10.io.wakeup_ports[1].bits.uop.pimm, issue_slots[10].wakeup_ports[1].bits.uop.pimm connect slots_10.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[10].wakeup_ports[1].bits.uop.imm_sel connect slots_10.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[10].wakeup_ports[1].bits.uop.imm_rename connect slots_10.io.wakeup_ports[1].bits.uop.taken, issue_slots[10].wakeup_ports[1].bits.uop.taken connect slots_10.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[10].wakeup_ports[1].bits.uop.pc_lob connect slots_10.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[10].wakeup_ports[1].bits.uop.edge_inst connect slots_10.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[10].wakeup_ports[1].bits.uop.ftq_idx connect slots_10.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[10].wakeup_ports[1].bits.uop.is_mov connect slots_10.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[10].wakeup_ports[1].bits.uop.is_rocc connect slots_10.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[10].wakeup_ports[1].bits.uop.is_sys_pc2epc connect slots_10.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[10].wakeup_ports[1].bits.uop.is_eret connect slots_10.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[10].wakeup_ports[1].bits.uop.is_amo connect slots_10.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[10].wakeup_ports[1].bits.uop.is_sfence connect slots_10.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[10].wakeup_ports[1].bits.uop.is_fencei connect slots_10.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[10].wakeup_ports[1].bits.uop.is_fence connect slots_10.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[10].wakeup_ports[1].bits.uop.is_sfb connect slots_10.io.wakeup_ports[1].bits.uop.br_type, issue_slots[10].wakeup_ports[1].bits.uop.br_type connect slots_10.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[10].wakeup_ports[1].bits.uop.br_tag connect slots_10.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[10].wakeup_ports[1].bits.uop.br_mask connect slots_10.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[10].wakeup_ports[1].bits.uop.dis_col_sel connect slots_10.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[10].wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect slots_10.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[10].wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect slots_10.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[10].wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect slots_10.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[10].wakeup_ports[1].bits.uop.iw_p2_speculative_child connect slots_10.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[10].wakeup_ports[1].bits.uop.iw_p1_speculative_child connect slots_10.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[10].wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect slots_10.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[10].wakeup_ports[1].bits.uop.iw_issued_partial_agen connect slots_10.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[10].wakeup_ports[1].bits.uop.iw_issued connect slots_10.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[10].wakeup_ports[1].bits.uop.fu_code[0] connect slots_10.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[10].wakeup_ports[1].bits.uop.fu_code[1] connect slots_10.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[10].wakeup_ports[1].bits.uop.fu_code[2] connect slots_10.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[10].wakeup_ports[1].bits.uop.fu_code[3] connect slots_10.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[10].wakeup_ports[1].bits.uop.fu_code[4] connect slots_10.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[10].wakeup_ports[1].bits.uop.fu_code[5] connect slots_10.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[10].wakeup_ports[1].bits.uop.fu_code[6] connect slots_10.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[10].wakeup_ports[1].bits.uop.fu_code[7] connect slots_10.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[10].wakeup_ports[1].bits.uop.fu_code[8] connect slots_10.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[10].wakeup_ports[1].bits.uop.fu_code[9] connect slots_10.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[10].wakeup_ports[1].bits.uop.iq_type[0] connect slots_10.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[10].wakeup_ports[1].bits.uop.iq_type[1] connect slots_10.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[10].wakeup_ports[1].bits.uop.iq_type[2] connect slots_10.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[10].wakeup_ports[1].bits.uop.iq_type[3] connect slots_10.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[10].wakeup_ports[1].bits.uop.debug_pc connect slots_10.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[10].wakeup_ports[1].bits.uop.is_rvc connect slots_10.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[10].wakeup_ports[1].bits.uop.debug_inst connect slots_10.io.wakeup_ports[1].bits.uop.inst, issue_slots[10].wakeup_ports[1].bits.uop.inst connect slots_10.io.wakeup_ports[1].valid, issue_slots[10].wakeup_ports[1].valid connect slots_10.io.wakeup_ports[2].bits.rebusy, issue_slots[10].wakeup_ports[2].bits.rebusy connect slots_10.io.wakeup_ports[2].bits.speculative_mask, issue_slots[10].wakeup_ports[2].bits.speculative_mask connect slots_10.io.wakeup_ports[2].bits.bypassable, issue_slots[10].wakeup_ports[2].bits.bypassable connect slots_10.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[10].wakeup_ports[2].bits.uop.debug_tsrc connect slots_10.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[10].wakeup_ports[2].bits.uop.debug_fsrc connect slots_10.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[10].wakeup_ports[2].bits.uop.bp_xcpt_if connect slots_10.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[10].wakeup_ports[2].bits.uop.bp_debug_if connect slots_10.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[10].wakeup_ports[2].bits.uop.xcpt_ma_if connect slots_10.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[10].wakeup_ports[2].bits.uop.xcpt_ae_if connect slots_10.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[10].wakeup_ports[2].bits.uop.xcpt_pf_if connect slots_10.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[10].wakeup_ports[2].bits.uop.fp_typ connect slots_10.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[10].wakeup_ports[2].bits.uop.fp_rm connect slots_10.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[10].wakeup_ports[2].bits.uop.fp_val connect slots_10.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[10].wakeup_ports[2].bits.uop.fcn_op connect slots_10.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[10].wakeup_ports[2].bits.uop.fcn_dw connect slots_10.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[10].wakeup_ports[2].bits.uop.frs3_en connect slots_10.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[10].wakeup_ports[2].bits.uop.lrs2_rtype connect slots_10.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[10].wakeup_ports[2].bits.uop.lrs1_rtype connect slots_10.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[10].wakeup_ports[2].bits.uop.dst_rtype connect slots_10.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[10].wakeup_ports[2].bits.uop.lrs3 connect slots_10.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[10].wakeup_ports[2].bits.uop.lrs2 connect slots_10.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[10].wakeup_ports[2].bits.uop.lrs1 connect slots_10.io.wakeup_ports[2].bits.uop.ldst, issue_slots[10].wakeup_ports[2].bits.uop.ldst connect slots_10.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[10].wakeup_ports[2].bits.uop.ldst_is_rs1 connect slots_10.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[10].wakeup_ports[2].bits.uop.csr_cmd connect slots_10.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[10].wakeup_ports[2].bits.uop.flush_on_commit connect slots_10.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[10].wakeup_ports[2].bits.uop.is_unique connect slots_10.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[10].wakeup_ports[2].bits.uop.uses_stq connect slots_10.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[10].wakeup_ports[2].bits.uop.uses_ldq connect slots_10.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[10].wakeup_ports[2].bits.uop.mem_signed connect slots_10.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[10].wakeup_ports[2].bits.uop.mem_size connect slots_10.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[10].wakeup_ports[2].bits.uop.mem_cmd connect slots_10.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[10].wakeup_ports[2].bits.uop.exc_cause connect slots_10.io.wakeup_ports[2].bits.uop.exception, issue_slots[10].wakeup_ports[2].bits.uop.exception connect slots_10.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[10].wakeup_ports[2].bits.uop.stale_pdst connect slots_10.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[10].wakeup_ports[2].bits.uop.ppred_busy connect slots_10.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[10].wakeup_ports[2].bits.uop.prs3_busy connect slots_10.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[10].wakeup_ports[2].bits.uop.prs2_busy connect slots_10.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[10].wakeup_ports[2].bits.uop.prs1_busy connect slots_10.io.wakeup_ports[2].bits.uop.ppred, issue_slots[10].wakeup_ports[2].bits.uop.ppred connect slots_10.io.wakeup_ports[2].bits.uop.prs3, issue_slots[10].wakeup_ports[2].bits.uop.prs3 connect slots_10.io.wakeup_ports[2].bits.uop.prs2, issue_slots[10].wakeup_ports[2].bits.uop.prs2 connect slots_10.io.wakeup_ports[2].bits.uop.prs1, issue_slots[10].wakeup_ports[2].bits.uop.prs1 connect slots_10.io.wakeup_ports[2].bits.uop.pdst, issue_slots[10].wakeup_ports[2].bits.uop.pdst connect slots_10.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[10].wakeup_ports[2].bits.uop.rxq_idx connect slots_10.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[10].wakeup_ports[2].bits.uop.stq_idx connect slots_10.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[10].wakeup_ports[2].bits.uop.ldq_idx connect slots_10.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[10].wakeup_ports[2].bits.uop.rob_idx connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.vec connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.wflags connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.div connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.fma connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.toint connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.fromint connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.wen connect slots_10.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.ldst connect slots_10.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[10].wakeup_ports[2].bits.uop.op2_sel connect slots_10.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[10].wakeup_ports[2].bits.uop.op1_sel connect slots_10.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[10].wakeup_ports[2].bits.uop.imm_packed connect slots_10.io.wakeup_ports[2].bits.uop.pimm, issue_slots[10].wakeup_ports[2].bits.uop.pimm connect slots_10.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[10].wakeup_ports[2].bits.uop.imm_sel connect slots_10.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[10].wakeup_ports[2].bits.uop.imm_rename connect slots_10.io.wakeup_ports[2].bits.uop.taken, issue_slots[10].wakeup_ports[2].bits.uop.taken connect slots_10.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[10].wakeup_ports[2].bits.uop.pc_lob connect slots_10.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[10].wakeup_ports[2].bits.uop.edge_inst connect slots_10.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[10].wakeup_ports[2].bits.uop.ftq_idx connect slots_10.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[10].wakeup_ports[2].bits.uop.is_mov connect slots_10.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[10].wakeup_ports[2].bits.uop.is_rocc connect slots_10.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[10].wakeup_ports[2].bits.uop.is_sys_pc2epc connect slots_10.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[10].wakeup_ports[2].bits.uop.is_eret connect slots_10.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[10].wakeup_ports[2].bits.uop.is_amo connect slots_10.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[10].wakeup_ports[2].bits.uop.is_sfence connect slots_10.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[10].wakeup_ports[2].bits.uop.is_fencei connect slots_10.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[10].wakeup_ports[2].bits.uop.is_fence connect slots_10.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[10].wakeup_ports[2].bits.uop.is_sfb connect slots_10.io.wakeup_ports[2].bits.uop.br_type, issue_slots[10].wakeup_ports[2].bits.uop.br_type connect slots_10.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[10].wakeup_ports[2].bits.uop.br_tag connect slots_10.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[10].wakeup_ports[2].bits.uop.br_mask connect slots_10.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[10].wakeup_ports[2].bits.uop.dis_col_sel connect slots_10.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[10].wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect slots_10.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[10].wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect slots_10.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[10].wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect slots_10.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[10].wakeup_ports[2].bits.uop.iw_p2_speculative_child connect slots_10.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[10].wakeup_ports[2].bits.uop.iw_p1_speculative_child connect slots_10.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[10].wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect slots_10.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[10].wakeup_ports[2].bits.uop.iw_issued_partial_agen connect slots_10.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[10].wakeup_ports[2].bits.uop.iw_issued connect slots_10.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[10].wakeup_ports[2].bits.uop.fu_code[0] connect slots_10.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[10].wakeup_ports[2].bits.uop.fu_code[1] connect slots_10.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[10].wakeup_ports[2].bits.uop.fu_code[2] connect slots_10.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[10].wakeup_ports[2].bits.uop.fu_code[3] connect slots_10.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[10].wakeup_ports[2].bits.uop.fu_code[4] connect slots_10.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[10].wakeup_ports[2].bits.uop.fu_code[5] connect slots_10.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[10].wakeup_ports[2].bits.uop.fu_code[6] connect slots_10.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[10].wakeup_ports[2].bits.uop.fu_code[7] connect slots_10.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[10].wakeup_ports[2].bits.uop.fu_code[8] connect slots_10.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[10].wakeup_ports[2].bits.uop.fu_code[9] connect slots_10.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[10].wakeup_ports[2].bits.uop.iq_type[0] connect slots_10.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[10].wakeup_ports[2].bits.uop.iq_type[1] connect slots_10.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[10].wakeup_ports[2].bits.uop.iq_type[2] connect slots_10.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[10].wakeup_ports[2].bits.uop.iq_type[3] connect slots_10.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[10].wakeup_ports[2].bits.uop.debug_pc connect slots_10.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[10].wakeup_ports[2].bits.uop.is_rvc connect slots_10.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[10].wakeup_ports[2].bits.uop.debug_inst connect slots_10.io.wakeup_ports[2].bits.uop.inst, issue_slots[10].wakeup_ports[2].bits.uop.inst connect slots_10.io.wakeup_ports[2].valid, issue_slots[10].wakeup_ports[2].valid connect slots_10.io.wakeup_ports[3].bits.rebusy, issue_slots[10].wakeup_ports[3].bits.rebusy connect slots_10.io.wakeup_ports[3].bits.speculative_mask, issue_slots[10].wakeup_ports[3].bits.speculative_mask connect slots_10.io.wakeup_ports[3].bits.bypassable, issue_slots[10].wakeup_ports[3].bits.bypassable connect slots_10.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[10].wakeup_ports[3].bits.uop.debug_tsrc connect slots_10.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[10].wakeup_ports[3].bits.uop.debug_fsrc connect slots_10.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[10].wakeup_ports[3].bits.uop.bp_xcpt_if connect slots_10.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[10].wakeup_ports[3].bits.uop.bp_debug_if connect slots_10.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[10].wakeup_ports[3].bits.uop.xcpt_ma_if connect slots_10.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[10].wakeup_ports[3].bits.uop.xcpt_ae_if connect slots_10.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[10].wakeup_ports[3].bits.uop.xcpt_pf_if connect slots_10.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[10].wakeup_ports[3].bits.uop.fp_typ connect slots_10.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[10].wakeup_ports[3].bits.uop.fp_rm connect slots_10.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[10].wakeup_ports[3].bits.uop.fp_val connect slots_10.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[10].wakeup_ports[3].bits.uop.fcn_op connect slots_10.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[10].wakeup_ports[3].bits.uop.fcn_dw connect slots_10.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[10].wakeup_ports[3].bits.uop.frs3_en connect slots_10.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[10].wakeup_ports[3].bits.uop.lrs2_rtype connect slots_10.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[10].wakeup_ports[3].bits.uop.lrs1_rtype connect slots_10.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[10].wakeup_ports[3].bits.uop.dst_rtype connect slots_10.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[10].wakeup_ports[3].bits.uop.lrs3 connect slots_10.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[10].wakeup_ports[3].bits.uop.lrs2 connect slots_10.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[10].wakeup_ports[3].bits.uop.lrs1 connect slots_10.io.wakeup_ports[3].bits.uop.ldst, issue_slots[10].wakeup_ports[3].bits.uop.ldst connect slots_10.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[10].wakeup_ports[3].bits.uop.ldst_is_rs1 connect slots_10.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[10].wakeup_ports[3].bits.uop.csr_cmd connect slots_10.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[10].wakeup_ports[3].bits.uop.flush_on_commit connect slots_10.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[10].wakeup_ports[3].bits.uop.is_unique connect slots_10.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[10].wakeup_ports[3].bits.uop.uses_stq connect slots_10.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[10].wakeup_ports[3].bits.uop.uses_ldq connect slots_10.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[10].wakeup_ports[3].bits.uop.mem_signed connect slots_10.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[10].wakeup_ports[3].bits.uop.mem_size connect slots_10.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[10].wakeup_ports[3].bits.uop.mem_cmd connect slots_10.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[10].wakeup_ports[3].bits.uop.exc_cause connect slots_10.io.wakeup_ports[3].bits.uop.exception, issue_slots[10].wakeup_ports[3].bits.uop.exception connect slots_10.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[10].wakeup_ports[3].bits.uop.stale_pdst connect slots_10.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[10].wakeup_ports[3].bits.uop.ppred_busy connect slots_10.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[10].wakeup_ports[3].bits.uop.prs3_busy connect slots_10.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[10].wakeup_ports[3].bits.uop.prs2_busy connect slots_10.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[10].wakeup_ports[3].bits.uop.prs1_busy connect slots_10.io.wakeup_ports[3].bits.uop.ppred, issue_slots[10].wakeup_ports[3].bits.uop.ppred connect slots_10.io.wakeup_ports[3].bits.uop.prs3, issue_slots[10].wakeup_ports[3].bits.uop.prs3 connect slots_10.io.wakeup_ports[3].bits.uop.prs2, issue_slots[10].wakeup_ports[3].bits.uop.prs2 connect slots_10.io.wakeup_ports[3].bits.uop.prs1, issue_slots[10].wakeup_ports[3].bits.uop.prs1 connect slots_10.io.wakeup_ports[3].bits.uop.pdst, issue_slots[10].wakeup_ports[3].bits.uop.pdst connect slots_10.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[10].wakeup_ports[3].bits.uop.rxq_idx connect slots_10.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[10].wakeup_ports[3].bits.uop.stq_idx connect slots_10.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[10].wakeup_ports[3].bits.uop.ldq_idx connect slots_10.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[10].wakeup_ports[3].bits.uop.rob_idx connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.vec connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.wflags connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.div connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.fma connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.toint connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.fromint connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.wen connect slots_10.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.ldst connect slots_10.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[10].wakeup_ports[3].bits.uop.op2_sel connect slots_10.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[10].wakeup_ports[3].bits.uop.op1_sel connect slots_10.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[10].wakeup_ports[3].bits.uop.imm_packed connect slots_10.io.wakeup_ports[3].bits.uop.pimm, issue_slots[10].wakeup_ports[3].bits.uop.pimm connect slots_10.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[10].wakeup_ports[3].bits.uop.imm_sel connect slots_10.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[10].wakeup_ports[3].bits.uop.imm_rename connect slots_10.io.wakeup_ports[3].bits.uop.taken, issue_slots[10].wakeup_ports[3].bits.uop.taken connect slots_10.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[10].wakeup_ports[3].bits.uop.pc_lob connect slots_10.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[10].wakeup_ports[3].bits.uop.edge_inst connect slots_10.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[10].wakeup_ports[3].bits.uop.ftq_idx connect slots_10.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[10].wakeup_ports[3].bits.uop.is_mov connect slots_10.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[10].wakeup_ports[3].bits.uop.is_rocc connect slots_10.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[10].wakeup_ports[3].bits.uop.is_sys_pc2epc connect slots_10.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[10].wakeup_ports[3].bits.uop.is_eret connect slots_10.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[10].wakeup_ports[3].bits.uop.is_amo connect slots_10.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[10].wakeup_ports[3].bits.uop.is_sfence connect slots_10.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[10].wakeup_ports[3].bits.uop.is_fencei connect slots_10.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[10].wakeup_ports[3].bits.uop.is_fence connect slots_10.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[10].wakeup_ports[3].bits.uop.is_sfb connect slots_10.io.wakeup_ports[3].bits.uop.br_type, issue_slots[10].wakeup_ports[3].bits.uop.br_type connect slots_10.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[10].wakeup_ports[3].bits.uop.br_tag connect slots_10.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[10].wakeup_ports[3].bits.uop.br_mask connect slots_10.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[10].wakeup_ports[3].bits.uop.dis_col_sel connect slots_10.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[10].wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect slots_10.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[10].wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect slots_10.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[10].wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect slots_10.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[10].wakeup_ports[3].bits.uop.iw_p2_speculative_child connect slots_10.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[10].wakeup_ports[3].bits.uop.iw_p1_speculative_child connect slots_10.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[10].wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect slots_10.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[10].wakeup_ports[3].bits.uop.iw_issued_partial_agen connect slots_10.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[10].wakeup_ports[3].bits.uop.iw_issued connect slots_10.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[10].wakeup_ports[3].bits.uop.fu_code[0] connect slots_10.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[10].wakeup_ports[3].bits.uop.fu_code[1] connect slots_10.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[10].wakeup_ports[3].bits.uop.fu_code[2] connect slots_10.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[10].wakeup_ports[3].bits.uop.fu_code[3] connect slots_10.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[10].wakeup_ports[3].bits.uop.fu_code[4] connect slots_10.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[10].wakeup_ports[3].bits.uop.fu_code[5] connect slots_10.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[10].wakeup_ports[3].bits.uop.fu_code[6] connect slots_10.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[10].wakeup_ports[3].bits.uop.fu_code[7] connect slots_10.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[10].wakeup_ports[3].bits.uop.fu_code[8] connect slots_10.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[10].wakeup_ports[3].bits.uop.fu_code[9] connect slots_10.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[10].wakeup_ports[3].bits.uop.iq_type[0] connect slots_10.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[10].wakeup_ports[3].bits.uop.iq_type[1] connect slots_10.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[10].wakeup_ports[3].bits.uop.iq_type[2] connect slots_10.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[10].wakeup_ports[3].bits.uop.iq_type[3] connect slots_10.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[10].wakeup_ports[3].bits.uop.debug_pc connect slots_10.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[10].wakeup_ports[3].bits.uop.is_rvc connect slots_10.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[10].wakeup_ports[3].bits.uop.debug_inst connect slots_10.io.wakeup_ports[3].bits.uop.inst, issue_slots[10].wakeup_ports[3].bits.uop.inst connect slots_10.io.wakeup_ports[3].valid, issue_slots[10].wakeup_ports[3].valid connect slots_10.io.wakeup_ports[4].bits.rebusy, issue_slots[10].wakeup_ports[4].bits.rebusy connect slots_10.io.wakeup_ports[4].bits.speculative_mask, issue_slots[10].wakeup_ports[4].bits.speculative_mask connect slots_10.io.wakeup_ports[4].bits.bypassable, issue_slots[10].wakeup_ports[4].bits.bypassable connect slots_10.io.wakeup_ports[4].bits.uop.debug_tsrc, issue_slots[10].wakeup_ports[4].bits.uop.debug_tsrc connect slots_10.io.wakeup_ports[4].bits.uop.debug_fsrc, issue_slots[10].wakeup_ports[4].bits.uop.debug_fsrc connect slots_10.io.wakeup_ports[4].bits.uop.bp_xcpt_if, issue_slots[10].wakeup_ports[4].bits.uop.bp_xcpt_if connect slots_10.io.wakeup_ports[4].bits.uop.bp_debug_if, issue_slots[10].wakeup_ports[4].bits.uop.bp_debug_if connect slots_10.io.wakeup_ports[4].bits.uop.xcpt_ma_if, issue_slots[10].wakeup_ports[4].bits.uop.xcpt_ma_if connect slots_10.io.wakeup_ports[4].bits.uop.xcpt_ae_if, issue_slots[10].wakeup_ports[4].bits.uop.xcpt_ae_if connect slots_10.io.wakeup_ports[4].bits.uop.xcpt_pf_if, issue_slots[10].wakeup_ports[4].bits.uop.xcpt_pf_if connect slots_10.io.wakeup_ports[4].bits.uop.fp_typ, issue_slots[10].wakeup_ports[4].bits.uop.fp_typ connect slots_10.io.wakeup_ports[4].bits.uop.fp_rm, issue_slots[10].wakeup_ports[4].bits.uop.fp_rm connect slots_10.io.wakeup_ports[4].bits.uop.fp_val, issue_slots[10].wakeup_ports[4].bits.uop.fp_val connect slots_10.io.wakeup_ports[4].bits.uop.fcn_op, issue_slots[10].wakeup_ports[4].bits.uop.fcn_op connect slots_10.io.wakeup_ports[4].bits.uop.fcn_dw, issue_slots[10].wakeup_ports[4].bits.uop.fcn_dw connect slots_10.io.wakeup_ports[4].bits.uop.frs3_en, issue_slots[10].wakeup_ports[4].bits.uop.frs3_en connect slots_10.io.wakeup_ports[4].bits.uop.lrs2_rtype, issue_slots[10].wakeup_ports[4].bits.uop.lrs2_rtype connect slots_10.io.wakeup_ports[4].bits.uop.lrs1_rtype, issue_slots[10].wakeup_ports[4].bits.uop.lrs1_rtype connect slots_10.io.wakeup_ports[4].bits.uop.dst_rtype, issue_slots[10].wakeup_ports[4].bits.uop.dst_rtype connect slots_10.io.wakeup_ports[4].bits.uop.lrs3, issue_slots[10].wakeup_ports[4].bits.uop.lrs3 connect slots_10.io.wakeup_ports[4].bits.uop.lrs2, issue_slots[10].wakeup_ports[4].bits.uop.lrs2 connect slots_10.io.wakeup_ports[4].bits.uop.lrs1, issue_slots[10].wakeup_ports[4].bits.uop.lrs1 connect slots_10.io.wakeup_ports[4].bits.uop.ldst, issue_slots[10].wakeup_ports[4].bits.uop.ldst connect slots_10.io.wakeup_ports[4].bits.uop.ldst_is_rs1, issue_slots[10].wakeup_ports[4].bits.uop.ldst_is_rs1 connect slots_10.io.wakeup_ports[4].bits.uop.csr_cmd, issue_slots[10].wakeup_ports[4].bits.uop.csr_cmd connect slots_10.io.wakeup_ports[4].bits.uop.flush_on_commit, issue_slots[10].wakeup_ports[4].bits.uop.flush_on_commit connect slots_10.io.wakeup_ports[4].bits.uop.is_unique, issue_slots[10].wakeup_ports[4].bits.uop.is_unique connect slots_10.io.wakeup_ports[4].bits.uop.uses_stq, issue_slots[10].wakeup_ports[4].bits.uop.uses_stq connect slots_10.io.wakeup_ports[4].bits.uop.uses_ldq, issue_slots[10].wakeup_ports[4].bits.uop.uses_ldq connect slots_10.io.wakeup_ports[4].bits.uop.mem_signed, issue_slots[10].wakeup_ports[4].bits.uop.mem_signed connect slots_10.io.wakeup_ports[4].bits.uop.mem_size, issue_slots[10].wakeup_ports[4].bits.uop.mem_size connect slots_10.io.wakeup_ports[4].bits.uop.mem_cmd, issue_slots[10].wakeup_ports[4].bits.uop.mem_cmd connect slots_10.io.wakeup_ports[4].bits.uop.exc_cause, issue_slots[10].wakeup_ports[4].bits.uop.exc_cause connect slots_10.io.wakeup_ports[4].bits.uop.exception, issue_slots[10].wakeup_ports[4].bits.uop.exception connect slots_10.io.wakeup_ports[4].bits.uop.stale_pdst, issue_slots[10].wakeup_ports[4].bits.uop.stale_pdst connect slots_10.io.wakeup_ports[4].bits.uop.ppred_busy, issue_slots[10].wakeup_ports[4].bits.uop.ppred_busy connect slots_10.io.wakeup_ports[4].bits.uop.prs3_busy, issue_slots[10].wakeup_ports[4].bits.uop.prs3_busy connect slots_10.io.wakeup_ports[4].bits.uop.prs2_busy, issue_slots[10].wakeup_ports[4].bits.uop.prs2_busy connect slots_10.io.wakeup_ports[4].bits.uop.prs1_busy, issue_slots[10].wakeup_ports[4].bits.uop.prs1_busy connect slots_10.io.wakeup_ports[4].bits.uop.ppred, issue_slots[10].wakeup_ports[4].bits.uop.ppred connect slots_10.io.wakeup_ports[4].bits.uop.prs3, issue_slots[10].wakeup_ports[4].bits.uop.prs3 connect slots_10.io.wakeup_ports[4].bits.uop.prs2, issue_slots[10].wakeup_ports[4].bits.uop.prs2 connect slots_10.io.wakeup_ports[4].bits.uop.prs1, issue_slots[10].wakeup_ports[4].bits.uop.prs1 connect slots_10.io.wakeup_ports[4].bits.uop.pdst, issue_slots[10].wakeup_ports[4].bits.uop.pdst connect slots_10.io.wakeup_ports[4].bits.uop.rxq_idx, issue_slots[10].wakeup_ports[4].bits.uop.rxq_idx connect slots_10.io.wakeup_ports[4].bits.uop.stq_idx, issue_slots[10].wakeup_ports[4].bits.uop.stq_idx connect slots_10.io.wakeup_ports[4].bits.uop.ldq_idx, issue_slots[10].wakeup_ports[4].bits.uop.ldq_idx connect slots_10.io.wakeup_ports[4].bits.uop.rob_idx, issue_slots[10].wakeup_ports[4].bits.uop.rob_idx connect slots_10.io.wakeup_ports[4].bits.uop.fp_ctrl.vec, issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.vec connect slots_10.io.wakeup_ports[4].bits.uop.fp_ctrl.wflags, issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.wflags connect slots_10.io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt, issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect slots_10.io.wakeup_ports[4].bits.uop.fp_ctrl.div, issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.div connect slots_10.io.wakeup_ports[4].bits.uop.fp_ctrl.fma, issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.fma connect slots_10.io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect slots_10.io.wakeup_ports[4].bits.uop.fp_ctrl.toint, issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.toint connect slots_10.io.wakeup_ports[4].bits.uop.fp_ctrl.fromint, issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.fromint connect slots_10.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect slots_10.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect slots_10.io.wakeup_ports[4].bits.uop.fp_ctrl.swap23, issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect slots_10.io.wakeup_ports[4].bits.uop.fp_ctrl.swap12, issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect slots_10.io.wakeup_ports[4].bits.uop.fp_ctrl.ren3, issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect slots_10.io.wakeup_ports[4].bits.uop.fp_ctrl.ren2, issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect slots_10.io.wakeup_ports[4].bits.uop.fp_ctrl.ren1, issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect slots_10.io.wakeup_ports[4].bits.uop.fp_ctrl.wen, issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.wen connect slots_10.io.wakeup_ports[4].bits.uop.fp_ctrl.ldst, issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.ldst connect slots_10.io.wakeup_ports[4].bits.uop.op2_sel, issue_slots[10].wakeup_ports[4].bits.uop.op2_sel connect slots_10.io.wakeup_ports[4].bits.uop.op1_sel, issue_slots[10].wakeup_ports[4].bits.uop.op1_sel connect slots_10.io.wakeup_ports[4].bits.uop.imm_packed, issue_slots[10].wakeup_ports[4].bits.uop.imm_packed connect slots_10.io.wakeup_ports[4].bits.uop.pimm, issue_slots[10].wakeup_ports[4].bits.uop.pimm connect slots_10.io.wakeup_ports[4].bits.uop.imm_sel, issue_slots[10].wakeup_ports[4].bits.uop.imm_sel connect slots_10.io.wakeup_ports[4].bits.uop.imm_rename, issue_slots[10].wakeup_ports[4].bits.uop.imm_rename connect slots_10.io.wakeup_ports[4].bits.uop.taken, issue_slots[10].wakeup_ports[4].bits.uop.taken connect slots_10.io.wakeup_ports[4].bits.uop.pc_lob, issue_slots[10].wakeup_ports[4].bits.uop.pc_lob connect slots_10.io.wakeup_ports[4].bits.uop.edge_inst, issue_slots[10].wakeup_ports[4].bits.uop.edge_inst connect slots_10.io.wakeup_ports[4].bits.uop.ftq_idx, issue_slots[10].wakeup_ports[4].bits.uop.ftq_idx connect slots_10.io.wakeup_ports[4].bits.uop.is_mov, issue_slots[10].wakeup_ports[4].bits.uop.is_mov connect slots_10.io.wakeup_ports[4].bits.uop.is_rocc, issue_slots[10].wakeup_ports[4].bits.uop.is_rocc connect slots_10.io.wakeup_ports[4].bits.uop.is_sys_pc2epc, issue_slots[10].wakeup_ports[4].bits.uop.is_sys_pc2epc connect slots_10.io.wakeup_ports[4].bits.uop.is_eret, issue_slots[10].wakeup_ports[4].bits.uop.is_eret connect slots_10.io.wakeup_ports[4].bits.uop.is_amo, issue_slots[10].wakeup_ports[4].bits.uop.is_amo connect slots_10.io.wakeup_ports[4].bits.uop.is_sfence, issue_slots[10].wakeup_ports[4].bits.uop.is_sfence connect slots_10.io.wakeup_ports[4].bits.uop.is_fencei, issue_slots[10].wakeup_ports[4].bits.uop.is_fencei connect slots_10.io.wakeup_ports[4].bits.uop.is_fence, issue_slots[10].wakeup_ports[4].bits.uop.is_fence connect slots_10.io.wakeup_ports[4].bits.uop.is_sfb, issue_slots[10].wakeup_ports[4].bits.uop.is_sfb connect slots_10.io.wakeup_ports[4].bits.uop.br_type, issue_slots[10].wakeup_ports[4].bits.uop.br_type connect slots_10.io.wakeup_ports[4].bits.uop.br_tag, issue_slots[10].wakeup_ports[4].bits.uop.br_tag connect slots_10.io.wakeup_ports[4].bits.uop.br_mask, issue_slots[10].wakeup_ports[4].bits.uop.br_mask connect slots_10.io.wakeup_ports[4].bits.uop.dis_col_sel, issue_slots[10].wakeup_ports[4].bits.uop.dis_col_sel connect slots_10.io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint, issue_slots[10].wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect slots_10.io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint, issue_slots[10].wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect slots_10.io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint, issue_slots[10].wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect slots_10.io.wakeup_ports[4].bits.uop.iw_p2_speculative_child, issue_slots[10].wakeup_ports[4].bits.uop.iw_p2_speculative_child connect slots_10.io.wakeup_ports[4].bits.uop.iw_p1_speculative_child, issue_slots[10].wakeup_ports[4].bits.uop.iw_p1_speculative_child connect slots_10.io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen, issue_slots[10].wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect slots_10.io.wakeup_ports[4].bits.uop.iw_issued_partial_agen, issue_slots[10].wakeup_ports[4].bits.uop.iw_issued_partial_agen connect slots_10.io.wakeup_ports[4].bits.uop.iw_issued, issue_slots[10].wakeup_ports[4].bits.uop.iw_issued connect slots_10.io.wakeup_ports[4].bits.uop.fu_code[0], issue_slots[10].wakeup_ports[4].bits.uop.fu_code[0] connect slots_10.io.wakeup_ports[4].bits.uop.fu_code[1], issue_slots[10].wakeup_ports[4].bits.uop.fu_code[1] connect slots_10.io.wakeup_ports[4].bits.uop.fu_code[2], issue_slots[10].wakeup_ports[4].bits.uop.fu_code[2] connect slots_10.io.wakeup_ports[4].bits.uop.fu_code[3], issue_slots[10].wakeup_ports[4].bits.uop.fu_code[3] connect slots_10.io.wakeup_ports[4].bits.uop.fu_code[4], issue_slots[10].wakeup_ports[4].bits.uop.fu_code[4] connect slots_10.io.wakeup_ports[4].bits.uop.fu_code[5], issue_slots[10].wakeup_ports[4].bits.uop.fu_code[5] connect slots_10.io.wakeup_ports[4].bits.uop.fu_code[6], issue_slots[10].wakeup_ports[4].bits.uop.fu_code[6] connect slots_10.io.wakeup_ports[4].bits.uop.fu_code[7], issue_slots[10].wakeup_ports[4].bits.uop.fu_code[7] connect slots_10.io.wakeup_ports[4].bits.uop.fu_code[8], issue_slots[10].wakeup_ports[4].bits.uop.fu_code[8] connect slots_10.io.wakeup_ports[4].bits.uop.fu_code[9], issue_slots[10].wakeup_ports[4].bits.uop.fu_code[9] connect slots_10.io.wakeup_ports[4].bits.uop.iq_type[0], issue_slots[10].wakeup_ports[4].bits.uop.iq_type[0] connect slots_10.io.wakeup_ports[4].bits.uop.iq_type[1], issue_slots[10].wakeup_ports[4].bits.uop.iq_type[1] connect slots_10.io.wakeup_ports[4].bits.uop.iq_type[2], issue_slots[10].wakeup_ports[4].bits.uop.iq_type[2] connect slots_10.io.wakeup_ports[4].bits.uop.iq_type[3], issue_slots[10].wakeup_ports[4].bits.uop.iq_type[3] connect slots_10.io.wakeup_ports[4].bits.uop.debug_pc, issue_slots[10].wakeup_ports[4].bits.uop.debug_pc connect slots_10.io.wakeup_ports[4].bits.uop.is_rvc, issue_slots[10].wakeup_ports[4].bits.uop.is_rvc connect slots_10.io.wakeup_ports[4].bits.uop.debug_inst, issue_slots[10].wakeup_ports[4].bits.uop.debug_inst connect slots_10.io.wakeup_ports[4].bits.uop.inst, issue_slots[10].wakeup_ports[4].bits.uop.inst connect slots_10.io.wakeup_ports[4].valid, issue_slots[10].wakeup_ports[4].valid connect slots_10.io.squash_grant, issue_slots[10].squash_grant connect slots_10.io.clear, issue_slots[10].clear connect slots_10.io.kill, issue_slots[10].kill connect slots_10.io.brupdate.b2.target_offset, issue_slots[10].brupdate.b2.target_offset connect slots_10.io.brupdate.b2.jalr_target, issue_slots[10].brupdate.b2.jalr_target connect slots_10.io.brupdate.b2.pc_sel, issue_slots[10].brupdate.b2.pc_sel connect slots_10.io.brupdate.b2.cfi_type, issue_slots[10].brupdate.b2.cfi_type connect slots_10.io.brupdate.b2.taken, issue_slots[10].brupdate.b2.taken connect slots_10.io.brupdate.b2.mispredict, issue_slots[10].brupdate.b2.mispredict connect slots_10.io.brupdate.b2.uop.debug_tsrc, issue_slots[10].brupdate.b2.uop.debug_tsrc connect slots_10.io.brupdate.b2.uop.debug_fsrc, issue_slots[10].brupdate.b2.uop.debug_fsrc connect slots_10.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[10].brupdate.b2.uop.bp_xcpt_if connect slots_10.io.brupdate.b2.uop.bp_debug_if, issue_slots[10].brupdate.b2.uop.bp_debug_if connect slots_10.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[10].brupdate.b2.uop.xcpt_ma_if connect slots_10.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[10].brupdate.b2.uop.xcpt_ae_if connect slots_10.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[10].brupdate.b2.uop.xcpt_pf_if connect slots_10.io.brupdate.b2.uop.fp_typ, issue_slots[10].brupdate.b2.uop.fp_typ connect slots_10.io.brupdate.b2.uop.fp_rm, issue_slots[10].brupdate.b2.uop.fp_rm connect slots_10.io.brupdate.b2.uop.fp_val, issue_slots[10].brupdate.b2.uop.fp_val connect slots_10.io.brupdate.b2.uop.fcn_op, issue_slots[10].brupdate.b2.uop.fcn_op connect slots_10.io.brupdate.b2.uop.fcn_dw, issue_slots[10].brupdate.b2.uop.fcn_dw connect slots_10.io.brupdate.b2.uop.frs3_en, issue_slots[10].brupdate.b2.uop.frs3_en connect slots_10.io.brupdate.b2.uop.lrs2_rtype, issue_slots[10].brupdate.b2.uop.lrs2_rtype connect slots_10.io.brupdate.b2.uop.lrs1_rtype, issue_slots[10].brupdate.b2.uop.lrs1_rtype connect slots_10.io.brupdate.b2.uop.dst_rtype, issue_slots[10].brupdate.b2.uop.dst_rtype connect slots_10.io.brupdate.b2.uop.lrs3, issue_slots[10].brupdate.b2.uop.lrs3 connect slots_10.io.brupdate.b2.uop.lrs2, issue_slots[10].brupdate.b2.uop.lrs2 connect slots_10.io.brupdate.b2.uop.lrs1, issue_slots[10].brupdate.b2.uop.lrs1 connect slots_10.io.brupdate.b2.uop.ldst, issue_slots[10].brupdate.b2.uop.ldst connect slots_10.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[10].brupdate.b2.uop.ldst_is_rs1 connect slots_10.io.brupdate.b2.uop.csr_cmd, issue_slots[10].brupdate.b2.uop.csr_cmd connect slots_10.io.brupdate.b2.uop.flush_on_commit, issue_slots[10].brupdate.b2.uop.flush_on_commit connect slots_10.io.brupdate.b2.uop.is_unique, issue_slots[10].brupdate.b2.uop.is_unique connect slots_10.io.brupdate.b2.uop.uses_stq, issue_slots[10].brupdate.b2.uop.uses_stq connect slots_10.io.brupdate.b2.uop.uses_ldq, issue_slots[10].brupdate.b2.uop.uses_ldq connect slots_10.io.brupdate.b2.uop.mem_signed, issue_slots[10].brupdate.b2.uop.mem_signed connect slots_10.io.brupdate.b2.uop.mem_size, issue_slots[10].brupdate.b2.uop.mem_size connect slots_10.io.brupdate.b2.uop.mem_cmd, issue_slots[10].brupdate.b2.uop.mem_cmd connect slots_10.io.brupdate.b2.uop.exc_cause, issue_slots[10].brupdate.b2.uop.exc_cause connect slots_10.io.brupdate.b2.uop.exception, issue_slots[10].brupdate.b2.uop.exception connect slots_10.io.brupdate.b2.uop.stale_pdst, issue_slots[10].brupdate.b2.uop.stale_pdst connect slots_10.io.brupdate.b2.uop.ppred_busy, issue_slots[10].brupdate.b2.uop.ppred_busy connect slots_10.io.brupdate.b2.uop.prs3_busy, issue_slots[10].brupdate.b2.uop.prs3_busy connect slots_10.io.brupdate.b2.uop.prs2_busy, issue_slots[10].brupdate.b2.uop.prs2_busy connect slots_10.io.brupdate.b2.uop.prs1_busy, issue_slots[10].brupdate.b2.uop.prs1_busy connect slots_10.io.brupdate.b2.uop.ppred, issue_slots[10].brupdate.b2.uop.ppred connect slots_10.io.brupdate.b2.uop.prs3, issue_slots[10].brupdate.b2.uop.prs3 connect slots_10.io.brupdate.b2.uop.prs2, issue_slots[10].brupdate.b2.uop.prs2 connect slots_10.io.brupdate.b2.uop.prs1, issue_slots[10].brupdate.b2.uop.prs1 connect slots_10.io.brupdate.b2.uop.pdst, issue_slots[10].brupdate.b2.uop.pdst connect slots_10.io.brupdate.b2.uop.rxq_idx, issue_slots[10].brupdate.b2.uop.rxq_idx connect slots_10.io.brupdate.b2.uop.stq_idx, issue_slots[10].brupdate.b2.uop.stq_idx connect slots_10.io.brupdate.b2.uop.ldq_idx, issue_slots[10].brupdate.b2.uop.ldq_idx connect slots_10.io.brupdate.b2.uop.rob_idx, issue_slots[10].brupdate.b2.uop.rob_idx connect slots_10.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[10].brupdate.b2.uop.fp_ctrl.vec connect slots_10.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[10].brupdate.b2.uop.fp_ctrl.wflags connect slots_10.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[10].brupdate.b2.uop.fp_ctrl.sqrt connect slots_10.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[10].brupdate.b2.uop.fp_ctrl.div connect slots_10.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[10].brupdate.b2.uop.fp_ctrl.fma connect slots_10.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[10].brupdate.b2.uop.fp_ctrl.fastpipe connect slots_10.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[10].brupdate.b2.uop.fp_ctrl.toint connect slots_10.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[10].brupdate.b2.uop.fp_ctrl.fromint connect slots_10.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[10].brupdate.b2.uop.fp_ctrl.typeTagOut connect slots_10.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[10].brupdate.b2.uop.fp_ctrl.typeTagIn connect slots_10.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[10].brupdate.b2.uop.fp_ctrl.swap23 connect slots_10.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[10].brupdate.b2.uop.fp_ctrl.swap12 connect slots_10.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[10].brupdate.b2.uop.fp_ctrl.ren3 connect slots_10.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[10].brupdate.b2.uop.fp_ctrl.ren2 connect slots_10.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[10].brupdate.b2.uop.fp_ctrl.ren1 connect slots_10.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[10].brupdate.b2.uop.fp_ctrl.wen connect slots_10.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[10].brupdate.b2.uop.fp_ctrl.ldst connect slots_10.io.brupdate.b2.uop.op2_sel, issue_slots[10].brupdate.b2.uop.op2_sel connect slots_10.io.brupdate.b2.uop.op1_sel, issue_slots[10].brupdate.b2.uop.op1_sel connect slots_10.io.brupdate.b2.uop.imm_packed, issue_slots[10].brupdate.b2.uop.imm_packed connect slots_10.io.brupdate.b2.uop.pimm, issue_slots[10].brupdate.b2.uop.pimm connect slots_10.io.brupdate.b2.uop.imm_sel, issue_slots[10].brupdate.b2.uop.imm_sel connect slots_10.io.brupdate.b2.uop.imm_rename, issue_slots[10].brupdate.b2.uop.imm_rename connect slots_10.io.brupdate.b2.uop.taken, issue_slots[10].brupdate.b2.uop.taken connect slots_10.io.brupdate.b2.uop.pc_lob, issue_slots[10].brupdate.b2.uop.pc_lob connect slots_10.io.brupdate.b2.uop.edge_inst, issue_slots[10].brupdate.b2.uop.edge_inst connect slots_10.io.brupdate.b2.uop.ftq_idx, issue_slots[10].brupdate.b2.uop.ftq_idx connect slots_10.io.brupdate.b2.uop.is_mov, issue_slots[10].brupdate.b2.uop.is_mov connect slots_10.io.brupdate.b2.uop.is_rocc, issue_slots[10].brupdate.b2.uop.is_rocc connect slots_10.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[10].brupdate.b2.uop.is_sys_pc2epc connect slots_10.io.brupdate.b2.uop.is_eret, issue_slots[10].brupdate.b2.uop.is_eret connect slots_10.io.brupdate.b2.uop.is_amo, issue_slots[10].brupdate.b2.uop.is_amo connect slots_10.io.brupdate.b2.uop.is_sfence, issue_slots[10].brupdate.b2.uop.is_sfence connect slots_10.io.brupdate.b2.uop.is_fencei, issue_slots[10].brupdate.b2.uop.is_fencei connect slots_10.io.brupdate.b2.uop.is_fence, issue_slots[10].brupdate.b2.uop.is_fence connect slots_10.io.brupdate.b2.uop.is_sfb, issue_slots[10].brupdate.b2.uop.is_sfb connect slots_10.io.brupdate.b2.uop.br_type, issue_slots[10].brupdate.b2.uop.br_type connect slots_10.io.brupdate.b2.uop.br_tag, issue_slots[10].brupdate.b2.uop.br_tag connect slots_10.io.brupdate.b2.uop.br_mask, issue_slots[10].brupdate.b2.uop.br_mask connect slots_10.io.brupdate.b2.uop.dis_col_sel, issue_slots[10].brupdate.b2.uop.dis_col_sel connect slots_10.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[10].brupdate.b2.uop.iw_p3_bypass_hint connect slots_10.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[10].brupdate.b2.uop.iw_p2_bypass_hint connect slots_10.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[10].brupdate.b2.uop.iw_p1_bypass_hint connect slots_10.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[10].brupdate.b2.uop.iw_p2_speculative_child connect slots_10.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[10].brupdate.b2.uop.iw_p1_speculative_child connect slots_10.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[10].brupdate.b2.uop.iw_issued_partial_dgen connect slots_10.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[10].brupdate.b2.uop.iw_issued_partial_agen connect slots_10.io.brupdate.b2.uop.iw_issued, issue_slots[10].brupdate.b2.uop.iw_issued connect slots_10.io.brupdate.b2.uop.fu_code[0], issue_slots[10].brupdate.b2.uop.fu_code[0] connect slots_10.io.brupdate.b2.uop.fu_code[1], issue_slots[10].brupdate.b2.uop.fu_code[1] connect slots_10.io.brupdate.b2.uop.fu_code[2], issue_slots[10].brupdate.b2.uop.fu_code[2] connect slots_10.io.brupdate.b2.uop.fu_code[3], issue_slots[10].brupdate.b2.uop.fu_code[3] connect slots_10.io.brupdate.b2.uop.fu_code[4], issue_slots[10].brupdate.b2.uop.fu_code[4] connect slots_10.io.brupdate.b2.uop.fu_code[5], issue_slots[10].brupdate.b2.uop.fu_code[5] connect slots_10.io.brupdate.b2.uop.fu_code[6], issue_slots[10].brupdate.b2.uop.fu_code[6] connect slots_10.io.brupdate.b2.uop.fu_code[7], issue_slots[10].brupdate.b2.uop.fu_code[7] connect slots_10.io.brupdate.b2.uop.fu_code[8], issue_slots[10].brupdate.b2.uop.fu_code[8] connect slots_10.io.brupdate.b2.uop.fu_code[9], issue_slots[10].brupdate.b2.uop.fu_code[9] connect slots_10.io.brupdate.b2.uop.iq_type[0], issue_slots[10].brupdate.b2.uop.iq_type[0] connect slots_10.io.brupdate.b2.uop.iq_type[1], issue_slots[10].brupdate.b2.uop.iq_type[1] connect slots_10.io.brupdate.b2.uop.iq_type[2], issue_slots[10].brupdate.b2.uop.iq_type[2] connect slots_10.io.brupdate.b2.uop.iq_type[3], issue_slots[10].brupdate.b2.uop.iq_type[3] connect slots_10.io.brupdate.b2.uop.debug_pc, issue_slots[10].brupdate.b2.uop.debug_pc connect slots_10.io.brupdate.b2.uop.is_rvc, issue_slots[10].brupdate.b2.uop.is_rvc connect slots_10.io.brupdate.b2.uop.debug_inst, issue_slots[10].brupdate.b2.uop.debug_inst connect slots_10.io.brupdate.b2.uop.inst, issue_slots[10].brupdate.b2.uop.inst connect slots_10.io.brupdate.b1.mispredict_mask, issue_slots[10].brupdate.b1.mispredict_mask connect slots_10.io.brupdate.b1.resolve_mask, issue_slots[10].brupdate.b1.resolve_mask connect issue_slots[10].out_uop.debug_tsrc, slots_10.io.out_uop.debug_tsrc connect issue_slots[10].out_uop.debug_fsrc, slots_10.io.out_uop.debug_fsrc connect issue_slots[10].out_uop.bp_xcpt_if, slots_10.io.out_uop.bp_xcpt_if connect issue_slots[10].out_uop.bp_debug_if, slots_10.io.out_uop.bp_debug_if connect issue_slots[10].out_uop.xcpt_ma_if, slots_10.io.out_uop.xcpt_ma_if connect issue_slots[10].out_uop.xcpt_ae_if, slots_10.io.out_uop.xcpt_ae_if connect issue_slots[10].out_uop.xcpt_pf_if, slots_10.io.out_uop.xcpt_pf_if connect issue_slots[10].out_uop.fp_typ, slots_10.io.out_uop.fp_typ connect issue_slots[10].out_uop.fp_rm, slots_10.io.out_uop.fp_rm connect issue_slots[10].out_uop.fp_val, slots_10.io.out_uop.fp_val connect issue_slots[10].out_uop.fcn_op, slots_10.io.out_uop.fcn_op connect issue_slots[10].out_uop.fcn_dw, slots_10.io.out_uop.fcn_dw connect issue_slots[10].out_uop.frs3_en, slots_10.io.out_uop.frs3_en connect issue_slots[10].out_uop.lrs2_rtype, slots_10.io.out_uop.lrs2_rtype connect issue_slots[10].out_uop.lrs1_rtype, slots_10.io.out_uop.lrs1_rtype connect issue_slots[10].out_uop.dst_rtype, slots_10.io.out_uop.dst_rtype connect issue_slots[10].out_uop.lrs3, slots_10.io.out_uop.lrs3 connect issue_slots[10].out_uop.lrs2, slots_10.io.out_uop.lrs2 connect issue_slots[10].out_uop.lrs1, slots_10.io.out_uop.lrs1 connect issue_slots[10].out_uop.ldst, slots_10.io.out_uop.ldst connect issue_slots[10].out_uop.ldst_is_rs1, slots_10.io.out_uop.ldst_is_rs1 connect issue_slots[10].out_uop.csr_cmd, slots_10.io.out_uop.csr_cmd connect issue_slots[10].out_uop.flush_on_commit, slots_10.io.out_uop.flush_on_commit connect issue_slots[10].out_uop.is_unique, slots_10.io.out_uop.is_unique connect issue_slots[10].out_uop.uses_stq, slots_10.io.out_uop.uses_stq connect issue_slots[10].out_uop.uses_ldq, slots_10.io.out_uop.uses_ldq connect issue_slots[10].out_uop.mem_signed, slots_10.io.out_uop.mem_signed connect issue_slots[10].out_uop.mem_size, slots_10.io.out_uop.mem_size connect issue_slots[10].out_uop.mem_cmd, slots_10.io.out_uop.mem_cmd connect issue_slots[10].out_uop.exc_cause, slots_10.io.out_uop.exc_cause connect issue_slots[10].out_uop.exception, slots_10.io.out_uop.exception connect issue_slots[10].out_uop.stale_pdst, slots_10.io.out_uop.stale_pdst connect issue_slots[10].out_uop.ppred_busy, slots_10.io.out_uop.ppred_busy connect issue_slots[10].out_uop.prs3_busy, slots_10.io.out_uop.prs3_busy connect issue_slots[10].out_uop.prs2_busy, slots_10.io.out_uop.prs2_busy connect issue_slots[10].out_uop.prs1_busy, slots_10.io.out_uop.prs1_busy connect issue_slots[10].out_uop.ppred, slots_10.io.out_uop.ppred connect issue_slots[10].out_uop.prs3, slots_10.io.out_uop.prs3 connect issue_slots[10].out_uop.prs2, slots_10.io.out_uop.prs2 connect issue_slots[10].out_uop.prs1, slots_10.io.out_uop.prs1 connect issue_slots[10].out_uop.pdst, slots_10.io.out_uop.pdst connect issue_slots[10].out_uop.rxq_idx, slots_10.io.out_uop.rxq_idx connect issue_slots[10].out_uop.stq_idx, slots_10.io.out_uop.stq_idx connect issue_slots[10].out_uop.ldq_idx, slots_10.io.out_uop.ldq_idx connect issue_slots[10].out_uop.rob_idx, slots_10.io.out_uop.rob_idx connect issue_slots[10].out_uop.fp_ctrl.vec, slots_10.io.out_uop.fp_ctrl.vec connect issue_slots[10].out_uop.fp_ctrl.wflags, slots_10.io.out_uop.fp_ctrl.wflags connect issue_slots[10].out_uop.fp_ctrl.sqrt, slots_10.io.out_uop.fp_ctrl.sqrt connect issue_slots[10].out_uop.fp_ctrl.div, slots_10.io.out_uop.fp_ctrl.div connect issue_slots[10].out_uop.fp_ctrl.fma, slots_10.io.out_uop.fp_ctrl.fma connect issue_slots[10].out_uop.fp_ctrl.fastpipe, slots_10.io.out_uop.fp_ctrl.fastpipe connect issue_slots[10].out_uop.fp_ctrl.toint, slots_10.io.out_uop.fp_ctrl.toint connect issue_slots[10].out_uop.fp_ctrl.fromint, slots_10.io.out_uop.fp_ctrl.fromint connect issue_slots[10].out_uop.fp_ctrl.typeTagOut, slots_10.io.out_uop.fp_ctrl.typeTagOut connect issue_slots[10].out_uop.fp_ctrl.typeTagIn, slots_10.io.out_uop.fp_ctrl.typeTagIn connect issue_slots[10].out_uop.fp_ctrl.swap23, slots_10.io.out_uop.fp_ctrl.swap23 connect issue_slots[10].out_uop.fp_ctrl.swap12, slots_10.io.out_uop.fp_ctrl.swap12 connect issue_slots[10].out_uop.fp_ctrl.ren3, slots_10.io.out_uop.fp_ctrl.ren3 connect issue_slots[10].out_uop.fp_ctrl.ren2, slots_10.io.out_uop.fp_ctrl.ren2 connect issue_slots[10].out_uop.fp_ctrl.ren1, slots_10.io.out_uop.fp_ctrl.ren1 connect issue_slots[10].out_uop.fp_ctrl.wen, slots_10.io.out_uop.fp_ctrl.wen connect issue_slots[10].out_uop.fp_ctrl.ldst, slots_10.io.out_uop.fp_ctrl.ldst connect issue_slots[10].out_uop.op2_sel, slots_10.io.out_uop.op2_sel connect issue_slots[10].out_uop.op1_sel, slots_10.io.out_uop.op1_sel connect issue_slots[10].out_uop.imm_packed, slots_10.io.out_uop.imm_packed connect issue_slots[10].out_uop.pimm, slots_10.io.out_uop.pimm connect issue_slots[10].out_uop.imm_sel, slots_10.io.out_uop.imm_sel connect issue_slots[10].out_uop.imm_rename, slots_10.io.out_uop.imm_rename connect issue_slots[10].out_uop.taken, slots_10.io.out_uop.taken connect issue_slots[10].out_uop.pc_lob, slots_10.io.out_uop.pc_lob connect issue_slots[10].out_uop.edge_inst, slots_10.io.out_uop.edge_inst connect issue_slots[10].out_uop.ftq_idx, slots_10.io.out_uop.ftq_idx connect issue_slots[10].out_uop.is_mov, slots_10.io.out_uop.is_mov connect issue_slots[10].out_uop.is_rocc, slots_10.io.out_uop.is_rocc connect issue_slots[10].out_uop.is_sys_pc2epc, slots_10.io.out_uop.is_sys_pc2epc connect issue_slots[10].out_uop.is_eret, slots_10.io.out_uop.is_eret connect issue_slots[10].out_uop.is_amo, slots_10.io.out_uop.is_amo connect issue_slots[10].out_uop.is_sfence, slots_10.io.out_uop.is_sfence connect issue_slots[10].out_uop.is_fencei, slots_10.io.out_uop.is_fencei connect issue_slots[10].out_uop.is_fence, slots_10.io.out_uop.is_fence connect issue_slots[10].out_uop.is_sfb, slots_10.io.out_uop.is_sfb connect issue_slots[10].out_uop.br_type, slots_10.io.out_uop.br_type connect issue_slots[10].out_uop.br_tag, slots_10.io.out_uop.br_tag connect issue_slots[10].out_uop.br_mask, slots_10.io.out_uop.br_mask connect issue_slots[10].out_uop.dis_col_sel, slots_10.io.out_uop.dis_col_sel connect issue_slots[10].out_uop.iw_p3_bypass_hint, slots_10.io.out_uop.iw_p3_bypass_hint connect issue_slots[10].out_uop.iw_p2_bypass_hint, slots_10.io.out_uop.iw_p2_bypass_hint connect issue_slots[10].out_uop.iw_p1_bypass_hint, slots_10.io.out_uop.iw_p1_bypass_hint connect issue_slots[10].out_uop.iw_p2_speculative_child, slots_10.io.out_uop.iw_p2_speculative_child connect issue_slots[10].out_uop.iw_p1_speculative_child, slots_10.io.out_uop.iw_p1_speculative_child connect issue_slots[10].out_uop.iw_issued_partial_dgen, slots_10.io.out_uop.iw_issued_partial_dgen connect issue_slots[10].out_uop.iw_issued_partial_agen, slots_10.io.out_uop.iw_issued_partial_agen connect issue_slots[10].out_uop.iw_issued, slots_10.io.out_uop.iw_issued connect issue_slots[10].out_uop.fu_code[0], slots_10.io.out_uop.fu_code[0] connect issue_slots[10].out_uop.fu_code[1], slots_10.io.out_uop.fu_code[1] connect issue_slots[10].out_uop.fu_code[2], slots_10.io.out_uop.fu_code[2] connect issue_slots[10].out_uop.fu_code[3], slots_10.io.out_uop.fu_code[3] connect issue_slots[10].out_uop.fu_code[4], slots_10.io.out_uop.fu_code[4] connect issue_slots[10].out_uop.fu_code[5], slots_10.io.out_uop.fu_code[5] connect issue_slots[10].out_uop.fu_code[6], slots_10.io.out_uop.fu_code[6] connect issue_slots[10].out_uop.fu_code[7], slots_10.io.out_uop.fu_code[7] connect issue_slots[10].out_uop.fu_code[8], slots_10.io.out_uop.fu_code[8] connect issue_slots[10].out_uop.fu_code[9], slots_10.io.out_uop.fu_code[9] connect issue_slots[10].out_uop.iq_type[0], slots_10.io.out_uop.iq_type[0] connect issue_slots[10].out_uop.iq_type[1], slots_10.io.out_uop.iq_type[1] connect issue_slots[10].out_uop.iq_type[2], slots_10.io.out_uop.iq_type[2] connect issue_slots[10].out_uop.iq_type[3], slots_10.io.out_uop.iq_type[3] connect issue_slots[10].out_uop.debug_pc, slots_10.io.out_uop.debug_pc connect issue_slots[10].out_uop.is_rvc, slots_10.io.out_uop.is_rvc connect issue_slots[10].out_uop.debug_inst, slots_10.io.out_uop.debug_inst connect issue_slots[10].out_uop.inst, slots_10.io.out_uop.inst connect slots_10.io.in_uop.bits.debug_tsrc, issue_slots[10].in_uop.bits.debug_tsrc connect slots_10.io.in_uop.bits.debug_fsrc, issue_slots[10].in_uop.bits.debug_fsrc connect slots_10.io.in_uop.bits.bp_xcpt_if, issue_slots[10].in_uop.bits.bp_xcpt_if connect slots_10.io.in_uop.bits.bp_debug_if, issue_slots[10].in_uop.bits.bp_debug_if connect slots_10.io.in_uop.bits.xcpt_ma_if, issue_slots[10].in_uop.bits.xcpt_ma_if connect slots_10.io.in_uop.bits.xcpt_ae_if, issue_slots[10].in_uop.bits.xcpt_ae_if connect slots_10.io.in_uop.bits.xcpt_pf_if, issue_slots[10].in_uop.bits.xcpt_pf_if connect slots_10.io.in_uop.bits.fp_typ, issue_slots[10].in_uop.bits.fp_typ connect slots_10.io.in_uop.bits.fp_rm, issue_slots[10].in_uop.bits.fp_rm connect slots_10.io.in_uop.bits.fp_val, issue_slots[10].in_uop.bits.fp_val connect slots_10.io.in_uop.bits.fcn_op, issue_slots[10].in_uop.bits.fcn_op connect slots_10.io.in_uop.bits.fcn_dw, issue_slots[10].in_uop.bits.fcn_dw connect slots_10.io.in_uop.bits.frs3_en, issue_slots[10].in_uop.bits.frs3_en connect slots_10.io.in_uop.bits.lrs2_rtype, issue_slots[10].in_uop.bits.lrs2_rtype connect slots_10.io.in_uop.bits.lrs1_rtype, issue_slots[10].in_uop.bits.lrs1_rtype connect slots_10.io.in_uop.bits.dst_rtype, issue_slots[10].in_uop.bits.dst_rtype connect slots_10.io.in_uop.bits.lrs3, issue_slots[10].in_uop.bits.lrs3 connect slots_10.io.in_uop.bits.lrs2, issue_slots[10].in_uop.bits.lrs2 connect slots_10.io.in_uop.bits.lrs1, issue_slots[10].in_uop.bits.lrs1 connect slots_10.io.in_uop.bits.ldst, issue_slots[10].in_uop.bits.ldst connect slots_10.io.in_uop.bits.ldst_is_rs1, issue_slots[10].in_uop.bits.ldst_is_rs1 connect slots_10.io.in_uop.bits.csr_cmd, issue_slots[10].in_uop.bits.csr_cmd connect slots_10.io.in_uop.bits.flush_on_commit, issue_slots[10].in_uop.bits.flush_on_commit connect slots_10.io.in_uop.bits.is_unique, issue_slots[10].in_uop.bits.is_unique connect slots_10.io.in_uop.bits.uses_stq, issue_slots[10].in_uop.bits.uses_stq connect slots_10.io.in_uop.bits.uses_ldq, issue_slots[10].in_uop.bits.uses_ldq connect slots_10.io.in_uop.bits.mem_signed, issue_slots[10].in_uop.bits.mem_signed connect slots_10.io.in_uop.bits.mem_size, issue_slots[10].in_uop.bits.mem_size connect slots_10.io.in_uop.bits.mem_cmd, issue_slots[10].in_uop.bits.mem_cmd connect slots_10.io.in_uop.bits.exc_cause, issue_slots[10].in_uop.bits.exc_cause connect slots_10.io.in_uop.bits.exception, issue_slots[10].in_uop.bits.exception connect slots_10.io.in_uop.bits.stale_pdst, issue_slots[10].in_uop.bits.stale_pdst connect slots_10.io.in_uop.bits.ppred_busy, issue_slots[10].in_uop.bits.ppred_busy connect slots_10.io.in_uop.bits.prs3_busy, issue_slots[10].in_uop.bits.prs3_busy connect slots_10.io.in_uop.bits.prs2_busy, issue_slots[10].in_uop.bits.prs2_busy connect slots_10.io.in_uop.bits.prs1_busy, issue_slots[10].in_uop.bits.prs1_busy connect slots_10.io.in_uop.bits.ppred, issue_slots[10].in_uop.bits.ppred connect slots_10.io.in_uop.bits.prs3, issue_slots[10].in_uop.bits.prs3 connect slots_10.io.in_uop.bits.prs2, issue_slots[10].in_uop.bits.prs2 connect slots_10.io.in_uop.bits.prs1, issue_slots[10].in_uop.bits.prs1 connect slots_10.io.in_uop.bits.pdst, issue_slots[10].in_uop.bits.pdst connect slots_10.io.in_uop.bits.rxq_idx, issue_slots[10].in_uop.bits.rxq_idx connect slots_10.io.in_uop.bits.stq_idx, issue_slots[10].in_uop.bits.stq_idx connect slots_10.io.in_uop.bits.ldq_idx, issue_slots[10].in_uop.bits.ldq_idx connect slots_10.io.in_uop.bits.rob_idx, issue_slots[10].in_uop.bits.rob_idx connect slots_10.io.in_uop.bits.fp_ctrl.vec, issue_slots[10].in_uop.bits.fp_ctrl.vec connect slots_10.io.in_uop.bits.fp_ctrl.wflags, issue_slots[10].in_uop.bits.fp_ctrl.wflags connect slots_10.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[10].in_uop.bits.fp_ctrl.sqrt connect slots_10.io.in_uop.bits.fp_ctrl.div, issue_slots[10].in_uop.bits.fp_ctrl.div connect slots_10.io.in_uop.bits.fp_ctrl.fma, issue_slots[10].in_uop.bits.fp_ctrl.fma connect slots_10.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[10].in_uop.bits.fp_ctrl.fastpipe connect slots_10.io.in_uop.bits.fp_ctrl.toint, issue_slots[10].in_uop.bits.fp_ctrl.toint connect slots_10.io.in_uop.bits.fp_ctrl.fromint, issue_slots[10].in_uop.bits.fp_ctrl.fromint connect slots_10.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[10].in_uop.bits.fp_ctrl.typeTagOut connect slots_10.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[10].in_uop.bits.fp_ctrl.typeTagIn connect slots_10.io.in_uop.bits.fp_ctrl.swap23, issue_slots[10].in_uop.bits.fp_ctrl.swap23 connect slots_10.io.in_uop.bits.fp_ctrl.swap12, issue_slots[10].in_uop.bits.fp_ctrl.swap12 connect slots_10.io.in_uop.bits.fp_ctrl.ren3, issue_slots[10].in_uop.bits.fp_ctrl.ren3 connect slots_10.io.in_uop.bits.fp_ctrl.ren2, issue_slots[10].in_uop.bits.fp_ctrl.ren2 connect slots_10.io.in_uop.bits.fp_ctrl.ren1, issue_slots[10].in_uop.bits.fp_ctrl.ren1 connect slots_10.io.in_uop.bits.fp_ctrl.wen, issue_slots[10].in_uop.bits.fp_ctrl.wen connect slots_10.io.in_uop.bits.fp_ctrl.ldst, issue_slots[10].in_uop.bits.fp_ctrl.ldst connect slots_10.io.in_uop.bits.op2_sel, issue_slots[10].in_uop.bits.op2_sel connect slots_10.io.in_uop.bits.op1_sel, issue_slots[10].in_uop.bits.op1_sel connect slots_10.io.in_uop.bits.imm_packed, issue_slots[10].in_uop.bits.imm_packed connect slots_10.io.in_uop.bits.pimm, issue_slots[10].in_uop.bits.pimm connect slots_10.io.in_uop.bits.imm_sel, issue_slots[10].in_uop.bits.imm_sel connect slots_10.io.in_uop.bits.imm_rename, issue_slots[10].in_uop.bits.imm_rename connect slots_10.io.in_uop.bits.taken, issue_slots[10].in_uop.bits.taken connect slots_10.io.in_uop.bits.pc_lob, issue_slots[10].in_uop.bits.pc_lob connect slots_10.io.in_uop.bits.edge_inst, issue_slots[10].in_uop.bits.edge_inst connect slots_10.io.in_uop.bits.ftq_idx, issue_slots[10].in_uop.bits.ftq_idx connect slots_10.io.in_uop.bits.is_mov, issue_slots[10].in_uop.bits.is_mov connect slots_10.io.in_uop.bits.is_rocc, issue_slots[10].in_uop.bits.is_rocc connect slots_10.io.in_uop.bits.is_sys_pc2epc, issue_slots[10].in_uop.bits.is_sys_pc2epc connect slots_10.io.in_uop.bits.is_eret, issue_slots[10].in_uop.bits.is_eret connect slots_10.io.in_uop.bits.is_amo, issue_slots[10].in_uop.bits.is_amo connect slots_10.io.in_uop.bits.is_sfence, issue_slots[10].in_uop.bits.is_sfence connect slots_10.io.in_uop.bits.is_fencei, issue_slots[10].in_uop.bits.is_fencei connect slots_10.io.in_uop.bits.is_fence, issue_slots[10].in_uop.bits.is_fence connect slots_10.io.in_uop.bits.is_sfb, issue_slots[10].in_uop.bits.is_sfb connect slots_10.io.in_uop.bits.br_type, issue_slots[10].in_uop.bits.br_type connect slots_10.io.in_uop.bits.br_tag, issue_slots[10].in_uop.bits.br_tag connect slots_10.io.in_uop.bits.br_mask, issue_slots[10].in_uop.bits.br_mask connect slots_10.io.in_uop.bits.dis_col_sel, issue_slots[10].in_uop.bits.dis_col_sel connect slots_10.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[10].in_uop.bits.iw_p3_bypass_hint connect slots_10.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[10].in_uop.bits.iw_p2_bypass_hint connect slots_10.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[10].in_uop.bits.iw_p1_bypass_hint connect slots_10.io.in_uop.bits.iw_p2_speculative_child, issue_slots[10].in_uop.bits.iw_p2_speculative_child connect slots_10.io.in_uop.bits.iw_p1_speculative_child, issue_slots[10].in_uop.bits.iw_p1_speculative_child connect slots_10.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[10].in_uop.bits.iw_issued_partial_dgen connect slots_10.io.in_uop.bits.iw_issued_partial_agen, issue_slots[10].in_uop.bits.iw_issued_partial_agen connect slots_10.io.in_uop.bits.iw_issued, issue_slots[10].in_uop.bits.iw_issued connect slots_10.io.in_uop.bits.fu_code[0], issue_slots[10].in_uop.bits.fu_code[0] connect slots_10.io.in_uop.bits.fu_code[1], issue_slots[10].in_uop.bits.fu_code[1] connect slots_10.io.in_uop.bits.fu_code[2], issue_slots[10].in_uop.bits.fu_code[2] connect slots_10.io.in_uop.bits.fu_code[3], issue_slots[10].in_uop.bits.fu_code[3] connect slots_10.io.in_uop.bits.fu_code[4], issue_slots[10].in_uop.bits.fu_code[4] connect slots_10.io.in_uop.bits.fu_code[5], issue_slots[10].in_uop.bits.fu_code[5] connect slots_10.io.in_uop.bits.fu_code[6], issue_slots[10].in_uop.bits.fu_code[6] connect slots_10.io.in_uop.bits.fu_code[7], issue_slots[10].in_uop.bits.fu_code[7] connect slots_10.io.in_uop.bits.fu_code[8], issue_slots[10].in_uop.bits.fu_code[8] connect slots_10.io.in_uop.bits.fu_code[9], issue_slots[10].in_uop.bits.fu_code[9] connect slots_10.io.in_uop.bits.iq_type[0], issue_slots[10].in_uop.bits.iq_type[0] connect slots_10.io.in_uop.bits.iq_type[1], issue_slots[10].in_uop.bits.iq_type[1] connect slots_10.io.in_uop.bits.iq_type[2], issue_slots[10].in_uop.bits.iq_type[2] connect slots_10.io.in_uop.bits.iq_type[3], issue_slots[10].in_uop.bits.iq_type[3] connect slots_10.io.in_uop.bits.debug_pc, issue_slots[10].in_uop.bits.debug_pc connect slots_10.io.in_uop.bits.is_rvc, issue_slots[10].in_uop.bits.is_rvc connect slots_10.io.in_uop.bits.debug_inst, issue_slots[10].in_uop.bits.debug_inst connect slots_10.io.in_uop.bits.inst, issue_slots[10].in_uop.bits.inst connect slots_10.io.in_uop.valid, issue_slots[10].in_uop.valid connect issue_slots[10].iss_uop.debug_tsrc, slots_10.io.iss_uop.debug_tsrc connect issue_slots[10].iss_uop.debug_fsrc, slots_10.io.iss_uop.debug_fsrc connect issue_slots[10].iss_uop.bp_xcpt_if, slots_10.io.iss_uop.bp_xcpt_if connect issue_slots[10].iss_uop.bp_debug_if, slots_10.io.iss_uop.bp_debug_if connect issue_slots[10].iss_uop.xcpt_ma_if, slots_10.io.iss_uop.xcpt_ma_if connect issue_slots[10].iss_uop.xcpt_ae_if, slots_10.io.iss_uop.xcpt_ae_if connect issue_slots[10].iss_uop.xcpt_pf_if, slots_10.io.iss_uop.xcpt_pf_if connect issue_slots[10].iss_uop.fp_typ, slots_10.io.iss_uop.fp_typ connect issue_slots[10].iss_uop.fp_rm, slots_10.io.iss_uop.fp_rm connect issue_slots[10].iss_uop.fp_val, slots_10.io.iss_uop.fp_val connect issue_slots[10].iss_uop.fcn_op, slots_10.io.iss_uop.fcn_op connect issue_slots[10].iss_uop.fcn_dw, slots_10.io.iss_uop.fcn_dw connect issue_slots[10].iss_uop.frs3_en, slots_10.io.iss_uop.frs3_en connect issue_slots[10].iss_uop.lrs2_rtype, slots_10.io.iss_uop.lrs2_rtype connect issue_slots[10].iss_uop.lrs1_rtype, slots_10.io.iss_uop.lrs1_rtype connect issue_slots[10].iss_uop.dst_rtype, slots_10.io.iss_uop.dst_rtype connect issue_slots[10].iss_uop.lrs3, slots_10.io.iss_uop.lrs3 connect issue_slots[10].iss_uop.lrs2, slots_10.io.iss_uop.lrs2 connect issue_slots[10].iss_uop.lrs1, slots_10.io.iss_uop.lrs1 connect issue_slots[10].iss_uop.ldst, slots_10.io.iss_uop.ldst connect issue_slots[10].iss_uop.ldst_is_rs1, slots_10.io.iss_uop.ldst_is_rs1 connect issue_slots[10].iss_uop.csr_cmd, slots_10.io.iss_uop.csr_cmd connect issue_slots[10].iss_uop.flush_on_commit, slots_10.io.iss_uop.flush_on_commit connect issue_slots[10].iss_uop.is_unique, slots_10.io.iss_uop.is_unique connect issue_slots[10].iss_uop.uses_stq, slots_10.io.iss_uop.uses_stq connect issue_slots[10].iss_uop.uses_ldq, slots_10.io.iss_uop.uses_ldq connect issue_slots[10].iss_uop.mem_signed, slots_10.io.iss_uop.mem_signed connect issue_slots[10].iss_uop.mem_size, slots_10.io.iss_uop.mem_size connect issue_slots[10].iss_uop.mem_cmd, slots_10.io.iss_uop.mem_cmd connect issue_slots[10].iss_uop.exc_cause, slots_10.io.iss_uop.exc_cause connect issue_slots[10].iss_uop.exception, slots_10.io.iss_uop.exception connect issue_slots[10].iss_uop.stale_pdst, slots_10.io.iss_uop.stale_pdst connect issue_slots[10].iss_uop.ppred_busy, slots_10.io.iss_uop.ppred_busy connect issue_slots[10].iss_uop.prs3_busy, slots_10.io.iss_uop.prs3_busy connect issue_slots[10].iss_uop.prs2_busy, slots_10.io.iss_uop.prs2_busy connect issue_slots[10].iss_uop.prs1_busy, slots_10.io.iss_uop.prs1_busy connect issue_slots[10].iss_uop.ppred, slots_10.io.iss_uop.ppred connect issue_slots[10].iss_uop.prs3, slots_10.io.iss_uop.prs3 connect issue_slots[10].iss_uop.prs2, slots_10.io.iss_uop.prs2 connect issue_slots[10].iss_uop.prs1, slots_10.io.iss_uop.prs1 connect issue_slots[10].iss_uop.pdst, slots_10.io.iss_uop.pdst connect issue_slots[10].iss_uop.rxq_idx, slots_10.io.iss_uop.rxq_idx connect issue_slots[10].iss_uop.stq_idx, slots_10.io.iss_uop.stq_idx connect issue_slots[10].iss_uop.ldq_idx, slots_10.io.iss_uop.ldq_idx connect issue_slots[10].iss_uop.rob_idx, slots_10.io.iss_uop.rob_idx connect issue_slots[10].iss_uop.fp_ctrl.vec, slots_10.io.iss_uop.fp_ctrl.vec connect issue_slots[10].iss_uop.fp_ctrl.wflags, slots_10.io.iss_uop.fp_ctrl.wflags connect issue_slots[10].iss_uop.fp_ctrl.sqrt, slots_10.io.iss_uop.fp_ctrl.sqrt connect issue_slots[10].iss_uop.fp_ctrl.div, slots_10.io.iss_uop.fp_ctrl.div connect issue_slots[10].iss_uop.fp_ctrl.fma, slots_10.io.iss_uop.fp_ctrl.fma connect issue_slots[10].iss_uop.fp_ctrl.fastpipe, slots_10.io.iss_uop.fp_ctrl.fastpipe connect issue_slots[10].iss_uop.fp_ctrl.toint, slots_10.io.iss_uop.fp_ctrl.toint connect issue_slots[10].iss_uop.fp_ctrl.fromint, slots_10.io.iss_uop.fp_ctrl.fromint connect issue_slots[10].iss_uop.fp_ctrl.typeTagOut, slots_10.io.iss_uop.fp_ctrl.typeTagOut connect issue_slots[10].iss_uop.fp_ctrl.typeTagIn, slots_10.io.iss_uop.fp_ctrl.typeTagIn connect issue_slots[10].iss_uop.fp_ctrl.swap23, slots_10.io.iss_uop.fp_ctrl.swap23 connect issue_slots[10].iss_uop.fp_ctrl.swap12, slots_10.io.iss_uop.fp_ctrl.swap12 connect issue_slots[10].iss_uop.fp_ctrl.ren3, slots_10.io.iss_uop.fp_ctrl.ren3 connect issue_slots[10].iss_uop.fp_ctrl.ren2, slots_10.io.iss_uop.fp_ctrl.ren2 connect issue_slots[10].iss_uop.fp_ctrl.ren1, slots_10.io.iss_uop.fp_ctrl.ren1 connect issue_slots[10].iss_uop.fp_ctrl.wen, slots_10.io.iss_uop.fp_ctrl.wen connect issue_slots[10].iss_uop.fp_ctrl.ldst, slots_10.io.iss_uop.fp_ctrl.ldst connect issue_slots[10].iss_uop.op2_sel, slots_10.io.iss_uop.op2_sel connect issue_slots[10].iss_uop.op1_sel, slots_10.io.iss_uop.op1_sel connect issue_slots[10].iss_uop.imm_packed, slots_10.io.iss_uop.imm_packed connect issue_slots[10].iss_uop.pimm, slots_10.io.iss_uop.pimm connect issue_slots[10].iss_uop.imm_sel, slots_10.io.iss_uop.imm_sel connect issue_slots[10].iss_uop.imm_rename, slots_10.io.iss_uop.imm_rename connect issue_slots[10].iss_uop.taken, slots_10.io.iss_uop.taken connect issue_slots[10].iss_uop.pc_lob, slots_10.io.iss_uop.pc_lob connect issue_slots[10].iss_uop.edge_inst, slots_10.io.iss_uop.edge_inst connect issue_slots[10].iss_uop.ftq_idx, slots_10.io.iss_uop.ftq_idx connect issue_slots[10].iss_uop.is_mov, slots_10.io.iss_uop.is_mov connect issue_slots[10].iss_uop.is_rocc, slots_10.io.iss_uop.is_rocc connect issue_slots[10].iss_uop.is_sys_pc2epc, slots_10.io.iss_uop.is_sys_pc2epc connect issue_slots[10].iss_uop.is_eret, slots_10.io.iss_uop.is_eret connect issue_slots[10].iss_uop.is_amo, slots_10.io.iss_uop.is_amo connect issue_slots[10].iss_uop.is_sfence, slots_10.io.iss_uop.is_sfence connect issue_slots[10].iss_uop.is_fencei, slots_10.io.iss_uop.is_fencei connect issue_slots[10].iss_uop.is_fence, slots_10.io.iss_uop.is_fence connect issue_slots[10].iss_uop.is_sfb, slots_10.io.iss_uop.is_sfb connect issue_slots[10].iss_uop.br_type, slots_10.io.iss_uop.br_type connect issue_slots[10].iss_uop.br_tag, slots_10.io.iss_uop.br_tag connect issue_slots[10].iss_uop.br_mask, slots_10.io.iss_uop.br_mask connect issue_slots[10].iss_uop.dis_col_sel, slots_10.io.iss_uop.dis_col_sel connect issue_slots[10].iss_uop.iw_p3_bypass_hint, slots_10.io.iss_uop.iw_p3_bypass_hint connect issue_slots[10].iss_uop.iw_p2_bypass_hint, slots_10.io.iss_uop.iw_p2_bypass_hint connect issue_slots[10].iss_uop.iw_p1_bypass_hint, slots_10.io.iss_uop.iw_p1_bypass_hint connect issue_slots[10].iss_uop.iw_p2_speculative_child, slots_10.io.iss_uop.iw_p2_speculative_child connect issue_slots[10].iss_uop.iw_p1_speculative_child, slots_10.io.iss_uop.iw_p1_speculative_child connect issue_slots[10].iss_uop.iw_issued_partial_dgen, slots_10.io.iss_uop.iw_issued_partial_dgen connect issue_slots[10].iss_uop.iw_issued_partial_agen, slots_10.io.iss_uop.iw_issued_partial_agen connect issue_slots[10].iss_uop.iw_issued, slots_10.io.iss_uop.iw_issued connect issue_slots[10].iss_uop.fu_code[0], slots_10.io.iss_uop.fu_code[0] connect issue_slots[10].iss_uop.fu_code[1], slots_10.io.iss_uop.fu_code[1] connect issue_slots[10].iss_uop.fu_code[2], slots_10.io.iss_uop.fu_code[2] connect issue_slots[10].iss_uop.fu_code[3], slots_10.io.iss_uop.fu_code[3] connect issue_slots[10].iss_uop.fu_code[4], slots_10.io.iss_uop.fu_code[4] connect issue_slots[10].iss_uop.fu_code[5], slots_10.io.iss_uop.fu_code[5] connect issue_slots[10].iss_uop.fu_code[6], slots_10.io.iss_uop.fu_code[6] connect issue_slots[10].iss_uop.fu_code[7], slots_10.io.iss_uop.fu_code[7] connect issue_slots[10].iss_uop.fu_code[8], slots_10.io.iss_uop.fu_code[8] connect issue_slots[10].iss_uop.fu_code[9], slots_10.io.iss_uop.fu_code[9] connect issue_slots[10].iss_uop.iq_type[0], slots_10.io.iss_uop.iq_type[0] connect issue_slots[10].iss_uop.iq_type[1], slots_10.io.iss_uop.iq_type[1] connect issue_slots[10].iss_uop.iq_type[2], slots_10.io.iss_uop.iq_type[2] connect issue_slots[10].iss_uop.iq_type[3], slots_10.io.iss_uop.iq_type[3] connect issue_slots[10].iss_uop.debug_pc, slots_10.io.iss_uop.debug_pc connect issue_slots[10].iss_uop.is_rvc, slots_10.io.iss_uop.is_rvc connect issue_slots[10].iss_uop.debug_inst, slots_10.io.iss_uop.debug_inst connect issue_slots[10].iss_uop.inst, slots_10.io.iss_uop.inst connect slots_10.io.grant, issue_slots[10].grant connect issue_slots[10].request, slots_10.io.request connect issue_slots[10].will_be_valid, slots_10.io.will_be_valid connect issue_slots[10].valid, slots_10.io.valid connect slots_11.io.child_rebusys, issue_slots[11].child_rebusys connect slots_11.io.pred_wakeup_port.bits, issue_slots[11].pred_wakeup_port.bits connect slots_11.io.pred_wakeup_port.valid, issue_slots[11].pred_wakeup_port.valid connect slots_11.io.wakeup_ports[0].bits.rebusy, issue_slots[11].wakeup_ports[0].bits.rebusy connect slots_11.io.wakeup_ports[0].bits.speculative_mask, issue_slots[11].wakeup_ports[0].bits.speculative_mask connect slots_11.io.wakeup_ports[0].bits.bypassable, issue_slots[11].wakeup_ports[0].bits.bypassable connect slots_11.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[11].wakeup_ports[0].bits.uop.debug_tsrc connect slots_11.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[11].wakeup_ports[0].bits.uop.debug_fsrc connect slots_11.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[11].wakeup_ports[0].bits.uop.bp_xcpt_if connect slots_11.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[11].wakeup_ports[0].bits.uop.bp_debug_if connect slots_11.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[11].wakeup_ports[0].bits.uop.xcpt_ma_if connect slots_11.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[11].wakeup_ports[0].bits.uop.xcpt_ae_if connect slots_11.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[11].wakeup_ports[0].bits.uop.xcpt_pf_if connect slots_11.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[11].wakeup_ports[0].bits.uop.fp_typ connect slots_11.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[11].wakeup_ports[0].bits.uop.fp_rm connect slots_11.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[11].wakeup_ports[0].bits.uop.fp_val connect slots_11.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[11].wakeup_ports[0].bits.uop.fcn_op connect slots_11.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[11].wakeup_ports[0].bits.uop.fcn_dw connect slots_11.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[11].wakeup_ports[0].bits.uop.frs3_en connect slots_11.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[11].wakeup_ports[0].bits.uop.lrs2_rtype connect slots_11.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[11].wakeup_ports[0].bits.uop.lrs1_rtype connect slots_11.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[11].wakeup_ports[0].bits.uop.dst_rtype connect slots_11.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[11].wakeup_ports[0].bits.uop.lrs3 connect slots_11.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[11].wakeup_ports[0].bits.uop.lrs2 connect slots_11.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[11].wakeup_ports[0].bits.uop.lrs1 connect slots_11.io.wakeup_ports[0].bits.uop.ldst, issue_slots[11].wakeup_ports[0].bits.uop.ldst connect slots_11.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[11].wakeup_ports[0].bits.uop.ldst_is_rs1 connect slots_11.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[11].wakeup_ports[0].bits.uop.csr_cmd connect slots_11.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[11].wakeup_ports[0].bits.uop.flush_on_commit connect slots_11.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[11].wakeup_ports[0].bits.uop.is_unique connect slots_11.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[11].wakeup_ports[0].bits.uop.uses_stq connect slots_11.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[11].wakeup_ports[0].bits.uop.uses_ldq connect slots_11.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[11].wakeup_ports[0].bits.uop.mem_signed connect slots_11.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[11].wakeup_ports[0].bits.uop.mem_size connect slots_11.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[11].wakeup_ports[0].bits.uop.mem_cmd connect slots_11.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[11].wakeup_ports[0].bits.uop.exc_cause connect slots_11.io.wakeup_ports[0].bits.uop.exception, issue_slots[11].wakeup_ports[0].bits.uop.exception connect slots_11.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[11].wakeup_ports[0].bits.uop.stale_pdst connect slots_11.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[11].wakeup_ports[0].bits.uop.ppred_busy connect slots_11.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[11].wakeup_ports[0].bits.uop.prs3_busy connect slots_11.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[11].wakeup_ports[0].bits.uop.prs2_busy connect slots_11.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[11].wakeup_ports[0].bits.uop.prs1_busy connect slots_11.io.wakeup_ports[0].bits.uop.ppred, issue_slots[11].wakeup_ports[0].bits.uop.ppred connect slots_11.io.wakeup_ports[0].bits.uop.prs3, issue_slots[11].wakeup_ports[0].bits.uop.prs3 connect slots_11.io.wakeup_ports[0].bits.uop.prs2, issue_slots[11].wakeup_ports[0].bits.uop.prs2 connect slots_11.io.wakeup_ports[0].bits.uop.prs1, issue_slots[11].wakeup_ports[0].bits.uop.prs1 connect slots_11.io.wakeup_ports[0].bits.uop.pdst, issue_slots[11].wakeup_ports[0].bits.uop.pdst connect slots_11.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[11].wakeup_ports[0].bits.uop.rxq_idx connect slots_11.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[11].wakeup_ports[0].bits.uop.stq_idx connect slots_11.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[11].wakeup_ports[0].bits.uop.ldq_idx connect slots_11.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[11].wakeup_ports[0].bits.uop.rob_idx connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.vec connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.wflags connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.div connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.fma connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.toint connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.fromint connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.wen connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.ldst connect slots_11.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[11].wakeup_ports[0].bits.uop.op2_sel connect slots_11.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[11].wakeup_ports[0].bits.uop.op1_sel connect slots_11.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[11].wakeup_ports[0].bits.uop.imm_packed connect slots_11.io.wakeup_ports[0].bits.uop.pimm, issue_slots[11].wakeup_ports[0].bits.uop.pimm connect slots_11.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[11].wakeup_ports[0].bits.uop.imm_sel connect slots_11.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[11].wakeup_ports[0].bits.uop.imm_rename connect slots_11.io.wakeup_ports[0].bits.uop.taken, issue_slots[11].wakeup_ports[0].bits.uop.taken connect slots_11.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[11].wakeup_ports[0].bits.uop.pc_lob connect slots_11.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[11].wakeup_ports[0].bits.uop.edge_inst connect slots_11.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[11].wakeup_ports[0].bits.uop.ftq_idx connect slots_11.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[11].wakeup_ports[0].bits.uop.is_mov connect slots_11.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[11].wakeup_ports[0].bits.uop.is_rocc connect slots_11.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[11].wakeup_ports[0].bits.uop.is_sys_pc2epc connect slots_11.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[11].wakeup_ports[0].bits.uop.is_eret connect slots_11.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[11].wakeup_ports[0].bits.uop.is_amo connect slots_11.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[11].wakeup_ports[0].bits.uop.is_sfence connect slots_11.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[11].wakeup_ports[0].bits.uop.is_fencei connect slots_11.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[11].wakeup_ports[0].bits.uop.is_fence connect slots_11.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[11].wakeup_ports[0].bits.uop.is_sfb connect slots_11.io.wakeup_ports[0].bits.uop.br_type, issue_slots[11].wakeup_ports[0].bits.uop.br_type connect slots_11.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[11].wakeup_ports[0].bits.uop.br_tag connect slots_11.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[11].wakeup_ports[0].bits.uop.br_mask connect slots_11.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[11].wakeup_ports[0].bits.uop.dis_col_sel connect slots_11.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[11].wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect slots_11.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[11].wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect slots_11.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[11].wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect slots_11.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[11].wakeup_ports[0].bits.uop.iw_p2_speculative_child connect slots_11.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[11].wakeup_ports[0].bits.uop.iw_p1_speculative_child connect slots_11.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[11].wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect slots_11.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[11].wakeup_ports[0].bits.uop.iw_issued_partial_agen connect slots_11.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[11].wakeup_ports[0].bits.uop.iw_issued connect slots_11.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[11].wakeup_ports[0].bits.uop.fu_code[0] connect slots_11.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[11].wakeup_ports[0].bits.uop.fu_code[1] connect slots_11.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[11].wakeup_ports[0].bits.uop.fu_code[2] connect slots_11.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[11].wakeup_ports[0].bits.uop.fu_code[3] connect slots_11.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[11].wakeup_ports[0].bits.uop.fu_code[4] connect slots_11.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[11].wakeup_ports[0].bits.uop.fu_code[5] connect slots_11.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[11].wakeup_ports[0].bits.uop.fu_code[6] connect slots_11.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[11].wakeup_ports[0].bits.uop.fu_code[7] connect slots_11.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[11].wakeup_ports[0].bits.uop.fu_code[8] connect slots_11.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[11].wakeup_ports[0].bits.uop.fu_code[9] connect slots_11.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[11].wakeup_ports[0].bits.uop.iq_type[0] connect slots_11.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[11].wakeup_ports[0].bits.uop.iq_type[1] connect slots_11.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[11].wakeup_ports[0].bits.uop.iq_type[2] connect slots_11.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[11].wakeup_ports[0].bits.uop.iq_type[3] connect slots_11.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[11].wakeup_ports[0].bits.uop.debug_pc connect slots_11.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[11].wakeup_ports[0].bits.uop.is_rvc connect slots_11.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[11].wakeup_ports[0].bits.uop.debug_inst connect slots_11.io.wakeup_ports[0].bits.uop.inst, issue_slots[11].wakeup_ports[0].bits.uop.inst connect slots_11.io.wakeup_ports[0].valid, issue_slots[11].wakeup_ports[0].valid connect slots_11.io.wakeup_ports[1].bits.rebusy, issue_slots[11].wakeup_ports[1].bits.rebusy connect slots_11.io.wakeup_ports[1].bits.speculative_mask, issue_slots[11].wakeup_ports[1].bits.speculative_mask connect slots_11.io.wakeup_ports[1].bits.bypassable, issue_slots[11].wakeup_ports[1].bits.bypassable connect slots_11.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[11].wakeup_ports[1].bits.uop.debug_tsrc connect slots_11.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[11].wakeup_ports[1].bits.uop.debug_fsrc connect slots_11.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[11].wakeup_ports[1].bits.uop.bp_xcpt_if connect slots_11.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[11].wakeup_ports[1].bits.uop.bp_debug_if connect slots_11.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[11].wakeup_ports[1].bits.uop.xcpt_ma_if connect slots_11.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[11].wakeup_ports[1].bits.uop.xcpt_ae_if connect slots_11.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[11].wakeup_ports[1].bits.uop.xcpt_pf_if connect slots_11.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[11].wakeup_ports[1].bits.uop.fp_typ connect slots_11.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[11].wakeup_ports[1].bits.uop.fp_rm connect slots_11.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[11].wakeup_ports[1].bits.uop.fp_val connect slots_11.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[11].wakeup_ports[1].bits.uop.fcn_op connect slots_11.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[11].wakeup_ports[1].bits.uop.fcn_dw connect slots_11.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[11].wakeup_ports[1].bits.uop.frs3_en connect slots_11.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[11].wakeup_ports[1].bits.uop.lrs2_rtype connect slots_11.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[11].wakeup_ports[1].bits.uop.lrs1_rtype connect slots_11.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[11].wakeup_ports[1].bits.uop.dst_rtype connect slots_11.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[11].wakeup_ports[1].bits.uop.lrs3 connect slots_11.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[11].wakeup_ports[1].bits.uop.lrs2 connect slots_11.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[11].wakeup_ports[1].bits.uop.lrs1 connect slots_11.io.wakeup_ports[1].bits.uop.ldst, issue_slots[11].wakeup_ports[1].bits.uop.ldst connect slots_11.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[11].wakeup_ports[1].bits.uop.ldst_is_rs1 connect slots_11.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[11].wakeup_ports[1].bits.uop.csr_cmd connect slots_11.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[11].wakeup_ports[1].bits.uop.flush_on_commit connect slots_11.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[11].wakeup_ports[1].bits.uop.is_unique connect slots_11.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[11].wakeup_ports[1].bits.uop.uses_stq connect slots_11.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[11].wakeup_ports[1].bits.uop.uses_ldq connect slots_11.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[11].wakeup_ports[1].bits.uop.mem_signed connect slots_11.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[11].wakeup_ports[1].bits.uop.mem_size connect slots_11.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[11].wakeup_ports[1].bits.uop.mem_cmd connect slots_11.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[11].wakeup_ports[1].bits.uop.exc_cause connect slots_11.io.wakeup_ports[1].bits.uop.exception, issue_slots[11].wakeup_ports[1].bits.uop.exception connect slots_11.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[11].wakeup_ports[1].bits.uop.stale_pdst connect slots_11.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[11].wakeup_ports[1].bits.uop.ppred_busy connect slots_11.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[11].wakeup_ports[1].bits.uop.prs3_busy connect slots_11.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[11].wakeup_ports[1].bits.uop.prs2_busy connect slots_11.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[11].wakeup_ports[1].bits.uop.prs1_busy connect slots_11.io.wakeup_ports[1].bits.uop.ppred, issue_slots[11].wakeup_ports[1].bits.uop.ppred connect slots_11.io.wakeup_ports[1].bits.uop.prs3, issue_slots[11].wakeup_ports[1].bits.uop.prs3 connect slots_11.io.wakeup_ports[1].bits.uop.prs2, issue_slots[11].wakeup_ports[1].bits.uop.prs2 connect slots_11.io.wakeup_ports[1].bits.uop.prs1, issue_slots[11].wakeup_ports[1].bits.uop.prs1 connect slots_11.io.wakeup_ports[1].bits.uop.pdst, issue_slots[11].wakeup_ports[1].bits.uop.pdst connect slots_11.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[11].wakeup_ports[1].bits.uop.rxq_idx connect slots_11.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[11].wakeup_ports[1].bits.uop.stq_idx connect slots_11.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[11].wakeup_ports[1].bits.uop.ldq_idx connect slots_11.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[11].wakeup_ports[1].bits.uop.rob_idx connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.vec connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.wflags connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.div connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.fma connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.toint connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.fromint connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.wen connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.ldst connect slots_11.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[11].wakeup_ports[1].bits.uop.op2_sel connect slots_11.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[11].wakeup_ports[1].bits.uop.op1_sel connect slots_11.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[11].wakeup_ports[1].bits.uop.imm_packed connect slots_11.io.wakeup_ports[1].bits.uop.pimm, issue_slots[11].wakeup_ports[1].bits.uop.pimm connect slots_11.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[11].wakeup_ports[1].bits.uop.imm_sel connect slots_11.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[11].wakeup_ports[1].bits.uop.imm_rename connect slots_11.io.wakeup_ports[1].bits.uop.taken, issue_slots[11].wakeup_ports[1].bits.uop.taken connect slots_11.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[11].wakeup_ports[1].bits.uop.pc_lob connect slots_11.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[11].wakeup_ports[1].bits.uop.edge_inst connect slots_11.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[11].wakeup_ports[1].bits.uop.ftq_idx connect slots_11.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[11].wakeup_ports[1].bits.uop.is_mov connect slots_11.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[11].wakeup_ports[1].bits.uop.is_rocc connect slots_11.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[11].wakeup_ports[1].bits.uop.is_sys_pc2epc connect slots_11.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[11].wakeup_ports[1].bits.uop.is_eret connect slots_11.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[11].wakeup_ports[1].bits.uop.is_amo connect slots_11.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[11].wakeup_ports[1].bits.uop.is_sfence connect slots_11.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[11].wakeup_ports[1].bits.uop.is_fencei connect slots_11.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[11].wakeup_ports[1].bits.uop.is_fence connect slots_11.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[11].wakeup_ports[1].bits.uop.is_sfb connect slots_11.io.wakeup_ports[1].bits.uop.br_type, issue_slots[11].wakeup_ports[1].bits.uop.br_type connect slots_11.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[11].wakeup_ports[1].bits.uop.br_tag connect slots_11.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[11].wakeup_ports[1].bits.uop.br_mask connect slots_11.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[11].wakeup_ports[1].bits.uop.dis_col_sel connect slots_11.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[11].wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect slots_11.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[11].wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect slots_11.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[11].wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect slots_11.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[11].wakeup_ports[1].bits.uop.iw_p2_speculative_child connect slots_11.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[11].wakeup_ports[1].bits.uop.iw_p1_speculative_child connect slots_11.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[11].wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect slots_11.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[11].wakeup_ports[1].bits.uop.iw_issued_partial_agen connect slots_11.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[11].wakeup_ports[1].bits.uop.iw_issued connect slots_11.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[11].wakeup_ports[1].bits.uop.fu_code[0] connect slots_11.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[11].wakeup_ports[1].bits.uop.fu_code[1] connect slots_11.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[11].wakeup_ports[1].bits.uop.fu_code[2] connect slots_11.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[11].wakeup_ports[1].bits.uop.fu_code[3] connect slots_11.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[11].wakeup_ports[1].bits.uop.fu_code[4] connect slots_11.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[11].wakeup_ports[1].bits.uop.fu_code[5] connect slots_11.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[11].wakeup_ports[1].bits.uop.fu_code[6] connect slots_11.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[11].wakeup_ports[1].bits.uop.fu_code[7] connect slots_11.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[11].wakeup_ports[1].bits.uop.fu_code[8] connect slots_11.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[11].wakeup_ports[1].bits.uop.fu_code[9] connect slots_11.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[11].wakeup_ports[1].bits.uop.iq_type[0] connect slots_11.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[11].wakeup_ports[1].bits.uop.iq_type[1] connect slots_11.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[11].wakeup_ports[1].bits.uop.iq_type[2] connect slots_11.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[11].wakeup_ports[1].bits.uop.iq_type[3] connect slots_11.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[11].wakeup_ports[1].bits.uop.debug_pc connect slots_11.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[11].wakeup_ports[1].bits.uop.is_rvc connect slots_11.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[11].wakeup_ports[1].bits.uop.debug_inst connect slots_11.io.wakeup_ports[1].bits.uop.inst, issue_slots[11].wakeup_ports[1].bits.uop.inst connect slots_11.io.wakeup_ports[1].valid, issue_slots[11].wakeup_ports[1].valid connect slots_11.io.wakeup_ports[2].bits.rebusy, issue_slots[11].wakeup_ports[2].bits.rebusy connect slots_11.io.wakeup_ports[2].bits.speculative_mask, issue_slots[11].wakeup_ports[2].bits.speculative_mask connect slots_11.io.wakeup_ports[2].bits.bypassable, issue_slots[11].wakeup_ports[2].bits.bypassable connect slots_11.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[11].wakeup_ports[2].bits.uop.debug_tsrc connect slots_11.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[11].wakeup_ports[2].bits.uop.debug_fsrc connect slots_11.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[11].wakeup_ports[2].bits.uop.bp_xcpt_if connect slots_11.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[11].wakeup_ports[2].bits.uop.bp_debug_if connect slots_11.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[11].wakeup_ports[2].bits.uop.xcpt_ma_if connect slots_11.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[11].wakeup_ports[2].bits.uop.xcpt_ae_if connect slots_11.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[11].wakeup_ports[2].bits.uop.xcpt_pf_if connect slots_11.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[11].wakeup_ports[2].bits.uop.fp_typ connect slots_11.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[11].wakeup_ports[2].bits.uop.fp_rm connect slots_11.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[11].wakeup_ports[2].bits.uop.fp_val connect slots_11.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[11].wakeup_ports[2].bits.uop.fcn_op connect slots_11.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[11].wakeup_ports[2].bits.uop.fcn_dw connect slots_11.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[11].wakeup_ports[2].bits.uop.frs3_en connect slots_11.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[11].wakeup_ports[2].bits.uop.lrs2_rtype connect slots_11.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[11].wakeup_ports[2].bits.uop.lrs1_rtype connect slots_11.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[11].wakeup_ports[2].bits.uop.dst_rtype connect slots_11.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[11].wakeup_ports[2].bits.uop.lrs3 connect slots_11.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[11].wakeup_ports[2].bits.uop.lrs2 connect slots_11.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[11].wakeup_ports[2].bits.uop.lrs1 connect slots_11.io.wakeup_ports[2].bits.uop.ldst, issue_slots[11].wakeup_ports[2].bits.uop.ldst connect slots_11.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[11].wakeup_ports[2].bits.uop.ldst_is_rs1 connect slots_11.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[11].wakeup_ports[2].bits.uop.csr_cmd connect slots_11.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[11].wakeup_ports[2].bits.uop.flush_on_commit connect slots_11.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[11].wakeup_ports[2].bits.uop.is_unique connect slots_11.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[11].wakeup_ports[2].bits.uop.uses_stq connect slots_11.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[11].wakeup_ports[2].bits.uop.uses_ldq connect slots_11.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[11].wakeup_ports[2].bits.uop.mem_signed connect slots_11.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[11].wakeup_ports[2].bits.uop.mem_size connect slots_11.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[11].wakeup_ports[2].bits.uop.mem_cmd connect slots_11.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[11].wakeup_ports[2].bits.uop.exc_cause connect slots_11.io.wakeup_ports[2].bits.uop.exception, issue_slots[11].wakeup_ports[2].bits.uop.exception connect slots_11.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[11].wakeup_ports[2].bits.uop.stale_pdst connect slots_11.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[11].wakeup_ports[2].bits.uop.ppred_busy connect slots_11.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[11].wakeup_ports[2].bits.uop.prs3_busy connect slots_11.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[11].wakeup_ports[2].bits.uop.prs2_busy connect slots_11.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[11].wakeup_ports[2].bits.uop.prs1_busy connect slots_11.io.wakeup_ports[2].bits.uop.ppred, issue_slots[11].wakeup_ports[2].bits.uop.ppred connect slots_11.io.wakeup_ports[2].bits.uop.prs3, issue_slots[11].wakeup_ports[2].bits.uop.prs3 connect slots_11.io.wakeup_ports[2].bits.uop.prs2, issue_slots[11].wakeup_ports[2].bits.uop.prs2 connect slots_11.io.wakeup_ports[2].bits.uop.prs1, issue_slots[11].wakeup_ports[2].bits.uop.prs1 connect slots_11.io.wakeup_ports[2].bits.uop.pdst, issue_slots[11].wakeup_ports[2].bits.uop.pdst connect slots_11.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[11].wakeup_ports[2].bits.uop.rxq_idx connect slots_11.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[11].wakeup_ports[2].bits.uop.stq_idx connect slots_11.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[11].wakeup_ports[2].bits.uop.ldq_idx connect slots_11.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[11].wakeup_ports[2].bits.uop.rob_idx connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.vec connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.wflags connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.div connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.fma connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.toint connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.fromint connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.wen connect slots_11.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.ldst connect slots_11.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[11].wakeup_ports[2].bits.uop.op2_sel connect slots_11.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[11].wakeup_ports[2].bits.uop.op1_sel connect slots_11.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[11].wakeup_ports[2].bits.uop.imm_packed connect slots_11.io.wakeup_ports[2].bits.uop.pimm, issue_slots[11].wakeup_ports[2].bits.uop.pimm connect slots_11.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[11].wakeup_ports[2].bits.uop.imm_sel connect slots_11.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[11].wakeup_ports[2].bits.uop.imm_rename connect slots_11.io.wakeup_ports[2].bits.uop.taken, issue_slots[11].wakeup_ports[2].bits.uop.taken connect slots_11.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[11].wakeup_ports[2].bits.uop.pc_lob connect slots_11.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[11].wakeup_ports[2].bits.uop.edge_inst connect slots_11.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[11].wakeup_ports[2].bits.uop.ftq_idx connect slots_11.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[11].wakeup_ports[2].bits.uop.is_mov connect slots_11.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[11].wakeup_ports[2].bits.uop.is_rocc connect slots_11.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[11].wakeup_ports[2].bits.uop.is_sys_pc2epc connect slots_11.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[11].wakeup_ports[2].bits.uop.is_eret connect slots_11.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[11].wakeup_ports[2].bits.uop.is_amo connect slots_11.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[11].wakeup_ports[2].bits.uop.is_sfence connect slots_11.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[11].wakeup_ports[2].bits.uop.is_fencei connect slots_11.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[11].wakeup_ports[2].bits.uop.is_fence connect slots_11.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[11].wakeup_ports[2].bits.uop.is_sfb connect slots_11.io.wakeup_ports[2].bits.uop.br_type, issue_slots[11].wakeup_ports[2].bits.uop.br_type connect slots_11.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[11].wakeup_ports[2].bits.uop.br_tag connect slots_11.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[11].wakeup_ports[2].bits.uop.br_mask connect slots_11.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[11].wakeup_ports[2].bits.uop.dis_col_sel connect slots_11.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[11].wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect slots_11.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[11].wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect slots_11.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[11].wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect slots_11.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[11].wakeup_ports[2].bits.uop.iw_p2_speculative_child connect slots_11.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[11].wakeup_ports[2].bits.uop.iw_p1_speculative_child connect slots_11.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[11].wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect slots_11.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[11].wakeup_ports[2].bits.uop.iw_issued_partial_agen connect slots_11.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[11].wakeup_ports[2].bits.uop.iw_issued connect slots_11.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[11].wakeup_ports[2].bits.uop.fu_code[0] connect slots_11.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[11].wakeup_ports[2].bits.uop.fu_code[1] connect slots_11.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[11].wakeup_ports[2].bits.uop.fu_code[2] connect slots_11.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[11].wakeup_ports[2].bits.uop.fu_code[3] connect slots_11.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[11].wakeup_ports[2].bits.uop.fu_code[4] connect slots_11.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[11].wakeup_ports[2].bits.uop.fu_code[5] connect slots_11.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[11].wakeup_ports[2].bits.uop.fu_code[6] connect slots_11.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[11].wakeup_ports[2].bits.uop.fu_code[7] connect slots_11.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[11].wakeup_ports[2].bits.uop.fu_code[8] connect slots_11.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[11].wakeup_ports[2].bits.uop.fu_code[9] connect slots_11.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[11].wakeup_ports[2].bits.uop.iq_type[0] connect slots_11.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[11].wakeup_ports[2].bits.uop.iq_type[1] connect slots_11.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[11].wakeup_ports[2].bits.uop.iq_type[2] connect slots_11.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[11].wakeup_ports[2].bits.uop.iq_type[3] connect slots_11.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[11].wakeup_ports[2].bits.uop.debug_pc connect slots_11.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[11].wakeup_ports[2].bits.uop.is_rvc connect slots_11.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[11].wakeup_ports[2].bits.uop.debug_inst connect slots_11.io.wakeup_ports[2].bits.uop.inst, issue_slots[11].wakeup_ports[2].bits.uop.inst connect slots_11.io.wakeup_ports[2].valid, issue_slots[11].wakeup_ports[2].valid connect slots_11.io.wakeup_ports[3].bits.rebusy, issue_slots[11].wakeup_ports[3].bits.rebusy connect slots_11.io.wakeup_ports[3].bits.speculative_mask, issue_slots[11].wakeup_ports[3].bits.speculative_mask connect slots_11.io.wakeup_ports[3].bits.bypassable, issue_slots[11].wakeup_ports[3].bits.bypassable connect slots_11.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[11].wakeup_ports[3].bits.uop.debug_tsrc connect slots_11.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[11].wakeup_ports[3].bits.uop.debug_fsrc connect slots_11.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[11].wakeup_ports[3].bits.uop.bp_xcpt_if connect slots_11.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[11].wakeup_ports[3].bits.uop.bp_debug_if connect slots_11.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[11].wakeup_ports[3].bits.uop.xcpt_ma_if connect slots_11.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[11].wakeup_ports[3].bits.uop.xcpt_ae_if connect slots_11.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[11].wakeup_ports[3].bits.uop.xcpt_pf_if connect slots_11.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[11].wakeup_ports[3].bits.uop.fp_typ connect slots_11.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[11].wakeup_ports[3].bits.uop.fp_rm connect slots_11.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[11].wakeup_ports[3].bits.uop.fp_val connect slots_11.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[11].wakeup_ports[3].bits.uop.fcn_op connect slots_11.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[11].wakeup_ports[3].bits.uop.fcn_dw connect slots_11.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[11].wakeup_ports[3].bits.uop.frs3_en connect slots_11.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[11].wakeup_ports[3].bits.uop.lrs2_rtype connect slots_11.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[11].wakeup_ports[3].bits.uop.lrs1_rtype connect slots_11.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[11].wakeup_ports[3].bits.uop.dst_rtype connect slots_11.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[11].wakeup_ports[3].bits.uop.lrs3 connect slots_11.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[11].wakeup_ports[3].bits.uop.lrs2 connect slots_11.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[11].wakeup_ports[3].bits.uop.lrs1 connect slots_11.io.wakeup_ports[3].bits.uop.ldst, issue_slots[11].wakeup_ports[3].bits.uop.ldst connect slots_11.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[11].wakeup_ports[3].bits.uop.ldst_is_rs1 connect slots_11.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[11].wakeup_ports[3].bits.uop.csr_cmd connect slots_11.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[11].wakeup_ports[3].bits.uop.flush_on_commit connect slots_11.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[11].wakeup_ports[3].bits.uop.is_unique connect slots_11.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[11].wakeup_ports[3].bits.uop.uses_stq connect slots_11.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[11].wakeup_ports[3].bits.uop.uses_ldq connect slots_11.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[11].wakeup_ports[3].bits.uop.mem_signed connect slots_11.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[11].wakeup_ports[3].bits.uop.mem_size connect slots_11.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[11].wakeup_ports[3].bits.uop.mem_cmd connect slots_11.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[11].wakeup_ports[3].bits.uop.exc_cause connect slots_11.io.wakeup_ports[3].bits.uop.exception, issue_slots[11].wakeup_ports[3].bits.uop.exception connect slots_11.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[11].wakeup_ports[3].bits.uop.stale_pdst connect slots_11.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[11].wakeup_ports[3].bits.uop.ppred_busy connect slots_11.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[11].wakeup_ports[3].bits.uop.prs3_busy connect slots_11.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[11].wakeup_ports[3].bits.uop.prs2_busy connect slots_11.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[11].wakeup_ports[3].bits.uop.prs1_busy connect slots_11.io.wakeup_ports[3].bits.uop.ppred, issue_slots[11].wakeup_ports[3].bits.uop.ppred connect slots_11.io.wakeup_ports[3].bits.uop.prs3, issue_slots[11].wakeup_ports[3].bits.uop.prs3 connect slots_11.io.wakeup_ports[3].bits.uop.prs2, issue_slots[11].wakeup_ports[3].bits.uop.prs2 connect slots_11.io.wakeup_ports[3].bits.uop.prs1, issue_slots[11].wakeup_ports[3].bits.uop.prs1 connect slots_11.io.wakeup_ports[3].bits.uop.pdst, issue_slots[11].wakeup_ports[3].bits.uop.pdst connect slots_11.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[11].wakeup_ports[3].bits.uop.rxq_idx connect slots_11.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[11].wakeup_ports[3].bits.uop.stq_idx connect slots_11.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[11].wakeup_ports[3].bits.uop.ldq_idx connect slots_11.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[11].wakeup_ports[3].bits.uop.rob_idx connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.vec connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.wflags connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.div connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.fma connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.toint connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.fromint connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.wen connect slots_11.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.ldst connect slots_11.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[11].wakeup_ports[3].bits.uop.op2_sel connect slots_11.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[11].wakeup_ports[3].bits.uop.op1_sel connect slots_11.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[11].wakeup_ports[3].bits.uop.imm_packed connect slots_11.io.wakeup_ports[3].bits.uop.pimm, issue_slots[11].wakeup_ports[3].bits.uop.pimm connect slots_11.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[11].wakeup_ports[3].bits.uop.imm_sel connect slots_11.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[11].wakeup_ports[3].bits.uop.imm_rename connect slots_11.io.wakeup_ports[3].bits.uop.taken, issue_slots[11].wakeup_ports[3].bits.uop.taken connect slots_11.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[11].wakeup_ports[3].bits.uop.pc_lob connect slots_11.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[11].wakeup_ports[3].bits.uop.edge_inst connect slots_11.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[11].wakeup_ports[3].bits.uop.ftq_idx connect slots_11.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[11].wakeup_ports[3].bits.uop.is_mov connect slots_11.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[11].wakeup_ports[3].bits.uop.is_rocc connect slots_11.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[11].wakeup_ports[3].bits.uop.is_sys_pc2epc connect slots_11.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[11].wakeup_ports[3].bits.uop.is_eret connect slots_11.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[11].wakeup_ports[3].bits.uop.is_amo connect slots_11.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[11].wakeup_ports[3].bits.uop.is_sfence connect slots_11.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[11].wakeup_ports[3].bits.uop.is_fencei connect slots_11.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[11].wakeup_ports[3].bits.uop.is_fence connect slots_11.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[11].wakeup_ports[3].bits.uop.is_sfb connect slots_11.io.wakeup_ports[3].bits.uop.br_type, issue_slots[11].wakeup_ports[3].bits.uop.br_type connect slots_11.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[11].wakeup_ports[3].bits.uop.br_tag connect slots_11.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[11].wakeup_ports[3].bits.uop.br_mask connect slots_11.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[11].wakeup_ports[3].bits.uop.dis_col_sel connect slots_11.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[11].wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect slots_11.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[11].wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect slots_11.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[11].wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect slots_11.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[11].wakeup_ports[3].bits.uop.iw_p2_speculative_child connect slots_11.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[11].wakeup_ports[3].bits.uop.iw_p1_speculative_child connect slots_11.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[11].wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect slots_11.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[11].wakeup_ports[3].bits.uop.iw_issued_partial_agen connect slots_11.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[11].wakeup_ports[3].bits.uop.iw_issued connect slots_11.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[11].wakeup_ports[3].bits.uop.fu_code[0] connect slots_11.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[11].wakeup_ports[3].bits.uop.fu_code[1] connect slots_11.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[11].wakeup_ports[3].bits.uop.fu_code[2] connect slots_11.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[11].wakeup_ports[3].bits.uop.fu_code[3] connect slots_11.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[11].wakeup_ports[3].bits.uop.fu_code[4] connect slots_11.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[11].wakeup_ports[3].bits.uop.fu_code[5] connect slots_11.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[11].wakeup_ports[3].bits.uop.fu_code[6] connect slots_11.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[11].wakeup_ports[3].bits.uop.fu_code[7] connect slots_11.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[11].wakeup_ports[3].bits.uop.fu_code[8] connect slots_11.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[11].wakeup_ports[3].bits.uop.fu_code[9] connect slots_11.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[11].wakeup_ports[3].bits.uop.iq_type[0] connect slots_11.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[11].wakeup_ports[3].bits.uop.iq_type[1] connect slots_11.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[11].wakeup_ports[3].bits.uop.iq_type[2] connect slots_11.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[11].wakeup_ports[3].bits.uop.iq_type[3] connect slots_11.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[11].wakeup_ports[3].bits.uop.debug_pc connect slots_11.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[11].wakeup_ports[3].bits.uop.is_rvc connect slots_11.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[11].wakeup_ports[3].bits.uop.debug_inst connect slots_11.io.wakeup_ports[3].bits.uop.inst, issue_slots[11].wakeup_ports[3].bits.uop.inst connect slots_11.io.wakeup_ports[3].valid, issue_slots[11].wakeup_ports[3].valid connect slots_11.io.wakeup_ports[4].bits.rebusy, issue_slots[11].wakeup_ports[4].bits.rebusy connect slots_11.io.wakeup_ports[4].bits.speculative_mask, issue_slots[11].wakeup_ports[4].bits.speculative_mask connect slots_11.io.wakeup_ports[4].bits.bypassable, issue_slots[11].wakeup_ports[4].bits.bypassable connect slots_11.io.wakeup_ports[4].bits.uop.debug_tsrc, issue_slots[11].wakeup_ports[4].bits.uop.debug_tsrc connect slots_11.io.wakeup_ports[4].bits.uop.debug_fsrc, issue_slots[11].wakeup_ports[4].bits.uop.debug_fsrc connect slots_11.io.wakeup_ports[4].bits.uop.bp_xcpt_if, issue_slots[11].wakeup_ports[4].bits.uop.bp_xcpt_if connect slots_11.io.wakeup_ports[4].bits.uop.bp_debug_if, issue_slots[11].wakeup_ports[4].bits.uop.bp_debug_if connect slots_11.io.wakeup_ports[4].bits.uop.xcpt_ma_if, issue_slots[11].wakeup_ports[4].bits.uop.xcpt_ma_if connect slots_11.io.wakeup_ports[4].bits.uop.xcpt_ae_if, issue_slots[11].wakeup_ports[4].bits.uop.xcpt_ae_if connect slots_11.io.wakeup_ports[4].bits.uop.xcpt_pf_if, issue_slots[11].wakeup_ports[4].bits.uop.xcpt_pf_if connect slots_11.io.wakeup_ports[4].bits.uop.fp_typ, issue_slots[11].wakeup_ports[4].bits.uop.fp_typ connect slots_11.io.wakeup_ports[4].bits.uop.fp_rm, issue_slots[11].wakeup_ports[4].bits.uop.fp_rm connect slots_11.io.wakeup_ports[4].bits.uop.fp_val, issue_slots[11].wakeup_ports[4].bits.uop.fp_val connect slots_11.io.wakeup_ports[4].bits.uop.fcn_op, issue_slots[11].wakeup_ports[4].bits.uop.fcn_op connect slots_11.io.wakeup_ports[4].bits.uop.fcn_dw, issue_slots[11].wakeup_ports[4].bits.uop.fcn_dw connect slots_11.io.wakeup_ports[4].bits.uop.frs3_en, issue_slots[11].wakeup_ports[4].bits.uop.frs3_en connect slots_11.io.wakeup_ports[4].bits.uop.lrs2_rtype, issue_slots[11].wakeup_ports[4].bits.uop.lrs2_rtype connect slots_11.io.wakeup_ports[4].bits.uop.lrs1_rtype, issue_slots[11].wakeup_ports[4].bits.uop.lrs1_rtype connect slots_11.io.wakeup_ports[4].bits.uop.dst_rtype, issue_slots[11].wakeup_ports[4].bits.uop.dst_rtype connect slots_11.io.wakeup_ports[4].bits.uop.lrs3, issue_slots[11].wakeup_ports[4].bits.uop.lrs3 connect slots_11.io.wakeup_ports[4].bits.uop.lrs2, issue_slots[11].wakeup_ports[4].bits.uop.lrs2 connect slots_11.io.wakeup_ports[4].bits.uop.lrs1, issue_slots[11].wakeup_ports[4].bits.uop.lrs1 connect slots_11.io.wakeup_ports[4].bits.uop.ldst, issue_slots[11].wakeup_ports[4].bits.uop.ldst connect slots_11.io.wakeup_ports[4].bits.uop.ldst_is_rs1, issue_slots[11].wakeup_ports[4].bits.uop.ldst_is_rs1 connect slots_11.io.wakeup_ports[4].bits.uop.csr_cmd, issue_slots[11].wakeup_ports[4].bits.uop.csr_cmd connect slots_11.io.wakeup_ports[4].bits.uop.flush_on_commit, issue_slots[11].wakeup_ports[4].bits.uop.flush_on_commit connect slots_11.io.wakeup_ports[4].bits.uop.is_unique, issue_slots[11].wakeup_ports[4].bits.uop.is_unique connect slots_11.io.wakeup_ports[4].bits.uop.uses_stq, issue_slots[11].wakeup_ports[4].bits.uop.uses_stq connect slots_11.io.wakeup_ports[4].bits.uop.uses_ldq, issue_slots[11].wakeup_ports[4].bits.uop.uses_ldq connect slots_11.io.wakeup_ports[4].bits.uop.mem_signed, issue_slots[11].wakeup_ports[4].bits.uop.mem_signed connect slots_11.io.wakeup_ports[4].bits.uop.mem_size, issue_slots[11].wakeup_ports[4].bits.uop.mem_size connect slots_11.io.wakeup_ports[4].bits.uop.mem_cmd, issue_slots[11].wakeup_ports[4].bits.uop.mem_cmd connect slots_11.io.wakeup_ports[4].bits.uop.exc_cause, issue_slots[11].wakeup_ports[4].bits.uop.exc_cause connect slots_11.io.wakeup_ports[4].bits.uop.exception, issue_slots[11].wakeup_ports[4].bits.uop.exception connect slots_11.io.wakeup_ports[4].bits.uop.stale_pdst, issue_slots[11].wakeup_ports[4].bits.uop.stale_pdst connect slots_11.io.wakeup_ports[4].bits.uop.ppred_busy, issue_slots[11].wakeup_ports[4].bits.uop.ppred_busy connect slots_11.io.wakeup_ports[4].bits.uop.prs3_busy, issue_slots[11].wakeup_ports[4].bits.uop.prs3_busy connect slots_11.io.wakeup_ports[4].bits.uop.prs2_busy, issue_slots[11].wakeup_ports[4].bits.uop.prs2_busy connect slots_11.io.wakeup_ports[4].bits.uop.prs1_busy, issue_slots[11].wakeup_ports[4].bits.uop.prs1_busy connect slots_11.io.wakeup_ports[4].bits.uop.ppred, issue_slots[11].wakeup_ports[4].bits.uop.ppred connect slots_11.io.wakeup_ports[4].bits.uop.prs3, issue_slots[11].wakeup_ports[4].bits.uop.prs3 connect slots_11.io.wakeup_ports[4].bits.uop.prs2, issue_slots[11].wakeup_ports[4].bits.uop.prs2 connect slots_11.io.wakeup_ports[4].bits.uop.prs1, issue_slots[11].wakeup_ports[4].bits.uop.prs1 connect slots_11.io.wakeup_ports[4].bits.uop.pdst, issue_slots[11].wakeup_ports[4].bits.uop.pdst connect slots_11.io.wakeup_ports[4].bits.uop.rxq_idx, issue_slots[11].wakeup_ports[4].bits.uop.rxq_idx connect slots_11.io.wakeup_ports[4].bits.uop.stq_idx, issue_slots[11].wakeup_ports[4].bits.uop.stq_idx connect slots_11.io.wakeup_ports[4].bits.uop.ldq_idx, issue_slots[11].wakeup_ports[4].bits.uop.ldq_idx connect slots_11.io.wakeup_ports[4].bits.uop.rob_idx, issue_slots[11].wakeup_ports[4].bits.uop.rob_idx connect slots_11.io.wakeup_ports[4].bits.uop.fp_ctrl.vec, issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.vec connect slots_11.io.wakeup_ports[4].bits.uop.fp_ctrl.wflags, issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.wflags connect slots_11.io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt, issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect slots_11.io.wakeup_ports[4].bits.uop.fp_ctrl.div, issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.div connect slots_11.io.wakeup_ports[4].bits.uop.fp_ctrl.fma, issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.fma connect slots_11.io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect slots_11.io.wakeup_ports[4].bits.uop.fp_ctrl.toint, issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.toint connect slots_11.io.wakeup_ports[4].bits.uop.fp_ctrl.fromint, issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.fromint connect slots_11.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect slots_11.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect slots_11.io.wakeup_ports[4].bits.uop.fp_ctrl.swap23, issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect slots_11.io.wakeup_ports[4].bits.uop.fp_ctrl.swap12, issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect slots_11.io.wakeup_ports[4].bits.uop.fp_ctrl.ren3, issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect slots_11.io.wakeup_ports[4].bits.uop.fp_ctrl.ren2, issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect slots_11.io.wakeup_ports[4].bits.uop.fp_ctrl.ren1, issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect slots_11.io.wakeup_ports[4].bits.uop.fp_ctrl.wen, issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.wen connect slots_11.io.wakeup_ports[4].bits.uop.fp_ctrl.ldst, issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.ldst connect slots_11.io.wakeup_ports[4].bits.uop.op2_sel, issue_slots[11].wakeup_ports[4].bits.uop.op2_sel connect slots_11.io.wakeup_ports[4].bits.uop.op1_sel, issue_slots[11].wakeup_ports[4].bits.uop.op1_sel connect slots_11.io.wakeup_ports[4].bits.uop.imm_packed, issue_slots[11].wakeup_ports[4].bits.uop.imm_packed connect slots_11.io.wakeup_ports[4].bits.uop.pimm, issue_slots[11].wakeup_ports[4].bits.uop.pimm connect slots_11.io.wakeup_ports[4].bits.uop.imm_sel, issue_slots[11].wakeup_ports[4].bits.uop.imm_sel connect slots_11.io.wakeup_ports[4].bits.uop.imm_rename, issue_slots[11].wakeup_ports[4].bits.uop.imm_rename connect slots_11.io.wakeup_ports[4].bits.uop.taken, issue_slots[11].wakeup_ports[4].bits.uop.taken connect slots_11.io.wakeup_ports[4].bits.uop.pc_lob, issue_slots[11].wakeup_ports[4].bits.uop.pc_lob connect slots_11.io.wakeup_ports[4].bits.uop.edge_inst, issue_slots[11].wakeup_ports[4].bits.uop.edge_inst connect slots_11.io.wakeup_ports[4].bits.uop.ftq_idx, issue_slots[11].wakeup_ports[4].bits.uop.ftq_idx connect slots_11.io.wakeup_ports[4].bits.uop.is_mov, issue_slots[11].wakeup_ports[4].bits.uop.is_mov connect slots_11.io.wakeup_ports[4].bits.uop.is_rocc, issue_slots[11].wakeup_ports[4].bits.uop.is_rocc connect slots_11.io.wakeup_ports[4].bits.uop.is_sys_pc2epc, issue_slots[11].wakeup_ports[4].bits.uop.is_sys_pc2epc connect slots_11.io.wakeup_ports[4].bits.uop.is_eret, issue_slots[11].wakeup_ports[4].bits.uop.is_eret connect slots_11.io.wakeup_ports[4].bits.uop.is_amo, issue_slots[11].wakeup_ports[4].bits.uop.is_amo connect slots_11.io.wakeup_ports[4].bits.uop.is_sfence, issue_slots[11].wakeup_ports[4].bits.uop.is_sfence connect slots_11.io.wakeup_ports[4].bits.uop.is_fencei, issue_slots[11].wakeup_ports[4].bits.uop.is_fencei connect slots_11.io.wakeup_ports[4].bits.uop.is_fence, issue_slots[11].wakeup_ports[4].bits.uop.is_fence connect slots_11.io.wakeup_ports[4].bits.uop.is_sfb, issue_slots[11].wakeup_ports[4].bits.uop.is_sfb connect slots_11.io.wakeup_ports[4].bits.uop.br_type, issue_slots[11].wakeup_ports[4].bits.uop.br_type connect slots_11.io.wakeup_ports[4].bits.uop.br_tag, issue_slots[11].wakeup_ports[4].bits.uop.br_tag connect slots_11.io.wakeup_ports[4].bits.uop.br_mask, issue_slots[11].wakeup_ports[4].bits.uop.br_mask connect slots_11.io.wakeup_ports[4].bits.uop.dis_col_sel, issue_slots[11].wakeup_ports[4].bits.uop.dis_col_sel connect slots_11.io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint, issue_slots[11].wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect slots_11.io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint, issue_slots[11].wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect slots_11.io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint, issue_slots[11].wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect slots_11.io.wakeup_ports[4].bits.uop.iw_p2_speculative_child, issue_slots[11].wakeup_ports[4].bits.uop.iw_p2_speculative_child connect slots_11.io.wakeup_ports[4].bits.uop.iw_p1_speculative_child, issue_slots[11].wakeup_ports[4].bits.uop.iw_p1_speculative_child connect slots_11.io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen, issue_slots[11].wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect slots_11.io.wakeup_ports[4].bits.uop.iw_issued_partial_agen, issue_slots[11].wakeup_ports[4].bits.uop.iw_issued_partial_agen connect slots_11.io.wakeup_ports[4].bits.uop.iw_issued, issue_slots[11].wakeup_ports[4].bits.uop.iw_issued connect slots_11.io.wakeup_ports[4].bits.uop.fu_code[0], issue_slots[11].wakeup_ports[4].bits.uop.fu_code[0] connect slots_11.io.wakeup_ports[4].bits.uop.fu_code[1], issue_slots[11].wakeup_ports[4].bits.uop.fu_code[1] connect slots_11.io.wakeup_ports[4].bits.uop.fu_code[2], issue_slots[11].wakeup_ports[4].bits.uop.fu_code[2] connect slots_11.io.wakeup_ports[4].bits.uop.fu_code[3], issue_slots[11].wakeup_ports[4].bits.uop.fu_code[3] connect slots_11.io.wakeup_ports[4].bits.uop.fu_code[4], issue_slots[11].wakeup_ports[4].bits.uop.fu_code[4] connect slots_11.io.wakeup_ports[4].bits.uop.fu_code[5], issue_slots[11].wakeup_ports[4].bits.uop.fu_code[5] connect slots_11.io.wakeup_ports[4].bits.uop.fu_code[6], issue_slots[11].wakeup_ports[4].bits.uop.fu_code[6] connect slots_11.io.wakeup_ports[4].bits.uop.fu_code[7], issue_slots[11].wakeup_ports[4].bits.uop.fu_code[7] connect slots_11.io.wakeup_ports[4].bits.uop.fu_code[8], issue_slots[11].wakeup_ports[4].bits.uop.fu_code[8] connect slots_11.io.wakeup_ports[4].bits.uop.fu_code[9], issue_slots[11].wakeup_ports[4].bits.uop.fu_code[9] connect slots_11.io.wakeup_ports[4].bits.uop.iq_type[0], issue_slots[11].wakeup_ports[4].bits.uop.iq_type[0] connect slots_11.io.wakeup_ports[4].bits.uop.iq_type[1], issue_slots[11].wakeup_ports[4].bits.uop.iq_type[1] connect slots_11.io.wakeup_ports[4].bits.uop.iq_type[2], issue_slots[11].wakeup_ports[4].bits.uop.iq_type[2] connect slots_11.io.wakeup_ports[4].bits.uop.iq_type[3], issue_slots[11].wakeup_ports[4].bits.uop.iq_type[3] connect slots_11.io.wakeup_ports[4].bits.uop.debug_pc, issue_slots[11].wakeup_ports[4].bits.uop.debug_pc connect slots_11.io.wakeup_ports[4].bits.uop.is_rvc, issue_slots[11].wakeup_ports[4].bits.uop.is_rvc connect slots_11.io.wakeup_ports[4].bits.uop.debug_inst, issue_slots[11].wakeup_ports[4].bits.uop.debug_inst connect slots_11.io.wakeup_ports[4].bits.uop.inst, issue_slots[11].wakeup_ports[4].bits.uop.inst connect slots_11.io.wakeup_ports[4].valid, issue_slots[11].wakeup_ports[4].valid connect slots_11.io.squash_grant, issue_slots[11].squash_grant connect slots_11.io.clear, issue_slots[11].clear connect slots_11.io.kill, issue_slots[11].kill connect slots_11.io.brupdate.b2.target_offset, issue_slots[11].brupdate.b2.target_offset connect slots_11.io.brupdate.b2.jalr_target, issue_slots[11].brupdate.b2.jalr_target connect slots_11.io.brupdate.b2.pc_sel, issue_slots[11].brupdate.b2.pc_sel connect slots_11.io.brupdate.b2.cfi_type, issue_slots[11].brupdate.b2.cfi_type connect slots_11.io.brupdate.b2.taken, issue_slots[11].brupdate.b2.taken connect slots_11.io.brupdate.b2.mispredict, issue_slots[11].brupdate.b2.mispredict connect slots_11.io.brupdate.b2.uop.debug_tsrc, issue_slots[11].brupdate.b2.uop.debug_tsrc connect slots_11.io.brupdate.b2.uop.debug_fsrc, issue_slots[11].brupdate.b2.uop.debug_fsrc connect slots_11.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[11].brupdate.b2.uop.bp_xcpt_if connect slots_11.io.brupdate.b2.uop.bp_debug_if, issue_slots[11].brupdate.b2.uop.bp_debug_if connect slots_11.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[11].brupdate.b2.uop.xcpt_ma_if connect slots_11.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[11].brupdate.b2.uop.xcpt_ae_if connect slots_11.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[11].brupdate.b2.uop.xcpt_pf_if connect slots_11.io.brupdate.b2.uop.fp_typ, issue_slots[11].brupdate.b2.uop.fp_typ connect slots_11.io.brupdate.b2.uop.fp_rm, issue_slots[11].brupdate.b2.uop.fp_rm connect slots_11.io.brupdate.b2.uop.fp_val, issue_slots[11].brupdate.b2.uop.fp_val connect slots_11.io.brupdate.b2.uop.fcn_op, issue_slots[11].brupdate.b2.uop.fcn_op connect slots_11.io.brupdate.b2.uop.fcn_dw, issue_slots[11].brupdate.b2.uop.fcn_dw connect slots_11.io.brupdate.b2.uop.frs3_en, issue_slots[11].brupdate.b2.uop.frs3_en connect slots_11.io.brupdate.b2.uop.lrs2_rtype, issue_slots[11].brupdate.b2.uop.lrs2_rtype connect slots_11.io.brupdate.b2.uop.lrs1_rtype, issue_slots[11].brupdate.b2.uop.lrs1_rtype connect slots_11.io.brupdate.b2.uop.dst_rtype, issue_slots[11].brupdate.b2.uop.dst_rtype connect slots_11.io.brupdate.b2.uop.lrs3, issue_slots[11].brupdate.b2.uop.lrs3 connect slots_11.io.brupdate.b2.uop.lrs2, issue_slots[11].brupdate.b2.uop.lrs2 connect slots_11.io.brupdate.b2.uop.lrs1, issue_slots[11].brupdate.b2.uop.lrs1 connect slots_11.io.brupdate.b2.uop.ldst, issue_slots[11].brupdate.b2.uop.ldst connect slots_11.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[11].brupdate.b2.uop.ldst_is_rs1 connect slots_11.io.brupdate.b2.uop.csr_cmd, issue_slots[11].brupdate.b2.uop.csr_cmd connect slots_11.io.brupdate.b2.uop.flush_on_commit, issue_slots[11].brupdate.b2.uop.flush_on_commit connect slots_11.io.brupdate.b2.uop.is_unique, issue_slots[11].brupdate.b2.uop.is_unique connect slots_11.io.brupdate.b2.uop.uses_stq, issue_slots[11].brupdate.b2.uop.uses_stq connect slots_11.io.brupdate.b2.uop.uses_ldq, issue_slots[11].brupdate.b2.uop.uses_ldq connect slots_11.io.brupdate.b2.uop.mem_signed, issue_slots[11].brupdate.b2.uop.mem_signed connect slots_11.io.brupdate.b2.uop.mem_size, issue_slots[11].brupdate.b2.uop.mem_size connect slots_11.io.brupdate.b2.uop.mem_cmd, issue_slots[11].brupdate.b2.uop.mem_cmd connect slots_11.io.brupdate.b2.uop.exc_cause, issue_slots[11].brupdate.b2.uop.exc_cause connect slots_11.io.brupdate.b2.uop.exception, issue_slots[11].brupdate.b2.uop.exception connect slots_11.io.brupdate.b2.uop.stale_pdst, issue_slots[11].brupdate.b2.uop.stale_pdst connect slots_11.io.brupdate.b2.uop.ppred_busy, issue_slots[11].brupdate.b2.uop.ppred_busy connect slots_11.io.brupdate.b2.uop.prs3_busy, issue_slots[11].brupdate.b2.uop.prs3_busy connect slots_11.io.brupdate.b2.uop.prs2_busy, issue_slots[11].brupdate.b2.uop.prs2_busy connect slots_11.io.brupdate.b2.uop.prs1_busy, issue_slots[11].brupdate.b2.uop.prs1_busy connect slots_11.io.brupdate.b2.uop.ppred, issue_slots[11].brupdate.b2.uop.ppred connect slots_11.io.brupdate.b2.uop.prs3, issue_slots[11].brupdate.b2.uop.prs3 connect slots_11.io.brupdate.b2.uop.prs2, issue_slots[11].brupdate.b2.uop.prs2 connect slots_11.io.brupdate.b2.uop.prs1, issue_slots[11].brupdate.b2.uop.prs1 connect slots_11.io.brupdate.b2.uop.pdst, issue_slots[11].brupdate.b2.uop.pdst connect slots_11.io.brupdate.b2.uop.rxq_idx, issue_slots[11].brupdate.b2.uop.rxq_idx connect slots_11.io.brupdate.b2.uop.stq_idx, issue_slots[11].brupdate.b2.uop.stq_idx connect slots_11.io.brupdate.b2.uop.ldq_idx, issue_slots[11].brupdate.b2.uop.ldq_idx connect slots_11.io.brupdate.b2.uop.rob_idx, issue_slots[11].brupdate.b2.uop.rob_idx connect slots_11.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[11].brupdate.b2.uop.fp_ctrl.vec connect slots_11.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[11].brupdate.b2.uop.fp_ctrl.wflags connect slots_11.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[11].brupdate.b2.uop.fp_ctrl.sqrt connect slots_11.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[11].brupdate.b2.uop.fp_ctrl.div connect slots_11.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[11].brupdate.b2.uop.fp_ctrl.fma connect slots_11.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[11].brupdate.b2.uop.fp_ctrl.fastpipe connect slots_11.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[11].brupdate.b2.uop.fp_ctrl.toint connect slots_11.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[11].brupdate.b2.uop.fp_ctrl.fromint connect slots_11.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[11].brupdate.b2.uop.fp_ctrl.typeTagOut connect slots_11.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[11].brupdate.b2.uop.fp_ctrl.typeTagIn connect slots_11.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[11].brupdate.b2.uop.fp_ctrl.swap23 connect slots_11.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[11].brupdate.b2.uop.fp_ctrl.swap12 connect slots_11.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[11].brupdate.b2.uop.fp_ctrl.ren3 connect slots_11.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[11].brupdate.b2.uop.fp_ctrl.ren2 connect slots_11.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[11].brupdate.b2.uop.fp_ctrl.ren1 connect slots_11.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[11].brupdate.b2.uop.fp_ctrl.wen connect slots_11.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[11].brupdate.b2.uop.fp_ctrl.ldst connect slots_11.io.brupdate.b2.uop.op2_sel, issue_slots[11].brupdate.b2.uop.op2_sel connect slots_11.io.brupdate.b2.uop.op1_sel, issue_slots[11].brupdate.b2.uop.op1_sel connect slots_11.io.brupdate.b2.uop.imm_packed, issue_slots[11].brupdate.b2.uop.imm_packed connect slots_11.io.brupdate.b2.uop.pimm, issue_slots[11].brupdate.b2.uop.pimm connect slots_11.io.brupdate.b2.uop.imm_sel, issue_slots[11].brupdate.b2.uop.imm_sel connect slots_11.io.brupdate.b2.uop.imm_rename, issue_slots[11].brupdate.b2.uop.imm_rename connect slots_11.io.brupdate.b2.uop.taken, issue_slots[11].brupdate.b2.uop.taken connect slots_11.io.brupdate.b2.uop.pc_lob, issue_slots[11].brupdate.b2.uop.pc_lob connect slots_11.io.brupdate.b2.uop.edge_inst, issue_slots[11].brupdate.b2.uop.edge_inst connect slots_11.io.brupdate.b2.uop.ftq_idx, issue_slots[11].brupdate.b2.uop.ftq_idx connect slots_11.io.brupdate.b2.uop.is_mov, issue_slots[11].brupdate.b2.uop.is_mov connect slots_11.io.brupdate.b2.uop.is_rocc, issue_slots[11].brupdate.b2.uop.is_rocc connect slots_11.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[11].brupdate.b2.uop.is_sys_pc2epc connect slots_11.io.brupdate.b2.uop.is_eret, issue_slots[11].brupdate.b2.uop.is_eret connect slots_11.io.brupdate.b2.uop.is_amo, issue_slots[11].brupdate.b2.uop.is_amo connect slots_11.io.brupdate.b2.uop.is_sfence, issue_slots[11].brupdate.b2.uop.is_sfence connect slots_11.io.brupdate.b2.uop.is_fencei, issue_slots[11].brupdate.b2.uop.is_fencei connect slots_11.io.brupdate.b2.uop.is_fence, issue_slots[11].brupdate.b2.uop.is_fence connect slots_11.io.brupdate.b2.uop.is_sfb, issue_slots[11].brupdate.b2.uop.is_sfb connect slots_11.io.brupdate.b2.uop.br_type, issue_slots[11].brupdate.b2.uop.br_type connect slots_11.io.brupdate.b2.uop.br_tag, issue_slots[11].brupdate.b2.uop.br_tag connect slots_11.io.brupdate.b2.uop.br_mask, issue_slots[11].brupdate.b2.uop.br_mask connect slots_11.io.brupdate.b2.uop.dis_col_sel, issue_slots[11].brupdate.b2.uop.dis_col_sel connect slots_11.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[11].brupdate.b2.uop.iw_p3_bypass_hint connect slots_11.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[11].brupdate.b2.uop.iw_p2_bypass_hint connect slots_11.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[11].brupdate.b2.uop.iw_p1_bypass_hint connect slots_11.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[11].brupdate.b2.uop.iw_p2_speculative_child connect slots_11.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[11].brupdate.b2.uop.iw_p1_speculative_child connect slots_11.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[11].brupdate.b2.uop.iw_issued_partial_dgen connect slots_11.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[11].brupdate.b2.uop.iw_issued_partial_agen connect slots_11.io.brupdate.b2.uop.iw_issued, issue_slots[11].brupdate.b2.uop.iw_issued connect slots_11.io.brupdate.b2.uop.fu_code[0], issue_slots[11].brupdate.b2.uop.fu_code[0] connect slots_11.io.brupdate.b2.uop.fu_code[1], issue_slots[11].brupdate.b2.uop.fu_code[1] connect slots_11.io.brupdate.b2.uop.fu_code[2], issue_slots[11].brupdate.b2.uop.fu_code[2] connect slots_11.io.brupdate.b2.uop.fu_code[3], issue_slots[11].brupdate.b2.uop.fu_code[3] connect slots_11.io.brupdate.b2.uop.fu_code[4], issue_slots[11].brupdate.b2.uop.fu_code[4] connect slots_11.io.brupdate.b2.uop.fu_code[5], issue_slots[11].brupdate.b2.uop.fu_code[5] connect slots_11.io.brupdate.b2.uop.fu_code[6], issue_slots[11].brupdate.b2.uop.fu_code[6] connect slots_11.io.brupdate.b2.uop.fu_code[7], issue_slots[11].brupdate.b2.uop.fu_code[7] connect slots_11.io.brupdate.b2.uop.fu_code[8], issue_slots[11].brupdate.b2.uop.fu_code[8] connect slots_11.io.brupdate.b2.uop.fu_code[9], issue_slots[11].brupdate.b2.uop.fu_code[9] connect slots_11.io.brupdate.b2.uop.iq_type[0], issue_slots[11].brupdate.b2.uop.iq_type[0] connect slots_11.io.brupdate.b2.uop.iq_type[1], issue_slots[11].brupdate.b2.uop.iq_type[1] connect slots_11.io.brupdate.b2.uop.iq_type[2], issue_slots[11].brupdate.b2.uop.iq_type[2] connect slots_11.io.brupdate.b2.uop.iq_type[3], issue_slots[11].brupdate.b2.uop.iq_type[3] connect slots_11.io.brupdate.b2.uop.debug_pc, issue_slots[11].brupdate.b2.uop.debug_pc connect slots_11.io.brupdate.b2.uop.is_rvc, issue_slots[11].brupdate.b2.uop.is_rvc connect slots_11.io.brupdate.b2.uop.debug_inst, issue_slots[11].brupdate.b2.uop.debug_inst connect slots_11.io.brupdate.b2.uop.inst, issue_slots[11].brupdate.b2.uop.inst connect slots_11.io.brupdate.b1.mispredict_mask, issue_slots[11].brupdate.b1.mispredict_mask connect slots_11.io.brupdate.b1.resolve_mask, issue_slots[11].brupdate.b1.resolve_mask connect issue_slots[11].out_uop.debug_tsrc, slots_11.io.out_uop.debug_tsrc connect issue_slots[11].out_uop.debug_fsrc, slots_11.io.out_uop.debug_fsrc connect issue_slots[11].out_uop.bp_xcpt_if, slots_11.io.out_uop.bp_xcpt_if connect issue_slots[11].out_uop.bp_debug_if, slots_11.io.out_uop.bp_debug_if connect issue_slots[11].out_uop.xcpt_ma_if, slots_11.io.out_uop.xcpt_ma_if connect issue_slots[11].out_uop.xcpt_ae_if, slots_11.io.out_uop.xcpt_ae_if connect issue_slots[11].out_uop.xcpt_pf_if, slots_11.io.out_uop.xcpt_pf_if connect issue_slots[11].out_uop.fp_typ, slots_11.io.out_uop.fp_typ connect issue_slots[11].out_uop.fp_rm, slots_11.io.out_uop.fp_rm connect issue_slots[11].out_uop.fp_val, slots_11.io.out_uop.fp_val connect issue_slots[11].out_uop.fcn_op, slots_11.io.out_uop.fcn_op connect issue_slots[11].out_uop.fcn_dw, slots_11.io.out_uop.fcn_dw connect issue_slots[11].out_uop.frs3_en, slots_11.io.out_uop.frs3_en connect issue_slots[11].out_uop.lrs2_rtype, slots_11.io.out_uop.lrs2_rtype connect issue_slots[11].out_uop.lrs1_rtype, slots_11.io.out_uop.lrs1_rtype connect issue_slots[11].out_uop.dst_rtype, slots_11.io.out_uop.dst_rtype connect issue_slots[11].out_uop.lrs3, slots_11.io.out_uop.lrs3 connect issue_slots[11].out_uop.lrs2, slots_11.io.out_uop.lrs2 connect issue_slots[11].out_uop.lrs1, slots_11.io.out_uop.lrs1 connect issue_slots[11].out_uop.ldst, slots_11.io.out_uop.ldst connect issue_slots[11].out_uop.ldst_is_rs1, slots_11.io.out_uop.ldst_is_rs1 connect issue_slots[11].out_uop.csr_cmd, slots_11.io.out_uop.csr_cmd connect issue_slots[11].out_uop.flush_on_commit, slots_11.io.out_uop.flush_on_commit connect issue_slots[11].out_uop.is_unique, slots_11.io.out_uop.is_unique connect issue_slots[11].out_uop.uses_stq, slots_11.io.out_uop.uses_stq connect issue_slots[11].out_uop.uses_ldq, slots_11.io.out_uop.uses_ldq connect issue_slots[11].out_uop.mem_signed, slots_11.io.out_uop.mem_signed connect issue_slots[11].out_uop.mem_size, slots_11.io.out_uop.mem_size connect issue_slots[11].out_uop.mem_cmd, slots_11.io.out_uop.mem_cmd connect issue_slots[11].out_uop.exc_cause, slots_11.io.out_uop.exc_cause connect issue_slots[11].out_uop.exception, slots_11.io.out_uop.exception connect issue_slots[11].out_uop.stale_pdst, slots_11.io.out_uop.stale_pdst connect issue_slots[11].out_uop.ppred_busy, slots_11.io.out_uop.ppred_busy connect issue_slots[11].out_uop.prs3_busy, slots_11.io.out_uop.prs3_busy connect issue_slots[11].out_uop.prs2_busy, slots_11.io.out_uop.prs2_busy connect issue_slots[11].out_uop.prs1_busy, slots_11.io.out_uop.prs1_busy connect issue_slots[11].out_uop.ppred, slots_11.io.out_uop.ppred connect issue_slots[11].out_uop.prs3, slots_11.io.out_uop.prs3 connect issue_slots[11].out_uop.prs2, slots_11.io.out_uop.prs2 connect issue_slots[11].out_uop.prs1, slots_11.io.out_uop.prs1 connect issue_slots[11].out_uop.pdst, slots_11.io.out_uop.pdst connect issue_slots[11].out_uop.rxq_idx, slots_11.io.out_uop.rxq_idx connect issue_slots[11].out_uop.stq_idx, slots_11.io.out_uop.stq_idx connect issue_slots[11].out_uop.ldq_idx, slots_11.io.out_uop.ldq_idx connect issue_slots[11].out_uop.rob_idx, slots_11.io.out_uop.rob_idx connect issue_slots[11].out_uop.fp_ctrl.vec, slots_11.io.out_uop.fp_ctrl.vec connect issue_slots[11].out_uop.fp_ctrl.wflags, slots_11.io.out_uop.fp_ctrl.wflags connect issue_slots[11].out_uop.fp_ctrl.sqrt, slots_11.io.out_uop.fp_ctrl.sqrt connect issue_slots[11].out_uop.fp_ctrl.div, slots_11.io.out_uop.fp_ctrl.div connect issue_slots[11].out_uop.fp_ctrl.fma, slots_11.io.out_uop.fp_ctrl.fma connect issue_slots[11].out_uop.fp_ctrl.fastpipe, slots_11.io.out_uop.fp_ctrl.fastpipe connect issue_slots[11].out_uop.fp_ctrl.toint, slots_11.io.out_uop.fp_ctrl.toint connect issue_slots[11].out_uop.fp_ctrl.fromint, slots_11.io.out_uop.fp_ctrl.fromint connect issue_slots[11].out_uop.fp_ctrl.typeTagOut, slots_11.io.out_uop.fp_ctrl.typeTagOut connect issue_slots[11].out_uop.fp_ctrl.typeTagIn, slots_11.io.out_uop.fp_ctrl.typeTagIn connect issue_slots[11].out_uop.fp_ctrl.swap23, slots_11.io.out_uop.fp_ctrl.swap23 connect issue_slots[11].out_uop.fp_ctrl.swap12, slots_11.io.out_uop.fp_ctrl.swap12 connect issue_slots[11].out_uop.fp_ctrl.ren3, slots_11.io.out_uop.fp_ctrl.ren3 connect issue_slots[11].out_uop.fp_ctrl.ren2, slots_11.io.out_uop.fp_ctrl.ren2 connect issue_slots[11].out_uop.fp_ctrl.ren1, slots_11.io.out_uop.fp_ctrl.ren1 connect issue_slots[11].out_uop.fp_ctrl.wen, slots_11.io.out_uop.fp_ctrl.wen connect issue_slots[11].out_uop.fp_ctrl.ldst, slots_11.io.out_uop.fp_ctrl.ldst connect issue_slots[11].out_uop.op2_sel, slots_11.io.out_uop.op2_sel connect issue_slots[11].out_uop.op1_sel, slots_11.io.out_uop.op1_sel connect issue_slots[11].out_uop.imm_packed, slots_11.io.out_uop.imm_packed connect issue_slots[11].out_uop.pimm, slots_11.io.out_uop.pimm connect issue_slots[11].out_uop.imm_sel, slots_11.io.out_uop.imm_sel connect issue_slots[11].out_uop.imm_rename, slots_11.io.out_uop.imm_rename connect issue_slots[11].out_uop.taken, slots_11.io.out_uop.taken connect issue_slots[11].out_uop.pc_lob, slots_11.io.out_uop.pc_lob connect issue_slots[11].out_uop.edge_inst, slots_11.io.out_uop.edge_inst connect issue_slots[11].out_uop.ftq_idx, slots_11.io.out_uop.ftq_idx connect issue_slots[11].out_uop.is_mov, slots_11.io.out_uop.is_mov connect issue_slots[11].out_uop.is_rocc, slots_11.io.out_uop.is_rocc connect issue_slots[11].out_uop.is_sys_pc2epc, slots_11.io.out_uop.is_sys_pc2epc connect issue_slots[11].out_uop.is_eret, slots_11.io.out_uop.is_eret connect issue_slots[11].out_uop.is_amo, slots_11.io.out_uop.is_amo connect issue_slots[11].out_uop.is_sfence, slots_11.io.out_uop.is_sfence connect issue_slots[11].out_uop.is_fencei, slots_11.io.out_uop.is_fencei connect issue_slots[11].out_uop.is_fence, slots_11.io.out_uop.is_fence connect issue_slots[11].out_uop.is_sfb, slots_11.io.out_uop.is_sfb connect issue_slots[11].out_uop.br_type, slots_11.io.out_uop.br_type connect issue_slots[11].out_uop.br_tag, slots_11.io.out_uop.br_tag connect issue_slots[11].out_uop.br_mask, slots_11.io.out_uop.br_mask connect issue_slots[11].out_uop.dis_col_sel, slots_11.io.out_uop.dis_col_sel connect issue_slots[11].out_uop.iw_p3_bypass_hint, slots_11.io.out_uop.iw_p3_bypass_hint connect issue_slots[11].out_uop.iw_p2_bypass_hint, slots_11.io.out_uop.iw_p2_bypass_hint connect issue_slots[11].out_uop.iw_p1_bypass_hint, slots_11.io.out_uop.iw_p1_bypass_hint connect issue_slots[11].out_uop.iw_p2_speculative_child, slots_11.io.out_uop.iw_p2_speculative_child connect issue_slots[11].out_uop.iw_p1_speculative_child, slots_11.io.out_uop.iw_p1_speculative_child connect issue_slots[11].out_uop.iw_issued_partial_dgen, slots_11.io.out_uop.iw_issued_partial_dgen connect issue_slots[11].out_uop.iw_issued_partial_agen, slots_11.io.out_uop.iw_issued_partial_agen connect issue_slots[11].out_uop.iw_issued, slots_11.io.out_uop.iw_issued connect issue_slots[11].out_uop.fu_code[0], slots_11.io.out_uop.fu_code[0] connect issue_slots[11].out_uop.fu_code[1], slots_11.io.out_uop.fu_code[1] connect issue_slots[11].out_uop.fu_code[2], slots_11.io.out_uop.fu_code[2] connect issue_slots[11].out_uop.fu_code[3], slots_11.io.out_uop.fu_code[3] connect issue_slots[11].out_uop.fu_code[4], slots_11.io.out_uop.fu_code[4] connect issue_slots[11].out_uop.fu_code[5], slots_11.io.out_uop.fu_code[5] connect issue_slots[11].out_uop.fu_code[6], slots_11.io.out_uop.fu_code[6] connect issue_slots[11].out_uop.fu_code[7], slots_11.io.out_uop.fu_code[7] connect issue_slots[11].out_uop.fu_code[8], slots_11.io.out_uop.fu_code[8] connect issue_slots[11].out_uop.fu_code[9], slots_11.io.out_uop.fu_code[9] connect issue_slots[11].out_uop.iq_type[0], slots_11.io.out_uop.iq_type[0] connect issue_slots[11].out_uop.iq_type[1], slots_11.io.out_uop.iq_type[1] connect issue_slots[11].out_uop.iq_type[2], slots_11.io.out_uop.iq_type[2] connect issue_slots[11].out_uop.iq_type[3], slots_11.io.out_uop.iq_type[3] connect issue_slots[11].out_uop.debug_pc, slots_11.io.out_uop.debug_pc connect issue_slots[11].out_uop.is_rvc, slots_11.io.out_uop.is_rvc connect issue_slots[11].out_uop.debug_inst, slots_11.io.out_uop.debug_inst connect issue_slots[11].out_uop.inst, slots_11.io.out_uop.inst connect slots_11.io.in_uop.bits.debug_tsrc, issue_slots[11].in_uop.bits.debug_tsrc connect slots_11.io.in_uop.bits.debug_fsrc, issue_slots[11].in_uop.bits.debug_fsrc connect slots_11.io.in_uop.bits.bp_xcpt_if, issue_slots[11].in_uop.bits.bp_xcpt_if connect slots_11.io.in_uop.bits.bp_debug_if, issue_slots[11].in_uop.bits.bp_debug_if connect slots_11.io.in_uop.bits.xcpt_ma_if, issue_slots[11].in_uop.bits.xcpt_ma_if connect slots_11.io.in_uop.bits.xcpt_ae_if, issue_slots[11].in_uop.bits.xcpt_ae_if connect slots_11.io.in_uop.bits.xcpt_pf_if, issue_slots[11].in_uop.bits.xcpt_pf_if connect slots_11.io.in_uop.bits.fp_typ, issue_slots[11].in_uop.bits.fp_typ connect slots_11.io.in_uop.bits.fp_rm, issue_slots[11].in_uop.bits.fp_rm connect slots_11.io.in_uop.bits.fp_val, issue_slots[11].in_uop.bits.fp_val connect slots_11.io.in_uop.bits.fcn_op, issue_slots[11].in_uop.bits.fcn_op connect slots_11.io.in_uop.bits.fcn_dw, issue_slots[11].in_uop.bits.fcn_dw connect slots_11.io.in_uop.bits.frs3_en, issue_slots[11].in_uop.bits.frs3_en connect slots_11.io.in_uop.bits.lrs2_rtype, issue_slots[11].in_uop.bits.lrs2_rtype connect slots_11.io.in_uop.bits.lrs1_rtype, issue_slots[11].in_uop.bits.lrs1_rtype connect slots_11.io.in_uop.bits.dst_rtype, issue_slots[11].in_uop.bits.dst_rtype connect slots_11.io.in_uop.bits.lrs3, issue_slots[11].in_uop.bits.lrs3 connect slots_11.io.in_uop.bits.lrs2, issue_slots[11].in_uop.bits.lrs2 connect slots_11.io.in_uop.bits.lrs1, issue_slots[11].in_uop.bits.lrs1 connect slots_11.io.in_uop.bits.ldst, issue_slots[11].in_uop.bits.ldst connect slots_11.io.in_uop.bits.ldst_is_rs1, issue_slots[11].in_uop.bits.ldst_is_rs1 connect slots_11.io.in_uop.bits.csr_cmd, issue_slots[11].in_uop.bits.csr_cmd connect slots_11.io.in_uop.bits.flush_on_commit, issue_slots[11].in_uop.bits.flush_on_commit connect slots_11.io.in_uop.bits.is_unique, issue_slots[11].in_uop.bits.is_unique connect slots_11.io.in_uop.bits.uses_stq, issue_slots[11].in_uop.bits.uses_stq connect slots_11.io.in_uop.bits.uses_ldq, issue_slots[11].in_uop.bits.uses_ldq connect slots_11.io.in_uop.bits.mem_signed, issue_slots[11].in_uop.bits.mem_signed connect slots_11.io.in_uop.bits.mem_size, issue_slots[11].in_uop.bits.mem_size connect slots_11.io.in_uop.bits.mem_cmd, issue_slots[11].in_uop.bits.mem_cmd connect slots_11.io.in_uop.bits.exc_cause, issue_slots[11].in_uop.bits.exc_cause connect slots_11.io.in_uop.bits.exception, issue_slots[11].in_uop.bits.exception connect slots_11.io.in_uop.bits.stale_pdst, issue_slots[11].in_uop.bits.stale_pdst connect slots_11.io.in_uop.bits.ppred_busy, issue_slots[11].in_uop.bits.ppred_busy connect slots_11.io.in_uop.bits.prs3_busy, issue_slots[11].in_uop.bits.prs3_busy connect slots_11.io.in_uop.bits.prs2_busy, issue_slots[11].in_uop.bits.prs2_busy connect slots_11.io.in_uop.bits.prs1_busy, issue_slots[11].in_uop.bits.prs1_busy connect slots_11.io.in_uop.bits.ppred, issue_slots[11].in_uop.bits.ppred connect slots_11.io.in_uop.bits.prs3, issue_slots[11].in_uop.bits.prs3 connect slots_11.io.in_uop.bits.prs2, issue_slots[11].in_uop.bits.prs2 connect slots_11.io.in_uop.bits.prs1, issue_slots[11].in_uop.bits.prs1 connect slots_11.io.in_uop.bits.pdst, issue_slots[11].in_uop.bits.pdst connect slots_11.io.in_uop.bits.rxq_idx, issue_slots[11].in_uop.bits.rxq_idx connect slots_11.io.in_uop.bits.stq_idx, issue_slots[11].in_uop.bits.stq_idx connect slots_11.io.in_uop.bits.ldq_idx, issue_slots[11].in_uop.bits.ldq_idx connect slots_11.io.in_uop.bits.rob_idx, issue_slots[11].in_uop.bits.rob_idx connect slots_11.io.in_uop.bits.fp_ctrl.vec, issue_slots[11].in_uop.bits.fp_ctrl.vec connect slots_11.io.in_uop.bits.fp_ctrl.wflags, issue_slots[11].in_uop.bits.fp_ctrl.wflags connect slots_11.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[11].in_uop.bits.fp_ctrl.sqrt connect slots_11.io.in_uop.bits.fp_ctrl.div, issue_slots[11].in_uop.bits.fp_ctrl.div connect slots_11.io.in_uop.bits.fp_ctrl.fma, issue_slots[11].in_uop.bits.fp_ctrl.fma connect slots_11.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[11].in_uop.bits.fp_ctrl.fastpipe connect slots_11.io.in_uop.bits.fp_ctrl.toint, issue_slots[11].in_uop.bits.fp_ctrl.toint connect slots_11.io.in_uop.bits.fp_ctrl.fromint, issue_slots[11].in_uop.bits.fp_ctrl.fromint connect slots_11.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[11].in_uop.bits.fp_ctrl.typeTagOut connect slots_11.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[11].in_uop.bits.fp_ctrl.typeTagIn connect slots_11.io.in_uop.bits.fp_ctrl.swap23, issue_slots[11].in_uop.bits.fp_ctrl.swap23 connect slots_11.io.in_uop.bits.fp_ctrl.swap12, issue_slots[11].in_uop.bits.fp_ctrl.swap12 connect slots_11.io.in_uop.bits.fp_ctrl.ren3, issue_slots[11].in_uop.bits.fp_ctrl.ren3 connect slots_11.io.in_uop.bits.fp_ctrl.ren2, issue_slots[11].in_uop.bits.fp_ctrl.ren2 connect slots_11.io.in_uop.bits.fp_ctrl.ren1, issue_slots[11].in_uop.bits.fp_ctrl.ren1 connect slots_11.io.in_uop.bits.fp_ctrl.wen, issue_slots[11].in_uop.bits.fp_ctrl.wen connect slots_11.io.in_uop.bits.fp_ctrl.ldst, issue_slots[11].in_uop.bits.fp_ctrl.ldst connect slots_11.io.in_uop.bits.op2_sel, issue_slots[11].in_uop.bits.op2_sel connect slots_11.io.in_uop.bits.op1_sel, issue_slots[11].in_uop.bits.op1_sel connect slots_11.io.in_uop.bits.imm_packed, issue_slots[11].in_uop.bits.imm_packed connect slots_11.io.in_uop.bits.pimm, issue_slots[11].in_uop.bits.pimm connect slots_11.io.in_uop.bits.imm_sel, issue_slots[11].in_uop.bits.imm_sel connect slots_11.io.in_uop.bits.imm_rename, issue_slots[11].in_uop.bits.imm_rename connect slots_11.io.in_uop.bits.taken, issue_slots[11].in_uop.bits.taken connect slots_11.io.in_uop.bits.pc_lob, issue_slots[11].in_uop.bits.pc_lob connect slots_11.io.in_uop.bits.edge_inst, issue_slots[11].in_uop.bits.edge_inst connect slots_11.io.in_uop.bits.ftq_idx, issue_slots[11].in_uop.bits.ftq_idx connect slots_11.io.in_uop.bits.is_mov, issue_slots[11].in_uop.bits.is_mov connect slots_11.io.in_uop.bits.is_rocc, issue_slots[11].in_uop.bits.is_rocc connect slots_11.io.in_uop.bits.is_sys_pc2epc, issue_slots[11].in_uop.bits.is_sys_pc2epc connect slots_11.io.in_uop.bits.is_eret, issue_slots[11].in_uop.bits.is_eret connect slots_11.io.in_uop.bits.is_amo, issue_slots[11].in_uop.bits.is_amo connect slots_11.io.in_uop.bits.is_sfence, issue_slots[11].in_uop.bits.is_sfence connect slots_11.io.in_uop.bits.is_fencei, issue_slots[11].in_uop.bits.is_fencei connect slots_11.io.in_uop.bits.is_fence, issue_slots[11].in_uop.bits.is_fence connect slots_11.io.in_uop.bits.is_sfb, issue_slots[11].in_uop.bits.is_sfb connect slots_11.io.in_uop.bits.br_type, issue_slots[11].in_uop.bits.br_type connect slots_11.io.in_uop.bits.br_tag, issue_slots[11].in_uop.bits.br_tag connect slots_11.io.in_uop.bits.br_mask, issue_slots[11].in_uop.bits.br_mask connect slots_11.io.in_uop.bits.dis_col_sel, issue_slots[11].in_uop.bits.dis_col_sel connect slots_11.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[11].in_uop.bits.iw_p3_bypass_hint connect slots_11.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[11].in_uop.bits.iw_p2_bypass_hint connect slots_11.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[11].in_uop.bits.iw_p1_bypass_hint connect slots_11.io.in_uop.bits.iw_p2_speculative_child, issue_slots[11].in_uop.bits.iw_p2_speculative_child connect slots_11.io.in_uop.bits.iw_p1_speculative_child, issue_slots[11].in_uop.bits.iw_p1_speculative_child connect slots_11.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[11].in_uop.bits.iw_issued_partial_dgen connect slots_11.io.in_uop.bits.iw_issued_partial_agen, issue_slots[11].in_uop.bits.iw_issued_partial_agen connect slots_11.io.in_uop.bits.iw_issued, issue_slots[11].in_uop.bits.iw_issued connect slots_11.io.in_uop.bits.fu_code[0], issue_slots[11].in_uop.bits.fu_code[0] connect slots_11.io.in_uop.bits.fu_code[1], issue_slots[11].in_uop.bits.fu_code[1] connect slots_11.io.in_uop.bits.fu_code[2], issue_slots[11].in_uop.bits.fu_code[2] connect slots_11.io.in_uop.bits.fu_code[3], issue_slots[11].in_uop.bits.fu_code[3] connect slots_11.io.in_uop.bits.fu_code[4], issue_slots[11].in_uop.bits.fu_code[4] connect slots_11.io.in_uop.bits.fu_code[5], issue_slots[11].in_uop.bits.fu_code[5] connect slots_11.io.in_uop.bits.fu_code[6], issue_slots[11].in_uop.bits.fu_code[6] connect slots_11.io.in_uop.bits.fu_code[7], issue_slots[11].in_uop.bits.fu_code[7] connect slots_11.io.in_uop.bits.fu_code[8], issue_slots[11].in_uop.bits.fu_code[8] connect slots_11.io.in_uop.bits.fu_code[9], issue_slots[11].in_uop.bits.fu_code[9] connect slots_11.io.in_uop.bits.iq_type[0], issue_slots[11].in_uop.bits.iq_type[0] connect slots_11.io.in_uop.bits.iq_type[1], issue_slots[11].in_uop.bits.iq_type[1] connect slots_11.io.in_uop.bits.iq_type[2], issue_slots[11].in_uop.bits.iq_type[2] connect slots_11.io.in_uop.bits.iq_type[3], issue_slots[11].in_uop.bits.iq_type[3] connect slots_11.io.in_uop.bits.debug_pc, issue_slots[11].in_uop.bits.debug_pc connect slots_11.io.in_uop.bits.is_rvc, issue_slots[11].in_uop.bits.is_rvc connect slots_11.io.in_uop.bits.debug_inst, issue_slots[11].in_uop.bits.debug_inst connect slots_11.io.in_uop.bits.inst, issue_slots[11].in_uop.bits.inst connect slots_11.io.in_uop.valid, issue_slots[11].in_uop.valid connect issue_slots[11].iss_uop.debug_tsrc, slots_11.io.iss_uop.debug_tsrc connect issue_slots[11].iss_uop.debug_fsrc, slots_11.io.iss_uop.debug_fsrc connect issue_slots[11].iss_uop.bp_xcpt_if, slots_11.io.iss_uop.bp_xcpt_if connect issue_slots[11].iss_uop.bp_debug_if, slots_11.io.iss_uop.bp_debug_if connect issue_slots[11].iss_uop.xcpt_ma_if, slots_11.io.iss_uop.xcpt_ma_if connect issue_slots[11].iss_uop.xcpt_ae_if, slots_11.io.iss_uop.xcpt_ae_if connect issue_slots[11].iss_uop.xcpt_pf_if, slots_11.io.iss_uop.xcpt_pf_if connect issue_slots[11].iss_uop.fp_typ, slots_11.io.iss_uop.fp_typ connect issue_slots[11].iss_uop.fp_rm, slots_11.io.iss_uop.fp_rm connect issue_slots[11].iss_uop.fp_val, slots_11.io.iss_uop.fp_val connect issue_slots[11].iss_uop.fcn_op, slots_11.io.iss_uop.fcn_op connect issue_slots[11].iss_uop.fcn_dw, slots_11.io.iss_uop.fcn_dw connect issue_slots[11].iss_uop.frs3_en, slots_11.io.iss_uop.frs3_en connect issue_slots[11].iss_uop.lrs2_rtype, slots_11.io.iss_uop.lrs2_rtype connect issue_slots[11].iss_uop.lrs1_rtype, slots_11.io.iss_uop.lrs1_rtype connect issue_slots[11].iss_uop.dst_rtype, slots_11.io.iss_uop.dst_rtype connect issue_slots[11].iss_uop.lrs3, slots_11.io.iss_uop.lrs3 connect issue_slots[11].iss_uop.lrs2, slots_11.io.iss_uop.lrs2 connect issue_slots[11].iss_uop.lrs1, slots_11.io.iss_uop.lrs1 connect issue_slots[11].iss_uop.ldst, slots_11.io.iss_uop.ldst connect issue_slots[11].iss_uop.ldst_is_rs1, slots_11.io.iss_uop.ldst_is_rs1 connect issue_slots[11].iss_uop.csr_cmd, slots_11.io.iss_uop.csr_cmd connect issue_slots[11].iss_uop.flush_on_commit, slots_11.io.iss_uop.flush_on_commit connect issue_slots[11].iss_uop.is_unique, slots_11.io.iss_uop.is_unique connect issue_slots[11].iss_uop.uses_stq, slots_11.io.iss_uop.uses_stq connect issue_slots[11].iss_uop.uses_ldq, slots_11.io.iss_uop.uses_ldq connect issue_slots[11].iss_uop.mem_signed, slots_11.io.iss_uop.mem_signed connect issue_slots[11].iss_uop.mem_size, slots_11.io.iss_uop.mem_size connect issue_slots[11].iss_uop.mem_cmd, slots_11.io.iss_uop.mem_cmd connect issue_slots[11].iss_uop.exc_cause, slots_11.io.iss_uop.exc_cause connect issue_slots[11].iss_uop.exception, slots_11.io.iss_uop.exception connect issue_slots[11].iss_uop.stale_pdst, slots_11.io.iss_uop.stale_pdst connect issue_slots[11].iss_uop.ppred_busy, slots_11.io.iss_uop.ppred_busy connect issue_slots[11].iss_uop.prs3_busy, slots_11.io.iss_uop.prs3_busy connect issue_slots[11].iss_uop.prs2_busy, slots_11.io.iss_uop.prs2_busy connect issue_slots[11].iss_uop.prs1_busy, slots_11.io.iss_uop.prs1_busy connect issue_slots[11].iss_uop.ppred, slots_11.io.iss_uop.ppred connect issue_slots[11].iss_uop.prs3, slots_11.io.iss_uop.prs3 connect issue_slots[11].iss_uop.prs2, slots_11.io.iss_uop.prs2 connect issue_slots[11].iss_uop.prs1, slots_11.io.iss_uop.prs1 connect issue_slots[11].iss_uop.pdst, slots_11.io.iss_uop.pdst connect issue_slots[11].iss_uop.rxq_idx, slots_11.io.iss_uop.rxq_idx connect issue_slots[11].iss_uop.stq_idx, slots_11.io.iss_uop.stq_idx connect issue_slots[11].iss_uop.ldq_idx, slots_11.io.iss_uop.ldq_idx connect issue_slots[11].iss_uop.rob_idx, slots_11.io.iss_uop.rob_idx connect issue_slots[11].iss_uop.fp_ctrl.vec, slots_11.io.iss_uop.fp_ctrl.vec connect issue_slots[11].iss_uop.fp_ctrl.wflags, slots_11.io.iss_uop.fp_ctrl.wflags connect issue_slots[11].iss_uop.fp_ctrl.sqrt, slots_11.io.iss_uop.fp_ctrl.sqrt connect issue_slots[11].iss_uop.fp_ctrl.div, slots_11.io.iss_uop.fp_ctrl.div connect issue_slots[11].iss_uop.fp_ctrl.fma, slots_11.io.iss_uop.fp_ctrl.fma connect issue_slots[11].iss_uop.fp_ctrl.fastpipe, slots_11.io.iss_uop.fp_ctrl.fastpipe connect issue_slots[11].iss_uop.fp_ctrl.toint, slots_11.io.iss_uop.fp_ctrl.toint connect issue_slots[11].iss_uop.fp_ctrl.fromint, slots_11.io.iss_uop.fp_ctrl.fromint connect issue_slots[11].iss_uop.fp_ctrl.typeTagOut, slots_11.io.iss_uop.fp_ctrl.typeTagOut connect issue_slots[11].iss_uop.fp_ctrl.typeTagIn, slots_11.io.iss_uop.fp_ctrl.typeTagIn connect issue_slots[11].iss_uop.fp_ctrl.swap23, slots_11.io.iss_uop.fp_ctrl.swap23 connect issue_slots[11].iss_uop.fp_ctrl.swap12, slots_11.io.iss_uop.fp_ctrl.swap12 connect issue_slots[11].iss_uop.fp_ctrl.ren3, slots_11.io.iss_uop.fp_ctrl.ren3 connect issue_slots[11].iss_uop.fp_ctrl.ren2, slots_11.io.iss_uop.fp_ctrl.ren2 connect issue_slots[11].iss_uop.fp_ctrl.ren1, slots_11.io.iss_uop.fp_ctrl.ren1 connect issue_slots[11].iss_uop.fp_ctrl.wen, slots_11.io.iss_uop.fp_ctrl.wen connect issue_slots[11].iss_uop.fp_ctrl.ldst, slots_11.io.iss_uop.fp_ctrl.ldst connect issue_slots[11].iss_uop.op2_sel, slots_11.io.iss_uop.op2_sel connect issue_slots[11].iss_uop.op1_sel, slots_11.io.iss_uop.op1_sel connect issue_slots[11].iss_uop.imm_packed, slots_11.io.iss_uop.imm_packed connect issue_slots[11].iss_uop.pimm, slots_11.io.iss_uop.pimm connect issue_slots[11].iss_uop.imm_sel, slots_11.io.iss_uop.imm_sel connect issue_slots[11].iss_uop.imm_rename, slots_11.io.iss_uop.imm_rename connect issue_slots[11].iss_uop.taken, slots_11.io.iss_uop.taken connect issue_slots[11].iss_uop.pc_lob, slots_11.io.iss_uop.pc_lob connect issue_slots[11].iss_uop.edge_inst, slots_11.io.iss_uop.edge_inst connect issue_slots[11].iss_uop.ftq_idx, slots_11.io.iss_uop.ftq_idx connect issue_slots[11].iss_uop.is_mov, slots_11.io.iss_uop.is_mov connect issue_slots[11].iss_uop.is_rocc, slots_11.io.iss_uop.is_rocc connect issue_slots[11].iss_uop.is_sys_pc2epc, slots_11.io.iss_uop.is_sys_pc2epc connect issue_slots[11].iss_uop.is_eret, slots_11.io.iss_uop.is_eret connect issue_slots[11].iss_uop.is_amo, slots_11.io.iss_uop.is_amo connect issue_slots[11].iss_uop.is_sfence, slots_11.io.iss_uop.is_sfence connect issue_slots[11].iss_uop.is_fencei, slots_11.io.iss_uop.is_fencei connect issue_slots[11].iss_uop.is_fence, slots_11.io.iss_uop.is_fence connect issue_slots[11].iss_uop.is_sfb, slots_11.io.iss_uop.is_sfb connect issue_slots[11].iss_uop.br_type, slots_11.io.iss_uop.br_type connect issue_slots[11].iss_uop.br_tag, slots_11.io.iss_uop.br_tag connect issue_slots[11].iss_uop.br_mask, slots_11.io.iss_uop.br_mask connect issue_slots[11].iss_uop.dis_col_sel, slots_11.io.iss_uop.dis_col_sel connect issue_slots[11].iss_uop.iw_p3_bypass_hint, slots_11.io.iss_uop.iw_p3_bypass_hint connect issue_slots[11].iss_uop.iw_p2_bypass_hint, slots_11.io.iss_uop.iw_p2_bypass_hint connect issue_slots[11].iss_uop.iw_p1_bypass_hint, slots_11.io.iss_uop.iw_p1_bypass_hint connect issue_slots[11].iss_uop.iw_p2_speculative_child, slots_11.io.iss_uop.iw_p2_speculative_child connect issue_slots[11].iss_uop.iw_p1_speculative_child, slots_11.io.iss_uop.iw_p1_speculative_child connect issue_slots[11].iss_uop.iw_issued_partial_dgen, slots_11.io.iss_uop.iw_issued_partial_dgen connect issue_slots[11].iss_uop.iw_issued_partial_agen, slots_11.io.iss_uop.iw_issued_partial_agen connect issue_slots[11].iss_uop.iw_issued, slots_11.io.iss_uop.iw_issued connect issue_slots[11].iss_uop.fu_code[0], slots_11.io.iss_uop.fu_code[0] connect issue_slots[11].iss_uop.fu_code[1], slots_11.io.iss_uop.fu_code[1] connect issue_slots[11].iss_uop.fu_code[2], slots_11.io.iss_uop.fu_code[2] connect issue_slots[11].iss_uop.fu_code[3], slots_11.io.iss_uop.fu_code[3] connect issue_slots[11].iss_uop.fu_code[4], slots_11.io.iss_uop.fu_code[4] connect issue_slots[11].iss_uop.fu_code[5], slots_11.io.iss_uop.fu_code[5] connect issue_slots[11].iss_uop.fu_code[6], slots_11.io.iss_uop.fu_code[6] connect issue_slots[11].iss_uop.fu_code[7], slots_11.io.iss_uop.fu_code[7] connect issue_slots[11].iss_uop.fu_code[8], slots_11.io.iss_uop.fu_code[8] connect issue_slots[11].iss_uop.fu_code[9], slots_11.io.iss_uop.fu_code[9] connect issue_slots[11].iss_uop.iq_type[0], slots_11.io.iss_uop.iq_type[0] connect issue_slots[11].iss_uop.iq_type[1], slots_11.io.iss_uop.iq_type[1] connect issue_slots[11].iss_uop.iq_type[2], slots_11.io.iss_uop.iq_type[2] connect issue_slots[11].iss_uop.iq_type[3], slots_11.io.iss_uop.iq_type[3] connect issue_slots[11].iss_uop.debug_pc, slots_11.io.iss_uop.debug_pc connect issue_slots[11].iss_uop.is_rvc, slots_11.io.iss_uop.is_rvc connect issue_slots[11].iss_uop.debug_inst, slots_11.io.iss_uop.debug_inst connect issue_slots[11].iss_uop.inst, slots_11.io.iss_uop.inst connect slots_11.io.grant, issue_slots[11].grant connect issue_slots[11].request, slots_11.io.request connect issue_slots[11].will_be_valid, slots_11.io.will_be_valid connect issue_slots[11].valid, slots_11.io.valid connect slots_12.io.child_rebusys, issue_slots[12].child_rebusys connect slots_12.io.pred_wakeup_port.bits, issue_slots[12].pred_wakeup_port.bits connect slots_12.io.pred_wakeup_port.valid, issue_slots[12].pred_wakeup_port.valid connect slots_12.io.wakeup_ports[0].bits.rebusy, issue_slots[12].wakeup_ports[0].bits.rebusy connect slots_12.io.wakeup_ports[0].bits.speculative_mask, issue_slots[12].wakeup_ports[0].bits.speculative_mask connect slots_12.io.wakeup_ports[0].bits.bypassable, issue_slots[12].wakeup_ports[0].bits.bypassable connect slots_12.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[12].wakeup_ports[0].bits.uop.debug_tsrc connect slots_12.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[12].wakeup_ports[0].bits.uop.debug_fsrc connect slots_12.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[12].wakeup_ports[0].bits.uop.bp_xcpt_if connect slots_12.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[12].wakeup_ports[0].bits.uop.bp_debug_if connect slots_12.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[12].wakeup_ports[0].bits.uop.xcpt_ma_if connect slots_12.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[12].wakeup_ports[0].bits.uop.xcpt_ae_if connect slots_12.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[12].wakeup_ports[0].bits.uop.xcpt_pf_if connect slots_12.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[12].wakeup_ports[0].bits.uop.fp_typ connect slots_12.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[12].wakeup_ports[0].bits.uop.fp_rm connect slots_12.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[12].wakeup_ports[0].bits.uop.fp_val connect slots_12.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[12].wakeup_ports[0].bits.uop.fcn_op connect slots_12.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[12].wakeup_ports[0].bits.uop.fcn_dw connect slots_12.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[12].wakeup_ports[0].bits.uop.frs3_en connect slots_12.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[12].wakeup_ports[0].bits.uop.lrs2_rtype connect slots_12.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[12].wakeup_ports[0].bits.uop.lrs1_rtype connect slots_12.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[12].wakeup_ports[0].bits.uop.dst_rtype connect slots_12.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[12].wakeup_ports[0].bits.uop.lrs3 connect slots_12.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[12].wakeup_ports[0].bits.uop.lrs2 connect slots_12.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[12].wakeup_ports[0].bits.uop.lrs1 connect slots_12.io.wakeup_ports[0].bits.uop.ldst, issue_slots[12].wakeup_ports[0].bits.uop.ldst connect slots_12.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[12].wakeup_ports[0].bits.uop.ldst_is_rs1 connect slots_12.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[12].wakeup_ports[0].bits.uop.csr_cmd connect slots_12.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[12].wakeup_ports[0].bits.uop.flush_on_commit connect slots_12.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[12].wakeup_ports[0].bits.uop.is_unique connect slots_12.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[12].wakeup_ports[0].bits.uop.uses_stq connect slots_12.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[12].wakeup_ports[0].bits.uop.uses_ldq connect slots_12.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[12].wakeup_ports[0].bits.uop.mem_signed connect slots_12.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[12].wakeup_ports[0].bits.uop.mem_size connect slots_12.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[12].wakeup_ports[0].bits.uop.mem_cmd connect slots_12.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[12].wakeup_ports[0].bits.uop.exc_cause connect slots_12.io.wakeup_ports[0].bits.uop.exception, issue_slots[12].wakeup_ports[0].bits.uop.exception connect slots_12.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[12].wakeup_ports[0].bits.uop.stale_pdst connect slots_12.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[12].wakeup_ports[0].bits.uop.ppred_busy connect slots_12.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[12].wakeup_ports[0].bits.uop.prs3_busy connect slots_12.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[12].wakeup_ports[0].bits.uop.prs2_busy connect slots_12.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[12].wakeup_ports[0].bits.uop.prs1_busy connect slots_12.io.wakeup_ports[0].bits.uop.ppred, issue_slots[12].wakeup_ports[0].bits.uop.ppred connect slots_12.io.wakeup_ports[0].bits.uop.prs3, issue_slots[12].wakeup_ports[0].bits.uop.prs3 connect slots_12.io.wakeup_ports[0].bits.uop.prs2, issue_slots[12].wakeup_ports[0].bits.uop.prs2 connect slots_12.io.wakeup_ports[0].bits.uop.prs1, issue_slots[12].wakeup_ports[0].bits.uop.prs1 connect slots_12.io.wakeup_ports[0].bits.uop.pdst, issue_slots[12].wakeup_ports[0].bits.uop.pdst connect slots_12.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[12].wakeup_ports[0].bits.uop.rxq_idx connect slots_12.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[12].wakeup_ports[0].bits.uop.stq_idx connect slots_12.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[12].wakeup_ports[0].bits.uop.ldq_idx connect slots_12.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[12].wakeup_ports[0].bits.uop.rob_idx connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.vec connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.wflags connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.div connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.fma connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.toint connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.fromint connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.wen connect slots_12.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.ldst connect slots_12.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[12].wakeup_ports[0].bits.uop.op2_sel connect slots_12.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[12].wakeup_ports[0].bits.uop.op1_sel connect slots_12.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[12].wakeup_ports[0].bits.uop.imm_packed connect slots_12.io.wakeup_ports[0].bits.uop.pimm, issue_slots[12].wakeup_ports[0].bits.uop.pimm connect slots_12.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[12].wakeup_ports[0].bits.uop.imm_sel connect slots_12.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[12].wakeup_ports[0].bits.uop.imm_rename connect slots_12.io.wakeup_ports[0].bits.uop.taken, issue_slots[12].wakeup_ports[0].bits.uop.taken connect slots_12.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[12].wakeup_ports[0].bits.uop.pc_lob connect slots_12.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[12].wakeup_ports[0].bits.uop.edge_inst connect slots_12.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[12].wakeup_ports[0].bits.uop.ftq_idx connect slots_12.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[12].wakeup_ports[0].bits.uop.is_mov connect slots_12.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[12].wakeup_ports[0].bits.uop.is_rocc connect slots_12.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[12].wakeup_ports[0].bits.uop.is_sys_pc2epc connect slots_12.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[12].wakeup_ports[0].bits.uop.is_eret connect slots_12.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[12].wakeup_ports[0].bits.uop.is_amo connect slots_12.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[12].wakeup_ports[0].bits.uop.is_sfence connect slots_12.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[12].wakeup_ports[0].bits.uop.is_fencei connect slots_12.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[12].wakeup_ports[0].bits.uop.is_fence connect slots_12.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[12].wakeup_ports[0].bits.uop.is_sfb connect slots_12.io.wakeup_ports[0].bits.uop.br_type, issue_slots[12].wakeup_ports[0].bits.uop.br_type connect slots_12.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[12].wakeup_ports[0].bits.uop.br_tag connect slots_12.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[12].wakeup_ports[0].bits.uop.br_mask connect slots_12.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[12].wakeup_ports[0].bits.uop.dis_col_sel connect slots_12.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[12].wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect slots_12.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[12].wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect slots_12.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[12].wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect slots_12.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[12].wakeup_ports[0].bits.uop.iw_p2_speculative_child connect slots_12.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[12].wakeup_ports[0].bits.uop.iw_p1_speculative_child connect slots_12.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[12].wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect slots_12.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[12].wakeup_ports[0].bits.uop.iw_issued_partial_agen connect slots_12.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[12].wakeup_ports[0].bits.uop.iw_issued connect slots_12.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[12].wakeup_ports[0].bits.uop.fu_code[0] connect slots_12.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[12].wakeup_ports[0].bits.uop.fu_code[1] connect slots_12.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[12].wakeup_ports[0].bits.uop.fu_code[2] connect slots_12.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[12].wakeup_ports[0].bits.uop.fu_code[3] connect slots_12.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[12].wakeup_ports[0].bits.uop.fu_code[4] connect slots_12.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[12].wakeup_ports[0].bits.uop.fu_code[5] connect slots_12.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[12].wakeup_ports[0].bits.uop.fu_code[6] connect slots_12.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[12].wakeup_ports[0].bits.uop.fu_code[7] connect slots_12.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[12].wakeup_ports[0].bits.uop.fu_code[8] connect slots_12.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[12].wakeup_ports[0].bits.uop.fu_code[9] connect slots_12.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[12].wakeup_ports[0].bits.uop.iq_type[0] connect slots_12.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[12].wakeup_ports[0].bits.uop.iq_type[1] connect slots_12.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[12].wakeup_ports[0].bits.uop.iq_type[2] connect slots_12.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[12].wakeup_ports[0].bits.uop.iq_type[3] connect slots_12.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[12].wakeup_ports[0].bits.uop.debug_pc connect slots_12.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[12].wakeup_ports[0].bits.uop.is_rvc connect slots_12.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[12].wakeup_ports[0].bits.uop.debug_inst connect slots_12.io.wakeup_ports[0].bits.uop.inst, issue_slots[12].wakeup_ports[0].bits.uop.inst connect slots_12.io.wakeup_ports[0].valid, issue_slots[12].wakeup_ports[0].valid connect slots_12.io.wakeup_ports[1].bits.rebusy, issue_slots[12].wakeup_ports[1].bits.rebusy connect slots_12.io.wakeup_ports[1].bits.speculative_mask, issue_slots[12].wakeup_ports[1].bits.speculative_mask connect slots_12.io.wakeup_ports[1].bits.bypassable, issue_slots[12].wakeup_ports[1].bits.bypassable connect slots_12.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[12].wakeup_ports[1].bits.uop.debug_tsrc connect slots_12.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[12].wakeup_ports[1].bits.uop.debug_fsrc connect slots_12.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[12].wakeup_ports[1].bits.uop.bp_xcpt_if connect slots_12.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[12].wakeup_ports[1].bits.uop.bp_debug_if connect slots_12.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[12].wakeup_ports[1].bits.uop.xcpt_ma_if connect slots_12.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[12].wakeup_ports[1].bits.uop.xcpt_ae_if connect slots_12.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[12].wakeup_ports[1].bits.uop.xcpt_pf_if connect slots_12.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[12].wakeup_ports[1].bits.uop.fp_typ connect slots_12.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[12].wakeup_ports[1].bits.uop.fp_rm connect slots_12.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[12].wakeup_ports[1].bits.uop.fp_val connect slots_12.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[12].wakeup_ports[1].bits.uop.fcn_op connect slots_12.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[12].wakeup_ports[1].bits.uop.fcn_dw connect slots_12.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[12].wakeup_ports[1].bits.uop.frs3_en connect slots_12.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[12].wakeup_ports[1].bits.uop.lrs2_rtype connect slots_12.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[12].wakeup_ports[1].bits.uop.lrs1_rtype connect slots_12.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[12].wakeup_ports[1].bits.uop.dst_rtype connect slots_12.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[12].wakeup_ports[1].bits.uop.lrs3 connect slots_12.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[12].wakeup_ports[1].bits.uop.lrs2 connect slots_12.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[12].wakeup_ports[1].bits.uop.lrs1 connect slots_12.io.wakeup_ports[1].bits.uop.ldst, issue_slots[12].wakeup_ports[1].bits.uop.ldst connect slots_12.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[12].wakeup_ports[1].bits.uop.ldst_is_rs1 connect slots_12.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[12].wakeup_ports[1].bits.uop.csr_cmd connect slots_12.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[12].wakeup_ports[1].bits.uop.flush_on_commit connect slots_12.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[12].wakeup_ports[1].bits.uop.is_unique connect slots_12.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[12].wakeup_ports[1].bits.uop.uses_stq connect slots_12.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[12].wakeup_ports[1].bits.uop.uses_ldq connect slots_12.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[12].wakeup_ports[1].bits.uop.mem_signed connect slots_12.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[12].wakeup_ports[1].bits.uop.mem_size connect slots_12.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[12].wakeup_ports[1].bits.uop.mem_cmd connect slots_12.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[12].wakeup_ports[1].bits.uop.exc_cause connect slots_12.io.wakeup_ports[1].bits.uop.exception, issue_slots[12].wakeup_ports[1].bits.uop.exception connect slots_12.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[12].wakeup_ports[1].bits.uop.stale_pdst connect slots_12.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[12].wakeup_ports[1].bits.uop.ppred_busy connect slots_12.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[12].wakeup_ports[1].bits.uop.prs3_busy connect slots_12.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[12].wakeup_ports[1].bits.uop.prs2_busy connect slots_12.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[12].wakeup_ports[1].bits.uop.prs1_busy connect slots_12.io.wakeup_ports[1].bits.uop.ppred, issue_slots[12].wakeup_ports[1].bits.uop.ppred connect slots_12.io.wakeup_ports[1].bits.uop.prs3, issue_slots[12].wakeup_ports[1].bits.uop.prs3 connect slots_12.io.wakeup_ports[1].bits.uop.prs2, issue_slots[12].wakeup_ports[1].bits.uop.prs2 connect slots_12.io.wakeup_ports[1].bits.uop.prs1, issue_slots[12].wakeup_ports[1].bits.uop.prs1 connect slots_12.io.wakeup_ports[1].bits.uop.pdst, issue_slots[12].wakeup_ports[1].bits.uop.pdst connect slots_12.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[12].wakeup_ports[1].bits.uop.rxq_idx connect slots_12.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[12].wakeup_ports[1].bits.uop.stq_idx connect slots_12.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[12].wakeup_ports[1].bits.uop.ldq_idx connect slots_12.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[12].wakeup_ports[1].bits.uop.rob_idx connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.vec connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.wflags connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.div connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.fma connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.toint connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.fromint connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.wen connect slots_12.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.ldst connect slots_12.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[12].wakeup_ports[1].bits.uop.op2_sel connect slots_12.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[12].wakeup_ports[1].bits.uop.op1_sel connect slots_12.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[12].wakeup_ports[1].bits.uop.imm_packed connect slots_12.io.wakeup_ports[1].bits.uop.pimm, issue_slots[12].wakeup_ports[1].bits.uop.pimm connect slots_12.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[12].wakeup_ports[1].bits.uop.imm_sel connect slots_12.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[12].wakeup_ports[1].bits.uop.imm_rename connect slots_12.io.wakeup_ports[1].bits.uop.taken, issue_slots[12].wakeup_ports[1].bits.uop.taken connect slots_12.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[12].wakeup_ports[1].bits.uop.pc_lob connect slots_12.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[12].wakeup_ports[1].bits.uop.edge_inst connect slots_12.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[12].wakeup_ports[1].bits.uop.ftq_idx connect slots_12.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[12].wakeup_ports[1].bits.uop.is_mov connect slots_12.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[12].wakeup_ports[1].bits.uop.is_rocc connect slots_12.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[12].wakeup_ports[1].bits.uop.is_sys_pc2epc connect slots_12.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[12].wakeup_ports[1].bits.uop.is_eret connect slots_12.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[12].wakeup_ports[1].bits.uop.is_amo connect slots_12.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[12].wakeup_ports[1].bits.uop.is_sfence connect slots_12.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[12].wakeup_ports[1].bits.uop.is_fencei connect slots_12.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[12].wakeup_ports[1].bits.uop.is_fence connect slots_12.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[12].wakeup_ports[1].bits.uop.is_sfb connect slots_12.io.wakeup_ports[1].bits.uop.br_type, issue_slots[12].wakeup_ports[1].bits.uop.br_type connect slots_12.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[12].wakeup_ports[1].bits.uop.br_tag connect slots_12.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[12].wakeup_ports[1].bits.uop.br_mask connect slots_12.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[12].wakeup_ports[1].bits.uop.dis_col_sel connect slots_12.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[12].wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect slots_12.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[12].wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect slots_12.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[12].wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect slots_12.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[12].wakeup_ports[1].bits.uop.iw_p2_speculative_child connect slots_12.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[12].wakeup_ports[1].bits.uop.iw_p1_speculative_child connect slots_12.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[12].wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect slots_12.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[12].wakeup_ports[1].bits.uop.iw_issued_partial_agen connect slots_12.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[12].wakeup_ports[1].bits.uop.iw_issued connect slots_12.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[12].wakeup_ports[1].bits.uop.fu_code[0] connect slots_12.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[12].wakeup_ports[1].bits.uop.fu_code[1] connect slots_12.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[12].wakeup_ports[1].bits.uop.fu_code[2] connect slots_12.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[12].wakeup_ports[1].bits.uop.fu_code[3] connect slots_12.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[12].wakeup_ports[1].bits.uop.fu_code[4] connect slots_12.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[12].wakeup_ports[1].bits.uop.fu_code[5] connect slots_12.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[12].wakeup_ports[1].bits.uop.fu_code[6] connect slots_12.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[12].wakeup_ports[1].bits.uop.fu_code[7] connect slots_12.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[12].wakeup_ports[1].bits.uop.fu_code[8] connect slots_12.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[12].wakeup_ports[1].bits.uop.fu_code[9] connect slots_12.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[12].wakeup_ports[1].bits.uop.iq_type[0] connect slots_12.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[12].wakeup_ports[1].bits.uop.iq_type[1] connect slots_12.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[12].wakeup_ports[1].bits.uop.iq_type[2] connect slots_12.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[12].wakeup_ports[1].bits.uop.iq_type[3] connect slots_12.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[12].wakeup_ports[1].bits.uop.debug_pc connect slots_12.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[12].wakeup_ports[1].bits.uop.is_rvc connect slots_12.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[12].wakeup_ports[1].bits.uop.debug_inst connect slots_12.io.wakeup_ports[1].bits.uop.inst, issue_slots[12].wakeup_ports[1].bits.uop.inst connect slots_12.io.wakeup_ports[1].valid, issue_slots[12].wakeup_ports[1].valid connect slots_12.io.wakeup_ports[2].bits.rebusy, issue_slots[12].wakeup_ports[2].bits.rebusy connect slots_12.io.wakeup_ports[2].bits.speculative_mask, issue_slots[12].wakeup_ports[2].bits.speculative_mask connect slots_12.io.wakeup_ports[2].bits.bypassable, issue_slots[12].wakeup_ports[2].bits.bypassable connect slots_12.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[12].wakeup_ports[2].bits.uop.debug_tsrc connect slots_12.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[12].wakeup_ports[2].bits.uop.debug_fsrc connect slots_12.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[12].wakeup_ports[2].bits.uop.bp_xcpt_if connect slots_12.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[12].wakeup_ports[2].bits.uop.bp_debug_if connect slots_12.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[12].wakeup_ports[2].bits.uop.xcpt_ma_if connect slots_12.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[12].wakeup_ports[2].bits.uop.xcpt_ae_if connect slots_12.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[12].wakeup_ports[2].bits.uop.xcpt_pf_if connect slots_12.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[12].wakeup_ports[2].bits.uop.fp_typ connect slots_12.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[12].wakeup_ports[2].bits.uop.fp_rm connect slots_12.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[12].wakeup_ports[2].bits.uop.fp_val connect slots_12.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[12].wakeup_ports[2].bits.uop.fcn_op connect slots_12.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[12].wakeup_ports[2].bits.uop.fcn_dw connect slots_12.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[12].wakeup_ports[2].bits.uop.frs3_en connect slots_12.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[12].wakeup_ports[2].bits.uop.lrs2_rtype connect slots_12.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[12].wakeup_ports[2].bits.uop.lrs1_rtype connect slots_12.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[12].wakeup_ports[2].bits.uop.dst_rtype connect slots_12.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[12].wakeup_ports[2].bits.uop.lrs3 connect slots_12.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[12].wakeup_ports[2].bits.uop.lrs2 connect slots_12.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[12].wakeup_ports[2].bits.uop.lrs1 connect slots_12.io.wakeup_ports[2].bits.uop.ldst, issue_slots[12].wakeup_ports[2].bits.uop.ldst connect slots_12.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[12].wakeup_ports[2].bits.uop.ldst_is_rs1 connect slots_12.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[12].wakeup_ports[2].bits.uop.csr_cmd connect slots_12.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[12].wakeup_ports[2].bits.uop.flush_on_commit connect slots_12.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[12].wakeup_ports[2].bits.uop.is_unique connect slots_12.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[12].wakeup_ports[2].bits.uop.uses_stq connect slots_12.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[12].wakeup_ports[2].bits.uop.uses_ldq connect slots_12.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[12].wakeup_ports[2].bits.uop.mem_signed connect slots_12.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[12].wakeup_ports[2].bits.uop.mem_size connect slots_12.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[12].wakeup_ports[2].bits.uop.mem_cmd connect slots_12.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[12].wakeup_ports[2].bits.uop.exc_cause connect slots_12.io.wakeup_ports[2].bits.uop.exception, issue_slots[12].wakeup_ports[2].bits.uop.exception connect slots_12.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[12].wakeup_ports[2].bits.uop.stale_pdst connect slots_12.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[12].wakeup_ports[2].bits.uop.ppred_busy connect slots_12.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[12].wakeup_ports[2].bits.uop.prs3_busy connect slots_12.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[12].wakeup_ports[2].bits.uop.prs2_busy connect slots_12.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[12].wakeup_ports[2].bits.uop.prs1_busy connect slots_12.io.wakeup_ports[2].bits.uop.ppred, issue_slots[12].wakeup_ports[2].bits.uop.ppred connect slots_12.io.wakeup_ports[2].bits.uop.prs3, issue_slots[12].wakeup_ports[2].bits.uop.prs3 connect slots_12.io.wakeup_ports[2].bits.uop.prs2, issue_slots[12].wakeup_ports[2].bits.uop.prs2 connect slots_12.io.wakeup_ports[2].bits.uop.prs1, issue_slots[12].wakeup_ports[2].bits.uop.prs1 connect slots_12.io.wakeup_ports[2].bits.uop.pdst, issue_slots[12].wakeup_ports[2].bits.uop.pdst connect slots_12.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[12].wakeup_ports[2].bits.uop.rxq_idx connect slots_12.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[12].wakeup_ports[2].bits.uop.stq_idx connect slots_12.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[12].wakeup_ports[2].bits.uop.ldq_idx connect slots_12.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[12].wakeup_ports[2].bits.uop.rob_idx connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.vec connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.wflags connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.div connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.fma connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.toint connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.fromint connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.wen connect slots_12.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.ldst connect slots_12.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[12].wakeup_ports[2].bits.uop.op2_sel connect slots_12.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[12].wakeup_ports[2].bits.uop.op1_sel connect slots_12.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[12].wakeup_ports[2].bits.uop.imm_packed connect slots_12.io.wakeup_ports[2].bits.uop.pimm, issue_slots[12].wakeup_ports[2].bits.uop.pimm connect slots_12.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[12].wakeup_ports[2].bits.uop.imm_sel connect slots_12.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[12].wakeup_ports[2].bits.uop.imm_rename connect slots_12.io.wakeup_ports[2].bits.uop.taken, issue_slots[12].wakeup_ports[2].bits.uop.taken connect slots_12.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[12].wakeup_ports[2].bits.uop.pc_lob connect slots_12.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[12].wakeup_ports[2].bits.uop.edge_inst connect slots_12.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[12].wakeup_ports[2].bits.uop.ftq_idx connect slots_12.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[12].wakeup_ports[2].bits.uop.is_mov connect slots_12.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[12].wakeup_ports[2].bits.uop.is_rocc connect slots_12.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[12].wakeup_ports[2].bits.uop.is_sys_pc2epc connect slots_12.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[12].wakeup_ports[2].bits.uop.is_eret connect slots_12.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[12].wakeup_ports[2].bits.uop.is_amo connect slots_12.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[12].wakeup_ports[2].bits.uop.is_sfence connect slots_12.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[12].wakeup_ports[2].bits.uop.is_fencei connect slots_12.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[12].wakeup_ports[2].bits.uop.is_fence connect slots_12.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[12].wakeup_ports[2].bits.uop.is_sfb connect slots_12.io.wakeup_ports[2].bits.uop.br_type, issue_slots[12].wakeup_ports[2].bits.uop.br_type connect slots_12.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[12].wakeup_ports[2].bits.uop.br_tag connect slots_12.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[12].wakeup_ports[2].bits.uop.br_mask connect slots_12.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[12].wakeup_ports[2].bits.uop.dis_col_sel connect slots_12.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[12].wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect slots_12.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[12].wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect slots_12.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[12].wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect slots_12.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[12].wakeup_ports[2].bits.uop.iw_p2_speculative_child connect slots_12.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[12].wakeup_ports[2].bits.uop.iw_p1_speculative_child connect slots_12.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[12].wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect slots_12.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[12].wakeup_ports[2].bits.uop.iw_issued_partial_agen connect slots_12.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[12].wakeup_ports[2].bits.uop.iw_issued connect slots_12.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[12].wakeup_ports[2].bits.uop.fu_code[0] connect slots_12.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[12].wakeup_ports[2].bits.uop.fu_code[1] connect slots_12.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[12].wakeup_ports[2].bits.uop.fu_code[2] connect slots_12.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[12].wakeup_ports[2].bits.uop.fu_code[3] connect slots_12.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[12].wakeup_ports[2].bits.uop.fu_code[4] connect slots_12.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[12].wakeup_ports[2].bits.uop.fu_code[5] connect slots_12.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[12].wakeup_ports[2].bits.uop.fu_code[6] connect slots_12.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[12].wakeup_ports[2].bits.uop.fu_code[7] connect slots_12.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[12].wakeup_ports[2].bits.uop.fu_code[8] connect slots_12.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[12].wakeup_ports[2].bits.uop.fu_code[9] connect slots_12.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[12].wakeup_ports[2].bits.uop.iq_type[0] connect slots_12.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[12].wakeup_ports[2].bits.uop.iq_type[1] connect slots_12.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[12].wakeup_ports[2].bits.uop.iq_type[2] connect slots_12.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[12].wakeup_ports[2].bits.uop.iq_type[3] connect slots_12.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[12].wakeup_ports[2].bits.uop.debug_pc connect slots_12.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[12].wakeup_ports[2].bits.uop.is_rvc connect slots_12.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[12].wakeup_ports[2].bits.uop.debug_inst connect slots_12.io.wakeup_ports[2].bits.uop.inst, issue_slots[12].wakeup_ports[2].bits.uop.inst connect slots_12.io.wakeup_ports[2].valid, issue_slots[12].wakeup_ports[2].valid connect slots_12.io.wakeup_ports[3].bits.rebusy, issue_slots[12].wakeup_ports[3].bits.rebusy connect slots_12.io.wakeup_ports[3].bits.speculative_mask, issue_slots[12].wakeup_ports[3].bits.speculative_mask connect slots_12.io.wakeup_ports[3].bits.bypassable, issue_slots[12].wakeup_ports[3].bits.bypassable connect slots_12.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[12].wakeup_ports[3].bits.uop.debug_tsrc connect slots_12.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[12].wakeup_ports[3].bits.uop.debug_fsrc connect slots_12.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[12].wakeup_ports[3].bits.uop.bp_xcpt_if connect slots_12.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[12].wakeup_ports[3].bits.uop.bp_debug_if connect slots_12.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[12].wakeup_ports[3].bits.uop.xcpt_ma_if connect slots_12.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[12].wakeup_ports[3].bits.uop.xcpt_ae_if connect slots_12.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[12].wakeup_ports[3].bits.uop.xcpt_pf_if connect slots_12.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[12].wakeup_ports[3].bits.uop.fp_typ connect slots_12.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[12].wakeup_ports[3].bits.uop.fp_rm connect slots_12.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[12].wakeup_ports[3].bits.uop.fp_val connect slots_12.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[12].wakeup_ports[3].bits.uop.fcn_op connect slots_12.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[12].wakeup_ports[3].bits.uop.fcn_dw connect slots_12.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[12].wakeup_ports[3].bits.uop.frs3_en connect slots_12.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[12].wakeup_ports[3].bits.uop.lrs2_rtype connect slots_12.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[12].wakeup_ports[3].bits.uop.lrs1_rtype connect slots_12.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[12].wakeup_ports[3].bits.uop.dst_rtype connect slots_12.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[12].wakeup_ports[3].bits.uop.lrs3 connect slots_12.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[12].wakeup_ports[3].bits.uop.lrs2 connect slots_12.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[12].wakeup_ports[3].bits.uop.lrs1 connect slots_12.io.wakeup_ports[3].bits.uop.ldst, issue_slots[12].wakeup_ports[3].bits.uop.ldst connect slots_12.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[12].wakeup_ports[3].bits.uop.ldst_is_rs1 connect slots_12.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[12].wakeup_ports[3].bits.uop.csr_cmd connect slots_12.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[12].wakeup_ports[3].bits.uop.flush_on_commit connect slots_12.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[12].wakeup_ports[3].bits.uop.is_unique connect slots_12.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[12].wakeup_ports[3].bits.uop.uses_stq connect slots_12.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[12].wakeup_ports[3].bits.uop.uses_ldq connect slots_12.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[12].wakeup_ports[3].bits.uop.mem_signed connect slots_12.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[12].wakeup_ports[3].bits.uop.mem_size connect slots_12.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[12].wakeup_ports[3].bits.uop.mem_cmd connect slots_12.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[12].wakeup_ports[3].bits.uop.exc_cause connect slots_12.io.wakeup_ports[3].bits.uop.exception, issue_slots[12].wakeup_ports[3].bits.uop.exception connect slots_12.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[12].wakeup_ports[3].bits.uop.stale_pdst connect slots_12.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[12].wakeup_ports[3].bits.uop.ppred_busy connect slots_12.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[12].wakeup_ports[3].bits.uop.prs3_busy connect slots_12.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[12].wakeup_ports[3].bits.uop.prs2_busy connect slots_12.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[12].wakeup_ports[3].bits.uop.prs1_busy connect slots_12.io.wakeup_ports[3].bits.uop.ppred, issue_slots[12].wakeup_ports[3].bits.uop.ppred connect slots_12.io.wakeup_ports[3].bits.uop.prs3, issue_slots[12].wakeup_ports[3].bits.uop.prs3 connect slots_12.io.wakeup_ports[3].bits.uop.prs2, issue_slots[12].wakeup_ports[3].bits.uop.prs2 connect slots_12.io.wakeup_ports[3].bits.uop.prs1, issue_slots[12].wakeup_ports[3].bits.uop.prs1 connect slots_12.io.wakeup_ports[3].bits.uop.pdst, issue_slots[12].wakeup_ports[3].bits.uop.pdst connect slots_12.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[12].wakeup_ports[3].bits.uop.rxq_idx connect slots_12.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[12].wakeup_ports[3].bits.uop.stq_idx connect slots_12.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[12].wakeup_ports[3].bits.uop.ldq_idx connect slots_12.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[12].wakeup_ports[3].bits.uop.rob_idx connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.vec connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.wflags connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.div connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.fma connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.toint connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.fromint connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.wen connect slots_12.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.ldst connect slots_12.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[12].wakeup_ports[3].bits.uop.op2_sel connect slots_12.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[12].wakeup_ports[3].bits.uop.op1_sel connect slots_12.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[12].wakeup_ports[3].bits.uop.imm_packed connect slots_12.io.wakeup_ports[3].bits.uop.pimm, issue_slots[12].wakeup_ports[3].bits.uop.pimm connect slots_12.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[12].wakeup_ports[3].bits.uop.imm_sel connect slots_12.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[12].wakeup_ports[3].bits.uop.imm_rename connect slots_12.io.wakeup_ports[3].bits.uop.taken, issue_slots[12].wakeup_ports[3].bits.uop.taken connect slots_12.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[12].wakeup_ports[3].bits.uop.pc_lob connect slots_12.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[12].wakeup_ports[3].bits.uop.edge_inst connect slots_12.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[12].wakeup_ports[3].bits.uop.ftq_idx connect slots_12.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[12].wakeup_ports[3].bits.uop.is_mov connect slots_12.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[12].wakeup_ports[3].bits.uop.is_rocc connect slots_12.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[12].wakeup_ports[3].bits.uop.is_sys_pc2epc connect slots_12.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[12].wakeup_ports[3].bits.uop.is_eret connect slots_12.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[12].wakeup_ports[3].bits.uop.is_amo connect slots_12.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[12].wakeup_ports[3].bits.uop.is_sfence connect slots_12.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[12].wakeup_ports[3].bits.uop.is_fencei connect slots_12.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[12].wakeup_ports[3].bits.uop.is_fence connect slots_12.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[12].wakeup_ports[3].bits.uop.is_sfb connect slots_12.io.wakeup_ports[3].bits.uop.br_type, issue_slots[12].wakeup_ports[3].bits.uop.br_type connect slots_12.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[12].wakeup_ports[3].bits.uop.br_tag connect slots_12.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[12].wakeup_ports[3].bits.uop.br_mask connect slots_12.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[12].wakeup_ports[3].bits.uop.dis_col_sel connect slots_12.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[12].wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect slots_12.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[12].wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect slots_12.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[12].wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect slots_12.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[12].wakeup_ports[3].bits.uop.iw_p2_speculative_child connect slots_12.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[12].wakeup_ports[3].bits.uop.iw_p1_speculative_child connect slots_12.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[12].wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect slots_12.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[12].wakeup_ports[3].bits.uop.iw_issued_partial_agen connect slots_12.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[12].wakeup_ports[3].bits.uop.iw_issued connect slots_12.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[12].wakeup_ports[3].bits.uop.fu_code[0] connect slots_12.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[12].wakeup_ports[3].bits.uop.fu_code[1] connect slots_12.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[12].wakeup_ports[3].bits.uop.fu_code[2] connect slots_12.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[12].wakeup_ports[3].bits.uop.fu_code[3] connect slots_12.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[12].wakeup_ports[3].bits.uop.fu_code[4] connect slots_12.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[12].wakeup_ports[3].bits.uop.fu_code[5] connect slots_12.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[12].wakeup_ports[3].bits.uop.fu_code[6] connect slots_12.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[12].wakeup_ports[3].bits.uop.fu_code[7] connect slots_12.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[12].wakeup_ports[3].bits.uop.fu_code[8] connect slots_12.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[12].wakeup_ports[3].bits.uop.fu_code[9] connect slots_12.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[12].wakeup_ports[3].bits.uop.iq_type[0] connect slots_12.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[12].wakeup_ports[3].bits.uop.iq_type[1] connect slots_12.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[12].wakeup_ports[3].bits.uop.iq_type[2] connect slots_12.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[12].wakeup_ports[3].bits.uop.iq_type[3] connect slots_12.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[12].wakeup_ports[3].bits.uop.debug_pc connect slots_12.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[12].wakeup_ports[3].bits.uop.is_rvc connect slots_12.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[12].wakeup_ports[3].bits.uop.debug_inst connect slots_12.io.wakeup_ports[3].bits.uop.inst, issue_slots[12].wakeup_ports[3].bits.uop.inst connect slots_12.io.wakeup_ports[3].valid, issue_slots[12].wakeup_ports[3].valid connect slots_12.io.wakeup_ports[4].bits.rebusy, issue_slots[12].wakeup_ports[4].bits.rebusy connect slots_12.io.wakeup_ports[4].bits.speculative_mask, issue_slots[12].wakeup_ports[4].bits.speculative_mask connect slots_12.io.wakeup_ports[4].bits.bypassable, issue_slots[12].wakeup_ports[4].bits.bypassable connect slots_12.io.wakeup_ports[4].bits.uop.debug_tsrc, issue_slots[12].wakeup_ports[4].bits.uop.debug_tsrc connect slots_12.io.wakeup_ports[4].bits.uop.debug_fsrc, issue_slots[12].wakeup_ports[4].bits.uop.debug_fsrc connect slots_12.io.wakeup_ports[4].bits.uop.bp_xcpt_if, issue_slots[12].wakeup_ports[4].bits.uop.bp_xcpt_if connect slots_12.io.wakeup_ports[4].bits.uop.bp_debug_if, issue_slots[12].wakeup_ports[4].bits.uop.bp_debug_if connect slots_12.io.wakeup_ports[4].bits.uop.xcpt_ma_if, issue_slots[12].wakeup_ports[4].bits.uop.xcpt_ma_if connect slots_12.io.wakeup_ports[4].bits.uop.xcpt_ae_if, issue_slots[12].wakeup_ports[4].bits.uop.xcpt_ae_if connect slots_12.io.wakeup_ports[4].bits.uop.xcpt_pf_if, issue_slots[12].wakeup_ports[4].bits.uop.xcpt_pf_if connect slots_12.io.wakeup_ports[4].bits.uop.fp_typ, issue_slots[12].wakeup_ports[4].bits.uop.fp_typ connect slots_12.io.wakeup_ports[4].bits.uop.fp_rm, issue_slots[12].wakeup_ports[4].bits.uop.fp_rm connect slots_12.io.wakeup_ports[4].bits.uop.fp_val, issue_slots[12].wakeup_ports[4].bits.uop.fp_val connect slots_12.io.wakeup_ports[4].bits.uop.fcn_op, issue_slots[12].wakeup_ports[4].bits.uop.fcn_op connect slots_12.io.wakeup_ports[4].bits.uop.fcn_dw, issue_slots[12].wakeup_ports[4].bits.uop.fcn_dw connect slots_12.io.wakeup_ports[4].bits.uop.frs3_en, issue_slots[12].wakeup_ports[4].bits.uop.frs3_en connect slots_12.io.wakeup_ports[4].bits.uop.lrs2_rtype, issue_slots[12].wakeup_ports[4].bits.uop.lrs2_rtype connect slots_12.io.wakeup_ports[4].bits.uop.lrs1_rtype, issue_slots[12].wakeup_ports[4].bits.uop.lrs1_rtype connect slots_12.io.wakeup_ports[4].bits.uop.dst_rtype, issue_slots[12].wakeup_ports[4].bits.uop.dst_rtype connect slots_12.io.wakeup_ports[4].bits.uop.lrs3, issue_slots[12].wakeup_ports[4].bits.uop.lrs3 connect slots_12.io.wakeup_ports[4].bits.uop.lrs2, issue_slots[12].wakeup_ports[4].bits.uop.lrs2 connect slots_12.io.wakeup_ports[4].bits.uop.lrs1, issue_slots[12].wakeup_ports[4].bits.uop.lrs1 connect slots_12.io.wakeup_ports[4].bits.uop.ldst, issue_slots[12].wakeup_ports[4].bits.uop.ldst connect slots_12.io.wakeup_ports[4].bits.uop.ldst_is_rs1, issue_slots[12].wakeup_ports[4].bits.uop.ldst_is_rs1 connect slots_12.io.wakeup_ports[4].bits.uop.csr_cmd, issue_slots[12].wakeup_ports[4].bits.uop.csr_cmd connect slots_12.io.wakeup_ports[4].bits.uop.flush_on_commit, issue_slots[12].wakeup_ports[4].bits.uop.flush_on_commit connect slots_12.io.wakeup_ports[4].bits.uop.is_unique, issue_slots[12].wakeup_ports[4].bits.uop.is_unique connect slots_12.io.wakeup_ports[4].bits.uop.uses_stq, issue_slots[12].wakeup_ports[4].bits.uop.uses_stq connect slots_12.io.wakeup_ports[4].bits.uop.uses_ldq, issue_slots[12].wakeup_ports[4].bits.uop.uses_ldq connect slots_12.io.wakeup_ports[4].bits.uop.mem_signed, issue_slots[12].wakeup_ports[4].bits.uop.mem_signed connect slots_12.io.wakeup_ports[4].bits.uop.mem_size, issue_slots[12].wakeup_ports[4].bits.uop.mem_size connect slots_12.io.wakeup_ports[4].bits.uop.mem_cmd, issue_slots[12].wakeup_ports[4].bits.uop.mem_cmd connect slots_12.io.wakeup_ports[4].bits.uop.exc_cause, issue_slots[12].wakeup_ports[4].bits.uop.exc_cause connect slots_12.io.wakeup_ports[4].bits.uop.exception, issue_slots[12].wakeup_ports[4].bits.uop.exception connect slots_12.io.wakeup_ports[4].bits.uop.stale_pdst, issue_slots[12].wakeup_ports[4].bits.uop.stale_pdst connect slots_12.io.wakeup_ports[4].bits.uop.ppred_busy, issue_slots[12].wakeup_ports[4].bits.uop.ppred_busy connect slots_12.io.wakeup_ports[4].bits.uop.prs3_busy, issue_slots[12].wakeup_ports[4].bits.uop.prs3_busy connect slots_12.io.wakeup_ports[4].bits.uop.prs2_busy, issue_slots[12].wakeup_ports[4].bits.uop.prs2_busy connect slots_12.io.wakeup_ports[4].bits.uop.prs1_busy, issue_slots[12].wakeup_ports[4].bits.uop.prs1_busy connect slots_12.io.wakeup_ports[4].bits.uop.ppred, issue_slots[12].wakeup_ports[4].bits.uop.ppred connect slots_12.io.wakeup_ports[4].bits.uop.prs3, issue_slots[12].wakeup_ports[4].bits.uop.prs3 connect slots_12.io.wakeup_ports[4].bits.uop.prs2, issue_slots[12].wakeup_ports[4].bits.uop.prs2 connect slots_12.io.wakeup_ports[4].bits.uop.prs1, issue_slots[12].wakeup_ports[4].bits.uop.prs1 connect slots_12.io.wakeup_ports[4].bits.uop.pdst, issue_slots[12].wakeup_ports[4].bits.uop.pdst connect slots_12.io.wakeup_ports[4].bits.uop.rxq_idx, issue_slots[12].wakeup_ports[4].bits.uop.rxq_idx connect slots_12.io.wakeup_ports[4].bits.uop.stq_idx, issue_slots[12].wakeup_ports[4].bits.uop.stq_idx connect slots_12.io.wakeup_ports[4].bits.uop.ldq_idx, issue_slots[12].wakeup_ports[4].bits.uop.ldq_idx connect slots_12.io.wakeup_ports[4].bits.uop.rob_idx, issue_slots[12].wakeup_ports[4].bits.uop.rob_idx connect slots_12.io.wakeup_ports[4].bits.uop.fp_ctrl.vec, issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.vec connect slots_12.io.wakeup_ports[4].bits.uop.fp_ctrl.wflags, issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.wflags connect slots_12.io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt, issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect slots_12.io.wakeup_ports[4].bits.uop.fp_ctrl.div, issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.div connect slots_12.io.wakeup_ports[4].bits.uop.fp_ctrl.fma, issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.fma connect slots_12.io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect slots_12.io.wakeup_ports[4].bits.uop.fp_ctrl.toint, issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.toint connect slots_12.io.wakeup_ports[4].bits.uop.fp_ctrl.fromint, issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.fromint connect slots_12.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect slots_12.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect slots_12.io.wakeup_ports[4].bits.uop.fp_ctrl.swap23, issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect slots_12.io.wakeup_ports[4].bits.uop.fp_ctrl.swap12, issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect slots_12.io.wakeup_ports[4].bits.uop.fp_ctrl.ren3, issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect slots_12.io.wakeup_ports[4].bits.uop.fp_ctrl.ren2, issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect slots_12.io.wakeup_ports[4].bits.uop.fp_ctrl.ren1, issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect slots_12.io.wakeup_ports[4].bits.uop.fp_ctrl.wen, issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.wen connect slots_12.io.wakeup_ports[4].bits.uop.fp_ctrl.ldst, issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.ldst connect slots_12.io.wakeup_ports[4].bits.uop.op2_sel, issue_slots[12].wakeup_ports[4].bits.uop.op2_sel connect slots_12.io.wakeup_ports[4].bits.uop.op1_sel, issue_slots[12].wakeup_ports[4].bits.uop.op1_sel connect slots_12.io.wakeup_ports[4].bits.uop.imm_packed, issue_slots[12].wakeup_ports[4].bits.uop.imm_packed connect slots_12.io.wakeup_ports[4].bits.uop.pimm, issue_slots[12].wakeup_ports[4].bits.uop.pimm connect slots_12.io.wakeup_ports[4].bits.uop.imm_sel, issue_slots[12].wakeup_ports[4].bits.uop.imm_sel connect slots_12.io.wakeup_ports[4].bits.uop.imm_rename, issue_slots[12].wakeup_ports[4].bits.uop.imm_rename connect slots_12.io.wakeup_ports[4].bits.uop.taken, issue_slots[12].wakeup_ports[4].bits.uop.taken connect slots_12.io.wakeup_ports[4].bits.uop.pc_lob, issue_slots[12].wakeup_ports[4].bits.uop.pc_lob connect slots_12.io.wakeup_ports[4].bits.uop.edge_inst, issue_slots[12].wakeup_ports[4].bits.uop.edge_inst connect slots_12.io.wakeup_ports[4].bits.uop.ftq_idx, issue_slots[12].wakeup_ports[4].bits.uop.ftq_idx connect slots_12.io.wakeup_ports[4].bits.uop.is_mov, issue_slots[12].wakeup_ports[4].bits.uop.is_mov connect slots_12.io.wakeup_ports[4].bits.uop.is_rocc, issue_slots[12].wakeup_ports[4].bits.uop.is_rocc connect slots_12.io.wakeup_ports[4].bits.uop.is_sys_pc2epc, issue_slots[12].wakeup_ports[4].bits.uop.is_sys_pc2epc connect slots_12.io.wakeup_ports[4].bits.uop.is_eret, issue_slots[12].wakeup_ports[4].bits.uop.is_eret connect slots_12.io.wakeup_ports[4].bits.uop.is_amo, issue_slots[12].wakeup_ports[4].bits.uop.is_amo connect slots_12.io.wakeup_ports[4].bits.uop.is_sfence, issue_slots[12].wakeup_ports[4].bits.uop.is_sfence connect slots_12.io.wakeup_ports[4].bits.uop.is_fencei, issue_slots[12].wakeup_ports[4].bits.uop.is_fencei connect slots_12.io.wakeup_ports[4].bits.uop.is_fence, issue_slots[12].wakeup_ports[4].bits.uop.is_fence connect slots_12.io.wakeup_ports[4].bits.uop.is_sfb, issue_slots[12].wakeup_ports[4].bits.uop.is_sfb connect slots_12.io.wakeup_ports[4].bits.uop.br_type, issue_slots[12].wakeup_ports[4].bits.uop.br_type connect slots_12.io.wakeup_ports[4].bits.uop.br_tag, issue_slots[12].wakeup_ports[4].bits.uop.br_tag connect slots_12.io.wakeup_ports[4].bits.uop.br_mask, issue_slots[12].wakeup_ports[4].bits.uop.br_mask connect slots_12.io.wakeup_ports[4].bits.uop.dis_col_sel, issue_slots[12].wakeup_ports[4].bits.uop.dis_col_sel connect slots_12.io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint, issue_slots[12].wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect slots_12.io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint, issue_slots[12].wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect slots_12.io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint, issue_slots[12].wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect slots_12.io.wakeup_ports[4].bits.uop.iw_p2_speculative_child, issue_slots[12].wakeup_ports[4].bits.uop.iw_p2_speculative_child connect slots_12.io.wakeup_ports[4].bits.uop.iw_p1_speculative_child, issue_slots[12].wakeup_ports[4].bits.uop.iw_p1_speculative_child connect slots_12.io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen, issue_slots[12].wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect slots_12.io.wakeup_ports[4].bits.uop.iw_issued_partial_agen, issue_slots[12].wakeup_ports[4].bits.uop.iw_issued_partial_agen connect slots_12.io.wakeup_ports[4].bits.uop.iw_issued, issue_slots[12].wakeup_ports[4].bits.uop.iw_issued connect slots_12.io.wakeup_ports[4].bits.uop.fu_code[0], issue_slots[12].wakeup_ports[4].bits.uop.fu_code[0] connect slots_12.io.wakeup_ports[4].bits.uop.fu_code[1], issue_slots[12].wakeup_ports[4].bits.uop.fu_code[1] connect slots_12.io.wakeup_ports[4].bits.uop.fu_code[2], issue_slots[12].wakeup_ports[4].bits.uop.fu_code[2] connect slots_12.io.wakeup_ports[4].bits.uop.fu_code[3], issue_slots[12].wakeup_ports[4].bits.uop.fu_code[3] connect slots_12.io.wakeup_ports[4].bits.uop.fu_code[4], issue_slots[12].wakeup_ports[4].bits.uop.fu_code[4] connect slots_12.io.wakeup_ports[4].bits.uop.fu_code[5], issue_slots[12].wakeup_ports[4].bits.uop.fu_code[5] connect slots_12.io.wakeup_ports[4].bits.uop.fu_code[6], issue_slots[12].wakeup_ports[4].bits.uop.fu_code[6] connect slots_12.io.wakeup_ports[4].bits.uop.fu_code[7], issue_slots[12].wakeup_ports[4].bits.uop.fu_code[7] connect slots_12.io.wakeup_ports[4].bits.uop.fu_code[8], issue_slots[12].wakeup_ports[4].bits.uop.fu_code[8] connect slots_12.io.wakeup_ports[4].bits.uop.fu_code[9], issue_slots[12].wakeup_ports[4].bits.uop.fu_code[9] connect slots_12.io.wakeup_ports[4].bits.uop.iq_type[0], issue_slots[12].wakeup_ports[4].bits.uop.iq_type[0] connect slots_12.io.wakeup_ports[4].bits.uop.iq_type[1], issue_slots[12].wakeup_ports[4].bits.uop.iq_type[1] connect slots_12.io.wakeup_ports[4].bits.uop.iq_type[2], issue_slots[12].wakeup_ports[4].bits.uop.iq_type[2] connect slots_12.io.wakeup_ports[4].bits.uop.iq_type[3], issue_slots[12].wakeup_ports[4].bits.uop.iq_type[3] connect slots_12.io.wakeup_ports[4].bits.uop.debug_pc, issue_slots[12].wakeup_ports[4].bits.uop.debug_pc connect slots_12.io.wakeup_ports[4].bits.uop.is_rvc, issue_slots[12].wakeup_ports[4].bits.uop.is_rvc connect slots_12.io.wakeup_ports[4].bits.uop.debug_inst, issue_slots[12].wakeup_ports[4].bits.uop.debug_inst connect slots_12.io.wakeup_ports[4].bits.uop.inst, issue_slots[12].wakeup_ports[4].bits.uop.inst connect slots_12.io.wakeup_ports[4].valid, issue_slots[12].wakeup_ports[4].valid connect slots_12.io.squash_grant, issue_slots[12].squash_grant connect slots_12.io.clear, issue_slots[12].clear connect slots_12.io.kill, issue_slots[12].kill connect slots_12.io.brupdate.b2.target_offset, issue_slots[12].brupdate.b2.target_offset connect slots_12.io.brupdate.b2.jalr_target, issue_slots[12].brupdate.b2.jalr_target connect slots_12.io.brupdate.b2.pc_sel, issue_slots[12].brupdate.b2.pc_sel connect slots_12.io.brupdate.b2.cfi_type, issue_slots[12].brupdate.b2.cfi_type connect slots_12.io.brupdate.b2.taken, issue_slots[12].brupdate.b2.taken connect slots_12.io.brupdate.b2.mispredict, issue_slots[12].brupdate.b2.mispredict connect slots_12.io.brupdate.b2.uop.debug_tsrc, issue_slots[12].brupdate.b2.uop.debug_tsrc connect slots_12.io.brupdate.b2.uop.debug_fsrc, issue_slots[12].brupdate.b2.uop.debug_fsrc connect slots_12.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[12].brupdate.b2.uop.bp_xcpt_if connect slots_12.io.brupdate.b2.uop.bp_debug_if, issue_slots[12].brupdate.b2.uop.bp_debug_if connect slots_12.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[12].brupdate.b2.uop.xcpt_ma_if connect slots_12.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[12].brupdate.b2.uop.xcpt_ae_if connect slots_12.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[12].brupdate.b2.uop.xcpt_pf_if connect slots_12.io.brupdate.b2.uop.fp_typ, issue_slots[12].brupdate.b2.uop.fp_typ connect slots_12.io.brupdate.b2.uop.fp_rm, issue_slots[12].brupdate.b2.uop.fp_rm connect slots_12.io.brupdate.b2.uop.fp_val, issue_slots[12].brupdate.b2.uop.fp_val connect slots_12.io.brupdate.b2.uop.fcn_op, issue_slots[12].brupdate.b2.uop.fcn_op connect slots_12.io.brupdate.b2.uop.fcn_dw, issue_slots[12].brupdate.b2.uop.fcn_dw connect slots_12.io.brupdate.b2.uop.frs3_en, issue_slots[12].brupdate.b2.uop.frs3_en connect slots_12.io.brupdate.b2.uop.lrs2_rtype, issue_slots[12].brupdate.b2.uop.lrs2_rtype connect slots_12.io.brupdate.b2.uop.lrs1_rtype, issue_slots[12].brupdate.b2.uop.lrs1_rtype connect slots_12.io.brupdate.b2.uop.dst_rtype, issue_slots[12].brupdate.b2.uop.dst_rtype connect slots_12.io.brupdate.b2.uop.lrs3, issue_slots[12].brupdate.b2.uop.lrs3 connect slots_12.io.brupdate.b2.uop.lrs2, issue_slots[12].brupdate.b2.uop.lrs2 connect slots_12.io.brupdate.b2.uop.lrs1, issue_slots[12].brupdate.b2.uop.lrs1 connect slots_12.io.brupdate.b2.uop.ldst, issue_slots[12].brupdate.b2.uop.ldst connect slots_12.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[12].brupdate.b2.uop.ldst_is_rs1 connect slots_12.io.brupdate.b2.uop.csr_cmd, issue_slots[12].brupdate.b2.uop.csr_cmd connect slots_12.io.brupdate.b2.uop.flush_on_commit, issue_slots[12].brupdate.b2.uop.flush_on_commit connect slots_12.io.brupdate.b2.uop.is_unique, issue_slots[12].brupdate.b2.uop.is_unique connect slots_12.io.brupdate.b2.uop.uses_stq, issue_slots[12].brupdate.b2.uop.uses_stq connect slots_12.io.brupdate.b2.uop.uses_ldq, issue_slots[12].brupdate.b2.uop.uses_ldq connect slots_12.io.brupdate.b2.uop.mem_signed, issue_slots[12].brupdate.b2.uop.mem_signed connect slots_12.io.brupdate.b2.uop.mem_size, issue_slots[12].brupdate.b2.uop.mem_size connect slots_12.io.brupdate.b2.uop.mem_cmd, issue_slots[12].brupdate.b2.uop.mem_cmd connect slots_12.io.brupdate.b2.uop.exc_cause, issue_slots[12].brupdate.b2.uop.exc_cause connect slots_12.io.brupdate.b2.uop.exception, issue_slots[12].brupdate.b2.uop.exception connect slots_12.io.brupdate.b2.uop.stale_pdst, issue_slots[12].brupdate.b2.uop.stale_pdst connect slots_12.io.brupdate.b2.uop.ppred_busy, issue_slots[12].brupdate.b2.uop.ppred_busy connect slots_12.io.brupdate.b2.uop.prs3_busy, issue_slots[12].brupdate.b2.uop.prs3_busy connect slots_12.io.brupdate.b2.uop.prs2_busy, issue_slots[12].brupdate.b2.uop.prs2_busy connect slots_12.io.brupdate.b2.uop.prs1_busy, issue_slots[12].brupdate.b2.uop.prs1_busy connect slots_12.io.brupdate.b2.uop.ppred, issue_slots[12].brupdate.b2.uop.ppred connect slots_12.io.brupdate.b2.uop.prs3, issue_slots[12].brupdate.b2.uop.prs3 connect slots_12.io.brupdate.b2.uop.prs2, issue_slots[12].brupdate.b2.uop.prs2 connect slots_12.io.brupdate.b2.uop.prs1, issue_slots[12].brupdate.b2.uop.prs1 connect slots_12.io.brupdate.b2.uop.pdst, issue_slots[12].brupdate.b2.uop.pdst connect slots_12.io.brupdate.b2.uop.rxq_idx, issue_slots[12].brupdate.b2.uop.rxq_idx connect slots_12.io.brupdate.b2.uop.stq_idx, issue_slots[12].brupdate.b2.uop.stq_idx connect slots_12.io.brupdate.b2.uop.ldq_idx, issue_slots[12].brupdate.b2.uop.ldq_idx connect slots_12.io.brupdate.b2.uop.rob_idx, issue_slots[12].brupdate.b2.uop.rob_idx connect slots_12.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[12].brupdate.b2.uop.fp_ctrl.vec connect slots_12.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[12].brupdate.b2.uop.fp_ctrl.wflags connect slots_12.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[12].brupdate.b2.uop.fp_ctrl.sqrt connect slots_12.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[12].brupdate.b2.uop.fp_ctrl.div connect slots_12.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[12].brupdate.b2.uop.fp_ctrl.fma connect slots_12.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[12].brupdate.b2.uop.fp_ctrl.fastpipe connect slots_12.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[12].brupdate.b2.uop.fp_ctrl.toint connect slots_12.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[12].brupdate.b2.uop.fp_ctrl.fromint connect slots_12.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[12].brupdate.b2.uop.fp_ctrl.typeTagOut connect slots_12.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[12].brupdate.b2.uop.fp_ctrl.typeTagIn connect slots_12.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[12].brupdate.b2.uop.fp_ctrl.swap23 connect slots_12.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[12].brupdate.b2.uop.fp_ctrl.swap12 connect slots_12.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[12].brupdate.b2.uop.fp_ctrl.ren3 connect slots_12.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[12].brupdate.b2.uop.fp_ctrl.ren2 connect slots_12.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[12].brupdate.b2.uop.fp_ctrl.ren1 connect slots_12.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[12].brupdate.b2.uop.fp_ctrl.wen connect slots_12.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[12].brupdate.b2.uop.fp_ctrl.ldst connect slots_12.io.brupdate.b2.uop.op2_sel, issue_slots[12].brupdate.b2.uop.op2_sel connect slots_12.io.brupdate.b2.uop.op1_sel, issue_slots[12].brupdate.b2.uop.op1_sel connect slots_12.io.brupdate.b2.uop.imm_packed, issue_slots[12].brupdate.b2.uop.imm_packed connect slots_12.io.brupdate.b2.uop.pimm, issue_slots[12].brupdate.b2.uop.pimm connect slots_12.io.brupdate.b2.uop.imm_sel, issue_slots[12].brupdate.b2.uop.imm_sel connect slots_12.io.brupdate.b2.uop.imm_rename, issue_slots[12].brupdate.b2.uop.imm_rename connect slots_12.io.brupdate.b2.uop.taken, issue_slots[12].brupdate.b2.uop.taken connect slots_12.io.brupdate.b2.uop.pc_lob, issue_slots[12].brupdate.b2.uop.pc_lob connect slots_12.io.brupdate.b2.uop.edge_inst, issue_slots[12].brupdate.b2.uop.edge_inst connect slots_12.io.brupdate.b2.uop.ftq_idx, issue_slots[12].brupdate.b2.uop.ftq_idx connect slots_12.io.brupdate.b2.uop.is_mov, issue_slots[12].brupdate.b2.uop.is_mov connect slots_12.io.brupdate.b2.uop.is_rocc, issue_slots[12].brupdate.b2.uop.is_rocc connect slots_12.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[12].brupdate.b2.uop.is_sys_pc2epc connect slots_12.io.brupdate.b2.uop.is_eret, issue_slots[12].brupdate.b2.uop.is_eret connect slots_12.io.brupdate.b2.uop.is_amo, issue_slots[12].brupdate.b2.uop.is_amo connect slots_12.io.brupdate.b2.uop.is_sfence, issue_slots[12].brupdate.b2.uop.is_sfence connect slots_12.io.brupdate.b2.uop.is_fencei, issue_slots[12].brupdate.b2.uop.is_fencei connect slots_12.io.brupdate.b2.uop.is_fence, issue_slots[12].brupdate.b2.uop.is_fence connect slots_12.io.brupdate.b2.uop.is_sfb, issue_slots[12].brupdate.b2.uop.is_sfb connect slots_12.io.brupdate.b2.uop.br_type, issue_slots[12].brupdate.b2.uop.br_type connect slots_12.io.brupdate.b2.uop.br_tag, issue_slots[12].brupdate.b2.uop.br_tag connect slots_12.io.brupdate.b2.uop.br_mask, issue_slots[12].brupdate.b2.uop.br_mask connect slots_12.io.brupdate.b2.uop.dis_col_sel, issue_slots[12].brupdate.b2.uop.dis_col_sel connect slots_12.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[12].brupdate.b2.uop.iw_p3_bypass_hint connect slots_12.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[12].brupdate.b2.uop.iw_p2_bypass_hint connect slots_12.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[12].brupdate.b2.uop.iw_p1_bypass_hint connect slots_12.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[12].brupdate.b2.uop.iw_p2_speculative_child connect slots_12.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[12].brupdate.b2.uop.iw_p1_speculative_child connect slots_12.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[12].brupdate.b2.uop.iw_issued_partial_dgen connect slots_12.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[12].brupdate.b2.uop.iw_issued_partial_agen connect slots_12.io.brupdate.b2.uop.iw_issued, issue_slots[12].brupdate.b2.uop.iw_issued connect slots_12.io.brupdate.b2.uop.fu_code[0], issue_slots[12].brupdate.b2.uop.fu_code[0] connect slots_12.io.brupdate.b2.uop.fu_code[1], issue_slots[12].brupdate.b2.uop.fu_code[1] connect slots_12.io.brupdate.b2.uop.fu_code[2], issue_slots[12].brupdate.b2.uop.fu_code[2] connect slots_12.io.brupdate.b2.uop.fu_code[3], issue_slots[12].brupdate.b2.uop.fu_code[3] connect slots_12.io.brupdate.b2.uop.fu_code[4], issue_slots[12].brupdate.b2.uop.fu_code[4] connect slots_12.io.brupdate.b2.uop.fu_code[5], issue_slots[12].brupdate.b2.uop.fu_code[5] connect slots_12.io.brupdate.b2.uop.fu_code[6], issue_slots[12].brupdate.b2.uop.fu_code[6] connect slots_12.io.brupdate.b2.uop.fu_code[7], issue_slots[12].brupdate.b2.uop.fu_code[7] connect slots_12.io.brupdate.b2.uop.fu_code[8], issue_slots[12].brupdate.b2.uop.fu_code[8] connect slots_12.io.brupdate.b2.uop.fu_code[9], issue_slots[12].brupdate.b2.uop.fu_code[9] connect slots_12.io.brupdate.b2.uop.iq_type[0], issue_slots[12].brupdate.b2.uop.iq_type[0] connect slots_12.io.brupdate.b2.uop.iq_type[1], issue_slots[12].brupdate.b2.uop.iq_type[1] connect slots_12.io.brupdate.b2.uop.iq_type[2], issue_slots[12].brupdate.b2.uop.iq_type[2] connect slots_12.io.brupdate.b2.uop.iq_type[3], issue_slots[12].brupdate.b2.uop.iq_type[3] connect slots_12.io.brupdate.b2.uop.debug_pc, issue_slots[12].brupdate.b2.uop.debug_pc connect slots_12.io.brupdate.b2.uop.is_rvc, issue_slots[12].brupdate.b2.uop.is_rvc connect slots_12.io.brupdate.b2.uop.debug_inst, issue_slots[12].brupdate.b2.uop.debug_inst connect slots_12.io.brupdate.b2.uop.inst, issue_slots[12].brupdate.b2.uop.inst connect slots_12.io.brupdate.b1.mispredict_mask, issue_slots[12].brupdate.b1.mispredict_mask connect slots_12.io.brupdate.b1.resolve_mask, issue_slots[12].brupdate.b1.resolve_mask connect issue_slots[12].out_uop.debug_tsrc, slots_12.io.out_uop.debug_tsrc connect issue_slots[12].out_uop.debug_fsrc, slots_12.io.out_uop.debug_fsrc connect issue_slots[12].out_uop.bp_xcpt_if, slots_12.io.out_uop.bp_xcpt_if connect issue_slots[12].out_uop.bp_debug_if, slots_12.io.out_uop.bp_debug_if connect issue_slots[12].out_uop.xcpt_ma_if, slots_12.io.out_uop.xcpt_ma_if connect issue_slots[12].out_uop.xcpt_ae_if, slots_12.io.out_uop.xcpt_ae_if connect issue_slots[12].out_uop.xcpt_pf_if, slots_12.io.out_uop.xcpt_pf_if connect issue_slots[12].out_uop.fp_typ, slots_12.io.out_uop.fp_typ connect issue_slots[12].out_uop.fp_rm, slots_12.io.out_uop.fp_rm connect issue_slots[12].out_uop.fp_val, slots_12.io.out_uop.fp_val connect issue_slots[12].out_uop.fcn_op, slots_12.io.out_uop.fcn_op connect issue_slots[12].out_uop.fcn_dw, slots_12.io.out_uop.fcn_dw connect issue_slots[12].out_uop.frs3_en, slots_12.io.out_uop.frs3_en connect issue_slots[12].out_uop.lrs2_rtype, slots_12.io.out_uop.lrs2_rtype connect issue_slots[12].out_uop.lrs1_rtype, slots_12.io.out_uop.lrs1_rtype connect issue_slots[12].out_uop.dst_rtype, slots_12.io.out_uop.dst_rtype connect issue_slots[12].out_uop.lrs3, slots_12.io.out_uop.lrs3 connect issue_slots[12].out_uop.lrs2, slots_12.io.out_uop.lrs2 connect issue_slots[12].out_uop.lrs1, slots_12.io.out_uop.lrs1 connect issue_slots[12].out_uop.ldst, slots_12.io.out_uop.ldst connect issue_slots[12].out_uop.ldst_is_rs1, slots_12.io.out_uop.ldst_is_rs1 connect issue_slots[12].out_uop.csr_cmd, slots_12.io.out_uop.csr_cmd connect issue_slots[12].out_uop.flush_on_commit, slots_12.io.out_uop.flush_on_commit connect issue_slots[12].out_uop.is_unique, slots_12.io.out_uop.is_unique connect issue_slots[12].out_uop.uses_stq, slots_12.io.out_uop.uses_stq connect issue_slots[12].out_uop.uses_ldq, slots_12.io.out_uop.uses_ldq connect issue_slots[12].out_uop.mem_signed, slots_12.io.out_uop.mem_signed connect issue_slots[12].out_uop.mem_size, slots_12.io.out_uop.mem_size connect issue_slots[12].out_uop.mem_cmd, slots_12.io.out_uop.mem_cmd connect issue_slots[12].out_uop.exc_cause, slots_12.io.out_uop.exc_cause connect issue_slots[12].out_uop.exception, slots_12.io.out_uop.exception connect issue_slots[12].out_uop.stale_pdst, slots_12.io.out_uop.stale_pdst connect issue_slots[12].out_uop.ppred_busy, slots_12.io.out_uop.ppred_busy connect issue_slots[12].out_uop.prs3_busy, slots_12.io.out_uop.prs3_busy connect issue_slots[12].out_uop.prs2_busy, slots_12.io.out_uop.prs2_busy connect issue_slots[12].out_uop.prs1_busy, slots_12.io.out_uop.prs1_busy connect issue_slots[12].out_uop.ppred, slots_12.io.out_uop.ppred connect issue_slots[12].out_uop.prs3, slots_12.io.out_uop.prs3 connect issue_slots[12].out_uop.prs2, slots_12.io.out_uop.prs2 connect issue_slots[12].out_uop.prs1, slots_12.io.out_uop.prs1 connect issue_slots[12].out_uop.pdst, slots_12.io.out_uop.pdst connect issue_slots[12].out_uop.rxq_idx, slots_12.io.out_uop.rxq_idx connect issue_slots[12].out_uop.stq_idx, slots_12.io.out_uop.stq_idx connect issue_slots[12].out_uop.ldq_idx, slots_12.io.out_uop.ldq_idx connect issue_slots[12].out_uop.rob_idx, slots_12.io.out_uop.rob_idx connect issue_slots[12].out_uop.fp_ctrl.vec, slots_12.io.out_uop.fp_ctrl.vec connect issue_slots[12].out_uop.fp_ctrl.wflags, slots_12.io.out_uop.fp_ctrl.wflags connect issue_slots[12].out_uop.fp_ctrl.sqrt, slots_12.io.out_uop.fp_ctrl.sqrt connect issue_slots[12].out_uop.fp_ctrl.div, slots_12.io.out_uop.fp_ctrl.div connect issue_slots[12].out_uop.fp_ctrl.fma, slots_12.io.out_uop.fp_ctrl.fma connect issue_slots[12].out_uop.fp_ctrl.fastpipe, slots_12.io.out_uop.fp_ctrl.fastpipe connect issue_slots[12].out_uop.fp_ctrl.toint, slots_12.io.out_uop.fp_ctrl.toint connect issue_slots[12].out_uop.fp_ctrl.fromint, slots_12.io.out_uop.fp_ctrl.fromint connect issue_slots[12].out_uop.fp_ctrl.typeTagOut, slots_12.io.out_uop.fp_ctrl.typeTagOut connect issue_slots[12].out_uop.fp_ctrl.typeTagIn, slots_12.io.out_uop.fp_ctrl.typeTagIn connect issue_slots[12].out_uop.fp_ctrl.swap23, slots_12.io.out_uop.fp_ctrl.swap23 connect issue_slots[12].out_uop.fp_ctrl.swap12, slots_12.io.out_uop.fp_ctrl.swap12 connect issue_slots[12].out_uop.fp_ctrl.ren3, slots_12.io.out_uop.fp_ctrl.ren3 connect issue_slots[12].out_uop.fp_ctrl.ren2, slots_12.io.out_uop.fp_ctrl.ren2 connect issue_slots[12].out_uop.fp_ctrl.ren1, slots_12.io.out_uop.fp_ctrl.ren1 connect issue_slots[12].out_uop.fp_ctrl.wen, slots_12.io.out_uop.fp_ctrl.wen connect issue_slots[12].out_uop.fp_ctrl.ldst, slots_12.io.out_uop.fp_ctrl.ldst connect issue_slots[12].out_uop.op2_sel, slots_12.io.out_uop.op2_sel connect issue_slots[12].out_uop.op1_sel, slots_12.io.out_uop.op1_sel connect issue_slots[12].out_uop.imm_packed, slots_12.io.out_uop.imm_packed connect issue_slots[12].out_uop.pimm, slots_12.io.out_uop.pimm connect issue_slots[12].out_uop.imm_sel, slots_12.io.out_uop.imm_sel connect issue_slots[12].out_uop.imm_rename, slots_12.io.out_uop.imm_rename connect issue_slots[12].out_uop.taken, slots_12.io.out_uop.taken connect issue_slots[12].out_uop.pc_lob, slots_12.io.out_uop.pc_lob connect issue_slots[12].out_uop.edge_inst, slots_12.io.out_uop.edge_inst connect issue_slots[12].out_uop.ftq_idx, slots_12.io.out_uop.ftq_idx connect issue_slots[12].out_uop.is_mov, slots_12.io.out_uop.is_mov connect issue_slots[12].out_uop.is_rocc, slots_12.io.out_uop.is_rocc connect issue_slots[12].out_uop.is_sys_pc2epc, slots_12.io.out_uop.is_sys_pc2epc connect issue_slots[12].out_uop.is_eret, slots_12.io.out_uop.is_eret connect issue_slots[12].out_uop.is_amo, slots_12.io.out_uop.is_amo connect issue_slots[12].out_uop.is_sfence, slots_12.io.out_uop.is_sfence connect issue_slots[12].out_uop.is_fencei, slots_12.io.out_uop.is_fencei connect issue_slots[12].out_uop.is_fence, slots_12.io.out_uop.is_fence connect issue_slots[12].out_uop.is_sfb, slots_12.io.out_uop.is_sfb connect issue_slots[12].out_uop.br_type, slots_12.io.out_uop.br_type connect issue_slots[12].out_uop.br_tag, slots_12.io.out_uop.br_tag connect issue_slots[12].out_uop.br_mask, slots_12.io.out_uop.br_mask connect issue_slots[12].out_uop.dis_col_sel, slots_12.io.out_uop.dis_col_sel connect issue_slots[12].out_uop.iw_p3_bypass_hint, slots_12.io.out_uop.iw_p3_bypass_hint connect issue_slots[12].out_uop.iw_p2_bypass_hint, slots_12.io.out_uop.iw_p2_bypass_hint connect issue_slots[12].out_uop.iw_p1_bypass_hint, slots_12.io.out_uop.iw_p1_bypass_hint connect issue_slots[12].out_uop.iw_p2_speculative_child, slots_12.io.out_uop.iw_p2_speculative_child connect issue_slots[12].out_uop.iw_p1_speculative_child, slots_12.io.out_uop.iw_p1_speculative_child connect issue_slots[12].out_uop.iw_issued_partial_dgen, slots_12.io.out_uop.iw_issued_partial_dgen connect issue_slots[12].out_uop.iw_issued_partial_agen, slots_12.io.out_uop.iw_issued_partial_agen connect issue_slots[12].out_uop.iw_issued, slots_12.io.out_uop.iw_issued connect issue_slots[12].out_uop.fu_code[0], slots_12.io.out_uop.fu_code[0] connect issue_slots[12].out_uop.fu_code[1], slots_12.io.out_uop.fu_code[1] connect issue_slots[12].out_uop.fu_code[2], slots_12.io.out_uop.fu_code[2] connect issue_slots[12].out_uop.fu_code[3], slots_12.io.out_uop.fu_code[3] connect issue_slots[12].out_uop.fu_code[4], slots_12.io.out_uop.fu_code[4] connect issue_slots[12].out_uop.fu_code[5], slots_12.io.out_uop.fu_code[5] connect issue_slots[12].out_uop.fu_code[6], slots_12.io.out_uop.fu_code[6] connect issue_slots[12].out_uop.fu_code[7], slots_12.io.out_uop.fu_code[7] connect issue_slots[12].out_uop.fu_code[8], slots_12.io.out_uop.fu_code[8] connect issue_slots[12].out_uop.fu_code[9], slots_12.io.out_uop.fu_code[9] connect issue_slots[12].out_uop.iq_type[0], slots_12.io.out_uop.iq_type[0] connect issue_slots[12].out_uop.iq_type[1], slots_12.io.out_uop.iq_type[1] connect issue_slots[12].out_uop.iq_type[2], slots_12.io.out_uop.iq_type[2] connect issue_slots[12].out_uop.iq_type[3], slots_12.io.out_uop.iq_type[3] connect issue_slots[12].out_uop.debug_pc, slots_12.io.out_uop.debug_pc connect issue_slots[12].out_uop.is_rvc, slots_12.io.out_uop.is_rvc connect issue_slots[12].out_uop.debug_inst, slots_12.io.out_uop.debug_inst connect issue_slots[12].out_uop.inst, slots_12.io.out_uop.inst connect slots_12.io.in_uop.bits.debug_tsrc, issue_slots[12].in_uop.bits.debug_tsrc connect slots_12.io.in_uop.bits.debug_fsrc, issue_slots[12].in_uop.bits.debug_fsrc connect slots_12.io.in_uop.bits.bp_xcpt_if, issue_slots[12].in_uop.bits.bp_xcpt_if connect slots_12.io.in_uop.bits.bp_debug_if, issue_slots[12].in_uop.bits.bp_debug_if connect slots_12.io.in_uop.bits.xcpt_ma_if, issue_slots[12].in_uop.bits.xcpt_ma_if connect slots_12.io.in_uop.bits.xcpt_ae_if, issue_slots[12].in_uop.bits.xcpt_ae_if connect slots_12.io.in_uop.bits.xcpt_pf_if, issue_slots[12].in_uop.bits.xcpt_pf_if connect slots_12.io.in_uop.bits.fp_typ, issue_slots[12].in_uop.bits.fp_typ connect slots_12.io.in_uop.bits.fp_rm, issue_slots[12].in_uop.bits.fp_rm connect slots_12.io.in_uop.bits.fp_val, issue_slots[12].in_uop.bits.fp_val connect slots_12.io.in_uop.bits.fcn_op, issue_slots[12].in_uop.bits.fcn_op connect slots_12.io.in_uop.bits.fcn_dw, issue_slots[12].in_uop.bits.fcn_dw connect slots_12.io.in_uop.bits.frs3_en, issue_slots[12].in_uop.bits.frs3_en connect slots_12.io.in_uop.bits.lrs2_rtype, issue_slots[12].in_uop.bits.lrs2_rtype connect slots_12.io.in_uop.bits.lrs1_rtype, issue_slots[12].in_uop.bits.lrs1_rtype connect slots_12.io.in_uop.bits.dst_rtype, issue_slots[12].in_uop.bits.dst_rtype connect slots_12.io.in_uop.bits.lrs3, issue_slots[12].in_uop.bits.lrs3 connect slots_12.io.in_uop.bits.lrs2, issue_slots[12].in_uop.bits.lrs2 connect slots_12.io.in_uop.bits.lrs1, issue_slots[12].in_uop.bits.lrs1 connect slots_12.io.in_uop.bits.ldst, issue_slots[12].in_uop.bits.ldst connect slots_12.io.in_uop.bits.ldst_is_rs1, issue_slots[12].in_uop.bits.ldst_is_rs1 connect slots_12.io.in_uop.bits.csr_cmd, issue_slots[12].in_uop.bits.csr_cmd connect slots_12.io.in_uop.bits.flush_on_commit, issue_slots[12].in_uop.bits.flush_on_commit connect slots_12.io.in_uop.bits.is_unique, issue_slots[12].in_uop.bits.is_unique connect slots_12.io.in_uop.bits.uses_stq, issue_slots[12].in_uop.bits.uses_stq connect slots_12.io.in_uop.bits.uses_ldq, issue_slots[12].in_uop.bits.uses_ldq connect slots_12.io.in_uop.bits.mem_signed, issue_slots[12].in_uop.bits.mem_signed connect slots_12.io.in_uop.bits.mem_size, issue_slots[12].in_uop.bits.mem_size connect slots_12.io.in_uop.bits.mem_cmd, issue_slots[12].in_uop.bits.mem_cmd connect slots_12.io.in_uop.bits.exc_cause, issue_slots[12].in_uop.bits.exc_cause connect slots_12.io.in_uop.bits.exception, issue_slots[12].in_uop.bits.exception connect slots_12.io.in_uop.bits.stale_pdst, issue_slots[12].in_uop.bits.stale_pdst connect slots_12.io.in_uop.bits.ppred_busy, issue_slots[12].in_uop.bits.ppred_busy connect slots_12.io.in_uop.bits.prs3_busy, issue_slots[12].in_uop.bits.prs3_busy connect slots_12.io.in_uop.bits.prs2_busy, issue_slots[12].in_uop.bits.prs2_busy connect slots_12.io.in_uop.bits.prs1_busy, issue_slots[12].in_uop.bits.prs1_busy connect slots_12.io.in_uop.bits.ppred, issue_slots[12].in_uop.bits.ppred connect slots_12.io.in_uop.bits.prs3, issue_slots[12].in_uop.bits.prs3 connect slots_12.io.in_uop.bits.prs2, issue_slots[12].in_uop.bits.prs2 connect slots_12.io.in_uop.bits.prs1, issue_slots[12].in_uop.bits.prs1 connect slots_12.io.in_uop.bits.pdst, issue_slots[12].in_uop.bits.pdst connect slots_12.io.in_uop.bits.rxq_idx, issue_slots[12].in_uop.bits.rxq_idx connect slots_12.io.in_uop.bits.stq_idx, issue_slots[12].in_uop.bits.stq_idx connect slots_12.io.in_uop.bits.ldq_idx, issue_slots[12].in_uop.bits.ldq_idx connect slots_12.io.in_uop.bits.rob_idx, issue_slots[12].in_uop.bits.rob_idx connect slots_12.io.in_uop.bits.fp_ctrl.vec, issue_slots[12].in_uop.bits.fp_ctrl.vec connect slots_12.io.in_uop.bits.fp_ctrl.wflags, issue_slots[12].in_uop.bits.fp_ctrl.wflags connect slots_12.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[12].in_uop.bits.fp_ctrl.sqrt connect slots_12.io.in_uop.bits.fp_ctrl.div, issue_slots[12].in_uop.bits.fp_ctrl.div connect slots_12.io.in_uop.bits.fp_ctrl.fma, issue_slots[12].in_uop.bits.fp_ctrl.fma connect slots_12.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[12].in_uop.bits.fp_ctrl.fastpipe connect slots_12.io.in_uop.bits.fp_ctrl.toint, issue_slots[12].in_uop.bits.fp_ctrl.toint connect slots_12.io.in_uop.bits.fp_ctrl.fromint, issue_slots[12].in_uop.bits.fp_ctrl.fromint connect slots_12.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[12].in_uop.bits.fp_ctrl.typeTagOut connect slots_12.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[12].in_uop.bits.fp_ctrl.typeTagIn connect slots_12.io.in_uop.bits.fp_ctrl.swap23, issue_slots[12].in_uop.bits.fp_ctrl.swap23 connect slots_12.io.in_uop.bits.fp_ctrl.swap12, issue_slots[12].in_uop.bits.fp_ctrl.swap12 connect slots_12.io.in_uop.bits.fp_ctrl.ren3, issue_slots[12].in_uop.bits.fp_ctrl.ren3 connect slots_12.io.in_uop.bits.fp_ctrl.ren2, issue_slots[12].in_uop.bits.fp_ctrl.ren2 connect slots_12.io.in_uop.bits.fp_ctrl.ren1, issue_slots[12].in_uop.bits.fp_ctrl.ren1 connect slots_12.io.in_uop.bits.fp_ctrl.wen, issue_slots[12].in_uop.bits.fp_ctrl.wen connect slots_12.io.in_uop.bits.fp_ctrl.ldst, issue_slots[12].in_uop.bits.fp_ctrl.ldst connect slots_12.io.in_uop.bits.op2_sel, issue_slots[12].in_uop.bits.op2_sel connect slots_12.io.in_uop.bits.op1_sel, issue_slots[12].in_uop.bits.op1_sel connect slots_12.io.in_uop.bits.imm_packed, issue_slots[12].in_uop.bits.imm_packed connect slots_12.io.in_uop.bits.pimm, issue_slots[12].in_uop.bits.pimm connect slots_12.io.in_uop.bits.imm_sel, issue_slots[12].in_uop.bits.imm_sel connect slots_12.io.in_uop.bits.imm_rename, issue_slots[12].in_uop.bits.imm_rename connect slots_12.io.in_uop.bits.taken, issue_slots[12].in_uop.bits.taken connect slots_12.io.in_uop.bits.pc_lob, issue_slots[12].in_uop.bits.pc_lob connect slots_12.io.in_uop.bits.edge_inst, issue_slots[12].in_uop.bits.edge_inst connect slots_12.io.in_uop.bits.ftq_idx, issue_slots[12].in_uop.bits.ftq_idx connect slots_12.io.in_uop.bits.is_mov, issue_slots[12].in_uop.bits.is_mov connect slots_12.io.in_uop.bits.is_rocc, issue_slots[12].in_uop.bits.is_rocc connect slots_12.io.in_uop.bits.is_sys_pc2epc, issue_slots[12].in_uop.bits.is_sys_pc2epc connect slots_12.io.in_uop.bits.is_eret, issue_slots[12].in_uop.bits.is_eret connect slots_12.io.in_uop.bits.is_amo, issue_slots[12].in_uop.bits.is_amo connect slots_12.io.in_uop.bits.is_sfence, issue_slots[12].in_uop.bits.is_sfence connect slots_12.io.in_uop.bits.is_fencei, issue_slots[12].in_uop.bits.is_fencei connect slots_12.io.in_uop.bits.is_fence, issue_slots[12].in_uop.bits.is_fence connect slots_12.io.in_uop.bits.is_sfb, issue_slots[12].in_uop.bits.is_sfb connect slots_12.io.in_uop.bits.br_type, issue_slots[12].in_uop.bits.br_type connect slots_12.io.in_uop.bits.br_tag, issue_slots[12].in_uop.bits.br_tag connect slots_12.io.in_uop.bits.br_mask, issue_slots[12].in_uop.bits.br_mask connect slots_12.io.in_uop.bits.dis_col_sel, issue_slots[12].in_uop.bits.dis_col_sel connect slots_12.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[12].in_uop.bits.iw_p3_bypass_hint connect slots_12.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[12].in_uop.bits.iw_p2_bypass_hint connect slots_12.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[12].in_uop.bits.iw_p1_bypass_hint connect slots_12.io.in_uop.bits.iw_p2_speculative_child, issue_slots[12].in_uop.bits.iw_p2_speculative_child connect slots_12.io.in_uop.bits.iw_p1_speculative_child, issue_slots[12].in_uop.bits.iw_p1_speculative_child connect slots_12.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[12].in_uop.bits.iw_issued_partial_dgen connect slots_12.io.in_uop.bits.iw_issued_partial_agen, issue_slots[12].in_uop.bits.iw_issued_partial_agen connect slots_12.io.in_uop.bits.iw_issued, issue_slots[12].in_uop.bits.iw_issued connect slots_12.io.in_uop.bits.fu_code[0], issue_slots[12].in_uop.bits.fu_code[0] connect slots_12.io.in_uop.bits.fu_code[1], issue_slots[12].in_uop.bits.fu_code[1] connect slots_12.io.in_uop.bits.fu_code[2], issue_slots[12].in_uop.bits.fu_code[2] connect slots_12.io.in_uop.bits.fu_code[3], issue_slots[12].in_uop.bits.fu_code[3] connect slots_12.io.in_uop.bits.fu_code[4], issue_slots[12].in_uop.bits.fu_code[4] connect slots_12.io.in_uop.bits.fu_code[5], issue_slots[12].in_uop.bits.fu_code[5] connect slots_12.io.in_uop.bits.fu_code[6], issue_slots[12].in_uop.bits.fu_code[6] connect slots_12.io.in_uop.bits.fu_code[7], issue_slots[12].in_uop.bits.fu_code[7] connect slots_12.io.in_uop.bits.fu_code[8], issue_slots[12].in_uop.bits.fu_code[8] connect slots_12.io.in_uop.bits.fu_code[9], issue_slots[12].in_uop.bits.fu_code[9] connect slots_12.io.in_uop.bits.iq_type[0], issue_slots[12].in_uop.bits.iq_type[0] connect slots_12.io.in_uop.bits.iq_type[1], issue_slots[12].in_uop.bits.iq_type[1] connect slots_12.io.in_uop.bits.iq_type[2], issue_slots[12].in_uop.bits.iq_type[2] connect slots_12.io.in_uop.bits.iq_type[3], issue_slots[12].in_uop.bits.iq_type[3] connect slots_12.io.in_uop.bits.debug_pc, issue_slots[12].in_uop.bits.debug_pc connect slots_12.io.in_uop.bits.is_rvc, issue_slots[12].in_uop.bits.is_rvc connect slots_12.io.in_uop.bits.debug_inst, issue_slots[12].in_uop.bits.debug_inst connect slots_12.io.in_uop.bits.inst, issue_slots[12].in_uop.bits.inst connect slots_12.io.in_uop.valid, issue_slots[12].in_uop.valid connect issue_slots[12].iss_uop.debug_tsrc, slots_12.io.iss_uop.debug_tsrc connect issue_slots[12].iss_uop.debug_fsrc, slots_12.io.iss_uop.debug_fsrc connect issue_slots[12].iss_uop.bp_xcpt_if, slots_12.io.iss_uop.bp_xcpt_if connect issue_slots[12].iss_uop.bp_debug_if, slots_12.io.iss_uop.bp_debug_if connect issue_slots[12].iss_uop.xcpt_ma_if, slots_12.io.iss_uop.xcpt_ma_if connect issue_slots[12].iss_uop.xcpt_ae_if, slots_12.io.iss_uop.xcpt_ae_if connect issue_slots[12].iss_uop.xcpt_pf_if, slots_12.io.iss_uop.xcpt_pf_if connect issue_slots[12].iss_uop.fp_typ, slots_12.io.iss_uop.fp_typ connect issue_slots[12].iss_uop.fp_rm, slots_12.io.iss_uop.fp_rm connect issue_slots[12].iss_uop.fp_val, slots_12.io.iss_uop.fp_val connect issue_slots[12].iss_uop.fcn_op, slots_12.io.iss_uop.fcn_op connect issue_slots[12].iss_uop.fcn_dw, slots_12.io.iss_uop.fcn_dw connect issue_slots[12].iss_uop.frs3_en, slots_12.io.iss_uop.frs3_en connect issue_slots[12].iss_uop.lrs2_rtype, slots_12.io.iss_uop.lrs2_rtype connect issue_slots[12].iss_uop.lrs1_rtype, slots_12.io.iss_uop.lrs1_rtype connect issue_slots[12].iss_uop.dst_rtype, slots_12.io.iss_uop.dst_rtype connect issue_slots[12].iss_uop.lrs3, slots_12.io.iss_uop.lrs3 connect issue_slots[12].iss_uop.lrs2, slots_12.io.iss_uop.lrs2 connect issue_slots[12].iss_uop.lrs1, slots_12.io.iss_uop.lrs1 connect issue_slots[12].iss_uop.ldst, slots_12.io.iss_uop.ldst connect issue_slots[12].iss_uop.ldst_is_rs1, slots_12.io.iss_uop.ldst_is_rs1 connect issue_slots[12].iss_uop.csr_cmd, slots_12.io.iss_uop.csr_cmd connect issue_slots[12].iss_uop.flush_on_commit, slots_12.io.iss_uop.flush_on_commit connect issue_slots[12].iss_uop.is_unique, slots_12.io.iss_uop.is_unique connect issue_slots[12].iss_uop.uses_stq, slots_12.io.iss_uop.uses_stq connect issue_slots[12].iss_uop.uses_ldq, slots_12.io.iss_uop.uses_ldq connect issue_slots[12].iss_uop.mem_signed, slots_12.io.iss_uop.mem_signed connect issue_slots[12].iss_uop.mem_size, slots_12.io.iss_uop.mem_size connect issue_slots[12].iss_uop.mem_cmd, slots_12.io.iss_uop.mem_cmd connect issue_slots[12].iss_uop.exc_cause, slots_12.io.iss_uop.exc_cause connect issue_slots[12].iss_uop.exception, slots_12.io.iss_uop.exception connect issue_slots[12].iss_uop.stale_pdst, slots_12.io.iss_uop.stale_pdst connect issue_slots[12].iss_uop.ppred_busy, slots_12.io.iss_uop.ppred_busy connect issue_slots[12].iss_uop.prs3_busy, slots_12.io.iss_uop.prs3_busy connect issue_slots[12].iss_uop.prs2_busy, slots_12.io.iss_uop.prs2_busy connect issue_slots[12].iss_uop.prs1_busy, slots_12.io.iss_uop.prs1_busy connect issue_slots[12].iss_uop.ppred, slots_12.io.iss_uop.ppred connect issue_slots[12].iss_uop.prs3, slots_12.io.iss_uop.prs3 connect issue_slots[12].iss_uop.prs2, slots_12.io.iss_uop.prs2 connect issue_slots[12].iss_uop.prs1, slots_12.io.iss_uop.prs1 connect issue_slots[12].iss_uop.pdst, slots_12.io.iss_uop.pdst connect issue_slots[12].iss_uop.rxq_idx, slots_12.io.iss_uop.rxq_idx connect issue_slots[12].iss_uop.stq_idx, slots_12.io.iss_uop.stq_idx connect issue_slots[12].iss_uop.ldq_idx, slots_12.io.iss_uop.ldq_idx connect issue_slots[12].iss_uop.rob_idx, slots_12.io.iss_uop.rob_idx connect issue_slots[12].iss_uop.fp_ctrl.vec, slots_12.io.iss_uop.fp_ctrl.vec connect issue_slots[12].iss_uop.fp_ctrl.wflags, slots_12.io.iss_uop.fp_ctrl.wflags connect issue_slots[12].iss_uop.fp_ctrl.sqrt, slots_12.io.iss_uop.fp_ctrl.sqrt connect issue_slots[12].iss_uop.fp_ctrl.div, slots_12.io.iss_uop.fp_ctrl.div connect issue_slots[12].iss_uop.fp_ctrl.fma, slots_12.io.iss_uop.fp_ctrl.fma connect issue_slots[12].iss_uop.fp_ctrl.fastpipe, slots_12.io.iss_uop.fp_ctrl.fastpipe connect issue_slots[12].iss_uop.fp_ctrl.toint, slots_12.io.iss_uop.fp_ctrl.toint connect issue_slots[12].iss_uop.fp_ctrl.fromint, slots_12.io.iss_uop.fp_ctrl.fromint connect issue_slots[12].iss_uop.fp_ctrl.typeTagOut, slots_12.io.iss_uop.fp_ctrl.typeTagOut connect issue_slots[12].iss_uop.fp_ctrl.typeTagIn, slots_12.io.iss_uop.fp_ctrl.typeTagIn connect issue_slots[12].iss_uop.fp_ctrl.swap23, slots_12.io.iss_uop.fp_ctrl.swap23 connect issue_slots[12].iss_uop.fp_ctrl.swap12, slots_12.io.iss_uop.fp_ctrl.swap12 connect issue_slots[12].iss_uop.fp_ctrl.ren3, slots_12.io.iss_uop.fp_ctrl.ren3 connect issue_slots[12].iss_uop.fp_ctrl.ren2, slots_12.io.iss_uop.fp_ctrl.ren2 connect issue_slots[12].iss_uop.fp_ctrl.ren1, slots_12.io.iss_uop.fp_ctrl.ren1 connect issue_slots[12].iss_uop.fp_ctrl.wen, slots_12.io.iss_uop.fp_ctrl.wen connect issue_slots[12].iss_uop.fp_ctrl.ldst, slots_12.io.iss_uop.fp_ctrl.ldst connect issue_slots[12].iss_uop.op2_sel, slots_12.io.iss_uop.op2_sel connect issue_slots[12].iss_uop.op1_sel, slots_12.io.iss_uop.op1_sel connect issue_slots[12].iss_uop.imm_packed, slots_12.io.iss_uop.imm_packed connect issue_slots[12].iss_uop.pimm, slots_12.io.iss_uop.pimm connect issue_slots[12].iss_uop.imm_sel, slots_12.io.iss_uop.imm_sel connect issue_slots[12].iss_uop.imm_rename, slots_12.io.iss_uop.imm_rename connect issue_slots[12].iss_uop.taken, slots_12.io.iss_uop.taken connect issue_slots[12].iss_uop.pc_lob, slots_12.io.iss_uop.pc_lob connect issue_slots[12].iss_uop.edge_inst, slots_12.io.iss_uop.edge_inst connect issue_slots[12].iss_uop.ftq_idx, slots_12.io.iss_uop.ftq_idx connect issue_slots[12].iss_uop.is_mov, slots_12.io.iss_uop.is_mov connect issue_slots[12].iss_uop.is_rocc, slots_12.io.iss_uop.is_rocc connect issue_slots[12].iss_uop.is_sys_pc2epc, slots_12.io.iss_uop.is_sys_pc2epc connect issue_slots[12].iss_uop.is_eret, slots_12.io.iss_uop.is_eret connect issue_slots[12].iss_uop.is_amo, slots_12.io.iss_uop.is_amo connect issue_slots[12].iss_uop.is_sfence, slots_12.io.iss_uop.is_sfence connect issue_slots[12].iss_uop.is_fencei, slots_12.io.iss_uop.is_fencei connect issue_slots[12].iss_uop.is_fence, slots_12.io.iss_uop.is_fence connect issue_slots[12].iss_uop.is_sfb, slots_12.io.iss_uop.is_sfb connect issue_slots[12].iss_uop.br_type, slots_12.io.iss_uop.br_type connect issue_slots[12].iss_uop.br_tag, slots_12.io.iss_uop.br_tag connect issue_slots[12].iss_uop.br_mask, slots_12.io.iss_uop.br_mask connect issue_slots[12].iss_uop.dis_col_sel, slots_12.io.iss_uop.dis_col_sel connect issue_slots[12].iss_uop.iw_p3_bypass_hint, slots_12.io.iss_uop.iw_p3_bypass_hint connect issue_slots[12].iss_uop.iw_p2_bypass_hint, slots_12.io.iss_uop.iw_p2_bypass_hint connect issue_slots[12].iss_uop.iw_p1_bypass_hint, slots_12.io.iss_uop.iw_p1_bypass_hint connect issue_slots[12].iss_uop.iw_p2_speculative_child, slots_12.io.iss_uop.iw_p2_speculative_child connect issue_slots[12].iss_uop.iw_p1_speculative_child, slots_12.io.iss_uop.iw_p1_speculative_child connect issue_slots[12].iss_uop.iw_issued_partial_dgen, slots_12.io.iss_uop.iw_issued_partial_dgen connect issue_slots[12].iss_uop.iw_issued_partial_agen, slots_12.io.iss_uop.iw_issued_partial_agen connect issue_slots[12].iss_uop.iw_issued, slots_12.io.iss_uop.iw_issued connect issue_slots[12].iss_uop.fu_code[0], slots_12.io.iss_uop.fu_code[0] connect issue_slots[12].iss_uop.fu_code[1], slots_12.io.iss_uop.fu_code[1] connect issue_slots[12].iss_uop.fu_code[2], slots_12.io.iss_uop.fu_code[2] connect issue_slots[12].iss_uop.fu_code[3], slots_12.io.iss_uop.fu_code[3] connect issue_slots[12].iss_uop.fu_code[4], slots_12.io.iss_uop.fu_code[4] connect issue_slots[12].iss_uop.fu_code[5], slots_12.io.iss_uop.fu_code[5] connect issue_slots[12].iss_uop.fu_code[6], slots_12.io.iss_uop.fu_code[6] connect issue_slots[12].iss_uop.fu_code[7], slots_12.io.iss_uop.fu_code[7] connect issue_slots[12].iss_uop.fu_code[8], slots_12.io.iss_uop.fu_code[8] connect issue_slots[12].iss_uop.fu_code[9], slots_12.io.iss_uop.fu_code[9] connect issue_slots[12].iss_uop.iq_type[0], slots_12.io.iss_uop.iq_type[0] connect issue_slots[12].iss_uop.iq_type[1], slots_12.io.iss_uop.iq_type[1] connect issue_slots[12].iss_uop.iq_type[2], slots_12.io.iss_uop.iq_type[2] connect issue_slots[12].iss_uop.iq_type[3], slots_12.io.iss_uop.iq_type[3] connect issue_slots[12].iss_uop.debug_pc, slots_12.io.iss_uop.debug_pc connect issue_slots[12].iss_uop.is_rvc, slots_12.io.iss_uop.is_rvc connect issue_slots[12].iss_uop.debug_inst, slots_12.io.iss_uop.debug_inst connect issue_slots[12].iss_uop.inst, slots_12.io.iss_uop.inst connect slots_12.io.grant, issue_slots[12].grant connect issue_slots[12].request, slots_12.io.request connect issue_slots[12].will_be_valid, slots_12.io.will_be_valid connect issue_slots[12].valid, slots_12.io.valid connect slots_13.io.child_rebusys, issue_slots[13].child_rebusys connect slots_13.io.pred_wakeup_port.bits, issue_slots[13].pred_wakeup_port.bits connect slots_13.io.pred_wakeup_port.valid, issue_slots[13].pred_wakeup_port.valid connect slots_13.io.wakeup_ports[0].bits.rebusy, issue_slots[13].wakeup_ports[0].bits.rebusy connect slots_13.io.wakeup_ports[0].bits.speculative_mask, issue_slots[13].wakeup_ports[0].bits.speculative_mask connect slots_13.io.wakeup_ports[0].bits.bypassable, issue_slots[13].wakeup_ports[0].bits.bypassable connect slots_13.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[13].wakeup_ports[0].bits.uop.debug_tsrc connect slots_13.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[13].wakeup_ports[0].bits.uop.debug_fsrc connect slots_13.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[13].wakeup_ports[0].bits.uop.bp_xcpt_if connect slots_13.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[13].wakeup_ports[0].bits.uop.bp_debug_if connect slots_13.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[13].wakeup_ports[0].bits.uop.xcpt_ma_if connect slots_13.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[13].wakeup_ports[0].bits.uop.xcpt_ae_if connect slots_13.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[13].wakeup_ports[0].bits.uop.xcpt_pf_if connect slots_13.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[13].wakeup_ports[0].bits.uop.fp_typ connect slots_13.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[13].wakeup_ports[0].bits.uop.fp_rm connect slots_13.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[13].wakeup_ports[0].bits.uop.fp_val connect slots_13.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[13].wakeup_ports[0].bits.uop.fcn_op connect slots_13.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[13].wakeup_ports[0].bits.uop.fcn_dw connect slots_13.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[13].wakeup_ports[0].bits.uop.frs3_en connect slots_13.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[13].wakeup_ports[0].bits.uop.lrs2_rtype connect slots_13.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[13].wakeup_ports[0].bits.uop.lrs1_rtype connect slots_13.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[13].wakeup_ports[0].bits.uop.dst_rtype connect slots_13.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[13].wakeup_ports[0].bits.uop.lrs3 connect slots_13.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[13].wakeup_ports[0].bits.uop.lrs2 connect slots_13.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[13].wakeup_ports[0].bits.uop.lrs1 connect slots_13.io.wakeup_ports[0].bits.uop.ldst, issue_slots[13].wakeup_ports[0].bits.uop.ldst connect slots_13.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[13].wakeup_ports[0].bits.uop.ldst_is_rs1 connect slots_13.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[13].wakeup_ports[0].bits.uop.csr_cmd connect slots_13.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[13].wakeup_ports[0].bits.uop.flush_on_commit connect slots_13.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[13].wakeup_ports[0].bits.uop.is_unique connect slots_13.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[13].wakeup_ports[0].bits.uop.uses_stq connect slots_13.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[13].wakeup_ports[0].bits.uop.uses_ldq connect slots_13.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[13].wakeup_ports[0].bits.uop.mem_signed connect slots_13.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[13].wakeup_ports[0].bits.uop.mem_size connect slots_13.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[13].wakeup_ports[0].bits.uop.mem_cmd connect slots_13.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[13].wakeup_ports[0].bits.uop.exc_cause connect slots_13.io.wakeup_ports[0].bits.uop.exception, issue_slots[13].wakeup_ports[0].bits.uop.exception connect slots_13.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[13].wakeup_ports[0].bits.uop.stale_pdst connect slots_13.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[13].wakeup_ports[0].bits.uop.ppred_busy connect slots_13.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[13].wakeup_ports[0].bits.uop.prs3_busy connect slots_13.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[13].wakeup_ports[0].bits.uop.prs2_busy connect slots_13.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[13].wakeup_ports[0].bits.uop.prs1_busy connect slots_13.io.wakeup_ports[0].bits.uop.ppred, issue_slots[13].wakeup_ports[0].bits.uop.ppred connect slots_13.io.wakeup_ports[0].bits.uop.prs3, issue_slots[13].wakeup_ports[0].bits.uop.prs3 connect slots_13.io.wakeup_ports[0].bits.uop.prs2, issue_slots[13].wakeup_ports[0].bits.uop.prs2 connect slots_13.io.wakeup_ports[0].bits.uop.prs1, issue_slots[13].wakeup_ports[0].bits.uop.prs1 connect slots_13.io.wakeup_ports[0].bits.uop.pdst, issue_slots[13].wakeup_ports[0].bits.uop.pdst connect slots_13.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[13].wakeup_ports[0].bits.uop.rxq_idx connect slots_13.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[13].wakeup_ports[0].bits.uop.stq_idx connect slots_13.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[13].wakeup_ports[0].bits.uop.ldq_idx connect slots_13.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[13].wakeup_ports[0].bits.uop.rob_idx connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.vec connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.wflags connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.div connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.fma connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.toint connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.fromint connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.wen connect slots_13.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.ldst connect slots_13.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[13].wakeup_ports[0].bits.uop.op2_sel connect slots_13.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[13].wakeup_ports[0].bits.uop.op1_sel connect slots_13.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[13].wakeup_ports[0].bits.uop.imm_packed connect slots_13.io.wakeup_ports[0].bits.uop.pimm, issue_slots[13].wakeup_ports[0].bits.uop.pimm connect slots_13.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[13].wakeup_ports[0].bits.uop.imm_sel connect slots_13.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[13].wakeup_ports[0].bits.uop.imm_rename connect slots_13.io.wakeup_ports[0].bits.uop.taken, issue_slots[13].wakeup_ports[0].bits.uop.taken connect slots_13.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[13].wakeup_ports[0].bits.uop.pc_lob connect slots_13.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[13].wakeup_ports[0].bits.uop.edge_inst connect slots_13.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[13].wakeup_ports[0].bits.uop.ftq_idx connect slots_13.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[13].wakeup_ports[0].bits.uop.is_mov connect slots_13.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[13].wakeup_ports[0].bits.uop.is_rocc connect slots_13.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[13].wakeup_ports[0].bits.uop.is_sys_pc2epc connect slots_13.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[13].wakeup_ports[0].bits.uop.is_eret connect slots_13.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[13].wakeup_ports[0].bits.uop.is_amo connect slots_13.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[13].wakeup_ports[0].bits.uop.is_sfence connect slots_13.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[13].wakeup_ports[0].bits.uop.is_fencei connect slots_13.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[13].wakeup_ports[0].bits.uop.is_fence connect slots_13.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[13].wakeup_ports[0].bits.uop.is_sfb connect slots_13.io.wakeup_ports[0].bits.uop.br_type, issue_slots[13].wakeup_ports[0].bits.uop.br_type connect slots_13.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[13].wakeup_ports[0].bits.uop.br_tag connect slots_13.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[13].wakeup_ports[0].bits.uop.br_mask connect slots_13.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[13].wakeup_ports[0].bits.uop.dis_col_sel connect slots_13.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[13].wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect slots_13.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[13].wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect slots_13.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[13].wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect slots_13.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[13].wakeup_ports[0].bits.uop.iw_p2_speculative_child connect slots_13.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[13].wakeup_ports[0].bits.uop.iw_p1_speculative_child connect slots_13.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[13].wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect slots_13.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[13].wakeup_ports[0].bits.uop.iw_issued_partial_agen connect slots_13.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[13].wakeup_ports[0].bits.uop.iw_issued connect slots_13.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[13].wakeup_ports[0].bits.uop.fu_code[0] connect slots_13.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[13].wakeup_ports[0].bits.uop.fu_code[1] connect slots_13.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[13].wakeup_ports[0].bits.uop.fu_code[2] connect slots_13.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[13].wakeup_ports[0].bits.uop.fu_code[3] connect slots_13.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[13].wakeup_ports[0].bits.uop.fu_code[4] connect slots_13.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[13].wakeup_ports[0].bits.uop.fu_code[5] connect slots_13.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[13].wakeup_ports[0].bits.uop.fu_code[6] connect slots_13.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[13].wakeup_ports[0].bits.uop.fu_code[7] connect slots_13.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[13].wakeup_ports[0].bits.uop.fu_code[8] connect slots_13.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[13].wakeup_ports[0].bits.uop.fu_code[9] connect slots_13.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[13].wakeup_ports[0].bits.uop.iq_type[0] connect slots_13.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[13].wakeup_ports[0].bits.uop.iq_type[1] connect slots_13.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[13].wakeup_ports[0].bits.uop.iq_type[2] connect slots_13.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[13].wakeup_ports[0].bits.uop.iq_type[3] connect slots_13.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[13].wakeup_ports[0].bits.uop.debug_pc connect slots_13.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[13].wakeup_ports[0].bits.uop.is_rvc connect slots_13.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[13].wakeup_ports[0].bits.uop.debug_inst connect slots_13.io.wakeup_ports[0].bits.uop.inst, issue_slots[13].wakeup_ports[0].bits.uop.inst connect slots_13.io.wakeup_ports[0].valid, issue_slots[13].wakeup_ports[0].valid connect slots_13.io.wakeup_ports[1].bits.rebusy, issue_slots[13].wakeup_ports[1].bits.rebusy connect slots_13.io.wakeup_ports[1].bits.speculative_mask, issue_slots[13].wakeup_ports[1].bits.speculative_mask connect slots_13.io.wakeup_ports[1].bits.bypassable, issue_slots[13].wakeup_ports[1].bits.bypassable connect slots_13.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[13].wakeup_ports[1].bits.uop.debug_tsrc connect slots_13.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[13].wakeup_ports[1].bits.uop.debug_fsrc connect slots_13.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[13].wakeup_ports[1].bits.uop.bp_xcpt_if connect slots_13.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[13].wakeup_ports[1].bits.uop.bp_debug_if connect slots_13.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[13].wakeup_ports[1].bits.uop.xcpt_ma_if connect slots_13.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[13].wakeup_ports[1].bits.uop.xcpt_ae_if connect slots_13.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[13].wakeup_ports[1].bits.uop.xcpt_pf_if connect slots_13.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[13].wakeup_ports[1].bits.uop.fp_typ connect slots_13.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[13].wakeup_ports[1].bits.uop.fp_rm connect slots_13.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[13].wakeup_ports[1].bits.uop.fp_val connect slots_13.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[13].wakeup_ports[1].bits.uop.fcn_op connect slots_13.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[13].wakeup_ports[1].bits.uop.fcn_dw connect slots_13.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[13].wakeup_ports[1].bits.uop.frs3_en connect slots_13.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[13].wakeup_ports[1].bits.uop.lrs2_rtype connect slots_13.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[13].wakeup_ports[1].bits.uop.lrs1_rtype connect slots_13.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[13].wakeup_ports[1].bits.uop.dst_rtype connect slots_13.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[13].wakeup_ports[1].bits.uop.lrs3 connect slots_13.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[13].wakeup_ports[1].bits.uop.lrs2 connect slots_13.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[13].wakeup_ports[1].bits.uop.lrs1 connect slots_13.io.wakeup_ports[1].bits.uop.ldst, issue_slots[13].wakeup_ports[1].bits.uop.ldst connect slots_13.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[13].wakeup_ports[1].bits.uop.ldst_is_rs1 connect slots_13.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[13].wakeup_ports[1].bits.uop.csr_cmd connect slots_13.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[13].wakeup_ports[1].bits.uop.flush_on_commit connect slots_13.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[13].wakeup_ports[1].bits.uop.is_unique connect slots_13.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[13].wakeup_ports[1].bits.uop.uses_stq connect slots_13.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[13].wakeup_ports[1].bits.uop.uses_ldq connect slots_13.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[13].wakeup_ports[1].bits.uop.mem_signed connect slots_13.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[13].wakeup_ports[1].bits.uop.mem_size connect slots_13.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[13].wakeup_ports[1].bits.uop.mem_cmd connect slots_13.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[13].wakeup_ports[1].bits.uop.exc_cause connect slots_13.io.wakeup_ports[1].bits.uop.exception, issue_slots[13].wakeup_ports[1].bits.uop.exception connect slots_13.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[13].wakeup_ports[1].bits.uop.stale_pdst connect slots_13.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[13].wakeup_ports[1].bits.uop.ppred_busy connect slots_13.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[13].wakeup_ports[1].bits.uop.prs3_busy connect slots_13.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[13].wakeup_ports[1].bits.uop.prs2_busy connect slots_13.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[13].wakeup_ports[1].bits.uop.prs1_busy connect slots_13.io.wakeup_ports[1].bits.uop.ppred, issue_slots[13].wakeup_ports[1].bits.uop.ppred connect slots_13.io.wakeup_ports[1].bits.uop.prs3, issue_slots[13].wakeup_ports[1].bits.uop.prs3 connect slots_13.io.wakeup_ports[1].bits.uop.prs2, issue_slots[13].wakeup_ports[1].bits.uop.prs2 connect slots_13.io.wakeup_ports[1].bits.uop.prs1, issue_slots[13].wakeup_ports[1].bits.uop.prs1 connect slots_13.io.wakeup_ports[1].bits.uop.pdst, issue_slots[13].wakeup_ports[1].bits.uop.pdst connect slots_13.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[13].wakeup_ports[1].bits.uop.rxq_idx connect slots_13.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[13].wakeup_ports[1].bits.uop.stq_idx connect slots_13.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[13].wakeup_ports[1].bits.uop.ldq_idx connect slots_13.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[13].wakeup_ports[1].bits.uop.rob_idx connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.vec connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.wflags connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.div connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.fma connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.toint connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.fromint connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.wen connect slots_13.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.ldst connect slots_13.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[13].wakeup_ports[1].bits.uop.op2_sel connect slots_13.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[13].wakeup_ports[1].bits.uop.op1_sel connect slots_13.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[13].wakeup_ports[1].bits.uop.imm_packed connect slots_13.io.wakeup_ports[1].bits.uop.pimm, issue_slots[13].wakeup_ports[1].bits.uop.pimm connect slots_13.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[13].wakeup_ports[1].bits.uop.imm_sel connect slots_13.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[13].wakeup_ports[1].bits.uop.imm_rename connect slots_13.io.wakeup_ports[1].bits.uop.taken, issue_slots[13].wakeup_ports[1].bits.uop.taken connect slots_13.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[13].wakeup_ports[1].bits.uop.pc_lob connect slots_13.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[13].wakeup_ports[1].bits.uop.edge_inst connect slots_13.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[13].wakeup_ports[1].bits.uop.ftq_idx connect slots_13.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[13].wakeup_ports[1].bits.uop.is_mov connect slots_13.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[13].wakeup_ports[1].bits.uop.is_rocc connect slots_13.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[13].wakeup_ports[1].bits.uop.is_sys_pc2epc connect slots_13.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[13].wakeup_ports[1].bits.uop.is_eret connect slots_13.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[13].wakeup_ports[1].bits.uop.is_amo connect slots_13.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[13].wakeup_ports[1].bits.uop.is_sfence connect slots_13.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[13].wakeup_ports[1].bits.uop.is_fencei connect slots_13.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[13].wakeup_ports[1].bits.uop.is_fence connect slots_13.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[13].wakeup_ports[1].bits.uop.is_sfb connect slots_13.io.wakeup_ports[1].bits.uop.br_type, issue_slots[13].wakeup_ports[1].bits.uop.br_type connect slots_13.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[13].wakeup_ports[1].bits.uop.br_tag connect slots_13.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[13].wakeup_ports[1].bits.uop.br_mask connect slots_13.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[13].wakeup_ports[1].bits.uop.dis_col_sel connect slots_13.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[13].wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect slots_13.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[13].wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect slots_13.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[13].wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect slots_13.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[13].wakeup_ports[1].bits.uop.iw_p2_speculative_child connect slots_13.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[13].wakeup_ports[1].bits.uop.iw_p1_speculative_child connect slots_13.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[13].wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect slots_13.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[13].wakeup_ports[1].bits.uop.iw_issued_partial_agen connect slots_13.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[13].wakeup_ports[1].bits.uop.iw_issued connect slots_13.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[13].wakeup_ports[1].bits.uop.fu_code[0] connect slots_13.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[13].wakeup_ports[1].bits.uop.fu_code[1] connect slots_13.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[13].wakeup_ports[1].bits.uop.fu_code[2] connect slots_13.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[13].wakeup_ports[1].bits.uop.fu_code[3] connect slots_13.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[13].wakeup_ports[1].bits.uop.fu_code[4] connect slots_13.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[13].wakeup_ports[1].bits.uop.fu_code[5] connect slots_13.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[13].wakeup_ports[1].bits.uop.fu_code[6] connect slots_13.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[13].wakeup_ports[1].bits.uop.fu_code[7] connect slots_13.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[13].wakeup_ports[1].bits.uop.fu_code[8] connect slots_13.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[13].wakeup_ports[1].bits.uop.fu_code[9] connect slots_13.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[13].wakeup_ports[1].bits.uop.iq_type[0] connect slots_13.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[13].wakeup_ports[1].bits.uop.iq_type[1] connect slots_13.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[13].wakeup_ports[1].bits.uop.iq_type[2] connect slots_13.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[13].wakeup_ports[1].bits.uop.iq_type[3] connect slots_13.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[13].wakeup_ports[1].bits.uop.debug_pc connect slots_13.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[13].wakeup_ports[1].bits.uop.is_rvc connect slots_13.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[13].wakeup_ports[1].bits.uop.debug_inst connect slots_13.io.wakeup_ports[1].bits.uop.inst, issue_slots[13].wakeup_ports[1].bits.uop.inst connect slots_13.io.wakeup_ports[1].valid, issue_slots[13].wakeup_ports[1].valid connect slots_13.io.wakeup_ports[2].bits.rebusy, issue_slots[13].wakeup_ports[2].bits.rebusy connect slots_13.io.wakeup_ports[2].bits.speculative_mask, issue_slots[13].wakeup_ports[2].bits.speculative_mask connect slots_13.io.wakeup_ports[2].bits.bypassable, issue_slots[13].wakeup_ports[2].bits.bypassable connect slots_13.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[13].wakeup_ports[2].bits.uop.debug_tsrc connect slots_13.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[13].wakeup_ports[2].bits.uop.debug_fsrc connect slots_13.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[13].wakeup_ports[2].bits.uop.bp_xcpt_if connect slots_13.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[13].wakeup_ports[2].bits.uop.bp_debug_if connect slots_13.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[13].wakeup_ports[2].bits.uop.xcpt_ma_if connect slots_13.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[13].wakeup_ports[2].bits.uop.xcpt_ae_if connect slots_13.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[13].wakeup_ports[2].bits.uop.xcpt_pf_if connect slots_13.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[13].wakeup_ports[2].bits.uop.fp_typ connect slots_13.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[13].wakeup_ports[2].bits.uop.fp_rm connect slots_13.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[13].wakeup_ports[2].bits.uop.fp_val connect slots_13.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[13].wakeup_ports[2].bits.uop.fcn_op connect slots_13.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[13].wakeup_ports[2].bits.uop.fcn_dw connect slots_13.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[13].wakeup_ports[2].bits.uop.frs3_en connect slots_13.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[13].wakeup_ports[2].bits.uop.lrs2_rtype connect slots_13.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[13].wakeup_ports[2].bits.uop.lrs1_rtype connect slots_13.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[13].wakeup_ports[2].bits.uop.dst_rtype connect slots_13.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[13].wakeup_ports[2].bits.uop.lrs3 connect slots_13.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[13].wakeup_ports[2].bits.uop.lrs2 connect slots_13.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[13].wakeup_ports[2].bits.uop.lrs1 connect slots_13.io.wakeup_ports[2].bits.uop.ldst, issue_slots[13].wakeup_ports[2].bits.uop.ldst connect slots_13.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[13].wakeup_ports[2].bits.uop.ldst_is_rs1 connect slots_13.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[13].wakeup_ports[2].bits.uop.csr_cmd connect slots_13.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[13].wakeup_ports[2].bits.uop.flush_on_commit connect slots_13.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[13].wakeup_ports[2].bits.uop.is_unique connect slots_13.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[13].wakeup_ports[2].bits.uop.uses_stq connect slots_13.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[13].wakeup_ports[2].bits.uop.uses_ldq connect slots_13.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[13].wakeup_ports[2].bits.uop.mem_signed connect slots_13.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[13].wakeup_ports[2].bits.uop.mem_size connect slots_13.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[13].wakeup_ports[2].bits.uop.mem_cmd connect slots_13.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[13].wakeup_ports[2].bits.uop.exc_cause connect slots_13.io.wakeup_ports[2].bits.uop.exception, issue_slots[13].wakeup_ports[2].bits.uop.exception connect slots_13.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[13].wakeup_ports[2].bits.uop.stale_pdst connect slots_13.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[13].wakeup_ports[2].bits.uop.ppred_busy connect slots_13.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[13].wakeup_ports[2].bits.uop.prs3_busy connect slots_13.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[13].wakeup_ports[2].bits.uop.prs2_busy connect slots_13.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[13].wakeup_ports[2].bits.uop.prs1_busy connect slots_13.io.wakeup_ports[2].bits.uop.ppred, issue_slots[13].wakeup_ports[2].bits.uop.ppred connect slots_13.io.wakeup_ports[2].bits.uop.prs3, issue_slots[13].wakeup_ports[2].bits.uop.prs3 connect slots_13.io.wakeup_ports[2].bits.uop.prs2, issue_slots[13].wakeup_ports[2].bits.uop.prs2 connect slots_13.io.wakeup_ports[2].bits.uop.prs1, issue_slots[13].wakeup_ports[2].bits.uop.prs1 connect slots_13.io.wakeup_ports[2].bits.uop.pdst, issue_slots[13].wakeup_ports[2].bits.uop.pdst connect slots_13.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[13].wakeup_ports[2].bits.uop.rxq_idx connect slots_13.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[13].wakeup_ports[2].bits.uop.stq_idx connect slots_13.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[13].wakeup_ports[2].bits.uop.ldq_idx connect slots_13.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[13].wakeup_ports[2].bits.uop.rob_idx connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.vec connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.wflags connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.div connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.fma connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.toint connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.fromint connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.wen connect slots_13.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.ldst connect slots_13.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[13].wakeup_ports[2].bits.uop.op2_sel connect slots_13.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[13].wakeup_ports[2].bits.uop.op1_sel connect slots_13.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[13].wakeup_ports[2].bits.uop.imm_packed connect slots_13.io.wakeup_ports[2].bits.uop.pimm, issue_slots[13].wakeup_ports[2].bits.uop.pimm connect slots_13.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[13].wakeup_ports[2].bits.uop.imm_sel connect slots_13.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[13].wakeup_ports[2].bits.uop.imm_rename connect slots_13.io.wakeup_ports[2].bits.uop.taken, issue_slots[13].wakeup_ports[2].bits.uop.taken connect slots_13.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[13].wakeup_ports[2].bits.uop.pc_lob connect slots_13.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[13].wakeup_ports[2].bits.uop.edge_inst connect slots_13.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[13].wakeup_ports[2].bits.uop.ftq_idx connect slots_13.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[13].wakeup_ports[2].bits.uop.is_mov connect slots_13.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[13].wakeup_ports[2].bits.uop.is_rocc connect slots_13.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[13].wakeup_ports[2].bits.uop.is_sys_pc2epc connect slots_13.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[13].wakeup_ports[2].bits.uop.is_eret connect slots_13.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[13].wakeup_ports[2].bits.uop.is_amo connect slots_13.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[13].wakeup_ports[2].bits.uop.is_sfence connect slots_13.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[13].wakeup_ports[2].bits.uop.is_fencei connect slots_13.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[13].wakeup_ports[2].bits.uop.is_fence connect slots_13.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[13].wakeup_ports[2].bits.uop.is_sfb connect slots_13.io.wakeup_ports[2].bits.uop.br_type, issue_slots[13].wakeup_ports[2].bits.uop.br_type connect slots_13.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[13].wakeup_ports[2].bits.uop.br_tag connect slots_13.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[13].wakeup_ports[2].bits.uop.br_mask connect slots_13.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[13].wakeup_ports[2].bits.uop.dis_col_sel connect slots_13.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[13].wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect slots_13.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[13].wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect slots_13.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[13].wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect slots_13.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[13].wakeup_ports[2].bits.uop.iw_p2_speculative_child connect slots_13.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[13].wakeup_ports[2].bits.uop.iw_p1_speculative_child connect slots_13.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[13].wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect slots_13.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[13].wakeup_ports[2].bits.uop.iw_issued_partial_agen connect slots_13.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[13].wakeup_ports[2].bits.uop.iw_issued connect slots_13.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[13].wakeup_ports[2].bits.uop.fu_code[0] connect slots_13.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[13].wakeup_ports[2].bits.uop.fu_code[1] connect slots_13.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[13].wakeup_ports[2].bits.uop.fu_code[2] connect slots_13.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[13].wakeup_ports[2].bits.uop.fu_code[3] connect slots_13.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[13].wakeup_ports[2].bits.uop.fu_code[4] connect slots_13.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[13].wakeup_ports[2].bits.uop.fu_code[5] connect slots_13.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[13].wakeup_ports[2].bits.uop.fu_code[6] connect slots_13.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[13].wakeup_ports[2].bits.uop.fu_code[7] connect slots_13.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[13].wakeup_ports[2].bits.uop.fu_code[8] connect slots_13.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[13].wakeup_ports[2].bits.uop.fu_code[9] connect slots_13.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[13].wakeup_ports[2].bits.uop.iq_type[0] connect slots_13.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[13].wakeup_ports[2].bits.uop.iq_type[1] connect slots_13.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[13].wakeup_ports[2].bits.uop.iq_type[2] connect slots_13.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[13].wakeup_ports[2].bits.uop.iq_type[3] connect slots_13.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[13].wakeup_ports[2].bits.uop.debug_pc connect slots_13.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[13].wakeup_ports[2].bits.uop.is_rvc connect slots_13.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[13].wakeup_ports[2].bits.uop.debug_inst connect slots_13.io.wakeup_ports[2].bits.uop.inst, issue_slots[13].wakeup_ports[2].bits.uop.inst connect slots_13.io.wakeup_ports[2].valid, issue_slots[13].wakeup_ports[2].valid connect slots_13.io.wakeup_ports[3].bits.rebusy, issue_slots[13].wakeup_ports[3].bits.rebusy connect slots_13.io.wakeup_ports[3].bits.speculative_mask, issue_slots[13].wakeup_ports[3].bits.speculative_mask connect slots_13.io.wakeup_ports[3].bits.bypassable, issue_slots[13].wakeup_ports[3].bits.bypassable connect slots_13.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[13].wakeup_ports[3].bits.uop.debug_tsrc connect slots_13.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[13].wakeup_ports[3].bits.uop.debug_fsrc connect slots_13.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[13].wakeup_ports[3].bits.uop.bp_xcpt_if connect slots_13.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[13].wakeup_ports[3].bits.uop.bp_debug_if connect slots_13.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[13].wakeup_ports[3].bits.uop.xcpt_ma_if connect slots_13.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[13].wakeup_ports[3].bits.uop.xcpt_ae_if connect slots_13.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[13].wakeup_ports[3].bits.uop.xcpt_pf_if connect slots_13.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[13].wakeup_ports[3].bits.uop.fp_typ connect slots_13.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[13].wakeup_ports[3].bits.uop.fp_rm connect slots_13.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[13].wakeup_ports[3].bits.uop.fp_val connect slots_13.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[13].wakeup_ports[3].bits.uop.fcn_op connect slots_13.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[13].wakeup_ports[3].bits.uop.fcn_dw connect slots_13.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[13].wakeup_ports[3].bits.uop.frs3_en connect slots_13.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[13].wakeup_ports[3].bits.uop.lrs2_rtype connect slots_13.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[13].wakeup_ports[3].bits.uop.lrs1_rtype connect slots_13.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[13].wakeup_ports[3].bits.uop.dst_rtype connect slots_13.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[13].wakeup_ports[3].bits.uop.lrs3 connect slots_13.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[13].wakeup_ports[3].bits.uop.lrs2 connect slots_13.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[13].wakeup_ports[3].bits.uop.lrs1 connect slots_13.io.wakeup_ports[3].bits.uop.ldst, issue_slots[13].wakeup_ports[3].bits.uop.ldst connect slots_13.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[13].wakeup_ports[3].bits.uop.ldst_is_rs1 connect slots_13.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[13].wakeup_ports[3].bits.uop.csr_cmd connect slots_13.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[13].wakeup_ports[3].bits.uop.flush_on_commit connect slots_13.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[13].wakeup_ports[3].bits.uop.is_unique connect slots_13.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[13].wakeup_ports[3].bits.uop.uses_stq connect slots_13.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[13].wakeup_ports[3].bits.uop.uses_ldq connect slots_13.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[13].wakeup_ports[3].bits.uop.mem_signed connect slots_13.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[13].wakeup_ports[3].bits.uop.mem_size connect slots_13.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[13].wakeup_ports[3].bits.uop.mem_cmd connect slots_13.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[13].wakeup_ports[3].bits.uop.exc_cause connect slots_13.io.wakeup_ports[3].bits.uop.exception, issue_slots[13].wakeup_ports[3].bits.uop.exception connect slots_13.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[13].wakeup_ports[3].bits.uop.stale_pdst connect slots_13.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[13].wakeup_ports[3].bits.uop.ppred_busy connect slots_13.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[13].wakeup_ports[3].bits.uop.prs3_busy connect slots_13.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[13].wakeup_ports[3].bits.uop.prs2_busy connect slots_13.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[13].wakeup_ports[3].bits.uop.prs1_busy connect slots_13.io.wakeup_ports[3].bits.uop.ppred, issue_slots[13].wakeup_ports[3].bits.uop.ppred connect slots_13.io.wakeup_ports[3].bits.uop.prs3, issue_slots[13].wakeup_ports[3].bits.uop.prs3 connect slots_13.io.wakeup_ports[3].bits.uop.prs2, issue_slots[13].wakeup_ports[3].bits.uop.prs2 connect slots_13.io.wakeup_ports[3].bits.uop.prs1, issue_slots[13].wakeup_ports[3].bits.uop.prs1 connect slots_13.io.wakeup_ports[3].bits.uop.pdst, issue_slots[13].wakeup_ports[3].bits.uop.pdst connect slots_13.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[13].wakeup_ports[3].bits.uop.rxq_idx connect slots_13.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[13].wakeup_ports[3].bits.uop.stq_idx connect slots_13.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[13].wakeup_ports[3].bits.uop.ldq_idx connect slots_13.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[13].wakeup_ports[3].bits.uop.rob_idx connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.vec connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.wflags connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.div connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.fma connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.toint connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.fromint connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.wen connect slots_13.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.ldst connect slots_13.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[13].wakeup_ports[3].bits.uop.op2_sel connect slots_13.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[13].wakeup_ports[3].bits.uop.op1_sel connect slots_13.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[13].wakeup_ports[3].bits.uop.imm_packed connect slots_13.io.wakeup_ports[3].bits.uop.pimm, issue_slots[13].wakeup_ports[3].bits.uop.pimm connect slots_13.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[13].wakeup_ports[3].bits.uop.imm_sel connect slots_13.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[13].wakeup_ports[3].bits.uop.imm_rename connect slots_13.io.wakeup_ports[3].bits.uop.taken, issue_slots[13].wakeup_ports[3].bits.uop.taken connect slots_13.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[13].wakeup_ports[3].bits.uop.pc_lob connect slots_13.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[13].wakeup_ports[3].bits.uop.edge_inst connect slots_13.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[13].wakeup_ports[3].bits.uop.ftq_idx connect slots_13.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[13].wakeup_ports[3].bits.uop.is_mov connect slots_13.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[13].wakeup_ports[3].bits.uop.is_rocc connect slots_13.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[13].wakeup_ports[3].bits.uop.is_sys_pc2epc connect slots_13.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[13].wakeup_ports[3].bits.uop.is_eret connect slots_13.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[13].wakeup_ports[3].bits.uop.is_amo connect slots_13.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[13].wakeup_ports[3].bits.uop.is_sfence connect slots_13.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[13].wakeup_ports[3].bits.uop.is_fencei connect slots_13.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[13].wakeup_ports[3].bits.uop.is_fence connect slots_13.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[13].wakeup_ports[3].bits.uop.is_sfb connect slots_13.io.wakeup_ports[3].bits.uop.br_type, issue_slots[13].wakeup_ports[3].bits.uop.br_type connect slots_13.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[13].wakeup_ports[3].bits.uop.br_tag connect slots_13.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[13].wakeup_ports[3].bits.uop.br_mask connect slots_13.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[13].wakeup_ports[3].bits.uop.dis_col_sel connect slots_13.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[13].wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect slots_13.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[13].wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect slots_13.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[13].wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect slots_13.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[13].wakeup_ports[3].bits.uop.iw_p2_speculative_child connect slots_13.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[13].wakeup_ports[3].bits.uop.iw_p1_speculative_child connect slots_13.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[13].wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect slots_13.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[13].wakeup_ports[3].bits.uop.iw_issued_partial_agen connect slots_13.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[13].wakeup_ports[3].bits.uop.iw_issued connect slots_13.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[13].wakeup_ports[3].bits.uop.fu_code[0] connect slots_13.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[13].wakeup_ports[3].bits.uop.fu_code[1] connect slots_13.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[13].wakeup_ports[3].bits.uop.fu_code[2] connect slots_13.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[13].wakeup_ports[3].bits.uop.fu_code[3] connect slots_13.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[13].wakeup_ports[3].bits.uop.fu_code[4] connect slots_13.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[13].wakeup_ports[3].bits.uop.fu_code[5] connect slots_13.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[13].wakeup_ports[3].bits.uop.fu_code[6] connect slots_13.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[13].wakeup_ports[3].bits.uop.fu_code[7] connect slots_13.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[13].wakeup_ports[3].bits.uop.fu_code[8] connect slots_13.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[13].wakeup_ports[3].bits.uop.fu_code[9] connect slots_13.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[13].wakeup_ports[3].bits.uop.iq_type[0] connect slots_13.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[13].wakeup_ports[3].bits.uop.iq_type[1] connect slots_13.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[13].wakeup_ports[3].bits.uop.iq_type[2] connect slots_13.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[13].wakeup_ports[3].bits.uop.iq_type[3] connect slots_13.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[13].wakeup_ports[3].bits.uop.debug_pc connect slots_13.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[13].wakeup_ports[3].bits.uop.is_rvc connect slots_13.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[13].wakeup_ports[3].bits.uop.debug_inst connect slots_13.io.wakeup_ports[3].bits.uop.inst, issue_slots[13].wakeup_ports[3].bits.uop.inst connect slots_13.io.wakeup_ports[3].valid, issue_slots[13].wakeup_ports[3].valid connect slots_13.io.wakeup_ports[4].bits.rebusy, issue_slots[13].wakeup_ports[4].bits.rebusy connect slots_13.io.wakeup_ports[4].bits.speculative_mask, issue_slots[13].wakeup_ports[4].bits.speculative_mask connect slots_13.io.wakeup_ports[4].bits.bypassable, issue_slots[13].wakeup_ports[4].bits.bypassable connect slots_13.io.wakeup_ports[4].bits.uop.debug_tsrc, issue_slots[13].wakeup_ports[4].bits.uop.debug_tsrc connect slots_13.io.wakeup_ports[4].bits.uop.debug_fsrc, issue_slots[13].wakeup_ports[4].bits.uop.debug_fsrc connect slots_13.io.wakeup_ports[4].bits.uop.bp_xcpt_if, issue_slots[13].wakeup_ports[4].bits.uop.bp_xcpt_if connect slots_13.io.wakeup_ports[4].bits.uop.bp_debug_if, issue_slots[13].wakeup_ports[4].bits.uop.bp_debug_if connect slots_13.io.wakeup_ports[4].bits.uop.xcpt_ma_if, issue_slots[13].wakeup_ports[4].bits.uop.xcpt_ma_if connect slots_13.io.wakeup_ports[4].bits.uop.xcpt_ae_if, issue_slots[13].wakeup_ports[4].bits.uop.xcpt_ae_if connect slots_13.io.wakeup_ports[4].bits.uop.xcpt_pf_if, issue_slots[13].wakeup_ports[4].bits.uop.xcpt_pf_if connect slots_13.io.wakeup_ports[4].bits.uop.fp_typ, issue_slots[13].wakeup_ports[4].bits.uop.fp_typ connect slots_13.io.wakeup_ports[4].bits.uop.fp_rm, issue_slots[13].wakeup_ports[4].bits.uop.fp_rm connect slots_13.io.wakeup_ports[4].bits.uop.fp_val, issue_slots[13].wakeup_ports[4].bits.uop.fp_val connect slots_13.io.wakeup_ports[4].bits.uop.fcn_op, issue_slots[13].wakeup_ports[4].bits.uop.fcn_op connect slots_13.io.wakeup_ports[4].bits.uop.fcn_dw, issue_slots[13].wakeup_ports[4].bits.uop.fcn_dw connect slots_13.io.wakeup_ports[4].bits.uop.frs3_en, issue_slots[13].wakeup_ports[4].bits.uop.frs3_en connect slots_13.io.wakeup_ports[4].bits.uop.lrs2_rtype, issue_slots[13].wakeup_ports[4].bits.uop.lrs2_rtype connect slots_13.io.wakeup_ports[4].bits.uop.lrs1_rtype, issue_slots[13].wakeup_ports[4].bits.uop.lrs1_rtype connect slots_13.io.wakeup_ports[4].bits.uop.dst_rtype, issue_slots[13].wakeup_ports[4].bits.uop.dst_rtype connect slots_13.io.wakeup_ports[4].bits.uop.lrs3, issue_slots[13].wakeup_ports[4].bits.uop.lrs3 connect slots_13.io.wakeup_ports[4].bits.uop.lrs2, issue_slots[13].wakeup_ports[4].bits.uop.lrs2 connect slots_13.io.wakeup_ports[4].bits.uop.lrs1, issue_slots[13].wakeup_ports[4].bits.uop.lrs1 connect slots_13.io.wakeup_ports[4].bits.uop.ldst, issue_slots[13].wakeup_ports[4].bits.uop.ldst connect slots_13.io.wakeup_ports[4].bits.uop.ldst_is_rs1, issue_slots[13].wakeup_ports[4].bits.uop.ldst_is_rs1 connect slots_13.io.wakeup_ports[4].bits.uop.csr_cmd, issue_slots[13].wakeup_ports[4].bits.uop.csr_cmd connect slots_13.io.wakeup_ports[4].bits.uop.flush_on_commit, issue_slots[13].wakeup_ports[4].bits.uop.flush_on_commit connect slots_13.io.wakeup_ports[4].bits.uop.is_unique, issue_slots[13].wakeup_ports[4].bits.uop.is_unique connect slots_13.io.wakeup_ports[4].bits.uop.uses_stq, issue_slots[13].wakeup_ports[4].bits.uop.uses_stq connect slots_13.io.wakeup_ports[4].bits.uop.uses_ldq, issue_slots[13].wakeup_ports[4].bits.uop.uses_ldq connect slots_13.io.wakeup_ports[4].bits.uop.mem_signed, issue_slots[13].wakeup_ports[4].bits.uop.mem_signed connect slots_13.io.wakeup_ports[4].bits.uop.mem_size, issue_slots[13].wakeup_ports[4].bits.uop.mem_size connect slots_13.io.wakeup_ports[4].bits.uop.mem_cmd, issue_slots[13].wakeup_ports[4].bits.uop.mem_cmd connect slots_13.io.wakeup_ports[4].bits.uop.exc_cause, issue_slots[13].wakeup_ports[4].bits.uop.exc_cause connect slots_13.io.wakeup_ports[4].bits.uop.exception, issue_slots[13].wakeup_ports[4].bits.uop.exception connect slots_13.io.wakeup_ports[4].bits.uop.stale_pdst, issue_slots[13].wakeup_ports[4].bits.uop.stale_pdst connect slots_13.io.wakeup_ports[4].bits.uop.ppred_busy, issue_slots[13].wakeup_ports[4].bits.uop.ppred_busy connect slots_13.io.wakeup_ports[4].bits.uop.prs3_busy, issue_slots[13].wakeup_ports[4].bits.uop.prs3_busy connect slots_13.io.wakeup_ports[4].bits.uop.prs2_busy, issue_slots[13].wakeup_ports[4].bits.uop.prs2_busy connect slots_13.io.wakeup_ports[4].bits.uop.prs1_busy, issue_slots[13].wakeup_ports[4].bits.uop.prs1_busy connect slots_13.io.wakeup_ports[4].bits.uop.ppred, issue_slots[13].wakeup_ports[4].bits.uop.ppred connect slots_13.io.wakeup_ports[4].bits.uop.prs3, issue_slots[13].wakeup_ports[4].bits.uop.prs3 connect slots_13.io.wakeup_ports[4].bits.uop.prs2, issue_slots[13].wakeup_ports[4].bits.uop.prs2 connect slots_13.io.wakeup_ports[4].bits.uop.prs1, issue_slots[13].wakeup_ports[4].bits.uop.prs1 connect slots_13.io.wakeup_ports[4].bits.uop.pdst, issue_slots[13].wakeup_ports[4].bits.uop.pdst connect slots_13.io.wakeup_ports[4].bits.uop.rxq_idx, issue_slots[13].wakeup_ports[4].bits.uop.rxq_idx connect slots_13.io.wakeup_ports[4].bits.uop.stq_idx, issue_slots[13].wakeup_ports[4].bits.uop.stq_idx connect slots_13.io.wakeup_ports[4].bits.uop.ldq_idx, issue_slots[13].wakeup_ports[4].bits.uop.ldq_idx connect slots_13.io.wakeup_ports[4].bits.uop.rob_idx, issue_slots[13].wakeup_ports[4].bits.uop.rob_idx connect slots_13.io.wakeup_ports[4].bits.uop.fp_ctrl.vec, issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.vec connect slots_13.io.wakeup_ports[4].bits.uop.fp_ctrl.wflags, issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.wflags connect slots_13.io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt, issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect slots_13.io.wakeup_ports[4].bits.uop.fp_ctrl.div, issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.div connect slots_13.io.wakeup_ports[4].bits.uop.fp_ctrl.fma, issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.fma connect slots_13.io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect slots_13.io.wakeup_ports[4].bits.uop.fp_ctrl.toint, issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.toint connect slots_13.io.wakeup_ports[4].bits.uop.fp_ctrl.fromint, issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.fromint connect slots_13.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect slots_13.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect slots_13.io.wakeup_ports[4].bits.uop.fp_ctrl.swap23, issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect slots_13.io.wakeup_ports[4].bits.uop.fp_ctrl.swap12, issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect slots_13.io.wakeup_ports[4].bits.uop.fp_ctrl.ren3, issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect slots_13.io.wakeup_ports[4].bits.uop.fp_ctrl.ren2, issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect slots_13.io.wakeup_ports[4].bits.uop.fp_ctrl.ren1, issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect slots_13.io.wakeup_ports[4].bits.uop.fp_ctrl.wen, issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.wen connect slots_13.io.wakeup_ports[4].bits.uop.fp_ctrl.ldst, issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.ldst connect slots_13.io.wakeup_ports[4].bits.uop.op2_sel, issue_slots[13].wakeup_ports[4].bits.uop.op2_sel connect slots_13.io.wakeup_ports[4].bits.uop.op1_sel, issue_slots[13].wakeup_ports[4].bits.uop.op1_sel connect slots_13.io.wakeup_ports[4].bits.uop.imm_packed, issue_slots[13].wakeup_ports[4].bits.uop.imm_packed connect slots_13.io.wakeup_ports[4].bits.uop.pimm, issue_slots[13].wakeup_ports[4].bits.uop.pimm connect slots_13.io.wakeup_ports[4].bits.uop.imm_sel, issue_slots[13].wakeup_ports[4].bits.uop.imm_sel connect slots_13.io.wakeup_ports[4].bits.uop.imm_rename, issue_slots[13].wakeup_ports[4].bits.uop.imm_rename connect slots_13.io.wakeup_ports[4].bits.uop.taken, issue_slots[13].wakeup_ports[4].bits.uop.taken connect slots_13.io.wakeup_ports[4].bits.uop.pc_lob, issue_slots[13].wakeup_ports[4].bits.uop.pc_lob connect slots_13.io.wakeup_ports[4].bits.uop.edge_inst, issue_slots[13].wakeup_ports[4].bits.uop.edge_inst connect slots_13.io.wakeup_ports[4].bits.uop.ftq_idx, issue_slots[13].wakeup_ports[4].bits.uop.ftq_idx connect slots_13.io.wakeup_ports[4].bits.uop.is_mov, issue_slots[13].wakeup_ports[4].bits.uop.is_mov connect slots_13.io.wakeup_ports[4].bits.uop.is_rocc, issue_slots[13].wakeup_ports[4].bits.uop.is_rocc connect slots_13.io.wakeup_ports[4].bits.uop.is_sys_pc2epc, issue_slots[13].wakeup_ports[4].bits.uop.is_sys_pc2epc connect slots_13.io.wakeup_ports[4].bits.uop.is_eret, issue_slots[13].wakeup_ports[4].bits.uop.is_eret connect slots_13.io.wakeup_ports[4].bits.uop.is_amo, issue_slots[13].wakeup_ports[4].bits.uop.is_amo connect slots_13.io.wakeup_ports[4].bits.uop.is_sfence, issue_slots[13].wakeup_ports[4].bits.uop.is_sfence connect slots_13.io.wakeup_ports[4].bits.uop.is_fencei, issue_slots[13].wakeup_ports[4].bits.uop.is_fencei connect slots_13.io.wakeup_ports[4].bits.uop.is_fence, issue_slots[13].wakeup_ports[4].bits.uop.is_fence connect slots_13.io.wakeup_ports[4].bits.uop.is_sfb, issue_slots[13].wakeup_ports[4].bits.uop.is_sfb connect slots_13.io.wakeup_ports[4].bits.uop.br_type, issue_slots[13].wakeup_ports[4].bits.uop.br_type connect slots_13.io.wakeup_ports[4].bits.uop.br_tag, issue_slots[13].wakeup_ports[4].bits.uop.br_tag connect slots_13.io.wakeup_ports[4].bits.uop.br_mask, issue_slots[13].wakeup_ports[4].bits.uop.br_mask connect slots_13.io.wakeup_ports[4].bits.uop.dis_col_sel, issue_slots[13].wakeup_ports[4].bits.uop.dis_col_sel connect slots_13.io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint, issue_slots[13].wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect slots_13.io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint, issue_slots[13].wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect slots_13.io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint, issue_slots[13].wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect slots_13.io.wakeup_ports[4].bits.uop.iw_p2_speculative_child, issue_slots[13].wakeup_ports[4].bits.uop.iw_p2_speculative_child connect slots_13.io.wakeup_ports[4].bits.uop.iw_p1_speculative_child, issue_slots[13].wakeup_ports[4].bits.uop.iw_p1_speculative_child connect slots_13.io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen, issue_slots[13].wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect slots_13.io.wakeup_ports[4].bits.uop.iw_issued_partial_agen, issue_slots[13].wakeup_ports[4].bits.uop.iw_issued_partial_agen connect slots_13.io.wakeup_ports[4].bits.uop.iw_issued, issue_slots[13].wakeup_ports[4].bits.uop.iw_issued connect slots_13.io.wakeup_ports[4].bits.uop.fu_code[0], issue_slots[13].wakeup_ports[4].bits.uop.fu_code[0] connect slots_13.io.wakeup_ports[4].bits.uop.fu_code[1], issue_slots[13].wakeup_ports[4].bits.uop.fu_code[1] connect slots_13.io.wakeup_ports[4].bits.uop.fu_code[2], issue_slots[13].wakeup_ports[4].bits.uop.fu_code[2] connect slots_13.io.wakeup_ports[4].bits.uop.fu_code[3], issue_slots[13].wakeup_ports[4].bits.uop.fu_code[3] connect slots_13.io.wakeup_ports[4].bits.uop.fu_code[4], issue_slots[13].wakeup_ports[4].bits.uop.fu_code[4] connect slots_13.io.wakeup_ports[4].bits.uop.fu_code[5], issue_slots[13].wakeup_ports[4].bits.uop.fu_code[5] connect slots_13.io.wakeup_ports[4].bits.uop.fu_code[6], issue_slots[13].wakeup_ports[4].bits.uop.fu_code[6] connect slots_13.io.wakeup_ports[4].bits.uop.fu_code[7], issue_slots[13].wakeup_ports[4].bits.uop.fu_code[7] connect slots_13.io.wakeup_ports[4].bits.uop.fu_code[8], issue_slots[13].wakeup_ports[4].bits.uop.fu_code[8] connect slots_13.io.wakeup_ports[4].bits.uop.fu_code[9], issue_slots[13].wakeup_ports[4].bits.uop.fu_code[9] connect slots_13.io.wakeup_ports[4].bits.uop.iq_type[0], issue_slots[13].wakeup_ports[4].bits.uop.iq_type[0] connect slots_13.io.wakeup_ports[4].bits.uop.iq_type[1], issue_slots[13].wakeup_ports[4].bits.uop.iq_type[1] connect slots_13.io.wakeup_ports[4].bits.uop.iq_type[2], issue_slots[13].wakeup_ports[4].bits.uop.iq_type[2] connect slots_13.io.wakeup_ports[4].bits.uop.iq_type[3], issue_slots[13].wakeup_ports[4].bits.uop.iq_type[3] connect slots_13.io.wakeup_ports[4].bits.uop.debug_pc, issue_slots[13].wakeup_ports[4].bits.uop.debug_pc connect slots_13.io.wakeup_ports[4].bits.uop.is_rvc, issue_slots[13].wakeup_ports[4].bits.uop.is_rvc connect slots_13.io.wakeup_ports[4].bits.uop.debug_inst, issue_slots[13].wakeup_ports[4].bits.uop.debug_inst connect slots_13.io.wakeup_ports[4].bits.uop.inst, issue_slots[13].wakeup_ports[4].bits.uop.inst connect slots_13.io.wakeup_ports[4].valid, issue_slots[13].wakeup_ports[4].valid connect slots_13.io.squash_grant, issue_slots[13].squash_grant connect slots_13.io.clear, issue_slots[13].clear connect slots_13.io.kill, issue_slots[13].kill connect slots_13.io.brupdate.b2.target_offset, issue_slots[13].brupdate.b2.target_offset connect slots_13.io.brupdate.b2.jalr_target, issue_slots[13].brupdate.b2.jalr_target connect slots_13.io.brupdate.b2.pc_sel, issue_slots[13].brupdate.b2.pc_sel connect slots_13.io.brupdate.b2.cfi_type, issue_slots[13].brupdate.b2.cfi_type connect slots_13.io.brupdate.b2.taken, issue_slots[13].brupdate.b2.taken connect slots_13.io.brupdate.b2.mispredict, issue_slots[13].brupdate.b2.mispredict connect slots_13.io.brupdate.b2.uop.debug_tsrc, issue_slots[13].brupdate.b2.uop.debug_tsrc connect slots_13.io.brupdate.b2.uop.debug_fsrc, issue_slots[13].brupdate.b2.uop.debug_fsrc connect slots_13.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[13].brupdate.b2.uop.bp_xcpt_if connect slots_13.io.brupdate.b2.uop.bp_debug_if, issue_slots[13].brupdate.b2.uop.bp_debug_if connect slots_13.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[13].brupdate.b2.uop.xcpt_ma_if connect slots_13.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[13].brupdate.b2.uop.xcpt_ae_if connect slots_13.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[13].brupdate.b2.uop.xcpt_pf_if connect slots_13.io.brupdate.b2.uop.fp_typ, issue_slots[13].brupdate.b2.uop.fp_typ connect slots_13.io.brupdate.b2.uop.fp_rm, issue_slots[13].brupdate.b2.uop.fp_rm connect slots_13.io.brupdate.b2.uop.fp_val, issue_slots[13].brupdate.b2.uop.fp_val connect slots_13.io.brupdate.b2.uop.fcn_op, issue_slots[13].brupdate.b2.uop.fcn_op connect slots_13.io.brupdate.b2.uop.fcn_dw, issue_slots[13].brupdate.b2.uop.fcn_dw connect slots_13.io.brupdate.b2.uop.frs3_en, issue_slots[13].brupdate.b2.uop.frs3_en connect slots_13.io.brupdate.b2.uop.lrs2_rtype, issue_slots[13].brupdate.b2.uop.lrs2_rtype connect slots_13.io.brupdate.b2.uop.lrs1_rtype, issue_slots[13].brupdate.b2.uop.lrs1_rtype connect slots_13.io.brupdate.b2.uop.dst_rtype, issue_slots[13].brupdate.b2.uop.dst_rtype connect slots_13.io.brupdate.b2.uop.lrs3, issue_slots[13].brupdate.b2.uop.lrs3 connect slots_13.io.brupdate.b2.uop.lrs2, issue_slots[13].brupdate.b2.uop.lrs2 connect slots_13.io.brupdate.b2.uop.lrs1, issue_slots[13].brupdate.b2.uop.lrs1 connect slots_13.io.brupdate.b2.uop.ldst, issue_slots[13].brupdate.b2.uop.ldst connect slots_13.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[13].brupdate.b2.uop.ldst_is_rs1 connect slots_13.io.brupdate.b2.uop.csr_cmd, issue_slots[13].brupdate.b2.uop.csr_cmd connect slots_13.io.brupdate.b2.uop.flush_on_commit, issue_slots[13].brupdate.b2.uop.flush_on_commit connect slots_13.io.brupdate.b2.uop.is_unique, issue_slots[13].brupdate.b2.uop.is_unique connect slots_13.io.brupdate.b2.uop.uses_stq, issue_slots[13].brupdate.b2.uop.uses_stq connect slots_13.io.brupdate.b2.uop.uses_ldq, issue_slots[13].brupdate.b2.uop.uses_ldq connect slots_13.io.brupdate.b2.uop.mem_signed, issue_slots[13].brupdate.b2.uop.mem_signed connect slots_13.io.brupdate.b2.uop.mem_size, issue_slots[13].brupdate.b2.uop.mem_size connect slots_13.io.brupdate.b2.uop.mem_cmd, issue_slots[13].brupdate.b2.uop.mem_cmd connect slots_13.io.brupdate.b2.uop.exc_cause, issue_slots[13].brupdate.b2.uop.exc_cause connect slots_13.io.brupdate.b2.uop.exception, issue_slots[13].brupdate.b2.uop.exception connect slots_13.io.brupdate.b2.uop.stale_pdst, issue_slots[13].brupdate.b2.uop.stale_pdst connect slots_13.io.brupdate.b2.uop.ppred_busy, issue_slots[13].brupdate.b2.uop.ppred_busy connect slots_13.io.brupdate.b2.uop.prs3_busy, issue_slots[13].brupdate.b2.uop.prs3_busy connect slots_13.io.brupdate.b2.uop.prs2_busy, issue_slots[13].brupdate.b2.uop.prs2_busy connect slots_13.io.brupdate.b2.uop.prs1_busy, issue_slots[13].brupdate.b2.uop.prs1_busy connect slots_13.io.brupdate.b2.uop.ppred, issue_slots[13].brupdate.b2.uop.ppred connect slots_13.io.brupdate.b2.uop.prs3, issue_slots[13].brupdate.b2.uop.prs3 connect slots_13.io.brupdate.b2.uop.prs2, issue_slots[13].brupdate.b2.uop.prs2 connect slots_13.io.brupdate.b2.uop.prs1, issue_slots[13].brupdate.b2.uop.prs1 connect slots_13.io.brupdate.b2.uop.pdst, issue_slots[13].brupdate.b2.uop.pdst connect slots_13.io.brupdate.b2.uop.rxq_idx, issue_slots[13].brupdate.b2.uop.rxq_idx connect slots_13.io.brupdate.b2.uop.stq_idx, issue_slots[13].brupdate.b2.uop.stq_idx connect slots_13.io.brupdate.b2.uop.ldq_idx, issue_slots[13].brupdate.b2.uop.ldq_idx connect slots_13.io.brupdate.b2.uop.rob_idx, issue_slots[13].brupdate.b2.uop.rob_idx connect slots_13.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[13].brupdate.b2.uop.fp_ctrl.vec connect slots_13.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[13].brupdate.b2.uop.fp_ctrl.wflags connect slots_13.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[13].brupdate.b2.uop.fp_ctrl.sqrt connect slots_13.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[13].brupdate.b2.uop.fp_ctrl.div connect slots_13.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[13].brupdate.b2.uop.fp_ctrl.fma connect slots_13.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[13].brupdate.b2.uop.fp_ctrl.fastpipe connect slots_13.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[13].brupdate.b2.uop.fp_ctrl.toint connect slots_13.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[13].brupdate.b2.uop.fp_ctrl.fromint connect slots_13.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[13].brupdate.b2.uop.fp_ctrl.typeTagOut connect slots_13.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[13].brupdate.b2.uop.fp_ctrl.typeTagIn connect slots_13.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[13].brupdate.b2.uop.fp_ctrl.swap23 connect slots_13.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[13].brupdate.b2.uop.fp_ctrl.swap12 connect slots_13.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[13].brupdate.b2.uop.fp_ctrl.ren3 connect slots_13.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[13].brupdate.b2.uop.fp_ctrl.ren2 connect slots_13.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[13].brupdate.b2.uop.fp_ctrl.ren1 connect slots_13.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[13].brupdate.b2.uop.fp_ctrl.wen connect slots_13.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[13].brupdate.b2.uop.fp_ctrl.ldst connect slots_13.io.brupdate.b2.uop.op2_sel, issue_slots[13].brupdate.b2.uop.op2_sel connect slots_13.io.brupdate.b2.uop.op1_sel, issue_slots[13].brupdate.b2.uop.op1_sel connect slots_13.io.brupdate.b2.uop.imm_packed, issue_slots[13].brupdate.b2.uop.imm_packed connect slots_13.io.brupdate.b2.uop.pimm, issue_slots[13].brupdate.b2.uop.pimm connect slots_13.io.brupdate.b2.uop.imm_sel, issue_slots[13].brupdate.b2.uop.imm_sel connect slots_13.io.brupdate.b2.uop.imm_rename, issue_slots[13].brupdate.b2.uop.imm_rename connect slots_13.io.brupdate.b2.uop.taken, issue_slots[13].brupdate.b2.uop.taken connect slots_13.io.brupdate.b2.uop.pc_lob, issue_slots[13].brupdate.b2.uop.pc_lob connect slots_13.io.brupdate.b2.uop.edge_inst, issue_slots[13].brupdate.b2.uop.edge_inst connect slots_13.io.brupdate.b2.uop.ftq_idx, issue_slots[13].brupdate.b2.uop.ftq_idx connect slots_13.io.brupdate.b2.uop.is_mov, issue_slots[13].brupdate.b2.uop.is_mov connect slots_13.io.brupdate.b2.uop.is_rocc, issue_slots[13].brupdate.b2.uop.is_rocc connect slots_13.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[13].brupdate.b2.uop.is_sys_pc2epc connect slots_13.io.brupdate.b2.uop.is_eret, issue_slots[13].brupdate.b2.uop.is_eret connect slots_13.io.brupdate.b2.uop.is_amo, issue_slots[13].brupdate.b2.uop.is_amo connect slots_13.io.brupdate.b2.uop.is_sfence, issue_slots[13].brupdate.b2.uop.is_sfence connect slots_13.io.brupdate.b2.uop.is_fencei, issue_slots[13].brupdate.b2.uop.is_fencei connect slots_13.io.brupdate.b2.uop.is_fence, issue_slots[13].brupdate.b2.uop.is_fence connect slots_13.io.brupdate.b2.uop.is_sfb, issue_slots[13].brupdate.b2.uop.is_sfb connect slots_13.io.brupdate.b2.uop.br_type, issue_slots[13].brupdate.b2.uop.br_type connect slots_13.io.brupdate.b2.uop.br_tag, issue_slots[13].brupdate.b2.uop.br_tag connect slots_13.io.brupdate.b2.uop.br_mask, issue_slots[13].brupdate.b2.uop.br_mask connect slots_13.io.brupdate.b2.uop.dis_col_sel, issue_slots[13].brupdate.b2.uop.dis_col_sel connect slots_13.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[13].brupdate.b2.uop.iw_p3_bypass_hint connect slots_13.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[13].brupdate.b2.uop.iw_p2_bypass_hint connect slots_13.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[13].brupdate.b2.uop.iw_p1_bypass_hint connect slots_13.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[13].brupdate.b2.uop.iw_p2_speculative_child connect slots_13.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[13].brupdate.b2.uop.iw_p1_speculative_child connect slots_13.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[13].brupdate.b2.uop.iw_issued_partial_dgen connect slots_13.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[13].brupdate.b2.uop.iw_issued_partial_agen connect slots_13.io.brupdate.b2.uop.iw_issued, issue_slots[13].brupdate.b2.uop.iw_issued connect slots_13.io.brupdate.b2.uop.fu_code[0], issue_slots[13].brupdate.b2.uop.fu_code[0] connect slots_13.io.brupdate.b2.uop.fu_code[1], issue_slots[13].brupdate.b2.uop.fu_code[1] connect slots_13.io.brupdate.b2.uop.fu_code[2], issue_slots[13].brupdate.b2.uop.fu_code[2] connect slots_13.io.brupdate.b2.uop.fu_code[3], issue_slots[13].brupdate.b2.uop.fu_code[3] connect slots_13.io.brupdate.b2.uop.fu_code[4], issue_slots[13].brupdate.b2.uop.fu_code[4] connect slots_13.io.brupdate.b2.uop.fu_code[5], issue_slots[13].brupdate.b2.uop.fu_code[5] connect slots_13.io.brupdate.b2.uop.fu_code[6], issue_slots[13].brupdate.b2.uop.fu_code[6] connect slots_13.io.brupdate.b2.uop.fu_code[7], issue_slots[13].brupdate.b2.uop.fu_code[7] connect slots_13.io.brupdate.b2.uop.fu_code[8], issue_slots[13].brupdate.b2.uop.fu_code[8] connect slots_13.io.brupdate.b2.uop.fu_code[9], issue_slots[13].brupdate.b2.uop.fu_code[9] connect slots_13.io.brupdate.b2.uop.iq_type[0], issue_slots[13].brupdate.b2.uop.iq_type[0] connect slots_13.io.brupdate.b2.uop.iq_type[1], issue_slots[13].brupdate.b2.uop.iq_type[1] connect slots_13.io.brupdate.b2.uop.iq_type[2], issue_slots[13].brupdate.b2.uop.iq_type[2] connect slots_13.io.brupdate.b2.uop.iq_type[3], issue_slots[13].brupdate.b2.uop.iq_type[3] connect slots_13.io.brupdate.b2.uop.debug_pc, issue_slots[13].brupdate.b2.uop.debug_pc connect slots_13.io.brupdate.b2.uop.is_rvc, issue_slots[13].brupdate.b2.uop.is_rvc connect slots_13.io.brupdate.b2.uop.debug_inst, issue_slots[13].brupdate.b2.uop.debug_inst connect slots_13.io.brupdate.b2.uop.inst, issue_slots[13].brupdate.b2.uop.inst connect slots_13.io.brupdate.b1.mispredict_mask, issue_slots[13].brupdate.b1.mispredict_mask connect slots_13.io.brupdate.b1.resolve_mask, issue_slots[13].brupdate.b1.resolve_mask connect issue_slots[13].out_uop.debug_tsrc, slots_13.io.out_uop.debug_tsrc connect issue_slots[13].out_uop.debug_fsrc, slots_13.io.out_uop.debug_fsrc connect issue_slots[13].out_uop.bp_xcpt_if, slots_13.io.out_uop.bp_xcpt_if connect issue_slots[13].out_uop.bp_debug_if, slots_13.io.out_uop.bp_debug_if connect issue_slots[13].out_uop.xcpt_ma_if, slots_13.io.out_uop.xcpt_ma_if connect issue_slots[13].out_uop.xcpt_ae_if, slots_13.io.out_uop.xcpt_ae_if connect issue_slots[13].out_uop.xcpt_pf_if, slots_13.io.out_uop.xcpt_pf_if connect issue_slots[13].out_uop.fp_typ, slots_13.io.out_uop.fp_typ connect issue_slots[13].out_uop.fp_rm, slots_13.io.out_uop.fp_rm connect issue_slots[13].out_uop.fp_val, slots_13.io.out_uop.fp_val connect issue_slots[13].out_uop.fcn_op, slots_13.io.out_uop.fcn_op connect issue_slots[13].out_uop.fcn_dw, slots_13.io.out_uop.fcn_dw connect issue_slots[13].out_uop.frs3_en, slots_13.io.out_uop.frs3_en connect issue_slots[13].out_uop.lrs2_rtype, slots_13.io.out_uop.lrs2_rtype connect issue_slots[13].out_uop.lrs1_rtype, slots_13.io.out_uop.lrs1_rtype connect issue_slots[13].out_uop.dst_rtype, slots_13.io.out_uop.dst_rtype connect issue_slots[13].out_uop.lrs3, slots_13.io.out_uop.lrs3 connect issue_slots[13].out_uop.lrs2, slots_13.io.out_uop.lrs2 connect issue_slots[13].out_uop.lrs1, slots_13.io.out_uop.lrs1 connect issue_slots[13].out_uop.ldst, slots_13.io.out_uop.ldst connect issue_slots[13].out_uop.ldst_is_rs1, slots_13.io.out_uop.ldst_is_rs1 connect issue_slots[13].out_uop.csr_cmd, slots_13.io.out_uop.csr_cmd connect issue_slots[13].out_uop.flush_on_commit, slots_13.io.out_uop.flush_on_commit connect issue_slots[13].out_uop.is_unique, slots_13.io.out_uop.is_unique connect issue_slots[13].out_uop.uses_stq, slots_13.io.out_uop.uses_stq connect issue_slots[13].out_uop.uses_ldq, slots_13.io.out_uop.uses_ldq connect issue_slots[13].out_uop.mem_signed, slots_13.io.out_uop.mem_signed connect issue_slots[13].out_uop.mem_size, slots_13.io.out_uop.mem_size connect issue_slots[13].out_uop.mem_cmd, slots_13.io.out_uop.mem_cmd connect issue_slots[13].out_uop.exc_cause, slots_13.io.out_uop.exc_cause connect issue_slots[13].out_uop.exception, slots_13.io.out_uop.exception connect issue_slots[13].out_uop.stale_pdst, slots_13.io.out_uop.stale_pdst connect issue_slots[13].out_uop.ppred_busy, slots_13.io.out_uop.ppred_busy connect issue_slots[13].out_uop.prs3_busy, slots_13.io.out_uop.prs3_busy connect issue_slots[13].out_uop.prs2_busy, slots_13.io.out_uop.prs2_busy connect issue_slots[13].out_uop.prs1_busy, slots_13.io.out_uop.prs1_busy connect issue_slots[13].out_uop.ppred, slots_13.io.out_uop.ppred connect issue_slots[13].out_uop.prs3, slots_13.io.out_uop.prs3 connect issue_slots[13].out_uop.prs2, slots_13.io.out_uop.prs2 connect issue_slots[13].out_uop.prs1, slots_13.io.out_uop.prs1 connect issue_slots[13].out_uop.pdst, slots_13.io.out_uop.pdst connect issue_slots[13].out_uop.rxq_idx, slots_13.io.out_uop.rxq_idx connect issue_slots[13].out_uop.stq_idx, slots_13.io.out_uop.stq_idx connect issue_slots[13].out_uop.ldq_idx, slots_13.io.out_uop.ldq_idx connect issue_slots[13].out_uop.rob_idx, slots_13.io.out_uop.rob_idx connect issue_slots[13].out_uop.fp_ctrl.vec, slots_13.io.out_uop.fp_ctrl.vec connect issue_slots[13].out_uop.fp_ctrl.wflags, slots_13.io.out_uop.fp_ctrl.wflags connect issue_slots[13].out_uop.fp_ctrl.sqrt, slots_13.io.out_uop.fp_ctrl.sqrt connect issue_slots[13].out_uop.fp_ctrl.div, slots_13.io.out_uop.fp_ctrl.div connect issue_slots[13].out_uop.fp_ctrl.fma, slots_13.io.out_uop.fp_ctrl.fma connect issue_slots[13].out_uop.fp_ctrl.fastpipe, slots_13.io.out_uop.fp_ctrl.fastpipe connect issue_slots[13].out_uop.fp_ctrl.toint, slots_13.io.out_uop.fp_ctrl.toint connect issue_slots[13].out_uop.fp_ctrl.fromint, slots_13.io.out_uop.fp_ctrl.fromint connect issue_slots[13].out_uop.fp_ctrl.typeTagOut, slots_13.io.out_uop.fp_ctrl.typeTagOut connect issue_slots[13].out_uop.fp_ctrl.typeTagIn, slots_13.io.out_uop.fp_ctrl.typeTagIn connect issue_slots[13].out_uop.fp_ctrl.swap23, slots_13.io.out_uop.fp_ctrl.swap23 connect issue_slots[13].out_uop.fp_ctrl.swap12, slots_13.io.out_uop.fp_ctrl.swap12 connect issue_slots[13].out_uop.fp_ctrl.ren3, slots_13.io.out_uop.fp_ctrl.ren3 connect issue_slots[13].out_uop.fp_ctrl.ren2, slots_13.io.out_uop.fp_ctrl.ren2 connect issue_slots[13].out_uop.fp_ctrl.ren1, slots_13.io.out_uop.fp_ctrl.ren1 connect issue_slots[13].out_uop.fp_ctrl.wen, slots_13.io.out_uop.fp_ctrl.wen connect issue_slots[13].out_uop.fp_ctrl.ldst, slots_13.io.out_uop.fp_ctrl.ldst connect issue_slots[13].out_uop.op2_sel, slots_13.io.out_uop.op2_sel connect issue_slots[13].out_uop.op1_sel, slots_13.io.out_uop.op1_sel connect issue_slots[13].out_uop.imm_packed, slots_13.io.out_uop.imm_packed connect issue_slots[13].out_uop.pimm, slots_13.io.out_uop.pimm connect issue_slots[13].out_uop.imm_sel, slots_13.io.out_uop.imm_sel connect issue_slots[13].out_uop.imm_rename, slots_13.io.out_uop.imm_rename connect issue_slots[13].out_uop.taken, slots_13.io.out_uop.taken connect issue_slots[13].out_uop.pc_lob, slots_13.io.out_uop.pc_lob connect issue_slots[13].out_uop.edge_inst, slots_13.io.out_uop.edge_inst connect issue_slots[13].out_uop.ftq_idx, slots_13.io.out_uop.ftq_idx connect issue_slots[13].out_uop.is_mov, slots_13.io.out_uop.is_mov connect issue_slots[13].out_uop.is_rocc, slots_13.io.out_uop.is_rocc connect issue_slots[13].out_uop.is_sys_pc2epc, slots_13.io.out_uop.is_sys_pc2epc connect issue_slots[13].out_uop.is_eret, slots_13.io.out_uop.is_eret connect issue_slots[13].out_uop.is_amo, slots_13.io.out_uop.is_amo connect issue_slots[13].out_uop.is_sfence, slots_13.io.out_uop.is_sfence connect issue_slots[13].out_uop.is_fencei, slots_13.io.out_uop.is_fencei connect issue_slots[13].out_uop.is_fence, slots_13.io.out_uop.is_fence connect issue_slots[13].out_uop.is_sfb, slots_13.io.out_uop.is_sfb connect issue_slots[13].out_uop.br_type, slots_13.io.out_uop.br_type connect issue_slots[13].out_uop.br_tag, slots_13.io.out_uop.br_tag connect issue_slots[13].out_uop.br_mask, slots_13.io.out_uop.br_mask connect issue_slots[13].out_uop.dis_col_sel, slots_13.io.out_uop.dis_col_sel connect issue_slots[13].out_uop.iw_p3_bypass_hint, slots_13.io.out_uop.iw_p3_bypass_hint connect issue_slots[13].out_uop.iw_p2_bypass_hint, slots_13.io.out_uop.iw_p2_bypass_hint connect issue_slots[13].out_uop.iw_p1_bypass_hint, slots_13.io.out_uop.iw_p1_bypass_hint connect issue_slots[13].out_uop.iw_p2_speculative_child, slots_13.io.out_uop.iw_p2_speculative_child connect issue_slots[13].out_uop.iw_p1_speculative_child, slots_13.io.out_uop.iw_p1_speculative_child connect issue_slots[13].out_uop.iw_issued_partial_dgen, slots_13.io.out_uop.iw_issued_partial_dgen connect issue_slots[13].out_uop.iw_issued_partial_agen, slots_13.io.out_uop.iw_issued_partial_agen connect issue_slots[13].out_uop.iw_issued, slots_13.io.out_uop.iw_issued connect issue_slots[13].out_uop.fu_code[0], slots_13.io.out_uop.fu_code[0] connect issue_slots[13].out_uop.fu_code[1], slots_13.io.out_uop.fu_code[1] connect issue_slots[13].out_uop.fu_code[2], slots_13.io.out_uop.fu_code[2] connect issue_slots[13].out_uop.fu_code[3], slots_13.io.out_uop.fu_code[3] connect issue_slots[13].out_uop.fu_code[4], slots_13.io.out_uop.fu_code[4] connect issue_slots[13].out_uop.fu_code[5], slots_13.io.out_uop.fu_code[5] connect issue_slots[13].out_uop.fu_code[6], slots_13.io.out_uop.fu_code[6] connect issue_slots[13].out_uop.fu_code[7], slots_13.io.out_uop.fu_code[7] connect issue_slots[13].out_uop.fu_code[8], slots_13.io.out_uop.fu_code[8] connect issue_slots[13].out_uop.fu_code[9], slots_13.io.out_uop.fu_code[9] connect issue_slots[13].out_uop.iq_type[0], slots_13.io.out_uop.iq_type[0] connect issue_slots[13].out_uop.iq_type[1], slots_13.io.out_uop.iq_type[1] connect issue_slots[13].out_uop.iq_type[2], slots_13.io.out_uop.iq_type[2] connect issue_slots[13].out_uop.iq_type[3], slots_13.io.out_uop.iq_type[3] connect issue_slots[13].out_uop.debug_pc, slots_13.io.out_uop.debug_pc connect issue_slots[13].out_uop.is_rvc, slots_13.io.out_uop.is_rvc connect issue_slots[13].out_uop.debug_inst, slots_13.io.out_uop.debug_inst connect issue_slots[13].out_uop.inst, slots_13.io.out_uop.inst connect slots_13.io.in_uop.bits.debug_tsrc, issue_slots[13].in_uop.bits.debug_tsrc connect slots_13.io.in_uop.bits.debug_fsrc, issue_slots[13].in_uop.bits.debug_fsrc connect slots_13.io.in_uop.bits.bp_xcpt_if, issue_slots[13].in_uop.bits.bp_xcpt_if connect slots_13.io.in_uop.bits.bp_debug_if, issue_slots[13].in_uop.bits.bp_debug_if connect slots_13.io.in_uop.bits.xcpt_ma_if, issue_slots[13].in_uop.bits.xcpt_ma_if connect slots_13.io.in_uop.bits.xcpt_ae_if, issue_slots[13].in_uop.bits.xcpt_ae_if connect slots_13.io.in_uop.bits.xcpt_pf_if, issue_slots[13].in_uop.bits.xcpt_pf_if connect slots_13.io.in_uop.bits.fp_typ, issue_slots[13].in_uop.bits.fp_typ connect slots_13.io.in_uop.bits.fp_rm, issue_slots[13].in_uop.bits.fp_rm connect slots_13.io.in_uop.bits.fp_val, issue_slots[13].in_uop.bits.fp_val connect slots_13.io.in_uop.bits.fcn_op, issue_slots[13].in_uop.bits.fcn_op connect slots_13.io.in_uop.bits.fcn_dw, issue_slots[13].in_uop.bits.fcn_dw connect slots_13.io.in_uop.bits.frs3_en, issue_slots[13].in_uop.bits.frs3_en connect slots_13.io.in_uop.bits.lrs2_rtype, issue_slots[13].in_uop.bits.lrs2_rtype connect slots_13.io.in_uop.bits.lrs1_rtype, issue_slots[13].in_uop.bits.lrs1_rtype connect slots_13.io.in_uop.bits.dst_rtype, issue_slots[13].in_uop.bits.dst_rtype connect slots_13.io.in_uop.bits.lrs3, issue_slots[13].in_uop.bits.lrs3 connect slots_13.io.in_uop.bits.lrs2, issue_slots[13].in_uop.bits.lrs2 connect slots_13.io.in_uop.bits.lrs1, issue_slots[13].in_uop.bits.lrs1 connect slots_13.io.in_uop.bits.ldst, issue_slots[13].in_uop.bits.ldst connect slots_13.io.in_uop.bits.ldst_is_rs1, issue_slots[13].in_uop.bits.ldst_is_rs1 connect slots_13.io.in_uop.bits.csr_cmd, issue_slots[13].in_uop.bits.csr_cmd connect slots_13.io.in_uop.bits.flush_on_commit, issue_slots[13].in_uop.bits.flush_on_commit connect slots_13.io.in_uop.bits.is_unique, issue_slots[13].in_uop.bits.is_unique connect slots_13.io.in_uop.bits.uses_stq, issue_slots[13].in_uop.bits.uses_stq connect slots_13.io.in_uop.bits.uses_ldq, issue_slots[13].in_uop.bits.uses_ldq connect slots_13.io.in_uop.bits.mem_signed, issue_slots[13].in_uop.bits.mem_signed connect slots_13.io.in_uop.bits.mem_size, issue_slots[13].in_uop.bits.mem_size connect slots_13.io.in_uop.bits.mem_cmd, issue_slots[13].in_uop.bits.mem_cmd connect slots_13.io.in_uop.bits.exc_cause, issue_slots[13].in_uop.bits.exc_cause connect slots_13.io.in_uop.bits.exception, issue_slots[13].in_uop.bits.exception connect slots_13.io.in_uop.bits.stale_pdst, issue_slots[13].in_uop.bits.stale_pdst connect slots_13.io.in_uop.bits.ppred_busy, issue_slots[13].in_uop.bits.ppred_busy connect slots_13.io.in_uop.bits.prs3_busy, issue_slots[13].in_uop.bits.prs3_busy connect slots_13.io.in_uop.bits.prs2_busy, issue_slots[13].in_uop.bits.prs2_busy connect slots_13.io.in_uop.bits.prs1_busy, issue_slots[13].in_uop.bits.prs1_busy connect slots_13.io.in_uop.bits.ppred, issue_slots[13].in_uop.bits.ppred connect slots_13.io.in_uop.bits.prs3, issue_slots[13].in_uop.bits.prs3 connect slots_13.io.in_uop.bits.prs2, issue_slots[13].in_uop.bits.prs2 connect slots_13.io.in_uop.bits.prs1, issue_slots[13].in_uop.bits.prs1 connect slots_13.io.in_uop.bits.pdst, issue_slots[13].in_uop.bits.pdst connect slots_13.io.in_uop.bits.rxq_idx, issue_slots[13].in_uop.bits.rxq_idx connect slots_13.io.in_uop.bits.stq_idx, issue_slots[13].in_uop.bits.stq_idx connect slots_13.io.in_uop.bits.ldq_idx, issue_slots[13].in_uop.bits.ldq_idx connect slots_13.io.in_uop.bits.rob_idx, issue_slots[13].in_uop.bits.rob_idx connect slots_13.io.in_uop.bits.fp_ctrl.vec, issue_slots[13].in_uop.bits.fp_ctrl.vec connect slots_13.io.in_uop.bits.fp_ctrl.wflags, issue_slots[13].in_uop.bits.fp_ctrl.wflags connect slots_13.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[13].in_uop.bits.fp_ctrl.sqrt connect slots_13.io.in_uop.bits.fp_ctrl.div, issue_slots[13].in_uop.bits.fp_ctrl.div connect slots_13.io.in_uop.bits.fp_ctrl.fma, issue_slots[13].in_uop.bits.fp_ctrl.fma connect slots_13.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[13].in_uop.bits.fp_ctrl.fastpipe connect slots_13.io.in_uop.bits.fp_ctrl.toint, issue_slots[13].in_uop.bits.fp_ctrl.toint connect slots_13.io.in_uop.bits.fp_ctrl.fromint, issue_slots[13].in_uop.bits.fp_ctrl.fromint connect slots_13.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[13].in_uop.bits.fp_ctrl.typeTagOut connect slots_13.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[13].in_uop.bits.fp_ctrl.typeTagIn connect slots_13.io.in_uop.bits.fp_ctrl.swap23, issue_slots[13].in_uop.bits.fp_ctrl.swap23 connect slots_13.io.in_uop.bits.fp_ctrl.swap12, issue_slots[13].in_uop.bits.fp_ctrl.swap12 connect slots_13.io.in_uop.bits.fp_ctrl.ren3, issue_slots[13].in_uop.bits.fp_ctrl.ren3 connect slots_13.io.in_uop.bits.fp_ctrl.ren2, issue_slots[13].in_uop.bits.fp_ctrl.ren2 connect slots_13.io.in_uop.bits.fp_ctrl.ren1, issue_slots[13].in_uop.bits.fp_ctrl.ren1 connect slots_13.io.in_uop.bits.fp_ctrl.wen, issue_slots[13].in_uop.bits.fp_ctrl.wen connect slots_13.io.in_uop.bits.fp_ctrl.ldst, issue_slots[13].in_uop.bits.fp_ctrl.ldst connect slots_13.io.in_uop.bits.op2_sel, issue_slots[13].in_uop.bits.op2_sel connect slots_13.io.in_uop.bits.op1_sel, issue_slots[13].in_uop.bits.op1_sel connect slots_13.io.in_uop.bits.imm_packed, issue_slots[13].in_uop.bits.imm_packed connect slots_13.io.in_uop.bits.pimm, issue_slots[13].in_uop.bits.pimm connect slots_13.io.in_uop.bits.imm_sel, issue_slots[13].in_uop.bits.imm_sel connect slots_13.io.in_uop.bits.imm_rename, issue_slots[13].in_uop.bits.imm_rename connect slots_13.io.in_uop.bits.taken, issue_slots[13].in_uop.bits.taken connect slots_13.io.in_uop.bits.pc_lob, issue_slots[13].in_uop.bits.pc_lob connect slots_13.io.in_uop.bits.edge_inst, issue_slots[13].in_uop.bits.edge_inst connect slots_13.io.in_uop.bits.ftq_idx, issue_slots[13].in_uop.bits.ftq_idx connect slots_13.io.in_uop.bits.is_mov, issue_slots[13].in_uop.bits.is_mov connect slots_13.io.in_uop.bits.is_rocc, issue_slots[13].in_uop.bits.is_rocc connect slots_13.io.in_uop.bits.is_sys_pc2epc, issue_slots[13].in_uop.bits.is_sys_pc2epc connect slots_13.io.in_uop.bits.is_eret, issue_slots[13].in_uop.bits.is_eret connect slots_13.io.in_uop.bits.is_amo, issue_slots[13].in_uop.bits.is_amo connect slots_13.io.in_uop.bits.is_sfence, issue_slots[13].in_uop.bits.is_sfence connect slots_13.io.in_uop.bits.is_fencei, issue_slots[13].in_uop.bits.is_fencei connect slots_13.io.in_uop.bits.is_fence, issue_slots[13].in_uop.bits.is_fence connect slots_13.io.in_uop.bits.is_sfb, issue_slots[13].in_uop.bits.is_sfb connect slots_13.io.in_uop.bits.br_type, issue_slots[13].in_uop.bits.br_type connect slots_13.io.in_uop.bits.br_tag, issue_slots[13].in_uop.bits.br_tag connect slots_13.io.in_uop.bits.br_mask, issue_slots[13].in_uop.bits.br_mask connect slots_13.io.in_uop.bits.dis_col_sel, issue_slots[13].in_uop.bits.dis_col_sel connect slots_13.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[13].in_uop.bits.iw_p3_bypass_hint connect slots_13.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[13].in_uop.bits.iw_p2_bypass_hint connect slots_13.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[13].in_uop.bits.iw_p1_bypass_hint connect slots_13.io.in_uop.bits.iw_p2_speculative_child, issue_slots[13].in_uop.bits.iw_p2_speculative_child connect slots_13.io.in_uop.bits.iw_p1_speculative_child, issue_slots[13].in_uop.bits.iw_p1_speculative_child connect slots_13.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[13].in_uop.bits.iw_issued_partial_dgen connect slots_13.io.in_uop.bits.iw_issued_partial_agen, issue_slots[13].in_uop.bits.iw_issued_partial_agen connect slots_13.io.in_uop.bits.iw_issued, issue_slots[13].in_uop.bits.iw_issued connect slots_13.io.in_uop.bits.fu_code[0], issue_slots[13].in_uop.bits.fu_code[0] connect slots_13.io.in_uop.bits.fu_code[1], issue_slots[13].in_uop.bits.fu_code[1] connect slots_13.io.in_uop.bits.fu_code[2], issue_slots[13].in_uop.bits.fu_code[2] connect slots_13.io.in_uop.bits.fu_code[3], issue_slots[13].in_uop.bits.fu_code[3] connect slots_13.io.in_uop.bits.fu_code[4], issue_slots[13].in_uop.bits.fu_code[4] connect slots_13.io.in_uop.bits.fu_code[5], issue_slots[13].in_uop.bits.fu_code[5] connect slots_13.io.in_uop.bits.fu_code[6], issue_slots[13].in_uop.bits.fu_code[6] connect slots_13.io.in_uop.bits.fu_code[7], issue_slots[13].in_uop.bits.fu_code[7] connect slots_13.io.in_uop.bits.fu_code[8], issue_slots[13].in_uop.bits.fu_code[8] connect slots_13.io.in_uop.bits.fu_code[9], issue_slots[13].in_uop.bits.fu_code[9] connect slots_13.io.in_uop.bits.iq_type[0], issue_slots[13].in_uop.bits.iq_type[0] connect slots_13.io.in_uop.bits.iq_type[1], issue_slots[13].in_uop.bits.iq_type[1] connect slots_13.io.in_uop.bits.iq_type[2], issue_slots[13].in_uop.bits.iq_type[2] connect slots_13.io.in_uop.bits.iq_type[3], issue_slots[13].in_uop.bits.iq_type[3] connect slots_13.io.in_uop.bits.debug_pc, issue_slots[13].in_uop.bits.debug_pc connect slots_13.io.in_uop.bits.is_rvc, issue_slots[13].in_uop.bits.is_rvc connect slots_13.io.in_uop.bits.debug_inst, issue_slots[13].in_uop.bits.debug_inst connect slots_13.io.in_uop.bits.inst, issue_slots[13].in_uop.bits.inst connect slots_13.io.in_uop.valid, issue_slots[13].in_uop.valid connect issue_slots[13].iss_uop.debug_tsrc, slots_13.io.iss_uop.debug_tsrc connect issue_slots[13].iss_uop.debug_fsrc, slots_13.io.iss_uop.debug_fsrc connect issue_slots[13].iss_uop.bp_xcpt_if, slots_13.io.iss_uop.bp_xcpt_if connect issue_slots[13].iss_uop.bp_debug_if, slots_13.io.iss_uop.bp_debug_if connect issue_slots[13].iss_uop.xcpt_ma_if, slots_13.io.iss_uop.xcpt_ma_if connect issue_slots[13].iss_uop.xcpt_ae_if, slots_13.io.iss_uop.xcpt_ae_if connect issue_slots[13].iss_uop.xcpt_pf_if, slots_13.io.iss_uop.xcpt_pf_if connect issue_slots[13].iss_uop.fp_typ, slots_13.io.iss_uop.fp_typ connect issue_slots[13].iss_uop.fp_rm, slots_13.io.iss_uop.fp_rm connect issue_slots[13].iss_uop.fp_val, slots_13.io.iss_uop.fp_val connect issue_slots[13].iss_uop.fcn_op, slots_13.io.iss_uop.fcn_op connect issue_slots[13].iss_uop.fcn_dw, slots_13.io.iss_uop.fcn_dw connect issue_slots[13].iss_uop.frs3_en, slots_13.io.iss_uop.frs3_en connect issue_slots[13].iss_uop.lrs2_rtype, slots_13.io.iss_uop.lrs2_rtype connect issue_slots[13].iss_uop.lrs1_rtype, slots_13.io.iss_uop.lrs1_rtype connect issue_slots[13].iss_uop.dst_rtype, slots_13.io.iss_uop.dst_rtype connect issue_slots[13].iss_uop.lrs3, slots_13.io.iss_uop.lrs3 connect issue_slots[13].iss_uop.lrs2, slots_13.io.iss_uop.lrs2 connect issue_slots[13].iss_uop.lrs1, slots_13.io.iss_uop.lrs1 connect issue_slots[13].iss_uop.ldst, slots_13.io.iss_uop.ldst connect issue_slots[13].iss_uop.ldst_is_rs1, slots_13.io.iss_uop.ldst_is_rs1 connect issue_slots[13].iss_uop.csr_cmd, slots_13.io.iss_uop.csr_cmd connect issue_slots[13].iss_uop.flush_on_commit, slots_13.io.iss_uop.flush_on_commit connect issue_slots[13].iss_uop.is_unique, slots_13.io.iss_uop.is_unique connect issue_slots[13].iss_uop.uses_stq, slots_13.io.iss_uop.uses_stq connect issue_slots[13].iss_uop.uses_ldq, slots_13.io.iss_uop.uses_ldq connect issue_slots[13].iss_uop.mem_signed, slots_13.io.iss_uop.mem_signed connect issue_slots[13].iss_uop.mem_size, slots_13.io.iss_uop.mem_size connect issue_slots[13].iss_uop.mem_cmd, slots_13.io.iss_uop.mem_cmd connect issue_slots[13].iss_uop.exc_cause, slots_13.io.iss_uop.exc_cause connect issue_slots[13].iss_uop.exception, slots_13.io.iss_uop.exception connect issue_slots[13].iss_uop.stale_pdst, slots_13.io.iss_uop.stale_pdst connect issue_slots[13].iss_uop.ppred_busy, slots_13.io.iss_uop.ppred_busy connect issue_slots[13].iss_uop.prs3_busy, slots_13.io.iss_uop.prs3_busy connect issue_slots[13].iss_uop.prs2_busy, slots_13.io.iss_uop.prs2_busy connect issue_slots[13].iss_uop.prs1_busy, slots_13.io.iss_uop.prs1_busy connect issue_slots[13].iss_uop.ppred, slots_13.io.iss_uop.ppred connect issue_slots[13].iss_uop.prs3, slots_13.io.iss_uop.prs3 connect issue_slots[13].iss_uop.prs2, slots_13.io.iss_uop.prs2 connect issue_slots[13].iss_uop.prs1, slots_13.io.iss_uop.prs1 connect issue_slots[13].iss_uop.pdst, slots_13.io.iss_uop.pdst connect issue_slots[13].iss_uop.rxq_idx, slots_13.io.iss_uop.rxq_idx connect issue_slots[13].iss_uop.stq_idx, slots_13.io.iss_uop.stq_idx connect issue_slots[13].iss_uop.ldq_idx, slots_13.io.iss_uop.ldq_idx connect issue_slots[13].iss_uop.rob_idx, slots_13.io.iss_uop.rob_idx connect issue_slots[13].iss_uop.fp_ctrl.vec, slots_13.io.iss_uop.fp_ctrl.vec connect issue_slots[13].iss_uop.fp_ctrl.wflags, slots_13.io.iss_uop.fp_ctrl.wflags connect issue_slots[13].iss_uop.fp_ctrl.sqrt, slots_13.io.iss_uop.fp_ctrl.sqrt connect issue_slots[13].iss_uop.fp_ctrl.div, slots_13.io.iss_uop.fp_ctrl.div connect issue_slots[13].iss_uop.fp_ctrl.fma, slots_13.io.iss_uop.fp_ctrl.fma connect issue_slots[13].iss_uop.fp_ctrl.fastpipe, slots_13.io.iss_uop.fp_ctrl.fastpipe connect issue_slots[13].iss_uop.fp_ctrl.toint, slots_13.io.iss_uop.fp_ctrl.toint connect issue_slots[13].iss_uop.fp_ctrl.fromint, slots_13.io.iss_uop.fp_ctrl.fromint connect issue_slots[13].iss_uop.fp_ctrl.typeTagOut, slots_13.io.iss_uop.fp_ctrl.typeTagOut connect issue_slots[13].iss_uop.fp_ctrl.typeTagIn, slots_13.io.iss_uop.fp_ctrl.typeTagIn connect issue_slots[13].iss_uop.fp_ctrl.swap23, slots_13.io.iss_uop.fp_ctrl.swap23 connect issue_slots[13].iss_uop.fp_ctrl.swap12, slots_13.io.iss_uop.fp_ctrl.swap12 connect issue_slots[13].iss_uop.fp_ctrl.ren3, slots_13.io.iss_uop.fp_ctrl.ren3 connect issue_slots[13].iss_uop.fp_ctrl.ren2, slots_13.io.iss_uop.fp_ctrl.ren2 connect issue_slots[13].iss_uop.fp_ctrl.ren1, slots_13.io.iss_uop.fp_ctrl.ren1 connect issue_slots[13].iss_uop.fp_ctrl.wen, slots_13.io.iss_uop.fp_ctrl.wen connect issue_slots[13].iss_uop.fp_ctrl.ldst, slots_13.io.iss_uop.fp_ctrl.ldst connect issue_slots[13].iss_uop.op2_sel, slots_13.io.iss_uop.op2_sel connect issue_slots[13].iss_uop.op1_sel, slots_13.io.iss_uop.op1_sel connect issue_slots[13].iss_uop.imm_packed, slots_13.io.iss_uop.imm_packed connect issue_slots[13].iss_uop.pimm, slots_13.io.iss_uop.pimm connect issue_slots[13].iss_uop.imm_sel, slots_13.io.iss_uop.imm_sel connect issue_slots[13].iss_uop.imm_rename, slots_13.io.iss_uop.imm_rename connect issue_slots[13].iss_uop.taken, slots_13.io.iss_uop.taken connect issue_slots[13].iss_uop.pc_lob, slots_13.io.iss_uop.pc_lob connect issue_slots[13].iss_uop.edge_inst, slots_13.io.iss_uop.edge_inst connect issue_slots[13].iss_uop.ftq_idx, slots_13.io.iss_uop.ftq_idx connect issue_slots[13].iss_uop.is_mov, slots_13.io.iss_uop.is_mov connect issue_slots[13].iss_uop.is_rocc, slots_13.io.iss_uop.is_rocc connect issue_slots[13].iss_uop.is_sys_pc2epc, slots_13.io.iss_uop.is_sys_pc2epc connect issue_slots[13].iss_uop.is_eret, slots_13.io.iss_uop.is_eret connect issue_slots[13].iss_uop.is_amo, slots_13.io.iss_uop.is_amo connect issue_slots[13].iss_uop.is_sfence, slots_13.io.iss_uop.is_sfence connect issue_slots[13].iss_uop.is_fencei, slots_13.io.iss_uop.is_fencei connect issue_slots[13].iss_uop.is_fence, slots_13.io.iss_uop.is_fence connect issue_slots[13].iss_uop.is_sfb, slots_13.io.iss_uop.is_sfb connect issue_slots[13].iss_uop.br_type, slots_13.io.iss_uop.br_type connect issue_slots[13].iss_uop.br_tag, slots_13.io.iss_uop.br_tag connect issue_slots[13].iss_uop.br_mask, slots_13.io.iss_uop.br_mask connect issue_slots[13].iss_uop.dis_col_sel, slots_13.io.iss_uop.dis_col_sel connect issue_slots[13].iss_uop.iw_p3_bypass_hint, slots_13.io.iss_uop.iw_p3_bypass_hint connect issue_slots[13].iss_uop.iw_p2_bypass_hint, slots_13.io.iss_uop.iw_p2_bypass_hint connect issue_slots[13].iss_uop.iw_p1_bypass_hint, slots_13.io.iss_uop.iw_p1_bypass_hint connect issue_slots[13].iss_uop.iw_p2_speculative_child, slots_13.io.iss_uop.iw_p2_speculative_child connect issue_slots[13].iss_uop.iw_p1_speculative_child, slots_13.io.iss_uop.iw_p1_speculative_child connect issue_slots[13].iss_uop.iw_issued_partial_dgen, slots_13.io.iss_uop.iw_issued_partial_dgen connect issue_slots[13].iss_uop.iw_issued_partial_agen, slots_13.io.iss_uop.iw_issued_partial_agen connect issue_slots[13].iss_uop.iw_issued, slots_13.io.iss_uop.iw_issued connect issue_slots[13].iss_uop.fu_code[0], slots_13.io.iss_uop.fu_code[0] connect issue_slots[13].iss_uop.fu_code[1], slots_13.io.iss_uop.fu_code[1] connect issue_slots[13].iss_uop.fu_code[2], slots_13.io.iss_uop.fu_code[2] connect issue_slots[13].iss_uop.fu_code[3], slots_13.io.iss_uop.fu_code[3] connect issue_slots[13].iss_uop.fu_code[4], slots_13.io.iss_uop.fu_code[4] connect issue_slots[13].iss_uop.fu_code[5], slots_13.io.iss_uop.fu_code[5] connect issue_slots[13].iss_uop.fu_code[6], slots_13.io.iss_uop.fu_code[6] connect issue_slots[13].iss_uop.fu_code[7], slots_13.io.iss_uop.fu_code[7] connect issue_slots[13].iss_uop.fu_code[8], slots_13.io.iss_uop.fu_code[8] connect issue_slots[13].iss_uop.fu_code[9], slots_13.io.iss_uop.fu_code[9] connect issue_slots[13].iss_uop.iq_type[0], slots_13.io.iss_uop.iq_type[0] connect issue_slots[13].iss_uop.iq_type[1], slots_13.io.iss_uop.iq_type[1] connect issue_slots[13].iss_uop.iq_type[2], slots_13.io.iss_uop.iq_type[2] connect issue_slots[13].iss_uop.iq_type[3], slots_13.io.iss_uop.iq_type[3] connect issue_slots[13].iss_uop.debug_pc, slots_13.io.iss_uop.debug_pc connect issue_slots[13].iss_uop.is_rvc, slots_13.io.iss_uop.is_rvc connect issue_slots[13].iss_uop.debug_inst, slots_13.io.iss_uop.debug_inst connect issue_slots[13].iss_uop.inst, slots_13.io.iss_uop.inst connect slots_13.io.grant, issue_slots[13].grant connect issue_slots[13].request, slots_13.io.request connect issue_slots[13].will_be_valid, slots_13.io.will_be_valid connect issue_slots[13].valid, slots_13.io.valid connect slots_14.io.child_rebusys, issue_slots[14].child_rebusys connect slots_14.io.pred_wakeup_port.bits, issue_slots[14].pred_wakeup_port.bits connect slots_14.io.pred_wakeup_port.valid, issue_slots[14].pred_wakeup_port.valid connect slots_14.io.wakeup_ports[0].bits.rebusy, issue_slots[14].wakeup_ports[0].bits.rebusy connect slots_14.io.wakeup_ports[0].bits.speculative_mask, issue_slots[14].wakeup_ports[0].bits.speculative_mask connect slots_14.io.wakeup_ports[0].bits.bypassable, issue_slots[14].wakeup_ports[0].bits.bypassable connect slots_14.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[14].wakeup_ports[0].bits.uop.debug_tsrc connect slots_14.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[14].wakeup_ports[0].bits.uop.debug_fsrc connect slots_14.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[14].wakeup_ports[0].bits.uop.bp_xcpt_if connect slots_14.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[14].wakeup_ports[0].bits.uop.bp_debug_if connect slots_14.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[14].wakeup_ports[0].bits.uop.xcpt_ma_if connect slots_14.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[14].wakeup_ports[0].bits.uop.xcpt_ae_if connect slots_14.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[14].wakeup_ports[0].bits.uop.xcpt_pf_if connect slots_14.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[14].wakeup_ports[0].bits.uop.fp_typ connect slots_14.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[14].wakeup_ports[0].bits.uop.fp_rm connect slots_14.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[14].wakeup_ports[0].bits.uop.fp_val connect slots_14.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[14].wakeup_ports[0].bits.uop.fcn_op connect slots_14.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[14].wakeup_ports[0].bits.uop.fcn_dw connect slots_14.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[14].wakeup_ports[0].bits.uop.frs3_en connect slots_14.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[14].wakeup_ports[0].bits.uop.lrs2_rtype connect slots_14.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[14].wakeup_ports[0].bits.uop.lrs1_rtype connect slots_14.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[14].wakeup_ports[0].bits.uop.dst_rtype connect slots_14.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[14].wakeup_ports[0].bits.uop.lrs3 connect slots_14.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[14].wakeup_ports[0].bits.uop.lrs2 connect slots_14.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[14].wakeup_ports[0].bits.uop.lrs1 connect slots_14.io.wakeup_ports[0].bits.uop.ldst, issue_slots[14].wakeup_ports[0].bits.uop.ldst connect slots_14.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[14].wakeup_ports[0].bits.uop.ldst_is_rs1 connect slots_14.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[14].wakeup_ports[0].bits.uop.csr_cmd connect slots_14.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[14].wakeup_ports[0].bits.uop.flush_on_commit connect slots_14.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[14].wakeup_ports[0].bits.uop.is_unique connect slots_14.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[14].wakeup_ports[0].bits.uop.uses_stq connect slots_14.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[14].wakeup_ports[0].bits.uop.uses_ldq connect slots_14.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[14].wakeup_ports[0].bits.uop.mem_signed connect slots_14.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[14].wakeup_ports[0].bits.uop.mem_size connect slots_14.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[14].wakeup_ports[0].bits.uop.mem_cmd connect slots_14.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[14].wakeup_ports[0].bits.uop.exc_cause connect slots_14.io.wakeup_ports[0].bits.uop.exception, issue_slots[14].wakeup_ports[0].bits.uop.exception connect slots_14.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[14].wakeup_ports[0].bits.uop.stale_pdst connect slots_14.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[14].wakeup_ports[0].bits.uop.ppred_busy connect slots_14.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[14].wakeup_ports[0].bits.uop.prs3_busy connect slots_14.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[14].wakeup_ports[0].bits.uop.prs2_busy connect slots_14.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[14].wakeup_ports[0].bits.uop.prs1_busy connect slots_14.io.wakeup_ports[0].bits.uop.ppred, issue_slots[14].wakeup_ports[0].bits.uop.ppred connect slots_14.io.wakeup_ports[0].bits.uop.prs3, issue_slots[14].wakeup_ports[0].bits.uop.prs3 connect slots_14.io.wakeup_ports[0].bits.uop.prs2, issue_slots[14].wakeup_ports[0].bits.uop.prs2 connect slots_14.io.wakeup_ports[0].bits.uop.prs1, issue_slots[14].wakeup_ports[0].bits.uop.prs1 connect slots_14.io.wakeup_ports[0].bits.uop.pdst, issue_slots[14].wakeup_ports[0].bits.uop.pdst connect slots_14.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[14].wakeup_ports[0].bits.uop.rxq_idx connect slots_14.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[14].wakeup_ports[0].bits.uop.stq_idx connect slots_14.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[14].wakeup_ports[0].bits.uop.ldq_idx connect slots_14.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[14].wakeup_ports[0].bits.uop.rob_idx connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.vec connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.wflags connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.div connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.fma connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.toint connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.fromint connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.wen connect slots_14.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.ldst connect slots_14.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[14].wakeup_ports[0].bits.uop.op2_sel connect slots_14.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[14].wakeup_ports[0].bits.uop.op1_sel connect slots_14.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[14].wakeup_ports[0].bits.uop.imm_packed connect slots_14.io.wakeup_ports[0].bits.uop.pimm, issue_slots[14].wakeup_ports[0].bits.uop.pimm connect slots_14.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[14].wakeup_ports[0].bits.uop.imm_sel connect slots_14.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[14].wakeup_ports[0].bits.uop.imm_rename connect slots_14.io.wakeup_ports[0].bits.uop.taken, issue_slots[14].wakeup_ports[0].bits.uop.taken connect slots_14.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[14].wakeup_ports[0].bits.uop.pc_lob connect slots_14.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[14].wakeup_ports[0].bits.uop.edge_inst connect slots_14.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[14].wakeup_ports[0].bits.uop.ftq_idx connect slots_14.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[14].wakeup_ports[0].bits.uop.is_mov connect slots_14.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[14].wakeup_ports[0].bits.uop.is_rocc connect slots_14.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[14].wakeup_ports[0].bits.uop.is_sys_pc2epc connect slots_14.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[14].wakeup_ports[0].bits.uop.is_eret connect slots_14.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[14].wakeup_ports[0].bits.uop.is_amo connect slots_14.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[14].wakeup_ports[0].bits.uop.is_sfence connect slots_14.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[14].wakeup_ports[0].bits.uop.is_fencei connect slots_14.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[14].wakeup_ports[0].bits.uop.is_fence connect slots_14.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[14].wakeup_ports[0].bits.uop.is_sfb connect slots_14.io.wakeup_ports[0].bits.uop.br_type, issue_slots[14].wakeup_ports[0].bits.uop.br_type connect slots_14.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[14].wakeup_ports[0].bits.uop.br_tag connect slots_14.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[14].wakeup_ports[0].bits.uop.br_mask connect slots_14.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[14].wakeup_ports[0].bits.uop.dis_col_sel connect slots_14.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[14].wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect slots_14.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[14].wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect slots_14.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[14].wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect slots_14.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[14].wakeup_ports[0].bits.uop.iw_p2_speculative_child connect slots_14.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[14].wakeup_ports[0].bits.uop.iw_p1_speculative_child connect slots_14.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[14].wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect slots_14.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[14].wakeup_ports[0].bits.uop.iw_issued_partial_agen connect slots_14.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[14].wakeup_ports[0].bits.uop.iw_issued connect slots_14.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[14].wakeup_ports[0].bits.uop.fu_code[0] connect slots_14.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[14].wakeup_ports[0].bits.uop.fu_code[1] connect slots_14.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[14].wakeup_ports[0].bits.uop.fu_code[2] connect slots_14.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[14].wakeup_ports[0].bits.uop.fu_code[3] connect slots_14.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[14].wakeup_ports[0].bits.uop.fu_code[4] connect slots_14.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[14].wakeup_ports[0].bits.uop.fu_code[5] connect slots_14.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[14].wakeup_ports[0].bits.uop.fu_code[6] connect slots_14.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[14].wakeup_ports[0].bits.uop.fu_code[7] connect slots_14.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[14].wakeup_ports[0].bits.uop.fu_code[8] connect slots_14.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[14].wakeup_ports[0].bits.uop.fu_code[9] connect slots_14.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[14].wakeup_ports[0].bits.uop.iq_type[0] connect slots_14.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[14].wakeup_ports[0].bits.uop.iq_type[1] connect slots_14.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[14].wakeup_ports[0].bits.uop.iq_type[2] connect slots_14.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[14].wakeup_ports[0].bits.uop.iq_type[3] connect slots_14.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[14].wakeup_ports[0].bits.uop.debug_pc connect slots_14.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[14].wakeup_ports[0].bits.uop.is_rvc connect slots_14.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[14].wakeup_ports[0].bits.uop.debug_inst connect slots_14.io.wakeup_ports[0].bits.uop.inst, issue_slots[14].wakeup_ports[0].bits.uop.inst connect slots_14.io.wakeup_ports[0].valid, issue_slots[14].wakeup_ports[0].valid connect slots_14.io.wakeup_ports[1].bits.rebusy, issue_slots[14].wakeup_ports[1].bits.rebusy connect slots_14.io.wakeup_ports[1].bits.speculative_mask, issue_slots[14].wakeup_ports[1].bits.speculative_mask connect slots_14.io.wakeup_ports[1].bits.bypassable, issue_slots[14].wakeup_ports[1].bits.bypassable connect slots_14.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[14].wakeup_ports[1].bits.uop.debug_tsrc connect slots_14.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[14].wakeup_ports[1].bits.uop.debug_fsrc connect slots_14.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[14].wakeup_ports[1].bits.uop.bp_xcpt_if connect slots_14.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[14].wakeup_ports[1].bits.uop.bp_debug_if connect slots_14.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[14].wakeup_ports[1].bits.uop.xcpt_ma_if connect slots_14.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[14].wakeup_ports[1].bits.uop.xcpt_ae_if connect slots_14.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[14].wakeup_ports[1].bits.uop.xcpt_pf_if connect slots_14.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[14].wakeup_ports[1].bits.uop.fp_typ connect slots_14.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[14].wakeup_ports[1].bits.uop.fp_rm connect slots_14.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[14].wakeup_ports[1].bits.uop.fp_val connect slots_14.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[14].wakeup_ports[1].bits.uop.fcn_op connect slots_14.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[14].wakeup_ports[1].bits.uop.fcn_dw connect slots_14.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[14].wakeup_ports[1].bits.uop.frs3_en connect slots_14.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[14].wakeup_ports[1].bits.uop.lrs2_rtype connect slots_14.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[14].wakeup_ports[1].bits.uop.lrs1_rtype connect slots_14.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[14].wakeup_ports[1].bits.uop.dst_rtype connect slots_14.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[14].wakeup_ports[1].bits.uop.lrs3 connect slots_14.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[14].wakeup_ports[1].bits.uop.lrs2 connect slots_14.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[14].wakeup_ports[1].bits.uop.lrs1 connect slots_14.io.wakeup_ports[1].bits.uop.ldst, issue_slots[14].wakeup_ports[1].bits.uop.ldst connect slots_14.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[14].wakeup_ports[1].bits.uop.ldst_is_rs1 connect slots_14.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[14].wakeup_ports[1].bits.uop.csr_cmd connect slots_14.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[14].wakeup_ports[1].bits.uop.flush_on_commit connect slots_14.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[14].wakeup_ports[1].bits.uop.is_unique connect slots_14.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[14].wakeup_ports[1].bits.uop.uses_stq connect slots_14.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[14].wakeup_ports[1].bits.uop.uses_ldq connect slots_14.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[14].wakeup_ports[1].bits.uop.mem_signed connect slots_14.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[14].wakeup_ports[1].bits.uop.mem_size connect slots_14.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[14].wakeup_ports[1].bits.uop.mem_cmd connect slots_14.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[14].wakeup_ports[1].bits.uop.exc_cause connect slots_14.io.wakeup_ports[1].bits.uop.exception, issue_slots[14].wakeup_ports[1].bits.uop.exception connect slots_14.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[14].wakeup_ports[1].bits.uop.stale_pdst connect slots_14.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[14].wakeup_ports[1].bits.uop.ppred_busy connect slots_14.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[14].wakeup_ports[1].bits.uop.prs3_busy connect slots_14.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[14].wakeup_ports[1].bits.uop.prs2_busy connect slots_14.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[14].wakeup_ports[1].bits.uop.prs1_busy connect slots_14.io.wakeup_ports[1].bits.uop.ppred, issue_slots[14].wakeup_ports[1].bits.uop.ppred connect slots_14.io.wakeup_ports[1].bits.uop.prs3, issue_slots[14].wakeup_ports[1].bits.uop.prs3 connect slots_14.io.wakeup_ports[1].bits.uop.prs2, issue_slots[14].wakeup_ports[1].bits.uop.prs2 connect slots_14.io.wakeup_ports[1].bits.uop.prs1, issue_slots[14].wakeup_ports[1].bits.uop.prs1 connect slots_14.io.wakeup_ports[1].bits.uop.pdst, issue_slots[14].wakeup_ports[1].bits.uop.pdst connect slots_14.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[14].wakeup_ports[1].bits.uop.rxq_idx connect slots_14.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[14].wakeup_ports[1].bits.uop.stq_idx connect slots_14.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[14].wakeup_ports[1].bits.uop.ldq_idx connect slots_14.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[14].wakeup_ports[1].bits.uop.rob_idx connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.vec connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.wflags connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.div connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.fma connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.toint connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.fromint connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.wen connect slots_14.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.ldst connect slots_14.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[14].wakeup_ports[1].bits.uop.op2_sel connect slots_14.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[14].wakeup_ports[1].bits.uop.op1_sel connect slots_14.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[14].wakeup_ports[1].bits.uop.imm_packed connect slots_14.io.wakeup_ports[1].bits.uop.pimm, issue_slots[14].wakeup_ports[1].bits.uop.pimm connect slots_14.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[14].wakeup_ports[1].bits.uop.imm_sel connect slots_14.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[14].wakeup_ports[1].bits.uop.imm_rename connect slots_14.io.wakeup_ports[1].bits.uop.taken, issue_slots[14].wakeup_ports[1].bits.uop.taken connect slots_14.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[14].wakeup_ports[1].bits.uop.pc_lob connect slots_14.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[14].wakeup_ports[1].bits.uop.edge_inst connect slots_14.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[14].wakeup_ports[1].bits.uop.ftq_idx connect slots_14.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[14].wakeup_ports[1].bits.uop.is_mov connect slots_14.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[14].wakeup_ports[1].bits.uop.is_rocc connect slots_14.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[14].wakeup_ports[1].bits.uop.is_sys_pc2epc connect slots_14.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[14].wakeup_ports[1].bits.uop.is_eret connect slots_14.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[14].wakeup_ports[1].bits.uop.is_amo connect slots_14.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[14].wakeup_ports[1].bits.uop.is_sfence connect slots_14.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[14].wakeup_ports[1].bits.uop.is_fencei connect slots_14.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[14].wakeup_ports[1].bits.uop.is_fence connect slots_14.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[14].wakeup_ports[1].bits.uop.is_sfb connect slots_14.io.wakeup_ports[1].bits.uop.br_type, issue_slots[14].wakeup_ports[1].bits.uop.br_type connect slots_14.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[14].wakeup_ports[1].bits.uop.br_tag connect slots_14.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[14].wakeup_ports[1].bits.uop.br_mask connect slots_14.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[14].wakeup_ports[1].bits.uop.dis_col_sel connect slots_14.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[14].wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect slots_14.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[14].wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect slots_14.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[14].wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect slots_14.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[14].wakeup_ports[1].bits.uop.iw_p2_speculative_child connect slots_14.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[14].wakeup_ports[1].bits.uop.iw_p1_speculative_child connect slots_14.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[14].wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect slots_14.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[14].wakeup_ports[1].bits.uop.iw_issued_partial_agen connect slots_14.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[14].wakeup_ports[1].bits.uop.iw_issued connect slots_14.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[14].wakeup_ports[1].bits.uop.fu_code[0] connect slots_14.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[14].wakeup_ports[1].bits.uop.fu_code[1] connect slots_14.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[14].wakeup_ports[1].bits.uop.fu_code[2] connect slots_14.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[14].wakeup_ports[1].bits.uop.fu_code[3] connect slots_14.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[14].wakeup_ports[1].bits.uop.fu_code[4] connect slots_14.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[14].wakeup_ports[1].bits.uop.fu_code[5] connect slots_14.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[14].wakeup_ports[1].bits.uop.fu_code[6] connect slots_14.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[14].wakeup_ports[1].bits.uop.fu_code[7] connect slots_14.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[14].wakeup_ports[1].bits.uop.fu_code[8] connect slots_14.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[14].wakeup_ports[1].bits.uop.fu_code[9] connect slots_14.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[14].wakeup_ports[1].bits.uop.iq_type[0] connect slots_14.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[14].wakeup_ports[1].bits.uop.iq_type[1] connect slots_14.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[14].wakeup_ports[1].bits.uop.iq_type[2] connect slots_14.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[14].wakeup_ports[1].bits.uop.iq_type[3] connect slots_14.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[14].wakeup_ports[1].bits.uop.debug_pc connect slots_14.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[14].wakeup_ports[1].bits.uop.is_rvc connect slots_14.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[14].wakeup_ports[1].bits.uop.debug_inst connect slots_14.io.wakeup_ports[1].bits.uop.inst, issue_slots[14].wakeup_ports[1].bits.uop.inst connect slots_14.io.wakeup_ports[1].valid, issue_slots[14].wakeup_ports[1].valid connect slots_14.io.wakeup_ports[2].bits.rebusy, issue_slots[14].wakeup_ports[2].bits.rebusy connect slots_14.io.wakeup_ports[2].bits.speculative_mask, issue_slots[14].wakeup_ports[2].bits.speculative_mask connect slots_14.io.wakeup_ports[2].bits.bypassable, issue_slots[14].wakeup_ports[2].bits.bypassable connect slots_14.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[14].wakeup_ports[2].bits.uop.debug_tsrc connect slots_14.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[14].wakeup_ports[2].bits.uop.debug_fsrc connect slots_14.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[14].wakeup_ports[2].bits.uop.bp_xcpt_if connect slots_14.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[14].wakeup_ports[2].bits.uop.bp_debug_if connect slots_14.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[14].wakeup_ports[2].bits.uop.xcpt_ma_if connect slots_14.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[14].wakeup_ports[2].bits.uop.xcpt_ae_if connect slots_14.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[14].wakeup_ports[2].bits.uop.xcpt_pf_if connect slots_14.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[14].wakeup_ports[2].bits.uop.fp_typ connect slots_14.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[14].wakeup_ports[2].bits.uop.fp_rm connect slots_14.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[14].wakeup_ports[2].bits.uop.fp_val connect slots_14.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[14].wakeup_ports[2].bits.uop.fcn_op connect slots_14.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[14].wakeup_ports[2].bits.uop.fcn_dw connect slots_14.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[14].wakeup_ports[2].bits.uop.frs3_en connect slots_14.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[14].wakeup_ports[2].bits.uop.lrs2_rtype connect slots_14.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[14].wakeup_ports[2].bits.uop.lrs1_rtype connect slots_14.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[14].wakeup_ports[2].bits.uop.dst_rtype connect slots_14.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[14].wakeup_ports[2].bits.uop.lrs3 connect slots_14.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[14].wakeup_ports[2].bits.uop.lrs2 connect slots_14.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[14].wakeup_ports[2].bits.uop.lrs1 connect slots_14.io.wakeup_ports[2].bits.uop.ldst, issue_slots[14].wakeup_ports[2].bits.uop.ldst connect slots_14.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[14].wakeup_ports[2].bits.uop.ldst_is_rs1 connect slots_14.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[14].wakeup_ports[2].bits.uop.csr_cmd connect slots_14.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[14].wakeup_ports[2].bits.uop.flush_on_commit connect slots_14.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[14].wakeup_ports[2].bits.uop.is_unique connect slots_14.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[14].wakeup_ports[2].bits.uop.uses_stq connect slots_14.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[14].wakeup_ports[2].bits.uop.uses_ldq connect slots_14.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[14].wakeup_ports[2].bits.uop.mem_signed connect slots_14.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[14].wakeup_ports[2].bits.uop.mem_size connect slots_14.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[14].wakeup_ports[2].bits.uop.mem_cmd connect slots_14.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[14].wakeup_ports[2].bits.uop.exc_cause connect slots_14.io.wakeup_ports[2].bits.uop.exception, issue_slots[14].wakeup_ports[2].bits.uop.exception connect slots_14.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[14].wakeup_ports[2].bits.uop.stale_pdst connect slots_14.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[14].wakeup_ports[2].bits.uop.ppred_busy connect slots_14.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[14].wakeup_ports[2].bits.uop.prs3_busy connect slots_14.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[14].wakeup_ports[2].bits.uop.prs2_busy connect slots_14.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[14].wakeup_ports[2].bits.uop.prs1_busy connect slots_14.io.wakeup_ports[2].bits.uop.ppred, issue_slots[14].wakeup_ports[2].bits.uop.ppred connect slots_14.io.wakeup_ports[2].bits.uop.prs3, issue_slots[14].wakeup_ports[2].bits.uop.prs3 connect slots_14.io.wakeup_ports[2].bits.uop.prs2, issue_slots[14].wakeup_ports[2].bits.uop.prs2 connect slots_14.io.wakeup_ports[2].bits.uop.prs1, issue_slots[14].wakeup_ports[2].bits.uop.prs1 connect slots_14.io.wakeup_ports[2].bits.uop.pdst, issue_slots[14].wakeup_ports[2].bits.uop.pdst connect slots_14.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[14].wakeup_ports[2].bits.uop.rxq_idx connect slots_14.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[14].wakeup_ports[2].bits.uop.stq_idx connect slots_14.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[14].wakeup_ports[2].bits.uop.ldq_idx connect slots_14.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[14].wakeup_ports[2].bits.uop.rob_idx connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.vec connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.wflags connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.div connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.fma connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.toint connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.fromint connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.wen connect slots_14.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.ldst connect slots_14.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[14].wakeup_ports[2].bits.uop.op2_sel connect slots_14.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[14].wakeup_ports[2].bits.uop.op1_sel connect slots_14.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[14].wakeup_ports[2].bits.uop.imm_packed connect slots_14.io.wakeup_ports[2].bits.uop.pimm, issue_slots[14].wakeup_ports[2].bits.uop.pimm connect slots_14.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[14].wakeup_ports[2].bits.uop.imm_sel connect slots_14.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[14].wakeup_ports[2].bits.uop.imm_rename connect slots_14.io.wakeup_ports[2].bits.uop.taken, issue_slots[14].wakeup_ports[2].bits.uop.taken connect slots_14.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[14].wakeup_ports[2].bits.uop.pc_lob connect slots_14.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[14].wakeup_ports[2].bits.uop.edge_inst connect slots_14.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[14].wakeup_ports[2].bits.uop.ftq_idx connect slots_14.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[14].wakeup_ports[2].bits.uop.is_mov connect slots_14.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[14].wakeup_ports[2].bits.uop.is_rocc connect slots_14.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[14].wakeup_ports[2].bits.uop.is_sys_pc2epc connect slots_14.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[14].wakeup_ports[2].bits.uop.is_eret connect slots_14.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[14].wakeup_ports[2].bits.uop.is_amo connect slots_14.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[14].wakeup_ports[2].bits.uop.is_sfence connect slots_14.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[14].wakeup_ports[2].bits.uop.is_fencei connect slots_14.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[14].wakeup_ports[2].bits.uop.is_fence connect slots_14.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[14].wakeup_ports[2].bits.uop.is_sfb connect slots_14.io.wakeup_ports[2].bits.uop.br_type, issue_slots[14].wakeup_ports[2].bits.uop.br_type connect slots_14.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[14].wakeup_ports[2].bits.uop.br_tag connect slots_14.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[14].wakeup_ports[2].bits.uop.br_mask connect slots_14.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[14].wakeup_ports[2].bits.uop.dis_col_sel connect slots_14.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[14].wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect slots_14.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[14].wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect slots_14.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[14].wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect slots_14.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[14].wakeup_ports[2].bits.uop.iw_p2_speculative_child connect slots_14.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[14].wakeup_ports[2].bits.uop.iw_p1_speculative_child connect slots_14.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[14].wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect slots_14.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[14].wakeup_ports[2].bits.uop.iw_issued_partial_agen connect slots_14.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[14].wakeup_ports[2].bits.uop.iw_issued connect slots_14.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[14].wakeup_ports[2].bits.uop.fu_code[0] connect slots_14.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[14].wakeup_ports[2].bits.uop.fu_code[1] connect slots_14.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[14].wakeup_ports[2].bits.uop.fu_code[2] connect slots_14.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[14].wakeup_ports[2].bits.uop.fu_code[3] connect slots_14.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[14].wakeup_ports[2].bits.uop.fu_code[4] connect slots_14.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[14].wakeup_ports[2].bits.uop.fu_code[5] connect slots_14.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[14].wakeup_ports[2].bits.uop.fu_code[6] connect slots_14.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[14].wakeup_ports[2].bits.uop.fu_code[7] connect slots_14.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[14].wakeup_ports[2].bits.uop.fu_code[8] connect slots_14.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[14].wakeup_ports[2].bits.uop.fu_code[9] connect slots_14.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[14].wakeup_ports[2].bits.uop.iq_type[0] connect slots_14.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[14].wakeup_ports[2].bits.uop.iq_type[1] connect slots_14.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[14].wakeup_ports[2].bits.uop.iq_type[2] connect slots_14.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[14].wakeup_ports[2].bits.uop.iq_type[3] connect slots_14.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[14].wakeup_ports[2].bits.uop.debug_pc connect slots_14.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[14].wakeup_ports[2].bits.uop.is_rvc connect slots_14.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[14].wakeup_ports[2].bits.uop.debug_inst connect slots_14.io.wakeup_ports[2].bits.uop.inst, issue_slots[14].wakeup_ports[2].bits.uop.inst connect slots_14.io.wakeup_ports[2].valid, issue_slots[14].wakeup_ports[2].valid connect slots_14.io.wakeup_ports[3].bits.rebusy, issue_slots[14].wakeup_ports[3].bits.rebusy connect slots_14.io.wakeup_ports[3].bits.speculative_mask, issue_slots[14].wakeup_ports[3].bits.speculative_mask connect slots_14.io.wakeup_ports[3].bits.bypassable, issue_slots[14].wakeup_ports[3].bits.bypassable connect slots_14.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[14].wakeup_ports[3].bits.uop.debug_tsrc connect slots_14.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[14].wakeup_ports[3].bits.uop.debug_fsrc connect slots_14.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[14].wakeup_ports[3].bits.uop.bp_xcpt_if connect slots_14.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[14].wakeup_ports[3].bits.uop.bp_debug_if connect slots_14.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[14].wakeup_ports[3].bits.uop.xcpt_ma_if connect slots_14.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[14].wakeup_ports[3].bits.uop.xcpt_ae_if connect slots_14.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[14].wakeup_ports[3].bits.uop.xcpt_pf_if connect slots_14.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[14].wakeup_ports[3].bits.uop.fp_typ connect slots_14.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[14].wakeup_ports[3].bits.uop.fp_rm connect slots_14.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[14].wakeup_ports[3].bits.uop.fp_val connect slots_14.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[14].wakeup_ports[3].bits.uop.fcn_op connect slots_14.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[14].wakeup_ports[3].bits.uop.fcn_dw connect slots_14.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[14].wakeup_ports[3].bits.uop.frs3_en connect slots_14.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[14].wakeup_ports[3].bits.uop.lrs2_rtype connect slots_14.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[14].wakeup_ports[3].bits.uop.lrs1_rtype connect slots_14.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[14].wakeup_ports[3].bits.uop.dst_rtype connect slots_14.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[14].wakeup_ports[3].bits.uop.lrs3 connect slots_14.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[14].wakeup_ports[3].bits.uop.lrs2 connect slots_14.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[14].wakeup_ports[3].bits.uop.lrs1 connect slots_14.io.wakeup_ports[3].bits.uop.ldst, issue_slots[14].wakeup_ports[3].bits.uop.ldst connect slots_14.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[14].wakeup_ports[3].bits.uop.ldst_is_rs1 connect slots_14.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[14].wakeup_ports[3].bits.uop.csr_cmd connect slots_14.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[14].wakeup_ports[3].bits.uop.flush_on_commit connect slots_14.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[14].wakeup_ports[3].bits.uop.is_unique connect slots_14.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[14].wakeup_ports[3].bits.uop.uses_stq connect slots_14.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[14].wakeup_ports[3].bits.uop.uses_ldq connect slots_14.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[14].wakeup_ports[3].bits.uop.mem_signed connect slots_14.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[14].wakeup_ports[3].bits.uop.mem_size connect slots_14.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[14].wakeup_ports[3].bits.uop.mem_cmd connect slots_14.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[14].wakeup_ports[3].bits.uop.exc_cause connect slots_14.io.wakeup_ports[3].bits.uop.exception, issue_slots[14].wakeup_ports[3].bits.uop.exception connect slots_14.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[14].wakeup_ports[3].bits.uop.stale_pdst connect slots_14.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[14].wakeup_ports[3].bits.uop.ppred_busy connect slots_14.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[14].wakeup_ports[3].bits.uop.prs3_busy connect slots_14.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[14].wakeup_ports[3].bits.uop.prs2_busy connect slots_14.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[14].wakeup_ports[3].bits.uop.prs1_busy connect slots_14.io.wakeup_ports[3].bits.uop.ppred, issue_slots[14].wakeup_ports[3].bits.uop.ppred connect slots_14.io.wakeup_ports[3].bits.uop.prs3, issue_slots[14].wakeup_ports[3].bits.uop.prs3 connect slots_14.io.wakeup_ports[3].bits.uop.prs2, issue_slots[14].wakeup_ports[3].bits.uop.prs2 connect slots_14.io.wakeup_ports[3].bits.uop.prs1, issue_slots[14].wakeup_ports[3].bits.uop.prs1 connect slots_14.io.wakeup_ports[3].bits.uop.pdst, issue_slots[14].wakeup_ports[3].bits.uop.pdst connect slots_14.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[14].wakeup_ports[3].bits.uop.rxq_idx connect slots_14.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[14].wakeup_ports[3].bits.uop.stq_idx connect slots_14.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[14].wakeup_ports[3].bits.uop.ldq_idx connect slots_14.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[14].wakeup_ports[3].bits.uop.rob_idx connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.vec connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.wflags connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.div connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.fma connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.toint connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.fromint connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.wen connect slots_14.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.ldst connect slots_14.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[14].wakeup_ports[3].bits.uop.op2_sel connect slots_14.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[14].wakeup_ports[3].bits.uop.op1_sel connect slots_14.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[14].wakeup_ports[3].bits.uop.imm_packed connect slots_14.io.wakeup_ports[3].bits.uop.pimm, issue_slots[14].wakeup_ports[3].bits.uop.pimm connect slots_14.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[14].wakeup_ports[3].bits.uop.imm_sel connect slots_14.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[14].wakeup_ports[3].bits.uop.imm_rename connect slots_14.io.wakeup_ports[3].bits.uop.taken, issue_slots[14].wakeup_ports[3].bits.uop.taken connect slots_14.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[14].wakeup_ports[3].bits.uop.pc_lob connect slots_14.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[14].wakeup_ports[3].bits.uop.edge_inst connect slots_14.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[14].wakeup_ports[3].bits.uop.ftq_idx connect slots_14.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[14].wakeup_ports[3].bits.uop.is_mov connect slots_14.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[14].wakeup_ports[3].bits.uop.is_rocc connect slots_14.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[14].wakeup_ports[3].bits.uop.is_sys_pc2epc connect slots_14.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[14].wakeup_ports[3].bits.uop.is_eret connect slots_14.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[14].wakeup_ports[3].bits.uop.is_amo connect slots_14.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[14].wakeup_ports[3].bits.uop.is_sfence connect slots_14.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[14].wakeup_ports[3].bits.uop.is_fencei connect slots_14.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[14].wakeup_ports[3].bits.uop.is_fence connect slots_14.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[14].wakeup_ports[3].bits.uop.is_sfb connect slots_14.io.wakeup_ports[3].bits.uop.br_type, issue_slots[14].wakeup_ports[3].bits.uop.br_type connect slots_14.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[14].wakeup_ports[3].bits.uop.br_tag connect slots_14.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[14].wakeup_ports[3].bits.uop.br_mask connect slots_14.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[14].wakeup_ports[3].bits.uop.dis_col_sel connect slots_14.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[14].wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect slots_14.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[14].wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect slots_14.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[14].wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect slots_14.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[14].wakeup_ports[3].bits.uop.iw_p2_speculative_child connect slots_14.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[14].wakeup_ports[3].bits.uop.iw_p1_speculative_child connect slots_14.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[14].wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect slots_14.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[14].wakeup_ports[3].bits.uop.iw_issued_partial_agen connect slots_14.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[14].wakeup_ports[3].bits.uop.iw_issued connect slots_14.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[14].wakeup_ports[3].bits.uop.fu_code[0] connect slots_14.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[14].wakeup_ports[3].bits.uop.fu_code[1] connect slots_14.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[14].wakeup_ports[3].bits.uop.fu_code[2] connect slots_14.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[14].wakeup_ports[3].bits.uop.fu_code[3] connect slots_14.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[14].wakeup_ports[3].bits.uop.fu_code[4] connect slots_14.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[14].wakeup_ports[3].bits.uop.fu_code[5] connect slots_14.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[14].wakeup_ports[3].bits.uop.fu_code[6] connect slots_14.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[14].wakeup_ports[3].bits.uop.fu_code[7] connect slots_14.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[14].wakeup_ports[3].bits.uop.fu_code[8] connect slots_14.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[14].wakeup_ports[3].bits.uop.fu_code[9] connect slots_14.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[14].wakeup_ports[3].bits.uop.iq_type[0] connect slots_14.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[14].wakeup_ports[3].bits.uop.iq_type[1] connect slots_14.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[14].wakeup_ports[3].bits.uop.iq_type[2] connect slots_14.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[14].wakeup_ports[3].bits.uop.iq_type[3] connect slots_14.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[14].wakeup_ports[3].bits.uop.debug_pc connect slots_14.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[14].wakeup_ports[3].bits.uop.is_rvc connect slots_14.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[14].wakeup_ports[3].bits.uop.debug_inst connect slots_14.io.wakeup_ports[3].bits.uop.inst, issue_slots[14].wakeup_ports[3].bits.uop.inst connect slots_14.io.wakeup_ports[3].valid, issue_slots[14].wakeup_ports[3].valid connect slots_14.io.wakeup_ports[4].bits.rebusy, issue_slots[14].wakeup_ports[4].bits.rebusy connect slots_14.io.wakeup_ports[4].bits.speculative_mask, issue_slots[14].wakeup_ports[4].bits.speculative_mask connect slots_14.io.wakeup_ports[4].bits.bypassable, issue_slots[14].wakeup_ports[4].bits.bypassable connect slots_14.io.wakeup_ports[4].bits.uop.debug_tsrc, issue_slots[14].wakeup_ports[4].bits.uop.debug_tsrc connect slots_14.io.wakeup_ports[4].bits.uop.debug_fsrc, issue_slots[14].wakeup_ports[4].bits.uop.debug_fsrc connect slots_14.io.wakeup_ports[4].bits.uop.bp_xcpt_if, issue_slots[14].wakeup_ports[4].bits.uop.bp_xcpt_if connect slots_14.io.wakeup_ports[4].bits.uop.bp_debug_if, issue_slots[14].wakeup_ports[4].bits.uop.bp_debug_if connect slots_14.io.wakeup_ports[4].bits.uop.xcpt_ma_if, issue_slots[14].wakeup_ports[4].bits.uop.xcpt_ma_if connect slots_14.io.wakeup_ports[4].bits.uop.xcpt_ae_if, issue_slots[14].wakeup_ports[4].bits.uop.xcpt_ae_if connect slots_14.io.wakeup_ports[4].bits.uop.xcpt_pf_if, issue_slots[14].wakeup_ports[4].bits.uop.xcpt_pf_if connect slots_14.io.wakeup_ports[4].bits.uop.fp_typ, issue_slots[14].wakeup_ports[4].bits.uop.fp_typ connect slots_14.io.wakeup_ports[4].bits.uop.fp_rm, issue_slots[14].wakeup_ports[4].bits.uop.fp_rm connect slots_14.io.wakeup_ports[4].bits.uop.fp_val, issue_slots[14].wakeup_ports[4].bits.uop.fp_val connect slots_14.io.wakeup_ports[4].bits.uop.fcn_op, issue_slots[14].wakeup_ports[4].bits.uop.fcn_op connect slots_14.io.wakeup_ports[4].bits.uop.fcn_dw, issue_slots[14].wakeup_ports[4].bits.uop.fcn_dw connect slots_14.io.wakeup_ports[4].bits.uop.frs3_en, issue_slots[14].wakeup_ports[4].bits.uop.frs3_en connect slots_14.io.wakeup_ports[4].bits.uop.lrs2_rtype, issue_slots[14].wakeup_ports[4].bits.uop.lrs2_rtype connect slots_14.io.wakeup_ports[4].bits.uop.lrs1_rtype, issue_slots[14].wakeup_ports[4].bits.uop.lrs1_rtype connect slots_14.io.wakeup_ports[4].bits.uop.dst_rtype, issue_slots[14].wakeup_ports[4].bits.uop.dst_rtype connect slots_14.io.wakeup_ports[4].bits.uop.lrs3, issue_slots[14].wakeup_ports[4].bits.uop.lrs3 connect slots_14.io.wakeup_ports[4].bits.uop.lrs2, issue_slots[14].wakeup_ports[4].bits.uop.lrs2 connect slots_14.io.wakeup_ports[4].bits.uop.lrs1, issue_slots[14].wakeup_ports[4].bits.uop.lrs1 connect slots_14.io.wakeup_ports[4].bits.uop.ldst, issue_slots[14].wakeup_ports[4].bits.uop.ldst connect slots_14.io.wakeup_ports[4].bits.uop.ldst_is_rs1, issue_slots[14].wakeup_ports[4].bits.uop.ldst_is_rs1 connect slots_14.io.wakeup_ports[4].bits.uop.csr_cmd, issue_slots[14].wakeup_ports[4].bits.uop.csr_cmd connect slots_14.io.wakeup_ports[4].bits.uop.flush_on_commit, issue_slots[14].wakeup_ports[4].bits.uop.flush_on_commit connect slots_14.io.wakeup_ports[4].bits.uop.is_unique, issue_slots[14].wakeup_ports[4].bits.uop.is_unique connect slots_14.io.wakeup_ports[4].bits.uop.uses_stq, issue_slots[14].wakeup_ports[4].bits.uop.uses_stq connect slots_14.io.wakeup_ports[4].bits.uop.uses_ldq, issue_slots[14].wakeup_ports[4].bits.uop.uses_ldq connect slots_14.io.wakeup_ports[4].bits.uop.mem_signed, issue_slots[14].wakeup_ports[4].bits.uop.mem_signed connect slots_14.io.wakeup_ports[4].bits.uop.mem_size, issue_slots[14].wakeup_ports[4].bits.uop.mem_size connect slots_14.io.wakeup_ports[4].bits.uop.mem_cmd, issue_slots[14].wakeup_ports[4].bits.uop.mem_cmd connect slots_14.io.wakeup_ports[4].bits.uop.exc_cause, issue_slots[14].wakeup_ports[4].bits.uop.exc_cause connect slots_14.io.wakeup_ports[4].bits.uop.exception, issue_slots[14].wakeup_ports[4].bits.uop.exception connect slots_14.io.wakeup_ports[4].bits.uop.stale_pdst, issue_slots[14].wakeup_ports[4].bits.uop.stale_pdst connect slots_14.io.wakeup_ports[4].bits.uop.ppred_busy, issue_slots[14].wakeup_ports[4].bits.uop.ppred_busy connect slots_14.io.wakeup_ports[4].bits.uop.prs3_busy, issue_slots[14].wakeup_ports[4].bits.uop.prs3_busy connect slots_14.io.wakeup_ports[4].bits.uop.prs2_busy, issue_slots[14].wakeup_ports[4].bits.uop.prs2_busy connect slots_14.io.wakeup_ports[4].bits.uop.prs1_busy, issue_slots[14].wakeup_ports[4].bits.uop.prs1_busy connect slots_14.io.wakeup_ports[4].bits.uop.ppred, issue_slots[14].wakeup_ports[4].bits.uop.ppred connect slots_14.io.wakeup_ports[4].bits.uop.prs3, issue_slots[14].wakeup_ports[4].bits.uop.prs3 connect slots_14.io.wakeup_ports[4].bits.uop.prs2, issue_slots[14].wakeup_ports[4].bits.uop.prs2 connect slots_14.io.wakeup_ports[4].bits.uop.prs1, issue_slots[14].wakeup_ports[4].bits.uop.prs1 connect slots_14.io.wakeup_ports[4].bits.uop.pdst, issue_slots[14].wakeup_ports[4].bits.uop.pdst connect slots_14.io.wakeup_ports[4].bits.uop.rxq_idx, issue_slots[14].wakeup_ports[4].bits.uop.rxq_idx connect slots_14.io.wakeup_ports[4].bits.uop.stq_idx, issue_slots[14].wakeup_ports[4].bits.uop.stq_idx connect slots_14.io.wakeup_ports[4].bits.uop.ldq_idx, issue_slots[14].wakeup_ports[4].bits.uop.ldq_idx connect slots_14.io.wakeup_ports[4].bits.uop.rob_idx, issue_slots[14].wakeup_ports[4].bits.uop.rob_idx connect slots_14.io.wakeup_ports[4].bits.uop.fp_ctrl.vec, issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.vec connect slots_14.io.wakeup_ports[4].bits.uop.fp_ctrl.wflags, issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.wflags connect slots_14.io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt, issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect slots_14.io.wakeup_ports[4].bits.uop.fp_ctrl.div, issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.div connect slots_14.io.wakeup_ports[4].bits.uop.fp_ctrl.fma, issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.fma connect slots_14.io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect slots_14.io.wakeup_ports[4].bits.uop.fp_ctrl.toint, issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.toint connect slots_14.io.wakeup_ports[4].bits.uop.fp_ctrl.fromint, issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.fromint connect slots_14.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect slots_14.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect slots_14.io.wakeup_ports[4].bits.uop.fp_ctrl.swap23, issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect slots_14.io.wakeup_ports[4].bits.uop.fp_ctrl.swap12, issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect slots_14.io.wakeup_ports[4].bits.uop.fp_ctrl.ren3, issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect slots_14.io.wakeup_ports[4].bits.uop.fp_ctrl.ren2, issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect slots_14.io.wakeup_ports[4].bits.uop.fp_ctrl.ren1, issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect slots_14.io.wakeup_ports[4].bits.uop.fp_ctrl.wen, issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.wen connect slots_14.io.wakeup_ports[4].bits.uop.fp_ctrl.ldst, issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.ldst connect slots_14.io.wakeup_ports[4].bits.uop.op2_sel, issue_slots[14].wakeup_ports[4].bits.uop.op2_sel connect slots_14.io.wakeup_ports[4].bits.uop.op1_sel, issue_slots[14].wakeup_ports[4].bits.uop.op1_sel connect slots_14.io.wakeup_ports[4].bits.uop.imm_packed, issue_slots[14].wakeup_ports[4].bits.uop.imm_packed connect slots_14.io.wakeup_ports[4].bits.uop.pimm, issue_slots[14].wakeup_ports[4].bits.uop.pimm connect slots_14.io.wakeup_ports[4].bits.uop.imm_sel, issue_slots[14].wakeup_ports[4].bits.uop.imm_sel connect slots_14.io.wakeup_ports[4].bits.uop.imm_rename, issue_slots[14].wakeup_ports[4].bits.uop.imm_rename connect slots_14.io.wakeup_ports[4].bits.uop.taken, issue_slots[14].wakeup_ports[4].bits.uop.taken connect slots_14.io.wakeup_ports[4].bits.uop.pc_lob, issue_slots[14].wakeup_ports[4].bits.uop.pc_lob connect slots_14.io.wakeup_ports[4].bits.uop.edge_inst, issue_slots[14].wakeup_ports[4].bits.uop.edge_inst connect slots_14.io.wakeup_ports[4].bits.uop.ftq_idx, issue_slots[14].wakeup_ports[4].bits.uop.ftq_idx connect slots_14.io.wakeup_ports[4].bits.uop.is_mov, issue_slots[14].wakeup_ports[4].bits.uop.is_mov connect slots_14.io.wakeup_ports[4].bits.uop.is_rocc, issue_slots[14].wakeup_ports[4].bits.uop.is_rocc connect slots_14.io.wakeup_ports[4].bits.uop.is_sys_pc2epc, issue_slots[14].wakeup_ports[4].bits.uop.is_sys_pc2epc connect slots_14.io.wakeup_ports[4].bits.uop.is_eret, issue_slots[14].wakeup_ports[4].bits.uop.is_eret connect slots_14.io.wakeup_ports[4].bits.uop.is_amo, issue_slots[14].wakeup_ports[4].bits.uop.is_amo connect slots_14.io.wakeup_ports[4].bits.uop.is_sfence, issue_slots[14].wakeup_ports[4].bits.uop.is_sfence connect slots_14.io.wakeup_ports[4].bits.uop.is_fencei, issue_slots[14].wakeup_ports[4].bits.uop.is_fencei connect slots_14.io.wakeup_ports[4].bits.uop.is_fence, issue_slots[14].wakeup_ports[4].bits.uop.is_fence connect slots_14.io.wakeup_ports[4].bits.uop.is_sfb, issue_slots[14].wakeup_ports[4].bits.uop.is_sfb connect slots_14.io.wakeup_ports[4].bits.uop.br_type, issue_slots[14].wakeup_ports[4].bits.uop.br_type connect slots_14.io.wakeup_ports[4].bits.uop.br_tag, issue_slots[14].wakeup_ports[4].bits.uop.br_tag connect slots_14.io.wakeup_ports[4].bits.uop.br_mask, issue_slots[14].wakeup_ports[4].bits.uop.br_mask connect slots_14.io.wakeup_ports[4].bits.uop.dis_col_sel, issue_slots[14].wakeup_ports[4].bits.uop.dis_col_sel connect slots_14.io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint, issue_slots[14].wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect slots_14.io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint, issue_slots[14].wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect slots_14.io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint, issue_slots[14].wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect slots_14.io.wakeup_ports[4].bits.uop.iw_p2_speculative_child, issue_slots[14].wakeup_ports[4].bits.uop.iw_p2_speculative_child connect slots_14.io.wakeup_ports[4].bits.uop.iw_p1_speculative_child, issue_slots[14].wakeup_ports[4].bits.uop.iw_p1_speculative_child connect slots_14.io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen, issue_slots[14].wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect slots_14.io.wakeup_ports[4].bits.uop.iw_issued_partial_agen, issue_slots[14].wakeup_ports[4].bits.uop.iw_issued_partial_agen connect slots_14.io.wakeup_ports[4].bits.uop.iw_issued, issue_slots[14].wakeup_ports[4].bits.uop.iw_issued connect slots_14.io.wakeup_ports[4].bits.uop.fu_code[0], issue_slots[14].wakeup_ports[4].bits.uop.fu_code[0] connect slots_14.io.wakeup_ports[4].bits.uop.fu_code[1], issue_slots[14].wakeup_ports[4].bits.uop.fu_code[1] connect slots_14.io.wakeup_ports[4].bits.uop.fu_code[2], issue_slots[14].wakeup_ports[4].bits.uop.fu_code[2] connect slots_14.io.wakeup_ports[4].bits.uop.fu_code[3], issue_slots[14].wakeup_ports[4].bits.uop.fu_code[3] connect slots_14.io.wakeup_ports[4].bits.uop.fu_code[4], issue_slots[14].wakeup_ports[4].bits.uop.fu_code[4] connect slots_14.io.wakeup_ports[4].bits.uop.fu_code[5], issue_slots[14].wakeup_ports[4].bits.uop.fu_code[5] connect slots_14.io.wakeup_ports[4].bits.uop.fu_code[6], issue_slots[14].wakeup_ports[4].bits.uop.fu_code[6] connect slots_14.io.wakeup_ports[4].bits.uop.fu_code[7], issue_slots[14].wakeup_ports[4].bits.uop.fu_code[7] connect slots_14.io.wakeup_ports[4].bits.uop.fu_code[8], issue_slots[14].wakeup_ports[4].bits.uop.fu_code[8] connect slots_14.io.wakeup_ports[4].bits.uop.fu_code[9], issue_slots[14].wakeup_ports[4].bits.uop.fu_code[9] connect slots_14.io.wakeup_ports[4].bits.uop.iq_type[0], issue_slots[14].wakeup_ports[4].bits.uop.iq_type[0] connect slots_14.io.wakeup_ports[4].bits.uop.iq_type[1], issue_slots[14].wakeup_ports[4].bits.uop.iq_type[1] connect slots_14.io.wakeup_ports[4].bits.uop.iq_type[2], issue_slots[14].wakeup_ports[4].bits.uop.iq_type[2] connect slots_14.io.wakeup_ports[4].bits.uop.iq_type[3], issue_slots[14].wakeup_ports[4].bits.uop.iq_type[3] connect slots_14.io.wakeup_ports[4].bits.uop.debug_pc, issue_slots[14].wakeup_ports[4].bits.uop.debug_pc connect slots_14.io.wakeup_ports[4].bits.uop.is_rvc, issue_slots[14].wakeup_ports[4].bits.uop.is_rvc connect slots_14.io.wakeup_ports[4].bits.uop.debug_inst, issue_slots[14].wakeup_ports[4].bits.uop.debug_inst connect slots_14.io.wakeup_ports[4].bits.uop.inst, issue_slots[14].wakeup_ports[4].bits.uop.inst connect slots_14.io.wakeup_ports[4].valid, issue_slots[14].wakeup_ports[4].valid connect slots_14.io.squash_grant, issue_slots[14].squash_grant connect slots_14.io.clear, issue_slots[14].clear connect slots_14.io.kill, issue_slots[14].kill connect slots_14.io.brupdate.b2.target_offset, issue_slots[14].brupdate.b2.target_offset connect slots_14.io.brupdate.b2.jalr_target, issue_slots[14].brupdate.b2.jalr_target connect slots_14.io.brupdate.b2.pc_sel, issue_slots[14].brupdate.b2.pc_sel connect slots_14.io.brupdate.b2.cfi_type, issue_slots[14].brupdate.b2.cfi_type connect slots_14.io.brupdate.b2.taken, issue_slots[14].brupdate.b2.taken connect slots_14.io.brupdate.b2.mispredict, issue_slots[14].brupdate.b2.mispredict connect slots_14.io.brupdate.b2.uop.debug_tsrc, issue_slots[14].brupdate.b2.uop.debug_tsrc connect slots_14.io.brupdate.b2.uop.debug_fsrc, issue_slots[14].brupdate.b2.uop.debug_fsrc connect slots_14.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[14].brupdate.b2.uop.bp_xcpt_if connect slots_14.io.brupdate.b2.uop.bp_debug_if, issue_slots[14].brupdate.b2.uop.bp_debug_if connect slots_14.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[14].brupdate.b2.uop.xcpt_ma_if connect slots_14.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[14].brupdate.b2.uop.xcpt_ae_if connect slots_14.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[14].brupdate.b2.uop.xcpt_pf_if connect slots_14.io.brupdate.b2.uop.fp_typ, issue_slots[14].brupdate.b2.uop.fp_typ connect slots_14.io.brupdate.b2.uop.fp_rm, issue_slots[14].brupdate.b2.uop.fp_rm connect slots_14.io.brupdate.b2.uop.fp_val, issue_slots[14].brupdate.b2.uop.fp_val connect slots_14.io.brupdate.b2.uop.fcn_op, issue_slots[14].brupdate.b2.uop.fcn_op connect slots_14.io.brupdate.b2.uop.fcn_dw, issue_slots[14].brupdate.b2.uop.fcn_dw connect slots_14.io.brupdate.b2.uop.frs3_en, issue_slots[14].brupdate.b2.uop.frs3_en connect slots_14.io.brupdate.b2.uop.lrs2_rtype, issue_slots[14].brupdate.b2.uop.lrs2_rtype connect slots_14.io.brupdate.b2.uop.lrs1_rtype, issue_slots[14].brupdate.b2.uop.lrs1_rtype connect slots_14.io.brupdate.b2.uop.dst_rtype, issue_slots[14].brupdate.b2.uop.dst_rtype connect slots_14.io.brupdate.b2.uop.lrs3, issue_slots[14].brupdate.b2.uop.lrs3 connect slots_14.io.brupdate.b2.uop.lrs2, issue_slots[14].brupdate.b2.uop.lrs2 connect slots_14.io.brupdate.b2.uop.lrs1, issue_slots[14].brupdate.b2.uop.lrs1 connect slots_14.io.brupdate.b2.uop.ldst, issue_slots[14].brupdate.b2.uop.ldst connect slots_14.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[14].brupdate.b2.uop.ldst_is_rs1 connect slots_14.io.brupdate.b2.uop.csr_cmd, issue_slots[14].brupdate.b2.uop.csr_cmd connect slots_14.io.brupdate.b2.uop.flush_on_commit, issue_slots[14].brupdate.b2.uop.flush_on_commit connect slots_14.io.brupdate.b2.uop.is_unique, issue_slots[14].brupdate.b2.uop.is_unique connect slots_14.io.brupdate.b2.uop.uses_stq, issue_slots[14].brupdate.b2.uop.uses_stq connect slots_14.io.brupdate.b2.uop.uses_ldq, issue_slots[14].brupdate.b2.uop.uses_ldq connect slots_14.io.brupdate.b2.uop.mem_signed, issue_slots[14].brupdate.b2.uop.mem_signed connect slots_14.io.brupdate.b2.uop.mem_size, issue_slots[14].brupdate.b2.uop.mem_size connect slots_14.io.brupdate.b2.uop.mem_cmd, issue_slots[14].brupdate.b2.uop.mem_cmd connect slots_14.io.brupdate.b2.uop.exc_cause, issue_slots[14].brupdate.b2.uop.exc_cause connect slots_14.io.brupdate.b2.uop.exception, issue_slots[14].brupdate.b2.uop.exception connect slots_14.io.brupdate.b2.uop.stale_pdst, issue_slots[14].brupdate.b2.uop.stale_pdst connect slots_14.io.brupdate.b2.uop.ppred_busy, issue_slots[14].brupdate.b2.uop.ppred_busy connect slots_14.io.brupdate.b2.uop.prs3_busy, issue_slots[14].brupdate.b2.uop.prs3_busy connect slots_14.io.brupdate.b2.uop.prs2_busy, issue_slots[14].brupdate.b2.uop.prs2_busy connect slots_14.io.brupdate.b2.uop.prs1_busy, issue_slots[14].brupdate.b2.uop.prs1_busy connect slots_14.io.brupdate.b2.uop.ppred, issue_slots[14].brupdate.b2.uop.ppred connect slots_14.io.brupdate.b2.uop.prs3, issue_slots[14].brupdate.b2.uop.prs3 connect slots_14.io.brupdate.b2.uop.prs2, issue_slots[14].brupdate.b2.uop.prs2 connect slots_14.io.brupdate.b2.uop.prs1, issue_slots[14].brupdate.b2.uop.prs1 connect slots_14.io.brupdate.b2.uop.pdst, issue_slots[14].brupdate.b2.uop.pdst connect slots_14.io.brupdate.b2.uop.rxq_idx, issue_slots[14].brupdate.b2.uop.rxq_idx connect slots_14.io.brupdate.b2.uop.stq_idx, issue_slots[14].brupdate.b2.uop.stq_idx connect slots_14.io.brupdate.b2.uop.ldq_idx, issue_slots[14].brupdate.b2.uop.ldq_idx connect slots_14.io.brupdate.b2.uop.rob_idx, issue_slots[14].brupdate.b2.uop.rob_idx connect slots_14.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[14].brupdate.b2.uop.fp_ctrl.vec connect slots_14.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[14].brupdate.b2.uop.fp_ctrl.wflags connect slots_14.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[14].brupdate.b2.uop.fp_ctrl.sqrt connect slots_14.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[14].brupdate.b2.uop.fp_ctrl.div connect slots_14.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[14].brupdate.b2.uop.fp_ctrl.fma connect slots_14.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[14].brupdate.b2.uop.fp_ctrl.fastpipe connect slots_14.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[14].brupdate.b2.uop.fp_ctrl.toint connect slots_14.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[14].brupdate.b2.uop.fp_ctrl.fromint connect slots_14.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[14].brupdate.b2.uop.fp_ctrl.typeTagOut connect slots_14.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[14].brupdate.b2.uop.fp_ctrl.typeTagIn connect slots_14.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[14].brupdate.b2.uop.fp_ctrl.swap23 connect slots_14.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[14].brupdate.b2.uop.fp_ctrl.swap12 connect slots_14.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[14].brupdate.b2.uop.fp_ctrl.ren3 connect slots_14.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[14].brupdate.b2.uop.fp_ctrl.ren2 connect slots_14.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[14].brupdate.b2.uop.fp_ctrl.ren1 connect slots_14.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[14].brupdate.b2.uop.fp_ctrl.wen connect slots_14.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[14].brupdate.b2.uop.fp_ctrl.ldst connect slots_14.io.brupdate.b2.uop.op2_sel, issue_slots[14].brupdate.b2.uop.op2_sel connect slots_14.io.brupdate.b2.uop.op1_sel, issue_slots[14].brupdate.b2.uop.op1_sel connect slots_14.io.brupdate.b2.uop.imm_packed, issue_slots[14].brupdate.b2.uop.imm_packed connect slots_14.io.brupdate.b2.uop.pimm, issue_slots[14].brupdate.b2.uop.pimm connect slots_14.io.brupdate.b2.uop.imm_sel, issue_slots[14].brupdate.b2.uop.imm_sel connect slots_14.io.brupdate.b2.uop.imm_rename, issue_slots[14].brupdate.b2.uop.imm_rename connect slots_14.io.brupdate.b2.uop.taken, issue_slots[14].brupdate.b2.uop.taken connect slots_14.io.brupdate.b2.uop.pc_lob, issue_slots[14].brupdate.b2.uop.pc_lob connect slots_14.io.brupdate.b2.uop.edge_inst, issue_slots[14].brupdate.b2.uop.edge_inst connect slots_14.io.brupdate.b2.uop.ftq_idx, issue_slots[14].brupdate.b2.uop.ftq_idx connect slots_14.io.brupdate.b2.uop.is_mov, issue_slots[14].brupdate.b2.uop.is_mov connect slots_14.io.brupdate.b2.uop.is_rocc, issue_slots[14].brupdate.b2.uop.is_rocc connect slots_14.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[14].brupdate.b2.uop.is_sys_pc2epc connect slots_14.io.brupdate.b2.uop.is_eret, issue_slots[14].brupdate.b2.uop.is_eret connect slots_14.io.brupdate.b2.uop.is_amo, issue_slots[14].brupdate.b2.uop.is_amo connect slots_14.io.brupdate.b2.uop.is_sfence, issue_slots[14].brupdate.b2.uop.is_sfence connect slots_14.io.brupdate.b2.uop.is_fencei, issue_slots[14].brupdate.b2.uop.is_fencei connect slots_14.io.brupdate.b2.uop.is_fence, issue_slots[14].brupdate.b2.uop.is_fence connect slots_14.io.brupdate.b2.uop.is_sfb, issue_slots[14].brupdate.b2.uop.is_sfb connect slots_14.io.brupdate.b2.uop.br_type, issue_slots[14].brupdate.b2.uop.br_type connect slots_14.io.brupdate.b2.uop.br_tag, issue_slots[14].brupdate.b2.uop.br_tag connect slots_14.io.brupdate.b2.uop.br_mask, issue_slots[14].brupdate.b2.uop.br_mask connect slots_14.io.brupdate.b2.uop.dis_col_sel, issue_slots[14].brupdate.b2.uop.dis_col_sel connect slots_14.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[14].brupdate.b2.uop.iw_p3_bypass_hint connect slots_14.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[14].brupdate.b2.uop.iw_p2_bypass_hint connect slots_14.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[14].brupdate.b2.uop.iw_p1_bypass_hint connect slots_14.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[14].brupdate.b2.uop.iw_p2_speculative_child connect slots_14.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[14].brupdate.b2.uop.iw_p1_speculative_child connect slots_14.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[14].brupdate.b2.uop.iw_issued_partial_dgen connect slots_14.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[14].brupdate.b2.uop.iw_issued_partial_agen connect slots_14.io.brupdate.b2.uop.iw_issued, issue_slots[14].brupdate.b2.uop.iw_issued connect slots_14.io.brupdate.b2.uop.fu_code[0], issue_slots[14].brupdate.b2.uop.fu_code[0] connect slots_14.io.brupdate.b2.uop.fu_code[1], issue_slots[14].brupdate.b2.uop.fu_code[1] connect slots_14.io.brupdate.b2.uop.fu_code[2], issue_slots[14].brupdate.b2.uop.fu_code[2] connect slots_14.io.brupdate.b2.uop.fu_code[3], issue_slots[14].brupdate.b2.uop.fu_code[3] connect slots_14.io.brupdate.b2.uop.fu_code[4], issue_slots[14].brupdate.b2.uop.fu_code[4] connect slots_14.io.brupdate.b2.uop.fu_code[5], issue_slots[14].brupdate.b2.uop.fu_code[5] connect slots_14.io.brupdate.b2.uop.fu_code[6], issue_slots[14].brupdate.b2.uop.fu_code[6] connect slots_14.io.brupdate.b2.uop.fu_code[7], issue_slots[14].brupdate.b2.uop.fu_code[7] connect slots_14.io.brupdate.b2.uop.fu_code[8], issue_slots[14].brupdate.b2.uop.fu_code[8] connect slots_14.io.brupdate.b2.uop.fu_code[9], issue_slots[14].brupdate.b2.uop.fu_code[9] connect slots_14.io.brupdate.b2.uop.iq_type[0], issue_slots[14].brupdate.b2.uop.iq_type[0] connect slots_14.io.brupdate.b2.uop.iq_type[1], issue_slots[14].brupdate.b2.uop.iq_type[1] connect slots_14.io.brupdate.b2.uop.iq_type[2], issue_slots[14].brupdate.b2.uop.iq_type[2] connect slots_14.io.brupdate.b2.uop.iq_type[3], issue_slots[14].brupdate.b2.uop.iq_type[3] connect slots_14.io.brupdate.b2.uop.debug_pc, issue_slots[14].brupdate.b2.uop.debug_pc connect slots_14.io.brupdate.b2.uop.is_rvc, issue_slots[14].brupdate.b2.uop.is_rvc connect slots_14.io.brupdate.b2.uop.debug_inst, issue_slots[14].brupdate.b2.uop.debug_inst connect slots_14.io.brupdate.b2.uop.inst, issue_slots[14].brupdate.b2.uop.inst connect slots_14.io.brupdate.b1.mispredict_mask, issue_slots[14].brupdate.b1.mispredict_mask connect slots_14.io.brupdate.b1.resolve_mask, issue_slots[14].brupdate.b1.resolve_mask connect issue_slots[14].out_uop.debug_tsrc, slots_14.io.out_uop.debug_tsrc connect issue_slots[14].out_uop.debug_fsrc, slots_14.io.out_uop.debug_fsrc connect issue_slots[14].out_uop.bp_xcpt_if, slots_14.io.out_uop.bp_xcpt_if connect issue_slots[14].out_uop.bp_debug_if, slots_14.io.out_uop.bp_debug_if connect issue_slots[14].out_uop.xcpt_ma_if, slots_14.io.out_uop.xcpt_ma_if connect issue_slots[14].out_uop.xcpt_ae_if, slots_14.io.out_uop.xcpt_ae_if connect issue_slots[14].out_uop.xcpt_pf_if, slots_14.io.out_uop.xcpt_pf_if connect issue_slots[14].out_uop.fp_typ, slots_14.io.out_uop.fp_typ connect issue_slots[14].out_uop.fp_rm, slots_14.io.out_uop.fp_rm connect issue_slots[14].out_uop.fp_val, slots_14.io.out_uop.fp_val connect issue_slots[14].out_uop.fcn_op, slots_14.io.out_uop.fcn_op connect issue_slots[14].out_uop.fcn_dw, slots_14.io.out_uop.fcn_dw connect issue_slots[14].out_uop.frs3_en, slots_14.io.out_uop.frs3_en connect issue_slots[14].out_uop.lrs2_rtype, slots_14.io.out_uop.lrs2_rtype connect issue_slots[14].out_uop.lrs1_rtype, slots_14.io.out_uop.lrs1_rtype connect issue_slots[14].out_uop.dst_rtype, slots_14.io.out_uop.dst_rtype connect issue_slots[14].out_uop.lrs3, slots_14.io.out_uop.lrs3 connect issue_slots[14].out_uop.lrs2, slots_14.io.out_uop.lrs2 connect issue_slots[14].out_uop.lrs1, slots_14.io.out_uop.lrs1 connect issue_slots[14].out_uop.ldst, slots_14.io.out_uop.ldst connect issue_slots[14].out_uop.ldst_is_rs1, slots_14.io.out_uop.ldst_is_rs1 connect issue_slots[14].out_uop.csr_cmd, slots_14.io.out_uop.csr_cmd connect issue_slots[14].out_uop.flush_on_commit, slots_14.io.out_uop.flush_on_commit connect issue_slots[14].out_uop.is_unique, slots_14.io.out_uop.is_unique connect issue_slots[14].out_uop.uses_stq, slots_14.io.out_uop.uses_stq connect issue_slots[14].out_uop.uses_ldq, slots_14.io.out_uop.uses_ldq connect issue_slots[14].out_uop.mem_signed, slots_14.io.out_uop.mem_signed connect issue_slots[14].out_uop.mem_size, slots_14.io.out_uop.mem_size connect issue_slots[14].out_uop.mem_cmd, slots_14.io.out_uop.mem_cmd connect issue_slots[14].out_uop.exc_cause, slots_14.io.out_uop.exc_cause connect issue_slots[14].out_uop.exception, slots_14.io.out_uop.exception connect issue_slots[14].out_uop.stale_pdst, slots_14.io.out_uop.stale_pdst connect issue_slots[14].out_uop.ppred_busy, slots_14.io.out_uop.ppred_busy connect issue_slots[14].out_uop.prs3_busy, slots_14.io.out_uop.prs3_busy connect issue_slots[14].out_uop.prs2_busy, slots_14.io.out_uop.prs2_busy connect issue_slots[14].out_uop.prs1_busy, slots_14.io.out_uop.prs1_busy connect issue_slots[14].out_uop.ppred, slots_14.io.out_uop.ppred connect issue_slots[14].out_uop.prs3, slots_14.io.out_uop.prs3 connect issue_slots[14].out_uop.prs2, slots_14.io.out_uop.prs2 connect issue_slots[14].out_uop.prs1, slots_14.io.out_uop.prs1 connect issue_slots[14].out_uop.pdst, slots_14.io.out_uop.pdst connect issue_slots[14].out_uop.rxq_idx, slots_14.io.out_uop.rxq_idx connect issue_slots[14].out_uop.stq_idx, slots_14.io.out_uop.stq_idx connect issue_slots[14].out_uop.ldq_idx, slots_14.io.out_uop.ldq_idx connect issue_slots[14].out_uop.rob_idx, slots_14.io.out_uop.rob_idx connect issue_slots[14].out_uop.fp_ctrl.vec, slots_14.io.out_uop.fp_ctrl.vec connect issue_slots[14].out_uop.fp_ctrl.wflags, slots_14.io.out_uop.fp_ctrl.wflags connect issue_slots[14].out_uop.fp_ctrl.sqrt, slots_14.io.out_uop.fp_ctrl.sqrt connect issue_slots[14].out_uop.fp_ctrl.div, slots_14.io.out_uop.fp_ctrl.div connect issue_slots[14].out_uop.fp_ctrl.fma, slots_14.io.out_uop.fp_ctrl.fma connect issue_slots[14].out_uop.fp_ctrl.fastpipe, slots_14.io.out_uop.fp_ctrl.fastpipe connect issue_slots[14].out_uop.fp_ctrl.toint, slots_14.io.out_uop.fp_ctrl.toint connect issue_slots[14].out_uop.fp_ctrl.fromint, slots_14.io.out_uop.fp_ctrl.fromint connect issue_slots[14].out_uop.fp_ctrl.typeTagOut, slots_14.io.out_uop.fp_ctrl.typeTagOut connect issue_slots[14].out_uop.fp_ctrl.typeTagIn, slots_14.io.out_uop.fp_ctrl.typeTagIn connect issue_slots[14].out_uop.fp_ctrl.swap23, slots_14.io.out_uop.fp_ctrl.swap23 connect issue_slots[14].out_uop.fp_ctrl.swap12, slots_14.io.out_uop.fp_ctrl.swap12 connect issue_slots[14].out_uop.fp_ctrl.ren3, slots_14.io.out_uop.fp_ctrl.ren3 connect issue_slots[14].out_uop.fp_ctrl.ren2, slots_14.io.out_uop.fp_ctrl.ren2 connect issue_slots[14].out_uop.fp_ctrl.ren1, slots_14.io.out_uop.fp_ctrl.ren1 connect issue_slots[14].out_uop.fp_ctrl.wen, slots_14.io.out_uop.fp_ctrl.wen connect issue_slots[14].out_uop.fp_ctrl.ldst, slots_14.io.out_uop.fp_ctrl.ldst connect issue_slots[14].out_uop.op2_sel, slots_14.io.out_uop.op2_sel connect issue_slots[14].out_uop.op1_sel, slots_14.io.out_uop.op1_sel connect issue_slots[14].out_uop.imm_packed, slots_14.io.out_uop.imm_packed connect issue_slots[14].out_uop.pimm, slots_14.io.out_uop.pimm connect issue_slots[14].out_uop.imm_sel, slots_14.io.out_uop.imm_sel connect issue_slots[14].out_uop.imm_rename, slots_14.io.out_uop.imm_rename connect issue_slots[14].out_uop.taken, slots_14.io.out_uop.taken connect issue_slots[14].out_uop.pc_lob, slots_14.io.out_uop.pc_lob connect issue_slots[14].out_uop.edge_inst, slots_14.io.out_uop.edge_inst connect issue_slots[14].out_uop.ftq_idx, slots_14.io.out_uop.ftq_idx connect issue_slots[14].out_uop.is_mov, slots_14.io.out_uop.is_mov connect issue_slots[14].out_uop.is_rocc, slots_14.io.out_uop.is_rocc connect issue_slots[14].out_uop.is_sys_pc2epc, slots_14.io.out_uop.is_sys_pc2epc connect issue_slots[14].out_uop.is_eret, slots_14.io.out_uop.is_eret connect issue_slots[14].out_uop.is_amo, slots_14.io.out_uop.is_amo connect issue_slots[14].out_uop.is_sfence, slots_14.io.out_uop.is_sfence connect issue_slots[14].out_uop.is_fencei, slots_14.io.out_uop.is_fencei connect issue_slots[14].out_uop.is_fence, slots_14.io.out_uop.is_fence connect issue_slots[14].out_uop.is_sfb, slots_14.io.out_uop.is_sfb connect issue_slots[14].out_uop.br_type, slots_14.io.out_uop.br_type connect issue_slots[14].out_uop.br_tag, slots_14.io.out_uop.br_tag connect issue_slots[14].out_uop.br_mask, slots_14.io.out_uop.br_mask connect issue_slots[14].out_uop.dis_col_sel, slots_14.io.out_uop.dis_col_sel connect issue_slots[14].out_uop.iw_p3_bypass_hint, slots_14.io.out_uop.iw_p3_bypass_hint connect issue_slots[14].out_uop.iw_p2_bypass_hint, slots_14.io.out_uop.iw_p2_bypass_hint connect issue_slots[14].out_uop.iw_p1_bypass_hint, slots_14.io.out_uop.iw_p1_bypass_hint connect issue_slots[14].out_uop.iw_p2_speculative_child, slots_14.io.out_uop.iw_p2_speculative_child connect issue_slots[14].out_uop.iw_p1_speculative_child, slots_14.io.out_uop.iw_p1_speculative_child connect issue_slots[14].out_uop.iw_issued_partial_dgen, slots_14.io.out_uop.iw_issued_partial_dgen connect issue_slots[14].out_uop.iw_issued_partial_agen, slots_14.io.out_uop.iw_issued_partial_agen connect issue_slots[14].out_uop.iw_issued, slots_14.io.out_uop.iw_issued connect issue_slots[14].out_uop.fu_code[0], slots_14.io.out_uop.fu_code[0] connect issue_slots[14].out_uop.fu_code[1], slots_14.io.out_uop.fu_code[1] connect issue_slots[14].out_uop.fu_code[2], slots_14.io.out_uop.fu_code[2] connect issue_slots[14].out_uop.fu_code[3], slots_14.io.out_uop.fu_code[3] connect issue_slots[14].out_uop.fu_code[4], slots_14.io.out_uop.fu_code[4] connect issue_slots[14].out_uop.fu_code[5], slots_14.io.out_uop.fu_code[5] connect issue_slots[14].out_uop.fu_code[6], slots_14.io.out_uop.fu_code[6] connect issue_slots[14].out_uop.fu_code[7], slots_14.io.out_uop.fu_code[7] connect issue_slots[14].out_uop.fu_code[8], slots_14.io.out_uop.fu_code[8] connect issue_slots[14].out_uop.fu_code[9], slots_14.io.out_uop.fu_code[9] connect issue_slots[14].out_uop.iq_type[0], slots_14.io.out_uop.iq_type[0] connect issue_slots[14].out_uop.iq_type[1], slots_14.io.out_uop.iq_type[1] connect issue_slots[14].out_uop.iq_type[2], slots_14.io.out_uop.iq_type[2] connect issue_slots[14].out_uop.iq_type[3], slots_14.io.out_uop.iq_type[3] connect issue_slots[14].out_uop.debug_pc, slots_14.io.out_uop.debug_pc connect issue_slots[14].out_uop.is_rvc, slots_14.io.out_uop.is_rvc connect issue_slots[14].out_uop.debug_inst, slots_14.io.out_uop.debug_inst connect issue_slots[14].out_uop.inst, slots_14.io.out_uop.inst connect slots_14.io.in_uop.bits.debug_tsrc, issue_slots[14].in_uop.bits.debug_tsrc connect slots_14.io.in_uop.bits.debug_fsrc, issue_slots[14].in_uop.bits.debug_fsrc connect slots_14.io.in_uop.bits.bp_xcpt_if, issue_slots[14].in_uop.bits.bp_xcpt_if connect slots_14.io.in_uop.bits.bp_debug_if, issue_slots[14].in_uop.bits.bp_debug_if connect slots_14.io.in_uop.bits.xcpt_ma_if, issue_slots[14].in_uop.bits.xcpt_ma_if connect slots_14.io.in_uop.bits.xcpt_ae_if, issue_slots[14].in_uop.bits.xcpt_ae_if connect slots_14.io.in_uop.bits.xcpt_pf_if, issue_slots[14].in_uop.bits.xcpt_pf_if connect slots_14.io.in_uop.bits.fp_typ, issue_slots[14].in_uop.bits.fp_typ connect slots_14.io.in_uop.bits.fp_rm, issue_slots[14].in_uop.bits.fp_rm connect slots_14.io.in_uop.bits.fp_val, issue_slots[14].in_uop.bits.fp_val connect slots_14.io.in_uop.bits.fcn_op, issue_slots[14].in_uop.bits.fcn_op connect slots_14.io.in_uop.bits.fcn_dw, issue_slots[14].in_uop.bits.fcn_dw connect slots_14.io.in_uop.bits.frs3_en, issue_slots[14].in_uop.bits.frs3_en connect slots_14.io.in_uop.bits.lrs2_rtype, issue_slots[14].in_uop.bits.lrs2_rtype connect slots_14.io.in_uop.bits.lrs1_rtype, issue_slots[14].in_uop.bits.lrs1_rtype connect slots_14.io.in_uop.bits.dst_rtype, issue_slots[14].in_uop.bits.dst_rtype connect slots_14.io.in_uop.bits.lrs3, issue_slots[14].in_uop.bits.lrs3 connect slots_14.io.in_uop.bits.lrs2, issue_slots[14].in_uop.bits.lrs2 connect slots_14.io.in_uop.bits.lrs1, issue_slots[14].in_uop.bits.lrs1 connect slots_14.io.in_uop.bits.ldst, issue_slots[14].in_uop.bits.ldst connect slots_14.io.in_uop.bits.ldst_is_rs1, issue_slots[14].in_uop.bits.ldst_is_rs1 connect slots_14.io.in_uop.bits.csr_cmd, issue_slots[14].in_uop.bits.csr_cmd connect slots_14.io.in_uop.bits.flush_on_commit, issue_slots[14].in_uop.bits.flush_on_commit connect slots_14.io.in_uop.bits.is_unique, issue_slots[14].in_uop.bits.is_unique connect slots_14.io.in_uop.bits.uses_stq, issue_slots[14].in_uop.bits.uses_stq connect slots_14.io.in_uop.bits.uses_ldq, issue_slots[14].in_uop.bits.uses_ldq connect slots_14.io.in_uop.bits.mem_signed, issue_slots[14].in_uop.bits.mem_signed connect slots_14.io.in_uop.bits.mem_size, issue_slots[14].in_uop.bits.mem_size connect slots_14.io.in_uop.bits.mem_cmd, issue_slots[14].in_uop.bits.mem_cmd connect slots_14.io.in_uop.bits.exc_cause, issue_slots[14].in_uop.bits.exc_cause connect slots_14.io.in_uop.bits.exception, issue_slots[14].in_uop.bits.exception connect slots_14.io.in_uop.bits.stale_pdst, issue_slots[14].in_uop.bits.stale_pdst connect slots_14.io.in_uop.bits.ppred_busy, issue_slots[14].in_uop.bits.ppred_busy connect slots_14.io.in_uop.bits.prs3_busy, issue_slots[14].in_uop.bits.prs3_busy connect slots_14.io.in_uop.bits.prs2_busy, issue_slots[14].in_uop.bits.prs2_busy connect slots_14.io.in_uop.bits.prs1_busy, issue_slots[14].in_uop.bits.prs1_busy connect slots_14.io.in_uop.bits.ppred, issue_slots[14].in_uop.bits.ppred connect slots_14.io.in_uop.bits.prs3, issue_slots[14].in_uop.bits.prs3 connect slots_14.io.in_uop.bits.prs2, issue_slots[14].in_uop.bits.prs2 connect slots_14.io.in_uop.bits.prs1, issue_slots[14].in_uop.bits.prs1 connect slots_14.io.in_uop.bits.pdst, issue_slots[14].in_uop.bits.pdst connect slots_14.io.in_uop.bits.rxq_idx, issue_slots[14].in_uop.bits.rxq_idx connect slots_14.io.in_uop.bits.stq_idx, issue_slots[14].in_uop.bits.stq_idx connect slots_14.io.in_uop.bits.ldq_idx, issue_slots[14].in_uop.bits.ldq_idx connect slots_14.io.in_uop.bits.rob_idx, issue_slots[14].in_uop.bits.rob_idx connect slots_14.io.in_uop.bits.fp_ctrl.vec, issue_slots[14].in_uop.bits.fp_ctrl.vec connect slots_14.io.in_uop.bits.fp_ctrl.wflags, issue_slots[14].in_uop.bits.fp_ctrl.wflags connect slots_14.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[14].in_uop.bits.fp_ctrl.sqrt connect slots_14.io.in_uop.bits.fp_ctrl.div, issue_slots[14].in_uop.bits.fp_ctrl.div connect slots_14.io.in_uop.bits.fp_ctrl.fma, issue_slots[14].in_uop.bits.fp_ctrl.fma connect slots_14.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[14].in_uop.bits.fp_ctrl.fastpipe connect slots_14.io.in_uop.bits.fp_ctrl.toint, issue_slots[14].in_uop.bits.fp_ctrl.toint connect slots_14.io.in_uop.bits.fp_ctrl.fromint, issue_slots[14].in_uop.bits.fp_ctrl.fromint connect slots_14.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[14].in_uop.bits.fp_ctrl.typeTagOut connect slots_14.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[14].in_uop.bits.fp_ctrl.typeTagIn connect slots_14.io.in_uop.bits.fp_ctrl.swap23, issue_slots[14].in_uop.bits.fp_ctrl.swap23 connect slots_14.io.in_uop.bits.fp_ctrl.swap12, issue_slots[14].in_uop.bits.fp_ctrl.swap12 connect slots_14.io.in_uop.bits.fp_ctrl.ren3, issue_slots[14].in_uop.bits.fp_ctrl.ren3 connect slots_14.io.in_uop.bits.fp_ctrl.ren2, issue_slots[14].in_uop.bits.fp_ctrl.ren2 connect slots_14.io.in_uop.bits.fp_ctrl.ren1, issue_slots[14].in_uop.bits.fp_ctrl.ren1 connect slots_14.io.in_uop.bits.fp_ctrl.wen, issue_slots[14].in_uop.bits.fp_ctrl.wen connect slots_14.io.in_uop.bits.fp_ctrl.ldst, issue_slots[14].in_uop.bits.fp_ctrl.ldst connect slots_14.io.in_uop.bits.op2_sel, issue_slots[14].in_uop.bits.op2_sel connect slots_14.io.in_uop.bits.op1_sel, issue_slots[14].in_uop.bits.op1_sel connect slots_14.io.in_uop.bits.imm_packed, issue_slots[14].in_uop.bits.imm_packed connect slots_14.io.in_uop.bits.pimm, issue_slots[14].in_uop.bits.pimm connect slots_14.io.in_uop.bits.imm_sel, issue_slots[14].in_uop.bits.imm_sel connect slots_14.io.in_uop.bits.imm_rename, issue_slots[14].in_uop.bits.imm_rename connect slots_14.io.in_uop.bits.taken, issue_slots[14].in_uop.bits.taken connect slots_14.io.in_uop.bits.pc_lob, issue_slots[14].in_uop.bits.pc_lob connect slots_14.io.in_uop.bits.edge_inst, issue_slots[14].in_uop.bits.edge_inst connect slots_14.io.in_uop.bits.ftq_idx, issue_slots[14].in_uop.bits.ftq_idx connect slots_14.io.in_uop.bits.is_mov, issue_slots[14].in_uop.bits.is_mov connect slots_14.io.in_uop.bits.is_rocc, issue_slots[14].in_uop.bits.is_rocc connect slots_14.io.in_uop.bits.is_sys_pc2epc, issue_slots[14].in_uop.bits.is_sys_pc2epc connect slots_14.io.in_uop.bits.is_eret, issue_slots[14].in_uop.bits.is_eret connect slots_14.io.in_uop.bits.is_amo, issue_slots[14].in_uop.bits.is_amo connect slots_14.io.in_uop.bits.is_sfence, issue_slots[14].in_uop.bits.is_sfence connect slots_14.io.in_uop.bits.is_fencei, issue_slots[14].in_uop.bits.is_fencei connect slots_14.io.in_uop.bits.is_fence, issue_slots[14].in_uop.bits.is_fence connect slots_14.io.in_uop.bits.is_sfb, issue_slots[14].in_uop.bits.is_sfb connect slots_14.io.in_uop.bits.br_type, issue_slots[14].in_uop.bits.br_type connect slots_14.io.in_uop.bits.br_tag, issue_slots[14].in_uop.bits.br_tag connect slots_14.io.in_uop.bits.br_mask, issue_slots[14].in_uop.bits.br_mask connect slots_14.io.in_uop.bits.dis_col_sel, issue_slots[14].in_uop.bits.dis_col_sel connect slots_14.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[14].in_uop.bits.iw_p3_bypass_hint connect slots_14.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[14].in_uop.bits.iw_p2_bypass_hint connect slots_14.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[14].in_uop.bits.iw_p1_bypass_hint connect slots_14.io.in_uop.bits.iw_p2_speculative_child, issue_slots[14].in_uop.bits.iw_p2_speculative_child connect slots_14.io.in_uop.bits.iw_p1_speculative_child, issue_slots[14].in_uop.bits.iw_p1_speculative_child connect slots_14.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[14].in_uop.bits.iw_issued_partial_dgen connect slots_14.io.in_uop.bits.iw_issued_partial_agen, issue_slots[14].in_uop.bits.iw_issued_partial_agen connect slots_14.io.in_uop.bits.iw_issued, issue_slots[14].in_uop.bits.iw_issued connect slots_14.io.in_uop.bits.fu_code[0], issue_slots[14].in_uop.bits.fu_code[0] connect slots_14.io.in_uop.bits.fu_code[1], issue_slots[14].in_uop.bits.fu_code[1] connect slots_14.io.in_uop.bits.fu_code[2], issue_slots[14].in_uop.bits.fu_code[2] connect slots_14.io.in_uop.bits.fu_code[3], issue_slots[14].in_uop.bits.fu_code[3] connect slots_14.io.in_uop.bits.fu_code[4], issue_slots[14].in_uop.bits.fu_code[4] connect slots_14.io.in_uop.bits.fu_code[5], issue_slots[14].in_uop.bits.fu_code[5] connect slots_14.io.in_uop.bits.fu_code[6], issue_slots[14].in_uop.bits.fu_code[6] connect slots_14.io.in_uop.bits.fu_code[7], issue_slots[14].in_uop.bits.fu_code[7] connect slots_14.io.in_uop.bits.fu_code[8], issue_slots[14].in_uop.bits.fu_code[8] connect slots_14.io.in_uop.bits.fu_code[9], issue_slots[14].in_uop.bits.fu_code[9] connect slots_14.io.in_uop.bits.iq_type[0], issue_slots[14].in_uop.bits.iq_type[0] connect slots_14.io.in_uop.bits.iq_type[1], issue_slots[14].in_uop.bits.iq_type[1] connect slots_14.io.in_uop.bits.iq_type[2], issue_slots[14].in_uop.bits.iq_type[2] connect slots_14.io.in_uop.bits.iq_type[3], issue_slots[14].in_uop.bits.iq_type[3] connect slots_14.io.in_uop.bits.debug_pc, issue_slots[14].in_uop.bits.debug_pc connect slots_14.io.in_uop.bits.is_rvc, issue_slots[14].in_uop.bits.is_rvc connect slots_14.io.in_uop.bits.debug_inst, issue_slots[14].in_uop.bits.debug_inst connect slots_14.io.in_uop.bits.inst, issue_slots[14].in_uop.bits.inst connect slots_14.io.in_uop.valid, issue_slots[14].in_uop.valid connect issue_slots[14].iss_uop.debug_tsrc, slots_14.io.iss_uop.debug_tsrc connect issue_slots[14].iss_uop.debug_fsrc, slots_14.io.iss_uop.debug_fsrc connect issue_slots[14].iss_uop.bp_xcpt_if, slots_14.io.iss_uop.bp_xcpt_if connect issue_slots[14].iss_uop.bp_debug_if, slots_14.io.iss_uop.bp_debug_if connect issue_slots[14].iss_uop.xcpt_ma_if, slots_14.io.iss_uop.xcpt_ma_if connect issue_slots[14].iss_uop.xcpt_ae_if, slots_14.io.iss_uop.xcpt_ae_if connect issue_slots[14].iss_uop.xcpt_pf_if, slots_14.io.iss_uop.xcpt_pf_if connect issue_slots[14].iss_uop.fp_typ, slots_14.io.iss_uop.fp_typ connect issue_slots[14].iss_uop.fp_rm, slots_14.io.iss_uop.fp_rm connect issue_slots[14].iss_uop.fp_val, slots_14.io.iss_uop.fp_val connect issue_slots[14].iss_uop.fcn_op, slots_14.io.iss_uop.fcn_op connect issue_slots[14].iss_uop.fcn_dw, slots_14.io.iss_uop.fcn_dw connect issue_slots[14].iss_uop.frs3_en, slots_14.io.iss_uop.frs3_en connect issue_slots[14].iss_uop.lrs2_rtype, slots_14.io.iss_uop.lrs2_rtype connect issue_slots[14].iss_uop.lrs1_rtype, slots_14.io.iss_uop.lrs1_rtype connect issue_slots[14].iss_uop.dst_rtype, slots_14.io.iss_uop.dst_rtype connect issue_slots[14].iss_uop.lrs3, slots_14.io.iss_uop.lrs3 connect issue_slots[14].iss_uop.lrs2, slots_14.io.iss_uop.lrs2 connect issue_slots[14].iss_uop.lrs1, slots_14.io.iss_uop.lrs1 connect issue_slots[14].iss_uop.ldst, slots_14.io.iss_uop.ldst connect issue_slots[14].iss_uop.ldst_is_rs1, slots_14.io.iss_uop.ldst_is_rs1 connect issue_slots[14].iss_uop.csr_cmd, slots_14.io.iss_uop.csr_cmd connect issue_slots[14].iss_uop.flush_on_commit, slots_14.io.iss_uop.flush_on_commit connect issue_slots[14].iss_uop.is_unique, slots_14.io.iss_uop.is_unique connect issue_slots[14].iss_uop.uses_stq, slots_14.io.iss_uop.uses_stq connect issue_slots[14].iss_uop.uses_ldq, slots_14.io.iss_uop.uses_ldq connect issue_slots[14].iss_uop.mem_signed, slots_14.io.iss_uop.mem_signed connect issue_slots[14].iss_uop.mem_size, slots_14.io.iss_uop.mem_size connect issue_slots[14].iss_uop.mem_cmd, slots_14.io.iss_uop.mem_cmd connect issue_slots[14].iss_uop.exc_cause, slots_14.io.iss_uop.exc_cause connect issue_slots[14].iss_uop.exception, slots_14.io.iss_uop.exception connect issue_slots[14].iss_uop.stale_pdst, slots_14.io.iss_uop.stale_pdst connect issue_slots[14].iss_uop.ppred_busy, slots_14.io.iss_uop.ppred_busy connect issue_slots[14].iss_uop.prs3_busy, slots_14.io.iss_uop.prs3_busy connect issue_slots[14].iss_uop.prs2_busy, slots_14.io.iss_uop.prs2_busy connect issue_slots[14].iss_uop.prs1_busy, slots_14.io.iss_uop.prs1_busy connect issue_slots[14].iss_uop.ppred, slots_14.io.iss_uop.ppred connect issue_slots[14].iss_uop.prs3, slots_14.io.iss_uop.prs3 connect issue_slots[14].iss_uop.prs2, slots_14.io.iss_uop.prs2 connect issue_slots[14].iss_uop.prs1, slots_14.io.iss_uop.prs1 connect issue_slots[14].iss_uop.pdst, slots_14.io.iss_uop.pdst connect issue_slots[14].iss_uop.rxq_idx, slots_14.io.iss_uop.rxq_idx connect issue_slots[14].iss_uop.stq_idx, slots_14.io.iss_uop.stq_idx connect issue_slots[14].iss_uop.ldq_idx, slots_14.io.iss_uop.ldq_idx connect issue_slots[14].iss_uop.rob_idx, slots_14.io.iss_uop.rob_idx connect issue_slots[14].iss_uop.fp_ctrl.vec, slots_14.io.iss_uop.fp_ctrl.vec connect issue_slots[14].iss_uop.fp_ctrl.wflags, slots_14.io.iss_uop.fp_ctrl.wflags connect issue_slots[14].iss_uop.fp_ctrl.sqrt, slots_14.io.iss_uop.fp_ctrl.sqrt connect issue_slots[14].iss_uop.fp_ctrl.div, slots_14.io.iss_uop.fp_ctrl.div connect issue_slots[14].iss_uop.fp_ctrl.fma, slots_14.io.iss_uop.fp_ctrl.fma connect issue_slots[14].iss_uop.fp_ctrl.fastpipe, slots_14.io.iss_uop.fp_ctrl.fastpipe connect issue_slots[14].iss_uop.fp_ctrl.toint, slots_14.io.iss_uop.fp_ctrl.toint connect issue_slots[14].iss_uop.fp_ctrl.fromint, slots_14.io.iss_uop.fp_ctrl.fromint connect issue_slots[14].iss_uop.fp_ctrl.typeTagOut, slots_14.io.iss_uop.fp_ctrl.typeTagOut connect issue_slots[14].iss_uop.fp_ctrl.typeTagIn, slots_14.io.iss_uop.fp_ctrl.typeTagIn connect issue_slots[14].iss_uop.fp_ctrl.swap23, slots_14.io.iss_uop.fp_ctrl.swap23 connect issue_slots[14].iss_uop.fp_ctrl.swap12, slots_14.io.iss_uop.fp_ctrl.swap12 connect issue_slots[14].iss_uop.fp_ctrl.ren3, slots_14.io.iss_uop.fp_ctrl.ren3 connect issue_slots[14].iss_uop.fp_ctrl.ren2, slots_14.io.iss_uop.fp_ctrl.ren2 connect issue_slots[14].iss_uop.fp_ctrl.ren1, slots_14.io.iss_uop.fp_ctrl.ren1 connect issue_slots[14].iss_uop.fp_ctrl.wen, slots_14.io.iss_uop.fp_ctrl.wen connect issue_slots[14].iss_uop.fp_ctrl.ldst, slots_14.io.iss_uop.fp_ctrl.ldst connect issue_slots[14].iss_uop.op2_sel, slots_14.io.iss_uop.op2_sel connect issue_slots[14].iss_uop.op1_sel, slots_14.io.iss_uop.op1_sel connect issue_slots[14].iss_uop.imm_packed, slots_14.io.iss_uop.imm_packed connect issue_slots[14].iss_uop.pimm, slots_14.io.iss_uop.pimm connect issue_slots[14].iss_uop.imm_sel, slots_14.io.iss_uop.imm_sel connect issue_slots[14].iss_uop.imm_rename, slots_14.io.iss_uop.imm_rename connect issue_slots[14].iss_uop.taken, slots_14.io.iss_uop.taken connect issue_slots[14].iss_uop.pc_lob, slots_14.io.iss_uop.pc_lob connect issue_slots[14].iss_uop.edge_inst, slots_14.io.iss_uop.edge_inst connect issue_slots[14].iss_uop.ftq_idx, slots_14.io.iss_uop.ftq_idx connect issue_slots[14].iss_uop.is_mov, slots_14.io.iss_uop.is_mov connect issue_slots[14].iss_uop.is_rocc, slots_14.io.iss_uop.is_rocc connect issue_slots[14].iss_uop.is_sys_pc2epc, slots_14.io.iss_uop.is_sys_pc2epc connect issue_slots[14].iss_uop.is_eret, slots_14.io.iss_uop.is_eret connect issue_slots[14].iss_uop.is_amo, slots_14.io.iss_uop.is_amo connect issue_slots[14].iss_uop.is_sfence, slots_14.io.iss_uop.is_sfence connect issue_slots[14].iss_uop.is_fencei, slots_14.io.iss_uop.is_fencei connect issue_slots[14].iss_uop.is_fence, slots_14.io.iss_uop.is_fence connect issue_slots[14].iss_uop.is_sfb, slots_14.io.iss_uop.is_sfb connect issue_slots[14].iss_uop.br_type, slots_14.io.iss_uop.br_type connect issue_slots[14].iss_uop.br_tag, slots_14.io.iss_uop.br_tag connect issue_slots[14].iss_uop.br_mask, slots_14.io.iss_uop.br_mask connect issue_slots[14].iss_uop.dis_col_sel, slots_14.io.iss_uop.dis_col_sel connect issue_slots[14].iss_uop.iw_p3_bypass_hint, slots_14.io.iss_uop.iw_p3_bypass_hint connect issue_slots[14].iss_uop.iw_p2_bypass_hint, slots_14.io.iss_uop.iw_p2_bypass_hint connect issue_slots[14].iss_uop.iw_p1_bypass_hint, slots_14.io.iss_uop.iw_p1_bypass_hint connect issue_slots[14].iss_uop.iw_p2_speculative_child, slots_14.io.iss_uop.iw_p2_speculative_child connect issue_slots[14].iss_uop.iw_p1_speculative_child, slots_14.io.iss_uop.iw_p1_speculative_child connect issue_slots[14].iss_uop.iw_issued_partial_dgen, slots_14.io.iss_uop.iw_issued_partial_dgen connect issue_slots[14].iss_uop.iw_issued_partial_agen, slots_14.io.iss_uop.iw_issued_partial_agen connect issue_slots[14].iss_uop.iw_issued, slots_14.io.iss_uop.iw_issued connect issue_slots[14].iss_uop.fu_code[0], slots_14.io.iss_uop.fu_code[0] connect issue_slots[14].iss_uop.fu_code[1], slots_14.io.iss_uop.fu_code[1] connect issue_slots[14].iss_uop.fu_code[2], slots_14.io.iss_uop.fu_code[2] connect issue_slots[14].iss_uop.fu_code[3], slots_14.io.iss_uop.fu_code[3] connect issue_slots[14].iss_uop.fu_code[4], slots_14.io.iss_uop.fu_code[4] connect issue_slots[14].iss_uop.fu_code[5], slots_14.io.iss_uop.fu_code[5] connect issue_slots[14].iss_uop.fu_code[6], slots_14.io.iss_uop.fu_code[6] connect issue_slots[14].iss_uop.fu_code[7], slots_14.io.iss_uop.fu_code[7] connect issue_slots[14].iss_uop.fu_code[8], slots_14.io.iss_uop.fu_code[8] connect issue_slots[14].iss_uop.fu_code[9], slots_14.io.iss_uop.fu_code[9] connect issue_slots[14].iss_uop.iq_type[0], slots_14.io.iss_uop.iq_type[0] connect issue_slots[14].iss_uop.iq_type[1], slots_14.io.iss_uop.iq_type[1] connect issue_slots[14].iss_uop.iq_type[2], slots_14.io.iss_uop.iq_type[2] connect issue_slots[14].iss_uop.iq_type[3], slots_14.io.iss_uop.iq_type[3] connect issue_slots[14].iss_uop.debug_pc, slots_14.io.iss_uop.debug_pc connect issue_slots[14].iss_uop.is_rvc, slots_14.io.iss_uop.is_rvc connect issue_slots[14].iss_uop.debug_inst, slots_14.io.iss_uop.debug_inst connect issue_slots[14].iss_uop.inst, slots_14.io.iss_uop.inst connect slots_14.io.grant, issue_slots[14].grant connect issue_slots[14].request, slots_14.io.request connect issue_slots[14].will_be_valid, slots_14.io.will_be_valid connect issue_slots[14].valid, slots_14.io.valid connect slots_15.io.child_rebusys, issue_slots[15].child_rebusys connect slots_15.io.pred_wakeup_port.bits, issue_slots[15].pred_wakeup_port.bits connect slots_15.io.pred_wakeup_port.valid, issue_slots[15].pred_wakeup_port.valid connect slots_15.io.wakeup_ports[0].bits.rebusy, issue_slots[15].wakeup_ports[0].bits.rebusy connect slots_15.io.wakeup_ports[0].bits.speculative_mask, issue_slots[15].wakeup_ports[0].bits.speculative_mask connect slots_15.io.wakeup_ports[0].bits.bypassable, issue_slots[15].wakeup_ports[0].bits.bypassable connect slots_15.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[15].wakeup_ports[0].bits.uop.debug_tsrc connect slots_15.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[15].wakeup_ports[0].bits.uop.debug_fsrc connect slots_15.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[15].wakeup_ports[0].bits.uop.bp_xcpt_if connect slots_15.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[15].wakeup_ports[0].bits.uop.bp_debug_if connect slots_15.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[15].wakeup_ports[0].bits.uop.xcpt_ma_if connect slots_15.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[15].wakeup_ports[0].bits.uop.xcpt_ae_if connect slots_15.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[15].wakeup_ports[0].bits.uop.xcpt_pf_if connect slots_15.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[15].wakeup_ports[0].bits.uop.fp_typ connect slots_15.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[15].wakeup_ports[0].bits.uop.fp_rm connect slots_15.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[15].wakeup_ports[0].bits.uop.fp_val connect slots_15.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[15].wakeup_ports[0].bits.uop.fcn_op connect slots_15.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[15].wakeup_ports[0].bits.uop.fcn_dw connect slots_15.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[15].wakeup_ports[0].bits.uop.frs3_en connect slots_15.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[15].wakeup_ports[0].bits.uop.lrs2_rtype connect slots_15.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[15].wakeup_ports[0].bits.uop.lrs1_rtype connect slots_15.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[15].wakeup_ports[0].bits.uop.dst_rtype connect slots_15.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[15].wakeup_ports[0].bits.uop.lrs3 connect slots_15.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[15].wakeup_ports[0].bits.uop.lrs2 connect slots_15.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[15].wakeup_ports[0].bits.uop.lrs1 connect slots_15.io.wakeup_ports[0].bits.uop.ldst, issue_slots[15].wakeup_ports[0].bits.uop.ldst connect slots_15.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[15].wakeup_ports[0].bits.uop.ldst_is_rs1 connect slots_15.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[15].wakeup_ports[0].bits.uop.csr_cmd connect slots_15.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[15].wakeup_ports[0].bits.uop.flush_on_commit connect slots_15.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[15].wakeup_ports[0].bits.uop.is_unique connect slots_15.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[15].wakeup_ports[0].bits.uop.uses_stq connect slots_15.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[15].wakeup_ports[0].bits.uop.uses_ldq connect slots_15.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[15].wakeup_ports[0].bits.uop.mem_signed connect slots_15.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[15].wakeup_ports[0].bits.uop.mem_size connect slots_15.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[15].wakeup_ports[0].bits.uop.mem_cmd connect slots_15.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[15].wakeup_ports[0].bits.uop.exc_cause connect slots_15.io.wakeup_ports[0].bits.uop.exception, issue_slots[15].wakeup_ports[0].bits.uop.exception connect slots_15.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[15].wakeup_ports[0].bits.uop.stale_pdst connect slots_15.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[15].wakeup_ports[0].bits.uop.ppred_busy connect slots_15.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[15].wakeup_ports[0].bits.uop.prs3_busy connect slots_15.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[15].wakeup_ports[0].bits.uop.prs2_busy connect slots_15.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[15].wakeup_ports[0].bits.uop.prs1_busy connect slots_15.io.wakeup_ports[0].bits.uop.ppred, issue_slots[15].wakeup_ports[0].bits.uop.ppred connect slots_15.io.wakeup_ports[0].bits.uop.prs3, issue_slots[15].wakeup_ports[0].bits.uop.prs3 connect slots_15.io.wakeup_ports[0].bits.uop.prs2, issue_slots[15].wakeup_ports[0].bits.uop.prs2 connect slots_15.io.wakeup_ports[0].bits.uop.prs1, issue_slots[15].wakeup_ports[0].bits.uop.prs1 connect slots_15.io.wakeup_ports[0].bits.uop.pdst, issue_slots[15].wakeup_ports[0].bits.uop.pdst connect slots_15.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[15].wakeup_ports[0].bits.uop.rxq_idx connect slots_15.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[15].wakeup_ports[0].bits.uop.stq_idx connect slots_15.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[15].wakeup_ports[0].bits.uop.ldq_idx connect slots_15.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[15].wakeup_ports[0].bits.uop.rob_idx connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.vec connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.wflags connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.div connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.fma connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.toint connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.fromint connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.wen connect slots_15.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.ldst connect slots_15.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[15].wakeup_ports[0].bits.uop.op2_sel connect slots_15.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[15].wakeup_ports[0].bits.uop.op1_sel connect slots_15.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[15].wakeup_ports[0].bits.uop.imm_packed connect slots_15.io.wakeup_ports[0].bits.uop.pimm, issue_slots[15].wakeup_ports[0].bits.uop.pimm connect slots_15.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[15].wakeup_ports[0].bits.uop.imm_sel connect slots_15.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[15].wakeup_ports[0].bits.uop.imm_rename connect slots_15.io.wakeup_ports[0].bits.uop.taken, issue_slots[15].wakeup_ports[0].bits.uop.taken connect slots_15.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[15].wakeup_ports[0].bits.uop.pc_lob connect slots_15.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[15].wakeup_ports[0].bits.uop.edge_inst connect slots_15.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[15].wakeup_ports[0].bits.uop.ftq_idx connect slots_15.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[15].wakeup_ports[0].bits.uop.is_mov connect slots_15.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[15].wakeup_ports[0].bits.uop.is_rocc connect slots_15.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[15].wakeup_ports[0].bits.uop.is_sys_pc2epc connect slots_15.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[15].wakeup_ports[0].bits.uop.is_eret connect slots_15.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[15].wakeup_ports[0].bits.uop.is_amo connect slots_15.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[15].wakeup_ports[0].bits.uop.is_sfence connect slots_15.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[15].wakeup_ports[0].bits.uop.is_fencei connect slots_15.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[15].wakeup_ports[0].bits.uop.is_fence connect slots_15.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[15].wakeup_ports[0].bits.uop.is_sfb connect slots_15.io.wakeup_ports[0].bits.uop.br_type, issue_slots[15].wakeup_ports[0].bits.uop.br_type connect slots_15.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[15].wakeup_ports[0].bits.uop.br_tag connect slots_15.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[15].wakeup_ports[0].bits.uop.br_mask connect slots_15.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[15].wakeup_ports[0].bits.uop.dis_col_sel connect slots_15.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[15].wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect slots_15.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[15].wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect slots_15.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[15].wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect slots_15.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[15].wakeup_ports[0].bits.uop.iw_p2_speculative_child connect slots_15.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[15].wakeup_ports[0].bits.uop.iw_p1_speculative_child connect slots_15.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[15].wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect slots_15.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[15].wakeup_ports[0].bits.uop.iw_issued_partial_agen connect slots_15.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[15].wakeup_ports[0].bits.uop.iw_issued connect slots_15.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[15].wakeup_ports[0].bits.uop.fu_code[0] connect slots_15.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[15].wakeup_ports[0].bits.uop.fu_code[1] connect slots_15.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[15].wakeup_ports[0].bits.uop.fu_code[2] connect slots_15.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[15].wakeup_ports[0].bits.uop.fu_code[3] connect slots_15.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[15].wakeup_ports[0].bits.uop.fu_code[4] connect slots_15.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[15].wakeup_ports[0].bits.uop.fu_code[5] connect slots_15.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[15].wakeup_ports[0].bits.uop.fu_code[6] connect slots_15.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[15].wakeup_ports[0].bits.uop.fu_code[7] connect slots_15.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[15].wakeup_ports[0].bits.uop.fu_code[8] connect slots_15.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[15].wakeup_ports[0].bits.uop.fu_code[9] connect slots_15.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[15].wakeup_ports[0].bits.uop.iq_type[0] connect slots_15.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[15].wakeup_ports[0].bits.uop.iq_type[1] connect slots_15.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[15].wakeup_ports[0].bits.uop.iq_type[2] connect slots_15.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[15].wakeup_ports[0].bits.uop.iq_type[3] connect slots_15.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[15].wakeup_ports[0].bits.uop.debug_pc connect slots_15.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[15].wakeup_ports[0].bits.uop.is_rvc connect slots_15.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[15].wakeup_ports[0].bits.uop.debug_inst connect slots_15.io.wakeup_ports[0].bits.uop.inst, issue_slots[15].wakeup_ports[0].bits.uop.inst connect slots_15.io.wakeup_ports[0].valid, issue_slots[15].wakeup_ports[0].valid connect slots_15.io.wakeup_ports[1].bits.rebusy, issue_slots[15].wakeup_ports[1].bits.rebusy connect slots_15.io.wakeup_ports[1].bits.speculative_mask, issue_slots[15].wakeup_ports[1].bits.speculative_mask connect slots_15.io.wakeup_ports[1].bits.bypassable, issue_slots[15].wakeup_ports[1].bits.bypassable connect slots_15.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[15].wakeup_ports[1].bits.uop.debug_tsrc connect slots_15.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[15].wakeup_ports[1].bits.uop.debug_fsrc connect slots_15.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[15].wakeup_ports[1].bits.uop.bp_xcpt_if connect slots_15.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[15].wakeup_ports[1].bits.uop.bp_debug_if connect slots_15.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[15].wakeup_ports[1].bits.uop.xcpt_ma_if connect slots_15.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[15].wakeup_ports[1].bits.uop.xcpt_ae_if connect slots_15.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[15].wakeup_ports[1].bits.uop.xcpt_pf_if connect slots_15.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[15].wakeup_ports[1].bits.uop.fp_typ connect slots_15.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[15].wakeup_ports[1].bits.uop.fp_rm connect slots_15.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[15].wakeup_ports[1].bits.uop.fp_val connect slots_15.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[15].wakeup_ports[1].bits.uop.fcn_op connect slots_15.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[15].wakeup_ports[1].bits.uop.fcn_dw connect slots_15.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[15].wakeup_ports[1].bits.uop.frs3_en connect slots_15.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[15].wakeup_ports[1].bits.uop.lrs2_rtype connect slots_15.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[15].wakeup_ports[1].bits.uop.lrs1_rtype connect slots_15.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[15].wakeup_ports[1].bits.uop.dst_rtype connect slots_15.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[15].wakeup_ports[1].bits.uop.lrs3 connect slots_15.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[15].wakeup_ports[1].bits.uop.lrs2 connect slots_15.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[15].wakeup_ports[1].bits.uop.lrs1 connect slots_15.io.wakeup_ports[1].bits.uop.ldst, issue_slots[15].wakeup_ports[1].bits.uop.ldst connect slots_15.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[15].wakeup_ports[1].bits.uop.ldst_is_rs1 connect slots_15.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[15].wakeup_ports[1].bits.uop.csr_cmd connect slots_15.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[15].wakeup_ports[1].bits.uop.flush_on_commit connect slots_15.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[15].wakeup_ports[1].bits.uop.is_unique connect slots_15.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[15].wakeup_ports[1].bits.uop.uses_stq connect slots_15.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[15].wakeup_ports[1].bits.uop.uses_ldq connect slots_15.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[15].wakeup_ports[1].bits.uop.mem_signed connect slots_15.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[15].wakeup_ports[1].bits.uop.mem_size connect slots_15.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[15].wakeup_ports[1].bits.uop.mem_cmd connect slots_15.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[15].wakeup_ports[1].bits.uop.exc_cause connect slots_15.io.wakeup_ports[1].bits.uop.exception, issue_slots[15].wakeup_ports[1].bits.uop.exception connect slots_15.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[15].wakeup_ports[1].bits.uop.stale_pdst connect slots_15.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[15].wakeup_ports[1].bits.uop.ppred_busy connect slots_15.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[15].wakeup_ports[1].bits.uop.prs3_busy connect slots_15.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[15].wakeup_ports[1].bits.uop.prs2_busy connect slots_15.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[15].wakeup_ports[1].bits.uop.prs1_busy connect slots_15.io.wakeup_ports[1].bits.uop.ppred, issue_slots[15].wakeup_ports[1].bits.uop.ppred connect slots_15.io.wakeup_ports[1].bits.uop.prs3, issue_slots[15].wakeup_ports[1].bits.uop.prs3 connect slots_15.io.wakeup_ports[1].bits.uop.prs2, issue_slots[15].wakeup_ports[1].bits.uop.prs2 connect slots_15.io.wakeup_ports[1].bits.uop.prs1, issue_slots[15].wakeup_ports[1].bits.uop.prs1 connect slots_15.io.wakeup_ports[1].bits.uop.pdst, issue_slots[15].wakeup_ports[1].bits.uop.pdst connect slots_15.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[15].wakeup_ports[1].bits.uop.rxq_idx connect slots_15.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[15].wakeup_ports[1].bits.uop.stq_idx connect slots_15.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[15].wakeup_ports[1].bits.uop.ldq_idx connect slots_15.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[15].wakeup_ports[1].bits.uop.rob_idx connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.vec connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.wflags connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.div connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.fma connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.toint connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.fromint connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.wen connect slots_15.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.ldst connect slots_15.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[15].wakeup_ports[1].bits.uop.op2_sel connect slots_15.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[15].wakeup_ports[1].bits.uop.op1_sel connect slots_15.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[15].wakeup_ports[1].bits.uop.imm_packed connect slots_15.io.wakeup_ports[1].bits.uop.pimm, issue_slots[15].wakeup_ports[1].bits.uop.pimm connect slots_15.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[15].wakeup_ports[1].bits.uop.imm_sel connect slots_15.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[15].wakeup_ports[1].bits.uop.imm_rename connect slots_15.io.wakeup_ports[1].bits.uop.taken, issue_slots[15].wakeup_ports[1].bits.uop.taken connect slots_15.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[15].wakeup_ports[1].bits.uop.pc_lob connect slots_15.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[15].wakeup_ports[1].bits.uop.edge_inst connect slots_15.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[15].wakeup_ports[1].bits.uop.ftq_idx connect slots_15.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[15].wakeup_ports[1].bits.uop.is_mov connect slots_15.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[15].wakeup_ports[1].bits.uop.is_rocc connect slots_15.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[15].wakeup_ports[1].bits.uop.is_sys_pc2epc connect slots_15.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[15].wakeup_ports[1].bits.uop.is_eret connect slots_15.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[15].wakeup_ports[1].bits.uop.is_amo connect slots_15.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[15].wakeup_ports[1].bits.uop.is_sfence connect slots_15.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[15].wakeup_ports[1].bits.uop.is_fencei connect slots_15.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[15].wakeup_ports[1].bits.uop.is_fence connect slots_15.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[15].wakeup_ports[1].bits.uop.is_sfb connect slots_15.io.wakeup_ports[1].bits.uop.br_type, issue_slots[15].wakeup_ports[1].bits.uop.br_type connect slots_15.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[15].wakeup_ports[1].bits.uop.br_tag connect slots_15.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[15].wakeup_ports[1].bits.uop.br_mask connect slots_15.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[15].wakeup_ports[1].bits.uop.dis_col_sel connect slots_15.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[15].wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect slots_15.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[15].wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect slots_15.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[15].wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect slots_15.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[15].wakeup_ports[1].bits.uop.iw_p2_speculative_child connect slots_15.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[15].wakeup_ports[1].bits.uop.iw_p1_speculative_child connect slots_15.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[15].wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect slots_15.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[15].wakeup_ports[1].bits.uop.iw_issued_partial_agen connect slots_15.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[15].wakeup_ports[1].bits.uop.iw_issued connect slots_15.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[15].wakeup_ports[1].bits.uop.fu_code[0] connect slots_15.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[15].wakeup_ports[1].bits.uop.fu_code[1] connect slots_15.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[15].wakeup_ports[1].bits.uop.fu_code[2] connect slots_15.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[15].wakeup_ports[1].bits.uop.fu_code[3] connect slots_15.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[15].wakeup_ports[1].bits.uop.fu_code[4] connect slots_15.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[15].wakeup_ports[1].bits.uop.fu_code[5] connect slots_15.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[15].wakeup_ports[1].bits.uop.fu_code[6] connect slots_15.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[15].wakeup_ports[1].bits.uop.fu_code[7] connect slots_15.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[15].wakeup_ports[1].bits.uop.fu_code[8] connect slots_15.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[15].wakeup_ports[1].bits.uop.fu_code[9] connect slots_15.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[15].wakeup_ports[1].bits.uop.iq_type[0] connect slots_15.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[15].wakeup_ports[1].bits.uop.iq_type[1] connect slots_15.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[15].wakeup_ports[1].bits.uop.iq_type[2] connect slots_15.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[15].wakeup_ports[1].bits.uop.iq_type[3] connect slots_15.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[15].wakeup_ports[1].bits.uop.debug_pc connect slots_15.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[15].wakeup_ports[1].bits.uop.is_rvc connect slots_15.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[15].wakeup_ports[1].bits.uop.debug_inst connect slots_15.io.wakeup_ports[1].bits.uop.inst, issue_slots[15].wakeup_ports[1].bits.uop.inst connect slots_15.io.wakeup_ports[1].valid, issue_slots[15].wakeup_ports[1].valid connect slots_15.io.wakeup_ports[2].bits.rebusy, issue_slots[15].wakeup_ports[2].bits.rebusy connect slots_15.io.wakeup_ports[2].bits.speculative_mask, issue_slots[15].wakeup_ports[2].bits.speculative_mask connect slots_15.io.wakeup_ports[2].bits.bypassable, issue_slots[15].wakeup_ports[2].bits.bypassable connect slots_15.io.wakeup_ports[2].bits.uop.debug_tsrc, issue_slots[15].wakeup_ports[2].bits.uop.debug_tsrc connect slots_15.io.wakeup_ports[2].bits.uop.debug_fsrc, issue_slots[15].wakeup_ports[2].bits.uop.debug_fsrc connect slots_15.io.wakeup_ports[2].bits.uop.bp_xcpt_if, issue_slots[15].wakeup_ports[2].bits.uop.bp_xcpt_if connect slots_15.io.wakeup_ports[2].bits.uop.bp_debug_if, issue_slots[15].wakeup_ports[2].bits.uop.bp_debug_if connect slots_15.io.wakeup_ports[2].bits.uop.xcpt_ma_if, issue_slots[15].wakeup_ports[2].bits.uop.xcpt_ma_if connect slots_15.io.wakeup_ports[2].bits.uop.xcpt_ae_if, issue_slots[15].wakeup_ports[2].bits.uop.xcpt_ae_if connect slots_15.io.wakeup_ports[2].bits.uop.xcpt_pf_if, issue_slots[15].wakeup_ports[2].bits.uop.xcpt_pf_if connect slots_15.io.wakeup_ports[2].bits.uop.fp_typ, issue_slots[15].wakeup_ports[2].bits.uop.fp_typ connect slots_15.io.wakeup_ports[2].bits.uop.fp_rm, issue_slots[15].wakeup_ports[2].bits.uop.fp_rm connect slots_15.io.wakeup_ports[2].bits.uop.fp_val, issue_slots[15].wakeup_ports[2].bits.uop.fp_val connect slots_15.io.wakeup_ports[2].bits.uop.fcn_op, issue_slots[15].wakeup_ports[2].bits.uop.fcn_op connect slots_15.io.wakeup_ports[2].bits.uop.fcn_dw, issue_slots[15].wakeup_ports[2].bits.uop.fcn_dw connect slots_15.io.wakeup_ports[2].bits.uop.frs3_en, issue_slots[15].wakeup_ports[2].bits.uop.frs3_en connect slots_15.io.wakeup_ports[2].bits.uop.lrs2_rtype, issue_slots[15].wakeup_ports[2].bits.uop.lrs2_rtype connect slots_15.io.wakeup_ports[2].bits.uop.lrs1_rtype, issue_slots[15].wakeup_ports[2].bits.uop.lrs1_rtype connect slots_15.io.wakeup_ports[2].bits.uop.dst_rtype, issue_slots[15].wakeup_ports[2].bits.uop.dst_rtype connect slots_15.io.wakeup_ports[2].bits.uop.lrs3, issue_slots[15].wakeup_ports[2].bits.uop.lrs3 connect slots_15.io.wakeup_ports[2].bits.uop.lrs2, issue_slots[15].wakeup_ports[2].bits.uop.lrs2 connect slots_15.io.wakeup_ports[2].bits.uop.lrs1, issue_slots[15].wakeup_ports[2].bits.uop.lrs1 connect slots_15.io.wakeup_ports[2].bits.uop.ldst, issue_slots[15].wakeup_ports[2].bits.uop.ldst connect slots_15.io.wakeup_ports[2].bits.uop.ldst_is_rs1, issue_slots[15].wakeup_ports[2].bits.uop.ldst_is_rs1 connect slots_15.io.wakeup_ports[2].bits.uop.csr_cmd, issue_slots[15].wakeup_ports[2].bits.uop.csr_cmd connect slots_15.io.wakeup_ports[2].bits.uop.flush_on_commit, issue_slots[15].wakeup_ports[2].bits.uop.flush_on_commit connect slots_15.io.wakeup_ports[2].bits.uop.is_unique, issue_slots[15].wakeup_ports[2].bits.uop.is_unique connect slots_15.io.wakeup_ports[2].bits.uop.uses_stq, issue_slots[15].wakeup_ports[2].bits.uop.uses_stq connect slots_15.io.wakeup_ports[2].bits.uop.uses_ldq, issue_slots[15].wakeup_ports[2].bits.uop.uses_ldq connect slots_15.io.wakeup_ports[2].bits.uop.mem_signed, issue_slots[15].wakeup_ports[2].bits.uop.mem_signed connect slots_15.io.wakeup_ports[2].bits.uop.mem_size, issue_slots[15].wakeup_ports[2].bits.uop.mem_size connect slots_15.io.wakeup_ports[2].bits.uop.mem_cmd, issue_slots[15].wakeup_ports[2].bits.uop.mem_cmd connect slots_15.io.wakeup_ports[2].bits.uop.exc_cause, issue_slots[15].wakeup_ports[2].bits.uop.exc_cause connect slots_15.io.wakeup_ports[2].bits.uop.exception, issue_slots[15].wakeup_ports[2].bits.uop.exception connect slots_15.io.wakeup_ports[2].bits.uop.stale_pdst, issue_slots[15].wakeup_ports[2].bits.uop.stale_pdst connect slots_15.io.wakeup_ports[2].bits.uop.ppred_busy, issue_slots[15].wakeup_ports[2].bits.uop.ppred_busy connect slots_15.io.wakeup_ports[2].bits.uop.prs3_busy, issue_slots[15].wakeup_ports[2].bits.uop.prs3_busy connect slots_15.io.wakeup_ports[2].bits.uop.prs2_busy, issue_slots[15].wakeup_ports[2].bits.uop.prs2_busy connect slots_15.io.wakeup_ports[2].bits.uop.prs1_busy, issue_slots[15].wakeup_ports[2].bits.uop.prs1_busy connect slots_15.io.wakeup_ports[2].bits.uop.ppred, issue_slots[15].wakeup_ports[2].bits.uop.ppred connect slots_15.io.wakeup_ports[2].bits.uop.prs3, issue_slots[15].wakeup_ports[2].bits.uop.prs3 connect slots_15.io.wakeup_ports[2].bits.uop.prs2, issue_slots[15].wakeup_ports[2].bits.uop.prs2 connect slots_15.io.wakeup_ports[2].bits.uop.prs1, issue_slots[15].wakeup_ports[2].bits.uop.prs1 connect slots_15.io.wakeup_ports[2].bits.uop.pdst, issue_slots[15].wakeup_ports[2].bits.uop.pdst connect slots_15.io.wakeup_ports[2].bits.uop.rxq_idx, issue_slots[15].wakeup_ports[2].bits.uop.rxq_idx connect slots_15.io.wakeup_ports[2].bits.uop.stq_idx, issue_slots[15].wakeup_ports[2].bits.uop.stq_idx connect slots_15.io.wakeup_ports[2].bits.uop.ldq_idx, issue_slots[15].wakeup_ports[2].bits.uop.ldq_idx connect slots_15.io.wakeup_ports[2].bits.uop.rob_idx, issue_slots[15].wakeup_ports[2].bits.uop.rob_idx connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.vec connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.wflags connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.div, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.div connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.fma connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.toint connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.fromint connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.wen connect slots_15.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.ldst connect slots_15.io.wakeup_ports[2].bits.uop.op2_sel, issue_slots[15].wakeup_ports[2].bits.uop.op2_sel connect slots_15.io.wakeup_ports[2].bits.uop.op1_sel, issue_slots[15].wakeup_ports[2].bits.uop.op1_sel connect slots_15.io.wakeup_ports[2].bits.uop.imm_packed, issue_slots[15].wakeup_ports[2].bits.uop.imm_packed connect slots_15.io.wakeup_ports[2].bits.uop.pimm, issue_slots[15].wakeup_ports[2].bits.uop.pimm connect slots_15.io.wakeup_ports[2].bits.uop.imm_sel, issue_slots[15].wakeup_ports[2].bits.uop.imm_sel connect slots_15.io.wakeup_ports[2].bits.uop.imm_rename, issue_slots[15].wakeup_ports[2].bits.uop.imm_rename connect slots_15.io.wakeup_ports[2].bits.uop.taken, issue_slots[15].wakeup_ports[2].bits.uop.taken connect slots_15.io.wakeup_ports[2].bits.uop.pc_lob, issue_slots[15].wakeup_ports[2].bits.uop.pc_lob connect slots_15.io.wakeup_ports[2].bits.uop.edge_inst, issue_slots[15].wakeup_ports[2].bits.uop.edge_inst connect slots_15.io.wakeup_ports[2].bits.uop.ftq_idx, issue_slots[15].wakeup_ports[2].bits.uop.ftq_idx connect slots_15.io.wakeup_ports[2].bits.uop.is_mov, issue_slots[15].wakeup_ports[2].bits.uop.is_mov connect slots_15.io.wakeup_ports[2].bits.uop.is_rocc, issue_slots[15].wakeup_ports[2].bits.uop.is_rocc connect slots_15.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, issue_slots[15].wakeup_ports[2].bits.uop.is_sys_pc2epc connect slots_15.io.wakeup_ports[2].bits.uop.is_eret, issue_slots[15].wakeup_ports[2].bits.uop.is_eret connect slots_15.io.wakeup_ports[2].bits.uop.is_amo, issue_slots[15].wakeup_ports[2].bits.uop.is_amo connect slots_15.io.wakeup_ports[2].bits.uop.is_sfence, issue_slots[15].wakeup_ports[2].bits.uop.is_sfence connect slots_15.io.wakeup_ports[2].bits.uop.is_fencei, issue_slots[15].wakeup_ports[2].bits.uop.is_fencei connect slots_15.io.wakeup_ports[2].bits.uop.is_fence, issue_slots[15].wakeup_ports[2].bits.uop.is_fence connect slots_15.io.wakeup_ports[2].bits.uop.is_sfb, issue_slots[15].wakeup_ports[2].bits.uop.is_sfb connect slots_15.io.wakeup_ports[2].bits.uop.br_type, issue_slots[15].wakeup_ports[2].bits.uop.br_type connect slots_15.io.wakeup_ports[2].bits.uop.br_tag, issue_slots[15].wakeup_ports[2].bits.uop.br_tag connect slots_15.io.wakeup_ports[2].bits.uop.br_mask, issue_slots[15].wakeup_ports[2].bits.uop.br_mask connect slots_15.io.wakeup_ports[2].bits.uop.dis_col_sel, issue_slots[15].wakeup_ports[2].bits.uop.dis_col_sel connect slots_15.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, issue_slots[15].wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect slots_15.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, issue_slots[15].wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect slots_15.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, issue_slots[15].wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect slots_15.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, issue_slots[15].wakeup_ports[2].bits.uop.iw_p2_speculative_child connect slots_15.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, issue_slots[15].wakeup_ports[2].bits.uop.iw_p1_speculative_child connect slots_15.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, issue_slots[15].wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect slots_15.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, issue_slots[15].wakeup_ports[2].bits.uop.iw_issued_partial_agen connect slots_15.io.wakeup_ports[2].bits.uop.iw_issued, issue_slots[15].wakeup_ports[2].bits.uop.iw_issued connect slots_15.io.wakeup_ports[2].bits.uop.fu_code[0], issue_slots[15].wakeup_ports[2].bits.uop.fu_code[0] connect slots_15.io.wakeup_ports[2].bits.uop.fu_code[1], issue_slots[15].wakeup_ports[2].bits.uop.fu_code[1] connect slots_15.io.wakeup_ports[2].bits.uop.fu_code[2], issue_slots[15].wakeup_ports[2].bits.uop.fu_code[2] connect slots_15.io.wakeup_ports[2].bits.uop.fu_code[3], issue_slots[15].wakeup_ports[2].bits.uop.fu_code[3] connect slots_15.io.wakeup_ports[2].bits.uop.fu_code[4], issue_slots[15].wakeup_ports[2].bits.uop.fu_code[4] connect slots_15.io.wakeup_ports[2].bits.uop.fu_code[5], issue_slots[15].wakeup_ports[2].bits.uop.fu_code[5] connect slots_15.io.wakeup_ports[2].bits.uop.fu_code[6], issue_slots[15].wakeup_ports[2].bits.uop.fu_code[6] connect slots_15.io.wakeup_ports[2].bits.uop.fu_code[7], issue_slots[15].wakeup_ports[2].bits.uop.fu_code[7] connect slots_15.io.wakeup_ports[2].bits.uop.fu_code[8], issue_slots[15].wakeup_ports[2].bits.uop.fu_code[8] connect slots_15.io.wakeup_ports[2].bits.uop.fu_code[9], issue_slots[15].wakeup_ports[2].bits.uop.fu_code[9] connect slots_15.io.wakeup_ports[2].bits.uop.iq_type[0], issue_slots[15].wakeup_ports[2].bits.uop.iq_type[0] connect slots_15.io.wakeup_ports[2].bits.uop.iq_type[1], issue_slots[15].wakeup_ports[2].bits.uop.iq_type[1] connect slots_15.io.wakeup_ports[2].bits.uop.iq_type[2], issue_slots[15].wakeup_ports[2].bits.uop.iq_type[2] connect slots_15.io.wakeup_ports[2].bits.uop.iq_type[3], issue_slots[15].wakeup_ports[2].bits.uop.iq_type[3] connect slots_15.io.wakeup_ports[2].bits.uop.debug_pc, issue_slots[15].wakeup_ports[2].bits.uop.debug_pc connect slots_15.io.wakeup_ports[2].bits.uop.is_rvc, issue_slots[15].wakeup_ports[2].bits.uop.is_rvc connect slots_15.io.wakeup_ports[2].bits.uop.debug_inst, issue_slots[15].wakeup_ports[2].bits.uop.debug_inst connect slots_15.io.wakeup_ports[2].bits.uop.inst, issue_slots[15].wakeup_ports[2].bits.uop.inst connect slots_15.io.wakeup_ports[2].valid, issue_slots[15].wakeup_ports[2].valid connect slots_15.io.wakeup_ports[3].bits.rebusy, issue_slots[15].wakeup_ports[3].bits.rebusy connect slots_15.io.wakeup_ports[3].bits.speculative_mask, issue_slots[15].wakeup_ports[3].bits.speculative_mask connect slots_15.io.wakeup_ports[3].bits.bypassable, issue_slots[15].wakeup_ports[3].bits.bypassable connect slots_15.io.wakeup_ports[3].bits.uop.debug_tsrc, issue_slots[15].wakeup_ports[3].bits.uop.debug_tsrc connect slots_15.io.wakeup_ports[3].bits.uop.debug_fsrc, issue_slots[15].wakeup_ports[3].bits.uop.debug_fsrc connect slots_15.io.wakeup_ports[3].bits.uop.bp_xcpt_if, issue_slots[15].wakeup_ports[3].bits.uop.bp_xcpt_if connect slots_15.io.wakeup_ports[3].bits.uop.bp_debug_if, issue_slots[15].wakeup_ports[3].bits.uop.bp_debug_if connect slots_15.io.wakeup_ports[3].bits.uop.xcpt_ma_if, issue_slots[15].wakeup_ports[3].bits.uop.xcpt_ma_if connect slots_15.io.wakeup_ports[3].bits.uop.xcpt_ae_if, issue_slots[15].wakeup_ports[3].bits.uop.xcpt_ae_if connect slots_15.io.wakeup_ports[3].bits.uop.xcpt_pf_if, issue_slots[15].wakeup_ports[3].bits.uop.xcpt_pf_if connect slots_15.io.wakeup_ports[3].bits.uop.fp_typ, issue_slots[15].wakeup_ports[3].bits.uop.fp_typ connect slots_15.io.wakeup_ports[3].bits.uop.fp_rm, issue_slots[15].wakeup_ports[3].bits.uop.fp_rm connect slots_15.io.wakeup_ports[3].bits.uop.fp_val, issue_slots[15].wakeup_ports[3].bits.uop.fp_val connect slots_15.io.wakeup_ports[3].bits.uop.fcn_op, issue_slots[15].wakeup_ports[3].bits.uop.fcn_op connect slots_15.io.wakeup_ports[3].bits.uop.fcn_dw, issue_slots[15].wakeup_ports[3].bits.uop.fcn_dw connect slots_15.io.wakeup_ports[3].bits.uop.frs3_en, issue_slots[15].wakeup_ports[3].bits.uop.frs3_en connect slots_15.io.wakeup_ports[3].bits.uop.lrs2_rtype, issue_slots[15].wakeup_ports[3].bits.uop.lrs2_rtype connect slots_15.io.wakeup_ports[3].bits.uop.lrs1_rtype, issue_slots[15].wakeup_ports[3].bits.uop.lrs1_rtype connect slots_15.io.wakeup_ports[3].bits.uop.dst_rtype, issue_slots[15].wakeup_ports[3].bits.uop.dst_rtype connect slots_15.io.wakeup_ports[3].bits.uop.lrs3, issue_slots[15].wakeup_ports[3].bits.uop.lrs3 connect slots_15.io.wakeup_ports[3].bits.uop.lrs2, issue_slots[15].wakeup_ports[3].bits.uop.lrs2 connect slots_15.io.wakeup_ports[3].bits.uop.lrs1, issue_slots[15].wakeup_ports[3].bits.uop.lrs1 connect slots_15.io.wakeup_ports[3].bits.uop.ldst, issue_slots[15].wakeup_ports[3].bits.uop.ldst connect slots_15.io.wakeup_ports[3].bits.uop.ldst_is_rs1, issue_slots[15].wakeup_ports[3].bits.uop.ldst_is_rs1 connect slots_15.io.wakeup_ports[3].bits.uop.csr_cmd, issue_slots[15].wakeup_ports[3].bits.uop.csr_cmd connect slots_15.io.wakeup_ports[3].bits.uop.flush_on_commit, issue_slots[15].wakeup_ports[3].bits.uop.flush_on_commit connect slots_15.io.wakeup_ports[3].bits.uop.is_unique, issue_slots[15].wakeup_ports[3].bits.uop.is_unique connect slots_15.io.wakeup_ports[3].bits.uop.uses_stq, issue_slots[15].wakeup_ports[3].bits.uop.uses_stq connect slots_15.io.wakeup_ports[3].bits.uop.uses_ldq, issue_slots[15].wakeup_ports[3].bits.uop.uses_ldq connect slots_15.io.wakeup_ports[3].bits.uop.mem_signed, issue_slots[15].wakeup_ports[3].bits.uop.mem_signed connect slots_15.io.wakeup_ports[3].bits.uop.mem_size, issue_slots[15].wakeup_ports[3].bits.uop.mem_size connect slots_15.io.wakeup_ports[3].bits.uop.mem_cmd, issue_slots[15].wakeup_ports[3].bits.uop.mem_cmd connect slots_15.io.wakeup_ports[3].bits.uop.exc_cause, issue_slots[15].wakeup_ports[3].bits.uop.exc_cause connect slots_15.io.wakeup_ports[3].bits.uop.exception, issue_slots[15].wakeup_ports[3].bits.uop.exception connect slots_15.io.wakeup_ports[3].bits.uop.stale_pdst, issue_slots[15].wakeup_ports[3].bits.uop.stale_pdst connect slots_15.io.wakeup_ports[3].bits.uop.ppred_busy, issue_slots[15].wakeup_ports[3].bits.uop.ppred_busy connect slots_15.io.wakeup_ports[3].bits.uop.prs3_busy, issue_slots[15].wakeup_ports[3].bits.uop.prs3_busy connect slots_15.io.wakeup_ports[3].bits.uop.prs2_busy, issue_slots[15].wakeup_ports[3].bits.uop.prs2_busy connect slots_15.io.wakeup_ports[3].bits.uop.prs1_busy, issue_slots[15].wakeup_ports[3].bits.uop.prs1_busy connect slots_15.io.wakeup_ports[3].bits.uop.ppred, issue_slots[15].wakeup_ports[3].bits.uop.ppred connect slots_15.io.wakeup_ports[3].bits.uop.prs3, issue_slots[15].wakeup_ports[3].bits.uop.prs3 connect slots_15.io.wakeup_ports[3].bits.uop.prs2, issue_slots[15].wakeup_ports[3].bits.uop.prs2 connect slots_15.io.wakeup_ports[3].bits.uop.prs1, issue_slots[15].wakeup_ports[3].bits.uop.prs1 connect slots_15.io.wakeup_ports[3].bits.uop.pdst, issue_slots[15].wakeup_ports[3].bits.uop.pdst connect slots_15.io.wakeup_ports[3].bits.uop.rxq_idx, issue_slots[15].wakeup_ports[3].bits.uop.rxq_idx connect slots_15.io.wakeup_ports[3].bits.uop.stq_idx, issue_slots[15].wakeup_ports[3].bits.uop.stq_idx connect slots_15.io.wakeup_ports[3].bits.uop.ldq_idx, issue_slots[15].wakeup_ports[3].bits.uop.ldq_idx connect slots_15.io.wakeup_ports[3].bits.uop.rob_idx, issue_slots[15].wakeup_ports[3].bits.uop.rob_idx connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.vec connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.wflags connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.div, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.div connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.fma connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.toint connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.fromint connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.wen connect slots_15.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.ldst connect slots_15.io.wakeup_ports[3].bits.uop.op2_sel, issue_slots[15].wakeup_ports[3].bits.uop.op2_sel connect slots_15.io.wakeup_ports[3].bits.uop.op1_sel, issue_slots[15].wakeup_ports[3].bits.uop.op1_sel connect slots_15.io.wakeup_ports[3].bits.uop.imm_packed, issue_slots[15].wakeup_ports[3].bits.uop.imm_packed connect slots_15.io.wakeup_ports[3].bits.uop.pimm, issue_slots[15].wakeup_ports[3].bits.uop.pimm connect slots_15.io.wakeup_ports[3].bits.uop.imm_sel, issue_slots[15].wakeup_ports[3].bits.uop.imm_sel connect slots_15.io.wakeup_ports[3].bits.uop.imm_rename, issue_slots[15].wakeup_ports[3].bits.uop.imm_rename connect slots_15.io.wakeup_ports[3].bits.uop.taken, issue_slots[15].wakeup_ports[3].bits.uop.taken connect slots_15.io.wakeup_ports[3].bits.uop.pc_lob, issue_slots[15].wakeup_ports[3].bits.uop.pc_lob connect slots_15.io.wakeup_ports[3].bits.uop.edge_inst, issue_slots[15].wakeup_ports[3].bits.uop.edge_inst connect slots_15.io.wakeup_ports[3].bits.uop.ftq_idx, issue_slots[15].wakeup_ports[3].bits.uop.ftq_idx connect slots_15.io.wakeup_ports[3].bits.uop.is_mov, issue_slots[15].wakeup_ports[3].bits.uop.is_mov connect slots_15.io.wakeup_ports[3].bits.uop.is_rocc, issue_slots[15].wakeup_ports[3].bits.uop.is_rocc connect slots_15.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, issue_slots[15].wakeup_ports[3].bits.uop.is_sys_pc2epc connect slots_15.io.wakeup_ports[3].bits.uop.is_eret, issue_slots[15].wakeup_ports[3].bits.uop.is_eret connect slots_15.io.wakeup_ports[3].bits.uop.is_amo, issue_slots[15].wakeup_ports[3].bits.uop.is_amo connect slots_15.io.wakeup_ports[3].bits.uop.is_sfence, issue_slots[15].wakeup_ports[3].bits.uop.is_sfence connect slots_15.io.wakeup_ports[3].bits.uop.is_fencei, issue_slots[15].wakeup_ports[3].bits.uop.is_fencei connect slots_15.io.wakeup_ports[3].bits.uop.is_fence, issue_slots[15].wakeup_ports[3].bits.uop.is_fence connect slots_15.io.wakeup_ports[3].bits.uop.is_sfb, issue_slots[15].wakeup_ports[3].bits.uop.is_sfb connect slots_15.io.wakeup_ports[3].bits.uop.br_type, issue_slots[15].wakeup_ports[3].bits.uop.br_type connect slots_15.io.wakeup_ports[3].bits.uop.br_tag, issue_slots[15].wakeup_ports[3].bits.uop.br_tag connect slots_15.io.wakeup_ports[3].bits.uop.br_mask, issue_slots[15].wakeup_ports[3].bits.uop.br_mask connect slots_15.io.wakeup_ports[3].bits.uop.dis_col_sel, issue_slots[15].wakeup_ports[3].bits.uop.dis_col_sel connect slots_15.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, issue_slots[15].wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect slots_15.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, issue_slots[15].wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect slots_15.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, issue_slots[15].wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect slots_15.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, issue_slots[15].wakeup_ports[3].bits.uop.iw_p2_speculative_child connect slots_15.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, issue_slots[15].wakeup_ports[3].bits.uop.iw_p1_speculative_child connect slots_15.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, issue_slots[15].wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect slots_15.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, issue_slots[15].wakeup_ports[3].bits.uop.iw_issued_partial_agen connect slots_15.io.wakeup_ports[3].bits.uop.iw_issued, issue_slots[15].wakeup_ports[3].bits.uop.iw_issued connect slots_15.io.wakeup_ports[3].bits.uop.fu_code[0], issue_slots[15].wakeup_ports[3].bits.uop.fu_code[0] connect slots_15.io.wakeup_ports[3].bits.uop.fu_code[1], issue_slots[15].wakeup_ports[3].bits.uop.fu_code[1] connect slots_15.io.wakeup_ports[3].bits.uop.fu_code[2], issue_slots[15].wakeup_ports[3].bits.uop.fu_code[2] connect slots_15.io.wakeup_ports[3].bits.uop.fu_code[3], issue_slots[15].wakeup_ports[3].bits.uop.fu_code[3] connect slots_15.io.wakeup_ports[3].bits.uop.fu_code[4], issue_slots[15].wakeup_ports[3].bits.uop.fu_code[4] connect slots_15.io.wakeup_ports[3].bits.uop.fu_code[5], issue_slots[15].wakeup_ports[3].bits.uop.fu_code[5] connect slots_15.io.wakeup_ports[3].bits.uop.fu_code[6], issue_slots[15].wakeup_ports[3].bits.uop.fu_code[6] connect slots_15.io.wakeup_ports[3].bits.uop.fu_code[7], issue_slots[15].wakeup_ports[3].bits.uop.fu_code[7] connect slots_15.io.wakeup_ports[3].bits.uop.fu_code[8], issue_slots[15].wakeup_ports[3].bits.uop.fu_code[8] connect slots_15.io.wakeup_ports[3].bits.uop.fu_code[9], issue_slots[15].wakeup_ports[3].bits.uop.fu_code[9] connect slots_15.io.wakeup_ports[3].bits.uop.iq_type[0], issue_slots[15].wakeup_ports[3].bits.uop.iq_type[0] connect slots_15.io.wakeup_ports[3].bits.uop.iq_type[1], issue_slots[15].wakeup_ports[3].bits.uop.iq_type[1] connect slots_15.io.wakeup_ports[3].bits.uop.iq_type[2], issue_slots[15].wakeup_ports[3].bits.uop.iq_type[2] connect slots_15.io.wakeup_ports[3].bits.uop.iq_type[3], issue_slots[15].wakeup_ports[3].bits.uop.iq_type[3] connect slots_15.io.wakeup_ports[3].bits.uop.debug_pc, issue_slots[15].wakeup_ports[3].bits.uop.debug_pc connect slots_15.io.wakeup_ports[3].bits.uop.is_rvc, issue_slots[15].wakeup_ports[3].bits.uop.is_rvc connect slots_15.io.wakeup_ports[3].bits.uop.debug_inst, issue_slots[15].wakeup_ports[3].bits.uop.debug_inst connect slots_15.io.wakeup_ports[3].bits.uop.inst, issue_slots[15].wakeup_ports[3].bits.uop.inst connect slots_15.io.wakeup_ports[3].valid, issue_slots[15].wakeup_ports[3].valid connect slots_15.io.wakeup_ports[4].bits.rebusy, issue_slots[15].wakeup_ports[4].bits.rebusy connect slots_15.io.wakeup_ports[4].bits.speculative_mask, issue_slots[15].wakeup_ports[4].bits.speculative_mask connect slots_15.io.wakeup_ports[4].bits.bypassable, issue_slots[15].wakeup_ports[4].bits.bypassable connect slots_15.io.wakeup_ports[4].bits.uop.debug_tsrc, issue_slots[15].wakeup_ports[4].bits.uop.debug_tsrc connect slots_15.io.wakeup_ports[4].bits.uop.debug_fsrc, issue_slots[15].wakeup_ports[4].bits.uop.debug_fsrc connect slots_15.io.wakeup_ports[4].bits.uop.bp_xcpt_if, issue_slots[15].wakeup_ports[4].bits.uop.bp_xcpt_if connect slots_15.io.wakeup_ports[4].bits.uop.bp_debug_if, issue_slots[15].wakeup_ports[4].bits.uop.bp_debug_if connect slots_15.io.wakeup_ports[4].bits.uop.xcpt_ma_if, issue_slots[15].wakeup_ports[4].bits.uop.xcpt_ma_if connect slots_15.io.wakeup_ports[4].bits.uop.xcpt_ae_if, issue_slots[15].wakeup_ports[4].bits.uop.xcpt_ae_if connect slots_15.io.wakeup_ports[4].bits.uop.xcpt_pf_if, issue_slots[15].wakeup_ports[4].bits.uop.xcpt_pf_if connect slots_15.io.wakeup_ports[4].bits.uop.fp_typ, issue_slots[15].wakeup_ports[4].bits.uop.fp_typ connect slots_15.io.wakeup_ports[4].bits.uop.fp_rm, issue_slots[15].wakeup_ports[4].bits.uop.fp_rm connect slots_15.io.wakeup_ports[4].bits.uop.fp_val, issue_slots[15].wakeup_ports[4].bits.uop.fp_val connect slots_15.io.wakeup_ports[4].bits.uop.fcn_op, issue_slots[15].wakeup_ports[4].bits.uop.fcn_op connect slots_15.io.wakeup_ports[4].bits.uop.fcn_dw, issue_slots[15].wakeup_ports[4].bits.uop.fcn_dw connect slots_15.io.wakeup_ports[4].bits.uop.frs3_en, issue_slots[15].wakeup_ports[4].bits.uop.frs3_en connect slots_15.io.wakeup_ports[4].bits.uop.lrs2_rtype, issue_slots[15].wakeup_ports[4].bits.uop.lrs2_rtype connect slots_15.io.wakeup_ports[4].bits.uop.lrs1_rtype, issue_slots[15].wakeup_ports[4].bits.uop.lrs1_rtype connect slots_15.io.wakeup_ports[4].bits.uop.dst_rtype, issue_slots[15].wakeup_ports[4].bits.uop.dst_rtype connect slots_15.io.wakeup_ports[4].bits.uop.lrs3, issue_slots[15].wakeup_ports[4].bits.uop.lrs3 connect slots_15.io.wakeup_ports[4].bits.uop.lrs2, issue_slots[15].wakeup_ports[4].bits.uop.lrs2 connect slots_15.io.wakeup_ports[4].bits.uop.lrs1, issue_slots[15].wakeup_ports[4].bits.uop.lrs1 connect slots_15.io.wakeup_ports[4].bits.uop.ldst, issue_slots[15].wakeup_ports[4].bits.uop.ldst connect slots_15.io.wakeup_ports[4].bits.uop.ldst_is_rs1, issue_slots[15].wakeup_ports[4].bits.uop.ldst_is_rs1 connect slots_15.io.wakeup_ports[4].bits.uop.csr_cmd, issue_slots[15].wakeup_ports[4].bits.uop.csr_cmd connect slots_15.io.wakeup_ports[4].bits.uop.flush_on_commit, issue_slots[15].wakeup_ports[4].bits.uop.flush_on_commit connect slots_15.io.wakeup_ports[4].bits.uop.is_unique, issue_slots[15].wakeup_ports[4].bits.uop.is_unique connect slots_15.io.wakeup_ports[4].bits.uop.uses_stq, issue_slots[15].wakeup_ports[4].bits.uop.uses_stq connect slots_15.io.wakeup_ports[4].bits.uop.uses_ldq, issue_slots[15].wakeup_ports[4].bits.uop.uses_ldq connect slots_15.io.wakeup_ports[4].bits.uop.mem_signed, issue_slots[15].wakeup_ports[4].bits.uop.mem_signed connect slots_15.io.wakeup_ports[4].bits.uop.mem_size, issue_slots[15].wakeup_ports[4].bits.uop.mem_size connect slots_15.io.wakeup_ports[4].bits.uop.mem_cmd, issue_slots[15].wakeup_ports[4].bits.uop.mem_cmd connect slots_15.io.wakeup_ports[4].bits.uop.exc_cause, issue_slots[15].wakeup_ports[4].bits.uop.exc_cause connect slots_15.io.wakeup_ports[4].bits.uop.exception, issue_slots[15].wakeup_ports[4].bits.uop.exception connect slots_15.io.wakeup_ports[4].bits.uop.stale_pdst, issue_slots[15].wakeup_ports[4].bits.uop.stale_pdst connect slots_15.io.wakeup_ports[4].bits.uop.ppred_busy, issue_slots[15].wakeup_ports[4].bits.uop.ppred_busy connect slots_15.io.wakeup_ports[4].bits.uop.prs3_busy, issue_slots[15].wakeup_ports[4].bits.uop.prs3_busy connect slots_15.io.wakeup_ports[4].bits.uop.prs2_busy, issue_slots[15].wakeup_ports[4].bits.uop.prs2_busy connect slots_15.io.wakeup_ports[4].bits.uop.prs1_busy, issue_slots[15].wakeup_ports[4].bits.uop.prs1_busy connect slots_15.io.wakeup_ports[4].bits.uop.ppred, issue_slots[15].wakeup_ports[4].bits.uop.ppred connect slots_15.io.wakeup_ports[4].bits.uop.prs3, issue_slots[15].wakeup_ports[4].bits.uop.prs3 connect slots_15.io.wakeup_ports[4].bits.uop.prs2, issue_slots[15].wakeup_ports[4].bits.uop.prs2 connect slots_15.io.wakeup_ports[4].bits.uop.prs1, issue_slots[15].wakeup_ports[4].bits.uop.prs1 connect slots_15.io.wakeup_ports[4].bits.uop.pdst, issue_slots[15].wakeup_ports[4].bits.uop.pdst connect slots_15.io.wakeup_ports[4].bits.uop.rxq_idx, issue_slots[15].wakeup_ports[4].bits.uop.rxq_idx connect slots_15.io.wakeup_ports[4].bits.uop.stq_idx, issue_slots[15].wakeup_ports[4].bits.uop.stq_idx connect slots_15.io.wakeup_ports[4].bits.uop.ldq_idx, issue_slots[15].wakeup_ports[4].bits.uop.ldq_idx connect slots_15.io.wakeup_ports[4].bits.uop.rob_idx, issue_slots[15].wakeup_ports[4].bits.uop.rob_idx connect slots_15.io.wakeup_ports[4].bits.uop.fp_ctrl.vec, issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.vec connect slots_15.io.wakeup_ports[4].bits.uop.fp_ctrl.wflags, issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.wflags connect slots_15.io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt, issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect slots_15.io.wakeup_ports[4].bits.uop.fp_ctrl.div, issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.div connect slots_15.io.wakeup_ports[4].bits.uop.fp_ctrl.fma, issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.fma connect slots_15.io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect slots_15.io.wakeup_ports[4].bits.uop.fp_ctrl.toint, issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.toint connect slots_15.io.wakeup_ports[4].bits.uop.fp_ctrl.fromint, issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.fromint connect slots_15.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect slots_15.io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect slots_15.io.wakeup_ports[4].bits.uop.fp_ctrl.swap23, issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect slots_15.io.wakeup_ports[4].bits.uop.fp_ctrl.swap12, issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect slots_15.io.wakeup_ports[4].bits.uop.fp_ctrl.ren3, issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect slots_15.io.wakeup_ports[4].bits.uop.fp_ctrl.ren2, issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect slots_15.io.wakeup_ports[4].bits.uop.fp_ctrl.ren1, issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect slots_15.io.wakeup_ports[4].bits.uop.fp_ctrl.wen, issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.wen connect slots_15.io.wakeup_ports[4].bits.uop.fp_ctrl.ldst, issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.ldst connect slots_15.io.wakeup_ports[4].bits.uop.op2_sel, issue_slots[15].wakeup_ports[4].bits.uop.op2_sel connect slots_15.io.wakeup_ports[4].bits.uop.op1_sel, issue_slots[15].wakeup_ports[4].bits.uop.op1_sel connect slots_15.io.wakeup_ports[4].bits.uop.imm_packed, issue_slots[15].wakeup_ports[4].bits.uop.imm_packed connect slots_15.io.wakeup_ports[4].bits.uop.pimm, issue_slots[15].wakeup_ports[4].bits.uop.pimm connect slots_15.io.wakeup_ports[4].bits.uop.imm_sel, issue_slots[15].wakeup_ports[4].bits.uop.imm_sel connect slots_15.io.wakeup_ports[4].bits.uop.imm_rename, issue_slots[15].wakeup_ports[4].bits.uop.imm_rename connect slots_15.io.wakeup_ports[4].bits.uop.taken, issue_slots[15].wakeup_ports[4].bits.uop.taken connect slots_15.io.wakeup_ports[4].bits.uop.pc_lob, issue_slots[15].wakeup_ports[4].bits.uop.pc_lob connect slots_15.io.wakeup_ports[4].bits.uop.edge_inst, issue_slots[15].wakeup_ports[4].bits.uop.edge_inst connect slots_15.io.wakeup_ports[4].bits.uop.ftq_idx, issue_slots[15].wakeup_ports[4].bits.uop.ftq_idx connect slots_15.io.wakeup_ports[4].bits.uop.is_mov, issue_slots[15].wakeup_ports[4].bits.uop.is_mov connect slots_15.io.wakeup_ports[4].bits.uop.is_rocc, issue_slots[15].wakeup_ports[4].bits.uop.is_rocc connect slots_15.io.wakeup_ports[4].bits.uop.is_sys_pc2epc, issue_slots[15].wakeup_ports[4].bits.uop.is_sys_pc2epc connect slots_15.io.wakeup_ports[4].bits.uop.is_eret, issue_slots[15].wakeup_ports[4].bits.uop.is_eret connect slots_15.io.wakeup_ports[4].bits.uop.is_amo, issue_slots[15].wakeup_ports[4].bits.uop.is_amo connect slots_15.io.wakeup_ports[4].bits.uop.is_sfence, issue_slots[15].wakeup_ports[4].bits.uop.is_sfence connect slots_15.io.wakeup_ports[4].bits.uop.is_fencei, issue_slots[15].wakeup_ports[4].bits.uop.is_fencei connect slots_15.io.wakeup_ports[4].bits.uop.is_fence, issue_slots[15].wakeup_ports[4].bits.uop.is_fence connect slots_15.io.wakeup_ports[4].bits.uop.is_sfb, issue_slots[15].wakeup_ports[4].bits.uop.is_sfb connect slots_15.io.wakeup_ports[4].bits.uop.br_type, issue_slots[15].wakeup_ports[4].bits.uop.br_type connect slots_15.io.wakeup_ports[4].bits.uop.br_tag, issue_slots[15].wakeup_ports[4].bits.uop.br_tag connect slots_15.io.wakeup_ports[4].bits.uop.br_mask, issue_slots[15].wakeup_ports[4].bits.uop.br_mask connect slots_15.io.wakeup_ports[4].bits.uop.dis_col_sel, issue_slots[15].wakeup_ports[4].bits.uop.dis_col_sel connect slots_15.io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint, issue_slots[15].wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect slots_15.io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint, issue_slots[15].wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect slots_15.io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint, issue_slots[15].wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect slots_15.io.wakeup_ports[4].bits.uop.iw_p2_speculative_child, issue_slots[15].wakeup_ports[4].bits.uop.iw_p2_speculative_child connect slots_15.io.wakeup_ports[4].bits.uop.iw_p1_speculative_child, issue_slots[15].wakeup_ports[4].bits.uop.iw_p1_speculative_child connect slots_15.io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen, issue_slots[15].wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect slots_15.io.wakeup_ports[4].bits.uop.iw_issued_partial_agen, issue_slots[15].wakeup_ports[4].bits.uop.iw_issued_partial_agen connect slots_15.io.wakeup_ports[4].bits.uop.iw_issued, issue_slots[15].wakeup_ports[4].bits.uop.iw_issued connect slots_15.io.wakeup_ports[4].bits.uop.fu_code[0], issue_slots[15].wakeup_ports[4].bits.uop.fu_code[0] connect slots_15.io.wakeup_ports[4].bits.uop.fu_code[1], issue_slots[15].wakeup_ports[4].bits.uop.fu_code[1] connect slots_15.io.wakeup_ports[4].bits.uop.fu_code[2], issue_slots[15].wakeup_ports[4].bits.uop.fu_code[2] connect slots_15.io.wakeup_ports[4].bits.uop.fu_code[3], issue_slots[15].wakeup_ports[4].bits.uop.fu_code[3] connect slots_15.io.wakeup_ports[4].bits.uop.fu_code[4], issue_slots[15].wakeup_ports[4].bits.uop.fu_code[4] connect slots_15.io.wakeup_ports[4].bits.uop.fu_code[5], issue_slots[15].wakeup_ports[4].bits.uop.fu_code[5] connect slots_15.io.wakeup_ports[4].bits.uop.fu_code[6], issue_slots[15].wakeup_ports[4].bits.uop.fu_code[6] connect slots_15.io.wakeup_ports[4].bits.uop.fu_code[7], issue_slots[15].wakeup_ports[4].bits.uop.fu_code[7] connect slots_15.io.wakeup_ports[4].bits.uop.fu_code[8], issue_slots[15].wakeup_ports[4].bits.uop.fu_code[8] connect slots_15.io.wakeup_ports[4].bits.uop.fu_code[9], issue_slots[15].wakeup_ports[4].bits.uop.fu_code[9] connect slots_15.io.wakeup_ports[4].bits.uop.iq_type[0], issue_slots[15].wakeup_ports[4].bits.uop.iq_type[0] connect slots_15.io.wakeup_ports[4].bits.uop.iq_type[1], issue_slots[15].wakeup_ports[4].bits.uop.iq_type[1] connect slots_15.io.wakeup_ports[4].bits.uop.iq_type[2], issue_slots[15].wakeup_ports[4].bits.uop.iq_type[2] connect slots_15.io.wakeup_ports[4].bits.uop.iq_type[3], issue_slots[15].wakeup_ports[4].bits.uop.iq_type[3] connect slots_15.io.wakeup_ports[4].bits.uop.debug_pc, issue_slots[15].wakeup_ports[4].bits.uop.debug_pc connect slots_15.io.wakeup_ports[4].bits.uop.is_rvc, issue_slots[15].wakeup_ports[4].bits.uop.is_rvc connect slots_15.io.wakeup_ports[4].bits.uop.debug_inst, issue_slots[15].wakeup_ports[4].bits.uop.debug_inst connect slots_15.io.wakeup_ports[4].bits.uop.inst, issue_slots[15].wakeup_ports[4].bits.uop.inst connect slots_15.io.wakeup_ports[4].valid, issue_slots[15].wakeup_ports[4].valid connect slots_15.io.squash_grant, issue_slots[15].squash_grant connect slots_15.io.clear, issue_slots[15].clear connect slots_15.io.kill, issue_slots[15].kill connect slots_15.io.brupdate.b2.target_offset, issue_slots[15].brupdate.b2.target_offset connect slots_15.io.brupdate.b2.jalr_target, issue_slots[15].brupdate.b2.jalr_target connect slots_15.io.brupdate.b2.pc_sel, issue_slots[15].brupdate.b2.pc_sel connect slots_15.io.brupdate.b2.cfi_type, issue_slots[15].brupdate.b2.cfi_type connect slots_15.io.brupdate.b2.taken, issue_slots[15].brupdate.b2.taken connect slots_15.io.brupdate.b2.mispredict, issue_slots[15].brupdate.b2.mispredict connect slots_15.io.brupdate.b2.uop.debug_tsrc, issue_slots[15].brupdate.b2.uop.debug_tsrc connect slots_15.io.brupdate.b2.uop.debug_fsrc, issue_slots[15].brupdate.b2.uop.debug_fsrc connect slots_15.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[15].brupdate.b2.uop.bp_xcpt_if connect slots_15.io.brupdate.b2.uop.bp_debug_if, issue_slots[15].brupdate.b2.uop.bp_debug_if connect slots_15.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[15].brupdate.b2.uop.xcpt_ma_if connect slots_15.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[15].brupdate.b2.uop.xcpt_ae_if connect slots_15.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[15].brupdate.b2.uop.xcpt_pf_if connect slots_15.io.brupdate.b2.uop.fp_typ, issue_slots[15].brupdate.b2.uop.fp_typ connect slots_15.io.brupdate.b2.uop.fp_rm, issue_slots[15].brupdate.b2.uop.fp_rm connect slots_15.io.brupdate.b2.uop.fp_val, issue_slots[15].brupdate.b2.uop.fp_val connect slots_15.io.brupdate.b2.uop.fcn_op, issue_slots[15].brupdate.b2.uop.fcn_op connect slots_15.io.brupdate.b2.uop.fcn_dw, issue_slots[15].brupdate.b2.uop.fcn_dw connect slots_15.io.brupdate.b2.uop.frs3_en, issue_slots[15].brupdate.b2.uop.frs3_en connect slots_15.io.brupdate.b2.uop.lrs2_rtype, issue_slots[15].brupdate.b2.uop.lrs2_rtype connect slots_15.io.brupdate.b2.uop.lrs1_rtype, issue_slots[15].brupdate.b2.uop.lrs1_rtype connect slots_15.io.brupdate.b2.uop.dst_rtype, issue_slots[15].brupdate.b2.uop.dst_rtype connect slots_15.io.brupdate.b2.uop.lrs3, issue_slots[15].brupdate.b2.uop.lrs3 connect slots_15.io.brupdate.b2.uop.lrs2, issue_slots[15].brupdate.b2.uop.lrs2 connect slots_15.io.brupdate.b2.uop.lrs1, issue_slots[15].brupdate.b2.uop.lrs1 connect slots_15.io.brupdate.b2.uop.ldst, issue_slots[15].brupdate.b2.uop.ldst connect slots_15.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[15].brupdate.b2.uop.ldst_is_rs1 connect slots_15.io.brupdate.b2.uop.csr_cmd, issue_slots[15].brupdate.b2.uop.csr_cmd connect slots_15.io.brupdate.b2.uop.flush_on_commit, issue_slots[15].brupdate.b2.uop.flush_on_commit connect slots_15.io.brupdate.b2.uop.is_unique, issue_slots[15].brupdate.b2.uop.is_unique connect slots_15.io.brupdate.b2.uop.uses_stq, issue_slots[15].brupdate.b2.uop.uses_stq connect slots_15.io.brupdate.b2.uop.uses_ldq, issue_slots[15].brupdate.b2.uop.uses_ldq connect slots_15.io.brupdate.b2.uop.mem_signed, issue_slots[15].brupdate.b2.uop.mem_signed connect slots_15.io.brupdate.b2.uop.mem_size, issue_slots[15].brupdate.b2.uop.mem_size connect slots_15.io.brupdate.b2.uop.mem_cmd, issue_slots[15].brupdate.b2.uop.mem_cmd connect slots_15.io.brupdate.b2.uop.exc_cause, issue_slots[15].brupdate.b2.uop.exc_cause connect slots_15.io.brupdate.b2.uop.exception, issue_slots[15].brupdate.b2.uop.exception connect slots_15.io.brupdate.b2.uop.stale_pdst, issue_slots[15].brupdate.b2.uop.stale_pdst connect slots_15.io.brupdate.b2.uop.ppred_busy, issue_slots[15].brupdate.b2.uop.ppred_busy connect slots_15.io.brupdate.b2.uop.prs3_busy, issue_slots[15].brupdate.b2.uop.prs3_busy connect slots_15.io.brupdate.b2.uop.prs2_busy, issue_slots[15].brupdate.b2.uop.prs2_busy connect slots_15.io.brupdate.b2.uop.prs1_busy, issue_slots[15].brupdate.b2.uop.prs1_busy connect slots_15.io.brupdate.b2.uop.ppred, issue_slots[15].brupdate.b2.uop.ppred connect slots_15.io.brupdate.b2.uop.prs3, issue_slots[15].brupdate.b2.uop.prs3 connect slots_15.io.brupdate.b2.uop.prs2, issue_slots[15].brupdate.b2.uop.prs2 connect slots_15.io.brupdate.b2.uop.prs1, issue_slots[15].brupdate.b2.uop.prs1 connect slots_15.io.brupdate.b2.uop.pdst, issue_slots[15].brupdate.b2.uop.pdst connect slots_15.io.brupdate.b2.uop.rxq_idx, issue_slots[15].brupdate.b2.uop.rxq_idx connect slots_15.io.brupdate.b2.uop.stq_idx, issue_slots[15].brupdate.b2.uop.stq_idx connect slots_15.io.brupdate.b2.uop.ldq_idx, issue_slots[15].brupdate.b2.uop.ldq_idx connect slots_15.io.brupdate.b2.uop.rob_idx, issue_slots[15].brupdate.b2.uop.rob_idx connect slots_15.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[15].brupdate.b2.uop.fp_ctrl.vec connect slots_15.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[15].brupdate.b2.uop.fp_ctrl.wflags connect slots_15.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[15].brupdate.b2.uop.fp_ctrl.sqrt connect slots_15.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[15].brupdate.b2.uop.fp_ctrl.div connect slots_15.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[15].brupdate.b2.uop.fp_ctrl.fma connect slots_15.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[15].brupdate.b2.uop.fp_ctrl.fastpipe connect slots_15.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[15].brupdate.b2.uop.fp_ctrl.toint connect slots_15.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[15].brupdate.b2.uop.fp_ctrl.fromint connect slots_15.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[15].brupdate.b2.uop.fp_ctrl.typeTagOut connect slots_15.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[15].brupdate.b2.uop.fp_ctrl.typeTagIn connect slots_15.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[15].brupdate.b2.uop.fp_ctrl.swap23 connect slots_15.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[15].brupdate.b2.uop.fp_ctrl.swap12 connect slots_15.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[15].brupdate.b2.uop.fp_ctrl.ren3 connect slots_15.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[15].brupdate.b2.uop.fp_ctrl.ren2 connect slots_15.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[15].brupdate.b2.uop.fp_ctrl.ren1 connect slots_15.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[15].brupdate.b2.uop.fp_ctrl.wen connect slots_15.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[15].brupdate.b2.uop.fp_ctrl.ldst connect slots_15.io.brupdate.b2.uop.op2_sel, issue_slots[15].brupdate.b2.uop.op2_sel connect slots_15.io.brupdate.b2.uop.op1_sel, issue_slots[15].brupdate.b2.uop.op1_sel connect slots_15.io.brupdate.b2.uop.imm_packed, issue_slots[15].brupdate.b2.uop.imm_packed connect slots_15.io.brupdate.b2.uop.pimm, issue_slots[15].brupdate.b2.uop.pimm connect slots_15.io.brupdate.b2.uop.imm_sel, issue_slots[15].brupdate.b2.uop.imm_sel connect slots_15.io.brupdate.b2.uop.imm_rename, issue_slots[15].brupdate.b2.uop.imm_rename connect slots_15.io.brupdate.b2.uop.taken, issue_slots[15].brupdate.b2.uop.taken connect slots_15.io.brupdate.b2.uop.pc_lob, issue_slots[15].brupdate.b2.uop.pc_lob connect slots_15.io.brupdate.b2.uop.edge_inst, issue_slots[15].brupdate.b2.uop.edge_inst connect slots_15.io.brupdate.b2.uop.ftq_idx, issue_slots[15].brupdate.b2.uop.ftq_idx connect slots_15.io.brupdate.b2.uop.is_mov, issue_slots[15].brupdate.b2.uop.is_mov connect slots_15.io.brupdate.b2.uop.is_rocc, issue_slots[15].brupdate.b2.uop.is_rocc connect slots_15.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[15].brupdate.b2.uop.is_sys_pc2epc connect slots_15.io.brupdate.b2.uop.is_eret, issue_slots[15].brupdate.b2.uop.is_eret connect slots_15.io.brupdate.b2.uop.is_amo, issue_slots[15].brupdate.b2.uop.is_amo connect slots_15.io.brupdate.b2.uop.is_sfence, issue_slots[15].brupdate.b2.uop.is_sfence connect slots_15.io.brupdate.b2.uop.is_fencei, issue_slots[15].brupdate.b2.uop.is_fencei connect slots_15.io.brupdate.b2.uop.is_fence, issue_slots[15].brupdate.b2.uop.is_fence connect slots_15.io.brupdate.b2.uop.is_sfb, issue_slots[15].brupdate.b2.uop.is_sfb connect slots_15.io.brupdate.b2.uop.br_type, issue_slots[15].brupdate.b2.uop.br_type connect slots_15.io.brupdate.b2.uop.br_tag, issue_slots[15].brupdate.b2.uop.br_tag connect slots_15.io.brupdate.b2.uop.br_mask, issue_slots[15].brupdate.b2.uop.br_mask connect slots_15.io.brupdate.b2.uop.dis_col_sel, issue_slots[15].brupdate.b2.uop.dis_col_sel connect slots_15.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[15].brupdate.b2.uop.iw_p3_bypass_hint connect slots_15.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[15].brupdate.b2.uop.iw_p2_bypass_hint connect slots_15.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[15].brupdate.b2.uop.iw_p1_bypass_hint connect slots_15.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[15].brupdate.b2.uop.iw_p2_speculative_child connect slots_15.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[15].brupdate.b2.uop.iw_p1_speculative_child connect slots_15.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[15].brupdate.b2.uop.iw_issued_partial_dgen connect slots_15.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[15].brupdate.b2.uop.iw_issued_partial_agen connect slots_15.io.brupdate.b2.uop.iw_issued, issue_slots[15].brupdate.b2.uop.iw_issued connect slots_15.io.brupdate.b2.uop.fu_code[0], issue_slots[15].brupdate.b2.uop.fu_code[0] connect slots_15.io.brupdate.b2.uop.fu_code[1], issue_slots[15].brupdate.b2.uop.fu_code[1] connect slots_15.io.brupdate.b2.uop.fu_code[2], issue_slots[15].brupdate.b2.uop.fu_code[2] connect slots_15.io.brupdate.b2.uop.fu_code[3], issue_slots[15].brupdate.b2.uop.fu_code[3] connect slots_15.io.brupdate.b2.uop.fu_code[4], issue_slots[15].brupdate.b2.uop.fu_code[4] connect slots_15.io.brupdate.b2.uop.fu_code[5], issue_slots[15].brupdate.b2.uop.fu_code[5] connect slots_15.io.brupdate.b2.uop.fu_code[6], issue_slots[15].brupdate.b2.uop.fu_code[6] connect slots_15.io.brupdate.b2.uop.fu_code[7], issue_slots[15].brupdate.b2.uop.fu_code[7] connect slots_15.io.brupdate.b2.uop.fu_code[8], issue_slots[15].brupdate.b2.uop.fu_code[8] connect slots_15.io.brupdate.b2.uop.fu_code[9], issue_slots[15].brupdate.b2.uop.fu_code[9] connect slots_15.io.brupdate.b2.uop.iq_type[0], issue_slots[15].brupdate.b2.uop.iq_type[0] connect slots_15.io.brupdate.b2.uop.iq_type[1], issue_slots[15].brupdate.b2.uop.iq_type[1] connect slots_15.io.brupdate.b2.uop.iq_type[2], issue_slots[15].brupdate.b2.uop.iq_type[2] connect slots_15.io.brupdate.b2.uop.iq_type[3], issue_slots[15].brupdate.b2.uop.iq_type[3] connect slots_15.io.brupdate.b2.uop.debug_pc, issue_slots[15].brupdate.b2.uop.debug_pc connect slots_15.io.brupdate.b2.uop.is_rvc, issue_slots[15].brupdate.b2.uop.is_rvc connect slots_15.io.brupdate.b2.uop.debug_inst, issue_slots[15].brupdate.b2.uop.debug_inst connect slots_15.io.brupdate.b2.uop.inst, issue_slots[15].brupdate.b2.uop.inst connect slots_15.io.brupdate.b1.mispredict_mask, issue_slots[15].brupdate.b1.mispredict_mask connect slots_15.io.brupdate.b1.resolve_mask, issue_slots[15].brupdate.b1.resolve_mask connect issue_slots[15].out_uop.debug_tsrc, slots_15.io.out_uop.debug_tsrc connect issue_slots[15].out_uop.debug_fsrc, slots_15.io.out_uop.debug_fsrc connect issue_slots[15].out_uop.bp_xcpt_if, slots_15.io.out_uop.bp_xcpt_if connect issue_slots[15].out_uop.bp_debug_if, slots_15.io.out_uop.bp_debug_if connect issue_slots[15].out_uop.xcpt_ma_if, slots_15.io.out_uop.xcpt_ma_if connect issue_slots[15].out_uop.xcpt_ae_if, slots_15.io.out_uop.xcpt_ae_if connect issue_slots[15].out_uop.xcpt_pf_if, slots_15.io.out_uop.xcpt_pf_if connect issue_slots[15].out_uop.fp_typ, slots_15.io.out_uop.fp_typ connect issue_slots[15].out_uop.fp_rm, slots_15.io.out_uop.fp_rm connect issue_slots[15].out_uop.fp_val, slots_15.io.out_uop.fp_val connect issue_slots[15].out_uop.fcn_op, slots_15.io.out_uop.fcn_op connect issue_slots[15].out_uop.fcn_dw, slots_15.io.out_uop.fcn_dw connect issue_slots[15].out_uop.frs3_en, slots_15.io.out_uop.frs3_en connect issue_slots[15].out_uop.lrs2_rtype, slots_15.io.out_uop.lrs2_rtype connect issue_slots[15].out_uop.lrs1_rtype, slots_15.io.out_uop.lrs1_rtype connect issue_slots[15].out_uop.dst_rtype, slots_15.io.out_uop.dst_rtype connect issue_slots[15].out_uop.lrs3, slots_15.io.out_uop.lrs3 connect issue_slots[15].out_uop.lrs2, slots_15.io.out_uop.lrs2 connect issue_slots[15].out_uop.lrs1, slots_15.io.out_uop.lrs1 connect issue_slots[15].out_uop.ldst, slots_15.io.out_uop.ldst connect issue_slots[15].out_uop.ldst_is_rs1, slots_15.io.out_uop.ldst_is_rs1 connect issue_slots[15].out_uop.csr_cmd, slots_15.io.out_uop.csr_cmd connect issue_slots[15].out_uop.flush_on_commit, slots_15.io.out_uop.flush_on_commit connect issue_slots[15].out_uop.is_unique, slots_15.io.out_uop.is_unique connect issue_slots[15].out_uop.uses_stq, slots_15.io.out_uop.uses_stq connect issue_slots[15].out_uop.uses_ldq, slots_15.io.out_uop.uses_ldq connect issue_slots[15].out_uop.mem_signed, slots_15.io.out_uop.mem_signed connect issue_slots[15].out_uop.mem_size, slots_15.io.out_uop.mem_size connect issue_slots[15].out_uop.mem_cmd, slots_15.io.out_uop.mem_cmd connect issue_slots[15].out_uop.exc_cause, slots_15.io.out_uop.exc_cause connect issue_slots[15].out_uop.exception, slots_15.io.out_uop.exception connect issue_slots[15].out_uop.stale_pdst, slots_15.io.out_uop.stale_pdst connect issue_slots[15].out_uop.ppred_busy, slots_15.io.out_uop.ppred_busy connect issue_slots[15].out_uop.prs3_busy, slots_15.io.out_uop.prs3_busy connect issue_slots[15].out_uop.prs2_busy, slots_15.io.out_uop.prs2_busy connect issue_slots[15].out_uop.prs1_busy, slots_15.io.out_uop.prs1_busy connect issue_slots[15].out_uop.ppred, slots_15.io.out_uop.ppred connect issue_slots[15].out_uop.prs3, slots_15.io.out_uop.prs3 connect issue_slots[15].out_uop.prs2, slots_15.io.out_uop.prs2 connect issue_slots[15].out_uop.prs1, slots_15.io.out_uop.prs1 connect issue_slots[15].out_uop.pdst, slots_15.io.out_uop.pdst connect issue_slots[15].out_uop.rxq_idx, slots_15.io.out_uop.rxq_idx connect issue_slots[15].out_uop.stq_idx, slots_15.io.out_uop.stq_idx connect issue_slots[15].out_uop.ldq_idx, slots_15.io.out_uop.ldq_idx connect issue_slots[15].out_uop.rob_idx, slots_15.io.out_uop.rob_idx connect issue_slots[15].out_uop.fp_ctrl.vec, slots_15.io.out_uop.fp_ctrl.vec connect issue_slots[15].out_uop.fp_ctrl.wflags, slots_15.io.out_uop.fp_ctrl.wflags connect issue_slots[15].out_uop.fp_ctrl.sqrt, slots_15.io.out_uop.fp_ctrl.sqrt connect issue_slots[15].out_uop.fp_ctrl.div, slots_15.io.out_uop.fp_ctrl.div connect issue_slots[15].out_uop.fp_ctrl.fma, slots_15.io.out_uop.fp_ctrl.fma connect issue_slots[15].out_uop.fp_ctrl.fastpipe, slots_15.io.out_uop.fp_ctrl.fastpipe connect issue_slots[15].out_uop.fp_ctrl.toint, slots_15.io.out_uop.fp_ctrl.toint connect issue_slots[15].out_uop.fp_ctrl.fromint, slots_15.io.out_uop.fp_ctrl.fromint connect issue_slots[15].out_uop.fp_ctrl.typeTagOut, slots_15.io.out_uop.fp_ctrl.typeTagOut connect issue_slots[15].out_uop.fp_ctrl.typeTagIn, slots_15.io.out_uop.fp_ctrl.typeTagIn connect issue_slots[15].out_uop.fp_ctrl.swap23, slots_15.io.out_uop.fp_ctrl.swap23 connect issue_slots[15].out_uop.fp_ctrl.swap12, slots_15.io.out_uop.fp_ctrl.swap12 connect issue_slots[15].out_uop.fp_ctrl.ren3, slots_15.io.out_uop.fp_ctrl.ren3 connect issue_slots[15].out_uop.fp_ctrl.ren2, slots_15.io.out_uop.fp_ctrl.ren2 connect issue_slots[15].out_uop.fp_ctrl.ren1, slots_15.io.out_uop.fp_ctrl.ren1 connect issue_slots[15].out_uop.fp_ctrl.wen, slots_15.io.out_uop.fp_ctrl.wen connect issue_slots[15].out_uop.fp_ctrl.ldst, slots_15.io.out_uop.fp_ctrl.ldst connect issue_slots[15].out_uop.op2_sel, slots_15.io.out_uop.op2_sel connect issue_slots[15].out_uop.op1_sel, slots_15.io.out_uop.op1_sel connect issue_slots[15].out_uop.imm_packed, slots_15.io.out_uop.imm_packed connect issue_slots[15].out_uop.pimm, slots_15.io.out_uop.pimm connect issue_slots[15].out_uop.imm_sel, slots_15.io.out_uop.imm_sel connect issue_slots[15].out_uop.imm_rename, slots_15.io.out_uop.imm_rename connect issue_slots[15].out_uop.taken, slots_15.io.out_uop.taken connect issue_slots[15].out_uop.pc_lob, slots_15.io.out_uop.pc_lob connect issue_slots[15].out_uop.edge_inst, slots_15.io.out_uop.edge_inst connect issue_slots[15].out_uop.ftq_idx, slots_15.io.out_uop.ftq_idx connect issue_slots[15].out_uop.is_mov, slots_15.io.out_uop.is_mov connect issue_slots[15].out_uop.is_rocc, slots_15.io.out_uop.is_rocc connect issue_slots[15].out_uop.is_sys_pc2epc, slots_15.io.out_uop.is_sys_pc2epc connect issue_slots[15].out_uop.is_eret, slots_15.io.out_uop.is_eret connect issue_slots[15].out_uop.is_amo, slots_15.io.out_uop.is_amo connect issue_slots[15].out_uop.is_sfence, slots_15.io.out_uop.is_sfence connect issue_slots[15].out_uop.is_fencei, slots_15.io.out_uop.is_fencei connect issue_slots[15].out_uop.is_fence, slots_15.io.out_uop.is_fence connect issue_slots[15].out_uop.is_sfb, slots_15.io.out_uop.is_sfb connect issue_slots[15].out_uop.br_type, slots_15.io.out_uop.br_type connect issue_slots[15].out_uop.br_tag, slots_15.io.out_uop.br_tag connect issue_slots[15].out_uop.br_mask, slots_15.io.out_uop.br_mask connect issue_slots[15].out_uop.dis_col_sel, slots_15.io.out_uop.dis_col_sel connect issue_slots[15].out_uop.iw_p3_bypass_hint, slots_15.io.out_uop.iw_p3_bypass_hint connect issue_slots[15].out_uop.iw_p2_bypass_hint, slots_15.io.out_uop.iw_p2_bypass_hint connect issue_slots[15].out_uop.iw_p1_bypass_hint, slots_15.io.out_uop.iw_p1_bypass_hint connect issue_slots[15].out_uop.iw_p2_speculative_child, slots_15.io.out_uop.iw_p2_speculative_child connect issue_slots[15].out_uop.iw_p1_speculative_child, slots_15.io.out_uop.iw_p1_speculative_child connect issue_slots[15].out_uop.iw_issued_partial_dgen, slots_15.io.out_uop.iw_issued_partial_dgen connect issue_slots[15].out_uop.iw_issued_partial_agen, slots_15.io.out_uop.iw_issued_partial_agen connect issue_slots[15].out_uop.iw_issued, slots_15.io.out_uop.iw_issued connect issue_slots[15].out_uop.fu_code[0], slots_15.io.out_uop.fu_code[0] connect issue_slots[15].out_uop.fu_code[1], slots_15.io.out_uop.fu_code[1] connect issue_slots[15].out_uop.fu_code[2], slots_15.io.out_uop.fu_code[2] connect issue_slots[15].out_uop.fu_code[3], slots_15.io.out_uop.fu_code[3] connect issue_slots[15].out_uop.fu_code[4], slots_15.io.out_uop.fu_code[4] connect issue_slots[15].out_uop.fu_code[5], slots_15.io.out_uop.fu_code[5] connect issue_slots[15].out_uop.fu_code[6], slots_15.io.out_uop.fu_code[6] connect issue_slots[15].out_uop.fu_code[7], slots_15.io.out_uop.fu_code[7] connect issue_slots[15].out_uop.fu_code[8], slots_15.io.out_uop.fu_code[8] connect issue_slots[15].out_uop.fu_code[9], slots_15.io.out_uop.fu_code[9] connect issue_slots[15].out_uop.iq_type[0], slots_15.io.out_uop.iq_type[0] connect issue_slots[15].out_uop.iq_type[1], slots_15.io.out_uop.iq_type[1] connect issue_slots[15].out_uop.iq_type[2], slots_15.io.out_uop.iq_type[2] connect issue_slots[15].out_uop.iq_type[3], slots_15.io.out_uop.iq_type[3] connect issue_slots[15].out_uop.debug_pc, slots_15.io.out_uop.debug_pc connect issue_slots[15].out_uop.is_rvc, slots_15.io.out_uop.is_rvc connect issue_slots[15].out_uop.debug_inst, slots_15.io.out_uop.debug_inst connect issue_slots[15].out_uop.inst, slots_15.io.out_uop.inst connect slots_15.io.in_uop.bits.debug_tsrc, issue_slots[15].in_uop.bits.debug_tsrc connect slots_15.io.in_uop.bits.debug_fsrc, issue_slots[15].in_uop.bits.debug_fsrc connect slots_15.io.in_uop.bits.bp_xcpt_if, issue_slots[15].in_uop.bits.bp_xcpt_if connect slots_15.io.in_uop.bits.bp_debug_if, issue_slots[15].in_uop.bits.bp_debug_if connect slots_15.io.in_uop.bits.xcpt_ma_if, issue_slots[15].in_uop.bits.xcpt_ma_if connect slots_15.io.in_uop.bits.xcpt_ae_if, issue_slots[15].in_uop.bits.xcpt_ae_if connect slots_15.io.in_uop.bits.xcpt_pf_if, issue_slots[15].in_uop.bits.xcpt_pf_if connect slots_15.io.in_uop.bits.fp_typ, issue_slots[15].in_uop.bits.fp_typ connect slots_15.io.in_uop.bits.fp_rm, issue_slots[15].in_uop.bits.fp_rm connect slots_15.io.in_uop.bits.fp_val, issue_slots[15].in_uop.bits.fp_val connect slots_15.io.in_uop.bits.fcn_op, issue_slots[15].in_uop.bits.fcn_op connect slots_15.io.in_uop.bits.fcn_dw, issue_slots[15].in_uop.bits.fcn_dw connect slots_15.io.in_uop.bits.frs3_en, issue_slots[15].in_uop.bits.frs3_en connect slots_15.io.in_uop.bits.lrs2_rtype, issue_slots[15].in_uop.bits.lrs2_rtype connect slots_15.io.in_uop.bits.lrs1_rtype, issue_slots[15].in_uop.bits.lrs1_rtype connect slots_15.io.in_uop.bits.dst_rtype, issue_slots[15].in_uop.bits.dst_rtype connect slots_15.io.in_uop.bits.lrs3, issue_slots[15].in_uop.bits.lrs3 connect slots_15.io.in_uop.bits.lrs2, issue_slots[15].in_uop.bits.lrs2 connect slots_15.io.in_uop.bits.lrs1, issue_slots[15].in_uop.bits.lrs1 connect slots_15.io.in_uop.bits.ldst, issue_slots[15].in_uop.bits.ldst connect slots_15.io.in_uop.bits.ldst_is_rs1, issue_slots[15].in_uop.bits.ldst_is_rs1 connect slots_15.io.in_uop.bits.csr_cmd, issue_slots[15].in_uop.bits.csr_cmd connect slots_15.io.in_uop.bits.flush_on_commit, issue_slots[15].in_uop.bits.flush_on_commit connect slots_15.io.in_uop.bits.is_unique, issue_slots[15].in_uop.bits.is_unique connect slots_15.io.in_uop.bits.uses_stq, issue_slots[15].in_uop.bits.uses_stq connect slots_15.io.in_uop.bits.uses_ldq, issue_slots[15].in_uop.bits.uses_ldq connect slots_15.io.in_uop.bits.mem_signed, issue_slots[15].in_uop.bits.mem_signed connect slots_15.io.in_uop.bits.mem_size, issue_slots[15].in_uop.bits.mem_size connect slots_15.io.in_uop.bits.mem_cmd, issue_slots[15].in_uop.bits.mem_cmd connect slots_15.io.in_uop.bits.exc_cause, issue_slots[15].in_uop.bits.exc_cause connect slots_15.io.in_uop.bits.exception, issue_slots[15].in_uop.bits.exception connect slots_15.io.in_uop.bits.stale_pdst, issue_slots[15].in_uop.bits.stale_pdst connect slots_15.io.in_uop.bits.ppred_busy, issue_slots[15].in_uop.bits.ppred_busy connect slots_15.io.in_uop.bits.prs3_busy, issue_slots[15].in_uop.bits.prs3_busy connect slots_15.io.in_uop.bits.prs2_busy, issue_slots[15].in_uop.bits.prs2_busy connect slots_15.io.in_uop.bits.prs1_busy, issue_slots[15].in_uop.bits.prs1_busy connect slots_15.io.in_uop.bits.ppred, issue_slots[15].in_uop.bits.ppred connect slots_15.io.in_uop.bits.prs3, issue_slots[15].in_uop.bits.prs3 connect slots_15.io.in_uop.bits.prs2, issue_slots[15].in_uop.bits.prs2 connect slots_15.io.in_uop.bits.prs1, issue_slots[15].in_uop.bits.prs1 connect slots_15.io.in_uop.bits.pdst, issue_slots[15].in_uop.bits.pdst connect slots_15.io.in_uop.bits.rxq_idx, issue_slots[15].in_uop.bits.rxq_idx connect slots_15.io.in_uop.bits.stq_idx, issue_slots[15].in_uop.bits.stq_idx connect slots_15.io.in_uop.bits.ldq_idx, issue_slots[15].in_uop.bits.ldq_idx connect slots_15.io.in_uop.bits.rob_idx, issue_slots[15].in_uop.bits.rob_idx connect slots_15.io.in_uop.bits.fp_ctrl.vec, issue_slots[15].in_uop.bits.fp_ctrl.vec connect slots_15.io.in_uop.bits.fp_ctrl.wflags, issue_slots[15].in_uop.bits.fp_ctrl.wflags connect slots_15.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[15].in_uop.bits.fp_ctrl.sqrt connect slots_15.io.in_uop.bits.fp_ctrl.div, issue_slots[15].in_uop.bits.fp_ctrl.div connect slots_15.io.in_uop.bits.fp_ctrl.fma, issue_slots[15].in_uop.bits.fp_ctrl.fma connect slots_15.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[15].in_uop.bits.fp_ctrl.fastpipe connect slots_15.io.in_uop.bits.fp_ctrl.toint, issue_slots[15].in_uop.bits.fp_ctrl.toint connect slots_15.io.in_uop.bits.fp_ctrl.fromint, issue_slots[15].in_uop.bits.fp_ctrl.fromint connect slots_15.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[15].in_uop.bits.fp_ctrl.typeTagOut connect slots_15.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[15].in_uop.bits.fp_ctrl.typeTagIn connect slots_15.io.in_uop.bits.fp_ctrl.swap23, issue_slots[15].in_uop.bits.fp_ctrl.swap23 connect slots_15.io.in_uop.bits.fp_ctrl.swap12, issue_slots[15].in_uop.bits.fp_ctrl.swap12 connect slots_15.io.in_uop.bits.fp_ctrl.ren3, issue_slots[15].in_uop.bits.fp_ctrl.ren3 connect slots_15.io.in_uop.bits.fp_ctrl.ren2, issue_slots[15].in_uop.bits.fp_ctrl.ren2 connect slots_15.io.in_uop.bits.fp_ctrl.ren1, issue_slots[15].in_uop.bits.fp_ctrl.ren1 connect slots_15.io.in_uop.bits.fp_ctrl.wen, issue_slots[15].in_uop.bits.fp_ctrl.wen connect slots_15.io.in_uop.bits.fp_ctrl.ldst, issue_slots[15].in_uop.bits.fp_ctrl.ldst connect slots_15.io.in_uop.bits.op2_sel, issue_slots[15].in_uop.bits.op2_sel connect slots_15.io.in_uop.bits.op1_sel, issue_slots[15].in_uop.bits.op1_sel connect slots_15.io.in_uop.bits.imm_packed, issue_slots[15].in_uop.bits.imm_packed connect slots_15.io.in_uop.bits.pimm, issue_slots[15].in_uop.bits.pimm connect slots_15.io.in_uop.bits.imm_sel, issue_slots[15].in_uop.bits.imm_sel connect slots_15.io.in_uop.bits.imm_rename, issue_slots[15].in_uop.bits.imm_rename connect slots_15.io.in_uop.bits.taken, issue_slots[15].in_uop.bits.taken connect slots_15.io.in_uop.bits.pc_lob, issue_slots[15].in_uop.bits.pc_lob connect slots_15.io.in_uop.bits.edge_inst, issue_slots[15].in_uop.bits.edge_inst connect slots_15.io.in_uop.bits.ftq_idx, issue_slots[15].in_uop.bits.ftq_idx connect slots_15.io.in_uop.bits.is_mov, issue_slots[15].in_uop.bits.is_mov connect slots_15.io.in_uop.bits.is_rocc, issue_slots[15].in_uop.bits.is_rocc connect slots_15.io.in_uop.bits.is_sys_pc2epc, issue_slots[15].in_uop.bits.is_sys_pc2epc connect slots_15.io.in_uop.bits.is_eret, issue_slots[15].in_uop.bits.is_eret connect slots_15.io.in_uop.bits.is_amo, issue_slots[15].in_uop.bits.is_amo connect slots_15.io.in_uop.bits.is_sfence, issue_slots[15].in_uop.bits.is_sfence connect slots_15.io.in_uop.bits.is_fencei, issue_slots[15].in_uop.bits.is_fencei connect slots_15.io.in_uop.bits.is_fence, issue_slots[15].in_uop.bits.is_fence connect slots_15.io.in_uop.bits.is_sfb, issue_slots[15].in_uop.bits.is_sfb connect slots_15.io.in_uop.bits.br_type, issue_slots[15].in_uop.bits.br_type connect slots_15.io.in_uop.bits.br_tag, issue_slots[15].in_uop.bits.br_tag connect slots_15.io.in_uop.bits.br_mask, issue_slots[15].in_uop.bits.br_mask connect slots_15.io.in_uop.bits.dis_col_sel, issue_slots[15].in_uop.bits.dis_col_sel connect slots_15.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[15].in_uop.bits.iw_p3_bypass_hint connect slots_15.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[15].in_uop.bits.iw_p2_bypass_hint connect slots_15.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[15].in_uop.bits.iw_p1_bypass_hint connect slots_15.io.in_uop.bits.iw_p2_speculative_child, issue_slots[15].in_uop.bits.iw_p2_speculative_child connect slots_15.io.in_uop.bits.iw_p1_speculative_child, issue_slots[15].in_uop.bits.iw_p1_speculative_child connect slots_15.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[15].in_uop.bits.iw_issued_partial_dgen connect slots_15.io.in_uop.bits.iw_issued_partial_agen, issue_slots[15].in_uop.bits.iw_issued_partial_agen connect slots_15.io.in_uop.bits.iw_issued, issue_slots[15].in_uop.bits.iw_issued connect slots_15.io.in_uop.bits.fu_code[0], issue_slots[15].in_uop.bits.fu_code[0] connect slots_15.io.in_uop.bits.fu_code[1], issue_slots[15].in_uop.bits.fu_code[1] connect slots_15.io.in_uop.bits.fu_code[2], issue_slots[15].in_uop.bits.fu_code[2] connect slots_15.io.in_uop.bits.fu_code[3], issue_slots[15].in_uop.bits.fu_code[3] connect slots_15.io.in_uop.bits.fu_code[4], issue_slots[15].in_uop.bits.fu_code[4] connect slots_15.io.in_uop.bits.fu_code[5], issue_slots[15].in_uop.bits.fu_code[5] connect slots_15.io.in_uop.bits.fu_code[6], issue_slots[15].in_uop.bits.fu_code[6] connect slots_15.io.in_uop.bits.fu_code[7], issue_slots[15].in_uop.bits.fu_code[7] connect slots_15.io.in_uop.bits.fu_code[8], issue_slots[15].in_uop.bits.fu_code[8] connect slots_15.io.in_uop.bits.fu_code[9], issue_slots[15].in_uop.bits.fu_code[9] connect slots_15.io.in_uop.bits.iq_type[0], issue_slots[15].in_uop.bits.iq_type[0] connect slots_15.io.in_uop.bits.iq_type[1], issue_slots[15].in_uop.bits.iq_type[1] connect slots_15.io.in_uop.bits.iq_type[2], issue_slots[15].in_uop.bits.iq_type[2] connect slots_15.io.in_uop.bits.iq_type[3], issue_slots[15].in_uop.bits.iq_type[3] connect slots_15.io.in_uop.bits.debug_pc, issue_slots[15].in_uop.bits.debug_pc connect slots_15.io.in_uop.bits.is_rvc, issue_slots[15].in_uop.bits.is_rvc connect slots_15.io.in_uop.bits.debug_inst, issue_slots[15].in_uop.bits.debug_inst connect slots_15.io.in_uop.bits.inst, issue_slots[15].in_uop.bits.inst connect slots_15.io.in_uop.valid, issue_slots[15].in_uop.valid connect issue_slots[15].iss_uop.debug_tsrc, slots_15.io.iss_uop.debug_tsrc connect issue_slots[15].iss_uop.debug_fsrc, slots_15.io.iss_uop.debug_fsrc connect issue_slots[15].iss_uop.bp_xcpt_if, slots_15.io.iss_uop.bp_xcpt_if connect issue_slots[15].iss_uop.bp_debug_if, slots_15.io.iss_uop.bp_debug_if connect issue_slots[15].iss_uop.xcpt_ma_if, slots_15.io.iss_uop.xcpt_ma_if connect issue_slots[15].iss_uop.xcpt_ae_if, slots_15.io.iss_uop.xcpt_ae_if connect issue_slots[15].iss_uop.xcpt_pf_if, slots_15.io.iss_uop.xcpt_pf_if connect issue_slots[15].iss_uop.fp_typ, slots_15.io.iss_uop.fp_typ connect issue_slots[15].iss_uop.fp_rm, slots_15.io.iss_uop.fp_rm connect issue_slots[15].iss_uop.fp_val, slots_15.io.iss_uop.fp_val connect issue_slots[15].iss_uop.fcn_op, slots_15.io.iss_uop.fcn_op connect issue_slots[15].iss_uop.fcn_dw, slots_15.io.iss_uop.fcn_dw connect issue_slots[15].iss_uop.frs3_en, slots_15.io.iss_uop.frs3_en connect issue_slots[15].iss_uop.lrs2_rtype, slots_15.io.iss_uop.lrs2_rtype connect issue_slots[15].iss_uop.lrs1_rtype, slots_15.io.iss_uop.lrs1_rtype connect issue_slots[15].iss_uop.dst_rtype, slots_15.io.iss_uop.dst_rtype connect issue_slots[15].iss_uop.lrs3, slots_15.io.iss_uop.lrs3 connect issue_slots[15].iss_uop.lrs2, slots_15.io.iss_uop.lrs2 connect issue_slots[15].iss_uop.lrs1, slots_15.io.iss_uop.lrs1 connect issue_slots[15].iss_uop.ldst, slots_15.io.iss_uop.ldst connect issue_slots[15].iss_uop.ldst_is_rs1, slots_15.io.iss_uop.ldst_is_rs1 connect issue_slots[15].iss_uop.csr_cmd, slots_15.io.iss_uop.csr_cmd connect issue_slots[15].iss_uop.flush_on_commit, slots_15.io.iss_uop.flush_on_commit connect issue_slots[15].iss_uop.is_unique, slots_15.io.iss_uop.is_unique connect issue_slots[15].iss_uop.uses_stq, slots_15.io.iss_uop.uses_stq connect issue_slots[15].iss_uop.uses_ldq, slots_15.io.iss_uop.uses_ldq connect issue_slots[15].iss_uop.mem_signed, slots_15.io.iss_uop.mem_signed connect issue_slots[15].iss_uop.mem_size, slots_15.io.iss_uop.mem_size connect issue_slots[15].iss_uop.mem_cmd, slots_15.io.iss_uop.mem_cmd connect issue_slots[15].iss_uop.exc_cause, slots_15.io.iss_uop.exc_cause connect issue_slots[15].iss_uop.exception, slots_15.io.iss_uop.exception connect issue_slots[15].iss_uop.stale_pdst, slots_15.io.iss_uop.stale_pdst connect issue_slots[15].iss_uop.ppred_busy, slots_15.io.iss_uop.ppred_busy connect issue_slots[15].iss_uop.prs3_busy, slots_15.io.iss_uop.prs3_busy connect issue_slots[15].iss_uop.prs2_busy, slots_15.io.iss_uop.prs2_busy connect issue_slots[15].iss_uop.prs1_busy, slots_15.io.iss_uop.prs1_busy connect issue_slots[15].iss_uop.ppred, slots_15.io.iss_uop.ppred connect issue_slots[15].iss_uop.prs3, slots_15.io.iss_uop.prs3 connect issue_slots[15].iss_uop.prs2, slots_15.io.iss_uop.prs2 connect issue_slots[15].iss_uop.prs1, slots_15.io.iss_uop.prs1 connect issue_slots[15].iss_uop.pdst, slots_15.io.iss_uop.pdst connect issue_slots[15].iss_uop.rxq_idx, slots_15.io.iss_uop.rxq_idx connect issue_slots[15].iss_uop.stq_idx, slots_15.io.iss_uop.stq_idx connect issue_slots[15].iss_uop.ldq_idx, slots_15.io.iss_uop.ldq_idx connect issue_slots[15].iss_uop.rob_idx, slots_15.io.iss_uop.rob_idx connect issue_slots[15].iss_uop.fp_ctrl.vec, slots_15.io.iss_uop.fp_ctrl.vec connect issue_slots[15].iss_uop.fp_ctrl.wflags, slots_15.io.iss_uop.fp_ctrl.wflags connect issue_slots[15].iss_uop.fp_ctrl.sqrt, slots_15.io.iss_uop.fp_ctrl.sqrt connect issue_slots[15].iss_uop.fp_ctrl.div, slots_15.io.iss_uop.fp_ctrl.div connect issue_slots[15].iss_uop.fp_ctrl.fma, slots_15.io.iss_uop.fp_ctrl.fma connect issue_slots[15].iss_uop.fp_ctrl.fastpipe, slots_15.io.iss_uop.fp_ctrl.fastpipe connect issue_slots[15].iss_uop.fp_ctrl.toint, slots_15.io.iss_uop.fp_ctrl.toint connect issue_slots[15].iss_uop.fp_ctrl.fromint, slots_15.io.iss_uop.fp_ctrl.fromint connect issue_slots[15].iss_uop.fp_ctrl.typeTagOut, slots_15.io.iss_uop.fp_ctrl.typeTagOut connect issue_slots[15].iss_uop.fp_ctrl.typeTagIn, slots_15.io.iss_uop.fp_ctrl.typeTagIn connect issue_slots[15].iss_uop.fp_ctrl.swap23, slots_15.io.iss_uop.fp_ctrl.swap23 connect issue_slots[15].iss_uop.fp_ctrl.swap12, slots_15.io.iss_uop.fp_ctrl.swap12 connect issue_slots[15].iss_uop.fp_ctrl.ren3, slots_15.io.iss_uop.fp_ctrl.ren3 connect issue_slots[15].iss_uop.fp_ctrl.ren2, slots_15.io.iss_uop.fp_ctrl.ren2 connect issue_slots[15].iss_uop.fp_ctrl.ren1, slots_15.io.iss_uop.fp_ctrl.ren1 connect issue_slots[15].iss_uop.fp_ctrl.wen, slots_15.io.iss_uop.fp_ctrl.wen connect issue_slots[15].iss_uop.fp_ctrl.ldst, slots_15.io.iss_uop.fp_ctrl.ldst connect issue_slots[15].iss_uop.op2_sel, slots_15.io.iss_uop.op2_sel connect issue_slots[15].iss_uop.op1_sel, slots_15.io.iss_uop.op1_sel connect issue_slots[15].iss_uop.imm_packed, slots_15.io.iss_uop.imm_packed connect issue_slots[15].iss_uop.pimm, slots_15.io.iss_uop.pimm connect issue_slots[15].iss_uop.imm_sel, slots_15.io.iss_uop.imm_sel connect issue_slots[15].iss_uop.imm_rename, slots_15.io.iss_uop.imm_rename connect issue_slots[15].iss_uop.taken, slots_15.io.iss_uop.taken connect issue_slots[15].iss_uop.pc_lob, slots_15.io.iss_uop.pc_lob connect issue_slots[15].iss_uop.edge_inst, slots_15.io.iss_uop.edge_inst connect issue_slots[15].iss_uop.ftq_idx, slots_15.io.iss_uop.ftq_idx connect issue_slots[15].iss_uop.is_mov, slots_15.io.iss_uop.is_mov connect issue_slots[15].iss_uop.is_rocc, slots_15.io.iss_uop.is_rocc connect issue_slots[15].iss_uop.is_sys_pc2epc, slots_15.io.iss_uop.is_sys_pc2epc connect issue_slots[15].iss_uop.is_eret, slots_15.io.iss_uop.is_eret connect issue_slots[15].iss_uop.is_amo, slots_15.io.iss_uop.is_amo connect issue_slots[15].iss_uop.is_sfence, slots_15.io.iss_uop.is_sfence connect issue_slots[15].iss_uop.is_fencei, slots_15.io.iss_uop.is_fencei connect issue_slots[15].iss_uop.is_fence, slots_15.io.iss_uop.is_fence connect issue_slots[15].iss_uop.is_sfb, slots_15.io.iss_uop.is_sfb connect issue_slots[15].iss_uop.br_type, slots_15.io.iss_uop.br_type connect issue_slots[15].iss_uop.br_tag, slots_15.io.iss_uop.br_tag connect issue_slots[15].iss_uop.br_mask, slots_15.io.iss_uop.br_mask connect issue_slots[15].iss_uop.dis_col_sel, slots_15.io.iss_uop.dis_col_sel connect issue_slots[15].iss_uop.iw_p3_bypass_hint, slots_15.io.iss_uop.iw_p3_bypass_hint connect issue_slots[15].iss_uop.iw_p2_bypass_hint, slots_15.io.iss_uop.iw_p2_bypass_hint connect issue_slots[15].iss_uop.iw_p1_bypass_hint, slots_15.io.iss_uop.iw_p1_bypass_hint connect issue_slots[15].iss_uop.iw_p2_speculative_child, slots_15.io.iss_uop.iw_p2_speculative_child connect issue_slots[15].iss_uop.iw_p1_speculative_child, slots_15.io.iss_uop.iw_p1_speculative_child connect issue_slots[15].iss_uop.iw_issued_partial_dgen, slots_15.io.iss_uop.iw_issued_partial_dgen connect issue_slots[15].iss_uop.iw_issued_partial_agen, slots_15.io.iss_uop.iw_issued_partial_agen connect issue_slots[15].iss_uop.iw_issued, slots_15.io.iss_uop.iw_issued connect issue_slots[15].iss_uop.fu_code[0], slots_15.io.iss_uop.fu_code[0] connect issue_slots[15].iss_uop.fu_code[1], slots_15.io.iss_uop.fu_code[1] connect issue_slots[15].iss_uop.fu_code[2], slots_15.io.iss_uop.fu_code[2] connect issue_slots[15].iss_uop.fu_code[3], slots_15.io.iss_uop.fu_code[3] connect issue_slots[15].iss_uop.fu_code[4], slots_15.io.iss_uop.fu_code[4] connect issue_slots[15].iss_uop.fu_code[5], slots_15.io.iss_uop.fu_code[5] connect issue_slots[15].iss_uop.fu_code[6], slots_15.io.iss_uop.fu_code[6] connect issue_slots[15].iss_uop.fu_code[7], slots_15.io.iss_uop.fu_code[7] connect issue_slots[15].iss_uop.fu_code[8], slots_15.io.iss_uop.fu_code[8] connect issue_slots[15].iss_uop.fu_code[9], slots_15.io.iss_uop.fu_code[9] connect issue_slots[15].iss_uop.iq_type[0], slots_15.io.iss_uop.iq_type[0] connect issue_slots[15].iss_uop.iq_type[1], slots_15.io.iss_uop.iq_type[1] connect issue_slots[15].iss_uop.iq_type[2], slots_15.io.iss_uop.iq_type[2] connect issue_slots[15].iss_uop.iq_type[3], slots_15.io.iss_uop.iq_type[3] connect issue_slots[15].iss_uop.debug_pc, slots_15.io.iss_uop.debug_pc connect issue_slots[15].iss_uop.is_rvc, slots_15.io.iss_uop.is_rvc connect issue_slots[15].iss_uop.debug_inst, slots_15.io.iss_uop.debug_inst connect issue_slots[15].iss_uop.inst, slots_15.io.iss_uop.inst connect slots_15.io.grant, issue_slots[15].grant connect issue_slots[15].request, slots_15.io.request connect issue_slots[15].will_be_valid, slots_15.io.will_be_valid connect issue_slots[15].valid, slots_15.io.valid connect issue_slots[0].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy connect issue_slots[0].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask connect issue_slots[0].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable connect issue_slots[0].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc connect issue_slots[0].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc connect issue_slots[0].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if connect issue_slots[0].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if connect issue_slots[0].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if connect issue_slots[0].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if connect issue_slots[0].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if connect issue_slots[0].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ connect issue_slots[0].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm connect issue_slots[0].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val connect issue_slots[0].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op connect issue_slots[0].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw connect issue_slots[0].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en connect issue_slots[0].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype connect issue_slots[0].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype connect issue_slots[0].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype connect issue_slots[0].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 connect issue_slots[0].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 connect issue_slots[0].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 connect issue_slots[0].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst connect issue_slots[0].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 connect issue_slots[0].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd connect issue_slots[0].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit connect issue_slots[0].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique connect issue_slots[0].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq connect issue_slots[0].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq connect issue_slots[0].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed connect issue_slots[0].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size connect issue_slots[0].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd connect issue_slots[0].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause connect issue_slots[0].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception connect issue_slots[0].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst connect issue_slots[0].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy connect issue_slots[0].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy connect issue_slots[0].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy connect issue_slots[0].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy connect issue_slots[0].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred connect issue_slots[0].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 connect issue_slots[0].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 connect issue_slots[0].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 connect issue_slots[0].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst connect issue_slots[0].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx connect issue_slots[0].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx connect issue_slots[0].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx connect issue_slots[0].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst connect issue_slots[0].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel connect issue_slots[0].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel connect issue_slots[0].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed connect issue_slots[0].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm connect issue_slots[0].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel connect issue_slots[0].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename connect issue_slots[0].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken connect issue_slots[0].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob connect issue_slots[0].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst connect issue_slots[0].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx connect issue_slots[0].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov connect issue_slots[0].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc connect issue_slots[0].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc connect issue_slots[0].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret connect issue_slots[0].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo connect issue_slots[0].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence connect issue_slots[0].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei connect issue_slots[0].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence connect issue_slots[0].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb connect issue_slots[0].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type connect issue_slots[0].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag connect issue_slots[0].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask connect issue_slots[0].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel connect issue_slots[0].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect issue_slots[0].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect issue_slots[0].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect issue_slots[0].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child connect issue_slots[0].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child connect issue_slots[0].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect issue_slots[0].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen connect issue_slots[0].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued connect issue_slots[0].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] connect issue_slots[0].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] connect issue_slots[0].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] connect issue_slots[0].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] connect issue_slots[0].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] connect issue_slots[0].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] connect issue_slots[0].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] connect issue_slots[0].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] connect issue_slots[0].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] connect issue_slots[0].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] connect issue_slots[0].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] connect issue_slots[0].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] connect issue_slots[0].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] connect issue_slots[0].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] connect issue_slots[0].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc connect issue_slots[0].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc connect issue_slots[0].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst connect issue_slots[0].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst connect issue_slots[0].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[0].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy connect issue_slots[0].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask connect issue_slots[0].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable connect issue_slots[0].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc connect issue_slots[0].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc connect issue_slots[0].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if connect issue_slots[0].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if connect issue_slots[0].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if connect issue_slots[0].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if connect issue_slots[0].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if connect issue_slots[0].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ connect issue_slots[0].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm connect issue_slots[0].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val connect issue_slots[0].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op connect issue_slots[0].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw connect issue_slots[0].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en connect issue_slots[0].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype connect issue_slots[0].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype connect issue_slots[0].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype connect issue_slots[0].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 connect issue_slots[0].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 connect issue_slots[0].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 connect issue_slots[0].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst connect issue_slots[0].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 connect issue_slots[0].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd connect issue_slots[0].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit connect issue_slots[0].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique connect issue_slots[0].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq connect issue_slots[0].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq connect issue_slots[0].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed connect issue_slots[0].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size connect issue_slots[0].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd connect issue_slots[0].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause connect issue_slots[0].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception connect issue_slots[0].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst connect issue_slots[0].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy connect issue_slots[0].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy connect issue_slots[0].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy connect issue_slots[0].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy connect issue_slots[0].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred connect issue_slots[0].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 connect issue_slots[0].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 connect issue_slots[0].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 connect issue_slots[0].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst connect issue_slots[0].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx connect issue_slots[0].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx connect issue_slots[0].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx connect issue_slots[0].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst connect issue_slots[0].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel connect issue_slots[0].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel connect issue_slots[0].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed connect issue_slots[0].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm connect issue_slots[0].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel connect issue_slots[0].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename connect issue_slots[0].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken connect issue_slots[0].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob connect issue_slots[0].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst connect issue_slots[0].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx connect issue_slots[0].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov connect issue_slots[0].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc connect issue_slots[0].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc connect issue_slots[0].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret connect issue_slots[0].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo connect issue_slots[0].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence connect issue_slots[0].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei connect issue_slots[0].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence connect issue_slots[0].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb connect issue_slots[0].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type connect issue_slots[0].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag connect issue_slots[0].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask connect issue_slots[0].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel connect issue_slots[0].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect issue_slots[0].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect issue_slots[0].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect issue_slots[0].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child connect issue_slots[0].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child connect issue_slots[0].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect issue_slots[0].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen connect issue_slots[0].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued connect issue_slots[0].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] connect issue_slots[0].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] connect issue_slots[0].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] connect issue_slots[0].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] connect issue_slots[0].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] connect issue_slots[0].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] connect issue_slots[0].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] connect issue_slots[0].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] connect issue_slots[0].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] connect issue_slots[0].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] connect issue_slots[0].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] connect issue_slots[0].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] connect issue_slots[0].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] connect issue_slots[0].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] connect issue_slots[0].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc connect issue_slots[0].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc connect issue_slots[0].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst connect issue_slots[0].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst connect issue_slots[0].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[0].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy connect issue_slots[0].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask connect issue_slots[0].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable connect issue_slots[0].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc connect issue_slots[0].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc connect issue_slots[0].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if connect issue_slots[0].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if connect issue_slots[0].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if connect issue_slots[0].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if connect issue_slots[0].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if connect issue_slots[0].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ connect issue_slots[0].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm connect issue_slots[0].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val connect issue_slots[0].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op connect issue_slots[0].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw connect issue_slots[0].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en connect issue_slots[0].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype connect issue_slots[0].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype connect issue_slots[0].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype connect issue_slots[0].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3 connect issue_slots[0].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2 connect issue_slots[0].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1 connect issue_slots[0].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst connect issue_slots[0].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1 connect issue_slots[0].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd connect issue_slots[0].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit connect issue_slots[0].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique connect issue_slots[0].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq connect issue_slots[0].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq connect issue_slots[0].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed connect issue_slots[0].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size connect issue_slots[0].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd connect issue_slots[0].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause connect issue_slots[0].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception connect issue_slots[0].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst connect issue_slots[0].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy connect issue_slots[0].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy connect issue_slots[0].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy connect issue_slots[0].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy connect issue_slots[0].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred connect issue_slots[0].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3 connect issue_slots[0].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2 connect issue_slots[0].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1 connect issue_slots[0].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst connect issue_slots[0].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx connect issue_slots[0].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx connect issue_slots[0].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx connect issue_slots[0].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen connect issue_slots[0].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst connect issue_slots[0].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel connect issue_slots[0].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel connect issue_slots[0].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed connect issue_slots[0].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm connect issue_slots[0].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel connect issue_slots[0].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename connect issue_slots[0].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken connect issue_slots[0].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob connect issue_slots[0].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst connect issue_slots[0].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx connect issue_slots[0].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov connect issue_slots[0].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc connect issue_slots[0].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc connect issue_slots[0].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret connect issue_slots[0].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo connect issue_slots[0].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence connect issue_slots[0].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei connect issue_slots[0].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence connect issue_slots[0].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb connect issue_slots[0].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type connect issue_slots[0].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag connect issue_slots[0].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask connect issue_slots[0].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel connect issue_slots[0].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect issue_slots[0].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect issue_slots[0].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect issue_slots[0].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child connect issue_slots[0].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child connect issue_slots[0].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect issue_slots[0].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen connect issue_slots[0].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued connect issue_slots[0].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0] connect issue_slots[0].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1] connect issue_slots[0].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2] connect issue_slots[0].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3] connect issue_slots[0].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4] connect issue_slots[0].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5] connect issue_slots[0].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6] connect issue_slots[0].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7] connect issue_slots[0].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8] connect issue_slots[0].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9] connect issue_slots[0].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0] connect issue_slots[0].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1] connect issue_slots[0].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2] connect issue_slots[0].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3] connect issue_slots[0].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc connect issue_slots[0].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc connect issue_slots[0].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst connect issue_slots[0].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst connect issue_slots[0].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[0].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy connect issue_slots[0].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask connect issue_slots[0].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable connect issue_slots[0].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc connect issue_slots[0].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc connect issue_slots[0].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if connect issue_slots[0].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if connect issue_slots[0].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if connect issue_slots[0].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if connect issue_slots[0].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if connect issue_slots[0].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ connect issue_slots[0].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm connect issue_slots[0].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val connect issue_slots[0].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op connect issue_slots[0].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw connect issue_slots[0].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en connect issue_slots[0].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype connect issue_slots[0].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype connect issue_slots[0].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype connect issue_slots[0].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3 connect issue_slots[0].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2 connect issue_slots[0].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1 connect issue_slots[0].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst connect issue_slots[0].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1 connect issue_slots[0].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd connect issue_slots[0].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit connect issue_slots[0].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique connect issue_slots[0].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq connect issue_slots[0].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq connect issue_slots[0].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed connect issue_slots[0].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size connect issue_slots[0].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd connect issue_slots[0].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause connect issue_slots[0].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception connect issue_slots[0].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst connect issue_slots[0].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy connect issue_slots[0].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy connect issue_slots[0].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy connect issue_slots[0].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy connect issue_slots[0].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred connect issue_slots[0].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3 connect issue_slots[0].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2 connect issue_slots[0].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1 connect issue_slots[0].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst connect issue_slots[0].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx connect issue_slots[0].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx connect issue_slots[0].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx connect issue_slots[0].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen connect issue_slots[0].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst connect issue_slots[0].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel connect issue_slots[0].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel connect issue_slots[0].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed connect issue_slots[0].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm connect issue_slots[0].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel connect issue_slots[0].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename connect issue_slots[0].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken connect issue_slots[0].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob connect issue_slots[0].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst connect issue_slots[0].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx connect issue_slots[0].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov connect issue_slots[0].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc connect issue_slots[0].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc connect issue_slots[0].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret connect issue_slots[0].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo connect issue_slots[0].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence connect issue_slots[0].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei connect issue_slots[0].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence connect issue_slots[0].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb connect issue_slots[0].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type connect issue_slots[0].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag connect issue_slots[0].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask connect issue_slots[0].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel connect issue_slots[0].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect issue_slots[0].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect issue_slots[0].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect issue_slots[0].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child connect issue_slots[0].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child connect issue_slots[0].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect issue_slots[0].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen connect issue_slots[0].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued connect issue_slots[0].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0] connect issue_slots[0].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1] connect issue_slots[0].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2] connect issue_slots[0].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3] connect issue_slots[0].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4] connect issue_slots[0].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5] connect issue_slots[0].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6] connect issue_slots[0].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7] connect issue_slots[0].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8] connect issue_slots[0].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9] connect issue_slots[0].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0] connect issue_slots[0].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1] connect issue_slots[0].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2] connect issue_slots[0].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3] connect issue_slots[0].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc connect issue_slots[0].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc connect issue_slots[0].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst connect issue_slots[0].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst connect issue_slots[0].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[0].wakeup_ports[4].bits.rebusy, io.wakeup_ports[4].bits.rebusy connect issue_slots[0].wakeup_ports[4].bits.speculative_mask, io.wakeup_ports[4].bits.speculative_mask connect issue_slots[0].wakeup_ports[4].bits.bypassable, io.wakeup_ports[4].bits.bypassable connect issue_slots[0].wakeup_ports[4].bits.uop.debug_tsrc, io.wakeup_ports[4].bits.uop.debug_tsrc connect issue_slots[0].wakeup_ports[4].bits.uop.debug_fsrc, io.wakeup_ports[4].bits.uop.debug_fsrc connect issue_slots[0].wakeup_ports[4].bits.uop.bp_xcpt_if, io.wakeup_ports[4].bits.uop.bp_xcpt_if connect issue_slots[0].wakeup_ports[4].bits.uop.bp_debug_if, io.wakeup_ports[4].bits.uop.bp_debug_if connect issue_slots[0].wakeup_ports[4].bits.uop.xcpt_ma_if, io.wakeup_ports[4].bits.uop.xcpt_ma_if connect issue_slots[0].wakeup_ports[4].bits.uop.xcpt_ae_if, io.wakeup_ports[4].bits.uop.xcpt_ae_if connect issue_slots[0].wakeup_ports[4].bits.uop.xcpt_pf_if, io.wakeup_ports[4].bits.uop.xcpt_pf_if connect issue_slots[0].wakeup_ports[4].bits.uop.fp_typ, io.wakeup_ports[4].bits.uop.fp_typ connect issue_slots[0].wakeup_ports[4].bits.uop.fp_rm, io.wakeup_ports[4].bits.uop.fp_rm connect issue_slots[0].wakeup_ports[4].bits.uop.fp_val, io.wakeup_ports[4].bits.uop.fp_val connect issue_slots[0].wakeup_ports[4].bits.uop.fcn_op, io.wakeup_ports[4].bits.uop.fcn_op connect issue_slots[0].wakeup_ports[4].bits.uop.fcn_dw, io.wakeup_ports[4].bits.uop.fcn_dw connect issue_slots[0].wakeup_ports[4].bits.uop.frs3_en, io.wakeup_ports[4].bits.uop.frs3_en connect issue_slots[0].wakeup_ports[4].bits.uop.lrs2_rtype, io.wakeup_ports[4].bits.uop.lrs2_rtype connect issue_slots[0].wakeup_ports[4].bits.uop.lrs1_rtype, io.wakeup_ports[4].bits.uop.lrs1_rtype connect issue_slots[0].wakeup_ports[4].bits.uop.dst_rtype, io.wakeup_ports[4].bits.uop.dst_rtype connect issue_slots[0].wakeup_ports[4].bits.uop.lrs3, io.wakeup_ports[4].bits.uop.lrs3 connect issue_slots[0].wakeup_ports[4].bits.uop.lrs2, io.wakeup_ports[4].bits.uop.lrs2 connect issue_slots[0].wakeup_ports[4].bits.uop.lrs1, io.wakeup_ports[4].bits.uop.lrs1 connect issue_slots[0].wakeup_ports[4].bits.uop.ldst, io.wakeup_ports[4].bits.uop.ldst connect issue_slots[0].wakeup_ports[4].bits.uop.ldst_is_rs1, io.wakeup_ports[4].bits.uop.ldst_is_rs1 connect issue_slots[0].wakeup_ports[4].bits.uop.csr_cmd, io.wakeup_ports[4].bits.uop.csr_cmd connect issue_slots[0].wakeup_ports[4].bits.uop.flush_on_commit, io.wakeup_ports[4].bits.uop.flush_on_commit connect issue_slots[0].wakeup_ports[4].bits.uop.is_unique, io.wakeup_ports[4].bits.uop.is_unique connect issue_slots[0].wakeup_ports[4].bits.uop.uses_stq, io.wakeup_ports[4].bits.uop.uses_stq connect issue_slots[0].wakeup_ports[4].bits.uop.uses_ldq, io.wakeup_ports[4].bits.uop.uses_ldq connect issue_slots[0].wakeup_ports[4].bits.uop.mem_signed, io.wakeup_ports[4].bits.uop.mem_signed connect issue_slots[0].wakeup_ports[4].bits.uop.mem_size, io.wakeup_ports[4].bits.uop.mem_size connect issue_slots[0].wakeup_ports[4].bits.uop.mem_cmd, io.wakeup_ports[4].bits.uop.mem_cmd connect issue_slots[0].wakeup_ports[4].bits.uop.exc_cause, io.wakeup_ports[4].bits.uop.exc_cause connect issue_slots[0].wakeup_ports[4].bits.uop.exception, io.wakeup_ports[4].bits.uop.exception connect issue_slots[0].wakeup_ports[4].bits.uop.stale_pdst, io.wakeup_ports[4].bits.uop.stale_pdst connect issue_slots[0].wakeup_ports[4].bits.uop.ppred_busy, io.wakeup_ports[4].bits.uop.ppred_busy connect issue_slots[0].wakeup_ports[4].bits.uop.prs3_busy, io.wakeup_ports[4].bits.uop.prs3_busy connect issue_slots[0].wakeup_ports[4].bits.uop.prs2_busy, io.wakeup_ports[4].bits.uop.prs2_busy connect issue_slots[0].wakeup_ports[4].bits.uop.prs1_busy, io.wakeup_ports[4].bits.uop.prs1_busy connect issue_slots[0].wakeup_ports[4].bits.uop.ppred, io.wakeup_ports[4].bits.uop.ppred connect issue_slots[0].wakeup_ports[4].bits.uop.prs3, io.wakeup_ports[4].bits.uop.prs3 connect issue_slots[0].wakeup_ports[4].bits.uop.prs2, io.wakeup_ports[4].bits.uop.prs2 connect issue_slots[0].wakeup_ports[4].bits.uop.prs1, io.wakeup_ports[4].bits.uop.prs1 connect issue_slots[0].wakeup_ports[4].bits.uop.pdst, io.wakeup_ports[4].bits.uop.pdst connect issue_slots[0].wakeup_ports[4].bits.uop.rxq_idx, io.wakeup_ports[4].bits.uop.rxq_idx connect issue_slots[0].wakeup_ports[4].bits.uop.stq_idx, io.wakeup_ports[4].bits.uop.stq_idx connect issue_slots[0].wakeup_ports[4].bits.uop.ldq_idx, io.wakeup_ports[4].bits.uop.ldq_idx connect issue_slots[0].wakeup_ports[4].bits.uop.rob_idx, io.wakeup_ports[4].bits.uop.rob_idx connect issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.vec, io.wakeup_ports[4].bits.uop.fp_ctrl.vec connect issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.wflags, io.wakeup_ports[4].bits.uop.fp_ctrl.wflags connect issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.div, io.wakeup_ports[4].bits.uop.fp_ctrl.div connect issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.fma, io.wakeup_ports[4].bits.uop.fp_ctrl.fma connect issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.toint, io.wakeup_ports[4].bits.uop.fp_ctrl.toint connect issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.fromint, io.wakeup_ports[4].bits.uop.fp_ctrl.fromint connect issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.swap23, io.wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.swap12, io.wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.ren3, io.wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.ren2, io.wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.ren1, io.wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.wen, io.wakeup_ports[4].bits.uop.fp_ctrl.wen connect issue_slots[0].wakeup_ports[4].bits.uop.fp_ctrl.ldst, io.wakeup_ports[4].bits.uop.fp_ctrl.ldst connect issue_slots[0].wakeup_ports[4].bits.uop.op2_sel, io.wakeup_ports[4].bits.uop.op2_sel connect issue_slots[0].wakeup_ports[4].bits.uop.op1_sel, io.wakeup_ports[4].bits.uop.op1_sel connect issue_slots[0].wakeup_ports[4].bits.uop.imm_packed, io.wakeup_ports[4].bits.uop.imm_packed connect issue_slots[0].wakeup_ports[4].bits.uop.pimm, io.wakeup_ports[4].bits.uop.pimm connect issue_slots[0].wakeup_ports[4].bits.uop.imm_sel, io.wakeup_ports[4].bits.uop.imm_sel connect issue_slots[0].wakeup_ports[4].bits.uop.imm_rename, io.wakeup_ports[4].bits.uop.imm_rename connect issue_slots[0].wakeup_ports[4].bits.uop.taken, io.wakeup_ports[4].bits.uop.taken connect issue_slots[0].wakeup_ports[4].bits.uop.pc_lob, io.wakeup_ports[4].bits.uop.pc_lob connect issue_slots[0].wakeup_ports[4].bits.uop.edge_inst, io.wakeup_ports[4].bits.uop.edge_inst connect issue_slots[0].wakeup_ports[4].bits.uop.ftq_idx, io.wakeup_ports[4].bits.uop.ftq_idx connect issue_slots[0].wakeup_ports[4].bits.uop.is_mov, io.wakeup_ports[4].bits.uop.is_mov connect issue_slots[0].wakeup_ports[4].bits.uop.is_rocc, io.wakeup_ports[4].bits.uop.is_rocc connect issue_slots[0].wakeup_ports[4].bits.uop.is_sys_pc2epc, io.wakeup_ports[4].bits.uop.is_sys_pc2epc connect issue_slots[0].wakeup_ports[4].bits.uop.is_eret, io.wakeup_ports[4].bits.uop.is_eret connect issue_slots[0].wakeup_ports[4].bits.uop.is_amo, io.wakeup_ports[4].bits.uop.is_amo connect issue_slots[0].wakeup_ports[4].bits.uop.is_sfence, io.wakeup_ports[4].bits.uop.is_sfence connect issue_slots[0].wakeup_ports[4].bits.uop.is_fencei, io.wakeup_ports[4].bits.uop.is_fencei connect issue_slots[0].wakeup_ports[4].bits.uop.is_fence, io.wakeup_ports[4].bits.uop.is_fence connect issue_slots[0].wakeup_ports[4].bits.uop.is_sfb, io.wakeup_ports[4].bits.uop.is_sfb connect issue_slots[0].wakeup_ports[4].bits.uop.br_type, io.wakeup_ports[4].bits.uop.br_type connect issue_slots[0].wakeup_ports[4].bits.uop.br_tag, io.wakeup_ports[4].bits.uop.br_tag connect issue_slots[0].wakeup_ports[4].bits.uop.br_mask, io.wakeup_ports[4].bits.uop.br_mask connect issue_slots[0].wakeup_ports[4].bits.uop.dis_col_sel, io.wakeup_ports[4].bits.uop.dis_col_sel connect issue_slots[0].wakeup_ports[4].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect issue_slots[0].wakeup_ports[4].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect issue_slots[0].wakeup_ports[4].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect issue_slots[0].wakeup_ports[4].bits.uop.iw_p2_speculative_child, io.wakeup_ports[4].bits.uop.iw_p2_speculative_child connect issue_slots[0].wakeup_ports[4].bits.uop.iw_p1_speculative_child, io.wakeup_ports[4].bits.uop.iw_p1_speculative_child connect issue_slots[0].wakeup_ports[4].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect issue_slots[0].wakeup_ports[4].bits.uop.iw_issued_partial_agen, io.wakeup_ports[4].bits.uop.iw_issued_partial_agen connect issue_slots[0].wakeup_ports[4].bits.uop.iw_issued, io.wakeup_ports[4].bits.uop.iw_issued connect issue_slots[0].wakeup_ports[4].bits.uop.fu_code[0], io.wakeup_ports[4].bits.uop.fu_code[0] connect issue_slots[0].wakeup_ports[4].bits.uop.fu_code[1], io.wakeup_ports[4].bits.uop.fu_code[1] connect issue_slots[0].wakeup_ports[4].bits.uop.fu_code[2], io.wakeup_ports[4].bits.uop.fu_code[2] connect issue_slots[0].wakeup_ports[4].bits.uop.fu_code[3], io.wakeup_ports[4].bits.uop.fu_code[3] connect issue_slots[0].wakeup_ports[4].bits.uop.fu_code[4], io.wakeup_ports[4].bits.uop.fu_code[4] connect issue_slots[0].wakeup_ports[4].bits.uop.fu_code[5], io.wakeup_ports[4].bits.uop.fu_code[5] connect issue_slots[0].wakeup_ports[4].bits.uop.fu_code[6], io.wakeup_ports[4].bits.uop.fu_code[6] connect issue_slots[0].wakeup_ports[4].bits.uop.fu_code[7], io.wakeup_ports[4].bits.uop.fu_code[7] connect issue_slots[0].wakeup_ports[4].bits.uop.fu_code[8], io.wakeup_ports[4].bits.uop.fu_code[8] connect issue_slots[0].wakeup_ports[4].bits.uop.fu_code[9], io.wakeup_ports[4].bits.uop.fu_code[9] connect issue_slots[0].wakeup_ports[4].bits.uop.iq_type[0], io.wakeup_ports[4].bits.uop.iq_type[0] connect issue_slots[0].wakeup_ports[4].bits.uop.iq_type[1], io.wakeup_ports[4].bits.uop.iq_type[1] connect issue_slots[0].wakeup_ports[4].bits.uop.iq_type[2], io.wakeup_ports[4].bits.uop.iq_type[2] connect issue_slots[0].wakeup_ports[4].bits.uop.iq_type[3], io.wakeup_ports[4].bits.uop.iq_type[3] connect issue_slots[0].wakeup_ports[4].bits.uop.debug_pc, io.wakeup_ports[4].bits.uop.debug_pc connect issue_slots[0].wakeup_ports[4].bits.uop.is_rvc, io.wakeup_ports[4].bits.uop.is_rvc connect issue_slots[0].wakeup_ports[4].bits.uop.debug_inst, io.wakeup_ports[4].bits.uop.debug_inst connect issue_slots[0].wakeup_ports[4].bits.uop.inst, io.wakeup_ports[4].bits.uop.inst connect issue_slots[0].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[0].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[0].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[0].child_rebusys, io.child_rebusys connect issue_slots[0].squash_grant, io.squash_grant connect issue_slots[0].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[0].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[0].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[0].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[0].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[0].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[0].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[0].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[0].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[0].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[0].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[0].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[0].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[0].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect issue_slots[0].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect issue_slots[0].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[0].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect issue_slots[0].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect issue_slots[0].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[0].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[0].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[0].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[0].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[0].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[0].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[0].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[0].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[0].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect issue_slots[0].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[0].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[0].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[0].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[0].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[0].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[0].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[0].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[0].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[0].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[0].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[0].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[0].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[0].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[0].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[0].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[0].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[0].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[0].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[0].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[0].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[0].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[0].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[0].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect issue_slots[0].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect issue_slots[0].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect issue_slots[0].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect issue_slots[0].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect issue_slots[0].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect issue_slots[0].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect issue_slots[0].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect issue_slots[0].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect issue_slots[0].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect issue_slots[0].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect issue_slots[0].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect issue_slots[0].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect issue_slots[0].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect issue_slots[0].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect issue_slots[0].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect issue_slots[0].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect issue_slots[0].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect issue_slots[0].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect issue_slots[0].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[0].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect issue_slots[0].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect issue_slots[0].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect issue_slots[0].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[0].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[0].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[0].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[0].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect issue_slots[0].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect issue_slots[0].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[0].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect issue_slots[0].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[0].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect issue_slots[0].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[0].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[0].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[0].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect issue_slots[0].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[0].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[0].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect issue_slots[0].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect issue_slots[0].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect issue_slots[0].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect issue_slots[0].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect issue_slots[0].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect issue_slots[0].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect issue_slots[0].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect issue_slots[0].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect issue_slots[0].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect issue_slots[0].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect issue_slots[0].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect issue_slots[0].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect issue_slots[0].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect issue_slots[0].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect issue_slots[0].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect issue_slots[0].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect issue_slots[0].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect issue_slots[0].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect issue_slots[0].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect issue_slots[0].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect issue_slots[0].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect issue_slots[0].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect issue_slots[0].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[0].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[0].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[0].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[0].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[0].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[0].kill, io.flush_pipeline connect issue_slots[1].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy connect issue_slots[1].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask connect issue_slots[1].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable connect issue_slots[1].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc connect issue_slots[1].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc connect issue_slots[1].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if connect issue_slots[1].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if connect issue_slots[1].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if connect issue_slots[1].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if connect issue_slots[1].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if connect issue_slots[1].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ connect issue_slots[1].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm connect issue_slots[1].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val connect issue_slots[1].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op connect issue_slots[1].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw connect issue_slots[1].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en connect issue_slots[1].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype connect issue_slots[1].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype connect issue_slots[1].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype connect issue_slots[1].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 connect issue_slots[1].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 connect issue_slots[1].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 connect issue_slots[1].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst connect issue_slots[1].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 connect issue_slots[1].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd connect issue_slots[1].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit connect issue_slots[1].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique connect issue_slots[1].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq connect issue_slots[1].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq connect issue_slots[1].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed connect issue_slots[1].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size connect issue_slots[1].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd connect issue_slots[1].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause connect issue_slots[1].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception connect issue_slots[1].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst connect issue_slots[1].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy connect issue_slots[1].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy connect issue_slots[1].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy connect issue_slots[1].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy connect issue_slots[1].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred connect issue_slots[1].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 connect issue_slots[1].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 connect issue_slots[1].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 connect issue_slots[1].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst connect issue_slots[1].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx connect issue_slots[1].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx connect issue_slots[1].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx connect issue_slots[1].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst connect issue_slots[1].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel connect issue_slots[1].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel connect issue_slots[1].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed connect issue_slots[1].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm connect issue_slots[1].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel connect issue_slots[1].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename connect issue_slots[1].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken connect issue_slots[1].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob connect issue_slots[1].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst connect issue_slots[1].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx connect issue_slots[1].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov connect issue_slots[1].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc connect issue_slots[1].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc connect issue_slots[1].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret connect issue_slots[1].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo connect issue_slots[1].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence connect issue_slots[1].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei connect issue_slots[1].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence connect issue_slots[1].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb connect issue_slots[1].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type connect issue_slots[1].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag connect issue_slots[1].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask connect issue_slots[1].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel connect issue_slots[1].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect issue_slots[1].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect issue_slots[1].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect issue_slots[1].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child connect issue_slots[1].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child connect issue_slots[1].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect issue_slots[1].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen connect issue_slots[1].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued connect issue_slots[1].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] connect issue_slots[1].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] connect issue_slots[1].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] connect issue_slots[1].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] connect issue_slots[1].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] connect issue_slots[1].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] connect issue_slots[1].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] connect issue_slots[1].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] connect issue_slots[1].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] connect issue_slots[1].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] connect issue_slots[1].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] connect issue_slots[1].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] connect issue_slots[1].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] connect issue_slots[1].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] connect issue_slots[1].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc connect issue_slots[1].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc connect issue_slots[1].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst connect issue_slots[1].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst connect issue_slots[1].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[1].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy connect issue_slots[1].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask connect issue_slots[1].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable connect issue_slots[1].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc connect issue_slots[1].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc connect issue_slots[1].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if connect issue_slots[1].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if connect issue_slots[1].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if connect issue_slots[1].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if connect issue_slots[1].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if connect issue_slots[1].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ connect issue_slots[1].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm connect issue_slots[1].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val connect issue_slots[1].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op connect issue_slots[1].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw connect issue_slots[1].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en connect issue_slots[1].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype connect issue_slots[1].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype connect issue_slots[1].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype connect issue_slots[1].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 connect issue_slots[1].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 connect issue_slots[1].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 connect issue_slots[1].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst connect issue_slots[1].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 connect issue_slots[1].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd connect issue_slots[1].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit connect issue_slots[1].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique connect issue_slots[1].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq connect issue_slots[1].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq connect issue_slots[1].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed connect issue_slots[1].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size connect issue_slots[1].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd connect issue_slots[1].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause connect issue_slots[1].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception connect issue_slots[1].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst connect issue_slots[1].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy connect issue_slots[1].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy connect issue_slots[1].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy connect issue_slots[1].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy connect issue_slots[1].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred connect issue_slots[1].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 connect issue_slots[1].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 connect issue_slots[1].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 connect issue_slots[1].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst connect issue_slots[1].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx connect issue_slots[1].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx connect issue_slots[1].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx connect issue_slots[1].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst connect issue_slots[1].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel connect issue_slots[1].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel connect issue_slots[1].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed connect issue_slots[1].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm connect issue_slots[1].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel connect issue_slots[1].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename connect issue_slots[1].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken connect issue_slots[1].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob connect issue_slots[1].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst connect issue_slots[1].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx connect issue_slots[1].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov connect issue_slots[1].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc connect issue_slots[1].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc connect issue_slots[1].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret connect issue_slots[1].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo connect issue_slots[1].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence connect issue_slots[1].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei connect issue_slots[1].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence connect issue_slots[1].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb connect issue_slots[1].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type connect issue_slots[1].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag connect issue_slots[1].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask connect issue_slots[1].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel connect issue_slots[1].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect issue_slots[1].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect issue_slots[1].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect issue_slots[1].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child connect issue_slots[1].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child connect issue_slots[1].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect issue_slots[1].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen connect issue_slots[1].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued connect issue_slots[1].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] connect issue_slots[1].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] connect issue_slots[1].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] connect issue_slots[1].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] connect issue_slots[1].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] connect issue_slots[1].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] connect issue_slots[1].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] connect issue_slots[1].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] connect issue_slots[1].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] connect issue_slots[1].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] connect issue_slots[1].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] connect issue_slots[1].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] connect issue_slots[1].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] connect issue_slots[1].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] connect issue_slots[1].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc connect issue_slots[1].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc connect issue_slots[1].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst connect issue_slots[1].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst connect issue_slots[1].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[1].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy connect issue_slots[1].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask connect issue_slots[1].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable connect issue_slots[1].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc connect issue_slots[1].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc connect issue_slots[1].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if connect issue_slots[1].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if connect issue_slots[1].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if connect issue_slots[1].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if connect issue_slots[1].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if connect issue_slots[1].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ connect issue_slots[1].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm connect issue_slots[1].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val connect issue_slots[1].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op connect issue_slots[1].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw connect issue_slots[1].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en connect issue_slots[1].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype connect issue_slots[1].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype connect issue_slots[1].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype connect issue_slots[1].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3 connect issue_slots[1].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2 connect issue_slots[1].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1 connect issue_slots[1].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst connect issue_slots[1].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1 connect issue_slots[1].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd connect issue_slots[1].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit connect issue_slots[1].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique connect issue_slots[1].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq connect issue_slots[1].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq connect issue_slots[1].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed connect issue_slots[1].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size connect issue_slots[1].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd connect issue_slots[1].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause connect issue_slots[1].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception connect issue_slots[1].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst connect issue_slots[1].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy connect issue_slots[1].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy connect issue_slots[1].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy connect issue_slots[1].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy connect issue_slots[1].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred connect issue_slots[1].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3 connect issue_slots[1].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2 connect issue_slots[1].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1 connect issue_slots[1].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst connect issue_slots[1].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx connect issue_slots[1].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx connect issue_slots[1].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx connect issue_slots[1].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen connect issue_slots[1].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst connect issue_slots[1].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel connect issue_slots[1].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel connect issue_slots[1].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed connect issue_slots[1].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm connect issue_slots[1].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel connect issue_slots[1].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename connect issue_slots[1].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken connect issue_slots[1].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob connect issue_slots[1].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst connect issue_slots[1].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx connect issue_slots[1].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov connect issue_slots[1].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc connect issue_slots[1].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc connect issue_slots[1].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret connect issue_slots[1].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo connect issue_slots[1].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence connect issue_slots[1].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei connect issue_slots[1].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence connect issue_slots[1].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb connect issue_slots[1].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type connect issue_slots[1].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag connect issue_slots[1].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask connect issue_slots[1].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel connect issue_slots[1].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect issue_slots[1].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect issue_slots[1].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect issue_slots[1].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child connect issue_slots[1].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child connect issue_slots[1].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect issue_slots[1].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen connect issue_slots[1].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued connect issue_slots[1].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0] connect issue_slots[1].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1] connect issue_slots[1].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2] connect issue_slots[1].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3] connect issue_slots[1].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4] connect issue_slots[1].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5] connect issue_slots[1].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6] connect issue_slots[1].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7] connect issue_slots[1].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8] connect issue_slots[1].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9] connect issue_slots[1].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0] connect issue_slots[1].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1] connect issue_slots[1].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2] connect issue_slots[1].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3] connect issue_slots[1].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc connect issue_slots[1].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc connect issue_slots[1].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst connect issue_slots[1].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst connect issue_slots[1].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[1].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy connect issue_slots[1].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask connect issue_slots[1].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable connect issue_slots[1].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc connect issue_slots[1].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc connect issue_slots[1].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if connect issue_slots[1].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if connect issue_slots[1].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if connect issue_slots[1].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if connect issue_slots[1].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if connect issue_slots[1].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ connect issue_slots[1].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm connect issue_slots[1].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val connect issue_slots[1].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op connect issue_slots[1].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw connect issue_slots[1].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en connect issue_slots[1].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype connect issue_slots[1].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype connect issue_slots[1].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype connect issue_slots[1].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3 connect issue_slots[1].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2 connect issue_slots[1].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1 connect issue_slots[1].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst connect issue_slots[1].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1 connect issue_slots[1].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd connect issue_slots[1].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit connect issue_slots[1].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique connect issue_slots[1].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq connect issue_slots[1].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq connect issue_slots[1].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed connect issue_slots[1].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size connect issue_slots[1].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd connect issue_slots[1].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause connect issue_slots[1].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception connect issue_slots[1].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst connect issue_slots[1].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy connect issue_slots[1].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy connect issue_slots[1].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy connect issue_slots[1].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy connect issue_slots[1].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred connect issue_slots[1].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3 connect issue_slots[1].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2 connect issue_slots[1].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1 connect issue_slots[1].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst connect issue_slots[1].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx connect issue_slots[1].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx connect issue_slots[1].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx connect issue_slots[1].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen connect issue_slots[1].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst connect issue_slots[1].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel connect issue_slots[1].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel connect issue_slots[1].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed connect issue_slots[1].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm connect issue_slots[1].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel connect issue_slots[1].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename connect issue_slots[1].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken connect issue_slots[1].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob connect issue_slots[1].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst connect issue_slots[1].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx connect issue_slots[1].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov connect issue_slots[1].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc connect issue_slots[1].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc connect issue_slots[1].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret connect issue_slots[1].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo connect issue_slots[1].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence connect issue_slots[1].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei connect issue_slots[1].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence connect issue_slots[1].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb connect issue_slots[1].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type connect issue_slots[1].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag connect issue_slots[1].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask connect issue_slots[1].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel connect issue_slots[1].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect issue_slots[1].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect issue_slots[1].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect issue_slots[1].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child connect issue_slots[1].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child connect issue_slots[1].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect issue_slots[1].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen connect issue_slots[1].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued connect issue_slots[1].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0] connect issue_slots[1].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1] connect issue_slots[1].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2] connect issue_slots[1].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3] connect issue_slots[1].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4] connect issue_slots[1].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5] connect issue_slots[1].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6] connect issue_slots[1].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7] connect issue_slots[1].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8] connect issue_slots[1].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9] connect issue_slots[1].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0] connect issue_slots[1].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1] connect issue_slots[1].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2] connect issue_slots[1].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3] connect issue_slots[1].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc connect issue_slots[1].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc connect issue_slots[1].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst connect issue_slots[1].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst connect issue_slots[1].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[1].wakeup_ports[4].bits.rebusy, io.wakeup_ports[4].bits.rebusy connect issue_slots[1].wakeup_ports[4].bits.speculative_mask, io.wakeup_ports[4].bits.speculative_mask connect issue_slots[1].wakeup_ports[4].bits.bypassable, io.wakeup_ports[4].bits.bypassable connect issue_slots[1].wakeup_ports[4].bits.uop.debug_tsrc, io.wakeup_ports[4].bits.uop.debug_tsrc connect issue_slots[1].wakeup_ports[4].bits.uop.debug_fsrc, io.wakeup_ports[4].bits.uop.debug_fsrc connect issue_slots[1].wakeup_ports[4].bits.uop.bp_xcpt_if, io.wakeup_ports[4].bits.uop.bp_xcpt_if connect issue_slots[1].wakeup_ports[4].bits.uop.bp_debug_if, io.wakeup_ports[4].bits.uop.bp_debug_if connect issue_slots[1].wakeup_ports[4].bits.uop.xcpt_ma_if, io.wakeup_ports[4].bits.uop.xcpt_ma_if connect issue_slots[1].wakeup_ports[4].bits.uop.xcpt_ae_if, io.wakeup_ports[4].bits.uop.xcpt_ae_if connect issue_slots[1].wakeup_ports[4].bits.uop.xcpt_pf_if, io.wakeup_ports[4].bits.uop.xcpt_pf_if connect issue_slots[1].wakeup_ports[4].bits.uop.fp_typ, io.wakeup_ports[4].bits.uop.fp_typ connect issue_slots[1].wakeup_ports[4].bits.uop.fp_rm, io.wakeup_ports[4].bits.uop.fp_rm connect issue_slots[1].wakeup_ports[4].bits.uop.fp_val, io.wakeup_ports[4].bits.uop.fp_val connect issue_slots[1].wakeup_ports[4].bits.uop.fcn_op, io.wakeup_ports[4].bits.uop.fcn_op connect issue_slots[1].wakeup_ports[4].bits.uop.fcn_dw, io.wakeup_ports[4].bits.uop.fcn_dw connect issue_slots[1].wakeup_ports[4].bits.uop.frs3_en, io.wakeup_ports[4].bits.uop.frs3_en connect issue_slots[1].wakeup_ports[4].bits.uop.lrs2_rtype, io.wakeup_ports[4].bits.uop.lrs2_rtype connect issue_slots[1].wakeup_ports[4].bits.uop.lrs1_rtype, io.wakeup_ports[4].bits.uop.lrs1_rtype connect issue_slots[1].wakeup_ports[4].bits.uop.dst_rtype, io.wakeup_ports[4].bits.uop.dst_rtype connect issue_slots[1].wakeup_ports[4].bits.uop.lrs3, io.wakeup_ports[4].bits.uop.lrs3 connect issue_slots[1].wakeup_ports[4].bits.uop.lrs2, io.wakeup_ports[4].bits.uop.lrs2 connect issue_slots[1].wakeup_ports[4].bits.uop.lrs1, io.wakeup_ports[4].bits.uop.lrs1 connect issue_slots[1].wakeup_ports[4].bits.uop.ldst, io.wakeup_ports[4].bits.uop.ldst connect issue_slots[1].wakeup_ports[4].bits.uop.ldst_is_rs1, io.wakeup_ports[4].bits.uop.ldst_is_rs1 connect issue_slots[1].wakeup_ports[4].bits.uop.csr_cmd, io.wakeup_ports[4].bits.uop.csr_cmd connect issue_slots[1].wakeup_ports[4].bits.uop.flush_on_commit, io.wakeup_ports[4].bits.uop.flush_on_commit connect issue_slots[1].wakeup_ports[4].bits.uop.is_unique, io.wakeup_ports[4].bits.uop.is_unique connect issue_slots[1].wakeup_ports[4].bits.uop.uses_stq, io.wakeup_ports[4].bits.uop.uses_stq connect issue_slots[1].wakeup_ports[4].bits.uop.uses_ldq, io.wakeup_ports[4].bits.uop.uses_ldq connect issue_slots[1].wakeup_ports[4].bits.uop.mem_signed, io.wakeup_ports[4].bits.uop.mem_signed connect issue_slots[1].wakeup_ports[4].bits.uop.mem_size, io.wakeup_ports[4].bits.uop.mem_size connect issue_slots[1].wakeup_ports[4].bits.uop.mem_cmd, io.wakeup_ports[4].bits.uop.mem_cmd connect issue_slots[1].wakeup_ports[4].bits.uop.exc_cause, io.wakeup_ports[4].bits.uop.exc_cause connect issue_slots[1].wakeup_ports[4].bits.uop.exception, io.wakeup_ports[4].bits.uop.exception connect issue_slots[1].wakeup_ports[4].bits.uop.stale_pdst, io.wakeup_ports[4].bits.uop.stale_pdst connect issue_slots[1].wakeup_ports[4].bits.uop.ppred_busy, io.wakeup_ports[4].bits.uop.ppred_busy connect issue_slots[1].wakeup_ports[4].bits.uop.prs3_busy, io.wakeup_ports[4].bits.uop.prs3_busy connect issue_slots[1].wakeup_ports[4].bits.uop.prs2_busy, io.wakeup_ports[4].bits.uop.prs2_busy connect issue_slots[1].wakeup_ports[4].bits.uop.prs1_busy, io.wakeup_ports[4].bits.uop.prs1_busy connect issue_slots[1].wakeup_ports[4].bits.uop.ppred, io.wakeup_ports[4].bits.uop.ppred connect issue_slots[1].wakeup_ports[4].bits.uop.prs3, io.wakeup_ports[4].bits.uop.prs3 connect issue_slots[1].wakeup_ports[4].bits.uop.prs2, io.wakeup_ports[4].bits.uop.prs2 connect issue_slots[1].wakeup_ports[4].bits.uop.prs1, io.wakeup_ports[4].bits.uop.prs1 connect issue_slots[1].wakeup_ports[4].bits.uop.pdst, io.wakeup_ports[4].bits.uop.pdst connect issue_slots[1].wakeup_ports[4].bits.uop.rxq_idx, io.wakeup_ports[4].bits.uop.rxq_idx connect issue_slots[1].wakeup_ports[4].bits.uop.stq_idx, io.wakeup_ports[4].bits.uop.stq_idx connect issue_slots[1].wakeup_ports[4].bits.uop.ldq_idx, io.wakeup_ports[4].bits.uop.ldq_idx connect issue_slots[1].wakeup_ports[4].bits.uop.rob_idx, io.wakeup_ports[4].bits.uop.rob_idx connect issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.vec, io.wakeup_ports[4].bits.uop.fp_ctrl.vec connect issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.wflags, io.wakeup_ports[4].bits.uop.fp_ctrl.wflags connect issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.div, io.wakeup_ports[4].bits.uop.fp_ctrl.div connect issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.fma, io.wakeup_ports[4].bits.uop.fp_ctrl.fma connect issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.toint, io.wakeup_ports[4].bits.uop.fp_ctrl.toint connect issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.fromint, io.wakeup_ports[4].bits.uop.fp_ctrl.fromint connect issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.swap23, io.wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.swap12, io.wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.ren3, io.wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.ren2, io.wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.ren1, io.wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.wen, io.wakeup_ports[4].bits.uop.fp_ctrl.wen connect issue_slots[1].wakeup_ports[4].bits.uop.fp_ctrl.ldst, io.wakeup_ports[4].bits.uop.fp_ctrl.ldst connect issue_slots[1].wakeup_ports[4].bits.uop.op2_sel, io.wakeup_ports[4].bits.uop.op2_sel connect issue_slots[1].wakeup_ports[4].bits.uop.op1_sel, io.wakeup_ports[4].bits.uop.op1_sel connect issue_slots[1].wakeup_ports[4].bits.uop.imm_packed, io.wakeup_ports[4].bits.uop.imm_packed connect issue_slots[1].wakeup_ports[4].bits.uop.pimm, io.wakeup_ports[4].bits.uop.pimm connect issue_slots[1].wakeup_ports[4].bits.uop.imm_sel, io.wakeup_ports[4].bits.uop.imm_sel connect issue_slots[1].wakeup_ports[4].bits.uop.imm_rename, io.wakeup_ports[4].bits.uop.imm_rename connect issue_slots[1].wakeup_ports[4].bits.uop.taken, io.wakeup_ports[4].bits.uop.taken connect issue_slots[1].wakeup_ports[4].bits.uop.pc_lob, io.wakeup_ports[4].bits.uop.pc_lob connect issue_slots[1].wakeup_ports[4].bits.uop.edge_inst, io.wakeup_ports[4].bits.uop.edge_inst connect issue_slots[1].wakeup_ports[4].bits.uop.ftq_idx, io.wakeup_ports[4].bits.uop.ftq_idx connect issue_slots[1].wakeup_ports[4].bits.uop.is_mov, io.wakeup_ports[4].bits.uop.is_mov connect issue_slots[1].wakeup_ports[4].bits.uop.is_rocc, io.wakeup_ports[4].bits.uop.is_rocc connect issue_slots[1].wakeup_ports[4].bits.uop.is_sys_pc2epc, io.wakeup_ports[4].bits.uop.is_sys_pc2epc connect issue_slots[1].wakeup_ports[4].bits.uop.is_eret, io.wakeup_ports[4].bits.uop.is_eret connect issue_slots[1].wakeup_ports[4].bits.uop.is_amo, io.wakeup_ports[4].bits.uop.is_amo connect issue_slots[1].wakeup_ports[4].bits.uop.is_sfence, io.wakeup_ports[4].bits.uop.is_sfence connect issue_slots[1].wakeup_ports[4].bits.uop.is_fencei, io.wakeup_ports[4].bits.uop.is_fencei connect issue_slots[1].wakeup_ports[4].bits.uop.is_fence, io.wakeup_ports[4].bits.uop.is_fence connect issue_slots[1].wakeup_ports[4].bits.uop.is_sfb, io.wakeup_ports[4].bits.uop.is_sfb connect issue_slots[1].wakeup_ports[4].bits.uop.br_type, io.wakeup_ports[4].bits.uop.br_type connect issue_slots[1].wakeup_ports[4].bits.uop.br_tag, io.wakeup_ports[4].bits.uop.br_tag connect issue_slots[1].wakeup_ports[4].bits.uop.br_mask, io.wakeup_ports[4].bits.uop.br_mask connect issue_slots[1].wakeup_ports[4].bits.uop.dis_col_sel, io.wakeup_ports[4].bits.uop.dis_col_sel connect issue_slots[1].wakeup_ports[4].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect issue_slots[1].wakeup_ports[4].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect issue_slots[1].wakeup_ports[4].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect issue_slots[1].wakeup_ports[4].bits.uop.iw_p2_speculative_child, io.wakeup_ports[4].bits.uop.iw_p2_speculative_child connect issue_slots[1].wakeup_ports[4].bits.uop.iw_p1_speculative_child, io.wakeup_ports[4].bits.uop.iw_p1_speculative_child connect issue_slots[1].wakeup_ports[4].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect issue_slots[1].wakeup_ports[4].bits.uop.iw_issued_partial_agen, io.wakeup_ports[4].bits.uop.iw_issued_partial_agen connect issue_slots[1].wakeup_ports[4].bits.uop.iw_issued, io.wakeup_ports[4].bits.uop.iw_issued connect issue_slots[1].wakeup_ports[4].bits.uop.fu_code[0], io.wakeup_ports[4].bits.uop.fu_code[0] connect issue_slots[1].wakeup_ports[4].bits.uop.fu_code[1], io.wakeup_ports[4].bits.uop.fu_code[1] connect issue_slots[1].wakeup_ports[4].bits.uop.fu_code[2], io.wakeup_ports[4].bits.uop.fu_code[2] connect issue_slots[1].wakeup_ports[4].bits.uop.fu_code[3], io.wakeup_ports[4].bits.uop.fu_code[3] connect issue_slots[1].wakeup_ports[4].bits.uop.fu_code[4], io.wakeup_ports[4].bits.uop.fu_code[4] connect issue_slots[1].wakeup_ports[4].bits.uop.fu_code[5], io.wakeup_ports[4].bits.uop.fu_code[5] connect issue_slots[1].wakeup_ports[4].bits.uop.fu_code[6], io.wakeup_ports[4].bits.uop.fu_code[6] connect issue_slots[1].wakeup_ports[4].bits.uop.fu_code[7], io.wakeup_ports[4].bits.uop.fu_code[7] connect issue_slots[1].wakeup_ports[4].bits.uop.fu_code[8], io.wakeup_ports[4].bits.uop.fu_code[8] connect issue_slots[1].wakeup_ports[4].bits.uop.fu_code[9], io.wakeup_ports[4].bits.uop.fu_code[9] connect issue_slots[1].wakeup_ports[4].bits.uop.iq_type[0], io.wakeup_ports[4].bits.uop.iq_type[0] connect issue_slots[1].wakeup_ports[4].bits.uop.iq_type[1], io.wakeup_ports[4].bits.uop.iq_type[1] connect issue_slots[1].wakeup_ports[4].bits.uop.iq_type[2], io.wakeup_ports[4].bits.uop.iq_type[2] connect issue_slots[1].wakeup_ports[4].bits.uop.iq_type[3], io.wakeup_ports[4].bits.uop.iq_type[3] connect issue_slots[1].wakeup_ports[4].bits.uop.debug_pc, io.wakeup_ports[4].bits.uop.debug_pc connect issue_slots[1].wakeup_ports[4].bits.uop.is_rvc, io.wakeup_ports[4].bits.uop.is_rvc connect issue_slots[1].wakeup_ports[4].bits.uop.debug_inst, io.wakeup_ports[4].bits.uop.debug_inst connect issue_slots[1].wakeup_ports[4].bits.uop.inst, io.wakeup_ports[4].bits.uop.inst connect issue_slots[1].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[1].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[1].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[1].child_rebusys, io.child_rebusys connect issue_slots[1].squash_grant, io.squash_grant connect issue_slots[1].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[1].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[1].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[1].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[1].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[1].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[1].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[1].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[1].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[1].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[1].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[1].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[1].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[1].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect issue_slots[1].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect issue_slots[1].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[1].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect issue_slots[1].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect issue_slots[1].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[1].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[1].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[1].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[1].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[1].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[1].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[1].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[1].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[1].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect issue_slots[1].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[1].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[1].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[1].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[1].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[1].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[1].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[1].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[1].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[1].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[1].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[1].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[1].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[1].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[1].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[1].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[1].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[1].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[1].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[1].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[1].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[1].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[1].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[1].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect issue_slots[1].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect issue_slots[1].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect issue_slots[1].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect issue_slots[1].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect issue_slots[1].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect issue_slots[1].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect issue_slots[1].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect issue_slots[1].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect issue_slots[1].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect issue_slots[1].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect issue_slots[1].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect issue_slots[1].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect issue_slots[1].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect issue_slots[1].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect issue_slots[1].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect issue_slots[1].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect issue_slots[1].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect issue_slots[1].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect issue_slots[1].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[1].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect issue_slots[1].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect issue_slots[1].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect issue_slots[1].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[1].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[1].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[1].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[1].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect issue_slots[1].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect issue_slots[1].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[1].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect issue_slots[1].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[1].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect issue_slots[1].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[1].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[1].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[1].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect issue_slots[1].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[1].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[1].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect issue_slots[1].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect issue_slots[1].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect issue_slots[1].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect issue_slots[1].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect issue_slots[1].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect issue_slots[1].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect issue_slots[1].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect issue_slots[1].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect issue_slots[1].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect issue_slots[1].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect issue_slots[1].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect issue_slots[1].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect issue_slots[1].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect issue_slots[1].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect issue_slots[1].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect issue_slots[1].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect issue_slots[1].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect issue_slots[1].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect issue_slots[1].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect issue_slots[1].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect issue_slots[1].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect issue_slots[1].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect issue_slots[1].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[1].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[1].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[1].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[1].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[1].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[1].kill, io.flush_pipeline connect issue_slots[2].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy connect issue_slots[2].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask connect issue_slots[2].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable connect issue_slots[2].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc connect issue_slots[2].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc connect issue_slots[2].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if connect issue_slots[2].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if connect issue_slots[2].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if connect issue_slots[2].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if connect issue_slots[2].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if connect issue_slots[2].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ connect issue_slots[2].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm connect issue_slots[2].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val connect issue_slots[2].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op connect issue_slots[2].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw connect issue_slots[2].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en connect issue_slots[2].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype connect issue_slots[2].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype connect issue_slots[2].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype connect issue_slots[2].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 connect issue_slots[2].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 connect issue_slots[2].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 connect issue_slots[2].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst connect issue_slots[2].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 connect issue_slots[2].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd connect issue_slots[2].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit connect issue_slots[2].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique connect issue_slots[2].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq connect issue_slots[2].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq connect issue_slots[2].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed connect issue_slots[2].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size connect issue_slots[2].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd connect issue_slots[2].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause connect issue_slots[2].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception connect issue_slots[2].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst connect issue_slots[2].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy connect issue_slots[2].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy connect issue_slots[2].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy connect issue_slots[2].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy connect issue_slots[2].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred connect issue_slots[2].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 connect issue_slots[2].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 connect issue_slots[2].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 connect issue_slots[2].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst connect issue_slots[2].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx connect issue_slots[2].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx connect issue_slots[2].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx connect issue_slots[2].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst connect issue_slots[2].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel connect issue_slots[2].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel connect issue_slots[2].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed connect issue_slots[2].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm connect issue_slots[2].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel connect issue_slots[2].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename connect issue_slots[2].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken connect issue_slots[2].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob connect issue_slots[2].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst connect issue_slots[2].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx connect issue_slots[2].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov connect issue_slots[2].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc connect issue_slots[2].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc connect issue_slots[2].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret connect issue_slots[2].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo connect issue_slots[2].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence connect issue_slots[2].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei connect issue_slots[2].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence connect issue_slots[2].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb connect issue_slots[2].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type connect issue_slots[2].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag connect issue_slots[2].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask connect issue_slots[2].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel connect issue_slots[2].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect issue_slots[2].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect issue_slots[2].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect issue_slots[2].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child connect issue_slots[2].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child connect issue_slots[2].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect issue_slots[2].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen connect issue_slots[2].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued connect issue_slots[2].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] connect issue_slots[2].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] connect issue_slots[2].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] connect issue_slots[2].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] connect issue_slots[2].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] connect issue_slots[2].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] connect issue_slots[2].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] connect issue_slots[2].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] connect issue_slots[2].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] connect issue_slots[2].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] connect issue_slots[2].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] connect issue_slots[2].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] connect issue_slots[2].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] connect issue_slots[2].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] connect issue_slots[2].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc connect issue_slots[2].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc connect issue_slots[2].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst connect issue_slots[2].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst connect issue_slots[2].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[2].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy connect issue_slots[2].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask connect issue_slots[2].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable connect issue_slots[2].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc connect issue_slots[2].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc connect issue_slots[2].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if connect issue_slots[2].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if connect issue_slots[2].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if connect issue_slots[2].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if connect issue_slots[2].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if connect issue_slots[2].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ connect issue_slots[2].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm connect issue_slots[2].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val connect issue_slots[2].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op connect issue_slots[2].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw connect issue_slots[2].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en connect issue_slots[2].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype connect issue_slots[2].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype connect issue_slots[2].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype connect issue_slots[2].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 connect issue_slots[2].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 connect issue_slots[2].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 connect issue_slots[2].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst connect issue_slots[2].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 connect issue_slots[2].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd connect issue_slots[2].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit connect issue_slots[2].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique connect issue_slots[2].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq connect issue_slots[2].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq connect issue_slots[2].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed connect issue_slots[2].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size connect issue_slots[2].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd connect issue_slots[2].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause connect issue_slots[2].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception connect issue_slots[2].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst connect issue_slots[2].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy connect issue_slots[2].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy connect issue_slots[2].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy connect issue_slots[2].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy connect issue_slots[2].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred connect issue_slots[2].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 connect issue_slots[2].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 connect issue_slots[2].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 connect issue_slots[2].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst connect issue_slots[2].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx connect issue_slots[2].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx connect issue_slots[2].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx connect issue_slots[2].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst connect issue_slots[2].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel connect issue_slots[2].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel connect issue_slots[2].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed connect issue_slots[2].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm connect issue_slots[2].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel connect issue_slots[2].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename connect issue_slots[2].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken connect issue_slots[2].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob connect issue_slots[2].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst connect issue_slots[2].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx connect issue_slots[2].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov connect issue_slots[2].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc connect issue_slots[2].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc connect issue_slots[2].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret connect issue_slots[2].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo connect issue_slots[2].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence connect issue_slots[2].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei connect issue_slots[2].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence connect issue_slots[2].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb connect issue_slots[2].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type connect issue_slots[2].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag connect issue_slots[2].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask connect issue_slots[2].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel connect issue_slots[2].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect issue_slots[2].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect issue_slots[2].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect issue_slots[2].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child connect issue_slots[2].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child connect issue_slots[2].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect issue_slots[2].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen connect issue_slots[2].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued connect issue_slots[2].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] connect issue_slots[2].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] connect issue_slots[2].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] connect issue_slots[2].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] connect issue_slots[2].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] connect issue_slots[2].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] connect issue_slots[2].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] connect issue_slots[2].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] connect issue_slots[2].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] connect issue_slots[2].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] connect issue_slots[2].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] connect issue_slots[2].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] connect issue_slots[2].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] connect issue_slots[2].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] connect issue_slots[2].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc connect issue_slots[2].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc connect issue_slots[2].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst connect issue_slots[2].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst connect issue_slots[2].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[2].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy connect issue_slots[2].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask connect issue_slots[2].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable connect issue_slots[2].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc connect issue_slots[2].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc connect issue_slots[2].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if connect issue_slots[2].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if connect issue_slots[2].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if connect issue_slots[2].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if connect issue_slots[2].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if connect issue_slots[2].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ connect issue_slots[2].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm connect issue_slots[2].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val connect issue_slots[2].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op connect issue_slots[2].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw connect issue_slots[2].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en connect issue_slots[2].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype connect issue_slots[2].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype connect issue_slots[2].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype connect issue_slots[2].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3 connect issue_slots[2].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2 connect issue_slots[2].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1 connect issue_slots[2].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst connect issue_slots[2].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1 connect issue_slots[2].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd connect issue_slots[2].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit connect issue_slots[2].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique connect issue_slots[2].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq connect issue_slots[2].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq connect issue_slots[2].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed connect issue_slots[2].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size connect issue_slots[2].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd connect issue_slots[2].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause connect issue_slots[2].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception connect issue_slots[2].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst connect issue_slots[2].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy connect issue_slots[2].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy connect issue_slots[2].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy connect issue_slots[2].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy connect issue_slots[2].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred connect issue_slots[2].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3 connect issue_slots[2].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2 connect issue_slots[2].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1 connect issue_slots[2].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst connect issue_slots[2].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx connect issue_slots[2].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx connect issue_slots[2].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx connect issue_slots[2].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen connect issue_slots[2].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst connect issue_slots[2].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel connect issue_slots[2].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel connect issue_slots[2].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed connect issue_slots[2].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm connect issue_slots[2].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel connect issue_slots[2].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename connect issue_slots[2].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken connect issue_slots[2].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob connect issue_slots[2].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst connect issue_slots[2].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx connect issue_slots[2].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov connect issue_slots[2].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc connect issue_slots[2].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc connect issue_slots[2].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret connect issue_slots[2].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo connect issue_slots[2].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence connect issue_slots[2].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei connect issue_slots[2].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence connect issue_slots[2].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb connect issue_slots[2].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type connect issue_slots[2].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag connect issue_slots[2].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask connect issue_slots[2].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel connect issue_slots[2].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect issue_slots[2].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect issue_slots[2].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect issue_slots[2].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child connect issue_slots[2].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child connect issue_slots[2].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect issue_slots[2].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen connect issue_slots[2].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued connect issue_slots[2].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0] connect issue_slots[2].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1] connect issue_slots[2].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2] connect issue_slots[2].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3] connect issue_slots[2].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4] connect issue_slots[2].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5] connect issue_slots[2].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6] connect issue_slots[2].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7] connect issue_slots[2].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8] connect issue_slots[2].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9] connect issue_slots[2].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0] connect issue_slots[2].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1] connect issue_slots[2].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2] connect issue_slots[2].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3] connect issue_slots[2].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc connect issue_slots[2].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc connect issue_slots[2].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst connect issue_slots[2].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst connect issue_slots[2].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[2].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy connect issue_slots[2].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask connect issue_slots[2].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable connect issue_slots[2].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc connect issue_slots[2].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc connect issue_slots[2].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if connect issue_slots[2].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if connect issue_slots[2].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if connect issue_slots[2].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if connect issue_slots[2].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if connect issue_slots[2].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ connect issue_slots[2].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm connect issue_slots[2].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val connect issue_slots[2].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op connect issue_slots[2].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw connect issue_slots[2].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en connect issue_slots[2].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype connect issue_slots[2].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype connect issue_slots[2].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype connect issue_slots[2].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3 connect issue_slots[2].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2 connect issue_slots[2].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1 connect issue_slots[2].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst connect issue_slots[2].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1 connect issue_slots[2].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd connect issue_slots[2].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit connect issue_slots[2].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique connect issue_slots[2].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq connect issue_slots[2].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq connect issue_slots[2].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed connect issue_slots[2].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size connect issue_slots[2].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd connect issue_slots[2].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause connect issue_slots[2].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception connect issue_slots[2].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst connect issue_slots[2].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy connect issue_slots[2].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy connect issue_slots[2].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy connect issue_slots[2].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy connect issue_slots[2].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred connect issue_slots[2].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3 connect issue_slots[2].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2 connect issue_slots[2].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1 connect issue_slots[2].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst connect issue_slots[2].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx connect issue_slots[2].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx connect issue_slots[2].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx connect issue_slots[2].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen connect issue_slots[2].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst connect issue_slots[2].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel connect issue_slots[2].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel connect issue_slots[2].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed connect issue_slots[2].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm connect issue_slots[2].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel connect issue_slots[2].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename connect issue_slots[2].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken connect issue_slots[2].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob connect issue_slots[2].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst connect issue_slots[2].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx connect issue_slots[2].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov connect issue_slots[2].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc connect issue_slots[2].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc connect issue_slots[2].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret connect issue_slots[2].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo connect issue_slots[2].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence connect issue_slots[2].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei connect issue_slots[2].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence connect issue_slots[2].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb connect issue_slots[2].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type connect issue_slots[2].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag connect issue_slots[2].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask connect issue_slots[2].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel connect issue_slots[2].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect issue_slots[2].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect issue_slots[2].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect issue_slots[2].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child connect issue_slots[2].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child connect issue_slots[2].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect issue_slots[2].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen connect issue_slots[2].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued connect issue_slots[2].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0] connect issue_slots[2].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1] connect issue_slots[2].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2] connect issue_slots[2].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3] connect issue_slots[2].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4] connect issue_slots[2].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5] connect issue_slots[2].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6] connect issue_slots[2].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7] connect issue_slots[2].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8] connect issue_slots[2].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9] connect issue_slots[2].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0] connect issue_slots[2].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1] connect issue_slots[2].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2] connect issue_slots[2].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3] connect issue_slots[2].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc connect issue_slots[2].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc connect issue_slots[2].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst connect issue_slots[2].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst connect issue_slots[2].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[2].wakeup_ports[4].bits.rebusy, io.wakeup_ports[4].bits.rebusy connect issue_slots[2].wakeup_ports[4].bits.speculative_mask, io.wakeup_ports[4].bits.speculative_mask connect issue_slots[2].wakeup_ports[4].bits.bypassable, io.wakeup_ports[4].bits.bypassable connect issue_slots[2].wakeup_ports[4].bits.uop.debug_tsrc, io.wakeup_ports[4].bits.uop.debug_tsrc connect issue_slots[2].wakeup_ports[4].bits.uop.debug_fsrc, io.wakeup_ports[4].bits.uop.debug_fsrc connect issue_slots[2].wakeup_ports[4].bits.uop.bp_xcpt_if, io.wakeup_ports[4].bits.uop.bp_xcpt_if connect issue_slots[2].wakeup_ports[4].bits.uop.bp_debug_if, io.wakeup_ports[4].bits.uop.bp_debug_if connect issue_slots[2].wakeup_ports[4].bits.uop.xcpt_ma_if, io.wakeup_ports[4].bits.uop.xcpt_ma_if connect issue_slots[2].wakeup_ports[4].bits.uop.xcpt_ae_if, io.wakeup_ports[4].bits.uop.xcpt_ae_if connect issue_slots[2].wakeup_ports[4].bits.uop.xcpt_pf_if, io.wakeup_ports[4].bits.uop.xcpt_pf_if connect issue_slots[2].wakeup_ports[4].bits.uop.fp_typ, io.wakeup_ports[4].bits.uop.fp_typ connect issue_slots[2].wakeup_ports[4].bits.uop.fp_rm, io.wakeup_ports[4].bits.uop.fp_rm connect issue_slots[2].wakeup_ports[4].bits.uop.fp_val, io.wakeup_ports[4].bits.uop.fp_val connect issue_slots[2].wakeup_ports[4].bits.uop.fcn_op, io.wakeup_ports[4].bits.uop.fcn_op connect issue_slots[2].wakeup_ports[4].bits.uop.fcn_dw, io.wakeup_ports[4].bits.uop.fcn_dw connect issue_slots[2].wakeup_ports[4].bits.uop.frs3_en, io.wakeup_ports[4].bits.uop.frs3_en connect issue_slots[2].wakeup_ports[4].bits.uop.lrs2_rtype, io.wakeup_ports[4].bits.uop.lrs2_rtype connect issue_slots[2].wakeup_ports[4].bits.uop.lrs1_rtype, io.wakeup_ports[4].bits.uop.lrs1_rtype connect issue_slots[2].wakeup_ports[4].bits.uop.dst_rtype, io.wakeup_ports[4].bits.uop.dst_rtype connect issue_slots[2].wakeup_ports[4].bits.uop.lrs3, io.wakeup_ports[4].bits.uop.lrs3 connect issue_slots[2].wakeup_ports[4].bits.uop.lrs2, io.wakeup_ports[4].bits.uop.lrs2 connect issue_slots[2].wakeup_ports[4].bits.uop.lrs1, io.wakeup_ports[4].bits.uop.lrs1 connect issue_slots[2].wakeup_ports[4].bits.uop.ldst, io.wakeup_ports[4].bits.uop.ldst connect issue_slots[2].wakeup_ports[4].bits.uop.ldst_is_rs1, io.wakeup_ports[4].bits.uop.ldst_is_rs1 connect issue_slots[2].wakeup_ports[4].bits.uop.csr_cmd, io.wakeup_ports[4].bits.uop.csr_cmd connect issue_slots[2].wakeup_ports[4].bits.uop.flush_on_commit, io.wakeup_ports[4].bits.uop.flush_on_commit connect issue_slots[2].wakeup_ports[4].bits.uop.is_unique, io.wakeup_ports[4].bits.uop.is_unique connect issue_slots[2].wakeup_ports[4].bits.uop.uses_stq, io.wakeup_ports[4].bits.uop.uses_stq connect issue_slots[2].wakeup_ports[4].bits.uop.uses_ldq, io.wakeup_ports[4].bits.uop.uses_ldq connect issue_slots[2].wakeup_ports[4].bits.uop.mem_signed, io.wakeup_ports[4].bits.uop.mem_signed connect issue_slots[2].wakeup_ports[4].bits.uop.mem_size, io.wakeup_ports[4].bits.uop.mem_size connect issue_slots[2].wakeup_ports[4].bits.uop.mem_cmd, io.wakeup_ports[4].bits.uop.mem_cmd connect issue_slots[2].wakeup_ports[4].bits.uop.exc_cause, io.wakeup_ports[4].bits.uop.exc_cause connect issue_slots[2].wakeup_ports[4].bits.uop.exception, io.wakeup_ports[4].bits.uop.exception connect issue_slots[2].wakeup_ports[4].bits.uop.stale_pdst, io.wakeup_ports[4].bits.uop.stale_pdst connect issue_slots[2].wakeup_ports[4].bits.uop.ppred_busy, io.wakeup_ports[4].bits.uop.ppred_busy connect issue_slots[2].wakeup_ports[4].bits.uop.prs3_busy, io.wakeup_ports[4].bits.uop.prs3_busy connect issue_slots[2].wakeup_ports[4].bits.uop.prs2_busy, io.wakeup_ports[4].bits.uop.prs2_busy connect issue_slots[2].wakeup_ports[4].bits.uop.prs1_busy, io.wakeup_ports[4].bits.uop.prs1_busy connect issue_slots[2].wakeup_ports[4].bits.uop.ppred, io.wakeup_ports[4].bits.uop.ppred connect issue_slots[2].wakeup_ports[4].bits.uop.prs3, io.wakeup_ports[4].bits.uop.prs3 connect issue_slots[2].wakeup_ports[4].bits.uop.prs2, io.wakeup_ports[4].bits.uop.prs2 connect issue_slots[2].wakeup_ports[4].bits.uop.prs1, io.wakeup_ports[4].bits.uop.prs1 connect issue_slots[2].wakeup_ports[4].bits.uop.pdst, io.wakeup_ports[4].bits.uop.pdst connect issue_slots[2].wakeup_ports[4].bits.uop.rxq_idx, io.wakeup_ports[4].bits.uop.rxq_idx connect issue_slots[2].wakeup_ports[4].bits.uop.stq_idx, io.wakeup_ports[4].bits.uop.stq_idx connect issue_slots[2].wakeup_ports[4].bits.uop.ldq_idx, io.wakeup_ports[4].bits.uop.ldq_idx connect issue_slots[2].wakeup_ports[4].bits.uop.rob_idx, io.wakeup_ports[4].bits.uop.rob_idx connect issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.vec, io.wakeup_ports[4].bits.uop.fp_ctrl.vec connect issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.wflags, io.wakeup_ports[4].bits.uop.fp_ctrl.wflags connect issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.div, io.wakeup_ports[4].bits.uop.fp_ctrl.div connect issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.fma, io.wakeup_ports[4].bits.uop.fp_ctrl.fma connect issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.toint, io.wakeup_ports[4].bits.uop.fp_ctrl.toint connect issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.fromint, io.wakeup_ports[4].bits.uop.fp_ctrl.fromint connect issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.swap23, io.wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.swap12, io.wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.ren3, io.wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.ren2, io.wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.ren1, io.wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.wen, io.wakeup_ports[4].bits.uop.fp_ctrl.wen connect issue_slots[2].wakeup_ports[4].bits.uop.fp_ctrl.ldst, io.wakeup_ports[4].bits.uop.fp_ctrl.ldst connect issue_slots[2].wakeup_ports[4].bits.uop.op2_sel, io.wakeup_ports[4].bits.uop.op2_sel connect issue_slots[2].wakeup_ports[4].bits.uop.op1_sel, io.wakeup_ports[4].bits.uop.op1_sel connect issue_slots[2].wakeup_ports[4].bits.uop.imm_packed, io.wakeup_ports[4].bits.uop.imm_packed connect issue_slots[2].wakeup_ports[4].bits.uop.pimm, io.wakeup_ports[4].bits.uop.pimm connect issue_slots[2].wakeup_ports[4].bits.uop.imm_sel, io.wakeup_ports[4].bits.uop.imm_sel connect issue_slots[2].wakeup_ports[4].bits.uop.imm_rename, io.wakeup_ports[4].bits.uop.imm_rename connect issue_slots[2].wakeup_ports[4].bits.uop.taken, io.wakeup_ports[4].bits.uop.taken connect issue_slots[2].wakeup_ports[4].bits.uop.pc_lob, io.wakeup_ports[4].bits.uop.pc_lob connect issue_slots[2].wakeup_ports[4].bits.uop.edge_inst, io.wakeup_ports[4].bits.uop.edge_inst connect issue_slots[2].wakeup_ports[4].bits.uop.ftq_idx, io.wakeup_ports[4].bits.uop.ftq_idx connect issue_slots[2].wakeup_ports[4].bits.uop.is_mov, io.wakeup_ports[4].bits.uop.is_mov connect issue_slots[2].wakeup_ports[4].bits.uop.is_rocc, io.wakeup_ports[4].bits.uop.is_rocc connect issue_slots[2].wakeup_ports[4].bits.uop.is_sys_pc2epc, io.wakeup_ports[4].bits.uop.is_sys_pc2epc connect issue_slots[2].wakeup_ports[4].bits.uop.is_eret, io.wakeup_ports[4].bits.uop.is_eret connect issue_slots[2].wakeup_ports[4].bits.uop.is_amo, io.wakeup_ports[4].bits.uop.is_amo connect issue_slots[2].wakeup_ports[4].bits.uop.is_sfence, io.wakeup_ports[4].bits.uop.is_sfence connect issue_slots[2].wakeup_ports[4].bits.uop.is_fencei, io.wakeup_ports[4].bits.uop.is_fencei connect issue_slots[2].wakeup_ports[4].bits.uop.is_fence, io.wakeup_ports[4].bits.uop.is_fence connect issue_slots[2].wakeup_ports[4].bits.uop.is_sfb, io.wakeup_ports[4].bits.uop.is_sfb connect issue_slots[2].wakeup_ports[4].bits.uop.br_type, io.wakeup_ports[4].bits.uop.br_type connect issue_slots[2].wakeup_ports[4].bits.uop.br_tag, io.wakeup_ports[4].bits.uop.br_tag connect issue_slots[2].wakeup_ports[4].bits.uop.br_mask, io.wakeup_ports[4].bits.uop.br_mask connect issue_slots[2].wakeup_ports[4].bits.uop.dis_col_sel, io.wakeup_ports[4].bits.uop.dis_col_sel connect issue_slots[2].wakeup_ports[4].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect issue_slots[2].wakeup_ports[4].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect issue_slots[2].wakeup_ports[4].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect issue_slots[2].wakeup_ports[4].bits.uop.iw_p2_speculative_child, io.wakeup_ports[4].bits.uop.iw_p2_speculative_child connect issue_slots[2].wakeup_ports[4].bits.uop.iw_p1_speculative_child, io.wakeup_ports[4].bits.uop.iw_p1_speculative_child connect issue_slots[2].wakeup_ports[4].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect issue_slots[2].wakeup_ports[4].bits.uop.iw_issued_partial_agen, io.wakeup_ports[4].bits.uop.iw_issued_partial_agen connect issue_slots[2].wakeup_ports[4].bits.uop.iw_issued, io.wakeup_ports[4].bits.uop.iw_issued connect issue_slots[2].wakeup_ports[4].bits.uop.fu_code[0], io.wakeup_ports[4].bits.uop.fu_code[0] connect issue_slots[2].wakeup_ports[4].bits.uop.fu_code[1], io.wakeup_ports[4].bits.uop.fu_code[1] connect issue_slots[2].wakeup_ports[4].bits.uop.fu_code[2], io.wakeup_ports[4].bits.uop.fu_code[2] connect issue_slots[2].wakeup_ports[4].bits.uop.fu_code[3], io.wakeup_ports[4].bits.uop.fu_code[3] connect issue_slots[2].wakeup_ports[4].bits.uop.fu_code[4], io.wakeup_ports[4].bits.uop.fu_code[4] connect issue_slots[2].wakeup_ports[4].bits.uop.fu_code[5], io.wakeup_ports[4].bits.uop.fu_code[5] connect issue_slots[2].wakeup_ports[4].bits.uop.fu_code[6], io.wakeup_ports[4].bits.uop.fu_code[6] connect issue_slots[2].wakeup_ports[4].bits.uop.fu_code[7], io.wakeup_ports[4].bits.uop.fu_code[7] connect issue_slots[2].wakeup_ports[4].bits.uop.fu_code[8], io.wakeup_ports[4].bits.uop.fu_code[8] connect issue_slots[2].wakeup_ports[4].bits.uop.fu_code[9], io.wakeup_ports[4].bits.uop.fu_code[9] connect issue_slots[2].wakeup_ports[4].bits.uop.iq_type[0], io.wakeup_ports[4].bits.uop.iq_type[0] connect issue_slots[2].wakeup_ports[4].bits.uop.iq_type[1], io.wakeup_ports[4].bits.uop.iq_type[1] connect issue_slots[2].wakeup_ports[4].bits.uop.iq_type[2], io.wakeup_ports[4].bits.uop.iq_type[2] connect issue_slots[2].wakeup_ports[4].bits.uop.iq_type[3], io.wakeup_ports[4].bits.uop.iq_type[3] connect issue_slots[2].wakeup_ports[4].bits.uop.debug_pc, io.wakeup_ports[4].bits.uop.debug_pc connect issue_slots[2].wakeup_ports[4].bits.uop.is_rvc, io.wakeup_ports[4].bits.uop.is_rvc connect issue_slots[2].wakeup_ports[4].bits.uop.debug_inst, io.wakeup_ports[4].bits.uop.debug_inst connect issue_slots[2].wakeup_ports[4].bits.uop.inst, io.wakeup_ports[4].bits.uop.inst connect issue_slots[2].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[2].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[2].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[2].child_rebusys, io.child_rebusys connect issue_slots[2].squash_grant, io.squash_grant connect issue_slots[2].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[2].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[2].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[2].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[2].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[2].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[2].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[2].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[2].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[2].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[2].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[2].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[2].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[2].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect issue_slots[2].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect issue_slots[2].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[2].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect issue_slots[2].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect issue_slots[2].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[2].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[2].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[2].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[2].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[2].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[2].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[2].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[2].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[2].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect issue_slots[2].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[2].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[2].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[2].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[2].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[2].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[2].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[2].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[2].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[2].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[2].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[2].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[2].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[2].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[2].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[2].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[2].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[2].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[2].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[2].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[2].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[2].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[2].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[2].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect issue_slots[2].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect issue_slots[2].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect issue_slots[2].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect issue_slots[2].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect issue_slots[2].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect issue_slots[2].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect issue_slots[2].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect issue_slots[2].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect issue_slots[2].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect issue_slots[2].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect issue_slots[2].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect issue_slots[2].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect issue_slots[2].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect issue_slots[2].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect issue_slots[2].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect issue_slots[2].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect issue_slots[2].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect issue_slots[2].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect issue_slots[2].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[2].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect issue_slots[2].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect issue_slots[2].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect issue_slots[2].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[2].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[2].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[2].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[2].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect issue_slots[2].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect issue_slots[2].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[2].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect issue_slots[2].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[2].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect issue_slots[2].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[2].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[2].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[2].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect issue_slots[2].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[2].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[2].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect issue_slots[2].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect issue_slots[2].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect issue_slots[2].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect issue_slots[2].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect issue_slots[2].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect issue_slots[2].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect issue_slots[2].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect issue_slots[2].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect issue_slots[2].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect issue_slots[2].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect issue_slots[2].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect issue_slots[2].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect issue_slots[2].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect issue_slots[2].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect issue_slots[2].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect issue_slots[2].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect issue_slots[2].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect issue_slots[2].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect issue_slots[2].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect issue_slots[2].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect issue_slots[2].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect issue_slots[2].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect issue_slots[2].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[2].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[2].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[2].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[2].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[2].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[2].kill, io.flush_pipeline connect issue_slots[3].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy connect issue_slots[3].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask connect issue_slots[3].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable connect issue_slots[3].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc connect issue_slots[3].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc connect issue_slots[3].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if connect issue_slots[3].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if connect issue_slots[3].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if connect issue_slots[3].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if connect issue_slots[3].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if connect issue_slots[3].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ connect issue_slots[3].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm connect issue_slots[3].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val connect issue_slots[3].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op connect issue_slots[3].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw connect issue_slots[3].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en connect issue_slots[3].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype connect issue_slots[3].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype connect issue_slots[3].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype connect issue_slots[3].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 connect issue_slots[3].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 connect issue_slots[3].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 connect issue_slots[3].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst connect issue_slots[3].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 connect issue_slots[3].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd connect issue_slots[3].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit connect issue_slots[3].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique connect issue_slots[3].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq connect issue_slots[3].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq connect issue_slots[3].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed connect issue_slots[3].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size connect issue_slots[3].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd connect issue_slots[3].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause connect issue_slots[3].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception connect issue_slots[3].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst connect issue_slots[3].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy connect issue_slots[3].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy connect issue_slots[3].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy connect issue_slots[3].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy connect issue_slots[3].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred connect issue_slots[3].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 connect issue_slots[3].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 connect issue_slots[3].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 connect issue_slots[3].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst connect issue_slots[3].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx connect issue_slots[3].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx connect issue_slots[3].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx connect issue_slots[3].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst connect issue_slots[3].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel connect issue_slots[3].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel connect issue_slots[3].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed connect issue_slots[3].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm connect issue_slots[3].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel connect issue_slots[3].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename connect issue_slots[3].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken connect issue_slots[3].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob connect issue_slots[3].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst connect issue_slots[3].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx connect issue_slots[3].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov connect issue_slots[3].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc connect issue_slots[3].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc connect issue_slots[3].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret connect issue_slots[3].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo connect issue_slots[3].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence connect issue_slots[3].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei connect issue_slots[3].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence connect issue_slots[3].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb connect issue_slots[3].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type connect issue_slots[3].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag connect issue_slots[3].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask connect issue_slots[3].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel connect issue_slots[3].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect issue_slots[3].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect issue_slots[3].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect issue_slots[3].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child connect issue_slots[3].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child connect issue_slots[3].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect issue_slots[3].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen connect issue_slots[3].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued connect issue_slots[3].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] connect issue_slots[3].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] connect issue_slots[3].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] connect issue_slots[3].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] connect issue_slots[3].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] connect issue_slots[3].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] connect issue_slots[3].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] connect issue_slots[3].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] connect issue_slots[3].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] connect issue_slots[3].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] connect issue_slots[3].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] connect issue_slots[3].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] connect issue_slots[3].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] connect issue_slots[3].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] connect issue_slots[3].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc connect issue_slots[3].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc connect issue_slots[3].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst connect issue_slots[3].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst connect issue_slots[3].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[3].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy connect issue_slots[3].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask connect issue_slots[3].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable connect issue_slots[3].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc connect issue_slots[3].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc connect issue_slots[3].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if connect issue_slots[3].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if connect issue_slots[3].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if connect issue_slots[3].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if connect issue_slots[3].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if connect issue_slots[3].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ connect issue_slots[3].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm connect issue_slots[3].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val connect issue_slots[3].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op connect issue_slots[3].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw connect issue_slots[3].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en connect issue_slots[3].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype connect issue_slots[3].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype connect issue_slots[3].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype connect issue_slots[3].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 connect issue_slots[3].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 connect issue_slots[3].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 connect issue_slots[3].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst connect issue_slots[3].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 connect issue_slots[3].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd connect issue_slots[3].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit connect issue_slots[3].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique connect issue_slots[3].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq connect issue_slots[3].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq connect issue_slots[3].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed connect issue_slots[3].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size connect issue_slots[3].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd connect issue_slots[3].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause connect issue_slots[3].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception connect issue_slots[3].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst connect issue_slots[3].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy connect issue_slots[3].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy connect issue_slots[3].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy connect issue_slots[3].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy connect issue_slots[3].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred connect issue_slots[3].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 connect issue_slots[3].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 connect issue_slots[3].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 connect issue_slots[3].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst connect issue_slots[3].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx connect issue_slots[3].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx connect issue_slots[3].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx connect issue_slots[3].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst connect issue_slots[3].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel connect issue_slots[3].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel connect issue_slots[3].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed connect issue_slots[3].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm connect issue_slots[3].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel connect issue_slots[3].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename connect issue_slots[3].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken connect issue_slots[3].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob connect issue_slots[3].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst connect issue_slots[3].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx connect issue_slots[3].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov connect issue_slots[3].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc connect issue_slots[3].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc connect issue_slots[3].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret connect issue_slots[3].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo connect issue_slots[3].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence connect issue_slots[3].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei connect issue_slots[3].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence connect issue_slots[3].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb connect issue_slots[3].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type connect issue_slots[3].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag connect issue_slots[3].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask connect issue_slots[3].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel connect issue_slots[3].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect issue_slots[3].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect issue_slots[3].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect issue_slots[3].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child connect issue_slots[3].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child connect issue_slots[3].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect issue_slots[3].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen connect issue_slots[3].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued connect issue_slots[3].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] connect issue_slots[3].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] connect issue_slots[3].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] connect issue_slots[3].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] connect issue_slots[3].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] connect issue_slots[3].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] connect issue_slots[3].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] connect issue_slots[3].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] connect issue_slots[3].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] connect issue_slots[3].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] connect issue_slots[3].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] connect issue_slots[3].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] connect issue_slots[3].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] connect issue_slots[3].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] connect issue_slots[3].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc connect issue_slots[3].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc connect issue_slots[3].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst connect issue_slots[3].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst connect issue_slots[3].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[3].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy connect issue_slots[3].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask connect issue_slots[3].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable connect issue_slots[3].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc connect issue_slots[3].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc connect issue_slots[3].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if connect issue_slots[3].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if connect issue_slots[3].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if connect issue_slots[3].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if connect issue_slots[3].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if connect issue_slots[3].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ connect issue_slots[3].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm connect issue_slots[3].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val connect issue_slots[3].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op connect issue_slots[3].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw connect issue_slots[3].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en connect issue_slots[3].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype connect issue_slots[3].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype connect issue_slots[3].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype connect issue_slots[3].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3 connect issue_slots[3].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2 connect issue_slots[3].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1 connect issue_slots[3].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst connect issue_slots[3].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1 connect issue_slots[3].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd connect issue_slots[3].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit connect issue_slots[3].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique connect issue_slots[3].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq connect issue_slots[3].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq connect issue_slots[3].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed connect issue_slots[3].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size connect issue_slots[3].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd connect issue_slots[3].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause connect issue_slots[3].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception connect issue_slots[3].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst connect issue_slots[3].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy connect issue_slots[3].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy connect issue_slots[3].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy connect issue_slots[3].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy connect issue_slots[3].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred connect issue_slots[3].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3 connect issue_slots[3].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2 connect issue_slots[3].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1 connect issue_slots[3].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst connect issue_slots[3].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx connect issue_slots[3].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx connect issue_slots[3].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx connect issue_slots[3].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen connect issue_slots[3].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst connect issue_slots[3].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel connect issue_slots[3].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel connect issue_slots[3].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed connect issue_slots[3].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm connect issue_slots[3].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel connect issue_slots[3].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename connect issue_slots[3].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken connect issue_slots[3].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob connect issue_slots[3].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst connect issue_slots[3].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx connect issue_slots[3].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov connect issue_slots[3].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc connect issue_slots[3].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc connect issue_slots[3].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret connect issue_slots[3].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo connect issue_slots[3].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence connect issue_slots[3].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei connect issue_slots[3].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence connect issue_slots[3].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb connect issue_slots[3].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type connect issue_slots[3].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag connect issue_slots[3].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask connect issue_slots[3].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel connect issue_slots[3].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect issue_slots[3].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect issue_slots[3].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect issue_slots[3].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child connect issue_slots[3].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child connect issue_slots[3].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect issue_slots[3].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen connect issue_slots[3].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued connect issue_slots[3].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0] connect issue_slots[3].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1] connect issue_slots[3].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2] connect issue_slots[3].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3] connect issue_slots[3].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4] connect issue_slots[3].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5] connect issue_slots[3].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6] connect issue_slots[3].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7] connect issue_slots[3].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8] connect issue_slots[3].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9] connect issue_slots[3].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0] connect issue_slots[3].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1] connect issue_slots[3].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2] connect issue_slots[3].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3] connect issue_slots[3].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc connect issue_slots[3].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc connect issue_slots[3].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst connect issue_slots[3].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst connect issue_slots[3].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[3].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy connect issue_slots[3].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask connect issue_slots[3].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable connect issue_slots[3].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc connect issue_slots[3].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc connect issue_slots[3].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if connect issue_slots[3].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if connect issue_slots[3].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if connect issue_slots[3].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if connect issue_slots[3].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if connect issue_slots[3].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ connect issue_slots[3].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm connect issue_slots[3].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val connect issue_slots[3].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op connect issue_slots[3].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw connect issue_slots[3].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en connect issue_slots[3].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype connect issue_slots[3].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype connect issue_slots[3].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype connect issue_slots[3].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3 connect issue_slots[3].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2 connect issue_slots[3].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1 connect issue_slots[3].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst connect issue_slots[3].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1 connect issue_slots[3].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd connect issue_slots[3].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit connect issue_slots[3].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique connect issue_slots[3].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq connect issue_slots[3].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq connect issue_slots[3].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed connect issue_slots[3].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size connect issue_slots[3].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd connect issue_slots[3].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause connect issue_slots[3].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception connect issue_slots[3].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst connect issue_slots[3].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy connect issue_slots[3].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy connect issue_slots[3].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy connect issue_slots[3].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy connect issue_slots[3].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred connect issue_slots[3].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3 connect issue_slots[3].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2 connect issue_slots[3].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1 connect issue_slots[3].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst connect issue_slots[3].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx connect issue_slots[3].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx connect issue_slots[3].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx connect issue_slots[3].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen connect issue_slots[3].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst connect issue_slots[3].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel connect issue_slots[3].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel connect issue_slots[3].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed connect issue_slots[3].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm connect issue_slots[3].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel connect issue_slots[3].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename connect issue_slots[3].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken connect issue_slots[3].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob connect issue_slots[3].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst connect issue_slots[3].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx connect issue_slots[3].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov connect issue_slots[3].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc connect issue_slots[3].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc connect issue_slots[3].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret connect issue_slots[3].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo connect issue_slots[3].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence connect issue_slots[3].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei connect issue_slots[3].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence connect issue_slots[3].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb connect issue_slots[3].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type connect issue_slots[3].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag connect issue_slots[3].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask connect issue_slots[3].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel connect issue_slots[3].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect issue_slots[3].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect issue_slots[3].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect issue_slots[3].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child connect issue_slots[3].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child connect issue_slots[3].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect issue_slots[3].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen connect issue_slots[3].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued connect issue_slots[3].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0] connect issue_slots[3].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1] connect issue_slots[3].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2] connect issue_slots[3].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3] connect issue_slots[3].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4] connect issue_slots[3].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5] connect issue_slots[3].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6] connect issue_slots[3].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7] connect issue_slots[3].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8] connect issue_slots[3].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9] connect issue_slots[3].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0] connect issue_slots[3].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1] connect issue_slots[3].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2] connect issue_slots[3].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3] connect issue_slots[3].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc connect issue_slots[3].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc connect issue_slots[3].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst connect issue_slots[3].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst connect issue_slots[3].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[3].wakeup_ports[4].bits.rebusy, io.wakeup_ports[4].bits.rebusy connect issue_slots[3].wakeup_ports[4].bits.speculative_mask, io.wakeup_ports[4].bits.speculative_mask connect issue_slots[3].wakeup_ports[4].bits.bypassable, io.wakeup_ports[4].bits.bypassable connect issue_slots[3].wakeup_ports[4].bits.uop.debug_tsrc, io.wakeup_ports[4].bits.uop.debug_tsrc connect issue_slots[3].wakeup_ports[4].bits.uop.debug_fsrc, io.wakeup_ports[4].bits.uop.debug_fsrc connect issue_slots[3].wakeup_ports[4].bits.uop.bp_xcpt_if, io.wakeup_ports[4].bits.uop.bp_xcpt_if connect issue_slots[3].wakeup_ports[4].bits.uop.bp_debug_if, io.wakeup_ports[4].bits.uop.bp_debug_if connect issue_slots[3].wakeup_ports[4].bits.uop.xcpt_ma_if, io.wakeup_ports[4].bits.uop.xcpt_ma_if connect issue_slots[3].wakeup_ports[4].bits.uop.xcpt_ae_if, io.wakeup_ports[4].bits.uop.xcpt_ae_if connect issue_slots[3].wakeup_ports[4].bits.uop.xcpt_pf_if, io.wakeup_ports[4].bits.uop.xcpt_pf_if connect issue_slots[3].wakeup_ports[4].bits.uop.fp_typ, io.wakeup_ports[4].bits.uop.fp_typ connect issue_slots[3].wakeup_ports[4].bits.uop.fp_rm, io.wakeup_ports[4].bits.uop.fp_rm connect issue_slots[3].wakeup_ports[4].bits.uop.fp_val, io.wakeup_ports[4].bits.uop.fp_val connect issue_slots[3].wakeup_ports[4].bits.uop.fcn_op, io.wakeup_ports[4].bits.uop.fcn_op connect issue_slots[3].wakeup_ports[4].bits.uop.fcn_dw, io.wakeup_ports[4].bits.uop.fcn_dw connect issue_slots[3].wakeup_ports[4].bits.uop.frs3_en, io.wakeup_ports[4].bits.uop.frs3_en connect issue_slots[3].wakeup_ports[4].bits.uop.lrs2_rtype, io.wakeup_ports[4].bits.uop.lrs2_rtype connect issue_slots[3].wakeup_ports[4].bits.uop.lrs1_rtype, io.wakeup_ports[4].bits.uop.lrs1_rtype connect issue_slots[3].wakeup_ports[4].bits.uop.dst_rtype, io.wakeup_ports[4].bits.uop.dst_rtype connect issue_slots[3].wakeup_ports[4].bits.uop.lrs3, io.wakeup_ports[4].bits.uop.lrs3 connect issue_slots[3].wakeup_ports[4].bits.uop.lrs2, io.wakeup_ports[4].bits.uop.lrs2 connect issue_slots[3].wakeup_ports[4].bits.uop.lrs1, io.wakeup_ports[4].bits.uop.lrs1 connect issue_slots[3].wakeup_ports[4].bits.uop.ldst, io.wakeup_ports[4].bits.uop.ldst connect issue_slots[3].wakeup_ports[4].bits.uop.ldst_is_rs1, io.wakeup_ports[4].bits.uop.ldst_is_rs1 connect issue_slots[3].wakeup_ports[4].bits.uop.csr_cmd, io.wakeup_ports[4].bits.uop.csr_cmd connect issue_slots[3].wakeup_ports[4].bits.uop.flush_on_commit, io.wakeup_ports[4].bits.uop.flush_on_commit connect issue_slots[3].wakeup_ports[4].bits.uop.is_unique, io.wakeup_ports[4].bits.uop.is_unique connect issue_slots[3].wakeup_ports[4].bits.uop.uses_stq, io.wakeup_ports[4].bits.uop.uses_stq connect issue_slots[3].wakeup_ports[4].bits.uop.uses_ldq, io.wakeup_ports[4].bits.uop.uses_ldq connect issue_slots[3].wakeup_ports[4].bits.uop.mem_signed, io.wakeup_ports[4].bits.uop.mem_signed connect issue_slots[3].wakeup_ports[4].bits.uop.mem_size, io.wakeup_ports[4].bits.uop.mem_size connect issue_slots[3].wakeup_ports[4].bits.uop.mem_cmd, io.wakeup_ports[4].bits.uop.mem_cmd connect issue_slots[3].wakeup_ports[4].bits.uop.exc_cause, io.wakeup_ports[4].bits.uop.exc_cause connect issue_slots[3].wakeup_ports[4].bits.uop.exception, io.wakeup_ports[4].bits.uop.exception connect issue_slots[3].wakeup_ports[4].bits.uop.stale_pdst, io.wakeup_ports[4].bits.uop.stale_pdst connect issue_slots[3].wakeup_ports[4].bits.uop.ppred_busy, io.wakeup_ports[4].bits.uop.ppred_busy connect issue_slots[3].wakeup_ports[4].bits.uop.prs3_busy, io.wakeup_ports[4].bits.uop.prs3_busy connect issue_slots[3].wakeup_ports[4].bits.uop.prs2_busy, io.wakeup_ports[4].bits.uop.prs2_busy connect issue_slots[3].wakeup_ports[4].bits.uop.prs1_busy, io.wakeup_ports[4].bits.uop.prs1_busy connect issue_slots[3].wakeup_ports[4].bits.uop.ppred, io.wakeup_ports[4].bits.uop.ppred connect issue_slots[3].wakeup_ports[4].bits.uop.prs3, io.wakeup_ports[4].bits.uop.prs3 connect issue_slots[3].wakeup_ports[4].bits.uop.prs2, io.wakeup_ports[4].bits.uop.prs2 connect issue_slots[3].wakeup_ports[4].bits.uop.prs1, io.wakeup_ports[4].bits.uop.prs1 connect issue_slots[3].wakeup_ports[4].bits.uop.pdst, io.wakeup_ports[4].bits.uop.pdst connect issue_slots[3].wakeup_ports[4].bits.uop.rxq_idx, io.wakeup_ports[4].bits.uop.rxq_idx connect issue_slots[3].wakeup_ports[4].bits.uop.stq_idx, io.wakeup_ports[4].bits.uop.stq_idx connect issue_slots[3].wakeup_ports[4].bits.uop.ldq_idx, io.wakeup_ports[4].bits.uop.ldq_idx connect issue_slots[3].wakeup_ports[4].bits.uop.rob_idx, io.wakeup_ports[4].bits.uop.rob_idx connect issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.vec, io.wakeup_ports[4].bits.uop.fp_ctrl.vec connect issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.wflags, io.wakeup_ports[4].bits.uop.fp_ctrl.wflags connect issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.div, io.wakeup_ports[4].bits.uop.fp_ctrl.div connect issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.fma, io.wakeup_ports[4].bits.uop.fp_ctrl.fma connect issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.toint, io.wakeup_ports[4].bits.uop.fp_ctrl.toint connect issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.fromint, io.wakeup_ports[4].bits.uop.fp_ctrl.fromint connect issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.swap23, io.wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.swap12, io.wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.ren3, io.wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.ren2, io.wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.ren1, io.wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.wen, io.wakeup_ports[4].bits.uop.fp_ctrl.wen connect issue_slots[3].wakeup_ports[4].bits.uop.fp_ctrl.ldst, io.wakeup_ports[4].bits.uop.fp_ctrl.ldst connect issue_slots[3].wakeup_ports[4].bits.uop.op2_sel, io.wakeup_ports[4].bits.uop.op2_sel connect issue_slots[3].wakeup_ports[4].bits.uop.op1_sel, io.wakeup_ports[4].bits.uop.op1_sel connect issue_slots[3].wakeup_ports[4].bits.uop.imm_packed, io.wakeup_ports[4].bits.uop.imm_packed connect issue_slots[3].wakeup_ports[4].bits.uop.pimm, io.wakeup_ports[4].bits.uop.pimm connect issue_slots[3].wakeup_ports[4].bits.uop.imm_sel, io.wakeup_ports[4].bits.uop.imm_sel connect issue_slots[3].wakeup_ports[4].bits.uop.imm_rename, io.wakeup_ports[4].bits.uop.imm_rename connect issue_slots[3].wakeup_ports[4].bits.uop.taken, io.wakeup_ports[4].bits.uop.taken connect issue_slots[3].wakeup_ports[4].bits.uop.pc_lob, io.wakeup_ports[4].bits.uop.pc_lob connect issue_slots[3].wakeup_ports[4].bits.uop.edge_inst, io.wakeup_ports[4].bits.uop.edge_inst connect issue_slots[3].wakeup_ports[4].bits.uop.ftq_idx, io.wakeup_ports[4].bits.uop.ftq_idx connect issue_slots[3].wakeup_ports[4].bits.uop.is_mov, io.wakeup_ports[4].bits.uop.is_mov connect issue_slots[3].wakeup_ports[4].bits.uop.is_rocc, io.wakeup_ports[4].bits.uop.is_rocc connect issue_slots[3].wakeup_ports[4].bits.uop.is_sys_pc2epc, io.wakeup_ports[4].bits.uop.is_sys_pc2epc connect issue_slots[3].wakeup_ports[4].bits.uop.is_eret, io.wakeup_ports[4].bits.uop.is_eret connect issue_slots[3].wakeup_ports[4].bits.uop.is_amo, io.wakeup_ports[4].bits.uop.is_amo connect issue_slots[3].wakeup_ports[4].bits.uop.is_sfence, io.wakeup_ports[4].bits.uop.is_sfence connect issue_slots[3].wakeup_ports[4].bits.uop.is_fencei, io.wakeup_ports[4].bits.uop.is_fencei connect issue_slots[3].wakeup_ports[4].bits.uop.is_fence, io.wakeup_ports[4].bits.uop.is_fence connect issue_slots[3].wakeup_ports[4].bits.uop.is_sfb, io.wakeup_ports[4].bits.uop.is_sfb connect issue_slots[3].wakeup_ports[4].bits.uop.br_type, io.wakeup_ports[4].bits.uop.br_type connect issue_slots[3].wakeup_ports[4].bits.uop.br_tag, io.wakeup_ports[4].bits.uop.br_tag connect issue_slots[3].wakeup_ports[4].bits.uop.br_mask, io.wakeup_ports[4].bits.uop.br_mask connect issue_slots[3].wakeup_ports[4].bits.uop.dis_col_sel, io.wakeup_ports[4].bits.uop.dis_col_sel connect issue_slots[3].wakeup_ports[4].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect issue_slots[3].wakeup_ports[4].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect issue_slots[3].wakeup_ports[4].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect issue_slots[3].wakeup_ports[4].bits.uop.iw_p2_speculative_child, io.wakeup_ports[4].bits.uop.iw_p2_speculative_child connect issue_slots[3].wakeup_ports[4].bits.uop.iw_p1_speculative_child, io.wakeup_ports[4].bits.uop.iw_p1_speculative_child connect issue_slots[3].wakeup_ports[4].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect issue_slots[3].wakeup_ports[4].bits.uop.iw_issued_partial_agen, io.wakeup_ports[4].bits.uop.iw_issued_partial_agen connect issue_slots[3].wakeup_ports[4].bits.uop.iw_issued, io.wakeup_ports[4].bits.uop.iw_issued connect issue_slots[3].wakeup_ports[4].bits.uop.fu_code[0], io.wakeup_ports[4].bits.uop.fu_code[0] connect issue_slots[3].wakeup_ports[4].bits.uop.fu_code[1], io.wakeup_ports[4].bits.uop.fu_code[1] connect issue_slots[3].wakeup_ports[4].bits.uop.fu_code[2], io.wakeup_ports[4].bits.uop.fu_code[2] connect issue_slots[3].wakeup_ports[4].bits.uop.fu_code[3], io.wakeup_ports[4].bits.uop.fu_code[3] connect issue_slots[3].wakeup_ports[4].bits.uop.fu_code[4], io.wakeup_ports[4].bits.uop.fu_code[4] connect issue_slots[3].wakeup_ports[4].bits.uop.fu_code[5], io.wakeup_ports[4].bits.uop.fu_code[5] connect issue_slots[3].wakeup_ports[4].bits.uop.fu_code[6], io.wakeup_ports[4].bits.uop.fu_code[6] connect issue_slots[3].wakeup_ports[4].bits.uop.fu_code[7], io.wakeup_ports[4].bits.uop.fu_code[7] connect issue_slots[3].wakeup_ports[4].bits.uop.fu_code[8], io.wakeup_ports[4].bits.uop.fu_code[8] connect issue_slots[3].wakeup_ports[4].bits.uop.fu_code[9], io.wakeup_ports[4].bits.uop.fu_code[9] connect issue_slots[3].wakeup_ports[4].bits.uop.iq_type[0], io.wakeup_ports[4].bits.uop.iq_type[0] connect issue_slots[3].wakeup_ports[4].bits.uop.iq_type[1], io.wakeup_ports[4].bits.uop.iq_type[1] connect issue_slots[3].wakeup_ports[4].bits.uop.iq_type[2], io.wakeup_ports[4].bits.uop.iq_type[2] connect issue_slots[3].wakeup_ports[4].bits.uop.iq_type[3], io.wakeup_ports[4].bits.uop.iq_type[3] connect issue_slots[3].wakeup_ports[4].bits.uop.debug_pc, io.wakeup_ports[4].bits.uop.debug_pc connect issue_slots[3].wakeup_ports[4].bits.uop.is_rvc, io.wakeup_ports[4].bits.uop.is_rvc connect issue_slots[3].wakeup_ports[4].bits.uop.debug_inst, io.wakeup_ports[4].bits.uop.debug_inst connect issue_slots[3].wakeup_ports[4].bits.uop.inst, io.wakeup_ports[4].bits.uop.inst connect issue_slots[3].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[3].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[3].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[3].child_rebusys, io.child_rebusys connect issue_slots[3].squash_grant, io.squash_grant connect issue_slots[3].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[3].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[3].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[3].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[3].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[3].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[3].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[3].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[3].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[3].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[3].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[3].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[3].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[3].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect issue_slots[3].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect issue_slots[3].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[3].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect issue_slots[3].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect issue_slots[3].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[3].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[3].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[3].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[3].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[3].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[3].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[3].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[3].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[3].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect issue_slots[3].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[3].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[3].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[3].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[3].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[3].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[3].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[3].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[3].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[3].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[3].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[3].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[3].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[3].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[3].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[3].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[3].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[3].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[3].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[3].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[3].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[3].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[3].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[3].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect issue_slots[3].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect issue_slots[3].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect issue_slots[3].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect issue_slots[3].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect issue_slots[3].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect issue_slots[3].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect issue_slots[3].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect issue_slots[3].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect issue_slots[3].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect issue_slots[3].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect issue_slots[3].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect issue_slots[3].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect issue_slots[3].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect issue_slots[3].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect issue_slots[3].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect issue_slots[3].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect issue_slots[3].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect issue_slots[3].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect issue_slots[3].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[3].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect issue_slots[3].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect issue_slots[3].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect issue_slots[3].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[3].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[3].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[3].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[3].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect issue_slots[3].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect issue_slots[3].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[3].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect issue_slots[3].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[3].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect issue_slots[3].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[3].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[3].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[3].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect issue_slots[3].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[3].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[3].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect issue_slots[3].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect issue_slots[3].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect issue_slots[3].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect issue_slots[3].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect issue_slots[3].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect issue_slots[3].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect issue_slots[3].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect issue_slots[3].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect issue_slots[3].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect issue_slots[3].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect issue_slots[3].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect issue_slots[3].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect issue_slots[3].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect issue_slots[3].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect issue_slots[3].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect issue_slots[3].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect issue_slots[3].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect issue_slots[3].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect issue_slots[3].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect issue_slots[3].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect issue_slots[3].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect issue_slots[3].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect issue_slots[3].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[3].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[3].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[3].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[3].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[3].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[3].kill, io.flush_pipeline connect issue_slots[4].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy connect issue_slots[4].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask connect issue_slots[4].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable connect issue_slots[4].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc connect issue_slots[4].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc connect issue_slots[4].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if connect issue_slots[4].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if connect issue_slots[4].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if connect issue_slots[4].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if connect issue_slots[4].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if connect issue_slots[4].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ connect issue_slots[4].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm connect issue_slots[4].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val connect issue_slots[4].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op connect issue_slots[4].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw connect issue_slots[4].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en connect issue_slots[4].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype connect issue_slots[4].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype connect issue_slots[4].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype connect issue_slots[4].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 connect issue_slots[4].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 connect issue_slots[4].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 connect issue_slots[4].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst connect issue_slots[4].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 connect issue_slots[4].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd connect issue_slots[4].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit connect issue_slots[4].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique connect issue_slots[4].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq connect issue_slots[4].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq connect issue_slots[4].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed connect issue_slots[4].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size connect issue_slots[4].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd connect issue_slots[4].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause connect issue_slots[4].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception connect issue_slots[4].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst connect issue_slots[4].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy connect issue_slots[4].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy connect issue_slots[4].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy connect issue_slots[4].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy connect issue_slots[4].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred connect issue_slots[4].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 connect issue_slots[4].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 connect issue_slots[4].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 connect issue_slots[4].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst connect issue_slots[4].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx connect issue_slots[4].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx connect issue_slots[4].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx connect issue_slots[4].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst connect issue_slots[4].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel connect issue_slots[4].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel connect issue_slots[4].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed connect issue_slots[4].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm connect issue_slots[4].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel connect issue_slots[4].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename connect issue_slots[4].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken connect issue_slots[4].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob connect issue_slots[4].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst connect issue_slots[4].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx connect issue_slots[4].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov connect issue_slots[4].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc connect issue_slots[4].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc connect issue_slots[4].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret connect issue_slots[4].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo connect issue_slots[4].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence connect issue_slots[4].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei connect issue_slots[4].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence connect issue_slots[4].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb connect issue_slots[4].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type connect issue_slots[4].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag connect issue_slots[4].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask connect issue_slots[4].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel connect issue_slots[4].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect issue_slots[4].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect issue_slots[4].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect issue_slots[4].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child connect issue_slots[4].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child connect issue_slots[4].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect issue_slots[4].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen connect issue_slots[4].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued connect issue_slots[4].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] connect issue_slots[4].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] connect issue_slots[4].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] connect issue_slots[4].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] connect issue_slots[4].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] connect issue_slots[4].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] connect issue_slots[4].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] connect issue_slots[4].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] connect issue_slots[4].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] connect issue_slots[4].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] connect issue_slots[4].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] connect issue_slots[4].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] connect issue_slots[4].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] connect issue_slots[4].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] connect issue_slots[4].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc connect issue_slots[4].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc connect issue_slots[4].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst connect issue_slots[4].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst connect issue_slots[4].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[4].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy connect issue_slots[4].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask connect issue_slots[4].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable connect issue_slots[4].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc connect issue_slots[4].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc connect issue_slots[4].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if connect issue_slots[4].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if connect issue_slots[4].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if connect issue_slots[4].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if connect issue_slots[4].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if connect issue_slots[4].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ connect issue_slots[4].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm connect issue_slots[4].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val connect issue_slots[4].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op connect issue_slots[4].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw connect issue_slots[4].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en connect issue_slots[4].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype connect issue_slots[4].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype connect issue_slots[4].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype connect issue_slots[4].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 connect issue_slots[4].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 connect issue_slots[4].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 connect issue_slots[4].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst connect issue_slots[4].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 connect issue_slots[4].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd connect issue_slots[4].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit connect issue_slots[4].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique connect issue_slots[4].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq connect issue_slots[4].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq connect issue_slots[4].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed connect issue_slots[4].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size connect issue_slots[4].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd connect issue_slots[4].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause connect issue_slots[4].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception connect issue_slots[4].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst connect issue_slots[4].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy connect issue_slots[4].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy connect issue_slots[4].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy connect issue_slots[4].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy connect issue_slots[4].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred connect issue_slots[4].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 connect issue_slots[4].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 connect issue_slots[4].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 connect issue_slots[4].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst connect issue_slots[4].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx connect issue_slots[4].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx connect issue_slots[4].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx connect issue_slots[4].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst connect issue_slots[4].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel connect issue_slots[4].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel connect issue_slots[4].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed connect issue_slots[4].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm connect issue_slots[4].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel connect issue_slots[4].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename connect issue_slots[4].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken connect issue_slots[4].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob connect issue_slots[4].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst connect issue_slots[4].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx connect issue_slots[4].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov connect issue_slots[4].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc connect issue_slots[4].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc connect issue_slots[4].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret connect issue_slots[4].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo connect issue_slots[4].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence connect issue_slots[4].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei connect issue_slots[4].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence connect issue_slots[4].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb connect issue_slots[4].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type connect issue_slots[4].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag connect issue_slots[4].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask connect issue_slots[4].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel connect issue_slots[4].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect issue_slots[4].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect issue_slots[4].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect issue_slots[4].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child connect issue_slots[4].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child connect issue_slots[4].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect issue_slots[4].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen connect issue_slots[4].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued connect issue_slots[4].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] connect issue_slots[4].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] connect issue_slots[4].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] connect issue_slots[4].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] connect issue_slots[4].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] connect issue_slots[4].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] connect issue_slots[4].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] connect issue_slots[4].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] connect issue_slots[4].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] connect issue_slots[4].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] connect issue_slots[4].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] connect issue_slots[4].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] connect issue_slots[4].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] connect issue_slots[4].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] connect issue_slots[4].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc connect issue_slots[4].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc connect issue_slots[4].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst connect issue_slots[4].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst connect issue_slots[4].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[4].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy connect issue_slots[4].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask connect issue_slots[4].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable connect issue_slots[4].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc connect issue_slots[4].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc connect issue_slots[4].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if connect issue_slots[4].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if connect issue_slots[4].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if connect issue_slots[4].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if connect issue_slots[4].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if connect issue_slots[4].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ connect issue_slots[4].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm connect issue_slots[4].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val connect issue_slots[4].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op connect issue_slots[4].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw connect issue_slots[4].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en connect issue_slots[4].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype connect issue_slots[4].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype connect issue_slots[4].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype connect issue_slots[4].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3 connect issue_slots[4].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2 connect issue_slots[4].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1 connect issue_slots[4].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst connect issue_slots[4].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1 connect issue_slots[4].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd connect issue_slots[4].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit connect issue_slots[4].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique connect issue_slots[4].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq connect issue_slots[4].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq connect issue_slots[4].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed connect issue_slots[4].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size connect issue_slots[4].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd connect issue_slots[4].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause connect issue_slots[4].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception connect issue_slots[4].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst connect issue_slots[4].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy connect issue_slots[4].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy connect issue_slots[4].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy connect issue_slots[4].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy connect issue_slots[4].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred connect issue_slots[4].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3 connect issue_slots[4].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2 connect issue_slots[4].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1 connect issue_slots[4].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst connect issue_slots[4].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx connect issue_slots[4].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx connect issue_slots[4].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx connect issue_slots[4].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen connect issue_slots[4].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst connect issue_slots[4].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel connect issue_slots[4].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel connect issue_slots[4].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed connect issue_slots[4].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm connect issue_slots[4].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel connect issue_slots[4].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename connect issue_slots[4].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken connect issue_slots[4].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob connect issue_slots[4].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst connect issue_slots[4].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx connect issue_slots[4].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov connect issue_slots[4].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc connect issue_slots[4].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc connect issue_slots[4].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret connect issue_slots[4].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo connect issue_slots[4].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence connect issue_slots[4].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei connect issue_slots[4].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence connect issue_slots[4].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb connect issue_slots[4].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type connect issue_slots[4].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag connect issue_slots[4].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask connect issue_slots[4].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel connect issue_slots[4].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect issue_slots[4].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect issue_slots[4].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect issue_slots[4].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child connect issue_slots[4].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child connect issue_slots[4].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect issue_slots[4].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen connect issue_slots[4].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued connect issue_slots[4].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0] connect issue_slots[4].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1] connect issue_slots[4].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2] connect issue_slots[4].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3] connect issue_slots[4].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4] connect issue_slots[4].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5] connect issue_slots[4].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6] connect issue_slots[4].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7] connect issue_slots[4].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8] connect issue_slots[4].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9] connect issue_slots[4].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0] connect issue_slots[4].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1] connect issue_slots[4].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2] connect issue_slots[4].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3] connect issue_slots[4].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc connect issue_slots[4].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc connect issue_slots[4].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst connect issue_slots[4].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst connect issue_slots[4].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[4].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy connect issue_slots[4].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask connect issue_slots[4].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable connect issue_slots[4].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc connect issue_slots[4].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc connect issue_slots[4].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if connect issue_slots[4].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if connect issue_slots[4].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if connect issue_slots[4].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if connect issue_slots[4].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if connect issue_slots[4].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ connect issue_slots[4].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm connect issue_slots[4].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val connect issue_slots[4].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op connect issue_slots[4].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw connect issue_slots[4].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en connect issue_slots[4].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype connect issue_slots[4].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype connect issue_slots[4].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype connect issue_slots[4].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3 connect issue_slots[4].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2 connect issue_slots[4].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1 connect issue_slots[4].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst connect issue_slots[4].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1 connect issue_slots[4].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd connect issue_slots[4].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit connect issue_slots[4].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique connect issue_slots[4].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq connect issue_slots[4].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq connect issue_slots[4].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed connect issue_slots[4].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size connect issue_slots[4].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd connect issue_slots[4].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause connect issue_slots[4].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception connect issue_slots[4].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst connect issue_slots[4].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy connect issue_slots[4].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy connect issue_slots[4].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy connect issue_slots[4].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy connect issue_slots[4].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred connect issue_slots[4].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3 connect issue_slots[4].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2 connect issue_slots[4].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1 connect issue_slots[4].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst connect issue_slots[4].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx connect issue_slots[4].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx connect issue_slots[4].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx connect issue_slots[4].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen connect issue_slots[4].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst connect issue_slots[4].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel connect issue_slots[4].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel connect issue_slots[4].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed connect issue_slots[4].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm connect issue_slots[4].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel connect issue_slots[4].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename connect issue_slots[4].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken connect issue_slots[4].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob connect issue_slots[4].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst connect issue_slots[4].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx connect issue_slots[4].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov connect issue_slots[4].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc connect issue_slots[4].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc connect issue_slots[4].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret connect issue_slots[4].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo connect issue_slots[4].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence connect issue_slots[4].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei connect issue_slots[4].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence connect issue_slots[4].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb connect issue_slots[4].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type connect issue_slots[4].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag connect issue_slots[4].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask connect issue_slots[4].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel connect issue_slots[4].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect issue_slots[4].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect issue_slots[4].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect issue_slots[4].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child connect issue_slots[4].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child connect issue_slots[4].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect issue_slots[4].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen connect issue_slots[4].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued connect issue_slots[4].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0] connect issue_slots[4].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1] connect issue_slots[4].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2] connect issue_slots[4].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3] connect issue_slots[4].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4] connect issue_slots[4].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5] connect issue_slots[4].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6] connect issue_slots[4].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7] connect issue_slots[4].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8] connect issue_slots[4].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9] connect issue_slots[4].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0] connect issue_slots[4].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1] connect issue_slots[4].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2] connect issue_slots[4].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3] connect issue_slots[4].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc connect issue_slots[4].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc connect issue_slots[4].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst connect issue_slots[4].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst connect issue_slots[4].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[4].wakeup_ports[4].bits.rebusy, io.wakeup_ports[4].bits.rebusy connect issue_slots[4].wakeup_ports[4].bits.speculative_mask, io.wakeup_ports[4].bits.speculative_mask connect issue_slots[4].wakeup_ports[4].bits.bypassable, io.wakeup_ports[4].bits.bypassable connect issue_slots[4].wakeup_ports[4].bits.uop.debug_tsrc, io.wakeup_ports[4].bits.uop.debug_tsrc connect issue_slots[4].wakeup_ports[4].bits.uop.debug_fsrc, io.wakeup_ports[4].bits.uop.debug_fsrc connect issue_slots[4].wakeup_ports[4].bits.uop.bp_xcpt_if, io.wakeup_ports[4].bits.uop.bp_xcpt_if connect issue_slots[4].wakeup_ports[4].bits.uop.bp_debug_if, io.wakeup_ports[4].bits.uop.bp_debug_if connect issue_slots[4].wakeup_ports[4].bits.uop.xcpt_ma_if, io.wakeup_ports[4].bits.uop.xcpt_ma_if connect issue_slots[4].wakeup_ports[4].bits.uop.xcpt_ae_if, io.wakeup_ports[4].bits.uop.xcpt_ae_if connect issue_slots[4].wakeup_ports[4].bits.uop.xcpt_pf_if, io.wakeup_ports[4].bits.uop.xcpt_pf_if connect issue_slots[4].wakeup_ports[4].bits.uop.fp_typ, io.wakeup_ports[4].bits.uop.fp_typ connect issue_slots[4].wakeup_ports[4].bits.uop.fp_rm, io.wakeup_ports[4].bits.uop.fp_rm connect issue_slots[4].wakeup_ports[4].bits.uop.fp_val, io.wakeup_ports[4].bits.uop.fp_val connect issue_slots[4].wakeup_ports[4].bits.uop.fcn_op, io.wakeup_ports[4].bits.uop.fcn_op connect issue_slots[4].wakeup_ports[4].bits.uop.fcn_dw, io.wakeup_ports[4].bits.uop.fcn_dw connect issue_slots[4].wakeup_ports[4].bits.uop.frs3_en, io.wakeup_ports[4].bits.uop.frs3_en connect issue_slots[4].wakeup_ports[4].bits.uop.lrs2_rtype, io.wakeup_ports[4].bits.uop.lrs2_rtype connect issue_slots[4].wakeup_ports[4].bits.uop.lrs1_rtype, io.wakeup_ports[4].bits.uop.lrs1_rtype connect issue_slots[4].wakeup_ports[4].bits.uop.dst_rtype, io.wakeup_ports[4].bits.uop.dst_rtype connect issue_slots[4].wakeup_ports[4].bits.uop.lrs3, io.wakeup_ports[4].bits.uop.lrs3 connect issue_slots[4].wakeup_ports[4].bits.uop.lrs2, io.wakeup_ports[4].bits.uop.lrs2 connect issue_slots[4].wakeup_ports[4].bits.uop.lrs1, io.wakeup_ports[4].bits.uop.lrs1 connect issue_slots[4].wakeup_ports[4].bits.uop.ldst, io.wakeup_ports[4].bits.uop.ldst connect issue_slots[4].wakeup_ports[4].bits.uop.ldst_is_rs1, io.wakeup_ports[4].bits.uop.ldst_is_rs1 connect issue_slots[4].wakeup_ports[4].bits.uop.csr_cmd, io.wakeup_ports[4].bits.uop.csr_cmd connect issue_slots[4].wakeup_ports[4].bits.uop.flush_on_commit, io.wakeup_ports[4].bits.uop.flush_on_commit connect issue_slots[4].wakeup_ports[4].bits.uop.is_unique, io.wakeup_ports[4].bits.uop.is_unique connect issue_slots[4].wakeup_ports[4].bits.uop.uses_stq, io.wakeup_ports[4].bits.uop.uses_stq connect issue_slots[4].wakeup_ports[4].bits.uop.uses_ldq, io.wakeup_ports[4].bits.uop.uses_ldq connect issue_slots[4].wakeup_ports[4].bits.uop.mem_signed, io.wakeup_ports[4].bits.uop.mem_signed connect issue_slots[4].wakeup_ports[4].bits.uop.mem_size, io.wakeup_ports[4].bits.uop.mem_size connect issue_slots[4].wakeup_ports[4].bits.uop.mem_cmd, io.wakeup_ports[4].bits.uop.mem_cmd connect issue_slots[4].wakeup_ports[4].bits.uop.exc_cause, io.wakeup_ports[4].bits.uop.exc_cause connect issue_slots[4].wakeup_ports[4].bits.uop.exception, io.wakeup_ports[4].bits.uop.exception connect issue_slots[4].wakeup_ports[4].bits.uop.stale_pdst, io.wakeup_ports[4].bits.uop.stale_pdst connect issue_slots[4].wakeup_ports[4].bits.uop.ppred_busy, io.wakeup_ports[4].bits.uop.ppred_busy connect issue_slots[4].wakeup_ports[4].bits.uop.prs3_busy, io.wakeup_ports[4].bits.uop.prs3_busy connect issue_slots[4].wakeup_ports[4].bits.uop.prs2_busy, io.wakeup_ports[4].bits.uop.prs2_busy connect issue_slots[4].wakeup_ports[4].bits.uop.prs1_busy, io.wakeup_ports[4].bits.uop.prs1_busy connect issue_slots[4].wakeup_ports[4].bits.uop.ppred, io.wakeup_ports[4].bits.uop.ppred connect issue_slots[4].wakeup_ports[4].bits.uop.prs3, io.wakeup_ports[4].bits.uop.prs3 connect issue_slots[4].wakeup_ports[4].bits.uop.prs2, io.wakeup_ports[4].bits.uop.prs2 connect issue_slots[4].wakeup_ports[4].bits.uop.prs1, io.wakeup_ports[4].bits.uop.prs1 connect issue_slots[4].wakeup_ports[4].bits.uop.pdst, io.wakeup_ports[4].bits.uop.pdst connect issue_slots[4].wakeup_ports[4].bits.uop.rxq_idx, io.wakeup_ports[4].bits.uop.rxq_idx connect issue_slots[4].wakeup_ports[4].bits.uop.stq_idx, io.wakeup_ports[4].bits.uop.stq_idx connect issue_slots[4].wakeup_ports[4].bits.uop.ldq_idx, io.wakeup_ports[4].bits.uop.ldq_idx connect issue_slots[4].wakeup_ports[4].bits.uop.rob_idx, io.wakeup_ports[4].bits.uop.rob_idx connect issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.vec, io.wakeup_ports[4].bits.uop.fp_ctrl.vec connect issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.wflags, io.wakeup_ports[4].bits.uop.fp_ctrl.wflags connect issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.div, io.wakeup_ports[4].bits.uop.fp_ctrl.div connect issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.fma, io.wakeup_ports[4].bits.uop.fp_ctrl.fma connect issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.toint, io.wakeup_ports[4].bits.uop.fp_ctrl.toint connect issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.fromint, io.wakeup_ports[4].bits.uop.fp_ctrl.fromint connect issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.swap23, io.wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.swap12, io.wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.ren3, io.wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.ren2, io.wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.ren1, io.wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.wen, io.wakeup_ports[4].bits.uop.fp_ctrl.wen connect issue_slots[4].wakeup_ports[4].bits.uop.fp_ctrl.ldst, io.wakeup_ports[4].bits.uop.fp_ctrl.ldst connect issue_slots[4].wakeup_ports[4].bits.uop.op2_sel, io.wakeup_ports[4].bits.uop.op2_sel connect issue_slots[4].wakeup_ports[4].bits.uop.op1_sel, io.wakeup_ports[4].bits.uop.op1_sel connect issue_slots[4].wakeup_ports[4].bits.uop.imm_packed, io.wakeup_ports[4].bits.uop.imm_packed connect issue_slots[4].wakeup_ports[4].bits.uop.pimm, io.wakeup_ports[4].bits.uop.pimm connect issue_slots[4].wakeup_ports[4].bits.uop.imm_sel, io.wakeup_ports[4].bits.uop.imm_sel connect issue_slots[4].wakeup_ports[4].bits.uop.imm_rename, io.wakeup_ports[4].bits.uop.imm_rename connect issue_slots[4].wakeup_ports[4].bits.uop.taken, io.wakeup_ports[4].bits.uop.taken connect issue_slots[4].wakeup_ports[4].bits.uop.pc_lob, io.wakeup_ports[4].bits.uop.pc_lob connect issue_slots[4].wakeup_ports[4].bits.uop.edge_inst, io.wakeup_ports[4].bits.uop.edge_inst connect issue_slots[4].wakeup_ports[4].bits.uop.ftq_idx, io.wakeup_ports[4].bits.uop.ftq_idx connect issue_slots[4].wakeup_ports[4].bits.uop.is_mov, io.wakeup_ports[4].bits.uop.is_mov connect issue_slots[4].wakeup_ports[4].bits.uop.is_rocc, io.wakeup_ports[4].bits.uop.is_rocc connect issue_slots[4].wakeup_ports[4].bits.uop.is_sys_pc2epc, io.wakeup_ports[4].bits.uop.is_sys_pc2epc connect issue_slots[4].wakeup_ports[4].bits.uop.is_eret, io.wakeup_ports[4].bits.uop.is_eret connect issue_slots[4].wakeup_ports[4].bits.uop.is_amo, io.wakeup_ports[4].bits.uop.is_amo connect issue_slots[4].wakeup_ports[4].bits.uop.is_sfence, io.wakeup_ports[4].bits.uop.is_sfence connect issue_slots[4].wakeup_ports[4].bits.uop.is_fencei, io.wakeup_ports[4].bits.uop.is_fencei connect issue_slots[4].wakeup_ports[4].bits.uop.is_fence, io.wakeup_ports[4].bits.uop.is_fence connect issue_slots[4].wakeup_ports[4].bits.uop.is_sfb, io.wakeup_ports[4].bits.uop.is_sfb connect issue_slots[4].wakeup_ports[4].bits.uop.br_type, io.wakeup_ports[4].bits.uop.br_type connect issue_slots[4].wakeup_ports[4].bits.uop.br_tag, io.wakeup_ports[4].bits.uop.br_tag connect issue_slots[4].wakeup_ports[4].bits.uop.br_mask, io.wakeup_ports[4].bits.uop.br_mask connect issue_slots[4].wakeup_ports[4].bits.uop.dis_col_sel, io.wakeup_ports[4].bits.uop.dis_col_sel connect issue_slots[4].wakeup_ports[4].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect issue_slots[4].wakeup_ports[4].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect issue_slots[4].wakeup_ports[4].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect issue_slots[4].wakeup_ports[4].bits.uop.iw_p2_speculative_child, io.wakeup_ports[4].bits.uop.iw_p2_speculative_child connect issue_slots[4].wakeup_ports[4].bits.uop.iw_p1_speculative_child, io.wakeup_ports[4].bits.uop.iw_p1_speculative_child connect issue_slots[4].wakeup_ports[4].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect issue_slots[4].wakeup_ports[4].bits.uop.iw_issued_partial_agen, io.wakeup_ports[4].bits.uop.iw_issued_partial_agen connect issue_slots[4].wakeup_ports[4].bits.uop.iw_issued, io.wakeup_ports[4].bits.uop.iw_issued connect issue_slots[4].wakeup_ports[4].bits.uop.fu_code[0], io.wakeup_ports[4].bits.uop.fu_code[0] connect issue_slots[4].wakeup_ports[4].bits.uop.fu_code[1], io.wakeup_ports[4].bits.uop.fu_code[1] connect issue_slots[4].wakeup_ports[4].bits.uop.fu_code[2], io.wakeup_ports[4].bits.uop.fu_code[2] connect issue_slots[4].wakeup_ports[4].bits.uop.fu_code[3], io.wakeup_ports[4].bits.uop.fu_code[3] connect issue_slots[4].wakeup_ports[4].bits.uop.fu_code[4], io.wakeup_ports[4].bits.uop.fu_code[4] connect issue_slots[4].wakeup_ports[4].bits.uop.fu_code[5], io.wakeup_ports[4].bits.uop.fu_code[5] connect issue_slots[4].wakeup_ports[4].bits.uop.fu_code[6], io.wakeup_ports[4].bits.uop.fu_code[6] connect issue_slots[4].wakeup_ports[4].bits.uop.fu_code[7], io.wakeup_ports[4].bits.uop.fu_code[7] connect issue_slots[4].wakeup_ports[4].bits.uop.fu_code[8], io.wakeup_ports[4].bits.uop.fu_code[8] connect issue_slots[4].wakeup_ports[4].bits.uop.fu_code[9], io.wakeup_ports[4].bits.uop.fu_code[9] connect issue_slots[4].wakeup_ports[4].bits.uop.iq_type[0], io.wakeup_ports[4].bits.uop.iq_type[0] connect issue_slots[4].wakeup_ports[4].bits.uop.iq_type[1], io.wakeup_ports[4].bits.uop.iq_type[1] connect issue_slots[4].wakeup_ports[4].bits.uop.iq_type[2], io.wakeup_ports[4].bits.uop.iq_type[2] connect issue_slots[4].wakeup_ports[4].bits.uop.iq_type[3], io.wakeup_ports[4].bits.uop.iq_type[3] connect issue_slots[4].wakeup_ports[4].bits.uop.debug_pc, io.wakeup_ports[4].bits.uop.debug_pc connect issue_slots[4].wakeup_ports[4].bits.uop.is_rvc, io.wakeup_ports[4].bits.uop.is_rvc connect issue_slots[4].wakeup_ports[4].bits.uop.debug_inst, io.wakeup_ports[4].bits.uop.debug_inst connect issue_slots[4].wakeup_ports[4].bits.uop.inst, io.wakeup_ports[4].bits.uop.inst connect issue_slots[4].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[4].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[4].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[4].child_rebusys, io.child_rebusys connect issue_slots[4].squash_grant, io.squash_grant connect issue_slots[4].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[4].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[4].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[4].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[4].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[4].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[4].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[4].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[4].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[4].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[4].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[4].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[4].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[4].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect issue_slots[4].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect issue_slots[4].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[4].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect issue_slots[4].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect issue_slots[4].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[4].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[4].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[4].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[4].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[4].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[4].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[4].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[4].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[4].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect issue_slots[4].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[4].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[4].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[4].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[4].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[4].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[4].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[4].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[4].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[4].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[4].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[4].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[4].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[4].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[4].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[4].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[4].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[4].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[4].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[4].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[4].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[4].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[4].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[4].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect issue_slots[4].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect issue_slots[4].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect issue_slots[4].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect issue_slots[4].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect issue_slots[4].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect issue_slots[4].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect issue_slots[4].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect issue_slots[4].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect issue_slots[4].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect issue_slots[4].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect issue_slots[4].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect issue_slots[4].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect issue_slots[4].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect issue_slots[4].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect issue_slots[4].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect issue_slots[4].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect issue_slots[4].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect issue_slots[4].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect issue_slots[4].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[4].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect issue_slots[4].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect issue_slots[4].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect issue_slots[4].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[4].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[4].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[4].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[4].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect issue_slots[4].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect issue_slots[4].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[4].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect issue_slots[4].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[4].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect issue_slots[4].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[4].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[4].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[4].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect issue_slots[4].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[4].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[4].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect issue_slots[4].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect issue_slots[4].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect issue_slots[4].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect issue_slots[4].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect issue_slots[4].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect issue_slots[4].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect issue_slots[4].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect issue_slots[4].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect issue_slots[4].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect issue_slots[4].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect issue_slots[4].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect issue_slots[4].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect issue_slots[4].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect issue_slots[4].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect issue_slots[4].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect issue_slots[4].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect issue_slots[4].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect issue_slots[4].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect issue_slots[4].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect issue_slots[4].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect issue_slots[4].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect issue_slots[4].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect issue_slots[4].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[4].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[4].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[4].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[4].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[4].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[4].kill, io.flush_pipeline connect issue_slots[5].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy connect issue_slots[5].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask connect issue_slots[5].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable connect issue_slots[5].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc connect issue_slots[5].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc connect issue_slots[5].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if connect issue_slots[5].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if connect issue_slots[5].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if connect issue_slots[5].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if connect issue_slots[5].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if connect issue_slots[5].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ connect issue_slots[5].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm connect issue_slots[5].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val connect issue_slots[5].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op connect issue_slots[5].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw connect issue_slots[5].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en connect issue_slots[5].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype connect issue_slots[5].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype connect issue_slots[5].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype connect issue_slots[5].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 connect issue_slots[5].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 connect issue_slots[5].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 connect issue_slots[5].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst connect issue_slots[5].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 connect issue_slots[5].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd connect issue_slots[5].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit connect issue_slots[5].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique connect issue_slots[5].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq connect issue_slots[5].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq connect issue_slots[5].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed connect issue_slots[5].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size connect issue_slots[5].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd connect issue_slots[5].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause connect issue_slots[5].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception connect issue_slots[5].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst connect issue_slots[5].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy connect issue_slots[5].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy connect issue_slots[5].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy connect issue_slots[5].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy connect issue_slots[5].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred connect issue_slots[5].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 connect issue_slots[5].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 connect issue_slots[5].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 connect issue_slots[5].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst connect issue_slots[5].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx connect issue_slots[5].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx connect issue_slots[5].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx connect issue_slots[5].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst connect issue_slots[5].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel connect issue_slots[5].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel connect issue_slots[5].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed connect issue_slots[5].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm connect issue_slots[5].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel connect issue_slots[5].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename connect issue_slots[5].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken connect issue_slots[5].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob connect issue_slots[5].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst connect issue_slots[5].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx connect issue_slots[5].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov connect issue_slots[5].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc connect issue_slots[5].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc connect issue_slots[5].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret connect issue_slots[5].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo connect issue_slots[5].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence connect issue_slots[5].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei connect issue_slots[5].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence connect issue_slots[5].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb connect issue_slots[5].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type connect issue_slots[5].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag connect issue_slots[5].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask connect issue_slots[5].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel connect issue_slots[5].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect issue_slots[5].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect issue_slots[5].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect issue_slots[5].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child connect issue_slots[5].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child connect issue_slots[5].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect issue_slots[5].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen connect issue_slots[5].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued connect issue_slots[5].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] connect issue_slots[5].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] connect issue_slots[5].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] connect issue_slots[5].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] connect issue_slots[5].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] connect issue_slots[5].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] connect issue_slots[5].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] connect issue_slots[5].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] connect issue_slots[5].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] connect issue_slots[5].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] connect issue_slots[5].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] connect issue_slots[5].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] connect issue_slots[5].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] connect issue_slots[5].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] connect issue_slots[5].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc connect issue_slots[5].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc connect issue_slots[5].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst connect issue_slots[5].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst connect issue_slots[5].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[5].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy connect issue_slots[5].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask connect issue_slots[5].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable connect issue_slots[5].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc connect issue_slots[5].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc connect issue_slots[5].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if connect issue_slots[5].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if connect issue_slots[5].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if connect issue_slots[5].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if connect issue_slots[5].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if connect issue_slots[5].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ connect issue_slots[5].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm connect issue_slots[5].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val connect issue_slots[5].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op connect issue_slots[5].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw connect issue_slots[5].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en connect issue_slots[5].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype connect issue_slots[5].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype connect issue_slots[5].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype connect issue_slots[5].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 connect issue_slots[5].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 connect issue_slots[5].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 connect issue_slots[5].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst connect issue_slots[5].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 connect issue_slots[5].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd connect issue_slots[5].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit connect issue_slots[5].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique connect issue_slots[5].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq connect issue_slots[5].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq connect issue_slots[5].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed connect issue_slots[5].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size connect issue_slots[5].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd connect issue_slots[5].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause connect issue_slots[5].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception connect issue_slots[5].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst connect issue_slots[5].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy connect issue_slots[5].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy connect issue_slots[5].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy connect issue_slots[5].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy connect issue_slots[5].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred connect issue_slots[5].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 connect issue_slots[5].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 connect issue_slots[5].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 connect issue_slots[5].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst connect issue_slots[5].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx connect issue_slots[5].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx connect issue_slots[5].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx connect issue_slots[5].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst connect issue_slots[5].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel connect issue_slots[5].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel connect issue_slots[5].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed connect issue_slots[5].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm connect issue_slots[5].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel connect issue_slots[5].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename connect issue_slots[5].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken connect issue_slots[5].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob connect issue_slots[5].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst connect issue_slots[5].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx connect issue_slots[5].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov connect issue_slots[5].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc connect issue_slots[5].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc connect issue_slots[5].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret connect issue_slots[5].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo connect issue_slots[5].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence connect issue_slots[5].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei connect issue_slots[5].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence connect issue_slots[5].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb connect issue_slots[5].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type connect issue_slots[5].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag connect issue_slots[5].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask connect issue_slots[5].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel connect issue_slots[5].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect issue_slots[5].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect issue_slots[5].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect issue_slots[5].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child connect issue_slots[5].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child connect issue_slots[5].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect issue_slots[5].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen connect issue_slots[5].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued connect issue_slots[5].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] connect issue_slots[5].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] connect issue_slots[5].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] connect issue_slots[5].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] connect issue_slots[5].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] connect issue_slots[5].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] connect issue_slots[5].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] connect issue_slots[5].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] connect issue_slots[5].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] connect issue_slots[5].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] connect issue_slots[5].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] connect issue_slots[5].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] connect issue_slots[5].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] connect issue_slots[5].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] connect issue_slots[5].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc connect issue_slots[5].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc connect issue_slots[5].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst connect issue_slots[5].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst connect issue_slots[5].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[5].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy connect issue_slots[5].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask connect issue_slots[5].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable connect issue_slots[5].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc connect issue_slots[5].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc connect issue_slots[5].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if connect issue_slots[5].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if connect issue_slots[5].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if connect issue_slots[5].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if connect issue_slots[5].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if connect issue_slots[5].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ connect issue_slots[5].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm connect issue_slots[5].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val connect issue_slots[5].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op connect issue_slots[5].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw connect issue_slots[5].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en connect issue_slots[5].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype connect issue_slots[5].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype connect issue_slots[5].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype connect issue_slots[5].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3 connect issue_slots[5].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2 connect issue_slots[5].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1 connect issue_slots[5].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst connect issue_slots[5].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1 connect issue_slots[5].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd connect issue_slots[5].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit connect issue_slots[5].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique connect issue_slots[5].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq connect issue_slots[5].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq connect issue_slots[5].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed connect issue_slots[5].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size connect issue_slots[5].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd connect issue_slots[5].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause connect issue_slots[5].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception connect issue_slots[5].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst connect issue_slots[5].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy connect issue_slots[5].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy connect issue_slots[5].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy connect issue_slots[5].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy connect issue_slots[5].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred connect issue_slots[5].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3 connect issue_slots[5].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2 connect issue_slots[5].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1 connect issue_slots[5].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst connect issue_slots[5].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx connect issue_slots[5].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx connect issue_slots[5].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx connect issue_slots[5].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen connect issue_slots[5].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst connect issue_slots[5].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel connect issue_slots[5].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel connect issue_slots[5].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed connect issue_slots[5].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm connect issue_slots[5].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel connect issue_slots[5].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename connect issue_slots[5].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken connect issue_slots[5].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob connect issue_slots[5].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst connect issue_slots[5].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx connect issue_slots[5].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov connect issue_slots[5].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc connect issue_slots[5].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc connect issue_slots[5].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret connect issue_slots[5].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo connect issue_slots[5].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence connect issue_slots[5].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei connect issue_slots[5].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence connect issue_slots[5].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb connect issue_slots[5].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type connect issue_slots[5].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag connect issue_slots[5].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask connect issue_slots[5].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel connect issue_slots[5].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect issue_slots[5].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect issue_slots[5].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect issue_slots[5].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child connect issue_slots[5].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child connect issue_slots[5].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect issue_slots[5].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen connect issue_slots[5].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued connect issue_slots[5].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0] connect issue_slots[5].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1] connect issue_slots[5].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2] connect issue_slots[5].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3] connect issue_slots[5].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4] connect issue_slots[5].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5] connect issue_slots[5].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6] connect issue_slots[5].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7] connect issue_slots[5].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8] connect issue_slots[5].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9] connect issue_slots[5].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0] connect issue_slots[5].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1] connect issue_slots[5].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2] connect issue_slots[5].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3] connect issue_slots[5].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc connect issue_slots[5].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc connect issue_slots[5].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst connect issue_slots[5].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst connect issue_slots[5].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[5].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy connect issue_slots[5].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask connect issue_slots[5].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable connect issue_slots[5].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc connect issue_slots[5].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc connect issue_slots[5].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if connect issue_slots[5].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if connect issue_slots[5].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if connect issue_slots[5].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if connect issue_slots[5].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if connect issue_slots[5].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ connect issue_slots[5].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm connect issue_slots[5].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val connect issue_slots[5].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op connect issue_slots[5].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw connect issue_slots[5].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en connect issue_slots[5].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype connect issue_slots[5].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype connect issue_slots[5].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype connect issue_slots[5].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3 connect issue_slots[5].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2 connect issue_slots[5].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1 connect issue_slots[5].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst connect issue_slots[5].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1 connect issue_slots[5].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd connect issue_slots[5].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit connect issue_slots[5].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique connect issue_slots[5].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq connect issue_slots[5].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq connect issue_slots[5].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed connect issue_slots[5].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size connect issue_slots[5].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd connect issue_slots[5].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause connect issue_slots[5].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception connect issue_slots[5].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst connect issue_slots[5].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy connect issue_slots[5].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy connect issue_slots[5].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy connect issue_slots[5].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy connect issue_slots[5].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred connect issue_slots[5].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3 connect issue_slots[5].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2 connect issue_slots[5].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1 connect issue_slots[5].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst connect issue_slots[5].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx connect issue_slots[5].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx connect issue_slots[5].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx connect issue_slots[5].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen connect issue_slots[5].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst connect issue_slots[5].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel connect issue_slots[5].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel connect issue_slots[5].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed connect issue_slots[5].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm connect issue_slots[5].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel connect issue_slots[5].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename connect issue_slots[5].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken connect issue_slots[5].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob connect issue_slots[5].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst connect issue_slots[5].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx connect issue_slots[5].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov connect issue_slots[5].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc connect issue_slots[5].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc connect issue_slots[5].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret connect issue_slots[5].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo connect issue_slots[5].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence connect issue_slots[5].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei connect issue_slots[5].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence connect issue_slots[5].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb connect issue_slots[5].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type connect issue_slots[5].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag connect issue_slots[5].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask connect issue_slots[5].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel connect issue_slots[5].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect issue_slots[5].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect issue_slots[5].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect issue_slots[5].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child connect issue_slots[5].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child connect issue_slots[5].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect issue_slots[5].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen connect issue_slots[5].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued connect issue_slots[5].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0] connect issue_slots[5].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1] connect issue_slots[5].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2] connect issue_slots[5].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3] connect issue_slots[5].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4] connect issue_slots[5].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5] connect issue_slots[5].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6] connect issue_slots[5].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7] connect issue_slots[5].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8] connect issue_slots[5].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9] connect issue_slots[5].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0] connect issue_slots[5].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1] connect issue_slots[5].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2] connect issue_slots[5].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3] connect issue_slots[5].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc connect issue_slots[5].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc connect issue_slots[5].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst connect issue_slots[5].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst connect issue_slots[5].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[5].wakeup_ports[4].bits.rebusy, io.wakeup_ports[4].bits.rebusy connect issue_slots[5].wakeup_ports[4].bits.speculative_mask, io.wakeup_ports[4].bits.speculative_mask connect issue_slots[5].wakeup_ports[4].bits.bypassable, io.wakeup_ports[4].bits.bypassable connect issue_slots[5].wakeup_ports[4].bits.uop.debug_tsrc, io.wakeup_ports[4].bits.uop.debug_tsrc connect issue_slots[5].wakeup_ports[4].bits.uop.debug_fsrc, io.wakeup_ports[4].bits.uop.debug_fsrc connect issue_slots[5].wakeup_ports[4].bits.uop.bp_xcpt_if, io.wakeup_ports[4].bits.uop.bp_xcpt_if connect issue_slots[5].wakeup_ports[4].bits.uop.bp_debug_if, io.wakeup_ports[4].bits.uop.bp_debug_if connect issue_slots[5].wakeup_ports[4].bits.uop.xcpt_ma_if, io.wakeup_ports[4].bits.uop.xcpt_ma_if connect issue_slots[5].wakeup_ports[4].bits.uop.xcpt_ae_if, io.wakeup_ports[4].bits.uop.xcpt_ae_if connect issue_slots[5].wakeup_ports[4].bits.uop.xcpt_pf_if, io.wakeup_ports[4].bits.uop.xcpt_pf_if connect issue_slots[5].wakeup_ports[4].bits.uop.fp_typ, io.wakeup_ports[4].bits.uop.fp_typ connect issue_slots[5].wakeup_ports[4].bits.uop.fp_rm, io.wakeup_ports[4].bits.uop.fp_rm connect issue_slots[5].wakeup_ports[4].bits.uop.fp_val, io.wakeup_ports[4].bits.uop.fp_val connect issue_slots[5].wakeup_ports[4].bits.uop.fcn_op, io.wakeup_ports[4].bits.uop.fcn_op connect issue_slots[5].wakeup_ports[4].bits.uop.fcn_dw, io.wakeup_ports[4].bits.uop.fcn_dw connect issue_slots[5].wakeup_ports[4].bits.uop.frs3_en, io.wakeup_ports[4].bits.uop.frs3_en connect issue_slots[5].wakeup_ports[4].bits.uop.lrs2_rtype, io.wakeup_ports[4].bits.uop.lrs2_rtype connect issue_slots[5].wakeup_ports[4].bits.uop.lrs1_rtype, io.wakeup_ports[4].bits.uop.lrs1_rtype connect issue_slots[5].wakeup_ports[4].bits.uop.dst_rtype, io.wakeup_ports[4].bits.uop.dst_rtype connect issue_slots[5].wakeup_ports[4].bits.uop.lrs3, io.wakeup_ports[4].bits.uop.lrs3 connect issue_slots[5].wakeup_ports[4].bits.uop.lrs2, io.wakeup_ports[4].bits.uop.lrs2 connect issue_slots[5].wakeup_ports[4].bits.uop.lrs1, io.wakeup_ports[4].bits.uop.lrs1 connect issue_slots[5].wakeup_ports[4].bits.uop.ldst, io.wakeup_ports[4].bits.uop.ldst connect issue_slots[5].wakeup_ports[4].bits.uop.ldst_is_rs1, io.wakeup_ports[4].bits.uop.ldst_is_rs1 connect issue_slots[5].wakeup_ports[4].bits.uop.csr_cmd, io.wakeup_ports[4].bits.uop.csr_cmd connect issue_slots[5].wakeup_ports[4].bits.uop.flush_on_commit, io.wakeup_ports[4].bits.uop.flush_on_commit connect issue_slots[5].wakeup_ports[4].bits.uop.is_unique, io.wakeup_ports[4].bits.uop.is_unique connect issue_slots[5].wakeup_ports[4].bits.uop.uses_stq, io.wakeup_ports[4].bits.uop.uses_stq connect issue_slots[5].wakeup_ports[4].bits.uop.uses_ldq, io.wakeup_ports[4].bits.uop.uses_ldq connect issue_slots[5].wakeup_ports[4].bits.uop.mem_signed, io.wakeup_ports[4].bits.uop.mem_signed connect issue_slots[5].wakeup_ports[4].bits.uop.mem_size, io.wakeup_ports[4].bits.uop.mem_size connect issue_slots[5].wakeup_ports[4].bits.uop.mem_cmd, io.wakeup_ports[4].bits.uop.mem_cmd connect issue_slots[5].wakeup_ports[4].bits.uop.exc_cause, io.wakeup_ports[4].bits.uop.exc_cause connect issue_slots[5].wakeup_ports[4].bits.uop.exception, io.wakeup_ports[4].bits.uop.exception connect issue_slots[5].wakeup_ports[4].bits.uop.stale_pdst, io.wakeup_ports[4].bits.uop.stale_pdst connect issue_slots[5].wakeup_ports[4].bits.uop.ppred_busy, io.wakeup_ports[4].bits.uop.ppred_busy connect issue_slots[5].wakeup_ports[4].bits.uop.prs3_busy, io.wakeup_ports[4].bits.uop.prs3_busy connect issue_slots[5].wakeup_ports[4].bits.uop.prs2_busy, io.wakeup_ports[4].bits.uop.prs2_busy connect issue_slots[5].wakeup_ports[4].bits.uop.prs1_busy, io.wakeup_ports[4].bits.uop.prs1_busy connect issue_slots[5].wakeup_ports[4].bits.uop.ppred, io.wakeup_ports[4].bits.uop.ppred connect issue_slots[5].wakeup_ports[4].bits.uop.prs3, io.wakeup_ports[4].bits.uop.prs3 connect issue_slots[5].wakeup_ports[4].bits.uop.prs2, io.wakeup_ports[4].bits.uop.prs2 connect issue_slots[5].wakeup_ports[4].bits.uop.prs1, io.wakeup_ports[4].bits.uop.prs1 connect issue_slots[5].wakeup_ports[4].bits.uop.pdst, io.wakeup_ports[4].bits.uop.pdst connect issue_slots[5].wakeup_ports[4].bits.uop.rxq_idx, io.wakeup_ports[4].bits.uop.rxq_idx connect issue_slots[5].wakeup_ports[4].bits.uop.stq_idx, io.wakeup_ports[4].bits.uop.stq_idx connect issue_slots[5].wakeup_ports[4].bits.uop.ldq_idx, io.wakeup_ports[4].bits.uop.ldq_idx connect issue_slots[5].wakeup_ports[4].bits.uop.rob_idx, io.wakeup_ports[4].bits.uop.rob_idx connect issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.vec, io.wakeup_ports[4].bits.uop.fp_ctrl.vec connect issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.wflags, io.wakeup_ports[4].bits.uop.fp_ctrl.wflags connect issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.div, io.wakeup_ports[4].bits.uop.fp_ctrl.div connect issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.fma, io.wakeup_ports[4].bits.uop.fp_ctrl.fma connect issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.toint, io.wakeup_ports[4].bits.uop.fp_ctrl.toint connect issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.fromint, io.wakeup_ports[4].bits.uop.fp_ctrl.fromint connect issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.swap23, io.wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.swap12, io.wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.ren3, io.wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.ren2, io.wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.ren1, io.wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.wen, io.wakeup_ports[4].bits.uop.fp_ctrl.wen connect issue_slots[5].wakeup_ports[4].bits.uop.fp_ctrl.ldst, io.wakeup_ports[4].bits.uop.fp_ctrl.ldst connect issue_slots[5].wakeup_ports[4].bits.uop.op2_sel, io.wakeup_ports[4].bits.uop.op2_sel connect issue_slots[5].wakeup_ports[4].bits.uop.op1_sel, io.wakeup_ports[4].bits.uop.op1_sel connect issue_slots[5].wakeup_ports[4].bits.uop.imm_packed, io.wakeup_ports[4].bits.uop.imm_packed connect issue_slots[5].wakeup_ports[4].bits.uop.pimm, io.wakeup_ports[4].bits.uop.pimm connect issue_slots[5].wakeup_ports[4].bits.uop.imm_sel, io.wakeup_ports[4].bits.uop.imm_sel connect issue_slots[5].wakeup_ports[4].bits.uop.imm_rename, io.wakeup_ports[4].bits.uop.imm_rename connect issue_slots[5].wakeup_ports[4].bits.uop.taken, io.wakeup_ports[4].bits.uop.taken connect issue_slots[5].wakeup_ports[4].bits.uop.pc_lob, io.wakeup_ports[4].bits.uop.pc_lob connect issue_slots[5].wakeup_ports[4].bits.uop.edge_inst, io.wakeup_ports[4].bits.uop.edge_inst connect issue_slots[5].wakeup_ports[4].bits.uop.ftq_idx, io.wakeup_ports[4].bits.uop.ftq_idx connect issue_slots[5].wakeup_ports[4].bits.uop.is_mov, io.wakeup_ports[4].bits.uop.is_mov connect issue_slots[5].wakeup_ports[4].bits.uop.is_rocc, io.wakeup_ports[4].bits.uop.is_rocc connect issue_slots[5].wakeup_ports[4].bits.uop.is_sys_pc2epc, io.wakeup_ports[4].bits.uop.is_sys_pc2epc connect issue_slots[5].wakeup_ports[4].bits.uop.is_eret, io.wakeup_ports[4].bits.uop.is_eret connect issue_slots[5].wakeup_ports[4].bits.uop.is_amo, io.wakeup_ports[4].bits.uop.is_amo connect issue_slots[5].wakeup_ports[4].bits.uop.is_sfence, io.wakeup_ports[4].bits.uop.is_sfence connect issue_slots[5].wakeup_ports[4].bits.uop.is_fencei, io.wakeup_ports[4].bits.uop.is_fencei connect issue_slots[5].wakeup_ports[4].bits.uop.is_fence, io.wakeup_ports[4].bits.uop.is_fence connect issue_slots[5].wakeup_ports[4].bits.uop.is_sfb, io.wakeup_ports[4].bits.uop.is_sfb connect issue_slots[5].wakeup_ports[4].bits.uop.br_type, io.wakeup_ports[4].bits.uop.br_type connect issue_slots[5].wakeup_ports[4].bits.uop.br_tag, io.wakeup_ports[4].bits.uop.br_tag connect issue_slots[5].wakeup_ports[4].bits.uop.br_mask, io.wakeup_ports[4].bits.uop.br_mask connect issue_slots[5].wakeup_ports[4].bits.uop.dis_col_sel, io.wakeup_ports[4].bits.uop.dis_col_sel connect issue_slots[5].wakeup_ports[4].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect issue_slots[5].wakeup_ports[4].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect issue_slots[5].wakeup_ports[4].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect issue_slots[5].wakeup_ports[4].bits.uop.iw_p2_speculative_child, io.wakeup_ports[4].bits.uop.iw_p2_speculative_child connect issue_slots[5].wakeup_ports[4].bits.uop.iw_p1_speculative_child, io.wakeup_ports[4].bits.uop.iw_p1_speculative_child connect issue_slots[5].wakeup_ports[4].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect issue_slots[5].wakeup_ports[4].bits.uop.iw_issued_partial_agen, io.wakeup_ports[4].bits.uop.iw_issued_partial_agen connect issue_slots[5].wakeup_ports[4].bits.uop.iw_issued, io.wakeup_ports[4].bits.uop.iw_issued connect issue_slots[5].wakeup_ports[4].bits.uop.fu_code[0], io.wakeup_ports[4].bits.uop.fu_code[0] connect issue_slots[5].wakeup_ports[4].bits.uop.fu_code[1], io.wakeup_ports[4].bits.uop.fu_code[1] connect issue_slots[5].wakeup_ports[4].bits.uop.fu_code[2], io.wakeup_ports[4].bits.uop.fu_code[2] connect issue_slots[5].wakeup_ports[4].bits.uop.fu_code[3], io.wakeup_ports[4].bits.uop.fu_code[3] connect issue_slots[5].wakeup_ports[4].bits.uop.fu_code[4], io.wakeup_ports[4].bits.uop.fu_code[4] connect issue_slots[5].wakeup_ports[4].bits.uop.fu_code[5], io.wakeup_ports[4].bits.uop.fu_code[5] connect issue_slots[5].wakeup_ports[4].bits.uop.fu_code[6], io.wakeup_ports[4].bits.uop.fu_code[6] connect issue_slots[5].wakeup_ports[4].bits.uop.fu_code[7], io.wakeup_ports[4].bits.uop.fu_code[7] connect issue_slots[5].wakeup_ports[4].bits.uop.fu_code[8], io.wakeup_ports[4].bits.uop.fu_code[8] connect issue_slots[5].wakeup_ports[4].bits.uop.fu_code[9], io.wakeup_ports[4].bits.uop.fu_code[9] connect issue_slots[5].wakeup_ports[4].bits.uop.iq_type[0], io.wakeup_ports[4].bits.uop.iq_type[0] connect issue_slots[5].wakeup_ports[4].bits.uop.iq_type[1], io.wakeup_ports[4].bits.uop.iq_type[1] connect issue_slots[5].wakeup_ports[4].bits.uop.iq_type[2], io.wakeup_ports[4].bits.uop.iq_type[2] connect issue_slots[5].wakeup_ports[4].bits.uop.iq_type[3], io.wakeup_ports[4].bits.uop.iq_type[3] connect issue_slots[5].wakeup_ports[4].bits.uop.debug_pc, io.wakeup_ports[4].bits.uop.debug_pc connect issue_slots[5].wakeup_ports[4].bits.uop.is_rvc, io.wakeup_ports[4].bits.uop.is_rvc connect issue_slots[5].wakeup_ports[4].bits.uop.debug_inst, io.wakeup_ports[4].bits.uop.debug_inst connect issue_slots[5].wakeup_ports[4].bits.uop.inst, io.wakeup_ports[4].bits.uop.inst connect issue_slots[5].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[5].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[5].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[5].child_rebusys, io.child_rebusys connect issue_slots[5].squash_grant, io.squash_grant connect issue_slots[5].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[5].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[5].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[5].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[5].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[5].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[5].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[5].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[5].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[5].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[5].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[5].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[5].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[5].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect issue_slots[5].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect issue_slots[5].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[5].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect issue_slots[5].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect issue_slots[5].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[5].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[5].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[5].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[5].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[5].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[5].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[5].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[5].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[5].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect issue_slots[5].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[5].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[5].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[5].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[5].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[5].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[5].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[5].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[5].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[5].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[5].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[5].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[5].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[5].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[5].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[5].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[5].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[5].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[5].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[5].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[5].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[5].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[5].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[5].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect issue_slots[5].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect issue_slots[5].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect issue_slots[5].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect issue_slots[5].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect issue_slots[5].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect issue_slots[5].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect issue_slots[5].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect issue_slots[5].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect issue_slots[5].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect issue_slots[5].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect issue_slots[5].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect issue_slots[5].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect issue_slots[5].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect issue_slots[5].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect issue_slots[5].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect issue_slots[5].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect issue_slots[5].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect issue_slots[5].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect issue_slots[5].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[5].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect issue_slots[5].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect issue_slots[5].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect issue_slots[5].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[5].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[5].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[5].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[5].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect issue_slots[5].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect issue_slots[5].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[5].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect issue_slots[5].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[5].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect issue_slots[5].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[5].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[5].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[5].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect issue_slots[5].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[5].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[5].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect issue_slots[5].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect issue_slots[5].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect issue_slots[5].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect issue_slots[5].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect issue_slots[5].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect issue_slots[5].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect issue_slots[5].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect issue_slots[5].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect issue_slots[5].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect issue_slots[5].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect issue_slots[5].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect issue_slots[5].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect issue_slots[5].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect issue_slots[5].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect issue_slots[5].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect issue_slots[5].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect issue_slots[5].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect issue_slots[5].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect issue_slots[5].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect issue_slots[5].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect issue_slots[5].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect issue_slots[5].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect issue_slots[5].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[5].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[5].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[5].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[5].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[5].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[5].kill, io.flush_pipeline connect issue_slots[6].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy connect issue_slots[6].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask connect issue_slots[6].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable connect issue_slots[6].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc connect issue_slots[6].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc connect issue_slots[6].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if connect issue_slots[6].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if connect issue_slots[6].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if connect issue_slots[6].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if connect issue_slots[6].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if connect issue_slots[6].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ connect issue_slots[6].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm connect issue_slots[6].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val connect issue_slots[6].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op connect issue_slots[6].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw connect issue_slots[6].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en connect issue_slots[6].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype connect issue_slots[6].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype connect issue_slots[6].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype connect issue_slots[6].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 connect issue_slots[6].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 connect issue_slots[6].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 connect issue_slots[6].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst connect issue_slots[6].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 connect issue_slots[6].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd connect issue_slots[6].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit connect issue_slots[6].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique connect issue_slots[6].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq connect issue_slots[6].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq connect issue_slots[6].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed connect issue_slots[6].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size connect issue_slots[6].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd connect issue_slots[6].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause connect issue_slots[6].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception connect issue_slots[6].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst connect issue_slots[6].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy connect issue_slots[6].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy connect issue_slots[6].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy connect issue_slots[6].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy connect issue_slots[6].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred connect issue_slots[6].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 connect issue_slots[6].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 connect issue_slots[6].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 connect issue_slots[6].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst connect issue_slots[6].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx connect issue_slots[6].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx connect issue_slots[6].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx connect issue_slots[6].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst connect issue_slots[6].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel connect issue_slots[6].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel connect issue_slots[6].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed connect issue_slots[6].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm connect issue_slots[6].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel connect issue_slots[6].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename connect issue_slots[6].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken connect issue_slots[6].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob connect issue_slots[6].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst connect issue_slots[6].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx connect issue_slots[6].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov connect issue_slots[6].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc connect issue_slots[6].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc connect issue_slots[6].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret connect issue_slots[6].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo connect issue_slots[6].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence connect issue_slots[6].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei connect issue_slots[6].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence connect issue_slots[6].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb connect issue_slots[6].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type connect issue_slots[6].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag connect issue_slots[6].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask connect issue_slots[6].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel connect issue_slots[6].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect issue_slots[6].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect issue_slots[6].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect issue_slots[6].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child connect issue_slots[6].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child connect issue_slots[6].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect issue_slots[6].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen connect issue_slots[6].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued connect issue_slots[6].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] connect issue_slots[6].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] connect issue_slots[6].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] connect issue_slots[6].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] connect issue_slots[6].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] connect issue_slots[6].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] connect issue_slots[6].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] connect issue_slots[6].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] connect issue_slots[6].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] connect issue_slots[6].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] connect issue_slots[6].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] connect issue_slots[6].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] connect issue_slots[6].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] connect issue_slots[6].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] connect issue_slots[6].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc connect issue_slots[6].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc connect issue_slots[6].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst connect issue_slots[6].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst connect issue_slots[6].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[6].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy connect issue_slots[6].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask connect issue_slots[6].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable connect issue_slots[6].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc connect issue_slots[6].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc connect issue_slots[6].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if connect issue_slots[6].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if connect issue_slots[6].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if connect issue_slots[6].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if connect issue_slots[6].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if connect issue_slots[6].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ connect issue_slots[6].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm connect issue_slots[6].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val connect issue_slots[6].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op connect issue_slots[6].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw connect issue_slots[6].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en connect issue_slots[6].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype connect issue_slots[6].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype connect issue_slots[6].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype connect issue_slots[6].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 connect issue_slots[6].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 connect issue_slots[6].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 connect issue_slots[6].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst connect issue_slots[6].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 connect issue_slots[6].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd connect issue_slots[6].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit connect issue_slots[6].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique connect issue_slots[6].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq connect issue_slots[6].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq connect issue_slots[6].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed connect issue_slots[6].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size connect issue_slots[6].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd connect issue_slots[6].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause connect issue_slots[6].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception connect issue_slots[6].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst connect issue_slots[6].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy connect issue_slots[6].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy connect issue_slots[6].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy connect issue_slots[6].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy connect issue_slots[6].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred connect issue_slots[6].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 connect issue_slots[6].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 connect issue_slots[6].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 connect issue_slots[6].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst connect issue_slots[6].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx connect issue_slots[6].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx connect issue_slots[6].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx connect issue_slots[6].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst connect issue_slots[6].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel connect issue_slots[6].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel connect issue_slots[6].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed connect issue_slots[6].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm connect issue_slots[6].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel connect issue_slots[6].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename connect issue_slots[6].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken connect issue_slots[6].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob connect issue_slots[6].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst connect issue_slots[6].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx connect issue_slots[6].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov connect issue_slots[6].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc connect issue_slots[6].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc connect issue_slots[6].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret connect issue_slots[6].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo connect issue_slots[6].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence connect issue_slots[6].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei connect issue_slots[6].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence connect issue_slots[6].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb connect issue_slots[6].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type connect issue_slots[6].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag connect issue_slots[6].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask connect issue_slots[6].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel connect issue_slots[6].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect issue_slots[6].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect issue_slots[6].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect issue_slots[6].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child connect issue_slots[6].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child connect issue_slots[6].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect issue_slots[6].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen connect issue_slots[6].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued connect issue_slots[6].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] connect issue_slots[6].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] connect issue_slots[6].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] connect issue_slots[6].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] connect issue_slots[6].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] connect issue_slots[6].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] connect issue_slots[6].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] connect issue_slots[6].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] connect issue_slots[6].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] connect issue_slots[6].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] connect issue_slots[6].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] connect issue_slots[6].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] connect issue_slots[6].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] connect issue_slots[6].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] connect issue_slots[6].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc connect issue_slots[6].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc connect issue_slots[6].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst connect issue_slots[6].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst connect issue_slots[6].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[6].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy connect issue_slots[6].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask connect issue_slots[6].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable connect issue_slots[6].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc connect issue_slots[6].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc connect issue_slots[6].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if connect issue_slots[6].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if connect issue_slots[6].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if connect issue_slots[6].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if connect issue_slots[6].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if connect issue_slots[6].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ connect issue_slots[6].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm connect issue_slots[6].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val connect issue_slots[6].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op connect issue_slots[6].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw connect issue_slots[6].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en connect issue_slots[6].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype connect issue_slots[6].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype connect issue_slots[6].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype connect issue_slots[6].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3 connect issue_slots[6].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2 connect issue_slots[6].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1 connect issue_slots[6].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst connect issue_slots[6].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1 connect issue_slots[6].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd connect issue_slots[6].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit connect issue_slots[6].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique connect issue_slots[6].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq connect issue_slots[6].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq connect issue_slots[6].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed connect issue_slots[6].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size connect issue_slots[6].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd connect issue_slots[6].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause connect issue_slots[6].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception connect issue_slots[6].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst connect issue_slots[6].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy connect issue_slots[6].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy connect issue_slots[6].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy connect issue_slots[6].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy connect issue_slots[6].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred connect issue_slots[6].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3 connect issue_slots[6].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2 connect issue_slots[6].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1 connect issue_slots[6].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst connect issue_slots[6].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx connect issue_slots[6].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx connect issue_slots[6].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx connect issue_slots[6].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen connect issue_slots[6].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst connect issue_slots[6].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel connect issue_slots[6].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel connect issue_slots[6].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed connect issue_slots[6].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm connect issue_slots[6].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel connect issue_slots[6].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename connect issue_slots[6].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken connect issue_slots[6].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob connect issue_slots[6].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst connect issue_slots[6].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx connect issue_slots[6].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov connect issue_slots[6].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc connect issue_slots[6].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc connect issue_slots[6].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret connect issue_slots[6].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo connect issue_slots[6].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence connect issue_slots[6].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei connect issue_slots[6].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence connect issue_slots[6].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb connect issue_slots[6].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type connect issue_slots[6].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag connect issue_slots[6].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask connect issue_slots[6].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel connect issue_slots[6].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect issue_slots[6].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect issue_slots[6].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect issue_slots[6].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child connect issue_slots[6].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child connect issue_slots[6].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect issue_slots[6].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen connect issue_slots[6].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued connect issue_slots[6].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0] connect issue_slots[6].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1] connect issue_slots[6].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2] connect issue_slots[6].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3] connect issue_slots[6].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4] connect issue_slots[6].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5] connect issue_slots[6].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6] connect issue_slots[6].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7] connect issue_slots[6].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8] connect issue_slots[6].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9] connect issue_slots[6].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0] connect issue_slots[6].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1] connect issue_slots[6].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2] connect issue_slots[6].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3] connect issue_slots[6].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc connect issue_slots[6].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc connect issue_slots[6].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst connect issue_slots[6].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst connect issue_slots[6].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[6].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy connect issue_slots[6].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask connect issue_slots[6].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable connect issue_slots[6].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc connect issue_slots[6].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc connect issue_slots[6].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if connect issue_slots[6].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if connect issue_slots[6].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if connect issue_slots[6].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if connect issue_slots[6].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if connect issue_slots[6].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ connect issue_slots[6].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm connect issue_slots[6].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val connect issue_slots[6].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op connect issue_slots[6].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw connect issue_slots[6].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en connect issue_slots[6].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype connect issue_slots[6].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype connect issue_slots[6].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype connect issue_slots[6].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3 connect issue_slots[6].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2 connect issue_slots[6].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1 connect issue_slots[6].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst connect issue_slots[6].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1 connect issue_slots[6].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd connect issue_slots[6].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit connect issue_slots[6].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique connect issue_slots[6].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq connect issue_slots[6].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq connect issue_slots[6].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed connect issue_slots[6].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size connect issue_slots[6].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd connect issue_slots[6].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause connect issue_slots[6].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception connect issue_slots[6].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst connect issue_slots[6].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy connect issue_slots[6].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy connect issue_slots[6].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy connect issue_slots[6].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy connect issue_slots[6].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred connect issue_slots[6].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3 connect issue_slots[6].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2 connect issue_slots[6].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1 connect issue_slots[6].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst connect issue_slots[6].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx connect issue_slots[6].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx connect issue_slots[6].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx connect issue_slots[6].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen connect issue_slots[6].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst connect issue_slots[6].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel connect issue_slots[6].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel connect issue_slots[6].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed connect issue_slots[6].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm connect issue_slots[6].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel connect issue_slots[6].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename connect issue_slots[6].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken connect issue_slots[6].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob connect issue_slots[6].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst connect issue_slots[6].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx connect issue_slots[6].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov connect issue_slots[6].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc connect issue_slots[6].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc connect issue_slots[6].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret connect issue_slots[6].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo connect issue_slots[6].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence connect issue_slots[6].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei connect issue_slots[6].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence connect issue_slots[6].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb connect issue_slots[6].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type connect issue_slots[6].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag connect issue_slots[6].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask connect issue_slots[6].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel connect issue_slots[6].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect issue_slots[6].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect issue_slots[6].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect issue_slots[6].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child connect issue_slots[6].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child connect issue_slots[6].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect issue_slots[6].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen connect issue_slots[6].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued connect issue_slots[6].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0] connect issue_slots[6].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1] connect issue_slots[6].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2] connect issue_slots[6].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3] connect issue_slots[6].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4] connect issue_slots[6].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5] connect issue_slots[6].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6] connect issue_slots[6].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7] connect issue_slots[6].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8] connect issue_slots[6].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9] connect issue_slots[6].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0] connect issue_slots[6].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1] connect issue_slots[6].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2] connect issue_slots[6].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3] connect issue_slots[6].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc connect issue_slots[6].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc connect issue_slots[6].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst connect issue_slots[6].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst connect issue_slots[6].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[6].wakeup_ports[4].bits.rebusy, io.wakeup_ports[4].bits.rebusy connect issue_slots[6].wakeup_ports[4].bits.speculative_mask, io.wakeup_ports[4].bits.speculative_mask connect issue_slots[6].wakeup_ports[4].bits.bypassable, io.wakeup_ports[4].bits.bypassable connect issue_slots[6].wakeup_ports[4].bits.uop.debug_tsrc, io.wakeup_ports[4].bits.uop.debug_tsrc connect issue_slots[6].wakeup_ports[4].bits.uop.debug_fsrc, io.wakeup_ports[4].bits.uop.debug_fsrc connect issue_slots[6].wakeup_ports[4].bits.uop.bp_xcpt_if, io.wakeup_ports[4].bits.uop.bp_xcpt_if connect issue_slots[6].wakeup_ports[4].bits.uop.bp_debug_if, io.wakeup_ports[4].bits.uop.bp_debug_if connect issue_slots[6].wakeup_ports[4].bits.uop.xcpt_ma_if, io.wakeup_ports[4].bits.uop.xcpt_ma_if connect issue_slots[6].wakeup_ports[4].bits.uop.xcpt_ae_if, io.wakeup_ports[4].bits.uop.xcpt_ae_if connect issue_slots[6].wakeup_ports[4].bits.uop.xcpt_pf_if, io.wakeup_ports[4].bits.uop.xcpt_pf_if connect issue_slots[6].wakeup_ports[4].bits.uop.fp_typ, io.wakeup_ports[4].bits.uop.fp_typ connect issue_slots[6].wakeup_ports[4].bits.uop.fp_rm, io.wakeup_ports[4].bits.uop.fp_rm connect issue_slots[6].wakeup_ports[4].bits.uop.fp_val, io.wakeup_ports[4].bits.uop.fp_val connect issue_slots[6].wakeup_ports[4].bits.uop.fcn_op, io.wakeup_ports[4].bits.uop.fcn_op connect issue_slots[6].wakeup_ports[4].bits.uop.fcn_dw, io.wakeup_ports[4].bits.uop.fcn_dw connect issue_slots[6].wakeup_ports[4].bits.uop.frs3_en, io.wakeup_ports[4].bits.uop.frs3_en connect issue_slots[6].wakeup_ports[4].bits.uop.lrs2_rtype, io.wakeup_ports[4].bits.uop.lrs2_rtype connect issue_slots[6].wakeup_ports[4].bits.uop.lrs1_rtype, io.wakeup_ports[4].bits.uop.lrs1_rtype connect issue_slots[6].wakeup_ports[4].bits.uop.dst_rtype, io.wakeup_ports[4].bits.uop.dst_rtype connect issue_slots[6].wakeup_ports[4].bits.uop.lrs3, io.wakeup_ports[4].bits.uop.lrs3 connect issue_slots[6].wakeup_ports[4].bits.uop.lrs2, io.wakeup_ports[4].bits.uop.lrs2 connect issue_slots[6].wakeup_ports[4].bits.uop.lrs1, io.wakeup_ports[4].bits.uop.lrs1 connect issue_slots[6].wakeup_ports[4].bits.uop.ldst, io.wakeup_ports[4].bits.uop.ldst connect issue_slots[6].wakeup_ports[4].bits.uop.ldst_is_rs1, io.wakeup_ports[4].bits.uop.ldst_is_rs1 connect issue_slots[6].wakeup_ports[4].bits.uop.csr_cmd, io.wakeup_ports[4].bits.uop.csr_cmd connect issue_slots[6].wakeup_ports[4].bits.uop.flush_on_commit, io.wakeup_ports[4].bits.uop.flush_on_commit connect issue_slots[6].wakeup_ports[4].bits.uop.is_unique, io.wakeup_ports[4].bits.uop.is_unique connect issue_slots[6].wakeup_ports[4].bits.uop.uses_stq, io.wakeup_ports[4].bits.uop.uses_stq connect issue_slots[6].wakeup_ports[4].bits.uop.uses_ldq, io.wakeup_ports[4].bits.uop.uses_ldq connect issue_slots[6].wakeup_ports[4].bits.uop.mem_signed, io.wakeup_ports[4].bits.uop.mem_signed connect issue_slots[6].wakeup_ports[4].bits.uop.mem_size, io.wakeup_ports[4].bits.uop.mem_size connect issue_slots[6].wakeup_ports[4].bits.uop.mem_cmd, io.wakeup_ports[4].bits.uop.mem_cmd connect issue_slots[6].wakeup_ports[4].bits.uop.exc_cause, io.wakeup_ports[4].bits.uop.exc_cause connect issue_slots[6].wakeup_ports[4].bits.uop.exception, io.wakeup_ports[4].bits.uop.exception connect issue_slots[6].wakeup_ports[4].bits.uop.stale_pdst, io.wakeup_ports[4].bits.uop.stale_pdst connect issue_slots[6].wakeup_ports[4].bits.uop.ppred_busy, io.wakeup_ports[4].bits.uop.ppred_busy connect issue_slots[6].wakeup_ports[4].bits.uop.prs3_busy, io.wakeup_ports[4].bits.uop.prs3_busy connect issue_slots[6].wakeup_ports[4].bits.uop.prs2_busy, io.wakeup_ports[4].bits.uop.prs2_busy connect issue_slots[6].wakeup_ports[4].bits.uop.prs1_busy, io.wakeup_ports[4].bits.uop.prs1_busy connect issue_slots[6].wakeup_ports[4].bits.uop.ppred, io.wakeup_ports[4].bits.uop.ppred connect issue_slots[6].wakeup_ports[4].bits.uop.prs3, io.wakeup_ports[4].bits.uop.prs3 connect issue_slots[6].wakeup_ports[4].bits.uop.prs2, io.wakeup_ports[4].bits.uop.prs2 connect issue_slots[6].wakeup_ports[4].bits.uop.prs1, io.wakeup_ports[4].bits.uop.prs1 connect issue_slots[6].wakeup_ports[4].bits.uop.pdst, io.wakeup_ports[4].bits.uop.pdst connect issue_slots[6].wakeup_ports[4].bits.uop.rxq_idx, io.wakeup_ports[4].bits.uop.rxq_idx connect issue_slots[6].wakeup_ports[4].bits.uop.stq_idx, io.wakeup_ports[4].bits.uop.stq_idx connect issue_slots[6].wakeup_ports[4].bits.uop.ldq_idx, io.wakeup_ports[4].bits.uop.ldq_idx connect issue_slots[6].wakeup_ports[4].bits.uop.rob_idx, io.wakeup_ports[4].bits.uop.rob_idx connect issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.vec, io.wakeup_ports[4].bits.uop.fp_ctrl.vec connect issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.wflags, io.wakeup_ports[4].bits.uop.fp_ctrl.wflags connect issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.div, io.wakeup_ports[4].bits.uop.fp_ctrl.div connect issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.fma, io.wakeup_ports[4].bits.uop.fp_ctrl.fma connect issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.toint, io.wakeup_ports[4].bits.uop.fp_ctrl.toint connect issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.fromint, io.wakeup_ports[4].bits.uop.fp_ctrl.fromint connect issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.swap23, io.wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.swap12, io.wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.ren3, io.wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.ren2, io.wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.ren1, io.wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.wen, io.wakeup_ports[4].bits.uop.fp_ctrl.wen connect issue_slots[6].wakeup_ports[4].bits.uop.fp_ctrl.ldst, io.wakeup_ports[4].bits.uop.fp_ctrl.ldst connect issue_slots[6].wakeup_ports[4].bits.uop.op2_sel, io.wakeup_ports[4].bits.uop.op2_sel connect issue_slots[6].wakeup_ports[4].bits.uop.op1_sel, io.wakeup_ports[4].bits.uop.op1_sel connect issue_slots[6].wakeup_ports[4].bits.uop.imm_packed, io.wakeup_ports[4].bits.uop.imm_packed connect issue_slots[6].wakeup_ports[4].bits.uop.pimm, io.wakeup_ports[4].bits.uop.pimm connect issue_slots[6].wakeup_ports[4].bits.uop.imm_sel, io.wakeup_ports[4].bits.uop.imm_sel connect issue_slots[6].wakeup_ports[4].bits.uop.imm_rename, io.wakeup_ports[4].bits.uop.imm_rename connect issue_slots[6].wakeup_ports[4].bits.uop.taken, io.wakeup_ports[4].bits.uop.taken connect issue_slots[6].wakeup_ports[4].bits.uop.pc_lob, io.wakeup_ports[4].bits.uop.pc_lob connect issue_slots[6].wakeup_ports[4].bits.uop.edge_inst, io.wakeup_ports[4].bits.uop.edge_inst connect issue_slots[6].wakeup_ports[4].bits.uop.ftq_idx, io.wakeup_ports[4].bits.uop.ftq_idx connect issue_slots[6].wakeup_ports[4].bits.uop.is_mov, io.wakeup_ports[4].bits.uop.is_mov connect issue_slots[6].wakeup_ports[4].bits.uop.is_rocc, io.wakeup_ports[4].bits.uop.is_rocc connect issue_slots[6].wakeup_ports[4].bits.uop.is_sys_pc2epc, io.wakeup_ports[4].bits.uop.is_sys_pc2epc connect issue_slots[6].wakeup_ports[4].bits.uop.is_eret, io.wakeup_ports[4].bits.uop.is_eret connect issue_slots[6].wakeup_ports[4].bits.uop.is_amo, io.wakeup_ports[4].bits.uop.is_amo connect issue_slots[6].wakeup_ports[4].bits.uop.is_sfence, io.wakeup_ports[4].bits.uop.is_sfence connect issue_slots[6].wakeup_ports[4].bits.uop.is_fencei, io.wakeup_ports[4].bits.uop.is_fencei connect issue_slots[6].wakeup_ports[4].bits.uop.is_fence, io.wakeup_ports[4].bits.uop.is_fence connect issue_slots[6].wakeup_ports[4].bits.uop.is_sfb, io.wakeup_ports[4].bits.uop.is_sfb connect issue_slots[6].wakeup_ports[4].bits.uop.br_type, io.wakeup_ports[4].bits.uop.br_type connect issue_slots[6].wakeup_ports[4].bits.uop.br_tag, io.wakeup_ports[4].bits.uop.br_tag connect issue_slots[6].wakeup_ports[4].bits.uop.br_mask, io.wakeup_ports[4].bits.uop.br_mask connect issue_slots[6].wakeup_ports[4].bits.uop.dis_col_sel, io.wakeup_ports[4].bits.uop.dis_col_sel connect issue_slots[6].wakeup_ports[4].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect issue_slots[6].wakeup_ports[4].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect issue_slots[6].wakeup_ports[4].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect issue_slots[6].wakeup_ports[4].bits.uop.iw_p2_speculative_child, io.wakeup_ports[4].bits.uop.iw_p2_speculative_child connect issue_slots[6].wakeup_ports[4].bits.uop.iw_p1_speculative_child, io.wakeup_ports[4].bits.uop.iw_p1_speculative_child connect issue_slots[6].wakeup_ports[4].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect issue_slots[6].wakeup_ports[4].bits.uop.iw_issued_partial_agen, io.wakeup_ports[4].bits.uop.iw_issued_partial_agen connect issue_slots[6].wakeup_ports[4].bits.uop.iw_issued, io.wakeup_ports[4].bits.uop.iw_issued connect issue_slots[6].wakeup_ports[4].bits.uop.fu_code[0], io.wakeup_ports[4].bits.uop.fu_code[0] connect issue_slots[6].wakeup_ports[4].bits.uop.fu_code[1], io.wakeup_ports[4].bits.uop.fu_code[1] connect issue_slots[6].wakeup_ports[4].bits.uop.fu_code[2], io.wakeup_ports[4].bits.uop.fu_code[2] connect issue_slots[6].wakeup_ports[4].bits.uop.fu_code[3], io.wakeup_ports[4].bits.uop.fu_code[3] connect issue_slots[6].wakeup_ports[4].bits.uop.fu_code[4], io.wakeup_ports[4].bits.uop.fu_code[4] connect issue_slots[6].wakeup_ports[4].bits.uop.fu_code[5], io.wakeup_ports[4].bits.uop.fu_code[5] connect issue_slots[6].wakeup_ports[4].bits.uop.fu_code[6], io.wakeup_ports[4].bits.uop.fu_code[6] connect issue_slots[6].wakeup_ports[4].bits.uop.fu_code[7], io.wakeup_ports[4].bits.uop.fu_code[7] connect issue_slots[6].wakeup_ports[4].bits.uop.fu_code[8], io.wakeup_ports[4].bits.uop.fu_code[8] connect issue_slots[6].wakeup_ports[4].bits.uop.fu_code[9], io.wakeup_ports[4].bits.uop.fu_code[9] connect issue_slots[6].wakeup_ports[4].bits.uop.iq_type[0], io.wakeup_ports[4].bits.uop.iq_type[0] connect issue_slots[6].wakeup_ports[4].bits.uop.iq_type[1], io.wakeup_ports[4].bits.uop.iq_type[1] connect issue_slots[6].wakeup_ports[4].bits.uop.iq_type[2], io.wakeup_ports[4].bits.uop.iq_type[2] connect issue_slots[6].wakeup_ports[4].bits.uop.iq_type[3], io.wakeup_ports[4].bits.uop.iq_type[3] connect issue_slots[6].wakeup_ports[4].bits.uop.debug_pc, io.wakeup_ports[4].bits.uop.debug_pc connect issue_slots[6].wakeup_ports[4].bits.uop.is_rvc, io.wakeup_ports[4].bits.uop.is_rvc connect issue_slots[6].wakeup_ports[4].bits.uop.debug_inst, io.wakeup_ports[4].bits.uop.debug_inst connect issue_slots[6].wakeup_ports[4].bits.uop.inst, io.wakeup_ports[4].bits.uop.inst connect issue_slots[6].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[6].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[6].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[6].child_rebusys, io.child_rebusys connect issue_slots[6].squash_grant, io.squash_grant connect issue_slots[6].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[6].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[6].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[6].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[6].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[6].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[6].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[6].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[6].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[6].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[6].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[6].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[6].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[6].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect issue_slots[6].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect issue_slots[6].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[6].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect issue_slots[6].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect issue_slots[6].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[6].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[6].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[6].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[6].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[6].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[6].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[6].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[6].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[6].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect issue_slots[6].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[6].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[6].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[6].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[6].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[6].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[6].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[6].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[6].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[6].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[6].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[6].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[6].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[6].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[6].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[6].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[6].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[6].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[6].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[6].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[6].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[6].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[6].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[6].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect issue_slots[6].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect issue_slots[6].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect issue_slots[6].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect issue_slots[6].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect issue_slots[6].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect issue_slots[6].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect issue_slots[6].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect issue_slots[6].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect issue_slots[6].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect issue_slots[6].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect issue_slots[6].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect issue_slots[6].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect issue_slots[6].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect issue_slots[6].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect issue_slots[6].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect issue_slots[6].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect issue_slots[6].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect issue_slots[6].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect issue_slots[6].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[6].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect issue_slots[6].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect issue_slots[6].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect issue_slots[6].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[6].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[6].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[6].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[6].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect issue_slots[6].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect issue_slots[6].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[6].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect issue_slots[6].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[6].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect issue_slots[6].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[6].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[6].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[6].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect issue_slots[6].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[6].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[6].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect issue_slots[6].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect issue_slots[6].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect issue_slots[6].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect issue_slots[6].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect issue_slots[6].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect issue_slots[6].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect issue_slots[6].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect issue_slots[6].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect issue_slots[6].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect issue_slots[6].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect issue_slots[6].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect issue_slots[6].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect issue_slots[6].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect issue_slots[6].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect issue_slots[6].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect issue_slots[6].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect issue_slots[6].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect issue_slots[6].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect issue_slots[6].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect issue_slots[6].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect issue_slots[6].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect issue_slots[6].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect issue_slots[6].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[6].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[6].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[6].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[6].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[6].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[6].kill, io.flush_pipeline connect issue_slots[7].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy connect issue_slots[7].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask connect issue_slots[7].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable connect issue_slots[7].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc connect issue_slots[7].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc connect issue_slots[7].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if connect issue_slots[7].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if connect issue_slots[7].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if connect issue_slots[7].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if connect issue_slots[7].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if connect issue_slots[7].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ connect issue_slots[7].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm connect issue_slots[7].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val connect issue_slots[7].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op connect issue_slots[7].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw connect issue_slots[7].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en connect issue_slots[7].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype connect issue_slots[7].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype connect issue_slots[7].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype connect issue_slots[7].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 connect issue_slots[7].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 connect issue_slots[7].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 connect issue_slots[7].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst connect issue_slots[7].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 connect issue_slots[7].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd connect issue_slots[7].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit connect issue_slots[7].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique connect issue_slots[7].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq connect issue_slots[7].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq connect issue_slots[7].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed connect issue_slots[7].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size connect issue_slots[7].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd connect issue_slots[7].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause connect issue_slots[7].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception connect issue_slots[7].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst connect issue_slots[7].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy connect issue_slots[7].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy connect issue_slots[7].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy connect issue_slots[7].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy connect issue_slots[7].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred connect issue_slots[7].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 connect issue_slots[7].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 connect issue_slots[7].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 connect issue_slots[7].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst connect issue_slots[7].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx connect issue_slots[7].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx connect issue_slots[7].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx connect issue_slots[7].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst connect issue_slots[7].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel connect issue_slots[7].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel connect issue_slots[7].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed connect issue_slots[7].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm connect issue_slots[7].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel connect issue_slots[7].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename connect issue_slots[7].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken connect issue_slots[7].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob connect issue_slots[7].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst connect issue_slots[7].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx connect issue_slots[7].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov connect issue_slots[7].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc connect issue_slots[7].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc connect issue_slots[7].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret connect issue_slots[7].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo connect issue_slots[7].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence connect issue_slots[7].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei connect issue_slots[7].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence connect issue_slots[7].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb connect issue_slots[7].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type connect issue_slots[7].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag connect issue_slots[7].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask connect issue_slots[7].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel connect issue_slots[7].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect issue_slots[7].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect issue_slots[7].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect issue_slots[7].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child connect issue_slots[7].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child connect issue_slots[7].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect issue_slots[7].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen connect issue_slots[7].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued connect issue_slots[7].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] connect issue_slots[7].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] connect issue_slots[7].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] connect issue_slots[7].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] connect issue_slots[7].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] connect issue_slots[7].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] connect issue_slots[7].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] connect issue_slots[7].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] connect issue_slots[7].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] connect issue_slots[7].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] connect issue_slots[7].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] connect issue_slots[7].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] connect issue_slots[7].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] connect issue_slots[7].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] connect issue_slots[7].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc connect issue_slots[7].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc connect issue_slots[7].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst connect issue_slots[7].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst connect issue_slots[7].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[7].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy connect issue_slots[7].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask connect issue_slots[7].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable connect issue_slots[7].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc connect issue_slots[7].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc connect issue_slots[7].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if connect issue_slots[7].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if connect issue_slots[7].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if connect issue_slots[7].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if connect issue_slots[7].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if connect issue_slots[7].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ connect issue_slots[7].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm connect issue_slots[7].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val connect issue_slots[7].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op connect issue_slots[7].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw connect issue_slots[7].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en connect issue_slots[7].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype connect issue_slots[7].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype connect issue_slots[7].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype connect issue_slots[7].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 connect issue_slots[7].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 connect issue_slots[7].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 connect issue_slots[7].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst connect issue_slots[7].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 connect issue_slots[7].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd connect issue_slots[7].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit connect issue_slots[7].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique connect issue_slots[7].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq connect issue_slots[7].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq connect issue_slots[7].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed connect issue_slots[7].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size connect issue_slots[7].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd connect issue_slots[7].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause connect issue_slots[7].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception connect issue_slots[7].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst connect issue_slots[7].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy connect issue_slots[7].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy connect issue_slots[7].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy connect issue_slots[7].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy connect issue_slots[7].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred connect issue_slots[7].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 connect issue_slots[7].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 connect issue_slots[7].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 connect issue_slots[7].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst connect issue_slots[7].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx connect issue_slots[7].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx connect issue_slots[7].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx connect issue_slots[7].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst connect issue_slots[7].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel connect issue_slots[7].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel connect issue_slots[7].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed connect issue_slots[7].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm connect issue_slots[7].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel connect issue_slots[7].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename connect issue_slots[7].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken connect issue_slots[7].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob connect issue_slots[7].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst connect issue_slots[7].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx connect issue_slots[7].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov connect issue_slots[7].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc connect issue_slots[7].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc connect issue_slots[7].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret connect issue_slots[7].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo connect issue_slots[7].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence connect issue_slots[7].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei connect issue_slots[7].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence connect issue_slots[7].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb connect issue_slots[7].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type connect issue_slots[7].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag connect issue_slots[7].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask connect issue_slots[7].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel connect issue_slots[7].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect issue_slots[7].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect issue_slots[7].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect issue_slots[7].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child connect issue_slots[7].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child connect issue_slots[7].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect issue_slots[7].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen connect issue_slots[7].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued connect issue_slots[7].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] connect issue_slots[7].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] connect issue_slots[7].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] connect issue_slots[7].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] connect issue_slots[7].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] connect issue_slots[7].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] connect issue_slots[7].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] connect issue_slots[7].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] connect issue_slots[7].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] connect issue_slots[7].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] connect issue_slots[7].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] connect issue_slots[7].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] connect issue_slots[7].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] connect issue_slots[7].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] connect issue_slots[7].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc connect issue_slots[7].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc connect issue_slots[7].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst connect issue_slots[7].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst connect issue_slots[7].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[7].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy connect issue_slots[7].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask connect issue_slots[7].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable connect issue_slots[7].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc connect issue_slots[7].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc connect issue_slots[7].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if connect issue_slots[7].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if connect issue_slots[7].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if connect issue_slots[7].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if connect issue_slots[7].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if connect issue_slots[7].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ connect issue_slots[7].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm connect issue_slots[7].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val connect issue_slots[7].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op connect issue_slots[7].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw connect issue_slots[7].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en connect issue_slots[7].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype connect issue_slots[7].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype connect issue_slots[7].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype connect issue_slots[7].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3 connect issue_slots[7].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2 connect issue_slots[7].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1 connect issue_slots[7].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst connect issue_slots[7].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1 connect issue_slots[7].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd connect issue_slots[7].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit connect issue_slots[7].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique connect issue_slots[7].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq connect issue_slots[7].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq connect issue_slots[7].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed connect issue_slots[7].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size connect issue_slots[7].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd connect issue_slots[7].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause connect issue_slots[7].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception connect issue_slots[7].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst connect issue_slots[7].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy connect issue_slots[7].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy connect issue_slots[7].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy connect issue_slots[7].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy connect issue_slots[7].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred connect issue_slots[7].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3 connect issue_slots[7].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2 connect issue_slots[7].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1 connect issue_slots[7].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst connect issue_slots[7].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx connect issue_slots[7].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx connect issue_slots[7].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx connect issue_slots[7].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen connect issue_slots[7].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst connect issue_slots[7].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel connect issue_slots[7].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel connect issue_slots[7].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed connect issue_slots[7].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm connect issue_slots[7].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel connect issue_slots[7].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename connect issue_slots[7].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken connect issue_slots[7].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob connect issue_slots[7].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst connect issue_slots[7].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx connect issue_slots[7].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov connect issue_slots[7].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc connect issue_slots[7].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc connect issue_slots[7].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret connect issue_slots[7].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo connect issue_slots[7].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence connect issue_slots[7].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei connect issue_slots[7].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence connect issue_slots[7].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb connect issue_slots[7].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type connect issue_slots[7].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag connect issue_slots[7].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask connect issue_slots[7].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel connect issue_slots[7].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect issue_slots[7].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect issue_slots[7].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect issue_slots[7].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child connect issue_slots[7].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child connect issue_slots[7].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect issue_slots[7].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen connect issue_slots[7].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued connect issue_slots[7].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0] connect issue_slots[7].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1] connect issue_slots[7].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2] connect issue_slots[7].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3] connect issue_slots[7].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4] connect issue_slots[7].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5] connect issue_slots[7].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6] connect issue_slots[7].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7] connect issue_slots[7].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8] connect issue_slots[7].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9] connect issue_slots[7].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0] connect issue_slots[7].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1] connect issue_slots[7].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2] connect issue_slots[7].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3] connect issue_slots[7].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc connect issue_slots[7].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc connect issue_slots[7].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst connect issue_slots[7].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst connect issue_slots[7].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[7].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy connect issue_slots[7].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask connect issue_slots[7].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable connect issue_slots[7].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc connect issue_slots[7].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc connect issue_slots[7].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if connect issue_slots[7].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if connect issue_slots[7].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if connect issue_slots[7].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if connect issue_slots[7].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if connect issue_slots[7].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ connect issue_slots[7].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm connect issue_slots[7].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val connect issue_slots[7].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op connect issue_slots[7].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw connect issue_slots[7].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en connect issue_slots[7].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype connect issue_slots[7].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype connect issue_slots[7].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype connect issue_slots[7].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3 connect issue_slots[7].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2 connect issue_slots[7].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1 connect issue_slots[7].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst connect issue_slots[7].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1 connect issue_slots[7].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd connect issue_slots[7].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit connect issue_slots[7].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique connect issue_slots[7].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq connect issue_slots[7].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq connect issue_slots[7].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed connect issue_slots[7].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size connect issue_slots[7].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd connect issue_slots[7].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause connect issue_slots[7].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception connect issue_slots[7].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst connect issue_slots[7].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy connect issue_slots[7].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy connect issue_slots[7].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy connect issue_slots[7].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy connect issue_slots[7].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred connect issue_slots[7].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3 connect issue_slots[7].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2 connect issue_slots[7].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1 connect issue_slots[7].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst connect issue_slots[7].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx connect issue_slots[7].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx connect issue_slots[7].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx connect issue_slots[7].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen connect issue_slots[7].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst connect issue_slots[7].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel connect issue_slots[7].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel connect issue_slots[7].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed connect issue_slots[7].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm connect issue_slots[7].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel connect issue_slots[7].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename connect issue_slots[7].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken connect issue_slots[7].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob connect issue_slots[7].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst connect issue_slots[7].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx connect issue_slots[7].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov connect issue_slots[7].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc connect issue_slots[7].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc connect issue_slots[7].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret connect issue_slots[7].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo connect issue_slots[7].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence connect issue_slots[7].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei connect issue_slots[7].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence connect issue_slots[7].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb connect issue_slots[7].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type connect issue_slots[7].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag connect issue_slots[7].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask connect issue_slots[7].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel connect issue_slots[7].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect issue_slots[7].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect issue_slots[7].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect issue_slots[7].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child connect issue_slots[7].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child connect issue_slots[7].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect issue_slots[7].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen connect issue_slots[7].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued connect issue_slots[7].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0] connect issue_slots[7].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1] connect issue_slots[7].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2] connect issue_slots[7].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3] connect issue_slots[7].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4] connect issue_slots[7].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5] connect issue_slots[7].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6] connect issue_slots[7].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7] connect issue_slots[7].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8] connect issue_slots[7].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9] connect issue_slots[7].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0] connect issue_slots[7].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1] connect issue_slots[7].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2] connect issue_slots[7].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3] connect issue_slots[7].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc connect issue_slots[7].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc connect issue_slots[7].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst connect issue_slots[7].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst connect issue_slots[7].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[7].wakeup_ports[4].bits.rebusy, io.wakeup_ports[4].bits.rebusy connect issue_slots[7].wakeup_ports[4].bits.speculative_mask, io.wakeup_ports[4].bits.speculative_mask connect issue_slots[7].wakeup_ports[4].bits.bypassable, io.wakeup_ports[4].bits.bypassable connect issue_slots[7].wakeup_ports[4].bits.uop.debug_tsrc, io.wakeup_ports[4].bits.uop.debug_tsrc connect issue_slots[7].wakeup_ports[4].bits.uop.debug_fsrc, io.wakeup_ports[4].bits.uop.debug_fsrc connect issue_slots[7].wakeup_ports[4].bits.uop.bp_xcpt_if, io.wakeup_ports[4].bits.uop.bp_xcpt_if connect issue_slots[7].wakeup_ports[4].bits.uop.bp_debug_if, io.wakeup_ports[4].bits.uop.bp_debug_if connect issue_slots[7].wakeup_ports[4].bits.uop.xcpt_ma_if, io.wakeup_ports[4].bits.uop.xcpt_ma_if connect issue_slots[7].wakeup_ports[4].bits.uop.xcpt_ae_if, io.wakeup_ports[4].bits.uop.xcpt_ae_if connect issue_slots[7].wakeup_ports[4].bits.uop.xcpt_pf_if, io.wakeup_ports[4].bits.uop.xcpt_pf_if connect issue_slots[7].wakeup_ports[4].bits.uop.fp_typ, io.wakeup_ports[4].bits.uop.fp_typ connect issue_slots[7].wakeup_ports[4].bits.uop.fp_rm, io.wakeup_ports[4].bits.uop.fp_rm connect issue_slots[7].wakeup_ports[4].bits.uop.fp_val, io.wakeup_ports[4].bits.uop.fp_val connect issue_slots[7].wakeup_ports[4].bits.uop.fcn_op, io.wakeup_ports[4].bits.uop.fcn_op connect issue_slots[7].wakeup_ports[4].bits.uop.fcn_dw, io.wakeup_ports[4].bits.uop.fcn_dw connect issue_slots[7].wakeup_ports[4].bits.uop.frs3_en, io.wakeup_ports[4].bits.uop.frs3_en connect issue_slots[7].wakeup_ports[4].bits.uop.lrs2_rtype, io.wakeup_ports[4].bits.uop.lrs2_rtype connect issue_slots[7].wakeup_ports[4].bits.uop.lrs1_rtype, io.wakeup_ports[4].bits.uop.lrs1_rtype connect issue_slots[7].wakeup_ports[4].bits.uop.dst_rtype, io.wakeup_ports[4].bits.uop.dst_rtype connect issue_slots[7].wakeup_ports[4].bits.uop.lrs3, io.wakeup_ports[4].bits.uop.lrs3 connect issue_slots[7].wakeup_ports[4].bits.uop.lrs2, io.wakeup_ports[4].bits.uop.lrs2 connect issue_slots[7].wakeup_ports[4].bits.uop.lrs1, io.wakeup_ports[4].bits.uop.lrs1 connect issue_slots[7].wakeup_ports[4].bits.uop.ldst, io.wakeup_ports[4].bits.uop.ldst connect issue_slots[7].wakeup_ports[4].bits.uop.ldst_is_rs1, io.wakeup_ports[4].bits.uop.ldst_is_rs1 connect issue_slots[7].wakeup_ports[4].bits.uop.csr_cmd, io.wakeup_ports[4].bits.uop.csr_cmd connect issue_slots[7].wakeup_ports[4].bits.uop.flush_on_commit, io.wakeup_ports[4].bits.uop.flush_on_commit connect issue_slots[7].wakeup_ports[4].bits.uop.is_unique, io.wakeup_ports[4].bits.uop.is_unique connect issue_slots[7].wakeup_ports[4].bits.uop.uses_stq, io.wakeup_ports[4].bits.uop.uses_stq connect issue_slots[7].wakeup_ports[4].bits.uop.uses_ldq, io.wakeup_ports[4].bits.uop.uses_ldq connect issue_slots[7].wakeup_ports[4].bits.uop.mem_signed, io.wakeup_ports[4].bits.uop.mem_signed connect issue_slots[7].wakeup_ports[4].bits.uop.mem_size, io.wakeup_ports[4].bits.uop.mem_size connect issue_slots[7].wakeup_ports[4].bits.uop.mem_cmd, io.wakeup_ports[4].bits.uop.mem_cmd connect issue_slots[7].wakeup_ports[4].bits.uop.exc_cause, io.wakeup_ports[4].bits.uop.exc_cause connect issue_slots[7].wakeup_ports[4].bits.uop.exception, io.wakeup_ports[4].bits.uop.exception connect issue_slots[7].wakeup_ports[4].bits.uop.stale_pdst, io.wakeup_ports[4].bits.uop.stale_pdst connect issue_slots[7].wakeup_ports[4].bits.uop.ppred_busy, io.wakeup_ports[4].bits.uop.ppred_busy connect issue_slots[7].wakeup_ports[4].bits.uop.prs3_busy, io.wakeup_ports[4].bits.uop.prs3_busy connect issue_slots[7].wakeup_ports[4].bits.uop.prs2_busy, io.wakeup_ports[4].bits.uop.prs2_busy connect issue_slots[7].wakeup_ports[4].bits.uop.prs1_busy, io.wakeup_ports[4].bits.uop.prs1_busy connect issue_slots[7].wakeup_ports[4].bits.uop.ppred, io.wakeup_ports[4].bits.uop.ppred connect issue_slots[7].wakeup_ports[4].bits.uop.prs3, io.wakeup_ports[4].bits.uop.prs3 connect issue_slots[7].wakeup_ports[4].bits.uop.prs2, io.wakeup_ports[4].bits.uop.prs2 connect issue_slots[7].wakeup_ports[4].bits.uop.prs1, io.wakeup_ports[4].bits.uop.prs1 connect issue_slots[7].wakeup_ports[4].bits.uop.pdst, io.wakeup_ports[4].bits.uop.pdst connect issue_slots[7].wakeup_ports[4].bits.uop.rxq_idx, io.wakeup_ports[4].bits.uop.rxq_idx connect issue_slots[7].wakeup_ports[4].bits.uop.stq_idx, io.wakeup_ports[4].bits.uop.stq_idx connect issue_slots[7].wakeup_ports[4].bits.uop.ldq_idx, io.wakeup_ports[4].bits.uop.ldq_idx connect issue_slots[7].wakeup_ports[4].bits.uop.rob_idx, io.wakeup_ports[4].bits.uop.rob_idx connect issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.vec, io.wakeup_ports[4].bits.uop.fp_ctrl.vec connect issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.wflags, io.wakeup_ports[4].bits.uop.fp_ctrl.wflags connect issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.div, io.wakeup_ports[4].bits.uop.fp_ctrl.div connect issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.fma, io.wakeup_ports[4].bits.uop.fp_ctrl.fma connect issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.toint, io.wakeup_ports[4].bits.uop.fp_ctrl.toint connect issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.fromint, io.wakeup_ports[4].bits.uop.fp_ctrl.fromint connect issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.swap23, io.wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.swap12, io.wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.ren3, io.wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.ren2, io.wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.ren1, io.wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.wen, io.wakeup_ports[4].bits.uop.fp_ctrl.wen connect issue_slots[7].wakeup_ports[4].bits.uop.fp_ctrl.ldst, io.wakeup_ports[4].bits.uop.fp_ctrl.ldst connect issue_slots[7].wakeup_ports[4].bits.uop.op2_sel, io.wakeup_ports[4].bits.uop.op2_sel connect issue_slots[7].wakeup_ports[4].bits.uop.op1_sel, io.wakeup_ports[4].bits.uop.op1_sel connect issue_slots[7].wakeup_ports[4].bits.uop.imm_packed, io.wakeup_ports[4].bits.uop.imm_packed connect issue_slots[7].wakeup_ports[4].bits.uop.pimm, io.wakeup_ports[4].bits.uop.pimm connect issue_slots[7].wakeup_ports[4].bits.uop.imm_sel, io.wakeup_ports[4].bits.uop.imm_sel connect issue_slots[7].wakeup_ports[4].bits.uop.imm_rename, io.wakeup_ports[4].bits.uop.imm_rename connect issue_slots[7].wakeup_ports[4].bits.uop.taken, io.wakeup_ports[4].bits.uop.taken connect issue_slots[7].wakeup_ports[4].bits.uop.pc_lob, io.wakeup_ports[4].bits.uop.pc_lob connect issue_slots[7].wakeup_ports[4].bits.uop.edge_inst, io.wakeup_ports[4].bits.uop.edge_inst connect issue_slots[7].wakeup_ports[4].bits.uop.ftq_idx, io.wakeup_ports[4].bits.uop.ftq_idx connect issue_slots[7].wakeup_ports[4].bits.uop.is_mov, io.wakeup_ports[4].bits.uop.is_mov connect issue_slots[7].wakeup_ports[4].bits.uop.is_rocc, io.wakeup_ports[4].bits.uop.is_rocc connect issue_slots[7].wakeup_ports[4].bits.uop.is_sys_pc2epc, io.wakeup_ports[4].bits.uop.is_sys_pc2epc connect issue_slots[7].wakeup_ports[4].bits.uop.is_eret, io.wakeup_ports[4].bits.uop.is_eret connect issue_slots[7].wakeup_ports[4].bits.uop.is_amo, io.wakeup_ports[4].bits.uop.is_amo connect issue_slots[7].wakeup_ports[4].bits.uop.is_sfence, io.wakeup_ports[4].bits.uop.is_sfence connect issue_slots[7].wakeup_ports[4].bits.uop.is_fencei, io.wakeup_ports[4].bits.uop.is_fencei connect issue_slots[7].wakeup_ports[4].bits.uop.is_fence, io.wakeup_ports[4].bits.uop.is_fence connect issue_slots[7].wakeup_ports[4].bits.uop.is_sfb, io.wakeup_ports[4].bits.uop.is_sfb connect issue_slots[7].wakeup_ports[4].bits.uop.br_type, io.wakeup_ports[4].bits.uop.br_type connect issue_slots[7].wakeup_ports[4].bits.uop.br_tag, io.wakeup_ports[4].bits.uop.br_tag connect issue_slots[7].wakeup_ports[4].bits.uop.br_mask, io.wakeup_ports[4].bits.uop.br_mask connect issue_slots[7].wakeup_ports[4].bits.uop.dis_col_sel, io.wakeup_ports[4].bits.uop.dis_col_sel connect issue_slots[7].wakeup_ports[4].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect issue_slots[7].wakeup_ports[4].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect issue_slots[7].wakeup_ports[4].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect issue_slots[7].wakeup_ports[4].bits.uop.iw_p2_speculative_child, io.wakeup_ports[4].bits.uop.iw_p2_speculative_child connect issue_slots[7].wakeup_ports[4].bits.uop.iw_p1_speculative_child, io.wakeup_ports[4].bits.uop.iw_p1_speculative_child connect issue_slots[7].wakeup_ports[4].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect issue_slots[7].wakeup_ports[4].bits.uop.iw_issued_partial_agen, io.wakeup_ports[4].bits.uop.iw_issued_partial_agen connect issue_slots[7].wakeup_ports[4].bits.uop.iw_issued, io.wakeup_ports[4].bits.uop.iw_issued connect issue_slots[7].wakeup_ports[4].bits.uop.fu_code[0], io.wakeup_ports[4].bits.uop.fu_code[0] connect issue_slots[7].wakeup_ports[4].bits.uop.fu_code[1], io.wakeup_ports[4].bits.uop.fu_code[1] connect issue_slots[7].wakeup_ports[4].bits.uop.fu_code[2], io.wakeup_ports[4].bits.uop.fu_code[2] connect issue_slots[7].wakeup_ports[4].bits.uop.fu_code[3], io.wakeup_ports[4].bits.uop.fu_code[3] connect issue_slots[7].wakeup_ports[4].bits.uop.fu_code[4], io.wakeup_ports[4].bits.uop.fu_code[4] connect issue_slots[7].wakeup_ports[4].bits.uop.fu_code[5], io.wakeup_ports[4].bits.uop.fu_code[5] connect issue_slots[7].wakeup_ports[4].bits.uop.fu_code[6], io.wakeup_ports[4].bits.uop.fu_code[6] connect issue_slots[7].wakeup_ports[4].bits.uop.fu_code[7], io.wakeup_ports[4].bits.uop.fu_code[7] connect issue_slots[7].wakeup_ports[4].bits.uop.fu_code[8], io.wakeup_ports[4].bits.uop.fu_code[8] connect issue_slots[7].wakeup_ports[4].bits.uop.fu_code[9], io.wakeup_ports[4].bits.uop.fu_code[9] connect issue_slots[7].wakeup_ports[4].bits.uop.iq_type[0], io.wakeup_ports[4].bits.uop.iq_type[0] connect issue_slots[7].wakeup_ports[4].bits.uop.iq_type[1], io.wakeup_ports[4].bits.uop.iq_type[1] connect issue_slots[7].wakeup_ports[4].bits.uop.iq_type[2], io.wakeup_ports[4].bits.uop.iq_type[2] connect issue_slots[7].wakeup_ports[4].bits.uop.iq_type[3], io.wakeup_ports[4].bits.uop.iq_type[3] connect issue_slots[7].wakeup_ports[4].bits.uop.debug_pc, io.wakeup_ports[4].bits.uop.debug_pc connect issue_slots[7].wakeup_ports[4].bits.uop.is_rvc, io.wakeup_ports[4].bits.uop.is_rvc connect issue_slots[7].wakeup_ports[4].bits.uop.debug_inst, io.wakeup_ports[4].bits.uop.debug_inst connect issue_slots[7].wakeup_ports[4].bits.uop.inst, io.wakeup_ports[4].bits.uop.inst connect issue_slots[7].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[7].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[7].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[7].child_rebusys, io.child_rebusys connect issue_slots[7].squash_grant, io.squash_grant connect issue_slots[7].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[7].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[7].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[7].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[7].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[7].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[7].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[7].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[7].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[7].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[7].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[7].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[7].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[7].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect issue_slots[7].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect issue_slots[7].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[7].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect issue_slots[7].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect issue_slots[7].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[7].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[7].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[7].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[7].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[7].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[7].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[7].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[7].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[7].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect issue_slots[7].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[7].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[7].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[7].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[7].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[7].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[7].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[7].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[7].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[7].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[7].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[7].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[7].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[7].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[7].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[7].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[7].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[7].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[7].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[7].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[7].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[7].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[7].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[7].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect issue_slots[7].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect issue_slots[7].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect issue_slots[7].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect issue_slots[7].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect issue_slots[7].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect issue_slots[7].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect issue_slots[7].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect issue_slots[7].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect issue_slots[7].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect issue_slots[7].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect issue_slots[7].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect issue_slots[7].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect issue_slots[7].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect issue_slots[7].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect issue_slots[7].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect issue_slots[7].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect issue_slots[7].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect issue_slots[7].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect issue_slots[7].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[7].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect issue_slots[7].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect issue_slots[7].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect issue_slots[7].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[7].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[7].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[7].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[7].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect issue_slots[7].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect issue_slots[7].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[7].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect issue_slots[7].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[7].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect issue_slots[7].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[7].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[7].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[7].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect issue_slots[7].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[7].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[7].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect issue_slots[7].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect issue_slots[7].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect issue_slots[7].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect issue_slots[7].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect issue_slots[7].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect issue_slots[7].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect issue_slots[7].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect issue_slots[7].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect issue_slots[7].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect issue_slots[7].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect issue_slots[7].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect issue_slots[7].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect issue_slots[7].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect issue_slots[7].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect issue_slots[7].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect issue_slots[7].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect issue_slots[7].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect issue_slots[7].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect issue_slots[7].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect issue_slots[7].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect issue_slots[7].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect issue_slots[7].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect issue_slots[7].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[7].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[7].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[7].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[7].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[7].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[7].kill, io.flush_pipeline connect issue_slots[8].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy connect issue_slots[8].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask connect issue_slots[8].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable connect issue_slots[8].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc connect issue_slots[8].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc connect issue_slots[8].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if connect issue_slots[8].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if connect issue_slots[8].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if connect issue_slots[8].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if connect issue_slots[8].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if connect issue_slots[8].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ connect issue_slots[8].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm connect issue_slots[8].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val connect issue_slots[8].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op connect issue_slots[8].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw connect issue_slots[8].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en connect issue_slots[8].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype connect issue_slots[8].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype connect issue_slots[8].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype connect issue_slots[8].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 connect issue_slots[8].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 connect issue_slots[8].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 connect issue_slots[8].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst connect issue_slots[8].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 connect issue_slots[8].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd connect issue_slots[8].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit connect issue_slots[8].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique connect issue_slots[8].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq connect issue_slots[8].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq connect issue_slots[8].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed connect issue_slots[8].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size connect issue_slots[8].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd connect issue_slots[8].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause connect issue_slots[8].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception connect issue_slots[8].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst connect issue_slots[8].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy connect issue_slots[8].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy connect issue_slots[8].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy connect issue_slots[8].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy connect issue_slots[8].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred connect issue_slots[8].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 connect issue_slots[8].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 connect issue_slots[8].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 connect issue_slots[8].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst connect issue_slots[8].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx connect issue_slots[8].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx connect issue_slots[8].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx connect issue_slots[8].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst connect issue_slots[8].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel connect issue_slots[8].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel connect issue_slots[8].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed connect issue_slots[8].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm connect issue_slots[8].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel connect issue_slots[8].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename connect issue_slots[8].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken connect issue_slots[8].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob connect issue_slots[8].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst connect issue_slots[8].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx connect issue_slots[8].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov connect issue_slots[8].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc connect issue_slots[8].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc connect issue_slots[8].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret connect issue_slots[8].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo connect issue_slots[8].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence connect issue_slots[8].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei connect issue_slots[8].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence connect issue_slots[8].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb connect issue_slots[8].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type connect issue_slots[8].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag connect issue_slots[8].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask connect issue_slots[8].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel connect issue_slots[8].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect issue_slots[8].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect issue_slots[8].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect issue_slots[8].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child connect issue_slots[8].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child connect issue_slots[8].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect issue_slots[8].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen connect issue_slots[8].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued connect issue_slots[8].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] connect issue_slots[8].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] connect issue_slots[8].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] connect issue_slots[8].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] connect issue_slots[8].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] connect issue_slots[8].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] connect issue_slots[8].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] connect issue_slots[8].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] connect issue_slots[8].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] connect issue_slots[8].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] connect issue_slots[8].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] connect issue_slots[8].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] connect issue_slots[8].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] connect issue_slots[8].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] connect issue_slots[8].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc connect issue_slots[8].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc connect issue_slots[8].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst connect issue_slots[8].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst connect issue_slots[8].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[8].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy connect issue_slots[8].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask connect issue_slots[8].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable connect issue_slots[8].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc connect issue_slots[8].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc connect issue_slots[8].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if connect issue_slots[8].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if connect issue_slots[8].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if connect issue_slots[8].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if connect issue_slots[8].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if connect issue_slots[8].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ connect issue_slots[8].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm connect issue_slots[8].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val connect issue_slots[8].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op connect issue_slots[8].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw connect issue_slots[8].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en connect issue_slots[8].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype connect issue_slots[8].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype connect issue_slots[8].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype connect issue_slots[8].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 connect issue_slots[8].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 connect issue_slots[8].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 connect issue_slots[8].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst connect issue_slots[8].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 connect issue_slots[8].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd connect issue_slots[8].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit connect issue_slots[8].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique connect issue_slots[8].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq connect issue_slots[8].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq connect issue_slots[8].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed connect issue_slots[8].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size connect issue_slots[8].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd connect issue_slots[8].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause connect issue_slots[8].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception connect issue_slots[8].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst connect issue_slots[8].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy connect issue_slots[8].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy connect issue_slots[8].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy connect issue_slots[8].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy connect issue_slots[8].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred connect issue_slots[8].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 connect issue_slots[8].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 connect issue_slots[8].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 connect issue_slots[8].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst connect issue_slots[8].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx connect issue_slots[8].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx connect issue_slots[8].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx connect issue_slots[8].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst connect issue_slots[8].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel connect issue_slots[8].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel connect issue_slots[8].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed connect issue_slots[8].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm connect issue_slots[8].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel connect issue_slots[8].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename connect issue_slots[8].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken connect issue_slots[8].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob connect issue_slots[8].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst connect issue_slots[8].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx connect issue_slots[8].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov connect issue_slots[8].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc connect issue_slots[8].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc connect issue_slots[8].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret connect issue_slots[8].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo connect issue_slots[8].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence connect issue_slots[8].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei connect issue_slots[8].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence connect issue_slots[8].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb connect issue_slots[8].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type connect issue_slots[8].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag connect issue_slots[8].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask connect issue_slots[8].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel connect issue_slots[8].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect issue_slots[8].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect issue_slots[8].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect issue_slots[8].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child connect issue_slots[8].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child connect issue_slots[8].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect issue_slots[8].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen connect issue_slots[8].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued connect issue_slots[8].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] connect issue_slots[8].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] connect issue_slots[8].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] connect issue_slots[8].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] connect issue_slots[8].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] connect issue_slots[8].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] connect issue_slots[8].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] connect issue_slots[8].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] connect issue_slots[8].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] connect issue_slots[8].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] connect issue_slots[8].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] connect issue_slots[8].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] connect issue_slots[8].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] connect issue_slots[8].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] connect issue_slots[8].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc connect issue_slots[8].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc connect issue_slots[8].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst connect issue_slots[8].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst connect issue_slots[8].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[8].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy connect issue_slots[8].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask connect issue_slots[8].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable connect issue_slots[8].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc connect issue_slots[8].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc connect issue_slots[8].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if connect issue_slots[8].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if connect issue_slots[8].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if connect issue_slots[8].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if connect issue_slots[8].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if connect issue_slots[8].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ connect issue_slots[8].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm connect issue_slots[8].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val connect issue_slots[8].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op connect issue_slots[8].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw connect issue_slots[8].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en connect issue_slots[8].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype connect issue_slots[8].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype connect issue_slots[8].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype connect issue_slots[8].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3 connect issue_slots[8].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2 connect issue_slots[8].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1 connect issue_slots[8].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst connect issue_slots[8].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1 connect issue_slots[8].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd connect issue_slots[8].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit connect issue_slots[8].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique connect issue_slots[8].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq connect issue_slots[8].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq connect issue_slots[8].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed connect issue_slots[8].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size connect issue_slots[8].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd connect issue_slots[8].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause connect issue_slots[8].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception connect issue_slots[8].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst connect issue_slots[8].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy connect issue_slots[8].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy connect issue_slots[8].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy connect issue_slots[8].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy connect issue_slots[8].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred connect issue_slots[8].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3 connect issue_slots[8].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2 connect issue_slots[8].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1 connect issue_slots[8].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst connect issue_slots[8].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx connect issue_slots[8].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx connect issue_slots[8].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx connect issue_slots[8].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen connect issue_slots[8].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst connect issue_slots[8].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel connect issue_slots[8].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel connect issue_slots[8].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed connect issue_slots[8].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm connect issue_slots[8].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel connect issue_slots[8].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename connect issue_slots[8].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken connect issue_slots[8].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob connect issue_slots[8].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst connect issue_slots[8].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx connect issue_slots[8].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov connect issue_slots[8].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc connect issue_slots[8].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc connect issue_slots[8].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret connect issue_slots[8].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo connect issue_slots[8].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence connect issue_slots[8].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei connect issue_slots[8].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence connect issue_slots[8].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb connect issue_slots[8].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type connect issue_slots[8].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag connect issue_slots[8].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask connect issue_slots[8].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel connect issue_slots[8].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect issue_slots[8].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect issue_slots[8].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect issue_slots[8].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child connect issue_slots[8].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child connect issue_slots[8].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect issue_slots[8].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen connect issue_slots[8].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued connect issue_slots[8].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0] connect issue_slots[8].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1] connect issue_slots[8].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2] connect issue_slots[8].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3] connect issue_slots[8].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4] connect issue_slots[8].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5] connect issue_slots[8].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6] connect issue_slots[8].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7] connect issue_slots[8].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8] connect issue_slots[8].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9] connect issue_slots[8].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0] connect issue_slots[8].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1] connect issue_slots[8].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2] connect issue_slots[8].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3] connect issue_slots[8].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc connect issue_slots[8].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc connect issue_slots[8].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst connect issue_slots[8].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst connect issue_slots[8].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[8].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy connect issue_slots[8].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask connect issue_slots[8].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable connect issue_slots[8].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc connect issue_slots[8].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc connect issue_slots[8].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if connect issue_slots[8].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if connect issue_slots[8].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if connect issue_slots[8].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if connect issue_slots[8].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if connect issue_slots[8].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ connect issue_slots[8].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm connect issue_slots[8].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val connect issue_slots[8].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op connect issue_slots[8].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw connect issue_slots[8].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en connect issue_slots[8].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype connect issue_slots[8].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype connect issue_slots[8].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype connect issue_slots[8].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3 connect issue_slots[8].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2 connect issue_slots[8].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1 connect issue_slots[8].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst connect issue_slots[8].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1 connect issue_slots[8].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd connect issue_slots[8].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit connect issue_slots[8].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique connect issue_slots[8].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq connect issue_slots[8].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq connect issue_slots[8].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed connect issue_slots[8].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size connect issue_slots[8].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd connect issue_slots[8].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause connect issue_slots[8].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception connect issue_slots[8].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst connect issue_slots[8].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy connect issue_slots[8].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy connect issue_slots[8].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy connect issue_slots[8].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy connect issue_slots[8].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred connect issue_slots[8].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3 connect issue_slots[8].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2 connect issue_slots[8].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1 connect issue_slots[8].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst connect issue_slots[8].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx connect issue_slots[8].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx connect issue_slots[8].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx connect issue_slots[8].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen connect issue_slots[8].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst connect issue_slots[8].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel connect issue_slots[8].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel connect issue_slots[8].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed connect issue_slots[8].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm connect issue_slots[8].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel connect issue_slots[8].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename connect issue_slots[8].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken connect issue_slots[8].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob connect issue_slots[8].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst connect issue_slots[8].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx connect issue_slots[8].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov connect issue_slots[8].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc connect issue_slots[8].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc connect issue_slots[8].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret connect issue_slots[8].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo connect issue_slots[8].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence connect issue_slots[8].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei connect issue_slots[8].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence connect issue_slots[8].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb connect issue_slots[8].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type connect issue_slots[8].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag connect issue_slots[8].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask connect issue_slots[8].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel connect issue_slots[8].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect issue_slots[8].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect issue_slots[8].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect issue_slots[8].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child connect issue_slots[8].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child connect issue_slots[8].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect issue_slots[8].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen connect issue_slots[8].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued connect issue_slots[8].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0] connect issue_slots[8].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1] connect issue_slots[8].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2] connect issue_slots[8].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3] connect issue_slots[8].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4] connect issue_slots[8].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5] connect issue_slots[8].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6] connect issue_slots[8].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7] connect issue_slots[8].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8] connect issue_slots[8].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9] connect issue_slots[8].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0] connect issue_slots[8].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1] connect issue_slots[8].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2] connect issue_slots[8].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3] connect issue_slots[8].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc connect issue_slots[8].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc connect issue_slots[8].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst connect issue_slots[8].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst connect issue_slots[8].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[8].wakeup_ports[4].bits.rebusy, io.wakeup_ports[4].bits.rebusy connect issue_slots[8].wakeup_ports[4].bits.speculative_mask, io.wakeup_ports[4].bits.speculative_mask connect issue_slots[8].wakeup_ports[4].bits.bypassable, io.wakeup_ports[4].bits.bypassable connect issue_slots[8].wakeup_ports[4].bits.uop.debug_tsrc, io.wakeup_ports[4].bits.uop.debug_tsrc connect issue_slots[8].wakeup_ports[4].bits.uop.debug_fsrc, io.wakeup_ports[4].bits.uop.debug_fsrc connect issue_slots[8].wakeup_ports[4].bits.uop.bp_xcpt_if, io.wakeup_ports[4].bits.uop.bp_xcpt_if connect issue_slots[8].wakeup_ports[4].bits.uop.bp_debug_if, io.wakeup_ports[4].bits.uop.bp_debug_if connect issue_slots[8].wakeup_ports[4].bits.uop.xcpt_ma_if, io.wakeup_ports[4].bits.uop.xcpt_ma_if connect issue_slots[8].wakeup_ports[4].bits.uop.xcpt_ae_if, io.wakeup_ports[4].bits.uop.xcpt_ae_if connect issue_slots[8].wakeup_ports[4].bits.uop.xcpt_pf_if, io.wakeup_ports[4].bits.uop.xcpt_pf_if connect issue_slots[8].wakeup_ports[4].bits.uop.fp_typ, io.wakeup_ports[4].bits.uop.fp_typ connect issue_slots[8].wakeup_ports[4].bits.uop.fp_rm, io.wakeup_ports[4].bits.uop.fp_rm connect issue_slots[8].wakeup_ports[4].bits.uop.fp_val, io.wakeup_ports[4].bits.uop.fp_val connect issue_slots[8].wakeup_ports[4].bits.uop.fcn_op, io.wakeup_ports[4].bits.uop.fcn_op connect issue_slots[8].wakeup_ports[4].bits.uop.fcn_dw, io.wakeup_ports[4].bits.uop.fcn_dw connect issue_slots[8].wakeup_ports[4].bits.uop.frs3_en, io.wakeup_ports[4].bits.uop.frs3_en connect issue_slots[8].wakeup_ports[4].bits.uop.lrs2_rtype, io.wakeup_ports[4].bits.uop.lrs2_rtype connect issue_slots[8].wakeup_ports[4].bits.uop.lrs1_rtype, io.wakeup_ports[4].bits.uop.lrs1_rtype connect issue_slots[8].wakeup_ports[4].bits.uop.dst_rtype, io.wakeup_ports[4].bits.uop.dst_rtype connect issue_slots[8].wakeup_ports[4].bits.uop.lrs3, io.wakeup_ports[4].bits.uop.lrs3 connect issue_slots[8].wakeup_ports[4].bits.uop.lrs2, io.wakeup_ports[4].bits.uop.lrs2 connect issue_slots[8].wakeup_ports[4].bits.uop.lrs1, io.wakeup_ports[4].bits.uop.lrs1 connect issue_slots[8].wakeup_ports[4].bits.uop.ldst, io.wakeup_ports[4].bits.uop.ldst connect issue_slots[8].wakeup_ports[4].bits.uop.ldst_is_rs1, io.wakeup_ports[4].bits.uop.ldst_is_rs1 connect issue_slots[8].wakeup_ports[4].bits.uop.csr_cmd, io.wakeup_ports[4].bits.uop.csr_cmd connect issue_slots[8].wakeup_ports[4].bits.uop.flush_on_commit, io.wakeup_ports[4].bits.uop.flush_on_commit connect issue_slots[8].wakeup_ports[4].bits.uop.is_unique, io.wakeup_ports[4].bits.uop.is_unique connect issue_slots[8].wakeup_ports[4].bits.uop.uses_stq, io.wakeup_ports[4].bits.uop.uses_stq connect issue_slots[8].wakeup_ports[4].bits.uop.uses_ldq, io.wakeup_ports[4].bits.uop.uses_ldq connect issue_slots[8].wakeup_ports[4].bits.uop.mem_signed, io.wakeup_ports[4].bits.uop.mem_signed connect issue_slots[8].wakeup_ports[4].bits.uop.mem_size, io.wakeup_ports[4].bits.uop.mem_size connect issue_slots[8].wakeup_ports[4].bits.uop.mem_cmd, io.wakeup_ports[4].bits.uop.mem_cmd connect issue_slots[8].wakeup_ports[4].bits.uop.exc_cause, io.wakeup_ports[4].bits.uop.exc_cause connect issue_slots[8].wakeup_ports[4].bits.uop.exception, io.wakeup_ports[4].bits.uop.exception connect issue_slots[8].wakeup_ports[4].bits.uop.stale_pdst, io.wakeup_ports[4].bits.uop.stale_pdst connect issue_slots[8].wakeup_ports[4].bits.uop.ppred_busy, io.wakeup_ports[4].bits.uop.ppred_busy connect issue_slots[8].wakeup_ports[4].bits.uop.prs3_busy, io.wakeup_ports[4].bits.uop.prs3_busy connect issue_slots[8].wakeup_ports[4].bits.uop.prs2_busy, io.wakeup_ports[4].bits.uop.prs2_busy connect issue_slots[8].wakeup_ports[4].bits.uop.prs1_busy, io.wakeup_ports[4].bits.uop.prs1_busy connect issue_slots[8].wakeup_ports[4].bits.uop.ppred, io.wakeup_ports[4].bits.uop.ppred connect issue_slots[8].wakeup_ports[4].bits.uop.prs3, io.wakeup_ports[4].bits.uop.prs3 connect issue_slots[8].wakeup_ports[4].bits.uop.prs2, io.wakeup_ports[4].bits.uop.prs2 connect issue_slots[8].wakeup_ports[4].bits.uop.prs1, io.wakeup_ports[4].bits.uop.prs1 connect issue_slots[8].wakeup_ports[4].bits.uop.pdst, io.wakeup_ports[4].bits.uop.pdst connect issue_slots[8].wakeup_ports[4].bits.uop.rxq_idx, io.wakeup_ports[4].bits.uop.rxq_idx connect issue_slots[8].wakeup_ports[4].bits.uop.stq_idx, io.wakeup_ports[4].bits.uop.stq_idx connect issue_slots[8].wakeup_ports[4].bits.uop.ldq_idx, io.wakeup_ports[4].bits.uop.ldq_idx connect issue_slots[8].wakeup_ports[4].bits.uop.rob_idx, io.wakeup_ports[4].bits.uop.rob_idx connect issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.vec, io.wakeup_ports[4].bits.uop.fp_ctrl.vec connect issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.wflags, io.wakeup_ports[4].bits.uop.fp_ctrl.wflags connect issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.div, io.wakeup_ports[4].bits.uop.fp_ctrl.div connect issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.fma, io.wakeup_ports[4].bits.uop.fp_ctrl.fma connect issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.toint, io.wakeup_ports[4].bits.uop.fp_ctrl.toint connect issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.fromint, io.wakeup_ports[4].bits.uop.fp_ctrl.fromint connect issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.swap23, io.wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.swap12, io.wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.ren3, io.wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.ren2, io.wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.ren1, io.wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.wen, io.wakeup_ports[4].bits.uop.fp_ctrl.wen connect issue_slots[8].wakeup_ports[4].bits.uop.fp_ctrl.ldst, io.wakeup_ports[4].bits.uop.fp_ctrl.ldst connect issue_slots[8].wakeup_ports[4].bits.uop.op2_sel, io.wakeup_ports[4].bits.uop.op2_sel connect issue_slots[8].wakeup_ports[4].bits.uop.op1_sel, io.wakeup_ports[4].bits.uop.op1_sel connect issue_slots[8].wakeup_ports[4].bits.uop.imm_packed, io.wakeup_ports[4].bits.uop.imm_packed connect issue_slots[8].wakeup_ports[4].bits.uop.pimm, io.wakeup_ports[4].bits.uop.pimm connect issue_slots[8].wakeup_ports[4].bits.uop.imm_sel, io.wakeup_ports[4].bits.uop.imm_sel connect issue_slots[8].wakeup_ports[4].bits.uop.imm_rename, io.wakeup_ports[4].bits.uop.imm_rename connect issue_slots[8].wakeup_ports[4].bits.uop.taken, io.wakeup_ports[4].bits.uop.taken connect issue_slots[8].wakeup_ports[4].bits.uop.pc_lob, io.wakeup_ports[4].bits.uop.pc_lob connect issue_slots[8].wakeup_ports[4].bits.uop.edge_inst, io.wakeup_ports[4].bits.uop.edge_inst connect issue_slots[8].wakeup_ports[4].bits.uop.ftq_idx, io.wakeup_ports[4].bits.uop.ftq_idx connect issue_slots[8].wakeup_ports[4].bits.uop.is_mov, io.wakeup_ports[4].bits.uop.is_mov connect issue_slots[8].wakeup_ports[4].bits.uop.is_rocc, io.wakeup_ports[4].bits.uop.is_rocc connect issue_slots[8].wakeup_ports[4].bits.uop.is_sys_pc2epc, io.wakeup_ports[4].bits.uop.is_sys_pc2epc connect issue_slots[8].wakeup_ports[4].bits.uop.is_eret, io.wakeup_ports[4].bits.uop.is_eret connect issue_slots[8].wakeup_ports[4].bits.uop.is_amo, io.wakeup_ports[4].bits.uop.is_amo connect issue_slots[8].wakeup_ports[4].bits.uop.is_sfence, io.wakeup_ports[4].bits.uop.is_sfence connect issue_slots[8].wakeup_ports[4].bits.uop.is_fencei, io.wakeup_ports[4].bits.uop.is_fencei connect issue_slots[8].wakeup_ports[4].bits.uop.is_fence, io.wakeup_ports[4].bits.uop.is_fence connect issue_slots[8].wakeup_ports[4].bits.uop.is_sfb, io.wakeup_ports[4].bits.uop.is_sfb connect issue_slots[8].wakeup_ports[4].bits.uop.br_type, io.wakeup_ports[4].bits.uop.br_type connect issue_slots[8].wakeup_ports[4].bits.uop.br_tag, io.wakeup_ports[4].bits.uop.br_tag connect issue_slots[8].wakeup_ports[4].bits.uop.br_mask, io.wakeup_ports[4].bits.uop.br_mask connect issue_slots[8].wakeup_ports[4].bits.uop.dis_col_sel, io.wakeup_ports[4].bits.uop.dis_col_sel connect issue_slots[8].wakeup_ports[4].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect issue_slots[8].wakeup_ports[4].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect issue_slots[8].wakeup_ports[4].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect issue_slots[8].wakeup_ports[4].bits.uop.iw_p2_speculative_child, io.wakeup_ports[4].bits.uop.iw_p2_speculative_child connect issue_slots[8].wakeup_ports[4].bits.uop.iw_p1_speculative_child, io.wakeup_ports[4].bits.uop.iw_p1_speculative_child connect issue_slots[8].wakeup_ports[4].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect issue_slots[8].wakeup_ports[4].bits.uop.iw_issued_partial_agen, io.wakeup_ports[4].bits.uop.iw_issued_partial_agen connect issue_slots[8].wakeup_ports[4].bits.uop.iw_issued, io.wakeup_ports[4].bits.uop.iw_issued connect issue_slots[8].wakeup_ports[4].bits.uop.fu_code[0], io.wakeup_ports[4].bits.uop.fu_code[0] connect issue_slots[8].wakeup_ports[4].bits.uop.fu_code[1], io.wakeup_ports[4].bits.uop.fu_code[1] connect issue_slots[8].wakeup_ports[4].bits.uop.fu_code[2], io.wakeup_ports[4].bits.uop.fu_code[2] connect issue_slots[8].wakeup_ports[4].bits.uop.fu_code[3], io.wakeup_ports[4].bits.uop.fu_code[3] connect issue_slots[8].wakeup_ports[4].bits.uop.fu_code[4], io.wakeup_ports[4].bits.uop.fu_code[4] connect issue_slots[8].wakeup_ports[4].bits.uop.fu_code[5], io.wakeup_ports[4].bits.uop.fu_code[5] connect issue_slots[8].wakeup_ports[4].bits.uop.fu_code[6], io.wakeup_ports[4].bits.uop.fu_code[6] connect issue_slots[8].wakeup_ports[4].bits.uop.fu_code[7], io.wakeup_ports[4].bits.uop.fu_code[7] connect issue_slots[8].wakeup_ports[4].bits.uop.fu_code[8], io.wakeup_ports[4].bits.uop.fu_code[8] connect issue_slots[8].wakeup_ports[4].bits.uop.fu_code[9], io.wakeup_ports[4].bits.uop.fu_code[9] connect issue_slots[8].wakeup_ports[4].bits.uop.iq_type[0], io.wakeup_ports[4].bits.uop.iq_type[0] connect issue_slots[8].wakeup_ports[4].bits.uop.iq_type[1], io.wakeup_ports[4].bits.uop.iq_type[1] connect issue_slots[8].wakeup_ports[4].bits.uop.iq_type[2], io.wakeup_ports[4].bits.uop.iq_type[2] connect issue_slots[8].wakeup_ports[4].bits.uop.iq_type[3], io.wakeup_ports[4].bits.uop.iq_type[3] connect issue_slots[8].wakeup_ports[4].bits.uop.debug_pc, io.wakeup_ports[4].bits.uop.debug_pc connect issue_slots[8].wakeup_ports[4].bits.uop.is_rvc, io.wakeup_ports[4].bits.uop.is_rvc connect issue_slots[8].wakeup_ports[4].bits.uop.debug_inst, io.wakeup_ports[4].bits.uop.debug_inst connect issue_slots[8].wakeup_ports[4].bits.uop.inst, io.wakeup_ports[4].bits.uop.inst connect issue_slots[8].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[8].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[8].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[8].child_rebusys, io.child_rebusys connect issue_slots[8].squash_grant, io.squash_grant connect issue_slots[8].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[8].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[8].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[8].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[8].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[8].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[8].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[8].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[8].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[8].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[8].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[8].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[8].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[8].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect issue_slots[8].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect issue_slots[8].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[8].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect issue_slots[8].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect issue_slots[8].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[8].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[8].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[8].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[8].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[8].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[8].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[8].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[8].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[8].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect issue_slots[8].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[8].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[8].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[8].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[8].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[8].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[8].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[8].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[8].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[8].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[8].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[8].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[8].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[8].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[8].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[8].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[8].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[8].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[8].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[8].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[8].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[8].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[8].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[8].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect issue_slots[8].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect issue_slots[8].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect issue_slots[8].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect issue_slots[8].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect issue_slots[8].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect issue_slots[8].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect issue_slots[8].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect issue_slots[8].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect issue_slots[8].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect issue_slots[8].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect issue_slots[8].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect issue_slots[8].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect issue_slots[8].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect issue_slots[8].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect issue_slots[8].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect issue_slots[8].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect issue_slots[8].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect issue_slots[8].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect issue_slots[8].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[8].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect issue_slots[8].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect issue_slots[8].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect issue_slots[8].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[8].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[8].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[8].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[8].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect issue_slots[8].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect issue_slots[8].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[8].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect issue_slots[8].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[8].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect issue_slots[8].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[8].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[8].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[8].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect issue_slots[8].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[8].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[8].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect issue_slots[8].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect issue_slots[8].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect issue_slots[8].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect issue_slots[8].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect issue_slots[8].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect issue_slots[8].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect issue_slots[8].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect issue_slots[8].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect issue_slots[8].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect issue_slots[8].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect issue_slots[8].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect issue_slots[8].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect issue_slots[8].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect issue_slots[8].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect issue_slots[8].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect issue_slots[8].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect issue_slots[8].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect issue_slots[8].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect issue_slots[8].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect issue_slots[8].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect issue_slots[8].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect issue_slots[8].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect issue_slots[8].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[8].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[8].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[8].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[8].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[8].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[8].kill, io.flush_pipeline connect issue_slots[9].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy connect issue_slots[9].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask connect issue_slots[9].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable connect issue_slots[9].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc connect issue_slots[9].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc connect issue_slots[9].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if connect issue_slots[9].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if connect issue_slots[9].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if connect issue_slots[9].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if connect issue_slots[9].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if connect issue_slots[9].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ connect issue_slots[9].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm connect issue_slots[9].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val connect issue_slots[9].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op connect issue_slots[9].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw connect issue_slots[9].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en connect issue_slots[9].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype connect issue_slots[9].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype connect issue_slots[9].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype connect issue_slots[9].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 connect issue_slots[9].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 connect issue_slots[9].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 connect issue_slots[9].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst connect issue_slots[9].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 connect issue_slots[9].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd connect issue_slots[9].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit connect issue_slots[9].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique connect issue_slots[9].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq connect issue_slots[9].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq connect issue_slots[9].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed connect issue_slots[9].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size connect issue_slots[9].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd connect issue_slots[9].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause connect issue_slots[9].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception connect issue_slots[9].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst connect issue_slots[9].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy connect issue_slots[9].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy connect issue_slots[9].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy connect issue_slots[9].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy connect issue_slots[9].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred connect issue_slots[9].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 connect issue_slots[9].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 connect issue_slots[9].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 connect issue_slots[9].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst connect issue_slots[9].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx connect issue_slots[9].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx connect issue_slots[9].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx connect issue_slots[9].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst connect issue_slots[9].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel connect issue_slots[9].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel connect issue_slots[9].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed connect issue_slots[9].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm connect issue_slots[9].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel connect issue_slots[9].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename connect issue_slots[9].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken connect issue_slots[9].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob connect issue_slots[9].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst connect issue_slots[9].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx connect issue_slots[9].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov connect issue_slots[9].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc connect issue_slots[9].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc connect issue_slots[9].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret connect issue_slots[9].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo connect issue_slots[9].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence connect issue_slots[9].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei connect issue_slots[9].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence connect issue_slots[9].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb connect issue_slots[9].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type connect issue_slots[9].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag connect issue_slots[9].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask connect issue_slots[9].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel connect issue_slots[9].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect issue_slots[9].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect issue_slots[9].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect issue_slots[9].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child connect issue_slots[9].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child connect issue_slots[9].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect issue_slots[9].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen connect issue_slots[9].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued connect issue_slots[9].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] connect issue_slots[9].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] connect issue_slots[9].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] connect issue_slots[9].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] connect issue_slots[9].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] connect issue_slots[9].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] connect issue_slots[9].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] connect issue_slots[9].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] connect issue_slots[9].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] connect issue_slots[9].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] connect issue_slots[9].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] connect issue_slots[9].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] connect issue_slots[9].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] connect issue_slots[9].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] connect issue_slots[9].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc connect issue_slots[9].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc connect issue_slots[9].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst connect issue_slots[9].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst connect issue_slots[9].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[9].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy connect issue_slots[9].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask connect issue_slots[9].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable connect issue_slots[9].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc connect issue_slots[9].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc connect issue_slots[9].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if connect issue_slots[9].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if connect issue_slots[9].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if connect issue_slots[9].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if connect issue_slots[9].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if connect issue_slots[9].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ connect issue_slots[9].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm connect issue_slots[9].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val connect issue_slots[9].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op connect issue_slots[9].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw connect issue_slots[9].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en connect issue_slots[9].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype connect issue_slots[9].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype connect issue_slots[9].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype connect issue_slots[9].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 connect issue_slots[9].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 connect issue_slots[9].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 connect issue_slots[9].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst connect issue_slots[9].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 connect issue_slots[9].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd connect issue_slots[9].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit connect issue_slots[9].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique connect issue_slots[9].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq connect issue_slots[9].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq connect issue_slots[9].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed connect issue_slots[9].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size connect issue_slots[9].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd connect issue_slots[9].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause connect issue_slots[9].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception connect issue_slots[9].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst connect issue_slots[9].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy connect issue_slots[9].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy connect issue_slots[9].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy connect issue_slots[9].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy connect issue_slots[9].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred connect issue_slots[9].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 connect issue_slots[9].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 connect issue_slots[9].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 connect issue_slots[9].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst connect issue_slots[9].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx connect issue_slots[9].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx connect issue_slots[9].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx connect issue_slots[9].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst connect issue_slots[9].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel connect issue_slots[9].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel connect issue_slots[9].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed connect issue_slots[9].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm connect issue_slots[9].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel connect issue_slots[9].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename connect issue_slots[9].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken connect issue_slots[9].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob connect issue_slots[9].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst connect issue_slots[9].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx connect issue_slots[9].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov connect issue_slots[9].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc connect issue_slots[9].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc connect issue_slots[9].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret connect issue_slots[9].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo connect issue_slots[9].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence connect issue_slots[9].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei connect issue_slots[9].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence connect issue_slots[9].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb connect issue_slots[9].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type connect issue_slots[9].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag connect issue_slots[9].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask connect issue_slots[9].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel connect issue_slots[9].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect issue_slots[9].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect issue_slots[9].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect issue_slots[9].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child connect issue_slots[9].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child connect issue_slots[9].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect issue_slots[9].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen connect issue_slots[9].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued connect issue_slots[9].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] connect issue_slots[9].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] connect issue_slots[9].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] connect issue_slots[9].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] connect issue_slots[9].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] connect issue_slots[9].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] connect issue_slots[9].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] connect issue_slots[9].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] connect issue_slots[9].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] connect issue_slots[9].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] connect issue_slots[9].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] connect issue_slots[9].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] connect issue_slots[9].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] connect issue_slots[9].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] connect issue_slots[9].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc connect issue_slots[9].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc connect issue_slots[9].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst connect issue_slots[9].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst connect issue_slots[9].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[9].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy connect issue_slots[9].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask connect issue_slots[9].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable connect issue_slots[9].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc connect issue_slots[9].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc connect issue_slots[9].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if connect issue_slots[9].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if connect issue_slots[9].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if connect issue_slots[9].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if connect issue_slots[9].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if connect issue_slots[9].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ connect issue_slots[9].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm connect issue_slots[9].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val connect issue_slots[9].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op connect issue_slots[9].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw connect issue_slots[9].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en connect issue_slots[9].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype connect issue_slots[9].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype connect issue_slots[9].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype connect issue_slots[9].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3 connect issue_slots[9].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2 connect issue_slots[9].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1 connect issue_slots[9].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst connect issue_slots[9].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1 connect issue_slots[9].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd connect issue_slots[9].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit connect issue_slots[9].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique connect issue_slots[9].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq connect issue_slots[9].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq connect issue_slots[9].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed connect issue_slots[9].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size connect issue_slots[9].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd connect issue_slots[9].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause connect issue_slots[9].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception connect issue_slots[9].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst connect issue_slots[9].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy connect issue_slots[9].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy connect issue_slots[9].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy connect issue_slots[9].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy connect issue_slots[9].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred connect issue_slots[9].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3 connect issue_slots[9].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2 connect issue_slots[9].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1 connect issue_slots[9].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst connect issue_slots[9].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx connect issue_slots[9].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx connect issue_slots[9].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx connect issue_slots[9].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen connect issue_slots[9].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst connect issue_slots[9].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel connect issue_slots[9].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel connect issue_slots[9].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed connect issue_slots[9].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm connect issue_slots[9].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel connect issue_slots[9].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename connect issue_slots[9].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken connect issue_slots[9].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob connect issue_slots[9].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst connect issue_slots[9].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx connect issue_slots[9].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov connect issue_slots[9].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc connect issue_slots[9].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc connect issue_slots[9].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret connect issue_slots[9].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo connect issue_slots[9].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence connect issue_slots[9].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei connect issue_slots[9].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence connect issue_slots[9].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb connect issue_slots[9].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type connect issue_slots[9].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag connect issue_slots[9].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask connect issue_slots[9].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel connect issue_slots[9].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect issue_slots[9].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect issue_slots[9].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect issue_slots[9].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child connect issue_slots[9].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child connect issue_slots[9].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect issue_slots[9].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen connect issue_slots[9].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued connect issue_slots[9].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0] connect issue_slots[9].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1] connect issue_slots[9].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2] connect issue_slots[9].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3] connect issue_slots[9].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4] connect issue_slots[9].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5] connect issue_slots[9].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6] connect issue_slots[9].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7] connect issue_slots[9].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8] connect issue_slots[9].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9] connect issue_slots[9].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0] connect issue_slots[9].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1] connect issue_slots[9].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2] connect issue_slots[9].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3] connect issue_slots[9].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc connect issue_slots[9].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc connect issue_slots[9].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst connect issue_slots[9].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst connect issue_slots[9].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[9].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy connect issue_slots[9].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask connect issue_slots[9].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable connect issue_slots[9].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc connect issue_slots[9].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc connect issue_slots[9].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if connect issue_slots[9].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if connect issue_slots[9].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if connect issue_slots[9].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if connect issue_slots[9].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if connect issue_slots[9].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ connect issue_slots[9].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm connect issue_slots[9].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val connect issue_slots[9].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op connect issue_slots[9].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw connect issue_slots[9].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en connect issue_slots[9].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype connect issue_slots[9].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype connect issue_slots[9].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype connect issue_slots[9].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3 connect issue_slots[9].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2 connect issue_slots[9].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1 connect issue_slots[9].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst connect issue_slots[9].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1 connect issue_slots[9].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd connect issue_slots[9].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit connect issue_slots[9].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique connect issue_slots[9].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq connect issue_slots[9].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq connect issue_slots[9].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed connect issue_slots[9].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size connect issue_slots[9].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd connect issue_slots[9].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause connect issue_slots[9].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception connect issue_slots[9].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst connect issue_slots[9].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy connect issue_slots[9].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy connect issue_slots[9].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy connect issue_slots[9].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy connect issue_slots[9].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred connect issue_slots[9].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3 connect issue_slots[9].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2 connect issue_slots[9].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1 connect issue_slots[9].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst connect issue_slots[9].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx connect issue_slots[9].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx connect issue_slots[9].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx connect issue_slots[9].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen connect issue_slots[9].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst connect issue_slots[9].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel connect issue_slots[9].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel connect issue_slots[9].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed connect issue_slots[9].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm connect issue_slots[9].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel connect issue_slots[9].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename connect issue_slots[9].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken connect issue_slots[9].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob connect issue_slots[9].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst connect issue_slots[9].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx connect issue_slots[9].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov connect issue_slots[9].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc connect issue_slots[9].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc connect issue_slots[9].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret connect issue_slots[9].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo connect issue_slots[9].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence connect issue_slots[9].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei connect issue_slots[9].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence connect issue_slots[9].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb connect issue_slots[9].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type connect issue_slots[9].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag connect issue_slots[9].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask connect issue_slots[9].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel connect issue_slots[9].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect issue_slots[9].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect issue_slots[9].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect issue_slots[9].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child connect issue_slots[9].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child connect issue_slots[9].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect issue_slots[9].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen connect issue_slots[9].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued connect issue_slots[9].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0] connect issue_slots[9].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1] connect issue_slots[9].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2] connect issue_slots[9].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3] connect issue_slots[9].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4] connect issue_slots[9].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5] connect issue_slots[9].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6] connect issue_slots[9].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7] connect issue_slots[9].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8] connect issue_slots[9].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9] connect issue_slots[9].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0] connect issue_slots[9].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1] connect issue_slots[9].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2] connect issue_slots[9].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3] connect issue_slots[9].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc connect issue_slots[9].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc connect issue_slots[9].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst connect issue_slots[9].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst connect issue_slots[9].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[9].wakeup_ports[4].bits.rebusy, io.wakeup_ports[4].bits.rebusy connect issue_slots[9].wakeup_ports[4].bits.speculative_mask, io.wakeup_ports[4].bits.speculative_mask connect issue_slots[9].wakeup_ports[4].bits.bypassable, io.wakeup_ports[4].bits.bypassable connect issue_slots[9].wakeup_ports[4].bits.uop.debug_tsrc, io.wakeup_ports[4].bits.uop.debug_tsrc connect issue_slots[9].wakeup_ports[4].bits.uop.debug_fsrc, io.wakeup_ports[4].bits.uop.debug_fsrc connect issue_slots[9].wakeup_ports[4].bits.uop.bp_xcpt_if, io.wakeup_ports[4].bits.uop.bp_xcpt_if connect issue_slots[9].wakeup_ports[4].bits.uop.bp_debug_if, io.wakeup_ports[4].bits.uop.bp_debug_if connect issue_slots[9].wakeup_ports[4].bits.uop.xcpt_ma_if, io.wakeup_ports[4].bits.uop.xcpt_ma_if connect issue_slots[9].wakeup_ports[4].bits.uop.xcpt_ae_if, io.wakeup_ports[4].bits.uop.xcpt_ae_if connect issue_slots[9].wakeup_ports[4].bits.uop.xcpt_pf_if, io.wakeup_ports[4].bits.uop.xcpt_pf_if connect issue_slots[9].wakeup_ports[4].bits.uop.fp_typ, io.wakeup_ports[4].bits.uop.fp_typ connect issue_slots[9].wakeup_ports[4].bits.uop.fp_rm, io.wakeup_ports[4].bits.uop.fp_rm connect issue_slots[9].wakeup_ports[4].bits.uop.fp_val, io.wakeup_ports[4].bits.uop.fp_val connect issue_slots[9].wakeup_ports[4].bits.uop.fcn_op, io.wakeup_ports[4].bits.uop.fcn_op connect issue_slots[9].wakeup_ports[4].bits.uop.fcn_dw, io.wakeup_ports[4].bits.uop.fcn_dw connect issue_slots[9].wakeup_ports[4].bits.uop.frs3_en, io.wakeup_ports[4].bits.uop.frs3_en connect issue_slots[9].wakeup_ports[4].bits.uop.lrs2_rtype, io.wakeup_ports[4].bits.uop.lrs2_rtype connect issue_slots[9].wakeup_ports[4].bits.uop.lrs1_rtype, io.wakeup_ports[4].bits.uop.lrs1_rtype connect issue_slots[9].wakeup_ports[4].bits.uop.dst_rtype, io.wakeup_ports[4].bits.uop.dst_rtype connect issue_slots[9].wakeup_ports[4].bits.uop.lrs3, io.wakeup_ports[4].bits.uop.lrs3 connect issue_slots[9].wakeup_ports[4].bits.uop.lrs2, io.wakeup_ports[4].bits.uop.lrs2 connect issue_slots[9].wakeup_ports[4].bits.uop.lrs1, io.wakeup_ports[4].bits.uop.lrs1 connect issue_slots[9].wakeup_ports[4].bits.uop.ldst, io.wakeup_ports[4].bits.uop.ldst connect issue_slots[9].wakeup_ports[4].bits.uop.ldst_is_rs1, io.wakeup_ports[4].bits.uop.ldst_is_rs1 connect issue_slots[9].wakeup_ports[4].bits.uop.csr_cmd, io.wakeup_ports[4].bits.uop.csr_cmd connect issue_slots[9].wakeup_ports[4].bits.uop.flush_on_commit, io.wakeup_ports[4].bits.uop.flush_on_commit connect issue_slots[9].wakeup_ports[4].bits.uop.is_unique, io.wakeup_ports[4].bits.uop.is_unique connect issue_slots[9].wakeup_ports[4].bits.uop.uses_stq, io.wakeup_ports[4].bits.uop.uses_stq connect issue_slots[9].wakeup_ports[4].bits.uop.uses_ldq, io.wakeup_ports[4].bits.uop.uses_ldq connect issue_slots[9].wakeup_ports[4].bits.uop.mem_signed, io.wakeup_ports[4].bits.uop.mem_signed connect issue_slots[9].wakeup_ports[4].bits.uop.mem_size, io.wakeup_ports[4].bits.uop.mem_size connect issue_slots[9].wakeup_ports[4].bits.uop.mem_cmd, io.wakeup_ports[4].bits.uop.mem_cmd connect issue_slots[9].wakeup_ports[4].bits.uop.exc_cause, io.wakeup_ports[4].bits.uop.exc_cause connect issue_slots[9].wakeup_ports[4].bits.uop.exception, io.wakeup_ports[4].bits.uop.exception connect issue_slots[9].wakeup_ports[4].bits.uop.stale_pdst, io.wakeup_ports[4].bits.uop.stale_pdst connect issue_slots[9].wakeup_ports[4].bits.uop.ppred_busy, io.wakeup_ports[4].bits.uop.ppred_busy connect issue_slots[9].wakeup_ports[4].bits.uop.prs3_busy, io.wakeup_ports[4].bits.uop.prs3_busy connect issue_slots[9].wakeup_ports[4].bits.uop.prs2_busy, io.wakeup_ports[4].bits.uop.prs2_busy connect issue_slots[9].wakeup_ports[4].bits.uop.prs1_busy, io.wakeup_ports[4].bits.uop.prs1_busy connect issue_slots[9].wakeup_ports[4].bits.uop.ppred, io.wakeup_ports[4].bits.uop.ppred connect issue_slots[9].wakeup_ports[4].bits.uop.prs3, io.wakeup_ports[4].bits.uop.prs3 connect issue_slots[9].wakeup_ports[4].bits.uop.prs2, io.wakeup_ports[4].bits.uop.prs2 connect issue_slots[9].wakeup_ports[4].bits.uop.prs1, io.wakeup_ports[4].bits.uop.prs1 connect issue_slots[9].wakeup_ports[4].bits.uop.pdst, io.wakeup_ports[4].bits.uop.pdst connect issue_slots[9].wakeup_ports[4].bits.uop.rxq_idx, io.wakeup_ports[4].bits.uop.rxq_idx connect issue_slots[9].wakeup_ports[4].bits.uop.stq_idx, io.wakeup_ports[4].bits.uop.stq_idx connect issue_slots[9].wakeup_ports[4].bits.uop.ldq_idx, io.wakeup_ports[4].bits.uop.ldq_idx connect issue_slots[9].wakeup_ports[4].bits.uop.rob_idx, io.wakeup_ports[4].bits.uop.rob_idx connect issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.vec, io.wakeup_ports[4].bits.uop.fp_ctrl.vec connect issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.wflags, io.wakeup_ports[4].bits.uop.fp_ctrl.wflags connect issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.div, io.wakeup_ports[4].bits.uop.fp_ctrl.div connect issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.fma, io.wakeup_ports[4].bits.uop.fp_ctrl.fma connect issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.toint, io.wakeup_ports[4].bits.uop.fp_ctrl.toint connect issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.fromint, io.wakeup_ports[4].bits.uop.fp_ctrl.fromint connect issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.swap23, io.wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.swap12, io.wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.ren3, io.wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.ren2, io.wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.ren1, io.wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.wen, io.wakeup_ports[4].bits.uop.fp_ctrl.wen connect issue_slots[9].wakeup_ports[4].bits.uop.fp_ctrl.ldst, io.wakeup_ports[4].bits.uop.fp_ctrl.ldst connect issue_slots[9].wakeup_ports[4].bits.uop.op2_sel, io.wakeup_ports[4].bits.uop.op2_sel connect issue_slots[9].wakeup_ports[4].bits.uop.op1_sel, io.wakeup_ports[4].bits.uop.op1_sel connect issue_slots[9].wakeup_ports[4].bits.uop.imm_packed, io.wakeup_ports[4].bits.uop.imm_packed connect issue_slots[9].wakeup_ports[4].bits.uop.pimm, io.wakeup_ports[4].bits.uop.pimm connect issue_slots[9].wakeup_ports[4].bits.uop.imm_sel, io.wakeup_ports[4].bits.uop.imm_sel connect issue_slots[9].wakeup_ports[4].bits.uop.imm_rename, io.wakeup_ports[4].bits.uop.imm_rename connect issue_slots[9].wakeup_ports[4].bits.uop.taken, io.wakeup_ports[4].bits.uop.taken connect issue_slots[9].wakeup_ports[4].bits.uop.pc_lob, io.wakeup_ports[4].bits.uop.pc_lob connect issue_slots[9].wakeup_ports[4].bits.uop.edge_inst, io.wakeup_ports[4].bits.uop.edge_inst connect issue_slots[9].wakeup_ports[4].bits.uop.ftq_idx, io.wakeup_ports[4].bits.uop.ftq_idx connect issue_slots[9].wakeup_ports[4].bits.uop.is_mov, io.wakeup_ports[4].bits.uop.is_mov connect issue_slots[9].wakeup_ports[4].bits.uop.is_rocc, io.wakeup_ports[4].bits.uop.is_rocc connect issue_slots[9].wakeup_ports[4].bits.uop.is_sys_pc2epc, io.wakeup_ports[4].bits.uop.is_sys_pc2epc connect issue_slots[9].wakeup_ports[4].bits.uop.is_eret, io.wakeup_ports[4].bits.uop.is_eret connect issue_slots[9].wakeup_ports[4].bits.uop.is_amo, io.wakeup_ports[4].bits.uop.is_amo connect issue_slots[9].wakeup_ports[4].bits.uop.is_sfence, io.wakeup_ports[4].bits.uop.is_sfence connect issue_slots[9].wakeup_ports[4].bits.uop.is_fencei, io.wakeup_ports[4].bits.uop.is_fencei connect issue_slots[9].wakeup_ports[4].bits.uop.is_fence, io.wakeup_ports[4].bits.uop.is_fence connect issue_slots[9].wakeup_ports[4].bits.uop.is_sfb, io.wakeup_ports[4].bits.uop.is_sfb connect issue_slots[9].wakeup_ports[4].bits.uop.br_type, io.wakeup_ports[4].bits.uop.br_type connect issue_slots[9].wakeup_ports[4].bits.uop.br_tag, io.wakeup_ports[4].bits.uop.br_tag connect issue_slots[9].wakeup_ports[4].bits.uop.br_mask, io.wakeup_ports[4].bits.uop.br_mask connect issue_slots[9].wakeup_ports[4].bits.uop.dis_col_sel, io.wakeup_ports[4].bits.uop.dis_col_sel connect issue_slots[9].wakeup_ports[4].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect issue_slots[9].wakeup_ports[4].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect issue_slots[9].wakeup_ports[4].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect issue_slots[9].wakeup_ports[4].bits.uop.iw_p2_speculative_child, io.wakeup_ports[4].bits.uop.iw_p2_speculative_child connect issue_slots[9].wakeup_ports[4].bits.uop.iw_p1_speculative_child, io.wakeup_ports[4].bits.uop.iw_p1_speculative_child connect issue_slots[9].wakeup_ports[4].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect issue_slots[9].wakeup_ports[4].bits.uop.iw_issued_partial_agen, io.wakeup_ports[4].bits.uop.iw_issued_partial_agen connect issue_slots[9].wakeup_ports[4].bits.uop.iw_issued, io.wakeup_ports[4].bits.uop.iw_issued connect issue_slots[9].wakeup_ports[4].bits.uop.fu_code[0], io.wakeup_ports[4].bits.uop.fu_code[0] connect issue_slots[9].wakeup_ports[4].bits.uop.fu_code[1], io.wakeup_ports[4].bits.uop.fu_code[1] connect issue_slots[9].wakeup_ports[4].bits.uop.fu_code[2], io.wakeup_ports[4].bits.uop.fu_code[2] connect issue_slots[9].wakeup_ports[4].bits.uop.fu_code[3], io.wakeup_ports[4].bits.uop.fu_code[3] connect issue_slots[9].wakeup_ports[4].bits.uop.fu_code[4], io.wakeup_ports[4].bits.uop.fu_code[4] connect issue_slots[9].wakeup_ports[4].bits.uop.fu_code[5], io.wakeup_ports[4].bits.uop.fu_code[5] connect issue_slots[9].wakeup_ports[4].bits.uop.fu_code[6], io.wakeup_ports[4].bits.uop.fu_code[6] connect issue_slots[9].wakeup_ports[4].bits.uop.fu_code[7], io.wakeup_ports[4].bits.uop.fu_code[7] connect issue_slots[9].wakeup_ports[4].bits.uop.fu_code[8], io.wakeup_ports[4].bits.uop.fu_code[8] connect issue_slots[9].wakeup_ports[4].bits.uop.fu_code[9], io.wakeup_ports[4].bits.uop.fu_code[9] connect issue_slots[9].wakeup_ports[4].bits.uop.iq_type[0], io.wakeup_ports[4].bits.uop.iq_type[0] connect issue_slots[9].wakeup_ports[4].bits.uop.iq_type[1], io.wakeup_ports[4].bits.uop.iq_type[1] connect issue_slots[9].wakeup_ports[4].bits.uop.iq_type[2], io.wakeup_ports[4].bits.uop.iq_type[2] connect issue_slots[9].wakeup_ports[4].bits.uop.iq_type[3], io.wakeup_ports[4].bits.uop.iq_type[3] connect issue_slots[9].wakeup_ports[4].bits.uop.debug_pc, io.wakeup_ports[4].bits.uop.debug_pc connect issue_slots[9].wakeup_ports[4].bits.uop.is_rvc, io.wakeup_ports[4].bits.uop.is_rvc connect issue_slots[9].wakeup_ports[4].bits.uop.debug_inst, io.wakeup_ports[4].bits.uop.debug_inst connect issue_slots[9].wakeup_ports[4].bits.uop.inst, io.wakeup_ports[4].bits.uop.inst connect issue_slots[9].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[9].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[9].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[9].child_rebusys, io.child_rebusys connect issue_slots[9].squash_grant, io.squash_grant connect issue_slots[9].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[9].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[9].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[9].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[9].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[9].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[9].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[9].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[9].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[9].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[9].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[9].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[9].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[9].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect issue_slots[9].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect issue_slots[9].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[9].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect issue_slots[9].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect issue_slots[9].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[9].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[9].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[9].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[9].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[9].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[9].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[9].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[9].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[9].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect issue_slots[9].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[9].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[9].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[9].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[9].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[9].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[9].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[9].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[9].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[9].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[9].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[9].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[9].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[9].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[9].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[9].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[9].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[9].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[9].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[9].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[9].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[9].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[9].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[9].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect issue_slots[9].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect issue_slots[9].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect issue_slots[9].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect issue_slots[9].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect issue_slots[9].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect issue_slots[9].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect issue_slots[9].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect issue_slots[9].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect issue_slots[9].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect issue_slots[9].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect issue_slots[9].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect issue_slots[9].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect issue_slots[9].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect issue_slots[9].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect issue_slots[9].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect issue_slots[9].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect issue_slots[9].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect issue_slots[9].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect issue_slots[9].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[9].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect issue_slots[9].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect issue_slots[9].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect issue_slots[9].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[9].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[9].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[9].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[9].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect issue_slots[9].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect issue_slots[9].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[9].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect issue_slots[9].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[9].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect issue_slots[9].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[9].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[9].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[9].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect issue_slots[9].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[9].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[9].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect issue_slots[9].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect issue_slots[9].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect issue_slots[9].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect issue_slots[9].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect issue_slots[9].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect issue_slots[9].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect issue_slots[9].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect issue_slots[9].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect issue_slots[9].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect issue_slots[9].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect issue_slots[9].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect issue_slots[9].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect issue_slots[9].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect issue_slots[9].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect issue_slots[9].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect issue_slots[9].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect issue_slots[9].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect issue_slots[9].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect issue_slots[9].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect issue_slots[9].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect issue_slots[9].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect issue_slots[9].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect issue_slots[9].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[9].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[9].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[9].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[9].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[9].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[9].kill, io.flush_pipeline connect issue_slots[10].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy connect issue_slots[10].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask connect issue_slots[10].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable connect issue_slots[10].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc connect issue_slots[10].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc connect issue_slots[10].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if connect issue_slots[10].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if connect issue_slots[10].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if connect issue_slots[10].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if connect issue_slots[10].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if connect issue_slots[10].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ connect issue_slots[10].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm connect issue_slots[10].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val connect issue_slots[10].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op connect issue_slots[10].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw connect issue_slots[10].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en connect issue_slots[10].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype connect issue_slots[10].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype connect issue_slots[10].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype connect issue_slots[10].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 connect issue_slots[10].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 connect issue_slots[10].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 connect issue_slots[10].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst connect issue_slots[10].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 connect issue_slots[10].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd connect issue_slots[10].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit connect issue_slots[10].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique connect issue_slots[10].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq connect issue_slots[10].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq connect issue_slots[10].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed connect issue_slots[10].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size connect issue_slots[10].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd connect issue_slots[10].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause connect issue_slots[10].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception connect issue_slots[10].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst connect issue_slots[10].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy connect issue_slots[10].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy connect issue_slots[10].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy connect issue_slots[10].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy connect issue_slots[10].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred connect issue_slots[10].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 connect issue_slots[10].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 connect issue_slots[10].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 connect issue_slots[10].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst connect issue_slots[10].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx connect issue_slots[10].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx connect issue_slots[10].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx connect issue_slots[10].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst connect issue_slots[10].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel connect issue_slots[10].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel connect issue_slots[10].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed connect issue_slots[10].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm connect issue_slots[10].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel connect issue_slots[10].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename connect issue_slots[10].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken connect issue_slots[10].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob connect issue_slots[10].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst connect issue_slots[10].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx connect issue_slots[10].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov connect issue_slots[10].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc connect issue_slots[10].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc connect issue_slots[10].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret connect issue_slots[10].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo connect issue_slots[10].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence connect issue_slots[10].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei connect issue_slots[10].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence connect issue_slots[10].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb connect issue_slots[10].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type connect issue_slots[10].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag connect issue_slots[10].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask connect issue_slots[10].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel connect issue_slots[10].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect issue_slots[10].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect issue_slots[10].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect issue_slots[10].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child connect issue_slots[10].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child connect issue_slots[10].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect issue_slots[10].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen connect issue_slots[10].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued connect issue_slots[10].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] connect issue_slots[10].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] connect issue_slots[10].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] connect issue_slots[10].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] connect issue_slots[10].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] connect issue_slots[10].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] connect issue_slots[10].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] connect issue_slots[10].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] connect issue_slots[10].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] connect issue_slots[10].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] connect issue_slots[10].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] connect issue_slots[10].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] connect issue_slots[10].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] connect issue_slots[10].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] connect issue_slots[10].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc connect issue_slots[10].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc connect issue_slots[10].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst connect issue_slots[10].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst connect issue_slots[10].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[10].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy connect issue_slots[10].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask connect issue_slots[10].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable connect issue_slots[10].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc connect issue_slots[10].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc connect issue_slots[10].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if connect issue_slots[10].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if connect issue_slots[10].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if connect issue_slots[10].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if connect issue_slots[10].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if connect issue_slots[10].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ connect issue_slots[10].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm connect issue_slots[10].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val connect issue_slots[10].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op connect issue_slots[10].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw connect issue_slots[10].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en connect issue_slots[10].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype connect issue_slots[10].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype connect issue_slots[10].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype connect issue_slots[10].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 connect issue_slots[10].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 connect issue_slots[10].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 connect issue_slots[10].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst connect issue_slots[10].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 connect issue_slots[10].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd connect issue_slots[10].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit connect issue_slots[10].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique connect issue_slots[10].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq connect issue_slots[10].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq connect issue_slots[10].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed connect issue_slots[10].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size connect issue_slots[10].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd connect issue_slots[10].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause connect issue_slots[10].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception connect issue_slots[10].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst connect issue_slots[10].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy connect issue_slots[10].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy connect issue_slots[10].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy connect issue_slots[10].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy connect issue_slots[10].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred connect issue_slots[10].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 connect issue_slots[10].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 connect issue_slots[10].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 connect issue_slots[10].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst connect issue_slots[10].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx connect issue_slots[10].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx connect issue_slots[10].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx connect issue_slots[10].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst connect issue_slots[10].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel connect issue_slots[10].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel connect issue_slots[10].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed connect issue_slots[10].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm connect issue_slots[10].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel connect issue_slots[10].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename connect issue_slots[10].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken connect issue_slots[10].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob connect issue_slots[10].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst connect issue_slots[10].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx connect issue_slots[10].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov connect issue_slots[10].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc connect issue_slots[10].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc connect issue_slots[10].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret connect issue_slots[10].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo connect issue_slots[10].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence connect issue_slots[10].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei connect issue_slots[10].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence connect issue_slots[10].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb connect issue_slots[10].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type connect issue_slots[10].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag connect issue_slots[10].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask connect issue_slots[10].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel connect issue_slots[10].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect issue_slots[10].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect issue_slots[10].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect issue_slots[10].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child connect issue_slots[10].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child connect issue_slots[10].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect issue_slots[10].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen connect issue_slots[10].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued connect issue_slots[10].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] connect issue_slots[10].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] connect issue_slots[10].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] connect issue_slots[10].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] connect issue_slots[10].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] connect issue_slots[10].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] connect issue_slots[10].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] connect issue_slots[10].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] connect issue_slots[10].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] connect issue_slots[10].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] connect issue_slots[10].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] connect issue_slots[10].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] connect issue_slots[10].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] connect issue_slots[10].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] connect issue_slots[10].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc connect issue_slots[10].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc connect issue_slots[10].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst connect issue_slots[10].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst connect issue_slots[10].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[10].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy connect issue_slots[10].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask connect issue_slots[10].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable connect issue_slots[10].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc connect issue_slots[10].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc connect issue_slots[10].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if connect issue_slots[10].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if connect issue_slots[10].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if connect issue_slots[10].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if connect issue_slots[10].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if connect issue_slots[10].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ connect issue_slots[10].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm connect issue_slots[10].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val connect issue_slots[10].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op connect issue_slots[10].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw connect issue_slots[10].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en connect issue_slots[10].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype connect issue_slots[10].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype connect issue_slots[10].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype connect issue_slots[10].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3 connect issue_slots[10].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2 connect issue_slots[10].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1 connect issue_slots[10].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst connect issue_slots[10].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1 connect issue_slots[10].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd connect issue_slots[10].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit connect issue_slots[10].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique connect issue_slots[10].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq connect issue_slots[10].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq connect issue_slots[10].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed connect issue_slots[10].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size connect issue_slots[10].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd connect issue_slots[10].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause connect issue_slots[10].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception connect issue_slots[10].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst connect issue_slots[10].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy connect issue_slots[10].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy connect issue_slots[10].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy connect issue_slots[10].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy connect issue_slots[10].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred connect issue_slots[10].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3 connect issue_slots[10].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2 connect issue_slots[10].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1 connect issue_slots[10].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst connect issue_slots[10].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx connect issue_slots[10].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx connect issue_slots[10].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx connect issue_slots[10].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen connect issue_slots[10].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst connect issue_slots[10].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel connect issue_slots[10].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel connect issue_slots[10].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed connect issue_slots[10].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm connect issue_slots[10].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel connect issue_slots[10].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename connect issue_slots[10].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken connect issue_slots[10].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob connect issue_slots[10].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst connect issue_slots[10].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx connect issue_slots[10].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov connect issue_slots[10].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc connect issue_slots[10].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc connect issue_slots[10].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret connect issue_slots[10].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo connect issue_slots[10].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence connect issue_slots[10].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei connect issue_slots[10].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence connect issue_slots[10].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb connect issue_slots[10].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type connect issue_slots[10].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag connect issue_slots[10].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask connect issue_slots[10].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel connect issue_slots[10].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect issue_slots[10].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect issue_slots[10].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect issue_slots[10].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child connect issue_slots[10].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child connect issue_slots[10].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect issue_slots[10].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen connect issue_slots[10].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued connect issue_slots[10].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0] connect issue_slots[10].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1] connect issue_slots[10].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2] connect issue_slots[10].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3] connect issue_slots[10].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4] connect issue_slots[10].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5] connect issue_slots[10].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6] connect issue_slots[10].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7] connect issue_slots[10].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8] connect issue_slots[10].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9] connect issue_slots[10].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0] connect issue_slots[10].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1] connect issue_slots[10].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2] connect issue_slots[10].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3] connect issue_slots[10].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc connect issue_slots[10].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc connect issue_slots[10].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst connect issue_slots[10].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst connect issue_slots[10].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[10].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy connect issue_slots[10].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask connect issue_slots[10].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable connect issue_slots[10].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc connect issue_slots[10].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc connect issue_slots[10].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if connect issue_slots[10].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if connect issue_slots[10].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if connect issue_slots[10].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if connect issue_slots[10].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if connect issue_slots[10].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ connect issue_slots[10].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm connect issue_slots[10].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val connect issue_slots[10].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op connect issue_slots[10].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw connect issue_slots[10].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en connect issue_slots[10].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype connect issue_slots[10].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype connect issue_slots[10].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype connect issue_slots[10].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3 connect issue_slots[10].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2 connect issue_slots[10].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1 connect issue_slots[10].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst connect issue_slots[10].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1 connect issue_slots[10].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd connect issue_slots[10].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit connect issue_slots[10].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique connect issue_slots[10].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq connect issue_slots[10].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq connect issue_slots[10].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed connect issue_slots[10].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size connect issue_slots[10].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd connect issue_slots[10].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause connect issue_slots[10].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception connect issue_slots[10].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst connect issue_slots[10].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy connect issue_slots[10].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy connect issue_slots[10].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy connect issue_slots[10].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy connect issue_slots[10].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred connect issue_slots[10].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3 connect issue_slots[10].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2 connect issue_slots[10].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1 connect issue_slots[10].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst connect issue_slots[10].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx connect issue_slots[10].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx connect issue_slots[10].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx connect issue_slots[10].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen connect issue_slots[10].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst connect issue_slots[10].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel connect issue_slots[10].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel connect issue_slots[10].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed connect issue_slots[10].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm connect issue_slots[10].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel connect issue_slots[10].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename connect issue_slots[10].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken connect issue_slots[10].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob connect issue_slots[10].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst connect issue_slots[10].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx connect issue_slots[10].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov connect issue_slots[10].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc connect issue_slots[10].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc connect issue_slots[10].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret connect issue_slots[10].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo connect issue_slots[10].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence connect issue_slots[10].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei connect issue_slots[10].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence connect issue_slots[10].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb connect issue_slots[10].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type connect issue_slots[10].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag connect issue_slots[10].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask connect issue_slots[10].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel connect issue_slots[10].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect issue_slots[10].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect issue_slots[10].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect issue_slots[10].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child connect issue_slots[10].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child connect issue_slots[10].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect issue_slots[10].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen connect issue_slots[10].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued connect issue_slots[10].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0] connect issue_slots[10].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1] connect issue_slots[10].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2] connect issue_slots[10].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3] connect issue_slots[10].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4] connect issue_slots[10].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5] connect issue_slots[10].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6] connect issue_slots[10].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7] connect issue_slots[10].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8] connect issue_slots[10].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9] connect issue_slots[10].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0] connect issue_slots[10].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1] connect issue_slots[10].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2] connect issue_slots[10].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3] connect issue_slots[10].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc connect issue_slots[10].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc connect issue_slots[10].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst connect issue_slots[10].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst connect issue_slots[10].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[10].wakeup_ports[4].bits.rebusy, io.wakeup_ports[4].bits.rebusy connect issue_slots[10].wakeup_ports[4].bits.speculative_mask, io.wakeup_ports[4].bits.speculative_mask connect issue_slots[10].wakeup_ports[4].bits.bypassable, io.wakeup_ports[4].bits.bypassable connect issue_slots[10].wakeup_ports[4].bits.uop.debug_tsrc, io.wakeup_ports[4].bits.uop.debug_tsrc connect issue_slots[10].wakeup_ports[4].bits.uop.debug_fsrc, io.wakeup_ports[4].bits.uop.debug_fsrc connect issue_slots[10].wakeup_ports[4].bits.uop.bp_xcpt_if, io.wakeup_ports[4].bits.uop.bp_xcpt_if connect issue_slots[10].wakeup_ports[4].bits.uop.bp_debug_if, io.wakeup_ports[4].bits.uop.bp_debug_if connect issue_slots[10].wakeup_ports[4].bits.uop.xcpt_ma_if, io.wakeup_ports[4].bits.uop.xcpt_ma_if connect issue_slots[10].wakeup_ports[4].bits.uop.xcpt_ae_if, io.wakeup_ports[4].bits.uop.xcpt_ae_if connect issue_slots[10].wakeup_ports[4].bits.uop.xcpt_pf_if, io.wakeup_ports[4].bits.uop.xcpt_pf_if connect issue_slots[10].wakeup_ports[4].bits.uop.fp_typ, io.wakeup_ports[4].bits.uop.fp_typ connect issue_slots[10].wakeup_ports[4].bits.uop.fp_rm, io.wakeup_ports[4].bits.uop.fp_rm connect issue_slots[10].wakeup_ports[4].bits.uop.fp_val, io.wakeup_ports[4].bits.uop.fp_val connect issue_slots[10].wakeup_ports[4].bits.uop.fcn_op, io.wakeup_ports[4].bits.uop.fcn_op connect issue_slots[10].wakeup_ports[4].bits.uop.fcn_dw, io.wakeup_ports[4].bits.uop.fcn_dw connect issue_slots[10].wakeup_ports[4].bits.uop.frs3_en, io.wakeup_ports[4].bits.uop.frs3_en connect issue_slots[10].wakeup_ports[4].bits.uop.lrs2_rtype, io.wakeup_ports[4].bits.uop.lrs2_rtype connect issue_slots[10].wakeup_ports[4].bits.uop.lrs1_rtype, io.wakeup_ports[4].bits.uop.lrs1_rtype connect issue_slots[10].wakeup_ports[4].bits.uop.dst_rtype, io.wakeup_ports[4].bits.uop.dst_rtype connect issue_slots[10].wakeup_ports[4].bits.uop.lrs3, io.wakeup_ports[4].bits.uop.lrs3 connect issue_slots[10].wakeup_ports[4].bits.uop.lrs2, io.wakeup_ports[4].bits.uop.lrs2 connect issue_slots[10].wakeup_ports[4].bits.uop.lrs1, io.wakeup_ports[4].bits.uop.lrs1 connect issue_slots[10].wakeup_ports[4].bits.uop.ldst, io.wakeup_ports[4].bits.uop.ldst connect issue_slots[10].wakeup_ports[4].bits.uop.ldst_is_rs1, io.wakeup_ports[4].bits.uop.ldst_is_rs1 connect issue_slots[10].wakeup_ports[4].bits.uop.csr_cmd, io.wakeup_ports[4].bits.uop.csr_cmd connect issue_slots[10].wakeup_ports[4].bits.uop.flush_on_commit, io.wakeup_ports[4].bits.uop.flush_on_commit connect issue_slots[10].wakeup_ports[4].bits.uop.is_unique, io.wakeup_ports[4].bits.uop.is_unique connect issue_slots[10].wakeup_ports[4].bits.uop.uses_stq, io.wakeup_ports[4].bits.uop.uses_stq connect issue_slots[10].wakeup_ports[4].bits.uop.uses_ldq, io.wakeup_ports[4].bits.uop.uses_ldq connect issue_slots[10].wakeup_ports[4].bits.uop.mem_signed, io.wakeup_ports[4].bits.uop.mem_signed connect issue_slots[10].wakeup_ports[4].bits.uop.mem_size, io.wakeup_ports[4].bits.uop.mem_size connect issue_slots[10].wakeup_ports[4].bits.uop.mem_cmd, io.wakeup_ports[4].bits.uop.mem_cmd connect issue_slots[10].wakeup_ports[4].bits.uop.exc_cause, io.wakeup_ports[4].bits.uop.exc_cause connect issue_slots[10].wakeup_ports[4].bits.uop.exception, io.wakeup_ports[4].bits.uop.exception connect issue_slots[10].wakeup_ports[4].bits.uop.stale_pdst, io.wakeup_ports[4].bits.uop.stale_pdst connect issue_slots[10].wakeup_ports[4].bits.uop.ppred_busy, io.wakeup_ports[4].bits.uop.ppred_busy connect issue_slots[10].wakeup_ports[4].bits.uop.prs3_busy, io.wakeup_ports[4].bits.uop.prs3_busy connect issue_slots[10].wakeup_ports[4].bits.uop.prs2_busy, io.wakeup_ports[4].bits.uop.prs2_busy connect issue_slots[10].wakeup_ports[4].bits.uop.prs1_busy, io.wakeup_ports[4].bits.uop.prs1_busy connect issue_slots[10].wakeup_ports[4].bits.uop.ppred, io.wakeup_ports[4].bits.uop.ppred connect issue_slots[10].wakeup_ports[4].bits.uop.prs3, io.wakeup_ports[4].bits.uop.prs3 connect issue_slots[10].wakeup_ports[4].bits.uop.prs2, io.wakeup_ports[4].bits.uop.prs2 connect issue_slots[10].wakeup_ports[4].bits.uop.prs1, io.wakeup_ports[4].bits.uop.prs1 connect issue_slots[10].wakeup_ports[4].bits.uop.pdst, io.wakeup_ports[4].bits.uop.pdst connect issue_slots[10].wakeup_ports[4].bits.uop.rxq_idx, io.wakeup_ports[4].bits.uop.rxq_idx connect issue_slots[10].wakeup_ports[4].bits.uop.stq_idx, io.wakeup_ports[4].bits.uop.stq_idx connect issue_slots[10].wakeup_ports[4].bits.uop.ldq_idx, io.wakeup_ports[4].bits.uop.ldq_idx connect issue_slots[10].wakeup_ports[4].bits.uop.rob_idx, io.wakeup_ports[4].bits.uop.rob_idx connect issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.vec, io.wakeup_ports[4].bits.uop.fp_ctrl.vec connect issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.wflags, io.wakeup_ports[4].bits.uop.fp_ctrl.wflags connect issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.div, io.wakeup_ports[4].bits.uop.fp_ctrl.div connect issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.fma, io.wakeup_ports[4].bits.uop.fp_ctrl.fma connect issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.toint, io.wakeup_ports[4].bits.uop.fp_ctrl.toint connect issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.fromint, io.wakeup_ports[4].bits.uop.fp_ctrl.fromint connect issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.swap23, io.wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.swap12, io.wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.ren3, io.wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.ren2, io.wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.ren1, io.wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.wen, io.wakeup_ports[4].bits.uop.fp_ctrl.wen connect issue_slots[10].wakeup_ports[4].bits.uop.fp_ctrl.ldst, io.wakeup_ports[4].bits.uop.fp_ctrl.ldst connect issue_slots[10].wakeup_ports[4].bits.uop.op2_sel, io.wakeup_ports[4].bits.uop.op2_sel connect issue_slots[10].wakeup_ports[4].bits.uop.op1_sel, io.wakeup_ports[4].bits.uop.op1_sel connect issue_slots[10].wakeup_ports[4].bits.uop.imm_packed, io.wakeup_ports[4].bits.uop.imm_packed connect issue_slots[10].wakeup_ports[4].bits.uop.pimm, io.wakeup_ports[4].bits.uop.pimm connect issue_slots[10].wakeup_ports[4].bits.uop.imm_sel, io.wakeup_ports[4].bits.uop.imm_sel connect issue_slots[10].wakeup_ports[4].bits.uop.imm_rename, io.wakeup_ports[4].bits.uop.imm_rename connect issue_slots[10].wakeup_ports[4].bits.uop.taken, io.wakeup_ports[4].bits.uop.taken connect issue_slots[10].wakeup_ports[4].bits.uop.pc_lob, io.wakeup_ports[4].bits.uop.pc_lob connect issue_slots[10].wakeup_ports[4].bits.uop.edge_inst, io.wakeup_ports[4].bits.uop.edge_inst connect issue_slots[10].wakeup_ports[4].bits.uop.ftq_idx, io.wakeup_ports[4].bits.uop.ftq_idx connect issue_slots[10].wakeup_ports[4].bits.uop.is_mov, io.wakeup_ports[4].bits.uop.is_mov connect issue_slots[10].wakeup_ports[4].bits.uop.is_rocc, io.wakeup_ports[4].bits.uop.is_rocc connect issue_slots[10].wakeup_ports[4].bits.uop.is_sys_pc2epc, io.wakeup_ports[4].bits.uop.is_sys_pc2epc connect issue_slots[10].wakeup_ports[4].bits.uop.is_eret, io.wakeup_ports[4].bits.uop.is_eret connect issue_slots[10].wakeup_ports[4].bits.uop.is_amo, io.wakeup_ports[4].bits.uop.is_amo connect issue_slots[10].wakeup_ports[4].bits.uop.is_sfence, io.wakeup_ports[4].bits.uop.is_sfence connect issue_slots[10].wakeup_ports[4].bits.uop.is_fencei, io.wakeup_ports[4].bits.uop.is_fencei connect issue_slots[10].wakeup_ports[4].bits.uop.is_fence, io.wakeup_ports[4].bits.uop.is_fence connect issue_slots[10].wakeup_ports[4].bits.uop.is_sfb, io.wakeup_ports[4].bits.uop.is_sfb connect issue_slots[10].wakeup_ports[4].bits.uop.br_type, io.wakeup_ports[4].bits.uop.br_type connect issue_slots[10].wakeup_ports[4].bits.uop.br_tag, io.wakeup_ports[4].bits.uop.br_tag connect issue_slots[10].wakeup_ports[4].bits.uop.br_mask, io.wakeup_ports[4].bits.uop.br_mask connect issue_slots[10].wakeup_ports[4].bits.uop.dis_col_sel, io.wakeup_ports[4].bits.uop.dis_col_sel connect issue_slots[10].wakeup_ports[4].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect issue_slots[10].wakeup_ports[4].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect issue_slots[10].wakeup_ports[4].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect issue_slots[10].wakeup_ports[4].bits.uop.iw_p2_speculative_child, io.wakeup_ports[4].bits.uop.iw_p2_speculative_child connect issue_slots[10].wakeup_ports[4].bits.uop.iw_p1_speculative_child, io.wakeup_ports[4].bits.uop.iw_p1_speculative_child connect issue_slots[10].wakeup_ports[4].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect issue_slots[10].wakeup_ports[4].bits.uop.iw_issued_partial_agen, io.wakeup_ports[4].bits.uop.iw_issued_partial_agen connect issue_slots[10].wakeup_ports[4].bits.uop.iw_issued, io.wakeup_ports[4].bits.uop.iw_issued connect issue_slots[10].wakeup_ports[4].bits.uop.fu_code[0], io.wakeup_ports[4].bits.uop.fu_code[0] connect issue_slots[10].wakeup_ports[4].bits.uop.fu_code[1], io.wakeup_ports[4].bits.uop.fu_code[1] connect issue_slots[10].wakeup_ports[4].bits.uop.fu_code[2], io.wakeup_ports[4].bits.uop.fu_code[2] connect issue_slots[10].wakeup_ports[4].bits.uop.fu_code[3], io.wakeup_ports[4].bits.uop.fu_code[3] connect issue_slots[10].wakeup_ports[4].bits.uop.fu_code[4], io.wakeup_ports[4].bits.uop.fu_code[4] connect issue_slots[10].wakeup_ports[4].bits.uop.fu_code[5], io.wakeup_ports[4].bits.uop.fu_code[5] connect issue_slots[10].wakeup_ports[4].bits.uop.fu_code[6], io.wakeup_ports[4].bits.uop.fu_code[6] connect issue_slots[10].wakeup_ports[4].bits.uop.fu_code[7], io.wakeup_ports[4].bits.uop.fu_code[7] connect issue_slots[10].wakeup_ports[4].bits.uop.fu_code[8], io.wakeup_ports[4].bits.uop.fu_code[8] connect issue_slots[10].wakeup_ports[4].bits.uop.fu_code[9], io.wakeup_ports[4].bits.uop.fu_code[9] connect issue_slots[10].wakeup_ports[4].bits.uop.iq_type[0], io.wakeup_ports[4].bits.uop.iq_type[0] connect issue_slots[10].wakeup_ports[4].bits.uop.iq_type[1], io.wakeup_ports[4].bits.uop.iq_type[1] connect issue_slots[10].wakeup_ports[4].bits.uop.iq_type[2], io.wakeup_ports[4].bits.uop.iq_type[2] connect issue_slots[10].wakeup_ports[4].bits.uop.iq_type[3], io.wakeup_ports[4].bits.uop.iq_type[3] connect issue_slots[10].wakeup_ports[4].bits.uop.debug_pc, io.wakeup_ports[4].bits.uop.debug_pc connect issue_slots[10].wakeup_ports[4].bits.uop.is_rvc, io.wakeup_ports[4].bits.uop.is_rvc connect issue_slots[10].wakeup_ports[4].bits.uop.debug_inst, io.wakeup_ports[4].bits.uop.debug_inst connect issue_slots[10].wakeup_ports[4].bits.uop.inst, io.wakeup_ports[4].bits.uop.inst connect issue_slots[10].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[10].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[10].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[10].child_rebusys, io.child_rebusys connect issue_slots[10].squash_grant, io.squash_grant connect issue_slots[10].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[10].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[10].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[10].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[10].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[10].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[10].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[10].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[10].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[10].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[10].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[10].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[10].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[10].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect issue_slots[10].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect issue_slots[10].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[10].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect issue_slots[10].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect issue_slots[10].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[10].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[10].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[10].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[10].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[10].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[10].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[10].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[10].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[10].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect issue_slots[10].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[10].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[10].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[10].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[10].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[10].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[10].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[10].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[10].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[10].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[10].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[10].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[10].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[10].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[10].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[10].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[10].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[10].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[10].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[10].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[10].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[10].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[10].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[10].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect issue_slots[10].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect issue_slots[10].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect issue_slots[10].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect issue_slots[10].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect issue_slots[10].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect issue_slots[10].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect issue_slots[10].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect issue_slots[10].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect issue_slots[10].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect issue_slots[10].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect issue_slots[10].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect issue_slots[10].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect issue_slots[10].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect issue_slots[10].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect issue_slots[10].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect issue_slots[10].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect issue_slots[10].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect issue_slots[10].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect issue_slots[10].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[10].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect issue_slots[10].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect issue_slots[10].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect issue_slots[10].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[10].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[10].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[10].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[10].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect issue_slots[10].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect issue_slots[10].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[10].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect issue_slots[10].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[10].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect issue_slots[10].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[10].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[10].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[10].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect issue_slots[10].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[10].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[10].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect issue_slots[10].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect issue_slots[10].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect issue_slots[10].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect issue_slots[10].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect issue_slots[10].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect issue_slots[10].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect issue_slots[10].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect issue_slots[10].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect issue_slots[10].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect issue_slots[10].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect issue_slots[10].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect issue_slots[10].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect issue_slots[10].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect issue_slots[10].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect issue_slots[10].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect issue_slots[10].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect issue_slots[10].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect issue_slots[10].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect issue_slots[10].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect issue_slots[10].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect issue_slots[10].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect issue_slots[10].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect issue_slots[10].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[10].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[10].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[10].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[10].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[10].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[10].kill, io.flush_pipeline connect issue_slots[11].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy connect issue_slots[11].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask connect issue_slots[11].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable connect issue_slots[11].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc connect issue_slots[11].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc connect issue_slots[11].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if connect issue_slots[11].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if connect issue_slots[11].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if connect issue_slots[11].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if connect issue_slots[11].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if connect issue_slots[11].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ connect issue_slots[11].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm connect issue_slots[11].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val connect issue_slots[11].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op connect issue_slots[11].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw connect issue_slots[11].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en connect issue_slots[11].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype connect issue_slots[11].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype connect issue_slots[11].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype connect issue_slots[11].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 connect issue_slots[11].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 connect issue_slots[11].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 connect issue_slots[11].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst connect issue_slots[11].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 connect issue_slots[11].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd connect issue_slots[11].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit connect issue_slots[11].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique connect issue_slots[11].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq connect issue_slots[11].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq connect issue_slots[11].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed connect issue_slots[11].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size connect issue_slots[11].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd connect issue_slots[11].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause connect issue_slots[11].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception connect issue_slots[11].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst connect issue_slots[11].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy connect issue_slots[11].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy connect issue_slots[11].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy connect issue_slots[11].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy connect issue_slots[11].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred connect issue_slots[11].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 connect issue_slots[11].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 connect issue_slots[11].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 connect issue_slots[11].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst connect issue_slots[11].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx connect issue_slots[11].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx connect issue_slots[11].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx connect issue_slots[11].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst connect issue_slots[11].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel connect issue_slots[11].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel connect issue_slots[11].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed connect issue_slots[11].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm connect issue_slots[11].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel connect issue_slots[11].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename connect issue_slots[11].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken connect issue_slots[11].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob connect issue_slots[11].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst connect issue_slots[11].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx connect issue_slots[11].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov connect issue_slots[11].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc connect issue_slots[11].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc connect issue_slots[11].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret connect issue_slots[11].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo connect issue_slots[11].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence connect issue_slots[11].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei connect issue_slots[11].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence connect issue_slots[11].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb connect issue_slots[11].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type connect issue_slots[11].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag connect issue_slots[11].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask connect issue_slots[11].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel connect issue_slots[11].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect issue_slots[11].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect issue_slots[11].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect issue_slots[11].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child connect issue_slots[11].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child connect issue_slots[11].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect issue_slots[11].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen connect issue_slots[11].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued connect issue_slots[11].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] connect issue_slots[11].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] connect issue_slots[11].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] connect issue_slots[11].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] connect issue_slots[11].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] connect issue_slots[11].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] connect issue_slots[11].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] connect issue_slots[11].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] connect issue_slots[11].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] connect issue_slots[11].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] connect issue_slots[11].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] connect issue_slots[11].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] connect issue_slots[11].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] connect issue_slots[11].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] connect issue_slots[11].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc connect issue_slots[11].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc connect issue_slots[11].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst connect issue_slots[11].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst connect issue_slots[11].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[11].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy connect issue_slots[11].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask connect issue_slots[11].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable connect issue_slots[11].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc connect issue_slots[11].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc connect issue_slots[11].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if connect issue_slots[11].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if connect issue_slots[11].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if connect issue_slots[11].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if connect issue_slots[11].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if connect issue_slots[11].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ connect issue_slots[11].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm connect issue_slots[11].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val connect issue_slots[11].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op connect issue_slots[11].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw connect issue_slots[11].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en connect issue_slots[11].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype connect issue_slots[11].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype connect issue_slots[11].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype connect issue_slots[11].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 connect issue_slots[11].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 connect issue_slots[11].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 connect issue_slots[11].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst connect issue_slots[11].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 connect issue_slots[11].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd connect issue_slots[11].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit connect issue_slots[11].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique connect issue_slots[11].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq connect issue_slots[11].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq connect issue_slots[11].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed connect issue_slots[11].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size connect issue_slots[11].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd connect issue_slots[11].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause connect issue_slots[11].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception connect issue_slots[11].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst connect issue_slots[11].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy connect issue_slots[11].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy connect issue_slots[11].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy connect issue_slots[11].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy connect issue_slots[11].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred connect issue_slots[11].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 connect issue_slots[11].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 connect issue_slots[11].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 connect issue_slots[11].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst connect issue_slots[11].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx connect issue_slots[11].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx connect issue_slots[11].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx connect issue_slots[11].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst connect issue_slots[11].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel connect issue_slots[11].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel connect issue_slots[11].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed connect issue_slots[11].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm connect issue_slots[11].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel connect issue_slots[11].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename connect issue_slots[11].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken connect issue_slots[11].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob connect issue_slots[11].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst connect issue_slots[11].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx connect issue_slots[11].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov connect issue_slots[11].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc connect issue_slots[11].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc connect issue_slots[11].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret connect issue_slots[11].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo connect issue_slots[11].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence connect issue_slots[11].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei connect issue_slots[11].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence connect issue_slots[11].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb connect issue_slots[11].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type connect issue_slots[11].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag connect issue_slots[11].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask connect issue_slots[11].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel connect issue_slots[11].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect issue_slots[11].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect issue_slots[11].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect issue_slots[11].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child connect issue_slots[11].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child connect issue_slots[11].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect issue_slots[11].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen connect issue_slots[11].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued connect issue_slots[11].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] connect issue_slots[11].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] connect issue_slots[11].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] connect issue_slots[11].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] connect issue_slots[11].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] connect issue_slots[11].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] connect issue_slots[11].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] connect issue_slots[11].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] connect issue_slots[11].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] connect issue_slots[11].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] connect issue_slots[11].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] connect issue_slots[11].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] connect issue_slots[11].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] connect issue_slots[11].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] connect issue_slots[11].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc connect issue_slots[11].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc connect issue_slots[11].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst connect issue_slots[11].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst connect issue_slots[11].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[11].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy connect issue_slots[11].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask connect issue_slots[11].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable connect issue_slots[11].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc connect issue_slots[11].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc connect issue_slots[11].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if connect issue_slots[11].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if connect issue_slots[11].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if connect issue_slots[11].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if connect issue_slots[11].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if connect issue_slots[11].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ connect issue_slots[11].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm connect issue_slots[11].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val connect issue_slots[11].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op connect issue_slots[11].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw connect issue_slots[11].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en connect issue_slots[11].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype connect issue_slots[11].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype connect issue_slots[11].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype connect issue_slots[11].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3 connect issue_slots[11].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2 connect issue_slots[11].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1 connect issue_slots[11].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst connect issue_slots[11].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1 connect issue_slots[11].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd connect issue_slots[11].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit connect issue_slots[11].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique connect issue_slots[11].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq connect issue_slots[11].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq connect issue_slots[11].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed connect issue_slots[11].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size connect issue_slots[11].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd connect issue_slots[11].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause connect issue_slots[11].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception connect issue_slots[11].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst connect issue_slots[11].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy connect issue_slots[11].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy connect issue_slots[11].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy connect issue_slots[11].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy connect issue_slots[11].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred connect issue_slots[11].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3 connect issue_slots[11].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2 connect issue_slots[11].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1 connect issue_slots[11].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst connect issue_slots[11].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx connect issue_slots[11].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx connect issue_slots[11].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx connect issue_slots[11].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen connect issue_slots[11].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst connect issue_slots[11].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel connect issue_slots[11].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel connect issue_slots[11].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed connect issue_slots[11].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm connect issue_slots[11].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel connect issue_slots[11].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename connect issue_slots[11].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken connect issue_slots[11].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob connect issue_slots[11].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst connect issue_slots[11].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx connect issue_slots[11].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov connect issue_slots[11].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc connect issue_slots[11].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc connect issue_slots[11].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret connect issue_slots[11].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo connect issue_slots[11].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence connect issue_slots[11].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei connect issue_slots[11].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence connect issue_slots[11].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb connect issue_slots[11].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type connect issue_slots[11].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag connect issue_slots[11].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask connect issue_slots[11].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel connect issue_slots[11].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect issue_slots[11].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect issue_slots[11].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect issue_slots[11].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child connect issue_slots[11].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child connect issue_slots[11].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect issue_slots[11].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen connect issue_slots[11].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued connect issue_slots[11].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0] connect issue_slots[11].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1] connect issue_slots[11].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2] connect issue_slots[11].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3] connect issue_slots[11].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4] connect issue_slots[11].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5] connect issue_slots[11].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6] connect issue_slots[11].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7] connect issue_slots[11].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8] connect issue_slots[11].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9] connect issue_slots[11].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0] connect issue_slots[11].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1] connect issue_slots[11].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2] connect issue_slots[11].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3] connect issue_slots[11].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc connect issue_slots[11].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc connect issue_slots[11].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst connect issue_slots[11].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst connect issue_slots[11].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[11].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy connect issue_slots[11].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask connect issue_slots[11].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable connect issue_slots[11].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc connect issue_slots[11].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc connect issue_slots[11].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if connect issue_slots[11].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if connect issue_slots[11].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if connect issue_slots[11].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if connect issue_slots[11].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if connect issue_slots[11].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ connect issue_slots[11].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm connect issue_slots[11].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val connect issue_slots[11].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op connect issue_slots[11].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw connect issue_slots[11].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en connect issue_slots[11].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype connect issue_slots[11].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype connect issue_slots[11].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype connect issue_slots[11].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3 connect issue_slots[11].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2 connect issue_slots[11].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1 connect issue_slots[11].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst connect issue_slots[11].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1 connect issue_slots[11].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd connect issue_slots[11].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit connect issue_slots[11].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique connect issue_slots[11].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq connect issue_slots[11].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq connect issue_slots[11].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed connect issue_slots[11].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size connect issue_slots[11].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd connect issue_slots[11].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause connect issue_slots[11].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception connect issue_slots[11].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst connect issue_slots[11].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy connect issue_slots[11].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy connect issue_slots[11].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy connect issue_slots[11].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy connect issue_slots[11].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred connect issue_slots[11].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3 connect issue_slots[11].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2 connect issue_slots[11].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1 connect issue_slots[11].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst connect issue_slots[11].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx connect issue_slots[11].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx connect issue_slots[11].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx connect issue_slots[11].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen connect issue_slots[11].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst connect issue_slots[11].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel connect issue_slots[11].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel connect issue_slots[11].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed connect issue_slots[11].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm connect issue_slots[11].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel connect issue_slots[11].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename connect issue_slots[11].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken connect issue_slots[11].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob connect issue_slots[11].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst connect issue_slots[11].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx connect issue_slots[11].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov connect issue_slots[11].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc connect issue_slots[11].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc connect issue_slots[11].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret connect issue_slots[11].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo connect issue_slots[11].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence connect issue_slots[11].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei connect issue_slots[11].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence connect issue_slots[11].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb connect issue_slots[11].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type connect issue_slots[11].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag connect issue_slots[11].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask connect issue_slots[11].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel connect issue_slots[11].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect issue_slots[11].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect issue_slots[11].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect issue_slots[11].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child connect issue_slots[11].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child connect issue_slots[11].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect issue_slots[11].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen connect issue_slots[11].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued connect issue_slots[11].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0] connect issue_slots[11].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1] connect issue_slots[11].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2] connect issue_slots[11].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3] connect issue_slots[11].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4] connect issue_slots[11].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5] connect issue_slots[11].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6] connect issue_slots[11].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7] connect issue_slots[11].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8] connect issue_slots[11].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9] connect issue_slots[11].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0] connect issue_slots[11].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1] connect issue_slots[11].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2] connect issue_slots[11].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3] connect issue_slots[11].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc connect issue_slots[11].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc connect issue_slots[11].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst connect issue_slots[11].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst connect issue_slots[11].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[11].wakeup_ports[4].bits.rebusy, io.wakeup_ports[4].bits.rebusy connect issue_slots[11].wakeup_ports[4].bits.speculative_mask, io.wakeup_ports[4].bits.speculative_mask connect issue_slots[11].wakeup_ports[4].bits.bypassable, io.wakeup_ports[4].bits.bypassable connect issue_slots[11].wakeup_ports[4].bits.uop.debug_tsrc, io.wakeup_ports[4].bits.uop.debug_tsrc connect issue_slots[11].wakeup_ports[4].bits.uop.debug_fsrc, io.wakeup_ports[4].bits.uop.debug_fsrc connect issue_slots[11].wakeup_ports[4].bits.uop.bp_xcpt_if, io.wakeup_ports[4].bits.uop.bp_xcpt_if connect issue_slots[11].wakeup_ports[4].bits.uop.bp_debug_if, io.wakeup_ports[4].bits.uop.bp_debug_if connect issue_slots[11].wakeup_ports[4].bits.uop.xcpt_ma_if, io.wakeup_ports[4].bits.uop.xcpt_ma_if connect issue_slots[11].wakeup_ports[4].bits.uop.xcpt_ae_if, io.wakeup_ports[4].bits.uop.xcpt_ae_if connect issue_slots[11].wakeup_ports[4].bits.uop.xcpt_pf_if, io.wakeup_ports[4].bits.uop.xcpt_pf_if connect issue_slots[11].wakeup_ports[4].bits.uop.fp_typ, io.wakeup_ports[4].bits.uop.fp_typ connect issue_slots[11].wakeup_ports[4].bits.uop.fp_rm, io.wakeup_ports[4].bits.uop.fp_rm connect issue_slots[11].wakeup_ports[4].bits.uop.fp_val, io.wakeup_ports[4].bits.uop.fp_val connect issue_slots[11].wakeup_ports[4].bits.uop.fcn_op, io.wakeup_ports[4].bits.uop.fcn_op connect issue_slots[11].wakeup_ports[4].bits.uop.fcn_dw, io.wakeup_ports[4].bits.uop.fcn_dw connect issue_slots[11].wakeup_ports[4].bits.uop.frs3_en, io.wakeup_ports[4].bits.uop.frs3_en connect issue_slots[11].wakeup_ports[4].bits.uop.lrs2_rtype, io.wakeup_ports[4].bits.uop.lrs2_rtype connect issue_slots[11].wakeup_ports[4].bits.uop.lrs1_rtype, io.wakeup_ports[4].bits.uop.lrs1_rtype connect issue_slots[11].wakeup_ports[4].bits.uop.dst_rtype, io.wakeup_ports[4].bits.uop.dst_rtype connect issue_slots[11].wakeup_ports[4].bits.uop.lrs3, io.wakeup_ports[4].bits.uop.lrs3 connect issue_slots[11].wakeup_ports[4].bits.uop.lrs2, io.wakeup_ports[4].bits.uop.lrs2 connect issue_slots[11].wakeup_ports[4].bits.uop.lrs1, io.wakeup_ports[4].bits.uop.lrs1 connect issue_slots[11].wakeup_ports[4].bits.uop.ldst, io.wakeup_ports[4].bits.uop.ldst connect issue_slots[11].wakeup_ports[4].bits.uop.ldst_is_rs1, io.wakeup_ports[4].bits.uop.ldst_is_rs1 connect issue_slots[11].wakeup_ports[4].bits.uop.csr_cmd, io.wakeup_ports[4].bits.uop.csr_cmd connect issue_slots[11].wakeup_ports[4].bits.uop.flush_on_commit, io.wakeup_ports[4].bits.uop.flush_on_commit connect issue_slots[11].wakeup_ports[4].bits.uop.is_unique, io.wakeup_ports[4].bits.uop.is_unique connect issue_slots[11].wakeup_ports[4].bits.uop.uses_stq, io.wakeup_ports[4].bits.uop.uses_stq connect issue_slots[11].wakeup_ports[4].bits.uop.uses_ldq, io.wakeup_ports[4].bits.uop.uses_ldq connect issue_slots[11].wakeup_ports[4].bits.uop.mem_signed, io.wakeup_ports[4].bits.uop.mem_signed connect issue_slots[11].wakeup_ports[4].bits.uop.mem_size, io.wakeup_ports[4].bits.uop.mem_size connect issue_slots[11].wakeup_ports[4].bits.uop.mem_cmd, io.wakeup_ports[4].bits.uop.mem_cmd connect issue_slots[11].wakeup_ports[4].bits.uop.exc_cause, io.wakeup_ports[4].bits.uop.exc_cause connect issue_slots[11].wakeup_ports[4].bits.uop.exception, io.wakeup_ports[4].bits.uop.exception connect issue_slots[11].wakeup_ports[4].bits.uop.stale_pdst, io.wakeup_ports[4].bits.uop.stale_pdst connect issue_slots[11].wakeup_ports[4].bits.uop.ppred_busy, io.wakeup_ports[4].bits.uop.ppred_busy connect issue_slots[11].wakeup_ports[4].bits.uop.prs3_busy, io.wakeup_ports[4].bits.uop.prs3_busy connect issue_slots[11].wakeup_ports[4].bits.uop.prs2_busy, io.wakeup_ports[4].bits.uop.prs2_busy connect issue_slots[11].wakeup_ports[4].bits.uop.prs1_busy, io.wakeup_ports[4].bits.uop.prs1_busy connect issue_slots[11].wakeup_ports[4].bits.uop.ppred, io.wakeup_ports[4].bits.uop.ppred connect issue_slots[11].wakeup_ports[4].bits.uop.prs3, io.wakeup_ports[4].bits.uop.prs3 connect issue_slots[11].wakeup_ports[4].bits.uop.prs2, io.wakeup_ports[4].bits.uop.prs2 connect issue_slots[11].wakeup_ports[4].bits.uop.prs1, io.wakeup_ports[4].bits.uop.prs1 connect issue_slots[11].wakeup_ports[4].bits.uop.pdst, io.wakeup_ports[4].bits.uop.pdst connect issue_slots[11].wakeup_ports[4].bits.uop.rxq_idx, io.wakeup_ports[4].bits.uop.rxq_idx connect issue_slots[11].wakeup_ports[4].bits.uop.stq_idx, io.wakeup_ports[4].bits.uop.stq_idx connect issue_slots[11].wakeup_ports[4].bits.uop.ldq_idx, io.wakeup_ports[4].bits.uop.ldq_idx connect issue_slots[11].wakeup_ports[4].bits.uop.rob_idx, io.wakeup_ports[4].bits.uop.rob_idx connect issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.vec, io.wakeup_ports[4].bits.uop.fp_ctrl.vec connect issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.wflags, io.wakeup_ports[4].bits.uop.fp_ctrl.wflags connect issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.div, io.wakeup_ports[4].bits.uop.fp_ctrl.div connect issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.fma, io.wakeup_ports[4].bits.uop.fp_ctrl.fma connect issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.toint, io.wakeup_ports[4].bits.uop.fp_ctrl.toint connect issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.fromint, io.wakeup_ports[4].bits.uop.fp_ctrl.fromint connect issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.swap23, io.wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.swap12, io.wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.ren3, io.wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.ren2, io.wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.ren1, io.wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.wen, io.wakeup_ports[4].bits.uop.fp_ctrl.wen connect issue_slots[11].wakeup_ports[4].bits.uop.fp_ctrl.ldst, io.wakeup_ports[4].bits.uop.fp_ctrl.ldst connect issue_slots[11].wakeup_ports[4].bits.uop.op2_sel, io.wakeup_ports[4].bits.uop.op2_sel connect issue_slots[11].wakeup_ports[4].bits.uop.op1_sel, io.wakeup_ports[4].bits.uop.op1_sel connect issue_slots[11].wakeup_ports[4].bits.uop.imm_packed, io.wakeup_ports[4].bits.uop.imm_packed connect issue_slots[11].wakeup_ports[4].bits.uop.pimm, io.wakeup_ports[4].bits.uop.pimm connect issue_slots[11].wakeup_ports[4].bits.uop.imm_sel, io.wakeup_ports[4].bits.uop.imm_sel connect issue_slots[11].wakeup_ports[4].bits.uop.imm_rename, io.wakeup_ports[4].bits.uop.imm_rename connect issue_slots[11].wakeup_ports[4].bits.uop.taken, io.wakeup_ports[4].bits.uop.taken connect issue_slots[11].wakeup_ports[4].bits.uop.pc_lob, io.wakeup_ports[4].bits.uop.pc_lob connect issue_slots[11].wakeup_ports[4].bits.uop.edge_inst, io.wakeup_ports[4].bits.uop.edge_inst connect issue_slots[11].wakeup_ports[4].bits.uop.ftq_idx, io.wakeup_ports[4].bits.uop.ftq_idx connect issue_slots[11].wakeup_ports[4].bits.uop.is_mov, io.wakeup_ports[4].bits.uop.is_mov connect issue_slots[11].wakeup_ports[4].bits.uop.is_rocc, io.wakeup_ports[4].bits.uop.is_rocc connect issue_slots[11].wakeup_ports[4].bits.uop.is_sys_pc2epc, io.wakeup_ports[4].bits.uop.is_sys_pc2epc connect issue_slots[11].wakeup_ports[4].bits.uop.is_eret, io.wakeup_ports[4].bits.uop.is_eret connect issue_slots[11].wakeup_ports[4].bits.uop.is_amo, io.wakeup_ports[4].bits.uop.is_amo connect issue_slots[11].wakeup_ports[4].bits.uop.is_sfence, io.wakeup_ports[4].bits.uop.is_sfence connect issue_slots[11].wakeup_ports[4].bits.uop.is_fencei, io.wakeup_ports[4].bits.uop.is_fencei connect issue_slots[11].wakeup_ports[4].bits.uop.is_fence, io.wakeup_ports[4].bits.uop.is_fence connect issue_slots[11].wakeup_ports[4].bits.uop.is_sfb, io.wakeup_ports[4].bits.uop.is_sfb connect issue_slots[11].wakeup_ports[4].bits.uop.br_type, io.wakeup_ports[4].bits.uop.br_type connect issue_slots[11].wakeup_ports[4].bits.uop.br_tag, io.wakeup_ports[4].bits.uop.br_tag connect issue_slots[11].wakeup_ports[4].bits.uop.br_mask, io.wakeup_ports[4].bits.uop.br_mask connect issue_slots[11].wakeup_ports[4].bits.uop.dis_col_sel, io.wakeup_ports[4].bits.uop.dis_col_sel connect issue_slots[11].wakeup_ports[4].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect issue_slots[11].wakeup_ports[4].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect issue_slots[11].wakeup_ports[4].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect issue_slots[11].wakeup_ports[4].bits.uop.iw_p2_speculative_child, io.wakeup_ports[4].bits.uop.iw_p2_speculative_child connect issue_slots[11].wakeup_ports[4].bits.uop.iw_p1_speculative_child, io.wakeup_ports[4].bits.uop.iw_p1_speculative_child connect issue_slots[11].wakeup_ports[4].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect issue_slots[11].wakeup_ports[4].bits.uop.iw_issued_partial_agen, io.wakeup_ports[4].bits.uop.iw_issued_partial_agen connect issue_slots[11].wakeup_ports[4].bits.uop.iw_issued, io.wakeup_ports[4].bits.uop.iw_issued connect issue_slots[11].wakeup_ports[4].bits.uop.fu_code[0], io.wakeup_ports[4].bits.uop.fu_code[0] connect issue_slots[11].wakeup_ports[4].bits.uop.fu_code[1], io.wakeup_ports[4].bits.uop.fu_code[1] connect issue_slots[11].wakeup_ports[4].bits.uop.fu_code[2], io.wakeup_ports[4].bits.uop.fu_code[2] connect issue_slots[11].wakeup_ports[4].bits.uop.fu_code[3], io.wakeup_ports[4].bits.uop.fu_code[3] connect issue_slots[11].wakeup_ports[4].bits.uop.fu_code[4], io.wakeup_ports[4].bits.uop.fu_code[4] connect issue_slots[11].wakeup_ports[4].bits.uop.fu_code[5], io.wakeup_ports[4].bits.uop.fu_code[5] connect issue_slots[11].wakeup_ports[4].bits.uop.fu_code[6], io.wakeup_ports[4].bits.uop.fu_code[6] connect issue_slots[11].wakeup_ports[4].bits.uop.fu_code[7], io.wakeup_ports[4].bits.uop.fu_code[7] connect issue_slots[11].wakeup_ports[4].bits.uop.fu_code[8], io.wakeup_ports[4].bits.uop.fu_code[8] connect issue_slots[11].wakeup_ports[4].bits.uop.fu_code[9], io.wakeup_ports[4].bits.uop.fu_code[9] connect issue_slots[11].wakeup_ports[4].bits.uop.iq_type[0], io.wakeup_ports[4].bits.uop.iq_type[0] connect issue_slots[11].wakeup_ports[4].bits.uop.iq_type[1], io.wakeup_ports[4].bits.uop.iq_type[1] connect issue_slots[11].wakeup_ports[4].bits.uop.iq_type[2], io.wakeup_ports[4].bits.uop.iq_type[2] connect issue_slots[11].wakeup_ports[4].bits.uop.iq_type[3], io.wakeup_ports[4].bits.uop.iq_type[3] connect issue_slots[11].wakeup_ports[4].bits.uop.debug_pc, io.wakeup_ports[4].bits.uop.debug_pc connect issue_slots[11].wakeup_ports[4].bits.uop.is_rvc, io.wakeup_ports[4].bits.uop.is_rvc connect issue_slots[11].wakeup_ports[4].bits.uop.debug_inst, io.wakeup_ports[4].bits.uop.debug_inst connect issue_slots[11].wakeup_ports[4].bits.uop.inst, io.wakeup_ports[4].bits.uop.inst connect issue_slots[11].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[11].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[11].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[11].child_rebusys, io.child_rebusys connect issue_slots[11].squash_grant, io.squash_grant connect issue_slots[11].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[11].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[11].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[11].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[11].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[11].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[11].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[11].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[11].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[11].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[11].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[11].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[11].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[11].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect issue_slots[11].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect issue_slots[11].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[11].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect issue_slots[11].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect issue_slots[11].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[11].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[11].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[11].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[11].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[11].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[11].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[11].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[11].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[11].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect issue_slots[11].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[11].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[11].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[11].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[11].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[11].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[11].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[11].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[11].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[11].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[11].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[11].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[11].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[11].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[11].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[11].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[11].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[11].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[11].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[11].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[11].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[11].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[11].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[11].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect issue_slots[11].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect issue_slots[11].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect issue_slots[11].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect issue_slots[11].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect issue_slots[11].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect issue_slots[11].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect issue_slots[11].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect issue_slots[11].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect issue_slots[11].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect issue_slots[11].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect issue_slots[11].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect issue_slots[11].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect issue_slots[11].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect issue_slots[11].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect issue_slots[11].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect issue_slots[11].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect issue_slots[11].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect issue_slots[11].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect issue_slots[11].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[11].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect issue_slots[11].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect issue_slots[11].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect issue_slots[11].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[11].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[11].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[11].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[11].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect issue_slots[11].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect issue_slots[11].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[11].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect issue_slots[11].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[11].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect issue_slots[11].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[11].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[11].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[11].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect issue_slots[11].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[11].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[11].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect issue_slots[11].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect issue_slots[11].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect issue_slots[11].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect issue_slots[11].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect issue_slots[11].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect issue_slots[11].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect issue_slots[11].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect issue_slots[11].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect issue_slots[11].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect issue_slots[11].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect issue_slots[11].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect issue_slots[11].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect issue_slots[11].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect issue_slots[11].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect issue_slots[11].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect issue_slots[11].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect issue_slots[11].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect issue_slots[11].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect issue_slots[11].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect issue_slots[11].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect issue_slots[11].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect issue_slots[11].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect issue_slots[11].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[11].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[11].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[11].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[11].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[11].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[11].kill, io.flush_pipeline connect issue_slots[12].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy connect issue_slots[12].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask connect issue_slots[12].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable connect issue_slots[12].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc connect issue_slots[12].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc connect issue_slots[12].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if connect issue_slots[12].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if connect issue_slots[12].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if connect issue_slots[12].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if connect issue_slots[12].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if connect issue_slots[12].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ connect issue_slots[12].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm connect issue_slots[12].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val connect issue_slots[12].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op connect issue_slots[12].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw connect issue_slots[12].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en connect issue_slots[12].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype connect issue_slots[12].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype connect issue_slots[12].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype connect issue_slots[12].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 connect issue_slots[12].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 connect issue_slots[12].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 connect issue_slots[12].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst connect issue_slots[12].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 connect issue_slots[12].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd connect issue_slots[12].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit connect issue_slots[12].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique connect issue_slots[12].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq connect issue_slots[12].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq connect issue_slots[12].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed connect issue_slots[12].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size connect issue_slots[12].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd connect issue_slots[12].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause connect issue_slots[12].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception connect issue_slots[12].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst connect issue_slots[12].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy connect issue_slots[12].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy connect issue_slots[12].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy connect issue_slots[12].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy connect issue_slots[12].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred connect issue_slots[12].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 connect issue_slots[12].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 connect issue_slots[12].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 connect issue_slots[12].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst connect issue_slots[12].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx connect issue_slots[12].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx connect issue_slots[12].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx connect issue_slots[12].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen connect issue_slots[12].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst connect issue_slots[12].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel connect issue_slots[12].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel connect issue_slots[12].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed connect issue_slots[12].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm connect issue_slots[12].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel connect issue_slots[12].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename connect issue_slots[12].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken connect issue_slots[12].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob connect issue_slots[12].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst connect issue_slots[12].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx connect issue_slots[12].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov connect issue_slots[12].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc connect issue_slots[12].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc connect issue_slots[12].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret connect issue_slots[12].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo connect issue_slots[12].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence connect issue_slots[12].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei connect issue_slots[12].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence connect issue_slots[12].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb connect issue_slots[12].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type connect issue_slots[12].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag connect issue_slots[12].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask connect issue_slots[12].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel connect issue_slots[12].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect issue_slots[12].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect issue_slots[12].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect issue_slots[12].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child connect issue_slots[12].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child connect issue_slots[12].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect issue_slots[12].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen connect issue_slots[12].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued connect issue_slots[12].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] connect issue_slots[12].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] connect issue_slots[12].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] connect issue_slots[12].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] connect issue_slots[12].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] connect issue_slots[12].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] connect issue_slots[12].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] connect issue_slots[12].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] connect issue_slots[12].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] connect issue_slots[12].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] connect issue_slots[12].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] connect issue_slots[12].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] connect issue_slots[12].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] connect issue_slots[12].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] connect issue_slots[12].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc connect issue_slots[12].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc connect issue_slots[12].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst connect issue_slots[12].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst connect issue_slots[12].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[12].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy connect issue_slots[12].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask connect issue_slots[12].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable connect issue_slots[12].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc connect issue_slots[12].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc connect issue_slots[12].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if connect issue_slots[12].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if connect issue_slots[12].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if connect issue_slots[12].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if connect issue_slots[12].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if connect issue_slots[12].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ connect issue_slots[12].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm connect issue_slots[12].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val connect issue_slots[12].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op connect issue_slots[12].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw connect issue_slots[12].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en connect issue_slots[12].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype connect issue_slots[12].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype connect issue_slots[12].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype connect issue_slots[12].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 connect issue_slots[12].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 connect issue_slots[12].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 connect issue_slots[12].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst connect issue_slots[12].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 connect issue_slots[12].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd connect issue_slots[12].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit connect issue_slots[12].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique connect issue_slots[12].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq connect issue_slots[12].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq connect issue_slots[12].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed connect issue_slots[12].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size connect issue_slots[12].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd connect issue_slots[12].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause connect issue_slots[12].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception connect issue_slots[12].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst connect issue_slots[12].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy connect issue_slots[12].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy connect issue_slots[12].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy connect issue_slots[12].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy connect issue_slots[12].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred connect issue_slots[12].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 connect issue_slots[12].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 connect issue_slots[12].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 connect issue_slots[12].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst connect issue_slots[12].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx connect issue_slots[12].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx connect issue_slots[12].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx connect issue_slots[12].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen connect issue_slots[12].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst connect issue_slots[12].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel connect issue_slots[12].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel connect issue_slots[12].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed connect issue_slots[12].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm connect issue_slots[12].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel connect issue_slots[12].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename connect issue_slots[12].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken connect issue_slots[12].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob connect issue_slots[12].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst connect issue_slots[12].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx connect issue_slots[12].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov connect issue_slots[12].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc connect issue_slots[12].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc connect issue_slots[12].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret connect issue_slots[12].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo connect issue_slots[12].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence connect issue_slots[12].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei connect issue_slots[12].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence connect issue_slots[12].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb connect issue_slots[12].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type connect issue_slots[12].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag connect issue_slots[12].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask connect issue_slots[12].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel connect issue_slots[12].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect issue_slots[12].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect issue_slots[12].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect issue_slots[12].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child connect issue_slots[12].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child connect issue_slots[12].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect issue_slots[12].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen connect issue_slots[12].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued connect issue_slots[12].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] connect issue_slots[12].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] connect issue_slots[12].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] connect issue_slots[12].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] connect issue_slots[12].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] connect issue_slots[12].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] connect issue_slots[12].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] connect issue_slots[12].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] connect issue_slots[12].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] connect issue_slots[12].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] connect issue_slots[12].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] connect issue_slots[12].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] connect issue_slots[12].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] connect issue_slots[12].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] connect issue_slots[12].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc connect issue_slots[12].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc connect issue_slots[12].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst connect issue_slots[12].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst connect issue_slots[12].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[12].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy connect issue_slots[12].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask connect issue_slots[12].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable connect issue_slots[12].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc connect issue_slots[12].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc connect issue_slots[12].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if connect issue_slots[12].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if connect issue_slots[12].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if connect issue_slots[12].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if connect issue_slots[12].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if connect issue_slots[12].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ connect issue_slots[12].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm connect issue_slots[12].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val connect issue_slots[12].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op connect issue_slots[12].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw connect issue_slots[12].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en connect issue_slots[12].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype connect issue_slots[12].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype connect issue_slots[12].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype connect issue_slots[12].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3 connect issue_slots[12].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2 connect issue_slots[12].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1 connect issue_slots[12].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst connect issue_slots[12].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1 connect issue_slots[12].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd connect issue_slots[12].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit connect issue_slots[12].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique connect issue_slots[12].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq connect issue_slots[12].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq connect issue_slots[12].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed connect issue_slots[12].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size connect issue_slots[12].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd connect issue_slots[12].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause connect issue_slots[12].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception connect issue_slots[12].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst connect issue_slots[12].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy connect issue_slots[12].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy connect issue_slots[12].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy connect issue_slots[12].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy connect issue_slots[12].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred connect issue_slots[12].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3 connect issue_slots[12].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2 connect issue_slots[12].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1 connect issue_slots[12].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst connect issue_slots[12].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx connect issue_slots[12].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx connect issue_slots[12].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx connect issue_slots[12].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen connect issue_slots[12].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst connect issue_slots[12].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel connect issue_slots[12].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel connect issue_slots[12].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed connect issue_slots[12].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm connect issue_slots[12].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel connect issue_slots[12].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename connect issue_slots[12].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken connect issue_slots[12].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob connect issue_slots[12].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst connect issue_slots[12].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx connect issue_slots[12].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov connect issue_slots[12].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc connect issue_slots[12].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc connect issue_slots[12].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret connect issue_slots[12].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo connect issue_slots[12].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence connect issue_slots[12].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei connect issue_slots[12].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence connect issue_slots[12].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb connect issue_slots[12].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type connect issue_slots[12].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag connect issue_slots[12].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask connect issue_slots[12].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel connect issue_slots[12].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect issue_slots[12].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect issue_slots[12].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect issue_slots[12].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child connect issue_slots[12].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child connect issue_slots[12].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect issue_slots[12].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen connect issue_slots[12].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued connect issue_slots[12].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0] connect issue_slots[12].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1] connect issue_slots[12].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2] connect issue_slots[12].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3] connect issue_slots[12].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4] connect issue_slots[12].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5] connect issue_slots[12].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6] connect issue_slots[12].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7] connect issue_slots[12].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8] connect issue_slots[12].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9] connect issue_slots[12].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0] connect issue_slots[12].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1] connect issue_slots[12].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2] connect issue_slots[12].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3] connect issue_slots[12].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc connect issue_slots[12].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc connect issue_slots[12].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst connect issue_slots[12].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst connect issue_slots[12].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[12].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy connect issue_slots[12].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask connect issue_slots[12].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable connect issue_slots[12].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc connect issue_slots[12].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc connect issue_slots[12].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if connect issue_slots[12].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if connect issue_slots[12].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if connect issue_slots[12].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if connect issue_slots[12].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if connect issue_slots[12].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ connect issue_slots[12].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm connect issue_slots[12].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val connect issue_slots[12].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op connect issue_slots[12].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw connect issue_slots[12].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en connect issue_slots[12].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype connect issue_slots[12].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype connect issue_slots[12].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype connect issue_slots[12].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3 connect issue_slots[12].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2 connect issue_slots[12].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1 connect issue_slots[12].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst connect issue_slots[12].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1 connect issue_slots[12].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd connect issue_slots[12].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit connect issue_slots[12].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique connect issue_slots[12].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq connect issue_slots[12].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq connect issue_slots[12].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed connect issue_slots[12].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size connect issue_slots[12].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd connect issue_slots[12].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause connect issue_slots[12].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception connect issue_slots[12].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst connect issue_slots[12].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy connect issue_slots[12].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy connect issue_slots[12].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy connect issue_slots[12].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy connect issue_slots[12].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred connect issue_slots[12].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3 connect issue_slots[12].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2 connect issue_slots[12].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1 connect issue_slots[12].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst connect issue_slots[12].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx connect issue_slots[12].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx connect issue_slots[12].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx connect issue_slots[12].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen connect issue_slots[12].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst connect issue_slots[12].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel connect issue_slots[12].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel connect issue_slots[12].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed connect issue_slots[12].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm connect issue_slots[12].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel connect issue_slots[12].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename connect issue_slots[12].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken connect issue_slots[12].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob connect issue_slots[12].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst connect issue_slots[12].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx connect issue_slots[12].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov connect issue_slots[12].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc connect issue_slots[12].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc connect issue_slots[12].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret connect issue_slots[12].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo connect issue_slots[12].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence connect issue_slots[12].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei connect issue_slots[12].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence connect issue_slots[12].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb connect issue_slots[12].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type connect issue_slots[12].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag connect issue_slots[12].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask connect issue_slots[12].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel connect issue_slots[12].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect issue_slots[12].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect issue_slots[12].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect issue_slots[12].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child connect issue_slots[12].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child connect issue_slots[12].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect issue_slots[12].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen connect issue_slots[12].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued connect issue_slots[12].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0] connect issue_slots[12].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1] connect issue_slots[12].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2] connect issue_slots[12].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3] connect issue_slots[12].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4] connect issue_slots[12].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5] connect issue_slots[12].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6] connect issue_slots[12].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7] connect issue_slots[12].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8] connect issue_slots[12].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9] connect issue_slots[12].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0] connect issue_slots[12].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1] connect issue_slots[12].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2] connect issue_slots[12].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3] connect issue_slots[12].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc connect issue_slots[12].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc connect issue_slots[12].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst connect issue_slots[12].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst connect issue_slots[12].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[12].wakeup_ports[4].bits.rebusy, io.wakeup_ports[4].bits.rebusy connect issue_slots[12].wakeup_ports[4].bits.speculative_mask, io.wakeup_ports[4].bits.speculative_mask connect issue_slots[12].wakeup_ports[4].bits.bypassable, io.wakeup_ports[4].bits.bypassable connect issue_slots[12].wakeup_ports[4].bits.uop.debug_tsrc, io.wakeup_ports[4].bits.uop.debug_tsrc connect issue_slots[12].wakeup_ports[4].bits.uop.debug_fsrc, io.wakeup_ports[4].bits.uop.debug_fsrc connect issue_slots[12].wakeup_ports[4].bits.uop.bp_xcpt_if, io.wakeup_ports[4].bits.uop.bp_xcpt_if connect issue_slots[12].wakeup_ports[4].bits.uop.bp_debug_if, io.wakeup_ports[4].bits.uop.bp_debug_if connect issue_slots[12].wakeup_ports[4].bits.uop.xcpt_ma_if, io.wakeup_ports[4].bits.uop.xcpt_ma_if connect issue_slots[12].wakeup_ports[4].bits.uop.xcpt_ae_if, io.wakeup_ports[4].bits.uop.xcpt_ae_if connect issue_slots[12].wakeup_ports[4].bits.uop.xcpt_pf_if, io.wakeup_ports[4].bits.uop.xcpt_pf_if connect issue_slots[12].wakeup_ports[4].bits.uop.fp_typ, io.wakeup_ports[4].bits.uop.fp_typ connect issue_slots[12].wakeup_ports[4].bits.uop.fp_rm, io.wakeup_ports[4].bits.uop.fp_rm connect issue_slots[12].wakeup_ports[4].bits.uop.fp_val, io.wakeup_ports[4].bits.uop.fp_val connect issue_slots[12].wakeup_ports[4].bits.uop.fcn_op, io.wakeup_ports[4].bits.uop.fcn_op connect issue_slots[12].wakeup_ports[4].bits.uop.fcn_dw, io.wakeup_ports[4].bits.uop.fcn_dw connect issue_slots[12].wakeup_ports[4].bits.uop.frs3_en, io.wakeup_ports[4].bits.uop.frs3_en connect issue_slots[12].wakeup_ports[4].bits.uop.lrs2_rtype, io.wakeup_ports[4].bits.uop.lrs2_rtype connect issue_slots[12].wakeup_ports[4].bits.uop.lrs1_rtype, io.wakeup_ports[4].bits.uop.lrs1_rtype connect issue_slots[12].wakeup_ports[4].bits.uop.dst_rtype, io.wakeup_ports[4].bits.uop.dst_rtype connect issue_slots[12].wakeup_ports[4].bits.uop.lrs3, io.wakeup_ports[4].bits.uop.lrs3 connect issue_slots[12].wakeup_ports[4].bits.uop.lrs2, io.wakeup_ports[4].bits.uop.lrs2 connect issue_slots[12].wakeup_ports[4].bits.uop.lrs1, io.wakeup_ports[4].bits.uop.lrs1 connect issue_slots[12].wakeup_ports[4].bits.uop.ldst, io.wakeup_ports[4].bits.uop.ldst connect issue_slots[12].wakeup_ports[4].bits.uop.ldst_is_rs1, io.wakeup_ports[4].bits.uop.ldst_is_rs1 connect issue_slots[12].wakeup_ports[4].bits.uop.csr_cmd, io.wakeup_ports[4].bits.uop.csr_cmd connect issue_slots[12].wakeup_ports[4].bits.uop.flush_on_commit, io.wakeup_ports[4].bits.uop.flush_on_commit connect issue_slots[12].wakeup_ports[4].bits.uop.is_unique, io.wakeup_ports[4].bits.uop.is_unique connect issue_slots[12].wakeup_ports[4].bits.uop.uses_stq, io.wakeup_ports[4].bits.uop.uses_stq connect issue_slots[12].wakeup_ports[4].bits.uop.uses_ldq, io.wakeup_ports[4].bits.uop.uses_ldq connect issue_slots[12].wakeup_ports[4].bits.uop.mem_signed, io.wakeup_ports[4].bits.uop.mem_signed connect issue_slots[12].wakeup_ports[4].bits.uop.mem_size, io.wakeup_ports[4].bits.uop.mem_size connect issue_slots[12].wakeup_ports[4].bits.uop.mem_cmd, io.wakeup_ports[4].bits.uop.mem_cmd connect issue_slots[12].wakeup_ports[4].bits.uop.exc_cause, io.wakeup_ports[4].bits.uop.exc_cause connect issue_slots[12].wakeup_ports[4].bits.uop.exception, io.wakeup_ports[4].bits.uop.exception connect issue_slots[12].wakeup_ports[4].bits.uop.stale_pdst, io.wakeup_ports[4].bits.uop.stale_pdst connect issue_slots[12].wakeup_ports[4].bits.uop.ppred_busy, io.wakeup_ports[4].bits.uop.ppred_busy connect issue_slots[12].wakeup_ports[4].bits.uop.prs3_busy, io.wakeup_ports[4].bits.uop.prs3_busy connect issue_slots[12].wakeup_ports[4].bits.uop.prs2_busy, io.wakeup_ports[4].bits.uop.prs2_busy connect issue_slots[12].wakeup_ports[4].bits.uop.prs1_busy, io.wakeup_ports[4].bits.uop.prs1_busy connect issue_slots[12].wakeup_ports[4].bits.uop.ppred, io.wakeup_ports[4].bits.uop.ppred connect issue_slots[12].wakeup_ports[4].bits.uop.prs3, io.wakeup_ports[4].bits.uop.prs3 connect issue_slots[12].wakeup_ports[4].bits.uop.prs2, io.wakeup_ports[4].bits.uop.prs2 connect issue_slots[12].wakeup_ports[4].bits.uop.prs1, io.wakeup_ports[4].bits.uop.prs1 connect issue_slots[12].wakeup_ports[4].bits.uop.pdst, io.wakeup_ports[4].bits.uop.pdst connect issue_slots[12].wakeup_ports[4].bits.uop.rxq_idx, io.wakeup_ports[4].bits.uop.rxq_idx connect issue_slots[12].wakeup_ports[4].bits.uop.stq_idx, io.wakeup_ports[4].bits.uop.stq_idx connect issue_slots[12].wakeup_ports[4].bits.uop.ldq_idx, io.wakeup_ports[4].bits.uop.ldq_idx connect issue_slots[12].wakeup_ports[4].bits.uop.rob_idx, io.wakeup_ports[4].bits.uop.rob_idx connect issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.vec, io.wakeup_ports[4].bits.uop.fp_ctrl.vec connect issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.wflags, io.wakeup_ports[4].bits.uop.fp_ctrl.wflags connect issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.div, io.wakeup_ports[4].bits.uop.fp_ctrl.div connect issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.fma, io.wakeup_ports[4].bits.uop.fp_ctrl.fma connect issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.toint, io.wakeup_ports[4].bits.uop.fp_ctrl.toint connect issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.fromint, io.wakeup_ports[4].bits.uop.fp_ctrl.fromint connect issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.swap23, io.wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.swap12, io.wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.ren3, io.wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.ren2, io.wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.ren1, io.wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.wen, io.wakeup_ports[4].bits.uop.fp_ctrl.wen connect issue_slots[12].wakeup_ports[4].bits.uop.fp_ctrl.ldst, io.wakeup_ports[4].bits.uop.fp_ctrl.ldst connect issue_slots[12].wakeup_ports[4].bits.uop.op2_sel, io.wakeup_ports[4].bits.uop.op2_sel connect issue_slots[12].wakeup_ports[4].bits.uop.op1_sel, io.wakeup_ports[4].bits.uop.op1_sel connect issue_slots[12].wakeup_ports[4].bits.uop.imm_packed, io.wakeup_ports[4].bits.uop.imm_packed connect issue_slots[12].wakeup_ports[4].bits.uop.pimm, io.wakeup_ports[4].bits.uop.pimm connect issue_slots[12].wakeup_ports[4].bits.uop.imm_sel, io.wakeup_ports[4].bits.uop.imm_sel connect issue_slots[12].wakeup_ports[4].bits.uop.imm_rename, io.wakeup_ports[4].bits.uop.imm_rename connect issue_slots[12].wakeup_ports[4].bits.uop.taken, io.wakeup_ports[4].bits.uop.taken connect issue_slots[12].wakeup_ports[4].bits.uop.pc_lob, io.wakeup_ports[4].bits.uop.pc_lob connect issue_slots[12].wakeup_ports[4].bits.uop.edge_inst, io.wakeup_ports[4].bits.uop.edge_inst connect issue_slots[12].wakeup_ports[4].bits.uop.ftq_idx, io.wakeup_ports[4].bits.uop.ftq_idx connect issue_slots[12].wakeup_ports[4].bits.uop.is_mov, io.wakeup_ports[4].bits.uop.is_mov connect issue_slots[12].wakeup_ports[4].bits.uop.is_rocc, io.wakeup_ports[4].bits.uop.is_rocc connect issue_slots[12].wakeup_ports[4].bits.uop.is_sys_pc2epc, io.wakeup_ports[4].bits.uop.is_sys_pc2epc connect issue_slots[12].wakeup_ports[4].bits.uop.is_eret, io.wakeup_ports[4].bits.uop.is_eret connect issue_slots[12].wakeup_ports[4].bits.uop.is_amo, io.wakeup_ports[4].bits.uop.is_amo connect issue_slots[12].wakeup_ports[4].bits.uop.is_sfence, io.wakeup_ports[4].bits.uop.is_sfence connect issue_slots[12].wakeup_ports[4].bits.uop.is_fencei, io.wakeup_ports[4].bits.uop.is_fencei connect issue_slots[12].wakeup_ports[4].bits.uop.is_fence, io.wakeup_ports[4].bits.uop.is_fence connect issue_slots[12].wakeup_ports[4].bits.uop.is_sfb, io.wakeup_ports[4].bits.uop.is_sfb connect issue_slots[12].wakeup_ports[4].bits.uop.br_type, io.wakeup_ports[4].bits.uop.br_type connect issue_slots[12].wakeup_ports[4].bits.uop.br_tag, io.wakeup_ports[4].bits.uop.br_tag connect issue_slots[12].wakeup_ports[4].bits.uop.br_mask, io.wakeup_ports[4].bits.uop.br_mask connect issue_slots[12].wakeup_ports[4].bits.uop.dis_col_sel, io.wakeup_ports[4].bits.uop.dis_col_sel connect issue_slots[12].wakeup_ports[4].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect issue_slots[12].wakeup_ports[4].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect issue_slots[12].wakeup_ports[4].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect issue_slots[12].wakeup_ports[4].bits.uop.iw_p2_speculative_child, io.wakeup_ports[4].bits.uop.iw_p2_speculative_child connect issue_slots[12].wakeup_ports[4].bits.uop.iw_p1_speculative_child, io.wakeup_ports[4].bits.uop.iw_p1_speculative_child connect issue_slots[12].wakeup_ports[4].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect issue_slots[12].wakeup_ports[4].bits.uop.iw_issued_partial_agen, io.wakeup_ports[4].bits.uop.iw_issued_partial_agen connect issue_slots[12].wakeup_ports[4].bits.uop.iw_issued, io.wakeup_ports[4].bits.uop.iw_issued connect issue_slots[12].wakeup_ports[4].bits.uop.fu_code[0], io.wakeup_ports[4].bits.uop.fu_code[0] connect issue_slots[12].wakeup_ports[4].bits.uop.fu_code[1], io.wakeup_ports[4].bits.uop.fu_code[1] connect issue_slots[12].wakeup_ports[4].bits.uop.fu_code[2], io.wakeup_ports[4].bits.uop.fu_code[2] connect issue_slots[12].wakeup_ports[4].bits.uop.fu_code[3], io.wakeup_ports[4].bits.uop.fu_code[3] connect issue_slots[12].wakeup_ports[4].bits.uop.fu_code[4], io.wakeup_ports[4].bits.uop.fu_code[4] connect issue_slots[12].wakeup_ports[4].bits.uop.fu_code[5], io.wakeup_ports[4].bits.uop.fu_code[5] connect issue_slots[12].wakeup_ports[4].bits.uop.fu_code[6], io.wakeup_ports[4].bits.uop.fu_code[6] connect issue_slots[12].wakeup_ports[4].bits.uop.fu_code[7], io.wakeup_ports[4].bits.uop.fu_code[7] connect issue_slots[12].wakeup_ports[4].bits.uop.fu_code[8], io.wakeup_ports[4].bits.uop.fu_code[8] connect issue_slots[12].wakeup_ports[4].bits.uop.fu_code[9], io.wakeup_ports[4].bits.uop.fu_code[9] connect issue_slots[12].wakeup_ports[4].bits.uop.iq_type[0], io.wakeup_ports[4].bits.uop.iq_type[0] connect issue_slots[12].wakeup_ports[4].bits.uop.iq_type[1], io.wakeup_ports[4].bits.uop.iq_type[1] connect issue_slots[12].wakeup_ports[4].bits.uop.iq_type[2], io.wakeup_ports[4].bits.uop.iq_type[2] connect issue_slots[12].wakeup_ports[4].bits.uop.iq_type[3], io.wakeup_ports[4].bits.uop.iq_type[3] connect issue_slots[12].wakeup_ports[4].bits.uop.debug_pc, io.wakeup_ports[4].bits.uop.debug_pc connect issue_slots[12].wakeup_ports[4].bits.uop.is_rvc, io.wakeup_ports[4].bits.uop.is_rvc connect issue_slots[12].wakeup_ports[4].bits.uop.debug_inst, io.wakeup_ports[4].bits.uop.debug_inst connect issue_slots[12].wakeup_ports[4].bits.uop.inst, io.wakeup_ports[4].bits.uop.inst connect issue_slots[12].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[12].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[12].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[12].child_rebusys, io.child_rebusys connect issue_slots[12].squash_grant, io.squash_grant connect issue_slots[12].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[12].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[12].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[12].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[12].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[12].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[12].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[12].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[12].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[12].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[12].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[12].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[12].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[12].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect issue_slots[12].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect issue_slots[12].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[12].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect issue_slots[12].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect issue_slots[12].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[12].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[12].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[12].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[12].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[12].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[12].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[12].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[12].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[12].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect issue_slots[12].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[12].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[12].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[12].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[12].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[12].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[12].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[12].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[12].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[12].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[12].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[12].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[12].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[12].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[12].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[12].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[12].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[12].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[12].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[12].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[12].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[12].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[12].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[12].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect issue_slots[12].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect issue_slots[12].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect issue_slots[12].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect issue_slots[12].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect issue_slots[12].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect issue_slots[12].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect issue_slots[12].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect issue_slots[12].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect issue_slots[12].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect issue_slots[12].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect issue_slots[12].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect issue_slots[12].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect issue_slots[12].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect issue_slots[12].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect issue_slots[12].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect issue_slots[12].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect issue_slots[12].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect issue_slots[12].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect issue_slots[12].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[12].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect issue_slots[12].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect issue_slots[12].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect issue_slots[12].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[12].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[12].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[12].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[12].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect issue_slots[12].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect issue_slots[12].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[12].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect issue_slots[12].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[12].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect issue_slots[12].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[12].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[12].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[12].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect issue_slots[12].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[12].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[12].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect issue_slots[12].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect issue_slots[12].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect issue_slots[12].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect issue_slots[12].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect issue_slots[12].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect issue_slots[12].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect issue_slots[12].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect issue_slots[12].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect issue_slots[12].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect issue_slots[12].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect issue_slots[12].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect issue_slots[12].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect issue_slots[12].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect issue_slots[12].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect issue_slots[12].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect issue_slots[12].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect issue_slots[12].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect issue_slots[12].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect issue_slots[12].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect issue_slots[12].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect issue_slots[12].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect issue_slots[12].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect issue_slots[12].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[12].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[12].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[12].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[12].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[12].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[12].kill, io.flush_pipeline connect issue_slots[13].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy connect issue_slots[13].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask connect issue_slots[13].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable connect issue_slots[13].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc connect issue_slots[13].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc connect issue_slots[13].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if connect issue_slots[13].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if connect issue_slots[13].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if connect issue_slots[13].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if connect issue_slots[13].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if connect issue_slots[13].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ connect issue_slots[13].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm connect issue_slots[13].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val connect issue_slots[13].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op connect issue_slots[13].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw connect issue_slots[13].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en connect issue_slots[13].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype connect issue_slots[13].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype connect issue_slots[13].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype connect issue_slots[13].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 connect issue_slots[13].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 connect issue_slots[13].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 connect issue_slots[13].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst connect issue_slots[13].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 connect issue_slots[13].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd connect issue_slots[13].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit connect issue_slots[13].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique connect issue_slots[13].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq connect issue_slots[13].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq connect issue_slots[13].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed connect issue_slots[13].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size connect issue_slots[13].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd connect issue_slots[13].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause connect issue_slots[13].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception connect issue_slots[13].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst connect issue_slots[13].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy connect issue_slots[13].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy connect issue_slots[13].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy connect issue_slots[13].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy connect issue_slots[13].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred connect issue_slots[13].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 connect issue_slots[13].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 connect issue_slots[13].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 connect issue_slots[13].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst connect issue_slots[13].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx connect issue_slots[13].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx connect issue_slots[13].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx connect issue_slots[13].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen connect issue_slots[13].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst connect issue_slots[13].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel connect issue_slots[13].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel connect issue_slots[13].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed connect issue_slots[13].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm connect issue_slots[13].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel connect issue_slots[13].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename connect issue_slots[13].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken connect issue_slots[13].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob connect issue_slots[13].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst connect issue_slots[13].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx connect issue_slots[13].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov connect issue_slots[13].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc connect issue_slots[13].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc connect issue_slots[13].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret connect issue_slots[13].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo connect issue_slots[13].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence connect issue_slots[13].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei connect issue_slots[13].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence connect issue_slots[13].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb connect issue_slots[13].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type connect issue_slots[13].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag connect issue_slots[13].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask connect issue_slots[13].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel connect issue_slots[13].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect issue_slots[13].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect issue_slots[13].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect issue_slots[13].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child connect issue_slots[13].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child connect issue_slots[13].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect issue_slots[13].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen connect issue_slots[13].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued connect issue_slots[13].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] connect issue_slots[13].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] connect issue_slots[13].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] connect issue_slots[13].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] connect issue_slots[13].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] connect issue_slots[13].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] connect issue_slots[13].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] connect issue_slots[13].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] connect issue_slots[13].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] connect issue_slots[13].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] connect issue_slots[13].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] connect issue_slots[13].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] connect issue_slots[13].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] connect issue_slots[13].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] connect issue_slots[13].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc connect issue_slots[13].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc connect issue_slots[13].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst connect issue_slots[13].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst connect issue_slots[13].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[13].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy connect issue_slots[13].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask connect issue_slots[13].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable connect issue_slots[13].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc connect issue_slots[13].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc connect issue_slots[13].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if connect issue_slots[13].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if connect issue_slots[13].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if connect issue_slots[13].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if connect issue_slots[13].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if connect issue_slots[13].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ connect issue_slots[13].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm connect issue_slots[13].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val connect issue_slots[13].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op connect issue_slots[13].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw connect issue_slots[13].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en connect issue_slots[13].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype connect issue_slots[13].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype connect issue_slots[13].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype connect issue_slots[13].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 connect issue_slots[13].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 connect issue_slots[13].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 connect issue_slots[13].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst connect issue_slots[13].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 connect issue_slots[13].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd connect issue_slots[13].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit connect issue_slots[13].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique connect issue_slots[13].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq connect issue_slots[13].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq connect issue_slots[13].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed connect issue_slots[13].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size connect issue_slots[13].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd connect issue_slots[13].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause connect issue_slots[13].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception connect issue_slots[13].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst connect issue_slots[13].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy connect issue_slots[13].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy connect issue_slots[13].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy connect issue_slots[13].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy connect issue_slots[13].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred connect issue_slots[13].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 connect issue_slots[13].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 connect issue_slots[13].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 connect issue_slots[13].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst connect issue_slots[13].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx connect issue_slots[13].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx connect issue_slots[13].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx connect issue_slots[13].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen connect issue_slots[13].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst connect issue_slots[13].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel connect issue_slots[13].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel connect issue_slots[13].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed connect issue_slots[13].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm connect issue_slots[13].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel connect issue_slots[13].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename connect issue_slots[13].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken connect issue_slots[13].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob connect issue_slots[13].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst connect issue_slots[13].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx connect issue_slots[13].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov connect issue_slots[13].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc connect issue_slots[13].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc connect issue_slots[13].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret connect issue_slots[13].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo connect issue_slots[13].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence connect issue_slots[13].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei connect issue_slots[13].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence connect issue_slots[13].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb connect issue_slots[13].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type connect issue_slots[13].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag connect issue_slots[13].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask connect issue_slots[13].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel connect issue_slots[13].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect issue_slots[13].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect issue_slots[13].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect issue_slots[13].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child connect issue_slots[13].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child connect issue_slots[13].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect issue_slots[13].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen connect issue_slots[13].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued connect issue_slots[13].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] connect issue_slots[13].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] connect issue_slots[13].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] connect issue_slots[13].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] connect issue_slots[13].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] connect issue_slots[13].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] connect issue_slots[13].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] connect issue_slots[13].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] connect issue_slots[13].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] connect issue_slots[13].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] connect issue_slots[13].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] connect issue_slots[13].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] connect issue_slots[13].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] connect issue_slots[13].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] connect issue_slots[13].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc connect issue_slots[13].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc connect issue_slots[13].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst connect issue_slots[13].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst connect issue_slots[13].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[13].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy connect issue_slots[13].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask connect issue_slots[13].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable connect issue_slots[13].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc connect issue_slots[13].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc connect issue_slots[13].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if connect issue_slots[13].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if connect issue_slots[13].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if connect issue_slots[13].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if connect issue_slots[13].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if connect issue_slots[13].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ connect issue_slots[13].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm connect issue_slots[13].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val connect issue_slots[13].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op connect issue_slots[13].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw connect issue_slots[13].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en connect issue_slots[13].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype connect issue_slots[13].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype connect issue_slots[13].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype connect issue_slots[13].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3 connect issue_slots[13].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2 connect issue_slots[13].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1 connect issue_slots[13].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst connect issue_slots[13].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1 connect issue_slots[13].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd connect issue_slots[13].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit connect issue_slots[13].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique connect issue_slots[13].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq connect issue_slots[13].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq connect issue_slots[13].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed connect issue_slots[13].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size connect issue_slots[13].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd connect issue_slots[13].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause connect issue_slots[13].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception connect issue_slots[13].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst connect issue_slots[13].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy connect issue_slots[13].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy connect issue_slots[13].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy connect issue_slots[13].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy connect issue_slots[13].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred connect issue_slots[13].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3 connect issue_slots[13].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2 connect issue_slots[13].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1 connect issue_slots[13].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst connect issue_slots[13].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx connect issue_slots[13].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx connect issue_slots[13].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx connect issue_slots[13].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen connect issue_slots[13].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst connect issue_slots[13].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel connect issue_slots[13].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel connect issue_slots[13].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed connect issue_slots[13].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm connect issue_slots[13].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel connect issue_slots[13].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename connect issue_slots[13].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken connect issue_slots[13].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob connect issue_slots[13].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst connect issue_slots[13].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx connect issue_slots[13].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov connect issue_slots[13].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc connect issue_slots[13].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc connect issue_slots[13].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret connect issue_slots[13].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo connect issue_slots[13].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence connect issue_slots[13].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei connect issue_slots[13].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence connect issue_slots[13].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb connect issue_slots[13].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type connect issue_slots[13].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag connect issue_slots[13].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask connect issue_slots[13].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel connect issue_slots[13].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect issue_slots[13].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect issue_slots[13].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect issue_slots[13].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child connect issue_slots[13].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child connect issue_slots[13].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect issue_slots[13].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen connect issue_slots[13].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued connect issue_slots[13].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0] connect issue_slots[13].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1] connect issue_slots[13].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2] connect issue_slots[13].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3] connect issue_slots[13].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4] connect issue_slots[13].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5] connect issue_slots[13].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6] connect issue_slots[13].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7] connect issue_slots[13].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8] connect issue_slots[13].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9] connect issue_slots[13].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0] connect issue_slots[13].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1] connect issue_slots[13].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2] connect issue_slots[13].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3] connect issue_slots[13].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc connect issue_slots[13].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc connect issue_slots[13].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst connect issue_slots[13].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst connect issue_slots[13].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[13].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy connect issue_slots[13].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask connect issue_slots[13].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable connect issue_slots[13].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc connect issue_slots[13].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc connect issue_slots[13].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if connect issue_slots[13].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if connect issue_slots[13].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if connect issue_slots[13].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if connect issue_slots[13].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if connect issue_slots[13].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ connect issue_slots[13].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm connect issue_slots[13].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val connect issue_slots[13].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op connect issue_slots[13].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw connect issue_slots[13].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en connect issue_slots[13].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype connect issue_slots[13].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype connect issue_slots[13].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype connect issue_slots[13].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3 connect issue_slots[13].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2 connect issue_slots[13].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1 connect issue_slots[13].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst connect issue_slots[13].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1 connect issue_slots[13].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd connect issue_slots[13].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit connect issue_slots[13].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique connect issue_slots[13].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq connect issue_slots[13].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq connect issue_slots[13].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed connect issue_slots[13].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size connect issue_slots[13].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd connect issue_slots[13].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause connect issue_slots[13].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception connect issue_slots[13].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst connect issue_slots[13].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy connect issue_slots[13].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy connect issue_slots[13].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy connect issue_slots[13].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy connect issue_slots[13].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred connect issue_slots[13].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3 connect issue_slots[13].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2 connect issue_slots[13].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1 connect issue_slots[13].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst connect issue_slots[13].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx connect issue_slots[13].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx connect issue_slots[13].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx connect issue_slots[13].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen connect issue_slots[13].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst connect issue_slots[13].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel connect issue_slots[13].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel connect issue_slots[13].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed connect issue_slots[13].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm connect issue_slots[13].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel connect issue_slots[13].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename connect issue_slots[13].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken connect issue_slots[13].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob connect issue_slots[13].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst connect issue_slots[13].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx connect issue_slots[13].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov connect issue_slots[13].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc connect issue_slots[13].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc connect issue_slots[13].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret connect issue_slots[13].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo connect issue_slots[13].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence connect issue_slots[13].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei connect issue_slots[13].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence connect issue_slots[13].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb connect issue_slots[13].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type connect issue_slots[13].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag connect issue_slots[13].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask connect issue_slots[13].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel connect issue_slots[13].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect issue_slots[13].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect issue_slots[13].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect issue_slots[13].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child connect issue_slots[13].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child connect issue_slots[13].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect issue_slots[13].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen connect issue_slots[13].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued connect issue_slots[13].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0] connect issue_slots[13].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1] connect issue_slots[13].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2] connect issue_slots[13].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3] connect issue_slots[13].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4] connect issue_slots[13].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5] connect issue_slots[13].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6] connect issue_slots[13].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7] connect issue_slots[13].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8] connect issue_slots[13].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9] connect issue_slots[13].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0] connect issue_slots[13].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1] connect issue_slots[13].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2] connect issue_slots[13].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3] connect issue_slots[13].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc connect issue_slots[13].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc connect issue_slots[13].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst connect issue_slots[13].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst connect issue_slots[13].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[13].wakeup_ports[4].bits.rebusy, io.wakeup_ports[4].bits.rebusy connect issue_slots[13].wakeup_ports[4].bits.speculative_mask, io.wakeup_ports[4].bits.speculative_mask connect issue_slots[13].wakeup_ports[4].bits.bypassable, io.wakeup_ports[4].bits.bypassable connect issue_slots[13].wakeup_ports[4].bits.uop.debug_tsrc, io.wakeup_ports[4].bits.uop.debug_tsrc connect issue_slots[13].wakeup_ports[4].bits.uop.debug_fsrc, io.wakeup_ports[4].bits.uop.debug_fsrc connect issue_slots[13].wakeup_ports[4].bits.uop.bp_xcpt_if, io.wakeup_ports[4].bits.uop.bp_xcpt_if connect issue_slots[13].wakeup_ports[4].bits.uop.bp_debug_if, io.wakeup_ports[4].bits.uop.bp_debug_if connect issue_slots[13].wakeup_ports[4].bits.uop.xcpt_ma_if, io.wakeup_ports[4].bits.uop.xcpt_ma_if connect issue_slots[13].wakeup_ports[4].bits.uop.xcpt_ae_if, io.wakeup_ports[4].bits.uop.xcpt_ae_if connect issue_slots[13].wakeup_ports[4].bits.uop.xcpt_pf_if, io.wakeup_ports[4].bits.uop.xcpt_pf_if connect issue_slots[13].wakeup_ports[4].bits.uop.fp_typ, io.wakeup_ports[4].bits.uop.fp_typ connect issue_slots[13].wakeup_ports[4].bits.uop.fp_rm, io.wakeup_ports[4].bits.uop.fp_rm connect issue_slots[13].wakeup_ports[4].bits.uop.fp_val, io.wakeup_ports[4].bits.uop.fp_val connect issue_slots[13].wakeup_ports[4].bits.uop.fcn_op, io.wakeup_ports[4].bits.uop.fcn_op connect issue_slots[13].wakeup_ports[4].bits.uop.fcn_dw, io.wakeup_ports[4].bits.uop.fcn_dw connect issue_slots[13].wakeup_ports[4].bits.uop.frs3_en, io.wakeup_ports[4].bits.uop.frs3_en connect issue_slots[13].wakeup_ports[4].bits.uop.lrs2_rtype, io.wakeup_ports[4].bits.uop.lrs2_rtype connect issue_slots[13].wakeup_ports[4].bits.uop.lrs1_rtype, io.wakeup_ports[4].bits.uop.lrs1_rtype connect issue_slots[13].wakeup_ports[4].bits.uop.dst_rtype, io.wakeup_ports[4].bits.uop.dst_rtype connect issue_slots[13].wakeup_ports[4].bits.uop.lrs3, io.wakeup_ports[4].bits.uop.lrs3 connect issue_slots[13].wakeup_ports[4].bits.uop.lrs2, io.wakeup_ports[4].bits.uop.lrs2 connect issue_slots[13].wakeup_ports[4].bits.uop.lrs1, io.wakeup_ports[4].bits.uop.lrs1 connect issue_slots[13].wakeup_ports[4].bits.uop.ldst, io.wakeup_ports[4].bits.uop.ldst connect issue_slots[13].wakeup_ports[4].bits.uop.ldst_is_rs1, io.wakeup_ports[4].bits.uop.ldst_is_rs1 connect issue_slots[13].wakeup_ports[4].bits.uop.csr_cmd, io.wakeup_ports[4].bits.uop.csr_cmd connect issue_slots[13].wakeup_ports[4].bits.uop.flush_on_commit, io.wakeup_ports[4].bits.uop.flush_on_commit connect issue_slots[13].wakeup_ports[4].bits.uop.is_unique, io.wakeup_ports[4].bits.uop.is_unique connect issue_slots[13].wakeup_ports[4].bits.uop.uses_stq, io.wakeup_ports[4].bits.uop.uses_stq connect issue_slots[13].wakeup_ports[4].bits.uop.uses_ldq, io.wakeup_ports[4].bits.uop.uses_ldq connect issue_slots[13].wakeup_ports[4].bits.uop.mem_signed, io.wakeup_ports[4].bits.uop.mem_signed connect issue_slots[13].wakeup_ports[4].bits.uop.mem_size, io.wakeup_ports[4].bits.uop.mem_size connect issue_slots[13].wakeup_ports[4].bits.uop.mem_cmd, io.wakeup_ports[4].bits.uop.mem_cmd connect issue_slots[13].wakeup_ports[4].bits.uop.exc_cause, io.wakeup_ports[4].bits.uop.exc_cause connect issue_slots[13].wakeup_ports[4].bits.uop.exception, io.wakeup_ports[4].bits.uop.exception connect issue_slots[13].wakeup_ports[4].bits.uop.stale_pdst, io.wakeup_ports[4].bits.uop.stale_pdst connect issue_slots[13].wakeup_ports[4].bits.uop.ppred_busy, io.wakeup_ports[4].bits.uop.ppred_busy connect issue_slots[13].wakeup_ports[4].bits.uop.prs3_busy, io.wakeup_ports[4].bits.uop.prs3_busy connect issue_slots[13].wakeup_ports[4].bits.uop.prs2_busy, io.wakeup_ports[4].bits.uop.prs2_busy connect issue_slots[13].wakeup_ports[4].bits.uop.prs1_busy, io.wakeup_ports[4].bits.uop.prs1_busy connect issue_slots[13].wakeup_ports[4].bits.uop.ppred, io.wakeup_ports[4].bits.uop.ppred connect issue_slots[13].wakeup_ports[4].bits.uop.prs3, io.wakeup_ports[4].bits.uop.prs3 connect issue_slots[13].wakeup_ports[4].bits.uop.prs2, io.wakeup_ports[4].bits.uop.prs2 connect issue_slots[13].wakeup_ports[4].bits.uop.prs1, io.wakeup_ports[4].bits.uop.prs1 connect issue_slots[13].wakeup_ports[4].bits.uop.pdst, io.wakeup_ports[4].bits.uop.pdst connect issue_slots[13].wakeup_ports[4].bits.uop.rxq_idx, io.wakeup_ports[4].bits.uop.rxq_idx connect issue_slots[13].wakeup_ports[4].bits.uop.stq_idx, io.wakeup_ports[4].bits.uop.stq_idx connect issue_slots[13].wakeup_ports[4].bits.uop.ldq_idx, io.wakeup_ports[4].bits.uop.ldq_idx connect issue_slots[13].wakeup_ports[4].bits.uop.rob_idx, io.wakeup_ports[4].bits.uop.rob_idx connect issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.vec, io.wakeup_ports[4].bits.uop.fp_ctrl.vec connect issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.wflags, io.wakeup_ports[4].bits.uop.fp_ctrl.wflags connect issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.div, io.wakeup_ports[4].bits.uop.fp_ctrl.div connect issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.fma, io.wakeup_ports[4].bits.uop.fp_ctrl.fma connect issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.toint, io.wakeup_ports[4].bits.uop.fp_ctrl.toint connect issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.fromint, io.wakeup_ports[4].bits.uop.fp_ctrl.fromint connect issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.swap23, io.wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.swap12, io.wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.ren3, io.wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.ren2, io.wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.ren1, io.wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.wen, io.wakeup_ports[4].bits.uop.fp_ctrl.wen connect issue_slots[13].wakeup_ports[4].bits.uop.fp_ctrl.ldst, io.wakeup_ports[4].bits.uop.fp_ctrl.ldst connect issue_slots[13].wakeup_ports[4].bits.uop.op2_sel, io.wakeup_ports[4].bits.uop.op2_sel connect issue_slots[13].wakeup_ports[4].bits.uop.op1_sel, io.wakeup_ports[4].bits.uop.op1_sel connect issue_slots[13].wakeup_ports[4].bits.uop.imm_packed, io.wakeup_ports[4].bits.uop.imm_packed connect issue_slots[13].wakeup_ports[4].bits.uop.pimm, io.wakeup_ports[4].bits.uop.pimm connect issue_slots[13].wakeup_ports[4].bits.uop.imm_sel, io.wakeup_ports[4].bits.uop.imm_sel connect issue_slots[13].wakeup_ports[4].bits.uop.imm_rename, io.wakeup_ports[4].bits.uop.imm_rename connect issue_slots[13].wakeup_ports[4].bits.uop.taken, io.wakeup_ports[4].bits.uop.taken connect issue_slots[13].wakeup_ports[4].bits.uop.pc_lob, io.wakeup_ports[4].bits.uop.pc_lob connect issue_slots[13].wakeup_ports[4].bits.uop.edge_inst, io.wakeup_ports[4].bits.uop.edge_inst connect issue_slots[13].wakeup_ports[4].bits.uop.ftq_idx, io.wakeup_ports[4].bits.uop.ftq_idx connect issue_slots[13].wakeup_ports[4].bits.uop.is_mov, io.wakeup_ports[4].bits.uop.is_mov connect issue_slots[13].wakeup_ports[4].bits.uop.is_rocc, io.wakeup_ports[4].bits.uop.is_rocc connect issue_slots[13].wakeup_ports[4].bits.uop.is_sys_pc2epc, io.wakeup_ports[4].bits.uop.is_sys_pc2epc connect issue_slots[13].wakeup_ports[4].bits.uop.is_eret, io.wakeup_ports[4].bits.uop.is_eret connect issue_slots[13].wakeup_ports[4].bits.uop.is_amo, io.wakeup_ports[4].bits.uop.is_amo connect issue_slots[13].wakeup_ports[4].bits.uop.is_sfence, io.wakeup_ports[4].bits.uop.is_sfence connect issue_slots[13].wakeup_ports[4].bits.uop.is_fencei, io.wakeup_ports[4].bits.uop.is_fencei connect issue_slots[13].wakeup_ports[4].bits.uop.is_fence, io.wakeup_ports[4].bits.uop.is_fence connect issue_slots[13].wakeup_ports[4].bits.uop.is_sfb, io.wakeup_ports[4].bits.uop.is_sfb connect issue_slots[13].wakeup_ports[4].bits.uop.br_type, io.wakeup_ports[4].bits.uop.br_type connect issue_slots[13].wakeup_ports[4].bits.uop.br_tag, io.wakeup_ports[4].bits.uop.br_tag connect issue_slots[13].wakeup_ports[4].bits.uop.br_mask, io.wakeup_ports[4].bits.uop.br_mask connect issue_slots[13].wakeup_ports[4].bits.uop.dis_col_sel, io.wakeup_ports[4].bits.uop.dis_col_sel connect issue_slots[13].wakeup_ports[4].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect issue_slots[13].wakeup_ports[4].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect issue_slots[13].wakeup_ports[4].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect issue_slots[13].wakeup_ports[4].bits.uop.iw_p2_speculative_child, io.wakeup_ports[4].bits.uop.iw_p2_speculative_child connect issue_slots[13].wakeup_ports[4].bits.uop.iw_p1_speculative_child, io.wakeup_ports[4].bits.uop.iw_p1_speculative_child connect issue_slots[13].wakeup_ports[4].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect issue_slots[13].wakeup_ports[4].bits.uop.iw_issued_partial_agen, io.wakeup_ports[4].bits.uop.iw_issued_partial_agen connect issue_slots[13].wakeup_ports[4].bits.uop.iw_issued, io.wakeup_ports[4].bits.uop.iw_issued connect issue_slots[13].wakeup_ports[4].bits.uop.fu_code[0], io.wakeup_ports[4].bits.uop.fu_code[0] connect issue_slots[13].wakeup_ports[4].bits.uop.fu_code[1], io.wakeup_ports[4].bits.uop.fu_code[1] connect issue_slots[13].wakeup_ports[4].bits.uop.fu_code[2], io.wakeup_ports[4].bits.uop.fu_code[2] connect issue_slots[13].wakeup_ports[4].bits.uop.fu_code[3], io.wakeup_ports[4].bits.uop.fu_code[3] connect issue_slots[13].wakeup_ports[4].bits.uop.fu_code[4], io.wakeup_ports[4].bits.uop.fu_code[4] connect issue_slots[13].wakeup_ports[4].bits.uop.fu_code[5], io.wakeup_ports[4].bits.uop.fu_code[5] connect issue_slots[13].wakeup_ports[4].bits.uop.fu_code[6], io.wakeup_ports[4].bits.uop.fu_code[6] connect issue_slots[13].wakeup_ports[4].bits.uop.fu_code[7], io.wakeup_ports[4].bits.uop.fu_code[7] connect issue_slots[13].wakeup_ports[4].bits.uop.fu_code[8], io.wakeup_ports[4].bits.uop.fu_code[8] connect issue_slots[13].wakeup_ports[4].bits.uop.fu_code[9], io.wakeup_ports[4].bits.uop.fu_code[9] connect issue_slots[13].wakeup_ports[4].bits.uop.iq_type[0], io.wakeup_ports[4].bits.uop.iq_type[0] connect issue_slots[13].wakeup_ports[4].bits.uop.iq_type[1], io.wakeup_ports[4].bits.uop.iq_type[1] connect issue_slots[13].wakeup_ports[4].bits.uop.iq_type[2], io.wakeup_ports[4].bits.uop.iq_type[2] connect issue_slots[13].wakeup_ports[4].bits.uop.iq_type[3], io.wakeup_ports[4].bits.uop.iq_type[3] connect issue_slots[13].wakeup_ports[4].bits.uop.debug_pc, io.wakeup_ports[4].bits.uop.debug_pc connect issue_slots[13].wakeup_ports[4].bits.uop.is_rvc, io.wakeup_ports[4].bits.uop.is_rvc connect issue_slots[13].wakeup_ports[4].bits.uop.debug_inst, io.wakeup_ports[4].bits.uop.debug_inst connect issue_slots[13].wakeup_ports[4].bits.uop.inst, io.wakeup_ports[4].bits.uop.inst connect issue_slots[13].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[13].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[13].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[13].child_rebusys, io.child_rebusys connect issue_slots[13].squash_grant, io.squash_grant connect issue_slots[13].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[13].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[13].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[13].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[13].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[13].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[13].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[13].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[13].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[13].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[13].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[13].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[13].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[13].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect issue_slots[13].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect issue_slots[13].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[13].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect issue_slots[13].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect issue_slots[13].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[13].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[13].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[13].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[13].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[13].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[13].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[13].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[13].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[13].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect issue_slots[13].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[13].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[13].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[13].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[13].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[13].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[13].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[13].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[13].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[13].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[13].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[13].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[13].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[13].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[13].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[13].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[13].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[13].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[13].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[13].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[13].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[13].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[13].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[13].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect issue_slots[13].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect issue_slots[13].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect issue_slots[13].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect issue_slots[13].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect issue_slots[13].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect issue_slots[13].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect issue_slots[13].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect issue_slots[13].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect issue_slots[13].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect issue_slots[13].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect issue_slots[13].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect issue_slots[13].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect issue_slots[13].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect issue_slots[13].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect issue_slots[13].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect issue_slots[13].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect issue_slots[13].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect issue_slots[13].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect issue_slots[13].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[13].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect issue_slots[13].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect issue_slots[13].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect issue_slots[13].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[13].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[13].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[13].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[13].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect issue_slots[13].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect issue_slots[13].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[13].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect issue_slots[13].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[13].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect issue_slots[13].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[13].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[13].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[13].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect issue_slots[13].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[13].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[13].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect issue_slots[13].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect issue_slots[13].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect issue_slots[13].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect issue_slots[13].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect issue_slots[13].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect issue_slots[13].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect issue_slots[13].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect issue_slots[13].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect issue_slots[13].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect issue_slots[13].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect issue_slots[13].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect issue_slots[13].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect issue_slots[13].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect issue_slots[13].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect issue_slots[13].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect issue_slots[13].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect issue_slots[13].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect issue_slots[13].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect issue_slots[13].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect issue_slots[13].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect issue_slots[13].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect issue_slots[13].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect issue_slots[13].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[13].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[13].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[13].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[13].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[13].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[13].kill, io.flush_pipeline connect issue_slots[14].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy connect issue_slots[14].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask connect issue_slots[14].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable connect issue_slots[14].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc connect issue_slots[14].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc connect issue_slots[14].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if connect issue_slots[14].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if connect issue_slots[14].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if connect issue_slots[14].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if connect issue_slots[14].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if connect issue_slots[14].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ connect issue_slots[14].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm connect issue_slots[14].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val connect issue_slots[14].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op connect issue_slots[14].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw connect issue_slots[14].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en connect issue_slots[14].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype connect issue_slots[14].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype connect issue_slots[14].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype connect issue_slots[14].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 connect issue_slots[14].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 connect issue_slots[14].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 connect issue_slots[14].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst connect issue_slots[14].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 connect issue_slots[14].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd connect issue_slots[14].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit connect issue_slots[14].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique connect issue_slots[14].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq connect issue_slots[14].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq connect issue_slots[14].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed connect issue_slots[14].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size connect issue_slots[14].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd connect issue_slots[14].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause connect issue_slots[14].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception connect issue_slots[14].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst connect issue_slots[14].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy connect issue_slots[14].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy connect issue_slots[14].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy connect issue_slots[14].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy connect issue_slots[14].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred connect issue_slots[14].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 connect issue_slots[14].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 connect issue_slots[14].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 connect issue_slots[14].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst connect issue_slots[14].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx connect issue_slots[14].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx connect issue_slots[14].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx connect issue_slots[14].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen connect issue_slots[14].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst connect issue_slots[14].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel connect issue_slots[14].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel connect issue_slots[14].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed connect issue_slots[14].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm connect issue_slots[14].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel connect issue_slots[14].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename connect issue_slots[14].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken connect issue_slots[14].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob connect issue_slots[14].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst connect issue_slots[14].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx connect issue_slots[14].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov connect issue_slots[14].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc connect issue_slots[14].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc connect issue_slots[14].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret connect issue_slots[14].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo connect issue_slots[14].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence connect issue_slots[14].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei connect issue_slots[14].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence connect issue_slots[14].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb connect issue_slots[14].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type connect issue_slots[14].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag connect issue_slots[14].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask connect issue_slots[14].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel connect issue_slots[14].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect issue_slots[14].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect issue_slots[14].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect issue_slots[14].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child connect issue_slots[14].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child connect issue_slots[14].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect issue_slots[14].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen connect issue_slots[14].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued connect issue_slots[14].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] connect issue_slots[14].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] connect issue_slots[14].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] connect issue_slots[14].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] connect issue_slots[14].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] connect issue_slots[14].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] connect issue_slots[14].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] connect issue_slots[14].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] connect issue_slots[14].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] connect issue_slots[14].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] connect issue_slots[14].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] connect issue_slots[14].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] connect issue_slots[14].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] connect issue_slots[14].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] connect issue_slots[14].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc connect issue_slots[14].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc connect issue_slots[14].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst connect issue_slots[14].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst connect issue_slots[14].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[14].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy connect issue_slots[14].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask connect issue_slots[14].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable connect issue_slots[14].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc connect issue_slots[14].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc connect issue_slots[14].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if connect issue_slots[14].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if connect issue_slots[14].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if connect issue_slots[14].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if connect issue_slots[14].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if connect issue_slots[14].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ connect issue_slots[14].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm connect issue_slots[14].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val connect issue_slots[14].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op connect issue_slots[14].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw connect issue_slots[14].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en connect issue_slots[14].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype connect issue_slots[14].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype connect issue_slots[14].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype connect issue_slots[14].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 connect issue_slots[14].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 connect issue_slots[14].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 connect issue_slots[14].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst connect issue_slots[14].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 connect issue_slots[14].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd connect issue_slots[14].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit connect issue_slots[14].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique connect issue_slots[14].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq connect issue_slots[14].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq connect issue_slots[14].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed connect issue_slots[14].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size connect issue_slots[14].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd connect issue_slots[14].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause connect issue_slots[14].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception connect issue_slots[14].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst connect issue_slots[14].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy connect issue_slots[14].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy connect issue_slots[14].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy connect issue_slots[14].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy connect issue_slots[14].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred connect issue_slots[14].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 connect issue_slots[14].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 connect issue_slots[14].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 connect issue_slots[14].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst connect issue_slots[14].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx connect issue_slots[14].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx connect issue_slots[14].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx connect issue_slots[14].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen connect issue_slots[14].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst connect issue_slots[14].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel connect issue_slots[14].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel connect issue_slots[14].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed connect issue_slots[14].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm connect issue_slots[14].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel connect issue_slots[14].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename connect issue_slots[14].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken connect issue_slots[14].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob connect issue_slots[14].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst connect issue_slots[14].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx connect issue_slots[14].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov connect issue_slots[14].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc connect issue_slots[14].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc connect issue_slots[14].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret connect issue_slots[14].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo connect issue_slots[14].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence connect issue_slots[14].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei connect issue_slots[14].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence connect issue_slots[14].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb connect issue_slots[14].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type connect issue_slots[14].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag connect issue_slots[14].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask connect issue_slots[14].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel connect issue_slots[14].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect issue_slots[14].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect issue_slots[14].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect issue_slots[14].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child connect issue_slots[14].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child connect issue_slots[14].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect issue_slots[14].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen connect issue_slots[14].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued connect issue_slots[14].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] connect issue_slots[14].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] connect issue_slots[14].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] connect issue_slots[14].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] connect issue_slots[14].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] connect issue_slots[14].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] connect issue_slots[14].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] connect issue_slots[14].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] connect issue_slots[14].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] connect issue_slots[14].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] connect issue_slots[14].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] connect issue_slots[14].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] connect issue_slots[14].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] connect issue_slots[14].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] connect issue_slots[14].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc connect issue_slots[14].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc connect issue_slots[14].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst connect issue_slots[14].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst connect issue_slots[14].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[14].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy connect issue_slots[14].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask connect issue_slots[14].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable connect issue_slots[14].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc connect issue_slots[14].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc connect issue_slots[14].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if connect issue_slots[14].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if connect issue_slots[14].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if connect issue_slots[14].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if connect issue_slots[14].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if connect issue_slots[14].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ connect issue_slots[14].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm connect issue_slots[14].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val connect issue_slots[14].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op connect issue_slots[14].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw connect issue_slots[14].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en connect issue_slots[14].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype connect issue_slots[14].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype connect issue_slots[14].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype connect issue_slots[14].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3 connect issue_slots[14].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2 connect issue_slots[14].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1 connect issue_slots[14].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst connect issue_slots[14].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1 connect issue_slots[14].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd connect issue_slots[14].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit connect issue_slots[14].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique connect issue_slots[14].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq connect issue_slots[14].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq connect issue_slots[14].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed connect issue_slots[14].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size connect issue_slots[14].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd connect issue_slots[14].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause connect issue_slots[14].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception connect issue_slots[14].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst connect issue_slots[14].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy connect issue_slots[14].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy connect issue_slots[14].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy connect issue_slots[14].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy connect issue_slots[14].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred connect issue_slots[14].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3 connect issue_slots[14].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2 connect issue_slots[14].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1 connect issue_slots[14].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst connect issue_slots[14].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx connect issue_slots[14].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx connect issue_slots[14].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx connect issue_slots[14].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen connect issue_slots[14].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst connect issue_slots[14].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel connect issue_slots[14].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel connect issue_slots[14].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed connect issue_slots[14].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm connect issue_slots[14].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel connect issue_slots[14].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename connect issue_slots[14].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken connect issue_slots[14].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob connect issue_slots[14].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst connect issue_slots[14].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx connect issue_slots[14].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov connect issue_slots[14].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc connect issue_slots[14].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc connect issue_slots[14].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret connect issue_slots[14].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo connect issue_slots[14].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence connect issue_slots[14].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei connect issue_slots[14].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence connect issue_slots[14].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb connect issue_slots[14].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type connect issue_slots[14].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag connect issue_slots[14].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask connect issue_slots[14].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel connect issue_slots[14].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect issue_slots[14].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect issue_slots[14].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect issue_slots[14].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child connect issue_slots[14].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child connect issue_slots[14].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect issue_slots[14].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen connect issue_slots[14].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued connect issue_slots[14].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0] connect issue_slots[14].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1] connect issue_slots[14].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2] connect issue_slots[14].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3] connect issue_slots[14].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4] connect issue_slots[14].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5] connect issue_slots[14].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6] connect issue_slots[14].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7] connect issue_slots[14].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8] connect issue_slots[14].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9] connect issue_slots[14].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0] connect issue_slots[14].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1] connect issue_slots[14].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2] connect issue_slots[14].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3] connect issue_slots[14].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc connect issue_slots[14].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc connect issue_slots[14].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst connect issue_slots[14].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst connect issue_slots[14].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[14].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy connect issue_slots[14].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask connect issue_slots[14].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable connect issue_slots[14].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc connect issue_slots[14].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc connect issue_slots[14].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if connect issue_slots[14].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if connect issue_slots[14].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if connect issue_slots[14].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if connect issue_slots[14].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if connect issue_slots[14].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ connect issue_slots[14].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm connect issue_slots[14].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val connect issue_slots[14].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op connect issue_slots[14].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw connect issue_slots[14].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en connect issue_slots[14].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype connect issue_slots[14].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype connect issue_slots[14].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype connect issue_slots[14].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3 connect issue_slots[14].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2 connect issue_slots[14].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1 connect issue_slots[14].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst connect issue_slots[14].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1 connect issue_slots[14].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd connect issue_slots[14].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit connect issue_slots[14].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique connect issue_slots[14].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq connect issue_slots[14].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq connect issue_slots[14].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed connect issue_slots[14].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size connect issue_slots[14].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd connect issue_slots[14].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause connect issue_slots[14].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception connect issue_slots[14].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst connect issue_slots[14].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy connect issue_slots[14].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy connect issue_slots[14].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy connect issue_slots[14].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy connect issue_slots[14].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred connect issue_slots[14].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3 connect issue_slots[14].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2 connect issue_slots[14].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1 connect issue_slots[14].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst connect issue_slots[14].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx connect issue_slots[14].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx connect issue_slots[14].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx connect issue_slots[14].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen connect issue_slots[14].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst connect issue_slots[14].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel connect issue_slots[14].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel connect issue_slots[14].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed connect issue_slots[14].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm connect issue_slots[14].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel connect issue_slots[14].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename connect issue_slots[14].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken connect issue_slots[14].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob connect issue_slots[14].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst connect issue_slots[14].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx connect issue_slots[14].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov connect issue_slots[14].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc connect issue_slots[14].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc connect issue_slots[14].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret connect issue_slots[14].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo connect issue_slots[14].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence connect issue_slots[14].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei connect issue_slots[14].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence connect issue_slots[14].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb connect issue_slots[14].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type connect issue_slots[14].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag connect issue_slots[14].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask connect issue_slots[14].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel connect issue_slots[14].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect issue_slots[14].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect issue_slots[14].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect issue_slots[14].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child connect issue_slots[14].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child connect issue_slots[14].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect issue_slots[14].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen connect issue_slots[14].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued connect issue_slots[14].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0] connect issue_slots[14].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1] connect issue_slots[14].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2] connect issue_slots[14].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3] connect issue_slots[14].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4] connect issue_slots[14].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5] connect issue_slots[14].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6] connect issue_slots[14].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7] connect issue_slots[14].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8] connect issue_slots[14].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9] connect issue_slots[14].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0] connect issue_slots[14].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1] connect issue_slots[14].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2] connect issue_slots[14].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3] connect issue_slots[14].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc connect issue_slots[14].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc connect issue_slots[14].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst connect issue_slots[14].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst connect issue_slots[14].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[14].wakeup_ports[4].bits.rebusy, io.wakeup_ports[4].bits.rebusy connect issue_slots[14].wakeup_ports[4].bits.speculative_mask, io.wakeup_ports[4].bits.speculative_mask connect issue_slots[14].wakeup_ports[4].bits.bypassable, io.wakeup_ports[4].bits.bypassable connect issue_slots[14].wakeup_ports[4].bits.uop.debug_tsrc, io.wakeup_ports[4].bits.uop.debug_tsrc connect issue_slots[14].wakeup_ports[4].bits.uop.debug_fsrc, io.wakeup_ports[4].bits.uop.debug_fsrc connect issue_slots[14].wakeup_ports[4].bits.uop.bp_xcpt_if, io.wakeup_ports[4].bits.uop.bp_xcpt_if connect issue_slots[14].wakeup_ports[4].bits.uop.bp_debug_if, io.wakeup_ports[4].bits.uop.bp_debug_if connect issue_slots[14].wakeup_ports[4].bits.uop.xcpt_ma_if, io.wakeup_ports[4].bits.uop.xcpt_ma_if connect issue_slots[14].wakeup_ports[4].bits.uop.xcpt_ae_if, io.wakeup_ports[4].bits.uop.xcpt_ae_if connect issue_slots[14].wakeup_ports[4].bits.uop.xcpt_pf_if, io.wakeup_ports[4].bits.uop.xcpt_pf_if connect issue_slots[14].wakeup_ports[4].bits.uop.fp_typ, io.wakeup_ports[4].bits.uop.fp_typ connect issue_slots[14].wakeup_ports[4].bits.uop.fp_rm, io.wakeup_ports[4].bits.uop.fp_rm connect issue_slots[14].wakeup_ports[4].bits.uop.fp_val, io.wakeup_ports[4].bits.uop.fp_val connect issue_slots[14].wakeup_ports[4].bits.uop.fcn_op, io.wakeup_ports[4].bits.uop.fcn_op connect issue_slots[14].wakeup_ports[4].bits.uop.fcn_dw, io.wakeup_ports[4].bits.uop.fcn_dw connect issue_slots[14].wakeup_ports[4].bits.uop.frs3_en, io.wakeup_ports[4].bits.uop.frs3_en connect issue_slots[14].wakeup_ports[4].bits.uop.lrs2_rtype, io.wakeup_ports[4].bits.uop.lrs2_rtype connect issue_slots[14].wakeup_ports[4].bits.uop.lrs1_rtype, io.wakeup_ports[4].bits.uop.lrs1_rtype connect issue_slots[14].wakeup_ports[4].bits.uop.dst_rtype, io.wakeup_ports[4].bits.uop.dst_rtype connect issue_slots[14].wakeup_ports[4].bits.uop.lrs3, io.wakeup_ports[4].bits.uop.lrs3 connect issue_slots[14].wakeup_ports[4].bits.uop.lrs2, io.wakeup_ports[4].bits.uop.lrs2 connect issue_slots[14].wakeup_ports[4].bits.uop.lrs1, io.wakeup_ports[4].bits.uop.lrs1 connect issue_slots[14].wakeup_ports[4].bits.uop.ldst, io.wakeup_ports[4].bits.uop.ldst connect issue_slots[14].wakeup_ports[4].bits.uop.ldst_is_rs1, io.wakeup_ports[4].bits.uop.ldst_is_rs1 connect issue_slots[14].wakeup_ports[4].bits.uop.csr_cmd, io.wakeup_ports[4].bits.uop.csr_cmd connect issue_slots[14].wakeup_ports[4].bits.uop.flush_on_commit, io.wakeup_ports[4].bits.uop.flush_on_commit connect issue_slots[14].wakeup_ports[4].bits.uop.is_unique, io.wakeup_ports[4].bits.uop.is_unique connect issue_slots[14].wakeup_ports[4].bits.uop.uses_stq, io.wakeup_ports[4].bits.uop.uses_stq connect issue_slots[14].wakeup_ports[4].bits.uop.uses_ldq, io.wakeup_ports[4].bits.uop.uses_ldq connect issue_slots[14].wakeup_ports[4].bits.uop.mem_signed, io.wakeup_ports[4].bits.uop.mem_signed connect issue_slots[14].wakeup_ports[4].bits.uop.mem_size, io.wakeup_ports[4].bits.uop.mem_size connect issue_slots[14].wakeup_ports[4].bits.uop.mem_cmd, io.wakeup_ports[4].bits.uop.mem_cmd connect issue_slots[14].wakeup_ports[4].bits.uop.exc_cause, io.wakeup_ports[4].bits.uop.exc_cause connect issue_slots[14].wakeup_ports[4].bits.uop.exception, io.wakeup_ports[4].bits.uop.exception connect issue_slots[14].wakeup_ports[4].bits.uop.stale_pdst, io.wakeup_ports[4].bits.uop.stale_pdst connect issue_slots[14].wakeup_ports[4].bits.uop.ppred_busy, io.wakeup_ports[4].bits.uop.ppred_busy connect issue_slots[14].wakeup_ports[4].bits.uop.prs3_busy, io.wakeup_ports[4].bits.uop.prs3_busy connect issue_slots[14].wakeup_ports[4].bits.uop.prs2_busy, io.wakeup_ports[4].bits.uop.prs2_busy connect issue_slots[14].wakeup_ports[4].bits.uop.prs1_busy, io.wakeup_ports[4].bits.uop.prs1_busy connect issue_slots[14].wakeup_ports[4].bits.uop.ppred, io.wakeup_ports[4].bits.uop.ppred connect issue_slots[14].wakeup_ports[4].bits.uop.prs3, io.wakeup_ports[4].bits.uop.prs3 connect issue_slots[14].wakeup_ports[4].bits.uop.prs2, io.wakeup_ports[4].bits.uop.prs2 connect issue_slots[14].wakeup_ports[4].bits.uop.prs1, io.wakeup_ports[4].bits.uop.prs1 connect issue_slots[14].wakeup_ports[4].bits.uop.pdst, io.wakeup_ports[4].bits.uop.pdst connect issue_slots[14].wakeup_ports[4].bits.uop.rxq_idx, io.wakeup_ports[4].bits.uop.rxq_idx connect issue_slots[14].wakeup_ports[4].bits.uop.stq_idx, io.wakeup_ports[4].bits.uop.stq_idx connect issue_slots[14].wakeup_ports[4].bits.uop.ldq_idx, io.wakeup_ports[4].bits.uop.ldq_idx connect issue_slots[14].wakeup_ports[4].bits.uop.rob_idx, io.wakeup_ports[4].bits.uop.rob_idx connect issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.vec, io.wakeup_ports[4].bits.uop.fp_ctrl.vec connect issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.wflags, io.wakeup_ports[4].bits.uop.fp_ctrl.wflags connect issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.div, io.wakeup_ports[4].bits.uop.fp_ctrl.div connect issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.fma, io.wakeup_ports[4].bits.uop.fp_ctrl.fma connect issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.toint, io.wakeup_ports[4].bits.uop.fp_ctrl.toint connect issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.fromint, io.wakeup_ports[4].bits.uop.fp_ctrl.fromint connect issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.swap23, io.wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.swap12, io.wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.ren3, io.wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.ren2, io.wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.ren1, io.wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.wen, io.wakeup_ports[4].bits.uop.fp_ctrl.wen connect issue_slots[14].wakeup_ports[4].bits.uop.fp_ctrl.ldst, io.wakeup_ports[4].bits.uop.fp_ctrl.ldst connect issue_slots[14].wakeup_ports[4].bits.uop.op2_sel, io.wakeup_ports[4].bits.uop.op2_sel connect issue_slots[14].wakeup_ports[4].bits.uop.op1_sel, io.wakeup_ports[4].bits.uop.op1_sel connect issue_slots[14].wakeup_ports[4].bits.uop.imm_packed, io.wakeup_ports[4].bits.uop.imm_packed connect issue_slots[14].wakeup_ports[4].bits.uop.pimm, io.wakeup_ports[4].bits.uop.pimm connect issue_slots[14].wakeup_ports[4].bits.uop.imm_sel, io.wakeup_ports[4].bits.uop.imm_sel connect issue_slots[14].wakeup_ports[4].bits.uop.imm_rename, io.wakeup_ports[4].bits.uop.imm_rename connect issue_slots[14].wakeup_ports[4].bits.uop.taken, io.wakeup_ports[4].bits.uop.taken connect issue_slots[14].wakeup_ports[4].bits.uop.pc_lob, io.wakeup_ports[4].bits.uop.pc_lob connect issue_slots[14].wakeup_ports[4].bits.uop.edge_inst, io.wakeup_ports[4].bits.uop.edge_inst connect issue_slots[14].wakeup_ports[4].bits.uop.ftq_idx, io.wakeup_ports[4].bits.uop.ftq_idx connect issue_slots[14].wakeup_ports[4].bits.uop.is_mov, io.wakeup_ports[4].bits.uop.is_mov connect issue_slots[14].wakeup_ports[4].bits.uop.is_rocc, io.wakeup_ports[4].bits.uop.is_rocc connect issue_slots[14].wakeup_ports[4].bits.uop.is_sys_pc2epc, io.wakeup_ports[4].bits.uop.is_sys_pc2epc connect issue_slots[14].wakeup_ports[4].bits.uop.is_eret, io.wakeup_ports[4].bits.uop.is_eret connect issue_slots[14].wakeup_ports[4].bits.uop.is_amo, io.wakeup_ports[4].bits.uop.is_amo connect issue_slots[14].wakeup_ports[4].bits.uop.is_sfence, io.wakeup_ports[4].bits.uop.is_sfence connect issue_slots[14].wakeup_ports[4].bits.uop.is_fencei, io.wakeup_ports[4].bits.uop.is_fencei connect issue_slots[14].wakeup_ports[4].bits.uop.is_fence, io.wakeup_ports[4].bits.uop.is_fence connect issue_slots[14].wakeup_ports[4].bits.uop.is_sfb, io.wakeup_ports[4].bits.uop.is_sfb connect issue_slots[14].wakeup_ports[4].bits.uop.br_type, io.wakeup_ports[4].bits.uop.br_type connect issue_slots[14].wakeup_ports[4].bits.uop.br_tag, io.wakeup_ports[4].bits.uop.br_tag connect issue_slots[14].wakeup_ports[4].bits.uop.br_mask, io.wakeup_ports[4].bits.uop.br_mask connect issue_slots[14].wakeup_ports[4].bits.uop.dis_col_sel, io.wakeup_ports[4].bits.uop.dis_col_sel connect issue_slots[14].wakeup_ports[4].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect issue_slots[14].wakeup_ports[4].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect issue_slots[14].wakeup_ports[4].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect issue_slots[14].wakeup_ports[4].bits.uop.iw_p2_speculative_child, io.wakeup_ports[4].bits.uop.iw_p2_speculative_child connect issue_slots[14].wakeup_ports[4].bits.uop.iw_p1_speculative_child, io.wakeup_ports[4].bits.uop.iw_p1_speculative_child connect issue_slots[14].wakeup_ports[4].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect issue_slots[14].wakeup_ports[4].bits.uop.iw_issued_partial_agen, io.wakeup_ports[4].bits.uop.iw_issued_partial_agen connect issue_slots[14].wakeup_ports[4].bits.uop.iw_issued, io.wakeup_ports[4].bits.uop.iw_issued connect issue_slots[14].wakeup_ports[4].bits.uop.fu_code[0], io.wakeup_ports[4].bits.uop.fu_code[0] connect issue_slots[14].wakeup_ports[4].bits.uop.fu_code[1], io.wakeup_ports[4].bits.uop.fu_code[1] connect issue_slots[14].wakeup_ports[4].bits.uop.fu_code[2], io.wakeup_ports[4].bits.uop.fu_code[2] connect issue_slots[14].wakeup_ports[4].bits.uop.fu_code[3], io.wakeup_ports[4].bits.uop.fu_code[3] connect issue_slots[14].wakeup_ports[4].bits.uop.fu_code[4], io.wakeup_ports[4].bits.uop.fu_code[4] connect issue_slots[14].wakeup_ports[4].bits.uop.fu_code[5], io.wakeup_ports[4].bits.uop.fu_code[5] connect issue_slots[14].wakeup_ports[4].bits.uop.fu_code[6], io.wakeup_ports[4].bits.uop.fu_code[6] connect issue_slots[14].wakeup_ports[4].bits.uop.fu_code[7], io.wakeup_ports[4].bits.uop.fu_code[7] connect issue_slots[14].wakeup_ports[4].bits.uop.fu_code[8], io.wakeup_ports[4].bits.uop.fu_code[8] connect issue_slots[14].wakeup_ports[4].bits.uop.fu_code[9], io.wakeup_ports[4].bits.uop.fu_code[9] connect issue_slots[14].wakeup_ports[4].bits.uop.iq_type[0], io.wakeup_ports[4].bits.uop.iq_type[0] connect issue_slots[14].wakeup_ports[4].bits.uop.iq_type[1], io.wakeup_ports[4].bits.uop.iq_type[1] connect issue_slots[14].wakeup_ports[4].bits.uop.iq_type[2], io.wakeup_ports[4].bits.uop.iq_type[2] connect issue_slots[14].wakeup_ports[4].bits.uop.iq_type[3], io.wakeup_ports[4].bits.uop.iq_type[3] connect issue_slots[14].wakeup_ports[4].bits.uop.debug_pc, io.wakeup_ports[4].bits.uop.debug_pc connect issue_slots[14].wakeup_ports[4].bits.uop.is_rvc, io.wakeup_ports[4].bits.uop.is_rvc connect issue_slots[14].wakeup_ports[4].bits.uop.debug_inst, io.wakeup_ports[4].bits.uop.debug_inst connect issue_slots[14].wakeup_ports[4].bits.uop.inst, io.wakeup_ports[4].bits.uop.inst connect issue_slots[14].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[14].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[14].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[14].child_rebusys, io.child_rebusys connect issue_slots[14].squash_grant, io.squash_grant connect issue_slots[14].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[14].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[14].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[14].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[14].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[14].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[14].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[14].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[14].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[14].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[14].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[14].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[14].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[14].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect issue_slots[14].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect issue_slots[14].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[14].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect issue_slots[14].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect issue_slots[14].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[14].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[14].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[14].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[14].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[14].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[14].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[14].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[14].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[14].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect issue_slots[14].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[14].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[14].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[14].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[14].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[14].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[14].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[14].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[14].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[14].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[14].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[14].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[14].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[14].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[14].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[14].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[14].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[14].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[14].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[14].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[14].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[14].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[14].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[14].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect issue_slots[14].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect issue_slots[14].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect issue_slots[14].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect issue_slots[14].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect issue_slots[14].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect issue_slots[14].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect issue_slots[14].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect issue_slots[14].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect issue_slots[14].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect issue_slots[14].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect issue_slots[14].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect issue_slots[14].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect issue_slots[14].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect issue_slots[14].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect issue_slots[14].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect issue_slots[14].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect issue_slots[14].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect issue_slots[14].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect issue_slots[14].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[14].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect issue_slots[14].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect issue_slots[14].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect issue_slots[14].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[14].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[14].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[14].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[14].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect issue_slots[14].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect issue_slots[14].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[14].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect issue_slots[14].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[14].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect issue_slots[14].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[14].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[14].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[14].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect issue_slots[14].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[14].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[14].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect issue_slots[14].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect issue_slots[14].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect issue_slots[14].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect issue_slots[14].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect issue_slots[14].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect issue_slots[14].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect issue_slots[14].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect issue_slots[14].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect issue_slots[14].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect issue_slots[14].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect issue_slots[14].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect issue_slots[14].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect issue_slots[14].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect issue_slots[14].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect issue_slots[14].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect issue_slots[14].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect issue_slots[14].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect issue_slots[14].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect issue_slots[14].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect issue_slots[14].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect issue_slots[14].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect issue_slots[14].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect issue_slots[14].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[14].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[14].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[14].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[14].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[14].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[14].kill, io.flush_pipeline connect issue_slots[15].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy connect issue_slots[15].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask connect issue_slots[15].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable connect issue_slots[15].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc connect issue_slots[15].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc connect issue_slots[15].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if connect issue_slots[15].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if connect issue_slots[15].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if connect issue_slots[15].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if connect issue_slots[15].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if connect issue_slots[15].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ connect issue_slots[15].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm connect issue_slots[15].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val connect issue_slots[15].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op connect issue_slots[15].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw connect issue_slots[15].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en connect issue_slots[15].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype connect issue_slots[15].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype connect issue_slots[15].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype connect issue_slots[15].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 connect issue_slots[15].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 connect issue_slots[15].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 connect issue_slots[15].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst connect issue_slots[15].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 connect issue_slots[15].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd connect issue_slots[15].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit connect issue_slots[15].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique connect issue_slots[15].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq connect issue_slots[15].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq connect issue_slots[15].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed connect issue_slots[15].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size connect issue_slots[15].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd connect issue_slots[15].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause connect issue_slots[15].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception connect issue_slots[15].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst connect issue_slots[15].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy connect issue_slots[15].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy connect issue_slots[15].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy connect issue_slots[15].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy connect issue_slots[15].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred connect issue_slots[15].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 connect issue_slots[15].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 connect issue_slots[15].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 connect issue_slots[15].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst connect issue_slots[15].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx connect issue_slots[15].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx connect issue_slots[15].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx connect issue_slots[15].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen connect issue_slots[15].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst connect issue_slots[15].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel connect issue_slots[15].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel connect issue_slots[15].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed connect issue_slots[15].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm connect issue_slots[15].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel connect issue_slots[15].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename connect issue_slots[15].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken connect issue_slots[15].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob connect issue_slots[15].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst connect issue_slots[15].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx connect issue_slots[15].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov connect issue_slots[15].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc connect issue_slots[15].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc connect issue_slots[15].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret connect issue_slots[15].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo connect issue_slots[15].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence connect issue_slots[15].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei connect issue_slots[15].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence connect issue_slots[15].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb connect issue_slots[15].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type connect issue_slots[15].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag connect issue_slots[15].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask connect issue_slots[15].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel connect issue_slots[15].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect issue_slots[15].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect issue_slots[15].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect issue_slots[15].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child connect issue_slots[15].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child connect issue_slots[15].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect issue_slots[15].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen connect issue_slots[15].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued connect issue_slots[15].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] connect issue_slots[15].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] connect issue_slots[15].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] connect issue_slots[15].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] connect issue_slots[15].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] connect issue_slots[15].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] connect issue_slots[15].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] connect issue_slots[15].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] connect issue_slots[15].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] connect issue_slots[15].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] connect issue_slots[15].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] connect issue_slots[15].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] connect issue_slots[15].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] connect issue_slots[15].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] connect issue_slots[15].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc connect issue_slots[15].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc connect issue_slots[15].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst connect issue_slots[15].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst connect issue_slots[15].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[15].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy connect issue_slots[15].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask connect issue_slots[15].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable connect issue_slots[15].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc connect issue_slots[15].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc connect issue_slots[15].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if connect issue_slots[15].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if connect issue_slots[15].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if connect issue_slots[15].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if connect issue_slots[15].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if connect issue_slots[15].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ connect issue_slots[15].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm connect issue_slots[15].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val connect issue_slots[15].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op connect issue_slots[15].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw connect issue_slots[15].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en connect issue_slots[15].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype connect issue_slots[15].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype connect issue_slots[15].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype connect issue_slots[15].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 connect issue_slots[15].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 connect issue_slots[15].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 connect issue_slots[15].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst connect issue_slots[15].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 connect issue_slots[15].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd connect issue_slots[15].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit connect issue_slots[15].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique connect issue_slots[15].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq connect issue_slots[15].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq connect issue_slots[15].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed connect issue_slots[15].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size connect issue_slots[15].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd connect issue_slots[15].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause connect issue_slots[15].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception connect issue_slots[15].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst connect issue_slots[15].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy connect issue_slots[15].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy connect issue_slots[15].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy connect issue_slots[15].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy connect issue_slots[15].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred connect issue_slots[15].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 connect issue_slots[15].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 connect issue_slots[15].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 connect issue_slots[15].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst connect issue_slots[15].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx connect issue_slots[15].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx connect issue_slots[15].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx connect issue_slots[15].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen connect issue_slots[15].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst connect issue_slots[15].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel connect issue_slots[15].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel connect issue_slots[15].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed connect issue_slots[15].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm connect issue_slots[15].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel connect issue_slots[15].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename connect issue_slots[15].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken connect issue_slots[15].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob connect issue_slots[15].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst connect issue_slots[15].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx connect issue_slots[15].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov connect issue_slots[15].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc connect issue_slots[15].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc connect issue_slots[15].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret connect issue_slots[15].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo connect issue_slots[15].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence connect issue_slots[15].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei connect issue_slots[15].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence connect issue_slots[15].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb connect issue_slots[15].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type connect issue_slots[15].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag connect issue_slots[15].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask connect issue_slots[15].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel connect issue_slots[15].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect issue_slots[15].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect issue_slots[15].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect issue_slots[15].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child connect issue_slots[15].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child connect issue_slots[15].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect issue_slots[15].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen connect issue_slots[15].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued connect issue_slots[15].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] connect issue_slots[15].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] connect issue_slots[15].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] connect issue_slots[15].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] connect issue_slots[15].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] connect issue_slots[15].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] connect issue_slots[15].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] connect issue_slots[15].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] connect issue_slots[15].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] connect issue_slots[15].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] connect issue_slots[15].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] connect issue_slots[15].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] connect issue_slots[15].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] connect issue_slots[15].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] connect issue_slots[15].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc connect issue_slots[15].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc connect issue_slots[15].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst connect issue_slots[15].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst connect issue_slots[15].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[15].wakeup_ports[2].bits.rebusy, io.wakeup_ports[2].bits.rebusy connect issue_slots[15].wakeup_ports[2].bits.speculative_mask, io.wakeup_ports[2].bits.speculative_mask connect issue_slots[15].wakeup_ports[2].bits.bypassable, io.wakeup_ports[2].bits.bypassable connect issue_slots[15].wakeup_ports[2].bits.uop.debug_tsrc, io.wakeup_ports[2].bits.uop.debug_tsrc connect issue_slots[15].wakeup_ports[2].bits.uop.debug_fsrc, io.wakeup_ports[2].bits.uop.debug_fsrc connect issue_slots[15].wakeup_ports[2].bits.uop.bp_xcpt_if, io.wakeup_ports[2].bits.uop.bp_xcpt_if connect issue_slots[15].wakeup_ports[2].bits.uop.bp_debug_if, io.wakeup_ports[2].bits.uop.bp_debug_if connect issue_slots[15].wakeup_ports[2].bits.uop.xcpt_ma_if, io.wakeup_ports[2].bits.uop.xcpt_ma_if connect issue_slots[15].wakeup_ports[2].bits.uop.xcpt_ae_if, io.wakeup_ports[2].bits.uop.xcpt_ae_if connect issue_slots[15].wakeup_ports[2].bits.uop.xcpt_pf_if, io.wakeup_ports[2].bits.uop.xcpt_pf_if connect issue_slots[15].wakeup_ports[2].bits.uop.fp_typ, io.wakeup_ports[2].bits.uop.fp_typ connect issue_slots[15].wakeup_ports[2].bits.uop.fp_rm, io.wakeup_ports[2].bits.uop.fp_rm connect issue_slots[15].wakeup_ports[2].bits.uop.fp_val, io.wakeup_ports[2].bits.uop.fp_val connect issue_slots[15].wakeup_ports[2].bits.uop.fcn_op, io.wakeup_ports[2].bits.uop.fcn_op connect issue_slots[15].wakeup_ports[2].bits.uop.fcn_dw, io.wakeup_ports[2].bits.uop.fcn_dw connect issue_slots[15].wakeup_ports[2].bits.uop.frs3_en, io.wakeup_ports[2].bits.uop.frs3_en connect issue_slots[15].wakeup_ports[2].bits.uop.lrs2_rtype, io.wakeup_ports[2].bits.uop.lrs2_rtype connect issue_slots[15].wakeup_ports[2].bits.uop.lrs1_rtype, io.wakeup_ports[2].bits.uop.lrs1_rtype connect issue_slots[15].wakeup_ports[2].bits.uop.dst_rtype, io.wakeup_ports[2].bits.uop.dst_rtype connect issue_slots[15].wakeup_ports[2].bits.uop.lrs3, io.wakeup_ports[2].bits.uop.lrs3 connect issue_slots[15].wakeup_ports[2].bits.uop.lrs2, io.wakeup_ports[2].bits.uop.lrs2 connect issue_slots[15].wakeup_ports[2].bits.uop.lrs1, io.wakeup_ports[2].bits.uop.lrs1 connect issue_slots[15].wakeup_ports[2].bits.uop.ldst, io.wakeup_ports[2].bits.uop.ldst connect issue_slots[15].wakeup_ports[2].bits.uop.ldst_is_rs1, io.wakeup_ports[2].bits.uop.ldst_is_rs1 connect issue_slots[15].wakeup_ports[2].bits.uop.csr_cmd, io.wakeup_ports[2].bits.uop.csr_cmd connect issue_slots[15].wakeup_ports[2].bits.uop.flush_on_commit, io.wakeup_ports[2].bits.uop.flush_on_commit connect issue_slots[15].wakeup_ports[2].bits.uop.is_unique, io.wakeup_ports[2].bits.uop.is_unique connect issue_slots[15].wakeup_ports[2].bits.uop.uses_stq, io.wakeup_ports[2].bits.uop.uses_stq connect issue_slots[15].wakeup_ports[2].bits.uop.uses_ldq, io.wakeup_ports[2].bits.uop.uses_ldq connect issue_slots[15].wakeup_ports[2].bits.uop.mem_signed, io.wakeup_ports[2].bits.uop.mem_signed connect issue_slots[15].wakeup_ports[2].bits.uop.mem_size, io.wakeup_ports[2].bits.uop.mem_size connect issue_slots[15].wakeup_ports[2].bits.uop.mem_cmd, io.wakeup_ports[2].bits.uop.mem_cmd connect issue_slots[15].wakeup_ports[2].bits.uop.exc_cause, io.wakeup_ports[2].bits.uop.exc_cause connect issue_slots[15].wakeup_ports[2].bits.uop.exception, io.wakeup_ports[2].bits.uop.exception connect issue_slots[15].wakeup_ports[2].bits.uop.stale_pdst, io.wakeup_ports[2].bits.uop.stale_pdst connect issue_slots[15].wakeup_ports[2].bits.uop.ppred_busy, io.wakeup_ports[2].bits.uop.ppred_busy connect issue_slots[15].wakeup_ports[2].bits.uop.prs3_busy, io.wakeup_ports[2].bits.uop.prs3_busy connect issue_slots[15].wakeup_ports[2].bits.uop.prs2_busy, io.wakeup_ports[2].bits.uop.prs2_busy connect issue_slots[15].wakeup_ports[2].bits.uop.prs1_busy, io.wakeup_ports[2].bits.uop.prs1_busy connect issue_slots[15].wakeup_ports[2].bits.uop.ppred, io.wakeup_ports[2].bits.uop.ppred connect issue_slots[15].wakeup_ports[2].bits.uop.prs3, io.wakeup_ports[2].bits.uop.prs3 connect issue_slots[15].wakeup_ports[2].bits.uop.prs2, io.wakeup_ports[2].bits.uop.prs2 connect issue_slots[15].wakeup_ports[2].bits.uop.prs1, io.wakeup_ports[2].bits.uop.prs1 connect issue_slots[15].wakeup_ports[2].bits.uop.pdst, io.wakeup_ports[2].bits.uop.pdst connect issue_slots[15].wakeup_ports[2].bits.uop.rxq_idx, io.wakeup_ports[2].bits.uop.rxq_idx connect issue_slots[15].wakeup_ports[2].bits.uop.stq_idx, io.wakeup_ports[2].bits.uop.stq_idx connect issue_slots[15].wakeup_ports[2].bits.uop.ldq_idx, io.wakeup_ports[2].bits.uop.ldq_idx connect issue_slots[15].wakeup_ports[2].bits.uop.rob_idx, io.wakeup_ports[2].bits.uop.rob_idx connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.vec, io.wakeup_ports[2].bits.uop.fp_ctrl.vec connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.wflags, io.wakeup_ports[2].bits.uop.fp_ctrl.wflags connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.div, io.wakeup_ports[2].bits.uop.fp_ctrl.div connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.fma, io.wakeup_ports[2].bits.uop.fp_ctrl.fma connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.toint, io.wakeup_ports[2].bits.uop.fp_ctrl.toint connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.fromint, io.wakeup_ports[2].bits.uop.fp_ctrl.fromint connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.swap23, io.wakeup_ports[2].bits.uop.fp_ctrl.swap23 connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.swap12, io.wakeup_ports[2].bits.uop.fp_ctrl.swap12 connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.ren3, io.wakeup_ports[2].bits.uop.fp_ctrl.ren3 connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.ren2, io.wakeup_ports[2].bits.uop.fp_ctrl.ren2 connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.ren1, io.wakeup_ports[2].bits.uop.fp_ctrl.ren1 connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.wen, io.wakeup_ports[2].bits.uop.fp_ctrl.wen connect issue_slots[15].wakeup_ports[2].bits.uop.fp_ctrl.ldst, io.wakeup_ports[2].bits.uop.fp_ctrl.ldst connect issue_slots[15].wakeup_ports[2].bits.uop.op2_sel, io.wakeup_ports[2].bits.uop.op2_sel connect issue_slots[15].wakeup_ports[2].bits.uop.op1_sel, io.wakeup_ports[2].bits.uop.op1_sel connect issue_slots[15].wakeup_ports[2].bits.uop.imm_packed, io.wakeup_ports[2].bits.uop.imm_packed connect issue_slots[15].wakeup_ports[2].bits.uop.pimm, io.wakeup_ports[2].bits.uop.pimm connect issue_slots[15].wakeup_ports[2].bits.uop.imm_sel, io.wakeup_ports[2].bits.uop.imm_sel connect issue_slots[15].wakeup_ports[2].bits.uop.imm_rename, io.wakeup_ports[2].bits.uop.imm_rename connect issue_slots[15].wakeup_ports[2].bits.uop.taken, io.wakeup_ports[2].bits.uop.taken connect issue_slots[15].wakeup_ports[2].bits.uop.pc_lob, io.wakeup_ports[2].bits.uop.pc_lob connect issue_slots[15].wakeup_ports[2].bits.uop.edge_inst, io.wakeup_ports[2].bits.uop.edge_inst connect issue_slots[15].wakeup_ports[2].bits.uop.ftq_idx, io.wakeup_ports[2].bits.uop.ftq_idx connect issue_slots[15].wakeup_ports[2].bits.uop.is_mov, io.wakeup_ports[2].bits.uop.is_mov connect issue_slots[15].wakeup_ports[2].bits.uop.is_rocc, io.wakeup_ports[2].bits.uop.is_rocc connect issue_slots[15].wakeup_ports[2].bits.uop.is_sys_pc2epc, io.wakeup_ports[2].bits.uop.is_sys_pc2epc connect issue_slots[15].wakeup_ports[2].bits.uop.is_eret, io.wakeup_ports[2].bits.uop.is_eret connect issue_slots[15].wakeup_ports[2].bits.uop.is_amo, io.wakeup_ports[2].bits.uop.is_amo connect issue_slots[15].wakeup_ports[2].bits.uop.is_sfence, io.wakeup_ports[2].bits.uop.is_sfence connect issue_slots[15].wakeup_ports[2].bits.uop.is_fencei, io.wakeup_ports[2].bits.uop.is_fencei connect issue_slots[15].wakeup_ports[2].bits.uop.is_fence, io.wakeup_ports[2].bits.uop.is_fence connect issue_slots[15].wakeup_ports[2].bits.uop.is_sfb, io.wakeup_ports[2].bits.uop.is_sfb connect issue_slots[15].wakeup_ports[2].bits.uop.br_type, io.wakeup_ports[2].bits.uop.br_type connect issue_slots[15].wakeup_ports[2].bits.uop.br_tag, io.wakeup_ports[2].bits.uop.br_tag connect issue_slots[15].wakeup_ports[2].bits.uop.br_mask, io.wakeup_ports[2].bits.uop.br_mask connect issue_slots[15].wakeup_ports[2].bits.uop.dis_col_sel, io.wakeup_ports[2].bits.uop.dis_col_sel connect issue_slots[15].wakeup_ports[2].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint connect issue_slots[15].wakeup_ports[2].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint connect issue_slots[15].wakeup_ports[2].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint connect issue_slots[15].wakeup_ports[2].bits.uop.iw_p2_speculative_child, io.wakeup_ports[2].bits.uop.iw_p2_speculative_child connect issue_slots[15].wakeup_ports[2].bits.uop.iw_p1_speculative_child, io.wakeup_ports[2].bits.uop.iw_p1_speculative_child connect issue_slots[15].wakeup_ports[2].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen connect issue_slots[15].wakeup_ports[2].bits.uop.iw_issued_partial_agen, io.wakeup_ports[2].bits.uop.iw_issued_partial_agen connect issue_slots[15].wakeup_ports[2].bits.uop.iw_issued, io.wakeup_ports[2].bits.uop.iw_issued connect issue_slots[15].wakeup_ports[2].bits.uop.fu_code[0], io.wakeup_ports[2].bits.uop.fu_code[0] connect issue_slots[15].wakeup_ports[2].bits.uop.fu_code[1], io.wakeup_ports[2].bits.uop.fu_code[1] connect issue_slots[15].wakeup_ports[2].bits.uop.fu_code[2], io.wakeup_ports[2].bits.uop.fu_code[2] connect issue_slots[15].wakeup_ports[2].bits.uop.fu_code[3], io.wakeup_ports[2].bits.uop.fu_code[3] connect issue_slots[15].wakeup_ports[2].bits.uop.fu_code[4], io.wakeup_ports[2].bits.uop.fu_code[4] connect issue_slots[15].wakeup_ports[2].bits.uop.fu_code[5], io.wakeup_ports[2].bits.uop.fu_code[5] connect issue_slots[15].wakeup_ports[2].bits.uop.fu_code[6], io.wakeup_ports[2].bits.uop.fu_code[6] connect issue_slots[15].wakeup_ports[2].bits.uop.fu_code[7], io.wakeup_ports[2].bits.uop.fu_code[7] connect issue_slots[15].wakeup_ports[2].bits.uop.fu_code[8], io.wakeup_ports[2].bits.uop.fu_code[8] connect issue_slots[15].wakeup_ports[2].bits.uop.fu_code[9], io.wakeup_ports[2].bits.uop.fu_code[9] connect issue_slots[15].wakeup_ports[2].bits.uop.iq_type[0], io.wakeup_ports[2].bits.uop.iq_type[0] connect issue_slots[15].wakeup_ports[2].bits.uop.iq_type[1], io.wakeup_ports[2].bits.uop.iq_type[1] connect issue_slots[15].wakeup_ports[2].bits.uop.iq_type[2], io.wakeup_ports[2].bits.uop.iq_type[2] connect issue_slots[15].wakeup_ports[2].bits.uop.iq_type[3], io.wakeup_ports[2].bits.uop.iq_type[3] connect issue_slots[15].wakeup_ports[2].bits.uop.debug_pc, io.wakeup_ports[2].bits.uop.debug_pc connect issue_slots[15].wakeup_ports[2].bits.uop.is_rvc, io.wakeup_ports[2].bits.uop.is_rvc connect issue_slots[15].wakeup_ports[2].bits.uop.debug_inst, io.wakeup_ports[2].bits.uop.debug_inst connect issue_slots[15].wakeup_ports[2].bits.uop.inst, io.wakeup_ports[2].bits.uop.inst connect issue_slots[15].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[15].wakeup_ports[3].bits.rebusy, io.wakeup_ports[3].bits.rebusy connect issue_slots[15].wakeup_ports[3].bits.speculative_mask, io.wakeup_ports[3].bits.speculative_mask connect issue_slots[15].wakeup_ports[3].bits.bypassable, io.wakeup_ports[3].bits.bypassable connect issue_slots[15].wakeup_ports[3].bits.uop.debug_tsrc, io.wakeup_ports[3].bits.uop.debug_tsrc connect issue_slots[15].wakeup_ports[3].bits.uop.debug_fsrc, io.wakeup_ports[3].bits.uop.debug_fsrc connect issue_slots[15].wakeup_ports[3].bits.uop.bp_xcpt_if, io.wakeup_ports[3].bits.uop.bp_xcpt_if connect issue_slots[15].wakeup_ports[3].bits.uop.bp_debug_if, io.wakeup_ports[3].bits.uop.bp_debug_if connect issue_slots[15].wakeup_ports[3].bits.uop.xcpt_ma_if, io.wakeup_ports[3].bits.uop.xcpt_ma_if connect issue_slots[15].wakeup_ports[3].bits.uop.xcpt_ae_if, io.wakeup_ports[3].bits.uop.xcpt_ae_if connect issue_slots[15].wakeup_ports[3].bits.uop.xcpt_pf_if, io.wakeup_ports[3].bits.uop.xcpt_pf_if connect issue_slots[15].wakeup_ports[3].bits.uop.fp_typ, io.wakeup_ports[3].bits.uop.fp_typ connect issue_slots[15].wakeup_ports[3].bits.uop.fp_rm, io.wakeup_ports[3].bits.uop.fp_rm connect issue_slots[15].wakeup_ports[3].bits.uop.fp_val, io.wakeup_ports[3].bits.uop.fp_val connect issue_slots[15].wakeup_ports[3].bits.uop.fcn_op, io.wakeup_ports[3].bits.uop.fcn_op connect issue_slots[15].wakeup_ports[3].bits.uop.fcn_dw, io.wakeup_ports[3].bits.uop.fcn_dw connect issue_slots[15].wakeup_ports[3].bits.uop.frs3_en, io.wakeup_ports[3].bits.uop.frs3_en connect issue_slots[15].wakeup_ports[3].bits.uop.lrs2_rtype, io.wakeup_ports[3].bits.uop.lrs2_rtype connect issue_slots[15].wakeup_ports[3].bits.uop.lrs1_rtype, io.wakeup_ports[3].bits.uop.lrs1_rtype connect issue_slots[15].wakeup_ports[3].bits.uop.dst_rtype, io.wakeup_ports[3].bits.uop.dst_rtype connect issue_slots[15].wakeup_ports[3].bits.uop.lrs3, io.wakeup_ports[3].bits.uop.lrs3 connect issue_slots[15].wakeup_ports[3].bits.uop.lrs2, io.wakeup_ports[3].bits.uop.lrs2 connect issue_slots[15].wakeup_ports[3].bits.uop.lrs1, io.wakeup_ports[3].bits.uop.lrs1 connect issue_slots[15].wakeup_ports[3].bits.uop.ldst, io.wakeup_ports[3].bits.uop.ldst connect issue_slots[15].wakeup_ports[3].bits.uop.ldst_is_rs1, io.wakeup_ports[3].bits.uop.ldst_is_rs1 connect issue_slots[15].wakeup_ports[3].bits.uop.csr_cmd, io.wakeup_ports[3].bits.uop.csr_cmd connect issue_slots[15].wakeup_ports[3].bits.uop.flush_on_commit, io.wakeup_ports[3].bits.uop.flush_on_commit connect issue_slots[15].wakeup_ports[3].bits.uop.is_unique, io.wakeup_ports[3].bits.uop.is_unique connect issue_slots[15].wakeup_ports[3].bits.uop.uses_stq, io.wakeup_ports[3].bits.uop.uses_stq connect issue_slots[15].wakeup_ports[3].bits.uop.uses_ldq, io.wakeup_ports[3].bits.uop.uses_ldq connect issue_slots[15].wakeup_ports[3].bits.uop.mem_signed, io.wakeup_ports[3].bits.uop.mem_signed connect issue_slots[15].wakeup_ports[3].bits.uop.mem_size, io.wakeup_ports[3].bits.uop.mem_size connect issue_slots[15].wakeup_ports[3].bits.uop.mem_cmd, io.wakeup_ports[3].bits.uop.mem_cmd connect issue_slots[15].wakeup_ports[3].bits.uop.exc_cause, io.wakeup_ports[3].bits.uop.exc_cause connect issue_slots[15].wakeup_ports[3].bits.uop.exception, io.wakeup_ports[3].bits.uop.exception connect issue_slots[15].wakeup_ports[3].bits.uop.stale_pdst, io.wakeup_ports[3].bits.uop.stale_pdst connect issue_slots[15].wakeup_ports[3].bits.uop.ppred_busy, io.wakeup_ports[3].bits.uop.ppred_busy connect issue_slots[15].wakeup_ports[3].bits.uop.prs3_busy, io.wakeup_ports[3].bits.uop.prs3_busy connect issue_slots[15].wakeup_ports[3].bits.uop.prs2_busy, io.wakeup_ports[3].bits.uop.prs2_busy connect issue_slots[15].wakeup_ports[3].bits.uop.prs1_busy, io.wakeup_ports[3].bits.uop.prs1_busy connect issue_slots[15].wakeup_ports[3].bits.uop.ppred, io.wakeup_ports[3].bits.uop.ppred connect issue_slots[15].wakeup_ports[3].bits.uop.prs3, io.wakeup_ports[3].bits.uop.prs3 connect issue_slots[15].wakeup_ports[3].bits.uop.prs2, io.wakeup_ports[3].bits.uop.prs2 connect issue_slots[15].wakeup_ports[3].bits.uop.prs1, io.wakeup_ports[3].bits.uop.prs1 connect issue_slots[15].wakeup_ports[3].bits.uop.pdst, io.wakeup_ports[3].bits.uop.pdst connect issue_slots[15].wakeup_ports[3].bits.uop.rxq_idx, io.wakeup_ports[3].bits.uop.rxq_idx connect issue_slots[15].wakeup_ports[3].bits.uop.stq_idx, io.wakeup_ports[3].bits.uop.stq_idx connect issue_slots[15].wakeup_ports[3].bits.uop.ldq_idx, io.wakeup_ports[3].bits.uop.ldq_idx connect issue_slots[15].wakeup_ports[3].bits.uop.rob_idx, io.wakeup_ports[3].bits.uop.rob_idx connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.vec, io.wakeup_ports[3].bits.uop.fp_ctrl.vec connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.wflags, io.wakeup_ports[3].bits.uop.fp_ctrl.wflags connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.div, io.wakeup_ports[3].bits.uop.fp_ctrl.div connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.fma, io.wakeup_ports[3].bits.uop.fp_ctrl.fma connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.toint, io.wakeup_ports[3].bits.uop.fp_ctrl.toint connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.fromint, io.wakeup_ports[3].bits.uop.fp_ctrl.fromint connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.swap23, io.wakeup_ports[3].bits.uop.fp_ctrl.swap23 connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.swap12, io.wakeup_ports[3].bits.uop.fp_ctrl.swap12 connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.ren3, io.wakeup_ports[3].bits.uop.fp_ctrl.ren3 connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.ren2, io.wakeup_ports[3].bits.uop.fp_ctrl.ren2 connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.ren1, io.wakeup_ports[3].bits.uop.fp_ctrl.ren1 connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.wen, io.wakeup_ports[3].bits.uop.fp_ctrl.wen connect issue_slots[15].wakeup_ports[3].bits.uop.fp_ctrl.ldst, io.wakeup_ports[3].bits.uop.fp_ctrl.ldst connect issue_slots[15].wakeup_ports[3].bits.uop.op2_sel, io.wakeup_ports[3].bits.uop.op2_sel connect issue_slots[15].wakeup_ports[3].bits.uop.op1_sel, io.wakeup_ports[3].bits.uop.op1_sel connect issue_slots[15].wakeup_ports[3].bits.uop.imm_packed, io.wakeup_ports[3].bits.uop.imm_packed connect issue_slots[15].wakeup_ports[3].bits.uop.pimm, io.wakeup_ports[3].bits.uop.pimm connect issue_slots[15].wakeup_ports[3].bits.uop.imm_sel, io.wakeup_ports[3].bits.uop.imm_sel connect issue_slots[15].wakeup_ports[3].bits.uop.imm_rename, io.wakeup_ports[3].bits.uop.imm_rename connect issue_slots[15].wakeup_ports[3].bits.uop.taken, io.wakeup_ports[3].bits.uop.taken connect issue_slots[15].wakeup_ports[3].bits.uop.pc_lob, io.wakeup_ports[3].bits.uop.pc_lob connect issue_slots[15].wakeup_ports[3].bits.uop.edge_inst, io.wakeup_ports[3].bits.uop.edge_inst connect issue_slots[15].wakeup_ports[3].bits.uop.ftq_idx, io.wakeup_ports[3].bits.uop.ftq_idx connect issue_slots[15].wakeup_ports[3].bits.uop.is_mov, io.wakeup_ports[3].bits.uop.is_mov connect issue_slots[15].wakeup_ports[3].bits.uop.is_rocc, io.wakeup_ports[3].bits.uop.is_rocc connect issue_slots[15].wakeup_ports[3].bits.uop.is_sys_pc2epc, io.wakeup_ports[3].bits.uop.is_sys_pc2epc connect issue_slots[15].wakeup_ports[3].bits.uop.is_eret, io.wakeup_ports[3].bits.uop.is_eret connect issue_slots[15].wakeup_ports[3].bits.uop.is_amo, io.wakeup_ports[3].bits.uop.is_amo connect issue_slots[15].wakeup_ports[3].bits.uop.is_sfence, io.wakeup_ports[3].bits.uop.is_sfence connect issue_slots[15].wakeup_ports[3].bits.uop.is_fencei, io.wakeup_ports[3].bits.uop.is_fencei connect issue_slots[15].wakeup_ports[3].bits.uop.is_fence, io.wakeup_ports[3].bits.uop.is_fence connect issue_slots[15].wakeup_ports[3].bits.uop.is_sfb, io.wakeup_ports[3].bits.uop.is_sfb connect issue_slots[15].wakeup_ports[3].bits.uop.br_type, io.wakeup_ports[3].bits.uop.br_type connect issue_slots[15].wakeup_ports[3].bits.uop.br_tag, io.wakeup_ports[3].bits.uop.br_tag connect issue_slots[15].wakeup_ports[3].bits.uop.br_mask, io.wakeup_ports[3].bits.uop.br_mask connect issue_slots[15].wakeup_ports[3].bits.uop.dis_col_sel, io.wakeup_ports[3].bits.uop.dis_col_sel connect issue_slots[15].wakeup_ports[3].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint connect issue_slots[15].wakeup_ports[3].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint connect issue_slots[15].wakeup_ports[3].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint connect issue_slots[15].wakeup_ports[3].bits.uop.iw_p2_speculative_child, io.wakeup_ports[3].bits.uop.iw_p2_speculative_child connect issue_slots[15].wakeup_ports[3].bits.uop.iw_p1_speculative_child, io.wakeup_ports[3].bits.uop.iw_p1_speculative_child connect issue_slots[15].wakeup_ports[3].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen connect issue_slots[15].wakeup_ports[3].bits.uop.iw_issued_partial_agen, io.wakeup_ports[3].bits.uop.iw_issued_partial_agen connect issue_slots[15].wakeup_ports[3].bits.uop.iw_issued, io.wakeup_ports[3].bits.uop.iw_issued connect issue_slots[15].wakeup_ports[3].bits.uop.fu_code[0], io.wakeup_ports[3].bits.uop.fu_code[0] connect issue_slots[15].wakeup_ports[3].bits.uop.fu_code[1], io.wakeup_ports[3].bits.uop.fu_code[1] connect issue_slots[15].wakeup_ports[3].bits.uop.fu_code[2], io.wakeup_ports[3].bits.uop.fu_code[2] connect issue_slots[15].wakeup_ports[3].bits.uop.fu_code[3], io.wakeup_ports[3].bits.uop.fu_code[3] connect issue_slots[15].wakeup_ports[3].bits.uop.fu_code[4], io.wakeup_ports[3].bits.uop.fu_code[4] connect issue_slots[15].wakeup_ports[3].bits.uop.fu_code[5], io.wakeup_ports[3].bits.uop.fu_code[5] connect issue_slots[15].wakeup_ports[3].bits.uop.fu_code[6], io.wakeup_ports[3].bits.uop.fu_code[6] connect issue_slots[15].wakeup_ports[3].bits.uop.fu_code[7], io.wakeup_ports[3].bits.uop.fu_code[7] connect issue_slots[15].wakeup_ports[3].bits.uop.fu_code[8], io.wakeup_ports[3].bits.uop.fu_code[8] connect issue_slots[15].wakeup_ports[3].bits.uop.fu_code[9], io.wakeup_ports[3].bits.uop.fu_code[9] connect issue_slots[15].wakeup_ports[3].bits.uop.iq_type[0], io.wakeup_ports[3].bits.uop.iq_type[0] connect issue_slots[15].wakeup_ports[3].bits.uop.iq_type[1], io.wakeup_ports[3].bits.uop.iq_type[1] connect issue_slots[15].wakeup_ports[3].bits.uop.iq_type[2], io.wakeup_ports[3].bits.uop.iq_type[2] connect issue_slots[15].wakeup_ports[3].bits.uop.iq_type[3], io.wakeup_ports[3].bits.uop.iq_type[3] connect issue_slots[15].wakeup_ports[3].bits.uop.debug_pc, io.wakeup_ports[3].bits.uop.debug_pc connect issue_slots[15].wakeup_ports[3].bits.uop.is_rvc, io.wakeup_ports[3].bits.uop.is_rvc connect issue_slots[15].wakeup_ports[3].bits.uop.debug_inst, io.wakeup_ports[3].bits.uop.debug_inst connect issue_slots[15].wakeup_ports[3].bits.uop.inst, io.wakeup_ports[3].bits.uop.inst connect issue_slots[15].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[15].wakeup_ports[4].bits.rebusy, io.wakeup_ports[4].bits.rebusy connect issue_slots[15].wakeup_ports[4].bits.speculative_mask, io.wakeup_ports[4].bits.speculative_mask connect issue_slots[15].wakeup_ports[4].bits.bypassable, io.wakeup_ports[4].bits.bypassable connect issue_slots[15].wakeup_ports[4].bits.uop.debug_tsrc, io.wakeup_ports[4].bits.uop.debug_tsrc connect issue_slots[15].wakeup_ports[4].bits.uop.debug_fsrc, io.wakeup_ports[4].bits.uop.debug_fsrc connect issue_slots[15].wakeup_ports[4].bits.uop.bp_xcpt_if, io.wakeup_ports[4].bits.uop.bp_xcpt_if connect issue_slots[15].wakeup_ports[4].bits.uop.bp_debug_if, io.wakeup_ports[4].bits.uop.bp_debug_if connect issue_slots[15].wakeup_ports[4].bits.uop.xcpt_ma_if, io.wakeup_ports[4].bits.uop.xcpt_ma_if connect issue_slots[15].wakeup_ports[4].bits.uop.xcpt_ae_if, io.wakeup_ports[4].bits.uop.xcpt_ae_if connect issue_slots[15].wakeup_ports[4].bits.uop.xcpt_pf_if, io.wakeup_ports[4].bits.uop.xcpt_pf_if connect issue_slots[15].wakeup_ports[4].bits.uop.fp_typ, io.wakeup_ports[4].bits.uop.fp_typ connect issue_slots[15].wakeup_ports[4].bits.uop.fp_rm, io.wakeup_ports[4].bits.uop.fp_rm connect issue_slots[15].wakeup_ports[4].bits.uop.fp_val, io.wakeup_ports[4].bits.uop.fp_val connect issue_slots[15].wakeup_ports[4].bits.uop.fcn_op, io.wakeup_ports[4].bits.uop.fcn_op connect issue_slots[15].wakeup_ports[4].bits.uop.fcn_dw, io.wakeup_ports[4].bits.uop.fcn_dw connect issue_slots[15].wakeup_ports[4].bits.uop.frs3_en, io.wakeup_ports[4].bits.uop.frs3_en connect issue_slots[15].wakeup_ports[4].bits.uop.lrs2_rtype, io.wakeup_ports[4].bits.uop.lrs2_rtype connect issue_slots[15].wakeup_ports[4].bits.uop.lrs1_rtype, io.wakeup_ports[4].bits.uop.lrs1_rtype connect issue_slots[15].wakeup_ports[4].bits.uop.dst_rtype, io.wakeup_ports[4].bits.uop.dst_rtype connect issue_slots[15].wakeup_ports[4].bits.uop.lrs3, io.wakeup_ports[4].bits.uop.lrs3 connect issue_slots[15].wakeup_ports[4].bits.uop.lrs2, io.wakeup_ports[4].bits.uop.lrs2 connect issue_slots[15].wakeup_ports[4].bits.uop.lrs1, io.wakeup_ports[4].bits.uop.lrs1 connect issue_slots[15].wakeup_ports[4].bits.uop.ldst, io.wakeup_ports[4].bits.uop.ldst connect issue_slots[15].wakeup_ports[4].bits.uop.ldst_is_rs1, io.wakeup_ports[4].bits.uop.ldst_is_rs1 connect issue_slots[15].wakeup_ports[4].bits.uop.csr_cmd, io.wakeup_ports[4].bits.uop.csr_cmd connect issue_slots[15].wakeup_ports[4].bits.uop.flush_on_commit, io.wakeup_ports[4].bits.uop.flush_on_commit connect issue_slots[15].wakeup_ports[4].bits.uop.is_unique, io.wakeup_ports[4].bits.uop.is_unique connect issue_slots[15].wakeup_ports[4].bits.uop.uses_stq, io.wakeup_ports[4].bits.uop.uses_stq connect issue_slots[15].wakeup_ports[4].bits.uop.uses_ldq, io.wakeup_ports[4].bits.uop.uses_ldq connect issue_slots[15].wakeup_ports[4].bits.uop.mem_signed, io.wakeup_ports[4].bits.uop.mem_signed connect issue_slots[15].wakeup_ports[4].bits.uop.mem_size, io.wakeup_ports[4].bits.uop.mem_size connect issue_slots[15].wakeup_ports[4].bits.uop.mem_cmd, io.wakeup_ports[4].bits.uop.mem_cmd connect issue_slots[15].wakeup_ports[4].bits.uop.exc_cause, io.wakeup_ports[4].bits.uop.exc_cause connect issue_slots[15].wakeup_ports[4].bits.uop.exception, io.wakeup_ports[4].bits.uop.exception connect issue_slots[15].wakeup_ports[4].bits.uop.stale_pdst, io.wakeup_ports[4].bits.uop.stale_pdst connect issue_slots[15].wakeup_ports[4].bits.uop.ppred_busy, io.wakeup_ports[4].bits.uop.ppred_busy connect issue_slots[15].wakeup_ports[4].bits.uop.prs3_busy, io.wakeup_ports[4].bits.uop.prs3_busy connect issue_slots[15].wakeup_ports[4].bits.uop.prs2_busy, io.wakeup_ports[4].bits.uop.prs2_busy connect issue_slots[15].wakeup_ports[4].bits.uop.prs1_busy, io.wakeup_ports[4].bits.uop.prs1_busy connect issue_slots[15].wakeup_ports[4].bits.uop.ppred, io.wakeup_ports[4].bits.uop.ppred connect issue_slots[15].wakeup_ports[4].bits.uop.prs3, io.wakeup_ports[4].bits.uop.prs3 connect issue_slots[15].wakeup_ports[4].bits.uop.prs2, io.wakeup_ports[4].bits.uop.prs2 connect issue_slots[15].wakeup_ports[4].bits.uop.prs1, io.wakeup_ports[4].bits.uop.prs1 connect issue_slots[15].wakeup_ports[4].bits.uop.pdst, io.wakeup_ports[4].bits.uop.pdst connect issue_slots[15].wakeup_ports[4].bits.uop.rxq_idx, io.wakeup_ports[4].bits.uop.rxq_idx connect issue_slots[15].wakeup_ports[4].bits.uop.stq_idx, io.wakeup_ports[4].bits.uop.stq_idx connect issue_slots[15].wakeup_ports[4].bits.uop.ldq_idx, io.wakeup_ports[4].bits.uop.ldq_idx connect issue_slots[15].wakeup_ports[4].bits.uop.rob_idx, io.wakeup_ports[4].bits.uop.rob_idx connect issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.vec, io.wakeup_ports[4].bits.uop.fp_ctrl.vec connect issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.wflags, io.wakeup_ports[4].bits.uop.fp_ctrl.wflags connect issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[4].bits.uop.fp_ctrl.sqrt connect issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.div, io.wakeup_ports[4].bits.uop.fp_ctrl.div connect issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.fma, io.wakeup_ports[4].bits.uop.fp_ctrl.fma connect issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[4].bits.uop.fp_ctrl.fastpipe connect issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.toint, io.wakeup_ports[4].bits.uop.fp_ctrl.toint connect issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.fromint, io.wakeup_ports[4].bits.uop.fp_ctrl.fromint connect issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagOut connect issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[4].bits.uop.fp_ctrl.typeTagIn connect issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.swap23, io.wakeup_ports[4].bits.uop.fp_ctrl.swap23 connect issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.swap12, io.wakeup_ports[4].bits.uop.fp_ctrl.swap12 connect issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.ren3, io.wakeup_ports[4].bits.uop.fp_ctrl.ren3 connect issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.ren2, io.wakeup_ports[4].bits.uop.fp_ctrl.ren2 connect issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.ren1, io.wakeup_ports[4].bits.uop.fp_ctrl.ren1 connect issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.wen, io.wakeup_ports[4].bits.uop.fp_ctrl.wen connect issue_slots[15].wakeup_ports[4].bits.uop.fp_ctrl.ldst, io.wakeup_ports[4].bits.uop.fp_ctrl.ldst connect issue_slots[15].wakeup_ports[4].bits.uop.op2_sel, io.wakeup_ports[4].bits.uop.op2_sel connect issue_slots[15].wakeup_ports[4].bits.uop.op1_sel, io.wakeup_ports[4].bits.uop.op1_sel connect issue_slots[15].wakeup_ports[4].bits.uop.imm_packed, io.wakeup_ports[4].bits.uop.imm_packed connect issue_slots[15].wakeup_ports[4].bits.uop.pimm, io.wakeup_ports[4].bits.uop.pimm connect issue_slots[15].wakeup_ports[4].bits.uop.imm_sel, io.wakeup_ports[4].bits.uop.imm_sel connect issue_slots[15].wakeup_ports[4].bits.uop.imm_rename, io.wakeup_ports[4].bits.uop.imm_rename connect issue_slots[15].wakeup_ports[4].bits.uop.taken, io.wakeup_ports[4].bits.uop.taken connect issue_slots[15].wakeup_ports[4].bits.uop.pc_lob, io.wakeup_ports[4].bits.uop.pc_lob connect issue_slots[15].wakeup_ports[4].bits.uop.edge_inst, io.wakeup_ports[4].bits.uop.edge_inst connect issue_slots[15].wakeup_ports[4].bits.uop.ftq_idx, io.wakeup_ports[4].bits.uop.ftq_idx connect issue_slots[15].wakeup_ports[4].bits.uop.is_mov, io.wakeup_ports[4].bits.uop.is_mov connect issue_slots[15].wakeup_ports[4].bits.uop.is_rocc, io.wakeup_ports[4].bits.uop.is_rocc connect issue_slots[15].wakeup_ports[4].bits.uop.is_sys_pc2epc, io.wakeup_ports[4].bits.uop.is_sys_pc2epc connect issue_slots[15].wakeup_ports[4].bits.uop.is_eret, io.wakeup_ports[4].bits.uop.is_eret connect issue_slots[15].wakeup_ports[4].bits.uop.is_amo, io.wakeup_ports[4].bits.uop.is_amo connect issue_slots[15].wakeup_ports[4].bits.uop.is_sfence, io.wakeup_ports[4].bits.uop.is_sfence connect issue_slots[15].wakeup_ports[4].bits.uop.is_fencei, io.wakeup_ports[4].bits.uop.is_fencei connect issue_slots[15].wakeup_ports[4].bits.uop.is_fence, io.wakeup_ports[4].bits.uop.is_fence connect issue_slots[15].wakeup_ports[4].bits.uop.is_sfb, io.wakeup_ports[4].bits.uop.is_sfb connect issue_slots[15].wakeup_ports[4].bits.uop.br_type, io.wakeup_ports[4].bits.uop.br_type connect issue_slots[15].wakeup_ports[4].bits.uop.br_tag, io.wakeup_ports[4].bits.uop.br_tag connect issue_slots[15].wakeup_ports[4].bits.uop.br_mask, io.wakeup_ports[4].bits.uop.br_mask connect issue_slots[15].wakeup_ports[4].bits.uop.dis_col_sel, io.wakeup_ports[4].bits.uop.dis_col_sel connect issue_slots[15].wakeup_ports[4].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p3_bypass_hint connect issue_slots[15].wakeup_ports[4].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p2_bypass_hint connect issue_slots[15].wakeup_ports[4].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[4].bits.uop.iw_p1_bypass_hint connect issue_slots[15].wakeup_ports[4].bits.uop.iw_p2_speculative_child, io.wakeup_ports[4].bits.uop.iw_p2_speculative_child connect issue_slots[15].wakeup_ports[4].bits.uop.iw_p1_speculative_child, io.wakeup_ports[4].bits.uop.iw_p1_speculative_child connect issue_slots[15].wakeup_ports[4].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[4].bits.uop.iw_issued_partial_dgen connect issue_slots[15].wakeup_ports[4].bits.uop.iw_issued_partial_agen, io.wakeup_ports[4].bits.uop.iw_issued_partial_agen connect issue_slots[15].wakeup_ports[4].bits.uop.iw_issued, io.wakeup_ports[4].bits.uop.iw_issued connect issue_slots[15].wakeup_ports[4].bits.uop.fu_code[0], io.wakeup_ports[4].bits.uop.fu_code[0] connect issue_slots[15].wakeup_ports[4].bits.uop.fu_code[1], io.wakeup_ports[4].bits.uop.fu_code[1] connect issue_slots[15].wakeup_ports[4].bits.uop.fu_code[2], io.wakeup_ports[4].bits.uop.fu_code[2] connect issue_slots[15].wakeup_ports[4].bits.uop.fu_code[3], io.wakeup_ports[4].bits.uop.fu_code[3] connect issue_slots[15].wakeup_ports[4].bits.uop.fu_code[4], io.wakeup_ports[4].bits.uop.fu_code[4] connect issue_slots[15].wakeup_ports[4].bits.uop.fu_code[5], io.wakeup_ports[4].bits.uop.fu_code[5] connect issue_slots[15].wakeup_ports[4].bits.uop.fu_code[6], io.wakeup_ports[4].bits.uop.fu_code[6] connect issue_slots[15].wakeup_ports[4].bits.uop.fu_code[7], io.wakeup_ports[4].bits.uop.fu_code[7] connect issue_slots[15].wakeup_ports[4].bits.uop.fu_code[8], io.wakeup_ports[4].bits.uop.fu_code[8] connect issue_slots[15].wakeup_ports[4].bits.uop.fu_code[9], io.wakeup_ports[4].bits.uop.fu_code[9] connect issue_slots[15].wakeup_ports[4].bits.uop.iq_type[0], io.wakeup_ports[4].bits.uop.iq_type[0] connect issue_slots[15].wakeup_ports[4].bits.uop.iq_type[1], io.wakeup_ports[4].bits.uop.iq_type[1] connect issue_slots[15].wakeup_ports[4].bits.uop.iq_type[2], io.wakeup_ports[4].bits.uop.iq_type[2] connect issue_slots[15].wakeup_ports[4].bits.uop.iq_type[3], io.wakeup_ports[4].bits.uop.iq_type[3] connect issue_slots[15].wakeup_ports[4].bits.uop.debug_pc, io.wakeup_ports[4].bits.uop.debug_pc connect issue_slots[15].wakeup_ports[4].bits.uop.is_rvc, io.wakeup_ports[4].bits.uop.is_rvc connect issue_slots[15].wakeup_ports[4].bits.uop.debug_inst, io.wakeup_ports[4].bits.uop.debug_inst connect issue_slots[15].wakeup_ports[4].bits.uop.inst, io.wakeup_ports[4].bits.uop.inst connect issue_slots[15].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[15].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[15].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[15].child_rebusys, io.child_rebusys connect issue_slots[15].squash_grant, io.squash_grant connect issue_slots[15].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[15].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[15].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[15].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[15].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[15].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[15].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[15].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[15].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[15].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[15].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[15].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[15].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[15].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect issue_slots[15].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect issue_slots[15].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[15].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect issue_slots[15].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect issue_slots[15].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[15].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[15].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[15].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[15].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[15].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[15].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[15].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[15].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[15].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect issue_slots[15].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[15].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[15].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[15].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[15].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[15].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[15].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[15].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[15].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[15].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[15].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[15].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[15].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[15].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[15].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[15].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[15].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[15].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[15].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[15].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[15].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[15].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[15].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[15].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect issue_slots[15].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect issue_slots[15].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect issue_slots[15].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect issue_slots[15].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect issue_slots[15].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect issue_slots[15].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect issue_slots[15].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect issue_slots[15].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect issue_slots[15].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect issue_slots[15].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect issue_slots[15].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect issue_slots[15].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect issue_slots[15].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect issue_slots[15].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect issue_slots[15].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect issue_slots[15].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect issue_slots[15].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect issue_slots[15].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect issue_slots[15].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[15].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect issue_slots[15].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect issue_slots[15].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect issue_slots[15].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[15].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[15].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[15].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[15].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect issue_slots[15].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect issue_slots[15].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[15].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect issue_slots[15].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[15].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect issue_slots[15].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[15].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[15].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[15].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect issue_slots[15].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[15].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[15].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect issue_slots[15].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect issue_slots[15].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect issue_slots[15].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect issue_slots[15].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect issue_slots[15].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect issue_slots[15].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect issue_slots[15].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect issue_slots[15].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect issue_slots[15].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect issue_slots[15].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect issue_slots[15].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect issue_slots[15].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect issue_slots[15].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect issue_slots[15].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect issue_slots[15].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect issue_slots[15].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect issue_slots[15].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect issue_slots[15].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect issue_slots[15].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect issue_slots[15].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect issue_slots[15].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect issue_slots[15].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect issue_slots[15].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[15].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[15].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[15].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[15].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[15].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[15].kill, io.flush_pipeline connect io.iss_uops[0].valid, UInt<1>(0h0) node _T_243 = add(issue_slots[0].grant, issue_slots[1].grant) node _T_244 = bits(_T_243, 1, 0) node _T_245 = add(issue_slots[2].grant, issue_slots[3].grant) node _T_246 = bits(_T_245, 1, 0) node _T_247 = add(_T_244, _T_246) node _T_248 = bits(_T_247, 2, 0) node _T_249 = add(issue_slots[4].grant, issue_slots[5].grant) node _T_250 = bits(_T_249, 1, 0) node _T_251 = add(issue_slots[6].grant, issue_slots[7].grant) node _T_252 = bits(_T_251, 1, 0) node _T_253 = add(_T_250, _T_252) node _T_254 = bits(_T_253, 2, 0) node _T_255 = add(_T_248, _T_254) node _T_256 = bits(_T_255, 3, 0) node _T_257 = add(issue_slots[8].grant, issue_slots[9].grant) node _T_258 = bits(_T_257, 1, 0) node _T_259 = add(issue_slots[10].grant, issue_slots[11].grant) node _T_260 = bits(_T_259, 1, 0) node _T_261 = add(_T_258, _T_260) node _T_262 = bits(_T_261, 2, 0) node _T_263 = add(issue_slots[12].grant, issue_slots[13].grant) node _T_264 = bits(_T_263, 1, 0) node _T_265 = add(issue_slots[14].grant, issue_slots[15].grant) node _T_266 = bits(_T_265, 1, 0) node _T_267 = add(_T_264, _T_266) node _T_268 = bits(_T_267, 2, 0) node _T_269 = add(_T_262, _T_268) node _T_270 = bits(_T_269, 3, 0) node _T_271 = add(_T_256, _T_270) node _T_272 = bits(_T_271, 4, 0) node _T_273 = leq(_T_272, UInt<1>(0h1)) node _T_274 = asUInt(reset) node _T_275 = eq(_T_274, UInt<1>(0h0)) when _T_275 : node _T_276 = eq(_T_273, UInt<1>(0h0)) when _T_276 : printf(clock, UInt<1>(0h1), "Assertion failed: [issue] window giving out too many grants.\n at issue-unit-age-ordered.scala:141 assert (PopCount(issue_slots.map(s => s.grant)) <= issueWidth.U, \"[issue] window giving out too many grants.\")\n") : printf_3 assert(clock, _T_273, UInt<1>(0h1), "") : assert_3 node vacants_0 = eq(issue_slots[0].valid, UInt<1>(0h0)) node vacants_1 = eq(issue_slots[1].valid, UInt<1>(0h0)) node vacants_2 = eq(issue_slots[2].valid, UInt<1>(0h0)) node vacants_3 = eq(issue_slots[3].valid, UInt<1>(0h0)) node vacants_4 = eq(issue_slots[4].valid, UInt<1>(0h0)) node vacants_5 = eq(issue_slots[5].valid, UInt<1>(0h0)) node vacants_6 = eq(issue_slots[6].valid, UInt<1>(0h0)) node vacants_7 = eq(issue_slots[7].valid, UInt<1>(0h0)) node vacants_8 = eq(issue_slots[8].valid, UInt<1>(0h0)) node vacants_9 = eq(issue_slots[9].valid, UInt<1>(0h0)) node vacants_10 = eq(issue_slots[10].valid, UInt<1>(0h0)) node vacants_11 = eq(issue_slots[11].valid, UInt<1>(0h0)) node vacants_12 = eq(issue_slots[12].valid, UInt<1>(0h0)) node vacants_13 = eq(issue_slots[13].valid, UInt<1>(0h0)) node vacants_14 = eq(issue_slots[14].valid, UInt<1>(0h0)) node vacants_15 = eq(issue_slots[15].valid, UInt<1>(0h0)) node vacants_16 = eq(io.dis_uops[0].valid, UInt<1>(0h0)) node vacants_17 = eq(io.dis_uops[1].valid, UInt<1>(0h0)) node vacants_18 = eq(io.dis_uops[2].valid, UInt<1>(0h0)) wire shamts_oh : UInt<3>[19] connect shamts_oh[0], UInt<1>(0h0) connect shamts_oh[1], vacants_0 node _shamts_oh_2_T = or(vacants_0, vacants_1) connect shamts_oh[2], _shamts_oh_2_T node _shamts_oh_3_T = or(vacants_0, vacants_1) node _shamts_oh_3_T_1 = or(_shamts_oh_3_T, vacants_2) connect shamts_oh[3], _shamts_oh_3_T_1 wire shamts_oh_4_next : UInt<2> connect shamts_oh_4_next, shamts_oh[3] node _shamts_oh_4_T = eq(shamts_oh[3], UInt<1>(0h0)) node _shamts_oh_4_T_1 = and(_shamts_oh_4_T, vacants_3) when _shamts_oh_4_T_1 : connect shamts_oh_4_next, UInt<1>(0h1) else : node _shamts_oh_4_T_2 = bits(shamts_oh[3], 1, 1) node _shamts_oh_4_T_3 = eq(_shamts_oh_4_T_2, UInt<1>(0h0)) node _shamts_oh_4_T_4 = and(_shamts_oh_4_T_3, vacants_3) when _shamts_oh_4_T_4 : node _shamts_oh_4_next_T = dshl(shamts_oh[3], UInt<1>(0h1)) connect shamts_oh_4_next, _shamts_oh_4_next_T connect shamts_oh[4], shamts_oh_4_next wire shamts_oh_5_next : UInt<2> connect shamts_oh_5_next, shamts_oh[4] node _shamts_oh_5_T = eq(shamts_oh[4], UInt<1>(0h0)) node _shamts_oh_5_T_1 = and(_shamts_oh_5_T, vacants_4) when _shamts_oh_5_T_1 : connect shamts_oh_5_next, UInt<1>(0h1) else : node _shamts_oh_5_T_2 = bits(shamts_oh[4], 1, 1) node _shamts_oh_5_T_3 = eq(_shamts_oh_5_T_2, UInt<1>(0h0)) node _shamts_oh_5_T_4 = and(_shamts_oh_5_T_3, vacants_4) when _shamts_oh_5_T_4 : node _shamts_oh_5_next_T = dshl(shamts_oh[4], UInt<1>(0h1)) connect shamts_oh_5_next, _shamts_oh_5_next_T connect shamts_oh[5], shamts_oh_5_next wire shamts_oh_6_next : UInt<2> connect shamts_oh_6_next, shamts_oh[5] node _shamts_oh_6_T = eq(shamts_oh[5], UInt<1>(0h0)) node _shamts_oh_6_T_1 = and(_shamts_oh_6_T, vacants_5) when _shamts_oh_6_T_1 : connect shamts_oh_6_next, UInt<1>(0h1) else : node _shamts_oh_6_T_2 = bits(shamts_oh[5], 1, 1) node _shamts_oh_6_T_3 = eq(_shamts_oh_6_T_2, UInt<1>(0h0)) node _shamts_oh_6_T_4 = and(_shamts_oh_6_T_3, vacants_5) when _shamts_oh_6_T_4 : node _shamts_oh_6_next_T = dshl(shamts_oh[5], UInt<1>(0h1)) connect shamts_oh_6_next, _shamts_oh_6_next_T connect shamts_oh[6], shamts_oh_6_next wire shamts_oh_7_next : UInt<2> connect shamts_oh_7_next, shamts_oh[6] node _shamts_oh_7_T = eq(shamts_oh[6], UInt<1>(0h0)) node _shamts_oh_7_T_1 = and(_shamts_oh_7_T, vacants_6) when _shamts_oh_7_T_1 : connect shamts_oh_7_next, UInt<1>(0h1) else : node _shamts_oh_7_T_2 = bits(shamts_oh[6], 1, 1) node _shamts_oh_7_T_3 = eq(_shamts_oh_7_T_2, UInt<1>(0h0)) node _shamts_oh_7_T_4 = and(_shamts_oh_7_T_3, vacants_6) when _shamts_oh_7_T_4 : node _shamts_oh_7_next_T = dshl(shamts_oh[6], UInt<1>(0h1)) connect shamts_oh_7_next, _shamts_oh_7_next_T connect shamts_oh[7], shamts_oh_7_next wire shamts_oh_8_next : UInt<3> connect shamts_oh_8_next, shamts_oh[7] node _shamts_oh_8_T = eq(shamts_oh[7], UInt<1>(0h0)) node _shamts_oh_8_T_1 = and(_shamts_oh_8_T, vacants_7) when _shamts_oh_8_T_1 : connect shamts_oh_8_next, UInt<1>(0h1) else : node _shamts_oh_8_T_2 = bits(shamts_oh[7], 2, 2) node _shamts_oh_8_T_3 = eq(_shamts_oh_8_T_2, UInt<1>(0h0)) node _shamts_oh_8_T_4 = and(_shamts_oh_8_T_3, vacants_7) when _shamts_oh_8_T_4 : node _shamts_oh_8_next_T = dshl(shamts_oh[7], UInt<1>(0h1)) connect shamts_oh_8_next, _shamts_oh_8_next_T connect shamts_oh[8], shamts_oh_8_next wire shamts_oh_9_next : UInt<3> connect shamts_oh_9_next, shamts_oh[8] node _shamts_oh_9_T = eq(shamts_oh[8], UInt<1>(0h0)) node _shamts_oh_9_T_1 = and(_shamts_oh_9_T, vacants_8) when _shamts_oh_9_T_1 : connect shamts_oh_9_next, UInt<1>(0h1) else : node _shamts_oh_9_T_2 = bits(shamts_oh[8], 2, 2) node _shamts_oh_9_T_3 = eq(_shamts_oh_9_T_2, UInt<1>(0h0)) node _shamts_oh_9_T_4 = and(_shamts_oh_9_T_3, vacants_8) when _shamts_oh_9_T_4 : node _shamts_oh_9_next_T = dshl(shamts_oh[8], UInt<1>(0h1)) connect shamts_oh_9_next, _shamts_oh_9_next_T connect shamts_oh[9], shamts_oh_9_next wire shamts_oh_10_next : UInt<3> connect shamts_oh_10_next, shamts_oh[9] node _shamts_oh_10_T = eq(shamts_oh[9], UInt<1>(0h0)) node _shamts_oh_10_T_1 = and(_shamts_oh_10_T, vacants_9) when _shamts_oh_10_T_1 : connect shamts_oh_10_next, UInt<1>(0h1) else : node _shamts_oh_10_T_2 = bits(shamts_oh[9], 2, 2) node _shamts_oh_10_T_3 = eq(_shamts_oh_10_T_2, UInt<1>(0h0)) node _shamts_oh_10_T_4 = and(_shamts_oh_10_T_3, vacants_9) when _shamts_oh_10_T_4 : node _shamts_oh_10_next_T = dshl(shamts_oh[9], UInt<1>(0h1)) connect shamts_oh_10_next, _shamts_oh_10_next_T connect shamts_oh[10], shamts_oh_10_next wire shamts_oh_11_next : UInt<3> connect shamts_oh_11_next, shamts_oh[10] node _shamts_oh_11_T = eq(shamts_oh[10], UInt<1>(0h0)) node _shamts_oh_11_T_1 = and(_shamts_oh_11_T, vacants_10) when _shamts_oh_11_T_1 : connect shamts_oh_11_next, UInt<1>(0h1) else : node _shamts_oh_11_T_2 = bits(shamts_oh[10], 2, 2) node _shamts_oh_11_T_3 = eq(_shamts_oh_11_T_2, UInt<1>(0h0)) node _shamts_oh_11_T_4 = and(_shamts_oh_11_T_3, vacants_10) when _shamts_oh_11_T_4 : node _shamts_oh_11_next_T = dshl(shamts_oh[10], UInt<1>(0h1)) connect shamts_oh_11_next, _shamts_oh_11_next_T connect shamts_oh[11], shamts_oh_11_next wire shamts_oh_12_next : UInt<3> connect shamts_oh_12_next, shamts_oh[11] node _shamts_oh_12_T = eq(shamts_oh[11], UInt<1>(0h0)) node _shamts_oh_12_T_1 = and(_shamts_oh_12_T, vacants_11) when _shamts_oh_12_T_1 : connect shamts_oh_12_next, UInt<1>(0h1) else : node _shamts_oh_12_T_2 = bits(shamts_oh[11], 2, 2) node _shamts_oh_12_T_3 = eq(_shamts_oh_12_T_2, UInt<1>(0h0)) node _shamts_oh_12_T_4 = and(_shamts_oh_12_T_3, vacants_11) when _shamts_oh_12_T_4 : node _shamts_oh_12_next_T = dshl(shamts_oh[11], UInt<1>(0h1)) connect shamts_oh_12_next, _shamts_oh_12_next_T connect shamts_oh[12], shamts_oh_12_next wire shamts_oh_13_next : UInt<3> connect shamts_oh_13_next, shamts_oh[12] node _shamts_oh_13_T = eq(shamts_oh[12], UInt<1>(0h0)) node _shamts_oh_13_T_1 = and(_shamts_oh_13_T, vacants_12) when _shamts_oh_13_T_1 : connect shamts_oh_13_next, UInt<1>(0h1) else : node _shamts_oh_13_T_2 = bits(shamts_oh[12], 2, 2) node _shamts_oh_13_T_3 = eq(_shamts_oh_13_T_2, UInt<1>(0h0)) node _shamts_oh_13_T_4 = and(_shamts_oh_13_T_3, vacants_12) when _shamts_oh_13_T_4 : node _shamts_oh_13_next_T = dshl(shamts_oh[12], UInt<1>(0h1)) connect shamts_oh_13_next, _shamts_oh_13_next_T connect shamts_oh[13], shamts_oh_13_next wire shamts_oh_14_next : UInt<3> connect shamts_oh_14_next, shamts_oh[13] node _shamts_oh_14_T = eq(shamts_oh[13], UInt<1>(0h0)) node _shamts_oh_14_T_1 = and(_shamts_oh_14_T, vacants_13) when _shamts_oh_14_T_1 : connect shamts_oh_14_next, UInt<1>(0h1) else : node _shamts_oh_14_T_2 = bits(shamts_oh[13], 2, 2) node _shamts_oh_14_T_3 = eq(_shamts_oh_14_T_2, UInt<1>(0h0)) node _shamts_oh_14_T_4 = and(_shamts_oh_14_T_3, vacants_13) when _shamts_oh_14_T_4 : node _shamts_oh_14_next_T = dshl(shamts_oh[13], UInt<1>(0h1)) connect shamts_oh_14_next, _shamts_oh_14_next_T connect shamts_oh[14], shamts_oh_14_next wire shamts_oh_15_next : UInt<3> connect shamts_oh_15_next, shamts_oh[14] node _shamts_oh_15_T = eq(shamts_oh[14], UInt<1>(0h0)) node _shamts_oh_15_T_1 = and(_shamts_oh_15_T, vacants_14) when _shamts_oh_15_T_1 : connect shamts_oh_15_next, UInt<1>(0h1) else : node _shamts_oh_15_T_2 = bits(shamts_oh[14], 2, 2) node _shamts_oh_15_T_3 = eq(_shamts_oh_15_T_2, UInt<1>(0h0)) node _shamts_oh_15_T_4 = and(_shamts_oh_15_T_3, vacants_14) when _shamts_oh_15_T_4 : node _shamts_oh_15_next_T = dshl(shamts_oh[14], UInt<1>(0h1)) connect shamts_oh_15_next, _shamts_oh_15_next_T connect shamts_oh[15], shamts_oh_15_next wire shamts_oh_16_next : UInt<3> connect shamts_oh_16_next, shamts_oh[15] node _shamts_oh_16_T = eq(shamts_oh[15], UInt<1>(0h0)) node _shamts_oh_16_T_1 = and(_shamts_oh_16_T, vacants_15) when _shamts_oh_16_T_1 : connect shamts_oh_16_next, UInt<1>(0h1) else : node _shamts_oh_16_T_2 = bits(shamts_oh[15], 2, 2) node _shamts_oh_16_T_3 = eq(_shamts_oh_16_T_2, UInt<1>(0h0)) node _shamts_oh_16_T_4 = and(_shamts_oh_16_T_3, vacants_15) when _shamts_oh_16_T_4 : node _shamts_oh_16_next_T = dshl(shamts_oh[15], UInt<1>(0h1)) connect shamts_oh_16_next, _shamts_oh_16_next_T connect shamts_oh[16], shamts_oh_16_next wire shamts_oh_17_next : UInt<3> connect shamts_oh_17_next, shamts_oh[16] node _shamts_oh_17_T = eq(shamts_oh[16], UInt<1>(0h0)) node _shamts_oh_17_T_1 = and(_shamts_oh_17_T, vacants_16) when _shamts_oh_17_T_1 : connect shamts_oh_17_next, UInt<1>(0h1) else : node _shamts_oh_17_T_2 = bits(shamts_oh[16], 2, 2) node _shamts_oh_17_T_3 = eq(_shamts_oh_17_T_2, UInt<1>(0h0)) node _shamts_oh_17_T_4 = and(_shamts_oh_17_T_3, vacants_16) when _shamts_oh_17_T_4 : node _shamts_oh_17_next_T = dshl(shamts_oh[16], UInt<1>(0h1)) connect shamts_oh_17_next, _shamts_oh_17_next_T connect shamts_oh[17], shamts_oh_17_next wire shamts_oh_18_next : UInt<3> connect shamts_oh_18_next, shamts_oh[17] node _shamts_oh_18_T = eq(shamts_oh[17], UInt<1>(0h0)) node _shamts_oh_18_T_1 = and(_shamts_oh_18_T, vacants_17) when _shamts_oh_18_T_1 : connect shamts_oh_18_next, UInt<1>(0h1) else : node _shamts_oh_18_T_2 = bits(shamts_oh[17], 2, 2) node _shamts_oh_18_T_3 = eq(_shamts_oh_18_T_2, UInt<1>(0h0)) node _shamts_oh_18_T_4 = and(_shamts_oh_18_T_3, vacants_17) when _shamts_oh_18_T_4 : node _shamts_oh_18_next_T = dshl(shamts_oh[17], UInt<1>(0h1)) connect shamts_oh_18_next, _shamts_oh_18_next_T connect shamts_oh[18], shamts_oh_18_next node _will_be_valid_T = eq(_WIRE.exception, UInt<1>(0h0)) node _will_be_valid_T_1 = and(io.dis_uops[0].valid, _will_be_valid_T) node _will_be_valid_T_2 = eq(_WIRE.is_fence, UInt<1>(0h0)) node _will_be_valid_T_3 = and(_will_be_valid_T_1, _will_be_valid_T_2) node _will_be_valid_T_4 = eq(_WIRE.is_fencei, UInt<1>(0h0)) node will_be_valid_16 = and(_will_be_valid_T_3, _will_be_valid_T_4) node _will_be_valid_T_5 = eq(_WIRE_1.exception, UInt<1>(0h0)) node _will_be_valid_T_6 = and(io.dis_uops[1].valid, _will_be_valid_T_5) node _will_be_valid_T_7 = eq(_WIRE_1.is_fence, UInt<1>(0h0)) node _will_be_valid_T_8 = and(_will_be_valid_T_6, _will_be_valid_T_7) node _will_be_valid_T_9 = eq(_WIRE_1.is_fencei, UInt<1>(0h0)) node will_be_valid_17 = and(_will_be_valid_T_8, _will_be_valid_T_9) node _will_be_valid_T_10 = eq(_WIRE_2.exception, UInt<1>(0h0)) node _will_be_valid_T_11 = and(io.dis_uops[2].valid, _will_be_valid_T_10) node _will_be_valid_T_12 = eq(_WIRE_2.is_fence, UInt<1>(0h0)) node _will_be_valid_T_13 = and(_will_be_valid_T_11, _will_be_valid_T_12) node _will_be_valid_T_14 = eq(_WIRE_2.is_fencei, UInt<1>(0h0)) node will_be_valid_18 = and(_will_be_valid_T_13, _will_be_valid_T_14) connect issue_slots[0].in_uop.valid, UInt<1>(0h0) connect issue_slots[0].in_uop.bits.debug_tsrc, issue_slots[1].out_uop.debug_tsrc connect issue_slots[0].in_uop.bits.debug_fsrc, issue_slots[1].out_uop.debug_fsrc connect issue_slots[0].in_uop.bits.bp_xcpt_if, issue_slots[1].out_uop.bp_xcpt_if connect issue_slots[0].in_uop.bits.bp_debug_if, issue_slots[1].out_uop.bp_debug_if connect issue_slots[0].in_uop.bits.xcpt_ma_if, issue_slots[1].out_uop.xcpt_ma_if connect issue_slots[0].in_uop.bits.xcpt_ae_if, issue_slots[1].out_uop.xcpt_ae_if connect issue_slots[0].in_uop.bits.xcpt_pf_if, issue_slots[1].out_uop.xcpt_pf_if connect issue_slots[0].in_uop.bits.fp_typ, issue_slots[1].out_uop.fp_typ connect issue_slots[0].in_uop.bits.fp_rm, issue_slots[1].out_uop.fp_rm connect issue_slots[0].in_uop.bits.fp_val, issue_slots[1].out_uop.fp_val connect issue_slots[0].in_uop.bits.fcn_op, issue_slots[1].out_uop.fcn_op connect issue_slots[0].in_uop.bits.fcn_dw, issue_slots[1].out_uop.fcn_dw connect issue_slots[0].in_uop.bits.frs3_en, issue_slots[1].out_uop.frs3_en connect issue_slots[0].in_uop.bits.lrs2_rtype, issue_slots[1].out_uop.lrs2_rtype connect issue_slots[0].in_uop.bits.lrs1_rtype, issue_slots[1].out_uop.lrs1_rtype connect issue_slots[0].in_uop.bits.dst_rtype, issue_slots[1].out_uop.dst_rtype connect issue_slots[0].in_uop.bits.lrs3, issue_slots[1].out_uop.lrs3 connect issue_slots[0].in_uop.bits.lrs2, issue_slots[1].out_uop.lrs2 connect issue_slots[0].in_uop.bits.lrs1, issue_slots[1].out_uop.lrs1 connect issue_slots[0].in_uop.bits.ldst, issue_slots[1].out_uop.ldst connect issue_slots[0].in_uop.bits.ldst_is_rs1, issue_slots[1].out_uop.ldst_is_rs1 connect issue_slots[0].in_uop.bits.csr_cmd, issue_slots[1].out_uop.csr_cmd connect issue_slots[0].in_uop.bits.flush_on_commit, issue_slots[1].out_uop.flush_on_commit connect issue_slots[0].in_uop.bits.is_unique, issue_slots[1].out_uop.is_unique connect issue_slots[0].in_uop.bits.uses_stq, issue_slots[1].out_uop.uses_stq connect issue_slots[0].in_uop.bits.uses_ldq, issue_slots[1].out_uop.uses_ldq connect issue_slots[0].in_uop.bits.mem_signed, issue_slots[1].out_uop.mem_signed connect issue_slots[0].in_uop.bits.mem_size, issue_slots[1].out_uop.mem_size connect issue_slots[0].in_uop.bits.mem_cmd, issue_slots[1].out_uop.mem_cmd connect issue_slots[0].in_uop.bits.exc_cause, issue_slots[1].out_uop.exc_cause connect issue_slots[0].in_uop.bits.exception, issue_slots[1].out_uop.exception connect issue_slots[0].in_uop.bits.stale_pdst, issue_slots[1].out_uop.stale_pdst connect issue_slots[0].in_uop.bits.ppred_busy, issue_slots[1].out_uop.ppred_busy connect issue_slots[0].in_uop.bits.prs3_busy, issue_slots[1].out_uop.prs3_busy connect issue_slots[0].in_uop.bits.prs2_busy, issue_slots[1].out_uop.prs2_busy connect issue_slots[0].in_uop.bits.prs1_busy, issue_slots[1].out_uop.prs1_busy connect issue_slots[0].in_uop.bits.ppred, issue_slots[1].out_uop.ppred connect issue_slots[0].in_uop.bits.prs3, issue_slots[1].out_uop.prs3 connect issue_slots[0].in_uop.bits.prs2, issue_slots[1].out_uop.prs2 connect issue_slots[0].in_uop.bits.prs1, issue_slots[1].out_uop.prs1 connect issue_slots[0].in_uop.bits.pdst, issue_slots[1].out_uop.pdst connect issue_slots[0].in_uop.bits.rxq_idx, issue_slots[1].out_uop.rxq_idx connect issue_slots[0].in_uop.bits.stq_idx, issue_slots[1].out_uop.stq_idx connect issue_slots[0].in_uop.bits.ldq_idx, issue_slots[1].out_uop.ldq_idx connect issue_slots[0].in_uop.bits.rob_idx, issue_slots[1].out_uop.rob_idx connect issue_slots[0].in_uop.bits.fp_ctrl.vec, issue_slots[1].out_uop.fp_ctrl.vec connect issue_slots[0].in_uop.bits.fp_ctrl.wflags, issue_slots[1].out_uop.fp_ctrl.wflags connect issue_slots[0].in_uop.bits.fp_ctrl.sqrt, issue_slots[1].out_uop.fp_ctrl.sqrt connect issue_slots[0].in_uop.bits.fp_ctrl.div, issue_slots[1].out_uop.fp_ctrl.div connect issue_slots[0].in_uop.bits.fp_ctrl.fma, issue_slots[1].out_uop.fp_ctrl.fma connect issue_slots[0].in_uop.bits.fp_ctrl.fastpipe, issue_slots[1].out_uop.fp_ctrl.fastpipe connect issue_slots[0].in_uop.bits.fp_ctrl.toint, issue_slots[1].out_uop.fp_ctrl.toint connect issue_slots[0].in_uop.bits.fp_ctrl.fromint, issue_slots[1].out_uop.fp_ctrl.fromint connect issue_slots[0].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[1].out_uop.fp_ctrl.typeTagOut connect issue_slots[0].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[1].out_uop.fp_ctrl.typeTagIn connect issue_slots[0].in_uop.bits.fp_ctrl.swap23, issue_slots[1].out_uop.fp_ctrl.swap23 connect issue_slots[0].in_uop.bits.fp_ctrl.swap12, issue_slots[1].out_uop.fp_ctrl.swap12 connect issue_slots[0].in_uop.bits.fp_ctrl.ren3, issue_slots[1].out_uop.fp_ctrl.ren3 connect issue_slots[0].in_uop.bits.fp_ctrl.ren2, issue_slots[1].out_uop.fp_ctrl.ren2 connect issue_slots[0].in_uop.bits.fp_ctrl.ren1, issue_slots[1].out_uop.fp_ctrl.ren1 connect issue_slots[0].in_uop.bits.fp_ctrl.wen, issue_slots[1].out_uop.fp_ctrl.wen connect issue_slots[0].in_uop.bits.fp_ctrl.ldst, issue_slots[1].out_uop.fp_ctrl.ldst connect issue_slots[0].in_uop.bits.op2_sel, issue_slots[1].out_uop.op2_sel connect issue_slots[0].in_uop.bits.op1_sel, issue_slots[1].out_uop.op1_sel connect issue_slots[0].in_uop.bits.imm_packed, issue_slots[1].out_uop.imm_packed connect issue_slots[0].in_uop.bits.pimm, issue_slots[1].out_uop.pimm connect issue_slots[0].in_uop.bits.imm_sel, issue_slots[1].out_uop.imm_sel connect issue_slots[0].in_uop.bits.imm_rename, issue_slots[1].out_uop.imm_rename connect issue_slots[0].in_uop.bits.taken, issue_slots[1].out_uop.taken connect issue_slots[0].in_uop.bits.pc_lob, issue_slots[1].out_uop.pc_lob connect issue_slots[0].in_uop.bits.edge_inst, issue_slots[1].out_uop.edge_inst connect issue_slots[0].in_uop.bits.ftq_idx, issue_slots[1].out_uop.ftq_idx connect issue_slots[0].in_uop.bits.is_mov, issue_slots[1].out_uop.is_mov connect issue_slots[0].in_uop.bits.is_rocc, issue_slots[1].out_uop.is_rocc connect issue_slots[0].in_uop.bits.is_sys_pc2epc, issue_slots[1].out_uop.is_sys_pc2epc connect issue_slots[0].in_uop.bits.is_eret, issue_slots[1].out_uop.is_eret connect issue_slots[0].in_uop.bits.is_amo, issue_slots[1].out_uop.is_amo connect issue_slots[0].in_uop.bits.is_sfence, issue_slots[1].out_uop.is_sfence connect issue_slots[0].in_uop.bits.is_fencei, issue_slots[1].out_uop.is_fencei connect issue_slots[0].in_uop.bits.is_fence, issue_slots[1].out_uop.is_fence connect issue_slots[0].in_uop.bits.is_sfb, issue_slots[1].out_uop.is_sfb connect issue_slots[0].in_uop.bits.br_type, issue_slots[1].out_uop.br_type connect issue_slots[0].in_uop.bits.br_tag, issue_slots[1].out_uop.br_tag connect issue_slots[0].in_uop.bits.br_mask, issue_slots[1].out_uop.br_mask connect issue_slots[0].in_uop.bits.dis_col_sel, issue_slots[1].out_uop.dis_col_sel connect issue_slots[0].in_uop.bits.iw_p3_bypass_hint, issue_slots[1].out_uop.iw_p3_bypass_hint connect issue_slots[0].in_uop.bits.iw_p2_bypass_hint, issue_slots[1].out_uop.iw_p2_bypass_hint connect issue_slots[0].in_uop.bits.iw_p1_bypass_hint, issue_slots[1].out_uop.iw_p1_bypass_hint connect issue_slots[0].in_uop.bits.iw_p2_speculative_child, issue_slots[1].out_uop.iw_p2_speculative_child connect issue_slots[0].in_uop.bits.iw_p1_speculative_child, issue_slots[1].out_uop.iw_p1_speculative_child connect issue_slots[0].in_uop.bits.iw_issued_partial_dgen, issue_slots[1].out_uop.iw_issued_partial_dgen connect issue_slots[0].in_uop.bits.iw_issued_partial_agen, issue_slots[1].out_uop.iw_issued_partial_agen connect issue_slots[0].in_uop.bits.iw_issued, issue_slots[1].out_uop.iw_issued connect issue_slots[0].in_uop.bits.fu_code[0], issue_slots[1].out_uop.fu_code[0] connect issue_slots[0].in_uop.bits.fu_code[1], issue_slots[1].out_uop.fu_code[1] connect issue_slots[0].in_uop.bits.fu_code[2], issue_slots[1].out_uop.fu_code[2] connect issue_slots[0].in_uop.bits.fu_code[3], issue_slots[1].out_uop.fu_code[3] connect issue_slots[0].in_uop.bits.fu_code[4], issue_slots[1].out_uop.fu_code[4] connect issue_slots[0].in_uop.bits.fu_code[5], issue_slots[1].out_uop.fu_code[5] connect issue_slots[0].in_uop.bits.fu_code[6], issue_slots[1].out_uop.fu_code[6] connect issue_slots[0].in_uop.bits.fu_code[7], issue_slots[1].out_uop.fu_code[7] connect issue_slots[0].in_uop.bits.fu_code[8], issue_slots[1].out_uop.fu_code[8] connect issue_slots[0].in_uop.bits.fu_code[9], issue_slots[1].out_uop.fu_code[9] connect issue_slots[0].in_uop.bits.iq_type[0], issue_slots[1].out_uop.iq_type[0] connect issue_slots[0].in_uop.bits.iq_type[1], issue_slots[1].out_uop.iq_type[1] connect issue_slots[0].in_uop.bits.iq_type[2], issue_slots[1].out_uop.iq_type[2] connect issue_slots[0].in_uop.bits.iq_type[3], issue_slots[1].out_uop.iq_type[3] connect issue_slots[0].in_uop.bits.debug_pc, issue_slots[1].out_uop.debug_pc connect issue_slots[0].in_uop.bits.is_rvc, issue_slots[1].out_uop.is_rvc connect issue_slots[0].in_uop.bits.debug_inst, issue_slots[1].out_uop.debug_inst connect issue_slots[0].in_uop.bits.inst, issue_slots[1].out_uop.inst node _T_277 = eq(shamts_oh[1], UInt<1>(0h1)) when _T_277 : connect issue_slots[0].in_uop.valid, issue_slots[1].will_be_valid connect issue_slots[0].in_uop.bits.debug_tsrc, issue_slots[1].out_uop.debug_tsrc connect issue_slots[0].in_uop.bits.debug_fsrc, issue_slots[1].out_uop.debug_fsrc connect issue_slots[0].in_uop.bits.bp_xcpt_if, issue_slots[1].out_uop.bp_xcpt_if connect issue_slots[0].in_uop.bits.bp_debug_if, issue_slots[1].out_uop.bp_debug_if connect issue_slots[0].in_uop.bits.xcpt_ma_if, issue_slots[1].out_uop.xcpt_ma_if connect issue_slots[0].in_uop.bits.xcpt_ae_if, issue_slots[1].out_uop.xcpt_ae_if connect issue_slots[0].in_uop.bits.xcpt_pf_if, issue_slots[1].out_uop.xcpt_pf_if connect issue_slots[0].in_uop.bits.fp_typ, issue_slots[1].out_uop.fp_typ connect issue_slots[0].in_uop.bits.fp_rm, issue_slots[1].out_uop.fp_rm connect issue_slots[0].in_uop.bits.fp_val, issue_slots[1].out_uop.fp_val connect issue_slots[0].in_uop.bits.fcn_op, issue_slots[1].out_uop.fcn_op connect issue_slots[0].in_uop.bits.fcn_dw, issue_slots[1].out_uop.fcn_dw connect issue_slots[0].in_uop.bits.frs3_en, issue_slots[1].out_uop.frs3_en connect issue_slots[0].in_uop.bits.lrs2_rtype, issue_slots[1].out_uop.lrs2_rtype connect issue_slots[0].in_uop.bits.lrs1_rtype, issue_slots[1].out_uop.lrs1_rtype connect issue_slots[0].in_uop.bits.dst_rtype, issue_slots[1].out_uop.dst_rtype connect issue_slots[0].in_uop.bits.lrs3, issue_slots[1].out_uop.lrs3 connect issue_slots[0].in_uop.bits.lrs2, issue_slots[1].out_uop.lrs2 connect issue_slots[0].in_uop.bits.lrs1, issue_slots[1].out_uop.lrs1 connect issue_slots[0].in_uop.bits.ldst, issue_slots[1].out_uop.ldst connect issue_slots[0].in_uop.bits.ldst_is_rs1, issue_slots[1].out_uop.ldst_is_rs1 connect issue_slots[0].in_uop.bits.csr_cmd, issue_slots[1].out_uop.csr_cmd connect issue_slots[0].in_uop.bits.flush_on_commit, issue_slots[1].out_uop.flush_on_commit connect issue_slots[0].in_uop.bits.is_unique, issue_slots[1].out_uop.is_unique connect issue_slots[0].in_uop.bits.uses_stq, issue_slots[1].out_uop.uses_stq connect issue_slots[0].in_uop.bits.uses_ldq, issue_slots[1].out_uop.uses_ldq connect issue_slots[0].in_uop.bits.mem_signed, issue_slots[1].out_uop.mem_signed connect issue_slots[0].in_uop.bits.mem_size, issue_slots[1].out_uop.mem_size connect issue_slots[0].in_uop.bits.mem_cmd, issue_slots[1].out_uop.mem_cmd connect issue_slots[0].in_uop.bits.exc_cause, issue_slots[1].out_uop.exc_cause connect issue_slots[0].in_uop.bits.exception, issue_slots[1].out_uop.exception connect issue_slots[0].in_uop.bits.stale_pdst, issue_slots[1].out_uop.stale_pdst connect issue_slots[0].in_uop.bits.ppred_busy, issue_slots[1].out_uop.ppred_busy connect issue_slots[0].in_uop.bits.prs3_busy, issue_slots[1].out_uop.prs3_busy connect issue_slots[0].in_uop.bits.prs2_busy, issue_slots[1].out_uop.prs2_busy connect issue_slots[0].in_uop.bits.prs1_busy, issue_slots[1].out_uop.prs1_busy connect issue_slots[0].in_uop.bits.ppred, issue_slots[1].out_uop.ppred connect issue_slots[0].in_uop.bits.prs3, issue_slots[1].out_uop.prs3 connect issue_slots[0].in_uop.bits.prs2, issue_slots[1].out_uop.prs2 connect issue_slots[0].in_uop.bits.prs1, issue_slots[1].out_uop.prs1 connect issue_slots[0].in_uop.bits.pdst, issue_slots[1].out_uop.pdst connect issue_slots[0].in_uop.bits.rxq_idx, issue_slots[1].out_uop.rxq_idx connect issue_slots[0].in_uop.bits.stq_idx, issue_slots[1].out_uop.stq_idx connect issue_slots[0].in_uop.bits.ldq_idx, issue_slots[1].out_uop.ldq_idx connect issue_slots[0].in_uop.bits.rob_idx, issue_slots[1].out_uop.rob_idx connect issue_slots[0].in_uop.bits.fp_ctrl.vec, issue_slots[1].out_uop.fp_ctrl.vec connect issue_slots[0].in_uop.bits.fp_ctrl.wflags, issue_slots[1].out_uop.fp_ctrl.wflags connect issue_slots[0].in_uop.bits.fp_ctrl.sqrt, issue_slots[1].out_uop.fp_ctrl.sqrt connect issue_slots[0].in_uop.bits.fp_ctrl.div, issue_slots[1].out_uop.fp_ctrl.div connect issue_slots[0].in_uop.bits.fp_ctrl.fma, issue_slots[1].out_uop.fp_ctrl.fma connect issue_slots[0].in_uop.bits.fp_ctrl.fastpipe, issue_slots[1].out_uop.fp_ctrl.fastpipe connect issue_slots[0].in_uop.bits.fp_ctrl.toint, issue_slots[1].out_uop.fp_ctrl.toint connect issue_slots[0].in_uop.bits.fp_ctrl.fromint, issue_slots[1].out_uop.fp_ctrl.fromint connect issue_slots[0].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[1].out_uop.fp_ctrl.typeTagOut connect issue_slots[0].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[1].out_uop.fp_ctrl.typeTagIn connect issue_slots[0].in_uop.bits.fp_ctrl.swap23, issue_slots[1].out_uop.fp_ctrl.swap23 connect issue_slots[0].in_uop.bits.fp_ctrl.swap12, issue_slots[1].out_uop.fp_ctrl.swap12 connect issue_slots[0].in_uop.bits.fp_ctrl.ren3, issue_slots[1].out_uop.fp_ctrl.ren3 connect issue_slots[0].in_uop.bits.fp_ctrl.ren2, issue_slots[1].out_uop.fp_ctrl.ren2 connect issue_slots[0].in_uop.bits.fp_ctrl.ren1, issue_slots[1].out_uop.fp_ctrl.ren1 connect issue_slots[0].in_uop.bits.fp_ctrl.wen, issue_slots[1].out_uop.fp_ctrl.wen connect issue_slots[0].in_uop.bits.fp_ctrl.ldst, issue_slots[1].out_uop.fp_ctrl.ldst connect issue_slots[0].in_uop.bits.op2_sel, issue_slots[1].out_uop.op2_sel connect issue_slots[0].in_uop.bits.op1_sel, issue_slots[1].out_uop.op1_sel connect issue_slots[0].in_uop.bits.imm_packed, issue_slots[1].out_uop.imm_packed connect issue_slots[0].in_uop.bits.pimm, issue_slots[1].out_uop.pimm connect issue_slots[0].in_uop.bits.imm_sel, issue_slots[1].out_uop.imm_sel connect issue_slots[0].in_uop.bits.imm_rename, issue_slots[1].out_uop.imm_rename connect issue_slots[0].in_uop.bits.taken, issue_slots[1].out_uop.taken connect issue_slots[0].in_uop.bits.pc_lob, issue_slots[1].out_uop.pc_lob connect issue_slots[0].in_uop.bits.edge_inst, issue_slots[1].out_uop.edge_inst connect issue_slots[0].in_uop.bits.ftq_idx, issue_slots[1].out_uop.ftq_idx connect issue_slots[0].in_uop.bits.is_mov, issue_slots[1].out_uop.is_mov connect issue_slots[0].in_uop.bits.is_rocc, issue_slots[1].out_uop.is_rocc connect issue_slots[0].in_uop.bits.is_sys_pc2epc, issue_slots[1].out_uop.is_sys_pc2epc connect issue_slots[0].in_uop.bits.is_eret, issue_slots[1].out_uop.is_eret connect issue_slots[0].in_uop.bits.is_amo, issue_slots[1].out_uop.is_amo connect issue_slots[0].in_uop.bits.is_sfence, issue_slots[1].out_uop.is_sfence connect issue_slots[0].in_uop.bits.is_fencei, issue_slots[1].out_uop.is_fencei connect issue_slots[0].in_uop.bits.is_fence, issue_slots[1].out_uop.is_fence connect issue_slots[0].in_uop.bits.is_sfb, issue_slots[1].out_uop.is_sfb connect issue_slots[0].in_uop.bits.br_type, issue_slots[1].out_uop.br_type connect issue_slots[0].in_uop.bits.br_tag, issue_slots[1].out_uop.br_tag connect issue_slots[0].in_uop.bits.br_mask, issue_slots[1].out_uop.br_mask connect issue_slots[0].in_uop.bits.dis_col_sel, issue_slots[1].out_uop.dis_col_sel connect issue_slots[0].in_uop.bits.iw_p3_bypass_hint, issue_slots[1].out_uop.iw_p3_bypass_hint connect issue_slots[0].in_uop.bits.iw_p2_bypass_hint, issue_slots[1].out_uop.iw_p2_bypass_hint connect issue_slots[0].in_uop.bits.iw_p1_bypass_hint, issue_slots[1].out_uop.iw_p1_bypass_hint connect issue_slots[0].in_uop.bits.iw_p2_speculative_child, issue_slots[1].out_uop.iw_p2_speculative_child connect issue_slots[0].in_uop.bits.iw_p1_speculative_child, issue_slots[1].out_uop.iw_p1_speculative_child connect issue_slots[0].in_uop.bits.iw_issued_partial_dgen, issue_slots[1].out_uop.iw_issued_partial_dgen connect issue_slots[0].in_uop.bits.iw_issued_partial_agen, issue_slots[1].out_uop.iw_issued_partial_agen connect issue_slots[0].in_uop.bits.iw_issued, issue_slots[1].out_uop.iw_issued connect issue_slots[0].in_uop.bits.fu_code[0], issue_slots[1].out_uop.fu_code[0] connect issue_slots[0].in_uop.bits.fu_code[1], issue_slots[1].out_uop.fu_code[1] connect issue_slots[0].in_uop.bits.fu_code[2], issue_slots[1].out_uop.fu_code[2] connect issue_slots[0].in_uop.bits.fu_code[3], issue_slots[1].out_uop.fu_code[3] connect issue_slots[0].in_uop.bits.fu_code[4], issue_slots[1].out_uop.fu_code[4] connect issue_slots[0].in_uop.bits.fu_code[5], issue_slots[1].out_uop.fu_code[5] connect issue_slots[0].in_uop.bits.fu_code[6], issue_slots[1].out_uop.fu_code[6] connect issue_slots[0].in_uop.bits.fu_code[7], issue_slots[1].out_uop.fu_code[7] connect issue_slots[0].in_uop.bits.fu_code[8], issue_slots[1].out_uop.fu_code[8] connect issue_slots[0].in_uop.bits.fu_code[9], issue_slots[1].out_uop.fu_code[9] connect issue_slots[0].in_uop.bits.iq_type[0], issue_slots[1].out_uop.iq_type[0] connect issue_slots[0].in_uop.bits.iq_type[1], issue_slots[1].out_uop.iq_type[1] connect issue_slots[0].in_uop.bits.iq_type[2], issue_slots[1].out_uop.iq_type[2] connect issue_slots[0].in_uop.bits.iq_type[3], issue_slots[1].out_uop.iq_type[3] connect issue_slots[0].in_uop.bits.debug_pc, issue_slots[1].out_uop.debug_pc connect issue_slots[0].in_uop.bits.is_rvc, issue_slots[1].out_uop.is_rvc connect issue_slots[0].in_uop.bits.debug_inst, issue_slots[1].out_uop.debug_inst connect issue_slots[0].in_uop.bits.inst, issue_slots[1].out_uop.inst node _T_278 = eq(shamts_oh[2], UInt<2>(0h2)) when _T_278 : connect issue_slots[0].in_uop.valid, issue_slots[2].will_be_valid connect issue_slots[0].in_uop.bits.debug_tsrc, issue_slots[2].out_uop.debug_tsrc connect issue_slots[0].in_uop.bits.debug_fsrc, issue_slots[2].out_uop.debug_fsrc connect issue_slots[0].in_uop.bits.bp_xcpt_if, issue_slots[2].out_uop.bp_xcpt_if connect issue_slots[0].in_uop.bits.bp_debug_if, issue_slots[2].out_uop.bp_debug_if connect issue_slots[0].in_uop.bits.xcpt_ma_if, issue_slots[2].out_uop.xcpt_ma_if connect issue_slots[0].in_uop.bits.xcpt_ae_if, issue_slots[2].out_uop.xcpt_ae_if connect issue_slots[0].in_uop.bits.xcpt_pf_if, issue_slots[2].out_uop.xcpt_pf_if connect issue_slots[0].in_uop.bits.fp_typ, issue_slots[2].out_uop.fp_typ connect issue_slots[0].in_uop.bits.fp_rm, issue_slots[2].out_uop.fp_rm connect issue_slots[0].in_uop.bits.fp_val, issue_slots[2].out_uop.fp_val connect issue_slots[0].in_uop.bits.fcn_op, issue_slots[2].out_uop.fcn_op connect issue_slots[0].in_uop.bits.fcn_dw, issue_slots[2].out_uop.fcn_dw connect issue_slots[0].in_uop.bits.frs3_en, issue_slots[2].out_uop.frs3_en connect issue_slots[0].in_uop.bits.lrs2_rtype, issue_slots[2].out_uop.lrs2_rtype connect issue_slots[0].in_uop.bits.lrs1_rtype, issue_slots[2].out_uop.lrs1_rtype connect issue_slots[0].in_uop.bits.dst_rtype, issue_slots[2].out_uop.dst_rtype connect issue_slots[0].in_uop.bits.lrs3, issue_slots[2].out_uop.lrs3 connect issue_slots[0].in_uop.bits.lrs2, issue_slots[2].out_uop.lrs2 connect issue_slots[0].in_uop.bits.lrs1, issue_slots[2].out_uop.lrs1 connect issue_slots[0].in_uop.bits.ldst, issue_slots[2].out_uop.ldst connect issue_slots[0].in_uop.bits.ldst_is_rs1, issue_slots[2].out_uop.ldst_is_rs1 connect issue_slots[0].in_uop.bits.csr_cmd, issue_slots[2].out_uop.csr_cmd connect issue_slots[0].in_uop.bits.flush_on_commit, issue_slots[2].out_uop.flush_on_commit connect issue_slots[0].in_uop.bits.is_unique, issue_slots[2].out_uop.is_unique connect issue_slots[0].in_uop.bits.uses_stq, issue_slots[2].out_uop.uses_stq connect issue_slots[0].in_uop.bits.uses_ldq, issue_slots[2].out_uop.uses_ldq connect issue_slots[0].in_uop.bits.mem_signed, issue_slots[2].out_uop.mem_signed connect issue_slots[0].in_uop.bits.mem_size, issue_slots[2].out_uop.mem_size connect issue_slots[0].in_uop.bits.mem_cmd, issue_slots[2].out_uop.mem_cmd connect issue_slots[0].in_uop.bits.exc_cause, issue_slots[2].out_uop.exc_cause connect issue_slots[0].in_uop.bits.exception, issue_slots[2].out_uop.exception connect issue_slots[0].in_uop.bits.stale_pdst, issue_slots[2].out_uop.stale_pdst connect issue_slots[0].in_uop.bits.ppred_busy, issue_slots[2].out_uop.ppred_busy connect issue_slots[0].in_uop.bits.prs3_busy, issue_slots[2].out_uop.prs3_busy connect issue_slots[0].in_uop.bits.prs2_busy, issue_slots[2].out_uop.prs2_busy connect issue_slots[0].in_uop.bits.prs1_busy, issue_slots[2].out_uop.prs1_busy connect issue_slots[0].in_uop.bits.ppred, issue_slots[2].out_uop.ppred connect issue_slots[0].in_uop.bits.prs3, issue_slots[2].out_uop.prs3 connect issue_slots[0].in_uop.bits.prs2, issue_slots[2].out_uop.prs2 connect issue_slots[0].in_uop.bits.prs1, issue_slots[2].out_uop.prs1 connect issue_slots[0].in_uop.bits.pdst, issue_slots[2].out_uop.pdst connect issue_slots[0].in_uop.bits.rxq_idx, issue_slots[2].out_uop.rxq_idx connect issue_slots[0].in_uop.bits.stq_idx, issue_slots[2].out_uop.stq_idx connect issue_slots[0].in_uop.bits.ldq_idx, issue_slots[2].out_uop.ldq_idx connect issue_slots[0].in_uop.bits.rob_idx, issue_slots[2].out_uop.rob_idx connect issue_slots[0].in_uop.bits.fp_ctrl.vec, issue_slots[2].out_uop.fp_ctrl.vec connect issue_slots[0].in_uop.bits.fp_ctrl.wflags, issue_slots[2].out_uop.fp_ctrl.wflags connect issue_slots[0].in_uop.bits.fp_ctrl.sqrt, issue_slots[2].out_uop.fp_ctrl.sqrt connect issue_slots[0].in_uop.bits.fp_ctrl.div, issue_slots[2].out_uop.fp_ctrl.div connect issue_slots[0].in_uop.bits.fp_ctrl.fma, issue_slots[2].out_uop.fp_ctrl.fma connect issue_slots[0].in_uop.bits.fp_ctrl.fastpipe, issue_slots[2].out_uop.fp_ctrl.fastpipe connect issue_slots[0].in_uop.bits.fp_ctrl.toint, issue_slots[2].out_uop.fp_ctrl.toint connect issue_slots[0].in_uop.bits.fp_ctrl.fromint, issue_slots[2].out_uop.fp_ctrl.fromint connect issue_slots[0].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[2].out_uop.fp_ctrl.typeTagOut connect issue_slots[0].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[2].out_uop.fp_ctrl.typeTagIn connect issue_slots[0].in_uop.bits.fp_ctrl.swap23, issue_slots[2].out_uop.fp_ctrl.swap23 connect issue_slots[0].in_uop.bits.fp_ctrl.swap12, issue_slots[2].out_uop.fp_ctrl.swap12 connect issue_slots[0].in_uop.bits.fp_ctrl.ren3, issue_slots[2].out_uop.fp_ctrl.ren3 connect issue_slots[0].in_uop.bits.fp_ctrl.ren2, issue_slots[2].out_uop.fp_ctrl.ren2 connect issue_slots[0].in_uop.bits.fp_ctrl.ren1, issue_slots[2].out_uop.fp_ctrl.ren1 connect issue_slots[0].in_uop.bits.fp_ctrl.wen, issue_slots[2].out_uop.fp_ctrl.wen connect issue_slots[0].in_uop.bits.fp_ctrl.ldst, issue_slots[2].out_uop.fp_ctrl.ldst connect issue_slots[0].in_uop.bits.op2_sel, issue_slots[2].out_uop.op2_sel connect issue_slots[0].in_uop.bits.op1_sel, issue_slots[2].out_uop.op1_sel connect issue_slots[0].in_uop.bits.imm_packed, issue_slots[2].out_uop.imm_packed connect issue_slots[0].in_uop.bits.pimm, issue_slots[2].out_uop.pimm connect issue_slots[0].in_uop.bits.imm_sel, issue_slots[2].out_uop.imm_sel connect issue_slots[0].in_uop.bits.imm_rename, issue_slots[2].out_uop.imm_rename connect issue_slots[0].in_uop.bits.taken, issue_slots[2].out_uop.taken connect issue_slots[0].in_uop.bits.pc_lob, issue_slots[2].out_uop.pc_lob connect issue_slots[0].in_uop.bits.edge_inst, issue_slots[2].out_uop.edge_inst connect issue_slots[0].in_uop.bits.ftq_idx, issue_slots[2].out_uop.ftq_idx connect issue_slots[0].in_uop.bits.is_mov, issue_slots[2].out_uop.is_mov connect issue_slots[0].in_uop.bits.is_rocc, issue_slots[2].out_uop.is_rocc connect issue_slots[0].in_uop.bits.is_sys_pc2epc, issue_slots[2].out_uop.is_sys_pc2epc connect issue_slots[0].in_uop.bits.is_eret, issue_slots[2].out_uop.is_eret connect issue_slots[0].in_uop.bits.is_amo, issue_slots[2].out_uop.is_amo connect issue_slots[0].in_uop.bits.is_sfence, issue_slots[2].out_uop.is_sfence connect issue_slots[0].in_uop.bits.is_fencei, issue_slots[2].out_uop.is_fencei connect issue_slots[0].in_uop.bits.is_fence, issue_slots[2].out_uop.is_fence connect issue_slots[0].in_uop.bits.is_sfb, issue_slots[2].out_uop.is_sfb connect issue_slots[0].in_uop.bits.br_type, issue_slots[2].out_uop.br_type connect issue_slots[0].in_uop.bits.br_tag, issue_slots[2].out_uop.br_tag connect issue_slots[0].in_uop.bits.br_mask, issue_slots[2].out_uop.br_mask connect issue_slots[0].in_uop.bits.dis_col_sel, issue_slots[2].out_uop.dis_col_sel connect issue_slots[0].in_uop.bits.iw_p3_bypass_hint, issue_slots[2].out_uop.iw_p3_bypass_hint connect issue_slots[0].in_uop.bits.iw_p2_bypass_hint, issue_slots[2].out_uop.iw_p2_bypass_hint connect issue_slots[0].in_uop.bits.iw_p1_bypass_hint, issue_slots[2].out_uop.iw_p1_bypass_hint connect issue_slots[0].in_uop.bits.iw_p2_speculative_child, issue_slots[2].out_uop.iw_p2_speculative_child connect issue_slots[0].in_uop.bits.iw_p1_speculative_child, issue_slots[2].out_uop.iw_p1_speculative_child connect issue_slots[0].in_uop.bits.iw_issued_partial_dgen, issue_slots[2].out_uop.iw_issued_partial_dgen connect issue_slots[0].in_uop.bits.iw_issued_partial_agen, issue_slots[2].out_uop.iw_issued_partial_agen connect issue_slots[0].in_uop.bits.iw_issued, issue_slots[2].out_uop.iw_issued connect issue_slots[0].in_uop.bits.fu_code[0], issue_slots[2].out_uop.fu_code[0] connect issue_slots[0].in_uop.bits.fu_code[1], issue_slots[2].out_uop.fu_code[1] connect issue_slots[0].in_uop.bits.fu_code[2], issue_slots[2].out_uop.fu_code[2] connect issue_slots[0].in_uop.bits.fu_code[3], issue_slots[2].out_uop.fu_code[3] connect issue_slots[0].in_uop.bits.fu_code[4], issue_slots[2].out_uop.fu_code[4] connect issue_slots[0].in_uop.bits.fu_code[5], issue_slots[2].out_uop.fu_code[5] connect issue_slots[0].in_uop.bits.fu_code[6], issue_slots[2].out_uop.fu_code[6] connect issue_slots[0].in_uop.bits.fu_code[7], issue_slots[2].out_uop.fu_code[7] connect issue_slots[0].in_uop.bits.fu_code[8], issue_slots[2].out_uop.fu_code[8] connect issue_slots[0].in_uop.bits.fu_code[9], issue_slots[2].out_uop.fu_code[9] connect issue_slots[0].in_uop.bits.iq_type[0], issue_slots[2].out_uop.iq_type[0] connect issue_slots[0].in_uop.bits.iq_type[1], issue_slots[2].out_uop.iq_type[1] connect issue_slots[0].in_uop.bits.iq_type[2], issue_slots[2].out_uop.iq_type[2] connect issue_slots[0].in_uop.bits.iq_type[3], issue_slots[2].out_uop.iq_type[3] connect issue_slots[0].in_uop.bits.debug_pc, issue_slots[2].out_uop.debug_pc connect issue_slots[0].in_uop.bits.is_rvc, issue_slots[2].out_uop.is_rvc connect issue_slots[0].in_uop.bits.debug_inst, issue_slots[2].out_uop.debug_inst connect issue_slots[0].in_uop.bits.inst, issue_slots[2].out_uop.inst node _T_279 = eq(shamts_oh[3], UInt<3>(0h4)) when _T_279 : connect issue_slots[0].in_uop.valid, issue_slots[3].will_be_valid connect issue_slots[0].in_uop.bits.debug_tsrc, issue_slots[3].out_uop.debug_tsrc connect issue_slots[0].in_uop.bits.debug_fsrc, issue_slots[3].out_uop.debug_fsrc connect issue_slots[0].in_uop.bits.bp_xcpt_if, issue_slots[3].out_uop.bp_xcpt_if connect issue_slots[0].in_uop.bits.bp_debug_if, issue_slots[3].out_uop.bp_debug_if connect issue_slots[0].in_uop.bits.xcpt_ma_if, issue_slots[3].out_uop.xcpt_ma_if connect issue_slots[0].in_uop.bits.xcpt_ae_if, issue_slots[3].out_uop.xcpt_ae_if connect issue_slots[0].in_uop.bits.xcpt_pf_if, issue_slots[3].out_uop.xcpt_pf_if connect issue_slots[0].in_uop.bits.fp_typ, issue_slots[3].out_uop.fp_typ connect issue_slots[0].in_uop.bits.fp_rm, issue_slots[3].out_uop.fp_rm connect issue_slots[0].in_uop.bits.fp_val, issue_slots[3].out_uop.fp_val connect issue_slots[0].in_uop.bits.fcn_op, issue_slots[3].out_uop.fcn_op connect issue_slots[0].in_uop.bits.fcn_dw, issue_slots[3].out_uop.fcn_dw connect issue_slots[0].in_uop.bits.frs3_en, issue_slots[3].out_uop.frs3_en connect issue_slots[0].in_uop.bits.lrs2_rtype, issue_slots[3].out_uop.lrs2_rtype connect issue_slots[0].in_uop.bits.lrs1_rtype, issue_slots[3].out_uop.lrs1_rtype connect issue_slots[0].in_uop.bits.dst_rtype, issue_slots[3].out_uop.dst_rtype connect issue_slots[0].in_uop.bits.lrs3, issue_slots[3].out_uop.lrs3 connect issue_slots[0].in_uop.bits.lrs2, issue_slots[3].out_uop.lrs2 connect issue_slots[0].in_uop.bits.lrs1, issue_slots[3].out_uop.lrs1 connect issue_slots[0].in_uop.bits.ldst, issue_slots[3].out_uop.ldst connect issue_slots[0].in_uop.bits.ldst_is_rs1, issue_slots[3].out_uop.ldst_is_rs1 connect issue_slots[0].in_uop.bits.csr_cmd, issue_slots[3].out_uop.csr_cmd connect issue_slots[0].in_uop.bits.flush_on_commit, issue_slots[3].out_uop.flush_on_commit connect issue_slots[0].in_uop.bits.is_unique, issue_slots[3].out_uop.is_unique connect issue_slots[0].in_uop.bits.uses_stq, issue_slots[3].out_uop.uses_stq connect issue_slots[0].in_uop.bits.uses_ldq, issue_slots[3].out_uop.uses_ldq connect issue_slots[0].in_uop.bits.mem_signed, issue_slots[3].out_uop.mem_signed connect issue_slots[0].in_uop.bits.mem_size, issue_slots[3].out_uop.mem_size connect issue_slots[0].in_uop.bits.mem_cmd, issue_slots[3].out_uop.mem_cmd connect issue_slots[0].in_uop.bits.exc_cause, issue_slots[3].out_uop.exc_cause connect issue_slots[0].in_uop.bits.exception, issue_slots[3].out_uop.exception connect issue_slots[0].in_uop.bits.stale_pdst, issue_slots[3].out_uop.stale_pdst connect issue_slots[0].in_uop.bits.ppred_busy, issue_slots[3].out_uop.ppred_busy connect issue_slots[0].in_uop.bits.prs3_busy, issue_slots[3].out_uop.prs3_busy connect issue_slots[0].in_uop.bits.prs2_busy, issue_slots[3].out_uop.prs2_busy connect issue_slots[0].in_uop.bits.prs1_busy, issue_slots[3].out_uop.prs1_busy connect issue_slots[0].in_uop.bits.ppred, issue_slots[3].out_uop.ppred connect issue_slots[0].in_uop.bits.prs3, issue_slots[3].out_uop.prs3 connect issue_slots[0].in_uop.bits.prs2, issue_slots[3].out_uop.prs2 connect issue_slots[0].in_uop.bits.prs1, issue_slots[3].out_uop.prs1 connect issue_slots[0].in_uop.bits.pdst, issue_slots[3].out_uop.pdst connect issue_slots[0].in_uop.bits.rxq_idx, issue_slots[3].out_uop.rxq_idx connect issue_slots[0].in_uop.bits.stq_idx, issue_slots[3].out_uop.stq_idx connect issue_slots[0].in_uop.bits.ldq_idx, issue_slots[3].out_uop.ldq_idx connect issue_slots[0].in_uop.bits.rob_idx, issue_slots[3].out_uop.rob_idx connect issue_slots[0].in_uop.bits.fp_ctrl.vec, issue_slots[3].out_uop.fp_ctrl.vec connect issue_slots[0].in_uop.bits.fp_ctrl.wflags, issue_slots[3].out_uop.fp_ctrl.wflags connect issue_slots[0].in_uop.bits.fp_ctrl.sqrt, issue_slots[3].out_uop.fp_ctrl.sqrt connect issue_slots[0].in_uop.bits.fp_ctrl.div, issue_slots[3].out_uop.fp_ctrl.div connect issue_slots[0].in_uop.bits.fp_ctrl.fma, issue_slots[3].out_uop.fp_ctrl.fma connect issue_slots[0].in_uop.bits.fp_ctrl.fastpipe, issue_slots[3].out_uop.fp_ctrl.fastpipe connect issue_slots[0].in_uop.bits.fp_ctrl.toint, issue_slots[3].out_uop.fp_ctrl.toint connect issue_slots[0].in_uop.bits.fp_ctrl.fromint, issue_slots[3].out_uop.fp_ctrl.fromint connect issue_slots[0].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[3].out_uop.fp_ctrl.typeTagOut connect issue_slots[0].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[3].out_uop.fp_ctrl.typeTagIn connect issue_slots[0].in_uop.bits.fp_ctrl.swap23, issue_slots[3].out_uop.fp_ctrl.swap23 connect issue_slots[0].in_uop.bits.fp_ctrl.swap12, issue_slots[3].out_uop.fp_ctrl.swap12 connect issue_slots[0].in_uop.bits.fp_ctrl.ren3, issue_slots[3].out_uop.fp_ctrl.ren3 connect issue_slots[0].in_uop.bits.fp_ctrl.ren2, issue_slots[3].out_uop.fp_ctrl.ren2 connect issue_slots[0].in_uop.bits.fp_ctrl.ren1, issue_slots[3].out_uop.fp_ctrl.ren1 connect issue_slots[0].in_uop.bits.fp_ctrl.wen, issue_slots[3].out_uop.fp_ctrl.wen connect issue_slots[0].in_uop.bits.fp_ctrl.ldst, issue_slots[3].out_uop.fp_ctrl.ldst connect issue_slots[0].in_uop.bits.op2_sel, issue_slots[3].out_uop.op2_sel connect issue_slots[0].in_uop.bits.op1_sel, issue_slots[3].out_uop.op1_sel connect issue_slots[0].in_uop.bits.imm_packed, issue_slots[3].out_uop.imm_packed connect issue_slots[0].in_uop.bits.pimm, issue_slots[3].out_uop.pimm connect issue_slots[0].in_uop.bits.imm_sel, issue_slots[3].out_uop.imm_sel connect issue_slots[0].in_uop.bits.imm_rename, issue_slots[3].out_uop.imm_rename connect issue_slots[0].in_uop.bits.taken, issue_slots[3].out_uop.taken connect issue_slots[0].in_uop.bits.pc_lob, issue_slots[3].out_uop.pc_lob connect issue_slots[0].in_uop.bits.edge_inst, issue_slots[3].out_uop.edge_inst connect issue_slots[0].in_uop.bits.ftq_idx, issue_slots[3].out_uop.ftq_idx connect issue_slots[0].in_uop.bits.is_mov, issue_slots[3].out_uop.is_mov connect issue_slots[0].in_uop.bits.is_rocc, issue_slots[3].out_uop.is_rocc connect issue_slots[0].in_uop.bits.is_sys_pc2epc, issue_slots[3].out_uop.is_sys_pc2epc connect issue_slots[0].in_uop.bits.is_eret, issue_slots[3].out_uop.is_eret connect issue_slots[0].in_uop.bits.is_amo, issue_slots[3].out_uop.is_amo connect issue_slots[0].in_uop.bits.is_sfence, issue_slots[3].out_uop.is_sfence connect issue_slots[0].in_uop.bits.is_fencei, issue_slots[3].out_uop.is_fencei connect issue_slots[0].in_uop.bits.is_fence, issue_slots[3].out_uop.is_fence connect issue_slots[0].in_uop.bits.is_sfb, issue_slots[3].out_uop.is_sfb connect issue_slots[0].in_uop.bits.br_type, issue_slots[3].out_uop.br_type connect issue_slots[0].in_uop.bits.br_tag, issue_slots[3].out_uop.br_tag connect issue_slots[0].in_uop.bits.br_mask, issue_slots[3].out_uop.br_mask connect issue_slots[0].in_uop.bits.dis_col_sel, issue_slots[3].out_uop.dis_col_sel connect issue_slots[0].in_uop.bits.iw_p3_bypass_hint, issue_slots[3].out_uop.iw_p3_bypass_hint connect issue_slots[0].in_uop.bits.iw_p2_bypass_hint, issue_slots[3].out_uop.iw_p2_bypass_hint connect issue_slots[0].in_uop.bits.iw_p1_bypass_hint, issue_slots[3].out_uop.iw_p1_bypass_hint connect issue_slots[0].in_uop.bits.iw_p2_speculative_child, issue_slots[3].out_uop.iw_p2_speculative_child connect issue_slots[0].in_uop.bits.iw_p1_speculative_child, issue_slots[3].out_uop.iw_p1_speculative_child connect issue_slots[0].in_uop.bits.iw_issued_partial_dgen, issue_slots[3].out_uop.iw_issued_partial_dgen connect issue_slots[0].in_uop.bits.iw_issued_partial_agen, issue_slots[3].out_uop.iw_issued_partial_agen connect issue_slots[0].in_uop.bits.iw_issued, issue_slots[3].out_uop.iw_issued connect issue_slots[0].in_uop.bits.fu_code[0], issue_slots[3].out_uop.fu_code[0] connect issue_slots[0].in_uop.bits.fu_code[1], issue_slots[3].out_uop.fu_code[1] connect issue_slots[0].in_uop.bits.fu_code[2], issue_slots[3].out_uop.fu_code[2] connect issue_slots[0].in_uop.bits.fu_code[3], issue_slots[3].out_uop.fu_code[3] connect issue_slots[0].in_uop.bits.fu_code[4], issue_slots[3].out_uop.fu_code[4] connect issue_slots[0].in_uop.bits.fu_code[5], issue_slots[3].out_uop.fu_code[5] connect issue_slots[0].in_uop.bits.fu_code[6], issue_slots[3].out_uop.fu_code[6] connect issue_slots[0].in_uop.bits.fu_code[7], issue_slots[3].out_uop.fu_code[7] connect issue_slots[0].in_uop.bits.fu_code[8], issue_slots[3].out_uop.fu_code[8] connect issue_slots[0].in_uop.bits.fu_code[9], issue_slots[3].out_uop.fu_code[9] connect issue_slots[0].in_uop.bits.iq_type[0], issue_slots[3].out_uop.iq_type[0] connect issue_slots[0].in_uop.bits.iq_type[1], issue_slots[3].out_uop.iq_type[1] connect issue_slots[0].in_uop.bits.iq_type[2], issue_slots[3].out_uop.iq_type[2] connect issue_slots[0].in_uop.bits.iq_type[3], issue_slots[3].out_uop.iq_type[3] connect issue_slots[0].in_uop.bits.debug_pc, issue_slots[3].out_uop.debug_pc connect issue_slots[0].in_uop.bits.is_rvc, issue_slots[3].out_uop.is_rvc connect issue_slots[0].in_uop.bits.debug_inst, issue_slots[3].out_uop.debug_inst connect issue_slots[0].in_uop.bits.inst, issue_slots[3].out_uop.inst node _issue_slots_0_clear_T = neq(shamts_oh[0], UInt<1>(0h0)) connect issue_slots[0].clear, _issue_slots_0_clear_T connect issue_slots[1].in_uop.valid, UInt<1>(0h0) connect issue_slots[1].in_uop.bits.debug_tsrc, issue_slots[2].out_uop.debug_tsrc connect issue_slots[1].in_uop.bits.debug_fsrc, issue_slots[2].out_uop.debug_fsrc connect issue_slots[1].in_uop.bits.bp_xcpt_if, issue_slots[2].out_uop.bp_xcpt_if connect issue_slots[1].in_uop.bits.bp_debug_if, issue_slots[2].out_uop.bp_debug_if connect issue_slots[1].in_uop.bits.xcpt_ma_if, issue_slots[2].out_uop.xcpt_ma_if connect issue_slots[1].in_uop.bits.xcpt_ae_if, issue_slots[2].out_uop.xcpt_ae_if connect issue_slots[1].in_uop.bits.xcpt_pf_if, issue_slots[2].out_uop.xcpt_pf_if connect issue_slots[1].in_uop.bits.fp_typ, issue_slots[2].out_uop.fp_typ connect issue_slots[1].in_uop.bits.fp_rm, issue_slots[2].out_uop.fp_rm connect issue_slots[1].in_uop.bits.fp_val, issue_slots[2].out_uop.fp_val connect issue_slots[1].in_uop.bits.fcn_op, issue_slots[2].out_uop.fcn_op connect issue_slots[1].in_uop.bits.fcn_dw, issue_slots[2].out_uop.fcn_dw connect issue_slots[1].in_uop.bits.frs3_en, issue_slots[2].out_uop.frs3_en connect issue_slots[1].in_uop.bits.lrs2_rtype, issue_slots[2].out_uop.lrs2_rtype connect issue_slots[1].in_uop.bits.lrs1_rtype, issue_slots[2].out_uop.lrs1_rtype connect issue_slots[1].in_uop.bits.dst_rtype, issue_slots[2].out_uop.dst_rtype connect issue_slots[1].in_uop.bits.lrs3, issue_slots[2].out_uop.lrs3 connect issue_slots[1].in_uop.bits.lrs2, issue_slots[2].out_uop.lrs2 connect issue_slots[1].in_uop.bits.lrs1, issue_slots[2].out_uop.lrs1 connect issue_slots[1].in_uop.bits.ldst, issue_slots[2].out_uop.ldst connect issue_slots[1].in_uop.bits.ldst_is_rs1, issue_slots[2].out_uop.ldst_is_rs1 connect issue_slots[1].in_uop.bits.csr_cmd, issue_slots[2].out_uop.csr_cmd connect issue_slots[1].in_uop.bits.flush_on_commit, issue_slots[2].out_uop.flush_on_commit connect issue_slots[1].in_uop.bits.is_unique, issue_slots[2].out_uop.is_unique connect issue_slots[1].in_uop.bits.uses_stq, issue_slots[2].out_uop.uses_stq connect issue_slots[1].in_uop.bits.uses_ldq, issue_slots[2].out_uop.uses_ldq connect issue_slots[1].in_uop.bits.mem_signed, issue_slots[2].out_uop.mem_signed connect issue_slots[1].in_uop.bits.mem_size, issue_slots[2].out_uop.mem_size connect issue_slots[1].in_uop.bits.mem_cmd, issue_slots[2].out_uop.mem_cmd connect issue_slots[1].in_uop.bits.exc_cause, issue_slots[2].out_uop.exc_cause connect issue_slots[1].in_uop.bits.exception, issue_slots[2].out_uop.exception connect issue_slots[1].in_uop.bits.stale_pdst, issue_slots[2].out_uop.stale_pdst connect issue_slots[1].in_uop.bits.ppred_busy, issue_slots[2].out_uop.ppred_busy connect issue_slots[1].in_uop.bits.prs3_busy, issue_slots[2].out_uop.prs3_busy connect issue_slots[1].in_uop.bits.prs2_busy, issue_slots[2].out_uop.prs2_busy connect issue_slots[1].in_uop.bits.prs1_busy, issue_slots[2].out_uop.prs1_busy connect issue_slots[1].in_uop.bits.ppred, issue_slots[2].out_uop.ppred connect issue_slots[1].in_uop.bits.prs3, issue_slots[2].out_uop.prs3 connect issue_slots[1].in_uop.bits.prs2, issue_slots[2].out_uop.prs2 connect issue_slots[1].in_uop.bits.prs1, issue_slots[2].out_uop.prs1 connect issue_slots[1].in_uop.bits.pdst, issue_slots[2].out_uop.pdst connect issue_slots[1].in_uop.bits.rxq_idx, issue_slots[2].out_uop.rxq_idx connect issue_slots[1].in_uop.bits.stq_idx, issue_slots[2].out_uop.stq_idx connect issue_slots[1].in_uop.bits.ldq_idx, issue_slots[2].out_uop.ldq_idx connect issue_slots[1].in_uop.bits.rob_idx, issue_slots[2].out_uop.rob_idx connect issue_slots[1].in_uop.bits.fp_ctrl.vec, issue_slots[2].out_uop.fp_ctrl.vec connect issue_slots[1].in_uop.bits.fp_ctrl.wflags, issue_slots[2].out_uop.fp_ctrl.wflags connect issue_slots[1].in_uop.bits.fp_ctrl.sqrt, issue_slots[2].out_uop.fp_ctrl.sqrt connect issue_slots[1].in_uop.bits.fp_ctrl.div, issue_slots[2].out_uop.fp_ctrl.div connect issue_slots[1].in_uop.bits.fp_ctrl.fma, issue_slots[2].out_uop.fp_ctrl.fma connect issue_slots[1].in_uop.bits.fp_ctrl.fastpipe, issue_slots[2].out_uop.fp_ctrl.fastpipe connect issue_slots[1].in_uop.bits.fp_ctrl.toint, issue_slots[2].out_uop.fp_ctrl.toint connect issue_slots[1].in_uop.bits.fp_ctrl.fromint, issue_slots[2].out_uop.fp_ctrl.fromint connect issue_slots[1].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[2].out_uop.fp_ctrl.typeTagOut connect issue_slots[1].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[2].out_uop.fp_ctrl.typeTagIn connect issue_slots[1].in_uop.bits.fp_ctrl.swap23, issue_slots[2].out_uop.fp_ctrl.swap23 connect issue_slots[1].in_uop.bits.fp_ctrl.swap12, issue_slots[2].out_uop.fp_ctrl.swap12 connect issue_slots[1].in_uop.bits.fp_ctrl.ren3, issue_slots[2].out_uop.fp_ctrl.ren3 connect issue_slots[1].in_uop.bits.fp_ctrl.ren2, issue_slots[2].out_uop.fp_ctrl.ren2 connect issue_slots[1].in_uop.bits.fp_ctrl.ren1, issue_slots[2].out_uop.fp_ctrl.ren1 connect issue_slots[1].in_uop.bits.fp_ctrl.wen, issue_slots[2].out_uop.fp_ctrl.wen connect issue_slots[1].in_uop.bits.fp_ctrl.ldst, issue_slots[2].out_uop.fp_ctrl.ldst connect issue_slots[1].in_uop.bits.op2_sel, issue_slots[2].out_uop.op2_sel connect issue_slots[1].in_uop.bits.op1_sel, issue_slots[2].out_uop.op1_sel connect issue_slots[1].in_uop.bits.imm_packed, issue_slots[2].out_uop.imm_packed connect issue_slots[1].in_uop.bits.pimm, issue_slots[2].out_uop.pimm connect issue_slots[1].in_uop.bits.imm_sel, issue_slots[2].out_uop.imm_sel connect issue_slots[1].in_uop.bits.imm_rename, issue_slots[2].out_uop.imm_rename connect issue_slots[1].in_uop.bits.taken, issue_slots[2].out_uop.taken connect issue_slots[1].in_uop.bits.pc_lob, issue_slots[2].out_uop.pc_lob connect issue_slots[1].in_uop.bits.edge_inst, issue_slots[2].out_uop.edge_inst connect issue_slots[1].in_uop.bits.ftq_idx, issue_slots[2].out_uop.ftq_idx connect issue_slots[1].in_uop.bits.is_mov, issue_slots[2].out_uop.is_mov connect issue_slots[1].in_uop.bits.is_rocc, issue_slots[2].out_uop.is_rocc connect issue_slots[1].in_uop.bits.is_sys_pc2epc, issue_slots[2].out_uop.is_sys_pc2epc connect issue_slots[1].in_uop.bits.is_eret, issue_slots[2].out_uop.is_eret connect issue_slots[1].in_uop.bits.is_amo, issue_slots[2].out_uop.is_amo connect issue_slots[1].in_uop.bits.is_sfence, issue_slots[2].out_uop.is_sfence connect issue_slots[1].in_uop.bits.is_fencei, issue_slots[2].out_uop.is_fencei connect issue_slots[1].in_uop.bits.is_fence, issue_slots[2].out_uop.is_fence connect issue_slots[1].in_uop.bits.is_sfb, issue_slots[2].out_uop.is_sfb connect issue_slots[1].in_uop.bits.br_type, issue_slots[2].out_uop.br_type connect issue_slots[1].in_uop.bits.br_tag, issue_slots[2].out_uop.br_tag connect issue_slots[1].in_uop.bits.br_mask, issue_slots[2].out_uop.br_mask connect issue_slots[1].in_uop.bits.dis_col_sel, issue_slots[2].out_uop.dis_col_sel connect issue_slots[1].in_uop.bits.iw_p3_bypass_hint, issue_slots[2].out_uop.iw_p3_bypass_hint connect issue_slots[1].in_uop.bits.iw_p2_bypass_hint, issue_slots[2].out_uop.iw_p2_bypass_hint connect issue_slots[1].in_uop.bits.iw_p1_bypass_hint, issue_slots[2].out_uop.iw_p1_bypass_hint connect issue_slots[1].in_uop.bits.iw_p2_speculative_child, issue_slots[2].out_uop.iw_p2_speculative_child connect issue_slots[1].in_uop.bits.iw_p1_speculative_child, issue_slots[2].out_uop.iw_p1_speculative_child connect issue_slots[1].in_uop.bits.iw_issued_partial_dgen, issue_slots[2].out_uop.iw_issued_partial_dgen connect issue_slots[1].in_uop.bits.iw_issued_partial_agen, issue_slots[2].out_uop.iw_issued_partial_agen connect issue_slots[1].in_uop.bits.iw_issued, issue_slots[2].out_uop.iw_issued connect issue_slots[1].in_uop.bits.fu_code[0], issue_slots[2].out_uop.fu_code[0] connect issue_slots[1].in_uop.bits.fu_code[1], issue_slots[2].out_uop.fu_code[1] connect issue_slots[1].in_uop.bits.fu_code[2], issue_slots[2].out_uop.fu_code[2] connect issue_slots[1].in_uop.bits.fu_code[3], issue_slots[2].out_uop.fu_code[3] connect issue_slots[1].in_uop.bits.fu_code[4], issue_slots[2].out_uop.fu_code[4] connect issue_slots[1].in_uop.bits.fu_code[5], issue_slots[2].out_uop.fu_code[5] connect issue_slots[1].in_uop.bits.fu_code[6], issue_slots[2].out_uop.fu_code[6] connect issue_slots[1].in_uop.bits.fu_code[7], issue_slots[2].out_uop.fu_code[7] connect issue_slots[1].in_uop.bits.fu_code[8], issue_slots[2].out_uop.fu_code[8] connect issue_slots[1].in_uop.bits.fu_code[9], issue_slots[2].out_uop.fu_code[9] connect issue_slots[1].in_uop.bits.iq_type[0], issue_slots[2].out_uop.iq_type[0] connect issue_slots[1].in_uop.bits.iq_type[1], issue_slots[2].out_uop.iq_type[1] connect issue_slots[1].in_uop.bits.iq_type[2], issue_slots[2].out_uop.iq_type[2] connect issue_slots[1].in_uop.bits.iq_type[3], issue_slots[2].out_uop.iq_type[3] connect issue_slots[1].in_uop.bits.debug_pc, issue_slots[2].out_uop.debug_pc connect issue_slots[1].in_uop.bits.is_rvc, issue_slots[2].out_uop.is_rvc connect issue_slots[1].in_uop.bits.debug_inst, issue_slots[2].out_uop.debug_inst connect issue_slots[1].in_uop.bits.inst, issue_slots[2].out_uop.inst node _T_280 = eq(shamts_oh[2], UInt<1>(0h1)) when _T_280 : connect issue_slots[1].in_uop.valid, issue_slots[2].will_be_valid connect issue_slots[1].in_uop.bits.debug_tsrc, issue_slots[2].out_uop.debug_tsrc connect issue_slots[1].in_uop.bits.debug_fsrc, issue_slots[2].out_uop.debug_fsrc connect issue_slots[1].in_uop.bits.bp_xcpt_if, issue_slots[2].out_uop.bp_xcpt_if connect issue_slots[1].in_uop.bits.bp_debug_if, issue_slots[2].out_uop.bp_debug_if connect issue_slots[1].in_uop.bits.xcpt_ma_if, issue_slots[2].out_uop.xcpt_ma_if connect issue_slots[1].in_uop.bits.xcpt_ae_if, issue_slots[2].out_uop.xcpt_ae_if connect issue_slots[1].in_uop.bits.xcpt_pf_if, issue_slots[2].out_uop.xcpt_pf_if connect issue_slots[1].in_uop.bits.fp_typ, issue_slots[2].out_uop.fp_typ connect issue_slots[1].in_uop.bits.fp_rm, issue_slots[2].out_uop.fp_rm connect issue_slots[1].in_uop.bits.fp_val, issue_slots[2].out_uop.fp_val connect issue_slots[1].in_uop.bits.fcn_op, issue_slots[2].out_uop.fcn_op connect issue_slots[1].in_uop.bits.fcn_dw, issue_slots[2].out_uop.fcn_dw connect issue_slots[1].in_uop.bits.frs3_en, issue_slots[2].out_uop.frs3_en connect issue_slots[1].in_uop.bits.lrs2_rtype, issue_slots[2].out_uop.lrs2_rtype connect issue_slots[1].in_uop.bits.lrs1_rtype, issue_slots[2].out_uop.lrs1_rtype connect issue_slots[1].in_uop.bits.dst_rtype, issue_slots[2].out_uop.dst_rtype connect issue_slots[1].in_uop.bits.lrs3, issue_slots[2].out_uop.lrs3 connect issue_slots[1].in_uop.bits.lrs2, issue_slots[2].out_uop.lrs2 connect issue_slots[1].in_uop.bits.lrs1, issue_slots[2].out_uop.lrs1 connect issue_slots[1].in_uop.bits.ldst, issue_slots[2].out_uop.ldst connect issue_slots[1].in_uop.bits.ldst_is_rs1, issue_slots[2].out_uop.ldst_is_rs1 connect issue_slots[1].in_uop.bits.csr_cmd, issue_slots[2].out_uop.csr_cmd connect issue_slots[1].in_uop.bits.flush_on_commit, issue_slots[2].out_uop.flush_on_commit connect issue_slots[1].in_uop.bits.is_unique, issue_slots[2].out_uop.is_unique connect issue_slots[1].in_uop.bits.uses_stq, issue_slots[2].out_uop.uses_stq connect issue_slots[1].in_uop.bits.uses_ldq, issue_slots[2].out_uop.uses_ldq connect issue_slots[1].in_uop.bits.mem_signed, issue_slots[2].out_uop.mem_signed connect issue_slots[1].in_uop.bits.mem_size, issue_slots[2].out_uop.mem_size connect issue_slots[1].in_uop.bits.mem_cmd, issue_slots[2].out_uop.mem_cmd connect issue_slots[1].in_uop.bits.exc_cause, issue_slots[2].out_uop.exc_cause connect issue_slots[1].in_uop.bits.exception, issue_slots[2].out_uop.exception connect issue_slots[1].in_uop.bits.stale_pdst, issue_slots[2].out_uop.stale_pdst connect issue_slots[1].in_uop.bits.ppred_busy, issue_slots[2].out_uop.ppred_busy connect issue_slots[1].in_uop.bits.prs3_busy, issue_slots[2].out_uop.prs3_busy connect issue_slots[1].in_uop.bits.prs2_busy, issue_slots[2].out_uop.prs2_busy connect issue_slots[1].in_uop.bits.prs1_busy, issue_slots[2].out_uop.prs1_busy connect issue_slots[1].in_uop.bits.ppred, issue_slots[2].out_uop.ppred connect issue_slots[1].in_uop.bits.prs3, issue_slots[2].out_uop.prs3 connect issue_slots[1].in_uop.bits.prs2, issue_slots[2].out_uop.prs2 connect issue_slots[1].in_uop.bits.prs1, issue_slots[2].out_uop.prs1 connect issue_slots[1].in_uop.bits.pdst, issue_slots[2].out_uop.pdst connect issue_slots[1].in_uop.bits.rxq_idx, issue_slots[2].out_uop.rxq_idx connect issue_slots[1].in_uop.bits.stq_idx, issue_slots[2].out_uop.stq_idx connect issue_slots[1].in_uop.bits.ldq_idx, issue_slots[2].out_uop.ldq_idx connect issue_slots[1].in_uop.bits.rob_idx, issue_slots[2].out_uop.rob_idx connect issue_slots[1].in_uop.bits.fp_ctrl.vec, issue_slots[2].out_uop.fp_ctrl.vec connect issue_slots[1].in_uop.bits.fp_ctrl.wflags, issue_slots[2].out_uop.fp_ctrl.wflags connect issue_slots[1].in_uop.bits.fp_ctrl.sqrt, issue_slots[2].out_uop.fp_ctrl.sqrt connect issue_slots[1].in_uop.bits.fp_ctrl.div, issue_slots[2].out_uop.fp_ctrl.div connect issue_slots[1].in_uop.bits.fp_ctrl.fma, issue_slots[2].out_uop.fp_ctrl.fma connect issue_slots[1].in_uop.bits.fp_ctrl.fastpipe, issue_slots[2].out_uop.fp_ctrl.fastpipe connect issue_slots[1].in_uop.bits.fp_ctrl.toint, issue_slots[2].out_uop.fp_ctrl.toint connect issue_slots[1].in_uop.bits.fp_ctrl.fromint, issue_slots[2].out_uop.fp_ctrl.fromint connect issue_slots[1].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[2].out_uop.fp_ctrl.typeTagOut connect issue_slots[1].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[2].out_uop.fp_ctrl.typeTagIn connect issue_slots[1].in_uop.bits.fp_ctrl.swap23, issue_slots[2].out_uop.fp_ctrl.swap23 connect issue_slots[1].in_uop.bits.fp_ctrl.swap12, issue_slots[2].out_uop.fp_ctrl.swap12 connect issue_slots[1].in_uop.bits.fp_ctrl.ren3, issue_slots[2].out_uop.fp_ctrl.ren3 connect issue_slots[1].in_uop.bits.fp_ctrl.ren2, issue_slots[2].out_uop.fp_ctrl.ren2 connect issue_slots[1].in_uop.bits.fp_ctrl.ren1, issue_slots[2].out_uop.fp_ctrl.ren1 connect issue_slots[1].in_uop.bits.fp_ctrl.wen, issue_slots[2].out_uop.fp_ctrl.wen connect issue_slots[1].in_uop.bits.fp_ctrl.ldst, issue_slots[2].out_uop.fp_ctrl.ldst connect issue_slots[1].in_uop.bits.op2_sel, issue_slots[2].out_uop.op2_sel connect issue_slots[1].in_uop.bits.op1_sel, issue_slots[2].out_uop.op1_sel connect issue_slots[1].in_uop.bits.imm_packed, issue_slots[2].out_uop.imm_packed connect issue_slots[1].in_uop.bits.pimm, issue_slots[2].out_uop.pimm connect issue_slots[1].in_uop.bits.imm_sel, issue_slots[2].out_uop.imm_sel connect issue_slots[1].in_uop.bits.imm_rename, issue_slots[2].out_uop.imm_rename connect issue_slots[1].in_uop.bits.taken, issue_slots[2].out_uop.taken connect issue_slots[1].in_uop.bits.pc_lob, issue_slots[2].out_uop.pc_lob connect issue_slots[1].in_uop.bits.edge_inst, issue_slots[2].out_uop.edge_inst connect issue_slots[1].in_uop.bits.ftq_idx, issue_slots[2].out_uop.ftq_idx connect issue_slots[1].in_uop.bits.is_mov, issue_slots[2].out_uop.is_mov connect issue_slots[1].in_uop.bits.is_rocc, issue_slots[2].out_uop.is_rocc connect issue_slots[1].in_uop.bits.is_sys_pc2epc, issue_slots[2].out_uop.is_sys_pc2epc connect issue_slots[1].in_uop.bits.is_eret, issue_slots[2].out_uop.is_eret connect issue_slots[1].in_uop.bits.is_amo, issue_slots[2].out_uop.is_amo connect issue_slots[1].in_uop.bits.is_sfence, issue_slots[2].out_uop.is_sfence connect issue_slots[1].in_uop.bits.is_fencei, issue_slots[2].out_uop.is_fencei connect issue_slots[1].in_uop.bits.is_fence, issue_slots[2].out_uop.is_fence connect issue_slots[1].in_uop.bits.is_sfb, issue_slots[2].out_uop.is_sfb connect issue_slots[1].in_uop.bits.br_type, issue_slots[2].out_uop.br_type connect issue_slots[1].in_uop.bits.br_tag, issue_slots[2].out_uop.br_tag connect issue_slots[1].in_uop.bits.br_mask, issue_slots[2].out_uop.br_mask connect issue_slots[1].in_uop.bits.dis_col_sel, issue_slots[2].out_uop.dis_col_sel connect issue_slots[1].in_uop.bits.iw_p3_bypass_hint, issue_slots[2].out_uop.iw_p3_bypass_hint connect issue_slots[1].in_uop.bits.iw_p2_bypass_hint, issue_slots[2].out_uop.iw_p2_bypass_hint connect issue_slots[1].in_uop.bits.iw_p1_bypass_hint, issue_slots[2].out_uop.iw_p1_bypass_hint connect issue_slots[1].in_uop.bits.iw_p2_speculative_child, issue_slots[2].out_uop.iw_p2_speculative_child connect issue_slots[1].in_uop.bits.iw_p1_speculative_child, issue_slots[2].out_uop.iw_p1_speculative_child connect issue_slots[1].in_uop.bits.iw_issued_partial_dgen, issue_slots[2].out_uop.iw_issued_partial_dgen connect issue_slots[1].in_uop.bits.iw_issued_partial_agen, issue_slots[2].out_uop.iw_issued_partial_agen connect issue_slots[1].in_uop.bits.iw_issued, issue_slots[2].out_uop.iw_issued connect issue_slots[1].in_uop.bits.fu_code[0], issue_slots[2].out_uop.fu_code[0] connect issue_slots[1].in_uop.bits.fu_code[1], issue_slots[2].out_uop.fu_code[1] connect issue_slots[1].in_uop.bits.fu_code[2], issue_slots[2].out_uop.fu_code[2] connect issue_slots[1].in_uop.bits.fu_code[3], issue_slots[2].out_uop.fu_code[3] connect issue_slots[1].in_uop.bits.fu_code[4], issue_slots[2].out_uop.fu_code[4] connect issue_slots[1].in_uop.bits.fu_code[5], issue_slots[2].out_uop.fu_code[5] connect issue_slots[1].in_uop.bits.fu_code[6], issue_slots[2].out_uop.fu_code[6] connect issue_slots[1].in_uop.bits.fu_code[7], issue_slots[2].out_uop.fu_code[7] connect issue_slots[1].in_uop.bits.fu_code[8], issue_slots[2].out_uop.fu_code[8] connect issue_slots[1].in_uop.bits.fu_code[9], issue_slots[2].out_uop.fu_code[9] connect issue_slots[1].in_uop.bits.iq_type[0], issue_slots[2].out_uop.iq_type[0] connect issue_slots[1].in_uop.bits.iq_type[1], issue_slots[2].out_uop.iq_type[1] connect issue_slots[1].in_uop.bits.iq_type[2], issue_slots[2].out_uop.iq_type[2] connect issue_slots[1].in_uop.bits.iq_type[3], issue_slots[2].out_uop.iq_type[3] connect issue_slots[1].in_uop.bits.debug_pc, issue_slots[2].out_uop.debug_pc connect issue_slots[1].in_uop.bits.is_rvc, issue_slots[2].out_uop.is_rvc connect issue_slots[1].in_uop.bits.debug_inst, issue_slots[2].out_uop.debug_inst connect issue_slots[1].in_uop.bits.inst, issue_slots[2].out_uop.inst node _T_281 = eq(shamts_oh[3], UInt<2>(0h2)) when _T_281 : connect issue_slots[1].in_uop.valid, issue_slots[3].will_be_valid connect issue_slots[1].in_uop.bits.debug_tsrc, issue_slots[3].out_uop.debug_tsrc connect issue_slots[1].in_uop.bits.debug_fsrc, issue_slots[3].out_uop.debug_fsrc connect issue_slots[1].in_uop.bits.bp_xcpt_if, issue_slots[3].out_uop.bp_xcpt_if connect issue_slots[1].in_uop.bits.bp_debug_if, issue_slots[3].out_uop.bp_debug_if connect issue_slots[1].in_uop.bits.xcpt_ma_if, issue_slots[3].out_uop.xcpt_ma_if connect issue_slots[1].in_uop.bits.xcpt_ae_if, issue_slots[3].out_uop.xcpt_ae_if connect issue_slots[1].in_uop.bits.xcpt_pf_if, issue_slots[3].out_uop.xcpt_pf_if connect issue_slots[1].in_uop.bits.fp_typ, issue_slots[3].out_uop.fp_typ connect issue_slots[1].in_uop.bits.fp_rm, issue_slots[3].out_uop.fp_rm connect issue_slots[1].in_uop.bits.fp_val, issue_slots[3].out_uop.fp_val connect issue_slots[1].in_uop.bits.fcn_op, issue_slots[3].out_uop.fcn_op connect issue_slots[1].in_uop.bits.fcn_dw, issue_slots[3].out_uop.fcn_dw connect issue_slots[1].in_uop.bits.frs3_en, issue_slots[3].out_uop.frs3_en connect issue_slots[1].in_uop.bits.lrs2_rtype, issue_slots[3].out_uop.lrs2_rtype connect issue_slots[1].in_uop.bits.lrs1_rtype, issue_slots[3].out_uop.lrs1_rtype connect issue_slots[1].in_uop.bits.dst_rtype, issue_slots[3].out_uop.dst_rtype connect issue_slots[1].in_uop.bits.lrs3, issue_slots[3].out_uop.lrs3 connect issue_slots[1].in_uop.bits.lrs2, issue_slots[3].out_uop.lrs2 connect issue_slots[1].in_uop.bits.lrs1, issue_slots[3].out_uop.lrs1 connect issue_slots[1].in_uop.bits.ldst, issue_slots[3].out_uop.ldst connect issue_slots[1].in_uop.bits.ldst_is_rs1, issue_slots[3].out_uop.ldst_is_rs1 connect issue_slots[1].in_uop.bits.csr_cmd, issue_slots[3].out_uop.csr_cmd connect issue_slots[1].in_uop.bits.flush_on_commit, issue_slots[3].out_uop.flush_on_commit connect issue_slots[1].in_uop.bits.is_unique, issue_slots[3].out_uop.is_unique connect issue_slots[1].in_uop.bits.uses_stq, issue_slots[3].out_uop.uses_stq connect issue_slots[1].in_uop.bits.uses_ldq, issue_slots[3].out_uop.uses_ldq connect issue_slots[1].in_uop.bits.mem_signed, issue_slots[3].out_uop.mem_signed connect issue_slots[1].in_uop.bits.mem_size, issue_slots[3].out_uop.mem_size connect issue_slots[1].in_uop.bits.mem_cmd, issue_slots[3].out_uop.mem_cmd connect issue_slots[1].in_uop.bits.exc_cause, issue_slots[3].out_uop.exc_cause connect issue_slots[1].in_uop.bits.exception, issue_slots[3].out_uop.exception connect issue_slots[1].in_uop.bits.stale_pdst, issue_slots[3].out_uop.stale_pdst connect issue_slots[1].in_uop.bits.ppred_busy, issue_slots[3].out_uop.ppred_busy connect issue_slots[1].in_uop.bits.prs3_busy, issue_slots[3].out_uop.prs3_busy connect issue_slots[1].in_uop.bits.prs2_busy, issue_slots[3].out_uop.prs2_busy connect issue_slots[1].in_uop.bits.prs1_busy, issue_slots[3].out_uop.prs1_busy connect issue_slots[1].in_uop.bits.ppred, issue_slots[3].out_uop.ppred connect issue_slots[1].in_uop.bits.prs3, issue_slots[3].out_uop.prs3 connect issue_slots[1].in_uop.bits.prs2, issue_slots[3].out_uop.prs2 connect issue_slots[1].in_uop.bits.prs1, issue_slots[3].out_uop.prs1 connect issue_slots[1].in_uop.bits.pdst, issue_slots[3].out_uop.pdst connect issue_slots[1].in_uop.bits.rxq_idx, issue_slots[3].out_uop.rxq_idx connect issue_slots[1].in_uop.bits.stq_idx, issue_slots[3].out_uop.stq_idx connect issue_slots[1].in_uop.bits.ldq_idx, issue_slots[3].out_uop.ldq_idx connect issue_slots[1].in_uop.bits.rob_idx, issue_slots[3].out_uop.rob_idx connect issue_slots[1].in_uop.bits.fp_ctrl.vec, issue_slots[3].out_uop.fp_ctrl.vec connect issue_slots[1].in_uop.bits.fp_ctrl.wflags, issue_slots[3].out_uop.fp_ctrl.wflags connect issue_slots[1].in_uop.bits.fp_ctrl.sqrt, issue_slots[3].out_uop.fp_ctrl.sqrt connect issue_slots[1].in_uop.bits.fp_ctrl.div, issue_slots[3].out_uop.fp_ctrl.div connect issue_slots[1].in_uop.bits.fp_ctrl.fma, issue_slots[3].out_uop.fp_ctrl.fma connect issue_slots[1].in_uop.bits.fp_ctrl.fastpipe, issue_slots[3].out_uop.fp_ctrl.fastpipe connect issue_slots[1].in_uop.bits.fp_ctrl.toint, issue_slots[3].out_uop.fp_ctrl.toint connect issue_slots[1].in_uop.bits.fp_ctrl.fromint, issue_slots[3].out_uop.fp_ctrl.fromint connect issue_slots[1].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[3].out_uop.fp_ctrl.typeTagOut connect issue_slots[1].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[3].out_uop.fp_ctrl.typeTagIn connect issue_slots[1].in_uop.bits.fp_ctrl.swap23, issue_slots[3].out_uop.fp_ctrl.swap23 connect issue_slots[1].in_uop.bits.fp_ctrl.swap12, issue_slots[3].out_uop.fp_ctrl.swap12 connect issue_slots[1].in_uop.bits.fp_ctrl.ren3, issue_slots[3].out_uop.fp_ctrl.ren3 connect issue_slots[1].in_uop.bits.fp_ctrl.ren2, issue_slots[3].out_uop.fp_ctrl.ren2 connect issue_slots[1].in_uop.bits.fp_ctrl.ren1, issue_slots[3].out_uop.fp_ctrl.ren1 connect issue_slots[1].in_uop.bits.fp_ctrl.wen, issue_slots[3].out_uop.fp_ctrl.wen connect issue_slots[1].in_uop.bits.fp_ctrl.ldst, issue_slots[3].out_uop.fp_ctrl.ldst connect issue_slots[1].in_uop.bits.op2_sel, issue_slots[3].out_uop.op2_sel connect issue_slots[1].in_uop.bits.op1_sel, issue_slots[3].out_uop.op1_sel connect issue_slots[1].in_uop.bits.imm_packed, issue_slots[3].out_uop.imm_packed connect issue_slots[1].in_uop.bits.pimm, issue_slots[3].out_uop.pimm connect issue_slots[1].in_uop.bits.imm_sel, issue_slots[3].out_uop.imm_sel connect issue_slots[1].in_uop.bits.imm_rename, issue_slots[3].out_uop.imm_rename connect issue_slots[1].in_uop.bits.taken, issue_slots[3].out_uop.taken connect issue_slots[1].in_uop.bits.pc_lob, issue_slots[3].out_uop.pc_lob connect issue_slots[1].in_uop.bits.edge_inst, issue_slots[3].out_uop.edge_inst connect issue_slots[1].in_uop.bits.ftq_idx, issue_slots[3].out_uop.ftq_idx connect issue_slots[1].in_uop.bits.is_mov, issue_slots[3].out_uop.is_mov connect issue_slots[1].in_uop.bits.is_rocc, issue_slots[3].out_uop.is_rocc connect issue_slots[1].in_uop.bits.is_sys_pc2epc, issue_slots[3].out_uop.is_sys_pc2epc connect issue_slots[1].in_uop.bits.is_eret, issue_slots[3].out_uop.is_eret connect issue_slots[1].in_uop.bits.is_amo, issue_slots[3].out_uop.is_amo connect issue_slots[1].in_uop.bits.is_sfence, issue_slots[3].out_uop.is_sfence connect issue_slots[1].in_uop.bits.is_fencei, issue_slots[3].out_uop.is_fencei connect issue_slots[1].in_uop.bits.is_fence, issue_slots[3].out_uop.is_fence connect issue_slots[1].in_uop.bits.is_sfb, issue_slots[3].out_uop.is_sfb connect issue_slots[1].in_uop.bits.br_type, issue_slots[3].out_uop.br_type connect issue_slots[1].in_uop.bits.br_tag, issue_slots[3].out_uop.br_tag connect issue_slots[1].in_uop.bits.br_mask, issue_slots[3].out_uop.br_mask connect issue_slots[1].in_uop.bits.dis_col_sel, issue_slots[3].out_uop.dis_col_sel connect issue_slots[1].in_uop.bits.iw_p3_bypass_hint, issue_slots[3].out_uop.iw_p3_bypass_hint connect issue_slots[1].in_uop.bits.iw_p2_bypass_hint, issue_slots[3].out_uop.iw_p2_bypass_hint connect issue_slots[1].in_uop.bits.iw_p1_bypass_hint, issue_slots[3].out_uop.iw_p1_bypass_hint connect issue_slots[1].in_uop.bits.iw_p2_speculative_child, issue_slots[3].out_uop.iw_p2_speculative_child connect issue_slots[1].in_uop.bits.iw_p1_speculative_child, issue_slots[3].out_uop.iw_p1_speculative_child connect issue_slots[1].in_uop.bits.iw_issued_partial_dgen, issue_slots[3].out_uop.iw_issued_partial_dgen connect issue_slots[1].in_uop.bits.iw_issued_partial_agen, issue_slots[3].out_uop.iw_issued_partial_agen connect issue_slots[1].in_uop.bits.iw_issued, issue_slots[3].out_uop.iw_issued connect issue_slots[1].in_uop.bits.fu_code[0], issue_slots[3].out_uop.fu_code[0] connect issue_slots[1].in_uop.bits.fu_code[1], issue_slots[3].out_uop.fu_code[1] connect issue_slots[1].in_uop.bits.fu_code[2], issue_slots[3].out_uop.fu_code[2] connect issue_slots[1].in_uop.bits.fu_code[3], issue_slots[3].out_uop.fu_code[3] connect issue_slots[1].in_uop.bits.fu_code[4], issue_slots[3].out_uop.fu_code[4] connect issue_slots[1].in_uop.bits.fu_code[5], issue_slots[3].out_uop.fu_code[5] connect issue_slots[1].in_uop.bits.fu_code[6], issue_slots[3].out_uop.fu_code[6] connect issue_slots[1].in_uop.bits.fu_code[7], issue_slots[3].out_uop.fu_code[7] connect issue_slots[1].in_uop.bits.fu_code[8], issue_slots[3].out_uop.fu_code[8] connect issue_slots[1].in_uop.bits.fu_code[9], issue_slots[3].out_uop.fu_code[9] connect issue_slots[1].in_uop.bits.iq_type[0], issue_slots[3].out_uop.iq_type[0] connect issue_slots[1].in_uop.bits.iq_type[1], issue_slots[3].out_uop.iq_type[1] connect issue_slots[1].in_uop.bits.iq_type[2], issue_slots[3].out_uop.iq_type[2] connect issue_slots[1].in_uop.bits.iq_type[3], issue_slots[3].out_uop.iq_type[3] connect issue_slots[1].in_uop.bits.debug_pc, issue_slots[3].out_uop.debug_pc connect issue_slots[1].in_uop.bits.is_rvc, issue_slots[3].out_uop.is_rvc connect issue_slots[1].in_uop.bits.debug_inst, issue_slots[3].out_uop.debug_inst connect issue_slots[1].in_uop.bits.inst, issue_slots[3].out_uop.inst node _T_282 = eq(shamts_oh[4], UInt<3>(0h4)) when _T_282 : connect issue_slots[1].in_uop.valid, issue_slots[4].will_be_valid connect issue_slots[1].in_uop.bits.debug_tsrc, issue_slots[4].out_uop.debug_tsrc connect issue_slots[1].in_uop.bits.debug_fsrc, issue_slots[4].out_uop.debug_fsrc connect issue_slots[1].in_uop.bits.bp_xcpt_if, issue_slots[4].out_uop.bp_xcpt_if connect issue_slots[1].in_uop.bits.bp_debug_if, issue_slots[4].out_uop.bp_debug_if connect issue_slots[1].in_uop.bits.xcpt_ma_if, issue_slots[4].out_uop.xcpt_ma_if connect issue_slots[1].in_uop.bits.xcpt_ae_if, issue_slots[4].out_uop.xcpt_ae_if connect issue_slots[1].in_uop.bits.xcpt_pf_if, issue_slots[4].out_uop.xcpt_pf_if connect issue_slots[1].in_uop.bits.fp_typ, issue_slots[4].out_uop.fp_typ connect issue_slots[1].in_uop.bits.fp_rm, issue_slots[4].out_uop.fp_rm connect issue_slots[1].in_uop.bits.fp_val, issue_slots[4].out_uop.fp_val connect issue_slots[1].in_uop.bits.fcn_op, issue_slots[4].out_uop.fcn_op connect issue_slots[1].in_uop.bits.fcn_dw, issue_slots[4].out_uop.fcn_dw connect issue_slots[1].in_uop.bits.frs3_en, issue_slots[4].out_uop.frs3_en connect issue_slots[1].in_uop.bits.lrs2_rtype, issue_slots[4].out_uop.lrs2_rtype connect issue_slots[1].in_uop.bits.lrs1_rtype, issue_slots[4].out_uop.lrs1_rtype connect issue_slots[1].in_uop.bits.dst_rtype, issue_slots[4].out_uop.dst_rtype connect issue_slots[1].in_uop.bits.lrs3, issue_slots[4].out_uop.lrs3 connect issue_slots[1].in_uop.bits.lrs2, issue_slots[4].out_uop.lrs2 connect issue_slots[1].in_uop.bits.lrs1, issue_slots[4].out_uop.lrs1 connect issue_slots[1].in_uop.bits.ldst, issue_slots[4].out_uop.ldst connect issue_slots[1].in_uop.bits.ldst_is_rs1, issue_slots[4].out_uop.ldst_is_rs1 connect issue_slots[1].in_uop.bits.csr_cmd, issue_slots[4].out_uop.csr_cmd connect issue_slots[1].in_uop.bits.flush_on_commit, issue_slots[4].out_uop.flush_on_commit connect issue_slots[1].in_uop.bits.is_unique, issue_slots[4].out_uop.is_unique connect issue_slots[1].in_uop.bits.uses_stq, issue_slots[4].out_uop.uses_stq connect issue_slots[1].in_uop.bits.uses_ldq, issue_slots[4].out_uop.uses_ldq connect issue_slots[1].in_uop.bits.mem_signed, issue_slots[4].out_uop.mem_signed connect issue_slots[1].in_uop.bits.mem_size, issue_slots[4].out_uop.mem_size connect issue_slots[1].in_uop.bits.mem_cmd, issue_slots[4].out_uop.mem_cmd connect issue_slots[1].in_uop.bits.exc_cause, issue_slots[4].out_uop.exc_cause connect issue_slots[1].in_uop.bits.exception, issue_slots[4].out_uop.exception connect issue_slots[1].in_uop.bits.stale_pdst, issue_slots[4].out_uop.stale_pdst connect issue_slots[1].in_uop.bits.ppred_busy, issue_slots[4].out_uop.ppred_busy connect issue_slots[1].in_uop.bits.prs3_busy, issue_slots[4].out_uop.prs3_busy connect issue_slots[1].in_uop.bits.prs2_busy, issue_slots[4].out_uop.prs2_busy connect issue_slots[1].in_uop.bits.prs1_busy, issue_slots[4].out_uop.prs1_busy connect issue_slots[1].in_uop.bits.ppred, issue_slots[4].out_uop.ppred connect issue_slots[1].in_uop.bits.prs3, issue_slots[4].out_uop.prs3 connect issue_slots[1].in_uop.bits.prs2, issue_slots[4].out_uop.prs2 connect issue_slots[1].in_uop.bits.prs1, issue_slots[4].out_uop.prs1 connect issue_slots[1].in_uop.bits.pdst, issue_slots[4].out_uop.pdst connect issue_slots[1].in_uop.bits.rxq_idx, issue_slots[4].out_uop.rxq_idx connect issue_slots[1].in_uop.bits.stq_idx, issue_slots[4].out_uop.stq_idx connect issue_slots[1].in_uop.bits.ldq_idx, issue_slots[4].out_uop.ldq_idx connect issue_slots[1].in_uop.bits.rob_idx, issue_slots[4].out_uop.rob_idx connect issue_slots[1].in_uop.bits.fp_ctrl.vec, issue_slots[4].out_uop.fp_ctrl.vec connect issue_slots[1].in_uop.bits.fp_ctrl.wflags, issue_slots[4].out_uop.fp_ctrl.wflags connect issue_slots[1].in_uop.bits.fp_ctrl.sqrt, issue_slots[4].out_uop.fp_ctrl.sqrt connect issue_slots[1].in_uop.bits.fp_ctrl.div, issue_slots[4].out_uop.fp_ctrl.div connect issue_slots[1].in_uop.bits.fp_ctrl.fma, issue_slots[4].out_uop.fp_ctrl.fma connect issue_slots[1].in_uop.bits.fp_ctrl.fastpipe, issue_slots[4].out_uop.fp_ctrl.fastpipe connect issue_slots[1].in_uop.bits.fp_ctrl.toint, issue_slots[4].out_uop.fp_ctrl.toint connect issue_slots[1].in_uop.bits.fp_ctrl.fromint, issue_slots[4].out_uop.fp_ctrl.fromint connect issue_slots[1].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[4].out_uop.fp_ctrl.typeTagOut connect issue_slots[1].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[4].out_uop.fp_ctrl.typeTagIn connect issue_slots[1].in_uop.bits.fp_ctrl.swap23, issue_slots[4].out_uop.fp_ctrl.swap23 connect issue_slots[1].in_uop.bits.fp_ctrl.swap12, issue_slots[4].out_uop.fp_ctrl.swap12 connect issue_slots[1].in_uop.bits.fp_ctrl.ren3, issue_slots[4].out_uop.fp_ctrl.ren3 connect issue_slots[1].in_uop.bits.fp_ctrl.ren2, issue_slots[4].out_uop.fp_ctrl.ren2 connect issue_slots[1].in_uop.bits.fp_ctrl.ren1, issue_slots[4].out_uop.fp_ctrl.ren1 connect issue_slots[1].in_uop.bits.fp_ctrl.wen, issue_slots[4].out_uop.fp_ctrl.wen connect issue_slots[1].in_uop.bits.fp_ctrl.ldst, issue_slots[4].out_uop.fp_ctrl.ldst connect issue_slots[1].in_uop.bits.op2_sel, issue_slots[4].out_uop.op2_sel connect issue_slots[1].in_uop.bits.op1_sel, issue_slots[4].out_uop.op1_sel connect issue_slots[1].in_uop.bits.imm_packed, issue_slots[4].out_uop.imm_packed connect issue_slots[1].in_uop.bits.pimm, issue_slots[4].out_uop.pimm connect issue_slots[1].in_uop.bits.imm_sel, issue_slots[4].out_uop.imm_sel connect issue_slots[1].in_uop.bits.imm_rename, issue_slots[4].out_uop.imm_rename connect issue_slots[1].in_uop.bits.taken, issue_slots[4].out_uop.taken connect issue_slots[1].in_uop.bits.pc_lob, issue_slots[4].out_uop.pc_lob connect issue_slots[1].in_uop.bits.edge_inst, issue_slots[4].out_uop.edge_inst connect issue_slots[1].in_uop.bits.ftq_idx, issue_slots[4].out_uop.ftq_idx connect issue_slots[1].in_uop.bits.is_mov, issue_slots[4].out_uop.is_mov connect issue_slots[1].in_uop.bits.is_rocc, issue_slots[4].out_uop.is_rocc connect issue_slots[1].in_uop.bits.is_sys_pc2epc, issue_slots[4].out_uop.is_sys_pc2epc connect issue_slots[1].in_uop.bits.is_eret, issue_slots[4].out_uop.is_eret connect issue_slots[1].in_uop.bits.is_amo, issue_slots[4].out_uop.is_amo connect issue_slots[1].in_uop.bits.is_sfence, issue_slots[4].out_uop.is_sfence connect issue_slots[1].in_uop.bits.is_fencei, issue_slots[4].out_uop.is_fencei connect issue_slots[1].in_uop.bits.is_fence, issue_slots[4].out_uop.is_fence connect issue_slots[1].in_uop.bits.is_sfb, issue_slots[4].out_uop.is_sfb connect issue_slots[1].in_uop.bits.br_type, issue_slots[4].out_uop.br_type connect issue_slots[1].in_uop.bits.br_tag, issue_slots[4].out_uop.br_tag connect issue_slots[1].in_uop.bits.br_mask, issue_slots[4].out_uop.br_mask connect issue_slots[1].in_uop.bits.dis_col_sel, issue_slots[4].out_uop.dis_col_sel connect issue_slots[1].in_uop.bits.iw_p3_bypass_hint, issue_slots[4].out_uop.iw_p3_bypass_hint connect issue_slots[1].in_uop.bits.iw_p2_bypass_hint, issue_slots[4].out_uop.iw_p2_bypass_hint connect issue_slots[1].in_uop.bits.iw_p1_bypass_hint, issue_slots[4].out_uop.iw_p1_bypass_hint connect issue_slots[1].in_uop.bits.iw_p2_speculative_child, issue_slots[4].out_uop.iw_p2_speculative_child connect issue_slots[1].in_uop.bits.iw_p1_speculative_child, issue_slots[4].out_uop.iw_p1_speculative_child connect issue_slots[1].in_uop.bits.iw_issued_partial_dgen, issue_slots[4].out_uop.iw_issued_partial_dgen connect issue_slots[1].in_uop.bits.iw_issued_partial_agen, issue_slots[4].out_uop.iw_issued_partial_agen connect issue_slots[1].in_uop.bits.iw_issued, issue_slots[4].out_uop.iw_issued connect issue_slots[1].in_uop.bits.fu_code[0], issue_slots[4].out_uop.fu_code[0] connect issue_slots[1].in_uop.bits.fu_code[1], issue_slots[4].out_uop.fu_code[1] connect issue_slots[1].in_uop.bits.fu_code[2], issue_slots[4].out_uop.fu_code[2] connect issue_slots[1].in_uop.bits.fu_code[3], issue_slots[4].out_uop.fu_code[3] connect issue_slots[1].in_uop.bits.fu_code[4], issue_slots[4].out_uop.fu_code[4] connect issue_slots[1].in_uop.bits.fu_code[5], issue_slots[4].out_uop.fu_code[5] connect issue_slots[1].in_uop.bits.fu_code[6], issue_slots[4].out_uop.fu_code[6] connect issue_slots[1].in_uop.bits.fu_code[7], issue_slots[4].out_uop.fu_code[7] connect issue_slots[1].in_uop.bits.fu_code[8], issue_slots[4].out_uop.fu_code[8] connect issue_slots[1].in_uop.bits.fu_code[9], issue_slots[4].out_uop.fu_code[9] connect issue_slots[1].in_uop.bits.iq_type[0], issue_slots[4].out_uop.iq_type[0] connect issue_slots[1].in_uop.bits.iq_type[1], issue_slots[4].out_uop.iq_type[1] connect issue_slots[1].in_uop.bits.iq_type[2], issue_slots[4].out_uop.iq_type[2] connect issue_slots[1].in_uop.bits.iq_type[3], issue_slots[4].out_uop.iq_type[3] connect issue_slots[1].in_uop.bits.debug_pc, issue_slots[4].out_uop.debug_pc connect issue_slots[1].in_uop.bits.is_rvc, issue_slots[4].out_uop.is_rvc connect issue_slots[1].in_uop.bits.debug_inst, issue_slots[4].out_uop.debug_inst connect issue_slots[1].in_uop.bits.inst, issue_slots[4].out_uop.inst node _issue_slots_1_clear_T = neq(shamts_oh[1], UInt<1>(0h0)) connect issue_slots[1].clear, _issue_slots_1_clear_T connect issue_slots[2].in_uop.valid, UInt<1>(0h0) connect issue_slots[2].in_uop.bits.debug_tsrc, issue_slots[3].out_uop.debug_tsrc connect issue_slots[2].in_uop.bits.debug_fsrc, issue_slots[3].out_uop.debug_fsrc connect issue_slots[2].in_uop.bits.bp_xcpt_if, issue_slots[3].out_uop.bp_xcpt_if connect issue_slots[2].in_uop.bits.bp_debug_if, issue_slots[3].out_uop.bp_debug_if connect issue_slots[2].in_uop.bits.xcpt_ma_if, issue_slots[3].out_uop.xcpt_ma_if connect issue_slots[2].in_uop.bits.xcpt_ae_if, issue_slots[3].out_uop.xcpt_ae_if connect issue_slots[2].in_uop.bits.xcpt_pf_if, issue_slots[3].out_uop.xcpt_pf_if connect issue_slots[2].in_uop.bits.fp_typ, issue_slots[3].out_uop.fp_typ connect issue_slots[2].in_uop.bits.fp_rm, issue_slots[3].out_uop.fp_rm connect issue_slots[2].in_uop.bits.fp_val, issue_slots[3].out_uop.fp_val connect issue_slots[2].in_uop.bits.fcn_op, issue_slots[3].out_uop.fcn_op connect issue_slots[2].in_uop.bits.fcn_dw, issue_slots[3].out_uop.fcn_dw connect issue_slots[2].in_uop.bits.frs3_en, issue_slots[3].out_uop.frs3_en connect issue_slots[2].in_uop.bits.lrs2_rtype, issue_slots[3].out_uop.lrs2_rtype connect issue_slots[2].in_uop.bits.lrs1_rtype, issue_slots[3].out_uop.lrs1_rtype connect issue_slots[2].in_uop.bits.dst_rtype, issue_slots[3].out_uop.dst_rtype connect issue_slots[2].in_uop.bits.lrs3, issue_slots[3].out_uop.lrs3 connect issue_slots[2].in_uop.bits.lrs2, issue_slots[3].out_uop.lrs2 connect issue_slots[2].in_uop.bits.lrs1, issue_slots[3].out_uop.lrs1 connect issue_slots[2].in_uop.bits.ldst, issue_slots[3].out_uop.ldst connect issue_slots[2].in_uop.bits.ldst_is_rs1, issue_slots[3].out_uop.ldst_is_rs1 connect issue_slots[2].in_uop.bits.csr_cmd, issue_slots[3].out_uop.csr_cmd connect issue_slots[2].in_uop.bits.flush_on_commit, issue_slots[3].out_uop.flush_on_commit connect issue_slots[2].in_uop.bits.is_unique, issue_slots[3].out_uop.is_unique connect issue_slots[2].in_uop.bits.uses_stq, issue_slots[3].out_uop.uses_stq connect issue_slots[2].in_uop.bits.uses_ldq, issue_slots[3].out_uop.uses_ldq connect issue_slots[2].in_uop.bits.mem_signed, issue_slots[3].out_uop.mem_signed connect issue_slots[2].in_uop.bits.mem_size, issue_slots[3].out_uop.mem_size connect issue_slots[2].in_uop.bits.mem_cmd, issue_slots[3].out_uop.mem_cmd connect issue_slots[2].in_uop.bits.exc_cause, issue_slots[3].out_uop.exc_cause connect issue_slots[2].in_uop.bits.exception, issue_slots[3].out_uop.exception connect issue_slots[2].in_uop.bits.stale_pdst, issue_slots[3].out_uop.stale_pdst connect issue_slots[2].in_uop.bits.ppred_busy, issue_slots[3].out_uop.ppred_busy connect issue_slots[2].in_uop.bits.prs3_busy, issue_slots[3].out_uop.prs3_busy connect issue_slots[2].in_uop.bits.prs2_busy, issue_slots[3].out_uop.prs2_busy connect issue_slots[2].in_uop.bits.prs1_busy, issue_slots[3].out_uop.prs1_busy connect issue_slots[2].in_uop.bits.ppred, issue_slots[3].out_uop.ppred connect issue_slots[2].in_uop.bits.prs3, issue_slots[3].out_uop.prs3 connect issue_slots[2].in_uop.bits.prs2, issue_slots[3].out_uop.prs2 connect issue_slots[2].in_uop.bits.prs1, issue_slots[3].out_uop.prs1 connect issue_slots[2].in_uop.bits.pdst, issue_slots[3].out_uop.pdst connect issue_slots[2].in_uop.bits.rxq_idx, issue_slots[3].out_uop.rxq_idx connect issue_slots[2].in_uop.bits.stq_idx, issue_slots[3].out_uop.stq_idx connect issue_slots[2].in_uop.bits.ldq_idx, issue_slots[3].out_uop.ldq_idx connect issue_slots[2].in_uop.bits.rob_idx, issue_slots[3].out_uop.rob_idx connect issue_slots[2].in_uop.bits.fp_ctrl.vec, issue_slots[3].out_uop.fp_ctrl.vec connect issue_slots[2].in_uop.bits.fp_ctrl.wflags, issue_slots[3].out_uop.fp_ctrl.wflags connect issue_slots[2].in_uop.bits.fp_ctrl.sqrt, issue_slots[3].out_uop.fp_ctrl.sqrt connect issue_slots[2].in_uop.bits.fp_ctrl.div, issue_slots[3].out_uop.fp_ctrl.div connect issue_slots[2].in_uop.bits.fp_ctrl.fma, issue_slots[3].out_uop.fp_ctrl.fma connect issue_slots[2].in_uop.bits.fp_ctrl.fastpipe, issue_slots[3].out_uop.fp_ctrl.fastpipe connect issue_slots[2].in_uop.bits.fp_ctrl.toint, issue_slots[3].out_uop.fp_ctrl.toint connect issue_slots[2].in_uop.bits.fp_ctrl.fromint, issue_slots[3].out_uop.fp_ctrl.fromint connect issue_slots[2].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[3].out_uop.fp_ctrl.typeTagOut connect issue_slots[2].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[3].out_uop.fp_ctrl.typeTagIn connect issue_slots[2].in_uop.bits.fp_ctrl.swap23, issue_slots[3].out_uop.fp_ctrl.swap23 connect issue_slots[2].in_uop.bits.fp_ctrl.swap12, issue_slots[3].out_uop.fp_ctrl.swap12 connect issue_slots[2].in_uop.bits.fp_ctrl.ren3, issue_slots[3].out_uop.fp_ctrl.ren3 connect issue_slots[2].in_uop.bits.fp_ctrl.ren2, issue_slots[3].out_uop.fp_ctrl.ren2 connect issue_slots[2].in_uop.bits.fp_ctrl.ren1, issue_slots[3].out_uop.fp_ctrl.ren1 connect issue_slots[2].in_uop.bits.fp_ctrl.wen, issue_slots[3].out_uop.fp_ctrl.wen connect issue_slots[2].in_uop.bits.fp_ctrl.ldst, issue_slots[3].out_uop.fp_ctrl.ldst connect issue_slots[2].in_uop.bits.op2_sel, issue_slots[3].out_uop.op2_sel connect issue_slots[2].in_uop.bits.op1_sel, issue_slots[3].out_uop.op1_sel connect issue_slots[2].in_uop.bits.imm_packed, issue_slots[3].out_uop.imm_packed connect issue_slots[2].in_uop.bits.pimm, issue_slots[3].out_uop.pimm connect issue_slots[2].in_uop.bits.imm_sel, issue_slots[3].out_uop.imm_sel connect issue_slots[2].in_uop.bits.imm_rename, issue_slots[3].out_uop.imm_rename connect issue_slots[2].in_uop.bits.taken, issue_slots[3].out_uop.taken connect issue_slots[2].in_uop.bits.pc_lob, issue_slots[3].out_uop.pc_lob connect issue_slots[2].in_uop.bits.edge_inst, issue_slots[3].out_uop.edge_inst connect issue_slots[2].in_uop.bits.ftq_idx, issue_slots[3].out_uop.ftq_idx connect issue_slots[2].in_uop.bits.is_mov, issue_slots[3].out_uop.is_mov connect issue_slots[2].in_uop.bits.is_rocc, issue_slots[3].out_uop.is_rocc connect issue_slots[2].in_uop.bits.is_sys_pc2epc, issue_slots[3].out_uop.is_sys_pc2epc connect issue_slots[2].in_uop.bits.is_eret, issue_slots[3].out_uop.is_eret connect issue_slots[2].in_uop.bits.is_amo, issue_slots[3].out_uop.is_amo connect issue_slots[2].in_uop.bits.is_sfence, issue_slots[3].out_uop.is_sfence connect issue_slots[2].in_uop.bits.is_fencei, issue_slots[3].out_uop.is_fencei connect issue_slots[2].in_uop.bits.is_fence, issue_slots[3].out_uop.is_fence connect issue_slots[2].in_uop.bits.is_sfb, issue_slots[3].out_uop.is_sfb connect issue_slots[2].in_uop.bits.br_type, issue_slots[3].out_uop.br_type connect issue_slots[2].in_uop.bits.br_tag, issue_slots[3].out_uop.br_tag connect issue_slots[2].in_uop.bits.br_mask, issue_slots[3].out_uop.br_mask connect issue_slots[2].in_uop.bits.dis_col_sel, issue_slots[3].out_uop.dis_col_sel connect issue_slots[2].in_uop.bits.iw_p3_bypass_hint, issue_slots[3].out_uop.iw_p3_bypass_hint connect issue_slots[2].in_uop.bits.iw_p2_bypass_hint, issue_slots[3].out_uop.iw_p2_bypass_hint connect issue_slots[2].in_uop.bits.iw_p1_bypass_hint, issue_slots[3].out_uop.iw_p1_bypass_hint connect issue_slots[2].in_uop.bits.iw_p2_speculative_child, issue_slots[3].out_uop.iw_p2_speculative_child connect issue_slots[2].in_uop.bits.iw_p1_speculative_child, issue_slots[3].out_uop.iw_p1_speculative_child connect issue_slots[2].in_uop.bits.iw_issued_partial_dgen, issue_slots[3].out_uop.iw_issued_partial_dgen connect issue_slots[2].in_uop.bits.iw_issued_partial_agen, issue_slots[3].out_uop.iw_issued_partial_agen connect issue_slots[2].in_uop.bits.iw_issued, issue_slots[3].out_uop.iw_issued connect issue_slots[2].in_uop.bits.fu_code[0], issue_slots[3].out_uop.fu_code[0] connect issue_slots[2].in_uop.bits.fu_code[1], issue_slots[3].out_uop.fu_code[1] connect issue_slots[2].in_uop.bits.fu_code[2], issue_slots[3].out_uop.fu_code[2] connect issue_slots[2].in_uop.bits.fu_code[3], issue_slots[3].out_uop.fu_code[3] connect issue_slots[2].in_uop.bits.fu_code[4], issue_slots[3].out_uop.fu_code[4] connect issue_slots[2].in_uop.bits.fu_code[5], issue_slots[3].out_uop.fu_code[5] connect issue_slots[2].in_uop.bits.fu_code[6], issue_slots[3].out_uop.fu_code[6] connect issue_slots[2].in_uop.bits.fu_code[7], issue_slots[3].out_uop.fu_code[7] connect issue_slots[2].in_uop.bits.fu_code[8], issue_slots[3].out_uop.fu_code[8] connect issue_slots[2].in_uop.bits.fu_code[9], issue_slots[3].out_uop.fu_code[9] connect issue_slots[2].in_uop.bits.iq_type[0], issue_slots[3].out_uop.iq_type[0] connect issue_slots[2].in_uop.bits.iq_type[1], issue_slots[3].out_uop.iq_type[1] connect issue_slots[2].in_uop.bits.iq_type[2], issue_slots[3].out_uop.iq_type[2] connect issue_slots[2].in_uop.bits.iq_type[3], issue_slots[3].out_uop.iq_type[3] connect issue_slots[2].in_uop.bits.debug_pc, issue_slots[3].out_uop.debug_pc connect issue_slots[2].in_uop.bits.is_rvc, issue_slots[3].out_uop.is_rvc connect issue_slots[2].in_uop.bits.debug_inst, issue_slots[3].out_uop.debug_inst connect issue_slots[2].in_uop.bits.inst, issue_slots[3].out_uop.inst node _T_283 = eq(shamts_oh[3], UInt<1>(0h1)) when _T_283 : connect issue_slots[2].in_uop.valid, issue_slots[3].will_be_valid connect issue_slots[2].in_uop.bits.debug_tsrc, issue_slots[3].out_uop.debug_tsrc connect issue_slots[2].in_uop.bits.debug_fsrc, issue_slots[3].out_uop.debug_fsrc connect issue_slots[2].in_uop.bits.bp_xcpt_if, issue_slots[3].out_uop.bp_xcpt_if connect issue_slots[2].in_uop.bits.bp_debug_if, issue_slots[3].out_uop.bp_debug_if connect issue_slots[2].in_uop.bits.xcpt_ma_if, issue_slots[3].out_uop.xcpt_ma_if connect issue_slots[2].in_uop.bits.xcpt_ae_if, issue_slots[3].out_uop.xcpt_ae_if connect issue_slots[2].in_uop.bits.xcpt_pf_if, issue_slots[3].out_uop.xcpt_pf_if connect issue_slots[2].in_uop.bits.fp_typ, issue_slots[3].out_uop.fp_typ connect issue_slots[2].in_uop.bits.fp_rm, issue_slots[3].out_uop.fp_rm connect issue_slots[2].in_uop.bits.fp_val, issue_slots[3].out_uop.fp_val connect issue_slots[2].in_uop.bits.fcn_op, issue_slots[3].out_uop.fcn_op connect issue_slots[2].in_uop.bits.fcn_dw, issue_slots[3].out_uop.fcn_dw connect issue_slots[2].in_uop.bits.frs3_en, issue_slots[3].out_uop.frs3_en connect issue_slots[2].in_uop.bits.lrs2_rtype, issue_slots[3].out_uop.lrs2_rtype connect issue_slots[2].in_uop.bits.lrs1_rtype, issue_slots[3].out_uop.lrs1_rtype connect issue_slots[2].in_uop.bits.dst_rtype, issue_slots[3].out_uop.dst_rtype connect issue_slots[2].in_uop.bits.lrs3, issue_slots[3].out_uop.lrs3 connect issue_slots[2].in_uop.bits.lrs2, issue_slots[3].out_uop.lrs2 connect issue_slots[2].in_uop.bits.lrs1, issue_slots[3].out_uop.lrs1 connect issue_slots[2].in_uop.bits.ldst, issue_slots[3].out_uop.ldst connect issue_slots[2].in_uop.bits.ldst_is_rs1, issue_slots[3].out_uop.ldst_is_rs1 connect issue_slots[2].in_uop.bits.csr_cmd, issue_slots[3].out_uop.csr_cmd connect issue_slots[2].in_uop.bits.flush_on_commit, issue_slots[3].out_uop.flush_on_commit connect issue_slots[2].in_uop.bits.is_unique, issue_slots[3].out_uop.is_unique connect issue_slots[2].in_uop.bits.uses_stq, issue_slots[3].out_uop.uses_stq connect issue_slots[2].in_uop.bits.uses_ldq, issue_slots[3].out_uop.uses_ldq connect issue_slots[2].in_uop.bits.mem_signed, issue_slots[3].out_uop.mem_signed connect issue_slots[2].in_uop.bits.mem_size, issue_slots[3].out_uop.mem_size connect issue_slots[2].in_uop.bits.mem_cmd, issue_slots[3].out_uop.mem_cmd connect issue_slots[2].in_uop.bits.exc_cause, issue_slots[3].out_uop.exc_cause connect issue_slots[2].in_uop.bits.exception, issue_slots[3].out_uop.exception connect issue_slots[2].in_uop.bits.stale_pdst, issue_slots[3].out_uop.stale_pdst connect issue_slots[2].in_uop.bits.ppred_busy, issue_slots[3].out_uop.ppred_busy connect issue_slots[2].in_uop.bits.prs3_busy, issue_slots[3].out_uop.prs3_busy connect issue_slots[2].in_uop.bits.prs2_busy, issue_slots[3].out_uop.prs2_busy connect issue_slots[2].in_uop.bits.prs1_busy, issue_slots[3].out_uop.prs1_busy connect issue_slots[2].in_uop.bits.ppred, issue_slots[3].out_uop.ppred connect issue_slots[2].in_uop.bits.prs3, issue_slots[3].out_uop.prs3 connect issue_slots[2].in_uop.bits.prs2, issue_slots[3].out_uop.prs2 connect issue_slots[2].in_uop.bits.prs1, issue_slots[3].out_uop.prs1 connect issue_slots[2].in_uop.bits.pdst, issue_slots[3].out_uop.pdst connect issue_slots[2].in_uop.bits.rxq_idx, issue_slots[3].out_uop.rxq_idx connect issue_slots[2].in_uop.bits.stq_idx, issue_slots[3].out_uop.stq_idx connect issue_slots[2].in_uop.bits.ldq_idx, issue_slots[3].out_uop.ldq_idx connect issue_slots[2].in_uop.bits.rob_idx, issue_slots[3].out_uop.rob_idx connect issue_slots[2].in_uop.bits.fp_ctrl.vec, issue_slots[3].out_uop.fp_ctrl.vec connect issue_slots[2].in_uop.bits.fp_ctrl.wflags, issue_slots[3].out_uop.fp_ctrl.wflags connect issue_slots[2].in_uop.bits.fp_ctrl.sqrt, issue_slots[3].out_uop.fp_ctrl.sqrt connect issue_slots[2].in_uop.bits.fp_ctrl.div, issue_slots[3].out_uop.fp_ctrl.div connect issue_slots[2].in_uop.bits.fp_ctrl.fma, issue_slots[3].out_uop.fp_ctrl.fma connect issue_slots[2].in_uop.bits.fp_ctrl.fastpipe, issue_slots[3].out_uop.fp_ctrl.fastpipe connect issue_slots[2].in_uop.bits.fp_ctrl.toint, issue_slots[3].out_uop.fp_ctrl.toint connect issue_slots[2].in_uop.bits.fp_ctrl.fromint, issue_slots[3].out_uop.fp_ctrl.fromint connect issue_slots[2].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[3].out_uop.fp_ctrl.typeTagOut connect issue_slots[2].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[3].out_uop.fp_ctrl.typeTagIn connect issue_slots[2].in_uop.bits.fp_ctrl.swap23, issue_slots[3].out_uop.fp_ctrl.swap23 connect issue_slots[2].in_uop.bits.fp_ctrl.swap12, issue_slots[3].out_uop.fp_ctrl.swap12 connect issue_slots[2].in_uop.bits.fp_ctrl.ren3, issue_slots[3].out_uop.fp_ctrl.ren3 connect issue_slots[2].in_uop.bits.fp_ctrl.ren2, issue_slots[3].out_uop.fp_ctrl.ren2 connect issue_slots[2].in_uop.bits.fp_ctrl.ren1, issue_slots[3].out_uop.fp_ctrl.ren1 connect issue_slots[2].in_uop.bits.fp_ctrl.wen, issue_slots[3].out_uop.fp_ctrl.wen connect issue_slots[2].in_uop.bits.fp_ctrl.ldst, issue_slots[3].out_uop.fp_ctrl.ldst connect issue_slots[2].in_uop.bits.op2_sel, issue_slots[3].out_uop.op2_sel connect issue_slots[2].in_uop.bits.op1_sel, issue_slots[3].out_uop.op1_sel connect issue_slots[2].in_uop.bits.imm_packed, issue_slots[3].out_uop.imm_packed connect issue_slots[2].in_uop.bits.pimm, issue_slots[3].out_uop.pimm connect issue_slots[2].in_uop.bits.imm_sel, issue_slots[3].out_uop.imm_sel connect issue_slots[2].in_uop.bits.imm_rename, issue_slots[3].out_uop.imm_rename connect issue_slots[2].in_uop.bits.taken, issue_slots[3].out_uop.taken connect issue_slots[2].in_uop.bits.pc_lob, issue_slots[3].out_uop.pc_lob connect issue_slots[2].in_uop.bits.edge_inst, issue_slots[3].out_uop.edge_inst connect issue_slots[2].in_uop.bits.ftq_idx, issue_slots[3].out_uop.ftq_idx connect issue_slots[2].in_uop.bits.is_mov, issue_slots[3].out_uop.is_mov connect issue_slots[2].in_uop.bits.is_rocc, issue_slots[3].out_uop.is_rocc connect issue_slots[2].in_uop.bits.is_sys_pc2epc, issue_slots[3].out_uop.is_sys_pc2epc connect issue_slots[2].in_uop.bits.is_eret, issue_slots[3].out_uop.is_eret connect issue_slots[2].in_uop.bits.is_amo, issue_slots[3].out_uop.is_amo connect issue_slots[2].in_uop.bits.is_sfence, issue_slots[3].out_uop.is_sfence connect issue_slots[2].in_uop.bits.is_fencei, issue_slots[3].out_uop.is_fencei connect issue_slots[2].in_uop.bits.is_fence, issue_slots[3].out_uop.is_fence connect issue_slots[2].in_uop.bits.is_sfb, issue_slots[3].out_uop.is_sfb connect issue_slots[2].in_uop.bits.br_type, issue_slots[3].out_uop.br_type connect issue_slots[2].in_uop.bits.br_tag, issue_slots[3].out_uop.br_tag connect issue_slots[2].in_uop.bits.br_mask, issue_slots[3].out_uop.br_mask connect issue_slots[2].in_uop.bits.dis_col_sel, issue_slots[3].out_uop.dis_col_sel connect issue_slots[2].in_uop.bits.iw_p3_bypass_hint, issue_slots[3].out_uop.iw_p3_bypass_hint connect issue_slots[2].in_uop.bits.iw_p2_bypass_hint, issue_slots[3].out_uop.iw_p2_bypass_hint connect issue_slots[2].in_uop.bits.iw_p1_bypass_hint, issue_slots[3].out_uop.iw_p1_bypass_hint connect issue_slots[2].in_uop.bits.iw_p2_speculative_child, issue_slots[3].out_uop.iw_p2_speculative_child connect issue_slots[2].in_uop.bits.iw_p1_speculative_child, issue_slots[3].out_uop.iw_p1_speculative_child connect issue_slots[2].in_uop.bits.iw_issued_partial_dgen, issue_slots[3].out_uop.iw_issued_partial_dgen connect issue_slots[2].in_uop.bits.iw_issued_partial_agen, issue_slots[3].out_uop.iw_issued_partial_agen connect issue_slots[2].in_uop.bits.iw_issued, issue_slots[3].out_uop.iw_issued connect issue_slots[2].in_uop.bits.fu_code[0], issue_slots[3].out_uop.fu_code[0] connect issue_slots[2].in_uop.bits.fu_code[1], issue_slots[3].out_uop.fu_code[1] connect issue_slots[2].in_uop.bits.fu_code[2], issue_slots[3].out_uop.fu_code[2] connect issue_slots[2].in_uop.bits.fu_code[3], issue_slots[3].out_uop.fu_code[3] connect issue_slots[2].in_uop.bits.fu_code[4], issue_slots[3].out_uop.fu_code[4] connect issue_slots[2].in_uop.bits.fu_code[5], issue_slots[3].out_uop.fu_code[5] connect issue_slots[2].in_uop.bits.fu_code[6], issue_slots[3].out_uop.fu_code[6] connect issue_slots[2].in_uop.bits.fu_code[7], issue_slots[3].out_uop.fu_code[7] connect issue_slots[2].in_uop.bits.fu_code[8], issue_slots[3].out_uop.fu_code[8] connect issue_slots[2].in_uop.bits.fu_code[9], issue_slots[3].out_uop.fu_code[9] connect issue_slots[2].in_uop.bits.iq_type[0], issue_slots[3].out_uop.iq_type[0] connect issue_slots[2].in_uop.bits.iq_type[1], issue_slots[3].out_uop.iq_type[1] connect issue_slots[2].in_uop.bits.iq_type[2], issue_slots[3].out_uop.iq_type[2] connect issue_slots[2].in_uop.bits.iq_type[3], issue_slots[3].out_uop.iq_type[3] connect issue_slots[2].in_uop.bits.debug_pc, issue_slots[3].out_uop.debug_pc connect issue_slots[2].in_uop.bits.is_rvc, issue_slots[3].out_uop.is_rvc connect issue_slots[2].in_uop.bits.debug_inst, issue_slots[3].out_uop.debug_inst connect issue_slots[2].in_uop.bits.inst, issue_slots[3].out_uop.inst node _T_284 = eq(shamts_oh[4], UInt<2>(0h2)) when _T_284 : connect issue_slots[2].in_uop.valid, issue_slots[4].will_be_valid connect issue_slots[2].in_uop.bits.debug_tsrc, issue_slots[4].out_uop.debug_tsrc connect issue_slots[2].in_uop.bits.debug_fsrc, issue_slots[4].out_uop.debug_fsrc connect issue_slots[2].in_uop.bits.bp_xcpt_if, issue_slots[4].out_uop.bp_xcpt_if connect issue_slots[2].in_uop.bits.bp_debug_if, issue_slots[4].out_uop.bp_debug_if connect issue_slots[2].in_uop.bits.xcpt_ma_if, issue_slots[4].out_uop.xcpt_ma_if connect issue_slots[2].in_uop.bits.xcpt_ae_if, issue_slots[4].out_uop.xcpt_ae_if connect issue_slots[2].in_uop.bits.xcpt_pf_if, issue_slots[4].out_uop.xcpt_pf_if connect issue_slots[2].in_uop.bits.fp_typ, issue_slots[4].out_uop.fp_typ connect issue_slots[2].in_uop.bits.fp_rm, issue_slots[4].out_uop.fp_rm connect issue_slots[2].in_uop.bits.fp_val, issue_slots[4].out_uop.fp_val connect issue_slots[2].in_uop.bits.fcn_op, issue_slots[4].out_uop.fcn_op connect issue_slots[2].in_uop.bits.fcn_dw, issue_slots[4].out_uop.fcn_dw connect issue_slots[2].in_uop.bits.frs3_en, issue_slots[4].out_uop.frs3_en connect issue_slots[2].in_uop.bits.lrs2_rtype, issue_slots[4].out_uop.lrs2_rtype connect issue_slots[2].in_uop.bits.lrs1_rtype, issue_slots[4].out_uop.lrs1_rtype connect issue_slots[2].in_uop.bits.dst_rtype, issue_slots[4].out_uop.dst_rtype connect issue_slots[2].in_uop.bits.lrs3, issue_slots[4].out_uop.lrs3 connect issue_slots[2].in_uop.bits.lrs2, issue_slots[4].out_uop.lrs2 connect issue_slots[2].in_uop.bits.lrs1, issue_slots[4].out_uop.lrs1 connect issue_slots[2].in_uop.bits.ldst, issue_slots[4].out_uop.ldst connect issue_slots[2].in_uop.bits.ldst_is_rs1, issue_slots[4].out_uop.ldst_is_rs1 connect issue_slots[2].in_uop.bits.csr_cmd, issue_slots[4].out_uop.csr_cmd connect issue_slots[2].in_uop.bits.flush_on_commit, issue_slots[4].out_uop.flush_on_commit connect issue_slots[2].in_uop.bits.is_unique, issue_slots[4].out_uop.is_unique connect issue_slots[2].in_uop.bits.uses_stq, issue_slots[4].out_uop.uses_stq connect issue_slots[2].in_uop.bits.uses_ldq, issue_slots[4].out_uop.uses_ldq connect issue_slots[2].in_uop.bits.mem_signed, issue_slots[4].out_uop.mem_signed connect issue_slots[2].in_uop.bits.mem_size, issue_slots[4].out_uop.mem_size connect issue_slots[2].in_uop.bits.mem_cmd, issue_slots[4].out_uop.mem_cmd connect issue_slots[2].in_uop.bits.exc_cause, issue_slots[4].out_uop.exc_cause connect issue_slots[2].in_uop.bits.exception, issue_slots[4].out_uop.exception connect issue_slots[2].in_uop.bits.stale_pdst, issue_slots[4].out_uop.stale_pdst connect issue_slots[2].in_uop.bits.ppred_busy, issue_slots[4].out_uop.ppred_busy connect issue_slots[2].in_uop.bits.prs3_busy, issue_slots[4].out_uop.prs3_busy connect issue_slots[2].in_uop.bits.prs2_busy, issue_slots[4].out_uop.prs2_busy connect issue_slots[2].in_uop.bits.prs1_busy, issue_slots[4].out_uop.prs1_busy connect issue_slots[2].in_uop.bits.ppred, issue_slots[4].out_uop.ppred connect issue_slots[2].in_uop.bits.prs3, issue_slots[4].out_uop.prs3 connect issue_slots[2].in_uop.bits.prs2, issue_slots[4].out_uop.prs2 connect issue_slots[2].in_uop.bits.prs1, issue_slots[4].out_uop.prs1 connect issue_slots[2].in_uop.bits.pdst, issue_slots[4].out_uop.pdst connect issue_slots[2].in_uop.bits.rxq_idx, issue_slots[4].out_uop.rxq_idx connect issue_slots[2].in_uop.bits.stq_idx, issue_slots[4].out_uop.stq_idx connect issue_slots[2].in_uop.bits.ldq_idx, issue_slots[4].out_uop.ldq_idx connect issue_slots[2].in_uop.bits.rob_idx, issue_slots[4].out_uop.rob_idx connect issue_slots[2].in_uop.bits.fp_ctrl.vec, issue_slots[4].out_uop.fp_ctrl.vec connect issue_slots[2].in_uop.bits.fp_ctrl.wflags, issue_slots[4].out_uop.fp_ctrl.wflags connect issue_slots[2].in_uop.bits.fp_ctrl.sqrt, issue_slots[4].out_uop.fp_ctrl.sqrt connect issue_slots[2].in_uop.bits.fp_ctrl.div, issue_slots[4].out_uop.fp_ctrl.div connect issue_slots[2].in_uop.bits.fp_ctrl.fma, issue_slots[4].out_uop.fp_ctrl.fma connect issue_slots[2].in_uop.bits.fp_ctrl.fastpipe, issue_slots[4].out_uop.fp_ctrl.fastpipe connect issue_slots[2].in_uop.bits.fp_ctrl.toint, issue_slots[4].out_uop.fp_ctrl.toint connect issue_slots[2].in_uop.bits.fp_ctrl.fromint, issue_slots[4].out_uop.fp_ctrl.fromint connect issue_slots[2].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[4].out_uop.fp_ctrl.typeTagOut connect issue_slots[2].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[4].out_uop.fp_ctrl.typeTagIn connect issue_slots[2].in_uop.bits.fp_ctrl.swap23, issue_slots[4].out_uop.fp_ctrl.swap23 connect issue_slots[2].in_uop.bits.fp_ctrl.swap12, issue_slots[4].out_uop.fp_ctrl.swap12 connect issue_slots[2].in_uop.bits.fp_ctrl.ren3, issue_slots[4].out_uop.fp_ctrl.ren3 connect issue_slots[2].in_uop.bits.fp_ctrl.ren2, issue_slots[4].out_uop.fp_ctrl.ren2 connect issue_slots[2].in_uop.bits.fp_ctrl.ren1, issue_slots[4].out_uop.fp_ctrl.ren1 connect issue_slots[2].in_uop.bits.fp_ctrl.wen, issue_slots[4].out_uop.fp_ctrl.wen connect issue_slots[2].in_uop.bits.fp_ctrl.ldst, issue_slots[4].out_uop.fp_ctrl.ldst connect issue_slots[2].in_uop.bits.op2_sel, issue_slots[4].out_uop.op2_sel connect issue_slots[2].in_uop.bits.op1_sel, issue_slots[4].out_uop.op1_sel connect issue_slots[2].in_uop.bits.imm_packed, issue_slots[4].out_uop.imm_packed connect issue_slots[2].in_uop.bits.pimm, issue_slots[4].out_uop.pimm connect issue_slots[2].in_uop.bits.imm_sel, issue_slots[4].out_uop.imm_sel connect issue_slots[2].in_uop.bits.imm_rename, issue_slots[4].out_uop.imm_rename connect issue_slots[2].in_uop.bits.taken, issue_slots[4].out_uop.taken connect issue_slots[2].in_uop.bits.pc_lob, issue_slots[4].out_uop.pc_lob connect issue_slots[2].in_uop.bits.edge_inst, issue_slots[4].out_uop.edge_inst connect issue_slots[2].in_uop.bits.ftq_idx, issue_slots[4].out_uop.ftq_idx connect issue_slots[2].in_uop.bits.is_mov, issue_slots[4].out_uop.is_mov connect issue_slots[2].in_uop.bits.is_rocc, issue_slots[4].out_uop.is_rocc connect issue_slots[2].in_uop.bits.is_sys_pc2epc, issue_slots[4].out_uop.is_sys_pc2epc connect issue_slots[2].in_uop.bits.is_eret, issue_slots[4].out_uop.is_eret connect issue_slots[2].in_uop.bits.is_amo, issue_slots[4].out_uop.is_amo connect issue_slots[2].in_uop.bits.is_sfence, issue_slots[4].out_uop.is_sfence connect issue_slots[2].in_uop.bits.is_fencei, issue_slots[4].out_uop.is_fencei connect issue_slots[2].in_uop.bits.is_fence, issue_slots[4].out_uop.is_fence connect issue_slots[2].in_uop.bits.is_sfb, issue_slots[4].out_uop.is_sfb connect issue_slots[2].in_uop.bits.br_type, issue_slots[4].out_uop.br_type connect issue_slots[2].in_uop.bits.br_tag, issue_slots[4].out_uop.br_tag connect issue_slots[2].in_uop.bits.br_mask, issue_slots[4].out_uop.br_mask connect issue_slots[2].in_uop.bits.dis_col_sel, issue_slots[4].out_uop.dis_col_sel connect issue_slots[2].in_uop.bits.iw_p3_bypass_hint, issue_slots[4].out_uop.iw_p3_bypass_hint connect issue_slots[2].in_uop.bits.iw_p2_bypass_hint, issue_slots[4].out_uop.iw_p2_bypass_hint connect issue_slots[2].in_uop.bits.iw_p1_bypass_hint, issue_slots[4].out_uop.iw_p1_bypass_hint connect issue_slots[2].in_uop.bits.iw_p2_speculative_child, issue_slots[4].out_uop.iw_p2_speculative_child connect issue_slots[2].in_uop.bits.iw_p1_speculative_child, issue_slots[4].out_uop.iw_p1_speculative_child connect issue_slots[2].in_uop.bits.iw_issued_partial_dgen, issue_slots[4].out_uop.iw_issued_partial_dgen connect issue_slots[2].in_uop.bits.iw_issued_partial_agen, issue_slots[4].out_uop.iw_issued_partial_agen connect issue_slots[2].in_uop.bits.iw_issued, issue_slots[4].out_uop.iw_issued connect issue_slots[2].in_uop.bits.fu_code[0], issue_slots[4].out_uop.fu_code[0] connect issue_slots[2].in_uop.bits.fu_code[1], issue_slots[4].out_uop.fu_code[1] connect issue_slots[2].in_uop.bits.fu_code[2], issue_slots[4].out_uop.fu_code[2] connect issue_slots[2].in_uop.bits.fu_code[3], issue_slots[4].out_uop.fu_code[3] connect issue_slots[2].in_uop.bits.fu_code[4], issue_slots[4].out_uop.fu_code[4] connect issue_slots[2].in_uop.bits.fu_code[5], issue_slots[4].out_uop.fu_code[5] connect issue_slots[2].in_uop.bits.fu_code[6], issue_slots[4].out_uop.fu_code[6] connect issue_slots[2].in_uop.bits.fu_code[7], issue_slots[4].out_uop.fu_code[7] connect issue_slots[2].in_uop.bits.fu_code[8], issue_slots[4].out_uop.fu_code[8] connect issue_slots[2].in_uop.bits.fu_code[9], issue_slots[4].out_uop.fu_code[9] connect issue_slots[2].in_uop.bits.iq_type[0], issue_slots[4].out_uop.iq_type[0] connect issue_slots[2].in_uop.bits.iq_type[1], issue_slots[4].out_uop.iq_type[1] connect issue_slots[2].in_uop.bits.iq_type[2], issue_slots[4].out_uop.iq_type[2] connect issue_slots[2].in_uop.bits.iq_type[3], issue_slots[4].out_uop.iq_type[3] connect issue_slots[2].in_uop.bits.debug_pc, issue_slots[4].out_uop.debug_pc connect issue_slots[2].in_uop.bits.is_rvc, issue_slots[4].out_uop.is_rvc connect issue_slots[2].in_uop.bits.debug_inst, issue_slots[4].out_uop.debug_inst connect issue_slots[2].in_uop.bits.inst, issue_slots[4].out_uop.inst node _T_285 = eq(shamts_oh[5], UInt<3>(0h4)) when _T_285 : connect issue_slots[2].in_uop.valid, issue_slots[5].will_be_valid connect issue_slots[2].in_uop.bits.debug_tsrc, issue_slots[5].out_uop.debug_tsrc connect issue_slots[2].in_uop.bits.debug_fsrc, issue_slots[5].out_uop.debug_fsrc connect issue_slots[2].in_uop.bits.bp_xcpt_if, issue_slots[5].out_uop.bp_xcpt_if connect issue_slots[2].in_uop.bits.bp_debug_if, issue_slots[5].out_uop.bp_debug_if connect issue_slots[2].in_uop.bits.xcpt_ma_if, issue_slots[5].out_uop.xcpt_ma_if connect issue_slots[2].in_uop.bits.xcpt_ae_if, issue_slots[5].out_uop.xcpt_ae_if connect issue_slots[2].in_uop.bits.xcpt_pf_if, issue_slots[5].out_uop.xcpt_pf_if connect issue_slots[2].in_uop.bits.fp_typ, issue_slots[5].out_uop.fp_typ connect issue_slots[2].in_uop.bits.fp_rm, issue_slots[5].out_uop.fp_rm connect issue_slots[2].in_uop.bits.fp_val, issue_slots[5].out_uop.fp_val connect issue_slots[2].in_uop.bits.fcn_op, issue_slots[5].out_uop.fcn_op connect issue_slots[2].in_uop.bits.fcn_dw, issue_slots[5].out_uop.fcn_dw connect issue_slots[2].in_uop.bits.frs3_en, issue_slots[5].out_uop.frs3_en connect issue_slots[2].in_uop.bits.lrs2_rtype, issue_slots[5].out_uop.lrs2_rtype connect issue_slots[2].in_uop.bits.lrs1_rtype, issue_slots[5].out_uop.lrs1_rtype connect issue_slots[2].in_uop.bits.dst_rtype, issue_slots[5].out_uop.dst_rtype connect issue_slots[2].in_uop.bits.lrs3, issue_slots[5].out_uop.lrs3 connect issue_slots[2].in_uop.bits.lrs2, issue_slots[5].out_uop.lrs2 connect issue_slots[2].in_uop.bits.lrs1, issue_slots[5].out_uop.lrs1 connect issue_slots[2].in_uop.bits.ldst, issue_slots[5].out_uop.ldst connect issue_slots[2].in_uop.bits.ldst_is_rs1, issue_slots[5].out_uop.ldst_is_rs1 connect issue_slots[2].in_uop.bits.csr_cmd, issue_slots[5].out_uop.csr_cmd connect issue_slots[2].in_uop.bits.flush_on_commit, issue_slots[5].out_uop.flush_on_commit connect issue_slots[2].in_uop.bits.is_unique, issue_slots[5].out_uop.is_unique connect issue_slots[2].in_uop.bits.uses_stq, issue_slots[5].out_uop.uses_stq connect issue_slots[2].in_uop.bits.uses_ldq, issue_slots[5].out_uop.uses_ldq connect issue_slots[2].in_uop.bits.mem_signed, issue_slots[5].out_uop.mem_signed connect issue_slots[2].in_uop.bits.mem_size, issue_slots[5].out_uop.mem_size connect issue_slots[2].in_uop.bits.mem_cmd, issue_slots[5].out_uop.mem_cmd connect issue_slots[2].in_uop.bits.exc_cause, issue_slots[5].out_uop.exc_cause connect issue_slots[2].in_uop.bits.exception, issue_slots[5].out_uop.exception connect issue_slots[2].in_uop.bits.stale_pdst, issue_slots[5].out_uop.stale_pdst connect issue_slots[2].in_uop.bits.ppred_busy, issue_slots[5].out_uop.ppred_busy connect issue_slots[2].in_uop.bits.prs3_busy, issue_slots[5].out_uop.prs3_busy connect issue_slots[2].in_uop.bits.prs2_busy, issue_slots[5].out_uop.prs2_busy connect issue_slots[2].in_uop.bits.prs1_busy, issue_slots[5].out_uop.prs1_busy connect issue_slots[2].in_uop.bits.ppred, issue_slots[5].out_uop.ppred connect issue_slots[2].in_uop.bits.prs3, issue_slots[5].out_uop.prs3 connect issue_slots[2].in_uop.bits.prs2, issue_slots[5].out_uop.prs2 connect issue_slots[2].in_uop.bits.prs1, issue_slots[5].out_uop.prs1 connect issue_slots[2].in_uop.bits.pdst, issue_slots[5].out_uop.pdst connect issue_slots[2].in_uop.bits.rxq_idx, issue_slots[5].out_uop.rxq_idx connect issue_slots[2].in_uop.bits.stq_idx, issue_slots[5].out_uop.stq_idx connect issue_slots[2].in_uop.bits.ldq_idx, issue_slots[5].out_uop.ldq_idx connect issue_slots[2].in_uop.bits.rob_idx, issue_slots[5].out_uop.rob_idx connect issue_slots[2].in_uop.bits.fp_ctrl.vec, issue_slots[5].out_uop.fp_ctrl.vec connect issue_slots[2].in_uop.bits.fp_ctrl.wflags, issue_slots[5].out_uop.fp_ctrl.wflags connect issue_slots[2].in_uop.bits.fp_ctrl.sqrt, issue_slots[5].out_uop.fp_ctrl.sqrt connect issue_slots[2].in_uop.bits.fp_ctrl.div, issue_slots[5].out_uop.fp_ctrl.div connect issue_slots[2].in_uop.bits.fp_ctrl.fma, issue_slots[5].out_uop.fp_ctrl.fma connect issue_slots[2].in_uop.bits.fp_ctrl.fastpipe, issue_slots[5].out_uop.fp_ctrl.fastpipe connect issue_slots[2].in_uop.bits.fp_ctrl.toint, issue_slots[5].out_uop.fp_ctrl.toint connect issue_slots[2].in_uop.bits.fp_ctrl.fromint, issue_slots[5].out_uop.fp_ctrl.fromint connect issue_slots[2].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[5].out_uop.fp_ctrl.typeTagOut connect issue_slots[2].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[5].out_uop.fp_ctrl.typeTagIn connect issue_slots[2].in_uop.bits.fp_ctrl.swap23, issue_slots[5].out_uop.fp_ctrl.swap23 connect issue_slots[2].in_uop.bits.fp_ctrl.swap12, issue_slots[5].out_uop.fp_ctrl.swap12 connect issue_slots[2].in_uop.bits.fp_ctrl.ren3, issue_slots[5].out_uop.fp_ctrl.ren3 connect issue_slots[2].in_uop.bits.fp_ctrl.ren2, issue_slots[5].out_uop.fp_ctrl.ren2 connect issue_slots[2].in_uop.bits.fp_ctrl.ren1, issue_slots[5].out_uop.fp_ctrl.ren1 connect issue_slots[2].in_uop.bits.fp_ctrl.wen, issue_slots[5].out_uop.fp_ctrl.wen connect issue_slots[2].in_uop.bits.fp_ctrl.ldst, issue_slots[5].out_uop.fp_ctrl.ldst connect issue_slots[2].in_uop.bits.op2_sel, issue_slots[5].out_uop.op2_sel connect issue_slots[2].in_uop.bits.op1_sel, issue_slots[5].out_uop.op1_sel connect issue_slots[2].in_uop.bits.imm_packed, issue_slots[5].out_uop.imm_packed connect issue_slots[2].in_uop.bits.pimm, issue_slots[5].out_uop.pimm connect issue_slots[2].in_uop.bits.imm_sel, issue_slots[5].out_uop.imm_sel connect issue_slots[2].in_uop.bits.imm_rename, issue_slots[5].out_uop.imm_rename connect issue_slots[2].in_uop.bits.taken, issue_slots[5].out_uop.taken connect issue_slots[2].in_uop.bits.pc_lob, issue_slots[5].out_uop.pc_lob connect issue_slots[2].in_uop.bits.edge_inst, issue_slots[5].out_uop.edge_inst connect issue_slots[2].in_uop.bits.ftq_idx, issue_slots[5].out_uop.ftq_idx connect issue_slots[2].in_uop.bits.is_mov, issue_slots[5].out_uop.is_mov connect issue_slots[2].in_uop.bits.is_rocc, issue_slots[5].out_uop.is_rocc connect issue_slots[2].in_uop.bits.is_sys_pc2epc, issue_slots[5].out_uop.is_sys_pc2epc connect issue_slots[2].in_uop.bits.is_eret, issue_slots[5].out_uop.is_eret connect issue_slots[2].in_uop.bits.is_amo, issue_slots[5].out_uop.is_amo connect issue_slots[2].in_uop.bits.is_sfence, issue_slots[5].out_uop.is_sfence connect issue_slots[2].in_uop.bits.is_fencei, issue_slots[5].out_uop.is_fencei connect issue_slots[2].in_uop.bits.is_fence, issue_slots[5].out_uop.is_fence connect issue_slots[2].in_uop.bits.is_sfb, issue_slots[5].out_uop.is_sfb connect issue_slots[2].in_uop.bits.br_type, issue_slots[5].out_uop.br_type connect issue_slots[2].in_uop.bits.br_tag, issue_slots[5].out_uop.br_tag connect issue_slots[2].in_uop.bits.br_mask, issue_slots[5].out_uop.br_mask connect issue_slots[2].in_uop.bits.dis_col_sel, issue_slots[5].out_uop.dis_col_sel connect issue_slots[2].in_uop.bits.iw_p3_bypass_hint, issue_slots[5].out_uop.iw_p3_bypass_hint connect issue_slots[2].in_uop.bits.iw_p2_bypass_hint, issue_slots[5].out_uop.iw_p2_bypass_hint connect issue_slots[2].in_uop.bits.iw_p1_bypass_hint, issue_slots[5].out_uop.iw_p1_bypass_hint connect issue_slots[2].in_uop.bits.iw_p2_speculative_child, issue_slots[5].out_uop.iw_p2_speculative_child connect issue_slots[2].in_uop.bits.iw_p1_speculative_child, issue_slots[5].out_uop.iw_p1_speculative_child connect issue_slots[2].in_uop.bits.iw_issued_partial_dgen, issue_slots[5].out_uop.iw_issued_partial_dgen connect issue_slots[2].in_uop.bits.iw_issued_partial_agen, issue_slots[5].out_uop.iw_issued_partial_agen connect issue_slots[2].in_uop.bits.iw_issued, issue_slots[5].out_uop.iw_issued connect issue_slots[2].in_uop.bits.fu_code[0], issue_slots[5].out_uop.fu_code[0] connect issue_slots[2].in_uop.bits.fu_code[1], issue_slots[5].out_uop.fu_code[1] connect issue_slots[2].in_uop.bits.fu_code[2], issue_slots[5].out_uop.fu_code[2] connect issue_slots[2].in_uop.bits.fu_code[3], issue_slots[5].out_uop.fu_code[3] connect issue_slots[2].in_uop.bits.fu_code[4], issue_slots[5].out_uop.fu_code[4] connect issue_slots[2].in_uop.bits.fu_code[5], issue_slots[5].out_uop.fu_code[5] connect issue_slots[2].in_uop.bits.fu_code[6], issue_slots[5].out_uop.fu_code[6] connect issue_slots[2].in_uop.bits.fu_code[7], issue_slots[5].out_uop.fu_code[7] connect issue_slots[2].in_uop.bits.fu_code[8], issue_slots[5].out_uop.fu_code[8] connect issue_slots[2].in_uop.bits.fu_code[9], issue_slots[5].out_uop.fu_code[9] connect issue_slots[2].in_uop.bits.iq_type[0], issue_slots[5].out_uop.iq_type[0] connect issue_slots[2].in_uop.bits.iq_type[1], issue_slots[5].out_uop.iq_type[1] connect issue_slots[2].in_uop.bits.iq_type[2], issue_slots[5].out_uop.iq_type[2] connect issue_slots[2].in_uop.bits.iq_type[3], issue_slots[5].out_uop.iq_type[3] connect issue_slots[2].in_uop.bits.debug_pc, issue_slots[5].out_uop.debug_pc connect issue_slots[2].in_uop.bits.is_rvc, issue_slots[5].out_uop.is_rvc connect issue_slots[2].in_uop.bits.debug_inst, issue_slots[5].out_uop.debug_inst connect issue_slots[2].in_uop.bits.inst, issue_slots[5].out_uop.inst node _issue_slots_2_clear_T = neq(shamts_oh[2], UInt<1>(0h0)) connect issue_slots[2].clear, _issue_slots_2_clear_T connect issue_slots[3].in_uop.valid, UInt<1>(0h0) connect issue_slots[3].in_uop.bits.debug_tsrc, issue_slots[4].out_uop.debug_tsrc connect issue_slots[3].in_uop.bits.debug_fsrc, issue_slots[4].out_uop.debug_fsrc connect issue_slots[3].in_uop.bits.bp_xcpt_if, issue_slots[4].out_uop.bp_xcpt_if connect issue_slots[3].in_uop.bits.bp_debug_if, issue_slots[4].out_uop.bp_debug_if connect issue_slots[3].in_uop.bits.xcpt_ma_if, issue_slots[4].out_uop.xcpt_ma_if connect issue_slots[3].in_uop.bits.xcpt_ae_if, issue_slots[4].out_uop.xcpt_ae_if connect issue_slots[3].in_uop.bits.xcpt_pf_if, issue_slots[4].out_uop.xcpt_pf_if connect issue_slots[3].in_uop.bits.fp_typ, issue_slots[4].out_uop.fp_typ connect issue_slots[3].in_uop.bits.fp_rm, issue_slots[4].out_uop.fp_rm connect issue_slots[3].in_uop.bits.fp_val, issue_slots[4].out_uop.fp_val connect issue_slots[3].in_uop.bits.fcn_op, issue_slots[4].out_uop.fcn_op connect issue_slots[3].in_uop.bits.fcn_dw, issue_slots[4].out_uop.fcn_dw connect issue_slots[3].in_uop.bits.frs3_en, issue_slots[4].out_uop.frs3_en connect issue_slots[3].in_uop.bits.lrs2_rtype, issue_slots[4].out_uop.lrs2_rtype connect issue_slots[3].in_uop.bits.lrs1_rtype, issue_slots[4].out_uop.lrs1_rtype connect issue_slots[3].in_uop.bits.dst_rtype, issue_slots[4].out_uop.dst_rtype connect issue_slots[3].in_uop.bits.lrs3, issue_slots[4].out_uop.lrs3 connect issue_slots[3].in_uop.bits.lrs2, issue_slots[4].out_uop.lrs2 connect issue_slots[3].in_uop.bits.lrs1, issue_slots[4].out_uop.lrs1 connect issue_slots[3].in_uop.bits.ldst, issue_slots[4].out_uop.ldst connect issue_slots[3].in_uop.bits.ldst_is_rs1, issue_slots[4].out_uop.ldst_is_rs1 connect issue_slots[3].in_uop.bits.csr_cmd, issue_slots[4].out_uop.csr_cmd connect issue_slots[3].in_uop.bits.flush_on_commit, issue_slots[4].out_uop.flush_on_commit connect issue_slots[3].in_uop.bits.is_unique, issue_slots[4].out_uop.is_unique connect issue_slots[3].in_uop.bits.uses_stq, issue_slots[4].out_uop.uses_stq connect issue_slots[3].in_uop.bits.uses_ldq, issue_slots[4].out_uop.uses_ldq connect issue_slots[3].in_uop.bits.mem_signed, issue_slots[4].out_uop.mem_signed connect issue_slots[3].in_uop.bits.mem_size, issue_slots[4].out_uop.mem_size connect issue_slots[3].in_uop.bits.mem_cmd, issue_slots[4].out_uop.mem_cmd connect issue_slots[3].in_uop.bits.exc_cause, issue_slots[4].out_uop.exc_cause connect issue_slots[3].in_uop.bits.exception, issue_slots[4].out_uop.exception connect issue_slots[3].in_uop.bits.stale_pdst, issue_slots[4].out_uop.stale_pdst connect issue_slots[3].in_uop.bits.ppred_busy, issue_slots[4].out_uop.ppred_busy connect issue_slots[3].in_uop.bits.prs3_busy, issue_slots[4].out_uop.prs3_busy connect issue_slots[3].in_uop.bits.prs2_busy, issue_slots[4].out_uop.prs2_busy connect issue_slots[3].in_uop.bits.prs1_busy, issue_slots[4].out_uop.prs1_busy connect issue_slots[3].in_uop.bits.ppred, issue_slots[4].out_uop.ppred connect issue_slots[3].in_uop.bits.prs3, issue_slots[4].out_uop.prs3 connect issue_slots[3].in_uop.bits.prs2, issue_slots[4].out_uop.prs2 connect issue_slots[3].in_uop.bits.prs1, issue_slots[4].out_uop.prs1 connect issue_slots[3].in_uop.bits.pdst, issue_slots[4].out_uop.pdst connect issue_slots[3].in_uop.bits.rxq_idx, issue_slots[4].out_uop.rxq_idx connect issue_slots[3].in_uop.bits.stq_idx, issue_slots[4].out_uop.stq_idx connect issue_slots[3].in_uop.bits.ldq_idx, issue_slots[4].out_uop.ldq_idx connect issue_slots[3].in_uop.bits.rob_idx, issue_slots[4].out_uop.rob_idx connect issue_slots[3].in_uop.bits.fp_ctrl.vec, issue_slots[4].out_uop.fp_ctrl.vec connect issue_slots[3].in_uop.bits.fp_ctrl.wflags, issue_slots[4].out_uop.fp_ctrl.wflags connect issue_slots[3].in_uop.bits.fp_ctrl.sqrt, issue_slots[4].out_uop.fp_ctrl.sqrt connect issue_slots[3].in_uop.bits.fp_ctrl.div, issue_slots[4].out_uop.fp_ctrl.div connect issue_slots[3].in_uop.bits.fp_ctrl.fma, issue_slots[4].out_uop.fp_ctrl.fma connect issue_slots[3].in_uop.bits.fp_ctrl.fastpipe, issue_slots[4].out_uop.fp_ctrl.fastpipe connect issue_slots[3].in_uop.bits.fp_ctrl.toint, issue_slots[4].out_uop.fp_ctrl.toint connect issue_slots[3].in_uop.bits.fp_ctrl.fromint, issue_slots[4].out_uop.fp_ctrl.fromint connect issue_slots[3].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[4].out_uop.fp_ctrl.typeTagOut connect issue_slots[3].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[4].out_uop.fp_ctrl.typeTagIn connect issue_slots[3].in_uop.bits.fp_ctrl.swap23, issue_slots[4].out_uop.fp_ctrl.swap23 connect issue_slots[3].in_uop.bits.fp_ctrl.swap12, issue_slots[4].out_uop.fp_ctrl.swap12 connect issue_slots[3].in_uop.bits.fp_ctrl.ren3, issue_slots[4].out_uop.fp_ctrl.ren3 connect issue_slots[3].in_uop.bits.fp_ctrl.ren2, issue_slots[4].out_uop.fp_ctrl.ren2 connect issue_slots[3].in_uop.bits.fp_ctrl.ren1, issue_slots[4].out_uop.fp_ctrl.ren1 connect issue_slots[3].in_uop.bits.fp_ctrl.wen, issue_slots[4].out_uop.fp_ctrl.wen connect issue_slots[3].in_uop.bits.fp_ctrl.ldst, issue_slots[4].out_uop.fp_ctrl.ldst connect issue_slots[3].in_uop.bits.op2_sel, issue_slots[4].out_uop.op2_sel connect issue_slots[3].in_uop.bits.op1_sel, issue_slots[4].out_uop.op1_sel connect issue_slots[3].in_uop.bits.imm_packed, issue_slots[4].out_uop.imm_packed connect issue_slots[3].in_uop.bits.pimm, issue_slots[4].out_uop.pimm connect issue_slots[3].in_uop.bits.imm_sel, issue_slots[4].out_uop.imm_sel connect issue_slots[3].in_uop.bits.imm_rename, issue_slots[4].out_uop.imm_rename connect issue_slots[3].in_uop.bits.taken, issue_slots[4].out_uop.taken connect issue_slots[3].in_uop.bits.pc_lob, issue_slots[4].out_uop.pc_lob connect issue_slots[3].in_uop.bits.edge_inst, issue_slots[4].out_uop.edge_inst connect issue_slots[3].in_uop.bits.ftq_idx, issue_slots[4].out_uop.ftq_idx connect issue_slots[3].in_uop.bits.is_mov, issue_slots[4].out_uop.is_mov connect issue_slots[3].in_uop.bits.is_rocc, issue_slots[4].out_uop.is_rocc connect issue_slots[3].in_uop.bits.is_sys_pc2epc, issue_slots[4].out_uop.is_sys_pc2epc connect issue_slots[3].in_uop.bits.is_eret, issue_slots[4].out_uop.is_eret connect issue_slots[3].in_uop.bits.is_amo, issue_slots[4].out_uop.is_amo connect issue_slots[3].in_uop.bits.is_sfence, issue_slots[4].out_uop.is_sfence connect issue_slots[3].in_uop.bits.is_fencei, issue_slots[4].out_uop.is_fencei connect issue_slots[3].in_uop.bits.is_fence, issue_slots[4].out_uop.is_fence connect issue_slots[3].in_uop.bits.is_sfb, issue_slots[4].out_uop.is_sfb connect issue_slots[3].in_uop.bits.br_type, issue_slots[4].out_uop.br_type connect issue_slots[3].in_uop.bits.br_tag, issue_slots[4].out_uop.br_tag connect issue_slots[3].in_uop.bits.br_mask, issue_slots[4].out_uop.br_mask connect issue_slots[3].in_uop.bits.dis_col_sel, issue_slots[4].out_uop.dis_col_sel connect issue_slots[3].in_uop.bits.iw_p3_bypass_hint, issue_slots[4].out_uop.iw_p3_bypass_hint connect issue_slots[3].in_uop.bits.iw_p2_bypass_hint, issue_slots[4].out_uop.iw_p2_bypass_hint connect issue_slots[3].in_uop.bits.iw_p1_bypass_hint, issue_slots[4].out_uop.iw_p1_bypass_hint connect issue_slots[3].in_uop.bits.iw_p2_speculative_child, issue_slots[4].out_uop.iw_p2_speculative_child connect issue_slots[3].in_uop.bits.iw_p1_speculative_child, issue_slots[4].out_uop.iw_p1_speculative_child connect issue_slots[3].in_uop.bits.iw_issued_partial_dgen, issue_slots[4].out_uop.iw_issued_partial_dgen connect issue_slots[3].in_uop.bits.iw_issued_partial_agen, issue_slots[4].out_uop.iw_issued_partial_agen connect issue_slots[3].in_uop.bits.iw_issued, issue_slots[4].out_uop.iw_issued connect issue_slots[3].in_uop.bits.fu_code[0], issue_slots[4].out_uop.fu_code[0] connect issue_slots[3].in_uop.bits.fu_code[1], issue_slots[4].out_uop.fu_code[1] connect issue_slots[3].in_uop.bits.fu_code[2], issue_slots[4].out_uop.fu_code[2] connect issue_slots[3].in_uop.bits.fu_code[3], issue_slots[4].out_uop.fu_code[3] connect issue_slots[3].in_uop.bits.fu_code[4], issue_slots[4].out_uop.fu_code[4] connect issue_slots[3].in_uop.bits.fu_code[5], issue_slots[4].out_uop.fu_code[5] connect issue_slots[3].in_uop.bits.fu_code[6], issue_slots[4].out_uop.fu_code[6] connect issue_slots[3].in_uop.bits.fu_code[7], issue_slots[4].out_uop.fu_code[7] connect issue_slots[3].in_uop.bits.fu_code[8], issue_slots[4].out_uop.fu_code[8] connect issue_slots[3].in_uop.bits.fu_code[9], issue_slots[4].out_uop.fu_code[9] connect issue_slots[3].in_uop.bits.iq_type[0], issue_slots[4].out_uop.iq_type[0] connect issue_slots[3].in_uop.bits.iq_type[1], issue_slots[4].out_uop.iq_type[1] connect issue_slots[3].in_uop.bits.iq_type[2], issue_slots[4].out_uop.iq_type[2] connect issue_slots[3].in_uop.bits.iq_type[3], issue_slots[4].out_uop.iq_type[3] connect issue_slots[3].in_uop.bits.debug_pc, issue_slots[4].out_uop.debug_pc connect issue_slots[3].in_uop.bits.is_rvc, issue_slots[4].out_uop.is_rvc connect issue_slots[3].in_uop.bits.debug_inst, issue_slots[4].out_uop.debug_inst connect issue_slots[3].in_uop.bits.inst, issue_slots[4].out_uop.inst node _T_286 = eq(shamts_oh[4], UInt<1>(0h1)) when _T_286 : connect issue_slots[3].in_uop.valid, issue_slots[4].will_be_valid connect issue_slots[3].in_uop.bits.debug_tsrc, issue_slots[4].out_uop.debug_tsrc connect issue_slots[3].in_uop.bits.debug_fsrc, issue_slots[4].out_uop.debug_fsrc connect issue_slots[3].in_uop.bits.bp_xcpt_if, issue_slots[4].out_uop.bp_xcpt_if connect issue_slots[3].in_uop.bits.bp_debug_if, issue_slots[4].out_uop.bp_debug_if connect issue_slots[3].in_uop.bits.xcpt_ma_if, issue_slots[4].out_uop.xcpt_ma_if connect issue_slots[3].in_uop.bits.xcpt_ae_if, issue_slots[4].out_uop.xcpt_ae_if connect issue_slots[3].in_uop.bits.xcpt_pf_if, issue_slots[4].out_uop.xcpt_pf_if connect issue_slots[3].in_uop.bits.fp_typ, issue_slots[4].out_uop.fp_typ connect issue_slots[3].in_uop.bits.fp_rm, issue_slots[4].out_uop.fp_rm connect issue_slots[3].in_uop.bits.fp_val, issue_slots[4].out_uop.fp_val connect issue_slots[3].in_uop.bits.fcn_op, issue_slots[4].out_uop.fcn_op connect issue_slots[3].in_uop.bits.fcn_dw, issue_slots[4].out_uop.fcn_dw connect issue_slots[3].in_uop.bits.frs3_en, issue_slots[4].out_uop.frs3_en connect issue_slots[3].in_uop.bits.lrs2_rtype, issue_slots[4].out_uop.lrs2_rtype connect issue_slots[3].in_uop.bits.lrs1_rtype, issue_slots[4].out_uop.lrs1_rtype connect issue_slots[3].in_uop.bits.dst_rtype, issue_slots[4].out_uop.dst_rtype connect issue_slots[3].in_uop.bits.lrs3, issue_slots[4].out_uop.lrs3 connect issue_slots[3].in_uop.bits.lrs2, issue_slots[4].out_uop.lrs2 connect issue_slots[3].in_uop.bits.lrs1, issue_slots[4].out_uop.lrs1 connect issue_slots[3].in_uop.bits.ldst, issue_slots[4].out_uop.ldst connect issue_slots[3].in_uop.bits.ldst_is_rs1, issue_slots[4].out_uop.ldst_is_rs1 connect issue_slots[3].in_uop.bits.csr_cmd, issue_slots[4].out_uop.csr_cmd connect issue_slots[3].in_uop.bits.flush_on_commit, issue_slots[4].out_uop.flush_on_commit connect issue_slots[3].in_uop.bits.is_unique, issue_slots[4].out_uop.is_unique connect issue_slots[3].in_uop.bits.uses_stq, issue_slots[4].out_uop.uses_stq connect issue_slots[3].in_uop.bits.uses_ldq, issue_slots[4].out_uop.uses_ldq connect issue_slots[3].in_uop.bits.mem_signed, issue_slots[4].out_uop.mem_signed connect issue_slots[3].in_uop.bits.mem_size, issue_slots[4].out_uop.mem_size connect issue_slots[3].in_uop.bits.mem_cmd, issue_slots[4].out_uop.mem_cmd connect issue_slots[3].in_uop.bits.exc_cause, issue_slots[4].out_uop.exc_cause connect issue_slots[3].in_uop.bits.exception, issue_slots[4].out_uop.exception connect issue_slots[3].in_uop.bits.stale_pdst, issue_slots[4].out_uop.stale_pdst connect issue_slots[3].in_uop.bits.ppred_busy, issue_slots[4].out_uop.ppred_busy connect issue_slots[3].in_uop.bits.prs3_busy, issue_slots[4].out_uop.prs3_busy connect issue_slots[3].in_uop.bits.prs2_busy, issue_slots[4].out_uop.prs2_busy connect issue_slots[3].in_uop.bits.prs1_busy, issue_slots[4].out_uop.prs1_busy connect issue_slots[3].in_uop.bits.ppred, issue_slots[4].out_uop.ppred connect issue_slots[3].in_uop.bits.prs3, issue_slots[4].out_uop.prs3 connect issue_slots[3].in_uop.bits.prs2, issue_slots[4].out_uop.prs2 connect issue_slots[3].in_uop.bits.prs1, issue_slots[4].out_uop.prs1 connect issue_slots[3].in_uop.bits.pdst, issue_slots[4].out_uop.pdst connect issue_slots[3].in_uop.bits.rxq_idx, issue_slots[4].out_uop.rxq_idx connect issue_slots[3].in_uop.bits.stq_idx, issue_slots[4].out_uop.stq_idx connect issue_slots[3].in_uop.bits.ldq_idx, issue_slots[4].out_uop.ldq_idx connect issue_slots[3].in_uop.bits.rob_idx, issue_slots[4].out_uop.rob_idx connect issue_slots[3].in_uop.bits.fp_ctrl.vec, issue_slots[4].out_uop.fp_ctrl.vec connect issue_slots[3].in_uop.bits.fp_ctrl.wflags, issue_slots[4].out_uop.fp_ctrl.wflags connect issue_slots[3].in_uop.bits.fp_ctrl.sqrt, issue_slots[4].out_uop.fp_ctrl.sqrt connect issue_slots[3].in_uop.bits.fp_ctrl.div, issue_slots[4].out_uop.fp_ctrl.div connect issue_slots[3].in_uop.bits.fp_ctrl.fma, issue_slots[4].out_uop.fp_ctrl.fma connect issue_slots[3].in_uop.bits.fp_ctrl.fastpipe, issue_slots[4].out_uop.fp_ctrl.fastpipe connect issue_slots[3].in_uop.bits.fp_ctrl.toint, issue_slots[4].out_uop.fp_ctrl.toint connect issue_slots[3].in_uop.bits.fp_ctrl.fromint, issue_slots[4].out_uop.fp_ctrl.fromint connect issue_slots[3].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[4].out_uop.fp_ctrl.typeTagOut connect issue_slots[3].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[4].out_uop.fp_ctrl.typeTagIn connect issue_slots[3].in_uop.bits.fp_ctrl.swap23, issue_slots[4].out_uop.fp_ctrl.swap23 connect issue_slots[3].in_uop.bits.fp_ctrl.swap12, issue_slots[4].out_uop.fp_ctrl.swap12 connect issue_slots[3].in_uop.bits.fp_ctrl.ren3, issue_slots[4].out_uop.fp_ctrl.ren3 connect issue_slots[3].in_uop.bits.fp_ctrl.ren2, issue_slots[4].out_uop.fp_ctrl.ren2 connect issue_slots[3].in_uop.bits.fp_ctrl.ren1, issue_slots[4].out_uop.fp_ctrl.ren1 connect issue_slots[3].in_uop.bits.fp_ctrl.wen, issue_slots[4].out_uop.fp_ctrl.wen connect issue_slots[3].in_uop.bits.fp_ctrl.ldst, issue_slots[4].out_uop.fp_ctrl.ldst connect issue_slots[3].in_uop.bits.op2_sel, issue_slots[4].out_uop.op2_sel connect issue_slots[3].in_uop.bits.op1_sel, issue_slots[4].out_uop.op1_sel connect issue_slots[3].in_uop.bits.imm_packed, issue_slots[4].out_uop.imm_packed connect issue_slots[3].in_uop.bits.pimm, issue_slots[4].out_uop.pimm connect issue_slots[3].in_uop.bits.imm_sel, issue_slots[4].out_uop.imm_sel connect issue_slots[3].in_uop.bits.imm_rename, issue_slots[4].out_uop.imm_rename connect issue_slots[3].in_uop.bits.taken, issue_slots[4].out_uop.taken connect issue_slots[3].in_uop.bits.pc_lob, issue_slots[4].out_uop.pc_lob connect issue_slots[3].in_uop.bits.edge_inst, issue_slots[4].out_uop.edge_inst connect issue_slots[3].in_uop.bits.ftq_idx, issue_slots[4].out_uop.ftq_idx connect issue_slots[3].in_uop.bits.is_mov, issue_slots[4].out_uop.is_mov connect issue_slots[3].in_uop.bits.is_rocc, issue_slots[4].out_uop.is_rocc connect issue_slots[3].in_uop.bits.is_sys_pc2epc, issue_slots[4].out_uop.is_sys_pc2epc connect issue_slots[3].in_uop.bits.is_eret, issue_slots[4].out_uop.is_eret connect issue_slots[3].in_uop.bits.is_amo, issue_slots[4].out_uop.is_amo connect issue_slots[3].in_uop.bits.is_sfence, issue_slots[4].out_uop.is_sfence connect issue_slots[3].in_uop.bits.is_fencei, issue_slots[4].out_uop.is_fencei connect issue_slots[3].in_uop.bits.is_fence, issue_slots[4].out_uop.is_fence connect issue_slots[3].in_uop.bits.is_sfb, issue_slots[4].out_uop.is_sfb connect issue_slots[3].in_uop.bits.br_type, issue_slots[4].out_uop.br_type connect issue_slots[3].in_uop.bits.br_tag, issue_slots[4].out_uop.br_tag connect issue_slots[3].in_uop.bits.br_mask, issue_slots[4].out_uop.br_mask connect issue_slots[3].in_uop.bits.dis_col_sel, issue_slots[4].out_uop.dis_col_sel connect issue_slots[3].in_uop.bits.iw_p3_bypass_hint, issue_slots[4].out_uop.iw_p3_bypass_hint connect issue_slots[3].in_uop.bits.iw_p2_bypass_hint, issue_slots[4].out_uop.iw_p2_bypass_hint connect issue_slots[3].in_uop.bits.iw_p1_bypass_hint, issue_slots[4].out_uop.iw_p1_bypass_hint connect issue_slots[3].in_uop.bits.iw_p2_speculative_child, issue_slots[4].out_uop.iw_p2_speculative_child connect issue_slots[3].in_uop.bits.iw_p1_speculative_child, issue_slots[4].out_uop.iw_p1_speculative_child connect issue_slots[3].in_uop.bits.iw_issued_partial_dgen, issue_slots[4].out_uop.iw_issued_partial_dgen connect issue_slots[3].in_uop.bits.iw_issued_partial_agen, issue_slots[4].out_uop.iw_issued_partial_agen connect issue_slots[3].in_uop.bits.iw_issued, issue_slots[4].out_uop.iw_issued connect issue_slots[3].in_uop.bits.fu_code[0], issue_slots[4].out_uop.fu_code[0] connect issue_slots[3].in_uop.bits.fu_code[1], issue_slots[4].out_uop.fu_code[1] connect issue_slots[3].in_uop.bits.fu_code[2], issue_slots[4].out_uop.fu_code[2] connect issue_slots[3].in_uop.bits.fu_code[3], issue_slots[4].out_uop.fu_code[3] connect issue_slots[3].in_uop.bits.fu_code[4], issue_slots[4].out_uop.fu_code[4] connect issue_slots[3].in_uop.bits.fu_code[5], issue_slots[4].out_uop.fu_code[5] connect issue_slots[3].in_uop.bits.fu_code[6], issue_slots[4].out_uop.fu_code[6] connect issue_slots[3].in_uop.bits.fu_code[7], issue_slots[4].out_uop.fu_code[7] connect issue_slots[3].in_uop.bits.fu_code[8], issue_slots[4].out_uop.fu_code[8] connect issue_slots[3].in_uop.bits.fu_code[9], issue_slots[4].out_uop.fu_code[9] connect issue_slots[3].in_uop.bits.iq_type[0], issue_slots[4].out_uop.iq_type[0] connect issue_slots[3].in_uop.bits.iq_type[1], issue_slots[4].out_uop.iq_type[1] connect issue_slots[3].in_uop.bits.iq_type[2], issue_slots[4].out_uop.iq_type[2] connect issue_slots[3].in_uop.bits.iq_type[3], issue_slots[4].out_uop.iq_type[3] connect issue_slots[3].in_uop.bits.debug_pc, issue_slots[4].out_uop.debug_pc connect issue_slots[3].in_uop.bits.is_rvc, issue_slots[4].out_uop.is_rvc connect issue_slots[3].in_uop.bits.debug_inst, issue_slots[4].out_uop.debug_inst connect issue_slots[3].in_uop.bits.inst, issue_slots[4].out_uop.inst node _T_287 = eq(shamts_oh[5], UInt<2>(0h2)) when _T_287 : connect issue_slots[3].in_uop.valid, issue_slots[5].will_be_valid connect issue_slots[3].in_uop.bits.debug_tsrc, issue_slots[5].out_uop.debug_tsrc connect issue_slots[3].in_uop.bits.debug_fsrc, issue_slots[5].out_uop.debug_fsrc connect issue_slots[3].in_uop.bits.bp_xcpt_if, issue_slots[5].out_uop.bp_xcpt_if connect issue_slots[3].in_uop.bits.bp_debug_if, issue_slots[5].out_uop.bp_debug_if connect issue_slots[3].in_uop.bits.xcpt_ma_if, issue_slots[5].out_uop.xcpt_ma_if connect issue_slots[3].in_uop.bits.xcpt_ae_if, issue_slots[5].out_uop.xcpt_ae_if connect issue_slots[3].in_uop.bits.xcpt_pf_if, issue_slots[5].out_uop.xcpt_pf_if connect issue_slots[3].in_uop.bits.fp_typ, issue_slots[5].out_uop.fp_typ connect issue_slots[3].in_uop.bits.fp_rm, issue_slots[5].out_uop.fp_rm connect issue_slots[3].in_uop.bits.fp_val, issue_slots[5].out_uop.fp_val connect issue_slots[3].in_uop.bits.fcn_op, issue_slots[5].out_uop.fcn_op connect issue_slots[3].in_uop.bits.fcn_dw, issue_slots[5].out_uop.fcn_dw connect issue_slots[3].in_uop.bits.frs3_en, issue_slots[5].out_uop.frs3_en connect issue_slots[3].in_uop.bits.lrs2_rtype, issue_slots[5].out_uop.lrs2_rtype connect issue_slots[3].in_uop.bits.lrs1_rtype, issue_slots[5].out_uop.lrs1_rtype connect issue_slots[3].in_uop.bits.dst_rtype, issue_slots[5].out_uop.dst_rtype connect issue_slots[3].in_uop.bits.lrs3, issue_slots[5].out_uop.lrs3 connect issue_slots[3].in_uop.bits.lrs2, issue_slots[5].out_uop.lrs2 connect issue_slots[3].in_uop.bits.lrs1, issue_slots[5].out_uop.lrs1 connect issue_slots[3].in_uop.bits.ldst, issue_slots[5].out_uop.ldst connect issue_slots[3].in_uop.bits.ldst_is_rs1, issue_slots[5].out_uop.ldst_is_rs1 connect issue_slots[3].in_uop.bits.csr_cmd, issue_slots[5].out_uop.csr_cmd connect issue_slots[3].in_uop.bits.flush_on_commit, issue_slots[5].out_uop.flush_on_commit connect issue_slots[3].in_uop.bits.is_unique, issue_slots[5].out_uop.is_unique connect issue_slots[3].in_uop.bits.uses_stq, issue_slots[5].out_uop.uses_stq connect issue_slots[3].in_uop.bits.uses_ldq, issue_slots[5].out_uop.uses_ldq connect issue_slots[3].in_uop.bits.mem_signed, issue_slots[5].out_uop.mem_signed connect issue_slots[3].in_uop.bits.mem_size, issue_slots[5].out_uop.mem_size connect issue_slots[3].in_uop.bits.mem_cmd, issue_slots[5].out_uop.mem_cmd connect issue_slots[3].in_uop.bits.exc_cause, issue_slots[5].out_uop.exc_cause connect issue_slots[3].in_uop.bits.exception, issue_slots[5].out_uop.exception connect issue_slots[3].in_uop.bits.stale_pdst, issue_slots[5].out_uop.stale_pdst connect issue_slots[3].in_uop.bits.ppred_busy, issue_slots[5].out_uop.ppred_busy connect issue_slots[3].in_uop.bits.prs3_busy, issue_slots[5].out_uop.prs3_busy connect issue_slots[3].in_uop.bits.prs2_busy, issue_slots[5].out_uop.prs2_busy connect issue_slots[3].in_uop.bits.prs1_busy, issue_slots[5].out_uop.prs1_busy connect issue_slots[3].in_uop.bits.ppred, issue_slots[5].out_uop.ppred connect issue_slots[3].in_uop.bits.prs3, issue_slots[5].out_uop.prs3 connect issue_slots[3].in_uop.bits.prs2, issue_slots[5].out_uop.prs2 connect issue_slots[3].in_uop.bits.prs1, issue_slots[5].out_uop.prs1 connect issue_slots[3].in_uop.bits.pdst, issue_slots[5].out_uop.pdst connect issue_slots[3].in_uop.bits.rxq_idx, issue_slots[5].out_uop.rxq_idx connect issue_slots[3].in_uop.bits.stq_idx, issue_slots[5].out_uop.stq_idx connect issue_slots[3].in_uop.bits.ldq_idx, issue_slots[5].out_uop.ldq_idx connect issue_slots[3].in_uop.bits.rob_idx, issue_slots[5].out_uop.rob_idx connect issue_slots[3].in_uop.bits.fp_ctrl.vec, issue_slots[5].out_uop.fp_ctrl.vec connect issue_slots[3].in_uop.bits.fp_ctrl.wflags, issue_slots[5].out_uop.fp_ctrl.wflags connect issue_slots[3].in_uop.bits.fp_ctrl.sqrt, issue_slots[5].out_uop.fp_ctrl.sqrt connect issue_slots[3].in_uop.bits.fp_ctrl.div, issue_slots[5].out_uop.fp_ctrl.div connect issue_slots[3].in_uop.bits.fp_ctrl.fma, issue_slots[5].out_uop.fp_ctrl.fma connect issue_slots[3].in_uop.bits.fp_ctrl.fastpipe, issue_slots[5].out_uop.fp_ctrl.fastpipe connect issue_slots[3].in_uop.bits.fp_ctrl.toint, issue_slots[5].out_uop.fp_ctrl.toint connect issue_slots[3].in_uop.bits.fp_ctrl.fromint, issue_slots[5].out_uop.fp_ctrl.fromint connect issue_slots[3].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[5].out_uop.fp_ctrl.typeTagOut connect issue_slots[3].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[5].out_uop.fp_ctrl.typeTagIn connect issue_slots[3].in_uop.bits.fp_ctrl.swap23, issue_slots[5].out_uop.fp_ctrl.swap23 connect issue_slots[3].in_uop.bits.fp_ctrl.swap12, issue_slots[5].out_uop.fp_ctrl.swap12 connect issue_slots[3].in_uop.bits.fp_ctrl.ren3, issue_slots[5].out_uop.fp_ctrl.ren3 connect issue_slots[3].in_uop.bits.fp_ctrl.ren2, issue_slots[5].out_uop.fp_ctrl.ren2 connect issue_slots[3].in_uop.bits.fp_ctrl.ren1, issue_slots[5].out_uop.fp_ctrl.ren1 connect issue_slots[3].in_uop.bits.fp_ctrl.wen, issue_slots[5].out_uop.fp_ctrl.wen connect issue_slots[3].in_uop.bits.fp_ctrl.ldst, issue_slots[5].out_uop.fp_ctrl.ldst connect issue_slots[3].in_uop.bits.op2_sel, issue_slots[5].out_uop.op2_sel connect issue_slots[3].in_uop.bits.op1_sel, issue_slots[5].out_uop.op1_sel connect issue_slots[3].in_uop.bits.imm_packed, issue_slots[5].out_uop.imm_packed connect issue_slots[3].in_uop.bits.pimm, issue_slots[5].out_uop.pimm connect issue_slots[3].in_uop.bits.imm_sel, issue_slots[5].out_uop.imm_sel connect issue_slots[3].in_uop.bits.imm_rename, issue_slots[5].out_uop.imm_rename connect issue_slots[3].in_uop.bits.taken, issue_slots[5].out_uop.taken connect issue_slots[3].in_uop.bits.pc_lob, issue_slots[5].out_uop.pc_lob connect issue_slots[3].in_uop.bits.edge_inst, issue_slots[5].out_uop.edge_inst connect issue_slots[3].in_uop.bits.ftq_idx, issue_slots[5].out_uop.ftq_idx connect issue_slots[3].in_uop.bits.is_mov, issue_slots[5].out_uop.is_mov connect issue_slots[3].in_uop.bits.is_rocc, issue_slots[5].out_uop.is_rocc connect issue_slots[3].in_uop.bits.is_sys_pc2epc, issue_slots[5].out_uop.is_sys_pc2epc connect issue_slots[3].in_uop.bits.is_eret, issue_slots[5].out_uop.is_eret connect issue_slots[3].in_uop.bits.is_amo, issue_slots[5].out_uop.is_amo connect issue_slots[3].in_uop.bits.is_sfence, issue_slots[5].out_uop.is_sfence connect issue_slots[3].in_uop.bits.is_fencei, issue_slots[5].out_uop.is_fencei connect issue_slots[3].in_uop.bits.is_fence, issue_slots[5].out_uop.is_fence connect issue_slots[3].in_uop.bits.is_sfb, issue_slots[5].out_uop.is_sfb connect issue_slots[3].in_uop.bits.br_type, issue_slots[5].out_uop.br_type connect issue_slots[3].in_uop.bits.br_tag, issue_slots[5].out_uop.br_tag connect issue_slots[3].in_uop.bits.br_mask, issue_slots[5].out_uop.br_mask connect issue_slots[3].in_uop.bits.dis_col_sel, issue_slots[5].out_uop.dis_col_sel connect issue_slots[3].in_uop.bits.iw_p3_bypass_hint, issue_slots[5].out_uop.iw_p3_bypass_hint connect issue_slots[3].in_uop.bits.iw_p2_bypass_hint, issue_slots[5].out_uop.iw_p2_bypass_hint connect issue_slots[3].in_uop.bits.iw_p1_bypass_hint, issue_slots[5].out_uop.iw_p1_bypass_hint connect issue_slots[3].in_uop.bits.iw_p2_speculative_child, issue_slots[5].out_uop.iw_p2_speculative_child connect issue_slots[3].in_uop.bits.iw_p1_speculative_child, issue_slots[5].out_uop.iw_p1_speculative_child connect issue_slots[3].in_uop.bits.iw_issued_partial_dgen, issue_slots[5].out_uop.iw_issued_partial_dgen connect issue_slots[3].in_uop.bits.iw_issued_partial_agen, issue_slots[5].out_uop.iw_issued_partial_agen connect issue_slots[3].in_uop.bits.iw_issued, issue_slots[5].out_uop.iw_issued connect issue_slots[3].in_uop.bits.fu_code[0], issue_slots[5].out_uop.fu_code[0] connect issue_slots[3].in_uop.bits.fu_code[1], issue_slots[5].out_uop.fu_code[1] connect issue_slots[3].in_uop.bits.fu_code[2], issue_slots[5].out_uop.fu_code[2] connect issue_slots[3].in_uop.bits.fu_code[3], issue_slots[5].out_uop.fu_code[3] connect issue_slots[3].in_uop.bits.fu_code[4], issue_slots[5].out_uop.fu_code[4] connect issue_slots[3].in_uop.bits.fu_code[5], issue_slots[5].out_uop.fu_code[5] connect issue_slots[3].in_uop.bits.fu_code[6], issue_slots[5].out_uop.fu_code[6] connect issue_slots[3].in_uop.bits.fu_code[7], issue_slots[5].out_uop.fu_code[7] connect issue_slots[3].in_uop.bits.fu_code[8], issue_slots[5].out_uop.fu_code[8] connect issue_slots[3].in_uop.bits.fu_code[9], issue_slots[5].out_uop.fu_code[9] connect issue_slots[3].in_uop.bits.iq_type[0], issue_slots[5].out_uop.iq_type[0] connect issue_slots[3].in_uop.bits.iq_type[1], issue_slots[5].out_uop.iq_type[1] connect issue_slots[3].in_uop.bits.iq_type[2], issue_slots[5].out_uop.iq_type[2] connect issue_slots[3].in_uop.bits.iq_type[3], issue_slots[5].out_uop.iq_type[3] connect issue_slots[3].in_uop.bits.debug_pc, issue_slots[5].out_uop.debug_pc connect issue_slots[3].in_uop.bits.is_rvc, issue_slots[5].out_uop.is_rvc connect issue_slots[3].in_uop.bits.debug_inst, issue_slots[5].out_uop.debug_inst connect issue_slots[3].in_uop.bits.inst, issue_slots[5].out_uop.inst node _T_288 = eq(shamts_oh[6], UInt<3>(0h4)) when _T_288 : connect issue_slots[3].in_uop.valid, issue_slots[6].will_be_valid connect issue_slots[3].in_uop.bits.debug_tsrc, issue_slots[6].out_uop.debug_tsrc connect issue_slots[3].in_uop.bits.debug_fsrc, issue_slots[6].out_uop.debug_fsrc connect issue_slots[3].in_uop.bits.bp_xcpt_if, issue_slots[6].out_uop.bp_xcpt_if connect issue_slots[3].in_uop.bits.bp_debug_if, issue_slots[6].out_uop.bp_debug_if connect issue_slots[3].in_uop.bits.xcpt_ma_if, issue_slots[6].out_uop.xcpt_ma_if connect issue_slots[3].in_uop.bits.xcpt_ae_if, issue_slots[6].out_uop.xcpt_ae_if connect issue_slots[3].in_uop.bits.xcpt_pf_if, issue_slots[6].out_uop.xcpt_pf_if connect issue_slots[3].in_uop.bits.fp_typ, issue_slots[6].out_uop.fp_typ connect issue_slots[3].in_uop.bits.fp_rm, issue_slots[6].out_uop.fp_rm connect issue_slots[3].in_uop.bits.fp_val, issue_slots[6].out_uop.fp_val connect issue_slots[3].in_uop.bits.fcn_op, issue_slots[6].out_uop.fcn_op connect issue_slots[3].in_uop.bits.fcn_dw, issue_slots[6].out_uop.fcn_dw connect issue_slots[3].in_uop.bits.frs3_en, issue_slots[6].out_uop.frs3_en connect issue_slots[3].in_uop.bits.lrs2_rtype, issue_slots[6].out_uop.lrs2_rtype connect issue_slots[3].in_uop.bits.lrs1_rtype, issue_slots[6].out_uop.lrs1_rtype connect issue_slots[3].in_uop.bits.dst_rtype, issue_slots[6].out_uop.dst_rtype connect issue_slots[3].in_uop.bits.lrs3, issue_slots[6].out_uop.lrs3 connect issue_slots[3].in_uop.bits.lrs2, issue_slots[6].out_uop.lrs2 connect issue_slots[3].in_uop.bits.lrs1, issue_slots[6].out_uop.lrs1 connect issue_slots[3].in_uop.bits.ldst, issue_slots[6].out_uop.ldst connect issue_slots[3].in_uop.bits.ldst_is_rs1, issue_slots[6].out_uop.ldst_is_rs1 connect issue_slots[3].in_uop.bits.csr_cmd, issue_slots[6].out_uop.csr_cmd connect issue_slots[3].in_uop.bits.flush_on_commit, issue_slots[6].out_uop.flush_on_commit connect issue_slots[3].in_uop.bits.is_unique, issue_slots[6].out_uop.is_unique connect issue_slots[3].in_uop.bits.uses_stq, issue_slots[6].out_uop.uses_stq connect issue_slots[3].in_uop.bits.uses_ldq, issue_slots[6].out_uop.uses_ldq connect issue_slots[3].in_uop.bits.mem_signed, issue_slots[6].out_uop.mem_signed connect issue_slots[3].in_uop.bits.mem_size, issue_slots[6].out_uop.mem_size connect issue_slots[3].in_uop.bits.mem_cmd, issue_slots[6].out_uop.mem_cmd connect issue_slots[3].in_uop.bits.exc_cause, issue_slots[6].out_uop.exc_cause connect issue_slots[3].in_uop.bits.exception, issue_slots[6].out_uop.exception connect issue_slots[3].in_uop.bits.stale_pdst, issue_slots[6].out_uop.stale_pdst connect issue_slots[3].in_uop.bits.ppred_busy, issue_slots[6].out_uop.ppred_busy connect issue_slots[3].in_uop.bits.prs3_busy, issue_slots[6].out_uop.prs3_busy connect issue_slots[3].in_uop.bits.prs2_busy, issue_slots[6].out_uop.prs2_busy connect issue_slots[3].in_uop.bits.prs1_busy, issue_slots[6].out_uop.prs1_busy connect issue_slots[3].in_uop.bits.ppred, issue_slots[6].out_uop.ppred connect issue_slots[3].in_uop.bits.prs3, issue_slots[6].out_uop.prs3 connect issue_slots[3].in_uop.bits.prs2, issue_slots[6].out_uop.prs2 connect issue_slots[3].in_uop.bits.prs1, issue_slots[6].out_uop.prs1 connect issue_slots[3].in_uop.bits.pdst, issue_slots[6].out_uop.pdst connect issue_slots[3].in_uop.bits.rxq_idx, issue_slots[6].out_uop.rxq_idx connect issue_slots[3].in_uop.bits.stq_idx, issue_slots[6].out_uop.stq_idx connect issue_slots[3].in_uop.bits.ldq_idx, issue_slots[6].out_uop.ldq_idx connect issue_slots[3].in_uop.bits.rob_idx, issue_slots[6].out_uop.rob_idx connect issue_slots[3].in_uop.bits.fp_ctrl.vec, issue_slots[6].out_uop.fp_ctrl.vec connect issue_slots[3].in_uop.bits.fp_ctrl.wflags, issue_slots[6].out_uop.fp_ctrl.wflags connect issue_slots[3].in_uop.bits.fp_ctrl.sqrt, issue_slots[6].out_uop.fp_ctrl.sqrt connect issue_slots[3].in_uop.bits.fp_ctrl.div, issue_slots[6].out_uop.fp_ctrl.div connect issue_slots[3].in_uop.bits.fp_ctrl.fma, issue_slots[6].out_uop.fp_ctrl.fma connect issue_slots[3].in_uop.bits.fp_ctrl.fastpipe, issue_slots[6].out_uop.fp_ctrl.fastpipe connect issue_slots[3].in_uop.bits.fp_ctrl.toint, issue_slots[6].out_uop.fp_ctrl.toint connect issue_slots[3].in_uop.bits.fp_ctrl.fromint, issue_slots[6].out_uop.fp_ctrl.fromint connect issue_slots[3].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[6].out_uop.fp_ctrl.typeTagOut connect issue_slots[3].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[6].out_uop.fp_ctrl.typeTagIn connect issue_slots[3].in_uop.bits.fp_ctrl.swap23, issue_slots[6].out_uop.fp_ctrl.swap23 connect issue_slots[3].in_uop.bits.fp_ctrl.swap12, issue_slots[6].out_uop.fp_ctrl.swap12 connect issue_slots[3].in_uop.bits.fp_ctrl.ren3, issue_slots[6].out_uop.fp_ctrl.ren3 connect issue_slots[3].in_uop.bits.fp_ctrl.ren2, issue_slots[6].out_uop.fp_ctrl.ren2 connect issue_slots[3].in_uop.bits.fp_ctrl.ren1, issue_slots[6].out_uop.fp_ctrl.ren1 connect issue_slots[3].in_uop.bits.fp_ctrl.wen, issue_slots[6].out_uop.fp_ctrl.wen connect issue_slots[3].in_uop.bits.fp_ctrl.ldst, issue_slots[6].out_uop.fp_ctrl.ldst connect issue_slots[3].in_uop.bits.op2_sel, issue_slots[6].out_uop.op2_sel connect issue_slots[3].in_uop.bits.op1_sel, issue_slots[6].out_uop.op1_sel connect issue_slots[3].in_uop.bits.imm_packed, issue_slots[6].out_uop.imm_packed connect issue_slots[3].in_uop.bits.pimm, issue_slots[6].out_uop.pimm connect issue_slots[3].in_uop.bits.imm_sel, issue_slots[6].out_uop.imm_sel connect issue_slots[3].in_uop.bits.imm_rename, issue_slots[6].out_uop.imm_rename connect issue_slots[3].in_uop.bits.taken, issue_slots[6].out_uop.taken connect issue_slots[3].in_uop.bits.pc_lob, issue_slots[6].out_uop.pc_lob connect issue_slots[3].in_uop.bits.edge_inst, issue_slots[6].out_uop.edge_inst connect issue_slots[3].in_uop.bits.ftq_idx, issue_slots[6].out_uop.ftq_idx connect issue_slots[3].in_uop.bits.is_mov, issue_slots[6].out_uop.is_mov connect issue_slots[3].in_uop.bits.is_rocc, issue_slots[6].out_uop.is_rocc connect issue_slots[3].in_uop.bits.is_sys_pc2epc, issue_slots[6].out_uop.is_sys_pc2epc connect issue_slots[3].in_uop.bits.is_eret, issue_slots[6].out_uop.is_eret connect issue_slots[3].in_uop.bits.is_amo, issue_slots[6].out_uop.is_amo connect issue_slots[3].in_uop.bits.is_sfence, issue_slots[6].out_uop.is_sfence connect issue_slots[3].in_uop.bits.is_fencei, issue_slots[6].out_uop.is_fencei connect issue_slots[3].in_uop.bits.is_fence, issue_slots[6].out_uop.is_fence connect issue_slots[3].in_uop.bits.is_sfb, issue_slots[6].out_uop.is_sfb connect issue_slots[3].in_uop.bits.br_type, issue_slots[6].out_uop.br_type connect issue_slots[3].in_uop.bits.br_tag, issue_slots[6].out_uop.br_tag connect issue_slots[3].in_uop.bits.br_mask, issue_slots[6].out_uop.br_mask connect issue_slots[3].in_uop.bits.dis_col_sel, issue_slots[6].out_uop.dis_col_sel connect issue_slots[3].in_uop.bits.iw_p3_bypass_hint, issue_slots[6].out_uop.iw_p3_bypass_hint connect issue_slots[3].in_uop.bits.iw_p2_bypass_hint, issue_slots[6].out_uop.iw_p2_bypass_hint connect issue_slots[3].in_uop.bits.iw_p1_bypass_hint, issue_slots[6].out_uop.iw_p1_bypass_hint connect issue_slots[3].in_uop.bits.iw_p2_speculative_child, issue_slots[6].out_uop.iw_p2_speculative_child connect issue_slots[3].in_uop.bits.iw_p1_speculative_child, issue_slots[6].out_uop.iw_p1_speculative_child connect issue_slots[3].in_uop.bits.iw_issued_partial_dgen, issue_slots[6].out_uop.iw_issued_partial_dgen connect issue_slots[3].in_uop.bits.iw_issued_partial_agen, issue_slots[6].out_uop.iw_issued_partial_agen connect issue_slots[3].in_uop.bits.iw_issued, issue_slots[6].out_uop.iw_issued connect issue_slots[3].in_uop.bits.fu_code[0], issue_slots[6].out_uop.fu_code[0] connect issue_slots[3].in_uop.bits.fu_code[1], issue_slots[6].out_uop.fu_code[1] connect issue_slots[3].in_uop.bits.fu_code[2], issue_slots[6].out_uop.fu_code[2] connect issue_slots[3].in_uop.bits.fu_code[3], issue_slots[6].out_uop.fu_code[3] connect issue_slots[3].in_uop.bits.fu_code[4], issue_slots[6].out_uop.fu_code[4] connect issue_slots[3].in_uop.bits.fu_code[5], issue_slots[6].out_uop.fu_code[5] connect issue_slots[3].in_uop.bits.fu_code[6], issue_slots[6].out_uop.fu_code[6] connect issue_slots[3].in_uop.bits.fu_code[7], issue_slots[6].out_uop.fu_code[7] connect issue_slots[3].in_uop.bits.fu_code[8], issue_slots[6].out_uop.fu_code[8] connect issue_slots[3].in_uop.bits.fu_code[9], issue_slots[6].out_uop.fu_code[9] connect issue_slots[3].in_uop.bits.iq_type[0], issue_slots[6].out_uop.iq_type[0] connect issue_slots[3].in_uop.bits.iq_type[1], issue_slots[6].out_uop.iq_type[1] connect issue_slots[3].in_uop.bits.iq_type[2], issue_slots[6].out_uop.iq_type[2] connect issue_slots[3].in_uop.bits.iq_type[3], issue_slots[6].out_uop.iq_type[3] connect issue_slots[3].in_uop.bits.debug_pc, issue_slots[6].out_uop.debug_pc connect issue_slots[3].in_uop.bits.is_rvc, issue_slots[6].out_uop.is_rvc connect issue_slots[3].in_uop.bits.debug_inst, issue_slots[6].out_uop.debug_inst connect issue_slots[3].in_uop.bits.inst, issue_slots[6].out_uop.inst node _issue_slots_3_clear_T = neq(shamts_oh[3], UInt<1>(0h0)) connect issue_slots[3].clear, _issue_slots_3_clear_T connect issue_slots[4].in_uop.valid, UInt<1>(0h0) connect issue_slots[4].in_uop.bits.debug_tsrc, issue_slots[5].out_uop.debug_tsrc connect issue_slots[4].in_uop.bits.debug_fsrc, issue_slots[5].out_uop.debug_fsrc connect issue_slots[4].in_uop.bits.bp_xcpt_if, issue_slots[5].out_uop.bp_xcpt_if connect issue_slots[4].in_uop.bits.bp_debug_if, issue_slots[5].out_uop.bp_debug_if connect issue_slots[4].in_uop.bits.xcpt_ma_if, issue_slots[5].out_uop.xcpt_ma_if connect issue_slots[4].in_uop.bits.xcpt_ae_if, issue_slots[5].out_uop.xcpt_ae_if connect issue_slots[4].in_uop.bits.xcpt_pf_if, issue_slots[5].out_uop.xcpt_pf_if connect issue_slots[4].in_uop.bits.fp_typ, issue_slots[5].out_uop.fp_typ connect issue_slots[4].in_uop.bits.fp_rm, issue_slots[5].out_uop.fp_rm connect issue_slots[4].in_uop.bits.fp_val, issue_slots[5].out_uop.fp_val connect issue_slots[4].in_uop.bits.fcn_op, issue_slots[5].out_uop.fcn_op connect issue_slots[4].in_uop.bits.fcn_dw, issue_slots[5].out_uop.fcn_dw connect issue_slots[4].in_uop.bits.frs3_en, issue_slots[5].out_uop.frs3_en connect issue_slots[4].in_uop.bits.lrs2_rtype, issue_slots[5].out_uop.lrs2_rtype connect issue_slots[4].in_uop.bits.lrs1_rtype, issue_slots[5].out_uop.lrs1_rtype connect issue_slots[4].in_uop.bits.dst_rtype, issue_slots[5].out_uop.dst_rtype connect issue_slots[4].in_uop.bits.lrs3, issue_slots[5].out_uop.lrs3 connect issue_slots[4].in_uop.bits.lrs2, issue_slots[5].out_uop.lrs2 connect issue_slots[4].in_uop.bits.lrs1, issue_slots[5].out_uop.lrs1 connect issue_slots[4].in_uop.bits.ldst, issue_slots[5].out_uop.ldst connect issue_slots[4].in_uop.bits.ldst_is_rs1, issue_slots[5].out_uop.ldst_is_rs1 connect issue_slots[4].in_uop.bits.csr_cmd, issue_slots[5].out_uop.csr_cmd connect issue_slots[4].in_uop.bits.flush_on_commit, issue_slots[5].out_uop.flush_on_commit connect issue_slots[4].in_uop.bits.is_unique, issue_slots[5].out_uop.is_unique connect issue_slots[4].in_uop.bits.uses_stq, issue_slots[5].out_uop.uses_stq connect issue_slots[4].in_uop.bits.uses_ldq, issue_slots[5].out_uop.uses_ldq connect issue_slots[4].in_uop.bits.mem_signed, issue_slots[5].out_uop.mem_signed connect issue_slots[4].in_uop.bits.mem_size, issue_slots[5].out_uop.mem_size connect issue_slots[4].in_uop.bits.mem_cmd, issue_slots[5].out_uop.mem_cmd connect issue_slots[4].in_uop.bits.exc_cause, issue_slots[5].out_uop.exc_cause connect issue_slots[4].in_uop.bits.exception, issue_slots[5].out_uop.exception connect issue_slots[4].in_uop.bits.stale_pdst, issue_slots[5].out_uop.stale_pdst connect issue_slots[4].in_uop.bits.ppred_busy, issue_slots[5].out_uop.ppred_busy connect issue_slots[4].in_uop.bits.prs3_busy, issue_slots[5].out_uop.prs3_busy connect issue_slots[4].in_uop.bits.prs2_busy, issue_slots[5].out_uop.prs2_busy connect issue_slots[4].in_uop.bits.prs1_busy, issue_slots[5].out_uop.prs1_busy connect issue_slots[4].in_uop.bits.ppred, issue_slots[5].out_uop.ppred connect issue_slots[4].in_uop.bits.prs3, issue_slots[5].out_uop.prs3 connect issue_slots[4].in_uop.bits.prs2, issue_slots[5].out_uop.prs2 connect issue_slots[4].in_uop.bits.prs1, issue_slots[5].out_uop.prs1 connect issue_slots[4].in_uop.bits.pdst, issue_slots[5].out_uop.pdst connect issue_slots[4].in_uop.bits.rxq_idx, issue_slots[5].out_uop.rxq_idx connect issue_slots[4].in_uop.bits.stq_idx, issue_slots[5].out_uop.stq_idx connect issue_slots[4].in_uop.bits.ldq_idx, issue_slots[5].out_uop.ldq_idx connect issue_slots[4].in_uop.bits.rob_idx, issue_slots[5].out_uop.rob_idx connect issue_slots[4].in_uop.bits.fp_ctrl.vec, issue_slots[5].out_uop.fp_ctrl.vec connect issue_slots[4].in_uop.bits.fp_ctrl.wflags, issue_slots[5].out_uop.fp_ctrl.wflags connect issue_slots[4].in_uop.bits.fp_ctrl.sqrt, issue_slots[5].out_uop.fp_ctrl.sqrt connect issue_slots[4].in_uop.bits.fp_ctrl.div, issue_slots[5].out_uop.fp_ctrl.div connect issue_slots[4].in_uop.bits.fp_ctrl.fma, issue_slots[5].out_uop.fp_ctrl.fma connect issue_slots[4].in_uop.bits.fp_ctrl.fastpipe, issue_slots[5].out_uop.fp_ctrl.fastpipe connect issue_slots[4].in_uop.bits.fp_ctrl.toint, issue_slots[5].out_uop.fp_ctrl.toint connect issue_slots[4].in_uop.bits.fp_ctrl.fromint, issue_slots[5].out_uop.fp_ctrl.fromint connect issue_slots[4].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[5].out_uop.fp_ctrl.typeTagOut connect issue_slots[4].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[5].out_uop.fp_ctrl.typeTagIn connect issue_slots[4].in_uop.bits.fp_ctrl.swap23, issue_slots[5].out_uop.fp_ctrl.swap23 connect issue_slots[4].in_uop.bits.fp_ctrl.swap12, issue_slots[5].out_uop.fp_ctrl.swap12 connect issue_slots[4].in_uop.bits.fp_ctrl.ren3, issue_slots[5].out_uop.fp_ctrl.ren3 connect issue_slots[4].in_uop.bits.fp_ctrl.ren2, issue_slots[5].out_uop.fp_ctrl.ren2 connect issue_slots[4].in_uop.bits.fp_ctrl.ren1, issue_slots[5].out_uop.fp_ctrl.ren1 connect issue_slots[4].in_uop.bits.fp_ctrl.wen, issue_slots[5].out_uop.fp_ctrl.wen connect issue_slots[4].in_uop.bits.fp_ctrl.ldst, issue_slots[5].out_uop.fp_ctrl.ldst connect issue_slots[4].in_uop.bits.op2_sel, issue_slots[5].out_uop.op2_sel connect issue_slots[4].in_uop.bits.op1_sel, issue_slots[5].out_uop.op1_sel connect issue_slots[4].in_uop.bits.imm_packed, issue_slots[5].out_uop.imm_packed connect issue_slots[4].in_uop.bits.pimm, issue_slots[5].out_uop.pimm connect issue_slots[4].in_uop.bits.imm_sel, issue_slots[5].out_uop.imm_sel connect issue_slots[4].in_uop.bits.imm_rename, issue_slots[5].out_uop.imm_rename connect issue_slots[4].in_uop.bits.taken, issue_slots[5].out_uop.taken connect issue_slots[4].in_uop.bits.pc_lob, issue_slots[5].out_uop.pc_lob connect issue_slots[4].in_uop.bits.edge_inst, issue_slots[5].out_uop.edge_inst connect issue_slots[4].in_uop.bits.ftq_idx, issue_slots[5].out_uop.ftq_idx connect issue_slots[4].in_uop.bits.is_mov, issue_slots[5].out_uop.is_mov connect issue_slots[4].in_uop.bits.is_rocc, issue_slots[5].out_uop.is_rocc connect issue_slots[4].in_uop.bits.is_sys_pc2epc, issue_slots[5].out_uop.is_sys_pc2epc connect issue_slots[4].in_uop.bits.is_eret, issue_slots[5].out_uop.is_eret connect issue_slots[4].in_uop.bits.is_amo, issue_slots[5].out_uop.is_amo connect issue_slots[4].in_uop.bits.is_sfence, issue_slots[5].out_uop.is_sfence connect issue_slots[4].in_uop.bits.is_fencei, issue_slots[5].out_uop.is_fencei connect issue_slots[4].in_uop.bits.is_fence, issue_slots[5].out_uop.is_fence connect issue_slots[4].in_uop.bits.is_sfb, issue_slots[5].out_uop.is_sfb connect issue_slots[4].in_uop.bits.br_type, issue_slots[5].out_uop.br_type connect issue_slots[4].in_uop.bits.br_tag, issue_slots[5].out_uop.br_tag connect issue_slots[4].in_uop.bits.br_mask, issue_slots[5].out_uop.br_mask connect issue_slots[4].in_uop.bits.dis_col_sel, issue_slots[5].out_uop.dis_col_sel connect issue_slots[4].in_uop.bits.iw_p3_bypass_hint, issue_slots[5].out_uop.iw_p3_bypass_hint connect issue_slots[4].in_uop.bits.iw_p2_bypass_hint, issue_slots[5].out_uop.iw_p2_bypass_hint connect issue_slots[4].in_uop.bits.iw_p1_bypass_hint, issue_slots[5].out_uop.iw_p1_bypass_hint connect issue_slots[4].in_uop.bits.iw_p2_speculative_child, issue_slots[5].out_uop.iw_p2_speculative_child connect issue_slots[4].in_uop.bits.iw_p1_speculative_child, issue_slots[5].out_uop.iw_p1_speculative_child connect issue_slots[4].in_uop.bits.iw_issued_partial_dgen, issue_slots[5].out_uop.iw_issued_partial_dgen connect issue_slots[4].in_uop.bits.iw_issued_partial_agen, issue_slots[5].out_uop.iw_issued_partial_agen connect issue_slots[4].in_uop.bits.iw_issued, issue_slots[5].out_uop.iw_issued connect issue_slots[4].in_uop.bits.fu_code[0], issue_slots[5].out_uop.fu_code[0] connect issue_slots[4].in_uop.bits.fu_code[1], issue_slots[5].out_uop.fu_code[1] connect issue_slots[4].in_uop.bits.fu_code[2], issue_slots[5].out_uop.fu_code[2] connect issue_slots[4].in_uop.bits.fu_code[3], issue_slots[5].out_uop.fu_code[3] connect issue_slots[4].in_uop.bits.fu_code[4], issue_slots[5].out_uop.fu_code[4] connect issue_slots[4].in_uop.bits.fu_code[5], issue_slots[5].out_uop.fu_code[5] connect issue_slots[4].in_uop.bits.fu_code[6], issue_slots[5].out_uop.fu_code[6] connect issue_slots[4].in_uop.bits.fu_code[7], issue_slots[5].out_uop.fu_code[7] connect issue_slots[4].in_uop.bits.fu_code[8], issue_slots[5].out_uop.fu_code[8] connect issue_slots[4].in_uop.bits.fu_code[9], issue_slots[5].out_uop.fu_code[9] connect issue_slots[4].in_uop.bits.iq_type[0], issue_slots[5].out_uop.iq_type[0] connect issue_slots[4].in_uop.bits.iq_type[1], issue_slots[5].out_uop.iq_type[1] connect issue_slots[4].in_uop.bits.iq_type[2], issue_slots[5].out_uop.iq_type[2] connect issue_slots[4].in_uop.bits.iq_type[3], issue_slots[5].out_uop.iq_type[3] connect issue_slots[4].in_uop.bits.debug_pc, issue_slots[5].out_uop.debug_pc connect issue_slots[4].in_uop.bits.is_rvc, issue_slots[5].out_uop.is_rvc connect issue_slots[4].in_uop.bits.debug_inst, issue_slots[5].out_uop.debug_inst connect issue_slots[4].in_uop.bits.inst, issue_slots[5].out_uop.inst node _T_289 = eq(shamts_oh[5], UInt<1>(0h1)) when _T_289 : connect issue_slots[4].in_uop.valid, issue_slots[5].will_be_valid connect issue_slots[4].in_uop.bits.debug_tsrc, issue_slots[5].out_uop.debug_tsrc connect issue_slots[4].in_uop.bits.debug_fsrc, issue_slots[5].out_uop.debug_fsrc connect issue_slots[4].in_uop.bits.bp_xcpt_if, issue_slots[5].out_uop.bp_xcpt_if connect issue_slots[4].in_uop.bits.bp_debug_if, issue_slots[5].out_uop.bp_debug_if connect issue_slots[4].in_uop.bits.xcpt_ma_if, issue_slots[5].out_uop.xcpt_ma_if connect issue_slots[4].in_uop.bits.xcpt_ae_if, issue_slots[5].out_uop.xcpt_ae_if connect issue_slots[4].in_uop.bits.xcpt_pf_if, issue_slots[5].out_uop.xcpt_pf_if connect issue_slots[4].in_uop.bits.fp_typ, issue_slots[5].out_uop.fp_typ connect issue_slots[4].in_uop.bits.fp_rm, issue_slots[5].out_uop.fp_rm connect issue_slots[4].in_uop.bits.fp_val, issue_slots[5].out_uop.fp_val connect issue_slots[4].in_uop.bits.fcn_op, issue_slots[5].out_uop.fcn_op connect issue_slots[4].in_uop.bits.fcn_dw, issue_slots[5].out_uop.fcn_dw connect issue_slots[4].in_uop.bits.frs3_en, issue_slots[5].out_uop.frs3_en connect issue_slots[4].in_uop.bits.lrs2_rtype, issue_slots[5].out_uop.lrs2_rtype connect issue_slots[4].in_uop.bits.lrs1_rtype, issue_slots[5].out_uop.lrs1_rtype connect issue_slots[4].in_uop.bits.dst_rtype, issue_slots[5].out_uop.dst_rtype connect issue_slots[4].in_uop.bits.lrs3, issue_slots[5].out_uop.lrs3 connect issue_slots[4].in_uop.bits.lrs2, issue_slots[5].out_uop.lrs2 connect issue_slots[4].in_uop.bits.lrs1, issue_slots[5].out_uop.lrs1 connect issue_slots[4].in_uop.bits.ldst, issue_slots[5].out_uop.ldst connect issue_slots[4].in_uop.bits.ldst_is_rs1, issue_slots[5].out_uop.ldst_is_rs1 connect issue_slots[4].in_uop.bits.csr_cmd, issue_slots[5].out_uop.csr_cmd connect issue_slots[4].in_uop.bits.flush_on_commit, issue_slots[5].out_uop.flush_on_commit connect issue_slots[4].in_uop.bits.is_unique, issue_slots[5].out_uop.is_unique connect issue_slots[4].in_uop.bits.uses_stq, issue_slots[5].out_uop.uses_stq connect issue_slots[4].in_uop.bits.uses_ldq, issue_slots[5].out_uop.uses_ldq connect issue_slots[4].in_uop.bits.mem_signed, issue_slots[5].out_uop.mem_signed connect issue_slots[4].in_uop.bits.mem_size, issue_slots[5].out_uop.mem_size connect issue_slots[4].in_uop.bits.mem_cmd, issue_slots[5].out_uop.mem_cmd connect issue_slots[4].in_uop.bits.exc_cause, issue_slots[5].out_uop.exc_cause connect issue_slots[4].in_uop.bits.exception, issue_slots[5].out_uop.exception connect issue_slots[4].in_uop.bits.stale_pdst, issue_slots[5].out_uop.stale_pdst connect issue_slots[4].in_uop.bits.ppred_busy, issue_slots[5].out_uop.ppred_busy connect issue_slots[4].in_uop.bits.prs3_busy, issue_slots[5].out_uop.prs3_busy connect issue_slots[4].in_uop.bits.prs2_busy, issue_slots[5].out_uop.prs2_busy connect issue_slots[4].in_uop.bits.prs1_busy, issue_slots[5].out_uop.prs1_busy connect issue_slots[4].in_uop.bits.ppred, issue_slots[5].out_uop.ppred connect issue_slots[4].in_uop.bits.prs3, issue_slots[5].out_uop.prs3 connect issue_slots[4].in_uop.bits.prs2, issue_slots[5].out_uop.prs2 connect issue_slots[4].in_uop.bits.prs1, issue_slots[5].out_uop.prs1 connect issue_slots[4].in_uop.bits.pdst, issue_slots[5].out_uop.pdst connect issue_slots[4].in_uop.bits.rxq_idx, issue_slots[5].out_uop.rxq_idx connect issue_slots[4].in_uop.bits.stq_idx, issue_slots[5].out_uop.stq_idx connect issue_slots[4].in_uop.bits.ldq_idx, issue_slots[5].out_uop.ldq_idx connect issue_slots[4].in_uop.bits.rob_idx, issue_slots[5].out_uop.rob_idx connect issue_slots[4].in_uop.bits.fp_ctrl.vec, issue_slots[5].out_uop.fp_ctrl.vec connect issue_slots[4].in_uop.bits.fp_ctrl.wflags, issue_slots[5].out_uop.fp_ctrl.wflags connect issue_slots[4].in_uop.bits.fp_ctrl.sqrt, issue_slots[5].out_uop.fp_ctrl.sqrt connect issue_slots[4].in_uop.bits.fp_ctrl.div, issue_slots[5].out_uop.fp_ctrl.div connect issue_slots[4].in_uop.bits.fp_ctrl.fma, issue_slots[5].out_uop.fp_ctrl.fma connect issue_slots[4].in_uop.bits.fp_ctrl.fastpipe, issue_slots[5].out_uop.fp_ctrl.fastpipe connect issue_slots[4].in_uop.bits.fp_ctrl.toint, issue_slots[5].out_uop.fp_ctrl.toint connect issue_slots[4].in_uop.bits.fp_ctrl.fromint, issue_slots[5].out_uop.fp_ctrl.fromint connect issue_slots[4].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[5].out_uop.fp_ctrl.typeTagOut connect issue_slots[4].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[5].out_uop.fp_ctrl.typeTagIn connect issue_slots[4].in_uop.bits.fp_ctrl.swap23, issue_slots[5].out_uop.fp_ctrl.swap23 connect issue_slots[4].in_uop.bits.fp_ctrl.swap12, issue_slots[5].out_uop.fp_ctrl.swap12 connect issue_slots[4].in_uop.bits.fp_ctrl.ren3, issue_slots[5].out_uop.fp_ctrl.ren3 connect issue_slots[4].in_uop.bits.fp_ctrl.ren2, issue_slots[5].out_uop.fp_ctrl.ren2 connect issue_slots[4].in_uop.bits.fp_ctrl.ren1, issue_slots[5].out_uop.fp_ctrl.ren1 connect issue_slots[4].in_uop.bits.fp_ctrl.wen, issue_slots[5].out_uop.fp_ctrl.wen connect issue_slots[4].in_uop.bits.fp_ctrl.ldst, issue_slots[5].out_uop.fp_ctrl.ldst connect issue_slots[4].in_uop.bits.op2_sel, issue_slots[5].out_uop.op2_sel connect issue_slots[4].in_uop.bits.op1_sel, issue_slots[5].out_uop.op1_sel connect issue_slots[4].in_uop.bits.imm_packed, issue_slots[5].out_uop.imm_packed connect issue_slots[4].in_uop.bits.pimm, issue_slots[5].out_uop.pimm connect issue_slots[4].in_uop.bits.imm_sel, issue_slots[5].out_uop.imm_sel connect issue_slots[4].in_uop.bits.imm_rename, issue_slots[5].out_uop.imm_rename connect issue_slots[4].in_uop.bits.taken, issue_slots[5].out_uop.taken connect issue_slots[4].in_uop.bits.pc_lob, issue_slots[5].out_uop.pc_lob connect issue_slots[4].in_uop.bits.edge_inst, issue_slots[5].out_uop.edge_inst connect issue_slots[4].in_uop.bits.ftq_idx, issue_slots[5].out_uop.ftq_idx connect issue_slots[4].in_uop.bits.is_mov, issue_slots[5].out_uop.is_mov connect issue_slots[4].in_uop.bits.is_rocc, issue_slots[5].out_uop.is_rocc connect issue_slots[4].in_uop.bits.is_sys_pc2epc, issue_slots[5].out_uop.is_sys_pc2epc connect issue_slots[4].in_uop.bits.is_eret, issue_slots[5].out_uop.is_eret connect issue_slots[4].in_uop.bits.is_amo, issue_slots[5].out_uop.is_amo connect issue_slots[4].in_uop.bits.is_sfence, issue_slots[5].out_uop.is_sfence connect issue_slots[4].in_uop.bits.is_fencei, issue_slots[5].out_uop.is_fencei connect issue_slots[4].in_uop.bits.is_fence, issue_slots[5].out_uop.is_fence connect issue_slots[4].in_uop.bits.is_sfb, issue_slots[5].out_uop.is_sfb connect issue_slots[4].in_uop.bits.br_type, issue_slots[5].out_uop.br_type connect issue_slots[4].in_uop.bits.br_tag, issue_slots[5].out_uop.br_tag connect issue_slots[4].in_uop.bits.br_mask, issue_slots[5].out_uop.br_mask connect issue_slots[4].in_uop.bits.dis_col_sel, issue_slots[5].out_uop.dis_col_sel connect issue_slots[4].in_uop.bits.iw_p3_bypass_hint, issue_slots[5].out_uop.iw_p3_bypass_hint connect issue_slots[4].in_uop.bits.iw_p2_bypass_hint, issue_slots[5].out_uop.iw_p2_bypass_hint connect issue_slots[4].in_uop.bits.iw_p1_bypass_hint, issue_slots[5].out_uop.iw_p1_bypass_hint connect issue_slots[4].in_uop.bits.iw_p2_speculative_child, issue_slots[5].out_uop.iw_p2_speculative_child connect issue_slots[4].in_uop.bits.iw_p1_speculative_child, issue_slots[5].out_uop.iw_p1_speculative_child connect issue_slots[4].in_uop.bits.iw_issued_partial_dgen, issue_slots[5].out_uop.iw_issued_partial_dgen connect issue_slots[4].in_uop.bits.iw_issued_partial_agen, issue_slots[5].out_uop.iw_issued_partial_agen connect issue_slots[4].in_uop.bits.iw_issued, issue_slots[5].out_uop.iw_issued connect issue_slots[4].in_uop.bits.fu_code[0], issue_slots[5].out_uop.fu_code[0] connect issue_slots[4].in_uop.bits.fu_code[1], issue_slots[5].out_uop.fu_code[1] connect issue_slots[4].in_uop.bits.fu_code[2], issue_slots[5].out_uop.fu_code[2] connect issue_slots[4].in_uop.bits.fu_code[3], issue_slots[5].out_uop.fu_code[3] connect issue_slots[4].in_uop.bits.fu_code[4], issue_slots[5].out_uop.fu_code[4] connect issue_slots[4].in_uop.bits.fu_code[5], issue_slots[5].out_uop.fu_code[5] connect issue_slots[4].in_uop.bits.fu_code[6], issue_slots[5].out_uop.fu_code[6] connect issue_slots[4].in_uop.bits.fu_code[7], issue_slots[5].out_uop.fu_code[7] connect issue_slots[4].in_uop.bits.fu_code[8], issue_slots[5].out_uop.fu_code[8] connect issue_slots[4].in_uop.bits.fu_code[9], issue_slots[5].out_uop.fu_code[9] connect issue_slots[4].in_uop.bits.iq_type[0], issue_slots[5].out_uop.iq_type[0] connect issue_slots[4].in_uop.bits.iq_type[1], issue_slots[5].out_uop.iq_type[1] connect issue_slots[4].in_uop.bits.iq_type[2], issue_slots[5].out_uop.iq_type[2] connect issue_slots[4].in_uop.bits.iq_type[3], issue_slots[5].out_uop.iq_type[3] connect issue_slots[4].in_uop.bits.debug_pc, issue_slots[5].out_uop.debug_pc connect issue_slots[4].in_uop.bits.is_rvc, issue_slots[5].out_uop.is_rvc connect issue_slots[4].in_uop.bits.debug_inst, issue_slots[5].out_uop.debug_inst connect issue_slots[4].in_uop.bits.inst, issue_slots[5].out_uop.inst node _T_290 = eq(shamts_oh[6], UInt<2>(0h2)) when _T_290 : connect issue_slots[4].in_uop.valid, issue_slots[6].will_be_valid connect issue_slots[4].in_uop.bits.debug_tsrc, issue_slots[6].out_uop.debug_tsrc connect issue_slots[4].in_uop.bits.debug_fsrc, issue_slots[6].out_uop.debug_fsrc connect issue_slots[4].in_uop.bits.bp_xcpt_if, issue_slots[6].out_uop.bp_xcpt_if connect issue_slots[4].in_uop.bits.bp_debug_if, issue_slots[6].out_uop.bp_debug_if connect issue_slots[4].in_uop.bits.xcpt_ma_if, issue_slots[6].out_uop.xcpt_ma_if connect issue_slots[4].in_uop.bits.xcpt_ae_if, issue_slots[6].out_uop.xcpt_ae_if connect issue_slots[4].in_uop.bits.xcpt_pf_if, issue_slots[6].out_uop.xcpt_pf_if connect issue_slots[4].in_uop.bits.fp_typ, issue_slots[6].out_uop.fp_typ connect issue_slots[4].in_uop.bits.fp_rm, issue_slots[6].out_uop.fp_rm connect issue_slots[4].in_uop.bits.fp_val, issue_slots[6].out_uop.fp_val connect issue_slots[4].in_uop.bits.fcn_op, issue_slots[6].out_uop.fcn_op connect issue_slots[4].in_uop.bits.fcn_dw, issue_slots[6].out_uop.fcn_dw connect issue_slots[4].in_uop.bits.frs3_en, issue_slots[6].out_uop.frs3_en connect issue_slots[4].in_uop.bits.lrs2_rtype, issue_slots[6].out_uop.lrs2_rtype connect issue_slots[4].in_uop.bits.lrs1_rtype, issue_slots[6].out_uop.lrs1_rtype connect issue_slots[4].in_uop.bits.dst_rtype, issue_slots[6].out_uop.dst_rtype connect issue_slots[4].in_uop.bits.lrs3, issue_slots[6].out_uop.lrs3 connect issue_slots[4].in_uop.bits.lrs2, issue_slots[6].out_uop.lrs2 connect issue_slots[4].in_uop.bits.lrs1, issue_slots[6].out_uop.lrs1 connect issue_slots[4].in_uop.bits.ldst, issue_slots[6].out_uop.ldst connect issue_slots[4].in_uop.bits.ldst_is_rs1, issue_slots[6].out_uop.ldst_is_rs1 connect issue_slots[4].in_uop.bits.csr_cmd, issue_slots[6].out_uop.csr_cmd connect issue_slots[4].in_uop.bits.flush_on_commit, issue_slots[6].out_uop.flush_on_commit connect issue_slots[4].in_uop.bits.is_unique, issue_slots[6].out_uop.is_unique connect issue_slots[4].in_uop.bits.uses_stq, issue_slots[6].out_uop.uses_stq connect issue_slots[4].in_uop.bits.uses_ldq, issue_slots[6].out_uop.uses_ldq connect issue_slots[4].in_uop.bits.mem_signed, issue_slots[6].out_uop.mem_signed connect issue_slots[4].in_uop.bits.mem_size, issue_slots[6].out_uop.mem_size connect issue_slots[4].in_uop.bits.mem_cmd, issue_slots[6].out_uop.mem_cmd connect issue_slots[4].in_uop.bits.exc_cause, issue_slots[6].out_uop.exc_cause connect issue_slots[4].in_uop.bits.exception, issue_slots[6].out_uop.exception connect issue_slots[4].in_uop.bits.stale_pdst, issue_slots[6].out_uop.stale_pdst connect issue_slots[4].in_uop.bits.ppred_busy, issue_slots[6].out_uop.ppred_busy connect issue_slots[4].in_uop.bits.prs3_busy, issue_slots[6].out_uop.prs3_busy connect issue_slots[4].in_uop.bits.prs2_busy, issue_slots[6].out_uop.prs2_busy connect issue_slots[4].in_uop.bits.prs1_busy, issue_slots[6].out_uop.prs1_busy connect issue_slots[4].in_uop.bits.ppred, issue_slots[6].out_uop.ppred connect issue_slots[4].in_uop.bits.prs3, issue_slots[6].out_uop.prs3 connect issue_slots[4].in_uop.bits.prs2, issue_slots[6].out_uop.prs2 connect issue_slots[4].in_uop.bits.prs1, issue_slots[6].out_uop.prs1 connect issue_slots[4].in_uop.bits.pdst, issue_slots[6].out_uop.pdst connect issue_slots[4].in_uop.bits.rxq_idx, issue_slots[6].out_uop.rxq_idx connect issue_slots[4].in_uop.bits.stq_idx, issue_slots[6].out_uop.stq_idx connect issue_slots[4].in_uop.bits.ldq_idx, issue_slots[6].out_uop.ldq_idx connect issue_slots[4].in_uop.bits.rob_idx, issue_slots[6].out_uop.rob_idx connect issue_slots[4].in_uop.bits.fp_ctrl.vec, issue_slots[6].out_uop.fp_ctrl.vec connect issue_slots[4].in_uop.bits.fp_ctrl.wflags, issue_slots[6].out_uop.fp_ctrl.wflags connect issue_slots[4].in_uop.bits.fp_ctrl.sqrt, issue_slots[6].out_uop.fp_ctrl.sqrt connect issue_slots[4].in_uop.bits.fp_ctrl.div, issue_slots[6].out_uop.fp_ctrl.div connect issue_slots[4].in_uop.bits.fp_ctrl.fma, issue_slots[6].out_uop.fp_ctrl.fma connect issue_slots[4].in_uop.bits.fp_ctrl.fastpipe, issue_slots[6].out_uop.fp_ctrl.fastpipe connect issue_slots[4].in_uop.bits.fp_ctrl.toint, issue_slots[6].out_uop.fp_ctrl.toint connect issue_slots[4].in_uop.bits.fp_ctrl.fromint, issue_slots[6].out_uop.fp_ctrl.fromint connect issue_slots[4].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[6].out_uop.fp_ctrl.typeTagOut connect issue_slots[4].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[6].out_uop.fp_ctrl.typeTagIn connect issue_slots[4].in_uop.bits.fp_ctrl.swap23, issue_slots[6].out_uop.fp_ctrl.swap23 connect issue_slots[4].in_uop.bits.fp_ctrl.swap12, issue_slots[6].out_uop.fp_ctrl.swap12 connect issue_slots[4].in_uop.bits.fp_ctrl.ren3, issue_slots[6].out_uop.fp_ctrl.ren3 connect issue_slots[4].in_uop.bits.fp_ctrl.ren2, issue_slots[6].out_uop.fp_ctrl.ren2 connect issue_slots[4].in_uop.bits.fp_ctrl.ren1, issue_slots[6].out_uop.fp_ctrl.ren1 connect issue_slots[4].in_uop.bits.fp_ctrl.wen, issue_slots[6].out_uop.fp_ctrl.wen connect issue_slots[4].in_uop.bits.fp_ctrl.ldst, issue_slots[6].out_uop.fp_ctrl.ldst connect issue_slots[4].in_uop.bits.op2_sel, issue_slots[6].out_uop.op2_sel connect issue_slots[4].in_uop.bits.op1_sel, issue_slots[6].out_uop.op1_sel connect issue_slots[4].in_uop.bits.imm_packed, issue_slots[6].out_uop.imm_packed connect issue_slots[4].in_uop.bits.pimm, issue_slots[6].out_uop.pimm connect issue_slots[4].in_uop.bits.imm_sel, issue_slots[6].out_uop.imm_sel connect issue_slots[4].in_uop.bits.imm_rename, issue_slots[6].out_uop.imm_rename connect issue_slots[4].in_uop.bits.taken, issue_slots[6].out_uop.taken connect issue_slots[4].in_uop.bits.pc_lob, issue_slots[6].out_uop.pc_lob connect issue_slots[4].in_uop.bits.edge_inst, issue_slots[6].out_uop.edge_inst connect issue_slots[4].in_uop.bits.ftq_idx, issue_slots[6].out_uop.ftq_idx connect issue_slots[4].in_uop.bits.is_mov, issue_slots[6].out_uop.is_mov connect issue_slots[4].in_uop.bits.is_rocc, issue_slots[6].out_uop.is_rocc connect issue_slots[4].in_uop.bits.is_sys_pc2epc, issue_slots[6].out_uop.is_sys_pc2epc connect issue_slots[4].in_uop.bits.is_eret, issue_slots[6].out_uop.is_eret connect issue_slots[4].in_uop.bits.is_amo, issue_slots[6].out_uop.is_amo connect issue_slots[4].in_uop.bits.is_sfence, issue_slots[6].out_uop.is_sfence connect issue_slots[4].in_uop.bits.is_fencei, issue_slots[6].out_uop.is_fencei connect issue_slots[4].in_uop.bits.is_fence, issue_slots[6].out_uop.is_fence connect issue_slots[4].in_uop.bits.is_sfb, issue_slots[6].out_uop.is_sfb connect issue_slots[4].in_uop.bits.br_type, issue_slots[6].out_uop.br_type connect issue_slots[4].in_uop.bits.br_tag, issue_slots[6].out_uop.br_tag connect issue_slots[4].in_uop.bits.br_mask, issue_slots[6].out_uop.br_mask connect issue_slots[4].in_uop.bits.dis_col_sel, issue_slots[6].out_uop.dis_col_sel connect issue_slots[4].in_uop.bits.iw_p3_bypass_hint, issue_slots[6].out_uop.iw_p3_bypass_hint connect issue_slots[4].in_uop.bits.iw_p2_bypass_hint, issue_slots[6].out_uop.iw_p2_bypass_hint connect issue_slots[4].in_uop.bits.iw_p1_bypass_hint, issue_slots[6].out_uop.iw_p1_bypass_hint connect issue_slots[4].in_uop.bits.iw_p2_speculative_child, issue_slots[6].out_uop.iw_p2_speculative_child connect issue_slots[4].in_uop.bits.iw_p1_speculative_child, issue_slots[6].out_uop.iw_p1_speculative_child connect issue_slots[4].in_uop.bits.iw_issued_partial_dgen, issue_slots[6].out_uop.iw_issued_partial_dgen connect issue_slots[4].in_uop.bits.iw_issued_partial_agen, issue_slots[6].out_uop.iw_issued_partial_agen connect issue_slots[4].in_uop.bits.iw_issued, issue_slots[6].out_uop.iw_issued connect issue_slots[4].in_uop.bits.fu_code[0], issue_slots[6].out_uop.fu_code[0] connect issue_slots[4].in_uop.bits.fu_code[1], issue_slots[6].out_uop.fu_code[1] connect issue_slots[4].in_uop.bits.fu_code[2], issue_slots[6].out_uop.fu_code[2] connect issue_slots[4].in_uop.bits.fu_code[3], issue_slots[6].out_uop.fu_code[3] connect issue_slots[4].in_uop.bits.fu_code[4], issue_slots[6].out_uop.fu_code[4] connect issue_slots[4].in_uop.bits.fu_code[5], issue_slots[6].out_uop.fu_code[5] connect issue_slots[4].in_uop.bits.fu_code[6], issue_slots[6].out_uop.fu_code[6] connect issue_slots[4].in_uop.bits.fu_code[7], issue_slots[6].out_uop.fu_code[7] connect issue_slots[4].in_uop.bits.fu_code[8], issue_slots[6].out_uop.fu_code[8] connect issue_slots[4].in_uop.bits.fu_code[9], issue_slots[6].out_uop.fu_code[9] connect issue_slots[4].in_uop.bits.iq_type[0], issue_slots[6].out_uop.iq_type[0] connect issue_slots[4].in_uop.bits.iq_type[1], issue_slots[6].out_uop.iq_type[1] connect issue_slots[4].in_uop.bits.iq_type[2], issue_slots[6].out_uop.iq_type[2] connect issue_slots[4].in_uop.bits.iq_type[3], issue_slots[6].out_uop.iq_type[3] connect issue_slots[4].in_uop.bits.debug_pc, issue_slots[6].out_uop.debug_pc connect issue_slots[4].in_uop.bits.is_rvc, issue_slots[6].out_uop.is_rvc connect issue_slots[4].in_uop.bits.debug_inst, issue_slots[6].out_uop.debug_inst connect issue_slots[4].in_uop.bits.inst, issue_slots[6].out_uop.inst node _T_291 = eq(shamts_oh[7], UInt<3>(0h4)) when _T_291 : connect issue_slots[4].in_uop.valid, issue_slots[7].will_be_valid connect issue_slots[4].in_uop.bits.debug_tsrc, issue_slots[7].out_uop.debug_tsrc connect issue_slots[4].in_uop.bits.debug_fsrc, issue_slots[7].out_uop.debug_fsrc connect issue_slots[4].in_uop.bits.bp_xcpt_if, issue_slots[7].out_uop.bp_xcpt_if connect issue_slots[4].in_uop.bits.bp_debug_if, issue_slots[7].out_uop.bp_debug_if connect issue_slots[4].in_uop.bits.xcpt_ma_if, issue_slots[7].out_uop.xcpt_ma_if connect issue_slots[4].in_uop.bits.xcpt_ae_if, issue_slots[7].out_uop.xcpt_ae_if connect issue_slots[4].in_uop.bits.xcpt_pf_if, issue_slots[7].out_uop.xcpt_pf_if connect issue_slots[4].in_uop.bits.fp_typ, issue_slots[7].out_uop.fp_typ connect issue_slots[4].in_uop.bits.fp_rm, issue_slots[7].out_uop.fp_rm connect issue_slots[4].in_uop.bits.fp_val, issue_slots[7].out_uop.fp_val connect issue_slots[4].in_uop.bits.fcn_op, issue_slots[7].out_uop.fcn_op connect issue_slots[4].in_uop.bits.fcn_dw, issue_slots[7].out_uop.fcn_dw connect issue_slots[4].in_uop.bits.frs3_en, issue_slots[7].out_uop.frs3_en connect issue_slots[4].in_uop.bits.lrs2_rtype, issue_slots[7].out_uop.lrs2_rtype connect issue_slots[4].in_uop.bits.lrs1_rtype, issue_slots[7].out_uop.lrs1_rtype connect issue_slots[4].in_uop.bits.dst_rtype, issue_slots[7].out_uop.dst_rtype connect issue_slots[4].in_uop.bits.lrs3, issue_slots[7].out_uop.lrs3 connect issue_slots[4].in_uop.bits.lrs2, issue_slots[7].out_uop.lrs2 connect issue_slots[4].in_uop.bits.lrs1, issue_slots[7].out_uop.lrs1 connect issue_slots[4].in_uop.bits.ldst, issue_slots[7].out_uop.ldst connect issue_slots[4].in_uop.bits.ldst_is_rs1, issue_slots[7].out_uop.ldst_is_rs1 connect issue_slots[4].in_uop.bits.csr_cmd, issue_slots[7].out_uop.csr_cmd connect issue_slots[4].in_uop.bits.flush_on_commit, issue_slots[7].out_uop.flush_on_commit connect issue_slots[4].in_uop.bits.is_unique, issue_slots[7].out_uop.is_unique connect issue_slots[4].in_uop.bits.uses_stq, issue_slots[7].out_uop.uses_stq connect issue_slots[4].in_uop.bits.uses_ldq, issue_slots[7].out_uop.uses_ldq connect issue_slots[4].in_uop.bits.mem_signed, issue_slots[7].out_uop.mem_signed connect issue_slots[4].in_uop.bits.mem_size, issue_slots[7].out_uop.mem_size connect issue_slots[4].in_uop.bits.mem_cmd, issue_slots[7].out_uop.mem_cmd connect issue_slots[4].in_uop.bits.exc_cause, issue_slots[7].out_uop.exc_cause connect issue_slots[4].in_uop.bits.exception, issue_slots[7].out_uop.exception connect issue_slots[4].in_uop.bits.stale_pdst, issue_slots[7].out_uop.stale_pdst connect issue_slots[4].in_uop.bits.ppred_busy, issue_slots[7].out_uop.ppred_busy connect issue_slots[4].in_uop.bits.prs3_busy, issue_slots[7].out_uop.prs3_busy connect issue_slots[4].in_uop.bits.prs2_busy, issue_slots[7].out_uop.prs2_busy connect issue_slots[4].in_uop.bits.prs1_busy, issue_slots[7].out_uop.prs1_busy connect issue_slots[4].in_uop.bits.ppred, issue_slots[7].out_uop.ppred connect issue_slots[4].in_uop.bits.prs3, issue_slots[7].out_uop.prs3 connect issue_slots[4].in_uop.bits.prs2, issue_slots[7].out_uop.prs2 connect issue_slots[4].in_uop.bits.prs1, issue_slots[7].out_uop.prs1 connect issue_slots[4].in_uop.bits.pdst, issue_slots[7].out_uop.pdst connect issue_slots[4].in_uop.bits.rxq_idx, issue_slots[7].out_uop.rxq_idx connect issue_slots[4].in_uop.bits.stq_idx, issue_slots[7].out_uop.stq_idx connect issue_slots[4].in_uop.bits.ldq_idx, issue_slots[7].out_uop.ldq_idx connect issue_slots[4].in_uop.bits.rob_idx, issue_slots[7].out_uop.rob_idx connect issue_slots[4].in_uop.bits.fp_ctrl.vec, issue_slots[7].out_uop.fp_ctrl.vec connect issue_slots[4].in_uop.bits.fp_ctrl.wflags, issue_slots[7].out_uop.fp_ctrl.wflags connect issue_slots[4].in_uop.bits.fp_ctrl.sqrt, issue_slots[7].out_uop.fp_ctrl.sqrt connect issue_slots[4].in_uop.bits.fp_ctrl.div, issue_slots[7].out_uop.fp_ctrl.div connect issue_slots[4].in_uop.bits.fp_ctrl.fma, issue_slots[7].out_uop.fp_ctrl.fma connect issue_slots[4].in_uop.bits.fp_ctrl.fastpipe, issue_slots[7].out_uop.fp_ctrl.fastpipe connect issue_slots[4].in_uop.bits.fp_ctrl.toint, issue_slots[7].out_uop.fp_ctrl.toint connect issue_slots[4].in_uop.bits.fp_ctrl.fromint, issue_slots[7].out_uop.fp_ctrl.fromint connect issue_slots[4].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[7].out_uop.fp_ctrl.typeTagOut connect issue_slots[4].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[7].out_uop.fp_ctrl.typeTagIn connect issue_slots[4].in_uop.bits.fp_ctrl.swap23, issue_slots[7].out_uop.fp_ctrl.swap23 connect issue_slots[4].in_uop.bits.fp_ctrl.swap12, issue_slots[7].out_uop.fp_ctrl.swap12 connect issue_slots[4].in_uop.bits.fp_ctrl.ren3, issue_slots[7].out_uop.fp_ctrl.ren3 connect issue_slots[4].in_uop.bits.fp_ctrl.ren2, issue_slots[7].out_uop.fp_ctrl.ren2 connect issue_slots[4].in_uop.bits.fp_ctrl.ren1, issue_slots[7].out_uop.fp_ctrl.ren1 connect issue_slots[4].in_uop.bits.fp_ctrl.wen, issue_slots[7].out_uop.fp_ctrl.wen connect issue_slots[4].in_uop.bits.fp_ctrl.ldst, issue_slots[7].out_uop.fp_ctrl.ldst connect issue_slots[4].in_uop.bits.op2_sel, issue_slots[7].out_uop.op2_sel connect issue_slots[4].in_uop.bits.op1_sel, issue_slots[7].out_uop.op1_sel connect issue_slots[4].in_uop.bits.imm_packed, issue_slots[7].out_uop.imm_packed connect issue_slots[4].in_uop.bits.pimm, issue_slots[7].out_uop.pimm connect issue_slots[4].in_uop.bits.imm_sel, issue_slots[7].out_uop.imm_sel connect issue_slots[4].in_uop.bits.imm_rename, issue_slots[7].out_uop.imm_rename connect issue_slots[4].in_uop.bits.taken, issue_slots[7].out_uop.taken connect issue_slots[4].in_uop.bits.pc_lob, issue_slots[7].out_uop.pc_lob connect issue_slots[4].in_uop.bits.edge_inst, issue_slots[7].out_uop.edge_inst connect issue_slots[4].in_uop.bits.ftq_idx, issue_slots[7].out_uop.ftq_idx connect issue_slots[4].in_uop.bits.is_mov, issue_slots[7].out_uop.is_mov connect issue_slots[4].in_uop.bits.is_rocc, issue_slots[7].out_uop.is_rocc connect issue_slots[4].in_uop.bits.is_sys_pc2epc, issue_slots[7].out_uop.is_sys_pc2epc connect issue_slots[4].in_uop.bits.is_eret, issue_slots[7].out_uop.is_eret connect issue_slots[4].in_uop.bits.is_amo, issue_slots[7].out_uop.is_amo connect issue_slots[4].in_uop.bits.is_sfence, issue_slots[7].out_uop.is_sfence connect issue_slots[4].in_uop.bits.is_fencei, issue_slots[7].out_uop.is_fencei connect issue_slots[4].in_uop.bits.is_fence, issue_slots[7].out_uop.is_fence connect issue_slots[4].in_uop.bits.is_sfb, issue_slots[7].out_uop.is_sfb connect issue_slots[4].in_uop.bits.br_type, issue_slots[7].out_uop.br_type connect issue_slots[4].in_uop.bits.br_tag, issue_slots[7].out_uop.br_tag connect issue_slots[4].in_uop.bits.br_mask, issue_slots[7].out_uop.br_mask connect issue_slots[4].in_uop.bits.dis_col_sel, issue_slots[7].out_uop.dis_col_sel connect issue_slots[4].in_uop.bits.iw_p3_bypass_hint, issue_slots[7].out_uop.iw_p3_bypass_hint connect issue_slots[4].in_uop.bits.iw_p2_bypass_hint, issue_slots[7].out_uop.iw_p2_bypass_hint connect issue_slots[4].in_uop.bits.iw_p1_bypass_hint, issue_slots[7].out_uop.iw_p1_bypass_hint connect issue_slots[4].in_uop.bits.iw_p2_speculative_child, issue_slots[7].out_uop.iw_p2_speculative_child connect issue_slots[4].in_uop.bits.iw_p1_speculative_child, issue_slots[7].out_uop.iw_p1_speculative_child connect issue_slots[4].in_uop.bits.iw_issued_partial_dgen, issue_slots[7].out_uop.iw_issued_partial_dgen connect issue_slots[4].in_uop.bits.iw_issued_partial_agen, issue_slots[7].out_uop.iw_issued_partial_agen connect issue_slots[4].in_uop.bits.iw_issued, issue_slots[7].out_uop.iw_issued connect issue_slots[4].in_uop.bits.fu_code[0], issue_slots[7].out_uop.fu_code[0] connect issue_slots[4].in_uop.bits.fu_code[1], issue_slots[7].out_uop.fu_code[1] connect issue_slots[4].in_uop.bits.fu_code[2], issue_slots[7].out_uop.fu_code[2] connect issue_slots[4].in_uop.bits.fu_code[3], issue_slots[7].out_uop.fu_code[3] connect issue_slots[4].in_uop.bits.fu_code[4], issue_slots[7].out_uop.fu_code[4] connect issue_slots[4].in_uop.bits.fu_code[5], issue_slots[7].out_uop.fu_code[5] connect issue_slots[4].in_uop.bits.fu_code[6], issue_slots[7].out_uop.fu_code[6] connect issue_slots[4].in_uop.bits.fu_code[7], issue_slots[7].out_uop.fu_code[7] connect issue_slots[4].in_uop.bits.fu_code[8], issue_slots[7].out_uop.fu_code[8] connect issue_slots[4].in_uop.bits.fu_code[9], issue_slots[7].out_uop.fu_code[9] connect issue_slots[4].in_uop.bits.iq_type[0], issue_slots[7].out_uop.iq_type[0] connect issue_slots[4].in_uop.bits.iq_type[1], issue_slots[7].out_uop.iq_type[1] connect issue_slots[4].in_uop.bits.iq_type[2], issue_slots[7].out_uop.iq_type[2] connect issue_slots[4].in_uop.bits.iq_type[3], issue_slots[7].out_uop.iq_type[3] connect issue_slots[4].in_uop.bits.debug_pc, issue_slots[7].out_uop.debug_pc connect issue_slots[4].in_uop.bits.is_rvc, issue_slots[7].out_uop.is_rvc connect issue_slots[4].in_uop.bits.debug_inst, issue_slots[7].out_uop.debug_inst connect issue_slots[4].in_uop.bits.inst, issue_slots[7].out_uop.inst node _issue_slots_4_clear_T = neq(shamts_oh[4], UInt<1>(0h0)) connect issue_slots[4].clear, _issue_slots_4_clear_T connect issue_slots[5].in_uop.valid, UInt<1>(0h0) connect issue_slots[5].in_uop.bits.debug_tsrc, issue_slots[6].out_uop.debug_tsrc connect issue_slots[5].in_uop.bits.debug_fsrc, issue_slots[6].out_uop.debug_fsrc connect issue_slots[5].in_uop.bits.bp_xcpt_if, issue_slots[6].out_uop.bp_xcpt_if connect issue_slots[5].in_uop.bits.bp_debug_if, issue_slots[6].out_uop.bp_debug_if connect issue_slots[5].in_uop.bits.xcpt_ma_if, issue_slots[6].out_uop.xcpt_ma_if connect issue_slots[5].in_uop.bits.xcpt_ae_if, issue_slots[6].out_uop.xcpt_ae_if connect issue_slots[5].in_uop.bits.xcpt_pf_if, issue_slots[6].out_uop.xcpt_pf_if connect issue_slots[5].in_uop.bits.fp_typ, issue_slots[6].out_uop.fp_typ connect issue_slots[5].in_uop.bits.fp_rm, issue_slots[6].out_uop.fp_rm connect issue_slots[5].in_uop.bits.fp_val, issue_slots[6].out_uop.fp_val connect issue_slots[5].in_uop.bits.fcn_op, issue_slots[6].out_uop.fcn_op connect issue_slots[5].in_uop.bits.fcn_dw, issue_slots[6].out_uop.fcn_dw connect issue_slots[5].in_uop.bits.frs3_en, issue_slots[6].out_uop.frs3_en connect issue_slots[5].in_uop.bits.lrs2_rtype, issue_slots[6].out_uop.lrs2_rtype connect issue_slots[5].in_uop.bits.lrs1_rtype, issue_slots[6].out_uop.lrs1_rtype connect issue_slots[5].in_uop.bits.dst_rtype, issue_slots[6].out_uop.dst_rtype connect issue_slots[5].in_uop.bits.lrs3, issue_slots[6].out_uop.lrs3 connect issue_slots[5].in_uop.bits.lrs2, issue_slots[6].out_uop.lrs2 connect issue_slots[5].in_uop.bits.lrs1, issue_slots[6].out_uop.lrs1 connect issue_slots[5].in_uop.bits.ldst, issue_slots[6].out_uop.ldst connect issue_slots[5].in_uop.bits.ldst_is_rs1, issue_slots[6].out_uop.ldst_is_rs1 connect issue_slots[5].in_uop.bits.csr_cmd, issue_slots[6].out_uop.csr_cmd connect issue_slots[5].in_uop.bits.flush_on_commit, issue_slots[6].out_uop.flush_on_commit connect issue_slots[5].in_uop.bits.is_unique, issue_slots[6].out_uop.is_unique connect issue_slots[5].in_uop.bits.uses_stq, issue_slots[6].out_uop.uses_stq connect issue_slots[5].in_uop.bits.uses_ldq, issue_slots[6].out_uop.uses_ldq connect issue_slots[5].in_uop.bits.mem_signed, issue_slots[6].out_uop.mem_signed connect issue_slots[5].in_uop.bits.mem_size, issue_slots[6].out_uop.mem_size connect issue_slots[5].in_uop.bits.mem_cmd, issue_slots[6].out_uop.mem_cmd connect issue_slots[5].in_uop.bits.exc_cause, issue_slots[6].out_uop.exc_cause connect issue_slots[5].in_uop.bits.exception, issue_slots[6].out_uop.exception connect issue_slots[5].in_uop.bits.stale_pdst, issue_slots[6].out_uop.stale_pdst connect issue_slots[5].in_uop.bits.ppred_busy, issue_slots[6].out_uop.ppred_busy connect issue_slots[5].in_uop.bits.prs3_busy, issue_slots[6].out_uop.prs3_busy connect issue_slots[5].in_uop.bits.prs2_busy, issue_slots[6].out_uop.prs2_busy connect issue_slots[5].in_uop.bits.prs1_busy, issue_slots[6].out_uop.prs1_busy connect issue_slots[5].in_uop.bits.ppred, issue_slots[6].out_uop.ppred connect issue_slots[5].in_uop.bits.prs3, issue_slots[6].out_uop.prs3 connect issue_slots[5].in_uop.bits.prs2, issue_slots[6].out_uop.prs2 connect issue_slots[5].in_uop.bits.prs1, issue_slots[6].out_uop.prs1 connect issue_slots[5].in_uop.bits.pdst, issue_slots[6].out_uop.pdst connect issue_slots[5].in_uop.bits.rxq_idx, issue_slots[6].out_uop.rxq_idx connect issue_slots[5].in_uop.bits.stq_idx, issue_slots[6].out_uop.stq_idx connect issue_slots[5].in_uop.bits.ldq_idx, issue_slots[6].out_uop.ldq_idx connect issue_slots[5].in_uop.bits.rob_idx, issue_slots[6].out_uop.rob_idx connect issue_slots[5].in_uop.bits.fp_ctrl.vec, issue_slots[6].out_uop.fp_ctrl.vec connect issue_slots[5].in_uop.bits.fp_ctrl.wflags, issue_slots[6].out_uop.fp_ctrl.wflags connect issue_slots[5].in_uop.bits.fp_ctrl.sqrt, issue_slots[6].out_uop.fp_ctrl.sqrt connect issue_slots[5].in_uop.bits.fp_ctrl.div, issue_slots[6].out_uop.fp_ctrl.div connect issue_slots[5].in_uop.bits.fp_ctrl.fma, issue_slots[6].out_uop.fp_ctrl.fma connect issue_slots[5].in_uop.bits.fp_ctrl.fastpipe, issue_slots[6].out_uop.fp_ctrl.fastpipe connect issue_slots[5].in_uop.bits.fp_ctrl.toint, issue_slots[6].out_uop.fp_ctrl.toint connect issue_slots[5].in_uop.bits.fp_ctrl.fromint, issue_slots[6].out_uop.fp_ctrl.fromint connect issue_slots[5].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[6].out_uop.fp_ctrl.typeTagOut connect issue_slots[5].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[6].out_uop.fp_ctrl.typeTagIn connect issue_slots[5].in_uop.bits.fp_ctrl.swap23, issue_slots[6].out_uop.fp_ctrl.swap23 connect issue_slots[5].in_uop.bits.fp_ctrl.swap12, issue_slots[6].out_uop.fp_ctrl.swap12 connect issue_slots[5].in_uop.bits.fp_ctrl.ren3, issue_slots[6].out_uop.fp_ctrl.ren3 connect issue_slots[5].in_uop.bits.fp_ctrl.ren2, issue_slots[6].out_uop.fp_ctrl.ren2 connect issue_slots[5].in_uop.bits.fp_ctrl.ren1, issue_slots[6].out_uop.fp_ctrl.ren1 connect issue_slots[5].in_uop.bits.fp_ctrl.wen, issue_slots[6].out_uop.fp_ctrl.wen connect issue_slots[5].in_uop.bits.fp_ctrl.ldst, issue_slots[6].out_uop.fp_ctrl.ldst connect issue_slots[5].in_uop.bits.op2_sel, issue_slots[6].out_uop.op2_sel connect issue_slots[5].in_uop.bits.op1_sel, issue_slots[6].out_uop.op1_sel connect issue_slots[5].in_uop.bits.imm_packed, issue_slots[6].out_uop.imm_packed connect issue_slots[5].in_uop.bits.pimm, issue_slots[6].out_uop.pimm connect issue_slots[5].in_uop.bits.imm_sel, issue_slots[6].out_uop.imm_sel connect issue_slots[5].in_uop.bits.imm_rename, issue_slots[6].out_uop.imm_rename connect issue_slots[5].in_uop.bits.taken, issue_slots[6].out_uop.taken connect issue_slots[5].in_uop.bits.pc_lob, issue_slots[6].out_uop.pc_lob connect issue_slots[5].in_uop.bits.edge_inst, issue_slots[6].out_uop.edge_inst connect issue_slots[5].in_uop.bits.ftq_idx, issue_slots[6].out_uop.ftq_idx connect issue_slots[5].in_uop.bits.is_mov, issue_slots[6].out_uop.is_mov connect issue_slots[5].in_uop.bits.is_rocc, issue_slots[6].out_uop.is_rocc connect issue_slots[5].in_uop.bits.is_sys_pc2epc, issue_slots[6].out_uop.is_sys_pc2epc connect issue_slots[5].in_uop.bits.is_eret, issue_slots[6].out_uop.is_eret connect issue_slots[5].in_uop.bits.is_amo, issue_slots[6].out_uop.is_amo connect issue_slots[5].in_uop.bits.is_sfence, issue_slots[6].out_uop.is_sfence connect issue_slots[5].in_uop.bits.is_fencei, issue_slots[6].out_uop.is_fencei connect issue_slots[5].in_uop.bits.is_fence, issue_slots[6].out_uop.is_fence connect issue_slots[5].in_uop.bits.is_sfb, issue_slots[6].out_uop.is_sfb connect issue_slots[5].in_uop.bits.br_type, issue_slots[6].out_uop.br_type connect issue_slots[5].in_uop.bits.br_tag, issue_slots[6].out_uop.br_tag connect issue_slots[5].in_uop.bits.br_mask, issue_slots[6].out_uop.br_mask connect issue_slots[5].in_uop.bits.dis_col_sel, issue_slots[6].out_uop.dis_col_sel connect issue_slots[5].in_uop.bits.iw_p3_bypass_hint, issue_slots[6].out_uop.iw_p3_bypass_hint connect issue_slots[5].in_uop.bits.iw_p2_bypass_hint, issue_slots[6].out_uop.iw_p2_bypass_hint connect issue_slots[5].in_uop.bits.iw_p1_bypass_hint, issue_slots[6].out_uop.iw_p1_bypass_hint connect issue_slots[5].in_uop.bits.iw_p2_speculative_child, issue_slots[6].out_uop.iw_p2_speculative_child connect issue_slots[5].in_uop.bits.iw_p1_speculative_child, issue_slots[6].out_uop.iw_p1_speculative_child connect issue_slots[5].in_uop.bits.iw_issued_partial_dgen, issue_slots[6].out_uop.iw_issued_partial_dgen connect issue_slots[5].in_uop.bits.iw_issued_partial_agen, issue_slots[6].out_uop.iw_issued_partial_agen connect issue_slots[5].in_uop.bits.iw_issued, issue_slots[6].out_uop.iw_issued connect issue_slots[5].in_uop.bits.fu_code[0], issue_slots[6].out_uop.fu_code[0] connect issue_slots[5].in_uop.bits.fu_code[1], issue_slots[6].out_uop.fu_code[1] connect issue_slots[5].in_uop.bits.fu_code[2], issue_slots[6].out_uop.fu_code[2] connect issue_slots[5].in_uop.bits.fu_code[3], issue_slots[6].out_uop.fu_code[3] connect issue_slots[5].in_uop.bits.fu_code[4], issue_slots[6].out_uop.fu_code[4] connect issue_slots[5].in_uop.bits.fu_code[5], issue_slots[6].out_uop.fu_code[5] connect issue_slots[5].in_uop.bits.fu_code[6], issue_slots[6].out_uop.fu_code[6] connect issue_slots[5].in_uop.bits.fu_code[7], issue_slots[6].out_uop.fu_code[7] connect issue_slots[5].in_uop.bits.fu_code[8], issue_slots[6].out_uop.fu_code[8] connect issue_slots[5].in_uop.bits.fu_code[9], issue_slots[6].out_uop.fu_code[9] connect issue_slots[5].in_uop.bits.iq_type[0], issue_slots[6].out_uop.iq_type[0] connect issue_slots[5].in_uop.bits.iq_type[1], issue_slots[6].out_uop.iq_type[1] connect issue_slots[5].in_uop.bits.iq_type[2], issue_slots[6].out_uop.iq_type[2] connect issue_slots[5].in_uop.bits.iq_type[3], issue_slots[6].out_uop.iq_type[3] connect issue_slots[5].in_uop.bits.debug_pc, issue_slots[6].out_uop.debug_pc connect issue_slots[5].in_uop.bits.is_rvc, issue_slots[6].out_uop.is_rvc connect issue_slots[5].in_uop.bits.debug_inst, issue_slots[6].out_uop.debug_inst connect issue_slots[5].in_uop.bits.inst, issue_slots[6].out_uop.inst node _T_292 = eq(shamts_oh[6], UInt<1>(0h1)) when _T_292 : connect issue_slots[5].in_uop.valid, issue_slots[6].will_be_valid connect issue_slots[5].in_uop.bits.debug_tsrc, issue_slots[6].out_uop.debug_tsrc connect issue_slots[5].in_uop.bits.debug_fsrc, issue_slots[6].out_uop.debug_fsrc connect issue_slots[5].in_uop.bits.bp_xcpt_if, issue_slots[6].out_uop.bp_xcpt_if connect issue_slots[5].in_uop.bits.bp_debug_if, issue_slots[6].out_uop.bp_debug_if connect issue_slots[5].in_uop.bits.xcpt_ma_if, issue_slots[6].out_uop.xcpt_ma_if connect issue_slots[5].in_uop.bits.xcpt_ae_if, issue_slots[6].out_uop.xcpt_ae_if connect issue_slots[5].in_uop.bits.xcpt_pf_if, issue_slots[6].out_uop.xcpt_pf_if connect issue_slots[5].in_uop.bits.fp_typ, issue_slots[6].out_uop.fp_typ connect issue_slots[5].in_uop.bits.fp_rm, issue_slots[6].out_uop.fp_rm connect issue_slots[5].in_uop.bits.fp_val, issue_slots[6].out_uop.fp_val connect issue_slots[5].in_uop.bits.fcn_op, issue_slots[6].out_uop.fcn_op connect issue_slots[5].in_uop.bits.fcn_dw, issue_slots[6].out_uop.fcn_dw connect issue_slots[5].in_uop.bits.frs3_en, issue_slots[6].out_uop.frs3_en connect issue_slots[5].in_uop.bits.lrs2_rtype, issue_slots[6].out_uop.lrs2_rtype connect issue_slots[5].in_uop.bits.lrs1_rtype, issue_slots[6].out_uop.lrs1_rtype connect issue_slots[5].in_uop.bits.dst_rtype, issue_slots[6].out_uop.dst_rtype connect issue_slots[5].in_uop.bits.lrs3, issue_slots[6].out_uop.lrs3 connect issue_slots[5].in_uop.bits.lrs2, issue_slots[6].out_uop.lrs2 connect issue_slots[5].in_uop.bits.lrs1, issue_slots[6].out_uop.lrs1 connect issue_slots[5].in_uop.bits.ldst, issue_slots[6].out_uop.ldst connect issue_slots[5].in_uop.bits.ldst_is_rs1, issue_slots[6].out_uop.ldst_is_rs1 connect issue_slots[5].in_uop.bits.csr_cmd, issue_slots[6].out_uop.csr_cmd connect issue_slots[5].in_uop.bits.flush_on_commit, issue_slots[6].out_uop.flush_on_commit connect issue_slots[5].in_uop.bits.is_unique, issue_slots[6].out_uop.is_unique connect issue_slots[5].in_uop.bits.uses_stq, issue_slots[6].out_uop.uses_stq connect issue_slots[5].in_uop.bits.uses_ldq, issue_slots[6].out_uop.uses_ldq connect issue_slots[5].in_uop.bits.mem_signed, issue_slots[6].out_uop.mem_signed connect issue_slots[5].in_uop.bits.mem_size, issue_slots[6].out_uop.mem_size connect issue_slots[5].in_uop.bits.mem_cmd, issue_slots[6].out_uop.mem_cmd connect issue_slots[5].in_uop.bits.exc_cause, issue_slots[6].out_uop.exc_cause connect issue_slots[5].in_uop.bits.exception, issue_slots[6].out_uop.exception connect issue_slots[5].in_uop.bits.stale_pdst, issue_slots[6].out_uop.stale_pdst connect issue_slots[5].in_uop.bits.ppred_busy, issue_slots[6].out_uop.ppred_busy connect issue_slots[5].in_uop.bits.prs3_busy, issue_slots[6].out_uop.prs3_busy connect issue_slots[5].in_uop.bits.prs2_busy, issue_slots[6].out_uop.prs2_busy connect issue_slots[5].in_uop.bits.prs1_busy, issue_slots[6].out_uop.prs1_busy connect issue_slots[5].in_uop.bits.ppred, issue_slots[6].out_uop.ppred connect issue_slots[5].in_uop.bits.prs3, issue_slots[6].out_uop.prs3 connect issue_slots[5].in_uop.bits.prs2, issue_slots[6].out_uop.prs2 connect issue_slots[5].in_uop.bits.prs1, issue_slots[6].out_uop.prs1 connect issue_slots[5].in_uop.bits.pdst, issue_slots[6].out_uop.pdst connect issue_slots[5].in_uop.bits.rxq_idx, issue_slots[6].out_uop.rxq_idx connect issue_slots[5].in_uop.bits.stq_idx, issue_slots[6].out_uop.stq_idx connect issue_slots[5].in_uop.bits.ldq_idx, issue_slots[6].out_uop.ldq_idx connect issue_slots[5].in_uop.bits.rob_idx, issue_slots[6].out_uop.rob_idx connect issue_slots[5].in_uop.bits.fp_ctrl.vec, issue_slots[6].out_uop.fp_ctrl.vec connect issue_slots[5].in_uop.bits.fp_ctrl.wflags, issue_slots[6].out_uop.fp_ctrl.wflags connect issue_slots[5].in_uop.bits.fp_ctrl.sqrt, issue_slots[6].out_uop.fp_ctrl.sqrt connect issue_slots[5].in_uop.bits.fp_ctrl.div, issue_slots[6].out_uop.fp_ctrl.div connect issue_slots[5].in_uop.bits.fp_ctrl.fma, issue_slots[6].out_uop.fp_ctrl.fma connect issue_slots[5].in_uop.bits.fp_ctrl.fastpipe, issue_slots[6].out_uop.fp_ctrl.fastpipe connect issue_slots[5].in_uop.bits.fp_ctrl.toint, issue_slots[6].out_uop.fp_ctrl.toint connect issue_slots[5].in_uop.bits.fp_ctrl.fromint, issue_slots[6].out_uop.fp_ctrl.fromint connect issue_slots[5].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[6].out_uop.fp_ctrl.typeTagOut connect issue_slots[5].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[6].out_uop.fp_ctrl.typeTagIn connect issue_slots[5].in_uop.bits.fp_ctrl.swap23, issue_slots[6].out_uop.fp_ctrl.swap23 connect issue_slots[5].in_uop.bits.fp_ctrl.swap12, issue_slots[6].out_uop.fp_ctrl.swap12 connect issue_slots[5].in_uop.bits.fp_ctrl.ren3, issue_slots[6].out_uop.fp_ctrl.ren3 connect issue_slots[5].in_uop.bits.fp_ctrl.ren2, issue_slots[6].out_uop.fp_ctrl.ren2 connect issue_slots[5].in_uop.bits.fp_ctrl.ren1, issue_slots[6].out_uop.fp_ctrl.ren1 connect issue_slots[5].in_uop.bits.fp_ctrl.wen, issue_slots[6].out_uop.fp_ctrl.wen connect issue_slots[5].in_uop.bits.fp_ctrl.ldst, issue_slots[6].out_uop.fp_ctrl.ldst connect issue_slots[5].in_uop.bits.op2_sel, issue_slots[6].out_uop.op2_sel connect issue_slots[5].in_uop.bits.op1_sel, issue_slots[6].out_uop.op1_sel connect issue_slots[5].in_uop.bits.imm_packed, issue_slots[6].out_uop.imm_packed connect issue_slots[5].in_uop.bits.pimm, issue_slots[6].out_uop.pimm connect issue_slots[5].in_uop.bits.imm_sel, issue_slots[6].out_uop.imm_sel connect issue_slots[5].in_uop.bits.imm_rename, issue_slots[6].out_uop.imm_rename connect issue_slots[5].in_uop.bits.taken, issue_slots[6].out_uop.taken connect issue_slots[5].in_uop.bits.pc_lob, issue_slots[6].out_uop.pc_lob connect issue_slots[5].in_uop.bits.edge_inst, issue_slots[6].out_uop.edge_inst connect issue_slots[5].in_uop.bits.ftq_idx, issue_slots[6].out_uop.ftq_idx connect issue_slots[5].in_uop.bits.is_mov, issue_slots[6].out_uop.is_mov connect issue_slots[5].in_uop.bits.is_rocc, issue_slots[6].out_uop.is_rocc connect issue_slots[5].in_uop.bits.is_sys_pc2epc, issue_slots[6].out_uop.is_sys_pc2epc connect issue_slots[5].in_uop.bits.is_eret, issue_slots[6].out_uop.is_eret connect issue_slots[5].in_uop.bits.is_amo, issue_slots[6].out_uop.is_amo connect issue_slots[5].in_uop.bits.is_sfence, issue_slots[6].out_uop.is_sfence connect issue_slots[5].in_uop.bits.is_fencei, issue_slots[6].out_uop.is_fencei connect issue_slots[5].in_uop.bits.is_fence, issue_slots[6].out_uop.is_fence connect issue_slots[5].in_uop.bits.is_sfb, issue_slots[6].out_uop.is_sfb connect issue_slots[5].in_uop.bits.br_type, issue_slots[6].out_uop.br_type connect issue_slots[5].in_uop.bits.br_tag, issue_slots[6].out_uop.br_tag connect issue_slots[5].in_uop.bits.br_mask, issue_slots[6].out_uop.br_mask connect issue_slots[5].in_uop.bits.dis_col_sel, issue_slots[6].out_uop.dis_col_sel connect issue_slots[5].in_uop.bits.iw_p3_bypass_hint, issue_slots[6].out_uop.iw_p3_bypass_hint connect issue_slots[5].in_uop.bits.iw_p2_bypass_hint, issue_slots[6].out_uop.iw_p2_bypass_hint connect issue_slots[5].in_uop.bits.iw_p1_bypass_hint, issue_slots[6].out_uop.iw_p1_bypass_hint connect issue_slots[5].in_uop.bits.iw_p2_speculative_child, issue_slots[6].out_uop.iw_p2_speculative_child connect issue_slots[5].in_uop.bits.iw_p1_speculative_child, issue_slots[6].out_uop.iw_p1_speculative_child connect issue_slots[5].in_uop.bits.iw_issued_partial_dgen, issue_slots[6].out_uop.iw_issued_partial_dgen connect issue_slots[5].in_uop.bits.iw_issued_partial_agen, issue_slots[6].out_uop.iw_issued_partial_agen connect issue_slots[5].in_uop.bits.iw_issued, issue_slots[6].out_uop.iw_issued connect issue_slots[5].in_uop.bits.fu_code[0], issue_slots[6].out_uop.fu_code[0] connect issue_slots[5].in_uop.bits.fu_code[1], issue_slots[6].out_uop.fu_code[1] connect issue_slots[5].in_uop.bits.fu_code[2], issue_slots[6].out_uop.fu_code[2] connect issue_slots[5].in_uop.bits.fu_code[3], issue_slots[6].out_uop.fu_code[3] connect issue_slots[5].in_uop.bits.fu_code[4], issue_slots[6].out_uop.fu_code[4] connect issue_slots[5].in_uop.bits.fu_code[5], issue_slots[6].out_uop.fu_code[5] connect issue_slots[5].in_uop.bits.fu_code[6], issue_slots[6].out_uop.fu_code[6] connect issue_slots[5].in_uop.bits.fu_code[7], issue_slots[6].out_uop.fu_code[7] connect issue_slots[5].in_uop.bits.fu_code[8], issue_slots[6].out_uop.fu_code[8] connect issue_slots[5].in_uop.bits.fu_code[9], issue_slots[6].out_uop.fu_code[9] connect issue_slots[5].in_uop.bits.iq_type[0], issue_slots[6].out_uop.iq_type[0] connect issue_slots[5].in_uop.bits.iq_type[1], issue_slots[6].out_uop.iq_type[1] connect issue_slots[5].in_uop.bits.iq_type[2], issue_slots[6].out_uop.iq_type[2] connect issue_slots[5].in_uop.bits.iq_type[3], issue_slots[6].out_uop.iq_type[3] connect issue_slots[5].in_uop.bits.debug_pc, issue_slots[6].out_uop.debug_pc connect issue_slots[5].in_uop.bits.is_rvc, issue_slots[6].out_uop.is_rvc connect issue_slots[5].in_uop.bits.debug_inst, issue_slots[6].out_uop.debug_inst connect issue_slots[5].in_uop.bits.inst, issue_slots[6].out_uop.inst node _T_293 = eq(shamts_oh[7], UInt<2>(0h2)) when _T_293 : connect issue_slots[5].in_uop.valid, issue_slots[7].will_be_valid connect issue_slots[5].in_uop.bits.debug_tsrc, issue_slots[7].out_uop.debug_tsrc connect issue_slots[5].in_uop.bits.debug_fsrc, issue_slots[7].out_uop.debug_fsrc connect issue_slots[5].in_uop.bits.bp_xcpt_if, issue_slots[7].out_uop.bp_xcpt_if connect issue_slots[5].in_uop.bits.bp_debug_if, issue_slots[7].out_uop.bp_debug_if connect issue_slots[5].in_uop.bits.xcpt_ma_if, issue_slots[7].out_uop.xcpt_ma_if connect issue_slots[5].in_uop.bits.xcpt_ae_if, issue_slots[7].out_uop.xcpt_ae_if connect issue_slots[5].in_uop.bits.xcpt_pf_if, issue_slots[7].out_uop.xcpt_pf_if connect issue_slots[5].in_uop.bits.fp_typ, issue_slots[7].out_uop.fp_typ connect issue_slots[5].in_uop.bits.fp_rm, issue_slots[7].out_uop.fp_rm connect issue_slots[5].in_uop.bits.fp_val, issue_slots[7].out_uop.fp_val connect issue_slots[5].in_uop.bits.fcn_op, issue_slots[7].out_uop.fcn_op connect issue_slots[5].in_uop.bits.fcn_dw, issue_slots[7].out_uop.fcn_dw connect issue_slots[5].in_uop.bits.frs3_en, issue_slots[7].out_uop.frs3_en connect issue_slots[5].in_uop.bits.lrs2_rtype, issue_slots[7].out_uop.lrs2_rtype connect issue_slots[5].in_uop.bits.lrs1_rtype, issue_slots[7].out_uop.lrs1_rtype connect issue_slots[5].in_uop.bits.dst_rtype, issue_slots[7].out_uop.dst_rtype connect issue_slots[5].in_uop.bits.lrs3, issue_slots[7].out_uop.lrs3 connect issue_slots[5].in_uop.bits.lrs2, issue_slots[7].out_uop.lrs2 connect issue_slots[5].in_uop.bits.lrs1, issue_slots[7].out_uop.lrs1 connect issue_slots[5].in_uop.bits.ldst, issue_slots[7].out_uop.ldst connect issue_slots[5].in_uop.bits.ldst_is_rs1, issue_slots[7].out_uop.ldst_is_rs1 connect issue_slots[5].in_uop.bits.csr_cmd, issue_slots[7].out_uop.csr_cmd connect issue_slots[5].in_uop.bits.flush_on_commit, issue_slots[7].out_uop.flush_on_commit connect issue_slots[5].in_uop.bits.is_unique, issue_slots[7].out_uop.is_unique connect issue_slots[5].in_uop.bits.uses_stq, issue_slots[7].out_uop.uses_stq connect issue_slots[5].in_uop.bits.uses_ldq, issue_slots[7].out_uop.uses_ldq connect issue_slots[5].in_uop.bits.mem_signed, issue_slots[7].out_uop.mem_signed connect issue_slots[5].in_uop.bits.mem_size, issue_slots[7].out_uop.mem_size connect issue_slots[5].in_uop.bits.mem_cmd, issue_slots[7].out_uop.mem_cmd connect issue_slots[5].in_uop.bits.exc_cause, issue_slots[7].out_uop.exc_cause connect issue_slots[5].in_uop.bits.exception, issue_slots[7].out_uop.exception connect issue_slots[5].in_uop.bits.stale_pdst, issue_slots[7].out_uop.stale_pdst connect issue_slots[5].in_uop.bits.ppred_busy, issue_slots[7].out_uop.ppred_busy connect issue_slots[5].in_uop.bits.prs3_busy, issue_slots[7].out_uop.prs3_busy connect issue_slots[5].in_uop.bits.prs2_busy, issue_slots[7].out_uop.prs2_busy connect issue_slots[5].in_uop.bits.prs1_busy, issue_slots[7].out_uop.prs1_busy connect issue_slots[5].in_uop.bits.ppred, issue_slots[7].out_uop.ppred connect issue_slots[5].in_uop.bits.prs3, issue_slots[7].out_uop.prs3 connect issue_slots[5].in_uop.bits.prs2, issue_slots[7].out_uop.prs2 connect issue_slots[5].in_uop.bits.prs1, issue_slots[7].out_uop.prs1 connect issue_slots[5].in_uop.bits.pdst, issue_slots[7].out_uop.pdst connect issue_slots[5].in_uop.bits.rxq_idx, issue_slots[7].out_uop.rxq_idx connect issue_slots[5].in_uop.bits.stq_idx, issue_slots[7].out_uop.stq_idx connect issue_slots[5].in_uop.bits.ldq_idx, issue_slots[7].out_uop.ldq_idx connect issue_slots[5].in_uop.bits.rob_idx, issue_slots[7].out_uop.rob_idx connect issue_slots[5].in_uop.bits.fp_ctrl.vec, issue_slots[7].out_uop.fp_ctrl.vec connect issue_slots[5].in_uop.bits.fp_ctrl.wflags, issue_slots[7].out_uop.fp_ctrl.wflags connect issue_slots[5].in_uop.bits.fp_ctrl.sqrt, issue_slots[7].out_uop.fp_ctrl.sqrt connect issue_slots[5].in_uop.bits.fp_ctrl.div, issue_slots[7].out_uop.fp_ctrl.div connect issue_slots[5].in_uop.bits.fp_ctrl.fma, issue_slots[7].out_uop.fp_ctrl.fma connect issue_slots[5].in_uop.bits.fp_ctrl.fastpipe, issue_slots[7].out_uop.fp_ctrl.fastpipe connect issue_slots[5].in_uop.bits.fp_ctrl.toint, issue_slots[7].out_uop.fp_ctrl.toint connect issue_slots[5].in_uop.bits.fp_ctrl.fromint, issue_slots[7].out_uop.fp_ctrl.fromint connect issue_slots[5].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[7].out_uop.fp_ctrl.typeTagOut connect issue_slots[5].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[7].out_uop.fp_ctrl.typeTagIn connect issue_slots[5].in_uop.bits.fp_ctrl.swap23, issue_slots[7].out_uop.fp_ctrl.swap23 connect issue_slots[5].in_uop.bits.fp_ctrl.swap12, issue_slots[7].out_uop.fp_ctrl.swap12 connect issue_slots[5].in_uop.bits.fp_ctrl.ren3, issue_slots[7].out_uop.fp_ctrl.ren3 connect issue_slots[5].in_uop.bits.fp_ctrl.ren2, issue_slots[7].out_uop.fp_ctrl.ren2 connect issue_slots[5].in_uop.bits.fp_ctrl.ren1, issue_slots[7].out_uop.fp_ctrl.ren1 connect issue_slots[5].in_uop.bits.fp_ctrl.wen, issue_slots[7].out_uop.fp_ctrl.wen connect issue_slots[5].in_uop.bits.fp_ctrl.ldst, issue_slots[7].out_uop.fp_ctrl.ldst connect issue_slots[5].in_uop.bits.op2_sel, issue_slots[7].out_uop.op2_sel connect issue_slots[5].in_uop.bits.op1_sel, issue_slots[7].out_uop.op1_sel connect issue_slots[5].in_uop.bits.imm_packed, issue_slots[7].out_uop.imm_packed connect issue_slots[5].in_uop.bits.pimm, issue_slots[7].out_uop.pimm connect issue_slots[5].in_uop.bits.imm_sel, issue_slots[7].out_uop.imm_sel connect issue_slots[5].in_uop.bits.imm_rename, issue_slots[7].out_uop.imm_rename connect issue_slots[5].in_uop.bits.taken, issue_slots[7].out_uop.taken connect issue_slots[5].in_uop.bits.pc_lob, issue_slots[7].out_uop.pc_lob connect issue_slots[5].in_uop.bits.edge_inst, issue_slots[7].out_uop.edge_inst connect issue_slots[5].in_uop.bits.ftq_idx, issue_slots[7].out_uop.ftq_idx connect issue_slots[5].in_uop.bits.is_mov, issue_slots[7].out_uop.is_mov connect issue_slots[5].in_uop.bits.is_rocc, issue_slots[7].out_uop.is_rocc connect issue_slots[5].in_uop.bits.is_sys_pc2epc, issue_slots[7].out_uop.is_sys_pc2epc connect issue_slots[5].in_uop.bits.is_eret, issue_slots[7].out_uop.is_eret connect issue_slots[5].in_uop.bits.is_amo, issue_slots[7].out_uop.is_amo connect issue_slots[5].in_uop.bits.is_sfence, issue_slots[7].out_uop.is_sfence connect issue_slots[5].in_uop.bits.is_fencei, issue_slots[7].out_uop.is_fencei connect issue_slots[5].in_uop.bits.is_fence, issue_slots[7].out_uop.is_fence connect issue_slots[5].in_uop.bits.is_sfb, issue_slots[7].out_uop.is_sfb connect issue_slots[5].in_uop.bits.br_type, issue_slots[7].out_uop.br_type connect issue_slots[5].in_uop.bits.br_tag, issue_slots[7].out_uop.br_tag connect issue_slots[5].in_uop.bits.br_mask, issue_slots[7].out_uop.br_mask connect issue_slots[5].in_uop.bits.dis_col_sel, issue_slots[7].out_uop.dis_col_sel connect issue_slots[5].in_uop.bits.iw_p3_bypass_hint, issue_slots[7].out_uop.iw_p3_bypass_hint connect issue_slots[5].in_uop.bits.iw_p2_bypass_hint, issue_slots[7].out_uop.iw_p2_bypass_hint connect issue_slots[5].in_uop.bits.iw_p1_bypass_hint, issue_slots[7].out_uop.iw_p1_bypass_hint connect issue_slots[5].in_uop.bits.iw_p2_speculative_child, issue_slots[7].out_uop.iw_p2_speculative_child connect issue_slots[5].in_uop.bits.iw_p1_speculative_child, issue_slots[7].out_uop.iw_p1_speculative_child connect issue_slots[5].in_uop.bits.iw_issued_partial_dgen, issue_slots[7].out_uop.iw_issued_partial_dgen connect issue_slots[5].in_uop.bits.iw_issued_partial_agen, issue_slots[7].out_uop.iw_issued_partial_agen connect issue_slots[5].in_uop.bits.iw_issued, issue_slots[7].out_uop.iw_issued connect issue_slots[5].in_uop.bits.fu_code[0], issue_slots[7].out_uop.fu_code[0] connect issue_slots[5].in_uop.bits.fu_code[1], issue_slots[7].out_uop.fu_code[1] connect issue_slots[5].in_uop.bits.fu_code[2], issue_slots[7].out_uop.fu_code[2] connect issue_slots[5].in_uop.bits.fu_code[3], issue_slots[7].out_uop.fu_code[3] connect issue_slots[5].in_uop.bits.fu_code[4], issue_slots[7].out_uop.fu_code[4] connect issue_slots[5].in_uop.bits.fu_code[5], issue_slots[7].out_uop.fu_code[5] connect issue_slots[5].in_uop.bits.fu_code[6], issue_slots[7].out_uop.fu_code[6] connect issue_slots[5].in_uop.bits.fu_code[7], issue_slots[7].out_uop.fu_code[7] connect issue_slots[5].in_uop.bits.fu_code[8], issue_slots[7].out_uop.fu_code[8] connect issue_slots[5].in_uop.bits.fu_code[9], issue_slots[7].out_uop.fu_code[9] connect issue_slots[5].in_uop.bits.iq_type[0], issue_slots[7].out_uop.iq_type[0] connect issue_slots[5].in_uop.bits.iq_type[1], issue_slots[7].out_uop.iq_type[1] connect issue_slots[5].in_uop.bits.iq_type[2], issue_slots[7].out_uop.iq_type[2] connect issue_slots[5].in_uop.bits.iq_type[3], issue_slots[7].out_uop.iq_type[3] connect issue_slots[5].in_uop.bits.debug_pc, issue_slots[7].out_uop.debug_pc connect issue_slots[5].in_uop.bits.is_rvc, issue_slots[7].out_uop.is_rvc connect issue_slots[5].in_uop.bits.debug_inst, issue_slots[7].out_uop.debug_inst connect issue_slots[5].in_uop.bits.inst, issue_slots[7].out_uop.inst node _T_294 = eq(shamts_oh[8], UInt<3>(0h4)) when _T_294 : connect issue_slots[5].in_uop.valid, issue_slots[8].will_be_valid connect issue_slots[5].in_uop.bits.debug_tsrc, issue_slots[8].out_uop.debug_tsrc connect issue_slots[5].in_uop.bits.debug_fsrc, issue_slots[8].out_uop.debug_fsrc connect issue_slots[5].in_uop.bits.bp_xcpt_if, issue_slots[8].out_uop.bp_xcpt_if connect issue_slots[5].in_uop.bits.bp_debug_if, issue_slots[8].out_uop.bp_debug_if connect issue_slots[5].in_uop.bits.xcpt_ma_if, issue_slots[8].out_uop.xcpt_ma_if connect issue_slots[5].in_uop.bits.xcpt_ae_if, issue_slots[8].out_uop.xcpt_ae_if connect issue_slots[5].in_uop.bits.xcpt_pf_if, issue_slots[8].out_uop.xcpt_pf_if connect issue_slots[5].in_uop.bits.fp_typ, issue_slots[8].out_uop.fp_typ connect issue_slots[5].in_uop.bits.fp_rm, issue_slots[8].out_uop.fp_rm connect issue_slots[5].in_uop.bits.fp_val, issue_slots[8].out_uop.fp_val connect issue_slots[5].in_uop.bits.fcn_op, issue_slots[8].out_uop.fcn_op connect issue_slots[5].in_uop.bits.fcn_dw, issue_slots[8].out_uop.fcn_dw connect issue_slots[5].in_uop.bits.frs3_en, issue_slots[8].out_uop.frs3_en connect issue_slots[5].in_uop.bits.lrs2_rtype, issue_slots[8].out_uop.lrs2_rtype connect issue_slots[5].in_uop.bits.lrs1_rtype, issue_slots[8].out_uop.lrs1_rtype connect issue_slots[5].in_uop.bits.dst_rtype, issue_slots[8].out_uop.dst_rtype connect issue_slots[5].in_uop.bits.lrs3, issue_slots[8].out_uop.lrs3 connect issue_slots[5].in_uop.bits.lrs2, issue_slots[8].out_uop.lrs2 connect issue_slots[5].in_uop.bits.lrs1, issue_slots[8].out_uop.lrs1 connect issue_slots[5].in_uop.bits.ldst, issue_slots[8].out_uop.ldst connect issue_slots[5].in_uop.bits.ldst_is_rs1, issue_slots[8].out_uop.ldst_is_rs1 connect issue_slots[5].in_uop.bits.csr_cmd, issue_slots[8].out_uop.csr_cmd connect issue_slots[5].in_uop.bits.flush_on_commit, issue_slots[8].out_uop.flush_on_commit connect issue_slots[5].in_uop.bits.is_unique, issue_slots[8].out_uop.is_unique connect issue_slots[5].in_uop.bits.uses_stq, issue_slots[8].out_uop.uses_stq connect issue_slots[5].in_uop.bits.uses_ldq, issue_slots[8].out_uop.uses_ldq connect issue_slots[5].in_uop.bits.mem_signed, issue_slots[8].out_uop.mem_signed connect issue_slots[5].in_uop.bits.mem_size, issue_slots[8].out_uop.mem_size connect issue_slots[5].in_uop.bits.mem_cmd, issue_slots[8].out_uop.mem_cmd connect issue_slots[5].in_uop.bits.exc_cause, issue_slots[8].out_uop.exc_cause connect issue_slots[5].in_uop.bits.exception, issue_slots[8].out_uop.exception connect issue_slots[5].in_uop.bits.stale_pdst, issue_slots[8].out_uop.stale_pdst connect issue_slots[5].in_uop.bits.ppred_busy, issue_slots[8].out_uop.ppred_busy connect issue_slots[5].in_uop.bits.prs3_busy, issue_slots[8].out_uop.prs3_busy connect issue_slots[5].in_uop.bits.prs2_busy, issue_slots[8].out_uop.prs2_busy connect issue_slots[5].in_uop.bits.prs1_busy, issue_slots[8].out_uop.prs1_busy connect issue_slots[5].in_uop.bits.ppred, issue_slots[8].out_uop.ppred connect issue_slots[5].in_uop.bits.prs3, issue_slots[8].out_uop.prs3 connect issue_slots[5].in_uop.bits.prs2, issue_slots[8].out_uop.prs2 connect issue_slots[5].in_uop.bits.prs1, issue_slots[8].out_uop.prs1 connect issue_slots[5].in_uop.bits.pdst, issue_slots[8].out_uop.pdst connect issue_slots[5].in_uop.bits.rxq_idx, issue_slots[8].out_uop.rxq_idx connect issue_slots[5].in_uop.bits.stq_idx, issue_slots[8].out_uop.stq_idx connect issue_slots[5].in_uop.bits.ldq_idx, issue_slots[8].out_uop.ldq_idx connect issue_slots[5].in_uop.bits.rob_idx, issue_slots[8].out_uop.rob_idx connect issue_slots[5].in_uop.bits.fp_ctrl.vec, issue_slots[8].out_uop.fp_ctrl.vec connect issue_slots[5].in_uop.bits.fp_ctrl.wflags, issue_slots[8].out_uop.fp_ctrl.wflags connect issue_slots[5].in_uop.bits.fp_ctrl.sqrt, issue_slots[8].out_uop.fp_ctrl.sqrt connect issue_slots[5].in_uop.bits.fp_ctrl.div, issue_slots[8].out_uop.fp_ctrl.div connect issue_slots[5].in_uop.bits.fp_ctrl.fma, issue_slots[8].out_uop.fp_ctrl.fma connect issue_slots[5].in_uop.bits.fp_ctrl.fastpipe, issue_slots[8].out_uop.fp_ctrl.fastpipe connect issue_slots[5].in_uop.bits.fp_ctrl.toint, issue_slots[8].out_uop.fp_ctrl.toint connect issue_slots[5].in_uop.bits.fp_ctrl.fromint, issue_slots[8].out_uop.fp_ctrl.fromint connect issue_slots[5].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[8].out_uop.fp_ctrl.typeTagOut connect issue_slots[5].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[8].out_uop.fp_ctrl.typeTagIn connect issue_slots[5].in_uop.bits.fp_ctrl.swap23, issue_slots[8].out_uop.fp_ctrl.swap23 connect issue_slots[5].in_uop.bits.fp_ctrl.swap12, issue_slots[8].out_uop.fp_ctrl.swap12 connect issue_slots[5].in_uop.bits.fp_ctrl.ren3, issue_slots[8].out_uop.fp_ctrl.ren3 connect issue_slots[5].in_uop.bits.fp_ctrl.ren2, issue_slots[8].out_uop.fp_ctrl.ren2 connect issue_slots[5].in_uop.bits.fp_ctrl.ren1, issue_slots[8].out_uop.fp_ctrl.ren1 connect issue_slots[5].in_uop.bits.fp_ctrl.wen, issue_slots[8].out_uop.fp_ctrl.wen connect issue_slots[5].in_uop.bits.fp_ctrl.ldst, issue_slots[8].out_uop.fp_ctrl.ldst connect issue_slots[5].in_uop.bits.op2_sel, issue_slots[8].out_uop.op2_sel connect issue_slots[5].in_uop.bits.op1_sel, issue_slots[8].out_uop.op1_sel connect issue_slots[5].in_uop.bits.imm_packed, issue_slots[8].out_uop.imm_packed connect issue_slots[5].in_uop.bits.pimm, issue_slots[8].out_uop.pimm connect issue_slots[5].in_uop.bits.imm_sel, issue_slots[8].out_uop.imm_sel connect issue_slots[5].in_uop.bits.imm_rename, issue_slots[8].out_uop.imm_rename connect issue_slots[5].in_uop.bits.taken, issue_slots[8].out_uop.taken connect issue_slots[5].in_uop.bits.pc_lob, issue_slots[8].out_uop.pc_lob connect issue_slots[5].in_uop.bits.edge_inst, issue_slots[8].out_uop.edge_inst connect issue_slots[5].in_uop.bits.ftq_idx, issue_slots[8].out_uop.ftq_idx connect issue_slots[5].in_uop.bits.is_mov, issue_slots[8].out_uop.is_mov connect issue_slots[5].in_uop.bits.is_rocc, issue_slots[8].out_uop.is_rocc connect issue_slots[5].in_uop.bits.is_sys_pc2epc, issue_slots[8].out_uop.is_sys_pc2epc connect issue_slots[5].in_uop.bits.is_eret, issue_slots[8].out_uop.is_eret connect issue_slots[5].in_uop.bits.is_amo, issue_slots[8].out_uop.is_amo connect issue_slots[5].in_uop.bits.is_sfence, issue_slots[8].out_uop.is_sfence connect issue_slots[5].in_uop.bits.is_fencei, issue_slots[8].out_uop.is_fencei connect issue_slots[5].in_uop.bits.is_fence, issue_slots[8].out_uop.is_fence connect issue_slots[5].in_uop.bits.is_sfb, issue_slots[8].out_uop.is_sfb connect issue_slots[5].in_uop.bits.br_type, issue_slots[8].out_uop.br_type connect issue_slots[5].in_uop.bits.br_tag, issue_slots[8].out_uop.br_tag connect issue_slots[5].in_uop.bits.br_mask, issue_slots[8].out_uop.br_mask connect issue_slots[5].in_uop.bits.dis_col_sel, issue_slots[8].out_uop.dis_col_sel connect issue_slots[5].in_uop.bits.iw_p3_bypass_hint, issue_slots[8].out_uop.iw_p3_bypass_hint connect issue_slots[5].in_uop.bits.iw_p2_bypass_hint, issue_slots[8].out_uop.iw_p2_bypass_hint connect issue_slots[5].in_uop.bits.iw_p1_bypass_hint, issue_slots[8].out_uop.iw_p1_bypass_hint connect issue_slots[5].in_uop.bits.iw_p2_speculative_child, issue_slots[8].out_uop.iw_p2_speculative_child connect issue_slots[5].in_uop.bits.iw_p1_speculative_child, issue_slots[8].out_uop.iw_p1_speculative_child connect issue_slots[5].in_uop.bits.iw_issued_partial_dgen, issue_slots[8].out_uop.iw_issued_partial_dgen connect issue_slots[5].in_uop.bits.iw_issued_partial_agen, issue_slots[8].out_uop.iw_issued_partial_agen connect issue_slots[5].in_uop.bits.iw_issued, issue_slots[8].out_uop.iw_issued connect issue_slots[5].in_uop.bits.fu_code[0], issue_slots[8].out_uop.fu_code[0] connect issue_slots[5].in_uop.bits.fu_code[1], issue_slots[8].out_uop.fu_code[1] connect issue_slots[5].in_uop.bits.fu_code[2], issue_slots[8].out_uop.fu_code[2] connect issue_slots[5].in_uop.bits.fu_code[3], issue_slots[8].out_uop.fu_code[3] connect issue_slots[5].in_uop.bits.fu_code[4], issue_slots[8].out_uop.fu_code[4] connect issue_slots[5].in_uop.bits.fu_code[5], issue_slots[8].out_uop.fu_code[5] connect issue_slots[5].in_uop.bits.fu_code[6], issue_slots[8].out_uop.fu_code[6] connect issue_slots[5].in_uop.bits.fu_code[7], issue_slots[8].out_uop.fu_code[7] connect issue_slots[5].in_uop.bits.fu_code[8], issue_slots[8].out_uop.fu_code[8] connect issue_slots[5].in_uop.bits.fu_code[9], issue_slots[8].out_uop.fu_code[9] connect issue_slots[5].in_uop.bits.iq_type[0], issue_slots[8].out_uop.iq_type[0] connect issue_slots[5].in_uop.bits.iq_type[1], issue_slots[8].out_uop.iq_type[1] connect issue_slots[5].in_uop.bits.iq_type[2], issue_slots[8].out_uop.iq_type[2] connect issue_slots[5].in_uop.bits.iq_type[3], issue_slots[8].out_uop.iq_type[3] connect issue_slots[5].in_uop.bits.debug_pc, issue_slots[8].out_uop.debug_pc connect issue_slots[5].in_uop.bits.is_rvc, issue_slots[8].out_uop.is_rvc connect issue_slots[5].in_uop.bits.debug_inst, issue_slots[8].out_uop.debug_inst connect issue_slots[5].in_uop.bits.inst, issue_slots[8].out_uop.inst node _issue_slots_5_clear_T = neq(shamts_oh[5], UInt<1>(0h0)) connect issue_slots[5].clear, _issue_slots_5_clear_T connect issue_slots[6].in_uop.valid, UInt<1>(0h0) connect issue_slots[6].in_uop.bits.debug_tsrc, issue_slots[7].out_uop.debug_tsrc connect issue_slots[6].in_uop.bits.debug_fsrc, issue_slots[7].out_uop.debug_fsrc connect issue_slots[6].in_uop.bits.bp_xcpt_if, issue_slots[7].out_uop.bp_xcpt_if connect issue_slots[6].in_uop.bits.bp_debug_if, issue_slots[7].out_uop.bp_debug_if connect issue_slots[6].in_uop.bits.xcpt_ma_if, issue_slots[7].out_uop.xcpt_ma_if connect issue_slots[6].in_uop.bits.xcpt_ae_if, issue_slots[7].out_uop.xcpt_ae_if connect issue_slots[6].in_uop.bits.xcpt_pf_if, issue_slots[7].out_uop.xcpt_pf_if connect issue_slots[6].in_uop.bits.fp_typ, issue_slots[7].out_uop.fp_typ connect issue_slots[6].in_uop.bits.fp_rm, issue_slots[7].out_uop.fp_rm connect issue_slots[6].in_uop.bits.fp_val, issue_slots[7].out_uop.fp_val connect issue_slots[6].in_uop.bits.fcn_op, issue_slots[7].out_uop.fcn_op connect issue_slots[6].in_uop.bits.fcn_dw, issue_slots[7].out_uop.fcn_dw connect issue_slots[6].in_uop.bits.frs3_en, issue_slots[7].out_uop.frs3_en connect issue_slots[6].in_uop.bits.lrs2_rtype, issue_slots[7].out_uop.lrs2_rtype connect issue_slots[6].in_uop.bits.lrs1_rtype, issue_slots[7].out_uop.lrs1_rtype connect issue_slots[6].in_uop.bits.dst_rtype, issue_slots[7].out_uop.dst_rtype connect issue_slots[6].in_uop.bits.lrs3, issue_slots[7].out_uop.lrs3 connect issue_slots[6].in_uop.bits.lrs2, issue_slots[7].out_uop.lrs2 connect issue_slots[6].in_uop.bits.lrs1, issue_slots[7].out_uop.lrs1 connect issue_slots[6].in_uop.bits.ldst, issue_slots[7].out_uop.ldst connect issue_slots[6].in_uop.bits.ldst_is_rs1, issue_slots[7].out_uop.ldst_is_rs1 connect issue_slots[6].in_uop.bits.csr_cmd, issue_slots[7].out_uop.csr_cmd connect issue_slots[6].in_uop.bits.flush_on_commit, issue_slots[7].out_uop.flush_on_commit connect issue_slots[6].in_uop.bits.is_unique, issue_slots[7].out_uop.is_unique connect issue_slots[6].in_uop.bits.uses_stq, issue_slots[7].out_uop.uses_stq connect issue_slots[6].in_uop.bits.uses_ldq, issue_slots[7].out_uop.uses_ldq connect issue_slots[6].in_uop.bits.mem_signed, issue_slots[7].out_uop.mem_signed connect issue_slots[6].in_uop.bits.mem_size, issue_slots[7].out_uop.mem_size connect issue_slots[6].in_uop.bits.mem_cmd, issue_slots[7].out_uop.mem_cmd connect issue_slots[6].in_uop.bits.exc_cause, issue_slots[7].out_uop.exc_cause connect issue_slots[6].in_uop.bits.exception, issue_slots[7].out_uop.exception connect issue_slots[6].in_uop.bits.stale_pdst, issue_slots[7].out_uop.stale_pdst connect issue_slots[6].in_uop.bits.ppred_busy, issue_slots[7].out_uop.ppred_busy connect issue_slots[6].in_uop.bits.prs3_busy, issue_slots[7].out_uop.prs3_busy connect issue_slots[6].in_uop.bits.prs2_busy, issue_slots[7].out_uop.prs2_busy connect issue_slots[6].in_uop.bits.prs1_busy, issue_slots[7].out_uop.prs1_busy connect issue_slots[6].in_uop.bits.ppred, issue_slots[7].out_uop.ppred connect issue_slots[6].in_uop.bits.prs3, issue_slots[7].out_uop.prs3 connect issue_slots[6].in_uop.bits.prs2, issue_slots[7].out_uop.prs2 connect issue_slots[6].in_uop.bits.prs1, issue_slots[7].out_uop.prs1 connect issue_slots[6].in_uop.bits.pdst, issue_slots[7].out_uop.pdst connect issue_slots[6].in_uop.bits.rxq_idx, issue_slots[7].out_uop.rxq_idx connect issue_slots[6].in_uop.bits.stq_idx, issue_slots[7].out_uop.stq_idx connect issue_slots[6].in_uop.bits.ldq_idx, issue_slots[7].out_uop.ldq_idx connect issue_slots[6].in_uop.bits.rob_idx, issue_slots[7].out_uop.rob_idx connect issue_slots[6].in_uop.bits.fp_ctrl.vec, issue_slots[7].out_uop.fp_ctrl.vec connect issue_slots[6].in_uop.bits.fp_ctrl.wflags, issue_slots[7].out_uop.fp_ctrl.wflags connect issue_slots[6].in_uop.bits.fp_ctrl.sqrt, issue_slots[7].out_uop.fp_ctrl.sqrt connect issue_slots[6].in_uop.bits.fp_ctrl.div, issue_slots[7].out_uop.fp_ctrl.div connect issue_slots[6].in_uop.bits.fp_ctrl.fma, issue_slots[7].out_uop.fp_ctrl.fma connect issue_slots[6].in_uop.bits.fp_ctrl.fastpipe, issue_slots[7].out_uop.fp_ctrl.fastpipe connect issue_slots[6].in_uop.bits.fp_ctrl.toint, issue_slots[7].out_uop.fp_ctrl.toint connect issue_slots[6].in_uop.bits.fp_ctrl.fromint, issue_slots[7].out_uop.fp_ctrl.fromint connect issue_slots[6].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[7].out_uop.fp_ctrl.typeTagOut connect issue_slots[6].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[7].out_uop.fp_ctrl.typeTagIn connect issue_slots[6].in_uop.bits.fp_ctrl.swap23, issue_slots[7].out_uop.fp_ctrl.swap23 connect issue_slots[6].in_uop.bits.fp_ctrl.swap12, issue_slots[7].out_uop.fp_ctrl.swap12 connect issue_slots[6].in_uop.bits.fp_ctrl.ren3, issue_slots[7].out_uop.fp_ctrl.ren3 connect issue_slots[6].in_uop.bits.fp_ctrl.ren2, issue_slots[7].out_uop.fp_ctrl.ren2 connect issue_slots[6].in_uop.bits.fp_ctrl.ren1, issue_slots[7].out_uop.fp_ctrl.ren1 connect issue_slots[6].in_uop.bits.fp_ctrl.wen, issue_slots[7].out_uop.fp_ctrl.wen connect issue_slots[6].in_uop.bits.fp_ctrl.ldst, issue_slots[7].out_uop.fp_ctrl.ldst connect issue_slots[6].in_uop.bits.op2_sel, issue_slots[7].out_uop.op2_sel connect issue_slots[6].in_uop.bits.op1_sel, issue_slots[7].out_uop.op1_sel connect issue_slots[6].in_uop.bits.imm_packed, issue_slots[7].out_uop.imm_packed connect issue_slots[6].in_uop.bits.pimm, issue_slots[7].out_uop.pimm connect issue_slots[6].in_uop.bits.imm_sel, issue_slots[7].out_uop.imm_sel connect issue_slots[6].in_uop.bits.imm_rename, issue_slots[7].out_uop.imm_rename connect issue_slots[6].in_uop.bits.taken, issue_slots[7].out_uop.taken connect issue_slots[6].in_uop.bits.pc_lob, issue_slots[7].out_uop.pc_lob connect issue_slots[6].in_uop.bits.edge_inst, issue_slots[7].out_uop.edge_inst connect issue_slots[6].in_uop.bits.ftq_idx, issue_slots[7].out_uop.ftq_idx connect issue_slots[6].in_uop.bits.is_mov, issue_slots[7].out_uop.is_mov connect issue_slots[6].in_uop.bits.is_rocc, issue_slots[7].out_uop.is_rocc connect issue_slots[6].in_uop.bits.is_sys_pc2epc, issue_slots[7].out_uop.is_sys_pc2epc connect issue_slots[6].in_uop.bits.is_eret, issue_slots[7].out_uop.is_eret connect issue_slots[6].in_uop.bits.is_amo, issue_slots[7].out_uop.is_amo connect issue_slots[6].in_uop.bits.is_sfence, issue_slots[7].out_uop.is_sfence connect issue_slots[6].in_uop.bits.is_fencei, issue_slots[7].out_uop.is_fencei connect issue_slots[6].in_uop.bits.is_fence, issue_slots[7].out_uop.is_fence connect issue_slots[6].in_uop.bits.is_sfb, issue_slots[7].out_uop.is_sfb connect issue_slots[6].in_uop.bits.br_type, issue_slots[7].out_uop.br_type connect issue_slots[6].in_uop.bits.br_tag, issue_slots[7].out_uop.br_tag connect issue_slots[6].in_uop.bits.br_mask, issue_slots[7].out_uop.br_mask connect issue_slots[6].in_uop.bits.dis_col_sel, issue_slots[7].out_uop.dis_col_sel connect issue_slots[6].in_uop.bits.iw_p3_bypass_hint, issue_slots[7].out_uop.iw_p3_bypass_hint connect issue_slots[6].in_uop.bits.iw_p2_bypass_hint, issue_slots[7].out_uop.iw_p2_bypass_hint connect issue_slots[6].in_uop.bits.iw_p1_bypass_hint, issue_slots[7].out_uop.iw_p1_bypass_hint connect issue_slots[6].in_uop.bits.iw_p2_speculative_child, issue_slots[7].out_uop.iw_p2_speculative_child connect issue_slots[6].in_uop.bits.iw_p1_speculative_child, issue_slots[7].out_uop.iw_p1_speculative_child connect issue_slots[6].in_uop.bits.iw_issued_partial_dgen, issue_slots[7].out_uop.iw_issued_partial_dgen connect issue_slots[6].in_uop.bits.iw_issued_partial_agen, issue_slots[7].out_uop.iw_issued_partial_agen connect issue_slots[6].in_uop.bits.iw_issued, issue_slots[7].out_uop.iw_issued connect issue_slots[6].in_uop.bits.fu_code[0], issue_slots[7].out_uop.fu_code[0] connect issue_slots[6].in_uop.bits.fu_code[1], issue_slots[7].out_uop.fu_code[1] connect issue_slots[6].in_uop.bits.fu_code[2], issue_slots[7].out_uop.fu_code[2] connect issue_slots[6].in_uop.bits.fu_code[3], issue_slots[7].out_uop.fu_code[3] connect issue_slots[6].in_uop.bits.fu_code[4], issue_slots[7].out_uop.fu_code[4] connect issue_slots[6].in_uop.bits.fu_code[5], issue_slots[7].out_uop.fu_code[5] connect issue_slots[6].in_uop.bits.fu_code[6], issue_slots[7].out_uop.fu_code[6] connect issue_slots[6].in_uop.bits.fu_code[7], issue_slots[7].out_uop.fu_code[7] connect issue_slots[6].in_uop.bits.fu_code[8], issue_slots[7].out_uop.fu_code[8] connect issue_slots[6].in_uop.bits.fu_code[9], issue_slots[7].out_uop.fu_code[9] connect issue_slots[6].in_uop.bits.iq_type[0], issue_slots[7].out_uop.iq_type[0] connect issue_slots[6].in_uop.bits.iq_type[1], issue_slots[7].out_uop.iq_type[1] connect issue_slots[6].in_uop.bits.iq_type[2], issue_slots[7].out_uop.iq_type[2] connect issue_slots[6].in_uop.bits.iq_type[3], issue_slots[7].out_uop.iq_type[3] connect issue_slots[6].in_uop.bits.debug_pc, issue_slots[7].out_uop.debug_pc connect issue_slots[6].in_uop.bits.is_rvc, issue_slots[7].out_uop.is_rvc connect issue_slots[6].in_uop.bits.debug_inst, issue_slots[7].out_uop.debug_inst connect issue_slots[6].in_uop.bits.inst, issue_slots[7].out_uop.inst node _T_295 = eq(shamts_oh[7], UInt<1>(0h1)) when _T_295 : connect issue_slots[6].in_uop.valid, issue_slots[7].will_be_valid connect issue_slots[6].in_uop.bits.debug_tsrc, issue_slots[7].out_uop.debug_tsrc connect issue_slots[6].in_uop.bits.debug_fsrc, issue_slots[7].out_uop.debug_fsrc connect issue_slots[6].in_uop.bits.bp_xcpt_if, issue_slots[7].out_uop.bp_xcpt_if connect issue_slots[6].in_uop.bits.bp_debug_if, issue_slots[7].out_uop.bp_debug_if connect issue_slots[6].in_uop.bits.xcpt_ma_if, issue_slots[7].out_uop.xcpt_ma_if connect issue_slots[6].in_uop.bits.xcpt_ae_if, issue_slots[7].out_uop.xcpt_ae_if connect issue_slots[6].in_uop.bits.xcpt_pf_if, issue_slots[7].out_uop.xcpt_pf_if connect issue_slots[6].in_uop.bits.fp_typ, issue_slots[7].out_uop.fp_typ connect issue_slots[6].in_uop.bits.fp_rm, issue_slots[7].out_uop.fp_rm connect issue_slots[6].in_uop.bits.fp_val, issue_slots[7].out_uop.fp_val connect issue_slots[6].in_uop.bits.fcn_op, issue_slots[7].out_uop.fcn_op connect issue_slots[6].in_uop.bits.fcn_dw, issue_slots[7].out_uop.fcn_dw connect issue_slots[6].in_uop.bits.frs3_en, issue_slots[7].out_uop.frs3_en connect issue_slots[6].in_uop.bits.lrs2_rtype, issue_slots[7].out_uop.lrs2_rtype connect issue_slots[6].in_uop.bits.lrs1_rtype, issue_slots[7].out_uop.lrs1_rtype connect issue_slots[6].in_uop.bits.dst_rtype, issue_slots[7].out_uop.dst_rtype connect issue_slots[6].in_uop.bits.lrs3, issue_slots[7].out_uop.lrs3 connect issue_slots[6].in_uop.bits.lrs2, issue_slots[7].out_uop.lrs2 connect issue_slots[6].in_uop.bits.lrs1, issue_slots[7].out_uop.lrs1 connect issue_slots[6].in_uop.bits.ldst, issue_slots[7].out_uop.ldst connect issue_slots[6].in_uop.bits.ldst_is_rs1, issue_slots[7].out_uop.ldst_is_rs1 connect issue_slots[6].in_uop.bits.csr_cmd, issue_slots[7].out_uop.csr_cmd connect issue_slots[6].in_uop.bits.flush_on_commit, issue_slots[7].out_uop.flush_on_commit connect issue_slots[6].in_uop.bits.is_unique, issue_slots[7].out_uop.is_unique connect issue_slots[6].in_uop.bits.uses_stq, issue_slots[7].out_uop.uses_stq connect issue_slots[6].in_uop.bits.uses_ldq, issue_slots[7].out_uop.uses_ldq connect issue_slots[6].in_uop.bits.mem_signed, issue_slots[7].out_uop.mem_signed connect issue_slots[6].in_uop.bits.mem_size, issue_slots[7].out_uop.mem_size connect issue_slots[6].in_uop.bits.mem_cmd, issue_slots[7].out_uop.mem_cmd connect issue_slots[6].in_uop.bits.exc_cause, issue_slots[7].out_uop.exc_cause connect issue_slots[6].in_uop.bits.exception, issue_slots[7].out_uop.exception connect issue_slots[6].in_uop.bits.stale_pdst, issue_slots[7].out_uop.stale_pdst connect issue_slots[6].in_uop.bits.ppred_busy, issue_slots[7].out_uop.ppred_busy connect issue_slots[6].in_uop.bits.prs3_busy, issue_slots[7].out_uop.prs3_busy connect issue_slots[6].in_uop.bits.prs2_busy, issue_slots[7].out_uop.prs2_busy connect issue_slots[6].in_uop.bits.prs1_busy, issue_slots[7].out_uop.prs1_busy connect issue_slots[6].in_uop.bits.ppred, issue_slots[7].out_uop.ppred connect issue_slots[6].in_uop.bits.prs3, issue_slots[7].out_uop.prs3 connect issue_slots[6].in_uop.bits.prs2, issue_slots[7].out_uop.prs2 connect issue_slots[6].in_uop.bits.prs1, issue_slots[7].out_uop.prs1 connect issue_slots[6].in_uop.bits.pdst, issue_slots[7].out_uop.pdst connect issue_slots[6].in_uop.bits.rxq_idx, issue_slots[7].out_uop.rxq_idx connect issue_slots[6].in_uop.bits.stq_idx, issue_slots[7].out_uop.stq_idx connect issue_slots[6].in_uop.bits.ldq_idx, issue_slots[7].out_uop.ldq_idx connect issue_slots[6].in_uop.bits.rob_idx, issue_slots[7].out_uop.rob_idx connect issue_slots[6].in_uop.bits.fp_ctrl.vec, issue_slots[7].out_uop.fp_ctrl.vec connect issue_slots[6].in_uop.bits.fp_ctrl.wflags, issue_slots[7].out_uop.fp_ctrl.wflags connect issue_slots[6].in_uop.bits.fp_ctrl.sqrt, issue_slots[7].out_uop.fp_ctrl.sqrt connect issue_slots[6].in_uop.bits.fp_ctrl.div, issue_slots[7].out_uop.fp_ctrl.div connect issue_slots[6].in_uop.bits.fp_ctrl.fma, issue_slots[7].out_uop.fp_ctrl.fma connect issue_slots[6].in_uop.bits.fp_ctrl.fastpipe, issue_slots[7].out_uop.fp_ctrl.fastpipe connect issue_slots[6].in_uop.bits.fp_ctrl.toint, issue_slots[7].out_uop.fp_ctrl.toint connect issue_slots[6].in_uop.bits.fp_ctrl.fromint, issue_slots[7].out_uop.fp_ctrl.fromint connect issue_slots[6].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[7].out_uop.fp_ctrl.typeTagOut connect issue_slots[6].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[7].out_uop.fp_ctrl.typeTagIn connect issue_slots[6].in_uop.bits.fp_ctrl.swap23, issue_slots[7].out_uop.fp_ctrl.swap23 connect issue_slots[6].in_uop.bits.fp_ctrl.swap12, issue_slots[7].out_uop.fp_ctrl.swap12 connect issue_slots[6].in_uop.bits.fp_ctrl.ren3, issue_slots[7].out_uop.fp_ctrl.ren3 connect issue_slots[6].in_uop.bits.fp_ctrl.ren2, issue_slots[7].out_uop.fp_ctrl.ren2 connect issue_slots[6].in_uop.bits.fp_ctrl.ren1, issue_slots[7].out_uop.fp_ctrl.ren1 connect issue_slots[6].in_uop.bits.fp_ctrl.wen, issue_slots[7].out_uop.fp_ctrl.wen connect issue_slots[6].in_uop.bits.fp_ctrl.ldst, issue_slots[7].out_uop.fp_ctrl.ldst connect issue_slots[6].in_uop.bits.op2_sel, issue_slots[7].out_uop.op2_sel connect issue_slots[6].in_uop.bits.op1_sel, issue_slots[7].out_uop.op1_sel connect issue_slots[6].in_uop.bits.imm_packed, issue_slots[7].out_uop.imm_packed connect issue_slots[6].in_uop.bits.pimm, issue_slots[7].out_uop.pimm connect issue_slots[6].in_uop.bits.imm_sel, issue_slots[7].out_uop.imm_sel connect issue_slots[6].in_uop.bits.imm_rename, issue_slots[7].out_uop.imm_rename connect issue_slots[6].in_uop.bits.taken, issue_slots[7].out_uop.taken connect issue_slots[6].in_uop.bits.pc_lob, issue_slots[7].out_uop.pc_lob connect issue_slots[6].in_uop.bits.edge_inst, issue_slots[7].out_uop.edge_inst connect issue_slots[6].in_uop.bits.ftq_idx, issue_slots[7].out_uop.ftq_idx connect issue_slots[6].in_uop.bits.is_mov, issue_slots[7].out_uop.is_mov connect issue_slots[6].in_uop.bits.is_rocc, issue_slots[7].out_uop.is_rocc connect issue_slots[6].in_uop.bits.is_sys_pc2epc, issue_slots[7].out_uop.is_sys_pc2epc connect issue_slots[6].in_uop.bits.is_eret, issue_slots[7].out_uop.is_eret connect issue_slots[6].in_uop.bits.is_amo, issue_slots[7].out_uop.is_amo connect issue_slots[6].in_uop.bits.is_sfence, issue_slots[7].out_uop.is_sfence connect issue_slots[6].in_uop.bits.is_fencei, issue_slots[7].out_uop.is_fencei connect issue_slots[6].in_uop.bits.is_fence, issue_slots[7].out_uop.is_fence connect issue_slots[6].in_uop.bits.is_sfb, issue_slots[7].out_uop.is_sfb connect issue_slots[6].in_uop.bits.br_type, issue_slots[7].out_uop.br_type connect issue_slots[6].in_uop.bits.br_tag, issue_slots[7].out_uop.br_tag connect issue_slots[6].in_uop.bits.br_mask, issue_slots[7].out_uop.br_mask connect issue_slots[6].in_uop.bits.dis_col_sel, issue_slots[7].out_uop.dis_col_sel connect issue_slots[6].in_uop.bits.iw_p3_bypass_hint, issue_slots[7].out_uop.iw_p3_bypass_hint connect issue_slots[6].in_uop.bits.iw_p2_bypass_hint, issue_slots[7].out_uop.iw_p2_bypass_hint connect issue_slots[6].in_uop.bits.iw_p1_bypass_hint, issue_slots[7].out_uop.iw_p1_bypass_hint connect issue_slots[6].in_uop.bits.iw_p2_speculative_child, issue_slots[7].out_uop.iw_p2_speculative_child connect issue_slots[6].in_uop.bits.iw_p1_speculative_child, issue_slots[7].out_uop.iw_p1_speculative_child connect issue_slots[6].in_uop.bits.iw_issued_partial_dgen, issue_slots[7].out_uop.iw_issued_partial_dgen connect issue_slots[6].in_uop.bits.iw_issued_partial_agen, issue_slots[7].out_uop.iw_issued_partial_agen connect issue_slots[6].in_uop.bits.iw_issued, issue_slots[7].out_uop.iw_issued connect issue_slots[6].in_uop.bits.fu_code[0], issue_slots[7].out_uop.fu_code[0] connect issue_slots[6].in_uop.bits.fu_code[1], issue_slots[7].out_uop.fu_code[1] connect issue_slots[6].in_uop.bits.fu_code[2], issue_slots[7].out_uop.fu_code[2] connect issue_slots[6].in_uop.bits.fu_code[3], issue_slots[7].out_uop.fu_code[3] connect issue_slots[6].in_uop.bits.fu_code[4], issue_slots[7].out_uop.fu_code[4] connect issue_slots[6].in_uop.bits.fu_code[5], issue_slots[7].out_uop.fu_code[5] connect issue_slots[6].in_uop.bits.fu_code[6], issue_slots[7].out_uop.fu_code[6] connect issue_slots[6].in_uop.bits.fu_code[7], issue_slots[7].out_uop.fu_code[7] connect issue_slots[6].in_uop.bits.fu_code[8], issue_slots[7].out_uop.fu_code[8] connect issue_slots[6].in_uop.bits.fu_code[9], issue_slots[7].out_uop.fu_code[9] connect issue_slots[6].in_uop.bits.iq_type[0], issue_slots[7].out_uop.iq_type[0] connect issue_slots[6].in_uop.bits.iq_type[1], issue_slots[7].out_uop.iq_type[1] connect issue_slots[6].in_uop.bits.iq_type[2], issue_slots[7].out_uop.iq_type[2] connect issue_slots[6].in_uop.bits.iq_type[3], issue_slots[7].out_uop.iq_type[3] connect issue_slots[6].in_uop.bits.debug_pc, issue_slots[7].out_uop.debug_pc connect issue_slots[6].in_uop.bits.is_rvc, issue_slots[7].out_uop.is_rvc connect issue_slots[6].in_uop.bits.debug_inst, issue_slots[7].out_uop.debug_inst connect issue_slots[6].in_uop.bits.inst, issue_slots[7].out_uop.inst node _T_296 = eq(shamts_oh[8], UInt<2>(0h2)) when _T_296 : connect issue_slots[6].in_uop.valid, issue_slots[8].will_be_valid connect issue_slots[6].in_uop.bits.debug_tsrc, issue_slots[8].out_uop.debug_tsrc connect issue_slots[6].in_uop.bits.debug_fsrc, issue_slots[8].out_uop.debug_fsrc connect issue_slots[6].in_uop.bits.bp_xcpt_if, issue_slots[8].out_uop.bp_xcpt_if connect issue_slots[6].in_uop.bits.bp_debug_if, issue_slots[8].out_uop.bp_debug_if connect issue_slots[6].in_uop.bits.xcpt_ma_if, issue_slots[8].out_uop.xcpt_ma_if connect issue_slots[6].in_uop.bits.xcpt_ae_if, issue_slots[8].out_uop.xcpt_ae_if connect issue_slots[6].in_uop.bits.xcpt_pf_if, issue_slots[8].out_uop.xcpt_pf_if connect issue_slots[6].in_uop.bits.fp_typ, issue_slots[8].out_uop.fp_typ connect issue_slots[6].in_uop.bits.fp_rm, issue_slots[8].out_uop.fp_rm connect issue_slots[6].in_uop.bits.fp_val, issue_slots[8].out_uop.fp_val connect issue_slots[6].in_uop.bits.fcn_op, issue_slots[8].out_uop.fcn_op connect issue_slots[6].in_uop.bits.fcn_dw, issue_slots[8].out_uop.fcn_dw connect issue_slots[6].in_uop.bits.frs3_en, issue_slots[8].out_uop.frs3_en connect issue_slots[6].in_uop.bits.lrs2_rtype, issue_slots[8].out_uop.lrs2_rtype connect issue_slots[6].in_uop.bits.lrs1_rtype, issue_slots[8].out_uop.lrs1_rtype connect issue_slots[6].in_uop.bits.dst_rtype, issue_slots[8].out_uop.dst_rtype connect issue_slots[6].in_uop.bits.lrs3, issue_slots[8].out_uop.lrs3 connect issue_slots[6].in_uop.bits.lrs2, issue_slots[8].out_uop.lrs2 connect issue_slots[6].in_uop.bits.lrs1, issue_slots[8].out_uop.lrs1 connect issue_slots[6].in_uop.bits.ldst, issue_slots[8].out_uop.ldst connect issue_slots[6].in_uop.bits.ldst_is_rs1, issue_slots[8].out_uop.ldst_is_rs1 connect issue_slots[6].in_uop.bits.csr_cmd, issue_slots[8].out_uop.csr_cmd connect issue_slots[6].in_uop.bits.flush_on_commit, issue_slots[8].out_uop.flush_on_commit connect issue_slots[6].in_uop.bits.is_unique, issue_slots[8].out_uop.is_unique connect issue_slots[6].in_uop.bits.uses_stq, issue_slots[8].out_uop.uses_stq connect issue_slots[6].in_uop.bits.uses_ldq, issue_slots[8].out_uop.uses_ldq connect issue_slots[6].in_uop.bits.mem_signed, issue_slots[8].out_uop.mem_signed connect issue_slots[6].in_uop.bits.mem_size, issue_slots[8].out_uop.mem_size connect issue_slots[6].in_uop.bits.mem_cmd, issue_slots[8].out_uop.mem_cmd connect issue_slots[6].in_uop.bits.exc_cause, issue_slots[8].out_uop.exc_cause connect issue_slots[6].in_uop.bits.exception, issue_slots[8].out_uop.exception connect issue_slots[6].in_uop.bits.stale_pdst, issue_slots[8].out_uop.stale_pdst connect issue_slots[6].in_uop.bits.ppred_busy, issue_slots[8].out_uop.ppred_busy connect issue_slots[6].in_uop.bits.prs3_busy, issue_slots[8].out_uop.prs3_busy connect issue_slots[6].in_uop.bits.prs2_busy, issue_slots[8].out_uop.prs2_busy connect issue_slots[6].in_uop.bits.prs1_busy, issue_slots[8].out_uop.prs1_busy connect issue_slots[6].in_uop.bits.ppred, issue_slots[8].out_uop.ppred connect issue_slots[6].in_uop.bits.prs3, issue_slots[8].out_uop.prs3 connect issue_slots[6].in_uop.bits.prs2, issue_slots[8].out_uop.prs2 connect issue_slots[6].in_uop.bits.prs1, issue_slots[8].out_uop.prs1 connect issue_slots[6].in_uop.bits.pdst, issue_slots[8].out_uop.pdst connect issue_slots[6].in_uop.bits.rxq_idx, issue_slots[8].out_uop.rxq_idx connect issue_slots[6].in_uop.bits.stq_idx, issue_slots[8].out_uop.stq_idx connect issue_slots[6].in_uop.bits.ldq_idx, issue_slots[8].out_uop.ldq_idx connect issue_slots[6].in_uop.bits.rob_idx, issue_slots[8].out_uop.rob_idx connect issue_slots[6].in_uop.bits.fp_ctrl.vec, issue_slots[8].out_uop.fp_ctrl.vec connect issue_slots[6].in_uop.bits.fp_ctrl.wflags, issue_slots[8].out_uop.fp_ctrl.wflags connect issue_slots[6].in_uop.bits.fp_ctrl.sqrt, issue_slots[8].out_uop.fp_ctrl.sqrt connect issue_slots[6].in_uop.bits.fp_ctrl.div, issue_slots[8].out_uop.fp_ctrl.div connect issue_slots[6].in_uop.bits.fp_ctrl.fma, issue_slots[8].out_uop.fp_ctrl.fma connect issue_slots[6].in_uop.bits.fp_ctrl.fastpipe, issue_slots[8].out_uop.fp_ctrl.fastpipe connect issue_slots[6].in_uop.bits.fp_ctrl.toint, issue_slots[8].out_uop.fp_ctrl.toint connect issue_slots[6].in_uop.bits.fp_ctrl.fromint, issue_slots[8].out_uop.fp_ctrl.fromint connect issue_slots[6].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[8].out_uop.fp_ctrl.typeTagOut connect issue_slots[6].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[8].out_uop.fp_ctrl.typeTagIn connect issue_slots[6].in_uop.bits.fp_ctrl.swap23, issue_slots[8].out_uop.fp_ctrl.swap23 connect issue_slots[6].in_uop.bits.fp_ctrl.swap12, issue_slots[8].out_uop.fp_ctrl.swap12 connect issue_slots[6].in_uop.bits.fp_ctrl.ren3, issue_slots[8].out_uop.fp_ctrl.ren3 connect issue_slots[6].in_uop.bits.fp_ctrl.ren2, issue_slots[8].out_uop.fp_ctrl.ren2 connect issue_slots[6].in_uop.bits.fp_ctrl.ren1, issue_slots[8].out_uop.fp_ctrl.ren1 connect issue_slots[6].in_uop.bits.fp_ctrl.wen, issue_slots[8].out_uop.fp_ctrl.wen connect issue_slots[6].in_uop.bits.fp_ctrl.ldst, issue_slots[8].out_uop.fp_ctrl.ldst connect issue_slots[6].in_uop.bits.op2_sel, issue_slots[8].out_uop.op2_sel connect issue_slots[6].in_uop.bits.op1_sel, issue_slots[8].out_uop.op1_sel connect issue_slots[6].in_uop.bits.imm_packed, issue_slots[8].out_uop.imm_packed connect issue_slots[6].in_uop.bits.pimm, issue_slots[8].out_uop.pimm connect issue_slots[6].in_uop.bits.imm_sel, issue_slots[8].out_uop.imm_sel connect issue_slots[6].in_uop.bits.imm_rename, issue_slots[8].out_uop.imm_rename connect issue_slots[6].in_uop.bits.taken, issue_slots[8].out_uop.taken connect issue_slots[6].in_uop.bits.pc_lob, issue_slots[8].out_uop.pc_lob connect issue_slots[6].in_uop.bits.edge_inst, issue_slots[8].out_uop.edge_inst connect issue_slots[6].in_uop.bits.ftq_idx, issue_slots[8].out_uop.ftq_idx connect issue_slots[6].in_uop.bits.is_mov, issue_slots[8].out_uop.is_mov connect issue_slots[6].in_uop.bits.is_rocc, issue_slots[8].out_uop.is_rocc connect issue_slots[6].in_uop.bits.is_sys_pc2epc, issue_slots[8].out_uop.is_sys_pc2epc connect issue_slots[6].in_uop.bits.is_eret, issue_slots[8].out_uop.is_eret connect issue_slots[6].in_uop.bits.is_amo, issue_slots[8].out_uop.is_amo connect issue_slots[6].in_uop.bits.is_sfence, issue_slots[8].out_uop.is_sfence connect issue_slots[6].in_uop.bits.is_fencei, issue_slots[8].out_uop.is_fencei connect issue_slots[6].in_uop.bits.is_fence, issue_slots[8].out_uop.is_fence connect issue_slots[6].in_uop.bits.is_sfb, issue_slots[8].out_uop.is_sfb connect issue_slots[6].in_uop.bits.br_type, issue_slots[8].out_uop.br_type connect issue_slots[6].in_uop.bits.br_tag, issue_slots[8].out_uop.br_tag connect issue_slots[6].in_uop.bits.br_mask, issue_slots[8].out_uop.br_mask connect issue_slots[6].in_uop.bits.dis_col_sel, issue_slots[8].out_uop.dis_col_sel connect issue_slots[6].in_uop.bits.iw_p3_bypass_hint, issue_slots[8].out_uop.iw_p3_bypass_hint connect issue_slots[6].in_uop.bits.iw_p2_bypass_hint, issue_slots[8].out_uop.iw_p2_bypass_hint connect issue_slots[6].in_uop.bits.iw_p1_bypass_hint, issue_slots[8].out_uop.iw_p1_bypass_hint connect issue_slots[6].in_uop.bits.iw_p2_speculative_child, issue_slots[8].out_uop.iw_p2_speculative_child connect issue_slots[6].in_uop.bits.iw_p1_speculative_child, issue_slots[8].out_uop.iw_p1_speculative_child connect issue_slots[6].in_uop.bits.iw_issued_partial_dgen, issue_slots[8].out_uop.iw_issued_partial_dgen connect issue_slots[6].in_uop.bits.iw_issued_partial_agen, issue_slots[8].out_uop.iw_issued_partial_agen connect issue_slots[6].in_uop.bits.iw_issued, issue_slots[8].out_uop.iw_issued connect issue_slots[6].in_uop.bits.fu_code[0], issue_slots[8].out_uop.fu_code[0] connect issue_slots[6].in_uop.bits.fu_code[1], issue_slots[8].out_uop.fu_code[1] connect issue_slots[6].in_uop.bits.fu_code[2], issue_slots[8].out_uop.fu_code[2] connect issue_slots[6].in_uop.bits.fu_code[3], issue_slots[8].out_uop.fu_code[3] connect issue_slots[6].in_uop.bits.fu_code[4], issue_slots[8].out_uop.fu_code[4] connect issue_slots[6].in_uop.bits.fu_code[5], issue_slots[8].out_uop.fu_code[5] connect issue_slots[6].in_uop.bits.fu_code[6], issue_slots[8].out_uop.fu_code[6] connect issue_slots[6].in_uop.bits.fu_code[7], issue_slots[8].out_uop.fu_code[7] connect issue_slots[6].in_uop.bits.fu_code[8], issue_slots[8].out_uop.fu_code[8] connect issue_slots[6].in_uop.bits.fu_code[9], issue_slots[8].out_uop.fu_code[9] connect issue_slots[6].in_uop.bits.iq_type[0], issue_slots[8].out_uop.iq_type[0] connect issue_slots[6].in_uop.bits.iq_type[1], issue_slots[8].out_uop.iq_type[1] connect issue_slots[6].in_uop.bits.iq_type[2], issue_slots[8].out_uop.iq_type[2] connect issue_slots[6].in_uop.bits.iq_type[3], issue_slots[8].out_uop.iq_type[3] connect issue_slots[6].in_uop.bits.debug_pc, issue_slots[8].out_uop.debug_pc connect issue_slots[6].in_uop.bits.is_rvc, issue_slots[8].out_uop.is_rvc connect issue_slots[6].in_uop.bits.debug_inst, issue_slots[8].out_uop.debug_inst connect issue_slots[6].in_uop.bits.inst, issue_slots[8].out_uop.inst node _T_297 = eq(shamts_oh[9], UInt<3>(0h4)) when _T_297 : connect issue_slots[6].in_uop.valid, issue_slots[9].will_be_valid connect issue_slots[6].in_uop.bits.debug_tsrc, issue_slots[9].out_uop.debug_tsrc connect issue_slots[6].in_uop.bits.debug_fsrc, issue_slots[9].out_uop.debug_fsrc connect issue_slots[6].in_uop.bits.bp_xcpt_if, issue_slots[9].out_uop.bp_xcpt_if connect issue_slots[6].in_uop.bits.bp_debug_if, issue_slots[9].out_uop.bp_debug_if connect issue_slots[6].in_uop.bits.xcpt_ma_if, issue_slots[9].out_uop.xcpt_ma_if connect issue_slots[6].in_uop.bits.xcpt_ae_if, issue_slots[9].out_uop.xcpt_ae_if connect issue_slots[6].in_uop.bits.xcpt_pf_if, issue_slots[9].out_uop.xcpt_pf_if connect issue_slots[6].in_uop.bits.fp_typ, issue_slots[9].out_uop.fp_typ connect issue_slots[6].in_uop.bits.fp_rm, issue_slots[9].out_uop.fp_rm connect issue_slots[6].in_uop.bits.fp_val, issue_slots[9].out_uop.fp_val connect issue_slots[6].in_uop.bits.fcn_op, issue_slots[9].out_uop.fcn_op connect issue_slots[6].in_uop.bits.fcn_dw, issue_slots[9].out_uop.fcn_dw connect issue_slots[6].in_uop.bits.frs3_en, issue_slots[9].out_uop.frs3_en connect issue_slots[6].in_uop.bits.lrs2_rtype, issue_slots[9].out_uop.lrs2_rtype connect issue_slots[6].in_uop.bits.lrs1_rtype, issue_slots[9].out_uop.lrs1_rtype connect issue_slots[6].in_uop.bits.dst_rtype, issue_slots[9].out_uop.dst_rtype connect issue_slots[6].in_uop.bits.lrs3, issue_slots[9].out_uop.lrs3 connect issue_slots[6].in_uop.bits.lrs2, issue_slots[9].out_uop.lrs2 connect issue_slots[6].in_uop.bits.lrs1, issue_slots[9].out_uop.lrs1 connect issue_slots[6].in_uop.bits.ldst, issue_slots[9].out_uop.ldst connect issue_slots[6].in_uop.bits.ldst_is_rs1, issue_slots[9].out_uop.ldst_is_rs1 connect issue_slots[6].in_uop.bits.csr_cmd, issue_slots[9].out_uop.csr_cmd connect issue_slots[6].in_uop.bits.flush_on_commit, issue_slots[9].out_uop.flush_on_commit connect issue_slots[6].in_uop.bits.is_unique, issue_slots[9].out_uop.is_unique connect issue_slots[6].in_uop.bits.uses_stq, issue_slots[9].out_uop.uses_stq connect issue_slots[6].in_uop.bits.uses_ldq, issue_slots[9].out_uop.uses_ldq connect issue_slots[6].in_uop.bits.mem_signed, issue_slots[9].out_uop.mem_signed connect issue_slots[6].in_uop.bits.mem_size, issue_slots[9].out_uop.mem_size connect issue_slots[6].in_uop.bits.mem_cmd, issue_slots[9].out_uop.mem_cmd connect issue_slots[6].in_uop.bits.exc_cause, issue_slots[9].out_uop.exc_cause connect issue_slots[6].in_uop.bits.exception, issue_slots[9].out_uop.exception connect issue_slots[6].in_uop.bits.stale_pdst, issue_slots[9].out_uop.stale_pdst connect issue_slots[6].in_uop.bits.ppred_busy, issue_slots[9].out_uop.ppred_busy connect issue_slots[6].in_uop.bits.prs3_busy, issue_slots[9].out_uop.prs3_busy connect issue_slots[6].in_uop.bits.prs2_busy, issue_slots[9].out_uop.prs2_busy connect issue_slots[6].in_uop.bits.prs1_busy, issue_slots[9].out_uop.prs1_busy connect issue_slots[6].in_uop.bits.ppred, issue_slots[9].out_uop.ppred connect issue_slots[6].in_uop.bits.prs3, issue_slots[9].out_uop.prs3 connect issue_slots[6].in_uop.bits.prs2, issue_slots[9].out_uop.prs2 connect issue_slots[6].in_uop.bits.prs1, issue_slots[9].out_uop.prs1 connect issue_slots[6].in_uop.bits.pdst, issue_slots[9].out_uop.pdst connect issue_slots[6].in_uop.bits.rxq_idx, issue_slots[9].out_uop.rxq_idx connect issue_slots[6].in_uop.bits.stq_idx, issue_slots[9].out_uop.stq_idx connect issue_slots[6].in_uop.bits.ldq_idx, issue_slots[9].out_uop.ldq_idx connect issue_slots[6].in_uop.bits.rob_idx, issue_slots[9].out_uop.rob_idx connect issue_slots[6].in_uop.bits.fp_ctrl.vec, issue_slots[9].out_uop.fp_ctrl.vec connect issue_slots[6].in_uop.bits.fp_ctrl.wflags, issue_slots[9].out_uop.fp_ctrl.wflags connect issue_slots[6].in_uop.bits.fp_ctrl.sqrt, issue_slots[9].out_uop.fp_ctrl.sqrt connect issue_slots[6].in_uop.bits.fp_ctrl.div, issue_slots[9].out_uop.fp_ctrl.div connect issue_slots[6].in_uop.bits.fp_ctrl.fma, issue_slots[9].out_uop.fp_ctrl.fma connect issue_slots[6].in_uop.bits.fp_ctrl.fastpipe, issue_slots[9].out_uop.fp_ctrl.fastpipe connect issue_slots[6].in_uop.bits.fp_ctrl.toint, issue_slots[9].out_uop.fp_ctrl.toint connect issue_slots[6].in_uop.bits.fp_ctrl.fromint, issue_slots[9].out_uop.fp_ctrl.fromint connect issue_slots[6].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[9].out_uop.fp_ctrl.typeTagOut connect issue_slots[6].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[9].out_uop.fp_ctrl.typeTagIn connect issue_slots[6].in_uop.bits.fp_ctrl.swap23, issue_slots[9].out_uop.fp_ctrl.swap23 connect issue_slots[6].in_uop.bits.fp_ctrl.swap12, issue_slots[9].out_uop.fp_ctrl.swap12 connect issue_slots[6].in_uop.bits.fp_ctrl.ren3, issue_slots[9].out_uop.fp_ctrl.ren3 connect issue_slots[6].in_uop.bits.fp_ctrl.ren2, issue_slots[9].out_uop.fp_ctrl.ren2 connect issue_slots[6].in_uop.bits.fp_ctrl.ren1, issue_slots[9].out_uop.fp_ctrl.ren1 connect issue_slots[6].in_uop.bits.fp_ctrl.wen, issue_slots[9].out_uop.fp_ctrl.wen connect issue_slots[6].in_uop.bits.fp_ctrl.ldst, issue_slots[9].out_uop.fp_ctrl.ldst connect issue_slots[6].in_uop.bits.op2_sel, issue_slots[9].out_uop.op2_sel connect issue_slots[6].in_uop.bits.op1_sel, issue_slots[9].out_uop.op1_sel connect issue_slots[6].in_uop.bits.imm_packed, issue_slots[9].out_uop.imm_packed connect issue_slots[6].in_uop.bits.pimm, issue_slots[9].out_uop.pimm connect issue_slots[6].in_uop.bits.imm_sel, issue_slots[9].out_uop.imm_sel connect issue_slots[6].in_uop.bits.imm_rename, issue_slots[9].out_uop.imm_rename connect issue_slots[6].in_uop.bits.taken, issue_slots[9].out_uop.taken connect issue_slots[6].in_uop.bits.pc_lob, issue_slots[9].out_uop.pc_lob connect issue_slots[6].in_uop.bits.edge_inst, issue_slots[9].out_uop.edge_inst connect issue_slots[6].in_uop.bits.ftq_idx, issue_slots[9].out_uop.ftq_idx connect issue_slots[6].in_uop.bits.is_mov, issue_slots[9].out_uop.is_mov connect issue_slots[6].in_uop.bits.is_rocc, issue_slots[9].out_uop.is_rocc connect issue_slots[6].in_uop.bits.is_sys_pc2epc, issue_slots[9].out_uop.is_sys_pc2epc connect issue_slots[6].in_uop.bits.is_eret, issue_slots[9].out_uop.is_eret connect issue_slots[6].in_uop.bits.is_amo, issue_slots[9].out_uop.is_amo connect issue_slots[6].in_uop.bits.is_sfence, issue_slots[9].out_uop.is_sfence connect issue_slots[6].in_uop.bits.is_fencei, issue_slots[9].out_uop.is_fencei connect issue_slots[6].in_uop.bits.is_fence, issue_slots[9].out_uop.is_fence connect issue_slots[6].in_uop.bits.is_sfb, issue_slots[9].out_uop.is_sfb connect issue_slots[6].in_uop.bits.br_type, issue_slots[9].out_uop.br_type connect issue_slots[6].in_uop.bits.br_tag, issue_slots[9].out_uop.br_tag connect issue_slots[6].in_uop.bits.br_mask, issue_slots[9].out_uop.br_mask connect issue_slots[6].in_uop.bits.dis_col_sel, issue_slots[9].out_uop.dis_col_sel connect issue_slots[6].in_uop.bits.iw_p3_bypass_hint, issue_slots[9].out_uop.iw_p3_bypass_hint connect issue_slots[6].in_uop.bits.iw_p2_bypass_hint, issue_slots[9].out_uop.iw_p2_bypass_hint connect issue_slots[6].in_uop.bits.iw_p1_bypass_hint, issue_slots[9].out_uop.iw_p1_bypass_hint connect issue_slots[6].in_uop.bits.iw_p2_speculative_child, issue_slots[9].out_uop.iw_p2_speculative_child connect issue_slots[6].in_uop.bits.iw_p1_speculative_child, issue_slots[9].out_uop.iw_p1_speculative_child connect issue_slots[6].in_uop.bits.iw_issued_partial_dgen, issue_slots[9].out_uop.iw_issued_partial_dgen connect issue_slots[6].in_uop.bits.iw_issued_partial_agen, issue_slots[9].out_uop.iw_issued_partial_agen connect issue_slots[6].in_uop.bits.iw_issued, issue_slots[9].out_uop.iw_issued connect issue_slots[6].in_uop.bits.fu_code[0], issue_slots[9].out_uop.fu_code[0] connect issue_slots[6].in_uop.bits.fu_code[1], issue_slots[9].out_uop.fu_code[1] connect issue_slots[6].in_uop.bits.fu_code[2], issue_slots[9].out_uop.fu_code[2] connect issue_slots[6].in_uop.bits.fu_code[3], issue_slots[9].out_uop.fu_code[3] connect issue_slots[6].in_uop.bits.fu_code[4], issue_slots[9].out_uop.fu_code[4] connect issue_slots[6].in_uop.bits.fu_code[5], issue_slots[9].out_uop.fu_code[5] connect issue_slots[6].in_uop.bits.fu_code[6], issue_slots[9].out_uop.fu_code[6] connect issue_slots[6].in_uop.bits.fu_code[7], issue_slots[9].out_uop.fu_code[7] connect issue_slots[6].in_uop.bits.fu_code[8], issue_slots[9].out_uop.fu_code[8] connect issue_slots[6].in_uop.bits.fu_code[9], issue_slots[9].out_uop.fu_code[9] connect issue_slots[6].in_uop.bits.iq_type[0], issue_slots[9].out_uop.iq_type[0] connect issue_slots[6].in_uop.bits.iq_type[1], issue_slots[9].out_uop.iq_type[1] connect issue_slots[6].in_uop.bits.iq_type[2], issue_slots[9].out_uop.iq_type[2] connect issue_slots[6].in_uop.bits.iq_type[3], issue_slots[9].out_uop.iq_type[3] connect issue_slots[6].in_uop.bits.debug_pc, issue_slots[9].out_uop.debug_pc connect issue_slots[6].in_uop.bits.is_rvc, issue_slots[9].out_uop.is_rvc connect issue_slots[6].in_uop.bits.debug_inst, issue_slots[9].out_uop.debug_inst connect issue_slots[6].in_uop.bits.inst, issue_slots[9].out_uop.inst node _issue_slots_6_clear_T = neq(shamts_oh[6], UInt<1>(0h0)) connect issue_slots[6].clear, _issue_slots_6_clear_T connect issue_slots[7].in_uop.valid, UInt<1>(0h0) connect issue_slots[7].in_uop.bits.debug_tsrc, issue_slots[8].out_uop.debug_tsrc connect issue_slots[7].in_uop.bits.debug_fsrc, issue_slots[8].out_uop.debug_fsrc connect issue_slots[7].in_uop.bits.bp_xcpt_if, issue_slots[8].out_uop.bp_xcpt_if connect issue_slots[7].in_uop.bits.bp_debug_if, issue_slots[8].out_uop.bp_debug_if connect issue_slots[7].in_uop.bits.xcpt_ma_if, issue_slots[8].out_uop.xcpt_ma_if connect issue_slots[7].in_uop.bits.xcpt_ae_if, issue_slots[8].out_uop.xcpt_ae_if connect issue_slots[7].in_uop.bits.xcpt_pf_if, issue_slots[8].out_uop.xcpt_pf_if connect issue_slots[7].in_uop.bits.fp_typ, issue_slots[8].out_uop.fp_typ connect issue_slots[7].in_uop.bits.fp_rm, issue_slots[8].out_uop.fp_rm connect issue_slots[7].in_uop.bits.fp_val, issue_slots[8].out_uop.fp_val connect issue_slots[7].in_uop.bits.fcn_op, issue_slots[8].out_uop.fcn_op connect issue_slots[7].in_uop.bits.fcn_dw, issue_slots[8].out_uop.fcn_dw connect issue_slots[7].in_uop.bits.frs3_en, issue_slots[8].out_uop.frs3_en connect issue_slots[7].in_uop.bits.lrs2_rtype, issue_slots[8].out_uop.lrs2_rtype connect issue_slots[7].in_uop.bits.lrs1_rtype, issue_slots[8].out_uop.lrs1_rtype connect issue_slots[7].in_uop.bits.dst_rtype, issue_slots[8].out_uop.dst_rtype connect issue_slots[7].in_uop.bits.lrs3, issue_slots[8].out_uop.lrs3 connect issue_slots[7].in_uop.bits.lrs2, issue_slots[8].out_uop.lrs2 connect issue_slots[7].in_uop.bits.lrs1, issue_slots[8].out_uop.lrs1 connect issue_slots[7].in_uop.bits.ldst, issue_slots[8].out_uop.ldst connect issue_slots[7].in_uop.bits.ldst_is_rs1, issue_slots[8].out_uop.ldst_is_rs1 connect issue_slots[7].in_uop.bits.csr_cmd, issue_slots[8].out_uop.csr_cmd connect issue_slots[7].in_uop.bits.flush_on_commit, issue_slots[8].out_uop.flush_on_commit connect issue_slots[7].in_uop.bits.is_unique, issue_slots[8].out_uop.is_unique connect issue_slots[7].in_uop.bits.uses_stq, issue_slots[8].out_uop.uses_stq connect issue_slots[7].in_uop.bits.uses_ldq, issue_slots[8].out_uop.uses_ldq connect issue_slots[7].in_uop.bits.mem_signed, issue_slots[8].out_uop.mem_signed connect issue_slots[7].in_uop.bits.mem_size, issue_slots[8].out_uop.mem_size connect issue_slots[7].in_uop.bits.mem_cmd, issue_slots[8].out_uop.mem_cmd connect issue_slots[7].in_uop.bits.exc_cause, issue_slots[8].out_uop.exc_cause connect issue_slots[7].in_uop.bits.exception, issue_slots[8].out_uop.exception connect issue_slots[7].in_uop.bits.stale_pdst, issue_slots[8].out_uop.stale_pdst connect issue_slots[7].in_uop.bits.ppred_busy, issue_slots[8].out_uop.ppred_busy connect issue_slots[7].in_uop.bits.prs3_busy, issue_slots[8].out_uop.prs3_busy connect issue_slots[7].in_uop.bits.prs2_busy, issue_slots[8].out_uop.prs2_busy connect issue_slots[7].in_uop.bits.prs1_busy, issue_slots[8].out_uop.prs1_busy connect issue_slots[7].in_uop.bits.ppred, issue_slots[8].out_uop.ppred connect issue_slots[7].in_uop.bits.prs3, issue_slots[8].out_uop.prs3 connect issue_slots[7].in_uop.bits.prs2, issue_slots[8].out_uop.prs2 connect issue_slots[7].in_uop.bits.prs1, issue_slots[8].out_uop.prs1 connect issue_slots[7].in_uop.bits.pdst, issue_slots[8].out_uop.pdst connect issue_slots[7].in_uop.bits.rxq_idx, issue_slots[8].out_uop.rxq_idx connect issue_slots[7].in_uop.bits.stq_idx, issue_slots[8].out_uop.stq_idx connect issue_slots[7].in_uop.bits.ldq_idx, issue_slots[8].out_uop.ldq_idx connect issue_slots[7].in_uop.bits.rob_idx, issue_slots[8].out_uop.rob_idx connect issue_slots[7].in_uop.bits.fp_ctrl.vec, issue_slots[8].out_uop.fp_ctrl.vec connect issue_slots[7].in_uop.bits.fp_ctrl.wflags, issue_slots[8].out_uop.fp_ctrl.wflags connect issue_slots[7].in_uop.bits.fp_ctrl.sqrt, issue_slots[8].out_uop.fp_ctrl.sqrt connect issue_slots[7].in_uop.bits.fp_ctrl.div, issue_slots[8].out_uop.fp_ctrl.div connect issue_slots[7].in_uop.bits.fp_ctrl.fma, issue_slots[8].out_uop.fp_ctrl.fma connect issue_slots[7].in_uop.bits.fp_ctrl.fastpipe, issue_slots[8].out_uop.fp_ctrl.fastpipe connect issue_slots[7].in_uop.bits.fp_ctrl.toint, issue_slots[8].out_uop.fp_ctrl.toint connect issue_slots[7].in_uop.bits.fp_ctrl.fromint, issue_slots[8].out_uop.fp_ctrl.fromint connect issue_slots[7].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[8].out_uop.fp_ctrl.typeTagOut connect issue_slots[7].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[8].out_uop.fp_ctrl.typeTagIn connect issue_slots[7].in_uop.bits.fp_ctrl.swap23, issue_slots[8].out_uop.fp_ctrl.swap23 connect issue_slots[7].in_uop.bits.fp_ctrl.swap12, issue_slots[8].out_uop.fp_ctrl.swap12 connect issue_slots[7].in_uop.bits.fp_ctrl.ren3, issue_slots[8].out_uop.fp_ctrl.ren3 connect issue_slots[7].in_uop.bits.fp_ctrl.ren2, issue_slots[8].out_uop.fp_ctrl.ren2 connect issue_slots[7].in_uop.bits.fp_ctrl.ren1, issue_slots[8].out_uop.fp_ctrl.ren1 connect issue_slots[7].in_uop.bits.fp_ctrl.wen, issue_slots[8].out_uop.fp_ctrl.wen connect issue_slots[7].in_uop.bits.fp_ctrl.ldst, issue_slots[8].out_uop.fp_ctrl.ldst connect issue_slots[7].in_uop.bits.op2_sel, issue_slots[8].out_uop.op2_sel connect issue_slots[7].in_uop.bits.op1_sel, issue_slots[8].out_uop.op1_sel connect issue_slots[7].in_uop.bits.imm_packed, issue_slots[8].out_uop.imm_packed connect issue_slots[7].in_uop.bits.pimm, issue_slots[8].out_uop.pimm connect issue_slots[7].in_uop.bits.imm_sel, issue_slots[8].out_uop.imm_sel connect issue_slots[7].in_uop.bits.imm_rename, issue_slots[8].out_uop.imm_rename connect issue_slots[7].in_uop.bits.taken, issue_slots[8].out_uop.taken connect issue_slots[7].in_uop.bits.pc_lob, issue_slots[8].out_uop.pc_lob connect issue_slots[7].in_uop.bits.edge_inst, issue_slots[8].out_uop.edge_inst connect issue_slots[7].in_uop.bits.ftq_idx, issue_slots[8].out_uop.ftq_idx connect issue_slots[7].in_uop.bits.is_mov, issue_slots[8].out_uop.is_mov connect issue_slots[7].in_uop.bits.is_rocc, issue_slots[8].out_uop.is_rocc connect issue_slots[7].in_uop.bits.is_sys_pc2epc, issue_slots[8].out_uop.is_sys_pc2epc connect issue_slots[7].in_uop.bits.is_eret, issue_slots[8].out_uop.is_eret connect issue_slots[7].in_uop.bits.is_amo, issue_slots[8].out_uop.is_amo connect issue_slots[7].in_uop.bits.is_sfence, issue_slots[8].out_uop.is_sfence connect issue_slots[7].in_uop.bits.is_fencei, issue_slots[8].out_uop.is_fencei connect issue_slots[7].in_uop.bits.is_fence, issue_slots[8].out_uop.is_fence connect issue_slots[7].in_uop.bits.is_sfb, issue_slots[8].out_uop.is_sfb connect issue_slots[7].in_uop.bits.br_type, issue_slots[8].out_uop.br_type connect issue_slots[7].in_uop.bits.br_tag, issue_slots[8].out_uop.br_tag connect issue_slots[7].in_uop.bits.br_mask, issue_slots[8].out_uop.br_mask connect issue_slots[7].in_uop.bits.dis_col_sel, issue_slots[8].out_uop.dis_col_sel connect issue_slots[7].in_uop.bits.iw_p3_bypass_hint, issue_slots[8].out_uop.iw_p3_bypass_hint connect issue_slots[7].in_uop.bits.iw_p2_bypass_hint, issue_slots[8].out_uop.iw_p2_bypass_hint connect issue_slots[7].in_uop.bits.iw_p1_bypass_hint, issue_slots[8].out_uop.iw_p1_bypass_hint connect issue_slots[7].in_uop.bits.iw_p2_speculative_child, issue_slots[8].out_uop.iw_p2_speculative_child connect issue_slots[7].in_uop.bits.iw_p1_speculative_child, issue_slots[8].out_uop.iw_p1_speculative_child connect issue_slots[7].in_uop.bits.iw_issued_partial_dgen, issue_slots[8].out_uop.iw_issued_partial_dgen connect issue_slots[7].in_uop.bits.iw_issued_partial_agen, issue_slots[8].out_uop.iw_issued_partial_agen connect issue_slots[7].in_uop.bits.iw_issued, issue_slots[8].out_uop.iw_issued connect issue_slots[7].in_uop.bits.fu_code[0], issue_slots[8].out_uop.fu_code[0] connect issue_slots[7].in_uop.bits.fu_code[1], issue_slots[8].out_uop.fu_code[1] connect issue_slots[7].in_uop.bits.fu_code[2], issue_slots[8].out_uop.fu_code[2] connect issue_slots[7].in_uop.bits.fu_code[3], issue_slots[8].out_uop.fu_code[3] connect issue_slots[7].in_uop.bits.fu_code[4], issue_slots[8].out_uop.fu_code[4] connect issue_slots[7].in_uop.bits.fu_code[5], issue_slots[8].out_uop.fu_code[5] connect issue_slots[7].in_uop.bits.fu_code[6], issue_slots[8].out_uop.fu_code[6] connect issue_slots[7].in_uop.bits.fu_code[7], issue_slots[8].out_uop.fu_code[7] connect issue_slots[7].in_uop.bits.fu_code[8], issue_slots[8].out_uop.fu_code[8] connect issue_slots[7].in_uop.bits.fu_code[9], issue_slots[8].out_uop.fu_code[9] connect issue_slots[7].in_uop.bits.iq_type[0], issue_slots[8].out_uop.iq_type[0] connect issue_slots[7].in_uop.bits.iq_type[1], issue_slots[8].out_uop.iq_type[1] connect issue_slots[7].in_uop.bits.iq_type[2], issue_slots[8].out_uop.iq_type[2] connect issue_slots[7].in_uop.bits.iq_type[3], issue_slots[8].out_uop.iq_type[3] connect issue_slots[7].in_uop.bits.debug_pc, issue_slots[8].out_uop.debug_pc connect issue_slots[7].in_uop.bits.is_rvc, issue_slots[8].out_uop.is_rvc connect issue_slots[7].in_uop.bits.debug_inst, issue_slots[8].out_uop.debug_inst connect issue_slots[7].in_uop.bits.inst, issue_slots[8].out_uop.inst node _T_298 = eq(shamts_oh[8], UInt<1>(0h1)) when _T_298 : connect issue_slots[7].in_uop.valid, issue_slots[8].will_be_valid connect issue_slots[7].in_uop.bits.debug_tsrc, issue_slots[8].out_uop.debug_tsrc connect issue_slots[7].in_uop.bits.debug_fsrc, issue_slots[8].out_uop.debug_fsrc connect issue_slots[7].in_uop.bits.bp_xcpt_if, issue_slots[8].out_uop.bp_xcpt_if connect issue_slots[7].in_uop.bits.bp_debug_if, issue_slots[8].out_uop.bp_debug_if connect issue_slots[7].in_uop.bits.xcpt_ma_if, issue_slots[8].out_uop.xcpt_ma_if connect issue_slots[7].in_uop.bits.xcpt_ae_if, issue_slots[8].out_uop.xcpt_ae_if connect issue_slots[7].in_uop.bits.xcpt_pf_if, issue_slots[8].out_uop.xcpt_pf_if connect issue_slots[7].in_uop.bits.fp_typ, issue_slots[8].out_uop.fp_typ connect issue_slots[7].in_uop.bits.fp_rm, issue_slots[8].out_uop.fp_rm connect issue_slots[7].in_uop.bits.fp_val, issue_slots[8].out_uop.fp_val connect issue_slots[7].in_uop.bits.fcn_op, issue_slots[8].out_uop.fcn_op connect issue_slots[7].in_uop.bits.fcn_dw, issue_slots[8].out_uop.fcn_dw connect issue_slots[7].in_uop.bits.frs3_en, issue_slots[8].out_uop.frs3_en connect issue_slots[7].in_uop.bits.lrs2_rtype, issue_slots[8].out_uop.lrs2_rtype connect issue_slots[7].in_uop.bits.lrs1_rtype, issue_slots[8].out_uop.lrs1_rtype connect issue_slots[7].in_uop.bits.dst_rtype, issue_slots[8].out_uop.dst_rtype connect issue_slots[7].in_uop.bits.lrs3, issue_slots[8].out_uop.lrs3 connect issue_slots[7].in_uop.bits.lrs2, issue_slots[8].out_uop.lrs2 connect issue_slots[7].in_uop.bits.lrs1, issue_slots[8].out_uop.lrs1 connect issue_slots[7].in_uop.bits.ldst, issue_slots[8].out_uop.ldst connect issue_slots[7].in_uop.bits.ldst_is_rs1, issue_slots[8].out_uop.ldst_is_rs1 connect issue_slots[7].in_uop.bits.csr_cmd, issue_slots[8].out_uop.csr_cmd connect issue_slots[7].in_uop.bits.flush_on_commit, issue_slots[8].out_uop.flush_on_commit connect issue_slots[7].in_uop.bits.is_unique, issue_slots[8].out_uop.is_unique connect issue_slots[7].in_uop.bits.uses_stq, issue_slots[8].out_uop.uses_stq connect issue_slots[7].in_uop.bits.uses_ldq, issue_slots[8].out_uop.uses_ldq connect issue_slots[7].in_uop.bits.mem_signed, issue_slots[8].out_uop.mem_signed connect issue_slots[7].in_uop.bits.mem_size, issue_slots[8].out_uop.mem_size connect issue_slots[7].in_uop.bits.mem_cmd, issue_slots[8].out_uop.mem_cmd connect issue_slots[7].in_uop.bits.exc_cause, issue_slots[8].out_uop.exc_cause connect issue_slots[7].in_uop.bits.exception, issue_slots[8].out_uop.exception connect issue_slots[7].in_uop.bits.stale_pdst, issue_slots[8].out_uop.stale_pdst connect issue_slots[7].in_uop.bits.ppred_busy, issue_slots[8].out_uop.ppred_busy connect issue_slots[7].in_uop.bits.prs3_busy, issue_slots[8].out_uop.prs3_busy connect issue_slots[7].in_uop.bits.prs2_busy, issue_slots[8].out_uop.prs2_busy connect issue_slots[7].in_uop.bits.prs1_busy, issue_slots[8].out_uop.prs1_busy connect issue_slots[7].in_uop.bits.ppred, issue_slots[8].out_uop.ppred connect issue_slots[7].in_uop.bits.prs3, issue_slots[8].out_uop.prs3 connect issue_slots[7].in_uop.bits.prs2, issue_slots[8].out_uop.prs2 connect issue_slots[7].in_uop.bits.prs1, issue_slots[8].out_uop.prs1 connect issue_slots[7].in_uop.bits.pdst, issue_slots[8].out_uop.pdst connect issue_slots[7].in_uop.bits.rxq_idx, issue_slots[8].out_uop.rxq_idx connect issue_slots[7].in_uop.bits.stq_idx, issue_slots[8].out_uop.stq_idx connect issue_slots[7].in_uop.bits.ldq_idx, issue_slots[8].out_uop.ldq_idx connect issue_slots[7].in_uop.bits.rob_idx, issue_slots[8].out_uop.rob_idx connect issue_slots[7].in_uop.bits.fp_ctrl.vec, issue_slots[8].out_uop.fp_ctrl.vec connect issue_slots[7].in_uop.bits.fp_ctrl.wflags, issue_slots[8].out_uop.fp_ctrl.wflags connect issue_slots[7].in_uop.bits.fp_ctrl.sqrt, issue_slots[8].out_uop.fp_ctrl.sqrt connect issue_slots[7].in_uop.bits.fp_ctrl.div, issue_slots[8].out_uop.fp_ctrl.div connect issue_slots[7].in_uop.bits.fp_ctrl.fma, issue_slots[8].out_uop.fp_ctrl.fma connect issue_slots[7].in_uop.bits.fp_ctrl.fastpipe, issue_slots[8].out_uop.fp_ctrl.fastpipe connect issue_slots[7].in_uop.bits.fp_ctrl.toint, issue_slots[8].out_uop.fp_ctrl.toint connect issue_slots[7].in_uop.bits.fp_ctrl.fromint, issue_slots[8].out_uop.fp_ctrl.fromint connect issue_slots[7].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[8].out_uop.fp_ctrl.typeTagOut connect issue_slots[7].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[8].out_uop.fp_ctrl.typeTagIn connect issue_slots[7].in_uop.bits.fp_ctrl.swap23, issue_slots[8].out_uop.fp_ctrl.swap23 connect issue_slots[7].in_uop.bits.fp_ctrl.swap12, issue_slots[8].out_uop.fp_ctrl.swap12 connect issue_slots[7].in_uop.bits.fp_ctrl.ren3, issue_slots[8].out_uop.fp_ctrl.ren3 connect issue_slots[7].in_uop.bits.fp_ctrl.ren2, issue_slots[8].out_uop.fp_ctrl.ren2 connect issue_slots[7].in_uop.bits.fp_ctrl.ren1, issue_slots[8].out_uop.fp_ctrl.ren1 connect issue_slots[7].in_uop.bits.fp_ctrl.wen, issue_slots[8].out_uop.fp_ctrl.wen connect issue_slots[7].in_uop.bits.fp_ctrl.ldst, issue_slots[8].out_uop.fp_ctrl.ldst connect issue_slots[7].in_uop.bits.op2_sel, issue_slots[8].out_uop.op2_sel connect issue_slots[7].in_uop.bits.op1_sel, issue_slots[8].out_uop.op1_sel connect issue_slots[7].in_uop.bits.imm_packed, issue_slots[8].out_uop.imm_packed connect issue_slots[7].in_uop.bits.pimm, issue_slots[8].out_uop.pimm connect issue_slots[7].in_uop.bits.imm_sel, issue_slots[8].out_uop.imm_sel connect issue_slots[7].in_uop.bits.imm_rename, issue_slots[8].out_uop.imm_rename connect issue_slots[7].in_uop.bits.taken, issue_slots[8].out_uop.taken connect issue_slots[7].in_uop.bits.pc_lob, issue_slots[8].out_uop.pc_lob connect issue_slots[7].in_uop.bits.edge_inst, issue_slots[8].out_uop.edge_inst connect issue_slots[7].in_uop.bits.ftq_idx, issue_slots[8].out_uop.ftq_idx connect issue_slots[7].in_uop.bits.is_mov, issue_slots[8].out_uop.is_mov connect issue_slots[7].in_uop.bits.is_rocc, issue_slots[8].out_uop.is_rocc connect issue_slots[7].in_uop.bits.is_sys_pc2epc, issue_slots[8].out_uop.is_sys_pc2epc connect issue_slots[7].in_uop.bits.is_eret, issue_slots[8].out_uop.is_eret connect issue_slots[7].in_uop.bits.is_amo, issue_slots[8].out_uop.is_amo connect issue_slots[7].in_uop.bits.is_sfence, issue_slots[8].out_uop.is_sfence connect issue_slots[7].in_uop.bits.is_fencei, issue_slots[8].out_uop.is_fencei connect issue_slots[7].in_uop.bits.is_fence, issue_slots[8].out_uop.is_fence connect issue_slots[7].in_uop.bits.is_sfb, issue_slots[8].out_uop.is_sfb connect issue_slots[7].in_uop.bits.br_type, issue_slots[8].out_uop.br_type connect issue_slots[7].in_uop.bits.br_tag, issue_slots[8].out_uop.br_tag connect issue_slots[7].in_uop.bits.br_mask, issue_slots[8].out_uop.br_mask connect issue_slots[7].in_uop.bits.dis_col_sel, issue_slots[8].out_uop.dis_col_sel connect issue_slots[7].in_uop.bits.iw_p3_bypass_hint, issue_slots[8].out_uop.iw_p3_bypass_hint connect issue_slots[7].in_uop.bits.iw_p2_bypass_hint, issue_slots[8].out_uop.iw_p2_bypass_hint connect issue_slots[7].in_uop.bits.iw_p1_bypass_hint, issue_slots[8].out_uop.iw_p1_bypass_hint connect issue_slots[7].in_uop.bits.iw_p2_speculative_child, issue_slots[8].out_uop.iw_p2_speculative_child connect issue_slots[7].in_uop.bits.iw_p1_speculative_child, issue_slots[8].out_uop.iw_p1_speculative_child connect issue_slots[7].in_uop.bits.iw_issued_partial_dgen, issue_slots[8].out_uop.iw_issued_partial_dgen connect issue_slots[7].in_uop.bits.iw_issued_partial_agen, issue_slots[8].out_uop.iw_issued_partial_agen connect issue_slots[7].in_uop.bits.iw_issued, issue_slots[8].out_uop.iw_issued connect issue_slots[7].in_uop.bits.fu_code[0], issue_slots[8].out_uop.fu_code[0] connect issue_slots[7].in_uop.bits.fu_code[1], issue_slots[8].out_uop.fu_code[1] connect issue_slots[7].in_uop.bits.fu_code[2], issue_slots[8].out_uop.fu_code[2] connect issue_slots[7].in_uop.bits.fu_code[3], issue_slots[8].out_uop.fu_code[3] connect issue_slots[7].in_uop.bits.fu_code[4], issue_slots[8].out_uop.fu_code[4] connect issue_slots[7].in_uop.bits.fu_code[5], issue_slots[8].out_uop.fu_code[5] connect issue_slots[7].in_uop.bits.fu_code[6], issue_slots[8].out_uop.fu_code[6] connect issue_slots[7].in_uop.bits.fu_code[7], issue_slots[8].out_uop.fu_code[7] connect issue_slots[7].in_uop.bits.fu_code[8], issue_slots[8].out_uop.fu_code[8] connect issue_slots[7].in_uop.bits.fu_code[9], issue_slots[8].out_uop.fu_code[9] connect issue_slots[7].in_uop.bits.iq_type[0], issue_slots[8].out_uop.iq_type[0] connect issue_slots[7].in_uop.bits.iq_type[1], issue_slots[8].out_uop.iq_type[1] connect issue_slots[7].in_uop.bits.iq_type[2], issue_slots[8].out_uop.iq_type[2] connect issue_slots[7].in_uop.bits.iq_type[3], issue_slots[8].out_uop.iq_type[3] connect issue_slots[7].in_uop.bits.debug_pc, issue_slots[8].out_uop.debug_pc connect issue_slots[7].in_uop.bits.is_rvc, issue_slots[8].out_uop.is_rvc connect issue_slots[7].in_uop.bits.debug_inst, issue_slots[8].out_uop.debug_inst connect issue_slots[7].in_uop.bits.inst, issue_slots[8].out_uop.inst node _T_299 = eq(shamts_oh[9], UInt<2>(0h2)) when _T_299 : connect issue_slots[7].in_uop.valid, issue_slots[9].will_be_valid connect issue_slots[7].in_uop.bits.debug_tsrc, issue_slots[9].out_uop.debug_tsrc connect issue_slots[7].in_uop.bits.debug_fsrc, issue_slots[9].out_uop.debug_fsrc connect issue_slots[7].in_uop.bits.bp_xcpt_if, issue_slots[9].out_uop.bp_xcpt_if connect issue_slots[7].in_uop.bits.bp_debug_if, issue_slots[9].out_uop.bp_debug_if connect issue_slots[7].in_uop.bits.xcpt_ma_if, issue_slots[9].out_uop.xcpt_ma_if connect issue_slots[7].in_uop.bits.xcpt_ae_if, issue_slots[9].out_uop.xcpt_ae_if connect issue_slots[7].in_uop.bits.xcpt_pf_if, issue_slots[9].out_uop.xcpt_pf_if connect issue_slots[7].in_uop.bits.fp_typ, issue_slots[9].out_uop.fp_typ connect issue_slots[7].in_uop.bits.fp_rm, issue_slots[9].out_uop.fp_rm connect issue_slots[7].in_uop.bits.fp_val, issue_slots[9].out_uop.fp_val connect issue_slots[7].in_uop.bits.fcn_op, issue_slots[9].out_uop.fcn_op connect issue_slots[7].in_uop.bits.fcn_dw, issue_slots[9].out_uop.fcn_dw connect issue_slots[7].in_uop.bits.frs3_en, issue_slots[9].out_uop.frs3_en connect issue_slots[7].in_uop.bits.lrs2_rtype, issue_slots[9].out_uop.lrs2_rtype connect issue_slots[7].in_uop.bits.lrs1_rtype, issue_slots[9].out_uop.lrs1_rtype connect issue_slots[7].in_uop.bits.dst_rtype, issue_slots[9].out_uop.dst_rtype connect issue_slots[7].in_uop.bits.lrs3, issue_slots[9].out_uop.lrs3 connect issue_slots[7].in_uop.bits.lrs2, issue_slots[9].out_uop.lrs2 connect issue_slots[7].in_uop.bits.lrs1, issue_slots[9].out_uop.lrs1 connect issue_slots[7].in_uop.bits.ldst, issue_slots[9].out_uop.ldst connect issue_slots[7].in_uop.bits.ldst_is_rs1, issue_slots[9].out_uop.ldst_is_rs1 connect issue_slots[7].in_uop.bits.csr_cmd, issue_slots[9].out_uop.csr_cmd connect issue_slots[7].in_uop.bits.flush_on_commit, issue_slots[9].out_uop.flush_on_commit connect issue_slots[7].in_uop.bits.is_unique, issue_slots[9].out_uop.is_unique connect issue_slots[7].in_uop.bits.uses_stq, issue_slots[9].out_uop.uses_stq connect issue_slots[7].in_uop.bits.uses_ldq, issue_slots[9].out_uop.uses_ldq connect issue_slots[7].in_uop.bits.mem_signed, issue_slots[9].out_uop.mem_signed connect issue_slots[7].in_uop.bits.mem_size, issue_slots[9].out_uop.mem_size connect issue_slots[7].in_uop.bits.mem_cmd, issue_slots[9].out_uop.mem_cmd connect issue_slots[7].in_uop.bits.exc_cause, issue_slots[9].out_uop.exc_cause connect issue_slots[7].in_uop.bits.exception, issue_slots[9].out_uop.exception connect issue_slots[7].in_uop.bits.stale_pdst, issue_slots[9].out_uop.stale_pdst connect issue_slots[7].in_uop.bits.ppred_busy, issue_slots[9].out_uop.ppred_busy connect issue_slots[7].in_uop.bits.prs3_busy, issue_slots[9].out_uop.prs3_busy connect issue_slots[7].in_uop.bits.prs2_busy, issue_slots[9].out_uop.prs2_busy connect issue_slots[7].in_uop.bits.prs1_busy, issue_slots[9].out_uop.prs1_busy connect issue_slots[7].in_uop.bits.ppred, issue_slots[9].out_uop.ppred connect issue_slots[7].in_uop.bits.prs3, issue_slots[9].out_uop.prs3 connect issue_slots[7].in_uop.bits.prs2, issue_slots[9].out_uop.prs2 connect issue_slots[7].in_uop.bits.prs1, issue_slots[9].out_uop.prs1 connect issue_slots[7].in_uop.bits.pdst, issue_slots[9].out_uop.pdst connect issue_slots[7].in_uop.bits.rxq_idx, issue_slots[9].out_uop.rxq_idx connect issue_slots[7].in_uop.bits.stq_idx, issue_slots[9].out_uop.stq_idx connect issue_slots[7].in_uop.bits.ldq_idx, issue_slots[9].out_uop.ldq_idx connect issue_slots[7].in_uop.bits.rob_idx, issue_slots[9].out_uop.rob_idx connect issue_slots[7].in_uop.bits.fp_ctrl.vec, issue_slots[9].out_uop.fp_ctrl.vec connect issue_slots[7].in_uop.bits.fp_ctrl.wflags, issue_slots[9].out_uop.fp_ctrl.wflags connect issue_slots[7].in_uop.bits.fp_ctrl.sqrt, issue_slots[9].out_uop.fp_ctrl.sqrt connect issue_slots[7].in_uop.bits.fp_ctrl.div, issue_slots[9].out_uop.fp_ctrl.div connect issue_slots[7].in_uop.bits.fp_ctrl.fma, issue_slots[9].out_uop.fp_ctrl.fma connect issue_slots[7].in_uop.bits.fp_ctrl.fastpipe, issue_slots[9].out_uop.fp_ctrl.fastpipe connect issue_slots[7].in_uop.bits.fp_ctrl.toint, issue_slots[9].out_uop.fp_ctrl.toint connect issue_slots[7].in_uop.bits.fp_ctrl.fromint, issue_slots[9].out_uop.fp_ctrl.fromint connect issue_slots[7].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[9].out_uop.fp_ctrl.typeTagOut connect issue_slots[7].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[9].out_uop.fp_ctrl.typeTagIn connect issue_slots[7].in_uop.bits.fp_ctrl.swap23, issue_slots[9].out_uop.fp_ctrl.swap23 connect issue_slots[7].in_uop.bits.fp_ctrl.swap12, issue_slots[9].out_uop.fp_ctrl.swap12 connect issue_slots[7].in_uop.bits.fp_ctrl.ren3, issue_slots[9].out_uop.fp_ctrl.ren3 connect issue_slots[7].in_uop.bits.fp_ctrl.ren2, issue_slots[9].out_uop.fp_ctrl.ren2 connect issue_slots[7].in_uop.bits.fp_ctrl.ren1, issue_slots[9].out_uop.fp_ctrl.ren1 connect issue_slots[7].in_uop.bits.fp_ctrl.wen, issue_slots[9].out_uop.fp_ctrl.wen connect issue_slots[7].in_uop.bits.fp_ctrl.ldst, issue_slots[9].out_uop.fp_ctrl.ldst connect issue_slots[7].in_uop.bits.op2_sel, issue_slots[9].out_uop.op2_sel connect issue_slots[7].in_uop.bits.op1_sel, issue_slots[9].out_uop.op1_sel connect issue_slots[7].in_uop.bits.imm_packed, issue_slots[9].out_uop.imm_packed connect issue_slots[7].in_uop.bits.pimm, issue_slots[9].out_uop.pimm connect issue_slots[7].in_uop.bits.imm_sel, issue_slots[9].out_uop.imm_sel connect issue_slots[7].in_uop.bits.imm_rename, issue_slots[9].out_uop.imm_rename connect issue_slots[7].in_uop.bits.taken, issue_slots[9].out_uop.taken connect issue_slots[7].in_uop.bits.pc_lob, issue_slots[9].out_uop.pc_lob connect issue_slots[7].in_uop.bits.edge_inst, issue_slots[9].out_uop.edge_inst connect issue_slots[7].in_uop.bits.ftq_idx, issue_slots[9].out_uop.ftq_idx connect issue_slots[7].in_uop.bits.is_mov, issue_slots[9].out_uop.is_mov connect issue_slots[7].in_uop.bits.is_rocc, issue_slots[9].out_uop.is_rocc connect issue_slots[7].in_uop.bits.is_sys_pc2epc, issue_slots[9].out_uop.is_sys_pc2epc connect issue_slots[7].in_uop.bits.is_eret, issue_slots[9].out_uop.is_eret connect issue_slots[7].in_uop.bits.is_amo, issue_slots[9].out_uop.is_amo connect issue_slots[7].in_uop.bits.is_sfence, issue_slots[9].out_uop.is_sfence connect issue_slots[7].in_uop.bits.is_fencei, issue_slots[9].out_uop.is_fencei connect issue_slots[7].in_uop.bits.is_fence, issue_slots[9].out_uop.is_fence connect issue_slots[7].in_uop.bits.is_sfb, issue_slots[9].out_uop.is_sfb connect issue_slots[7].in_uop.bits.br_type, issue_slots[9].out_uop.br_type connect issue_slots[7].in_uop.bits.br_tag, issue_slots[9].out_uop.br_tag connect issue_slots[7].in_uop.bits.br_mask, issue_slots[9].out_uop.br_mask connect issue_slots[7].in_uop.bits.dis_col_sel, issue_slots[9].out_uop.dis_col_sel connect issue_slots[7].in_uop.bits.iw_p3_bypass_hint, issue_slots[9].out_uop.iw_p3_bypass_hint connect issue_slots[7].in_uop.bits.iw_p2_bypass_hint, issue_slots[9].out_uop.iw_p2_bypass_hint connect issue_slots[7].in_uop.bits.iw_p1_bypass_hint, issue_slots[9].out_uop.iw_p1_bypass_hint connect issue_slots[7].in_uop.bits.iw_p2_speculative_child, issue_slots[9].out_uop.iw_p2_speculative_child connect issue_slots[7].in_uop.bits.iw_p1_speculative_child, issue_slots[9].out_uop.iw_p1_speculative_child connect issue_slots[7].in_uop.bits.iw_issued_partial_dgen, issue_slots[9].out_uop.iw_issued_partial_dgen connect issue_slots[7].in_uop.bits.iw_issued_partial_agen, issue_slots[9].out_uop.iw_issued_partial_agen connect issue_slots[7].in_uop.bits.iw_issued, issue_slots[9].out_uop.iw_issued connect issue_slots[7].in_uop.bits.fu_code[0], issue_slots[9].out_uop.fu_code[0] connect issue_slots[7].in_uop.bits.fu_code[1], issue_slots[9].out_uop.fu_code[1] connect issue_slots[7].in_uop.bits.fu_code[2], issue_slots[9].out_uop.fu_code[2] connect issue_slots[7].in_uop.bits.fu_code[3], issue_slots[9].out_uop.fu_code[3] connect issue_slots[7].in_uop.bits.fu_code[4], issue_slots[9].out_uop.fu_code[4] connect issue_slots[7].in_uop.bits.fu_code[5], issue_slots[9].out_uop.fu_code[5] connect issue_slots[7].in_uop.bits.fu_code[6], issue_slots[9].out_uop.fu_code[6] connect issue_slots[7].in_uop.bits.fu_code[7], issue_slots[9].out_uop.fu_code[7] connect issue_slots[7].in_uop.bits.fu_code[8], issue_slots[9].out_uop.fu_code[8] connect issue_slots[7].in_uop.bits.fu_code[9], issue_slots[9].out_uop.fu_code[9] connect issue_slots[7].in_uop.bits.iq_type[0], issue_slots[9].out_uop.iq_type[0] connect issue_slots[7].in_uop.bits.iq_type[1], issue_slots[9].out_uop.iq_type[1] connect issue_slots[7].in_uop.bits.iq_type[2], issue_slots[9].out_uop.iq_type[2] connect issue_slots[7].in_uop.bits.iq_type[3], issue_slots[9].out_uop.iq_type[3] connect issue_slots[7].in_uop.bits.debug_pc, issue_slots[9].out_uop.debug_pc connect issue_slots[7].in_uop.bits.is_rvc, issue_slots[9].out_uop.is_rvc connect issue_slots[7].in_uop.bits.debug_inst, issue_slots[9].out_uop.debug_inst connect issue_slots[7].in_uop.bits.inst, issue_slots[9].out_uop.inst node _T_300 = eq(shamts_oh[10], UInt<3>(0h4)) when _T_300 : connect issue_slots[7].in_uop.valid, issue_slots[10].will_be_valid connect issue_slots[7].in_uop.bits.debug_tsrc, issue_slots[10].out_uop.debug_tsrc connect issue_slots[7].in_uop.bits.debug_fsrc, issue_slots[10].out_uop.debug_fsrc connect issue_slots[7].in_uop.bits.bp_xcpt_if, issue_slots[10].out_uop.bp_xcpt_if connect issue_slots[7].in_uop.bits.bp_debug_if, issue_slots[10].out_uop.bp_debug_if connect issue_slots[7].in_uop.bits.xcpt_ma_if, issue_slots[10].out_uop.xcpt_ma_if connect issue_slots[7].in_uop.bits.xcpt_ae_if, issue_slots[10].out_uop.xcpt_ae_if connect issue_slots[7].in_uop.bits.xcpt_pf_if, issue_slots[10].out_uop.xcpt_pf_if connect issue_slots[7].in_uop.bits.fp_typ, issue_slots[10].out_uop.fp_typ connect issue_slots[7].in_uop.bits.fp_rm, issue_slots[10].out_uop.fp_rm connect issue_slots[7].in_uop.bits.fp_val, issue_slots[10].out_uop.fp_val connect issue_slots[7].in_uop.bits.fcn_op, issue_slots[10].out_uop.fcn_op connect issue_slots[7].in_uop.bits.fcn_dw, issue_slots[10].out_uop.fcn_dw connect issue_slots[7].in_uop.bits.frs3_en, issue_slots[10].out_uop.frs3_en connect issue_slots[7].in_uop.bits.lrs2_rtype, issue_slots[10].out_uop.lrs2_rtype connect issue_slots[7].in_uop.bits.lrs1_rtype, issue_slots[10].out_uop.lrs1_rtype connect issue_slots[7].in_uop.bits.dst_rtype, issue_slots[10].out_uop.dst_rtype connect issue_slots[7].in_uop.bits.lrs3, issue_slots[10].out_uop.lrs3 connect issue_slots[7].in_uop.bits.lrs2, issue_slots[10].out_uop.lrs2 connect issue_slots[7].in_uop.bits.lrs1, issue_slots[10].out_uop.lrs1 connect issue_slots[7].in_uop.bits.ldst, issue_slots[10].out_uop.ldst connect issue_slots[7].in_uop.bits.ldst_is_rs1, issue_slots[10].out_uop.ldst_is_rs1 connect issue_slots[7].in_uop.bits.csr_cmd, issue_slots[10].out_uop.csr_cmd connect issue_slots[7].in_uop.bits.flush_on_commit, issue_slots[10].out_uop.flush_on_commit connect issue_slots[7].in_uop.bits.is_unique, issue_slots[10].out_uop.is_unique connect issue_slots[7].in_uop.bits.uses_stq, issue_slots[10].out_uop.uses_stq connect issue_slots[7].in_uop.bits.uses_ldq, issue_slots[10].out_uop.uses_ldq connect issue_slots[7].in_uop.bits.mem_signed, issue_slots[10].out_uop.mem_signed connect issue_slots[7].in_uop.bits.mem_size, issue_slots[10].out_uop.mem_size connect issue_slots[7].in_uop.bits.mem_cmd, issue_slots[10].out_uop.mem_cmd connect issue_slots[7].in_uop.bits.exc_cause, issue_slots[10].out_uop.exc_cause connect issue_slots[7].in_uop.bits.exception, issue_slots[10].out_uop.exception connect issue_slots[7].in_uop.bits.stale_pdst, issue_slots[10].out_uop.stale_pdst connect issue_slots[7].in_uop.bits.ppred_busy, issue_slots[10].out_uop.ppred_busy connect issue_slots[7].in_uop.bits.prs3_busy, issue_slots[10].out_uop.prs3_busy connect issue_slots[7].in_uop.bits.prs2_busy, issue_slots[10].out_uop.prs2_busy connect issue_slots[7].in_uop.bits.prs1_busy, issue_slots[10].out_uop.prs1_busy connect issue_slots[7].in_uop.bits.ppred, issue_slots[10].out_uop.ppred connect issue_slots[7].in_uop.bits.prs3, issue_slots[10].out_uop.prs3 connect issue_slots[7].in_uop.bits.prs2, issue_slots[10].out_uop.prs2 connect issue_slots[7].in_uop.bits.prs1, issue_slots[10].out_uop.prs1 connect issue_slots[7].in_uop.bits.pdst, issue_slots[10].out_uop.pdst connect issue_slots[7].in_uop.bits.rxq_idx, issue_slots[10].out_uop.rxq_idx connect issue_slots[7].in_uop.bits.stq_idx, issue_slots[10].out_uop.stq_idx connect issue_slots[7].in_uop.bits.ldq_idx, issue_slots[10].out_uop.ldq_idx connect issue_slots[7].in_uop.bits.rob_idx, issue_slots[10].out_uop.rob_idx connect issue_slots[7].in_uop.bits.fp_ctrl.vec, issue_slots[10].out_uop.fp_ctrl.vec connect issue_slots[7].in_uop.bits.fp_ctrl.wflags, issue_slots[10].out_uop.fp_ctrl.wflags connect issue_slots[7].in_uop.bits.fp_ctrl.sqrt, issue_slots[10].out_uop.fp_ctrl.sqrt connect issue_slots[7].in_uop.bits.fp_ctrl.div, issue_slots[10].out_uop.fp_ctrl.div connect issue_slots[7].in_uop.bits.fp_ctrl.fma, issue_slots[10].out_uop.fp_ctrl.fma connect issue_slots[7].in_uop.bits.fp_ctrl.fastpipe, issue_slots[10].out_uop.fp_ctrl.fastpipe connect issue_slots[7].in_uop.bits.fp_ctrl.toint, issue_slots[10].out_uop.fp_ctrl.toint connect issue_slots[7].in_uop.bits.fp_ctrl.fromint, issue_slots[10].out_uop.fp_ctrl.fromint connect issue_slots[7].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[10].out_uop.fp_ctrl.typeTagOut connect issue_slots[7].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[10].out_uop.fp_ctrl.typeTagIn connect issue_slots[7].in_uop.bits.fp_ctrl.swap23, issue_slots[10].out_uop.fp_ctrl.swap23 connect issue_slots[7].in_uop.bits.fp_ctrl.swap12, issue_slots[10].out_uop.fp_ctrl.swap12 connect issue_slots[7].in_uop.bits.fp_ctrl.ren3, issue_slots[10].out_uop.fp_ctrl.ren3 connect issue_slots[7].in_uop.bits.fp_ctrl.ren2, issue_slots[10].out_uop.fp_ctrl.ren2 connect issue_slots[7].in_uop.bits.fp_ctrl.ren1, issue_slots[10].out_uop.fp_ctrl.ren1 connect issue_slots[7].in_uop.bits.fp_ctrl.wen, issue_slots[10].out_uop.fp_ctrl.wen connect issue_slots[7].in_uop.bits.fp_ctrl.ldst, issue_slots[10].out_uop.fp_ctrl.ldst connect issue_slots[7].in_uop.bits.op2_sel, issue_slots[10].out_uop.op2_sel connect issue_slots[7].in_uop.bits.op1_sel, issue_slots[10].out_uop.op1_sel connect issue_slots[7].in_uop.bits.imm_packed, issue_slots[10].out_uop.imm_packed connect issue_slots[7].in_uop.bits.pimm, issue_slots[10].out_uop.pimm connect issue_slots[7].in_uop.bits.imm_sel, issue_slots[10].out_uop.imm_sel connect issue_slots[7].in_uop.bits.imm_rename, issue_slots[10].out_uop.imm_rename connect issue_slots[7].in_uop.bits.taken, issue_slots[10].out_uop.taken connect issue_slots[7].in_uop.bits.pc_lob, issue_slots[10].out_uop.pc_lob connect issue_slots[7].in_uop.bits.edge_inst, issue_slots[10].out_uop.edge_inst connect issue_slots[7].in_uop.bits.ftq_idx, issue_slots[10].out_uop.ftq_idx connect issue_slots[7].in_uop.bits.is_mov, issue_slots[10].out_uop.is_mov connect issue_slots[7].in_uop.bits.is_rocc, issue_slots[10].out_uop.is_rocc connect issue_slots[7].in_uop.bits.is_sys_pc2epc, issue_slots[10].out_uop.is_sys_pc2epc connect issue_slots[7].in_uop.bits.is_eret, issue_slots[10].out_uop.is_eret connect issue_slots[7].in_uop.bits.is_amo, issue_slots[10].out_uop.is_amo connect issue_slots[7].in_uop.bits.is_sfence, issue_slots[10].out_uop.is_sfence connect issue_slots[7].in_uop.bits.is_fencei, issue_slots[10].out_uop.is_fencei connect issue_slots[7].in_uop.bits.is_fence, issue_slots[10].out_uop.is_fence connect issue_slots[7].in_uop.bits.is_sfb, issue_slots[10].out_uop.is_sfb connect issue_slots[7].in_uop.bits.br_type, issue_slots[10].out_uop.br_type connect issue_slots[7].in_uop.bits.br_tag, issue_slots[10].out_uop.br_tag connect issue_slots[7].in_uop.bits.br_mask, issue_slots[10].out_uop.br_mask connect issue_slots[7].in_uop.bits.dis_col_sel, issue_slots[10].out_uop.dis_col_sel connect issue_slots[7].in_uop.bits.iw_p3_bypass_hint, issue_slots[10].out_uop.iw_p3_bypass_hint connect issue_slots[7].in_uop.bits.iw_p2_bypass_hint, issue_slots[10].out_uop.iw_p2_bypass_hint connect issue_slots[7].in_uop.bits.iw_p1_bypass_hint, issue_slots[10].out_uop.iw_p1_bypass_hint connect issue_slots[7].in_uop.bits.iw_p2_speculative_child, issue_slots[10].out_uop.iw_p2_speculative_child connect issue_slots[7].in_uop.bits.iw_p1_speculative_child, issue_slots[10].out_uop.iw_p1_speculative_child connect issue_slots[7].in_uop.bits.iw_issued_partial_dgen, issue_slots[10].out_uop.iw_issued_partial_dgen connect issue_slots[7].in_uop.bits.iw_issued_partial_agen, issue_slots[10].out_uop.iw_issued_partial_agen connect issue_slots[7].in_uop.bits.iw_issued, issue_slots[10].out_uop.iw_issued connect issue_slots[7].in_uop.bits.fu_code[0], issue_slots[10].out_uop.fu_code[0] connect issue_slots[7].in_uop.bits.fu_code[1], issue_slots[10].out_uop.fu_code[1] connect issue_slots[7].in_uop.bits.fu_code[2], issue_slots[10].out_uop.fu_code[2] connect issue_slots[7].in_uop.bits.fu_code[3], issue_slots[10].out_uop.fu_code[3] connect issue_slots[7].in_uop.bits.fu_code[4], issue_slots[10].out_uop.fu_code[4] connect issue_slots[7].in_uop.bits.fu_code[5], issue_slots[10].out_uop.fu_code[5] connect issue_slots[7].in_uop.bits.fu_code[6], issue_slots[10].out_uop.fu_code[6] connect issue_slots[7].in_uop.bits.fu_code[7], issue_slots[10].out_uop.fu_code[7] connect issue_slots[7].in_uop.bits.fu_code[8], issue_slots[10].out_uop.fu_code[8] connect issue_slots[7].in_uop.bits.fu_code[9], issue_slots[10].out_uop.fu_code[9] connect issue_slots[7].in_uop.bits.iq_type[0], issue_slots[10].out_uop.iq_type[0] connect issue_slots[7].in_uop.bits.iq_type[1], issue_slots[10].out_uop.iq_type[1] connect issue_slots[7].in_uop.bits.iq_type[2], issue_slots[10].out_uop.iq_type[2] connect issue_slots[7].in_uop.bits.iq_type[3], issue_slots[10].out_uop.iq_type[3] connect issue_slots[7].in_uop.bits.debug_pc, issue_slots[10].out_uop.debug_pc connect issue_slots[7].in_uop.bits.is_rvc, issue_slots[10].out_uop.is_rvc connect issue_slots[7].in_uop.bits.debug_inst, issue_slots[10].out_uop.debug_inst connect issue_slots[7].in_uop.bits.inst, issue_slots[10].out_uop.inst node _issue_slots_7_clear_T = neq(shamts_oh[7], UInt<1>(0h0)) connect issue_slots[7].clear, _issue_slots_7_clear_T connect issue_slots[8].in_uop.valid, UInt<1>(0h0) connect issue_slots[8].in_uop.bits.debug_tsrc, issue_slots[9].out_uop.debug_tsrc connect issue_slots[8].in_uop.bits.debug_fsrc, issue_slots[9].out_uop.debug_fsrc connect issue_slots[8].in_uop.bits.bp_xcpt_if, issue_slots[9].out_uop.bp_xcpt_if connect issue_slots[8].in_uop.bits.bp_debug_if, issue_slots[9].out_uop.bp_debug_if connect issue_slots[8].in_uop.bits.xcpt_ma_if, issue_slots[9].out_uop.xcpt_ma_if connect issue_slots[8].in_uop.bits.xcpt_ae_if, issue_slots[9].out_uop.xcpt_ae_if connect issue_slots[8].in_uop.bits.xcpt_pf_if, issue_slots[9].out_uop.xcpt_pf_if connect issue_slots[8].in_uop.bits.fp_typ, issue_slots[9].out_uop.fp_typ connect issue_slots[8].in_uop.bits.fp_rm, issue_slots[9].out_uop.fp_rm connect issue_slots[8].in_uop.bits.fp_val, issue_slots[9].out_uop.fp_val connect issue_slots[8].in_uop.bits.fcn_op, issue_slots[9].out_uop.fcn_op connect issue_slots[8].in_uop.bits.fcn_dw, issue_slots[9].out_uop.fcn_dw connect issue_slots[8].in_uop.bits.frs3_en, issue_slots[9].out_uop.frs3_en connect issue_slots[8].in_uop.bits.lrs2_rtype, issue_slots[9].out_uop.lrs2_rtype connect issue_slots[8].in_uop.bits.lrs1_rtype, issue_slots[9].out_uop.lrs1_rtype connect issue_slots[8].in_uop.bits.dst_rtype, issue_slots[9].out_uop.dst_rtype connect issue_slots[8].in_uop.bits.lrs3, issue_slots[9].out_uop.lrs3 connect issue_slots[8].in_uop.bits.lrs2, issue_slots[9].out_uop.lrs2 connect issue_slots[8].in_uop.bits.lrs1, issue_slots[9].out_uop.lrs1 connect issue_slots[8].in_uop.bits.ldst, issue_slots[9].out_uop.ldst connect issue_slots[8].in_uop.bits.ldst_is_rs1, issue_slots[9].out_uop.ldst_is_rs1 connect issue_slots[8].in_uop.bits.csr_cmd, issue_slots[9].out_uop.csr_cmd connect issue_slots[8].in_uop.bits.flush_on_commit, issue_slots[9].out_uop.flush_on_commit connect issue_slots[8].in_uop.bits.is_unique, issue_slots[9].out_uop.is_unique connect issue_slots[8].in_uop.bits.uses_stq, issue_slots[9].out_uop.uses_stq connect issue_slots[8].in_uop.bits.uses_ldq, issue_slots[9].out_uop.uses_ldq connect issue_slots[8].in_uop.bits.mem_signed, issue_slots[9].out_uop.mem_signed connect issue_slots[8].in_uop.bits.mem_size, issue_slots[9].out_uop.mem_size connect issue_slots[8].in_uop.bits.mem_cmd, issue_slots[9].out_uop.mem_cmd connect issue_slots[8].in_uop.bits.exc_cause, issue_slots[9].out_uop.exc_cause connect issue_slots[8].in_uop.bits.exception, issue_slots[9].out_uop.exception connect issue_slots[8].in_uop.bits.stale_pdst, issue_slots[9].out_uop.stale_pdst connect issue_slots[8].in_uop.bits.ppred_busy, issue_slots[9].out_uop.ppred_busy connect issue_slots[8].in_uop.bits.prs3_busy, issue_slots[9].out_uop.prs3_busy connect issue_slots[8].in_uop.bits.prs2_busy, issue_slots[9].out_uop.prs2_busy connect issue_slots[8].in_uop.bits.prs1_busy, issue_slots[9].out_uop.prs1_busy connect issue_slots[8].in_uop.bits.ppred, issue_slots[9].out_uop.ppred connect issue_slots[8].in_uop.bits.prs3, issue_slots[9].out_uop.prs3 connect issue_slots[8].in_uop.bits.prs2, issue_slots[9].out_uop.prs2 connect issue_slots[8].in_uop.bits.prs1, issue_slots[9].out_uop.prs1 connect issue_slots[8].in_uop.bits.pdst, issue_slots[9].out_uop.pdst connect issue_slots[8].in_uop.bits.rxq_idx, issue_slots[9].out_uop.rxq_idx connect issue_slots[8].in_uop.bits.stq_idx, issue_slots[9].out_uop.stq_idx connect issue_slots[8].in_uop.bits.ldq_idx, issue_slots[9].out_uop.ldq_idx connect issue_slots[8].in_uop.bits.rob_idx, issue_slots[9].out_uop.rob_idx connect issue_slots[8].in_uop.bits.fp_ctrl.vec, issue_slots[9].out_uop.fp_ctrl.vec connect issue_slots[8].in_uop.bits.fp_ctrl.wflags, issue_slots[9].out_uop.fp_ctrl.wflags connect issue_slots[8].in_uop.bits.fp_ctrl.sqrt, issue_slots[9].out_uop.fp_ctrl.sqrt connect issue_slots[8].in_uop.bits.fp_ctrl.div, issue_slots[9].out_uop.fp_ctrl.div connect issue_slots[8].in_uop.bits.fp_ctrl.fma, issue_slots[9].out_uop.fp_ctrl.fma connect issue_slots[8].in_uop.bits.fp_ctrl.fastpipe, issue_slots[9].out_uop.fp_ctrl.fastpipe connect issue_slots[8].in_uop.bits.fp_ctrl.toint, issue_slots[9].out_uop.fp_ctrl.toint connect issue_slots[8].in_uop.bits.fp_ctrl.fromint, issue_slots[9].out_uop.fp_ctrl.fromint connect issue_slots[8].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[9].out_uop.fp_ctrl.typeTagOut connect issue_slots[8].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[9].out_uop.fp_ctrl.typeTagIn connect issue_slots[8].in_uop.bits.fp_ctrl.swap23, issue_slots[9].out_uop.fp_ctrl.swap23 connect issue_slots[8].in_uop.bits.fp_ctrl.swap12, issue_slots[9].out_uop.fp_ctrl.swap12 connect issue_slots[8].in_uop.bits.fp_ctrl.ren3, issue_slots[9].out_uop.fp_ctrl.ren3 connect issue_slots[8].in_uop.bits.fp_ctrl.ren2, issue_slots[9].out_uop.fp_ctrl.ren2 connect issue_slots[8].in_uop.bits.fp_ctrl.ren1, issue_slots[9].out_uop.fp_ctrl.ren1 connect issue_slots[8].in_uop.bits.fp_ctrl.wen, issue_slots[9].out_uop.fp_ctrl.wen connect issue_slots[8].in_uop.bits.fp_ctrl.ldst, issue_slots[9].out_uop.fp_ctrl.ldst connect issue_slots[8].in_uop.bits.op2_sel, issue_slots[9].out_uop.op2_sel connect issue_slots[8].in_uop.bits.op1_sel, issue_slots[9].out_uop.op1_sel connect issue_slots[8].in_uop.bits.imm_packed, issue_slots[9].out_uop.imm_packed connect issue_slots[8].in_uop.bits.pimm, issue_slots[9].out_uop.pimm connect issue_slots[8].in_uop.bits.imm_sel, issue_slots[9].out_uop.imm_sel connect issue_slots[8].in_uop.bits.imm_rename, issue_slots[9].out_uop.imm_rename connect issue_slots[8].in_uop.bits.taken, issue_slots[9].out_uop.taken connect issue_slots[8].in_uop.bits.pc_lob, issue_slots[9].out_uop.pc_lob connect issue_slots[8].in_uop.bits.edge_inst, issue_slots[9].out_uop.edge_inst connect issue_slots[8].in_uop.bits.ftq_idx, issue_slots[9].out_uop.ftq_idx connect issue_slots[8].in_uop.bits.is_mov, issue_slots[9].out_uop.is_mov connect issue_slots[8].in_uop.bits.is_rocc, issue_slots[9].out_uop.is_rocc connect issue_slots[8].in_uop.bits.is_sys_pc2epc, issue_slots[9].out_uop.is_sys_pc2epc connect issue_slots[8].in_uop.bits.is_eret, issue_slots[9].out_uop.is_eret connect issue_slots[8].in_uop.bits.is_amo, issue_slots[9].out_uop.is_amo connect issue_slots[8].in_uop.bits.is_sfence, issue_slots[9].out_uop.is_sfence connect issue_slots[8].in_uop.bits.is_fencei, issue_slots[9].out_uop.is_fencei connect issue_slots[8].in_uop.bits.is_fence, issue_slots[9].out_uop.is_fence connect issue_slots[8].in_uop.bits.is_sfb, issue_slots[9].out_uop.is_sfb connect issue_slots[8].in_uop.bits.br_type, issue_slots[9].out_uop.br_type connect issue_slots[8].in_uop.bits.br_tag, issue_slots[9].out_uop.br_tag connect issue_slots[8].in_uop.bits.br_mask, issue_slots[9].out_uop.br_mask connect issue_slots[8].in_uop.bits.dis_col_sel, issue_slots[9].out_uop.dis_col_sel connect issue_slots[8].in_uop.bits.iw_p3_bypass_hint, issue_slots[9].out_uop.iw_p3_bypass_hint connect issue_slots[8].in_uop.bits.iw_p2_bypass_hint, issue_slots[9].out_uop.iw_p2_bypass_hint connect issue_slots[8].in_uop.bits.iw_p1_bypass_hint, issue_slots[9].out_uop.iw_p1_bypass_hint connect issue_slots[8].in_uop.bits.iw_p2_speculative_child, issue_slots[9].out_uop.iw_p2_speculative_child connect issue_slots[8].in_uop.bits.iw_p1_speculative_child, issue_slots[9].out_uop.iw_p1_speculative_child connect issue_slots[8].in_uop.bits.iw_issued_partial_dgen, issue_slots[9].out_uop.iw_issued_partial_dgen connect issue_slots[8].in_uop.bits.iw_issued_partial_agen, issue_slots[9].out_uop.iw_issued_partial_agen connect issue_slots[8].in_uop.bits.iw_issued, issue_slots[9].out_uop.iw_issued connect issue_slots[8].in_uop.bits.fu_code[0], issue_slots[9].out_uop.fu_code[0] connect issue_slots[8].in_uop.bits.fu_code[1], issue_slots[9].out_uop.fu_code[1] connect issue_slots[8].in_uop.bits.fu_code[2], issue_slots[9].out_uop.fu_code[2] connect issue_slots[8].in_uop.bits.fu_code[3], issue_slots[9].out_uop.fu_code[3] connect issue_slots[8].in_uop.bits.fu_code[4], issue_slots[9].out_uop.fu_code[4] connect issue_slots[8].in_uop.bits.fu_code[5], issue_slots[9].out_uop.fu_code[5] connect issue_slots[8].in_uop.bits.fu_code[6], issue_slots[9].out_uop.fu_code[6] connect issue_slots[8].in_uop.bits.fu_code[7], issue_slots[9].out_uop.fu_code[7] connect issue_slots[8].in_uop.bits.fu_code[8], issue_slots[9].out_uop.fu_code[8] connect issue_slots[8].in_uop.bits.fu_code[9], issue_slots[9].out_uop.fu_code[9] connect issue_slots[8].in_uop.bits.iq_type[0], issue_slots[9].out_uop.iq_type[0] connect issue_slots[8].in_uop.bits.iq_type[1], issue_slots[9].out_uop.iq_type[1] connect issue_slots[8].in_uop.bits.iq_type[2], issue_slots[9].out_uop.iq_type[2] connect issue_slots[8].in_uop.bits.iq_type[3], issue_slots[9].out_uop.iq_type[3] connect issue_slots[8].in_uop.bits.debug_pc, issue_slots[9].out_uop.debug_pc connect issue_slots[8].in_uop.bits.is_rvc, issue_slots[9].out_uop.is_rvc connect issue_slots[8].in_uop.bits.debug_inst, issue_slots[9].out_uop.debug_inst connect issue_slots[8].in_uop.bits.inst, issue_slots[9].out_uop.inst node _T_301 = eq(shamts_oh[9], UInt<1>(0h1)) when _T_301 : connect issue_slots[8].in_uop.valid, issue_slots[9].will_be_valid connect issue_slots[8].in_uop.bits.debug_tsrc, issue_slots[9].out_uop.debug_tsrc connect issue_slots[8].in_uop.bits.debug_fsrc, issue_slots[9].out_uop.debug_fsrc connect issue_slots[8].in_uop.bits.bp_xcpt_if, issue_slots[9].out_uop.bp_xcpt_if connect issue_slots[8].in_uop.bits.bp_debug_if, issue_slots[9].out_uop.bp_debug_if connect issue_slots[8].in_uop.bits.xcpt_ma_if, issue_slots[9].out_uop.xcpt_ma_if connect issue_slots[8].in_uop.bits.xcpt_ae_if, issue_slots[9].out_uop.xcpt_ae_if connect issue_slots[8].in_uop.bits.xcpt_pf_if, issue_slots[9].out_uop.xcpt_pf_if connect issue_slots[8].in_uop.bits.fp_typ, issue_slots[9].out_uop.fp_typ connect issue_slots[8].in_uop.bits.fp_rm, issue_slots[9].out_uop.fp_rm connect issue_slots[8].in_uop.bits.fp_val, issue_slots[9].out_uop.fp_val connect issue_slots[8].in_uop.bits.fcn_op, issue_slots[9].out_uop.fcn_op connect issue_slots[8].in_uop.bits.fcn_dw, issue_slots[9].out_uop.fcn_dw connect issue_slots[8].in_uop.bits.frs3_en, issue_slots[9].out_uop.frs3_en connect issue_slots[8].in_uop.bits.lrs2_rtype, issue_slots[9].out_uop.lrs2_rtype connect issue_slots[8].in_uop.bits.lrs1_rtype, issue_slots[9].out_uop.lrs1_rtype connect issue_slots[8].in_uop.bits.dst_rtype, issue_slots[9].out_uop.dst_rtype connect issue_slots[8].in_uop.bits.lrs3, issue_slots[9].out_uop.lrs3 connect issue_slots[8].in_uop.bits.lrs2, issue_slots[9].out_uop.lrs2 connect issue_slots[8].in_uop.bits.lrs1, issue_slots[9].out_uop.lrs1 connect issue_slots[8].in_uop.bits.ldst, issue_slots[9].out_uop.ldst connect issue_slots[8].in_uop.bits.ldst_is_rs1, issue_slots[9].out_uop.ldst_is_rs1 connect issue_slots[8].in_uop.bits.csr_cmd, issue_slots[9].out_uop.csr_cmd connect issue_slots[8].in_uop.bits.flush_on_commit, issue_slots[9].out_uop.flush_on_commit connect issue_slots[8].in_uop.bits.is_unique, issue_slots[9].out_uop.is_unique connect issue_slots[8].in_uop.bits.uses_stq, issue_slots[9].out_uop.uses_stq connect issue_slots[8].in_uop.bits.uses_ldq, issue_slots[9].out_uop.uses_ldq connect issue_slots[8].in_uop.bits.mem_signed, issue_slots[9].out_uop.mem_signed connect issue_slots[8].in_uop.bits.mem_size, issue_slots[9].out_uop.mem_size connect issue_slots[8].in_uop.bits.mem_cmd, issue_slots[9].out_uop.mem_cmd connect issue_slots[8].in_uop.bits.exc_cause, issue_slots[9].out_uop.exc_cause connect issue_slots[8].in_uop.bits.exception, issue_slots[9].out_uop.exception connect issue_slots[8].in_uop.bits.stale_pdst, issue_slots[9].out_uop.stale_pdst connect issue_slots[8].in_uop.bits.ppred_busy, issue_slots[9].out_uop.ppred_busy connect issue_slots[8].in_uop.bits.prs3_busy, issue_slots[9].out_uop.prs3_busy connect issue_slots[8].in_uop.bits.prs2_busy, issue_slots[9].out_uop.prs2_busy connect issue_slots[8].in_uop.bits.prs1_busy, issue_slots[9].out_uop.prs1_busy connect issue_slots[8].in_uop.bits.ppred, issue_slots[9].out_uop.ppred connect issue_slots[8].in_uop.bits.prs3, issue_slots[9].out_uop.prs3 connect issue_slots[8].in_uop.bits.prs2, issue_slots[9].out_uop.prs2 connect issue_slots[8].in_uop.bits.prs1, issue_slots[9].out_uop.prs1 connect issue_slots[8].in_uop.bits.pdst, issue_slots[9].out_uop.pdst connect issue_slots[8].in_uop.bits.rxq_idx, issue_slots[9].out_uop.rxq_idx connect issue_slots[8].in_uop.bits.stq_idx, issue_slots[9].out_uop.stq_idx connect issue_slots[8].in_uop.bits.ldq_idx, issue_slots[9].out_uop.ldq_idx connect issue_slots[8].in_uop.bits.rob_idx, issue_slots[9].out_uop.rob_idx connect issue_slots[8].in_uop.bits.fp_ctrl.vec, issue_slots[9].out_uop.fp_ctrl.vec connect issue_slots[8].in_uop.bits.fp_ctrl.wflags, issue_slots[9].out_uop.fp_ctrl.wflags connect issue_slots[8].in_uop.bits.fp_ctrl.sqrt, issue_slots[9].out_uop.fp_ctrl.sqrt connect issue_slots[8].in_uop.bits.fp_ctrl.div, issue_slots[9].out_uop.fp_ctrl.div connect issue_slots[8].in_uop.bits.fp_ctrl.fma, issue_slots[9].out_uop.fp_ctrl.fma connect issue_slots[8].in_uop.bits.fp_ctrl.fastpipe, issue_slots[9].out_uop.fp_ctrl.fastpipe connect issue_slots[8].in_uop.bits.fp_ctrl.toint, issue_slots[9].out_uop.fp_ctrl.toint connect issue_slots[8].in_uop.bits.fp_ctrl.fromint, issue_slots[9].out_uop.fp_ctrl.fromint connect issue_slots[8].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[9].out_uop.fp_ctrl.typeTagOut connect issue_slots[8].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[9].out_uop.fp_ctrl.typeTagIn connect issue_slots[8].in_uop.bits.fp_ctrl.swap23, issue_slots[9].out_uop.fp_ctrl.swap23 connect issue_slots[8].in_uop.bits.fp_ctrl.swap12, issue_slots[9].out_uop.fp_ctrl.swap12 connect issue_slots[8].in_uop.bits.fp_ctrl.ren3, issue_slots[9].out_uop.fp_ctrl.ren3 connect issue_slots[8].in_uop.bits.fp_ctrl.ren2, issue_slots[9].out_uop.fp_ctrl.ren2 connect issue_slots[8].in_uop.bits.fp_ctrl.ren1, issue_slots[9].out_uop.fp_ctrl.ren1 connect issue_slots[8].in_uop.bits.fp_ctrl.wen, issue_slots[9].out_uop.fp_ctrl.wen connect issue_slots[8].in_uop.bits.fp_ctrl.ldst, issue_slots[9].out_uop.fp_ctrl.ldst connect issue_slots[8].in_uop.bits.op2_sel, issue_slots[9].out_uop.op2_sel connect issue_slots[8].in_uop.bits.op1_sel, issue_slots[9].out_uop.op1_sel connect issue_slots[8].in_uop.bits.imm_packed, issue_slots[9].out_uop.imm_packed connect issue_slots[8].in_uop.bits.pimm, issue_slots[9].out_uop.pimm connect issue_slots[8].in_uop.bits.imm_sel, issue_slots[9].out_uop.imm_sel connect issue_slots[8].in_uop.bits.imm_rename, issue_slots[9].out_uop.imm_rename connect issue_slots[8].in_uop.bits.taken, issue_slots[9].out_uop.taken connect issue_slots[8].in_uop.bits.pc_lob, issue_slots[9].out_uop.pc_lob connect issue_slots[8].in_uop.bits.edge_inst, issue_slots[9].out_uop.edge_inst connect issue_slots[8].in_uop.bits.ftq_idx, issue_slots[9].out_uop.ftq_idx connect issue_slots[8].in_uop.bits.is_mov, issue_slots[9].out_uop.is_mov connect issue_slots[8].in_uop.bits.is_rocc, issue_slots[9].out_uop.is_rocc connect issue_slots[8].in_uop.bits.is_sys_pc2epc, issue_slots[9].out_uop.is_sys_pc2epc connect issue_slots[8].in_uop.bits.is_eret, issue_slots[9].out_uop.is_eret connect issue_slots[8].in_uop.bits.is_amo, issue_slots[9].out_uop.is_amo connect issue_slots[8].in_uop.bits.is_sfence, issue_slots[9].out_uop.is_sfence connect issue_slots[8].in_uop.bits.is_fencei, issue_slots[9].out_uop.is_fencei connect issue_slots[8].in_uop.bits.is_fence, issue_slots[9].out_uop.is_fence connect issue_slots[8].in_uop.bits.is_sfb, issue_slots[9].out_uop.is_sfb connect issue_slots[8].in_uop.bits.br_type, issue_slots[9].out_uop.br_type connect issue_slots[8].in_uop.bits.br_tag, issue_slots[9].out_uop.br_tag connect issue_slots[8].in_uop.bits.br_mask, issue_slots[9].out_uop.br_mask connect issue_slots[8].in_uop.bits.dis_col_sel, issue_slots[9].out_uop.dis_col_sel connect issue_slots[8].in_uop.bits.iw_p3_bypass_hint, issue_slots[9].out_uop.iw_p3_bypass_hint connect issue_slots[8].in_uop.bits.iw_p2_bypass_hint, issue_slots[9].out_uop.iw_p2_bypass_hint connect issue_slots[8].in_uop.bits.iw_p1_bypass_hint, issue_slots[9].out_uop.iw_p1_bypass_hint connect issue_slots[8].in_uop.bits.iw_p2_speculative_child, issue_slots[9].out_uop.iw_p2_speculative_child connect issue_slots[8].in_uop.bits.iw_p1_speculative_child, issue_slots[9].out_uop.iw_p1_speculative_child connect issue_slots[8].in_uop.bits.iw_issued_partial_dgen, issue_slots[9].out_uop.iw_issued_partial_dgen connect issue_slots[8].in_uop.bits.iw_issued_partial_agen, issue_slots[9].out_uop.iw_issued_partial_agen connect issue_slots[8].in_uop.bits.iw_issued, issue_slots[9].out_uop.iw_issued connect issue_slots[8].in_uop.bits.fu_code[0], issue_slots[9].out_uop.fu_code[0] connect issue_slots[8].in_uop.bits.fu_code[1], issue_slots[9].out_uop.fu_code[1] connect issue_slots[8].in_uop.bits.fu_code[2], issue_slots[9].out_uop.fu_code[2] connect issue_slots[8].in_uop.bits.fu_code[3], issue_slots[9].out_uop.fu_code[3] connect issue_slots[8].in_uop.bits.fu_code[4], issue_slots[9].out_uop.fu_code[4] connect issue_slots[8].in_uop.bits.fu_code[5], issue_slots[9].out_uop.fu_code[5] connect issue_slots[8].in_uop.bits.fu_code[6], issue_slots[9].out_uop.fu_code[6] connect issue_slots[8].in_uop.bits.fu_code[7], issue_slots[9].out_uop.fu_code[7] connect issue_slots[8].in_uop.bits.fu_code[8], issue_slots[9].out_uop.fu_code[8] connect issue_slots[8].in_uop.bits.fu_code[9], issue_slots[9].out_uop.fu_code[9] connect issue_slots[8].in_uop.bits.iq_type[0], issue_slots[9].out_uop.iq_type[0] connect issue_slots[8].in_uop.bits.iq_type[1], issue_slots[9].out_uop.iq_type[1] connect issue_slots[8].in_uop.bits.iq_type[2], issue_slots[9].out_uop.iq_type[2] connect issue_slots[8].in_uop.bits.iq_type[3], issue_slots[9].out_uop.iq_type[3] connect issue_slots[8].in_uop.bits.debug_pc, issue_slots[9].out_uop.debug_pc connect issue_slots[8].in_uop.bits.is_rvc, issue_slots[9].out_uop.is_rvc connect issue_slots[8].in_uop.bits.debug_inst, issue_slots[9].out_uop.debug_inst connect issue_slots[8].in_uop.bits.inst, issue_slots[9].out_uop.inst node _T_302 = eq(shamts_oh[10], UInt<2>(0h2)) when _T_302 : connect issue_slots[8].in_uop.valid, issue_slots[10].will_be_valid connect issue_slots[8].in_uop.bits.debug_tsrc, issue_slots[10].out_uop.debug_tsrc connect issue_slots[8].in_uop.bits.debug_fsrc, issue_slots[10].out_uop.debug_fsrc connect issue_slots[8].in_uop.bits.bp_xcpt_if, issue_slots[10].out_uop.bp_xcpt_if connect issue_slots[8].in_uop.bits.bp_debug_if, issue_slots[10].out_uop.bp_debug_if connect issue_slots[8].in_uop.bits.xcpt_ma_if, issue_slots[10].out_uop.xcpt_ma_if connect issue_slots[8].in_uop.bits.xcpt_ae_if, issue_slots[10].out_uop.xcpt_ae_if connect issue_slots[8].in_uop.bits.xcpt_pf_if, issue_slots[10].out_uop.xcpt_pf_if connect issue_slots[8].in_uop.bits.fp_typ, issue_slots[10].out_uop.fp_typ connect issue_slots[8].in_uop.bits.fp_rm, issue_slots[10].out_uop.fp_rm connect issue_slots[8].in_uop.bits.fp_val, issue_slots[10].out_uop.fp_val connect issue_slots[8].in_uop.bits.fcn_op, issue_slots[10].out_uop.fcn_op connect issue_slots[8].in_uop.bits.fcn_dw, issue_slots[10].out_uop.fcn_dw connect issue_slots[8].in_uop.bits.frs3_en, issue_slots[10].out_uop.frs3_en connect issue_slots[8].in_uop.bits.lrs2_rtype, issue_slots[10].out_uop.lrs2_rtype connect issue_slots[8].in_uop.bits.lrs1_rtype, issue_slots[10].out_uop.lrs1_rtype connect issue_slots[8].in_uop.bits.dst_rtype, issue_slots[10].out_uop.dst_rtype connect issue_slots[8].in_uop.bits.lrs3, issue_slots[10].out_uop.lrs3 connect issue_slots[8].in_uop.bits.lrs2, issue_slots[10].out_uop.lrs2 connect issue_slots[8].in_uop.bits.lrs1, issue_slots[10].out_uop.lrs1 connect issue_slots[8].in_uop.bits.ldst, issue_slots[10].out_uop.ldst connect issue_slots[8].in_uop.bits.ldst_is_rs1, issue_slots[10].out_uop.ldst_is_rs1 connect issue_slots[8].in_uop.bits.csr_cmd, issue_slots[10].out_uop.csr_cmd connect issue_slots[8].in_uop.bits.flush_on_commit, issue_slots[10].out_uop.flush_on_commit connect issue_slots[8].in_uop.bits.is_unique, issue_slots[10].out_uop.is_unique connect issue_slots[8].in_uop.bits.uses_stq, issue_slots[10].out_uop.uses_stq connect issue_slots[8].in_uop.bits.uses_ldq, issue_slots[10].out_uop.uses_ldq connect issue_slots[8].in_uop.bits.mem_signed, issue_slots[10].out_uop.mem_signed connect issue_slots[8].in_uop.bits.mem_size, issue_slots[10].out_uop.mem_size connect issue_slots[8].in_uop.bits.mem_cmd, issue_slots[10].out_uop.mem_cmd connect issue_slots[8].in_uop.bits.exc_cause, issue_slots[10].out_uop.exc_cause connect issue_slots[8].in_uop.bits.exception, issue_slots[10].out_uop.exception connect issue_slots[8].in_uop.bits.stale_pdst, issue_slots[10].out_uop.stale_pdst connect issue_slots[8].in_uop.bits.ppred_busy, issue_slots[10].out_uop.ppred_busy connect issue_slots[8].in_uop.bits.prs3_busy, issue_slots[10].out_uop.prs3_busy connect issue_slots[8].in_uop.bits.prs2_busy, issue_slots[10].out_uop.prs2_busy connect issue_slots[8].in_uop.bits.prs1_busy, issue_slots[10].out_uop.prs1_busy connect issue_slots[8].in_uop.bits.ppred, issue_slots[10].out_uop.ppred connect issue_slots[8].in_uop.bits.prs3, issue_slots[10].out_uop.prs3 connect issue_slots[8].in_uop.bits.prs2, issue_slots[10].out_uop.prs2 connect issue_slots[8].in_uop.bits.prs1, issue_slots[10].out_uop.prs1 connect issue_slots[8].in_uop.bits.pdst, issue_slots[10].out_uop.pdst connect issue_slots[8].in_uop.bits.rxq_idx, issue_slots[10].out_uop.rxq_idx connect issue_slots[8].in_uop.bits.stq_idx, issue_slots[10].out_uop.stq_idx connect issue_slots[8].in_uop.bits.ldq_idx, issue_slots[10].out_uop.ldq_idx connect issue_slots[8].in_uop.bits.rob_idx, issue_slots[10].out_uop.rob_idx connect issue_slots[8].in_uop.bits.fp_ctrl.vec, issue_slots[10].out_uop.fp_ctrl.vec connect issue_slots[8].in_uop.bits.fp_ctrl.wflags, issue_slots[10].out_uop.fp_ctrl.wflags connect issue_slots[8].in_uop.bits.fp_ctrl.sqrt, issue_slots[10].out_uop.fp_ctrl.sqrt connect issue_slots[8].in_uop.bits.fp_ctrl.div, issue_slots[10].out_uop.fp_ctrl.div connect issue_slots[8].in_uop.bits.fp_ctrl.fma, issue_slots[10].out_uop.fp_ctrl.fma connect issue_slots[8].in_uop.bits.fp_ctrl.fastpipe, issue_slots[10].out_uop.fp_ctrl.fastpipe connect issue_slots[8].in_uop.bits.fp_ctrl.toint, issue_slots[10].out_uop.fp_ctrl.toint connect issue_slots[8].in_uop.bits.fp_ctrl.fromint, issue_slots[10].out_uop.fp_ctrl.fromint connect issue_slots[8].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[10].out_uop.fp_ctrl.typeTagOut connect issue_slots[8].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[10].out_uop.fp_ctrl.typeTagIn connect issue_slots[8].in_uop.bits.fp_ctrl.swap23, issue_slots[10].out_uop.fp_ctrl.swap23 connect issue_slots[8].in_uop.bits.fp_ctrl.swap12, issue_slots[10].out_uop.fp_ctrl.swap12 connect issue_slots[8].in_uop.bits.fp_ctrl.ren3, issue_slots[10].out_uop.fp_ctrl.ren3 connect issue_slots[8].in_uop.bits.fp_ctrl.ren2, issue_slots[10].out_uop.fp_ctrl.ren2 connect issue_slots[8].in_uop.bits.fp_ctrl.ren1, issue_slots[10].out_uop.fp_ctrl.ren1 connect issue_slots[8].in_uop.bits.fp_ctrl.wen, issue_slots[10].out_uop.fp_ctrl.wen connect issue_slots[8].in_uop.bits.fp_ctrl.ldst, issue_slots[10].out_uop.fp_ctrl.ldst connect issue_slots[8].in_uop.bits.op2_sel, issue_slots[10].out_uop.op2_sel connect issue_slots[8].in_uop.bits.op1_sel, issue_slots[10].out_uop.op1_sel connect issue_slots[8].in_uop.bits.imm_packed, issue_slots[10].out_uop.imm_packed connect issue_slots[8].in_uop.bits.pimm, issue_slots[10].out_uop.pimm connect issue_slots[8].in_uop.bits.imm_sel, issue_slots[10].out_uop.imm_sel connect issue_slots[8].in_uop.bits.imm_rename, issue_slots[10].out_uop.imm_rename connect issue_slots[8].in_uop.bits.taken, issue_slots[10].out_uop.taken connect issue_slots[8].in_uop.bits.pc_lob, issue_slots[10].out_uop.pc_lob connect issue_slots[8].in_uop.bits.edge_inst, issue_slots[10].out_uop.edge_inst connect issue_slots[8].in_uop.bits.ftq_idx, issue_slots[10].out_uop.ftq_idx connect issue_slots[8].in_uop.bits.is_mov, issue_slots[10].out_uop.is_mov connect issue_slots[8].in_uop.bits.is_rocc, issue_slots[10].out_uop.is_rocc connect issue_slots[8].in_uop.bits.is_sys_pc2epc, issue_slots[10].out_uop.is_sys_pc2epc connect issue_slots[8].in_uop.bits.is_eret, issue_slots[10].out_uop.is_eret connect issue_slots[8].in_uop.bits.is_amo, issue_slots[10].out_uop.is_amo connect issue_slots[8].in_uop.bits.is_sfence, issue_slots[10].out_uop.is_sfence connect issue_slots[8].in_uop.bits.is_fencei, issue_slots[10].out_uop.is_fencei connect issue_slots[8].in_uop.bits.is_fence, issue_slots[10].out_uop.is_fence connect issue_slots[8].in_uop.bits.is_sfb, issue_slots[10].out_uop.is_sfb connect issue_slots[8].in_uop.bits.br_type, issue_slots[10].out_uop.br_type connect issue_slots[8].in_uop.bits.br_tag, issue_slots[10].out_uop.br_tag connect issue_slots[8].in_uop.bits.br_mask, issue_slots[10].out_uop.br_mask connect issue_slots[8].in_uop.bits.dis_col_sel, issue_slots[10].out_uop.dis_col_sel connect issue_slots[8].in_uop.bits.iw_p3_bypass_hint, issue_slots[10].out_uop.iw_p3_bypass_hint connect issue_slots[8].in_uop.bits.iw_p2_bypass_hint, issue_slots[10].out_uop.iw_p2_bypass_hint connect issue_slots[8].in_uop.bits.iw_p1_bypass_hint, issue_slots[10].out_uop.iw_p1_bypass_hint connect issue_slots[8].in_uop.bits.iw_p2_speculative_child, issue_slots[10].out_uop.iw_p2_speculative_child connect issue_slots[8].in_uop.bits.iw_p1_speculative_child, issue_slots[10].out_uop.iw_p1_speculative_child connect issue_slots[8].in_uop.bits.iw_issued_partial_dgen, issue_slots[10].out_uop.iw_issued_partial_dgen connect issue_slots[8].in_uop.bits.iw_issued_partial_agen, issue_slots[10].out_uop.iw_issued_partial_agen connect issue_slots[8].in_uop.bits.iw_issued, issue_slots[10].out_uop.iw_issued connect issue_slots[8].in_uop.bits.fu_code[0], issue_slots[10].out_uop.fu_code[0] connect issue_slots[8].in_uop.bits.fu_code[1], issue_slots[10].out_uop.fu_code[1] connect issue_slots[8].in_uop.bits.fu_code[2], issue_slots[10].out_uop.fu_code[2] connect issue_slots[8].in_uop.bits.fu_code[3], issue_slots[10].out_uop.fu_code[3] connect issue_slots[8].in_uop.bits.fu_code[4], issue_slots[10].out_uop.fu_code[4] connect issue_slots[8].in_uop.bits.fu_code[5], issue_slots[10].out_uop.fu_code[5] connect issue_slots[8].in_uop.bits.fu_code[6], issue_slots[10].out_uop.fu_code[6] connect issue_slots[8].in_uop.bits.fu_code[7], issue_slots[10].out_uop.fu_code[7] connect issue_slots[8].in_uop.bits.fu_code[8], issue_slots[10].out_uop.fu_code[8] connect issue_slots[8].in_uop.bits.fu_code[9], issue_slots[10].out_uop.fu_code[9] connect issue_slots[8].in_uop.bits.iq_type[0], issue_slots[10].out_uop.iq_type[0] connect issue_slots[8].in_uop.bits.iq_type[1], issue_slots[10].out_uop.iq_type[1] connect issue_slots[8].in_uop.bits.iq_type[2], issue_slots[10].out_uop.iq_type[2] connect issue_slots[8].in_uop.bits.iq_type[3], issue_slots[10].out_uop.iq_type[3] connect issue_slots[8].in_uop.bits.debug_pc, issue_slots[10].out_uop.debug_pc connect issue_slots[8].in_uop.bits.is_rvc, issue_slots[10].out_uop.is_rvc connect issue_slots[8].in_uop.bits.debug_inst, issue_slots[10].out_uop.debug_inst connect issue_slots[8].in_uop.bits.inst, issue_slots[10].out_uop.inst node _T_303 = eq(shamts_oh[11], UInt<3>(0h4)) when _T_303 : connect issue_slots[8].in_uop.valid, issue_slots[11].will_be_valid connect issue_slots[8].in_uop.bits.debug_tsrc, issue_slots[11].out_uop.debug_tsrc connect issue_slots[8].in_uop.bits.debug_fsrc, issue_slots[11].out_uop.debug_fsrc connect issue_slots[8].in_uop.bits.bp_xcpt_if, issue_slots[11].out_uop.bp_xcpt_if connect issue_slots[8].in_uop.bits.bp_debug_if, issue_slots[11].out_uop.bp_debug_if connect issue_slots[8].in_uop.bits.xcpt_ma_if, issue_slots[11].out_uop.xcpt_ma_if connect issue_slots[8].in_uop.bits.xcpt_ae_if, issue_slots[11].out_uop.xcpt_ae_if connect issue_slots[8].in_uop.bits.xcpt_pf_if, issue_slots[11].out_uop.xcpt_pf_if connect issue_slots[8].in_uop.bits.fp_typ, issue_slots[11].out_uop.fp_typ connect issue_slots[8].in_uop.bits.fp_rm, issue_slots[11].out_uop.fp_rm connect issue_slots[8].in_uop.bits.fp_val, issue_slots[11].out_uop.fp_val connect issue_slots[8].in_uop.bits.fcn_op, issue_slots[11].out_uop.fcn_op connect issue_slots[8].in_uop.bits.fcn_dw, issue_slots[11].out_uop.fcn_dw connect issue_slots[8].in_uop.bits.frs3_en, issue_slots[11].out_uop.frs3_en connect issue_slots[8].in_uop.bits.lrs2_rtype, issue_slots[11].out_uop.lrs2_rtype connect issue_slots[8].in_uop.bits.lrs1_rtype, issue_slots[11].out_uop.lrs1_rtype connect issue_slots[8].in_uop.bits.dst_rtype, issue_slots[11].out_uop.dst_rtype connect issue_slots[8].in_uop.bits.lrs3, issue_slots[11].out_uop.lrs3 connect issue_slots[8].in_uop.bits.lrs2, issue_slots[11].out_uop.lrs2 connect issue_slots[8].in_uop.bits.lrs1, issue_slots[11].out_uop.lrs1 connect issue_slots[8].in_uop.bits.ldst, issue_slots[11].out_uop.ldst connect issue_slots[8].in_uop.bits.ldst_is_rs1, issue_slots[11].out_uop.ldst_is_rs1 connect issue_slots[8].in_uop.bits.csr_cmd, issue_slots[11].out_uop.csr_cmd connect issue_slots[8].in_uop.bits.flush_on_commit, issue_slots[11].out_uop.flush_on_commit connect issue_slots[8].in_uop.bits.is_unique, issue_slots[11].out_uop.is_unique connect issue_slots[8].in_uop.bits.uses_stq, issue_slots[11].out_uop.uses_stq connect issue_slots[8].in_uop.bits.uses_ldq, issue_slots[11].out_uop.uses_ldq connect issue_slots[8].in_uop.bits.mem_signed, issue_slots[11].out_uop.mem_signed connect issue_slots[8].in_uop.bits.mem_size, issue_slots[11].out_uop.mem_size connect issue_slots[8].in_uop.bits.mem_cmd, issue_slots[11].out_uop.mem_cmd connect issue_slots[8].in_uop.bits.exc_cause, issue_slots[11].out_uop.exc_cause connect issue_slots[8].in_uop.bits.exception, issue_slots[11].out_uop.exception connect issue_slots[8].in_uop.bits.stale_pdst, issue_slots[11].out_uop.stale_pdst connect issue_slots[8].in_uop.bits.ppred_busy, issue_slots[11].out_uop.ppred_busy connect issue_slots[8].in_uop.bits.prs3_busy, issue_slots[11].out_uop.prs3_busy connect issue_slots[8].in_uop.bits.prs2_busy, issue_slots[11].out_uop.prs2_busy connect issue_slots[8].in_uop.bits.prs1_busy, issue_slots[11].out_uop.prs1_busy connect issue_slots[8].in_uop.bits.ppred, issue_slots[11].out_uop.ppred connect issue_slots[8].in_uop.bits.prs3, issue_slots[11].out_uop.prs3 connect issue_slots[8].in_uop.bits.prs2, issue_slots[11].out_uop.prs2 connect issue_slots[8].in_uop.bits.prs1, issue_slots[11].out_uop.prs1 connect issue_slots[8].in_uop.bits.pdst, issue_slots[11].out_uop.pdst connect issue_slots[8].in_uop.bits.rxq_idx, issue_slots[11].out_uop.rxq_idx connect issue_slots[8].in_uop.bits.stq_idx, issue_slots[11].out_uop.stq_idx connect issue_slots[8].in_uop.bits.ldq_idx, issue_slots[11].out_uop.ldq_idx connect issue_slots[8].in_uop.bits.rob_idx, issue_slots[11].out_uop.rob_idx connect issue_slots[8].in_uop.bits.fp_ctrl.vec, issue_slots[11].out_uop.fp_ctrl.vec connect issue_slots[8].in_uop.bits.fp_ctrl.wflags, issue_slots[11].out_uop.fp_ctrl.wflags connect issue_slots[8].in_uop.bits.fp_ctrl.sqrt, issue_slots[11].out_uop.fp_ctrl.sqrt connect issue_slots[8].in_uop.bits.fp_ctrl.div, issue_slots[11].out_uop.fp_ctrl.div connect issue_slots[8].in_uop.bits.fp_ctrl.fma, issue_slots[11].out_uop.fp_ctrl.fma connect issue_slots[8].in_uop.bits.fp_ctrl.fastpipe, issue_slots[11].out_uop.fp_ctrl.fastpipe connect issue_slots[8].in_uop.bits.fp_ctrl.toint, issue_slots[11].out_uop.fp_ctrl.toint connect issue_slots[8].in_uop.bits.fp_ctrl.fromint, issue_slots[11].out_uop.fp_ctrl.fromint connect issue_slots[8].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[11].out_uop.fp_ctrl.typeTagOut connect issue_slots[8].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[11].out_uop.fp_ctrl.typeTagIn connect issue_slots[8].in_uop.bits.fp_ctrl.swap23, issue_slots[11].out_uop.fp_ctrl.swap23 connect issue_slots[8].in_uop.bits.fp_ctrl.swap12, issue_slots[11].out_uop.fp_ctrl.swap12 connect issue_slots[8].in_uop.bits.fp_ctrl.ren3, issue_slots[11].out_uop.fp_ctrl.ren3 connect issue_slots[8].in_uop.bits.fp_ctrl.ren2, issue_slots[11].out_uop.fp_ctrl.ren2 connect issue_slots[8].in_uop.bits.fp_ctrl.ren1, issue_slots[11].out_uop.fp_ctrl.ren1 connect issue_slots[8].in_uop.bits.fp_ctrl.wen, issue_slots[11].out_uop.fp_ctrl.wen connect issue_slots[8].in_uop.bits.fp_ctrl.ldst, issue_slots[11].out_uop.fp_ctrl.ldst connect issue_slots[8].in_uop.bits.op2_sel, issue_slots[11].out_uop.op2_sel connect issue_slots[8].in_uop.bits.op1_sel, issue_slots[11].out_uop.op1_sel connect issue_slots[8].in_uop.bits.imm_packed, issue_slots[11].out_uop.imm_packed connect issue_slots[8].in_uop.bits.pimm, issue_slots[11].out_uop.pimm connect issue_slots[8].in_uop.bits.imm_sel, issue_slots[11].out_uop.imm_sel connect issue_slots[8].in_uop.bits.imm_rename, issue_slots[11].out_uop.imm_rename connect issue_slots[8].in_uop.bits.taken, issue_slots[11].out_uop.taken connect issue_slots[8].in_uop.bits.pc_lob, issue_slots[11].out_uop.pc_lob connect issue_slots[8].in_uop.bits.edge_inst, issue_slots[11].out_uop.edge_inst connect issue_slots[8].in_uop.bits.ftq_idx, issue_slots[11].out_uop.ftq_idx connect issue_slots[8].in_uop.bits.is_mov, issue_slots[11].out_uop.is_mov connect issue_slots[8].in_uop.bits.is_rocc, issue_slots[11].out_uop.is_rocc connect issue_slots[8].in_uop.bits.is_sys_pc2epc, issue_slots[11].out_uop.is_sys_pc2epc connect issue_slots[8].in_uop.bits.is_eret, issue_slots[11].out_uop.is_eret connect issue_slots[8].in_uop.bits.is_amo, issue_slots[11].out_uop.is_amo connect issue_slots[8].in_uop.bits.is_sfence, issue_slots[11].out_uop.is_sfence connect issue_slots[8].in_uop.bits.is_fencei, issue_slots[11].out_uop.is_fencei connect issue_slots[8].in_uop.bits.is_fence, issue_slots[11].out_uop.is_fence connect issue_slots[8].in_uop.bits.is_sfb, issue_slots[11].out_uop.is_sfb connect issue_slots[8].in_uop.bits.br_type, issue_slots[11].out_uop.br_type connect issue_slots[8].in_uop.bits.br_tag, issue_slots[11].out_uop.br_tag connect issue_slots[8].in_uop.bits.br_mask, issue_slots[11].out_uop.br_mask connect issue_slots[8].in_uop.bits.dis_col_sel, issue_slots[11].out_uop.dis_col_sel connect issue_slots[8].in_uop.bits.iw_p3_bypass_hint, issue_slots[11].out_uop.iw_p3_bypass_hint connect issue_slots[8].in_uop.bits.iw_p2_bypass_hint, issue_slots[11].out_uop.iw_p2_bypass_hint connect issue_slots[8].in_uop.bits.iw_p1_bypass_hint, issue_slots[11].out_uop.iw_p1_bypass_hint connect issue_slots[8].in_uop.bits.iw_p2_speculative_child, issue_slots[11].out_uop.iw_p2_speculative_child connect issue_slots[8].in_uop.bits.iw_p1_speculative_child, issue_slots[11].out_uop.iw_p1_speculative_child connect issue_slots[8].in_uop.bits.iw_issued_partial_dgen, issue_slots[11].out_uop.iw_issued_partial_dgen connect issue_slots[8].in_uop.bits.iw_issued_partial_agen, issue_slots[11].out_uop.iw_issued_partial_agen connect issue_slots[8].in_uop.bits.iw_issued, issue_slots[11].out_uop.iw_issued connect issue_slots[8].in_uop.bits.fu_code[0], issue_slots[11].out_uop.fu_code[0] connect issue_slots[8].in_uop.bits.fu_code[1], issue_slots[11].out_uop.fu_code[1] connect issue_slots[8].in_uop.bits.fu_code[2], issue_slots[11].out_uop.fu_code[2] connect issue_slots[8].in_uop.bits.fu_code[3], issue_slots[11].out_uop.fu_code[3] connect issue_slots[8].in_uop.bits.fu_code[4], issue_slots[11].out_uop.fu_code[4] connect issue_slots[8].in_uop.bits.fu_code[5], issue_slots[11].out_uop.fu_code[5] connect issue_slots[8].in_uop.bits.fu_code[6], issue_slots[11].out_uop.fu_code[6] connect issue_slots[8].in_uop.bits.fu_code[7], issue_slots[11].out_uop.fu_code[7] connect issue_slots[8].in_uop.bits.fu_code[8], issue_slots[11].out_uop.fu_code[8] connect issue_slots[8].in_uop.bits.fu_code[9], issue_slots[11].out_uop.fu_code[9] connect issue_slots[8].in_uop.bits.iq_type[0], issue_slots[11].out_uop.iq_type[0] connect issue_slots[8].in_uop.bits.iq_type[1], issue_slots[11].out_uop.iq_type[1] connect issue_slots[8].in_uop.bits.iq_type[2], issue_slots[11].out_uop.iq_type[2] connect issue_slots[8].in_uop.bits.iq_type[3], issue_slots[11].out_uop.iq_type[3] connect issue_slots[8].in_uop.bits.debug_pc, issue_slots[11].out_uop.debug_pc connect issue_slots[8].in_uop.bits.is_rvc, issue_slots[11].out_uop.is_rvc connect issue_slots[8].in_uop.bits.debug_inst, issue_slots[11].out_uop.debug_inst connect issue_slots[8].in_uop.bits.inst, issue_slots[11].out_uop.inst node _issue_slots_8_clear_T = neq(shamts_oh[8], UInt<1>(0h0)) connect issue_slots[8].clear, _issue_slots_8_clear_T connect issue_slots[9].in_uop.valid, UInt<1>(0h0) connect issue_slots[9].in_uop.bits.debug_tsrc, issue_slots[10].out_uop.debug_tsrc connect issue_slots[9].in_uop.bits.debug_fsrc, issue_slots[10].out_uop.debug_fsrc connect issue_slots[9].in_uop.bits.bp_xcpt_if, issue_slots[10].out_uop.bp_xcpt_if connect issue_slots[9].in_uop.bits.bp_debug_if, issue_slots[10].out_uop.bp_debug_if connect issue_slots[9].in_uop.bits.xcpt_ma_if, issue_slots[10].out_uop.xcpt_ma_if connect issue_slots[9].in_uop.bits.xcpt_ae_if, issue_slots[10].out_uop.xcpt_ae_if connect issue_slots[9].in_uop.bits.xcpt_pf_if, issue_slots[10].out_uop.xcpt_pf_if connect issue_slots[9].in_uop.bits.fp_typ, issue_slots[10].out_uop.fp_typ connect issue_slots[9].in_uop.bits.fp_rm, issue_slots[10].out_uop.fp_rm connect issue_slots[9].in_uop.bits.fp_val, issue_slots[10].out_uop.fp_val connect issue_slots[9].in_uop.bits.fcn_op, issue_slots[10].out_uop.fcn_op connect issue_slots[9].in_uop.bits.fcn_dw, issue_slots[10].out_uop.fcn_dw connect issue_slots[9].in_uop.bits.frs3_en, issue_slots[10].out_uop.frs3_en connect issue_slots[9].in_uop.bits.lrs2_rtype, issue_slots[10].out_uop.lrs2_rtype connect issue_slots[9].in_uop.bits.lrs1_rtype, issue_slots[10].out_uop.lrs1_rtype connect issue_slots[9].in_uop.bits.dst_rtype, issue_slots[10].out_uop.dst_rtype connect issue_slots[9].in_uop.bits.lrs3, issue_slots[10].out_uop.lrs3 connect issue_slots[9].in_uop.bits.lrs2, issue_slots[10].out_uop.lrs2 connect issue_slots[9].in_uop.bits.lrs1, issue_slots[10].out_uop.lrs1 connect issue_slots[9].in_uop.bits.ldst, issue_slots[10].out_uop.ldst connect issue_slots[9].in_uop.bits.ldst_is_rs1, issue_slots[10].out_uop.ldst_is_rs1 connect issue_slots[9].in_uop.bits.csr_cmd, issue_slots[10].out_uop.csr_cmd connect issue_slots[9].in_uop.bits.flush_on_commit, issue_slots[10].out_uop.flush_on_commit connect issue_slots[9].in_uop.bits.is_unique, issue_slots[10].out_uop.is_unique connect issue_slots[9].in_uop.bits.uses_stq, issue_slots[10].out_uop.uses_stq connect issue_slots[9].in_uop.bits.uses_ldq, issue_slots[10].out_uop.uses_ldq connect issue_slots[9].in_uop.bits.mem_signed, issue_slots[10].out_uop.mem_signed connect issue_slots[9].in_uop.bits.mem_size, issue_slots[10].out_uop.mem_size connect issue_slots[9].in_uop.bits.mem_cmd, issue_slots[10].out_uop.mem_cmd connect issue_slots[9].in_uop.bits.exc_cause, issue_slots[10].out_uop.exc_cause connect issue_slots[9].in_uop.bits.exception, issue_slots[10].out_uop.exception connect issue_slots[9].in_uop.bits.stale_pdst, issue_slots[10].out_uop.stale_pdst connect issue_slots[9].in_uop.bits.ppred_busy, issue_slots[10].out_uop.ppred_busy connect issue_slots[9].in_uop.bits.prs3_busy, issue_slots[10].out_uop.prs3_busy connect issue_slots[9].in_uop.bits.prs2_busy, issue_slots[10].out_uop.prs2_busy connect issue_slots[9].in_uop.bits.prs1_busy, issue_slots[10].out_uop.prs1_busy connect issue_slots[9].in_uop.bits.ppred, issue_slots[10].out_uop.ppred connect issue_slots[9].in_uop.bits.prs3, issue_slots[10].out_uop.prs3 connect issue_slots[9].in_uop.bits.prs2, issue_slots[10].out_uop.prs2 connect issue_slots[9].in_uop.bits.prs1, issue_slots[10].out_uop.prs1 connect issue_slots[9].in_uop.bits.pdst, issue_slots[10].out_uop.pdst connect issue_slots[9].in_uop.bits.rxq_idx, issue_slots[10].out_uop.rxq_idx connect issue_slots[9].in_uop.bits.stq_idx, issue_slots[10].out_uop.stq_idx connect issue_slots[9].in_uop.bits.ldq_idx, issue_slots[10].out_uop.ldq_idx connect issue_slots[9].in_uop.bits.rob_idx, issue_slots[10].out_uop.rob_idx connect issue_slots[9].in_uop.bits.fp_ctrl.vec, issue_slots[10].out_uop.fp_ctrl.vec connect issue_slots[9].in_uop.bits.fp_ctrl.wflags, issue_slots[10].out_uop.fp_ctrl.wflags connect issue_slots[9].in_uop.bits.fp_ctrl.sqrt, issue_slots[10].out_uop.fp_ctrl.sqrt connect issue_slots[9].in_uop.bits.fp_ctrl.div, issue_slots[10].out_uop.fp_ctrl.div connect issue_slots[9].in_uop.bits.fp_ctrl.fma, issue_slots[10].out_uop.fp_ctrl.fma connect issue_slots[9].in_uop.bits.fp_ctrl.fastpipe, issue_slots[10].out_uop.fp_ctrl.fastpipe connect issue_slots[9].in_uop.bits.fp_ctrl.toint, issue_slots[10].out_uop.fp_ctrl.toint connect issue_slots[9].in_uop.bits.fp_ctrl.fromint, issue_slots[10].out_uop.fp_ctrl.fromint connect issue_slots[9].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[10].out_uop.fp_ctrl.typeTagOut connect issue_slots[9].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[10].out_uop.fp_ctrl.typeTagIn connect issue_slots[9].in_uop.bits.fp_ctrl.swap23, issue_slots[10].out_uop.fp_ctrl.swap23 connect issue_slots[9].in_uop.bits.fp_ctrl.swap12, issue_slots[10].out_uop.fp_ctrl.swap12 connect issue_slots[9].in_uop.bits.fp_ctrl.ren3, issue_slots[10].out_uop.fp_ctrl.ren3 connect issue_slots[9].in_uop.bits.fp_ctrl.ren2, issue_slots[10].out_uop.fp_ctrl.ren2 connect issue_slots[9].in_uop.bits.fp_ctrl.ren1, issue_slots[10].out_uop.fp_ctrl.ren1 connect issue_slots[9].in_uop.bits.fp_ctrl.wen, issue_slots[10].out_uop.fp_ctrl.wen connect issue_slots[9].in_uop.bits.fp_ctrl.ldst, issue_slots[10].out_uop.fp_ctrl.ldst connect issue_slots[9].in_uop.bits.op2_sel, issue_slots[10].out_uop.op2_sel connect issue_slots[9].in_uop.bits.op1_sel, issue_slots[10].out_uop.op1_sel connect issue_slots[9].in_uop.bits.imm_packed, issue_slots[10].out_uop.imm_packed connect issue_slots[9].in_uop.bits.pimm, issue_slots[10].out_uop.pimm connect issue_slots[9].in_uop.bits.imm_sel, issue_slots[10].out_uop.imm_sel connect issue_slots[9].in_uop.bits.imm_rename, issue_slots[10].out_uop.imm_rename connect issue_slots[9].in_uop.bits.taken, issue_slots[10].out_uop.taken connect issue_slots[9].in_uop.bits.pc_lob, issue_slots[10].out_uop.pc_lob connect issue_slots[9].in_uop.bits.edge_inst, issue_slots[10].out_uop.edge_inst connect issue_slots[9].in_uop.bits.ftq_idx, issue_slots[10].out_uop.ftq_idx connect issue_slots[9].in_uop.bits.is_mov, issue_slots[10].out_uop.is_mov connect issue_slots[9].in_uop.bits.is_rocc, issue_slots[10].out_uop.is_rocc connect issue_slots[9].in_uop.bits.is_sys_pc2epc, issue_slots[10].out_uop.is_sys_pc2epc connect issue_slots[9].in_uop.bits.is_eret, issue_slots[10].out_uop.is_eret connect issue_slots[9].in_uop.bits.is_amo, issue_slots[10].out_uop.is_amo connect issue_slots[9].in_uop.bits.is_sfence, issue_slots[10].out_uop.is_sfence connect issue_slots[9].in_uop.bits.is_fencei, issue_slots[10].out_uop.is_fencei connect issue_slots[9].in_uop.bits.is_fence, issue_slots[10].out_uop.is_fence connect issue_slots[9].in_uop.bits.is_sfb, issue_slots[10].out_uop.is_sfb connect issue_slots[9].in_uop.bits.br_type, issue_slots[10].out_uop.br_type connect issue_slots[9].in_uop.bits.br_tag, issue_slots[10].out_uop.br_tag connect issue_slots[9].in_uop.bits.br_mask, issue_slots[10].out_uop.br_mask connect issue_slots[9].in_uop.bits.dis_col_sel, issue_slots[10].out_uop.dis_col_sel connect issue_slots[9].in_uop.bits.iw_p3_bypass_hint, issue_slots[10].out_uop.iw_p3_bypass_hint connect issue_slots[9].in_uop.bits.iw_p2_bypass_hint, issue_slots[10].out_uop.iw_p2_bypass_hint connect issue_slots[9].in_uop.bits.iw_p1_bypass_hint, issue_slots[10].out_uop.iw_p1_bypass_hint connect issue_slots[9].in_uop.bits.iw_p2_speculative_child, issue_slots[10].out_uop.iw_p2_speculative_child connect issue_slots[9].in_uop.bits.iw_p1_speculative_child, issue_slots[10].out_uop.iw_p1_speculative_child connect issue_slots[9].in_uop.bits.iw_issued_partial_dgen, issue_slots[10].out_uop.iw_issued_partial_dgen connect issue_slots[9].in_uop.bits.iw_issued_partial_agen, issue_slots[10].out_uop.iw_issued_partial_agen connect issue_slots[9].in_uop.bits.iw_issued, issue_slots[10].out_uop.iw_issued connect issue_slots[9].in_uop.bits.fu_code[0], issue_slots[10].out_uop.fu_code[0] connect issue_slots[9].in_uop.bits.fu_code[1], issue_slots[10].out_uop.fu_code[1] connect issue_slots[9].in_uop.bits.fu_code[2], issue_slots[10].out_uop.fu_code[2] connect issue_slots[9].in_uop.bits.fu_code[3], issue_slots[10].out_uop.fu_code[3] connect issue_slots[9].in_uop.bits.fu_code[4], issue_slots[10].out_uop.fu_code[4] connect issue_slots[9].in_uop.bits.fu_code[5], issue_slots[10].out_uop.fu_code[5] connect issue_slots[9].in_uop.bits.fu_code[6], issue_slots[10].out_uop.fu_code[6] connect issue_slots[9].in_uop.bits.fu_code[7], issue_slots[10].out_uop.fu_code[7] connect issue_slots[9].in_uop.bits.fu_code[8], issue_slots[10].out_uop.fu_code[8] connect issue_slots[9].in_uop.bits.fu_code[9], issue_slots[10].out_uop.fu_code[9] connect issue_slots[9].in_uop.bits.iq_type[0], issue_slots[10].out_uop.iq_type[0] connect issue_slots[9].in_uop.bits.iq_type[1], issue_slots[10].out_uop.iq_type[1] connect issue_slots[9].in_uop.bits.iq_type[2], issue_slots[10].out_uop.iq_type[2] connect issue_slots[9].in_uop.bits.iq_type[3], issue_slots[10].out_uop.iq_type[3] connect issue_slots[9].in_uop.bits.debug_pc, issue_slots[10].out_uop.debug_pc connect issue_slots[9].in_uop.bits.is_rvc, issue_slots[10].out_uop.is_rvc connect issue_slots[9].in_uop.bits.debug_inst, issue_slots[10].out_uop.debug_inst connect issue_slots[9].in_uop.bits.inst, issue_slots[10].out_uop.inst node _T_304 = eq(shamts_oh[10], UInt<1>(0h1)) when _T_304 : connect issue_slots[9].in_uop.valid, issue_slots[10].will_be_valid connect issue_slots[9].in_uop.bits.debug_tsrc, issue_slots[10].out_uop.debug_tsrc connect issue_slots[9].in_uop.bits.debug_fsrc, issue_slots[10].out_uop.debug_fsrc connect issue_slots[9].in_uop.bits.bp_xcpt_if, issue_slots[10].out_uop.bp_xcpt_if connect issue_slots[9].in_uop.bits.bp_debug_if, issue_slots[10].out_uop.bp_debug_if connect issue_slots[9].in_uop.bits.xcpt_ma_if, issue_slots[10].out_uop.xcpt_ma_if connect issue_slots[9].in_uop.bits.xcpt_ae_if, issue_slots[10].out_uop.xcpt_ae_if connect issue_slots[9].in_uop.bits.xcpt_pf_if, issue_slots[10].out_uop.xcpt_pf_if connect issue_slots[9].in_uop.bits.fp_typ, issue_slots[10].out_uop.fp_typ connect issue_slots[9].in_uop.bits.fp_rm, issue_slots[10].out_uop.fp_rm connect issue_slots[9].in_uop.bits.fp_val, issue_slots[10].out_uop.fp_val connect issue_slots[9].in_uop.bits.fcn_op, issue_slots[10].out_uop.fcn_op connect issue_slots[9].in_uop.bits.fcn_dw, issue_slots[10].out_uop.fcn_dw connect issue_slots[9].in_uop.bits.frs3_en, issue_slots[10].out_uop.frs3_en connect issue_slots[9].in_uop.bits.lrs2_rtype, issue_slots[10].out_uop.lrs2_rtype connect issue_slots[9].in_uop.bits.lrs1_rtype, issue_slots[10].out_uop.lrs1_rtype connect issue_slots[9].in_uop.bits.dst_rtype, issue_slots[10].out_uop.dst_rtype connect issue_slots[9].in_uop.bits.lrs3, issue_slots[10].out_uop.lrs3 connect issue_slots[9].in_uop.bits.lrs2, issue_slots[10].out_uop.lrs2 connect issue_slots[9].in_uop.bits.lrs1, issue_slots[10].out_uop.lrs1 connect issue_slots[9].in_uop.bits.ldst, issue_slots[10].out_uop.ldst connect issue_slots[9].in_uop.bits.ldst_is_rs1, issue_slots[10].out_uop.ldst_is_rs1 connect issue_slots[9].in_uop.bits.csr_cmd, issue_slots[10].out_uop.csr_cmd connect issue_slots[9].in_uop.bits.flush_on_commit, issue_slots[10].out_uop.flush_on_commit connect issue_slots[9].in_uop.bits.is_unique, issue_slots[10].out_uop.is_unique connect issue_slots[9].in_uop.bits.uses_stq, issue_slots[10].out_uop.uses_stq connect issue_slots[9].in_uop.bits.uses_ldq, issue_slots[10].out_uop.uses_ldq connect issue_slots[9].in_uop.bits.mem_signed, issue_slots[10].out_uop.mem_signed connect issue_slots[9].in_uop.bits.mem_size, issue_slots[10].out_uop.mem_size connect issue_slots[9].in_uop.bits.mem_cmd, issue_slots[10].out_uop.mem_cmd connect issue_slots[9].in_uop.bits.exc_cause, issue_slots[10].out_uop.exc_cause connect issue_slots[9].in_uop.bits.exception, issue_slots[10].out_uop.exception connect issue_slots[9].in_uop.bits.stale_pdst, issue_slots[10].out_uop.stale_pdst connect issue_slots[9].in_uop.bits.ppred_busy, issue_slots[10].out_uop.ppred_busy connect issue_slots[9].in_uop.bits.prs3_busy, issue_slots[10].out_uop.prs3_busy connect issue_slots[9].in_uop.bits.prs2_busy, issue_slots[10].out_uop.prs2_busy connect issue_slots[9].in_uop.bits.prs1_busy, issue_slots[10].out_uop.prs1_busy connect issue_slots[9].in_uop.bits.ppred, issue_slots[10].out_uop.ppred connect issue_slots[9].in_uop.bits.prs3, issue_slots[10].out_uop.prs3 connect issue_slots[9].in_uop.bits.prs2, issue_slots[10].out_uop.prs2 connect issue_slots[9].in_uop.bits.prs1, issue_slots[10].out_uop.prs1 connect issue_slots[9].in_uop.bits.pdst, issue_slots[10].out_uop.pdst connect issue_slots[9].in_uop.bits.rxq_idx, issue_slots[10].out_uop.rxq_idx connect issue_slots[9].in_uop.bits.stq_idx, issue_slots[10].out_uop.stq_idx connect issue_slots[9].in_uop.bits.ldq_idx, issue_slots[10].out_uop.ldq_idx connect issue_slots[9].in_uop.bits.rob_idx, issue_slots[10].out_uop.rob_idx connect issue_slots[9].in_uop.bits.fp_ctrl.vec, issue_slots[10].out_uop.fp_ctrl.vec connect issue_slots[9].in_uop.bits.fp_ctrl.wflags, issue_slots[10].out_uop.fp_ctrl.wflags connect issue_slots[9].in_uop.bits.fp_ctrl.sqrt, issue_slots[10].out_uop.fp_ctrl.sqrt connect issue_slots[9].in_uop.bits.fp_ctrl.div, issue_slots[10].out_uop.fp_ctrl.div connect issue_slots[9].in_uop.bits.fp_ctrl.fma, issue_slots[10].out_uop.fp_ctrl.fma connect issue_slots[9].in_uop.bits.fp_ctrl.fastpipe, issue_slots[10].out_uop.fp_ctrl.fastpipe connect issue_slots[9].in_uop.bits.fp_ctrl.toint, issue_slots[10].out_uop.fp_ctrl.toint connect issue_slots[9].in_uop.bits.fp_ctrl.fromint, issue_slots[10].out_uop.fp_ctrl.fromint connect issue_slots[9].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[10].out_uop.fp_ctrl.typeTagOut connect issue_slots[9].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[10].out_uop.fp_ctrl.typeTagIn connect issue_slots[9].in_uop.bits.fp_ctrl.swap23, issue_slots[10].out_uop.fp_ctrl.swap23 connect issue_slots[9].in_uop.bits.fp_ctrl.swap12, issue_slots[10].out_uop.fp_ctrl.swap12 connect issue_slots[9].in_uop.bits.fp_ctrl.ren3, issue_slots[10].out_uop.fp_ctrl.ren3 connect issue_slots[9].in_uop.bits.fp_ctrl.ren2, issue_slots[10].out_uop.fp_ctrl.ren2 connect issue_slots[9].in_uop.bits.fp_ctrl.ren1, issue_slots[10].out_uop.fp_ctrl.ren1 connect issue_slots[9].in_uop.bits.fp_ctrl.wen, issue_slots[10].out_uop.fp_ctrl.wen connect issue_slots[9].in_uop.bits.fp_ctrl.ldst, issue_slots[10].out_uop.fp_ctrl.ldst connect issue_slots[9].in_uop.bits.op2_sel, issue_slots[10].out_uop.op2_sel connect issue_slots[9].in_uop.bits.op1_sel, issue_slots[10].out_uop.op1_sel connect issue_slots[9].in_uop.bits.imm_packed, issue_slots[10].out_uop.imm_packed connect issue_slots[9].in_uop.bits.pimm, issue_slots[10].out_uop.pimm connect issue_slots[9].in_uop.bits.imm_sel, issue_slots[10].out_uop.imm_sel connect issue_slots[9].in_uop.bits.imm_rename, issue_slots[10].out_uop.imm_rename connect issue_slots[9].in_uop.bits.taken, issue_slots[10].out_uop.taken connect issue_slots[9].in_uop.bits.pc_lob, issue_slots[10].out_uop.pc_lob connect issue_slots[9].in_uop.bits.edge_inst, issue_slots[10].out_uop.edge_inst connect issue_slots[9].in_uop.bits.ftq_idx, issue_slots[10].out_uop.ftq_idx connect issue_slots[9].in_uop.bits.is_mov, issue_slots[10].out_uop.is_mov connect issue_slots[9].in_uop.bits.is_rocc, issue_slots[10].out_uop.is_rocc connect issue_slots[9].in_uop.bits.is_sys_pc2epc, issue_slots[10].out_uop.is_sys_pc2epc connect issue_slots[9].in_uop.bits.is_eret, issue_slots[10].out_uop.is_eret connect issue_slots[9].in_uop.bits.is_amo, issue_slots[10].out_uop.is_amo connect issue_slots[9].in_uop.bits.is_sfence, issue_slots[10].out_uop.is_sfence connect issue_slots[9].in_uop.bits.is_fencei, issue_slots[10].out_uop.is_fencei connect issue_slots[9].in_uop.bits.is_fence, issue_slots[10].out_uop.is_fence connect issue_slots[9].in_uop.bits.is_sfb, issue_slots[10].out_uop.is_sfb connect issue_slots[9].in_uop.bits.br_type, issue_slots[10].out_uop.br_type connect issue_slots[9].in_uop.bits.br_tag, issue_slots[10].out_uop.br_tag connect issue_slots[9].in_uop.bits.br_mask, issue_slots[10].out_uop.br_mask connect issue_slots[9].in_uop.bits.dis_col_sel, issue_slots[10].out_uop.dis_col_sel connect issue_slots[9].in_uop.bits.iw_p3_bypass_hint, issue_slots[10].out_uop.iw_p3_bypass_hint connect issue_slots[9].in_uop.bits.iw_p2_bypass_hint, issue_slots[10].out_uop.iw_p2_bypass_hint connect issue_slots[9].in_uop.bits.iw_p1_bypass_hint, issue_slots[10].out_uop.iw_p1_bypass_hint connect issue_slots[9].in_uop.bits.iw_p2_speculative_child, issue_slots[10].out_uop.iw_p2_speculative_child connect issue_slots[9].in_uop.bits.iw_p1_speculative_child, issue_slots[10].out_uop.iw_p1_speculative_child connect issue_slots[9].in_uop.bits.iw_issued_partial_dgen, issue_slots[10].out_uop.iw_issued_partial_dgen connect issue_slots[9].in_uop.bits.iw_issued_partial_agen, issue_slots[10].out_uop.iw_issued_partial_agen connect issue_slots[9].in_uop.bits.iw_issued, issue_slots[10].out_uop.iw_issued connect issue_slots[9].in_uop.bits.fu_code[0], issue_slots[10].out_uop.fu_code[0] connect issue_slots[9].in_uop.bits.fu_code[1], issue_slots[10].out_uop.fu_code[1] connect issue_slots[9].in_uop.bits.fu_code[2], issue_slots[10].out_uop.fu_code[2] connect issue_slots[9].in_uop.bits.fu_code[3], issue_slots[10].out_uop.fu_code[3] connect issue_slots[9].in_uop.bits.fu_code[4], issue_slots[10].out_uop.fu_code[4] connect issue_slots[9].in_uop.bits.fu_code[5], issue_slots[10].out_uop.fu_code[5] connect issue_slots[9].in_uop.bits.fu_code[6], issue_slots[10].out_uop.fu_code[6] connect issue_slots[9].in_uop.bits.fu_code[7], issue_slots[10].out_uop.fu_code[7] connect issue_slots[9].in_uop.bits.fu_code[8], issue_slots[10].out_uop.fu_code[8] connect issue_slots[9].in_uop.bits.fu_code[9], issue_slots[10].out_uop.fu_code[9] connect issue_slots[9].in_uop.bits.iq_type[0], issue_slots[10].out_uop.iq_type[0] connect issue_slots[9].in_uop.bits.iq_type[1], issue_slots[10].out_uop.iq_type[1] connect issue_slots[9].in_uop.bits.iq_type[2], issue_slots[10].out_uop.iq_type[2] connect issue_slots[9].in_uop.bits.iq_type[3], issue_slots[10].out_uop.iq_type[3] connect issue_slots[9].in_uop.bits.debug_pc, issue_slots[10].out_uop.debug_pc connect issue_slots[9].in_uop.bits.is_rvc, issue_slots[10].out_uop.is_rvc connect issue_slots[9].in_uop.bits.debug_inst, issue_slots[10].out_uop.debug_inst connect issue_slots[9].in_uop.bits.inst, issue_slots[10].out_uop.inst node _T_305 = eq(shamts_oh[11], UInt<2>(0h2)) when _T_305 : connect issue_slots[9].in_uop.valid, issue_slots[11].will_be_valid connect issue_slots[9].in_uop.bits.debug_tsrc, issue_slots[11].out_uop.debug_tsrc connect issue_slots[9].in_uop.bits.debug_fsrc, issue_slots[11].out_uop.debug_fsrc connect issue_slots[9].in_uop.bits.bp_xcpt_if, issue_slots[11].out_uop.bp_xcpt_if connect issue_slots[9].in_uop.bits.bp_debug_if, issue_slots[11].out_uop.bp_debug_if connect issue_slots[9].in_uop.bits.xcpt_ma_if, issue_slots[11].out_uop.xcpt_ma_if connect issue_slots[9].in_uop.bits.xcpt_ae_if, issue_slots[11].out_uop.xcpt_ae_if connect issue_slots[9].in_uop.bits.xcpt_pf_if, issue_slots[11].out_uop.xcpt_pf_if connect issue_slots[9].in_uop.bits.fp_typ, issue_slots[11].out_uop.fp_typ connect issue_slots[9].in_uop.bits.fp_rm, issue_slots[11].out_uop.fp_rm connect issue_slots[9].in_uop.bits.fp_val, issue_slots[11].out_uop.fp_val connect issue_slots[9].in_uop.bits.fcn_op, issue_slots[11].out_uop.fcn_op connect issue_slots[9].in_uop.bits.fcn_dw, issue_slots[11].out_uop.fcn_dw connect issue_slots[9].in_uop.bits.frs3_en, issue_slots[11].out_uop.frs3_en connect issue_slots[9].in_uop.bits.lrs2_rtype, issue_slots[11].out_uop.lrs2_rtype connect issue_slots[9].in_uop.bits.lrs1_rtype, issue_slots[11].out_uop.lrs1_rtype connect issue_slots[9].in_uop.bits.dst_rtype, issue_slots[11].out_uop.dst_rtype connect issue_slots[9].in_uop.bits.lrs3, issue_slots[11].out_uop.lrs3 connect issue_slots[9].in_uop.bits.lrs2, issue_slots[11].out_uop.lrs2 connect issue_slots[9].in_uop.bits.lrs1, issue_slots[11].out_uop.lrs1 connect issue_slots[9].in_uop.bits.ldst, issue_slots[11].out_uop.ldst connect issue_slots[9].in_uop.bits.ldst_is_rs1, issue_slots[11].out_uop.ldst_is_rs1 connect issue_slots[9].in_uop.bits.csr_cmd, issue_slots[11].out_uop.csr_cmd connect issue_slots[9].in_uop.bits.flush_on_commit, issue_slots[11].out_uop.flush_on_commit connect issue_slots[9].in_uop.bits.is_unique, issue_slots[11].out_uop.is_unique connect issue_slots[9].in_uop.bits.uses_stq, issue_slots[11].out_uop.uses_stq connect issue_slots[9].in_uop.bits.uses_ldq, issue_slots[11].out_uop.uses_ldq connect issue_slots[9].in_uop.bits.mem_signed, issue_slots[11].out_uop.mem_signed connect issue_slots[9].in_uop.bits.mem_size, issue_slots[11].out_uop.mem_size connect issue_slots[9].in_uop.bits.mem_cmd, issue_slots[11].out_uop.mem_cmd connect issue_slots[9].in_uop.bits.exc_cause, issue_slots[11].out_uop.exc_cause connect issue_slots[9].in_uop.bits.exception, issue_slots[11].out_uop.exception connect issue_slots[9].in_uop.bits.stale_pdst, issue_slots[11].out_uop.stale_pdst connect issue_slots[9].in_uop.bits.ppred_busy, issue_slots[11].out_uop.ppred_busy connect issue_slots[9].in_uop.bits.prs3_busy, issue_slots[11].out_uop.prs3_busy connect issue_slots[9].in_uop.bits.prs2_busy, issue_slots[11].out_uop.prs2_busy connect issue_slots[9].in_uop.bits.prs1_busy, issue_slots[11].out_uop.prs1_busy connect issue_slots[9].in_uop.bits.ppred, issue_slots[11].out_uop.ppred connect issue_slots[9].in_uop.bits.prs3, issue_slots[11].out_uop.prs3 connect issue_slots[9].in_uop.bits.prs2, issue_slots[11].out_uop.prs2 connect issue_slots[9].in_uop.bits.prs1, issue_slots[11].out_uop.prs1 connect issue_slots[9].in_uop.bits.pdst, issue_slots[11].out_uop.pdst connect issue_slots[9].in_uop.bits.rxq_idx, issue_slots[11].out_uop.rxq_idx connect issue_slots[9].in_uop.bits.stq_idx, issue_slots[11].out_uop.stq_idx connect issue_slots[9].in_uop.bits.ldq_idx, issue_slots[11].out_uop.ldq_idx connect issue_slots[9].in_uop.bits.rob_idx, issue_slots[11].out_uop.rob_idx connect issue_slots[9].in_uop.bits.fp_ctrl.vec, issue_slots[11].out_uop.fp_ctrl.vec connect issue_slots[9].in_uop.bits.fp_ctrl.wflags, issue_slots[11].out_uop.fp_ctrl.wflags connect issue_slots[9].in_uop.bits.fp_ctrl.sqrt, issue_slots[11].out_uop.fp_ctrl.sqrt connect issue_slots[9].in_uop.bits.fp_ctrl.div, issue_slots[11].out_uop.fp_ctrl.div connect issue_slots[9].in_uop.bits.fp_ctrl.fma, issue_slots[11].out_uop.fp_ctrl.fma connect issue_slots[9].in_uop.bits.fp_ctrl.fastpipe, issue_slots[11].out_uop.fp_ctrl.fastpipe connect issue_slots[9].in_uop.bits.fp_ctrl.toint, issue_slots[11].out_uop.fp_ctrl.toint connect issue_slots[9].in_uop.bits.fp_ctrl.fromint, issue_slots[11].out_uop.fp_ctrl.fromint connect issue_slots[9].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[11].out_uop.fp_ctrl.typeTagOut connect issue_slots[9].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[11].out_uop.fp_ctrl.typeTagIn connect issue_slots[9].in_uop.bits.fp_ctrl.swap23, issue_slots[11].out_uop.fp_ctrl.swap23 connect issue_slots[9].in_uop.bits.fp_ctrl.swap12, issue_slots[11].out_uop.fp_ctrl.swap12 connect issue_slots[9].in_uop.bits.fp_ctrl.ren3, issue_slots[11].out_uop.fp_ctrl.ren3 connect issue_slots[9].in_uop.bits.fp_ctrl.ren2, issue_slots[11].out_uop.fp_ctrl.ren2 connect issue_slots[9].in_uop.bits.fp_ctrl.ren1, issue_slots[11].out_uop.fp_ctrl.ren1 connect issue_slots[9].in_uop.bits.fp_ctrl.wen, issue_slots[11].out_uop.fp_ctrl.wen connect issue_slots[9].in_uop.bits.fp_ctrl.ldst, issue_slots[11].out_uop.fp_ctrl.ldst connect issue_slots[9].in_uop.bits.op2_sel, issue_slots[11].out_uop.op2_sel connect issue_slots[9].in_uop.bits.op1_sel, issue_slots[11].out_uop.op1_sel connect issue_slots[9].in_uop.bits.imm_packed, issue_slots[11].out_uop.imm_packed connect issue_slots[9].in_uop.bits.pimm, issue_slots[11].out_uop.pimm connect issue_slots[9].in_uop.bits.imm_sel, issue_slots[11].out_uop.imm_sel connect issue_slots[9].in_uop.bits.imm_rename, issue_slots[11].out_uop.imm_rename connect issue_slots[9].in_uop.bits.taken, issue_slots[11].out_uop.taken connect issue_slots[9].in_uop.bits.pc_lob, issue_slots[11].out_uop.pc_lob connect issue_slots[9].in_uop.bits.edge_inst, issue_slots[11].out_uop.edge_inst connect issue_slots[9].in_uop.bits.ftq_idx, issue_slots[11].out_uop.ftq_idx connect issue_slots[9].in_uop.bits.is_mov, issue_slots[11].out_uop.is_mov connect issue_slots[9].in_uop.bits.is_rocc, issue_slots[11].out_uop.is_rocc connect issue_slots[9].in_uop.bits.is_sys_pc2epc, issue_slots[11].out_uop.is_sys_pc2epc connect issue_slots[9].in_uop.bits.is_eret, issue_slots[11].out_uop.is_eret connect issue_slots[9].in_uop.bits.is_amo, issue_slots[11].out_uop.is_amo connect issue_slots[9].in_uop.bits.is_sfence, issue_slots[11].out_uop.is_sfence connect issue_slots[9].in_uop.bits.is_fencei, issue_slots[11].out_uop.is_fencei connect issue_slots[9].in_uop.bits.is_fence, issue_slots[11].out_uop.is_fence connect issue_slots[9].in_uop.bits.is_sfb, issue_slots[11].out_uop.is_sfb connect issue_slots[9].in_uop.bits.br_type, issue_slots[11].out_uop.br_type connect issue_slots[9].in_uop.bits.br_tag, issue_slots[11].out_uop.br_tag connect issue_slots[9].in_uop.bits.br_mask, issue_slots[11].out_uop.br_mask connect issue_slots[9].in_uop.bits.dis_col_sel, issue_slots[11].out_uop.dis_col_sel connect issue_slots[9].in_uop.bits.iw_p3_bypass_hint, issue_slots[11].out_uop.iw_p3_bypass_hint connect issue_slots[9].in_uop.bits.iw_p2_bypass_hint, issue_slots[11].out_uop.iw_p2_bypass_hint connect issue_slots[9].in_uop.bits.iw_p1_bypass_hint, issue_slots[11].out_uop.iw_p1_bypass_hint connect issue_slots[9].in_uop.bits.iw_p2_speculative_child, issue_slots[11].out_uop.iw_p2_speculative_child connect issue_slots[9].in_uop.bits.iw_p1_speculative_child, issue_slots[11].out_uop.iw_p1_speculative_child connect issue_slots[9].in_uop.bits.iw_issued_partial_dgen, issue_slots[11].out_uop.iw_issued_partial_dgen connect issue_slots[9].in_uop.bits.iw_issued_partial_agen, issue_slots[11].out_uop.iw_issued_partial_agen connect issue_slots[9].in_uop.bits.iw_issued, issue_slots[11].out_uop.iw_issued connect issue_slots[9].in_uop.bits.fu_code[0], issue_slots[11].out_uop.fu_code[0] connect issue_slots[9].in_uop.bits.fu_code[1], issue_slots[11].out_uop.fu_code[1] connect issue_slots[9].in_uop.bits.fu_code[2], issue_slots[11].out_uop.fu_code[2] connect issue_slots[9].in_uop.bits.fu_code[3], issue_slots[11].out_uop.fu_code[3] connect issue_slots[9].in_uop.bits.fu_code[4], issue_slots[11].out_uop.fu_code[4] connect issue_slots[9].in_uop.bits.fu_code[5], issue_slots[11].out_uop.fu_code[5] connect issue_slots[9].in_uop.bits.fu_code[6], issue_slots[11].out_uop.fu_code[6] connect issue_slots[9].in_uop.bits.fu_code[7], issue_slots[11].out_uop.fu_code[7] connect issue_slots[9].in_uop.bits.fu_code[8], issue_slots[11].out_uop.fu_code[8] connect issue_slots[9].in_uop.bits.fu_code[9], issue_slots[11].out_uop.fu_code[9] connect issue_slots[9].in_uop.bits.iq_type[0], issue_slots[11].out_uop.iq_type[0] connect issue_slots[9].in_uop.bits.iq_type[1], issue_slots[11].out_uop.iq_type[1] connect issue_slots[9].in_uop.bits.iq_type[2], issue_slots[11].out_uop.iq_type[2] connect issue_slots[9].in_uop.bits.iq_type[3], issue_slots[11].out_uop.iq_type[3] connect issue_slots[9].in_uop.bits.debug_pc, issue_slots[11].out_uop.debug_pc connect issue_slots[9].in_uop.bits.is_rvc, issue_slots[11].out_uop.is_rvc connect issue_slots[9].in_uop.bits.debug_inst, issue_slots[11].out_uop.debug_inst connect issue_slots[9].in_uop.bits.inst, issue_slots[11].out_uop.inst node _T_306 = eq(shamts_oh[12], UInt<3>(0h4)) when _T_306 : connect issue_slots[9].in_uop.valid, issue_slots[12].will_be_valid connect issue_slots[9].in_uop.bits.debug_tsrc, issue_slots[12].out_uop.debug_tsrc connect issue_slots[9].in_uop.bits.debug_fsrc, issue_slots[12].out_uop.debug_fsrc connect issue_slots[9].in_uop.bits.bp_xcpt_if, issue_slots[12].out_uop.bp_xcpt_if connect issue_slots[9].in_uop.bits.bp_debug_if, issue_slots[12].out_uop.bp_debug_if connect issue_slots[9].in_uop.bits.xcpt_ma_if, issue_slots[12].out_uop.xcpt_ma_if connect issue_slots[9].in_uop.bits.xcpt_ae_if, issue_slots[12].out_uop.xcpt_ae_if connect issue_slots[9].in_uop.bits.xcpt_pf_if, issue_slots[12].out_uop.xcpt_pf_if connect issue_slots[9].in_uop.bits.fp_typ, issue_slots[12].out_uop.fp_typ connect issue_slots[9].in_uop.bits.fp_rm, issue_slots[12].out_uop.fp_rm connect issue_slots[9].in_uop.bits.fp_val, issue_slots[12].out_uop.fp_val connect issue_slots[9].in_uop.bits.fcn_op, issue_slots[12].out_uop.fcn_op connect issue_slots[9].in_uop.bits.fcn_dw, issue_slots[12].out_uop.fcn_dw connect issue_slots[9].in_uop.bits.frs3_en, issue_slots[12].out_uop.frs3_en connect issue_slots[9].in_uop.bits.lrs2_rtype, issue_slots[12].out_uop.lrs2_rtype connect issue_slots[9].in_uop.bits.lrs1_rtype, issue_slots[12].out_uop.lrs1_rtype connect issue_slots[9].in_uop.bits.dst_rtype, issue_slots[12].out_uop.dst_rtype connect issue_slots[9].in_uop.bits.lrs3, issue_slots[12].out_uop.lrs3 connect issue_slots[9].in_uop.bits.lrs2, issue_slots[12].out_uop.lrs2 connect issue_slots[9].in_uop.bits.lrs1, issue_slots[12].out_uop.lrs1 connect issue_slots[9].in_uop.bits.ldst, issue_slots[12].out_uop.ldst connect issue_slots[9].in_uop.bits.ldst_is_rs1, issue_slots[12].out_uop.ldst_is_rs1 connect issue_slots[9].in_uop.bits.csr_cmd, issue_slots[12].out_uop.csr_cmd connect issue_slots[9].in_uop.bits.flush_on_commit, issue_slots[12].out_uop.flush_on_commit connect issue_slots[9].in_uop.bits.is_unique, issue_slots[12].out_uop.is_unique connect issue_slots[9].in_uop.bits.uses_stq, issue_slots[12].out_uop.uses_stq connect issue_slots[9].in_uop.bits.uses_ldq, issue_slots[12].out_uop.uses_ldq connect issue_slots[9].in_uop.bits.mem_signed, issue_slots[12].out_uop.mem_signed connect issue_slots[9].in_uop.bits.mem_size, issue_slots[12].out_uop.mem_size connect issue_slots[9].in_uop.bits.mem_cmd, issue_slots[12].out_uop.mem_cmd connect issue_slots[9].in_uop.bits.exc_cause, issue_slots[12].out_uop.exc_cause connect issue_slots[9].in_uop.bits.exception, issue_slots[12].out_uop.exception connect issue_slots[9].in_uop.bits.stale_pdst, issue_slots[12].out_uop.stale_pdst connect issue_slots[9].in_uop.bits.ppred_busy, issue_slots[12].out_uop.ppred_busy connect issue_slots[9].in_uop.bits.prs3_busy, issue_slots[12].out_uop.prs3_busy connect issue_slots[9].in_uop.bits.prs2_busy, issue_slots[12].out_uop.prs2_busy connect issue_slots[9].in_uop.bits.prs1_busy, issue_slots[12].out_uop.prs1_busy connect issue_slots[9].in_uop.bits.ppred, issue_slots[12].out_uop.ppred connect issue_slots[9].in_uop.bits.prs3, issue_slots[12].out_uop.prs3 connect issue_slots[9].in_uop.bits.prs2, issue_slots[12].out_uop.prs2 connect issue_slots[9].in_uop.bits.prs1, issue_slots[12].out_uop.prs1 connect issue_slots[9].in_uop.bits.pdst, issue_slots[12].out_uop.pdst connect issue_slots[9].in_uop.bits.rxq_idx, issue_slots[12].out_uop.rxq_idx connect issue_slots[9].in_uop.bits.stq_idx, issue_slots[12].out_uop.stq_idx connect issue_slots[9].in_uop.bits.ldq_idx, issue_slots[12].out_uop.ldq_idx connect issue_slots[9].in_uop.bits.rob_idx, issue_slots[12].out_uop.rob_idx connect issue_slots[9].in_uop.bits.fp_ctrl.vec, issue_slots[12].out_uop.fp_ctrl.vec connect issue_slots[9].in_uop.bits.fp_ctrl.wflags, issue_slots[12].out_uop.fp_ctrl.wflags connect issue_slots[9].in_uop.bits.fp_ctrl.sqrt, issue_slots[12].out_uop.fp_ctrl.sqrt connect issue_slots[9].in_uop.bits.fp_ctrl.div, issue_slots[12].out_uop.fp_ctrl.div connect issue_slots[9].in_uop.bits.fp_ctrl.fma, issue_slots[12].out_uop.fp_ctrl.fma connect issue_slots[9].in_uop.bits.fp_ctrl.fastpipe, issue_slots[12].out_uop.fp_ctrl.fastpipe connect issue_slots[9].in_uop.bits.fp_ctrl.toint, issue_slots[12].out_uop.fp_ctrl.toint connect issue_slots[9].in_uop.bits.fp_ctrl.fromint, issue_slots[12].out_uop.fp_ctrl.fromint connect issue_slots[9].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[12].out_uop.fp_ctrl.typeTagOut connect issue_slots[9].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[12].out_uop.fp_ctrl.typeTagIn connect issue_slots[9].in_uop.bits.fp_ctrl.swap23, issue_slots[12].out_uop.fp_ctrl.swap23 connect issue_slots[9].in_uop.bits.fp_ctrl.swap12, issue_slots[12].out_uop.fp_ctrl.swap12 connect issue_slots[9].in_uop.bits.fp_ctrl.ren3, issue_slots[12].out_uop.fp_ctrl.ren3 connect issue_slots[9].in_uop.bits.fp_ctrl.ren2, issue_slots[12].out_uop.fp_ctrl.ren2 connect issue_slots[9].in_uop.bits.fp_ctrl.ren1, issue_slots[12].out_uop.fp_ctrl.ren1 connect issue_slots[9].in_uop.bits.fp_ctrl.wen, issue_slots[12].out_uop.fp_ctrl.wen connect issue_slots[9].in_uop.bits.fp_ctrl.ldst, issue_slots[12].out_uop.fp_ctrl.ldst connect issue_slots[9].in_uop.bits.op2_sel, issue_slots[12].out_uop.op2_sel connect issue_slots[9].in_uop.bits.op1_sel, issue_slots[12].out_uop.op1_sel connect issue_slots[9].in_uop.bits.imm_packed, issue_slots[12].out_uop.imm_packed connect issue_slots[9].in_uop.bits.pimm, issue_slots[12].out_uop.pimm connect issue_slots[9].in_uop.bits.imm_sel, issue_slots[12].out_uop.imm_sel connect issue_slots[9].in_uop.bits.imm_rename, issue_slots[12].out_uop.imm_rename connect issue_slots[9].in_uop.bits.taken, issue_slots[12].out_uop.taken connect issue_slots[9].in_uop.bits.pc_lob, issue_slots[12].out_uop.pc_lob connect issue_slots[9].in_uop.bits.edge_inst, issue_slots[12].out_uop.edge_inst connect issue_slots[9].in_uop.bits.ftq_idx, issue_slots[12].out_uop.ftq_idx connect issue_slots[9].in_uop.bits.is_mov, issue_slots[12].out_uop.is_mov connect issue_slots[9].in_uop.bits.is_rocc, issue_slots[12].out_uop.is_rocc connect issue_slots[9].in_uop.bits.is_sys_pc2epc, issue_slots[12].out_uop.is_sys_pc2epc connect issue_slots[9].in_uop.bits.is_eret, issue_slots[12].out_uop.is_eret connect issue_slots[9].in_uop.bits.is_amo, issue_slots[12].out_uop.is_amo connect issue_slots[9].in_uop.bits.is_sfence, issue_slots[12].out_uop.is_sfence connect issue_slots[9].in_uop.bits.is_fencei, issue_slots[12].out_uop.is_fencei connect issue_slots[9].in_uop.bits.is_fence, issue_slots[12].out_uop.is_fence connect issue_slots[9].in_uop.bits.is_sfb, issue_slots[12].out_uop.is_sfb connect issue_slots[9].in_uop.bits.br_type, issue_slots[12].out_uop.br_type connect issue_slots[9].in_uop.bits.br_tag, issue_slots[12].out_uop.br_tag connect issue_slots[9].in_uop.bits.br_mask, issue_slots[12].out_uop.br_mask connect issue_slots[9].in_uop.bits.dis_col_sel, issue_slots[12].out_uop.dis_col_sel connect issue_slots[9].in_uop.bits.iw_p3_bypass_hint, issue_slots[12].out_uop.iw_p3_bypass_hint connect issue_slots[9].in_uop.bits.iw_p2_bypass_hint, issue_slots[12].out_uop.iw_p2_bypass_hint connect issue_slots[9].in_uop.bits.iw_p1_bypass_hint, issue_slots[12].out_uop.iw_p1_bypass_hint connect issue_slots[9].in_uop.bits.iw_p2_speculative_child, issue_slots[12].out_uop.iw_p2_speculative_child connect issue_slots[9].in_uop.bits.iw_p1_speculative_child, issue_slots[12].out_uop.iw_p1_speculative_child connect issue_slots[9].in_uop.bits.iw_issued_partial_dgen, issue_slots[12].out_uop.iw_issued_partial_dgen connect issue_slots[9].in_uop.bits.iw_issued_partial_agen, issue_slots[12].out_uop.iw_issued_partial_agen connect issue_slots[9].in_uop.bits.iw_issued, issue_slots[12].out_uop.iw_issued connect issue_slots[9].in_uop.bits.fu_code[0], issue_slots[12].out_uop.fu_code[0] connect issue_slots[9].in_uop.bits.fu_code[1], issue_slots[12].out_uop.fu_code[1] connect issue_slots[9].in_uop.bits.fu_code[2], issue_slots[12].out_uop.fu_code[2] connect issue_slots[9].in_uop.bits.fu_code[3], issue_slots[12].out_uop.fu_code[3] connect issue_slots[9].in_uop.bits.fu_code[4], issue_slots[12].out_uop.fu_code[4] connect issue_slots[9].in_uop.bits.fu_code[5], issue_slots[12].out_uop.fu_code[5] connect issue_slots[9].in_uop.bits.fu_code[6], issue_slots[12].out_uop.fu_code[6] connect issue_slots[9].in_uop.bits.fu_code[7], issue_slots[12].out_uop.fu_code[7] connect issue_slots[9].in_uop.bits.fu_code[8], issue_slots[12].out_uop.fu_code[8] connect issue_slots[9].in_uop.bits.fu_code[9], issue_slots[12].out_uop.fu_code[9] connect issue_slots[9].in_uop.bits.iq_type[0], issue_slots[12].out_uop.iq_type[0] connect issue_slots[9].in_uop.bits.iq_type[1], issue_slots[12].out_uop.iq_type[1] connect issue_slots[9].in_uop.bits.iq_type[2], issue_slots[12].out_uop.iq_type[2] connect issue_slots[9].in_uop.bits.iq_type[3], issue_slots[12].out_uop.iq_type[3] connect issue_slots[9].in_uop.bits.debug_pc, issue_slots[12].out_uop.debug_pc connect issue_slots[9].in_uop.bits.is_rvc, issue_slots[12].out_uop.is_rvc connect issue_slots[9].in_uop.bits.debug_inst, issue_slots[12].out_uop.debug_inst connect issue_slots[9].in_uop.bits.inst, issue_slots[12].out_uop.inst node _issue_slots_9_clear_T = neq(shamts_oh[9], UInt<1>(0h0)) connect issue_slots[9].clear, _issue_slots_9_clear_T connect issue_slots[10].in_uop.valid, UInt<1>(0h0) connect issue_slots[10].in_uop.bits.debug_tsrc, issue_slots[11].out_uop.debug_tsrc connect issue_slots[10].in_uop.bits.debug_fsrc, issue_slots[11].out_uop.debug_fsrc connect issue_slots[10].in_uop.bits.bp_xcpt_if, issue_slots[11].out_uop.bp_xcpt_if connect issue_slots[10].in_uop.bits.bp_debug_if, issue_slots[11].out_uop.bp_debug_if connect issue_slots[10].in_uop.bits.xcpt_ma_if, issue_slots[11].out_uop.xcpt_ma_if connect issue_slots[10].in_uop.bits.xcpt_ae_if, issue_slots[11].out_uop.xcpt_ae_if connect issue_slots[10].in_uop.bits.xcpt_pf_if, issue_slots[11].out_uop.xcpt_pf_if connect issue_slots[10].in_uop.bits.fp_typ, issue_slots[11].out_uop.fp_typ connect issue_slots[10].in_uop.bits.fp_rm, issue_slots[11].out_uop.fp_rm connect issue_slots[10].in_uop.bits.fp_val, issue_slots[11].out_uop.fp_val connect issue_slots[10].in_uop.bits.fcn_op, issue_slots[11].out_uop.fcn_op connect issue_slots[10].in_uop.bits.fcn_dw, issue_slots[11].out_uop.fcn_dw connect issue_slots[10].in_uop.bits.frs3_en, issue_slots[11].out_uop.frs3_en connect issue_slots[10].in_uop.bits.lrs2_rtype, issue_slots[11].out_uop.lrs2_rtype connect issue_slots[10].in_uop.bits.lrs1_rtype, issue_slots[11].out_uop.lrs1_rtype connect issue_slots[10].in_uop.bits.dst_rtype, issue_slots[11].out_uop.dst_rtype connect issue_slots[10].in_uop.bits.lrs3, issue_slots[11].out_uop.lrs3 connect issue_slots[10].in_uop.bits.lrs2, issue_slots[11].out_uop.lrs2 connect issue_slots[10].in_uop.bits.lrs1, issue_slots[11].out_uop.lrs1 connect issue_slots[10].in_uop.bits.ldst, issue_slots[11].out_uop.ldst connect issue_slots[10].in_uop.bits.ldst_is_rs1, issue_slots[11].out_uop.ldst_is_rs1 connect issue_slots[10].in_uop.bits.csr_cmd, issue_slots[11].out_uop.csr_cmd connect issue_slots[10].in_uop.bits.flush_on_commit, issue_slots[11].out_uop.flush_on_commit connect issue_slots[10].in_uop.bits.is_unique, issue_slots[11].out_uop.is_unique connect issue_slots[10].in_uop.bits.uses_stq, issue_slots[11].out_uop.uses_stq connect issue_slots[10].in_uop.bits.uses_ldq, issue_slots[11].out_uop.uses_ldq connect issue_slots[10].in_uop.bits.mem_signed, issue_slots[11].out_uop.mem_signed connect issue_slots[10].in_uop.bits.mem_size, issue_slots[11].out_uop.mem_size connect issue_slots[10].in_uop.bits.mem_cmd, issue_slots[11].out_uop.mem_cmd connect issue_slots[10].in_uop.bits.exc_cause, issue_slots[11].out_uop.exc_cause connect issue_slots[10].in_uop.bits.exception, issue_slots[11].out_uop.exception connect issue_slots[10].in_uop.bits.stale_pdst, issue_slots[11].out_uop.stale_pdst connect issue_slots[10].in_uop.bits.ppred_busy, issue_slots[11].out_uop.ppred_busy connect issue_slots[10].in_uop.bits.prs3_busy, issue_slots[11].out_uop.prs3_busy connect issue_slots[10].in_uop.bits.prs2_busy, issue_slots[11].out_uop.prs2_busy connect issue_slots[10].in_uop.bits.prs1_busy, issue_slots[11].out_uop.prs1_busy connect issue_slots[10].in_uop.bits.ppred, issue_slots[11].out_uop.ppred connect issue_slots[10].in_uop.bits.prs3, issue_slots[11].out_uop.prs3 connect issue_slots[10].in_uop.bits.prs2, issue_slots[11].out_uop.prs2 connect issue_slots[10].in_uop.bits.prs1, issue_slots[11].out_uop.prs1 connect issue_slots[10].in_uop.bits.pdst, issue_slots[11].out_uop.pdst connect issue_slots[10].in_uop.bits.rxq_idx, issue_slots[11].out_uop.rxq_idx connect issue_slots[10].in_uop.bits.stq_idx, issue_slots[11].out_uop.stq_idx connect issue_slots[10].in_uop.bits.ldq_idx, issue_slots[11].out_uop.ldq_idx connect issue_slots[10].in_uop.bits.rob_idx, issue_slots[11].out_uop.rob_idx connect issue_slots[10].in_uop.bits.fp_ctrl.vec, issue_slots[11].out_uop.fp_ctrl.vec connect issue_slots[10].in_uop.bits.fp_ctrl.wflags, issue_slots[11].out_uop.fp_ctrl.wflags connect issue_slots[10].in_uop.bits.fp_ctrl.sqrt, issue_slots[11].out_uop.fp_ctrl.sqrt connect issue_slots[10].in_uop.bits.fp_ctrl.div, issue_slots[11].out_uop.fp_ctrl.div connect issue_slots[10].in_uop.bits.fp_ctrl.fma, issue_slots[11].out_uop.fp_ctrl.fma connect issue_slots[10].in_uop.bits.fp_ctrl.fastpipe, issue_slots[11].out_uop.fp_ctrl.fastpipe connect issue_slots[10].in_uop.bits.fp_ctrl.toint, issue_slots[11].out_uop.fp_ctrl.toint connect issue_slots[10].in_uop.bits.fp_ctrl.fromint, issue_slots[11].out_uop.fp_ctrl.fromint connect issue_slots[10].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[11].out_uop.fp_ctrl.typeTagOut connect issue_slots[10].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[11].out_uop.fp_ctrl.typeTagIn connect issue_slots[10].in_uop.bits.fp_ctrl.swap23, issue_slots[11].out_uop.fp_ctrl.swap23 connect issue_slots[10].in_uop.bits.fp_ctrl.swap12, issue_slots[11].out_uop.fp_ctrl.swap12 connect issue_slots[10].in_uop.bits.fp_ctrl.ren3, issue_slots[11].out_uop.fp_ctrl.ren3 connect issue_slots[10].in_uop.bits.fp_ctrl.ren2, issue_slots[11].out_uop.fp_ctrl.ren2 connect issue_slots[10].in_uop.bits.fp_ctrl.ren1, issue_slots[11].out_uop.fp_ctrl.ren1 connect issue_slots[10].in_uop.bits.fp_ctrl.wen, issue_slots[11].out_uop.fp_ctrl.wen connect issue_slots[10].in_uop.bits.fp_ctrl.ldst, issue_slots[11].out_uop.fp_ctrl.ldst connect issue_slots[10].in_uop.bits.op2_sel, issue_slots[11].out_uop.op2_sel connect issue_slots[10].in_uop.bits.op1_sel, issue_slots[11].out_uop.op1_sel connect issue_slots[10].in_uop.bits.imm_packed, issue_slots[11].out_uop.imm_packed connect issue_slots[10].in_uop.bits.pimm, issue_slots[11].out_uop.pimm connect issue_slots[10].in_uop.bits.imm_sel, issue_slots[11].out_uop.imm_sel connect issue_slots[10].in_uop.bits.imm_rename, issue_slots[11].out_uop.imm_rename connect issue_slots[10].in_uop.bits.taken, issue_slots[11].out_uop.taken connect issue_slots[10].in_uop.bits.pc_lob, issue_slots[11].out_uop.pc_lob connect issue_slots[10].in_uop.bits.edge_inst, issue_slots[11].out_uop.edge_inst connect issue_slots[10].in_uop.bits.ftq_idx, issue_slots[11].out_uop.ftq_idx connect issue_slots[10].in_uop.bits.is_mov, issue_slots[11].out_uop.is_mov connect issue_slots[10].in_uop.bits.is_rocc, issue_slots[11].out_uop.is_rocc connect issue_slots[10].in_uop.bits.is_sys_pc2epc, issue_slots[11].out_uop.is_sys_pc2epc connect issue_slots[10].in_uop.bits.is_eret, issue_slots[11].out_uop.is_eret connect issue_slots[10].in_uop.bits.is_amo, issue_slots[11].out_uop.is_amo connect issue_slots[10].in_uop.bits.is_sfence, issue_slots[11].out_uop.is_sfence connect issue_slots[10].in_uop.bits.is_fencei, issue_slots[11].out_uop.is_fencei connect issue_slots[10].in_uop.bits.is_fence, issue_slots[11].out_uop.is_fence connect issue_slots[10].in_uop.bits.is_sfb, issue_slots[11].out_uop.is_sfb connect issue_slots[10].in_uop.bits.br_type, issue_slots[11].out_uop.br_type connect issue_slots[10].in_uop.bits.br_tag, issue_slots[11].out_uop.br_tag connect issue_slots[10].in_uop.bits.br_mask, issue_slots[11].out_uop.br_mask connect issue_slots[10].in_uop.bits.dis_col_sel, issue_slots[11].out_uop.dis_col_sel connect issue_slots[10].in_uop.bits.iw_p3_bypass_hint, issue_slots[11].out_uop.iw_p3_bypass_hint connect issue_slots[10].in_uop.bits.iw_p2_bypass_hint, issue_slots[11].out_uop.iw_p2_bypass_hint connect issue_slots[10].in_uop.bits.iw_p1_bypass_hint, issue_slots[11].out_uop.iw_p1_bypass_hint connect issue_slots[10].in_uop.bits.iw_p2_speculative_child, issue_slots[11].out_uop.iw_p2_speculative_child connect issue_slots[10].in_uop.bits.iw_p1_speculative_child, issue_slots[11].out_uop.iw_p1_speculative_child connect issue_slots[10].in_uop.bits.iw_issued_partial_dgen, issue_slots[11].out_uop.iw_issued_partial_dgen connect issue_slots[10].in_uop.bits.iw_issued_partial_agen, issue_slots[11].out_uop.iw_issued_partial_agen connect issue_slots[10].in_uop.bits.iw_issued, issue_slots[11].out_uop.iw_issued connect issue_slots[10].in_uop.bits.fu_code[0], issue_slots[11].out_uop.fu_code[0] connect issue_slots[10].in_uop.bits.fu_code[1], issue_slots[11].out_uop.fu_code[1] connect issue_slots[10].in_uop.bits.fu_code[2], issue_slots[11].out_uop.fu_code[2] connect issue_slots[10].in_uop.bits.fu_code[3], issue_slots[11].out_uop.fu_code[3] connect issue_slots[10].in_uop.bits.fu_code[4], issue_slots[11].out_uop.fu_code[4] connect issue_slots[10].in_uop.bits.fu_code[5], issue_slots[11].out_uop.fu_code[5] connect issue_slots[10].in_uop.bits.fu_code[6], issue_slots[11].out_uop.fu_code[6] connect issue_slots[10].in_uop.bits.fu_code[7], issue_slots[11].out_uop.fu_code[7] connect issue_slots[10].in_uop.bits.fu_code[8], issue_slots[11].out_uop.fu_code[8] connect issue_slots[10].in_uop.bits.fu_code[9], issue_slots[11].out_uop.fu_code[9] connect issue_slots[10].in_uop.bits.iq_type[0], issue_slots[11].out_uop.iq_type[0] connect issue_slots[10].in_uop.bits.iq_type[1], issue_slots[11].out_uop.iq_type[1] connect issue_slots[10].in_uop.bits.iq_type[2], issue_slots[11].out_uop.iq_type[2] connect issue_slots[10].in_uop.bits.iq_type[3], issue_slots[11].out_uop.iq_type[3] connect issue_slots[10].in_uop.bits.debug_pc, issue_slots[11].out_uop.debug_pc connect issue_slots[10].in_uop.bits.is_rvc, issue_slots[11].out_uop.is_rvc connect issue_slots[10].in_uop.bits.debug_inst, issue_slots[11].out_uop.debug_inst connect issue_slots[10].in_uop.bits.inst, issue_slots[11].out_uop.inst node _T_307 = eq(shamts_oh[11], UInt<1>(0h1)) when _T_307 : connect issue_slots[10].in_uop.valid, issue_slots[11].will_be_valid connect issue_slots[10].in_uop.bits.debug_tsrc, issue_slots[11].out_uop.debug_tsrc connect issue_slots[10].in_uop.bits.debug_fsrc, issue_slots[11].out_uop.debug_fsrc connect issue_slots[10].in_uop.bits.bp_xcpt_if, issue_slots[11].out_uop.bp_xcpt_if connect issue_slots[10].in_uop.bits.bp_debug_if, issue_slots[11].out_uop.bp_debug_if connect issue_slots[10].in_uop.bits.xcpt_ma_if, issue_slots[11].out_uop.xcpt_ma_if connect issue_slots[10].in_uop.bits.xcpt_ae_if, issue_slots[11].out_uop.xcpt_ae_if connect issue_slots[10].in_uop.bits.xcpt_pf_if, issue_slots[11].out_uop.xcpt_pf_if connect issue_slots[10].in_uop.bits.fp_typ, issue_slots[11].out_uop.fp_typ connect issue_slots[10].in_uop.bits.fp_rm, issue_slots[11].out_uop.fp_rm connect issue_slots[10].in_uop.bits.fp_val, issue_slots[11].out_uop.fp_val connect issue_slots[10].in_uop.bits.fcn_op, issue_slots[11].out_uop.fcn_op connect issue_slots[10].in_uop.bits.fcn_dw, issue_slots[11].out_uop.fcn_dw connect issue_slots[10].in_uop.bits.frs3_en, issue_slots[11].out_uop.frs3_en connect issue_slots[10].in_uop.bits.lrs2_rtype, issue_slots[11].out_uop.lrs2_rtype connect issue_slots[10].in_uop.bits.lrs1_rtype, issue_slots[11].out_uop.lrs1_rtype connect issue_slots[10].in_uop.bits.dst_rtype, issue_slots[11].out_uop.dst_rtype connect issue_slots[10].in_uop.bits.lrs3, issue_slots[11].out_uop.lrs3 connect issue_slots[10].in_uop.bits.lrs2, issue_slots[11].out_uop.lrs2 connect issue_slots[10].in_uop.bits.lrs1, issue_slots[11].out_uop.lrs1 connect issue_slots[10].in_uop.bits.ldst, issue_slots[11].out_uop.ldst connect issue_slots[10].in_uop.bits.ldst_is_rs1, issue_slots[11].out_uop.ldst_is_rs1 connect issue_slots[10].in_uop.bits.csr_cmd, issue_slots[11].out_uop.csr_cmd connect issue_slots[10].in_uop.bits.flush_on_commit, issue_slots[11].out_uop.flush_on_commit connect issue_slots[10].in_uop.bits.is_unique, issue_slots[11].out_uop.is_unique connect issue_slots[10].in_uop.bits.uses_stq, issue_slots[11].out_uop.uses_stq connect issue_slots[10].in_uop.bits.uses_ldq, issue_slots[11].out_uop.uses_ldq connect issue_slots[10].in_uop.bits.mem_signed, issue_slots[11].out_uop.mem_signed connect issue_slots[10].in_uop.bits.mem_size, issue_slots[11].out_uop.mem_size connect issue_slots[10].in_uop.bits.mem_cmd, issue_slots[11].out_uop.mem_cmd connect issue_slots[10].in_uop.bits.exc_cause, issue_slots[11].out_uop.exc_cause connect issue_slots[10].in_uop.bits.exception, issue_slots[11].out_uop.exception connect issue_slots[10].in_uop.bits.stale_pdst, issue_slots[11].out_uop.stale_pdst connect issue_slots[10].in_uop.bits.ppred_busy, issue_slots[11].out_uop.ppred_busy connect issue_slots[10].in_uop.bits.prs3_busy, issue_slots[11].out_uop.prs3_busy connect issue_slots[10].in_uop.bits.prs2_busy, issue_slots[11].out_uop.prs2_busy connect issue_slots[10].in_uop.bits.prs1_busy, issue_slots[11].out_uop.prs1_busy connect issue_slots[10].in_uop.bits.ppred, issue_slots[11].out_uop.ppred connect issue_slots[10].in_uop.bits.prs3, issue_slots[11].out_uop.prs3 connect issue_slots[10].in_uop.bits.prs2, issue_slots[11].out_uop.prs2 connect issue_slots[10].in_uop.bits.prs1, issue_slots[11].out_uop.prs1 connect issue_slots[10].in_uop.bits.pdst, issue_slots[11].out_uop.pdst connect issue_slots[10].in_uop.bits.rxq_idx, issue_slots[11].out_uop.rxq_idx connect issue_slots[10].in_uop.bits.stq_idx, issue_slots[11].out_uop.stq_idx connect issue_slots[10].in_uop.bits.ldq_idx, issue_slots[11].out_uop.ldq_idx connect issue_slots[10].in_uop.bits.rob_idx, issue_slots[11].out_uop.rob_idx connect issue_slots[10].in_uop.bits.fp_ctrl.vec, issue_slots[11].out_uop.fp_ctrl.vec connect issue_slots[10].in_uop.bits.fp_ctrl.wflags, issue_slots[11].out_uop.fp_ctrl.wflags connect issue_slots[10].in_uop.bits.fp_ctrl.sqrt, issue_slots[11].out_uop.fp_ctrl.sqrt connect issue_slots[10].in_uop.bits.fp_ctrl.div, issue_slots[11].out_uop.fp_ctrl.div connect issue_slots[10].in_uop.bits.fp_ctrl.fma, issue_slots[11].out_uop.fp_ctrl.fma connect issue_slots[10].in_uop.bits.fp_ctrl.fastpipe, issue_slots[11].out_uop.fp_ctrl.fastpipe connect issue_slots[10].in_uop.bits.fp_ctrl.toint, issue_slots[11].out_uop.fp_ctrl.toint connect issue_slots[10].in_uop.bits.fp_ctrl.fromint, issue_slots[11].out_uop.fp_ctrl.fromint connect issue_slots[10].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[11].out_uop.fp_ctrl.typeTagOut connect issue_slots[10].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[11].out_uop.fp_ctrl.typeTagIn connect issue_slots[10].in_uop.bits.fp_ctrl.swap23, issue_slots[11].out_uop.fp_ctrl.swap23 connect issue_slots[10].in_uop.bits.fp_ctrl.swap12, issue_slots[11].out_uop.fp_ctrl.swap12 connect issue_slots[10].in_uop.bits.fp_ctrl.ren3, issue_slots[11].out_uop.fp_ctrl.ren3 connect issue_slots[10].in_uop.bits.fp_ctrl.ren2, issue_slots[11].out_uop.fp_ctrl.ren2 connect issue_slots[10].in_uop.bits.fp_ctrl.ren1, issue_slots[11].out_uop.fp_ctrl.ren1 connect issue_slots[10].in_uop.bits.fp_ctrl.wen, issue_slots[11].out_uop.fp_ctrl.wen connect issue_slots[10].in_uop.bits.fp_ctrl.ldst, issue_slots[11].out_uop.fp_ctrl.ldst connect issue_slots[10].in_uop.bits.op2_sel, issue_slots[11].out_uop.op2_sel connect issue_slots[10].in_uop.bits.op1_sel, issue_slots[11].out_uop.op1_sel connect issue_slots[10].in_uop.bits.imm_packed, issue_slots[11].out_uop.imm_packed connect issue_slots[10].in_uop.bits.pimm, issue_slots[11].out_uop.pimm connect issue_slots[10].in_uop.bits.imm_sel, issue_slots[11].out_uop.imm_sel connect issue_slots[10].in_uop.bits.imm_rename, issue_slots[11].out_uop.imm_rename connect issue_slots[10].in_uop.bits.taken, issue_slots[11].out_uop.taken connect issue_slots[10].in_uop.bits.pc_lob, issue_slots[11].out_uop.pc_lob connect issue_slots[10].in_uop.bits.edge_inst, issue_slots[11].out_uop.edge_inst connect issue_slots[10].in_uop.bits.ftq_idx, issue_slots[11].out_uop.ftq_idx connect issue_slots[10].in_uop.bits.is_mov, issue_slots[11].out_uop.is_mov connect issue_slots[10].in_uop.bits.is_rocc, issue_slots[11].out_uop.is_rocc connect issue_slots[10].in_uop.bits.is_sys_pc2epc, issue_slots[11].out_uop.is_sys_pc2epc connect issue_slots[10].in_uop.bits.is_eret, issue_slots[11].out_uop.is_eret connect issue_slots[10].in_uop.bits.is_amo, issue_slots[11].out_uop.is_amo connect issue_slots[10].in_uop.bits.is_sfence, issue_slots[11].out_uop.is_sfence connect issue_slots[10].in_uop.bits.is_fencei, issue_slots[11].out_uop.is_fencei connect issue_slots[10].in_uop.bits.is_fence, issue_slots[11].out_uop.is_fence connect issue_slots[10].in_uop.bits.is_sfb, issue_slots[11].out_uop.is_sfb connect issue_slots[10].in_uop.bits.br_type, issue_slots[11].out_uop.br_type connect issue_slots[10].in_uop.bits.br_tag, issue_slots[11].out_uop.br_tag connect issue_slots[10].in_uop.bits.br_mask, issue_slots[11].out_uop.br_mask connect issue_slots[10].in_uop.bits.dis_col_sel, issue_slots[11].out_uop.dis_col_sel connect issue_slots[10].in_uop.bits.iw_p3_bypass_hint, issue_slots[11].out_uop.iw_p3_bypass_hint connect issue_slots[10].in_uop.bits.iw_p2_bypass_hint, issue_slots[11].out_uop.iw_p2_bypass_hint connect issue_slots[10].in_uop.bits.iw_p1_bypass_hint, issue_slots[11].out_uop.iw_p1_bypass_hint connect issue_slots[10].in_uop.bits.iw_p2_speculative_child, issue_slots[11].out_uop.iw_p2_speculative_child connect issue_slots[10].in_uop.bits.iw_p1_speculative_child, issue_slots[11].out_uop.iw_p1_speculative_child connect issue_slots[10].in_uop.bits.iw_issued_partial_dgen, issue_slots[11].out_uop.iw_issued_partial_dgen connect issue_slots[10].in_uop.bits.iw_issued_partial_agen, issue_slots[11].out_uop.iw_issued_partial_agen connect issue_slots[10].in_uop.bits.iw_issued, issue_slots[11].out_uop.iw_issued connect issue_slots[10].in_uop.bits.fu_code[0], issue_slots[11].out_uop.fu_code[0] connect issue_slots[10].in_uop.bits.fu_code[1], issue_slots[11].out_uop.fu_code[1] connect issue_slots[10].in_uop.bits.fu_code[2], issue_slots[11].out_uop.fu_code[2] connect issue_slots[10].in_uop.bits.fu_code[3], issue_slots[11].out_uop.fu_code[3] connect issue_slots[10].in_uop.bits.fu_code[4], issue_slots[11].out_uop.fu_code[4] connect issue_slots[10].in_uop.bits.fu_code[5], issue_slots[11].out_uop.fu_code[5] connect issue_slots[10].in_uop.bits.fu_code[6], issue_slots[11].out_uop.fu_code[6] connect issue_slots[10].in_uop.bits.fu_code[7], issue_slots[11].out_uop.fu_code[7] connect issue_slots[10].in_uop.bits.fu_code[8], issue_slots[11].out_uop.fu_code[8] connect issue_slots[10].in_uop.bits.fu_code[9], issue_slots[11].out_uop.fu_code[9] connect issue_slots[10].in_uop.bits.iq_type[0], issue_slots[11].out_uop.iq_type[0] connect issue_slots[10].in_uop.bits.iq_type[1], issue_slots[11].out_uop.iq_type[1] connect issue_slots[10].in_uop.bits.iq_type[2], issue_slots[11].out_uop.iq_type[2] connect issue_slots[10].in_uop.bits.iq_type[3], issue_slots[11].out_uop.iq_type[3] connect issue_slots[10].in_uop.bits.debug_pc, issue_slots[11].out_uop.debug_pc connect issue_slots[10].in_uop.bits.is_rvc, issue_slots[11].out_uop.is_rvc connect issue_slots[10].in_uop.bits.debug_inst, issue_slots[11].out_uop.debug_inst connect issue_slots[10].in_uop.bits.inst, issue_slots[11].out_uop.inst node _T_308 = eq(shamts_oh[12], UInt<2>(0h2)) when _T_308 : connect issue_slots[10].in_uop.valid, issue_slots[12].will_be_valid connect issue_slots[10].in_uop.bits.debug_tsrc, issue_slots[12].out_uop.debug_tsrc connect issue_slots[10].in_uop.bits.debug_fsrc, issue_slots[12].out_uop.debug_fsrc connect issue_slots[10].in_uop.bits.bp_xcpt_if, issue_slots[12].out_uop.bp_xcpt_if connect issue_slots[10].in_uop.bits.bp_debug_if, issue_slots[12].out_uop.bp_debug_if connect issue_slots[10].in_uop.bits.xcpt_ma_if, issue_slots[12].out_uop.xcpt_ma_if connect issue_slots[10].in_uop.bits.xcpt_ae_if, issue_slots[12].out_uop.xcpt_ae_if connect issue_slots[10].in_uop.bits.xcpt_pf_if, issue_slots[12].out_uop.xcpt_pf_if connect issue_slots[10].in_uop.bits.fp_typ, issue_slots[12].out_uop.fp_typ connect issue_slots[10].in_uop.bits.fp_rm, issue_slots[12].out_uop.fp_rm connect issue_slots[10].in_uop.bits.fp_val, issue_slots[12].out_uop.fp_val connect issue_slots[10].in_uop.bits.fcn_op, issue_slots[12].out_uop.fcn_op connect issue_slots[10].in_uop.bits.fcn_dw, issue_slots[12].out_uop.fcn_dw connect issue_slots[10].in_uop.bits.frs3_en, issue_slots[12].out_uop.frs3_en connect issue_slots[10].in_uop.bits.lrs2_rtype, issue_slots[12].out_uop.lrs2_rtype connect issue_slots[10].in_uop.bits.lrs1_rtype, issue_slots[12].out_uop.lrs1_rtype connect issue_slots[10].in_uop.bits.dst_rtype, issue_slots[12].out_uop.dst_rtype connect issue_slots[10].in_uop.bits.lrs3, issue_slots[12].out_uop.lrs3 connect issue_slots[10].in_uop.bits.lrs2, issue_slots[12].out_uop.lrs2 connect issue_slots[10].in_uop.bits.lrs1, issue_slots[12].out_uop.lrs1 connect issue_slots[10].in_uop.bits.ldst, issue_slots[12].out_uop.ldst connect issue_slots[10].in_uop.bits.ldst_is_rs1, issue_slots[12].out_uop.ldst_is_rs1 connect issue_slots[10].in_uop.bits.csr_cmd, issue_slots[12].out_uop.csr_cmd connect issue_slots[10].in_uop.bits.flush_on_commit, issue_slots[12].out_uop.flush_on_commit connect issue_slots[10].in_uop.bits.is_unique, issue_slots[12].out_uop.is_unique connect issue_slots[10].in_uop.bits.uses_stq, issue_slots[12].out_uop.uses_stq connect issue_slots[10].in_uop.bits.uses_ldq, issue_slots[12].out_uop.uses_ldq connect issue_slots[10].in_uop.bits.mem_signed, issue_slots[12].out_uop.mem_signed connect issue_slots[10].in_uop.bits.mem_size, issue_slots[12].out_uop.mem_size connect issue_slots[10].in_uop.bits.mem_cmd, issue_slots[12].out_uop.mem_cmd connect issue_slots[10].in_uop.bits.exc_cause, issue_slots[12].out_uop.exc_cause connect issue_slots[10].in_uop.bits.exception, issue_slots[12].out_uop.exception connect issue_slots[10].in_uop.bits.stale_pdst, issue_slots[12].out_uop.stale_pdst connect issue_slots[10].in_uop.bits.ppred_busy, issue_slots[12].out_uop.ppred_busy connect issue_slots[10].in_uop.bits.prs3_busy, issue_slots[12].out_uop.prs3_busy connect issue_slots[10].in_uop.bits.prs2_busy, issue_slots[12].out_uop.prs2_busy connect issue_slots[10].in_uop.bits.prs1_busy, issue_slots[12].out_uop.prs1_busy connect issue_slots[10].in_uop.bits.ppred, issue_slots[12].out_uop.ppred connect issue_slots[10].in_uop.bits.prs3, issue_slots[12].out_uop.prs3 connect issue_slots[10].in_uop.bits.prs2, issue_slots[12].out_uop.prs2 connect issue_slots[10].in_uop.bits.prs1, issue_slots[12].out_uop.prs1 connect issue_slots[10].in_uop.bits.pdst, issue_slots[12].out_uop.pdst connect issue_slots[10].in_uop.bits.rxq_idx, issue_slots[12].out_uop.rxq_idx connect issue_slots[10].in_uop.bits.stq_idx, issue_slots[12].out_uop.stq_idx connect issue_slots[10].in_uop.bits.ldq_idx, issue_slots[12].out_uop.ldq_idx connect issue_slots[10].in_uop.bits.rob_idx, issue_slots[12].out_uop.rob_idx connect issue_slots[10].in_uop.bits.fp_ctrl.vec, issue_slots[12].out_uop.fp_ctrl.vec connect issue_slots[10].in_uop.bits.fp_ctrl.wflags, issue_slots[12].out_uop.fp_ctrl.wflags connect issue_slots[10].in_uop.bits.fp_ctrl.sqrt, issue_slots[12].out_uop.fp_ctrl.sqrt connect issue_slots[10].in_uop.bits.fp_ctrl.div, issue_slots[12].out_uop.fp_ctrl.div connect issue_slots[10].in_uop.bits.fp_ctrl.fma, issue_slots[12].out_uop.fp_ctrl.fma connect issue_slots[10].in_uop.bits.fp_ctrl.fastpipe, issue_slots[12].out_uop.fp_ctrl.fastpipe connect issue_slots[10].in_uop.bits.fp_ctrl.toint, issue_slots[12].out_uop.fp_ctrl.toint connect issue_slots[10].in_uop.bits.fp_ctrl.fromint, issue_slots[12].out_uop.fp_ctrl.fromint connect issue_slots[10].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[12].out_uop.fp_ctrl.typeTagOut connect issue_slots[10].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[12].out_uop.fp_ctrl.typeTagIn connect issue_slots[10].in_uop.bits.fp_ctrl.swap23, issue_slots[12].out_uop.fp_ctrl.swap23 connect issue_slots[10].in_uop.bits.fp_ctrl.swap12, issue_slots[12].out_uop.fp_ctrl.swap12 connect issue_slots[10].in_uop.bits.fp_ctrl.ren3, issue_slots[12].out_uop.fp_ctrl.ren3 connect issue_slots[10].in_uop.bits.fp_ctrl.ren2, issue_slots[12].out_uop.fp_ctrl.ren2 connect issue_slots[10].in_uop.bits.fp_ctrl.ren1, issue_slots[12].out_uop.fp_ctrl.ren1 connect issue_slots[10].in_uop.bits.fp_ctrl.wen, issue_slots[12].out_uop.fp_ctrl.wen connect issue_slots[10].in_uop.bits.fp_ctrl.ldst, issue_slots[12].out_uop.fp_ctrl.ldst connect issue_slots[10].in_uop.bits.op2_sel, issue_slots[12].out_uop.op2_sel connect issue_slots[10].in_uop.bits.op1_sel, issue_slots[12].out_uop.op1_sel connect issue_slots[10].in_uop.bits.imm_packed, issue_slots[12].out_uop.imm_packed connect issue_slots[10].in_uop.bits.pimm, issue_slots[12].out_uop.pimm connect issue_slots[10].in_uop.bits.imm_sel, issue_slots[12].out_uop.imm_sel connect issue_slots[10].in_uop.bits.imm_rename, issue_slots[12].out_uop.imm_rename connect issue_slots[10].in_uop.bits.taken, issue_slots[12].out_uop.taken connect issue_slots[10].in_uop.bits.pc_lob, issue_slots[12].out_uop.pc_lob connect issue_slots[10].in_uop.bits.edge_inst, issue_slots[12].out_uop.edge_inst connect issue_slots[10].in_uop.bits.ftq_idx, issue_slots[12].out_uop.ftq_idx connect issue_slots[10].in_uop.bits.is_mov, issue_slots[12].out_uop.is_mov connect issue_slots[10].in_uop.bits.is_rocc, issue_slots[12].out_uop.is_rocc connect issue_slots[10].in_uop.bits.is_sys_pc2epc, issue_slots[12].out_uop.is_sys_pc2epc connect issue_slots[10].in_uop.bits.is_eret, issue_slots[12].out_uop.is_eret connect issue_slots[10].in_uop.bits.is_amo, issue_slots[12].out_uop.is_amo connect issue_slots[10].in_uop.bits.is_sfence, issue_slots[12].out_uop.is_sfence connect issue_slots[10].in_uop.bits.is_fencei, issue_slots[12].out_uop.is_fencei connect issue_slots[10].in_uop.bits.is_fence, issue_slots[12].out_uop.is_fence connect issue_slots[10].in_uop.bits.is_sfb, issue_slots[12].out_uop.is_sfb connect issue_slots[10].in_uop.bits.br_type, issue_slots[12].out_uop.br_type connect issue_slots[10].in_uop.bits.br_tag, issue_slots[12].out_uop.br_tag connect issue_slots[10].in_uop.bits.br_mask, issue_slots[12].out_uop.br_mask connect issue_slots[10].in_uop.bits.dis_col_sel, issue_slots[12].out_uop.dis_col_sel connect issue_slots[10].in_uop.bits.iw_p3_bypass_hint, issue_slots[12].out_uop.iw_p3_bypass_hint connect issue_slots[10].in_uop.bits.iw_p2_bypass_hint, issue_slots[12].out_uop.iw_p2_bypass_hint connect issue_slots[10].in_uop.bits.iw_p1_bypass_hint, issue_slots[12].out_uop.iw_p1_bypass_hint connect issue_slots[10].in_uop.bits.iw_p2_speculative_child, issue_slots[12].out_uop.iw_p2_speculative_child connect issue_slots[10].in_uop.bits.iw_p1_speculative_child, issue_slots[12].out_uop.iw_p1_speculative_child connect issue_slots[10].in_uop.bits.iw_issued_partial_dgen, issue_slots[12].out_uop.iw_issued_partial_dgen connect issue_slots[10].in_uop.bits.iw_issued_partial_agen, issue_slots[12].out_uop.iw_issued_partial_agen connect issue_slots[10].in_uop.bits.iw_issued, issue_slots[12].out_uop.iw_issued connect issue_slots[10].in_uop.bits.fu_code[0], issue_slots[12].out_uop.fu_code[0] connect issue_slots[10].in_uop.bits.fu_code[1], issue_slots[12].out_uop.fu_code[1] connect issue_slots[10].in_uop.bits.fu_code[2], issue_slots[12].out_uop.fu_code[2] connect issue_slots[10].in_uop.bits.fu_code[3], issue_slots[12].out_uop.fu_code[3] connect issue_slots[10].in_uop.bits.fu_code[4], issue_slots[12].out_uop.fu_code[4] connect issue_slots[10].in_uop.bits.fu_code[5], issue_slots[12].out_uop.fu_code[5] connect issue_slots[10].in_uop.bits.fu_code[6], issue_slots[12].out_uop.fu_code[6] connect issue_slots[10].in_uop.bits.fu_code[7], issue_slots[12].out_uop.fu_code[7] connect issue_slots[10].in_uop.bits.fu_code[8], issue_slots[12].out_uop.fu_code[8] connect issue_slots[10].in_uop.bits.fu_code[9], issue_slots[12].out_uop.fu_code[9] connect issue_slots[10].in_uop.bits.iq_type[0], issue_slots[12].out_uop.iq_type[0] connect issue_slots[10].in_uop.bits.iq_type[1], issue_slots[12].out_uop.iq_type[1] connect issue_slots[10].in_uop.bits.iq_type[2], issue_slots[12].out_uop.iq_type[2] connect issue_slots[10].in_uop.bits.iq_type[3], issue_slots[12].out_uop.iq_type[3] connect issue_slots[10].in_uop.bits.debug_pc, issue_slots[12].out_uop.debug_pc connect issue_slots[10].in_uop.bits.is_rvc, issue_slots[12].out_uop.is_rvc connect issue_slots[10].in_uop.bits.debug_inst, issue_slots[12].out_uop.debug_inst connect issue_slots[10].in_uop.bits.inst, issue_slots[12].out_uop.inst node _T_309 = eq(shamts_oh[13], UInt<3>(0h4)) when _T_309 : connect issue_slots[10].in_uop.valid, issue_slots[13].will_be_valid connect issue_slots[10].in_uop.bits.debug_tsrc, issue_slots[13].out_uop.debug_tsrc connect issue_slots[10].in_uop.bits.debug_fsrc, issue_slots[13].out_uop.debug_fsrc connect issue_slots[10].in_uop.bits.bp_xcpt_if, issue_slots[13].out_uop.bp_xcpt_if connect issue_slots[10].in_uop.bits.bp_debug_if, issue_slots[13].out_uop.bp_debug_if connect issue_slots[10].in_uop.bits.xcpt_ma_if, issue_slots[13].out_uop.xcpt_ma_if connect issue_slots[10].in_uop.bits.xcpt_ae_if, issue_slots[13].out_uop.xcpt_ae_if connect issue_slots[10].in_uop.bits.xcpt_pf_if, issue_slots[13].out_uop.xcpt_pf_if connect issue_slots[10].in_uop.bits.fp_typ, issue_slots[13].out_uop.fp_typ connect issue_slots[10].in_uop.bits.fp_rm, issue_slots[13].out_uop.fp_rm connect issue_slots[10].in_uop.bits.fp_val, issue_slots[13].out_uop.fp_val connect issue_slots[10].in_uop.bits.fcn_op, issue_slots[13].out_uop.fcn_op connect issue_slots[10].in_uop.bits.fcn_dw, issue_slots[13].out_uop.fcn_dw connect issue_slots[10].in_uop.bits.frs3_en, issue_slots[13].out_uop.frs3_en connect issue_slots[10].in_uop.bits.lrs2_rtype, issue_slots[13].out_uop.lrs2_rtype connect issue_slots[10].in_uop.bits.lrs1_rtype, issue_slots[13].out_uop.lrs1_rtype connect issue_slots[10].in_uop.bits.dst_rtype, issue_slots[13].out_uop.dst_rtype connect issue_slots[10].in_uop.bits.lrs3, issue_slots[13].out_uop.lrs3 connect issue_slots[10].in_uop.bits.lrs2, issue_slots[13].out_uop.lrs2 connect issue_slots[10].in_uop.bits.lrs1, issue_slots[13].out_uop.lrs1 connect issue_slots[10].in_uop.bits.ldst, issue_slots[13].out_uop.ldst connect issue_slots[10].in_uop.bits.ldst_is_rs1, issue_slots[13].out_uop.ldst_is_rs1 connect issue_slots[10].in_uop.bits.csr_cmd, issue_slots[13].out_uop.csr_cmd connect issue_slots[10].in_uop.bits.flush_on_commit, issue_slots[13].out_uop.flush_on_commit connect issue_slots[10].in_uop.bits.is_unique, issue_slots[13].out_uop.is_unique connect issue_slots[10].in_uop.bits.uses_stq, issue_slots[13].out_uop.uses_stq connect issue_slots[10].in_uop.bits.uses_ldq, issue_slots[13].out_uop.uses_ldq connect issue_slots[10].in_uop.bits.mem_signed, issue_slots[13].out_uop.mem_signed connect issue_slots[10].in_uop.bits.mem_size, issue_slots[13].out_uop.mem_size connect issue_slots[10].in_uop.bits.mem_cmd, issue_slots[13].out_uop.mem_cmd connect issue_slots[10].in_uop.bits.exc_cause, issue_slots[13].out_uop.exc_cause connect issue_slots[10].in_uop.bits.exception, issue_slots[13].out_uop.exception connect issue_slots[10].in_uop.bits.stale_pdst, issue_slots[13].out_uop.stale_pdst connect issue_slots[10].in_uop.bits.ppred_busy, issue_slots[13].out_uop.ppred_busy connect issue_slots[10].in_uop.bits.prs3_busy, issue_slots[13].out_uop.prs3_busy connect issue_slots[10].in_uop.bits.prs2_busy, issue_slots[13].out_uop.prs2_busy connect issue_slots[10].in_uop.bits.prs1_busy, issue_slots[13].out_uop.prs1_busy connect issue_slots[10].in_uop.bits.ppred, issue_slots[13].out_uop.ppred connect issue_slots[10].in_uop.bits.prs3, issue_slots[13].out_uop.prs3 connect issue_slots[10].in_uop.bits.prs2, issue_slots[13].out_uop.prs2 connect issue_slots[10].in_uop.bits.prs1, issue_slots[13].out_uop.prs1 connect issue_slots[10].in_uop.bits.pdst, issue_slots[13].out_uop.pdst connect issue_slots[10].in_uop.bits.rxq_idx, issue_slots[13].out_uop.rxq_idx connect issue_slots[10].in_uop.bits.stq_idx, issue_slots[13].out_uop.stq_idx connect issue_slots[10].in_uop.bits.ldq_idx, issue_slots[13].out_uop.ldq_idx connect issue_slots[10].in_uop.bits.rob_idx, issue_slots[13].out_uop.rob_idx connect issue_slots[10].in_uop.bits.fp_ctrl.vec, issue_slots[13].out_uop.fp_ctrl.vec connect issue_slots[10].in_uop.bits.fp_ctrl.wflags, issue_slots[13].out_uop.fp_ctrl.wflags connect issue_slots[10].in_uop.bits.fp_ctrl.sqrt, issue_slots[13].out_uop.fp_ctrl.sqrt connect issue_slots[10].in_uop.bits.fp_ctrl.div, issue_slots[13].out_uop.fp_ctrl.div connect issue_slots[10].in_uop.bits.fp_ctrl.fma, issue_slots[13].out_uop.fp_ctrl.fma connect issue_slots[10].in_uop.bits.fp_ctrl.fastpipe, issue_slots[13].out_uop.fp_ctrl.fastpipe connect issue_slots[10].in_uop.bits.fp_ctrl.toint, issue_slots[13].out_uop.fp_ctrl.toint connect issue_slots[10].in_uop.bits.fp_ctrl.fromint, issue_slots[13].out_uop.fp_ctrl.fromint connect issue_slots[10].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[13].out_uop.fp_ctrl.typeTagOut connect issue_slots[10].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[13].out_uop.fp_ctrl.typeTagIn connect issue_slots[10].in_uop.bits.fp_ctrl.swap23, issue_slots[13].out_uop.fp_ctrl.swap23 connect issue_slots[10].in_uop.bits.fp_ctrl.swap12, issue_slots[13].out_uop.fp_ctrl.swap12 connect issue_slots[10].in_uop.bits.fp_ctrl.ren3, issue_slots[13].out_uop.fp_ctrl.ren3 connect issue_slots[10].in_uop.bits.fp_ctrl.ren2, issue_slots[13].out_uop.fp_ctrl.ren2 connect issue_slots[10].in_uop.bits.fp_ctrl.ren1, issue_slots[13].out_uop.fp_ctrl.ren1 connect issue_slots[10].in_uop.bits.fp_ctrl.wen, issue_slots[13].out_uop.fp_ctrl.wen connect issue_slots[10].in_uop.bits.fp_ctrl.ldst, issue_slots[13].out_uop.fp_ctrl.ldst connect issue_slots[10].in_uop.bits.op2_sel, issue_slots[13].out_uop.op2_sel connect issue_slots[10].in_uop.bits.op1_sel, issue_slots[13].out_uop.op1_sel connect issue_slots[10].in_uop.bits.imm_packed, issue_slots[13].out_uop.imm_packed connect issue_slots[10].in_uop.bits.pimm, issue_slots[13].out_uop.pimm connect issue_slots[10].in_uop.bits.imm_sel, issue_slots[13].out_uop.imm_sel connect issue_slots[10].in_uop.bits.imm_rename, issue_slots[13].out_uop.imm_rename connect issue_slots[10].in_uop.bits.taken, issue_slots[13].out_uop.taken connect issue_slots[10].in_uop.bits.pc_lob, issue_slots[13].out_uop.pc_lob connect issue_slots[10].in_uop.bits.edge_inst, issue_slots[13].out_uop.edge_inst connect issue_slots[10].in_uop.bits.ftq_idx, issue_slots[13].out_uop.ftq_idx connect issue_slots[10].in_uop.bits.is_mov, issue_slots[13].out_uop.is_mov connect issue_slots[10].in_uop.bits.is_rocc, issue_slots[13].out_uop.is_rocc connect issue_slots[10].in_uop.bits.is_sys_pc2epc, issue_slots[13].out_uop.is_sys_pc2epc connect issue_slots[10].in_uop.bits.is_eret, issue_slots[13].out_uop.is_eret connect issue_slots[10].in_uop.bits.is_amo, issue_slots[13].out_uop.is_amo connect issue_slots[10].in_uop.bits.is_sfence, issue_slots[13].out_uop.is_sfence connect issue_slots[10].in_uop.bits.is_fencei, issue_slots[13].out_uop.is_fencei connect issue_slots[10].in_uop.bits.is_fence, issue_slots[13].out_uop.is_fence connect issue_slots[10].in_uop.bits.is_sfb, issue_slots[13].out_uop.is_sfb connect issue_slots[10].in_uop.bits.br_type, issue_slots[13].out_uop.br_type connect issue_slots[10].in_uop.bits.br_tag, issue_slots[13].out_uop.br_tag connect issue_slots[10].in_uop.bits.br_mask, issue_slots[13].out_uop.br_mask connect issue_slots[10].in_uop.bits.dis_col_sel, issue_slots[13].out_uop.dis_col_sel connect issue_slots[10].in_uop.bits.iw_p3_bypass_hint, issue_slots[13].out_uop.iw_p3_bypass_hint connect issue_slots[10].in_uop.bits.iw_p2_bypass_hint, issue_slots[13].out_uop.iw_p2_bypass_hint connect issue_slots[10].in_uop.bits.iw_p1_bypass_hint, issue_slots[13].out_uop.iw_p1_bypass_hint connect issue_slots[10].in_uop.bits.iw_p2_speculative_child, issue_slots[13].out_uop.iw_p2_speculative_child connect issue_slots[10].in_uop.bits.iw_p1_speculative_child, issue_slots[13].out_uop.iw_p1_speculative_child connect issue_slots[10].in_uop.bits.iw_issued_partial_dgen, issue_slots[13].out_uop.iw_issued_partial_dgen connect issue_slots[10].in_uop.bits.iw_issued_partial_agen, issue_slots[13].out_uop.iw_issued_partial_agen connect issue_slots[10].in_uop.bits.iw_issued, issue_slots[13].out_uop.iw_issued connect issue_slots[10].in_uop.bits.fu_code[0], issue_slots[13].out_uop.fu_code[0] connect issue_slots[10].in_uop.bits.fu_code[1], issue_slots[13].out_uop.fu_code[1] connect issue_slots[10].in_uop.bits.fu_code[2], issue_slots[13].out_uop.fu_code[2] connect issue_slots[10].in_uop.bits.fu_code[3], issue_slots[13].out_uop.fu_code[3] connect issue_slots[10].in_uop.bits.fu_code[4], issue_slots[13].out_uop.fu_code[4] connect issue_slots[10].in_uop.bits.fu_code[5], issue_slots[13].out_uop.fu_code[5] connect issue_slots[10].in_uop.bits.fu_code[6], issue_slots[13].out_uop.fu_code[6] connect issue_slots[10].in_uop.bits.fu_code[7], issue_slots[13].out_uop.fu_code[7] connect issue_slots[10].in_uop.bits.fu_code[8], issue_slots[13].out_uop.fu_code[8] connect issue_slots[10].in_uop.bits.fu_code[9], issue_slots[13].out_uop.fu_code[9] connect issue_slots[10].in_uop.bits.iq_type[0], issue_slots[13].out_uop.iq_type[0] connect issue_slots[10].in_uop.bits.iq_type[1], issue_slots[13].out_uop.iq_type[1] connect issue_slots[10].in_uop.bits.iq_type[2], issue_slots[13].out_uop.iq_type[2] connect issue_slots[10].in_uop.bits.iq_type[3], issue_slots[13].out_uop.iq_type[3] connect issue_slots[10].in_uop.bits.debug_pc, issue_slots[13].out_uop.debug_pc connect issue_slots[10].in_uop.bits.is_rvc, issue_slots[13].out_uop.is_rvc connect issue_slots[10].in_uop.bits.debug_inst, issue_slots[13].out_uop.debug_inst connect issue_slots[10].in_uop.bits.inst, issue_slots[13].out_uop.inst node _issue_slots_10_clear_T = neq(shamts_oh[10], UInt<1>(0h0)) connect issue_slots[10].clear, _issue_slots_10_clear_T connect issue_slots[11].in_uop.valid, UInt<1>(0h0) connect issue_slots[11].in_uop.bits.debug_tsrc, issue_slots[12].out_uop.debug_tsrc connect issue_slots[11].in_uop.bits.debug_fsrc, issue_slots[12].out_uop.debug_fsrc connect issue_slots[11].in_uop.bits.bp_xcpt_if, issue_slots[12].out_uop.bp_xcpt_if connect issue_slots[11].in_uop.bits.bp_debug_if, issue_slots[12].out_uop.bp_debug_if connect issue_slots[11].in_uop.bits.xcpt_ma_if, issue_slots[12].out_uop.xcpt_ma_if connect issue_slots[11].in_uop.bits.xcpt_ae_if, issue_slots[12].out_uop.xcpt_ae_if connect issue_slots[11].in_uop.bits.xcpt_pf_if, issue_slots[12].out_uop.xcpt_pf_if connect issue_slots[11].in_uop.bits.fp_typ, issue_slots[12].out_uop.fp_typ connect issue_slots[11].in_uop.bits.fp_rm, issue_slots[12].out_uop.fp_rm connect issue_slots[11].in_uop.bits.fp_val, issue_slots[12].out_uop.fp_val connect issue_slots[11].in_uop.bits.fcn_op, issue_slots[12].out_uop.fcn_op connect issue_slots[11].in_uop.bits.fcn_dw, issue_slots[12].out_uop.fcn_dw connect issue_slots[11].in_uop.bits.frs3_en, issue_slots[12].out_uop.frs3_en connect issue_slots[11].in_uop.bits.lrs2_rtype, issue_slots[12].out_uop.lrs2_rtype connect issue_slots[11].in_uop.bits.lrs1_rtype, issue_slots[12].out_uop.lrs1_rtype connect issue_slots[11].in_uop.bits.dst_rtype, issue_slots[12].out_uop.dst_rtype connect issue_slots[11].in_uop.bits.lrs3, issue_slots[12].out_uop.lrs3 connect issue_slots[11].in_uop.bits.lrs2, issue_slots[12].out_uop.lrs2 connect issue_slots[11].in_uop.bits.lrs1, issue_slots[12].out_uop.lrs1 connect issue_slots[11].in_uop.bits.ldst, issue_slots[12].out_uop.ldst connect issue_slots[11].in_uop.bits.ldst_is_rs1, issue_slots[12].out_uop.ldst_is_rs1 connect issue_slots[11].in_uop.bits.csr_cmd, issue_slots[12].out_uop.csr_cmd connect issue_slots[11].in_uop.bits.flush_on_commit, issue_slots[12].out_uop.flush_on_commit connect issue_slots[11].in_uop.bits.is_unique, issue_slots[12].out_uop.is_unique connect issue_slots[11].in_uop.bits.uses_stq, issue_slots[12].out_uop.uses_stq connect issue_slots[11].in_uop.bits.uses_ldq, issue_slots[12].out_uop.uses_ldq connect issue_slots[11].in_uop.bits.mem_signed, issue_slots[12].out_uop.mem_signed connect issue_slots[11].in_uop.bits.mem_size, issue_slots[12].out_uop.mem_size connect issue_slots[11].in_uop.bits.mem_cmd, issue_slots[12].out_uop.mem_cmd connect issue_slots[11].in_uop.bits.exc_cause, issue_slots[12].out_uop.exc_cause connect issue_slots[11].in_uop.bits.exception, issue_slots[12].out_uop.exception connect issue_slots[11].in_uop.bits.stale_pdst, issue_slots[12].out_uop.stale_pdst connect issue_slots[11].in_uop.bits.ppred_busy, issue_slots[12].out_uop.ppred_busy connect issue_slots[11].in_uop.bits.prs3_busy, issue_slots[12].out_uop.prs3_busy connect issue_slots[11].in_uop.bits.prs2_busy, issue_slots[12].out_uop.prs2_busy connect issue_slots[11].in_uop.bits.prs1_busy, issue_slots[12].out_uop.prs1_busy connect issue_slots[11].in_uop.bits.ppred, issue_slots[12].out_uop.ppred connect issue_slots[11].in_uop.bits.prs3, issue_slots[12].out_uop.prs3 connect issue_slots[11].in_uop.bits.prs2, issue_slots[12].out_uop.prs2 connect issue_slots[11].in_uop.bits.prs1, issue_slots[12].out_uop.prs1 connect issue_slots[11].in_uop.bits.pdst, issue_slots[12].out_uop.pdst connect issue_slots[11].in_uop.bits.rxq_idx, issue_slots[12].out_uop.rxq_idx connect issue_slots[11].in_uop.bits.stq_idx, issue_slots[12].out_uop.stq_idx connect issue_slots[11].in_uop.bits.ldq_idx, issue_slots[12].out_uop.ldq_idx connect issue_slots[11].in_uop.bits.rob_idx, issue_slots[12].out_uop.rob_idx connect issue_slots[11].in_uop.bits.fp_ctrl.vec, issue_slots[12].out_uop.fp_ctrl.vec connect issue_slots[11].in_uop.bits.fp_ctrl.wflags, issue_slots[12].out_uop.fp_ctrl.wflags connect issue_slots[11].in_uop.bits.fp_ctrl.sqrt, issue_slots[12].out_uop.fp_ctrl.sqrt connect issue_slots[11].in_uop.bits.fp_ctrl.div, issue_slots[12].out_uop.fp_ctrl.div connect issue_slots[11].in_uop.bits.fp_ctrl.fma, issue_slots[12].out_uop.fp_ctrl.fma connect issue_slots[11].in_uop.bits.fp_ctrl.fastpipe, issue_slots[12].out_uop.fp_ctrl.fastpipe connect issue_slots[11].in_uop.bits.fp_ctrl.toint, issue_slots[12].out_uop.fp_ctrl.toint connect issue_slots[11].in_uop.bits.fp_ctrl.fromint, issue_slots[12].out_uop.fp_ctrl.fromint connect issue_slots[11].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[12].out_uop.fp_ctrl.typeTagOut connect issue_slots[11].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[12].out_uop.fp_ctrl.typeTagIn connect issue_slots[11].in_uop.bits.fp_ctrl.swap23, issue_slots[12].out_uop.fp_ctrl.swap23 connect issue_slots[11].in_uop.bits.fp_ctrl.swap12, issue_slots[12].out_uop.fp_ctrl.swap12 connect issue_slots[11].in_uop.bits.fp_ctrl.ren3, issue_slots[12].out_uop.fp_ctrl.ren3 connect issue_slots[11].in_uop.bits.fp_ctrl.ren2, issue_slots[12].out_uop.fp_ctrl.ren2 connect issue_slots[11].in_uop.bits.fp_ctrl.ren1, issue_slots[12].out_uop.fp_ctrl.ren1 connect issue_slots[11].in_uop.bits.fp_ctrl.wen, issue_slots[12].out_uop.fp_ctrl.wen connect issue_slots[11].in_uop.bits.fp_ctrl.ldst, issue_slots[12].out_uop.fp_ctrl.ldst connect issue_slots[11].in_uop.bits.op2_sel, issue_slots[12].out_uop.op2_sel connect issue_slots[11].in_uop.bits.op1_sel, issue_slots[12].out_uop.op1_sel connect issue_slots[11].in_uop.bits.imm_packed, issue_slots[12].out_uop.imm_packed connect issue_slots[11].in_uop.bits.pimm, issue_slots[12].out_uop.pimm connect issue_slots[11].in_uop.bits.imm_sel, issue_slots[12].out_uop.imm_sel connect issue_slots[11].in_uop.bits.imm_rename, issue_slots[12].out_uop.imm_rename connect issue_slots[11].in_uop.bits.taken, issue_slots[12].out_uop.taken connect issue_slots[11].in_uop.bits.pc_lob, issue_slots[12].out_uop.pc_lob connect issue_slots[11].in_uop.bits.edge_inst, issue_slots[12].out_uop.edge_inst connect issue_slots[11].in_uop.bits.ftq_idx, issue_slots[12].out_uop.ftq_idx connect issue_slots[11].in_uop.bits.is_mov, issue_slots[12].out_uop.is_mov connect issue_slots[11].in_uop.bits.is_rocc, issue_slots[12].out_uop.is_rocc connect issue_slots[11].in_uop.bits.is_sys_pc2epc, issue_slots[12].out_uop.is_sys_pc2epc connect issue_slots[11].in_uop.bits.is_eret, issue_slots[12].out_uop.is_eret connect issue_slots[11].in_uop.bits.is_amo, issue_slots[12].out_uop.is_amo connect issue_slots[11].in_uop.bits.is_sfence, issue_slots[12].out_uop.is_sfence connect issue_slots[11].in_uop.bits.is_fencei, issue_slots[12].out_uop.is_fencei connect issue_slots[11].in_uop.bits.is_fence, issue_slots[12].out_uop.is_fence connect issue_slots[11].in_uop.bits.is_sfb, issue_slots[12].out_uop.is_sfb connect issue_slots[11].in_uop.bits.br_type, issue_slots[12].out_uop.br_type connect issue_slots[11].in_uop.bits.br_tag, issue_slots[12].out_uop.br_tag connect issue_slots[11].in_uop.bits.br_mask, issue_slots[12].out_uop.br_mask connect issue_slots[11].in_uop.bits.dis_col_sel, issue_slots[12].out_uop.dis_col_sel connect issue_slots[11].in_uop.bits.iw_p3_bypass_hint, issue_slots[12].out_uop.iw_p3_bypass_hint connect issue_slots[11].in_uop.bits.iw_p2_bypass_hint, issue_slots[12].out_uop.iw_p2_bypass_hint connect issue_slots[11].in_uop.bits.iw_p1_bypass_hint, issue_slots[12].out_uop.iw_p1_bypass_hint connect issue_slots[11].in_uop.bits.iw_p2_speculative_child, issue_slots[12].out_uop.iw_p2_speculative_child connect issue_slots[11].in_uop.bits.iw_p1_speculative_child, issue_slots[12].out_uop.iw_p1_speculative_child connect issue_slots[11].in_uop.bits.iw_issued_partial_dgen, issue_slots[12].out_uop.iw_issued_partial_dgen connect issue_slots[11].in_uop.bits.iw_issued_partial_agen, issue_slots[12].out_uop.iw_issued_partial_agen connect issue_slots[11].in_uop.bits.iw_issued, issue_slots[12].out_uop.iw_issued connect issue_slots[11].in_uop.bits.fu_code[0], issue_slots[12].out_uop.fu_code[0] connect issue_slots[11].in_uop.bits.fu_code[1], issue_slots[12].out_uop.fu_code[1] connect issue_slots[11].in_uop.bits.fu_code[2], issue_slots[12].out_uop.fu_code[2] connect issue_slots[11].in_uop.bits.fu_code[3], issue_slots[12].out_uop.fu_code[3] connect issue_slots[11].in_uop.bits.fu_code[4], issue_slots[12].out_uop.fu_code[4] connect issue_slots[11].in_uop.bits.fu_code[5], issue_slots[12].out_uop.fu_code[5] connect issue_slots[11].in_uop.bits.fu_code[6], issue_slots[12].out_uop.fu_code[6] connect issue_slots[11].in_uop.bits.fu_code[7], issue_slots[12].out_uop.fu_code[7] connect issue_slots[11].in_uop.bits.fu_code[8], issue_slots[12].out_uop.fu_code[8] connect issue_slots[11].in_uop.bits.fu_code[9], issue_slots[12].out_uop.fu_code[9] connect issue_slots[11].in_uop.bits.iq_type[0], issue_slots[12].out_uop.iq_type[0] connect issue_slots[11].in_uop.bits.iq_type[1], issue_slots[12].out_uop.iq_type[1] connect issue_slots[11].in_uop.bits.iq_type[2], issue_slots[12].out_uop.iq_type[2] connect issue_slots[11].in_uop.bits.iq_type[3], issue_slots[12].out_uop.iq_type[3] connect issue_slots[11].in_uop.bits.debug_pc, issue_slots[12].out_uop.debug_pc connect issue_slots[11].in_uop.bits.is_rvc, issue_slots[12].out_uop.is_rvc connect issue_slots[11].in_uop.bits.debug_inst, issue_slots[12].out_uop.debug_inst connect issue_slots[11].in_uop.bits.inst, issue_slots[12].out_uop.inst node _T_310 = eq(shamts_oh[12], UInt<1>(0h1)) when _T_310 : connect issue_slots[11].in_uop.valid, issue_slots[12].will_be_valid connect issue_slots[11].in_uop.bits.debug_tsrc, issue_slots[12].out_uop.debug_tsrc connect issue_slots[11].in_uop.bits.debug_fsrc, issue_slots[12].out_uop.debug_fsrc connect issue_slots[11].in_uop.bits.bp_xcpt_if, issue_slots[12].out_uop.bp_xcpt_if connect issue_slots[11].in_uop.bits.bp_debug_if, issue_slots[12].out_uop.bp_debug_if connect issue_slots[11].in_uop.bits.xcpt_ma_if, issue_slots[12].out_uop.xcpt_ma_if connect issue_slots[11].in_uop.bits.xcpt_ae_if, issue_slots[12].out_uop.xcpt_ae_if connect issue_slots[11].in_uop.bits.xcpt_pf_if, issue_slots[12].out_uop.xcpt_pf_if connect issue_slots[11].in_uop.bits.fp_typ, issue_slots[12].out_uop.fp_typ connect issue_slots[11].in_uop.bits.fp_rm, issue_slots[12].out_uop.fp_rm connect issue_slots[11].in_uop.bits.fp_val, issue_slots[12].out_uop.fp_val connect issue_slots[11].in_uop.bits.fcn_op, issue_slots[12].out_uop.fcn_op connect issue_slots[11].in_uop.bits.fcn_dw, issue_slots[12].out_uop.fcn_dw connect issue_slots[11].in_uop.bits.frs3_en, issue_slots[12].out_uop.frs3_en connect issue_slots[11].in_uop.bits.lrs2_rtype, issue_slots[12].out_uop.lrs2_rtype connect issue_slots[11].in_uop.bits.lrs1_rtype, issue_slots[12].out_uop.lrs1_rtype connect issue_slots[11].in_uop.bits.dst_rtype, issue_slots[12].out_uop.dst_rtype connect issue_slots[11].in_uop.bits.lrs3, issue_slots[12].out_uop.lrs3 connect issue_slots[11].in_uop.bits.lrs2, issue_slots[12].out_uop.lrs2 connect issue_slots[11].in_uop.bits.lrs1, issue_slots[12].out_uop.lrs1 connect issue_slots[11].in_uop.bits.ldst, issue_slots[12].out_uop.ldst connect issue_slots[11].in_uop.bits.ldst_is_rs1, issue_slots[12].out_uop.ldst_is_rs1 connect issue_slots[11].in_uop.bits.csr_cmd, issue_slots[12].out_uop.csr_cmd connect issue_slots[11].in_uop.bits.flush_on_commit, issue_slots[12].out_uop.flush_on_commit connect issue_slots[11].in_uop.bits.is_unique, issue_slots[12].out_uop.is_unique connect issue_slots[11].in_uop.bits.uses_stq, issue_slots[12].out_uop.uses_stq connect issue_slots[11].in_uop.bits.uses_ldq, issue_slots[12].out_uop.uses_ldq connect issue_slots[11].in_uop.bits.mem_signed, issue_slots[12].out_uop.mem_signed connect issue_slots[11].in_uop.bits.mem_size, issue_slots[12].out_uop.mem_size connect issue_slots[11].in_uop.bits.mem_cmd, issue_slots[12].out_uop.mem_cmd connect issue_slots[11].in_uop.bits.exc_cause, issue_slots[12].out_uop.exc_cause connect issue_slots[11].in_uop.bits.exception, issue_slots[12].out_uop.exception connect issue_slots[11].in_uop.bits.stale_pdst, issue_slots[12].out_uop.stale_pdst connect issue_slots[11].in_uop.bits.ppred_busy, issue_slots[12].out_uop.ppred_busy connect issue_slots[11].in_uop.bits.prs3_busy, issue_slots[12].out_uop.prs3_busy connect issue_slots[11].in_uop.bits.prs2_busy, issue_slots[12].out_uop.prs2_busy connect issue_slots[11].in_uop.bits.prs1_busy, issue_slots[12].out_uop.prs1_busy connect issue_slots[11].in_uop.bits.ppred, issue_slots[12].out_uop.ppred connect issue_slots[11].in_uop.bits.prs3, issue_slots[12].out_uop.prs3 connect issue_slots[11].in_uop.bits.prs2, issue_slots[12].out_uop.prs2 connect issue_slots[11].in_uop.bits.prs1, issue_slots[12].out_uop.prs1 connect issue_slots[11].in_uop.bits.pdst, issue_slots[12].out_uop.pdst connect issue_slots[11].in_uop.bits.rxq_idx, issue_slots[12].out_uop.rxq_idx connect issue_slots[11].in_uop.bits.stq_idx, issue_slots[12].out_uop.stq_idx connect issue_slots[11].in_uop.bits.ldq_idx, issue_slots[12].out_uop.ldq_idx connect issue_slots[11].in_uop.bits.rob_idx, issue_slots[12].out_uop.rob_idx connect issue_slots[11].in_uop.bits.fp_ctrl.vec, issue_slots[12].out_uop.fp_ctrl.vec connect issue_slots[11].in_uop.bits.fp_ctrl.wflags, issue_slots[12].out_uop.fp_ctrl.wflags connect issue_slots[11].in_uop.bits.fp_ctrl.sqrt, issue_slots[12].out_uop.fp_ctrl.sqrt connect issue_slots[11].in_uop.bits.fp_ctrl.div, issue_slots[12].out_uop.fp_ctrl.div connect issue_slots[11].in_uop.bits.fp_ctrl.fma, issue_slots[12].out_uop.fp_ctrl.fma connect issue_slots[11].in_uop.bits.fp_ctrl.fastpipe, issue_slots[12].out_uop.fp_ctrl.fastpipe connect issue_slots[11].in_uop.bits.fp_ctrl.toint, issue_slots[12].out_uop.fp_ctrl.toint connect issue_slots[11].in_uop.bits.fp_ctrl.fromint, issue_slots[12].out_uop.fp_ctrl.fromint connect issue_slots[11].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[12].out_uop.fp_ctrl.typeTagOut connect issue_slots[11].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[12].out_uop.fp_ctrl.typeTagIn connect issue_slots[11].in_uop.bits.fp_ctrl.swap23, issue_slots[12].out_uop.fp_ctrl.swap23 connect issue_slots[11].in_uop.bits.fp_ctrl.swap12, issue_slots[12].out_uop.fp_ctrl.swap12 connect issue_slots[11].in_uop.bits.fp_ctrl.ren3, issue_slots[12].out_uop.fp_ctrl.ren3 connect issue_slots[11].in_uop.bits.fp_ctrl.ren2, issue_slots[12].out_uop.fp_ctrl.ren2 connect issue_slots[11].in_uop.bits.fp_ctrl.ren1, issue_slots[12].out_uop.fp_ctrl.ren1 connect issue_slots[11].in_uop.bits.fp_ctrl.wen, issue_slots[12].out_uop.fp_ctrl.wen connect issue_slots[11].in_uop.bits.fp_ctrl.ldst, issue_slots[12].out_uop.fp_ctrl.ldst connect issue_slots[11].in_uop.bits.op2_sel, issue_slots[12].out_uop.op2_sel connect issue_slots[11].in_uop.bits.op1_sel, issue_slots[12].out_uop.op1_sel connect issue_slots[11].in_uop.bits.imm_packed, issue_slots[12].out_uop.imm_packed connect issue_slots[11].in_uop.bits.pimm, issue_slots[12].out_uop.pimm connect issue_slots[11].in_uop.bits.imm_sel, issue_slots[12].out_uop.imm_sel connect issue_slots[11].in_uop.bits.imm_rename, issue_slots[12].out_uop.imm_rename connect issue_slots[11].in_uop.bits.taken, issue_slots[12].out_uop.taken connect issue_slots[11].in_uop.bits.pc_lob, issue_slots[12].out_uop.pc_lob connect issue_slots[11].in_uop.bits.edge_inst, issue_slots[12].out_uop.edge_inst connect issue_slots[11].in_uop.bits.ftq_idx, issue_slots[12].out_uop.ftq_idx connect issue_slots[11].in_uop.bits.is_mov, issue_slots[12].out_uop.is_mov connect issue_slots[11].in_uop.bits.is_rocc, issue_slots[12].out_uop.is_rocc connect issue_slots[11].in_uop.bits.is_sys_pc2epc, issue_slots[12].out_uop.is_sys_pc2epc connect issue_slots[11].in_uop.bits.is_eret, issue_slots[12].out_uop.is_eret connect issue_slots[11].in_uop.bits.is_amo, issue_slots[12].out_uop.is_amo connect issue_slots[11].in_uop.bits.is_sfence, issue_slots[12].out_uop.is_sfence connect issue_slots[11].in_uop.bits.is_fencei, issue_slots[12].out_uop.is_fencei connect issue_slots[11].in_uop.bits.is_fence, issue_slots[12].out_uop.is_fence connect issue_slots[11].in_uop.bits.is_sfb, issue_slots[12].out_uop.is_sfb connect issue_slots[11].in_uop.bits.br_type, issue_slots[12].out_uop.br_type connect issue_slots[11].in_uop.bits.br_tag, issue_slots[12].out_uop.br_tag connect issue_slots[11].in_uop.bits.br_mask, issue_slots[12].out_uop.br_mask connect issue_slots[11].in_uop.bits.dis_col_sel, issue_slots[12].out_uop.dis_col_sel connect issue_slots[11].in_uop.bits.iw_p3_bypass_hint, issue_slots[12].out_uop.iw_p3_bypass_hint connect issue_slots[11].in_uop.bits.iw_p2_bypass_hint, issue_slots[12].out_uop.iw_p2_bypass_hint connect issue_slots[11].in_uop.bits.iw_p1_bypass_hint, issue_slots[12].out_uop.iw_p1_bypass_hint connect issue_slots[11].in_uop.bits.iw_p2_speculative_child, issue_slots[12].out_uop.iw_p2_speculative_child connect issue_slots[11].in_uop.bits.iw_p1_speculative_child, issue_slots[12].out_uop.iw_p1_speculative_child connect issue_slots[11].in_uop.bits.iw_issued_partial_dgen, issue_slots[12].out_uop.iw_issued_partial_dgen connect issue_slots[11].in_uop.bits.iw_issued_partial_agen, issue_slots[12].out_uop.iw_issued_partial_agen connect issue_slots[11].in_uop.bits.iw_issued, issue_slots[12].out_uop.iw_issued connect issue_slots[11].in_uop.bits.fu_code[0], issue_slots[12].out_uop.fu_code[0] connect issue_slots[11].in_uop.bits.fu_code[1], issue_slots[12].out_uop.fu_code[1] connect issue_slots[11].in_uop.bits.fu_code[2], issue_slots[12].out_uop.fu_code[2] connect issue_slots[11].in_uop.bits.fu_code[3], issue_slots[12].out_uop.fu_code[3] connect issue_slots[11].in_uop.bits.fu_code[4], issue_slots[12].out_uop.fu_code[4] connect issue_slots[11].in_uop.bits.fu_code[5], issue_slots[12].out_uop.fu_code[5] connect issue_slots[11].in_uop.bits.fu_code[6], issue_slots[12].out_uop.fu_code[6] connect issue_slots[11].in_uop.bits.fu_code[7], issue_slots[12].out_uop.fu_code[7] connect issue_slots[11].in_uop.bits.fu_code[8], issue_slots[12].out_uop.fu_code[8] connect issue_slots[11].in_uop.bits.fu_code[9], issue_slots[12].out_uop.fu_code[9] connect issue_slots[11].in_uop.bits.iq_type[0], issue_slots[12].out_uop.iq_type[0] connect issue_slots[11].in_uop.bits.iq_type[1], issue_slots[12].out_uop.iq_type[1] connect issue_slots[11].in_uop.bits.iq_type[2], issue_slots[12].out_uop.iq_type[2] connect issue_slots[11].in_uop.bits.iq_type[3], issue_slots[12].out_uop.iq_type[3] connect issue_slots[11].in_uop.bits.debug_pc, issue_slots[12].out_uop.debug_pc connect issue_slots[11].in_uop.bits.is_rvc, issue_slots[12].out_uop.is_rvc connect issue_slots[11].in_uop.bits.debug_inst, issue_slots[12].out_uop.debug_inst connect issue_slots[11].in_uop.bits.inst, issue_slots[12].out_uop.inst node _T_311 = eq(shamts_oh[13], UInt<2>(0h2)) when _T_311 : connect issue_slots[11].in_uop.valid, issue_slots[13].will_be_valid connect issue_slots[11].in_uop.bits.debug_tsrc, issue_slots[13].out_uop.debug_tsrc connect issue_slots[11].in_uop.bits.debug_fsrc, issue_slots[13].out_uop.debug_fsrc connect issue_slots[11].in_uop.bits.bp_xcpt_if, issue_slots[13].out_uop.bp_xcpt_if connect issue_slots[11].in_uop.bits.bp_debug_if, issue_slots[13].out_uop.bp_debug_if connect issue_slots[11].in_uop.bits.xcpt_ma_if, issue_slots[13].out_uop.xcpt_ma_if connect issue_slots[11].in_uop.bits.xcpt_ae_if, issue_slots[13].out_uop.xcpt_ae_if connect issue_slots[11].in_uop.bits.xcpt_pf_if, issue_slots[13].out_uop.xcpt_pf_if connect issue_slots[11].in_uop.bits.fp_typ, issue_slots[13].out_uop.fp_typ connect issue_slots[11].in_uop.bits.fp_rm, issue_slots[13].out_uop.fp_rm connect issue_slots[11].in_uop.bits.fp_val, issue_slots[13].out_uop.fp_val connect issue_slots[11].in_uop.bits.fcn_op, issue_slots[13].out_uop.fcn_op connect issue_slots[11].in_uop.bits.fcn_dw, issue_slots[13].out_uop.fcn_dw connect issue_slots[11].in_uop.bits.frs3_en, issue_slots[13].out_uop.frs3_en connect issue_slots[11].in_uop.bits.lrs2_rtype, issue_slots[13].out_uop.lrs2_rtype connect issue_slots[11].in_uop.bits.lrs1_rtype, issue_slots[13].out_uop.lrs1_rtype connect issue_slots[11].in_uop.bits.dst_rtype, issue_slots[13].out_uop.dst_rtype connect issue_slots[11].in_uop.bits.lrs3, issue_slots[13].out_uop.lrs3 connect issue_slots[11].in_uop.bits.lrs2, issue_slots[13].out_uop.lrs2 connect issue_slots[11].in_uop.bits.lrs1, issue_slots[13].out_uop.lrs1 connect issue_slots[11].in_uop.bits.ldst, issue_slots[13].out_uop.ldst connect issue_slots[11].in_uop.bits.ldst_is_rs1, issue_slots[13].out_uop.ldst_is_rs1 connect issue_slots[11].in_uop.bits.csr_cmd, issue_slots[13].out_uop.csr_cmd connect issue_slots[11].in_uop.bits.flush_on_commit, issue_slots[13].out_uop.flush_on_commit connect issue_slots[11].in_uop.bits.is_unique, issue_slots[13].out_uop.is_unique connect issue_slots[11].in_uop.bits.uses_stq, issue_slots[13].out_uop.uses_stq connect issue_slots[11].in_uop.bits.uses_ldq, issue_slots[13].out_uop.uses_ldq connect issue_slots[11].in_uop.bits.mem_signed, issue_slots[13].out_uop.mem_signed connect issue_slots[11].in_uop.bits.mem_size, issue_slots[13].out_uop.mem_size connect issue_slots[11].in_uop.bits.mem_cmd, issue_slots[13].out_uop.mem_cmd connect issue_slots[11].in_uop.bits.exc_cause, issue_slots[13].out_uop.exc_cause connect issue_slots[11].in_uop.bits.exception, issue_slots[13].out_uop.exception connect issue_slots[11].in_uop.bits.stale_pdst, issue_slots[13].out_uop.stale_pdst connect issue_slots[11].in_uop.bits.ppred_busy, issue_slots[13].out_uop.ppred_busy connect issue_slots[11].in_uop.bits.prs3_busy, issue_slots[13].out_uop.prs3_busy connect issue_slots[11].in_uop.bits.prs2_busy, issue_slots[13].out_uop.prs2_busy connect issue_slots[11].in_uop.bits.prs1_busy, issue_slots[13].out_uop.prs1_busy connect issue_slots[11].in_uop.bits.ppred, issue_slots[13].out_uop.ppred connect issue_slots[11].in_uop.bits.prs3, issue_slots[13].out_uop.prs3 connect issue_slots[11].in_uop.bits.prs2, issue_slots[13].out_uop.prs2 connect issue_slots[11].in_uop.bits.prs1, issue_slots[13].out_uop.prs1 connect issue_slots[11].in_uop.bits.pdst, issue_slots[13].out_uop.pdst connect issue_slots[11].in_uop.bits.rxq_idx, issue_slots[13].out_uop.rxq_idx connect issue_slots[11].in_uop.bits.stq_idx, issue_slots[13].out_uop.stq_idx connect issue_slots[11].in_uop.bits.ldq_idx, issue_slots[13].out_uop.ldq_idx connect issue_slots[11].in_uop.bits.rob_idx, issue_slots[13].out_uop.rob_idx connect issue_slots[11].in_uop.bits.fp_ctrl.vec, issue_slots[13].out_uop.fp_ctrl.vec connect issue_slots[11].in_uop.bits.fp_ctrl.wflags, issue_slots[13].out_uop.fp_ctrl.wflags connect issue_slots[11].in_uop.bits.fp_ctrl.sqrt, issue_slots[13].out_uop.fp_ctrl.sqrt connect issue_slots[11].in_uop.bits.fp_ctrl.div, issue_slots[13].out_uop.fp_ctrl.div connect issue_slots[11].in_uop.bits.fp_ctrl.fma, issue_slots[13].out_uop.fp_ctrl.fma connect issue_slots[11].in_uop.bits.fp_ctrl.fastpipe, issue_slots[13].out_uop.fp_ctrl.fastpipe connect issue_slots[11].in_uop.bits.fp_ctrl.toint, issue_slots[13].out_uop.fp_ctrl.toint connect issue_slots[11].in_uop.bits.fp_ctrl.fromint, issue_slots[13].out_uop.fp_ctrl.fromint connect issue_slots[11].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[13].out_uop.fp_ctrl.typeTagOut connect issue_slots[11].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[13].out_uop.fp_ctrl.typeTagIn connect issue_slots[11].in_uop.bits.fp_ctrl.swap23, issue_slots[13].out_uop.fp_ctrl.swap23 connect issue_slots[11].in_uop.bits.fp_ctrl.swap12, issue_slots[13].out_uop.fp_ctrl.swap12 connect issue_slots[11].in_uop.bits.fp_ctrl.ren3, issue_slots[13].out_uop.fp_ctrl.ren3 connect issue_slots[11].in_uop.bits.fp_ctrl.ren2, issue_slots[13].out_uop.fp_ctrl.ren2 connect issue_slots[11].in_uop.bits.fp_ctrl.ren1, issue_slots[13].out_uop.fp_ctrl.ren1 connect issue_slots[11].in_uop.bits.fp_ctrl.wen, issue_slots[13].out_uop.fp_ctrl.wen connect issue_slots[11].in_uop.bits.fp_ctrl.ldst, issue_slots[13].out_uop.fp_ctrl.ldst connect issue_slots[11].in_uop.bits.op2_sel, issue_slots[13].out_uop.op2_sel connect issue_slots[11].in_uop.bits.op1_sel, issue_slots[13].out_uop.op1_sel connect issue_slots[11].in_uop.bits.imm_packed, issue_slots[13].out_uop.imm_packed connect issue_slots[11].in_uop.bits.pimm, issue_slots[13].out_uop.pimm connect issue_slots[11].in_uop.bits.imm_sel, issue_slots[13].out_uop.imm_sel connect issue_slots[11].in_uop.bits.imm_rename, issue_slots[13].out_uop.imm_rename connect issue_slots[11].in_uop.bits.taken, issue_slots[13].out_uop.taken connect issue_slots[11].in_uop.bits.pc_lob, issue_slots[13].out_uop.pc_lob connect issue_slots[11].in_uop.bits.edge_inst, issue_slots[13].out_uop.edge_inst connect issue_slots[11].in_uop.bits.ftq_idx, issue_slots[13].out_uop.ftq_idx connect issue_slots[11].in_uop.bits.is_mov, issue_slots[13].out_uop.is_mov connect issue_slots[11].in_uop.bits.is_rocc, issue_slots[13].out_uop.is_rocc connect issue_slots[11].in_uop.bits.is_sys_pc2epc, issue_slots[13].out_uop.is_sys_pc2epc connect issue_slots[11].in_uop.bits.is_eret, issue_slots[13].out_uop.is_eret connect issue_slots[11].in_uop.bits.is_amo, issue_slots[13].out_uop.is_amo connect issue_slots[11].in_uop.bits.is_sfence, issue_slots[13].out_uop.is_sfence connect issue_slots[11].in_uop.bits.is_fencei, issue_slots[13].out_uop.is_fencei connect issue_slots[11].in_uop.bits.is_fence, issue_slots[13].out_uop.is_fence connect issue_slots[11].in_uop.bits.is_sfb, issue_slots[13].out_uop.is_sfb connect issue_slots[11].in_uop.bits.br_type, issue_slots[13].out_uop.br_type connect issue_slots[11].in_uop.bits.br_tag, issue_slots[13].out_uop.br_tag connect issue_slots[11].in_uop.bits.br_mask, issue_slots[13].out_uop.br_mask connect issue_slots[11].in_uop.bits.dis_col_sel, issue_slots[13].out_uop.dis_col_sel connect issue_slots[11].in_uop.bits.iw_p3_bypass_hint, issue_slots[13].out_uop.iw_p3_bypass_hint connect issue_slots[11].in_uop.bits.iw_p2_bypass_hint, issue_slots[13].out_uop.iw_p2_bypass_hint connect issue_slots[11].in_uop.bits.iw_p1_bypass_hint, issue_slots[13].out_uop.iw_p1_bypass_hint connect issue_slots[11].in_uop.bits.iw_p2_speculative_child, issue_slots[13].out_uop.iw_p2_speculative_child connect issue_slots[11].in_uop.bits.iw_p1_speculative_child, issue_slots[13].out_uop.iw_p1_speculative_child connect issue_slots[11].in_uop.bits.iw_issued_partial_dgen, issue_slots[13].out_uop.iw_issued_partial_dgen connect issue_slots[11].in_uop.bits.iw_issued_partial_agen, issue_slots[13].out_uop.iw_issued_partial_agen connect issue_slots[11].in_uop.bits.iw_issued, issue_slots[13].out_uop.iw_issued connect issue_slots[11].in_uop.bits.fu_code[0], issue_slots[13].out_uop.fu_code[0] connect issue_slots[11].in_uop.bits.fu_code[1], issue_slots[13].out_uop.fu_code[1] connect issue_slots[11].in_uop.bits.fu_code[2], issue_slots[13].out_uop.fu_code[2] connect issue_slots[11].in_uop.bits.fu_code[3], issue_slots[13].out_uop.fu_code[3] connect issue_slots[11].in_uop.bits.fu_code[4], issue_slots[13].out_uop.fu_code[4] connect issue_slots[11].in_uop.bits.fu_code[5], issue_slots[13].out_uop.fu_code[5] connect issue_slots[11].in_uop.bits.fu_code[6], issue_slots[13].out_uop.fu_code[6] connect issue_slots[11].in_uop.bits.fu_code[7], issue_slots[13].out_uop.fu_code[7] connect issue_slots[11].in_uop.bits.fu_code[8], issue_slots[13].out_uop.fu_code[8] connect issue_slots[11].in_uop.bits.fu_code[9], issue_slots[13].out_uop.fu_code[9] connect issue_slots[11].in_uop.bits.iq_type[0], issue_slots[13].out_uop.iq_type[0] connect issue_slots[11].in_uop.bits.iq_type[1], issue_slots[13].out_uop.iq_type[1] connect issue_slots[11].in_uop.bits.iq_type[2], issue_slots[13].out_uop.iq_type[2] connect issue_slots[11].in_uop.bits.iq_type[3], issue_slots[13].out_uop.iq_type[3] connect issue_slots[11].in_uop.bits.debug_pc, issue_slots[13].out_uop.debug_pc connect issue_slots[11].in_uop.bits.is_rvc, issue_slots[13].out_uop.is_rvc connect issue_slots[11].in_uop.bits.debug_inst, issue_slots[13].out_uop.debug_inst connect issue_slots[11].in_uop.bits.inst, issue_slots[13].out_uop.inst node _T_312 = eq(shamts_oh[14], UInt<3>(0h4)) when _T_312 : connect issue_slots[11].in_uop.valid, issue_slots[14].will_be_valid connect issue_slots[11].in_uop.bits.debug_tsrc, issue_slots[14].out_uop.debug_tsrc connect issue_slots[11].in_uop.bits.debug_fsrc, issue_slots[14].out_uop.debug_fsrc connect issue_slots[11].in_uop.bits.bp_xcpt_if, issue_slots[14].out_uop.bp_xcpt_if connect issue_slots[11].in_uop.bits.bp_debug_if, issue_slots[14].out_uop.bp_debug_if connect issue_slots[11].in_uop.bits.xcpt_ma_if, issue_slots[14].out_uop.xcpt_ma_if connect issue_slots[11].in_uop.bits.xcpt_ae_if, issue_slots[14].out_uop.xcpt_ae_if connect issue_slots[11].in_uop.bits.xcpt_pf_if, issue_slots[14].out_uop.xcpt_pf_if connect issue_slots[11].in_uop.bits.fp_typ, issue_slots[14].out_uop.fp_typ connect issue_slots[11].in_uop.bits.fp_rm, issue_slots[14].out_uop.fp_rm connect issue_slots[11].in_uop.bits.fp_val, issue_slots[14].out_uop.fp_val connect issue_slots[11].in_uop.bits.fcn_op, issue_slots[14].out_uop.fcn_op connect issue_slots[11].in_uop.bits.fcn_dw, issue_slots[14].out_uop.fcn_dw connect issue_slots[11].in_uop.bits.frs3_en, issue_slots[14].out_uop.frs3_en connect issue_slots[11].in_uop.bits.lrs2_rtype, issue_slots[14].out_uop.lrs2_rtype connect issue_slots[11].in_uop.bits.lrs1_rtype, issue_slots[14].out_uop.lrs1_rtype connect issue_slots[11].in_uop.bits.dst_rtype, issue_slots[14].out_uop.dst_rtype connect issue_slots[11].in_uop.bits.lrs3, issue_slots[14].out_uop.lrs3 connect issue_slots[11].in_uop.bits.lrs2, issue_slots[14].out_uop.lrs2 connect issue_slots[11].in_uop.bits.lrs1, issue_slots[14].out_uop.lrs1 connect issue_slots[11].in_uop.bits.ldst, issue_slots[14].out_uop.ldst connect issue_slots[11].in_uop.bits.ldst_is_rs1, issue_slots[14].out_uop.ldst_is_rs1 connect issue_slots[11].in_uop.bits.csr_cmd, issue_slots[14].out_uop.csr_cmd connect issue_slots[11].in_uop.bits.flush_on_commit, issue_slots[14].out_uop.flush_on_commit connect issue_slots[11].in_uop.bits.is_unique, issue_slots[14].out_uop.is_unique connect issue_slots[11].in_uop.bits.uses_stq, issue_slots[14].out_uop.uses_stq connect issue_slots[11].in_uop.bits.uses_ldq, issue_slots[14].out_uop.uses_ldq connect issue_slots[11].in_uop.bits.mem_signed, issue_slots[14].out_uop.mem_signed connect issue_slots[11].in_uop.bits.mem_size, issue_slots[14].out_uop.mem_size connect issue_slots[11].in_uop.bits.mem_cmd, issue_slots[14].out_uop.mem_cmd connect issue_slots[11].in_uop.bits.exc_cause, issue_slots[14].out_uop.exc_cause connect issue_slots[11].in_uop.bits.exception, issue_slots[14].out_uop.exception connect issue_slots[11].in_uop.bits.stale_pdst, issue_slots[14].out_uop.stale_pdst connect issue_slots[11].in_uop.bits.ppred_busy, issue_slots[14].out_uop.ppred_busy connect issue_slots[11].in_uop.bits.prs3_busy, issue_slots[14].out_uop.prs3_busy connect issue_slots[11].in_uop.bits.prs2_busy, issue_slots[14].out_uop.prs2_busy connect issue_slots[11].in_uop.bits.prs1_busy, issue_slots[14].out_uop.prs1_busy connect issue_slots[11].in_uop.bits.ppred, issue_slots[14].out_uop.ppred connect issue_slots[11].in_uop.bits.prs3, issue_slots[14].out_uop.prs3 connect issue_slots[11].in_uop.bits.prs2, issue_slots[14].out_uop.prs2 connect issue_slots[11].in_uop.bits.prs1, issue_slots[14].out_uop.prs1 connect issue_slots[11].in_uop.bits.pdst, issue_slots[14].out_uop.pdst connect issue_slots[11].in_uop.bits.rxq_idx, issue_slots[14].out_uop.rxq_idx connect issue_slots[11].in_uop.bits.stq_idx, issue_slots[14].out_uop.stq_idx connect issue_slots[11].in_uop.bits.ldq_idx, issue_slots[14].out_uop.ldq_idx connect issue_slots[11].in_uop.bits.rob_idx, issue_slots[14].out_uop.rob_idx connect issue_slots[11].in_uop.bits.fp_ctrl.vec, issue_slots[14].out_uop.fp_ctrl.vec connect issue_slots[11].in_uop.bits.fp_ctrl.wflags, issue_slots[14].out_uop.fp_ctrl.wflags connect issue_slots[11].in_uop.bits.fp_ctrl.sqrt, issue_slots[14].out_uop.fp_ctrl.sqrt connect issue_slots[11].in_uop.bits.fp_ctrl.div, issue_slots[14].out_uop.fp_ctrl.div connect issue_slots[11].in_uop.bits.fp_ctrl.fma, issue_slots[14].out_uop.fp_ctrl.fma connect issue_slots[11].in_uop.bits.fp_ctrl.fastpipe, issue_slots[14].out_uop.fp_ctrl.fastpipe connect issue_slots[11].in_uop.bits.fp_ctrl.toint, issue_slots[14].out_uop.fp_ctrl.toint connect issue_slots[11].in_uop.bits.fp_ctrl.fromint, issue_slots[14].out_uop.fp_ctrl.fromint connect issue_slots[11].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[14].out_uop.fp_ctrl.typeTagOut connect issue_slots[11].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[14].out_uop.fp_ctrl.typeTagIn connect issue_slots[11].in_uop.bits.fp_ctrl.swap23, issue_slots[14].out_uop.fp_ctrl.swap23 connect issue_slots[11].in_uop.bits.fp_ctrl.swap12, issue_slots[14].out_uop.fp_ctrl.swap12 connect issue_slots[11].in_uop.bits.fp_ctrl.ren3, issue_slots[14].out_uop.fp_ctrl.ren3 connect issue_slots[11].in_uop.bits.fp_ctrl.ren2, issue_slots[14].out_uop.fp_ctrl.ren2 connect issue_slots[11].in_uop.bits.fp_ctrl.ren1, issue_slots[14].out_uop.fp_ctrl.ren1 connect issue_slots[11].in_uop.bits.fp_ctrl.wen, issue_slots[14].out_uop.fp_ctrl.wen connect issue_slots[11].in_uop.bits.fp_ctrl.ldst, issue_slots[14].out_uop.fp_ctrl.ldst connect issue_slots[11].in_uop.bits.op2_sel, issue_slots[14].out_uop.op2_sel connect issue_slots[11].in_uop.bits.op1_sel, issue_slots[14].out_uop.op1_sel connect issue_slots[11].in_uop.bits.imm_packed, issue_slots[14].out_uop.imm_packed connect issue_slots[11].in_uop.bits.pimm, issue_slots[14].out_uop.pimm connect issue_slots[11].in_uop.bits.imm_sel, issue_slots[14].out_uop.imm_sel connect issue_slots[11].in_uop.bits.imm_rename, issue_slots[14].out_uop.imm_rename connect issue_slots[11].in_uop.bits.taken, issue_slots[14].out_uop.taken connect issue_slots[11].in_uop.bits.pc_lob, issue_slots[14].out_uop.pc_lob connect issue_slots[11].in_uop.bits.edge_inst, issue_slots[14].out_uop.edge_inst connect issue_slots[11].in_uop.bits.ftq_idx, issue_slots[14].out_uop.ftq_idx connect issue_slots[11].in_uop.bits.is_mov, issue_slots[14].out_uop.is_mov connect issue_slots[11].in_uop.bits.is_rocc, issue_slots[14].out_uop.is_rocc connect issue_slots[11].in_uop.bits.is_sys_pc2epc, issue_slots[14].out_uop.is_sys_pc2epc connect issue_slots[11].in_uop.bits.is_eret, issue_slots[14].out_uop.is_eret connect issue_slots[11].in_uop.bits.is_amo, issue_slots[14].out_uop.is_amo connect issue_slots[11].in_uop.bits.is_sfence, issue_slots[14].out_uop.is_sfence connect issue_slots[11].in_uop.bits.is_fencei, issue_slots[14].out_uop.is_fencei connect issue_slots[11].in_uop.bits.is_fence, issue_slots[14].out_uop.is_fence connect issue_slots[11].in_uop.bits.is_sfb, issue_slots[14].out_uop.is_sfb connect issue_slots[11].in_uop.bits.br_type, issue_slots[14].out_uop.br_type connect issue_slots[11].in_uop.bits.br_tag, issue_slots[14].out_uop.br_tag connect issue_slots[11].in_uop.bits.br_mask, issue_slots[14].out_uop.br_mask connect issue_slots[11].in_uop.bits.dis_col_sel, issue_slots[14].out_uop.dis_col_sel connect issue_slots[11].in_uop.bits.iw_p3_bypass_hint, issue_slots[14].out_uop.iw_p3_bypass_hint connect issue_slots[11].in_uop.bits.iw_p2_bypass_hint, issue_slots[14].out_uop.iw_p2_bypass_hint connect issue_slots[11].in_uop.bits.iw_p1_bypass_hint, issue_slots[14].out_uop.iw_p1_bypass_hint connect issue_slots[11].in_uop.bits.iw_p2_speculative_child, issue_slots[14].out_uop.iw_p2_speculative_child connect issue_slots[11].in_uop.bits.iw_p1_speculative_child, issue_slots[14].out_uop.iw_p1_speculative_child connect issue_slots[11].in_uop.bits.iw_issued_partial_dgen, issue_slots[14].out_uop.iw_issued_partial_dgen connect issue_slots[11].in_uop.bits.iw_issued_partial_agen, issue_slots[14].out_uop.iw_issued_partial_agen connect issue_slots[11].in_uop.bits.iw_issued, issue_slots[14].out_uop.iw_issued connect issue_slots[11].in_uop.bits.fu_code[0], issue_slots[14].out_uop.fu_code[0] connect issue_slots[11].in_uop.bits.fu_code[1], issue_slots[14].out_uop.fu_code[1] connect issue_slots[11].in_uop.bits.fu_code[2], issue_slots[14].out_uop.fu_code[2] connect issue_slots[11].in_uop.bits.fu_code[3], issue_slots[14].out_uop.fu_code[3] connect issue_slots[11].in_uop.bits.fu_code[4], issue_slots[14].out_uop.fu_code[4] connect issue_slots[11].in_uop.bits.fu_code[5], issue_slots[14].out_uop.fu_code[5] connect issue_slots[11].in_uop.bits.fu_code[6], issue_slots[14].out_uop.fu_code[6] connect issue_slots[11].in_uop.bits.fu_code[7], issue_slots[14].out_uop.fu_code[7] connect issue_slots[11].in_uop.bits.fu_code[8], issue_slots[14].out_uop.fu_code[8] connect issue_slots[11].in_uop.bits.fu_code[9], issue_slots[14].out_uop.fu_code[9] connect issue_slots[11].in_uop.bits.iq_type[0], issue_slots[14].out_uop.iq_type[0] connect issue_slots[11].in_uop.bits.iq_type[1], issue_slots[14].out_uop.iq_type[1] connect issue_slots[11].in_uop.bits.iq_type[2], issue_slots[14].out_uop.iq_type[2] connect issue_slots[11].in_uop.bits.iq_type[3], issue_slots[14].out_uop.iq_type[3] connect issue_slots[11].in_uop.bits.debug_pc, issue_slots[14].out_uop.debug_pc connect issue_slots[11].in_uop.bits.is_rvc, issue_slots[14].out_uop.is_rvc connect issue_slots[11].in_uop.bits.debug_inst, issue_slots[14].out_uop.debug_inst connect issue_slots[11].in_uop.bits.inst, issue_slots[14].out_uop.inst node _issue_slots_11_clear_T = neq(shamts_oh[11], UInt<1>(0h0)) connect issue_slots[11].clear, _issue_slots_11_clear_T connect issue_slots[12].in_uop.valid, UInt<1>(0h0) connect issue_slots[12].in_uop.bits.debug_tsrc, issue_slots[13].out_uop.debug_tsrc connect issue_slots[12].in_uop.bits.debug_fsrc, issue_slots[13].out_uop.debug_fsrc connect issue_slots[12].in_uop.bits.bp_xcpt_if, issue_slots[13].out_uop.bp_xcpt_if connect issue_slots[12].in_uop.bits.bp_debug_if, issue_slots[13].out_uop.bp_debug_if connect issue_slots[12].in_uop.bits.xcpt_ma_if, issue_slots[13].out_uop.xcpt_ma_if connect issue_slots[12].in_uop.bits.xcpt_ae_if, issue_slots[13].out_uop.xcpt_ae_if connect issue_slots[12].in_uop.bits.xcpt_pf_if, issue_slots[13].out_uop.xcpt_pf_if connect issue_slots[12].in_uop.bits.fp_typ, issue_slots[13].out_uop.fp_typ connect issue_slots[12].in_uop.bits.fp_rm, issue_slots[13].out_uop.fp_rm connect issue_slots[12].in_uop.bits.fp_val, issue_slots[13].out_uop.fp_val connect issue_slots[12].in_uop.bits.fcn_op, issue_slots[13].out_uop.fcn_op connect issue_slots[12].in_uop.bits.fcn_dw, issue_slots[13].out_uop.fcn_dw connect issue_slots[12].in_uop.bits.frs3_en, issue_slots[13].out_uop.frs3_en connect issue_slots[12].in_uop.bits.lrs2_rtype, issue_slots[13].out_uop.lrs2_rtype connect issue_slots[12].in_uop.bits.lrs1_rtype, issue_slots[13].out_uop.lrs1_rtype connect issue_slots[12].in_uop.bits.dst_rtype, issue_slots[13].out_uop.dst_rtype connect issue_slots[12].in_uop.bits.lrs3, issue_slots[13].out_uop.lrs3 connect issue_slots[12].in_uop.bits.lrs2, issue_slots[13].out_uop.lrs2 connect issue_slots[12].in_uop.bits.lrs1, issue_slots[13].out_uop.lrs1 connect issue_slots[12].in_uop.bits.ldst, issue_slots[13].out_uop.ldst connect issue_slots[12].in_uop.bits.ldst_is_rs1, issue_slots[13].out_uop.ldst_is_rs1 connect issue_slots[12].in_uop.bits.csr_cmd, issue_slots[13].out_uop.csr_cmd connect issue_slots[12].in_uop.bits.flush_on_commit, issue_slots[13].out_uop.flush_on_commit connect issue_slots[12].in_uop.bits.is_unique, issue_slots[13].out_uop.is_unique connect issue_slots[12].in_uop.bits.uses_stq, issue_slots[13].out_uop.uses_stq connect issue_slots[12].in_uop.bits.uses_ldq, issue_slots[13].out_uop.uses_ldq connect issue_slots[12].in_uop.bits.mem_signed, issue_slots[13].out_uop.mem_signed connect issue_slots[12].in_uop.bits.mem_size, issue_slots[13].out_uop.mem_size connect issue_slots[12].in_uop.bits.mem_cmd, issue_slots[13].out_uop.mem_cmd connect issue_slots[12].in_uop.bits.exc_cause, issue_slots[13].out_uop.exc_cause connect issue_slots[12].in_uop.bits.exception, issue_slots[13].out_uop.exception connect issue_slots[12].in_uop.bits.stale_pdst, issue_slots[13].out_uop.stale_pdst connect issue_slots[12].in_uop.bits.ppred_busy, issue_slots[13].out_uop.ppred_busy connect issue_slots[12].in_uop.bits.prs3_busy, issue_slots[13].out_uop.prs3_busy connect issue_slots[12].in_uop.bits.prs2_busy, issue_slots[13].out_uop.prs2_busy connect issue_slots[12].in_uop.bits.prs1_busy, issue_slots[13].out_uop.prs1_busy connect issue_slots[12].in_uop.bits.ppred, issue_slots[13].out_uop.ppred connect issue_slots[12].in_uop.bits.prs3, issue_slots[13].out_uop.prs3 connect issue_slots[12].in_uop.bits.prs2, issue_slots[13].out_uop.prs2 connect issue_slots[12].in_uop.bits.prs1, issue_slots[13].out_uop.prs1 connect issue_slots[12].in_uop.bits.pdst, issue_slots[13].out_uop.pdst connect issue_slots[12].in_uop.bits.rxq_idx, issue_slots[13].out_uop.rxq_idx connect issue_slots[12].in_uop.bits.stq_idx, issue_slots[13].out_uop.stq_idx connect issue_slots[12].in_uop.bits.ldq_idx, issue_slots[13].out_uop.ldq_idx connect issue_slots[12].in_uop.bits.rob_idx, issue_slots[13].out_uop.rob_idx connect issue_slots[12].in_uop.bits.fp_ctrl.vec, issue_slots[13].out_uop.fp_ctrl.vec connect issue_slots[12].in_uop.bits.fp_ctrl.wflags, issue_slots[13].out_uop.fp_ctrl.wflags connect issue_slots[12].in_uop.bits.fp_ctrl.sqrt, issue_slots[13].out_uop.fp_ctrl.sqrt connect issue_slots[12].in_uop.bits.fp_ctrl.div, issue_slots[13].out_uop.fp_ctrl.div connect issue_slots[12].in_uop.bits.fp_ctrl.fma, issue_slots[13].out_uop.fp_ctrl.fma connect issue_slots[12].in_uop.bits.fp_ctrl.fastpipe, issue_slots[13].out_uop.fp_ctrl.fastpipe connect issue_slots[12].in_uop.bits.fp_ctrl.toint, issue_slots[13].out_uop.fp_ctrl.toint connect issue_slots[12].in_uop.bits.fp_ctrl.fromint, issue_slots[13].out_uop.fp_ctrl.fromint connect issue_slots[12].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[13].out_uop.fp_ctrl.typeTagOut connect issue_slots[12].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[13].out_uop.fp_ctrl.typeTagIn connect issue_slots[12].in_uop.bits.fp_ctrl.swap23, issue_slots[13].out_uop.fp_ctrl.swap23 connect issue_slots[12].in_uop.bits.fp_ctrl.swap12, issue_slots[13].out_uop.fp_ctrl.swap12 connect issue_slots[12].in_uop.bits.fp_ctrl.ren3, issue_slots[13].out_uop.fp_ctrl.ren3 connect issue_slots[12].in_uop.bits.fp_ctrl.ren2, issue_slots[13].out_uop.fp_ctrl.ren2 connect issue_slots[12].in_uop.bits.fp_ctrl.ren1, issue_slots[13].out_uop.fp_ctrl.ren1 connect issue_slots[12].in_uop.bits.fp_ctrl.wen, issue_slots[13].out_uop.fp_ctrl.wen connect issue_slots[12].in_uop.bits.fp_ctrl.ldst, issue_slots[13].out_uop.fp_ctrl.ldst connect issue_slots[12].in_uop.bits.op2_sel, issue_slots[13].out_uop.op2_sel connect issue_slots[12].in_uop.bits.op1_sel, issue_slots[13].out_uop.op1_sel connect issue_slots[12].in_uop.bits.imm_packed, issue_slots[13].out_uop.imm_packed connect issue_slots[12].in_uop.bits.pimm, issue_slots[13].out_uop.pimm connect issue_slots[12].in_uop.bits.imm_sel, issue_slots[13].out_uop.imm_sel connect issue_slots[12].in_uop.bits.imm_rename, issue_slots[13].out_uop.imm_rename connect issue_slots[12].in_uop.bits.taken, issue_slots[13].out_uop.taken connect issue_slots[12].in_uop.bits.pc_lob, issue_slots[13].out_uop.pc_lob connect issue_slots[12].in_uop.bits.edge_inst, issue_slots[13].out_uop.edge_inst connect issue_slots[12].in_uop.bits.ftq_idx, issue_slots[13].out_uop.ftq_idx connect issue_slots[12].in_uop.bits.is_mov, issue_slots[13].out_uop.is_mov connect issue_slots[12].in_uop.bits.is_rocc, issue_slots[13].out_uop.is_rocc connect issue_slots[12].in_uop.bits.is_sys_pc2epc, issue_slots[13].out_uop.is_sys_pc2epc connect issue_slots[12].in_uop.bits.is_eret, issue_slots[13].out_uop.is_eret connect issue_slots[12].in_uop.bits.is_amo, issue_slots[13].out_uop.is_amo connect issue_slots[12].in_uop.bits.is_sfence, issue_slots[13].out_uop.is_sfence connect issue_slots[12].in_uop.bits.is_fencei, issue_slots[13].out_uop.is_fencei connect issue_slots[12].in_uop.bits.is_fence, issue_slots[13].out_uop.is_fence connect issue_slots[12].in_uop.bits.is_sfb, issue_slots[13].out_uop.is_sfb connect issue_slots[12].in_uop.bits.br_type, issue_slots[13].out_uop.br_type connect issue_slots[12].in_uop.bits.br_tag, issue_slots[13].out_uop.br_tag connect issue_slots[12].in_uop.bits.br_mask, issue_slots[13].out_uop.br_mask connect issue_slots[12].in_uop.bits.dis_col_sel, issue_slots[13].out_uop.dis_col_sel connect issue_slots[12].in_uop.bits.iw_p3_bypass_hint, issue_slots[13].out_uop.iw_p3_bypass_hint connect issue_slots[12].in_uop.bits.iw_p2_bypass_hint, issue_slots[13].out_uop.iw_p2_bypass_hint connect issue_slots[12].in_uop.bits.iw_p1_bypass_hint, issue_slots[13].out_uop.iw_p1_bypass_hint connect issue_slots[12].in_uop.bits.iw_p2_speculative_child, issue_slots[13].out_uop.iw_p2_speculative_child connect issue_slots[12].in_uop.bits.iw_p1_speculative_child, issue_slots[13].out_uop.iw_p1_speculative_child connect issue_slots[12].in_uop.bits.iw_issued_partial_dgen, issue_slots[13].out_uop.iw_issued_partial_dgen connect issue_slots[12].in_uop.bits.iw_issued_partial_agen, issue_slots[13].out_uop.iw_issued_partial_agen connect issue_slots[12].in_uop.bits.iw_issued, issue_slots[13].out_uop.iw_issued connect issue_slots[12].in_uop.bits.fu_code[0], issue_slots[13].out_uop.fu_code[0] connect issue_slots[12].in_uop.bits.fu_code[1], issue_slots[13].out_uop.fu_code[1] connect issue_slots[12].in_uop.bits.fu_code[2], issue_slots[13].out_uop.fu_code[2] connect issue_slots[12].in_uop.bits.fu_code[3], issue_slots[13].out_uop.fu_code[3] connect issue_slots[12].in_uop.bits.fu_code[4], issue_slots[13].out_uop.fu_code[4] connect issue_slots[12].in_uop.bits.fu_code[5], issue_slots[13].out_uop.fu_code[5] connect issue_slots[12].in_uop.bits.fu_code[6], issue_slots[13].out_uop.fu_code[6] connect issue_slots[12].in_uop.bits.fu_code[7], issue_slots[13].out_uop.fu_code[7] connect issue_slots[12].in_uop.bits.fu_code[8], issue_slots[13].out_uop.fu_code[8] connect issue_slots[12].in_uop.bits.fu_code[9], issue_slots[13].out_uop.fu_code[9] connect issue_slots[12].in_uop.bits.iq_type[0], issue_slots[13].out_uop.iq_type[0] connect issue_slots[12].in_uop.bits.iq_type[1], issue_slots[13].out_uop.iq_type[1] connect issue_slots[12].in_uop.bits.iq_type[2], issue_slots[13].out_uop.iq_type[2] connect issue_slots[12].in_uop.bits.iq_type[3], issue_slots[13].out_uop.iq_type[3] connect issue_slots[12].in_uop.bits.debug_pc, issue_slots[13].out_uop.debug_pc connect issue_slots[12].in_uop.bits.is_rvc, issue_slots[13].out_uop.is_rvc connect issue_slots[12].in_uop.bits.debug_inst, issue_slots[13].out_uop.debug_inst connect issue_slots[12].in_uop.bits.inst, issue_slots[13].out_uop.inst node _T_313 = eq(shamts_oh[13], UInt<1>(0h1)) when _T_313 : connect issue_slots[12].in_uop.valid, issue_slots[13].will_be_valid connect issue_slots[12].in_uop.bits.debug_tsrc, issue_slots[13].out_uop.debug_tsrc connect issue_slots[12].in_uop.bits.debug_fsrc, issue_slots[13].out_uop.debug_fsrc connect issue_slots[12].in_uop.bits.bp_xcpt_if, issue_slots[13].out_uop.bp_xcpt_if connect issue_slots[12].in_uop.bits.bp_debug_if, issue_slots[13].out_uop.bp_debug_if connect issue_slots[12].in_uop.bits.xcpt_ma_if, issue_slots[13].out_uop.xcpt_ma_if connect issue_slots[12].in_uop.bits.xcpt_ae_if, issue_slots[13].out_uop.xcpt_ae_if connect issue_slots[12].in_uop.bits.xcpt_pf_if, issue_slots[13].out_uop.xcpt_pf_if connect issue_slots[12].in_uop.bits.fp_typ, issue_slots[13].out_uop.fp_typ connect issue_slots[12].in_uop.bits.fp_rm, issue_slots[13].out_uop.fp_rm connect issue_slots[12].in_uop.bits.fp_val, issue_slots[13].out_uop.fp_val connect issue_slots[12].in_uop.bits.fcn_op, issue_slots[13].out_uop.fcn_op connect issue_slots[12].in_uop.bits.fcn_dw, issue_slots[13].out_uop.fcn_dw connect issue_slots[12].in_uop.bits.frs3_en, issue_slots[13].out_uop.frs3_en connect issue_slots[12].in_uop.bits.lrs2_rtype, issue_slots[13].out_uop.lrs2_rtype connect issue_slots[12].in_uop.bits.lrs1_rtype, issue_slots[13].out_uop.lrs1_rtype connect issue_slots[12].in_uop.bits.dst_rtype, issue_slots[13].out_uop.dst_rtype connect issue_slots[12].in_uop.bits.lrs3, issue_slots[13].out_uop.lrs3 connect issue_slots[12].in_uop.bits.lrs2, issue_slots[13].out_uop.lrs2 connect issue_slots[12].in_uop.bits.lrs1, issue_slots[13].out_uop.lrs1 connect issue_slots[12].in_uop.bits.ldst, issue_slots[13].out_uop.ldst connect issue_slots[12].in_uop.bits.ldst_is_rs1, issue_slots[13].out_uop.ldst_is_rs1 connect issue_slots[12].in_uop.bits.csr_cmd, issue_slots[13].out_uop.csr_cmd connect issue_slots[12].in_uop.bits.flush_on_commit, issue_slots[13].out_uop.flush_on_commit connect issue_slots[12].in_uop.bits.is_unique, issue_slots[13].out_uop.is_unique connect issue_slots[12].in_uop.bits.uses_stq, issue_slots[13].out_uop.uses_stq connect issue_slots[12].in_uop.bits.uses_ldq, issue_slots[13].out_uop.uses_ldq connect issue_slots[12].in_uop.bits.mem_signed, issue_slots[13].out_uop.mem_signed connect issue_slots[12].in_uop.bits.mem_size, issue_slots[13].out_uop.mem_size connect issue_slots[12].in_uop.bits.mem_cmd, issue_slots[13].out_uop.mem_cmd connect issue_slots[12].in_uop.bits.exc_cause, issue_slots[13].out_uop.exc_cause connect issue_slots[12].in_uop.bits.exception, issue_slots[13].out_uop.exception connect issue_slots[12].in_uop.bits.stale_pdst, issue_slots[13].out_uop.stale_pdst connect issue_slots[12].in_uop.bits.ppred_busy, issue_slots[13].out_uop.ppred_busy connect issue_slots[12].in_uop.bits.prs3_busy, issue_slots[13].out_uop.prs3_busy connect issue_slots[12].in_uop.bits.prs2_busy, issue_slots[13].out_uop.prs2_busy connect issue_slots[12].in_uop.bits.prs1_busy, issue_slots[13].out_uop.prs1_busy connect issue_slots[12].in_uop.bits.ppred, issue_slots[13].out_uop.ppred connect issue_slots[12].in_uop.bits.prs3, issue_slots[13].out_uop.prs3 connect issue_slots[12].in_uop.bits.prs2, issue_slots[13].out_uop.prs2 connect issue_slots[12].in_uop.bits.prs1, issue_slots[13].out_uop.prs1 connect issue_slots[12].in_uop.bits.pdst, issue_slots[13].out_uop.pdst connect issue_slots[12].in_uop.bits.rxq_idx, issue_slots[13].out_uop.rxq_idx connect issue_slots[12].in_uop.bits.stq_idx, issue_slots[13].out_uop.stq_idx connect issue_slots[12].in_uop.bits.ldq_idx, issue_slots[13].out_uop.ldq_idx connect issue_slots[12].in_uop.bits.rob_idx, issue_slots[13].out_uop.rob_idx connect issue_slots[12].in_uop.bits.fp_ctrl.vec, issue_slots[13].out_uop.fp_ctrl.vec connect issue_slots[12].in_uop.bits.fp_ctrl.wflags, issue_slots[13].out_uop.fp_ctrl.wflags connect issue_slots[12].in_uop.bits.fp_ctrl.sqrt, issue_slots[13].out_uop.fp_ctrl.sqrt connect issue_slots[12].in_uop.bits.fp_ctrl.div, issue_slots[13].out_uop.fp_ctrl.div connect issue_slots[12].in_uop.bits.fp_ctrl.fma, issue_slots[13].out_uop.fp_ctrl.fma connect issue_slots[12].in_uop.bits.fp_ctrl.fastpipe, issue_slots[13].out_uop.fp_ctrl.fastpipe connect issue_slots[12].in_uop.bits.fp_ctrl.toint, issue_slots[13].out_uop.fp_ctrl.toint connect issue_slots[12].in_uop.bits.fp_ctrl.fromint, issue_slots[13].out_uop.fp_ctrl.fromint connect issue_slots[12].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[13].out_uop.fp_ctrl.typeTagOut connect issue_slots[12].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[13].out_uop.fp_ctrl.typeTagIn connect issue_slots[12].in_uop.bits.fp_ctrl.swap23, issue_slots[13].out_uop.fp_ctrl.swap23 connect issue_slots[12].in_uop.bits.fp_ctrl.swap12, issue_slots[13].out_uop.fp_ctrl.swap12 connect issue_slots[12].in_uop.bits.fp_ctrl.ren3, issue_slots[13].out_uop.fp_ctrl.ren3 connect issue_slots[12].in_uop.bits.fp_ctrl.ren2, issue_slots[13].out_uop.fp_ctrl.ren2 connect issue_slots[12].in_uop.bits.fp_ctrl.ren1, issue_slots[13].out_uop.fp_ctrl.ren1 connect issue_slots[12].in_uop.bits.fp_ctrl.wen, issue_slots[13].out_uop.fp_ctrl.wen connect issue_slots[12].in_uop.bits.fp_ctrl.ldst, issue_slots[13].out_uop.fp_ctrl.ldst connect issue_slots[12].in_uop.bits.op2_sel, issue_slots[13].out_uop.op2_sel connect issue_slots[12].in_uop.bits.op1_sel, issue_slots[13].out_uop.op1_sel connect issue_slots[12].in_uop.bits.imm_packed, issue_slots[13].out_uop.imm_packed connect issue_slots[12].in_uop.bits.pimm, issue_slots[13].out_uop.pimm connect issue_slots[12].in_uop.bits.imm_sel, issue_slots[13].out_uop.imm_sel connect issue_slots[12].in_uop.bits.imm_rename, issue_slots[13].out_uop.imm_rename connect issue_slots[12].in_uop.bits.taken, issue_slots[13].out_uop.taken connect issue_slots[12].in_uop.bits.pc_lob, issue_slots[13].out_uop.pc_lob connect issue_slots[12].in_uop.bits.edge_inst, issue_slots[13].out_uop.edge_inst connect issue_slots[12].in_uop.bits.ftq_idx, issue_slots[13].out_uop.ftq_idx connect issue_slots[12].in_uop.bits.is_mov, issue_slots[13].out_uop.is_mov connect issue_slots[12].in_uop.bits.is_rocc, issue_slots[13].out_uop.is_rocc connect issue_slots[12].in_uop.bits.is_sys_pc2epc, issue_slots[13].out_uop.is_sys_pc2epc connect issue_slots[12].in_uop.bits.is_eret, issue_slots[13].out_uop.is_eret connect issue_slots[12].in_uop.bits.is_amo, issue_slots[13].out_uop.is_amo connect issue_slots[12].in_uop.bits.is_sfence, issue_slots[13].out_uop.is_sfence connect issue_slots[12].in_uop.bits.is_fencei, issue_slots[13].out_uop.is_fencei connect issue_slots[12].in_uop.bits.is_fence, issue_slots[13].out_uop.is_fence connect issue_slots[12].in_uop.bits.is_sfb, issue_slots[13].out_uop.is_sfb connect issue_slots[12].in_uop.bits.br_type, issue_slots[13].out_uop.br_type connect issue_slots[12].in_uop.bits.br_tag, issue_slots[13].out_uop.br_tag connect issue_slots[12].in_uop.bits.br_mask, issue_slots[13].out_uop.br_mask connect issue_slots[12].in_uop.bits.dis_col_sel, issue_slots[13].out_uop.dis_col_sel connect issue_slots[12].in_uop.bits.iw_p3_bypass_hint, issue_slots[13].out_uop.iw_p3_bypass_hint connect issue_slots[12].in_uop.bits.iw_p2_bypass_hint, issue_slots[13].out_uop.iw_p2_bypass_hint connect issue_slots[12].in_uop.bits.iw_p1_bypass_hint, issue_slots[13].out_uop.iw_p1_bypass_hint connect issue_slots[12].in_uop.bits.iw_p2_speculative_child, issue_slots[13].out_uop.iw_p2_speculative_child connect issue_slots[12].in_uop.bits.iw_p1_speculative_child, issue_slots[13].out_uop.iw_p1_speculative_child connect issue_slots[12].in_uop.bits.iw_issued_partial_dgen, issue_slots[13].out_uop.iw_issued_partial_dgen connect issue_slots[12].in_uop.bits.iw_issued_partial_agen, issue_slots[13].out_uop.iw_issued_partial_agen connect issue_slots[12].in_uop.bits.iw_issued, issue_slots[13].out_uop.iw_issued connect issue_slots[12].in_uop.bits.fu_code[0], issue_slots[13].out_uop.fu_code[0] connect issue_slots[12].in_uop.bits.fu_code[1], issue_slots[13].out_uop.fu_code[1] connect issue_slots[12].in_uop.bits.fu_code[2], issue_slots[13].out_uop.fu_code[2] connect issue_slots[12].in_uop.bits.fu_code[3], issue_slots[13].out_uop.fu_code[3] connect issue_slots[12].in_uop.bits.fu_code[4], issue_slots[13].out_uop.fu_code[4] connect issue_slots[12].in_uop.bits.fu_code[5], issue_slots[13].out_uop.fu_code[5] connect issue_slots[12].in_uop.bits.fu_code[6], issue_slots[13].out_uop.fu_code[6] connect issue_slots[12].in_uop.bits.fu_code[7], issue_slots[13].out_uop.fu_code[7] connect issue_slots[12].in_uop.bits.fu_code[8], issue_slots[13].out_uop.fu_code[8] connect issue_slots[12].in_uop.bits.fu_code[9], issue_slots[13].out_uop.fu_code[9] connect issue_slots[12].in_uop.bits.iq_type[0], issue_slots[13].out_uop.iq_type[0] connect issue_slots[12].in_uop.bits.iq_type[1], issue_slots[13].out_uop.iq_type[1] connect issue_slots[12].in_uop.bits.iq_type[2], issue_slots[13].out_uop.iq_type[2] connect issue_slots[12].in_uop.bits.iq_type[3], issue_slots[13].out_uop.iq_type[3] connect issue_slots[12].in_uop.bits.debug_pc, issue_slots[13].out_uop.debug_pc connect issue_slots[12].in_uop.bits.is_rvc, issue_slots[13].out_uop.is_rvc connect issue_slots[12].in_uop.bits.debug_inst, issue_slots[13].out_uop.debug_inst connect issue_slots[12].in_uop.bits.inst, issue_slots[13].out_uop.inst node _T_314 = eq(shamts_oh[14], UInt<2>(0h2)) when _T_314 : connect issue_slots[12].in_uop.valid, issue_slots[14].will_be_valid connect issue_slots[12].in_uop.bits.debug_tsrc, issue_slots[14].out_uop.debug_tsrc connect issue_slots[12].in_uop.bits.debug_fsrc, issue_slots[14].out_uop.debug_fsrc connect issue_slots[12].in_uop.bits.bp_xcpt_if, issue_slots[14].out_uop.bp_xcpt_if connect issue_slots[12].in_uop.bits.bp_debug_if, issue_slots[14].out_uop.bp_debug_if connect issue_slots[12].in_uop.bits.xcpt_ma_if, issue_slots[14].out_uop.xcpt_ma_if connect issue_slots[12].in_uop.bits.xcpt_ae_if, issue_slots[14].out_uop.xcpt_ae_if connect issue_slots[12].in_uop.bits.xcpt_pf_if, issue_slots[14].out_uop.xcpt_pf_if connect issue_slots[12].in_uop.bits.fp_typ, issue_slots[14].out_uop.fp_typ connect issue_slots[12].in_uop.bits.fp_rm, issue_slots[14].out_uop.fp_rm connect issue_slots[12].in_uop.bits.fp_val, issue_slots[14].out_uop.fp_val connect issue_slots[12].in_uop.bits.fcn_op, issue_slots[14].out_uop.fcn_op connect issue_slots[12].in_uop.bits.fcn_dw, issue_slots[14].out_uop.fcn_dw connect issue_slots[12].in_uop.bits.frs3_en, issue_slots[14].out_uop.frs3_en connect issue_slots[12].in_uop.bits.lrs2_rtype, issue_slots[14].out_uop.lrs2_rtype connect issue_slots[12].in_uop.bits.lrs1_rtype, issue_slots[14].out_uop.lrs1_rtype connect issue_slots[12].in_uop.bits.dst_rtype, issue_slots[14].out_uop.dst_rtype connect issue_slots[12].in_uop.bits.lrs3, issue_slots[14].out_uop.lrs3 connect issue_slots[12].in_uop.bits.lrs2, issue_slots[14].out_uop.lrs2 connect issue_slots[12].in_uop.bits.lrs1, issue_slots[14].out_uop.lrs1 connect issue_slots[12].in_uop.bits.ldst, issue_slots[14].out_uop.ldst connect issue_slots[12].in_uop.bits.ldst_is_rs1, issue_slots[14].out_uop.ldst_is_rs1 connect issue_slots[12].in_uop.bits.csr_cmd, issue_slots[14].out_uop.csr_cmd connect issue_slots[12].in_uop.bits.flush_on_commit, issue_slots[14].out_uop.flush_on_commit connect issue_slots[12].in_uop.bits.is_unique, issue_slots[14].out_uop.is_unique connect issue_slots[12].in_uop.bits.uses_stq, issue_slots[14].out_uop.uses_stq connect issue_slots[12].in_uop.bits.uses_ldq, issue_slots[14].out_uop.uses_ldq connect issue_slots[12].in_uop.bits.mem_signed, issue_slots[14].out_uop.mem_signed connect issue_slots[12].in_uop.bits.mem_size, issue_slots[14].out_uop.mem_size connect issue_slots[12].in_uop.bits.mem_cmd, issue_slots[14].out_uop.mem_cmd connect issue_slots[12].in_uop.bits.exc_cause, issue_slots[14].out_uop.exc_cause connect issue_slots[12].in_uop.bits.exception, issue_slots[14].out_uop.exception connect issue_slots[12].in_uop.bits.stale_pdst, issue_slots[14].out_uop.stale_pdst connect issue_slots[12].in_uop.bits.ppred_busy, issue_slots[14].out_uop.ppred_busy connect issue_slots[12].in_uop.bits.prs3_busy, issue_slots[14].out_uop.prs3_busy connect issue_slots[12].in_uop.bits.prs2_busy, issue_slots[14].out_uop.prs2_busy connect issue_slots[12].in_uop.bits.prs1_busy, issue_slots[14].out_uop.prs1_busy connect issue_slots[12].in_uop.bits.ppred, issue_slots[14].out_uop.ppred connect issue_slots[12].in_uop.bits.prs3, issue_slots[14].out_uop.prs3 connect issue_slots[12].in_uop.bits.prs2, issue_slots[14].out_uop.prs2 connect issue_slots[12].in_uop.bits.prs1, issue_slots[14].out_uop.prs1 connect issue_slots[12].in_uop.bits.pdst, issue_slots[14].out_uop.pdst connect issue_slots[12].in_uop.bits.rxq_idx, issue_slots[14].out_uop.rxq_idx connect issue_slots[12].in_uop.bits.stq_idx, issue_slots[14].out_uop.stq_idx connect issue_slots[12].in_uop.bits.ldq_idx, issue_slots[14].out_uop.ldq_idx connect issue_slots[12].in_uop.bits.rob_idx, issue_slots[14].out_uop.rob_idx connect issue_slots[12].in_uop.bits.fp_ctrl.vec, issue_slots[14].out_uop.fp_ctrl.vec connect issue_slots[12].in_uop.bits.fp_ctrl.wflags, issue_slots[14].out_uop.fp_ctrl.wflags connect issue_slots[12].in_uop.bits.fp_ctrl.sqrt, issue_slots[14].out_uop.fp_ctrl.sqrt connect issue_slots[12].in_uop.bits.fp_ctrl.div, issue_slots[14].out_uop.fp_ctrl.div connect issue_slots[12].in_uop.bits.fp_ctrl.fma, issue_slots[14].out_uop.fp_ctrl.fma connect issue_slots[12].in_uop.bits.fp_ctrl.fastpipe, issue_slots[14].out_uop.fp_ctrl.fastpipe connect issue_slots[12].in_uop.bits.fp_ctrl.toint, issue_slots[14].out_uop.fp_ctrl.toint connect issue_slots[12].in_uop.bits.fp_ctrl.fromint, issue_slots[14].out_uop.fp_ctrl.fromint connect issue_slots[12].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[14].out_uop.fp_ctrl.typeTagOut connect issue_slots[12].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[14].out_uop.fp_ctrl.typeTagIn connect issue_slots[12].in_uop.bits.fp_ctrl.swap23, issue_slots[14].out_uop.fp_ctrl.swap23 connect issue_slots[12].in_uop.bits.fp_ctrl.swap12, issue_slots[14].out_uop.fp_ctrl.swap12 connect issue_slots[12].in_uop.bits.fp_ctrl.ren3, issue_slots[14].out_uop.fp_ctrl.ren3 connect issue_slots[12].in_uop.bits.fp_ctrl.ren2, issue_slots[14].out_uop.fp_ctrl.ren2 connect issue_slots[12].in_uop.bits.fp_ctrl.ren1, issue_slots[14].out_uop.fp_ctrl.ren1 connect issue_slots[12].in_uop.bits.fp_ctrl.wen, issue_slots[14].out_uop.fp_ctrl.wen connect issue_slots[12].in_uop.bits.fp_ctrl.ldst, issue_slots[14].out_uop.fp_ctrl.ldst connect issue_slots[12].in_uop.bits.op2_sel, issue_slots[14].out_uop.op2_sel connect issue_slots[12].in_uop.bits.op1_sel, issue_slots[14].out_uop.op1_sel connect issue_slots[12].in_uop.bits.imm_packed, issue_slots[14].out_uop.imm_packed connect issue_slots[12].in_uop.bits.pimm, issue_slots[14].out_uop.pimm connect issue_slots[12].in_uop.bits.imm_sel, issue_slots[14].out_uop.imm_sel connect issue_slots[12].in_uop.bits.imm_rename, issue_slots[14].out_uop.imm_rename connect issue_slots[12].in_uop.bits.taken, issue_slots[14].out_uop.taken connect issue_slots[12].in_uop.bits.pc_lob, issue_slots[14].out_uop.pc_lob connect issue_slots[12].in_uop.bits.edge_inst, issue_slots[14].out_uop.edge_inst connect issue_slots[12].in_uop.bits.ftq_idx, issue_slots[14].out_uop.ftq_idx connect issue_slots[12].in_uop.bits.is_mov, issue_slots[14].out_uop.is_mov connect issue_slots[12].in_uop.bits.is_rocc, issue_slots[14].out_uop.is_rocc connect issue_slots[12].in_uop.bits.is_sys_pc2epc, issue_slots[14].out_uop.is_sys_pc2epc connect issue_slots[12].in_uop.bits.is_eret, issue_slots[14].out_uop.is_eret connect issue_slots[12].in_uop.bits.is_amo, issue_slots[14].out_uop.is_amo connect issue_slots[12].in_uop.bits.is_sfence, issue_slots[14].out_uop.is_sfence connect issue_slots[12].in_uop.bits.is_fencei, issue_slots[14].out_uop.is_fencei connect issue_slots[12].in_uop.bits.is_fence, issue_slots[14].out_uop.is_fence connect issue_slots[12].in_uop.bits.is_sfb, issue_slots[14].out_uop.is_sfb connect issue_slots[12].in_uop.bits.br_type, issue_slots[14].out_uop.br_type connect issue_slots[12].in_uop.bits.br_tag, issue_slots[14].out_uop.br_tag connect issue_slots[12].in_uop.bits.br_mask, issue_slots[14].out_uop.br_mask connect issue_slots[12].in_uop.bits.dis_col_sel, issue_slots[14].out_uop.dis_col_sel connect issue_slots[12].in_uop.bits.iw_p3_bypass_hint, issue_slots[14].out_uop.iw_p3_bypass_hint connect issue_slots[12].in_uop.bits.iw_p2_bypass_hint, issue_slots[14].out_uop.iw_p2_bypass_hint connect issue_slots[12].in_uop.bits.iw_p1_bypass_hint, issue_slots[14].out_uop.iw_p1_bypass_hint connect issue_slots[12].in_uop.bits.iw_p2_speculative_child, issue_slots[14].out_uop.iw_p2_speculative_child connect issue_slots[12].in_uop.bits.iw_p1_speculative_child, issue_slots[14].out_uop.iw_p1_speculative_child connect issue_slots[12].in_uop.bits.iw_issued_partial_dgen, issue_slots[14].out_uop.iw_issued_partial_dgen connect issue_slots[12].in_uop.bits.iw_issued_partial_agen, issue_slots[14].out_uop.iw_issued_partial_agen connect issue_slots[12].in_uop.bits.iw_issued, issue_slots[14].out_uop.iw_issued connect issue_slots[12].in_uop.bits.fu_code[0], issue_slots[14].out_uop.fu_code[0] connect issue_slots[12].in_uop.bits.fu_code[1], issue_slots[14].out_uop.fu_code[1] connect issue_slots[12].in_uop.bits.fu_code[2], issue_slots[14].out_uop.fu_code[2] connect issue_slots[12].in_uop.bits.fu_code[3], issue_slots[14].out_uop.fu_code[3] connect issue_slots[12].in_uop.bits.fu_code[4], issue_slots[14].out_uop.fu_code[4] connect issue_slots[12].in_uop.bits.fu_code[5], issue_slots[14].out_uop.fu_code[5] connect issue_slots[12].in_uop.bits.fu_code[6], issue_slots[14].out_uop.fu_code[6] connect issue_slots[12].in_uop.bits.fu_code[7], issue_slots[14].out_uop.fu_code[7] connect issue_slots[12].in_uop.bits.fu_code[8], issue_slots[14].out_uop.fu_code[8] connect issue_slots[12].in_uop.bits.fu_code[9], issue_slots[14].out_uop.fu_code[9] connect issue_slots[12].in_uop.bits.iq_type[0], issue_slots[14].out_uop.iq_type[0] connect issue_slots[12].in_uop.bits.iq_type[1], issue_slots[14].out_uop.iq_type[1] connect issue_slots[12].in_uop.bits.iq_type[2], issue_slots[14].out_uop.iq_type[2] connect issue_slots[12].in_uop.bits.iq_type[3], issue_slots[14].out_uop.iq_type[3] connect issue_slots[12].in_uop.bits.debug_pc, issue_slots[14].out_uop.debug_pc connect issue_slots[12].in_uop.bits.is_rvc, issue_slots[14].out_uop.is_rvc connect issue_slots[12].in_uop.bits.debug_inst, issue_slots[14].out_uop.debug_inst connect issue_slots[12].in_uop.bits.inst, issue_slots[14].out_uop.inst node _T_315 = eq(shamts_oh[15], UInt<3>(0h4)) when _T_315 : connect issue_slots[12].in_uop.valid, issue_slots[15].will_be_valid connect issue_slots[12].in_uop.bits.debug_tsrc, issue_slots[15].out_uop.debug_tsrc connect issue_slots[12].in_uop.bits.debug_fsrc, issue_slots[15].out_uop.debug_fsrc connect issue_slots[12].in_uop.bits.bp_xcpt_if, issue_slots[15].out_uop.bp_xcpt_if connect issue_slots[12].in_uop.bits.bp_debug_if, issue_slots[15].out_uop.bp_debug_if connect issue_slots[12].in_uop.bits.xcpt_ma_if, issue_slots[15].out_uop.xcpt_ma_if connect issue_slots[12].in_uop.bits.xcpt_ae_if, issue_slots[15].out_uop.xcpt_ae_if connect issue_slots[12].in_uop.bits.xcpt_pf_if, issue_slots[15].out_uop.xcpt_pf_if connect issue_slots[12].in_uop.bits.fp_typ, issue_slots[15].out_uop.fp_typ connect issue_slots[12].in_uop.bits.fp_rm, issue_slots[15].out_uop.fp_rm connect issue_slots[12].in_uop.bits.fp_val, issue_slots[15].out_uop.fp_val connect issue_slots[12].in_uop.bits.fcn_op, issue_slots[15].out_uop.fcn_op connect issue_slots[12].in_uop.bits.fcn_dw, issue_slots[15].out_uop.fcn_dw connect issue_slots[12].in_uop.bits.frs3_en, issue_slots[15].out_uop.frs3_en connect issue_slots[12].in_uop.bits.lrs2_rtype, issue_slots[15].out_uop.lrs2_rtype connect issue_slots[12].in_uop.bits.lrs1_rtype, issue_slots[15].out_uop.lrs1_rtype connect issue_slots[12].in_uop.bits.dst_rtype, issue_slots[15].out_uop.dst_rtype connect issue_slots[12].in_uop.bits.lrs3, issue_slots[15].out_uop.lrs3 connect issue_slots[12].in_uop.bits.lrs2, issue_slots[15].out_uop.lrs2 connect issue_slots[12].in_uop.bits.lrs1, issue_slots[15].out_uop.lrs1 connect issue_slots[12].in_uop.bits.ldst, issue_slots[15].out_uop.ldst connect issue_slots[12].in_uop.bits.ldst_is_rs1, issue_slots[15].out_uop.ldst_is_rs1 connect issue_slots[12].in_uop.bits.csr_cmd, issue_slots[15].out_uop.csr_cmd connect issue_slots[12].in_uop.bits.flush_on_commit, issue_slots[15].out_uop.flush_on_commit connect issue_slots[12].in_uop.bits.is_unique, issue_slots[15].out_uop.is_unique connect issue_slots[12].in_uop.bits.uses_stq, issue_slots[15].out_uop.uses_stq connect issue_slots[12].in_uop.bits.uses_ldq, issue_slots[15].out_uop.uses_ldq connect issue_slots[12].in_uop.bits.mem_signed, issue_slots[15].out_uop.mem_signed connect issue_slots[12].in_uop.bits.mem_size, issue_slots[15].out_uop.mem_size connect issue_slots[12].in_uop.bits.mem_cmd, issue_slots[15].out_uop.mem_cmd connect issue_slots[12].in_uop.bits.exc_cause, issue_slots[15].out_uop.exc_cause connect issue_slots[12].in_uop.bits.exception, issue_slots[15].out_uop.exception connect issue_slots[12].in_uop.bits.stale_pdst, issue_slots[15].out_uop.stale_pdst connect issue_slots[12].in_uop.bits.ppred_busy, issue_slots[15].out_uop.ppred_busy connect issue_slots[12].in_uop.bits.prs3_busy, issue_slots[15].out_uop.prs3_busy connect issue_slots[12].in_uop.bits.prs2_busy, issue_slots[15].out_uop.prs2_busy connect issue_slots[12].in_uop.bits.prs1_busy, issue_slots[15].out_uop.prs1_busy connect issue_slots[12].in_uop.bits.ppred, issue_slots[15].out_uop.ppred connect issue_slots[12].in_uop.bits.prs3, issue_slots[15].out_uop.prs3 connect issue_slots[12].in_uop.bits.prs2, issue_slots[15].out_uop.prs2 connect issue_slots[12].in_uop.bits.prs1, issue_slots[15].out_uop.prs1 connect issue_slots[12].in_uop.bits.pdst, issue_slots[15].out_uop.pdst connect issue_slots[12].in_uop.bits.rxq_idx, issue_slots[15].out_uop.rxq_idx connect issue_slots[12].in_uop.bits.stq_idx, issue_slots[15].out_uop.stq_idx connect issue_slots[12].in_uop.bits.ldq_idx, issue_slots[15].out_uop.ldq_idx connect issue_slots[12].in_uop.bits.rob_idx, issue_slots[15].out_uop.rob_idx connect issue_slots[12].in_uop.bits.fp_ctrl.vec, issue_slots[15].out_uop.fp_ctrl.vec connect issue_slots[12].in_uop.bits.fp_ctrl.wflags, issue_slots[15].out_uop.fp_ctrl.wflags connect issue_slots[12].in_uop.bits.fp_ctrl.sqrt, issue_slots[15].out_uop.fp_ctrl.sqrt connect issue_slots[12].in_uop.bits.fp_ctrl.div, issue_slots[15].out_uop.fp_ctrl.div connect issue_slots[12].in_uop.bits.fp_ctrl.fma, issue_slots[15].out_uop.fp_ctrl.fma connect issue_slots[12].in_uop.bits.fp_ctrl.fastpipe, issue_slots[15].out_uop.fp_ctrl.fastpipe connect issue_slots[12].in_uop.bits.fp_ctrl.toint, issue_slots[15].out_uop.fp_ctrl.toint connect issue_slots[12].in_uop.bits.fp_ctrl.fromint, issue_slots[15].out_uop.fp_ctrl.fromint connect issue_slots[12].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[15].out_uop.fp_ctrl.typeTagOut connect issue_slots[12].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[15].out_uop.fp_ctrl.typeTagIn connect issue_slots[12].in_uop.bits.fp_ctrl.swap23, issue_slots[15].out_uop.fp_ctrl.swap23 connect issue_slots[12].in_uop.bits.fp_ctrl.swap12, issue_slots[15].out_uop.fp_ctrl.swap12 connect issue_slots[12].in_uop.bits.fp_ctrl.ren3, issue_slots[15].out_uop.fp_ctrl.ren3 connect issue_slots[12].in_uop.bits.fp_ctrl.ren2, issue_slots[15].out_uop.fp_ctrl.ren2 connect issue_slots[12].in_uop.bits.fp_ctrl.ren1, issue_slots[15].out_uop.fp_ctrl.ren1 connect issue_slots[12].in_uop.bits.fp_ctrl.wen, issue_slots[15].out_uop.fp_ctrl.wen connect issue_slots[12].in_uop.bits.fp_ctrl.ldst, issue_slots[15].out_uop.fp_ctrl.ldst connect issue_slots[12].in_uop.bits.op2_sel, issue_slots[15].out_uop.op2_sel connect issue_slots[12].in_uop.bits.op1_sel, issue_slots[15].out_uop.op1_sel connect issue_slots[12].in_uop.bits.imm_packed, issue_slots[15].out_uop.imm_packed connect issue_slots[12].in_uop.bits.pimm, issue_slots[15].out_uop.pimm connect issue_slots[12].in_uop.bits.imm_sel, issue_slots[15].out_uop.imm_sel connect issue_slots[12].in_uop.bits.imm_rename, issue_slots[15].out_uop.imm_rename connect issue_slots[12].in_uop.bits.taken, issue_slots[15].out_uop.taken connect issue_slots[12].in_uop.bits.pc_lob, issue_slots[15].out_uop.pc_lob connect issue_slots[12].in_uop.bits.edge_inst, issue_slots[15].out_uop.edge_inst connect issue_slots[12].in_uop.bits.ftq_idx, issue_slots[15].out_uop.ftq_idx connect issue_slots[12].in_uop.bits.is_mov, issue_slots[15].out_uop.is_mov connect issue_slots[12].in_uop.bits.is_rocc, issue_slots[15].out_uop.is_rocc connect issue_slots[12].in_uop.bits.is_sys_pc2epc, issue_slots[15].out_uop.is_sys_pc2epc connect issue_slots[12].in_uop.bits.is_eret, issue_slots[15].out_uop.is_eret connect issue_slots[12].in_uop.bits.is_amo, issue_slots[15].out_uop.is_amo connect issue_slots[12].in_uop.bits.is_sfence, issue_slots[15].out_uop.is_sfence connect issue_slots[12].in_uop.bits.is_fencei, issue_slots[15].out_uop.is_fencei connect issue_slots[12].in_uop.bits.is_fence, issue_slots[15].out_uop.is_fence connect issue_slots[12].in_uop.bits.is_sfb, issue_slots[15].out_uop.is_sfb connect issue_slots[12].in_uop.bits.br_type, issue_slots[15].out_uop.br_type connect issue_slots[12].in_uop.bits.br_tag, issue_slots[15].out_uop.br_tag connect issue_slots[12].in_uop.bits.br_mask, issue_slots[15].out_uop.br_mask connect issue_slots[12].in_uop.bits.dis_col_sel, issue_slots[15].out_uop.dis_col_sel connect issue_slots[12].in_uop.bits.iw_p3_bypass_hint, issue_slots[15].out_uop.iw_p3_bypass_hint connect issue_slots[12].in_uop.bits.iw_p2_bypass_hint, issue_slots[15].out_uop.iw_p2_bypass_hint connect issue_slots[12].in_uop.bits.iw_p1_bypass_hint, issue_slots[15].out_uop.iw_p1_bypass_hint connect issue_slots[12].in_uop.bits.iw_p2_speculative_child, issue_slots[15].out_uop.iw_p2_speculative_child connect issue_slots[12].in_uop.bits.iw_p1_speculative_child, issue_slots[15].out_uop.iw_p1_speculative_child connect issue_slots[12].in_uop.bits.iw_issued_partial_dgen, issue_slots[15].out_uop.iw_issued_partial_dgen connect issue_slots[12].in_uop.bits.iw_issued_partial_agen, issue_slots[15].out_uop.iw_issued_partial_agen connect issue_slots[12].in_uop.bits.iw_issued, issue_slots[15].out_uop.iw_issued connect issue_slots[12].in_uop.bits.fu_code[0], issue_slots[15].out_uop.fu_code[0] connect issue_slots[12].in_uop.bits.fu_code[1], issue_slots[15].out_uop.fu_code[1] connect issue_slots[12].in_uop.bits.fu_code[2], issue_slots[15].out_uop.fu_code[2] connect issue_slots[12].in_uop.bits.fu_code[3], issue_slots[15].out_uop.fu_code[3] connect issue_slots[12].in_uop.bits.fu_code[4], issue_slots[15].out_uop.fu_code[4] connect issue_slots[12].in_uop.bits.fu_code[5], issue_slots[15].out_uop.fu_code[5] connect issue_slots[12].in_uop.bits.fu_code[6], issue_slots[15].out_uop.fu_code[6] connect issue_slots[12].in_uop.bits.fu_code[7], issue_slots[15].out_uop.fu_code[7] connect issue_slots[12].in_uop.bits.fu_code[8], issue_slots[15].out_uop.fu_code[8] connect issue_slots[12].in_uop.bits.fu_code[9], issue_slots[15].out_uop.fu_code[9] connect issue_slots[12].in_uop.bits.iq_type[0], issue_slots[15].out_uop.iq_type[0] connect issue_slots[12].in_uop.bits.iq_type[1], issue_slots[15].out_uop.iq_type[1] connect issue_slots[12].in_uop.bits.iq_type[2], issue_slots[15].out_uop.iq_type[2] connect issue_slots[12].in_uop.bits.iq_type[3], issue_slots[15].out_uop.iq_type[3] connect issue_slots[12].in_uop.bits.debug_pc, issue_slots[15].out_uop.debug_pc connect issue_slots[12].in_uop.bits.is_rvc, issue_slots[15].out_uop.is_rvc connect issue_slots[12].in_uop.bits.debug_inst, issue_slots[15].out_uop.debug_inst connect issue_slots[12].in_uop.bits.inst, issue_slots[15].out_uop.inst node _issue_slots_12_clear_T = neq(shamts_oh[12], UInt<1>(0h0)) connect issue_slots[12].clear, _issue_slots_12_clear_T connect issue_slots[13].in_uop.valid, UInt<1>(0h0) connect issue_slots[13].in_uop.bits.debug_tsrc, issue_slots[14].out_uop.debug_tsrc connect issue_slots[13].in_uop.bits.debug_fsrc, issue_slots[14].out_uop.debug_fsrc connect issue_slots[13].in_uop.bits.bp_xcpt_if, issue_slots[14].out_uop.bp_xcpt_if connect issue_slots[13].in_uop.bits.bp_debug_if, issue_slots[14].out_uop.bp_debug_if connect issue_slots[13].in_uop.bits.xcpt_ma_if, issue_slots[14].out_uop.xcpt_ma_if connect issue_slots[13].in_uop.bits.xcpt_ae_if, issue_slots[14].out_uop.xcpt_ae_if connect issue_slots[13].in_uop.bits.xcpt_pf_if, issue_slots[14].out_uop.xcpt_pf_if connect issue_slots[13].in_uop.bits.fp_typ, issue_slots[14].out_uop.fp_typ connect issue_slots[13].in_uop.bits.fp_rm, issue_slots[14].out_uop.fp_rm connect issue_slots[13].in_uop.bits.fp_val, issue_slots[14].out_uop.fp_val connect issue_slots[13].in_uop.bits.fcn_op, issue_slots[14].out_uop.fcn_op connect issue_slots[13].in_uop.bits.fcn_dw, issue_slots[14].out_uop.fcn_dw connect issue_slots[13].in_uop.bits.frs3_en, issue_slots[14].out_uop.frs3_en connect issue_slots[13].in_uop.bits.lrs2_rtype, issue_slots[14].out_uop.lrs2_rtype connect issue_slots[13].in_uop.bits.lrs1_rtype, issue_slots[14].out_uop.lrs1_rtype connect issue_slots[13].in_uop.bits.dst_rtype, issue_slots[14].out_uop.dst_rtype connect issue_slots[13].in_uop.bits.lrs3, issue_slots[14].out_uop.lrs3 connect issue_slots[13].in_uop.bits.lrs2, issue_slots[14].out_uop.lrs2 connect issue_slots[13].in_uop.bits.lrs1, issue_slots[14].out_uop.lrs1 connect issue_slots[13].in_uop.bits.ldst, issue_slots[14].out_uop.ldst connect issue_slots[13].in_uop.bits.ldst_is_rs1, issue_slots[14].out_uop.ldst_is_rs1 connect issue_slots[13].in_uop.bits.csr_cmd, issue_slots[14].out_uop.csr_cmd connect issue_slots[13].in_uop.bits.flush_on_commit, issue_slots[14].out_uop.flush_on_commit connect issue_slots[13].in_uop.bits.is_unique, issue_slots[14].out_uop.is_unique connect issue_slots[13].in_uop.bits.uses_stq, issue_slots[14].out_uop.uses_stq connect issue_slots[13].in_uop.bits.uses_ldq, issue_slots[14].out_uop.uses_ldq connect issue_slots[13].in_uop.bits.mem_signed, issue_slots[14].out_uop.mem_signed connect issue_slots[13].in_uop.bits.mem_size, issue_slots[14].out_uop.mem_size connect issue_slots[13].in_uop.bits.mem_cmd, issue_slots[14].out_uop.mem_cmd connect issue_slots[13].in_uop.bits.exc_cause, issue_slots[14].out_uop.exc_cause connect issue_slots[13].in_uop.bits.exception, issue_slots[14].out_uop.exception connect issue_slots[13].in_uop.bits.stale_pdst, issue_slots[14].out_uop.stale_pdst connect issue_slots[13].in_uop.bits.ppred_busy, issue_slots[14].out_uop.ppred_busy connect issue_slots[13].in_uop.bits.prs3_busy, issue_slots[14].out_uop.prs3_busy connect issue_slots[13].in_uop.bits.prs2_busy, issue_slots[14].out_uop.prs2_busy connect issue_slots[13].in_uop.bits.prs1_busy, issue_slots[14].out_uop.prs1_busy connect issue_slots[13].in_uop.bits.ppred, issue_slots[14].out_uop.ppred connect issue_slots[13].in_uop.bits.prs3, issue_slots[14].out_uop.prs3 connect issue_slots[13].in_uop.bits.prs2, issue_slots[14].out_uop.prs2 connect issue_slots[13].in_uop.bits.prs1, issue_slots[14].out_uop.prs1 connect issue_slots[13].in_uop.bits.pdst, issue_slots[14].out_uop.pdst connect issue_slots[13].in_uop.bits.rxq_idx, issue_slots[14].out_uop.rxq_idx connect issue_slots[13].in_uop.bits.stq_idx, issue_slots[14].out_uop.stq_idx connect issue_slots[13].in_uop.bits.ldq_idx, issue_slots[14].out_uop.ldq_idx connect issue_slots[13].in_uop.bits.rob_idx, issue_slots[14].out_uop.rob_idx connect issue_slots[13].in_uop.bits.fp_ctrl.vec, issue_slots[14].out_uop.fp_ctrl.vec connect issue_slots[13].in_uop.bits.fp_ctrl.wflags, issue_slots[14].out_uop.fp_ctrl.wflags connect issue_slots[13].in_uop.bits.fp_ctrl.sqrt, issue_slots[14].out_uop.fp_ctrl.sqrt connect issue_slots[13].in_uop.bits.fp_ctrl.div, issue_slots[14].out_uop.fp_ctrl.div connect issue_slots[13].in_uop.bits.fp_ctrl.fma, issue_slots[14].out_uop.fp_ctrl.fma connect issue_slots[13].in_uop.bits.fp_ctrl.fastpipe, issue_slots[14].out_uop.fp_ctrl.fastpipe connect issue_slots[13].in_uop.bits.fp_ctrl.toint, issue_slots[14].out_uop.fp_ctrl.toint connect issue_slots[13].in_uop.bits.fp_ctrl.fromint, issue_slots[14].out_uop.fp_ctrl.fromint connect issue_slots[13].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[14].out_uop.fp_ctrl.typeTagOut connect issue_slots[13].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[14].out_uop.fp_ctrl.typeTagIn connect issue_slots[13].in_uop.bits.fp_ctrl.swap23, issue_slots[14].out_uop.fp_ctrl.swap23 connect issue_slots[13].in_uop.bits.fp_ctrl.swap12, issue_slots[14].out_uop.fp_ctrl.swap12 connect issue_slots[13].in_uop.bits.fp_ctrl.ren3, issue_slots[14].out_uop.fp_ctrl.ren3 connect issue_slots[13].in_uop.bits.fp_ctrl.ren2, issue_slots[14].out_uop.fp_ctrl.ren2 connect issue_slots[13].in_uop.bits.fp_ctrl.ren1, issue_slots[14].out_uop.fp_ctrl.ren1 connect issue_slots[13].in_uop.bits.fp_ctrl.wen, issue_slots[14].out_uop.fp_ctrl.wen connect issue_slots[13].in_uop.bits.fp_ctrl.ldst, issue_slots[14].out_uop.fp_ctrl.ldst connect issue_slots[13].in_uop.bits.op2_sel, issue_slots[14].out_uop.op2_sel connect issue_slots[13].in_uop.bits.op1_sel, issue_slots[14].out_uop.op1_sel connect issue_slots[13].in_uop.bits.imm_packed, issue_slots[14].out_uop.imm_packed connect issue_slots[13].in_uop.bits.pimm, issue_slots[14].out_uop.pimm connect issue_slots[13].in_uop.bits.imm_sel, issue_slots[14].out_uop.imm_sel connect issue_slots[13].in_uop.bits.imm_rename, issue_slots[14].out_uop.imm_rename connect issue_slots[13].in_uop.bits.taken, issue_slots[14].out_uop.taken connect issue_slots[13].in_uop.bits.pc_lob, issue_slots[14].out_uop.pc_lob connect issue_slots[13].in_uop.bits.edge_inst, issue_slots[14].out_uop.edge_inst connect issue_slots[13].in_uop.bits.ftq_idx, issue_slots[14].out_uop.ftq_idx connect issue_slots[13].in_uop.bits.is_mov, issue_slots[14].out_uop.is_mov connect issue_slots[13].in_uop.bits.is_rocc, issue_slots[14].out_uop.is_rocc connect issue_slots[13].in_uop.bits.is_sys_pc2epc, issue_slots[14].out_uop.is_sys_pc2epc connect issue_slots[13].in_uop.bits.is_eret, issue_slots[14].out_uop.is_eret connect issue_slots[13].in_uop.bits.is_amo, issue_slots[14].out_uop.is_amo connect issue_slots[13].in_uop.bits.is_sfence, issue_slots[14].out_uop.is_sfence connect issue_slots[13].in_uop.bits.is_fencei, issue_slots[14].out_uop.is_fencei connect issue_slots[13].in_uop.bits.is_fence, issue_slots[14].out_uop.is_fence connect issue_slots[13].in_uop.bits.is_sfb, issue_slots[14].out_uop.is_sfb connect issue_slots[13].in_uop.bits.br_type, issue_slots[14].out_uop.br_type connect issue_slots[13].in_uop.bits.br_tag, issue_slots[14].out_uop.br_tag connect issue_slots[13].in_uop.bits.br_mask, issue_slots[14].out_uop.br_mask connect issue_slots[13].in_uop.bits.dis_col_sel, issue_slots[14].out_uop.dis_col_sel connect issue_slots[13].in_uop.bits.iw_p3_bypass_hint, issue_slots[14].out_uop.iw_p3_bypass_hint connect issue_slots[13].in_uop.bits.iw_p2_bypass_hint, issue_slots[14].out_uop.iw_p2_bypass_hint connect issue_slots[13].in_uop.bits.iw_p1_bypass_hint, issue_slots[14].out_uop.iw_p1_bypass_hint connect issue_slots[13].in_uop.bits.iw_p2_speculative_child, issue_slots[14].out_uop.iw_p2_speculative_child connect issue_slots[13].in_uop.bits.iw_p1_speculative_child, issue_slots[14].out_uop.iw_p1_speculative_child connect issue_slots[13].in_uop.bits.iw_issued_partial_dgen, issue_slots[14].out_uop.iw_issued_partial_dgen connect issue_slots[13].in_uop.bits.iw_issued_partial_agen, issue_slots[14].out_uop.iw_issued_partial_agen connect issue_slots[13].in_uop.bits.iw_issued, issue_slots[14].out_uop.iw_issued connect issue_slots[13].in_uop.bits.fu_code[0], issue_slots[14].out_uop.fu_code[0] connect issue_slots[13].in_uop.bits.fu_code[1], issue_slots[14].out_uop.fu_code[1] connect issue_slots[13].in_uop.bits.fu_code[2], issue_slots[14].out_uop.fu_code[2] connect issue_slots[13].in_uop.bits.fu_code[3], issue_slots[14].out_uop.fu_code[3] connect issue_slots[13].in_uop.bits.fu_code[4], issue_slots[14].out_uop.fu_code[4] connect issue_slots[13].in_uop.bits.fu_code[5], issue_slots[14].out_uop.fu_code[5] connect issue_slots[13].in_uop.bits.fu_code[6], issue_slots[14].out_uop.fu_code[6] connect issue_slots[13].in_uop.bits.fu_code[7], issue_slots[14].out_uop.fu_code[7] connect issue_slots[13].in_uop.bits.fu_code[8], issue_slots[14].out_uop.fu_code[8] connect issue_slots[13].in_uop.bits.fu_code[9], issue_slots[14].out_uop.fu_code[9] connect issue_slots[13].in_uop.bits.iq_type[0], issue_slots[14].out_uop.iq_type[0] connect issue_slots[13].in_uop.bits.iq_type[1], issue_slots[14].out_uop.iq_type[1] connect issue_slots[13].in_uop.bits.iq_type[2], issue_slots[14].out_uop.iq_type[2] connect issue_slots[13].in_uop.bits.iq_type[3], issue_slots[14].out_uop.iq_type[3] connect issue_slots[13].in_uop.bits.debug_pc, issue_slots[14].out_uop.debug_pc connect issue_slots[13].in_uop.bits.is_rvc, issue_slots[14].out_uop.is_rvc connect issue_slots[13].in_uop.bits.debug_inst, issue_slots[14].out_uop.debug_inst connect issue_slots[13].in_uop.bits.inst, issue_slots[14].out_uop.inst node _T_316 = eq(shamts_oh[14], UInt<1>(0h1)) when _T_316 : connect issue_slots[13].in_uop.valid, issue_slots[14].will_be_valid connect issue_slots[13].in_uop.bits.debug_tsrc, issue_slots[14].out_uop.debug_tsrc connect issue_slots[13].in_uop.bits.debug_fsrc, issue_slots[14].out_uop.debug_fsrc connect issue_slots[13].in_uop.bits.bp_xcpt_if, issue_slots[14].out_uop.bp_xcpt_if connect issue_slots[13].in_uop.bits.bp_debug_if, issue_slots[14].out_uop.bp_debug_if connect issue_slots[13].in_uop.bits.xcpt_ma_if, issue_slots[14].out_uop.xcpt_ma_if connect issue_slots[13].in_uop.bits.xcpt_ae_if, issue_slots[14].out_uop.xcpt_ae_if connect issue_slots[13].in_uop.bits.xcpt_pf_if, issue_slots[14].out_uop.xcpt_pf_if connect issue_slots[13].in_uop.bits.fp_typ, issue_slots[14].out_uop.fp_typ connect issue_slots[13].in_uop.bits.fp_rm, issue_slots[14].out_uop.fp_rm connect issue_slots[13].in_uop.bits.fp_val, issue_slots[14].out_uop.fp_val connect issue_slots[13].in_uop.bits.fcn_op, issue_slots[14].out_uop.fcn_op connect issue_slots[13].in_uop.bits.fcn_dw, issue_slots[14].out_uop.fcn_dw connect issue_slots[13].in_uop.bits.frs3_en, issue_slots[14].out_uop.frs3_en connect issue_slots[13].in_uop.bits.lrs2_rtype, issue_slots[14].out_uop.lrs2_rtype connect issue_slots[13].in_uop.bits.lrs1_rtype, issue_slots[14].out_uop.lrs1_rtype connect issue_slots[13].in_uop.bits.dst_rtype, issue_slots[14].out_uop.dst_rtype connect issue_slots[13].in_uop.bits.lrs3, issue_slots[14].out_uop.lrs3 connect issue_slots[13].in_uop.bits.lrs2, issue_slots[14].out_uop.lrs2 connect issue_slots[13].in_uop.bits.lrs1, issue_slots[14].out_uop.lrs1 connect issue_slots[13].in_uop.bits.ldst, issue_slots[14].out_uop.ldst connect issue_slots[13].in_uop.bits.ldst_is_rs1, issue_slots[14].out_uop.ldst_is_rs1 connect issue_slots[13].in_uop.bits.csr_cmd, issue_slots[14].out_uop.csr_cmd connect issue_slots[13].in_uop.bits.flush_on_commit, issue_slots[14].out_uop.flush_on_commit connect issue_slots[13].in_uop.bits.is_unique, issue_slots[14].out_uop.is_unique connect issue_slots[13].in_uop.bits.uses_stq, issue_slots[14].out_uop.uses_stq connect issue_slots[13].in_uop.bits.uses_ldq, issue_slots[14].out_uop.uses_ldq connect issue_slots[13].in_uop.bits.mem_signed, issue_slots[14].out_uop.mem_signed connect issue_slots[13].in_uop.bits.mem_size, issue_slots[14].out_uop.mem_size connect issue_slots[13].in_uop.bits.mem_cmd, issue_slots[14].out_uop.mem_cmd connect issue_slots[13].in_uop.bits.exc_cause, issue_slots[14].out_uop.exc_cause connect issue_slots[13].in_uop.bits.exception, issue_slots[14].out_uop.exception connect issue_slots[13].in_uop.bits.stale_pdst, issue_slots[14].out_uop.stale_pdst connect issue_slots[13].in_uop.bits.ppred_busy, issue_slots[14].out_uop.ppred_busy connect issue_slots[13].in_uop.bits.prs3_busy, issue_slots[14].out_uop.prs3_busy connect issue_slots[13].in_uop.bits.prs2_busy, issue_slots[14].out_uop.prs2_busy connect issue_slots[13].in_uop.bits.prs1_busy, issue_slots[14].out_uop.prs1_busy connect issue_slots[13].in_uop.bits.ppred, issue_slots[14].out_uop.ppred connect issue_slots[13].in_uop.bits.prs3, issue_slots[14].out_uop.prs3 connect issue_slots[13].in_uop.bits.prs2, issue_slots[14].out_uop.prs2 connect issue_slots[13].in_uop.bits.prs1, issue_slots[14].out_uop.prs1 connect issue_slots[13].in_uop.bits.pdst, issue_slots[14].out_uop.pdst connect issue_slots[13].in_uop.bits.rxq_idx, issue_slots[14].out_uop.rxq_idx connect issue_slots[13].in_uop.bits.stq_idx, issue_slots[14].out_uop.stq_idx connect issue_slots[13].in_uop.bits.ldq_idx, issue_slots[14].out_uop.ldq_idx connect issue_slots[13].in_uop.bits.rob_idx, issue_slots[14].out_uop.rob_idx connect issue_slots[13].in_uop.bits.fp_ctrl.vec, issue_slots[14].out_uop.fp_ctrl.vec connect issue_slots[13].in_uop.bits.fp_ctrl.wflags, issue_slots[14].out_uop.fp_ctrl.wflags connect issue_slots[13].in_uop.bits.fp_ctrl.sqrt, issue_slots[14].out_uop.fp_ctrl.sqrt connect issue_slots[13].in_uop.bits.fp_ctrl.div, issue_slots[14].out_uop.fp_ctrl.div connect issue_slots[13].in_uop.bits.fp_ctrl.fma, issue_slots[14].out_uop.fp_ctrl.fma connect issue_slots[13].in_uop.bits.fp_ctrl.fastpipe, issue_slots[14].out_uop.fp_ctrl.fastpipe connect issue_slots[13].in_uop.bits.fp_ctrl.toint, issue_slots[14].out_uop.fp_ctrl.toint connect issue_slots[13].in_uop.bits.fp_ctrl.fromint, issue_slots[14].out_uop.fp_ctrl.fromint connect issue_slots[13].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[14].out_uop.fp_ctrl.typeTagOut connect issue_slots[13].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[14].out_uop.fp_ctrl.typeTagIn connect issue_slots[13].in_uop.bits.fp_ctrl.swap23, issue_slots[14].out_uop.fp_ctrl.swap23 connect issue_slots[13].in_uop.bits.fp_ctrl.swap12, issue_slots[14].out_uop.fp_ctrl.swap12 connect issue_slots[13].in_uop.bits.fp_ctrl.ren3, issue_slots[14].out_uop.fp_ctrl.ren3 connect issue_slots[13].in_uop.bits.fp_ctrl.ren2, issue_slots[14].out_uop.fp_ctrl.ren2 connect issue_slots[13].in_uop.bits.fp_ctrl.ren1, issue_slots[14].out_uop.fp_ctrl.ren1 connect issue_slots[13].in_uop.bits.fp_ctrl.wen, issue_slots[14].out_uop.fp_ctrl.wen connect issue_slots[13].in_uop.bits.fp_ctrl.ldst, issue_slots[14].out_uop.fp_ctrl.ldst connect issue_slots[13].in_uop.bits.op2_sel, issue_slots[14].out_uop.op2_sel connect issue_slots[13].in_uop.bits.op1_sel, issue_slots[14].out_uop.op1_sel connect issue_slots[13].in_uop.bits.imm_packed, issue_slots[14].out_uop.imm_packed connect issue_slots[13].in_uop.bits.pimm, issue_slots[14].out_uop.pimm connect issue_slots[13].in_uop.bits.imm_sel, issue_slots[14].out_uop.imm_sel connect issue_slots[13].in_uop.bits.imm_rename, issue_slots[14].out_uop.imm_rename connect issue_slots[13].in_uop.bits.taken, issue_slots[14].out_uop.taken connect issue_slots[13].in_uop.bits.pc_lob, issue_slots[14].out_uop.pc_lob connect issue_slots[13].in_uop.bits.edge_inst, issue_slots[14].out_uop.edge_inst connect issue_slots[13].in_uop.bits.ftq_idx, issue_slots[14].out_uop.ftq_idx connect issue_slots[13].in_uop.bits.is_mov, issue_slots[14].out_uop.is_mov connect issue_slots[13].in_uop.bits.is_rocc, issue_slots[14].out_uop.is_rocc connect issue_slots[13].in_uop.bits.is_sys_pc2epc, issue_slots[14].out_uop.is_sys_pc2epc connect issue_slots[13].in_uop.bits.is_eret, issue_slots[14].out_uop.is_eret connect issue_slots[13].in_uop.bits.is_amo, issue_slots[14].out_uop.is_amo connect issue_slots[13].in_uop.bits.is_sfence, issue_slots[14].out_uop.is_sfence connect issue_slots[13].in_uop.bits.is_fencei, issue_slots[14].out_uop.is_fencei connect issue_slots[13].in_uop.bits.is_fence, issue_slots[14].out_uop.is_fence connect issue_slots[13].in_uop.bits.is_sfb, issue_slots[14].out_uop.is_sfb connect issue_slots[13].in_uop.bits.br_type, issue_slots[14].out_uop.br_type connect issue_slots[13].in_uop.bits.br_tag, issue_slots[14].out_uop.br_tag connect issue_slots[13].in_uop.bits.br_mask, issue_slots[14].out_uop.br_mask connect issue_slots[13].in_uop.bits.dis_col_sel, issue_slots[14].out_uop.dis_col_sel connect issue_slots[13].in_uop.bits.iw_p3_bypass_hint, issue_slots[14].out_uop.iw_p3_bypass_hint connect issue_slots[13].in_uop.bits.iw_p2_bypass_hint, issue_slots[14].out_uop.iw_p2_bypass_hint connect issue_slots[13].in_uop.bits.iw_p1_bypass_hint, issue_slots[14].out_uop.iw_p1_bypass_hint connect issue_slots[13].in_uop.bits.iw_p2_speculative_child, issue_slots[14].out_uop.iw_p2_speculative_child connect issue_slots[13].in_uop.bits.iw_p1_speculative_child, issue_slots[14].out_uop.iw_p1_speculative_child connect issue_slots[13].in_uop.bits.iw_issued_partial_dgen, issue_slots[14].out_uop.iw_issued_partial_dgen connect issue_slots[13].in_uop.bits.iw_issued_partial_agen, issue_slots[14].out_uop.iw_issued_partial_agen connect issue_slots[13].in_uop.bits.iw_issued, issue_slots[14].out_uop.iw_issued connect issue_slots[13].in_uop.bits.fu_code[0], issue_slots[14].out_uop.fu_code[0] connect issue_slots[13].in_uop.bits.fu_code[1], issue_slots[14].out_uop.fu_code[1] connect issue_slots[13].in_uop.bits.fu_code[2], issue_slots[14].out_uop.fu_code[2] connect issue_slots[13].in_uop.bits.fu_code[3], issue_slots[14].out_uop.fu_code[3] connect issue_slots[13].in_uop.bits.fu_code[4], issue_slots[14].out_uop.fu_code[4] connect issue_slots[13].in_uop.bits.fu_code[5], issue_slots[14].out_uop.fu_code[5] connect issue_slots[13].in_uop.bits.fu_code[6], issue_slots[14].out_uop.fu_code[6] connect issue_slots[13].in_uop.bits.fu_code[7], issue_slots[14].out_uop.fu_code[7] connect issue_slots[13].in_uop.bits.fu_code[8], issue_slots[14].out_uop.fu_code[8] connect issue_slots[13].in_uop.bits.fu_code[9], issue_slots[14].out_uop.fu_code[9] connect issue_slots[13].in_uop.bits.iq_type[0], issue_slots[14].out_uop.iq_type[0] connect issue_slots[13].in_uop.bits.iq_type[1], issue_slots[14].out_uop.iq_type[1] connect issue_slots[13].in_uop.bits.iq_type[2], issue_slots[14].out_uop.iq_type[2] connect issue_slots[13].in_uop.bits.iq_type[3], issue_slots[14].out_uop.iq_type[3] connect issue_slots[13].in_uop.bits.debug_pc, issue_slots[14].out_uop.debug_pc connect issue_slots[13].in_uop.bits.is_rvc, issue_slots[14].out_uop.is_rvc connect issue_slots[13].in_uop.bits.debug_inst, issue_slots[14].out_uop.debug_inst connect issue_slots[13].in_uop.bits.inst, issue_slots[14].out_uop.inst node _T_317 = eq(shamts_oh[15], UInt<2>(0h2)) when _T_317 : connect issue_slots[13].in_uop.valid, issue_slots[15].will_be_valid connect issue_slots[13].in_uop.bits.debug_tsrc, issue_slots[15].out_uop.debug_tsrc connect issue_slots[13].in_uop.bits.debug_fsrc, issue_slots[15].out_uop.debug_fsrc connect issue_slots[13].in_uop.bits.bp_xcpt_if, issue_slots[15].out_uop.bp_xcpt_if connect issue_slots[13].in_uop.bits.bp_debug_if, issue_slots[15].out_uop.bp_debug_if connect issue_slots[13].in_uop.bits.xcpt_ma_if, issue_slots[15].out_uop.xcpt_ma_if connect issue_slots[13].in_uop.bits.xcpt_ae_if, issue_slots[15].out_uop.xcpt_ae_if connect issue_slots[13].in_uop.bits.xcpt_pf_if, issue_slots[15].out_uop.xcpt_pf_if connect issue_slots[13].in_uop.bits.fp_typ, issue_slots[15].out_uop.fp_typ connect issue_slots[13].in_uop.bits.fp_rm, issue_slots[15].out_uop.fp_rm connect issue_slots[13].in_uop.bits.fp_val, issue_slots[15].out_uop.fp_val connect issue_slots[13].in_uop.bits.fcn_op, issue_slots[15].out_uop.fcn_op connect issue_slots[13].in_uop.bits.fcn_dw, issue_slots[15].out_uop.fcn_dw connect issue_slots[13].in_uop.bits.frs3_en, issue_slots[15].out_uop.frs3_en connect issue_slots[13].in_uop.bits.lrs2_rtype, issue_slots[15].out_uop.lrs2_rtype connect issue_slots[13].in_uop.bits.lrs1_rtype, issue_slots[15].out_uop.lrs1_rtype connect issue_slots[13].in_uop.bits.dst_rtype, issue_slots[15].out_uop.dst_rtype connect issue_slots[13].in_uop.bits.lrs3, issue_slots[15].out_uop.lrs3 connect issue_slots[13].in_uop.bits.lrs2, issue_slots[15].out_uop.lrs2 connect issue_slots[13].in_uop.bits.lrs1, issue_slots[15].out_uop.lrs1 connect issue_slots[13].in_uop.bits.ldst, issue_slots[15].out_uop.ldst connect issue_slots[13].in_uop.bits.ldst_is_rs1, issue_slots[15].out_uop.ldst_is_rs1 connect issue_slots[13].in_uop.bits.csr_cmd, issue_slots[15].out_uop.csr_cmd connect issue_slots[13].in_uop.bits.flush_on_commit, issue_slots[15].out_uop.flush_on_commit connect issue_slots[13].in_uop.bits.is_unique, issue_slots[15].out_uop.is_unique connect issue_slots[13].in_uop.bits.uses_stq, issue_slots[15].out_uop.uses_stq connect issue_slots[13].in_uop.bits.uses_ldq, issue_slots[15].out_uop.uses_ldq connect issue_slots[13].in_uop.bits.mem_signed, issue_slots[15].out_uop.mem_signed connect issue_slots[13].in_uop.bits.mem_size, issue_slots[15].out_uop.mem_size connect issue_slots[13].in_uop.bits.mem_cmd, issue_slots[15].out_uop.mem_cmd connect issue_slots[13].in_uop.bits.exc_cause, issue_slots[15].out_uop.exc_cause connect issue_slots[13].in_uop.bits.exception, issue_slots[15].out_uop.exception connect issue_slots[13].in_uop.bits.stale_pdst, issue_slots[15].out_uop.stale_pdst connect issue_slots[13].in_uop.bits.ppred_busy, issue_slots[15].out_uop.ppred_busy connect issue_slots[13].in_uop.bits.prs3_busy, issue_slots[15].out_uop.prs3_busy connect issue_slots[13].in_uop.bits.prs2_busy, issue_slots[15].out_uop.prs2_busy connect issue_slots[13].in_uop.bits.prs1_busy, issue_slots[15].out_uop.prs1_busy connect issue_slots[13].in_uop.bits.ppred, issue_slots[15].out_uop.ppred connect issue_slots[13].in_uop.bits.prs3, issue_slots[15].out_uop.prs3 connect issue_slots[13].in_uop.bits.prs2, issue_slots[15].out_uop.prs2 connect issue_slots[13].in_uop.bits.prs1, issue_slots[15].out_uop.prs1 connect issue_slots[13].in_uop.bits.pdst, issue_slots[15].out_uop.pdst connect issue_slots[13].in_uop.bits.rxq_idx, issue_slots[15].out_uop.rxq_idx connect issue_slots[13].in_uop.bits.stq_idx, issue_slots[15].out_uop.stq_idx connect issue_slots[13].in_uop.bits.ldq_idx, issue_slots[15].out_uop.ldq_idx connect issue_slots[13].in_uop.bits.rob_idx, issue_slots[15].out_uop.rob_idx connect issue_slots[13].in_uop.bits.fp_ctrl.vec, issue_slots[15].out_uop.fp_ctrl.vec connect issue_slots[13].in_uop.bits.fp_ctrl.wflags, issue_slots[15].out_uop.fp_ctrl.wflags connect issue_slots[13].in_uop.bits.fp_ctrl.sqrt, issue_slots[15].out_uop.fp_ctrl.sqrt connect issue_slots[13].in_uop.bits.fp_ctrl.div, issue_slots[15].out_uop.fp_ctrl.div connect issue_slots[13].in_uop.bits.fp_ctrl.fma, issue_slots[15].out_uop.fp_ctrl.fma connect issue_slots[13].in_uop.bits.fp_ctrl.fastpipe, issue_slots[15].out_uop.fp_ctrl.fastpipe connect issue_slots[13].in_uop.bits.fp_ctrl.toint, issue_slots[15].out_uop.fp_ctrl.toint connect issue_slots[13].in_uop.bits.fp_ctrl.fromint, issue_slots[15].out_uop.fp_ctrl.fromint connect issue_slots[13].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[15].out_uop.fp_ctrl.typeTagOut connect issue_slots[13].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[15].out_uop.fp_ctrl.typeTagIn connect issue_slots[13].in_uop.bits.fp_ctrl.swap23, issue_slots[15].out_uop.fp_ctrl.swap23 connect issue_slots[13].in_uop.bits.fp_ctrl.swap12, issue_slots[15].out_uop.fp_ctrl.swap12 connect issue_slots[13].in_uop.bits.fp_ctrl.ren3, issue_slots[15].out_uop.fp_ctrl.ren3 connect issue_slots[13].in_uop.bits.fp_ctrl.ren2, issue_slots[15].out_uop.fp_ctrl.ren2 connect issue_slots[13].in_uop.bits.fp_ctrl.ren1, issue_slots[15].out_uop.fp_ctrl.ren1 connect issue_slots[13].in_uop.bits.fp_ctrl.wen, issue_slots[15].out_uop.fp_ctrl.wen connect issue_slots[13].in_uop.bits.fp_ctrl.ldst, issue_slots[15].out_uop.fp_ctrl.ldst connect issue_slots[13].in_uop.bits.op2_sel, issue_slots[15].out_uop.op2_sel connect issue_slots[13].in_uop.bits.op1_sel, issue_slots[15].out_uop.op1_sel connect issue_slots[13].in_uop.bits.imm_packed, issue_slots[15].out_uop.imm_packed connect issue_slots[13].in_uop.bits.pimm, issue_slots[15].out_uop.pimm connect issue_slots[13].in_uop.bits.imm_sel, issue_slots[15].out_uop.imm_sel connect issue_slots[13].in_uop.bits.imm_rename, issue_slots[15].out_uop.imm_rename connect issue_slots[13].in_uop.bits.taken, issue_slots[15].out_uop.taken connect issue_slots[13].in_uop.bits.pc_lob, issue_slots[15].out_uop.pc_lob connect issue_slots[13].in_uop.bits.edge_inst, issue_slots[15].out_uop.edge_inst connect issue_slots[13].in_uop.bits.ftq_idx, issue_slots[15].out_uop.ftq_idx connect issue_slots[13].in_uop.bits.is_mov, issue_slots[15].out_uop.is_mov connect issue_slots[13].in_uop.bits.is_rocc, issue_slots[15].out_uop.is_rocc connect issue_slots[13].in_uop.bits.is_sys_pc2epc, issue_slots[15].out_uop.is_sys_pc2epc connect issue_slots[13].in_uop.bits.is_eret, issue_slots[15].out_uop.is_eret connect issue_slots[13].in_uop.bits.is_amo, issue_slots[15].out_uop.is_amo connect issue_slots[13].in_uop.bits.is_sfence, issue_slots[15].out_uop.is_sfence connect issue_slots[13].in_uop.bits.is_fencei, issue_slots[15].out_uop.is_fencei connect issue_slots[13].in_uop.bits.is_fence, issue_slots[15].out_uop.is_fence connect issue_slots[13].in_uop.bits.is_sfb, issue_slots[15].out_uop.is_sfb connect issue_slots[13].in_uop.bits.br_type, issue_slots[15].out_uop.br_type connect issue_slots[13].in_uop.bits.br_tag, issue_slots[15].out_uop.br_tag connect issue_slots[13].in_uop.bits.br_mask, issue_slots[15].out_uop.br_mask connect issue_slots[13].in_uop.bits.dis_col_sel, issue_slots[15].out_uop.dis_col_sel connect issue_slots[13].in_uop.bits.iw_p3_bypass_hint, issue_slots[15].out_uop.iw_p3_bypass_hint connect issue_slots[13].in_uop.bits.iw_p2_bypass_hint, issue_slots[15].out_uop.iw_p2_bypass_hint connect issue_slots[13].in_uop.bits.iw_p1_bypass_hint, issue_slots[15].out_uop.iw_p1_bypass_hint connect issue_slots[13].in_uop.bits.iw_p2_speculative_child, issue_slots[15].out_uop.iw_p2_speculative_child connect issue_slots[13].in_uop.bits.iw_p1_speculative_child, issue_slots[15].out_uop.iw_p1_speculative_child connect issue_slots[13].in_uop.bits.iw_issued_partial_dgen, issue_slots[15].out_uop.iw_issued_partial_dgen connect issue_slots[13].in_uop.bits.iw_issued_partial_agen, issue_slots[15].out_uop.iw_issued_partial_agen connect issue_slots[13].in_uop.bits.iw_issued, issue_slots[15].out_uop.iw_issued connect issue_slots[13].in_uop.bits.fu_code[0], issue_slots[15].out_uop.fu_code[0] connect issue_slots[13].in_uop.bits.fu_code[1], issue_slots[15].out_uop.fu_code[1] connect issue_slots[13].in_uop.bits.fu_code[2], issue_slots[15].out_uop.fu_code[2] connect issue_slots[13].in_uop.bits.fu_code[3], issue_slots[15].out_uop.fu_code[3] connect issue_slots[13].in_uop.bits.fu_code[4], issue_slots[15].out_uop.fu_code[4] connect issue_slots[13].in_uop.bits.fu_code[5], issue_slots[15].out_uop.fu_code[5] connect issue_slots[13].in_uop.bits.fu_code[6], issue_slots[15].out_uop.fu_code[6] connect issue_slots[13].in_uop.bits.fu_code[7], issue_slots[15].out_uop.fu_code[7] connect issue_slots[13].in_uop.bits.fu_code[8], issue_slots[15].out_uop.fu_code[8] connect issue_slots[13].in_uop.bits.fu_code[9], issue_slots[15].out_uop.fu_code[9] connect issue_slots[13].in_uop.bits.iq_type[0], issue_slots[15].out_uop.iq_type[0] connect issue_slots[13].in_uop.bits.iq_type[1], issue_slots[15].out_uop.iq_type[1] connect issue_slots[13].in_uop.bits.iq_type[2], issue_slots[15].out_uop.iq_type[2] connect issue_slots[13].in_uop.bits.iq_type[3], issue_slots[15].out_uop.iq_type[3] connect issue_slots[13].in_uop.bits.debug_pc, issue_slots[15].out_uop.debug_pc connect issue_slots[13].in_uop.bits.is_rvc, issue_slots[15].out_uop.is_rvc connect issue_slots[13].in_uop.bits.debug_inst, issue_slots[15].out_uop.debug_inst connect issue_slots[13].in_uop.bits.inst, issue_slots[15].out_uop.inst node _T_318 = eq(shamts_oh[16], UInt<3>(0h4)) when _T_318 : connect issue_slots[13].in_uop.valid, will_be_valid_16 connect issue_slots[13].in_uop.bits.debug_tsrc, _WIRE.debug_tsrc connect issue_slots[13].in_uop.bits.debug_fsrc, _WIRE.debug_fsrc connect issue_slots[13].in_uop.bits.bp_xcpt_if, _WIRE.bp_xcpt_if connect issue_slots[13].in_uop.bits.bp_debug_if, _WIRE.bp_debug_if connect issue_slots[13].in_uop.bits.xcpt_ma_if, _WIRE.xcpt_ma_if connect issue_slots[13].in_uop.bits.xcpt_ae_if, _WIRE.xcpt_ae_if connect issue_slots[13].in_uop.bits.xcpt_pf_if, _WIRE.xcpt_pf_if connect issue_slots[13].in_uop.bits.fp_typ, _WIRE.fp_typ connect issue_slots[13].in_uop.bits.fp_rm, _WIRE.fp_rm connect issue_slots[13].in_uop.bits.fp_val, _WIRE.fp_val connect issue_slots[13].in_uop.bits.fcn_op, _WIRE.fcn_op connect issue_slots[13].in_uop.bits.fcn_dw, _WIRE.fcn_dw connect issue_slots[13].in_uop.bits.frs3_en, _WIRE.frs3_en connect issue_slots[13].in_uop.bits.lrs2_rtype, _WIRE.lrs2_rtype connect issue_slots[13].in_uop.bits.lrs1_rtype, _WIRE.lrs1_rtype connect issue_slots[13].in_uop.bits.dst_rtype, _WIRE.dst_rtype connect issue_slots[13].in_uop.bits.lrs3, _WIRE.lrs3 connect issue_slots[13].in_uop.bits.lrs2, _WIRE.lrs2 connect issue_slots[13].in_uop.bits.lrs1, _WIRE.lrs1 connect issue_slots[13].in_uop.bits.ldst, _WIRE.ldst connect issue_slots[13].in_uop.bits.ldst_is_rs1, _WIRE.ldst_is_rs1 connect issue_slots[13].in_uop.bits.csr_cmd, _WIRE.csr_cmd connect issue_slots[13].in_uop.bits.flush_on_commit, _WIRE.flush_on_commit connect issue_slots[13].in_uop.bits.is_unique, _WIRE.is_unique connect issue_slots[13].in_uop.bits.uses_stq, _WIRE.uses_stq connect issue_slots[13].in_uop.bits.uses_ldq, _WIRE.uses_ldq connect issue_slots[13].in_uop.bits.mem_signed, _WIRE.mem_signed connect issue_slots[13].in_uop.bits.mem_size, _WIRE.mem_size connect issue_slots[13].in_uop.bits.mem_cmd, _WIRE.mem_cmd connect issue_slots[13].in_uop.bits.exc_cause, _WIRE.exc_cause connect issue_slots[13].in_uop.bits.exception, _WIRE.exception connect issue_slots[13].in_uop.bits.stale_pdst, _WIRE.stale_pdst connect issue_slots[13].in_uop.bits.ppred_busy, _WIRE.ppred_busy connect issue_slots[13].in_uop.bits.prs3_busy, _WIRE.prs3_busy connect issue_slots[13].in_uop.bits.prs2_busy, _WIRE.prs2_busy connect issue_slots[13].in_uop.bits.prs1_busy, _WIRE.prs1_busy connect issue_slots[13].in_uop.bits.ppred, _WIRE.ppred connect issue_slots[13].in_uop.bits.prs3, _WIRE.prs3 connect issue_slots[13].in_uop.bits.prs2, _WIRE.prs2 connect issue_slots[13].in_uop.bits.prs1, _WIRE.prs1 connect issue_slots[13].in_uop.bits.pdst, _WIRE.pdst connect issue_slots[13].in_uop.bits.rxq_idx, _WIRE.rxq_idx connect issue_slots[13].in_uop.bits.stq_idx, _WIRE.stq_idx connect issue_slots[13].in_uop.bits.ldq_idx, _WIRE.ldq_idx connect issue_slots[13].in_uop.bits.rob_idx, _WIRE.rob_idx connect issue_slots[13].in_uop.bits.fp_ctrl.vec, _WIRE.fp_ctrl.vec connect issue_slots[13].in_uop.bits.fp_ctrl.wflags, _WIRE.fp_ctrl.wflags connect issue_slots[13].in_uop.bits.fp_ctrl.sqrt, _WIRE.fp_ctrl.sqrt connect issue_slots[13].in_uop.bits.fp_ctrl.div, _WIRE.fp_ctrl.div connect issue_slots[13].in_uop.bits.fp_ctrl.fma, _WIRE.fp_ctrl.fma connect issue_slots[13].in_uop.bits.fp_ctrl.fastpipe, _WIRE.fp_ctrl.fastpipe connect issue_slots[13].in_uop.bits.fp_ctrl.toint, _WIRE.fp_ctrl.toint connect issue_slots[13].in_uop.bits.fp_ctrl.fromint, _WIRE.fp_ctrl.fromint connect issue_slots[13].in_uop.bits.fp_ctrl.typeTagOut, _WIRE.fp_ctrl.typeTagOut connect issue_slots[13].in_uop.bits.fp_ctrl.typeTagIn, _WIRE.fp_ctrl.typeTagIn connect issue_slots[13].in_uop.bits.fp_ctrl.swap23, _WIRE.fp_ctrl.swap23 connect issue_slots[13].in_uop.bits.fp_ctrl.swap12, _WIRE.fp_ctrl.swap12 connect issue_slots[13].in_uop.bits.fp_ctrl.ren3, _WIRE.fp_ctrl.ren3 connect issue_slots[13].in_uop.bits.fp_ctrl.ren2, _WIRE.fp_ctrl.ren2 connect issue_slots[13].in_uop.bits.fp_ctrl.ren1, _WIRE.fp_ctrl.ren1 connect issue_slots[13].in_uop.bits.fp_ctrl.wen, _WIRE.fp_ctrl.wen connect issue_slots[13].in_uop.bits.fp_ctrl.ldst, _WIRE.fp_ctrl.ldst connect issue_slots[13].in_uop.bits.op2_sel, _WIRE.op2_sel connect issue_slots[13].in_uop.bits.op1_sel, _WIRE.op1_sel connect issue_slots[13].in_uop.bits.imm_packed, _WIRE.imm_packed connect issue_slots[13].in_uop.bits.pimm, _WIRE.pimm connect issue_slots[13].in_uop.bits.imm_sel, _WIRE.imm_sel connect issue_slots[13].in_uop.bits.imm_rename, _WIRE.imm_rename connect issue_slots[13].in_uop.bits.taken, _WIRE.taken connect issue_slots[13].in_uop.bits.pc_lob, _WIRE.pc_lob connect issue_slots[13].in_uop.bits.edge_inst, _WIRE.edge_inst connect issue_slots[13].in_uop.bits.ftq_idx, _WIRE.ftq_idx connect issue_slots[13].in_uop.bits.is_mov, _WIRE.is_mov connect issue_slots[13].in_uop.bits.is_rocc, _WIRE.is_rocc connect issue_slots[13].in_uop.bits.is_sys_pc2epc, _WIRE.is_sys_pc2epc connect issue_slots[13].in_uop.bits.is_eret, _WIRE.is_eret connect issue_slots[13].in_uop.bits.is_amo, _WIRE.is_amo connect issue_slots[13].in_uop.bits.is_sfence, _WIRE.is_sfence connect issue_slots[13].in_uop.bits.is_fencei, _WIRE.is_fencei connect issue_slots[13].in_uop.bits.is_fence, _WIRE.is_fence connect issue_slots[13].in_uop.bits.is_sfb, _WIRE.is_sfb connect issue_slots[13].in_uop.bits.br_type, _WIRE.br_type connect issue_slots[13].in_uop.bits.br_tag, _WIRE.br_tag connect issue_slots[13].in_uop.bits.br_mask, _WIRE.br_mask connect issue_slots[13].in_uop.bits.dis_col_sel, _WIRE.dis_col_sel connect issue_slots[13].in_uop.bits.iw_p3_bypass_hint, _WIRE.iw_p3_bypass_hint connect issue_slots[13].in_uop.bits.iw_p2_bypass_hint, _WIRE.iw_p2_bypass_hint connect issue_slots[13].in_uop.bits.iw_p1_bypass_hint, _WIRE.iw_p1_bypass_hint connect issue_slots[13].in_uop.bits.iw_p2_speculative_child, _WIRE.iw_p2_speculative_child connect issue_slots[13].in_uop.bits.iw_p1_speculative_child, _WIRE.iw_p1_speculative_child connect issue_slots[13].in_uop.bits.iw_issued_partial_dgen, _WIRE.iw_issued_partial_dgen connect issue_slots[13].in_uop.bits.iw_issued_partial_agen, _WIRE.iw_issued_partial_agen connect issue_slots[13].in_uop.bits.iw_issued, _WIRE.iw_issued connect issue_slots[13].in_uop.bits.fu_code[0], _WIRE.fu_code[0] connect issue_slots[13].in_uop.bits.fu_code[1], _WIRE.fu_code[1] connect issue_slots[13].in_uop.bits.fu_code[2], _WIRE.fu_code[2] connect issue_slots[13].in_uop.bits.fu_code[3], _WIRE.fu_code[3] connect issue_slots[13].in_uop.bits.fu_code[4], _WIRE.fu_code[4] connect issue_slots[13].in_uop.bits.fu_code[5], _WIRE.fu_code[5] connect issue_slots[13].in_uop.bits.fu_code[6], _WIRE.fu_code[6] connect issue_slots[13].in_uop.bits.fu_code[7], _WIRE.fu_code[7] connect issue_slots[13].in_uop.bits.fu_code[8], _WIRE.fu_code[8] connect issue_slots[13].in_uop.bits.fu_code[9], _WIRE.fu_code[9] connect issue_slots[13].in_uop.bits.iq_type[0], _WIRE.iq_type[0] connect issue_slots[13].in_uop.bits.iq_type[1], _WIRE.iq_type[1] connect issue_slots[13].in_uop.bits.iq_type[2], _WIRE.iq_type[2] connect issue_slots[13].in_uop.bits.iq_type[3], _WIRE.iq_type[3] connect issue_slots[13].in_uop.bits.debug_pc, _WIRE.debug_pc connect issue_slots[13].in_uop.bits.is_rvc, _WIRE.is_rvc connect issue_slots[13].in_uop.bits.debug_inst, _WIRE.debug_inst connect issue_slots[13].in_uop.bits.inst, _WIRE.inst node _issue_slots_13_clear_T = neq(shamts_oh[13], UInt<1>(0h0)) connect issue_slots[13].clear, _issue_slots_13_clear_T connect issue_slots[14].in_uop.valid, UInt<1>(0h0) connect issue_slots[14].in_uop.bits.debug_tsrc, issue_slots[15].out_uop.debug_tsrc connect issue_slots[14].in_uop.bits.debug_fsrc, issue_slots[15].out_uop.debug_fsrc connect issue_slots[14].in_uop.bits.bp_xcpt_if, issue_slots[15].out_uop.bp_xcpt_if connect issue_slots[14].in_uop.bits.bp_debug_if, issue_slots[15].out_uop.bp_debug_if connect issue_slots[14].in_uop.bits.xcpt_ma_if, issue_slots[15].out_uop.xcpt_ma_if connect issue_slots[14].in_uop.bits.xcpt_ae_if, issue_slots[15].out_uop.xcpt_ae_if connect issue_slots[14].in_uop.bits.xcpt_pf_if, issue_slots[15].out_uop.xcpt_pf_if connect issue_slots[14].in_uop.bits.fp_typ, issue_slots[15].out_uop.fp_typ connect issue_slots[14].in_uop.bits.fp_rm, issue_slots[15].out_uop.fp_rm connect issue_slots[14].in_uop.bits.fp_val, issue_slots[15].out_uop.fp_val connect issue_slots[14].in_uop.bits.fcn_op, issue_slots[15].out_uop.fcn_op connect issue_slots[14].in_uop.bits.fcn_dw, issue_slots[15].out_uop.fcn_dw connect issue_slots[14].in_uop.bits.frs3_en, issue_slots[15].out_uop.frs3_en connect issue_slots[14].in_uop.bits.lrs2_rtype, issue_slots[15].out_uop.lrs2_rtype connect issue_slots[14].in_uop.bits.lrs1_rtype, issue_slots[15].out_uop.lrs1_rtype connect issue_slots[14].in_uop.bits.dst_rtype, issue_slots[15].out_uop.dst_rtype connect issue_slots[14].in_uop.bits.lrs3, issue_slots[15].out_uop.lrs3 connect issue_slots[14].in_uop.bits.lrs2, issue_slots[15].out_uop.lrs2 connect issue_slots[14].in_uop.bits.lrs1, issue_slots[15].out_uop.lrs1 connect issue_slots[14].in_uop.bits.ldst, issue_slots[15].out_uop.ldst connect issue_slots[14].in_uop.bits.ldst_is_rs1, issue_slots[15].out_uop.ldst_is_rs1 connect issue_slots[14].in_uop.bits.csr_cmd, issue_slots[15].out_uop.csr_cmd connect issue_slots[14].in_uop.bits.flush_on_commit, issue_slots[15].out_uop.flush_on_commit connect issue_slots[14].in_uop.bits.is_unique, issue_slots[15].out_uop.is_unique connect issue_slots[14].in_uop.bits.uses_stq, issue_slots[15].out_uop.uses_stq connect issue_slots[14].in_uop.bits.uses_ldq, issue_slots[15].out_uop.uses_ldq connect issue_slots[14].in_uop.bits.mem_signed, issue_slots[15].out_uop.mem_signed connect issue_slots[14].in_uop.bits.mem_size, issue_slots[15].out_uop.mem_size connect issue_slots[14].in_uop.bits.mem_cmd, issue_slots[15].out_uop.mem_cmd connect issue_slots[14].in_uop.bits.exc_cause, issue_slots[15].out_uop.exc_cause connect issue_slots[14].in_uop.bits.exception, issue_slots[15].out_uop.exception connect issue_slots[14].in_uop.bits.stale_pdst, issue_slots[15].out_uop.stale_pdst connect issue_slots[14].in_uop.bits.ppred_busy, issue_slots[15].out_uop.ppred_busy connect issue_slots[14].in_uop.bits.prs3_busy, issue_slots[15].out_uop.prs3_busy connect issue_slots[14].in_uop.bits.prs2_busy, issue_slots[15].out_uop.prs2_busy connect issue_slots[14].in_uop.bits.prs1_busy, issue_slots[15].out_uop.prs1_busy connect issue_slots[14].in_uop.bits.ppred, issue_slots[15].out_uop.ppred connect issue_slots[14].in_uop.bits.prs3, issue_slots[15].out_uop.prs3 connect issue_slots[14].in_uop.bits.prs2, issue_slots[15].out_uop.prs2 connect issue_slots[14].in_uop.bits.prs1, issue_slots[15].out_uop.prs1 connect issue_slots[14].in_uop.bits.pdst, issue_slots[15].out_uop.pdst connect issue_slots[14].in_uop.bits.rxq_idx, issue_slots[15].out_uop.rxq_idx connect issue_slots[14].in_uop.bits.stq_idx, issue_slots[15].out_uop.stq_idx connect issue_slots[14].in_uop.bits.ldq_idx, issue_slots[15].out_uop.ldq_idx connect issue_slots[14].in_uop.bits.rob_idx, issue_slots[15].out_uop.rob_idx connect issue_slots[14].in_uop.bits.fp_ctrl.vec, issue_slots[15].out_uop.fp_ctrl.vec connect issue_slots[14].in_uop.bits.fp_ctrl.wflags, issue_slots[15].out_uop.fp_ctrl.wflags connect issue_slots[14].in_uop.bits.fp_ctrl.sqrt, issue_slots[15].out_uop.fp_ctrl.sqrt connect issue_slots[14].in_uop.bits.fp_ctrl.div, issue_slots[15].out_uop.fp_ctrl.div connect issue_slots[14].in_uop.bits.fp_ctrl.fma, issue_slots[15].out_uop.fp_ctrl.fma connect issue_slots[14].in_uop.bits.fp_ctrl.fastpipe, issue_slots[15].out_uop.fp_ctrl.fastpipe connect issue_slots[14].in_uop.bits.fp_ctrl.toint, issue_slots[15].out_uop.fp_ctrl.toint connect issue_slots[14].in_uop.bits.fp_ctrl.fromint, issue_slots[15].out_uop.fp_ctrl.fromint connect issue_slots[14].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[15].out_uop.fp_ctrl.typeTagOut connect issue_slots[14].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[15].out_uop.fp_ctrl.typeTagIn connect issue_slots[14].in_uop.bits.fp_ctrl.swap23, issue_slots[15].out_uop.fp_ctrl.swap23 connect issue_slots[14].in_uop.bits.fp_ctrl.swap12, issue_slots[15].out_uop.fp_ctrl.swap12 connect issue_slots[14].in_uop.bits.fp_ctrl.ren3, issue_slots[15].out_uop.fp_ctrl.ren3 connect issue_slots[14].in_uop.bits.fp_ctrl.ren2, issue_slots[15].out_uop.fp_ctrl.ren2 connect issue_slots[14].in_uop.bits.fp_ctrl.ren1, issue_slots[15].out_uop.fp_ctrl.ren1 connect issue_slots[14].in_uop.bits.fp_ctrl.wen, issue_slots[15].out_uop.fp_ctrl.wen connect issue_slots[14].in_uop.bits.fp_ctrl.ldst, issue_slots[15].out_uop.fp_ctrl.ldst connect issue_slots[14].in_uop.bits.op2_sel, issue_slots[15].out_uop.op2_sel connect issue_slots[14].in_uop.bits.op1_sel, issue_slots[15].out_uop.op1_sel connect issue_slots[14].in_uop.bits.imm_packed, issue_slots[15].out_uop.imm_packed connect issue_slots[14].in_uop.bits.pimm, issue_slots[15].out_uop.pimm connect issue_slots[14].in_uop.bits.imm_sel, issue_slots[15].out_uop.imm_sel connect issue_slots[14].in_uop.bits.imm_rename, issue_slots[15].out_uop.imm_rename connect issue_slots[14].in_uop.bits.taken, issue_slots[15].out_uop.taken connect issue_slots[14].in_uop.bits.pc_lob, issue_slots[15].out_uop.pc_lob connect issue_slots[14].in_uop.bits.edge_inst, issue_slots[15].out_uop.edge_inst connect issue_slots[14].in_uop.bits.ftq_idx, issue_slots[15].out_uop.ftq_idx connect issue_slots[14].in_uop.bits.is_mov, issue_slots[15].out_uop.is_mov connect issue_slots[14].in_uop.bits.is_rocc, issue_slots[15].out_uop.is_rocc connect issue_slots[14].in_uop.bits.is_sys_pc2epc, issue_slots[15].out_uop.is_sys_pc2epc connect issue_slots[14].in_uop.bits.is_eret, issue_slots[15].out_uop.is_eret connect issue_slots[14].in_uop.bits.is_amo, issue_slots[15].out_uop.is_amo connect issue_slots[14].in_uop.bits.is_sfence, issue_slots[15].out_uop.is_sfence connect issue_slots[14].in_uop.bits.is_fencei, issue_slots[15].out_uop.is_fencei connect issue_slots[14].in_uop.bits.is_fence, issue_slots[15].out_uop.is_fence connect issue_slots[14].in_uop.bits.is_sfb, issue_slots[15].out_uop.is_sfb connect issue_slots[14].in_uop.bits.br_type, issue_slots[15].out_uop.br_type connect issue_slots[14].in_uop.bits.br_tag, issue_slots[15].out_uop.br_tag connect issue_slots[14].in_uop.bits.br_mask, issue_slots[15].out_uop.br_mask connect issue_slots[14].in_uop.bits.dis_col_sel, issue_slots[15].out_uop.dis_col_sel connect issue_slots[14].in_uop.bits.iw_p3_bypass_hint, issue_slots[15].out_uop.iw_p3_bypass_hint connect issue_slots[14].in_uop.bits.iw_p2_bypass_hint, issue_slots[15].out_uop.iw_p2_bypass_hint connect issue_slots[14].in_uop.bits.iw_p1_bypass_hint, issue_slots[15].out_uop.iw_p1_bypass_hint connect issue_slots[14].in_uop.bits.iw_p2_speculative_child, issue_slots[15].out_uop.iw_p2_speculative_child connect issue_slots[14].in_uop.bits.iw_p1_speculative_child, issue_slots[15].out_uop.iw_p1_speculative_child connect issue_slots[14].in_uop.bits.iw_issued_partial_dgen, issue_slots[15].out_uop.iw_issued_partial_dgen connect issue_slots[14].in_uop.bits.iw_issued_partial_agen, issue_slots[15].out_uop.iw_issued_partial_agen connect issue_slots[14].in_uop.bits.iw_issued, issue_slots[15].out_uop.iw_issued connect issue_slots[14].in_uop.bits.fu_code[0], issue_slots[15].out_uop.fu_code[0] connect issue_slots[14].in_uop.bits.fu_code[1], issue_slots[15].out_uop.fu_code[1] connect issue_slots[14].in_uop.bits.fu_code[2], issue_slots[15].out_uop.fu_code[2] connect issue_slots[14].in_uop.bits.fu_code[3], issue_slots[15].out_uop.fu_code[3] connect issue_slots[14].in_uop.bits.fu_code[4], issue_slots[15].out_uop.fu_code[4] connect issue_slots[14].in_uop.bits.fu_code[5], issue_slots[15].out_uop.fu_code[5] connect issue_slots[14].in_uop.bits.fu_code[6], issue_slots[15].out_uop.fu_code[6] connect issue_slots[14].in_uop.bits.fu_code[7], issue_slots[15].out_uop.fu_code[7] connect issue_slots[14].in_uop.bits.fu_code[8], issue_slots[15].out_uop.fu_code[8] connect issue_slots[14].in_uop.bits.fu_code[9], issue_slots[15].out_uop.fu_code[9] connect issue_slots[14].in_uop.bits.iq_type[0], issue_slots[15].out_uop.iq_type[0] connect issue_slots[14].in_uop.bits.iq_type[1], issue_slots[15].out_uop.iq_type[1] connect issue_slots[14].in_uop.bits.iq_type[2], issue_slots[15].out_uop.iq_type[2] connect issue_slots[14].in_uop.bits.iq_type[3], issue_slots[15].out_uop.iq_type[3] connect issue_slots[14].in_uop.bits.debug_pc, issue_slots[15].out_uop.debug_pc connect issue_slots[14].in_uop.bits.is_rvc, issue_slots[15].out_uop.is_rvc connect issue_slots[14].in_uop.bits.debug_inst, issue_slots[15].out_uop.debug_inst connect issue_slots[14].in_uop.bits.inst, issue_slots[15].out_uop.inst node _T_319 = eq(shamts_oh[15], UInt<1>(0h1)) when _T_319 : connect issue_slots[14].in_uop.valid, issue_slots[15].will_be_valid connect issue_slots[14].in_uop.bits.debug_tsrc, issue_slots[15].out_uop.debug_tsrc connect issue_slots[14].in_uop.bits.debug_fsrc, issue_slots[15].out_uop.debug_fsrc connect issue_slots[14].in_uop.bits.bp_xcpt_if, issue_slots[15].out_uop.bp_xcpt_if connect issue_slots[14].in_uop.bits.bp_debug_if, issue_slots[15].out_uop.bp_debug_if connect issue_slots[14].in_uop.bits.xcpt_ma_if, issue_slots[15].out_uop.xcpt_ma_if connect issue_slots[14].in_uop.bits.xcpt_ae_if, issue_slots[15].out_uop.xcpt_ae_if connect issue_slots[14].in_uop.bits.xcpt_pf_if, issue_slots[15].out_uop.xcpt_pf_if connect issue_slots[14].in_uop.bits.fp_typ, issue_slots[15].out_uop.fp_typ connect issue_slots[14].in_uop.bits.fp_rm, issue_slots[15].out_uop.fp_rm connect issue_slots[14].in_uop.bits.fp_val, issue_slots[15].out_uop.fp_val connect issue_slots[14].in_uop.bits.fcn_op, issue_slots[15].out_uop.fcn_op connect issue_slots[14].in_uop.bits.fcn_dw, issue_slots[15].out_uop.fcn_dw connect issue_slots[14].in_uop.bits.frs3_en, issue_slots[15].out_uop.frs3_en connect issue_slots[14].in_uop.bits.lrs2_rtype, issue_slots[15].out_uop.lrs2_rtype connect issue_slots[14].in_uop.bits.lrs1_rtype, issue_slots[15].out_uop.lrs1_rtype connect issue_slots[14].in_uop.bits.dst_rtype, issue_slots[15].out_uop.dst_rtype connect issue_slots[14].in_uop.bits.lrs3, issue_slots[15].out_uop.lrs3 connect issue_slots[14].in_uop.bits.lrs2, issue_slots[15].out_uop.lrs2 connect issue_slots[14].in_uop.bits.lrs1, issue_slots[15].out_uop.lrs1 connect issue_slots[14].in_uop.bits.ldst, issue_slots[15].out_uop.ldst connect issue_slots[14].in_uop.bits.ldst_is_rs1, issue_slots[15].out_uop.ldst_is_rs1 connect issue_slots[14].in_uop.bits.csr_cmd, issue_slots[15].out_uop.csr_cmd connect issue_slots[14].in_uop.bits.flush_on_commit, issue_slots[15].out_uop.flush_on_commit connect issue_slots[14].in_uop.bits.is_unique, issue_slots[15].out_uop.is_unique connect issue_slots[14].in_uop.bits.uses_stq, issue_slots[15].out_uop.uses_stq connect issue_slots[14].in_uop.bits.uses_ldq, issue_slots[15].out_uop.uses_ldq connect issue_slots[14].in_uop.bits.mem_signed, issue_slots[15].out_uop.mem_signed connect issue_slots[14].in_uop.bits.mem_size, issue_slots[15].out_uop.mem_size connect issue_slots[14].in_uop.bits.mem_cmd, issue_slots[15].out_uop.mem_cmd connect issue_slots[14].in_uop.bits.exc_cause, issue_slots[15].out_uop.exc_cause connect issue_slots[14].in_uop.bits.exception, issue_slots[15].out_uop.exception connect issue_slots[14].in_uop.bits.stale_pdst, issue_slots[15].out_uop.stale_pdst connect issue_slots[14].in_uop.bits.ppred_busy, issue_slots[15].out_uop.ppred_busy connect issue_slots[14].in_uop.bits.prs3_busy, issue_slots[15].out_uop.prs3_busy connect issue_slots[14].in_uop.bits.prs2_busy, issue_slots[15].out_uop.prs2_busy connect issue_slots[14].in_uop.bits.prs1_busy, issue_slots[15].out_uop.prs1_busy connect issue_slots[14].in_uop.bits.ppred, issue_slots[15].out_uop.ppred connect issue_slots[14].in_uop.bits.prs3, issue_slots[15].out_uop.prs3 connect issue_slots[14].in_uop.bits.prs2, issue_slots[15].out_uop.prs2 connect issue_slots[14].in_uop.bits.prs1, issue_slots[15].out_uop.prs1 connect issue_slots[14].in_uop.bits.pdst, issue_slots[15].out_uop.pdst connect issue_slots[14].in_uop.bits.rxq_idx, issue_slots[15].out_uop.rxq_idx connect issue_slots[14].in_uop.bits.stq_idx, issue_slots[15].out_uop.stq_idx connect issue_slots[14].in_uop.bits.ldq_idx, issue_slots[15].out_uop.ldq_idx connect issue_slots[14].in_uop.bits.rob_idx, issue_slots[15].out_uop.rob_idx connect issue_slots[14].in_uop.bits.fp_ctrl.vec, issue_slots[15].out_uop.fp_ctrl.vec connect issue_slots[14].in_uop.bits.fp_ctrl.wflags, issue_slots[15].out_uop.fp_ctrl.wflags connect issue_slots[14].in_uop.bits.fp_ctrl.sqrt, issue_slots[15].out_uop.fp_ctrl.sqrt connect issue_slots[14].in_uop.bits.fp_ctrl.div, issue_slots[15].out_uop.fp_ctrl.div connect issue_slots[14].in_uop.bits.fp_ctrl.fma, issue_slots[15].out_uop.fp_ctrl.fma connect issue_slots[14].in_uop.bits.fp_ctrl.fastpipe, issue_slots[15].out_uop.fp_ctrl.fastpipe connect issue_slots[14].in_uop.bits.fp_ctrl.toint, issue_slots[15].out_uop.fp_ctrl.toint connect issue_slots[14].in_uop.bits.fp_ctrl.fromint, issue_slots[15].out_uop.fp_ctrl.fromint connect issue_slots[14].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[15].out_uop.fp_ctrl.typeTagOut connect issue_slots[14].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[15].out_uop.fp_ctrl.typeTagIn connect issue_slots[14].in_uop.bits.fp_ctrl.swap23, issue_slots[15].out_uop.fp_ctrl.swap23 connect issue_slots[14].in_uop.bits.fp_ctrl.swap12, issue_slots[15].out_uop.fp_ctrl.swap12 connect issue_slots[14].in_uop.bits.fp_ctrl.ren3, issue_slots[15].out_uop.fp_ctrl.ren3 connect issue_slots[14].in_uop.bits.fp_ctrl.ren2, issue_slots[15].out_uop.fp_ctrl.ren2 connect issue_slots[14].in_uop.bits.fp_ctrl.ren1, issue_slots[15].out_uop.fp_ctrl.ren1 connect issue_slots[14].in_uop.bits.fp_ctrl.wen, issue_slots[15].out_uop.fp_ctrl.wen connect issue_slots[14].in_uop.bits.fp_ctrl.ldst, issue_slots[15].out_uop.fp_ctrl.ldst connect issue_slots[14].in_uop.bits.op2_sel, issue_slots[15].out_uop.op2_sel connect issue_slots[14].in_uop.bits.op1_sel, issue_slots[15].out_uop.op1_sel connect issue_slots[14].in_uop.bits.imm_packed, issue_slots[15].out_uop.imm_packed connect issue_slots[14].in_uop.bits.pimm, issue_slots[15].out_uop.pimm connect issue_slots[14].in_uop.bits.imm_sel, issue_slots[15].out_uop.imm_sel connect issue_slots[14].in_uop.bits.imm_rename, issue_slots[15].out_uop.imm_rename connect issue_slots[14].in_uop.bits.taken, issue_slots[15].out_uop.taken connect issue_slots[14].in_uop.bits.pc_lob, issue_slots[15].out_uop.pc_lob connect issue_slots[14].in_uop.bits.edge_inst, issue_slots[15].out_uop.edge_inst connect issue_slots[14].in_uop.bits.ftq_idx, issue_slots[15].out_uop.ftq_idx connect issue_slots[14].in_uop.bits.is_mov, issue_slots[15].out_uop.is_mov connect issue_slots[14].in_uop.bits.is_rocc, issue_slots[15].out_uop.is_rocc connect issue_slots[14].in_uop.bits.is_sys_pc2epc, issue_slots[15].out_uop.is_sys_pc2epc connect issue_slots[14].in_uop.bits.is_eret, issue_slots[15].out_uop.is_eret connect issue_slots[14].in_uop.bits.is_amo, issue_slots[15].out_uop.is_amo connect issue_slots[14].in_uop.bits.is_sfence, issue_slots[15].out_uop.is_sfence connect issue_slots[14].in_uop.bits.is_fencei, issue_slots[15].out_uop.is_fencei connect issue_slots[14].in_uop.bits.is_fence, issue_slots[15].out_uop.is_fence connect issue_slots[14].in_uop.bits.is_sfb, issue_slots[15].out_uop.is_sfb connect issue_slots[14].in_uop.bits.br_type, issue_slots[15].out_uop.br_type connect issue_slots[14].in_uop.bits.br_tag, issue_slots[15].out_uop.br_tag connect issue_slots[14].in_uop.bits.br_mask, issue_slots[15].out_uop.br_mask connect issue_slots[14].in_uop.bits.dis_col_sel, issue_slots[15].out_uop.dis_col_sel connect issue_slots[14].in_uop.bits.iw_p3_bypass_hint, issue_slots[15].out_uop.iw_p3_bypass_hint connect issue_slots[14].in_uop.bits.iw_p2_bypass_hint, issue_slots[15].out_uop.iw_p2_bypass_hint connect issue_slots[14].in_uop.bits.iw_p1_bypass_hint, issue_slots[15].out_uop.iw_p1_bypass_hint connect issue_slots[14].in_uop.bits.iw_p2_speculative_child, issue_slots[15].out_uop.iw_p2_speculative_child connect issue_slots[14].in_uop.bits.iw_p1_speculative_child, issue_slots[15].out_uop.iw_p1_speculative_child connect issue_slots[14].in_uop.bits.iw_issued_partial_dgen, issue_slots[15].out_uop.iw_issued_partial_dgen connect issue_slots[14].in_uop.bits.iw_issued_partial_agen, issue_slots[15].out_uop.iw_issued_partial_agen connect issue_slots[14].in_uop.bits.iw_issued, issue_slots[15].out_uop.iw_issued connect issue_slots[14].in_uop.bits.fu_code[0], issue_slots[15].out_uop.fu_code[0] connect issue_slots[14].in_uop.bits.fu_code[1], issue_slots[15].out_uop.fu_code[1] connect issue_slots[14].in_uop.bits.fu_code[2], issue_slots[15].out_uop.fu_code[2] connect issue_slots[14].in_uop.bits.fu_code[3], issue_slots[15].out_uop.fu_code[3] connect issue_slots[14].in_uop.bits.fu_code[4], issue_slots[15].out_uop.fu_code[4] connect issue_slots[14].in_uop.bits.fu_code[5], issue_slots[15].out_uop.fu_code[5] connect issue_slots[14].in_uop.bits.fu_code[6], issue_slots[15].out_uop.fu_code[6] connect issue_slots[14].in_uop.bits.fu_code[7], issue_slots[15].out_uop.fu_code[7] connect issue_slots[14].in_uop.bits.fu_code[8], issue_slots[15].out_uop.fu_code[8] connect issue_slots[14].in_uop.bits.fu_code[9], issue_slots[15].out_uop.fu_code[9] connect issue_slots[14].in_uop.bits.iq_type[0], issue_slots[15].out_uop.iq_type[0] connect issue_slots[14].in_uop.bits.iq_type[1], issue_slots[15].out_uop.iq_type[1] connect issue_slots[14].in_uop.bits.iq_type[2], issue_slots[15].out_uop.iq_type[2] connect issue_slots[14].in_uop.bits.iq_type[3], issue_slots[15].out_uop.iq_type[3] connect issue_slots[14].in_uop.bits.debug_pc, issue_slots[15].out_uop.debug_pc connect issue_slots[14].in_uop.bits.is_rvc, issue_slots[15].out_uop.is_rvc connect issue_slots[14].in_uop.bits.debug_inst, issue_slots[15].out_uop.debug_inst connect issue_slots[14].in_uop.bits.inst, issue_slots[15].out_uop.inst node _T_320 = eq(shamts_oh[16], UInt<2>(0h2)) when _T_320 : connect issue_slots[14].in_uop.valid, will_be_valid_16 connect issue_slots[14].in_uop.bits.debug_tsrc, _WIRE.debug_tsrc connect issue_slots[14].in_uop.bits.debug_fsrc, _WIRE.debug_fsrc connect issue_slots[14].in_uop.bits.bp_xcpt_if, _WIRE.bp_xcpt_if connect issue_slots[14].in_uop.bits.bp_debug_if, _WIRE.bp_debug_if connect issue_slots[14].in_uop.bits.xcpt_ma_if, _WIRE.xcpt_ma_if connect issue_slots[14].in_uop.bits.xcpt_ae_if, _WIRE.xcpt_ae_if connect issue_slots[14].in_uop.bits.xcpt_pf_if, _WIRE.xcpt_pf_if connect issue_slots[14].in_uop.bits.fp_typ, _WIRE.fp_typ connect issue_slots[14].in_uop.bits.fp_rm, _WIRE.fp_rm connect issue_slots[14].in_uop.bits.fp_val, _WIRE.fp_val connect issue_slots[14].in_uop.bits.fcn_op, _WIRE.fcn_op connect issue_slots[14].in_uop.bits.fcn_dw, _WIRE.fcn_dw connect issue_slots[14].in_uop.bits.frs3_en, _WIRE.frs3_en connect issue_slots[14].in_uop.bits.lrs2_rtype, _WIRE.lrs2_rtype connect issue_slots[14].in_uop.bits.lrs1_rtype, _WIRE.lrs1_rtype connect issue_slots[14].in_uop.bits.dst_rtype, _WIRE.dst_rtype connect issue_slots[14].in_uop.bits.lrs3, _WIRE.lrs3 connect issue_slots[14].in_uop.bits.lrs2, _WIRE.lrs2 connect issue_slots[14].in_uop.bits.lrs1, _WIRE.lrs1 connect issue_slots[14].in_uop.bits.ldst, _WIRE.ldst connect issue_slots[14].in_uop.bits.ldst_is_rs1, _WIRE.ldst_is_rs1 connect issue_slots[14].in_uop.bits.csr_cmd, _WIRE.csr_cmd connect issue_slots[14].in_uop.bits.flush_on_commit, _WIRE.flush_on_commit connect issue_slots[14].in_uop.bits.is_unique, _WIRE.is_unique connect issue_slots[14].in_uop.bits.uses_stq, _WIRE.uses_stq connect issue_slots[14].in_uop.bits.uses_ldq, _WIRE.uses_ldq connect issue_slots[14].in_uop.bits.mem_signed, _WIRE.mem_signed connect issue_slots[14].in_uop.bits.mem_size, _WIRE.mem_size connect issue_slots[14].in_uop.bits.mem_cmd, _WIRE.mem_cmd connect issue_slots[14].in_uop.bits.exc_cause, _WIRE.exc_cause connect issue_slots[14].in_uop.bits.exception, _WIRE.exception connect issue_slots[14].in_uop.bits.stale_pdst, _WIRE.stale_pdst connect issue_slots[14].in_uop.bits.ppred_busy, _WIRE.ppred_busy connect issue_slots[14].in_uop.bits.prs3_busy, _WIRE.prs3_busy connect issue_slots[14].in_uop.bits.prs2_busy, _WIRE.prs2_busy connect issue_slots[14].in_uop.bits.prs1_busy, _WIRE.prs1_busy connect issue_slots[14].in_uop.bits.ppred, _WIRE.ppred connect issue_slots[14].in_uop.bits.prs3, _WIRE.prs3 connect issue_slots[14].in_uop.bits.prs2, _WIRE.prs2 connect issue_slots[14].in_uop.bits.prs1, _WIRE.prs1 connect issue_slots[14].in_uop.bits.pdst, _WIRE.pdst connect issue_slots[14].in_uop.bits.rxq_idx, _WIRE.rxq_idx connect issue_slots[14].in_uop.bits.stq_idx, _WIRE.stq_idx connect issue_slots[14].in_uop.bits.ldq_idx, _WIRE.ldq_idx connect issue_slots[14].in_uop.bits.rob_idx, _WIRE.rob_idx connect issue_slots[14].in_uop.bits.fp_ctrl.vec, _WIRE.fp_ctrl.vec connect issue_slots[14].in_uop.bits.fp_ctrl.wflags, _WIRE.fp_ctrl.wflags connect issue_slots[14].in_uop.bits.fp_ctrl.sqrt, _WIRE.fp_ctrl.sqrt connect issue_slots[14].in_uop.bits.fp_ctrl.div, _WIRE.fp_ctrl.div connect issue_slots[14].in_uop.bits.fp_ctrl.fma, _WIRE.fp_ctrl.fma connect issue_slots[14].in_uop.bits.fp_ctrl.fastpipe, _WIRE.fp_ctrl.fastpipe connect issue_slots[14].in_uop.bits.fp_ctrl.toint, _WIRE.fp_ctrl.toint connect issue_slots[14].in_uop.bits.fp_ctrl.fromint, _WIRE.fp_ctrl.fromint connect issue_slots[14].in_uop.bits.fp_ctrl.typeTagOut, _WIRE.fp_ctrl.typeTagOut connect issue_slots[14].in_uop.bits.fp_ctrl.typeTagIn, _WIRE.fp_ctrl.typeTagIn connect issue_slots[14].in_uop.bits.fp_ctrl.swap23, _WIRE.fp_ctrl.swap23 connect issue_slots[14].in_uop.bits.fp_ctrl.swap12, _WIRE.fp_ctrl.swap12 connect issue_slots[14].in_uop.bits.fp_ctrl.ren3, _WIRE.fp_ctrl.ren3 connect issue_slots[14].in_uop.bits.fp_ctrl.ren2, _WIRE.fp_ctrl.ren2 connect issue_slots[14].in_uop.bits.fp_ctrl.ren1, _WIRE.fp_ctrl.ren1 connect issue_slots[14].in_uop.bits.fp_ctrl.wen, _WIRE.fp_ctrl.wen connect issue_slots[14].in_uop.bits.fp_ctrl.ldst, _WIRE.fp_ctrl.ldst connect issue_slots[14].in_uop.bits.op2_sel, _WIRE.op2_sel connect issue_slots[14].in_uop.bits.op1_sel, _WIRE.op1_sel connect issue_slots[14].in_uop.bits.imm_packed, _WIRE.imm_packed connect issue_slots[14].in_uop.bits.pimm, _WIRE.pimm connect issue_slots[14].in_uop.bits.imm_sel, _WIRE.imm_sel connect issue_slots[14].in_uop.bits.imm_rename, _WIRE.imm_rename connect issue_slots[14].in_uop.bits.taken, _WIRE.taken connect issue_slots[14].in_uop.bits.pc_lob, _WIRE.pc_lob connect issue_slots[14].in_uop.bits.edge_inst, _WIRE.edge_inst connect issue_slots[14].in_uop.bits.ftq_idx, _WIRE.ftq_idx connect issue_slots[14].in_uop.bits.is_mov, _WIRE.is_mov connect issue_slots[14].in_uop.bits.is_rocc, _WIRE.is_rocc connect issue_slots[14].in_uop.bits.is_sys_pc2epc, _WIRE.is_sys_pc2epc connect issue_slots[14].in_uop.bits.is_eret, _WIRE.is_eret connect issue_slots[14].in_uop.bits.is_amo, _WIRE.is_amo connect issue_slots[14].in_uop.bits.is_sfence, _WIRE.is_sfence connect issue_slots[14].in_uop.bits.is_fencei, _WIRE.is_fencei connect issue_slots[14].in_uop.bits.is_fence, _WIRE.is_fence connect issue_slots[14].in_uop.bits.is_sfb, _WIRE.is_sfb connect issue_slots[14].in_uop.bits.br_type, _WIRE.br_type connect issue_slots[14].in_uop.bits.br_tag, _WIRE.br_tag connect issue_slots[14].in_uop.bits.br_mask, _WIRE.br_mask connect issue_slots[14].in_uop.bits.dis_col_sel, _WIRE.dis_col_sel connect issue_slots[14].in_uop.bits.iw_p3_bypass_hint, _WIRE.iw_p3_bypass_hint connect issue_slots[14].in_uop.bits.iw_p2_bypass_hint, _WIRE.iw_p2_bypass_hint connect issue_slots[14].in_uop.bits.iw_p1_bypass_hint, _WIRE.iw_p1_bypass_hint connect issue_slots[14].in_uop.bits.iw_p2_speculative_child, _WIRE.iw_p2_speculative_child connect issue_slots[14].in_uop.bits.iw_p1_speculative_child, _WIRE.iw_p1_speculative_child connect issue_slots[14].in_uop.bits.iw_issued_partial_dgen, _WIRE.iw_issued_partial_dgen connect issue_slots[14].in_uop.bits.iw_issued_partial_agen, _WIRE.iw_issued_partial_agen connect issue_slots[14].in_uop.bits.iw_issued, _WIRE.iw_issued connect issue_slots[14].in_uop.bits.fu_code[0], _WIRE.fu_code[0] connect issue_slots[14].in_uop.bits.fu_code[1], _WIRE.fu_code[1] connect issue_slots[14].in_uop.bits.fu_code[2], _WIRE.fu_code[2] connect issue_slots[14].in_uop.bits.fu_code[3], _WIRE.fu_code[3] connect issue_slots[14].in_uop.bits.fu_code[4], _WIRE.fu_code[4] connect issue_slots[14].in_uop.bits.fu_code[5], _WIRE.fu_code[5] connect issue_slots[14].in_uop.bits.fu_code[6], _WIRE.fu_code[6] connect issue_slots[14].in_uop.bits.fu_code[7], _WIRE.fu_code[7] connect issue_slots[14].in_uop.bits.fu_code[8], _WIRE.fu_code[8] connect issue_slots[14].in_uop.bits.fu_code[9], _WIRE.fu_code[9] connect issue_slots[14].in_uop.bits.iq_type[0], _WIRE.iq_type[0] connect issue_slots[14].in_uop.bits.iq_type[1], _WIRE.iq_type[1] connect issue_slots[14].in_uop.bits.iq_type[2], _WIRE.iq_type[2] connect issue_slots[14].in_uop.bits.iq_type[3], _WIRE.iq_type[3] connect issue_slots[14].in_uop.bits.debug_pc, _WIRE.debug_pc connect issue_slots[14].in_uop.bits.is_rvc, _WIRE.is_rvc connect issue_slots[14].in_uop.bits.debug_inst, _WIRE.debug_inst connect issue_slots[14].in_uop.bits.inst, _WIRE.inst node _T_321 = eq(shamts_oh[17], UInt<3>(0h4)) when _T_321 : connect issue_slots[14].in_uop.valid, will_be_valid_17 connect issue_slots[14].in_uop.bits.debug_tsrc, _WIRE_1.debug_tsrc connect issue_slots[14].in_uop.bits.debug_fsrc, _WIRE_1.debug_fsrc connect issue_slots[14].in_uop.bits.bp_xcpt_if, _WIRE_1.bp_xcpt_if connect issue_slots[14].in_uop.bits.bp_debug_if, _WIRE_1.bp_debug_if connect issue_slots[14].in_uop.bits.xcpt_ma_if, _WIRE_1.xcpt_ma_if connect issue_slots[14].in_uop.bits.xcpt_ae_if, _WIRE_1.xcpt_ae_if connect issue_slots[14].in_uop.bits.xcpt_pf_if, _WIRE_1.xcpt_pf_if connect issue_slots[14].in_uop.bits.fp_typ, _WIRE_1.fp_typ connect issue_slots[14].in_uop.bits.fp_rm, _WIRE_1.fp_rm connect issue_slots[14].in_uop.bits.fp_val, _WIRE_1.fp_val connect issue_slots[14].in_uop.bits.fcn_op, _WIRE_1.fcn_op connect issue_slots[14].in_uop.bits.fcn_dw, _WIRE_1.fcn_dw connect issue_slots[14].in_uop.bits.frs3_en, _WIRE_1.frs3_en connect issue_slots[14].in_uop.bits.lrs2_rtype, _WIRE_1.lrs2_rtype connect issue_slots[14].in_uop.bits.lrs1_rtype, _WIRE_1.lrs1_rtype connect issue_slots[14].in_uop.bits.dst_rtype, _WIRE_1.dst_rtype connect issue_slots[14].in_uop.bits.lrs3, _WIRE_1.lrs3 connect issue_slots[14].in_uop.bits.lrs2, _WIRE_1.lrs2 connect issue_slots[14].in_uop.bits.lrs1, _WIRE_1.lrs1 connect issue_slots[14].in_uop.bits.ldst, _WIRE_1.ldst connect issue_slots[14].in_uop.bits.ldst_is_rs1, _WIRE_1.ldst_is_rs1 connect issue_slots[14].in_uop.bits.csr_cmd, _WIRE_1.csr_cmd connect issue_slots[14].in_uop.bits.flush_on_commit, _WIRE_1.flush_on_commit connect issue_slots[14].in_uop.bits.is_unique, _WIRE_1.is_unique connect issue_slots[14].in_uop.bits.uses_stq, _WIRE_1.uses_stq connect issue_slots[14].in_uop.bits.uses_ldq, _WIRE_1.uses_ldq connect issue_slots[14].in_uop.bits.mem_signed, _WIRE_1.mem_signed connect issue_slots[14].in_uop.bits.mem_size, _WIRE_1.mem_size connect issue_slots[14].in_uop.bits.mem_cmd, _WIRE_1.mem_cmd connect issue_slots[14].in_uop.bits.exc_cause, _WIRE_1.exc_cause connect issue_slots[14].in_uop.bits.exception, _WIRE_1.exception connect issue_slots[14].in_uop.bits.stale_pdst, _WIRE_1.stale_pdst connect issue_slots[14].in_uop.bits.ppred_busy, _WIRE_1.ppred_busy connect issue_slots[14].in_uop.bits.prs3_busy, _WIRE_1.prs3_busy connect issue_slots[14].in_uop.bits.prs2_busy, _WIRE_1.prs2_busy connect issue_slots[14].in_uop.bits.prs1_busy, _WIRE_1.prs1_busy connect issue_slots[14].in_uop.bits.ppred, _WIRE_1.ppred connect issue_slots[14].in_uop.bits.prs3, _WIRE_1.prs3 connect issue_slots[14].in_uop.bits.prs2, _WIRE_1.prs2 connect issue_slots[14].in_uop.bits.prs1, _WIRE_1.prs1 connect issue_slots[14].in_uop.bits.pdst, _WIRE_1.pdst connect issue_slots[14].in_uop.bits.rxq_idx, _WIRE_1.rxq_idx connect issue_slots[14].in_uop.bits.stq_idx, _WIRE_1.stq_idx connect issue_slots[14].in_uop.bits.ldq_idx, _WIRE_1.ldq_idx connect issue_slots[14].in_uop.bits.rob_idx, _WIRE_1.rob_idx connect issue_slots[14].in_uop.bits.fp_ctrl.vec, _WIRE_1.fp_ctrl.vec connect issue_slots[14].in_uop.bits.fp_ctrl.wflags, _WIRE_1.fp_ctrl.wflags connect issue_slots[14].in_uop.bits.fp_ctrl.sqrt, _WIRE_1.fp_ctrl.sqrt connect issue_slots[14].in_uop.bits.fp_ctrl.div, _WIRE_1.fp_ctrl.div connect issue_slots[14].in_uop.bits.fp_ctrl.fma, _WIRE_1.fp_ctrl.fma connect issue_slots[14].in_uop.bits.fp_ctrl.fastpipe, _WIRE_1.fp_ctrl.fastpipe connect issue_slots[14].in_uop.bits.fp_ctrl.toint, _WIRE_1.fp_ctrl.toint connect issue_slots[14].in_uop.bits.fp_ctrl.fromint, _WIRE_1.fp_ctrl.fromint connect issue_slots[14].in_uop.bits.fp_ctrl.typeTagOut, _WIRE_1.fp_ctrl.typeTagOut connect issue_slots[14].in_uop.bits.fp_ctrl.typeTagIn, _WIRE_1.fp_ctrl.typeTagIn connect issue_slots[14].in_uop.bits.fp_ctrl.swap23, _WIRE_1.fp_ctrl.swap23 connect issue_slots[14].in_uop.bits.fp_ctrl.swap12, _WIRE_1.fp_ctrl.swap12 connect issue_slots[14].in_uop.bits.fp_ctrl.ren3, _WIRE_1.fp_ctrl.ren3 connect issue_slots[14].in_uop.bits.fp_ctrl.ren2, _WIRE_1.fp_ctrl.ren2 connect issue_slots[14].in_uop.bits.fp_ctrl.ren1, _WIRE_1.fp_ctrl.ren1 connect issue_slots[14].in_uop.bits.fp_ctrl.wen, _WIRE_1.fp_ctrl.wen connect issue_slots[14].in_uop.bits.fp_ctrl.ldst, _WIRE_1.fp_ctrl.ldst connect issue_slots[14].in_uop.bits.op2_sel, _WIRE_1.op2_sel connect issue_slots[14].in_uop.bits.op1_sel, _WIRE_1.op1_sel connect issue_slots[14].in_uop.bits.imm_packed, _WIRE_1.imm_packed connect issue_slots[14].in_uop.bits.pimm, _WIRE_1.pimm connect issue_slots[14].in_uop.bits.imm_sel, _WIRE_1.imm_sel connect issue_slots[14].in_uop.bits.imm_rename, _WIRE_1.imm_rename connect issue_slots[14].in_uop.bits.taken, _WIRE_1.taken connect issue_slots[14].in_uop.bits.pc_lob, _WIRE_1.pc_lob connect issue_slots[14].in_uop.bits.edge_inst, _WIRE_1.edge_inst connect issue_slots[14].in_uop.bits.ftq_idx, _WIRE_1.ftq_idx connect issue_slots[14].in_uop.bits.is_mov, _WIRE_1.is_mov connect issue_slots[14].in_uop.bits.is_rocc, _WIRE_1.is_rocc connect issue_slots[14].in_uop.bits.is_sys_pc2epc, _WIRE_1.is_sys_pc2epc connect issue_slots[14].in_uop.bits.is_eret, _WIRE_1.is_eret connect issue_slots[14].in_uop.bits.is_amo, _WIRE_1.is_amo connect issue_slots[14].in_uop.bits.is_sfence, _WIRE_1.is_sfence connect issue_slots[14].in_uop.bits.is_fencei, _WIRE_1.is_fencei connect issue_slots[14].in_uop.bits.is_fence, _WIRE_1.is_fence connect issue_slots[14].in_uop.bits.is_sfb, _WIRE_1.is_sfb connect issue_slots[14].in_uop.bits.br_type, _WIRE_1.br_type connect issue_slots[14].in_uop.bits.br_tag, _WIRE_1.br_tag connect issue_slots[14].in_uop.bits.br_mask, _WIRE_1.br_mask connect issue_slots[14].in_uop.bits.dis_col_sel, _WIRE_1.dis_col_sel connect issue_slots[14].in_uop.bits.iw_p3_bypass_hint, _WIRE_1.iw_p3_bypass_hint connect issue_slots[14].in_uop.bits.iw_p2_bypass_hint, _WIRE_1.iw_p2_bypass_hint connect issue_slots[14].in_uop.bits.iw_p1_bypass_hint, _WIRE_1.iw_p1_bypass_hint connect issue_slots[14].in_uop.bits.iw_p2_speculative_child, _WIRE_1.iw_p2_speculative_child connect issue_slots[14].in_uop.bits.iw_p1_speculative_child, _WIRE_1.iw_p1_speculative_child connect issue_slots[14].in_uop.bits.iw_issued_partial_dgen, _WIRE_1.iw_issued_partial_dgen connect issue_slots[14].in_uop.bits.iw_issued_partial_agen, _WIRE_1.iw_issued_partial_agen connect issue_slots[14].in_uop.bits.iw_issued, _WIRE_1.iw_issued connect issue_slots[14].in_uop.bits.fu_code[0], _WIRE_1.fu_code[0] connect issue_slots[14].in_uop.bits.fu_code[1], _WIRE_1.fu_code[1] connect issue_slots[14].in_uop.bits.fu_code[2], _WIRE_1.fu_code[2] connect issue_slots[14].in_uop.bits.fu_code[3], _WIRE_1.fu_code[3] connect issue_slots[14].in_uop.bits.fu_code[4], _WIRE_1.fu_code[4] connect issue_slots[14].in_uop.bits.fu_code[5], _WIRE_1.fu_code[5] connect issue_slots[14].in_uop.bits.fu_code[6], _WIRE_1.fu_code[6] connect issue_slots[14].in_uop.bits.fu_code[7], _WIRE_1.fu_code[7] connect issue_slots[14].in_uop.bits.fu_code[8], _WIRE_1.fu_code[8] connect issue_slots[14].in_uop.bits.fu_code[9], _WIRE_1.fu_code[9] connect issue_slots[14].in_uop.bits.iq_type[0], _WIRE_1.iq_type[0] connect issue_slots[14].in_uop.bits.iq_type[1], _WIRE_1.iq_type[1] connect issue_slots[14].in_uop.bits.iq_type[2], _WIRE_1.iq_type[2] connect issue_slots[14].in_uop.bits.iq_type[3], _WIRE_1.iq_type[3] connect issue_slots[14].in_uop.bits.debug_pc, _WIRE_1.debug_pc connect issue_slots[14].in_uop.bits.is_rvc, _WIRE_1.is_rvc connect issue_slots[14].in_uop.bits.debug_inst, _WIRE_1.debug_inst connect issue_slots[14].in_uop.bits.inst, _WIRE_1.inst node _issue_slots_14_clear_T = neq(shamts_oh[14], UInt<1>(0h0)) connect issue_slots[14].clear, _issue_slots_14_clear_T connect issue_slots[15].in_uop.valid, UInt<1>(0h0) connect issue_slots[15].in_uop.bits.debug_tsrc, _WIRE.debug_tsrc connect issue_slots[15].in_uop.bits.debug_fsrc, _WIRE.debug_fsrc connect issue_slots[15].in_uop.bits.bp_xcpt_if, _WIRE.bp_xcpt_if connect issue_slots[15].in_uop.bits.bp_debug_if, _WIRE.bp_debug_if connect issue_slots[15].in_uop.bits.xcpt_ma_if, _WIRE.xcpt_ma_if connect issue_slots[15].in_uop.bits.xcpt_ae_if, _WIRE.xcpt_ae_if connect issue_slots[15].in_uop.bits.xcpt_pf_if, _WIRE.xcpt_pf_if connect issue_slots[15].in_uop.bits.fp_typ, _WIRE.fp_typ connect issue_slots[15].in_uop.bits.fp_rm, _WIRE.fp_rm connect issue_slots[15].in_uop.bits.fp_val, _WIRE.fp_val connect issue_slots[15].in_uop.bits.fcn_op, _WIRE.fcn_op connect issue_slots[15].in_uop.bits.fcn_dw, _WIRE.fcn_dw connect issue_slots[15].in_uop.bits.frs3_en, _WIRE.frs3_en connect issue_slots[15].in_uop.bits.lrs2_rtype, _WIRE.lrs2_rtype connect issue_slots[15].in_uop.bits.lrs1_rtype, _WIRE.lrs1_rtype connect issue_slots[15].in_uop.bits.dst_rtype, _WIRE.dst_rtype connect issue_slots[15].in_uop.bits.lrs3, _WIRE.lrs3 connect issue_slots[15].in_uop.bits.lrs2, _WIRE.lrs2 connect issue_slots[15].in_uop.bits.lrs1, _WIRE.lrs1 connect issue_slots[15].in_uop.bits.ldst, _WIRE.ldst connect issue_slots[15].in_uop.bits.ldst_is_rs1, _WIRE.ldst_is_rs1 connect issue_slots[15].in_uop.bits.csr_cmd, _WIRE.csr_cmd connect issue_slots[15].in_uop.bits.flush_on_commit, _WIRE.flush_on_commit connect issue_slots[15].in_uop.bits.is_unique, _WIRE.is_unique connect issue_slots[15].in_uop.bits.uses_stq, _WIRE.uses_stq connect issue_slots[15].in_uop.bits.uses_ldq, _WIRE.uses_ldq connect issue_slots[15].in_uop.bits.mem_signed, _WIRE.mem_signed connect issue_slots[15].in_uop.bits.mem_size, _WIRE.mem_size connect issue_slots[15].in_uop.bits.mem_cmd, _WIRE.mem_cmd connect issue_slots[15].in_uop.bits.exc_cause, _WIRE.exc_cause connect issue_slots[15].in_uop.bits.exception, _WIRE.exception connect issue_slots[15].in_uop.bits.stale_pdst, _WIRE.stale_pdst connect issue_slots[15].in_uop.bits.ppred_busy, _WIRE.ppred_busy connect issue_slots[15].in_uop.bits.prs3_busy, _WIRE.prs3_busy connect issue_slots[15].in_uop.bits.prs2_busy, _WIRE.prs2_busy connect issue_slots[15].in_uop.bits.prs1_busy, _WIRE.prs1_busy connect issue_slots[15].in_uop.bits.ppred, _WIRE.ppred connect issue_slots[15].in_uop.bits.prs3, _WIRE.prs3 connect issue_slots[15].in_uop.bits.prs2, _WIRE.prs2 connect issue_slots[15].in_uop.bits.prs1, _WIRE.prs1 connect issue_slots[15].in_uop.bits.pdst, _WIRE.pdst connect issue_slots[15].in_uop.bits.rxq_idx, _WIRE.rxq_idx connect issue_slots[15].in_uop.bits.stq_idx, _WIRE.stq_idx connect issue_slots[15].in_uop.bits.ldq_idx, _WIRE.ldq_idx connect issue_slots[15].in_uop.bits.rob_idx, _WIRE.rob_idx connect issue_slots[15].in_uop.bits.fp_ctrl.vec, _WIRE.fp_ctrl.vec connect issue_slots[15].in_uop.bits.fp_ctrl.wflags, _WIRE.fp_ctrl.wflags connect issue_slots[15].in_uop.bits.fp_ctrl.sqrt, _WIRE.fp_ctrl.sqrt connect issue_slots[15].in_uop.bits.fp_ctrl.div, _WIRE.fp_ctrl.div connect issue_slots[15].in_uop.bits.fp_ctrl.fma, _WIRE.fp_ctrl.fma connect issue_slots[15].in_uop.bits.fp_ctrl.fastpipe, _WIRE.fp_ctrl.fastpipe connect issue_slots[15].in_uop.bits.fp_ctrl.toint, _WIRE.fp_ctrl.toint connect issue_slots[15].in_uop.bits.fp_ctrl.fromint, _WIRE.fp_ctrl.fromint connect issue_slots[15].in_uop.bits.fp_ctrl.typeTagOut, _WIRE.fp_ctrl.typeTagOut connect issue_slots[15].in_uop.bits.fp_ctrl.typeTagIn, _WIRE.fp_ctrl.typeTagIn connect issue_slots[15].in_uop.bits.fp_ctrl.swap23, _WIRE.fp_ctrl.swap23 connect issue_slots[15].in_uop.bits.fp_ctrl.swap12, _WIRE.fp_ctrl.swap12 connect issue_slots[15].in_uop.bits.fp_ctrl.ren3, _WIRE.fp_ctrl.ren3 connect issue_slots[15].in_uop.bits.fp_ctrl.ren2, _WIRE.fp_ctrl.ren2 connect issue_slots[15].in_uop.bits.fp_ctrl.ren1, _WIRE.fp_ctrl.ren1 connect issue_slots[15].in_uop.bits.fp_ctrl.wen, _WIRE.fp_ctrl.wen connect issue_slots[15].in_uop.bits.fp_ctrl.ldst, _WIRE.fp_ctrl.ldst connect issue_slots[15].in_uop.bits.op2_sel, _WIRE.op2_sel connect issue_slots[15].in_uop.bits.op1_sel, _WIRE.op1_sel connect issue_slots[15].in_uop.bits.imm_packed, _WIRE.imm_packed connect issue_slots[15].in_uop.bits.pimm, _WIRE.pimm connect issue_slots[15].in_uop.bits.imm_sel, _WIRE.imm_sel connect issue_slots[15].in_uop.bits.imm_rename, _WIRE.imm_rename connect issue_slots[15].in_uop.bits.taken, _WIRE.taken connect issue_slots[15].in_uop.bits.pc_lob, _WIRE.pc_lob connect issue_slots[15].in_uop.bits.edge_inst, _WIRE.edge_inst connect issue_slots[15].in_uop.bits.ftq_idx, _WIRE.ftq_idx connect issue_slots[15].in_uop.bits.is_mov, _WIRE.is_mov connect issue_slots[15].in_uop.bits.is_rocc, _WIRE.is_rocc connect issue_slots[15].in_uop.bits.is_sys_pc2epc, _WIRE.is_sys_pc2epc connect issue_slots[15].in_uop.bits.is_eret, _WIRE.is_eret connect issue_slots[15].in_uop.bits.is_amo, _WIRE.is_amo connect issue_slots[15].in_uop.bits.is_sfence, _WIRE.is_sfence connect issue_slots[15].in_uop.bits.is_fencei, _WIRE.is_fencei connect issue_slots[15].in_uop.bits.is_fence, _WIRE.is_fence connect issue_slots[15].in_uop.bits.is_sfb, _WIRE.is_sfb connect issue_slots[15].in_uop.bits.br_type, _WIRE.br_type connect issue_slots[15].in_uop.bits.br_tag, _WIRE.br_tag connect issue_slots[15].in_uop.bits.br_mask, _WIRE.br_mask connect issue_slots[15].in_uop.bits.dis_col_sel, _WIRE.dis_col_sel connect issue_slots[15].in_uop.bits.iw_p3_bypass_hint, _WIRE.iw_p3_bypass_hint connect issue_slots[15].in_uop.bits.iw_p2_bypass_hint, _WIRE.iw_p2_bypass_hint connect issue_slots[15].in_uop.bits.iw_p1_bypass_hint, _WIRE.iw_p1_bypass_hint connect issue_slots[15].in_uop.bits.iw_p2_speculative_child, _WIRE.iw_p2_speculative_child connect issue_slots[15].in_uop.bits.iw_p1_speculative_child, _WIRE.iw_p1_speculative_child connect issue_slots[15].in_uop.bits.iw_issued_partial_dgen, _WIRE.iw_issued_partial_dgen connect issue_slots[15].in_uop.bits.iw_issued_partial_agen, _WIRE.iw_issued_partial_agen connect issue_slots[15].in_uop.bits.iw_issued, _WIRE.iw_issued connect issue_slots[15].in_uop.bits.fu_code[0], _WIRE.fu_code[0] connect issue_slots[15].in_uop.bits.fu_code[1], _WIRE.fu_code[1] connect issue_slots[15].in_uop.bits.fu_code[2], _WIRE.fu_code[2] connect issue_slots[15].in_uop.bits.fu_code[3], _WIRE.fu_code[3] connect issue_slots[15].in_uop.bits.fu_code[4], _WIRE.fu_code[4] connect issue_slots[15].in_uop.bits.fu_code[5], _WIRE.fu_code[5] connect issue_slots[15].in_uop.bits.fu_code[6], _WIRE.fu_code[6] connect issue_slots[15].in_uop.bits.fu_code[7], _WIRE.fu_code[7] connect issue_slots[15].in_uop.bits.fu_code[8], _WIRE.fu_code[8] connect issue_slots[15].in_uop.bits.fu_code[9], _WIRE.fu_code[9] connect issue_slots[15].in_uop.bits.iq_type[0], _WIRE.iq_type[0] connect issue_slots[15].in_uop.bits.iq_type[1], _WIRE.iq_type[1] connect issue_slots[15].in_uop.bits.iq_type[2], _WIRE.iq_type[2] connect issue_slots[15].in_uop.bits.iq_type[3], _WIRE.iq_type[3] connect issue_slots[15].in_uop.bits.debug_pc, _WIRE.debug_pc connect issue_slots[15].in_uop.bits.is_rvc, _WIRE.is_rvc connect issue_slots[15].in_uop.bits.debug_inst, _WIRE.debug_inst connect issue_slots[15].in_uop.bits.inst, _WIRE.inst node _T_322 = eq(shamts_oh[16], UInt<1>(0h1)) when _T_322 : connect issue_slots[15].in_uop.valid, will_be_valid_16 connect issue_slots[15].in_uop.bits.debug_tsrc, _WIRE.debug_tsrc connect issue_slots[15].in_uop.bits.debug_fsrc, _WIRE.debug_fsrc connect issue_slots[15].in_uop.bits.bp_xcpt_if, _WIRE.bp_xcpt_if connect issue_slots[15].in_uop.bits.bp_debug_if, _WIRE.bp_debug_if connect issue_slots[15].in_uop.bits.xcpt_ma_if, _WIRE.xcpt_ma_if connect issue_slots[15].in_uop.bits.xcpt_ae_if, _WIRE.xcpt_ae_if connect issue_slots[15].in_uop.bits.xcpt_pf_if, _WIRE.xcpt_pf_if connect issue_slots[15].in_uop.bits.fp_typ, _WIRE.fp_typ connect issue_slots[15].in_uop.bits.fp_rm, _WIRE.fp_rm connect issue_slots[15].in_uop.bits.fp_val, _WIRE.fp_val connect issue_slots[15].in_uop.bits.fcn_op, _WIRE.fcn_op connect issue_slots[15].in_uop.bits.fcn_dw, _WIRE.fcn_dw connect issue_slots[15].in_uop.bits.frs3_en, _WIRE.frs3_en connect issue_slots[15].in_uop.bits.lrs2_rtype, _WIRE.lrs2_rtype connect issue_slots[15].in_uop.bits.lrs1_rtype, _WIRE.lrs1_rtype connect issue_slots[15].in_uop.bits.dst_rtype, _WIRE.dst_rtype connect issue_slots[15].in_uop.bits.lrs3, _WIRE.lrs3 connect issue_slots[15].in_uop.bits.lrs2, _WIRE.lrs2 connect issue_slots[15].in_uop.bits.lrs1, _WIRE.lrs1 connect issue_slots[15].in_uop.bits.ldst, _WIRE.ldst connect issue_slots[15].in_uop.bits.ldst_is_rs1, _WIRE.ldst_is_rs1 connect issue_slots[15].in_uop.bits.csr_cmd, _WIRE.csr_cmd connect issue_slots[15].in_uop.bits.flush_on_commit, _WIRE.flush_on_commit connect issue_slots[15].in_uop.bits.is_unique, _WIRE.is_unique connect issue_slots[15].in_uop.bits.uses_stq, _WIRE.uses_stq connect issue_slots[15].in_uop.bits.uses_ldq, _WIRE.uses_ldq connect issue_slots[15].in_uop.bits.mem_signed, _WIRE.mem_signed connect issue_slots[15].in_uop.bits.mem_size, _WIRE.mem_size connect issue_slots[15].in_uop.bits.mem_cmd, _WIRE.mem_cmd connect issue_slots[15].in_uop.bits.exc_cause, _WIRE.exc_cause connect issue_slots[15].in_uop.bits.exception, _WIRE.exception connect issue_slots[15].in_uop.bits.stale_pdst, _WIRE.stale_pdst connect issue_slots[15].in_uop.bits.ppred_busy, _WIRE.ppred_busy connect issue_slots[15].in_uop.bits.prs3_busy, _WIRE.prs3_busy connect issue_slots[15].in_uop.bits.prs2_busy, _WIRE.prs2_busy connect issue_slots[15].in_uop.bits.prs1_busy, _WIRE.prs1_busy connect issue_slots[15].in_uop.bits.ppred, _WIRE.ppred connect issue_slots[15].in_uop.bits.prs3, _WIRE.prs3 connect issue_slots[15].in_uop.bits.prs2, _WIRE.prs2 connect issue_slots[15].in_uop.bits.prs1, _WIRE.prs1 connect issue_slots[15].in_uop.bits.pdst, _WIRE.pdst connect issue_slots[15].in_uop.bits.rxq_idx, _WIRE.rxq_idx connect issue_slots[15].in_uop.bits.stq_idx, _WIRE.stq_idx connect issue_slots[15].in_uop.bits.ldq_idx, _WIRE.ldq_idx connect issue_slots[15].in_uop.bits.rob_idx, _WIRE.rob_idx connect issue_slots[15].in_uop.bits.fp_ctrl.vec, _WIRE.fp_ctrl.vec connect issue_slots[15].in_uop.bits.fp_ctrl.wflags, _WIRE.fp_ctrl.wflags connect issue_slots[15].in_uop.bits.fp_ctrl.sqrt, _WIRE.fp_ctrl.sqrt connect issue_slots[15].in_uop.bits.fp_ctrl.div, _WIRE.fp_ctrl.div connect issue_slots[15].in_uop.bits.fp_ctrl.fma, _WIRE.fp_ctrl.fma connect issue_slots[15].in_uop.bits.fp_ctrl.fastpipe, _WIRE.fp_ctrl.fastpipe connect issue_slots[15].in_uop.bits.fp_ctrl.toint, _WIRE.fp_ctrl.toint connect issue_slots[15].in_uop.bits.fp_ctrl.fromint, _WIRE.fp_ctrl.fromint connect issue_slots[15].in_uop.bits.fp_ctrl.typeTagOut, _WIRE.fp_ctrl.typeTagOut connect issue_slots[15].in_uop.bits.fp_ctrl.typeTagIn, _WIRE.fp_ctrl.typeTagIn connect issue_slots[15].in_uop.bits.fp_ctrl.swap23, _WIRE.fp_ctrl.swap23 connect issue_slots[15].in_uop.bits.fp_ctrl.swap12, _WIRE.fp_ctrl.swap12 connect issue_slots[15].in_uop.bits.fp_ctrl.ren3, _WIRE.fp_ctrl.ren3 connect issue_slots[15].in_uop.bits.fp_ctrl.ren2, _WIRE.fp_ctrl.ren2 connect issue_slots[15].in_uop.bits.fp_ctrl.ren1, _WIRE.fp_ctrl.ren1 connect issue_slots[15].in_uop.bits.fp_ctrl.wen, _WIRE.fp_ctrl.wen connect issue_slots[15].in_uop.bits.fp_ctrl.ldst, _WIRE.fp_ctrl.ldst connect issue_slots[15].in_uop.bits.op2_sel, _WIRE.op2_sel connect issue_slots[15].in_uop.bits.op1_sel, _WIRE.op1_sel connect issue_slots[15].in_uop.bits.imm_packed, _WIRE.imm_packed connect issue_slots[15].in_uop.bits.pimm, _WIRE.pimm connect issue_slots[15].in_uop.bits.imm_sel, _WIRE.imm_sel connect issue_slots[15].in_uop.bits.imm_rename, _WIRE.imm_rename connect issue_slots[15].in_uop.bits.taken, _WIRE.taken connect issue_slots[15].in_uop.bits.pc_lob, _WIRE.pc_lob connect issue_slots[15].in_uop.bits.edge_inst, _WIRE.edge_inst connect issue_slots[15].in_uop.bits.ftq_idx, _WIRE.ftq_idx connect issue_slots[15].in_uop.bits.is_mov, _WIRE.is_mov connect issue_slots[15].in_uop.bits.is_rocc, _WIRE.is_rocc connect issue_slots[15].in_uop.bits.is_sys_pc2epc, _WIRE.is_sys_pc2epc connect issue_slots[15].in_uop.bits.is_eret, _WIRE.is_eret connect issue_slots[15].in_uop.bits.is_amo, _WIRE.is_amo connect issue_slots[15].in_uop.bits.is_sfence, _WIRE.is_sfence connect issue_slots[15].in_uop.bits.is_fencei, _WIRE.is_fencei connect issue_slots[15].in_uop.bits.is_fence, _WIRE.is_fence connect issue_slots[15].in_uop.bits.is_sfb, _WIRE.is_sfb connect issue_slots[15].in_uop.bits.br_type, _WIRE.br_type connect issue_slots[15].in_uop.bits.br_tag, _WIRE.br_tag connect issue_slots[15].in_uop.bits.br_mask, _WIRE.br_mask connect issue_slots[15].in_uop.bits.dis_col_sel, _WIRE.dis_col_sel connect issue_slots[15].in_uop.bits.iw_p3_bypass_hint, _WIRE.iw_p3_bypass_hint connect issue_slots[15].in_uop.bits.iw_p2_bypass_hint, _WIRE.iw_p2_bypass_hint connect issue_slots[15].in_uop.bits.iw_p1_bypass_hint, _WIRE.iw_p1_bypass_hint connect issue_slots[15].in_uop.bits.iw_p2_speculative_child, _WIRE.iw_p2_speculative_child connect issue_slots[15].in_uop.bits.iw_p1_speculative_child, _WIRE.iw_p1_speculative_child connect issue_slots[15].in_uop.bits.iw_issued_partial_dgen, _WIRE.iw_issued_partial_dgen connect issue_slots[15].in_uop.bits.iw_issued_partial_agen, _WIRE.iw_issued_partial_agen connect issue_slots[15].in_uop.bits.iw_issued, _WIRE.iw_issued connect issue_slots[15].in_uop.bits.fu_code[0], _WIRE.fu_code[0] connect issue_slots[15].in_uop.bits.fu_code[1], _WIRE.fu_code[1] connect issue_slots[15].in_uop.bits.fu_code[2], _WIRE.fu_code[2] connect issue_slots[15].in_uop.bits.fu_code[3], _WIRE.fu_code[3] connect issue_slots[15].in_uop.bits.fu_code[4], _WIRE.fu_code[4] connect issue_slots[15].in_uop.bits.fu_code[5], _WIRE.fu_code[5] connect issue_slots[15].in_uop.bits.fu_code[6], _WIRE.fu_code[6] connect issue_slots[15].in_uop.bits.fu_code[7], _WIRE.fu_code[7] connect issue_slots[15].in_uop.bits.fu_code[8], _WIRE.fu_code[8] connect issue_slots[15].in_uop.bits.fu_code[9], _WIRE.fu_code[9] connect issue_slots[15].in_uop.bits.iq_type[0], _WIRE.iq_type[0] connect issue_slots[15].in_uop.bits.iq_type[1], _WIRE.iq_type[1] connect issue_slots[15].in_uop.bits.iq_type[2], _WIRE.iq_type[2] connect issue_slots[15].in_uop.bits.iq_type[3], _WIRE.iq_type[3] connect issue_slots[15].in_uop.bits.debug_pc, _WIRE.debug_pc connect issue_slots[15].in_uop.bits.is_rvc, _WIRE.is_rvc connect issue_slots[15].in_uop.bits.debug_inst, _WIRE.debug_inst connect issue_slots[15].in_uop.bits.inst, _WIRE.inst node _T_323 = eq(shamts_oh[17], UInt<2>(0h2)) when _T_323 : connect issue_slots[15].in_uop.valid, will_be_valid_17 connect issue_slots[15].in_uop.bits.debug_tsrc, _WIRE_1.debug_tsrc connect issue_slots[15].in_uop.bits.debug_fsrc, _WIRE_1.debug_fsrc connect issue_slots[15].in_uop.bits.bp_xcpt_if, _WIRE_1.bp_xcpt_if connect issue_slots[15].in_uop.bits.bp_debug_if, _WIRE_1.bp_debug_if connect issue_slots[15].in_uop.bits.xcpt_ma_if, _WIRE_1.xcpt_ma_if connect issue_slots[15].in_uop.bits.xcpt_ae_if, _WIRE_1.xcpt_ae_if connect issue_slots[15].in_uop.bits.xcpt_pf_if, _WIRE_1.xcpt_pf_if connect issue_slots[15].in_uop.bits.fp_typ, _WIRE_1.fp_typ connect issue_slots[15].in_uop.bits.fp_rm, _WIRE_1.fp_rm connect issue_slots[15].in_uop.bits.fp_val, _WIRE_1.fp_val connect issue_slots[15].in_uop.bits.fcn_op, _WIRE_1.fcn_op connect issue_slots[15].in_uop.bits.fcn_dw, _WIRE_1.fcn_dw connect issue_slots[15].in_uop.bits.frs3_en, _WIRE_1.frs3_en connect issue_slots[15].in_uop.bits.lrs2_rtype, _WIRE_1.lrs2_rtype connect issue_slots[15].in_uop.bits.lrs1_rtype, _WIRE_1.lrs1_rtype connect issue_slots[15].in_uop.bits.dst_rtype, _WIRE_1.dst_rtype connect issue_slots[15].in_uop.bits.lrs3, _WIRE_1.lrs3 connect issue_slots[15].in_uop.bits.lrs2, _WIRE_1.lrs2 connect issue_slots[15].in_uop.bits.lrs1, _WIRE_1.lrs1 connect issue_slots[15].in_uop.bits.ldst, _WIRE_1.ldst connect issue_slots[15].in_uop.bits.ldst_is_rs1, _WIRE_1.ldst_is_rs1 connect issue_slots[15].in_uop.bits.csr_cmd, _WIRE_1.csr_cmd connect issue_slots[15].in_uop.bits.flush_on_commit, _WIRE_1.flush_on_commit connect issue_slots[15].in_uop.bits.is_unique, _WIRE_1.is_unique connect issue_slots[15].in_uop.bits.uses_stq, _WIRE_1.uses_stq connect issue_slots[15].in_uop.bits.uses_ldq, _WIRE_1.uses_ldq connect issue_slots[15].in_uop.bits.mem_signed, _WIRE_1.mem_signed connect issue_slots[15].in_uop.bits.mem_size, _WIRE_1.mem_size connect issue_slots[15].in_uop.bits.mem_cmd, _WIRE_1.mem_cmd connect issue_slots[15].in_uop.bits.exc_cause, _WIRE_1.exc_cause connect issue_slots[15].in_uop.bits.exception, _WIRE_1.exception connect issue_slots[15].in_uop.bits.stale_pdst, _WIRE_1.stale_pdst connect issue_slots[15].in_uop.bits.ppred_busy, _WIRE_1.ppred_busy connect issue_slots[15].in_uop.bits.prs3_busy, _WIRE_1.prs3_busy connect issue_slots[15].in_uop.bits.prs2_busy, _WIRE_1.prs2_busy connect issue_slots[15].in_uop.bits.prs1_busy, _WIRE_1.prs1_busy connect issue_slots[15].in_uop.bits.ppred, _WIRE_1.ppred connect issue_slots[15].in_uop.bits.prs3, _WIRE_1.prs3 connect issue_slots[15].in_uop.bits.prs2, _WIRE_1.prs2 connect issue_slots[15].in_uop.bits.prs1, _WIRE_1.prs1 connect issue_slots[15].in_uop.bits.pdst, _WIRE_1.pdst connect issue_slots[15].in_uop.bits.rxq_idx, _WIRE_1.rxq_idx connect issue_slots[15].in_uop.bits.stq_idx, _WIRE_1.stq_idx connect issue_slots[15].in_uop.bits.ldq_idx, _WIRE_1.ldq_idx connect issue_slots[15].in_uop.bits.rob_idx, _WIRE_1.rob_idx connect issue_slots[15].in_uop.bits.fp_ctrl.vec, _WIRE_1.fp_ctrl.vec connect issue_slots[15].in_uop.bits.fp_ctrl.wflags, _WIRE_1.fp_ctrl.wflags connect issue_slots[15].in_uop.bits.fp_ctrl.sqrt, _WIRE_1.fp_ctrl.sqrt connect issue_slots[15].in_uop.bits.fp_ctrl.div, _WIRE_1.fp_ctrl.div connect issue_slots[15].in_uop.bits.fp_ctrl.fma, _WIRE_1.fp_ctrl.fma connect issue_slots[15].in_uop.bits.fp_ctrl.fastpipe, _WIRE_1.fp_ctrl.fastpipe connect issue_slots[15].in_uop.bits.fp_ctrl.toint, _WIRE_1.fp_ctrl.toint connect issue_slots[15].in_uop.bits.fp_ctrl.fromint, _WIRE_1.fp_ctrl.fromint connect issue_slots[15].in_uop.bits.fp_ctrl.typeTagOut, _WIRE_1.fp_ctrl.typeTagOut connect issue_slots[15].in_uop.bits.fp_ctrl.typeTagIn, _WIRE_1.fp_ctrl.typeTagIn connect issue_slots[15].in_uop.bits.fp_ctrl.swap23, _WIRE_1.fp_ctrl.swap23 connect issue_slots[15].in_uop.bits.fp_ctrl.swap12, _WIRE_1.fp_ctrl.swap12 connect issue_slots[15].in_uop.bits.fp_ctrl.ren3, _WIRE_1.fp_ctrl.ren3 connect issue_slots[15].in_uop.bits.fp_ctrl.ren2, _WIRE_1.fp_ctrl.ren2 connect issue_slots[15].in_uop.bits.fp_ctrl.ren1, _WIRE_1.fp_ctrl.ren1 connect issue_slots[15].in_uop.bits.fp_ctrl.wen, _WIRE_1.fp_ctrl.wen connect issue_slots[15].in_uop.bits.fp_ctrl.ldst, _WIRE_1.fp_ctrl.ldst connect issue_slots[15].in_uop.bits.op2_sel, _WIRE_1.op2_sel connect issue_slots[15].in_uop.bits.op1_sel, _WIRE_1.op1_sel connect issue_slots[15].in_uop.bits.imm_packed, _WIRE_1.imm_packed connect issue_slots[15].in_uop.bits.pimm, _WIRE_1.pimm connect issue_slots[15].in_uop.bits.imm_sel, _WIRE_1.imm_sel connect issue_slots[15].in_uop.bits.imm_rename, _WIRE_1.imm_rename connect issue_slots[15].in_uop.bits.taken, _WIRE_1.taken connect issue_slots[15].in_uop.bits.pc_lob, _WIRE_1.pc_lob connect issue_slots[15].in_uop.bits.edge_inst, _WIRE_1.edge_inst connect issue_slots[15].in_uop.bits.ftq_idx, _WIRE_1.ftq_idx connect issue_slots[15].in_uop.bits.is_mov, _WIRE_1.is_mov connect issue_slots[15].in_uop.bits.is_rocc, _WIRE_1.is_rocc connect issue_slots[15].in_uop.bits.is_sys_pc2epc, _WIRE_1.is_sys_pc2epc connect issue_slots[15].in_uop.bits.is_eret, _WIRE_1.is_eret connect issue_slots[15].in_uop.bits.is_amo, _WIRE_1.is_amo connect issue_slots[15].in_uop.bits.is_sfence, _WIRE_1.is_sfence connect issue_slots[15].in_uop.bits.is_fencei, _WIRE_1.is_fencei connect issue_slots[15].in_uop.bits.is_fence, _WIRE_1.is_fence connect issue_slots[15].in_uop.bits.is_sfb, _WIRE_1.is_sfb connect issue_slots[15].in_uop.bits.br_type, _WIRE_1.br_type connect issue_slots[15].in_uop.bits.br_tag, _WIRE_1.br_tag connect issue_slots[15].in_uop.bits.br_mask, _WIRE_1.br_mask connect issue_slots[15].in_uop.bits.dis_col_sel, _WIRE_1.dis_col_sel connect issue_slots[15].in_uop.bits.iw_p3_bypass_hint, _WIRE_1.iw_p3_bypass_hint connect issue_slots[15].in_uop.bits.iw_p2_bypass_hint, _WIRE_1.iw_p2_bypass_hint connect issue_slots[15].in_uop.bits.iw_p1_bypass_hint, _WIRE_1.iw_p1_bypass_hint connect issue_slots[15].in_uop.bits.iw_p2_speculative_child, _WIRE_1.iw_p2_speculative_child connect issue_slots[15].in_uop.bits.iw_p1_speculative_child, _WIRE_1.iw_p1_speculative_child connect issue_slots[15].in_uop.bits.iw_issued_partial_dgen, _WIRE_1.iw_issued_partial_dgen connect issue_slots[15].in_uop.bits.iw_issued_partial_agen, _WIRE_1.iw_issued_partial_agen connect issue_slots[15].in_uop.bits.iw_issued, _WIRE_1.iw_issued connect issue_slots[15].in_uop.bits.fu_code[0], _WIRE_1.fu_code[0] connect issue_slots[15].in_uop.bits.fu_code[1], _WIRE_1.fu_code[1] connect issue_slots[15].in_uop.bits.fu_code[2], _WIRE_1.fu_code[2] connect issue_slots[15].in_uop.bits.fu_code[3], _WIRE_1.fu_code[3] connect issue_slots[15].in_uop.bits.fu_code[4], _WIRE_1.fu_code[4] connect issue_slots[15].in_uop.bits.fu_code[5], _WIRE_1.fu_code[5] connect issue_slots[15].in_uop.bits.fu_code[6], _WIRE_1.fu_code[6] connect issue_slots[15].in_uop.bits.fu_code[7], _WIRE_1.fu_code[7] connect issue_slots[15].in_uop.bits.fu_code[8], _WIRE_1.fu_code[8] connect issue_slots[15].in_uop.bits.fu_code[9], _WIRE_1.fu_code[9] connect issue_slots[15].in_uop.bits.iq_type[0], _WIRE_1.iq_type[0] connect issue_slots[15].in_uop.bits.iq_type[1], _WIRE_1.iq_type[1] connect issue_slots[15].in_uop.bits.iq_type[2], _WIRE_1.iq_type[2] connect issue_slots[15].in_uop.bits.iq_type[3], _WIRE_1.iq_type[3] connect issue_slots[15].in_uop.bits.debug_pc, _WIRE_1.debug_pc connect issue_slots[15].in_uop.bits.is_rvc, _WIRE_1.is_rvc connect issue_slots[15].in_uop.bits.debug_inst, _WIRE_1.debug_inst connect issue_slots[15].in_uop.bits.inst, _WIRE_1.inst node _T_324 = eq(shamts_oh[18], UInt<3>(0h4)) when _T_324 : connect issue_slots[15].in_uop.valid, will_be_valid_18 connect issue_slots[15].in_uop.bits.debug_tsrc, _WIRE_2.debug_tsrc connect issue_slots[15].in_uop.bits.debug_fsrc, _WIRE_2.debug_fsrc connect issue_slots[15].in_uop.bits.bp_xcpt_if, _WIRE_2.bp_xcpt_if connect issue_slots[15].in_uop.bits.bp_debug_if, _WIRE_2.bp_debug_if connect issue_slots[15].in_uop.bits.xcpt_ma_if, _WIRE_2.xcpt_ma_if connect issue_slots[15].in_uop.bits.xcpt_ae_if, _WIRE_2.xcpt_ae_if connect issue_slots[15].in_uop.bits.xcpt_pf_if, _WIRE_2.xcpt_pf_if connect issue_slots[15].in_uop.bits.fp_typ, _WIRE_2.fp_typ connect issue_slots[15].in_uop.bits.fp_rm, _WIRE_2.fp_rm connect issue_slots[15].in_uop.bits.fp_val, _WIRE_2.fp_val connect issue_slots[15].in_uop.bits.fcn_op, _WIRE_2.fcn_op connect issue_slots[15].in_uop.bits.fcn_dw, _WIRE_2.fcn_dw connect issue_slots[15].in_uop.bits.frs3_en, _WIRE_2.frs3_en connect issue_slots[15].in_uop.bits.lrs2_rtype, _WIRE_2.lrs2_rtype connect issue_slots[15].in_uop.bits.lrs1_rtype, _WIRE_2.lrs1_rtype connect issue_slots[15].in_uop.bits.dst_rtype, _WIRE_2.dst_rtype connect issue_slots[15].in_uop.bits.lrs3, _WIRE_2.lrs3 connect issue_slots[15].in_uop.bits.lrs2, _WIRE_2.lrs2 connect issue_slots[15].in_uop.bits.lrs1, _WIRE_2.lrs1 connect issue_slots[15].in_uop.bits.ldst, _WIRE_2.ldst connect issue_slots[15].in_uop.bits.ldst_is_rs1, _WIRE_2.ldst_is_rs1 connect issue_slots[15].in_uop.bits.csr_cmd, _WIRE_2.csr_cmd connect issue_slots[15].in_uop.bits.flush_on_commit, _WIRE_2.flush_on_commit connect issue_slots[15].in_uop.bits.is_unique, _WIRE_2.is_unique connect issue_slots[15].in_uop.bits.uses_stq, _WIRE_2.uses_stq connect issue_slots[15].in_uop.bits.uses_ldq, _WIRE_2.uses_ldq connect issue_slots[15].in_uop.bits.mem_signed, _WIRE_2.mem_signed connect issue_slots[15].in_uop.bits.mem_size, _WIRE_2.mem_size connect issue_slots[15].in_uop.bits.mem_cmd, _WIRE_2.mem_cmd connect issue_slots[15].in_uop.bits.exc_cause, _WIRE_2.exc_cause connect issue_slots[15].in_uop.bits.exception, _WIRE_2.exception connect issue_slots[15].in_uop.bits.stale_pdst, _WIRE_2.stale_pdst connect issue_slots[15].in_uop.bits.ppred_busy, _WIRE_2.ppred_busy connect issue_slots[15].in_uop.bits.prs3_busy, _WIRE_2.prs3_busy connect issue_slots[15].in_uop.bits.prs2_busy, _WIRE_2.prs2_busy connect issue_slots[15].in_uop.bits.prs1_busy, _WIRE_2.prs1_busy connect issue_slots[15].in_uop.bits.ppred, _WIRE_2.ppred connect issue_slots[15].in_uop.bits.prs3, _WIRE_2.prs3 connect issue_slots[15].in_uop.bits.prs2, _WIRE_2.prs2 connect issue_slots[15].in_uop.bits.prs1, _WIRE_2.prs1 connect issue_slots[15].in_uop.bits.pdst, _WIRE_2.pdst connect issue_slots[15].in_uop.bits.rxq_idx, _WIRE_2.rxq_idx connect issue_slots[15].in_uop.bits.stq_idx, _WIRE_2.stq_idx connect issue_slots[15].in_uop.bits.ldq_idx, _WIRE_2.ldq_idx connect issue_slots[15].in_uop.bits.rob_idx, _WIRE_2.rob_idx connect issue_slots[15].in_uop.bits.fp_ctrl.vec, _WIRE_2.fp_ctrl.vec connect issue_slots[15].in_uop.bits.fp_ctrl.wflags, _WIRE_2.fp_ctrl.wflags connect issue_slots[15].in_uop.bits.fp_ctrl.sqrt, _WIRE_2.fp_ctrl.sqrt connect issue_slots[15].in_uop.bits.fp_ctrl.div, _WIRE_2.fp_ctrl.div connect issue_slots[15].in_uop.bits.fp_ctrl.fma, _WIRE_2.fp_ctrl.fma connect issue_slots[15].in_uop.bits.fp_ctrl.fastpipe, _WIRE_2.fp_ctrl.fastpipe connect issue_slots[15].in_uop.bits.fp_ctrl.toint, _WIRE_2.fp_ctrl.toint connect issue_slots[15].in_uop.bits.fp_ctrl.fromint, _WIRE_2.fp_ctrl.fromint connect issue_slots[15].in_uop.bits.fp_ctrl.typeTagOut, _WIRE_2.fp_ctrl.typeTagOut connect issue_slots[15].in_uop.bits.fp_ctrl.typeTagIn, _WIRE_2.fp_ctrl.typeTagIn connect issue_slots[15].in_uop.bits.fp_ctrl.swap23, _WIRE_2.fp_ctrl.swap23 connect issue_slots[15].in_uop.bits.fp_ctrl.swap12, _WIRE_2.fp_ctrl.swap12 connect issue_slots[15].in_uop.bits.fp_ctrl.ren3, _WIRE_2.fp_ctrl.ren3 connect issue_slots[15].in_uop.bits.fp_ctrl.ren2, _WIRE_2.fp_ctrl.ren2 connect issue_slots[15].in_uop.bits.fp_ctrl.ren1, _WIRE_2.fp_ctrl.ren1 connect issue_slots[15].in_uop.bits.fp_ctrl.wen, _WIRE_2.fp_ctrl.wen connect issue_slots[15].in_uop.bits.fp_ctrl.ldst, _WIRE_2.fp_ctrl.ldst connect issue_slots[15].in_uop.bits.op2_sel, _WIRE_2.op2_sel connect issue_slots[15].in_uop.bits.op1_sel, _WIRE_2.op1_sel connect issue_slots[15].in_uop.bits.imm_packed, _WIRE_2.imm_packed connect issue_slots[15].in_uop.bits.pimm, _WIRE_2.pimm connect issue_slots[15].in_uop.bits.imm_sel, _WIRE_2.imm_sel connect issue_slots[15].in_uop.bits.imm_rename, _WIRE_2.imm_rename connect issue_slots[15].in_uop.bits.taken, _WIRE_2.taken connect issue_slots[15].in_uop.bits.pc_lob, _WIRE_2.pc_lob connect issue_slots[15].in_uop.bits.edge_inst, _WIRE_2.edge_inst connect issue_slots[15].in_uop.bits.ftq_idx, _WIRE_2.ftq_idx connect issue_slots[15].in_uop.bits.is_mov, _WIRE_2.is_mov connect issue_slots[15].in_uop.bits.is_rocc, _WIRE_2.is_rocc connect issue_slots[15].in_uop.bits.is_sys_pc2epc, _WIRE_2.is_sys_pc2epc connect issue_slots[15].in_uop.bits.is_eret, _WIRE_2.is_eret connect issue_slots[15].in_uop.bits.is_amo, _WIRE_2.is_amo connect issue_slots[15].in_uop.bits.is_sfence, _WIRE_2.is_sfence connect issue_slots[15].in_uop.bits.is_fencei, _WIRE_2.is_fencei connect issue_slots[15].in_uop.bits.is_fence, _WIRE_2.is_fence connect issue_slots[15].in_uop.bits.is_sfb, _WIRE_2.is_sfb connect issue_slots[15].in_uop.bits.br_type, _WIRE_2.br_type connect issue_slots[15].in_uop.bits.br_tag, _WIRE_2.br_tag connect issue_slots[15].in_uop.bits.br_mask, _WIRE_2.br_mask connect issue_slots[15].in_uop.bits.dis_col_sel, _WIRE_2.dis_col_sel connect issue_slots[15].in_uop.bits.iw_p3_bypass_hint, _WIRE_2.iw_p3_bypass_hint connect issue_slots[15].in_uop.bits.iw_p2_bypass_hint, _WIRE_2.iw_p2_bypass_hint connect issue_slots[15].in_uop.bits.iw_p1_bypass_hint, _WIRE_2.iw_p1_bypass_hint connect issue_slots[15].in_uop.bits.iw_p2_speculative_child, _WIRE_2.iw_p2_speculative_child connect issue_slots[15].in_uop.bits.iw_p1_speculative_child, _WIRE_2.iw_p1_speculative_child connect issue_slots[15].in_uop.bits.iw_issued_partial_dgen, _WIRE_2.iw_issued_partial_dgen connect issue_slots[15].in_uop.bits.iw_issued_partial_agen, _WIRE_2.iw_issued_partial_agen connect issue_slots[15].in_uop.bits.iw_issued, _WIRE_2.iw_issued connect issue_slots[15].in_uop.bits.fu_code[0], _WIRE_2.fu_code[0] connect issue_slots[15].in_uop.bits.fu_code[1], _WIRE_2.fu_code[1] connect issue_slots[15].in_uop.bits.fu_code[2], _WIRE_2.fu_code[2] connect issue_slots[15].in_uop.bits.fu_code[3], _WIRE_2.fu_code[3] connect issue_slots[15].in_uop.bits.fu_code[4], _WIRE_2.fu_code[4] connect issue_slots[15].in_uop.bits.fu_code[5], _WIRE_2.fu_code[5] connect issue_slots[15].in_uop.bits.fu_code[6], _WIRE_2.fu_code[6] connect issue_slots[15].in_uop.bits.fu_code[7], _WIRE_2.fu_code[7] connect issue_slots[15].in_uop.bits.fu_code[8], _WIRE_2.fu_code[8] connect issue_slots[15].in_uop.bits.fu_code[9], _WIRE_2.fu_code[9] connect issue_slots[15].in_uop.bits.iq_type[0], _WIRE_2.iq_type[0] connect issue_slots[15].in_uop.bits.iq_type[1], _WIRE_2.iq_type[1] connect issue_slots[15].in_uop.bits.iq_type[2], _WIRE_2.iq_type[2] connect issue_slots[15].in_uop.bits.iq_type[3], _WIRE_2.iq_type[3] connect issue_slots[15].in_uop.bits.debug_pc, _WIRE_2.debug_pc connect issue_slots[15].in_uop.bits.is_rvc, _WIRE_2.is_rvc connect issue_slots[15].in_uop.bits.debug_inst, _WIRE_2.debug_inst connect issue_slots[15].in_uop.bits.inst, _WIRE_2.inst node _issue_slots_15_clear_T = neq(shamts_oh[15], UInt<1>(0h0)) connect issue_slots[15].clear, _issue_slots_15_clear_T reg is_available : UInt<1>[8], clock node _T_325 = eq(issue_slots[8].will_be_valid, UInt<1>(0h0)) node _T_326 = or(_T_325, issue_slots[8].clear) node _T_327 = eq(issue_slots[8].in_uop.valid, UInt<1>(0h0)) node _T_328 = and(_T_326, _T_327) node _T_329 = eq(issue_slots[9].will_be_valid, UInt<1>(0h0)) node _T_330 = or(_T_329, issue_slots[9].clear) node _T_331 = eq(issue_slots[9].in_uop.valid, UInt<1>(0h0)) node _T_332 = and(_T_330, _T_331) node _T_333 = eq(issue_slots[10].will_be_valid, UInt<1>(0h0)) node _T_334 = or(_T_333, issue_slots[10].clear) node _T_335 = eq(issue_slots[10].in_uop.valid, UInt<1>(0h0)) node _T_336 = and(_T_334, _T_335) node _T_337 = eq(issue_slots[11].will_be_valid, UInt<1>(0h0)) node _T_338 = or(_T_337, issue_slots[11].clear) node _T_339 = eq(issue_slots[11].in_uop.valid, UInt<1>(0h0)) node _T_340 = and(_T_338, _T_339) node _T_341 = eq(issue_slots[12].will_be_valid, UInt<1>(0h0)) node _T_342 = or(_T_341, issue_slots[12].clear) node _T_343 = eq(issue_slots[12].in_uop.valid, UInt<1>(0h0)) node _T_344 = and(_T_342, _T_343) node _T_345 = eq(issue_slots[13].will_be_valid, UInt<1>(0h0)) node _T_346 = or(_T_345, issue_slots[13].clear) node _T_347 = eq(issue_slots[13].in_uop.valid, UInt<1>(0h0)) node _T_348 = and(_T_346, _T_347) node _T_349 = eq(issue_slots[14].will_be_valid, UInt<1>(0h0)) node _T_350 = or(_T_349, issue_slots[14].clear) node _T_351 = eq(issue_slots[14].in_uop.valid, UInt<1>(0h0)) node _T_352 = and(_T_350, _T_351) node _T_353 = eq(issue_slots[15].will_be_valid, UInt<1>(0h0)) node _T_354 = or(_T_353, issue_slots[15].clear) node _T_355 = eq(issue_slots[15].in_uop.valid, UInt<1>(0h0)) node _T_356 = and(_T_354, _T_355) wire _WIRE_18 : UInt<1>[8] connect _WIRE_18[0], _T_328 connect _WIRE_18[1], _T_332 connect _WIRE_18[2], _T_336 connect _WIRE_18[3], _T_340 connect _WIRE_18[4], _T_344 connect _WIRE_18[5], _T_348 connect _WIRE_18[6], _T_352 connect _WIRE_18[7], _T_356 connect is_available, _WIRE_18 node _io_dis_uops_0_ready_T = add(is_available[0], is_available[1]) node _io_dis_uops_0_ready_T_1 = bits(_io_dis_uops_0_ready_T, 1, 0) node _io_dis_uops_0_ready_T_2 = add(is_available[2], is_available[3]) node _io_dis_uops_0_ready_T_3 = bits(_io_dis_uops_0_ready_T_2, 1, 0) node _io_dis_uops_0_ready_T_4 = add(_io_dis_uops_0_ready_T_1, _io_dis_uops_0_ready_T_3) node _io_dis_uops_0_ready_T_5 = bits(_io_dis_uops_0_ready_T_4, 2, 0) node _io_dis_uops_0_ready_T_6 = add(is_available[4], is_available[5]) node _io_dis_uops_0_ready_T_7 = bits(_io_dis_uops_0_ready_T_6, 1, 0) node _io_dis_uops_0_ready_T_8 = add(is_available[6], is_available[7]) node _io_dis_uops_0_ready_T_9 = bits(_io_dis_uops_0_ready_T_8, 1, 0) node _io_dis_uops_0_ready_T_10 = add(_io_dis_uops_0_ready_T_7, _io_dis_uops_0_ready_T_9) node _io_dis_uops_0_ready_T_11 = bits(_io_dis_uops_0_ready_T_10, 2, 0) node _io_dis_uops_0_ready_T_12 = add(_io_dis_uops_0_ready_T_5, _io_dis_uops_0_ready_T_11) node _io_dis_uops_0_ready_T_13 = bits(_io_dis_uops_0_ready_T_12, 3, 0) node _io_dis_uops_0_ready_T_14 = and(io.dis_uops[0].ready, io.dis_uops[0].valid) node _io_dis_uops_0_ready_T_15 = and(io.dis_uops[1].ready, io.dis_uops[1].valid) node _io_dis_uops_0_ready_T_16 = and(io.dis_uops[2].ready, io.dis_uops[2].valid) node _io_dis_uops_0_ready_T_17 = add(_io_dis_uops_0_ready_T_15, _io_dis_uops_0_ready_T_16) node _io_dis_uops_0_ready_T_18 = bits(_io_dis_uops_0_ready_T_17, 1, 0) node _io_dis_uops_0_ready_T_19 = add(_io_dis_uops_0_ready_T_14, _io_dis_uops_0_ready_T_18) node _io_dis_uops_0_ready_T_20 = bits(_io_dis_uops_0_ready_T_19, 1, 0) node _io_dis_uops_0_ready_T_21 = add(UInt<3>(0h0), _io_dis_uops_0_ready_T_20) node _io_dis_uops_0_ready_T_22 = tail(_io_dis_uops_0_ready_T_21, 1) node _io_dis_uops_0_ready_T_23 = gt(_io_dis_uops_0_ready_T_13, _io_dis_uops_0_ready_T_22) reg io_dis_uops_0_ready_REG : UInt<1>, clock connect io_dis_uops_0_ready_REG, _io_dis_uops_0_ready_T_23 connect io.dis_uops[0].ready, io_dis_uops_0_ready_REG node _T_357 = eq(io.dis_uops[0].ready, UInt<1>(0h0)) node _T_358 = shr(shamts_oh[16], 0) node _T_359 = neq(_T_358, UInt<1>(0h0)) node _T_360 = or(_T_357, _T_359) node _T_361 = asUInt(reset) node _T_362 = eq(_T_361, UInt<1>(0h0)) when _T_362 : node _T_363 = eq(_T_360, UInt<1>(0h0)) when _T_363 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-unit-age-ordered.scala:214 assert (!io.dis_uops(w).ready || (shamts_oh(w+numIssueSlots) >> w) =/= 0.U)\n") : printf_4 assert(clock, _T_360, UInt<1>(0h1), "") : assert_4 node _io_dis_uops_1_ready_T = add(is_available[0], is_available[1]) node _io_dis_uops_1_ready_T_1 = bits(_io_dis_uops_1_ready_T, 1, 0) node _io_dis_uops_1_ready_T_2 = add(is_available[2], is_available[3]) node _io_dis_uops_1_ready_T_3 = bits(_io_dis_uops_1_ready_T_2, 1, 0) node _io_dis_uops_1_ready_T_4 = add(_io_dis_uops_1_ready_T_1, _io_dis_uops_1_ready_T_3) node _io_dis_uops_1_ready_T_5 = bits(_io_dis_uops_1_ready_T_4, 2, 0) node _io_dis_uops_1_ready_T_6 = add(is_available[4], is_available[5]) node _io_dis_uops_1_ready_T_7 = bits(_io_dis_uops_1_ready_T_6, 1, 0) node _io_dis_uops_1_ready_T_8 = add(is_available[6], is_available[7]) node _io_dis_uops_1_ready_T_9 = bits(_io_dis_uops_1_ready_T_8, 1, 0) node _io_dis_uops_1_ready_T_10 = add(_io_dis_uops_1_ready_T_7, _io_dis_uops_1_ready_T_9) node _io_dis_uops_1_ready_T_11 = bits(_io_dis_uops_1_ready_T_10, 2, 0) node _io_dis_uops_1_ready_T_12 = add(_io_dis_uops_1_ready_T_5, _io_dis_uops_1_ready_T_11) node _io_dis_uops_1_ready_T_13 = bits(_io_dis_uops_1_ready_T_12, 3, 0) node _io_dis_uops_1_ready_T_14 = and(io.dis_uops[0].ready, io.dis_uops[0].valid) node _io_dis_uops_1_ready_T_15 = and(io.dis_uops[1].ready, io.dis_uops[1].valid) node _io_dis_uops_1_ready_T_16 = and(io.dis_uops[2].ready, io.dis_uops[2].valid) node _io_dis_uops_1_ready_T_17 = add(_io_dis_uops_1_ready_T_15, _io_dis_uops_1_ready_T_16) node _io_dis_uops_1_ready_T_18 = bits(_io_dis_uops_1_ready_T_17, 1, 0) node _io_dis_uops_1_ready_T_19 = add(_io_dis_uops_1_ready_T_14, _io_dis_uops_1_ready_T_18) node _io_dis_uops_1_ready_T_20 = bits(_io_dis_uops_1_ready_T_19, 1, 0) node _io_dis_uops_1_ready_T_21 = add(UInt<3>(0h1), _io_dis_uops_1_ready_T_20) node _io_dis_uops_1_ready_T_22 = tail(_io_dis_uops_1_ready_T_21, 1) node _io_dis_uops_1_ready_T_23 = gt(_io_dis_uops_1_ready_T_13, _io_dis_uops_1_ready_T_22) reg io_dis_uops_1_ready_REG : UInt<1>, clock connect io_dis_uops_1_ready_REG, _io_dis_uops_1_ready_T_23 connect io.dis_uops[1].ready, io_dis_uops_1_ready_REG node _T_364 = eq(io.dis_uops[1].ready, UInt<1>(0h0)) node _T_365 = shr(shamts_oh[17], 1) node _T_366 = neq(_T_365, UInt<1>(0h0)) node _T_367 = or(_T_364, _T_366) node _T_368 = asUInt(reset) node _T_369 = eq(_T_368, UInt<1>(0h0)) when _T_369 : node _T_370 = eq(_T_367, UInt<1>(0h0)) when _T_370 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-unit-age-ordered.scala:214 assert (!io.dis_uops(w).ready || (shamts_oh(w+numIssueSlots) >> w) =/= 0.U)\n") : printf_5 assert(clock, _T_367, UInt<1>(0h1), "") : assert_5 node _io_dis_uops_2_ready_T = add(is_available[0], is_available[1]) node _io_dis_uops_2_ready_T_1 = bits(_io_dis_uops_2_ready_T, 1, 0) node _io_dis_uops_2_ready_T_2 = add(is_available[2], is_available[3]) node _io_dis_uops_2_ready_T_3 = bits(_io_dis_uops_2_ready_T_2, 1, 0) node _io_dis_uops_2_ready_T_4 = add(_io_dis_uops_2_ready_T_1, _io_dis_uops_2_ready_T_3) node _io_dis_uops_2_ready_T_5 = bits(_io_dis_uops_2_ready_T_4, 2, 0) node _io_dis_uops_2_ready_T_6 = add(is_available[4], is_available[5]) node _io_dis_uops_2_ready_T_7 = bits(_io_dis_uops_2_ready_T_6, 1, 0) node _io_dis_uops_2_ready_T_8 = add(is_available[6], is_available[7]) node _io_dis_uops_2_ready_T_9 = bits(_io_dis_uops_2_ready_T_8, 1, 0) node _io_dis_uops_2_ready_T_10 = add(_io_dis_uops_2_ready_T_7, _io_dis_uops_2_ready_T_9) node _io_dis_uops_2_ready_T_11 = bits(_io_dis_uops_2_ready_T_10, 2, 0) node _io_dis_uops_2_ready_T_12 = add(_io_dis_uops_2_ready_T_5, _io_dis_uops_2_ready_T_11) node _io_dis_uops_2_ready_T_13 = bits(_io_dis_uops_2_ready_T_12, 3, 0) node _io_dis_uops_2_ready_T_14 = and(io.dis_uops[0].ready, io.dis_uops[0].valid) node _io_dis_uops_2_ready_T_15 = and(io.dis_uops[1].ready, io.dis_uops[1].valid) node _io_dis_uops_2_ready_T_16 = and(io.dis_uops[2].ready, io.dis_uops[2].valid) node _io_dis_uops_2_ready_T_17 = add(_io_dis_uops_2_ready_T_15, _io_dis_uops_2_ready_T_16) node _io_dis_uops_2_ready_T_18 = bits(_io_dis_uops_2_ready_T_17, 1, 0) node _io_dis_uops_2_ready_T_19 = add(_io_dis_uops_2_ready_T_14, _io_dis_uops_2_ready_T_18) node _io_dis_uops_2_ready_T_20 = bits(_io_dis_uops_2_ready_T_19, 1, 0) node _io_dis_uops_2_ready_T_21 = add(UInt<3>(0h2), _io_dis_uops_2_ready_T_20) node _io_dis_uops_2_ready_T_22 = tail(_io_dis_uops_2_ready_T_21, 1) node _io_dis_uops_2_ready_T_23 = gt(_io_dis_uops_2_ready_T_13, _io_dis_uops_2_ready_T_22) reg io_dis_uops_2_ready_REG : UInt<1>, clock connect io_dis_uops_2_ready_REG, _io_dis_uops_2_ready_T_23 connect io.dis_uops[2].ready, io_dis_uops_2_ready_REG node _T_371 = eq(io.dis_uops[2].ready, UInt<1>(0h0)) node _T_372 = shr(shamts_oh[18], 2) node _T_373 = neq(_T_372, UInt<1>(0h0)) node _T_374 = or(_T_371, _T_373) node _T_375 = asUInt(reset) node _T_376 = eq(_T_375, UInt<1>(0h0)) when _T_376 : node _T_377 = eq(_T_374, UInt<1>(0h0)) when _T_377 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-unit-age-ordered.scala:214 assert (!io.dis_uops(w).ready || (shamts_oh(w+numIssueSlots) >> w) =/= 0.U)\n") : printf_6 assert(clock, _T_374, UInt<1>(0h1), "") : assert_6 wire iss_uops : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}[1] connect iss_uops[0].valid, UInt<1>(0h0) invalidate iss_uops[0].bits.debug_tsrc invalidate iss_uops[0].bits.debug_fsrc invalidate iss_uops[0].bits.bp_xcpt_if invalidate iss_uops[0].bits.bp_debug_if invalidate iss_uops[0].bits.xcpt_ma_if invalidate iss_uops[0].bits.xcpt_ae_if invalidate iss_uops[0].bits.xcpt_pf_if invalidate iss_uops[0].bits.fp_typ invalidate iss_uops[0].bits.fp_rm invalidate iss_uops[0].bits.fp_val invalidate iss_uops[0].bits.fcn_op invalidate iss_uops[0].bits.fcn_dw invalidate iss_uops[0].bits.frs3_en invalidate iss_uops[0].bits.lrs2_rtype invalidate iss_uops[0].bits.lrs1_rtype invalidate iss_uops[0].bits.dst_rtype invalidate iss_uops[0].bits.lrs3 invalidate iss_uops[0].bits.lrs2 invalidate iss_uops[0].bits.lrs1 invalidate iss_uops[0].bits.ldst invalidate iss_uops[0].bits.ldst_is_rs1 invalidate iss_uops[0].bits.csr_cmd invalidate iss_uops[0].bits.flush_on_commit invalidate iss_uops[0].bits.is_unique invalidate iss_uops[0].bits.uses_stq invalidate iss_uops[0].bits.uses_ldq invalidate iss_uops[0].bits.mem_signed invalidate iss_uops[0].bits.mem_size invalidate iss_uops[0].bits.mem_cmd invalidate iss_uops[0].bits.exc_cause invalidate iss_uops[0].bits.exception invalidate iss_uops[0].bits.stale_pdst invalidate iss_uops[0].bits.ppred_busy invalidate iss_uops[0].bits.prs3_busy invalidate iss_uops[0].bits.prs2_busy invalidate iss_uops[0].bits.prs1_busy invalidate iss_uops[0].bits.ppred invalidate iss_uops[0].bits.prs3 invalidate iss_uops[0].bits.prs2 invalidate iss_uops[0].bits.prs1 invalidate iss_uops[0].bits.pdst invalidate iss_uops[0].bits.rxq_idx invalidate iss_uops[0].bits.stq_idx invalidate iss_uops[0].bits.ldq_idx invalidate iss_uops[0].bits.rob_idx invalidate iss_uops[0].bits.fp_ctrl.vec invalidate iss_uops[0].bits.fp_ctrl.wflags invalidate iss_uops[0].bits.fp_ctrl.sqrt invalidate iss_uops[0].bits.fp_ctrl.div invalidate iss_uops[0].bits.fp_ctrl.fma invalidate iss_uops[0].bits.fp_ctrl.fastpipe invalidate iss_uops[0].bits.fp_ctrl.toint invalidate iss_uops[0].bits.fp_ctrl.fromint invalidate iss_uops[0].bits.fp_ctrl.typeTagOut invalidate iss_uops[0].bits.fp_ctrl.typeTagIn invalidate iss_uops[0].bits.fp_ctrl.swap23 invalidate iss_uops[0].bits.fp_ctrl.swap12 invalidate iss_uops[0].bits.fp_ctrl.ren3 invalidate iss_uops[0].bits.fp_ctrl.ren2 invalidate iss_uops[0].bits.fp_ctrl.ren1 invalidate iss_uops[0].bits.fp_ctrl.wen invalidate iss_uops[0].bits.fp_ctrl.ldst invalidate iss_uops[0].bits.op2_sel invalidate iss_uops[0].bits.op1_sel invalidate iss_uops[0].bits.imm_packed invalidate iss_uops[0].bits.pimm invalidate iss_uops[0].bits.imm_sel invalidate iss_uops[0].bits.imm_rename invalidate iss_uops[0].bits.taken invalidate iss_uops[0].bits.pc_lob invalidate iss_uops[0].bits.edge_inst invalidate iss_uops[0].bits.ftq_idx invalidate iss_uops[0].bits.is_mov invalidate iss_uops[0].bits.is_rocc invalidate iss_uops[0].bits.is_sys_pc2epc invalidate iss_uops[0].bits.is_eret invalidate iss_uops[0].bits.is_amo invalidate iss_uops[0].bits.is_sfence invalidate iss_uops[0].bits.is_fencei invalidate iss_uops[0].bits.is_fence invalidate iss_uops[0].bits.is_sfb invalidate iss_uops[0].bits.br_type invalidate iss_uops[0].bits.br_tag invalidate iss_uops[0].bits.br_mask invalidate iss_uops[0].bits.dis_col_sel invalidate iss_uops[0].bits.iw_p3_bypass_hint invalidate iss_uops[0].bits.iw_p2_bypass_hint invalidate iss_uops[0].bits.iw_p1_bypass_hint invalidate iss_uops[0].bits.iw_p2_speculative_child invalidate iss_uops[0].bits.iw_p1_speculative_child invalidate iss_uops[0].bits.iw_issued_partial_dgen invalidate iss_uops[0].bits.iw_issued_partial_agen invalidate iss_uops[0].bits.iw_issued invalidate iss_uops[0].bits.fu_code[0] invalidate iss_uops[0].bits.fu_code[1] invalidate iss_uops[0].bits.fu_code[2] invalidate iss_uops[0].bits.fu_code[3] invalidate iss_uops[0].bits.fu_code[4] invalidate iss_uops[0].bits.fu_code[5] invalidate iss_uops[0].bits.fu_code[6] invalidate iss_uops[0].bits.fu_code[7] invalidate iss_uops[0].bits.fu_code[8] invalidate iss_uops[0].bits.fu_code[9] invalidate iss_uops[0].bits.iq_type[0] invalidate iss_uops[0].bits.iq_type[1] invalidate iss_uops[0].bits.iq_type[2] invalidate iss_uops[0].bits.iq_type[3] invalidate iss_uops[0].bits.debug_pc invalidate iss_uops[0].bits.is_rvc invalidate iss_uops[0].bits.debug_inst invalidate iss_uops[0].bits.inst connect issue_slots[0].grant, UInt<1>(0h0) node _fu_code_match_T = and(issue_slots[0].iss_uop.fu_code[0], io.fu_types[0][0]) node _fu_code_match_T_1 = and(issue_slots[0].iss_uop.fu_code[1], io.fu_types[0][1]) node _fu_code_match_T_2 = and(issue_slots[0].iss_uop.fu_code[2], io.fu_types[0][2]) node _fu_code_match_T_3 = and(issue_slots[0].iss_uop.fu_code[3], io.fu_types[0][3]) node _fu_code_match_T_4 = and(issue_slots[0].iss_uop.fu_code[4], io.fu_types[0][4]) node _fu_code_match_T_5 = and(issue_slots[0].iss_uop.fu_code[5], io.fu_types[0][5]) node _fu_code_match_T_6 = and(issue_slots[0].iss_uop.fu_code[6], io.fu_types[0][6]) node _fu_code_match_T_7 = and(issue_slots[0].iss_uop.fu_code[7], io.fu_types[0][7]) node _fu_code_match_T_8 = and(issue_slots[0].iss_uop.fu_code[8], io.fu_types[0][8]) node _fu_code_match_T_9 = and(issue_slots[0].iss_uop.fu_code[9], io.fu_types[0][9]) node _fu_code_match_T_10 = or(_fu_code_match_T, _fu_code_match_T_1) node _fu_code_match_T_11 = or(_fu_code_match_T_10, _fu_code_match_T_2) node _fu_code_match_T_12 = or(_fu_code_match_T_11, _fu_code_match_T_3) node _fu_code_match_T_13 = or(_fu_code_match_T_12, _fu_code_match_T_4) node _fu_code_match_T_14 = or(_fu_code_match_T_13, _fu_code_match_T_5) node _fu_code_match_T_15 = or(_fu_code_match_T_14, _fu_code_match_T_6) node _fu_code_match_T_16 = or(_fu_code_match_T_15, _fu_code_match_T_7) node _fu_code_match_T_17 = or(_fu_code_match_T_16, _fu_code_match_T_8) node fu_code_match = or(_fu_code_match_T_17, _fu_code_match_T_9) node can_allocate = and(fu_code_match, UInt<1>(0h1)) node _T_378 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_379 = and(issue_slots[0].request, _T_378) node _T_380 = and(_T_379, can_allocate) node _T_381 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_382 = and(_T_380, _T_381) when _T_382 : connect issue_slots[0].grant, UInt<1>(0h1) connect iss_uops[0].valid, UInt<1>(0h1) connect iss_uops[0].bits, issue_slots[0].iss_uop node _T_383 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_384 = and(issue_slots[0].request, _T_383) node _T_385 = and(_T_384, can_allocate) node _T_386 = or(_T_385, UInt<1>(0h0)) node _T_387 = and(issue_slots[0].request, can_allocate) node _T_388 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_389 = and(_T_387, _T_388) node _T_390 = or(_T_389, UInt<1>(0h0)) connect issue_slots[1].grant, UInt<1>(0h0) node _fu_code_match_T_18 = and(issue_slots[1].iss_uop.fu_code[0], io.fu_types[0][0]) node _fu_code_match_T_19 = and(issue_slots[1].iss_uop.fu_code[1], io.fu_types[0][1]) node _fu_code_match_T_20 = and(issue_slots[1].iss_uop.fu_code[2], io.fu_types[0][2]) node _fu_code_match_T_21 = and(issue_slots[1].iss_uop.fu_code[3], io.fu_types[0][3]) node _fu_code_match_T_22 = and(issue_slots[1].iss_uop.fu_code[4], io.fu_types[0][4]) node _fu_code_match_T_23 = and(issue_slots[1].iss_uop.fu_code[5], io.fu_types[0][5]) node _fu_code_match_T_24 = and(issue_slots[1].iss_uop.fu_code[6], io.fu_types[0][6]) node _fu_code_match_T_25 = and(issue_slots[1].iss_uop.fu_code[7], io.fu_types[0][7]) node _fu_code_match_T_26 = and(issue_slots[1].iss_uop.fu_code[8], io.fu_types[0][8]) node _fu_code_match_T_27 = and(issue_slots[1].iss_uop.fu_code[9], io.fu_types[0][9]) node _fu_code_match_T_28 = or(_fu_code_match_T_18, _fu_code_match_T_19) node _fu_code_match_T_29 = or(_fu_code_match_T_28, _fu_code_match_T_20) node _fu_code_match_T_30 = or(_fu_code_match_T_29, _fu_code_match_T_21) node _fu_code_match_T_31 = or(_fu_code_match_T_30, _fu_code_match_T_22) node _fu_code_match_T_32 = or(_fu_code_match_T_31, _fu_code_match_T_23) node _fu_code_match_T_33 = or(_fu_code_match_T_32, _fu_code_match_T_24) node _fu_code_match_T_34 = or(_fu_code_match_T_33, _fu_code_match_T_25) node _fu_code_match_T_35 = or(_fu_code_match_T_34, _fu_code_match_T_26) node fu_code_match_1 = or(_fu_code_match_T_35, _fu_code_match_T_27) node can_allocate_1 = and(fu_code_match_1, UInt<1>(0h1)) node _T_391 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_392 = and(issue_slots[1].request, _T_391) node _T_393 = and(_T_392, can_allocate_1) node _T_394 = eq(_T_386, UInt<1>(0h0)) node _T_395 = and(_T_393, _T_394) when _T_395 : connect issue_slots[1].grant, UInt<1>(0h1) connect iss_uops[0].valid, UInt<1>(0h1) connect iss_uops[0].bits, issue_slots[1].iss_uop node _T_396 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_397 = and(issue_slots[1].request, _T_396) node _T_398 = and(_T_397, can_allocate_1) node _T_399 = or(_T_398, _T_386) node _T_400 = and(issue_slots[1].request, can_allocate_1) node _T_401 = eq(_T_386, UInt<1>(0h0)) node _T_402 = and(_T_400, _T_401) node _T_403 = or(_T_402, UInt<1>(0h0)) connect issue_slots[2].grant, UInt<1>(0h0) node _fu_code_match_T_36 = and(issue_slots[2].iss_uop.fu_code[0], io.fu_types[0][0]) node _fu_code_match_T_37 = and(issue_slots[2].iss_uop.fu_code[1], io.fu_types[0][1]) node _fu_code_match_T_38 = and(issue_slots[2].iss_uop.fu_code[2], io.fu_types[0][2]) node _fu_code_match_T_39 = and(issue_slots[2].iss_uop.fu_code[3], io.fu_types[0][3]) node _fu_code_match_T_40 = and(issue_slots[2].iss_uop.fu_code[4], io.fu_types[0][4]) node _fu_code_match_T_41 = and(issue_slots[2].iss_uop.fu_code[5], io.fu_types[0][5]) node _fu_code_match_T_42 = and(issue_slots[2].iss_uop.fu_code[6], io.fu_types[0][6]) node _fu_code_match_T_43 = and(issue_slots[2].iss_uop.fu_code[7], io.fu_types[0][7]) node _fu_code_match_T_44 = and(issue_slots[2].iss_uop.fu_code[8], io.fu_types[0][8]) node _fu_code_match_T_45 = and(issue_slots[2].iss_uop.fu_code[9], io.fu_types[0][9]) node _fu_code_match_T_46 = or(_fu_code_match_T_36, _fu_code_match_T_37) node _fu_code_match_T_47 = or(_fu_code_match_T_46, _fu_code_match_T_38) node _fu_code_match_T_48 = or(_fu_code_match_T_47, _fu_code_match_T_39) node _fu_code_match_T_49 = or(_fu_code_match_T_48, _fu_code_match_T_40) node _fu_code_match_T_50 = or(_fu_code_match_T_49, _fu_code_match_T_41) node _fu_code_match_T_51 = or(_fu_code_match_T_50, _fu_code_match_T_42) node _fu_code_match_T_52 = or(_fu_code_match_T_51, _fu_code_match_T_43) node _fu_code_match_T_53 = or(_fu_code_match_T_52, _fu_code_match_T_44) node fu_code_match_2 = or(_fu_code_match_T_53, _fu_code_match_T_45) node can_allocate_2 = and(fu_code_match_2, UInt<1>(0h1)) node _T_404 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_405 = and(issue_slots[2].request, _T_404) node _T_406 = and(_T_405, can_allocate_2) node _T_407 = eq(_T_399, UInt<1>(0h0)) node _T_408 = and(_T_406, _T_407) when _T_408 : connect issue_slots[2].grant, UInt<1>(0h1) connect iss_uops[0].valid, UInt<1>(0h1) connect iss_uops[0].bits, issue_slots[2].iss_uop node _T_409 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_410 = and(issue_slots[2].request, _T_409) node _T_411 = and(_T_410, can_allocate_2) node _T_412 = or(_T_411, _T_399) node _T_413 = and(issue_slots[2].request, can_allocate_2) node _T_414 = eq(_T_399, UInt<1>(0h0)) node _T_415 = and(_T_413, _T_414) node _T_416 = or(_T_415, UInt<1>(0h0)) connect issue_slots[3].grant, UInt<1>(0h0) node _fu_code_match_T_54 = and(issue_slots[3].iss_uop.fu_code[0], io.fu_types[0][0]) node _fu_code_match_T_55 = and(issue_slots[3].iss_uop.fu_code[1], io.fu_types[0][1]) node _fu_code_match_T_56 = and(issue_slots[3].iss_uop.fu_code[2], io.fu_types[0][2]) node _fu_code_match_T_57 = and(issue_slots[3].iss_uop.fu_code[3], io.fu_types[0][3]) node _fu_code_match_T_58 = and(issue_slots[3].iss_uop.fu_code[4], io.fu_types[0][4]) node _fu_code_match_T_59 = and(issue_slots[3].iss_uop.fu_code[5], io.fu_types[0][5]) node _fu_code_match_T_60 = and(issue_slots[3].iss_uop.fu_code[6], io.fu_types[0][6]) node _fu_code_match_T_61 = and(issue_slots[3].iss_uop.fu_code[7], io.fu_types[0][7]) node _fu_code_match_T_62 = and(issue_slots[3].iss_uop.fu_code[8], io.fu_types[0][8]) node _fu_code_match_T_63 = and(issue_slots[3].iss_uop.fu_code[9], io.fu_types[0][9]) node _fu_code_match_T_64 = or(_fu_code_match_T_54, _fu_code_match_T_55) node _fu_code_match_T_65 = or(_fu_code_match_T_64, _fu_code_match_T_56) node _fu_code_match_T_66 = or(_fu_code_match_T_65, _fu_code_match_T_57) node _fu_code_match_T_67 = or(_fu_code_match_T_66, _fu_code_match_T_58) node _fu_code_match_T_68 = or(_fu_code_match_T_67, _fu_code_match_T_59) node _fu_code_match_T_69 = or(_fu_code_match_T_68, _fu_code_match_T_60) node _fu_code_match_T_70 = or(_fu_code_match_T_69, _fu_code_match_T_61) node _fu_code_match_T_71 = or(_fu_code_match_T_70, _fu_code_match_T_62) node fu_code_match_3 = or(_fu_code_match_T_71, _fu_code_match_T_63) node can_allocate_3 = and(fu_code_match_3, UInt<1>(0h1)) node _T_417 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_418 = and(issue_slots[3].request, _T_417) node _T_419 = and(_T_418, can_allocate_3) node _T_420 = eq(_T_412, UInt<1>(0h0)) node _T_421 = and(_T_419, _T_420) when _T_421 : connect issue_slots[3].grant, UInt<1>(0h1) connect iss_uops[0].valid, UInt<1>(0h1) connect iss_uops[0].bits, issue_slots[3].iss_uop node _T_422 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_423 = and(issue_slots[3].request, _T_422) node _T_424 = and(_T_423, can_allocate_3) node _T_425 = or(_T_424, _T_412) node _T_426 = and(issue_slots[3].request, can_allocate_3) node _T_427 = eq(_T_412, UInt<1>(0h0)) node _T_428 = and(_T_426, _T_427) node _T_429 = or(_T_428, UInt<1>(0h0)) connect issue_slots[4].grant, UInt<1>(0h0) node _fu_code_match_T_72 = and(issue_slots[4].iss_uop.fu_code[0], io.fu_types[0][0]) node _fu_code_match_T_73 = and(issue_slots[4].iss_uop.fu_code[1], io.fu_types[0][1]) node _fu_code_match_T_74 = and(issue_slots[4].iss_uop.fu_code[2], io.fu_types[0][2]) node _fu_code_match_T_75 = and(issue_slots[4].iss_uop.fu_code[3], io.fu_types[0][3]) node _fu_code_match_T_76 = and(issue_slots[4].iss_uop.fu_code[4], io.fu_types[0][4]) node _fu_code_match_T_77 = and(issue_slots[4].iss_uop.fu_code[5], io.fu_types[0][5]) node _fu_code_match_T_78 = and(issue_slots[4].iss_uop.fu_code[6], io.fu_types[0][6]) node _fu_code_match_T_79 = and(issue_slots[4].iss_uop.fu_code[7], io.fu_types[0][7]) node _fu_code_match_T_80 = and(issue_slots[4].iss_uop.fu_code[8], io.fu_types[0][8]) node _fu_code_match_T_81 = and(issue_slots[4].iss_uop.fu_code[9], io.fu_types[0][9]) node _fu_code_match_T_82 = or(_fu_code_match_T_72, _fu_code_match_T_73) node _fu_code_match_T_83 = or(_fu_code_match_T_82, _fu_code_match_T_74) node _fu_code_match_T_84 = or(_fu_code_match_T_83, _fu_code_match_T_75) node _fu_code_match_T_85 = or(_fu_code_match_T_84, _fu_code_match_T_76) node _fu_code_match_T_86 = or(_fu_code_match_T_85, _fu_code_match_T_77) node _fu_code_match_T_87 = or(_fu_code_match_T_86, _fu_code_match_T_78) node _fu_code_match_T_88 = or(_fu_code_match_T_87, _fu_code_match_T_79) node _fu_code_match_T_89 = or(_fu_code_match_T_88, _fu_code_match_T_80) node fu_code_match_4 = or(_fu_code_match_T_89, _fu_code_match_T_81) node can_allocate_4 = and(fu_code_match_4, UInt<1>(0h1)) node _T_430 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_431 = and(issue_slots[4].request, _T_430) node _T_432 = and(_T_431, can_allocate_4) node _T_433 = eq(_T_425, UInt<1>(0h0)) node _T_434 = and(_T_432, _T_433) when _T_434 : connect issue_slots[4].grant, UInt<1>(0h1) connect iss_uops[0].valid, UInt<1>(0h1) connect iss_uops[0].bits, issue_slots[4].iss_uop node _T_435 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_436 = and(issue_slots[4].request, _T_435) node _T_437 = and(_T_436, can_allocate_4) node _T_438 = or(_T_437, _T_425) node _T_439 = and(issue_slots[4].request, can_allocate_4) node _T_440 = eq(_T_425, UInt<1>(0h0)) node _T_441 = and(_T_439, _T_440) node _T_442 = or(_T_441, UInt<1>(0h0)) connect issue_slots[5].grant, UInt<1>(0h0) node _fu_code_match_T_90 = and(issue_slots[5].iss_uop.fu_code[0], io.fu_types[0][0]) node _fu_code_match_T_91 = and(issue_slots[5].iss_uop.fu_code[1], io.fu_types[0][1]) node _fu_code_match_T_92 = and(issue_slots[5].iss_uop.fu_code[2], io.fu_types[0][2]) node _fu_code_match_T_93 = and(issue_slots[5].iss_uop.fu_code[3], io.fu_types[0][3]) node _fu_code_match_T_94 = and(issue_slots[5].iss_uop.fu_code[4], io.fu_types[0][4]) node _fu_code_match_T_95 = and(issue_slots[5].iss_uop.fu_code[5], io.fu_types[0][5]) node _fu_code_match_T_96 = and(issue_slots[5].iss_uop.fu_code[6], io.fu_types[0][6]) node _fu_code_match_T_97 = and(issue_slots[5].iss_uop.fu_code[7], io.fu_types[0][7]) node _fu_code_match_T_98 = and(issue_slots[5].iss_uop.fu_code[8], io.fu_types[0][8]) node _fu_code_match_T_99 = and(issue_slots[5].iss_uop.fu_code[9], io.fu_types[0][9]) node _fu_code_match_T_100 = or(_fu_code_match_T_90, _fu_code_match_T_91) node _fu_code_match_T_101 = or(_fu_code_match_T_100, _fu_code_match_T_92) node _fu_code_match_T_102 = or(_fu_code_match_T_101, _fu_code_match_T_93) node _fu_code_match_T_103 = or(_fu_code_match_T_102, _fu_code_match_T_94) node _fu_code_match_T_104 = or(_fu_code_match_T_103, _fu_code_match_T_95) node _fu_code_match_T_105 = or(_fu_code_match_T_104, _fu_code_match_T_96) node _fu_code_match_T_106 = or(_fu_code_match_T_105, _fu_code_match_T_97) node _fu_code_match_T_107 = or(_fu_code_match_T_106, _fu_code_match_T_98) node fu_code_match_5 = or(_fu_code_match_T_107, _fu_code_match_T_99) node can_allocate_5 = and(fu_code_match_5, UInt<1>(0h1)) node _T_443 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_444 = and(issue_slots[5].request, _T_443) node _T_445 = and(_T_444, can_allocate_5) node _T_446 = eq(_T_438, UInt<1>(0h0)) node _T_447 = and(_T_445, _T_446) when _T_447 : connect issue_slots[5].grant, UInt<1>(0h1) connect iss_uops[0].valid, UInt<1>(0h1) connect iss_uops[0].bits, issue_slots[5].iss_uop node _T_448 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_449 = and(issue_slots[5].request, _T_448) node _T_450 = and(_T_449, can_allocate_5) node _T_451 = or(_T_450, _T_438) node _T_452 = and(issue_slots[5].request, can_allocate_5) node _T_453 = eq(_T_438, UInt<1>(0h0)) node _T_454 = and(_T_452, _T_453) node _T_455 = or(_T_454, UInt<1>(0h0)) connect issue_slots[6].grant, UInt<1>(0h0) node _fu_code_match_T_108 = and(issue_slots[6].iss_uop.fu_code[0], io.fu_types[0][0]) node _fu_code_match_T_109 = and(issue_slots[6].iss_uop.fu_code[1], io.fu_types[0][1]) node _fu_code_match_T_110 = and(issue_slots[6].iss_uop.fu_code[2], io.fu_types[0][2]) node _fu_code_match_T_111 = and(issue_slots[6].iss_uop.fu_code[3], io.fu_types[0][3]) node _fu_code_match_T_112 = and(issue_slots[6].iss_uop.fu_code[4], io.fu_types[0][4]) node _fu_code_match_T_113 = and(issue_slots[6].iss_uop.fu_code[5], io.fu_types[0][5]) node _fu_code_match_T_114 = and(issue_slots[6].iss_uop.fu_code[6], io.fu_types[0][6]) node _fu_code_match_T_115 = and(issue_slots[6].iss_uop.fu_code[7], io.fu_types[0][7]) node _fu_code_match_T_116 = and(issue_slots[6].iss_uop.fu_code[8], io.fu_types[0][8]) node _fu_code_match_T_117 = and(issue_slots[6].iss_uop.fu_code[9], io.fu_types[0][9]) node _fu_code_match_T_118 = or(_fu_code_match_T_108, _fu_code_match_T_109) node _fu_code_match_T_119 = or(_fu_code_match_T_118, _fu_code_match_T_110) node _fu_code_match_T_120 = or(_fu_code_match_T_119, _fu_code_match_T_111) node _fu_code_match_T_121 = or(_fu_code_match_T_120, _fu_code_match_T_112) node _fu_code_match_T_122 = or(_fu_code_match_T_121, _fu_code_match_T_113) node _fu_code_match_T_123 = or(_fu_code_match_T_122, _fu_code_match_T_114) node _fu_code_match_T_124 = or(_fu_code_match_T_123, _fu_code_match_T_115) node _fu_code_match_T_125 = or(_fu_code_match_T_124, _fu_code_match_T_116) node fu_code_match_6 = or(_fu_code_match_T_125, _fu_code_match_T_117) node can_allocate_6 = and(fu_code_match_6, UInt<1>(0h1)) node _T_456 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_457 = and(issue_slots[6].request, _T_456) node _T_458 = and(_T_457, can_allocate_6) node _T_459 = eq(_T_451, UInt<1>(0h0)) node _T_460 = and(_T_458, _T_459) when _T_460 : connect issue_slots[6].grant, UInt<1>(0h1) connect iss_uops[0].valid, UInt<1>(0h1) connect iss_uops[0].bits, issue_slots[6].iss_uop node _T_461 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_462 = and(issue_slots[6].request, _T_461) node _T_463 = and(_T_462, can_allocate_6) node _T_464 = or(_T_463, _T_451) node _T_465 = and(issue_slots[6].request, can_allocate_6) node _T_466 = eq(_T_451, UInt<1>(0h0)) node _T_467 = and(_T_465, _T_466) node _T_468 = or(_T_467, UInt<1>(0h0)) connect issue_slots[7].grant, UInt<1>(0h0) node _fu_code_match_T_126 = and(issue_slots[7].iss_uop.fu_code[0], io.fu_types[0][0]) node _fu_code_match_T_127 = and(issue_slots[7].iss_uop.fu_code[1], io.fu_types[0][1]) node _fu_code_match_T_128 = and(issue_slots[7].iss_uop.fu_code[2], io.fu_types[0][2]) node _fu_code_match_T_129 = and(issue_slots[7].iss_uop.fu_code[3], io.fu_types[0][3]) node _fu_code_match_T_130 = and(issue_slots[7].iss_uop.fu_code[4], io.fu_types[0][4]) node _fu_code_match_T_131 = and(issue_slots[7].iss_uop.fu_code[5], io.fu_types[0][5]) node _fu_code_match_T_132 = and(issue_slots[7].iss_uop.fu_code[6], io.fu_types[0][6]) node _fu_code_match_T_133 = and(issue_slots[7].iss_uop.fu_code[7], io.fu_types[0][7]) node _fu_code_match_T_134 = and(issue_slots[7].iss_uop.fu_code[8], io.fu_types[0][8]) node _fu_code_match_T_135 = and(issue_slots[7].iss_uop.fu_code[9], io.fu_types[0][9]) node _fu_code_match_T_136 = or(_fu_code_match_T_126, _fu_code_match_T_127) node _fu_code_match_T_137 = or(_fu_code_match_T_136, _fu_code_match_T_128) node _fu_code_match_T_138 = or(_fu_code_match_T_137, _fu_code_match_T_129) node _fu_code_match_T_139 = or(_fu_code_match_T_138, _fu_code_match_T_130) node _fu_code_match_T_140 = or(_fu_code_match_T_139, _fu_code_match_T_131) node _fu_code_match_T_141 = or(_fu_code_match_T_140, _fu_code_match_T_132) node _fu_code_match_T_142 = or(_fu_code_match_T_141, _fu_code_match_T_133) node _fu_code_match_T_143 = or(_fu_code_match_T_142, _fu_code_match_T_134) node fu_code_match_7 = or(_fu_code_match_T_143, _fu_code_match_T_135) node can_allocate_7 = and(fu_code_match_7, UInt<1>(0h1)) node _T_469 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_470 = and(issue_slots[7].request, _T_469) node _T_471 = and(_T_470, can_allocate_7) node _T_472 = eq(_T_464, UInt<1>(0h0)) node _T_473 = and(_T_471, _T_472) when _T_473 : connect issue_slots[7].grant, UInt<1>(0h1) connect iss_uops[0].valid, UInt<1>(0h1) connect iss_uops[0].bits, issue_slots[7].iss_uop node _T_474 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_475 = and(issue_slots[7].request, _T_474) node _T_476 = and(_T_475, can_allocate_7) node _T_477 = or(_T_476, _T_464) node _T_478 = and(issue_slots[7].request, can_allocate_7) node _T_479 = eq(_T_464, UInt<1>(0h0)) node _T_480 = and(_T_478, _T_479) node _T_481 = or(_T_480, UInt<1>(0h0)) connect issue_slots[8].grant, UInt<1>(0h0) node _fu_code_match_T_144 = and(issue_slots[8].iss_uop.fu_code[0], io.fu_types[0][0]) node _fu_code_match_T_145 = and(issue_slots[8].iss_uop.fu_code[1], io.fu_types[0][1]) node _fu_code_match_T_146 = and(issue_slots[8].iss_uop.fu_code[2], io.fu_types[0][2]) node _fu_code_match_T_147 = and(issue_slots[8].iss_uop.fu_code[3], io.fu_types[0][3]) node _fu_code_match_T_148 = and(issue_slots[8].iss_uop.fu_code[4], io.fu_types[0][4]) node _fu_code_match_T_149 = and(issue_slots[8].iss_uop.fu_code[5], io.fu_types[0][5]) node _fu_code_match_T_150 = and(issue_slots[8].iss_uop.fu_code[6], io.fu_types[0][6]) node _fu_code_match_T_151 = and(issue_slots[8].iss_uop.fu_code[7], io.fu_types[0][7]) node _fu_code_match_T_152 = and(issue_slots[8].iss_uop.fu_code[8], io.fu_types[0][8]) node _fu_code_match_T_153 = and(issue_slots[8].iss_uop.fu_code[9], io.fu_types[0][9]) node _fu_code_match_T_154 = or(_fu_code_match_T_144, _fu_code_match_T_145) node _fu_code_match_T_155 = or(_fu_code_match_T_154, _fu_code_match_T_146) node _fu_code_match_T_156 = or(_fu_code_match_T_155, _fu_code_match_T_147) node _fu_code_match_T_157 = or(_fu_code_match_T_156, _fu_code_match_T_148) node _fu_code_match_T_158 = or(_fu_code_match_T_157, _fu_code_match_T_149) node _fu_code_match_T_159 = or(_fu_code_match_T_158, _fu_code_match_T_150) node _fu_code_match_T_160 = or(_fu_code_match_T_159, _fu_code_match_T_151) node _fu_code_match_T_161 = or(_fu_code_match_T_160, _fu_code_match_T_152) node fu_code_match_8 = or(_fu_code_match_T_161, _fu_code_match_T_153) node can_allocate_8 = and(fu_code_match_8, UInt<1>(0h1)) node _T_482 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_483 = and(issue_slots[8].request, _T_482) node _T_484 = and(_T_483, can_allocate_8) node _T_485 = eq(_T_477, UInt<1>(0h0)) node _T_486 = and(_T_484, _T_485) when _T_486 : connect issue_slots[8].grant, UInt<1>(0h1) connect iss_uops[0].valid, UInt<1>(0h1) connect iss_uops[0].bits, issue_slots[8].iss_uop node _T_487 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_488 = and(issue_slots[8].request, _T_487) node _T_489 = and(_T_488, can_allocate_8) node _T_490 = or(_T_489, _T_477) node _T_491 = and(issue_slots[8].request, can_allocate_8) node _T_492 = eq(_T_477, UInt<1>(0h0)) node _T_493 = and(_T_491, _T_492) node _T_494 = or(_T_493, UInt<1>(0h0)) connect issue_slots[9].grant, UInt<1>(0h0) node _fu_code_match_T_162 = and(issue_slots[9].iss_uop.fu_code[0], io.fu_types[0][0]) node _fu_code_match_T_163 = and(issue_slots[9].iss_uop.fu_code[1], io.fu_types[0][1]) node _fu_code_match_T_164 = and(issue_slots[9].iss_uop.fu_code[2], io.fu_types[0][2]) node _fu_code_match_T_165 = and(issue_slots[9].iss_uop.fu_code[3], io.fu_types[0][3]) node _fu_code_match_T_166 = and(issue_slots[9].iss_uop.fu_code[4], io.fu_types[0][4]) node _fu_code_match_T_167 = and(issue_slots[9].iss_uop.fu_code[5], io.fu_types[0][5]) node _fu_code_match_T_168 = and(issue_slots[9].iss_uop.fu_code[6], io.fu_types[0][6]) node _fu_code_match_T_169 = and(issue_slots[9].iss_uop.fu_code[7], io.fu_types[0][7]) node _fu_code_match_T_170 = and(issue_slots[9].iss_uop.fu_code[8], io.fu_types[0][8]) node _fu_code_match_T_171 = and(issue_slots[9].iss_uop.fu_code[9], io.fu_types[0][9]) node _fu_code_match_T_172 = or(_fu_code_match_T_162, _fu_code_match_T_163) node _fu_code_match_T_173 = or(_fu_code_match_T_172, _fu_code_match_T_164) node _fu_code_match_T_174 = or(_fu_code_match_T_173, _fu_code_match_T_165) node _fu_code_match_T_175 = or(_fu_code_match_T_174, _fu_code_match_T_166) node _fu_code_match_T_176 = or(_fu_code_match_T_175, _fu_code_match_T_167) node _fu_code_match_T_177 = or(_fu_code_match_T_176, _fu_code_match_T_168) node _fu_code_match_T_178 = or(_fu_code_match_T_177, _fu_code_match_T_169) node _fu_code_match_T_179 = or(_fu_code_match_T_178, _fu_code_match_T_170) node fu_code_match_9 = or(_fu_code_match_T_179, _fu_code_match_T_171) node can_allocate_9 = and(fu_code_match_9, UInt<1>(0h1)) node _T_495 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_496 = and(issue_slots[9].request, _T_495) node _T_497 = and(_T_496, can_allocate_9) node _T_498 = eq(_T_490, UInt<1>(0h0)) node _T_499 = and(_T_497, _T_498) when _T_499 : connect issue_slots[9].grant, UInt<1>(0h1) connect iss_uops[0].valid, UInt<1>(0h1) connect iss_uops[0].bits, issue_slots[9].iss_uop node _T_500 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_501 = and(issue_slots[9].request, _T_500) node _T_502 = and(_T_501, can_allocate_9) node _T_503 = or(_T_502, _T_490) node _T_504 = and(issue_slots[9].request, can_allocate_9) node _T_505 = eq(_T_490, UInt<1>(0h0)) node _T_506 = and(_T_504, _T_505) node _T_507 = or(_T_506, UInt<1>(0h0)) connect issue_slots[10].grant, UInt<1>(0h0) node _fu_code_match_T_180 = and(issue_slots[10].iss_uop.fu_code[0], io.fu_types[0][0]) node _fu_code_match_T_181 = and(issue_slots[10].iss_uop.fu_code[1], io.fu_types[0][1]) node _fu_code_match_T_182 = and(issue_slots[10].iss_uop.fu_code[2], io.fu_types[0][2]) node _fu_code_match_T_183 = and(issue_slots[10].iss_uop.fu_code[3], io.fu_types[0][3]) node _fu_code_match_T_184 = and(issue_slots[10].iss_uop.fu_code[4], io.fu_types[0][4]) node _fu_code_match_T_185 = and(issue_slots[10].iss_uop.fu_code[5], io.fu_types[0][5]) node _fu_code_match_T_186 = and(issue_slots[10].iss_uop.fu_code[6], io.fu_types[0][6]) node _fu_code_match_T_187 = and(issue_slots[10].iss_uop.fu_code[7], io.fu_types[0][7]) node _fu_code_match_T_188 = and(issue_slots[10].iss_uop.fu_code[8], io.fu_types[0][8]) node _fu_code_match_T_189 = and(issue_slots[10].iss_uop.fu_code[9], io.fu_types[0][9]) node _fu_code_match_T_190 = or(_fu_code_match_T_180, _fu_code_match_T_181) node _fu_code_match_T_191 = or(_fu_code_match_T_190, _fu_code_match_T_182) node _fu_code_match_T_192 = or(_fu_code_match_T_191, _fu_code_match_T_183) node _fu_code_match_T_193 = or(_fu_code_match_T_192, _fu_code_match_T_184) node _fu_code_match_T_194 = or(_fu_code_match_T_193, _fu_code_match_T_185) node _fu_code_match_T_195 = or(_fu_code_match_T_194, _fu_code_match_T_186) node _fu_code_match_T_196 = or(_fu_code_match_T_195, _fu_code_match_T_187) node _fu_code_match_T_197 = or(_fu_code_match_T_196, _fu_code_match_T_188) node fu_code_match_10 = or(_fu_code_match_T_197, _fu_code_match_T_189) node can_allocate_10 = and(fu_code_match_10, UInt<1>(0h1)) node _T_508 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_509 = and(issue_slots[10].request, _T_508) node _T_510 = and(_T_509, can_allocate_10) node _T_511 = eq(_T_503, UInt<1>(0h0)) node _T_512 = and(_T_510, _T_511) when _T_512 : connect issue_slots[10].grant, UInt<1>(0h1) connect iss_uops[0].valid, UInt<1>(0h1) connect iss_uops[0].bits, issue_slots[10].iss_uop node _T_513 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_514 = and(issue_slots[10].request, _T_513) node _T_515 = and(_T_514, can_allocate_10) node _T_516 = or(_T_515, _T_503) node _T_517 = and(issue_slots[10].request, can_allocate_10) node _T_518 = eq(_T_503, UInt<1>(0h0)) node _T_519 = and(_T_517, _T_518) node _T_520 = or(_T_519, UInt<1>(0h0)) connect issue_slots[11].grant, UInt<1>(0h0) node _fu_code_match_T_198 = and(issue_slots[11].iss_uop.fu_code[0], io.fu_types[0][0]) node _fu_code_match_T_199 = and(issue_slots[11].iss_uop.fu_code[1], io.fu_types[0][1]) node _fu_code_match_T_200 = and(issue_slots[11].iss_uop.fu_code[2], io.fu_types[0][2]) node _fu_code_match_T_201 = and(issue_slots[11].iss_uop.fu_code[3], io.fu_types[0][3]) node _fu_code_match_T_202 = and(issue_slots[11].iss_uop.fu_code[4], io.fu_types[0][4]) node _fu_code_match_T_203 = and(issue_slots[11].iss_uop.fu_code[5], io.fu_types[0][5]) node _fu_code_match_T_204 = and(issue_slots[11].iss_uop.fu_code[6], io.fu_types[0][6]) node _fu_code_match_T_205 = and(issue_slots[11].iss_uop.fu_code[7], io.fu_types[0][7]) node _fu_code_match_T_206 = and(issue_slots[11].iss_uop.fu_code[8], io.fu_types[0][8]) node _fu_code_match_T_207 = and(issue_slots[11].iss_uop.fu_code[9], io.fu_types[0][9]) node _fu_code_match_T_208 = or(_fu_code_match_T_198, _fu_code_match_T_199) node _fu_code_match_T_209 = or(_fu_code_match_T_208, _fu_code_match_T_200) node _fu_code_match_T_210 = or(_fu_code_match_T_209, _fu_code_match_T_201) node _fu_code_match_T_211 = or(_fu_code_match_T_210, _fu_code_match_T_202) node _fu_code_match_T_212 = or(_fu_code_match_T_211, _fu_code_match_T_203) node _fu_code_match_T_213 = or(_fu_code_match_T_212, _fu_code_match_T_204) node _fu_code_match_T_214 = or(_fu_code_match_T_213, _fu_code_match_T_205) node _fu_code_match_T_215 = or(_fu_code_match_T_214, _fu_code_match_T_206) node fu_code_match_11 = or(_fu_code_match_T_215, _fu_code_match_T_207) node can_allocate_11 = and(fu_code_match_11, UInt<1>(0h1)) node _T_521 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_522 = and(issue_slots[11].request, _T_521) node _T_523 = and(_T_522, can_allocate_11) node _T_524 = eq(_T_516, UInt<1>(0h0)) node _T_525 = and(_T_523, _T_524) when _T_525 : connect issue_slots[11].grant, UInt<1>(0h1) connect iss_uops[0].valid, UInt<1>(0h1) connect iss_uops[0].bits, issue_slots[11].iss_uop node _T_526 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_527 = and(issue_slots[11].request, _T_526) node _T_528 = and(_T_527, can_allocate_11) node _T_529 = or(_T_528, _T_516) node _T_530 = and(issue_slots[11].request, can_allocate_11) node _T_531 = eq(_T_516, UInt<1>(0h0)) node _T_532 = and(_T_530, _T_531) node _T_533 = or(_T_532, UInt<1>(0h0)) connect issue_slots[12].grant, UInt<1>(0h0) node _fu_code_match_T_216 = and(issue_slots[12].iss_uop.fu_code[0], io.fu_types[0][0]) node _fu_code_match_T_217 = and(issue_slots[12].iss_uop.fu_code[1], io.fu_types[0][1]) node _fu_code_match_T_218 = and(issue_slots[12].iss_uop.fu_code[2], io.fu_types[0][2]) node _fu_code_match_T_219 = and(issue_slots[12].iss_uop.fu_code[3], io.fu_types[0][3]) node _fu_code_match_T_220 = and(issue_slots[12].iss_uop.fu_code[4], io.fu_types[0][4]) node _fu_code_match_T_221 = and(issue_slots[12].iss_uop.fu_code[5], io.fu_types[0][5]) node _fu_code_match_T_222 = and(issue_slots[12].iss_uop.fu_code[6], io.fu_types[0][6]) node _fu_code_match_T_223 = and(issue_slots[12].iss_uop.fu_code[7], io.fu_types[0][7]) node _fu_code_match_T_224 = and(issue_slots[12].iss_uop.fu_code[8], io.fu_types[0][8]) node _fu_code_match_T_225 = and(issue_slots[12].iss_uop.fu_code[9], io.fu_types[0][9]) node _fu_code_match_T_226 = or(_fu_code_match_T_216, _fu_code_match_T_217) node _fu_code_match_T_227 = or(_fu_code_match_T_226, _fu_code_match_T_218) node _fu_code_match_T_228 = or(_fu_code_match_T_227, _fu_code_match_T_219) node _fu_code_match_T_229 = or(_fu_code_match_T_228, _fu_code_match_T_220) node _fu_code_match_T_230 = or(_fu_code_match_T_229, _fu_code_match_T_221) node _fu_code_match_T_231 = or(_fu_code_match_T_230, _fu_code_match_T_222) node _fu_code_match_T_232 = or(_fu_code_match_T_231, _fu_code_match_T_223) node _fu_code_match_T_233 = or(_fu_code_match_T_232, _fu_code_match_T_224) node fu_code_match_12 = or(_fu_code_match_T_233, _fu_code_match_T_225) node can_allocate_12 = and(fu_code_match_12, UInt<1>(0h1)) node _T_534 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_535 = and(issue_slots[12].request, _T_534) node _T_536 = and(_T_535, can_allocate_12) node _T_537 = eq(_T_529, UInt<1>(0h0)) node _T_538 = and(_T_536, _T_537) when _T_538 : connect issue_slots[12].grant, UInt<1>(0h1) connect iss_uops[0].valid, UInt<1>(0h1) connect iss_uops[0].bits, issue_slots[12].iss_uop node _T_539 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_540 = and(issue_slots[12].request, _T_539) node _T_541 = and(_T_540, can_allocate_12) node _T_542 = or(_T_541, _T_529) node _T_543 = and(issue_slots[12].request, can_allocate_12) node _T_544 = eq(_T_529, UInt<1>(0h0)) node _T_545 = and(_T_543, _T_544) node _T_546 = or(_T_545, UInt<1>(0h0)) connect issue_slots[13].grant, UInt<1>(0h0) node _fu_code_match_T_234 = and(issue_slots[13].iss_uop.fu_code[0], io.fu_types[0][0]) node _fu_code_match_T_235 = and(issue_slots[13].iss_uop.fu_code[1], io.fu_types[0][1]) node _fu_code_match_T_236 = and(issue_slots[13].iss_uop.fu_code[2], io.fu_types[0][2]) node _fu_code_match_T_237 = and(issue_slots[13].iss_uop.fu_code[3], io.fu_types[0][3]) node _fu_code_match_T_238 = and(issue_slots[13].iss_uop.fu_code[4], io.fu_types[0][4]) node _fu_code_match_T_239 = and(issue_slots[13].iss_uop.fu_code[5], io.fu_types[0][5]) node _fu_code_match_T_240 = and(issue_slots[13].iss_uop.fu_code[6], io.fu_types[0][6]) node _fu_code_match_T_241 = and(issue_slots[13].iss_uop.fu_code[7], io.fu_types[0][7]) node _fu_code_match_T_242 = and(issue_slots[13].iss_uop.fu_code[8], io.fu_types[0][8]) node _fu_code_match_T_243 = and(issue_slots[13].iss_uop.fu_code[9], io.fu_types[0][9]) node _fu_code_match_T_244 = or(_fu_code_match_T_234, _fu_code_match_T_235) node _fu_code_match_T_245 = or(_fu_code_match_T_244, _fu_code_match_T_236) node _fu_code_match_T_246 = or(_fu_code_match_T_245, _fu_code_match_T_237) node _fu_code_match_T_247 = or(_fu_code_match_T_246, _fu_code_match_T_238) node _fu_code_match_T_248 = or(_fu_code_match_T_247, _fu_code_match_T_239) node _fu_code_match_T_249 = or(_fu_code_match_T_248, _fu_code_match_T_240) node _fu_code_match_T_250 = or(_fu_code_match_T_249, _fu_code_match_T_241) node _fu_code_match_T_251 = or(_fu_code_match_T_250, _fu_code_match_T_242) node fu_code_match_13 = or(_fu_code_match_T_251, _fu_code_match_T_243) node can_allocate_13 = and(fu_code_match_13, UInt<1>(0h1)) node _T_547 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_548 = and(issue_slots[13].request, _T_547) node _T_549 = and(_T_548, can_allocate_13) node _T_550 = eq(_T_542, UInt<1>(0h0)) node _T_551 = and(_T_549, _T_550) when _T_551 : connect issue_slots[13].grant, UInt<1>(0h1) connect iss_uops[0].valid, UInt<1>(0h1) connect iss_uops[0].bits, issue_slots[13].iss_uop node _T_552 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_553 = and(issue_slots[13].request, _T_552) node _T_554 = and(_T_553, can_allocate_13) node _T_555 = or(_T_554, _T_542) node _T_556 = and(issue_slots[13].request, can_allocate_13) node _T_557 = eq(_T_542, UInt<1>(0h0)) node _T_558 = and(_T_556, _T_557) node _T_559 = or(_T_558, UInt<1>(0h0)) connect issue_slots[14].grant, UInt<1>(0h0) node _fu_code_match_T_252 = and(issue_slots[14].iss_uop.fu_code[0], io.fu_types[0][0]) node _fu_code_match_T_253 = and(issue_slots[14].iss_uop.fu_code[1], io.fu_types[0][1]) node _fu_code_match_T_254 = and(issue_slots[14].iss_uop.fu_code[2], io.fu_types[0][2]) node _fu_code_match_T_255 = and(issue_slots[14].iss_uop.fu_code[3], io.fu_types[0][3]) node _fu_code_match_T_256 = and(issue_slots[14].iss_uop.fu_code[4], io.fu_types[0][4]) node _fu_code_match_T_257 = and(issue_slots[14].iss_uop.fu_code[5], io.fu_types[0][5]) node _fu_code_match_T_258 = and(issue_slots[14].iss_uop.fu_code[6], io.fu_types[0][6]) node _fu_code_match_T_259 = and(issue_slots[14].iss_uop.fu_code[7], io.fu_types[0][7]) node _fu_code_match_T_260 = and(issue_slots[14].iss_uop.fu_code[8], io.fu_types[0][8]) node _fu_code_match_T_261 = and(issue_slots[14].iss_uop.fu_code[9], io.fu_types[0][9]) node _fu_code_match_T_262 = or(_fu_code_match_T_252, _fu_code_match_T_253) node _fu_code_match_T_263 = or(_fu_code_match_T_262, _fu_code_match_T_254) node _fu_code_match_T_264 = or(_fu_code_match_T_263, _fu_code_match_T_255) node _fu_code_match_T_265 = or(_fu_code_match_T_264, _fu_code_match_T_256) node _fu_code_match_T_266 = or(_fu_code_match_T_265, _fu_code_match_T_257) node _fu_code_match_T_267 = or(_fu_code_match_T_266, _fu_code_match_T_258) node _fu_code_match_T_268 = or(_fu_code_match_T_267, _fu_code_match_T_259) node _fu_code_match_T_269 = or(_fu_code_match_T_268, _fu_code_match_T_260) node fu_code_match_14 = or(_fu_code_match_T_269, _fu_code_match_T_261) node can_allocate_14 = and(fu_code_match_14, UInt<1>(0h1)) node _T_560 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_561 = and(issue_slots[14].request, _T_560) node _T_562 = and(_T_561, can_allocate_14) node _T_563 = eq(_T_555, UInt<1>(0h0)) node _T_564 = and(_T_562, _T_563) when _T_564 : connect issue_slots[14].grant, UInt<1>(0h1) connect iss_uops[0].valid, UInt<1>(0h1) connect iss_uops[0].bits, issue_slots[14].iss_uop node _T_565 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_566 = and(issue_slots[14].request, _T_565) node _T_567 = and(_T_566, can_allocate_14) node _T_568 = or(_T_567, _T_555) node _T_569 = and(issue_slots[14].request, can_allocate_14) node _T_570 = eq(_T_555, UInt<1>(0h0)) node _T_571 = and(_T_569, _T_570) node _T_572 = or(_T_571, UInt<1>(0h0)) connect issue_slots[15].grant, UInt<1>(0h0) node _fu_code_match_T_270 = and(issue_slots[15].iss_uop.fu_code[0], io.fu_types[0][0]) node _fu_code_match_T_271 = and(issue_slots[15].iss_uop.fu_code[1], io.fu_types[0][1]) node _fu_code_match_T_272 = and(issue_slots[15].iss_uop.fu_code[2], io.fu_types[0][2]) node _fu_code_match_T_273 = and(issue_slots[15].iss_uop.fu_code[3], io.fu_types[0][3]) node _fu_code_match_T_274 = and(issue_slots[15].iss_uop.fu_code[4], io.fu_types[0][4]) node _fu_code_match_T_275 = and(issue_slots[15].iss_uop.fu_code[5], io.fu_types[0][5]) node _fu_code_match_T_276 = and(issue_slots[15].iss_uop.fu_code[6], io.fu_types[0][6]) node _fu_code_match_T_277 = and(issue_slots[15].iss_uop.fu_code[7], io.fu_types[0][7]) node _fu_code_match_T_278 = and(issue_slots[15].iss_uop.fu_code[8], io.fu_types[0][8]) node _fu_code_match_T_279 = and(issue_slots[15].iss_uop.fu_code[9], io.fu_types[0][9]) node _fu_code_match_T_280 = or(_fu_code_match_T_270, _fu_code_match_T_271) node _fu_code_match_T_281 = or(_fu_code_match_T_280, _fu_code_match_T_272) node _fu_code_match_T_282 = or(_fu_code_match_T_281, _fu_code_match_T_273) node _fu_code_match_T_283 = or(_fu_code_match_T_282, _fu_code_match_T_274) node _fu_code_match_T_284 = or(_fu_code_match_T_283, _fu_code_match_T_275) node _fu_code_match_T_285 = or(_fu_code_match_T_284, _fu_code_match_T_276) node _fu_code_match_T_286 = or(_fu_code_match_T_285, _fu_code_match_T_277) node _fu_code_match_T_287 = or(_fu_code_match_T_286, _fu_code_match_T_278) node fu_code_match_15 = or(_fu_code_match_T_287, _fu_code_match_T_279) node can_allocate_15 = and(fu_code_match_15, UInt<1>(0h1)) node _T_573 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_574 = and(issue_slots[15].request, _T_573) node _T_575 = and(_T_574, can_allocate_15) node _T_576 = eq(_T_568, UInt<1>(0h0)) node _T_577 = and(_T_575, _T_576) when _T_577 : connect issue_slots[15].grant, UInt<1>(0h1) connect iss_uops[0].valid, UInt<1>(0h1) connect iss_uops[0].bits, issue_slots[15].iss_uop node _T_578 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_579 = and(issue_slots[15].request, _T_578) node _T_580 = and(_T_579, can_allocate_15) node _T_581 = or(_T_580, _T_568) node _T_582 = and(issue_slots[15].request, can_allocate_15) node _T_583 = eq(_T_568, UInt<1>(0h0)) node _T_584 = and(_T_582, _T_583) node _T_585 = or(_T_584, UInt<1>(0h0)) connect io.iss_uops, iss_uops when io.squash_grant : connect io.iss_uops[0].valid, UInt<1>(0h0)
module IssueUnitCollapsing_2( // @[issue-unit-age-ordered.scala:22:7] input clock, // @[issue-unit-age-ordered.scala:22:7] input reset, // @[issue-unit-age-ordered.scala:22:7] output io_dis_uops_0_ready, // @[issue-unit.scala:44:14] input io_dis_uops_0_valid, // @[issue-unit.scala:44:14] input [31:0] io_dis_uops_0_bits_inst, // @[issue-unit.scala:44:14] input [31:0] io_dis_uops_0_bits_debug_inst, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_rvc, // @[issue-unit.scala:44:14] input [39:0] io_dis_uops_0_bits_debug_pc, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iq_type_0, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iq_type_1, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iq_type_2, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iq_type_3, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_0, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_1, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_2, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_3, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_4, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_5, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_6, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_7, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_8, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_9, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iw_issued, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iw_issued_partial_agen, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iw_issued_partial_dgen, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_iw_p1_speculative_child, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_iw_p2_speculative_child, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_dis_col_sel, // @[issue-unit.scala:44:14] input [15:0] io_dis_uops_0_bits_br_mask, // @[issue-unit.scala:44:14] input [3:0] io_dis_uops_0_bits_br_tag, // @[issue-unit.scala:44:14] input [3:0] io_dis_uops_0_bits_br_type, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_sfb, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_fence, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_fencei, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_sfence, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_amo, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_eret, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_sys_pc2epc, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_rocc, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_mov, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_0_bits_ftq_idx, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_edge_inst, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_0_bits_pc_lob, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_taken, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_imm_rename, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_imm_sel, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_0_bits_pimm, // @[issue-unit.scala:44:14] input [19:0] io_dis_uops_0_bits_imm_packed, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_op1_sel, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_op2_sel, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_ldst, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_wen, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_ren1, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_ren2, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_ren3, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_swap12, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_swap23, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_fromint, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_toint, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_fma, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_div, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_wflags, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_vec, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_0_bits_rob_idx, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_0_bits_ldq_idx, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_0_bits_stq_idx, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_rxq_idx, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_0_bits_pdst, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_0_bits_prs1, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_0_bits_prs2, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_0_bits_prs3, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_0_bits_ppred, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_prs1_busy, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_prs2_busy, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_prs3_busy, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_ppred_busy, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_0_bits_stale_pdst, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_exception, // @[issue-unit.scala:44:14] input [63:0] io_dis_uops_0_bits_exc_cause, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_0_bits_mem_cmd, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_mem_size, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_mem_signed, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_uses_ldq, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_uses_stq, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_unique, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_flush_on_commit, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_csr_cmd, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_ldst_is_rs1, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_0_bits_ldst, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_0_bits_lrs1, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_0_bits_lrs2, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_0_bits_lrs3, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_dst_rtype, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_lrs1_rtype, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_lrs2_rtype, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_frs3_en, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fcn_dw, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_0_bits_fcn_op, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_val, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_fp_rm, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_fp_typ, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_xcpt_pf_if, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_xcpt_ae_if, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_xcpt_ma_if, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_bp_debug_if, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_bp_xcpt_if, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_debug_fsrc, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_debug_tsrc, // @[issue-unit.scala:44:14] output io_dis_uops_1_ready, // @[issue-unit.scala:44:14] input io_dis_uops_1_valid, // @[issue-unit.scala:44:14] input [31:0] io_dis_uops_1_bits_inst, // @[issue-unit.scala:44:14] input [31:0] io_dis_uops_1_bits_debug_inst, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_rvc, // @[issue-unit.scala:44:14] input [39:0] io_dis_uops_1_bits_debug_pc, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iq_type_0, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iq_type_1, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iq_type_2, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iq_type_3, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_0, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_1, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_2, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_3, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_4, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_5, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_6, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_7, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_8, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_9, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iw_issued, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iw_issued_partial_agen, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iw_issued_partial_dgen, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_iw_p1_speculative_child, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_iw_p2_speculative_child, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_dis_col_sel, // @[issue-unit.scala:44:14] input [15:0] io_dis_uops_1_bits_br_mask, // @[issue-unit.scala:44:14] input [3:0] io_dis_uops_1_bits_br_tag, // @[issue-unit.scala:44:14] input [3:0] io_dis_uops_1_bits_br_type, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_sfb, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_fence, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_fencei, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_sfence, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_amo, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_eret, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_sys_pc2epc, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_rocc, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_mov, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_1_bits_ftq_idx, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_edge_inst, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_1_bits_pc_lob, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_taken, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_imm_rename, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_imm_sel, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_1_bits_pimm, // @[issue-unit.scala:44:14] input [19:0] io_dis_uops_1_bits_imm_packed, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_op1_sel, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_op2_sel, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_ldst, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_wen, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_ren1, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_ren2, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_ren3, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_swap12, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_swap23, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_fromint, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_toint, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_fma, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_div, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_wflags, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_vec, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_1_bits_rob_idx, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_1_bits_ldq_idx, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_1_bits_stq_idx, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_rxq_idx, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_1_bits_pdst, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_1_bits_prs1, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_1_bits_prs2, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_1_bits_prs3, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_1_bits_ppred, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_prs1_busy, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_prs2_busy, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_prs3_busy, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_ppred_busy, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_1_bits_stale_pdst, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_exception, // @[issue-unit.scala:44:14] input [63:0] io_dis_uops_1_bits_exc_cause, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_1_bits_mem_cmd, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_mem_size, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_mem_signed, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_uses_ldq, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_uses_stq, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_unique, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_flush_on_commit, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_csr_cmd, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_ldst_is_rs1, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_1_bits_ldst, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_1_bits_lrs1, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_1_bits_lrs2, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_1_bits_lrs3, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_dst_rtype, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_lrs1_rtype, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_lrs2_rtype, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_frs3_en, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fcn_dw, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_1_bits_fcn_op, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_val, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_fp_rm, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_fp_typ, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_xcpt_pf_if, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_xcpt_ae_if, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_xcpt_ma_if, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_bp_debug_if, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_bp_xcpt_if, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_debug_fsrc, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_debug_tsrc, // @[issue-unit.scala:44:14] output io_dis_uops_2_ready, // @[issue-unit.scala:44:14] input io_dis_uops_2_valid, // @[issue-unit.scala:44:14] input [31:0] io_dis_uops_2_bits_inst, // @[issue-unit.scala:44:14] input [31:0] io_dis_uops_2_bits_debug_inst, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_rvc, // @[issue-unit.scala:44:14] input [39:0] io_dis_uops_2_bits_debug_pc, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_iq_type_0, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_iq_type_1, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_iq_type_2, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_iq_type_3, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fu_code_0, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fu_code_1, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fu_code_2, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fu_code_3, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fu_code_4, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fu_code_5, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fu_code_6, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fu_code_7, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fu_code_8, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fu_code_9, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_iw_issued, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_iw_issued_partial_agen, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_iw_issued_partial_dgen, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_2_bits_iw_p1_speculative_child, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_2_bits_iw_p2_speculative_child, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_2_bits_dis_col_sel, // @[issue-unit.scala:44:14] input [15:0] io_dis_uops_2_bits_br_mask, // @[issue-unit.scala:44:14] input [3:0] io_dis_uops_2_bits_br_tag, // @[issue-unit.scala:44:14] input [3:0] io_dis_uops_2_bits_br_type, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_sfb, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_fence, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_fencei, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_sfence, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_amo, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_eret, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_sys_pc2epc, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_rocc, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_mov, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_2_bits_ftq_idx, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_edge_inst, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_2_bits_pc_lob, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_taken, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_imm_rename, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_2_bits_imm_sel, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_2_bits_pimm, // @[issue-unit.scala:44:14] input [19:0] io_dis_uops_2_bits_imm_packed, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_2_bits_op1_sel, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_2_bits_op2_sel, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_ldst, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_wen, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_ren1, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_ren2, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_ren3, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_swap12, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_swap23, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_2_bits_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_2_bits_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_fromint, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_toint, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_fma, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_div, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_wflags, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_vec, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_2_bits_rob_idx, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_2_bits_ldq_idx, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_2_bits_stq_idx, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_2_bits_rxq_idx, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_2_bits_pdst, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_2_bits_prs1, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_2_bits_prs2, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_2_bits_prs3, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_2_bits_ppred, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_prs1_busy, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_prs2_busy, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_prs3_busy, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_ppred_busy, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_2_bits_stale_pdst, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_exception, // @[issue-unit.scala:44:14] input [63:0] io_dis_uops_2_bits_exc_cause, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_2_bits_mem_cmd, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_2_bits_mem_size, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_mem_signed, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_uses_ldq, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_uses_stq, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_unique, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_flush_on_commit, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_2_bits_csr_cmd, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_ldst_is_rs1, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_2_bits_ldst, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_2_bits_lrs1, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_2_bits_lrs2, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_2_bits_lrs3, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_2_bits_dst_rtype, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_2_bits_lrs1_rtype, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_2_bits_lrs2_rtype, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_frs3_en, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fcn_dw, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_2_bits_fcn_op, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_val, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_2_bits_fp_rm, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_2_bits_fp_typ, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_xcpt_pf_if, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_xcpt_ae_if, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_xcpt_ma_if, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_bp_debug_if, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_bp_xcpt_if, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_2_bits_debug_fsrc, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_2_bits_debug_tsrc, // @[issue-unit.scala:44:14] output io_iss_uops_0_valid, // @[issue-unit.scala:44:14] output [31:0] io_iss_uops_0_bits_inst, // @[issue-unit.scala:44:14] output [31:0] io_iss_uops_0_bits_debug_inst, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_rvc, // @[issue-unit.scala:44:14] output [39:0] io_iss_uops_0_bits_debug_pc, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iq_type_0, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iq_type_1, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iq_type_2, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iq_type_3, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_0, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_1, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_2, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_3, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_4, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_5, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_6, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_7, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_8, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_9, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iw_issued, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_iw_p1_speculative_child, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_iw_p2_speculative_child, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_dis_col_sel, // @[issue-unit.scala:44:14] output [15:0] io_iss_uops_0_bits_br_mask, // @[issue-unit.scala:44:14] output [3:0] io_iss_uops_0_bits_br_tag, // @[issue-unit.scala:44:14] output [3:0] io_iss_uops_0_bits_br_type, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_sfb, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_fence, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_fencei, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_sfence, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_amo, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_eret, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_sys_pc2epc, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_rocc, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_mov, // @[issue-unit.scala:44:14] output [4:0] io_iss_uops_0_bits_ftq_idx, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_edge_inst, // @[issue-unit.scala:44:14] output [5:0] io_iss_uops_0_bits_pc_lob, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_taken, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_imm_rename, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_imm_sel, // @[issue-unit.scala:44:14] output [4:0] io_iss_uops_0_bits_pimm, // @[issue-unit.scala:44:14] output [19:0] io_iss_uops_0_bits_imm_packed, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_op1_sel, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_op2_sel, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_ldst, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_wen, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_ren1, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_ren2, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_ren3, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_swap12, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_swap23, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_fromint, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_toint, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_fma, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_div, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_wflags, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_vec, // @[issue-unit.scala:44:14] output [6:0] io_iss_uops_0_bits_rob_idx, // @[issue-unit.scala:44:14] output [4:0] io_iss_uops_0_bits_ldq_idx, // @[issue-unit.scala:44:14] output [4:0] io_iss_uops_0_bits_stq_idx, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_rxq_idx, // @[issue-unit.scala:44:14] output [6:0] io_iss_uops_0_bits_pdst, // @[issue-unit.scala:44:14] output [6:0] io_iss_uops_0_bits_prs1, // @[issue-unit.scala:44:14] output [6:0] io_iss_uops_0_bits_prs2, // @[issue-unit.scala:44:14] output [6:0] io_iss_uops_0_bits_prs3, // @[issue-unit.scala:44:14] output [4:0] io_iss_uops_0_bits_ppred, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_prs1_busy, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_prs2_busy, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_prs3_busy, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_ppred_busy, // @[issue-unit.scala:44:14] output [6:0] io_iss_uops_0_bits_stale_pdst, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_exception, // @[issue-unit.scala:44:14] output [63:0] io_iss_uops_0_bits_exc_cause, // @[issue-unit.scala:44:14] output [4:0] io_iss_uops_0_bits_mem_cmd, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_mem_size, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_mem_signed, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_uses_ldq, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_uses_stq, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_unique, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_flush_on_commit, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_csr_cmd, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_ldst_is_rs1, // @[issue-unit.scala:44:14] output [5:0] io_iss_uops_0_bits_ldst, // @[issue-unit.scala:44:14] output [5:0] io_iss_uops_0_bits_lrs1, // @[issue-unit.scala:44:14] output [5:0] io_iss_uops_0_bits_lrs2, // @[issue-unit.scala:44:14] output [5:0] io_iss_uops_0_bits_lrs3, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_dst_rtype, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_lrs1_rtype, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_lrs2_rtype, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_frs3_en, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fcn_dw, // @[issue-unit.scala:44:14] output [4:0] io_iss_uops_0_bits_fcn_op, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_val, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_fp_rm, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_fp_typ, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_xcpt_pf_if, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_xcpt_ae_if, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_xcpt_ma_if, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_bp_debug_if, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_bp_xcpt_if, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_debug_fsrc, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_debug_tsrc, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_valid, // @[issue-unit.scala:44:14] input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-unit.scala:44:14] input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-unit.scala:44:14] input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-unit.scala:44:14] input [15:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_taken, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-unit.scala:44:14] input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_exception, // @[issue-unit.scala:44:14] input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_bypassable, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_rebusy, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_valid, // @[issue-unit.scala:44:14] input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-unit.scala:44:14] input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-unit.scala:44:14] input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-unit.scala:44:14] input [15:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_taken, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-unit.scala:44:14] input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_exception, // @[issue-unit.scala:44:14] input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_valid, // @[issue-unit.scala:44:14] input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-unit.scala:44:14] input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-unit.scala:44:14] input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-unit.scala:44:14] input [15:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_taken, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-unit.scala:44:14] input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_exception, // @[issue-unit.scala:44:14] input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_valid, // @[issue-unit.scala:44:14] input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-unit.scala:44:14] input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-unit.scala:44:14] input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-unit.scala:44:14] input [15:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_taken, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-unit.scala:44:14] input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_exception, // @[issue-unit.scala:44:14] input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_valid, // @[issue-unit.scala:44:14] input [31:0] io_wakeup_ports_4_bits_uop_inst, // @[issue-unit.scala:44:14] input [31:0] io_wakeup_ports_4_bits_uop_debug_inst, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_is_rvc, // @[issue-unit.scala:44:14] input [39:0] io_wakeup_ports_4_bits_uop_debug_pc, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_iq_type_0, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_iq_type_1, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_iq_type_2, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_iq_type_3, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fu_code_0, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fu_code_1, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fu_code_2, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fu_code_3, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fu_code_4, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fu_code_5, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fu_code_6, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fu_code_7, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fu_code_8, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fu_code_9, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_iw_issued, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel, // @[issue-unit.scala:44:14] input [15:0] io_wakeup_ports_4_bits_uop_br_mask, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_4_bits_uop_br_tag, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_4_bits_uop_br_type, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_is_sfb, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_is_fence, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_is_fencei, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_is_sfence, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_is_amo, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_is_eret, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_is_sys_pc2epc, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_is_rocc, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_is_mov, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_4_bits_uop_ftq_idx, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_edge_inst, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_4_bits_uop_pc_lob, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_taken, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_imm_rename, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_4_bits_uop_imm_sel, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_4_bits_uop_pimm, // @[issue-unit.scala:44:14] input [19:0] io_wakeup_ports_4_bits_uop_imm_packed, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_4_bits_uop_op1_sel, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_4_bits_uop_op2_sel, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ldst, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_wen, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren1, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren2, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren3, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_swap12, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_swap23, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fromint, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_toint, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fma, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_div, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_wflags, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_vec, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_4_bits_uop_rob_idx, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_4_bits_uop_ldq_idx, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_4_bits_uop_stq_idx, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_4_bits_uop_rxq_idx, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_4_bits_uop_pdst, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_4_bits_uop_prs1, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_4_bits_uop_prs2, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_4_bits_uop_prs3, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_4_bits_uop_ppred, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_prs1_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_prs2_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_prs3_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_ppred_busy, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_4_bits_uop_stale_pdst, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_exception, // @[issue-unit.scala:44:14] input [63:0] io_wakeup_ports_4_bits_uop_exc_cause, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_4_bits_uop_mem_cmd, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_4_bits_uop_mem_size, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_mem_signed, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_uses_ldq, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_uses_stq, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_is_unique, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_flush_on_commit, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_4_bits_uop_csr_cmd, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_ldst_is_rs1, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_4_bits_uop_ldst, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs1, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs2, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs3, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_4_bits_uop_dst_rtype, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_frs3_en, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fcn_dw, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_4_bits_uop_fcn_op, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_fp_val, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_4_bits_uop_fp_rm, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_typ, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_xcpt_pf_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_xcpt_ae_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_xcpt_ma_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_bp_debug_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_4_bits_uop_bp_xcpt_if, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc, // @[issue-unit.scala:44:14] input [2:0] io_child_rebusys, // @[issue-unit.scala:44:14] input io_fu_types_0_4, // @[issue-unit.scala:44:14] input io_fu_types_0_8, // @[issue-unit.scala:44:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-unit.scala:44:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-unit.scala:44:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-unit.scala:44:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_rvc, // @[issue-unit.scala:44:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iq_type_0, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iq_type_1, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iq_type_2, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iq_type_3, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_0, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_1, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_2, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_3, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_4, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_5, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_6, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_7, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_8, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_9, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iw_issued, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-unit.scala:44:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-unit.scala:44:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-unit.scala:44:14] input [3:0] io_brupdate_b2_uop_br_type, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_sfb, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_fence, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_fencei, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_sfence, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_amo, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_eret, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_rocc, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_mov, // @[issue-unit.scala:44:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_edge_inst, // @[issue-unit.scala:44:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_taken, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_imm_rename, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-unit.scala:44:14] input [4:0] io_brupdate_b2_uop_pimm, // @[issue-unit.scala:44:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-unit.scala:44:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-unit.scala:44:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-unit.scala:44:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-unit.scala:44:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-unit.scala:44:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-unit.scala:44:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-unit.scala:44:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-unit.scala:44:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-unit.scala:44:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_exception, // @[issue-unit.scala:44:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-unit.scala:44:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_mem_signed, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_uses_stq, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_unique, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-unit.scala:44:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-unit.scala:44:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-unit.scala:44:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-unit.scala:44:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_frs3_en, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fcn_dw, // @[issue-unit.scala:44:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_val, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-unit.scala:44:14] input io_brupdate_b2_mispredict, // @[issue-unit.scala:44:14] input io_brupdate_b2_taken, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-unit.scala:44:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-unit.scala:44:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-unit.scala:44:14] input io_flush_pipeline, // @[issue-unit.scala:44:14] input io_squash_grant, // @[issue-unit.scala:44:14] input [63:0] io_tsc_reg // @[issue-unit.scala:44:14] ); wire issue_slots_15_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire io_dis_uops_0_valid_0 = io_dis_uops_0_valid; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_dis_uops_0_bits_inst_0 = io_dis_uops_0_bits_inst; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_dis_uops_0_bits_debug_inst_0 = io_dis_uops_0_bits_debug_inst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_rvc_0 = io_dis_uops_0_bits_is_rvc; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_dis_uops_0_bits_debug_pc_0 = io_dis_uops_0_bits_debug_pc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iq_type_0_0 = io_dis_uops_0_bits_iq_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iq_type_1_0 = io_dis_uops_0_bits_iq_type_1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iq_type_2_0 = io_dis_uops_0_bits_iq_type_2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iq_type_3_0 = io_dis_uops_0_bits_iq_type_3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_0_0 = io_dis_uops_0_bits_fu_code_0; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_1_0 = io_dis_uops_0_bits_fu_code_1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_2_0 = io_dis_uops_0_bits_fu_code_2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_3_0 = io_dis_uops_0_bits_fu_code_3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_4_0 = io_dis_uops_0_bits_fu_code_4; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_5_0 = io_dis_uops_0_bits_fu_code_5; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_6_0 = io_dis_uops_0_bits_fu_code_6; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_7_0 = io_dis_uops_0_bits_fu_code_7; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_8_0 = io_dis_uops_0_bits_fu_code_8; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_9_0 = io_dis_uops_0_bits_fu_code_9; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iw_issued_0 = io_dis_uops_0_bits_iw_issued; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iw_issued_partial_agen_0 = io_dis_uops_0_bits_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iw_issued_partial_dgen_0 = io_dis_uops_0_bits_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_iw_p1_speculative_child_0 = io_dis_uops_0_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_iw_p2_speculative_child_0 = io_dis_uops_0_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iw_p1_bypass_hint_0 = io_dis_uops_0_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iw_p2_bypass_hint_0 = io_dis_uops_0_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iw_p3_bypass_hint_0 = io_dis_uops_0_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_dis_col_sel_0 = io_dis_uops_0_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_dis_uops_0_bits_br_mask_0 = io_dis_uops_0_bits_br_mask; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_dis_uops_0_bits_br_tag_0 = io_dis_uops_0_bits_br_tag; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_dis_uops_0_bits_br_type_0 = io_dis_uops_0_bits_br_type; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_sfb_0 = io_dis_uops_0_bits_is_sfb; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_fence_0 = io_dis_uops_0_bits_is_fence; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_fencei_0 = io_dis_uops_0_bits_is_fencei; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_sfence_0 = io_dis_uops_0_bits_is_sfence; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_amo_0 = io_dis_uops_0_bits_is_amo; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_eret_0 = io_dis_uops_0_bits_is_eret; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_sys_pc2epc_0 = io_dis_uops_0_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_rocc_0 = io_dis_uops_0_bits_is_rocc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_mov_0 = io_dis_uops_0_bits_is_mov; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_0_bits_ftq_idx_0 = io_dis_uops_0_bits_ftq_idx; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_edge_inst_0 = io_dis_uops_0_bits_edge_inst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_0_bits_pc_lob_0 = io_dis_uops_0_bits_pc_lob; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_taken_0 = io_dis_uops_0_bits_taken; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_imm_rename_0 = io_dis_uops_0_bits_imm_rename; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_imm_sel_0 = io_dis_uops_0_bits_imm_sel; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_0_bits_pimm_0 = io_dis_uops_0_bits_pimm; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_dis_uops_0_bits_imm_packed_0 = io_dis_uops_0_bits_imm_packed; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_op1_sel_0 = io_dis_uops_0_bits_op1_sel; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_op2_sel_0 = io_dis_uops_0_bits_op2_sel; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_ldst_0 = io_dis_uops_0_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_wen_0 = io_dis_uops_0_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_ren1_0 = io_dis_uops_0_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_ren2_0 = io_dis_uops_0_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_ren3_0 = io_dis_uops_0_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_swap12_0 = io_dis_uops_0_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_swap23_0 = io_dis_uops_0_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_fp_ctrl_typeTagIn_0 = io_dis_uops_0_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_fp_ctrl_typeTagOut_0 = io_dis_uops_0_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_fromint_0 = io_dis_uops_0_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_toint_0 = io_dis_uops_0_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_fastpipe_0 = io_dis_uops_0_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_fma_0 = io_dis_uops_0_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_div_0 = io_dis_uops_0_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_sqrt_0 = io_dis_uops_0_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_wflags_0 = io_dis_uops_0_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_vec_0 = io_dis_uops_0_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_0_bits_rob_idx_0 = io_dis_uops_0_bits_rob_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_0_bits_ldq_idx_0 = io_dis_uops_0_bits_ldq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_0_bits_stq_idx_0 = io_dis_uops_0_bits_stq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_rxq_idx_0 = io_dis_uops_0_bits_rxq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_0_bits_pdst_0 = io_dis_uops_0_bits_pdst; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_0_bits_prs1_0 = io_dis_uops_0_bits_prs1; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_0_bits_prs2_0 = io_dis_uops_0_bits_prs2; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_0_bits_prs3_0 = io_dis_uops_0_bits_prs3; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_0_bits_ppred_0 = io_dis_uops_0_bits_ppred; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_prs1_busy_0 = io_dis_uops_0_bits_prs1_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_prs2_busy_0 = io_dis_uops_0_bits_prs2_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_prs3_busy_0 = io_dis_uops_0_bits_prs3_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_ppred_busy_0 = io_dis_uops_0_bits_ppred_busy; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_0_bits_stale_pdst_0 = io_dis_uops_0_bits_stale_pdst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_exception_0 = io_dis_uops_0_bits_exception; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_dis_uops_0_bits_exc_cause_0 = io_dis_uops_0_bits_exc_cause; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_0_bits_mem_cmd_0 = io_dis_uops_0_bits_mem_cmd; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_mem_size_0 = io_dis_uops_0_bits_mem_size; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_mem_signed_0 = io_dis_uops_0_bits_mem_signed; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_uses_ldq_0 = io_dis_uops_0_bits_uses_ldq; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_uses_stq_0 = io_dis_uops_0_bits_uses_stq; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_unique_0 = io_dis_uops_0_bits_is_unique; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_flush_on_commit_0 = io_dis_uops_0_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_csr_cmd_0 = io_dis_uops_0_bits_csr_cmd; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_ldst_is_rs1_0 = io_dis_uops_0_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_0_bits_ldst_0 = io_dis_uops_0_bits_ldst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_0_bits_lrs1_0 = io_dis_uops_0_bits_lrs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_0_bits_lrs2_0 = io_dis_uops_0_bits_lrs2; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_0_bits_lrs3_0 = io_dis_uops_0_bits_lrs3; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_dst_rtype_0 = io_dis_uops_0_bits_dst_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_lrs1_rtype_0 = io_dis_uops_0_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_lrs2_rtype_0 = io_dis_uops_0_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_frs3_en_0 = io_dis_uops_0_bits_frs3_en; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fcn_dw_0 = io_dis_uops_0_bits_fcn_dw; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_0_bits_fcn_op_0 = io_dis_uops_0_bits_fcn_op; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_val_0 = io_dis_uops_0_bits_fp_val; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_fp_rm_0 = io_dis_uops_0_bits_fp_rm; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_fp_typ_0 = io_dis_uops_0_bits_fp_typ; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_xcpt_pf_if_0 = io_dis_uops_0_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_xcpt_ae_if_0 = io_dis_uops_0_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_xcpt_ma_if_0 = io_dis_uops_0_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_bp_debug_if_0 = io_dis_uops_0_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_bp_xcpt_if_0 = io_dis_uops_0_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_debug_fsrc_0 = io_dis_uops_0_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_debug_tsrc_0 = io_dis_uops_0_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_valid_0 = io_dis_uops_1_valid; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_dis_uops_1_bits_inst_0 = io_dis_uops_1_bits_inst; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_dis_uops_1_bits_debug_inst_0 = io_dis_uops_1_bits_debug_inst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_rvc_0 = io_dis_uops_1_bits_is_rvc; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_dis_uops_1_bits_debug_pc_0 = io_dis_uops_1_bits_debug_pc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iq_type_0_0 = io_dis_uops_1_bits_iq_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iq_type_1_0 = io_dis_uops_1_bits_iq_type_1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iq_type_2_0 = io_dis_uops_1_bits_iq_type_2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iq_type_3_0 = io_dis_uops_1_bits_iq_type_3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_0_0 = io_dis_uops_1_bits_fu_code_0; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_1_0 = io_dis_uops_1_bits_fu_code_1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_2_0 = io_dis_uops_1_bits_fu_code_2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_3_0 = io_dis_uops_1_bits_fu_code_3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_4_0 = io_dis_uops_1_bits_fu_code_4; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_5_0 = io_dis_uops_1_bits_fu_code_5; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_6_0 = io_dis_uops_1_bits_fu_code_6; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_7_0 = io_dis_uops_1_bits_fu_code_7; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_8_0 = io_dis_uops_1_bits_fu_code_8; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_9_0 = io_dis_uops_1_bits_fu_code_9; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iw_issued_0 = io_dis_uops_1_bits_iw_issued; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iw_issued_partial_agen_0 = io_dis_uops_1_bits_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iw_issued_partial_dgen_0 = io_dis_uops_1_bits_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_iw_p1_speculative_child_0 = io_dis_uops_1_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_iw_p2_speculative_child_0 = io_dis_uops_1_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iw_p1_bypass_hint_0 = io_dis_uops_1_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iw_p2_bypass_hint_0 = io_dis_uops_1_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iw_p3_bypass_hint_0 = io_dis_uops_1_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_dis_col_sel_0 = io_dis_uops_1_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_dis_uops_1_bits_br_mask_0 = io_dis_uops_1_bits_br_mask; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_dis_uops_1_bits_br_tag_0 = io_dis_uops_1_bits_br_tag; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_dis_uops_1_bits_br_type_0 = io_dis_uops_1_bits_br_type; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_sfb_0 = io_dis_uops_1_bits_is_sfb; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_fence_0 = io_dis_uops_1_bits_is_fence; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_fencei_0 = io_dis_uops_1_bits_is_fencei; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_sfence_0 = io_dis_uops_1_bits_is_sfence; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_amo_0 = io_dis_uops_1_bits_is_amo; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_eret_0 = io_dis_uops_1_bits_is_eret; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_sys_pc2epc_0 = io_dis_uops_1_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_rocc_0 = io_dis_uops_1_bits_is_rocc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_mov_0 = io_dis_uops_1_bits_is_mov; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_1_bits_ftq_idx_0 = io_dis_uops_1_bits_ftq_idx; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_edge_inst_0 = io_dis_uops_1_bits_edge_inst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_1_bits_pc_lob_0 = io_dis_uops_1_bits_pc_lob; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_taken_0 = io_dis_uops_1_bits_taken; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_imm_rename_0 = io_dis_uops_1_bits_imm_rename; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_imm_sel_0 = io_dis_uops_1_bits_imm_sel; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_1_bits_pimm_0 = io_dis_uops_1_bits_pimm; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_dis_uops_1_bits_imm_packed_0 = io_dis_uops_1_bits_imm_packed; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_op1_sel_0 = io_dis_uops_1_bits_op1_sel; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_op2_sel_0 = io_dis_uops_1_bits_op2_sel; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_ldst_0 = io_dis_uops_1_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_wen_0 = io_dis_uops_1_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_ren1_0 = io_dis_uops_1_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_ren2_0 = io_dis_uops_1_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_ren3_0 = io_dis_uops_1_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_swap12_0 = io_dis_uops_1_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_swap23_0 = io_dis_uops_1_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_fp_ctrl_typeTagIn_0 = io_dis_uops_1_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_fp_ctrl_typeTagOut_0 = io_dis_uops_1_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_fromint_0 = io_dis_uops_1_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_toint_0 = io_dis_uops_1_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_fastpipe_0 = io_dis_uops_1_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_fma_0 = io_dis_uops_1_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_div_0 = io_dis_uops_1_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_sqrt_0 = io_dis_uops_1_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_wflags_0 = io_dis_uops_1_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_vec_0 = io_dis_uops_1_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_1_bits_rob_idx_0 = io_dis_uops_1_bits_rob_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_1_bits_ldq_idx_0 = io_dis_uops_1_bits_ldq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_1_bits_stq_idx_0 = io_dis_uops_1_bits_stq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_rxq_idx_0 = io_dis_uops_1_bits_rxq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_1_bits_pdst_0 = io_dis_uops_1_bits_pdst; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_1_bits_prs1_0 = io_dis_uops_1_bits_prs1; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_1_bits_prs2_0 = io_dis_uops_1_bits_prs2; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_1_bits_prs3_0 = io_dis_uops_1_bits_prs3; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_1_bits_ppred_0 = io_dis_uops_1_bits_ppred; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_prs1_busy_0 = io_dis_uops_1_bits_prs1_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_prs2_busy_0 = io_dis_uops_1_bits_prs2_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_prs3_busy_0 = io_dis_uops_1_bits_prs3_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_ppred_busy_0 = io_dis_uops_1_bits_ppred_busy; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_1_bits_stale_pdst_0 = io_dis_uops_1_bits_stale_pdst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_exception_0 = io_dis_uops_1_bits_exception; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_dis_uops_1_bits_exc_cause_0 = io_dis_uops_1_bits_exc_cause; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_1_bits_mem_cmd_0 = io_dis_uops_1_bits_mem_cmd; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_mem_size_0 = io_dis_uops_1_bits_mem_size; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_mem_signed_0 = io_dis_uops_1_bits_mem_signed; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_uses_ldq_0 = io_dis_uops_1_bits_uses_ldq; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_uses_stq_0 = io_dis_uops_1_bits_uses_stq; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_unique_0 = io_dis_uops_1_bits_is_unique; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_flush_on_commit_0 = io_dis_uops_1_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_csr_cmd_0 = io_dis_uops_1_bits_csr_cmd; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_ldst_is_rs1_0 = io_dis_uops_1_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_1_bits_ldst_0 = io_dis_uops_1_bits_ldst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_1_bits_lrs1_0 = io_dis_uops_1_bits_lrs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_1_bits_lrs2_0 = io_dis_uops_1_bits_lrs2; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_1_bits_lrs3_0 = io_dis_uops_1_bits_lrs3; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_dst_rtype_0 = io_dis_uops_1_bits_dst_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_lrs1_rtype_0 = io_dis_uops_1_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_lrs2_rtype_0 = io_dis_uops_1_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_frs3_en_0 = io_dis_uops_1_bits_frs3_en; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fcn_dw_0 = io_dis_uops_1_bits_fcn_dw; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_1_bits_fcn_op_0 = io_dis_uops_1_bits_fcn_op; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_val_0 = io_dis_uops_1_bits_fp_val; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_fp_rm_0 = io_dis_uops_1_bits_fp_rm; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_fp_typ_0 = io_dis_uops_1_bits_fp_typ; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_xcpt_pf_if_0 = io_dis_uops_1_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_xcpt_ae_if_0 = io_dis_uops_1_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_xcpt_ma_if_0 = io_dis_uops_1_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_bp_debug_if_0 = io_dis_uops_1_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_bp_xcpt_if_0 = io_dis_uops_1_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_debug_fsrc_0 = io_dis_uops_1_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_debug_tsrc_0 = io_dis_uops_1_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_valid_0 = io_dis_uops_2_valid; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_dis_uops_2_bits_inst_0 = io_dis_uops_2_bits_inst; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_dis_uops_2_bits_debug_inst_0 = io_dis_uops_2_bits_debug_inst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_rvc_0 = io_dis_uops_2_bits_is_rvc; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_dis_uops_2_bits_debug_pc_0 = io_dis_uops_2_bits_debug_pc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_iq_type_0_0 = io_dis_uops_2_bits_iq_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_iq_type_1_0 = io_dis_uops_2_bits_iq_type_1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_iq_type_2_0 = io_dis_uops_2_bits_iq_type_2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_iq_type_3_0 = io_dis_uops_2_bits_iq_type_3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fu_code_0_0 = io_dis_uops_2_bits_fu_code_0; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fu_code_1_0 = io_dis_uops_2_bits_fu_code_1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fu_code_2_0 = io_dis_uops_2_bits_fu_code_2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fu_code_3_0 = io_dis_uops_2_bits_fu_code_3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fu_code_4_0 = io_dis_uops_2_bits_fu_code_4; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fu_code_5_0 = io_dis_uops_2_bits_fu_code_5; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fu_code_6_0 = io_dis_uops_2_bits_fu_code_6; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fu_code_7_0 = io_dis_uops_2_bits_fu_code_7; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fu_code_8_0 = io_dis_uops_2_bits_fu_code_8; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fu_code_9_0 = io_dis_uops_2_bits_fu_code_9; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_iw_issued_0 = io_dis_uops_2_bits_iw_issued; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_iw_issued_partial_agen_0 = io_dis_uops_2_bits_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_iw_issued_partial_dgen_0 = io_dis_uops_2_bits_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_2_bits_iw_p1_speculative_child_0 = io_dis_uops_2_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_2_bits_iw_p2_speculative_child_0 = io_dis_uops_2_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_iw_p1_bypass_hint_0 = io_dis_uops_2_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_iw_p2_bypass_hint_0 = io_dis_uops_2_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_iw_p3_bypass_hint_0 = io_dis_uops_2_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_2_bits_dis_col_sel_0 = io_dis_uops_2_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_dis_uops_2_bits_br_mask_0 = io_dis_uops_2_bits_br_mask; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_dis_uops_2_bits_br_tag_0 = io_dis_uops_2_bits_br_tag; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_dis_uops_2_bits_br_type_0 = io_dis_uops_2_bits_br_type; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_sfb_0 = io_dis_uops_2_bits_is_sfb; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_fence_0 = io_dis_uops_2_bits_is_fence; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_fencei_0 = io_dis_uops_2_bits_is_fencei; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_sfence_0 = io_dis_uops_2_bits_is_sfence; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_amo_0 = io_dis_uops_2_bits_is_amo; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_eret_0 = io_dis_uops_2_bits_is_eret; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_sys_pc2epc_0 = io_dis_uops_2_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_rocc_0 = io_dis_uops_2_bits_is_rocc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_mov_0 = io_dis_uops_2_bits_is_mov; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_2_bits_ftq_idx_0 = io_dis_uops_2_bits_ftq_idx; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_edge_inst_0 = io_dis_uops_2_bits_edge_inst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_2_bits_pc_lob_0 = io_dis_uops_2_bits_pc_lob; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_taken_0 = io_dis_uops_2_bits_taken; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_imm_rename_0 = io_dis_uops_2_bits_imm_rename; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_2_bits_imm_sel_0 = io_dis_uops_2_bits_imm_sel; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_2_bits_pimm_0 = io_dis_uops_2_bits_pimm; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_dis_uops_2_bits_imm_packed_0 = io_dis_uops_2_bits_imm_packed; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_2_bits_op1_sel_0 = io_dis_uops_2_bits_op1_sel; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_2_bits_op2_sel_0 = io_dis_uops_2_bits_op2_sel; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_ldst_0 = io_dis_uops_2_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_wen_0 = io_dis_uops_2_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_ren1_0 = io_dis_uops_2_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_ren2_0 = io_dis_uops_2_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_ren3_0 = io_dis_uops_2_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_swap12_0 = io_dis_uops_2_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_swap23_0 = io_dis_uops_2_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_2_bits_fp_ctrl_typeTagIn_0 = io_dis_uops_2_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_2_bits_fp_ctrl_typeTagOut_0 = io_dis_uops_2_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_fromint_0 = io_dis_uops_2_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_toint_0 = io_dis_uops_2_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_fastpipe_0 = io_dis_uops_2_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_fma_0 = io_dis_uops_2_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_div_0 = io_dis_uops_2_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_sqrt_0 = io_dis_uops_2_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_wflags_0 = io_dis_uops_2_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_vec_0 = io_dis_uops_2_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_2_bits_rob_idx_0 = io_dis_uops_2_bits_rob_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_2_bits_ldq_idx_0 = io_dis_uops_2_bits_ldq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_2_bits_stq_idx_0 = io_dis_uops_2_bits_stq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_2_bits_rxq_idx_0 = io_dis_uops_2_bits_rxq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_2_bits_pdst_0 = io_dis_uops_2_bits_pdst; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_2_bits_prs1_0 = io_dis_uops_2_bits_prs1; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_2_bits_prs2_0 = io_dis_uops_2_bits_prs2; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_2_bits_prs3_0 = io_dis_uops_2_bits_prs3; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_2_bits_ppred_0 = io_dis_uops_2_bits_ppred; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_prs1_busy_0 = io_dis_uops_2_bits_prs1_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_prs2_busy_0 = io_dis_uops_2_bits_prs2_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_prs3_busy_0 = io_dis_uops_2_bits_prs3_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_ppred_busy_0 = io_dis_uops_2_bits_ppred_busy; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_2_bits_stale_pdst_0 = io_dis_uops_2_bits_stale_pdst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_exception_0 = io_dis_uops_2_bits_exception; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_dis_uops_2_bits_exc_cause_0 = io_dis_uops_2_bits_exc_cause; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_2_bits_mem_cmd_0 = io_dis_uops_2_bits_mem_cmd; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_2_bits_mem_size_0 = io_dis_uops_2_bits_mem_size; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_mem_signed_0 = io_dis_uops_2_bits_mem_signed; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_uses_ldq_0 = io_dis_uops_2_bits_uses_ldq; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_uses_stq_0 = io_dis_uops_2_bits_uses_stq; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_unique_0 = io_dis_uops_2_bits_is_unique; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_flush_on_commit_0 = io_dis_uops_2_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_2_bits_csr_cmd_0 = io_dis_uops_2_bits_csr_cmd; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_ldst_is_rs1_0 = io_dis_uops_2_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_2_bits_ldst_0 = io_dis_uops_2_bits_ldst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_2_bits_lrs1_0 = io_dis_uops_2_bits_lrs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_2_bits_lrs2_0 = io_dis_uops_2_bits_lrs2; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_2_bits_lrs3_0 = io_dis_uops_2_bits_lrs3; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_2_bits_dst_rtype_0 = io_dis_uops_2_bits_dst_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_2_bits_lrs1_rtype_0 = io_dis_uops_2_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_2_bits_lrs2_rtype_0 = io_dis_uops_2_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_frs3_en_0 = io_dis_uops_2_bits_frs3_en; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fcn_dw_0 = io_dis_uops_2_bits_fcn_dw; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_2_bits_fcn_op_0 = io_dis_uops_2_bits_fcn_op; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_val_0 = io_dis_uops_2_bits_fp_val; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_2_bits_fp_rm_0 = io_dis_uops_2_bits_fp_rm; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_2_bits_fp_typ_0 = io_dis_uops_2_bits_fp_typ; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_xcpt_pf_if_0 = io_dis_uops_2_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_xcpt_ae_if_0 = io_dis_uops_2_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_xcpt_ma_if_0 = io_dis_uops_2_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_bp_debug_if_0 = io_dis_uops_2_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_bp_xcpt_if_0 = io_dis_uops_2_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_2_bits_debug_fsrc_0 = io_dis_uops_2_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_2_bits_debug_tsrc_0 = io_dis_uops_2_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_wakeup_ports_4_bits_uop_inst_0 = io_wakeup_ports_4_bits_uop_inst; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_wakeup_ports_4_bits_uop_debug_inst_0 = io_wakeup_ports_4_bits_uop_debug_inst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_is_rvc_0 = io_wakeup_ports_4_bits_uop_is_rvc; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_wakeup_ports_4_bits_uop_debug_pc_0 = io_wakeup_ports_4_bits_uop_debug_pc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_iq_type_0_0 = io_wakeup_ports_4_bits_uop_iq_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_iq_type_1_0 = io_wakeup_ports_4_bits_uop_iq_type_1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_iq_type_2_0 = io_wakeup_ports_4_bits_uop_iq_type_2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_iq_type_3_0 = io_wakeup_ports_4_bits_uop_iq_type_3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fu_code_0_0 = io_wakeup_ports_4_bits_uop_fu_code_0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fu_code_1_0 = io_wakeup_ports_4_bits_uop_fu_code_1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fu_code_2_0 = io_wakeup_ports_4_bits_uop_fu_code_2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fu_code_3_0 = io_wakeup_ports_4_bits_uop_fu_code_3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fu_code_4_0 = io_wakeup_ports_4_bits_uop_fu_code_4; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fu_code_5_0 = io_wakeup_ports_4_bits_uop_fu_code_5; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fu_code_6_0 = io_wakeup_ports_4_bits_uop_fu_code_6; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fu_code_7_0 = io_wakeup_ports_4_bits_uop_fu_code_7; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fu_code_8_0 = io_wakeup_ports_4_bits_uop_fu_code_8; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fu_code_9_0 = io_wakeup_ports_4_bits_uop_fu_code_9; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_iw_issued_0 = io_wakeup_ports_4_bits_uop_iw_issued; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel_0 = io_wakeup_ports_4_bits_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_wakeup_ports_4_bits_uop_br_mask_0 = io_wakeup_ports_4_bits_uop_br_mask; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_4_bits_uop_br_tag_0 = io_wakeup_ports_4_bits_uop_br_tag; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_4_bits_uop_br_type_0 = io_wakeup_ports_4_bits_uop_br_type; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_is_sfb_0 = io_wakeup_ports_4_bits_uop_is_sfb; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_is_fence_0 = io_wakeup_ports_4_bits_uop_is_fence; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_is_fencei_0 = io_wakeup_ports_4_bits_uop_is_fencei; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_is_sfence_0 = io_wakeup_ports_4_bits_uop_is_sfence; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_is_amo_0 = io_wakeup_ports_4_bits_uop_is_amo; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_is_eret_0 = io_wakeup_ports_4_bits_uop_is_eret; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_4_bits_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_is_rocc_0 = io_wakeup_ports_4_bits_uop_is_rocc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_is_mov_0 = io_wakeup_ports_4_bits_uop_is_mov; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_4_bits_uop_ftq_idx_0 = io_wakeup_ports_4_bits_uop_ftq_idx; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_edge_inst_0 = io_wakeup_ports_4_bits_uop_edge_inst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_4_bits_uop_pc_lob_0 = io_wakeup_ports_4_bits_uop_pc_lob; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_taken_0 = io_wakeup_ports_4_bits_uop_taken; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_imm_rename_0 = io_wakeup_ports_4_bits_uop_imm_rename; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_4_bits_uop_imm_sel_0 = io_wakeup_ports_4_bits_uop_imm_sel; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_4_bits_uop_pimm_0 = io_wakeup_ports_4_bits_uop_pimm; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_wakeup_ports_4_bits_uop_imm_packed_0 = io_wakeup_ports_4_bits_uop_imm_packed; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_4_bits_uop_op1_sel_0 = io_wakeup_ports_4_bits_uop_op1_sel; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_4_bits_uop_op2_sel_0 = io_wakeup_ports_4_bits_uop_op2_sel; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_4_bits_uop_rob_idx_0 = io_wakeup_ports_4_bits_uop_rob_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_4_bits_uop_ldq_idx_0 = io_wakeup_ports_4_bits_uop_ldq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_4_bits_uop_stq_idx_0 = io_wakeup_ports_4_bits_uop_stq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_4_bits_uop_rxq_idx_0 = io_wakeup_ports_4_bits_uop_rxq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_4_bits_uop_pdst_0 = io_wakeup_ports_4_bits_uop_pdst; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs1_0 = io_wakeup_ports_4_bits_uop_prs1; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs2_0 = io_wakeup_ports_4_bits_uop_prs2; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs3_0 = io_wakeup_ports_4_bits_uop_prs3; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_4_bits_uop_ppred_0 = io_wakeup_ports_4_bits_uop_ppred; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_prs1_busy_0 = io_wakeup_ports_4_bits_uop_prs1_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_prs2_busy_0 = io_wakeup_ports_4_bits_uop_prs2_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_prs3_busy_0 = io_wakeup_ports_4_bits_uop_prs3_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_ppred_busy_0 = io_wakeup_ports_4_bits_uop_ppred_busy; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_4_bits_uop_stale_pdst_0 = io_wakeup_ports_4_bits_uop_stale_pdst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_exception_0 = io_wakeup_ports_4_bits_uop_exception; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_wakeup_ports_4_bits_uop_exc_cause_0 = io_wakeup_ports_4_bits_uop_exc_cause; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_4_bits_uop_mem_cmd_0 = io_wakeup_ports_4_bits_uop_mem_cmd; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_4_bits_uop_mem_size_0 = io_wakeup_ports_4_bits_uop_mem_size; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_mem_signed_0 = io_wakeup_ports_4_bits_uop_mem_signed; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_uses_ldq_0 = io_wakeup_ports_4_bits_uop_uses_ldq; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_uses_stq_0 = io_wakeup_ports_4_bits_uop_uses_stq; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_is_unique_0 = io_wakeup_ports_4_bits_uop_is_unique; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_flush_on_commit_0 = io_wakeup_ports_4_bits_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_4_bits_uop_csr_cmd_0 = io_wakeup_ports_4_bits_uop_csr_cmd; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_4_bits_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_4_bits_uop_ldst_0 = io_wakeup_ports_4_bits_uop_ldst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs1_0 = io_wakeup_ports_4_bits_uop_lrs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs2_0 = io_wakeup_ports_4_bits_uop_lrs2; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs3_0 = io_wakeup_ports_4_bits_uop_lrs3; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_4_bits_uop_dst_rtype_0 = io_wakeup_ports_4_bits_uop_dst_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype_0 = io_wakeup_ports_4_bits_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype_0 = io_wakeup_ports_4_bits_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_frs3_en_0 = io_wakeup_ports_4_bits_uop_frs3_en; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fcn_dw_0 = io_wakeup_ports_4_bits_uop_fcn_dw; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_4_bits_uop_fcn_op_0 = io_wakeup_ports_4_bits_uop_fcn_op; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_fp_val_0 = io_wakeup_ports_4_bits_uop_fp_val; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_4_bits_uop_fp_rm_0 = io_wakeup_ports_4_bits_uop_fp_rm; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_typ_0 = io_wakeup_ports_4_bits_uop_fp_typ; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_4_bits_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_bp_debug_if_0 = io_wakeup_ports_4_bits_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_4_bits_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc_0 = io_wakeup_ports_4_bits_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc_0 = io_wakeup_ports_4_bits_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_4_0 = io_fu_types_0_4; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_8_0 = io_fu_types_0_8; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-unit-age-ordered.scala:22:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-unit-age-ordered.scala:22:7] wire io_flush_pipeline_0 = io_flush_pipeline; // @[issue-unit-age-ordered.scala:22:7] wire io_squash_grant_0 = io_squash_grant; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_tsc_reg_0 = io_tsc_reg; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_0 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_1 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_2 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_6 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_7 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_9 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire prs1_rebusys_1 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs1_rebusys_2 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs1_rebusys_3 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs1_rebusys_4 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs2_rebusys_1 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire prs2_rebusys_2 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire prs2_rebusys_3 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire prs2_rebusys_4 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire prs1_rebusys_1_1 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs1_rebusys_2_1 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs1_rebusys_3_1 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs1_rebusys_4_1 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs2_rebusys_1_1 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire prs2_rebusys_2_1 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire prs2_rebusys_3_1 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire prs2_rebusys_4_1 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire prs1_rebusys_1_2 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs1_rebusys_2_2 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs1_rebusys_3_2 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs1_rebusys_4_2 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs2_rebusys_1_2 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire prs2_rebusys_2_2 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire prs2_rebusys_3_2 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire prs2_rebusys_4_2 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire issue_slots_0_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_clear = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_iw_issued = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_ppred_busy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire _issue_slots_0_clear_T = 1'h0; // @[issue-unit-age-ordered.scala:199:49] wire iss_uops_0_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:241:22] wire _fu_code_match_T = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_1 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_2 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_6 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_7 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_9 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_10 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_11 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_18 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_19 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_20 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_24 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_25 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_27 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_28 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_29 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_36 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_37 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_38 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_42 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_43 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_45 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_46 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_47 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_54 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_55 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_56 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_60 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_61 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_63 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_64 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_65 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_72 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_73 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_74 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_78 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_79 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_81 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_82 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_83 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_90 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_91 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_92 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_96 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_97 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_99 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_100 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_101 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_108 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_109 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_110 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_114 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_115 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_117 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_118 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_119 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_126 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_127 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_128 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_132 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_133 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_135 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_136 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_137 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_144 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_145 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_146 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_150 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_151 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_153 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_154 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_155 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_162 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_163 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_164 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_168 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_169 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_171 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_172 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_173 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_180 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_181 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_182 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_186 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_187 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_189 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_190 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_191 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_198 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_199 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_200 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_204 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_205 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_207 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_208 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_209 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_216 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_217 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_218 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_222 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_223 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_225 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_226 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_227 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_234 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_235 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_236 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_240 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_241 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_243 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_244 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_245 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_252 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_253 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_254 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_258 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_259 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_261 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_262 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_263 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_270 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_271 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_272 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_276 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_277 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_279 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_280 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_281 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire [2:0] io_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] issue_slots_0_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] shamts_oh_0 = 3'h0; // @[issue-unit-age-ordered.scala:158:23] wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_3 = 1'h1; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_5 = 1'h1; // @[issue-unit-age-ordered.scala:22:7] wire issue_slots_0_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] io_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] issue_slots_0_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] io_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] issue_slots_0_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] io_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] issue_slots_0_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] issue_slots_0_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] iss_uops_0_bits_inst; // @[issue-unit-age-ordered.scala:241:22] wire [31:0] iss_uops_0_bits_debug_inst; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_rvc; // @[issue-unit-age-ordered.scala:241:22] wire [39:0] iss_uops_0_bits_debug_pc; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iq_type_0; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iq_type_1; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iq_type_2; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iq_type_3; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_0; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_1; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_2; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_3; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_4; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_5; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_6; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_7; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_8; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_9; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iw_issued; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:241:22] wire [15:0] iss_uops_0_bits_br_mask; // @[issue-unit-age-ordered.scala:241:22] wire [3:0] iss_uops_0_bits_br_tag; // @[issue-unit-age-ordered.scala:241:22] wire [3:0] iss_uops_0_bits_br_type; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_sfb; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_fence; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_fencei; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_sfence; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_amo; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_eret; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_rocc; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_mov; // @[issue-unit-age-ordered.scala:241:22] wire [4:0] iss_uops_0_bits_ftq_idx; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_edge_inst; // @[issue-unit-age-ordered.scala:241:22] wire [5:0] iss_uops_0_bits_pc_lob; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_taken; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_imm_rename; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_imm_sel; // @[issue-unit-age-ordered.scala:241:22] wire [4:0] iss_uops_0_bits_pimm; // @[issue-unit-age-ordered.scala:241:22] wire [19:0] iss_uops_0_bits_imm_packed; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_op1_sel; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_op2_sel; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:241:22] wire [6:0] iss_uops_0_bits_rob_idx; // @[issue-unit-age-ordered.scala:241:22] wire [4:0] iss_uops_0_bits_ldq_idx; // @[issue-unit-age-ordered.scala:241:22] wire [4:0] iss_uops_0_bits_stq_idx; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_rxq_idx; // @[issue-unit-age-ordered.scala:241:22] wire [6:0] iss_uops_0_bits_pdst; // @[issue-unit-age-ordered.scala:241:22] wire [6:0] iss_uops_0_bits_prs1; // @[issue-unit-age-ordered.scala:241:22] wire [6:0] iss_uops_0_bits_prs2; // @[issue-unit-age-ordered.scala:241:22] wire [6:0] iss_uops_0_bits_prs3; // @[issue-unit-age-ordered.scala:241:22] wire [4:0] iss_uops_0_bits_ppred; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_prs1_busy; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_prs2_busy; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_prs3_busy; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_ppred_busy; // @[issue-unit-age-ordered.scala:241:22] wire [6:0] iss_uops_0_bits_stale_pdst; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_exception; // @[issue-unit-age-ordered.scala:241:22] wire [63:0] iss_uops_0_bits_exc_cause; // @[issue-unit-age-ordered.scala:241:22] wire [4:0] iss_uops_0_bits_mem_cmd; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_mem_size; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_mem_signed; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_uses_ldq; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_uses_stq; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_unique; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_csr_cmd; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:241:22] wire [5:0] iss_uops_0_bits_ldst; // @[issue-unit-age-ordered.scala:241:22] wire [5:0] iss_uops_0_bits_lrs1; // @[issue-unit-age-ordered.scala:241:22] wire [5:0] iss_uops_0_bits_lrs2; // @[issue-unit-age-ordered.scala:241:22] wire [5:0] iss_uops_0_bits_lrs3; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_dst_rtype; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_frs3_en; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fcn_dw; // @[issue-unit-age-ordered.scala:241:22] wire [4:0] iss_uops_0_bits_fcn_op; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_val; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_fp_rm; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_fp_typ; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:241:22] wire issue_slots_0_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_12_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_13_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_14_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_15_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_12_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_13_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_14_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_15_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_0_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_1_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_2_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_3_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_4_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_5_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_6_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_7_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_8_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_9_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_10_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_11_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_12_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_13_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_14_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_15_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_0_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_1_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_2_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_3_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_4_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_5_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_6_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_7_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_8_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_9_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_10_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_11_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_12_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_13_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_14_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_15_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_12_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_13_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_14_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_15_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_12_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_13_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_14_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_15_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_0_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_1_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_2_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_3_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_4_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_5_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_6_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_7_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_8_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_9_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_10_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_11_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_12_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_13_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_14_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_15_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_0_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_1_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_2_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_3_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_4_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_5_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_6_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_7_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_8_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_9_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_10_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_11_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_12_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_13_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_14_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_15_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_bypassable = io_wakeup_ports_0_bits_bypassable_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_0_bits_speculative_mask = io_wakeup_ports_0_bits_speculative_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_rebusy = io_wakeup_ports_0_bits_rebusy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_12_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_13_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_14_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_15_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_12_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_13_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_14_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_15_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_0_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_1_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_2_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_3_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_4_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_5_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_6_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_7_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_8_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_9_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_10_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_11_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_12_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_13_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_14_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_15_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_0_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_1_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_2_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_3_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_4_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_5_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_6_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_7_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_8_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_9_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_10_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_11_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_12_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_13_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_14_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_15_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_12_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_13_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_14_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_15_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_12_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_13_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_14_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_15_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_0_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_1_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_2_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_3_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_4_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_5_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_6_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_7_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_8_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_9_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_10_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_11_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_12_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_13_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_14_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_15_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_0_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_1_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_2_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_3_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_4_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_5_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_6_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_7_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_8_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_9_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_10_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_11_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_12_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_13_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_14_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_15_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_12_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_13_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_14_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_15_wakeup_ports_2_bits_uop_inst = io_wakeup_ports_2_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_12_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_13_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_14_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_15_wakeup_ports_2_bits_uop_debug_inst = io_wakeup_ports_2_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_is_rvc = io_wakeup_ports_2_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_0_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_1_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_2_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_3_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_4_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_5_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_6_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_7_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_8_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_9_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_10_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_11_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_12_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_13_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_14_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_15_wakeup_ports_2_bits_uop_debug_pc = io_wakeup_ports_2_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_iq_type_0 = io_wakeup_ports_2_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_iq_type_1 = io_wakeup_ports_2_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_iq_type_2 = io_wakeup_ports_2_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_iq_type_3 = io_wakeup_ports_2_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fu_code_0 = io_wakeup_ports_2_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fu_code_1 = io_wakeup_ports_2_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fu_code_2 = io_wakeup_ports_2_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fu_code_3 = io_wakeup_ports_2_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fu_code_4 = io_wakeup_ports_2_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fu_code_5 = io_wakeup_ports_2_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fu_code_6 = io_wakeup_ports_2_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fu_code_7 = io_wakeup_ports_2_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fu_code_8 = io_wakeup_ports_2_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fu_code_9 = io_wakeup_ports_2_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_iw_issued = io_wakeup_ports_2_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_2_bits_uop_iw_p1_speculative_child = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_2_bits_uop_iw_p2_speculative_child = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_2_bits_uop_dis_col_sel = io_wakeup_ports_2_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_0_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_1_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_2_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_3_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_4_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_5_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_6_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_7_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_8_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_9_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_10_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_11_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_12_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_13_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_14_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_15_wakeup_ports_2_bits_uop_br_mask = io_wakeup_ports_2_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_12_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_13_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_14_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_15_wakeup_ports_2_bits_uop_br_tag = io_wakeup_ports_2_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_12_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_13_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_14_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_15_wakeup_ports_2_bits_uop_br_type = io_wakeup_ports_2_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_is_sfb = io_wakeup_ports_2_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_is_fence = io_wakeup_ports_2_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_is_fencei = io_wakeup_ports_2_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_is_sfence = io_wakeup_ports_2_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_is_amo = io_wakeup_ports_2_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_is_eret = io_wakeup_ports_2_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_is_sys_pc2epc = io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_is_rocc = io_wakeup_ports_2_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_is_mov = io_wakeup_ports_2_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_2_bits_uop_ftq_idx = io_wakeup_ports_2_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_edge_inst = io_wakeup_ports_2_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_2_bits_uop_pc_lob = io_wakeup_ports_2_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_taken = io_wakeup_ports_2_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_imm_rename = io_wakeup_ports_2_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_2_bits_uop_imm_sel = io_wakeup_ports_2_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_2_bits_uop_pimm = io_wakeup_ports_2_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_0_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_1_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_2_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_3_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_4_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_5_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_6_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_7_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_8_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_9_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_10_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_11_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_12_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_13_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_14_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_15_wakeup_ports_2_bits_uop_imm_packed = io_wakeup_ports_2_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_2_bits_uop_op1_sel = io_wakeup_ports_2_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_2_bits_uop_op2_sel = io_wakeup_ports_2_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_ldst = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_wen = io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_fromint = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_toint = io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_fma = io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_div = io_wakeup_ports_2_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_wflags = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fp_ctrl_vec = io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_2_bits_uop_rob_idx = io_wakeup_ports_2_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_2_bits_uop_ldq_idx = io_wakeup_ports_2_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_2_bits_uop_stq_idx = io_wakeup_ports_2_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_2_bits_uop_rxq_idx = io_wakeup_ports_2_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_2_bits_uop_pdst = io_wakeup_ports_2_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_2_bits_uop_prs1 = io_wakeup_ports_2_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_2_bits_uop_prs2 = io_wakeup_ports_2_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_2_bits_uop_prs3 = io_wakeup_ports_2_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_2_bits_uop_ppred = io_wakeup_ports_2_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_prs1_busy = io_wakeup_ports_2_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_prs2_busy = io_wakeup_ports_2_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_prs3_busy = io_wakeup_ports_2_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_ppred_busy = io_wakeup_ports_2_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_2_bits_uop_stale_pdst = io_wakeup_ports_2_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_exception = io_wakeup_ports_2_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_0_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_1_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_2_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_3_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_4_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_5_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_6_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_7_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_8_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_9_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_10_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_11_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_12_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_13_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_14_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_15_wakeup_ports_2_bits_uop_exc_cause = io_wakeup_ports_2_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_2_bits_uop_mem_cmd = io_wakeup_ports_2_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_2_bits_uop_mem_size = io_wakeup_ports_2_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_mem_signed = io_wakeup_ports_2_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_uses_ldq = io_wakeup_ports_2_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_uses_stq = io_wakeup_ports_2_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_is_unique = io_wakeup_ports_2_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_flush_on_commit = io_wakeup_ports_2_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_2_bits_uop_csr_cmd = io_wakeup_ports_2_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_ldst_is_rs1 = io_wakeup_ports_2_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_2_bits_uop_ldst = io_wakeup_ports_2_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_2_bits_uop_lrs1 = io_wakeup_ports_2_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_2_bits_uop_lrs2 = io_wakeup_ports_2_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_2_bits_uop_lrs3 = io_wakeup_ports_2_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_2_bits_uop_dst_rtype = io_wakeup_ports_2_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_2_bits_uop_lrs1_rtype = io_wakeup_ports_2_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_2_bits_uop_lrs2_rtype = io_wakeup_ports_2_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_frs3_en = io_wakeup_ports_2_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fcn_dw = io_wakeup_ports_2_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_2_bits_uop_fcn_op = io_wakeup_ports_2_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_fp_val = io_wakeup_ports_2_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_2_bits_uop_fp_rm = io_wakeup_ports_2_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_2_bits_uop_fp_typ = io_wakeup_ports_2_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_xcpt_pf_if = io_wakeup_ports_2_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_xcpt_ae_if = io_wakeup_ports_2_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_xcpt_ma_if = io_wakeup_ports_2_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_bp_debug_if = io_wakeup_ports_2_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_2_bits_uop_bp_xcpt_if = io_wakeup_ports_2_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_2_bits_uop_debug_fsrc = io_wakeup_ports_2_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_2_bits_uop_debug_tsrc = io_wakeup_ports_2_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_12_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_13_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_14_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_15_wakeup_ports_3_bits_uop_inst = io_wakeup_ports_3_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_12_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_13_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_14_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_15_wakeup_ports_3_bits_uop_debug_inst = io_wakeup_ports_3_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_is_rvc = io_wakeup_ports_3_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_0_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_1_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_2_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_3_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_4_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_5_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_6_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_7_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_8_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_9_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_10_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_11_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_12_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_13_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_14_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_15_wakeup_ports_3_bits_uop_debug_pc = io_wakeup_ports_3_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_iq_type_0 = io_wakeup_ports_3_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_iq_type_1 = io_wakeup_ports_3_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_iq_type_2 = io_wakeup_ports_3_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_iq_type_3 = io_wakeup_ports_3_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fu_code_0 = io_wakeup_ports_3_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fu_code_1 = io_wakeup_ports_3_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fu_code_2 = io_wakeup_ports_3_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fu_code_3 = io_wakeup_ports_3_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fu_code_4 = io_wakeup_ports_3_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fu_code_5 = io_wakeup_ports_3_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fu_code_6 = io_wakeup_ports_3_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fu_code_7 = io_wakeup_ports_3_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fu_code_8 = io_wakeup_ports_3_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fu_code_9 = io_wakeup_ports_3_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_iw_issued = io_wakeup_ports_3_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_3_bits_uop_iw_p1_speculative_child = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_3_bits_uop_iw_p2_speculative_child = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_3_bits_uop_dis_col_sel = io_wakeup_ports_3_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_0_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_1_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_2_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_3_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_4_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_5_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_6_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_7_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_8_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_9_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_10_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_11_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_12_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_13_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_14_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_15_wakeup_ports_3_bits_uop_br_mask = io_wakeup_ports_3_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_12_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_13_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_14_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_15_wakeup_ports_3_bits_uop_br_tag = io_wakeup_ports_3_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_12_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_13_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_14_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_15_wakeup_ports_3_bits_uop_br_type = io_wakeup_ports_3_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_is_sfb = io_wakeup_ports_3_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_is_fence = io_wakeup_ports_3_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_is_fencei = io_wakeup_ports_3_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_is_sfence = io_wakeup_ports_3_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_is_amo = io_wakeup_ports_3_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_is_eret = io_wakeup_ports_3_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_is_sys_pc2epc = io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_is_rocc = io_wakeup_ports_3_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_is_mov = io_wakeup_ports_3_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_3_bits_uop_ftq_idx = io_wakeup_ports_3_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_edge_inst = io_wakeup_ports_3_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_3_bits_uop_pc_lob = io_wakeup_ports_3_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_taken = io_wakeup_ports_3_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_imm_rename = io_wakeup_ports_3_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_3_bits_uop_imm_sel = io_wakeup_ports_3_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_3_bits_uop_pimm = io_wakeup_ports_3_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_0_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_1_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_2_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_3_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_4_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_5_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_6_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_7_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_8_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_9_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_10_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_11_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_12_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_13_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_14_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_15_wakeup_ports_3_bits_uop_imm_packed = io_wakeup_ports_3_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_3_bits_uop_op1_sel = io_wakeup_ports_3_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_3_bits_uop_op2_sel = io_wakeup_ports_3_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_ldst = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_wen = io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_fromint = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_toint = io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_fma = io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_div = io_wakeup_ports_3_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_wflags = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fp_ctrl_vec = io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_3_bits_uop_rob_idx = io_wakeup_ports_3_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_3_bits_uop_ldq_idx = io_wakeup_ports_3_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_3_bits_uop_stq_idx = io_wakeup_ports_3_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_3_bits_uop_rxq_idx = io_wakeup_ports_3_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_3_bits_uop_pdst = io_wakeup_ports_3_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_3_bits_uop_prs1 = io_wakeup_ports_3_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_3_bits_uop_prs2 = io_wakeup_ports_3_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_3_bits_uop_prs3 = io_wakeup_ports_3_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_3_bits_uop_ppred = io_wakeup_ports_3_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_prs1_busy = io_wakeup_ports_3_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_prs2_busy = io_wakeup_ports_3_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_prs3_busy = io_wakeup_ports_3_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_ppred_busy = io_wakeup_ports_3_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_3_bits_uop_stale_pdst = io_wakeup_ports_3_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_exception = io_wakeup_ports_3_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_0_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_1_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_2_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_3_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_4_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_5_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_6_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_7_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_8_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_9_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_10_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_11_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_12_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_13_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_14_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_15_wakeup_ports_3_bits_uop_exc_cause = io_wakeup_ports_3_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_3_bits_uop_mem_cmd = io_wakeup_ports_3_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_3_bits_uop_mem_size = io_wakeup_ports_3_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_mem_signed = io_wakeup_ports_3_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_uses_ldq = io_wakeup_ports_3_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_uses_stq = io_wakeup_ports_3_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_is_unique = io_wakeup_ports_3_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_flush_on_commit = io_wakeup_ports_3_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_3_bits_uop_csr_cmd = io_wakeup_ports_3_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_ldst_is_rs1 = io_wakeup_ports_3_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_3_bits_uop_ldst = io_wakeup_ports_3_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_3_bits_uop_lrs1 = io_wakeup_ports_3_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_3_bits_uop_lrs2 = io_wakeup_ports_3_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_3_bits_uop_lrs3 = io_wakeup_ports_3_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_3_bits_uop_dst_rtype = io_wakeup_ports_3_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_3_bits_uop_lrs1_rtype = io_wakeup_ports_3_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_3_bits_uop_lrs2_rtype = io_wakeup_ports_3_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_frs3_en = io_wakeup_ports_3_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fcn_dw = io_wakeup_ports_3_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_3_bits_uop_fcn_op = io_wakeup_ports_3_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_fp_val = io_wakeup_ports_3_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_3_bits_uop_fp_rm = io_wakeup_ports_3_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_3_bits_uop_fp_typ = io_wakeup_ports_3_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_xcpt_pf_if = io_wakeup_ports_3_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_xcpt_ae_if = io_wakeup_ports_3_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_xcpt_ma_if = io_wakeup_ports_3_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_bp_debug_if = io_wakeup_ports_3_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_3_bits_uop_bp_xcpt_if = io_wakeup_ports_3_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_3_bits_uop_debug_fsrc = io_wakeup_ports_3_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_3_bits_uop_debug_tsrc = io_wakeup_ports_3_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_wakeup_ports_4_bits_uop_inst = io_wakeup_ports_4_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_wakeup_ports_4_bits_uop_inst = io_wakeup_ports_4_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_wakeup_ports_4_bits_uop_inst = io_wakeup_ports_4_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_wakeup_ports_4_bits_uop_inst = io_wakeup_ports_4_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_wakeup_ports_4_bits_uop_inst = io_wakeup_ports_4_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_wakeup_ports_4_bits_uop_inst = io_wakeup_ports_4_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_wakeup_ports_4_bits_uop_inst = io_wakeup_ports_4_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_wakeup_ports_4_bits_uop_inst = io_wakeup_ports_4_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_wakeup_ports_4_bits_uop_inst = io_wakeup_ports_4_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_wakeup_ports_4_bits_uop_inst = io_wakeup_ports_4_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_wakeup_ports_4_bits_uop_inst = io_wakeup_ports_4_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_wakeup_ports_4_bits_uop_inst = io_wakeup_ports_4_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_12_wakeup_ports_4_bits_uop_inst = io_wakeup_ports_4_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_13_wakeup_ports_4_bits_uop_inst = io_wakeup_ports_4_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_14_wakeup_ports_4_bits_uop_inst = io_wakeup_ports_4_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_15_wakeup_ports_4_bits_uop_inst = io_wakeup_ports_4_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_wakeup_ports_4_bits_uop_debug_inst = io_wakeup_ports_4_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_wakeup_ports_4_bits_uop_debug_inst = io_wakeup_ports_4_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_wakeup_ports_4_bits_uop_debug_inst = io_wakeup_ports_4_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_wakeup_ports_4_bits_uop_debug_inst = io_wakeup_ports_4_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_wakeup_ports_4_bits_uop_debug_inst = io_wakeup_ports_4_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_wakeup_ports_4_bits_uop_debug_inst = io_wakeup_ports_4_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_wakeup_ports_4_bits_uop_debug_inst = io_wakeup_ports_4_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_wakeup_ports_4_bits_uop_debug_inst = io_wakeup_ports_4_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_wakeup_ports_4_bits_uop_debug_inst = io_wakeup_ports_4_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_wakeup_ports_4_bits_uop_debug_inst = io_wakeup_ports_4_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_wakeup_ports_4_bits_uop_debug_inst = io_wakeup_ports_4_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_wakeup_ports_4_bits_uop_debug_inst = io_wakeup_ports_4_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_12_wakeup_ports_4_bits_uop_debug_inst = io_wakeup_ports_4_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_13_wakeup_ports_4_bits_uop_debug_inst = io_wakeup_ports_4_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_14_wakeup_ports_4_bits_uop_debug_inst = io_wakeup_ports_4_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_15_wakeup_ports_4_bits_uop_debug_inst = io_wakeup_ports_4_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_is_rvc = io_wakeup_ports_4_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_is_rvc = io_wakeup_ports_4_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_is_rvc = io_wakeup_ports_4_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_is_rvc = io_wakeup_ports_4_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_is_rvc = io_wakeup_ports_4_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_is_rvc = io_wakeup_ports_4_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_is_rvc = io_wakeup_ports_4_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_is_rvc = io_wakeup_ports_4_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_is_rvc = io_wakeup_ports_4_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_is_rvc = io_wakeup_ports_4_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_is_rvc = io_wakeup_ports_4_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_is_rvc = io_wakeup_ports_4_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_is_rvc = io_wakeup_ports_4_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_is_rvc = io_wakeup_ports_4_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_is_rvc = io_wakeup_ports_4_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_is_rvc = io_wakeup_ports_4_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_0_wakeup_ports_4_bits_uop_debug_pc = io_wakeup_ports_4_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_1_wakeup_ports_4_bits_uop_debug_pc = io_wakeup_ports_4_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_2_wakeup_ports_4_bits_uop_debug_pc = io_wakeup_ports_4_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_3_wakeup_ports_4_bits_uop_debug_pc = io_wakeup_ports_4_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_4_wakeup_ports_4_bits_uop_debug_pc = io_wakeup_ports_4_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_5_wakeup_ports_4_bits_uop_debug_pc = io_wakeup_ports_4_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_6_wakeup_ports_4_bits_uop_debug_pc = io_wakeup_ports_4_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_7_wakeup_ports_4_bits_uop_debug_pc = io_wakeup_ports_4_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_8_wakeup_ports_4_bits_uop_debug_pc = io_wakeup_ports_4_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_9_wakeup_ports_4_bits_uop_debug_pc = io_wakeup_ports_4_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_10_wakeup_ports_4_bits_uop_debug_pc = io_wakeup_ports_4_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_11_wakeup_ports_4_bits_uop_debug_pc = io_wakeup_ports_4_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_12_wakeup_ports_4_bits_uop_debug_pc = io_wakeup_ports_4_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_13_wakeup_ports_4_bits_uop_debug_pc = io_wakeup_ports_4_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_14_wakeup_ports_4_bits_uop_debug_pc = io_wakeup_ports_4_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_15_wakeup_ports_4_bits_uop_debug_pc = io_wakeup_ports_4_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_iq_type_0 = io_wakeup_ports_4_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_iq_type_0 = io_wakeup_ports_4_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_iq_type_0 = io_wakeup_ports_4_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_iq_type_0 = io_wakeup_ports_4_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_iq_type_0 = io_wakeup_ports_4_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_iq_type_0 = io_wakeup_ports_4_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_iq_type_0 = io_wakeup_ports_4_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_iq_type_0 = io_wakeup_ports_4_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_iq_type_0 = io_wakeup_ports_4_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_iq_type_0 = io_wakeup_ports_4_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_iq_type_0 = io_wakeup_ports_4_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_iq_type_0 = io_wakeup_ports_4_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_iq_type_0 = io_wakeup_ports_4_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_iq_type_0 = io_wakeup_ports_4_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_iq_type_0 = io_wakeup_ports_4_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_iq_type_0 = io_wakeup_ports_4_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_iq_type_1 = io_wakeup_ports_4_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_iq_type_1 = io_wakeup_ports_4_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_iq_type_1 = io_wakeup_ports_4_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_iq_type_1 = io_wakeup_ports_4_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_iq_type_1 = io_wakeup_ports_4_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_iq_type_1 = io_wakeup_ports_4_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_iq_type_1 = io_wakeup_ports_4_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_iq_type_1 = io_wakeup_ports_4_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_iq_type_1 = io_wakeup_ports_4_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_iq_type_1 = io_wakeup_ports_4_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_iq_type_1 = io_wakeup_ports_4_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_iq_type_1 = io_wakeup_ports_4_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_iq_type_1 = io_wakeup_ports_4_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_iq_type_1 = io_wakeup_ports_4_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_iq_type_1 = io_wakeup_ports_4_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_iq_type_1 = io_wakeup_ports_4_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_iq_type_2 = io_wakeup_ports_4_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_iq_type_2 = io_wakeup_ports_4_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_iq_type_2 = io_wakeup_ports_4_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_iq_type_2 = io_wakeup_ports_4_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_iq_type_2 = io_wakeup_ports_4_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_iq_type_2 = io_wakeup_ports_4_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_iq_type_2 = io_wakeup_ports_4_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_iq_type_2 = io_wakeup_ports_4_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_iq_type_2 = io_wakeup_ports_4_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_iq_type_2 = io_wakeup_ports_4_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_iq_type_2 = io_wakeup_ports_4_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_iq_type_2 = io_wakeup_ports_4_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_iq_type_2 = io_wakeup_ports_4_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_iq_type_2 = io_wakeup_ports_4_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_iq_type_2 = io_wakeup_ports_4_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_iq_type_2 = io_wakeup_ports_4_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_iq_type_3 = io_wakeup_ports_4_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_iq_type_3 = io_wakeup_ports_4_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_iq_type_3 = io_wakeup_ports_4_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_iq_type_3 = io_wakeup_ports_4_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_iq_type_3 = io_wakeup_ports_4_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_iq_type_3 = io_wakeup_ports_4_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_iq_type_3 = io_wakeup_ports_4_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_iq_type_3 = io_wakeup_ports_4_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_iq_type_3 = io_wakeup_ports_4_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_iq_type_3 = io_wakeup_ports_4_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_iq_type_3 = io_wakeup_ports_4_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_iq_type_3 = io_wakeup_ports_4_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_iq_type_3 = io_wakeup_ports_4_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_iq_type_3 = io_wakeup_ports_4_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_iq_type_3 = io_wakeup_ports_4_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_iq_type_3 = io_wakeup_ports_4_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fu_code_0 = io_wakeup_ports_4_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fu_code_0 = io_wakeup_ports_4_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fu_code_0 = io_wakeup_ports_4_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fu_code_0 = io_wakeup_ports_4_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fu_code_0 = io_wakeup_ports_4_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fu_code_0 = io_wakeup_ports_4_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fu_code_0 = io_wakeup_ports_4_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fu_code_0 = io_wakeup_ports_4_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fu_code_0 = io_wakeup_ports_4_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fu_code_0 = io_wakeup_ports_4_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fu_code_0 = io_wakeup_ports_4_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fu_code_0 = io_wakeup_ports_4_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fu_code_0 = io_wakeup_ports_4_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fu_code_0 = io_wakeup_ports_4_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fu_code_0 = io_wakeup_ports_4_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fu_code_0 = io_wakeup_ports_4_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fu_code_1 = io_wakeup_ports_4_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fu_code_1 = io_wakeup_ports_4_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fu_code_1 = io_wakeup_ports_4_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fu_code_1 = io_wakeup_ports_4_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fu_code_1 = io_wakeup_ports_4_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fu_code_1 = io_wakeup_ports_4_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fu_code_1 = io_wakeup_ports_4_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fu_code_1 = io_wakeup_ports_4_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fu_code_1 = io_wakeup_ports_4_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fu_code_1 = io_wakeup_ports_4_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fu_code_1 = io_wakeup_ports_4_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fu_code_1 = io_wakeup_ports_4_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fu_code_1 = io_wakeup_ports_4_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fu_code_1 = io_wakeup_ports_4_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fu_code_1 = io_wakeup_ports_4_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fu_code_1 = io_wakeup_ports_4_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fu_code_2 = io_wakeup_ports_4_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fu_code_2 = io_wakeup_ports_4_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fu_code_2 = io_wakeup_ports_4_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fu_code_2 = io_wakeup_ports_4_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fu_code_2 = io_wakeup_ports_4_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fu_code_2 = io_wakeup_ports_4_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fu_code_2 = io_wakeup_ports_4_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fu_code_2 = io_wakeup_ports_4_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fu_code_2 = io_wakeup_ports_4_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fu_code_2 = io_wakeup_ports_4_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fu_code_2 = io_wakeup_ports_4_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fu_code_2 = io_wakeup_ports_4_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fu_code_2 = io_wakeup_ports_4_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fu_code_2 = io_wakeup_ports_4_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fu_code_2 = io_wakeup_ports_4_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fu_code_2 = io_wakeup_ports_4_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fu_code_3 = io_wakeup_ports_4_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fu_code_3 = io_wakeup_ports_4_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fu_code_3 = io_wakeup_ports_4_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fu_code_3 = io_wakeup_ports_4_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fu_code_3 = io_wakeup_ports_4_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fu_code_3 = io_wakeup_ports_4_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fu_code_3 = io_wakeup_ports_4_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fu_code_3 = io_wakeup_ports_4_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fu_code_3 = io_wakeup_ports_4_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fu_code_3 = io_wakeup_ports_4_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fu_code_3 = io_wakeup_ports_4_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fu_code_3 = io_wakeup_ports_4_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fu_code_3 = io_wakeup_ports_4_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fu_code_3 = io_wakeup_ports_4_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fu_code_3 = io_wakeup_ports_4_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fu_code_3 = io_wakeup_ports_4_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fu_code_4 = io_wakeup_ports_4_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fu_code_4 = io_wakeup_ports_4_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fu_code_4 = io_wakeup_ports_4_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fu_code_4 = io_wakeup_ports_4_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fu_code_4 = io_wakeup_ports_4_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fu_code_4 = io_wakeup_ports_4_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fu_code_4 = io_wakeup_ports_4_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fu_code_4 = io_wakeup_ports_4_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fu_code_4 = io_wakeup_ports_4_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fu_code_4 = io_wakeup_ports_4_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fu_code_4 = io_wakeup_ports_4_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fu_code_4 = io_wakeup_ports_4_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fu_code_4 = io_wakeup_ports_4_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fu_code_4 = io_wakeup_ports_4_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fu_code_4 = io_wakeup_ports_4_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fu_code_4 = io_wakeup_ports_4_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fu_code_5 = io_wakeup_ports_4_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fu_code_5 = io_wakeup_ports_4_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fu_code_5 = io_wakeup_ports_4_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fu_code_5 = io_wakeup_ports_4_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fu_code_5 = io_wakeup_ports_4_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fu_code_5 = io_wakeup_ports_4_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fu_code_5 = io_wakeup_ports_4_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fu_code_5 = io_wakeup_ports_4_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fu_code_5 = io_wakeup_ports_4_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fu_code_5 = io_wakeup_ports_4_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fu_code_5 = io_wakeup_ports_4_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fu_code_5 = io_wakeup_ports_4_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fu_code_5 = io_wakeup_ports_4_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fu_code_5 = io_wakeup_ports_4_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fu_code_5 = io_wakeup_ports_4_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fu_code_5 = io_wakeup_ports_4_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fu_code_6 = io_wakeup_ports_4_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fu_code_6 = io_wakeup_ports_4_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fu_code_6 = io_wakeup_ports_4_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fu_code_6 = io_wakeup_ports_4_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fu_code_6 = io_wakeup_ports_4_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fu_code_6 = io_wakeup_ports_4_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fu_code_6 = io_wakeup_ports_4_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fu_code_6 = io_wakeup_ports_4_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fu_code_6 = io_wakeup_ports_4_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fu_code_6 = io_wakeup_ports_4_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fu_code_6 = io_wakeup_ports_4_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fu_code_6 = io_wakeup_ports_4_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fu_code_6 = io_wakeup_ports_4_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fu_code_6 = io_wakeup_ports_4_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fu_code_6 = io_wakeup_ports_4_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fu_code_6 = io_wakeup_ports_4_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fu_code_7 = io_wakeup_ports_4_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fu_code_7 = io_wakeup_ports_4_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fu_code_7 = io_wakeup_ports_4_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fu_code_7 = io_wakeup_ports_4_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fu_code_7 = io_wakeup_ports_4_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fu_code_7 = io_wakeup_ports_4_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fu_code_7 = io_wakeup_ports_4_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fu_code_7 = io_wakeup_ports_4_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fu_code_7 = io_wakeup_ports_4_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fu_code_7 = io_wakeup_ports_4_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fu_code_7 = io_wakeup_ports_4_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fu_code_7 = io_wakeup_ports_4_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fu_code_7 = io_wakeup_ports_4_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fu_code_7 = io_wakeup_ports_4_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fu_code_7 = io_wakeup_ports_4_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fu_code_7 = io_wakeup_ports_4_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fu_code_8 = io_wakeup_ports_4_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fu_code_8 = io_wakeup_ports_4_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fu_code_8 = io_wakeup_ports_4_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fu_code_8 = io_wakeup_ports_4_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fu_code_8 = io_wakeup_ports_4_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fu_code_8 = io_wakeup_ports_4_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fu_code_8 = io_wakeup_ports_4_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fu_code_8 = io_wakeup_ports_4_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fu_code_8 = io_wakeup_ports_4_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fu_code_8 = io_wakeup_ports_4_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fu_code_8 = io_wakeup_ports_4_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fu_code_8 = io_wakeup_ports_4_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fu_code_8 = io_wakeup_ports_4_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fu_code_8 = io_wakeup_ports_4_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fu_code_8 = io_wakeup_ports_4_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fu_code_8 = io_wakeup_ports_4_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fu_code_9 = io_wakeup_ports_4_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fu_code_9 = io_wakeup_ports_4_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fu_code_9 = io_wakeup_ports_4_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fu_code_9 = io_wakeup_ports_4_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fu_code_9 = io_wakeup_ports_4_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fu_code_9 = io_wakeup_ports_4_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fu_code_9 = io_wakeup_ports_4_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fu_code_9 = io_wakeup_ports_4_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fu_code_9 = io_wakeup_ports_4_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fu_code_9 = io_wakeup_ports_4_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fu_code_9 = io_wakeup_ports_4_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fu_code_9 = io_wakeup_ports_4_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fu_code_9 = io_wakeup_ports_4_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fu_code_9 = io_wakeup_ports_4_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fu_code_9 = io_wakeup_ports_4_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fu_code_9 = io_wakeup_ports_4_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_iw_issued = io_wakeup_ports_4_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_iw_issued = io_wakeup_ports_4_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_iw_issued = io_wakeup_ports_4_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_iw_issued = io_wakeup_ports_4_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_iw_issued = io_wakeup_ports_4_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_iw_issued = io_wakeup_ports_4_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_iw_issued = io_wakeup_ports_4_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_iw_issued = io_wakeup_ports_4_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_iw_issued = io_wakeup_ports_4_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_iw_issued = io_wakeup_ports_4_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_iw_issued = io_wakeup_ports_4_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_iw_issued = io_wakeup_ports_4_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_iw_issued = io_wakeup_ports_4_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_iw_issued = io_wakeup_ports_4_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_iw_issued = io_wakeup_ports_4_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_iw_issued = io_wakeup_ports_4_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_4_bits_uop_iw_p1_speculative_child = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_4_bits_uop_iw_p1_speculative_child = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_4_bits_uop_iw_p1_speculative_child = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_4_bits_uop_iw_p1_speculative_child = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_4_bits_uop_iw_p1_speculative_child = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_4_bits_uop_iw_p1_speculative_child = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_4_bits_uop_iw_p1_speculative_child = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_4_bits_uop_iw_p1_speculative_child = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_4_bits_uop_iw_p1_speculative_child = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_4_bits_uop_iw_p1_speculative_child = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_4_bits_uop_iw_p1_speculative_child = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_4_bits_uop_iw_p1_speculative_child = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_4_bits_uop_iw_p1_speculative_child = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_4_bits_uop_iw_p1_speculative_child = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_4_bits_uop_iw_p1_speculative_child = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_4_bits_uop_iw_p1_speculative_child = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_4_bits_uop_iw_p2_speculative_child = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_4_bits_uop_iw_p2_speculative_child = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_4_bits_uop_iw_p2_speculative_child = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_4_bits_uop_iw_p2_speculative_child = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_4_bits_uop_iw_p2_speculative_child = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_4_bits_uop_iw_p2_speculative_child = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_4_bits_uop_iw_p2_speculative_child = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_4_bits_uop_iw_p2_speculative_child = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_4_bits_uop_iw_p2_speculative_child = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_4_bits_uop_iw_p2_speculative_child = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_4_bits_uop_iw_p2_speculative_child = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_4_bits_uop_iw_p2_speculative_child = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_4_bits_uop_iw_p2_speculative_child = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_4_bits_uop_iw_p2_speculative_child = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_4_bits_uop_iw_p2_speculative_child = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_4_bits_uop_iw_p2_speculative_child = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_4_bits_uop_dis_col_sel = io_wakeup_ports_4_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_4_bits_uop_dis_col_sel = io_wakeup_ports_4_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_4_bits_uop_dis_col_sel = io_wakeup_ports_4_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_4_bits_uop_dis_col_sel = io_wakeup_ports_4_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_4_bits_uop_dis_col_sel = io_wakeup_ports_4_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_4_bits_uop_dis_col_sel = io_wakeup_ports_4_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_4_bits_uop_dis_col_sel = io_wakeup_ports_4_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_4_bits_uop_dis_col_sel = io_wakeup_ports_4_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_4_bits_uop_dis_col_sel = io_wakeup_ports_4_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_4_bits_uop_dis_col_sel = io_wakeup_ports_4_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_4_bits_uop_dis_col_sel = io_wakeup_ports_4_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_4_bits_uop_dis_col_sel = io_wakeup_ports_4_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_4_bits_uop_dis_col_sel = io_wakeup_ports_4_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_4_bits_uop_dis_col_sel = io_wakeup_ports_4_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_4_bits_uop_dis_col_sel = io_wakeup_ports_4_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_4_bits_uop_dis_col_sel = io_wakeup_ports_4_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_0_wakeup_ports_4_bits_uop_br_mask = io_wakeup_ports_4_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_1_wakeup_ports_4_bits_uop_br_mask = io_wakeup_ports_4_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_2_wakeup_ports_4_bits_uop_br_mask = io_wakeup_ports_4_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_3_wakeup_ports_4_bits_uop_br_mask = io_wakeup_ports_4_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_4_wakeup_ports_4_bits_uop_br_mask = io_wakeup_ports_4_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_5_wakeup_ports_4_bits_uop_br_mask = io_wakeup_ports_4_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_6_wakeup_ports_4_bits_uop_br_mask = io_wakeup_ports_4_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_7_wakeup_ports_4_bits_uop_br_mask = io_wakeup_ports_4_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_8_wakeup_ports_4_bits_uop_br_mask = io_wakeup_ports_4_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_9_wakeup_ports_4_bits_uop_br_mask = io_wakeup_ports_4_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_10_wakeup_ports_4_bits_uop_br_mask = io_wakeup_ports_4_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_11_wakeup_ports_4_bits_uop_br_mask = io_wakeup_ports_4_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_12_wakeup_ports_4_bits_uop_br_mask = io_wakeup_ports_4_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_13_wakeup_ports_4_bits_uop_br_mask = io_wakeup_ports_4_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_14_wakeup_ports_4_bits_uop_br_mask = io_wakeup_ports_4_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_15_wakeup_ports_4_bits_uop_br_mask = io_wakeup_ports_4_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_4_bits_uop_br_tag = io_wakeup_ports_4_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_4_bits_uop_br_tag = io_wakeup_ports_4_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_4_bits_uop_br_tag = io_wakeup_ports_4_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_4_bits_uop_br_tag = io_wakeup_ports_4_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_4_bits_uop_br_tag = io_wakeup_ports_4_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_4_bits_uop_br_tag = io_wakeup_ports_4_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_4_bits_uop_br_tag = io_wakeup_ports_4_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_4_bits_uop_br_tag = io_wakeup_ports_4_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_4_bits_uop_br_tag = io_wakeup_ports_4_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_4_bits_uop_br_tag = io_wakeup_ports_4_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_4_bits_uop_br_tag = io_wakeup_ports_4_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_4_bits_uop_br_tag = io_wakeup_ports_4_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_12_wakeup_ports_4_bits_uop_br_tag = io_wakeup_ports_4_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_13_wakeup_ports_4_bits_uop_br_tag = io_wakeup_ports_4_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_14_wakeup_ports_4_bits_uop_br_tag = io_wakeup_ports_4_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_15_wakeup_ports_4_bits_uop_br_tag = io_wakeup_ports_4_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_4_bits_uop_br_type = io_wakeup_ports_4_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_4_bits_uop_br_type = io_wakeup_ports_4_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_4_bits_uop_br_type = io_wakeup_ports_4_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_4_bits_uop_br_type = io_wakeup_ports_4_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_4_bits_uop_br_type = io_wakeup_ports_4_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_4_bits_uop_br_type = io_wakeup_ports_4_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_4_bits_uop_br_type = io_wakeup_ports_4_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_4_bits_uop_br_type = io_wakeup_ports_4_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_4_bits_uop_br_type = io_wakeup_ports_4_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_4_bits_uop_br_type = io_wakeup_ports_4_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_4_bits_uop_br_type = io_wakeup_ports_4_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_4_bits_uop_br_type = io_wakeup_ports_4_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_12_wakeup_ports_4_bits_uop_br_type = io_wakeup_ports_4_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_13_wakeup_ports_4_bits_uop_br_type = io_wakeup_ports_4_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_14_wakeup_ports_4_bits_uop_br_type = io_wakeup_ports_4_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_15_wakeup_ports_4_bits_uop_br_type = io_wakeup_ports_4_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_is_sfb = io_wakeup_ports_4_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_is_sfb = io_wakeup_ports_4_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_is_sfb = io_wakeup_ports_4_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_is_sfb = io_wakeup_ports_4_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_is_sfb = io_wakeup_ports_4_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_is_sfb = io_wakeup_ports_4_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_is_sfb = io_wakeup_ports_4_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_is_sfb = io_wakeup_ports_4_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_is_sfb = io_wakeup_ports_4_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_is_sfb = io_wakeup_ports_4_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_is_sfb = io_wakeup_ports_4_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_is_sfb = io_wakeup_ports_4_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_is_sfb = io_wakeup_ports_4_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_is_sfb = io_wakeup_ports_4_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_is_sfb = io_wakeup_ports_4_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_is_sfb = io_wakeup_ports_4_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_is_fence = io_wakeup_ports_4_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_is_fence = io_wakeup_ports_4_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_is_fence = io_wakeup_ports_4_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_is_fence = io_wakeup_ports_4_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_is_fence = io_wakeup_ports_4_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_is_fence = io_wakeup_ports_4_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_is_fence = io_wakeup_ports_4_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_is_fence = io_wakeup_ports_4_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_is_fence = io_wakeup_ports_4_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_is_fence = io_wakeup_ports_4_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_is_fence = io_wakeup_ports_4_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_is_fence = io_wakeup_ports_4_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_is_fence = io_wakeup_ports_4_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_is_fence = io_wakeup_ports_4_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_is_fence = io_wakeup_ports_4_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_is_fence = io_wakeup_ports_4_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_is_fencei = io_wakeup_ports_4_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_is_fencei = io_wakeup_ports_4_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_is_fencei = io_wakeup_ports_4_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_is_fencei = io_wakeup_ports_4_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_is_fencei = io_wakeup_ports_4_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_is_fencei = io_wakeup_ports_4_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_is_fencei = io_wakeup_ports_4_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_is_fencei = io_wakeup_ports_4_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_is_fencei = io_wakeup_ports_4_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_is_fencei = io_wakeup_ports_4_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_is_fencei = io_wakeup_ports_4_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_is_fencei = io_wakeup_ports_4_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_is_fencei = io_wakeup_ports_4_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_is_fencei = io_wakeup_ports_4_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_is_fencei = io_wakeup_ports_4_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_is_fencei = io_wakeup_ports_4_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_is_sfence = io_wakeup_ports_4_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_is_sfence = io_wakeup_ports_4_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_is_sfence = io_wakeup_ports_4_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_is_sfence = io_wakeup_ports_4_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_is_sfence = io_wakeup_ports_4_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_is_sfence = io_wakeup_ports_4_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_is_sfence = io_wakeup_ports_4_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_is_sfence = io_wakeup_ports_4_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_is_sfence = io_wakeup_ports_4_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_is_sfence = io_wakeup_ports_4_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_is_sfence = io_wakeup_ports_4_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_is_sfence = io_wakeup_ports_4_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_is_sfence = io_wakeup_ports_4_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_is_sfence = io_wakeup_ports_4_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_is_sfence = io_wakeup_ports_4_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_is_sfence = io_wakeup_ports_4_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_is_amo = io_wakeup_ports_4_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_is_amo = io_wakeup_ports_4_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_is_amo = io_wakeup_ports_4_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_is_amo = io_wakeup_ports_4_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_is_amo = io_wakeup_ports_4_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_is_amo = io_wakeup_ports_4_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_is_amo = io_wakeup_ports_4_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_is_amo = io_wakeup_ports_4_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_is_amo = io_wakeup_ports_4_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_is_amo = io_wakeup_ports_4_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_is_amo = io_wakeup_ports_4_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_is_amo = io_wakeup_ports_4_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_is_amo = io_wakeup_ports_4_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_is_amo = io_wakeup_ports_4_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_is_amo = io_wakeup_ports_4_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_is_amo = io_wakeup_ports_4_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_is_eret = io_wakeup_ports_4_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_is_eret = io_wakeup_ports_4_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_is_eret = io_wakeup_ports_4_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_is_eret = io_wakeup_ports_4_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_is_eret = io_wakeup_ports_4_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_is_eret = io_wakeup_ports_4_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_is_eret = io_wakeup_ports_4_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_is_eret = io_wakeup_ports_4_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_is_eret = io_wakeup_ports_4_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_is_eret = io_wakeup_ports_4_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_is_eret = io_wakeup_ports_4_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_is_eret = io_wakeup_ports_4_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_is_eret = io_wakeup_ports_4_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_is_eret = io_wakeup_ports_4_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_is_eret = io_wakeup_ports_4_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_is_eret = io_wakeup_ports_4_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_is_sys_pc2epc = io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_is_sys_pc2epc = io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_is_sys_pc2epc = io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_is_sys_pc2epc = io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_is_sys_pc2epc = io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_is_sys_pc2epc = io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_is_sys_pc2epc = io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_is_sys_pc2epc = io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_is_sys_pc2epc = io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_is_sys_pc2epc = io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_is_sys_pc2epc = io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_is_sys_pc2epc = io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_is_sys_pc2epc = io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_is_sys_pc2epc = io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_is_sys_pc2epc = io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_is_sys_pc2epc = io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_is_rocc = io_wakeup_ports_4_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_is_rocc = io_wakeup_ports_4_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_is_rocc = io_wakeup_ports_4_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_is_rocc = io_wakeup_ports_4_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_is_rocc = io_wakeup_ports_4_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_is_rocc = io_wakeup_ports_4_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_is_rocc = io_wakeup_ports_4_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_is_rocc = io_wakeup_ports_4_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_is_rocc = io_wakeup_ports_4_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_is_rocc = io_wakeup_ports_4_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_is_rocc = io_wakeup_ports_4_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_is_rocc = io_wakeup_ports_4_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_is_rocc = io_wakeup_ports_4_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_is_rocc = io_wakeup_ports_4_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_is_rocc = io_wakeup_ports_4_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_is_rocc = io_wakeup_ports_4_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_is_mov = io_wakeup_ports_4_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_is_mov = io_wakeup_ports_4_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_is_mov = io_wakeup_ports_4_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_is_mov = io_wakeup_ports_4_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_is_mov = io_wakeup_ports_4_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_is_mov = io_wakeup_ports_4_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_is_mov = io_wakeup_ports_4_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_is_mov = io_wakeup_ports_4_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_is_mov = io_wakeup_ports_4_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_is_mov = io_wakeup_ports_4_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_is_mov = io_wakeup_ports_4_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_is_mov = io_wakeup_ports_4_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_is_mov = io_wakeup_ports_4_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_is_mov = io_wakeup_ports_4_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_is_mov = io_wakeup_ports_4_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_is_mov = io_wakeup_ports_4_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_4_bits_uop_ftq_idx = io_wakeup_ports_4_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_4_bits_uop_ftq_idx = io_wakeup_ports_4_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_4_bits_uop_ftq_idx = io_wakeup_ports_4_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_4_bits_uop_ftq_idx = io_wakeup_ports_4_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_4_bits_uop_ftq_idx = io_wakeup_ports_4_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_4_bits_uop_ftq_idx = io_wakeup_ports_4_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_4_bits_uop_ftq_idx = io_wakeup_ports_4_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_4_bits_uop_ftq_idx = io_wakeup_ports_4_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_4_bits_uop_ftq_idx = io_wakeup_ports_4_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_4_bits_uop_ftq_idx = io_wakeup_ports_4_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_4_bits_uop_ftq_idx = io_wakeup_ports_4_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_4_bits_uop_ftq_idx = io_wakeup_ports_4_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_4_bits_uop_ftq_idx = io_wakeup_ports_4_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_4_bits_uop_ftq_idx = io_wakeup_ports_4_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_4_bits_uop_ftq_idx = io_wakeup_ports_4_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_4_bits_uop_ftq_idx = io_wakeup_ports_4_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_edge_inst = io_wakeup_ports_4_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_edge_inst = io_wakeup_ports_4_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_edge_inst = io_wakeup_ports_4_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_edge_inst = io_wakeup_ports_4_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_edge_inst = io_wakeup_ports_4_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_edge_inst = io_wakeup_ports_4_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_edge_inst = io_wakeup_ports_4_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_edge_inst = io_wakeup_ports_4_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_edge_inst = io_wakeup_ports_4_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_edge_inst = io_wakeup_ports_4_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_edge_inst = io_wakeup_ports_4_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_edge_inst = io_wakeup_ports_4_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_edge_inst = io_wakeup_ports_4_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_edge_inst = io_wakeup_ports_4_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_edge_inst = io_wakeup_ports_4_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_edge_inst = io_wakeup_ports_4_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_4_bits_uop_pc_lob = io_wakeup_ports_4_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_4_bits_uop_pc_lob = io_wakeup_ports_4_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_4_bits_uop_pc_lob = io_wakeup_ports_4_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_4_bits_uop_pc_lob = io_wakeup_ports_4_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_4_bits_uop_pc_lob = io_wakeup_ports_4_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_4_bits_uop_pc_lob = io_wakeup_ports_4_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_4_bits_uop_pc_lob = io_wakeup_ports_4_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_4_bits_uop_pc_lob = io_wakeup_ports_4_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_4_bits_uop_pc_lob = io_wakeup_ports_4_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_4_bits_uop_pc_lob = io_wakeup_ports_4_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_4_bits_uop_pc_lob = io_wakeup_ports_4_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_4_bits_uop_pc_lob = io_wakeup_ports_4_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_4_bits_uop_pc_lob = io_wakeup_ports_4_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_4_bits_uop_pc_lob = io_wakeup_ports_4_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_4_bits_uop_pc_lob = io_wakeup_ports_4_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_4_bits_uop_pc_lob = io_wakeup_ports_4_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_taken = io_wakeup_ports_4_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_taken = io_wakeup_ports_4_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_taken = io_wakeup_ports_4_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_taken = io_wakeup_ports_4_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_taken = io_wakeup_ports_4_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_taken = io_wakeup_ports_4_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_taken = io_wakeup_ports_4_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_taken = io_wakeup_ports_4_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_taken = io_wakeup_ports_4_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_taken = io_wakeup_ports_4_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_taken = io_wakeup_ports_4_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_taken = io_wakeup_ports_4_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_taken = io_wakeup_ports_4_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_taken = io_wakeup_ports_4_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_taken = io_wakeup_ports_4_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_taken = io_wakeup_ports_4_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_imm_rename = io_wakeup_ports_4_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_imm_rename = io_wakeup_ports_4_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_imm_rename = io_wakeup_ports_4_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_imm_rename = io_wakeup_ports_4_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_imm_rename = io_wakeup_ports_4_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_imm_rename = io_wakeup_ports_4_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_imm_rename = io_wakeup_ports_4_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_imm_rename = io_wakeup_ports_4_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_imm_rename = io_wakeup_ports_4_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_imm_rename = io_wakeup_ports_4_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_imm_rename = io_wakeup_ports_4_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_imm_rename = io_wakeup_ports_4_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_imm_rename = io_wakeup_ports_4_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_imm_rename = io_wakeup_ports_4_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_imm_rename = io_wakeup_ports_4_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_imm_rename = io_wakeup_ports_4_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_4_bits_uop_imm_sel = io_wakeup_ports_4_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_4_bits_uop_imm_sel = io_wakeup_ports_4_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_4_bits_uop_imm_sel = io_wakeup_ports_4_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_4_bits_uop_imm_sel = io_wakeup_ports_4_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_4_bits_uop_imm_sel = io_wakeup_ports_4_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_4_bits_uop_imm_sel = io_wakeup_ports_4_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_4_bits_uop_imm_sel = io_wakeup_ports_4_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_4_bits_uop_imm_sel = io_wakeup_ports_4_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_4_bits_uop_imm_sel = io_wakeup_ports_4_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_4_bits_uop_imm_sel = io_wakeup_ports_4_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_4_bits_uop_imm_sel = io_wakeup_ports_4_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_4_bits_uop_imm_sel = io_wakeup_ports_4_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_4_bits_uop_imm_sel = io_wakeup_ports_4_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_4_bits_uop_imm_sel = io_wakeup_ports_4_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_4_bits_uop_imm_sel = io_wakeup_ports_4_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_4_bits_uop_imm_sel = io_wakeup_ports_4_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_4_bits_uop_pimm = io_wakeup_ports_4_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_4_bits_uop_pimm = io_wakeup_ports_4_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_4_bits_uop_pimm = io_wakeup_ports_4_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_4_bits_uop_pimm = io_wakeup_ports_4_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_4_bits_uop_pimm = io_wakeup_ports_4_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_4_bits_uop_pimm = io_wakeup_ports_4_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_4_bits_uop_pimm = io_wakeup_ports_4_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_4_bits_uop_pimm = io_wakeup_ports_4_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_4_bits_uop_pimm = io_wakeup_ports_4_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_4_bits_uop_pimm = io_wakeup_ports_4_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_4_bits_uop_pimm = io_wakeup_ports_4_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_4_bits_uop_pimm = io_wakeup_ports_4_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_4_bits_uop_pimm = io_wakeup_ports_4_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_4_bits_uop_pimm = io_wakeup_ports_4_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_4_bits_uop_pimm = io_wakeup_ports_4_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_4_bits_uop_pimm = io_wakeup_ports_4_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_0_wakeup_ports_4_bits_uop_imm_packed = io_wakeup_ports_4_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_1_wakeup_ports_4_bits_uop_imm_packed = io_wakeup_ports_4_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_2_wakeup_ports_4_bits_uop_imm_packed = io_wakeup_ports_4_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_3_wakeup_ports_4_bits_uop_imm_packed = io_wakeup_ports_4_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_4_wakeup_ports_4_bits_uop_imm_packed = io_wakeup_ports_4_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_5_wakeup_ports_4_bits_uop_imm_packed = io_wakeup_ports_4_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_6_wakeup_ports_4_bits_uop_imm_packed = io_wakeup_ports_4_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_7_wakeup_ports_4_bits_uop_imm_packed = io_wakeup_ports_4_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_8_wakeup_ports_4_bits_uop_imm_packed = io_wakeup_ports_4_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_9_wakeup_ports_4_bits_uop_imm_packed = io_wakeup_ports_4_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_10_wakeup_ports_4_bits_uop_imm_packed = io_wakeup_ports_4_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_11_wakeup_ports_4_bits_uop_imm_packed = io_wakeup_ports_4_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_12_wakeup_ports_4_bits_uop_imm_packed = io_wakeup_ports_4_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_13_wakeup_ports_4_bits_uop_imm_packed = io_wakeup_ports_4_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_14_wakeup_ports_4_bits_uop_imm_packed = io_wakeup_ports_4_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_15_wakeup_ports_4_bits_uop_imm_packed = io_wakeup_ports_4_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_4_bits_uop_op1_sel = io_wakeup_ports_4_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_4_bits_uop_op1_sel = io_wakeup_ports_4_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_4_bits_uop_op1_sel = io_wakeup_ports_4_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_4_bits_uop_op1_sel = io_wakeup_ports_4_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_4_bits_uop_op1_sel = io_wakeup_ports_4_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_4_bits_uop_op1_sel = io_wakeup_ports_4_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_4_bits_uop_op1_sel = io_wakeup_ports_4_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_4_bits_uop_op1_sel = io_wakeup_ports_4_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_4_bits_uop_op1_sel = io_wakeup_ports_4_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_4_bits_uop_op1_sel = io_wakeup_ports_4_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_4_bits_uop_op1_sel = io_wakeup_ports_4_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_4_bits_uop_op1_sel = io_wakeup_ports_4_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_4_bits_uop_op1_sel = io_wakeup_ports_4_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_4_bits_uop_op1_sel = io_wakeup_ports_4_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_4_bits_uop_op1_sel = io_wakeup_ports_4_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_4_bits_uop_op1_sel = io_wakeup_ports_4_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_4_bits_uop_op2_sel = io_wakeup_ports_4_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_4_bits_uop_op2_sel = io_wakeup_ports_4_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_4_bits_uop_op2_sel = io_wakeup_ports_4_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_4_bits_uop_op2_sel = io_wakeup_ports_4_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_4_bits_uop_op2_sel = io_wakeup_ports_4_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_4_bits_uop_op2_sel = io_wakeup_ports_4_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_4_bits_uop_op2_sel = io_wakeup_ports_4_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_4_bits_uop_op2_sel = io_wakeup_ports_4_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_4_bits_uop_op2_sel = io_wakeup_ports_4_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_4_bits_uop_op2_sel = io_wakeup_ports_4_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_4_bits_uop_op2_sel = io_wakeup_ports_4_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_4_bits_uop_op2_sel = io_wakeup_ports_4_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_4_bits_uop_op2_sel = io_wakeup_ports_4_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_4_bits_uop_op2_sel = io_wakeup_ports_4_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_4_bits_uop_op2_sel = io_wakeup_ports_4_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_4_bits_uop_op2_sel = io_wakeup_ports_4_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fp_ctrl_ldst = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fp_ctrl_ldst = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fp_ctrl_ldst = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fp_ctrl_ldst = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fp_ctrl_ldst = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fp_ctrl_ldst = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fp_ctrl_ldst = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fp_ctrl_ldst = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fp_ctrl_ldst = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fp_ctrl_ldst = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fp_ctrl_ldst = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fp_ctrl_ldst = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fp_ctrl_ldst = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fp_ctrl_ldst = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fp_ctrl_ldst = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fp_ctrl_ldst = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fp_ctrl_wen = io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fp_ctrl_wen = io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fp_ctrl_wen = io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fp_ctrl_wen = io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fp_ctrl_wen = io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fp_ctrl_wen = io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fp_ctrl_wen = io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fp_ctrl_wen = io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fp_ctrl_wen = io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fp_ctrl_wen = io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fp_ctrl_wen = io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fp_ctrl_wen = io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fp_ctrl_wen = io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fp_ctrl_wen = io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fp_ctrl_wen = io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fp_ctrl_wen = io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fp_ctrl_fromint = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fp_ctrl_fromint = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fp_ctrl_fromint = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fp_ctrl_fromint = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fp_ctrl_fromint = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fp_ctrl_fromint = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fp_ctrl_fromint = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fp_ctrl_fromint = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fp_ctrl_fromint = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fp_ctrl_fromint = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fp_ctrl_fromint = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fp_ctrl_fromint = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fp_ctrl_fromint = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fp_ctrl_fromint = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fp_ctrl_fromint = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fp_ctrl_fromint = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fp_ctrl_toint = io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fp_ctrl_toint = io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fp_ctrl_toint = io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fp_ctrl_toint = io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fp_ctrl_toint = io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fp_ctrl_toint = io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fp_ctrl_toint = io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fp_ctrl_toint = io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fp_ctrl_toint = io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fp_ctrl_toint = io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fp_ctrl_toint = io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fp_ctrl_toint = io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fp_ctrl_toint = io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fp_ctrl_toint = io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fp_ctrl_toint = io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fp_ctrl_toint = io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fp_ctrl_fma = io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fp_ctrl_fma = io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fp_ctrl_fma = io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fp_ctrl_fma = io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fp_ctrl_fma = io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fp_ctrl_fma = io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fp_ctrl_fma = io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fp_ctrl_fma = io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fp_ctrl_fma = io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fp_ctrl_fma = io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fp_ctrl_fma = io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fp_ctrl_fma = io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fp_ctrl_fma = io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fp_ctrl_fma = io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fp_ctrl_fma = io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fp_ctrl_fma = io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fp_ctrl_div = io_wakeup_ports_4_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fp_ctrl_div = io_wakeup_ports_4_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fp_ctrl_div = io_wakeup_ports_4_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fp_ctrl_div = io_wakeup_ports_4_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fp_ctrl_div = io_wakeup_ports_4_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fp_ctrl_div = io_wakeup_ports_4_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fp_ctrl_div = io_wakeup_ports_4_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fp_ctrl_div = io_wakeup_ports_4_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fp_ctrl_div = io_wakeup_ports_4_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fp_ctrl_div = io_wakeup_ports_4_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fp_ctrl_div = io_wakeup_ports_4_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fp_ctrl_div = io_wakeup_ports_4_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fp_ctrl_div = io_wakeup_ports_4_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fp_ctrl_div = io_wakeup_ports_4_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fp_ctrl_div = io_wakeup_ports_4_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fp_ctrl_div = io_wakeup_ports_4_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fp_ctrl_wflags = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fp_ctrl_wflags = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fp_ctrl_wflags = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fp_ctrl_wflags = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fp_ctrl_wflags = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fp_ctrl_wflags = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fp_ctrl_wflags = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fp_ctrl_wflags = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fp_ctrl_wflags = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fp_ctrl_wflags = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fp_ctrl_wflags = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fp_ctrl_wflags = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fp_ctrl_wflags = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fp_ctrl_wflags = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fp_ctrl_wflags = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fp_ctrl_wflags = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fp_ctrl_vec = io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fp_ctrl_vec = io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fp_ctrl_vec = io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fp_ctrl_vec = io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fp_ctrl_vec = io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fp_ctrl_vec = io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fp_ctrl_vec = io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fp_ctrl_vec = io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fp_ctrl_vec = io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fp_ctrl_vec = io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fp_ctrl_vec = io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fp_ctrl_vec = io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fp_ctrl_vec = io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fp_ctrl_vec = io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fp_ctrl_vec = io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fp_ctrl_vec = io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_4_bits_uop_rob_idx = io_wakeup_ports_4_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_4_bits_uop_rob_idx = io_wakeup_ports_4_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_4_bits_uop_rob_idx = io_wakeup_ports_4_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_4_bits_uop_rob_idx = io_wakeup_ports_4_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_4_bits_uop_rob_idx = io_wakeup_ports_4_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_4_bits_uop_rob_idx = io_wakeup_ports_4_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_4_bits_uop_rob_idx = io_wakeup_ports_4_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_4_bits_uop_rob_idx = io_wakeup_ports_4_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_4_bits_uop_rob_idx = io_wakeup_ports_4_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_4_bits_uop_rob_idx = io_wakeup_ports_4_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_4_bits_uop_rob_idx = io_wakeup_ports_4_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_4_bits_uop_rob_idx = io_wakeup_ports_4_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_4_bits_uop_rob_idx = io_wakeup_ports_4_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_4_bits_uop_rob_idx = io_wakeup_ports_4_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_4_bits_uop_rob_idx = io_wakeup_ports_4_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_4_bits_uop_rob_idx = io_wakeup_ports_4_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_4_bits_uop_ldq_idx = io_wakeup_ports_4_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_4_bits_uop_ldq_idx = io_wakeup_ports_4_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_4_bits_uop_ldq_idx = io_wakeup_ports_4_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_4_bits_uop_ldq_idx = io_wakeup_ports_4_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_4_bits_uop_ldq_idx = io_wakeup_ports_4_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_4_bits_uop_ldq_idx = io_wakeup_ports_4_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_4_bits_uop_ldq_idx = io_wakeup_ports_4_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_4_bits_uop_ldq_idx = io_wakeup_ports_4_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_4_bits_uop_ldq_idx = io_wakeup_ports_4_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_4_bits_uop_ldq_idx = io_wakeup_ports_4_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_4_bits_uop_ldq_idx = io_wakeup_ports_4_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_4_bits_uop_ldq_idx = io_wakeup_ports_4_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_4_bits_uop_ldq_idx = io_wakeup_ports_4_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_4_bits_uop_ldq_idx = io_wakeup_ports_4_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_4_bits_uop_ldq_idx = io_wakeup_ports_4_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_4_bits_uop_ldq_idx = io_wakeup_ports_4_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_4_bits_uop_stq_idx = io_wakeup_ports_4_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_4_bits_uop_stq_idx = io_wakeup_ports_4_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_4_bits_uop_stq_idx = io_wakeup_ports_4_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_4_bits_uop_stq_idx = io_wakeup_ports_4_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_4_bits_uop_stq_idx = io_wakeup_ports_4_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_4_bits_uop_stq_idx = io_wakeup_ports_4_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_4_bits_uop_stq_idx = io_wakeup_ports_4_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_4_bits_uop_stq_idx = io_wakeup_ports_4_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_4_bits_uop_stq_idx = io_wakeup_ports_4_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_4_bits_uop_stq_idx = io_wakeup_ports_4_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_4_bits_uop_stq_idx = io_wakeup_ports_4_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_4_bits_uop_stq_idx = io_wakeup_ports_4_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_4_bits_uop_stq_idx = io_wakeup_ports_4_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_4_bits_uop_stq_idx = io_wakeup_ports_4_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_4_bits_uop_stq_idx = io_wakeup_ports_4_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_4_bits_uop_stq_idx = io_wakeup_ports_4_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_4_bits_uop_rxq_idx = io_wakeup_ports_4_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_4_bits_uop_rxq_idx = io_wakeup_ports_4_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_4_bits_uop_rxq_idx = io_wakeup_ports_4_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_4_bits_uop_rxq_idx = io_wakeup_ports_4_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_4_bits_uop_rxq_idx = io_wakeup_ports_4_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_4_bits_uop_rxq_idx = io_wakeup_ports_4_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_4_bits_uop_rxq_idx = io_wakeup_ports_4_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_4_bits_uop_rxq_idx = io_wakeup_ports_4_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_4_bits_uop_rxq_idx = io_wakeup_ports_4_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_4_bits_uop_rxq_idx = io_wakeup_ports_4_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_4_bits_uop_rxq_idx = io_wakeup_ports_4_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_4_bits_uop_rxq_idx = io_wakeup_ports_4_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_4_bits_uop_rxq_idx = io_wakeup_ports_4_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_4_bits_uop_rxq_idx = io_wakeup_ports_4_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_4_bits_uop_rxq_idx = io_wakeup_ports_4_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_4_bits_uop_rxq_idx = io_wakeup_ports_4_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_4_bits_uop_pdst = io_wakeup_ports_4_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_4_bits_uop_pdst = io_wakeup_ports_4_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_4_bits_uop_pdst = io_wakeup_ports_4_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_4_bits_uop_pdst = io_wakeup_ports_4_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_4_bits_uop_pdst = io_wakeup_ports_4_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_4_bits_uop_pdst = io_wakeup_ports_4_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_4_bits_uop_pdst = io_wakeup_ports_4_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_4_bits_uop_pdst = io_wakeup_ports_4_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_4_bits_uop_pdst = io_wakeup_ports_4_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_4_bits_uop_pdst = io_wakeup_ports_4_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_4_bits_uop_pdst = io_wakeup_ports_4_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_4_bits_uop_pdst = io_wakeup_ports_4_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_4_bits_uop_pdst = io_wakeup_ports_4_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_4_bits_uop_pdst = io_wakeup_ports_4_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_4_bits_uop_pdst = io_wakeup_ports_4_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_4_bits_uop_pdst = io_wakeup_ports_4_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_4_bits_uop_prs1 = io_wakeup_ports_4_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_4_bits_uop_prs1 = io_wakeup_ports_4_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_4_bits_uop_prs1 = io_wakeup_ports_4_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_4_bits_uop_prs1 = io_wakeup_ports_4_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_4_bits_uop_prs1 = io_wakeup_ports_4_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_4_bits_uop_prs1 = io_wakeup_ports_4_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_4_bits_uop_prs1 = io_wakeup_ports_4_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_4_bits_uop_prs1 = io_wakeup_ports_4_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_4_bits_uop_prs1 = io_wakeup_ports_4_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_4_bits_uop_prs1 = io_wakeup_ports_4_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_4_bits_uop_prs1 = io_wakeup_ports_4_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_4_bits_uop_prs1 = io_wakeup_ports_4_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_4_bits_uop_prs1 = io_wakeup_ports_4_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_4_bits_uop_prs1 = io_wakeup_ports_4_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_4_bits_uop_prs1 = io_wakeup_ports_4_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_4_bits_uop_prs1 = io_wakeup_ports_4_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_4_bits_uop_prs2 = io_wakeup_ports_4_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_4_bits_uop_prs2 = io_wakeup_ports_4_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_4_bits_uop_prs2 = io_wakeup_ports_4_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_4_bits_uop_prs2 = io_wakeup_ports_4_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_4_bits_uop_prs2 = io_wakeup_ports_4_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_4_bits_uop_prs2 = io_wakeup_ports_4_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_4_bits_uop_prs2 = io_wakeup_ports_4_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_4_bits_uop_prs2 = io_wakeup_ports_4_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_4_bits_uop_prs2 = io_wakeup_ports_4_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_4_bits_uop_prs2 = io_wakeup_ports_4_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_4_bits_uop_prs2 = io_wakeup_ports_4_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_4_bits_uop_prs2 = io_wakeup_ports_4_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_4_bits_uop_prs2 = io_wakeup_ports_4_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_4_bits_uop_prs2 = io_wakeup_ports_4_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_4_bits_uop_prs2 = io_wakeup_ports_4_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_4_bits_uop_prs2 = io_wakeup_ports_4_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_4_bits_uop_prs3 = io_wakeup_ports_4_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_4_bits_uop_prs3 = io_wakeup_ports_4_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_4_bits_uop_prs3 = io_wakeup_ports_4_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_4_bits_uop_prs3 = io_wakeup_ports_4_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_4_bits_uop_prs3 = io_wakeup_ports_4_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_4_bits_uop_prs3 = io_wakeup_ports_4_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_4_bits_uop_prs3 = io_wakeup_ports_4_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_4_bits_uop_prs3 = io_wakeup_ports_4_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_4_bits_uop_prs3 = io_wakeup_ports_4_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_4_bits_uop_prs3 = io_wakeup_ports_4_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_4_bits_uop_prs3 = io_wakeup_ports_4_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_4_bits_uop_prs3 = io_wakeup_ports_4_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_4_bits_uop_prs3 = io_wakeup_ports_4_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_4_bits_uop_prs3 = io_wakeup_ports_4_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_4_bits_uop_prs3 = io_wakeup_ports_4_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_4_bits_uop_prs3 = io_wakeup_ports_4_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_4_bits_uop_ppred = io_wakeup_ports_4_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_4_bits_uop_ppred = io_wakeup_ports_4_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_4_bits_uop_ppred = io_wakeup_ports_4_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_4_bits_uop_ppred = io_wakeup_ports_4_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_4_bits_uop_ppred = io_wakeup_ports_4_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_4_bits_uop_ppred = io_wakeup_ports_4_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_4_bits_uop_ppred = io_wakeup_ports_4_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_4_bits_uop_ppred = io_wakeup_ports_4_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_4_bits_uop_ppred = io_wakeup_ports_4_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_4_bits_uop_ppred = io_wakeup_ports_4_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_4_bits_uop_ppred = io_wakeup_ports_4_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_4_bits_uop_ppred = io_wakeup_ports_4_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_4_bits_uop_ppred = io_wakeup_ports_4_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_4_bits_uop_ppred = io_wakeup_ports_4_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_4_bits_uop_ppred = io_wakeup_ports_4_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_4_bits_uop_ppred = io_wakeup_ports_4_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_prs1_busy = io_wakeup_ports_4_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_prs1_busy = io_wakeup_ports_4_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_prs1_busy = io_wakeup_ports_4_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_prs1_busy = io_wakeup_ports_4_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_prs1_busy = io_wakeup_ports_4_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_prs1_busy = io_wakeup_ports_4_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_prs1_busy = io_wakeup_ports_4_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_prs1_busy = io_wakeup_ports_4_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_prs1_busy = io_wakeup_ports_4_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_prs1_busy = io_wakeup_ports_4_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_prs1_busy = io_wakeup_ports_4_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_prs1_busy = io_wakeup_ports_4_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_prs1_busy = io_wakeup_ports_4_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_prs1_busy = io_wakeup_ports_4_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_prs1_busy = io_wakeup_ports_4_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_prs1_busy = io_wakeup_ports_4_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_prs2_busy = io_wakeup_ports_4_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_prs2_busy = io_wakeup_ports_4_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_prs2_busy = io_wakeup_ports_4_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_prs2_busy = io_wakeup_ports_4_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_prs2_busy = io_wakeup_ports_4_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_prs2_busy = io_wakeup_ports_4_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_prs2_busy = io_wakeup_ports_4_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_prs2_busy = io_wakeup_ports_4_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_prs2_busy = io_wakeup_ports_4_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_prs2_busy = io_wakeup_ports_4_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_prs2_busy = io_wakeup_ports_4_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_prs2_busy = io_wakeup_ports_4_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_prs2_busy = io_wakeup_ports_4_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_prs2_busy = io_wakeup_ports_4_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_prs2_busy = io_wakeup_ports_4_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_prs2_busy = io_wakeup_ports_4_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_prs3_busy = io_wakeup_ports_4_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_prs3_busy = io_wakeup_ports_4_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_prs3_busy = io_wakeup_ports_4_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_prs3_busy = io_wakeup_ports_4_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_prs3_busy = io_wakeup_ports_4_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_prs3_busy = io_wakeup_ports_4_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_prs3_busy = io_wakeup_ports_4_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_prs3_busy = io_wakeup_ports_4_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_prs3_busy = io_wakeup_ports_4_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_prs3_busy = io_wakeup_ports_4_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_prs3_busy = io_wakeup_ports_4_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_prs3_busy = io_wakeup_ports_4_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_prs3_busy = io_wakeup_ports_4_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_prs3_busy = io_wakeup_ports_4_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_prs3_busy = io_wakeup_ports_4_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_prs3_busy = io_wakeup_ports_4_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_ppred_busy = io_wakeup_ports_4_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_ppred_busy = io_wakeup_ports_4_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_ppred_busy = io_wakeup_ports_4_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_ppred_busy = io_wakeup_ports_4_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_ppred_busy = io_wakeup_ports_4_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_ppred_busy = io_wakeup_ports_4_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_ppred_busy = io_wakeup_ports_4_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_ppred_busy = io_wakeup_ports_4_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_ppred_busy = io_wakeup_ports_4_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_ppred_busy = io_wakeup_ports_4_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_ppred_busy = io_wakeup_ports_4_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_ppred_busy = io_wakeup_ports_4_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_ppred_busy = io_wakeup_ports_4_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_ppred_busy = io_wakeup_ports_4_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_ppred_busy = io_wakeup_ports_4_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_ppred_busy = io_wakeup_ports_4_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_4_bits_uop_stale_pdst = io_wakeup_ports_4_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_4_bits_uop_stale_pdst = io_wakeup_ports_4_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_4_bits_uop_stale_pdst = io_wakeup_ports_4_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_4_bits_uop_stale_pdst = io_wakeup_ports_4_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_4_bits_uop_stale_pdst = io_wakeup_ports_4_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_4_bits_uop_stale_pdst = io_wakeup_ports_4_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_4_bits_uop_stale_pdst = io_wakeup_ports_4_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_4_bits_uop_stale_pdst = io_wakeup_ports_4_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_4_bits_uop_stale_pdst = io_wakeup_ports_4_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_4_bits_uop_stale_pdst = io_wakeup_ports_4_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_4_bits_uop_stale_pdst = io_wakeup_ports_4_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_4_bits_uop_stale_pdst = io_wakeup_ports_4_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_4_bits_uop_stale_pdst = io_wakeup_ports_4_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_4_bits_uop_stale_pdst = io_wakeup_ports_4_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_4_bits_uop_stale_pdst = io_wakeup_ports_4_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_4_bits_uop_stale_pdst = io_wakeup_ports_4_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_exception = io_wakeup_ports_4_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_exception = io_wakeup_ports_4_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_exception = io_wakeup_ports_4_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_exception = io_wakeup_ports_4_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_exception = io_wakeup_ports_4_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_exception = io_wakeup_ports_4_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_exception = io_wakeup_ports_4_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_exception = io_wakeup_ports_4_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_exception = io_wakeup_ports_4_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_exception = io_wakeup_ports_4_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_exception = io_wakeup_ports_4_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_exception = io_wakeup_ports_4_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_exception = io_wakeup_ports_4_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_exception = io_wakeup_ports_4_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_exception = io_wakeup_ports_4_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_exception = io_wakeup_ports_4_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_0_wakeup_ports_4_bits_uop_exc_cause = io_wakeup_ports_4_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_1_wakeup_ports_4_bits_uop_exc_cause = io_wakeup_ports_4_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_2_wakeup_ports_4_bits_uop_exc_cause = io_wakeup_ports_4_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_3_wakeup_ports_4_bits_uop_exc_cause = io_wakeup_ports_4_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_4_wakeup_ports_4_bits_uop_exc_cause = io_wakeup_ports_4_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_5_wakeup_ports_4_bits_uop_exc_cause = io_wakeup_ports_4_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_6_wakeup_ports_4_bits_uop_exc_cause = io_wakeup_ports_4_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_7_wakeup_ports_4_bits_uop_exc_cause = io_wakeup_ports_4_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_8_wakeup_ports_4_bits_uop_exc_cause = io_wakeup_ports_4_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_9_wakeup_ports_4_bits_uop_exc_cause = io_wakeup_ports_4_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_10_wakeup_ports_4_bits_uop_exc_cause = io_wakeup_ports_4_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_11_wakeup_ports_4_bits_uop_exc_cause = io_wakeup_ports_4_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_12_wakeup_ports_4_bits_uop_exc_cause = io_wakeup_ports_4_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_13_wakeup_ports_4_bits_uop_exc_cause = io_wakeup_ports_4_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_14_wakeup_ports_4_bits_uop_exc_cause = io_wakeup_ports_4_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_15_wakeup_ports_4_bits_uop_exc_cause = io_wakeup_ports_4_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_4_bits_uop_mem_cmd = io_wakeup_ports_4_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_4_bits_uop_mem_cmd = io_wakeup_ports_4_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_4_bits_uop_mem_cmd = io_wakeup_ports_4_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_4_bits_uop_mem_cmd = io_wakeup_ports_4_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_4_bits_uop_mem_cmd = io_wakeup_ports_4_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_4_bits_uop_mem_cmd = io_wakeup_ports_4_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_4_bits_uop_mem_cmd = io_wakeup_ports_4_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_4_bits_uop_mem_cmd = io_wakeup_ports_4_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_4_bits_uop_mem_cmd = io_wakeup_ports_4_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_4_bits_uop_mem_cmd = io_wakeup_ports_4_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_4_bits_uop_mem_cmd = io_wakeup_ports_4_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_4_bits_uop_mem_cmd = io_wakeup_ports_4_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_4_bits_uop_mem_cmd = io_wakeup_ports_4_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_4_bits_uop_mem_cmd = io_wakeup_ports_4_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_4_bits_uop_mem_cmd = io_wakeup_ports_4_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_4_bits_uop_mem_cmd = io_wakeup_ports_4_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_4_bits_uop_mem_size = io_wakeup_ports_4_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_4_bits_uop_mem_size = io_wakeup_ports_4_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_4_bits_uop_mem_size = io_wakeup_ports_4_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_4_bits_uop_mem_size = io_wakeup_ports_4_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_4_bits_uop_mem_size = io_wakeup_ports_4_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_4_bits_uop_mem_size = io_wakeup_ports_4_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_4_bits_uop_mem_size = io_wakeup_ports_4_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_4_bits_uop_mem_size = io_wakeup_ports_4_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_4_bits_uop_mem_size = io_wakeup_ports_4_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_4_bits_uop_mem_size = io_wakeup_ports_4_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_4_bits_uop_mem_size = io_wakeup_ports_4_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_4_bits_uop_mem_size = io_wakeup_ports_4_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_4_bits_uop_mem_size = io_wakeup_ports_4_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_4_bits_uop_mem_size = io_wakeup_ports_4_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_4_bits_uop_mem_size = io_wakeup_ports_4_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_4_bits_uop_mem_size = io_wakeup_ports_4_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_mem_signed = io_wakeup_ports_4_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_mem_signed = io_wakeup_ports_4_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_mem_signed = io_wakeup_ports_4_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_mem_signed = io_wakeup_ports_4_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_mem_signed = io_wakeup_ports_4_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_mem_signed = io_wakeup_ports_4_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_mem_signed = io_wakeup_ports_4_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_mem_signed = io_wakeup_ports_4_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_mem_signed = io_wakeup_ports_4_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_mem_signed = io_wakeup_ports_4_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_mem_signed = io_wakeup_ports_4_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_mem_signed = io_wakeup_ports_4_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_mem_signed = io_wakeup_ports_4_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_mem_signed = io_wakeup_ports_4_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_mem_signed = io_wakeup_ports_4_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_mem_signed = io_wakeup_ports_4_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_uses_ldq = io_wakeup_ports_4_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_uses_ldq = io_wakeup_ports_4_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_uses_ldq = io_wakeup_ports_4_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_uses_ldq = io_wakeup_ports_4_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_uses_ldq = io_wakeup_ports_4_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_uses_ldq = io_wakeup_ports_4_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_uses_ldq = io_wakeup_ports_4_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_uses_ldq = io_wakeup_ports_4_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_uses_ldq = io_wakeup_ports_4_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_uses_ldq = io_wakeup_ports_4_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_uses_ldq = io_wakeup_ports_4_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_uses_ldq = io_wakeup_ports_4_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_uses_ldq = io_wakeup_ports_4_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_uses_ldq = io_wakeup_ports_4_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_uses_ldq = io_wakeup_ports_4_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_uses_ldq = io_wakeup_ports_4_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_uses_stq = io_wakeup_ports_4_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_uses_stq = io_wakeup_ports_4_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_uses_stq = io_wakeup_ports_4_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_uses_stq = io_wakeup_ports_4_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_uses_stq = io_wakeup_ports_4_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_uses_stq = io_wakeup_ports_4_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_uses_stq = io_wakeup_ports_4_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_uses_stq = io_wakeup_ports_4_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_uses_stq = io_wakeup_ports_4_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_uses_stq = io_wakeup_ports_4_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_uses_stq = io_wakeup_ports_4_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_uses_stq = io_wakeup_ports_4_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_uses_stq = io_wakeup_ports_4_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_uses_stq = io_wakeup_ports_4_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_uses_stq = io_wakeup_ports_4_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_uses_stq = io_wakeup_ports_4_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_is_unique = io_wakeup_ports_4_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_is_unique = io_wakeup_ports_4_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_is_unique = io_wakeup_ports_4_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_is_unique = io_wakeup_ports_4_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_is_unique = io_wakeup_ports_4_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_is_unique = io_wakeup_ports_4_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_is_unique = io_wakeup_ports_4_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_is_unique = io_wakeup_ports_4_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_is_unique = io_wakeup_ports_4_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_is_unique = io_wakeup_ports_4_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_is_unique = io_wakeup_ports_4_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_is_unique = io_wakeup_ports_4_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_is_unique = io_wakeup_ports_4_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_is_unique = io_wakeup_ports_4_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_is_unique = io_wakeup_ports_4_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_is_unique = io_wakeup_ports_4_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_flush_on_commit = io_wakeup_ports_4_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_flush_on_commit = io_wakeup_ports_4_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_flush_on_commit = io_wakeup_ports_4_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_flush_on_commit = io_wakeup_ports_4_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_flush_on_commit = io_wakeup_ports_4_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_flush_on_commit = io_wakeup_ports_4_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_flush_on_commit = io_wakeup_ports_4_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_flush_on_commit = io_wakeup_ports_4_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_flush_on_commit = io_wakeup_ports_4_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_flush_on_commit = io_wakeup_ports_4_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_flush_on_commit = io_wakeup_ports_4_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_flush_on_commit = io_wakeup_ports_4_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_flush_on_commit = io_wakeup_ports_4_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_flush_on_commit = io_wakeup_ports_4_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_flush_on_commit = io_wakeup_ports_4_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_flush_on_commit = io_wakeup_ports_4_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_4_bits_uop_csr_cmd = io_wakeup_ports_4_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_4_bits_uop_csr_cmd = io_wakeup_ports_4_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_4_bits_uop_csr_cmd = io_wakeup_ports_4_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_4_bits_uop_csr_cmd = io_wakeup_ports_4_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_4_bits_uop_csr_cmd = io_wakeup_ports_4_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_4_bits_uop_csr_cmd = io_wakeup_ports_4_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_4_bits_uop_csr_cmd = io_wakeup_ports_4_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_4_bits_uop_csr_cmd = io_wakeup_ports_4_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_4_bits_uop_csr_cmd = io_wakeup_ports_4_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_4_bits_uop_csr_cmd = io_wakeup_ports_4_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_4_bits_uop_csr_cmd = io_wakeup_ports_4_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_4_bits_uop_csr_cmd = io_wakeup_ports_4_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_4_bits_uop_csr_cmd = io_wakeup_ports_4_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_4_bits_uop_csr_cmd = io_wakeup_ports_4_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_4_bits_uop_csr_cmd = io_wakeup_ports_4_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_4_bits_uop_csr_cmd = io_wakeup_ports_4_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_ldst_is_rs1 = io_wakeup_ports_4_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_ldst_is_rs1 = io_wakeup_ports_4_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_ldst_is_rs1 = io_wakeup_ports_4_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_ldst_is_rs1 = io_wakeup_ports_4_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_ldst_is_rs1 = io_wakeup_ports_4_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_ldst_is_rs1 = io_wakeup_ports_4_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_ldst_is_rs1 = io_wakeup_ports_4_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_ldst_is_rs1 = io_wakeup_ports_4_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_ldst_is_rs1 = io_wakeup_ports_4_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_ldst_is_rs1 = io_wakeup_ports_4_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_ldst_is_rs1 = io_wakeup_ports_4_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_ldst_is_rs1 = io_wakeup_ports_4_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_ldst_is_rs1 = io_wakeup_ports_4_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_ldst_is_rs1 = io_wakeup_ports_4_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_ldst_is_rs1 = io_wakeup_ports_4_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_ldst_is_rs1 = io_wakeup_ports_4_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_4_bits_uop_ldst = io_wakeup_ports_4_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_4_bits_uop_ldst = io_wakeup_ports_4_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_4_bits_uop_ldst = io_wakeup_ports_4_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_4_bits_uop_ldst = io_wakeup_ports_4_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_4_bits_uop_ldst = io_wakeup_ports_4_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_4_bits_uop_ldst = io_wakeup_ports_4_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_4_bits_uop_ldst = io_wakeup_ports_4_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_4_bits_uop_ldst = io_wakeup_ports_4_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_4_bits_uop_ldst = io_wakeup_ports_4_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_4_bits_uop_ldst = io_wakeup_ports_4_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_4_bits_uop_ldst = io_wakeup_ports_4_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_4_bits_uop_ldst = io_wakeup_ports_4_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_4_bits_uop_ldst = io_wakeup_ports_4_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_4_bits_uop_ldst = io_wakeup_ports_4_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_4_bits_uop_ldst = io_wakeup_ports_4_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_4_bits_uop_ldst = io_wakeup_ports_4_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_4_bits_uop_lrs1 = io_wakeup_ports_4_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_4_bits_uop_lrs1 = io_wakeup_ports_4_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_4_bits_uop_lrs1 = io_wakeup_ports_4_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_4_bits_uop_lrs1 = io_wakeup_ports_4_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_4_bits_uop_lrs1 = io_wakeup_ports_4_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_4_bits_uop_lrs1 = io_wakeup_ports_4_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_4_bits_uop_lrs1 = io_wakeup_ports_4_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_4_bits_uop_lrs1 = io_wakeup_ports_4_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_4_bits_uop_lrs1 = io_wakeup_ports_4_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_4_bits_uop_lrs1 = io_wakeup_ports_4_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_4_bits_uop_lrs1 = io_wakeup_ports_4_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_4_bits_uop_lrs1 = io_wakeup_ports_4_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_4_bits_uop_lrs1 = io_wakeup_ports_4_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_4_bits_uop_lrs1 = io_wakeup_ports_4_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_4_bits_uop_lrs1 = io_wakeup_ports_4_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_4_bits_uop_lrs1 = io_wakeup_ports_4_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_4_bits_uop_lrs2 = io_wakeup_ports_4_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_4_bits_uop_lrs2 = io_wakeup_ports_4_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_4_bits_uop_lrs2 = io_wakeup_ports_4_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_4_bits_uop_lrs2 = io_wakeup_ports_4_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_4_bits_uop_lrs2 = io_wakeup_ports_4_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_4_bits_uop_lrs2 = io_wakeup_ports_4_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_4_bits_uop_lrs2 = io_wakeup_ports_4_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_4_bits_uop_lrs2 = io_wakeup_ports_4_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_4_bits_uop_lrs2 = io_wakeup_ports_4_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_4_bits_uop_lrs2 = io_wakeup_ports_4_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_4_bits_uop_lrs2 = io_wakeup_ports_4_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_4_bits_uop_lrs2 = io_wakeup_ports_4_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_4_bits_uop_lrs2 = io_wakeup_ports_4_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_4_bits_uop_lrs2 = io_wakeup_ports_4_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_4_bits_uop_lrs2 = io_wakeup_ports_4_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_4_bits_uop_lrs2 = io_wakeup_ports_4_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_4_bits_uop_lrs3 = io_wakeup_ports_4_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_4_bits_uop_lrs3 = io_wakeup_ports_4_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_4_bits_uop_lrs3 = io_wakeup_ports_4_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_4_bits_uop_lrs3 = io_wakeup_ports_4_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_4_bits_uop_lrs3 = io_wakeup_ports_4_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_4_bits_uop_lrs3 = io_wakeup_ports_4_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_4_bits_uop_lrs3 = io_wakeup_ports_4_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_4_bits_uop_lrs3 = io_wakeup_ports_4_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_4_bits_uop_lrs3 = io_wakeup_ports_4_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_4_bits_uop_lrs3 = io_wakeup_ports_4_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_4_bits_uop_lrs3 = io_wakeup_ports_4_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_4_bits_uop_lrs3 = io_wakeup_ports_4_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_4_bits_uop_lrs3 = io_wakeup_ports_4_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_4_bits_uop_lrs3 = io_wakeup_ports_4_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_4_bits_uop_lrs3 = io_wakeup_ports_4_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_4_bits_uop_lrs3 = io_wakeup_ports_4_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_4_bits_uop_dst_rtype = io_wakeup_ports_4_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_4_bits_uop_dst_rtype = io_wakeup_ports_4_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_4_bits_uop_dst_rtype = io_wakeup_ports_4_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_4_bits_uop_dst_rtype = io_wakeup_ports_4_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_4_bits_uop_dst_rtype = io_wakeup_ports_4_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_4_bits_uop_dst_rtype = io_wakeup_ports_4_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_4_bits_uop_dst_rtype = io_wakeup_ports_4_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_4_bits_uop_dst_rtype = io_wakeup_ports_4_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_4_bits_uop_dst_rtype = io_wakeup_ports_4_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_4_bits_uop_dst_rtype = io_wakeup_ports_4_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_4_bits_uop_dst_rtype = io_wakeup_ports_4_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_4_bits_uop_dst_rtype = io_wakeup_ports_4_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_4_bits_uop_dst_rtype = io_wakeup_ports_4_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_4_bits_uop_dst_rtype = io_wakeup_ports_4_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_4_bits_uop_dst_rtype = io_wakeup_ports_4_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_4_bits_uop_dst_rtype = io_wakeup_ports_4_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_4_bits_uop_lrs1_rtype = io_wakeup_ports_4_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_4_bits_uop_lrs1_rtype = io_wakeup_ports_4_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_4_bits_uop_lrs1_rtype = io_wakeup_ports_4_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_4_bits_uop_lrs1_rtype = io_wakeup_ports_4_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_4_bits_uop_lrs1_rtype = io_wakeup_ports_4_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_4_bits_uop_lrs1_rtype = io_wakeup_ports_4_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_4_bits_uop_lrs1_rtype = io_wakeup_ports_4_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_4_bits_uop_lrs1_rtype = io_wakeup_ports_4_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_4_bits_uop_lrs1_rtype = io_wakeup_ports_4_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_4_bits_uop_lrs1_rtype = io_wakeup_ports_4_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_4_bits_uop_lrs1_rtype = io_wakeup_ports_4_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_4_bits_uop_lrs1_rtype = io_wakeup_ports_4_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_4_bits_uop_lrs1_rtype = io_wakeup_ports_4_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_4_bits_uop_lrs1_rtype = io_wakeup_ports_4_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_4_bits_uop_lrs1_rtype = io_wakeup_ports_4_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_4_bits_uop_lrs1_rtype = io_wakeup_ports_4_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_4_bits_uop_lrs2_rtype = io_wakeup_ports_4_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_4_bits_uop_lrs2_rtype = io_wakeup_ports_4_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_4_bits_uop_lrs2_rtype = io_wakeup_ports_4_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_4_bits_uop_lrs2_rtype = io_wakeup_ports_4_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_4_bits_uop_lrs2_rtype = io_wakeup_ports_4_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_4_bits_uop_lrs2_rtype = io_wakeup_ports_4_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_4_bits_uop_lrs2_rtype = io_wakeup_ports_4_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_4_bits_uop_lrs2_rtype = io_wakeup_ports_4_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_4_bits_uop_lrs2_rtype = io_wakeup_ports_4_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_4_bits_uop_lrs2_rtype = io_wakeup_ports_4_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_4_bits_uop_lrs2_rtype = io_wakeup_ports_4_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_4_bits_uop_lrs2_rtype = io_wakeup_ports_4_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_4_bits_uop_lrs2_rtype = io_wakeup_ports_4_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_4_bits_uop_lrs2_rtype = io_wakeup_ports_4_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_4_bits_uop_lrs2_rtype = io_wakeup_ports_4_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_4_bits_uop_lrs2_rtype = io_wakeup_ports_4_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_frs3_en = io_wakeup_ports_4_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_frs3_en = io_wakeup_ports_4_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_frs3_en = io_wakeup_ports_4_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_frs3_en = io_wakeup_ports_4_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_frs3_en = io_wakeup_ports_4_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_frs3_en = io_wakeup_ports_4_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_frs3_en = io_wakeup_ports_4_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_frs3_en = io_wakeup_ports_4_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_frs3_en = io_wakeup_ports_4_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_frs3_en = io_wakeup_ports_4_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_frs3_en = io_wakeup_ports_4_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_frs3_en = io_wakeup_ports_4_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_frs3_en = io_wakeup_ports_4_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_frs3_en = io_wakeup_ports_4_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_frs3_en = io_wakeup_ports_4_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_frs3_en = io_wakeup_ports_4_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fcn_dw = io_wakeup_ports_4_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fcn_dw = io_wakeup_ports_4_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fcn_dw = io_wakeup_ports_4_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fcn_dw = io_wakeup_ports_4_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fcn_dw = io_wakeup_ports_4_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fcn_dw = io_wakeup_ports_4_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fcn_dw = io_wakeup_ports_4_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fcn_dw = io_wakeup_ports_4_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fcn_dw = io_wakeup_ports_4_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fcn_dw = io_wakeup_ports_4_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fcn_dw = io_wakeup_ports_4_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fcn_dw = io_wakeup_ports_4_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fcn_dw = io_wakeup_ports_4_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fcn_dw = io_wakeup_ports_4_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fcn_dw = io_wakeup_ports_4_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fcn_dw = io_wakeup_ports_4_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_4_bits_uop_fcn_op = io_wakeup_ports_4_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_4_bits_uop_fcn_op = io_wakeup_ports_4_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_4_bits_uop_fcn_op = io_wakeup_ports_4_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_4_bits_uop_fcn_op = io_wakeup_ports_4_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_4_bits_uop_fcn_op = io_wakeup_ports_4_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_4_bits_uop_fcn_op = io_wakeup_ports_4_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_4_bits_uop_fcn_op = io_wakeup_ports_4_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_4_bits_uop_fcn_op = io_wakeup_ports_4_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_4_bits_uop_fcn_op = io_wakeup_ports_4_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_4_bits_uop_fcn_op = io_wakeup_ports_4_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_4_bits_uop_fcn_op = io_wakeup_ports_4_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_4_bits_uop_fcn_op = io_wakeup_ports_4_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_4_bits_uop_fcn_op = io_wakeup_ports_4_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_4_bits_uop_fcn_op = io_wakeup_ports_4_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_4_bits_uop_fcn_op = io_wakeup_ports_4_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_4_bits_uop_fcn_op = io_wakeup_ports_4_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_fp_val = io_wakeup_ports_4_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_fp_val = io_wakeup_ports_4_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_fp_val = io_wakeup_ports_4_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_fp_val = io_wakeup_ports_4_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_fp_val = io_wakeup_ports_4_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_fp_val = io_wakeup_ports_4_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_fp_val = io_wakeup_ports_4_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_fp_val = io_wakeup_ports_4_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_fp_val = io_wakeup_ports_4_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_fp_val = io_wakeup_ports_4_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_fp_val = io_wakeup_ports_4_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_fp_val = io_wakeup_ports_4_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_fp_val = io_wakeup_ports_4_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_fp_val = io_wakeup_ports_4_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_fp_val = io_wakeup_ports_4_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_fp_val = io_wakeup_ports_4_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_4_bits_uop_fp_rm = io_wakeup_ports_4_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_4_bits_uop_fp_rm = io_wakeup_ports_4_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_4_bits_uop_fp_rm = io_wakeup_ports_4_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_4_bits_uop_fp_rm = io_wakeup_ports_4_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_4_bits_uop_fp_rm = io_wakeup_ports_4_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_4_bits_uop_fp_rm = io_wakeup_ports_4_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_4_bits_uop_fp_rm = io_wakeup_ports_4_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_4_bits_uop_fp_rm = io_wakeup_ports_4_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_4_bits_uop_fp_rm = io_wakeup_ports_4_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_4_bits_uop_fp_rm = io_wakeup_ports_4_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_4_bits_uop_fp_rm = io_wakeup_ports_4_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_4_bits_uop_fp_rm = io_wakeup_ports_4_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_4_bits_uop_fp_rm = io_wakeup_ports_4_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_4_bits_uop_fp_rm = io_wakeup_ports_4_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_4_bits_uop_fp_rm = io_wakeup_ports_4_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_4_bits_uop_fp_rm = io_wakeup_ports_4_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_4_bits_uop_fp_typ = io_wakeup_ports_4_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_4_bits_uop_fp_typ = io_wakeup_ports_4_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_4_bits_uop_fp_typ = io_wakeup_ports_4_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_4_bits_uop_fp_typ = io_wakeup_ports_4_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_4_bits_uop_fp_typ = io_wakeup_ports_4_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_4_bits_uop_fp_typ = io_wakeup_ports_4_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_4_bits_uop_fp_typ = io_wakeup_ports_4_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_4_bits_uop_fp_typ = io_wakeup_ports_4_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_4_bits_uop_fp_typ = io_wakeup_ports_4_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_4_bits_uop_fp_typ = io_wakeup_ports_4_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_4_bits_uop_fp_typ = io_wakeup_ports_4_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_4_bits_uop_fp_typ = io_wakeup_ports_4_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_4_bits_uop_fp_typ = io_wakeup_ports_4_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_4_bits_uop_fp_typ = io_wakeup_ports_4_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_4_bits_uop_fp_typ = io_wakeup_ports_4_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_4_bits_uop_fp_typ = io_wakeup_ports_4_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_xcpt_pf_if = io_wakeup_ports_4_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_xcpt_pf_if = io_wakeup_ports_4_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_xcpt_pf_if = io_wakeup_ports_4_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_xcpt_pf_if = io_wakeup_ports_4_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_xcpt_pf_if = io_wakeup_ports_4_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_xcpt_pf_if = io_wakeup_ports_4_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_xcpt_pf_if = io_wakeup_ports_4_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_xcpt_pf_if = io_wakeup_ports_4_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_xcpt_pf_if = io_wakeup_ports_4_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_xcpt_pf_if = io_wakeup_ports_4_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_xcpt_pf_if = io_wakeup_ports_4_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_xcpt_pf_if = io_wakeup_ports_4_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_xcpt_pf_if = io_wakeup_ports_4_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_xcpt_pf_if = io_wakeup_ports_4_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_xcpt_pf_if = io_wakeup_ports_4_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_xcpt_pf_if = io_wakeup_ports_4_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_xcpt_ae_if = io_wakeup_ports_4_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_xcpt_ae_if = io_wakeup_ports_4_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_xcpt_ae_if = io_wakeup_ports_4_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_xcpt_ae_if = io_wakeup_ports_4_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_xcpt_ae_if = io_wakeup_ports_4_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_xcpt_ae_if = io_wakeup_ports_4_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_xcpt_ae_if = io_wakeup_ports_4_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_xcpt_ae_if = io_wakeup_ports_4_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_xcpt_ae_if = io_wakeup_ports_4_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_xcpt_ae_if = io_wakeup_ports_4_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_xcpt_ae_if = io_wakeup_ports_4_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_xcpt_ae_if = io_wakeup_ports_4_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_xcpt_ae_if = io_wakeup_ports_4_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_xcpt_ae_if = io_wakeup_ports_4_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_xcpt_ae_if = io_wakeup_ports_4_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_xcpt_ae_if = io_wakeup_ports_4_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_xcpt_ma_if = io_wakeup_ports_4_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_xcpt_ma_if = io_wakeup_ports_4_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_xcpt_ma_if = io_wakeup_ports_4_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_xcpt_ma_if = io_wakeup_ports_4_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_xcpt_ma_if = io_wakeup_ports_4_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_xcpt_ma_if = io_wakeup_ports_4_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_xcpt_ma_if = io_wakeup_ports_4_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_xcpt_ma_if = io_wakeup_ports_4_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_xcpt_ma_if = io_wakeup_ports_4_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_xcpt_ma_if = io_wakeup_ports_4_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_xcpt_ma_if = io_wakeup_ports_4_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_xcpt_ma_if = io_wakeup_ports_4_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_xcpt_ma_if = io_wakeup_ports_4_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_xcpt_ma_if = io_wakeup_ports_4_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_xcpt_ma_if = io_wakeup_ports_4_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_xcpt_ma_if = io_wakeup_ports_4_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_bp_debug_if = io_wakeup_ports_4_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_bp_debug_if = io_wakeup_ports_4_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_bp_debug_if = io_wakeup_ports_4_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_bp_debug_if = io_wakeup_ports_4_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_bp_debug_if = io_wakeup_ports_4_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_bp_debug_if = io_wakeup_ports_4_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_bp_debug_if = io_wakeup_ports_4_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_bp_debug_if = io_wakeup_ports_4_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_bp_debug_if = io_wakeup_ports_4_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_bp_debug_if = io_wakeup_ports_4_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_bp_debug_if = io_wakeup_ports_4_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_bp_debug_if = io_wakeup_ports_4_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_bp_debug_if = io_wakeup_ports_4_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_bp_debug_if = io_wakeup_ports_4_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_bp_debug_if = io_wakeup_ports_4_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_bp_debug_if = io_wakeup_ports_4_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_4_bits_uop_bp_xcpt_if = io_wakeup_ports_4_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_4_bits_uop_bp_xcpt_if = io_wakeup_ports_4_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_4_bits_uop_bp_xcpt_if = io_wakeup_ports_4_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_4_bits_uop_bp_xcpt_if = io_wakeup_ports_4_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_4_bits_uop_bp_xcpt_if = io_wakeup_ports_4_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_4_bits_uop_bp_xcpt_if = io_wakeup_ports_4_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_4_bits_uop_bp_xcpt_if = io_wakeup_ports_4_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_4_bits_uop_bp_xcpt_if = io_wakeup_ports_4_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_4_bits_uop_bp_xcpt_if = io_wakeup_ports_4_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_4_bits_uop_bp_xcpt_if = io_wakeup_ports_4_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_4_bits_uop_bp_xcpt_if = io_wakeup_ports_4_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_4_bits_uop_bp_xcpt_if = io_wakeup_ports_4_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_4_bits_uop_bp_xcpt_if = io_wakeup_ports_4_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_4_bits_uop_bp_xcpt_if = io_wakeup_ports_4_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_4_bits_uop_bp_xcpt_if = io_wakeup_ports_4_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_4_bits_uop_bp_xcpt_if = io_wakeup_ports_4_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_4_bits_uop_debug_fsrc = io_wakeup_ports_4_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_4_bits_uop_debug_fsrc = io_wakeup_ports_4_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_4_bits_uop_debug_fsrc = io_wakeup_ports_4_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_4_bits_uop_debug_fsrc = io_wakeup_ports_4_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_4_bits_uop_debug_fsrc = io_wakeup_ports_4_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_4_bits_uop_debug_fsrc = io_wakeup_ports_4_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_4_bits_uop_debug_fsrc = io_wakeup_ports_4_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_4_bits_uop_debug_fsrc = io_wakeup_ports_4_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_4_bits_uop_debug_fsrc = io_wakeup_ports_4_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_4_bits_uop_debug_fsrc = io_wakeup_ports_4_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_4_bits_uop_debug_fsrc = io_wakeup_ports_4_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_4_bits_uop_debug_fsrc = io_wakeup_ports_4_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_4_bits_uop_debug_fsrc = io_wakeup_ports_4_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_4_bits_uop_debug_fsrc = io_wakeup_ports_4_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_4_bits_uop_debug_fsrc = io_wakeup_ports_4_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_4_bits_uop_debug_fsrc = io_wakeup_ports_4_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_4_bits_uop_debug_tsrc = io_wakeup_ports_4_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_4_bits_uop_debug_tsrc = io_wakeup_ports_4_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_4_bits_uop_debug_tsrc = io_wakeup_ports_4_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_4_bits_uop_debug_tsrc = io_wakeup_ports_4_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_4_bits_uop_debug_tsrc = io_wakeup_ports_4_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_4_bits_uop_debug_tsrc = io_wakeup_ports_4_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_4_bits_uop_debug_tsrc = io_wakeup_ports_4_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_4_bits_uop_debug_tsrc = io_wakeup_ports_4_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_4_bits_uop_debug_tsrc = io_wakeup_ports_4_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_4_bits_uop_debug_tsrc = io_wakeup_ports_4_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_4_bits_uop_debug_tsrc = io_wakeup_ports_4_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_4_bits_uop_debug_tsrc = io_wakeup_ports_4_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_4_bits_uop_debug_tsrc = io_wakeup_ports_4_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_4_bits_uop_debug_tsrc = io_wakeup_ports_4_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_4_bits_uop_debug_tsrc = io_wakeup_ports_4_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_4_bits_uop_debug_tsrc = io_wakeup_ports_4_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_child_rebusys = io_child_rebusys_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_0_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_1_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_2_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_3_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_4_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_5_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_6_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_7_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_8_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_9_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_10_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_11_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_12_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_13_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_14_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_15_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_0_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_1_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_2_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_3_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_4_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_5_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_6_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_7_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_8_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_9_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_10_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_11_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_12_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_13_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_14_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_15_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_12_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_13_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_14_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_15_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_12_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_13_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_14_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_15_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_0_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_1_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_2_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_3_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_4_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_5_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_6_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_7_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_8_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_9_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_10_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_11_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_12_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_13_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_14_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_15_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_0_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_1_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_2_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_3_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_4_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_5_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_6_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_7_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_8_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_9_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_10_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_11_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_12_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_13_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_14_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_15_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_12_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_13_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_14_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_15_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_12_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_13_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_14_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_15_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_0_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_1_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_2_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_3_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_4_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_5_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_6_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_7_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_8_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_9_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_10_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_11_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_12_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_13_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_14_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_15_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_0_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_1_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_2_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_3_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_4_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_5_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_6_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_7_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_8_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_9_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_10_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_11_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_12_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_13_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_14_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_15_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_0_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_1_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_2_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_3_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_4_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_5_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_6_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_7_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_8_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_9_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_10_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_11_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_12_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_13_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_14_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_15_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_0_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_1_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_2_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_3_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_4_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_5_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_6_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_7_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_8_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_9_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_10_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_11_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_12_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_13_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_14_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_15_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire io_dis_uops_0_ready_0; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_ready_0; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_ready_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_iss_uops_0_bits_inst_0; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_iss_uops_0_bits_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_iss_uops_0_bits_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_iss_uops_0_bits_br_mask_0; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_iss_uops_0_bits_br_tag_0; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_iss_uops_0_bits_br_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_fence_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_amo_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_eret_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_mov_0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_iss_uops_0_bits_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_iss_uops_0_bits_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_taken_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_iss_uops_0_bits_pimm_0; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_iss_uops_0_bits_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_iss_uops_0_bits_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_iss_uops_0_bits_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_iss_uops_0_bits_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_iss_uops_0_bits_pdst_0; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_iss_uops_0_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_iss_uops_0_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_iss_uops_0_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_iss_uops_0_bits_ppred_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_iss_uops_0_bits_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_exception_0; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_iss_uops_0_bits_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_iss_uops_0_bits_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_mem_size_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_unique_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_iss_uops_0_bits_ldst_0; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_iss_uops_0_bits_lrs1_0; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_iss_uops_0_bits_lrs2_0; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_iss_uops_0_bits_lrs3_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_iss_uops_0_bits_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_val_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_valid_0; // @[issue-unit-age-ordered.scala:22:7] wire prs1_matches_0 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_0_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs1_matches_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_0_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs1_matches_2 = io_wakeup_ports_2_bits_uop_pdst_0 == io_dis_uops_0_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs1_matches_3 = io_wakeup_ports_3_bits_uop_pdst_0 == io_dis_uops_0_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs1_matches_4 = io_wakeup_ports_4_bits_uop_pdst_0 == io_dis_uops_0_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs2_matches_0 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_0_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs2_matches_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_0_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs2_matches_2 = io_wakeup_ports_2_bits_uop_pdst_0 == io_dis_uops_0_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs2_matches_3 = io_wakeup_ports_3_bits_uop_pdst_0 == io_dis_uops_0_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs2_matches_4 = io_wakeup_ports_4_bits_uop_pdst_0 == io_dis_uops_0_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs3_matches_0 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_0_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs3_matches_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_0_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs3_matches_2 = io_wakeup_ports_2_bits_uop_pdst_0 == io_dis_uops_0_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs3_matches_3 = io_wakeup_ports_3_bits_uop_pdst_0 == io_dis_uops_0_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs3_matches_4 = io_wakeup_ports_4_bits_uop_pdst_0 == io_dis_uops_0_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs1_wakeups_0 = io_wakeup_ports_0_valid_0 & prs1_matches_0; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs1_wakeups_1 = io_wakeup_ports_1_valid_0 & prs1_matches_1; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs1_wakeups_2 = io_wakeup_ports_2_valid_0 & prs1_matches_2; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs1_wakeups_3 = io_wakeup_ports_3_valid_0 & prs1_matches_3; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs1_wakeups_4 = io_wakeup_ports_4_valid_0 & prs1_matches_4; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs2_wakeups_0 = io_wakeup_ports_0_valid_0 & prs2_matches_0; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs2_wakeups_1 = io_wakeup_ports_1_valid_0 & prs2_matches_1; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs2_wakeups_2 = io_wakeup_ports_2_valid_0 & prs2_matches_2; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs2_wakeups_3 = io_wakeup_ports_3_valid_0 & prs2_matches_3; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs2_wakeups_4 = io_wakeup_ports_4_valid_0 & prs2_matches_4; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs3_wakeups_0 = io_wakeup_ports_0_valid_0 & prs3_matches_0; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs3_wakeups_1 = io_wakeup_ports_1_valid_0 & prs3_matches_1; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs3_wakeups_2 = io_wakeup_ports_2_valid_0 & prs3_matches_2; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs3_wakeups_3 = io_wakeup_ports_3_valid_0 & prs3_matches_3; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs3_wakeups_4 = io_wakeup_ports_4_valid_0 & prs3_matches_4; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs1_rebusys_0 = io_wakeup_ports_0_bits_rebusy_0 & prs1_matches_0; // @[issue-unit-age-ordered.scala:22:7, :44:69, :50:95] wire prs2_rebusys_0 = io_wakeup_ports_0_bits_rebusy_0 & prs2_matches_0; // @[issue-unit-age-ordered.scala:22:7, :45:69, :51:95] wire _T_3 = prs1_wakeups_0 | prs1_wakeups_1 | prs1_wakeups_2 | prs1_wakeups_3 | prs1_wakeups_4; // @[issue-unit-age-ordered.scala:47:89, :57:32] wire [2:0] _WIRE_iw_p1_speculative_child = _T_3 ? (prs1_wakeups_0 ? io_wakeup_ports_0_bits_speculative_mask_0 : 3'h0) | {prs1_wakeups_4, prs1_wakeups_3, prs1_wakeups_2} : io_dis_uops_0_bits_iw_p1_speculative_child_0; // @[Mux.scala:30:73] wire _WIRE_iw_p1_bypass_hint = _T_3 & (prs1_wakeups_0 & io_wakeup_ports_0_bits_bypassable_0 | prs1_wakeups_2 | prs1_wakeups_3 | prs1_wakeups_4); // @[Mux.scala:30:73] wire _WIRE_prs1_busy = (|{prs1_rebusys_0, io_child_rebusys_0 & io_dis_uops_0_bits_iw_p1_speculative_child_0}) ? io_dis_uops_0_bits_lrs1_rtype_0 == 2'h0 : ~_T_3 & io_dis_uops_0_bits_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :50:95, :57:{32,38}, :58:29, :62:{37,59,106,116}, :63:{29,63}] wire _T_33 = prs2_wakeups_0 | prs2_wakeups_1 | prs2_wakeups_2 | prs2_wakeups_3 | prs2_wakeups_4; // @[issue-unit-age-ordered.scala:48:89, :65:32] wire [2:0] _WIRE_iw_p2_speculative_child = _T_33 ? (prs2_wakeups_0 ? io_wakeup_ports_0_bits_speculative_mask_0 : 3'h0) | {prs2_wakeups_4, prs2_wakeups_3, prs2_wakeups_2} : io_dis_uops_0_bits_iw_p2_speculative_child_0; // @[Mux.scala:30:73] wire _WIRE_iw_p2_bypass_hint = _T_33 & (prs2_wakeups_0 & io_wakeup_ports_0_bits_bypassable_0 | prs2_wakeups_2 | prs2_wakeups_3 | prs2_wakeups_4); // @[Mux.scala:30:73] wire _WIRE_prs2_busy = (|{prs2_rebusys_0, io_child_rebusys_0 & io_dis_uops_0_bits_iw_p2_speculative_child_0}) ? io_dis_uops_0_bits_lrs2_rtype_0 == 2'h0 : ~_T_33 & io_dis_uops_0_bits_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :51:95, :65:{32,38}, :66:29, :71:{37,59,106,116}, :72:{29,63}] wire _T_63 = prs3_wakeups_0 | prs3_wakeups_1 | prs3_wakeups_2 | prs3_wakeups_3 | prs3_wakeups_4; // @[issue-unit-age-ordered.scala:49:89, :76:32] wire _WIRE_prs3_busy = ~_T_63 & io_dis_uops_0_bits_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :76:{32,38}, :77:29] wire _WIRE_iw_p3_bypass_hint = _T_63 & (prs3_wakeups_0 & io_wakeup_ports_0_bits_bypassable_0 | prs3_wakeups_2 | prs3_wakeups_3 | prs3_wakeups_4); // @[Mux.scala:30:73] wire [6:0] _WIRE_prs2 = io_dis_uops_0_bits_fu_code_8_0 ? {2'h0, io_dis_uops_0_bits_fp_rm_0, io_dis_uops_0_bits_fp_typ_0} : io_dis_uops_0_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :86:50, :87:26] wire [4:0] _WIRE_pimm = io_dis_uops_0_bits_is_sfence_0 ? {3'h0, io_dis_uops_0_bits_mem_size_0} : io_dis_uops_0_bits_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :89:44, :90:26] wire prs1_matches_0_1 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_1_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs1_matches_1_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_1_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs1_matches_2_1 = io_wakeup_ports_2_bits_uop_pdst_0 == io_dis_uops_1_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs1_matches_3_1 = io_wakeup_ports_3_bits_uop_pdst_0 == io_dis_uops_1_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs1_matches_4_1 = io_wakeup_ports_4_bits_uop_pdst_0 == io_dis_uops_1_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs2_matches_0_1 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_1_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs2_matches_1_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_1_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs2_matches_2_1 = io_wakeup_ports_2_bits_uop_pdst_0 == io_dis_uops_1_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs2_matches_3_1 = io_wakeup_ports_3_bits_uop_pdst_0 == io_dis_uops_1_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs2_matches_4_1 = io_wakeup_ports_4_bits_uop_pdst_0 == io_dis_uops_1_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs3_matches_0_1 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_1_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs3_matches_1_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_1_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs3_matches_2_1 = io_wakeup_ports_2_bits_uop_pdst_0 == io_dis_uops_1_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs3_matches_3_1 = io_wakeup_ports_3_bits_uop_pdst_0 == io_dis_uops_1_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs3_matches_4_1 = io_wakeup_ports_4_bits_uop_pdst_0 == io_dis_uops_1_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs1_wakeups_0_1 = io_wakeup_ports_0_valid_0 & prs1_matches_0_1; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs1_wakeups_1_1 = io_wakeup_ports_1_valid_0 & prs1_matches_1_1; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs1_wakeups_2_1 = io_wakeup_ports_2_valid_0 & prs1_matches_2_1; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs1_wakeups_3_1 = io_wakeup_ports_3_valid_0 & prs1_matches_3_1; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs1_wakeups_4_1 = io_wakeup_ports_4_valid_0 & prs1_matches_4_1; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs2_wakeups_0_1 = io_wakeup_ports_0_valid_0 & prs2_matches_0_1; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs2_wakeups_1_1 = io_wakeup_ports_1_valid_0 & prs2_matches_1_1; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs2_wakeups_2_1 = io_wakeup_ports_2_valid_0 & prs2_matches_2_1; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs2_wakeups_3_1 = io_wakeup_ports_3_valid_0 & prs2_matches_3_1; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs2_wakeups_4_1 = io_wakeup_ports_4_valid_0 & prs2_matches_4_1; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs3_wakeups_0_1 = io_wakeup_ports_0_valid_0 & prs3_matches_0_1; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs3_wakeups_1_1 = io_wakeup_ports_1_valid_0 & prs3_matches_1_1; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs3_wakeups_2_1 = io_wakeup_ports_2_valid_0 & prs3_matches_2_1; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs3_wakeups_3_1 = io_wakeup_ports_3_valid_0 & prs3_matches_3_1; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs3_wakeups_4_1 = io_wakeup_ports_4_valid_0 & prs3_matches_4_1; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs1_rebusys_0_1 = io_wakeup_ports_0_bits_rebusy_0 & prs1_matches_0_1; // @[issue-unit-age-ordered.scala:22:7, :44:69, :50:95] wire prs2_rebusys_0_1 = io_wakeup_ports_0_bits_rebusy_0 & prs2_matches_0_1; // @[issue-unit-age-ordered.scala:22:7, :45:69, :51:95] wire _T_84 = prs1_wakeups_0_1 | prs1_wakeups_1_1 | prs1_wakeups_2_1 | prs1_wakeups_3_1 | prs1_wakeups_4_1; // @[issue-unit-age-ordered.scala:47:89, :57:32] wire [2:0] _WIRE_1_iw_p1_speculative_child = _T_84 ? (prs1_wakeups_0_1 ? io_wakeup_ports_0_bits_speculative_mask_0 : 3'h0) | {prs1_wakeups_4_1, prs1_wakeups_3_1, prs1_wakeups_2_1} : io_dis_uops_1_bits_iw_p1_speculative_child_0; // @[Mux.scala:30:73] wire _WIRE_1_iw_p1_bypass_hint = _T_84 & (prs1_wakeups_0_1 & io_wakeup_ports_0_bits_bypassable_0 | prs1_wakeups_2_1 | prs1_wakeups_3_1 | prs1_wakeups_4_1); // @[Mux.scala:30:73] wire _WIRE_1_prs1_busy = (|{prs1_rebusys_0_1, io_child_rebusys_0 & io_dis_uops_1_bits_iw_p1_speculative_child_0}) ? io_dis_uops_1_bits_lrs1_rtype_0 == 2'h0 : ~_T_84 & io_dis_uops_1_bits_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :50:95, :57:{32,38}, :58:29, :62:{37,59,106,116}, :63:{29,63}] wire _T_114 = prs2_wakeups_0_1 | prs2_wakeups_1_1 | prs2_wakeups_2_1 | prs2_wakeups_3_1 | prs2_wakeups_4_1; // @[issue-unit-age-ordered.scala:48:89, :65:32] wire [2:0] _WIRE_1_iw_p2_speculative_child = _T_114 ? (prs2_wakeups_0_1 ? io_wakeup_ports_0_bits_speculative_mask_0 : 3'h0) | {prs2_wakeups_4_1, prs2_wakeups_3_1, prs2_wakeups_2_1} : io_dis_uops_1_bits_iw_p2_speculative_child_0; // @[Mux.scala:30:73] wire _WIRE_1_iw_p2_bypass_hint = _T_114 & (prs2_wakeups_0_1 & io_wakeup_ports_0_bits_bypassable_0 | prs2_wakeups_2_1 | prs2_wakeups_3_1 | prs2_wakeups_4_1); // @[Mux.scala:30:73] wire _WIRE_1_prs2_busy = (|{prs2_rebusys_0_1, io_child_rebusys_0 & io_dis_uops_1_bits_iw_p2_speculative_child_0}) ? io_dis_uops_1_bits_lrs2_rtype_0 == 2'h0 : ~_T_114 & io_dis_uops_1_bits_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :51:95, :65:{32,38}, :66:29, :71:{37,59,106,116}, :72:{29,63}] wire _T_144 = prs3_wakeups_0_1 | prs3_wakeups_1_1 | prs3_wakeups_2_1 | prs3_wakeups_3_1 | prs3_wakeups_4_1; // @[issue-unit-age-ordered.scala:49:89, :76:32] wire _WIRE_1_prs3_busy = ~_T_144 & io_dis_uops_1_bits_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :76:{32,38}, :77:29] wire _WIRE_1_iw_p3_bypass_hint = _T_144 & (prs3_wakeups_0_1 & io_wakeup_ports_0_bits_bypassable_0 | prs3_wakeups_2_1 | prs3_wakeups_3_1 | prs3_wakeups_4_1); // @[Mux.scala:30:73] wire [6:0] _WIRE_1_prs2 = io_dis_uops_1_bits_fu_code_8_0 ? {2'h0, io_dis_uops_1_bits_fp_rm_0, io_dis_uops_1_bits_fp_typ_0} : io_dis_uops_1_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :86:50, :87:26] wire [4:0] _WIRE_1_pimm = io_dis_uops_1_bits_is_sfence_0 ? {3'h0, io_dis_uops_1_bits_mem_size_0} : io_dis_uops_1_bits_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :89:44, :90:26] wire prs1_matches_0_2 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_2_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs1_matches_1_2 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_2_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs1_matches_2_2 = io_wakeup_ports_2_bits_uop_pdst_0 == io_dis_uops_2_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs1_matches_3_2 = io_wakeup_ports_3_bits_uop_pdst_0 == io_dis_uops_2_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs1_matches_4_2 = io_wakeup_ports_4_bits_uop_pdst_0 == io_dis_uops_2_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs2_matches_0_2 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_2_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs2_matches_1_2 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_2_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs2_matches_2_2 = io_wakeup_ports_2_bits_uop_pdst_0 == io_dis_uops_2_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs2_matches_3_2 = io_wakeup_ports_3_bits_uop_pdst_0 == io_dis_uops_2_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs2_matches_4_2 = io_wakeup_ports_4_bits_uop_pdst_0 == io_dis_uops_2_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs3_matches_0_2 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_2_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs3_matches_1_2 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_2_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs3_matches_2_2 = io_wakeup_ports_2_bits_uop_pdst_0 == io_dis_uops_2_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs3_matches_3_2 = io_wakeup_ports_3_bits_uop_pdst_0 == io_dis_uops_2_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs3_matches_4_2 = io_wakeup_ports_4_bits_uop_pdst_0 == io_dis_uops_2_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs1_wakeups_0_2 = io_wakeup_ports_0_valid_0 & prs1_matches_0_2; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs1_wakeups_1_2 = io_wakeup_ports_1_valid_0 & prs1_matches_1_2; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs1_wakeups_2_2 = io_wakeup_ports_2_valid_0 & prs1_matches_2_2; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs1_wakeups_3_2 = io_wakeup_ports_3_valid_0 & prs1_matches_3_2; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs1_wakeups_4_2 = io_wakeup_ports_4_valid_0 & prs1_matches_4_2; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs2_wakeups_0_2 = io_wakeup_ports_0_valid_0 & prs2_matches_0_2; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs2_wakeups_1_2 = io_wakeup_ports_1_valid_0 & prs2_matches_1_2; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs2_wakeups_2_2 = io_wakeup_ports_2_valid_0 & prs2_matches_2_2; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs2_wakeups_3_2 = io_wakeup_ports_3_valid_0 & prs2_matches_3_2; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs2_wakeups_4_2 = io_wakeup_ports_4_valid_0 & prs2_matches_4_2; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs3_wakeups_0_2 = io_wakeup_ports_0_valid_0 & prs3_matches_0_2; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs3_wakeups_1_2 = io_wakeup_ports_1_valid_0 & prs3_matches_1_2; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs3_wakeups_2_2 = io_wakeup_ports_2_valid_0 & prs3_matches_2_2; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs3_wakeups_3_2 = io_wakeup_ports_3_valid_0 & prs3_matches_3_2; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs3_wakeups_4_2 = io_wakeup_ports_4_valid_0 & prs3_matches_4_2; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs1_rebusys_0_2 = io_wakeup_ports_0_bits_rebusy_0 & prs1_matches_0_2; // @[issue-unit-age-ordered.scala:22:7, :44:69, :50:95] wire prs2_rebusys_0_2 = io_wakeup_ports_0_bits_rebusy_0 & prs2_matches_0_2; // @[issue-unit-age-ordered.scala:22:7, :45:69, :51:95] wire _T_165 = prs1_wakeups_0_2 | prs1_wakeups_1_2 | prs1_wakeups_2_2 | prs1_wakeups_3_2 | prs1_wakeups_4_2; // @[issue-unit-age-ordered.scala:47:89, :57:32] wire _T_195 = prs2_wakeups_0_2 | prs2_wakeups_1_2 | prs2_wakeups_2_2 | prs2_wakeups_3_2 | prs2_wakeups_4_2; // @[issue-unit-age-ordered.scala:48:89, :65:32] wire _T_225 = prs3_wakeups_0_2 | prs3_wakeups_1_2 | prs3_wakeups_2_2 | prs3_wakeups_3_2 | prs3_wakeups_4_2; // @[issue-unit-age-ordered.scala:49:89, :76:32] wire _fu_code_match_T_3 = issue_slots_0_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _fu_code_match_T_5 = issue_slots_0_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _fu_code_match_T_21 = issue_slots_1_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _fu_code_match_T_23 = issue_slots_1_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_1_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_39 = issue_slots_2_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _fu_code_match_T_41 = issue_slots_2_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_2_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_57 = issue_slots_3_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _fu_code_match_T_59 = issue_slots_3_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_3_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_75 = issue_slots_4_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _fu_code_match_T_77 = issue_slots_4_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_4_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_93 = issue_slots_5_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _fu_code_match_T_95 = issue_slots_5_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_5_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_111 = issue_slots_6_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _fu_code_match_T_113 = issue_slots_6_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_6_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_129 = issue_slots_7_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _fu_code_match_T_131 = issue_slots_7_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_7_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_147 = issue_slots_8_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _fu_code_match_T_149 = issue_slots_8_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_8_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_165 = issue_slots_9_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _fu_code_match_T_167 = issue_slots_9_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_9_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_183 = issue_slots_10_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _fu_code_match_T_185 = issue_slots_10_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_10_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_201 = issue_slots_11_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _fu_code_match_T_203 = issue_slots_11_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_11_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_219 = issue_slots_12_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _fu_code_match_T_221 = issue_slots_12_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_12_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_237 = issue_slots_13_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _fu_code_match_T_239 = issue_slots_13_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_13_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_255 = issue_slots_14_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _fu_code_match_T_257 = issue_slots_14_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_14_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_273 = issue_slots_15_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _fu_code_match_T_275 = issue_slots_15_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_15_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire issue_slots_0_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_0_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_0_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_0_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_0_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_0_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_0_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_0_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_0_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_0_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_0_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_0_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_0_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_0_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_0_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_0_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_0_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_0_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_0_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_1_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_1_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_1_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_1_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_1_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_1_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_1_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_1_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_1_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_1_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_1_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_1_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_1_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_1_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_1_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_1_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_1_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_1_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_2_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_2_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_2_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_2_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_2_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_2_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_2_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_2_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_2_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_2_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_2_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_2_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_2_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_2_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_2_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_2_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_2_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_2_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_3_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_3_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_3_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_3_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_3_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_3_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_3_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_3_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_3_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_3_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_3_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_3_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_3_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_3_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_3_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_3_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_3_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_3_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_4_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_4_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_4_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_4_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_4_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_4_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_4_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_4_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_4_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_4_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_4_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_4_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_4_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_4_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_4_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_4_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_4_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_4_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_5_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_5_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_5_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_5_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_5_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_5_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_5_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_5_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_5_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_5_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_5_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_5_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_5_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_5_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_5_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_5_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_5_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_5_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_6_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_6_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_6_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_6_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_6_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_6_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_6_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_6_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_6_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_6_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_6_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_6_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_6_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_6_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_6_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_6_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_6_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_6_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_7_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_7_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_7_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_7_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_7_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_7_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_7_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_7_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_7_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_7_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_7_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_7_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_7_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_7_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_7_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_7_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_7_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_7_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_8_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_8_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_8_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_8_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_8_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_8_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_8_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_8_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_8_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_8_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_8_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_8_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_8_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_8_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_8_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_8_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_8_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_8_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_9_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_9_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_9_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_9_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_9_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_9_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_9_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_9_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_9_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_9_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_9_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_9_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_9_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_9_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_9_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_9_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_9_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_9_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_10_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_10_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_10_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_10_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_10_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_10_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_10_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_10_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_10_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_10_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_10_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_10_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_10_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_10_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_10_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_10_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_10_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_10_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_11_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_11_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_11_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_11_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_11_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_11_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_11_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_11_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_11_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_11_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_11_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_11_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_11_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_11_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_11_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_11_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_11_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_11_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_12_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_12_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_12_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_12_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_12_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_12_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_12_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_12_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_12_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_12_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_12_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_12_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_12_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_12_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_12_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_12_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_12_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_12_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_12_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_12_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_12_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_12_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_12_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_12_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_13_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_13_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_13_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_13_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_13_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_13_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_13_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_13_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_13_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_13_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_13_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_13_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_13_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_13_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_13_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_13_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_13_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_13_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_13_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_13_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_13_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_13_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_13_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_13_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_14_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_14_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_14_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_14_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_14_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_14_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_14_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_14_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_14_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_14_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_14_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_14_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_14_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_14_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_14_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_14_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_14_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_14_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_14_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_14_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_14_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_14_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_14_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_14_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_15_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_15_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_15_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_15_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_15_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_15_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_15_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_15_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_15_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_15_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_15_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_15_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_15_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_15_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_15_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_15_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_15_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_15_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_15_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_15_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_15_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_15_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_15_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_15_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_clear; // @[issue-unit-age-ordered.scala:122:28] wire vacants_0 = ~issue_slots_0_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_1 = ~issue_slots_1_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_2 = ~issue_slots_2_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_3 = ~issue_slots_3_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_4 = ~issue_slots_4_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_5 = ~issue_slots_5_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_6 = ~issue_slots_6_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_7 = ~issue_slots_7_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_8 = ~issue_slots_8_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_9 = ~issue_slots_9_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_10 = ~issue_slots_10_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_11 = ~issue_slots_11_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_12 = ~issue_slots_12_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_13 = ~issue_slots_13_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_14 = ~issue_slots_14_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_15 = ~issue_slots_15_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_16 = ~io_dis_uops_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :157:82] wire vacants_17 = ~io_dis_uops_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :157:82] wire vacants_18 = ~io_dis_uops_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :157:82] wire [2:0] shamts_oh_8_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_9_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_10_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_11_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_12_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_13_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_14_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_15_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_16_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_17_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_18_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_1; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_2; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_3; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_4; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_5; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_6; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_7; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_8; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_9; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_10; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_11; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_12; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_13; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_14; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_15; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_16; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_17; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_18; // @[issue-unit-age-ordered.scala:158:23] assign shamts_oh_1 = {2'h0, vacants_0}; // @[issue-unit-age-ordered.scala:157:38, :158:23, :174:20] wire _GEN = vacants_0 | vacants_1; // @[issue-unit-age-ordered.scala:157:38, :174:47] wire _shamts_oh_2_T; // @[issue-unit-age-ordered.scala:174:47] assign _shamts_oh_2_T = _GEN; // @[issue-unit-age-ordered.scala:174:47] wire _shamts_oh_3_T; // @[issue-unit-age-ordered.scala:174:47] assign _shamts_oh_3_T = _GEN; // @[issue-unit-age-ordered.scala:174:47] assign shamts_oh_2 = {2'h0, _shamts_oh_2_T}; // @[issue-unit-age-ordered.scala:158:23, :174:{20,47}] wire _shamts_oh_3_T_1 = _shamts_oh_3_T | vacants_2; // @[issue-unit-age-ordered.scala:157:38, :174:47] assign shamts_oh_3 = {2'h0, _shamts_oh_3_T_1}; // @[issue-unit-age-ordered.scala:158:23, :174:{20,47}] wire [1:0] shamts_oh_4_next; // @[issue-unit-age-ordered.scala:161:21] wire _shamts_oh_4_T = ~(|shamts_oh_3); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_4_T_1 = _shamts_oh_4_T & vacants_3; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_4_T_2 = shamts_oh_3[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_4_T_3 = ~_shamts_oh_4_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_4_T_4 = _shamts_oh_4_T_3 & vacants_3; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_4_next_T = {shamts_oh_3, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_4_next = _shamts_oh_4_T_1 ? 2'h1 : _shamts_oh_4_T_4 ? _shamts_oh_4_next_T[1:0] : shamts_oh_3[1:0]; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_4 = {1'h0, shamts_oh_4_next}; // @[issue-unit-age-ordered.scala:158:23, :161:21, :176:20] wire [1:0] shamts_oh_5_next; // @[issue-unit-age-ordered.scala:161:21] wire _shamts_oh_5_T = ~(|shamts_oh_4); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_5_T_1 = _shamts_oh_5_T & vacants_4; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_5_T_2 = shamts_oh_4[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_5_T_3 = ~_shamts_oh_5_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_5_T_4 = _shamts_oh_5_T_3 & vacants_4; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_5_next_T = {shamts_oh_4, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_5_next = _shamts_oh_5_T_1 ? 2'h1 : _shamts_oh_5_T_4 ? _shamts_oh_5_next_T[1:0] : shamts_oh_4[1:0]; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_5 = {1'h0, shamts_oh_5_next}; // @[issue-unit-age-ordered.scala:158:23, :161:21, :176:20] wire [1:0] shamts_oh_6_next; // @[issue-unit-age-ordered.scala:161:21] wire _shamts_oh_6_T = ~(|shamts_oh_5); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_6_T_1 = _shamts_oh_6_T & vacants_5; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_6_T_2 = shamts_oh_5[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_6_T_3 = ~_shamts_oh_6_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_6_T_4 = _shamts_oh_6_T_3 & vacants_5; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_6_next_T = {shamts_oh_5, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_6_next = _shamts_oh_6_T_1 ? 2'h1 : _shamts_oh_6_T_4 ? _shamts_oh_6_next_T[1:0] : shamts_oh_5[1:0]; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_6 = {1'h0, shamts_oh_6_next}; // @[issue-unit-age-ordered.scala:158:23, :161:21, :176:20] wire [1:0] shamts_oh_7_next; // @[issue-unit-age-ordered.scala:161:21] wire _shamts_oh_7_T = ~(|shamts_oh_6); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_7_T_1 = _shamts_oh_7_T & vacants_6; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_7_T_2 = shamts_oh_6[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_7_T_3 = ~_shamts_oh_7_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_7_T_4 = _shamts_oh_7_T_3 & vacants_6; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_7_next_T = {shamts_oh_6, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_7_next = _shamts_oh_7_T_1 ? 2'h1 : _shamts_oh_7_T_4 ? _shamts_oh_7_next_T[1:0] : shamts_oh_6[1:0]; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_7 = {1'h0, shamts_oh_7_next}; // @[issue-unit-age-ordered.scala:158:23, :161:21, :176:20] assign shamts_oh_8 = shamts_oh_8_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_8_T = ~(|shamts_oh_7); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_8_T_1 = _shamts_oh_8_T & vacants_7; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_8_T_2 = shamts_oh_7[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_8_T_3 = ~_shamts_oh_8_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_8_T_4 = _shamts_oh_8_T_3 & vacants_7; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_8_next_T = {shamts_oh_7, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_8_next = _shamts_oh_8_T_1 ? 3'h1 : _shamts_oh_8_T_4 ? _shamts_oh_8_next_T[2:0] : shamts_oh_7; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_9 = shamts_oh_9_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_9_T = ~(|shamts_oh_8); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_9_T_1 = _shamts_oh_9_T & vacants_8; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_9_T_2 = shamts_oh_8[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_9_T_3 = ~_shamts_oh_9_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_9_T_4 = _shamts_oh_9_T_3 & vacants_8; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_9_next_T = {shamts_oh_8, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_9_next = _shamts_oh_9_T_1 ? 3'h1 : _shamts_oh_9_T_4 ? _shamts_oh_9_next_T[2:0] : shamts_oh_8; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_10 = shamts_oh_10_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_10_T = ~(|shamts_oh_9); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_10_T_1 = _shamts_oh_10_T & vacants_9; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_10_T_2 = shamts_oh_9[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_10_T_3 = ~_shamts_oh_10_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_10_T_4 = _shamts_oh_10_T_3 & vacants_9; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_10_next_T = {shamts_oh_9, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_10_next = _shamts_oh_10_T_1 ? 3'h1 : _shamts_oh_10_T_4 ? _shamts_oh_10_next_T[2:0] : shamts_oh_9; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_11 = shamts_oh_11_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_11_T = ~(|shamts_oh_10); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_11_T_1 = _shamts_oh_11_T & vacants_10; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_11_T_2 = shamts_oh_10[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_11_T_3 = ~_shamts_oh_11_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_11_T_4 = _shamts_oh_11_T_3 & vacants_10; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_11_next_T = {shamts_oh_10, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_11_next = _shamts_oh_11_T_1 ? 3'h1 : _shamts_oh_11_T_4 ? _shamts_oh_11_next_T[2:0] : shamts_oh_10; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_12 = shamts_oh_12_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_12_T = ~(|shamts_oh_11); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_12_T_1 = _shamts_oh_12_T & vacants_11; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_12_T_2 = shamts_oh_11[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_12_T_3 = ~_shamts_oh_12_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_12_T_4 = _shamts_oh_12_T_3 & vacants_11; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_12_next_T = {shamts_oh_11, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_12_next = _shamts_oh_12_T_1 ? 3'h1 : _shamts_oh_12_T_4 ? _shamts_oh_12_next_T[2:0] : shamts_oh_11; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_13 = shamts_oh_13_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_13_T = ~(|shamts_oh_12); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_13_T_1 = _shamts_oh_13_T & vacants_12; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_13_T_2 = shamts_oh_12[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_13_T_3 = ~_shamts_oh_13_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_13_T_4 = _shamts_oh_13_T_3 & vacants_12; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_13_next_T = {shamts_oh_12, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_13_next = _shamts_oh_13_T_1 ? 3'h1 : _shamts_oh_13_T_4 ? _shamts_oh_13_next_T[2:0] : shamts_oh_12; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_14 = shamts_oh_14_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_14_T = ~(|shamts_oh_13); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_14_T_1 = _shamts_oh_14_T & vacants_13; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_14_T_2 = shamts_oh_13[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_14_T_3 = ~_shamts_oh_14_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_14_T_4 = _shamts_oh_14_T_3 & vacants_13; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_14_next_T = {shamts_oh_13, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_14_next = _shamts_oh_14_T_1 ? 3'h1 : _shamts_oh_14_T_4 ? _shamts_oh_14_next_T[2:0] : shamts_oh_13; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_15 = shamts_oh_15_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_15_T = ~(|shamts_oh_14); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_15_T_1 = _shamts_oh_15_T & vacants_14; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_15_T_2 = shamts_oh_14[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_15_T_3 = ~_shamts_oh_15_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_15_T_4 = _shamts_oh_15_T_3 & vacants_14; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_15_next_T = {shamts_oh_14, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_15_next = _shamts_oh_15_T_1 ? 3'h1 : _shamts_oh_15_T_4 ? _shamts_oh_15_next_T[2:0] : shamts_oh_14; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_16 = shamts_oh_16_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_16_T = ~(|shamts_oh_15); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_16_T_1 = _shamts_oh_16_T & vacants_15; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_16_T_2 = shamts_oh_15[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_16_T_3 = ~_shamts_oh_16_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_16_T_4 = _shamts_oh_16_T_3 & vacants_15; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_16_next_T = {shamts_oh_15, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_16_next = _shamts_oh_16_T_1 ? 3'h1 : _shamts_oh_16_T_4 ? _shamts_oh_16_next_T[2:0] : shamts_oh_15; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_17 = shamts_oh_17_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_17_T = shamts_oh_16 == 3'h0; // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_17_T_1 = _shamts_oh_17_T & vacants_16; // @[issue-unit-age-ordered.scala:157:82, :163:{21,29}] wire _shamts_oh_17_T_2 = shamts_oh_16[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_17_T_3 = ~_shamts_oh_17_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_17_T_4 = _shamts_oh_17_T_3 & vacants_16; // @[issue-unit-age-ordered.scala:157:82, :165:{19,36}] wire [3:0] _shamts_oh_17_next_T = {shamts_oh_16, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_17_next = _shamts_oh_17_T_1 ? 3'h1 : _shamts_oh_17_T_4 ? _shamts_oh_17_next_T[2:0] : shamts_oh_16; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_18 = shamts_oh_18_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_18_T = shamts_oh_17 == 3'h0; // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_18_T_1 = _shamts_oh_18_T & vacants_17; // @[issue-unit-age-ordered.scala:157:82, :163:{21,29}] wire _shamts_oh_18_T_2 = shamts_oh_17[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_18_T_3 = ~_shamts_oh_18_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_18_T_4 = _shamts_oh_18_T_3 & vacants_17; // @[issue-unit-age-ordered.scala:157:82, :165:{19,36}] wire [3:0] _shamts_oh_18_next_T = {shamts_oh_17, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_18_next = _shamts_oh_18_T_1 ? 3'h1 : _shamts_oh_18_T_4 ? _shamts_oh_18_next_T[2:0] : shamts_oh_17; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] wire _will_be_valid_T = ~io_dis_uops_0_bits_exception_0; // @[issue-unit-age-ordered.scala:22:7, :185:57] wire _will_be_valid_T_1 = io_dis_uops_0_valid_0 & _will_be_valid_T; // @[issue-unit-age-ordered.scala:22:7, :184:77, :185:57] wire _will_be_valid_T_2 = ~io_dis_uops_0_bits_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :186:57] wire _will_be_valid_T_3 = _will_be_valid_T_1 & _will_be_valid_T_2; // @[issue-unit-age-ordered.scala:184:77, :185:80, :186:57] wire _will_be_valid_T_4 = ~io_dis_uops_0_bits_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :187:57] wire will_be_valid_16 = _will_be_valid_T_3 & _will_be_valid_T_4; // @[issue-unit-age-ordered.scala:185:80, :186:79, :187:57] wire _will_be_valid_T_5 = ~io_dis_uops_1_bits_exception_0; // @[issue-unit-age-ordered.scala:22:7, :185:57] wire _will_be_valid_T_6 = io_dis_uops_1_valid_0 & _will_be_valid_T_5; // @[issue-unit-age-ordered.scala:22:7, :184:77, :185:57] wire _will_be_valid_T_7 = ~io_dis_uops_1_bits_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :186:57] wire _will_be_valid_T_8 = _will_be_valid_T_6 & _will_be_valid_T_7; // @[issue-unit-age-ordered.scala:184:77, :185:80, :186:57] wire _will_be_valid_T_9 = ~io_dis_uops_1_bits_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :187:57] wire will_be_valid_17 = _will_be_valid_T_8 & _will_be_valid_T_9; // @[issue-unit-age-ordered.scala:185:80, :186:79, :187:57] wire _will_be_valid_T_10 = ~io_dis_uops_2_bits_exception_0; // @[issue-unit-age-ordered.scala:22:7, :185:57] wire _will_be_valid_T_11 = io_dis_uops_2_valid_0 & _will_be_valid_T_10; // @[issue-unit-age-ordered.scala:22:7, :184:77, :185:57] wire _will_be_valid_T_12 = ~io_dis_uops_2_bits_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :186:57] wire _will_be_valid_T_13 = _will_be_valid_T_11 & _will_be_valid_T_12; // @[issue-unit-age-ordered.scala:184:77, :185:80, :186:57] wire _will_be_valid_T_14 = ~io_dis_uops_2_bits_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :187:57] wire will_be_valid_18 = _will_be_valid_T_13 & _will_be_valid_T_14; // @[issue-unit-age-ordered.scala:185:80, :186:79, :187:57] wire _T_278 = shamts_oh_2 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_279 = shamts_oh_3 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_0_in_uop_valid = _T_279 ? issue_slots_3_will_be_valid : _T_278 ? issue_slots_2_will_be_valid : shamts_oh_1 == 3'h1 & issue_slots_1_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_0_in_uop_bits_debug_tsrc = _T_279 ? issue_slots_3_out_uop_debug_tsrc : _T_278 ? issue_slots_2_out_uop_debug_tsrc : issue_slots_1_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_debug_fsrc = _T_279 ? issue_slots_3_out_uop_debug_fsrc : _T_278 ? issue_slots_2_out_uop_debug_fsrc : issue_slots_1_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_bp_xcpt_if = _T_279 ? issue_slots_3_out_uop_bp_xcpt_if : _T_278 ? issue_slots_2_out_uop_bp_xcpt_if : issue_slots_1_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_bp_debug_if = _T_279 ? issue_slots_3_out_uop_bp_debug_if : _T_278 ? issue_slots_2_out_uop_bp_debug_if : issue_slots_1_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_xcpt_ma_if = _T_279 ? issue_slots_3_out_uop_xcpt_ma_if : _T_278 ? issue_slots_2_out_uop_xcpt_ma_if : issue_slots_1_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_xcpt_ae_if = _T_279 ? issue_slots_3_out_uop_xcpt_ae_if : _T_278 ? issue_slots_2_out_uop_xcpt_ae_if : issue_slots_1_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_xcpt_pf_if = _T_279 ? issue_slots_3_out_uop_xcpt_pf_if : _T_278 ? issue_slots_2_out_uop_xcpt_pf_if : issue_slots_1_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_typ = _T_279 ? issue_slots_3_out_uop_fp_typ : _T_278 ? issue_slots_2_out_uop_fp_typ : issue_slots_1_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_rm = _T_279 ? issue_slots_3_out_uop_fp_rm : _T_278 ? issue_slots_2_out_uop_fp_rm : issue_slots_1_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_val = _T_279 ? issue_slots_3_out_uop_fp_val : _T_278 ? issue_slots_2_out_uop_fp_val : issue_slots_1_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fcn_op = _T_279 ? issue_slots_3_out_uop_fcn_op : _T_278 ? issue_slots_2_out_uop_fcn_op : issue_slots_1_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fcn_dw = _T_279 ? issue_slots_3_out_uop_fcn_dw : _T_278 ? issue_slots_2_out_uop_fcn_dw : issue_slots_1_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_frs3_en = _T_279 ? issue_slots_3_out_uop_frs3_en : _T_278 ? issue_slots_2_out_uop_frs3_en : issue_slots_1_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_lrs2_rtype = _T_279 ? issue_slots_3_out_uop_lrs2_rtype : _T_278 ? issue_slots_2_out_uop_lrs2_rtype : issue_slots_1_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_lrs1_rtype = _T_279 ? issue_slots_3_out_uop_lrs1_rtype : _T_278 ? issue_slots_2_out_uop_lrs1_rtype : issue_slots_1_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_dst_rtype = _T_279 ? issue_slots_3_out_uop_dst_rtype : _T_278 ? issue_slots_2_out_uop_dst_rtype : issue_slots_1_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_lrs3 = _T_279 ? issue_slots_3_out_uop_lrs3 : _T_278 ? issue_slots_2_out_uop_lrs3 : issue_slots_1_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_lrs2 = _T_279 ? issue_slots_3_out_uop_lrs2 : _T_278 ? issue_slots_2_out_uop_lrs2 : issue_slots_1_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_lrs1 = _T_279 ? issue_slots_3_out_uop_lrs1 : _T_278 ? issue_slots_2_out_uop_lrs1 : issue_slots_1_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_ldst = _T_279 ? issue_slots_3_out_uop_ldst : _T_278 ? issue_slots_2_out_uop_ldst : issue_slots_1_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_ldst_is_rs1 = _T_279 ? issue_slots_3_out_uop_ldst_is_rs1 : _T_278 ? issue_slots_2_out_uop_ldst_is_rs1 : issue_slots_1_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_csr_cmd = _T_279 ? issue_slots_3_out_uop_csr_cmd : _T_278 ? issue_slots_2_out_uop_csr_cmd : issue_slots_1_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_flush_on_commit = _T_279 ? issue_slots_3_out_uop_flush_on_commit : _T_278 ? issue_slots_2_out_uop_flush_on_commit : issue_slots_1_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_unique = _T_279 ? issue_slots_3_out_uop_is_unique : _T_278 ? issue_slots_2_out_uop_is_unique : issue_slots_1_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_uses_stq = _T_279 ? issue_slots_3_out_uop_uses_stq : _T_278 ? issue_slots_2_out_uop_uses_stq : issue_slots_1_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_uses_ldq = _T_279 ? issue_slots_3_out_uop_uses_ldq : _T_278 ? issue_slots_2_out_uop_uses_ldq : issue_slots_1_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_mem_signed = _T_279 ? issue_slots_3_out_uop_mem_signed : _T_278 ? issue_slots_2_out_uop_mem_signed : issue_slots_1_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_mem_size = _T_279 ? issue_slots_3_out_uop_mem_size : _T_278 ? issue_slots_2_out_uop_mem_size : issue_slots_1_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_mem_cmd = _T_279 ? issue_slots_3_out_uop_mem_cmd : _T_278 ? issue_slots_2_out_uop_mem_cmd : issue_slots_1_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_exc_cause = _T_279 ? issue_slots_3_out_uop_exc_cause : _T_278 ? issue_slots_2_out_uop_exc_cause : issue_slots_1_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_exception = _T_279 ? issue_slots_3_out_uop_exception : _T_278 ? issue_slots_2_out_uop_exception : issue_slots_1_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_stale_pdst = _T_279 ? issue_slots_3_out_uop_stale_pdst : _T_278 ? issue_slots_2_out_uop_stale_pdst : issue_slots_1_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_ppred_busy = _T_279 ? issue_slots_3_out_uop_ppred_busy : _T_278 ? issue_slots_2_out_uop_ppred_busy : issue_slots_1_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_prs3_busy = _T_279 ? issue_slots_3_out_uop_prs3_busy : _T_278 ? issue_slots_2_out_uop_prs3_busy : issue_slots_1_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_prs2_busy = _T_279 ? issue_slots_3_out_uop_prs2_busy : _T_278 ? issue_slots_2_out_uop_prs2_busy : issue_slots_1_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_prs1_busy = _T_279 ? issue_slots_3_out_uop_prs1_busy : _T_278 ? issue_slots_2_out_uop_prs1_busy : issue_slots_1_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_ppred = _T_279 ? issue_slots_3_out_uop_ppred : _T_278 ? issue_slots_2_out_uop_ppred : issue_slots_1_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_prs3 = _T_279 ? issue_slots_3_out_uop_prs3 : _T_278 ? issue_slots_2_out_uop_prs3 : issue_slots_1_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_prs2 = _T_279 ? issue_slots_3_out_uop_prs2 : _T_278 ? issue_slots_2_out_uop_prs2 : issue_slots_1_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_prs1 = _T_279 ? issue_slots_3_out_uop_prs1 : _T_278 ? issue_slots_2_out_uop_prs1 : issue_slots_1_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_pdst = _T_279 ? issue_slots_3_out_uop_pdst : _T_278 ? issue_slots_2_out_uop_pdst : issue_slots_1_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_rxq_idx = _T_279 ? issue_slots_3_out_uop_rxq_idx : _T_278 ? issue_slots_2_out_uop_rxq_idx : issue_slots_1_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_stq_idx = _T_279 ? issue_slots_3_out_uop_stq_idx : _T_278 ? issue_slots_2_out_uop_stq_idx : issue_slots_1_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_ldq_idx = _T_279 ? issue_slots_3_out_uop_ldq_idx : _T_278 ? issue_slots_2_out_uop_ldq_idx : issue_slots_1_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_rob_idx = _T_279 ? issue_slots_3_out_uop_rob_idx : _T_278 ? issue_slots_2_out_uop_rob_idx : issue_slots_1_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_vec = _T_279 ? issue_slots_3_out_uop_fp_ctrl_vec : _T_278 ? issue_slots_2_out_uop_fp_ctrl_vec : issue_slots_1_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_wflags = _T_279 ? issue_slots_3_out_uop_fp_ctrl_wflags : _T_278 ? issue_slots_2_out_uop_fp_ctrl_wflags : issue_slots_1_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_sqrt = _T_279 ? issue_slots_3_out_uop_fp_ctrl_sqrt : _T_278 ? issue_slots_2_out_uop_fp_ctrl_sqrt : issue_slots_1_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_div = _T_279 ? issue_slots_3_out_uop_fp_ctrl_div : _T_278 ? issue_slots_2_out_uop_fp_ctrl_div : issue_slots_1_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_fma = _T_279 ? issue_slots_3_out_uop_fp_ctrl_fma : _T_278 ? issue_slots_2_out_uop_fp_ctrl_fma : issue_slots_1_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_fastpipe = _T_279 ? issue_slots_3_out_uop_fp_ctrl_fastpipe : _T_278 ? issue_slots_2_out_uop_fp_ctrl_fastpipe : issue_slots_1_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_toint = _T_279 ? issue_slots_3_out_uop_fp_ctrl_toint : _T_278 ? issue_slots_2_out_uop_fp_ctrl_toint : issue_slots_1_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_fromint = _T_279 ? issue_slots_3_out_uop_fp_ctrl_fromint : _T_278 ? issue_slots_2_out_uop_fp_ctrl_fromint : issue_slots_1_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_typeTagOut = _T_279 ? issue_slots_3_out_uop_fp_ctrl_typeTagOut : _T_278 ? issue_slots_2_out_uop_fp_ctrl_typeTagOut : issue_slots_1_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_typeTagIn = _T_279 ? issue_slots_3_out_uop_fp_ctrl_typeTagIn : _T_278 ? issue_slots_2_out_uop_fp_ctrl_typeTagIn : issue_slots_1_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_swap23 = _T_279 ? issue_slots_3_out_uop_fp_ctrl_swap23 : _T_278 ? issue_slots_2_out_uop_fp_ctrl_swap23 : issue_slots_1_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_swap12 = _T_279 ? issue_slots_3_out_uop_fp_ctrl_swap12 : _T_278 ? issue_slots_2_out_uop_fp_ctrl_swap12 : issue_slots_1_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_ren3 = _T_279 ? issue_slots_3_out_uop_fp_ctrl_ren3 : _T_278 ? issue_slots_2_out_uop_fp_ctrl_ren3 : issue_slots_1_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_ren2 = _T_279 ? issue_slots_3_out_uop_fp_ctrl_ren2 : _T_278 ? issue_slots_2_out_uop_fp_ctrl_ren2 : issue_slots_1_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_ren1 = _T_279 ? issue_slots_3_out_uop_fp_ctrl_ren1 : _T_278 ? issue_slots_2_out_uop_fp_ctrl_ren1 : issue_slots_1_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_wen = _T_279 ? issue_slots_3_out_uop_fp_ctrl_wen : _T_278 ? issue_slots_2_out_uop_fp_ctrl_wen : issue_slots_1_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_ldst = _T_279 ? issue_slots_3_out_uop_fp_ctrl_ldst : _T_278 ? issue_slots_2_out_uop_fp_ctrl_ldst : issue_slots_1_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_op2_sel = _T_279 ? issue_slots_3_out_uop_op2_sel : _T_278 ? issue_slots_2_out_uop_op2_sel : issue_slots_1_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_op1_sel = _T_279 ? issue_slots_3_out_uop_op1_sel : _T_278 ? issue_slots_2_out_uop_op1_sel : issue_slots_1_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_imm_packed = _T_279 ? issue_slots_3_out_uop_imm_packed : _T_278 ? issue_slots_2_out_uop_imm_packed : issue_slots_1_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_pimm = _T_279 ? issue_slots_3_out_uop_pimm : _T_278 ? issue_slots_2_out_uop_pimm : issue_slots_1_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_imm_sel = _T_279 ? issue_slots_3_out_uop_imm_sel : _T_278 ? issue_slots_2_out_uop_imm_sel : issue_slots_1_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_imm_rename = _T_279 ? issue_slots_3_out_uop_imm_rename : _T_278 ? issue_slots_2_out_uop_imm_rename : issue_slots_1_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_taken = _T_279 ? issue_slots_3_out_uop_taken : _T_278 ? issue_slots_2_out_uop_taken : issue_slots_1_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_pc_lob = _T_279 ? issue_slots_3_out_uop_pc_lob : _T_278 ? issue_slots_2_out_uop_pc_lob : issue_slots_1_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_edge_inst = _T_279 ? issue_slots_3_out_uop_edge_inst : _T_278 ? issue_slots_2_out_uop_edge_inst : issue_slots_1_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_ftq_idx = _T_279 ? issue_slots_3_out_uop_ftq_idx : _T_278 ? issue_slots_2_out_uop_ftq_idx : issue_slots_1_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_mov = _T_279 ? issue_slots_3_out_uop_is_mov : _T_278 ? issue_slots_2_out_uop_is_mov : issue_slots_1_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_rocc = _T_279 ? issue_slots_3_out_uop_is_rocc : _T_278 ? issue_slots_2_out_uop_is_rocc : issue_slots_1_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_sys_pc2epc = _T_279 ? issue_slots_3_out_uop_is_sys_pc2epc : _T_278 ? issue_slots_2_out_uop_is_sys_pc2epc : issue_slots_1_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_eret = _T_279 ? issue_slots_3_out_uop_is_eret : _T_278 ? issue_slots_2_out_uop_is_eret : issue_slots_1_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_amo = _T_279 ? issue_slots_3_out_uop_is_amo : _T_278 ? issue_slots_2_out_uop_is_amo : issue_slots_1_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_sfence = _T_279 ? issue_slots_3_out_uop_is_sfence : _T_278 ? issue_slots_2_out_uop_is_sfence : issue_slots_1_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_fencei = _T_279 ? issue_slots_3_out_uop_is_fencei : _T_278 ? issue_slots_2_out_uop_is_fencei : issue_slots_1_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_fence = _T_279 ? issue_slots_3_out_uop_is_fence : _T_278 ? issue_slots_2_out_uop_is_fence : issue_slots_1_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_sfb = _T_279 ? issue_slots_3_out_uop_is_sfb : _T_278 ? issue_slots_2_out_uop_is_sfb : issue_slots_1_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_br_type = _T_279 ? issue_slots_3_out_uop_br_type : _T_278 ? issue_slots_2_out_uop_br_type : issue_slots_1_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_br_tag = _T_279 ? issue_slots_3_out_uop_br_tag : _T_278 ? issue_slots_2_out_uop_br_tag : issue_slots_1_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_br_mask = _T_279 ? issue_slots_3_out_uop_br_mask : _T_278 ? issue_slots_2_out_uop_br_mask : issue_slots_1_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_dis_col_sel = _T_279 ? issue_slots_3_out_uop_dis_col_sel : _T_278 ? issue_slots_2_out_uop_dis_col_sel : issue_slots_1_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iw_p3_bypass_hint = _T_279 ? issue_slots_3_out_uop_iw_p3_bypass_hint : _T_278 ? issue_slots_2_out_uop_iw_p3_bypass_hint : issue_slots_1_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iw_p2_bypass_hint = _T_279 ? issue_slots_3_out_uop_iw_p2_bypass_hint : _T_278 ? issue_slots_2_out_uop_iw_p2_bypass_hint : issue_slots_1_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iw_p1_bypass_hint = _T_279 ? issue_slots_3_out_uop_iw_p1_bypass_hint : _T_278 ? issue_slots_2_out_uop_iw_p1_bypass_hint : issue_slots_1_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iw_p2_speculative_child = _T_279 ? issue_slots_3_out_uop_iw_p2_speculative_child : _T_278 ? issue_slots_2_out_uop_iw_p2_speculative_child : issue_slots_1_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iw_p1_speculative_child = _T_279 ? issue_slots_3_out_uop_iw_p1_speculative_child : _T_278 ? issue_slots_2_out_uop_iw_p1_speculative_child : issue_slots_1_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iw_issued = _T_279 ? issue_slots_3_out_uop_iw_issued : _T_278 ? issue_slots_2_out_uop_iw_issued : issue_slots_1_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_0 = _T_279 ? issue_slots_3_out_uop_fu_code_0 : _T_278 ? issue_slots_2_out_uop_fu_code_0 : issue_slots_1_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_1 = _T_279 ? issue_slots_3_out_uop_fu_code_1 : _T_278 ? issue_slots_2_out_uop_fu_code_1 : issue_slots_1_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_2 = _T_279 ? issue_slots_3_out_uop_fu_code_2 : _T_278 ? issue_slots_2_out_uop_fu_code_2 : issue_slots_1_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_3 = _T_279 ? issue_slots_3_out_uop_fu_code_3 : _T_278 ? issue_slots_2_out_uop_fu_code_3 : issue_slots_1_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_4 = _T_279 ? issue_slots_3_out_uop_fu_code_4 : _T_278 ? issue_slots_2_out_uop_fu_code_4 : issue_slots_1_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_5 = _T_279 ? issue_slots_3_out_uop_fu_code_5 : _T_278 ? issue_slots_2_out_uop_fu_code_5 : issue_slots_1_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_6 = _T_279 ? issue_slots_3_out_uop_fu_code_6 : _T_278 ? issue_slots_2_out_uop_fu_code_6 : issue_slots_1_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_7 = _T_279 ? issue_slots_3_out_uop_fu_code_7 : _T_278 ? issue_slots_2_out_uop_fu_code_7 : issue_slots_1_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_8 = _T_279 ? issue_slots_3_out_uop_fu_code_8 : _T_278 ? issue_slots_2_out_uop_fu_code_8 : issue_slots_1_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_9 = _T_279 ? issue_slots_3_out_uop_fu_code_9 : _T_278 ? issue_slots_2_out_uop_fu_code_9 : issue_slots_1_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iq_type_0 = _T_279 ? issue_slots_3_out_uop_iq_type_0 : _T_278 ? issue_slots_2_out_uop_iq_type_0 : issue_slots_1_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iq_type_1 = _T_279 ? issue_slots_3_out_uop_iq_type_1 : _T_278 ? issue_slots_2_out_uop_iq_type_1 : issue_slots_1_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iq_type_2 = _T_279 ? issue_slots_3_out_uop_iq_type_2 : _T_278 ? issue_slots_2_out_uop_iq_type_2 : issue_slots_1_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iq_type_3 = _T_279 ? issue_slots_3_out_uop_iq_type_3 : _T_278 ? issue_slots_2_out_uop_iq_type_3 : issue_slots_1_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_debug_pc = _T_279 ? issue_slots_3_out_uop_debug_pc : _T_278 ? issue_slots_2_out_uop_debug_pc : issue_slots_1_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_rvc = _T_279 ? issue_slots_3_out_uop_is_rvc : _T_278 ? issue_slots_2_out_uop_is_rvc : issue_slots_1_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_debug_inst = _T_279 ? issue_slots_3_out_uop_debug_inst : _T_278 ? issue_slots_2_out_uop_debug_inst : issue_slots_1_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_inst = _T_279 ? issue_slots_3_out_uop_inst : _T_278 ? issue_slots_2_out_uop_inst : issue_slots_1_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] wire _T_281 = shamts_oh_3 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_282 = shamts_oh_4 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_1_in_uop_valid = _T_282 ? issue_slots_4_will_be_valid : _T_281 ? issue_slots_3_will_be_valid : shamts_oh_2 == 3'h1 & issue_slots_2_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_1_in_uop_bits_debug_tsrc = _T_282 ? issue_slots_4_out_uop_debug_tsrc : _T_281 ? issue_slots_3_out_uop_debug_tsrc : issue_slots_2_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_debug_fsrc = _T_282 ? issue_slots_4_out_uop_debug_fsrc : _T_281 ? issue_slots_3_out_uop_debug_fsrc : issue_slots_2_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_bp_xcpt_if = _T_282 ? issue_slots_4_out_uop_bp_xcpt_if : _T_281 ? issue_slots_3_out_uop_bp_xcpt_if : issue_slots_2_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_bp_debug_if = _T_282 ? issue_slots_4_out_uop_bp_debug_if : _T_281 ? issue_slots_3_out_uop_bp_debug_if : issue_slots_2_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_xcpt_ma_if = _T_282 ? issue_slots_4_out_uop_xcpt_ma_if : _T_281 ? issue_slots_3_out_uop_xcpt_ma_if : issue_slots_2_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_xcpt_ae_if = _T_282 ? issue_slots_4_out_uop_xcpt_ae_if : _T_281 ? issue_slots_3_out_uop_xcpt_ae_if : issue_slots_2_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_xcpt_pf_if = _T_282 ? issue_slots_4_out_uop_xcpt_pf_if : _T_281 ? issue_slots_3_out_uop_xcpt_pf_if : issue_slots_2_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_typ = _T_282 ? issue_slots_4_out_uop_fp_typ : _T_281 ? issue_slots_3_out_uop_fp_typ : issue_slots_2_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_rm = _T_282 ? issue_slots_4_out_uop_fp_rm : _T_281 ? issue_slots_3_out_uop_fp_rm : issue_slots_2_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_val = _T_282 ? issue_slots_4_out_uop_fp_val : _T_281 ? issue_slots_3_out_uop_fp_val : issue_slots_2_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fcn_op = _T_282 ? issue_slots_4_out_uop_fcn_op : _T_281 ? issue_slots_3_out_uop_fcn_op : issue_slots_2_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fcn_dw = _T_282 ? issue_slots_4_out_uop_fcn_dw : _T_281 ? issue_slots_3_out_uop_fcn_dw : issue_slots_2_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_frs3_en = _T_282 ? issue_slots_4_out_uop_frs3_en : _T_281 ? issue_slots_3_out_uop_frs3_en : issue_slots_2_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_lrs2_rtype = _T_282 ? issue_slots_4_out_uop_lrs2_rtype : _T_281 ? issue_slots_3_out_uop_lrs2_rtype : issue_slots_2_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_lrs1_rtype = _T_282 ? issue_slots_4_out_uop_lrs1_rtype : _T_281 ? issue_slots_3_out_uop_lrs1_rtype : issue_slots_2_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_dst_rtype = _T_282 ? issue_slots_4_out_uop_dst_rtype : _T_281 ? issue_slots_3_out_uop_dst_rtype : issue_slots_2_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_lrs3 = _T_282 ? issue_slots_4_out_uop_lrs3 : _T_281 ? issue_slots_3_out_uop_lrs3 : issue_slots_2_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_lrs2 = _T_282 ? issue_slots_4_out_uop_lrs2 : _T_281 ? issue_slots_3_out_uop_lrs2 : issue_slots_2_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_lrs1 = _T_282 ? issue_slots_4_out_uop_lrs1 : _T_281 ? issue_slots_3_out_uop_lrs1 : issue_slots_2_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_ldst = _T_282 ? issue_slots_4_out_uop_ldst : _T_281 ? issue_slots_3_out_uop_ldst : issue_slots_2_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_ldst_is_rs1 = _T_282 ? issue_slots_4_out_uop_ldst_is_rs1 : _T_281 ? issue_slots_3_out_uop_ldst_is_rs1 : issue_slots_2_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_csr_cmd = _T_282 ? issue_slots_4_out_uop_csr_cmd : _T_281 ? issue_slots_3_out_uop_csr_cmd : issue_slots_2_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_flush_on_commit = _T_282 ? issue_slots_4_out_uop_flush_on_commit : _T_281 ? issue_slots_3_out_uop_flush_on_commit : issue_slots_2_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_unique = _T_282 ? issue_slots_4_out_uop_is_unique : _T_281 ? issue_slots_3_out_uop_is_unique : issue_slots_2_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_uses_stq = _T_282 ? issue_slots_4_out_uop_uses_stq : _T_281 ? issue_slots_3_out_uop_uses_stq : issue_slots_2_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_uses_ldq = _T_282 ? issue_slots_4_out_uop_uses_ldq : _T_281 ? issue_slots_3_out_uop_uses_ldq : issue_slots_2_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_mem_signed = _T_282 ? issue_slots_4_out_uop_mem_signed : _T_281 ? issue_slots_3_out_uop_mem_signed : issue_slots_2_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_mem_size = _T_282 ? issue_slots_4_out_uop_mem_size : _T_281 ? issue_slots_3_out_uop_mem_size : issue_slots_2_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_mem_cmd = _T_282 ? issue_slots_4_out_uop_mem_cmd : _T_281 ? issue_slots_3_out_uop_mem_cmd : issue_slots_2_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_exc_cause = _T_282 ? issue_slots_4_out_uop_exc_cause : _T_281 ? issue_slots_3_out_uop_exc_cause : issue_slots_2_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_exception = _T_282 ? issue_slots_4_out_uop_exception : _T_281 ? issue_slots_3_out_uop_exception : issue_slots_2_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_stale_pdst = _T_282 ? issue_slots_4_out_uop_stale_pdst : _T_281 ? issue_slots_3_out_uop_stale_pdst : issue_slots_2_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_ppred_busy = _T_282 ? issue_slots_4_out_uop_ppred_busy : _T_281 ? issue_slots_3_out_uop_ppred_busy : issue_slots_2_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_prs3_busy = _T_282 ? issue_slots_4_out_uop_prs3_busy : _T_281 ? issue_slots_3_out_uop_prs3_busy : issue_slots_2_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_prs2_busy = _T_282 ? issue_slots_4_out_uop_prs2_busy : _T_281 ? issue_slots_3_out_uop_prs2_busy : issue_slots_2_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_prs1_busy = _T_282 ? issue_slots_4_out_uop_prs1_busy : _T_281 ? issue_slots_3_out_uop_prs1_busy : issue_slots_2_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_ppred = _T_282 ? issue_slots_4_out_uop_ppred : _T_281 ? issue_slots_3_out_uop_ppred : issue_slots_2_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_prs3 = _T_282 ? issue_slots_4_out_uop_prs3 : _T_281 ? issue_slots_3_out_uop_prs3 : issue_slots_2_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_prs2 = _T_282 ? issue_slots_4_out_uop_prs2 : _T_281 ? issue_slots_3_out_uop_prs2 : issue_slots_2_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_prs1 = _T_282 ? issue_slots_4_out_uop_prs1 : _T_281 ? issue_slots_3_out_uop_prs1 : issue_slots_2_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_pdst = _T_282 ? issue_slots_4_out_uop_pdst : _T_281 ? issue_slots_3_out_uop_pdst : issue_slots_2_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_rxq_idx = _T_282 ? issue_slots_4_out_uop_rxq_idx : _T_281 ? issue_slots_3_out_uop_rxq_idx : issue_slots_2_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_stq_idx = _T_282 ? issue_slots_4_out_uop_stq_idx : _T_281 ? issue_slots_3_out_uop_stq_idx : issue_slots_2_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_ldq_idx = _T_282 ? issue_slots_4_out_uop_ldq_idx : _T_281 ? issue_slots_3_out_uop_ldq_idx : issue_slots_2_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_rob_idx = _T_282 ? issue_slots_4_out_uop_rob_idx : _T_281 ? issue_slots_3_out_uop_rob_idx : issue_slots_2_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_vec = _T_282 ? issue_slots_4_out_uop_fp_ctrl_vec : _T_281 ? issue_slots_3_out_uop_fp_ctrl_vec : issue_slots_2_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_wflags = _T_282 ? issue_slots_4_out_uop_fp_ctrl_wflags : _T_281 ? issue_slots_3_out_uop_fp_ctrl_wflags : issue_slots_2_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_sqrt = _T_282 ? issue_slots_4_out_uop_fp_ctrl_sqrt : _T_281 ? issue_slots_3_out_uop_fp_ctrl_sqrt : issue_slots_2_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_div = _T_282 ? issue_slots_4_out_uop_fp_ctrl_div : _T_281 ? issue_slots_3_out_uop_fp_ctrl_div : issue_slots_2_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_fma = _T_282 ? issue_slots_4_out_uop_fp_ctrl_fma : _T_281 ? issue_slots_3_out_uop_fp_ctrl_fma : issue_slots_2_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_fastpipe = _T_282 ? issue_slots_4_out_uop_fp_ctrl_fastpipe : _T_281 ? issue_slots_3_out_uop_fp_ctrl_fastpipe : issue_slots_2_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_toint = _T_282 ? issue_slots_4_out_uop_fp_ctrl_toint : _T_281 ? issue_slots_3_out_uop_fp_ctrl_toint : issue_slots_2_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_fromint = _T_282 ? issue_slots_4_out_uop_fp_ctrl_fromint : _T_281 ? issue_slots_3_out_uop_fp_ctrl_fromint : issue_slots_2_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_typeTagOut = _T_282 ? issue_slots_4_out_uop_fp_ctrl_typeTagOut : _T_281 ? issue_slots_3_out_uop_fp_ctrl_typeTagOut : issue_slots_2_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_typeTagIn = _T_282 ? issue_slots_4_out_uop_fp_ctrl_typeTagIn : _T_281 ? issue_slots_3_out_uop_fp_ctrl_typeTagIn : issue_slots_2_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_swap23 = _T_282 ? issue_slots_4_out_uop_fp_ctrl_swap23 : _T_281 ? issue_slots_3_out_uop_fp_ctrl_swap23 : issue_slots_2_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_swap12 = _T_282 ? issue_slots_4_out_uop_fp_ctrl_swap12 : _T_281 ? issue_slots_3_out_uop_fp_ctrl_swap12 : issue_slots_2_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_ren3 = _T_282 ? issue_slots_4_out_uop_fp_ctrl_ren3 : _T_281 ? issue_slots_3_out_uop_fp_ctrl_ren3 : issue_slots_2_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_ren2 = _T_282 ? issue_slots_4_out_uop_fp_ctrl_ren2 : _T_281 ? issue_slots_3_out_uop_fp_ctrl_ren2 : issue_slots_2_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_ren1 = _T_282 ? issue_slots_4_out_uop_fp_ctrl_ren1 : _T_281 ? issue_slots_3_out_uop_fp_ctrl_ren1 : issue_slots_2_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_wen = _T_282 ? issue_slots_4_out_uop_fp_ctrl_wen : _T_281 ? issue_slots_3_out_uop_fp_ctrl_wen : issue_slots_2_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_ldst = _T_282 ? issue_slots_4_out_uop_fp_ctrl_ldst : _T_281 ? issue_slots_3_out_uop_fp_ctrl_ldst : issue_slots_2_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_op2_sel = _T_282 ? issue_slots_4_out_uop_op2_sel : _T_281 ? issue_slots_3_out_uop_op2_sel : issue_slots_2_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_op1_sel = _T_282 ? issue_slots_4_out_uop_op1_sel : _T_281 ? issue_slots_3_out_uop_op1_sel : issue_slots_2_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_imm_packed = _T_282 ? issue_slots_4_out_uop_imm_packed : _T_281 ? issue_slots_3_out_uop_imm_packed : issue_slots_2_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_pimm = _T_282 ? issue_slots_4_out_uop_pimm : _T_281 ? issue_slots_3_out_uop_pimm : issue_slots_2_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_imm_sel = _T_282 ? issue_slots_4_out_uop_imm_sel : _T_281 ? issue_slots_3_out_uop_imm_sel : issue_slots_2_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_imm_rename = _T_282 ? issue_slots_4_out_uop_imm_rename : _T_281 ? issue_slots_3_out_uop_imm_rename : issue_slots_2_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_taken = _T_282 ? issue_slots_4_out_uop_taken : _T_281 ? issue_slots_3_out_uop_taken : issue_slots_2_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_pc_lob = _T_282 ? issue_slots_4_out_uop_pc_lob : _T_281 ? issue_slots_3_out_uop_pc_lob : issue_slots_2_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_edge_inst = _T_282 ? issue_slots_4_out_uop_edge_inst : _T_281 ? issue_slots_3_out_uop_edge_inst : issue_slots_2_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_ftq_idx = _T_282 ? issue_slots_4_out_uop_ftq_idx : _T_281 ? issue_slots_3_out_uop_ftq_idx : issue_slots_2_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_mov = _T_282 ? issue_slots_4_out_uop_is_mov : _T_281 ? issue_slots_3_out_uop_is_mov : issue_slots_2_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_rocc = _T_282 ? issue_slots_4_out_uop_is_rocc : _T_281 ? issue_slots_3_out_uop_is_rocc : issue_slots_2_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_sys_pc2epc = _T_282 ? issue_slots_4_out_uop_is_sys_pc2epc : _T_281 ? issue_slots_3_out_uop_is_sys_pc2epc : issue_slots_2_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_eret = _T_282 ? issue_slots_4_out_uop_is_eret : _T_281 ? issue_slots_3_out_uop_is_eret : issue_slots_2_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_amo = _T_282 ? issue_slots_4_out_uop_is_amo : _T_281 ? issue_slots_3_out_uop_is_amo : issue_slots_2_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_sfence = _T_282 ? issue_slots_4_out_uop_is_sfence : _T_281 ? issue_slots_3_out_uop_is_sfence : issue_slots_2_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_fencei = _T_282 ? issue_slots_4_out_uop_is_fencei : _T_281 ? issue_slots_3_out_uop_is_fencei : issue_slots_2_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_fence = _T_282 ? issue_slots_4_out_uop_is_fence : _T_281 ? issue_slots_3_out_uop_is_fence : issue_slots_2_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_sfb = _T_282 ? issue_slots_4_out_uop_is_sfb : _T_281 ? issue_slots_3_out_uop_is_sfb : issue_slots_2_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_br_type = _T_282 ? issue_slots_4_out_uop_br_type : _T_281 ? issue_slots_3_out_uop_br_type : issue_slots_2_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_br_tag = _T_282 ? issue_slots_4_out_uop_br_tag : _T_281 ? issue_slots_3_out_uop_br_tag : issue_slots_2_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_br_mask = _T_282 ? issue_slots_4_out_uop_br_mask : _T_281 ? issue_slots_3_out_uop_br_mask : issue_slots_2_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_dis_col_sel = _T_282 ? issue_slots_4_out_uop_dis_col_sel : _T_281 ? issue_slots_3_out_uop_dis_col_sel : issue_slots_2_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iw_p3_bypass_hint = _T_282 ? issue_slots_4_out_uop_iw_p3_bypass_hint : _T_281 ? issue_slots_3_out_uop_iw_p3_bypass_hint : issue_slots_2_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iw_p2_bypass_hint = _T_282 ? issue_slots_4_out_uop_iw_p2_bypass_hint : _T_281 ? issue_slots_3_out_uop_iw_p2_bypass_hint : issue_slots_2_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iw_p1_bypass_hint = _T_282 ? issue_slots_4_out_uop_iw_p1_bypass_hint : _T_281 ? issue_slots_3_out_uop_iw_p1_bypass_hint : issue_slots_2_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iw_p2_speculative_child = _T_282 ? issue_slots_4_out_uop_iw_p2_speculative_child : _T_281 ? issue_slots_3_out_uop_iw_p2_speculative_child : issue_slots_2_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iw_p1_speculative_child = _T_282 ? issue_slots_4_out_uop_iw_p1_speculative_child : _T_281 ? issue_slots_3_out_uop_iw_p1_speculative_child : issue_slots_2_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iw_issued = _T_282 ? issue_slots_4_out_uop_iw_issued : _T_281 ? issue_slots_3_out_uop_iw_issued : issue_slots_2_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_0 = _T_282 ? issue_slots_4_out_uop_fu_code_0 : _T_281 ? issue_slots_3_out_uop_fu_code_0 : issue_slots_2_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_1 = _T_282 ? issue_slots_4_out_uop_fu_code_1 : _T_281 ? issue_slots_3_out_uop_fu_code_1 : issue_slots_2_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_2 = _T_282 ? issue_slots_4_out_uop_fu_code_2 : _T_281 ? issue_slots_3_out_uop_fu_code_2 : issue_slots_2_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_3 = _T_282 ? issue_slots_4_out_uop_fu_code_3 : _T_281 ? issue_slots_3_out_uop_fu_code_3 : issue_slots_2_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_4 = _T_282 ? issue_slots_4_out_uop_fu_code_4 : _T_281 ? issue_slots_3_out_uop_fu_code_4 : issue_slots_2_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_5 = _T_282 ? issue_slots_4_out_uop_fu_code_5 : _T_281 ? issue_slots_3_out_uop_fu_code_5 : issue_slots_2_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_6 = _T_282 ? issue_slots_4_out_uop_fu_code_6 : _T_281 ? issue_slots_3_out_uop_fu_code_6 : issue_slots_2_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_7 = _T_282 ? issue_slots_4_out_uop_fu_code_7 : _T_281 ? issue_slots_3_out_uop_fu_code_7 : issue_slots_2_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_8 = _T_282 ? issue_slots_4_out_uop_fu_code_8 : _T_281 ? issue_slots_3_out_uop_fu_code_8 : issue_slots_2_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_9 = _T_282 ? issue_slots_4_out_uop_fu_code_9 : _T_281 ? issue_slots_3_out_uop_fu_code_9 : issue_slots_2_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iq_type_0 = _T_282 ? issue_slots_4_out_uop_iq_type_0 : _T_281 ? issue_slots_3_out_uop_iq_type_0 : issue_slots_2_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iq_type_1 = _T_282 ? issue_slots_4_out_uop_iq_type_1 : _T_281 ? issue_slots_3_out_uop_iq_type_1 : issue_slots_2_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iq_type_2 = _T_282 ? issue_slots_4_out_uop_iq_type_2 : _T_281 ? issue_slots_3_out_uop_iq_type_2 : issue_slots_2_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iq_type_3 = _T_282 ? issue_slots_4_out_uop_iq_type_3 : _T_281 ? issue_slots_3_out_uop_iq_type_3 : issue_slots_2_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_debug_pc = _T_282 ? issue_slots_4_out_uop_debug_pc : _T_281 ? issue_slots_3_out_uop_debug_pc : issue_slots_2_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_rvc = _T_282 ? issue_slots_4_out_uop_is_rvc : _T_281 ? issue_slots_3_out_uop_is_rvc : issue_slots_2_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_debug_inst = _T_282 ? issue_slots_4_out_uop_debug_inst : _T_281 ? issue_slots_3_out_uop_debug_inst : issue_slots_2_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_inst = _T_282 ? issue_slots_4_out_uop_inst : _T_281 ? issue_slots_3_out_uop_inst : issue_slots_2_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_1_clear_T = |shamts_oh_1; // @[issue-unit-age-ordered.scala:158:23, :199:49] assign issue_slots_1_clear = _issue_slots_1_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_284 = shamts_oh_4 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_285 = shamts_oh_5 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_2_in_uop_valid = _T_285 ? issue_slots_5_will_be_valid : _T_284 ? issue_slots_4_will_be_valid : shamts_oh_3 == 3'h1 & issue_slots_3_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_2_in_uop_bits_debug_tsrc = _T_285 ? issue_slots_5_out_uop_debug_tsrc : _T_284 ? issue_slots_4_out_uop_debug_tsrc : issue_slots_3_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_debug_fsrc = _T_285 ? issue_slots_5_out_uop_debug_fsrc : _T_284 ? issue_slots_4_out_uop_debug_fsrc : issue_slots_3_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_bp_xcpt_if = _T_285 ? issue_slots_5_out_uop_bp_xcpt_if : _T_284 ? issue_slots_4_out_uop_bp_xcpt_if : issue_slots_3_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_bp_debug_if = _T_285 ? issue_slots_5_out_uop_bp_debug_if : _T_284 ? issue_slots_4_out_uop_bp_debug_if : issue_slots_3_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_xcpt_ma_if = _T_285 ? issue_slots_5_out_uop_xcpt_ma_if : _T_284 ? issue_slots_4_out_uop_xcpt_ma_if : issue_slots_3_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_xcpt_ae_if = _T_285 ? issue_slots_5_out_uop_xcpt_ae_if : _T_284 ? issue_slots_4_out_uop_xcpt_ae_if : issue_slots_3_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_xcpt_pf_if = _T_285 ? issue_slots_5_out_uop_xcpt_pf_if : _T_284 ? issue_slots_4_out_uop_xcpt_pf_if : issue_slots_3_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_typ = _T_285 ? issue_slots_5_out_uop_fp_typ : _T_284 ? issue_slots_4_out_uop_fp_typ : issue_slots_3_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_rm = _T_285 ? issue_slots_5_out_uop_fp_rm : _T_284 ? issue_slots_4_out_uop_fp_rm : issue_slots_3_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_val = _T_285 ? issue_slots_5_out_uop_fp_val : _T_284 ? issue_slots_4_out_uop_fp_val : issue_slots_3_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fcn_op = _T_285 ? issue_slots_5_out_uop_fcn_op : _T_284 ? issue_slots_4_out_uop_fcn_op : issue_slots_3_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fcn_dw = _T_285 ? issue_slots_5_out_uop_fcn_dw : _T_284 ? issue_slots_4_out_uop_fcn_dw : issue_slots_3_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_frs3_en = _T_285 ? issue_slots_5_out_uop_frs3_en : _T_284 ? issue_slots_4_out_uop_frs3_en : issue_slots_3_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_lrs2_rtype = _T_285 ? issue_slots_5_out_uop_lrs2_rtype : _T_284 ? issue_slots_4_out_uop_lrs2_rtype : issue_slots_3_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_lrs1_rtype = _T_285 ? issue_slots_5_out_uop_lrs1_rtype : _T_284 ? issue_slots_4_out_uop_lrs1_rtype : issue_slots_3_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_dst_rtype = _T_285 ? issue_slots_5_out_uop_dst_rtype : _T_284 ? issue_slots_4_out_uop_dst_rtype : issue_slots_3_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_lrs3 = _T_285 ? issue_slots_5_out_uop_lrs3 : _T_284 ? issue_slots_4_out_uop_lrs3 : issue_slots_3_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_lrs2 = _T_285 ? issue_slots_5_out_uop_lrs2 : _T_284 ? issue_slots_4_out_uop_lrs2 : issue_slots_3_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_lrs1 = _T_285 ? issue_slots_5_out_uop_lrs1 : _T_284 ? issue_slots_4_out_uop_lrs1 : issue_slots_3_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_ldst = _T_285 ? issue_slots_5_out_uop_ldst : _T_284 ? issue_slots_4_out_uop_ldst : issue_slots_3_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_ldst_is_rs1 = _T_285 ? issue_slots_5_out_uop_ldst_is_rs1 : _T_284 ? issue_slots_4_out_uop_ldst_is_rs1 : issue_slots_3_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_csr_cmd = _T_285 ? issue_slots_5_out_uop_csr_cmd : _T_284 ? issue_slots_4_out_uop_csr_cmd : issue_slots_3_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_flush_on_commit = _T_285 ? issue_slots_5_out_uop_flush_on_commit : _T_284 ? issue_slots_4_out_uop_flush_on_commit : issue_slots_3_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_unique = _T_285 ? issue_slots_5_out_uop_is_unique : _T_284 ? issue_slots_4_out_uop_is_unique : issue_slots_3_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_uses_stq = _T_285 ? issue_slots_5_out_uop_uses_stq : _T_284 ? issue_slots_4_out_uop_uses_stq : issue_slots_3_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_uses_ldq = _T_285 ? issue_slots_5_out_uop_uses_ldq : _T_284 ? issue_slots_4_out_uop_uses_ldq : issue_slots_3_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_mem_signed = _T_285 ? issue_slots_5_out_uop_mem_signed : _T_284 ? issue_slots_4_out_uop_mem_signed : issue_slots_3_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_mem_size = _T_285 ? issue_slots_5_out_uop_mem_size : _T_284 ? issue_slots_4_out_uop_mem_size : issue_slots_3_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_mem_cmd = _T_285 ? issue_slots_5_out_uop_mem_cmd : _T_284 ? issue_slots_4_out_uop_mem_cmd : issue_slots_3_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_exc_cause = _T_285 ? issue_slots_5_out_uop_exc_cause : _T_284 ? issue_slots_4_out_uop_exc_cause : issue_slots_3_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_exception = _T_285 ? issue_slots_5_out_uop_exception : _T_284 ? issue_slots_4_out_uop_exception : issue_slots_3_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_stale_pdst = _T_285 ? issue_slots_5_out_uop_stale_pdst : _T_284 ? issue_slots_4_out_uop_stale_pdst : issue_slots_3_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_ppred_busy = _T_285 ? issue_slots_5_out_uop_ppred_busy : _T_284 ? issue_slots_4_out_uop_ppred_busy : issue_slots_3_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_prs3_busy = _T_285 ? issue_slots_5_out_uop_prs3_busy : _T_284 ? issue_slots_4_out_uop_prs3_busy : issue_slots_3_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_prs2_busy = _T_285 ? issue_slots_5_out_uop_prs2_busy : _T_284 ? issue_slots_4_out_uop_prs2_busy : issue_slots_3_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_prs1_busy = _T_285 ? issue_slots_5_out_uop_prs1_busy : _T_284 ? issue_slots_4_out_uop_prs1_busy : issue_slots_3_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_ppred = _T_285 ? issue_slots_5_out_uop_ppred : _T_284 ? issue_slots_4_out_uop_ppred : issue_slots_3_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_prs3 = _T_285 ? issue_slots_5_out_uop_prs3 : _T_284 ? issue_slots_4_out_uop_prs3 : issue_slots_3_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_prs2 = _T_285 ? issue_slots_5_out_uop_prs2 : _T_284 ? issue_slots_4_out_uop_prs2 : issue_slots_3_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_prs1 = _T_285 ? issue_slots_5_out_uop_prs1 : _T_284 ? issue_slots_4_out_uop_prs1 : issue_slots_3_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_pdst = _T_285 ? issue_slots_5_out_uop_pdst : _T_284 ? issue_slots_4_out_uop_pdst : issue_slots_3_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_rxq_idx = _T_285 ? issue_slots_5_out_uop_rxq_idx : _T_284 ? issue_slots_4_out_uop_rxq_idx : issue_slots_3_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_stq_idx = _T_285 ? issue_slots_5_out_uop_stq_idx : _T_284 ? issue_slots_4_out_uop_stq_idx : issue_slots_3_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_ldq_idx = _T_285 ? issue_slots_5_out_uop_ldq_idx : _T_284 ? issue_slots_4_out_uop_ldq_idx : issue_slots_3_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_rob_idx = _T_285 ? issue_slots_5_out_uop_rob_idx : _T_284 ? issue_slots_4_out_uop_rob_idx : issue_slots_3_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_vec = _T_285 ? issue_slots_5_out_uop_fp_ctrl_vec : _T_284 ? issue_slots_4_out_uop_fp_ctrl_vec : issue_slots_3_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_wflags = _T_285 ? issue_slots_5_out_uop_fp_ctrl_wflags : _T_284 ? issue_slots_4_out_uop_fp_ctrl_wflags : issue_slots_3_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_sqrt = _T_285 ? issue_slots_5_out_uop_fp_ctrl_sqrt : _T_284 ? issue_slots_4_out_uop_fp_ctrl_sqrt : issue_slots_3_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_div = _T_285 ? issue_slots_5_out_uop_fp_ctrl_div : _T_284 ? issue_slots_4_out_uop_fp_ctrl_div : issue_slots_3_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_fma = _T_285 ? issue_slots_5_out_uop_fp_ctrl_fma : _T_284 ? issue_slots_4_out_uop_fp_ctrl_fma : issue_slots_3_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_fastpipe = _T_285 ? issue_slots_5_out_uop_fp_ctrl_fastpipe : _T_284 ? issue_slots_4_out_uop_fp_ctrl_fastpipe : issue_slots_3_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_toint = _T_285 ? issue_slots_5_out_uop_fp_ctrl_toint : _T_284 ? issue_slots_4_out_uop_fp_ctrl_toint : issue_slots_3_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_fromint = _T_285 ? issue_slots_5_out_uop_fp_ctrl_fromint : _T_284 ? issue_slots_4_out_uop_fp_ctrl_fromint : issue_slots_3_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_typeTagOut = _T_285 ? issue_slots_5_out_uop_fp_ctrl_typeTagOut : _T_284 ? issue_slots_4_out_uop_fp_ctrl_typeTagOut : issue_slots_3_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_typeTagIn = _T_285 ? issue_slots_5_out_uop_fp_ctrl_typeTagIn : _T_284 ? issue_slots_4_out_uop_fp_ctrl_typeTagIn : issue_slots_3_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_swap23 = _T_285 ? issue_slots_5_out_uop_fp_ctrl_swap23 : _T_284 ? issue_slots_4_out_uop_fp_ctrl_swap23 : issue_slots_3_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_swap12 = _T_285 ? issue_slots_5_out_uop_fp_ctrl_swap12 : _T_284 ? issue_slots_4_out_uop_fp_ctrl_swap12 : issue_slots_3_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_ren3 = _T_285 ? issue_slots_5_out_uop_fp_ctrl_ren3 : _T_284 ? issue_slots_4_out_uop_fp_ctrl_ren3 : issue_slots_3_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_ren2 = _T_285 ? issue_slots_5_out_uop_fp_ctrl_ren2 : _T_284 ? issue_slots_4_out_uop_fp_ctrl_ren2 : issue_slots_3_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_ren1 = _T_285 ? issue_slots_5_out_uop_fp_ctrl_ren1 : _T_284 ? issue_slots_4_out_uop_fp_ctrl_ren1 : issue_slots_3_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_wen = _T_285 ? issue_slots_5_out_uop_fp_ctrl_wen : _T_284 ? issue_slots_4_out_uop_fp_ctrl_wen : issue_slots_3_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_ldst = _T_285 ? issue_slots_5_out_uop_fp_ctrl_ldst : _T_284 ? issue_slots_4_out_uop_fp_ctrl_ldst : issue_slots_3_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_op2_sel = _T_285 ? issue_slots_5_out_uop_op2_sel : _T_284 ? issue_slots_4_out_uop_op2_sel : issue_slots_3_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_op1_sel = _T_285 ? issue_slots_5_out_uop_op1_sel : _T_284 ? issue_slots_4_out_uop_op1_sel : issue_slots_3_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_imm_packed = _T_285 ? issue_slots_5_out_uop_imm_packed : _T_284 ? issue_slots_4_out_uop_imm_packed : issue_slots_3_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_pimm = _T_285 ? issue_slots_5_out_uop_pimm : _T_284 ? issue_slots_4_out_uop_pimm : issue_slots_3_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_imm_sel = _T_285 ? issue_slots_5_out_uop_imm_sel : _T_284 ? issue_slots_4_out_uop_imm_sel : issue_slots_3_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_imm_rename = _T_285 ? issue_slots_5_out_uop_imm_rename : _T_284 ? issue_slots_4_out_uop_imm_rename : issue_slots_3_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_taken = _T_285 ? issue_slots_5_out_uop_taken : _T_284 ? issue_slots_4_out_uop_taken : issue_slots_3_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_pc_lob = _T_285 ? issue_slots_5_out_uop_pc_lob : _T_284 ? issue_slots_4_out_uop_pc_lob : issue_slots_3_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_edge_inst = _T_285 ? issue_slots_5_out_uop_edge_inst : _T_284 ? issue_slots_4_out_uop_edge_inst : issue_slots_3_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_ftq_idx = _T_285 ? issue_slots_5_out_uop_ftq_idx : _T_284 ? issue_slots_4_out_uop_ftq_idx : issue_slots_3_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_mov = _T_285 ? issue_slots_5_out_uop_is_mov : _T_284 ? issue_slots_4_out_uop_is_mov : issue_slots_3_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_rocc = _T_285 ? issue_slots_5_out_uop_is_rocc : _T_284 ? issue_slots_4_out_uop_is_rocc : issue_slots_3_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_sys_pc2epc = _T_285 ? issue_slots_5_out_uop_is_sys_pc2epc : _T_284 ? issue_slots_4_out_uop_is_sys_pc2epc : issue_slots_3_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_eret = _T_285 ? issue_slots_5_out_uop_is_eret : _T_284 ? issue_slots_4_out_uop_is_eret : issue_slots_3_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_amo = _T_285 ? issue_slots_5_out_uop_is_amo : _T_284 ? issue_slots_4_out_uop_is_amo : issue_slots_3_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_sfence = _T_285 ? issue_slots_5_out_uop_is_sfence : _T_284 ? issue_slots_4_out_uop_is_sfence : issue_slots_3_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_fencei = _T_285 ? issue_slots_5_out_uop_is_fencei : _T_284 ? issue_slots_4_out_uop_is_fencei : issue_slots_3_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_fence = _T_285 ? issue_slots_5_out_uop_is_fence : _T_284 ? issue_slots_4_out_uop_is_fence : issue_slots_3_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_sfb = _T_285 ? issue_slots_5_out_uop_is_sfb : _T_284 ? issue_slots_4_out_uop_is_sfb : issue_slots_3_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_br_type = _T_285 ? issue_slots_5_out_uop_br_type : _T_284 ? issue_slots_4_out_uop_br_type : issue_slots_3_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_br_tag = _T_285 ? issue_slots_5_out_uop_br_tag : _T_284 ? issue_slots_4_out_uop_br_tag : issue_slots_3_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_br_mask = _T_285 ? issue_slots_5_out_uop_br_mask : _T_284 ? issue_slots_4_out_uop_br_mask : issue_slots_3_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_dis_col_sel = _T_285 ? issue_slots_5_out_uop_dis_col_sel : _T_284 ? issue_slots_4_out_uop_dis_col_sel : issue_slots_3_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iw_p3_bypass_hint = _T_285 ? issue_slots_5_out_uop_iw_p3_bypass_hint : _T_284 ? issue_slots_4_out_uop_iw_p3_bypass_hint : issue_slots_3_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iw_p2_bypass_hint = _T_285 ? issue_slots_5_out_uop_iw_p2_bypass_hint : _T_284 ? issue_slots_4_out_uop_iw_p2_bypass_hint : issue_slots_3_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iw_p1_bypass_hint = _T_285 ? issue_slots_5_out_uop_iw_p1_bypass_hint : _T_284 ? issue_slots_4_out_uop_iw_p1_bypass_hint : issue_slots_3_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iw_p2_speculative_child = _T_285 ? issue_slots_5_out_uop_iw_p2_speculative_child : _T_284 ? issue_slots_4_out_uop_iw_p2_speculative_child : issue_slots_3_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iw_p1_speculative_child = _T_285 ? issue_slots_5_out_uop_iw_p1_speculative_child : _T_284 ? issue_slots_4_out_uop_iw_p1_speculative_child : issue_slots_3_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iw_issued = _T_285 ? issue_slots_5_out_uop_iw_issued : _T_284 ? issue_slots_4_out_uop_iw_issued : issue_slots_3_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_0 = _T_285 ? issue_slots_5_out_uop_fu_code_0 : _T_284 ? issue_slots_4_out_uop_fu_code_0 : issue_slots_3_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_1 = _T_285 ? issue_slots_5_out_uop_fu_code_1 : _T_284 ? issue_slots_4_out_uop_fu_code_1 : issue_slots_3_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_2 = _T_285 ? issue_slots_5_out_uop_fu_code_2 : _T_284 ? issue_slots_4_out_uop_fu_code_2 : issue_slots_3_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_3 = _T_285 ? issue_slots_5_out_uop_fu_code_3 : _T_284 ? issue_slots_4_out_uop_fu_code_3 : issue_slots_3_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_4 = _T_285 ? issue_slots_5_out_uop_fu_code_4 : _T_284 ? issue_slots_4_out_uop_fu_code_4 : issue_slots_3_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_5 = _T_285 ? issue_slots_5_out_uop_fu_code_5 : _T_284 ? issue_slots_4_out_uop_fu_code_5 : issue_slots_3_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_6 = _T_285 ? issue_slots_5_out_uop_fu_code_6 : _T_284 ? issue_slots_4_out_uop_fu_code_6 : issue_slots_3_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_7 = _T_285 ? issue_slots_5_out_uop_fu_code_7 : _T_284 ? issue_slots_4_out_uop_fu_code_7 : issue_slots_3_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_8 = _T_285 ? issue_slots_5_out_uop_fu_code_8 : _T_284 ? issue_slots_4_out_uop_fu_code_8 : issue_slots_3_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_9 = _T_285 ? issue_slots_5_out_uop_fu_code_9 : _T_284 ? issue_slots_4_out_uop_fu_code_9 : issue_slots_3_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iq_type_0 = _T_285 ? issue_slots_5_out_uop_iq_type_0 : _T_284 ? issue_slots_4_out_uop_iq_type_0 : issue_slots_3_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iq_type_1 = _T_285 ? issue_slots_5_out_uop_iq_type_1 : _T_284 ? issue_slots_4_out_uop_iq_type_1 : issue_slots_3_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iq_type_2 = _T_285 ? issue_slots_5_out_uop_iq_type_2 : _T_284 ? issue_slots_4_out_uop_iq_type_2 : issue_slots_3_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iq_type_3 = _T_285 ? issue_slots_5_out_uop_iq_type_3 : _T_284 ? issue_slots_4_out_uop_iq_type_3 : issue_slots_3_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_debug_pc = _T_285 ? issue_slots_5_out_uop_debug_pc : _T_284 ? issue_slots_4_out_uop_debug_pc : issue_slots_3_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_rvc = _T_285 ? issue_slots_5_out_uop_is_rvc : _T_284 ? issue_slots_4_out_uop_is_rvc : issue_slots_3_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_debug_inst = _T_285 ? issue_slots_5_out_uop_debug_inst : _T_284 ? issue_slots_4_out_uop_debug_inst : issue_slots_3_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_inst = _T_285 ? issue_slots_5_out_uop_inst : _T_284 ? issue_slots_4_out_uop_inst : issue_slots_3_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_2_clear_T = |shamts_oh_2; // @[issue-unit-age-ordered.scala:158:23, :199:49] assign issue_slots_2_clear = _issue_slots_2_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_287 = shamts_oh_5 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_288 = shamts_oh_6 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_3_in_uop_valid = _T_288 ? issue_slots_6_will_be_valid : _T_287 ? issue_slots_5_will_be_valid : shamts_oh_4 == 3'h1 & issue_slots_4_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_3_in_uop_bits_debug_tsrc = _T_288 ? issue_slots_6_out_uop_debug_tsrc : _T_287 ? issue_slots_5_out_uop_debug_tsrc : issue_slots_4_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_debug_fsrc = _T_288 ? issue_slots_6_out_uop_debug_fsrc : _T_287 ? issue_slots_5_out_uop_debug_fsrc : issue_slots_4_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_bp_xcpt_if = _T_288 ? issue_slots_6_out_uop_bp_xcpt_if : _T_287 ? issue_slots_5_out_uop_bp_xcpt_if : issue_slots_4_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_bp_debug_if = _T_288 ? issue_slots_6_out_uop_bp_debug_if : _T_287 ? issue_slots_5_out_uop_bp_debug_if : issue_slots_4_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_xcpt_ma_if = _T_288 ? issue_slots_6_out_uop_xcpt_ma_if : _T_287 ? issue_slots_5_out_uop_xcpt_ma_if : issue_slots_4_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_xcpt_ae_if = _T_288 ? issue_slots_6_out_uop_xcpt_ae_if : _T_287 ? issue_slots_5_out_uop_xcpt_ae_if : issue_slots_4_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_xcpt_pf_if = _T_288 ? issue_slots_6_out_uop_xcpt_pf_if : _T_287 ? issue_slots_5_out_uop_xcpt_pf_if : issue_slots_4_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_typ = _T_288 ? issue_slots_6_out_uop_fp_typ : _T_287 ? issue_slots_5_out_uop_fp_typ : issue_slots_4_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_rm = _T_288 ? issue_slots_6_out_uop_fp_rm : _T_287 ? issue_slots_5_out_uop_fp_rm : issue_slots_4_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_val = _T_288 ? issue_slots_6_out_uop_fp_val : _T_287 ? issue_slots_5_out_uop_fp_val : issue_slots_4_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fcn_op = _T_288 ? issue_slots_6_out_uop_fcn_op : _T_287 ? issue_slots_5_out_uop_fcn_op : issue_slots_4_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fcn_dw = _T_288 ? issue_slots_6_out_uop_fcn_dw : _T_287 ? issue_slots_5_out_uop_fcn_dw : issue_slots_4_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_frs3_en = _T_288 ? issue_slots_6_out_uop_frs3_en : _T_287 ? issue_slots_5_out_uop_frs3_en : issue_slots_4_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_lrs2_rtype = _T_288 ? issue_slots_6_out_uop_lrs2_rtype : _T_287 ? issue_slots_5_out_uop_lrs2_rtype : issue_slots_4_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_lrs1_rtype = _T_288 ? issue_slots_6_out_uop_lrs1_rtype : _T_287 ? issue_slots_5_out_uop_lrs1_rtype : issue_slots_4_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_dst_rtype = _T_288 ? issue_slots_6_out_uop_dst_rtype : _T_287 ? issue_slots_5_out_uop_dst_rtype : issue_slots_4_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_lrs3 = _T_288 ? issue_slots_6_out_uop_lrs3 : _T_287 ? issue_slots_5_out_uop_lrs3 : issue_slots_4_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_lrs2 = _T_288 ? issue_slots_6_out_uop_lrs2 : _T_287 ? issue_slots_5_out_uop_lrs2 : issue_slots_4_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_lrs1 = _T_288 ? issue_slots_6_out_uop_lrs1 : _T_287 ? issue_slots_5_out_uop_lrs1 : issue_slots_4_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_ldst = _T_288 ? issue_slots_6_out_uop_ldst : _T_287 ? issue_slots_5_out_uop_ldst : issue_slots_4_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_ldst_is_rs1 = _T_288 ? issue_slots_6_out_uop_ldst_is_rs1 : _T_287 ? issue_slots_5_out_uop_ldst_is_rs1 : issue_slots_4_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_csr_cmd = _T_288 ? issue_slots_6_out_uop_csr_cmd : _T_287 ? issue_slots_5_out_uop_csr_cmd : issue_slots_4_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_flush_on_commit = _T_288 ? issue_slots_6_out_uop_flush_on_commit : _T_287 ? issue_slots_5_out_uop_flush_on_commit : issue_slots_4_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_unique = _T_288 ? issue_slots_6_out_uop_is_unique : _T_287 ? issue_slots_5_out_uop_is_unique : issue_slots_4_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_uses_stq = _T_288 ? issue_slots_6_out_uop_uses_stq : _T_287 ? issue_slots_5_out_uop_uses_stq : issue_slots_4_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_uses_ldq = _T_288 ? issue_slots_6_out_uop_uses_ldq : _T_287 ? issue_slots_5_out_uop_uses_ldq : issue_slots_4_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_mem_signed = _T_288 ? issue_slots_6_out_uop_mem_signed : _T_287 ? issue_slots_5_out_uop_mem_signed : issue_slots_4_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_mem_size = _T_288 ? issue_slots_6_out_uop_mem_size : _T_287 ? issue_slots_5_out_uop_mem_size : issue_slots_4_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_mem_cmd = _T_288 ? issue_slots_6_out_uop_mem_cmd : _T_287 ? issue_slots_5_out_uop_mem_cmd : issue_slots_4_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_exc_cause = _T_288 ? issue_slots_6_out_uop_exc_cause : _T_287 ? issue_slots_5_out_uop_exc_cause : issue_slots_4_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_exception = _T_288 ? issue_slots_6_out_uop_exception : _T_287 ? issue_slots_5_out_uop_exception : issue_slots_4_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_stale_pdst = _T_288 ? issue_slots_6_out_uop_stale_pdst : _T_287 ? issue_slots_5_out_uop_stale_pdst : issue_slots_4_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_ppred_busy = _T_288 ? issue_slots_6_out_uop_ppred_busy : _T_287 ? issue_slots_5_out_uop_ppred_busy : issue_slots_4_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_prs3_busy = _T_288 ? issue_slots_6_out_uop_prs3_busy : _T_287 ? issue_slots_5_out_uop_prs3_busy : issue_slots_4_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_prs2_busy = _T_288 ? issue_slots_6_out_uop_prs2_busy : _T_287 ? issue_slots_5_out_uop_prs2_busy : issue_slots_4_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_prs1_busy = _T_288 ? issue_slots_6_out_uop_prs1_busy : _T_287 ? issue_slots_5_out_uop_prs1_busy : issue_slots_4_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_ppred = _T_288 ? issue_slots_6_out_uop_ppred : _T_287 ? issue_slots_5_out_uop_ppred : issue_slots_4_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_prs3 = _T_288 ? issue_slots_6_out_uop_prs3 : _T_287 ? issue_slots_5_out_uop_prs3 : issue_slots_4_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_prs2 = _T_288 ? issue_slots_6_out_uop_prs2 : _T_287 ? issue_slots_5_out_uop_prs2 : issue_slots_4_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_prs1 = _T_288 ? issue_slots_6_out_uop_prs1 : _T_287 ? issue_slots_5_out_uop_prs1 : issue_slots_4_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_pdst = _T_288 ? issue_slots_6_out_uop_pdst : _T_287 ? issue_slots_5_out_uop_pdst : issue_slots_4_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_rxq_idx = _T_288 ? issue_slots_6_out_uop_rxq_idx : _T_287 ? issue_slots_5_out_uop_rxq_idx : issue_slots_4_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_stq_idx = _T_288 ? issue_slots_6_out_uop_stq_idx : _T_287 ? issue_slots_5_out_uop_stq_idx : issue_slots_4_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_ldq_idx = _T_288 ? issue_slots_6_out_uop_ldq_idx : _T_287 ? issue_slots_5_out_uop_ldq_idx : issue_slots_4_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_rob_idx = _T_288 ? issue_slots_6_out_uop_rob_idx : _T_287 ? issue_slots_5_out_uop_rob_idx : issue_slots_4_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_vec = _T_288 ? issue_slots_6_out_uop_fp_ctrl_vec : _T_287 ? issue_slots_5_out_uop_fp_ctrl_vec : issue_slots_4_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_wflags = _T_288 ? issue_slots_6_out_uop_fp_ctrl_wflags : _T_287 ? issue_slots_5_out_uop_fp_ctrl_wflags : issue_slots_4_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_sqrt = _T_288 ? issue_slots_6_out_uop_fp_ctrl_sqrt : _T_287 ? issue_slots_5_out_uop_fp_ctrl_sqrt : issue_slots_4_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_div = _T_288 ? issue_slots_6_out_uop_fp_ctrl_div : _T_287 ? issue_slots_5_out_uop_fp_ctrl_div : issue_slots_4_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_fma = _T_288 ? issue_slots_6_out_uop_fp_ctrl_fma : _T_287 ? issue_slots_5_out_uop_fp_ctrl_fma : issue_slots_4_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_fastpipe = _T_288 ? issue_slots_6_out_uop_fp_ctrl_fastpipe : _T_287 ? issue_slots_5_out_uop_fp_ctrl_fastpipe : issue_slots_4_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_toint = _T_288 ? issue_slots_6_out_uop_fp_ctrl_toint : _T_287 ? issue_slots_5_out_uop_fp_ctrl_toint : issue_slots_4_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_fromint = _T_288 ? issue_slots_6_out_uop_fp_ctrl_fromint : _T_287 ? issue_slots_5_out_uop_fp_ctrl_fromint : issue_slots_4_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_typeTagOut = _T_288 ? issue_slots_6_out_uop_fp_ctrl_typeTagOut : _T_287 ? issue_slots_5_out_uop_fp_ctrl_typeTagOut : issue_slots_4_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_typeTagIn = _T_288 ? issue_slots_6_out_uop_fp_ctrl_typeTagIn : _T_287 ? issue_slots_5_out_uop_fp_ctrl_typeTagIn : issue_slots_4_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_swap23 = _T_288 ? issue_slots_6_out_uop_fp_ctrl_swap23 : _T_287 ? issue_slots_5_out_uop_fp_ctrl_swap23 : issue_slots_4_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_swap12 = _T_288 ? issue_slots_6_out_uop_fp_ctrl_swap12 : _T_287 ? issue_slots_5_out_uop_fp_ctrl_swap12 : issue_slots_4_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_ren3 = _T_288 ? issue_slots_6_out_uop_fp_ctrl_ren3 : _T_287 ? issue_slots_5_out_uop_fp_ctrl_ren3 : issue_slots_4_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_ren2 = _T_288 ? issue_slots_6_out_uop_fp_ctrl_ren2 : _T_287 ? issue_slots_5_out_uop_fp_ctrl_ren2 : issue_slots_4_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_ren1 = _T_288 ? issue_slots_6_out_uop_fp_ctrl_ren1 : _T_287 ? issue_slots_5_out_uop_fp_ctrl_ren1 : issue_slots_4_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_wen = _T_288 ? issue_slots_6_out_uop_fp_ctrl_wen : _T_287 ? issue_slots_5_out_uop_fp_ctrl_wen : issue_slots_4_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_ldst = _T_288 ? issue_slots_6_out_uop_fp_ctrl_ldst : _T_287 ? issue_slots_5_out_uop_fp_ctrl_ldst : issue_slots_4_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_op2_sel = _T_288 ? issue_slots_6_out_uop_op2_sel : _T_287 ? issue_slots_5_out_uop_op2_sel : issue_slots_4_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_op1_sel = _T_288 ? issue_slots_6_out_uop_op1_sel : _T_287 ? issue_slots_5_out_uop_op1_sel : issue_slots_4_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_imm_packed = _T_288 ? issue_slots_6_out_uop_imm_packed : _T_287 ? issue_slots_5_out_uop_imm_packed : issue_slots_4_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_pimm = _T_288 ? issue_slots_6_out_uop_pimm : _T_287 ? issue_slots_5_out_uop_pimm : issue_slots_4_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_imm_sel = _T_288 ? issue_slots_6_out_uop_imm_sel : _T_287 ? issue_slots_5_out_uop_imm_sel : issue_slots_4_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_imm_rename = _T_288 ? issue_slots_6_out_uop_imm_rename : _T_287 ? issue_slots_5_out_uop_imm_rename : issue_slots_4_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_taken = _T_288 ? issue_slots_6_out_uop_taken : _T_287 ? issue_slots_5_out_uop_taken : issue_slots_4_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_pc_lob = _T_288 ? issue_slots_6_out_uop_pc_lob : _T_287 ? issue_slots_5_out_uop_pc_lob : issue_slots_4_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_edge_inst = _T_288 ? issue_slots_6_out_uop_edge_inst : _T_287 ? issue_slots_5_out_uop_edge_inst : issue_slots_4_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_ftq_idx = _T_288 ? issue_slots_6_out_uop_ftq_idx : _T_287 ? issue_slots_5_out_uop_ftq_idx : issue_slots_4_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_mov = _T_288 ? issue_slots_6_out_uop_is_mov : _T_287 ? issue_slots_5_out_uop_is_mov : issue_slots_4_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_rocc = _T_288 ? issue_slots_6_out_uop_is_rocc : _T_287 ? issue_slots_5_out_uop_is_rocc : issue_slots_4_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_sys_pc2epc = _T_288 ? issue_slots_6_out_uop_is_sys_pc2epc : _T_287 ? issue_slots_5_out_uop_is_sys_pc2epc : issue_slots_4_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_eret = _T_288 ? issue_slots_6_out_uop_is_eret : _T_287 ? issue_slots_5_out_uop_is_eret : issue_slots_4_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_amo = _T_288 ? issue_slots_6_out_uop_is_amo : _T_287 ? issue_slots_5_out_uop_is_amo : issue_slots_4_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_sfence = _T_288 ? issue_slots_6_out_uop_is_sfence : _T_287 ? issue_slots_5_out_uop_is_sfence : issue_slots_4_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_fencei = _T_288 ? issue_slots_6_out_uop_is_fencei : _T_287 ? issue_slots_5_out_uop_is_fencei : issue_slots_4_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_fence = _T_288 ? issue_slots_6_out_uop_is_fence : _T_287 ? issue_slots_5_out_uop_is_fence : issue_slots_4_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_sfb = _T_288 ? issue_slots_6_out_uop_is_sfb : _T_287 ? issue_slots_5_out_uop_is_sfb : issue_slots_4_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_br_type = _T_288 ? issue_slots_6_out_uop_br_type : _T_287 ? issue_slots_5_out_uop_br_type : issue_slots_4_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_br_tag = _T_288 ? issue_slots_6_out_uop_br_tag : _T_287 ? issue_slots_5_out_uop_br_tag : issue_slots_4_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_br_mask = _T_288 ? issue_slots_6_out_uop_br_mask : _T_287 ? issue_slots_5_out_uop_br_mask : issue_slots_4_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_dis_col_sel = _T_288 ? issue_slots_6_out_uop_dis_col_sel : _T_287 ? issue_slots_5_out_uop_dis_col_sel : issue_slots_4_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iw_p3_bypass_hint = _T_288 ? issue_slots_6_out_uop_iw_p3_bypass_hint : _T_287 ? issue_slots_5_out_uop_iw_p3_bypass_hint : issue_slots_4_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iw_p2_bypass_hint = _T_288 ? issue_slots_6_out_uop_iw_p2_bypass_hint : _T_287 ? issue_slots_5_out_uop_iw_p2_bypass_hint : issue_slots_4_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iw_p1_bypass_hint = _T_288 ? issue_slots_6_out_uop_iw_p1_bypass_hint : _T_287 ? issue_slots_5_out_uop_iw_p1_bypass_hint : issue_slots_4_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iw_p2_speculative_child = _T_288 ? issue_slots_6_out_uop_iw_p2_speculative_child : _T_287 ? issue_slots_5_out_uop_iw_p2_speculative_child : issue_slots_4_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iw_p1_speculative_child = _T_288 ? issue_slots_6_out_uop_iw_p1_speculative_child : _T_287 ? issue_slots_5_out_uop_iw_p1_speculative_child : issue_slots_4_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iw_issued = _T_288 ? issue_slots_6_out_uop_iw_issued : _T_287 ? issue_slots_5_out_uop_iw_issued : issue_slots_4_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_0 = _T_288 ? issue_slots_6_out_uop_fu_code_0 : _T_287 ? issue_slots_5_out_uop_fu_code_0 : issue_slots_4_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_1 = _T_288 ? issue_slots_6_out_uop_fu_code_1 : _T_287 ? issue_slots_5_out_uop_fu_code_1 : issue_slots_4_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_2 = _T_288 ? issue_slots_6_out_uop_fu_code_2 : _T_287 ? issue_slots_5_out_uop_fu_code_2 : issue_slots_4_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_3 = _T_288 ? issue_slots_6_out_uop_fu_code_3 : _T_287 ? issue_slots_5_out_uop_fu_code_3 : issue_slots_4_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_4 = _T_288 ? issue_slots_6_out_uop_fu_code_4 : _T_287 ? issue_slots_5_out_uop_fu_code_4 : issue_slots_4_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_5 = _T_288 ? issue_slots_6_out_uop_fu_code_5 : _T_287 ? issue_slots_5_out_uop_fu_code_5 : issue_slots_4_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_6 = _T_288 ? issue_slots_6_out_uop_fu_code_6 : _T_287 ? issue_slots_5_out_uop_fu_code_6 : issue_slots_4_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_7 = _T_288 ? issue_slots_6_out_uop_fu_code_7 : _T_287 ? issue_slots_5_out_uop_fu_code_7 : issue_slots_4_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_8 = _T_288 ? issue_slots_6_out_uop_fu_code_8 : _T_287 ? issue_slots_5_out_uop_fu_code_8 : issue_slots_4_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_9 = _T_288 ? issue_slots_6_out_uop_fu_code_9 : _T_287 ? issue_slots_5_out_uop_fu_code_9 : issue_slots_4_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iq_type_0 = _T_288 ? issue_slots_6_out_uop_iq_type_0 : _T_287 ? issue_slots_5_out_uop_iq_type_0 : issue_slots_4_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iq_type_1 = _T_288 ? issue_slots_6_out_uop_iq_type_1 : _T_287 ? issue_slots_5_out_uop_iq_type_1 : issue_slots_4_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iq_type_2 = _T_288 ? issue_slots_6_out_uop_iq_type_2 : _T_287 ? issue_slots_5_out_uop_iq_type_2 : issue_slots_4_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iq_type_3 = _T_288 ? issue_slots_6_out_uop_iq_type_3 : _T_287 ? issue_slots_5_out_uop_iq_type_3 : issue_slots_4_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_debug_pc = _T_288 ? issue_slots_6_out_uop_debug_pc : _T_287 ? issue_slots_5_out_uop_debug_pc : issue_slots_4_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_rvc = _T_288 ? issue_slots_6_out_uop_is_rvc : _T_287 ? issue_slots_5_out_uop_is_rvc : issue_slots_4_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_debug_inst = _T_288 ? issue_slots_6_out_uop_debug_inst : _T_287 ? issue_slots_5_out_uop_debug_inst : issue_slots_4_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_inst = _T_288 ? issue_slots_6_out_uop_inst : _T_287 ? issue_slots_5_out_uop_inst : issue_slots_4_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_3_clear_T = |shamts_oh_3; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_3_clear = _issue_slots_3_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_290 = shamts_oh_6 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_291 = shamts_oh_7 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_4_in_uop_valid = _T_291 ? issue_slots_7_will_be_valid : _T_290 ? issue_slots_6_will_be_valid : shamts_oh_5 == 3'h1 & issue_slots_5_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_4_in_uop_bits_debug_tsrc = _T_291 ? issue_slots_7_out_uop_debug_tsrc : _T_290 ? issue_slots_6_out_uop_debug_tsrc : issue_slots_5_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_debug_fsrc = _T_291 ? issue_slots_7_out_uop_debug_fsrc : _T_290 ? issue_slots_6_out_uop_debug_fsrc : issue_slots_5_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_bp_xcpt_if = _T_291 ? issue_slots_7_out_uop_bp_xcpt_if : _T_290 ? issue_slots_6_out_uop_bp_xcpt_if : issue_slots_5_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_bp_debug_if = _T_291 ? issue_slots_7_out_uop_bp_debug_if : _T_290 ? issue_slots_6_out_uop_bp_debug_if : issue_slots_5_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_xcpt_ma_if = _T_291 ? issue_slots_7_out_uop_xcpt_ma_if : _T_290 ? issue_slots_6_out_uop_xcpt_ma_if : issue_slots_5_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_xcpt_ae_if = _T_291 ? issue_slots_7_out_uop_xcpt_ae_if : _T_290 ? issue_slots_6_out_uop_xcpt_ae_if : issue_slots_5_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_xcpt_pf_if = _T_291 ? issue_slots_7_out_uop_xcpt_pf_if : _T_290 ? issue_slots_6_out_uop_xcpt_pf_if : issue_slots_5_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_typ = _T_291 ? issue_slots_7_out_uop_fp_typ : _T_290 ? issue_slots_6_out_uop_fp_typ : issue_slots_5_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_rm = _T_291 ? issue_slots_7_out_uop_fp_rm : _T_290 ? issue_slots_6_out_uop_fp_rm : issue_slots_5_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_val = _T_291 ? issue_slots_7_out_uop_fp_val : _T_290 ? issue_slots_6_out_uop_fp_val : issue_slots_5_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fcn_op = _T_291 ? issue_slots_7_out_uop_fcn_op : _T_290 ? issue_slots_6_out_uop_fcn_op : issue_slots_5_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fcn_dw = _T_291 ? issue_slots_7_out_uop_fcn_dw : _T_290 ? issue_slots_6_out_uop_fcn_dw : issue_slots_5_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_frs3_en = _T_291 ? issue_slots_7_out_uop_frs3_en : _T_290 ? issue_slots_6_out_uop_frs3_en : issue_slots_5_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_lrs2_rtype = _T_291 ? issue_slots_7_out_uop_lrs2_rtype : _T_290 ? issue_slots_6_out_uop_lrs2_rtype : issue_slots_5_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_lrs1_rtype = _T_291 ? issue_slots_7_out_uop_lrs1_rtype : _T_290 ? issue_slots_6_out_uop_lrs1_rtype : issue_slots_5_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_dst_rtype = _T_291 ? issue_slots_7_out_uop_dst_rtype : _T_290 ? issue_slots_6_out_uop_dst_rtype : issue_slots_5_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_lrs3 = _T_291 ? issue_slots_7_out_uop_lrs3 : _T_290 ? issue_slots_6_out_uop_lrs3 : issue_slots_5_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_lrs2 = _T_291 ? issue_slots_7_out_uop_lrs2 : _T_290 ? issue_slots_6_out_uop_lrs2 : issue_slots_5_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_lrs1 = _T_291 ? issue_slots_7_out_uop_lrs1 : _T_290 ? issue_slots_6_out_uop_lrs1 : issue_slots_5_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_ldst = _T_291 ? issue_slots_7_out_uop_ldst : _T_290 ? issue_slots_6_out_uop_ldst : issue_slots_5_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_ldst_is_rs1 = _T_291 ? issue_slots_7_out_uop_ldst_is_rs1 : _T_290 ? issue_slots_6_out_uop_ldst_is_rs1 : issue_slots_5_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_csr_cmd = _T_291 ? issue_slots_7_out_uop_csr_cmd : _T_290 ? issue_slots_6_out_uop_csr_cmd : issue_slots_5_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_flush_on_commit = _T_291 ? issue_slots_7_out_uop_flush_on_commit : _T_290 ? issue_slots_6_out_uop_flush_on_commit : issue_slots_5_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_unique = _T_291 ? issue_slots_7_out_uop_is_unique : _T_290 ? issue_slots_6_out_uop_is_unique : issue_slots_5_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_uses_stq = _T_291 ? issue_slots_7_out_uop_uses_stq : _T_290 ? issue_slots_6_out_uop_uses_stq : issue_slots_5_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_uses_ldq = _T_291 ? issue_slots_7_out_uop_uses_ldq : _T_290 ? issue_slots_6_out_uop_uses_ldq : issue_slots_5_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_mem_signed = _T_291 ? issue_slots_7_out_uop_mem_signed : _T_290 ? issue_slots_6_out_uop_mem_signed : issue_slots_5_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_mem_size = _T_291 ? issue_slots_7_out_uop_mem_size : _T_290 ? issue_slots_6_out_uop_mem_size : issue_slots_5_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_mem_cmd = _T_291 ? issue_slots_7_out_uop_mem_cmd : _T_290 ? issue_slots_6_out_uop_mem_cmd : issue_slots_5_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_exc_cause = _T_291 ? issue_slots_7_out_uop_exc_cause : _T_290 ? issue_slots_6_out_uop_exc_cause : issue_slots_5_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_exception = _T_291 ? issue_slots_7_out_uop_exception : _T_290 ? issue_slots_6_out_uop_exception : issue_slots_5_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_stale_pdst = _T_291 ? issue_slots_7_out_uop_stale_pdst : _T_290 ? issue_slots_6_out_uop_stale_pdst : issue_slots_5_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_ppred_busy = _T_291 ? issue_slots_7_out_uop_ppred_busy : _T_290 ? issue_slots_6_out_uop_ppred_busy : issue_slots_5_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_prs3_busy = _T_291 ? issue_slots_7_out_uop_prs3_busy : _T_290 ? issue_slots_6_out_uop_prs3_busy : issue_slots_5_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_prs2_busy = _T_291 ? issue_slots_7_out_uop_prs2_busy : _T_290 ? issue_slots_6_out_uop_prs2_busy : issue_slots_5_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_prs1_busy = _T_291 ? issue_slots_7_out_uop_prs1_busy : _T_290 ? issue_slots_6_out_uop_prs1_busy : issue_slots_5_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_ppred = _T_291 ? issue_slots_7_out_uop_ppred : _T_290 ? issue_slots_6_out_uop_ppred : issue_slots_5_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_prs3 = _T_291 ? issue_slots_7_out_uop_prs3 : _T_290 ? issue_slots_6_out_uop_prs3 : issue_slots_5_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_prs2 = _T_291 ? issue_slots_7_out_uop_prs2 : _T_290 ? issue_slots_6_out_uop_prs2 : issue_slots_5_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_prs1 = _T_291 ? issue_slots_7_out_uop_prs1 : _T_290 ? issue_slots_6_out_uop_prs1 : issue_slots_5_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_pdst = _T_291 ? issue_slots_7_out_uop_pdst : _T_290 ? issue_slots_6_out_uop_pdst : issue_slots_5_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_rxq_idx = _T_291 ? issue_slots_7_out_uop_rxq_idx : _T_290 ? issue_slots_6_out_uop_rxq_idx : issue_slots_5_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_stq_idx = _T_291 ? issue_slots_7_out_uop_stq_idx : _T_290 ? issue_slots_6_out_uop_stq_idx : issue_slots_5_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_ldq_idx = _T_291 ? issue_slots_7_out_uop_ldq_idx : _T_290 ? issue_slots_6_out_uop_ldq_idx : issue_slots_5_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_rob_idx = _T_291 ? issue_slots_7_out_uop_rob_idx : _T_290 ? issue_slots_6_out_uop_rob_idx : issue_slots_5_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_vec = _T_291 ? issue_slots_7_out_uop_fp_ctrl_vec : _T_290 ? issue_slots_6_out_uop_fp_ctrl_vec : issue_slots_5_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_wflags = _T_291 ? issue_slots_7_out_uop_fp_ctrl_wflags : _T_290 ? issue_slots_6_out_uop_fp_ctrl_wflags : issue_slots_5_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_sqrt = _T_291 ? issue_slots_7_out_uop_fp_ctrl_sqrt : _T_290 ? issue_slots_6_out_uop_fp_ctrl_sqrt : issue_slots_5_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_div = _T_291 ? issue_slots_7_out_uop_fp_ctrl_div : _T_290 ? issue_slots_6_out_uop_fp_ctrl_div : issue_slots_5_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_fma = _T_291 ? issue_slots_7_out_uop_fp_ctrl_fma : _T_290 ? issue_slots_6_out_uop_fp_ctrl_fma : issue_slots_5_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_fastpipe = _T_291 ? issue_slots_7_out_uop_fp_ctrl_fastpipe : _T_290 ? issue_slots_6_out_uop_fp_ctrl_fastpipe : issue_slots_5_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_toint = _T_291 ? issue_slots_7_out_uop_fp_ctrl_toint : _T_290 ? issue_slots_6_out_uop_fp_ctrl_toint : issue_slots_5_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_fromint = _T_291 ? issue_slots_7_out_uop_fp_ctrl_fromint : _T_290 ? issue_slots_6_out_uop_fp_ctrl_fromint : issue_slots_5_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_typeTagOut = _T_291 ? issue_slots_7_out_uop_fp_ctrl_typeTagOut : _T_290 ? issue_slots_6_out_uop_fp_ctrl_typeTagOut : issue_slots_5_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_typeTagIn = _T_291 ? issue_slots_7_out_uop_fp_ctrl_typeTagIn : _T_290 ? issue_slots_6_out_uop_fp_ctrl_typeTagIn : issue_slots_5_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_swap23 = _T_291 ? issue_slots_7_out_uop_fp_ctrl_swap23 : _T_290 ? issue_slots_6_out_uop_fp_ctrl_swap23 : issue_slots_5_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_swap12 = _T_291 ? issue_slots_7_out_uop_fp_ctrl_swap12 : _T_290 ? issue_slots_6_out_uop_fp_ctrl_swap12 : issue_slots_5_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_ren3 = _T_291 ? issue_slots_7_out_uop_fp_ctrl_ren3 : _T_290 ? issue_slots_6_out_uop_fp_ctrl_ren3 : issue_slots_5_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_ren2 = _T_291 ? issue_slots_7_out_uop_fp_ctrl_ren2 : _T_290 ? issue_slots_6_out_uop_fp_ctrl_ren2 : issue_slots_5_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_ren1 = _T_291 ? issue_slots_7_out_uop_fp_ctrl_ren1 : _T_290 ? issue_slots_6_out_uop_fp_ctrl_ren1 : issue_slots_5_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_wen = _T_291 ? issue_slots_7_out_uop_fp_ctrl_wen : _T_290 ? issue_slots_6_out_uop_fp_ctrl_wen : issue_slots_5_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_ldst = _T_291 ? issue_slots_7_out_uop_fp_ctrl_ldst : _T_290 ? issue_slots_6_out_uop_fp_ctrl_ldst : issue_slots_5_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_op2_sel = _T_291 ? issue_slots_7_out_uop_op2_sel : _T_290 ? issue_slots_6_out_uop_op2_sel : issue_slots_5_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_op1_sel = _T_291 ? issue_slots_7_out_uop_op1_sel : _T_290 ? issue_slots_6_out_uop_op1_sel : issue_slots_5_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_imm_packed = _T_291 ? issue_slots_7_out_uop_imm_packed : _T_290 ? issue_slots_6_out_uop_imm_packed : issue_slots_5_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_pimm = _T_291 ? issue_slots_7_out_uop_pimm : _T_290 ? issue_slots_6_out_uop_pimm : issue_slots_5_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_imm_sel = _T_291 ? issue_slots_7_out_uop_imm_sel : _T_290 ? issue_slots_6_out_uop_imm_sel : issue_slots_5_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_imm_rename = _T_291 ? issue_slots_7_out_uop_imm_rename : _T_290 ? issue_slots_6_out_uop_imm_rename : issue_slots_5_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_taken = _T_291 ? issue_slots_7_out_uop_taken : _T_290 ? issue_slots_6_out_uop_taken : issue_slots_5_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_pc_lob = _T_291 ? issue_slots_7_out_uop_pc_lob : _T_290 ? issue_slots_6_out_uop_pc_lob : issue_slots_5_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_edge_inst = _T_291 ? issue_slots_7_out_uop_edge_inst : _T_290 ? issue_slots_6_out_uop_edge_inst : issue_slots_5_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_ftq_idx = _T_291 ? issue_slots_7_out_uop_ftq_idx : _T_290 ? issue_slots_6_out_uop_ftq_idx : issue_slots_5_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_mov = _T_291 ? issue_slots_7_out_uop_is_mov : _T_290 ? issue_slots_6_out_uop_is_mov : issue_slots_5_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_rocc = _T_291 ? issue_slots_7_out_uop_is_rocc : _T_290 ? issue_slots_6_out_uop_is_rocc : issue_slots_5_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_sys_pc2epc = _T_291 ? issue_slots_7_out_uop_is_sys_pc2epc : _T_290 ? issue_slots_6_out_uop_is_sys_pc2epc : issue_slots_5_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_eret = _T_291 ? issue_slots_7_out_uop_is_eret : _T_290 ? issue_slots_6_out_uop_is_eret : issue_slots_5_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_amo = _T_291 ? issue_slots_7_out_uop_is_amo : _T_290 ? issue_slots_6_out_uop_is_amo : issue_slots_5_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_sfence = _T_291 ? issue_slots_7_out_uop_is_sfence : _T_290 ? issue_slots_6_out_uop_is_sfence : issue_slots_5_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_fencei = _T_291 ? issue_slots_7_out_uop_is_fencei : _T_290 ? issue_slots_6_out_uop_is_fencei : issue_slots_5_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_fence = _T_291 ? issue_slots_7_out_uop_is_fence : _T_290 ? issue_slots_6_out_uop_is_fence : issue_slots_5_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_sfb = _T_291 ? issue_slots_7_out_uop_is_sfb : _T_290 ? issue_slots_6_out_uop_is_sfb : issue_slots_5_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_br_type = _T_291 ? issue_slots_7_out_uop_br_type : _T_290 ? issue_slots_6_out_uop_br_type : issue_slots_5_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_br_tag = _T_291 ? issue_slots_7_out_uop_br_tag : _T_290 ? issue_slots_6_out_uop_br_tag : issue_slots_5_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_br_mask = _T_291 ? issue_slots_7_out_uop_br_mask : _T_290 ? issue_slots_6_out_uop_br_mask : issue_slots_5_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_dis_col_sel = _T_291 ? issue_slots_7_out_uop_dis_col_sel : _T_290 ? issue_slots_6_out_uop_dis_col_sel : issue_slots_5_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iw_p3_bypass_hint = _T_291 ? issue_slots_7_out_uop_iw_p3_bypass_hint : _T_290 ? issue_slots_6_out_uop_iw_p3_bypass_hint : issue_slots_5_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iw_p2_bypass_hint = _T_291 ? issue_slots_7_out_uop_iw_p2_bypass_hint : _T_290 ? issue_slots_6_out_uop_iw_p2_bypass_hint : issue_slots_5_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iw_p1_bypass_hint = _T_291 ? issue_slots_7_out_uop_iw_p1_bypass_hint : _T_290 ? issue_slots_6_out_uop_iw_p1_bypass_hint : issue_slots_5_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iw_p2_speculative_child = _T_291 ? issue_slots_7_out_uop_iw_p2_speculative_child : _T_290 ? issue_slots_6_out_uop_iw_p2_speculative_child : issue_slots_5_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iw_p1_speculative_child = _T_291 ? issue_slots_7_out_uop_iw_p1_speculative_child : _T_290 ? issue_slots_6_out_uop_iw_p1_speculative_child : issue_slots_5_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iw_issued = _T_291 ? issue_slots_7_out_uop_iw_issued : _T_290 ? issue_slots_6_out_uop_iw_issued : issue_slots_5_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_0 = _T_291 ? issue_slots_7_out_uop_fu_code_0 : _T_290 ? issue_slots_6_out_uop_fu_code_0 : issue_slots_5_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_1 = _T_291 ? issue_slots_7_out_uop_fu_code_1 : _T_290 ? issue_slots_6_out_uop_fu_code_1 : issue_slots_5_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_2 = _T_291 ? issue_slots_7_out_uop_fu_code_2 : _T_290 ? issue_slots_6_out_uop_fu_code_2 : issue_slots_5_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_3 = _T_291 ? issue_slots_7_out_uop_fu_code_3 : _T_290 ? issue_slots_6_out_uop_fu_code_3 : issue_slots_5_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_4 = _T_291 ? issue_slots_7_out_uop_fu_code_4 : _T_290 ? issue_slots_6_out_uop_fu_code_4 : issue_slots_5_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_5 = _T_291 ? issue_slots_7_out_uop_fu_code_5 : _T_290 ? issue_slots_6_out_uop_fu_code_5 : issue_slots_5_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_6 = _T_291 ? issue_slots_7_out_uop_fu_code_6 : _T_290 ? issue_slots_6_out_uop_fu_code_6 : issue_slots_5_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_7 = _T_291 ? issue_slots_7_out_uop_fu_code_7 : _T_290 ? issue_slots_6_out_uop_fu_code_7 : issue_slots_5_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_8 = _T_291 ? issue_slots_7_out_uop_fu_code_8 : _T_290 ? issue_slots_6_out_uop_fu_code_8 : issue_slots_5_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_9 = _T_291 ? issue_slots_7_out_uop_fu_code_9 : _T_290 ? issue_slots_6_out_uop_fu_code_9 : issue_slots_5_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iq_type_0 = _T_291 ? issue_slots_7_out_uop_iq_type_0 : _T_290 ? issue_slots_6_out_uop_iq_type_0 : issue_slots_5_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iq_type_1 = _T_291 ? issue_slots_7_out_uop_iq_type_1 : _T_290 ? issue_slots_6_out_uop_iq_type_1 : issue_slots_5_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iq_type_2 = _T_291 ? issue_slots_7_out_uop_iq_type_2 : _T_290 ? issue_slots_6_out_uop_iq_type_2 : issue_slots_5_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iq_type_3 = _T_291 ? issue_slots_7_out_uop_iq_type_3 : _T_290 ? issue_slots_6_out_uop_iq_type_3 : issue_slots_5_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_debug_pc = _T_291 ? issue_slots_7_out_uop_debug_pc : _T_290 ? issue_slots_6_out_uop_debug_pc : issue_slots_5_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_rvc = _T_291 ? issue_slots_7_out_uop_is_rvc : _T_290 ? issue_slots_6_out_uop_is_rvc : issue_slots_5_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_debug_inst = _T_291 ? issue_slots_7_out_uop_debug_inst : _T_290 ? issue_slots_6_out_uop_debug_inst : issue_slots_5_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_inst = _T_291 ? issue_slots_7_out_uop_inst : _T_290 ? issue_slots_6_out_uop_inst : issue_slots_5_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_4_clear_T = |shamts_oh_4; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_4_clear = _issue_slots_4_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_293 = shamts_oh_7 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_294 = shamts_oh_8 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_5_in_uop_valid = _T_294 ? issue_slots_8_will_be_valid : _T_293 ? issue_slots_7_will_be_valid : shamts_oh_6 == 3'h1 & issue_slots_6_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_5_in_uop_bits_debug_tsrc = _T_294 ? issue_slots_8_out_uop_debug_tsrc : _T_293 ? issue_slots_7_out_uop_debug_tsrc : issue_slots_6_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_debug_fsrc = _T_294 ? issue_slots_8_out_uop_debug_fsrc : _T_293 ? issue_slots_7_out_uop_debug_fsrc : issue_slots_6_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_bp_xcpt_if = _T_294 ? issue_slots_8_out_uop_bp_xcpt_if : _T_293 ? issue_slots_7_out_uop_bp_xcpt_if : issue_slots_6_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_bp_debug_if = _T_294 ? issue_slots_8_out_uop_bp_debug_if : _T_293 ? issue_slots_7_out_uop_bp_debug_if : issue_slots_6_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_xcpt_ma_if = _T_294 ? issue_slots_8_out_uop_xcpt_ma_if : _T_293 ? issue_slots_7_out_uop_xcpt_ma_if : issue_slots_6_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_xcpt_ae_if = _T_294 ? issue_slots_8_out_uop_xcpt_ae_if : _T_293 ? issue_slots_7_out_uop_xcpt_ae_if : issue_slots_6_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_xcpt_pf_if = _T_294 ? issue_slots_8_out_uop_xcpt_pf_if : _T_293 ? issue_slots_7_out_uop_xcpt_pf_if : issue_slots_6_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_typ = _T_294 ? issue_slots_8_out_uop_fp_typ : _T_293 ? issue_slots_7_out_uop_fp_typ : issue_slots_6_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_rm = _T_294 ? issue_slots_8_out_uop_fp_rm : _T_293 ? issue_slots_7_out_uop_fp_rm : issue_slots_6_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_val = _T_294 ? issue_slots_8_out_uop_fp_val : _T_293 ? issue_slots_7_out_uop_fp_val : issue_slots_6_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fcn_op = _T_294 ? issue_slots_8_out_uop_fcn_op : _T_293 ? issue_slots_7_out_uop_fcn_op : issue_slots_6_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fcn_dw = _T_294 ? issue_slots_8_out_uop_fcn_dw : _T_293 ? issue_slots_7_out_uop_fcn_dw : issue_slots_6_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_frs3_en = _T_294 ? issue_slots_8_out_uop_frs3_en : _T_293 ? issue_slots_7_out_uop_frs3_en : issue_slots_6_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_lrs2_rtype = _T_294 ? issue_slots_8_out_uop_lrs2_rtype : _T_293 ? issue_slots_7_out_uop_lrs2_rtype : issue_slots_6_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_lrs1_rtype = _T_294 ? issue_slots_8_out_uop_lrs1_rtype : _T_293 ? issue_slots_7_out_uop_lrs1_rtype : issue_slots_6_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_dst_rtype = _T_294 ? issue_slots_8_out_uop_dst_rtype : _T_293 ? issue_slots_7_out_uop_dst_rtype : issue_slots_6_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_lrs3 = _T_294 ? issue_slots_8_out_uop_lrs3 : _T_293 ? issue_slots_7_out_uop_lrs3 : issue_slots_6_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_lrs2 = _T_294 ? issue_slots_8_out_uop_lrs2 : _T_293 ? issue_slots_7_out_uop_lrs2 : issue_slots_6_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_lrs1 = _T_294 ? issue_slots_8_out_uop_lrs1 : _T_293 ? issue_slots_7_out_uop_lrs1 : issue_slots_6_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_ldst = _T_294 ? issue_slots_8_out_uop_ldst : _T_293 ? issue_slots_7_out_uop_ldst : issue_slots_6_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_ldst_is_rs1 = _T_294 ? issue_slots_8_out_uop_ldst_is_rs1 : _T_293 ? issue_slots_7_out_uop_ldst_is_rs1 : issue_slots_6_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_csr_cmd = _T_294 ? issue_slots_8_out_uop_csr_cmd : _T_293 ? issue_slots_7_out_uop_csr_cmd : issue_slots_6_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_flush_on_commit = _T_294 ? issue_slots_8_out_uop_flush_on_commit : _T_293 ? issue_slots_7_out_uop_flush_on_commit : issue_slots_6_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_unique = _T_294 ? issue_slots_8_out_uop_is_unique : _T_293 ? issue_slots_7_out_uop_is_unique : issue_slots_6_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_uses_stq = _T_294 ? issue_slots_8_out_uop_uses_stq : _T_293 ? issue_slots_7_out_uop_uses_stq : issue_slots_6_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_uses_ldq = _T_294 ? issue_slots_8_out_uop_uses_ldq : _T_293 ? issue_slots_7_out_uop_uses_ldq : issue_slots_6_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_mem_signed = _T_294 ? issue_slots_8_out_uop_mem_signed : _T_293 ? issue_slots_7_out_uop_mem_signed : issue_slots_6_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_mem_size = _T_294 ? issue_slots_8_out_uop_mem_size : _T_293 ? issue_slots_7_out_uop_mem_size : issue_slots_6_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_mem_cmd = _T_294 ? issue_slots_8_out_uop_mem_cmd : _T_293 ? issue_slots_7_out_uop_mem_cmd : issue_slots_6_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_exc_cause = _T_294 ? issue_slots_8_out_uop_exc_cause : _T_293 ? issue_slots_7_out_uop_exc_cause : issue_slots_6_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_exception = _T_294 ? issue_slots_8_out_uop_exception : _T_293 ? issue_slots_7_out_uop_exception : issue_slots_6_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_stale_pdst = _T_294 ? issue_slots_8_out_uop_stale_pdst : _T_293 ? issue_slots_7_out_uop_stale_pdst : issue_slots_6_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_ppred_busy = _T_294 ? issue_slots_8_out_uop_ppred_busy : _T_293 ? issue_slots_7_out_uop_ppred_busy : issue_slots_6_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_prs3_busy = _T_294 ? issue_slots_8_out_uop_prs3_busy : _T_293 ? issue_slots_7_out_uop_prs3_busy : issue_slots_6_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_prs2_busy = _T_294 ? issue_slots_8_out_uop_prs2_busy : _T_293 ? issue_slots_7_out_uop_prs2_busy : issue_slots_6_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_prs1_busy = _T_294 ? issue_slots_8_out_uop_prs1_busy : _T_293 ? issue_slots_7_out_uop_prs1_busy : issue_slots_6_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_ppred = _T_294 ? issue_slots_8_out_uop_ppred : _T_293 ? issue_slots_7_out_uop_ppred : issue_slots_6_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_prs3 = _T_294 ? issue_slots_8_out_uop_prs3 : _T_293 ? issue_slots_7_out_uop_prs3 : issue_slots_6_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_prs2 = _T_294 ? issue_slots_8_out_uop_prs2 : _T_293 ? issue_slots_7_out_uop_prs2 : issue_slots_6_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_prs1 = _T_294 ? issue_slots_8_out_uop_prs1 : _T_293 ? issue_slots_7_out_uop_prs1 : issue_slots_6_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_pdst = _T_294 ? issue_slots_8_out_uop_pdst : _T_293 ? issue_slots_7_out_uop_pdst : issue_slots_6_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_rxq_idx = _T_294 ? issue_slots_8_out_uop_rxq_idx : _T_293 ? issue_slots_7_out_uop_rxq_idx : issue_slots_6_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_stq_idx = _T_294 ? issue_slots_8_out_uop_stq_idx : _T_293 ? issue_slots_7_out_uop_stq_idx : issue_slots_6_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_ldq_idx = _T_294 ? issue_slots_8_out_uop_ldq_idx : _T_293 ? issue_slots_7_out_uop_ldq_idx : issue_slots_6_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_rob_idx = _T_294 ? issue_slots_8_out_uop_rob_idx : _T_293 ? issue_slots_7_out_uop_rob_idx : issue_slots_6_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_vec = _T_294 ? issue_slots_8_out_uop_fp_ctrl_vec : _T_293 ? issue_slots_7_out_uop_fp_ctrl_vec : issue_slots_6_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_wflags = _T_294 ? issue_slots_8_out_uop_fp_ctrl_wflags : _T_293 ? issue_slots_7_out_uop_fp_ctrl_wflags : issue_slots_6_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_sqrt = _T_294 ? issue_slots_8_out_uop_fp_ctrl_sqrt : _T_293 ? issue_slots_7_out_uop_fp_ctrl_sqrt : issue_slots_6_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_div = _T_294 ? issue_slots_8_out_uop_fp_ctrl_div : _T_293 ? issue_slots_7_out_uop_fp_ctrl_div : issue_slots_6_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_fma = _T_294 ? issue_slots_8_out_uop_fp_ctrl_fma : _T_293 ? issue_slots_7_out_uop_fp_ctrl_fma : issue_slots_6_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_fastpipe = _T_294 ? issue_slots_8_out_uop_fp_ctrl_fastpipe : _T_293 ? issue_slots_7_out_uop_fp_ctrl_fastpipe : issue_slots_6_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_toint = _T_294 ? issue_slots_8_out_uop_fp_ctrl_toint : _T_293 ? issue_slots_7_out_uop_fp_ctrl_toint : issue_slots_6_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_fromint = _T_294 ? issue_slots_8_out_uop_fp_ctrl_fromint : _T_293 ? issue_slots_7_out_uop_fp_ctrl_fromint : issue_slots_6_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_typeTagOut = _T_294 ? issue_slots_8_out_uop_fp_ctrl_typeTagOut : _T_293 ? issue_slots_7_out_uop_fp_ctrl_typeTagOut : issue_slots_6_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_typeTagIn = _T_294 ? issue_slots_8_out_uop_fp_ctrl_typeTagIn : _T_293 ? issue_slots_7_out_uop_fp_ctrl_typeTagIn : issue_slots_6_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_swap23 = _T_294 ? issue_slots_8_out_uop_fp_ctrl_swap23 : _T_293 ? issue_slots_7_out_uop_fp_ctrl_swap23 : issue_slots_6_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_swap12 = _T_294 ? issue_slots_8_out_uop_fp_ctrl_swap12 : _T_293 ? issue_slots_7_out_uop_fp_ctrl_swap12 : issue_slots_6_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_ren3 = _T_294 ? issue_slots_8_out_uop_fp_ctrl_ren3 : _T_293 ? issue_slots_7_out_uop_fp_ctrl_ren3 : issue_slots_6_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_ren2 = _T_294 ? issue_slots_8_out_uop_fp_ctrl_ren2 : _T_293 ? issue_slots_7_out_uop_fp_ctrl_ren2 : issue_slots_6_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_ren1 = _T_294 ? issue_slots_8_out_uop_fp_ctrl_ren1 : _T_293 ? issue_slots_7_out_uop_fp_ctrl_ren1 : issue_slots_6_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_wen = _T_294 ? issue_slots_8_out_uop_fp_ctrl_wen : _T_293 ? issue_slots_7_out_uop_fp_ctrl_wen : issue_slots_6_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_ldst = _T_294 ? issue_slots_8_out_uop_fp_ctrl_ldst : _T_293 ? issue_slots_7_out_uop_fp_ctrl_ldst : issue_slots_6_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_op2_sel = _T_294 ? issue_slots_8_out_uop_op2_sel : _T_293 ? issue_slots_7_out_uop_op2_sel : issue_slots_6_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_op1_sel = _T_294 ? issue_slots_8_out_uop_op1_sel : _T_293 ? issue_slots_7_out_uop_op1_sel : issue_slots_6_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_imm_packed = _T_294 ? issue_slots_8_out_uop_imm_packed : _T_293 ? issue_slots_7_out_uop_imm_packed : issue_slots_6_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_pimm = _T_294 ? issue_slots_8_out_uop_pimm : _T_293 ? issue_slots_7_out_uop_pimm : issue_slots_6_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_imm_sel = _T_294 ? issue_slots_8_out_uop_imm_sel : _T_293 ? issue_slots_7_out_uop_imm_sel : issue_slots_6_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_imm_rename = _T_294 ? issue_slots_8_out_uop_imm_rename : _T_293 ? issue_slots_7_out_uop_imm_rename : issue_slots_6_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_taken = _T_294 ? issue_slots_8_out_uop_taken : _T_293 ? issue_slots_7_out_uop_taken : issue_slots_6_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_pc_lob = _T_294 ? issue_slots_8_out_uop_pc_lob : _T_293 ? issue_slots_7_out_uop_pc_lob : issue_slots_6_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_edge_inst = _T_294 ? issue_slots_8_out_uop_edge_inst : _T_293 ? issue_slots_7_out_uop_edge_inst : issue_slots_6_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_ftq_idx = _T_294 ? issue_slots_8_out_uop_ftq_idx : _T_293 ? issue_slots_7_out_uop_ftq_idx : issue_slots_6_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_mov = _T_294 ? issue_slots_8_out_uop_is_mov : _T_293 ? issue_slots_7_out_uop_is_mov : issue_slots_6_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_rocc = _T_294 ? issue_slots_8_out_uop_is_rocc : _T_293 ? issue_slots_7_out_uop_is_rocc : issue_slots_6_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_sys_pc2epc = _T_294 ? issue_slots_8_out_uop_is_sys_pc2epc : _T_293 ? issue_slots_7_out_uop_is_sys_pc2epc : issue_slots_6_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_eret = _T_294 ? issue_slots_8_out_uop_is_eret : _T_293 ? issue_slots_7_out_uop_is_eret : issue_slots_6_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_amo = _T_294 ? issue_slots_8_out_uop_is_amo : _T_293 ? issue_slots_7_out_uop_is_amo : issue_slots_6_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_sfence = _T_294 ? issue_slots_8_out_uop_is_sfence : _T_293 ? issue_slots_7_out_uop_is_sfence : issue_slots_6_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_fencei = _T_294 ? issue_slots_8_out_uop_is_fencei : _T_293 ? issue_slots_7_out_uop_is_fencei : issue_slots_6_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_fence = _T_294 ? issue_slots_8_out_uop_is_fence : _T_293 ? issue_slots_7_out_uop_is_fence : issue_slots_6_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_sfb = _T_294 ? issue_slots_8_out_uop_is_sfb : _T_293 ? issue_slots_7_out_uop_is_sfb : issue_slots_6_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_br_type = _T_294 ? issue_slots_8_out_uop_br_type : _T_293 ? issue_slots_7_out_uop_br_type : issue_slots_6_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_br_tag = _T_294 ? issue_slots_8_out_uop_br_tag : _T_293 ? issue_slots_7_out_uop_br_tag : issue_slots_6_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_br_mask = _T_294 ? issue_slots_8_out_uop_br_mask : _T_293 ? issue_slots_7_out_uop_br_mask : issue_slots_6_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_dis_col_sel = _T_294 ? issue_slots_8_out_uop_dis_col_sel : _T_293 ? issue_slots_7_out_uop_dis_col_sel : issue_slots_6_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iw_p3_bypass_hint = _T_294 ? issue_slots_8_out_uop_iw_p3_bypass_hint : _T_293 ? issue_slots_7_out_uop_iw_p3_bypass_hint : issue_slots_6_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iw_p2_bypass_hint = _T_294 ? issue_slots_8_out_uop_iw_p2_bypass_hint : _T_293 ? issue_slots_7_out_uop_iw_p2_bypass_hint : issue_slots_6_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iw_p1_bypass_hint = _T_294 ? issue_slots_8_out_uop_iw_p1_bypass_hint : _T_293 ? issue_slots_7_out_uop_iw_p1_bypass_hint : issue_slots_6_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iw_p2_speculative_child = _T_294 ? issue_slots_8_out_uop_iw_p2_speculative_child : _T_293 ? issue_slots_7_out_uop_iw_p2_speculative_child : issue_slots_6_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iw_p1_speculative_child = _T_294 ? issue_slots_8_out_uop_iw_p1_speculative_child : _T_293 ? issue_slots_7_out_uop_iw_p1_speculative_child : issue_slots_6_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iw_issued = _T_294 ? issue_slots_8_out_uop_iw_issued : _T_293 ? issue_slots_7_out_uop_iw_issued : issue_slots_6_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_0 = _T_294 ? issue_slots_8_out_uop_fu_code_0 : _T_293 ? issue_slots_7_out_uop_fu_code_0 : issue_slots_6_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_1 = _T_294 ? issue_slots_8_out_uop_fu_code_1 : _T_293 ? issue_slots_7_out_uop_fu_code_1 : issue_slots_6_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_2 = _T_294 ? issue_slots_8_out_uop_fu_code_2 : _T_293 ? issue_slots_7_out_uop_fu_code_2 : issue_slots_6_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_3 = _T_294 ? issue_slots_8_out_uop_fu_code_3 : _T_293 ? issue_slots_7_out_uop_fu_code_3 : issue_slots_6_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_4 = _T_294 ? issue_slots_8_out_uop_fu_code_4 : _T_293 ? issue_slots_7_out_uop_fu_code_4 : issue_slots_6_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_5 = _T_294 ? issue_slots_8_out_uop_fu_code_5 : _T_293 ? issue_slots_7_out_uop_fu_code_5 : issue_slots_6_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_6 = _T_294 ? issue_slots_8_out_uop_fu_code_6 : _T_293 ? issue_slots_7_out_uop_fu_code_6 : issue_slots_6_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_7 = _T_294 ? issue_slots_8_out_uop_fu_code_7 : _T_293 ? issue_slots_7_out_uop_fu_code_7 : issue_slots_6_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_8 = _T_294 ? issue_slots_8_out_uop_fu_code_8 : _T_293 ? issue_slots_7_out_uop_fu_code_8 : issue_slots_6_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_9 = _T_294 ? issue_slots_8_out_uop_fu_code_9 : _T_293 ? issue_slots_7_out_uop_fu_code_9 : issue_slots_6_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iq_type_0 = _T_294 ? issue_slots_8_out_uop_iq_type_0 : _T_293 ? issue_slots_7_out_uop_iq_type_0 : issue_slots_6_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iq_type_1 = _T_294 ? issue_slots_8_out_uop_iq_type_1 : _T_293 ? issue_slots_7_out_uop_iq_type_1 : issue_slots_6_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iq_type_2 = _T_294 ? issue_slots_8_out_uop_iq_type_2 : _T_293 ? issue_slots_7_out_uop_iq_type_2 : issue_slots_6_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iq_type_3 = _T_294 ? issue_slots_8_out_uop_iq_type_3 : _T_293 ? issue_slots_7_out_uop_iq_type_3 : issue_slots_6_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_debug_pc = _T_294 ? issue_slots_8_out_uop_debug_pc : _T_293 ? issue_slots_7_out_uop_debug_pc : issue_slots_6_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_rvc = _T_294 ? issue_slots_8_out_uop_is_rvc : _T_293 ? issue_slots_7_out_uop_is_rvc : issue_slots_6_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_debug_inst = _T_294 ? issue_slots_8_out_uop_debug_inst : _T_293 ? issue_slots_7_out_uop_debug_inst : issue_slots_6_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_inst = _T_294 ? issue_slots_8_out_uop_inst : _T_293 ? issue_slots_7_out_uop_inst : issue_slots_6_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_5_clear_T = |shamts_oh_5; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_5_clear = _issue_slots_5_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_296 = shamts_oh_8 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_297 = shamts_oh_9 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_6_in_uop_valid = _T_297 ? issue_slots_9_will_be_valid : _T_296 ? issue_slots_8_will_be_valid : shamts_oh_7 == 3'h1 & issue_slots_7_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_6_in_uop_bits_debug_tsrc = _T_297 ? issue_slots_9_out_uop_debug_tsrc : _T_296 ? issue_slots_8_out_uop_debug_tsrc : issue_slots_7_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_debug_fsrc = _T_297 ? issue_slots_9_out_uop_debug_fsrc : _T_296 ? issue_slots_8_out_uop_debug_fsrc : issue_slots_7_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_bp_xcpt_if = _T_297 ? issue_slots_9_out_uop_bp_xcpt_if : _T_296 ? issue_slots_8_out_uop_bp_xcpt_if : issue_slots_7_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_bp_debug_if = _T_297 ? issue_slots_9_out_uop_bp_debug_if : _T_296 ? issue_slots_8_out_uop_bp_debug_if : issue_slots_7_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_xcpt_ma_if = _T_297 ? issue_slots_9_out_uop_xcpt_ma_if : _T_296 ? issue_slots_8_out_uop_xcpt_ma_if : issue_slots_7_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_xcpt_ae_if = _T_297 ? issue_slots_9_out_uop_xcpt_ae_if : _T_296 ? issue_slots_8_out_uop_xcpt_ae_if : issue_slots_7_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_xcpt_pf_if = _T_297 ? issue_slots_9_out_uop_xcpt_pf_if : _T_296 ? issue_slots_8_out_uop_xcpt_pf_if : issue_slots_7_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_typ = _T_297 ? issue_slots_9_out_uop_fp_typ : _T_296 ? issue_slots_8_out_uop_fp_typ : issue_slots_7_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_rm = _T_297 ? issue_slots_9_out_uop_fp_rm : _T_296 ? issue_slots_8_out_uop_fp_rm : issue_slots_7_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_val = _T_297 ? issue_slots_9_out_uop_fp_val : _T_296 ? issue_slots_8_out_uop_fp_val : issue_slots_7_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fcn_op = _T_297 ? issue_slots_9_out_uop_fcn_op : _T_296 ? issue_slots_8_out_uop_fcn_op : issue_slots_7_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fcn_dw = _T_297 ? issue_slots_9_out_uop_fcn_dw : _T_296 ? issue_slots_8_out_uop_fcn_dw : issue_slots_7_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_frs3_en = _T_297 ? issue_slots_9_out_uop_frs3_en : _T_296 ? issue_slots_8_out_uop_frs3_en : issue_slots_7_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_lrs2_rtype = _T_297 ? issue_slots_9_out_uop_lrs2_rtype : _T_296 ? issue_slots_8_out_uop_lrs2_rtype : issue_slots_7_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_lrs1_rtype = _T_297 ? issue_slots_9_out_uop_lrs1_rtype : _T_296 ? issue_slots_8_out_uop_lrs1_rtype : issue_slots_7_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_dst_rtype = _T_297 ? issue_slots_9_out_uop_dst_rtype : _T_296 ? issue_slots_8_out_uop_dst_rtype : issue_slots_7_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_lrs3 = _T_297 ? issue_slots_9_out_uop_lrs3 : _T_296 ? issue_slots_8_out_uop_lrs3 : issue_slots_7_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_lrs2 = _T_297 ? issue_slots_9_out_uop_lrs2 : _T_296 ? issue_slots_8_out_uop_lrs2 : issue_slots_7_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_lrs1 = _T_297 ? issue_slots_9_out_uop_lrs1 : _T_296 ? issue_slots_8_out_uop_lrs1 : issue_slots_7_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_ldst = _T_297 ? issue_slots_9_out_uop_ldst : _T_296 ? issue_slots_8_out_uop_ldst : issue_slots_7_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_ldst_is_rs1 = _T_297 ? issue_slots_9_out_uop_ldst_is_rs1 : _T_296 ? issue_slots_8_out_uop_ldst_is_rs1 : issue_slots_7_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_csr_cmd = _T_297 ? issue_slots_9_out_uop_csr_cmd : _T_296 ? issue_slots_8_out_uop_csr_cmd : issue_slots_7_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_flush_on_commit = _T_297 ? issue_slots_9_out_uop_flush_on_commit : _T_296 ? issue_slots_8_out_uop_flush_on_commit : issue_slots_7_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_unique = _T_297 ? issue_slots_9_out_uop_is_unique : _T_296 ? issue_slots_8_out_uop_is_unique : issue_slots_7_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_uses_stq = _T_297 ? issue_slots_9_out_uop_uses_stq : _T_296 ? issue_slots_8_out_uop_uses_stq : issue_slots_7_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_uses_ldq = _T_297 ? issue_slots_9_out_uop_uses_ldq : _T_296 ? issue_slots_8_out_uop_uses_ldq : issue_slots_7_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_mem_signed = _T_297 ? issue_slots_9_out_uop_mem_signed : _T_296 ? issue_slots_8_out_uop_mem_signed : issue_slots_7_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_mem_size = _T_297 ? issue_slots_9_out_uop_mem_size : _T_296 ? issue_slots_8_out_uop_mem_size : issue_slots_7_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_mem_cmd = _T_297 ? issue_slots_9_out_uop_mem_cmd : _T_296 ? issue_slots_8_out_uop_mem_cmd : issue_slots_7_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_exc_cause = _T_297 ? issue_slots_9_out_uop_exc_cause : _T_296 ? issue_slots_8_out_uop_exc_cause : issue_slots_7_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_exception = _T_297 ? issue_slots_9_out_uop_exception : _T_296 ? issue_slots_8_out_uop_exception : issue_slots_7_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_stale_pdst = _T_297 ? issue_slots_9_out_uop_stale_pdst : _T_296 ? issue_slots_8_out_uop_stale_pdst : issue_slots_7_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_ppred_busy = _T_297 ? issue_slots_9_out_uop_ppred_busy : _T_296 ? issue_slots_8_out_uop_ppred_busy : issue_slots_7_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_prs3_busy = _T_297 ? issue_slots_9_out_uop_prs3_busy : _T_296 ? issue_slots_8_out_uop_prs3_busy : issue_slots_7_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_prs2_busy = _T_297 ? issue_slots_9_out_uop_prs2_busy : _T_296 ? issue_slots_8_out_uop_prs2_busy : issue_slots_7_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_prs1_busy = _T_297 ? issue_slots_9_out_uop_prs1_busy : _T_296 ? issue_slots_8_out_uop_prs1_busy : issue_slots_7_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_ppred = _T_297 ? issue_slots_9_out_uop_ppred : _T_296 ? issue_slots_8_out_uop_ppred : issue_slots_7_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_prs3 = _T_297 ? issue_slots_9_out_uop_prs3 : _T_296 ? issue_slots_8_out_uop_prs3 : issue_slots_7_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_prs2 = _T_297 ? issue_slots_9_out_uop_prs2 : _T_296 ? issue_slots_8_out_uop_prs2 : issue_slots_7_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_prs1 = _T_297 ? issue_slots_9_out_uop_prs1 : _T_296 ? issue_slots_8_out_uop_prs1 : issue_slots_7_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_pdst = _T_297 ? issue_slots_9_out_uop_pdst : _T_296 ? issue_slots_8_out_uop_pdst : issue_slots_7_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_rxq_idx = _T_297 ? issue_slots_9_out_uop_rxq_idx : _T_296 ? issue_slots_8_out_uop_rxq_idx : issue_slots_7_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_stq_idx = _T_297 ? issue_slots_9_out_uop_stq_idx : _T_296 ? issue_slots_8_out_uop_stq_idx : issue_slots_7_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_ldq_idx = _T_297 ? issue_slots_9_out_uop_ldq_idx : _T_296 ? issue_slots_8_out_uop_ldq_idx : issue_slots_7_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_rob_idx = _T_297 ? issue_slots_9_out_uop_rob_idx : _T_296 ? issue_slots_8_out_uop_rob_idx : issue_slots_7_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_vec = _T_297 ? issue_slots_9_out_uop_fp_ctrl_vec : _T_296 ? issue_slots_8_out_uop_fp_ctrl_vec : issue_slots_7_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_wflags = _T_297 ? issue_slots_9_out_uop_fp_ctrl_wflags : _T_296 ? issue_slots_8_out_uop_fp_ctrl_wflags : issue_slots_7_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_sqrt = _T_297 ? issue_slots_9_out_uop_fp_ctrl_sqrt : _T_296 ? issue_slots_8_out_uop_fp_ctrl_sqrt : issue_slots_7_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_div = _T_297 ? issue_slots_9_out_uop_fp_ctrl_div : _T_296 ? issue_slots_8_out_uop_fp_ctrl_div : issue_slots_7_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_fma = _T_297 ? issue_slots_9_out_uop_fp_ctrl_fma : _T_296 ? issue_slots_8_out_uop_fp_ctrl_fma : issue_slots_7_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_fastpipe = _T_297 ? issue_slots_9_out_uop_fp_ctrl_fastpipe : _T_296 ? issue_slots_8_out_uop_fp_ctrl_fastpipe : issue_slots_7_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_toint = _T_297 ? issue_slots_9_out_uop_fp_ctrl_toint : _T_296 ? issue_slots_8_out_uop_fp_ctrl_toint : issue_slots_7_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_fromint = _T_297 ? issue_slots_9_out_uop_fp_ctrl_fromint : _T_296 ? issue_slots_8_out_uop_fp_ctrl_fromint : issue_slots_7_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_typeTagOut = _T_297 ? issue_slots_9_out_uop_fp_ctrl_typeTagOut : _T_296 ? issue_slots_8_out_uop_fp_ctrl_typeTagOut : issue_slots_7_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_typeTagIn = _T_297 ? issue_slots_9_out_uop_fp_ctrl_typeTagIn : _T_296 ? issue_slots_8_out_uop_fp_ctrl_typeTagIn : issue_slots_7_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_swap23 = _T_297 ? issue_slots_9_out_uop_fp_ctrl_swap23 : _T_296 ? issue_slots_8_out_uop_fp_ctrl_swap23 : issue_slots_7_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_swap12 = _T_297 ? issue_slots_9_out_uop_fp_ctrl_swap12 : _T_296 ? issue_slots_8_out_uop_fp_ctrl_swap12 : issue_slots_7_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_ren3 = _T_297 ? issue_slots_9_out_uop_fp_ctrl_ren3 : _T_296 ? issue_slots_8_out_uop_fp_ctrl_ren3 : issue_slots_7_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_ren2 = _T_297 ? issue_slots_9_out_uop_fp_ctrl_ren2 : _T_296 ? issue_slots_8_out_uop_fp_ctrl_ren2 : issue_slots_7_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_ren1 = _T_297 ? issue_slots_9_out_uop_fp_ctrl_ren1 : _T_296 ? issue_slots_8_out_uop_fp_ctrl_ren1 : issue_slots_7_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_wen = _T_297 ? issue_slots_9_out_uop_fp_ctrl_wen : _T_296 ? issue_slots_8_out_uop_fp_ctrl_wen : issue_slots_7_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_ldst = _T_297 ? issue_slots_9_out_uop_fp_ctrl_ldst : _T_296 ? issue_slots_8_out_uop_fp_ctrl_ldst : issue_slots_7_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_op2_sel = _T_297 ? issue_slots_9_out_uop_op2_sel : _T_296 ? issue_slots_8_out_uop_op2_sel : issue_slots_7_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_op1_sel = _T_297 ? issue_slots_9_out_uop_op1_sel : _T_296 ? issue_slots_8_out_uop_op1_sel : issue_slots_7_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_imm_packed = _T_297 ? issue_slots_9_out_uop_imm_packed : _T_296 ? issue_slots_8_out_uop_imm_packed : issue_slots_7_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_pimm = _T_297 ? issue_slots_9_out_uop_pimm : _T_296 ? issue_slots_8_out_uop_pimm : issue_slots_7_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_imm_sel = _T_297 ? issue_slots_9_out_uop_imm_sel : _T_296 ? issue_slots_8_out_uop_imm_sel : issue_slots_7_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_imm_rename = _T_297 ? issue_slots_9_out_uop_imm_rename : _T_296 ? issue_slots_8_out_uop_imm_rename : issue_slots_7_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_taken = _T_297 ? issue_slots_9_out_uop_taken : _T_296 ? issue_slots_8_out_uop_taken : issue_slots_7_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_pc_lob = _T_297 ? issue_slots_9_out_uop_pc_lob : _T_296 ? issue_slots_8_out_uop_pc_lob : issue_slots_7_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_edge_inst = _T_297 ? issue_slots_9_out_uop_edge_inst : _T_296 ? issue_slots_8_out_uop_edge_inst : issue_slots_7_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_ftq_idx = _T_297 ? issue_slots_9_out_uop_ftq_idx : _T_296 ? issue_slots_8_out_uop_ftq_idx : issue_slots_7_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_mov = _T_297 ? issue_slots_9_out_uop_is_mov : _T_296 ? issue_slots_8_out_uop_is_mov : issue_slots_7_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_rocc = _T_297 ? issue_slots_9_out_uop_is_rocc : _T_296 ? issue_slots_8_out_uop_is_rocc : issue_slots_7_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_sys_pc2epc = _T_297 ? issue_slots_9_out_uop_is_sys_pc2epc : _T_296 ? issue_slots_8_out_uop_is_sys_pc2epc : issue_slots_7_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_eret = _T_297 ? issue_slots_9_out_uop_is_eret : _T_296 ? issue_slots_8_out_uop_is_eret : issue_slots_7_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_amo = _T_297 ? issue_slots_9_out_uop_is_amo : _T_296 ? issue_slots_8_out_uop_is_amo : issue_slots_7_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_sfence = _T_297 ? issue_slots_9_out_uop_is_sfence : _T_296 ? issue_slots_8_out_uop_is_sfence : issue_slots_7_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_fencei = _T_297 ? issue_slots_9_out_uop_is_fencei : _T_296 ? issue_slots_8_out_uop_is_fencei : issue_slots_7_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_fence = _T_297 ? issue_slots_9_out_uop_is_fence : _T_296 ? issue_slots_8_out_uop_is_fence : issue_slots_7_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_sfb = _T_297 ? issue_slots_9_out_uop_is_sfb : _T_296 ? issue_slots_8_out_uop_is_sfb : issue_slots_7_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_br_type = _T_297 ? issue_slots_9_out_uop_br_type : _T_296 ? issue_slots_8_out_uop_br_type : issue_slots_7_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_br_tag = _T_297 ? issue_slots_9_out_uop_br_tag : _T_296 ? issue_slots_8_out_uop_br_tag : issue_slots_7_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_br_mask = _T_297 ? issue_slots_9_out_uop_br_mask : _T_296 ? issue_slots_8_out_uop_br_mask : issue_slots_7_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_dis_col_sel = _T_297 ? issue_slots_9_out_uop_dis_col_sel : _T_296 ? issue_slots_8_out_uop_dis_col_sel : issue_slots_7_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iw_p3_bypass_hint = _T_297 ? issue_slots_9_out_uop_iw_p3_bypass_hint : _T_296 ? issue_slots_8_out_uop_iw_p3_bypass_hint : issue_slots_7_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iw_p2_bypass_hint = _T_297 ? issue_slots_9_out_uop_iw_p2_bypass_hint : _T_296 ? issue_slots_8_out_uop_iw_p2_bypass_hint : issue_slots_7_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iw_p1_bypass_hint = _T_297 ? issue_slots_9_out_uop_iw_p1_bypass_hint : _T_296 ? issue_slots_8_out_uop_iw_p1_bypass_hint : issue_slots_7_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iw_p2_speculative_child = _T_297 ? issue_slots_9_out_uop_iw_p2_speculative_child : _T_296 ? issue_slots_8_out_uop_iw_p2_speculative_child : issue_slots_7_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iw_p1_speculative_child = _T_297 ? issue_slots_9_out_uop_iw_p1_speculative_child : _T_296 ? issue_slots_8_out_uop_iw_p1_speculative_child : issue_slots_7_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iw_issued = _T_297 ? issue_slots_9_out_uop_iw_issued : _T_296 ? issue_slots_8_out_uop_iw_issued : issue_slots_7_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_0 = _T_297 ? issue_slots_9_out_uop_fu_code_0 : _T_296 ? issue_slots_8_out_uop_fu_code_0 : issue_slots_7_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_1 = _T_297 ? issue_slots_9_out_uop_fu_code_1 : _T_296 ? issue_slots_8_out_uop_fu_code_1 : issue_slots_7_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_2 = _T_297 ? issue_slots_9_out_uop_fu_code_2 : _T_296 ? issue_slots_8_out_uop_fu_code_2 : issue_slots_7_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_3 = _T_297 ? issue_slots_9_out_uop_fu_code_3 : _T_296 ? issue_slots_8_out_uop_fu_code_3 : issue_slots_7_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_4 = _T_297 ? issue_slots_9_out_uop_fu_code_4 : _T_296 ? issue_slots_8_out_uop_fu_code_4 : issue_slots_7_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_5 = _T_297 ? issue_slots_9_out_uop_fu_code_5 : _T_296 ? issue_slots_8_out_uop_fu_code_5 : issue_slots_7_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_6 = _T_297 ? issue_slots_9_out_uop_fu_code_6 : _T_296 ? issue_slots_8_out_uop_fu_code_6 : issue_slots_7_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_7 = _T_297 ? issue_slots_9_out_uop_fu_code_7 : _T_296 ? issue_slots_8_out_uop_fu_code_7 : issue_slots_7_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_8 = _T_297 ? issue_slots_9_out_uop_fu_code_8 : _T_296 ? issue_slots_8_out_uop_fu_code_8 : issue_slots_7_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_9 = _T_297 ? issue_slots_9_out_uop_fu_code_9 : _T_296 ? issue_slots_8_out_uop_fu_code_9 : issue_slots_7_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iq_type_0 = _T_297 ? issue_slots_9_out_uop_iq_type_0 : _T_296 ? issue_slots_8_out_uop_iq_type_0 : issue_slots_7_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iq_type_1 = _T_297 ? issue_slots_9_out_uop_iq_type_1 : _T_296 ? issue_slots_8_out_uop_iq_type_1 : issue_slots_7_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iq_type_2 = _T_297 ? issue_slots_9_out_uop_iq_type_2 : _T_296 ? issue_slots_8_out_uop_iq_type_2 : issue_slots_7_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iq_type_3 = _T_297 ? issue_slots_9_out_uop_iq_type_3 : _T_296 ? issue_slots_8_out_uop_iq_type_3 : issue_slots_7_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_debug_pc = _T_297 ? issue_slots_9_out_uop_debug_pc : _T_296 ? issue_slots_8_out_uop_debug_pc : issue_slots_7_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_rvc = _T_297 ? issue_slots_9_out_uop_is_rvc : _T_296 ? issue_slots_8_out_uop_is_rvc : issue_slots_7_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_debug_inst = _T_297 ? issue_slots_9_out_uop_debug_inst : _T_296 ? issue_slots_8_out_uop_debug_inst : issue_slots_7_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_inst = _T_297 ? issue_slots_9_out_uop_inst : _T_296 ? issue_slots_8_out_uop_inst : issue_slots_7_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_6_clear_T = |shamts_oh_6; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_6_clear = _issue_slots_6_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_299 = shamts_oh_9 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_300 = shamts_oh_10 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_7_in_uop_valid = _T_300 ? issue_slots_10_will_be_valid : _T_299 ? issue_slots_9_will_be_valid : shamts_oh_8 == 3'h1 & issue_slots_8_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_7_in_uop_bits_debug_tsrc = _T_300 ? issue_slots_10_out_uop_debug_tsrc : _T_299 ? issue_slots_9_out_uop_debug_tsrc : issue_slots_8_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_debug_fsrc = _T_300 ? issue_slots_10_out_uop_debug_fsrc : _T_299 ? issue_slots_9_out_uop_debug_fsrc : issue_slots_8_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_bp_xcpt_if = _T_300 ? issue_slots_10_out_uop_bp_xcpt_if : _T_299 ? issue_slots_9_out_uop_bp_xcpt_if : issue_slots_8_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_bp_debug_if = _T_300 ? issue_slots_10_out_uop_bp_debug_if : _T_299 ? issue_slots_9_out_uop_bp_debug_if : issue_slots_8_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_xcpt_ma_if = _T_300 ? issue_slots_10_out_uop_xcpt_ma_if : _T_299 ? issue_slots_9_out_uop_xcpt_ma_if : issue_slots_8_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_xcpt_ae_if = _T_300 ? issue_slots_10_out_uop_xcpt_ae_if : _T_299 ? issue_slots_9_out_uop_xcpt_ae_if : issue_slots_8_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_xcpt_pf_if = _T_300 ? issue_slots_10_out_uop_xcpt_pf_if : _T_299 ? issue_slots_9_out_uop_xcpt_pf_if : issue_slots_8_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_typ = _T_300 ? issue_slots_10_out_uop_fp_typ : _T_299 ? issue_slots_9_out_uop_fp_typ : issue_slots_8_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_rm = _T_300 ? issue_slots_10_out_uop_fp_rm : _T_299 ? issue_slots_9_out_uop_fp_rm : issue_slots_8_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_val = _T_300 ? issue_slots_10_out_uop_fp_val : _T_299 ? issue_slots_9_out_uop_fp_val : issue_slots_8_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fcn_op = _T_300 ? issue_slots_10_out_uop_fcn_op : _T_299 ? issue_slots_9_out_uop_fcn_op : issue_slots_8_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fcn_dw = _T_300 ? issue_slots_10_out_uop_fcn_dw : _T_299 ? issue_slots_9_out_uop_fcn_dw : issue_slots_8_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_frs3_en = _T_300 ? issue_slots_10_out_uop_frs3_en : _T_299 ? issue_slots_9_out_uop_frs3_en : issue_slots_8_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_lrs2_rtype = _T_300 ? issue_slots_10_out_uop_lrs2_rtype : _T_299 ? issue_slots_9_out_uop_lrs2_rtype : issue_slots_8_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_lrs1_rtype = _T_300 ? issue_slots_10_out_uop_lrs1_rtype : _T_299 ? issue_slots_9_out_uop_lrs1_rtype : issue_slots_8_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_dst_rtype = _T_300 ? issue_slots_10_out_uop_dst_rtype : _T_299 ? issue_slots_9_out_uop_dst_rtype : issue_slots_8_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_lrs3 = _T_300 ? issue_slots_10_out_uop_lrs3 : _T_299 ? issue_slots_9_out_uop_lrs3 : issue_slots_8_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_lrs2 = _T_300 ? issue_slots_10_out_uop_lrs2 : _T_299 ? issue_slots_9_out_uop_lrs2 : issue_slots_8_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_lrs1 = _T_300 ? issue_slots_10_out_uop_lrs1 : _T_299 ? issue_slots_9_out_uop_lrs1 : issue_slots_8_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_ldst = _T_300 ? issue_slots_10_out_uop_ldst : _T_299 ? issue_slots_9_out_uop_ldst : issue_slots_8_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_ldst_is_rs1 = _T_300 ? issue_slots_10_out_uop_ldst_is_rs1 : _T_299 ? issue_slots_9_out_uop_ldst_is_rs1 : issue_slots_8_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_csr_cmd = _T_300 ? issue_slots_10_out_uop_csr_cmd : _T_299 ? issue_slots_9_out_uop_csr_cmd : issue_slots_8_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_flush_on_commit = _T_300 ? issue_slots_10_out_uop_flush_on_commit : _T_299 ? issue_slots_9_out_uop_flush_on_commit : issue_slots_8_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_unique = _T_300 ? issue_slots_10_out_uop_is_unique : _T_299 ? issue_slots_9_out_uop_is_unique : issue_slots_8_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_uses_stq = _T_300 ? issue_slots_10_out_uop_uses_stq : _T_299 ? issue_slots_9_out_uop_uses_stq : issue_slots_8_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_uses_ldq = _T_300 ? issue_slots_10_out_uop_uses_ldq : _T_299 ? issue_slots_9_out_uop_uses_ldq : issue_slots_8_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_mem_signed = _T_300 ? issue_slots_10_out_uop_mem_signed : _T_299 ? issue_slots_9_out_uop_mem_signed : issue_slots_8_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_mem_size = _T_300 ? issue_slots_10_out_uop_mem_size : _T_299 ? issue_slots_9_out_uop_mem_size : issue_slots_8_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_mem_cmd = _T_300 ? issue_slots_10_out_uop_mem_cmd : _T_299 ? issue_slots_9_out_uop_mem_cmd : issue_slots_8_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_exc_cause = _T_300 ? issue_slots_10_out_uop_exc_cause : _T_299 ? issue_slots_9_out_uop_exc_cause : issue_slots_8_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_exception = _T_300 ? issue_slots_10_out_uop_exception : _T_299 ? issue_slots_9_out_uop_exception : issue_slots_8_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_stale_pdst = _T_300 ? issue_slots_10_out_uop_stale_pdst : _T_299 ? issue_slots_9_out_uop_stale_pdst : issue_slots_8_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_ppred_busy = _T_300 ? issue_slots_10_out_uop_ppred_busy : _T_299 ? issue_slots_9_out_uop_ppred_busy : issue_slots_8_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_prs3_busy = _T_300 ? issue_slots_10_out_uop_prs3_busy : _T_299 ? issue_slots_9_out_uop_prs3_busy : issue_slots_8_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_prs2_busy = _T_300 ? issue_slots_10_out_uop_prs2_busy : _T_299 ? issue_slots_9_out_uop_prs2_busy : issue_slots_8_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_prs1_busy = _T_300 ? issue_slots_10_out_uop_prs1_busy : _T_299 ? issue_slots_9_out_uop_prs1_busy : issue_slots_8_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_ppred = _T_300 ? issue_slots_10_out_uop_ppred : _T_299 ? issue_slots_9_out_uop_ppred : issue_slots_8_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_prs3 = _T_300 ? issue_slots_10_out_uop_prs3 : _T_299 ? issue_slots_9_out_uop_prs3 : issue_slots_8_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_prs2 = _T_300 ? issue_slots_10_out_uop_prs2 : _T_299 ? issue_slots_9_out_uop_prs2 : issue_slots_8_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_prs1 = _T_300 ? issue_slots_10_out_uop_prs1 : _T_299 ? issue_slots_9_out_uop_prs1 : issue_slots_8_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_pdst = _T_300 ? issue_slots_10_out_uop_pdst : _T_299 ? issue_slots_9_out_uop_pdst : issue_slots_8_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_rxq_idx = _T_300 ? issue_slots_10_out_uop_rxq_idx : _T_299 ? issue_slots_9_out_uop_rxq_idx : issue_slots_8_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_stq_idx = _T_300 ? issue_slots_10_out_uop_stq_idx : _T_299 ? issue_slots_9_out_uop_stq_idx : issue_slots_8_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_ldq_idx = _T_300 ? issue_slots_10_out_uop_ldq_idx : _T_299 ? issue_slots_9_out_uop_ldq_idx : issue_slots_8_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_rob_idx = _T_300 ? issue_slots_10_out_uop_rob_idx : _T_299 ? issue_slots_9_out_uop_rob_idx : issue_slots_8_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_vec = _T_300 ? issue_slots_10_out_uop_fp_ctrl_vec : _T_299 ? issue_slots_9_out_uop_fp_ctrl_vec : issue_slots_8_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_wflags = _T_300 ? issue_slots_10_out_uop_fp_ctrl_wflags : _T_299 ? issue_slots_9_out_uop_fp_ctrl_wflags : issue_slots_8_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_sqrt = _T_300 ? issue_slots_10_out_uop_fp_ctrl_sqrt : _T_299 ? issue_slots_9_out_uop_fp_ctrl_sqrt : issue_slots_8_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_div = _T_300 ? issue_slots_10_out_uop_fp_ctrl_div : _T_299 ? issue_slots_9_out_uop_fp_ctrl_div : issue_slots_8_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_fma = _T_300 ? issue_slots_10_out_uop_fp_ctrl_fma : _T_299 ? issue_slots_9_out_uop_fp_ctrl_fma : issue_slots_8_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_fastpipe = _T_300 ? issue_slots_10_out_uop_fp_ctrl_fastpipe : _T_299 ? issue_slots_9_out_uop_fp_ctrl_fastpipe : issue_slots_8_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_toint = _T_300 ? issue_slots_10_out_uop_fp_ctrl_toint : _T_299 ? issue_slots_9_out_uop_fp_ctrl_toint : issue_slots_8_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_fromint = _T_300 ? issue_slots_10_out_uop_fp_ctrl_fromint : _T_299 ? issue_slots_9_out_uop_fp_ctrl_fromint : issue_slots_8_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_typeTagOut = _T_300 ? issue_slots_10_out_uop_fp_ctrl_typeTagOut : _T_299 ? issue_slots_9_out_uop_fp_ctrl_typeTagOut : issue_slots_8_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_typeTagIn = _T_300 ? issue_slots_10_out_uop_fp_ctrl_typeTagIn : _T_299 ? issue_slots_9_out_uop_fp_ctrl_typeTagIn : issue_slots_8_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_swap23 = _T_300 ? issue_slots_10_out_uop_fp_ctrl_swap23 : _T_299 ? issue_slots_9_out_uop_fp_ctrl_swap23 : issue_slots_8_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_swap12 = _T_300 ? issue_slots_10_out_uop_fp_ctrl_swap12 : _T_299 ? issue_slots_9_out_uop_fp_ctrl_swap12 : issue_slots_8_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_ren3 = _T_300 ? issue_slots_10_out_uop_fp_ctrl_ren3 : _T_299 ? issue_slots_9_out_uop_fp_ctrl_ren3 : issue_slots_8_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_ren2 = _T_300 ? issue_slots_10_out_uop_fp_ctrl_ren2 : _T_299 ? issue_slots_9_out_uop_fp_ctrl_ren2 : issue_slots_8_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_ren1 = _T_300 ? issue_slots_10_out_uop_fp_ctrl_ren1 : _T_299 ? issue_slots_9_out_uop_fp_ctrl_ren1 : issue_slots_8_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_wen = _T_300 ? issue_slots_10_out_uop_fp_ctrl_wen : _T_299 ? issue_slots_9_out_uop_fp_ctrl_wen : issue_slots_8_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_ldst = _T_300 ? issue_slots_10_out_uop_fp_ctrl_ldst : _T_299 ? issue_slots_9_out_uop_fp_ctrl_ldst : issue_slots_8_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_op2_sel = _T_300 ? issue_slots_10_out_uop_op2_sel : _T_299 ? issue_slots_9_out_uop_op2_sel : issue_slots_8_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_op1_sel = _T_300 ? issue_slots_10_out_uop_op1_sel : _T_299 ? issue_slots_9_out_uop_op1_sel : issue_slots_8_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_imm_packed = _T_300 ? issue_slots_10_out_uop_imm_packed : _T_299 ? issue_slots_9_out_uop_imm_packed : issue_slots_8_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_pimm = _T_300 ? issue_slots_10_out_uop_pimm : _T_299 ? issue_slots_9_out_uop_pimm : issue_slots_8_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_imm_sel = _T_300 ? issue_slots_10_out_uop_imm_sel : _T_299 ? issue_slots_9_out_uop_imm_sel : issue_slots_8_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_imm_rename = _T_300 ? issue_slots_10_out_uop_imm_rename : _T_299 ? issue_slots_9_out_uop_imm_rename : issue_slots_8_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_taken = _T_300 ? issue_slots_10_out_uop_taken : _T_299 ? issue_slots_9_out_uop_taken : issue_slots_8_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_pc_lob = _T_300 ? issue_slots_10_out_uop_pc_lob : _T_299 ? issue_slots_9_out_uop_pc_lob : issue_slots_8_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_edge_inst = _T_300 ? issue_slots_10_out_uop_edge_inst : _T_299 ? issue_slots_9_out_uop_edge_inst : issue_slots_8_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_ftq_idx = _T_300 ? issue_slots_10_out_uop_ftq_idx : _T_299 ? issue_slots_9_out_uop_ftq_idx : issue_slots_8_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_mov = _T_300 ? issue_slots_10_out_uop_is_mov : _T_299 ? issue_slots_9_out_uop_is_mov : issue_slots_8_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_rocc = _T_300 ? issue_slots_10_out_uop_is_rocc : _T_299 ? issue_slots_9_out_uop_is_rocc : issue_slots_8_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_sys_pc2epc = _T_300 ? issue_slots_10_out_uop_is_sys_pc2epc : _T_299 ? issue_slots_9_out_uop_is_sys_pc2epc : issue_slots_8_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_eret = _T_300 ? issue_slots_10_out_uop_is_eret : _T_299 ? issue_slots_9_out_uop_is_eret : issue_slots_8_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_amo = _T_300 ? issue_slots_10_out_uop_is_amo : _T_299 ? issue_slots_9_out_uop_is_amo : issue_slots_8_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_sfence = _T_300 ? issue_slots_10_out_uop_is_sfence : _T_299 ? issue_slots_9_out_uop_is_sfence : issue_slots_8_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_fencei = _T_300 ? issue_slots_10_out_uop_is_fencei : _T_299 ? issue_slots_9_out_uop_is_fencei : issue_slots_8_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_fence = _T_300 ? issue_slots_10_out_uop_is_fence : _T_299 ? issue_slots_9_out_uop_is_fence : issue_slots_8_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_sfb = _T_300 ? issue_slots_10_out_uop_is_sfb : _T_299 ? issue_slots_9_out_uop_is_sfb : issue_slots_8_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_br_type = _T_300 ? issue_slots_10_out_uop_br_type : _T_299 ? issue_slots_9_out_uop_br_type : issue_slots_8_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_br_tag = _T_300 ? issue_slots_10_out_uop_br_tag : _T_299 ? issue_slots_9_out_uop_br_tag : issue_slots_8_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_br_mask = _T_300 ? issue_slots_10_out_uop_br_mask : _T_299 ? issue_slots_9_out_uop_br_mask : issue_slots_8_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_dis_col_sel = _T_300 ? issue_slots_10_out_uop_dis_col_sel : _T_299 ? issue_slots_9_out_uop_dis_col_sel : issue_slots_8_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iw_p3_bypass_hint = _T_300 ? issue_slots_10_out_uop_iw_p3_bypass_hint : _T_299 ? issue_slots_9_out_uop_iw_p3_bypass_hint : issue_slots_8_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iw_p2_bypass_hint = _T_300 ? issue_slots_10_out_uop_iw_p2_bypass_hint : _T_299 ? issue_slots_9_out_uop_iw_p2_bypass_hint : issue_slots_8_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iw_p1_bypass_hint = _T_300 ? issue_slots_10_out_uop_iw_p1_bypass_hint : _T_299 ? issue_slots_9_out_uop_iw_p1_bypass_hint : issue_slots_8_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iw_p2_speculative_child = _T_300 ? issue_slots_10_out_uop_iw_p2_speculative_child : _T_299 ? issue_slots_9_out_uop_iw_p2_speculative_child : issue_slots_8_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iw_p1_speculative_child = _T_300 ? issue_slots_10_out_uop_iw_p1_speculative_child : _T_299 ? issue_slots_9_out_uop_iw_p1_speculative_child : issue_slots_8_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iw_issued = _T_300 ? issue_slots_10_out_uop_iw_issued : _T_299 ? issue_slots_9_out_uop_iw_issued : issue_slots_8_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_0 = _T_300 ? issue_slots_10_out_uop_fu_code_0 : _T_299 ? issue_slots_9_out_uop_fu_code_0 : issue_slots_8_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_1 = _T_300 ? issue_slots_10_out_uop_fu_code_1 : _T_299 ? issue_slots_9_out_uop_fu_code_1 : issue_slots_8_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_2 = _T_300 ? issue_slots_10_out_uop_fu_code_2 : _T_299 ? issue_slots_9_out_uop_fu_code_2 : issue_slots_8_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_3 = _T_300 ? issue_slots_10_out_uop_fu_code_3 : _T_299 ? issue_slots_9_out_uop_fu_code_3 : issue_slots_8_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_4 = _T_300 ? issue_slots_10_out_uop_fu_code_4 : _T_299 ? issue_slots_9_out_uop_fu_code_4 : issue_slots_8_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_5 = _T_300 ? issue_slots_10_out_uop_fu_code_5 : _T_299 ? issue_slots_9_out_uop_fu_code_5 : issue_slots_8_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_6 = _T_300 ? issue_slots_10_out_uop_fu_code_6 : _T_299 ? issue_slots_9_out_uop_fu_code_6 : issue_slots_8_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_7 = _T_300 ? issue_slots_10_out_uop_fu_code_7 : _T_299 ? issue_slots_9_out_uop_fu_code_7 : issue_slots_8_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_8 = _T_300 ? issue_slots_10_out_uop_fu_code_8 : _T_299 ? issue_slots_9_out_uop_fu_code_8 : issue_slots_8_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_9 = _T_300 ? issue_slots_10_out_uop_fu_code_9 : _T_299 ? issue_slots_9_out_uop_fu_code_9 : issue_slots_8_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iq_type_0 = _T_300 ? issue_slots_10_out_uop_iq_type_0 : _T_299 ? issue_slots_9_out_uop_iq_type_0 : issue_slots_8_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iq_type_1 = _T_300 ? issue_slots_10_out_uop_iq_type_1 : _T_299 ? issue_slots_9_out_uop_iq_type_1 : issue_slots_8_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iq_type_2 = _T_300 ? issue_slots_10_out_uop_iq_type_2 : _T_299 ? issue_slots_9_out_uop_iq_type_2 : issue_slots_8_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iq_type_3 = _T_300 ? issue_slots_10_out_uop_iq_type_3 : _T_299 ? issue_slots_9_out_uop_iq_type_3 : issue_slots_8_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_debug_pc = _T_300 ? issue_slots_10_out_uop_debug_pc : _T_299 ? issue_slots_9_out_uop_debug_pc : issue_slots_8_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_rvc = _T_300 ? issue_slots_10_out_uop_is_rvc : _T_299 ? issue_slots_9_out_uop_is_rvc : issue_slots_8_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_debug_inst = _T_300 ? issue_slots_10_out_uop_debug_inst : _T_299 ? issue_slots_9_out_uop_debug_inst : issue_slots_8_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_inst = _T_300 ? issue_slots_10_out_uop_inst : _T_299 ? issue_slots_9_out_uop_inst : issue_slots_8_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_7_clear_T = |shamts_oh_7; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_7_clear = _issue_slots_7_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_302 = shamts_oh_10 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_303 = shamts_oh_11 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_8_in_uop_valid = _T_303 ? issue_slots_11_will_be_valid : _T_302 ? issue_slots_10_will_be_valid : shamts_oh_9 == 3'h1 & issue_slots_9_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_8_in_uop_bits_debug_tsrc = _T_303 ? issue_slots_11_out_uop_debug_tsrc : _T_302 ? issue_slots_10_out_uop_debug_tsrc : issue_slots_9_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_debug_fsrc = _T_303 ? issue_slots_11_out_uop_debug_fsrc : _T_302 ? issue_slots_10_out_uop_debug_fsrc : issue_slots_9_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_bp_xcpt_if = _T_303 ? issue_slots_11_out_uop_bp_xcpt_if : _T_302 ? issue_slots_10_out_uop_bp_xcpt_if : issue_slots_9_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_bp_debug_if = _T_303 ? issue_slots_11_out_uop_bp_debug_if : _T_302 ? issue_slots_10_out_uop_bp_debug_if : issue_slots_9_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_xcpt_ma_if = _T_303 ? issue_slots_11_out_uop_xcpt_ma_if : _T_302 ? issue_slots_10_out_uop_xcpt_ma_if : issue_slots_9_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_xcpt_ae_if = _T_303 ? issue_slots_11_out_uop_xcpt_ae_if : _T_302 ? issue_slots_10_out_uop_xcpt_ae_if : issue_slots_9_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_xcpt_pf_if = _T_303 ? issue_slots_11_out_uop_xcpt_pf_if : _T_302 ? issue_slots_10_out_uop_xcpt_pf_if : issue_slots_9_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_typ = _T_303 ? issue_slots_11_out_uop_fp_typ : _T_302 ? issue_slots_10_out_uop_fp_typ : issue_slots_9_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_rm = _T_303 ? issue_slots_11_out_uop_fp_rm : _T_302 ? issue_slots_10_out_uop_fp_rm : issue_slots_9_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_val = _T_303 ? issue_slots_11_out_uop_fp_val : _T_302 ? issue_slots_10_out_uop_fp_val : issue_slots_9_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fcn_op = _T_303 ? issue_slots_11_out_uop_fcn_op : _T_302 ? issue_slots_10_out_uop_fcn_op : issue_slots_9_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fcn_dw = _T_303 ? issue_slots_11_out_uop_fcn_dw : _T_302 ? issue_slots_10_out_uop_fcn_dw : issue_slots_9_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_frs3_en = _T_303 ? issue_slots_11_out_uop_frs3_en : _T_302 ? issue_slots_10_out_uop_frs3_en : issue_slots_9_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_lrs2_rtype = _T_303 ? issue_slots_11_out_uop_lrs2_rtype : _T_302 ? issue_slots_10_out_uop_lrs2_rtype : issue_slots_9_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_lrs1_rtype = _T_303 ? issue_slots_11_out_uop_lrs1_rtype : _T_302 ? issue_slots_10_out_uop_lrs1_rtype : issue_slots_9_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_dst_rtype = _T_303 ? issue_slots_11_out_uop_dst_rtype : _T_302 ? issue_slots_10_out_uop_dst_rtype : issue_slots_9_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_lrs3 = _T_303 ? issue_slots_11_out_uop_lrs3 : _T_302 ? issue_slots_10_out_uop_lrs3 : issue_slots_9_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_lrs2 = _T_303 ? issue_slots_11_out_uop_lrs2 : _T_302 ? issue_slots_10_out_uop_lrs2 : issue_slots_9_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_lrs1 = _T_303 ? issue_slots_11_out_uop_lrs1 : _T_302 ? issue_slots_10_out_uop_lrs1 : issue_slots_9_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_ldst = _T_303 ? issue_slots_11_out_uop_ldst : _T_302 ? issue_slots_10_out_uop_ldst : issue_slots_9_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_ldst_is_rs1 = _T_303 ? issue_slots_11_out_uop_ldst_is_rs1 : _T_302 ? issue_slots_10_out_uop_ldst_is_rs1 : issue_slots_9_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_csr_cmd = _T_303 ? issue_slots_11_out_uop_csr_cmd : _T_302 ? issue_slots_10_out_uop_csr_cmd : issue_slots_9_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_flush_on_commit = _T_303 ? issue_slots_11_out_uop_flush_on_commit : _T_302 ? issue_slots_10_out_uop_flush_on_commit : issue_slots_9_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_unique = _T_303 ? issue_slots_11_out_uop_is_unique : _T_302 ? issue_slots_10_out_uop_is_unique : issue_slots_9_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_uses_stq = _T_303 ? issue_slots_11_out_uop_uses_stq : _T_302 ? issue_slots_10_out_uop_uses_stq : issue_slots_9_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_uses_ldq = _T_303 ? issue_slots_11_out_uop_uses_ldq : _T_302 ? issue_slots_10_out_uop_uses_ldq : issue_slots_9_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_mem_signed = _T_303 ? issue_slots_11_out_uop_mem_signed : _T_302 ? issue_slots_10_out_uop_mem_signed : issue_slots_9_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_mem_size = _T_303 ? issue_slots_11_out_uop_mem_size : _T_302 ? issue_slots_10_out_uop_mem_size : issue_slots_9_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_mem_cmd = _T_303 ? issue_slots_11_out_uop_mem_cmd : _T_302 ? issue_slots_10_out_uop_mem_cmd : issue_slots_9_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_exc_cause = _T_303 ? issue_slots_11_out_uop_exc_cause : _T_302 ? issue_slots_10_out_uop_exc_cause : issue_slots_9_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_exception = _T_303 ? issue_slots_11_out_uop_exception : _T_302 ? issue_slots_10_out_uop_exception : issue_slots_9_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_stale_pdst = _T_303 ? issue_slots_11_out_uop_stale_pdst : _T_302 ? issue_slots_10_out_uop_stale_pdst : issue_slots_9_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_ppred_busy = _T_303 ? issue_slots_11_out_uop_ppred_busy : _T_302 ? issue_slots_10_out_uop_ppred_busy : issue_slots_9_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_prs3_busy = _T_303 ? issue_slots_11_out_uop_prs3_busy : _T_302 ? issue_slots_10_out_uop_prs3_busy : issue_slots_9_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_prs2_busy = _T_303 ? issue_slots_11_out_uop_prs2_busy : _T_302 ? issue_slots_10_out_uop_prs2_busy : issue_slots_9_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_prs1_busy = _T_303 ? issue_slots_11_out_uop_prs1_busy : _T_302 ? issue_slots_10_out_uop_prs1_busy : issue_slots_9_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_ppred = _T_303 ? issue_slots_11_out_uop_ppred : _T_302 ? issue_slots_10_out_uop_ppred : issue_slots_9_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_prs3 = _T_303 ? issue_slots_11_out_uop_prs3 : _T_302 ? issue_slots_10_out_uop_prs3 : issue_slots_9_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_prs2 = _T_303 ? issue_slots_11_out_uop_prs2 : _T_302 ? issue_slots_10_out_uop_prs2 : issue_slots_9_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_prs1 = _T_303 ? issue_slots_11_out_uop_prs1 : _T_302 ? issue_slots_10_out_uop_prs1 : issue_slots_9_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_pdst = _T_303 ? issue_slots_11_out_uop_pdst : _T_302 ? issue_slots_10_out_uop_pdst : issue_slots_9_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_rxq_idx = _T_303 ? issue_slots_11_out_uop_rxq_idx : _T_302 ? issue_slots_10_out_uop_rxq_idx : issue_slots_9_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_stq_idx = _T_303 ? issue_slots_11_out_uop_stq_idx : _T_302 ? issue_slots_10_out_uop_stq_idx : issue_slots_9_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_ldq_idx = _T_303 ? issue_slots_11_out_uop_ldq_idx : _T_302 ? issue_slots_10_out_uop_ldq_idx : issue_slots_9_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_rob_idx = _T_303 ? issue_slots_11_out_uop_rob_idx : _T_302 ? issue_slots_10_out_uop_rob_idx : issue_slots_9_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_vec = _T_303 ? issue_slots_11_out_uop_fp_ctrl_vec : _T_302 ? issue_slots_10_out_uop_fp_ctrl_vec : issue_slots_9_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_wflags = _T_303 ? issue_slots_11_out_uop_fp_ctrl_wflags : _T_302 ? issue_slots_10_out_uop_fp_ctrl_wflags : issue_slots_9_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_sqrt = _T_303 ? issue_slots_11_out_uop_fp_ctrl_sqrt : _T_302 ? issue_slots_10_out_uop_fp_ctrl_sqrt : issue_slots_9_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_div = _T_303 ? issue_slots_11_out_uop_fp_ctrl_div : _T_302 ? issue_slots_10_out_uop_fp_ctrl_div : issue_slots_9_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_fma = _T_303 ? issue_slots_11_out_uop_fp_ctrl_fma : _T_302 ? issue_slots_10_out_uop_fp_ctrl_fma : issue_slots_9_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_fastpipe = _T_303 ? issue_slots_11_out_uop_fp_ctrl_fastpipe : _T_302 ? issue_slots_10_out_uop_fp_ctrl_fastpipe : issue_slots_9_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_toint = _T_303 ? issue_slots_11_out_uop_fp_ctrl_toint : _T_302 ? issue_slots_10_out_uop_fp_ctrl_toint : issue_slots_9_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_fromint = _T_303 ? issue_slots_11_out_uop_fp_ctrl_fromint : _T_302 ? issue_slots_10_out_uop_fp_ctrl_fromint : issue_slots_9_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_typeTagOut = _T_303 ? issue_slots_11_out_uop_fp_ctrl_typeTagOut : _T_302 ? issue_slots_10_out_uop_fp_ctrl_typeTagOut : issue_slots_9_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_typeTagIn = _T_303 ? issue_slots_11_out_uop_fp_ctrl_typeTagIn : _T_302 ? issue_slots_10_out_uop_fp_ctrl_typeTagIn : issue_slots_9_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_swap23 = _T_303 ? issue_slots_11_out_uop_fp_ctrl_swap23 : _T_302 ? issue_slots_10_out_uop_fp_ctrl_swap23 : issue_slots_9_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_swap12 = _T_303 ? issue_slots_11_out_uop_fp_ctrl_swap12 : _T_302 ? issue_slots_10_out_uop_fp_ctrl_swap12 : issue_slots_9_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_ren3 = _T_303 ? issue_slots_11_out_uop_fp_ctrl_ren3 : _T_302 ? issue_slots_10_out_uop_fp_ctrl_ren3 : issue_slots_9_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_ren2 = _T_303 ? issue_slots_11_out_uop_fp_ctrl_ren2 : _T_302 ? issue_slots_10_out_uop_fp_ctrl_ren2 : issue_slots_9_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_ren1 = _T_303 ? issue_slots_11_out_uop_fp_ctrl_ren1 : _T_302 ? issue_slots_10_out_uop_fp_ctrl_ren1 : issue_slots_9_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_wen = _T_303 ? issue_slots_11_out_uop_fp_ctrl_wen : _T_302 ? issue_slots_10_out_uop_fp_ctrl_wen : issue_slots_9_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_ldst = _T_303 ? issue_slots_11_out_uop_fp_ctrl_ldst : _T_302 ? issue_slots_10_out_uop_fp_ctrl_ldst : issue_slots_9_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_op2_sel = _T_303 ? issue_slots_11_out_uop_op2_sel : _T_302 ? issue_slots_10_out_uop_op2_sel : issue_slots_9_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_op1_sel = _T_303 ? issue_slots_11_out_uop_op1_sel : _T_302 ? issue_slots_10_out_uop_op1_sel : issue_slots_9_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_imm_packed = _T_303 ? issue_slots_11_out_uop_imm_packed : _T_302 ? issue_slots_10_out_uop_imm_packed : issue_slots_9_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_pimm = _T_303 ? issue_slots_11_out_uop_pimm : _T_302 ? issue_slots_10_out_uop_pimm : issue_slots_9_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_imm_sel = _T_303 ? issue_slots_11_out_uop_imm_sel : _T_302 ? issue_slots_10_out_uop_imm_sel : issue_slots_9_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_imm_rename = _T_303 ? issue_slots_11_out_uop_imm_rename : _T_302 ? issue_slots_10_out_uop_imm_rename : issue_slots_9_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_taken = _T_303 ? issue_slots_11_out_uop_taken : _T_302 ? issue_slots_10_out_uop_taken : issue_slots_9_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_pc_lob = _T_303 ? issue_slots_11_out_uop_pc_lob : _T_302 ? issue_slots_10_out_uop_pc_lob : issue_slots_9_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_edge_inst = _T_303 ? issue_slots_11_out_uop_edge_inst : _T_302 ? issue_slots_10_out_uop_edge_inst : issue_slots_9_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_ftq_idx = _T_303 ? issue_slots_11_out_uop_ftq_idx : _T_302 ? issue_slots_10_out_uop_ftq_idx : issue_slots_9_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_mov = _T_303 ? issue_slots_11_out_uop_is_mov : _T_302 ? issue_slots_10_out_uop_is_mov : issue_slots_9_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_rocc = _T_303 ? issue_slots_11_out_uop_is_rocc : _T_302 ? issue_slots_10_out_uop_is_rocc : issue_slots_9_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_sys_pc2epc = _T_303 ? issue_slots_11_out_uop_is_sys_pc2epc : _T_302 ? issue_slots_10_out_uop_is_sys_pc2epc : issue_slots_9_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_eret = _T_303 ? issue_slots_11_out_uop_is_eret : _T_302 ? issue_slots_10_out_uop_is_eret : issue_slots_9_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_amo = _T_303 ? issue_slots_11_out_uop_is_amo : _T_302 ? issue_slots_10_out_uop_is_amo : issue_slots_9_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_sfence = _T_303 ? issue_slots_11_out_uop_is_sfence : _T_302 ? issue_slots_10_out_uop_is_sfence : issue_slots_9_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_fencei = _T_303 ? issue_slots_11_out_uop_is_fencei : _T_302 ? issue_slots_10_out_uop_is_fencei : issue_slots_9_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_fence = _T_303 ? issue_slots_11_out_uop_is_fence : _T_302 ? issue_slots_10_out_uop_is_fence : issue_slots_9_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_sfb = _T_303 ? issue_slots_11_out_uop_is_sfb : _T_302 ? issue_slots_10_out_uop_is_sfb : issue_slots_9_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_br_type = _T_303 ? issue_slots_11_out_uop_br_type : _T_302 ? issue_slots_10_out_uop_br_type : issue_slots_9_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_br_tag = _T_303 ? issue_slots_11_out_uop_br_tag : _T_302 ? issue_slots_10_out_uop_br_tag : issue_slots_9_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_br_mask = _T_303 ? issue_slots_11_out_uop_br_mask : _T_302 ? issue_slots_10_out_uop_br_mask : issue_slots_9_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_dis_col_sel = _T_303 ? issue_slots_11_out_uop_dis_col_sel : _T_302 ? issue_slots_10_out_uop_dis_col_sel : issue_slots_9_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iw_p3_bypass_hint = _T_303 ? issue_slots_11_out_uop_iw_p3_bypass_hint : _T_302 ? issue_slots_10_out_uop_iw_p3_bypass_hint : issue_slots_9_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iw_p2_bypass_hint = _T_303 ? issue_slots_11_out_uop_iw_p2_bypass_hint : _T_302 ? issue_slots_10_out_uop_iw_p2_bypass_hint : issue_slots_9_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iw_p1_bypass_hint = _T_303 ? issue_slots_11_out_uop_iw_p1_bypass_hint : _T_302 ? issue_slots_10_out_uop_iw_p1_bypass_hint : issue_slots_9_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iw_p2_speculative_child = _T_303 ? issue_slots_11_out_uop_iw_p2_speculative_child : _T_302 ? issue_slots_10_out_uop_iw_p2_speculative_child : issue_slots_9_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iw_p1_speculative_child = _T_303 ? issue_slots_11_out_uop_iw_p1_speculative_child : _T_302 ? issue_slots_10_out_uop_iw_p1_speculative_child : issue_slots_9_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iw_issued = _T_303 ? issue_slots_11_out_uop_iw_issued : _T_302 ? issue_slots_10_out_uop_iw_issued : issue_slots_9_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_0 = _T_303 ? issue_slots_11_out_uop_fu_code_0 : _T_302 ? issue_slots_10_out_uop_fu_code_0 : issue_slots_9_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_1 = _T_303 ? issue_slots_11_out_uop_fu_code_1 : _T_302 ? issue_slots_10_out_uop_fu_code_1 : issue_slots_9_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_2 = _T_303 ? issue_slots_11_out_uop_fu_code_2 : _T_302 ? issue_slots_10_out_uop_fu_code_2 : issue_slots_9_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_3 = _T_303 ? issue_slots_11_out_uop_fu_code_3 : _T_302 ? issue_slots_10_out_uop_fu_code_3 : issue_slots_9_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_4 = _T_303 ? issue_slots_11_out_uop_fu_code_4 : _T_302 ? issue_slots_10_out_uop_fu_code_4 : issue_slots_9_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_5 = _T_303 ? issue_slots_11_out_uop_fu_code_5 : _T_302 ? issue_slots_10_out_uop_fu_code_5 : issue_slots_9_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_6 = _T_303 ? issue_slots_11_out_uop_fu_code_6 : _T_302 ? issue_slots_10_out_uop_fu_code_6 : issue_slots_9_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_7 = _T_303 ? issue_slots_11_out_uop_fu_code_7 : _T_302 ? issue_slots_10_out_uop_fu_code_7 : issue_slots_9_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_8 = _T_303 ? issue_slots_11_out_uop_fu_code_8 : _T_302 ? issue_slots_10_out_uop_fu_code_8 : issue_slots_9_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_9 = _T_303 ? issue_slots_11_out_uop_fu_code_9 : _T_302 ? issue_slots_10_out_uop_fu_code_9 : issue_slots_9_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iq_type_0 = _T_303 ? issue_slots_11_out_uop_iq_type_0 : _T_302 ? issue_slots_10_out_uop_iq_type_0 : issue_slots_9_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iq_type_1 = _T_303 ? issue_slots_11_out_uop_iq_type_1 : _T_302 ? issue_slots_10_out_uop_iq_type_1 : issue_slots_9_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iq_type_2 = _T_303 ? issue_slots_11_out_uop_iq_type_2 : _T_302 ? issue_slots_10_out_uop_iq_type_2 : issue_slots_9_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iq_type_3 = _T_303 ? issue_slots_11_out_uop_iq_type_3 : _T_302 ? issue_slots_10_out_uop_iq_type_3 : issue_slots_9_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_debug_pc = _T_303 ? issue_slots_11_out_uop_debug_pc : _T_302 ? issue_slots_10_out_uop_debug_pc : issue_slots_9_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_rvc = _T_303 ? issue_slots_11_out_uop_is_rvc : _T_302 ? issue_slots_10_out_uop_is_rvc : issue_slots_9_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_debug_inst = _T_303 ? issue_slots_11_out_uop_debug_inst : _T_302 ? issue_slots_10_out_uop_debug_inst : issue_slots_9_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_inst = _T_303 ? issue_slots_11_out_uop_inst : _T_302 ? issue_slots_10_out_uop_inst : issue_slots_9_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_8_clear_T = |shamts_oh_8; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_8_clear = _issue_slots_8_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_305 = shamts_oh_11 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_306 = shamts_oh_12 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_9_in_uop_valid = _T_306 ? issue_slots_12_will_be_valid : _T_305 ? issue_slots_11_will_be_valid : shamts_oh_10 == 3'h1 & issue_slots_10_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_9_in_uop_bits_debug_tsrc = _T_306 ? issue_slots_12_out_uop_debug_tsrc : _T_305 ? issue_slots_11_out_uop_debug_tsrc : issue_slots_10_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_debug_fsrc = _T_306 ? issue_slots_12_out_uop_debug_fsrc : _T_305 ? issue_slots_11_out_uop_debug_fsrc : issue_slots_10_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_bp_xcpt_if = _T_306 ? issue_slots_12_out_uop_bp_xcpt_if : _T_305 ? issue_slots_11_out_uop_bp_xcpt_if : issue_slots_10_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_bp_debug_if = _T_306 ? issue_slots_12_out_uop_bp_debug_if : _T_305 ? issue_slots_11_out_uop_bp_debug_if : issue_slots_10_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_xcpt_ma_if = _T_306 ? issue_slots_12_out_uop_xcpt_ma_if : _T_305 ? issue_slots_11_out_uop_xcpt_ma_if : issue_slots_10_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_xcpt_ae_if = _T_306 ? issue_slots_12_out_uop_xcpt_ae_if : _T_305 ? issue_slots_11_out_uop_xcpt_ae_if : issue_slots_10_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_xcpt_pf_if = _T_306 ? issue_slots_12_out_uop_xcpt_pf_if : _T_305 ? issue_slots_11_out_uop_xcpt_pf_if : issue_slots_10_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_typ = _T_306 ? issue_slots_12_out_uop_fp_typ : _T_305 ? issue_slots_11_out_uop_fp_typ : issue_slots_10_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_rm = _T_306 ? issue_slots_12_out_uop_fp_rm : _T_305 ? issue_slots_11_out_uop_fp_rm : issue_slots_10_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_val = _T_306 ? issue_slots_12_out_uop_fp_val : _T_305 ? issue_slots_11_out_uop_fp_val : issue_slots_10_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fcn_op = _T_306 ? issue_slots_12_out_uop_fcn_op : _T_305 ? issue_slots_11_out_uop_fcn_op : issue_slots_10_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fcn_dw = _T_306 ? issue_slots_12_out_uop_fcn_dw : _T_305 ? issue_slots_11_out_uop_fcn_dw : issue_slots_10_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_frs3_en = _T_306 ? issue_slots_12_out_uop_frs3_en : _T_305 ? issue_slots_11_out_uop_frs3_en : issue_slots_10_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_lrs2_rtype = _T_306 ? issue_slots_12_out_uop_lrs2_rtype : _T_305 ? issue_slots_11_out_uop_lrs2_rtype : issue_slots_10_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_lrs1_rtype = _T_306 ? issue_slots_12_out_uop_lrs1_rtype : _T_305 ? issue_slots_11_out_uop_lrs1_rtype : issue_slots_10_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_dst_rtype = _T_306 ? issue_slots_12_out_uop_dst_rtype : _T_305 ? issue_slots_11_out_uop_dst_rtype : issue_slots_10_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_lrs3 = _T_306 ? issue_slots_12_out_uop_lrs3 : _T_305 ? issue_slots_11_out_uop_lrs3 : issue_slots_10_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_lrs2 = _T_306 ? issue_slots_12_out_uop_lrs2 : _T_305 ? issue_slots_11_out_uop_lrs2 : issue_slots_10_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_lrs1 = _T_306 ? issue_slots_12_out_uop_lrs1 : _T_305 ? issue_slots_11_out_uop_lrs1 : issue_slots_10_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_ldst = _T_306 ? issue_slots_12_out_uop_ldst : _T_305 ? issue_slots_11_out_uop_ldst : issue_slots_10_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_ldst_is_rs1 = _T_306 ? issue_slots_12_out_uop_ldst_is_rs1 : _T_305 ? issue_slots_11_out_uop_ldst_is_rs1 : issue_slots_10_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_csr_cmd = _T_306 ? issue_slots_12_out_uop_csr_cmd : _T_305 ? issue_slots_11_out_uop_csr_cmd : issue_slots_10_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_flush_on_commit = _T_306 ? issue_slots_12_out_uop_flush_on_commit : _T_305 ? issue_slots_11_out_uop_flush_on_commit : issue_slots_10_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_unique = _T_306 ? issue_slots_12_out_uop_is_unique : _T_305 ? issue_slots_11_out_uop_is_unique : issue_slots_10_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_uses_stq = _T_306 ? issue_slots_12_out_uop_uses_stq : _T_305 ? issue_slots_11_out_uop_uses_stq : issue_slots_10_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_uses_ldq = _T_306 ? issue_slots_12_out_uop_uses_ldq : _T_305 ? issue_slots_11_out_uop_uses_ldq : issue_slots_10_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_mem_signed = _T_306 ? issue_slots_12_out_uop_mem_signed : _T_305 ? issue_slots_11_out_uop_mem_signed : issue_slots_10_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_mem_size = _T_306 ? issue_slots_12_out_uop_mem_size : _T_305 ? issue_slots_11_out_uop_mem_size : issue_slots_10_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_mem_cmd = _T_306 ? issue_slots_12_out_uop_mem_cmd : _T_305 ? issue_slots_11_out_uop_mem_cmd : issue_slots_10_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_exc_cause = _T_306 ? issue_slots_12_out_uop_exc_cause : _T_305 ? issue_slots_11_out_uop_exc_cause : issue_slots_10_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_exception = _T_306 ? issue_slots_12_out_uop_exception : _T_305 ? issue_slots_11_out_uop_exception : issue_slots_10_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_stale_pdst = _T_306 ? issue_slots_12_out_uop_stale_pdst : _T_305 ? issue_slots_11_out_uop_stale_pdst : issue_slots_10_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_ppred_busy = _T_306 ? issue_slots_12_out_uop_ppred_busy : _T_305 ? issue_slots_11_out_uop_ppred_busy : issue_slots_10_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_prs3_busy = _T_306 ? issue_slots_12_out_uop_prs3_busy : _T_305 ? issue_slots_11_out_uop_prs3_busy : issue_slots_10_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_prs2_busy = _T_306 ? issue_slots_12_out_uop_prs2_busy : _T_305 ? issue_slots_11_out_uop_prs2_busy : issue_slots_10_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_prs1_busy = _T_306 ? issue_slots_12_out_uop_prs1_busy : _T_305 ? issue_slots_11_out_uop_prs1_busy : issue_slots_10_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_ppred = _T_306 ? issue_slots_12_out_uop_ppred : _T_305 ? issue_slots_11_out_uop_ppred : issue_slots_10_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_prs3 = _T_306 ? issue_slots_12_out_uop_prs3 : _T_305 ? issue_slots_11_out_uop_prs3 : issue_slots_10_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_prs2 = _T_306 ? issue_slots_12_out_uop_prs2 : _T_305 ? issue_slots_11_out_uop_prs2 : issue_slots_10_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_prs1 = _T_306 ? issue_slots_12_out_uop_prs1 : _T_305 ? issue_slots_11_out_uop_prs1 : issue_slots_10_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_pdst = _T_306 ? issue_slots_12_out_uop_pdst : _T_305 ? issue_slots_11_out_uop_pdst : issue_slots_10_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_rxq_idx = _T_306 ? issue_slots_12_out_uop_rxq_idx : _T_305 ? issue_slots_11_out_uop_rxq_idx : issue_slots_10_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_stq_idx = _T_306 ? issue_slots_12_out_uop_stq_idx : _T_305 ? issue_slots_11_out_uop_stq_idx : issue_slots_10_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_ldq_idx = _T_306 ? issue_slots_12_out_uop_ldq_idx : _T_305 ? issue_slots_11_out_uop_ldq_idx : issue_slots_10_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_rob_idx = _T_306 ? issue_slots_12_out_uop_rob_idx : _T_305 ? issue_slots_11_out_uop_rob_idx : issue_slots_10_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_vec = _T_306 ? issue_slots_12_out_uop_fp_ctrl_vec : _T_305 ? issue_slots_11_out_uop_fp_ctrl_vec : issue_slots_10_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_wflags = _T_306 ? issue_slots_12_out_uop_fp_ctrl_wflags : _T_305 ? issue_slots_11_out_uop_fp_ctrl_wflags : issue_slots_10_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_sqrt = _T_306 ? issue_slots_12_out_uop_fp_ctrl_sqrt : _T_305 ? issue_slots_11_out_uop_fp_ctrl_sqrt : issue_slots_10_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_div = _T_306 ? issue_slots_12_out_uop_fp_ctrl_div : _T_305 ? issue_slots_11_out_uop_fp_ctrl_div : issue_slots_10_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_fma = _T_306 ? issue_slots_12_out_uop_fp_ctrl_fma : _T_305 ? issue_slots_11_out_uop_fp_ctrl_fma : issue_slots_10_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_fastpipe = _T_306 ? issue_slots_12_out_uop_fp_ctrl_fastpipe : _T_305 ? issue_slots_11_out_uop_fp_ctrl_fastpipe : issue_slots_10_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_toint = _T_306 ? issue_slots_12_out_uop_fp_ctrl_toint : _T_305 ? issue_slots_11_out_uop_fp_ctrl_toint : issue_slots_10_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_fromint = _T_306 ? issue_slots_12_out_uop_fp_ctrl_fromint : _T_305 ? issue_slots_11_out_uop_fp_ctrl_fromint : issue_slots_10_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_typeTagOut = _T_306 ? issue_slots_12_out_uop_fp_ctrl_typeTagOut : _T_305 ? issue_slots_11_out_uop_fp_ctrl_typeTagOut : issue_slots_10_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_typeTagIn = _T_306 ? issue_slots_12_out_uop_fp_ctrl_typeTagIn : _T_305 ? issue_slots_11_out_uop_fp_ctrl_typeTagIn : issue_slots_10_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_swap23 = _T_306 ? issue_slots_12_out_uop_fp_ctrl_swap23 : _T_305 ? issue_slots_11_out_uop_fp_ctrl_swap23 : issue_slots_10_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_swap12 = _T_306 ? issue_slots_12_out_uop_fp_ctrl_swap12 : _T_305 ? issue_slots_11_out_uop_fp_ctrl_swap12 : issue_slots_10_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_ren3 = _T_306 ? issue_slots_12_out_uop_fp_ctrl_ren3 : _T_305 ? issue_slots_11_out_uop_fp_ctrl_ren3 : issue_slots_10_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_ren2 = _T_306 ? issue_slots_12_out_uop_fp_ctrl_ren2 : _T_305 ? issue_slots_11_out_uop_fp_ctrl_ren2 : issue_slots_10_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_ren1 = _T_306 ? issue_slots_12_out_uop_fp_ctrl_ren1 : _T_305 ? issue_slots_11_out_uop_fp_ctrl_ren1 : issue_slots_10_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_wen = _T_306 ? issue_slots_12_out_uop_fp_ctrl_wen : _T_305 ? issue_slots_11_out_uop_fp_ctrl_wen : issue_slots_10_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_ldst = _T_306 ? issue_slots_12_out_uop_fp_ctrl_ldst : _T_305 ? issue_slots_11_out_uop_fp_ctrl_ldst : issue_slots_10_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_op2_sel = _T_306 ? issue_slots_12_out_uop_op2_sel : _T_305 ? issue_slots_11_out_uop_op2_sel : issue_slots_10_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_op1_sel = _T_306 ? issue_slots_12_out_uop_op1_sel : _T_305 ? issue_slots_11_out_uop_op1_sel : issue_slots_10_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_imm_packed = _T_306 ? issue_slots_12_out_uop_imm_packed : _T_305 ? issue_slots_11_out_uop_imm_packed : issue_slots_10_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_pimm = _T_306 ? issue_slots_12_out_uop_pimm : _T_305 ? issue_slots_11_out_uop_pimm : issue_slots_10_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_imm_sel = _T_306 ? issue_slots_12_out_uop_imm_sel : _T_305 ? issue_slots_11_out_uop_imm_sel : issue_slots_10_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_imm_rename = _T_306 ? issue_slots_12_out_uop_imm_rename : _T_305 ? issue_slots_11_out_uop_imm_rename : issue_slots_10_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_taken = _T_306 ? issue_slots_12_out_uop_taken : _T_305 ? issue_slots_11_out_uop_taken : issue_slots_10_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_pc_lob = _T_306 ? issue_slots_12_out_uop_pc_lob : _T_305 ? issue_slots_11_out_uop_pc_lob : issue_slots_10_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_edge_inst = _T_306 ? issue_slots_12_out_uop_edge_inst : _T_305 ? issue_slots_11_out_uop_edge_inst : issue_slots_10_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_ftq_idx = _T_306 ? issue_slots_12_out_uop_ftq_idx : _T_305 ? issue_slots_11_out_uop_ftq_idx : issue_slots_10_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_mov = _T_306 ? issue_slots_12_out_uop_is_mov : _T_305 ? issue_slots_11_out_uop_is_mov : issue_slots_10_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_rocc = _T_306 ? issue_slots_12_out_uop_is_rocc : _T_305 ? issue_slots_11_out_uop_is_rocc : issue_slots_10_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_sys_pc2epc = _T_306 ? issue_slots_12_out_uop_is_sys_pc2epc : _T_305 ? issue_slots_11_out_uop_is_sys_pc2epc : issue_slots_10_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_eret = _T_306 ? issue_slots_12_out_uop_is_eret : _T_305 ? issue_slots_11_out_uop_is_eret : issue_slots_10_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_amo = _T_306 ? issue_slots_12_out_uop_is_amo : _T_305 ? issue_slots_11_out_uop_is_amo : issue_slots_10_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_sfence = _T_306 ? issue_slots_12_out_uop_is_sfence : _T_305 ? issue_slots_11_out_uop_is_sfence : issue_slots_10_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_fencei = _T_306 ? issue_slots_12_out_uop_is_fencei : _T_305 ? issue_slots_11_out_uop_is_fencei : issue_slots_10_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_fence = _T_306 ? issue_slots_12_out_uop_is_fence : _T_305 ? issue_slots_11_out_uop_is_fence : issue_slots_10_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_sfb = _T_306 ? issue_slots_12_out_uop_is_sfb : _T_305 ? issue_slots_11_out_uop_is_sfb : issue_slots_10_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_br_type = _T_306 ? issue_slots_12_out_uop_br_type : _T_305 ? issue_slots_11_out_uop_br_type : issue_slots_10_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_br_tag = _T_306 ? issue_slots_12_out_uop_br_tag : _T_305 ? issue_slots_11_out_uop_br_tag : issue_slots_10_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_br_mask = _T_306 ? issue_slots_12_out_uop_br_mask : _T_305 ? issue_slots_11_out_uop_br_mask : issue_slots_10_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_dis_col_sel = _T_306 ? issue_slots_12_out_uop_dis_col_sel : _T_305 ? issue_slots_11_out_uop_dis_col_sel : issue_slots_10_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iw_p3_bypass_hint = _T_306 ? issue_slots_12_out_uop_iw_p3_bypass_hint : _T_305 ? issue_slots_11_out_uop_iw_p3_bypass_hint : issue_slots_10_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iw_p2_bypass_hint = _T_306 ? issue_slots_12_out_uop_iw_p2_bypass_hint : _T_305 ? issue_slots_11_out_uop_iw_p2_bypass_hint : issue_slots_10_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iw_p1_bypass_hint = _T_306 ? issue_slots_12_out_uop_iw_p1_bypass_hint : _T_305 ? issue_slots_11_out_uop_iw_p1_bypass_hint : issue_slots_10_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iw_p2_speculative_child = _T_306 ? issue_slots_12_out_uop_iw_p2_speculative_child : _T_305 ? issue_slots_11_out_uop_iw_p2_speculative_child : issue_slots_10_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iw_p1_speculative_child = _T_306 ? issue_slots_12_out_uop_iw_p1_speculative_child : _T_305 ? issue_slots_11_out_uop_iw_p1_speculative_child : issue_slots_10_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iw_issued = _T_306 ? issue_slots_12_out_uop_iw_issued : _T_305 ? issue_slots_11_out_uop_iw_issued : issue_slots_10_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_0 = _T_306 ? issue_slots_12_out_uop_fu_code_0 : _T_305 ? issue_slots_11_out_uop_fu_code_0 : issue_slots_10_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_1 = _T_306 ? issue_slots_12_out_uop_fu_code_1 : _T_305 ? issue_slots_11_out_uop_fu_code_1 : issue_slots_10_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_2 = _T_306 ? issue_slots_12_out_uop_fu_code_2 : _T_305 ? issue_slots_11_out_uop_fu_code_2 : issue_slots_10_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_3 = _T_306 ? issue_slots_12_out_uop_fu_code_3 : _T_305 ? issue_slots_11_out_uop_fu_code_3 : issue_slots_10_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_4 = _T_306 ? issue_slots_12_out_uop_fu_code_4 : _T_305 ? issue_slots_11_out_uop_fu_code_4 : issue_slots_10_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_5 = _T_306 ? issue_slots_12_out_uop_fu_code_5 : _T_305 ? issue_slots_11_out_uop_fu_code_5 : issue_slots_10_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_6 = _T_306 ? issue_slots_12_out_uop_fu_code_6 : _T_305 ? issue_slots_11_out_uop_fu_code_6 : issue_slots_10_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_7 = _T_306 ? issue_slots_12_out_uop_fu_code_7 : _T_305 ? issue_slots_11_out_uop_fu_code_7 : issue_slots_10_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_8 = _T_306 ? issue_slots_12_out_uop_fu_code_8 : _T_305 ? issue_slots_11_out_uop_fu_code_8 : issue_slots_10_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_9 = _T_306 ? issue_slots_12_out_uop_fu_code_9 : _T_305 ? issue_slots_11_out_uop_fu_code_9 : issue_slots_10_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iq_type_0 = _T_306 ? issue_slots_12_out_uop_iq_type_0 : _T_305 ? issue_slots_11_out_uop_iq_type_0 : issue_slots_10_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iq_type_1 = _T_306 ? issue_slots_12_out_uop_iq_type_1 : _T_305 ? issue_slots_11_out_uop_iq_type_1 : issue_slots_10_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iq_type_2 = _T_306 ? issue_slots_12_out_uop_iq_type_2 : _T_305 ? issue_slots_11_out_uop_iq_type_2 : issue_slots_10_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iq_type_3 = _T_306 ? issue_slots_12_out_uop_iq_type_3 : _T_305 ? issue_slots_11_out_uop_iq_type_3 : issue_slots_10_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_debug_pc = _T_306 ? issue_slots_12_out_uop_debug_pc : _T_305 ? issue_slots_11_out_uop_debug_pc : issue_slots_10_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_rvc = _T_306 ? issue_slots_12_out_uop_is_rvc : _T_305 ? issue_slots_11_out_uop_is_rvc : issue_slots_10_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_debug_inst = _T_306 ? issue_slots_12_out_uop_debug_inst : _T_305 ? issue_slots_11_out_uop_debug_inst : issue_slots_10_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_inst = _T_306 ? issue_slots_12_out_uop_inst : _T_305 ? issue_slots_11_out_uop_inst : issue_slots_10_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_9_clear_T = |shamts_oh_9; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_9_clear = _issue_slots_9_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_308 = shamts_oh_12 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_309 = shamts_oh_13 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_10_in_uop_valid = _T_309 ? issue_slots_13_will_be_valid : _T_308 ? issue_slots_12_will_be_valid : shamts_oh_11 == 3'h1 & issue_slots_11_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_10_in_uop_bits_debug_tsrc = _T_309 ? issue_slots_13_out_uop_debug_tsrc : _T_308 ? issue_slots_12_out_uop_debug_tsrc : issue_slots_11_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_debug_fsrc = _T_309 ? issue_slots_13_out_uop_debug_fsrc : _T_308 ? issue_slots_12_out_uop_debug_fsrc : issue_slots_11_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_bp_xcpt_if = _T_309 ? issue_slots_13_out_uop_bp_xcpt_if : _T_308 ? issue_slots_12_out_uop_bp_xcpt_if : issue_slots_11_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_bp_debug_if = _T_309 ? issue_slots_13_out_uop_bp_debug_if : _T_308 ? issue_slots_12_out_uop_bp_debug_if : issue_slots_11_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_xcpt_ma_if = _T_309 ? issue_slots_13_out_uop_xcpt_ma_if : _T_308 ? issue_slots_12_out_uop_xcpt_ma_if : issue_slots_11_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_xcpt_ae_if = _T_309 ? issue_slots_13_out_uop_xcpt_ae_if : _T_308 ? issue_slots_12_out_uop_xcpt_ae_if : issue_slots_11_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_xcpt_pf_if = _T_309 ? issue_slots_13_out_uop_xcpt_pf_if : _T_308 ? issue_slots_12_out_uop_xcpt_pf_if : issue_slots_11_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_typ = _T_309 ? issue_slots_13_out_uop_fp_typ : _T_308 ? issue_slots_12_out_uop_fp_typ : issue_slots_11_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_rm = _T_309 ? issue_slots_13_out_uop_fp_rm : _T_308 ? issue_slots_12_out_uop_fp_rm : issue_slots_11_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_val = _T_309 ? issue_slots_13_out_uop_fp_val : _T_308 ? issue_slots_12_out_uop_fp_val : issue_slots_11_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fcn_op = _T_309 ? issue_slots_13_out_uop_fcn_op : _T_308 ? issue_slots_12_out_uop_fcn_op : issue_slots_11_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fcn_dw = _T_309 ? issue_slots_13_out_uop_fcn_dw : _T_308 ? issue_slots_12_out_uop_fcn_dw : issue_slots_11_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_frs3_en = _T_309 ? issue_slots_13_out_uop_frs3_en : _T_308 ? issue_slots_12_out_uop_frs3_en : issue_slots_11_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_lrs2_rtype = _T_309 ? issue_slots_13_out_uop_lrs2_rtype : _T_308 ? issue_slots_12_out_uop_lrs2_rtype : issue_slots_11_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_lrs1_rtype = _T_309 ? issue_slots_13_out_uop_lrs1_rtype : _T_308 ? issue_slots_12_out_uop_lrs1_rtype : issue_slots_11_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_dst_rtype = _T_309 ? issue_slots_13_out_uop_dst_rtype : _T_308 ? issue_slots_12_out_uop_dst_rtype : issue_slots_11_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_lrs3 = _T_309 ? issue_slots_13_out_uop_lrs3 : _T_308 ? issue_slots_12_out_uop_lrs3 : issue_slots_11_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_lrs2 = _T_309 ? issue_slots_13_out_uop_lrs2 : _T_308 ? issue_slots_12_out_uop_lrs2 : issue_slots_11_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_lrs1 = _T_309 ? issue_slots_13_out_uop_lrs1 : _T_308 ? issue_slots_12_out_uop_lrs1 : issue_slots_11_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_ldst = _T_309 ? issue_slots_13_out_uop_ldst : _T_308 ? issue_slots_12_out_uop_ldst : issue_slots_11_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_ldst_is_rs1 = _T_309 ? issue_slots_13_out_uop_ldst_is_rs1 : _T_308 ? issue_slots_12_out_uop_ldst_is_rs1 : issue_slots_11_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_csr_cmd = _T_309 ? issue_slots_13_out_uop_csr_cmd : _T_308 ? issue_slots_12_out_uop_csr_cmd : issue_slots_11_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_flush_on_commit = _T_309 ? issue_slots_13_out_uop_flush_on_commit : _T_308 ? issue_slots_12_out_uop_flush_on_commit : issue_slots_11_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_unique = _T_309 ? issue_slots_13_out_uop_is_unique : _T_308 ? issue_slots_12_out_uop_is_unique : issue_slots_11_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_uses_stq = _T_309 ? issue_slots_13_out_uop_uses_stq : _T_308 ? issue_slots_12_out_uop_uses_stq : issue_slots_11_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_uses_ldq = _T_309 ? issue_slots_13_out_uop_uses_ldq : _T_308 ? issue_slots_12_out_uop_uses_ldq : issue_slots_11_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_mem_signed = _T_309 ? issue_slots_13_out_uop_mem_signed : _T_308 ? issue_slots_12_out_uop_mem_signed : issue_slots_11_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_mem_size = _T_309 ? issue_slots_13_out_uop_mem_size : _T_308 ? issue_slots_12_out_uop_mem_size : issue_slots_11_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_mem_cmd = _T_309 ? issue_slots_13_out_uop_mem_cmd : _T_308 ? issue_slots_12_out_uop_mem_cmd : issue_slots_11_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_exc_cause = _T_309 ? issue_slots_13_out_uop_exc_cause : _T_308 ? issue_slots_12_out_uop_exc_cause : issue_slots_11_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_exception = _T_309 ? issue_slots_13_out_uop_exception : _T_308 ? issue_slots_12_out_uop_exception : issue_slots_11_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_stale_pdst = _T_309 ? issue_slots_13_out_uop_stale_pdst : _T_308 ? issue_slots_12_out_uop_stale_pdst : issue_slots_11_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_ppred_busy = _T_309 ? issue_slots_13_out_uop_ppred_busy : _T_308 ? issue_slots_12_out_uop_ppred_busy : issue_slots_11_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_prs3_busy = _T_309 ? issue_slots_13_out_uop_prs3_busy : _T_308 ? issue_slots_12_out_uop_prs3_busy : issue_slots_11_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_prs2_busy = _T_309 ? issue_slots_13_out_uop_prs2_busy : _T_308 ? issue_slots_12_out_uop_prs2_busy : issue_slots_11_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_prs1_busy = _T_309 ? issue_slots_13_out_uop_prs1_busy : _T_308 ? issue_slots_12_out_uop_prs1_busy : issue_slots_11_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_ppred = _T_309 ? issue_slots_13_out_uop_ppred : _T_308 ? issue_slots_12_out_uop_ppred : issue_slots_11_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_prs3 = _T_309 ? issue_slots_13_out_uop_prs3 : _T_308 ? issue_slots_12_out_uop_prs3 : issue_slots_11_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_prs2 = _T_309 ? issue_slots_13_out_uop_prs2 : _T_308 ? issue_slots_12_out_uop_prs2 : issue_slots_11_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_prs1 = _T_309 ? issue_slots_13_out_uop_prs1 : _T_308 ? issue_slots_12_out_uop_prs1 : issue_slots_11_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_pdst = _T_309 ? issue_slots_13_out_uop_pdst : _T_308 ? issue_slots_12_out_uop_pdst : issue_slots_11_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_rxq_idx = _T_309 ? issue_slots_13_out_uop_rxq_idx : _T_308 ? issue_slots_12_out_uop_rxq_idx : issue_slots_11_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_stq_idx = _T_309 ? issue_slots_13_out_uop_stq_idx : _T_308 ? issue_slots_12_out_uop_stq_idx : issue_slots_11_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_ldq_idx = _T_309 ? issue_slots_13_out_uop_ldq_idx : _T_308 ? issue_slots_12_out_uop_ldq_idx : issue_slots_11_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_rob_idx = _T_309 ? issue_slots_13_out_uop_rob_idx : _T_308 ? issue_slots_12_out_uop_rob_idx : issue_slots_11_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_vec = _T_309 ? issue_slots_13_out_uop_fp_ctrl_vec : _T_308 ? issue_slots_12_out_uop_fp_ctrl_vec : issue_slots_11_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_wflags = _T_309 ? issue_slots_13_out_uop_fp_ctrl_wflags : _T_308 ? issue_slots_12_out_uop_fp_ctrl_wflags : issue_slots_11_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_sqrt = _T_309 ? issue_slots_13_out_uop_fp_ctrl_sqrt : _T_308 ? issue_slots_12_out_uop_fp_ctrl_sqrt : issue_slots_11_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_div = _T_309 ? issue_slots_13_out_uop_fp_ctrl_div : _T_308 ? issue_slots_12_out_uop_fp_ctrl_div : issue_slots_11_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_fma = _T_309 ? issue_slots_13_out_uop_fp_ctrl_fma : _T_308 ? issue_slots_12_out_uop_fp_ctrl_fma : issue_slots_11_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_fastpipe = _T_309 ? issue_slots_13_out_uop_fp_ctrl_fastpipe : _T_308 ? issue_slots_12_out_uop_fp_ctrl_fastpipe : issue_slots_11_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_toint = _T_309 ? issue_slots_13_out_uop_fp_ctrl_toint : _T_308 ? issue_slots_12_out_uop_fp_ctrl_toint : issue_slots_11_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_fromint = _T_309 ? issue_slots_13_out_uop_fp_ctrl_fromint : _T_308 ? issue_slots_12_out_uop_fp_ctrl_fromint : issue_slots_11_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_typeTagOut = _T_309 ? issue_slots_13_out_uop_fp_ctrl_typeTagOut : _T_308 ? issue_slots_12_out_uop_fp_ctrl_typeTagOut : issue_slots_11_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_typeTagIn = _T_309 ? issue_slots_13_out_uop_fp_ctrl_typeTagIn : _T_308 ? issue_slots_12_out_uop_fp_ctrl_typeTagIn : issue_slots_11_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_swap23 = _T_309 ? issue_slots_13_out_uop_fp_ctrl_swap23 : _T_308 ? issue_slots_12_out_uop_fp_ctrl_swap23 : issue_slots_11_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_swap12 = _T_309 ? issue_slots_13_out_uop_fp_ctrl_swap12 : _T_308 ? issue_slots_12_out_uop_fp_ctrl_swap12 : issue_slots_11_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_ren3 = _T_309 ? issue_slots_13_out_uop_fp_ctrl_ren3 : _T_308 ? issue_slots_12_out_uop_fp_ctrl_ren3 : issue_slots_11_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_ren2 = _T_309 ? issue_slots_13_out_uop_fp_ctrl_ren2 : _T_308 ? issue_slots_12_out_uop_fp_ctrl_ren2 : issue_slots_11_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_ren1 = _T_309 ? issue_slots_13_out_uop_fp_ctrl_ren1 : _T_308 ? issue_slots_12_out_uop_fp_ctrl_ren1 : issue_slots_11_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_wen = _T_309 ? issue_slots_13_out_uop_fp_ctrl_wen : _T_308 ? issue_slots_12_out_uop_fp_ctrl_wen : issue_slots_11_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_ldst = _T_309 ? issue_slots_13_out_uop_fp_ctrl_ldst : _T_308 ? issue_slots_12_out_uop_fp_ctrl_ldst : issue_slots_11_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_op2_sel = _T_309 ? issue_slots_13_out_uop_op2_sel : _T_308 ? issue_slots_12_out_uop_op2_sel : issue_slots_11_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_op1_sel = _T_309 ? issue_slots_13_out_uop_op1_sel : _T_308 ? issue_slots_12_out_uop_op1_sel : issue_slots_11_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_imm_packed = _T_309 ? issue_slots_13_out_uop_imm_packed : _T_308 ? issue_slots_12_out_uop_imm_packed : issue_slots_11_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_pimm = _T_309 ? issue_slots_13_out_uop_pimm : _T_308 ? issue_slots_12_out_uop_pimm : issue_slots_11_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_imm_sel = _T_309 ? issue_slots_13_out_uop_imm_sel : _T_308 ? issue_slots_12_out_uop_imm_sel : issue_slots_11_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_imm_rename = _T_309 ? issue_slots_13_out_uop_imm_rename : _T_308 ? issue_slots_12_out_uop_imm_rename : issue_slots_11_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_taken = _T_309 ? issue_slots_13_out_uop_taken : _T_308 ? issue_slots_12_out_uop_taken : issue_slots_11_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_pc_lob = _T_309 ? issue_slots_13_out_uop_pc_lob : _T_308 ? issue_slots_12_out_uop_pc_lob : issue_slots_11_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_edge_inst = _T_309 ? issue_slots_13_out_uop_edge_inst : _T_308 ? issue_slots_12_out_uop_edge_inst : issue_slots_11_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_ftq_idx = _T_309 ? issue_slots_13_out_uop_ftq_idx : _T_308 ? issue_slots_12_out_uop_ftq_idx : issue_slots_11_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_mov = _T_309 ? issue_slots_13_out_uop_is_mov : _T_308 ? issue_slots_12_out_uop_is_mov : issue_slots_11_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_rocc = _T_309 ? issue_slots_13_out_uop_is_rocc : _T_308 ? issue_slots_12_out_uop_is_rocc : issue_slots_11_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_sys_pc2epc = _T_309 ? issue_slots_13_out_uop_is_sys_pc2epc : _T_308 ? issue_slots_12_out_uop_is_sys_pc2epc : issue_slots_11_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_eret = _T_309 ? issue_slots_13_out_uop_is_eret : _T_308 ? issue_slots_12_out_uop_is_eret : issue_slots_11_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_amo = _T_309 ? issue_slots_13_out_uop_is_amo : _T_308 ? issue_slots_12_out_uop_is_amo : issue_slots_11_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_sfence = _T_309 ? issue_slots_13_out_uop_is_sfence : _T_308 ? issue_slots_12_out_uop_is_sfence : issue_slots_11_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_fencei = _T_309 ? issue_slots_13_out_uop_is_fencei : _T_308 ? issue_slots_12_out_uop_is_fencei : issue_slots_11_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_fence = _T_309 ? issue_slots_13_out_uop_is_fence : _T_308 ? issue_slots_12_out_uop_is_fence : issue_slots_11_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_sfb = _T_309 ? issue_slots_13_out_uop_is_sfb : _T_308 ? issue_slots_12_out_uop_is_sfb : issue_slots_11_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_br_type = _T_309 ? issue_slots_13_out_uop_br_type : _T_308 ? issue_slots_12_out_uop_br_type : issue_slots_11_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_br_tag = _T_309 ? issue_slots_13_out_uop_br_tag : _T_308 ? issue_slots_12_out_uop_br_tag : issue_slots_11_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_br_mask = _T_309 ? issue_slots_13_out_uop_br_mask : _T_308 ? issue_slots_12_out_uop_br_mask : issue_slots_11_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_dis_col_sel = _T_309 ? issue_slots_13_out_uop_dis_col_sel : _T_308 ? issue_slots_12_out_uop_dis_col_sel : issue_slots_11_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iw_p3_bypass_hint = _T_309 ? issue_slots_13_out_uop_iw_p3_bypass_hint : _T_308 ? issue_slots_12_out_uop_iw_p3_bypass_hint : issue_slots_11_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iw_p2_bypass_hint = _T_309 ? issue_slots_13_out_uop_iw_p2_bypass_hint : _T_308 ? issue_slots_12_out_uop_iw_p2_bypass_hint : issue_slots_11_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iw_p1_bypass_hint = _T_309 ? issue_slots_13_out_uop_iw_p1_bypass_hint : _T_308 ? issue_slots_12_out_uop_iw_p1_bypass_hint : issue_slots_11_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iw_p2_speculative_child = _T_309 ? issue_slots_13_out_uop_iw_p2_speculative_child : _T_308 ? issue_slots_12_out_uop_iw_p2_speculative_child : issue_slots_11_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iw_p1_speculative_child = _T_309 ? issue_slots_13_out_uop_iw_p1_speculative_child : _T_308 ? issue_slots_12_out_uop_iw_p1_speculative_child : issue_slots_11_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iw_issued = _T_309 ? issue_slots_13_out_uop_iw_issued : _T_308 ? issue_slots_12_out_uop_iw_issued : issue_slots_11_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_0 = _T_309 ? issue_slots_13_out_uop_fu_code_0 : _T_308 ? issue_slots_12_out_uop_fu_code_0 : issue_slots_11_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_1 = _T_309 ? issue_slots_13_out_uop_fu_code_1 : _T_308 ? issue_slots_12_out_uop_fu_code_1 : issue_slots_11_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_2 = _T_309 ? issue_slots_13_out_uop_fu_code_2 : _T_308 ? issue_slots_12_out_uop_fu_code_2 : issue_slots_11_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_3 = _T_309 ? issue_slots_13_out_uop_fu_code_3 : _T_308 ? issue_slots_12_out_uop_fu_code_3 : issue_slots_11_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_4 = _T_309 ? issue_slots_13_out_uop_fu_code_4 : _T_308 ? issue_slots_12_out_uop_fu_code_4 : issue_slots_11_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_5 = _T_309 ? issue_slots_13_out_uop_fu_code_5 : _T_308 ? issue_slots_12_out_uop_fu_code_5 : issue_slots_11_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_6 = _T_309 ? issue_slots_13_out_uop_fu_code_6 : _T_308 ? issue_slots_12_out_uop_fu_code_6 : issue_slots_11_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_7 = _T_309 ? issue_slots_13_out_uop_fu_code_7 : _T_308 ? issue_slots_12_out_uop_fu_code_7 : issue_slots_11_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_8 = _T_309 ? issue_slots_13_out_uop_fu_code_8 : _T_308 ? issue_slots_12_out_uop_fu_code_8 : issue_slots_11_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_9 = _T_309 ? issue_slots_13_out_uop_fu_code_9 : _T_308 ? issue_slots_12_out_uop_fu_code_9 : issue_slots_11_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iq_type_0 = _T_309 ? issue_slots_13_out_uop_iq_type_0 : _T_308 ? issue_slots_12_out_uop_iq_type_0 : issue_slots_11_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iq_type_1 = _T_309 ? issue_slots_13_out_uop_iq_type_1 : _T_308 ? issue_slots_12_out_uop_iq_type_1 : issue_slots_11_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iq_type_2 = _T_309 ? issue_slots_13_out_uop_iq_type_2 : _T_308 ? issue_slots_12_out_uop_iq_type_2 : issue_slots_11_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iq_type_3 = _T_309 ? issue_slots_13_out_uop_iq_type_3 : _T_308 ? issue_slots_12_out_uop_iq_type_3 : issue_slots_11_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_debug_pc = _T_309 ? issue_slots_13_out_uop_debug_pc : _T_308 ? issue_slots_12_out_uop_debug_pc : issue_slots_11_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_rvc = _T_309 ? issue_slots_13_out_uop_is_rvc : _T_308 ? issue_slots_12_out_uop_is_rvc : issue_slots_11_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_debug_inst = _T_309 ? issue_slots_13_out_uop_debug_inst : _T_308 ? issue_slots_12_out_uop_debug_inst : issue_slots_11_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_inst = _T_309 ? issue_slots_13_out_uop_inst : _T_308 ? issue_slots_12_out_uop_inst : issue_slots_11_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_10_clear_T = |shamts_oh_10; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_10_clear = _issue_slots_10_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_311 = shamts_oh_13 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_312 = shamts_oh_14 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_11_in_uop_valid = _T_312 ? issue_slots_14_will_be_valid : _T_311 ? issue_slots_13_will_be_valid : shamts_oh_12 == 3'h1 & issue_slots_12_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_11_in_uop_bits_debug_tsrc = _T_312 ? issue_slots_14_out_uop_debug_tsrc : _T_311 ? issue_slots_13_out_uop_debug_tsrc : issue_slots_12_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_debug_fsrc = _T_312 ? issue_slots_14_out_uop_debug_fsrc : _T_311 ? issue_slots_13_out_uop_debug_fsrc : issue_slots_12_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_bp_xcpt_if = _T_312 ? issue_slots_14_out_uop_bp_xcpt_if : _T_311 ? issue_slots_13_out_uop_bp_xcpt_if : issue_slots_12_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_bp_debug_if = _T_312 ? issue_slots_14_out_uop_bp_debug_if : _T_311 ? issue_slots_13_out_uop_bp_debug_if : issue_slots_12_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_xcpt_ma_if = _T_312 ? issue_slots_14_out_uop_xcpt_ma_if : _T_311 ? issue_slots_13_out_uop_xcpt_ma_if : issue_slots_12_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_xcpt_ae_if = _T_312 ? issue_slots_14_out_uop_xcpt_ae_if : _T_311 ? issue_slots_13_out_uop_xcpt_ae_if : issue_slots_12_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_xcpt_pf_if = _T_312 ? issue_slots_14_out_uop_xcpt_pf_if : _T_311 ? issue_slots_13_out_uop_xcpt_pf_if : issue_slots_12_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_typ = _T_312 ? issue_slots_14_out_uop_fp_typ : _T_311 ? issue_slots_13_out_uop_fp_typ : issue_slots_12_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_rm = _T_312 ? issue_slots_14_out_uop_fp_rm : _T_311 ? issue_slots_13_out_uop_fp_rm : issue_slots_12_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_val = _T_312 ? issue_slots_14_out_uop_fp_val : _T_311 ? issue_slots_13_out_uop_fp_val : issue_slots_12_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fcn_op = _T_312 ? issue_slots_14_out_uop_fcn_op : _T_311 ? issue_slots_13_out_uop_fcn_op : issue_slots_12_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fcn_dw = _T_312 ? issue_slots_14_out_uop_fcn_dw : _T_311 ? issue_slots_13_out_uop_fcn_dw : issue_slots_12_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_frs3_en = _T_312 ? issue_slots_14_out_uop_frs3_en : _T_311 ? issue_slots_13_out_uop_frs3_en : issue_slots_12_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_lrs2_rtype = _T_312 ? issue_slots_14_out_uop_lrs2_rtype : _T_311 ? issue_slots_13_out_uop_lrs2_rtype : issue_slots_12_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_lrs1_rtype = _T_312 ? issue_slots_14_out_uop_lrs1_rtype : _T_311 ? issue_slots_13_out_uop_lrs1_rtype : issue_slots_12_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_dst_rtype = _T_312 ? issue_slots_14_out_uop_dst_rtype : _T_311 ? issue_slots_13_out_uop_dst_rtype : issue_slots_12_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_lrs3 = _T_312 ? issue_slots_14_out_uop_lrs3 : _T_311 ? issue_slots_13_out_uop_lrs3 : issue_slots_12_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_lrs2 = _T_312 ? issue_slots_14_out_uop_lrs2 : _T_311 ? issue_slots_13_out_uop_lrs2 : issue_slots_12_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_lrs1 = _T_312 ? issue_slots_14_out_uop_lrs1 : _T_311 ? issue_slots_13_out_uop_lrs1 : issue_slots_12_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_ldst = _T_312 ? issue_slots_14_out_uop_ldst : _T_311 ? issue_slots_13_out_uop_ldst : issue_slots_12_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_ldst_is_rs1 = _T_312 ? issue_slots_14_out_uop_ldst_is_rs1 : _T_311 ? issue_slots_13_out_uop_ldst_is_rs1 : issue_slots_12_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_csr_cmd = _T_312 ? issue_slots_14_out_uop_csr_cmd : _T_311 ? issue_slots_13_out_uop_csr_cmd : issue_slots_12_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_flush_on_commit = _T_312 ? issue_slots_14_out_uop_flush_on_commit : _T_311 ? issue_slots_13_out_uop_flush_on_commit : issue_slots_12_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_unique = _T_312 ? issue_slots_14_out_uop_is_unique : _T_311 ? issue_slots_13_out_uop_is_unique : issue_slots_12_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_uses_stq = _T_312 ? issue_slots_14_out_uop_uses_stq : _T_311 ? issue_slots_13_out_uop_uses_stq : issue_slots_12_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_uses_ldq = _T_312 ? issue_slots_14_out_uop_uses_ldq : _T_311 ? issue_slots_13_out_uop_uses_ldq : issue_slots_12_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_mem_signed = _T_312 ? issue_slots_14_out_uop_mem_signed : _T_311 ? issue_slots_13_out_uop_mem_signed : issue_slots_12_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_mem_size = _T_312 ? issue_slots_14_out_uop_mem_size : _T_311 ? issue_slots_13_out_uop_mem_size : issue_slots_12_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_mem_cmd = _T_312 ? issue_slots_14_out_uop_mem_cmd : _T_311 ? issue_slots_13_out_uop_mem_cmd : issue_slots_12_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_exc_cause = _T_312 ? issue_slots_14_out_uop_exc_cause : _T_311 ? issue_slots_13_out_uop_exc_cause : issue_slots_12_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_exception = _T_312 ? issue_slots_14_out_uop_exception : _T_311 ? issue_slots_13_out_uop_exception : issue_slots_12_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_stale_pdst = _T_312 ? issue_slots_14_out_uop_stale_pdst : _T_311 ? issue_slots_13_out_uop_stale_pdst : issue_slots_12_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_ppred_busy = _T_312 ? issue_slots_14_out_uop_ppred_busy : _T_311 ? issue_slots_13_out_uop_ppred_busy : issue_slots_12_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_prs3_busy = _T_312 ? issue_slots_14_out_uop_prs3_busy : _T_311 ? issue_slots_13_out_uop_prs3_busy : issue_slots_12_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_prs2_busy = _T_312 ? issue_slots_14_out_uop_prs2_busy : _T_311 ? issue_slots_13_out_uop_prs2_busy : issue_slots_12_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_prs1_busy = _T_312 ? issue_slots_14_out_uop_prs1_busy : _T_311 ? issue_slots_13_out_uop_prs1_busy : issue_slots_12_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_ppred = _T_312 ? issue_slots_14_out_uop_ppred : _T_311 ? issue_slots_13_out_uop_ppred : issue_slots_12_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_prs3 = _T_312 ? issue_slots_14_out_uop_prs3 : _T_311 ? issue_slots_13_out_uop_prs3 : issue_slots_12_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_prs2 = _T_312 ? issue_slots_14_out_uop_prs2 : _T_311 ? issue_slots_13_out_uop_prs2 : issue_slots_12_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_prs1 = _T_312 ? issue_slots_14_out_uop_prs1 : _T_311 ? issue_slots_13_out_uop_prs1 : issue_slots_12_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_pdst = _T_312 ? issue_slots_14_out_uop_pdst : _T_311 ? issue_slots_13_out_uop_pdst : issue_slots_12_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_rxq_idx = _T_312 ? issue_slots_14_out_uop_rxq_idx : _T_311 ? issue_slots_13_out_uop_rxq_idx : issue_slots_12_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_stq_idx = _T_312 ? issue_slots_14_out_uop_stq_idx : _T_311 ? issue_slots_13_out_uop_stq_idx : issue_slots_12_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_ldq_idx = _T_312 ? issue_slots_14_out_uop_ldq_idx : _T_311 ? issue_slots_13_out_uop_ldq_idx : issue_slots_12_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_rob_idx = _T_312 ? issue_slots_14_out_uop_rob_idx : _T_311 ? issue_slots_13_out_uop_rob_idx : issue_slots_12_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_vec = _T_312 ? issue_slots_14_out_uop_fp_ctrl_vec : _T_311 ? issue_slots_13_out_uop_fp_ctrl_vec : issue_slots_12_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_wflags = _T_312 ? issue_slots_14_out_uop_fp_ctrl_wflags : _T_311 ? issue_slots_13_out_uop_fp_ctrl_wflags : issue_slots_12_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_sqrt = _T_312 ? issue_slots_14_out_uop_fp_ctrl_sqrt : _T_311 ? issue_slots_13_out_uop_fp_ctrl_sqrt : issue_slots_12_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_div = _T_312 ? issue_slots_14_out_uop_fp_ctrl_div : _T_311 ? issue_slots_13_out_uop_fp_ctrl_div : issue_slots_12_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_fma = _T_312 ? issue_slots_14_out_uop_fp_ctrl_fma : _T_311 ? issue_slots_13_out_uop_fp_ctrl_fma : issue_slots_12_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_fastpipe = _T_312 ? issue_slots_14_out_uop_fp_ctrl_fastpipe : _T_311 ? issue_slots_13_out_uop_fp_ctrl_fastpipe : issue_slots_12_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_toint = _T_312 ? issue_slots_14_out_uop_fp_ctrl_toint : _T_311 ? issue_slots_13_out_uop_fp_ctrl_toint : issue_slots_12_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_fromint = _T_312 ? issue_slots_14_out_uop_fp_ctrl_fromint : _T_311 ? issue_slots_13_out_uop_fp_ctrl_fromint : issue_slots_12_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_typeTagOut = _T_312 ? issue_slots_14_out_uop_fp_ctrl_typeTagOut : _T_311 ? issue_slots_13_out_uop_fp_ctrl_typeTagOut : issue_slots_12_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_typeTagIn = _T_312 ? issue_slots_14_out_uop_fp_ctrl_typeTagIn : _T_311 ? issue_slots_13_out_uop_fp_ctrl_typeTagIn : issue_slots_12_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_swap23 = _T_312 ? issue_slots_14_out_uop_fp_ctrl_swap23 : _T_311 ? issue_slots_13_out_uop_fp_ctrl_swap23 : issue_slots_12_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_swap12 = _T_312 ? issue_slots_14_out_uop_fp_ctrl_swap12 : _T_311 ? issue_slots_13_out_uop_fp_ctrl_swap12 : issue_slots_12_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_ren3 = _T_312 ? issue_slots_14_out_uop_fp_ctrl_ren3 : _T_311 ? issue_slots_13_out_uop_fp_ctrl_ren3 : issue_slots_12_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_ren2 = _T_312 ? issue_slots_14_out_uop_fp_ctrl_ren2 : _T_311 ? issue_slots_13_out_uop_fp_ctrl_ren2 : issue_slots_12_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_ren1 = _T_312 ? issue_slots_14_out_uop_fp_ctrl_ren1 : _T_311 ? issue_slots_13_out_uop_fp_ctrl_ren1 : issue_slots_12_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_wen = _T_312 ? issue_slots_14_out_uop_fp_ctrl_wen : _T_311 ? issue_slots_13_out_uop_fp_ctrl_wen : issue_slots_12_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_ldst = _T_312 ? issue_slots_14_out_uop_fp_ctrl_ldst : _T_311 ? issue_slots_13_out_uop_fp_ctrl_ldst : issue_slots_12_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_op2_sel = _T_312 ? issue_slots_14_out_uop_op2_sel : _T_311 ? issue_slots_13_out_uop_op2_sel : issue_slots_12_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_op1_sel = _T_312 ? issue_slots_14_out_uop_op1_sel : _T_311 ? issue_slots_13_out_uop_op1_sel : issue_slots_12_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_imm_packed = _T_312 ? issue_slots_14_out_uop_imm_packed : _T_311 ? issue_slots_13_out_uop_imm_packed : issue_slots_12_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_pimm = _T_312 ? issue_slots_14_out_uop_pimm : _T_311 ? issue_slots_13_out_uop_pimm : issue_slots_12_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_imm_sel = _T_312 ? issue_slots_14_out_uop_imm_sel : _T_311 ? issue_slots_13_out_uop_imm_sel : issue_slots_12_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_imm_rename = _T_312 ? issue_slots_14_out_uop_imm_rename : _T_311 ? issue_slots_13_out_uop_imm_rename : issue_slots_12_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_taken = _T_312 ? issue_slots_14_out_uop_taken : _T_311 ? issue_slots_13_out_uop_taken : issue_slots_12_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_pc_lob = _T_312 ? issue_slots_14_out_uop_pc_lob : _T_311 ? issue_slots_13_out_uop_pc_lob : issue_slots_12_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_edge_inst = _T_312 ? issue_slots_14_out_uop_edge_inst : _T_311 ? issue_slots_13_out_uop_edge_inst : issue_slots_12_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_ftq_idx = _T_312 ? issue_slots_14_out_uop_ftq_idx : _T_311 ? issue_slots_13_out_uop_ftq_idx : issue_slots_12_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_mov = _T_312 ? issue_slots_14_out_uop_is_mov : _T_311 ? issue_slots_13_out_uop_is_mov : issue_slots_12_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_rocc = _T_312 ? issue_slots_14_out_uop_is_rocc : _T_311 ? issue_slots_13_out_uop_is_rocc : issue_slots_12_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_sys_pc2epc = _T_312 ? issue_slots_14_out_uop_is_sys_pc2epc : _T_311 ? issue_slots_13_out_uop_is_sys_pc2epc : issue_slots_12_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_eret = _T_312 ? issue_slots_14_out_uop_is_eret : _T_311 ? issue_slots_13_out_uop_is_eret : issue_slots_12_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_amo = _T_312 ? issue_slots_14_out_uop_is_amo : _T_311 ? issue_slots_13_out_uop_is_amo : issue_slots_12_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_sfence = _T_312 ? issue_slots_14_out_uop_is_sfence : _T_311 ? issue_slots_13_out_uop_is_sfence : issue_slots_12_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_fencei = _T_312 ? issue_slots_14_out_uop_is_fencei : _T_311 ? issue_slots_13_out_uop_is_fencei : issue_slots_12_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_fence = _T_312 ? issue_slots_14_out_uop_is_fence : _T_311 ? issue_slots_13_out_uop_is_fence : issue_slots_12_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_sfb = _T_312 ? issue_slots_14_out_uop_is_sfb : _T_311 ? issue_slots_13_out_uop_is_sfb : issue_slots_12_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_br_type = _T_312 ? issue_slots_14_out_uop_br_type : _T_311 ? issue_slots_13_out_uop_br_type : issue_slots_12_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_br_tag = _T_312 ? issue_slots_14_out_uop_br_tag : _T_311 ? issue_slots_13_out_uop_br_tag : issue_slots_12_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_br_mask = _T_312 ? issue_slots_14_out_uop_br_mask : _T_311 ? issue_slots_13_out_uop_br_mask : issue_slots_12_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_dis_col_sel = _T_312 ? issue_slots_14_out_uop_dis_col_sel : _T_311 ? issue_slots_13_out_uop_dis_col_sel : issue_slots_12_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iw_p3_bypass_hint = _T_312 ? issue_slots_14_out_uop_iw_p3_bypass_hint : _T_311 ? issue_slots_13_out_uop_iw_p3_bypass_hint : issue_slots_12_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iw_p2_bypass_hint = _T_312 ? issue_slots_14_out_uop_iw_p2_bypass_hint : _T_311 ? issue_slots_13_out_uop_iw_p2_bypass_hint : issue_slots_12_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iw_p1_bypass_hint = _T_312 ? issue_slots_14_out_uop_iw_p1_bypass_hint : _T_311 ? issue_slots_13_out_uop_iw_p1_bypass_hint : issue_slots_12_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iw_p2_speculative_child = _T_312 ? issue_slots_14_out_uop_iw_p2_speculative_child : _T_311 ? issue_slots_13_out_uop_iw_p2_speculative_child : issue_slots_12_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iw_p1_speculative_child = _T_312 ? issue_slots_14_out_uop_iw_p1_speculative_child : _T_311 ? issue_slots_13_out_uop_iw_p1_speculative_child : issue_slots_12_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iw_issued = _T_312 ? issue_slots_14_out_uop_iw_issued : _T_311 ? issue_slots_13_out_uop_iw_issued : issue_slots_12_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_0 = _T_312 ? issue_slots_14_out_uop_fu_code_0 : _T_311 ? issue_slots_13_out_uop_fu_code_0 : issue_slots_12_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_1 = _T_312 ? issue_slots_14_out_uop_fu_code_1 : _T_311 ? issue_slots_13_out_uop_fu_code_1 : issue_slots_12_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_2 = _T_312 ? issue_slots_14_out_uop_fu_code_2 : _T_311 ? issue_slots_13_out_uop_fu_code_2 : issue_slots_12_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_3 = _T_312 ? issue_slots_14_out_uop_fu_code_3 : _T_311 ? issue_slots_13_out_uop_fu_code_3 : issue_slots_12_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_4 = _T_312 ? issue_slots_14_out_uop_fu_code_4 : _T_311 ? issue_slots_13_out_uop_fu_code_4 : issue_slots_12_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_5 = _T_312 ? issue_slots_14_out_uop_fu_code_5 : _T_311 ? issue_slots_13_out_uop_fu_code_5 : issue_slots_12_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_6 = _T_312 ? issue_slots_14_out_uop_fu_code_6 : _T_311 ? issue_slots_13_out_uop_fu_code_6 : issue_slots_12_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_7 = _T_312 ? issue_slots_14_out_uop_fu_code_7 : _T_311 ? issue_slots_13_out_uop_fu_code_7 : issue_slots_12_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_8 = _T_312 ? issue_slots_14_out_uop_fu_code_8 : _T_311 ? issue_slots_13_out_uop_fu_code_8 : issue_slots_12_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_9 = _T_312 ? issue_slots_14_out_uop_fu_code_9 : _T_311 ? issue_slots_13_out_uop_fu_code_9 : issue_slots_12_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iq_type_0 = _T_312 ? issue_slots_14_out_uop_iq_type_0 : _T_311 ? issue_slots_13_out_uop_iq_type_0 : issue_slots_12_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iq_type_1 = _T_312 ? issue_slots_14_out_uop_iq_type_1 : _T_311 ? issue_slots_13_out_uop_iq_type_1 : issue_slots_12_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iq_type_2 = _T_312 ? issue_slots_14_out_uop_iq_type_2 : _T_311 ? issue_slots_13_out_uop_iq_type_2 : issue_slots_12_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iq_type_3 = _T_312 ? issue_slots_14_out_uop_iq_type_3 : _T_311 ? issue_slots_13_out_uop_iq_type_3 : issue_slots_12_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_debug_pc = _T_312 ? issue_slots_14_out_uop_debug_pc : _T_311 ? issue_slots_13_out_uop_debug_pc : issue_slots_12_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_rvc = _T_312 ? issue_slots_14_out_uop_is_rvc : _T_311 ? issue_slots_13_out_uop_is_rvc : issue_slots_12_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_debug_inst = _T_312 ? issue_slots_14_out_uop_debug_inst : _T_311 ? issue_slots_13_out_uop_debug_inst : issue_slots_12_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_inst = _T_312 ? issue_slots_14_out_uop_inst : _T_311 ? issue_slots_13_out_uop_inst : issue_slots_12_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_11_clear_T = |shamts_oh_11; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_11_clear = _issue_slots_11_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_314 = shamts_oh_14 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_315 = shamts_oh_15 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_12_in_uop_valid = _T_315 ? issue_slots_15_will_be_valid : _T_314 ? issue_slots_14_will_be_valid : shamts_oh_13 == 3'h1 & issue_slots_13_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_12_in_uop_bits_debug_tsrc = _T_315 ? issue_slots_15_out_uop_debug_tsrc : _T_314 ? issue_slots_14_out_uop_debug_tsrc : issue_slots_13_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_debug_fsrc = _T_315 ? issue_slots_15_out_uop_debug_fsrc : _T_314 ? issue_slots_14_out_uop_debug_fsrc : issue_slots_13_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_bp_xcpt_if = _T_315 ? issue_slots_15_out_uop_bp_xcpt_if : _T_314 ? issue_slots_14_out_uop_bp_xcpt_if : issue_slots_13_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_bp_debug_if = _T_315 ? issue_slots_15_out_uop_bp_debug_if : _T_314 ? issue_slots_14_out_uop_bp_debug_if : issue_slots_13_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_xcpt_ma_if = _T_315 ? issue_slots_15_out_uop_xcpt_ma_if : _T_314 ? issue_slots_14_out_uop_xcpt_ma_if : issue_slots_13_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_xcpt_ae_if = _T_315 ? issue_slots_15_out_uop_xcpt_ae_if : _T_314 ? issue_slots_14_out_uop_xcpt_ae_if : issue_slots_13_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_xcpt_pf_if = _T_315 ? issue_slots_15_out_uop_xcpt_pf_if : _T_314 ? issue_slots_14_out_uop_xcpt_pf_if : issue_slots_13_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_typ = _T_315 ? issue_slots_15_out_uop_fp_typ : _T_314 ? issue_slots_14_out_uop_fp_typ : issue_slots_13_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_rm = _T_315 ? issue_slots_15_out_uop_fp_rm : _T_314 ? issue_slots_14_out_uop_fp_rm : issue_slots_13_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_val = _T_315 ? issue_slots_15_out_uop_fp_val : _T_314 ? issue_slots_14_out_uop_fp_val : issue_slots_13_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fcn_op = _T_315 ? issue_slots_15_out_uop_fcn_op : _T_314 ? issue_slots_14_out_uop_fcn_op : issue_slots_13_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fcn_dw = _T_315 ? issue_slots_15_out_uop_fcn_dw : _T_314 ? issue_slots_14_out_uop_fcn_dw : issue_slots_13_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_frs3_en = _T_315 ? issue_slots_15_out_uop_frs3_en : _T_314 ? issue_slots_14_out_uop_frs3_en : issue_slots_13_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_lrs2_rtype = _T_315 ? issue_slots_15_out_uop_lrs2_rtype : _T_314 ? issue_slots_14_out_uop_lrs2_rtype : issue_slots_13_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_lrs1_rtype = _T_315 ? issue_slots_15_out_uop_lrs1_rtype : _T_314 ? issue_slots_14_out_uop_lrs1_rtype : issue_slots_13_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_dst_rtype = _T_315 ? issue_slots_15_out_uop_dst_rtype : _T_314 ? issue_slots_14_out_uop_dst_rtype : issue_slots_13_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_lrs3 = _T_315 ? issue_slots_15_out_uop_lrs3 : _T_314 ? issue_slots_14_out_uop_lrs3 : issue_slots_13_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_lrs2 = _T_315 ? issue_slots_15_out_uop_lrs2 : _T_314 ? issue_slots_14_out_uop_lrs2 : issue_slots_13_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_lrs1 = _T_315 ? issue_slots_15_out_uop_lrs1 : _T_314 ? issue_slots_14_out_uop_lrs1 : issue_slots_13_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_ldst = _T_315 ? issue_slots_15_out_uop_ldst : _T_314 ? issue_slots_14_out_uop_ldst : issue_slots_13_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_ldst_is_rs1 = _T_315 ? issue_slots_15_out_uop_ldst_is_rs1 : _T_314 ? issue_slots_14_out_uop_ldst_is_rs1 : issue_slots_13_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_csr_cmd = _T_315 ? issue_slots_15_out_uop_csr_cmd : _T_314 ? issue_slots_14_out_uop_csr_cmd : issue_slots_13_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_flush_on_commit = _T_315 ? issue_slots_15_out_uop_flush_on_commit : _T_314 ? issue_slots_14_out_uop_flush_on_commit : issue_slots_13_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_unique = _T_315 ? issue_slots_15_out_uop_is_unique : _T_314 ? issue_slots_14_out_uop_is_unique : issue_slots_13_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_uses_stq = _T_315 ? issue_slots_15_out_uop_uses_stq : _T_314 ? issue_slots_14_out_uop_uses_stq : issue_slots_13_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_uses_ldq = _T_315 ? issue_slots_15_out_uop_uses_ldq : _T_314 ? issue_slots_14_out_uop_uses_ldq : issue_slots_13_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_mem_signed = _T_315 ? issue_slots_15_out_uop_mem_signed : _T_314 ? issue_slots_14_out_uop_mem_signed : issue_slots_13_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_mem_size = _T_315 ? issue_slots_15_out_uop_mem_size : _T_314 ? issue_slots_14_out_uop_mem_size : issue_slots_13_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_mem_cmd = _T_315 ? issue_slots_15_out_uop_mem_cmd : _T_314 ? issue_slots_14_out_uop_mem_cmd : issue_slots_13_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_exc_cause = _T_315 ? issue_slots_15_out_uop_exc_cause : _T_314 ? issue_slots_14_out_uop_exc_cause : issue_slots_13_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_exception = _T_315 ? issue_slots_15_out_uop_exception : _T_314 ? issue_slots_14_out_uop_exception : issue_slots_13_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_stale_pdst = _T_315 ? issue_slots_15_out_uop_stale_pdst : _T_314 ? issue_slots_14_out_uop_stale_pdst : issue_slots_13_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_ppred_busy = _T_315 ? issue_slots_15_out_uop_ppred_busy : _T_314 ? issue_slots_14_out_uop_ppred_busy : issue_slots_13_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_prs3_busy = _T_315 ? issue_slots_15_out_uop_prs3_busy : _T_314 ? issue_slots_14_out_uop_prs3_busy : issue_slots_13_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_prs2_busy = _T_315 ? issue_slots_15_out_uop_prs2_busy : _T_314 ? issue_slots_14_out_uop_prs2_busy : issue_slots_13_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_prs1_busy = _T_315 ? issue_slots_15_out_uop_prs1_busy : _T_314 ? issue_slots_14_out_uop_prs1_busy : issue_slots_13_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_ppred = _T_315 ? issue_slots_15_out_uop_ppred : _T_314 ? issue_slots_14_out_uop_ppred : issue_slots_13_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_prs3 = _T_315 ? issue_slots_15_out_uop_prs3 : _T_314 ? issue_slots_14_out_uop_prs3 : issue_slots_13_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_prs2 = _T_315 ? issue_slots_15_out_uop_prs2 : _T_314 ? issue_slots_14_out_uop_prs2 : issue_slots_13_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_prs1 = _T_315 ? issue_slots_15_out_uop_prs1 : _T_314 ? issue_slots_14_out_uop_prs1 : issue_slots_13_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_pdst = _T_315 ? issue_slots_15_out_uop_pdst : _T_314 ? issue_slots_14_out_uop_pdst : issue_slots_13_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_rxq_idx = _T_315 ? issue_slots_15_out_uop_rxq_idx : _T_314 ? issue_slots_14_out_uop_rxq_idx : issue_slots_13_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_stq_idx = _T_315 ? issue_slots_15_out_uop_stq_idx : _T_314 ? issue_slots_14_out_uop_stq_idx : issue_slots_13_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_ldq_idx = _T_315 ? issue_slots_15_out_uop_ldq_idx : _T_314 ? issue_slots_14_out_uop_ldq_idx : issue_slots_13_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_rob_idx = _T_315 ? issue_slots_15_out_uop_rob_idx : _T_314 ? issue_slots_14_out_uop_rob_idx : issue_slots_13_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_vec = _T_315 ? issue_slots_15_out_uop_fp_ctrl_vec : _T_314 ? issue_slots_14_out_uop_fp_ctrl_vec : issue_slots_13_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_wflags = _T_315 ? issue_slots_15_out_uop_fp_ctrl_wflags : _T_314 ? issue_slots_14_out_uop_fp_ctrl_wflags : issue_slots_13_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_sqrt = _T_315 ? issue_slots_15_out_uop_fp_ctrl_sqrt : _T_314 ? issue_slots_14_out_uop_fp_ctrl_sqrt : issue_slots_13_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_div = _T_315 ? issue_slots_15_out_uop_fp_ctrl_div : _T_314 ? issue_slots_14_out_uop_fp_ctrl_div : issue_slots_13_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_fma = _T_315 ? issue_slots_15_out_uop_fp_ctrl_fma : _T_314 ? issue_slots_14_out_uop_fp_ctrl_fma : issue_slots_13_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_fastpipe = _T_315 ? issue_slots_15_out_uop_fp_ctrl_fastpipe : _T_314 ? issue_slots_14_out_uop_fp_ctrl_fastpipe : issue_slots_13_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_toint = _T_315 ? issue_slots_15_out_uop_fp_ctrl_toint : _T_314 ? issue_slots_14_out_uop_fp_ctrl_toint : issue_slots_13_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_fromint = _T_315 ? issue_slots_15_out_uop_fp_ctrl_fromint : _T_314 ? issue_slots_14_out_uop_fp_ctrl_fromint : issue_slots_13_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_typeTagOut = _T_315 ? issue_slots_15_out_uop_fp_ctrl_typeTagOut : _T_314 ? issue_slots_14_out_uop_fp_ctrl_typeTagOut : issue_slots_13_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_typeTagIn = _T_315 ? issue_slots_15_out_uop_fp_ctrl_typeTagIn : _T_314 ? issue_slots_14_out_uop_fp_ctrl_typeTagIn : issue_slots_13_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_swap23 = _T_315 ? issue_slots_15_out_uop_fp_ctrl_swap23 : _T_314 ? issue_slots_14_out_uop_fp_ctrl_swap23 : issue_slots_13_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_swap12 = _T_315 ? issue_slots_15_out_uop_fp_ctrl_swap12 : _T_314 ? issue_slots_14_out_uop_fp_ctrl_swap12 : issue_slots_13_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_ren3 = _T_315 ? issue_slots_15_out_uop_fp_ctrl_ren3 : _T_314 ? issue_slots_14_out_uop_fp_ctrl_ren3 : issue_slots_13_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_ren2 = _T_315 ? issue_slots_15_out_uop_fp_ctrl_ren2 : _T_314 ? issue_slots_14_out_uop_fp_ctrl_ren2 : issue_slots_13_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_ren1 = _T_315 ? issue_slots_15_out_uop_fp_ctrl_ren1 : _T_314 ? issue_slots_14_out_uop_fp_ctrl_ren1 : issue_slots_13_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_wen = _T_315 ? issue_slots_15_out_uop_fp_ctrl_wen : _T_314 ? issue_slots_14_out_uop_fp_ctrl_wen : issue_slots_13_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_ldst = _T_315 ? issue_slots_15_out_uop_fp_ctrl_ldst : _T_314 ? issue_slots_14_out_uop_fp_ctrl_ldst : issue_slots_13_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_op2_sel = _T_315 ? issue_slots_15_out_uop_op2_sel : _T_314 ? issue_slots_14_out_uop_op2_sel : issue_slots_13_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_op1_sel = _T_315 ? issue_slots_15_out_uop_op1_sel : _T_314 ? issue_slots_14_out_uop_op1_sel : issue_slots_13_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_imm_packed = _T_315 ? issue_slots_15_out_uop_imm_packed : _T_314 ? issue_slots_14_out_uop_imm_packed : issue_slots_13_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_pimm = _T_315 ? issue_slots_15_out_uop_pimm : _T_314 ? issue_slots_14_out_uop_pimm : issue_slots_13_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_imm_sel = _T_315 ? issue_slots_15_out_uop_imm_sel : _T_314 ? issue_slots_14_out_uop_imm_sel : issue_slots_13_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_imm_rename = _T_315 ? issue_slots_15_out_uop_imm_rename : _T_314 ? issue_slots_14_out_uop_imm_rename : issue_slots_13_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_taken = _T_315 ? issue_slots_15_out_uop_taken : _T_314 ? issue_slots_14_out_uop_taken : issue_slots_13_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_pc_lob = _T_315 ? issue_slots_15_out_uop_pc_lob : _T_314 ? issue_slots_14_out_uop_pc_lob : issue_slots_13_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_edge_inst = _T_315 ? issue_slots_15_out_uop_edge_inst : _T_314 ? issue_slots_14_out_uop_edge_inst : issue_slots_13_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_ftq_idx = _T_315 ? issue_slots_15_out_uop_ftq_idx : _T_314 ? issue_slots_14_out_uop_ftq_idx : issue_slots_13_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_mov = _T_315 ? issue_slots_15_out_uop_is_mov : _T_314 ? issue_slots_14_out_uop_is_mov : issue_slots_13_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_rocc = _T_315 ? issue_slots_15_out_uop_is_rocc : _T_314 ? issue_slots_14_out_uop_is_rocc : issue_slots_13_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_sys_pc2epc = _T_315 ? issue_slots_15_out_uop_is_sys_pc2epc : _T_314 ? issue_slots_14_out_uop_is_sys_pc2epc : issue_slots_13_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_eret = _T_315 ? issue_slots_15_out_uop_is_eret : _T_314 ? issue_slots_14_out_uop_is_eret : issue_slots_13_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_amo = _T_315 ? issue_slots_15_out_uop_is_amo : _T_314 ? issue_slots_14_out_uop_is_amo : issue_slots_13_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_sfence = _T_315 ? issue_slots_15_out_uop_is_sfence : _T_314 ? issue_slots_14_out_uop_is_sfence : issue_slots_13_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_fencei = _T_315 ? issue_slots_15_out_uop_is_fencei : _T_314 ? issue_slots_14_out_uop_is_fencei : issue_slots_13_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_fence = _T_315 ? issue_slots_15_out_uop_is_fence : _T_314 ? issue_slots_14_out_uop_is_fence : issue_slots_13_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_sfb = _T_315 ? issue_slots_15_out_uop_is_sfb : _T_314 ? issue_slots_14_out_uop_is_sfb : issue_slots_13_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_br_type = _T_315 ? issue_slots_15_out_uop_br_type : _T_314 ? issue_slots_14_out_uop_br_type : issue_slots_13_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_br_tag = _T_315 ? issue_slots_15_out_uop_br_tag : _T_314 ? issue_slots_14_out_uop_br_tag : issue_slots_13_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_br_mask = _T_315 ? issue_slots_15_out_uop_br_mask : _T_314 ? issue_slots_14_out_uop_br_mask : issue_slots_13_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_dis_col_sel = _T_315 ? issue_slots_15_out_uop_dis_col_sel : _T_314 ? issue_slots_14_out_uop_dis_col_sel : issue_slots_13_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_iw_p3_bypass_hint = _T_315 ? issue_slots_15_out_uop_iw_p3_bypass_hint : _T_314 ? issue_slots_14_out_uop_iw_p3_bypass_hint : issue_slots_13_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_iw_p2_bypass_hint = _T_315 ? issue_slots_15_out_uop_iw_p2_bypass_hint : _T_314 ? issue_slots_14_out_uop_iw_p2_bypass_hint : issue_slots_13_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_iw_p1_bypass_hint = _T_315 ? issue_slots_15_out_uop_iw_p1_bypass_hint : _T_314 ? issue_slots_14_out_uop_iw_p1_bypass_hint : issue_slots_13_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_iw_p2_speculative_child = _T_315 ? issue_slots_15_out_uop_iw_p2_speculative_child : _T_314 ? issue_slots_14_out_uop_iw_p2_speculative_child : issue_slots_13_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_iw_p1_speculative_child = _T_315 ? issue_slots_15_out_uop_iw_p1_speculative_child : _T_314 ? issue_slots_14_out_uop_iw_p1_speculative_child : issue_slots_13_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_iw_issued = _T_315 ? issue_slots_15_out_uop_iw_issued : _T_314 ? issue_slots_14_out_uop_iw_issued : issue_slots_13_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fu_code_0 = _T_315 ? issue_slots_15_out_uop_fu_code_0 : _T_314 ? issue_slots_14_out_uop_fu_code_0 : issue_slots_13_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fu_code_1 = _T_315 ? issue_slots_15_out_uop_fu_code_1 : _T_314 ? issue_slots_14_out_uop_fu_code_1 : issue_slots_13_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fu_code_2 = _T_315 ? issue_slots_15_out_uop_fu_code_2 : _T_314 ? issue_slots_14_out_uop_fu_code_2 : issue_slots_13_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fu_code_3 = _T_315 ? issue_slots_15_out_uop_fu_code_3 : _T_314 ? issue_slots_14_out_uop_fu_code_3 : issue_slots_13_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fu_code_4 = _T_315 ? issue_slots_15_out_uop_fu_code_4 : _T_314 ? issue_slots_14_out_uop_fu_code_4 : issue_slots_13_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fu_code_5 = _T_315 ? issue_slots_15_out_uop_fu_code_5 : _T_314 ? issue_slots_14_out_uop_fu_code_5 : issue_slots_13_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fu_code_6 = _T_315 ? issue_slots_15_out_uop_fu_code_6 : _T_314 ? issue_slots_14_out_uop_fu_code_6 : issue_slots_13_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fu_code_7 = _T_315 ? issue_slots_15_out_uop_fu_code_7 : _T_314 ? issue_slots_14_out_uop_fu_code_7 : issue_slots_13_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fu_code_8 = _T_315 ? issue_slots_15_out_uop_fu_code_8 : _T_314 ? issue_slots_14_out_uop_fu_code_8 : issue_slots_13_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fu_code_9 = _T_315 ? issue_slots_15_out_uop_fu_code_9 : _T_314 ? issue_slots_14_out_uop_fu_code_9 : issue_slots_13_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_iq_type_0 = _T_315 ? issue_slots_15_out_uop_iq_type_0 : _T_314 ? issue_slots_14_out_uop_iq_type_0 : issue_slots_13_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_iq_type_1 = _T_315 ? issue_slots_15_out_uop_iq_type_1 : _T_314 ? issue_slots_14_out_uop_iq_type_1 : issue_slots_13_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_iq_type_2 = _T_315 ? issue_slots_15_out_uop_iq_type_2 : _T_314 ? issue_slots_14_out_uop_iq_type_2 : issue_slots_13_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_iq_type_3 = _T_315 ? issue_slots_15_out_uop_iq_type_3 : _T_314 ? issue_slots_14_out_uop_iq_type_3 : issue_slots_13_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_debug_pc = _T_315 ? issue_slots_15_out_uop_debug_pc : _T_314 ? issue_slots_14_out_uop_debug_pc : issue_slots_13_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_rvc = _T_315 ? issue_slots_15_out_uop_is_rvc : _T_314 ? issue_slots_14_out_uop_is_rvc : issue_slots_13_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_debug_inst = _T_315 ? issue_slots_15_out_uop_debug_inst : _T_314 ? issue_slots_14_out_uop_debug_inst : issue_slots_13_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_inst = _T_315 ? issue_slots_15_out_uop_inst : _T_314 ? issue_slots_14_out_uop_inst : issue_slots_13_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_12_clear_T = |shamts_oh_12; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_12_clear = _issue_slots_12_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_317 = shamts_oh_15 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_318 = shamts_oh_16 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_13_in_uop_valid = _T_318 ? will_be_valid_16 : _T_317 ? issue_slots_15_will_be_valid : shamts_oh_14 == 3'h1 & issue_slots_14_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :186:79, :191:33, :194:{28,48}, :195:37] assign issue_slots_13_in_uop_bits_debug_tsrc = _T_318 ? io_dis_uops_0_bits_debug_tsrc_0 : _T_317 ? issue_slots_15_out_uop_debug_tsrc : issue_slots_14_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_debug_fsrc = _T_318 ? io_dis_uops_0_bits_debug_fsrc_0 : _T_317 ? issue_slots_15_out_uop_debug_fsrc : issue_slots_14_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_bp_xcpt_if = _T_318 ? io_dis_uops_0_bits_bp_xcpt_if_0 : _T_317 ? issue_slots_15_out_uop_bp_xcpt_if : issue_slots_14_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_bp_debug_if = _T_318 ? io_dis_uops_0_bits_bp_debug_if_0 : _T_317 ? issue_slots_15_out_uop_bp_debug_if : issue_slots_14_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_xcpt_ma_if = _T_318 ? io_dis_uops_0_bits_xcpt_ma_if_0 : _T_317 ? issue_slots_15_out_uop_xcpt_ma_if : issue_slots_14_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_xcpt_ae_if = _T_318 ? io_dis_uops_0_bits_xcpt_ae_if_0 : _T_317 ? issue_slots_15_out_uop_xcpt_ae_if : issue_slots_14_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_xcpt_pf_if = _T_318 ? io_dis_uops_0_bits_xcpt_pf_if_0 : _T_317 ? issue_slots_15_out_uop_xcpt_pf_if : issue_slots_14_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_typ = _T_318 ? io_dis_uops_0_bits_fp_typ_0 : _T_317 ? issue_slots_15_out_uop_fp_typ : issue_slots_14_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_rm = _T_318 ? io_dis_uops_0_bits_fp_rm_0 : _T_317 ? issue_slots_15_out_uop_fp_rm : issue_slots_14_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_val = _T_318 ? io_dis_uops_0_bits_fp_val_0 : _T_317 ? issue_slots_15_out_uop_fp_val : issue_slots_14_out_uop_fp_val; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fcn_op = _T_318 ? io_dis_uops_0_bits_fcn_op_0 : _T_317 ? issue_slots_15_out_uop_fcn_op : issue_slots_14_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fcn_dw = _T_318 ? io_dis_uops_0_bits_fcn_dw_0 : _T_317 ? issue_slots_15_out_uop_fcn_dw : issue_slots_14_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_frs3_en = _T_318 ? io_dis_uops_0_bits_frs3_en_0 : _T_317 ? issue_slots_15_out_uop_frs3_en : issue_slots_14_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_lrs2_rtype = _T_318 ? io_dis_uops_0_bits_lrs2_rtype_0 : _T_317 ? issue_slots_15_out_uop_lrs2_rtype : issue_slots_14_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_lrs1_rtype = _T_318 ? io_dis_uops_0_bits_lrs1_rtype_0 : _T_317 ? issue_slots_15_out_uop_lrs1_rtype : issue_slots_14_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_dst_rtype = _T_318 ? io_dis_uops_0_bits_dst_rtype_0 : _T_317 ? issue_slots_15_out_uop_dst_rtype : issue_slots_14_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_lrs3 = _T_318 ? io_dis_uops_0_bits_lrs3_0 : _T_317 ? issue_slots_15_out_uop_lrs3 : issue_slots_14_out_uop_lrs3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_lrs2 = _T_318 ? io_dis_uops_0_bits_lrs2_0 : _T_317 ? issue_slots_15_out_uop_lrs2 : issue_slots_14_out_uop_lrs2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_lrs1 = _T_318 ? io_dis_uops_0_bits_lrs1_0 : _T_317 ? issue_slots_15_out_uop_lrs1 : issue_slots_14_out_uop_lrs1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_ldst = _T_318 ? io_dis_uops_0_bits_ldst_0 : _T_317 ? issue_slots_15_out_uop_ldst : issue_slots_14_out_uop_ldst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_ldst_is_rs1 = _T_318 ? io_dis_uops_0_bits_ldst_is_rs1_0 : _T_317 ? issue_slots_15_out_uop_ldst_is_rs1 : issue_slots_14_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_csr_cmd = _T_318 ? io_dis_uops_0_bits_csr_cmd_0 : _T_317 ? issue_slots_15_out_uop_csr_cmd : issue_slots_14_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_flush_on_commit = _T_318 ? io_dis_uops_0_bits_flush_on_commit_0 : _T_317 ? issue_slots_15_out_uop_flush_on_commit : issue_slots_14_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_unique = _T_318 ? io_dis_uops_0_bits_is_unique_0 : _T_317 ? issue_slots_15_out_uop_is_unique : issue_slots_14_out_uop_is_unique; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_uses_stq = _T_318 ? io_dis_uops_0_bits_uses_stq_0 : _T_317 ? issue_slots_15_out_uop_uses_stq : issue_slots_14_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_uses_ldq = _T_318 ? io_dis_uops_0_bits_uses_ldq_0 : _T_317 ? issue_slots_15_out_uop_uses_ldq : issue_slots_14_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_mem_signed = _T_318 ? io_dis_uops_0_bits_mem_signed_0 : _T_317 ? issue_slots_15_out_uop_mem_signed : issue_slots_14_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_mem_size = _T_318 ? io_dis_uops_0_bits_mem_size_0 : _T_317 ? issue_slots_15_out_uop_mem_size : issue_slots_14_out_uop_mem_size; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_mem_cmd = _T_318 ? io_dis_uops_0_bits_mem_cmd_0 : _T_317 ? issue_slots_15_out_uop_mem_cmd : issue_slots_14_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_exc_cause = _T_318 ? io_dis_uops_0_bits_exc_cause_0 : _T_317 ? issue_slots_15_out_uop_exc_cause : issue_slots_14_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_exception = _T_318 ? io_dis_uops_0_bits_exception_0 : _T_317 ? issue_slots_15_out_uop_exception : issue_slots_14_out_uop_exception; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_stale_pdst = _T_318 ? io_dis_uops_0_bits_stale_pdst_0 : _T_317 ? issue_slots_15_out_uop_stale_pdst : issue_slots_14_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_ppred_busy = ~_T_318 & (_T_317 ? issue_slots_15_out_uop_ppred_busy : issue_slots_14_out_uop_ppred_busy); // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_prs3_busy = _T_318 ? _WIRE_prs3_busy : _T_317 ? issue_slots_15_out_uop_prs3_busy : issue_slots_14_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:35:17, :76:38, :77:29, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_prs2_busy = _T_318 ? _WIRE_prs2_busy : _T_317 ? issue_slots_15_out_uop_prs2_busy : issue_slots_14_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:65:38, :71:116, :72:29, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_prs1_busy = _T_318 ? _WIRE_prs1_busy : _T_317 ? issue_slots_15_out_uop_prs1_busy : issue_slots_14_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:57:38, :62:116, :63:29, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_ppred = _T_318 ? io_dis_uops_0_bits_ppred_0 : _T_317 ? issue_slots_15_out_uop_ppred : issue_slots_14_out_uop_ppred; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_prs3 = _T_318 ? io_dis_uops_0_bits_prs3_0 : _T_317 ? issue_slots_15_out_uop_prs3 : issue_slots_14_out_uop_prs3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_prs2 = _T_318 ? _WIRE_prs2 : _T_317 ? issue_slots_15_out_uop_prs2 : issue_slots_14_out_uop_prs2; // @[issue-unit-age-ordered.scala:35:17, :86:50, :87:26, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_prs1 = _T_318 ? io_dis_uops_0_bits_prs1_0 : _T_317 ? issue_slots_15_out_uop_prs1 : issue_slots_14_out_uop_prs1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_pdst = _T_318 ? io_dis_uops_0_bits_pdst_0 : _T_317 ? issue_slots_15_out_uop_pdst : issue_slots_14_out_uop_pdst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_rxq_idx = _T_318 ? io_dis_uops_0_bits_rxq_idx_0 : _T_317 ? issue_slots_15_out_uop_rxq_idx : issue_slots_14_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_stq_idx = _T_318 ? io_dis_uops_0_bits_stq_idx_0 : _T_317 ? issue_slots_15_out_uop_stq_idx : issue_slots_14_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_ldq_idx = _T_318 ? io_dis_uops_0_bits_ldq_idx_0 : _T_317 ? issue_slots_15_out_uop_ldq_idx : issue_slots_14_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_rob_idx = _T_318 ? io_dis_uops_0_bits_rob_idx_0 : _T_317 ? issue_slots_15_out_uop_rob_idx : issue_slots_14_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_vec = _T_318 ? io_dis_uops_0_bits_fp_ctrl_vec_0 : _T_317 ? issue_slots_15_out_uop_fp_ctrl_vec : issue_slots_14_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_wflags = _T_318 ? io_dis_uops_0_bits_fp_ctrl_wflags_0 : _T_317 ? issue_slots_15_out_uop_fp_ctrl_wflags : issue_slots_14_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_sqrt = _T_318 ? io_dis_uops_0_bits_fp_ctrl_sqrt_0 : _T_317 ? issue_slots_15_out_uop_fp_ctrl_sqrt : issue_slots_14_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_div = _T_318 ? io_dis_uops_0_bits_fp_ctrl_div_0 : _T_317 ? issue_slots_15_out_uop_fp_ctrl_div : issue_slots_14_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_fma = _T_318 ? io_dis_uops_0_bits_fp_ctrl_fma_0 : _T_317 ? issue_slots_15_out_uop_fp_ctrl_fma : issue_slots_14_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_fastpipe = _T_318 ? io_dis_uops_0_bits_fp_ctrl_fastpipe_0 : _T_317 ? issue_slots_15_out_uop_fp_ctrl_fastpipe : issue_slots_14_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_toint = _T_318 ? io_dis_uops_0_bits_fp_ctrl_toint_0 : _T_317 ? issue_slots_15_out_uop_fp_ctrl_toint : issue_slots_14_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_fromint = _T_318 ? io_dis_uops_0_bits_fp_ctrl_fromint_0 : _T_317 ? issue_slots_15_out_uop_fp_ctrl_fromint : issue_slots_14_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_typeTagOut = _T_318 ? io_dis_uops_0_bits_fp_ctrl_typeTagOut_0 : _T_317 ? issue_slots_15_out_uop_fp_ctrl_typeTagOut : issue_slots_14_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_typeTagIn = _T_318 ? io_dis_uops_0_bits_fp_ctrl_typeTagIn_0 : _T_317 ? issue_slots_15_out_uop_fp_ctrl_typeTagIn : issue_slots_14_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_swap23 = _T_318 ? io_dis_uops_0_bits_fp_ctrl_swap23_0 : _T_317 ? issue_slots_15_out_uop_fp_ctrl_swap23 : issue_slots_14_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_swap12 = _T_318 ? io_dis_uops_0_bits_fp_ctrl_swap12_0 : _T_317 ? issue_slots_15_out_uop_fp_ctrl_swap12 : issue_slots_14_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_ren3 = _T_318 ? io_dis_uops_0_bits_fp_ctrl_ren3_0 : _T_317 ? issue_slots_15_out_uop_fp_ctrl_ren3 : issue_slots_14_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_ren2 = _T_318 ? io_dis_uops_0_bits_fp_ctrl_ren2_0 : _T_317 ? issue_slots_15_out_uop_fp_ctrl_ren2 : issue_slots_14_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_ren1 = _T_318 ? io_dis_uops_0_bits_fp_ctrl_ren1_0 : _T_317 ? issue_slots_15_out_uop_fp_ctrl_ren1 : issue_slots_14_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_wen = _T_318 ? io_dis_uops_0_bits_fp_ctrl_wen_0 : _T_317 ? issue_slots_15_out_uop_fp_ctrl_wen : issue_slots_14_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_ldst = _T_318 ? io_dis_uops_0_bits_fp_ctrl_ldst_0 : _T_317 ? issue_slots_15_out_uop_fp_ctrl_ldst : issue_slots_14_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_op2_sel = _T_318 ? io_dis_uops_0_bits_op2_sel_0 : _T_317 ? issue_slots_15_out_uop_op2_sel : issue_slots_14_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_op1_sel = _T_318 ? io_dis_uops_0_bits_op1_sel_0 : _T_317 ? issue_slots_15_out_uop_op1_sel : issue_slots_14_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_imm_packed = _T_318 ? io_dis_uops_0_bits_imm_packed_0 : _T_317 ? issue_slots_15_out_uop_imm_packed : issue_slots_14_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_pimm = _T_318 ? _WIRE_pimm : _T_317 ? issue_slots_15_out_uop_pimm : issue_slots_14_out_uop_pimm; // @[issue-unit-age-ordered.scala:35:17, :89:44, :90:26, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_imm_sel = _T_318 ? io_dis_uops_0_bits_imm_sel_0 : _T_317 ? issue_slots_15_out_uop_imm_sel : issue_slots_14_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_imm_rename = _T_318 ? io_dis_uops_0_bits_imm_rename_0 : _T_317 ? issue_slots_15_out_uop_imm_rename : issue_slots_14_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_taken = _T_318 ? io_dis_uops_0_bits_taken_0 : _T_317 ? issue_slots_15_out_uop_taken : issue_slots_14_out_uop_taken; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_pc_lob = _T_318 ? io_dis_uops_0_bits_pc_lob_0 : _T_317 ? issue_slots_15_out_uop_pc_lob : issue_slots_14_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_edge_inst = _T_318 ? io_dis_uops_0_bits_edge_inst_0 : _T_317 ? issue_slots_15_out_uop_edge_inst : issue_slots_14_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_ftq_idx = _T_318 ? io_dis_uops_0_bits_ftq_idx_0 : _T_317 ? issue_slots_15_out_uop_ftq_idx : issue_slots_14_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_mov = _T_318 ? io_dis_uops_0_bits_is_mov_0 : _T_317 ? issue_slots_15_out_uop_is_mov : issue_slots_14_out_uop_is_mov; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_rocc = _T_318 ? io_dis_uops_0_bits_is_rocc_0 : _T_317 ? issue_slots_15_out_uop_is_rocc : issue_slots_14_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_sys_pc2epc = _T_318 ? io_dis_uops_0_bits_is_sys_pc2epc_0 : _T_317 ? issue_slots_15_out_uop_is_sys_pc2epc : issue_slots_14_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_eret = _T_318 ? io_dis_uops_0_bits_is_eret_0 : _T_317 ? issue_slots_15_out_uop_is_eret : issue_slots_14_out_uop_is_eret; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_amo = _T_318 ? io_dis_uops_0_bits_is_amo_0 : _T_317 ? issue_slots_15_out_uop_is_amo : issue_slots_14_out_uop_is_amo; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_sfence = _T_318 ? io_dis_uops_0_bits_is_sfence_0 : _T_317 ? issue_slots_15_out_uop_is_sfence : issue_slots_14_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_fencei = _T_318 ? io_dis_uops_0_bits_is_fencei_0 : _T_317 ? issue_slots_15_out_uop_is_fencei : issue_slots_14_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_fence = _T_318 ? io_dis_uops_0_bits_is_fence_0 : _T_317 ? issue_slots_15_out_uop_is_fence : issue_slots_14_out_uop_is_fence; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_sfb = _T_318 ? io_dis_uops_0_bits_is_sfb_0 : _T_317 ? issue_slots_15_out_uop_is_sfb : issue_slots_14_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_br_type = _T_318 ? io_dis_uops_0_bits_br_type_0 : _T_317 ? issue_slots_15_out_uop_br_type : issue_slots_14_out_uop_br_type; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_br_tag = _T_318 ? io_dis_uops_0_bits_br_tag_0 : _T_317 ? issue_slots_15_out_uop_br_tag : issue_slots_14_out_uop_br_tag; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_br_mask = _T_318 ? io_dis_uops_0_bits_br_mask_0 : _T_317 ? issue_slots_15_out_uop_br_mask : issue_slots_14_out_uop_br_mask; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_dis_col_sel = _T_318 ? io_dis_uops_0_bits_dis_col_sel_0 : _T_317 ? issue_slots_15_out_uop_dis_col_sel : issue_slots_14_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_iw_p3_bypass_hint = _T_318 ? _WIRE_iw_p3_bypass_hint : _T_317 ? issue_slots_15_out_uop_iw_p3_bypass_hint : issue_slots_14_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:41:35, :76:38, :78:37, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_iw_p2_bypass_hint = _T_318 ? _WIRE_iw_p2_bypass_hint : _T_317 ? issue_slots_15_out_uop_iw_p2_bypass_hint : issue_slots_14_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:40:35, :65:38, :68:37, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_iw_p1_bypass_hint = _T_318 ? _WIRE_iw_p1_bypass_hint : _T_317 ? issue_slots_15_out_uop_iw_p1_bypass_hint : issue_slots_14_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:39:35, :57:38, :60:37, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_iw_p2_speculative_child = _T_318 ? _WIRE_iw_p2_speculative_child : _T_317 ? issue_slots_15_out_uop_iw_p2_speculative_child : issue_slots_14_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:35:17, :65:38, :67:43, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_iw_p1_speculative_child = _T_318 ? _WIRE_iw_p1_speculative_child : _T_317 ? issue_slots_15_out_uop_iw_p1_speculative_child : issue_slots_14_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:35:17, :57:38, :59:43, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_iw_issued = ~_T_318 & (_T_317 ? issue_slots_15_out_uop_iw_issued : issue_slots_14_out_uop_iw_issued); // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fu_code_0 = _T_318 ? io_dis_uops_0_bits_fu_code_0_0 : _T_317 ? issue_slots_15_out_uop_fu_code_0 : issue_slots_14_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fu_code_1 = _T_318 ? io_dis_uops_0_bits_fu_code_1_0 : _T_317 ? issue_slots_15_out_uop_fu_code_1 : issue_slots_14_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fu_code_2 = _T_318 ? io_dis_uops_0_bits_fu_code_2_0 : _T_317 ? issue_slots_15_out_uop_fu_code_2 : issue_slots_14_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fu_code_3 = _T_318 ? io_dis_uops_0_bits_fu_code_3_0 : _T_317 ? issue_slots_15_out_uop_fu_code_3 : issue_slots_14_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fu_code_4 = _T_318 ? io_dis_uops_0_bits_fu_code_4_0 : _T_317 ? issue_slots_15_out_uop_fu_code_4 : issue_slots_14_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fu_code_5 = _T_318 ? io_dis_uops_0_bits_fu_code_5_0 : _T_317 ? issue_slots_15_out_uop_fu_code_5 : issue_slots_14_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fu_code_6 = _T_318 ? io_dis_uops_0_bits_fu_code_6_0 : _T_317 ? issue_slots_15_out_uop_fu_code_6 : issue_slots_14_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fu_code_7 = _T_318 ? io_dis_uops_0_bits_fu_code_7_0 : _T_317 ? issue_slots_15_out_uop_fu_code_7 : issue_slots_14_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fu_code_8 = _T_318 ? io_dis_uops_0_bits_fu_code_8_0 : _T_317 ? issue_slots_15_out_uop_fu_code_8 : issue_slots_14_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fu_code_9 = _T_318 ? io_dis_uops_0_bits_fu_code_9_0 : _T_317 ? issue_slots_15_out_uop_fu_code_9 : issue_slots_14_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_iq_type_0 = _T_318 ? io_dis_uops_0_bits_iq_type_0_0 : _T_317 ? issue_slots_15_out_uop_iq_type_0 : issue_slots_14_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_iq_type_1 = _T_318 ? io_dis_uops_0_bits_iq_type_1_0 : _T_317 ? issue_slots_15_out_uop_iq_type_1 : issue_slots_14_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_iq_type_2 = _T_318 ? io_dis_uops_0_bits_iq_type_2_0 : _T_317 ? issue_slots_15_out_uop_iq_type_2 : issue_slots_14_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_iq_type_3 = _T_318 ? io_dis_uops_0_bits_iq_type_3_0 : _T_317 ? issue_slots_15_out_uop_iq_type_3 : issue_slots_14_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_debug_pc = _T_318 ? io_dis_uops_0_bits_debug_pc_0 : _T_317 ? issue_slots_15_out_uop_debug_pc : issue_slots_14_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_rvc = _T_318 ? io_dis_uops_0_bits_is_rvc_0 : _T_317 ? issue_slots_15_out_uop_is_rvc : issue_slots_14_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_debug_inst = _T_318 ? io_dis_uops_0_bits_debug_inst_0 : _T_317 ? issue_slots_15_out_uop_debug_inst : issue_slots_14_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_inst = _T_318 ? io_dis_uops_0_bits_inst_0 : _T_317 ? issue_slots_15_out_uop_inst : issue_slots_14_out_uop_inst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign _issue_slots_13_clear_T = |shamts_oh_13; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_13_clear = _issue_slots_13_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_320 = shamts_oh_16 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_321 = shamts_oh_17 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_14_in_uop_valid = _T_321 ? will_be_valid_17 : _T_320 ? will_be_valid_16 : shamts_oh_15 == 3'h1 & issue_slots_15_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :186:79, :191:33, :194:{28,48}, :195:37] assign issue_slots_14_in_uop_bits_debug_tsrc = _T_321 ? io_dis_uops_1_bits_debug_tsrc_0 : _T_320 ? io_dis_uops_0_bits_debug_tsrc_0 : issue_slots_15_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_debug_fsrc = _T_321 ? io_dis_uops_1_bits_debug_fsrc_0 : _T_320 ? io_dis_uops_0_bits_debug_fsrc_0 : issue_slots_15_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_bp_xcpt_if = _T_321 ? io_dis_uops_1_bits_bp_xcpt_if_0 : _T_320 ? io_dis_uops_0_bits_bp_xcpt_if_0 : issue_slots_15_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_bp_debug_if = _T_321 ? io_dis_uops_1_bits_bp_debug_if_0 : _T_320 ? io_dis_uops_0_bits_bp_debug_if_0 : issue_slots_15_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_xcpt_ma_if = _T_321 ? io_dis_uops_1_bits_xcpt_ma_if_0 : _T_320 ? io_dis_uops_0_bits_xcpt_ma_if_0 : issue_slots_15_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_xcpt_ae_if = _T_321 ? io_dis_uops_1_bits_xcpt_ae_if_0 : _T_320 ? io_dis_uops_0_bits_xcpt_ae_if_0 : issue_slots_15_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_xcpt_pf_if = _T_321 ? io_dis_uops_1_bits_xcpt_pf_if_0 : _T_320 ? io_dis_uops_0_bits_xcpt_pf_if_0 : issue_slots_15_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_typ = _T_321 ? io_dis_uops_1_bits_fp_typ_0 : _T_320 ? io_dis_uops_0_bits_fp_typ_0 : issue_slots_15_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_rm = _T_321 ? io_dis_uops_1_bits_fp_rm_0 : _T_320 ? io_dis_uops_0_bits_fp_rm_0 : issue_slots_15_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_val = _T_321 ? io_dis_uops_1_bits_fp_val_0 : _T_320 ? io_dis_uops_0_bits_fp_val_0 : issue_slots_15_out_uop_fp_val; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fcn_op = _T_321 ? io_dis_uops_1_bits_fcn_op_0 : _T_320 ? io_dis_uops_0_bits_fcn_op_0 : issue_slots_15_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fcn_dw = _T_321 ? io_dis_uops_1_bits_fcn_dw_0 : _T_320 ? io_dis_uops_0_bits_fcn_dw_0 : issue_slots_15_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_frs3_en = _T_321 ? io_dis_uops_1_bits_frs3_en_0 : _T_320 ? io_dis_uops_0_bits_frs3_en_0 : issue_slots_15_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_lrs2_rtype = _T_321 ? io_dis_uops_1_bits_lrs2_rtype_0 : _T_320 ? io_dis_uops_0_bits_lrs2_rtype_0 : issue_slots_15_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_lrs1_rtype = _T_321 ? io_dis_uops_1_bits_lrs1_rtype_0 : _T_320 ? io_dis_uops_0_bits_lrs1_rtype_0 : issue_slots_15_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_dst_rtype = _T_321 ? io_dis_uops_1_bits_dst_rtype_0 : _T_320 ? io_dis_uops_0_bits_dst_rtype_0 : issue_slots_15_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_lrs3 = _T_321 ? io_dis_uops_1_bits_lrs3_0 : _T_320 ? io_dis_uops_0_bits_lrs3_0 : issue_slots_15_out_uop_lrs3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_lrs2 = _T_321 ? io_dis_uops_1_bits_lrs2_0 : _T_320 ? io_dis_uops_0_bits_lrs2_0 : issue_slots_15_out_uop_lrs2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_lrs1 = _T_321 ? io_dis_uops_1_bits_lrs1_0 : _T_320 ? io_dis_uops_0_bits_lrs1_0 : issue_slots_15_out_uop_lrs1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_ldst = _T_321 ? io_dis_uops_1_bits_ldst_0 : _T_320 ? io_dis_uops_0_bits_ldst_0 : issue_slots_15_out_uop_ldst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_ldst_is_rs1 = _T_321 ? io_dis_uops_1_bits_ldst_is_rs1_0 : _T_320 ? io_dis_uops_0_bits_ldst_is_rs1_0 : issue_slots_15_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_csr_cmd = _T_321 ? io_dis_uops_1_bits_csr_cmd_0 : _T_320 ? io_dis_uops_0_bits_csr_cmd_0 : issue_slots_15_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_flush_on_commit = _T_321 ? io_dis_uops_1_bits_flush_on_commit_0 : _T_320 ? io_dis_uops_0_bits_flush_on_commit_0 : issue_slots_15_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_unique = _T_321 ? io_dis_uops_1_bits_is_unique_0 : _T_320 ? io_dis_uops_0_bits_is_unique_0 : issue_slots_15_out_uop_is_unique; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_uses_stq = _T_321 ? io_dis_uops_1_bits_uses_stq_0 : _T_320 ? io_dis_uops_0_bits_uses_stq_0 : issue_slots_15_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_uses_ldq = _T_321 ? io_dis_uops_1_bits_uses_ldq_0 : _T_320 ? io_dis_uops_0_bits_uses_ldq_0 : issue_slots_15_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_mem_signed = _T_321 ? io_dis_uops_1_bits_mem_signed_0 : _T_320 ? io_dis_uops_0_bits_mem_signed_0 : issue_slots_15_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_mem_size = _T_321 ? io_dis_uops_1_bits_mem_size_0 : _T_320 ? io_dis_uops_0_bits_mem_size_0 : issue_slots_15_out_uop_mem_size; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_mem_cmd = _T_321 ? io_dis_uops_1_bits_mem_cmd_0 : _T_320 ? io_dis_uops_0_bits_mem_cmd_0 : issue_slots_15_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_exc_cause = _T_321 ? io_dis_uops_1_bits_exc_cause_0 : _T_320 ? io_dis_uops_0_bits_exc_cause_0 : issue_slots_15_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_exception = _T_321 ? io_dis_uops_1_bits_exception_0 : _T_320 ? io_dis_uops_0_bits_exception_0 : issue_slots_15_out_uop_exception; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_stale_pdst = _T_321 ? io_dis_uops_1_bits_stale_pdst_0 : _T_320 ? io_dis_uops_0_bits_stale_pdst_0 : issue_slots_15_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] wire _GEN_0 = _T_321 | _T_320; // @[issue-unit-age-ordered.scala:194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_ppred_busy = ~_GEN_0 & issue_slots_15_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:48, :196:37] assign issue_slots_14_in_uop_bits_prs3_busy = _T_321 ? _WIRE_1_prs3_busy : _T_320 ? _WIRE_prs3_busy : issue_slots_15_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:35:17, :76:38, :77:29, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_prs2_busy = _T_321 ? _WIRE_1_prs2_busy : _T_320 ? _WIRE_prs2_busy : issue_slots_15_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:65:38, :71:116, :72:29, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_prs1_busy = _T_321 ? _WIRE_1_prs1_busy : _T_320 ? _WIRE_prs1_busy : issue_slots_15_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:57:38, :62:116, :63:29, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_ppred = _T_321 ? io_dis_uops_1_bits_ppred_0 : _T_320 ? io_dis_uops_0_bits_ppred_0 : issue_slots_15_out_uop_ppred; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_prs3 = _T_321 ? io_dis_uops_1_bits_prs3_0 : _T_320 ? io_dis_uops_0_bits_prs3_0 : issue_slots_15_out_uop_prs3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_prs2 = _T_321 ? _WIRE_1_prs2 : _T_320 ? _WIRE_prs2 : issue_slots_15_out_uop_prs2; // @[issue-unit-age-ordered.scala:35:17, :86:50, :87:26, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_prs1 = _T_321 ? io_dis_uops_1_bits_prs1_0 : _T_320 ? io_dis_uops_0_bits_prs1_0 : issue_slots_15_out_uop_prs1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_pdst = _T_321 ? io_dis_uops_1_bits_pdst_0 : _T_320 ? io_dis_uops_0_bits_pdst_0 : issue_slots_15_out_uop_pdst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_rxq_idx = _T_321 ? io_dis_uops_1_bits_rxq_idx_0 : _T_320 ? io_dis_uops_0_bits_rxq_idx_0 : issue_slots_15_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_stq_idx = _T_321 ? io_dis_uops_1_bits_stq_idx_0 : _T_320 ? io_dis_uops_0_bits_stq_idx_0 : issue_slots_15_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_ldq_idx = _T_321 ? io_dis_uops_1_bits_ldq_idx_0 : _T_320 ? io_dis_uops_0_bits_ldq_idx_0 : issue_slots_15_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_rob_idx = _T_321 ? io_dis_uops_1_bits_rob_idx_0 : _T_320 ? io_dis_uops_0_bits_rob_idx_0 : issue_slots_15_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_vec = _T_321 ? io_dis_uops_1_bits_fp_ctrl_vec_0 : _T_320 ? io_dis_uops_0_bits_fp_ctrl_vec_0 : issue_slots_15_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_wflags = _T_321 ? io_dis_uops_1_bits_fp_ctrl_wflags_0 : _T_320 ? io_dis_uops_0_bits_fp_ctrl_wflags_0 : issue_slots_15_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_sqrt = _T_321 ? io_dis_uops_1_bits_fp_ctrl_sqrt_0 : _T_320 ? io_dis_uops_0_bits_fp_ctrl_sqrt_0 : issue_slots_15_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_div = _T_321 ? io_dis_uops_1_bits_fp_ctrl_div_0 : _T_320 ? io_dis_uops_0_bits_fp_ctrl_div_0 : issue_slots_15_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_fma = _T_321 ? io_dis_uops_1_bits_fp_ctrl_fma_0 : _T_320 ? io_dis_uops_0_bits_fp_ctrl_fma_0 : issue_slots_15_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_fastpipe = _T_321 ? io_dis_uops_1_bits_fp_ctrl_fastpipe_0 : _T_320 ? io_dis_uops_0_bits_fp_ctrl_fastpipe_0 : issue_slots_15_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_toint = _T_321 ? io_dis_uops_1_bits_fp_ctrl_toint_0 : _T_320 ? io_dis_uops_0_bits_fp_ctrl_toint_0 : issue_slots_15_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_fromint = _T_321 ? io_dis_uops_1_bits_fp_ctrl_fromint_0 : _T_320 ? io_dis_uops_0_bits_fp_ctrl_fromint_0 : issue_slots_15_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_typeTagOut = _T_321 ? io_dis_uops_1_bits_fp_ctrl_typeTagOut_0 : _T_320 ? io_dis_uops_0_bits_fp_ctrl_typeTagOut_0 : issue_slots_15_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_typeTagIn = _T_321 ? io_dis_uops_1_bits_fp_ctrl_typeTagIn_0 : _T_320 ? io_dis_uops_0_bits_fp_ctrl_typeTagIn_0 : issue_slots_15_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_swap23 = _T_321 ? io_dis_uops_1_bits_fp_ctrl_swap23_0 : _T_320 ? io_dis_uops_0_bits_fp_ctrl_swap23_0 : issue_slots_15_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_swap12 = _T_321 ? io_dis_uops_1_bits_fp_ctrl_swap12_0 : _T_320 ? io_dis_uops_0_bits_fp_ctrl_swap12_0 : issue_slots_15_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_ren3 = _T_321 ? io_dis_uops_1_bits_fp_ctrl_ren3_0 : _T_320 ? io_dis_uops_0_bits_fp_ctrl_ren3_0 : issue_slots_15_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_ren2 = _T_321 ? io_dis_uops_1_bits_fp_ctrl_ren2_0 : _T_320 ? io_dis_uops_0_bits_fp_ctrl_ren2_0 : issue_slots_15_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_ren1 = _T_321 ? io_dis_uops_1_bits_fp_ctrl_ren1_0 : _T_320 ? io_dis_uops_0_bits_fp_ctrl_ren1_0 : issue_slots_15_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_wen = _T_321 ? io_dis_uops_1_bits_fp_ctrl_wen_0 : _T_320 ? io_dis_uops_0_bits_fp_ctrl_wen_0 : issue_slots_15_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_ldst = _T_321 ? io_dis_uops_1_bits_fp_ctrl_ldst_0 : _T_320 ? io_dis_uops_0_bits_fp_ctrl_ldst_0 : issue_slots_15_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_op2_sel = _T_321 ? io_dis_uops_1_bits_op2_sel_0 : _T_320 ? io_dis_uops_0_bits_op2_sel_0 : issue_slots_15_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_op1_sel = _T_321 ? io_dis_uops_1_bits_op1_sel_0 : _T_320 ? io_dis_uops_0_bits_op1_sel_0 : issue_slots_15_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_imm_packed = _T_321 ? io_dis_uops_1_bits_imm_packed_0 : _T_320 ? io_dis_uops_0_bits_imm_packed_0 : issue_slots_15_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_pimm = _T_321 ? _WIRE_1_pimm : _T_320 ? _WIRE_pimm : issue_slots_15_out_uop_pimm; // @[issue-unit-age-ordered.scala:35:17, :89:44, :90:26, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_imm_sel = _T_321 ? io_dis_uops_1_bits_imm_sel_0 : _T_320 ? io_dis_uops_0_bits_imm_sel_0 : issue_slots_15_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_imm_rename = _T_321 ? io_dis_uops_1_bits_imm_rename_0 : _T_320 ? io_dis_uops_0_bits_imm_rename_0 : issue_slots_15_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_taken = _T_321 ? io_dis_uops_1_bits_taken_0 : _T_320 ? io_dis_uops_0_bits_taken_0 : issue_slots_15_out_uop_taken; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_pc_lob = _T_321 ? io_dis_uops_1_bits_pc_lob_0 : _T_320 ? io_dis_uops_0_bits_pc_lob_0 : issue_slots_15_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_edge_inst = _T_321 ? io_dis_uops_1_bits_edge_inst_0 : _T_320 ? io_dis_uops_0_bits_edge_inst_0 : issue_slots_15_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_ftq_idx = _T_321 ? io_dis_uops_1_bits_ftq_idx_0 : _T_320 ? io_dis_uops_0_bits_ftq_idx_0 : issue_slots_15_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_mov = _T_321 ? io_dis_uops_1_bits_is_mov_0 : _T_320 ? io_dis_uops_0_bits_is_mov_0 : issue_slots_15_out_uop_is_mov; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_rocc = _T_321 ? io_dis_uops_1_bits_is_rocc_0 : _T_320 ? io_dis_uops_0_bits_is_rocc_0 : issue_slots_15_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_sys_pc2epc = _T_321 ? io_dis_uops_1_bits_is_sys_pc2epc_0 : _T_320 ? io_dis_uops_0_bits_is_sys_pc2epc_0 : issue_slots_15_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_eret = _T_321 ? io_dis_uops_1_bits_is_eret_0 : _T_320 ? io_dis_uops_0_bits_is_eret_0 : issue_slots_15_out_uop_is_eret; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_amo = _T_321 ? io_dis_uops_1_bits_is_amo_0 : _T_320 ? io_dis_uops_0_bits_is_amo_0 : issue_slots_15_out_uop_is_amo; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_sfence = _T_321 ? io_dis_uops_1_bits_is_sfence_0 : _T_320 ? io_dis_uops_0_bits_is_sfence_0 : issue_slots_15_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_fencei = _T_321 ? io_dis_uops_1_bits_is_fencei_0 : _T_320 ? io_dis_uops_0_bits_is_fencei_0 : issue_slots_15_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_fence = _T_321 ? io_dis_uops_1_bits_is_fence_0 : _T_320 ? io_dis_uops_0_bits_is_fence_0 : issue_slots_15_out_uop_is_fence; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_sfb = _T_321 ? io_dis_uops_1_bits_is_sfb_0 : _T_320 ? io_dis_uops_0_bits_is_sfb_0 : issue_slots_15_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_br_type = _T_321 ? io_dis_uops_1_bits_br_type_0 : _T_320 ? io_dis_uops_0_bits_br_type_0 : issue_slots_15_out_uop_br_type; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_br_tag = _T_321 ? io_dis_uops_1_bits_br_tag_0 : _T_320 ? io_dis_uops_0_bits_br_tag_0 : issue_slots_15_out_uop_br_tag; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_br_mask = _T_321 ? io_dis_uops_1_bits_br_mask_0 : _T_320 ? io_dis_uops_0_bits_br_mask_0 : issue_slots_15_out_uop_br_mask; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_dis_col_sel = _T_321 ? io_dis_uops_1_bits_dis_col_sel_0 : _T_320 ? io_dis_uops_0_bits_dis_col_sel_0 : issue_slots_15_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_iw_p3_bypass_hint = _T_321 ? _WIRE_1_iw_p3_bypass_hint : _T_320 ? _WIRE_iw_p3_bypass_hint : issue_slots_15_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:41:35, :76:38, :78:37, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_iw_p2_bypass_hint = _T_321 ? _WIRE_1_iw_p2_bypass_hint : _T_320 ? _WIRE_iw_p2_bypass_hint : issue_slots_15_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:40:35, :65:38, :68:37, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_iw_p1_bypass_hint = _T_321 ? _WIRE_1_iw_p1_bypass_hint : _T_320 ? _WIRE_iw_p1_bypass_hint : issue_slots_15_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:39:35, :57:38, :60:37, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_iw_p2_speculative_child = _T_321 ? _WIRE_1_iw_p2_speculative_child : _T_320 ? _WIRE_iw_p2_speculative_child : issue_slots_15_out_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:35:17, :65:38, :67:43, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_iw_p1_speculative_child = _T_321 ? _WIRE_1_iw_p1_speculative_child : _T_320 ? _WIRE_iw_p1_speculative_child : issue_slots_15_out_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:35:17, :57:38, :59:43, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_iw_issued = ~_GEN_0 & issue_slots_15_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:48, :196:37] assign issue_slots_14_in_uop_bits_fu_code_0 = _T_321 ? io_dis_uops_1_bits_fu_code_0_0 : _T_320 ? io_dis_uops_0_bits_fu_code_0_0 : issue_slots_15_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fu_code_1 = _T_321 ? io_dis_uops_1_bits_fu_code_1_0 : _T_320 ? io_dis_uops_0_bits_fu_code_1_0 : issue_slots_15_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fu_code_2 = _T_321 ? io_dis_uops_1_bits_fu_code_2_0 : _T_320 ? io_dis_uops_0_bits_fu_code_2_0 : issue_slots_15_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fu_code_3 = _T_321 ? io_dis_uops_1_bits_fu_code_3_0 : _T_320 ? io_dis_uops_0_bits_fu_code_3_0 : issue_slots_15_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fu_code_4 = _T_321 ? io_dis_uops_1_bits_fu_code_4_0 : _T_320 ? io_dis_uops_0_bits_fu_code_4_0 : issue_slots_15_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fu_code_5 = _T_321 ? io_dis_uops_1_bits_fu_code_5_0 : _T_320 ? io_dis_uops_0_bits_fu_code_5_0 : issue_slots_15_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fu_code_6 = _T_321 ? io_dis_uops_1_bits_fu_code_6_0 : _T_320 ? io_dis_uops_0_bits_fu_code_6_0 : issue_slots_15_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fu_code_7 = _T_321 ? io_dis_uops_1_bits_fu_code_7_0 : _T_320 ? io_dis_uops_0_bits_fu_code_7_0 : issue_slots_15_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fu_code_8 = _T_321 ? io_dis_uops_1_bits_fu_code_8_0 : _T_320 ? io_dis_uops_0_bits_fu_code_8_0 : issue_slots_15_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fu_code_9 = _T_321 ? io_dis_uops_1_bits_fu_code_9_0 : _T_320 ? io_dis_uops_0_bits_fu_code_9_0 : issue_slots_15_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_iq_type_0 = _T_321 ? io_dis_uops_1_bits_iq_type_0_0 : _T_320 ? io_dis_uops_0_bits_iq_type_0_0 : issue_slots_15_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_iq_type_1 = _T_321 ? io_dis_uops_1_bits_iq_type_1_0 : _T_320 ? io_dis_uops_0_bits_iq_type_1_0 : issue_slots_15_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_iq_type_2 = _T_321 ? io_dis_uops_1_bits_iq_type_2_0 : _T_320 ? io_dis_uops_0_bits_iq_type_2_0 : issue_slots_15_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_iq_type_3 = _T_321 ? io_dis_uops_1_bits_iq_type_3_0 : _T_320 ? io_dis_uops_0_bits_iq_type_3_0 : issue_slots_15_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_debug_pc = _T_321 ? io_dis_uops_1_bits_debug_pc_0 : _T_320 ? io_dis_uops_0_bits_debug_pc_0 : issue_slots_15_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_rvc = _T_321 ? io_dis_uops_1_bits_is_rvc_0 : _T_320 ? io_dis_uops_0_bits_is_rvc_0 : issue_slots_15_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_debug_inst = _T_321 ? io_dis_uops_1_bits_debug_inst_0 : _T_320 ? io_dis_uops_0_bits_debug_inst_0 : issue_slots_15_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_inst = _T_321 ? io_dis_uops_1_bits_inst_0 : _T_320 ? io_dis_uops_0_bits_inst_0 : issue_slots_15_out_uop_inst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign _issue_slots_14_clear_T = |shamts_oh_14; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_14_clear = _issue_slots_14_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_323 = shamts_oh_17 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_324 = shamts_oh_18 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_15_in_uop_valid = _T_324 ? will_be_valid_18 : _T_323 ? will_be_valid_17 : shamts_oh_16 == 3'h1 & will_be_valid_16; // @[issue-unit-age-ordered.scala:122:28, :158:23, :186:79, :191:33, :194:{28,48}, :195:37] assign issue_slots_15_in_uop_bits_debug_tsrc = _T_324 ? io_dis_uops_2_bits_debug_tsrc_0 : _T_323 ? io_dis_uops_1_bits_debug_tsrc_0 : io_dis_uops_0_bits_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_debug_fsrc = _T_324 ? io_dis_uops_2_bits_debug_fsrc_0 : _T_323 ? io_dis_uops_1_bits_debug_fsrc_0 : io_dis_uops_0_bits_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_bp_xcpt_if = _T_324 ? io_dis_uops_2_bits_bp_xcpt_if_0 : _T_323 ? io_dis_uops_1_bits_bp_xcpt_if_0 : io_dis_uops_0_bits_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_bp_debug_if = _T_324 ? io_dis_uops_2_bits_bp_debug_if_0 : _T_323 ? io_dis_uops_1_bits_bp_debug_if_0 : io_dis_uops_0_bits_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_xcpt_ma_if = _T_324 ? io_dis_uops_2_bits_xcpt_ma_if_0 : _T_323 ? io_dis_uops_1_bits_xcpt_ma_if_0 : io_dis_uops_0_bits_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_xcpt_ae_if = _T_324 ? io_dis_uops_2_bits_xcpt_ae_if_0 : _T_323 ? io_dis_uops_1_bits_xcpt_ae_if_0 : io_dis_uops_0_bits_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_xcpt_pf_if = _T_324 ? io_dis_uops_2_bits_xcpt_pf_if_0 : _T_323 ? io_dis_uops_1_bits_xcpt_pf_if_0 : io_dis_uops_0_bits_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_typ = _T_324 ? io_dis_uops_2_bits_fp_typ_0 : _T_323 ? io_dis_uops_1_bits_fp_typ_0 : io_dis_uops_0_bits_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_rm = _T_324 ? io_dis_uops_2_bits_fp_rm_0 : _T_323 ? io_dis_uops_1_bits_fp_rm_0 : io_dis_uops_0_bits_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_val = _T_324 ? io_dis_uops_2_bits_fp_val_0 : _T_323 ? io_dis_uops_1_bits_fp_val_0 : io_dis_uops_0_bits_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fcn_op = _T_324 ? io_dis_uops_2_bits_fcn_op_0 : _T_323 ? io_dis_uops_1_bits_fcn_op_0 : io_dis_uops_0_bits_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fcn_dw = _T_324 ? io_dis_uops_2_bits_fcn_dw_0 : _T_323 ? io_dis_uops_1_bits_fcn_dw_0 : io_dis_uops_0_bits_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_frs3_en = _T_324 ? io_dis_uops_2_bits_frs3_en_0 : _T_323 ? io_dis_uops_1_bits_frs3_en_0 : io_dis_uops_0_bits_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_lrs2_rtype = _T_324 ? io_dis_uops_2_bits_lrs2_rtype_0 : _T_323 ? io_dis_uops_1_bits_lrs2_rtype_0 : io_dis_uops_0_bits_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_lrs1_rtype = _T_324 ? io_dis_uops_2_bits_lrs1_rtype_0 : _T_323 ? io_dis_uops_1_bits_lrs1_rtype_0 : io_dis_uops_0_bits_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_dst_rtype = _T_324 ? io_dis_uops_2_bits_dst_rtype_0 : _T_323 ? io_dis_uops_1_bits_dst_rtype_0 : io_dis_uops_0_bits_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_lrs3 = _T_324 ? io_dis_uops_2_bits_lrs3_0 : _T_323 ? io_dis_uops_1_bits_lrs3_0 : io_dis_uops_0_bits_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_lrs2 = _T_324 ? io_dis_uops_2_bits_lrs2_0 : _T_323 ? io_dis_uops_1_bits_lrs2_0 : io_dis_uops_0_bits_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_lrs1 = _T_324 ? io_dis_uops_2_bits_lrs1_0 : _T_323 ? io_dis_uops_1_bits_lrs1_0 : io_dis_uops_0_bits_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_ldst = _T_324 ? io_dis_uops_2_bits_ldst_0 : _T_323 ? io_dis_uops_1_bits_ldst_0 : io_dis_uops_0_bits_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_ldst_is_rs1 = _T_324 ? io_dis_uops_2_bits_ldst_is_rs1_0 : _T_323 ? io_dis_uops_1_bits_ldst_is_rs1_0 : io_dis_uops_0_bits_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_csr_cmd = _T_324 ? io_dis_uops_2_bits_csr_cmd_0 : _T_323 ? io_dis_uops_1_bits_csr_cmd_0 : io_dis_uops_0_bits_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_flush_on_commit = _T_324 ? io_dis_uops_2_bits_flush_on_commit_0 : _T_323 ? io_dis_uops_1_bits_flush_on_commit_0 : io_dis_uops_0_bits_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_unique = _T_324 ? io_dis_uops_2_bits_is_unique_0 : _T_323 ? io_dis_uops_1_bits_is_unique_0 : io_dis_uops_0_bits_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_uses_stq = _T_324 ? io_dis_uops_2_bits_uses_stq_0 : _T_323 ? io_dis_uops_1_bits_uses_stq_0 : io_dis_uops_0_bits_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_uses_ldq = _T_324 ? io_dis_uops_2_bits_uses_ldq_0 : _T_323 ? io_dis_uops_1_bits_uses_ldq_0 : io_dis_uops_0_bits_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_mem_signed = _T_324 ? io_dis_uops_2_bits_mem_signed_0 : _T_323 ? io_dis_uops_1_bits_mem_signed_0 : io_dis_uops_0_bits_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_mem_size = _T_324 ? io_dis_uops_2_bits_mem_size_0 : _T_323 ? io_dis_uops_1_bits_mem_size_0 : io_dis_uops_0_bits_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_mem_cmd = _T_324 ? io_dis_uops_2_bits_mem_cmd_0 : _T_323 ? io_dis_uops_1_bits_mem_cmd_0 : io_dis_uops_0_bits_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_exc_cause = _T_324 ? io_dis_uops_2_bits_exc_cause_0 : _T_323 ? io_dis_uops_1_bits_exc_cause_0 : io_dis_uops_0_bits_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_exception = _T_324 ? io_dis_uops_2_bits_exception_0 : _T_323 ? io_dis_uops_1_bits_exception_0 : io_dis_uops_0_bits_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_stale_pdst = _T_324 ? io_dis_uops_2_bits_stale_pdst_0 : _T_323 ? io_dis_uops_1_bits_stale_pdst_0 : io_dis_uops_0_bits_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_prs3_busy = _T_324 ? ~_T_225 & io_dis_uops_2_bits_prs3_busy_0 : _T_323 ? _WIRE_1_prs3_busy : _WIRE_prs3_busy; // @[issue-unit-age-ordered.scala:22:7, :35:17, :76:{32,38}, :77:29, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_prs2_busy = _T_324 ? ((|{prs2_rebusys_0_2, io_child_rebusys_0 & io_dis_uops_2_bits_iw_p2_speculative_child_0}) ? io_dis_uops_2_bits_lrs2_rtype_0 == 2'h0 : ~_T_195 & io_dis_uops_2_bits_prs2_busy_0) : _T_323 ? _WIRE_1_prs2_busy : _WIRE_prs2_busy; // @[issue-unit-age-ordered.scala:22:7, :35:17, :51:95, :65:{32,38}, :66:29, :71:{37,59,106,116}, :72:{29,63}, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_prs1_busy = _T_324 ? ((|{prs1_rebusys_0_2, io_child_rebusys_0 & io_dis_uops_2_bits_iw_p1_speculative_child_0}) ? io_dis_uops_2_bits_lrs1_rtype_0 == 2'h0 : ~_T_165 & io_dis_uops_2_bits_prs1_busy_0) : _T_323 ? _WIRE_1_prs1_busy : _WIRE_prs1_busy; // @[issue-unit-age-ordered.scala:22:7, :35:17, :50:95, :57:{32,38}, :58:29, :62:{37,59,106,116}, :63:{29,63}, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_ppred = _T_324 ? io_dis_uops_2_bits_ppred_0 : _T_323 ? io_dis_uops_1_bits_ppred_0 : io_dis_uops_0_bits_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_prs3 = _T_324 ? io_dis_uops_2_bits_prs3_0 : _T_323 ? io_dis_uops_1_bits_prs3_0 : io_dis_uops_0_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_prs2 = _T_324 ? (io_dis_uops_2_bits_fu_code_8_0 ? {2'h0, io_dis_uops_2_bits_fp_rm_0, io_dis_uops_2_bits_fp_typ_0} : io_dis_uops_2_bits_prs2_0) : _T_323 ? _WIRE_1_prs2 : _WIRE_prs2; // @[issue-unit-age-ordered.scala:22:7, :35:17, :86:50, :87:26, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_prs1 = _T_324 ? io_dis_uops_2_bits_prs1_0 : _T_323 ? io_dis_uops_1_bits_prs1_0 : io_dis_uops_0_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_pdst = _T_324 ? io_dis_uops_2_bits_pdst_0 : _T_323 ? io_dis_uops_1_bits_pdst_0 : io_dis_uops_0_bits_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_rxq_idx = _T_324 ? io_dis_uops_2_bits_rxq_idx_0 : _T_323 ? io_dis_uops_1_bits_rxq_idx_0 : io_dis_uops_0_bits_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_stq_idx = _T_324 ? io_dis_uops_2_bits_stq_idx_0 : _T_323 ? io_dis_uops_1_bits_stq_idx_0 : io_dis_uops_0_bits_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_ldq_idx = _T_324 ? io_dis_uops_2_bits_ldq_idx_0 : _T_323 ? io_dis_uops_1_bits_ldq_idx_0 : io_dis_uops_0_bits_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_rob_idx = _T_324 ? io_dis_uops_2_bits_rob_idx_0 : _T_323 ? io_dis_uops_1_bits_rob_idx_0 : io_dis_uops_0_bits_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_vec = _T_324 ? io_dis_uops_2_bits_fp_ctrl_vec_0 : _T_323 ? io_dis_uops_1_bits_fp_ctrl_vec_0 : io_dis_uops_0_bits_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_wflags = _T_324 ? io_dis_uops_2_bits_fp_ctrl_wflags_0 : _T_323 ? io_dis_uops_1_bits_fp_ctrl_wflags_0 : io_dis_uops_0_bits_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_sqrt = _T_324 ? io_dis_uops_2_bits_fp_ctrl_sqrt_0 : _T_323 ? io_dis_uops_1_bits_fp_ctrl_sqrt_0 : io_dis_uops_0_bits_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_div = _T_324 ? io_dis_uops_2_bits_fp_ctrl_div_0 : _T_323 ? io_dis_uops_1_bits_fp_ctrl_div_0 : io_dis_uops_0_bits_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_fma = _T_324 ? io_dis_uops_2_bits_fp_ctrl_fma_0 : _T_323 ? io_dis_uops_1_bits_fp_ctrl_fma_0 : io_dis_uops_0_bits_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_fastpipe = _T_324 ? io_dis_uops_2_bits_fp_ctrl_fastpipe_0 : _T_323 ? io_dis_uops_1_bits_fp_ctrl_fastpipe_0 : io_dis_uops_0_bits_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_toint = _T_324 ? io_dis_uops_2_bits_fp_ctrl_toint_0 : _T_323 ? io_dis_uops_1_bits_fp_ctrl_toint_0 : io_dis_uops_0_bits_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_fromint = _T_324 ? io_dis_uops_2_bits_fp_ctrl_fromint_0 : _T_323 ? io_dis_uops_1_bits_fp_ctrl_fromint_0 : io_dis_uops_0_bits_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_typeTagOut = _T_324 ? io_dis_uops_2_bits_fp_ctrl_typeTagOut_0 : _T_323 ? io_dis_uops_1_bits_fp_ctrl_typeTagOut_0 : io_dis_uops_0_bits_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_typeTagIn = _T_324 ? io_dis_uops_2_bits_fp_ctrl_typeTagIn_0 : _T_323 ? io_dis_uops_1_bits_fp_ctrl_typeTagIn_0 : io_dis_uops_0_bits_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_swap23 = _T_324 ? io_dis_uops_2_bits_fp_ctrl_swap23_0 : _T_323 ? io_dis_uops_1_bits_fp_ctrl_swap23_0 : io_dis_uops_0_bits_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_swap12 = _T_324 ? io_dis_uops_2_bits_fp_ctrl_swap12_0 : _T_323 ? io_dis_uops_1_bits_fp_ctrl_swap12_0 : io_dis_uops_0_bits_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_ren3 = _T_324 ? io_dis_uops_2_bits_fp_ctrl_ren3_0 : _T_323 ? io_dis_uops_1_bits_fp_ctrl_ren3_0 : io_dis_uops_0_bits_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_ren2 = _T_324 ? io_dis_uops_2_bits_fp_ctrl_ren2_0 : _T_323 ? io_dis_uops_1_bits_fp_ctrl_ren2_0 : io_dis_uops_0_bits_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_ren1 = _T_324 ? io_dis_uops_2_bits_fp_ctrl_ren1_0 : _T_323 ? io_dis_uops_1_bits_fp_ctrl_ren1_0 : io_dis_uops_0_bits_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_wen = _T_324 ? io_dis_uops_2_bits_fp_ctrl_wen_0 : _T_323 ? io_dis_uops_1_bits_fp_ctrl_wen_0 : io_dis_uops_0_bits_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_ldst = _T_324 ? io_dis_uops_2_bits_fp_ctrl_ldst_0 : _T_323 ? io_dis_uops_1_bits_fp_ctrl_ldst_0 : io_dis_uops_0_bits_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_op2_sel = _T_324 ? io_dis_uops_2_bits_op2_sel_0 : _T_323 ? io_dis_uops_1_bits_op2_sel_0 : io_dis_uops_0_bits_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_op1_sel = _T_324 ? io_dis_uops_2_bits_op1_sel_0 : _T_323 ? io_dis_uops_1_bits_op1_sel_0 : io_dis_uops_0_bits_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_imm_packed = _T_324 ? io_dis_uops_2_bits_imm_packed_0 : _T_323 ? io_dis_uops_1_bits_imm_packed_0 : io_dis_uops_0_bits_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_pimm = _T_324 ? (io_dis_uops_2_bits_is_sfence_0 ? {3'h0, io_dis_uops_2_bits_mem_size_0} : io_dis_uops_2_bits_pimm_0) : _T_323 ? _WIRE_1_pimm : _WIRE_pimm; // @[issue-unit-age-ordered.scala:22:7, :35:17, :89:44, :90:26, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_imm_sel = _T_324 ? io_dis_uops_2_bits_imm_sel_0 : _T_323 ? io_dis_uops_1_bits_imm_sel_0 : io_dis_uops_0_bits_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_imm_rename = _T_324 ? io_dis_uops_2_bits_imm_rename_0 : _T_323 ? io_dis_uops_1_bits_imm_rename_0 : io_dis_uops_0_bits_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_taken = _T_324 ? io_dis_uops_2_bits_taken_0 : _T_323 ? io_dis_uops_1_bits_taken_0 : io_dis_uops_0_bits_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_pc_lob = _T_324 ? io_dis_uops_2_bits_pc_lob_0 : _T_323 ? io_dis_uops_1_bits_pc_lob_0 : io_dis_uops_0_bits_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_edge_inst = _T_324 ? io_dis_uops_2_bits_edge_inst_0 : _T_323 ? io_dis_uops_1_bits_edge_inst_0 : io_dis_uops_0_bits_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_ftq_idx = _T_324 ? io_dis_uops_2_bits_ftq_idx_0 : _T_323 ? io_dis_uops_1_bits_ftq_idx_0 : io_dis_uops_0_bits_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_mov = _T_324 ? io_dis_uops_2_bits_is_mov_0 : _T_323 ? io_dis_uops_1_bits_is_mov_0 : io_dis_uops_0_bits_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_rocc = _T_324 ? io_dis_uops_2_bits_is_rocc_0 : _T_323 ? io_dis_uops_1_bits_is_rocc_0 : io_dis_uops_0_bits_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_sys_pc2epc = _T_324 ? io_dis_uops_2_bits_is_sys_pc2epc_0 : _T_323 ? io_dis_uops_1_bits_is_sys_pc2epc_0 : io_dis_uops_0_bits_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_eret = _T_324 ? io_dis_uops_2_bits_is_eret_0 : _T_323 ? io_dis_uops_1_bits_is_eret_0 : io_dis_uops_0_bits_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_amo = _T_324 ? io_dis_uops_2_bits_is_amo_0 : _T_323 ? io_dis_uops_1_bits_is_amo_0 : io_dis_uops_0_bits_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_sfence = _T_324 ? io_dis_uops_2_bits_is_sfence_0 : _T_323 ? io_dis_uops_1_bits_is_sfence_0 : io_dis_uops_0_bits_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_fencei = _T_324 ? io_dis_uops_2_bits_is_fencei_0 : _T_323 ? io_dis_uops_1_bits_is_fencei_0 : io_dis_uops_0_bits_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_fence = _T_324 ? io_dis_uops_2_bits_is_fence_0 : _T_323 ? io_dis_uops_1_bits_is_fence_0 : io_dis_uops_0_bits_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_sfb = _T_324 ? io_dis_uops_2_bits_is_sfb_0 : _T_323 ? io_dis_uops_1_bits_is_sfb_0 : io_dis_uops_0_bits_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_br_type = _T_324 ? io_dis_uops_2_bits_br_type_0 : _T_323 ? io_dis_uops_1_bits_br_type_0 : io_dis_uops_0_bits_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_br_tag = _T_324 ? io_dis_uops_2_bits_br_tag_0 : _T_323 ? io_dis_uops_1_bits_br_tag_0 : io_dis_uops_0_bits_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_br_mask = _T_324 ? io_dis_uops_2_bits_br_mask_0 : _T_323 ? io_dis_uops_1_bits_br_mask_0 : io_dis_uops_0_bits_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_dis_col_sel = _T_324 ? io_dis_uops_2_bits_dis_col_sel_0 : _T_323 ? io_dis_uops_1_bits_dis_col_sel_0 : io_dis_uops_0_bits_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_iw_p3_bypass_hint = _T_324 ? _T_225 & (prs3_wakeups_0_2 & io_wakeup_ports_0_bits_bypassable_0 | prs3_wakeups_2_2 | prs3_wakeups_3_2 | prs3_wakeups_4_2) : _T_323 ? _WIRE_1_iw_p3_bypass_hint : _WIRE_iw_p3_bypass_hint; // @[Mux.scala:30:73] assign issue_slots_15_in_uop_bits_iw_p2_bypass_hint = _T_324 ? _T_195 & (prs2_wakeups_0_2 & io_wakeup_ports_0_bits_bypassable_0 | prs2_wakeups_2_2 | prs2_wakeups_3_2 | prs2_wakeups_4_2) : _T_323 ? _WIRE_1_iw_p2_bypass_hint : _WIRE_iw_p2_bypass_hint; // @[Mux.scala:30:73] assign issue_slots_15_in_uop_bits_iw_p1_bypass_hint = _T_324 ? _T_165 & (prs1_wakeups_0_2 & io_wakeup_ports_0_bits_bypassable_0 | prs1_wakeups_2_2 | prs1_wakeups_3_2 | prs1_wakeups_4_2) : _T_323 ? _WIRE_1_iw_p1_bypass_hint : _WIRE_iw_p1_bypass_hint; // @[Mux.scala:30:73] assign issue_slots_15_in_uop_bits_iw_p2_speculative_child = _T_324 ? (_T_195 ? (prs2_wakeups_0_2 ? io_wakeup_ports_0_bits_speculative_mask_0 : 3'h0) | {prs2_wakeups_4_2, prs2_wakeups_3_2, prs2_wakeups_2_2} : io_dis_uops_2_bits_iw_p2_speculative_child_0) : _T_323 ? _WIRE_1_iw_p2_speculative_child : _WIRE_iw_p2_speculative_child; // @[Mux.scala:30:73] assign issue_slots_15_in_uop_bits_iw_p1_speculative_child = _T_324 ? (_T_165 ? (prs1_wakeups_0_2 ? io_wakeup_ports_0_bits_speculative_mask_0 : 3'h0) | {prs1_wakeups_4_2, prs1_wakeups_3_2, prs1_wakeups_2_2} : io_dis_uops_2_bits_iw_p1_speculative_child_0) : _T_323 ? _WIRE_1_iw_p1_speculative_child : _WIRE_iw_p1_speculative_child; // @[Mux.scala:30:73] assign issue_slots_15_in_uop_bits_fu_code_0 = _T_324 ? io_dis_uops_2_bits_fu_code_0_0 : _T_323 ? io_dis_uops_1_bits_fu_code_0_0 : io_dis_uops_0_bits_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fu_code_1 = _T_324 ? io_dis_uops_2_bits_fu_code_1_0 : _T_323 ? io_dis_uops_1_bits_fu_code_1_0 : io_dis_uops_0_bits_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fu_code_2 = _T_324 ? io_dis_uops_2_bits_fu_code_2_0 : _T_323 ? io_dis_uops_1_bits_fu_code_2_0 : io_dis_uops_0_bits_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fu_code_3 = _T_324 ? io_dis_uops_2_bits_fu_code_3_0 : _T_323 ? io_dis_uops_1_bits_fu_code_3_0 : io_dis_uops_0_bits_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fu_code_4 = _T_324 ? io_dis_uops_2_bits_fu_code_4_0 : _T_323 ? io_dis_uops_1_bits_fu_code_4_0 : io_dis_uops_0_bits_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fu_code_5 = _T_324 ? io_dis_uops_2_bits_fu_code_5_0 : _T_323 ? io_dis_uops_1_bits_fu_code_5_0 : io_dis_uops_0_bits_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fu_code_6 = _T_324 ? io_dis_uops_2_bits_fu_code_6_0 : _T_323 ? io_dis_uops_1_bits_fu_code_6_0 : io_dis_uops_0_bits_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fu_code_7 = _T_324 ? io_dis_uops_2_bits_fu_code_7_0 : _T_323 ? io_dis_uops_1_bits_fu_code_7_0 : io_dis_uops_0_bits_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fu_code_8 = _T_324 ? io_dis_uops_2_bits_fu_code_8_0 : _T_323 ? io_dis_uops_1_bits_fu_code_8_0 : io_dis_uops_0_bits_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fu_code_9 = _T_324 ? io_dis_uops_2_bits_fu_code_9_0 : _T_323 ? io_dis_uops_1_bits_fu_code_9_0 : io_dis_uops_0_bits_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_iq_type_0 = _T_324 ? io_dis_uops_2_bits_iq_type_0_0 : _T_323 ? io_dis_uops_1_bits_iq_type_0_0 : io_dis_uops_0_bits_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_iq_type_1 = _T_324 ? io_dis_uops_2_bits_iq_type_1_0 : _T_323 ? io_dis_uops_1_bits_iq_type_1_0 : io_dis_uops_0_bits_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_iq_type_2 = _T_324 ? io_dis_uops_2_bits_iq_type_2_0 : _T_323 ? io_dis_uops_1_bits_iq_type_2_0 : io_dis_uops_0_bits_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_iq_type_3 = _T_324 ? io_dis_uops_2_bits_iq_type_3_0 : _T_323 ? io_dis_uops_1_bits_iq_type_3_0 : io_dis_uops_0_bits_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_debug_pc = _T_324 ? io_dis_uops_2_bits_debug_pc_0 : _T_323 ? io_dis_uops_1_bits_debug_pc_0 : io_dis_uops_0_bits_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_rvc = _T_324 ? io_dis_uops_2_bits_is_rvc_0 : _T_323 ? io_dis_uops_1_bits_is_rvc_0 : io_dis_uops_0_bits_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_debug_inst = _T_324 ? io_dis_uops_2_bits_debug_inst_0 : _T_323 ? io_dis_uops_1_bits_debug_inst_0 : io_dis_uops_0_bits_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_inst = _T_324 ? io_dis_uops_2_bits_inst_0 : _T_323 ? io_dis_uops_1_bits_inst_0 : io_dis_uops_0_bits_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign _issue_slots_15_clear_T = |shamts_oh_15; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_15_clear = _issue_slots_15_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] reg is_available_0; // @[issue-unit-age-ordered.scala:208:25] reg is_available_1; // @[issue-unit-age-ordered.scala:208:25] reg is_available_2; // @[issue-unit-age-ordered.scala:208:25] reg is_available_3; // @[issue-unit-age-ordered.scala:208:25] reg is_available_4; // @[issue-unit-age-ordered.scala:208:25] reg is_available_5; // @[issue-unit-age-ordered.scala:208:25] reg is_available_6; // @[issue-unit-age-ordered.scala:208:25] reg is_available_7; // @[issue-unit-age-ordered.scala:208:25] wire [1:0] _GEN_1 = {1'h0, is_available_0} + {1'h0, is_available_1}; // @[issue-unit-age-ordered.scala:208:25, :212:45] wire [1:0] _io_dis_uops_0_ready_T; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_0_ready_T = _GEN_1; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_1_ready_T = _GEN_1; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_2_ready_T = _GEN_1; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_0_ready_T_1 = _io_dis_uops_0_ready_T; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _GEN_2 = {1'h0, is_available_2} + {1'h0, is_available_3}; // @[issue-unit-age-ordered.scala:208:25, :212:45] wire [1:0] _io_dis_uops_0_ready_T_2; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_0_ready_T_2 = _GEN_2; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_2; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_1_ready_T_2 = _GEN_2; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T_2; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_2_ready_T_2 = _GEN_2; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_0_ready_T_3 = _io_dis_uops_0_ready_T_2; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_0_ready_T_4 = {1'h0, _io_dis_uops_0_ready_T_1} + {1'h0, _io_dis_uops_0_ready_T_3}; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_0_ready_T_5 = _io_dis_uops_0_ready_T_4; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _GEN_3 = {1'h0, is_available_4} + {1'h0, is_available_5}; // @[issue-unit-age-ordered.scala:208:25, :212:45] wire [1:0] _io_dis_uops_0_ready_T_6; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_0_ready_T_6 = _GEN_3; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_6; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_1_ready_T_6 = _GEN_3; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T_6; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_2_ready_T_6 = _GEN_3; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_0_ready_T_7 = _io_dis_uops_0_ready_T_6; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _GEN_4 = {1'h0, is_available_6} + {1'h0, is_available_7}; // @[issue-unit-age-ordered.scala:208:25, :212:45] wire [1:0] _io_dis_uops_0_ready_T_8; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_0_ready_T_8 = _GEN_4; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_8; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_1_ready_T_8 = _GEN_4; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T_8; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_2_ready_T_8 = _GEN_4; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_0_ready_T_9 = _io_dis_uops_0_ready_T_8; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_0_ready_T_10 = {1'h0, _io_dis_uops_0_ready_T_7} + {1'h0, _io_dis_uops_0_ready_T_9}; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_0_ready_T_11 = _io_dis_uops_0_ready_T_10; // @[issue-unit-age-ordered.scala:212:45] wire [3:0] _io_dis_uops_0_ready_T_12 = {1'h0, _io_dis_uops_0_ready_T_5} + {1'h0, _io_dis_uops_0_ready_T_11}; // @[issue-unit-age-ordered.scala:212:45] wire [3:0] _io_dis_uops_0_ready_T_13 = _io_dis_uops_0_ready_T_12; // @[issue-unit-age-ordered.scala:212:45] wire _GEN_5 = io_dis_uops_0_ready_0 & io_dis_uops_0_valid_0; // @[Decoupled.scala:51:35] wire _io_dis_uops_0_ready_T_14; // @[Decoupled.scala:51:35] assign _io_dis_uops_0_ready_T_14 = _GEN_5; // @[Decoupled.scala:51:35] wire _io_dis_uops_1_ready_T_14; // @[Decoupled.scala:51:35] assign _io_dis_uops_1_ready_T_14 = _GEN_5; // @[Decoupled.scala:51:35] wire _io_dis_uops_2_ready_T_14; // @[Decoupled.scala:51:35] assign _io_dis_uops_2_ready_T_14 = _GEN_5; // @[Decoupled.scala:51:35] wire _GEN_6 = io_dis_uops_1_ready_0 & io_dis_uops_1_valid_0; // @[Decoupled.scala:51:35] wire _io_dis_uops_0_ready_T_15; // @[Decoupled.scala:51:35] assign _io_dis_uops_0_ready_T_15 = _GEN_6; // @[Decoupled.scala:51:35] wire _io_dis_uops_1_ready_T_15; // @[Decoupled.scala:51:35] assign _io_dis_uops_1_ready_T_15 = _GEN_6; // @[Decoupled.scala:51:35] wire _io_dis_uops_2_ready_T_15; // @[Decoupled.scala:51:35] assign _io_dis_uops_2_ready_T_15 = _GEN_6; // @[Decoupled.scala:51:35] wire _GEN_7 = io_dis_uops_2_ready_0 & io_dis_uops_2_valid_0; // @[Decoupled.scala:51:35] wire _io_dis_uops_0_ready_T_16; // @[Decoupled.scala:51:35] assign _io_dis_uops_0_ready_T_16 = _GEN_7; // @[Decoupled.scala:51:35] wire _io_dis_uops_1_ready_T_16; // @[Decoupled.scala:51:35] assign _io_dis_uops_1_ready_T_16 = _GEN_7; // @[Decoupled.scala:51:35] wire _io_dis_uops_2_ready_T_16; // @[Decoupled.scala:51:35] assign _io_dis_uops_2_ready_T_16 = _GEN_7; // @[Decoupled.scala:51:35] wire [1:0] _io_dis_uops_0_ready_T_17 = {1'h0, _io_dis_uops_0_ready_T_15} + {1'h0, _io_dis_uops_0_ready_T_16}; // @[Decoupled.scala:51:35] wire [1:0] _io_dis_uops_0_ready_T_18 = _io_dis_uops_0_ready_T_17; // @[issue-unit-age-ordered.scala:212:100] wire [2:0] _io_dis_uops_0_ready_T_19 = {2'h0, _io_dis_uops_0_ready_T_14} + {1'h0, _io_dis_uops_0_ready_T_18}; // @[Decoupled.scala:51:35] wire [1:0] _io_dis_uops_0_ready_T_20 = _io_dis_uops_0_ready_T_19[1:0]; // @[issue-unit-age-ordered.scala:212:100] wire [3:0] _io_dis_uops_0_ready_T_21 = {2'h0, _io_dis_uops_0_ready_T_20}; // @[issue-unit-age-ordered.scala:212:{90,100}] wire [2:0] _io_dis_uops_0_ready_T_22 = _io_dis_uops_0_ready_T_21[2:0]; // @[issue-unit-age-ordered.scala:212:90] wire _io_dis_uops_0_ready_T_23 = _io_dis_uops_0_ready_T_13 > {1'h0, _io_dis_uops_0_ready_T_22}; // @[issue-unit-age-ordered.scala:212:{45,60,90}] reg io_dis_uops_0_ready_REG; // @[issue-unit-age-ordered.scala:212:36] assign io_dis_uops_0_ready_0 = io_dis_uops_0_ready_REG; // @[issue-unit-age-ordered.scala:22:7, :212:36] wire [1:0] _io_dis_uops_1_ready_T_1 = _io_dis_uops_1_ready_T; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_3 = _io_dis_uops_1_ready_T_2; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_1_ready_T_4 = {1'h0, _io_dis_uops_1_ready_T_1} + {1'h0, _io_dis_uops_1_ready_T_3}; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_1_ready_T_5 = _io_dis_uops_1_ready_T_4; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_7 = _io_dis_uops_1_ready_T_6; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_9 = _io_dis_uops_1_ready_T_8; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_1_ready_T_10 = {1'h0, _io_dis_uops_1_ready_T_7} + {1'h0, _io_dis_uops_1_ready_T_9}; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_1_ready_T_11 = _io_dis_uops_1_ready_T_10; // @[issue-unit-age-ordered.scala:212:45] wire [3:0] _io_dis_uops_1_ready_T_12 = {1'h0, _io_dis_uops_1_ready_T_5} + {1'h0, _io_dis_uops_1_ready_T_11}; // @[issue-unit-age-ordered.scala:212:45] wire [3:0] _io_dis_uops_1_ready_T_13 = _io_dis_uops_1_ready_T_12; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_17 = {1'h0, _io_dis_uops_1_ready_T_15} + {1'h0, _io_dis_uops_1_ready_T_16}; // @[Decoupled.scala:51:35] wire [1:0] _io_dis_uops_1_ready_T_18 = _io_dis_uops_1_ready_T_17; // @[issue-unit-age-ordered.scala:212:100] wire [2:0] _io_dis_uops_1_ready_T_19 = {2'h0, _io_dis_uops_1_ready_T_14} + {1'h0, _io_dis_uops_1_ready_T_18}; // @[Decoupled.scala:51:35] wire [1:0] _io_dis_uops_1_ready_T_20 = _io_dis_uops_1_ready_T_19[1:0]; // @[issue-unit-age-ordered.scala:212:100] wire [3:0] _io_dis_uops_1_ready_T_21 = {2'h0, _io_dis_uops_1_ready_T_20} + 4'h1; // @[issue-unit-age-ordered.scala:212:{90,100}] wire [2:0] _io_dis_uops_1_ready_T_22 = _io_dis_uops_1_ready_T_21[2:0]; // @[issue-unit-age-ordered.scala:212:90] wire _io_dis_uops_1_ready_T_23 = _io_dis_uops_1_ready_T_13 > {1'h0, _io_dis_uops_1_ready_T_22}; // @[issue-unit-age-ordered.scala:212:{45,60,90}] reg io_dis_uops_1_ready_REG; // @[issue-unit-age-ordered.scala:212:36] assign io_dis_uops_1_ready_0 = io_dis_uops_1_ready_REG; // @[issue-unit-age-ordered.scala:22:7, :212:36] wire [1:0] _io_dis_uops_2_ready_T_1 = _io_dis_uops_2_ready_T; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T_3 = _io_dis_uops_2_ready_T_2; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_2_ready_T_4 = {1'h0, _io_dis_uops_2_ready_T_1} + {1'h0, _io_dis_uops_2_ready_T_3}; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_2_ready_T_5 = _io_dis_uops_2_ready_T_4; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T_7 = _io_dis_uops_2_ready_T_6; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T_9 = _io_dis_uops_2_ready_T_8; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_2_ready_T_10 = {1'h0, _io_dis_uops_2_ready_T_7} + {1'h0, _io_dis_uops_2_ready_T_9}; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_2_ready_T_11 = _io_dis_uops_2_ready_T_10; // @[issue-unit-age-ordered.scala:212:45] wire [3:0] _io_dis_uops_2_ready_T_12 = {1'h0, _io_dis_uops_2_ready_T_5} + {1'h0, _io_dis_uops_2_ready_T_11}; // @[issue-unit-age-ordered.scala:212:45] wire [3:0] _io_dis_uops_2_ready_T_13 = _io_dis_uops_2_ready_T_12; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T_17 = {1'h0, _io_dis_uops_2_ready_T_15} + {1'h0, _io_dis_uops_2_ready_T_16}; // @[Decoupled.scala:51:35] wire [1:0] _io_dis_uops_2_ready_T_18 = _io_dis_uops_2_ready_T_17; // @[issue-unit-age-ordered.scala:212:100] wire [2:0] _io_dis_uops_2_ready_T_19 = {2'h0, _io_dis_uops_2_ready_T_14} + {1'h0, _io_dis_uops_2_ready_T_18}; // @[Decoupled.scala:51:35] wire [1:0] _io_dis_uops_2_ready_T_20 = _io_dis_uops_2_ready_T_19[1:0]; // @[issue-unit-age-ordered.scala:212:100] wire [3:0] _io_dis_uops_2_ready_T_21 = {2'h0, _io_dis_uops_2_ready_T_20} + 4'h2; // @[issue-unit-age-ordered.scala:212:{90,100}] wire [2:0] _io_dis_uops_2_ready_T_22 = _io_dis_uops_2_ready_T_21[2:0]; // @[issue-unit-age-ordered.scala:212:90] wire _io_dis_uops_2_ready_T_23 = _io_dis_uops_2_ready_T_13 > {1'h0, _io_dis_uops_2_ready_T_22}; // @[issue-unit-age-ordered.scala:212:{45,60,90}] reg io_dis_uops_2_ready_REG; // @[issue-unit-age-ordered.scala:212:36] assign io_dis_uops_2_ready_0 = io_dis_uops_2_ready_REG; // @[issue-unit-age-ordered.scala:22:7, :212:36]
Generate the Verilog code corresponding to this FIRRTL code module ReRoCCManagerControl_3 : input clock : Clock input reset : Reset output auto : { flip ctrl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} output io : { flip mgr_busy : UInt<1>, flip rocc_busy : UInt<1>} wire ctrlNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate ctrlNodeIn.d.bits.corrupt invalidate ctrlNodeIn.d.bits.data invalidate ctrlNodeIn.d.bits.denied invalidate ctrlNodeIn.d.bits.sink invalidate ctrlNodeIn.d.bits.source invalidate ctrlNodeIn.d.bits.size invalidate ctrlNodeIn.d.bits.param invalidate ctrlNodeIn.d.bits.opcode invalidate ctrlNodeIn.d.valid invalidate ctrlNodeIn.d.ready invalidate ctrlNodeIn.a.bits.corrupt invalidate ctrlNodeIn.a.bits.data invalidate ctrlNodeIn.a.bits.mask invalidate ctrlNodeIn.a.bits.address invalidate ctrlNodeIn.a.bits.source invalidate ctrlNodeIn.a.bits.size invalidate ctrlNodeIn.a.bits.param invalidate ctrlNodeIn.a.bits.opcode invalidate ctrlNodeIn.a.valid invalidate ctrlNodeIn.a.ready inst monitor of TLMonitor_82 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, ctrlNodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, ctrlNodeIn.d.bits.data connect monitor.io.in.d.bits.denied, ctrlNodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, ctrlNodeIn.d.bits.sink connect monitor.io.in.d.bits.source, ctrlNodeIn.d.bits.source connect monitor.io.in.d.bits.size, ctrlNodeIn.d.bits.size connect monitor.io.in.d.bits.param, ctrlNodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, ctrlNodeIn.d.bits.opcode connect monitor.io.in.d.valid, ctrlNodeIn.d.valid connect monitor.io.in.d.ready, ctrlNodeIn.d.ready connect monitor.io.in.a.bits.corrupt, ctrlNodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, ctrlNodeIn.a.bits.data connect monitor.io.in.a.bits.mask, ctrlNodeIn.a.bits.mask connect monitor.io.in.a.bits.address, ctrlNodeIn.a.bits.address connect monitor.io.in.a.bits.source, ctrlNodeIn.a.bits.source connect monitor.io.in.a.bits.size, ctrlNodeIn.a.bits.size connect monitor.io.in.a.bits.param, ctrlNodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, ctrlNodeIn.a.bits.opcode connect monitor.io.in.a.valid, ctrlNodeIn.a.valid connect monitor.io.in.a.ready, ctrlNodeIn.a.ready connect ctrlNodeIn, auto.ctrl_in wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<7>, size : UInt<3>}}}} node _in_bits_read_T = eq(ctrlNodeIn.a.bits.opcode, UInt<3>(0h4)) connect in.bits.read, _in_bits_read_T node _in_bits_index_T = shr(ctrlNodeIn.a.bits.address, 3) connect in.bits.index, _in_bits_index_T connect in.bits.data, ctrlNodeIn.a.bits.data connect in.bits.mask, ctrlNodeIn.a.bits.mask connect in.bits.extra.tlrr_extra.source, ctrlNodeIn.a.bits.source connect in.bits.extra.tlrr_extra.size, ctrlNodeIn.a.bits.size wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<7>, size : UInt<3>}}}} wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<7>, size : UInt<3>}}}} connect out_front.bits, in.bits inst out_back_front_q of Queue1_RegMapperInput_i9_m8_4 connect out_back_front_q.clock, clock connect out_back_front_q.reset, reset connect out_back_front_q.io.enq, out_front node out_maskMatch = not(UInt<9>(0h1)) node out_findex = and(out_front.bits.index, out_maskMatch) node out_bindex = and(out_back_front_q.io.deq.bits.index, out_maskMatch) node _out_T = eq(out_findex, UInt<9>(0h0)) node _out_T_1 = eq(out_bindex, UInt<9>(0h0)) node _out_T_2 = eq(out_findex, UInt<9>(0h0)) node _out_T_3 = eq(out_bindex, UInt<9>(0h0)) wire out_rivalid : UInt<1>[2] wire out_wivalid : UInt<1>[2] wire out_roready : UInt<1>[2] wire out_woready : UInt<1>[2] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) node _out_backMask_T = bits(out_back_front_q.io.deq.bits.mask, 0, 0) node _out_backMask_T_1 = bits(out_back_front_q.io.deq.bits.mask, 1, 1) node _out_backMask_T_2 = bits(out_back_front_q.io.deq.bits.mask, 2, 2) node _out_backMask_T_3 = bits(out_back_front_q.io.deq.bits.mask, 3, 3) node _out_backMask_T_4 = bits(out_back_front_q.io.deq.bits.mask, 4, 4) node _out_backMask_T_5 = bits(out_back_front_q.io.deq.bits.mask, 5, 5) node _out_backMask_T_6 = bits(out_back_front_q.io.deq.bits.mask, 6, 6) node _out_backMask_T_7 = bits(out_back_front_q.io.deq.bits.mask, 7, 7) node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) node out_backMask = cat(out_backMask_hi, out_backMask_lo) node _out_rimask_T = bits(out_frontMask, 7, 0) node out_rimask = orr(_out_rimask_T) node _out_wimask_T = bits(out_frontMask, 7, 0) node out_wimask = andr(_out_wimask_T) node _out_romask_T = bits(out_backMask, 7, 0) node out_romask = orr(_out_romask_T) node _out_womask_T = bits(out_backMask, 7, 0) node out_womask = andr(_out_womask_T) node out_f_rivalid = and(out_rivalid[0], out_rimask) node out_f_roready = and(out_roready[0], out_romask) node out_f_wivalid = and(out_wivalid[0], out_wimask) node out_f_woready = and(out_woready[0], out_womask) node _out_T_4 = bits(out_back_front_q.io.deq.bits.data, 7, 0) node _out_T_5 = and(out_f_rivalid, UInt<1>(0h1)) node _out_T_6 = and(UInt<1>(0h1), out_f_roready) node _out_T_7 = eq(out_rimask, UInt<1>(0h0)) node _out_T_8 = eq(out_wimask, UInt<1>(0h0)) node _out_T_9 = eq(out_romask, UInt<1>(0h0)) node _out_T_10 = eq(out_womask, UInt<1>(0h0)) node _out_T_11 = or(io.mgr_busy, UInt<8>(0h0)) node _out_T_12 = bits(_out_T_11, 7, 0) node _out_rimask_T_1 = bits(out_frontMask, 7, 0) node out_rimask_1 = orr(_out_rimask_T_1) node _out_wimask_T_1 = bits(out_frontMask, 7, 0) node out_wimask_1 = andr(_out_wimask_T_1) node _out_romask_T_1 = bits(out_backMask, 7, 0) node out_romask_1 = orr(_out_romask_T_1) node _out_womask_T_1 = bits(out_backMask, 7, 0) node out_womask_1 = andr(_out_womask_T_1) node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1) node out_f_roready_1 = and(out_roready[1], out_romask_1) node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1) node out_f_woready_1 = and(out_woready[1], out_womask_1) node _out_T_13 = bits(out_back_front_q.io.deq.bits.data, 7, 0) node _out_T_14 = and(out_f_rivalid_1, UInt<1>(0h1)) node _out_T_15 = and(UInt<1>(0h1), out_f_roready_1) node _out_T_16 = eq(out_rimask_1, UInt<1>(0h0)) node _out_T_17 = eq(out_wimask_1, UInt<1>(0h0)) node _out_T_18 = eq(out_romask_1, UInt<1>(0h0)) node _out_T_19 = eq(out_womask_1, UInt<1>(0h0)) node _out_T_20 = or(io.rocc_busy, UInt<8>(0h0)) node _out_T_21 = bits(_out_T_20, 7, 0) node out_iindex = bits(out_front.bits.index, 0, 0) node _out_iindex_T = bits(out_front.bits.index, 1, 1) node _out_iindex_T_1 = bits(out_front.bits.index, 2, 2) node _out_iindex_T_2 = bits(out_front.bits.index, 3, 3) node _out_iindex_T_3 = bits(out_front.bits.index, 4, 4) node _out_iindex_T_4 = bits(out_front.bits.index, 5, 5) node _out_iindex_T_5 = bits(out_front.bits.index, 6, 6) node _out_iindex_T_6 = bits(out_front.bits.index, 7, 7) node _out_iindex_T_7 = bits(out_front.bits.index, 8, 8) node out_oindex = bits(out_back_front_q.io.deq.bits.index, 0, 0) node _out_oindex_T = bits(out_back_front_q.io.deq.bits.index, 1, 1) node _out_oindex_T_1 = bits(out_back_front_q.io.deq.bits.index, 2, 2) node _out_oindex_T_2 = bits(out_back_front_q.io.deq.bits.index, 3, 3) node _out_oindex_T_3 = bits(out_back_front_q.io.deq.bits.index, 4, 4) node _out_oindex_T_4 = bits(out_back_front_q.io.deq.bits.index, 5, 5) node _out_oindex_T_5 = bits(out_back_front_q.io.deq.bits.index, 6, 6) node _out_oindex_T_6 = bits(out_back_front_q.io.deq.bits.index, 7, 7) node _out_oindex_T_7 = bits(out_back_front_q.io.deq.bits.index, 8, 8) node _out_frontSel_T = dshl(UInt<1>(0h1), out_iindex) node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) node _out_backSel_T = dshl(UInt<1>(0h1), out_oindex) node out_backSel_0 = bits(_out_backSel_T, 0, 0) node out_backSel_1 = bits(_out_backSel_T, 1, 1) node _out_rifireMux_T = and(in.valid, out_front.ready) node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) wire out_rifireMux_out : UInt<1> node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T) connect out_rifireMux_out, UInt<1>(0h1) connect out_rivalid[0], _out_rifireMux_T_3 node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0)) node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) wire out_rifireMux_out_1 : UInt<1> node _out_rifireMux_T_6 = and(_out_rifireMux_T_1, out_frontSel_1) node _out_rifireMux_T_7 = and(_out_rifireMux_T_6, _out_T_2) connect out_rifireMux_out_1, UInt<1>(0h1) connect out_rivalid[1], _out_rifireMux_T_7 node _out_rifireMux_T_8 = eq(_out_T_2, UInt<1>(0h0)) node _out_rifireMux_T_9 = or(out_rifireMux_out_1, _out_rifireMux_T_8) node _out_rifireMux_T_10 = geq(out_iindex, UInt<2>(0h2)) wire _out_rifireMux_WIRE : UInt<1>[2] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 connect _out_rifireMux_WIRE[1], _out_rifireMux_T_9 node out_rifireMux = mux(_out_rifireMux_T_10, UInt<1>(0h1), _out_rifireMux_WIRE[out_iindex]) node _out_wifireMux_T = and(in.valid, out_front.ready) node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) wire out_wifireMux_out : UInt<1> node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T) connect out_wifireMux_out, UInt<1>(0h1) connect out_wivalid[0], _out_wifireMux_T_4 node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0)) node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) wire out_wifireMux_out_1 : UInt<1> node _out_wifireMux_T_7 = and(_out_wifireMux_T_2, out_frontSel_1) node _out_wifireMux_T_8 = and(_out_wifireMux_T_7, _out_T_2) connect out_wifireMux_out_1, UInt<1>(0h1) connect out_wivalid[1], _out_wifireMux_T_8 node _out_wifireMux_T_9 = eq(_out_T_2, UInt<1>(0h0)) node _out_wifireMux_T_10 = or(out_wifireMux_out_1, _out_wifireMux_T_9) node _out_wifireMux_T_11 = geq(out_iindex, UInt<2>(0h2)) wire _out_wifireMux_WIRE : UInt<1>[2] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 connect _out_wifireMux_WIRE[1], _out_wifireMux_T_10 node out_wifireMux = mux(_out_wifireMux_T_11, UInt<1>(0h1), _out_wifireMux_WIRE[out_iindex]) node _out_rofireMux_T = and(out_back_front_q.io.deq.valid, out.ready) node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_back_front_q.io.deq.bits.read) wire out_rofireMux_out : UInt<1> node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1) connect out_rofireMux_out, UInt<1>(0h1) connect out_roready[0], _out_rofireMux_T_3 node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0)) node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) wire out_rofireMux_out_1 : UInt<1> node _out_rofireMux_T_6 = and(_out_rofireMux_T_1, out_backSel_1) node _out_rofireMux_T_7 = and(_out_rofireMux_T_6, _out_T_3) connect out_rofireMux_out_1, UInt<1>(0h1) connect out_roready[1], _out_rofireMux_T_7 node _out_rofireMux_T_8 = eq(_out_T_3, UInt<1>(0h0)) node _out_rofireMux_T_9 = or(out_rofireMux_out_1, _out_rofireMux_T_8) node _out_rofireMux_T_10 = geq(out_oindex, UInt<2>(0h2)) wire _out_rofireMux_WIRE : UInt<1>[2] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 connect _out_rofireMux_WIRE[1], _out_rofireMux_T_9 node out_rofireMux = mux(_out_rofireMux_T_10, UInt<1>(0h1), _out_rofireMux_WIRE[out_oindex]) node _out_wofireMux_T = and(out_back_front_q.io.deq.valid, out.ready) node _out_wofireMux_T_1 = eq(out_back_front_q.io.deq.bits.read, UInt<1>(0h0)) node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) wire out_wofireMux_out : UInt<1> node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1) connect out_wofireMux_out, UInt<1>(0h1) connect out_woready[0], _out_wofireMux_T_4 node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0)) node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) wire out_wofireMux_out_1 : UInt<1> node _out_wofireMux_T_7 = and(_out_wofireMux_T_2, out_backSel_1) node _out_wofireMux_T_8 = and(_out_wofireMux_T_7, _out_T_3) connect out_wofireMux_out_1, UInt<1>(0h1) connect out_woready[1], _out_wofireMux_T_8 node _out_wofireMux_T_9 = eq(_out_T_3, UInt<1>(0h0)) node _out_wofireMux_T_10 = or(out_wofireMux_out_1, _out_wofireMux_T_9) node _out_wofireMux_T_11 = geq(out_oindex, UInt<2>(0h2)) wire _out_wofireMux_WIRE : UInt<1>[2] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 connect _out_wofireMux_WIRE[1], _out_wofireMux_T_10 node out_wofireMux = mux(_out_wofireMux_T_11, UInt<1>(0h1), _out_wofireMux_WIRE[out_oindex]) node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) node out_oready = mux(out_back_front_q.io.deq.bits.read, out_rofireMux, out_wofireMux) node _out_in_ready_T = and(out_front.ready, out_iready) connect in.ready, _out_in_ready_T node _out_front_valid_T = and(in.valid, out_iready) connect out_front.valid, _out_front_valid_T node _out_front_q_io_deq_ready_T = and(out.ready, out_oready) connect out_back_front_q.io.deq.ready, _out_front_q_io_deq_ready_T node _out_out_valid_T = and(out_back_front_q.io.deq.valid, out_oready) connect out.valid, _out_out_valid_T connect out.bits.read, out_back_front_q.io.deq.bits.read node _out_out_bits_data_T = geq(out_oindex, UInt<2>(0h2)) wire _out_out_bits_data_WIRE : UInt<1>[2] connect _out_out_bits_data_WIRE[0], _out_T_1 connect _out_out_bits_data_WIRE[1], _out_T_3 node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[out_oindex]) node _out_out_bits_data_T_2 = geq(out_oindex, UInt<2>(0h2)) wire _out_out_bits_data_WIRE_1 : UInt<8>[2] connect _out_out_bits_data_WIRE_1[0], _out_T_12 connect _out_out_bits_data_WIRE_1[1], _out_T_21 node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[out_oindex]) node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0)) connect out.bits.data, _out_out_bits_data_T_4 connect out.bits.extra, out_back_front_q.io.deq.bits.extra connect in.valid, ctrlNodeIn.a.valid connect ctrlNodeIn.a.ready, in.ready connect ctrlNodeIn.d.valid, out.valid connect out.ready, ctrlNodeIn.d.ready wire ctrlNodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect ctrlNodeIn_d_bits_d.opcode, UInt<1>(0h0) connect ctrlNodeIn_d_bits_d.param, UInt<1>(0h0) connect ctrlNodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size connect ctrlNodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source connect ctrlNodeIn_d_bits_d.sink, UInt<1>(0h0) connect ctrlNodeIn_d_bits_d.denied, UInt<1>(0h0) invalidate ctrlNodeIn_d_bits_d.data connect ctrlNodeIn_d_bits_d.corrupt, UInt<1>(0h0) connect ctrlNodeIn.d.bits.corrupt, ctrlNodeIn_d_bits_d.corrupt connect ctrlNodeIn.d.bits.data, ctrlNodeIn_d_bits_d.data connect ctrlNodeIn.d.bits.denied, ctrlNodeIn_d_bits_d.denied connect ctrlNodeIn.d.bits.sink, ctrlNodeIn_d_bits_d.sink connect ctrlNodeIn.d.bits.source, ctrlNodeIn_d_bits_d.source connect ctrlNodeIn.d.bits.size, ctrlNodeIn_d_bits_d.size connect ctrlNodeIn.d.bits.param, ctrlNodeIn_d_bits_d.param connect ctrlNodeIn.d.bits.opcode, ctrlNodeIn_d_bits_d.opcode connect ctrlNodeIn.d.bits.data, out.bits.data node _ctrlNodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) connect ctrlNodeIn.d.bits.opcode, _ctrlNodeIn_d_bits_opcode_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<12>(0h0) connect _WIRE.bits.source, UInt<7>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<12>(0h0) connect _WIRE_2.bits.source, UInt<7>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1)
module ReRoCCManagerControl_3( // @[Control.scala:49:9] input clock, // @[Control.scala:49:9] input reset, // @[Control.scala:49:9] output auto_ctrl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_ctrl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_ctrl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_ctrl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_ctrl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_ctrl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [11:0] auto_ctrl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_ctrl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_ctrl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_ctrl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_ctrl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_ctrl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_ctrl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_ctrl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_ctrl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_ctrl_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input io_mgr_busy, // @[Control.scala:50:16] input io_rocc_busy // @[Control.scala:50:16] ); wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [6:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire _out_back_front_q_io_deq_valid; // @[RegisterRouter.scala:87:24] wire _out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24] wire [8:0] _out_back_front_q_io_deq_bits_index; // @[RegisterRouter.scala:87:24] wire [63:0] _out_back_front_q_io_deq_bits_data; // @[RegisterRouter.scala:87:24] wire [7:0] _out_back_front_q_io_deq_bits_mask; // @[RegisterRouter.scala:87:24] wire auto_ctrl_in_a_valid_0 = auto_ctrl_in_a_valid; // @[Control.scala:49:9] wire [2:0] auto_ctrl_in_a_bits_opcode_0 = auto_ctrl_in_a_bits_opcode; // @[Control.scala:49:9] wire [2:0] auto_ctrl_in_a_bits_param_0 = auto_ctrl_in_a_bits_param; // @[Control.scala:49:9] wire [2:0] auto_ctrl_in_a_bits_size_0 = auto_ctrl_in_a_bits_size; // @[Control.scala:49:9] wire [6:0] auto_ctrl_in_a_bits_source_0 = auto_ctrl_in_a_bits_source; // @[Control.scala:49:9] wire [11:0] auto_ctrl_in_a_bits_address_0 = auto_ctrl_in_a_bits_address; // @[Control.scala:49:9] wire [7:0] auto_ctrl_in_a_bits_mask_0 = auto_ctrl_in_a_bits_mask; // @[Control.scala:49:9] wire [63:0] auto_ctrl_in_a_bits_data_0 = auto_ctrl_in_a_bits_data; // @[Control.scala:49:9] wire auto_ctrl_in_a_bits_corrupt_0 = auto_ctrl_in_a_bits_corrupt; // @[Control.scala:49:9] wire auto_ctrl_in_d_ready_0 = auto_ctrl_in_d_ready; // @[Control.scala:49:9] wire io_mgr_busy_0 = io_mgr_busy; // @[Control.scala:49:9] wire io_rocc_busy_0 = io_rocc_busy; // @[Control.scala:49:9] wire [8:0] out_maskMatch = 9'h1FE; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24] wire [2:0] ctrlNodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [63:0] ctrlNodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire auto_ctrl_in_d_bits_sink = 1'h0; // @[Control.scala:49:9] wire auto_ctrl_in_d_bits_denied = 1'h0; // @[Control.scala:49:9] wire auto_ctrl_in_d_bits_corrupt = 1'h0; // @[Control.scala:49:9] wire ctrlNodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire ctrlNodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire ctrlNodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire _out_rifireMux_T_10 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_11 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_10 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_11 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire ctrlNodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire ctrlNodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire ctrlNodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [1:0] auto_ctrl_in_d_bits_param = 2'h0; // @[Control.scala:49:9] wire ctrlNodeIn_a_ready; // @[MixedNode.scala:551:17] wire [1:0] ctrlNodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] ctrlNodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire ctrlNodeIn_a_valid = auto_ctrl_in_a_valid_0; // @[Control.scala:49:9] wire [2:0] ctrlNodeIn_a_bits_opcode = auto_ctrl_in_a_bits_opcode_0; // @[Control.scala:49:9] wire [2:0] ctrlNodeIn_a_bits_param = auto_ctrl_in_a_bits_param_0; // @[Control.scala:49:9] wire [2:0] ctrlNodeIn_a_bits_size = auto_ctrl_in_a_bits_size_0; // @[Control.scala:49:9] wire [6:0] ctrlNodeIn_a_bits_source = auto_ctrl_in_a_bits_source_0; // @[Control.scala:49:9] wire [11:0] ctrlNodeIn_a_bits_address = auto_ctrl_in_a_bits_address_0; // @[Control.scala:49:9] wire [7:0] ctrlNodeIn_a_bits_mask = auto_ctrl_in_a_bits_mask_0; // @[Control.scala:49:9] wire [63:0] ctrlNodeIn_a_bits_data = auto_ctrl_in_a_bits_data_0; // @[Control.scala:49:9] wire ctrlNodeIn_a_bits_corrupt = auto_ctrl_in_a_bits_corrupt_0; // @[Control.scala:49:9] wire ctrlNodeIn_d_ready = auto_ctrl_in_d_ready_0; // @[Control.scala:49:9] wire ctrlNodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] ctrlNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] ctrlNodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [6:0] ctrlNodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] ctrlNodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire auto_ctrl_in_a_ready_0; // @[Control.scala:49:9] wire [2:0] auto_ctrl_in_d_bits_opcode_0; // @[Control.scala:49:9] wire [2:0] auto_ctrl_in_d_bits_size_0; // @[Control.scala:49:9] wire [6:0] auto_ctrl_in_d_bits_source_0; // @[Control.scala:49:9] wire [63:0] auto_ctrl_in_d_bits_data_0; // @[Control.scala:49:9] wire auto_ctrl_in_d_valid_0; // @[Control.scala:49:9] wire in_ready; // @[RegisterRouter.scala:73:18] assign auto_ctrl_in_a_ready_0 = ctrlNodeIn_a_ready; // @[Control.scala:49:9] wire in_valid = ctrlNodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [2:0] in_bits_extra_tlrr_extra_size = ctrlNodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [6:0] in_bits_extra_tlrr_extra_source = ctrlNodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = ctrlNodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = ctrlNodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = ctrlNodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign auto_ctrl_in_d_valid_0 = ctrlNodeIn_d_valid; // @[Control.scala:49:9] assign auto_ctrl_in_d_bits_opcode_0 = ctrlNodeIn_d_bits_opcode; // @[Control.scala:49:9] wire [2:0] ctrlNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign auto_ctrl_in_d_bits_size_0 = ctrlNodeIn_d_bits_size; // @[Control.scala:49:9] wire [6:0] ctrlNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign auto_ctrl_in_d_bits_source_0 = ctrlNodeIn_d_bits_source; // @[Control.scala:49:9] wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24] assign auto_ctrl_in_d_bits_data_0 = ctrlNodeIn_d_bits_data; // @[Control.scala:49:9] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign ctrlNodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24] wire [8:0] _in_bits_index_T; // @[Edges.scala:192:34] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [6:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [2:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = ctrlNodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] assign _in_bits_index_T = ctrlNodeIn_a_bits_address[11:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T; // @[RegisterRouter.scala:73:18] wire _out_front_q_io_deq_ready_T = out_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign ctrlNodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire _ctrlNodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign ctrlNodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24] assign ctrlNodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [2:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign ctrlNodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24] wire out_front_valid; // @[RegisterRouter.scala:87:24] wire [8:0] out_findex = out_front_bits_index & 9'h1FE; // @[RegisterRouter.scala:87:24] wire [8:0] out_bindex = _out_back_front_q_io_deq_bits_index & 9'h1FE; // @[RegisterRouter.scala:87:24] wire _GEN = out_findex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T; // @[RegisterRouter.scala:87:24] assign _out_T = _GEN; // @[RegisterRouter.scala:87:24] wire _out_T_2; // @[RegisterRouter.scala:87:24] assign _out_T_2 = _GEN; // @[RegisterRouter.scala:87:24] wire _GEN_0 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1; // @[RegisterRouter.scala:87:24] assign _out_T_1 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_3; // @[RegisterRouter.scala:87:24] assign _out_T_3 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_1 = _out_T_3; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire out_rivalid_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire out_wivalid_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire out_roready_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire out_woready_1; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = _out_back_front_q_io_deq_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = _out_back_front_q_io_deq_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = _out_back_front_q_io_deq_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = _out_back_front_q_io_deq_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = _out_back_front_q_io_deq_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = _out_back_front_q_io_deq_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = _out_back_front_q_io_deq_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = _out_back_front_q_io_deq_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_rimask = |_out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = &_out_wimask_T; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_romask = |_out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = &_out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_5 = out_f_rivalid; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_6 = out_f_roready; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4 = _out_back_front_q_io_deq_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_13 = _out_back_front_q_io_deq_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire _out_T_7 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_8 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_9 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_10 = ~out_womask; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11 = {7'h0, io_mgr_busy_0}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12 = _out_T_11; // @[RegisterRouter.scala:87:24] wire [7:0] _out_out_bits_data_WIRE_1_0 = _out_T_12; // @[MuxLiteral.scala:49:48] wire out_rimask_1 = |_out_rimask_T_1; // @[RegisterRouter.scala:87:24] wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24] wire out_romask_1 = |_out_romask_T_1; // @[RegisterRouter.scala:87:24] wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_14 = out_f_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_15 = out_f_roready_1; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24] wire out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24] wire _out_T_16 = ~out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_17 = ~out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_18 = ~out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_19 = ~out_womask_1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_20 = {7'h0, io_rocc_busy_0}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_21 = _out_T_20; // @[RegisterRouter.scala:87:24] wire [7:0] _out_out_bits_data_WIRE_1_1 = _out_T_21; // @[MuxLiteral.scala:49:48] wire out_iindex = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_1 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_2 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_3 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_4 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_5 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_6 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_7 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24] wire out_oindex = _out_back_front_q_io_deq_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T = _out_back_front_q_io_deq_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_1 = _out_back_front_q_io_deq_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_2 = _out_back_front_q_io_deq_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_3 = _out_back_front_q_io_deq_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_4 = _out_back_front_q_io_deq_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_5 = _out_back_front_q_io_deq_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_6 = _out_back_front_q_io_deq_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_7 = _out_back_front_q_io_deq_bits_index[8]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_frontSel_T = 2'h1 << out_iindex; // @[OneHot.scala:58:35] wire out_frontSel_0 = _out_frontSel_T[0]; // @[OneHot.scala:58:35] wire out_frontSel_1 = _out_frontSel_T[1]; // @[OneHot.scala:58:35] wire [1:0] _out_backSel_T = 2'h1 << out_oindex; // @[OneHot.scala:58:35] wire out_backSel_0 = _out_backSel_T[0]; // @[OneHot.scala:58:35] wire out_backSel_1 = _out_backSel_T[1]; // @[OneHot.scala:58:35] wire _GEN_1 = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = _out_rifireMux_T_1 & out_frontSel_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_7 = _out_rifireMux_T_6 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_rivalid_1 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_8 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_7 = _out_wifireMux_T_2 & out_frontSel_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_8 = _out_wifireMux_T_7 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_wivalid_1 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_9 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _GEN_2 = _out_back_front_q_io_deq_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & _out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_6 = _out_rofireMux_T_1 & out_backSel_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_7 = _out_rofireMux_T_6 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_1 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_8 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1 = ~_out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_7 = _out_wofireMux_T_2 & out_backSel_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_8 = _out_wofireMux_T_7 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_woready_1 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_9 = ~_out_T_3; // @[RegisterRouter.scala:87:24] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_T_1 = out_oindex ? _out_out_bits_data_WIRE_1 : _out_out_bits_data_WIRE_0; // @[MuxLiteral.scala:49:{10,48}] wire [7:0] _out_out_bits_data_T_3 = out_oindex ? _out_out_bits_data_WIRE_1_1 : _out_out_bits_data_WIRE_1_0; // @[MuxLiteral.scala:49:{10,48}] wire [7:0] _out_out_bits_data_T_4 = _out_out_bits_data_T_1 ? _out_out_bits_data_T_3 : 8'h0; // @[MuxLiteral.scala:49:10] assign out_bits_data = {56'h0, _out_out_bits_data_T_4}; // @[RegisterRouter.scala:87:24] assign ctrlNodeIn_d_bits_size = ctrlNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign ctrlNodeIn_d_bits_source = ctrlNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign ctrlNodeIn_d_bits_opcode = {2'h0, _ctrlNodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] TLMonitor_82 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (ctrlNodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (ctrlNodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (ctrlNodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (ctrlNodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (ctrlNodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (ctrlNodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (ctrlNodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (ctrlNodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (ctrlNodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (ctrlNodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (ctrlNodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (ctrlNodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (ctrlNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (ctrlNodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (ctrlNodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (ctrlNodeIn_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue1_RegMapperInput_i9_m8_4 out_back_front_q ( // @[RegisterRouter.scala:87:24] .clock (clock), .reset (reset), .io_enq_ready (out_front_ready), .io_enq_valid (out_front_valid), // @[RegisterRouter.scala:87:24] .io_enq_bits_read (out_front_bits_read), // @[RegisterRouter.scala:87:24] .io_enq_bits_index (out_front_bits_index), // @[RegisterRouter.scala:87:24] .io_enq_bits_data (out_front_bits_data), // @[RegisterRouter.scala:87:24] .io_enq_bits_mask (out_front_bits_mask), // @[RegisterRouter.scala:87:24] .io_enq_bits_extra_tlrr_extra_source (out_front_bits_extra_tlrr_extra_source), // @[RegisterRouter.scala:87:24] .io_enq_bits_extra_tlrr_extra_size (out_front_bits_extra_tlrr_extra_size), // @[RegisterRouter.scala:87:24] .io_deq_ready (_out_front_q_io_deq_ready_T), // @[RegisterRouter.scala:87:24] .io_deq_valid (_out_back_front_q_io_deq_valid), .io_deq_bits_read (_out_back_front_q_io_deq_bits_read), .io_deq_bits_index (_out_back_front_q_io_deq_bits_index), .io_deq_bits_data (_out_back_front_q_io_deq_bits_data), .io_deq_bits_mask (_out_back_front_q_io_deq_bits_mask), .io_deq_bits_extra_tlrr_extra_source (out_bits_extra_tlrr_extra_source), .io_deq_bits_extra_tlrr_extra_size (out_bits_extra_tlrr_extra_size) ); // @[RegisterRouter.scala:87:24] assign out_bits_read = _out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = _out_back_front_q_io_deq_valid; // @[RegisterRouter.scala:87:24] assign auto_ctrl_in_a_ready = auto_ctrl_in_a_ready_0; // @[Control.scala:49:9] assign auto_ctrl_in_d_valid = auto_ctrl_in_d_valid_0; // @[Control.scala:49:9] assign auto_ctrl_in_d_bits_opcode = auto_ctrl_in_d_bits_opcode_0; // @[Control.scala:49:9] assign auto_ctrl_in_d_bits_size = auto_ctrl_in_d_bits_size_0; // @[Control.scala:49:9] assign auto_ctrl_in_d_bits_source = auto_ctrl_in_d_bits_source_0; // @[Control.scala:49:9] assign auto_ctrl_in_d_bits_data = auto_ctrl_in_d_bits_data_0; // @[Control.scala:49:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_69 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 4, 0) node _source_ok_T = shr(io.in.a.bits.source, 5) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<5>(0h1f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<5>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 2, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 4, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<3>(0h5)) node mask_sub_sub_sub_sub_size = bits(mask_sizeOH, 4, 4) node mask_sub_sub_sub_sub_bit = bits(io.in.a.bits.address, 4, 4) node mask_sub_sub_sub_sub_nbit = eq(mask_sub_sub_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_sub_sub_nbit) node _mask_sub_sub_sub_sub_acc_T = and(mask_sub_sub_sub_sub_size, mask_sub_sub_sub_sub_0_2) node mask_sub_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_sub_acc_T) node mask_sub_sub_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_sub_sub_bit) node _mask_sub_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_sub_size, mask_sub_sub_sub_sub_1_2) node mask_sub_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_sub_acc_T_1) node mask_sub_sub_sub_size = bits(mask_sizeOH, 3, 3) node mask_sub_sub_sub_bit = bits(io.in.a.bits.address, 3, 3) node mask_sub_sub_sub_nbit = eq(mask_sub_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_sub_0_2 = and(mask_sub_sub_sub_sub_0_2, mask_sub_sub_sub_nbit) node _mask_sub_sub_sub_acc_T = and(mask_sub_sub_sub_size, mask_sub_sub_sub_0_2) node mask_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T) node mask_sub_sub_sub_1_2 = and(mask_sub_sub_sub_sub_0_2, mask_sub_sub_sub_bit) node _mask_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_1_2) node mask_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T_1) node mask_sub_sub_sub_2_2 = and(mask_sub_sub_sub_sub_1_2, mask_sub_sub_sub_nbit) node _mask_sub_sub_sub_acc_T_2 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_2_2) node mask_sub_sub_sub_2_1 = or(mask_sub_sub_sub_sub_1_1, _mask_sub_sub_sub_acc_T_2) node mask_sub_sub_sub_3_2 = and(mask_sub_sub_sub_sub_1_2, mask_sub_sub_sub_bit) node _mask_sub_sub_sub_acc_T_3 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_3_2) node mask_sub_sub_sub_3_1 = or(mask_sub_sub_sub_sub_1_1, _mask_sub_sub_sub_acc_T_3) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_sub_2_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size, mask_sub_sub_2_2) node mask_sub_sub_2_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_3_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size, mask_sub_sub_3_2) node mask_sub_sub_3_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_3) node mask_sub_sub_4_2 = and(mask_sub_sub_sub_2_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T_4 = and(mask_sub_sub_size, mask_sub_sub_4_2) node mask_sub_sub_4_1 = or(mask_sub_sub_sub_2_1, _mask_sub_sub_acc_T_4) node mask_sub_sub_5_2 = and(mask_sub_sub_sub_2_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_5 = and(mask_sub_sub_size, mask_sub_sub_5_2) node mask_sub_sub_5_1 = or(mask_sub_sub_sub_2_1, _mask_sub_sub_acc_T_5) node mask_sub_sub_6_2 = and(mask_sub_sub_sub_3_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T_6 = and(mask_sub_sub_size, mask_sub_sub_6_2) node mask_sub_sub_6_1 = or(mask_sub_sub_sub_3_1, _mask_sub_sub_acc_T_6) node mask_sub_sub_7_2 = and(mask_sub_sub_sub_3_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_7 = and(mask_sub_sub_size, mask_sub_sub_7_2) node mask_sub_sub_7_1 = or(mask_sub_sub_sub_3_1, _mask_sub_sub_acc_T_7) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_sub_4_2 = and(mask_sub_sub_2_2, mask_sub_nbit) node _mask_sub_acc_T_4 = and(mask_sub_size, mask_sub_4_2) node mask_sub_4_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_4) node mask_sub_5_2 = and(mask_sub_sub_2_2, mask_sub_bit) node _mask_sub_acc_T_5 = and(mask_sub_size, mask_sub_5_2) node mask_sub_5_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_5) node mask_sub_6_2 = and(mask_sub_sub_3_2, mask_sub_nbit) node _mask_sub_acc_T_6 = and(mask_sub_size, mask_sub_6_2) node mask_sub_6_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_6) node mask_sub_7_2 = and(mask_sub_sub_3_2, mask_sub_bit) node _mask_sub_acc_T_7 = and(mask_sub_size, mask_sub_7_2) node mask_sub_7_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_7) node mask_sub_8_2 = and(mask_sub_sub_4_2, mask_sub_nbit) node _mask_sub_acc_T_8 = and(mask_sub_size, mask_sub_8_2) node mask_sub_8_1 = or(mask_sub_sub_4_1, _mask_sub_acc_T_8) node mask_sub_9_2 = and(mask_sub_sub_4_2, mask_sub_bit) node _mask_sub_acc_T_9 = and(mask_sub_size, mask_sub_9_2) node mask_sub_9_1 = or(mask_sub_sub_4_1, _mask_sub_acc_T_9) node mask_sub_10_2 = and(mask_sub_sub_5_2, mask_sub_nbit) node _mask_sub_acc_T_10 = and(mask_sub_size, mask_sub_10_2) node mask_sub_10_1 = or(mask_sub_sub_5_1, _mask_sub_acc_T_10) node mask_sub_11_2 = and(mask_sub_sub_5_2, mask_sub_bit) node _mask_sub_acc_T_11 = and(mask_sub_size, mask_sub_11_2) node mask_sub_11_1 = or(mask_sub_sub_5_1, _mask_sub_acc_T_11) node mask_sub_12_2 = and(mask_sub_sub_6_2, mask_sub_nbit) node _mask_sub_acc_T_12 = and(mask_sub_size, mask_sub_12_2) node mask_sub_12_1 = or(mask_sub_sub_6_1, _mask_sub_acc_T_12) node mask_sub_13_2 = and(mask_sub_sub_6_2, mask_sub_bit) node _mask_sub_acc_T_13 = and(mask_sub_size, mask_sub_13_2) node mask_sub_13_1 = or(mask_sub_sub_6_1, _mask_sub_acc_T_13) node mask_sub_14_2 = and(mask_sub_sub_7_2, mask_sub_nbit) node _mask_sub_acc_T_14 = and(mask_sub_size, mask_sub_14_2) node mask_sub_14_1 = or(mask_sub_sub_7_1, _mask_sub_acc_T_14) node mask_sub_15_2 = and(mask_sub_sub_7_2, mask_sub_bit) node _mask_sub_acc_T_15 = and(mask_sub_size, mask_sub_15_2) node mask_sub_15_1 = or(mask_sub_sub_7_1, _mask_sub_acc_T_15) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_eq_8 = and(mask_sub_4_2, mask_nbit) node _mask_acc_T_8 = and(mask_size, mask_eq_8) node mask_acc_8 = or(mask_sub_4_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_4_2, mask_bit) node _mask_acc_T_9 = and(mask_size, mask_eq_9) node mask_acc_9 = or(mask_sub_4_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_5_2, mask_nbit) node _mask_acc_T_10 = and(mask_size, mask_eq_10) node mask_acc_10 = or(mask_sub_5_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_5_2, mask_bit) node _mask_acc_T_11 = and(mask_size, mask_eq_11) node mask_acc_11 = or(mask_sub_5_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_6_2, mask_nbit) node _mask_acc_T_12 = and(mask_size, mask_eq_12) node mask_acc_12 = or(mask_sub_6_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_6_2, mask_bit) node _mask_acc_T_13 = and(mask_size, mask_eq_13) node mask_acc_13 = or(mask_sub_6_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_7_2, mask_nbit) node _mask_acc_T_14 = and(mask_size, mask_eq_14) node mask_acc_14 = or(mask_sub_7_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_7_2, mask_bit) node _mask_acc_T_15 = and(mask_size, mask_eq_15) node mask_acc_15 = or(mask_sub_7_1, _mask_acc_T_15) node mask_eq_16 = and(mask_sub_8_2, mask_nbit) node _mask_acc_T_16 = and(mask_size, mask_eq_16) node mask_acc_16 = or(mask_sub_8_1, _mask_acc_T_16) node mask_eq_17 = and(mask_sub_8_2, mask_bit) node _mask_acc_T_17 = and(mask_size, mask_eq_17) node mask_acc_17 = or(mask_sub_8_1, _mask_acc_T_17) node mask_eq_18 = and(mask_sub_9_2, mask_nbit) node _mask_acc_T_18 = and(mask_size, mask_eq_18) node mask_acc_18 = or(mask_sub_9_1, _mask_acc_T_18) node mask_eq_19 = and(mask_sub_9_2, mask_bit) node _mask_acc_T_19 = and(mask_size, mask_eq_19) node mask_acc_19 = or(mask_sub_9_1, _mask_acc_T_19) node mask_eq_20 = and(mask_sub_10_2, mask_nbit) node _mask_acc_T_20 = and(mask_size, mask_eq_20) node mask_acc_20 = or(mask_sub_10_1, _mask_acc_T_20) node mask_eq_21 = and(mask_sub_10_2, mask_bit) node _mask_acc_T_21 = and(mask_size, mask_eq_21) node mask_acc_21 = or(mask_sub_10_1, _mask_acc_T_21) node mask_eq_22 = and(mask_sub_11_2, mask_nbit) node _mask_acc_T_22 = and(mask_size, mask_eq_22) node mask_acc_22 = or(mask_sub_11_1, _mask_acc_T_22) node mask_eq_23 = and(mask_sub_11_2, mask_bit) node _mask_acc_T_23 = and(mask_size, mask_eq_23) node mask_acc_23 = or(mask_sub_11_1, _mask_acc_T_23) node mask_eq_24 = and(mask_sub_12_2, mask_nbit) node _mask_acc_T_24 = and(mask_size, mask_eq_24) node mask_acc_24 = or(mask_sub_12_1, _mask_acc_T_24) node mask_eq_25 = and(mask_sub_12_2, mask_bit) node _mask_acc_T_25 = and(mask_size, mask_eq_25) node mask_acc_25 = or(mask_sub_12_1, _mask_acc_T_25) node mask_eq_26 = and(mask_sub_13_2, mask_nbit) node _mask_acc_T_26 = and(mask_size, mask_eq_26) node mask_acc_26 = or(mask_sub_13_1, _mask_acc_T_26) node mask_eq_27 = and(mask_sub_13_2, mask_bit) node _mask_acc_T_27 = and(mask_size, mask_eq_27) node mask_acc_27 = or(mask_sub_13_1, _mask_acc_T_27) node mask_eq_28 = and(mask_sub_14_2, mask_nbit) node _mask_acc_T_28 = and(mask_size, mask_eq_28) node mask_acc_28 = or(mask_sub_14_1, _mask_acc_T_28) node mask_eq_29 = and(mask_sub_14_2, mask_bit) node _mask_acc_T_29 = and(mask_size, mask_eq_29) node mask_acc_29 = or(mask_sub_14_1, _mask_acc_T_29) node mask_eq_30 = and(mask_sub_15_2, mask_nbit) node _mask_acc_T_30 = and(mask_size, mask_eq_30) node mask_acc_30 = or(mask_sub_15_1, _mask_acc_T_30) node mask_eq_31 = and(mask_sub_15_2, mask_bit) node _mask_acc_T_31 = and(mask_size, mask_eq_31) node mask_acc_31 = or(mask_sub_15_1, _mask_acc_T_31) node mask_lo_lo_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_lo_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo_lo_lo = cat(mask_lo_lo_lo_hi, mask_lo_lo_lo_lo) node mask_lo_lo_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_lo_lo_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_lo_lo_hi = cat(mask_lo_lo_hi_hi, mask_lo_lo_hi_lo) node mask_lo_lo = cat(mask_lo_lo_hi, mask_lo_lo_lo) node mask_lo_hi_lo_lo = cat(mask_acc_9, mask_acc_8) node mask_lo_hi_lo_hi = cat(mask_acc_11, mask_acc_10) node mask_lo_hi_lo = cat(mask_lo_hi_lo_hi, mask_lo_hi_lo_lo) node mask_lo_hi_hi_lo = cat(mask_acc_13, mask_acc_12) node mask_lo_hi_hi_hi = cat(mask_acc_15, mask_acc_14) node mask_lo_hi_hi = cat(mask_lo_hi_hi_hi, mask_lo_hi_hi_lo) node mask_lo_hi = cat(mask_lo_hi_hi, mask_lo_hi_lo) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo_lo_lo = cat(mask_acc_17, mask_acc_16) node mask_hi_lo_lo_hi = cat(mask_acc_19, mask_acc_18) node mask_hi_lo_lo = cat(mask_hi_lo_lo_hi, mask_hi_lo_lo_lo) node mask_hi_lo_hi_lo = cat(mask_acc_21, mask_acc_20) node mask_hi_lo_hi_hi = cat(mask_acc_23, mask_acc_22) node mask_hi_lo_hi = cat(mask_hi_lo_hi_hi, mask_hi_lo_hi_lo) node mask_hi_lo = cat(mask_hi_lo_hi, mask_hi_lo_lo) node mask_hi_hi_lo_lo = cat(mask_acc_25, mask_acc_24) node mask_hi_hi_lo_hi = cat(mask_acc_27, mask_acc_26) node mask_hi_hi_lo = cat(mask_hi_hi_lo_hi, mask_hi_hi_lo_lo) node mask_hi_hi_hi_lo = cat(mask_acc_29, mask_acc_28) node mask_hi_hi_hi_hi = cat(mask_acc_31, mask_acc_30) node mask_hi_hi_hi = cat(mask_hi_hi_hi_hi, mask_hi_hi_hi_lo) node mask_hi_hi = cat(mask_hi_hi_hi, mask_hi_hi_lo) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits = bits(_uncommonBits_T, 4, 0) node _T_4 = shr(io.in.a.bits.source, 5) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<5>(0h1f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 4, 0) node _T_24 = shr(io.in.a.bits.source, 5) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<5>(0h1f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<14>(0h2000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<13>(0h1000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<18>(0h2f000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<17>(0h10000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_64 = cvt(_T_63) node _T_65 = and(_T_64, asSInt(UInt<27>(0h4000000))) node _T_66 = asSInt(_T_65) node _T_67 = eq(_T_66, asSInt(UInt<1>(0h0))) node _T_68 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_69 = cvt(_T_68) node _T_70 = and(_T_69, asSInt(UInt<13>(0h1000))) node _T_71 = asSInt(_T_70) node _T_72 = eq(_T_71, asSInt(UInt<1>(0h0))) node _T_73 = or(_T_37, _T_42) node _T_74 = or(_T_73, _T_47) node _T_75 = or(_T_74, _T_52) node _T_76 = or(_T_75, _T_57) node _T_77 = or(_T_76, _T_62) node _T_78 = or(_T_77, _T_67) node _T_79 = or(_T_78, _T_72) node _T_80 = and(_T_32, _T_79) node _T_81 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_82 = or(UInt<1>(0h0), _T_81) node _T_83 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_84 = cvt(_T_83) node _T_85 = and(_T_84, asSInt(UInt<17>(0h10000))) node _T_86 = asSInt(_T_85) node _T_87 = eq(_T_86, asSInt(UInt<1>(0h0))) node _T_88 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_89 = cvt(_T_88) node _T_90 = and(_T_89, asSInt(UInt<29>(0h10000000))) node _T_91 = asSInt(_T_90) node _T_92 = eq(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = or(_T_87, _T_92) node _T_94 = and(_T_82, _T_93) node _T_95 = or(UInt<1>(0h0), _T_80) node _T_96 = or(_T_95, _T_94) node _T_97 = and(_T_31, _T_96) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_97, UInt<1>(0h1), "") : assert_2 node _T_101 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_102 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_103 = and(_T_101, _T_102) node _T_104 = or(UInt<1>(0h0), _T_103) node _T_105 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<14>(0h2000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_116 = cvt(_T_115) node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000))) node _T_118 = asSInt(_T_117) node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0))) node _T_120 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_121 = cvt(_T_120) node _T_122 = and(_T_121, asSInt(UInt<18>(0h2f000))) node _T_123 = asSInt(_T_122) node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_126 = cvt(_T_125) node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000))) node _T_128 = asSInt(_T_127) node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0))) node _T_130 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<13>(0h1000))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_136 = cvt(_T_135) node _T_137 = and(_T_136, asSInt(UInt<17>(0h10000))) node _T_138 = asSInt(_T_137) node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0))) node _T_140 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<27>(0h4000000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_146 = cvt(_T_145) node _T_147 = and(_T_146, asSInt(UInt<13>(0h1000))) node _T_148 = asSInt(_T_147) node _T_149 = eq(_T_148, asSInt(UInt<1>(0h0))) node _T_150 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_151 = cvt(_T_150) node _T_152 = and(_T_151, asSInt(UInt<29>(0h10000000))) node _T_153 = asSInt(_T_152) node _T_154 = eq(_T_153, asSInt(UInt<1>(0h0))) node _T_155 = or(_T_109, _T_114) node _T_156 = or(_T_155, _T_119) node _T_157 = or(_T_156, _T_124) node _T_158 = or(_T_157, _T_129) node _T_159 = or(_T_158, _T_134) node _T_160 = or(_T_159, _T_139) node _T_161 = or(_T_160, _T_144) node _T_162 = or(_T_161, _T_149) node _T_163 = or(_T_162, _T_154) node _T_164 = and(_T_104, _T_163) node _T_165 = or(UInt<1>(0h0), _T_164) node _T_166 = and(UInt<1>(0h0), _T_165) node _T_167 = asUInt(reset) node _T_168 = eq(_T_167, UInt<1>(0h0)) when _T_168 : node _T_169 = eq(_T_166, UInt<1>(0h0)) when _T_169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_166, UInt<1>(0h1), "") : assert_3 node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_173 = geq(io.in.a.bits.size, UInt<3>(0h5)) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_173, UInt<1>(0h1), "") : assert_5 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(is_aligned, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_180 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_181 = asUInt(reset) node _T_182 = eq(_T_181, UInt<1>(0h0)) when _T_182 : node _T_183 = eq(_T_180, UInt<1>(0h0)) when _T_183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_180, UInt<1>(0h1), "") : assert_7 node _T_184 = not(io.in.a.bits.mask) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = asUInt(reset) node _T_187 = eq(_T_186, UInt<1>(0h0)) when _T_187 : node _T_188 = eq(_T_185, UInt<1>(0h0)) when _T_188 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_185, UInt<1>(0h1), "") : assert_8 node _T_189 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_190 = asUInt(reset) node _T_191 = eq(_T_190, UInt<1>(0h0)) when _T_191 : node _T_192 = eq(_T_189, UInt<1>(0h0)) when _T_192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_189, UInt<1>(0h1), "") : assert_9 node _T_193 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_193 : node _T_194 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_195 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_196 = and(_T_194, _T_195) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 4, 0) node _T_197 = shr(io.in.a.bits.source, 5) node _T_198 = eq(_T_197, UInt<1>(0h0)) node _T_199 = leq(UInt<1>(0h0), uncommonBits_2) node _T_200 = and(_T_198, _T_199) node _T_201 = leq(uncommonBits_2, UInt<5>(0h1f)) node _T_202 = and(_T_200, _T_201) node _T_203 = and(_T_196, _T_202) node _T_204 = or(UInt<1>(0h0), _T_203) node _T_205 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_206 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<14>(0h2000))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_217 = cvt(_T_216) node _T_218 = and(_T_217, asSInt(UInt<17>(0h10000))) node _T_219 = asSInt(_T_218) node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<18>(0h2f000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<17>(0h10000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_232 = cvt(_T_231) node _T_233 = and(_T_232, asSInt(UInt<13>(0h1000))) node _T_234 = asSInt(_T_233) node _T_235 = eq(_T_234, asSInt(UInt<1>(0h0))) node _T_236 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_237 = cvt(_T_236) node _T_238 = and(_T_237, asSInt(UInt<27>(0h4000000))) node _T_239 = asSInt(_T_238) node _T_240 = eq(_T_239, asSInt(UInt<1>(0h0))) node _T_241 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<13>(0h1000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = or(_T_210, _T_215) node _T_247 = or(_T_246, _T_220) node _T_248 = or(_T_247, _T_225) node _T_249 = or(_T_248, _T_230) node _T_250 = or(_T_249, _T_235) node _T_251 = or(_T_250, _T_240) node _T_252 = or(_T_251, _T_245) node _T_253 = and(_T_205, _T_252) node _T_254 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_255 = or(UInt<1>(0h0), _T_254) node _T_256 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_257 = cvt(_T_256) node _T_258 = and(_T_257, asSInt(UInt<17>(0h10000))) node _T_259 = asSInt(_T_258) node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_262 = cvt(_T_261) node _T_263 = and(_T_262, asSInt(UInt<29>(0h10000000))) node _T_264 = asSInt(_T_263) node _T_265 = eq(_T_264, asSInt(UInt<1>(0h0))) node _T_266 = or(_T_260, _T_265) node _T_267 = and(_T_255, _T_266) node _T_268 = or(UInt<1>(0h0), _T_253) node _T_269 = or(_T_268, _T_267) node _T_270 = and(_T_204, _T_269) node _T_271 = asUInt(reset) node _T_272 = eq(_T_271, UInt<1>(0h0)) when _T_272 : node _T_273 = eq(_T_270, UInt<1>(0h0)) when _T_273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_270, UInt<1>(0h1), "") : assert_10 node _T_274 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_275 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_276 = and(_T_274, _T_275) node _T_277 = or(UInt<1>(0h0), _T_276) node _T_278 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<14>(0h2000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<13>(0h1000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<17>(0h10000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<18>(0h2f000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<17>(0h10000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<17>(0h10000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_314 = cvt(_T_313) node _T_315 = and(_T_314, asSInt(UInt<27>(0h4000000))) node _T_316 = asSInt(_T_315) node _T_317 = eq(_T_316, asSInt(UInt<1>(0h0))) node _T_318 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_319 = cvt(_T_318) node _T_320 = and(_T_319, asSInt(UInt<13>(0h1000))) node _T_321 = asSInt(_T_320) node _T_322 = eq(_T_321, asSInt(UInt<1>(0h0))) node _T_323 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_324 = cvt(_T_323) node _T_325 = and(_T_324, asSInt(UInt<29>(0h10000000))) node _T_326 = asSInt(_T_325) node _T_327 = eq(_T_326, asSInt(UInt<1>(0h0))) node _T_328 = or(_T_282, _T_287) node _T_329 = or(_T_328, _T_292) node _T_330 = or(_T_329, _T_297) node _T_331 = or(_T_330, _T_302) node _T_332 = or(_T_331, _T_307) node _T_333 = or(_T_332, _T_312) node _T_334 = or(_T_333, _T_317) node _T_335 = or(_T_334, _T_322) node _T_336 = or(_T_335, _T_327) node _T_337 = and(_T_277, _T_336) node _T_338 = or(UInt<1>(0h0), _T_337) node _T_339 = and(UInt<1>(0h0), _T_338) node _T_340 = asUInt(reset) node _T_341 = eq(_T_340, UInt<1>(0h0)) when _T_341 : node _T_342 = eq(_T_339, UInt<1>(0h0)) when _T_342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_339, UInt<1>(0h1), "") : assert_11 node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_346 = geq(io.in.a.bits.size, UInt<3>(0h5)) node _T_347 = asUInt(reset) node _T_348 = eq(_T_347, UInt<1>(0h0)) when _T_348 : node _T_349 = eq(_T_346, UInt<1>(0h0)) when _T_349 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_346, UInt<1>(0h1), "") : assert_13 node _T_350 = asUInt(reset) node _T_351 = eq(_T_350, UInt<1>(0h0)) when _T_351 : node _T_352 = eq(is_aligned, UInt<1>(0h0)) when _T_352 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_353 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_354 = asUInt(reset) node _T_355 = eq(_T_354, UInt<1>(0h0)) when _T_355 : node _T_356 = eq(_T_353, UInt<1>(0h0)) when _T_356 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_353, UInt<1>(0h1), "") : assert_15 node _T_357 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_358 = asUInt(reset) node _T_359 = eq(_T_358, UInt<1>(0h0)) when _T_359 : node _T_360 = eq(_T_357, UInt<1>(0h0)) when _T_360 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_357, UInt<1>(0h1), "") : assert_16 node _T_361 = not(io.in.a.bits.mask) node _T_362 = eq(_T_361, UInt<1>(0h0)) node _T_363 = asUInt(reset) node _T_364 = eq(_T_363, UInt<1>(0h0)) when _T_364 : node _T_365 = eq(_T_362, UInt<1>(0h0)) when _T_365 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_362, UInt<1>(0h1), "") : assert_17 node _T_366 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_366, UInt<1>(0h1), "") : assert_18 node _T_370 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_370 : node _T_371 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_372 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_373 = and(_T_371, _T_372) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 4, 0) node _T_374 = shr(io.in.a.bits.source, 5) node _T_375 = eq(_T_374, UInt<1>(0h0)) node _T_376 = leq(UInt<1>(0h0), uncommonBits_3) node _T_377 = and(_T_375, _T_376) node _T_378 = leq(uncommonBits_3, UInt<5>(0h1f)) node _T_379 = and(_T_377, _T_378) node _T_380 = and(_T_373, _T_379) node _T_381 = or(UInt<1>(0h0), _T_380) node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(_T_381, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_381, UInt<1>(0h1), "") : assert_19 node _T_385 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_386 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_387 = and(_T_385, _T_386) node _T_388 = or(UInt<1>(0h0), _T_387) node _T_389 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<13>(0h1000))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = and(_T_388, _T_393) node _T_395 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_396 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_397 = and(_T_395, _T_396) node _T_398 = or(UInt<1>(0h0), _T_397) node _T_399 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<14>(0h2000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<18>(0h2f000))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<17>(0h10000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<13>(0h1000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_425 = cvt(_T_424) node _T_426 = and(_T_425, asSInt(UInt<17>(0h10000))) node _T_427 = asSInt(_T_426) node _T_428 = eq(_T_427, asSInt(UInt<1>(0h0))) node _T_429 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_430 = cvt(_T_429) node _T_431 = and(_T_430, asSInt(UInt<27>(0h4000000))) node _T_432 = asSInt(_T_431) node _T_433 = eq(_T_432, asSInt(UInt<1>(0h0))) node _T_434 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_435 = cvt(_T_434) node _T_436 = and(_T_435, asSInt(UInt<13>(0h1000))) node _T_437 = asSInt(_T_436) node _T_438 = eq(_T_437, asSInt(UInt<1>(0h0))) node _T_439 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_440 = cvt(_T_439) node _T_441 = and(_T_440, asSInt(UInt<29>(0h10000000))) node _T_442 = asSInt(_T_441) node _T_443 = eq(_T_442, asSInt(UInt<1>(0h0))) node _T_444 = or(_T_403, _T_408) node _T_445 = or(_T_444, _T_413) node _T_446 = or(_T_445, _T_418) node _T_447 = or(_T_446, _T_423) node _T_448 = or(_T_447, _T_428) node _T_449 = or(_T_448, _T_433) node _T_450 = or(_T_449, _T_438) node _T_451 = or(_T_450, _T_443) node _T_452 = and(_T_398, _T_451) node _T_453 = or(UInt<1>(0h0), _T_394) node _T_454 = or(_T_453, _T_452) node _T_455 = asUInt(reset) node _T_456 = eq(_T_455, UInt<1>(0h0)) when _T_456 : node _T_457 = eq(_T_454, UInt<1>(0h0)) when _T_457 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_454, UInt<1>(0h1), "") : assert_20 node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(is_aligned, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_464 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_464, UInt<1>(0h1), "") : assert_23 node _T_468 = eq(io.in.a.bits.mask, mask) node _T_469 = asUInt(reset) node _T_470 = eq(_T_469, UInt<1>(0h0)) when _T_470 : node _T_471 = eq(_T_468, UInt<1>(0h0)) when _T_471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_468, UInt<1>(0h1), "") : assert_24 node _T_472 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_473 = asUInt(reset) node _T_474 = eq(_T_473, UInt<1>(0h0)) when _T_474 : node _T_475 = eq(_T_472, UInt<1>(0h0)) when _T_475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_472, UInt<1>(0h1), "") : assert_25 node _T_476 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_476 : node _T_477 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_478 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_479 = and(_T_477, _T_478) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 4, 0) node _T_480 = shr(io.in.a.bits.source, 5) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = leq(UInt<1>(0h0), uncommonBits_4) node _T_483 = and(_T_481, _T_482) node _T_484 = leq(uncommonBits_4, UInt<5>(0h1f)) node _T_485 = and(_T_483, _T_484) node _T_486 = and(_T_479, _T_485) node _T_487 = or(UInt<1>(0h0), _T_486) node _T_488 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_489 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_490 = and(_T_488, _T_489) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = and(_T_491, _T_496) node _T_498 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_499 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_500 = and(_T_498, _T_499) node _T_501 = or(UInt<1>(0h0), _T_500) node _T_502 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_503 = cvt(_T_502) node _T_504 = and(_T_503, asSInt(UInt<14>(0h2000))) node _T_505 = asSInt(_T_504) node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0))) node _T_507 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<18>(0h2f000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<17>(0h10000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_518 = cvt(_T_517) node _T_519 = and(_T_518, asSInt(UInt<13>(0h1000))) node _T_520 = asSInt(_T_519) node _T_521 = eq(_T_520, asSInt(UInt<1>(0h0))) node _T_522 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_523 = cvt(_T_522) node _T_524 = and(_T_523, asSInt(UInt<17>(0h10000))) node _T_525 = asSInt(_T_524) node _T_526 = eq(_T_525, asSInt(UInt<1>(0h0))) node _T_527 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_528 = cvt(_T_527) node _T_529 = and(_T_528, asSInt(UInt<27>(0h4000000))) node _T_530 = asSInt(_T_529) node _T_531 = eq(_T_530, asSInt(UInt<1>(0h0))) node _T_532 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_533 = cvt(_T_532) node _T_534 = and(_T_533, asSInt(UInt<13>(0h1000))) node _T_535 = asSInt(_T_534) node _T_536 = eq(_T_535, asSInt(UInt<1>(0h0))) node _T_537 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_538 = cvt(_T_537) node _T_539 = and(_T_538, asSInt(UInt<29>(0h10000000))) node _T_540 = asSInt(_T_539) node _T_541 = eq(_T_540, asSInt(UInt<1>(0h0))) node _T_542 = or(_T_506, _T_511) node _T_543 = or(_T_542, _T_516) node _T_544 = or(_T_543, _T_521) node _T_545 = or(_T_544, _T_526) node _T_546 = or(_T_545, _T_531) node _T_547 = or(_T_546, _T_536) node _T_548 = or(_T_547, _T_541) node _T_549 = and(_T_501, _T_548) node _T_550 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_551 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_552 = cvt(_T_551) node _T_553 = and(_T_552, asSInt(UInt<17>(0h10000))) node _T_554 = asSInt(_T_553) node _T_555 = eq(_T_554, asSInt(UInt<1>(0h0))) node _T_556 = and(_T_550, _T_555) node _T_557 = or(UInt<1>(0h0), _T_497) node _T_558 = or(_T_557, _T_549) node _T_559 = or(_T_558, _T_556) node _T_560 = and(_T_487, _T_559) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_560, UInt<1>(0h1), "") : assert_26 node _T_564 = asUInt(reset) node _T_565 = eq(_T_564, UInt<1>(0h0)) when _T_565 : node _T_566 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_567 = asUInt(reset) node _T_568 = eq(_T_567, UInt<1>(0h0)) when _T_568 : node _T_569 = eq(is_aligned, UInt<1>(0h0)) when _T_569 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_570 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_571 = asUInt(reset) node _T_572 = eq(_T_571, UInt<1>(0h0)) when _T_572 : node _T_573 = eq(_T_570, UInt<1>(0h0)) when _T_573 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_570, UInt<1>(0h1), "") : assert_29 node _T_574 = eq(io.in.a.bits.mask, mask) node _T_575 = asUInt(reset) node _T_576 = eq(_T_575, UInt<1>(0h0)) when _T_576 : node _T_577 = eq(_T_574, UInt<1>(0h0)) when _T_577 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_574, UInt<1>(0h1), "") : assert_30 node _T_578 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_578 : node _T_579 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_580 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_581 = and(_T_579, _T_580) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 4, 0) node _T_582 = shr(io.in.a.bits.source, 5) node _T_583 = eq(_T_582, UInt<1>(0h0)) node _T_584 = leq(UInt<1>(0h0), uncommonBits_5) node _T_585 = and(_T_583, _T_584) node _T_586 = leq(uncommonBits_5, UInt<5>(0h1f)) node _T_587 = and(_T_585, _T_586) node _T_588 = and(_T_581, _T_587) node _T_589 = or(UInt<1>(0h0), _T_588) node _T_590 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_591 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_592 = and(_T_590, _T_591) node _T_593 = or(UInt<1>(0h0), _T_592) node _T_594 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<13>(0h1000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = and(_T_593, _T_598) node _T_600 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_601 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_602 = and(_T_600, _T_601) node _T_603 = or(UInt<1>(0h0), _T_602) node _T_604 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_605 = cvt(_T_604) node _T_606 = and(_T_605, asSInt(UInt<14>(0h2000))) node _T_607 = asSInt(_T_606) node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0))) node _T_609 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<18>(0h2f000))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_615 = cvt(_T_614) node _T_616 = and(_T_615, asSInt(UInt<17>(0h10000))) node _T_617 = asSInt(_T_616) node _T_618 = eq(_T_617, asSInt(UInt<1>(0h0))) node _T_619 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_620 = cvt(_T_619) node _T_621 = and(_T_620, asSInt(UInt<13>(0h1000))) node _T_622 = asSInt(_T_621) node _T_623 = eq(_T_622, asSInt(UInt<1>(0h0))) node _T_624 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_625 = cvt(_T_624) node _T_626 = and(_T_625, asSInt(UInt<17>(0h10000))) node _T_627 = asSInt(_T_626) node _T_628 = eq(_T_627, asSInt(UInt<1>(0h0))) node _T_629 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_630 = cvt(_T_629) node _T_631 = and(_T_630, asSInt(UInt<27>(0h4000000))) node _T_632 = asSInt(_T_631) node _T_633 = eq(_T_632, asSInt(UInt<1>(0h0))) node _T_634 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_635 = cvt(_T_634) node _T_636 = and(_T_635, asSInt(UInt<13>(0h1000))) node _T_637 = asSInt(_T_636) node _T_638 = eq(_T_637, asSInt(UInt<1>(0h0))) node _T_639 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_640 = cvt(_T_639) node _T_641 = and(_T_640, asSInt(UInt<29>(0h10000000))) node _T_642 = asSInt(_T_641) node _T_643 = eq(_T_642, asSInt(UInt<1>(0h0))) node _T_644 = or(_T_608, _T_613) node _T_645 = or(_T_644, _T_618) node _T_646 = or(_T_645, _T_623) node _T_647 = or(_T_646, _T_628) node _T_648 = or(_T_647, _T_633) node _T_649 = or(_T_648, _T_638) node _T_650 = or(_T_649, _T_643) node _T_651 = and(_T_603, _T_650) node _T_652 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_653 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_654 = cvt(_T_653) node _T_655 = and(_T_654, asSInt(UInt<17>(0h10000))) node _T_656 = asSInt(_T_655) node _T_657 = eq(_T_656, asSInt(UInt<1>(0h0))) node _T_658 = and(_T_652, _T_657) node _T_659 = or(UInt<1>(0h0), _T_599) node _T_660 = or(_T_659, _T_651) node _T_661 = or(_T_660, _T_658) node _T_662 = and(_T_589, _T_661) node _T_663 = asUInt(reset) node _T_664 = eq(_T_663, UInt<1>(0h0)) when _T_664 : node _T_665 = eq(_T_662, UInt<1>(0h0)) when _T_665 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_662, UInt<1>(0h1), "") : assert_31 node _T_666 = asUInt(reset) node _T_667 = eq(_T_666, UInt<1>(0h0)) when _T_667 : node _T_668 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_668 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(is_aligned, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_672 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_673 = asUInt(reset) node _T_674 = eq(_T_673, UInt<1>(0h0)) when _T_674 : node _T_675 = eq(_T_672, UInt<1>(0h0)) when _T_675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_672, UInt<1>(0h1), "") : assert_34 node _T_676 = not(mask) node _T_677 = and(io.in.a.bits.mask, _T_676) node _T_678 = eq(_T_677, UInt<1>(0h0)) node _T_679 = asUInt(reset) node _T_680 = eq(_T_679, UInt<1>(0h0)) when _T_680 : node _T_681 = eq(_T_678, UInt<1>(0h0)) when _T_681 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_678, UInt<1>(0h1), "") : assert_35 node _T_682 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_682 : node _T_683 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_684 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_685 = and(_T_683, _T_684) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 4, 0) node _T_686 = shr(io.in.a.bits.source, 5) node _T_687 = eq(_T_686, UInt<1>(0h0)) node _T_688 = leq(UInt<1>(0h0), uncommonBits_6) node _T_689 = and(_T_687, _T_688) node _T_690 = leq(uncommonBits_6, UInt<5>(0h1f)) node _T_691 = and(_T_689, _T_690) node _T_692 = and(_T_685, _T_691) node _T_693 = or(UInt<1>(0h0), _T_692) node _T_694 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_695 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_696 = and(_T_694, _T_695) node _T_697 = or(UInt<1>(0h0), _T_696) node _T_698 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_699 = cvt(_T_698) node _T_700 = and(_T_699, asSInt(UInt<14>(0h2000))) node _T_701 = asSInt(_T_700) node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0))) node _T_703 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_704 = cvt(_T_703) node _T_705 = and(_T_704, asSInt(UInt<13>(0h1000))) node _T_706 = asSInt(_T_705) node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0))) node _T_708 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_709 = cvt(_T_708) node _T_710 = and(_T_709, asSInt(UInt<18>(0h2f000))) node _T_711 = asSInt(_T_710) node _T_712 = eq(_T_711, asSInt(UInt<1>(0h0))) node _T_713 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_714 = cvt(_T_713) node _T_715 = and(_T_714, asSInt(UInt<17>(0h10000))) node _T_716 = asSInt(_T_715) node _T_717 = eq(_T_716, asSInt(UInt<1>(0h0))) node _T_718 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_719 = cvt(_T_718) node _T_720 = and(_T_719, asSInt(UInt<13>(0h1000))) node _T_721 = asSInt(_T_720) node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0))) node _T_723 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_724 = cvt(_T_723) node _T_725 = and(_T_724, asSInt(UInt<17>(0h10000))) node _T_726 = asSInt(_T_725) node _T_727 = eq(_T_726, asSInt(UInt<1>(0h0))) node _T_728 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_729 = cvt(_T_728) node _T_730 = and(_T_729, asSInt(UInt<27>(0h4000000))) node _T_731 = asSInt(_T_730) node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0))) node _T_733 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_734 = cvt(_T_733) node _T_735 = and(_T_734, asSInt(UInt<13>(0h1000))) node _T_736 = asSInt(_T_735) node _T_737 = eq(_T_736, asSInt(UInt<1>(0h0))) node _T_738 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_739 = cvt(_T_738) node _T_740 = and(_T_739, asSInt(UInt<29>(0h10000000))) node _T_741 = asSInt(_T_740) node _T_742 = eq(_T_741, asSInt(UInt<1>(0h0))) node _T_743 = or(_T_702, _T_707) node _T_744 = or(_T_743, _T_712) node _T_745 = or(_T_744, _T_717) node _T_746 = or(_T_745, _T_722) node _T_747 = or(_T_746, _T_727) node _T_748 = or(_T_747, _T_732) node _T_749 = or(_T_748, _T_737) node _T_750 = or(_T_749, _T_742) node _T_751 = and(_T_697, _T_750) node _T_752 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_753 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_754 = cvt(_T_753) node _T_755 = and(_T_754, asSInt(UInt<17>(0h10000))) node _T_756 = asSInt(_T_755) node _T_757 = eq(_T_756, asSInt(UInt<1>(0h0))) node _T_758 = and(_T_752, _T_757) node _T_759 = or(UInt<1>(0h0), _T_751) node _T_760 = or(_T_759, _T_758) node _T_761 = and(_T_693, _T_760) node _T_762 = asUInt(reset) node _T_763 = eq(_T_762, UInt<1>(0h0)) when _T_763 : node _T_764 = eq(_T_761, UInt<1>(0h0)) when _T_764 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_761, UInt<1>(0h1), "") : assert_36 node _T_765 = asUInt(reset) node _T_766 = eq(_T_765, UInt<1>(0h0)) when _T_766 : node _T_767 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_767 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_768 = asUInt(reset) node _T_769 = eq(_T_768, UInt<1>(0h0)) when _T_769 : node _T_770 = eq(is_aligned, UInt<1>(0h0)) when _T_770 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_771 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_772 = asUInt(reset) node _T_773 = eq(_T_772, UInt<1>(0h0)) when _T_773 : node _T_774 = eq(_T_771, UInt<1>(0h0)) when _T_774 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_771, UInt<1>(0h1), "") : assert_39 node _T_775 = eq(io.in.a.bits.mask, mask) node _T_776 = asUInt(reset) node _T_777 = eq(_T_776, UInt<1>(0h0)) when _T_777 : node _T_778 = eq(_T_775, UInt<1>(0h0)) when _T_778 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_775, UInt<1>(0h1), "") : assert_40 node _T_779 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_779 : node _T_780 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_781 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_782 = and(_T_780, _T_781) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 4, 0) node _T_783 = shr(io.in.a.bits.source, 5) node _T_784 = eq(_T_783, UInt<1>(0h0)) node _T_785 = leq(UInt<1>(0h0), uncommonBits_7) node _T_786 = and(_T_784, _T_785) node _T_787 = leq(uncommonBits_7, UInt<5>(0h1f)) node _T_788 = and(_T_786, _T_787) node _T_789 = and(_T_782, _T_788) node _T_790 = or(UInt<1>(0h0), _T_789) node _T_791 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_792 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_793 = and(_T_791, _T_792) node _T_794 = or(UInt<1>(0h0), _T_793) node _T_795 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_796 = cvt(_T_795) node _T_797 = and(_T_796, asSInt(UInt<14>(0h2000))) node _T_798 = asSInt(_T_797) node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0))) node _T_800 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_801 = cvt(_T_800) node _T_802 = and(_T_801, asSInt(UInt<13>(0h1000))) node _T_803 = asSInt(_T_802) node _T_804 = eq(_T_803, asSInt(UInt<1>(0h0))) node _T_805 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_806 = cvt(_T_805) node _T_807 = and(_T_806, asSInt(UInt<18>(0h2f000))) node _T_808 = asSInt(_T_807) node _T_809 = eq(_T_808, asSInt(UInt<1>(0h0))) node _T_810 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_811 = cvt(_T_810) node _T_812 = and(_T_811, asSInt(UInt<17>(0h10000))) node _T_813 = asSInt(_T_812) node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0))) node _T_815 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_816 = cvt(_T_815) node _T_817 = and(_T_816, asSInt(UInt<13>(0h1000))) node _T_818 = asSInt(_T_817) node _T_819 = eq(_T_818, asSInt(UInt<1>(0h0))) node _T_820 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_821 = cvt(_T_820) node _T_822 = and(_T_821, asSInt(UInt<17>(0h10000))) node _T_823 = asSInt(_T_822) node _T_824 = eq(_T_823, asSInt(UInt<1>(0h0))) node _T_825 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_826 = cvt(_T_825) node _T_827 = and(_T_826, asSInt(UInt<27>(0h4000000))) node _T_828 = asSInt(_T_827) node _T_829 = eq(_T_828, asSInt(UInt<1>(0h0))) node _T_830 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_831 = cvt(_T_830) node _T_832 = and(_T_831, asSInt(UInt<13>(0h1000))) node _T_833 = asSInt(_T_832) node _T_834 = eq(_T_833, asSInt(UInt<1>(0h0))) node _T_835 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_836 = cvt(_T_835) node _T_837 = and(_T_836, asSInt(UInt<29>(0h10000000))) node _T_838 = asSInt(_T_837) node _T_839 = eq(_T_838, asSInt(UInt<1>(0h0))) node _T_840 = or(_T_799, _T_804) node _T_841 = or(_T_840, _T_809) node _T_842 = or(_T_841, _T_814) node _T_843 = or(_T_842, _T_819) node _T_844 = or(_T_843, _T_824) node _T_845 = or(_T_844, _T_829) node _T_846 = or(_T_845, _T_834) node _T_847 = or(_T_846, _T_839) node _T_848 = and(_T_794, _T_847) node _T_849 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_850 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_851 = cvt(_T_850) node _T_852 = and(_T_851, asSInt(UInt<17>(0h10000))) node _T_853 = asSInt(_T_852) node _T_854 = eq(_T_853, asSInt(UInt<1>(0h0))) node _T_855 = and(_T_849, _T_854) node _T_856 = or(UInt<1>(0h0), _T_848) node _T_857 = or(_T_856, _T_855) node _T_858 = and(_T_790, _T_857) node _T_859 = asUInt(reset) node _T_860 = eq(_T_859, UInt<1>(0h0)) when _T_860 : node _T_861 = eq(_T_858, UInt<1>(0h0)) when _T_861 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_858, UInt<1>(0h1), "") : assert_41 node _T_862 = asUInt(reset) node _T_863 = eq(_T_862, UInt<1>(0h0)) when _T_863 : node _T_864 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_865 = asUInt(reset) node _T_866 = eq(_T_865, UInt<1>(0h0)) when _T_866 : node _T_867 = eq(is_aligned, UInt<1>(0h0)) when _T_867 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_868 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_869 = asUInt(reset) node _T_870 = eq(_T_869, UInt<1>(0h0)) when _T_870 : node _T_871 = eq(_T_868, UInt<1>(0h0)) when _T_871 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_868, UInt<1>(0h1), "") : assert_44 node _T_872 = eq(io.in.a.bits.mask, mask) node _T_873 = asUInt(reset) node _T_874 = eq(_T_873, UInt<1>(0h0)) when _T_874 : node _T_875 = eq(_T_872, UInt<1>(0h0)) when _T_875 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_872, UInt<1>(0h1), "") : assert_45 node _T_876 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_876 : node _T_877 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_878 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_879 = and(_T_877, _T_878) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 4, 0) node _T_880 = shr(io.in.a.bits.source, 5) node _T_881 = eq(_T_880, UInt<1>(0h0)) node _T_882 = leq(UInt<1>(0h0), uncommonBits_8) node _T_883 = and(_T_881, _T_882) node _T_884 = leq(uncommonBits_8, UInt<5>(0h1f)) node _T_885 = and(_T_883, _T_884) node _T_886 = and(_T_879, _T_885) node _T_887 = or(UInt<1>(0h0), _T_886) node _T_888 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_889 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_890 = and(_T_888, _T_889) node _T_891 = or(UInt<1>(0h0), _T_890) node _T_892 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_893 = cvt(_T_892) node _T_894 = and(_T_893, asSInt(UInt<13>(0h1000))) node _T_895 = asSInt(_T_894) node _T_896 = eq(_T_895, asSInt(UInt<1>(0h0))) node _T_897 = and(_T_891, _T_896) node _T_898 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_899 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_900 = cvt(_T_899) node _T_901 = and(_T_900, asSInt(UInt<14>(0h2000))) node _T_902 = asSInt(_T_901) node _T_903 = eq(_T_902, asSInt(UInt<1>(0h0))) node _T_904 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_905 = cvt(_T_904) node _T_906 = and(_T_905, asSInt(UInt<17>(0h10000))) node _T_907 = asSInt(_T_906) node _T_908 = eq(_T_907, asSInt(UInt<1>(0h0))) node _T_909 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_910 = cvt(_T_909) node _T_911 = and(_T_910, asSInt(UInt<18>(0h2f000))) node _T_912 = asSInt(_T_911) node _T_913 = eq(_T_912, asSInt(UInt<1>(0h0))) node _T_914 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_915 = cvt(_T_914) node _T_916 = and(_T_915, asSInt(UInt<17>(0h10000))) node _T_917 = asSInt(_T_916) node _T_918 = eq(_T_917, asSInt(UInt<1>(0h0))) node _T_919 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_920 = cvt(_T_919) node _T_921 = and(_T_920, asSInt(UInt<13>(0h1000))) node _T_922 = asSInt(_T_921) node _T_923 = eq(_T_922, asSInt(UInt<1>(0h0))) node _T_924 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_925 = cvt(_T_924) node _T_926 = and(_T_925, asSInt(UInt<27>(0h4000000))) node _T_927 = asSInt(_T_926) node _T_928 = eq(_T_927, asSInt(UInt<1>(0h0))) node _T_929 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_930 = cvt(_T_929) node _T_931 = and(_T_930, asSInt(UInt<13>(0h1000))) node _T_932 = asSInt(_T_931) node _T_933 = eq(_T_932, asSInt(UInt<1>(0h0))) node _T_934 = or(_T_903, _T_908) node _T_935 = or(_T_934, _T_913) node _T_936 = or(_T_935, _T_918) node _T_937 = or(_T_936, _T_923) node _T_938 = or(_T_937, _T_928) node _T_939 = or(_T_938, _T_933) node _T_940 = and(_T_898, _T_939) node _T_941 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_942 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_943 = and(_T_941, _T_942) node _T_944 = or(UInt<1>(0h0), _T_943) node _T_945 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_946 = cvt(_T_945) node _T_947 = and(_T_946, asSInt(UInt<17>(0h10000))) node _T_948 = asSInt(_T_947) node _T_949 = eq(_T_948, asSInt(UInt<1>(0h0))) node _T_950 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_951 = cvt(_T_950) node _T_952 = and(_T_951, asSInt(UInt<29>(0h10000000))) node _T_953 = asSInt(_T_952) node _T_954 = eq(_T_953, asSInt(UInt<1>(0h0))) node _T_955 = or(_T_949, _T_954) node _T_956 = and(_T_944, _T_955) node _T_957 = or(UInt<1>(0h0), _T_897) node _T_958 = or(_T_957, _T_940) node _T_959 = or(_T_958, _T_956) node _T_960 = and(_T_887, _T_959) node _T_961 = asUInt(reset) node _T_962 = eq(_T_961, UInt<1>(0h0)) when _T_962 : node _T_963 = eq(_T_960, UInt<1>(0h0)) when _T_963 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_960, UInt<1>(0h1), "") : assert_46 node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_967 = asUInt(reset) node _T_968 = eq(_T_967, UInt<1>(0h0)) when _T_968 : node _T_969 = eq(is_aligned, UInt<1>(0h0)) when _T_969 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_970 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_971 = asUInt(reset) node _T_972 = eq(_T_971, UInt<1>(0h0)) when _T_972 : node _T_973 = eq(_T_970, UInt<1>(0h0)) when _T_973 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_970, UInt<1>(0h1), "") : assert_49 node _T_974 = eq(io.in.a.bits.mask, mask) node _T_975 = asUInt(reset) node _T_976 = eq(_T_975, UInt<1>(0h0)) when _T_976 : node _T_977 = eq(_T_974, UInt<1>(0h0)) when _T_977 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_974, UInt<1>(0h1), "") : assert_50 node _T_978 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_979 = asUInt(reset) node _T_980 = eq(_T_979, UInt<1>(0h0)) when _T_980 : node _T_981 = eq(_T_978, UInt<1>(0h0)) when _T_981 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_978, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_982 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_983 = asUInt(reset) node _T_984 = eq(_T_983, UInt<1>(0h0)) when _T_984 : node _T_985 = eq(_T_982, UInt<1>(0h0)) when _T_985 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_982, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 4, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 5) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<5>(0h1f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_986 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_986 : node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_990 = geq(io.in.d.bits.size, UInt<3>(0h5)) node _T_991 = asUInt(reset) node _T_992 = eq(_T_991, UInt<1>(0h0)) when _T_992 : node _T_993 = eq(_T_990, UInt<1>(0h0)) when _T_993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_990, UInt<1>(0h1), "") : assert_54 node _T_994 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_995 = asUInt(reset) node _T_996 = eq(_T_995, UInt<1>(0h0)) when _T_996 : node _T_997 = eq(_T_994, UInt<1>(0h0)) when _T_997 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_994, UInt<1>(0h1), "") : assert_55 node _T_998 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_999 = asUInt(reset) node _T_1000 = eq(_T_999, UInt<1>(0h0)) when _T_1000 : node _T_1001 = eq(_T_998, UInt<1>(0h0)) when _T_1001 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_998, UInt<1>(0h1), "") : assert_56 node _T_1002 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1003 = asUInt(reset) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) when _T_1004 : node _T_1005 = eq(_T_1002, UInt<1>(0h0)) when _T_1005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1002, UInt<1>(0h1), "") : assert_57 node _T_1006 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1006 : node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(sink_ok, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1013 = geq(io.in.d.bits.size, UInt<3>(0h5)) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_60 node _T_1017 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_61 node _T_1021 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1022 = asUInt(reset) node _T_1023 = eq(_T_1022, UInt<1>(0h0)) when _T_1023 : node _T_1024 = eq(_T_1021, UInt<1>(0h0)) when _T_1024 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1021, UInt<1>(0h1), "") : assert_62 node _T_1025 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1026 = asUInt(reset) node _T_1027 = eq(_T_1026, UInt<1>(0h0)) when _T_1027 : node _T_1028 = eq(_T_1025, UInt<1>(0h0)) when _T_1028 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1025, UInt<1>(0h1), "") : assert_63 node _T_1029 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1030 = or(UInt<1>(0h1), _T_1029) node _T_1031 = asUInt(reset) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) when _T_1032 : node _T_1033 = eq(_T_1030, UInt<1>(0h0)) when _T_1033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1030, UInt<1>(0h1), "") : assert_64 node _T_1034 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1034 : node _T_1035 = asUInt(reset) node _T_1036 = eq(_T_1035, UInt<1>(0h0)) when _T_1036 : node _T_1037 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1037 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_1038 = asUInt(reset) node _T_1039 = eq(_T_1038, UInt<1>(0h0)) when _T_1039 : node _T_1040 = eq(sink_ok, UInt<1>(0h0)) when _T_1040 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1041 = geq(io.in.d.bits.size, UInt<3>(0h5)) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_67 node _T_1045 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_T_1045, UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1045, UInt<1>(0h1), "") : assert_68 node _T_1049 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_69 node _T_1053 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1054 = or(_T_1053, io.in.d.bits.corrupt) node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(_T_1054, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1054, UInt<1>(0h1), "") : assert_70 node _T_1058 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1059 = or(UInt<1>(0h1), _T_1058) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_71 node _T_1063 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1063 : node _T_1064 = asUInt(reset) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) when _T_1065 : node _T_1066 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1067 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1068 = asUInt(reset) node _T_1069 = eq(_T_1068, UInt<1>(0h0)) when _T_1069 : node _T_1070 = eq(_T_1067, UInt<1>(0h0)) when _T_1070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1067, UInt<1>(0h1), "") : assert_73 node _T_1071 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1072 = asUInt(reset) node _T_1073 = eq(_T_1072, UInt<1>(0h0)) when _T_1073 : node _T_1074 = eq(_T_1071, UInt<1>(0h0)) when _T_1074 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1071, UInt<1>(0h1), "") : assert_74 node _T_1075 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1076 = or(UInt<1>(0h1), _T_1075) node _T_1077 = asUInt(reset) node _T_1078 = eq(_T_1077, UInt<1>(0h0)) when _T_1078 : node _T_1079 = eq(_T_1076, UInt<1>(0h0)) when _T_1079 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1076, UInt<1>(0h1), "") : assert_75 node _T_1080 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1080 : node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1084 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_77 node _T_1088 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1089 = or(_T_1088, io.in.d.bits.corrupt) node _T_1090 = asUInt(reset) node _T_1091 = eq(_T_1090, UInt<1>(0h0)) when _T_1091 : node _T_1092 = eq(_T_1089, UInt<1>(0h0)) when _T_1092 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1089, UInt<1>(0h1), "") : assert_78 node _T_1093 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1094 = or(UInt<1>(0h1), _T_1093) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_79 node _T_1098 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1098 : node _T_1099 = asUInt(reset) node _T_1100 = eq(_T_1099, UInt<1>(0h0)) when _T_1100 : node _T_1101 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1101 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1102 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1103 = asUInt(reset) node _T_1104 = eq(_T_1103, UInt<1>(0h0)) when _T_1104 : node _T_1105 = eq(_T_1102, UInt<1>(0h0)) when _T_1105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1102, UInt<1>(0h1), "") : assert_81 node _T_1106 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1107 = asUInt(reset) node _T_1108 = eq(_T_1107, UInt<1>(0h0)) when _T_1108 : node _T_1109 = eq(_T_1106, UInt<1>(0h0)) when _T_1109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1106, UInt<1>(0h1), "") : assert_82 node _T_1110 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1111 = or(UInt<1>(0h1), _T_1110) node _T_1112 = asUInt(reset) node _T_1113 = eq(_T_1112, UInt<1>(0h0)) when _T_1113 : node _T_1114 = eq(_T_1111, UInt<1>(0h0)) when _T_1114 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1111, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<256>(0h0) connect _WIRE.bits.mask, UInt<32>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<5>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1115 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1116 = asUInt(reset) node _T_1117 = eq(_T_1116, UInt<1>(0h0)) when _T_1117 : node _T_1118 = eq(_T_1115, UInt<1>(0h0)) when _T_1118 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1115, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<256>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<5>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1119 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1120 = asUInt(reset) node _T_1121 = eq(_T_1120, UInt<1>(0h0)) when _T_1121 : node _T_1122 = eq(_T_1119, UInt<1>(0h0)) when _T_1122 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1119, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1123 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1124 = asUInt(reset) node _T_1125 = eq(_T_1124, UInt<1>(0h0)) when _T_1125 : node _T_1126 = eq(_T_1123, UInt<1>(0h0)) when _T_1126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1123, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 5) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<7>, clock, reset, UInt<7>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1127 = eq(a_first, UInt<1>(0h0)) node _T_1128 = and(io.in.a.valid, _T_1127) when _T_1128 : node _T_1129 = eq(io.in.a.bits.opcode, opcode) node _T_1130 = asUInt(reset) node _T_1131 = eq(_T_1130, UInt<1>(0h0)) when _T_1131 : node _T_1132 = eq(_T_1129, UInt<1>(0h0)) when _T_1132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1129, UInt<1>(0h1), "") : assert_87 node _T_1133 = eq(io.in.a.bits.param, param) node _T_1134 = asUInt(reset) node _T_1135 = eq(_T_1134, UInt<1>(0h0)) when _T_1135 : node _T_1136 = eq(_T_1133, UInt<1>(0h0)) when _T_1136 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1133, UInt<1>(0h1), "") : assert_88 node _T_1137 = eq(io.in.a.bits.size, size) node _T_1138 = asUInt(reset) node _T_1139 = eq(_T_1138, UInt<1>(0h0)) when _T_1139 : node _T_1140 = eq(_T_1137, UInt<1>(0h0)) when _T_1140 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1137, UInt<1>(0h1), "") : assert_89 node _T_1141 = eq(io.in.a.bits.source, source) node _T_1142 = asUInt(reset) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) when _T_1143 : node _T_1144 = eq(_T_1141, UInt<1>(0h0)) when _T_1144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1141, UInt<1>(0h1), "") : assert_90 node _T_1145 = eq(io.in.a.bits.address, address) node _T_1146 = asUInt(reset) node _T_1147 = eq(_T_1146, UInt<1>(0h0)) when _T_1147 : node _T_1148 = eq(_T_1145, UInt<1>(0h0)) when _T_1148 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1145, UInt<1>(0h1), "") : assert_91 node _T_1149 = and(io.in.a.ready, io.in.a.valid) node _T_1150 = and(_T_1149, a_first) when _T_1150 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 5) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<7>, clock, reset, UInt<7>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1151 = eq(d_first, UInt<1>(0h0)) node _T_1152 = and(io.in.d.valid, _T_1151) when _T_1152 : node _T_1153 = eq(io.in.d.bits.opcode, opcode_1) node _T_1154 = asUInt(reset) node _T_1155 = eq(_T_1154, UInt<1>(0h0)) when _T_1155 : node _T_1156 = eq(_T_1153, UInt<1>(0h0)) when _T_1156 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1153, UInt<1>(0h1), "") : assert_92 node _T_1157 = eq(io.in.d.bits.param, param_1) node _T_1158 = asUInt(reset) node _T_1159 = eq(_T_1158, UInt<1>(0h0)) when _T_1159 : node _T_1160 = eq(_T_1157, UInt<1>(0h0)) when _T_1160 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1157, UInt<1>(0h1), "") : assert_93 node _T_1161 = eq(io.in.d.bits.size, size_1) node _T_1162 = asUInt(reset) node _T_1163 = eq(_T_1162, UInt<1>(0h0)) when _T_1163 : node _T_1164 = eq(_T_1161, UInt<1>(0h0)) when _T_1164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1161, UInt<1>(0h1), "") : assert_94 node _T_1165 = eq(io.in.d.bits.source, source_1) node _T_1166 = asUInt(reset) node _T_1167 = eq(_T_1166, UInt<1>(0h0)) when _T_1167 : node _T_1168 = eq(_T_1165, UInt<1>(0h0)) when _T_1168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1165, UInt<1>(0h1), "") : assert_95 node _T_1169 = eq(io.in.d.bits.sink, sink) node _T_1170 = asUInt(reset) node _T_1171 = eq(_T_1170, UInt<1>(0h0)) when _T_1171 : node _T_1172 = eq(_T_1169, UInt<1>(0h0)) when _T_1172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1169, UInt<1>(0h1), "") : assert_96 node _T_1173 = eq(io.in.d.bits.denied, denied) node _T_1174 = asUInt(reset) node _T_1175 = eq(_T_1174, UInt<1>(0h0)) when _T_1175 : node _T_1176 = eq(_T_1173, UInt<1>(0h0)) when _T_1176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1173, UInt<1>(0h1), "") : assert_97 node _T_1177 = and(io.in.d.ready, io.in.d.valid) node _T_1178 = and(_T_1177, d_first) when _T_1178 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<32>, clock, reset, UInt<32>(0h0) regreset inflight_opcodes : UInt<128>, clock, reset, UInt<128>(0h0) regreset inflight_sizes : UInt<256>, clock, reset, UInt<256>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 5) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<7>, clock, reset, UInt<7>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 5) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<7>, clock, reset, UInt<7>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<32> connect a_set, UInt<32>(0h0) wire a_set_wo_ready : UInt<32> connect a_set_wo_ready, UInt<32>(0h0) wire a_opcodes_set : UInt<128> connect a_opcodes_set, UInt<128>(0h0) wire a_sizes_set : UInt<256> connect a_sizes_set, UInt<256>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1179 = and(io.in.a.valid, a_first_1) node _T_1180 = and(_T_1179, UInt<1>(0h1)) when _T_1180 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1181 = and(io.in.a.ready, io.in.a.valid) node _T_1182 = and(_T_1181, a_first_1) node _T_1183 = and(_T_1182, UInt<1>(0h1)) when _T_1183 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1184 = dshr(inflight, io.in.a.bits.source) node _T_1185 = bits(_T_1184, 0, 0) node _T_1186 = eq(_T_1185, UInt<1>(0h0)) node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(_T_1186, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1186, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<32> connect d_clr, UInt<32>(0h0) wire d_clr_wo_ready : UInt<32> connect d_clr_wo_ready, UInt<32>(0h0) wire d_opcodes_clr : UInt<128> connect d_opcodes_clr, UInt<128>(0h0) wire d_sizes_clr : UInt<256> connect d_sizes_clr, UInt<256>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1190 = and(io.in.d.valid, d_first_1) node _T_1191 = and(_T_1190, UInt<1>(0h1)) node _T_1192 = eq(d_release_ack, UInt<1>(0h0)) node _T_1193 = and(_T_1191, _T_1192) when _T_1193 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1194 = and(io.in.d.ready, io.in.d.valid) node _T_1195 = and(_T_1194, d_first_1) node _T_1196 = and(_T_1195, UInt<1>(0h1)) node _T_1197 = eq(d_release_ack, UInt<1>(0h0)) node _T_1198 = and(_T_1196, _T_1197) when _T_1198 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1199 = and(io.in.d.valid, d_first_1) node _T_1200 = and(_T_1199, UInt<1>(0h1)) node _T_1201 = eq(d_release_ack, UInt<1>(0h0)) node _T_1202 = and(_T_1200, _T_1201) when _T_1202 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1203 = dshr(inflight, io.in.d.bits.source) node _T_1204 = bits(_T_1203, 0, 0) node _T_1205 = or(_T_1204, same_cycle_resp) node _T_1206 = asUInt(reset) node _T_1207 = eq(_T_1206, UInt<1>(0h0)) when _T_1207 : node _T_1208 = eq(_T_1205, UInt<1>(0h0)) when _T_1208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1205, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1209 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1210 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1211 = or(_T_1209, _T_1210) node _T_1212 = asUInt(reset) node _T_1213 = eq(_T_1212, UInt<1>(0h0)) when _T_1213 : node _T_1214 = eq(_T_1211, UInt<1>(0h0)) when _T_1214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1211, UInt<1>(0h1), "") : assert_100 node _T_1215 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1216 = asUInt(reset) node _T_1217 = eq(_T_1216, UInt<1>(0h0)) when _T_1217 : node _T_1218 = eq(_T_1215, UInt<1>(0h0)) when _T_1218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1215, UInt<1>(0h1), "") : assert_101 else : node _T_1219 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1220 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1221 = or(_T_1219, _T_1220) node _T_1222 = asUInt(reset) node _T_1223 = eq(_T_1222, UInt<1>(0h0)) when _T_1223 : node _T_1224 = eq(_T_1221, UInt<1>(0h0)) when _T_1224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1221, UInt<1>(0h1), "") : assert_102 node _T_1225 = eq(io.in.d.bits.size, a_size_lookup) node _T_1226 = asUInt(reset) node _T_1227 = eq(_T_1226, UInt<1>(0h0)) when _T_1227 : node _T_1228 = eq(_T_1225, UInt<1>(0h0)) when _T_1228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1225, UInt<1>(0h1), "") : assert_103 node _T_1229 = and(io.in.d.valid, d_first_1) node _T_1230 = and(_T_1229, a_first_1) node _T_1231 = and(_T_1230, io.in.a.valid) node _T_1232 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1233 = and(_T_1231, _T_1232) node _T_1234 = eq(d_release_ack, UInt<1>(0h0)) node _T_1235 = and(_T_1233, _T_1234) when _T_1235 : node _T_1236 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1237 = or(_T_1236, io.in.a.ready) node _T_1238 = asUInt(reset) node _T_1239 = eq(_T_1238, UInt<1>(0h0)) when _T_1239 : node _T_1240 = eq(_T_1237, UInt<1>(0h0)) when _T_1240 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1237, UInt<1>(0h1), "") : assert_104 node _T_1241 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1242 = orr(a_set_wo_ready) node _T_1243 = eq(_T_1242, UInt<1>(0h0)) node _T_1244 = or(_T_1241, _T_1243) node _T_1245 = asUInt(reset) node _T_1246 = eq(_T_1245, UInt<1>(0h0)) when _T_1246 : node _T_1247 = eq(_T_1244, UInt<1>(0h0)) when _T_1247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1244, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_138 node _T_1248 = orr(inflight) node _T_1249 = eq(_T_1248, UInt<1>(0h0)) node _T_1250 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1251 = or(_T_1249, _T_1250) node _T_1252 = lt(watchdog, plusarg_reader.out) node _T_1253 = or(_T_1251, _T_1252) node _T_1254 = asUInt(reset) node _T_1255 = eq(_T_1254, UInt<1>(0h0)) when _T_1255 : node _T_1256 = eq(_T_1253, UInt<1>(0h0)) when _T_1256 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1253, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1257 = and(io.in.a.ready, io.in.a.valid) node _T_1258 = and(io.in.d.ready, io.in.d.valid) node _T_1259 = or(_T_1257, _T_1258) when _T_1259 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<32>, clock, reset, UInt<32>(0h0) regreset inflight_opcodes_1 : UInt<128>, clock, reset, UInt<128>(0h0) regreset inflight_sizes_1 : UInt<256>, clock, reset, UInt<256>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<256>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<5>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<256>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<5>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 5) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<7>, clock, reset, UInt<7>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 5) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<7>, clock, reset, UInt<7>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<32> connect c_set, UInt<32>(0h0) wire c_set_wo_ready : UInt<32> connect c_set_wo_ready, UInt<32>(0h0) wire c_opcodes_set : UInt<128> connect c_opcodes_set, UInt<128>(0h0) wire c_sizes_set : UInt<256> connect c_sizes_set, UInt<256>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<256>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<5>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1260 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<256>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<5>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1261 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1262 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1263 = and(_T_1261, _T_1262) node _T_1264 = and(_T_1260, _T_1263) when _T_1264 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<256>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<5>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<256>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<5>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1265 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1266 = and(_T_1265, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<256>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<5>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1267 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1268 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1269 = and(_T_1267, _T_1268) node _T_1270 = and(_T_1266, _T_1269) when _T_1270 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<256>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<5>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<256>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<5>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<256>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<5>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<256>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<5>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<256>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<5>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<256>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<5>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1271 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1272 = bits(_T_1271, 0, 0) node _T_1273 = eq(_T_1272, UInt<1>(0h0)) node _T_1274 = asUInt(reset) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) when _T_1275 : node _T_1276 = eq(_T_1273, UInt<1>(0h0)) when _T_1276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1273, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<256>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<5>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<256>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<5>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<32> connect d_clr_1, UInt<32>(0h0) wire d_clr_wo_ready_1 : UInt<32> connect d_clr_wo_ready_1, UInt<32>(0h0) wire d_opcodes_clr_1 : UInt<128> connect d_opcodes_clr_1, UInt<128>(0h0) wire d_sizes_clr_1 : UInt<256> connect d_sizes_clr_1, UInt<256>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1277 = and(io.in.d.valid, d_first_2) node _T_1278 = and(_T_1277, UInt<1>(0h1)) node _T_1279 = and(_T_1278, d_release_ack_1) when _T_1279 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1280 = and(io.in.d.ready, io.in.d.valid) node _T_1281 = and(_T_1280, d_first_2) node _T_1282 = and(_T_1281, UInt<1>(0h1)) node _T_1283 = and(_T_1282, d_release_ack_1) when _T_1283 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1284 = and(io.in.d.valid, d_first_2) node _T_1285 = and(_T_1284, UInt<1>(0h1)) node _T_1286 = and(_T_1285, d_release_ack_1) when _T_1286 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<256>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<256>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<256>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1287 = dshr(inflight_1, io.in.d.bits.source) node _T_1288 = bits(_T_1287, 0, 0) node _T_1289 = or(_T_1288, same_cycle_resp_1) node _T_1290 = asUInt(reset) node _T_1291 = eq(_T_1290, UInt<1>(0h0)) when _T_1291 : node _T_1292 = eq(_T_1289, UInt<1>(0h0)) when _T_1292 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1289, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<256>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<5>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1293 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1294 = asUInt(reset) node _T_1295 = eq(_T_1294, UInt<1>(0h0)) when _T_1295 : node _T_1296 = eq(_T_1293, UInt<1>(0h0)) when _T_1296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1293, UInt<1>(0h1), "") : assert_109 else : node _T_1297 = eq(io.in.d.bits.size, c_size_lookup) node _T_1298 = asUInt(reset) node _T_1299 = eq(_T_1298, UInt<1>(0h0)) when _T_1299 : node _T_1300 = eq(_T_1297, UInt<1>(0h0)) when _T_1300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1297, UInt<1>(0h1), "") : assert_110 node _T_1301 = and(io.in.d.valid, d_first_2) node _T_1302 = and(_T_1301, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<256>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<5>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1303 = and(_T_1302, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<256>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<5>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1304 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1305 = and(_T_1303, _T_1304) node _T_1306 = and(_T_1305, d_release_ack_1) node _T_1307 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1308 = and(_T_1306, _T_1307) when _T_1308 : node _T_1309 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<256>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<5>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1310 = or(_T_1309, _WIRE_23.ready) node _T_1311 = asUInt(reset) node _T_1312 = eq(_T_1311, UInt<1>(0h0)) when _T_1312 : node _T_1313 = eq(_T_1310, UInt<1>(0h0)) when _T_1313 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1310, UInt<1>(0h1), "") : assert_111 node _T_1314 = orr(c_set_wo_ready) when _T_1314 : node _T_1315 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1316 = asUInt(reset) node _T_1317 = eq(_T_1316, UInt<1>(0h0)) when _T_1317 : node _T_1318 = eq(_T_1315, UInt<1>(0h0)) when _T_1318 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1315, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_139 node _T_1319 = orr(inflight_1) node _T_1320 = eq(_T_1319, UInt<1>(0h0)) node _T_1321 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1322 = or(_T_1320, _T_1321) node _T_1323 = lt(watchdog_1, plusarg_reader_1.out) node _T_1324 = or(_T_1322, _T_1323) node _T_1325 = asUInt(reset) node _T_1326 = eq(_T_1325, UInt<1>(0h0)) when _T_1326 : node _T_1327 = eq(_T_1324, UInt<1>(0h0)) when _T_1327 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:74:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1324, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<256>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<5>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1328 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1329 = and(io.in.d.ready, io.in.d.valid) node _T_1330 = or(_T_1328, _T_1329) when _T_1330 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_69( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [255:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [255:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [255:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [255:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [6:0] c_first_beats1_decode = 7'h0; // @[Edges.scala:220:59] wire [6:0] c_first_beats1 = 7'h0; // @[Edges.scala:221:14] wire [6:0] _c_first_count_T = 7'h0; // @[Edges.scala:234:27] wire [6:0] c_first_count = 7'h0; // @[Edges.scala:234:25] wire [6:0] _c_first_counter_T = 7'h0; // @[Edges.scala:236:21] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:56:48] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:56:48] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [6:0] c_first_counter1 = 7'h7F; // @[Edges.scala:230:28] wire [7:0] _c_first_counter1_T = 8'hFF; // @[Edges.scala:230:28] wire [255:0] _c_first_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_first_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_first_WIRE_2_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_first_WIRE_3_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] c_sizes_set = 256'h0; // @[Monitor.scala:741:34] wire [255:0] _c_set_wo_ready_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_set_wo_ready_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_set_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_set_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_opcodes_set_interm_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_opcodes_set_interm_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_sizes_set_interm_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_sizes_set_interm_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_opcodes_set_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_opcodes_set_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_sizes_set_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_sizes_set_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_probe_ack_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_probe_ack_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_probe_ack_WIRE_2_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_probe_ack_WIRE_3_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _same_cycle_resp_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _same_cycle_resp_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _same_cycle_resp_WIRE_2_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _same_cycle_resp_WIRE_3_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _same_cycle_resp_WIRE_4_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _same_cycle_resp_WIRE_5_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] c_set = 32'h0; // @[Monitor.scala:738:34] wire [31:0] c_set_wo_ready = 32'h0; // @[Monitor.scala:739:34] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [259:0] _c_sizes_set_T_1 = 260'h0; // @[Monitor.scala:768:52] wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79] wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77] wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35] wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35] wire [127:0] c_opcodes_set = 128'h0; // @[Monitor.scala:740:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [4:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [2:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[2:0]; // @[OneHot.scala:64:49] wire [7:0] _mask_sizeOH_T_1 = 8'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [4:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[4:0]; // @[OneHot.scala:65:{12,27}] wire [4:0] mask_sizeOH = {_mask_sizeOH_T_2[4:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h4; // @[Misc.scala:206:21] wire mask_sub_sub_sub_sub_size = mask_sizeOH[4]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_sub_bit = io_in_a_bits_address_0[4]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_sub_1_2 = mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_sub_nbit = ~mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_sub_0_2 = mask_sub_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_sub_acc_T = mask_sub_sub_sub_sub_size & mask_sub_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_sub_size & mask_sub_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_sub_0_2 & mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_sub_0_2 & mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_2_2 = mask_sub_sub_sub_sub_1_2 & mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T_2 = mask_sub_sub_sub_size & mask_sub_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_2_1 = mask_sub_sub_sub_sub_1_1 | _mask_sub_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_3_2 = mask_sub_sub_sub_sub_1_2 & mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_sub_acc_T_3 = mask_sub_sub_sub_size & mask_sub_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_3_1 = mask_sub_sub_sub_sub_1_1 | _mask_sub_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_4_2 = mask_sub_sub_sub_2_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_4 = mask_sub_sub_size & mask_sub_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_4_1 = mask_sub_sub_sub_2_1 | _mask_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_5_2 = mask_sub_sub_sub_2_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_5 = mask_sub_sub_size & mask_sub_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_5_1 = mask_sub_sub_sub_2_1 | _mask_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_6_2 = mask_sub_sub_sub_3_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_6 = mask_sub_sub_size & mask_sub_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_6_1 = mask_sub_sub_sub_3_1 | _mask_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_7_2 = mask_sub_sub_sub_3_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_7 = mask_sub_sub_size & mask_sub_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_7_1 = mask_sub_sub_sub_3_1 | _mask_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_sub_8_2 = mask_sub_sub_4_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_8 = mask_sub_size & mask_sub_8_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_8_1 = mask_sub_sub_4_1 | _mask_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_sub_9_2 = mask_sub_sub_4_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_9 = mask_sub_size & mask_sub_9_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_9_1 = mask_sub_sub_4_1 | _mask_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_sub_10_2 = mask_sub_sub_5_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_10 = mask_sub_size & mask_sub_10_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_10_1 = mask_sub_sub_5_1 | _mask_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_sub_11_2 = mask_sub_sub_5_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_11 = mask_sub_size & mask_sub_11_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_11_1 = mask_sub_sub_5_1 | _mask_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_sub_12_2 = mask_sub_sub_6_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_12 = mask_sub_size & mask_sub_12_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_12_1 = mask_sub_sub_6_1 | _mask_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_sub_13_2 = mask_sub_sub_6_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_13 = mask_sub_size & mask_sub_13_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_13_1 = mask_sub_sub_6_1 | _mask_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_sub_14_2 = mask_sub_sub_7_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_14 = mask_sub_size & mask_sub_14_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_14_1 = mask_sub_sub_7_1 | _mask_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_sub_15_2 = mask_sub_sub_7_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_15 = mask_sub_size & mask_sub_15_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_15_1 = mask_sub_sub_7_1 | _mask_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_4_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_4_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_5_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_5_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_6_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_6_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_7_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_7_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire mask_eq_16 = mask_sub_8_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_16 = mask_size & mask_eq_16; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_16 = mask_sub_8_1 | _mask_acc_T_16; // @[Misc.scala:215:{29,38}] wire mask_eq_17 = mask_sub_8_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_17 = mask_size & mask_eq_17; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_17 = mask_sub_8_1 | _mask_acc_T_17; // @[Misc.scala:215:{29,38}] wire mask_eq_18 = mask_sub_9_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_18 = mask_size & mask_eq_18; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_18 = mask_sub_9_1 | _mask_acc_T_18; // @[Misc.scala:215:{29,38}] wire mask_eq_19 = mask_sub_9_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_19 = mask_size & mask_eq_19; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_19 = mask_sub_9_1 | _mask_acc_T_19; // @[Misc.scala:215:{29,38}] wire mask_eq_20 = mask_sub_10_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_20 = mask_size & mask_eq_20; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_20 = mask_sub_10_1 | _mask_acc_T_20; // @[Misc.scala:215:{29,38}] wire mask_eq_21 = mask_sub_10_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_21 = mask_size & mask_eq_21; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_21 = mask_sub_10_1 | _mask_acc_T_21; // @[Misc.scala:215:{29,38}] wire mask_eq_22 = mask_sub_11_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_22 = mask_size & mask_eq_22; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_22 = mask_sub_11_1 | _mask_acc_T_22; // @[Misc.scala:215:{29,38}] wire mask_eq_23 = mask_sub_11_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_23 = mask_size & mask_eq_23; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_23 = mask_sub_11_1 | _mask_acc_T_23; // @[Misc.scala:215:{29,38}] wire mask_eq_24 = mask_sub_12_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_24 = mask_size & mask_eq_24; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_24 = mask_sub_12_1 | _mask_acc_T_24; // @[Misc.scala:215:{29,38}] wire mask_eq_25 = mask_sub_12_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_25 = mask_size & mask_eq_25; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_25 = mask_sub_12_1 | _mask_acc_T_25; // @[Misc.scala:215:{29,38}] wire mask_eq_26 = mask_sub_13_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_26 = mask_size & mask_eq_26; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_26 = mask_sub_13_1 | _mask_acc_T_26; // @[Misc.scala:215:{29,38}] wire mask_eq_27 = mask_sub_13_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_27 = mask_size & mask_eq_27; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_27 = mask_sub_13_1 | _mask_acc_T_27; // @[Misc.scala:215:{29,38}] wire mask_eq_28 = mask_sub_14_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_28 = mask_size & mask_eq_28; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_28 = mask_sub_14_1 | _mask_acc_T_28; // @[Misc.scala:215:{29,38}] wire mask_eq_29 = mask_sub_14_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_29 = mask_size & mask_eq_29; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_29 = mask_sub_14_1 | _mask_acc_T_29; // @[Misc.scala:215:{29,38}] wire mask_eq_30 = mask_sub_15_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_30 = mask_size & mask_eq_30; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_30 = mask_sub_15_1 | _mask_acc_T_30; // @[Misc.scala:215:{29,38}] wire mask_eq_31 = mask_sub_15_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_31 = mask_size & mask_eq_31; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_31 = mask_sub_15_1 | _mask_acc_T_31; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo_lo = {mask_lo_lo_lo_hi, mask_lo_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo_hi = {mask_lo_lo_hi_hi, mask_lo_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi_lo = {mask_lo_hi_lo_hi, mask_lo_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi_hi = {mask_lo_hi_hi_hi, mask_lo_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo_lo = {mask_acc_17, mask_acc_16}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_lo_hi = {mask_acc_19, mask_acc_18}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo_lo = {mask_hi_lo_lo_hi, mask_hi_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_hi_lo = {mask_acc_21, mask_acc_20}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi_hi = {mask_acc_23, mask_acc_22}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo_hi = {mask_hi_lo_hi_hi, mask_hi_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo_lo = {mask_acc_25, mask_acc_24}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_lo_hi = {mask_acc_27, mask_acc_26}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi_lo = {mask_hi_hi_lo_hi, mask_hi_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_hi_lo = {mask_acc_29, mask_acc_28}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi_hi = {mask_acc_31, mask_acc_30}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi_hi = {mask_hi_hi_hi_hi, mask_hi_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [31:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [4:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [4:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _T_1257 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1257; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1257; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [6:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:5]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [6:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 7'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [6:0] a_first_counter; // @[Edges.scala:229:27] wire [7:0] _a_first_counter1_T = {1'h0, a_first_counter} - 8'h1; // @[Edges.scala:229:27, :230:28] wire [6:0] a_first_counter1 = _a_first_counter1_T[6:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 7'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 7'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 7'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [6:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [6:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [6:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [4:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1330 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1330; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1330; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1330; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [6:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:5]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [6:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 7'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [6:0] d_first_counter; // @[Edges.scala:229:27] wire [7:0] _d_first_counter1_T = {1'h0, d_first_counter} - 8'h1; // @[Edges.scala:229:27, :230:28] wire [6:0] d_first_counter1 = _d_first_counter1_T[6:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 7'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 7'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 7'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [6:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [6:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [6:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [4:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [31:0] inflight; // @[Monitor.scala:614:27] reg [127:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [255:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [6:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:5]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [6:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 7'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [6:0] a_first_counter_1; // @[Edges.scala:229:27] wire [7:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 8'h1; // @[Edges.scala:229:27, :230:28] wire [6:0] a_first_counter1_1 = _a_first_counter1_T_1[6:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 7'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 7'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 7'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [6:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [6:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [6:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [6:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:5]; // @[package.scala:243:46] wire [6:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 7'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [6:0] d_first_counter_1; // @[Edges.scala:229:27] wire [7:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 8'h1; // @[Edges.scala:229:27, :230:28] wire [6:0] d_first_counter1_1 = _d_first_counter1_T_1[6:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 7'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 7'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 7'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [6:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [6:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [6:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [31:0] a_set; // @[Monitor.scala:626:34] wire [31:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [127:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [255:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [127:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [127:0] _a_opcode_lookup_T_6 = {124'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [127:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[127:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [7:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [255:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [255:0] _a_size_lookup_T_6 = {248'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [255:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[255:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [31:0] _GEN_3 = {27'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [31:0] _GEN_4 = 32'h1 << _GEN_3; // @[OneHot.scala:58:35] wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [31:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 32'h0; // @[OneHot.scala:58:35] wire _T_1183 = _T_1257 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1183 ? _a_set_T : 32'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1183 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1183 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [7:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1183 ? _a_opcodes_set_T_1[127:0] : 128'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [7:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [259:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1183 ? _a_sizes_set_T_1[255:0] : 256'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [31:0] d_clr; // @[Monitor.scala:664:34] wire [31:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [127:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [255:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_1229 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [31:0] _GEN_6 = {27'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [31:0] _GEN_7 = 32'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1229 & ~d_release_ack ? _d_clr_wo_ready_T : 32'h0; // @[OneHot.scala:58:35] wire _T_1198 = _T_1330 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1198 ? _d_clr_T : 32'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1198 ? _d_opcodes_clr_T_5[127:0] : 128'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [270:0] _d_sizes_clr_T_5 = 271'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1198 ? _d_sizes_clr_T_5[255:0] : 256'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [31:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [31:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [31:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [127:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [127:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [127:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [255:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [255:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [255:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [31:0] inflight_1; // @[Monitor.scala:726:35] wire [31:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [127:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [127:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [255:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [255:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [6:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:5]; // @[package.scala:243:46] wire [6:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 7'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [6:0] d_first_counter_2; // @[Edges.scala:229:27] wire [7:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 8'h1; // @[Edges.scala:229:27, :230:28] wire [6:0] d_first_counter1_2 = _d_first_counter1_T_2[6:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 7'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 7'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 7'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [6:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [6:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [6:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [127:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [127:0] _c_opcode_lookup_T_6 = {124'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [127:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[127:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [255:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [255:0] _c_size_lookup_T_6 = {248'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [255:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[255:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [31:0] d_clr_1; // @[Monitor.scala:774:34] wire [31:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [127:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [255:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1301 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1301 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 32'h0; // @[OneHot.scala:58:35] wire _T_1283 = _T_1330 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1283 ? _d_clr_T_1 : 32'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1283 ? _d_opcodes_clr_T_11[127:0] : 128'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [270:0] _d_sizes_clr_T_11 = 271'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1283 ? _d_sizes_clr_T_11[255:0] : 256'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113] wire [31:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [31:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [127:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [127:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [255:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [255:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module RenameBusyTable_1 : input clock : Clock input reset : Reset output io : { flip ren_uops : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}[2], busy_resps : { prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>}[2], flip rebusy_reqs : UInt<1>[2], flip wakeups : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<2>, rebusy : UInt<1>}}[2], flip child_rebusys : UInt<2>, debug : { busytable : UInt<64>}} wire wakeups_0 : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<2>, rebusy : UInt<1>}} reg wakeups_wu_valid_REG : UInt<1>, clock connect wakeups_wu_valid_REG, io.wakeups[0].valid reg wakeups_wu_valid_REG_1 : UInt, clock connect wakeups_wu_valid_REG_1, io.wakeups[0].bits.speculative_mask node _wakeups_wu_valid_T = and(wakeups_wu_valid_REG_1, io.child_rebusys) node _wakeups_wu_valid_T_1 = eq(_wakeups_wu_valid_T, UInt<1>(0h0)) node _wakeups_wu_valid_T_2 = and(wakeups_wu_valid_REG, _wakeups_wu_valid_T_1) connect wakeups_0.valid, _wakeups_wu_valid_T_2 reg wakeups_wu_bits_REG : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<2>, rebusy : UInt<1>}, clock connect wakeups_wu_bits_REG, io.wakeups[0].bits connect wakeups_0.bits, wakeups_wu_bits_REG wire wakeups_1 : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<2>, rebusy : UInt<1>}} reg wakeups_wu_valid_REG_2 : UInt<1>, clock connect wakeups_wu_valid_REG_2, io.wakeups[1].valid reg wakeups_wu_valid_REG_3 : UInt, clock connect wakeups_wu_valid_REG_3, io.wakeups[1].bits.speculative_mask node _wakeups_wu_valid_T_3 = and(wakeups_wu_valid_REG_3, io.child_rebusys) node _wakeups_wu_valid_T_4 = eq(_wakeups_wu_valid_T_3, UInt<1>(0h0)) node _wakeups_wu_valid_T_5 = and(wakeups_wu_valid_REG_2, _wakeups_wu_valid_T_4) connect wakeups_1.valid, _wakeups_wu_valid_T_5 reg wakeups_wu_bits_REG_1 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<2>, rebusy : UInt<1>}, clock connect wakeups_wu_bits_REG_1, io.wakeups[1].bits connect wakeups_1.bits, wakeups_wu_bits_REG_1 regreset busy_table : UInt<64>, clock, reset, UInt<64>(0h0) node _busy_table_wb_T = dshl(UInt<1>(0h1), wakeups_0.bits.uop.pdst) node _busy_table_wb_T_1 = eq(wakeups_0.bits.rebusy, UInt<1>(0h0)) node _busy_table_wb_T_2 = and(wakeups_0.valid, _busy_table_wb_T_1) node _busy_table_wb_T_3 = mux(_busy_table_wb_T_2, UInt<64>(0hffffffffffffffff), UInt<64>(0h0)) node _busy_table_wb_T_4 = and(_busy_table_wb_T, _busy_table_wb_T_3) node _busy_table_wb_T_5 = dshl(UInt<1>(0h1), wakeups_1.bits.uop.pdst) node _busy_table_wb_T_6 = eq(wakeups_1.bits.rebusy, UInt<1>(0h0)) node _busy_table_wb_T_7 = and(wakeups_1.valid, _busy_table_wb_T_6) node _busy_table_wb_T_8 = mux(_busy_table_wb_T_7, UInt<64>(0hffffffffffffffff), UInt<64>(0h0)) node _busy_table_wb_T_9 = and(_busy_table_wb_T_5, _busy_table_wb_T_8) node _busy_table_wb_T_10 = or(_busy_table_wb_T_4, _busy_table_wb_T_9) node _busy_table_wb_T_11 = not(_busy_table_wb_T_10) node busy_table_wb = and(busy_table, _busy_table_wb_T_11) node _busy_table_next_T = dshl(UInt<1>(0h1), io.ren_uops[0].pdst) node _busy_table_next_T_1 = mux(io.rebusy_reqs[0], UInt<64>(0hffffffffffffffff), UInt<64>(0h0)) node _busy_table_next_T_2 = and(_busy_table_next_T, _busy_table_next_T_1) node _busy_table_next_T_3 = dshl(UInt<1>(0h1), io.ren_uops[1].pdst) node _busy_table_next_T_4 = mux(io.rebusy_reqs[1], UInt<64>(0hffffffffffffffff), UInt<64>(0h0)) node _busy_table_next_T_5 = and(_busy_table_next_T_3, _busy_table_next_T_4) node _busy_table_next_T_6 = or(_busy_table_next_T_2, _busy_table_next_T_5) node _busy_table_next_T_7 = or(busy_table_wb, _busy_table_next_T_6) node _busy_table_next_T_8 = dshl(UInt<1>(0h1), wakeups_0.bits.uop.pdst) node _busy_table_next_T_9 = and(wakeups_0.valid, wakeups_0.bits.rebusy) node _busy_table_next_T_10 = mux(_busy_table_next_T_9, UInt<64>(0hffffffffffffffff), UInt<64>(0h0)) node _busy_table_next_T_11 = and(_busy_table_next_T_8, _busy_table_next_T_10) node _busy_table_next_T_12 = dshl(UInt<1>(0h1), wakeups_1.bits.uop.pdst) node _busy_table_next_T_13 = and(wakeups_1.valid, wakeups_1.bits.rebusy) node _busy_table_next_T_14 = mux(_busy_table_next_T_13, UInt<64>(0hffffffffffffffff), UInt<64>(0h0)) node _busy_table_next_T_15 = and(_busy_table_next_T_12, _busy_table_next_T_14) node _busy_table_next_T_16 = or(_busy_table_next_T_11, _busy_table_next_T_15) node busy_table_next = or(_busy_table_next_T_7, _busy_table_next_T_16) connect busy_table, busy_table_next node _prs1_match_T = eq(wakeups_0.bits.uop.pdst, io.ren_uops[0].prs1) node prs1_match_0 = and(wakeups_0.valid, _prs1_match_T) node _prs1_match_T_1 = eq(wakeups_1.bits.uop.pdst, io.ren_uops[0].prs1) node prs1_match_1 = and(wakeups_1.valid, _prs1_match_T_1) node _prs2_match_T = eq(wakeups_0.bits.uop.pdst, io.ren_uops[0].prs2) node prs2_match_0 = and(wakeups_0.valid, _prs2_match_T) node _prs2_match_T_1 = eq(wakeups_1.bits.uop.pdst, io.ren_uops[0].prs2) node prs2_match_1 = and(wakeups_1.valid, _prs2_match_T_1) node _prs3_match_T = eq(wakeups_0.bits.uop.pdst, io.ren_uops[0].prs3) node prs3_match_0 = and(wakeups_0.valid, _prs3_match_T) node _prs3_match_T_1 = eq(wakeups_1.bits.uop.pdst, io.ren_uops[0].prs3) node prs3_match_1 = and(wakeups_1.valid, _prs3_match_T_1) node _io_busy_resps_0_prs1_busy_T = dshr(busy_table, io.ren_uops[0].prs1) node _io_busy_resps_0_prs1_busy_T_1 = bits(_io_busy_resps_0_prs1_busy_T, 0, 0) connect io.busy_resps[0].prs1_busy, _io_busy_resps_0_prs1_busy_T_1 node _io_busy_resps_0_prs2_busy_T = dshr(busy_table, io.ren_uops[0].prs2) node _io_busy_resps_0_prs2_busy_T_1 = bits(_io_busy_resps_0_prs2_busy_T, 0, 0) connect io.busy_resps[0].prs2_busy, _io_busy_resps_0_prs2_busy_T_1 node _io_busy_resps_0_prs3_busy_T = dshr(busy_table, io.ren_uops[0].prs3) node _io_busy_resps_0_prs3_busy_T_1 = bits(_io_busy_resps_0_prs3_busy_T, 0, 0) connect io.busy_resps[0].prs3_busy, _io_busy_resps_0_prs3_busy_T_1 node _T = or(prs1_match_0, prs1_match_1) when _T : node _io_busy_resps_0_prs1_busy_T_2 = and(wakeups_0.valid, wakeups_0.bits.rebusy) node _io_busy_resps_0_prs1_busy_T_3 = and(wakeups_1.valid, wakeups_1.bits.rebusy) node _io_busy_resps_0_prs1_busy_T_4 = mux(prs1_match_0, _io_busy_resps_0_prs1_busy_T_2, UInt<1>(0h0)) node _io_busy_resps_0_prs1_busy_T_5 = mux(prs1_match_1, _io_busy_resps_0_prs1_busy_T_3, UInt<1>(0h0)) node _io_busy_resps_0_prs1_busy_T_6 = or(_io_busy_resps_0_prs1_busy_T_4, _io_busy_resps_0_prs1_busy_T_5) wire _io_busy_resps_0_prs1_busy_WIRE : UInt<1> connect _io_busy_resps_0_prs1_busy_WIRE, _io_busy_resps_0_prs1_busy_T_6 connect io.busy_resps[0].prs1_busy, _io_busy_resps_0_prs1_busy_WIRE node _T_1 = or(prs2_match_0, prs2_match_1) when _T_1 : node _io_busy_resps_0_prs2_busy_T_2 = and(wakeups_0.valid, wakeups_0.bits.rebusy) node _io_busy_resps_0_prs2_busy_T_3 = and(wakeups_1.valid, wakeups_1.bits.rebusy) node _io_busy_resps_0_prs2_busy_T_4 = mux(prs2_match_0, _io_busy_resps_0_prs2_busy_T_2, UInt<1>(0h0)) node _io_busy_resps_0_prs2_busy_T_5 = mux(prs2_match_1, _io_busy_resps_0_prs2_busy_T_3, UInt<1>(0h0)) node _io_busy_resps_0_prs2_busy_T_6 = or(_io_busy_resps_0_prs2_busy_T_4, _io_busy_resps_0_prs2_busy_T_5) wire _io_busy_resps_0_prs2_busy_WIRE : UInt<1> connect _io_busy_resps_0_prs2_busy_WIRE, _io_busy_resps_0_prs2_busy_T_6 connect io.busy_resps[0].prs2_busy, _io_busy_resps_0_prs2_busy_WIRE node _T_2 = or(prs3_match_0, prs3_match_1) when _T_2 : node _io_busy_resps_0_prs3_busy_T_2 = and(wakeups_0.valid, wakeups_0.bits.rebusy) node _io_busy_resps_0_prs3_busy_T_3 = and(wakeups_1.valid, wakeups_1.bits.rebusy) node _io_busy_resps_0_prs3_busy_T_4 = mux(prs3_match_0, _io_busy_resps_0_prs3_busy_T_2, UInt<1>(0h0)) node _io_busy_resps_0_prs3_busy_T_5 = mux(prs3_match_1, _io_busy_resps_0_prs3_busy_T_3, UInt<1>(0h0)) node _io_busy_resps_0_prs3_busy_T_6 = or(_io_busy_resps_0_prs3_busy_T_4, _io_busy_resps_0_prs3_busy_T_5) wire _io_busy_resps_0_prs3_busy_WIRE : UInt<1> connect _io_busy_resps_0_prs3_busy_WIRE, _io_busy_resps_0_prs3_busy_T_6 connect io.busy_resps[0].prs3_busy, _io_busy_resps_0_prs3_busy_WIRE node _prs1_match_T_2 = eq(wakeups_0.bits.uop.pdst, io.ren_uops[1].prs1) node prs1_match_0_1 = and(wakeups_0.valid, _prs1_match_T_2) node _prs1_match_T_3 = eq(wakeups_1.bits.uop.pdst, io.ren_uops[1].prs1) node prs1_match_1_1 = and(wakeups_1.valid, _prs1_match_T_3) node _prs2_match_T_2 = eq(wakeups_0.bits.uop.pdst, io.ren_uops[1].prs2) node prs2_match_0_1 = and(wakeups_0.valid, _prs2_match_T_2) node _prs2_match_T_3 = eq(wakeups_1.bits.uop.pdst, io.ren_uops[1].prs2) node prs2_match_1_1 = and(wakeups_1.valid, _prs2_match_T_3) node _prs3_match_T_2 = eq(wakeups_0.bits.uop.pdst, io.ren_uops[1].prs3) node prs3_match_0_1 = and(wakeups_0.valid, _prs3_match_T_2) node _prs3_match_T_3 = eq(wakeups_1.bits.uop.pdst, io.ren_uops[1].prs3) node prs3_match_1_1 = and(wakeups_1.valid, _prs3_match_T_3) node _io_busy_resps_1_prs1_busy_T = dshr(busy_table, io.ren_uops[1].prs1) node _io_busy_resps_1_prs1_busy_T_1 = bits(_io_busy_resps_1_prs1_busy_T, 0, 0) connect io.busy_resps[1].prs1_busy, _io_busy_resps_1_prs1_busy_T_1 node _io_busy_resps_1_prs2_busy_T = dshr(busy_table, io.ren_uops[1].prs2) node _io_busy_resps_1_prs2_busy_T_1 = bits(_io_busy_resps_1_prs2_busy_T, 0, 0) connect io.busy_resps[1].prs2_busy, _io_busy_resps_1_prs2_busy_T_1 node _io_busy_resps_1_prs3_busy_T = dshr(busy_table, io.ren_uops[1].prs3) node _io_busy_resps_1_prs3_busy_T_1 = bits(_io_busy_resps_1_prs3_busy_T, 0, 0) connect io.busy_resps[1].prs3_busy, _io_busy_resps_1_prs3_busy_T_1 node _T_3 = or(prs1_match_0_1, prs1_match_1_1) when _T_3 : node _io_busy_resps_1_prs1_busy_T_2 = and(wakeups_0.valid, wakeups_0.bits.rebusy) node _io_busy_resps_1_prs1_busy_T_3 = and(wakeups_1.valid, wakeups_1.bits.rebusy) node _io_busy_resps_1_prs1_busy_T_4 = mux(prs1_match_0_1, _io_busy_resps_1_prs1_busy_T_2, UInt<1>(0h0)) node _io_busy_resps_1_prs1_busy_T_5 = mux(prs1_match_1_1, _io_busy_resps_1_prs1_busy_T_3, UInt<1>(0h0)) node _io_busy_resps_1_prs1_busy_T_6 = or(_io_busy_resps_1_prs1_busy_T_4, _io_busy_resps_1_prs1_busy_T_5) wire _io_busy_resps_1_prs1_busy_WIRE : UInt<1> connect _io_busy_resps_1_prs1_busy_WIRE, _io_busy_resps_1_prs1_busy_T_6 connect io.busy_resps[1].prs1_busy, _io_busy_resps_1_prs1_busy_WIRE node _T_4 = or(prs2_match_0_1, prs2_match_1_1) when _T_4 : node _io_busy_resps_1_prs2_busy_T_2 = and(wakeups_0.valid, wakeups_0.bits.rebusy) node _io_busy_resps_1_prs2_busy_T_3 = and(wakeups_1.valid, wakeups_1.bits.rebusy) node _io_busy_resps_1_prs2_busy_T_4 = mux(prs2_match_0_1, _io_busy_resps_1_prs2_busy_T_2, UInt<1>(0h0)) node _io_busy_resps_1_prs2_busy_T_5 = mux(prs2_match_1_1, _io_busy_resps_1_prs2_busy_T_3, UInt<1>(0h0)) node _io_busy_resps_1_prs2_busy_T_6 = or(_io_busy_resps_1_prs2_busy_T_4, _io_busy_resps_1_prs2_busy_T_5) wire _io_busy_resps_1_prs2_busy_WIRE : UInt<1> connect _io_busy_resps_1_prs2_busy_WIRE, _io_busy_resps_1_prs2_busy_T_6 connect io.busy_resps[1].prs2_busy, _io_busy_resps_1_prs2_busy_WIRE node _T_5 = or(prs3_match_0_1, prs3_match_1_1) when _T_5 : node _io_busy_resps_1_prs3_busy_T_2 = and(wakeups_0.valid, wakeups_0.bits.rebusy) node _io_busy_resps_1_prs3_busy_T_3 = and(wakeups_1.valid, wakeups_1.bits.rebusy) node _io_busy_resps_1_prs3_busy_T_4 = mux(prs3_match_0_1, _io_busy_resps_1_prs3_busy_T_2, UInt<1>(0h0)) node _io_busy_resps_1_prs3_busy_T_5 = mux(prs3_match_1_1, _io_busy_resps_1_prs3_busy_T_3, UInt<1>(0h0)) node _io_busy_resps_1_prs3_busy_T_6 = or(_io_busy_resps_1_prs3_busy_T_4, _io_busy_resps_1_prs3_busy_T_5) wire _io_busy_resps_1_prs3_busy_WIRE : UInt<1> connect _io_busy_resps_1_prs3_busy_WIRE, _io_busy_resps_1_prs3_busy_T_6 connect io.busy_resps[1].prs3_busy, _io_busy_resps_1_prs3_busy_WIRE connect io.debug.busytable, busy_table
module RenameBusyTable_1( // @[rename-busytable.scala:27:7] input clock, // @[rename-busytable.scala:27:7] input reset, // @[rename-busytable.scala:27:7] input [31:0] io_ren_uops_0_inst, // @[rename-busytable.scala:36:14] input [31:0] io_ren_uops_0_debug_inst, // @[rename-busytable.scala:36:14] input io_ren_uops_0_is_rvc, // @[rename-busytable.scala:36:14] input [39:0] io_ren_uops_0_debug_pc, // @[rename-busytable.scala:36:14] input io_ren_uops_0_iq_type_0, // @[rename-busytable.scala:36:14] input io_ren_uops_0_iq_type_1, // @[rename-busytable.scala:36:14] input io_ren_uops_0_iq_type_2, // @[rename-busytable.scala:36:14] input io_ren_uops_0_iq_type_3, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fu_code_0, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fu_code_1, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fu_code_2, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fu_code_3, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fu_code_4, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fu_code_5, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fu_code_6, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fu_code_7, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fu_code_8, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fu_code_9, // @[rename-busytable.scala:36:14] input io_ren_uops_0_iw_issued, // @[rename-busytable.scala:36:14] input io_ren_uops_0_iw_issued_partial_agen, // @[rename-busytable.scala:36:14] input io_ren_uops_0_iw_issued_partial_dgen, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_0_iw_p1_speculative_child, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_0_iw_p2_speculative_child, // @[rename-busytable.scala:36:14] input io_ren_uops_0_iw_p1_bypass_hint, // @[rename-busytable.scala:36:14] input io_ren_uops_0_iw_p2_bypass_hint, // @[rename-busytable.scala:36:14] input io_ren_uops_0_iw_p3_bypass_hint, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_0_dis_col_sel, // @[rename-busytable.scala:36:14] input [11:0] io_ren_uops_0_br_mask, // @[rename-busytable.scala:36:14] input [3:0] io_ren_uops_0_br_tag, // @[rename-busytable.scala:36:14] input [3:0] io_ren_uops_0_br_type, // @[rename-busytable.scala:36:14] input io_ren_uops_0_is_sfb, // @[rename-busytable.scala:36:14] input io_ren_uops_0_is_fence, // @[rename-busytable.scala:36:14] input io_ren_uops_0_is_fencei, // @[rename-busytable.scala:36:14] input io_ren_uops_0_is_sfence, // @[rename-busytable.scala:36:14] input io_ren_uops_0_is_amo, // @[rename-busytable.scala:36:14] input io_ren_uops_0_is_eret, // @[rename-busytable.scala:36:14] input io_ren_uops_0_is_sys_pc2epc, // @[rename-busytable.scala:36:14] input io_ren_uops_0_is_rocc, // @[rename-busytable.scala:36:14] input io_ren_uops_0_is_mov, // @[rename-busytable.scala:36:14] input [4:0] io_ren_uops_0_ftq_idx, // @[rename-busytable.scala:36:14] input io_ren_uops_0_edge_inst, // @[rename-busytable.scala:36:14] input [5:0] io_ren_uops_0_pc_lob, // @[rename-busytable.scala:36:14] input io_ren_uops_0_taken, // @[rename-busytable.scala:36:14] input io_ren_uops_0_imm_rename, // @[rename-busytable.scala:36:14] input [2:0] io_ren_uops_0_imm_sel, // @[rename-busytable.scala:36:14] input [4:0] io_ren_uops_0_pimm, // @[rename-busytable.scala:36:14] input [19:0] io_ren_uops_0_imm_packed, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_0_op1_sel, // @[rename-busytable.scala:36:14] input [2:0] io_ren_uops_0_op2_sel, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fp_ctrl_ldst, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fp_ctrl_wen, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fp_ctrl_ren1, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fp_ctrl_ren2, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fp_ctrl_ren3, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fp_ctrl_swap12, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fp_ctrl_swap23, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_0_fp_ctrl_typeTagIn, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_0_fp_ctrl_typeTagOut, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fp_ctrl_fromint, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fp_ctrl_toint, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fp_ctrl_fastpipe, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fp_ctrl_fma, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fp_ctrl_div, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fp_ctrl_sqrt, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fp_ctrl_wflags, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fp_ctrl_vec, // @[rename-busytable.scala:36:14] input [5:0] io_ren_uops_0_rob_idx, // @[rename-busytable.scala:36:14] input [3:0] io_ren_uops_0_ldq_idx, // @[rename-busytable.scala:36:14] input [3:0] io_ren_uops_0_stq_idx, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_0_rxq_idx, // @[rename-busytable.scala:36:14] input [6:0] io_ren_uops_0_pdst, // @[rename-busytable.scala:36:14] input [6:0] io_ren_uops_0_prs1, // @[rename-busytable.scala:36:14] input [6:0] io_ren_uops_0_prs2, // @[rename-busytable.scala:36:14] input [6:0] io_ren_uops_0_prs3, // @[rename-busytable.scala:36:14] input [4:0] io_ren_uops_0_ppred, // @[rename-busytable.scala:36:14] input io_ren_uops_0_prs1_busy, // @[rename-busytable.scala:36:14] input io_ren_uops_0_prs2_busy, // @[rename-busytable.scala:36:14] input io_ren_uops_0_prs3_busy, // @[rename-busytable.scala:36:14] input io_ren_uops_0_ppred_busy, // @[rename-busytable.scala:36:14] input [6:0] io_ren_uops_0_stale_pdst, // @[rename-busytable.scala:36:14] input io_ren_uops_0_exception, // @[rename-busytable.scala:36:14] input [63:0] io_ren_uops_0_exc_cause, // @[rename-busytable.scala:36:14] input [4:0] io_ren_uops_0_mem_cmd, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_0_mem_size, // @[rename-busytable.scala:36:14] input io_ren_uops_0_mem_signed, // @[rename-busytable.scala:36:14] input io_ren_uops_0_uses_ldq, // @[rename-busytable.scala:36:14] input io_ren_uops_0_uses_stq, // @[rename-busytable.scala:36:14] input io_ren_uops_0_is_unique, // @[rename-busytable.scala:36:14] input io_ren_uops_0_flush_on_commit, // @[rename-busytable.scala:36:14] input [2:0] io_ren_uops_0_csr_cmd, // @[rename-busytable.scala:36:14] input io_ren_uops_0_ldst_is_rs1, // @[rename-busytable.scala:36:14] input [5:0] io_ren_uops_0_ldst, // @[rename-busytable.scala:36:14] input [5:0] io_ren_uops_0_lrs1, // @[rename-busytable.scala:36:14] input [5:0] io_ren_uops_0_lrs2, // @[rename-busytable.scala:36:14] input [5:0] io_ren_uops_0_lrs3, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_0_dst_rtype, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_0_lrs1_rtype, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_0_lrs2_rtype, // @[rename-busytable.scala:36:14] input io_ren_uops_0_frs3_en, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fcn_dw, // @[rename-busytable.scala:36:14] input [4:0] io_ren_uops_0_fcn_op, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fp_val, // @[rename-busytable.scala:36:14] input [2:0] io_ren_uops_0_fp_rm, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_0_fp_typ, // @[rename-busytable.scala:36:14] input io_ren_uops_0_xcpt_pf_if, // @[rename-busytable.scala:36:14] input io_ren_uops_0_xcpt_ae_if, // @[rename-busytable.scala:36:14] input io_ren_uops_0_xcpt_ma_if, // @[rename-busytable.scala:36:14] input io_ren_uops_0_bp_debug_if, // @[rename-busytable.scala:36:14] input io_ren_uops_0_bp_xcpt_if, // @[rename-busytable.scala:36:14] input [2:0] io_ren_uops_0_debug_fsrc, // @[rename-busytable.scala:36:14] input [2:0] io_ren_uops_0_debug_tsrc, // @[rename-busytable.scala:36:14] input [31:0] io_ren_uops_1_inst, // @[rename-busytable.scala:36:14] input [31:0] io_ren_uops_1_debug_inst, // @[rename-busytable.scala:36:14] input io_ren_uops_1_is_rvc, // @[rename-busytable.scala:36:14] input [39:0] io_ren_uops_1_debug_pc, // @[rename-busytable.scala:36:14] input io_ren_uops_1_iq_type_0, // @[rename-busytable.scala:36:14] input io_ren_uops_1_iq_type_1, // @[rename-busytable.scala:36:14] input io_ren_uops_1_iq_type_2, // @[rename-busytable.scala:36:14] input io_ren_uops_1_iq_type_3, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fu_code_0, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fu_code_1, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fu_code_2, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fu_code_3, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fu_code_4, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fu_code_5, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fu_code_6, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fu_code_7, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fu_code_8, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fu_code_9, // @[rename-busytable.scala:36:14] input io_ren_uops_1_iw_issued, // @[rename-busytable.scala:36:14] input io_ren_uops_1_iw_issued_partial_agen, // @[rename-busytable.scala:36:14] input io_ren_uops_1_iw_issued_partial_dgen, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_1_iw_p1_speculative_child, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_1_iw_p2_speculative_child, // @[rename-busytable.scala:36:14] input io_ren_uops_1_iw_p1_bypass_hint, // @[rename-busytable.scala:36:14] input io_ren_uops_1_iw_p2_bypass_hint, // @[rename-busytable.scala:36:14] input io_ren_uops_1_iw_p3_bypass_hint, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_1_dis_col_sel, // @[rename-busytable.scala:36:14] input [11:0] io_ren_uops_1_br_mask, // @[rename-busytable.scala:36:14] input [3:0] io_ren_uops_1_br_tag, // @[rename-busytable.scala:36:14] input [3:0] io_ren_uops_1_br_type, // @[rename-busytable.scala:36:14] input io_ren_uops_1_is_sfb, // @[rename-busytable.scala:36:14] input io_ren_uops_1_is_fence, // @[rename-busytable.scala:36:14] input io_ren_uops_1_is_fencei, // @[rename-busytable.scala:36:14] input io_ren_uops_1_is_sfence, // @[rename-busytable.scala:36:14] input io_ren_uops_1_is_amo, // @[rename-busytable.scala:36:14] input io_ren_uops_1_is_eret, // @[rename-busytable.scala:36:14] input io_ren_uops_1_is_sys_pc2epc, // @[rename-busytable.scala:36:14] input io_ren_uops_1_is_rocc, // @[rename-busytable.scala:36:14] input io_ren_uops_1_is_mov, // @[rename-busytable.scala:36:14] input [4:0] io_ren_uops_1_ftq_idx, // @[rename-busytable.scala:36:14] input io_ren_uops_1_edge_inst, // @[rename-busytable.scala:36:14] input [5:0] io_ren_uops_1_pc_lob, // @[rename-busytable.scala:36:14] input io_ren_uops_1_taken, // @[rename-busytable.scala:36:14] input io_ren_uops_1_imm_rename, // @[rename-busytable.scala:36:14] input [2:0] io_ren_uops_1_imm_sel, // @[rename-busytable.scala:36:14] input [4:0] io_ren_uops_1_pimm, // @[rename-busytable.scala:36:14] input [19:0] io_ren_uops_1_imm_packed, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_1_op1_sel, // @[rename-busytable.scala:36:14] input [2:0] io_ren_uops_1_op2_sel, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fp_ctrl_ldst, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fp_ctrl_wen, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fp_ctrl_ren1, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fp_ctrl_ren2, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fp_ctrl_ren3, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fp_ctrl_swap12, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fp_ctrl_swap23, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_1_fp_ctrl_typeTagIn, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_1_fp_ctrl_typeTagOut, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fp_ctrl_fromint, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fp_ctrl_toint, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fp_ctrl_fastpipe, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fp_ctrl_fma, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fp_ctrl_div, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fp_ctrl_sqrt, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fp_ctrl_wflags, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fp_ctrl_vec, // @[rename-busytable.scala:36:14] input [5:0] io_ren_uops_1_rob_idx, // @[rename-busytable.scala:36:14] input [3:0] io_ren_uops_1_ldq_idx, // @[rename-busytable.scala:36:14] input [3:0] io_ren_uops_1_stq_idx, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_1_rxq_idx, // @[rename-busytable.scala:36:14] input [6:0] io_ren_uops_1_pdst, // @[rename-busytable.scala:36:14] input [6:0] io_ren_uops_1_prs1, // @[rename-busytable.scala:36:14] input [6:0] io_ren_uops_1_prs2, // @[rename-busytable.scala:36:14] input [6:0] io_ren_uops_1_prs3, // @[rename-busytable.scala:36:14] input [4:0] io_ren_uops_1_ppred, // @[rename-busytable.scala:36:14] input io_ren_uops_1_prs1_busy, // @[rename-busytable.scala:36:14] input io_ren_uops_1_prs2_busy, // @[rename-busytable.scala:36:14] input io_ren_uops_1_prs3_busy, // @[rename-busytable.scala:36:14] input io_ren_uops_1_ppred_busy, // @[rename-busytable.scala:36:14] input [6:0] io_ren_uops_1_stale_pdst, // @[rename-busytable.scala:36:14] input io_ren_uops_1_exception, // @[rename-busytable.scala:36:14] input [63:0] io_ren_uops_1_exc_cause, // @[rename-busytable.scala:36:14] input [4:0] io_ren_uops_1_mem_cmd, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_1_mem_size, // @[rename-busytable.scala:36:14] input io_ren_uops_1_mem_signed, // @[rename-busytable.scala:36:14] input io_ren_uops_1_uses_ldq, // @[rename-busytable.scala:36:14] input io_ren_uops_1_uses_stq, // @[rename-busytable.scala:36:14] input io_ren_uops_1_is_unique, // @[rename-busytable.scala:36:14] input io_ren_uops_1_flush_on_commit, // @[rename-busytable.scala:36:14] input [2:0] io_ren_uops_1_csr_cmd, // @[rename-busytable.scala:36:14] input io_ren_uops_1_ldst_is_rs1, // @[rename-busytable.scala:36:14] input [5:0] io_ren_uops_1_ldst, // @[rename-busytable.scala:36:14] input [5:0] io_ren_uops_1_lrs1, // @[rename-busytable.scala:36:14] input [5:0] io_ren_uops_1_lrs2, // @[rename-busytable.scala:36:14] input [5:0] io_ren_uops_1_lrs3, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_1_dst_rtype, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_1_lrs1_rtype, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_1_lrs2_rtype, // @[rename-busytable.scala:36:14] input io_ren_uops_1_frs3_en, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fcn_dw, // @[rename-busytable.scala:36:14] input [4:0] io_ren_uops_1_fcn_op, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fp_val, // @[rename-busytable.scala:36:14] input [2:0] io_ren_uops_1_fp_rm, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_1_fp_typ, // @[rename-busytable.scala:36:14] input io_ren_uops_1_xcpt_pf_if, // @[rename-busytable.scala:36:14] input io_ren_uops_1_xcpt_ae_if, // @[rename-busytable.scala:36:14] input io_ren_uops_1_xcpt_ma_if, // @[rename-busytable.scala:36:14] input io_ren_uops_1_bp_debug_if, // @[rename-busytable.scala:36:14] input io_ren_uops_1_bp_xcpt_if, // @[rename-busytable.scala:36:14] input [2:0] io_ren_uops_1_debug_fsrc, // @[rename-busytable.scala:36:14] input [2:0] io_ren_uops_1_debug_tsrc, // @[rename-busytable.scala:36:14] output io_busy_resps_0_prs1_busy, // @[rename-busytable.scala:36:14] output io_busy_resps_0_prs2_busy, // @[rename-busytable.scala:36:14] output io_busy_resps_0_prs3_busy, // @[rename-busytable.scala:36:14] output io_busy_resps_1_prs1_busy, // @[rename-busytable.scala:36:14] output io_busy_resps_1_prs2_busy, // @[rename-busytable.scala:36:14] output io_busy_resps_1_prs3_busy, // @[rename-busytable.scala:36:14] input io_rebusy_reqs_0, // @[rename-busytable.scala:36:14] input io_rebusy_reqs_1, // @[rename-busytable.scala:36:14] input io_wakeups_0_valid, // @[rename-busytable.scala:36:14] input [31:0] io_wakeups_0_bits_uop_inst, // @[rename-busytable.scala:36:14] input [31:0] io_wakeups_0_bits_uop_debug_inst, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_is_rvc, // @[rename-busytable.scala:36:14] input [39:0] io_wakeups_0_bits_uop_debug_pc, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_iq_type_0, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_iq_type_1, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_iq_type_2, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_iq_type_3, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fu_code_0, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fu_code_1, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fu_code_2, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fu_code_3, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fu_code_4, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fu_code_5, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fu_code_6, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fu_code_7, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fu_code_8, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fu_code_9, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_iw_issued, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_iw_issued_partial_agen, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_iw_issued_partial_dgen, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_0_bits_uop_iw_p1_speculative_child, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_0_bits_uop_iw_p2_speculative_child, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_iw_p1_bypass_hint, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_iw_p2_bypass_hint, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_iw_p3_bypass_hint, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_0_bits_uop_dis_col_sel, // @[rename-busytable.scala:36:14] input [11:0] io_wakeups_0_bits_uop_br_mask, // @[rename-busytable.scala:36:14] input [3:0] io_wakeups_0_bits_uop_br_tag, // @[rename-busytable.scala:36:14] input [3:0] io_wakeups_0_bits_uop_br_type, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_is_sfb, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_is_fence, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_is_fencei, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_is_sfence, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_is_amo, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_is_eret, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_is_sys_pc2epc, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_is_rocc, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_is_mov, // @[rename-busytable.scala:36:14] input [4:0] io_wakeups_0_bits_uop_ftq_idx, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_edge_inst, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_0_bits_uop_pc_lob, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_taken, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_imm_rename, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_0_bits_uop_imm_sel, // @[rename-busytable.scala:36:14] input [4:0] io_wakeups_0_bits_uop_pimm, // @[rename-busytable.scala:36:14] input [19:0] io_wakeups_0_bits_uop_imm_packed, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_0_bits_uop_op1_sel, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_0_bits_uop_op2_sel, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fp_ctrl_ldst, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fp_ctrl_wen, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fp_ctrl_ren1, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fp_ctrl_ren2, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fp_ctrl_ren3, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fp_ctrl_swap12, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fp_ctrl_swap23, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_0_bits_uop_fp_ctrl_typeTagIn, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_0_bits_uop_fp_ctrl_typeTagOut, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fp_ctrl_fromint, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fp_ctrl_toint, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fp_ctrl_fastpipe, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fp_ctrl_fma, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fp_ctrl_div, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fp_ctrl_sqrt, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fp_ctrl_wflags, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fp_ctrl_vec, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_0_bits_uop_rob_idx, // @[rename-busytable.scala:36:14] input [3:0] io_wakeups_0_bits_uop_ldq_idx, // @[rename-busytable.scala:36:14] input [3:0] io_wakeups_0_bits_uop_stq_idx, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_0_bits_uop_rxq_idx, // @[rename-busytable.scala:36:14] input [6:0] io_wakeups_0_bits_uop_pdst, // @[rename-busytable.scala:36:14] input [6:0] io_wakeups_0_bits_uop_prs1, // @[rename-busytable.scala:36:14] input [6:0] io_wakeups_0_bits_uop_prs2, // @[rename-busytable.scala:36:14] input [6:0] io_wakeups_0_bits_uop_prs3, // @[rename-busytable.scala:36:14] input [4:0] io_wakeups_0_bits_uop_ppred, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_prs1_busy, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_prs2_busy, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_prs3_busy, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_ppred_busy, // @[rename-busytable.scala:36:14] input [6:0] io_wakeups_0_bits_uop_stale_pdst, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_exception, // @[rename-busytable.scala:36:14] input [63:0] io_wakeups_0_bits_uop_exc_cause, // @[rename-busytable.scala:36:14] input [4:0] io_wakeups_0_bits_uop_mem_cmd, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_0_bits_uop_mem_size, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_mem_signed, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_uses_ldq, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_uses_stq, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_is_unique, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_flush_on_commit, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_0_bits_uop_csr_cmd, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_ldst_is_rs1, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_0_bits_uop_ldst, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_0_bits_uop_lrs1, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_0_bits_uop_lrs2, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_0_bits_uop_lrs3, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_0_bits_uop_dst_rtype, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_0_bits_uop_lrs1_rtype, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_0_bits_uop_lrs2_rtype, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_frs3_en, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fcn_dw, // @[rename-busytable.scala:36:14] input [4:0] io_wakeups_0_bits_uop_fcn_op, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fp_val, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_0_bits_uop_fp_rm, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_0_bits_uop_fp_typ, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_xcpt_pf_if, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_xcpt_ae_if, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_xcpt_ma_if, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_bp_debug_if, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_bp_xcpt_if, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_0_bits_uop_debug_fsrc, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_0_bits_uop_debug_tsrc, // @[rename-busytable.scala:36:14] input io_wakeups_1_valid, // @[rename-busytable.scala:36:14] input [31:0] io_wakeups_1_bits_uop_inst, // @[rename-busytable.scala:36:14] input [31:0] io_wakeups_1_bits_uop_debug_inst, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_is_rvc, // @[rename-busytable.scala:36:14] input [39:0] io_wakeups_1_bits_uop_debug_pc, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_iq_type_0, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_iq_type_1, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_iq_type_2, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_iq_type_3, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fu_code_0, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fu_code_1, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fu_code_2, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fu_code_3, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fu_code_4, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fu_code_5, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fu_code_6, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fu_code_7, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fu_code_8, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fu_code_9, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_iw_issued, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_iw_issued_partial_agen, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_iw_issued_partial_dgen, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_1_bits_uop_iw_p1_speculative_child, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_1_bits_uop_iw_p2_speculative_child, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_iw_p1_bypass_hint, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_iw_p2_bypass_hint, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_iw_p3_bypass_hint, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_1_bits_uop_dis_col_sel, // @[rename-busytable.scala:36:14] input [11:0] io_wakeups_1_bits_uop_br_mask, // @[rename-busytable.scala:36:14] input [3:0] io_wakeups_1_bits_uop_br_tag, // @[rename-busytable.scala:36:14] input [3:0] io_wakeups_1_bits_uop_br_type, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_is_sfb, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_is_fence, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_is_fencei, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_is_sfence, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_is_amo, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_is_eret, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_is_sys_pc2epc, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_is_rocc, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_is_mov, // @[rename-busytable.scala:36:14] input [4:0] io_wakeups_1_bits_uop_ftq_idx, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_edge_inst, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_1_bits_uop_pc_lob, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_taken, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_imm_rename, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_1_bits_uop_imm_sel, // @[rename-busytable.scala:36:14] input [4:0] io_wakeups_1_bits_uop_pimm, // @[rename-busytable.scala:36:14] input [19:0] io_wakeups_1_bits_uop_imm_packed, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_1_bits_uop_op1_sel, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_1_bits_uop_op2_sel, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fp_ctrl_ldst, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fp_ctrl_wen, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fp_ctrl_ren1, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fp_ctrl_ren2, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fp_ctrl_ren3, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fp_ctrl_swap12, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fp_ctrl_swap23, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_1_bits_uop_fp_ctrl_typeTagIn, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_1_bits_uop_fp_ctrl_typeTagOut, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fp_ctrl_fromint, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fp_ctrl_toint, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fp_ctrl_fastpipe, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fp_ctrl_fma, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fp_ctrl_div, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fp_ctrl_sqrt, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fp_ctrl_wflags, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fp_ctrl_vec, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_1_bits_uop_rob_idx, // @[rename-busytable.scala:36:14] input [3:0] io_wakeups_1_bits_uop_ldq_idx, // @[rename-busytable.scala:36:14] input [3:0] io_wakeups_1_bits_uop_stq_idx, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_1_bits_uop_rxq_idx, // @[rename-busytable.scala:36:14] input [6:0] io_wakeups_1_bits_uop_pdst, // @[rename-busytable.scala:36:14] input [6:0] io_wakeups_1_bits_uop_prs1, // @[rename-busytable.scala:36:14] input [6:0] io_wakeups_1_bits_uop_prs2, // @[rename-busytable.scala:36:14] input [6:0] io_wakeups_1_bits_uop_prs3, // @[rename-busytable.scala:36:14] input [4:0] io_wakeups_1_bits_uop_ppred, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_prs1_busy, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_prs2_busy, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_prs3_busy, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_ppred_busy, // @[rename-busytable.scala:36:14] input [6:0] io_wakeups_1_bits_uop_stale_pdst, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_exception, // @[rename-busytable.scala:36:14] input [63:0] io_wakeups_1_bits_uop_exc_cause, // @[rename-busytable.scala:36:14] input [4:0] io_wakeups_1_bits_uop_mem_cmd, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_1_bits_uop_mem_size, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_mem_signed, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_uses_ldq, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_uses_stq, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_is_unique, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_flush_on_commit, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_1_bits_uop_csr_cmd, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_ldst_is_rs1, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_1_bits_uop_ldst, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_1_bits_uop_lrs1, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_1_bits_uop_lrs2, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_1_bits_uop_lrs3, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_1_bits_uop_dst_rtype, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_1_bits_uop_lrs1_rtype, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_1_bits_uop_lrs2_rtype, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_frs3_en, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fcn_dw, // @[rename-busytable.scala:36:14] input [4:0] io_wakeups_1_bits_uop_fcn_op, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fp_val, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_1_bits_uop_fp_rm, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_1_bits_uop_fp_typ, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_xcpt_pf_if, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_xcpt_ae_if, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_xcpt_ma_if, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_bp_debug_if, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_bp_xcpt_if, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_1_bits_uop_debug_fsrc, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_1_bits_uop_debug_tsrc // @[rename-busytable.scala:36:14] ); wire wakeups_1_valid; // @[rename-busytable.scala:47:18] wire [31:0] io_ren_uops_0_inst_0 = io_ren_uops_0_inst; // @[rename-busytable.scala:27:7] wire [31:0] io_ren_uops_0_debug_inst_0 = io_ren_uops_0_debug_inst; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_is_rvc_0 = io_ren_uops_0_is_rvc; // @[rename-busytable.scala:27:7] wire [39:0] io_ren_uops_0_debug_pc_0 = io_ren_uops_0_debug_pc; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_iq_type_0_0 = io_ren_uops_0_iq_type_0; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_iq_type_1_0 = io_ren_uops_0_iq_type_1; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_iq_type_2_0 = io_ren_uops_0_iq_type_2; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_iq_type_3_0 = io_ren_uops_0_iq_type_3; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fu_code_0_0 = io_ren_uops_0_fu_code_0; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fu_code_1_0 = io_ren_uops_0_fu_code_1; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fu_code_2_0 = io_ren_uops_0_fu_code_2; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fu_code_3_0 = io_ren_uops_0_fu_code_3; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fu_code_4_0 = io_ren_uops_0_fu_code_4; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fu_code_5_0 = io_ren_uops_0_fu_code_5; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fu_code_6_0 = io_ren_uops_0_fu_code_6; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fu_code_7_0 = io_ren_uops_0_fu_code_7; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fu_code_8_0 = io_ren_uops_0_fu_code_8; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fu_code_9_0 = io_ren_uops_0_fu_code_9; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_iw_issued_0 = io_ren_uops_0_iw_issued; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_iw_issued_partial_agen_0 = io_ren_uops_0_iw_issued_partial_agen; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_iw_issued_partial_dgen_0 = io_ren_uops_0_iw_issued_partial_dgen; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_iw_p1_speculative_child_0 = io_ren_uops_0_iw_p1_speculative_child; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_iw_p2_speculative_child_0 = io_ren_uops_0_iw_p2_speculative_child; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_iw_p1_bypass_hint_0 = io_ren_uops_0_iw_p1_bypass_hint; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_iw_p2_bypass_hint_0 = io_ren_uops_0_iw_p2_bypass_hint; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_iw_p3_bypass_hint_0 = io_ren_uops_0_iw_p3_bypass_hint; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_dis_col_sel_0 = io_ren_uops_0_dis_col_sel; // @[rename-busytable.scala:27:7] wire [11:0] io_ren_uops_0_br_mask_0 = io_ren_uops_0_br_mask; // @[rename-busytable.scala:27:7] wire [3:0] io_ren_uops_0_br_tag_0 = io_ren_uops_0_br_tag; // @[rename-busytable.scala:27:7] wire [3:0] io_ren_uops_0_br_type_0 = io_ren_uops_0_br_type; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_is_sfb_0 = io_ren_uops_0_is_sfb; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_is_fence_0 = io_ren_uops_0_is_fence; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_is_fencei_0 = io_ren_uops_0_is_fencei; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_is_sfence_0 = io_ren_uops_0_is_sfence; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_is_amo_0 = io_ren_uops_0_is_amo; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_is_eret_0 = io_ren_uops_0_is_eret; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_is_sys_pc2epc_0 = io_ren_uops_0_is_sys_pc2epc; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_is_rocc_0 = io_ren_uops_0_is_rocc; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_is_mov_0 = io_ren_uops_0_is_mov; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_0_ftq_idx_0 = io_ren_uops_0_ftq_idx; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_edge_inst_0 = io_ren_uops_0_edge_inst; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_0_pc_lob_0 = io_ren_uops_0_pc_lob; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_taken_0 = io_ren_uops_0_taken; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_imm_rename_0 = io_ren_uops_0_imm_rename; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_0_imm_sel_0 = io_ren_uops_0_imm_sel; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_0_pimm_0 = io_ren_uops_0_pimm; // @[rename-busytable.scala:27:7] wire [19:0] io_ren_uops_0_imm_packed_0 = io_ren_uops_0_imm_packed; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_op1_sel_0 = io_ren_uops_0_op1_sel; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_0_op2_sel_0 = io_ren_uops_0_op2_sel; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fp_ctrl_ldst_0 = io_ren_uops_0_fp_ctrl_ldst; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fp_ctrl_wen_0 = io_ren_uops_0_fp_ctrl_wen; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fp_ctrl_ren1_0 = io_ren_uops_0_fp_ctrl_ren1; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fp_ctrl_ren2_0 = io_ren_uops_0_fp_ctrl_ren2; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fp_ctrl_ren3_0 = io_ren_uops_0_fp_ctrl_ren3; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fp_ctrl_swap12_0 = io_ren_uops_0_fp_ctrl_swap12; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fp_ctrl_swap23_0 = io_ren_uops_0_fp_ctrl_swap23; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_fp_ctrl_typeTagIn_0 = io_ren_uops_0_fp_ctrl_typeTagIn; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_fp_ctrl_typeTagOut_0 = io_ren_uops_0_fp_ctrl_typeTagOut; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fp_ctrl_fromint_0 = io_ren_uops_0_fp_ctrl_fromint; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fp_ctrl_toint_0 = io_ren_uops_0_fp_ctrl_toint; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fp_ctrl_fastpipe_0 = io_ren_uops_0_fp_ctrl_fastpipe; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fp_ctrl_fma_0 = io_ren_uops_0_fp_ctrl_fma; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fp_ctrl_div_0 = io_ren_uops_0_fp_ctrl_div; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fp_ctrl_sqrt_0 = io_ren_uops_0_fp_ctrl_sqrt; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fp_ctrl_wflags_0 = io_ren_uops_0_fp_ctrl_wflags; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fp_ctrl_vec_0 = io_ren_uops_0_fp_ctrl_vec; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_0_rob_idx_0 = io_ren_uops_0_rob_idx; // @[rename-busytable.scala:27:7] wire [3:0] io_ren_uops_0_ldq_idx_0 = io_ren_uops_0_ldq_idx; // @[rename-busytable.scala:27:7] wire [3:0] io_ren_uops_0_stq_idx_0 = io_ren_uops_0_stq_idx; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_rxq_idx_0 = io_ren_uops_0_rxq_idx; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_0_pdst_0 = io_ren_uops_0_pdst; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_0_prs1_0 = io_ren_uops_0_prs1; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_0_prs2_0 = io_ren_uops_0_prs2; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_0_prs3_0 = io_ren_uops_0_prs3; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_0_ppred_0 = io_ren_uops_0_ppred; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_prs1_busy_0 = io_ren_uops_0_prs1_busy; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_prs2_busy_0 = io_ren_uops_0_prs2_busy; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_prs3_busy_0 = io_ren_uops_0_prs3_busy; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_ppred_busy_0 = io_ren_uops_0_ppred_busy; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_0_stale_pdst_0 = io_ren_uops_0_stale_pdst; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_exception_0 = io_ren_uops_0_exception; // @[rename-busytable.scala:27:7] wire [63:0] io_ren_uops_0_exc_cause_0 = io_ren_uops_0_exc_cause; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_0_mem_cmd_0 = io_ren_uops_0_mem_cmd; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_mem_size_0 = io_ren_uops_0_mem_size; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_mem_signed_0 = io_ren_uops_0_mem_signed; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_uses_ldq_0 = io_ren_uops_0_uses_ldq; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_uses_stq_0 = io_ren_uops_0_uses_stq; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_is_unique_0 = io_ren_uops_0_is_unique; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_flush_on_commit_0 = io_ren_uops_0_flush_on_commit; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_0_csr_cmd_0 = io_ren_uops_0_csr_cmd; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_ldst_is_rs1_0 = io_ren_uops_0_ldst_is_rs1; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_0_ldst_0 = io_ren_uops_0_ldst; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_0_lrs1_0 = io_ren_uops_0_lrs1; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_0_lrs2_0 = io_ren_uops_0_lrs2; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_0_lrs3_0 = io_ren_uops_0_lrs3; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_dst_rtype_0 = io_ren_uops_0_dst_rtype; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_lrs1_rtype_0 = io_ren_uops_0_lrs1_rtype; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_lrs2_rtype_0 = io_ren_uops_0_lrs2_rtype; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_frs3_en_0 = io_ren_uops_0_frs3_en; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fcn_dw_0 = io_ren_uops_0_fcn_dw; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_0_fcn_op_0 = io_ren_uops_0_fcn_op; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fp_val_0 = io_ren_uops_0_fp_val; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_0_fp_rm_0 = io_ren_uops_0_fp_rm; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_fp_typ_0 = io_ren_uops_0_fp_typ; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_xcpt_pf_if_0 = io_ren_uops_0_xcpt_pf_if; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_xcpt_ae_if_0 = io_ren_uops_0_xcpt_ae_if; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_xcpt_ma_if_0 = io_ren_uops_0_xcpt_ma_if; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_bp_debug_if_0 = io_ren_uops_0_bp_debug_if; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_bp_xcpt_if_0 = io_ren_uops_0_bp_xcpt_if; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_0_debug_fsrc_0 = io_ren_uops_0_debug_fsrc; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_0_debug_tsrc_0 = io_ren_uops_0_debug_tsrc; // @[rename-busytable.scala:27:7] wire [31:0] io_ren_uops_1_inst_0 = io_ren_uops_1_inst; // @[rename-busytable.scala:27:7] wire [31:0] io_ren_uops_1_debug_inst_0 = io_ren_uops_1_debug_inst; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_is_rvc_0 = io_ren_uops_1_is_rvc; // @[rename-busytable.scala:27:7] wire [39:0] io_ren_uops_1_debug_pc_0 = io_ren_uops_1_debug_pc; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_iq_type_0_0 = io_ren_uops_1_iq_type_0; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_iq_type_1_0 = io_ren_uops_1_iq_type_1; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_iq_type_2_0 = io_ren_uops_1_iq_type_2; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_iq_type_3_0 = io_ren_uops_1_iq_type_3; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fu_code_0_0 = io_ren_uops_1_fu_code_0; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fu_code_1_0 = io_ren_uops_1_fu_code_1; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fu_code_2_0 = io_ren_uops_1_fu_code_2; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fu_code_3_0 = io_ren_uops_1_fu_code_3; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fu_code_4_0 = io_ren_uops_1_fu_code_4; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fu_code_5_0 = io_ren_uops_1_fu_code_5; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fu_code_6_0 = io_ren_uops_1_fu_code_6; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fu_code_7_0 = io_ren_uops_1_fu_code_7; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fu_code_8_0 = io_ren_uops_1_fu_code_8; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fu_code_9_0 = io_ren_uops_1_fu_code_9; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_iw_issued_0 = io_ren_uops_1_iw_issued; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_iw_issued_partial_agen_0 = io_ren_uops_1_iw_issued_partial_agen; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_iw_issued_partial_dgen_0 = io_ren_uops_1_iw_issued_partial_dgen; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_iw_p1_speculative_child_0 = io_ren_uops_1_iw_p1_speculative_child; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_iw_p2_speculative_child_0 = io_ren_uops_1_iw_p2_speculative_child; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_iw_p1_bypass_hint_0 = io_ren_uops_1_iw_p1_bypass_hint; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_iw_p2_bypass_hint_0 = io_ren_uops_1_iw_p2_bypass_hint; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_iw_p3_bypass_hint_0 = io_ren_uops_1_iw_p3_bypass_hint; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_dis_col_sel_0 = io_ren_uops_1_dis_col_sel; // @[rename-busytable.scala:27:7] wire [11:0] io_ren_uops_1_br_mask_0 = io_ren_uops_1_br_mask; // @[rename-busytable.scala:27:7] wire [3:0] io_ren_uops_1_br_tag_0 = io_ren_uops_1_br_tag; // @[rename-busytable.scala:27:7] wire [3:0] io_ren_uops_1_br_type_0 = io_ren_uops_1_br_type; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_is_sfb_0 = io_ren_uops_1_is_sfb; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_is_fence_0 = io_ren_uops_1_is_fence; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_is_fencei_0 = io_ren_uops_1_is_fencei; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_is_sfence_0 = io_ren_uops_1_is_sfence; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_is_amo_0 = io_ren_uops_1_is_amo; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_is_eret_0 = io_ren_uops_1_is_eret; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_is_sys_pc2epc_0 = io_ren_uops_1_is_sys_pc2epc; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_is_rocc_0 = io_ren_uops_1_is_rocc; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_is_mov_0 = io_ren_uops_1_is_mov; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_1_ftq_idx_0 = io_ren_uops_1_ftq_idx; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_edge_inst_0 = io_ren_uops_1_edge_inst; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_1_pc_lob_0 = io_ren_uops_1_pc_lob; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_taken_0 = io_ren_uops_1_taken; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_imm_rename_0 = io_ren_uops_1_imm_rename; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_1_imm_sel_0 = io_ren_uops_1_imm_sel; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_1_pimm_0 = io_ren_uops_1_pimm; // @[rename-busytable.scala:27:7] wire [19:0] io_ren_uops_1_imm_packed_0 = io_ren_uops_1_imm_packed; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_op1_sel_0 = io_ren_uops_1_op1_sel; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_1_op2_sel_0 = io_ren_uops_1_op2_sel; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fp_ctrl_ldst_0 = io_ren_uops_1_fp_ctrl_ldst; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fp_ctrl_wen_0 = io_ren_uops_1_fp_ctrl_wen; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fp_ctrl_ren1_0 = io_ren_uops_1_fp_ctrl_ren1; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fp_ctrl_ren2_0 = io_ren_uops_1_fp_ctrl_ren2; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fp_ctrl_ren3_0 = io_ren_uops_1_fp_ctrl_ren3; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fp_ctrl_swap12_0 = io_ren_uops_1_fp_ctrl_swap12; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fp_ctrl_swap23_0 = io_ren_uops_1_fp_ctrl_swap23; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_fp_ctrl_typeTagIn_0 = io_ren_uops_1_fp_ctrl_typeTagIn; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_fp_ctrl_typeTagOut_0 = io_ren_uops_1_fp_ctrl_typeTagOut; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fp_ctrl_fromint_0 = io_ren_uops_1_fp_ctrl_fromint; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fp_ctrl_toint_0 = io_ren_uops_1_fp_ctrl_toint; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fp_ctrl_fastpipe_0 = io_ren_uops_1_fp_ctrl_fastpipe; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fp_ctrl_fma_0 = io_ren_uops_1_fp_ctrl_fma; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fp_ctrl_div_0 = io_ren_uops_1_fp_ctrl_div; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fp_ctrl_sqrt_0 = io_ren_uops_1_fp_ctrl_sqrt; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fp_ctrl_wflags_0 = io_ren_uops_1_fp_ctrl_wflags; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fp_ctrl_vec_0 = io_ren_uops_1_fp_ctrl_vec; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_1_rob_idx_0 = io_ren_uops_1_rob_idx; // @[rename-busytable.scala:27:7] wire [3:0] io_ren_uops_1_ldq_idx_0 = io_ren_uops_1_ldq_idx; // @[rename-busytable.scala:27:7] wire [3:0] io_ren_uops_1_stq_idx_0 = io_ren_uops_1_stq_idx; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_rxq_idx_0 = io_ren_uops_1_rxq_idx; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_1_pdst_0 = io_ren_uops_1_pdst; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_1_prs1_0 = io_ren_uops_1_prs1; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_1_prs2_0 = io_ren_uops_1_prs2; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_1_prs3_0 = io_ren_uops_1_prs3; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_1_ppred_0 = io_ren_uops_1_ppred; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_prs1_busy_0 = io_ren_uops_1_prs1_busy; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_prs2_busy_0 = io_ren_uops_1_prs2_busy; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_prs3_busy_0 = io_ren_uops_1_prs3_busy; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_ppred_busy_0 = io_ren_uops_1_ppred_busy; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_1_stale_pdst_0 = io_ren_uops_1_stale_pdst; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_exception_0 = io_ren_uops_1_exception; // @[rename-busytable.scala:27:7] wire [63:0] io_ren_uops_1_exc_cause_0 = io_ren_uops_1_exc_cause; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_1_mem_cmd_0 = io_ren_uops_1_mem_cmd; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_mem_size_0 = io_ren_uops_1_mem_size; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_mem_signed_0 = io_ren_uops_1_mem_signed; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_uses_ldq_0 = io_ren_uops_1_uses_ldq; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_uses_stq_0 = io_ren_uops_1_uses_stq; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_is_unique_0 = io_ren_uops_1_is_unique; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_flush_on_commit_0 = io_ren_uops_1_flush_on_commit; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_1_csr_cmd_0 = io_ren_uops_1_csr_cmd; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_ldst_is_rs1_0 = io_ren_uops_1_ldst_is_rs1; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_1_ldst_0 = io_ren_uops_1_ldst; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_1_lrs1_0 = io_ren_uops_1_lrs1; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_1_lrs2_0 = io_ren_uops_1_lrs2; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_1_lrs3_0 = io_ren_uops_1_lrs3; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_dst_rtype_0 = io_ren_uops_1_dst_rtype; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_lrs1_rtype_0 = io_ren_uops_1_lrs1_rtype; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_lrs2_rtype_0 = io_ren_uops_1_lrs2_rtype; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_frs3_en_0 = io_ren_uops_1_frs3_en; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fcn_dw_0 = io_ren_uops_1_fcn_dw; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_1_fcn_op_0 = io_ren_uops_1_fcn_op; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fp_val_0 = io_ren_uops_1_fp_val; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_1_fp_rm_0 = io_ren_uops_1_fp_rm; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_fp_typ_0 = io_ren_uops_1_fp_typ; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_xcpt_pf_if_0 = io_ren_uops_1_xcpt_pf_if; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_xcpt_ae_if_0 = io_ren_uops_1_xcpt_ae_if; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_xcpt_ma_if_0 = io_ren_uops_1_xcpt_ma_if; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_bp_debug_if_0 = io_ren_uops_1_bp_debug_if; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_bp_xcpt_if_0 = io_ren_uops_1_bp_xcpt_if; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_1_debug_fsrc_0 = io_ren_uops_1_debug_fsrc; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_1_debug_tsrc_0 = io_ren_uops_1_debug_tsrc; // @[rename-busytable.scala:27:7] wire io_rebusy_reqs_0_0 = io_rebusy_reqs_0; // @[rename-busytable.scala:27:7] wire io_rebusy_reqs_1_0 = io_rebusy_reqs_1; // @[rename-busytable.scala:27:7] wire io_wakeups_0_valid_0 = io_wakeups_0_valid; // @[rename-busytable.scala:27:7] wire [31:0] io_wakeups_0_bits_uop_inst_0 = io_wakeups_0_bits_uop_inst; // @[rename-busytable.scala:27:7] wire [31:0] io_wakeups_0_bits_uop_debug_inst_0 = io_wakeups_0_bits_uop_debug_inst; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_is_rvc_0 = io_wakeups_0_bits_uop_is_rvc; // @[rename-busytable.scala:27:7] wire [39:0] io_wakeups_0_bits_uop_debug_pc_0 = io_wakeups_0_bits_uop_debug_pc; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_iq_type_0_0 = io_wakeups_0_bits_uop_iq_type_0; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_iq_type_1_0 = io_wakeups_0_bits_uop_iq_type_1; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_iq_type_2_0 = io_wakeups_0_bits_uop_iq_type_2; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_iq_type_3_0 = io_wakeups_0_bits_uop_iq_type_3; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fu_code_0_0 = io_wakeups_0_bits_uop_fu_code_0; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fu_code_1_0 = io_wakeups_0_bits_uop_fu_code_1; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fu_code_2_0 = io_wakeups_0_bits_uop_fu_code_2; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fu_code_3_0 = io_wakeups_0_bits_uop_fu_code_3; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fu_code_4_0 = io_wakeups_0_bits_uop_fu_code_4; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fu_code_5_0 = io_wakeups_0_bits_uop_fu_code_5; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fu_code_6_0 = io_wakeups_0_bits_uop_fu_code_6; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fu_code_7_0 = io_wakeups_0_bits_uop_fu_code_7; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fu_code_8_0 = io_wakeups_0_bits_uop_fu_code_8; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fu_code_9_0 = io_wakeups_0_bits_uop_fu_code_9; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_iw_issued_0 = io_wakeups_0_bits_uop_iw_issued; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_iw_issued_partial_agen_0 = io_wakeups_0_bits_uop_iw_issued_partial_agen; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeups_0_bits_uop_iw_issued_partial_dgen; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_0_bits_uop_iw_p1_speculative_child_0 = io_wakeups_0_bits_uop_iw_p1_speculative_child; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_0_bits_uop_iw_p2_speculative_child_0 = io_wakeups_0_bits_uop_iw_p2_speculative_child; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeups_0_bits_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeups_0_bits_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeups_0_bits_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_0_bits_uop_dis_col_sel_0 = io_wakeups_0_bits_uop_dis_col_sel; // @[rename-busytable.scala:27:7] wire [11:0] io_wakeups_0_bits_uop_br_mask_0 = io_wakeups_0_bits_uop_br_mask; // @[rename-busytable.scala:27:7] wire [3:0] io_wakeups_0_bits_uop_br_tag_0 = io_wakeups_0_bits_uop_br_tag; // @[rename-busytable.scala:27:7] wire [3:0] io_wakeups_0_bits_uop_br_type_0 = io_wakeups_0_bits_uop_br_type; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_is_sfb_0 = io_wakeups_0_bits_uop_is_sfb; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_is_fence_0 = io_wakeups_0_bits_uop_is_fence; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_is_fencei_0 = io_wakeups_0_bits_uop_is_fencei; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_is_sfence_0 = io_wakeups_0_bits_uop_is_sfence; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_is_amo_0 = io_wakeups_0_bits_uop_is_amo; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_is_eret_0 = io_wakeups_0_bits_uop_is_eret; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_is_sys_pc2epc_0 = io_wakeups_0_bits_uop_is_sys_pc2epc; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_is_rocc_0 = io_wakeups_0_bits_uop_is_rocc; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_is_mov_0 = io_wakeups_0_bits_uop_is_mov; // @[rename-busytable.scala:27:7] wire [4:0] io_wakeups_0_bits_uop_ftq_idx_0 = io_wakeups_0_bits_uop_ftq_idx; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_edge_inst_0 = io_wakeups_0_bits_uop_edge_inst; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_0_bits_uop_pc_lob_0 = io_wakeups_0_bits_uop_pc_lob; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_taken_0 = io_wakeups_0_bits_uop_taken; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_imm_rename_0 = io_wakeups_0_bits_uop_imm_rename; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_0_bits_uop_imm_sel_0 = io_wakeups_0_bits_uop_imm_sel; // @[rename-busytable.scala:27:7] wire [4:0] io_wakeups_0_bits_uop_pimm_0 = io_wakeups_0_bits_uop_pimm; // @[rename-busytable.scala:27:7] wire [19:0] io_wakeups_0_bits_uop_imm_packed_0 = io_wakeups_0_bits_uop_imm_packed; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_0_bits_uop_op1_sel_0 = io_wakeups_0_bits_uop_op1_sel; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_0_bits_uop_op2_sel_0 = io_wakeups_0_bits_uop_op2_sel; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fp_ctrl_ldst_0 = io_wakeups_0_bits_uop_fp_ctrl_ldst; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fp_ctrl_wen_0 = io_wakeups_0_bits_uop_fp_ctrl_wen; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fp_ctrl_ren1_0 = io_wakeups_0_bits_uop_fp_ctrl_ren1; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fp_ctrl_ren2_0 = io_wakeups_0_bits_uop_fp_ctrl_ren2; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fp_ctrl_ren3_0 = io_wakeups_0_bits_uop_fp_ctrl_ren3; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fp_ctrl_swap12_0 = io_wakeups_0_bits_uop_fp_ctrl_swap12; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fp_ctrl_swap23_0 = io_wakeups_0_bits_uop_fp_ctrl_swap23; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeups_0_bits_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeups_0_bits_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fp_ctrl_fromint_0 = io_wakeups_0_bits_uop_fp_ctrl_fromint; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fp_ctrl_toint_0 = io_wakeups_0_bits_uop_fp_ctrl_toint; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeups_0_bits_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fp_ctrl_fma_0 = io_wakeups_0_bits_uop_fp_ctrl_fma; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fp_ctrl_div_0 = io_wakeups_0_bits_uop_fp_ctrl_div; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeups_0_bits_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fp_ctrl_wflags_0 = io_wakeups_0_bits_uop_fp_ctrl_wflags; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fp_ctrl_vec_0 = io_wakeups_0_bits_uop_fp_ctrl_vec; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_0_bits_uop_rob_idx_0 = io_wakeups_0_bits_uop_rob_idx; // @[rename-busytable.scala:27:7] wire [3:0] io_wakeups_0_bits_uop_ldq_idx_0 = io_wakeups_0_bits_uop_ldq_idx; // @[rename-busytable.scala:27:7] wire [3:0] io_wakeups_0_bits_uop_stq_idx_0 = io_wakeups_0_bits_uop_stq_idx; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_0_bits_uop_rxq_idx_0 = io_wakeups_0_bits_uop_rxq_idx; // @[rename-busytable.scala:27:7] wire [6:0] io_wakeups_0_bits_uop_pdst_0 = io_wakeups_0_bits_uop_pdst; // @[rename-busytable.scala:27:7] wire [6:0] io_wakeups_0_bits_uop_prs1_0 = io_wakeups_0_bits_uop_prs1; // @[rename-busytable.scala:27:7] wire [6:0] io_wakeups_0_bits_uop_prs2_0 = io_wakeups_0_bits_uop_prs2; // @[rename-busytable.scala:27:7] wire [6:0] io_wakeups_0_bits_uop_prs3_0 = io_wakeups_0_bits_uop_prs3; // @[rename-busytable.scala:27:7] wire [4:0] io_wakeups_0_bits_uop_ppred_0 = io_wakeups_0_bits_uop_ppred; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_prs1_busy_0 = io_wakeups_0_bits_uop_prs1_busy; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_prs2_busy_0 = io_wakeups_0_bits_uop_prs2_busy; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_prs3_busy_0 = io_wakeups_0_bits_uop_prs3_busy; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_ppred_busy_0 = io_wakeups_0_bits_uop_ppred_busy; // @[rename-busytable.scala:27:7] wire [6:0] io_wakeups_0_bits_uop_stale_pdst_0 = io_wakeups_0_bits_uop_stale_pdst; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_exception_0 = io_wakeups_0_bits_uop_exception; // @[rename-busytable.scala:27:7] wire [63:0] io_wakeups_0_bits_uop_exc_cause_0 = io_wakeups_0_bits_uop_exc_cause; // @[rename-busytable.scala:27:7] wire [4:0] io_wakeups_0_bits_uop_mem_cmd_0 = io_wakeups_0_bits_uop_mem_cmd; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_0_bits_uop_mem_size_0 = io_wakeups_0_bits_uop_mem_size; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_mem_signed_0 = io_wakeups_0_bits_uop_mem_signed; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_uses_ldq_0 = io_wakeups_0_bits_uop_uses_ldq; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_uses_stq_0 = io_wakeups_0_bits_uop_uses_stq; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_is_unique_0 = io_wakeups_0_bits_uop_is_unique; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_flush_on_commit_0 = io_wakeups_0_bits_uop_flush_on_commit; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_0_bits_uop_csr_cmd_0 = io_wakeups_0_bits_uop_csr_cmd; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_ldst_is_rs1_0 = io_wakeups_0_bits_uop_ldst_is_rs1; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_0_bits_uop_ldst_0 = io_wakeups_0_bits_uop_ldst; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_0_bits_uop_lrs1_0 = io_wakeups_0_bits_uop_lrs1; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_0_bits_uop_lrs2_0 = io_wakeups_0_bits_uop_lrs2; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_0_bits_uop_lrs3_0 = io_wakeups_0_bits_uop_lrs3; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_0_bits_uop_dst_rtype_0 = io_wakeups_0_bits_uop_dst_rtype; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_0_bits_uop_lrs1_rtype_0 = io_wakeups_0_bits_uop_lrs1_rtype; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_0_bits_uop_lrs2_rtype_0 = io_wakeups_0_bits_uop_lrs2_rtype; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_frs3_en_0 = io_wakeups_0_bits_uop_frs3_en; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fcn_dw_0 = io_wakeups_0_bits_uop_fcn_dw; // @[rename-busytable.scala:27:7] wire [4:0] io_wakeups_0_bits_uop_fcn_op_0 = io_wakeups_0_bits_uop_fcn_op; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fp_val_0 = io_wakeups_0_bits_uop_fp_val; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_0_bits_uop_fp_rm_0 = io_wakeups_0_bits_uop_fp_rm; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_0_bits_uop_fp_typ_0 = io_wakeups_0_bits_uop_fp_typ; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_xcpt_pf_if_0 = io_wakeups_0_bits_uop_xcpt_pf_if; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_xcpt_ae_if_0 = io_wakeups_0_bits_uop_xcpt_ae_if; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_xcpt_ma_if_0 = io_wakeups_0_bits_uop_xcpt_ma_if; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_bp_debug_if_0 = io_wakeups_0_bits_uop_bp_debug_if; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_bp_xcpt_if_0 = io_wakeups_0_bits_uop_bp_xcpt_if; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_0_bits_uop_debug_fsrc_0 = io_wakeups_0_bits_uop_debug_fsrc; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_0_bits_uop_debug_tsrc_0 = io_wakeups_0_bits_uop_debug_tsrc; // @[rename-busytable.scala:27:7] wire io_wakeups_1_valid_0 = io_wakeups_1_valid; // @[rename-busytable.scala:27:7] wire [31:0] io_wakeups_1_bits_uop_inst_0 = io_wakeups_1_bits_uop_inst; // @[rename-busytable.scala:27:7] wire [31:0] io_wakeups_1_bits_uop_debug_inst_0 = io_wakeups_1_bits_uop_debug_inst; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_is_rvc_0 = io_wakeups_1_bits_uop_is_rvc; // @[rename-busytable.scala:27:7] wire [39:0] io_wakeups_1_bits_uop_debug_pc_0 = io_wakeups_1_bits_uop_debug_pc; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_iq_type_0_0 = io_wakeups_1_bits_uop_iq_type_0; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_iq_type_1_0 = io_wakeups_1_bits_uop_iq_type_1; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_iq_type_2_0 = io_wakeups_1_bits_uop_iq_type_2; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_iq_type_3_0 = io_wakeups_1_bits_uop_iq_type_3; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fu_code_0_0 = io_wakeups_1_bits_uop_fu_code_0; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fu_code_1_0 = io_wakeups_1_bits_uop_fu_code_1; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fu_code_2_0 = io_wakeups_1_bits_uop_fu_code_2; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fu_code_3_0 = io_wakeups_1_bits_uop_fu_code_3; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fu_code_4_0 = io_wakeups_1_bits_uop_fu_code_4; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fu_code_5_0 = io_wakeups_1_bits_uop_fu_code_5; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fu_code_6_0 = io_wakeups_1_bits_uop_fu_code_6; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fu_code_7_0 = io_wakeups_1_bits_uop_fu_code_7; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fu_code_8_0 = io_wakeups_1_bits_uop_fu_code_8; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fu_code_9_0 = io_wakeups_1_bits_uop_fu_code_9; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_iw_issued_0 = io_wakeups_1_bits_uop_iw_issued; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_iw_issued_partial_agen_0 = io_wakeups_1_bits_uop_iw_issued_partial_agen; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeups_1_bits_uop_iw_issued_partial_dgen; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_1_bits_uop_iw_p1_speculative_child_0 = io_wakeups_1_bits_uop_iw_p1_speculative_child; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_1_bits_uop_iw_p2_speculative_child_0 = io_wakeups_1_bits_uop_iw_p2_speculative_child; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeups_1_bits_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeups_1_bits_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeups_1_bits_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_1_bits_uop_dis_col_sel_0 = io_wakeups_1_bits_uop_dis_col_sel; // @[rename-busytable.scala:27:7] wire [11:0] io_wakeups_1_bits_uop_br_mask_0 = io_wakeups_1_bits_uop_br_mask; // @[rename-busytable.scala:27:7] wire [3:0] io_wakeups_1_bits_uop_br_tag_0 = io_wakeups_1_bits_uop_br_tag; // @[rename-busytable.scala:27:7] wire [3:0] io_wakeups_1_bits_uop_br_type_0 = io_wakeups_1_bits_uop_br_type; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_is_sfb_0 = io_wakeups_1_bits_uop_is_sfb; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_is_fence_0 = io_wakeups_1_bits_uop_is_fence; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_is_fencei_0 = io_wakeups_1_bits_uop_is_fencei; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_is_sfence_0 = io_wakeups_1_bits_uop_is_sfence; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_is_amo_0 = io_wakeups_1_bits_uop_is_amo; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_is_eret_0 = io_wakeups_1_bits_uop_is_eret; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_is_sys_pc2epc_0 = io_wakeups_1_bits_uop_is_sys_pc2epc; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_is_rocc_0 = io_wakeups_1_bits_uop_is_rocc; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_is_mov_0 = io_wakeups_1_bits_uop_is_mov; // @[rename-busytable.scala:27:7] wire [4:0] io_wakeups_1_bits_uop_ftq_idx_0 = io_wakeups_1_bits_uop_ftq_idx; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_edge_inst_0 = io_wakeups_1_bits_uop_edge_inst; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_1_bits_uop_pc_lob_0 = io_wakeups_1_bits_uop_pc_lob; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_taken_0 = io_wakeups_1_bits_uop_taken; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_imm_rename_0 = io_wakeups_1_bits_uop_imm_rename; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_1_bits_uop_imm_sel_0 = io_wakeups_1_bits_uop_imm_sel; // @[rename-busytable.scala:27:7] wire [4:0] io_wakeups_1_bits_uop_pimm_0 = io_wakeups_1_bits_uop_pimm; // @[rename-busytable.scala:27:7] wire [19:0] io_wakeups_1_bits_uop_imm_packed_0 = io_wakeups_1_bits_uop_imm_packed; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_1_bits_uop_op1_sel_0 = io_wakeups_1_bits_uop_op1_sel; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_1_bits_uop_op2_sel_0 = io_wakeups_1_bits_uop_op2_sel; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fp_ctrl_ldst_0 = io_wakeups_1_bits_uop_fp_ctrl_ldst; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fp_ctrl_wen_0 = io_wakeups_1_bits_uop_fp_ctrl_wen; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fp_ctrl_ren1_0 = io_wakeups_1_bits_uop_fp_ctrl_ren1; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fp_ctrl_ren2_0 = io_wakeups_1_bits_uop_fp_ctrl_ren2; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fp_ctrl_ren3_0 = io_wakeups_1_bits_uop_fp_ctrl_ren3; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fp_ctrl_swap12_0 = io_wakeups_1_bits_uop_fp_ctrl_swap12; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fp_ctrl_swap23_0 = io_wakeups_1_bits_uop_fp_ctrl_swap23; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeups_1_bits_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeups_1_bits_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fp_ctrl_fromint_0 = io_wakeups_1_bits_uop_fp_ctrl_fromint; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fp_ctrl_toint_0 = io_wakeups_1_bits_uop_fp_ctrl_toint; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeups_1_bits_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fp_ctrl_fma_0 = io_wakeups_1_bits_uop_fp_ctrl_fma; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fp_ctrl_div_0 = io_wakeups_1_bits_uop_fp_ctrl_div; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeups_1_bits_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fp_ctrl_wflags_0 = io_wakeups_1_bits_uop_fp_ctrl_wflags; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fp_ctrl_vec_0 = io_wakeups_1_bits_uop_fp_ctrl_vec; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_1_bits_uop_rob_idx_0 = io_wakeups_1_bits_uop_rob_idx; // @[rename-busytable.scala:27:7] wire [3:0] io_wakeups_1_bits_uop_ldq_idx_0 = io_wakeups_1_bits_uop_ldq_idx; // @[rename-busytable.scala:27:7] wire [3:0] io_wakeups_1_bits_uop_stq_idx_0 = io_wakeups_1_bits_uop_stq_idx; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_1_bits_uop_rxq_idx_0 = io_wakeups_1_bits_uop_rxq_idx; // @[rename-busytable.scala:27:7] wire [6:0] io_wakeups_1_bits_uop_pdst_0 = io_wakeups_1_bits_uop_pdst; // @[rename-busytable.scala:27:7] wire [6:0] io_wakeups_1_bits_uop_prs1_0 = io_wakeups_1_bits_uop_prs1; // @[rename-busytable.scala:27:7] wire [6:0] io_wakeups_1_bits_uop_prs2_0 = io_wakeups_1_bits_uop_prs2; // @[rename-busytable.scala:27:7] wire [6:0] io_wakeups_1_bits_uop_prs3_0 = io_wakeups_1_bits_uop_prs3; // @[rename-busytable.scala:27:7] wire [4:0] io_wakeups_1_bits_uop_ppred_0 = io_wakeups_1_bits_uop_ppred; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_prs1_busy_0 = io_wakeups_1_bits_uop_prs1_busy; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_prs2_busy_0 = io_wakeups_1_bits_uop_prs2_busy; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_prs3_busy_0 = io_wakeups_1_bits_uop_prs3_busy; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_ppred_busy_0 = io_wakeups_1_bits_uop_ppred_busy; // @[rename-busytable.scala:27:7] wire [6:0] io_wakeups_1_bits_uop_stale_pdst_0 = io_wakeups_1_bits_uop_stale_pdst; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_exception_0 = io_wakeups_1_bits_uop_exception; // @[rename-busytable.scala:27:7] wire [63:0] io_wakeups_1_bits_uop_exc_cause_0 = io_wakeups_1_bits_uop_exc_cause; // @[rename-busytable.scala:27:7] wire [4:0] io_wakeups_1_bits_uop_mem_cmd_0 = io_wakeups_1_bits_uop_mem_cmd; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_1_bits_uop_mem_size_0 = io_wakeups_1_bits_uop_mem_size; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_mem_signed_0 = io_wakeups_1_bits_uop_mem_signed; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_uses_ldq_0 = io_wakeups_1_bits_uop_uses_ldq; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_uses_stq_0 = io_wakeups_1_bits_uop_uses_stq; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_is_unique_0 = io_wakeups_1_bits_uop_is_unique; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_flush_on_commit_0 = io_wakeups_1_bits_uop_flush_on_commit; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_1_bits_uop_csr_cmd_0 = io_wakeups_1_bits_uop_csr_cmd; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_ldst_is_rs1_0 = io_wakeups_1_bits_uop_ldst_is_rs1; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_1_bits_uop_ldst_0 = io_wakeups_1_bits_uop_ldst; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_1_bits_uop_lrs1_0 = io_wakeups_1_bits_uop_lrs1; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_1_bits_uop_lrs2_0 = io_wakeups_1_bits_uop_lrs2; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_1_bits_uop_lrs3_0 = io_wakeups_1_bits_uop_lrs3; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_1_bits_uop_dst_rtype_0 = io_wakeups_1_bits_uop_dst_rtype; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_1_bits_uop_lrs1_rtype_0 = io_wakeups_1_bits_uop_lrs1_rtype; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_1_bits_uop_lrs2_rtype_0 = io_wakeups_1_bits_uop_lrs2_rtype; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_frs3_en_0 = io_wakeups_1_bits_uop_frs3_en; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fcn_dw_0 = io_wakeups_1_bits_uop_fcn_dw; // @[rename-busytable.scala:27:7] wire [4:0] io_wakeups_1_bits_uop_fcn_op_0 = io_wakeups_1_bits_uop_fcn_op; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fp_val_0 = io_wakeups_1_bits_uop_fp_val; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_1_bits_uop_fp_rm_0 = io_wakeups_1_bits_uop_fp_rm; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_1_bits_uop_fp_typ_0 = io_wakeups_1_bits_uop_fp_typ; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_xcpt_pf_if_0 = io_wakeups_1_bits_uop_xcpt_pf_if; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_xcpt_ae_if_0 = io_wakeups_1_bits_uop_xcpt_ae_if; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_xcpt_ma_if_0 = io_wakeups_1_bits_uop_xcpt_ma_if; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_bp_debug_if_0 = io_wakeups_1_bits_uop_bp_debug_if; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_bp_xcpt_if_0 = io_wakeups_1_bits_uop_bp_xcpt_if; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_1_bits_uop_debug_fsrc_0 = io_wakeups_1_bits_uop_debug_fsrc; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_1_bits_uop_debug_tsrc_0 = io_wakeups_1_bits_uop_debug_tsrc; // @[rename-busytable.scala:27:7] wire [63:0] _busy_table_next_T_14 = 64'h0; // @[rename-busytable.scala:63:37] wire [127:0] _busy_table_next_T_15 = 128'h0; // @[rename-busytable.scala:63:31] wire io_wakeups_0_bits_rebusy = 1'h0; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_bypassable = 1'h0; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_rebusy = 1'h0; // @[rename-busytable.scala:27:7] wire wakeups_1_bits_bypassable = 1'h0; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_rebusy = 1'h0; // @[rename-busytable.scala:47:18] wire _busy_table_next_T_13 = 1'h0; // @[rename-busytable.scala:63:56] wire _io_busy_resps_0_prs1_busy_T_3 = 1'h0; // @[rename-busytable.scala:79:82] wire _io_busy_resps_0_prs1_busy_T_5 = 1'h0; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs2_busy_T_3 = 1'h0; // @[rename-busytable.scala:82:82] wire _io_busy_resps_0_prs2_busy_T_5 = 1'h0; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs3_busy_T_3 = 1'h0; // @[rename-busytable.scala:85:82] wire _io_busy_resps_0_prs3_busy_T_5 = 1'h0; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs1_busy_T_3 = 1'h0; // @[rename-busytable.scala:79:82] wire _io_busy_resps_1_prs1_busy_T_5 = 1'h0; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs2_busy_T_3 = 1'h0; // @[rename-busytable.scala:82:82] wire _io_busy_resps_1_prs2_busy_T_5 = 1'h0; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs3_busy_T_3 = 1'h0; // @[rename-busytable.scala:85:82] wire _io_busy_resps_1_prs3_busy_T_5 = 1'h0; // @[Mux.scala:30:73] wire [1:0] io_wakeups_0_bits_speculative_mask = 2'h0; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_1_bits_speculative_mask = 2'h0; // @[rename-busytable.scala:27:7] wire [1:0] io_child_rebusys = 2'h0; // @[rename-busytable.scala:27:7] wire [1:0] _wakeups_wu_valid_T = 2'h0; // @[rename-busytable.scala:48:72] wire [1:0] wakeups_1_bits_speculative_mask = 2'h0; // @[rename-busytable.scala:47:18] wire [1:0] _wakeups_wu_valid_T_3 = 2'h0; // @[rename-busytable.scala:48:72] wire io_wakeups_0_bits_bypassable = 1'h1; // @[rename-busytable.scala:27:7] wire _wakeups_wu_valid_T_1 = 1'h1; // @[rename-busytable.scala:48:92] wire _wakeups_wu_valid_T_4 = 1'h1; // @[rename-busytable.scala:48:92] wire _busy_table_wb_T_6 = 1'h1; // @[rename-busytable.scala:56:59] wire io_busy_resps_0_prs1_busy_0; // @[rename-busytable.scala:27:7] wire io_busy_resps_0_prs2_busy_0; // @[rename-busytable.scala:27:7] wire io_busy_resps_0_prs3_busy_0; // @[rename-busytable.scala:27:7] wire io_busy_resps_1_prs1_busy_0; // @[rename-busytable.scala:27:7] wire io_busy_resps_1_prs2_busy_0; // @[rename-busytable.scala:27:7] wire io_busy_resps_1_prs3_busy_0; // @[rename-busytable.scala:27:7] wire [63:0] io_debug_busytable; // @[rename-busytable.scala:27:7] wire _wakeups_wu_valid_T_2; // @[rename-busytable.scala:48:34] wire wakeups_0_bits_uop_iq_type_0; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_iq_type_1; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_iq_type_2; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_iq_type_3; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fu_code_0; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fu_code_1; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fu_code_2; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fu_code_3; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fu_code_4; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fu_code_5; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fu_code_6; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fu_code_7; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fu_code_8; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fu_code_9; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fp_ctrl_ldst; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fp_ctrl_wen; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fp_ctrl_ren1; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fp_ctrl_ren2; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fp_ctrl_ren3; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fp_ctrl_swap12; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fp_ctrl_swap23; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_0_bits_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_0_bits_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fp_ctrl_fromint; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fp_ctrl_toint; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fp_ctrl_fma; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fp_ctrl_div; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fp_ctrl_wflags; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fp_ctrl_vec; // @[rename-busytable.scala:47:18] wire [31:0] wakeups_0_bits_uop_inst; // @[rename-busytable.scala:47:18] wire [31:0] wakeups_0_bits_uop_debug_inst; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_is_rvc; // @[rename-busytable.scala:47:18] wire [39:0] wakeups_0_bits_uop_debug_pc; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_iw_issued; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_iw_issued_partial_agen; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_iw_issued_partial_dgen; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_0_bits_uop_iw_p1_speculative_child; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_0_bits_uop_iw_p2_speculative_child; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_0_bits_uop_dis_col_sel; // @[rename-busytable.scala:47:18] wire [11:0] wakeups_0_bits_uop_br_mask; // @[rename-busytable.scala:47:18] wire [3:0] wakeups_0_bits_uop_br_tag; // @[rename-busytable.scala:47:18] wire [3:0] wakeups_0_bits_uop_br_type; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_is_sfb; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_is_fence; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_is_fencei; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_is_sfence; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_is_amo; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_is_eret; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_is_sys_pc2epc; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_is_rocc; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_is_mov; // @[rename-busytable.scala:47:18] wire [4:0] wakeups_0_bits_uop_ftq_idx; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_edge_inst; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_0_bits_uop_pc_lob; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_taken; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_imm_rename; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_0_bits_uop_imm_sel; // @[rename-busytable.scala:47:18] wire [4:0] wakeups_0_bits_uop_pimm; // @[rename-busytable.scala:47:18] wire [19:0] wakeups_0_bits_uop_imm_packed; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_0_bits_uop_op1_sel; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_0_bits_uop_op2_sel; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_0_bits_uop_rob_idx; // @[rename-busytable.scala:47:18] wire [3:0] wakeups_0_bits_uop_ldq_idx; // @[rename-busytable.scala:47:18] wire [3:0] wakeups_0_bits_uop_stq_idx; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_0_bits_uop_rxq_idx; // @[rename-busytable.scala:47:18] wire [6:0] wakeups_0_bits_uop_pdst; // @[rename-busytable.scala:47:18] wire [6:0] wakeups_0_bits_uop_prs1; // @[rename-busytable.scala:47:18] wire [6:0] wakeups_0_bits_uop_prs2; // @[rename-busytable.scala:47:18] wire [6:0] wakeups_0_bits_uop_prs3; // @[rename-busytable.scala:47:18] wire [4:0] wakeups_0_bits_uop_ppred; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_prs1_busy; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_prs2_busy; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_prs3_busy; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_ppred_busy; // @[rename-busytable.scala:47:18] wire [6:0] wakeups_0_bits_uop_stale_pdst; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_exception; // @[rename-busytable.scala:47:18] wire [63:0] wakeups_0_bits_uop_exc_cause; // @[rename-busytable.scala:47:18] wire [4:0] wakeups_0_bits_uop_mem_cmd; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_0_bits_uop_mem_size; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_mem_signed; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_uses_ldq; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_uses_stq; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_is_unique; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_flush_on_commit; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_0_bits_uop_csr_cmd; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_ldst_is_rs1; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_0_bits_uop_ldst; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_0_bits_uop_lrs1; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_0_bits_uop_lrs2; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_0_bits_uop_lrs3; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_0_bits_uop_dst_rtype; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_0_bits_uop_lrs1_rtype; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_0_bits_uop_lrs2_rtype; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_frs3_en; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fcn_dw; // @[rename-busytable.scala:47:18] wire [4:0] wakeups_0_bits_uop_fcn_op; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fp_val; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_0_bits_uop_fp_rm; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_0_bits_uop_fp_typ; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_xcpt_pf_if; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_xcpt_ae_if; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_xcpt_ma_if; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_bp_debug_if; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_bp_xcpt_if; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_0_bits_uop_debug_fsrc; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_0_bits_uop_debug_tsrc; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_bypassable; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_0_bits_speculative_mask; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_rebusy; // @[rename-busytable.scala:47:18] wire wakeups_0_valid; // @[rename-busytable.scala:47:18] reg wakeups_wu_valid_REG; // @[rename-busytable.scala:48:24] assign _wakeups_wu_valid_T_2 = wakeups_wu_valid_REG; // @[rename-busytable.scala:48:{24,34}] reg [1:0] wakeups_wu_valid_REG_1; // @[rename-busytable.scala:48:46] assign wakeups_0_valid = _wakeups_wu_valid_T_2; // @[rename-busytable.scala:47:18, :48:34] reg [31:0] wakeups_wu_bits_REG_uop_inst; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_inst = wakeups_wu_bits_REG_uop_inst; // @[rename-busytable.scala:47:18, :49:24] reg [31:0] wakeups_wu_bits_REG_uop_debug_inst; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_debug_inst = wakeups_wu_bits_REG_uop_debug_inst; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_is_rvc; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_is_rvc = wakeups_wu_bits_REG_uop_is_rvc; // @[rename-busytable.scala:47:18, :49:24] reg [39:0] wakeups_wu_bits_REG_uop_debug_pc; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_debug_pc = wakeups_wu_bits_REG_uop_debug_pc; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_iq_type_0; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_iq_type_0 = wakeups_wu_bits_REG_uop_iq_type_0; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_iq_type_1; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_iq_type_1 = wakeups_wu_bits_REG_uop_iq_type_1; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_iq_type_2; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_iq_type_2 = wakeups_wu_bits_REG_uop_iq_type_2; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_iq_type_3; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_iq_type_3 = wakeups_wu_bits_REG_uop_iq_type_3; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fu_code_0; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fu_code_0 = wakeups_wu_bits_REG_uop_fu_code_0; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fu_code_1; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fu_code_1 = wakeups_wu_bits_REG_uop_fu_code_1; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fu_code_2; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fu_code_2 = wakeups_wu_bits_REG_uop_fu_code_2; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fu_code_3; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fu_code_3 = wakeups_wu_bits_REG_uop_fu_code_3; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fu_code_4; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fu_code_4 = wakeups_wu_bits_REG_uop_fu_code_4; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fu_code_5; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fu_code_5 = wakeups_wu_bits_REG_uop_fu_code_5; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fu_code_6; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fu_code_6 = wakeups_wu_bits_REG_uop_fu_code_6; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fu_code_7; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fu_code_7 = wakeups_wu_bits_REG_uop_fu_code_7; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fu_code_8; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fu_code_8 = wakeups_wu_bits_REG_uop_fu_code_8; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fu_code_9; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fu_code_9 = wakeups_wu_bits_REG_uop_fu_code_9; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_iw_issued; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_iw_issued = wakeups_wu_bits_REG_uop_iw_issued; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_iw_issued_partial_agen; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_iw_issued_partial_agen = wakeups_wu_bits_REG_uop_iw_issued_partial_agen; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_iw_issued_partial_dgen; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_iw_issued_partial_dgen = wakeups_wu_bits_REG_uop_iw_issued_partial_dgen; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_uop_iw_p1_speculative_child; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_iw_p1_speculative_child = wakeups_wu_bits_REG_uop_iw_p1_speculative_child; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_uop_iw_p2_speculative_child; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_iw_p2_speculative_child = wakeups_wu_bits_REG_uop_iw_p2_speculative_child; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_iw_p1_bypass_hint = wakeups_wu_bits_REG_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_iw_p2_bypass_hint = wakeups_wu_bits_REG_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_iw_p3_bypass_hint = wakeups_wu_bits_REG_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_uop_dis_col_sel; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_dis_col_sel = wakeups_wu_bits_REG_uop_dis_col_sel; // @[rename-busytable.scala:47:18, :49:24] reg [11:0] wakeups_wu_bits_REG_uop_br_mask; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_br_mask = wakeups_wu_bits_REG_uop_br_mask; // @[rename-busytable.scala:47:18, :49:24] reg [3:0] wakeups_wu_bits_REG_uop_br_tag; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_br_tag = wakeups_wu_bits_REG_uop_br_tag; // @[rename-busytable.scala:47:18, :49:24] reg [3:0] wakeups_wu_bits_REG_uop_br_type; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_br_type = wakeups_wu_bits_REG_uop_br_type; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_is_sfb; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_is_sfb = wakeups_wu_bits_REG_uop_is_sfb; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_is_fence; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_is_fence = wakeups_wu_bits_REG_uop_is_fence; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_is_fencei; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_is_fencei = wakeups_wu_bits_REG_uop_is_fencei; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_is_sfence; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_is_sfence = wakeups_wu_bits_REG_uop_is_sfence; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_is_amo; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_is_amo = wakeups_wu_bits_REG_uop_is_amo; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_is_eret; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_is_eret = wakeups_wu_bits_REG_uop_is_eret; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_is_sys_pc2epc; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_is_sys_pc2epc = wakeups_wu_bits_REG_uop_is_sys_pc2epc; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_is_rocc; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_is_rocc = wakeups_wu_bits_REG_uop_is_rocc; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_is_mov; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_is_mov = wakeups_wu_bits_REG_uop_is_mov; // @[rename-busytable.scala:47:18, :49:24] reg [4:0] wakeups_wu_bits_REG_uop_ftq_idx; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_ftq_idx = wakeups_wu_bits_REG_uop_ftq_idx; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_edge_inst; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_edge_inst = wakeups_wu_bits_REG_uop_edge_inst; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_uop_pc_lob; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_pc_lob = wakeups_wu_bits_REG_uop_pc_lob; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_taken; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_taken = wakeups_wu_bits_REG_uop_taken; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_imm_rename; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_imm_rename = wakeups_wu_bits_REG_uop_imm_rename; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_uop_imm_sel; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_imm_sel = wakeups_wu_bits_REG_uop_imm_sel; // @[rename-busytable.scala:47:18, :49:24] reg [4:0] wakeups_wu_bits_REG_uop_pimm; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_pimm = wakeups_wu_bits_REG_uop_pimm; // @[rename-busytable.scala:47:18, :49:24] reg [19:0] wakeups_wu_bits_REG_uop_imm_packed; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_imm_packed = wakeups_wu_bits_REG_uop_imm_packed; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_uop_op1_sel; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_op1_sel = wakeups_wu_bits_REG_uop_op1_sel; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_uop_op2_sel; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_op2_sel = wakeups_wu_bits_REG_uop_op2_sel; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fp_ctrl_ldst; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_ctrl_ldst = wakeups_wu_bits_REG_uop_fp_ctrl_ldst; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fp_ctrl_wen; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_ctrl_wen = wakeups_wu_bits_REG_uop_fp_ctrl_wen; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fp_ctrl_ren1; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_ctrl_ren1 = wakeups_wu_bits_REG_uop_fp_ctrl_ren1; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fp_ctrl_ren2; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_ctrl_ren2 = wakeups_wu_bits_REG_uop_fp_ctrl_ren2; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fp_ctrl_ren3; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_ctrl_ren3 = wakeups_wu_bits_REG_uop_fp_ctrl_ren3; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fp_ctrl_swap12; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_ctrl_swap12 = wakeups_wu_bits_REG_uop_fp_ctrl_swap12; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fp_ctrl_swap23; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_ctrl_swap23 = wakeups_wu_bits_REG_uop_fp_ctrl_swap23; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_ctrl_typeTagIn = wakeups_wu_bits_REG_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_ctrl_typeTagOut = wakeups_wu_bits_REG_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fp_ctrl_fromint; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_ctrl_fromint = wakeups_wu_bits_REG_uop_fp_ctrl_fromint; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fp_ctrl_toint; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_ctrl_toint = wakeups_wu_bits_REG_uop_fp_ctrl_toint; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_ctrl_fastpipe = wakeups_wu_bits_REG_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fp_ctrl_fma; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_ctrl_fma = wakeups_wu_bits_REG_uop_fp_ctrl_fma; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fp_ctrl_div; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_ctrl_div = wakeups_wu_bits_REG_uop_fp_ctrl_div; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_ctrl_sqrt = wakeups_wu_bits_REG_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fp_ctrl_wflags; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_ctrl_wflags = wakeups_wu_bits_REG_uop_fp_ctrl_wflags; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fp_ctrl_vec; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_ctrl_vec = wakeups_wu_bits_REG_uop_fp_ctrl_vec; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_uop_rob_idx; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_rob_idx = wakeups_wu_bits_REG_uop_rob_idx; // @[rename-busytable.scala:47:18, :49:24] reg [3:0] wakeups_wu_bits_REG_uop_ldq_idx; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_ldq_idx = wakeups_wu_bits_REG_uop_ldq_idx; // @[rename-busytable.scala:47:18, :49:24] reg [3:0] wakeups_wu_bits_REG_uop_stq_idx; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_stq_idx = wakeups_wu_bits_REG_uop_stq_idx; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_uop_rxq_idx; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_rxq_idx = wakeups_wu_bits_REG_uop_rxq_idx; // @[rename-busytable.scala:47:18, :49:24] reg [6:0] wakeups_wu_bits_REG_uop_pdst; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_pdst = wakeups_wu_bits_REG_uop_pdst; // @[rename-busytable.scala:47:18, :49:24] reg [6:0] wakeups_wu_bits_REG_uop_prs1; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_prs1 = wakeups_wu_bits_REG_uop_prs1; // @[rename-busytable.scala:47:18, :49:24] reg [6:0] wakeups_wu_bits_REG_uop_prs2; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_prs2 = wakeups_wu_bits_REG_uop_prs2; // @[rename-busytable.scala:47:18, :49:24] reg [6:0] wakeups_wu_bits_REG_uop_prs3; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_prs3 = wakeups_wu_bits_REG_uop_prs3; // @[rename-busytable.scala:47:18, :49:24] reg [4:0] wakeups_wu_bits_REG_uop_ppred; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_ppred = wakeups_wu_bits_REG_uop_ppred; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_prs1_busy; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_prs1_busy = wakeups_wu_bits_REG_uop_prs1_busy; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_prs2_busy; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_prs2_busy = wakeups_wu_bits_REG_uop_prs2_busy; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_prs3_busy; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_prs3_busy = wakeups_wu_bits_REG_uop_prs3_busy; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_ppred_busy; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_ppred_busy = wakeups_wu_bits_REG_uop_ppred_busy; // @[rename-busytable.scala:47:18, :49:24] reg [6:0] wakeups_wu_bits_REG_uop_stale_pdst; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_stale_pdst = wakeups_wu_bits_REG_uop_stale_pdst; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_exception; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_exception = wakeups_wu_bits_REG_uop_exception; // @[rename-busytable.scala:47:18, :49:24] reg [63:0] wakeups_wu_bits_REG_uop_exc_cause; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_exc_cause = wakeups_wu_bits_REG_uop_exc_cause; // @[rename-busytable.scala:47:18, :49:24] reg [4:0] wakeups_wu_bits_REG_uop_mem_cmd; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_mem_cmd = wakeups_wu_bits_REG_uop_mem_cmd; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_uop_mem_size; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_mem_size = wakeups_wu_bits_REG_uop_mem_size; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_mem_signed; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_mem_signed = wakeups_wu_bits_REG_uop_mem_signed; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_uses_ldq; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_uses_ldq = wakeups_wu_bits_REG_uop_uses_ldq; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_uses_stq; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_uses_stq = wakeups_wu_bits_REG_uop_uses_stq; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_is_unique; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_is_unique = wakeups_wu_bits_REG_uop_is_unique; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_flush_on_commit; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_flush_on_commit = wakeups_wu_bits_REG_uop_flush_on_commit; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_uop_csr_cmd; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_csr_cmd = wakeups_wu_bits_REG_uop_csr_cmd; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_ldst_is_rs1; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_ldst_is_rs1 = wakeups_wu_bits_REG_uop_ldst_is_rs1; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_uop_ldst; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_ldst = wakeups_wu_bits_REG_uop_ldst; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_uop_lrs1; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_lrs1 = wakeups_wu_bits_REG_uop_lrs1; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_uop_lrs2; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_lrs2 = wakeups_wu_bits_REG_uop_lrs2; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_uop_lrs3; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_lrs3 = wakeups_wu_bits_REG_uop_lrs3; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_uop_dst_rtype; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_dst_rtype = wakeups_wu_bits_REG_uop_dst_rtype; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_uop_lrs1_rtype; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_lrs1_rtype = wakeups_wu_bits_REG_uop_lrs1_rtype; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_uop_lrs2_rtype; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_lrs2_rtype = wakeups_wu_bits_REG_uop_lrs2_rtype; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_frs3_en; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_frs3_en = wakeups_wu_bits_REG_uop_frs3_en; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fcn_dw; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fcn_dw = wakeups_wu_bits_REG_uop_fcn_dw; // @[rename-busytable.scala:47:18, :49:24] reg [4:0] wakeups_wu_bits_REG_uop_fcn_op; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fcn_op = wakeups_wu_bits_REG_uop_fcn_op; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fp_val; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_val = wakeups_wu_bits_REG_uop_fp_val; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_uop_fp_rm; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_rm = wakeups_wu_bits_REG_uop_fp_rm; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_uop_fp_typ; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_typ = wakeups_wu_bits_REG_uop_fp_typ; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_xcpt_pf_if; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_xcpt_pf_if = wakeups_wu_bits_REG_uop_xcpt_pf_if; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_xcpt_ae_if; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_xcpt_ae_if = wakeups_wu_bits_REG_uop_xcpt_ae_if; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_xcpt_ma_if; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_xcpt_ma_if = wakeups_wu_bits_REG_uop_xcpt_ma_if; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_bp_debug_if; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_bp_debug_if = wakeups_wu_bits_REG_uop_bp_debug_if; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_bp_xcpt_if; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_bp_xcpt_if = wakeups_wu_bits_REG_uop_bp_xcpt_if; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_uop_debug_fsrc; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_debug_fsrc = wakeups_wu_bits_REG_uop_debug_fsrc; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_uop_debug_tsrc; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_debug_tsrc = wakeups_wu_bits_REG_uop_debug_tsrc; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_bypassable; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_bypassable = wakeups_wu_bits_REG_bypassable; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_speculative_mask; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_speculative_mask = wakeups_wu_bits_REG_speculative_mask; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_rebusy; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_rebusy = wakeups_wu_bits_REG_rebusy; // @[rename-busytable.scala:47:18, :49:24] wire _wakeups_wu_valid_T_5; // @[rename-busytable.scala:48:34] wire _busy_table_wb_T_7 = wakeups_1_valid; // @[rename-busytable.scala:47:18, :56:56] wire wakeups_1_bits_uop_iq_type_0; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_iq_type_1; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_iq_type_2; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_iq_type_3; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fu_code_0; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fu_code_1; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fu_code_2; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fu_code_3; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fu_code_4; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fu_code_5; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fu_code_6; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fu_code_7; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fu_code_8; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fu_code_9; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fp_ctrl_ldst; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fp_ctrl_wen; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fp_ctrl_ren1; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fp_ctrl_ren2; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fp_ctrl_ren3; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fp_ctrl_swap12; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fp_ctrl_swap23; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_1_bits_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_1_bits_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fp_ctrl_fromint; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fp_ctrl_toint; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fp_ctrl_fma; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fp_ctrl_div; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fp_ctrl_wflags; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fp_ctrl_vec; // @[rename-busytable.scala:47:18] wire [31:0] wakeups_1_bits_uop_inst; // @[rename-busytable.scala:47:18] wire [31:0] wakeups_1_bits_uop_debug_inst; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_is_rvc; // @[rename-busytable.scala:47:18] wire [39:0] wakeups_1_bits_uop_debug_pc; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_iw_issued; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_iw_issued_partial_agen; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_iw_issued_partial_dgen; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_1_bits_uop_iw_p1_speculative_child; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_1_bits_uop_iw_p2_speculative_child; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_1_bits_uop_dis_col_sel; // @[rename-busytable.scala:47:18] wire [11:0] wakeups_1_bits_uop_br_mask; // @[rename-busytable.scala:47:18] wire [3:0] wakeups_1_bits_uop_br_tag; // @[rename-busytable.scala:47:18] wire [3:0] wakeups_1_bits_uop_br_type; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_is_sfb; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_is_fence; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_is_fencei; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_is_sfence; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_is_amo; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_is_eret; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_is_sys_pc2epc; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_is_rocc; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_is_mov; // @[rename-busytable.scala:47:18] wire [4:0] wakeups_1_bits_uop_ftq_idx; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_edge_inst; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_1_bits_uop_pc_lob; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_taken; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_imm_rename; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_1_bits_uop_imm_sel; // @[rename-busytable.scala:47:18] wire [4:0] wakeups_1_bits_uop_pimm; // @[rename-busytable.scala:47:18] wire [19:0] wakeups_1_bits_uop_imm_packed; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_1_bits_uop_op1_sel; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_1_bits_uop_op2_sel; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_1_bits_uop_rob_idx; // @[rename-busytable.scala:47:18] wire [3:0] wakeups_1_bits_uop_ldq_idx; // @[rename-busytable.scala:47:18] wire [3:0] wakeups_1_bits_uop_stq_idx; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_1_bits_uop_rxq_idx; // @[rename-busytable.scala:47:18] wire [6:0] wakeups_1_bits_uop_pdst; // @[rename-busytable.scala:47:18] wire [6:0] wakeups_1_bits_uop_prs1; // @[rename-busytable.scala:47:18] wire [6:0] wakeups_1_bits_uop_prs2; // @[rename-busytable.scala:47:18] wire [6:0] wakeups_1_bits_uop_prs3; // @[rename-busytable.scala:47:18] wire [4:0] wakeups_1_bits_uop_ppred; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_prs1_busy; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_prs2_busy; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_prs3_busy; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_ppred_busy; // @[rename-busytable.scala:47:18] wire [6:0] wakeups_1_bits_uop_stale_pdst; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_exception; // @[rename-busytable.scala:47:18] wire [63:0] wakeups_1_bits_uop_exc_cause; // @[rename-busytable.scala:47:18] wire [4:0] wakeups_1_bits_uop_mem_cmd; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_1_bits_uop_mem_size; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_mem_signed; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_uses_ldq; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_uses_stq; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_is_unique; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_flush_on_commit; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_1_bits_uop_csr_cmd; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_ldst_is_rs1; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_1_bits_uop_ldst; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_1_bits_uop_lrs1; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_1_bits_uop_lrs2; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_1_bits_uop_lrs3; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_1_bits_uop_dst_rtype; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_1_bits_uop_lrs1_rtype; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_1_bits_uop_lrs2_rtype; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_frs3_en; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fcn_dw; // @[rename-busytable.scala:47:18] wire [4:0] wakeups_1_bits_uop_fcn_op; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fp_val; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_1_bits_uop_fp_rm; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_1_bits_uop_fp_typ; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_xcpt_pf_if; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_xcpt_ae_if; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_xcpt_ma_if; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_bp_debug_if; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_bp_xcpt_if; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_1_bits_uop_debug_fsrc; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_1_bits_uop_debug_tsrc; // @[rename-busytable.scala:47:18] reg wakeups_wu_valid_REG_2; // @[rename-busytable.scala:48:24] assign _wakeups_wu_valid_T_5 = wakeups_wu_valid_REG_2; // @[rename-busytable.scala:48:{24,34}] assign wakeups_1_valid = _wakeups_wu_valid_T_5; // @[rename-busytable.scala:47:18, :48:34] reg [31:0] wakeups_wu_bits_REG_1_uop_inst; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_inst = wakeups_wu_bits_REG_1_uop_inst; // @[rename-busytable.scala:47:18, :49:24] reg [31:0] wakeups_wu_bits_REG_1_uop_debug_inst; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_debug_inst = wakeups_wu_bits_REG_1_uop_debug_inst; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_is_rvc; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_is_rvc = wakeups_wu_bits_REG_1_uop_is_rvc; // @[rename-busytable.scala:47:18, :49:24] reg [39:0] wakeups_wu_bits_REG_1_uop_debug_pc; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_debug_pc = wakeups_wu_bits_REG_1_uop_debug_pc; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_iq_type_0; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_iq_type_0 = wakeups_wu_bits_REG_1_uop_iq_type_0; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_iq_type_1; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_iq_type_1 = wakeups_wu_bits_REG_1_uop_iq_type_1; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_iq_type_2; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_iq_type_2 = wakeups_wu_bits_REG_1_uop_iq_type_2; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_iq_type_3; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_iq_type_3 = wakeups_wu_bits_REG_1_uop_iq_type_3; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fu_code_0; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fu_code_0 = wakeups_wu_bits_REG_1_uop_fu_code_0; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fu_code_1; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fu_code_1 = wakeups_wu_bits_REG_1_uop_fu_code_1; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fu_code_2; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fu_code_2 = wakeups_wu_bits_REG_1_uop_fu_code_2; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fu_code_3; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fu_code_3 = wakeups_wu_bits_REG_1_uop_fu_code_3; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fu_code_4; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fu_code_4 = wakeups_wu_bits_REG_1_uop_fu_code_4; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fu_code_5; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fu_code_5 = wakeups_wu_bits_REG_1_uop_fu_code_5; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fu_code_6; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fu_code_6 = wakeups_wu_bits_REG_1_uop_fu_code_6; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fu_code_7; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fu_code_7 = wakeups_wu_bits_REG_1_uop_fu_code_7; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fu_code_8; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fu_code_8 = wakeups_wu_bits_REG_1_uop_fu_code_8; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fu_code_9; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fu_code_9 = wakeups_wu_bits_REG_1_uop_fu_code_9; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_iw_issued; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_iw_issued = wakeups_wu_bits_REG_1_uop_iw_issued; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_iw_issued_partial_agen; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_iw_issued_partial_agen = wakeups_wu_bits_REG_1_uop_iw_issued_partial_agen; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_iw_issued_partial_dgen; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_iw_issued_partial_dgen = wakeups_wu_bits_REG_1_uop_iw_issued_partial_dgen; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_1_uop_iw_p1_speculative_child; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_iw_p1_speculative_child = wakeups_wu_bits_REG_1_uop_iw_p1_speculative_child; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_1_uop_iw_p2_speculative_child; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_iw_p2_speculative_child = wakeups_wu_bits_REG_1_uop_iw_p2_speculative_child; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_iw_p1_bypass_hint = wakeups_wu_bits_REG_1_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_iw_p2_bypass_hint = wakeups_wu_bits_REG_1_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_iw_p3_bypass_hint = wakeups_wu_bits_REG_1_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_1_uop_dis_col_sel; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_dis_col_sel = wakeups_wu_bits_REG_1_uop_dis_col_sel; // @[rename-busytable.scala:47:18, :49:24] reg [11:0] wakeups_wu_bits_REG_1_uop_br_mask; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_br_mask = wakeups_wu_bits_REG_1_uop_br_mask; // @[rename-busytable.scala:47:18, :49:24] reg [3:0] wakeups_wu_bits_REG_1_uop_br_tag; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_br_tag = wakeups_wu_bits_REG_1_uop_br_tag; // @[rename-busytable.scala:47:18, :49:24] reg [3:0] wakeups_wu_bits_REG_1_uop_br_type; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_br_type = wakeups_wu_bits_REG_1_uop_br_type; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_is_sfb; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_is_sfb = wakeups_wu_bits_REG_1_uop_is_sfb; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_is_fence; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_is_fence = wakeups_wu_bits_REG_1_uop_is_fence; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_is_fencei; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_is_fencei = wakeups_wu_bits_REG_1_uop_is_fencei; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_is_sfence; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_is_sfence = wakeups_wu_bits_REG_1_uop_is_sfence; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_is_amo; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_is_amo = wakeups_wu_bits_REG_1_uop_is_amo; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_is_eret; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_is_eret = wakeups_wu_bits_REG_1_uop_is_eret; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_is_sys_pc2epc; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_is_sys_pc2epc = wakeups_wu_bits_REG_1_uop_is_sys_pc2epc; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_is_rocc; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_is_rocc = wakeups_wu_bits_REG_1_uop_is_rocc; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_is_mov; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_is_mov = wakeups_wu_bits_REG_1_uop_is_mov; // @[rename-busytable.scala:47:18, :49:24] reg [4:0] wakeups_wu_bits_REG_1_uop_ftq_idx; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_ftq_idx = wakeups_wu_bits_REG_1_uop_ftq_idx; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_edge_inst; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_edge_inst = wakeups_wu_bits_REG_1_uop_edge_inst; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_1_uop_pc_lob; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_pc_lob = wakeups_wu_bits_REG_1_uop_pc_lob; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_taken; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_taken = wakeups_wu_bits_REG_1_uop_taken; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_imm_rename; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_imm_rename = wakeups_wu_bits_REG_1_uop_imm_rename; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_1_uop_imm_sel; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_imm_sel = wakeups_wu_bits_REG_1_uop_imm_sel; // @[rename-busytable.scala:47:18, :49:24] reg [4:0] wakeups_wu_bits_REG_1_uop_pimm; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_pimm = wakeups_wu_bits_REG_1_uop_pimm; // @[rename-busytable.scala:47:18, :49:24] reg [19:0] wakeups_wu_bits_REG_1_uop_imm_packed; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_imm_packed = wakeups_wu_bits_REG_1_uop_imm_packed; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_1_uop_op1_sel; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_op1_sel = wakeups_wu_bits_REG_1_uop_op1_sel; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_1_uop_op2_sel; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_op2_sel = wakeups_wu_bits_REG_1_uop_op2_sel; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fp_ctrl_ldst; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_ctrl_ldst = wakeups_wu_bits_REG_1_uop_fp_ctrl_ldst; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fp_ctrl_wen; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_ctrl_wen = wakeups_wu_bits_REG_1_uop_fp_ctrl_wen; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fp_ctrl_ren1; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_ctrl_ren1 = wakeups_wu_bits_REG_1_uop_fp_ctrl_ren1; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fp_ctrl_ren2; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_ctrl_ren2 = wakeups_wu_bits_REG_1_uop_fp_ctrl_ren2; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fp_ctrl_ren3; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_ctrl_ren3 = wakeups_wu_bits_REG_1_uop_fp_ctrl_ren3; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fp_ctrl_swap12; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_ctrl_swap12 = wakeups_wu_bits_REG_1_uop_fp_ctrl_swap12; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fp_ctrl_swap23; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_ctrl_swap23 = wakeups_wu_bits_REG_1_uop_fp_ctrl_swap23; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_1_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_ctrl_typeTagIn = wakeups_wu_bits_REG_1_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_1_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_ctrl_typeTagOut = wakeups_wu_bits_REG_1_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fp_ctrl_fromint; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_ctrl_fromint = wakeups_wu_bits_REG_1_uop_fp_ctrl_fromint; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fp_ctrl_toint; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_ctrl_toint = wakeups_wu_bits_REG_1_uop_fp_ctrl_toint; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_ctrl_fastpipe = wakeups_wu_bits_REG_1_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fp_ctrl_fma; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_ctrl_fma = wakeups_wu_bits_REG_1_uop_fp_ctrl_fma; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fp_ctrl_div; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_ctrl_div = wakeups_wu_bits_REG_1_uop_fp_ctrl_div; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_ctrl_sqrt = wakeups_wu_bits_REG_1_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fp_ctrl_wflags; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_ctrl_wflags = wakeups_wu_bits_REG_1_uop_fp_ctrl_wflags; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fp_ctrl_vec; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_ctrl_vec = wakeups_wu_bits_REG_1_uop_fp_ctrl_vec; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_1_uop_rob_idx; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_rob_idx = wakeups_wu_bits_REG_1_uop_rob_idx; // @[rename-busytable.scala:47:18, :49:24] reg [3:0] wakeups_wu_bits_REG_1_uop_ldq_idx; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_ldq_idx = wakeups_wu_bits_REG_1_uop_ldq_idx; // @[rename-busytable.scala:47:18, :49:24] reg [3:0] wakeups_wu_bits_REG_1_uop_stq_idx; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_stq_idx = wakeups_wu_bits_REG_1_uop_stq_idx; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_1_uop_rxq_idx; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_rxq_idx = wakeups_wu_bits_REG_1_uop_rxq_idx; // @[rename-busytable.scala:47:18, :49:24] reg [6:0] wakeups_wu_bits_REG_1_uop_pdst; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_pdst = wakeups_wu_bits_REG_1_uop_pdst; // @[rename-busytable.scala:47:18, :49:24] reg [6:0] wakeups_wu_bits_REG_1_uop_prs1; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_prs1 = wakeups_wu_bits_REG_1_uop_prs1; // @[rename-busytable.scala:47:18, :49:24] reg [6:0] wakeups_wu_bits_REG_1_uop_prs2; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_prs2 = wakeups_wu_bits_REG_1_uop_prs2; // @[rename-busytable.scala:47:18, :49:24] reg [6:0] wakeups_wu_bits_REG_1_uop_prs3; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_prs3 = wakeups_wu_bits_REG_1_uop_prs3; // @[rename-busytable.scala:47:18, :49:24] reg [4:0] wakeups_wu_bits_REG_1_uop_ppred; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_ppred = wakeups_wu_bits_REG_1_uop_ppred; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_prs1_busy; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_prs1_busy = wakeups_wu_bits_REG_1_uop_prs1_busy; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_prs2_busy; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_prs2_busy = wakeups_wu_bits_REG_1_uop_prs2_busy; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_prs3_busy; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_prs3_busy = wakeups_wu_bits_REG_1_uop_prs3_busy; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_ppred_busy; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_ppred_busy = wakeups_wu_bits_REG_1_uop_ppred_busy; // @[rename-busytable.scala:47:18, :49:24] reg [6:0] wakeups_wu_bits_REG_1_uop_stale_pdst; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_stale_pdst = wakeups_wu_bits_REG_1_uop_stale_pdst; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_exception; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_exception = wakeups_wu_bits_REG_1_uop_exception; // @[rename-busytable.scala:47:18, :49:24] reg [63:0] wakeups_wu_bits_REG_1_uop_exc_cause; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_exc_cause = wakeups_wu_bits_REG_1_uop_exc_cause; // @[rename-busytable.scala:47:18, :49:24] reg [4:0] wakeups_wu_bits_REG_1_uop_mem_cmd; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_mem_cmd = wakeups_wu_bits_REG_1_uop_mem_cmd; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_1_uop_mem_size; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_mem_size = wakeups_wu_bits_REG_1_uop_mem_size; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_mem_signed; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_mem_signed = wakeups_wu_bits_REG_1_uop_mem_signed; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_uses_ldq; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_uses_ldq = wakeups_wu_bits_REG_1_uop_uses_ldq; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_uses_stq; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_uses_stq = wakeups_wu_bits_REG_1_uop_uses_stq; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_is_unique; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_is_unique = wakeups_wu_bits_REG_1_uop_is_unique; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_flush_on_commit; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_flush_on_commit = wakeups_wu_bits_REG_1_uop_flush_on_commit; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_1_uop_csr_cmd; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_csr_cmd = wakeups_wu_bits_REG_1_uop_csr_cmd; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_ldst_is_rs1; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_ldst_is_rs1 = wakeups_wu_bits_REG_1_uop_ldst_is_rs1; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_1_uop_ldst; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_ldst = wakeups_wu_bits_REG_1_uop_ldst; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_1_uop_lrs1; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_lrs1 = wakeups_wu_bits_REG_1_uop_lrs1; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_1_uop_lrs2; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_lrs2 = wakeups_wu_bits_REG_1_uop_lrs2; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_1_uop_lrs3; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_lrs3 = wakeups_wu_bits_REG_1_uop_lrs3; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_1_uop_dst_rtype; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_dst_rtype = wakeups_wu_bits_REG_1_uop_dst_rtype; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_1_uop_lrs1_rtype; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_lrs1_rtype = wakeups_wu_bits_REG_1_uop_lrs1_rtype; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_1_uop_lrs2_rtype; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_lrs2_rtype = wakeups_wu_bits_REG_1_uop_lrs2_rtype; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_frs3_en; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_frs3_en = wakeups_wu_bits_REG_1_uop_frs3_en; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fcn_dw; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fcn_dw = wakeups_wu_bits_REG_1_uop_fcn_dw; // @[rename-busytable.scala:47:18, :49:24] reg [4:0] wakeups_wu_bits_REG_1_uop_fcn_op; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fcn_op = wakeups_wu_bits_REG_1_uop_fcn_op; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fp_val; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_val = wakeups_wu_bits_REG_1_uop_fp_val; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_1_uop_fp_rm; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_rm = wakeups_wu_bits_REG_1_uop_fp_rm; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_1_uop_fp_typ; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_typ = wakeups_wu_bits_REG_1_uop_fp_typ; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_xcpt_pf_if; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_xcpt_pf_if = wakeups_wu_bits_REG_1_uop_xcpt_pf_if; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_xcpt_ae_if; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_xcpt_ae_if = wakeups_wu_bits_REG_1_uop_xcpt_ae_if; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_xcpt_ma_if; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_xcpt_ma_if = wakeups_wu_bits_REG_1_uop_xcpt_ma_if; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_bp_debug_if; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_bp_debug_if = wakeups_wu_bits_REG_1_uop_bp_debug_if; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_bp_xcpt_if; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_bp_xcpt_if = wakeups_wu_bits_REG_1_uop_bp_xcpt_if; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_1_uop_debug_fsrc; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_debug_fsrc = wakeups_wu_bits_REG_1_uop_debug_fsrc; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_1_uop_debug_tsrc; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_debug_tsrc = wakeups_wu_bits_REG_1_uop_debug_tsrc; // @[rename-busytable.scala:47:18, :49:24] reg [63:0] busy_table; // @[rename-busytable.scala:53:27] assign io_debug_busytable = busy_table; // @[rename-busytable.scala:27:7, :53:27] wire [127:0] _GEN = 128'h1 << wakeups_0_bits_uop_pdst; // @[OneHot.scala:58:35] wire [127:0] _busy_table_wb_T; // @[OneHot.scala:58:35] assign _busy_table_wb_T = _GEN; // @[OneHot.scala:58:35] wire [127:0] _busy_table_next_T_8; // @[OneHot.scala:58:35] assign _busy_table_next_T_8 = _GEN; // @[OneHot.scala:58:35] wire _busy_table_wb_T_1 = ~wakeups_0_bits_rebusy; // @[rename-busytable.scala:47:18, :56:59] wire _busy_table_wb_T_2 = wakeups_0_valid & _busy_table_wb_T_1; // @[rename-busytable.scala:47:18, :56:{56,59}] wire [63:0] _busy_table_wb_T_3 = {64{_busy_table_wb_T_2}}; // @[rename-busytable.scala:56:{37,56}] wire [127:0] _busy_table_wb_T_4 = {64'h0, _busy_table_wb_T[63:0] & _busy_table_wb_T_3}; // @[OneHot.scala:58:35] wire [127:0] _GEN_0 = 128'h1 << wakeups_1_bits_uop_pdst; // @[OneHot.scala:58:35] wire [127:0] _busy_table_wb_T_5; // @[OneHot.scala:58:35] assign _busy_table_wb_T_5 = _GEN_0; // @[OneHot.scala:58:35] wire [127:0] _busy_table_next_T_12; // @[OneHot.scala:58:35] assign _busy_table_next_T_12 = _GEN_0; // @[OneHot.scala:58:35] wire [63:0] _busy_table_wb_T_8 = {64{_busy_table_wb_T_7}}; // @[rename-busytable.scala:56:{37,56}] wire [127:0] _busy_table_wb_T_9 = {64'h0, _busy_table_wb_T_5[63:0] & _busy_table_wb_T_8}; // @[OneHot.scala:58:35] wire [127:0] _busy_table_wb_T_10 = _busy_table_wb_T_4 | _busy_table_wb_T_9; // @[rename-busytable.scala:56:31, :57:14] wire [127:0] _busy_table_wb_T_11 = ~_busy_table_wb_T_10; // @[rename-busytable.scala:55:36, :57:14] wire [127:0] busy_table_wb = {64'h0, _busy_table_wb_T_11[63:0] & busy_table}; // @[rename-busytable.scala:53:27, :55:{34,36}] wire [127:0] _busy_table_next_T = 128'h1 << io_ren_uops_0_pdst_0; // @[OneHot.scala:58:35] wire [63:0] _busy_table_next_T_1 = {64{io_rebusy_reqs_0_0}}; // @[rename-busytable.scala:27:7, :61:57] wire [127:0] _busy_table_next_T_2 = {64'h0, _busy_table_next_T[63:0] & _busy_table_next_T_1}; // @[OneHot.scala:58:35] wire [127:0] _busy_table_next_T_3 = 128'h1 << io_ren_uops_1_pdst_0; // @[OneHot.scala:58:35] wire [63:0] _busy_table_next_T_4 = {64{io_rebusy_reqs_1_0}}; // @[rename-busytable.scala:27:7, :61:57] wire [127:0] _busy_table_next_T_5 = {64'h0, _busy_table_next_T_3[63:0] & _busy_table_next_T_4}; // @[OneHot.scala:58:35] wire [127:0] _busy_table_next_T_6 = _busy_table_next_T_2 | _busy_table_next_T_5; // @[rename-busytable.scala:61:{51,82}] wire [127:0] _busy_table_next_T_7 = busy_table_wb | _busy_table_next_T_6; // @[rename-busytable.scala:55:34, :59:39, :61:82] wire _GEN_1 = wakeups_0_valid & wakeups_0_bits_rebusy; // @[rename-busytable.scala:47:18, :63:56] wire _busy_table_next_T_9; // @[rename-busytable.scala:63:56] assign _busy_table_next_T_9 = _GEN_1; // @[rename-busytable.scala:63:56] wire _io_busy_resps_0_prs1_busy_T_2; // @[rename-busytable.scala:79:82] assign _io_busy_resps_0_prs1_busy_T_2 = _GEN_1; // @[rename-busytable.scala:63:56, :79:82] wire _io_busy_resps_0_prs2_busy_T_2; // @[rename-busytable.scala:82:82] assign _io_busy_resps_0_prs2_busy_T_2 = _GEN_1; // @[rename-busytable.scala:63:56, :82:82] wire _io_busy_resps_0_prs3_busy_T_2; // @[rename-busytable.scala:85:82] assign _io_busy_resps_0_prs3_busy_T_2 = _GEN_1; // @[rename-busytable.scala:63:56, :85:82] wire _io_busy_resps_1_prs1_busy_T_2; // @[rename-busytable.scala:79:82] assign _io_busy_resps_1_prs1_busy_T_2 = _GEN_1; // @[rename-busytable.scala:63:56, :79:82] wire _io_busy_resps_1_prs2_busy_T_2; // @[rename-busytable.scala:82:82] assign _io_busy_resps_1_prs2_busy_T_2 = _GEN_1; // @[rename-busytable.scala:63:56, :82:82] wire _io_busy_resps_1_prs3_busy_T_2; // @[rename-busytable.scala:85:82] assign _io_busy_resps_1_prs3_busy_T_2 = _GEN_1; // @[rename-busytable.scala:63:56, :85:82] wire [63:0] _busy_table_next_T_10 = {64{_busy_table_next_T_9}}; // @[rename-busytable.scala:63:{37,56}] wire [127:0] _busy_table_next_T_11 = {64'h0, _busy_table_next_T_8[63:0] & _busy_table_next_T_10}; // @[OneHot.scala:58:35] wire [127:0] _busy_table_next_T_16 = _busy_table_next_T_11; // @[rename-busytable.scala:63:31, :64:14] wire [127:0] busy_table_next = _busy_table_next_T_7 | _busy_table_next_T_16; // @[rename-busytable.scala:59:39, :62:5, :64:14] wire _prs1_match_T = wakeups_0_bits_uop_pdst == io_ren_uops_0_prs1_0; // @[rename-busytable.scala:27:7, :47:18, :70:68] wire prs1_match_0 = wakeups_0_valid & _prs1_match_T; // @[rename-busytable.scala:47:18, :70:{49,68}] wire _prs1_match_T_1 = wakeups_1_bits_uop_pdst == io_ren_uops_0_prs1_0; // @[rename-busytable.scala:27:7, :47:18, :70:68] wire prs1_match_1 = wakeups_1_valid & _prs1_match_T_1; // @[rename-busytable.scala:47:18, :70:{49,68}] wire _prs2_match_T = wakeups_0_bits_uop_pdst == io_ren_uops_0_prs2_0; // @[rename-busytable.scala:27:7, :47:18, :71:68] wire prs2_match_0 = wakeups_0_valid & _prs2_match_T; // @[rename-busytable.scala:47:18, :71:{49,68}] wire _prs2_match_T_1 = wakeups_1_bits_uop_pdst == io_ren_uops_0_prs2_0; // @[rename-busytable.scala:27:7, :47:18, :71:68] wire prs2_match_1 = wakeups_1_valid & _prs2_match_T_1; // @[rename-busytable.scala:47:18, :71:{49,68}] wire _prs3_match_T = wakeups_0_bits_uop_pdst == io_ren_uops_0_prs3_0; // @[rename-busytable.scala:27:7, :47:18, :72:68] wire prs3_match_0 = wakeups_0_valid & _prs3_match_T; // @[rename-busytable.scala:47:18, :72:{49,68}] wire _prs3_match_T_1 = wakeups_1_bits_uop_pdst == io_ren_uops_0_prs3_0; // @[rename-busytable.scala:27:7, :47:18, :72:68] wire prs3_match_1 = wakeups_1_valid & _prs3_match_T_1; // @[rename-busytable.scala:47:18, :72:{49,68}] wire [63:0] _io_busy_resps_0_prs1_busy_T = busy_table >> io_ren_uops_0_prs1_0; // @[rename-busytable.scala:27:7, :53:27, :74:45] wire _io_busy_resps_0_prs1_busy_T_1 = _io_busy_resps_0_prs1_busy_T[0]; // @[rename-busytable.scala:74:45] wire [63:0] _io_busy_resps_0_prs2_busy_T = busy_table >> io_ren_uops_0_prs2_0; // @[rename-busytable.scala:27:7, :53:27, :75:45] wire _io_busy_resps_0_prs2_busy_T_1 = _io_busy_resps_0_prs2_busy_T[0]; // @[rename-busytable.scala:75:45] wire [63:0] _io_busy_resps_0_prs3_busy_T = busy_table >> io_ren_uops_0_prs3_0; // @[rename-busytable.scala:27:7, :53:27, :76:45] wire _io_busy_resps_0_prs3_busy_T_1 = _io_busy_resps_0_prs3_busy_T[0]; // @[rename-busytable.scala:76:45] wire _io_busy_resps_0_prs1_busy_T_4 = prs1_match_0 & _io_busy_resps_0_prs1_busy_T_2; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs1_busy_T_6 = _io_busy_resps_0_prs1_busy_T_4; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs1_busy_WIRE = _io_busy_resps_0_prs1_busy_T_6; // @[Mux.scala:30:73] assign io_busy_resps_0_prs1_busy_0 = prs1_match_0 | prs1_match_1 ? _io_busy_resps_0_prs1_busy_WIRE : _io_busy_resps_0_prs1_busy_T_1; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs2_busy_T_4 = prs2_match_0 & _io_busy_resps_0_prs2_busy_T_2; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs2_busy_T_6 = _io_busy_resps_0_prs2_busy_T_4; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs2_busy_WIRE = _io_busy_resps_0_prs2_busy_T_6; // @[Mux.scala:30:73] assign io_busy_resps_0_prs2_busy_0 = prs2_match_0 | prs2_match_1 ? _io_busy_resps_0_prs2_busy_WIRE : _io_busy_resps_0_prs2_busy_T_1; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs3_busy_T_4 = prs3_match_0 & _io_busy_resps_0_prs3_busy_T_2; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs3_busy_T_6 = _io_busy_resps_0_prs3_busy_T_4; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs3_busy_WIRE = _io_busy_resps_0_prs3_busy_T_6; // @[Mux.scala:30:73] assign io_busy_resps_0_prs3_busy_0 = prs3_match_0 | prs3_match_1 ? _io_busy_resps_0_prs3_busy_WIRE : _io_busy_resps_0_prs3_busy_T_1; // @[Mux.scala:30:73] wire _prs1_match_T_2 = wakeups_0_bits_uop_pdst == io_ren_uops_1_prs1_0; // @[rename-busytable.scala:27:7, :47:18, :70:68] wire prs1_match_0_1 = wakeups_0_valid & _prs1_match_T_2; // @[rename-busytable.scala:47:18, :70:{49,68}] wire _prs1_match_T_3 = wakeups_1_bits_uop_pdst == io_ren_uops_1_prs1_0; // @[rename-busytable.scala:27:7, :47:18, :70:68] wire prs1_match_1_1 = wakeups_1_valid & _prs1_match_T_3; // @[rename-busytable.scala:47:18, :70:{49,68}] wire _prs2_match_T_2 = wakeups_0_bits_uop_pdst == io_ren_uops_1_prs2_0; // @[rename-busytable.scala:27:7, :47:18, :71:68] wire prs2_match_0_1 = wakeups_0_valid & _prs2_match_T_2; // @[rename-busytable.scala:47:18, :71:{49,68}] wire _prs2_match_T_3 = wakeups_1_bits_uop_pdst == io_ren_uops_1_prs2_0; // @[rename-busytable.scala:27:7, :47:18, :71:68] wire prs2_match_1_1 = wakeups_1_valid & _prs2_match_T_3; // @[rename-busytable.scala:47:18, :71:{49,68}] wire _prs3_match_T_2 = wakeups_0_bits_uop_pdst == io_ren_uops_1_prs3_0; // @[rename-busytable.scala:27:7, :47:18, :72:68] wire prs3_match_0_1 = wakeups_0_valid & _prs3_match_T_2; // @[rename-busytable.scala:47:18, :72:{49,68}] wire _prs3_match_T_3 = wakeups_1_bits_uop_pdst == io_ren_uops_1_prs3_0; // @[rename-busytable.scala:27:7, :47:18, :72:68] wire prs3_match_1_1 = wakeups_1_valid & _prs3_match_T_3; // @[rename-busytable.scala:47:18, :72:{49,68}] wire [63:0] _io_busy_resps_1_prs1_busy_T = busy_table >> io_ren_uops_1_prs1_0; // @[rename-busytable.scala:27:7, :53:27, :74:45] wire _io_busy_resps_1_prs1_busy_T_1 = _io_busy_resps_1_prs1_busy_T[0]; // @[rename-busytable.scala:74:45] wire [63:0] _io_busy_resps_1_prs2_busy_T = busy_table >> io_ren_uops_1_prs2_0; // @[rename-busytable.scala:27:7, :53:27, :75:45] wire _io_busy_resps_1_prs2_busy_T_1 = _io_busy_resps_1_prs2_busy_T[0]; // @[rename-busytable.scala:75:45] wire [63:0] _io_busy_resps_1_prs3_busy_T = busy_table >> io_ren_uops_1_prs3_0; // @[rename-busytable.scala:27:7, :53:27, :76:45] wire _io_busy_resps_1_prs3_busy_T_1 = _io_busy_resps_1_prs3_busy_T[0]; // @[rename-busytable.scala:76:45] wire _io_busy_resps_1_prs1_busy_T_4 = prs1_match_0_1 & _io_busy_resps_1_prs1_busy_T_2; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs1_busy_T_6 = _io_busy_resps_1_prs1_busy_T_4; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs1_busy_WIRE = _io_busy_resps_1_prs1_busy_T_6; // @[Mux.scala:30:73] assign io_busy_resps_1_prs1_busy_0 = prs1_match_0_1 | prs1_match_1_1 ? _io_busy_resps_1_prs1_busy_WIRE : _io_busy_resps_1_prs1_busy_T_1; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs2_busy_T_4 = prs2_match_0_1 & _io_busy_resps_1_prs2_busy_T_2; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs2_busy_T_6 = _io_busy_resps_1_prs2_busy_T_4; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs2_busy_WIRE = _io_busy_resps_1_prs2_busy_T_6; // @[Mux.scala:30:73] assign io_busy_resps_1_prs2_busy_0 = prs2_match_0_1 | prs2_match_1_1 ? _io_busy_resps_1_prs2_busy_WIRE : _io_busy_resps_1_prs2_busy_T_1; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs3_busy_T_4 = prs3_match_0_1 & _io_busy_resps_1_prs3_busy_T_2; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs3_busy_T_6 = _io_busy_resps_1_prs3_busy_T_4; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs3_busy_WIRE = _io_busy_resps_1_prs3_busy_T_6; // @[Mux.scala:30:73] assign io_busy_resps_1_prs3_busy_0 = prs3_match_0_1 | prs3_match_1_1 ? _io_busy_resps_1_prs3_busy_WIRE : _io_busy_resps_1_prs3_busy_T_1; // @[Mux.scala:30:73] always @(posedge clock) begin // @[rename-busytable.scala:27:7] wakeups_wu_valid_REG <= io_wakeups_0_valid_0; // @[rename-busytable.scala:27:7, :48:24] wakeups_wu_valid_REG_1 <= 2'h0; // @[rename-busytable.scala:48:46] wakeups_wu_bits_REG_uop_inst <= io_wakeups_0_bits_uop_inst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_debug_inst <= io_wakeups_0_bits_uop_debug_inst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_is_rvc <= io_wakeups_0_bits_uop_is_rvc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_debug_pc <= io_wakeups_0_bits_uop_debug_pc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_iq_type_0 <= io_wakeups_0_bits_uop_iq_type_0_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_iq_type_1 <= io_wakeups_0_bits_uop_iq_type_1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_iq_type_2 <= io_wakeups_0_bits_uop_iq_type_2_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_iq_type_3 <= io_wakeups_0_bits_uop_iq_type_3_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fu_code_0 <= io_wakeups_0_bits_uop_fu_code_0_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fu_code_1 <= io_wakeups_0_bits_uop_fu_code_1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fu_code_2 <= io_wakeups_0_bits_uop_fu_code_2_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fu_code_3 <= io_wakeups_0_bits_uop_fu_code_3_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fu_code_4 <= io_wakeups_0_bits_uop_fu_code_4_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fu_code_5 <= io_wakeups_0_bits_uop_fu_code_5_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fu_code_6 <= io_wakeups_0_bits_uop_fu_code_6_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fu_code_7 <= io_wakeups_0_bits_uop_fu_code_7_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fu_code_8 <= io_wakeups_0_bits_uop_fu_code_8_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fu_code_9 <= io_wakeups_0_bits_uop_fu_code_9_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_iw_issued <= io_wakeups_0_bits_uop_iw_issued_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_iw_issued_partial_agen <= io_wakeups_0_bits_uop_iw_issued_partial_agen_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_iw_issued_partial_dgen <= io_wakeups_0_bits_uop_iw_issued_partial_dgen_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_iw_p1_speculative_child <= io_wakeups_0_bits_uop_iw_p1_speculative_child_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_iw_p2_speculative_child <= io_wakeups_0_bits_uop_iw_p2_speculative_child_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_iw_p1_bypass_hint <= io_wakeups_0_bits_uop_iw_p1_bypass_hint_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_iw_p2_bypass_hint <= io_wakeups_0_bits_uop_iw_p2_bypass_hint_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_iw_p3_bypass_hint <= io_wakeups_0_bits_uop_iw_p3_bypass_hint_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_dis_col_sel <= io_wakeups_0_bits_uop_dis_col_sel_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_br_mask <= io_wakeups_0_bits_uop_br_mask_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_br_tag <= io_wakeups_0_bits_uop_br_tag_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_br_type <= io_wakeups_0_bits_uop_br_type_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_is_sfb <= io_wakeups_0_bits_uop_is_sfb_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_is_fence <= io_wakeups_0_bits_uop_is_fence_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_is_fencei <= io_wakeups_0_bits_uop_is_fencei_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_is_sfence <= io_wakeups_0_bits_uop_is_sfence_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_is_amo <= io_wakeups_0_bits_uop_is_amo_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_is_eret <= io_wakeups_0_bits_uop_is_eret_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_is_sys_pc2epc <= io_wakeups_0_bits_uop_is_sys_pc2epc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_is_rocc <= io_wakeups_0_bits_uop_is_rocc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_is_mov <= io_wakeups_0_bits_uop_is_mov_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_ftq_idx <= io_wakeups_0_bits_uop_ftq_idx_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_edge_inst <= io_wakeups_0_bits_uop_edge_inst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_pc_lob <= io_wakeups_0_bits_uop_pc_lob_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_taken <= io_wakeups_0_bits_uop_taken_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_imm_rename <= io_wakeups_0_bits_uop_imm_rename_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_imm_sel <= io_wakeups_0_bits_uop_imm_sel_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_pimm <= io_wakeups_0_bits_uop_pimm_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_imm_packed <= io_wakeups_0_bits_uop_imm_packed_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_op1_sel <= io_wakeups_0_bits_uop_op1_sel_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_op2_sel <= io_wakeups_0_bits_uop_op2_sel_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_ctrl_ldst <= io_wakeups_0_bits_uop_fp_ctrl_ldst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_ctrl_wen <= io_wakeups_0_bits_uop_fp_ctrl_wen_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_ctrl_ren1 <= io_wakeups_0_bits_uop_fp_ctrl_ren1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_ctrl_ren2 <= io_wakeups_0_bits_uop_fp_ctrl_ren2_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_ctrl_ren3 <= io_wakeups_0_bits_uop_fp_ctrl_ren3_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_ctrl_swap12 <= io_wakeups_0_bits_uop_fp_ctrl_swap12_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_ctrl_swap23 <= io_wakeups_0_bits_uop_fp_ctrl_swap23_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_ctrl_typeTagIn <= io_wakeups_0_bits_uop_fp_ctrl_typeTagIn_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_ctrl_typeTagOut <= io_wakeups_0_bits_uop_fp_ctrl_typeTagOut_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_ctrl_fromint <= io_wakeups_0_bits_uop_fp_ctrl_fromint_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_ctrl_toint <= io_wakeups_0_bits_uop_fp_ctrl_toint_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_ctrl_fastpipe <= io_wakeups_0_bits_uop_fp_ctrl_fastpipe_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_ctrl_fma <= io_wakeups_0_bits_uop_fp_ctrl_fma_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_ctrl_div <= io_wakeups_0_bits_uop_fp_ctrl_div_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_ctrl_sqrt <= io_wakeups_0_bits_uop_fp_ctrl_sqrt_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_ctrl_wflags <= io_wakeups_0_bits_uop_fp_ctrl_wflags_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_ctrl_vec <= io_wakeups_0_bits_uop_fp_ctrl_vec_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_rob_idx <= io_wakeups_0_bits_uop_rob_idx_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_ldq_idx <= io_wakeups_0_bits_uop_ldq_idx_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_stq_idx <= io_wakeups_0_bits_uop_stq_idx_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_rxq_idx <= io_wakeups_0_bits_uop_rxq_idx_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_pdst <= io_wakeups_0_bits_uop_pdst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_prs1 <= io_wakeups_0_bits_uop_prs1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_prs2 <= io_wakeups_0_bits_uop_prs2_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_prs3 <= io_wakeups_0_bits_uop_prs3_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_ppred <= io_wakeups_0_bits_uop_ppred_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_prs1_busy <= io_wakeups_0_bits_uop_prs1_busy_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_prs2_busy <= io_wakeups_0_bits_uop_prs2_busy_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_prs3_busy <= io_wakeups_0_bits_uop_prs3_busy_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_ppred_busy <= io_wakeups_0_bits_uop_ppred_busy_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_stale_pdst <= io_wakeups_0_bits_uop_stale_pdst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_exception <= io_wakeups_0_bits_uop_exception_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_exc_cause <= io_wakeups_0_bits_uop_exc_cause_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_mem_cmd <= io_wakeups_0_bits_uop_mem_cmd_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_mem_size <= io_wakeups_0_bits_uop_mem_size_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_mem_signed <= io_wakeups_0_bits_uop_mem_signed_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_uses_ldq <= io_wakeups_0_bits_uop_uses_ldq_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_uses_stq <= io_wakeups_0_bits_uop_uses_stq_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_is_unique <= io_wakeups_0_bits_uop_is_unique_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_flush_on_commit <= io_wakeups_0_bits_uop_flush_on_commit_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_csr_cmd <= io_wakeups_0_bits_uop_csr_cmd_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_ldst_is_rs1 <= io_wakeups_0_bits_uop_ldst_is_rs1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_ldst <= io_wakeups_0_bits_uop_ldst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_lrs1 <= io_wakeups_0_bits_uop_lrs1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_lrs2 <= io_wakeups_0_bits_uop_lrs2_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_lrs3 <= io_wakeups_0_bits_uop_lrs3_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_dst_rtype <= io_wakeups_0_bits_uop_dst_rtype_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_lrs1_rtype <= io_wakeups_0_bits_uop_lrs1_rtype_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_lrs2_rtype <= io_wakeups_0_bits_uop_lrs2_rtype_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_frs3_en <= io_wakeups_0_bits_uop_frs3_en_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fcn_dw <= io_wakeups_0_bits_uop_fcn_dw_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fcn_op <= io_wakeups_0_bits_uop_fcn_op_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_val <= io_wakeups_0_bits_uop_fp_val_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_rm <= io_wakeups_0_bits_uop_fp_rm_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_typ <= io_wakeups_0_bits_uop_fp_typ_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_xcpt_pf_if <= io_wakeups_0_bits_uop_xcpt_pf_if_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_xcpt_ae_if <= io_wakeups_0_bits_uop_xcpt_ae_if_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_xcpt_ma_if <= io_wakeups_0_bits_uop_xcpt_ma_if_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_bp_debug_if <= io_wakeups_0_bits_uop_bp_debug_if_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_bp_xcpt_if <= io_wakeups_0_bits_uop_bp_xcpt_if_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_debug_fsrc <= io_wakeups_0_bits_uop_debug_fsrc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_debug_tsrc <= io_wakeups_0_bits_uop_debug_tsrc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_bypassable <= 1'h1; // @[rename-busytable.scala:49:24] wakeups_wu_bits_REG_speculative_mask <= 2'h0; // @[rename-busytable.scala:49:24] wakeups_wu_bits_REG_rebusy <= 1'h0; // @[rename-busytable.scala:49:24] wakeups_wu_valid_REG_2 <= io_wakeups_1_valid_0; // @[rename-busytable.scala:27:7, :48:24] wakeups_wu_bits_REG_1_uop_inst <= io_wakeups_1_bits_uop_inst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_debug_inst <= io_wakeups_1_bits_uop_debug_inst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_is_rvc <= io_wakeups_1_bits_uop_is_rvc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_debug_pc <= io_wakeups_1_bits_uop_debug_pc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_iq_type_0 <= io_wakeups_1_bits_uop_iq_type_0_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_iq_type_1 <= io_wakeups_1_bits_uop_iq_type_1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_iq_type_2 <= io_wakeups_1_bits_uop_iq_type_2_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_iq_type_3 <= io_wakeups_1_bits_uop_iq_type_3_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fu_code_0 <= io_wakeups_1_bits_uop_fu_code_0_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fu_code_1 <= io_wakeups_1_bits_uop_fu_code_1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fu_code_2 <= io_wakeups_1_bits_uop_fu_code_2_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fu_code_3 <= io_wakeups_1_bits_uop_fu_code_3_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fu_code_4 <= io_wakeups_1_bits_uop_fu_code_4_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fu_code_5 <= io_wakeups_1_bits_uop_fu_code_5_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fu_code_6 <= io_wakeups_1_bits_uop_fu_code_6_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fu_code_7 <= io_wakeups_1_bits_uop_fu_code_7_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fu_code_8 <= io_wakeups_1_bits_uop_fu_code_8_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fu_code_9 <= io_wakeups_1_bits_uop_fu_code_9_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_iw_issued <= io_wakeups_1_bits_uop_iw_issued_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_iw_issued_partial_agen <= io_wakeups_1_bits_uop_iw_issued_partial_agen_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_iw_issued_partial_dgen <= io_wakeups_1_bits_uop_iw_issued_partial_dgen_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_iw_p1_speculative_child <= io_wakeups_1_bits_uop_iw_p1_speculative_child_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_iw_p2_speculative_child <= io_wakeups_1_bits_uop_iw_p2_speculative_child_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_iw_p1_bypass_hint <= io_wakeups_1_bits_uop_iw_p1_bypass_hint_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_iw_p2_bypass_hint <= io_wakeups_1_bits_uop_iw_p2_bypass_hint_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_iw_p3_bypass_hint <= io_wakeups_1_bits_uop_iw_p3_bypass_hint_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_dis_col_sel <= io_wakeups_1_bits_uop_dis_col_sel_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_br_mask <= io_wakeups_1_bits_uop_br_mask_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_br_tag <= io_wakeups_1_bits_uop_br_tag_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_br_type <= io_wakeups_1_bits_uop_br_type_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_is_sfb <= io_wakeups_1_bits_uop_is_sfb_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_is_fence <= io_wakeups_1_bits_uop_is_fence_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_is_fencei <= io_wakeups_1_bits_uop_is_fencei_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_is_sfence <= io_wakeups_1_bits_uop_is_sfence_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_is_amo <= io_wakeups_1_bits_uop_is_amo_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_is_eret <= io_wakeups_1_bits_uop_is_eret_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_is_sys_pc2epc <= io_wakeups_1_bits_uop_is_sys_pc2epc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_is_rocc <= io_wakeups_1_bits_uop_is_rocc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_is_mov <= io_wakeups_1_bits_uop_is_mov_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_ftq_idx <= io_wakeups_1_bits_uop_ftq_idx_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_edge_inst <= io_wakeups_1_bits_uop_edge_inst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_pc_lob <= io_wakeups_1_bits_uop_pc_lob_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_taken <= io_wakeups_1_bits_uop_taken_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_imm_rename <= io_wakeups_1_bits_uop_imm_rename_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_imm_sel <= io_wakeups_1_bits_uop_imm_sel_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_pimm <= io_wakeups_1_bits_uop_pimm_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_imm_packed <= io_wakeups_1_bits_uop_imm_packed_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_op1_sel <= io_wakeups_1_bits_uop_op1_sel_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_op2_sel <= io_wakeups_1_bits_uop_op2_sel_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_ctrl_ldst <= io_wakeups_1_bits_uop_fp_ctrl_ldst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_ctrl_wen <= io_wakeups_1_bits_uop_fp_ctrl_wen_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_ctrl_ren1 <= io_wakeups_1_bits_uop_fp_ctrl_ren1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_ctrl_ren2 <= io_wakeups_1_bits_uop_fp_ctrl_ren2_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_ctrl_ren3 <= io_wakeups_1_bits_uop_fp_ctrl_ren3_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_ctrl_swap12 <= io_wakeups_1_bits_uop_fp_ctrl_swap12_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_ctrl_swap23 <= io_wakeups_1_bits_uop_fp_ctrl_swap23_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_ctrl_typeTagIn <= io_wakeups_1_bits_uop_fp_ctrl_typeTagIn_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_ctrl_typeTagOut <= io_wakeups_1_bits_uop_fp_ctrl_typeTagOut_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_ctrl_fromint <= io_wakeups_1_bits_uop_fp_ctrl_fromint_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_ctrl_toint <= io_wakeups_1_bits_uop_fp_ctrl_toint_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_ctrl_fastpipe <= io_wakeups_1_bits_uop_fp_ctrl_fastpipe_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_ctrl_fma <= io_wakeups_1_bits_uop_fp_ctrl_fma_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_ctrl_div <= io_wakeups_1_bits_uop_fp_ctrl_div_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_ctrl_sqrt <= io_wakeups_1_bits_uop_fp_ctrl_sqrt_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_ctrl_wflags <= io_wakeups_1_bits_uop_fp_ctrl_wflags_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_ctrl_vec <= io_wakeups_1_bits_uop_fp_ctrl_vec_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_rob_idx <= io_wakeups_1_bits_uop_rob_idx_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_ldq_idx <= io_wakeups_1_bits_uop_ldq_idx_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_stq_idx <= io_wakeups_1_bits_uop_stq_idx_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_rxq_idx <= io_wakeups_1_bits_uop_rxq_idx_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_pdst <= io_wakeups_1_bits_uop_pdst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_prs1 <= io_wakeups_1_bits_uop_prs1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_prs2 <= io_wakeups_1_bits_uop_prs2_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_prs3 <= io_wakeups_1_bits_uop_prs3_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_ppred <= io_wakeups_1_bits_uop_ppred_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_prs1_busy <= io_wakeups_1_bits_uop_prs1_busy_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_prs2_busy <= io_wakeups_1_bits_uop_prs2_busy_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_prs3_busy <= io_wakeups_1_bits_uop_prs3_busy_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_ppred_busy <= io_wakeups_1_bits_uop_ppred_busy_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_stale_pdst <= io_wakeups_1_bits_uop_stale_pdst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_exception <= io_wakeups_1_bits_uop_exception_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_exc_cause <= io_wakeups_1_bits_uop_exc_cause_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_mem_cmd <= io_wakeups_1_bits_uop_mem_cmd_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_mem_size <= io_wakeups_1_bits_uop_mem_size_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_mem_signed <= io_wakeups_1_bits_uop_mem_signed_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_uses_ldq <= io_wakeups_1_bits_uop_uses_ldq_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_uses_stq <= io_wakeups_1_bits_uop_uses_stq_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_is_unique <= io_wakeups_1_bits_uop_is_unique_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_flush_on_commit <= io_wakeups_1_bits_uop_flush_on_commit_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_csr_cmd <= io_wakeups_1_bits_uop_csr_cmd_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_ldst_is_rs1 <= io_wakeups_1_bits_uop_ldst_is_rs1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_ldst <= io_wakeups_1_bits_uop_ldst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_lrs1 <= io_wakeups_1_bits_uop_lrs1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_lrs2 <= io_wakeups_1_bits_uop_lrs2_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_lrs3 <= io_wakeups_1_bits_uop_lrs3_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_dst_rtype <= io_wakeups_1_bits_uop_dst_rtype_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_lrs1_rtype <= io_wakeups_1_bits_uop_lrs1_rtype_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_lrs2_rtype <= io_wakeups_1_bits_uop_lrs2_rtype_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_frs3_en <= io_wakeups_1_bits_uop_frs3_en_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fcn_dw <= io_wakeups_1_bits_uop_fcn_dw_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fcn_op <= io_wakeups_1_bits_uop_fcn_op_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_val <= io_wakeups_1_bits_uop_fp_val_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_rm <= io_wakeups_1_bits_uop_fp_rm_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_typ <= io_wakeups_1_bits_uop_fp_typ_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_xcpt_pf_if <= io_wakeups_1_bits_uop_xcpt_pf_if_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_xcpt_ae_if <= io_wakeups_1_bits_uop_xcpt_ae_if_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_xcpt_ma_if <= io_wakeups_1_bits_uop_xcpt_ma_if_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_bp_debug_if <= io_wakeups_1_bits_uop_bp_debug_if_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_bp_xcpt_if <= io_wakeups_1_bits_uop_bp_xcpt_if_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_debug_fsrc <= io_wakeups_1_bits_uop_debug_fsrc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_debug_tsrc <= io_wakeups_1_bits_uop_debug_tsrc_0; // @[rename-busytable.scala:27:7, :49:24] if (reset) // @[rename-busytable.scala:27:7] busy_table <= 64'h0; // @[rename-busytable.scala:53:27] else // @[rename-busytable.scala:27:7] busy_table <= busy_table_next[63:0]; // @[rename-busytable.scala:53:27, :62:5, :66:14] always @(posedge) assign io_busy_resps_0_prs1_busy = io_busy_resps_0_prs1_busy_0; // @[rename-busytable.scala:27:7] assign io_busy_resps_0_prs2_busy = io_busy_resps_0_prs2_busy_0; // @[rename-busytable.scala:27:7] assign io_busy_resps_0_prs3_busy = io_busy_resps_0_prs3_busy_0; // @[rename-busytable.scala:27:7] assign io_busy_resps_1_prs1_busy = io_busy_resps_1_prs1_busy_0; // @[rename-busytable.scala:27:7] assign io_busy_resps_1_prs2_busy = io_busy_resps_1_prs2_busy_0; // @[rename-busytable.scala:27:7] assign io_busy_resps_1_prs3_busy = io_busy_resps_1_prs3_busy_0; // @[rename-busytable.scala:27:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_396 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_140 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<32>, clock reg c2 : SInt<32>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node c1_sign = bits(io.in_d, 19, 19) node c1_lo_lo_hi = cat(c1_sign, c1_sign) node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign) node c1_lo_hi_hi = cat(c1_sign, c1_sign) node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign) node c1_lo = cat(c1_lo_hi, c1_lo_lo) node c1_hi_lo_hi = cat(c1_sign, c1_sign) node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign) node c1_hi_hi_hi = cat(c1_sign, c1_sign) node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign) node c1_hi = cat(c1_hi_hi, c1_hi_lo) node _c1_T = cat(c1_hi, c1_lo) node c1_lo_1 = asUInt(io.in_d) node _c1_T_1 = cat(_c1_T, c1_lo_1) wire _c1_WIRE : SInt<32> node _c1_T_2 = asSInt(_c1_T_1) connect _c1_WIRE, _c1_T_2 connect c1, _c1_WIRE else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node c2_sign = bits(io.in_d, 19, 19) node c2_lo_lo_hi = cat(c2_sign, c2_sign) node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign) node c2_lo_hi_hi = cat(c2_sign, c2_sign) node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign) node c2_lo = cat(c2_lo_hi, c2_lo_lo) node c2_hi_lo_hi = cat(c2_sign, c2_sign) node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign) node c2_hi_hi_hi = cat(c2_sign, c2_sign) node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign) node c2_hi = cat(c2_hi_hi, c2_hi_lo) node _c2_T = cat(c2_hi, c2_lo) node c2_lo_1 = asUInt(io.in_d) node _c2_T_1 = cat(_c2_T, c2_lo_1) wire _c2_WIRE : SInt<32> node _c2_T_2 = asSInt(_c2_T_1) connect _c2_WIRE, _c2_T_2 connect c2, _c2_WIRE else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h1), _T_4) node _T_6 = or(UInt<1>(0h0), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c
module PE_396( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_140 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_135 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_227 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0
module AsyncResetSynchronizerShiftReg_w1_d3_i0_135( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_227 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_61 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0) node _source_ok_T = shr(io.in.a.bits.source, 11) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits = bits(_uncommonBits_T, 10, 0) node _T_4 = shr(io.in.a.bits.source, 11) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<11>(0h40f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0) node _T_24 = shr(io.in.a.bits.source, 11) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<14>(0h2200)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<9>(0h100))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<14>(0h2200)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<9>(0h100))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0) node _T_86 = shr(io.in.a.bits.source, 11) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<14>(0h2200)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<9>(0h100))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<14>(0h2200)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<9>(0h100))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0) node _T_152 = shr(io.in.a.bits.source, 11) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<14>(0h2200)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<9>(0h100))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0) node _T_199 = shr(io.in.a.bits.source, 11) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<14>(0h2200)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<9>(0h100))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0) node _T_240 = shr(io.in.a.bits.source, 11) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<11>(0h40f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<14>(0h2200)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<9>(0h100))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0) node _T_283 = shr(io.in.a.bits.source, 11) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<11>(0h40f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<14>(0h2200)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<9>(0h100))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0) node _T_321 = shr(io.in.a.bits.source, 11) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<11>(0h40f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<14>(0h2200)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<9>(0h100))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0) node _T_359 = shr(io.in.a.bits.source, 11) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<11>(0h40f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<14>(0h2200)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<9>(0h100))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 11) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<14>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<14>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1040> connect a_set, UInt<1040>(0h0) wire a_set_wo_ready : UInt<1040> connect a_set_wo_ready, UInt<1040>(0h0) wire a_opcodes_set : UInt<4160> connect a_opcodes_set, UInt<4160>(0h0) wire a_sizes_set : UInt<4160> connect a_sizes_set, UInt<4160>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1040> connect d_clr, UInt<1040>(0h0) wire d_clr_wo_ready : UInt<1040> connect d_clr_wo_ready, UInt<1040>(0h0) wire d_opcodes_clr : UInt<4160> connect d_opcodes_clr, UInt<4160>(0h0) wire d_sizes_clr : UInt<4160> connect d_sizes_clr, UInt<4160>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_125 node _T_656 = orr(inflight) node _T_657 = eq(_T_656, UInt<1>(0h0)) node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_659 = or(_T_657, _T_658) node _T_660 = lt(watchdog, plusarg_reader.out) node _T_661 = or(_T_659, _T_660) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_661, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_665 = and(io.in.a.ready, io.in.a.valid) node _T_666 = and(io.in.d.ready, io.in.d.valid) node _T_667 = or(_T_665, _T_666) when _T_667 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<14>(0h0) connect _c_first_WIRE.bits.source, UInt<11>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<14>(0h0) connect _c_first_WIRE_2.bits.source, UInt<11>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1040> connect c_set, UInt<1040>(0h0) wire c_set_wo_ready : UInt<1040> connect c_set_wo_ready, UInt<1040>(0h0) wire c_opcodes_set : UInt<4160> connect c_opcodes_set, UInt<4160>(0h0) wire c_sizes_set : UInt<4160> connect c_sizes_set, UInt<4160>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<14>(0h0) connect _WIRE_6.bits.source, UInt<11>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_668 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<14>(0h0) connect _WIRE_8.bits.source, UInt<11>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_671 = and(_T_669, _T_670) node _T_672 = and(_T_668, _T_671) when _T_672 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<14>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<14>(0h0) connect _WIRE_10.bits.source, UInt<11>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_674 = and(_T_673, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<14>(0h0) connect _WIRE_12.bits.source, UInt<11>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_677 = and(_T_675, _T_676) node _T_678 = and(_T_674, _T_677) when _T_678 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<14>(0h0) connect _c_set_WIRE.bits.source, UInt<11>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<14>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<14>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<14>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<14>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<14>(0h0) connect _WIRE_14.bits.source, UInt<11>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_679 = dshr(inflight_1, _WIRE_15.bits.source) node _T_680 = bits(_T_679, 0, 0) node _T_681 = eq(_T_680, UInt<1>(0h0)) node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(_T_681, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_681, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<14>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<14>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1040> connect d_clr_1, UInt<1040>(0h0) wire d_clr_wo_ready_1 : UInt<1040> connect d_clr_wo_ready_1, UInt<1040>(0h0) wire d_opcodes_clr_1 : UInt<4160> connect d_opcodes_clr_1, UInt<4160>(0h0) wire d_sizes_clr_1 : UInt<4160> connect d_sizes_clr_1, UInt<4160>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_688 = and(io.in.d.ready, io.in.d.valid) node _T_689 = and(_T_688, d_first_2) node _T_690 = and(_T_689, UInt<1>(0h1)) node _T_691 = and(_T_690, d_release_ack_1) when _T_691 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_695 = dshr(inflight_1, io.in.d.bits.source) node _T_696 = bits(_T_695, 0, 0) node _T_697 = or(_T_696, same_cycle_resp_1) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_697, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<14>(0h0) connect _WIRE_16.bits.source, UInt<11>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_701, UInt<1>(0h1), "") : assert_108 else : node _T_705 = eq(io.in.d.bits.size, c_size_lookup) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_705, UInt<1>(0h1), "") : assert_109 node _T_709 = and(io.in.d.valid, d_first_2) node _T_710 = and(_T_709, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<14>(0h0) connect _WIRE_18.bits.source, UInt<11>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_711 = and(_T_710, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<14>(0h0) connect _WIRE_20.bits.source, UInt<11>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_713 = and(_T_711, _T_712) node _T_714 = and(_T_713, d_release_ack_1) node _T_715 = eq(c_probe_ack, UInt<1>(0h0)) node _T_716 = and(_T_714, _T_715) when _T_716 : node _T_717 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<14>(0h0) connect _WIRE_22.bits.source, UInt<11>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_718 = or(_T_717, _WIRE_23.ready) node _T_719 = asUInt(reset) node _T_720 = eq(_T_719, UInt<1>(0h0)) when _T_720 : node _T_721 = eq(_T_718, UInt<1>(0h0)) when _T_721 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_718, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_126 node _T_722 = orr(inflight_1) node _T_723 = eq(_T_722, UInt<1>(0h0)) node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_725 = or(_T_723, _T_724) node _T_726 = lt(watchdog_1, plusarg_reader_1.out) node _T_727 = or(_T_725, _T_726) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at tools/rocket-dsp-utils/src/main/scala/dspblocks/HierarchicalBlock.scala:54:23)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_727, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<14>(0h0) connect _WIRE_24.bits.source, UInt<11>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_732 = and(io.in.d.ready, io.in.d.valid) node _T_733 = or(_T_731, _T_732) when _T_733 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_61( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [13:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [13:0] address; // @[Monitor.scala:391:22] reg d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] reg a_first_counter_1; // @[Edges.scala:229:27] reg d_first_counter_1; // @[Edges.scala:229:27] wire _GEN = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg d_first_counter_2; // @[Edges.scala:229:27] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_35 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0) node _source_ok_T = shr(io.in.a.bits.source, 4) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0h9)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits = bits(_uncommonBits_T, 3, 0) node _T_4 = shr(io.in.a.bits.source, 4) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<4>(0h9)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<9>(0hc0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0) node _T_24 = shr(io.in.a.bits.source, 4) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<4>(0h9)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<29>(0h10000000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = or(_T_37, _T_42) node _T_44 = and(_T_32, _T_43) node _T_45 = or(UInt<1>(0h0), _T_44) node _T_46 = and(_T_31, _T_45) node _T_47 = asUInt(reset) node _T_48 = eq(_T_47, UInt<1>(0h0)) when _T_48 : node _T_49 = eq(_T_46, UInt<1>(0h0)) when _T_49 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_46, UInt<1>(0h1), "") : assert_2 node _T_50 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_51 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_52 = and(_T_50, _T_51) node _T_53 = or(UInt<1>(0h0), _T_52) node _T_54 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_55 = cvt(_T_54) node _T_56 = and(_T_55, asSInt(UInt<17>(0h10000))) node _T_57 = asSInt(_T_56) node _T_58 = eq(_T_57, asSInt(UInt<1>(0h0))) node _T_59 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_60 = cvt(_T_59) node _T_61 = and(_T_60, asSInt(UInt<29>(0h10000000))) node _T_62 = asSInt(_T_61) node _T_63 = eq(_T_62, asSInt(UInt<1>(0h0))) node _T_64 = or(_T_58, _T_63) node _T_65 = and(_T_53, _T_64) node _T_66 = or(UInt<1>(0h0), _T_65) node _T_67 = and(UInt<1>(0h0), _T_66) node _T_68 = asUInt(reset) node _T_69 = eq(_T_68, UInt<1>(0h0)) when _T_69 : node _T_70 = eq(_T_67, UInt<1>(0h0)) when _T_70 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_67, UInt<1>(0h1), "") : assert_3 node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_74 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_74, UInt<1>(0h1), "") : assert_5 node _T_78 = asUInt(reset) node _T_79 = eq(_T_78, UInt<1>(0h0)) when _T_79 : node _T_80 = eq(is_aligned, UInt<1>(0h0)) when _T_80 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_81 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_82 = asUInt(reset) node _T_83 = eq(_T_82, UInt<1>(0h0)) when _T_83 : node _T_84 = eq(_T_81, UInt<1>(0h0)) when _T_84 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_81, UInt<1>(0h1), "") : assert_7 node _T_85 = not(io.in.a.bits.mask) node _T_86 = eq(_T_85, UInt<1>(0h0)) node _T_87 = asUInt(reset) node _T_88 = eq(_T_87, UInt<1>(0h0)) when _T_88 : node _T_89 = eq(_T_86, UInt<1>(0h0)) when _T_89 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_86, UInt<1>(0h1), "") : assert_8 node _T_90 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_91 = asUInt(reset) node _T_92 = eq(_T_91, UInt<1>(0h0)) when _T_92 : node _T_93 = eq(_T_90, UInt<1>(0h0)) when _T_93 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_90, UInt<1>(0h1), "") : assert_9 node _T_94 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_94 : node _T_95 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_96 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_97 = and(_T_95, _T_96) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0) node _T_98 = shr(io.in.a.bits.source, 4) node _T_99 = eq(_T_98, UInt<1>(0h0)) node _T_100 = leq(UInt<1>(0h0), uncommonBits_2) node _T_101 = and(_T_99, _T_100) node _T_102 = leq(uncommonBits_2, UInt<4>(0h9)) node _T_103 = and(_T_101, _T_102) node _T_104 = and(_T_97, _T_103) node _T_105 = or(UInt<1>(0h0), _T_104) node _T_106 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_107 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_108 = cvt(_T_107) node _T_109 = and(_T_108, asSInt(UInt<17>(0h10000))) node _T_110 = asSInt(_T_109) node _T_111 = eq(_T_110, asSInt(UInt<1>(0h0))) node _T_112 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_113 = cvt(_T_112) node _T_114 = and(_T_113, asSInt(UInt<29>(0h10000000))) node _T_115 = asSInt(_T_114) node _T_116 = eq(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = or(_T_111, _T_116) node _T_118 = and(_T_106, _T_117) node _T_119 = or(UInt<1>(0h0), _T_118) node _T_120 = and(_T_105, _T_119) node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_T_120, UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_120, UInt<1>(0h1), "") : assert_10 node _T_124 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_125 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_126 = and(_T_124, _T_125) node _T_127 = or(UInt<1>(0h0), _T_126) node _T_128 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_129 = cvt(_T_128) node _T_130 = and(_T_129, asSInt(UInt<17>(0h10000))) node _T_131 = asSInt(_T_130) node _T_132 = eq(_T_131, asSInt(UInt<1>(0h0))) node _T_133 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_134 = cvt(_T_133) node _T_135 = and(_T_134, asSInt(UInt<29>(0h10000000))) node _T_136 = asSInt(_T_135) node _T_137 = eq(_T_136, asSInt(UInt<1>(0h0))) node _T_138 = or(_T_132, _T_137) node _T_139 = and(_T_127, _T_138) node _T_140 = or(UInt<1>(0h0), _T_139) node _T_141 = and(UInt<1>(0h0), _T_140) node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : node _T_144 = eq(_T_141, UInt<1>(0h0)) when _T_144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_141, UInt<1>(0h1), "") : assert_11 node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_148 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_T_148, UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_148, UInt<1>(0h1), "") : assert_13 node _T_152 = asUInt(reset) node _T_153 = eq(_T_152, UInt<1>(0h0)) when _T_153 : node _T_154 = eq(is_aligned, UInt<1>(0h0)) when _T_154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_155 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_155, UInt<1>(0h1), "") : assert_15 node _T_159 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_159, UInt<1>(0h1), "") : assert_16 node _T_163 = not(io.in.a.bits.mask) node _T_164 = eq(_T_163, UInt<1>(0h0)) node _T_165 = asUInt(reset) node _T_166 = eq(_T_165, UInt<1>(0h0)) when _T_166 : node _T_167 = eq(_T_164, UInt<1>(0h0)) when _T_167 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_164, UInt<1>(0h1), "") : assert_17 node _T_168 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_169 = asUInt(reset) node _T_170 = eq(_T_169, UInt<1>(0h0)) when _T_170 : node _T_171 = eq(_T_168, UInt<1>(0h0)) when _T_171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_168, UInt<1>(0h1), "") : assert_18 node _T_172 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_172 : node _T_173 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_174 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_175 = and(_T_173, _T_174) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0) node _T_176 = shr(io.in.a.bits.source, 4) node _T_177 = eq(_T_176, UInt<1>(0h0)) node _T_178 = leq(UInt<1>(0h0), uncommonBits_3) node _T_179 = and(_T_177, _T_178) node _T_180 = leq(uncommonBits_3, UInt<4>(0h9)) node _T_181 = and(_T_179, _T_180) node _T_182 = and(_T_175, _T_181) node _T_183 = or(UInt<1>(0h0), _T_182) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_183, UInt<1>(0h1), "") : assert_19 node _T_187 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_188 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_189 = and(_T_187, _T_188) node _T_190 = or(UInt<1>(0h0), _T_189) node _T_191 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_192 = cvt(_T_191) node _T_193 = and(_T_192, asSInt(UInt<17>(0h10000))) node _T_194 = asSInt(_T_193) node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0))) node _T_196 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_197 = cvt(_T_196) node _T_198 = and(_T_197, asSInt(UInt<29>(0h10000000))) node _T_199 = asSInt(_T_198) node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0))) node _T_201 = or(_T_195, _T_200) node _T_202 = and(_T_190, _T_201) node _T_203 = or(UInt<1>(0h0), _T_202) node _T_204 = asUInt(reset) node _T_205 = eq(_T_204, UInt<1>(0h0)) when _T_205 : node _T_206 = eq(_T_203, UInt<1>(0h0)) when _T_206 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_203, UInt<1>(0h1), "") : assert_20 node _T_207 = asUInt(reset) node _T_208 = eq(_T_207, UInt<1>(0h0)) when _T_208 : node _T_209 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_209 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_210 = asUInt(reset) node _T_211 = eq(_T_210, UInt<1>(0h0)) when _T_211 : node _T_212 = eq(is_aligned, UInt<1>(0h0)) when _T_212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_213 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_214 = asUInt(reset) node _T_215 = eq(_T_214, UInt<1>(0h0)) when _T_215 : node _T_216 = eq(_T_213, UInt<1>(0h0)) when _T_216 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_213, UInt<1>(0h1), "") : assert_23 node _T_217 = eq(io.in.a.bits.mask, mask) node _T_218 = asUInt(reset) node _T_219 = eq(_T_218, UInt<1>(0h0)) when _T_219 : node _T_220 = eq(_T_217, UInt<1>(0h0)) when _T_220 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_217, UInt<1>(0h1), "") : assert_24 node _T_221 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_T_221, UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_221, UInt<1>(0h1), "") : assert_25 node _T_225 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_225 : node _T_226 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_227 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_228 = and(_T_226, _T_227) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0) node _T_229 = shr(io.in.a.bits.source, 4) node _T_230 = eq(_T_229, UInt<1>(0h0)) node _T_231 = leq(UInt<1>(0h0), uncommonBits_4) node _T_232 = and(_T_230, _T_231) node _T_233 = leq(uncommonBits_4, UInt<4>(0h9)) node _T_234 = and(_T_232, _T_233) node _T_235 = and(_T_228, _T_234) node _T_236 = or(UInt<1>(0h0), _T_235) node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_239 = and(_T_237, _T_238) node _T_240 = or(UInt<1>(0h0), _T_239) node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<29>(0h10000000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = or(_T_245, _T_250) node _T_252 = and(_T_240, _T_251) node _T_253 = or(UInt<1>(0h0), _T_252) node _T_254 = and(_T_236, _T_253) node _T_255 = asUInt(reset) node _T_256 = eq(_T_255, UInt<1>(0h0)) when _T_256 : node _T_257 = eq(_T_254, UInt<1>(0h0)) when _T_257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_254, UInt<1>(0h1), "") : assert_26 node _T_258 = asUInt(reset) node _T_259 = eq(_T_258, UInt<1>(0h0)) when _T_259 : node _T_260 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_260 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(is_aligned, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_264 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_265 = asUInt(reset) node _T_266 = eq(_T_265, UInt<1>(0h0)) when _T_266 : node _T_267 = eq(_T_264, UInt<1>(0h0)) when _T_267 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_264, UInt<1>(0h1), "") : assert_29 node _T_268 = eq(io.in.a.bits.mask, mask) node _T_269 = asUInt(reset) node _T_270 = eq(_T_269, UInt<1>(0h0)) when _T_270 : node _T_271 = eq(_T_268, UInt<1>(0h0)) when _T_271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_268, UInt<1>(0h1), "") : assert_30 node _T_272 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_272 : node _T_273 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_274 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_275 = and(_T_273, _T_274) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0) node _T_276 = shr(io.in.a.bits.source, 4) node _T_277 = eq(_T_276, UInt<1>(0h0)) node _T_278 = leq(UInt<1>(0h0), uncommonBits_5) node _T_279 = and(_T_277, _T_278) node _T_280 = leq(uncommonBits_5, UInt<4>(0h9)) node _T_281 = and(_T_279, _T_280) node _T_282 = and(_T_275, _T_281) node _T_283 = or(UInt<1>(0h0), _T_282) node _T_284 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_285 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_286 = and(_T_284, _T_285) node _T_287 = or(UInt<1>(0h0), _T_286) node _T_288 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<17>(0h10000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<29>(0h10000000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = or(_T_292, _T_297) node _T_299 = and(_T_287, _T_298) node _T_300 = or(UInt<1>(0h0), _T_299) node _T_301 = and(_T_283, _T_300) node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(_T_301, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_301, UInt<1>(0h1), "") : assert_31 node _T_305 = asUInt(reset) node _T_306 = eq(_T_305, UInt<1>(0h0)) when _T_306 : node _T_307 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_307 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_308 = asUInt(reset) node _T_309 = eq(_T_308, UInt<1>(0h0)) when _T_309 : node _T_310 = eq(is_aligned, UInt<1>(0h0)) when _T_310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_311 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_312 = asUInt(reset) node _T_313 = eq(_T_312, UInt<1>(0h0)) when _T_313 : node _T_314 = eq(_T_311, UInt<1>(0h0)) when _T_314 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_311, UInt<1>(0h1), "") : assert_34 node _T_315 = not(mask) node _T_316 = and(io.in.a.bits.mask, _T_315) node _T_317 = eq(_T_316, UInt<1>(0h0)) node _T_318 = asUInt(reset) node _T_319 = eq(_T_318, UInt<1>(0h0)) when _T_319 : node _T_320 = eq(_T_317, UInt<1>(0h0)) when _T_320 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_317, UInt<1>(0h1), "") : assert_35 node _T_321 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_321 : node _T_322 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_323 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_324 = and(_T_322, _T_323) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0) node _T_325 = shr(io.in.a.bits.source, 4) node _T_326 = eq(_T_325, UInt<1>(0h0)) node _T_327 = leq(UInt<1>(0h0), uncommonBits_6) node _T_328 = and(_T_326, _T_327) node _T_329 = leq(uncommonBits_6, UInt<4>(0h9)) node _T_330 = and(_T_328, _T_329) node _T_331 = and(_T_324, _T_330) node _T_332 = or(UInt<1>(0h0), _T_331) node _T_333 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_334 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_335 = cvt(_T_334) node _T_336 = and(_T_335, asSInt(UInt<17>(0h10000))) node _T_337 = asSInt(_T_336) node _T_338 = eq(_T_337, asSInt(UInt<1>(0h0))) node _T_339 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_340 = cvt(_T_339) node _T_341 = and(_T_340, asSInt(UInt<29>(0h10000000))) node _T_342 = asSInt(_T_341) node _T_343 = eq(_T_342, asSInt(UInt<1>(0h0))) node _T_344 = or(_T_338, _T_343) node _T_345 = and(_T_333, _T_344) node _T_346 = or(UInt<1>(0h0), _T_345) node _T_347 = and(_T_332, _T_346) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_347, UInt<1>(0h1), "") : assert_36 node _T_351 = asUInt(reset) node _T_352 = eq(_T_351, UInt<1>(0h0)) when _T_352 : node _T_353 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_353 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_354 = asUInt(reset) node _T_355 = eq(_T_354, UInt<1>(0h0)) when _T_355 : node _T_356 = eq(is_aligned, UInt<1>(0h0)) when _T_356 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_357 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_358 = asUInt(reset) node _T_359 = eq(_T_358, UInt<1>(0h0)) when _T_359 : node _T_360 = eq(_T_357, UInt<1>(0h0)) when _T_360 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_357, UInt<1>(0h1), "") : assert_39 node _T_361 = eq(io.in.a.bits.mask, mask) node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(_T_361, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_361, UInt<1>(0h1), "") : assert_40 node _T_365 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_365 : node _T_366 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_367 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_368 = and(_T_366, _T_367) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0) node _T_369 = shr(io.in.a.bits.source, 4) node _T_370 = eq(_T_369, UInt<1>(0h0)) node _T_371 = leq(UInt<1>(0h0), uncommonBits_7) node _T_372 = and(_T_370, _T_371) node _T_373 = leq(uncommonBits_7, UInt<4>(0h9)) node _T_374 = and(_T_372, _T_373) node _T_375 = and(_T_368, _T_374) node _T_376 = or(UInt<1>(0h0), _T_375) node _T_377 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_378 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_379 = cvt(_T_378) node _T_380 = and(_T_379, asSInt(UInt<17>(0h10000))) node _T_381 = asSInt(_T_380) node _T_382 = eq(_T_381, asSInt(UInt<1>(0h0))) node _T_383 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_384 = cvt(_T_383) node _T_385 = and(_T_384, asSInt(UInt<29>(0h10000000))) node _T_386 = asSInt(_T_385) node _T_387 = eq(_T_386, asSInt(UInt<1>(0h0))) node _T_388 = or(_T_382, _T_387) node _T_389 = and(_T_377, _T_388) node _T_390 = or(UInt<1>(0h0), _T_389) node _T_391 = and(_T_376, _T_390) node _T_392 = asUInt(reset) node _T_393 = eq(_T_392, UInt<1>(0h0)) when _T_393 : node _T_394 = eq(_T_391, UInt<1>(0h0)) when _T_394 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_391, UInt<1>(0h1), "") : assert_41 node _T_395 = asUInt(reset) node _T_396 = eq(_T_395, UInt<1>(0h0)) when _T_396 : node _T_397 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_397 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(is_aligned, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_401 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_T_401, UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_401, UInt<1>(0h1), "") : assert_44 node _T_405 = eq(io.in.a.bits.mask, mask) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_405, UInt<1>(0h1), "") : assert_45 node _T_409 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_409 : node _T_410 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_411 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_412 = and(_T_410, _T_411) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0) node _T_413 = shr(io.in.a.bits.source, 4) node _T_414 = eq(_T_413, UInt<1>(0h0)) node _T_415 = leq(UInt<1>(0h0), uncommonBits_8) node _T_416 = and(_T_414, _T_415) node _T_417 = leq(uncommonBits_8, UInt<4>(0h9)) node _T_418 = and(_T_416, _T_417) node _T_419 = and(_T_412, _T_418) node _T_420 = or(UInt<1>(0h0), _T_419) node _T_421 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_422 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_423 = cvt(_T_422) node _T_424 = and(_T_423, asSInt(UInt<17>(0h10000))) node _T_425 = asSInt(_T_424) node _T_426 = eq(_T_425, asSInt(UInt<1>(0h0))) node _T_427 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_428 = cvt(_T_427) node _T_429 = and(_T_428, asSInt(UInt<29>(0h10000000))) node _T_430 = asSInt(_T_429) node _T_431 = eq(_T_430, asSInt(UInt<1>(0h0))) node _T_432 = or(_T_426, _T_431) node _T_433 = and(_T_421, _T_432) node _T_434 = or(UInt<1>(0h0), _T_433) node _T_435 = and(_T_420, _T_434) node _T_436 = asUInt(reset) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(_T_435, UInt<1>(0h0)) when _T_438 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_435, UInt<1>(0h1), "") : assert_46 node _T_439 = asUInt(reset) node _T_440 = eq(_T_439, UInt<1>(0h0)) when _T_440 : node _T_441 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_441 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_442 = asUInt(reset) node _T_443 = eq(_T_442, UInt<1>(0h0)) when _T_443 : node _T_444 = eq(is_aligned, UInt<1>(0h0)) when _T_444 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_445 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_445, UInt<1>(0h1), "") : assert_49 node _T_449 = eq(io.in.a.bits.mask, mask) node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_T_449, UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_449, UInt<1>(0h1), "") : assert_50 node _T_453 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_454 = asUInt(reset) node _T_455 = eq(_T_454, UInt<1>(0h0)) when _T_455 : node _T_456 = eq(_T_453, UInt<1>(0h0)) when _T_456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_453, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_457 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_T_457, UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_457, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 4) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<4>(0h9)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_461 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_461 : node _T_462 = asUInt(reset) node _T_463 = eq(_T_462, UInt<1>(0h0)) when _T_463 : node _T_464 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_464 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_465 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_466 = asUInt(reset) node _T_467 = eq(_T_466, UInt<1>(0h0)) when _T_467 : node _T_468 = eq(_T_465, UInt<1>(0h0)) when _T_468 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_465, UInt<1>(0h1), "") : assert_54 node _T_469 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_469, UInt<1>(0h1), "") : assert_55 node _T_473 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_474 = asUInt(reset) node _T_475 = eq(_T_474, UInt<1>(0h0)) when _T_475 : node _T_476 = eq(_T_473, UInt<1>(0h0)) when _T_476 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_473, UInt<1>(0h1), "") : assert_56 node _T_477 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_478 = asUInt(reset) node _T_479 = eq(_T_478, UInt<1>(0h0)) when _T_479 : node _T_480 = eq(_T_477, UInt<1>(0h0)) when _T_480 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_477, UInt<1>(0h1), "") : assert_57 node _T_481 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_481 : node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_485 = asUInt(reset) node _T_486 = eq(_T_485, UInt<1>(0h0)) when _T_486 : node _T_487 = eq(sink_ok, UInt<1>(0h0)) when _T_487 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_488 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_488, UInt<1>(0h1), "") : assert_60 node _T_492 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_493 = asUInt(reset) node _T_494 = eq(_T_493, UInt<1>(0h0)) when _T_494 : node _T_495 = eq(_T_492, UInt<1>(0h0)) when _T_495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_492, UInt<1>(0h1), "") : assert_61 node _T_496 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_497 = asUInt(reset) node _T_498 = eq(_T_497, UInt<1>(0h0)) when _T_498 : node _T_499 = eq(_T_496, UInt<1>(0h0)) when _T_499 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_496, UInt<1>(0h1), "") : assert_62 node _T_500 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_501 = asUInt(reset) node _T_502 = eq(_T_501, UInt<1>(0h0)) when _T_502 : node _T_503 = eq(_T_500, UInt<1>(0h0)) when _T_503 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_500, UInt<1>(0h1), "") : assert_63 node _T_504 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_505 = or(UInt<1>(0h1), _T_504) node _T_506 = asUInt(reset) node _T_507 = eq(_T_506, UInt<1>(0h0)) when _T_507 : node _T_508 = eq(_T_505, UInt<1>(0h0)) when _T_508 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_505, UInt<1>(0h1), "") : assert_64 node _T_509 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_509 : node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_513 = asUInt(reset) node _T_514 = eq(_T_513, UInt<1>(0h0)) when _T_514 : node _T_515 = eq(sink_ok, UInt<1>(0h0)) when _T_515 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_516 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_517 = asUInt(reset) node _T_518 = eq(_T_517, UInt<1>(0h0)) when _T_518 : node _T_519 = eq(_T_516, UInt<1>(0h0)) when _T_519 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_516, UInt<1>(0h1), "") : assert_67 node _T_520 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_521 = asUInt(reset) node _T_522 = eq(_T_521, UInt<1>(0h0)) when _T_522 : node _T_523 = eq(_T_520, UInt<1>(0h0)) when _T_523 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_520, UInt<1>(0h1), "") : assert_68 node _T_524 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_525 = asUInt(reset) node _T_526 = eq(_T_525, UInt<1>(0h0)) when _T_526 : node _T_527 = eq(_T_524, UInt<1>(0h0)) when _T_527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_524, UInt<1>(0h1), "") : assert_69 node _T_528 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_529 = or(_T_528, io.in.d.bits.corrupt) node _T_530 = asUInt(reset) node _T_531 = eq(_T_530, UInt<1>(0h0)) when _T_531 : node _T_532 = eq(_T_529, UInt<1>(0h0)) when _T_532 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_529, UInt<1>(0h1), "") : assert_70 node _T_533 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_534 = or(UInt<1>(0h1), _T_533) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_534, UInt<1>(0h1), "") : assert_71 node _T_538 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_538 : node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_542 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_543 = asUInt(reset) node _T_544 = eq(_T_543, UInt<1>(0h0)) when _T_544 : node _T_545 = eq(_T_542, UInt<1>(0h0)) when _T_545 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_542, UInt<1>(0h1), "") : assert_73 node _T_546 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_547 = asUInt(reset) node _T_548 = eq(_T_547, UInt<1>(0h0)) when _T_548 : node _T_549 = eq(_T_546, UInt<1>(0h0)) when _T_549 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_546, UInt<1>(0h1), "") : assert_74 node _T_550 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_551 = or(UInt<1>(0h1), _T_550) node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_T_551, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_551, UInt<1>(0h1), "") : assert_75 node _T_555 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_555 : node _T_556 = asUInt(reset) node _T_557 = eq(_T_556, UInt<1>(0h0)) when _T_557 : node _T_558 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_558 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_559 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_560 = asUInt(reset) node _T_561 = eq(_T_560, UInt<1>(0h0)) when _T_561 : node _T_562 = eq(_T_559, UInt<1>(0h0)) when _T_562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_559, UInt<1>(0h1), "") : assert_77 node _T_563 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_564 = or(_T_563, io.in.d.bits.corrupt) node _T_565 = asUInt(reset) node _T_566 = eq(_T_565, UInt<1>(0h0)) when _T_566 : node _T_567 = eq(_T_564, UInt<1>(0h0)) when _T_567 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_564, UInt<1>(0h1), "") : assert_78 node _T_568 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_569 = or(UInt<1>(0h1), _T_568) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_569, UInt<1>(0h1), "") : assert_79 node _T_573 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_573 : node _T_574 = asUInt(reset) node _T_575 = eq(_T_574, UInt<1>(0h0)) when _T_575 : node _T_576 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_577 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_578 = asUInt(reset) node _T_579 = eq(_T_578, UInt<1>(0h0)) when _T_579 : node _T_580 = eq(_T_577, UInt<1>(0h0)) when _T_580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_577, UInt<1>(0h1), "") : assert_81 node _T_581 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_582 = asUInt(reset) node _T_583 = eq(_T_582, UInt<1>(0h0)) when _T_583 : node _T_584 = eq(_T_581, UInt<1>(0h0)) when _T_584 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_581, UInt<1>(0h1), "") : assert_82 node _T_585 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_586 = or(UInt<1>(0h1), _T_585) node _T_587 = asUInt(reset) node _T_588 = eq(_T_587, UInt<1>(0h0)) when _T_588 : node _T_589 = eq(_T_586, UInt<1>(0h0)) when _T_589 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_586, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<4>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_590 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_591 = asUInt(reset) node _T_592 = eq(_T_591, UInt<1>(0h0)) when _T_592 : node _T_593 = eq(_T_590, UInt<1>(0h0)) when _T_593 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_590, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<4>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_594 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_595 = asUInt(reset) node _T_596 = eq(_T_595, UInt<1>(0h0)) when _T_596 : node _T_597 = eq(_T_594, UInt<1>(0h0)) when _T_597 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_594, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_598 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_599 = asUInt(reset) node _T_600 = eq(_T_599, UInt<1>(0h0)) when _T_600 : node _T_601 = eq(_T_598, UInt<1>(0h0)) when _T_601 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_598, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_602 = eq(a_first, UInt<1>(0h0)) node _T_603 = and(io.in.a.valid, _T_602) when _T_603 : node _T_604 = eq(io.in.a.bits.opcode, opcode) node _T_605 = asUInt(reset) node _T_606 = eq(_T_605, UInt<1>(0h0)) when _T_606 : node _T_607 = eq(_T_604, UInt<1>(0h0)) when _T_607 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_604, UInt<1>(0h1), "") : assert_87 node _T_608 = eq(io.in.a.bits.param, param) node _T_609 = asUInt(reset) node _T_610 = eq(_T_609, UInt<1>(0h0)) when _T_610 : node _T_611 = eq(_T_608, UInt<1>(0h0)) when _T_611 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_608, UInt<1>(0h1), "") : assert_88 node _T_612 = eq(io.in.a.bits.size, size) node _T_613 = asUInt(reset) node _T_614 = eq(_T_613, UInt<1>(0h0)) when _T_614 : node _T_615 = eq(_T_612, UInt<1>(0h0)) when _T_615 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_612, UInt<1>(0h1), "") : assert_89 node _T_616 = eq(io.in.a.bits.source, source) node _T_617 = asUInt(reset) node _T_618 = eq(_T_617, UInt<1>(0h0)) when _T_618 : node _T_619 = eq(_T_616, UInt<1>(0h0)) when _T_619 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_616, UInt<1>(0h1), "") : assert_90 node _T_620 = eq(io.in.a.bits.address, address) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_620, UInt<1>(0h1), "") : assert_91 node _T_624 = and(io.in.a.ready, io.in.a.valid) node _T_625 = and(_T_624, a_first) when _T_625 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_626 = eq(d_first, UInt<1>(0h0)) node _T_627 = and(io.in.d.valid, _T_626) when _T_627 : node _T_628 = eq(io.in.d.bits.opcode, opcode_1) node _T_629 = asUInt(reset) node _T_630 = eq(_T_629, UInt<1>(0h0)) when _T_630 : node _T_631 = eq(_T_628, UInt<1>(0h0)) when _T_631 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_628, UInt<1>(0h1), "") : assert_92 node _T_632 = eq(io.in.d.bits.param, param_1) node _T_633 = asUInt(reset) node _T_634 = eq(_T_633, UInt<1>(0h0)) when _T_634 : node _T_635 = eq(_T_632, UInt<1>(0h0)) when _T_635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_632, UInt<1>(0h1), "") : assert_93 node _T_636 = eq(io.in.d.bits.size, size_1) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_636, UInt<1>(0h1), "") : assert_94 node _T_640 = eq(io.in.d.bits.source, source_1) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_640, UInt<1>(0h1), "") : assert_95 node _T_644 = eq(io.in.d.bits.sink, sink) node _T_645 = asUInt(reset) node _T_646 = eq(_T_645, UInt<1>(0h0)) when _T_646 : node _T_647 = eq(_T_644, UInt<1>(0h0)) when _T_647 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_644, UInt<1>(0h1), "") : assert_96 node _T_648 = eq(io.in.d.bits.denied, denied) node _T_649 = asUInt(reset) node _T_650 = eq(_T_649, UInt<1>(0h0)) when _T_650 : node _T_651 = eq(_T_648, UInt<1>(0h0)) when _T_651 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_648, UInt<1>(0h1), "") : assert_97 node _T_652 = and(io.in.d.ready, io.in.d.valid) node _T_653 = and(_T_652, d_first) when _T_653 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes : UInt<40>, clock, reset, UInt<40>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<10> connect a_set, UInt<10>(0h0) wire a_set_wo_ready : UInt<10> connect a_set_wo_ready, UInt<10>(0h0) wire a_opcodes_set : UInt<40> connect a_opcodes_set, UInt<40>(0h0) wire a_sizes_set : UInt<40> connect a_sizes_set, UInt<40>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_654 = and(io.in.a.valid, a_first_1) node _T_655 = and(_T_654, UInt<1>(0h1)) when _T_655 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_656 = and(io.in.a.ready, io.in.a.valid) node _T_657 = and(_T_656, a_first_1) node _T_658 = and(_T_657, UInt<1>(0h1)) when _T_658 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_659 = dshr(inflight, io.in.a.bits.source) node _T_660 = bits(_T_659, 0, 0) node _T_661 = eq(_T_660, UInt<1>(0h0)) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_661, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<10> connect d_clr, UInt<10>(0h0) wire d_clr_wo_ready : UInt<10> connect d_clr_wo_ready, UInt<10>(0h0) wire d_opcodes_clr : UInt<40> connect d_opcodes_clr, UInt<40>(0h0) wire d_sizes_clr : UInt<40> connect d_sizes_clr, UInt<40>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_665 = and(io.in.d.valid, d_first_1) node _T_666 = and(_T_665, UInt<1>(0h1)) node _T_667 = eq(d_release_ack, UInt<1>(0h0)) node _T_668 = and(_T_666, _T_667) when _T_668 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_669 = and(io.in.d.ready, io.in.d.valid) node _T_670 = and(_T_669, d_first_1) node _T_671 = and(_T_670, UInt<1>(0h1)) node _T_672 = eq(d_release_ack, UInt<1>(0h0)) node _T_673 = and(_T_671, _T_672) when _T_673 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_674 = and(io.in.d.valid, d_first_1) node _T_675 = and(_T_674, UInt<1>(0h1)) node _T_676 = eq(d_release_ack, UInt<1>(0h0)) node _T_677 = and(_T_675, _T_676) when _T_677 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_678 = dshr(inflight, io.in.d.bits.source) node _T_679 = bits(_T_678, 0, 0) node _T_680 = or(_T_679, same_cycle_resp) node _T_681 = asUInt(reset) node _T_682 = eq(_T_681, UInt<1>(0h0)) when _T_682 : node _T_683 = eq(_T_680, UInt<1>(0h0)) when _T_683 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_680, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_684 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_685 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_686 = or(_T_684, _T_685) node _T_687 = asUInt(reset) node _T_688 = eq(_T_687, UInt<1>(0h0)) when _T_688 : node _T_689 = eq(_T_686, UInt<1>(0h0)) when _T_689 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_686, UInt<1>(0h1), "") : assert_100 node _T_690 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_691 = asUInt(reset) node _T_692 = eq(_T_691, UInt<1>(0h0)) when _T_692 : node _T_693 = eq(_T_690, UInt<1>(0h0)) when _T_693 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_690, UInt<1>(0h1), "") : assert_101 else : node _T_694 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_695 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_696 = or(_T_694, _T_695) node _T_697 = asUInt(reset) node _T_698 = eq(_T_697, UInt<1>(0h0)) when _T_698 : node _T_699 = eq(_T_696, UInt<1>(0h0)) when _T_699 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_696, UInt<1>(0h1), "") : assert_102 node _T_700 = eq(io.in.d.bits.size, a_size_lookup) node _T_701 = asUInt(reset) node _T_702 = eq(_T_701, UInt<1>(0h0)) when _T_702 : node _T_703 = eq(_T_700, UInt<1>(0h0)) when _T_703 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_700, UInt<1>(0h1), "") : assert_103 node _T_704 = and(io.in.d.valid, d_first_1) node _T_705 = and(_T_704, a_first_1) node _T_706 = and(_T_705, io.in.a.valid) node _T_707 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_708 = and(_T_706, _T_707) node _T_709 = eq(d_release_ack, UInt<1>(0h0)) node _T_710 = and(_T_708, _T_709) when _T_710 : node _T_711 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_712 = or(_T_711, io.in.a.ready) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_712, UInt<1>(0h1), "") : assert_104 node _T_716 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_717 = orr(a_set_wo_ready) node _T_718 = eq(_T_717, UInt<1>(0h0)) node _T_719 = or(_T_716, _T_718) node _T_720 = asUInt(reset) node _T_721 = eq(_T_720, UInt<1>(0h0)) when _T_721 : node _T_722 = eq(_T_719, UInt<1>(0h0)) when _T_722 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_719, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_96 node _T_723 = orr(inflight) node _T_724 = eq(_T_723, UInt<1>(0h0)) node _T_725 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_726 = or(_T_724, _T_725) node _T_727 = lt(watchdog, plusarg_reader.out) node _T_728 = or(_T_726, _T_727) node _T_729 = asUInt(reset) node _T_730 = eq(_T_729, UInt<1>(0h0)) when _T_730 : node _T_731 = eq(_T_728, UInt<1>(0h0)) when _T_731 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_728, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_732 = and(io.in.a.ready, io.in.a.valid) node _T_733 = and(io.in.d.ready, io.in.d.valid) node _T_734 = or(_T_732, _T_733) when _T_734 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes_1 : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes_1 : UInt<40>, clock, reset, UInt<40>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<4>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<4>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<10> connect c_set, UInt<10>(0h0) wire c_set_wo_ready : UInt<10> connect c_set_wo_ready, UInt<10>(0h0) wire c_opcodes_set : UInt<40> connect c_opcodes_set, UInt<40>(0h0) wire c_sizes_set : UInt<40> connect c_sizes_set, UInt<40>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<4>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_735 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<4>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_736 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_737 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_738 = and(_T_736, _T_737) node _T_739 = and(_T_735, _T_738) when _T_739 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<4>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_740 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_741 = and(_T_740, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<4>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_742 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_743 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_744 = and(_T_742, _T_743) node _T_745 = and(_T_741, _T_744) when _T_745 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<4>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<4>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_746 = dshr(inflight_1, _WIRE_15.bits.source) node _T_747 = bits(_T_746, 0, 0) node _T_748 = eq(_T_747, UInt<1>(0h0)) node _T_749 = asUInt(reset) node _T_750 = eq(_T_749, UInt<1>(0h0)) when _T_750 : node _T_751 = eq(_T_748, UInt<1>(0h0)) when _T_751 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_748, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<10> connect d_clr_1, UInt<10>(0h0) wire d_clr_wo_ready_1 : UInt<10> connect d_clr_wo_ready_1, UInt<10>(0h0) wire d_opcodes_clr_1 : UInt<40> connect d_opcodes_clr_1, UInt<40>(0h0) wire d_sizes_clr_1 : UInt<40> connect d_sizes_clr_1, UInt<40>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_752 = and(io.in.d.valid, d_first_2) node _T_753 = and(_T_752, UInt<1>(0h1)) node _T_754 = and(_T_753, d_release_ack_1) when _T_754 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_755 = and(io.in.d.ready, io.in.d.valid) node _T_756 = and(_T_755, d_first_2) node _T_757 = and(_T_756, UInt<1>(0h1)) node _T_758 = and(_T_757, d_release_ack_1) when _T_758 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_759 = and(io.in.d.valid, d_first_2) node _T_760 = and(_T_759, UInt<1>(0h1)) node _T_761 = and(_T_760, d_release_ack_1) when _T_761 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_762 = dshr(inflight_1, io.in.d.bits.source) node _T_763 = bits(_T_762, 0, 0) node _T_764 = or(_T_763, same_cycle_resp_1) node _T_765 = asUInt(reset) node _T_766 = eq(_T_765, UInt<1>(0h0)) when _T_766 : node _T_767 = eq(_T_764, UInt<1>(0h0)) when _T_767 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_764, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<4>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_768 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_769 = asUInt(reset) node _T_770 = eq(_T_769, UInt<1>(0h0)) when _T_770 : node _T_771 = eq(_T_768, UInt<1>(0h0)) when _T_771 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_768, UInt<1>(0h1), "") : assert_109 else : node _T_772 = eq(io.in.d.bits.size, c_size_lookup) node _T_773 = asUInt(reset) node _T_774 = eq(_T_773, UInt<1>(0h0)) when _T_774 : node _T_775 = eq(_T_772, UInt<1>(0h0)) when _T_775 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_772, UInt<1>(0h1), "") : assert_110 node _T_776 = and(io.in.d.valid, d_first_2) node _T_777 = and(_T_776, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<4>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_778 = and(_T_777, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<4>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_779 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_780 = and(_T_778, _T_779) node _T_781 = and(_T_780, d_release_ack_1) node _T_782 = eq(c_probe_ack, UInt<1>(0h0)) node _T_783 = and(_T_781, _T_782) when _T_783 : node _T_784 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<4>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_785 = or(_T_784, _WIRE_23.ready) node _T_786 = asUInt(reset) node _T_787 = eq(_T_786, UInt<1>(0h0)) when _T_787 : node _T_788 = eq(_T_785, UInt<1>(0h0)) when _T_788 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_785, UInt<1>(0h1), "") : assert_111 node _T_789 = orr(c_set_wo_ready) when _T_789 : node _T_790 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_791 = asUInt(reset) node _T_792 = eq(_T_791, UInt<1>(0h0)) when _T_792 : node _T_793 = eq(_T_790, UInt<1>(0h0)) when _T_793 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_790, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_97 node _T_794 = orr(inflight_1) node _T_795 = eq(_T_794, UInt<1>(0h0)) node _T_796 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_797 = or(_T_795, _T_796) node _T_798 = lt(watchdog_1, plusarg_reader_1.out) node _T_799 = or(_T_797, _T_798) node _T_800 = asUInt(reset) node _T_801 = eq(_T_800, UInt<1>(0h0)) when _T_801 : node _T_802 = eq(_T_799, UInt<1>(0h0)) when _T_802 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_799, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<4>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_803 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_804 = and(io.in.d.ready, io.in.d.valid) node _T_805 = or(_T_803, _T_804) when _T_805 : connect watchdog_1, UInt<1>(0h0) extmodule plusarg_reader_98 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_99 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32
module TLMonitor_35( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [9:0] inflight; // @[Monitor.scala:614:27] reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [39:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire [15:0] _GEN_0 = {12'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [15:0] _GEN_3 = {12'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [9:0] inflight_1; // @[Monitor.scala:726:35] reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module IDPool_2 : input clock : Clock input reset : Reset output io : { flip free : { valid : UInt<1>, bits : UInt<3>}, alloc : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<3>}} regreset bitmap : UInt<8>, clock, reset, UInt<8>(0hff) regreset select : UInt<3>, clock, reset, UInt<3>(0h0) regreset valid : UInt<1>, clock, reset, UInt<1>(0h1) connect io.alloc.valid, valid connect io.alloc.bits, select node taken_shiftAmount = bits(io.alloc.bits, 2, 0) node _taken_T = dshl(UInt<1>(0h1), taken_shiftAmount) node _taken_T_1 = bits(_taken_T, 7, 0) node taken = mux(io.alloc.ready, _taken_T_1, UInt<1>(0h0)) node allocated_shiftAmount = bits(io.free.bits, 2, 0) node _allocated_T = dshl(UInt<1>(0h1), allocated_shiftAmount) node _allocated_T_1 = bits(_allocated_T, 7, 0) node allocated = mux(io.free.valid, _allocated_T_1, UInt<1>(0h0)) node _bitmap1_T = not(taken) node _bitmap1_T_1 = and(bitmap, _bitmap1_T) node bitmap1 = or(_bitmap1_T_1, allocated) node _select1_T = bits(bitmap1, 0, 0) node _select1_T_1 = bits(bitmap1, 1, 1) node _select1_T_2 = bits(bitmap1, 2, 2) node _select1_T_3 = bits(bitmap1, 3, 3) node _select1_T_4 = bits(bitmap1, 4, 4) node _select1_T_5 = bits(bitmap1, 5, 5) node _select1_T_6 = bits(bitmap1, 6, 6) node _select1_T_7 = bits(bitmap1, 7, 7) node _select1_T_8 = mux(_select1_T_6, UInt<3>(0h6), UInt<3>(0h7)) node _select1_T_9 = mux(_select1_T_5, UInt<3>(0h5), _select1_T_8) node _select1_T_10 = mux(_select1_T_4, UInt<3>(0h4), _select1_T_9) node _select1_T_11 = mux(_select1_T_3, UInt<2>(0h3), _select1_T_10) node _select1_T_12 = mux(_select1_T_2, UInt<2>(0h2), _select1_T_11) node _select1_T_13 = mux(_select1_T_1, UInt<1>(0h1), _select1_T_12) node select1 = mux(_select1_T, UInt<1>(0h0), _select1_T_13) node _valid1_T = orr(bitmap) node _valid1_T_1 = bits(bitmap, 0, 0) node _valid1_T_2 = bits(bitmap, 1, 1) node _valid1_T_3 = bits(bitmap, 2, 2) node _valid1_T_4 = bits(bitmap, 3, 3) node _valid1_T_5 = bits(bitmap, 4, 4) node _valid1_T_6 = bits(bitmap, 5, 5) node _valid1_T_7 = bits(bitmap, 6, 6) node _valid1_T_8 = bits(bitmap, 7, 7) node _valid1_T_9 = add(_valid1_T_1, _valid1_T_2) node _valid1_T_10 = bits(_valid1_T_9, 1, 0) node _valid1_T_11 = add(_valid1_T_3, _valid1_T_4) node _valid1_T_12 = bits(_valid1_T_11, 1, 0) node _valid1_T_13 = add(_valid1_T_10, _valid1_T_12) node _valid1_T_14 = bits(_valid1_T_13, 2, 0) node _valid1_T_15 = add(_valid1_T_5, _valid1_T_6) node _valid1_T_16 = bits(_valid1_T_15, 1, 0) node _valid1_T_17 = add(_valid1_T_7, _valid1_T_8) node _valid1_T_18 = bits(_valid1_T_17, 1, 0) node _valid1_T_19 = add(_valid1_T_16, _valid1_T_18) node _valid1_T_20 = bits(_valid1_T_19, 2, 0) node _valid1_T_21 = add(_valid1_T_14, _valid1_T_20) node _valid1_T_22 = bits(_valid1_T_21, 3, 0) node _valid1_T_23 = eq(_valid1_T_22, UInt<1>(0h1)) node _valid1_T_24 = and(_valid1_T_23, io.alloc.ready) node _valid1_T_25 = eq(_valid1_T_24, UInt<1>(0h0)) node _valid1_T_26 = and(_valid1_T, _valid1_T_25) node valid1 = or(_valid1_T_26, io.free.valid) node _T = or(io.alloc.ready, io.free.valid) when _T : connect bitmap, bitmap1 connect valid, valid1 node _T_1 = eq(io.alloc.valid, UInt<1>(0h0)) node _T_2 = and(_T_1, io.free.valid) node _T_3 = or(io.alloc.ready, _T_2) when _T_3 : connect select, select1 node _T_4 = eq(io.free.valid, UInt<1>(0h0)) node _T_5 = not(taken) node _T_6 = and(bitmap, _T_5) node _T_7 = dshr(_T_6, io.free.bits) node _T_8 = bits(_T_7, 0, 0) node _T_9 = eq(_T_8, UInt<1>(0h0)) node _T_10 = or(_T_4, _T_9) node _T_11 = asUInt(reset) node _T_12 = eq(_T_11, UInt<1>(0h0)) when _T_12 : node _T_13 = eq(_T_10, UInt<1>(0h0)) when _T_13 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IDPool.scala:44 assert (!io.free.valid || !(bitmap & ~taken)(io.free.bits))\n") : printf assert(clock, _T_10, UInt<1>(0h1), "") : assert node _T_14 = orr(bitmap) node _T_15 = eq(valid, _T_14) node _T_16 = asUInt(reset) node _T_17 = eq(_T_16, UInt<1>(0h0)) when _T_17 : node _T_18 = eq(_T_15, UInt<1>(0h0)) when _T_18 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IDPool.scala:48 assert (valid === bitmap.orR)\n") : printf_1 assert(clock, _T_15, UInt<1>(0h1), "") : assert_1 node _T_19 = eq(io.alloc.valid, UInt<1>(0h0)) node _T_20 = and(_T_19, io.free.valid) node _T_21 = or(io.alloc.ready, _T_20) reg REG : UInt<1>, clock connect REG, _T_21 node _T_22 = and(io.alloc.valid, REG) when _T_22 : node _T_23 = bits(bitmap, 0, 0) node _T_24 = bits(bitmap, 1, 1) node _T_25 = bits(bitmap, 2, 2) node _T_26 = bits(bitmap, 3, 3) node _T_27 = bits(bitmap, 4, 4) node _T_28 = bits(bitmap, 5, 5) node _T_29 = bits(bitmap, 6, 6) node _T_30 = bits(bitmap, 7, 7) node _T_31 = mux(_T_29, UInt<3>(0h6), UInt<3>(0h7)) node _T_32 = mux(_T_28, UInt<3>(0h5), _T_31) node _T_33 = mux(_T_27, UInt<3>(0h4), _T_32) node _T_34 = mux(_T_26, UInt<2>(0h3), _T_33) node _T_35 = mux(_T_25, UInt<2>(0h2), _T_34) node _T_36 = mux(_T_24, UInt<1>(0h1), _T_35) node _T_37 = mux(_T_23, UInt<1>(0h0), _T_36) node _T_38 = eq(select, _T_37) node _T_39 = asUInt(reset) node _T_40 = eq(_T_39, UInt<1>(0h0)) when _T_40 : node _T_41 = eq(_T_38, UInt<1>(0h0)) when _T_41 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IDPool.scala:52 assert (select === PriorityEncoder(bitmap))\n") : printf_2 assert(clock, _T_38, UInt<1>(0h1), "") : assert_2
module IDPool_2( // @[IDPool.scala:8:7] input clock, // @[IDPool.scala:8:7] input reset, // @[IDPool.scala:8:7] input io_free_valid, // @[IDPool.scala:12:14] input [2:0] io_free_bits, // @[IDPool.scala:12:14] input io_alloc_ready, // @[IDPool.scala:12:14] output io_alloc_valid, // @[IDPool.scala:12:14] output [2:0] io_alloc_bits // @[IDPool.scala:12:14] ); wire [2:0] io_alloc_bits_0; // @[IDPool.scala:8:7] wire io_free_valid_0 = io_free_valid; // @[IDPool.scala:8:7] wire [2:0] io_free_bits_0 = io_free_bits; // @[IDPool.scala:8:7] wire io_alloc_ready_0 = io_alloc_ready; // @[IDPool.scala:8:7] wire [2:0] allocated_shiftAmount = io_free_bits_0; // @[OneHot.scala:64:49] wire [2:0] taken_shiftAmount = io_alloc_bits_0; // @[OneHot.scala:64:49] wire io_alloc_valid_0; // @[IDPool.scala:8:7] reg [7:0] bitmap; // @[IDPool.scala:18:23] reg [2:0] select; // @[IDPool.scala:19:23] assign io_alloc_bits_0 = select; // @[IDPool.scala:8:7, :19:23] reg valid; // @[IDPool.scala:20:23] assign io_alloc_valid_0 = valid; // @[IDPool.scala:8:7, :20:23] wire [7:0] _taken_T = 8'h1 << taken_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [7:0] _taken_T_1 = _taken_T; // @[OneHot.scala:65:{12,27}] wire [7:0] taken = io_alloc_ready_0 ? _taken_T_1 : 8'h0; // @[OneHot.scala:65:27] wire [7:0] _allocated_T = 8'h1 << allocated_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [7:0] _allocated_T_1 = _allocated_T; // @[OneHot.scala:65:{12,27}] wire [7:0] allocated = io_free_valid_0 ? _allocated_T_1 : 8'h0; // @[OneHot.scala:65:27] wire [7:0] _bitmap1_T = ~taken; // @[IDPool.scala:25:19, :27:27] wire [7:0] _bitmap1_T_1 = bitmap & _bitmap1_T; // @[IDPool.scala:18:23, :27:{25,27}] wire [7:0] bitmap1 = _bitmap1_T_1 | allocated; // @[IDPool.scala:26:22, :27:{25,35}] wire _select1_T = bitmap1[0]; // @[OneHot.scala:48:45] wire _select1_T_1 = bitmap1[1]; // @[OneHot.scala:48:45] wire _select1_T_2 = bitmap1[2]; // @[OneHot.scala:48:45] wire _select1_T_3 = bitmap1[3]; // @[OneHot.scala:48:45] wire _select1_T_4 = bitmap1[4]; // @[OneHot.scala:48:45] wire _select1_T_5 = bitmap1[5]; // @[OneHot.scala:48:45] wire _select1_T_6 = bitmap1[6]; // @[OneHot.scala:48:45] wire _select1_T_7 = bitmap1[7]; // @[OneHot.scala:48:45] wire [2:0] _select1_T_8 = {2'h3, ~_select1_T_6}; // @[OneHot.scala:48:45] wire [2:0] _select1_T_9 = _select1_T_5 ? 3'h5 : _select1_T_8; // @[OneHot.scala:48:45] wire [2:0] _select1_T_10 = _select1_T_4 ? 3'h4 : _select1_T_9; // @[OneHot.scala:48:45] wire [2:0] _select1_T_11 = _select1_T_3 ? 3'h3 : _select1_T_10; // @[OneHot.scala:48:45] wire [2:0] _select1_T_12 = _select1_T_2 ? 3'h2 : _select1_T_11; // @[OneHot.scala:48:45] wire [2:0] _select1_T_13 = _select1_T_1 ? 3'h1 : _select1_T_12; // @[OneHot.scala:48:45] wire [2:0] select1 = _select1_T ? 3'h0 : _select1_T_13; // @[OneHot.scala:48:45] wire _valid1_T = |bitmap; // @[IDPool.scala:18:23, :29:28] wire _valid1_T_1 = bitmap[0]; // @[IDPool.scala:18:23, :29:46] wire _valid1_T_2 = bitmap[1]; // @[IDPool.scala:18:23, :29:46] wire _valid1_T_3 = bitmap[2]; // @[IDPool.scala:18:23, :29:46] wire _valid1_T_4 = bitmap[3]; // @[IDPool.scala:18:23, :29:46] wire _valid1_T_5 = bitmap[4]; // @[IDPool.scala:18:23, :29:46] wire _valid1_T_6 = bitmap[5]; // @[IDPool.scala:18:23, :29:46] wire _valid1_T_7 = bitmap[6]; // @[IDPool.scala:18:23, :29:46] wire _valid1_T_8 = bitmap[7]; // @[IDPool.scala:18:23, :29:46] wire [1:0] _valid1_T_9 = {1'h0, _valid1_T_1} + {1'h0, _valid1_T_2}; // @[IDPool.scala:29:46] wire [1:0] _valid1_T_10 = _valid1_T_9; // @[IDPool.scala:29:46] wire [1:0] _valid1_T_11 = {1'h0, _valid1_T_3} + {1'h0, _valid1_T_4}; // @[IDPool.scala:29:46] wire [1:0] _valid1_T_12 = _valid1_T_11; // @[IDPool.scala:29:46] wire [2:0] _valid1_T_13 = {1'h0, _valid1_T_10} + {1'h0, _valid1_T_12}; // @[IDPool.scala:29:46] wire [2:0] _valid1_T_14 = _valid1_T_13; // @[IDPool.scala:29:46] wire [1:0] _valid1_T_15 = {1'h0, _valid1_T_5} + {1'h0, _valid1_T_6}; // @[IDPool.scala:29:46] wire [1:0] _valid1_T_16 = _valid1_T_15; // @[IDPool.scala:29:46] wire [1:0] _valid1_T_17 = {1'h0, _valid1_T_7} + {1'h0, _valid1_T_8}; // @[IDPool.scala:29:46] wire [1:0] _valid1_T_18 = _valid1_T_17; // @[IDPool.scala:29:46] wire [2:0] _valid1_T_19 = {1'h0, _valid1_T_16} + {1'h0, _valid1_T_18}; // @[IDPool.scala:29:46] wire [2:0] _valid1_T_20 = _valid1_T_19; // @[IDPool.scala:29:46] wire [3:0] _valid1_T_21 = {1'h0, _valid1_T_14} + {1'h0, _valid1_T_20}; // @[IDPool.scala:29:46] wire [3:0] _valid1_T_22 = _valid1_T_21; // @[IDPool.scala:29:46] wire _valid1_T_23 = _valid1_T_22 == 4'h1; // @[IDPool.scala:29:{46,55}] wire _valid1_T_24 = _valid1_T_23 & io_alloc_ready_0; // @[IDPool.scala:8:7, :29:{55,64}] wire _valid1_T_25 = ~_valid1_T_24; // @[IDPool.scala:29:{35,64}] wire _valid1_T_26 = _valid1_T & _valid1_T_25; // @[IDPool.scala:29:{28,32,35}] wire valid1 = _valid1_T_26 | io_free_valid_0; // @[IDPool.scala:8:7, :29:32, :30:17] reg REG; // @[IDPool.scala:51:36]
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_104 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3
module MacUnit_104( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule